`define FPGA
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  timescale.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  Defines of the Core                                         ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None                                                        ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
// Timescale define

`timescale 1ns/10ps
/*
 * Memory Harness with Wishbone Slave interface
 *
 * (C) Copyleft 2007 Simply RISC LLP
 * AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
 *
 * LICENSE:
 * This is a Free Hardware Design; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 * The above named program is distributed in the hope that it will
 * be useful, but WITHOUT ANY WARRANTY; without even the implied
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * DESCRIPTION:
 * Filename is a parameter, and the corresponding file content
 * must follow the rules stated in Verilog standard for the
 * $readmemh() system task.
 * For instance if you don't change the default name you just
 * have to put a text file named "memory.hex" in your simulation
 * directory with the following content inside:
 *
 *   // We start from address zero by default:
 *   1234567812345678
 *   FEDCBA9876543210
 *   // Now we jump to doubleword number 10 (i.e. address 80):
 *   @ 10
 *   02468ACE13579BDF
 *
 * This memory harness was originally based upon a Wishbone Slave
 * model written by Rudolf Usselmann <rudi@asics.ws> but now I've
 * written it again entirely from scratch.
 */


module mem_harness(sys_clock_i, sys_reset_i, wbs_addr_i, wbs_data_i, wbs_data_o,
	wbs_cycle_i, wbs_strobe_i, wbs_sel_i, wbs_we_i, wbs_ack_o);
	// syn black_box
	parameter		addr_bits	= 24;
	parameter		addr_max	= ((1 << addr_bits) - 1);
	parameter		memfilename	= "memory.hex";
	parameter		initmem		= 0;
	parameter		loadmem		= 1;
	parameter		memdefaultcontent					= 64'b0;
	input			sys_clock_i;
	input			sys_reset_i;
	input			wbs_cycle_i;
	input			wbs_strobe_i;
	input	[63:0]		wbs_addr_i;
	input	[63:0]		wbs_data_i;
	input			wbs_we_i;
	input	[7:0]		wbs_sel_i;
	output			wbs_ack_o;
	output	[63:0]		wbs_data_o;

	reg			wbs_ack_o;
	reg	[63:0]		wbs_data_o;
	reg /*sparse*/
		[63:0]		mem[addr_max:0];
	wire	[63:0]		tmp_rd;
	wire	[63:0]		tmp_wd;
	integer			i;


/* synthesis translate_off */
  initial begin
    $display("INFO: MEMH %m: Memory Harness with Wishbone Slave interface starting...");
    $display("INFO: MEMH %m: %0d Address Bits / %0d Doublewords / %0d Bytes Total Memory", addr_bits, addr_max+1, (addr_max+1)*8);
    $readmemh(memfilename, mem);
    $display("INFO: MEMH %m: Memory initialization completed");
  end

 /* synthesis translate_on */


	always @(posedge sys_clock_i) begin
	  if ((wbs_cycle_i & wbs_strobe_i) & (!wbs_we_i)) begin
	    wbs_ack_o = 1;
	    wbs_data_o <= mem[wbs_addr_i[(addr_bits + 2):3]];
	  end
	  else if ((wbs_cycle_i & wbs_strobe_i) & wbs_we_i) begin
	    wbs_ack_o = 1;
	    if (wbs_sel_i[7]) mem[wbs_addr_i[(addr_bits + 2):3]][63:56] <= wbs_data_i[63:56];
	    if (wbs_sel_i[6]) mem[wbs_addr_i[(addr_bits + 2):3]][55:48] <= wbs_data_i[55:48];
	    if (wbs_sel_i[5]) mem[wbs_addr_i[(addr_bits + 2):3]][47:40] <= wbs_data_i[47:40];
	    if (wbs_sel_i[4]) mem[wbs_addr_i[(addr_bits + 2):3]][39:32] <= wbs_data_i[39:32];
	    if (wbs_sel_i[3]) mem[wbs_addr_i[(addr_bits + 2):3]][31:24] <= wbs_data_i[31:24];
	    if (wbs_sel_i[2]) mem[wbs_addr_i[(addr_bits + 2):3]][23:16] <= wbs_data_i[23:16];
	    if (wbs_sel_i[1]) mem[wbs_addr_i[(addr_bits + 2):3]][15:8] <= wbs_data_i[15:8];
	    if (wbs_sel_i[0]) mem[wbs_addr_i[(addr_bits + 2):3]][7:0] <= wbs_data_i[7:0];
	  end
	  else
	    begin
	      wbs_ack_o = 0;
	    end
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  raminfr.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  Inferrable Distributed RAM for FIFOs                        ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None                .                                       ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing so far.                                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////                                                              ////
////  Created:        2002/07/22                                  ////
////  Last Updated:   2002/07/22                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: raminfr.v,v $
// Revision 1.2  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//

//Following is the Verilog code for a dual-port RAM with asynchronous read.

module raminfr(clk, we, a, dpra, di, dpo);

	parameter		addr_width	= 4;
	parameter		data_width	= 8;
	parameter		depth		= 16;

	input			clk;
	input			we;
	input	[(addr_width - 1):0]
				a;
	input	[(addr_width - 1):0]
				dpra;
	input	[(data_width - 1):0]
				di;
	output	[(data_width - 1):0]
				dpo;

	reg	[(data_width - 1):0]
				ram[(depth - 1):0];

	assign dpo = ram[dpra];

	always @(posedge clk) begin
	  if (we) begin
	    ram[a] <= di;
	  end
	end
endmodule
/*
 * Bridge from SPARC Core to Wishbone Master
 *
 * (C) 2007 Simply RISC LLP
 * AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
 *
 * LICENSE:
 * This is a Free Hardware Design; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 * The above named program is distributed in the hope that it will
 * be useful, but WITHOUT ANY WARRANTY; without even the implied
 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * DESCRIPTION:
 * This block implements a bridge from one SPARC Core of the
 * OpenSPARC T1 to a master interface that makes use of the
 * Wishbone interconnect protocol.
 * For informations about Sun Microsystems' OpenSPARC T1
 * refer to the web site http://www.opensparc.net
 * For informations about OpenCores' Wishbone interconnect
 * please refer to the web site http://www.opencores.org
 */


module spc2wbm(sys_clock_i, sys_reset_i, sys_interrupt_source_i, spc_req_i, 
	spc_atom_i, spc_packetout_i, spc_grant_o, spc_ready_o, spc_packetin_o, 
	spc_stallreq_o, wbm_ack_i, wbm_data_i, wbm_cycle_o, wbm_strobe_o, 
	wbm_we_o, wbm_addr_o, wbm_data_o, wbm_sel_o);

	input			sys_clock_i;
	input			sys_reset_i;
	input	[5:0]		sys_interrupt_source_i;
	input	[4:0]		spc_req_i;
	input			spc_atom_i;
	input	[(130 - 1):0]	spc_packetout_i;
	input			wbm_ack_i;
	input	[(64 - 1):0]	wbm_data_i;
	output	[4:0]		spc_grant_o;
	output			spc_ready_o;
	output	[(146 - 1):0]	spc_packetin_o;
	output			spc_stallreq_o;
	output			wbm_cycle_o;
	output			wbm_strobe_o;
	output			wbm_we_o;
	output	[(64 - 1):0]	wbm_addr_o;
	output	[(64 - 1):0]	wbm_data_o;
	output	[((64 / 8) - 1):0]
				wbm_sel_o;

	wire	[4:0]		spc_req_w;
	wire			spc_atom_w;
	reg			spc_atom_r;
	wire	[(130 - 1):0]	spc_packetout_w;
	reg	[(130 - 1):0]	spc_packetout_i_save;
	reg	[(130 - 1):0]	spc_packetout_i_save2;
	reg	[4:0]		spc_grant_w;
	reg			spc_ready_o;
	reg	[(146 - 1):0]	spc_packetin_o;
	reg	[(146 - 1):0]	spc_packetin_w;
	reg			spc_stallreq_w;
	reg			wbm_cycle_o;
	reg			wbm_strobe_o;
	reg			wbm_we_o;
	reg	[(64 - 1):0]	wbm_addr_o;
	reg	[(64 - 1):0]	wbm_data_o;
	reg	[((64 / 8) - 1):0]
				wbm_sel_o;
	reg	[3:0]		state;
	reg	[4:0]		spc2wbm_region;
	reg			spc2wbm_atomic;
	reg			fifo_vld;
	reg			fifo_vld2;
	reg	[(130 - 1):0]	spc2wbm_packet;
	reg			wbm2spc_valid;
	reg	[(144 - 141):0]	wbm2spc_type;
	reg			wbm2spc_miss;
	reg	[(139 - 138):0]	wbm2spc_error;
	reg			wbm2spc_nc;
	reg	[(136 - 134):0]	wbm2spc_thread;
	reg			wbm2spc_way_valid;
	reg	[(132 - 131):0]	wbm2spc_way;
	reg			wbm2spc_boot_fetch;
	reg			wbm2spc_atomic;
	reg			wbm2spc_pfl;
	reg	[(127 - 0):0]	wbm2spc_data;
	reg	[6:0]		wbm2spc_interrupt_source;
	reg			wbm2spc_interrupt_new;
	wire			spc2wbm_req;
	wire			spc2wbm_valid;
	wire	[(128 - 124):0]	spc2wbm_type;
	wire			spc2wbm_nc;
	wire	[(122 - 120):0]	spc2wbm_cpu_id;
	wire	[(119 - 117):0]	spc2wbm_thread;
	wire			spc2wbm_invalidate;
	wire	[(113 - 112):0]	spc2wbm_way;
	wire	[(111 - 104):0]	spc2wbm_size;
	wire	[(103 - 64):0]	spc2wbm_addr;
	wire	[(63 - 0):0]	spc2wbm_data;
	wire	[(146 - 1):0]	wbm2spc_packet;
	reg			dir_rd_en;
	reg			val_ic;
	reg			val_dc;
	reg	[3:0]		dc_dir_wen;
	wire	[3:0]		dc_dir_hit;
	reg	[3:0]		old_dc_hit;
	reg	[4:0]		ic_dir_wen;
	wire	[7:0]		ic_dir_hit;
	reg	[7:0]		old_ic_hit;
	wire	[2:0]		ic_dir_hit_way_enc;
	wire	[1:0]		dc_dir_hit_way_enc;
	reg			spc2wbm_addr_subword;
	reg			spc_stallreq_d;
	reg			fifo_vld_d;
	reg			cas1_matched;
	wire	[63:0]		wbm_sel_o_bytemask = {{8 {spc2wbm_size[7]}}, {8
		{spc2wbm_size[6]}}, {8 {spc2wbm_size[5]}}, {8
		{spc2wbm_size[4]}}, {8 {spc2wbm_size[3]}}, {8
		{spc2wbm_size[2]}}, {8 {spc2wbm_size[1]}}, {8 {spc2wbm_size[0]}}
		};
	wire	[1:0]		ic_dir_hit_way_enc0;
	wire	[1:0]		ic_dir_hit_way_enc1;

	assign spc2wbm_req = ((((spc_req_w[4] | spc_req_w[3]) | spc_req_w[2]) | 
		spc_req_w[1]) | spc_req_w[0]);
	assign spc2wbm_valid = spc2wbm_packet[129];
	assign spc2wbm_type = spc2wbm_packet[128:124];
	assign spc2wbm_nc = spc2wbm_packet[123];
	assign spc2wbm_cpu_id = spc2wbm_packet[122:120];
	assign spc2wbm_thread = spc2wbm_packet[119:117];
	assign spc2wbm_invalidate = spc2wbm_packet[116];
	assign spc2wbm_way = spc2wbm_packet[113:112];
	assign spc2wbm_size = spc2wbm_packet[111:104];
	assign spc2wbm_addr = spc2wbm_packet[103:64];
	assign spc2wbm_data = spc2wbm_packet[63:0];
	assign wbm2spc_packet = {wbm2spc_valid, wbm2spc_type, wbm2spc_miss, 
		wbm2spc_error, wbm2spc_nc, wbm2spc_thread, wbm2spc_way_valid, 
		wbm2spc_way, wbm2spc_boot_fetch, wbm2spc_atomic, wbm2spc_pfl, 
		wbm2spc_data};
	assign spc_grant_o = (spc_grant_w & (!spc_stallreq_o));
	assign spc_atom_w = spc_atom_r;
	assign spc_req_w = (spc_req_i | {4'b0, (fifo_vld & (~spc_stallreq_w))});
	assign spc_stallreq_o = ((spc_stallreq_w | fifo_vld) | {(|spc_req_i)});
	assign spc_packetout_w = ((fifo_vld | fifo_vld_d) ? spc_packetout_i_save
		: spc_packetout_i);
	assign ic_dir_hit_way_enc = ((|ic_dir_hit[3:0]) ? {1'b0, 
		ic_dir_hit_way_enc0} : {1'b1, ic_dir_hit_way_enc1});

	l2_dir l2_dird(sys_clock_i, sys_reset_i, spc2wbm_addr[38:11], 
		{spc2wbm_addr[10:5], spc2wbm_addr_subword}, dc_dir_wen, val_dc, 
		dc_dir_hit, dc_dir_hit_way_enc, dir_rd_en);
	l2_dir l2_diri0(sys_clock_i, sys_reset_i, spc2wbm_addr[38:11], 
		{spc2wbm_addr[10:5], 1'b0}, ({4 {(~ic_dir_wen[4])}} &
		ic_dir_wen[3:0]), val_ic, ic_dir_hit[3:0], ic_dir_hit_way_enc0, 
		dir_rd_en);
	l2_dir l2_diri1(sys_clock_i, sys_reset_i, spc2wbm_addr[38:11], 
		{spc2wbm_addr[10:5], 1'b0}, ({4 {ic_dir_wen[4]}} &
		ic_dir_wen[3:0]), val_ic, ic_dir_hit[7:4], ic_dir_hit_way_enc1, 
		dir_rd_en);

	always @(posedge sys_clock_i) begin
	  spc_packetout_i_save <= (((spc_packetout_i[(130 - 1)] & spc_stallreq_d
		  ) & (~fifo_vld)) ? spc_packetout_i : ((fifo_vld & 
		  spc_stallreq_d) ? spc_packetout_i_save : spc_packetout_i_save2
		  ));
	  spc_packetout_i_save2 <= ((spc_packetout_i[(130 - 1)] & fifo_vld) ? 
		  spc_packetout_i : (fifo_vld2 ? spc_packetout_i_save2 : 0));
	  fifo_vld <= ((spc_packetout_i[(130 - 1)] & spc_stallreq_d) ? 1 : (
		  spc_stallreq_w ? fifo_vld : fifo_vld2));
	  fifo_vld2 <= ((spc_packetout_i[(130 - 1)] & fifo_vld) ? 1 : (
		  spc_stallreq_w ? fifo_vld2 : 0));
	  spc_stallreq_d <= spc_stallreq_w;
	  spc_atom_r <= (fifo_vld ? spc_atom_r : spc_atom_i);
	  fifo_vld_d <= fifo_vld;
	end
	always @(posedge sys_clock_i) begin
	  spc_packetin_o <= spc_packetin_w;
	  if (sys_reset_i == 1) begin
	    dir_rd_en <= 0;
	    spc_grant_w <= 5'b0;
	    spc_ready_o <= 0;
	    spc_packetin_w <= 0;
	    spc_stallreq_w <= 0;
	    wbm_cycle_o <= 0;
	    wbm_strobe_o <= 0;
	    wbm_we_o <= 0;
	    wbm_addr_o <= 64'b0;
	    wbm_data_o <= 64'b0;
	    wbm_sel_o <= 8'b0;
	    spc2wbm_addr_subword <= 0;
	    wbm2spc_valid <= 1;
	    wbm2spc_type <= 4'd7;
	    wbm2spc_miss <= 0;
	    wbm2spc_error <= 0;
	    wbm2spc_nc <= 0;
	    wbm2spc_thread <= 0;
	    wbm2spc_way_valid <= 0;
	    wbm2spc_way <= 0;
	    wbm2spc_boot_fetch <= 0;
	    wbm2spc_atomic <= 0;
	    wbm2spc_pfl <= 0;
	    wbm2spc_data <= 64'h0000000000010001;
	    wbm2spc_interrupt_source <= 7'b0;
	    wbm2spc_interrupt_new <= 1'b0;
	    val_ic <= 0;
	    val_dc <= 0;
	    state <= 4'b0;
	  end
	  else
	    begin
	      if (state == 4'b0) begin
		spc_packetin_w <= wbm2spc_packet;
		state <= 4'b1;
	      end
	      else if (state == 4'b1) begin
		if (spc2wbm_req == 1) begin
		  spc_ready_o <= 0;
		  spc_packetin_w <= 0;
		  dc_dir_wen <= 0;
		  ic_dir_wen <= 0;
		  wbm2spc_way_valid <= 0;
		  wbm2spc_way <= 0;
		  wbm2spc_pfl <= 0;
		  wbm2spc_data <= 0;
		  spc_stallreq_w <= 1;
		  spc2wbm_region <= spc_req_w;
		  spc2wbm_atomic <= spc_atom_w;
		  state <= 4'd2;
		end
		else if (sys_interrupt_source_i != wbm2spc_interrupt_source) 
			begin
		  wbm2spc_interrupt_new <= 1;
		  wbm2spc_valid <= 1;
		  wbm2spc_type <= 4'd7;
		  wbm2spc_miss <= 0;
		  wbm2spc_error <= 0;
		  wbm2spc_nc <= 0;
		  wbm2spc_thread <= 0;
		  wbm2spc_boot_fetch <= 0;
		  wbm2spc_atomic <= 0;
		  wbm2spc_pfl <= 0;
		  spc_stallreq_w <= 1;
		end
		else if ((wbm2spc_interrupt_source != 6'b0) && 
			wbm2spc_interrupt_new) begin
		  wbm2spc_interrupt_new <= 0;
		  spc_ready_o <= 1;
		  spc_packetin_w <= wbm2spc_packet;
		  spc_stallreq_w <= 1;
		  state <= 4'b1;
		end
		else
		  begin
		    spc_ready_o <= 0;
		    spc_packetin_w <= 0;
		    spc_stallreq_w <= 0;
		    state <= 4'b1;
		  end
	      end
	      else if (state == 4'd2) begin
		spc2wbm_addr_subword <= spc_packetout_w[4+64];
		spc2wbm_packet <= spc_packetout_w;
		spc_grant_w <= spc2wbm_region;
		state <= 4'd3;
	      end
	      else if (state == 4'd3) begin
		spc2wbm_addr_subword <= spc2wbm_addr[4];
		spc_grant_w <= 5'b0;
		wbm_cycle_o <= 1;
		wbm_strobe_o <= 1;
		if ((~spc2wbm_addr[39]) && ((spc2wbm_type == 5'b0) || (
			spc2wbm_type == 5'b00010))) begin
		  wbm_addr_o <= {spc2wbm_region, 19'b0, spc2wbm_addr[(103 -
			  64):4], 4'b0};
		  dc_dir_wen <= ({4 {(~spc2wbm_nc)}} & ((spc2wbm_way == 0) ? 
			  4'b1 : ((spc2wbm_way == 1) ? 4'd2 : ((spc2wbm_way == 2
			  ) ? 4'd4 : 4'd8))));
		  val_dc <= 1;
		end
		else begin
		  wbm_addr_o <= {spc2wbm_region, 19'b0, spc2wbm_addr[(103 -
			  64):3], 3'b0};
		end
		wbm_data_o <= spc2wbm_data;
		if (spc2wbm_type == 5'b10000) begin
		  ic_dir_wen <= ({5 {(~spc2wbm_nc)}} & {spc2wbm_packet[114], 
			  ((spc2wbm_way == 0) ? 4'b1 : ((spc2wbm_way == 1) ?
			  4'd2 : ((spc2wbm_way == 2) ? 4'd4 : 4'd8)))});
		  val_ic <= 1;
		  wbm_we_o <= 0;
		  if (spc2wbm_region == 5'b10000) begin
		    wbm_sel_o <= (4'b1111 << (spc2wbm_addr[2] << 2));
		  end
		  else begin
		    wbm_sel_o <= 8'b11111111;
		  end
		end
		else if (spc2wbm_type == 5'b01000) begin
		  wbm_sel_o <= 8'b11111111;
		  wbm_we_o <= 0;
		end
		else if (((spc2wbm_type == 5'b0) || (spc2wbm_type == 5'b00010)) 
			|| (spc2wbm_type == 5'b00111)) begin
		  if (spc2wbm_addr[39]) begin
		    wbm_we_o <= 0;
		    if (spc2wbm_type == 5'b0) begin
		      case (spc2wbm_size)
			3'b0:
			  wbm_sel_o <= (1'b1 << spc2wbm_addr[2:0]);
			3'b1:
			  wbm_sel_o <= (2'b11 << (spc2wbm_addr[2:1] << 1));
			3'd2:
			  wbm_sel_o <= (4'b1111 << (spc2wbm_addr[2] << 2));
			3'd3:
			  wbm_sel_o <= 8'b11111111;
			3'd7:
			  wbm_sel_o <= 8'b11111111;
			default:
			  wbm_sel_o <= 8'b0;
		      endcase
		    end
		    else begin
		      wbm_sel_o <= spc2wbm_size;
		    end
		  end
		  else
		    begin
		      wbm_sel_o <= 8'b11111111;
		    end
		end
		else if ((spc2wbm_type == 5'b1) || ((spc2wbm_type == 5'b00011) 
			&& cas1_matched)) begin
		  wbm_we_o <= 1;
		  wbm_sel_o <= spc2wbm_size;
		end
		else
		  begin
		    wbm_we_o <= 1;
		    wbm_sel_o <= 8'b0;
		  end
                 
		begin
                   // synopsys translate_off
		  case (spc2wbm_type)
		    5'b0:
		      $display("INFO: SPC2WBM: Request of Type LOAD_RQ");
		    5'b10000:
		      $display("INFO: SPC2WBM: Request of Type IMISS_RQ");
		    5'b1:
		      $display("INFO: SPC2WBM: Request of Type STORE_RQ");
		    5'b01000:
		      $display("INFO: SPC2WBM: Request of Type MMU_RQ");
		    5'b00010:
		      $display("INFO: SPC2WBM: Request of Type CAS1_RQ");
		    5'b00011:
		      $display("INFO: SPC2WBM: Request of Type CAS2_RQ");
		    5'b00111:
		      $display("INFO: SPC2WBM: Request of Type SWAP_RQ");
		    5'b00100:
		      $display("INFO: SPC2WBM: Request of Type STRLOAD_RQ");
		    5'b01001:
		      $display("INFO: SPC2WBM: Request of Type INT_RQ");
		    5'b11111:
		      $display("INFO: SPC2WBM: Request of Type RSVD_RQ");
		    default:
		      $display("INFO: SPC2WBM: ERROR!!! Request of Type Unknown"
			      );
		  endcase
		  $display("INFO: SPC2WBM: Address is %X", spc2wbm_addr);
		  $display("INFO: SPC2WBM: Data is %X", spc2wbm_data);
                   // synopsys translate_on
		end
		state <= 4'd4;
	      end
	      else if (state == 4'd4) begin
		dc_dir_wen <= 0;
		ic_dir_wen <= 0;
		if (wbm_ack_i == 1) begin
		  dir_rd_en <= 1;
		  if (spc2wbm_atomic == 0) begin
		    wbm_cycle_o <= 0;
		  end
		  wbm_strobe_o <= 0;
		  wbm_we_o <= 0;
		  wbm_addr_o <= 64'b0;
		  wbm_data_o <= 64'b0;
		  wbm_sel_o <= 8'b0;
		  wbm2spc_valid <= 1;
		  case (spc2wbm_type)
		    5'b10000: begin
		      wbm2spc_type <= 4'b1;
		      wbm2spc_way_valid <= (|dc_dir_hit);
		      wbm2spc_way <= dc_dir_hit_way_enc;
		      wbm2spc_atomic <= 0;
		      val_dc <= 0;
		      if (|dc_dir_hit) begin
			dc_dir_wen <= dc_dir_hit;
			val_dc <= 0;
		      end
		    end
		    5'b00111: begin
		      $display("%t, SWAP %x", $time, spc_packetin_w);
		      wbm2spc_type <= 4'b0;
		      wbm2spc_atomic <= 1;
		    end
		    5'b0: begin
		      wbm2spc_atomic <= 0;
		      if (spc2wbm_addr[39]) begin
			wbm2spc_type <= 4'd8;
		      end
		      else
			begin
			  wbm2spc_pfl <= spc2wbm_packet[115];
			  wbm2spc_type <= 4'b0;
			  wbm2spc_way_valid <= (|ic_dir_hit);
			  wbm2spc_way <= ic_dir_hit_way_enc[2:1];
			  wbm2spc_boot_fetch <= ic_dir_hit_way_enc[0];
			  if (|ic_dir_hit) begin
			    ic_dir_wen <= ((|ic_dir_hit[3:0]) ? {1'b0, 
				    ic_dir_hit[3:0]} : {1'b1, ic_dir_hit[7:4]});
			    val_ic <= 0;
			  end
			end
		    end
		    5'b01000: begin
		      wbm2spc_type <= 4'd5;
		      wbm2spc_atomic <= spc2wbm_atomic;
		    end
		    5'b1: begin
		      wbm2spc_type <= 4'd4;
		      wbm2spc_atomic <= spc2wbm_atomic;
		    end
		    5'b00010: begin
		      wbm2spc_type <= 4'b0;
		      wbm2spc_atomic <= 1'b1;
		    end
		    5'b00011: begin
		      wbm2spc_type <= 4'd4;
		      wbm2spc_atomic <= 1'b1;
		    end
		  endcase
		  wbm2spc_miss <= 0;
		  wbm2spc_error <= 0;
		  wbm2spc_nc <= spc2wbm_nc;
		  wbm2spc_thread <= spc2wbm_thread;
		  if (spc2wbm_addr[39]) begin
		    if (spc2wbm_region == 5'b10000) begin
		      wbm2spc_boot_fetch <= 1;
		    end
		    else begin
		      wbm2spc_boot_fetch <= 0;
		    end
		  end
		  if ((spc2wbm_type == 5'b1) || (spc2wbm_type == 5'b00011)) 
			  begin
		    wbm2spc_data[125] <= spc2wbm_packet[114];
		    wbm2spc_data[63:0] <= spc2wbm_data[63:0];
		    if (|ic_dir_hit) begin
		      wbm2spc_data[67:64] <= {ic_dir_hit_way_enc, 1'b1};
		      ic_dir_wen <= ((|ic_dir_hit[3:0]) ? {1'b0, ic_dir_hit[3:0]
			      } : {1'b1, ic_dir_hit[7:4]});
		      val_ic <= 0;
                      wbm2spc_data[116:112] <= spc2wbm_addr[10:6];
                      wbm2spc_data[122:121] <= spc2wbm_addr[5:4];
                      wbm2spc_data[104] <= spc2wbm_addr[3];
                      wbm2spc_data[103:96] <= spc2wbm_size[7:0];
		    end
		    if (|dc_dir_hit) begin
		      wbm2spc_data[116:112] <= spc2wbm_addr[10:6];
		      wbm2spc_data[122:121] <= spc2wbm_addr[5:4];
		      wbm2spc_data[104] <= spc2wbm_addr[3];
		      wbm2spc_data[103:96] <= spc2wbm_size[7:0];
		      wbm2spc_data[67:64] <= {dc_dir_hit_way_enc, 2'b10};
		      if (spc2wbm_type == 5'b00011) begin
			dc_dir_wen <= dc_dir_hit;
			val_dc <= 0;
		      end
		    end
		  end
		  else
		    begin //DW FIX FIX for mpgen problem
		      if ((spc2wbm_addr[3] == 0) || (spc2wbm_addr[39] == 0 && spc2wbm_type != 5'b00111))
			      begin
			 wbm2spc_data <= {wbm_data_i, 64'b0};
		      end
		      else begin
			wbm2spc_data <= {64'b0, wbm_data_i};
		      end
		    end
		  if (((((spc2wbm_type == 5'b10000) && (spc2wbm_region != 
			  5'b10000)) || (spc2wbm_type == 5'b01000)) || (
			  spc2wbm_type == 5'b00010)) || ((spc2wbm_type == 5'b0) 
			  && ((spc2wbm_size == 3'd7) || (spc2wbm_addr[39] == 0))
			  )) begin
		    state <= 4'd5;
		  end
		  else if (spc2wbm_type == 5'b00111) begin
		    state <= 4'd9;
		    $display("%t, SWAP 2  %x", $time, spc_packetin_w);
		  end
		  else begin
		    state <= 4'b1011;
		  end
		end
		else begin
		  state <= 4'd4;
		end
	      end
	      else if (state == 4'd5) begin
		dir_rd_en <= 0;
		dc_dir_wen <= 0;
		ic_dir_wen <= 0;
		wbm_cycle_o <= 1;
		wbm_strobe_o <= 1;
		wbm_we_o <= 0;
		wbm_addr_o <= {spc2wbm_region, 19'b0, spc2wbm_addr[(103 -
			64):4], 4'd8};
		wbm_data_o <= 64'b0;
		wbm_sel_o <= 8'b11111111;
		state <= 4'd6;
	      end
	      else if (state == 4'd6) begin
		if (wbm_ack_i == 1) begin
		  if (spc2wbm_atomic == 0) begin
		    wbm_cycle_o <= 0;
		  end
		  wbm_strobe_o <= 0;
		  wbm_we_o <= 0;
		  wbm_addr_o <= 64'b0;
		  wbm_data_o <= 64'b0;
		  wbm_sel_o <= 8'b0;
		  wbm2spc_data[63:0] <= wbm_data_i;
		  if ((spc2wbm_type == 5'b10000) && (spc2wbm_region != 5'b10000)
			  ) begin
		    state <= 4'd7;
		  end
		  else begin
		    state <= 4'b1011;
		  end
		end
		else begin
		  state <= 4'd6;
		end
	      end
	      else if (state == 4'd7) begin
		spc2wbm_addr_subword <= 2'b1;
		spc_packetin_w <= wbm2spc_packet;
		wbm_cycle_o <= 1;
		wbm_strobe_o <= 1;
		wbm_we_o <= 0;
		dir_rd_en <= 1;
		wbm_addr_o <= {spc2wbm_region, 19'b0, spc2wbm_addr[(103 -
			64):5], 5'b10000};
		wbm_data_o <= 64'b0;
		wbm_sel_o <= 8'b11111111;
		// synopsys translate_off
		case (wbm2spc_type)
		  4'b1:
		    $display("INFO: WBM2SPC: Return Packet of Type IFILL_RET");
		  4'b0:
		    $display("INFO: WBM2SPC: Return Packet of Type LOAD_RET");
		  4'd5:
		    $display("INFO: WBM2SPC: Return Packet of Type MMU_RET");
		  4'd4:
		    $display("INFO: WBM2SPC: Return Packet of Type ST_ACK");
		  default:
		    $display("INFO: WBM2SPC: Return Packet of Type Unknown");
		endcase
		$display("INFO: WBM2SPC: Data is %X", wbm2spc_data);
		// synopsys translate_on
		state <= 4'd8;
	      end
	      else if (state == 4'd8) begin
		if (|dc_dir_hit) begin
		  dc_dir_wen <= dc_dir_hit;
		  val_dc <= 0;
		end
		wbm2spc_way_valid <= (|dc_dir_hit);
		wbm2spc_way <= dc_dir_hit_way_enc;
		spc_ready_o <= 0;
		if (wbm_ack_i == 1) begin
		  if (spc2wbm_atomic == 0) begin
		    wbm_cycle_o <= 0;
		  end
		  wbm_strobe_o <= 0;
		  wbm_we_o <= 0;
		  wbm_addr_o <= 64'b0;
		  wbm_data_o <= 64'b0;
		  wbm_sel_o <= 8'b0;
		  wbm2spc_data <= {wbm_data_i, 64'b0};
		  wbm2spc_way_valid <= (|dc_dir_hit);
		  wbm2spc_way <= dc_dir_hit_way_enc;
		  dir_rd_en <= 1;
		  state <= 4'd9;
		end
		else begin
		  state <= 4'd8;
		end
	      end
	      else if (state == 4'd9) begin
		wbm_cycle_o <= 1;
		wbm_strobe_o <= 1;
		if (spc2wbm_type == 5'b00111) begin
		  $display("%t, SWAP 3  %x", $time, spc_packetin_w);
		  spc_ready_o <= 1;
		  spc_packetin_w <= wbm2spc_packet;
		  wbm_we_o <= 1;
		  wbm_data_o <= spc2wbm_data;
		  wbm_sel_o <= spc2wbm_size;
		  wbm_addr_o <= {spc2wbm_region, 19'b0, spc2wbm_addr[(103 -
			  64):0]};
		  dir_rd_en <= 1;
		end
		else
		  begin
		    wbm_we_o <= 0;
		    wbm_sel_o <= 8'b11111111;
		    wbm_addr_o <= {spc2wbm_region, 19'b0, spc2wbm_addr[(103 -
			    64):5], 5'b11000};
		    wbm_data_o <= 64'b0;
		  end
		state <= 4'd10;
	      end
	      else if (state == 4'd10) begin
		spc_ready_o <= 0;
		if (wbm_ack_i == 1) begin
		  if (spc2wbm_atomic == 0) begin
		    wbm_cycle_o <= 0;
		  end
		  wbm_strobe_o <= 0;
		  wbm_we_o <= 0;
		  wbm_addr_o <= 64'b0;
		  wbm_data_o <= 64'b0;
		  wbm_sel_o <= 8'b0;
		  if (spc2wbm_type == 5'b00111) begin
		    wbm2spc_data[127:64] <= 64'b0;
		    wbm2spc_atomic <= 1;
		    wbm2spc_type <= 4'd4;
		    wbm2spc_data[63:0] <= spc2wbm_data[63:0];
		    if (|ic_dir_hit) begin
		      wbm2spc_data[67:64] <= {ic_dir_hit_way_enc, 1'b1};
		      ic_dir_wen <= ((|ic_dir_hit[3:0]) ? {1'b0, ic_dir_hit[3:0]
			      } : {1'b1, ic_dir_hit[7:4]});
		      val_ic <= 0;
		    end
		    if (|dc_dir_hit) begin
		      wbm2spc_data[116:112] <= spc2wbm_addr[10:6];
		      wbm2spc_data[122:121] <= spc2wbm_addr[5:4];
		      wbm2spc_data[104] <= spc2wbm_addr[3];
		      wbm2spc_data[103:96] <= spc2wbm_size[7:0];
		      wbm2spc_data[67:64] <= {dc_dir_hit_way_enc, 2'b10};
		    end
		  end
		  else
		    begin
		      spc_ready_o <= 1;
		      wbm2spc_atomic <= 1;
		      wbm2spc_data[63:0] <= wbm_data_i;
		    end
		  state <= 4'b1011;
		end
		else begin
		  state <= 4'd10;
		end
	      end
	      else if (state == 4'b1011) begin
		if (spc2wbm_type == 5'b00010) begin
		  if (((wbm2spc_data[63:0] & wbm_sel_o_bytemask) == (
			  spc2wbm_data[63:0] & wbm_sel_o_bytemask)) & 
			  spc2wbm_addr[3]) begin
		    cas1_matched <= 1'b1;
		  end
		  else if (((wbm2spc_data[127:64] & wbm_sel_o_bytemask) == (
			  spc2wbm_data[63:0] & wbm_sel_o_bytemask)) & (~
			  spc2wbm_addr[3])) begin
		    cas1_matched <= 1'b1;
		  end
		  else
		    begin
		      $display("%t, CAS failed pa:%x Act:%x Exp:%x Mask:%x", 
			      $time, spc2wbm_addr, wbm_data_i, spc2wbm_data, 
			      wbm_sel_o_bytemask);
		      cas1_matched <= 1'b0;
		    end
		end
		dir_rd_en <= 0;
		dc_dir_wen <= 0;
		ic_dir_wen <= 0;
		spc_ready_o <= 1;
		spc_packetin_w <= wbm2spc_packet;
		state <= 4'b1;
	      end
	    end
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_regs.v                                                 ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  Registers of the uart 16550 core                            ////
////                                                              ////
////  Known problems (limits):                                    ////
////  Inserts 1 wait state in all WISHBONE transfers              ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing or verification.                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   (See log for the revision history           ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_regs.v,v $
// Revision 1.42  2004/11/22 09:21:59  igorm
// Timeout interrupt should be generated only when there is at least ony
// character in the fifo.
//
// Revision 1.41  2004/05/21 11:44:41  tadejm
// Added synchronizer flops for RX input.
//
// Revision 1.40  2003/06/11 16:37:47  gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.39  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.38  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.37  2001/12/27 13:24:09  mohor
// lsr[7] was not showing overrun errors.
//
// Revision 1.36  2001/12/20 13:25:46  mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.35  2001/12/19 08:03:34  mohor
// Warnings cleared.
//
// Revision 1.34  2001/12/19 07:33:54  mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.33  2001/12/17 10:14:43  mohor
// Things related to msr register changed. After THRE IRQ occurs, and one
// character is written to the transmit fifo, the detection of the THRE bit in the
// LSR is delayed for one character time.
//
// Revision 1.32  2001/12/14 13:19:24  mohor
// MSR register fixed.
//
// Revision 1.31  2001/12/14 10:06:58  mohor
// After reset modem status register MSR should be reset.
//
// Revision 1.30  2001/12/13 10:09:13  mohor
// thre irq should be cleared only when being source of interrupt.
//
// Revision 1.29  2001/12/12 09:05:46  mohor
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
//
// Revision 1.28  2001/12/10 19:52:41  gorban
// Scratch register added
//
// Revision 1.27  2001/12/06 14:51:04  gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.26  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.25  2001/11/28 19:36:39  gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.24  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.23  2001/11/12 21:57:29  gorban
// fixed more typo bugs
//
// Revision 1.22  2001/11/12 15:02:28  mohor
// lsr1r error fixed.
//
// Revision 1.21  2001/11/12 14:57:27  mohor
// ti_int_pnd error fixed.
//
// Revision 1.20  2001/11/12 14:50:27  mohor
// ti_int_d error fixed.
//
// Revision 1.19  2001/11/10 12:43:21  gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.18  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.17  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.16  2001/11/02 09:55:16  mohor
// no message
//
// Revision 1.15  2001/10/31 15:19:22  gorban
// Fixes to break and timeout conditions
//
// Revision 1.14  2001/10/29 17:00:46  gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.13  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.12  2001/10/19 16:21:40  gorban
// Changes data_out to be synchronous again as it should have been.
//
// Revision 1.11  2001/10/18 20:35:45  gorban
// small fix
//
// Revision 1.10  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.9  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.10  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.8  2001/05/29 20:05:04  gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.5  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:11+02  jacob
// Initial revision
//

`timescale 1 ns / 10 ps
module uart_regs(clk, wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
	modem_inputs, stx_pad_o, srx_pad_i, rts_pad_o, dtr_pad_o, int_o, baud_o)
	;

	input			clk;
	input			wb_rst_i;
	input	[(3 - 1):0]	wb_addr_i;
	input	[7:0]		wb_dat_i;
	output	[7:0]		wb_dat_o;
	input			wb_we_i;
	input			wb_re_i;
	output			stx_pad_o;
	input			srx_pad_i;
	input	[3:0]		modem_inputs;
	output			rts_pad_o;
	output			dtr_pad_o;
	output			int_o;
	output			baud_o;

	reg			enable;
	wire			srx_pad;
	reg	[7:0]		wb_dat_o;
	reg	[3:0]		ier;
	reg	[3:0]		iir;
	reg	[1:0]		fcr;
	reg	[4:0]		mcr;
	reg	[7:0]		lcr;
	reg	[7:0]		msr;
	reg	[15:0]		dl;
	reg	[7:0]		scratch;
	reg			start_dlc;
	reg			lsr_mask_d;
	reg			msi_reset;
	reg	[15:0]		dlc;
	reg	[3:0]		trigger_level;
	reg			rx_reset;
	reg			tx_reset;
	wire			dlab;
	wire			cts_pad_i;
	wire			dsr_pad_i;
	wire			ri_pad_i;
	wire			dcd_pad_i;
	wire			loopback;
	wire			cts;
	wire			dsr;
	wire			ri;
	wire			dcd;
	wire			cts_c;
	wire			dsr_c;
	wire			ri_c;
	wire			dcd_c;
	reg			int_o;
	wire	[7:0]		lsr;
	wire			lsr0;
	wire			lsr1;
	wire			lsr2;
	wire			lsr3;
	wire			lsr4;
	wire			lsr5;
	wire			lsr6;
	wire			lsr7;
	reg			lsr0r;
	reg			lsr1r;
	reg			lsr2r;
	reg			lsr3r;
	reg			lsr4r;
	reg			lsr5r;
	reg			lsr6r;
	reg			lsr7r;
	wire			lsr_mask;
	wire			rls_int;
	wire			rda_int;
	wire			ti_int;
	wire			thre_int;
	wire			ms_int;
	reg			tf_push;
	reg			rf_pop;
	wire	[(11 - 1):0]	rf_data_out;
	wire			rf_error_bit;
	wire	[(5 - 1):0]	rf_count;
	wire	[(5 - 1):0]	tf_count;
	wire	[2:0]		tstate;
	wire	[3:0]		rstate;
	wire	[9:0]		counter_t;
	wire			thre_set_en;
	reg	[7:0]		block_cnt;
	reg	[7:0]		block_value;
	wire			serial_out;
	wire			serial_in = (loopback ? serial_out : srx_pad);
	wire			rf_overrun;
	wire			rf_push_pulse;
	wire			lsr_mask_condition;
	wire			iir_read;
	wire			msr_read;
	wire			fifo_read;
	wire			fifo_write;
	reg	[3:0]		delayed_modem_signals;
	reg			lsr0_d;
	reg			lsr1_d;
	reg			lsr2_d;
	reg			lsr3_d;
	reg			lsr4_d;
	reg			lsr5_d;
	reg			lsr6_d;
	reg			lsr7_d;
	reg			rls_int_d;
	reg			thre_int_d;
	reg			ms_int_d;
	reg			ti_int_d;
	reg			rda_int_d;
	wire			rls_int_rise;
	wire			thre_int_rise;
	wire			ms_int_rise;
	wire			ti_int_rise;
	wire			rda_int_rise;
	reg			rls_int_pnd;
	reg			rda_int_pnd;
	reg			thre_int_pnd;
	reg			ms_int_pnd;
	reg			ti_int_pnd;

	defparam i_uart_sync_flops.width	= 1;
	defparam i_uart_sync_flops.init_value	= 1'b1;

	assign baud_o = enable;
	assign lsr[7:0] = {lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, 
		lsr0r};
	assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
	assign {cts, dsr, ri, dcd} = (~{cts_pad_i, dsr_pad_i, ri_pad_i, 
		dcd_pad_i});
	assign {cts_c, dsr_c, ri_c, dcd_c} = (loopback ? {mcr[1], mcr[0], 
		mcr[2], mcr[3]} : {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i});
	assign dlab = lcr[7];
	assign loopback = mcr[4];
	assign rts_pad_o = mcr[1];
	assign dtr_pad_o = mcr[0];
	assign stx_pad_o = (loopback ? 1'b1 : serial_out);
	assign lsr_mask_condition = ((wb_re_i && (wb_addr_i == 3'd5)) && (!dlab)
		);
	assign iir_read = ((wb_re_i && (wb_addr_i == 3'd2)) && (!dlab));
	assign msr_read = ((wb_re_i && (wb_addr_i == 3'd6)) && (!dlab));
	assign fifo_read = ((wb_re_i && (wb_addr_i == 3'b0)) && (!dlab));
	assign fifo_write = ((wb_we_i && (wb_addr_i == 3'b0)) && (!dlab));
	assign lsr_mask = (lsr_mask_condition && (~lsr_mask_d));
	assign lsr0 = ((rf_count == 0) && rf_push_pulse);
	assign lsr1 = rf_overrun;
	assign lsr2 = rf_data_out[1];
	assign lsr3 = rf_data_out[0];
	assign lsr4 = rf_data_out[2];
	assign lsr5 = (tf_count != 5'b01111);
	assign lsr6 = (((tf_count == 5'b0) && thre_set_en) && (tstate == 0));
	assign lsr7 = (rf_error_bit | rf_overrun);
	assign thre_set_en = (~(|block_cnt));
	assign rls_int = (ier[2] && (((lsr[1] || lsr[2]) || lsr[3]) || lsr[4]));
	assign rda_int = (ier[0] && (rf_count >= {1'b0, trigger_level}));
	assign thre_int = (ier[1] && lsr[5]);
	assign ms_int = (ier[3] && (|msr[3:0]));
	assign ti_int = ((ier[0] && (counter_t == 10'b0)) && (|rf_count));
	assign rda_int_rise = (rda_int & (~rda_int_d));
	assign rls_int_rise = (rls_int & (~rls_int_d));
	assign thre_int_rise = (thre_int & (~thre_int_d));
	assign ms_int_rise = (ms_int & (~ms_int_d));
	assign ti_int_rise = (ti_int & (~ti_int_d));

	uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, 
		enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
	uart_sync_flops i_uart_sync_flops(
		.rst_i				(wb_rst_i), 
		.clk_i				(clk), 
		.stage1_rst_i			(1'b0), 
		.stage1_clk_en_i		(1'b1), 
		.async_dat_i			(srx_pad_i), 
		.sync_dat_o			(srx_pad));
	uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable, 
		counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, 
		rx_reset, lsr_mask, rstate, rf_push_pulse);

	always @(dl or dlab or ier or iir or scratch or lcr or lsr or msr or 
		rf_data_out or wb_addr_i or wb_re_i) begin
	  case (wb_addr_i)
	    3'b0:
	      wb_dat_o = (dlab ? dl[7:0] : rf_data_out[10:3]);
	    3'b1:
	      wb_dat_o = (dlab ? dl[15:8] : ier);
	    3'd2:
	      wb_dat_o = {4'b1100, iir};
	    3'd3:
	      wb_dat_o = lcr;
	    3'd5:
	      wb_dat_o = lsr;
	    3'd6:
	      wb_dat_o = msr;
	    3'd7:
	      wb_dat_o = scratch;
	    default:
	      wb_dat_o = 8'b0;
	  endcase
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    rf_pop <= #(1) 0;
	  end
	  else if (rf_pop) begin
	    rf_pop <= #(1) 0;
	  end
	  else if ((wb_re_i && (wb_addr_i == 3'b0)) && (!dlab)) begin
	    rf_pop <= #(1) 1;
	  end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    lsr_mask_d <= #(1) 0;
	  end
	  else begin
	    lsr_mask_d <= #(1) lsr_mask_condition;
	  end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    msi_reset <= #(1) 1;
	  end
	  else if (msi_reset) begin
	    msi_reset <= #(1) 0;
	  end
	  else if (msr_read) begin
	    msi_reset <= #(1) 1;
	  end
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lcr <= #(1) 8'b00000011;
	end
	else if (wb_we_i && (wb_addr_i == 3'd3)) begin
	  lcr <= #(1) wb_dat_i;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  ier <= #(1) 4'b0;
	  dl[15:8] <= #(1) 8'b0;
	end
	else if (wb_we_i && (wb_addr_i == 3'b1)) begin
	  if (dlab) begin
	    dl[15:8] <= #(1) wb_dat_i;
	  end
	  else begin
	    ier <= #(1) wb_dat_i[3:0];
	  end
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  fcr <= #(1) 2'b11;
	  rx_reset <= #(1) 0;
	  tx_reset <= #(1) 0;
	end
	else if (wb_we_i && (wb_addr_i == 3'd2)) begin
	  fcr <= #(1) wb_dat_i[7:6];
	  rx_reset <= #(1) wb_dat_i[1];
	  tx_reset <= #(1) wb_dat_i[2];
	end
	else
	  begin
	    rx_reset <= #(1) 0;
	    tx_reset <= #(1) 0;
	  end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  mcr <= #(1) 5'b0;
	end
	else if (wb_we_i && (wb_addr_i == 3'd4)) begin
	  mcr <= #(1) wb_dat_i[4:0];
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  scratch <= #(1) 0;
	end
	else if (wb_we_i && (wb_addr_i == 3'd7)) begin
	  scratch <= #(1) wb_dat_i;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  dl[7:0] <= #(1) 8'b0;
	  tf_push <= #(1) 1'b0;
	  start_dlc <= #(1) 1'b0;
	end
	else if (wb_we_i && (wb_addr_i == 3'b0)) begin
	  if (dlab) begin
	    dl[7:0] <= #(1) wb_dat_i;
	    start_dlc <= #(1) 1'b1;
	    tf_push <= #(1) 1'b0;
	  end
	  else
	    begin
	      tf_push <= #(1) 1'b1;
	      start_dlc <= #(1) 1'b0;
	    end
	end
	else
	  begin
	    start_dlc <= #(1) 1'b0;
	    tf_push <= #(1) 1'b0;
	  end
	always @(fcr) case (fcr[1:0])
	  2'b0:
	    trigger_level = 1;
	  2'b1:
	    trigger_level = 4;
	  2'b10:
	    trigger_level = 8;
	  2'b11:
	    trigger_level = 14;
	endcase
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    msr <= #(1) 0;
	    delayed_modem_signals[3:0] <= #(1) 0;
	  end
	  else
	    begin
	      msr[3:0] <= #(1) (msi_reset ? 4'b0 : (msr[3:0] | ({dcd, ri, dsr, 
		      cts} ^ delayed_modem_signals[3:0])));
	      msr[7:4] <= #(1) {dcd_c, ri_c, dsr_c, cts_c};
	      delayed_modem_signals[3:0] <= #(1) {dcd, ri, dsr, cts};
	    end
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr0_d <= #(1) 0;
	end
	else begin
	  lsr0_d <= #(1) lsr0;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr0r <= #(1) 0;
	end
	else begin
	  lsr0r <= #(1) (((((rf_count == 1) && rf_pop) && (!rf_push_pulse)) || 
		  rx_reset) ? 0 : (lsr0r || (lsr0 && (~lsr0_d))));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr1_d <= #(1) 0;
	end
	else begin
	  lsr1_d <= #(1) lsr1;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr1r <= #(1) 0;
	end
	else begin
	  lsr1r <= #(1) (lsr_mask ? 0 : (lsr1r || (lsr1 && (~lsr1_d))));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr2_d <= #(1) 0;
	end
	else begin
	  lsr2_d <= #(1) lsr2;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr2r <= #(1) 0;
	end
	else begin
	  lsr2r <= #(1) (lsr_mask ? 0 : (lsr2r || (lsr2 && (~lsr2_d))));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr3_d <= #(1) 0;
	end
	else begin
	  lsr3_d <= #(1) lsr3;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr3r <= #(1) 0;
	end
	else begin
	  lsr3r <= #(1) (lsr_mask ? 0 : (lsr3r || (lsr3 && (~lsr3_d))));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr4_d <= #(1) 0;
	end
	else begin
	  lsr4_d <= #(1) lsr4;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr4r <= #(1) 0;
	end
	else begin
	  lsr4r <= #(1) (lsr_mask ? 0 : (lsr4r || (lsr4 && (~lsr4_d))));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr5_d <= #(1) 1;
	end
	else begin
	  lsr5_d <= #(1) lsr5;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr5r <= #(1) 1;
	end
	else begin
	  lsr5r <= #(1) lsr5;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr6_d <= #(1) 1;
	end
	else begin
	  lsr6_d <= #(1) lsr6;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr6r <= #(1) 1;
	end
	else begin
	  lsr6r <= #(1) (fifo_write ? 0 : (lsr6r || (lsr6 && (~lsr6_d))));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr7_d <= #(1) 0;
	end
	else begin
	  lsr7_d <= #(1) lsr7;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  lsr7r <= #(1) 0;
	end
	else begin
	  lsr7r <= #(1) (lsr_mask ? 0 : (lsr7r || (lsr7 && (~lsr7_d))));
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    dlc <= #(1) 0;
	  end
	  else if (start_dlc | (~(|dlc))) begin
	    dlc <= #(1) (dl - 1);
	  end
	  else begin
	    dlc <= #(1) (dlc - 1);
	  end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    enable <= #(1) 1'b0;
	  end
	  else if ((|dl) & (~(|dlc))) begin
	    enable <= #(1) 1'b1;
	  end
	  else begin
	    enable <= #(1) 1'b0;
	  end
	end
	always @(lcr) case (lcr[3:0])
	  4'b0:
	    block_value = 95;
	  4'd4:
	    block_value = 103;
	  4'b1, 4'd8:
	    block_value = 111;
	  4'b1100:
	    block_value = 119;
	  4'd2, 4'd5, 4'd9:
	    block_value = 127;
	  4'd3, 4'd6, 4'd10, 4'b1101:
	    block_value = 143;
	  4'd7, 4'b1011, 4'b1110:
	    block_value = 159;
	  4'b1111:
	    block_value = 175;
	endcase
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    block_cnt <= #(1) 8'b0;
	  end
	  else if (lsr5r & fifo_write) begin
	    block_cnt <= #(1) block_value;
	  end
	  else if (enable & (block_cnt != 8'b0)) begin
	    block_cnt <= #(1) (block_cnt - 1);
	  end
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  rls_int_d <= #(1) 0;
	end
	else begin
	  rls_int_d <= #(1) rls_int;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  rda_int_d <= #(1) 0;
	end
	else begin
	  rda_int_d <= #(1) rda_int;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  thre_int_d <= #(1) 0;
	end
	else begin
	  thre_int_d <= #(1) thre_int;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  ms_int_d <= #(1) 0;
	end
	else begin
	  ms_int_d <= #(1) ms_int;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  ti_int_d <= #(1) 0;
	end
	else begin
	  ti_int_d <= #(1) ti_int;
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  rls_int_pnd <= #(1) 0;
	end
	else begin
	  rls_int_pnd <= #(1) (lsr_mask ? 0 : (rls_int_rise ? 1 : (rls_int_pnd 
		  && ier[2])));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  rda_int_pnd <= #(1) 0;
	end
	else begin
	  rda_int_pnd <= #(1) (((rf_count == {1'b0, trigger_level}) && fifo_read
		  ) ? 0 : (rda_int_rise ? 1 : (rda_int_pnd && ier[0])));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  thre_int_pnd <= #(1) 0;
	end
	else begin
	  thre_int_pnd <= #(1) ((fifo_write || ((iir_read & (~iir[0])) & (
		  iir[3:1] == 3'b1))) ? 0 : (thre_int_rise ? 1 : (thre_int_pnd 
		  && ier[1])));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  ms_int_pnd <= #(1) 0;
	end
	else begin
	  ms_int_pnd <= #(1) (msr_read ? 0 : (ms_int_rise ? 1 : (ms_int_pnd && 
		  ier[3])));
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  ti_int_pnd <= #(1) 0;
	end
	else begin
	  ti_int_pnd <= #(1) (fifo_read ? 0 : (ti_int_rise ? 1 : (ti_int_pnd && 
		  ier[0])));
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    int_o <= #(1) 1'b0;
	  end
	  else begin
	    int_o <= #(1) (rls_int_pnd ? (~lsr_mask) : (rda_int_pnd ? 1 : (
		    ti_int_pnd ? (~fifo_read) : (thre_int_pnd ? (!(fifo_write & 
		    iir_read)) : (ms_int_pnd ? (~msr_read) : 0)))));
	  end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    iir <= #(1) 1;
	  end
	  else if (rls_int_pnd) begin
	    iir[3:1] <= #(1) 3'd3;
	    iir[0] <= #(1) 1'b0;
	  end
	  else if (rda_int) begin
	    iir[3:1] <= #(1) 3'd2;
	    iir[0] <= #(1) 1'b0;
	  end
	  else if (ti_int_pnd) begin
	    iir[3:1] <= #(1) 3'd6;
	    iir[0] <= #(1) 1'b0;
	  end
	  else if (thre_int_pnd) begin
	    iir[3:1] <= #(1) 3'b1;
	    iir[0] <= #(1) 1'b0;
	  end
	  else if (ms_int_pnd) begin
	    iir[3:1] <= #(1) 3'b0;
	    iir[0] <= #(1) 1'b0;
	  end
	  else
	    begin
	      iir[3:1] <= #(1) 0;
	      iir[0] <= #(1) 1'b1;
	    end
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_receiver.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core receiver logic                                    ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_receiver.v,v $
// Revision 1.31  2004/06/18 14:46:15  tadejm
// Brandl Tobias repaired a bug regarding frame error in receiver when brake is received.
//
// Revision 1.29  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.28  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.27  2001/12/30 20:39:13  mohor
// More than one character was stored in case of break. End of the break
// was not detected correctly.
//
// Revision 1.26  2001/12/20 13:28:27  mohor
// Missing declaration of rf_push_q fixed.
//
// Revision 1.25  2001/12/20 13:25:46  mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.24  2001/12/19 08:03:34  mohor
// Warnings cleared.
//
// Revision 1.23  2001/12/19 07:33:54  mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.22  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.21  2001/12/13 10:31:16  mohor
// timeout irq must be set regardless of the rda irq (rda irq does not reset the
// timeout counter).
//
// Revision 1.20  2001/12/10 19:52:05  gorban
// Igor fixed break condition bugs
//
// Revision 1.19  2001/12/06 14:51:04  gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.18  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.17  2001/11/28 19:36:39  gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.16  2001/11/27 22:17:09  gorban
// Fixed bug that prevented synthesis in uart_receiver.v
//
// Revision 1.15  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.14  2001/11/10 12:43:21  gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.13  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11  2001/10/31 15:19:22  gorban
// Fixes to break and timeout conditions
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5  2001/06/02 14:28:14  gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.1  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:11+02  jacob
// Initial revision
//
//

`timescale 1 ns / 10 ps

module uart_receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, counter_t, 
	rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, 
	rstate, rf_push_pulse);

	parameter		sr_idle		= 4'b0;
	parameter		sr_rec_start	= 4'b1;
	parameter		sr_rec_bit	= 4'd2;
	parameter		sr_rec_parity	= 4'd3;
	parameter		sr_rec_stop	= 4'd4;
	parameter		sr_check_parity	= 4'd5;
	parameter		sr_rec_prepare	= 4'd6;
	parameter		sr_end_bit	= 4'd7;
	parameter		sr_ca_lc_parity	= 4'd8;
	parameter		sr_wait1	= 4'd9;
	parameter		sr_push		= 4'd10;

	input			clk;
	input			wb_rst_i;
	input	[7:0]		lcr;
	input			rf_pop;
	input			srx_pad_i;
	input			enable;
	input			rx_reset;
	input			lsr_mask;
	output	[9:0]		counter_t;
	output	[(5 - 1):0]	rf_count;
	output	[(11 - 1):0]	rf_data_out;
	output			rf_overrun;
	output			rf_error_bit;
	output	[3:0]		rstate;
	output			rf_push_pulse;

	reg	[3:0]		rcounter16;
	reg	[2:0]		rbit_counter;
	reg	[7:0]		rshift;
	reg			rparity;
	reg			rparity_error;
	reg			rframing_error;
	reg			rbit_in;
	reg			rparity_xor;
	reg	[7:0]		counter_b;
	reg			rf_push_q;
	reg	[(11 - 1):0]	rf_data_in;
	reg			rf_push;
	wire			break_error = (counter_b == 0);
	wire			rcounter16_eq_7 = (rcounter16 == 4'd7);
	wire			rcounter16_eq_0 = (rcounter16 == 4'b0);
	wire			rcounter16_eq_1 = (rcounter16 == 4'b1);
	wire	[3:0]		rcounter16_minus_1 = (rcounter16 - 1'b1);
	reg	[9:0]		toc_value;
	wire	[7:0]		brc_value;
	reg	[9:0]		counter_t;
	reg	[3:0]		rstate;

	assign rf_push_pulse = (rf_push & (~rf_push_q));
	assign brc_value = toc_value[9:2];

	uart_rfifo #(11) fifo_rx(
		.clk				(clk), 
		.wb_rst_i			(wb_rst_i), 
		.data_in			(rf_data_in), 
		.data_out			(rf_data_out), 
		.push				(rf_push_pulse), 
		.pop				(rf_pop), 
		.overrun			(rf_overrun), 
		.count				(rf_count), 
		.error_bit			(rf_error_bit), 
		.fifo_reset			(rx_reset), 
		.reset_status			(lsr_mask));

	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    rstate <= #(1) sr_idle;
	    rbit_in <= #(1) 1'b0;
	    rcounter16 <= #(1) 0;
	    rbit_counter <= #(1) 0;
	    rparity_xor <= #(1) 1'b0;
	    rframing_error <= #(1) 1'b0;
	    rparity_error <= #(1) 1'b0;
	    rparity <= #(1) 1'b0;
	    rshift <= #(1) 0;
	    rf_push <= #(1) 1'b0;
	    rf_data_in <= #(1) 0;
	  end
	  else if (enable) begin
	    case (rstate)
	      sr_idle: begin
		rf_push <= #(1) 1'b0;
		rf_data_in <= #(1) 0;
		rcounter16 <= #(1) 4'b1110;
		if ((srx_pad_i == 1'b0) & (~break_error)) begin
		  rstate <= #(1) sr_rec_start;
		end
	      end
	      sr_rec_start: begin
		rf_push <= #(1) 1'b0;
		if (rcounter16_eq_7) begin
		  if (srx_pad_i == 1'b1) begin
		    rstate <= #(1) sr_idle;
		  end
		  else begin
		    rstate <= #(1) sr_rec_prepare;
		  end
		end
		rcounter16 <= #(1) rcounter16_minus_1;
	      end
	      sr_rec_prepare: begin
		case (lcr[1:0])
		  2'b0:
		    rbit_counter <= #(1) 3'd4;
		  2'b1:
		    rbit_counter <= #(1) 3'd5;
		  2'b10:
		    rbit_counter <= #(1) 3'd6;
		  2'b11:
		    rbit_counter <= #(1) 3'd7;
		endcase
		if (rcounter16_eq_0) begin
		  rstate <= #(1) sr_rec_bit;
		  rcounter16 <= #(1) 4'b1110;
		  rshift <= #(1) 0;
		end
		else begin
		  rstate <= #(1) sr_rec_prepare;
		end
		rcounter16 <= #(1) rcounter16_minus_1;
	      end
	      sr_rec_bit: begin
		if (rcounter16_eq_0) begin
		  rstate <= #(1) sr_end_bit;
		end
		if (rcounter16_eq_7) begin
		  case (lcr[1:0])
		    2'b0:
		      rshift[4:0] <= #(1) {srx_pad_i, rshift[4:1]};
		    2'b1:
		      rshift[5:0] <= #(1) {srx_pad_i, rshift[5:1]};
		    2'b10:
		      rshift[6:0] <= #(1) {srx_pad_i, rshift[6:1]};
		    2'b11:
		      rshift[7:0] <= #(1) {srx_pad_i, rshift[7:1]};
		  endcase
		end
		rcounter16 <= #(1) rcounter16_minus_1;
	      end
	      sr_end_bit: begin
		if (rbit_counter == 3'b0) begin
		  if (lcr[3]) begin
		    rstate <= #(1) sr_rec_parity;
		  end
		  else
		    begin
		      rstate <= #(1) sr_rec_stop;
		      rparity_error <= #(1) 1'b0;
		    end
		end
		else
		  begin
		    rstate <= #(1) sr_rec_bit;
		    rbit_counter <= #(1) (rbit_counter - 1'b1);
		  end
		rcounter16 <= #(1) 4'b1110;
	      end
	      sr_rec_parity: begin
		if (rcounter16_eq_7) begin
		  rparity <= #(1) srx_pad_i;
		  rstate <= #(1) sr_ca_lc_parity;
		end
		rcounter16 <= #(1) rcounter16_minus_1;
	      end
	      sr_ca_lc_parity: begin
		rcounter16 <= #(1) rcounter16_minus_1;
		rparity_xor <= #(1) (^{rshift, rparity});
		rstate <= #(1) sr_check_parity;
	      end
	      sr_check_parity: begin
		case ({lcr[4], lcr[5]})
		  2'b0:
		    rparity_error <= #(1) (rparity_xor == 0);
		  2'b1:
		    rparity_error <= #(1) (~rparity);
		  2'b10:
		    rparity_error <= #(1) (rparity_xor == 1);
		  2'b11:
		    rparity_error <= #(1) rparity;
		endcase
		rcounter16 <= #(1) rcounter16_minus_1;
		rstate <= #(1) sr_wait1;
	      end
	      sr_wait1:
		if (rcounter16_eq_0) begin
		  rstate <= #(1) sr_rec_stop;
		  rcounter16 <= #(1) 4'b1110;
		end
		else begin
		  rcounter16 <= #(1) rcounter16_minus_1;
		end
	      sr_rec_stop: begin
		if (rcounter16_eq_7) begin
		  rframing_error <= #(1) (!srx_pad_i);
		  rstate <= #(1) sr_push;
		end
		rcounter16 <= #(1) rcounter16_minus_1;
	      end
	      sr_push: begin
		if (srx_pad_i | break_error) begin
		  if (break_error) begin
		    rf_data_in <= #(1) {8'b0, 3'd4};
		  end
		  else begin
		    rf_data_in <= #(1) {rshift, 1'b0, rparity_error, 
			    rframing_error};
		  end
		  rf_push <= #(1) 1'b1;
		  rstate <= #(1) sr_idle;
		end
		else if (~rframing_error) begin
		  rf_data_in <= #(1) {rshift, 1'b0, rparity_error, 
			  rframing_error};
		  rf_push <= #(1) 1'b1;
		  rcounter16 <= #(1) 4'b1110;
		  rstate <= #(1) sr_rec_start;
		end
	      end
	      default:
		rstate <= #(1) sr_idle;
	    endcase
	  end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    rf_push_q <= 0;
	  end
	  else begin
	    rf_push_q <= #(1) rf_push;
	  end
	end
	always @(lcr) case (lcr[3:0])
	  4'b0:
	    toc_value = 447;
	  4'd4:
	    toc_value = 479;
	  4'b1, 4'd8:
	    toc_value = 511;
	  4'b1100:
	    toc_value = 543;
	  4'd2, 4'd5, 4'd9:
	    toc_value = 575;
	  4'd3, 4'd6, 4'd10, 4'b1101:
	    toc_value = 639;
	  4'd7, 4'b1011, 4'b1110:
	    toc_value = 703;
	  4'b1111:
	    toc_value = 767;
	endcase
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    counter_b <= #(1) 8'd159;
	  end
	  else if (srx_pad_i) begin
	    counter_b <= #(1) brc_value;
	  end
	  else if (enable & (counter_b != 8'b0)) begin
	    counter_b <= #(1) (counter_b - 1);
	  end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    counter_t <= #(1) 10'd639;
	  end
	  else if ((rf_push_pulse || rf_pop) || (rf_count == 0)) begin
	    counter_t <= #(1) toc_value;
	  end
	  else if (enable && (counter_t != 10'b0)) begin
	    counter_t <= #(1) (counter_t - 1);
	  end
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_rfifo.v (Modified from uart_fifo.v)                    ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core receiver FIFO                                     ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2002/07/22                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_rfifo.v,v $
// Revision 1.4  2003/07/11 18:20:26  gorban
// added clearing the receiver fifo statuses on resets
//
// Revision 1.3  2003/06/11 16:37:47  gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.2  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16  2001/12/20 13:25:46  mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15  2001/12/18 09:01:07  mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/24 08:48:10  mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:48  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//
`timescale 1 ns / 10 ps
module uart_rfifo(clk, wb_rst_i, data_in, data_out, push, pop, overrun, count, 
	error_bit, fifo_reset, reset_status);

	parameter		fifo_width	= 8;
	parameter		fifo_depth	= 16;
	parameter		fifo_pointer_w	= 4;
	parameter		fifo_counter_w	= 5;

	input			clk;
	input			wb_rst_i;
	input			push;
	input			pop;
	input	[(fifo_width - 1):0]
				data_in;
	input			fifo_reset;
	input			reset_status;
	output	[(fifo_width - 1):0]
				data_out;
	output			overrun;
	output	[(fifo_counter_w - 1):0]
				count;
	output			error_bit;

	wire	[7:0]		data8_out;

	reg	[2:0]		fifo[(fifo_depth - 1):0];
	reg	[(fifo_pointer_w - 1):0]
				top;
	reg	[(fifo_pointer_w - 1):0]
				bottom;
	reg			overrun;
	reg	[(fifo_counter_w - 1):0]
				count;
	wire	[(fifo_pointer_w - 1):0]
				top_plus_1 = (top + 1'b1);
	wire	[2:0]		word0 = fifo[0];
	wire	[2:0]		word1 = fifo[1];
	wire	[2:0]		word2 = fifo[2];
	wire	[2:0]		word3 = fifo[3];
	wire	[2:0]		word4 = fifo[4];
	wire	[2:0]		word5 = fifo[5];
	wire	[2:0]		word6 = fifo[6];
	wire	[2:0]		word7 = fifo[7];
	wire	[2:0]		word8 = fifo[8];
	wire	[2:0]		word9 = fifo[9];
	wire	[2:0]		word10 = fifo[10];
	wire	[2:0]		word11 = fifo[11];
	wire	[2:0]		word12 = fifo[12];
	wire	[2:0]		word13 = fifo[13];
	wire	[2:0]		word14 = fifo[14];
	wire	[2:0]		word15 = fifo[15];

	assign data_out = {data8_out, fifo[bottom]};
	assign error_bit = (|(((((((((((((((word0[2:0] | word1[2:0]) | 
		word2[2:0]) | word3[2:0]) | word4[2:0]) | word5[2:0]) | 
		word6[2:0]) | word7[2:0]) | word8[2:0]) | word9[2:0]) | 
		word10[2:0]) | word11[2:0]) | word12[2:0]) | word13[2:0]) | 
		word14[2:0]) | word15[2:0]));

	raminfr #(fifo_pointer_w, 8, fifo_depth) rfifo(
		.clk				(clk), 
		.we				(push), 
		.a				(top), 
		.dpra				(bottom), 
		.di				(data_in[(fifo_width -
		1):(fifo_width - 8)]), 
		.dpo				(data8_out));

	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    top <= #(1) 0;
	    bottom <= #(1) 1'b0;
	    count <= #(1) 0;
	    fifo[0] <= #(1) 0;
	    fifo[1] <= #(1) 0;
	    fifo[2] <= #(1) 0;
	    fifo[3] <= #(1) 0;
	    fifo[4] <= #(1) 0;
	    fifo[5] <= #(1) 0;
	    fifo[6] <= #(1) 0;
	    fifo[7] <= #(1) 0;
	    fifo[8] <= #(1) 0;
	    fifo[9] <= #(1) 0;
	    fifo[10] <= #(1) 0;
	    fifo[11] <= #(1) 0;
	    fifo[12] <= #(1) 0;
	    fifo[13] <= #(1) 0;
	    fifo[14] <= #(1) 0;
	    fifo[15] <= #(1) 0;
	  end
	  else if (fifo_reset) begin
	    top <= #(1) 0;
	    bottom <= #(1) 1'b0;
	    count <= #(1) 0;
	    fifo[0] <= #(1) 0;
	    fifo[1] <= #(1) 0;
	    fifo[2] <= #(1) 0;
	    fifo[3] <= #(1) 0;
	    fifo[4] <= #(1) 0;
	    fifo[5] <= #(1) 0;
	    fifo[6] <= #(1) 0;
	    fifo[7] <= #(1) 0;
	    fifo[8] <= #(1) 0;
	    fifo[9] <= #(1) 0;
	    fifo[10] <= #(1) 0;
	    fifo[11] <= #(1) 0;
	    fifo[12] <= #(1) 0;
	    fifo[13] <= #(1) 0;
	    fifo[14] <= #(1) 0;
	    fifo[15] <= #(1) 0;
	  end
	  else
	    begin
	      case ({push, pop})
		2'b10:
		  if (count < fifo_depth) begin
		    top <= #(1) top_plus_1;
		    fifo[top] <= #(1) data_in[2:0];
		    count <= #(1) (count + 1'b1);
		  end
		2'b1:
		  if (count > 0) begin
		    fifo[bottom] <= #(1) 0;
		    bottom <= #(1) (bottom + 1'b1);
		    count <= #(1) (count - 1'b1);
		  end
		2'b11: begin
		  bottom <= #(1) (bottom + 1'b1);
		  top <= #(1) top_plus_1;
		  fifo[top] <= #(1) data_in[2:0];
		end
		default:
		  ;
	      endcase
	    end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    overrun <= #(1) 1'b0;
	  end
	  else if (fifo_reset | reset_status) begin
	    overrun <= #(1) 1'b0;
	  end
	  else if ((push & (~pop)) & (count == fifo_depth)) begin
	    overrun <= #(1) 1'b1;
	  end
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_sync_flops.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core receiver logic                                    ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Andrej Erzen (andreje@flextronics.si)                 ////
////      - Tadej Markovic (tadejm@flextronics.si)                ////
////                                                              ////
////  Created:        2004/05/20                                  ////
////  Last Updated:   2004/05/20                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_sync_flops.v,v $
// Revision 1.1  2004/05/21 11:43:25  tadejm
// Added to synchronize RX input to Wishbone clock.
//
//

`timescale 1 ns / 10 ps
module uart_sync_flops(rst_i, clk_i, stage1_rst_i, stage1_clk_en_i, async_dat_i,
	sync_dat_o);

	parameter		Tp		= 1;
	parameter		width		= 1;
	parameter		init_value	= 1'b0;

	input			rst_i;
	input			clk_i;
	input			stage1_rst_i;
	input			stage1_clk_en_i;
	input	[(width - 1):0]	async_dat_i;
	output	[(width - 1):0]	sync_dat_o;

	reg	[(width - 1):0]	sync_dat_o;
	reg	[(width - 1):0]	flop_0;

	always @(posedge clk_i or posedge rst_i) begin
	  if (rst_i) begin
	    flop_0 <= #(Tp) {width {init_value}};
	  end
	  else begin
	    flop_0 <= #(Tp) async_dat_i;
	  end
	end
	always @(posedge clk_i or posedge rst_i) begin
	  if (rst_i) begin
	    sync_dat_o <= #(Tp) {width {init_value}};
	  end
	  else if (stage1_rst_i) begin
	    sync_dat_o <= #(Tp) {width {init_value}};
	  end
	  else if (stage1_clk_en_i) begin
	    sync_dat_o <= #(Tp) flop_0;
	  end
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_tfifo.v                                                ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter FIFO                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2002/07/22                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_tfifo.v,v $
// Revision 1.2  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16  2001/12/20 13:25:46  mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15  2001/12/18 09:01:07  mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/24 08:48:10  mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:48  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//

`timescale 1 ns / 10 ps
module uart_tfifo(clk, wb_rst_i, data_in, data_out, push, pop, overrun, count, 
	fifo_reset, reset_status);

	parameter		fifo_width	= 8;
	parameter		fifo_depth	= 16;
	parameter		fifo_pointer_w	= 4;
	parameter		fifo_counter_w	= 5;

	input			clk;
	input			wb_rst_i;
	input			push;
	input			pop;
	input	[(fifo_width - 1):0]
				data_in;
	input			fifo_reset;
	input			reset_status;
	output	[(fifo_width - 1):0]
				data_out;
	output			overrun;
	output	[(fifo_counter_w - 1):0]
				count;

	reg	[(fifo_pointer_w - 1):0]
				top;
	reg	[(fifo_pointer_w - 1):0]
				bottom;
	reg			overrun;
	reg	[(fifo_counter_w - 1):0]
				count;
	wire	[(fifo_pointer_w - 1):0]
				top_plus_1 = (top + 1'b1);


	raminfr #(fifo_pointer_w, fifo_width, fifo_depth) tfifo(
		.clk				(clk), 
		.we				(push), 
		.a				(top), 
		.dpra				(bottom), 
		.di				(data_in), 
		.dpo				(data_out));

	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    top <= #(1) 0;
	    bottom <= #(1) 1'b0;
	    count <= #(1) 0;
	  end
	  else if (fifo_reset) begin
	    top <= #(1) 0;
	    bottom <= #(1) 1'b0;
	    count <= #(1) 0;
	  end
	  else
	    begin
	      case ({push, pop})
		2'b10:
		  if (count < fifo_depth) begin
		    top <= #(1) top_plus_1;
		    count <= #(1) (count + 1'b1);
		  end
		2'b1:
		  if (count > 0) begin
		    bottom <= #(1) (bottom + 1'b1);
		    count <= #(1) (count - 1'b1);
		  end
		2'b11: begin
		  bottom <= #(1) (bottom + 1'b1);
		  top <= #(1) top_plus_1;
		end
		default:
		  ;
	      endcase
	    end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    overrun <= #(1) 1'b0;
	  end
	  else if (fifo_reset | reset_status) begin
	    overrun <= #(1) 1'b0;
	  end
	  else if (push & (count == fifo_depth)) begin
	    overrun <= #(1) 1'b1;
	  end
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_top.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core top level.                                        ////
////                                                              ////
////  Known problems (limits):                                    ////
////  Note that transmitter and receiver instances are inside     ////
////  the uart_regs.v file.                                       ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing so far.                                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_top.v,v $
// Revision 1.19  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.18  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.17  2001/12/19 08:40:03  mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.16  2001/12/06 14:51:04  gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.15  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.14  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.13  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.12  2001/08/25 15:46:19  gorban
// Modified port names again
//
// Revision 1.11  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.10  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//

`timescale 1 ns / 10 ps
module uart_top(wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, 
	wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, int_o, stx_pad_o, srx_pad_i, 
	rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i, baud_o)
	;

	parameter		uart_data_width	= 8;
	parameter		uart_addr_width	= 3;

	input			wb_clk_i;
	input			wb_rst_i;
	input	[(uart_addr_width - 1):0]
				wb_adr_i;
	input	[(uart_data_width - 1):0]
				wb_dat_i;
	output	[(uart_data_width - 1):0]
				wb_dat_o;
	input			wb_we_i;
	input			wb_stb_i;
	input			wb_cyc_i;
	input	[3:0]		wb_sel_i;
	output			wb_ack_o;
	output			int_o;
	input			srx_pad_i;
	output			stx_pad_o;
	output			rts_pad_o;
	input			cts_pad_i;
	output			dtr_pad_o;
	input			dsr_pad_i;
	input			ri_pad_i;
	input			dcd_pad_i;
	output			baud_o;

	wire	[7:0]		wb_dat8_i;
	wire	[7:0]		wb_dat8_o;
	wire	[31:0]		wb_dat32_o;
	wire	[(uart_addr_width - 1):0]
				wb_adr_int;
	wire			we_o;
	wire			re_o;

	uart_wb wb_interface(
		.clk				(wb_clk_i), 
		.wb_rst_i			(wb_rst_i), 
		.wb_dat_i			(wb_dat_i), 
		.wb_dat_o			(wb_dat_o), 
		.wb_dat8_i			(wb_dat8_i), 
		.wb_dat8_o			(wb_dat8_o), 
		.wb_dat32_o			(32'b0), 
		.wb_sel_i			(4'b0), 
		.wb_we_i			(wb_we_i), 
		.wb_stb_i			(wb_stb_i), 
		.wb_cyc_i			(wb_cyc_i), 
		.wb_ack_o			(wb_ack_o), 
		.wb_adr_i			(wb_adr_i), 
		.wb_adr_int			(wb_adr_int), 
		.we_o				(we_o), 
		.re_o				(re_o));
	uart_regs regs(
		.clk				(wb_clk_i), 
		.wb_rst_i			(wb_rst_i), 
		.wb_addr_i			(wb_adr_int), 
		.wb_dat_i			(wb_dat8_i), 
		.wb_dat_o			(wb_dat8_o), 
		.wb_we_i			(we_o), 
		.wb_re_i			(re_o), 
		.modem_inputs			({cts_pad_i, dsr_pad_i,
		ri_pad_i, dcd_pad_i}), 
		.stx_pad_o			(stx_pad_o), 
		.srx_pad_i			(srx_pad_i), 
		.rts_pad_o			(rts_pad_o), 
		.dtr_pad_o			(dtr_pad_o), 
		.int_o				(int_o), 
		.baud_o				(baud_o));

	initial begin
	  $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n")
		  ;
	  $display("(%m) UART INFO: Has baudrate output\n");
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_transmitter.v                                          ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter logic                                 ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_transmitter.v,v $
// Revision 1.19  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.18  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16  2002/01/08 11:29:40  mohor
// tf_pop was too wide. Now it is only 1 clk cycle width.
//
// Revision 1.15  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.14  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.13  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11  2001/10/29 17:00:46  gorban
// fixed parity sending and tx_fifo resets over- and underrun
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6  2001/06/23 11:21:48  gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5  2001/06/02 14:28:14  gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:49  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.1  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//


`timescale 1 ns / 10 ps
module uart_transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, 
	stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);

	parameter		s_idle		= 3'b0;
	parameter		s_send_start	= 3'b1;
	parameter		s_send_byte	= 3'd2;
	parameter		s_send_parity	= 3'd3;
	parameter		s_send_stop	= 3'd4;
	parameter		s_pop_byte	= 3'd5;

	input			clk;
	input			wb_rst_i;
	input	[7:0]		lcr;
	input			tf_push;
	input	[7:0]		wb_dat_i;
	input			enable;
	input			tx_reset;
	input			lsr_mask;
	output			stx_pad_o;
	output	[2:0]		tstate;
	output	[(5 - 1):0]	tf_count;

	reg	[4:0]		counter;
	reg	[2:0]		bit_counter;
	reg	[6:0]		shift_out;
	reg			stx_o_tmp;
	reg			parity_xor;
	reg			tf_pop;
	reg			bit_out;
	reg	[(8 - 1):0]	tf_data_in;
	wire	[(8 - 1):0]	tf_data_out;
	reg	[2:0]		tstate;
	wire			tf_overrun;

	assign stx_pad_o = (lcr[6] ? 1'b0 : stx_o_tmp);

	uart_tfifo fifo_tx(
		.clk				(clk), 
		.wb_rst_i			(wb_rst_i), 
		.data_in			(tf_data_in), 
		.data_out			(tf_data_out), 
		.push				(tf_push), 
		.pop				(tf_pop), 
		.overrun			(tf_overrun), 
		.count				(tf_count), 
		.fifo_reset			(tx_reset), 
		.reset_status			(lsr_mask));

	always @(posedge clk) tf_data_in <= wb_dat_i;
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    tstate <= #(1) s_idle;
	    stx_o_tmp <= #(1) 1'b1;
	    counter <= #(1) 5'b0;
	    shift_out <= #(1) 7'b0;
	    bit_out <= #(1) 1'b0;
	    parity_xor <= #(1) 1'b0;
	    tf_pop <= #(1) 1'b0;
	    bit_counter <= #(1) 3'b0;
	  end
	  else if (enable) begin
	    case (tstate)
	      s_idle:
		if (~|tf_count) begin
		  tstate <= #(1) s_idle;
		  stx_o_tmp <= #(1) 1'b1;
		end
		else
		  begin
		    tf_pop <= #(1) 1'b0;
		    stx_o_tmp <= #(1) 1'b1;
		    tstate <= #(1) s_pop_byte;
		  end
	      s_pop_byte: begin
		tf_pop <= #(1) 1'b1;
		case (lcr[1:0])
		  2'b0: begin
		    bit_counter <= #(1) 3'd4;
		    parity_xor <= #(1) (^tf_data_out[4:0]);
		  end
		  2'b1: begin
		    bit_counter <= #(1) 3'd5;
		    parity_xor <= #(1) (^tf_data_out[5:0]);
		  end
		  2'b10: begin
		    bit_counter <= #(1) 3'd6;
		    parity_xor <= #(1) (^tf_data_out[6:0]);
		  end
		  2'b11: begin
		    bit_counter <= #(1) 3'd7;
		    parity_xor <= #(1) (^tf_data_out[7:0]);
		  end
		endcase
		{shift_out[6:0], bit_out} <= #(1) tf_data_out;
		tstate <= #(1) s_send_start;
	      end
	      s_send_start: begin
		tf_pop <= #(1) 1'b0;
		if (~|counter) begin
		  counter <= #(1) 5'b01111;
		end
		else if (counter == 5'b1) begin
		  counter <= #(1) 0;
		  tstate <= #(1) s_send_byte;
		end
		else begin
		  counter <= #(1) (counter - 1'b1);
		end
		stx_o_tmp <= #(1) 1'b0;
	      end
	      s_send_byte: begin
		if (~|counter) begin
		  counter <= #(1) 5'b01111;
		end
		else if (counter == 5'b1) begin
		  if (bit_counter > 3'b0) begin
		    bit_counter <= #(1) (bit_counter - 1'b1);
		    {shift_out[5:0], bit_out} <= #(1) {shift_out[6:1], 
			    shift_out[0]};
		    tstate <= #(1) s_send_byte;
		  end
		  else if (~lcr[3]) begin
		    tstate <= #(1) s_send_stop;
		  end
		  else
		    begin
		      case ({lcr[4], lcr[5]})
			2'b0:
			  bit_out <= #(1) (~parity_xor);
			2'b1:
			  bit_out <= #(1) 1'b1;
			2'b10:
			  bit_out <= #(1) parity_xor;
			2'b11:
			  bit_out <= #(1) 1'b0;
		      endcase
		      tstate <= #(1) s_send_parity;
		    end
		  counter <= #(1) 0;
		end
		else begin
		  counter <= #(1) (counter - 1'b1);
		end
		stx_o_tmp <= #(1) bit_out;
	      end
	      s_send_parity: begin
		if (~|counter) begin
		  counter <= #(1) 5'b01111;
		end
		else if (counter == 5'b1) begin
		  counter <= #(1) 4'b0;
		  tstate <= #(1) s_send_stop;
		end
		else begin
		  counter <= #(1) (counter - 1'b1);
		end
		stx_o_tmp <= #(1) bit_out;
	      end
	      s_send_stop: begin
		if (~|counter) begin
		  casex ({lcr[2], lcr[1:0]})
		    3'b0xx:
		      counter <= #(1) 5'b01101;
		    3'd4:
		      counter <= #(1) 5'b10101;
		    default:
		      counter <= #(1) 5'b11101;
		  endcase
		end
		else if (counter == 5'b1) begin
		  counter <= #(1) 0;
		  tstate <= #(1) s_idle;
		end
		else begin
		  counter <= #(1) (counter - 1'b1);
		end
		stx_o_tmp <= #(1) 1'b1;
	      end
	      default:
		tstate <= #(1) s_idle;
	    endcase
	  end
	  else begin
	    tf_pop <= #(1) 1'b0;
	  end
	end
endmodule
//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_wb.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core WISHBONE interface.                               ////
////                                                              ////
////  Known problems (limits):                                    ////
////  Inserts one wait state on all transfers.                    ////
////  Note affected signals and the way they are affected.        ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_wb.v,v $
// Revision 1.17  2004/05/21 12:35:15  tadejm
// Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.
//
// Revision 1.16  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.15  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.12  2001/12/19 08:03:34  mohor
// Warnings cleared.
//
// Revision 1.11  2001/12/06 14:51:04  gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.10  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.8  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/21 19:12:01  gorban
// Corrected some Linter messages.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:13+02  jacob
// Initial revision
//
//

// UART core WISHBONE interface 
//
// Author: Jacob Gorban   (jacob.gorban@flextronicssemi.com)
// Company: Flextronics Semiconductor
//

`timescale 1 ns / 10 ps
module uart_wb(clk, wb_rst_i, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, 
	wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, 
	wb_sel_i, we_o, re_o);

	input			clk;
	input			wb_rst_i;
	input			wb_we_i;
	input			wb_stb_i;
	input			wb_cyc_i;
	input	[3:0]		wb_sel_i;
	input	[(3 - 1):0]	wb_adr_i;
	input	[7:0]		wb_dat_i;
	output	[7:0]		wb_dat_o;
	output	[(3 - 1):0]	wb_adr_int;
	input	[7:0]		wb_dat8_o;
	output	[7:0]		wb_dat8_i;
	input	[31:0]		wb_dat32_o;
	output			wb_ack_o;
	output			we_o;
	output			re_o;

	reg	[7:0]		wb_dat_is;
	reg	[(3 - 1):0]	wb_adr_is;
	reg			wb_we_is;
	reg			wb_cyc_is;
	reg			wb_stb_is;
	reg	[3:0]		wb_sel_is;
	reg	[7:0]		wb_dat_o;
	reg	[7:0]		wb_dat8_i;
	reg			wb_ack_o;
	reg			wre;
	reg	[1:0]		wbstate;

	assign we_o = (wb_we_is & wb_ack_o);
	assign re_o = ((((~wb_we_is) & wb_stb_is) & wb_cyc_is) & wre);
	assign wb_adr_int = wb_adr_is;

	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  wb_ack_o <= #(1) 1'b0;
	  wbstate <= #(1) 0;
	  wre <= #(1) 1'b1;
	end
	else begin
	  case (wbstate)
	    0: begin
	      if (wb_stb_is & wb_cyc_is) begin
		wre <= #(1) 0;
		wbstate <= #(1) 1;
		wb_ack_o <= #(1) 1;
	      end
	      else
		begin
		  wre <= #(1) 1;
		  wb_ack_o <= #(1) 0;
		end
	    end
	    1: begin
	      wb_ack_o <= #(1) 0;
	      wbstate <= #(1) 2;
	      wre <= #(1) 0;
	    end
	    2, 3: begin
	      wb_ack_o <= #(1) 0;
	      wbstate <= #(1) 0;
	      wre <= #(1) 0;
	    end
	  endcase
	end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  wb_adr_is <= #(1) 0;
	  wb_we_is <= #(1) 0;
	  wb_cyc_is <= #(1) 0;
	  wb_stb_is <= #(1) 0;
	  wb_dat_is <= #(1) 0;
	  wb_sel_is <= #(1) 0;
	end
	else
	  begin
	    wb_adr_is <= #(1) wb_adr_i;
	    wb_we_is <= #(1) wb_we_i;
	    wb_cyc_is <= #(1) wb_cyc_i;
	    wb_stb_is <= #(1) wb_stb_i;
	    wb_dat_is <= #(1) wb_dat_i;
	    wb_sel_is <= #(1) wb_sel_i;
	  end
	always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin
	  wb_dat_o <= #(1) 0;
	end
	else begin
	  wb_dat_o <= #(1) wb_dat8_o;
	end
	always @(wb_dat_is) wb_dat8_i = wb_dat_is;
endmodule
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: l2_dir.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`timescale 1 ns / 10 ps
module l2_dir(clk, reset, pa_in, index, pa_wr, val, way_hit, dir_hit_way_enc, 
	rd_en);

	input			clk;
	input			reset;
	input			rd_en;
	input			val;
	input	[27:0]		pa_in;
	input	[3:0]		pa_wr;
	input	[6:0]		index;
	output	[3:0]		way_hit;
	output	[1:0]		dir_hit_way_enc;

	reg	[27:0]		dta_way0[127:0];
	reg	[27:0]		dta_way1[127:0];
	reg	[27:0]		dta_way2[127:0];
	reg	[27:0]		dta_way3[127:0];

	reg	[127:0]		valid_w0;
	reg	[127:0]		valid_w1;
	reg	[127:0]		valid_w2;
	reg	[127:0]		valid_w3;
	wire	[3:0]		wr_way_d = pa_wr;
	reg	[3:0]		way_hit_r;
	wire	[6:0]		index_y_d = index;
	wire	[27:0]		wrtag_y = pa_in;
	reg	[3:0]		squash;
	reg			mult;
	reg			dbg_en;
	reg			dbg_en2;
	reg	[3:0]		wr_way_d_d;
	reg	[3:0]		wr_way_d_d_d;

	assign dir_hit_way_enc = (way_hit[0] ? 0 : (way_hit[1] ? 1 : (way_hit[2]
		? 2 : 3)));
	assign way_hit = way_hit_r;

	always @(posedge clk) begin
	  if (reset) begin
	    valid_w0 <= 0;
	    valid_w1 <= 0;
	    valid_w2 <= 0;
	    valid_w3 <= 0;
	  end
	  else
	    begin
	      if (wr_way_d[0] | squash[0]) begin
		valid_w0[index_y_d] <= (val & (~squash[0]));
	      end
	      if (wr_way_d[1] | squash[1]) begin
		valid_w1[index_y_d] <= (val & (~squash[1]));
	      end
	      if (wr_way_d[2] | squash[2]) begin
		valid_w2[index_y_d] <= (val & (~squash[2]));
	      end
	      if (wr_way_d[3] | squash[3]) begin
		valid_w3[index_y_d] <= (val & (~squash[3]));
	      end
	    end
	end
	always @(posedge clk) begin
	  wr_way_d_d <= wr_way_d;
	  wr_way_d_d_d <= wr_way_d_d;
	  if ((((way_hit_r[0] + way_hit_r[1]) + way_hit_r[2]) + way_hit_r[3]) > 
		  1) begin
	    mult <= 1;
	  end
	  else
	    begin
	      mult <= 0;
	    end
	  if (((((way_hit_r[0] + way_hit_r[1]) + way_hit_r[2]) + way_hit_r[3]) >
		  1) & (|wr_way_d_d_d)) begin
	    squash <= (way_hit_r & (~wr_way_d_d_d));
	  end
	  else
	    begin
	      squash <= 4'b0;
	    end
	  way_hit_r <= {((dta_way3[index_y_d[6:0]] == pa_in) &
		  valid_w3[index_y_d]), ((dta_way2[index_y_d[6:0]] == pa_in) &
		  valid_w2[index_y_d]), ((dta_way1[index_y_d[6:0]] == pa_in) &
		  valid_w1[index_y_d]), ((dta_way0[index_y_d[6:0]] == pa_in) &
		  valid_w0[index_y_d])};
	  if (wr_way_d[0]) begin
	    dta_way0[index_y_d[6:0]] <= wrtag_y;
	  end
	  if (wr_way_d[1]) begin
	    dta_way1[index_y_d[6:0]] <= wrtag_y;
	  end
	  if (wr_way_d[2]) begin
	    dta_way2[index_y_d[6:0]] <= wrtag_y;
	  end
	  if (wr_way_d[3]) begin
	    dta_way3[index_y_d[6:0]] <= wrtag_y;
	  end
	end
endmodule
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: t2.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`timescale 1 ns / 100 ps
module t2(sys_interrupt_source_i , ccx_lstg_in, ccx_rstg_in, 
	cluster_arst_l,
	cpu_rep0_in, cpu_rep1_in,
	gclk, 
	sctag2_cpx_atom_cq, 
	sctag2_cpx_data_ca, sctag2_cpx_req_cq, sctag2_pcx_stall_pq, 
	sctag3_cpx_atom_cq, sctag3_cpx_data_ca, sctag3_cpx_req_cq, 
	sctag3_pcx_stall_pq, sctag4_cpx_atom_cq, sctag4_cpx_data_ca, 
	sctag4_cpx_req_cq, sctag4_pcx_stall_pq, sctag5_cpx_atom_cq, 
	sctag5_cpx_data_ca, sctag5_cpx_req_cq, sctag5_pcx_stall_pq, 
	sctag6_cpx_atom_cq, sctag6_cpx_data_ca, sctag6_cpx_req_cq, 
	sctag6_pcx_stall_pq, sctag7_cpx_atom_cq, sctag7_cpx_data_ca, 
	sctag7_cpx_req_cq, sctag7_pcx_stall_pq, spc1_pcx_atm_pq, 
	spc1_pcx_data_pa, spc1_pcx_req_pq, spc2_pcx_atm_pq, spc2_pcx_data_pa, 
	spc2_pcx_req_pq, spc3_pcx_atm_pq, spc3_pcx_data_pa, spc3_pcx_req_pq, 
	spc4_pcx_atm_pq, spc4_pcx_data_pa, spc4_pcx_req_pq, spc5_pcx_atm_pq, 
	spc5_pcx_data_pa, spc5_pcx_req_pq, spc6_pcx_atm_pq, spc6_pcx_data_pa, 
	spc6_pcx_req_pq, spc7_pcx_atm_pq, spc7_pcx_data_pa, spc7_pcx_req_pq, 
	tcu_aclk,
	wbm_ack_i0, wbm_ack_i1,
	wbm_ack_i8, wbm_data_i0, wbm_data_i1, wbm_data_i8, ccx_lstg_out, 
	ccx_rstg_out, cpu_rep0_out, cpu_rep1_out, cpx_io_grant_cx, 
	cpx_sctag0_grant_cx, cpx_sctag1_grant_cx, cpx_sctag2_grant_cx, 
	cpx_sctag3_grant_cx, cpx_sctag4_grant_cx, cpx_sctag5_grant_cx, 
	cpx_sctag6_grant_cx, cpx_sctag7_grant_cx, cpx_spc1_data_cx2, 
	cpx_spc2_data_cx2, cpx_spc3_data_cx2, cpx_spc4_data_cx2, 
	cpx_spc5_data_cx2, cpx_spc6_data_cx2, cpx_spc7_data_cx2, dmo_dout, 
	pcx_sctag2_atm_px1, pcx_sctag2_data_px2, pcx_sctag2_data_rdy_px1, 
	pcx_sctag3_atm_px1, pcx_sctag3_data_px2, pcx_sctag3_data_rdy_px1, 
	pcx_sctag4_atm_px1, pcx_sctag4_data_px2, pcx_sctag4_data_rdy_px1, 
	pcx_sctag5_atm_px1, pcx_sctag5_data_px2, pcx_sctag5_data_rdy_px1, 
	pcx_sctag6_atm_px1, pcx_sctag6_data_px2, pcx_sctag6_data_rdy_px1, 
	pcx_sctag7_atm_px1, pcx_sctag7_data_px2, pcx_sctag7_data_rdy_px1, 
	pcx_spc1_grant_px, pcx_spc2_grant_px, pcx_spc3_grant_px, 
	pcx_spc4_grant_px, pcx_spc5_grant_px, pcx_spc6_grant_px, 
	pcx_spc7_grant_px, scan_out, spc_core_running_status, 
	spc_dbg_instr_cmt_grp0, spc_dbg_instr_cmt_grp1, spc_efu_fuse_ddata, 
	spc_efu_fuse_dxfer_en, spc_efu_fuse_idata, spc_efu_fuse_ixfer_en, 
	spc_grant_o, spc_grant_o_8, spc_hardstop_request, spc_mbist_done, 
	spc_mbist_fail, spc_shscan_scan_out, spc_softstop_request, 
	spc_ss_complete, spc_tcu_lbist_done, spc_tcu_lbist_scan_out, 
	spc_tcu_mbist_scan_out, spc_trigger_pulse, wbm_addr_o0, wbm_addr_o1, 
	wbm_addr_o8, wbm_cycle_o0, wbm_cycle_o1, wbm_cycle_o8, wbm_data_o0, 
	wbm_data_o1, wbm_data_o8, wbm_sel_o0, wbm_sel_o1, wbm_sel_o8, 
	wbm_strobe_o0, wbm_strobe_o1, wbm_strobe_o8, wbm_we_o0, wbm_we_o1, 
	wbm_we_o8);

	input   [5:0]           sys_interrupt_source_i;


	input	[159:0]		ccx_lstg_in;
	input	[159:0]		ccx_rstg_in;
	input			cluster_arst_l;
	input	[191:0]		cpu_rep0_in;
	input	[191:0]		cpu_rep1_in;
	input			gclk;
	input			sctag2_cpx_atom_cq;
	input	[145:0]		sctag2_cpx_data_ca;
	input	[7:0]		sctag2_cpx_req_cq;
	input			sctag2_pcx_stall_pq;
	input			sctag3_cpx_atom_cq;
	input	[145:0]		sctag3_cpx_data_ca;
	input	[7:0]		sctag3_cpx_req_cq;
	input			sctag3_pcx_stall_pq;
	input			sctag4_cpx_atom_cq;
	input	[145:0]		sctag4_cpx_data_ca;
	input	[7:0]		sctag4_cpx_req_cq;
	input			sctag4_pcx_stall_pq;
	input			sctag5_cpx_atom_cq;
	input	[145:0]		sctag5_cpx_data_ca;
	input	[7:0]		sctag5_cpx_req_cq;
	input			sctag5_pcx_stall_pq;
	input			sctag6_cpx_atom_cq;
	input	[145:0]		sctag6_cpx_data_ca;
	input	[7:0]		sctag6_cpx_req_cq;
	input			sctag6_pcx_stall_pq;
	input			sctag7_cpx_atom_cq;
	input	[145:0]		sctag7_cpx_data_ca;
	input	[7:0]		sctag7_cpx_req_cq;
	input			sctag7_pcx_stall_pq;
	input	[8:0]		spc1_pcx_atm_pq;
	input	[129:0]		spc1_pcx_data_pa;
	input	[8:0]		spc1_pcx_req_pq;
	input	[8:0]		spc2_pcx_atm_pq;
	input	[129:0]		spc2_pcx_data_pa;
	input	[8:0]		spc2_pcx_req_pq;
	input	[8:0]		spc3_pcx_atm_pq;
	input	[129:0]		spc3_pcx_data_pa;
	input	[8:0]		spc3_pcx_req_pq;
	input	[8:0]		spc4_pcx_atm_pq;
	input	[129:0]		spc4_pcx_data_pa;
	input	[8:0]		spc4_pcx_req_pq;
	input	[8:0]		spc5_pcx_atm_pq;
	input	[129:0]		spc5_pcx_data_pa;
	input	[8:0]		spc5_pcx_req_pq;
	input	[8:0]		spc6_pcx_atm_pq;
	input	[129:0]		spc6_pcx_data_pa;
	input	[8:0]		spc6_pcx_req_pq;
	input	[8:0]		spc7_pcx_atm_pq;
	input	[129:0]		spc7_pcx_data_pa;
	input	[8:0]		spc7_pcx_req_pq;
	input			tcu_aclk;
	input			wbm_ack_i0;
	input			wbm_ack_i1;
	input			wbm_ack_i8;
	input	[(64 - 1):0]	wbm_data_i0;
	input	[(64 - 1):0]	wbm_data_i1;
	input	[(64 - 1):0]	wbm_data_i8;
	output	[159:0]		ccx_lstg_out;
	output	[159:0]		ccx_rstg_out;
	output	[191:0]		cpu_rep0_out;
	output	[191:0]		cpu_rep1_out;
	output	[7:0]		cpx_io_grant_cx;
	output	[7:0]		cpx_sctag0_grant_cx;
	output	[7:0]		cpx_sctag1_grant_cx;
	output	[7:0]		cpx_sctag2_grant_cx;
	output	[7:0]		cpx_sctag3_grant_cx;
	output	[7:0]		cpx_sctag4_grant_cx;
	output	[7:0]		cpx_sctag5_grant_cx;
	output	[7:0]		cpx_sctag6_grant_cx;
	output	[7:0]		cpx_sctag7_grant_cx;
	output	[145:0]		cpx_spc1_data_cx2;
	output	[145:0]		cpx_spc2_data_cx2;
	output	[145:0]		cpx_spc3_data_cx2;
	output	[145:0]		cpx_spc4_data_cx2;
	output	[145:0]		cpx_spc5_data_cx2;
	output	[145:0]		cpx_spc6_data_cx2;
	output	[145:0]		cpx_spc7_data_cx2;
	output	[35:0]		dmo_dout;
	output			pcx_sctag2_atm_px1;
	output	[129:0]		pcx_sctag2_data_px2;
	output			pcx_sctag2_data_rdy_px1;
	output			pcx_sctag3_atm_px1;
	output	[129:0]		pcx_sctag3_data_px2;
	output			pcx_sctag3_data_rdy_px1;
	output			pcx_sctag4_atm_px1;
	output	[129:0]		pcx_sctag4_data_px2;
	output			pcx_sctag4_data_rdy_px1;
	output			pcx_sctag5_atm_px1;
	output	[129:0]		pcx_sctag5_data_px2;
	output			pcx_sctag5_data_rdy_px1;
	output			pcx_sctag6_atm_px1;
	output	[129:0]		pcx_sctag6_data_px2;
	output			pcx_sctag6_data_rdy_px1;
	output			pcx_sctag7_atm_px1;
	output	[129:0]		pcx_sctag7_data_px2;
	output			pcx_sctag7_data_rdy_px1;
	output	[8:0]		pcx_spc1_grant_px;
	output	[8:0]		pcx_spc2_grant_px;
	output	[8:0]		pcx_spc3_grant_px;
	output	[8:0]		pcx_spc4_grant_px;
	output	[8:0]		pcx_spc5_grant_px;
	output	[8:0]		pcx_spc6_grant_px;
	output	[8:0]		pcx_spc7_grant_px;
	output	[1:0]		scan_out;
	output	[7:0]		spc_core_running_status;
	output	[1:0]		spc_dbg_instr_cmt_grp0;
	output	[1:0]		spc_dbg_instr_cmt_grp1;
	output			spc_efu_fuse_ddata;
	output			spc_efu_fuse_dxfer_en;
	output			spc_efu_fuse_idata;
	output			spc_efu_fuse_ixfer_en;
	output	[4:0]		spc_grant_o;
	output			spc_grant_o_8;
	output			spc_hardstop_request;
	output			spc_mbist_done;
	output			spc_mbist_fail;
	output			spc_shscan_scan_out;
	output			spc_softstop_request;
	output			spc_ss_complete;
	output			spc_tcu_lbist_done;
	output			spc_tcu_lbist_scan_out;
	output			spc_tcu_mbist_scan_out;
	output			spc_trigger_pulse;
	output	[(64 - 1):0]	wbm_addr_o0;
	output	[(64 - 1):0]	wbm_addr_o1;
	output	[(64 - 1):0]	wbm_addr_o8;
	output			wbm_cycle_o0;
	output			wbm_cycle_o1;
	output			wbm_cycle_o8;
	output	[(64 - 1):0]	wbm_data_o0;
	output	[(64 - 1):0]	wbm_data_o1;
	output	[(64 - 1):0]	wbm_data_o8;
	output	[((64 / 8) - 1):0]
				wbm_sel_o0;
	output	[((64 / 8) - 1):0]
				wbm_sel_o1;
	output	[((64 / 8) - 1):0]
				wbm_sel_o8;
	output			wbm_strobe_o0;
	output			wbm_strobe_o1;
	output			wbm_strobe_o8;
	output			wbm_we_o0;
	output			wbm_we_o1;
	output			wbm_we_o8;

	wire	[145:0]		cpx_spc0_data_cx2;
	wire	[145:0]		io_cpx_data_ca;
	wire	[7:0]		io_cpx_req_cq;
	wire			io_pcx_stall_pq;
	wire	[129:0]		pcx_fpio_data_px2;
	wire			pcx_sctag0_atm_px1;
	wire			pcx_sctag0_data_rdy_px1;
	wire			pcx_sctag1_atm_px1;
	wire			pcx_sctag1_data_rdy_px1;
	wire	[8:0]		pcx_spc0_grant_px;
	wire			sctag0_pcx_stall_pq;
	wire			sctag1_pcx_stall_pq;
	wire	[8:0]		spc0_pcx_atm_pq;
	wire	[129:0]		spc0_pcx_data_pa;
	wire	[8:0]		spc0_pcx_req_pq;
	wire	[145:0]		spc_packetin_o_0;
	wire	[145:0]		spc_packetin_o_1;
	wire	[129:0]		spc_packetout_i_0;
	wire	[129:0]		spc_packetout_i_1;
	wire			spc_ready_o_0;
	wire			spc_ready_o_1;
	wire			spc_req_i_8;

//. 
	//. wire 	[5:0]	sys_interrupt_source_i = 6'h0 ;
	wire 		tcu_clk_stop = 0;
	wire 		tcu_dectest = 1;
	wire 		tcu_muxtest = 1;
	wire tcu_array_wr_inhibit = 0;
	wire tcu_se_scancollar_in = 0;
	wire tcu_se_scancollar_out = 0;
	wire rst_wmr_protect = 0;
	wire tcu_shscan_pce_ov = 0;
	wire tcu_shscan_clk_stop = 0;
	wire tcu_shscan_aclk = 0;
	wire tcu_shscan_bclk = 0;
	wire tcu_shscan_scan_in = 0;
	wire tcu_shscan_scan_en = 0;
	wire [2:0]      tcu_shscanid = 0;
	wire tcu_spc_mbist_scan_in = 0;
	wire tcu_mbist_bisi_en = 0;
	wire tcu_spc_mbist_start = 0;
	wire tcu_mbist_user_mode = 0;
	wire [2:0]      const_cpuid = 0;
	wire tcu_ss_mode = 0;
	wire tcu_do_mode = 0;
	wire tcu_ss_request = 0;
	wire ncu_cmp_tick_enable = 1;
	wire ncu_wmr_vec_mask = 1;
	wire ncu_spc_pm = 1;
	wire ncu_spc_ba01 = 1;
	wire ncu_spc_ba23 = 0;
	wire ncu_spc_ba45 = 0;
	wire ncu_spc_ba67 = 0;
	wire efu_spc_fuse_data = 0;
	wire efu_spc_fuse_ixfer_en = 0;
	wire efu_spc_fuse_dxfer_en = 0;
	wire efu_spc_fuse_iclr = 0;
	wire efu_spc_fuse_dclr = 0;
	wire vnw_ary0 = 1;
	wire vnw_ary1 = 1;
	wire tcu_spc_lbist_start = 0;
	wire tcu_spc_lbist_scan_in = 0;
	wire tcu_spc_lbist_pgm = 0;
	wire tcu_spc_test_mode = 0;
	wire [35:0]     dmo_din = 36'b0;
	wire dmo_coresel = 0;
	wire dmo_icmuxctl = 0;
	wire dmo_dcmuxctl = 0;
	wire ncu_spc_l2_idx_hash_en = 0;
	wire [7:0]      tcu_core_running = 8'b1;
	wire [2:0]      power_throttle = 0;
	wire [3:0]      hver_mask_minor_rev = 0;
	wire ccu_slow_cmp_sync_en = 1;
	wire ccu_cmp_slow_sync_en = 1;
	wire cmp_gclk_c2_ccx_left = gclk;
	wire cmp_gclk_c2_ccx_right = gclk;
	wire [1:0] scan_in = 0;
	wire tcu_pce_ov = 0;
	wire gl_ccx_clk_stop_left = 0;
	wire gl_ccx_clk_stop_right = 0;
	wire tcu_bclk = 0;
	wire tcu_scan_en = 0;
	wire tcu_atpg_mode = 0;


	spc spc(
		.gclk				(gclk), 
		.scan_in			(scan_in[1:0]), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.tcu_clk_stop			(tcu_clk_stop), 
		.tcu_aclk			(tcu_aclk), 
		.tcu_bclk			(tcu_bclk), 
		.tcu_dectest			(tcu_dectest), 
		.tcu_muxtest			(tcu_muxtest), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_array_wr_inhibit		(tcu_array_wr_inhibit), 
		.tcu_se_scancollar_in		(tcu_se_scancollar_in), 
		.tcu_se_scancollar_out		(tcu_se_scancollar_out), 
		.tcu_atpg_mode			(tcu_atpg_mode), 
		.rst_wmr_protect		(rst_wmr_protect), 
		.scan_out			(), 
		.tcu_shscan_pce_ov		(tcu_shscan_pce_ov), 
		.tcu_shscan_clk_stop		(tcu_shscan_clk_stop), 
		.tcu_shscan_aclk		(tcu_shscan_aclk), 
		.tcu_shscan_bclk		(tcu_shscan_bclk), 
		.tcu_shscan_scan_in		(tcu_shscan_scan_in), 
		.tcu_shscan_scan_en		(tcu_shscan_scan_en), 
		.tcu_shscanid			(tcu_shscanid[2:0]), 
		.spc_shscan_scan_out		(spc_shscan_scan_out), 
		.cluster_arst_l			(cluster_arst_l), 
		.tcu_spc_mbist_scan_in		(tcu_spc_mbist_scan_in), 
		.tcu_mbist_bisi_en		(tcu_mbist_bisi_en), 
		.tcu_spc_mbist_start		(tcu_spc_mbist_start), 
		.tcu_mbist_user_mode		(tcu_mbist_user_mode), 
		.spc_mbist_fail			(spc_mbist_fail), 
		.spc_mbist_done			(spc_mbist_done), 
		.spc_tcu_mbist_scan_out		(spc_tcu_mbist_scan_out), 
		.const_cpuid			(const_cpuid[2:0]), 
		.tcu_ss_mode			(tcu_ss_mode), 
		.tcu_do_mode			(tcu_do_mode), 
		.tcu_ss_request			(tcu_ss_request), 
		.ncu_cmp_tick_enable		(ncu_cmp_tick_enable), 
		.spc_ss_complete		(spc_ss_complete), 
		.ncu_wmr_vec_mask		(ncu_wmr_vec_mask), 
		.spc_hardstop_request		(spc_hardstop_request), 
		.spc_softstop_request		(spc_softstop_request), 
		.spc_trigger_pulse		(spc_trigger_pulse), 
		.ncu_spc_pm			(ncu_spc_pm), 
		.ncu_spc_ba01			(ncu_spc_ba01), 
		.ncu_spc_ba23			(ncu_spc_ba23), 
		.ncu_spc_ba45			(ncu_spc_ba45), 
		.ncu_spc_ba67			(ncu_spc_ba67), 
		.efu_spc_fuse_data		(efu_spc_fuse_data), 
		.efu_spc_fuse_ixfer_en		(efu_spc_fuse_ixfer_en), 
		.efu_spc_fuse_dxfer_en		(efu_spc_fuse_dxfer_en), 
		.efu_spc_fuse_iclr		(efu_spc_fuse_iclr), 
		.efu_spc_fuse_dclr		(efu_spc_fuse_dclr), 
		.spc_efu_fuse_ddata		(spc_efu_fuse_ddata), 
		.spc_efu_fuse_idata		(spc_efu_fuse_idata), 
		.spc_efu_fuse_ixfer_en		(spc_efu_fuse_ixfer_en), 
		.spc_efu_fuse_dxfer_en		(spc_efu_fuse_dxfer_en), 
		.vnw_ary0			(vnw_ary0), 
		.vnw_ary1			(vnw_ary1), 
		.tcu_spc_lbist_start		(tcu_spc_lbist_start), 
		.tcu_spc_lbist_scan_in		(tcu_spc_lbist_scan_in), 
		.tcu_spc_lbist_pgm		(tcu_spc_lbist_pgm), 
		.tcu_spc_test_mode		(tcu_spc_test_mode), 
		.spc_tcu_lbist_done		(spc_tcu_lbist_done), 
		.spc_tcu_lbist_scan_out		(spc_tcu_lbist_scan_out), 
		.dmo_din			(dmo_din[35:0]), 
		.dmo_coresel			(dmo_coresel), 
		.dmo_icmuxctl			(dmo_icmuxctl), 
		.dmo_dcmuxctl			(dmo_dcmuxctl), 
		.dmo_dout			(dmo_dout[35:0]), 
		.ncu_spc_l2_idx_hash_en		(ncu_spc_l2_idx_hash_en), 
		.cpx_spc_data_cx		(cpx_spc0_data_cx2), 
		.pcx_spc_grant_px		(pcx_spc0_grant_px), 
		.spc_pcx_req_pq			(spc0_pcx_req_pq), 
		.spc_pcx_atm_pq			(spc0_pcx_atm_pq), 
		.spc_pcx_data_pa		(spc0_pcx_data_pa), 
		.tcu_core_running		(tcu_core_running[7:0]), 
		.spc_core_running_status	(spc_core_running_status[7:0]), 
		.power_throttle			(power_throttle[2:0]), 
		.spc_dbg_instr_cmt_grp0		(spc_dbg_instr_cmt_grp0[1:0]), 
		.spc_dbg_instr_cmt_grp1		(spc_dbg_instr_cmt_grp1[1:0]), 
		.hver_mask_minor_rev		(hver_mask_minor_rev[3:0]), 
		.ccu_slow_cmp_sync_en		(ccu_slow_cmp_sync_en), 
		.ccu_cmp_slow_sync_en		(ccu_cmp_slow_sync_en));
	spc2wbm spc2wbm0(
		.sys_clock_i			(gclk), 
		.sys_reset_i			((~cluster_arst_l)), 
		.sys_interrupt_source_i		(sys_interrupt_source_i[5:0]), 
		.spc_req_i			({4'h0,pcx_sctag0_data_rdy_px1}), 
		.spc_atom_i			(pcx_sctag0_atm_px1), 
		.spc_packetout_i		(spc_packetout_i_0[129:0]), 
		.wbm_ack_i			(wbm_ack_i0), 
		.wbm_data_i			(wbm_data_i0[(64 - 1):0]), 
		.spc_grant_o			(spc_grant_o[4:0]), 
		.spc_ready_o			(spc_ready_o_0), 
		.spc_packetin_o			(spc_packetin_o_0[145:0]), 
		.spc_stallreq_o			(sctag0_pcx_stall_pq), 
		.wbm_cycle_o			(wbm_cycle_o0), 
		.wbm_strobe_o			(wbm_strobe_o0), 
		.wbm_we_o			(wbm_we_o0), 
		.wbm_addr_o			(wbm_addr_o0[(64 - 1):0]), 
		.wbm_data_o			(wbm_data_o0[(64 - 1):0]), 
		.wbm_sel_o			(wbm_sel_o0[((64 / 8) - 1):0]));
	spc2wbm spc2wbm1(
		.sys_clock_i			(gclk), 
		.sys_reset_i			((~cluster_arst_l)), 
		.sys_interrupt_source_i		(sys_interrupt_source_i[5:0]), 
		.spc_req_i			({4'h0,pcx_sctag1_data_rdy_px1}), 
		.spc_atom_i			(pcx_sctag1_atm_px1), 
		.spc_packetout_i		(spc_packetout_i_1[129:0]), 
		.wbm_ack_i			(wbm_ack_i1), 
		.wbm_data_i			(wbm_data_i1[(64 - 1):0]), 
		.spc_grant_o			(), 
		.spc_ready_o			(spc_ready_o_1), 
		.spc_packetin_o			(spc_packetin_o_1[145:0]), 
		.spc_stallreq_o			(sctag1_pcx_stall_pq), 
		.wbm_cycle_o			(wbm_cycle_o1), 
		.wbm_strobe_o			(wbm_strobe_o1), 
		.wbm_we_o			(wbm_we_o1), 
		.wbm_addr_o			(wbm_addr_o1[(64 - 1):0]), 
		.wbm_data_o			(wbm_data_o1[(64 - 1):0]), 
		.wbm_sel_o			(wbm_sel_o1[((64 / 8) - 1):0]));
	spc2wbm spc2wbm_ncu(
		.sys_clock_i			(gclk), 
		.sys_reset_i			((~cluster_arst_l)), 
		.sys_interrupt_source_i		(sys_interrupt_source_i[5:0]), 
		.spc_req_i			({4'h0,spc_req_i_8}), 
		.spc_atom_i			(1'b0), 
		.spc_packetout_i		(pcx_fpio_data_px2), 
		.wbm_ack_i			(wbm_ack_i8), 
		.wbm_data_i			(wbm_data_i8[(64 - 1):0]), 
		.spc_grant_o			(spc_grant_o_8), 
		.spc_ready_o			(io_cpx_req_cq), 
		.spc_packetin_o			(io_cpx_data_ca), 
		.spc_stallreq_o			(io_pcx_stall_pq), 
		.wbm_cycle_o			(wbm_cycle_o8), 
		.wbm_strobe_o			(wbm_strobe_o8), 
		.wbm_we_o			(wbm_we_o8), 
		.wbm_addr_o			(wbm_addr_o8[(64 - 1):0]), 
		.wbm_data_o			(wbm_data_o8[(64 - 1):0]), 
		.wbm_sel_o			(wbm_sel_o8[((64 / 8) - 1):0]));
	ccx ccx(
		.cmp_gclk_c2_ccx_left		(cmp_gclk_c2_ccx_left), 
		.cmp_gclk_c2_ccx_right		(cmp_gclk_c2_ccx_right), 
		.scan_in			(scan_in[1:0]), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.gl_ccx_clk_stop_left		(gl_ccx_clk_stop_left), 
		.gl_ccx_clk_stop_right		(gl_ccx_clk_stop_right), 
		.tcu_aclk			(tcu_aclk), 
		.tcu_bclk			(tcu_bclk), 
		.tcu_scan_en			(tcu_scan_en), 
		.cluster_arst_l			(cluster_arst_l), 
		.tcu_atpg_mode			(tcu_atpg_mode), 
		.scan_out			(), 
		.cpu_rep0_in			(cpu_rep0_in[191:0]), 
		.cpu_rep0_out			(cpu_rep0_out[191:0]), 
		.cpu_rep1_in			(cpu_rep1_in[191:0]), 
		.cpu_rep1_out			(cpu_rep1_out[191:0]), 
		.ccx_lstg_in			(ccx_lstg_in[159:0]), 
		.ccx_lstg_out			(ccx_lstg_out[159:0]), 
		.ccx_rstg_in			(ccx_rstg_in[159:0]), 
		.ccx_rstg_out			(ccx_rstg_out[159:0]), 
		.spc0_pcx_data_pa		(spc0_pcx_data_pa[129:0]), 
		.spc0_pcx_req_pq		(spc0_pcx_req_pq[8:0]), 
		.spc0_pcx_atm_pq		(spc0_pcx_atm_pq[8:0]), 
		.spc1_pcx_data_pa		(spc1_pcx_data_pa[129:0]), 
		.spc1_pcx_req_pq		(spc1_pcx_req_pq[8:0]), 
		.spc1_pcx_atm_pq		(spc1_pcx_atm_pq[8:0]), 
		.spc2_pcx_data_pa		(spc2_pcx_data_pa[129:0]), 
		.spc2_pcx_req_pq		(spc2_pcx_req_pq[8:0]), 
		.spc2_pcx_atm_pq		(spc2_pcx_atm_pq[8:0]), 
		.spc3_pcx_data_pa		(spc3_pcx_data_pa[129:0]), 
		.spc3_pcx_req_pq		(spc3_pcx_req_pq[8:0]), 
		.spc3_pcx_atm_pq		(spc3_pcx_atm_pq[8:0]), 
		.spc4_pcx_data_pa		(spc4_pcx_data_pa[129:0]), 
		.spc4_pcx_req_pq		(spc4_pcx_req_pq[8:0]), 
		.spc4_pcx_atm_pq		(spc4_pcx_atm_pq[8:0]), 
		.spc5_pcx_data_pa		(spc5_pcx_data_pa[129:0]), 
		.spc5_pcx_req_pq		(spc5_pcx_req_pq[8:0]), 
		.spc5_pcx_atm_pq		(spc5_pcx_atm_pq[8:0]), 
		.spc6_pcx_data_pa		(spc6_pcx_data_pa[129:0]), 
		.spc6_pcx_req_pq		(spc6_pcx_req_pq[8:0]), 
		.spc6_pcx_atm_pq		(spc6_pcx_atm_pq[8:0]), 
		.spc7_pcx_data_pa		(spc7_pcx_data_pa[129:0]), 
		.spc7_pcx_req_pq		(spc7_pcx_req_pq[8:0]), 
		.spc7_pcx_atm_pq		(spc7_pcx_atm_pq[8:0]), 
		.io_pcx_stall_pq		(io_pcx_stall_pq), 
		.sctag0_pcx_stall_pq		(sctag0_pcx_stall_pq), 
		.sctag1_pcx_stall_pq		(sctag1_pcx_stall_pq), 
		.sctag2_pcx_stall_pq		(sctag2_pcx_stall_pq), 
		.sctag3_pcx_stall_pq		(sctag3_pcx_stall_pq), 
		.sctag4_pcx_stall_pq		(sctag4_pcx_stall_pq), 
		.sctag5_pcx_stall_pq		(sctag5_pcx_stall_pq), 
		.sctag6_pcx_stall_pq		(sctag6_pcx_stall_pq), 
		.sctag7_pcx_stall_pq		(sctag7_pcx_stall_pq), 
		.pcx_spc0_grant_px		(pcx_spc0_grant_px[8:0]), 
		.pcx_spc1_grant_px		(pcx_spc1_grant_px[8:0]), 
		.pcx_spc2_grant_px		(pcx_spc2_grant_px[8:0]), 
		.pcx_spc3_grant_px		(pcx_spc3_grant_px[8:0]), 
		.pcx_spc4_grant_px		(pcx_spc4_grant_px[8:0]), 
		.pcx_spc5_grant_px		(pcx_spc5_grant_px[8:0]), 
		.pcx_spc6_grant_px		(pcx_spc6_grant_px[8:0]), 
		.pcx_spc7_grant_px		(pcx_spc7_grant_px[8:0]), 
		.pcx_fpio_data_px2		(pcx_fpio_data_px2[129:0]), 
		.pcx_fpio_data_rdy_px1		(spc_req_i_8), 
		.pcx_sctag0_atm_px1		(pcx_sctag0_atm_px1), 
		.pcx_sctag0_data_px2		(spc_packetout_i_0[129:0]), 
		.pcx_sctag0_data_rdy_px1	(pcx_sctag0_data_rdy_px1), 
		.pcx_sctag1_atm_px1		(pcx_sctag1_atm_px1), 
		.pcx_sctag1_data_px2		(spc_packetout_i_1[129:0]), 
		.pcx_sctag1_data_rdy_px1	(pcx_sctag1_data_rdy_px1), 
		.pcx_sctag2_atm_px1		(pcx_sctag2_atm_px1), 
		.pcx_sctag2_data_px2		(pcx_sctag2_data_px2[129:0]), 
		.pcx_sctag2_data_rdy_px1	(pcx_sctag2_data_rdy_px1), 
		.pcx_sctag3_atm_px1		(pcx_sctag3_atm_px1), 
		.pcx_sctag3_data_px2		(pcx_sctag3_data_px2[129:0]), 
		.pcx_sctag3_data_rdy_px1	(pcx_sctag3_data_rdy_px1), 
		.pcx_sctag4_atm_px1		(pcx_sctag4_atm_px1), 
		.pcx_sctag4_data_px2		(pcx_sctag4_data_px2[129:0]), 
		.pcx_sctag4_data_rdy_px1	(pcx_sctag4_data_rdy_px1), 
		.pcx_sctag5_atm_px1		(pcx_sctag5_atm_px1), 
		.pcx_sctag5_data_px2		(pcx_sctag5_data_px2[129:0]), 
		.pcx_sctag5_data_rdy_px1	(pcx_sctag5_data_rdy_px1), 
		.pcx_sctag6_atm_px1		(pcx_sctag6_atm_px1), 
		.pcx_sctag6_data_px2		(pcx_sctag6_data_px2[129:0]), 
		.pcx_sctag6_data_rdy_px1	(pcx_sctag6_data_rdy_px1), 
		.pcx_sctag7_atm_px1		(pcx_sctag7_atm_px1), 
		.pcx_sctag7_data_px2		(pcx_sctag7_data_px2[129:0]), 
		.pcx_sctag7_data_rdy_px1	(pcx_sctag7_data_rdy_px1), 
		.io_cpx_data_ca			(io_cpx_data_ca[145:0]), 
		.io_cpx_req_cq			(io_cpx_req_cq[7:0]), 
		.sctag0_cpx_atom_cq		(1'b0), 
		.sctag0_cpx_data_ca		(spc_packetin_o_0[145:0]), 
		.sctag0_cpx_req_cq		(spc_ready_o_0), 
		.sctag1_cpx_atom_cq		(1'b0), 
		.sctag1_cpx_data_ca		(spc_packetin_o_1[145:0]), 
		.sctag1_cpx_req_cq		(spc_ready_o_1), 
		.sctag2_cpx_atom_cq		(sctag2_cpx_atom_cq), 
		.sctag2_cpx_data_ca		(sctag2_cpx_data_ca[145:0]), 
		.sctag2_cpx_req_cq		(sctag2_cpx_req_cq[7:0]), 
		.sctag3_cpx_atom_cq		(sctag3_cpx_atom_cq), 
		.sctag3_cpx_data_ca		(sctag3_cpx_data_ca[145:0]), 
		.sctag3_cpx_req_cq		(sctag3_cpx_req_cq[7:0]), 
		.sctag4_cpx_atom_cq		(sctag4_cpx_atom_cq), 
		.sctag4_cpx_data_ca		(sctag4_cpx_data_ca[145:0]), 
		.sctag4_cpx_req_cq		(sctag4_cpx_req_cq[7:0]), 
		.sctag5_cpx_atom_cq		(sctag5_cpx_atom_cq), 
		.sctag5_cpx_data_ca		(sctag5_cpx_data_ca[145:0]), 
		.sctag5_cpx_req_cq		(sctag5_cpx_req_cq[7:0]), 
		.sctag6_cpx_atom_cq		(sctag6_cpx_atom_cq), 
		.sctag6_cpx_data_ca		(sctag6_cpx_data_ca[145:0]), 
		.sctag6_cpx_req_cq		(sctag6_cpx_req_cq[7:0]), 
		.sctag7_cpx_atom_cq		(sctag7_cpx_atom_cq), 
		.sctag7_cpx_data_ca		(sctag7_cpx_data_ca[145:0]), 
		.sctag7_cpx_req_cq		(sctag7_cpx_req_cq[7:0]), 
		.cpx_io_grant_cx		(cpx_io_grant_cx[7:0]), 
		.cpx_sctag0_grant_cx		(cpx_sctag0_grant_cx[7:0]), 
		.cpx_sctag1_grant_cx		(cpx_sctag1_grant_cx[7:0]), 
		.cpx_sctag2_grant_cx		(cpx_sctag2_grant_cx[7:0]), 
		.cpx_sctag3_grant_cx		(cpx_sctag3_grant_cx[7:0]), 
		.cpx_sctag4_grant_cx		(cpx_sctag4_grant_cx[7:0]), 
		.cpx_sctag5_grant_cx		(cpx_sctag5_grant_cx[7:0]), 
		.cpx_sctag6_grant_cx		(cpx_sctag6_grant_cx[7:0]), 
		.cpx_sctag7_grant_cx		(cpx_sctag7_grant_cx[7:0]), 
		.cpx_spc0_data_cx2		(cpx_spc0_data_cx2[145:0]), 
		.cpx_spc1_data_cx2		(cpx_spc1_data_cx2[145:0]), 
		.cpx_spc2_data_cx2		(cpx_spc2_data_cx2[145:0]), 
		.cpx_spc3_data_cx2		(cpx_spc3_data_cx2[145:0]), 
		.cpx_spc4_data_cx2		(cpx_spc4_data_cx2[145:0]), 
		.cpx_spc5_data_cx2		(cpx_spc5_data_cx2[145:0]), 
		.cpx_spc6_data_cx2		(cpx_spc6_data_cx2[145:0]), 
		.cpx_spc7_data_cx2		(cpx_spc7_data_cx2[145:0]));
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: t2_fpga.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`timescale 1 ns / 100 ps
(* top *)
module t2_fpga(
         clk, 
            cts_pad_i, 
         dsr_pad_i, 
        efu_spc_fuse_ixfer_en, 
         ri_pad_i, 
         srx_pad_i, sys_interrupt_source_i,
            wbm_ack_i8, wbm_adr_uart, wbm_cycle_nc_not_uart,
        wbm_cycle_uart, wbm_data_i8, wbm_data_uart_i, wbm_sel_uart,
        wbm_strobe_nc_not_uart, wbm_strobe_uart,
         cpx_io_grant_cx, cpx_sctag0_grant_cx,
        cpx_sctag1_grant_cx, cpx_sctag2_grant_cx, cpx_sctag3_grant_cx,
        cpx_sctag4_grant_cx, cpx_sctag5_grant_cx, cpx_sctag6_grant_cx,
        cpx_sctag7_grant_cx,
        dmo_dout, dtr_pad_o, int_o,
        pcx_spc1_grant_px, pcx_spc2_grant_px, pcx_spc3_grant_px,
        pcx_spc4_grant_px, pcx_spc5_grant_px, pcx_spc6_grant_px,
        pcx_spc7_grant_px, rts_pad_o, 
        spc_core_running_status,
        spc_dbg_instr_cmt_grp0, spc_dbg_instr_cmt_grp1, spc_efu_fuse_ddata,
        spc_efu_fuse_dxfer_en, spc_efu_fuse_idata, spc_efu_fuse_ixfer_en,
        spc_grant_o, spc_grant_o_8, spc_hardstop_request, spc_mbist_done,
        spc_mbist_fail, spc_shscan_scan_out, spc_softstop_request,
        spc_ss_complete, spc_tcu_lbist_done, spc_tcu_lbist_scan_out,
        spc_tcu_mbist_scan_out, spc_trigger_pulse, stx_pad_o,
        wbm_ack_nc_not_uart, wbm_ack_uart, wbm_cycle_o8, wbm_data_nc_not_uart,
        wbm_data_uart, wbm_strobe_o8,
mem_harness0_wbs_addr_i ,
mem_harness1_wbs_addr_i ,
wbm_ack_i0 ,
wbm_ack_i1 ,
wbm_addr_o0 ,
wbm_addr_o1 ,
wbm_addr_o8 ,
wbm_cycle_o0 ,
wbm_cycle_o1 ,
wbm_data_i0 ,
wbm_data_i1 ,
wbm_data_o0 ,
wbm_data_o1 ,
wbm_data_o8 ,
wbm_sel_o0 ,
wbm_sel_o1 ,
wbm_sel_o8,
wbm_strobe_o0 ,
wbm_strobe_o1 ,
wbm_we_o0 ,
wbm_we_o1 
 );

        wire    [159:0]         ccx_lstg_in = 0;
        wire [159:0]            ccx_rstg_in = 0;
        input                   clk;
        wire    [191:0]         cpu_rep0_in = 0;
        wire    [191:0]         cpu_rep1_in = 0;
        input                   cts_pad_i;
        input                   dsr_pad_i;
        input                   efu_spc_fuse_ixfer_en;
        input                   ri_pad_i;
        wire                    sctag2_cpx_atom_cq = 0;
        wire    [145:0]         sctag2_cpx_data_ca = 0;
        wire    [7:0]           sctag2_cpx_req_cq = 0;
        wire                    sctag2_pcx_stall_pq = 0;
        wire                    sctag3_cpx_atom_cq = 0;
        wire    [145:0]         sctag3_cpx_data_ca = 0;
        wire    [7:0]           sctag3_cpx_req_cq = 0;
        wire                    sctag3_pcx_stall_pq = 0;
        wire                    sctag4_cpx_atom_cq = 0;
        wire    [145:0]         sctag4_cpx_data_ca = 0;
        wire    [7:0]           sctag4_cpx_req_cq = 0;
        wire                    sctag4_pcx_stall_pq = 0; 
        wire                    sctag5_cpx_atom_cq = 0;
        wire    [145:0]         sctag5_cpx_data_ca = 0;
        wire    [7:0]           sctag5_cpx_req_cq = 0;
        wire                    sctag5_pcx_stall_pq = 0;
        wire                    sctag6_cpx_atom_cq = 0;
       wire    [145:0]         sctag6_cpx_data_ca = 0;
        wire    [7:0]           sctag6_cpx_req_cq = 0;
        wire                    sctag6_pcx_stall_pq = 0;
        wire                    sctag7_cpx_atom_cq = 0;
        wire    [145:0]         sctag7_cpx_data_ca = 0;
        wire    [7:0]           sctag7_cpx_req_cq = 0;


        wire                    sctag7_pcx_stall_pq;
        wire    [8:0]           spc1_pcx_atm_pq;
        wire    [129:0]         spc1_pcx_data_pa = 0;
        wire    [8:0]           spc1_pcx_req_pq = 0;
        wire    [8:0]           spc2_pcx_atm_pq = 0;
        wire    [129:0]         spc2_pcx_data_pa = 0;
        wire    [8:0]           spc2_pcx_req_pq = 0;
        wire    [8:0]           spc3_pcx_atm_pq = 0;
        wire    [129:0]         spc3_pcx_data_pa = 0;
        wire    [8:0]           spc3_pcx_req_pq = 0;
        wire    [8:0]           spc4_pcx_atm_pq = 0;
        wire    [129:0]         spc4_pcx_data_pa = 0;
        wire    [8:0]           spc4_pcx_req_pq = 0;
        wire    [8:0]           spc5_pcx_atm_pq = 0;
        wire    [129:0]         spc5_pcx_data_pa = 0;
        wire    [8:0]           spc5_pcx_req_pq = 0;
        wire    [8:0]           spc6_pcx_atm_pq = 0;
        wire    [129:0]         spc6_pcx_data_pa = 0;
        wire    [8:0]           spc6_pcx_req_pq = 0;
        wire    [8:0]           spc7_pcx_atm_pq = 0;
        wire    [129:0]         spc7_pcx_data_pa = 0;
        wire    [8:0]           spc7_pcx_req_pq = 0;

        input                   srx_pad_i;
        input   [5:0]           sys_interrupt_source_i;
        output                  wbm_ack_i8;
        output  [(3 - 1):0]     wbm_adr_uart;
        output                  wbm_cycle_nc_not_uart;
        output                  wbm_cycle_uart;
        output  [(64 - 1):0]    wbm_data_i8;
        output  [7:0]           wbm_data_uart_i;
        input   [3:0]           wbm_sel_uart;
        output                  wbm_strobe_nc_not_uart;
        output                  wbm_strobe_uart;
        wire    [159:0]         ccx_lstg_out;
        wire    [159:0]         ccx_rstg_out;
        wire    [191:0]         cpu_rep0_out;
        wire    [191:0]         cpu_rep1_out;
        output  [7:0]           cpx_io_grant_cx;
        output  [7:0]           cpx_sctag0_grant_cx;
        output  [7:0]           cpx_sctag1_grant_cx;
        output  [7:0]           cpx_sctag2_grant_cx;
        output  [7:0]           cpx_sctag3_grant_cx;
        output  [7:0]           cpx_sctag4_grant_cx;
        output  [7:0]           cpx_sctag5_grant_cx;
        output  [7:0]           cpx_sctag6_grant_cx;
        output  [7:0]           cpx_sctag7_grant_cx;
        wire    [145:0]         cpx_spc1_data_cx2;
        wire    [145:0]         cpx_spc2_data_cx2;
        wire    [145:0]         cpx_spc3_data_cx2;
        wire    [145:0]         cpx_spc4_data_cx2;
        wire    [145:0]         cpx_spc5_data_cx2;
        wire    [145:0]         cpx_spc6_data_cx2;
        wire    [145:0]         cpx_spc7_data_cx2;
        output  [35:0]          dmo_dout;
        output                  dtr_pad_o;
        output                  int_o;
        wire                    pcx_sctag2_atm_px1;
        wire    [129:0]         pcx_sctag2_data_px2;
        wire                    pcx_sctag2_data_rdy_px1;
wire                    pcx_sctag3_atm_px1;
        wire    [129:0]         pcx_sctag3_data_px2;
        wire                    pcx_sctag3_data_rdy_px1;
        wire                    pcx_sctag4_atm_px1;
        wire    [129:0]         pcx_sctag4_data_px2;
        wire                    pcx_sctag4_data_rdy_px1;
        wire                    pcx_sctag5_atm_px1;
        wire    [129:0]         pcx_sctag5_data_px2;
        wire                    pcx_sctag5_data_rdy_px1;
        wire                    pcx_sctag6_atm_px1;
        wire    [129:0]         pcx_sctag6_data_px2;
        wire                    pcx_sctag6_data_rdy_px1;
        wire                    pcx_sctag7_atm_px1;
        wire    [129:0]         pcx_sctag7_data_px2;
        wire                    pcx_sctag7_data_rdy_px1;
        output  [8:0]           pcx_spc1_grant_px;
        output  [8:0]           pcx_spc2_grant_px;
        output  [8:0]           pcx_spc3_grant_px;
        output  [8:0]           pcx_spc4_grant_px;
        output  [8:0]           pcx_spc5_grant_px;
        output  [8:0]           pcx_spc6_grant_px;
        output  [8:0]           pcx_spc7_grant_px;
        output                  rts_pad_o;
        output  [7:0]           spc_core_running_status;
        output  [1:0]           spc_dbg_instr_cmt_grp0;
        output  [1:0]           spc_dbg_instr_cmt_grp1;
        output                  spc_efu_fuse_ddata;
        output                  spc_efu_fuse_dxfer_en;
        output                  spc_efu_fuse_idata;
        output                  spc_efu_fuse_ixfer_en;
        output  [4:0]           spc_grant_o;
        output                  spc_grant_o_8;
        output                  spc_hardstop_request;
        output                  spc_mbist_done;
        output                  spc_mbist_fail;
        output                  spc_shscan_scan_out;
        output                  spc_softstop_request;
        output                  spc_ss_complete;
        output                  spc_tcu_lbist_done;
        output                  spc_tcu_lbist_scan_out;
        output                  spc_tcu_mbist_scan_out;
        output                  spc_trigger_pulse;
        output                  stx_pad_o;
        output                  wbm_ack_nc_not_uart;
        output                  wbm_ack_uart;
        output                  wbm_cycle_o8;
     output  [(64 - 1):0]    wbm_data_nc_not_uart;
        output  [31:0]          wbm_data_uart;
        output                  wbm_strobe_o8;

        output  [63:0]          mem_harness0_wbs_addr_i ;
        output  [63:0]          mem_harness1_wbs_addr_i ;
        output                  wbm_ack_i0 ;
        output                  wbm_ack_i1 ;
        output  [(64 - 1):0]    wbm_addr_o0 ;
        output  [(64 - 1):0]    wbm_addr_o1 ;
        output  [(64 - 1):0]    wbm_addr_o8 ;
        output                  wbm_cycle_o0 ;
        output                  wbm_cycle_o1 ;
        output  [(64 - 1):0]    wbm_data_i0 ;
        output  [(64 - 1):0]    wbm_data_i1 ;
        output  [(64 - 1):0]    wbm_data_o0 ;
        output  [(64 - 1):0]    wbm_data_o1 ;
        output  [(64 - 1):0]    wbm_data_o8 ;
        output  [((64 / 8) - 1):0] wbm_sel_o0 ;
        output  [((64 / 8) - 1):0] wbm_sel_o1 ;
        output  [((64 / 8) - 1):0] wbm_sel_o8;
        output                  wbm_strobe_o0 ;
        output                  wbm_strobe_o1 ;
        output                  wbm_we_o0 ;
        output                  wbm_we_o1 ;


	wire			gclk;
	wire	[63:0]		mem_harness0_wbs_addr_i;
	wire	[63:0]		mem_harness1_wbs_addr_i;
	wire			reset;
	wire			wbm_ack_i0;
	wire			wbm_ack_i1;
	wire	[(64 - 1):0]	wbm_addr_o0;
	wire	[(64 - 1):0]	wbm_addr_o1;
	wire	[(64 - 1):0]	wbm_addr_o8;
	wire			wbm_cycle_o0;
	wire			wbm_cycle_o1;
	wire	[(64 - 1):0]	wbm_data_i0;
	wire	[(64 - 1):0]	wbm_data_i1;
	wire	[(64 - 1):0]	wbm_data_o0;
	wire	[(64 - 1):0]	wbm_data_o1;
	wire	[(64 - 1):0]	wbm_data_o8;
	wire	[((64 / 8) - 1):0]
				wbm_sel_o0;
	wire	[((64 / 8) - 1):0]
				wbm_sel_o1;
	wire	[((64 / 8) - 1):0]
				wbm_sel_o8;
	wire			wbm_strobe_o0;
	wire			wbm_strobe_o1;
	wire			wbm_we_o0;
	wire			wbm_we_o1;
	wire			wbm_we_o8;
	reg	[7:0]		count;

  `ifdef FPGA_SIM
        reg cmp_refclk ;
        assign GlobalReset = 1'b1;
          initial begin         // generate cmp ref clock (100 MHZ)
            count = 0;
            cmp_refclk = 1'b0;
        end

        initial begin         // generate cmp ref clock (100 MHZ)
           #7;
         forever #(100) cmp_refclk = ~cmp_refclk;
        end
`else
        wire                    cmp_refclk;
`endif

	wire			clk1;
	wire			clk2;
	reg	[7:0]		uart_dat;
	reg	[2:0]		adr_uart;
	reg			rst;

        assign gclk = clk;


`ifndef SYNTHESIS
                assign sys_interrupt_source_i = 6'h0 ;

		defparam mem_harness0.memfilename	= "memory0.hex";
		defparam mem_harness1.memfilename	= "memory1.hex";
		defparam mem_harness2.initmem		= 1;
		defparam mem_harness2.loadmem		= 1;
		defparam mem_harness2.memfilename	= "memory2.hex";
		defparam mem_harness0.addr_bits		= 26;
		defparam mem_harness1.addr_bits		= 26;
		defparam mem_harness2.addr_bits		= 20;
`else 
        defparam mem_harness0.addr_bits     = 13;
        defparam mem_harness1.addr_bits     = 13;
        defparam mem_harness2.addr_bits     = 13;
`endif

		assign mem_harness0_wbs_addr_i = {wbm_addr_o0[(64 - 1):7], 
			wbm_addr_o0[5:0]};
		assign mem_harness1_wbs_addr_i = {wbm_addr_o1[(64 - 1):7], 
			wbm_addr_o1[5:0]};
		assign clk = cmp_refclk;
		assign reset = rst;
		assign wbm_strobe_nc_not_uart = ((wbm_addr_o8[39:12] == 28'hfff0c2c) ? 0
			: wbm_strobe_o8);
		assign wbm_strobe_uart = ((wbm_addr_o8[39:12] == 28'hfff0c2c) ? 
			wbm_strobe_o8 : 0);
		assign wbm_cycle_nc_not_uart = ((wbm_addr_o8[39:12] == 28'hfff0c2c) ? 0
			: wbm_cycle_o8);
		assign wbm_cycle_uart = ((wbm_addr_o8[39:12] == 28'hfff0c2c) ? 
			wbm_cycle_o8 : 0);
		assign wbm_ack_i8 = (wbm_ack_nc_not_uart | wbm_ack_uart);
		assign wbm_data_i8 = (wbm_ack_nc_not_uart ? wbm_data_nc_not_uart : {8 {
			wbm_data_uart[7:0]}});
		assign wbm_data_uart_i = wbm_data_o8[7:0];
		assign wbm_adr_uart[2:0] = (wbm_sel_o8[0] ? 3'b0 : (wbm_sel_o8[1] ? 3'b1
			: (wbm_sel_o8[2] ? 3'd2 : (wbm_sel_o8[3] ? 3'd3 : (wbm_sel_o8[4]
			? 3'd4 : (wbm_sel_o8[5] ? 3'd5 : (wbm_sel_o8[6] ? 3'd6 : 3'd7)))
			))));

		t2 t2(	.ccx_lstg_in			(ccx_lstg_in[159:0]), 
			.ccx_rstg_in			(ccx_rstg_in[159:0]), 
			.cluster_arst_l			((~reset)), 
			.cpu_rep0_in			(cpu_rep0_in[191:0]), 
			.cpu_rep1_in			(cpu_rep1_in[191:0]), 
			.gclk				(clk), 
			.sctag2_cpx_atom_cq		(sctag2_cpx_atom_cq), 
			.sctag2_cpx_data_ca		(sctag2_cpx_data_ca[145:0]), 
			.sctag2_cpx_req_cq		(sctag2_cpx_req_cq[7:0]), 
			.sctag2_pcx_stall_pq		(sctag2_pcx_stall_pq), 
			.sctag3_cpx_atom_cq		(sctag3_cpx_atom_cq), 
			.sctag3_cpx_data_ca		(sctag3_cpx_data_ca[145:0]), 
			.sctag3_cpx_req_cq		(sctag3_cpx_req_cq[7:0]), 
			.sctag3_pcx_stall_pq		(sctag3_pcx_stall_pq), 
			.sctag4_cpx_atom_cq		(sctag4_cpx_atom_cq), 
			.sctag4_cpx_data_ca		(sctag4_cpx_data_ca[145:0]), 
			.sctag4_cpx_req_cq		(sctag4_cpx_req_cq[7:0]), 
			.sctag4_pcx_stall_pq		(sctag4_pcx_stall_pq), 
			.sctag5_cpx_atom_cq		(sctag5_cpx_atom_cq), 
			.sctag5_cpx_data_ca		(sctag5_cpx_data_ca[145:0]), 
			.sctag5_cpx_req_cq		(sctag5_cpx_req_cq[7:0]), 
			.sctag5_pcx_stall_pq		(sctag5_pcx_stall_pq), 
			.sctag6_cpx_atom_cq		(sctag6_cpx_atom_cq), 
			.sctag6_cpx_data_ca		(sctag6_cpx_data_ca[145:0]), 
			.sctag6_cpx_req_cq		(sctag6_cpx_req_cq[7:0]), 
			.sctag6_pcx_stall_pq		(sctag6_pcx_stall_pq), 
			.sctag7_cpx_atom_cq		(sctag7_cpx_atom_cq), 
			.sctag7_cpx_data_ca		(sctag7_cpx_data_ca[145:0]), 
			.sctag7_cpx_req_cq		(sctag7_cpx_req_cq[7:0]), 
			.sctag7_pcx_stall_pq		(sctag7_pcx_stall_pq), 
			.spc1_pcx_atm_pq		(spc1_pcx_atm_pq[8:0]), 
			.spc1_pcx_data_pa		(spc1_pcx_data_pa[129:0]), 
			.spc1_pcx_req_pq		(spc1_pcx_req_pq[8:0]), 
			.spc2_pcx_atm_pq		(spc2_pcx_atm_pq[8:0]), 
			.spc2_pcx_data_pa		(spc2_pcx_data_pa[129:0]), 
			.spc2_pcx_req_pq		(spc2_pcx_req_pq[8:0]), 
			.spc3_pcx_atm_pq		(spc3_pcx_atm_pq[8:0]), 
			.spc3_pcx_data_pa		(spc3_pcx_data_pa[129:0]), 
			.spc3_pcx_req_pq		(spc3_pcx_req_pq[8:0]), 
			.spc4_pcx_atm_pq		(spc4_pcx_atm_pq[8:0]), 
			.spc4_pcx_data_pa		(spc4_pcx_data_pa[129:0]), 
			.spc4_pcx_req_pq		(spc4_pcx_req_pq[8:0]), 
			.spc5_pcx_atm_pq		(spc5_pcx_atm_pq[8:0]), 
			.spc5_pcx_data_pa		(spc5_pcx_data_pa[129:0]), 
			.spc5_pcx_req_pq		(spc5_pcx_req_pq[8:0]), 
			.spc6_pcx_atm_pq		(spc6_pcx_atm_pq[8:0]), 
			.spc6_pcx_data_pa		(spc6_pcx_data_pa[129:0]), 
			.spc6_pcx_req_pq		(spc6_pcx_req_pq[8:0]), 
			.spc7_pcx_atm_pq		(spc7_pcx_atm_pq[8:0]), 
			.spc7_pcx_data_pa		(spc7_pcx_data_pa[129:0]), 
			.spc7_pcx_req_pq		(spc7_pcx_req_pq[8:0]), 
    			.sys_interrupt_source_i         (sys_interrupt_source_i[5:0]),	
			.tcu_aclk			(reset), 
			.wbm_ack_i0			(wbm_ack_i0), 
			.wbm_ack_i1			(wbm_ack_i1), 
			.wbm_ack_i8			(wbm_ack_i8), 
			.wbm_data_i0			(wbm_data_i0[(64 - 1):0]), 
			.wbm_data_i1			(wbm_data_i1[(64 - 1):0]), 
			.wbm_data_i8			(wbm_data_i8[(64 - 1):0]), 
			.ccx_lstg_out			(ccx_lstg_out[159:0]), 
			.ccx_rstg_out			(ccx_rstg_out[159:0]), 
			.cpu_rep0_out			(cpu_rep0_out[191:0]), 
			.cpu_rep1_out			(cpu_rep1_out[191:0]), 
			.cpx_io_grant_cx		(cpx_io_grant_cx[7:0]), 
			.cpx_sctag0_grant_cx		(cpx_sctag0_grant_cx[7:0]), 
			.cpx_sctag1_grant_cx		(cpx_sctag1_grant_cx[7:0]), 
			.cpx_sctag2_grant_cx		(cpx_sctag2_grant_cx[7:0]), 
			.cpx_sctag3_grant_cx		(cpx_sctag3_grant_cx[7:0]), 
			.cpx_sctag4_grant_cx		(cpx_sctag4_grant_cx[7:0]), 
			.cpx_sctag5_grant_cx		(cpx_sctag5_grant_cx[7:0]), 
			.cpx_sctag6_grant_cx		(cpx_sctag6_grant_cx[7:0]), 
			.cpx_sctag7_grant_cx		(cpx_sctag7_grant_cx[7:0]), 
			.cpx_spc1_data_cx2		(cpx_spc1_data_cx2[145:0]), 
			.cpx_spc2_data_cx2		(cpx_spc2_data_cx2[145:0]), 
			.cpx_spc3_data_cx2		(cpx_spc3_data_cx2[145:0]), 
			.cpx_spc4_data_cx2		(cpx_spc4_data_cx2[145:0]), 
			.cpx_spc5_data_cx2		(cpx_spc5_data_cx2[145:0]), 
			.cpx_spc6_data_cx2		(cpx_spc6_data_cx2[145:0]), 
			.cpx_spc7_data_cx2		(cpx_spc7_data_cx2[145:0]), 
			.dmo_dout			(dmo_dout[35:0]), 
			.pcx_sctag2_atm_px1		(pcx_sctag2_atm_px1), 
			.pcx_sctag2_data_px2		(pcx_sctag2_data_px2[129:0]), 
			.pcx_sctag2_data_rdy_px1	(pcx_sctag2_data_rdy_px1), 
			.pcx_sctag3_atm_px1		(pcx_sctag3_atm_px1), 
			.pcx_sctag3_data_px2		(pcx_sctag3_data_px2[129:0]), 
			.pcx_sctag3_data_rdy_px1	(pcx_sctag3_data_rdy_px1), 
			.pcx_sctag4_atm_px1		(pcx_sctag4_atm_px1), 
			.pcx_sctag4_data_px2		(pcx_sctag4_data_px2[129:0]), 
			.pcx_sctag4_data_rdy_px1	(pcx_sctag4_data_rdy_px1), 
			.pcx_sctag5_atm_px1		(pcx_sctag5_atm_px1), 
			.pcx_sctag5_data_px2		(pcx_sctag5_data_px2[129:0]), 
			.pcx_sctag5_data_rdy_px1	(pcx_sctag5_data_rdy_px1), 
			.pcx_sctag6_atm_px1		(pcx_sctag6_atm_px1), 
			.pcx_sctag6_data_px2		(pcx_sctag6_data_px2[129:0]), 
			.pcx_sctag6_data_rdy_px1	(pcx_sctag6_data_rdy_px1), 
			.pcx_sctag7_atm_px1		(pcx_sctag7_atm_px1), 
			.pcx_sctag7_data_px2		(pcx_sctag7_data_px2[129:0]), 
			.pcx_sctag7_data_rdy_px1	(pcx_sctag7_data_rdy_px1), 
			.pcx_spc1_grant_px		(pcx_spc1_grant_px[8:0]), 
			.pcx_spc2_grant_px		(pcx_spc2_grant_px[8:0]), 
			.pcx_spc3_grant_px		(pcx_spc3_grant_px[8:0]), 
			.pcx_spc4_grant_px		(pcx_spc4_grant_px[8:0]), 
			.pcx_spc5_grant_px		(pcx_spc5_grant_px[8:0]), 
			.pcx_spc6_grant_px		(pcx_spc6_grant_px[8:0]), 
			.pcx_spc7_grant_px		(pcx_spc7_grant_px[8:0]), 
			.scan_out			(), 
			.spc_core_running_status	(spc_core_running_status[7:0]), 
			.spc_dbg_instr_cmt_grp0		(spc_dbg_instr_cmt_grp0[1:0]), 
			.spc_dbg_instr_cmt_grp1		(spc_dbg_instr_cmt_grp1[1:0]), 
			.spc_efu_fuse_ddata		(spc_efu_fuse_ddata), 
			.spc_efu_fuse_dxfer_en		(spc_efu_fuse_dxfer_en), 
			.spc_efu_fuse_idata		(spc_efu_fuse_idata), 
			.spc_efu_fuse_ixfer_en		(spc_efu_fuse_ixfer_en), 
			.spc_grant_o			(spc_grant_o[4:0]), 
			.spc_grant_o_8			(spc_grant_o_8), 
			.spc_hardstop_request		(spc_hardstop_request), 
			.spc_mbist_done			(spc_mbist_done), 
			.spc_mbist_fail			(spc_mbist_fail), 
			.spc_shscan_scan_out		(spc_shscan_scan_out), 
			.spc_softstop_request		(spc_softstop_request), 
			.spc_ss_complete		(spc_ss_complete), 
			.spc_tcu_lbist_done		(spc_tcu_lbist_done), 
			.spc_tcu_lbist_scan_out		(spc_tcu_lbist_scan_out), 
			.spc_tcu_mbist_scan_out		(spc_tcu_mbist_scan_out), 
			.spc_trigger_pulse		(spc_trigger_pulse), 
			.wbm_addr_o0			(wbm_addr_o0[(64 - 1):0]), 
			.wbm_addr_o1			(wbm_addr_o1[(64 - 1):0]), 
			.wbm_addr_o8			(wbm_addr_o8[(64 - 1):0]), 
			.wbm_cycle_o0			(wbm_cycle_o0), 
			.wbm_cycle_o1			(wbm_cycle_o1), 
			.wbm_cycle_o8			(wbm_cycle_o8), 
			.wbm_data_o0			(wbm_data_o0[(64 - 1):0]), 
			.wbm_data_o1			(wbm_data_o1[(64 - 1):0]), 
			.wbm_data_o8			(wbm_data_o8[(64 - 1):0]), 
			.wbm_sel_o0			(wbm_sel_o0[((64 / 8) - 1):0]), 
			.wbm_sel_o1			(wbm_sel_o1[((64 / 8) - 1):0]), 
			.wbm_sel_o8			(wbm_sel_o8[((64 / 8) - 1):0]), 
			.wbm_strobe_o0			(wbm_strobe_o0), 
			.wbm_strobe_o1			(wbm_strobe_o1), 
			.wbm_strobe_o8			(wbm_strobe_o8), 
			.wbm_we_o0			(wbm_we_o0), 
			.wbm_we_o1			(wbm_we_o1), 
			.wbm_we_o8			(wbm_we_o8));

	mem_harness mem_harness0(
		.sys_clock_i			(clk), 
		.sys_reset_i			(reset), 
		.wbs_cycle_i			(wbm_cycle_o0), 
		.wbs_strobe_i			(wbm_strobe_o0), 
		.wbs_addr_i			(mem_harness0_wbs_addr_i), 
		.wbs_data_i			(wbm_data_o0[(64 - 1):0]), 
		.wbs_we_i			(wbm_we_o0), 
		.wbs_sel_i			(wbm_sel_o0[((64 / 8) - 1):0]), 
		.wbs_ack_o			(wbm_ack_i0), 
		.wbs_data_o			(wbm_data_i0));
	mem_harness mem_harness1(
		.sys_clock_i			(clk), 
		.sys_reset_i			(reset), 
		.wbs_cycle_i			(wbm_cycle_o1), 
		.wbs_strobe_i			(wbm_strobe_o1), 
		.wbs_addr_i			(mem_harness1_wbs_addr_i), 
		.wbs_data_i			(wbm_data_o1[(64 - 1):0]), 
		.wbs_we_i			(wbm_we_o1), 
		.wbs_sel_i			(wbm_sel_o1[((64 / 8) - 1):0]), 
		.wbs_ack_o			(wbm_ack_i1), 
		.wbs_data_o			(wbm_data_i1));
	mem_harness mem_harness2(
		.sys_clock_i			(clk), 
		.sys_reset_i			(reset), 
		.wbs_cycle_i			(wbm_cycle_nc_not_uart), 
		.wbs_strobe_i			(wbm_strobe_nc_not_uart), 
		.wbs_addr_i			(wbm_addr_o8[(64 - 1):0]), 
		.wbs_data_i			(wbm_data_o8[(64 - 1):0]), 
		.wbs_we_i			(wbm_we_o8), 
		.wbs_sel_i			(wbm_sel_o8[((64 / 8) - 1):0]), 
		.wbs_ack_o			(wbm_ack_nc_not_uart), 
		.wbs_data_o			(wbm_data_nc_not_uart[(64 -
		1):0]));

	uart_top uart_top(
		.wb_clk_i			(clk), 
		.wb_rst_i			(reset), 
		.wb_adr_i			(wbm_adr_uart[(3 - 1):0]), 
		.wb_dat_i			(wbm_data_uart_i[7:0]), 
		.wb_dat_o			(wbm_data_uart[31:0]), 
		.wb_we_i			(wbm_we_o8), 
		.wb_stb_i			(wbm_strobe_uart), 
		.wb_cyc_i			(wbm_cycle_uart), 
		.wb_sel_i			(wbm_sel_uart[3:0]), 
		.wb_ack_o			(wbm_ack_uart), 
		.int_o				(int_o), 
		.srx_pad_i			(srx_pad_i), 
		.stx_pad_o			(stx_pad_o), 
		.rts_pad_o			(rts_pad_o), 
		.cts_pad_i			(cts_pad_i), 
		.dtr_pad_o			(dtr_pad_o), 
		.dsr_pad_i			(dsr_pad_i), 
		.ri_pad_i			(ri_pad_i));

	always @(negedge clk) begin
	  if ((wbm_cycle_uart & wbm_strobe_uart) & wbm_we_o8) begin
	    uart_dat <= wbm_data_uart_i;
	    adr_uart <= wbm_adr_uart;
	  end
	  if (wbm_ack_uart) begin
	    $display("SSI CONSOLE WRITE 0 %x %x", adr_uart, uart_dat);
	  end
	end
	always @(posedge clk) if (count < 8'hf0) begin
	  rst <= 1'b1;
	  count <= (count + 8'b1);
	end
	else begin
	  rst <= 1'b0;
	end

// synopsys translate_off
`ifdef FPGA_SIM 

reg [47:0] pc0_w ;
reg [47:0] last_pc ;
reg timeout_count_en ;
reg [31:0] timeout_count ;

initial
begin
timeout_count_en = 1'b0 ;
timeout_count = 32'h00000000 ;
end

always @ (negedge clk) begin

//pc0_w[47:0] <= {t2_fpga.t2.spc.tlu_pc_0_d[47:2], 2'b00} ;
pc0_w[47:0] <= {t2_fpga.t2.spc.tlu.pct0.pc_0_w[47:2], 2'b00} ;
last_pc <= pc0_w ;

if(last_pc == 48'h000000083400) begin
$display ("%t : GOOD TRAP Reached ! " ,$time ,last_pc );
        // regreport needs "GOOD End". Do not alter.
$display ("%t: dummyClass[]: Diag Reached GOOD End! (pre regreport checking)",$time);
$display("");
$display ("%t: dummyClass[]: regreport will determine if diag has really PASSED",$time);
$display("");
$display ("%t: dummyClass[]: regreport clock period: 100000 units",$time);
$display("");

$finish ;
end

if(last_pc == 48'h000000083420) begin
$display ("%t : BAD TRAP Reached !  ",$time ,last_pc );
$display ("%t: ERROR : Diag Reached BAD End! (pre regreport checking)",$time);
$display("");
$display ("%t: ERROR : regreport clock period: 100000 units",$time);
$display("");

$finish ;
end


// Logic to catch timeout 

if(last_pc != pc0_w) begin
timeout_count_en <= 1'b0 ;
`ifdef FPGA_MONITOR
$display ("%t : PC VALUE is %h ",$time ,pc0_w) ;
`endif
end

if(last_pc ==  pc0_w) begin
timeout_count_en <= 1'b1;
end

if(timeout_count_en == 1'b1) begin
timeout_count <= timeout_count + 1 ;
end
else if (timeout_count_en == 1'b0) begin
timeout_count <= 32'h00000000 ;
end

if(timeout_count == 32'd100000) begin
$display ("%t : ERROR : Time out reached after 100K idle cycles ! " ,$time ) ;
$display("");
$display ("%t: ERROR : regreport clock period: 100000 units",$time);
$display("");
$finish ;
end


end  // end always


// dump enabler

`include "dump.v"
`endif
// synopsys translate_on 


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module ccx (
  cmp_gclk_c2_ccx_left, 
  cmp_gclk_c2_ccx_right, 
  scan_in, 
  tcu_pce_ov, 
  gl_ccx_clk_stop_left, 
  gl_ccx_clk_stop_right, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  cluster_arst_l, 
  tcu_atpg_mode, 
  scan_out, 
  cpu_rep0_in, 
  cpu_rep0_out, 
  cpu_rep1_in, 
  cpu_rep1_out, 
  ccx_lstg_in, 
  ccx_lstg_out, 
  ccx_rstg_in, 
  ccx_rstg_out, 
  spc0_pcx_data_pa, 
  spc0_pcx_req_pq, 
  spc0_pcx_atm_pq, 
  spc1_pcx_data_pa, 
  spc1_pcx_req_pq, 
  spc1_pcx_atm_pq, 
  spc2_pcx_data_pa, 
  spc2_pcx_req_pq, 
  spc2_pcx_atm_pq, 
  spc3_pcx_data_pa, 
  spc3_pcx_req_pq, 
  spc3_pcx_atm_pq, 
  spc4_pcx_data_pa, 
  spc4_pcx_req_pq, 
  spc4_pcx_atm_pq, 
  spc5_pcx_data_pa, 
  spc5_pcx_req_pq, 
  spc5_pcx_atm_pq, 
  spc6_pcx_data_pa, 
  spc6_pcx_req_pq, 
  spc6_pcx_atm_pq, 
  spc7_pcx_data_pa, 
  spc7_pcx_req_pq, 
  spc7_pcx_atm_pq, 
  io_pcx_stall_pq, 
  sctag0_pcx_stall_pq, 
  sctag1_pcx_stall_pq, 
  sctag2_pcx_stall_pq, 
  sctag3_pcx_stall_pq, 
  sctag4_pcx_stall_pq, 
  sctag5_pcx_stall_pq, 
  sctag6_pcx_stall_pq, 
  sctag7_pcx_stall_pq, 
  pcx_spc0_grant_px, 
  pcx_spc1_grant_px, 
  pcx_spc2_grant_px, 
  pcx_spc3_grant_px, 
  pcx_spc4_grant_px, 
  pcx_spc5_grant_px, 
  pcx_spc6_grant_px, 
  pcx_spc7_grant_px, 
  pcx_fpio_data_px2, 
  pcx_fpio_data_rdy_px1, 
  pcx_sctag0_atm_px1, 
  pcx_sctag0_data_px2, 
  pcx_sctag0_data_rdy_px1, 
  pcx_sctag1_atm_px1, 
  pcx_sctag1_data_px2, 
  pcx_sctag1_data_rdy_px1, 
  pcx_sctag2_atm_px1, 
  pcx_sctag2_data_px2, 
  pcx_sctag2_data_rdy_px1, 
  pcx_sctag3_atm_px1, 
  pcx_sctag3_data_px2, 
  pcx_sctag3_data_rdy_px1, 
  pcx_sctag4_atm_px1, 
  pcx_sctag4_data_px2, 
  pcx_sctag4_data_rdy_px1, 
  pcx_sctag5_atm_px1, 
  pcx_sctag5_data_px2, 
  pcx_sctag5_data_rdy_px1, 
  pcx_sctag6_atm_px1, 
  pcx_sctag6_data_px2, 
  pcx_sctag6_data_rdy_px1, 
  pcx_sctag7_atm_px1, 
  pcx_sctag7_data_px2, 
  pcx_sctag7_data_rdy_px1, 
  io_cpx_data_ca, 
  io_cpx_req_cq, 
  sctag0_cpx_atom_cq, 
  sctag0_cpx_data_ca, 
  sctag0_cpx_req_cq, 
  sctag1_cpx_atom_cq, 
  sctag1_cpx_data_ca, 
  sctag1_cpx_req_cq, 
  sctag2_cpx_atom_cq, 
  sctag2_cpx_data_ca, 
  sctag2_cpx_req_cq, 
  sctag3_cpx_atom_cq, 
  sctag3_cpx_data_ca, 
  sctag3_cpx_req_cq, 
  sctag4_cpx_atom_cq, 
  sctag4_cpx_data_ca, 
  sctag4_cpx_req_cq, 
  sctag5_cpx_atom_cq, 
  sctag5_cpx_data_ca, 
  sctag5_cpx_req_cq, 
  sctag6_cpx_atom_cq, 
  sctag6_cpx_data_ca, 
  sctag6_cpx_req_cq, 
  sctag7_cpx_atom_cq, 
  sctag7_cpx_data_ca, 
  sctag7_cpx_req_cq, 
  cpx_io_grant_cx, 
  cpx_sctag0_grant_cx, 
  cpx_sctag1_grant_cx, 
  cpx_sctag2_grant_cx, 
  cpx_sctag3_grant_cx, 
  cpx_sctag4_grant_cx, 
  cpx_sctag5_grant_cx, 
  cpx_sctag6_grant_cx, 
  cpx_sctag7_grant_cx, 
  cpx_spc0_data_cx2, 
  cpx_spc1_data_cx2, 
  cpx_spc2_data_cx2, 
  cpx_spc3_data_cx2, 
  cpx_spc4_data_cx2, 
  cpx_spc5_data_cx2, 
  cpx_spc6_data_cx2, 
  cpx_spc7_data_cx2);
wire [1:0] scan_in_buf;
wire tcu_pce_ov_buf;
wire tcu_aclk_buf;
wire tcu_bclk_buf;
wire tcu_scan_en_buf;
wire cluster_arst_l_buf;
wire tcu_atpg_mode_buf;
wire array_wr_inhibit_unused;
wire l2clk;
wire ccx_aclk;
wire ccx_bclk;
wire clkgen_scanout;
wire tcu_pce_ov_r;
wire aclk_wmr_r_unused;
wire wmr_protect_r_unused;
wire wmr_r_unused;
wire por_r_unused;
wire cmp_slow_sync_en_r_unused;
wire slow_cmp_sync_en_r_unused;
wire scan_out_0;
wire pcx_scan_out;
wire tstgl_scan_out;
wire scan_out_1;


// globals
//input           gclk;                // PINDEF:RIGHT     
input           cmp_gclk_c2_ccx_left;                // PINDEF:RIGHT     
input           cmp_gclk_c2_ccx_right;                // PINDEF:RIGHT     
input  [1:0]         scan_in;              // PINDEF:RIGHT      arc=l2clk:30 cap=20
input           tcu_pce_ov;           // PINDEF:RIGHT      arc=l2clk:30 cap=20
//input           tcu_clk_stop;         // PINDEF:RIGHT      arc=l2clk:30 cap=20
input           gl_ccx_clk_stop_left;         // PINDEF:RIGHT      arc=l2clk:30 cap=20
input           gl_ccx_clk_stop_right;         // PINDEF:RIGHT      arc=l2clk:30 cap=20
input           tcu_aclk;         // PINDEF:RIGHT
input           tcu_bclk;         // PINDEF:RIGHT
input           tcu_scan_en;      // PINDEF:RIGHT
input           cluster_arst_l;	  // PINDEF:RIGHT	
input           tcu_atpg_mode;	  // PINDEF:RIGHT	
output [1:0]         scan_out;             // PINDEF:LEFT      arc=l2clk:30 cap=20

// top level repeater ports

input [191:0]   cpu_rep0_in;
output [191:0]  cpu_rep0_out;

input [191:0]   cpu_rep1_in;
output [191:0]  cpu_rep1_out;

// TOP LEVEL STAGING FLOPS
input [159:0]   ccx_lstg_in;
output [159:0]   ccx_lstg_out;

input [159:0]   ccx_rstg_in;
output [159:0]   ccx_rstg_out;

// inputs from sparc core to pcx
input [129:0]   spc0_pcx_data_pa;      // PINDEF:TOP      arc=l2clk:100 cap=20
input [8:0]     spc0_pcx_req_pq;       // PINDEF:TOP      arc=l2clk:50  cap=20
input [8:0]     spc0_pcx_atm_pq;       // PINDEF:TOP      arc=l2clk:50  cap=20
input [129:0]   spc1_pcx_data_pa;      // PINDEF:TOP      arc=l2clk:100 cap=20
input [8:0]     spc1_pcx_req_pq;       // PINDEF:TOP      arc=l2clk:50  cap=20
input [8:0]     spc1_pcx_atm_pq;       // PINDEF:TOP      arc=l2clk:50  cap=20
input [129:0]   spc2_pcx_data_pa;      // PINDEF:BOT      arc=l2clk:100 cap=20
input [8:0]     spc2_pcx_req_pq;       // PINDEF:BOT      arc=l2clk:50  cap=20
input [8:0]     spc2_pcx_atm_pq;       // PINDEF:BOT      arc=l2clk:50  cap=20
input [129:0]   spc3_pcx_data_pa;      // PINDEF:BOT      arc=l2clk:100 cap=20
input [8:0]     spc3_pcx_req_pq;       // PINDEF:BOT      arc=l2clk:50  cap=20
input [8:0]     spc3_pcx_atm_pq;       // PINDEF:BOT      arc=l2clk:50  cap=20
input [129:0]   spc4_pcx_data_pa;      // PINDEF:TOP      arc=l2clk:100 cap=20
input [8:0]     spc4_pcx_req_pq;       // PINDEF:TOP      arc=l2clk:50  cap=20
input [8:0]     spc4_pcx_atm_pq;       // PINDEF:TOP      arc=l2clk:50  cap=20
input [129:0]   spc5_pcx_data_pa;      // PINDEF:TOP      arc=l2clk:100 cap=20
input [8:0]     spc5_pcx_req_pq;       // PINDEF:TOP      arc=l2clk:50  cap=20
input [8:0]     spc5_pcx_atm_pq;       // PINDEF:TOP      arc=l2clk:50  cap=20
input [129:0]   spc6_pcx_data_pa;      // PINDEF:BOT      arc=l2clk:100 cap=20
input [8:0]     spc6_pcx_req_pq;       // PINDEF:BOT      arc=l2clk:50  cap=20
input [8:0]     spc6_pcx_atm_pq;       // PINDEF:BOT      arc=l2clk:50  cap=20
input [129:0]   spc7_pcx_data_pa;      // PINDEF:BOT      arc=l2clk:100 cap=20
input [8:0]     spc7_pcx_req_pq;       // PINDEF:BOT      arc=l2clk:50  cap=20
input [8:0]     spc7_pcx_atm_pq;       // PINDEF:BOT      arc=l2clk:50  cap=20

// inputs from l2 to pcx
input                   io_pcx_stall_pq;        // PINDEF:TOP      arc=l2clk:50 cap=20
input                   sctag0_pcx_stall_pq;    // PINDEF:TOP      arc=l2clk:50 cap=20
input                   sctag1_pcx_stall_pq;    // PINDEF:TOP      arc=l2clk:50 cap=20
input                   sctag2_pcx_stall_pq;    // PINDEF:BOT      arc=l2clk:50 cap=20
input                   sctag3_pcx_stall_pq;    // PINDEF:BOT      arc=l2clk:50 cap=20
input                   sctag4_pcx_stall_pq;    // PINDEF:TOP      arc=l2clk:50 cap=20
input                   sctag5_pcx_stall_pq;    // PINDEF:TOP      arc=l2clk:50 cap=20
input                   sctag6_pcx_stall_pq;    // PINDEF:BOT      arc=l2clk:50 cap=20
input                   sctag7_pcx_stall_pq;    // PINDEF:BOT      arc=l2clk:50 cap=20


// outputs from pcx to sparc core
output [8:0]            pcx_spc0_grant_px;      // PINDEF:TOP      arc=l2clk:100 drv=32x
output [8:0]            pcx_spc1_grant_px;      // PINDEF:TOP      arc=l2clk:100 drv=32x
output [8:0]            pcx_spc2_grant_px;      // PINDEF:BOT      arc=l2clk:100 drv=32x
output [8:0]            pcx_spc3_grant_px;      // PINDEF:BOT      arc=l2clk:100 drv=32x
output [8:0]            pcx_spc4_grant_px;      // PINDEF:TOP      arc=l2clk:100 drv=32x
output [8:0]            pcx_spc5_grant_px;      // PINDEF:TOP      arc=l2clk:100 drv=32x
output [8:0]            pcx_spc6_grant_px;      // PINDEF:BOT      arc=l2clk:100 drv=32x
output [8:0]            pcx_spc7_grant_px;      // PINDEF:BOT      arc=l2clk:100 drv=32x


// outputs from pcx to l2
output [129:0]          pcx_fpio_data_px2;              // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_fpio_data_rdy_px1;          // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag0_atm_px1;             // PINDEF:TOP      arc=l2clk:100 drv=32x
output [129:0]          pcx_sctag0_data_px2;            // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag0_data_rdy_px1;        // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag1_atm_px1;             // PINDEF:TOP      arc=l2clk:100 drv=32x
output [129:0]          pcx_sctag1_data_px2;            // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag1_data_rdy_px1;        // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag2_atm_px1;             // PINDEF:BOT      arc=l2clk:100 drv=32x
output [129:0]          pcx_sctag2_data_px2;            // PINDEF:BOT      arc=l2clk:100 drv=32x
output                  pcx_sctag2_data_rdy_px1;        // PINDEF:BOT      arc=l2clk:100 drv=32x
output                  pcx_sctag3_atm_px1;             // PINDEF:BOT      arc=l2clk:100 drv=32x
output [129:0]          pcx_sctag3_data_px2;            // PINDEF:BOT      arc=l2clk:100 drv=32x
output                  pcx_sctag3_data_rdy_px1;        // PINDEF:BOT      arc=l2clk:100 drv=32x
output                  pcx_sctag4_atm_px1;             // PINDEF:TOP      arc=l2clk:100 drv=32x
output [129:0]          pcx_sctag4_data_px2;            // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag4_data_rdy_px1;        // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag5_atm_px1;             // PINDEF:TOP      arc=l2clk:100 drv=32x
output [129:0]          pcx_sctag5_data_px2;            // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag5_data_rdy_px1;        // PINDEF:TOP      arc=l2clk:100 drv=32x
output                  pcx_sctag6_atm_px1;             // PINDEF:BOT      arc=l2clk:100 drv=32x
output [129:0]          pcx_sctag6_data_px2;            // PINDEF:BOT      arc=l2clk:100 drv=32x
output                  pcx_sctag6_data_rdy_px1;        // PINDEF:BOT      arc=l2clk:100 drv=32x
output                  pcx_sctag7_atm_px1;             // PINDEF:BOT      arc=l2clk:100 drv=32x
output [129:0]          pcx_sctag7_data_px2;            // PINDEF:BOT      arc=l2clk:100 drv=32x
output                  pcx_sctag7_data_rdy_px1;        // PINDEF:BOT      arc=l2clk:100 drv=32x


// inputs from l2 to cpx
input [145:0]           io_cpx_data_ca;         // PINDEF:TOP      arc=l2clk:100 cap=20
input [7:0]             io_cpx_req_cq;          // PINDEF:TOP      arc=l2clk:50  cap=20
input                   sctag0_cpx_atom_cq;     // PINDEF:TOP      arc=l2clk:50  cap=20
input [145:0]           sctag0_cpx_data_ca;     // PINDEF:TOP      arc=l2clk:100 cap=20
input [7:0]             sctag0_cpx_req_cq;      // PINDEF:TOP      arc=l2clk:50  cap=20
input                   sctag1_cpx_atom_cq;     // PINDEF:TOP      arc=l2clk:50  cap=20
input [145:0]           sctag1_cpx_data_ca;     // PINDEF:TOP      arc=l2clk:100 cap=20
input [7:0]             sctag1_cpx_req_cq;      // PINDEF:BOT      arc=l2clk:50  cap=20
input                   sctag2_cpx_atom_cq;     // PINDEF:BOT      arc=l2clk:50  cap=20
input [145:0]           sctag2_cpx_data_ca;     // PINDEF:BOT      arc=l2clk:100 cap=20
input [7:0]             sctag2_cpx_req_cq;      // PINDEF:BOT      arc=l2clk:50  cap=20
input                   sctag3_cpx_atom_cq;     // PINDEF:BOT      arc=l2clk:50  cap=20
input [145:0]           sctag3_cpx_data_ca;     // PINDEF:BOT      arc=l2clk:100 cap=20
input [7:0]             sctag3_cpx_req_cq;      // PINDEF:TOP      arc=l2clk:50  cap=20
input                   sctag4_cpx_atom_cq;     // PINDEF:TOP      arc=l2clk:50  cap=20
input [145:0]           sctag4_cpx_data_ca;     // PINDEF:TOP      arc=l2clk:100 cap=20
input [7:0]             sctag4_cpx_req_cq;      // PINDEF:TOP      arc=l2clk:50  cap=20
input                   sctag5_cpx_atom_cq;     // PINDEF:TOP      arc=l2clk:50  cap=20
input [145:0]           sctag5_cpx_data_ca;     // PINDEF:TOP      arc=l2clk:100 cap=20
input [7:0]             sctag5_cpx_req_cq;      // PINDEF:TOP      arc=l2clk:50  cap=20
input                   sctag6_cpx_atom_cq;     // PINDEF:BOT      arc=l2clk:50  cap=20
input [145:0]           sctag6_cpx_data_ca;     // PINDEF:BOT      arc=l2clk:100 cap=20
input [7:0]             sctag6_cpx_req_cq;      // PINDEF:BOT      arc=l2clk:50  cap=20
input                   sctag7_cpx_atom_cq;     // PINDEF:BOT      arc=l2clk:50  cap=20
input [145:0]           sctag7_cpx_data_ca;     // PINDEF:BOT      arc=l2clk:100 cap=20
input [7:0]             sctag7_cpx_req_cq;      // PINDEF:BOT      arc=l2clk:50  cap=20


// outputs from cpx to l2
output [7:0]            cpx_io_grant_cx;        // PINDEF:TOP      arc=l2clk:100 drv=32x
output [7:0]            cpx_sctag0_grant_cx;    // PINDEF:TOP      arc=l2clk:100 drv=32x
output [7:0]            cpx_sctag1_grant_cx;    // PINDEF:TOP      arc=l2clk:100 drv=32x
output [7:0]            cpx_sctag2_grant_cx;    // PINDEF:BOT      arc=l2clk:100 drv=32x
output [7:0]            cpx_sctag3_grant_cx;    // PINDEF:BOT      arc=l2clk:100 drv=32x
output [7:0]            cpx_sctag4_grant_cx;    // PINDEF:TOP      arc=l2clk:100 drv=32x
output [7:0]            cpx_sctag5_grant_cx;    // PINDEF:TOP      arc=l2clk:100 drv=32x
output [7:0]            cpx_sctag6_grant_cx;    // PINDEF:BOT      arc=l2clk:100 drv=32x
output [7:0]            cpx_sctag7_grant_cx;    // PINDEF:BOT      arc=l2clk:100 drv=32x

// outputs from cpx to sparc core
output [145:0]          cpx_spc0_data_cx2;      // PINDEF:TOP      arc=l2clk:100 drv=32x
output [145:0]          cpx_spc1_data_cx2;      // PINDEF:TOP      arc=l2clk:100 drv=32x
output [145:0]          cpx_spc2_data_cx2;      // PINDEF:BOT      arc=l2clk:100 drv=32x
output [145:0]          cpx_spc3_data_cx2;      // PINDEF:BOT      arc=l2clk:100 drv=32x
output [145:0]          cpx_spc4_data_cx2;      // PINDEF:TOP      arc=l2clk:100 drv=32x
output [145:0]          cpx_spc5_data_cx2;      // PINDEF:TOP      arc=l2clk:100 drv=32x
output [145:0]          cpx_spc6_data_cx2;      // PINDEF:BOT      arc=l2clk:100 drv=32x
output [145:0]          cpx_spc7_data_cx2;      // PINDEF:BOT      arc=l2clk:100 drv=32x


// isolation buffer for test/scan/clk signals

ccx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_buf_test_r     (
	.din	({scan_in[1:0],tcu_pce_ov, tcu_aclk, 
              tcu_bclk, tcu_scan_en, cluster_arst_l,tcu_atpg_mode}),
	.dout	({scan_in_buf[1:0],tcu_pce_ov_buf,tcu_aclk_buf, 
              tcu_bclk_buf, tcu_scan_en_buf, cluster_arst_l_buf,tcu_atpg_mode_buf})
);


clkgen_ccx_cmp clk_ccx
(
 .array_wr_inhibit(array_wr_inhibit_unused),
 .tcu_atpg_mode(tcu_atpg_mode_buf),
 .tcu_wr_inhibit(1'b0),
 .l2clk(l2clk),
 .aclk(ccx_aclk),
 .bclk(ccx_bclk),
 .scan_out(clkgen_scanout),
 .pce_ov(tcu_pce_ov_r),
 .aclk_wmr(aclk_wmr_r_unused),
 .wmr_protect(wmr_protect_r_unused),
 .wmr_(wmr_r_unused),
 .por_(por_r_unused),
 .cmp_slow_sync_en(cmp_slow_sync_en_r_unused),
 .slow_cmp_sync_en(slow_cmp_sync_en_r_unused),
 .tcu_clk_stop_left(gl_ccx_clk_stop_left),
 .tcu_clk_stop_right(gl_ccx_clk_stop_right),
 .tcu_pce_ov(tcu_pce_ov_buf),
 .rst_wmr_protect(1'b0),
 .rst_wmr_(1'b1),
 .rst_por_(1'b1),
 .ccu_cmp_slow_sync_en(1'b0),
 .ccu_slow_cmp_sync_en(1'b0),
 .tcu_div_bypass_left(1'b0),
 .tcu_div_bypass_right(1'b0),
 .ccu_div_ph(1'b1),
 .cluster_div_en(1'b0),
 .gclk_left(cmp_gclk_c2_ccx_left),
 .gclk_right(cmp_gclk_c2_ccx_right),
 .cluster_arst_l_left(cluster_arst_l_buf),
 .cluster_arst_l_right(cluster_arst_l_buf),
 .clk_ext(1'b0),
 .ccu_serdes_dtm(1'b0),
 .tcu_aclk(tcu_aclk_buf),
 .tcu_bclk(tcu_bclk_buf),
 .scan_en(tcu_scan_en_buf),
 .scan_in(scan_in_buf[0]) 
 );
                       
//assign cmp_gclk_c2_ccx_left_unused = cmp_gclk_c2_ccx_left;
//assign gl_ccx_clk_stop_left_unused = gl_ccx_clk_stop_left;


/*
 cpx AUTO_TEMPLATE(
 .cpx_spc0_data_cx2 (spc0_data_cx2[149:0]),
 .cpx_spc1_data_cx2 (spc1_data_cx2[149:0]),
 .cpx_spc2_data_cx2 (spc2_data_cx2[149:0]),
 .cpx_spc3_data_cx2 (spc3_data_cx2[149:0]),
 .cpx_spc4_data_cx2 (spc4_data_cx2[149:0]),
 .cpx_spc5_data_cx2 (spc5_data_cx2[149:0]),
 .cpx_spc6_data_cx2 (spc6_data_cx2[149:0]),
 .cpx_spc7_data_cx2 (spc7_data_cx2[149:0]));
 */
cpx cpx (/*AUTOINST*/
         // Outputs
         .cpx_io_grant_cx               (cpx_io_grant_cx[7:0]),
         .cpx_sctag0_grant_cx           (cpx_sctag0_grant_cx[7:0]),
         .cpx_sctag1_grant_cx           (cpx_sctag1_grant_cx[7:0]),
         .cpx_sctag2_grant_cx           (cpx_sctag2_grant_cx[7:0]),
         .cpx_sctag3_grant_cx           (cpx_sctag3_grant_cx[7:0]),
         .cpx_sctag4_grant_cx           (cpx_sctag4_grant_cx[7:0]),
         .cpx_sctag5_grant_cx           (cpx_sctag5_grant_cx[7:0]),
         .cpx_sctag6_grant_cx           (cpx_sctag6_grant_cx[7:0]),
         .cpx_sctag7_grant_cx           (cpx_sctag7_grant_cx[7:0]),
         .cpx_spc0_data_cx2             (cpx_spc0_data_cx2[145:0]),  // Templated
         .cpx_spc1_data_cx2             (cpx_spc1_data_cx2[145:0]),  // Templated
         .cpx_spc2_data_cx2             (cpx_spc2_data_cx2[145:0]),  // Templated
         .cpx_spc3_data_cx2             (cpx_spc3_data_cx2[145:0]),  // Templated
         .cpx_spc4_data_cx2             (cpx_spc4_data_cx2[145:0]),  // Templated
         .cpx_spc5_data_cx2             (cpx_spc5_data_cx2[145:0]),  // Templated
         .cpx_spc6_data_cx2             (cpx_spc6_data_cx2[145:0]),  // Templated
         .cpx_spc7_data_cx2             (cpx_spc7_data_cx2[145:0]),  // Templated
         // Inputs
         .io_cpx_data_ca                (io_cpx_data_ca[145:0]),
         .io_cpx_req_cq                 (io_cpx_req_cq[7:0]),
         .sctag0_cpx_atom_cq            (sctag0_cpx_atom_cq),
         .sctag0_cpx_data_ca            (sctag0_cpx_data_ca[145:0]),
         .sctag0_cpx_req_cq             (sctag0_cpx_req_cq[7:0]),
         .sctag1_cpx_atom_cq            (sctag1_cpx_atom_cq),
         .sctag1_cpx_data_ca            (sctag1_cpx_data_ca[145:0]),
         .sctag1_cpx_req_cq             (sctag1_cpx_req_cq[7:0]),
         .sctag2_cpx_atom_cq            (sctag2_cpx_atom_cq),
         .sctag2_cpx_data_ca            (sctag2_cpx_data_ca[145:0]),
         .sctag2_cpx_req_cq             (sctag2_cpx_req_cq[7:0]),
         .sctag3_cpx_atom_cq            (sctag3_cpx_atom_cq),
         .sctag3_cpx_data_ca            (sctag3_cpx_data_ca[145:0]),
         .sctag3_cpx_req_cq             (sctag3_cpx_req_cq[7:0]),
         .sctag4_cpx_atom_cq            (sctag4_cpx_atom_cq),
         .sctag4_cpx_data_ca            (sctag4_cpx_data_ca[145:0]),
         .sctag4_cpx_req_cq             (sctag4_cpx_req_cq[7:0]),
         .sctag5_cpx_atom_cq            (sctag5_cpx_atom_cq),
         .sctag5_cpx_data_ca            (sctag5_cpx_data_ca[145:0]),
         .sctag5_cpx_req_cq             (sctag5_cpx_req_cq[7:0]),
         .sctag6_cpx_atom_cq            (sctag6_cpx_atom_cq),
         .sctag6_cpx_data_ca            (sctag6_cpx_data_ca[145:0]),
         .sctag6_cpx_req_cq             (sctag6_cpx_req_cq[7:0]),
         .sctag7_cpx_atom_cq            (sctag7_cpx_atom_cq),
         .sctag7_cpx_data_ca            (sctag7_cpx_data_ca[145:0]),
         .sctag7_cpx_req_cq             (sctag7_cpx_req_cq[7:0]),
         .scan_in(clkgen_scanout),
         .scan_out(scan_out_0),
         .l2clk                         (l2clk),
         .ccx_aclk (ccx_aclk),
         .ccx_bclk (ccx_bclk),
         .tcu_scan_en                   (tcu_scan_en_buf),
         .tcu_pce_ov                    (tcu_pce_ov_r));

pcx pcx (/*AUTOINST*/
         // Outputs
         .pcx_fpio_data_px2             (pcx_fpio_data_px2[129:0]),
         .pcx_fpio_data_rdy_px1         (pcx_fpio_data_rdy_px1),
         .pcx_sctag0_atm_px1            (pcx_sctag0_atm_px1),
         .pcx_sctag0_data_px2           (pcx_sctag0_data_px2[129:0]),
         .pcx_sctag0_data_rdy_px1       (pcx_sctag0_data_rdy_px1),
         .pcx_sctag1_atm_px1            (pcx_sctag1_atm_px1),
         .pcx_sctag1_data_px2           (pcx_sctag1_data_px2[129:0]),
         .pcx_sctag1_data_rdy_px1       (pcx_sctag1_data_rdy_px1),
         .pcx_sctag2_atm_px1            (pcx_sctag2_atm_px1),
         .pcx_sctag2_data_px2           (pcx_sctag2_data_px2[129:0]),
         .pcx_sctag2_data_rdy_px1       (pcx_sctag2_data_rdy_px1),
         .pcx_sctag3_atm_px1            (pcx_sctag3_atm_px1),
         .pcx_sctag3_data_px2           (pcx_sctag3_data_px2[129:0]),
         .pcx_sctag3_data_rdy_px1       (pcx_sctag3_data_rdy_px1),
         .pcx_sctag4_atm_px1            (pcx_sctag4_atm_px1),
         .pcx_sctag4_data_px2           (pcx_sctag4_data_px2[129:0]),
         .pcx_sctag4_data_rdy_px1       (pcx_sctag4_data_rdy_px1),
         .pcx_sctag5_atm_px1            (pcx_sctag5_atm_px1),
         .pcx_sctag5_data_px2           (pcx_sctag5_data_px2[129:0]),
         .pcx_sctag5_data_rdy_px1       (pcx_sctag5_data_rdy_px1),
         .pcx_sctag6_atm_px1            (pcx_sctag6_atm_px1),
         .pcx_sctag6_data_px2           (pcx_sctag6_data_px2[129:0]),
         .pcx_sctag6_data_rdy_px1       (pcx_sctag6_data_rdy_px1),
         .pcx_sctag7_atm_px1            (pcx_sctag7_atm_px1),
         .pcx_sctag7_data_px2           (pcx_sctag7_data_px2[129:0]),
         .pcx_sctag7_data_rdy_px1       (pcx_sctag7_data_rdy_px1),
         .pcx_spc0_grant_px             (pcx_spc0_grant_px[8:0]),
         .pcx_spc1_grant_px             (pcx_spc1_grant_px[8:0]),
         .pcx_spc2_grant_px             (pcx_spc2_grant_px[8:0]),
         .pcx_spc3_grant_px             (pcx_spc3_grant_px[8:0]),
         .pcx_spc4_grant_px             (pcx_spc4_grant_px[8:0]),
         .pcx_spc5_grant_px             (pcx_spc5_grant_px[8:0]),
         .pcx_spc6_grant_px             (pcx_spc6_grant_px[8:0]),
         .pcx_spc7_grant_px             (pcx_spc7_grant_px[8:0]),
         // Inputs
         .io_pcx_stall_pq               (io_pcx_stall_pq),
         .sctag0_pcx_stall_pq           (sctag0_pcx_stall_pq),
         .sctag1_pcx_stall_pq           (sctag1_pcx_stall_pq),
         .sctag2_pcx_stall_pq           (sctag2_pcx_stall_pq),
         .sctag3_pcx_stall_pq           (sctag3_pcx_stall_pq),
         .sctag4_pcx_stall_pq           (sctag4_pcx_stall_pq),
         .sctag5_pcx_stall_pq           (sctag5_pcx_stall_pq),
         .sctag6_pcx_stall_pq           (sctag6_pcx_stall_pq),
         .sctag7_pcx_stall_pq           (sctag7_pcx_stall_pq),
         .spc0_pcx_data_pa              (spc0_pcx_data_pa[129:0]),
         .spc0_pcx_req_pq               (spc0_pcx_req_pq[8:0]),
         .spc0_pcx_atm_pq               (spc0_pcx_atm_pq[8:0]),
         .spc1_pcx_data_pa              (spc1_pcx_data_pa[129:0]),
         .spc1_pcx_req_pq               (spc1_pcx_req_pq[8:0]),
         .spc1_pcx_atm_pq               (spc1_pcx_atm_pq[8:0]),
         .spc2_pcx_data_pa              (spc2_pcx_data_pa[129:0]),
         .spc2_pcx_req_pq               (spc2_pcx_req_pq[8:0]),
         .spc2_pcx_atm_pq               (spc2_pcx_atm_pq[8:0]),
         .spc3_pcx_data_pa              (spc3_pcx_data_pa[129:0]),
         .spc3_pcx_req_pq               (spc3_pcx_req_pq[8:0]),
         .spc3_pcx_atm_pq               (spc3_pcx_atm_pq[8:0]),
         .spc4_pcx_data_pa              (spc4_pcx_data_pa[129:0]),
         .spc4_pcx_req_pq               (spc4_pcx_req_pq[8:0]),
         .spc4_pcx_atm_pq               (spc4_pcx_atm_pq[8:0]),
         .spc5_pcx_data_pa              (spc5_pcx_data_pa[129:0]),
         .spc5_pcx_req_pq               (spc5_pcx_req_pq[8:0]),
         .spc5_pcx_atm_pq               (spc5_pcx_atm_pq[8:0]),
         .spc6_pcx_data_pa              (spc6_pcx_data_pa[129:0]),
         .spc6_pcx_req_pq               (spc6_pcx_req_pq[8:0]),
         .spc6_pcx_atm_pq               (spc6_pcx_atm_pq[8:0]),
         .spc7_pcx_data_pa              (spc7_pcx_data_pa[129:0]),
         .spc7_pcx_req_pq               (spc7_pcx_req_pq[8:0]),
         .spc7_pcx_atm_pq               (spc7_pcx_atm_pq[8:0]),
         .scan_in(scan_in_buf[1]),
         .scan_out(pcx_scan_out),
         .l2clk                         (l2clk),
         .ccx_aclk (ccx_aclk),
         .ccx_bclk (ccx_bclk),
         .tcu_scan_en                   (tcu_scan_en_buf),
         .tcu_pce_ov                    (tcu_pce_ov_r));


// top level repeaters

ccx_trep trep0(
              .cpu_rep_in (cpu_rep0_in[191:0]),
              .cpu_rep_out (cpu_rep0_out[191:0]));

ccx_trep trep1(
              .cpu_rep_in (cpu_rep1_in[191:0]),
              .cpu_rep_out (cpu_rep1_out[191:0]));


// top level staging flops

ccx_tstg tstgl (
	.din	(ccx_lstg_in[159:0]),
	.dout	(ccx_lstg_out[159:0]),
        .local_stop (1'b0),
         .scan_in(pcx_scan_out),
         .scan_out(tstgl_scan_out),
         .l2clk                         (l2clk),
         .tcu_aclk (ccx_aclk),
         .tcu_bclk (ccx_bclk),
         .tcu_scan_en                   (tcu_scan_en_buf),
         .tcu_pce_ov                    (tcu_pce_ov_r));

ccx_tstg tstgr (
	.din	(ccx_rstg_in[159:0]),
	.dout	(ccx_rstg_out[159:0]),
        .local_stop (1'b0),
         .scan_in(tstgl_scan_out),
         .scan_out(scan_out_1),
         .l2clk                         (l2clk),
         .tcu_aclk (ccx_aclk),
         .tcu_bclk (ccx_bclk),
         .tcu_scan_en                   (tcu_scan_en_buf),
         .tcu_pce_ov                    (tcu_pce_ov_r));

// buffer scanout

ccx_buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_buf_scan     (
	.din	({scan_out_1, scan_out_0}),
	.dout	({scan_out[1:0]})
);
                                                               
              
endmodule // ccx

//
//   buff macro
//
//


module ccx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 (
  din,
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   invert macro
//
//


/*

module ccx_inv_macro__dinv_32x__stack_150c__width_150 (
  din, 
  dout);
  input [149:0] din;
  output [149:0] dout;


inv #(150)  d0_0 (
.in(din[149:0]),
.out(dout[149:0])
);


endmodule

*/


//
//   buff macro
//
//


module ccx_buff_macro__dbuff_32x__rep_1__stack_none__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module ccx(cmp_gclk_c2_ccx_left, cmp_gclk_c2_ccx_right, scan_in, tcu_pce_ov, 
	gl_ccx_clk_stop_left, gl_ccx_clk_stop_right, tcu_aclk, tcu_bclk, 
	tcu_scan_en, cluster_arst_l, tcu_atpg_mode, scan_out, cpu_rep0_in, 
	cpu_rep0_out, cpu_rep1_in, cpu_rep1_out, ccx_lstg_in, ccx_lstg_out, 
	ccx_rstg_in, ccx_rstg_out, spc0_pcx_data_pa, spc0_pcx_req_pq, 
	spc0_pcx_atm_pq, spc1_pcx_data_pa, spc1_pcx_req_pq, spc1_pcx_atm_pq, 
	spc2_pcx_data_pa, spc2_pcx_req_pq, spc2_pcx_atm_pq, spc3_pcx_data_pa, 
	spc3_pcx_req_pq, spc3_pcx_atm_pq, spc4_pcx_data_pa, spc4_pcx_req_pq, 
	spc4_pcx_atm_pq, spc5_pcx_data_pa, spc5_pcx_req_pq, spc5_pcx_atm_pq, 
	spc6_pcx_data_pa, spc6_pcx_req_pq, spc6_pcx_atm_pq, spc7_pcx_data_pa, 
	spc7_pcx_req_pq, spc7_pcx_atm_pq, io_pcx_stall_pq, sctag0_pcx_stall_pq, 
	sctag1_pcx_stall_pq, sctag2_pcx_stall_pq, sctag3_pcx_stall_pq, 
	sctag4_pcx_stall_pq, sctag5_pcx_stall_pq, sctag6_pcx_stall_pq, 
	sctag7_pcx_stall_pq, pcx_spc0_grant_px, pcx_spc1_grant_px, 
	pcx_spc2_grant_px, pcx_spc3_grant_px, pcx_spc4_grant_px, 
	pcx_spc5_grant_px, pcx_spc6_grant_px, pcx_spc7_grant_px, 
	pcx_fpio_data_px2, pcx_fpio_data_rdy_px1, pcx_sctag0_atm_px1, 
	pcx_sctag0_data_px2, pcx_sctag0_data_rdy_px1, pcx_sctag1_atm_px1, 
	pcx_sctag1_data_px2, pcx_sctag1_data_rdy_px1, pcx_sctag2_atm_px1, 
	pcx_sctag2_data_px2, pcx_sctag2_data_rdy_px1, pcx_sctag3_atm_px1, 
	pcx_sctag3_data_px2, pcx_sctag3_data_rdy_px1, pcx_sctag4_atm_px1, 
	pcx_sctag4_data_px2, pcx_sctag4_data_rdy_px1, pcx_sctag5_atm_px1, 
	pcx_sctag5_data_px2, pcx_sctag5_data_rdy_px1, pcx_sctag6_atm_px1, 
	pcx_sctag6_data_px2, pcx_sctag6_data_rdy_px1, pcx_sctag7_atm_px1, 
	pcx_sctag7_data_px2, pcx_sctag7_data_rdy_px1, io_cpx_data_ca, 
	io_cpx_req_cq, sctag0_cpx_atom_cq, sctag0_cpx_data_ca, 
	sctag0_cpx_req_cq, sctag1_cpx_atom_cq, sctag1_cpx_data_ca, 
	sctag1_cpx_req_cq, sctag2_cpx_atom_cq, sctag2_cpx_data_ca, 
	sctag2_cpx_req_cq, sctag3_cpx_atom_cq, sctag3_cpx_data_ca, 
	sctag3_cpx_req_cq, sctag4_cpx_atom_cq, sctag4_cpx_data_ca, 
	sctag4_cpx_req_cq, sctag5_cpx_atom_cq, sctag5_cpx_data_ca, 
	sctag5_cpx_req_cq, sctag6_cpx_atom_cq, sctag6_cpx_data_ca, 
	sctag6_cpx_req_cq, sctag7_cpx_atom_cq, sctag7_cpx_data_ca, 
	sctag7_cpx_req_cq, cpx_io_grant_cx, cpx_sctag0_grant_cx, 
	cpx_sctag1_grant_cx, cpx_sctag2_grant_cx, cpx_sctag3_grant_cx, 
	cpx_sctag4_grant_cx, cpx_sctag5_grant_cx, cpx_sctag6_grant_cx, 
	cpx_sctag7_grant_cx, cpx_spc0_data_cx2, cpx_spc1_data_cx2, 
	cpx_spc2_data_cx2, cpx_spc3_data_cx2, cpx_spc4_data_cx2, 
	cpx_spc5_data_cx2, cpx_spc6_data_cx2, cpx_spc7_data_cx2);

	input			cmp_gclk_c2_ccx_left;
	input			cmp_gclk_c2_ccx_right;
	input	[1:0]		scan_in;
	input			tcu_pce_ov;
	input			gl_ccx_clk_stop_left;
	input			gl_ccx_clk_stop_right;
	input			tcu_aclk;
	input			tcu_bclk;
	input			tcu_scan_en;
	input			cluster_arst_l;
	input			tcu_atpg_mode;
	output	[1:0]		scan_out;
	input	[191:0]		cpu_rep0_in;
	output	[191:0]		cpu_rep0_out;
	input	[191:0]		cpu_rep1_in;
	output	[191:0]		cpu_rep1_out;
	input	[159:0]		ccx_lstg_in;
	output	[159:0]		ccx_lstg_out;
	input	[159:0]		ccx_rstg_in;
	output	[159:0]		ccx_rstg_out;
	input	[129:0]		spc0_pcx_data_pa;
	input	[8:0]		spc0_pcx_req_pq;
	input	[8:0]		spc0_pcx_atm_pq;
	input	[129:0]		spc1_pcx_data_pa;
	input	[8:0]		spc1_pcx_req_pq;
	input	[8:0]		spc1_pcx_atm_pq;
	input	[129:0]		spc2_pcx_data_pa;
	input	[8:0]		spc2_pcx_req_pq;
	input	[8:0]		spc2_pcx_atm_pq;
	input	[129:0]		spc3_pcx_data_pa;
	input	[8:0]		spc3_pcx_req_pq;
	input	[8:0]		spc3_pcx_atm_pq;
	input	[129:0]		spc4_pcx_data_pa;
	input	[8:0]		spc4_pcx_req_pq;
	input	[8:0]		spc4_pcx_atm_pq;
	input	[129:0]		spc5_pcx_data_pa;
	input	[8:0]		spc5_pcx_req_pq;
	input	[8:0]		spc5_pcx_atm_pq;
	input	[129:0]		spc6_pcx_data_pa;
	input	[8:0]		spc6_pcx_req_pq;
	input	[8:0]		spc6_pcx_atm_pq;
	input	[129:0]		spc7_pcx_data_pa;
	input	[8:0]		spc7_pcx_req_pq;
	input	[8:0]		spc7_pcx_atm_pq;
	input			io_pcx_stall_pq;
	input			sctag0_pcx_stall_pq;
	input			sctag1_pcx_stall_pq;
	input			sctag2_pcx_stall_pq;
	input			sctag3_pcx_stall_pq;
	input			sctag4_pcx_stall_pq;
	input			sctag5_pcx_stall_pq;
	input			sctag6_pcx_stall_pq;
	input			sctag7_pcx_stall_pq;
	output	[8:0]		pcx_spc0_grant_px;
	output	[8:0]		pcx_spc1_grant_px;
	output	[8:0]		pcx_spc2_grant_px;
	output	[8:0]		pcx_spc3_grant_px;
	output	[8:0]		pcx_spc4_grant_px;
	output	[8:0]		pcx_spc5_grant_px;
	output	[8:0]		pcx_spc6_grant_px;
	output	[8:0]		pcx_spc7_grant_px;
	output	[129:0]		pcx_fpio_data_px2;
	output			pcx_fpio_data_rdy_px1;
	output			pcx_sctag0_atm_px1;
	output	[129:0]		pcx_sctag0_data_px2;
	output			pcx_sctag0_data_rdy_px1;
	output			pcx_sctag1_atm_px1;
	output	[129:0]		pcx_sctag1_data_px2;
	output			pcx_sctag1_data_rdy_px1;
	output			pcx_sctag2_atm_px1;
	output	[129:0]		pcx_sctag2_data_px2;
	output			pcx_sctag2_data_rdy_px1;
	output			pcx_sctag3_atm_px1;
	output	[129:0]		pcx_sctag3_data_px2;
	output			pcx_sctag3_data_rdy_px1;
	output			pcx_sctag4_atm_px1;
	output	[129:0]		pcx_sctag4_data_px2;
	output			pcx_sctag4_data_rdy_px1;
	output			pcx_sctag5_atm_px1;
	output	[129:0]		pcx_sctag5_data_px2;
	output			pcx_sctag5_data_rdy_px1;
	output			pcx_sctag6_atm_px1;
	output	[129:0]		pcx_sctag6_data_px2;
	output			pcx_sctag6_data_rdy_px1;
	output			pcx_sctag7_atm_px1;
	output	[129:0]		pcx_sctag7_data_px2;
	output			pcx_sctag7_data_rdy_px1;
	input	[145:0]		io_cpx_data_ca;
	input	[7:0]		io_cpx_req_cq;
	input			sctag0_cpx_atom_cq;
	input	[145:0]		sctag0_cpx_data_ca;
	input	[7:0]		sctag0_cpx_req_cq;
	input			sctag1_cpx_atom_cq;
	input	[145:0]		sctag1_cpx_data_ca;
	input	[7:0]		sctag1_cpx_req_cq;
	input			sctag2_cpx_atom_cq;
	input	[145:0]		sctag2_cpx_data_ca;
	input	[7:0]		sctag2_cpx_req_cq;
	input			sctag3_cpx_atom_cq;
	input	[145:0]		sctag3_cpx_data_ca;
	input	[7:0]		sctag3_cpx_req_cq;
	input			sctag4_cpx_atom_cq;
	input	[145:0]		sctag4_cpx_data_ca;
	input	[7:0]		sctag4_cpx_req_cq;
	input			sctag5_cpx_atom_cq;
	input	[145:0]		sctag5_cpx_data_ca;
	input	[7:0]		sctag5_cpx_req_cq;
	input			sctag6_cpx_atom_cq;
	input	[145:0]		sctag6_cpx_data_ca;
	input	[7:0]		sctag6_cpx_req_cq;
	input			sctag7_cpx_atom_cq;
	input	[145:0]		sctag7_cpx_data_ca;
	input	[7:0]		sctag7_cpx_req_cq;
	output	[7:0]		cpx_io_grant_cx;
	output	[7:0]		cpx_sctag0_grant_cx;
	output	[7:0]		cpx_sctag1_grant_cx;
	output	[7:0]		cpx_sctag2_grant_cx;
	output	[7:0]		cpx_sctag3_grant_cx;
	output	[7:0]		cpx_sctag4_grant_cx;
	output	[7:0]		cpx_sctag5_grant_cx;
	output	[7:0]		cpx_sctag6_grant_cx;
	output	[7:0]		cpx_sctag7_grant_cx;
	output	[145:0]		cpx_spc0_data_cx2;
	output	[145:0]		cpx_spc1_data_cx2;
	output	[145:0]		cpx_spc2_data_cx2;
	output	[145:0]		cpx_spc3_data_cx2;
	output	[145:0]		cpx_spc4_data_cx2;
	output	[145:0]		cpx_spc5_data_cx2;
	output	[145:0]		cpx_spc6_data_cx2;
	output	[145:0]		cpx_spc7_data_cx2;

	wire	[1:0]		scan_in_buf;
	wire			tcu_pce_ov_buf;
	wire			tcu_aclk_buf;
	wire			tcu_bclk_buf;
	wire			tcu_scan_en_buf;
	wire			cluster_arst_l_buf;
	wire			tcu_atpg_mode_buf;
	wire			array_wr_inhibit_unused;
	wire			l2clk;
	wire			ccx_aclk;
	wire			ccx_bclk;
	wire			clkgen_scanout;
	wire			tcu_pce_ov_r;
	wire			aclk_wmr_r_unused;
	wire			wmr_protect_r_unused;
	wire			wmr_r_unused;
	wire			por_r_unused;
	wire			cmp_slow_sync_en_r_unused;
	wire			slow_cmp_sync_en_r_unused;
	wire			scan_out_0;
	wire			pcx_scan_out;
	wire			tstgl_scan_out;
	wire			scan_out_1;

	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_buf_test_r(
		.din				({scan_in[1:0], tcu_pce_ov,
		tcu_aclk, tcu_bclk, tcu_scan_en, cluster_arst_l,
		tcu_atpg_mode}), 
		.dout				({scan_in_buf[1:0],
		tcu_pce_ov_buf, tcu_aclk_buf, tcu_bclk_buf, tcu_scan_en_buf,
		cluster_arst_l_buf, tcu_atpg_mode_buf}));
	clkgen_ccx_cmp clk_ccx(
		.array_wr_inhibit		(array_wr_inhibit_unused), 
		.tcu_atpg_mode			(tcu_atpg_mode_buf), 
		.tcu_wr_inhibit			(1'b0), 
		.l2clk				(l2clk), 
		.aclk				(ccx_aclk), 
		.bclk				(ccx_bclk), 
		.scan_out			(clkgen_scanout), 
		.pce_ov				(tcu_pce_ov_r), 
		.aclk_wmr			(aclk_wmr_r_unused), 
		.wmr_protect			(wmr_protect_r_unused), 
		.wmr_				(wmr_r_unused), 
		.por_				(por_r_unused), 
		.cmp_slow_sync_en		(cmp_slow_sync_en_r_unused), 
		.slow_cmp_sync_en		(slow_cmp_sync_en_r_unused), 
		.tcu_clk_stop_left		(gl_ccx_clk_stop_left), 
		.tcu_clk_stop_right		(gl_ccx_clk_stop_right), 
		.tcu_pce_ov			(tcu_pce_ov_buf), 
		.rst_wmr_protect		(1'b0), 
		.rst_wmr_			(1'b1), 
		.rst_por_			(1'b1), 
		.ccu_cmp_slow_sync_en		(1'b0), 
		.ccu_slow_cmp_sync_en		(1'b0), 
		.tcu_div_bypass_left		(1'b0), 
		.tcu_div_bypass_right		(1'b0), 
		.ccu_div_ph			(1'b1), 
		.cluster_div_en			(1'b0), 
		.gclk_left			(cmp_gclk_c2_ccx_left), 
		.gclk_right			(cmp_gclk_c2_ccx_right), 
		.cluster_arst_l_left		(cluster_arst_l_buf), 
		.cluster_arst_l_right		(cluster_arst_l_buf), 
		.clk_ext			(1'b0), 
		.ccu_serdes_dtm			(1'b0), 
		.tcu_aclk			(tcu_aclk_buf), 
		.tcu_bclk			(tcu_bclk_buf), 
		.scan_en			(tcu_scan_en_buf), 
		.scan_in			(scan_in_buf[0]));
	cpx cpx(
		.cpx_io_grant_cx		(cpx_io_grant_cx[7:0]), 
		.cpx_sctag0_grant_cx		(cpx_sctag0_grant_cx[7:0]), 
		.cpx_sctag1_grant_cx		(cpx_sctag1_grant_cx[7:0]), 
		.cpx_sctag2_grant_cx		(cpx_sctag2_grant_cx[7:0]), 
		.cpx_sctag3_grant_cx		(cpx_sctag3_grant_cx[7:0]), 
		.cpx_sctag4_grant_cx		(cpx_sctag4_grant_cx[7:0]), 
		.cpx_sctag5_grant_cx		(cpx_sctag5_grant_cx[7:0]), 
		.cpx_sctag6_grant_cx		(cpx_sctag6_grant_cx[7:0]), 
		.cpx_sctag7_grant_cx		(cpx_sctag7_grant_cx[7:0]), 
		.cpx_spc0_data_cx2		(cpx_spc0_data_cx2[145:0]), 
		.cpx_spc1_data_cx2		(cpx_spc1_data_cx2[145:0]), 
		.cpx_spc2_data_cx2		(cpx_spc2_data_cx2[145:0]), 
		.cpx_spc3_data_cx2		(cpx_spc3_data_cx2[145:0]), 
		.cpx_spc4_data_cx2		(cpx_spc4_data_cx2[145:0]), 
		.cpx_spc5_data_cx2		(cpx_spc5_data_cx2[145:0]), 
		.cpx_spc6_data_cx2		(cpx_spc6_data_cx2[145:0]), 
		.cpx_spc7_data_cx2		(cpx_spc7_data_cx2[145:0]), 
		.io_cpx_data_ca			(io_cpx_data_ca[145:0]), 
		.io_cpx_req_cq			(io_cpx_req_cq[7:0]), 
		.sctag0_cpx_atom_cq		(sctag0_cpx_atom_cq), 
		.sctag0_cpx_data_ca		(sctag0_cpx_data_ca[145:0]), 
		.sctag0_cpx_req_cq		(sctag0_cpx_req_cq[7:0]), 
		.sctag1_cpx_atom_cq		(sctag1_cpx_atom_cq), 
		.sctag1_cpx_data_ca		(sctag1_cpx_data_ca[145:0]), 
		.sctag1_cpx_req_cq		(sctag1_cpx_req_cq[7:0]), 
		.sctag2_cpx_atom_cq		(sctag2_cpx_atom_cq), 
		.sctag2_cpx_data_ca		(sctag2_cpx_data_ca[145:0]), 
		.sctag2_cpx_req_cq		(sctag2_cpx_req_cq[7:0]), 
		.sctag3_cpx_atom_cq		(sctag3_cpx_atom_cq), 
		.sctag3_cpx_data_ca		(sctag3_cpx_data_ca[145:0]), 
		.sctag3_cpx_req_cq		(sctag3_cpx_req_cq[7:0]), 
		.sctag4_cpx_atom_cq		(sctag4_cpx_atom_cq), 
		.sctag4_cpx_data_ca		(sctag4_cpx_data_ca[145:0]), 
		.sctag4_cpx_req_cq		(sctag4_cpx_req_cq[7:0]), 
		.sctag5_cpx_atom_cq		(sctag5_cpx_atom_cq), 
		.sctag5_cpx_data_ca		(sctag5_cpx_data_ca[145:0]), 
		.sctag5_cpx_req_cq		(sctag5_cpx_req_cq[7:0]), 
		.sctag6_cpx_atom_cq		(sctag6_cpx_atom_cq), 
		.sctag6_cpx_data_ca		(sctag6_cpx_data_ca[145:0]), 
		.sctag6_cpx_req_cq		(sctag6_cpx_req_cq[7:0]), 
		.sctag7_cpx_atom_cq		(sctag7_cpx_atom_cq), 
		.sctag7_cpx_data_ca		(sctag7_cpx_data_ca[145:0]), 
		.sctag7_cpx_req_cq		(sctag7_cpx_req_cq[7:0]), 
		.scan_in			(clkgen_scanout), 
		.scan_out			(scan_out_0), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk), 
		.tcu_scan_en			(tcu_scan_en_buf), 
		.tcu_pce_ov			(tcu_pce_ov_r));
	pcx pcx(
		.pcx_fpio_data_px2		(pcx_fpio_data_px2[129:0]), 
		.pcx_fpio_data_rdy_px1		(pcx_fpio_data_rdy_px1), 
		.pcx_sctag0_atm_px1		(pcx_sctag0_atm_px1), 
		.pcx_sctag0_data_px2		(pcx_sctag0_data_px2[129:0]), 
		.pcx_sctag0_data_rdy_px1	(pcx_sctag0_data_rdy_px1), 
		.pcx_sctag1_atm_px1		(pcx_sctag1_atm_px1), 
		.pcx_sctag1_data_px2		(pcx_sctag1_data_px2[129:0]), 
		.pcx_sctag1_data_rdy_px1	(pcx_sctag1_data_rdy_px1), 
		.pcx_sctag2_atm_px1		(pcx_sctag2_atm_px1), 
		.pcx_sctag2_data_px2		(pcx_sctag2_data_px2[129:0]), 
		.pcx_sctag2_data_rdy_px1	(pcx_sctag2_data_rdy_px1), 
		.pcx_sctag3_atm_px1		(pcx_sctag3_atm_px1), 
		.pcx_sctag3_data_px2		(pcx_sctag3_data_px2[129:0]), 
		.pcx_sctag3_data_rdy_px1	(pcx_sctag3_data_rdy_px1), 
		.pcx_sctag4_atm_px1		(pcx_sctag4_atm_px1), 
		.pcx_sctag4_data_px2		(pcx_sctag4_data_px2[129:0]), 
		.pcx_sctag4_data_rdy_px1	(pcx_sctag4_data_rdy_px1), 
		.pcx_sctag5_atm_px1		(pcx_sctag5_atm_px1), 
		.pcx_sctag5_data_px2		(pcx_sctag5_data_px2[129:0]), 
		.pcx_sctag5_data_rdy_px1	(pcx_sctag5_data_rdy_px1), 
		.pcx_sctag6_atm_px1		(pcx_sctag6_atm_px1), 
		.pcx_sctag6_data_px2		(pcx_sctag6_data_px2[129:0]), 
		.pcx_sctag6_data_rdy_px1	(pcx_sctag6_data_rdy_px1), 
		.pcx_sctag7_atm_px1		(pcx_sctag7_atm_px1), 
		.pcx_sctag7_data_px2		(pcx_sctag7_data_px2[129:0]), 
		.pcx_sctag7_data_rdy_px1	(pcx_sctag7_data_rdy_px1), 
		.pcx_spc0_grant_px		(pcx_spc0_grant_px[8:0]), 
		.pcx_spc1_grant_px		(pcx_spc1_grant_px[8:0]), 
		.pcx_spc2_grant_px		(pcx_spc2_grant_px[8:0]), 
		.pcx_spc3_grant_px		(pcx_spc3_grant_px[8:0]), 
		.pcx_spc4_grant_px		(pcx_spc4_grant_px[8:0]), 
		.pcx_spc5_grant_px		(pcx_spc5_grant_px[8:0]), 
		.pcx_spc6_grant_px		(pcx_spc6_grant_px[8:0]), 
		.pcx_spc7_grant_px		(pcx_spc7_grant_px[8:0]), 
		.io_pcx_stall_pq		(io_pcx_stall_pq), 
		.sctag0_pcx_stall_pq		(sctag0_pcx_stall_pq), 
		.sctag1_pcx_stall_pq		(sctag1_pcx_stall_pq), 
		.sctag2_pcx_stall_pq		(sctag2_pcx_stall_pq), 
		.sctag3_pcx_stall_pq		(sctag3_pcx_stall_pq), 
		.sctag4_pcx_stall_pq		(sctag4_pcx_stall_pq), 
		.sctag5_pcx_stall_pq		(sctag5_pcx_stall_pq), 
		.sctag6_pcx_stall_pq		(sctag6_pcx_stall_pq), 
		.sctag7_pcx_stall_pq		(sctag7_pcx_stall_pq), 
		.spc0_pcx_data_pa		(spc0_pcx_data_pa[129:0]), 
		.spc0_pcx_req_pq		(spc0_pcx_req_pq[8:0]), 
		.spc0_pcx_atm_pq		(spc0_pcx_atm_pq[8:0]), 
		.spc1_pcx_data_pa		(spc1_pcx_data_pa[129:0]), 
		.spc1_pcx_req_pq		(spc1_pcx_req_pq[8:0]), 
		.spc1_pcx_atm_pq		(spc1_pcx_atm_pq[8:0]), 
		.spc2_pcx_data_pa		(spc2_pcx_data_pa[129:0]), 
		.spc2_pcx_req_pq		(spc2_pcx_req_pq[8:0]), 
		.spc2_pcx_atm_pq		(spc2_pcx_atm_pq[8:0]), 
		.spc3_pcx_data_pa		(spc3_pcx_data_pa[129:0]), 
		.spc3_pcx_req_pq		(spc3_pcx_req_pq[8:0]), 
		.spc3_pcx_atm_pq		(spc3_pcx_atm_pq[8:0]), 
		.spc4_pcx_data_pa		(spc4_pcx_data_pa[129:0]), 
		.spc4_pcx_req_pq		(spc4_pcx_req_pq[8:0]), 
		.spc4_pcx_atm_pq		(spc4_pcx_atm_pq[8:0]), 
		.spc5_pcx_data_pa		(spc5_pcx_data_pa[129:0]), 
		.spc5_pcx_req_pq		(spc5_pcx_req_pq[8:0]), 
		.spc5_pcx_atm_pq		(spc5_pcx_atm_pq[8:0]), 
		.spc6_pcx_data_pa		(spc6_pcx_data_pa[129:0]), 
		.spc6_pcx_req_pq		(spc6_pcx_req_pq[8:0]), 
		.spc6_pcx_atm_pq		(spc6_pcx_atm_pq[8:0]), 
		.spc7_pcx_data_pa		(spc7_pcx_data_pa[129:0]), 
		.spc7_pcx_req_pq		(spc7_pcx_req_pq[8:0]), 
		.spc7_pcx_atm_pq		(spc7_pcx_atm_pq[8:0]), 
		.scan_in			(scan_in_buf[1]), 
		.scan_out			(pcx_scan_out), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk), 
		.tcu_scan_en			(tcu_scan_en_buf), 
		.tcu_pce_ov			(tcu_pce_ov_r));
	ccx_trep trep0(
		.cpu_rep_in			(cpu_rep0_in[191:0]), 
		.cpu_rep_out			(cpu_rep0_out[191:0]));
	ccx_trep trep1(
		.cpu_rep_in			(cpu_rep1_in[191:0]), 
		.cpu_rep_out			(cpu_rep1_out[191:0]));
	ccx_tstg tstgl(
		.din				(ccx_lstg_in[159:0]), 
		.dout				(ccx_lstg_out[159:0]), 
		.local_stop			(1'b0), 
		.scan_in			(pcx_scan_out), 
		.scan_out			(tstgl_scan_out), 
		.l2clk				(l2clk), 
		.tcu_aclk			(ccx_aclk), 
		.tcu_bclk			(ccx_bclk), 
		.tcu_scan_en			(tcu_scan_en_buf), 
		.tcu_pce_ov			(tcu_pce_ov_r));
	ccx_tstg tstgr(
		.din				(ccx_rstg_in[159:0]), 
		.dout				(ccx_rstg_out[159:0]), 
		.local_stop			(1'b0), 
		.scan_in			(tstgl_scan_out), 
		.scan_out			(scan_out_1), 
		.l2clk				(l2clk), 
		.tcu_aclk			(ccx_aclk), 
		.tcu_bclk			(ccx_bclk), 
		.tcu_scan_en			(tcu_scan_en_buf), 
		.tcu_pce_ov			(tcu_pce_ov_r));
	buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_buf_scan(
		.din				({scan_out_1, scan_out_0}), 
		.dout				({scan_out[1:0]}));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx_arb.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module ccx_arb (
  arb_grant_a, 
  arb_q0_holdbar_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_shift_a, 
  arb_src0_grant_a, 
  arb_src1_grant_a, 
  arb_src2_grant_a, 
  arb_src3_grant_a, 
  arb_src4_grant_a, 
  arb_src5_grant_a, 
  arb_src6_grant_a, 
  arb_src7_grant_a, 
  arb_src8_grant_a, 
  ccx_dest_atom_a, 
  ccx_dest_data_rdy_a, 
  src0_arb_atom_q, 
  src0_arb_req_q, 
  src1_arb_atom_q, 
  src1_arb_req_q, 
  src2_arb_atom_q, 
  src2_arb_req_q, 
  src3_arb_atom_q, 
  src3_arb_req_q, 
  src4_arb_atom_q, 
  src4_arb_req_q, 
  src5_arb_atom_q, 
  src5_arb_req_q, 
  src6_arb_atom_q, 
  src6_arb_req_q, 
  src7_arb_atom_q, 
  src7_arb_req_q, 
  src8_arb_atom_q, 
  src8_arb_req_q, 
  stall_q_d1, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire direction;
wire [17:0] write_fifo_a;
wire [2:0] fifo_rptr_a;
wire [1:0] fifo_read_select;
wire input_req_sel_a;
wire input_req_sel_a_;
wire fifo_req_sel_a;
wire [8:0] qfullbar_a;
wire [8:0] atom_x;
wire [8:0] grant_a;
wire req_pkt_empty_a;
wire arc_scanin;
wire arc_scanout;
wire tcu_pce_ov_out;
wire tcu_scan_en_out;
wire ccx_aclk_out;
wire ccx_bclk_out;
wire ard_scanin;
wire ard_scanout;
wire [8:0] atom_a;
wire [8:0] req_a;


// Beginning of automatic outputs (from unused autoinst outputs)
output [8:0]            arb_grant_a;            // From i_arbdp of ccx_ard_dp.v
output [8:0]            arb_q0_holdbar_a;          // From i_arbctl of ccx_arc_ctl.v
output [8:0]            arb_qsel0_a;            // From i_arbctl of ccx_arc_ctl.v
output [8:0]            arb_qsel1_a;            // From i_arbctl of ccx_arc_ctl.v
output [8:0]            arb_shift_a;            // From i_arbctl of ccx_arc_ctl.v
output                  arb_src0_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  arb_src1_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  arb_src2_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  arb_src3_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  arb_src4_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  arb_src5_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  arb_src6_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  arb_src7_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  arb_src8_grant_a;       // From i_arbdp of ccx_ard_dp.v
output                  ccx_dest_atom_a;        // From i_arbctl of ccx_arc_ctl.v
output                  ccx_dest_data_rdy_a;    // From i_arbctl of ccx_arc_ctl.v

// End of automatics


// Beginning of automatic inputs (from unused autoinst inputs)

input                   src0_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src0_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   src1_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src1_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   src2_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src2_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   src3_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src3_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   src4_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src4_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   src5_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src5_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   src6_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src6_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   src7_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src7_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   src8_arb_atom_q;        // To i_arbctl of ccx_arc_ctl.v, ...
input                   src8_arb_req_q;         // To i_arbctl of ccx_arc_ctl.v, ...
input                   stall_q_d1;                // To i_arbctl of ccx_arc_ctl.v
// End of automatics

//globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

ccx_arc_ctl arc (
   /*AUTOINST*/
                 // Outputs
                 .direction             (direction),
                 .write_fifo_a          (write_fifo_a[17:0]),
                 .fifo_rptr_a           (fifo_rptr_a[2:0]),
                 .fifo_read_select      (fifo_read_select[1:0]),
                 .input_req_sel_a       (input_req_sel_a),
                 .input_req_sel_a_      (input_req_sel_a_),
                 .fifo_req_sel_a        (fifo_req_sel_a),
                 .qfullbar_a            (qfullbar_a[8:0]),
                 .atom_x                (atom_x[8:0]),
                 .arb_qsel0_a           (arb_qsel0_a[8:0]),
                 .arb_qsel1_a           (arb_qsel1_a[8:0]),
                 .arb_shift_a           (arb_shift_a[8:0]),
                 .arb_q0_holdbar_a      (arb_q0_holdbar_a[8:0]),
                 // Inputs
                 .grant_a               (grant_a[8:0]),
                 .req_pkt_empty_a       (req_pkt_empty_a),
                 .scan_in(arc_scanin),
                 .scan_out(arc_scanout),
                 .l2clk                 (l2clk),
                 .tcu_pce_ov            (tcu_pce_ov_out),
                 .tcu_scan_en           (tcu_scan_en_out),
                 .ccx_aclk           (ccx_aclk_out),
                 .ccx_bclk            (ccx_bclk_out),
  .atom_a(atom_a[8:0]),
  .req_a(req_a[8:0])
);

ccx_ard_dp ard (
   /*AUTOINST*/
                // Outputs
                .arb_grant_a            (arb_grant_a[8:0]),
                .arb_src8_grant_a       (arb_src8_grant_a),
                .arb_src7_grant_a       (arb_src7_grant_a),
                .arb_src6_grant_a       (arb_src6_grant_a),
                .arb_src5_grant_a       (arb_src5_grant_a),
                .arb_src4_grant_a       (arb_src4_grant_a),
                .arb_src3_grant_a       (arb_src3_grant_a),
                .arb_src2_grant_a       (arb_src2_grant_a),
                .arb_src1_grant_a       (arb_src1_grant_a),
                .arb_src0_grant_a       (arb_src0_grant_a),
                .ccx_dest_data_rdy_a   (ccx_dest_data_rdy_a),
                .ccx_dest_atom_a        (ccx_dest_atom_a),
                .req_pkt_empty_a        (req_pkt_empty_a),
                .grant_a                (grant_a[8:0]),
                // Inputs
                .src8_arb_atom_q        (src8_arb_atom_q),
                .src7_arb_atom_q        (src7_arb_atom_q),
                .src6_arb_atom_q        (src6_arb_atom_q),
                .src5_arb_atom_q        (src5_arb_atom_q),
                .src4_arb_atom_q        (src4_arb_atom_q),
                .src3_arb_atom_q        (src3_arb_atom_q),
                .src2_arb_atom_q        (src2_arb_atom_q),
                .src1_arb_atom_q        (src1_arb_atom_q),
                .src0_arb_atom_q        (src0_arb_atom_q),
                .src8_arb_req_q         (src8_arb_req_q),
                .src7_arb_req_q         (src7_arb_req_q),
                .src6_arb_req_q         (src6_arb_req_q),
                .src5_arb_req_q         (src5_arb_req_q),
                .src4_arb_req_q         (src4_arb_req_q),
                .src3_arb_req_q         (src3_arb_req_q),
                .src2_arb_req_q         (src2_arb_req_q),
                .src1_arb_req_q         (src1_arb_req_q),
                .src0_arb_req_q         (src0_arb_req_q),
                .qfullbar_a             (qfullbar_a[8:0]),
                .direction              (direction),
                .fifo_req_sel_a         (fifo_req_sel_a),
                .input_req_sel_a        (input_req_sel_a),
                .input_req_sel_a_       (input_req_sel_a_),
                .write_fifo_a           (write_fifo_a[17:0]),
                .fifo_rptr_a            (fifo_rptr_a[2:0]),
                .fifo_read_select       (fifo_read_select[1:0]),
                .atom_x                 (atom_x[8:0]),
                .stall_q_d1                (stall_q_d1),
                .scan_in(ard_scanin),
                .scan_out(ard_scanout),
                .l2clk                  (l2clk),
                .tcu_pce_ov             (tcu_pce_ov),
  .req_a(req_a[8:0]),
  .atom_a(atom_a[8:0]),
  .tcu_scan_en(tcu_scan_en),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk),
  .tcu_pce_ov_out(tcu_pce_ov_out),
  .tcu_scan_en_out(tcu_scan_en_out),
  .ccx_aclk_out(ccx_aclk_out),
  .ccx_bclk_out(ccx_bclk_out));

			 
// fixscan start:
assign arc_scanin                = scan_in                  ;
assign ard_scanin                = arc_scanout              ;
assign scan_out                  = ard_scanout              ;
// fixscan end:
endmodule
   
// Local Variables:
// verilog-library-directories:("." "./v")
// End:


// any PARAMS parms go into naming of macro

module ccx_arb_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_arb_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_arb_msff_ctl_macro (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ccx_arb_spare_ctl_macro__num_10 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire si_8;
wire so_8;
wire spare8_flop_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;
wire si_9;
wire so_9;
wire spare9_flop_unused;
wire spare9_buf_32x_unused;
wire spare9_nand3_8x_unused;
wire spare9_inv_8x_unused;
wire spare9_aoi22_4x_unused;
wire spare9_buf_8x_unused;
wire spare9_oai22_4x_unused;
wire spare9_inv_16x_unused;
wire spare9_nand2_16x_unused;
wire spare9_nor3_4x_unused;
wire spare9_nand2_8x_unused;
wire spare9_buf_16x_unused;
wire spare9_nor2_16x_unused;
wire spare9_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));

cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_8),
                               .so(so_8),
                               .d(1'b0),
                               .q(spare8_flop_unused));
assign si_8 = so_7;

cl_u1_buf_32x   spare8_buf_32x (.in(1'b1),
                                   .out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare8_nand3_8x_unused));
cl_u1_inv_8x    spare8_inv_8x (.in(1'b1),
                                  .out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_aoi22_4x_unused));
cl_u1_buf_8x    spare8_buf_8x (.in(1'b1),
                                  .out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_oai22_4x_unused));
cl_u1_inv_16x   spare8_inv_16x (.in(1'b1),
                                   .out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare8_nand2_8x_unused));
cl_u1_buf_16x   spare8_buf_16x (.in(1'b1),
                                   .out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare8_nor2_16x_unused));
cl_u1_inv_32x   spare8_inv_32x (.in(1'b1),
                                   .out(spare8_inv_32x_unused));

cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_9),
                               .so(so_9),
                               .d(1'b0),
                               .q(spare9_flop_unused));
assign si_9 = so_8;

cl_u1_buf_32x   spare9_buf_32x (.in(1'b1),
                                   .out(spare9_buf_32x_unused));
cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare9_nand3_8x_unused));
cl_u1_inv_8x    spare9_inv_8x (.in(1'b1),
                                  .out(spare9_inv_8x_unused));
cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_aoi22_4x_unused));
cl_u1_buf_8x    spare9_buf_8x (.in(1'b1),
                                  .out(spare9_buf_8x_unused));
cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_oai22_4x_unused));
cl_u1_inv_16x   spare9_inv_16x (.in(1'b1),
                                   .out(spare9_inv_16x_unused));
cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare9_nand2_16x_unused));
cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare9_nor3_4x_unused));
cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare9_nand2_8x_unused));
cl_u1_buf_16x   spare9_buf_16x (.in(1'b1),
                                   .out(spare9_buf_16x_unused));
cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare9_nor2_16x_unused));
cl_u1_inv_32x   spare9_inv_32x (.in(1'b1),
                                   .out(spare9_inv_32x_unused));
assign scan_out = so_9;


endmodule


//
//   buff macro
//
//


module ccx_arb_buff_macro__dbuff_16x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_arb_msff_macro__dmsff_16x__stack_10c__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_1x__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   invert macro
//
//


module ccx_arb_inv_macro__dinv_24x__stack_10c__width_10 (
  din, 
  dout);
  input [9:0] din;
  output [9:0] dout;


inv #(10)  d0_0 (
.in(din[9:0]),
.out(dout[9:0])
);


endmodule


//
//   buff macro
//
//


module ccx_arb_buff_macro__dbuff_32x__minbuff_1__stack_none__width_19 (
  din, 
  dout);
  input [18:0] din;
  output [18:0] dout;


buff #(19)  d0_0 (
.in(din[18:0]),
.out(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_arb_msff_macro__stack_10c__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_arb_mux_macro__dbuff_8x__dmux_4x__mux_aope__ports_2__stack_10c__width_10 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [9:0] din0;
  input [9:0] din1;
  input sel0;
  output [9:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(10)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
.dout(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_arb_mux_macro__dbuff_8x__dmux_4x__mux_aodec__ports_8__stack_10c__width_10 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [9:0] din0;
  input [9:0] din1;
  input [9:0] din2;
  input [9:0] din3;
  input [9:0] din4;
  input [9:0] din5;
  input [9:0] din6;
  input [9:0] din7;
  input [2:0] sel;
  output [9:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(10)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
  .in2(din2[9:0]),
  .in3(din3[9:0]),
  .in4(din4[9:0]),
  .in5(din5[9:0]),
  .in6(din6[9:0]),
  .in7(din7[9:0]),
.dout(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_arb_mux_macro__dmux_1x__mux_aodec__ports_4__stack_10c__width_10 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [9:0] din0;
  input [9:0] din1;
  input [9:0] din2;
  input [9:0] din3;
  input [1:0] sel;
  output [9:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(10)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
  .in2(din2[9:0]),
  .in3(din3[9:0]),
.dout(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_arb_mux_macro__dmux_1x__mux_aonpe__ports_2__stack_10c__width_10 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [9:0] din0;
  input sel0;
  input [9:0] din1;
  input sel1;
  output [9:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(10)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
.dout(dout[9:0])
);


endmodule


//
//   buff macro
//
//


module ccx_arb_buff_macro__dbuff_8x__stack_10c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_4x__ports_3__stack_10c__width_10 (
  din0, 
  din1, 
  din2, 
  dout);
  input [9:0] din0;
  input [9:0] din1;
  input [9:0] din2;
  output [9:0] dout;


nand3 #(10)  d0_0 (
.in0(din0[9:0]),
.in1(din1[9:0]),
.in2(din2[9:0]),
.out(dout[9:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_4x__ports_2__stack_10c__width_10 (
  din0, 
  din1, 
  dout);
  input [9:0] din0;
  input [9:0] din1;
  output [9:0] dout;


nand2 #(10)  d0_0 (
.in0(din0[9:0]),
.in1(din1[9:0]),
.out(dout[9:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_12x__ports_2__stack_10c__width_10 (
  din0, 
  din1, 
  dout);
  input [9:0] din0;
  input [9:0] din1;
  output [9:0] dout;


nand2 #(10)  d0_0 (
.in0(din0[9:0]),
.in1(din1[9:0]),
.out(dout[9:0])
);


endmodule


//
//   invert macro
//
//


module ccx_arb_inv_macro__dinv_2x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


inv #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_arb_mux_macro__dmux_8x__mux_aope__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [8:0] din0;
  input [8:0] din1;
  input sel0;
  output [8:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(9)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[8:0]),
  .in1(din1[8:0]),
.dout(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_4x__ports_3__stack_10c__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nand3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_12x__ports_2__stack_10c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module ccx_arb_inv_macro__dinv_4x__stack_10c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module ccx_arb_inv_macro__dinv_12x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


inv #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ccx_arb_and_macro__dinv_12x__dnand_4x__ports_4__stack_10c__width_2 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  input [1:0] din2;
  input [1:0] din3;
  output [1:0] dout;


and4 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.in2(din2[1:0]),
.in3(din3[1:0]),
.out(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ccx_arb_and_macro__dinv_8x__dnand_2x__ports_3__stack_10c__width_4 (
  din0, 
  din1, 
  din2, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  input [3:0] din2;
  output [3:0] dout;


and3 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.in2(din2[3:0]),
.out(dout[3:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module ccx_arb_nor_macro__dnor_8x__ports_2__stack_10c__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


nor2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_2x__ports_2__stack_10c__width_5 (
  din0, 
  din1, 
  dout);
  input [4:0] din0;
  input [4:0] din1;
  output [4:0] dout;


nand2 #(5)  d0_0 (
.in0(din0[4:0]),
.in1(din1[4:0]),
.out(dout[4:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_8x__ports_2__stack_10c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module ccx_arb_inv_macro__dinv_4x__stack_10c__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


inv #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_8x__ports_3__stack_10c__width_8 (
  din0, 
  din1, 
  din2, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  output [7:0] dout;


nand3 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.in2(din2[7:0]),
.out(dout[7:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_32x__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module ccx_arb_buff_macro__dbuff_48x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module ccx_arb_buff_macro__dbuff_32x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module ccx_arb_buff_macro__dbuff_16x__minbuff_1__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   invert macro
//
//


module ccx_arb_inv_macro__dinv_8x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


inv #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_1x__ports_3__stack_10c__width_9 (
  din0, 
  din1, 
  din2, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  input [8:0] din2;
  output [8:0] dout;


nand3 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.in2(din2[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_1x__ports_2__stack_10c__width_10 (
  din0, 
  din1, 
  dout);
  input [9:0] din0;
  input [9:0] din1;
  output [9:0] dout;


nand2 #(10)  d0_0 (
.in0(din0[9:0]),
.in1(din1[9:0]),
.out(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_arb_msff_macro__dmsff_8x__stack_10c__stack_10c__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_2x__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_4x__ports_3__stack_10c__width_9 (
  din0, 
  din1, 
  din2, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  input [8:0] din2;
  output [8:0] dout;


nand3 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.in2(din2[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_8x__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module ccx_arb_nor_macro__dnor_4x__ports_3__stack_10c__width_6 (
  din0, 
  din1, 
  din2, 
  dout);
  input [5:0] din0;
  input [5:0] din1;
  input [5:0] din2;
  output [5:0] dout;


nor3 #(6)  d0_0 (
.in0(din0[5:0]),
.in1(din1[5:0]),
.in2(din2[5:0]),
.out(dout[5:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_8x__ports_3__stack_10c__width_2 (
  din0, 
  din1, 
  din2, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  input [1:0] din2;
  output [1:0] dout;


nand3 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.in2(din2[1:0]),
.out(dout[1:0])
);


endmodule


//
//   invert macro
//
//


module ccx_arb_inv_macro__dinv_32x__stack_10c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module ccx_arb_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_arb_nand_macro__dnand_1x__ports_3__stack_10c__width_3 (
  din0, 
  din1, 
  din2, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  output [2:0] dout;


nand3 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.in2(din2[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module ccx_arb_nor_macro__dnor_4x__ports_3__stack_10c__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nor3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module ccx_arb_buff_macro__dbuff_8x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA

/* Source file "ccx_arb_vj.v", line 2 */
// No timescale specified
module ccx_arb(arb_grant_a, arb_q0_holdbar_a, arb_qsel0_a, arb_qsel1_a, 
	arb_shift_a, arb_src0_grant_a, arb_src1_grant_a, arb_src2_grant_a, 
	arb_src3_grant_a, arb_src4_grant_a, arb_src5_grant_a, arb_src6_grant_a, 
	arb_src7_grant_a, arb_src8_grant_a, ccx_dest_atom_a, 
	ccx_dest_data_rdy_a, src0_arb_atom_q, src0_arb_req_q, src1_arb_atom_q, 
	src1_arb_req_q, src2_arb_atom_q, src2_arb_req_q, src3_arb_atom_q, 
	src3_arb_req_q, src4_arb_atom_q, src4_arb_req_q, src5_arb_atom_q, 
	src5_arb_req_q, src6_arb_atom_q, src6_arb_req_q, src7_arb_atom_q, 
	src7_arb_req_q, src8_arb_atom_q, src8_arb_req_q, stall_q_d1, 
	tcu_scan_en, l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[8:0]		arb_grant_a;
	output	[8:0]		arb_q0_holdbar_a;
	output	[8:0]		arb_qsel0_a;
	output	[8:0]		arb_qsel1_a;
	output	[8:0]		arb_shift_a;
	output			arb_src0_grant_a;
	output			arb_src1_grant_a;
	output			arb_src2_grant_a;
	output			arb_src3_grant_a;
	output			arb_src4_grant_a;
	output			arb_src5_grant_a;
	output			arb_src6_grant_a;
	output			arb_src7_grant_a;
	output			arb_src8_grant_a;
	output			ccx_dest_atom_a;
	output			ccx_dest_data_rdy_a;
	input			src0_arb_atom_q;
	input			src0_arb_req_q;
	input			src1_arb_atom_q;
	input			src1_arb_req_q;
	input			src2_arb_atom_q;
	input			src2_arb_req_q;
	input			src3_arb_atom_q;
	input			src3_arb_req_q;
	input			src4_arb_atom_q;
	input			src4_arb_req_q;
	input			src5_arb_atom_q;
	input			src5_arb_req_q;
	input			src6_arb_atom_q;
	input			src6_arb_req_q;
	input			src7_arb_atom_q;
	input			src7_arb_req_q;
	input			src8_arb_atom_q;
	input			src8_arb_req_q;
	input			stall_q_d1;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire			direction;
	wire	[17:0]		write_fifo_a;
	wire	[2:0]		fifo_rptr_a;
	wire	[1:0]		fifo_read_select;
	wire			input_req_sel_a;
	wire			input_req_sel_a_;
	wire			fifo_req_sel_a;
	wire	[8:0]		qfullbar_a;
	wire	[8:0]		atom_x;
	wire	[8:0]		grant_a;
	wire			req_pkt_empty_a;
	wire			arc_scanin;
	wire			arc_scanout;
	wire			tcu_pce_ov_out;
	wire			tcu_scan_en_out;
	wire			ccx_aclk_out;
	wire			ccx_bclk_out;
	wire			ard_scanin;
	wire			ard_scanout;
	wire	[8:0]		atom_a;
	wire	[8:0]		req_a;

	assign arc_scanin = scan_in;
	assign ard_scanin = arc_scanout;
	assign scan_out = ard_scanout;

	ccx_arc_ctl arc(
		.direction			(direction), 
		.write_fifo_a			(write_fifo_a[17:0]), 
		.fifo_rptr_a			(fifo_rptr_a[2:0]), 
		.fifo_read_select		(fifo_read_select[1:0]), 
		.input_req_sel_a		(input_req_sel_a), 
		.input_req_sel_a_		(input_req_sel_a_), 
		.fifo_req_sel_a			(fifo_req_sel_a), 
		.qfullbar_a			(qfullbar_a[8:0]), 
		.atom_x				(atom_x[8:0]), 
		.arb_qsel0_a			(arb_qsel0_a[8:0]), 
		.arb_qsel1_a			(arb_qsel1_a[8:0]), 
		.arb_shift_a			(arb_shift_a[8:0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_a[8:0]), 
		.grant_a			(grant_a[8:0]), 
		.req_pkt_empty_a		(req_pkt_empty_a), 
		.scan_in			(arc_scanin), 
		.scan_out			(arc_scanout), 
		.l2clk				(l2clk), 
		.tcu_pce_ov			(tcu_pce_ov_out), 
		.tcu_scan_en			(tcu_scan_en_out), 
		.ccx_aclk			(ccx_aclk_out), 
		.ccx_bclk			(ccx_bclk_out), 
		.atom_a				(atom_a[8:0]), 
		.req_a				(req_a[8:0]));
	ccx_ard_dp ard(
		.arb_grant_a			(arb_grant_a[8:0]), 
		.arb_src8_grant_a		(arb_src8_grant_a), 
		.arb_src7_grant_a		(arb_src7_grant_a), 
		.arb_src6_grant_a		(arb_src6_grant_a), 
		.arb_src5_grant_a		(arb_src5_grant_a), 
		.arb_src4_grant_a		(arb_src4_grant_a), 
		.arb_src3_grant_a		(arb_src3_grant_a), 
		.arb_src2_grant_a		(arb_src2_grant_a), 
		.arb_src1_grant_a		(arb_src1_grant_a), 
		.arb_src0_grant_a		(arb_src0_grant_a), 
		.ccx_dest_data_rdy_a		(ccx_dest_data_rdy_a), 
		.ccx_dest_atom_a		(ccx_dest_atom_a), 
		.req_pkt_empty_a		(req_pkt_empty_a), 
		.grant_a			(grant_a[8:0]), 
		.src8_arb_atom_q		(src8_arb_atom_q), 
		.src7_arb_atom_q		(src7_arb_atom_q), 
		.src6_arb_atom_q		(src6_arb_atom_q), 
		.src5_arb_atom_q		(src5_arb_atom_q), 
		.src4_arb_atom_q		(src4_arb_atom_q), 
		.src3_arb_atom_q		(src3_arb_atom_q), 
		.src2_arb_atom_q		(src2_arb_atom_q), 
		.src1_arb_atom_q		(src1_arb_atom_q), 
		.src0_arb_atom_q		(src0_arb_atom_q), 
		.src8_arb_req_q			(src8_arb_req_q), 
		.src7_arb_req_q			(src7_arb_req_q), 
		.src6_arb_req_q			(src6_arb_req_q), 
		.src5_arb_req_q			(src5_arb_req_q), 
		.src4_arb_req_q			(src4_arb_req_q), 
		.src3_arb_req_q			(src3_arb_req_q), 
		.src2_arb_req_q			(src2_arb_req_q), 
		.src1_arb_req_q			(src1_arb_req_q), 
		.src0_arb_req_q			(src0_arb_req_q), 
		.qfullbar_a			(qfullbar_a[8:0]), 
		.direction			(direction), 
		.fifo_req_sel_a			(fifo_req_sel_a), 
		.input_req_sel_a		(input_req_sel_a), 
		.input_req_sel_a_		(input_req_sel_a_), 
		.write_fifo_a			(write_fifo_a[17:0]), 
		.fifo_rptr_a			(fifo_rptr_a[2:0]), 
		.fifo_read_select		(fifo_read_select[1:0]), 
		.atom_x				(atom_x[8:0]), 
		.stall_q_d1			(stall_q_d1), 
		.scan_in			(ard_scanin), 
		.scan_out			(ard_scanout), 
		.l2clk				(l2clk), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.req_a				(req_a[8:0]), 
		.atom_a				(atom_a[8:0]), 
		.tcu_scan_en			(tcu_scan_en), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk), 
		.tcu_pce_ov_out			(tcu_pce_ov_out), 
		.tcu_scan_en_out		(tcu_scan_en_out), 
		.ccx_aclk_out			(ccx_aclk_out), 
		.ccx_bclk_out			(ccx_bclk_out));
endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx_arc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module ccx_arc_ctl (
  grant_a, 
  req_pkt_empty_a, 
  direction, 
  write_fifo_a, 
  fifo_rptr_a, 
  fifo_read_select, 
  input_req_sel_a, 
  input_req_sel_a_, 
  fifo_req_sel_a, 
  qfullbar_a, 
  atom_x, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_shift_a, 
  arb_q0_holdbar_a, 
  atom_a, 
  req_a, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire [8:0] input_req_a;
wire [8:0] qfull_a;
wire inreg_req_vld_a;
wire wr_en_a;
wire fifo_empty_a;
wire wptr_eq17;
wire [4:0] wptr_a;
wire [4:0] wptr_next;
wire dff_wptr_scanin;
wire dff_wptr_scanout;
wire rd_en_a;
wire rptr_eq17;
wire [4:0] rptr_a;
wire [4:0] rptr_next;
wire dff_rptr_scanin;
wire dff_rptr_scanout;
wire fifo_bypass_a;
wire [17:0] wptr_dcd_a;
wire input_req_sel_q;
wire input_req_sel_q_;
wire dff_inreg_select_scanin;
wire dff_inreg_select_scanout;
wire dff_inreg_select__scanin;
wire dff_inreg_select__scanout;
wire direction_in;
wire dff_dir_scanin;
wire dff_dir_scanout;
wire q0_scanin;
wire q0_scanout;
wire q1_scanin;
wire q1_scanout;
wire q2_scanin;
wire q2_scanout;
wire q3_scanin;
wire q3_scanout;
wire q4_scanin;
wire q4_scanout;
wire q5_scanin;
wire q5_scanout;
wire q6_scanin;
wire q6_scanout;
wire q7_scanin;
wire q7_scanout;
wire q8_scanin;
wire q8_scanout;
wire spares_scanin;
wire spares_scanout;


// input from arbdp
input [8:0]   grant_a;             // one-hot grant bit for each source
input         req_pkt_empty_a;     // request register is empty

// Interface with arbdp
output        direction;	       // PE direction controls
output [17:0] write_fifo_a;        // write pointer
output [2:0]  fifo_rptr_a;         // read pointer
output [1:0]  fifo_read_select;    // read select
output        input_req_sel_a;     // select for input mux
output        input_req_sel_a_;     // select for input mux
output        fifo_req_sel_a;      // select for request  mux
//output        current_req_sel_a;   // select for request mux
output [8:0]  qfullbar_a;          // src queue full indicator
output [8:0]  atom_x;              // atomic request indicator from srq


//Outputs to datapaths
output [8:0]  arb_qsel0_a;         // queue0 select
output [8:0]  arb_qsel1_a;         // queue1 select
output [8:0]  arb_shift_a;         // queue shift
output [8:0]  arb_q0_holdbar_a;        // q0 hold


//Inputs from sources
input [8:0]   atom_a;
input [8:0]   req_a;

//Globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = ccx_aclk;
assign soclk = ccx_bclk;
assign se = tcu_scan_en ;
// end scan

//////////////////////////////
// Clock header
//////////////////////////////
ccx_arc_ctl_l1clkhdr_ctl_macro clkgen 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );
//////////////////////////////////////////////////////////////////////
// DATAPATH STRUCTURE
//
//                                               req_q
//                                                 |
//                                                 |
//                                           -------------    
//                                          |  input reg  |   
//                                           -------------    
//                                                 |           
//     --------------------------------------------|---------           
//     |                                           |         |
//     |        ------------                       |         |
//     |        |          |                       v         |   
//     v        v          |                 -------------   |
//  ----------------       |                |    FIFO     |  |
//  \  input mux   /       |                |             |  |
//   --------------        |                |             |  |
//         |               |                |             |  |
//     ----------          |                 -------------   |
//     |        |          |                       |         |
//     v        v          |                       v         v
//  -------  -------       |                    ----------------    
// |  ASC  || DESC  |      |                    \  bypass mux  /<--------fifo_bypass             
// |  P E  || P E   |      |                     --------------     
// |       ||       |      |                            |                             
// |       ||       |      |      --------------        |
//  -------  -------       |     |              |       |                                    
//     |        |          |     |              v       v                                
//     v        v          |     |           ----------------                              
//  ----------------       |     |           \ request mux  / <--------current_req_sel     
//  \  dir mux     /       |     |            \            /  <--------fifo_req_sel        
//   --------------        |     |             ------------   
//         |               |     |                  |                                      
//         |-----grant-----|-----                   v                                      
//         |     qual      |                   -------------                               
//         |               |                  | request reg |                              
//         |               |                   -------------                                
//         |               |                       |                                       
//         v               |                       |                                       
//       grant             |                       v                                       
//                          -----------------------                                        
//
//////////////////////////////////////////////////////////////////////
// PIPELINE
// Consider case where REQ A has 3 requests, followed by REQ B which has 1
// request and REQ C.
//
//
// input reg     |REQ A|REQ B|     |REQ C|     |REQ D|REQ E|     |     |
//               |     |     |     |     |     |     |     |     |     |
//               |     |     |     |     |     |     |     |     |     |
//--------------------------------------------------------------------------
// input mux     |IN   |REQ  |REQ  |REQ  |REQ  |IN   |REQ  |REQ  |     |
//               |     |     |     |     |     |     |     |     |     |
//               |     |     |     |     |     |     |     |     |     |
//--------------------------------------------------------------------------
// FIFO          |     |     |REQ B|     |     |     |     |REQ E|     |
//               |     |     |     |     |     |     |     |     |     |
//               |     |     |     |     |     |     |     |     |     |
//--------------------------------------------------------------------------
// request mux   |REQ  |REQ  |FIFO |BYP  |     |REQ   |REQ |FIFO |     |
//               |     |     |     |     |     |     |     |     |     |
//               |     |     |     |     |     |     |     |     |     |
//--------------------------------------------------------------------------
// request reg   |     |REQ A|REQ A|REQ B|REQ C|     |REQ D|REQ D|REQ E|
//               |     |     |     |     |     |     |     |     |     |
//               |     |     |     |     |     |     |     |     |     |
//--------------------------------------------------------------------------
// grant         | A   | A   | A   | B   |C    | D   | D   | D   | E   |
//               |     |     |     |     |     |     |     |     |     |
//               |     |     |     |     |     |     |     |     |     |
//--------------------------------------------------------------------------
//


// Do not accept a request for a queue that is full.
assign input_req_a[8:0] = req_a[8:0] & ~qfull_a[8:0];
// see if any valid requests in flopped input request packet.
assign inreg_req_vld_a = |(input_req_a[8:0]);

// 

assign wr_en_a = ~input_req_sel_a & inreg_req_vld_a & 
                 (~req_pkt_empty_a | ~fifo_empty_a);


// 18 entry fifo must wrap to zero when counter equals 17.
assign wptr_eq17 = (wptr_a[4:0] == 5'b10001);
assign wptr_next[4:0] = (wr_en_a ? (wptr_eq17 ? 5'b00000 : wptr_a[4:0] + 5'b00001) : wptr_a[4:0]);


ccx_arc_ctl_msff_ctl_macro__width_5 dff_wptr  
(
 .scan_in(dff_wptr_scanin),
 .scan_out(dff_wptr_scanout),
 .din		(wptr_next[4:0]),
 .dout		(wptr_a[4:0]),
 .l1clk		(l1clk),
  .siclk(siclk),
  .soclk(soclk)
 );

//assign rd_en_a = req_pkt_empty_a & ~fifo_empty_a & ~input_req_sel_a;
assign rd_en_a = req_pkt_empty_a & ~fifo_empty_a;

// 18 entry fifo must wrap to zero when counter equals 17.
assign rptr_eq17 = (rptr_a[4:0] == 5'b10001);
assign rptr_next[4:0] = (rd_en_a ? (rptr_eq17 ? 5'b00000 : rptr_a[4:0] + 5'b00001) : rptr_a[4:0]);

ccx_arc_ctl_msff_ctl_macro__width_5 dff_rptr  
(
 .scan_in(dff_rptr_scanin),
 .scan_out(dff_rptr_scanout),
 .din		(rptr_next[4:0]),
 .dout		(rptr_a[4:0]),
 .l1clk		(l1clk),
  .siclk(siclk),
  .soclk(soclk)
 );

// Bits 2:0 of rdptr are used for the first level decode of the FIFO muxes
// The final FIFO mux is a four input mux with the following select
// assignments.
// sel[1:0] - input
//    00    - muxed result of entries 7:0
//    01    - muxed result of entries 15:8
//    10    - muxed result of entries 17:16
//    11    - bypass data
assign fifo_rptr_a[2:0] = rptr_a[2:0];
assign fifo_read_select[1:0] = rptr_a[4:3] | {2{fifo_bypass_a}};

assign fifo_empty_a = (rptr_a[4:0] == wptr_a[4:0]);


// Bypass valid input requests around the FIFO when it's empty.
// FIFO gets bypassed under following condition:
// 1. Request register was selected by input mux,
// 2. FIFO is empty
// 3. Input register is valid
// 4. Request packet goes empty.
// Following equation does not fully qualify the bypass condition.
// 
assign fifo_bypass_a = fifo_empty_a & inreg_req_vld_a;

// decode write pointer 
assign wptr_dcd_a[0]  =  (~wptr_a[4] & ~wptr_a[3] & ~wptr_a[2] & ~wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[1]  =  (~wptr_a[4] & ~wptr_a[3] & ~wptr_a[2] & ~wptr_a[1] &  wptr_a[0]);
assign wptr_dcd_a[2]  =  (~wptr_a[4] & ~wptr_a[3] & ~wptr_a[2] &  wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[3]  =  (~wptr_a[4] & ~wptr_a[3] & ~wptr_a[2] &  wptr_a[1] &  wptr_a[0]);
assign wptr_dcd_a[4]  =  (~wptr_a[4] & ~wptr_a[3] &  wptr_a[2] & ~wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[5]  =  (~wptr_a[4] & ~wptr_a[3] &  wptr_a[2] & ~wptr_a[1] &  wptr_a[0]);
assign wptr_dcd_a[6]  =  (~wptr_a[4] & ~wptr_a[3] &  wptr_a[2] &  wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[7]  =  (~wptr_a[4] & ~wptr_a[3] &  wptr_a[2] &  wptr_a[1] &  wptr_a[0]);
assign wptr_dcd_a[8]  =  (~wptr_a[4] &  wptr_a[3] & ~wptr_a[2] & ~wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[9]  =  (~wptr_a[4] &  wptr_a[3] & ~wptr_a[2] & ~wptr_a[1] &  wptr_a[0]);
assign wptr_dcd_a[10] =  (~wptr_a[4] &  wptr_a[3] & ~wptr_a[2] &  wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[11] =  (~wptr_a[4] &  wptr_a[3] & ~wptr_a[2] &  wptr_a[1] &  wptr_a[0]);
assign wptr_dcd_a[12] =  (~wptr_a[4] &  wptr_a[3] &  wptr_a[2] & ~wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[13] =  (~wptr_a[4] &  wptr_a[3] &  wptr_a[2] & ~wptr_a[1] &  wptr_a[0]);
assign wptr_dcd_a[14] =  (~wptr_a[4] &  wptr_a[3] &  wptr_a[2] &  wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[15] =  (~wptr_a[4] &  wptr_a[3] &  wptr_a[2] &  wptr_a[1] &  wptr_a[0]);
assign wptr_dcd_a[16] =  ( wptr_a[4] & ~wptr_a[3] & ~wptr_a[2] & ~wptr_a[1] & ~wptr_a[0]);
assign wptr_dcd_a[17] =  ( wptr_a[4] & ~wptr_a[3] & ~wptr_a[2] & ~wptr_a[1] &  wptr_a[0]);

// Qualify with the wr_en_a signal.  This isn't functionally necessary, but
// it does keep the clocks from toggling unless the FIFO needs to be written.
//assign write_fifo_a[17:0] = wptr_dcd_a[17:0] & {18{wr_en_a}};
// write enable timing is very tight.
assign write_fifo_a[17:0] = wptr_dcd_a[17:0];


// END FIFO LOGIC

// MUX CONTROLS


assign input_req_sel_q = (req_pkt_empty_a & fifo_empty_a & ~inreg_req_vld_a) | 
                         (req_pkt_empty_a & input_req_sel_a);


assign fifo_req_sel_a = req_pkt_empty_a & (~fifo_empty_a | (inreg_req_vld_a & ~input_req_sel_a));

assign input_req_sel_q_ = ~input_req_sel_q;

ccx_arc_ctl_msff_ctl_macro dff_inreg_select 
  (
   .scan_in(dff_inreg_select_scanin),
   .scan_out(dff_inreg_select_scanout),
   .din		(input_req_sel_q),
   .dout		(input_req_sel_a),
   .l1clk		(l1clk),
  .siclk(siclk),
  .soclk(soclk)
   );

ccx_arc_ctl_msff_ctl_macro dff_inreg_select_x 
  (
   .scan_in(dff_inreg_select__scanin),
   .scan_out(dff_inreg_select__scanout),
   .din		(input_req_sel_q_),
   .dout		(input_req_sel_a_),
   .l1clk		(l1clk),
  .siclk(siclk),
  .soclk(soclk)
   );


//assign direction_in = (current_req_sel_a ~^ direction);
assign direction_in = ~direction;

ccx_arc_ctl_msff_ctl_macro dff_dir 
  (
   .scan_in(dff_dir_scanin),
   .scan_out(dff_dir_scanout),
   .din		(direction_in),
   .dout		(direction),
   .l1clk		(l1clk),
  .siclk(siclk),
  .soclk(soclk)
   );


//assign dira = ~stall_a & direction;
//assign dird = ~stall_a & ~direction;


// ARB SRC Q LOGIC
///*
// ccx_srq_ctl    AUTO_TEMPLATE(
// // Outputs
// .scan_in(AUTO_TEMPLATE_scanin),
// .scan_out(AUTO_TEMPLATE_scanout),
// .qfull_a		(qfull_a[@]),
// .qfullbar_a		(qfullbar_a[@]),
// .qsel0_a		(arb_qsel0_a[@]),
// .qsel1_a		(arb_qsel1_a[@]),
// .shift_a	(arb_shift_a[@]),
// .q0_holdbar_a	(arb_q0_holdbar_a[@]),
// .atom_x(atom_x[@]),
// // Inputs
// .req_q		(src@_arb_req_q),
// .atom_q		(src@_arb_atom_q),
// .grant_a	(grant_a[@]));
//  */

ccx_srq_ctl q0 (
/*AUTOINST*/
                // Outputs
                .scan_in(q0_scanin),
                .scan_out(q0_scanout),
                .qfull_a                (qfull_a[0]),            // Templated
                .qfullbar_a             (qfullbar_a[0]),         // Templated
                .qsel0_a                (arb_qsel0_a[0]),        // Templated
                .qsel1_a                (arb_qsel1_a[0]),        // Templated
                .shift_a                (arb_shift_a[0]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[0]),   // Templated
                .atom_x                 (atom_x[0]),             // Templated
                // Inputs
                .req_a                  (req_a[0]),              // Templated
                .atom_a                 (atom_a[0]),             // Templated
                .grant_a                (grant_a[0]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 

ccx_srq_ctl q1 (
/*AUTOINST*/
                // Outputs
                .scan_in(q1_scanin),
                .scan_out(q1_scanout),
                .qfull_a                (qfull_a[1]),            // Templated
                .qfullbar_a             (qfullbar_a[1]),         // Templated
                .qsel0_a                (arb_qsel0_a[1]),        // Templated
                .qsel1_a                (arb_qsel1_a[1]),        // Templated
                .shift_a                (arb_shift_a[1]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[1]),   // Templated
                .atom_x                 (atom_x[1]),             // Templated
                // Inputs
                .req_a                  (req_a[1]),              // Templated
                .atom_a                 (atom_a[1]),             // Templated
                .grant_a                (grant_a[1]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 

ccx_srq_ctl q2 (
/*AUTOINST*/
                // Outputs
                .scan_in(q2_scanin),
                .scan_out(q2_scanout),
                .qfull_a                (qfull_a[2]),            // Templated
                .qfullbar_a             (qfullbar_a[2]),         // Templated
                .qsel0_a                (arb_qsel0_a[2]),        // Templated
                .qsel1_a                (arb_qsel1_a[2]),        // Templated
                .shift_a                (arb_shift_a[2]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[2]),   // Templated
                .atom_x                 (atom_x[2]),             // Templated
                // Inputs
                .req_a                  (req_a[2]),              // Templated
                .atom_a                 (atom_a[2]),             // Templated
                .grant_a                (grant_a[2]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 

ccx_srq_ctl q3 (
/*AUTOINST*/
                // Outputs
                .scan_in(q3_scanin),
                .scan_out(q3_scanout),
                .qfull_a                (qfull_a[3]),            // Templated
                .qfullbar_a             (qfullbar_a[3]),         // Templated
                .qsel0_a                (arb_qsel0_a[3]),        // Templated
                .qsel1_a                (arb_qsel1_a[3]),        // Templated
                .shift_a                (arb_shift_a[3]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[3]),   // Templated
                .atom_x                 (atom_x[3]),             // Templated
                // Inputs
                .req_a                  (req_a[3]),              // Templated
                .atom_a                 (atom_a[3]),             // Templated
                .grant_a                (grant_a[3]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 

ccx_srq_ctl q4 (
/*AUTOINST*/
                // Outputs
                .scan_in(q4_scanin),
                .scan_out(q4_scanout),
                .qfull_a                (qfull_a[4]),            // Templated
                .qfullbar_a             (qfullbar_a[4]),         // Templated
                .qsel0_a                (arb_qsel0_a[4]),        // Templated
                .qsel1_a                (arb_qsel1_a[4]),        // Templated
                .shift_a                (arb_shift_a[4]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[4]),   // Templated
                .atom_x                 (atom_x[4]),             // Templated
                // Inputs
                .req_a                  (req_a[4]),              // Templated
                .atom_a                 (atom_a[4]),             // Templated
                .grant_a                (grant_a[4]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 

ccx_srq_ctl q5 (
/*AUTOINST*/
                // Outputs
                .scan_in(q5_scanin),
                .scan_out(q5_scanout),
                .qfull_a                (qfull_a[5]),            // Templated
                .qfullbar_a             (qfullbar_a[5]),         // Templated
                .qsel0_a                (arb_qsel0_a[5]),        // Templated
                .qsel1_a                (arb_qsel1_a[5]),        // Templated
                .shift_a                (arb_shift_a[5]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[5]),   // Templated
                .atom_x                 (atom_x[5]),             // Templated
                // Inputs
                .req_a                  (req_a[5]),              // Templated
                .atom_a                 (atom_a[5]),             // Templated
                .grant_a                (grant_a[5]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 

ccx_srq_ctl q6 (
/*AUTOINST*/
                // Outputs
                .scan_in(q6_scanin),
                .scan_out(q6_scanout),
                .qfull_a                (qfull_a[6]),            // Templated
                .qfullbar_a             (qfullbar_a[6]),         // Templated
                .qsel0_a                (arb_qsel0_a[6]),        // Templated
                .qsel1_a                (arb_qsel1_a[6]),        // Templated
                .shift_a                (arb_shift_a[6]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[6]),   // Templated
                .atom_x                 (atom_x[6]),             // Templated
                // Inputs
                .req_a                  (req_a[6]),              // Templated
                .atom_a                 (atom_a[6]),             // Templated
                .grant_a                (grant_a[6]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 

ccx_srq_ctl q7 (
/*AUTOINST*/
                // Outputs
                .scan_in(q7_scanin),
                .scan_out(q7_scanout),
                .qfull_a                (qfull_a[7]),            // Templated
                .qfullbar_a             (qfullbar_a[7]),         // Templated
                .qsel0_a                (arb_qsel0_a[7]),        // Templated
                .qsel1_a                (arb_qsel1_a[7]),        // Templated
                .shift_a                (arb_shift_a[7]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[7]),   // Templated
                .atom_x                 (atom_x[7]),             // Templated
                // Inputs
                .req_a                  (req_a[7]),              // Templated
                .atom_a                 (atom_a[7]),             // Templated
                .grant_a                (grant_a[7]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 

ccx_srq_ctl q8 (
/*AUTOINST*/
                // Outputs
                .scan_in(q8_scanin),
                .scan_out(q8_scanout),
                .qfull_a                (qfull_a[8]),            // Templated
                .qfullbar_a             (qfullbar_a[8]),         // Templated
                .qsel0_a                (arb_qsel0_a[8]),        // Templated
                .qsel1_a                (arb_qsel1_a[8]),        // Templated
                .shift_a                (arb_shift_a[8]),        // Templated
                .q0_holdbar_a           (arb_q0_holdbar_a[8]),   // Templated
                .atom_x                 (atom_x[8]),             // Templated
                // Inputs
                .req_a                  (req_a[8]),              // Templated
                .atom_a                 (atom_a[8]),             // Templated
                .grant_a                (grant_a[8]),            // Templated
                .l1clk                  (l1clk),
  .ccx_aclk(ccx_aclk),
  .ccx_bclk(ccx_bclk));		 


////////////////////////////////////////////////////////
// SPARE CELLS
////////////////////////////////////////////////////////
ccx_arc_ctl_spare_ctl_macro__num_10 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
////////////////////////////////////////////////////////

// fixscan start:
assign dff_wptr_scanin           = scan_in                  ;
assign dff_rptr_scanin           = dff_wptr_scanout         ;
assign dff_inreg_select_scanin   = dff_rptr_scanout         ;
assign dff_inreg_select__scanin  = dff_inreg_select_scanout ;
assign dff_dir_scanin            = dff_inreg_select__scanout;
assign q0_scanin                 = dff_dir_scanout          ;
assign q1_scanin                 = q0_scanout               ;
assign q2_scanin                 = q1_scanout               ;
assign q3_scanin                 = q2_scanout               ;
assign q4_scanin                 = q3_scanout               ;
assign q5_scanin                 = q4_scanout               ;
assign q6_scanin                 = q5_scanout               ;
assign q7_scanin                 = q6_scanout               ;
assign q8_scanin                 = q7_scanout               ;
assign spares_scanin             = q8_scanout               ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


// any PARAMS parms go into naming of macro

module ccx_arc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_arc_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_arc_ctl_msff_ctl_macro (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ccx_arc_ctl_spare_ctl_macro__num_10 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire si_8;
wire so_8;
wire spare8_flop_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;
wire si_9;
wire so_9;
wire spare9_flop_unused;
wire spare9_buf_32x_unused;
wire spare9_nand3_8x_unused;
wire spare9_inv_8x_unused;
wire spare9_aoi22_4x_unused;
wire spare9_buf_8x_unused;
wire spare9_oai22_4x_unused;
wire spare9_inv_16x_unused;
wire spare9_nand2_16x_unused;
wire spare9_nor3_4x_unused;
wire spare9_nand2_8x_unused;
wire spare9_buf_16x_unused;
wire spare9_nor2_16x_unused;
wire spare9_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));

cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_8),
                               .so(so_8),
                               .d(1'b0),
                               .q(spare8_flop_unused));
assign si_8 = so_7;

cl_u1_buf_32x   spare8_buf_32x (.in(1'b1),
                                   .out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare8_nand3_8x_unused));
cl_u1_inv_8x    spare8_inv_8x (.in(1'b1),
                                  .out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_aoi22_4x_unused));
cl_u1_buf_8x    spare8_buf_8x (.in(1'b1),
                                  .out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_oai22_4x_unused));
cl_u1_inv_16x   spare8_inv_16x (.in(1'b1),
                                   .out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare8_nand2_8x_unused));
cl_u1_buf_16x   spare8_buf_16x (.in(1'b1),
                                   .out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare8_nor2_16x_unused));
cl_u1_inv_32x   spare8_inv_32x (.in(1'b1),
                                   .out(spare8_inv_32x_unused));

cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_9),
                               .so(so_9),
                               .d(1'b0),
                               .q(spare9_flop_unused));
assign si_9 = so_8;

cl_u1_buf_32x   spare9_buf_32x (.in(1'b1),
                                   .out(spare9_buf_32x_unused));
cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare9_nand3_8x_unused));
cl_u1_inv_8x    spare9_inv_8x (.in(1'b1),
                                  .out(spare9_inv_8x_unused));
cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_aoi22_4x_unused));
cl_u1_buf_8x    spare9_buf_8x (.in(1'b1),
                                  .out(spare9_buf_8x_unused));
cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_oai22_4x_unused));
cl_u1_inv_16x   spare9_inv_16x (.in(1'b1),
                                   .out(spare9_inv_16x_unused));
cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare9_nand2_16x_unused));
cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare9_nor3_4x_unused));
cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare9_nand2_8x_unused));
cl_u1_buf_16x   spare9_buf_16x (.in(1'b1),
                                   .out(spare9_buf_16x_unused));
cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare9_nor2_16x_unused));
cl_u1_inv_32x   spare9_inv_32x (.in(1'b1),
                                   .out(spare9_inv_32x_unused));
assign scan_out = so_9;


endmodule
`endif // `ifndef FPGA

`ifdef FPGA
module ccx_arc_ctl(grant_a, req_pkt_empty_a, direction, write_fifo_a, 
	fifo_rptr_a, fifo_read_select, input_req_sel_a, input_req_sel_a_, 
	fifo_req_sel_a, qfullbar_a, atom_x, arb_qsel0_a, arb_qsel1_a, 
	arb_shift_a, arb_q0_holdbar_a, atom_a, req_a, tcu_scan_en, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	input	[8:0]		grant_a;
	input			req_pkt_empty_a;
	output			direction;
	output	[17:0]		write_fifo_a;
	output	[2:0]		fifo_rptr_a;
	output	[1:0]		fifo_read_select;
	output			input_req_sel_a;
	output			input_req_sel_a_;
	output			fifo_req_sel_a;
	output	[8:0]		qfullbar_a;
	output	[8:0]		atom_x;
	output	[8:0]		arb_qsel0_a;
	output	[8:0]		arb_qsel1_a;
	output	[8:0]		arb_shift_a;
	output	[8:0]		arb_q0_holdbar_a;
	input	[8:0]		atom_a;
	input	[8:0]		req_a;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk;
	wire			soclk;
	wire			se;
	wire			l1clk;
	wire	[8:0]		input_req_a;
	wire	[8:0]		qfull_a;
	wire			inreg_req_vld_a;
	wire			wr_en_a;
	wire			fifo_empty_a;
	wire			wptr_eq17;
	wire	[4:0]		wptr_a;
	wire	[4:0]		wptr_next;
	wire			dff_wptr_scanin;
	wire			dff_wptr_scanout;
	wire			rd_en_a;
	wire			rptr_eq17;
	wire	[4:0]		rptr_a;
	wire	[4:0]		rptr_next;
	wire			dff_rptr_scanin;
	wire			dff_rptr_scanout;
	wire			fifo_bypass_a;
	wire	[17:0]		wptr_dcd_a;
	wire			input_req_sel_q;
	wire			input_req_sel_q_;
	wire			dff_inreg_select_scanin;
	wire			dff_inreg_select_scanout;
	wire			dff_inreg_select__scanin;
	wire			dff_inreg_select__scanout;
	wire			direction_in;
	wire			dff_dir_scanin;
	wire			dff_dir_scanout;
	wire			q0_scanin;
	wire			q0_scanout;
	wire			q1_scanin;
	wire			q1_scanout;
	wire			q2_scanin;
	wire			q2_scanout;
	wire			q3_scanin;
	wire			q3_scanout;
	wire			q4_scanin;
	wire			q4_scanout;
	wire			q5_scanin;
	wire			q5_scanout;
	wire			q6_scanin;
	wire			q6_scanout;
	wire			q7_scanin;
	wire			q7_scanout;
	wire			q8_scanin;
	wire			q8_scanout;
	wire			spares_scanin;
	wire			spares_scanout;

	assign pce_ov = tcu_pce_ov;
	assign stop = 1'b0;
	assign siclk = ccx_aclk;
	assign soclk = ccx_bclk;
	assign se = tcu_scan_en;
	assign input_req_a[8:0] = (req_a[8:0] & (~qfull_a[8:0]));
	assign inreg_req_vld_a = (|input_req_a[8:0]);
	assign wr_en_a = (((~input_req_sel_a) & inreg_req_vld_a) & ((~
		req_pkt_empty_a) | (~fifo_empty_a)));
	assign wptr_eq17 = (wptr_a[4:0] == 5'b10001);
	assign wptr_next[4:0] = (wr_en_a ? (wptr_eq17 ? 5'b0 : (wptr_a[4:0] + 
		5'b1)) : wptr_a[4:0]);
	assign rd_en_a = (req_pkt_empty_a & (~fifo_empty_a));
	assign rptr_eq17 = (rptr_a[4:0] == 5'b10001);
	assign rptr_next[4:0] = (rd_en_a ? (rptr_eq17 ? 5'b0 : (rptr_a[4:0] + 
		5'b1)) : rptr_a[4:0]);
	assign fifo_rptr_a[2:0] = rptr_a[2:0];
	assign fifo_read_select[1:0] = (rptr_a[4:3] | {2 {fifo_bypass_a}});
	assign fifo_empty_a = (rptr_a[4:0] == wptr_a[4:0]);
	assign fifo_bypass_a = (fifo_empty_a & inreg_req_vld_a);
	assign wptr_dcd_a[0] = (((((~wptr_a[4]) & (~wptr_a[3])) & (~wptr_a[2])) 
		& (~wptr_a[1])) & (~wptr_a[0]));
	assign wptr_dcd_a[1] = (((((~wptr_a[4]) & (~wptr_a[3])) & (~wptr_a[2])) 
		& (~wptr_a[1])) & wptr_a[0]);
	assign wptr_dcd_a[2] = (((((~wptr_a[4]) & (~wptr_a[3])) & (~wptr_a[2])) 
		& wptr_a[1]) & (~wptr_a[0]));
	assign wptr_dcd_a[3] = (((((~wptr_a[4]) & (~wptr_a[3])) & (~wptr_a[2])) 
		& wptr_a[1]) & wptr_a[0]);
	assign wptr_dcd_a[4] = (((((~wptr_a[4]) & (~wptr_a[3])) & wptr_a[2]) & (
		~wptr_a[1])) & (~wptr_a[0]));
	assign wptr_dcd_a[5] = (((((~wptr_a[4]) & (~wptr_a[3])) & wptr_a[2]) & (
		~wptr_a[1])) & wptr_a[0]);
	assign wptr_dcd_a[6] = (((((~wptr_a[4]) & (~wptr_a[3])) & wptr_a[2]) & 
		wptr_a[1]) & (~wptr_a[0]));
	assign wptr_dcd_a[7] = (((((~wptr_a[4]) & (~wptr_a[3])) & wptr_a[2]) & 
		wptr_a[1]) & wptr_a[0]);
	assign wptr_dcd_a[8] = (((((~wptr_a[4]) & wptr_a[3]) & (~wptr_a[2])) & (
		~wptr_a[1])) & (~wptr_a[0]));
	assign wptr_dcd_a[9] = (((((~wptr_a[4]) & wptr_a[3]) & (~wptr_a[2])) & (
		~wptr_a[1])) & wptr_a[0]);
	assign wptr_dcd_a[10] = (((((~wptr_a[4]) & wptr_a[3]) & (~wptr_a[2])) & 
		wptr_a[1]) & (~wptr_a[0]));
	assign wptr_dcd_a[11] = (((((~wptr_a[4]) & wptr_a[3]) & (~wptr_a[2])) & 
		wptr_a[1]) & wptr_a[0]);
	assign wptr_dcd_a[12] = (((((~wptr_a[4]) & wptr_a[3]) & wptr_a[2]) & (~
		wptr_a[1])) & (~wptr_a[0]));
	assign wptr_dcd_a[13] = (((((~wptr_a[4]) & wptr_a[3]) & wptr_a[2]) & (~
		wptr_a[1])) & wptr_a[0]);
	assign wptr_dcd_a[14] = (((((~wptr_a[4]) & wptr_a[3]) & wptr_a[2]) & 
		wptr_a[1]) & (~wptr_a[0]));
	assign wptr_dcd_a[15] = (((((~wptr_a[4]) & wptr_a[3]) & wptr_a[2]) & 
		wptr_a[1]) & wptr_a[0]);
	assign wptr_dcd_a[16] = ((((wptr_a[4] & (~wptr_a[3])) & (~wptr_a[2])) & 
		(~wptr_a[1])) & (~wptr_a[0]));
	assign wptr_dcd_a[17] = ((((wptr_a[4] & (~wptr_a[3])) & (~wptr_a[2])) & 
		(~wptr_a[1])) & wptr_a[0]);
	assign write_fifo_a[17:0] = wptr_dcd_a[17:0];
	assign input_req_sel_q = (((req_pkt_empty_a & fifo_empty_a) & (~
		inreg_req_vld_a)) | (req_pkt_empty_a & input_req_sel_a));
	assign fifo_req_sel_a = (req_pkt_empty_a & ((~fifo_empty_a) | (
		inreg_req_vld_a & (~input_req_sel_a))));
	assign input_req_sel_q_ = (~input_req_sel_q);
	assign direction_in = (~direction);
	assign dff_wptr_scanin = scan_in;
	assign dff_rptr_scanin = dff_wptr_scanout;
	assign dff_inreg_select_scanin = dff_rptr_scanout;
	assign dff_inreg_select__scanin = dff_inreg_select_scanout;
	assign dff_dir_scanin = dff_inreg_select__scanout;
	assign q0_scanin = dff_dir_scanout;
	assign q1_scanin = q0_scanout;
	assign q2_scanin = q1_scanout;
	assign q3_scanin = q2_scanout;
	assign q4_scanin = q3_scanout;
	assign q5_scanin = q4_scanout;
	assign q6_scanin = q5_scanout;
	assign q7_scanin = q6_scanout;
	assign q8_scanin = q7_scanout;
	assign spares_scanin = q8_scanout;
	assign scan_out = spares_scanout;

	l1clkhdr_ctl_macro clkgen(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clk), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	msff_ctl_macro__width_5 dff_wptr(
		.scan_in			(dff_wptr_scanin), 
		.scan_out			(dff_wptr_scanout), 
		.din				(wptr_next[4:0]), 
		.dout				(wptr_a[4:0]), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__width_5 dff_rptr(
		.scan_in			(dff_rptr_scanin), 
		.scan_out			(dff_rptr_scanout), 
		.din				(rptr_next[4:0]), 
		.dout				(rptr_a[4:0]), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_inreg_select(
		.scan_in			(dff_inreg_select_scanin), 
		.scan_out			(dff_inreg_select_scanout), 
		.din				(input_req_sel_q), 
		.dout				(input_req_sel_a), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_inreg_select_x(
		.scan_in			(dff_inreg_select__scanin), 
		.scan_out			(dff_inreg_select__scanout), 
		.din				(input_req_sel_q_), 
		.dout				(input_req_sel_a_), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_dir(
		.scan_in			(dff_dir_scanin), 
		.scan_out			(dff_dir_scanout), 
		.din				(direction_in), 
		.dout				(direction), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	ccx_srq_ctl q0(
		.scan_in			(q0_scanin), 
		.scan_out			(q0_scanout), 
		.qfull_a			(qfull_a[0]), 
		.qfullbar_a			(qfullbar_a[0]), 
		.qsel0_a			(arb_qsel0_a[0]), 
		.qsel1_a			(arb_qsel1_a[0]), 
		.shift_a			(arb_shift_a[0]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[0]), 
		.atom_x				(atom_x[0]), 
		.req_a				(req_a[0]), 
		.atom_a				(atom_a[0]), 
		.grant_a			(grant_a[0]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	ccx_srq_ctl q1(
		.scan_in			(q1_scanin), 
		.scan_out			(q1_scanout), 
		.qfull_a			(qfull_a[1]), 
		.qfullbar_a			(qfullbar_a[1]), 
		.qsel0_a			(arb_qsel0_a[1]), 
		.qsel1_a			(arb_qsel1_a[1]), 
		.shift_a			(arb_shift_a[1]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[1]), 
		.atom_x				(atom_x[1]), 
		.req_a				(req_a[1]), 
		.atom_a				(atom_a[1]), 
		.grant_a			(grant_a[1]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	ccx_srq_ctl q2(
		.scan_in			(q2_scanin), 
		.scan_out			(q2_scanout), 
		.qfull_a			(qfull_a[2]), 
		.qfullbar_a			(qfullbar_a[2]), 
		.qsel0_a			(arb_qsel0_a[2]), 
		.qsel1_a			(arb_qsel1_a[2]), 
		.shift_a			(arb_shift_a[2]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[2]), 
		.atom_x				(atom_x[2]), 
		.req_a				(req_a[2]), 
		.atom_a				(atom_a[2]), 
		.grant_a			(grant_a[2]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	ccx_srq_ctl q3(
		.scan_in			(q3_scanin), 
		.scan_out			(q3_scanout), 
		.qfull_a			(qfull_a[3]), 
		.qfullbar_a			(qfullbar_a[3]), 
		.qsel0_a			(arb_qsel0_a[3]), 
		.qsel1_a			(arb_qsel1_a[3]), 
		.shift_a			(arb_shift_a[3]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[3]), 
		.atom_x				(atom_x[3]), 
		.req_a				(req_a[3]), 
		.atom_a				(atom_a[3]), 
		.grant_a			(grant_a[3]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	ccx_srq_ctl q4(
		.scan_in			(q4_scanin), 
		.scan_out			(q4_scanout), 
		.qfull_a			(qfull_a[4]), 
		.qfullbar_a			(qfullbar_a[4]), 
		.qsel0_a			(arb_qsel0_a[4]), 
		.qsel1_a			(arb_qsel1_a[4]), 
		.shift_a			(arb_shift_a[4]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[4]), 
		.atom_x				(atom_x[4]), 
		.req_a				(req_a[4]), 
		.atom_a				(atom_a[4]), 
		.grant_a			(grant_a[4]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	ccx_srq_ctl q5(
		.scan_in			(q5_scanin), 
		.scan_out			(q5_scanout), 
		.qfull_a			(qfull_a[5]), 
		.qfullbar_a			(qfullbar_a[5]), 
		.qsel0_a			(arb_qsel0_a[5]), 
		.qsel1_a			(arb_qsel1_a[5]), 
		.shift_a			(arb_shift_a[5]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[5]), 
		.atom_x				(atom_x[5]), 
		.req_a				(req_a[5]), 
		.atom_a				(atom_a[5]), 
		.grant_a			(grant_a[5]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	ccx_srq_ctl q6(
		.scan_in			(q6_scanin), 
		.scan_out			(q6_scanout), 
		.qfull_a			(qfull_a[6]), 
		.qfullbar_a			(qfullbar_a[6]), 
		.qsel0_a			(arb_qsel0_a[6]), 
		.qsel1_a			(arb_qsel1_a[6]), 
		.shift_a			(arb_shift_a[6]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[6]), 
		.atom_x				(atom_x[6]), 
		.req_a				(req_a[6]), 
		.atom_a				(atom_a[6]), 
		.grant_a			(grant_a[6]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	ccx_srq_ctl q7(
		.scan_in			(q7_scanin), 
		.scan_out			(q7_scanout), 
		.qfull_a			(qfull_a[7]), 
		.qfullbar_a			(qfullbar_a[7]), 
		.qsel0_a			(arb_qsel0_a[7]), 
		.qsel1_a			(arb_qsel1_a[7]), 
		.shift_a			(arb_shift_a[7]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[7]), 
		.atom_x				(atom_x[7]), 
		.req_a				(req_a[7]), 
		.atom_a				(atom_a[7]), 
		.grant_a			(grant_a[7]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	ccx_srq_ctl q8(
		.scan_in			(q8_scanin), 
		.scan_out			(q8_scanout), 
		.qfull_a			(qfull_a[8]), 
		.qfullbar_a			(qfullbar_a[8]), 
		.qsel0_a			(arb_qsel0_a[8]), 
		.qsel1_a			(arb_qsel1_a[8]), 
		.shift_a			(arb_shift_a[8]), 
		.q0_holdbar_a			(arb_q0_holdbar_a[8]), 
		.atom_x				(atom_x[8]), 
		.req_a				(req_a[8]), 
		.atom_a				(atom_a[8]), 
		.grant_a			(grant_a[8]), 
		.l1clk				(l1clk), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	spare_ctl_macro__num_10 spares(
		.scan_in			(spares_scanin), 
		.scan_out			(spares_scanout), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
endmodule
`endcelldefine

`celldefine
module msff_ctl_macro(din, l1clk, scan_in, siclk, soclk, dout, scan_out);

	input	[0:0]		din;
	input			l1clk;
	input			scan_in;
	input			siclk;
	input			soclk;
	output	[0:0]		dout;
	output			scan_out;

	wire	[0:0]		fdin;

	assign fdin[0] = din[0];

	dff #(1) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.d				(fdin[0]), 
		.si				(scan_in), 
		.so				(scan_out), 
		.q				(dout[0]));
endmodule
`endcelldefine

`celldefine
module spare_ctl_macro__num_10(l1clk, scan_in, siclk, soclk, scan_out);

	input			l1clk;
	input			scan_in;
	input			siclk;
	input			soclk;
	output			scan_out;

	wire			si_0;
	wire			so_0;
	wire			spare0_flop_unused;
	wire			spare0_buf_32x_unused;
	wire			spare0_nand3_8x_unused;
	wire			spare0_inv_8x_unused;
	wire			spare0_aoi22_4x_unused;
	wire			spare0_buf_8x_unused;
	wire			spare0_oai22_4x_unused;
	wire			spare0_inv_16x_unused;
	wire			spare0_nand2_16x_unused;
	wire			spare0_nor3_4x_unused;
	wire			spare0_nand2_8x_unused;
	wire			spare0_buf_16x_unused;
	wire			spare0_nor2_16x_unused;
	wire			spare0_inv_32x_unused;
	wire			si_1;
	wire			so_1;
	wire			spare1_flop_unused;
	wire			spare1_buf_32x_unused;
	wire			spare1_nand3_8x_unused;
	wire			spare1_inv_8x_unused;
	wire			spare1_aoi22_4x_unused;
	wire			spare1_buf_8x_unused;
	wire			spare1_oai22_4x_unused;
	wire			spare1_inv_16x_unused;
	wire			spare1_nand2_16x_unused;
	wire			spare1_nor3_4x_unused;
	wire			spare1_nand2_8x_unused;
	wire			spare1_buf_16x_unused;
	wire			spare1_nor2_16x_unused;
	wire			spare1_inv_32x_unused;
	wire			si_2;
	wire			so_2;
	wire			spare2_flop_unused;
	wire			spare2_buf_32x_unused;
	wire			spare2_nand3_8x_unused;
	wire			spare2_inv_8x_unused;
	wire			spare2_aoi22_4x_unused;
	wire			spare2_buf_8x_unused;
	wire			spare2_oai22_4x_unused;
	wire			spare2_inv_16x_unused;
	wire			spare2_nand2_16x_unused;
	wire			spare2_nor3_4x_unused;
	wire			spare2_nand2_8x_unused;
	wire			spare2_buf_16x_unused;
	wire			spare2_nor2_16x_unused;
	wire			spare2_inv_32x_unused;
	wire			si_3;
	wire			so_3;
	wire			spare3_flop_unused;
	wire			spare3_buf_32x_unused;
	wire			spare3_nand3_8x_unused;
	wire			spare3_inv_8x_unused;
	wire			spare3_aoi22_4x_unused;
	wire			spare3_buf_8x_unused;
	wire			spare3_oai22_4x_unused;
	wire			spare3_inv_16x_unused;
	wire			spare3_nand2_16x_unused;
	wire			spare3_nor3_4x_unused;
	wire			spare3_nand2_8x_unused;
	wire			spare3_buf_16x_unused;
	wire			spare3_nor2_16x_unused;
	wire			spare3_inv_32x_unused;
	wire			si_4;
	wire			so_4;
	wire			spare4_flop_unused;
	wire			spare4_buf_32x_unused;
	wire			spare4_nand3_8x_unused;
	wire			spare4_inv_8x_unused;
	wire			spare4_aoi22_4x_unused;
	wire			spare4_buf_8x_unused;
	wire			spare4_oai22_4x_unused;
	wire			spare4_inv_16x_unused;
	wire			spare4_nand2_16x_unused;
	wire			spare4_nor3_4x_unused;
	wire			spare4_nand2_8x_unused;
	wire			spare4_buf_16x_unused;
	wire			spare4_nor2_16x_unused;
	wire			spare4_inv_32x_unused;
	wire			si_5;
	wire			so_5;
	wire			spare5_flop_unused;
	wire			spare5_buf_32x_unused;
	wire			spare5_nand3_8x_unused;
	wire			spare5_inv_8x_unused;
	wire			spare5_aoi22_4x_unused;
	wire			spare5_buf_8x_unused;
	wire			spare5_oai22_4x_unused;
	wire			spare5_inv_16x_unused;
	wire			spare5_nand2_16x_unused;
	wire			spare5_nor3_4x_unused;
	wire			spare5_nand2_8x_unused;
	wire			spare5_buf_16x_unused;
	wire			spare5_nor2_16x_unused;
	wire			spare5_inv_32x_unused;
	wire			si_6;
	wire			so_6;
	wire			spare6_flop_unused;
	wire			spare6_buf_32x_unused;
	wire			spare6_nand3_8x_unused;
	wire			spare6_inv_8x_unused;
	wire			spare6_aoi22_4x_unused;
	wire			spare6_buf_8x_unused;
	wire			spare6_oai22_4x_unused;
	wire			spare6_inv_16x_unused;
	wire			spare6_nand2_16x_unused;
	wire			spare6_nor3_4x_unused;
	wire			spare6_nand2_8x_unused;
	wire			spare6_buf_16x_unused;
	wire			spare6_nor2_16x_unused;
	wire			spare6_inv_32x_unused;
	wire			si_7;
	wire			so_7;
	wire			spare7_flop_unused;
	wire			spare7_buf_32x_unused;
	wire			spare7_nand3_8x_unused;
	wire			spare7_inv_8x_unused;
	wire			spare7_aoi22_4x_unused;
	wire			spare7_buf_8x_unused;
	wire			spare7_oai22_4x_unused;
	wire			spare7_inv_16x_unused;
	wire			spare7_nand2_16x_unused;
	wire			spare7_nor3_4x_unused;
	wire			spare7_nand2_8x_unused;
	wire			spare7_buf_16x_unused;
	wire			spare7_nor2_16x_unused;
	wire			spare7_inv_32x_unused;
	wire			si_8;
	wire			so_8;
	wire			spare8_flop_unused;
	wire			spare8_buf_32x_unused;
	wire			spare8_nand3_8x_unused;
	wire			spare8_inv_8x_unused;
	wire			spare8_aoi22_4x_unused;
	wire			spare8_buf_8x_unused;
	wire			spare8_oai22_4x_unused;
	wire			spare8_inv_16x_unused;
	wire			spare8_nand2_16x_unused;
	wire			spare8_nor3_4x_unused;
	wire			spare8_nand2_8x_unused;
	wire			spare8_buf_16x_unused;
	wire			spare8_nor2_16x_unused;
	wire			spare8_inv_32x_unused;
	wire			si_9;
	wire			so_9;
	wire			spare9_flop_unused;
	wire			spare9_buf_32x_unused;
	wire			spare9_nand3_8x_unused;
	wire			spare9_inv_8x_unused;
	wire			spare9_aoi22_4x_unused;
	wire			spare9_buf_8x_unused;
	wire			spare9_oai22_4x_unused;
	wire			spare9_inv_16x_unused;
	wire			spare9_nand2_16x_unused;
	wire			spare9_nor3_4x_unused;
	wire			spare9_nand2_8x_unused;
	wire			spare9_buf_16x_unused;
	wire			spare9_nor2_16x_unused;
	wire			spare9_inv_32x_unused;

	assign si_0 = scan_in;
	assign si_1 = so_0;
	assign si_2 = so_1;
	assign si_3 = so_2;
	assign si_4 = so_3;
	assign si_5 = so_4;
	assign si_6 = so_5;
	assign si_7 = so_6;
	assign si_8 = so_7;
	assign si_9 = so_8;
	assign scan_out = so_9;

	cl_sc1_msff_8x spare0_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_0), 
		.so				(so_0), 
		.d				(1'b0), 
		.q				(spare0_flop_unused));
	cl_u1_buf_32x spare0_buf_32x(
		.in				(1'b1), 
		.out				(spare0_buf_32x_unused));
	cl_u1_nand3_8x spare0_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare0_nand3_8x_unused));
	cl_u1_inv_8x spare0_inv_8x(
		.in				(1'b1), 
		.out				(spare0_inv_8x_unused));
	cl_u1_aoi22_4x spare0_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare0_aoi22_4x_unused));
	cl_u1_buf_8x spare0_buf_8x(
		.in				(1'b1), 
		.out				(spare0_buf_8x_unused));
	cl_u1_oai22_4x spare0_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare0_oai22_4x_unused));
	cl_u1_inv_16x spare0_inv_16x(
		.in				(1'b1), 
		.out				(spare0_inv_16x_unused));
	cl_u1_nand2_16x spare0_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare0_nand2_16x_unused));
	cl_u1_nor3_4x spare0_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare0_nor3_4x_unused));
	cl_u1_nand2_8x spare0_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare0_nand2_8x_unused));
	cl_u1_buf_16x spare0_buf_16x(
		.in				(1'b1), 
		.out				(spare0_buf_16x_unused));
	cl_u1_nor2_16x spare0_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare0_nor2_16x_unused));
	cl_u1_inv_32x spare0_inv_32x(
		.in				(1'b1), 
		.out				(spare0_inv_32x_unused));
	cl_sc1_msff_8x spare1_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_1), 
		.so				(so_1), 
		.d				(1'b0), 
		.q				(spare1_flop_unused));
	cl_u1_buf_32x spare1_buf_32x(
		.in				(1'b1), 
		.out				(spare1_buf_32x_unused));
	cl_u1_nand3_8x spare1_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare1_nand3_8x_unused));
	cl_u1_inv_8x spare1_inv_8x(
		.in				(1'b1), 
		.out				(spare1_inv_8x_unused));
	cl_u1_aoi22_4x spare1_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare1_aoi22_4x_unused));
	cl_u1_buf_8x spare1_buf_8x(
		.in				(1'b1), 
		.out				(spare1_buf_8x_unused));
	cl_u1_oai22_4x spare1_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare1_oai22_4x_unused));
	cl_u1_inv_16x spare1_inv_16x(
		.in				(1'b1), 
		.out				(spare1_inv_16x_unused));
	cl_u1_nand2_16x spare1_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare1_nand2_16x_unused));
	cl_u1_nor3_4x spare1_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare1_nor3_4x_unused));
	cl_u1_nand2_8x spare1_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare1_nand2_8x_unused));
	cl_u1_buf_16x spare1_buf_16x(
		.in				(1'b1), 
		.out				(spare1_buf_16x_unused));
	cl_u1_nor2_16x spare1_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare1_nor2_16x_unused));
	cl_u1_inv_32x spare1_inv_32x(
		.in				(1'b1), 
		.out				(spare1_inv_32x_unused));
	cl_sc1_msff_8x spare2_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_2), 
		.so				(so_2), 
		.d				(1'b0), 
		.q				(spare2_flop_unused));
	cl_u1_buf_32x spare2_buf_32x(
		.in				(1'b1), 
		.out				(spare2_buf_32x_unused));
	cl_u1_nand3_8x spare2_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare2_nand3_8x_unused));
	cl_u1_inv_8x spare2_inv_8x(
		.in				(1'b1), 
		.out				(spare2_inv_8x_unused));
	cl_u1_aoi22_4x spare2_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare2_aoi22_4x_unused));
	cl_u1_buf_8x spare2_buf_8x(
		.in				(1'b1), 
		.out				(spare2_buf_8x_unused));
	cl_u1_oai22_4x spare2_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare2_oai22_4x_unused));
	cl_u1_inv_16x spare2_inv_16x(
		.in				(1'b1), 
		.out				(spare2_inv_16x_unused));
	cl_u1_nand2_16x spare2_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare2_nand2_16x_unused));
	cl_u1_nor3_4x spare2_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare2_nor3_4x_unused));
	cl_u1_nand2_8x spare2_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare2_nand2_8x_unused));
	cl_u1_buf_16x spare2_buf_16x(
		.in				(1'b1), 
		.out				(spare2_buf_16x_unused));
	cl_u1_nor2_16x spare2_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare2_nor2_16x_unused));
	cl_u1_inv_32x spare2_inv_32x(
		.in				(1'b1), 
		.out				(spare2_inv_32x_unused));
	cl_sc1_msff_8x spare3_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_3), 
		.so				(so_3), 
		.d				(1'b0), 
		.q				(spare3_flop_unused));
	cl_u1_buf_32x spare3_buf_32x(
		.in				(1'b1), 
		.out				(spare3_buf_32x_unused));
	cl_u1_nand3_8x spare3_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare3_nand3_8x_unused));
	cl_u1_inv_8x spare3_inv_8x(
		.in				(1'b1), 
		.out				(spare3_inv_8x_unused));
	cl_u1_aoi22_4x spare3_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare3_aoi22_4x_unused));
	cl_u1_buf_8x spare3_buf_8x(
		.in				(1'b1), 
		.out				(spare3_buf_8x_unused));
	cl_u1_oai22_4x spare3_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare3_oai22_4x_unused));
	cl_u1_inv_16x spare3_inv_16x(
		.in				(1'b1), 
		.out				(spare3_inv_16x_unused));
	cl_u1_nand2_16x spare3_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare3_nand2_16x_unused));
	cl_u1_nor3_4x spare3_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare3_nor3_4x_unused));
	cl_u1_nand2_8x spare3_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare3_nand2_8x_unused));
	cl_u1_buf_16x spare3_buf_16x(
		.in				(1'b1), 
		.out				(spare3_buf_16x_unused));
	cl_u1_nor2_16x spare3_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare3_nor2_16x_unused));
	cl_u1_inv_32x spare3_inv_32x(
		.in				(1'b1), 
		.out				(spare3_inv_32x_unused));
	cl_sc1_msff_8x spare4_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_4), 
		.so				(so_4), 
		.d				(1'b0), 
		.q				(spare4_flop_unused));
	cl_u1_buf_32x spare4_buf_32x(
		.in				(1'b1), 
		.out				(spare4_buf_32x_unused));
	cl_u1_nand3_8x spare4_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare4_nand3_8x_unused));
	cl_u1_inv_8x spare4_inv_8x(
		.in				(1'b1), 
		.out				(spare4_inv_8x_unused));
	cl_u1_aoi22_4x spare4_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare4_aoi22_4x_unused));
	cl_u1_buf_8x spare4_buf_8x(
		.in				(1'b1), 
		.out				(spare4_buf_8x_unused));
	cl_u1_oai22_4x spare4_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare4_oai22_4x_unused));
	cl_u1_inv_16x spare4_inv_16x(
		.in				(1'b1), 
		.out				(spare4_inv_16x_unused));
	cl_u1_nand2_16x spare4_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare4_nand2_16x_unused));
	cl_u1_nor3_4x spare4_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare4_nor3_4x_unused));
	cl_u1_nand2_8x spare4_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare4_nand2_8x_unused));
	cl_u1_buf_16x spare4_buf_16x(
		.in				(1'b1), 
		.out				(spare4_buf_16x_unused));
	cl_u1_nor2_16x spare4_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare4_nor2_16x_unused));
	cl_u1_inv_32x spare4_inv_32x(
		.in				(1'b1), 
		.out				(spare4_inv_32x_unused));
	cl_sc1_msff_8x spare5_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_5), 
		.so				(so_5), 
		.d				(1'b0), 
		.q				(spare5_flop_unused));
	cl_u1_buf_32x spare5_buf_32x(
		.in				(1'b1), 
		.out				(spare5_buf_32x_unused));
	cl_u1_nand3_8x spare5_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare5_nand3_8x_unused));
	cl_u1_inv_8x spare5_inv_8x(
		.in				(1'b1), 
		.out				(spare5_inv_8x_unused));
	cl_u1_aoi22_4x spare5_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare5_aoi22_4x_unused));
	cl_u1_buf_8x spare5_buf_8x(
		.in				(1'b1), 
		.out				(spare5_buf_8x_unused));
	cl_u1_oai22_4x spare5_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare5_oai22_4x_unused));
	cl_u1_inv_16x spare5_inv_16x(
		.in				(1'b1), 
		.out				(spare5_inv_16x_unused));
	cl_u1_nand2_16x spare5_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare5_nand2_16x_unused));
	cl_u1_nor3_4x spare5_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare5_nor3_4x_unused));
	cl_u1_nand2_8x spare5_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare5_nand2_8x_unused));
	cl_u1_buf_16x spare5_buf_16x(
		.in				(1'b1), 
		.out				(spare5_buf_16x_unused));
	cl_u1_nor2_16x spare5_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare5_nor2_16x_unused));
	cl_u1_inv_32x spare5_inv_32x(
		.in				(1'b1), 
		.out				(spare5_inv_32x_unused));
	cl_sc1_msff_8x spare6_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_6), 
		.so				(so_6), 
		.d				(1'b0), 
		.q				(spare6_flop_unused));
	cl_u1_buf_32x spare6_buf_32x(
		.in				(1'b1), 
		.out				(spare6_buf_32x_unused));
	cl_u1_nand3_8x spare6_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare6_nand3_8x_unused));
	cl_u1_inv_8x spare6_inv_8x(
		.in				(1'b1), 
		.out				(spare6_inv_8x_unused));
	cl_u1_aoi22_4x spare6_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare6_aoi22_4x_unused));
	cl_u1_buf_8x spare6_buf_8x(
		.in				(1'b1), 
		.out				(spare6_buf_8x_unused));
	cl_u1_oai22_4x spare6_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare6_oai22_4x_unused));
	cl_u1_inv_16x spare6_inv_16x(
		.in				(1'b1), 
		.out				(spare6_inv_16x_unused));
	cl_u1_nand2_16x spare6_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare6_nand2_16x_unused));
	cl_u1_nor3_4x spare6_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare6_nor3_4x_unused));
	cl_u1_nand2_8x spare6_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare6_nand2_8x_unused));
	cl_u1_buf_16x spare6_buf_16x(
		.in				(1'b1), 
		.out				(spare6_buf_16x_unused));
	cl_u1_nor2_16x spare6_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare6_nor2_16x_unused));
	cl_u1_inv_32x spare6_inv_32x(
		.in				(1'b1), 
		.out				(spare6_inv_32x_unused));
	cl_sc1_msff_8x spare7_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_7), 
		.so				(so_7), 
		.d				(1'b0), 
		.q				(spare7_flop_unused));
	cl_u1_buf_32x spare7_buf_32x(
		.in				(1'b1), 
		.out				(spare7_buf_32x_unused));
	cl_u1_nand3_8x spare7_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare7_nand3_8x_unused));
	cl_u1_inv_8x spare7_inv_8x(
		.in				(1'b1), 
		.out				(spare7_inv_8x_unused));
	cl_u1_aoi22_4x spare7_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare7_aoi22_4x_unused));
	cl_u1_buf_8x spare7_buf_8x(
		.in				(1'b1), 
		.out				(spare7_buf_8x_unused));
	cl_u1_oai22_4x spare7_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare7_oai22_4x_unused));
	cl_u1_inv_16x spare7_inv_16x(
		.in				(1'b1), 
		.out				(spare7_inv_16x_unused));
	cl_u1_nand2_16x spare7_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare7_nand2_16x_unused));
	cl_u1_nor3_4x spare7_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare7_nor3_4x_unused));
	cl_u1_nand2_8x spare7_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare7_nand2_8x_unused));
	cl_u1_buf_16x spare7_buf_16x(
		.in				(1'b1), 
		.out				(spare7_buf_16x_unused));
	cl_u1_nor2_16x spare7_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare7_nor2_16x_unused));
	cl_u1_inv_32x spare7_inv_32x(
		.in				(1'b1), 
		.out				(spare7_inv_32x_unused));
	cl_sc1_msff_8x spare8_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_8), 
		.so				(so_8), 
		.d				(1'b0), 
		.q				(spare8_flop_unused));
	cl_u1_buf_32x spare8_buf_32x(
		.in				(1'b1), 
		.out				(spare8_buf_32x_unused));
	cl_u1_nand3_8x spare8_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare8_nand3_8x_unused));
	cl_u1_inv_8x spare8_inv_8x(
		.in				(1'b1), 
		.out				(spare8_inv_8x_unused));
	cl_u1_aoi22_4x spare8_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare8_aoi22_4x_unused));
	cl_u1_buf_8x spare8_buf_8x(
		.in				(1'b1), 
		.out				(spare8_buf_8x_unused));
	cl_u1_oai22_4x spare8_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare8_oai22_4x_unused));
	cl_u1_inv_16x spare8_inv_16x(
		.in				(1'b1), 
		.out				(spare8_inv_16x_unused));
	cl_u1_nand2_16x spare8_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare8_nand2_16x_unused));
	cl_u1_nor3_4x spare8_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare8_nor3_4x_unused));
	cl_u1_nand2_8x spare8_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare8_nand2_8x_unused));
	cl_u1_buf_16x spare8_buf_16x(
		.in				(1'b1), 
		.out				(spare8_buf_16x_unused));
	cl_u1_nor2_16x spare8_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare8_nor2_16x_unused));
	cl_u1_inv_32x spare8_inv_32x(
		.in				(1'b1), 
		.out				(spare8_inv_32x_unused));
	cl_sc1_msff_8x spare9_flop(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.si				(si_9), 
		.so				(so_9), 
		.d				(1'b0), 
		.q				(spare9_flop_unused));
	cl_u1_buf_32x spare9_buf_32x(
		.in				(1'b1), 
		.out				(spare9_buf_32x_unused));
	cl_u1_nand3_8x spare9_nand3_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.in2				(1'b1), 
		.out				(spare9_nand3_8x_unused));
	cl_u1_inv_8x spare9_inv_8x(
		.in				(1'b1), 
		.out				(spare9_inv_8x_unused));
	cl_u1_aoi22_4x spare9_aoi22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare9_aoi22_4x_unused));
	cl_u1_buf_8x spare9_buf_8x(
		.in				(1'b1), 
		.out				(spare9_buf_8x_unused));
	cl_u1_oai22_4x spare9_oai22_4x(
		.in00				(1'b1), 
		.in01				(1'b1), 
		.in10				(1'b1), 
		.in11				(1'b1), 
		.out				(spare9_oai22_4x_unused));
	cl_u1_inv_16x spare9_inv_16x(
		.in				(1'b1), 
		.out				(spare9_inv_16x_unused));
	cl_u1_nand2_16x spare9_nand2_16x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare9_nand2_16x_unused));
	cl_u1_nor3_4x spare9_nor3_4x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.in2				(1'b0), 
		.out				(spare9_nor3_4x_unused));
	cl_u1_nand2_8x spare9_nand2_8x(
		.in0				(1'b1), 
		.in1				(1'b1), 
		.out				(spare9_nand2_8x_unused));
	cl_u1_buf_16x spare9_buf_16x(
		.in				(1'b1), 
		.out				(spare9_buf_16x_unused));
	cl_u1_nor2_16x spare9_nor2_16x(
		.in0				(1'b0), 
		.in1				(1'b0), 
		.out				(spare9_nor2_16x_unused));
	cl_u1_inv_32x spare9_inv_32x(
		.in				(1'b1), 
		.out				(spare9_inv_32x_unused));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_16x__stack_none__width_4(din, dout);

	input	[3:0]		din;
	output	[3:0]		dout;

	buff #(4) d0_0(
		.in				(din[3:0]), 
		.out				(dout[3:0]));
endmodule
`endcelldefine

`celldefine
module msff_macro__dmsff_16x__stack_10c__width_10(din, clk, en, se, scan_in, 
	siclk, soclk, pce_ov, stop, dout, scan_out);

	input	[9:0]		din;
	input			clk;
	input			en;
	input			se;
	input			scan_in;
	input			siclk;
	input			soclk;
	input			pce_ov;
	input			stop;
	output	[9:0]		dout;
	output			scan_out;

	wire			l1clk;
	wire			siclk_out;
	wire			soclk_out;
	wire	[8:0]		so;

	cl_dp1_l1hdr_8x c0_0(
		.l2clk				(clk), 
		.pce				(en), 
		.aclk				(siclk), 
		.bclk				(soclk), 
		.l1clk				(l1clk), 
		.se				(se), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_out			(siclk_out), 
		.soclk_out			(soclk_out));
	dff #(10) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk_out), 
		.soclk				(soclk_out), 
		.d				(din[9:0]), 
		.si				({scan_in, so[8:0]}), 
		.so				({so[8:0], scan_out}), 
		.q				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_1x__ports_2__stack_10c__width_9(din0, din1, dout);

	input	[8:0]		din0;
	input	[8:0]		din1;
	output	[8:0]		dout;

	nand2 #(9) d0_0(
		.in0				(din0[8:0]), 
		.in1				(din1[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module inv_macro__dinv_24x__stack_10c__width_10(din, dout);

	input	[9:0]		din;
	output	[9:0]		dout;

	inv #(10) d0_0(
		.in				(din[9:0]), 
		.out				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_32x__minbuff_1__stack_none__width_19(din, dout);

	input	[18:0]		din;
	output	[18:0]		dout;

	buff #(19) d0_0(
		.in				(din[18:0]), 
		.out				(dout[18:0]));
endmodule
`endcelldefine

`celldefine
module msff_macro__stack_10c__width_10(din, clk, en, se, scan_in, siclk, soclk, 
	pce_ov, stop, dout, scan_out);

	input	[9:0]		din;
	input			clk;
	input			en;
	input			se;
	input			scan_in;
	input			siclk;
	input			soclk;
	input			pce_ov;
	input			stop;
	output	[9:0]		dout;
	output			scan_out;

	wire			l1clk;
	wire			siclk_out;
	wire			soclk_out;
	wire	[8:0]		so;

	cl_dp1_l1hdr_8x c0_0(
		.l2clk				(clk), 
		.pce				(en), 
		.aclk				(siclk), 
		.bclk				(soclk), 
		.l1clk				(l1clk), 
		.se				(se), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_out			(siclk_out), 
		.soclk_out			(soclk_out));
	dff #(10) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk_out), 
		.soclk				(soclk_out), 
		.d				(din[9:0]), 
		.si				({scan_in, so[8:0]}), 
		.so				({so[8:0], scan_out}), 
		.q				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module mux_macro__dbuff_8x__dmux_4x__mux_aope__ports_2__stack_10c__width_10(
	din0, din1, sel0, dout);

	input	[9:0]		din0;
	input	[9:0]		din1;
	input			sel0;
	output	[9:0]		dout;

	wire			psel0;
	wire			psel1;

	cl_dp1_penc2_8x c0_0(
		.sel0				(sel0), 
		.psel0				(psel0), 
		.psel1				(psel1));
	mux2s #(10) d0_0(
		.sel0				(psel0), 
		.sel1				(psel1), 
		.in0				(din0[9:0]), 
		.in1				(din1[9:0]), 
		.dout				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module mux_macro__dbuff_8x__dmux_4x__mux_aodec__ports_8__stack_10c__width_10(
	din0, din1, din2, din3, din4, din5, din6, din7, sel, dout);

	input	[9:0]		din0;
	input	[9:0]		din1;
	input	[9:0]		din2;
	input	[9:0]		din3;
	input	[9:0]		din4;
	input	[9:0]		din5;
	input	[9:0]		din6;
	input	[9:0]		din7;
	input	[2:0]		sel;
	output	[9:0]		dout;

	wire			psel0;
	wire			psel1;
	wire			psel2;
	wire			psel3;
	wire			psel4;
	wire			psel5;
	wire			psel6;
	wire			psel7;

	cl_dp1_pdec8_8x c0_0(
		.test				(1'b1), 
		.sel0				(sel[0]), 
		.sel1				(sel[1]), 
		.sel2				(sel[2]), 
		.psel0				(psel0), 
		.psel1				(psel1), 
		.psel2				(psel2), 
		.psel3				(psel3), 
		.psel4				(psel4), 
		.psel5				(psel5), 
		.psel6				(psel6), 
		.psel7				(psel7));
	mux8s #(10) d0_0(
		.sel0				(psel0), 
		.sel1				(psel1), 
		.sel2				(psel2), 
		.sel3				(psel3), 
		.sel4				(psel4), 
		.sel5				(psel5), 
		.sel6				(psel6), 
		.sel7				(psel7), 
		.in0				(din0[9:0]), 
		.in1				(din1[9:0]), 
		.in2				(din2[9:0]), 
		.in3				(din3[9:0]), 
		.in4				(din4[9:0]), 
		.in5				(din5[9:0]), 
		.in6				(din6[9:0]), 
		.in7				(din7[9:0]), 
		.dout				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module mux_macro__dmux_1x__mux_aodec__ports_4__stack_10c__width_10(din0, din1, 
	din2, din3, sel, dout);

	input	[9:0]		din0;
	input	[9:0]		din1;
	input	[9:0]		din2;
	input	[9:0]		din3;
	input	[1:0]		sel;
	output	[9:0]		dout;

	wire			psel0;
	wire			psel1;
	wire			psel2;
	wire			psel3;

	cl_dp1_pdec4_8x c0_0(
		.test				(1'b1), 
		.sel0				(sel[0]), 
		.sel1				(sel[1]), 
		.psel0				(psel0), 
		.psel1				(psel1), 
		.psel2				(psel2), 
		.psel3				(psel3));
	mux4s #(10) d0_0(
		.sel0				(psel0), 
		.sel1				(psel1), 
		.sel2				(psel2), 
		.sel3				(psel3), 
		.in0				(din0[9:0]), 
		.in1				(din1[9:0]), 
		.in2				(din2[9:0]), 
		.in3				(din3[9:0]), 
		.dout				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module mux_macro__dmux_1x__mux_aonpe__ports_2__stack_10c__width_10(din0, sel0, 
	din1, sel1, dout);

	input	[9:0]		din0;
	input			sel0;
	input	[9:0]		din1;
	input			sel1;
	output	[9:0]		dout;

	wire			buffout0;
	wire			buffout1;

	cl_dp1_muxbuff2_8x c0_0(
		.in0				(sel0), 
		.in1				(sel1), 
		.out0				(buffout0), 
		.out1				(buffout1));
	mux2s #(10) d0_0(
		.sel0				(buffout0), 
		.sel1				(buffout1), 
		.in0				(din0[9:0]), 
		.in1				(din1[9:0]), 
		.dout				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_8x__stack_10c__width_1(din, dout);

	input	[0:0]		din;
	output	[0:0]		dout;

	buff #(1) d0_0(
		.in				(din[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_4x__ports_3__stack_10c__width_10(din0, din1, din2, dout
	);

	input	[9:0]		din0;
	input	[9:0]		din1;
	input	[9:0]		din2;
	output	[9:0]		dout;

	nand3 #(10) d0_0(
		.in0				(din0[9:0]), 
		.in1				(din1[9:0]), 
		.in2				(din2[9:0]), 
		.out				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_4x__ports_2__stack_10c__width_10(din0, din1, dout);

	input	[9:0]		din0;
	input	[9:0]		din1;
	output	[9:0]		dout;

	nand2 #(10) d0_0(
		.in0				(din0[9:0]), 
		.in1				(din1[9:0]), 
		.out				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_12x__ports_2__stack_10c__width_10(din0, din1, dout);

	input	[9:0]		din0;
	input	[9:0]		din1;
	output	[9:0]		dout;

	nand2 #(10) d0_0(
		.in0				(din0[9:0]), 
		.in1				(din1[9:0]), 
		.out				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module inv_macro__dinv_2x__stack_10c__width_9(din, dout);

	input	[8:0]		din;
	output	[8:0]		dout;

	inv #(9) d0_0(
		.in				(din[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module mux_macro__dmux_8x__mux_aope__ports_2__stack_10c__width_9(din0, din1, 
	sel0, dout);

	input	[8:0]		din0;
	input	[8:0]		din1;
	input			sel0;
	output	[8:0]		dout;

	wire			psel0;
	wire			psel1;

	cl_dp1_penc2_8x c0_0(
		.sel0				(sel0), 
		.psel0				(psel0), 
		.psel1				(psel1));
	mux2s #(9) d0_0(
		.sel0				(psel0), 
		.sel1				(psel1), 
		.in0				(din0[8:0]), 
		.in1				(din1[8:0]), 
		.dout				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_4x__ports_3__stack_10c__width_1(din0, din1, din2, dout)
	;

	input	[0:0]		din0;
	input	[0:0]		din1;
	input	[0:0]		din2;
	output	[0:0]		dout;

	nand3 #(1) d0_0(
		.in0				(din0[0]), 
		.in1				(din1[0]), 
		.in2				(din2[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_12x__ports_2__stack_10c__width_1(din0, din1, dout);

	input	[0:0]		din0;
	input	[0:0]		din1;
	output	[0:0]		dout;

	nand2 #(1) d0_0(
		.in0				(din0[0]), 
		.in1				(din1[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`celldefine
module inv_macro__dinv_4x__stack_10c__width_1(din, dout);

	input	[0:0]		din;
	output	[0:0]		dout;

	inv #(1) d0_0(
		.in				(din[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`celldefine
module inv_macro__dinv_12x__stack_10c__width_9(din, dout);

	input	[8:0]		din;
	output	[8:0]		dout;

	inv #(9) d0_0(
		.in				(din[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module and_macro__dinv_12x__dnand_4x__ports_4__stack_10c__width_2(din0, din1, 
	din2, din3, dout);

	input	[1:0]		din0;
	input	[1:0]		din1;
	input	[1:0]		din2;
	input	[1:0]		din3;
	output	[1:0]		dout;

	and4 #(2) d0_0(
		.in0				(din0[1:0]), 
		.in1				(din1[1:0]), 
		.in2				(din2[1:0]), 
		.in3				(din3[1:0]), 
		.out				(dout[1:0]));
endmodule
`endcelldefine

`celldefine
module and_macro__dinv_8x__dnand_2x__ports_3__stack_10c__width_4(din0, din1, 
	din2, dout);

	input	[3:0]		din0;
	input	[3:0]		din1;
	input	[3:0]		din2;
	output	[3:0]		dout;

	and3 #(4) d0_0(
		.in0				(din0[3:0]), 
		.in1				(din1[3:0]), 
		.in2				(din2[3:0]), 
		.out				(dout[3:0]));
endmodule
`endcelldefine

`celldefine
module nor_macro__dnor_8x__ports_2__stack_10c__width_3(din0, din1, dout);

	input	[2:0]		din0;
	input	[2:0]		din1;
	output	[2:0]		dout;

	nor2 #(3) d0_0(
		.in0				(din0[2:0]), 
		.in1				(din1[2:0]), 
		.out				(dout[2:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_2x__ports_2__stack_10c__width_5(din0, din1, dout);

	input	[4:0]		din0;
	input	[4:0]		din1;
	output	[4:0]		dout;

	nand2 #(5) d0_0(
		.in0				(din0[4:0]), 
		.in1				(din1[4:0]), 
		.out				(dout[4:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_8x__ports_2__stack_10c__width_1(din0, din1, dout);

	input	[0:0]		din0;
	input	[0:0]		din1;
	output	[0:0]		dout;

	nand2 #(1) d0_0(
		.in0				(din0[0]), 
		.in1				(din1[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`celldefine
module inv_macro__dinv_4x__stack_10c__width_5(din, dout);

	input	[4:0]		din;
	output	[4:0]		dout;

	inv #(5) d0_0(
		.in				(din[4:0]), 
		.out				(dout[4:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_8x__ports_3__stack_10c__width_8(din0, din1, din2, dout)
	;

	input	[7:0]		din0;
	input	[7:0]		din1;
	input	[7:0]		din2;
	output	[7:0]		dout;

	nand3 #(8) d0_0(
		.in0				(din0[7:0]), 
		.in1				(din1[7:0]), 
		.in2				(din2[7:0]), 
		.out				(dout[7:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_32x__ports_2__stack_10c__width_9(din0, din1, dout);

	input	[8:0]		din0;
	input	[8:0]		din1;
	output	[8:0]		dout;

	nand2 #(9) d0_0(
		.in0				(din0[8:0]), 
		.in1				(din1[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_48x__stack_10c__width_9(din, dout);

	input	[8:0]		din;
	output	[8:0]		dout;

	buff #(9) d0_0(
		.in				(din[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_32x__stack_10c__width_9(din, dout);

	input	[8:0]		din;
	output	[8:0]		dout;

	buff #(9) d0_0(
		.in				(din[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_16x__minbuff_1__stack_10c__width_9(din, dout);

	input	[8:0]		din;
	output	[8:0]		dout;

	buff #(9) d0_0(
		.in				(din[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module inv_macro__dinv_8x__stack_10c__width_9(din, dout);

	input	[8:0]		din;
	output	[8:0]		dout;

	inv #(9) d0_0(
		.in				(din[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_1x__ports_3__stack_10c__width_9(din0, din1, din2, dout)
	;

	input	[8:0]		din0;
	input	[8:0]		din1;
	input	[8:0]		din2;
	output	[8:0]		dout;

	nand3 #(9) d0_0(
		.in0				(din0[8:0]), 
		.in1				(din1[8:0]), 
		.in2				(din2[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_1x__ports_2__stack_10c__width_10(din0, din1, dout);

	input	[9:0]		din0;
	input	[9:0]		din1;
	output	[9:0]		dout;

	nand2 #(10) d0_0(
		.in0				(din0[9:0]), 
		.in1				(din1[9:0]), 
		.out				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module msff_macro__dmsff_8x__stack_10c__stack_10c__width_10(din, clk, en, se, 
	scan_in, siclk, soclk, pce_ov, stop, dout, scan_out);

	input	[9:0]		din;
	input			clk;
	input			en;
	input			se;
	input			scan_in;
	input			siclk;
	input			soclk;
	input			pce_ov;
	input			stop;
	output	[9:0]		dout;
	output			scan_out;

	wire			l1clk;
	wire			siclk_out;
	wire			soclk_out;
	wire	[8:0]		so;

	cl_dp1_l1hdr_8x c0_0(
		.l2clk				(clk), 
		.pce				(en), 
		.aclk				(siclk), 
		.bclk				(soclk), 
		.l1clk				(l1clk), 
		.se				(se), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_out			(siclk_out), 
		.soclk_out			(soclk_out));
	dff #(10) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk_out), 
		.soclk				(soclk_out), 
		.d				(din[9:0]), 
		.si				({scan_in, so[8:0]}), 
		.so				({so[8:0], scan_out}), 
		.q				(dout[9:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_2x__ports_2__stack_10c__width_9(din0, din1, dout);

	input	[8:0]		din0;
	input	[8:0]		din1;
	output	[8:0]		dout;

	nand2 #(9) d0_0(
		.in0				(din0[8:0]), 
		.in1				(din1[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_4x__ports_3__stack_10c__width_9(din0, din1, din2, dout)
	;

	input	[8:0]		din0;
	input	[8:0]		din1;
	input	[8:0]		din2;
	output	[8:0]		dout;

	nand3 #(9) d0_0(
		.in0				(din0[8:0]), 
		.in1				(din1[8:0]), 
		.in2				(din2[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_8x__ports_2__stack_10c__width_9(din0, din1, dout);

	input	[8:0]		din0;
	input	[8:0]		din1;
	output	[8:0]		dout;

	nand2 #(9) d0_0(
		.in0				(din0[8:0]), 
		.in1				(din1[8:0]), 
		.out				(dout[8:0]));
endmodule
`endcelldefine

`celldefine
module nor_macro__dnor_4x__ports_3__stack_10c__width_6(din0, din1, din2, dout);

	input	[5:0]		din0;
	input	[5:0]		din1;
	input	[5:0]		din2;
	output	[5:0]		dout;

	nor3 #(6) d0_0(
		.in0				(din0[5:0]), 
		.in1				(din1[5:0]), 
		.in2				(din2[5:0]), 
		.out				(dout[5:0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_8x__ports_3__stack_10c__width_2(din0, din1, din2, dout)
	;

	input	[1:0]		din0;
	input	[1:0]		din1;
	input	[1:0]		din2;
	output	[1:0]		dout;

	nand3 #(2) d0_0(
		.in0				(din0[1:0]), 
		.in1				(din1[1:0]), 
		.in2				(din2[1:0]), 
		.out				(dout[1:0]));
endmodule
`endcelldefine

`celldefine
module inv_macro__dinv_32x__stack_10c__width_1(din, dout);

	input	[0:0]		din;
	output	[0:0]		dout;

	inv #(1) d0_0(
		.in				(din[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`celldefine
module nand_macro__dnand_1x__ports_3__stack_10c__width_3(din0, din1, din2, dout)
	;

	input	[2:0]		din0;
	input	[2:0]		din1;
	input	[2:0]		din2;
	output	[2:0]		dout;

	nand3 #(3) d0_0(
		.in0				(din0[2:0]), 
		.in1				(din1[2:0]), 
		.in2				(din2[2:0]), 
		.out				(dout[2:0]));
endmodule
`endcelldefine

`celldefine
module nor_macro__dnor_4x__ports_3__stack_10c__width_1(din0, din1, din2, dout);

	input	[0:0]		din0;
	input	[0:0]		din1;
	input	[0:0]		din2;
	output	[0:0]		dout;

	nor3 #(1) d0_0(
		.in0				(din0[0]), 
		.in1				(din1[0]), 
		.in2				(din2[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`celldefine
module mux2s(dout, in0, in1, sel0, sel1);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	dout;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;
	input			sel0;
	input			sel1;

	assign dout = ((in0 & {SIZE {sel0}}) | (in1 & {SIZE {sel1}}));
endmodule
`endcelldefine

`celldefine
module mux4s(dout, in0, in1, in2, in3, sel0, sel1, sel2, sel3);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	dout;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;
	input	[(SIZE - 1):0]	in2;
	input	[(SIZE - 1):0]	in3;
	input			sel0;
	input			sel1;
	input			sel2;
	input			sel3;

	assign dout = ((((in0 & {SIZE {sel0}}) | (in1 & {SIZE {sel1}})) | (in2 &
		{SIZE {sel2}})) | (in3 & {SIZE {sel3}}));
endmodule
`endcelldefine

`celldefine
module mux8s(dout, in0, in1, in2, in3, in4, in5, in6, in7, sel0, sel1, sel2, 
	sel3, sel4, sel5, sel6, sel7);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	dout;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;
	input	[(SIZE - 1):0]	in2;
	input	[(SIZE - 1):0]	in3;
	input	[(SIZE - 1):0]	in4;
	input	[(SIZE - 1):0]	in5;
	input	[(SIZE - 1):0]	in6;
	input	[(SIZE - 1):0]	in7;
	input			sel0;
	input			sel1;
	input			sel2;
	input			sel3;
	input			sel4;
	input			sel5;
	input			sel6;
	input			sel7;

	assign dout = ((((((((in0 & {SIZE {sel0}}) | (in1 & {SIZE {sel1}})) | (
		in2 & {SIZE {sel2}})) | (in3 & {SIZE {sel3}})) | (in4 & {SIZE {
		sel4}})) | (in5 & {SIZE {sel5}})) | (in6 & {SIZE {sel6}})) | (
		in7 & {SIZE {sel7}}));
endmodule
`endcelldefine

`celldefine
module dff(q, so, d, l1clk, si, siclk, soclk);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	q;
	output	[(SIZE - 1):0]	so;
	input	[(SIZE - 1):0]	d;
	input			l1clk;
	input	[(SIZE - 1):0]	si;
	input			siclk;
	input			soclk;

	reg	[(SIZE - 1):0]	q;
	reg	[(SIZE - 1):0]	l1;

	assign so[(SIZE - 1):0] = q[(SIZE - 1):0];

	always @(posedge l1clk or posedge siclk) begin
	  if (siclk) begin
	    q[(SIZE - 1):0] <= {SIZE {1'b0}};
	  end
	  else
	    begin
	      q[(SIZE - 1):0] <= d[(SIZE - 1):0];
	    end
	end
endmodule
`endcelldefine

`celldefine
module and3(out, in0, in1, in2);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	out;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;
	input	[(SIZE - 1):0]	in2;

	assign out[(SIZE - 1):0] = ((in0[(SIZE - 1):0] & in1[(SIZE - 1):0]) & 
		in2[(SIZE - 1):0]);
endmodule
`endcelldefine

`celldefine
module and4(out, in0, in1, in2, in3);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	out;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;
	input	[(SIZE - 1):0]	in2;
	input	[(SIZE - 1):0]	in3;

	assign out[(SIZE - 1):0] = (((in0[(SIZE - 1):0] & in1[(SIZE - 1):0]) & 
		in2[(SIZE - 1):0]) & in3[(SIZE - 1):0]);
endmodule
`endcelldefine

`celldefine
module nand2(out, in0, in1);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	out;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;

	assign out[(SIZE - 1):0] = (~(in0[(SIZE - 1):0] & in1[(SIZE - 1):0]));
endmodule
`endcelldefine

`celldefine
module nand3(out, in0, in1, in2);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	out;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;
	input	[(SIZE - 1):0]	in2;

	assign out[(SIZE - 1):0] = (~((in0[(SIZE - 1):0] & in1[(SIZE - 1):0]) & 
		in2[(SIZE - 1):0]));
endmodule
`endcelldefine

`celldefine
module nor2(out, in0, in1);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	out;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;

	assign out[(SIZE - 1):0] = (~(in0[(SIZE - 1):0] | in1[(SIZE - 1):0]));
endmodule
`endcelldefine

`celldefine
module nor3(out, in0, in1, in2);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	out;
	input	[(SIZE - 1):0]	in0;
	input	[(SIZE - 1):0]	in1;
	input	[(SIZE - 1):0]	in2;

	assign out[(SIZE - 1):0] = (~((in0[(SIZE - 1):0] | in1[(SIZE - 1):0]) | 
		in2[(SIZE - 1):0]));
endmodule
`endcelldefine

`celldefine
module buff(out, in);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	out;
	input	[(SIZE - 1):0]	in;

	assign out[(SIZE - 1):0] = in[(SIZE - 1):0];
endmodule
`endcelldefine

`celldefine
module inv(out, in);

	parameter		SIZE		= 1;

	output	[(SIZE - 1):0]	out;
	input	[(SIZE - 1):0]	in;

	assign out[(SIZE - 1):0] = (~in[(SIZE - 1):0]);
endmodule
`endcelldefine

`celldefine
module cl_dp1_l1hdr_8x(l1clk, l2clk, se, pce, pce_ov, stop, aclk, bclk, 
	siclk_out, soclk_out);

	output			l1clk;
	input			l2clk;
	input			se;
	input			pce;
	input			pce_ov;
	input			stop;
	input			aclk;
	input			bclk;
	output			siclk_out;
	output			soclk_out;

	reg			l1en;

	assign l1clk = ((l2clk & l1en) || se);
	assign siclk_out = aclk;
	assign soclk_out = bclk;

	always @(l2clk or stop or pce or pce_ov) begin
	  if (~l2clk) begin
	    l1en <= ((~stop) & (pce | pce_ov));
	  end
	end
endmodule
`endcelldefine

`celldefine
module cl_dp1_muxbuff2_8x(in0, in1, out0, out1);

	input			in0;
	input			in1;
	output			out0;
	output			out1;

	buf (out1, in1);
	buf (out0, in0);
endmodule
`endcelldefine

`celldefine
module cl_dp1_pdec4_8x(sel0, sel1, test, psel0, psel1, psel2, psel3);

	input			sel0;
	input			sel1;
	input			test;
	output			psel0;
	output			psel1;
	output			psel2;
	output			psel3;

	assign psel0 = ((~sel1) & (~sel0));
	assign psel1 = ((~sel1) & sel0);
	assign psel2 = (sel1 & (~sel0));
	assign psel3 = ((sel1 & sel0) & test);
endmodule
`endcelldefine

`celldefine
module cl_dp1_pdec8_8x(sel0, sel1, sel2, test, psel0, psel1, psel2, psel3, 
	psel4, psel5, psel6, psel7);

	input			sel0;
	input			sel1;
	input			sel2;
	input			test;
	output			psel0;
	output			psel1;
	output			psel2;
	output			psel3;
	output			psel4;
	output			psel5;
	output			psel6;
	output			psel7;

	assign psel0 = ((((~sel2) & (~sel1)) & (~sel0)) & test);
	assign psel1 = (((~sel2) & (~sel1)) & sel0);
	assign psel2 = (((~sel2) & sel1) & (~sel0));
	assign psel3 = (((~sel2) & sel1) & sel0);
	assign psel4 = ((sel2 & (~sel1)) & (~sel0));
	assign psel5 = ((sel2 & (~sel1)) & sel0);
	assign psel6 = ((sel2 & sel1) & (~sel0));
	assign psel7 = ((sel2 & sel1) & sel0);
endmodule
`endcelldefine

`celldefine
module cl_dp1_penc2_8x(sel0, psel0, psel1);

	input			sel0;
	output			psel0;
	output			psel1;

	assign psel0 = sel0;
	assign psel1 = (~sel0);
endmodule
`endcelldefine

`celldefine
module cl_u1_aoi22_4x(out, in10, in11, in00, in01);

	output			out;
	input			in10;
	input			in11;
	input			in00;
	input			in01;

	assign out = (~((in10 & in11) | (in00 & in01)));
endmodule
`endcelldefine

`celldefine
module cl_u1_buf_16x(in, out);

	input			in;
	output			out;

	buf (out, in);
endmodule
`endcelldefine

`celldefine
module cl_u1_buf_32x(in, out);

	input			in;
	output			out;

	buf (out, in);
endmodule
`endcelldefine

`celldefine
module cl_u1_buf_8x(in, out);

	input			in;
	output			out;

	buf (out, in);
endmodule
`endcelldefine

`celldefine
module cl_u1_inv_16x(in, out);

	input			in;
	output			out;

	not (out, in);
endmodule
`endcelldefine

`celldefine
module cl_u1_inv_32x(in, out);

	input			in;
	output			out;

	not (out, in);
endmodule
`endcelldefine

`celldefine
module cl_u1_inv_8x(in, out);

	input			in;
	output			out;

	not (out, in);
endmodule
`endcelldefine

`celldefine
module cl_u1_nand2_16x(in0, in1, out);

	input			in0;
	input			in1;
	output			out;

	assign out = (~(in0 & in1));
endmodule
`endcelldefine

`celldefine
module cl_u1_nand2_8x(in0, in1, out);

	input			in0;
	input			in1;
	output			out;

	assign out = (~(in0 & in1));
endmodule
`endcelldefine

`celldefine
module cl_u1_nand3_8x(in0, in1, in2, out);

	input			in0;
	input			in1;
	input			in2;
	output			out;

	assign out = (~((in0 & in1) & in2));
endmodule
`endcelldefine

`celldefine
module cl_u1_nor2_16x(in0, in1, out);

	input			in0;
	input			in1;
	output			out;

	assign out = (~(in0 | in1));
endmodule
`endcelldefine

`celldefine
module cl_u1_nor3_4x(in0, in1, in2, out);

	input			in0;
	input			in1;
	input			in2;
	output			out;

	assign out = (~((in0 | in1) | in2));
endmodule
`endcelldefine

`celldefine
module cl_u1_oai22_4x(out, in10, in11, in00, in01);

	output			out;
	input			in10;
	input			in11;
	input			in00;
	input			in01;

	assign out = (~((in10 | in11) & (in00 | in01)));
endmodule
`endcelldefine

`celldefine
module cl_sc1_l1hdr_8x(l2clk, se, pce, pce_ov, stop, l1clk);

	input			l2clk;
	input			se;
	input			pce;
	input			pce_ov;
	input			stop;
	output			l1clk;

	reg			l1en;

	assign l1clk = ((l2clk & l1en) | se);

	always @(l2clk or stop or pce or pce_ov) begin
	  if (~l2clk) begin
	    l1en <= ((~stop) & (pce | pce_ov));
	  end
	end
endmodule
`endcelldefine

`celldefine
module cl_sc1_msff_8x(q, so, d, l1clk, si, siclk, soclk);

	parameter		SIZE		= 1;

	output			q;
	output			so;
	input			d;
	input			l1clk;
	input			si;
	input			siclk;
	input			soclk;

	reg			q;
	reg			l1;

	assign so = q;

	always @(posedge l1clk or posedge siclk) begin
	  if (siclk) begin
	    q <= 1'b0;
	  end
	  else
	    begin
	      q <= d;
	    end
	end
endmodule
`endcelldefine

`celldefine
module msff_ctl_macro__width_5(din, l1clk, scan_in, siclk, soclk, dout, scan_out
	);

	input	[4:0]		din;
	input			l1clk;
	input			scan_in;
	input			siclk;
	input			soclk;
	output	[4:0]		dout;
	output			scan_out;

	wire	[4:0]		fdin;
	wire	[3:0]		so;

	assign fdin[4:0] = din[4:0];

	dff #(5) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.d				(fdin[4:0]), 
		.si				({scan_in, so[3:0]}), 
		.so				({so[3:0], scan_out}), 
		.q				(dout[4:0]));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_32x__stack_none__width_1(din, dout);

	input	[0:0]		din;
	output	[0:0]		dout;

	buff #(1) d0_0(
		.in				(din[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_8x__stack_none__width_1(din, dout);

	input	[0:0]		din;
	output	[0:0]		dout;

	buff #(1) d0_0(
		.in				(din[0]), 
		.out				(dout[0]));
endmodule
`endcelldefine

`endif // `ifdef FPGA
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx_ard_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module ccx_ard_dp (
  arb_grant_a, 
  arb_src8_grant_a, 
  arb_src7_grant_a, 
  arb_src6_grant_a, 
  arb_src5_grant_a, 
  arb_src4_grant_a, 
  arb_src3_grant_a, 
  arb_src2_grant_a, 
  arb_src1_grant_a, 
  arb_src0_grant_a, 
  ccx_dest_data_rdy_a, 
  ccx_dest_atom_a, 
  req_pkt_empty_a, 
  grant_a, 
  req_a, 
  atom_a, 
  src8_arb_atom_q, 
  src7_arb_atom_q, 
  src6_arb_atom_q, 
  src5_arb_atom_q, 
  src4_arb_atom_q, 
  src3_arb_atom_q, 
  src2_arb_atom_q, 
  src1_arb_atom_q, 
  src0_arb_atom_q, 
  src8_arb_req_q, 
  src7_arb_req_q, 
  src6_arb_req_q, 
  src5_arb_req_q, 
  src4_arb_req_q, 
  src3_arb_req_q, 
  src2_arb_req_q, 
  src1_arb_req_q, 
  src0_arb_req_q, 
  qfullbar_a, 
  direction, 
  fifo_req_sel_a, 
  input_req_sel_a, 
  input_req_sel_a_, 
  write_fifo_a, 
  fifo_rptr_a, 
  fifo_read_select, 
  atom_x, 
  stall_q_d1, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out, 
  ccx_aclk_out, 
  ccx_bclk_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire [8:0] atom_q;
wire [8:0] req_q;
wire i_dff_atom_a_scanin;
wire i_dff_atom_a_scanout;
wire direction_;
wire dir_a_;
wire [8:0] atom_int_a;
wire i_dff_req_a_scanin;
wire i_dff_req_a_scanout;
wire dir_a;
wire [8:0] input_req_a_;
wire [8:0] input_req_a;
wire [9:0] fifo_wdata_prebuf;
wire [9:0] fifo_wdata;
wire i_dff_fmem17_scanin;
wire i_dff_fmem17_scanout;
wire [9:0] fifo_rdata17;
wire i_dff_fmem16_scanin;
wire i_dff_fmem16_scanout;
wire [9:0] fifo_rdata16;
wire [9:0] fifo_rdata17_16;
wire i_dff_fmem15_scanin;
wire i_dff_fmem15_scanout;
wire [9:0] fifo_rdata15;
wire i_dff_fmem14_scanin;
wire i_dff_fmem14_scanout;
wire [9:0] fifo_rdata14;
wire i_dff_fmem13_scanin;
wire i_dff_fmem13_scanout;
wire [9:0] fifo_rdata13;
wire i_dff_fmem12_scanin;
wire i_dff_fmem12_scanout;
wire [9:0] fifo_rdata12;
wire i_dff_fmem11_scanin;
wire i_dff_fmem11_scanout;
wire [9:0] fifo_rdata11;
wire i_dff_fmem10_scanin;
wire i_dff_fmem10_scanout;
wire [9:0] fifo_rdata10;
wire i_dff_fmem9_scanin;
wire i_dff_fmem9_scanout;
wire [9:0] fifo_rdata9;
wire i_dff_fmem8_scanin;
wire i_dff_fmem8_scanout;
wire [9:0] fifo_rdata8;
wire [9:0] fifo_rdata15_8;
wire i_dff_fmem7_scanin;
wire i_dff_fmem7_scanout;
wire [9:0] fifo_rdata7;
wire i_dff_fmem6_scanin;
wire i_dff_fmem6_scanout;
wire [9:0] fifo_rdata6;
wire i_dff_fmem5_scanin;
wire i_dff_fmem5_scanout;
wire [9:0] fifo_rdata5;
wire i_dff_fmem4_scanin;
wire i_dff_fmem4_scanout;
wire [9:0] fifo_rdata4;
wire i_dff_fmem3_scanin;
wire i_dff_fmem3_scanout;
wire [9:0] fifo_rdata3;
wire i_dff_fmem2_scanin;
wire i_dff_fmem2_scanout;
wire [9:0] fifo_rdata2;
wire i_dff_fmem1_scanin;
wire i_dff_fmem1_scanout;
wire [9:0] fifo_rdata1;
wire i_dff_fmem0_scanin;
wire i_dff_fmem0_scanout;
wire [9:0] fifo_rdata0;
wire [9:0] fifo_rdata7_0;
wire fifo_dir;
wire [8:0] fifo_req;
wire qual_dir;
wire [8:0] qual_req;
wire current_req_sel_a;
wire fq_dir;
wire [8:0] fq_req;
wire i_dff_reqreg_scanin;
wire i_dff_reqreg_scanout;
wire fq_dir_a_prebuf;
wire [8:0] fq_req_a;
wire fq_dir_a;
wire input_dir_a_;
wire [8:0] input_req_qfullbar_a_;
wire fq_input_dir_a_;
wire [8:0] fq_input_req_a_;
wire dir;
wire [8:0] req;
wire [8:0] atom_req_a_;
wire [8:0] atom_req_a;
wire [8:0] atom;
wire stall_a_;
wire input_dira_stall_;
wire fq_input_dira_stall_;
wire dira;
wire fq_dir_a_;
wire input_dird_stall_;
wire fq_input_dird_stall_;
wire dird;
wire r8_;
wire r7_;
wire r6_;
wire r5_;
wire r4_;
wire r3_;
wire r2_;
wire r1_;
wire r0_;
wire ra_or_7654_;
wire ra_or_3210_;
wire ra_or_654_;
wire ra_d54x;
wire ra_or_543_;
wire ra_or_210_;
wire ra_or_32_;
wire ra_or_21_;
wire ra_or_10_;
wire ra_d8_;
wire ra_d7_;
wire ra_d6_;
wire ra_d4_;
wire ra_d3_;
wire [8:0] grant_asc_;
wire ra_d8;
wire ra_d7;
wire ra_d6;
wire ra_d4;
wire ra_d3;
wire [8:0] reqd;
wire rd7_;
wire rd6_;
wire rd5_;
wire rd4_;
wire rd3_;
wire rd2_;
wire rd1_;
wire rd0_;
wire rd_or_7654_;
wire rd_or_3210_;
wire rd_or_654_;
wire rd_d54x;
wire rd_or_543_;
wire rd_or_210_;
wire rd_or_32_;
wire rd_or_21_;
wire rd_or_10_;
wire rd_d8_;
wire rd_d7_;
wire rd_d6_;
wire rd_d4_;
wire rd_d3_;
wire [8:0] grant_dsc_;
wire rd_d8;
wire rd_d7;
wire rd_d6;
wire rd_d4;
wire rd_d3;
wire [8:0] grant_des_;
wire [8:0] grant_int_a;
wire [8:0] grant_a_;
wire [8:0] qual_atomic_d1_;
wire [8:0] set_qual_atomic;
wire [8:0] qual_atomic_d1;
wire [8:0] hold_qual_atomic;
wire stall_q_d1_;
wire [8:0] qual_atomic;
wire i_dff_qual_atomic_d1_scanin;
wire i_dff_qual_atomic_d1_scanout;
wire [8:0] req_nogrant_;
wire [8:0] atom_2pass_;
wire qreq_8_6_;
wire qreq_5_3_;
wire qreq_2_0_;
wire drdy_8_6;
wire drdy_5_3;
wire drdy_2_0;
wire req_pkt_empty_a_;
wire data_rdy_a;
wire atom_8_6;
wire atom_5_3;
wire atom_2_0;
wire ccx_dest_atom_a_;
wire scan_out_prebuf;


//Primary outputs to ccx datapaths
output [8:0] arb_grant_a; //to ccx datapath

//Output to source: sparc or sctag grant flops
output         arb_src8_grant_a;
output         arb_src7_grant_a;
output         arb_src6_grant_a;
output         arb_src5_grant_a;
output         arb_src4_grant_a;
output         arb_src3_grant_a;
output         arb_src2_grant_a;
output         arb_src1_grant_a;
output         arb_src0_grant_a;

output        ccx_dest_data_rdy_a; // 
output        ccx_dest_atom_a;

//Output to arb control logic
output         req_pkt_empty_a;
output [8:0]   grant_a;   
output [8:0]   req_a;
output [8:0]   atom_a;
   

//Primary inputs from sources		 
input          src8_arb_atom_q;
input          src7_arb_atom_q;
input          src6_arb_atom_q;
input          src5_arb_atom_q;
input          src4_arb_atom_q;
input          src3_arb_atom_q;
input          src2_arb_atom_q;
input          src1_arb_atom_q;
input          src0_arb_atom_q;

input          src8_arb_req_q;
input          src7_arb_req_q;
input          src6_arb_req_q;
input          src5_arb_req_q;
input          src4_arb_req_q;
input          src3_arb_req_q;
input          src2_arb_req_q;
input          src1_arb_req_q;
input          src0_arb_req_q;

//Primary inputs from arbiter control logic
input [8:0]    qfullbar_a;
input          direction;	// priority encoder direction
input          fifo_req_sel_a;
//input          current_req_sel_a;
input          input_req_sel_a;
input          input_req_sel_a_;
input [17:0]   write_fifo_a; 	//write pointer for fifo.
input [2:0]    fifo_rptr_a;		//read pointer for fifo
input [1:0]    fifo_read_select;	//read pointer for fifo
input [8:0]    atom_x;
input          stall_q_d1;    // stall request from dest, flopped inside ccx

//Global signals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

// buffer HFN and drive to ctl
output          tcu_pce_ov_out;
output          tcu_scan_en_out;
output          ccx_aclk_out;
output          ccx_bclk_out;


// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk = ccx_aclk_out;
assign soclk = ccx_bclk_out;
assign se = tcu_scan_en_out;
// end scan


// buffer hfn


ccx_ard_dp_buff_macro__dbuff_16x__stack_none__width_4 i_buf_hfn   (
	.din	({tcu_pce_ov, tcu_scan_en, ccx_aclk, ccx_bclk}),
	.dout	({tcu_pce_ov_out, tcu_scan_en_out, ccx_aclk_out, ccx_bclk_out})
);

assign atom_q[8:0] = { src8_arb_atom_q,
			src7_arb_atom_q,
			src6_arb_atom_q,
			src5_arb_atom_q,
			src4_arb_atom_q,
			src3_arb_atom_q,
			src2_arb_atom_q,
			src1_arb_atom_q,
			src0_arb_atom_q };

assign req_q[8:0] =    { src8_arb_req_q,
			src7_arb_req_q,
			src6_arb_req_q,
			src5_arb_req_q,
			src4_arb_req_q,
			src3_arb_req_q,
			src2_arb_req_q,
			src1_arb_req_q,
			src0_arb_req_q };

ccx_ard_dp_msff_macro__dmsff_16x__stack_10c__width_10 i_dff_atom_a  
(
 .scan_in(i_dff_atom_a_scanin),
 .scan_out(i_dff_atom_a_scanout),
 .clk	(l2clk),
 .din	({direction_, atom_q[8:0]}),
 .dout	({dir_a_,     atom_int_a[8:0]}),
 .en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
 );
		 
ccx_ard_dp_msff_macro__dmsff_16x__stack_10c__width_10 i_dff_req_a   
(
 .scan_in(i_dff_req_a_scanin),
 .scan_out(i_dff_req_a_scanout),
 .clk	(l2clk),
 .din	({direction,req_q[8:0]}),
 .dout	({dir_a,req_a[8:0]}),
 .en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
 );


//BEGIN FIFO SECTION


// Do not accept a request for a queue that is full.
ccx_ard_dp_nand_macro__dnand_1x__ports_2__stack_10c__width_9 i_nand_inreq_a     
(
 .din0   (qfullbar_a[8:0]),
 .din1   (req_a[8:0]),
 .dout   (input_req_a_[8:0])
 );

ccx_ard_dp_inv_macro__dinv_24x__stack_10c__width_10 i_inv_inreq_a    
(
 .din   ({direction,input_req_a_[8:0]}),
 .dout   ({direction_,input_req_a[8:0]})
 );


// flop memory
assign fifo_wdata_prebuf[9:0] = {dir_a,input_req_a[8:0]};
ccx_ard_dp_buff_macro__dbuff_32x__minbuff_1__stack_none__width_19 i_buf_fifo_wdata    (
	.din	({atom_int_a[8:0], fifo_wdata_prebuf[9:0]}),
	.dout	({atom_a[8:0],     fifo_wdata[9:0]})
);

                                                             
ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem17  (
	.scan_in(i_dff_fmem17_scanin),
	.scan_out(i_dff_fmem17_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata17[9:0]),
	.en	(write_fifo_a[17]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem16  (
	.scan_in(i_dff_fmem16_scanin),
	.scan_out(i_dff_fmem16_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata16[9:0]),
	.en	(write_fifo_a[16]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_mux_macro__dbuff_8x__dmux_4x__mux_aope__ports_2__stack_10c__width_10 i_mux_fmem17_16      (
	.din0	(fifo_rdata17[9:0]),
	.din1	(fifo_rdata16[9:0]),
	.sel0	(fifo_rptr_a[0]),
	.dout	(fifo_rdata17_16[9:0])
);

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem15  (
	.scan_in(i_dff_fmem15_scanin),
	.scan_out(i_dff_fmem15_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata15[9:0]),
	.en	(write_fifo_a[15]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem14  (
	.scan_in(i_dff_fmem14_scanin),
	.scan_out(i_dff_fmem14_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata14[9:0]),
	.en	(write_fifo_a[14]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem13  (
	.scan_in(i_dff_fmem13_scanin),
	.scan_out(i_dff_fmem13_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata13[9:0]),
	.en	(write_fifo_a[13]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem12  (
	.scan_in(i_dff_fmem12_scanin),
	.scan_out(i_dff_fmem12_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata12[9:0]),
	.en	(write_fifo_a[12]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

		 
ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem11  (
	.scan_in(i_dff_fmem11_scanin),
	.scan_out(i_dff_fmem11_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata11[9:0]),
	.en	(write_fifo_a[11]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem10  (
	.scan_in(i_dff_fmem10_scanin),
	.scan_out(i_dff_fmem10_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata10[9:0]),
	.en	(write_fifo_a[10]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem9  (
	.scan_in(i_dff_fmem9_scanin),
	.scan_out(i_dff_fmem9_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata9[9:0]),
	.en	(write_fifo_a[9]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem8  (
	.scan_in(i_dff_fmem8_scanin),
	.scan_out(i_dff_fmem8_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata8[9:0]),
	.en	(write_fifo_a[8]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_mux_macro__dbuff_8x__dmux_4x__mux_aodec__ports_8__stack_10c__width_10 i_mux_fmem15_8      (
	.din0	(fifo_rdata8[9:0]),
	.din1	(fifo_rdata9[9:0]),
	.din2	(fifo_rdata10[9:0]),
	.din3	(fifo_rdata11[9:0]),
	.din4	(fifo_rdata12[9:0]),
	.din5	(fifo_rdata13[9:0]),
	.din6	(fifo_rdata14[9:0]),
	.din7	(fifo_rdata15[9:0]),
	.sel	(fifo_rptr_a[2:0]),
	.dout	(fifo_rdata15_8[9:0])
);

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem7  (
	.scan_in(i_dff_fmem7_scanin),
	.scan_out(i_dff_fmem7_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata7[9:0]),
	.en	(write_fifo_a[7]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem6  (
	.scan_in(i_dff_fmem6_scanin),
	.scan_out(i_dff_fmem6_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata6[9:0]),
	.en	(write_fifo_a[6]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem5  (
	.scan_in(i_dff_fmem5_scanin),
	.scan_out(i_dff_fmem5_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata5[9:0]),
	.en	(write_fifo_a[5]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem4  (
	.scan_in(i_dff_fmem4_scanin),
	.scan_out(i_dff_fmem4_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata4[9:0]),
	.en	(write_fifo_a[4]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem3  (
	.scan_in(i_dff_fmem3_scanin),
	.scan_out(i_dff_fmem3_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata3[9:0]),
	.en	(write_fifo_a[3]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem2  (
	.scan_in(i_dff_fmem2_scanin),
	.scan_out(i_dff_fmem2_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata2[9:0]),
	.en	(write_fifo_a[2]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem1  (
	.scan_in(i_dff_fmem1_scanin),
	.scan_out(i_dff_fmem1_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata1[9:0]),
	.en	(write_fifo_a[1]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_fmem0  (
	.scan_in(i_dff_fmem0_scanin),
	.scan_out(i_dff_fmem0_scanout),
	.clk	(l2clk),
	.din	(fifo_wdata[9:0]),
	.dout	(fifo_rdata0[9:0]),
	.en	(write_fifo_a[0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);		

ccx_ard_dp_mux_macro__dbuff_8x__dmux_4x__mux_aodec__ports_8__stack_10c__width_10 i_mux_fmem7_0      (
	.din0	(fifo_rdata0[9:0]),
	.din1	(fifo_rdata1[9:0]),
	.din2	(fifo_rdata2[9:0]),
	.din3	(fifo_rdata3[9:0]),
	.din4	(fifo_rdata4[9:0]),
	.din5	(fifo_rdata5[9:0]),
	.din6	(fifo_rdata6[9:0]),
	.din7	(fifo_rdata7[9:0]),
	.sel	(fifo_rptr_a[2:0]),
	.dout	(fifo_rdata7_0[9:0])
);
		 
ccx_ard_dp_mux_macro__dmux_1x__mux_aodec__ports_4__stack_10c__width_10 i_mux_fifo_req     (
	.din0	(fifo_rdata7_0[9:0]),
	.din1	(fifo_rdata15_8[9:0]),
	.din2	(fifo_rdata17_16[9:0]),
	.din3	(fifo_wdata[9:0]),
	.sel	({fifo_read_select[1:0]}),
	.dout   ({fifo_dir,fifo_req[8:0]})
);

//End flop memory section 


//BEGIN PE SECTION		 

ccx_ard_dp_mux_macro__dmux_1x__mux_aonpe__ports_2__stack_10c__width_10 i_mux_reqmux     (
	.din0	({qual_dir,qual_req[8:0]}),
	.din1	({fifo_dir,fifo_req[8:0]}),
	.sel0	(current_req_sel_a),
	.sel1	(fifo_req_sel_a),
	.dout	({fq_dir,fq_req[8:0]})
);

ccx_ard_dp_msff_macro__stack_10c__width_10 i_dff_reqreg  (
	.scan_in(i_dff_reqreg_scanin),
	.scan_out(i_dff_reqreg_scanout),
	.clk	(l2clk),
	.din	({fq_dir,fq_req[8:0]}),
	.dout	({fq_dir_a_prebuf,fq_req_a[8:0]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ccx_ard_dp_buff_macro__dbuff_8x__stack_10c__width_1 i_buf_fqdir   (
	.din	(fq_dir_a_prebuf),
	.dout	(fq_dir_a)
                                                      
);


// implement this mux using nand-nand. During the first nand, qualify
// req_a with qfull_bar. This removes one AND gate from critical path
//mux_macro i_mux_inmux (width=10, mux=aope, ports=2,stack=10c) (
//	.din0	({dir_a,input_req_a[8:0]}),
//	.din1	({fq_dir_a,fq_req_a[8:0]}),
//	.sel0	(input_req_sel_a),
//	.dout   ({dir,req[8:0]}),
//);


ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_10 i_nand3i_inmux    (
	.din0	({dir_a,req_a[8:0]}),
	.din1	({1'b1,qfullbar_a[8:0]}),
	.din2	({10{input_req_sel_a}}),
	.dout   ({input_dir_a_,input_req_qfullbar_a_[8:0]})
);

ccx_ard_dp_nand_macro__dnand_4x__ports_2__stack_10c__width_10 i_nand2i_inmux    (
	.din0	({fq_dir_a,fq_req_a[8:0]}),
	.din1	({10{input_req_sel_a_}}),
	.dout   ({fq_input_dir_a_,fq_input_req_a_[8:0]})
);

ccx_ard_dp_nand_macro__dnand_12x__ports_2__stack_10c__width_10 i_nand2o_inmux    (
	.din0	({input_dir_a_,input_req_qfullbar_a_[8:0]}),
	.din1	({fq_input_dir_a_,fq_input_req_a_[8:0]}),
	.dout   ({dir,req[8:0]})
);
                                                        

ccx_ard_dp_nand_macro__dnand_1x__ports_2__stack_10c__width_9 i_nand_atomreq    (
	.din0	(atom_int_a[8:0]),
	.din1	(input_req_a[8:0]),
	.dout	(atom_req_a_[8:0])
);

ccx_ard_dp_inv_macro__dinv_2x__stack_10c__width_9 i_inv_atomreq    (
	.din	(atom_req_a_[8:0]),
	.dout	(atom_req_a[8:0])
);

ccx_ard_dp_mux_macro__dmux_8x__mux_aope__ports_2__stack_10c__width_9 i_mux_atom     (
	.din0	(atom_req_a[8:0]),
	.din1	(atom_x[8:0]),
	.sel0	(input_req_sel_a),
	.dout   (atom[8:0])
);

//assign dira = ~stall_a & dir;
//assign dird = ~stall_a & ~dir;
// replicate the input mux with this functionality built in.

ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_1 i_nand3_dira_inmux     
(
	.din0	(dir_a),
	.din1	(stall_a_),
	.din2	(input_req_sel_a),
	.dout   (input_dira_stall_)
 );
                               
ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_1 i_nand3_fq_dira_inmux    (
	.din0	(fq_dir_a),
	.din1	(stall_a_),
	.din2	(input_req_sel_a_),
	.dout   (fq_input_dira_stall_)
);

ccx_ard_dp_nand_macro__dnand_12x__ports_2__stack_10c__width_1 i_nand2o_dira_inmux    (
	.din0	(input_dira_stall_),
	.din1	(fq_input_dira_stall_),
	.dout   (dira)
);

ccx_ard_dp_inv_macro__dinv_4x__stack_10c__width_1 i_inv_dir    (
	.din	({fq_dir_a}),
	.dout	({fq_dir_a_})
);

ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_1 i_nand3_dird_inmux     
(
	.din0	(dir_a_),
	.din1	(stall_a_),
	.din2	(input_req_sel_a),
	.dout   (input_dird_stall_)
 );
                               
ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_1 i_nand3_fq_dird_inmux    (
	.din0	(fq_dir_a_),
	.din1	(stall_a_),
	.din2   (input_req_sel_a_),
	.dout   (fq_input_dird_stall_)
);

ccx_ard_dp_nand_macro__dnand_12x__ports_2__stack_10c__width_1 i_nand2o_dird_inmux    (
	.din0	(input_dird_stall_),
	.din1	(fq_input_dird_stall_),
	.dout   (dird)
);


ccx_ard_dp_inv_macro__dinv_12x__stack_10c__width_9 i_ainv_1_w9   (
	.din	({req[8:0]}),
	.dout	({r8_,r7_,r6_,r5_,r4_,r3_,r2_,r1_,r0_})
);

ccx_ard_dp_and_macro__dinv_12x__dnand_4x__ports_4__stack_10c__width_2 i_aand4_1_w2      
(
 .din0 ({r4_,r0_}),
 .din1 ({r5_,r1_}),
 .din2 ({r6_,r2_}),
 .din3 ({r7_,r3_}),
 .dout({ra_or_7654_,ra_or_3210_})
 );

ccx_ard_dp_and_macro__dinv_8x__dnand_2x__ports_3__stack_10c__width_4 i_aand3_1_w4      
(
 .din0 ({r4_,       r4_,      r4_,       r0_}),
 .din1 ({r5_,       req[5],   r5_,       r1_}), 
 .din2 ({r6_,       dira,     r3_,       r2_}),
 .dout({ ra_or_654_, ra_d54x, ra_or_543_, ra_or_210_})
 );

ccx_ard_dp_nor_macro__dnor_8x__ports_2__stack_10c__width_3 i_anor2_1_w3    
(
 .din0({req[2],req[2],req[0]}),
 .din1({req[3],req[1],req[1]}),
 .dout({ra_or_32_,ra_or_21_,ra_or_10_})
 );

ccx_ard_dp_nand_macro__dnand_2x__ports_2__stack_10c__width_5 i_anand2_1_w5     
(
 .din0 ({dira,   dira,    dira,    dira,    dira   }),
 .din1 ({req[8], req[7],  req[6],  req[4],  req[3] }),
 .dout ({ra_d8_, ra_d7_,  ra_d6_,  ra_d4_,  ra_d3_ })
 );

ccx_ard_dp_nand_macro__dnand_8x__ports_2__stack_10c__width_1 i_anand2_2_w1     
(
 .din0 ({dira}),
 .din1 ({req[0]}),
 .dout ({grant_asc_[0]})
 );

ccx_ard_dp_inv_macro__dinv_4x__stack_10c__width_5 i_ainv_2_w5   (
	.din	({ra_d8_, ra_d7_,  ra_d6_,  ra_d4_,  ra_d3_}),
	.dout	({ra_d8,  ra_d7,   ra_d6,   ra_d4,   ra_d3})
); 

ccx_ard_dp_nand_macro__dnand_8x__ports_3__stack_10c__width_8 i_anand3_2_w8     
(
 .din0 ({ra_or_3210_, ra_or_3210_, ra_or_210_, ra_or_10_, ra_or_10_, r0_,       ra_or_10_, r0_}),
 .din1 ({ra_or_7654_, ra_or_654_,  ra_or_543_, ra_or_32_, ra_or_32_, ra_or_21_, req[2],    req[1]}),
 .din2 ({ra_d8,       ra_d7,       ra_d6,      ra_d54x,   ra_d4,     ra_d3,     dira,      dira}),
 .dout(grant_asc_[8:1])
 );

                               
//Descending priority encoder.
//assign grant_des[8] =  req[8];
//assign grant_des[7] = ~req[8]& req[7];
//assign grant_des[6] = ~req[8]&~req[7]& req[6];
//assign grant_des[5] = ~req[8]&~req[7]&~req[6]& req[5];                                  
//assign grant_des[4] = ~req[8]&~req[7]&~req[6]&~req[5]& req[4];                          
//assign grant_des[3] = ~req[8]&~req[7]&~req[6]&~req[5]&~req[4]& req[3];                    
//assign grant_des[2] = ~req[8]&~req[7]&~req[6]&~req[5]&~req[4]&~req[3]& req[2];        
//assign grant_des[1] = ~req[8]&~req[7]&~req[6]&~req[5]&~req[4]&~req[3]&~req[2]&req[1];
//assign grant_des[0] = ~req[8]&~req[7]&~req[6]&~req[5]&~req[4]&~req[3]&~req[2]&~req[1]&req[0];


assign reqd[8:0] = {req[0],req[1],req[2],req[3],req[4],req[5],req[6],req[7],req[8]};
assign {rd7_,rd6_,rd5_,rd4_,rd3_,rd2_,rd1_,rd0_} = {r1_,r2_,r3_,r4_,r5_,r6_,r7_,r8_};

ccx_ard_dp_and_macro__dinv_12x__dnand_4x__ports_4__stack_10c__width_2 i_dand4_1_w2      
(
 .din0 ({rd4_,rd0_}),
 .din1 ({rd5_,rd1_}),
 .din2 ({rd6_,rd2_}),
 .din3 ({rd7_,rd3_}),
 .dout({rd_or_7654_,rd_or_3210_})
 );


ccx_ard_dp_and_macro__dinv_8x__dnand_2x__ports_3__stack_10c__width_4 i_dand3_1_w4      
(
 .din0 ({rd4_,        rd4_,      rd4_,      rd0_}),
 .din1 ({rd5_,        reqd[5],   rd5_,      rd1_}), 
 .din2 ({rd6_,        dird,      rd3_,      rd2_}),
 .dout({ rd_or_654_,   rd_d54x,  rd_or_543_, rd_or_210_})
 );

ccx_ard_dp_nor_macro__dnor_8x__ports_2__stack_10c__width_3 i_dnor2_1_w3    
(
 .din0({reqd[2],reqd[2],reqd[0]}),
 .din1({reqd[3],reqd[1],reqd[1]}),
 .dout({rd_or_32_,rd_or_21_,rd_or_10_})
 );

ccx_ard_dp_nand_macro__dnand_2x__ports_2__stack_10c__width_5 i_dnand2_1_w5     
(
 .din0 ({dird,    dird,    dird,    dird,    dird   }),
 .din1 ({reqd[8], reqd[7], reqd[6], reqd[4], reqd[3]}),
 .dout ({rd_d8_,  rd_d7_,  rd_d6_,  rd_d4_,  rd_d3_ })
 );

ccx_ard_dp_nand_macro__dnand_8x__ports_2__stack_10c__width_1 i_dnand2_2_w1     
(
 .din0 ({dird}),
 .din1 ({reqd[0]}),
 .dout ({grant_dsc_[0]})
 );

ccx_ard_dp_inv_macro__dinv_4x__stack_10c__width_5 i_dinv_2_w5   (
	.din	({rd_d8_, rd_d7_,  rd_d6_,  rd_d4_,  rd_d3_}),
	.dout	({rd_d8,  rd_d7,   rd_d6,   rd_d4,   rd_d3})
); 

ccx_ard_dp_nand_macro__dnand_8x__ports_3__stack_10c__width_8 i_dnand3_2_w8     
(
 .din0 ({rd_or_3210_, rd_or_3210_, rd_or_210_, rd_or_10_, rd_or_10_, rd0_,       rd_or_10_, rd0_}),
 .din1 ({rd_or_7654_, rd_or_654_,  rd_or_543_, rd_or_32_, rd_or_32_, rd_or_21_, reqd[2],    reqd[1]}),
 .din2 ({rd_d8,       rd_d7,       rd_d6,      rd_d54x,   rd_d4,     rd_d3,     dird,      dird}),
 .dout(grant_dsc_[8:1])
 );

assign grant_des_[8:0] = {grant_dsc_[0],grant_dsc_[1],grant_dsc_[2],grant_dsc_[3],grant_dsc_[4],grant_dsc_[5],grant_dsc_[6],grant_dsc_[7],grant_dsc_[8]};
                                         
                               
ccx_ard_dp_nand_macro__dnand_32x__ports_2__stack_10c__width_9 i_nand_dirmux   
(
 .din0 (grant_asc_[8:0]),
 .din1	(grant_des_[8:0]),
 .dout   (grant_int_a[8:0])
 );

                                                      
// Buffer grants to be sent back to the sources (sparcs/L2s)
ccx_ard_dp_buff_macro__dbuff_48x__stack_10c__width_9 i_buf_src_grant   (
	.din	(grant_int_a[8:0]),
	.dout	({arb_src8_grant_a,
		  arb_src7_grant_a,
		  arb_src6_grant_a,
		  arb_src5_grant_a,
		  arb_src4_grant_a,
		  arb_src3_grant_a,
		  arb_src2_grant_a,
		  arb_src1_grant_a,
		  arb_src0_grant_a})
);

// Buffer grants to be sent back to the source queues
ccx_ard_dp_buff_macro__dbuff_32x__stack_10c__width_9 i_buf_queue_grant   
(
 .din	(grant_int_a[8:0]),
 .dout	(arb_grant_a[8:0])
 );

// Add MINTIME Buffer to grants to be sent back to the control block arc
ccx_ard_dp_buff_macro__dbuff_16x__minbuff_1__stack_10c__width_9 i_bufmin_grant    
(
 .din	(grant_int_a[8:0]),
 .dout	(grant_a[8:0])
 );


ccx_ard_dp_inv_macro__dinv_8x__stack_10c__width_9 i_inv_grant_a_x   (
	.din	(grant_int_a[8:0]),
	.dout	(grant_a_[8:0])
);


// When an atomic request is granted for the first time, the request needs
// to be preserved so that the second packet gets granted immediately following.
// The indicator is set when an atomic request is granted for first time.
// The indicator is held until the request is granted again.
//assign qual_atomic[8:0] = (atom[8:0] & grant_int_a[8:0] & qual_atomic_d1_[8:0]) | // set
//			              (grant_a_[8:0] & qual_atomic_d1[8:0]); // hold

ccx_ard_dp_nand_macro__dnand_1x__ports_3__stack_10c__width_9 i_nand_set_qualatom    (
	.din0	(atom[8:0]),
	.din1	(grant_int_a[8:0]),
	.din2	(qual_atomic_d1_[8:0]),
	.dout	(set_qual_atomic[8:0])
);

ccx_ard_dp_nand_macro__dnand_1x__ports_2__stack_10c__width_9 i_nand_hold_qualatom    (
	.din0	(grant_a_[8:0]),
	.din1	(qual_atomic_d1[8:0]),
	.dout	(hold_qual_atomic[8:0])
);

ccx_ard_dp_nand_macro__dnand_1x__ports_2__stack_10c__width_10 i_nand_qual_atomic    (
	.din0	({stall_q_d1,set_qual_atomic[8:0]}),
	.din1	({1'b1,hold_qual_atomic[8:0]}),
	.dout	({stall_q_d1_,qual_atomic[8:0]})
);

ccx_ard_dp_msff_macro__dmsff_8x__stack_10c__stack_10c__width_10 i_dff_qual_atomic_d1   (
	.scan_in(i_dff_qual_atomic_d1_scanin),
	.scan_out(i_dff_qual_atomic_d1_scanout),
	.clk	(l2clk),
	.din	({stall_q_d1_,qual_atomic[8:0]}),
	.dout	({stall_a_,qual_atomic_d1[8:0]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
ccx_ard_dp_inv_macro__dinv_2x__stack_10c__width_9 i_inv_qual_atomic_d1_x   (
	.din	(qual_atomic_d1[8:0]),
	.dout	(qual_atomic_d1_[8:0])
);

// Recycle the packet until it is empty.
// Keep any request that was not granted.
// Keep an atomic request after it's first grant.
// This gets fed into the request selection mux.
// one of the terms is the same as the SET term in qual_atomic
//assign qual_req[8:0] = (req[8:0] & grant_a_[8:0]) | (atom[8:0] & grant_int_a[8:0] & qual_atomic_d1_[8:0]) ;

ccx_ard_dp_nand_macro__dnand_2x__ports_2__stack_10c__width_9 i_nand_req_nogrant    (
	.din0	(req[8:0]),
	.din1	(grant_a_[8:0]),
	.dout	(req_nogrant_[8:0])
);

ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_9 i_nand_set_qualatom2    (
	.din0	(atom[8:0]),
	.din1	(grant_int_a[8:0]),
	.din2	(qual_atomic_d1_[8:0]),
	.dout	(atom_2pass_[8:0])
);
ccx_ard_dp_nand_macro__dnand_8x__ports_2__stack_10c__width_9 i_nand_qual_req    (
	.din0	(req_nogrant_[8:0]),
	.din1	(atom_2pass_[8:0]),
	.dout	(qual_req[8:0])
);

assign qual_dir = dir;

//assign req_pkt_empty_a  = ~(|(qual_req[8:0]));
//assign ccx_dest_data_rdy_a = |(grant_int_a[8:0]);
ccx_ard_dp_nor_macro__dnor_4x__ports_3__stack_10c__width_6 i_nor_rpe    (
	.din0	({qual_req[8], qual_req[5], qual_req[2], grant_int_a[8], grant_int_a[5], grant_int_a[2]}),
	.din1	({qual_req[7], qual_req[4], qual_req[1], grant_int_a[7], grant_int_a[4], grant_int_a[1]}),
	.din2	({qual_req[6], qual_req[3], qual_req[0], grant_int_a[6], grant_int_a[3], grant_int_a[0]}),
	.dout	({qreq_8_6_, qreq_5_3_, qreq_2_0_, drdy_8_6, drdy_5_3, drdy_2_0})
);
ccx_ard_dp_nand_macro__dnand_8x__ports_3__stack_10c__width_2 i_nand_rpe    (
	.din0	({qreq_8_6_,drdy_8_6}),
	.din1	({qreq_5_3_,drdy_5_3}),
	.din2	({qreq_2_0_,drdy_2_0}),
	.dout	({req_pkt_empty_a_,data_rdy_a})
);
ccx_ard_dp_inv_macro__dinv_32x__stack_10c__width_1 i_inv_rpe    (
	.din	(req_pkt_empty_a_),
	.dout	(req_pkt_empty_a)
);

ccx_ard_dp_buff_macro__dbuff_32x__stack_none__width_1 buff_drdy   (
	.din	(data_rdy_a),
	.dout	(ccx_dest_data_rdy_a)
);
assign current_req_sel_a = req_pkt_empty_a_;


//assign ccx_dest_atom_a = |(grant_int_a[8:0] & atom[8:0] & qual_atomic_d1_[8:0]);
ccx_ard_dp_nand_macro__dnand_1x__ports_3__stack_10c__width_3 i_nand_atom    (
	.din0	({atom_2pass_[8], atom_2pass_[5], atom_2pass_[2]}),
	.din1	({atom_2pass_[7], atom_2pass_[4], atom_2pass_[1]}),
	.din2	({atom_2pass_[6], atom_2pass_[3], atom_2pass_[0]}),
	.dout	({atom_8_6, atom_5_3, atom_2_0})
);
ccx_ard_dp_nor_macro__dnor_4x__ports_3__stack_10c__width_1 i_nor_atom    (
	.din0	(atom_8_6),
	.din1	(atom_5_3),
	.din2	(atom_2_0),
	.dout	(ccx_dest_atom_a_)
);
ccx_ard_dp_inv_macro__dinv_32x__stack_10c__width_1 i_inv_dest_atom   (
	.din	(ccx_dest_atom_a_),
	.dout	(ccx_dest_atom_a)
);
ccx_ard_dp_buff_macro__dbuff_8x__stack_none__width_1 buff_scanout   (
	.din	(scan_out_prebuf),
	.dout	(scan_out)
);


// fixscan start:
assign i_dff_atom_a_scanin       = scan_in                  ;
assign i_dff_req_a_scanin        = i_dff_atom_a_scanout     ;
assign i_dff_fmem17_scanin       = i_dff_req_a_scanout      ;
assign i_dff_fmem16_scanin       = i_dff_fmem17_scanout     ;
assign i_dff_fmem15_scanin       = i_dff_fmem16_scanout     ;
assign i_dff_fmem14_scanin       = i_dff_fmem15_scanout     ;
assign i_dff_fmem13_scanin       = i_dff_fmem14_scanout     ;
assign i_dff_fmem12_scanin       = i_dff_fmem13_scanout     ;
assign i_dff_fmem11_scanin       = i_dff_fmem12_scanout     ;
assign i_dff_fmem10_scanin       = i_dff_fmem11_scanout     ;
assign i_dff_fmem9_scanin        = i_dff_fmem10_scanout     ;
assign i_dff_fmem8_scanin        = i_dff_fmem9_scanout      ;
assign i_dff_fmem7_scanin        = i_dff_fmem8_scanout      ;
assign i_dff_fmem6_scanin        = i_dff_fmem7_scanout      ;
assign i_dff_fmem5_scanin        = i_dff_fmem6_scanout      ;
assign i_dff_fmem4_scanin        = i_dff_fmem5_scanout      ;
assign i_dff_fmem3_scanin        = i_dff_fmem4_scanout      ;
assign i_dff_fmem2_scanin        = i_dff_fmem3_scanout      ;
assign i_dff_fmem1_scanin        = i_dff_fmem2_scanout      ;
assign i_dff_fmem0_scanin        = i_dff_fmem1_scanout      ;
assign i_dff_reqreg_scanin       = i_dff_fmem0_scanout      ;
assign i_dff_qual_atomic_d1_scanin = i_dff_reqreg_scanout     ;
assign scan_out_prebuf             = i_dff_qual_atomic_d1_scanout;
// fixscan end:
endmodule


//
//   buff macro
//
//


module ccx_ard_dp_buff_macro__dbuff_16x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_ard_dp_msff_macro__dmsff_16x__stack_10c__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_1x__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   invert macro
//
//


module ccx_ard_dp_inv_macro__dinv_24x__stack_10c__width_10 (
  din, 
  dout);
  input [9:0] din;
  output [9:0] dout;


inv #(10)  d0_0 (
.in(din[9:0]),
.out(dout[9:0])
);


endmodule


//
//   buff macro
//
//


module ccx_ard_dp_buff_macro__dbuff_32x__minbuff_1__stack_none__width_19 (
  din, 
  dout);
  input [18:0] din;
  output [18:0] dout;


buff #(19)  d0_0 (
.in(din[18:0]),
.out(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_ard_dp_msff_macro__stack_10c__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_ard_dp_mux_macro__dbuff_8x__dmux_4x__mux_aope__ports_2__stack_10c__width_10 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [9:0] din0;
  input [9:0] din1;
  input sel0;
  output [9:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(10)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
.dout(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_ard_dp_mux_macro__dbuff_8x__dmux_4x__mux_aodec__ports_8__stack_10c__width_10 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [9:0] din0;
  input [9:0] din1;
  input [9:0] din2;
  input [9:0] din3;
  input [9:0] din4;
  input [9:0] din5;
  input [9:0] din6;
  input [9:0] din7;
  input [2:0] sel;
  output [9:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(10)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
  .in2(din2[9:0]),
  .in3(din3[9:0]),
  .in4(din4[9:0]),
  .in5(din5[9:0]),
  .in6(din6[9:0]),
  .in7(din7[9:0]),
.dout(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_ard_dp_mux_macro__dmux_1x__mux_aodec__ports_4__stack_10c__width_10 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [9:0] din0;
  input [9:0] din1;
  input [9:0] din2;
  input [9:0] din3;
  input [1:0] sel;
  output [9:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(10)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
  .in2(din2[9:0]),
  .in3(din3[9:0]),
.dout(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_ard_dp_mux_macro__dmux_1x__mux_aonpe__ports_2__stack_10c__width_10 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [9:0] din0;
  input sel0;
  input [9:0] din1;
  input sel1;
  output [9:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(10)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
.dout(dout[9:0])
);


endmodule


//
//   buff macro
//
//


module ccx_ard_dp_buff_macro__dbuff_8x__stack_10c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_10 (
  din0, 
  din1, 
  din2, 
  dout);
  input [9:0] din0;
  input [9:0] din1;
  input [9:0] din2;
  output [9:0] dout;


nand3 #(10)  d0_0 (
.in0(din0[9:0]),
.in1(din1[9:0]),
.in2(din2[9:0]),
.out(dout[9:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_4x__ports_2__stack_10c__width_10 (
  din0, 
  din1, 
  dout);
  input [9:0] din0;
  input [9:0] din1;
  output [9:0] dout;


nand2 #(10)  d0_0 (
.in0(din0[9:0]),
.in1(din1[9:0]),
.out(dout[9:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_12x__ports_2__stack_10c__width_10 (
  din0, 
  din1, 
  dout);
  input [9:0] din0;
  input [9:0] din1;
  output [9:0] dout;


nand2 #(10)  d0_0 (
.in0(din0[9:0]),
.in1(din1[9:0]),
.out(dout[9:0])
);


endmodule


//
//   invert macro
//
//


module ccx_ard_dp_inv_macro__dinv_2x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


inv #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ccx_ard_dp_mux_macro__dmux_8x__mux_aope__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [8:0] din0;
  input [8:0] din1;
  input sel0;
  output [8:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(9)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[8:0]),
  .in1(din1[8:0]),
.dout(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nand3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_12x__ports_2__stack_10c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module ccx_ard_dp_inv_macro__dinv_4x__stack_10c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module ccx_ard_dp_inv_macro__dinv_12x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


inv #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ccx_ard_dp_and_macro__dinv_12x__dnand_4x__ports_4__stack_10c__width_2 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  input [1:0] din2;
  input [1:0] din3;
  output [1:0] dout;


and4 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.in2(din2[1:0]),
.in3(din3[1:0]),
.out(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ccx_ard_dp_and_macro__dinv_8x__dnand_2x__ports_3__stack_10c__width_4 (
  din0, 
  din1, 
  din2, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  input [3:0] din2;
  output [3:0] dout;


and3 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.in2(din2[3:0]),
.out(dout[3:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module ccx_ard_dp_nor_macro__dnor_8x__ports_2__stack_10c__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


nor2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_2x__ports_2__stack_10c__width_5 (
  din0, 
  din1, 
  dout);
  input [4:0] din0;
  input [4:0] din1;
  output [4:0] dout;


nand2 #(5)  d0_0 (
.in0(din0[4:0]),
.in1(din1[4:0]),
.out(dout[4:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_8x__ports_2__stack_10c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module ccx_ard_dp_inv_macro__dinv_4x__stack_10c__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


inv #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_8x__ports_3__stack_10c__width_8 (
  din0, 
  din1, 
  din2, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  output [7:0] dout;


nand3 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.in2(din2[7:0]),
.out(dout[7:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_32x__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module ccx_ard_dp_buff_macro__dbuff_48x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module ccx_ard_dp_buff_macro__dbuff_32x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module ccx_ard_dp_buff_macro__dbuff_16x__minbuff_1__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   invert macro
//
//


module ccx_ard_dp_inv_macro__dinv_8x__stack_10c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


inv #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_1x__ports_3__stack_10c__width_9 (
  din0, 
  din1, 
  din2, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  input [8:0] din2;
  output [8:0] dout;


nand3 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.in2(din2[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_1x__ports_2__stack_10c__width_10 (
  din0, 
  din1, 
  dout);
  input [9:0] din0;
  input [9:0] din1;
  output [9:0] dout;


nand2 #(10)  d0_0 (
.in0(din0[9:0]),
.in1(din1[9:0]),
.out(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ccx_ard_dp_msff_macro__dmsff_8x__stack_10c__stack_10c__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_2x__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_4x__ports_3__stack_10c__width_9 (
  din0, 
  din1, 
  din2, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  input [8:0] din2;
  output [8:0] dout;


nand3 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.in2(din2[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_8x__ports_2__stack_10c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module ccx_ard_dp_nor_macro__dnor_4x__ports_3__stack_10c__width_6 (
  din0, 
  din1, 
  din2, 
  dout);
  input [5:0] din0;
  input [5:0] din1;
  input [5:0] din2;
  output [5:0] dout;


nor3 #(6)  d0_0 (
.in0(din0[5:0]),
.in1(din1[5:0]),
.in2(din2[5:0]),
.out(dout[5:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_8x__ports_3__stack_10c__width_2 (
  din0, 
  din1, 
  din2, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  input [1:0] din2;
  output [1:0] dout;


nand3 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.in2(din2[1:0]),
.out(dout[1:0])
);


endmodule


//
//   invert macro
//
//


module ccx_ard_dp_inv_macro__dinv_32x__stack_10c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module ccx_ard_dp_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ccx_ard_dp_nand_macro__dnand_1x__ports_3__stack_10c__width_3 (
  din0, 
  din1, 
  din2, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  output [2:0] dout;


nand3 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.in2(din2[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module ccx_ard_dp_nor_macro__dnor_4x__ports_3__stack_10c__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nor3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module ccx_ard_dp_buff_macro__dbuff_8x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
module ccx_ard_dp(arb_grant_a, arb_src8_grant_a, arb_src7_grant_a, 
	arb_src6_grant_a, arb_src5_grant_a, arb_src4_grant_a, arb_src3_grant_a, 
	arb_src2_grant_a, arb_src1_grant_a, arb_src0_grant_a, 
	ccx_dest_data_rdy_a, ccx_dest_atom_a, req_pkt_empty_a, grant_a, req_a, 
	atom_a, src8_arb_atom_q, src7_arb_atom_q, src6_arb_atom_q, 
	src5_arb_atom_q, src4_arb_atom_q, src3_arb_atom_q, src2_arb_atom_q, 
	src1_arb_atom_q, src0_arb_atom_q, src8_arb_req_q, src7_arb_req_q, 
	src6_arb_req_q, src5_arb_req_q, src4_arb_req_q, src3_arb_req_q, 
	src2_arb_req_q, src1_arb_req_q, src0_arb_req_q, qfullbar_a, direction, 
	fifo_req_sel_a, input_req_sel_a, input_req_sel_a_, write_fifo_a, 
	fifo_rptr_a, fifo_read_select, atom_x, stall_q_d1, tcu_scan_en, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out, tcu_pce_ov_out, 
	tcu_scan_en_out, ccx_aclk_out, ccx_bclk_out);

	output	[8:0]		arb_grant_a;
	output			arb_src8_grant_a;
	output			arb_src7_grant_a;
	output			arb_src6_grant_a;
	output			arb_src5_grant_a;
	output			arb_src4_grant_a;
	output			arb_src3_grant_a;
	output			arb_src2_grant_a;
	output			arb_src1_grant_a;
	output			arb_src0_grant_a;
	output			ccx_dest_data_rdy_a;
	output			ccx_dest_atom_a;
	output			req_pkt_empty_a;
	output	[8:0]		grant_a;
	output	[8:0]		req_a;
	output	[8:0]		atom_a;
	input			src8_arb_atom_q;
	input			src7_arb_atom_q;
	input			src6_arb_atom_q;
	input			src5_arb_atom_q;
	input			src4_arb_atom_q;
	input			src3_arb_atom_q;
	input			src2_arb_atom_q;
	input			src1_arb_atom_q;
	input			src0_arb_atom_q;
	input			src8_arb_req_q;
	input			src7_arb_req_q;
	input			src6_arb_req_q;
	input			src5_arb_req_q;
	input			src4_arb_req_q;
	input			src3_arb_req_q;
	input			src2_arb_req_q;
	input			src1_arb_req_q;
	input			src0_arb_req_q;
	input	[8:0]		qfullbar_a;
	input			direction;
	input			fifo_req_sel_a;
	input			input_req_sel_a;
	input			input_req_sel_a_;
	input	[17:0]		write_fifo_a;
	input	[2:0]		fifo_rptr_a;
	input	[1:0]		fifo_read_select;
	input	[8:0]		atom_x;
	input			stall_q_d1;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk;
	wire			soclk;
	wire			se;
	wire	[8:0]		atom_q;
	wire	[8:0]		req_q;
	wire			i_dff_atom_a_scanin;
	wire			i_dff_atom_a_scanout;
	wire			direction_;
	wire			dir_a_;
	wire	[8:0]		atom_int_a;
	wire			i_dff_req_a_scanin;
	wire			i_dff_req_a_scanout;
	wire			dir_a;
	wire	[8:0]		input_req_a_;
	wire	[8:0]		input_req_a;
	wire	[9:0]		fifo_wdata_prebuf;
	wire	[9:0]		fifo_wdata;
	wire			i_dff_fmem17_scanin;
	wire			i_dff_fmem17_scanout;
	wire	[9:0]		fifo_rdata17;
	wire			i_dff_fmem16_scanin;
	wire			i_dff_fmem16_scanout;
	wire	[9:0]		fifo_rdata16;
	wire	[9:0]		fifo_rdata17_16;
	wire			i_dff_fmem15_scanin;
	wire			i_dff_fmem15_scanout;
	wire	[9:0]		fifo_rdata15;
	wire			i_dff_fmem14_scanin;
	wire			i_dff_fmem14_scanout;
	wire	[9:0]		fifo_rdata14;
	wire			i_dff_fmem13_scanin;
	wire			i_dff_fmem13_scanout;
	wire	[9:0]		fifo_rdata13;
	wire			i_dff_fmem12_scanin;
	wire			i_dff_fmem12_scanout;
	wire	[9:0]		fifo_rdata12;
	wire			i_dff_fmem11_scanin;
	wire			i_dff_fmem11_scanout;
	wire	[9:0]		fifo_rdata11;
	wire			i_dff_fmem10_scanin;
	wire			i_dff_fmem10_scanout;
	wire	[9:0]		fifo_rdata10;
	wire			i_dff_fmem9_scanin;
	wire			i_dff_fmem9_scanout;
	wire	[9:0]		fifo_rdata9;
	wire			i_dff_fmem8_scanin;
	wire			i_dff_fmem8_scanout;
	wire	[9:0]		fifo_rdata8;
	wire	[9:0]		fifo_rdata15_8;
	wire			i_dff_fmem7_scanin;
	wire			i_dff_fmem7_scanout;
	wire	[9:0]		fifo_rdata7;
	wire			i_dff_fmem6_scanin;
	wire			i_dff_fmem6_scanout;
	wire	[9:0]		fifo_rdata6;
	wire			i_dff_fmem5_scanin;
	wire			i_dff_fmem5_scanout;
	wire	[9:0]		fifo_rdata5;
	wire			i_dff_fmem4_scanin;
	wire			i_dff_fmem4_scanout;
	wire	[9:0]		fifo_rdata4;
	wire			i_dff_fmem3_scanin;
	wire			i_dff_fmem3_scanout;
	wire	[9:0]		fifo_rdata3;
	wire			i_dff_fmem2_scanin;
	wire			i_dff_fmem2_scanout;
	wire	[9:0]		fifo_rdata2;
	wire			i_dff_fmem1_scanin;
	wire			i_dff_fmem1_scanout;
	wire	[9:0]		fifo_rdata1;
	wire			i_dff_fmem0_scanin;
	wire			i_dff_fmem0_scanout;
	wire	[9:0]		fifo_rdata0;
	wire	[9:0]		fifo_rdata7_0;
	wire			fifo_dir;
	wire	[8:0]		fifo_req;
	wire			qual_dir;
	wire	[8:0]		qual_req;
	wire			current_req_sel_a;
	wire			fq_dir;
	wire	[8:0]		fq_req;
	wire			i_dff_reqreg_scanin;
	wire			i_dff_reqreg_scanout;
	wire			fq_dir_a_prebuf;
	wire	[8:0]		fq_req_a;
	wire			fq_dir_a;
	wire			input_dir_a_;
	wire	[8:0]		input_req_qfullbar_a_;
	wire			fq_input_dir_a_;
	wire	[8:0]		fq_input_req_a_;
	wire			dir;
	wire	[8:0]		req;
	wire	[8:0]		atom_req_a_;
	wire	[8:0]		atom_req_a;
	wire	[8:0]		atom;
	wire			stall_a_;
	wire			input_dira_stall_;
	wire			fq_input_dira_stall_;
	wire			dira;
	wire			fq_dir_a_;
	wire			input_dird_stall_;
	wire			fq_input_dird_stall_;
	wire			dird;
	wire			r8_;
	wire			r7_;
	wire			r6_;
	wire			r5_;
	wire			r4_;
	wire			r3_;
	wire			r2_;
	wire			r1_;
	wire			r0_;
	wire			ra_or_7654_;
	wire			ra_or_3210_;
	wire			ra_or_654_;
	wire			ra_d54x;
	wire			ra_or_543_;
	wire			ra_or_210_;
	wire			ra_or_32_;
	wire			ra_or_21_;
	wire			ra_or_10_;
	wire			ra_d8_;
	wire			ra_d7_;
	wire			ra_d6_;
	wire			ra_d4_;
	wire			ra_d3_;
	wire	[8:0]		grant_asc_;
	wire			ra_d8;
	wire			ra_d7;
	wire			ra_d6;
	wire			ra_d4;
	wire			ra_d3;
	wire	[8:0]		reqd;
	wire			rd7_;
	wire			rd6_;
	wire			rd5_;
	wire			rd4_;
	wire			rd3_;
	wire			rd2_;
	wire			rd1_;
	wire			rd0_;
	wire			rd_or_7654_;
	wire			rd_or_3210_;
	wire			rd_or_654_;
	wire			rd_d54x;
	wire			rd_or_543_;
	wire			rd_or_210_;
	wire			rd_or_32_;
	wire			rd_or_21_;
	wire			rd_or_10_;
	wire			rd_d8_;
	wire			rd_d7_;
	wire			rd_d6_;
	wire			rd_d4_;
	wire			rd_d3_;
	wire	[8:0]		grant_dsc_;
	wire			rd_d8;
	wire			rd_d7;
	wire			rd_d6;
	wire			rd_d4;
	wire			rd_d3;
	wire	[8:0]		grant_des_;
	wire	[8:0]		grant_int_a;
	wire	[8:0]		grant_a_;
	wire	[8:0]		qual_atomic_d1_;
	wire	[8:0]		set_qual_atomic;
	wire	[8:0]		qual_atomic_d1;
	wire	[8:0]		hold_qual_atomic;
	wire			stall_q_d1_;
	wire	[8:0]		qual_atomic;
	wire			i_dff_qual_atomic_d1_scanin;
	wire			i_dff_qual_atomic_d1_scanout;
	wire	[8:0]		req_nogrant_;
	wire	[8:0]		atom_2pass_;
	wire			qreq_8_6_;
	wire			qreq_5_3_;
	wire			qreq_2_0_;
	wire			drdy_8_6;
	wire			drdy_5_3;
	wire			drdy_2_0;
	wire			req_pkt_empty_a_;
	wire			data_rdy_a;
	wire			atom_8_6;
	wire			atom_5_3;
	wire			atom_2_0;
	wire			ccx_dest_atom_a_;
	wire			scan_out_prebuf;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk = ccx_aclk_out;
	assign soclk = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign atom_q[8:0] = {src8_arb_atom_q, src7_arb_atom_q, src6_arb_atom_q,
		src5_arb_atom_q, src4_arb_atom_q, src3_arb_atom_q, 
		src2_arb_atom_q, src1_arb_atom_q, src0_arb_atom_q};
	assign req_q[8:0] = {src8_arb_req_q, src7_arb_req_q, src6_arb_req_q, 
		src5_arb_req_q, src4_arb_req_q, src3_arb_req_q, src2_arb_req_q, 
		src1_arb_req_q, src0_arb_req_q};
	assign fifo_wdata_prebuf[9:0] = {dir_a, input_req_a[8:0]};
	assign reqd[8:0] = {req[0], req[1], req[2], req[3], req[4], req[5], 
		req[6], req[7], req[8]};
	assign {rd7_, rd6_, rd5_, rd4_, rd3_, rd2_, rd1_, rd0_} = {r1_, r2_, 
		r3_, r4_, r5_, r6_, r7_, r8_};
	assign grant_des_[8:0] = {grant_dsc_[0], grant_dsc_[1], grant_dsc_[2], 
		grant_dsc_[3], grant_dsc_[4], grant_dsc_[5], grant_dsc_[6], 
		grant_dsc_[7], grant_dsc_[8]};
	assign qual_dir = dir;
	assign current_req_sel_a = req_pkt_empty_a_;
	assign i_dff_atom_a_scanin = scan_in;
	assign i_dff_req_a_scanin = i_dff_atom_a_scanout;
	assign i_dff_fmem17_scanin = i_dff_req_a_scanout;
	assign i_dff_fmem16_scanin = i_dff_fmem17_scanout;
	assign i_dff_fmem15_scanin = i_dff_fmem16_scanout;
	assign i_dff_fmem14_scanin = i_dff_fmem15_scanout;
	assign i_dff_fmem13_scanin = i_dff_fmem14_scanout;
	assign i_dff_fmem12_scanin = i_dff_fmem13_scanout;
	assign i_dff_fmem11_scanin = i_dff_fmem12_scanout;
	assign i_dff_fmem10_scanin = i_dff_fmem11_scanout;
	assign i_dff_fmem9_scanin = i_dff_fmem10_scanout;
	assign i_dff_fmem8_scanin = i_dff_fmem9_scanout;
	assign i_dff_fmem7_scanin = i_dff_fmem8_scanout;
	assign i_dff_fmem6_scanin = i_dff_fmem7_scanout;
	assign i_dff_fmem5_scanin = i_dff_fmem6_scanout;
	assign i_dff_fmem4_scanin = i_dff_fmem5_scanout;
	assign i_dff_fmem3_scanin = i_dff_fmem4_scanout;
	assign i_dff_fmem2_scanin = i_dff_fmem3_scanout;
	assign i_dff_fmem1_scanin = i_dff_fmem2_scanout;
	assign i_dff_fmem0_scanin = i_dff_fmem1_scanout;
	assign i_dff_reqreg_scanin = i_dff_fmem0_scanout;
	assign i_dff_qual_atomic_d1_scanin = i_dff_reqreg_scanout;
	assign scan_out_prebuf = i_dff_qual_atomic_d1_scanout;

	buff_macro__dbuff_16x__stack_none__width_4 i_buf_hfn(
		.din				({tcu_pce_ov, tcu_scan_en,
		ccx_aclk, ccx_bclk}), 
		.dout				({tcu_pce_ov_out,
		tcu_scan_en_out, ccx_aclk_out, ccx_bclk_out}));
	msff_macro__dmsff_16x__stack_10c__width_10 i_dff_atom_a(
		.scan_in			(i_dff_atom_a_scanin), 
		.scan_out			(i_dff_atom_a_scanout), 
		.clk				(l2clk), 
		.din				({direction_, atom_q[8:0]}), 
		.dout				({dir_a_, atom_int_a[8:0]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__dmsff_16x__stack_10c__width_10 i_dff_req_a(
		.scan_in			(i_dff_req_a_scanin), 
		.scan_out			(i_dff_req_a_scanout), 
		.clk				(l2clk), 
		.din				({direction, req_q[8:0]}), 
		.dout				({dir_a, req_a[8:0]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	nand_macro__dnand_1x__ports_2__stack_10c__width_9 i_nand_inreq_a(
		.din0				(qfullbar_a[8:0]), 
		.din1				(req_a[8:0]), 
		.dout				(input_req_a_[8:0]));
	inv_macro__dinv_24x__stack_10c__width_10 i_inv_inreq_a(
		.din				({direction,
		input_req_a_[8:0]}), 
		.dout				({direction_, input_req_a[8:0]})
		);
	buff_macro__dbuff_32x__minbuff_1__stack_none__width_19 i_buf_fifo_wdata(
		.din				({atom_int_a[8:0],
		fifo_wdata_prebuf[9:0]}), 
		.dout				({atom_a[8:0], fifo_wdata[9:0]})
		);
	msff_macro__stack_10c__width_10 i_dff_fmem17(
		.scan_in			(i_dff_fmem17_scanin), 
		.scan_out			(i_dff_fmem17_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata17[9:0]), 
		.en				(write_fifo_a[17]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem16(
		.scan_in			(i_dff_fmem16_scanin), 
		.scan_out			(i_dff_fmem16_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata16[9:0]), 
		.en				(write_fifo_a[16]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	mux_macro__dbuff_8x__dmux_4x__mux_aope__ports_2__stack_10c__width_10 
		i_mux_fmem17_16(
		.din0				(fifo_rdata17[9:0]), 
		.din1				(fifo_rdata16[9:0]), 
		.sel0				(fifo_rptr_a[0]), 
		.dout				(fifo_rdata17_16[9:0]));
	msff_macro__stack_10c__width_10 i_dff_fmem15(
		.scan_in			(i_dff_fmem15_scanin), 
		.scan_out			(i_dff_fmem15_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata15[9:0]), 
		.en				(write_fifo_a[15]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem14(
		.scan_in			(i_dff_fmem14_scanin), 
		.scan_out			(i_dff_fmem14_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata14[9:0]), 
		.en				(write_fifo_a[14]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem13(
		.scan_in			(i_dff_fmem13_scanin), 
		.scan_out			(i_dff_fmem13_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata13[9:0]), 
		.en				(write_fifo_a[13]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem12(
		.scan_in			(i_dff_fmem12_scanin), 
		.scan_out			(i_dff_fmem12_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata12[9:0]), 
		.en				(write_fifo_a[12]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem11(
		.scan_in			(i_dff_fmem11_scanin), 
		.scan_out			(i_dff_fmem11_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata11[9:0]), 
		.en				(write_fifo_a[11]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem10(
		.scan_in			(i_dff_fmem10_scanin), 
		.scan_out			(i_dff_fmem10_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata10[9:0]), 
		.en				(write_fifo_a[10]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem9(
		.scan_in			(i_dff_fmem9_scanin), 
		.scan_out			(i_dff_fmem9_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata9[9:0]), 
		.en				(write_fifo_a[9]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem8(
		.scan_in			(i_dff_fmem8_scanin), 
		.scan_out			(i_dff_fmem8_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata8[9:0]), 
		.en				(write_fifo_a[8]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	mux_macro__dbuff_8x__dmux_4x__mux_aodec__ports_8__stack_10c__width_10 
		i_mux_fmem15_8(
		.din0				(fifo_rdata8[9:0]), 
		.din1				(fifo_rdata9[9:0]), 
		.din2				(fifo_rdata10[9:0]), 
		.din3				(fifo_rdata11[9:0]), 
		.din4				(fifo_rdata12[9:0]), 
		.din5				(fifo_rdata13[9:0]), 
		.din6				(fifo_rdata14[9:0]), 
		.din7				(fifo_rdata15[9:0]), 
		.sel				(fifo_rptr_a[2:0]), 
		.dout				(fifo_rdata15_8[9:0]));
	msff_macro__stack_10c__width_10 i_dff_fmem7(
		.scan_in			(i_dff_fmem7_scanin), 
		.scan_out			(i_dff_fmem7_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata7[9:0]), 
		.en				(write_fifo_a[7]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem6(
		.scan_in			(i_dff_fmem6_scanin), 
		.scan_out			(i_dff_fmem6_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata6[9:0]), 
		.en				(write_fifo_a[6]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem5(
		.scan_in			(i_dff_fmem5_scanin), 
		.scan_out			(i_dff_fmem5_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata5[9:0]), 
		.en				(write_fifo_a[5]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem4(
		.scan_in			(i_dff_fmem4_scanin), 
		.scan_out			(i_dff_fmem4_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata4[9:0]), 
		.en				(write_fifo_a[4]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem3(
		.scan_in			(i_dff_fmem3_scanin), 
		.scan_out			(i_dff_fmem3_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata3[9:0]), 
		.en				(write_fifo_a[3]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem2(
		.scan_in			(i_dff_fmem2_scanin), 
		.scan_out			(i_dff_fmem2_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata2[9:0]), 
		.en				(write_fifo_a[2]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem1(
		.scan_in			(i_dff_fmem1_scanin), 
		.scan_out			(i_dff_fmem1_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata1[9:0]), 
		.en				(write_fifo_a[1]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msff_macro__stack_10c__width_10 i_dff_fmem0(
		.scan_in			(i_dff_fmem0_scanin), 
		.scan_out			(i_dff_fmem0_scanout), 
		.clk				(l2clk), 
		.din				(fifo_wdata[9:0]), 
		.dout				(fifo_rdata0[9:0]), 
		.en				(write_fifo_a[0]), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	mux_macro__dbuff_8x__dmux_4x__mux_aodec__ports_8__stack_10c__width_10 
		i_mux_fmem7_0(
		.din0				(fifo_rdata0[9:0]), 
		.din1				(fifo_rdata1[9:0]), 
		.din2				(fifo_rdata2[9:0]), 
		.din3				(fifo_rdata3[9:0]), 
		.din4				(fifo_rdata4[9:0]), 
		.din5				(fifo_rdata5[9:0]), 
		.din6				(fifo_rdata6[9:0]), 
		.din7				(fifo_rdata7[9:0]), 
		.sel				(fifo_rptr_a[2:0]), 
		.dout				(fifo_rdata7_0[9:0]));
	mux_macro__dmux_1x__mux_aodec__ports_4__stack_10c__width_10 
		i_mux_fifo_req(
		.din0				(fifo_rdata7_0[9:0]), 
		.din1				(fifo_rdata15_8[9:0]), 
		.din2				(fifo_rdata17_16[9:0]), 
		.din3				(fifo_wdata[9:0]), 
		.sel				({fifo_read_select[1:0]}), 
		.dout				({fifo_dir, fifo_req[8:0]}));
	mux_macro__dmux_1x__mux_aonpe__ports_2__stack_10c__width_10 i_mux_reqmux
		(
		.din0				({qual_dir, qual_req[8:0]}), 
		.din1				({fifo_dir, fifo_req[8:0]}), 
		.sel0				(current_req_sel_a), 
		.sel1				(fifo_req_sel_a), 
		.dout				({fq_dir, fq_req[8:0]}));
	msff_macro__stack_10c__width_10 i_dff_reqreg(
		.scan_in			(i_dff_reqreg_scanin), 
		.scan_out			(i_dff_reqreg_scanout), 
		.clk				(l2clk), 
		.din				({fq_dir, fq_req[8:0]}), 
		.dout				({fq_dir_a_prebuf,
		fq_req_a[8:0]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	buff_macro__dbuff_8x__stack_10c__width_1 i_buf_fqdir(
		.din				(fq_dir_a_prebuf), 
		.dout				(fq_dir_a));
	nand_macro__dnand_4x__ports_3__stack_10c__width_10 i_nand3i_inmux(
		.din0				({dir_a, req_a[8:0]}), 
		.din1				({1'b1, qfullbar_a[8:0]}), 
		.din2				({10 {input_req_sel_a}}), 
		.dout				({input_dir_a_,
		input_req_qfullbar_a_[8:0]}));
	nand_macro__dnand_4x__ports_2__stack_10c__width_10 i_nand2i_inmux(
		.din0				({fq_dir_a, fq_req_a[8:0]}), 
		.din1				({10 {input_req_sel_a_}}), 
		.dout				({fq_input_dir_a_,
		fq_input_req_a_[8:0]}));
	nand_macro__dnand_12x__ports_2__stack_10c__width_10 i_nand2o_inmux(
		.din0				({input_dir_a_,
		input_req_qfullbar_a_[8:0]}), 
		.din1				({fq_input_dir_a_,
		fq_input_req_a_[8:0]}), 
		.dout				({dir, req[8:0]}));
	nand_macro__dnand_1x__ports_2__stack_10c__width_9 i_nand_atomreq(
		.din0				(atom_int_a[8:0]), 
		.din1				(input_req_a[8:0]), 
		.dout				(atom_req_a_[8:0]));
	inv_macro__dinv_2x__stack_10c__width_9 i_inv_atomreq(
		.din				(atom_req_a_[8:0]), 
		.dout				(atom_req_a[8:0]));
	mux_macro__dmux_8x__mux_aope__ports_2__stack_10c__width_9 i_mux_atom(
		.din0				(atom_req_a[8:0]), 
		.din1				(atom_x[8:0]), 
		.sel0				(input_req_sel_a), 
		.dout				(atom[8:0]));
	nand_macro__dnand_4x__ports_3__stack_10c__width_1 i_nand3_dira_inmux(
		.din0				(dir_a), 
		.din1				(stall_a_), 
		.din2				(input_req_sel_a), 
		.dout				(input_dira_stall_));
	nand_macro__dnand_4x__ports_3__stack_10c__width_1 i_nand3_fq_dira_inmux(
		.din0				(fq_dir_a), 
		.din1				(stall_a_), 
		.din2				(input_req_sel_a_), 
		.dout				(fq_input_dira_stall_));
	nand_macro__dnand_12x__ports_2__stack_10c__width_1 i_nand2o_dira_inmux(
		.din0				(input_dira_stall_), 
		.din1				(fq_input_dira_stall_), 
		.dout				(dira));
	inv_macro__dinv_4x__stack_10c__width_1 i_inv_dir(
		.din				({fq_dir_a}), 
		.dout				({fq_dir_a_}));
	nand_macro__dnand_4x__ports_3__stack_10c__width_1 i_nand3_dird_inmux(
		.din0				(dir_a_), 
		.din1				(stall_a_), 
		.din2				(input_req_sel_a), 
		.dout				(input_dird_stall_));
	nand_macro__dnand_4x__ports_3__stack_10c__width_1 i_nand3_fq_dird_inmux(
		.din0				(fq_dir_a_), 
		.din1				(stall_a_), 
		.din2				(input_req_sel_a_), 
		.dout				(fq_input_dird_stall_));
	nand_macro__dnand_12x__ports_2__stack_10c__width_1 i_nand2o_dird_inmux(
		.din0				(input_dird_stall_), 
		.din1				(fq_input_dird_stall_), 
		.dout				(dird));
	inv_macro__dinv_12x__stack_10c__width_9 i_ainv_1_w9(
		.din				({req[8:0]}), 
		.dout				({r8_, r7_, r6_, r5_, r4_, r3_,
		r2_, r1_, r0_}));
	and_macro__dinv_12x__dnand_4x__ports_4__stack_10c__width_2 i_aand4_1_w2(
		.din0				({r4_, r0_}), 
		.din1				({r5_, r1_}), 
		.din2				({r6_, r2_}), 
		.din3				({r7_, r3_}), 
		.dout				({ra_or_7654_, ra_or_3210_}));
	and_macro__dinv_8x__dnand_2x__ports_3__stack_10c__width_4 i_aand3_1_w4(
		.din0				({r4_, r4_, r4_, r0_}), 
		.din1				({r5_, req[5], r5_, r1_}), 
		.din2				({r6_, dira, r3_, r2_}), 
		.dout				({ra_or_654_, ra_d54x,
		ra_or_543_, ra_or_210_}));
	nor_macro__dnor_8x__ports_2__stack_10c__width_3 i_anor2_1_w3(
		.din0				({req[2], req[2], req[0]}), 
		.din1				({req[3], req[1], req[1]}), 
		.dout				({ra_or_32_, ra_or_21_,
		ra_or_10_}));
	nand_macro__dnand_2x__ports_2__stack_10c__width_5 i_anand2_1_w5(
		.din0				({dira, dira, dira, dira,
		dira}), 
		.din1				({req[8], req[7], req[6],
		req[4], req[3]}), 
		.dout				({ra_d8_, ra_d7_, ra_d6_,
		ra_d4_, ra_d3_}));
	nand_macro__dnand_8x__ports_2__stack_10c__width_1 i_anand2_2_w1(
		.din0				({dira}), 
		.din1				({req[0]}), 
		.dout				({grant_asc_[0]}));
	inv_macro__dinv_4x__stack_10c__width_5 i_ainv_2_w5(
		.din				({ra_d8_, ra_d7_, ra_d6_,
		ra_d4_, ra_d3_}), 
		.dout				({ra_d8, ra_d7, ra_d6, ra_d4,
		ra_d3}));
	nand_macro__dnand_8x__ports_3__stack_10c__width_8 i_anand3_2_w8(
		.din0				({ra_or_3210_, ra_or_3210_,
		ra_or_210_, ra_or_10_, ra_or_10_, r0_, ra_or_10_, r0_}), 
		.din1				({ra_or_7654_, ra_or_654_,
		ra_or_543_, ra_or_32_, ra_or_32_, ra_or_21_, req[2], req[1]}), 
		.din2				({ra_d8, ra_d7, ra_d6, ra_d54x,
		ra_d4, ra_d3, dira, dira}), 
		.dout				(grant_asc_[8:1]));
	and_macro__dinv_12x__dnand_4x__ports_4__stack_10c__width_2 i_dand4_1_w2(
		.din0				({rd4_, rd0_}), 
		.din1				({rd5_, rd1_}), 
		.din2				({rd6_, rd2_}), 
		.din3				({rd7_, rd3_}), 
		.dout				({rd_or_7654_, rd_or_3210_}));
	and_macro__dinv_8x__dnand_2x__ports_3__stack_10c__width_4 i_dand3_1_w4(
		.din0				({rd4_, rd4_, rd4_, rd0_}), 
		.din1				({rd5_, reqd[5], rd5_, rd1_}), 
		.din2				({rd6_, dird, rd3_, rd2_}), 
		.dout				({rd_or_654_, rd_d54x,
		rd_or_543_, rd_or_210_}));
	nor_macro__dnor_8x__ports_2__stack_10c__width_3 i_dnor2_1_w3(
		.din0				({reqd[2], reqd[2], reqd[0]}), 
		.din1				({reqd[3], reqd[1], reqd[1]}), 
		.dout				({rd_or_32_, rd_or_21_,
		rd_or_10_}));
	nand_macro__dnand_2x__ports_2__stack_10c__width_5 i_dnand2_1_w5(
		.din0				({dird, dird, dird, dird,
		dird}), 
		.din1				({reqd[8], reqd[7], reqd[6],
		reqd[4], reqd[3]}), 
		.dout				({rd_d8_, rd_d7_, rd_d6_,
		rd_d4_, rd_d3_}));
	nand_macro__dnand_8x__ports_2__stack_10c__width_1 i_dnand2_2_w1(
		.din0				({dird}), 
		.din1				({reqd[0]}), 
		.dout				({grant_dsc_[0]}));
	inv_macro__dinv_4x__stack_10c__width_5 i_dinv_2_w5(
		.din				({rd_d8_, rd_d7_, rd_d6_,
		rd_d4_, rd_d3_}), 
		.dout				({rd_d8, rd_d7, rd_d6, rd_d4,
		rd_d3}));
	nand_macro__dnand_8x__ports_3__stack_10c__width_8 i_dnand3_2_w8(
		.din0				({rd_or_3210_, rd_or_3210_,
		rd_or_210_, rd_or_10_, rd_or_10_, rd0_, rd_or_10_, rd0_}), 
		.din1				({rd_or_7654_, rd_or_654_,
		rd_or_543_, rd_or_32_, rd_or_32_, rd_or_21_, reqd[2], reqd[1]}),
		.din2				({rd_d8, rd_d7, rd_d6, rd_d54x,
		rd_d4, rd_d3, dird, dird}), 
		.dout				(grant_dsc_[8:1]));
	nand_macro__dnand_32x__ports_2__stack_10c__width_9 i_nand_dirmux(
		.din0				(grant_asc_[8:0]), 
		.din1				(grant_des_[8:0]), 
		.dout				(grant_int_a[8:0]));
	buff_macro__dbuff_48x__stack_10c__width_9 i_buf_src_grant(
		.din				(grant_int_a[8:0]), 
		.dout				({arb_src8_grant_a,
		arb_src7_grant_a, arb_src6_grant_a, arb_src5_grant_a,
		arb_src4_grant_a, arb_src3_grant_a, arb_src2_grant_a,
		arb_src1_grant_a, arb_src0_grant_a}));
	buff_macro__dbuff_32x__stack_10c__width_9 i_buf_queue_grant(
		.din				(grant_int_a[8:0]), 
		.dout				(arb_grant_a[8:0]));
	buff_macro__dbuff_16x__minbuff_1__stack_10c__width_9 i_bufmin_grant(
		.din				(grant_int_a[8:0]), 
		.dout				(grant_a[8:0]));
	inv_macro__dinv_8x__stack_10c__width_9 i_inv_grant_a_x(
		.din				(grant_int_a[8:0]), 
		.dout				(grant_a_[8:0]));
	nand_macro__dnand_1x__ports_3__stack_10c__width_9 i_nand_set_qualatom(
		.din0				(atom[8:0]), 
		.din1				(grant_int_a[8:0]), 
		.din2				(qual_atomic_d1_[8:0]), 
		.dout				(set_qual_atomic[8:0]));
	nand_macro__dnand_1x__ports_2__stack_10c__width_9 i_nand_hold_qualatom(
		.din0				(grant_a_[8:0]), 
		.din1				(qual_atomic_d1[8:0]), 
		.dout				(hold_qual_atomic[8:0]));
	nand_macro__dnand_1x__ports_2__stack_10c__width_10 i_nand_qual_atomic(
		.din0				({stall_q_d1,
		set_qual_atomic[8:0]}), 
		.din1				({1'b1, hold_qual_atomic[8:0]}),
		.dout				({stall_q_d1_,
		qual_atomic[8:0]}));
	msff_macro__dmsff_8x__stack_10c__stack_10c__width_10 
		i_dff_qual_atomic_d1(
		.scan_in			(i_dff_qual_atomic_d1_scanin), 
		.scan_out			(i_dff_qual_atomic_d1_scanout), 
		.clk				(l2clk), 
		.din				({stall_q_d1_,
		qual_atomic[8:0]}), 
		.dout				({stall_a_,
		qual_atomic_d1[8:0]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	inv_macro__dinv_2x__stack_10c__width_9 i_inv_qual_atomic_d1_x(
		.din				(qual_atomic_d1[8:0]), 
		.dout				(qual_atomic_d1_[8:0]));
	nand_macro__dnand_2x__ports_2__stack_10c__width_9 i_nand_req_nogrant(
		.din0				(req[8:0]), 
		.din1				(grant_a_[8:0]), 
		.dout				(req_nogrant_[8:0]));
	nand_macro__dnand_4x__ports_3__stack_10c__width_9 i_nand_set_qualatom2(
		.din0				(atom[8:0]), 
		.din1				(grant_int_a[8:0]), 
		.din2				(qual_atomic_d1_[8:0]), 
		.dout				(atom_2pass_[8:0]));
	nand_macro__dnand_8x__ports_2__stack_10c__width_9 i_nand_qual_req(
		.din0				(req_nogrant_[8:0]), 
		.din1				(atom_2pass_[8:0]), 
		.dout				(qual_req[8:0]));
	nor_macro__dnor_4x__ports_3__stack_10c__width_6 i_nor_rpe(
		.din0				({qual_req[8], qual_req[5],
		qual_req[2], grant_int_a[8], grant_int_a[5], grant_int_a[2]}), 
		.din1				({qual_req[7], qual_req[4],
		qual_req[1], grant_int_a[7], grant_int_a[4], grant_int_a[1]}), 
		.din2				({qual_req[6], qual_req[3],
		qual_req[0], grant_int_a[6], grant_int_a[3], grant_int_a[0]}), 
		.dout				({qreq_8_6_, qreq_5_3_,
		qreq_2_0_, drdy_8_6, drdy_5_3, drdy_2_0}));
	nand_macro__dnand_8x__ports_3__stack_10c__width_2 i_nand_rpe(
		.din0				({qreq_8_6_, drdy_8_6}), 
		.din1				({qreq_5_3_, drdy_5_3}), 
		.din2				({qreq_2_0_, drdy_2_0}), 
		.dout				({req_pkt_empty_a_, data_rdy_a})
		);
	inv_macro__dinv_32x__stack_10c__width_1 i_inv_rpe(
		.din				(req_pkt_empty_a_), 
		.dout				(req_pkt_empty_a));
	buff_macro__dbuff_32x__stack_none__width_1 buff_drdy(
		.din				(data_rdy_a), 
		.dout				(ccx_dest_data_rdy_a));
	nand_macro__dnand_1x__ports_3__stack_10c__width_3 i_nand_atom(
		.din0				({atom_2pass_[8],
		atom_2pass_[5], atom_2pass_[2]}), 
		.din1				({atom_2pass_[7],
		atom_2pass_[4], atom_2pass_[1]}), 
		.din2				({atom_2pass_[6],
		atom_2pass_[3], atom_2pass_[0]}), 
		.dout				({atom_8_6, atom_5_3, atom_2_0})
		);
	nor_macro__dnor_4x__ports_3__stack_10c__width_1 i_nor_atom(
		.din0				(atom_8_6), 
		.din1				(atom_5_3), 
		.din2				(atom_2_0), 
		.dout				(ccx_dest_atom_a_));
	inv_macro__dinv_32x__stack_10c__width_1 i_inv_dest_atom(
		.din				(ccx_dest_atom_a_), 
		.dout				(ccx_dest_atom_a));
	buff_macro__dbuff_8x__stack_none__width_1 buff_scanout(
		.din				(scan_out_prebuf), 
		.dout				(scan_out));
endmodule

`ifdef FPGA
`else

`celldefine
module inv_macro__dinv_32x__stack_10c__width_1(din, dout);

        input   [0:0]           din;
        output  [0:0]           dout;

        inv #(1) d0_0(
                .in                             (din[0]),
                .out                            (dout[0]));
endmodule
`endcelldefine

module msff_macro__dmsff_8x__stack_10c__stack_10c__width_10(din, clk, en, se,
        scan_in, siclk, soclk, pce_ov, stop, dout, scan_out);

        input   [9:0]           din;
        input                   clk;
        input                   en;
        input                   se;
        input                   scan_in;
        input                   siclk;
        input                   soclk;
        input                   pce_ov;
        input                   stop;
        output  [9:0]           dout;
        output                  scan_out;

        wire                    l1clk;
        wire                    siclk_out;
        wire                    soclk_out;
        wire    [8:0]           so;

        cl_dp1_l1hdr_8x c0_0(
                .l2clk                          (clk),
                .pce                            (en),
                .aclk                           (siclk),
                .bclk                           (soclk),
                .l1clk                          (l1clk),
                .se                             (se),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out));
        dff #(10) d0_0(
                .l1clk                          (l1clk),
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .d                              (din[9:0]),
                .si                             ({scan_in, so[8:0]}),
                .so                             ({so[8:0], scan_out}),
                .q                              (dout[9:0]));
endmodule

`celldefine
module nor_macro__dnor_4x__ports_3__stack_10c__width_1(din0, din1, din2, dout);

        input   [0:0]           din0;
        input   [0:0]           din1;
        input   [0:0]           din2;
        output  [0:0]           dout;

        nor3 #(1) d0_0(
                .in0                            (din0[0]),
                .in1                            (din1[0]),
                .in2                            (din2[0]),
                .out                            (dout[0]));
endmodule
`endcelldefine

`celldefine
module inv_macro__dinv_32x__stack_10c__width_1(din, dout);

        input   [0:0]           din;
        output  [0:0]           dout;

        inv #(1) d0_0(
                .in                             (din[0]),
                .out                            (dout[0]));
endmodule
`endcelldefine

`endif  // ifdef FPGA


`endif // `ifdef FPGA
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx_rep.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ccx_rep (
  rep_out, 
  rep_in);

output [11:0] rep_out;

input [11:0]  rep_in;

cl_dp1_rep_m6_32x i0(
                  .in (rep_in[0]),
                  .out(rep_out[0]));

cl_dp1_rep_m6_32x i1(
                  .in (rep_in[1]),
                  .out(rep_out[1]));

cl_dp1_rep_m6_32x i2(
                  .in (rep_in[2]),
                  .out(rep_out[2]));

cl_dp1_rep_m6_32x i3(
                  .in (rep_in[3]),
                  .out(rep_out[3]));

cl_dp1_rep_m6_32x i4(
                  .in (rep_in[4]),
                  .out(rep_out[4]));

cl_dp1_rep_m6_32x i5(
                  .in (rep_in[5]),
                  .out(rep_out[5]));

cl_dp1_rep_m6_32x i6(
                  .in (rep_in[6]),
                  .out(rep_out[6]));

cl_dp1_rep_m6_32x i7(
                  .in (rep_in[7]),
                  .out(rep_out[7]));

cl_dp1_rep_m6_32x i8(
                  .in (rep_in[8]),
                  .out(rep_out[8]));

cl_dp1_rep_m6_32x i9(
                  .in (rep_in[9]),
                  .out(rep_out[9]));

cl_dp1_rep_m6_32x i10(
                  .in (rep_in[10]),
                  .out(rep_out[10]));

cl_dp1_rep_m6_32x i11(
                  .in (rep_in[11]),
                  .out(rep_out[11]));


endmodule // ccx_rep


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx_srq_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module ccx_srq_ctl (
  qfull_a, 
  qfullbar_a, 
  qsel0_a, 
  qsel1_a, 
  shift_a, 
  q0_holdbar_a, 
  atom_x, 
  req_a, 
  atom_a, 
  grant_a, 
  l1clk, 
  scan_in, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire siclk;
wire soclk;
wire dff_grant_x_scanin;
wire dff_grant_x_scanout;
wire grant_x;
wire atom_rq_a;
wire atom_rq_x;
wire dff_atom_rq_x_scanin;
wire dff_atom_rq_x_scanout;
wire dff_qfull_a_scanin;
wire dff_qfull_a_scanout;
wire qfull;
wire req_new;
wire v0_in;
wire v0;
wire v1;
wire v1_in;
wire qfullbar;
wire dff_v0_scanin;
wire dff_v0_scanout;
wire dff_v1_scanin;
wire dff_v1_scanout;
wire dff_qfullbar_a_scanin;
wire dff_qfullbar_a_scanout;
wire av0_in;
wire av0;
wire av1;
wire av1_in;
wire aqsel0_a;
wire aqsel1_a;
wire ashift_a;
wire dff_av0_scanin;
wire dff_av0_scanout;
wire dff_av1_scanin;
wire dff_av1_scanout;
wire atom1_in;
wire atom1;
wire dff_atom1_scanin;
wire dff_atom1_scanout;
wire atom0_in;
wire atom0;
wire dff_atom0_scanin;
wire dff_atom0_scanout;

 
output	qfull_a;
output	qfullbar_a;
output	qsel0_a;
output	qsel1_a;
output	shift_a;
output	q0_holdbar_a;
output	atom_x;
   
input	req_a;
input	atom_a;
input	grant_a;
 
//Globals
input           l1clk;
input           scan_in;
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

// scan renames
assign siclk = ccx_aclk;
assign soclk = ccx_bclk;
// end scan


// latch the grant
// grant is generated in the same cycle as req_a.
// The data corresponding to the grant is consumed from the queues
// in next cycle. grant_x is used to update the FIFO.
ccx_srq_ctl_msff_ctl_macro dff_grant_x  
  (
   .scan_in(dff_grant_x_scanin),
   .scan_out(dff_grant_x_scanout),
   .din           (grant_a),
   .dout          (grant_x),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
   );


// set up state to detect an atomic request and hold it until queue stays
// full. The atomic requests are guaranteed to be back-to-back.
// On PCX, an atomic req will not be made unless queue  is empty.
// On CPX, L2 can make the req when queue is not full (it need not be empty). 
// In this case atom_rq_a will get set after the first packet is accepted. It will
// stay set until the queue remains full. When the queue goes not full, the
// next packet (second part of the atomic req) will  get accepted and a req
// will be generated for it. At the same time atom_rq_a will be cleared.
// 
// ideally the setting should be qualified with !qfull, but it is not needed
// since design guarantees that LSU and L2 will not make an atomic request
// unless the queue is not full.

//assign atom_rq_a = atom_a & req_a | atom_rq_x & qfull_a;
assign atom_rq_a = atom_a & req_a & ~qfull_a | atom_rq_x & qfull_a;

ccx_srq_ctl_msff_ctl_macro dff_atom_rq_x  
  (
   .scan_in(dff_atom_rq_x_scanin),
   .scan_out(dff_atom_rq_x_scanout),
   .din           (atom_rq_a),
   .dout          (atom_rq_x),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

ccx_srq_ctl_msff_ctl_macro dff_qfull_a
  (
   .scan_in(dff_qfull_a_scanin),
   .scan_out(dff_qfull_a_scanout),
   .din           (qfull),
   .dout          (qfull_a),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// req_new indicates that a valid request is presented with FIFO not full.
assign req_new = (atom_rq_x | req_a) & ~qfull_a;

// v0 and v1 are the valids for queue entries q0 and q1
//
// v1_in does not include the term (v1 & v0 & req_new & grant_x) 
// because with v1 set, the queue would be full.
// No new requests can be accepted if v1 is set. This is because the source
// continues to drive the request until the cycle after grant_x. Accepting
// a request in the cycle of grant_x will result in same request being
// latched twice in the FIFO.

assign v0_in = ((~v0 & req_new) | (v0 & req_new & grant_x) | (v1 & grant_x) | (v0 & ~grant_x));
assign v1_in = ((v0 & req_new & ~grant_x) | (v1 & ~grant_x));


// qsel0 is the mux select which loads incoming new data into q0
// shift_a is the mux select whicl loads q1 data into q0
// qsel1 is the enable for q1
// speed these up by using earlier versions of the signals
//assign qsel0 = (~v0 & req_new) | (v0 & req_new & grant_x) 
//             = req_new & (~v0 | v0 & grant_x) 
//             = req_new & (~v0 | grant_x);
assign qsel0_a = req_new & (~v0 | grant_x);
assign shift_a = v1 & grant_x;
assign q0_holdbar_a = ~(~qsel0_a & ~shift_a);

assign qsel1_a = v0 & req_new & ~grant_x;
assign qfull = v1_in;
assign qfullbar = ~v1_in;

ccx_srq_ctl_msff_ctl_macro dff_v0
  (
   .scan_in(dff_v0_scanin),
   .scan_out(dff_v0_scanout),
   .din           (v0_in),
   .dout             (v0),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
ccx_srq_ctl_msff_ctl_macro dff_v1
  (
   .scan_in(dff_v1_scanin),
   .scan_out(dff_v1_scanout),
   .din           (v1_in),
   .dout             (v1),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

ccx_srq_ctl_msff_ctl_macro dff_qfullbar_a
  (
   .scan_in(dff_qfullbar_a_scanin),
   .scan_out(dff_qfullbar_a_scanout),
   .din           (qfullbar),
   .dout          (qfullbar_a),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Atomic flag tracking
// Should place this in the dp FIFO.

// This queue has different timing then the data queue
// The atomic request indicator comes one cycle earlier than data, along with the request.
// Also, on a "grant", the queue shifts very next cycle.

// ideally this should be:
// the term (~av0 & req_new & ~grant_a) allows for the fact that if a grant_a comes with ~av0 & req_new, then the
// request does not get latched in the FIFO. Basically in this case, the arbiter processes the request directly out
// of the input register.
assign av0_in = ((~av0 & req_new & ~grant_a) | (av0 & ~av1 & req_new & grant_a) | (av1 & grant_a) | (av0 & ~grant_a));
assign av1_in = ((av0 & req_new & ~grant_a) | (av1 & ~grant_a));

assign aqsel0_a = (req_new &  ~av0 ) | (req_new & av0 &  ~av1 & grant_a);	
assign aqsel1_a = (req_new & av0  &  ~grant_a);

assign ashift_a = av1 & grant_a;

ccx_srq_ctl_msff_ctl_macro dff_av0
  (
   .scan_in(dff_av0_scanin),
   .scan_out(dff_av0_scanout),
   .din           (av0_in),
   .dout             (av0),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
ccx_srq_ctl_msff_ctl_macro dff_av1
  (
   .scan_in(dff_av1_scanin),
   .scan_out(dff_av1_scanout),
   .din           (av1_in),
   .dout             (av1),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign atom1_in = (aqsel1_a  & atom_a) | (~aqsel1_a & atom1);	

ccx_srq_ctl_msff_ctl_macro dff_atom1   (
	.scan_in(dff_atom1_scanin),
	.scan_out(dff_atom1_scanout),
	.din           (atom1_in),
	.dout          (atom1),
	.l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign atom0_in = (aqsel0_a  & atom_a) | (ashift_a & atom1) | (~aqsel0_a &  ~ ashift_a & atom0);	

ccx_srq_ctl_msff_ctl_macro dff_atom0   (
	.scan_in(dff_atom0_scanin),
	.scan_out(dff_atom0_scanout),
	.din           (atom0_in),
	.dout          (atom0),
	.l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign atom_x = atom0;

// fixscan start:
assign dff_grant_x_scanin        = scan_in                  ;
assign dff_atom_rq_x_scanin      = dff_grant_x_scanout      ;
assign dff_qfull_a_scanin        = dff_atom_rq_x_scanout    ;
assign dff_v0_scanin             = dff_qfull_a_scanout      ;
assign dff_v1_scanin             = dff_v0_scanout           ;
assign dff_qfullbar_a_scanin     = dff_v1_scanout           ;
assign dff_av0_scanin            = dff_qfullbar_a_scanout   ;
assign dff_av1_scanin            = dff_av0_scanout          ;
assign dff_atom1_scanin          = dff_av1_scanout          ;
assign dff_atom0_scanin          = dff_atom1_scanout        ;
assign scan_out                  = dff_atom0_scanout        ;
// fixscan end:
endmodule 


// any PARAMS parms go into naming of macro

module ccx_srq_ctl_msff_ctl_macro (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
// No timescale specified
module ccx_srq_ctl(qfull_a, qfullbar_a, qsel0_a, qsel1_a, shift_a, q0_holdbar_a,
	atom_x, req_a, atom_a, grant_a, l1clk, scan_in, ccx_aclk, ccx_bclk, 
	scan_out);

	output			qfull_a;
	output			qfullbar_a;
	output			qsel0_a;
	output			qsel1_a;
	output			shift_a;
	output			q0_holdbar_a;
	output			atom_x;
	input			req_a;
	input			atom_a;
	input			grant_a;
	input			l1clk;
	input			scan_in;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire			siclk;
	wire			soclk;
	wire			dff_grant_x_scanin;
	wire			dff_grant_x_scanout;
	wire			grant_x;
	wire			atom_rq_a;
	wire			atom_rq_x;
	wire			dff_atom_rq_x_scanin;
	wire			dff_atom_rq_x_scanout;
	wire			dff_qfull_a_scanin;
	wire			dff_qfull_a_scanout;
	wire			qfull;
	wire			req_new;
	wire			v0_in;
	wire			v0;
	wire			v1;
	wire			v1_in;
	wire			qfullbar;
	wire			dff_v0_scanin;
	wire			dff_v0_scanout;
	wire			dff_v1_scanin;
	wire			dff_v1_scanout;
	wire			dff_qfullbar_a_scanin;
	wire			dff_qfullbar_a_scanout;
	wire			av0_in;
	wire			av0;
	wire			av1;
	wire			av1_in;
	wire			aqsel0_a;
	wire			aqsel1_a;
	wire			ashift_a;
	wire			dff_av0_scanin;
	wire			dff_av0_scanout;
	wire			dff_av1_scanin;
	wire			dff_av1_scanout;
	wire			atom1_in;
	wire			atom1;
	wire			dff_atom1_scanin;
	wire			dff_atom1_scanout;
	wire			atom0_in;
	wire			atom0;
	wire			dff_atom0_scanin;
	wire			dff_atom0_scanout;

	assign siclk = ccx_aclk;
	assign soclk = ccx_bclk;
	assign atom_rq_a = (((atom_a & req_a) & (~qfull_a)) | (atom_rq_x & 
		qfull_a));
	assign req_new = ((atom_rq_x | req_a) & (~qfull_a));
	assign v0_in = (((((~v0) & req_new) | ((v0 & req_new) & grant_x)) | (v1 
		& grant_x)) | (v0 & (~grant_x)));
	assign v1_in = (((v0 & req_new) & (~grant_x)) | (v1 & (~grant_x)));
	assign qsel0_a = (req_new & ((~v0) | grant_x));
	assign shift_a = (v1 & grant_x);
	assign q0_holdbar_a = (~((~qsel0_a) & (~shift_a)));
	assign qsel1_a = ((v0 & req_new) & (~grant_x));
	assign qfull = v1_in;
	assign qfullbar = (~v1_in);
	assign av0_in = ((((((~av0) & req_new) & (~grant_a)) | (((av0 & (~av1)) 
		& req_new) & grant_a)) | (av1 & grant_a)) | (av0 & (~grant_a)));
	assign av1_in = (((av0 & req_new) & (~grant_a)) | (av1 & (~grant_a)));
	assign aqsel0_a = ((req_new & (~av0)) | (((req_new & av0) & (~av1)) & 
		grant_a));
	assign aqsel1_a = ((req_new & av0) & (~grant_a));
	assign ashift_a = (av1 & grant_a);
	assign atom1_in = ((aqsel1_a & atom_a) | ((~aqsel1_a) & atom1));
	assign atom0_in = (((aqsel0_a & atom_a) | (ashift_a & atom1)) | (((~
		aqsel0_a) & (~ashift_a)) & atom0));
	assign atom_x = atom0;
	assign dff_grant_x_scanin = scan_in;
	assign dff_atom_rq_x_scanin = dff_grant_x_scanout;
	assign dff_qfull_a_scanin = dff_atom_rq_x_scanout;
	assign dff_v0_scanin = dff_qfull_a_scanout;
	assign dff_v1_scanin = dff_v0_scanout;
	assign dff_qfullbar_a_scanin = dff_v1_scanout;
	assign dff_av0_scanin = dff_qfullbar_a_scanout;
	assign dff_av1_scanin = dff_av0_scanout;
	assign dff_atom1_scanin = dff_av1_scanout;
	assign dff_atom0_scanin = dff_atom1_scanout;
	assign scan_out = dff_atom0_scanout;

	msff_ctl_macro dff_grant_x(
		.scan_in			(dff_grant_x_scanin), 
		.scan_out			(dff_grant_x_scanout), 
		.din				(grant_a), 
		.dout				(grant_x), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_atom_rq_x(
		.scan_in			(dff_atom_rq_x_scanin), 
		.scan_out			(dff_atom_rq_x_scanout), 
		.din				(atom_rq_a), 
		.dout				(atom_rq_x), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_qfull_a(
		.scan_in			(dff_qfull_a_scanin), 
		.scan_out			(dff_qfull_a_scanout), 
		.din				(qfull), 
		.dout				(qfull_a), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_v0(
		.scan_in			(dff_v0_scanin), 
		.scan_out			(dff_v0_scanout), 
		.din				(v0_in), 
		.dout				(v0), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_v1(
		.scan_in			(dff_v1_scanin), 
		.scan_out			(dff_v1_scanout), 
		.din				(v1_in), 
		.dout				(v1), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_qfullbar_a(
		.scan_in			(dff_qfullbar_a_scanin), 
		.scan_out			(dff_qfullbar_a_scanout), 
		.din				(qfullbar), 
		.dout				(qfullbar_a), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_av0(
		.scan_in			(dff_av0_scanin), 
		.scan_out			(dff_av0_scanout), 
		.din				(av0_in), 
		.dout				(av0), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_av1(
		.scan_in			(dff_av1_scanin), 
		.scan_out			(dff_av1_scanout), 
		.din				(av1_in), 
		.dout				(av1), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_atom1(
		.scan_in			(dff_atom1_scanin), 
		.scan_out			(dff_atom1_scanout), 
		.din				(atom1_in), 
		.dout				(atom1), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro dff_atom0(
		.scan_in			(dff_atom0_scanin), 
		.scan_out			(dff_atom0_scanout), 
		.din				(atom0_in), 
		.dout				(atom0), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk));
endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx_trep.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ccx_trep (
  cpu_rep_out, 
  cpu_rep_in);

output [191:0] cpu_rep_out;

input [191:0]  cpu_rep_in;

ccx_rep i0(
           .rep_out(cpu_rep_out[11:0]),
           .rep_in(cpu_rep_in[11:0]));

ccx_rep i1(
           .rep_out(cpu_rep_out[23:12]),
           .rep_in(cpu_rep_in[23:12]));

ccx_rep i2(
           .rep_out(cpu_rep_out[35:24]),
           .rep_in(cpu_rep_in[35:24]));

ccx_rep i3(
           .rep_out(cpu_rep_out[47:36]),
           .rep_in(cpu_rep_in[47:36]));

ccx_rep i4(
           .rep_out(cpu_rep_out[59:48]),
           .rep_in(cpu_rep_in[59:48]));

ccx_rep i5(
           .rep_out(cpu_rep_out[71:60]),
           .rep_in(cpu_rep_in[71:60]));

ccx_rep i6(
           .rep_out(cpu_rep_out[83:72]),
           .rep_in(cpu_rep_in[83:72]));

ccx_rep i7(
           .rep_out(cpu_rep_out[95:84]),
           .rep_in(cpu_rep_in[95:84]));

ccx_rep i8(
           .rep_out(cpu_rep_out[107:96]),
           .rep_in(cpu_rep_in[107:96]));

ccx_rep i9(
           .rep_out(cpu_rep_out[119:108]),
           .rep_in(cpu_rep_in[119:108]));

ccx_rep i10(
           .rep_out(cpu_rep_out[131:120]),
           .rep_in(cpu_rep_in[131:120]));

ccx_rep i11(
           .rep_out(cpu_rep_out[143:132]),
           .rep_in(cpu_rep_in[143:132]));

ccx_rep i12(
           .rep_out(cpu_rep_out[155:144]),
           .rep_in(cpu_rep_in[155:144]));

ccx_rep i13(
           .rep_out(cpu_rep_out[167:156]),
           .rep_in(cpu_rep_in[167:156]));

ccx_rep i14(
           .rep_out(cpu_rep_out[179:168]),
           .rep_in(cpu_rep_in[179:168]));

ccx_rep i15(
           .rep_out(cpu_rep_out[191:180]),
           .rep_in(cpu_rep_in[191:180]));

endmodule // ccx_trep


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccx_tstg.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ccx_tstg (
  dout, 
  din, 
  l2clk, 
  scan_in, 
  scan_out, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  tcu_pce_ov, 
  local_stop);
wire scan_out0;
wire scan_out1;
wire scan_out2;
wire scan_out3;
wire scan_out4;
wire scan_out5;
wire scan_out6;
wire scan_out7;
wire scan_out8;


output [159:0] dout;

input [159:0]  din;

input           l2clk;          
input           scan_in;
output          scan_out;
input           tcu_aclk;
input           tcu_bclk;
input           tcu_scan_en;
input           tcu_pce_ov;
input           local_stop;


n2_flop_bank_cust i0(
           .data_out(dout[15:0]),
           .data_in(din[15:0]),
           .scan_in(scan_in),
           .scan_out(scan_out0),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i1(
           .data_out(dout[31:16]),
           .data_in(din[31:16]),
           .scan_in(scan_out0),
           .scan_out(scan_out1),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i2(
           .data_out(dout[47:32]),
           .data_in(din[47:32]),
           .scan_in(scan_out1),
           .scan_out(scan_out2),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i3(
           .data_out(dout[63:48]),
           .data_in(din[63:48]),
           .scan_in(scan_out2),
           .scan_out(scan_out3),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i4(
           .data_out(dout[79:64]),
           .data_in(din[79:64]),
           .scan_in(scan_out3),
           .scan_out(scan_out4),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i5(
           .data_out(dout[95:80]),
           .data_in(din[95:80]),
           .scan_in(scan_out4),
           .scan_out(scan_out5),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i6(
           .data_out(dout[111:96]),
           .data_in(din[111:96]),
           .scan_in(scan_out5),
           .scan_out(scan_out6),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i7(
           .data_out(dout[127:112]),
           .data_in(din[127:112]),
           .scan_in(scan_out6),
           .scan_out(scan_out7),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i8(
           .data_out(dout[143:128]),
           .data_in(din[143:128]),
           .scan_in(scan_out7),
           .scan_out(scan_out8),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

n2_flop_bank_cust i9(
           .data_out(dout[159:144]),
           .data_in(din[159:144]),
           .scan_in(scan_out8),
           .scan_out(scan_out),
  .l2clk(l2clk),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .local_stop(local_stop)
);

endmodule // ccx_trep


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx (
  cpx_io_grant_cx, 
  cpx_sctag0_grant_cx, 
  cpx_sctag1_grant_cx, 
  cpx_sctag2_grant_cx, 
  cpx_sctag3_grant_cx, 
  cpx_sctag4_grant_cx, 
  cpx_sctag5_grant_cx, 
  cpx_sctag6_grant_cx, 
  cpx_sctag7_grant_cx, 
  cpx_spc0_data_cx2, 
  cpx_spc1_data_cx2, 
  cpx_spc2_data_cx2, 
  cpx_spc3_data_cx2, 
  cpx_spc4_data_cx2, 
  cpx_spc5_data_cx2, 
  cpx_spc6_data_cx2, 
  cpx_spc7_data_cx2, 
  io_cpx_data_ca, 
  io_cpx_req_cq, 
  sctag0_cpx_atom_cq, 
  sctag0_cpx_data_ca, 
  sctag0_cpx_req_cq, 
  sctag1_cpx_atom_cq, 
  sctag1_cpx_data_ca, 
  sctag1_cpx_req_cq, 
  sctag2_cpx_atom_cq, 
  sctag2_cpx_data_ca, 
  sctag2_cpx_req_cq, 
  sctag3_cpx_atom_cq, 
  sctag3_cpx_data_ca, 
  sctag3_cpx_req_cq, 
  sctag4_cpx_atom_cq, 
  sctag4_cpx_data_ca, 
  sctag4_cpx_req_cq, 
  sctag5_cpx_atom_cq, 
  sctag5_cpx_data_ca, 
  sctag5_cpx_req_cq, 
  sctag6_cpx_atom_cq, 
  sctag6_cpx_data_ca, 
  sctag6_cpx_req_cq, 
  sctag7_cpx_atom_cq, 
  sctag7_cpx_data_ca, 
  sctag7_cpx_req_cq, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [7:0] cpx_sctag0_grant_a;
wire [7:0] cpx_sctag0_grant_a_0;
wire [7:0] cpx_sctag1_grant_a;
wire [7:0] cpx_sctag1_grant_a_0;
wire [7:0] cpx_sctag2_grant_a;
wire [7:0] cpx_sctag2_grant_a_0;
wire [7:0] cpx_sctag3_grant_a;
wire [7:0] cpx_sctag3_grant_a_0;
wire [7:0] cpx_sctag4_grant_a;
wire [7:0] cpx_sctag4_grant_a_0;
wire [7:0] cpx_sctag5_grant_a;
wire [7:0] cpx_sctag5_grant_a_0;
wire [7:0] cpx_sctag6_grant_a;
wire [7:0] cpx_sctag6_grant_a_0;
wire [7:0] cpx_sctag7_grant_a;
wire [7:0] cpx_sctag7_grant_a_0;
wire [7:0] cpx_io_grant_a;
wire [7:0] cpx_io_grant_a_0;
wire tcu_scan_en_bfg_0;
wire tcu_pce_ov_bfg_0;
wire ccx_aclk_bfg_0;
wire ccx_bclk_bfg_0;
wire bfg0_scanin;
wire bfg0_scanout;
wire tcu_scan_en_bfd_lt;
wire tcu_pce_ov_bfd_lt;
wire ccx_aclk_bfd_lt;
wire ccx_bclk_bfd_lt;
wire tcu_scan_en_bfg_1_unused;
wire tcu_pce_ov_bfg_1_unused;
wire ccx_aclk_bfg_1_unused;
wire ccx_bclk_bfg_1_unused;
wire bfg1_scanin;
wire bfg1_scanout;
wire tcu_scan_en_bfd_t;
wire tcu_pce_ov_bfd_t;
wire ccx_aclk_bfd_t;
wire ccx_bclk_bfd_t;
wire tcu_scan_en_bfg_2_unused;
wire tcu_pce_ov_bfg_2_unused;
wire ccx_aclk_bfg_2_unused;
wire ccx_bclk_bfg_2_unused;
wire bfg2_scanin;
wire bfg2_scanout;
wire tcu_scan_en_bfd_lb;
wire tcu_pce_ov_bfd_lb;
wire ccx_aclk_bfd_lb;
wire ccx_bclk_bfd_lb;
wire tcu_scan_en_bfg_3_unused;
wire tcu_pce_ov_bfg_3_unused;
wire ccx_aclk_bfg_3_unused;
wire ccx_bclk_bfg_3_unused;
wire bfg3_scanin;
wire bfg3_scanout;
wire tcu_scan_en_bfd_b;
wire tcu_pce_ov_bfd_b;
wire ccx_aclk_bfd_b;
wire ccx_bclk_bfd_b;
wire tcu_scan_en_bfg_4_unused;
wire tcu_pce_ov_bfg_4_unused;
wire ccx_aclk_bfg_4_unused;
wire ccx_bclk_bfg_4_unused;
wire bfg4_scanin;
wire bfg4_scanout;
wire tcu_scan_en_bfd_rt;
wire tcu_pce_ov_bfd_rt;
wire ccx_aclk_bfd_rt;
wire ccx_bclk_bfd_rt;
wire tcu_scan_en_bfg_5_unused;
wire tcu_pce_ov_bfg_5_unused;
wire ccx_aclk_bfg_5_unused;
wire ccx_bclk_bfg_5_unused;
wire bfg5_scanin;
wire bfg5_scanout;
wire tcu_scan_en_bfg_6_unused;
wire tcu_pce_ov_bfg_6_unused;
wire ccx_aclk_bfg_6_unused;
wire ccx_bclk_bfg_6_unused;
wire bfg6_scanin;
wire bfg6_scanout;
wire tcu_scan_en_bfd_rb;
wire tcu_pce_ov_bfd_rb;
wire ccx_aclk_bfd_rb;
wire ccx_bclk_bfd_rb;
wire tcu_scan_en_bfg_7_unused;
wire tcu_pce_ov_bfg_7_unused;
wire ccx_aclk_bfg_7_unused;
wire ccx_bclk_bfg_7_unused;
wire bfg7_scanin;
wire bfg7_scanout;
wire tcu_scan_en_bfg_8_unused;
wire tcu_pce_ov_bfg_8_unused;
wire ccx_aclk_bfg_8_unused;
wire ccx_bclk_bfg_8_unused;
wire bfg8_scanin;
wire bfg8_scanout;
wire [145:0] io_cpx_data_ca_buf;
wire [145:0] io_cpx_data_ca_d1_;
wire tcu_scan_en_bfd_io_unused;
wire tcu_pce_ov_bfd_io_unused;
wire ccx_aclk_bfd_io_unused;
wire ccx_bclk_bfd_io_unused;
wire bfd_io_scanin;
wire bfd_io_scanout;
wire [7:0] sctag0_cpx_req_cq_0_l;
wire sctag0_cpx_atom_cq_0_l;
wire [7:0] sctag0_cpx_req_cq_0_r;
wire sctag0_cpx_atom_cq_0_r;
wire [7:0] sctag1_cpx_req_cq_0_l;
wire sctag1_cpx_atom_cq_0_l;
wire [7:0] sctag1_cpx_req_cq_0_r;
wire sctag1_cpx_atom_cq_0_r;
wire [7:0] sctag2_cpx_req_cq_0_l;
wire sctag2_cpx_atom_cq_0_l;
wire [7:0] sctag2_cpx_req_cq_0_r;
wire sctag2_cpx_atom_cq_0_r;
wire [7:0] sctag3_cpx_req_cq_0_l;
wire sctag3_cpx_atom_cq_0_l;
wire [7:0] sctag3_cpx_req_cq_0_r;
wire sctag3_cpx_atom_cq_0_r;
wire [7:0] sctag4_cpx_req_cq_0_l;
wire sctag4_cpx_atom_cq_0_l;
wire [7:0] sctag4_cpx_req_cq_0_r;
wire sctag4_cpx_atom_cq_0_r;
wire [7:0] sctag5_cpx_req_cq_0_l;
wire sctag5_cpx_atom_cq_0_l;
wire [7:0] sctag5_cpx_req_cq_0_r;
wire sctag5_cpx_atom_cq_0_r;
wire [7:0] sctag6_cpx_req_cq_0_l;
wire sctag6_cpx_atom_cq_0_l;
wire [7:0] sctag6_cpx_req_cq_0_r;
wire sctag6_cpx_atom_cq_0_r;
wire [7:0] sctag7_cpx_req_cq_0_l;
wire sctag7_cpx_atom_cq_0_l;
wire [7:0] sctag7_cpx_req_cq_0_r;
wire sctag7_cpx_atom_cq_0_r;
wire [7:0] io_cpx_req_cq_buf;
wire [7:0] io_cpx_req_cq_d1;
wire tcu_scan_en_bfg_req_8_unused;
wire tcu_pce_ov_bfg_req_8_unused;
wire ccx_aclk_bfg_req_8_unused;
wire ccx_bclk_bfg_req_8_unused;
wire bfg8_req_scanin;
wire bfg8_req_scanout;
wire [149:0] sctag0_cpx_data_a_;
wire [149:0] sctag0_cpx_data_a;
wire [149:0] sctag1_cpx_data_a_;
wire [149:0] sctag1_cpx_data_a;
wire [149:0] sctag2_cpx_data_a_;
wire [149:0] sctag2_cpx_data_a;
wire [149:0] sctag3_cpx_data_a_;
wire [149:0] sctag3_cpx_data_a;
wire [149:0] sctag4_cpx_data_a_;
wire [149:0] sctag4_cpx_data_a;
wire [149:0] sctag5_cpx_data_a_;
wire [149:0] sctag5_cpx_data_a;
wire [149:0] sctag6_cpx_data_a_;
wire [149:0] sctag6_cpx_data_a;
wire [149:0] sctag7_cpx_data_a_;
wire [149:0] sctag7_cpx_data_a;
wire [149:0] io_cpx_data_a_;
wire [149:0] io_cpx_data_a;
wire ccx_aclk_dpa_t;
wire ccx_bclk_dpa_t;
wire tcu_pce_ov_dpa_t;
wire tcu_scan_en_dpa_t;
wire ccx_aclk_dpa_b;
wire ccx_bclk_dpa_b;
wire tcu_pce_ov_dpa_b;
wire tcu_scan_en_dpa_b;
wire [3:0] cpx_spc0_data_x_unused;
wire [149:0] cpx_spc0_data_x_;
wire [3:0] cpx_spc1_data_x_unused;
wire [149:0] cpx_spc1_data_x_;
wire [3:0] cpx_spc2_data_x_unused;
wire [149:0] cpx_spc2_data_x_;
wire [3:0] cpx_spc3_data_x_unused;
wire [149:0] cpx_spc3_data_x_;
wire [3:0] cpx_spc4_data_x_unused;
wire [149:0] cpx_spc4_data_x_;
wire [3:0] cpx_spc5_data_x_unused;
wire [149:0] cpx_spc5_data_x_;
wire [3:0] cpx_spc6_data_x_unused;
wire [149:0] cpx_spc6_data_x_;
wire [3:0] cpx_spc7_data_x_unused;
wire [149:0] cpx_spc7_data_x_;
wire [8:0] arb0_grant_l_a;
wire [8:0] arb0_q0_holdbar_l_a;
wire [8:0] arb0_qsel0_l_a;
wire [8:0] arb0_qsel1_l_a;
wire [8:0] arb0_shift_l_a;
wire [8:0] arb1_grant_l_a;
wire [8:0] arb1_q0_holdbar_l_a;
wire [8:0] arb1_qsel0_l_a;
wire [8:0] arb1_qsel1_l_a;
wire [8:0] arb1_shift_l_a;
wire [8:0] arb2_grant_l_a;
wire [8:0] arb2_q0_holdbar_l_a;
wire [8:0] arb2_qsel0_l_a;
wire [8:0] arb2_qsel1_l_a;
wire [8:0] arb2_shift_l_a;
wire [8:0] arb3_grant_l_a;
wire [8:0] arb3_q0_holdbar_l_a;
wire [8:0] arb3_qsel0_l_a;
wire [8:0] arb3_qsel1_l_a;
wire [8:0] arb3_shift_l_a;
wire [8:0] arb4_grant_l_a;
wire [8:0] arb4_q0_holdbar_l_a;
wire [8:0] arb4_qsel0_l_a;
wire [8:0] arb4_qsel1_l_a;
wire [8:0] arb4_shift_l_a;
wire [8:0] arb5_grant_l_a;
wire [8:0] arb5_q0_holdbar_l_a;
wire [8:0] arb5_qsel0_l_a;
wire [8:0] arb5_qsel1_l_a;
wire [8:0] arb5_shift_l_a;
wire [8:0] arb6_grant_l_a;
wire [8:0] arb6_q0_holdbar_l_a;
wire [8:0] arb6_qsel0_l_a;
wire [8:0] arb6_qsel1_l_a;
wire [8:0] arb6_shift_l_a;
wire [8:0] arb7_grant_l_a;
wire [8:0] arb7_q0_holdbar_l_a;
wire [8:0] arb7_qsel0_l_a;
wire [8:0] arb7_qsel1_l_a;
wire [8:0] arb7_shift_l_a;
wire [8:0] arb0_grant_r_a;
wire [8:0] arb0_q0_holdbar_r_a;
wire [8:0] arb0_qsel0_r_a;
wire [8:0] arb0_qsel1_r_a;
wire [8:0] arb0_shift_r_a;
wire [8:0] arb1_grant_r_a;
wire [8:0] arb1_q0_holdbar_r_a;
wire [8:0] arb1_qsel0_r_a;
wire [8:0] arb1_qsel1_r_a;
wire [8:0] arb1_shift_r_a;
wire [8:0] arb2_grant_r_a;
wire [8:0] arb2_q0_holdbar_r_a;
wire [8:0] arb2_qsel0_r_a;
wire [8:0] arb2_qsel1_r_a;
wire [8:0] arb2_shift_r_a;
wire [8:0] arb3_grant_r_a;
wire [8:0] arb3_q0_holdbar_r_a;
wire [8:0] arb3_qsel0_r_a;
wire [8:0] arb3_qsel1_r_a;
wire [8:0] arb3_shift_r_a;
wire [8:0] arb4_grant_r_a;
wire [8:0] arb4_q0_holdbar_r_a;
wire [8:0] arb4_qsel0_r_a;
wire [8:0] arb4_qsel1_r_a;
wire [8:0] arb4_shift_r_a;
wire [8:0] arb5_grant_r_a;
wire [8:0] arb5_q0_holdbar_r_a;
wire [8:0] arb5_qsel0_r_a;
wire [8:0] arb5_qsel1_r_a;
wire [8:0] arb5_shift_r_a;
wire [8:0] arb6_grant_r_a;
wire [8:0] arb6_q0_holdbar_r_a;
wire [8:0] arb6_qsel0_r_a;
wire [8:0] arb6_qsel1_r_a;
wire [8:0] arb6_shift_r_a;
wire [8:0] arb7_grant_r_a;
wire [8:0] arb7_q0_holdbar_r_a;
wire [8:0] arb7_qsel0_r_a;
wire [8:0] arb7_qsel1_r_a;
wire [8:0] arb7_shift_r_a;
wire cpx_dpa_scanin;
wire cpx_dpa_scanout;
wire [145:0] cpx_spc0_data_cx2_prebuf;
wire bfd0_scanin;
wire bfd0_scanout;
wire tcu_scan_en_bfd_1;
wire tcu_pce_ov_bfd_1;
wire ccx_aclk_bfd_1;
wire ccx_bclk_bfd_1;
wire [145:0] cpx_spc1_data_cx2_prebuf;
wire bfd1_scanin;
wire bfd1_scanout;
wire [145:0] cpx_spc2_data_cx2_prebuf;
wire bfd2_scanin;
wire bfd2_scanout;
wire tcu_scan_en_bfd_3;
wire tcu_pce_ov_bfd_3;
wire ccx_aclk_bfd_3;
wire ccx_bclk_bfd_3;
wire [145:0] cpx_spc3_data_cx2_prebuf;
wire bfd3_scanin;
wire bfd3_scanout;
wire [145:0] cpx_spc4_data_cx2_prebuf;
wire bfd4_scanin;
wire bfd4_scanout;
wire tcu_scan_en_bfd_5;
wire tcu_pce_ov_bfd_5;
wire ccx_aclk_bfd_5;
wire ccx_bclk_bfd_5;
wire [145:0] cpx_spc5_data_cx2_prebuf;
wire bfd5_scanin;
wire bfd5_scanout;
wire [145:0] cpx_spc6_data_cx2_prebuf;
wire bfd6_scanin;
wire bfd6_scanout;
wire tcu_scan_en_bfd_7;
wire tcu_pce_ov_bfd_7;
wire ccx_aclk_bfd_7;
wire ccx_bclk_bfd_7;
wire [145:0] cpx_spc7_data_cx2_prebuf;
wire bfd7_scanin;
wire bfd7_scanout;
wire [7:0] sctag0_cpx_req_lq;
wire sctag0_cpx_atom_lq_t;
wire sctag0_cpx_atom_lq_b;
wire [7:0] sctag1_cpx_req_lq;
wire sctag1_cpx_atom_lq_t;
wire sctag1_cpx_atom_lq_b;
wire [7:0] sctag2_cpx_req_lq;
wire sctag2_cpx_atom_lq_t;
wire sctag2_cpx_atom_lq_b;
wire [7:0] sctag3_cpx_req_lq;
wire sctag3_cpx_atom_lq_t;
wire sctag3_cpx_atom_lq_b;
wire [7:0] sctag4_cpx_req_lq;
wire sctag4_cpx_atom_lq_t;
wire sctag4_cpx_atom_lq_b;
wire [7:0] sctag5_cpx_req_lq;
wire sctag5_cpx_atom_lq_t;
wire sctag5_cpx_atom_lq_b;
wire [7:0] sctag6_cpx_req_lq;
wire sctag6_cpx_atom_lq_t;
wire sctag6_cpx_atom_lq_b;
wire [7:0] sctag7_cpx_req_lq;
wire sctag7_cpx_atom_lq_t;
wire sctag7_cpx_atom_lq_b;
wire [7:0] io_cpx_req_lq;
wire ccx_aclk_arb_lt;
wire ccx_bclk_arb_lt;
wire tcu_pce_ov_arb_lt;
wire tcu_scan_en_arb_lt;
wire ccx_aclk_arb_lb;
wire ccx_bclk_arb_lb;
wire tcu_pce_ov_arb_lb;
wire tcu_scan_en_arb_lb;
wire ccx_aclk_arb_rt;
wire ccx_bclk_arb_rt;
wire tcu_pce_ov_arb_rt;
wire tcu_scan_en_arb_rt;
wire ccx_aclk_arb_rb;
wire ccx_bclk_arb_rb;
wire tcu_pce_ov_arb_rb;
wire tcu_scan_en_arb_rb;
wire [7:0] cpx_sctag4_grant_a_unused;
wire [7:0] cpx_sctag5_grant_a_unused;
wire [7:0] cpx_sctag6_grant_a_unused;
wire [7:0] cpx_sctag7_grant_a_unused;
wire [7:0] ccx_dest_atom_a_l_unused;
wire [7:0] ccx_dest_data_rdy_a_l_unused;
wire cpx_arbl0_scanin;
wire cpx_arbl0_scanout;
wire cpx_arbl1_scanin;
wire cpx_arbl1_scanout;
wire cpx_arbl2_scanin;
wire cpx_arbl2_scanout;
wire cpx_arbl3_scanin;
wire cpx_arbl3_scanout;
wire cpx_arbl4_scanin;
wire cpx_arbl4_scanout;
wire cpx_arbl5_scanin;
wire cpx_arbl5_scanout;
wire cpx_arbl6_scanin;
wire cpx_arbl6_scanout;
wire cpx_arbl7_scanin;
wire cpx_arbl7_scanout;
wire [7:0] sctag0_cpx_req_rq;
wire sctag0_cpx_atom_rq_t;
wire sctag0_cpx_atom_rq_b;
wire [7:0] sctag1_cpx_req_rq;
wire sctag1_cpx_atom_rq_t;
wire sctag1_cpx_atom_rq_b;
wire [7:0] sctag2_cpx_req_rq;
wire sctag2_cpx_atom_rq_t;
wire sctag2_cpx_atom_rq_b;
wire [7:0] sctag3_cpx_req_rq;
wire sctag3_cpx_atom_rq_t;
wire sctag3_cpx_atom_rq_b;
wire [7:0] sctag4_cpx_req_rq;
wire sctag4_cpx_atom_rq_t;
wire sctag4_cpx_atom_rq_b;
wire [7:0] sctag5_cpx_req_rq;
wire sctag5_cpx_atom_rq_t;
wire sctag5_cpx_atom_rq_b;
wire [7:0] sctag6_cpx_req_rq;
wire sctag6_cpx_atom_rq_t;
wire sctag6_cpx_atom_rq_b;
wire [7:0] sctag7_cpx_req_rq;
wire sctag7_cpx_atom_rq_t;
wire sctag7_cpx_atom_rq_b;
wire [7:0] io_cpx_req_rq;
wire [7:0] cpx_sctag0_grant_a_unused;
wire [7:0] cpx_sctag1_grant_a_unused;
wire [7:0] cpx_sctag2_grant_a_unused;
wire [7:0] cpx_sctag3_grant_a_unused;
wire [7:0] cpx_sctag8_grant_a_unused;
wire [7:0] ccx_dest_atom_a_r_unused;
wire [7:0] ccx_dest_data_rdy_a_r_unused;
wire cpx_arbr0_scanin;
wire cpx_arbr0_scanout;
wire cpx_arbr1_scanin;
wire cpx_arbr1_scanout;
wire cpx_arbr2_scanin;
wire cpx_arbr2_scanout;
wire cpx_arbr3_scanin;
wire cpx_arbr3_scanout;
wire cpx_arbr4_scanin;
wire cpx_arbr4_scanout;
wire cpx_arbr5_scanin;
wire cpx_arbr5_scanout;
wire cpx_arbr6_scanin;
wire cpx_arbr6_scanout;
wire cpx_arbr7_scanin;
wire cpx_arbr7_scanout;
wire scan_out_prebuf;


output [7:0]            cpx_io_grant_cx;        // From sctag_buf8 of cpx_bfs_dp.v
output [7:0]            cpx_sctag0_grant_cx;    // From sctag_buf0 of cpx_bfs_dp.v
output [7:0]            cpx_sctag1_grant_cx;    // From sctag_buf1 of cpx_bfs_dp.v
output [7:0]            cpx_sctag2_grant_cx;    // From sctag_buf2 of cpx_bfs_dp.v
output [7:0]            cpx_sctag3_grant_cx;    // From sctag_buf3 of cpx_bfs_dp.v
output [7:0]            cpx_sctag4_grant_cx;    // From sctag_buf4 of cpx_bfs_dp.v
output [7:0]            cpx_sctag5_grant_cx;    // From sctag_buf5 of cpx_bfs_dp.v
output [7:0]            cpx_sctag6_grant_cx;    // From sctag_buf6 of cpx_bfs_dp.v
output [7:0]            cpx_sctag7_grant_cx;    // From sctag_buf7 of cpx_bfs_dp.v
output [145:0]          cpx_spc0_data_cx2;      // From spc_buf0 of cpx_bfc_dp.v
output [145:0]          cpx_spc1_data_cx2;      // From spc_buf1 of cpx_bfc_dp.v
output [145:0]          cpx_spc2_data_cx2;      // From spc_buf2 of cpx_bfc_dp.v
output [145:0]          cpx_spc3_data_cx2;      // From spc_buf3 of cpx_bfc_dp.v
output [145:0]          cpx_spc4_data_cx2;      // From spc_buf4 of cpx_bfc_dp.v
output [145:0]          cpx_spc5_data_cx2;      // From spc_buf5 of cpx_bfc_dp.v
output [145:0]          cpx_spc6_data_cx2;      // From spc_buf6 of cpx_bfc_dp.v
output [145:0]          cpx_spc7_data_cx2;      // From spc_buf7 of cpx_bfc_dp.v


input [145:0]           io_cpx_data_ca;         // To cpx_dpa of cpx_dpa.v
input [7:0]             io_cpx_req_cq;          // To arb0 of ccx_arb.v, ...
input                   sctag0_cpx_atom_cq;     // To arb0 of ccx_arb.v, ...
input [145:0]           sctag0_cpx_data_ca;     // To cpx_dpa of cpx_dpa.v
input [7:0]             sctag0_cpx_req_cq;      // To arb0 of ccx_arb.v, ...
input                   sctag1_cpx_atom_cq;     // To arb0 of ccx_arb.v, ...
input [145:0]           sctag1_cpx_data_ca;     // To cpx_dpa of cpx_dpa.v
input [7:0]             sctag1_cpx_req_cq;      // To arb0 of ccx_arb.v, ...
input                   sctag2_cpx_atom_cq;     // To arb0 of ccx_arb.v, ...
input [145:0]           sctag2_cpx_data_ca;     // To cpx_dpa of cpx_dpa.v
input [7:0]             sctag2_cpx_req_cq;      // To arb0 of ccx_arb.v, ...
input                   sctag3_cpx_atom_cq;     // To arb0 of ccx_arb.v, ...
input [145:0]           sctag3_cpx_data_ca;     // To cpx_dpa of cpx_dpa.v
input [7:0]             sctag3_cpx_req_cq;      // To arb0 of ccx_arb.v, ...
input                   sctag4_cpx_atom_cq;     // To arb0 of ccx_arb.v, ...
input [145:0]           sctag4_cpx_data_ca;     // To cpx_dpa of cpx_dpa.v
input [7:0]             sctag4_cpx_req_cq;      // To arb0 of ccx_arb.v, ...
input                   sctag5_cpx_atom_cq;     // To arb0 of ccx_arb.v, ...
input [145:0]           sctag5_cpx_data_ca;     // To cpx_dpa of cpx_dpa.v
input [7:0]             sctag5_cpx_req_cq;      // To arb0 of ccx_arb.v, ...
input                   sctag6_cpx_atom_cq;     // To arb0 of ccx_arb.v, ...
input [145:0]           sctag6_cpx_data_ca;     // To cpx_dpa of cpx_dpa.v
input [7:0]             sctag6_cpx_req_cq;      // To arb0 of ccx_arb.v, ...
input                   sctag7_cpx_atom_cq;     // To arb0 of ccx_arb.v, ...
input [145:0]           sctag7_cpx_data_ca;     // To cpx_dpa of cpx_dpa.v
input [7:0]             sctag7_cpx_req_cq;      // To arb0 of ccx_arb.v, ...

// Extra inputs which exist in N1

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;


// buffer output grant signals
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct0     (
	.din	(cpx_sctag0_grant_a[7:0]),
	.dout	(cpx_sctag0_grant_a_0[7:0])
);

cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct1     (
	.din	(cpx_sctag1_grant_a[7:0]),
	.dout	(cpx_sctag1_grant_a_0[7:0])
);

cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct2     (
	.din	(cpx_sctag2_grant_a[7:0]),
	.dout	(cpx_sctag2_grant_a_0[7:0])
);

cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct3     (
	.din	(cpx_sctag3_grant_a[7:0]),
	.dout	(cpx_sctag3_grant_a_0[7:0])
);

cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct4     (
	.din	(cpx_sctag4_grant_a[7:0]),
	.dout	(cpx_sctag4_grant_a_0[7:0])
);

cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct5     (
	.din	(cpx_sctag5_grant_a[7:0]),
	.dout	(cpx_sctag5_grant_a_0[7:0])
);

cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct6     (
	.din	(cpx_sctag6_grant_a[7:0]),
	.dout	(cpx_sctag6_grant_a_0[7:0])
);

cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct7     (
	.din	(cpx_sctag7_grant_a[7:0]),
	.dout	(cpx_sctag7_grant_a_0[7:0])
);

cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_io     (
	.din	(cpx_io_grant_a[7:0]),
	.dout	(cpx_io_grant_a_0[7:0])
);

/*
 cpx_bfg_dp AUTO_TEMPLATE(
 .cpx_sctag_grant_cx (cpx_sctag@_grant_cx_0[7:0]),
 .cpx_sctag_grant_ca (cpx_sctag@_grant_a[7:0]));
   */

cpx_bfg_dp bfg0 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_sctag0_grant_cx[7:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_0),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_0),
                 .ccx_aclk_out          (ccx_aclk_bfg_0),
                 .ccx_bclk_out          (ccx_bclk_bfg_0),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_sctag0_grant_a_0[7:0]), // Templated
                 .scan_in(bfg0_scanin),
                 .scan_out(bfg0_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_lt),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_lt),
                 .ccx_aclk                (ccx_aclk_bfd_lt),
                 .ccx_bclk                (ccx_bclk_bfd_lt)
                 );

cpx_bfg_dp bfg1 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_sctag1_grant_cx[7:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_1_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_1_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_1_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_1_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_sctag1_grant_a_0[7:0]), // Templated
                 .scan_in(bfg1_scanin),
                 .scan_out(bfg1_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_t),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_t),
                 .ccx_aclk                (ccx_aclk_bfd_t),
                 .ccx_bclk                (ccx_bclk_bfd_t)
                 );

cpx_bfg_dp bfg2 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_sctag2_grant_cx[7:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_2_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_2_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_2_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_2_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_sctag2_grant_a_0[7:0]), // Templated
                 .scan_in(bfg2_scanin),
                 .scan_out(bfg2_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_lb),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_lb),
                 .ccx_aclk                (ccx_aclk_bfd_lb),
                 .ccx_bclk                (ccx_bclk_bfd_lb)
                 );

cpx_bfg_dp bfg3 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_sctag3_grant_cx[7:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_3_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_3_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_3_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_3_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_sctag3_grant_a_0[7:0]), // Templated
                 .scan_in(bfg3_scanin),
                 .scan_out(bfg3_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_b),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_b),
                 .ccx_aclk                (ccx_aclk_bfd_b),
                 .ccx_bclk                (ccx_bclk_bfd_b)
                 );

cpx_bfg_dp bfg4 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_sctag4_grant_cx[7:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_4_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_4_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_4_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_4_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_sctag4_grant_a_0[7:0]), // Templated
                 .scan_in(bfg4_scanin),
                 .scan_out(bfg4_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_rt),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_rt),
                 .ccx_aclk                (ccx_aclk_bfd_rt),
                 .ccx_bclk                (ccx_bclk_bfd_rt)
                 );

cpx_bfg_dp bfg5 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_sctag5_grant_cx[7:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_5_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_5_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_5_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_5_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_sctag5_grant_a_0[7:0]), // Templated
                 .scan_in(bfg5_scanin),
                 .scan_out(bfg5_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_t),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_t),
                 .ccx_aclk                (ccx_aclk_bfd_t),
                 .ccx_bclk                (ccx_bclk_bfd_t)
                 );

cpx_bfg_dp bfg6 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_sctag6_grant_cx[7:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_6_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_6_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_6_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_6_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_sctag6_grant_a_0[7:0]), // Templated
                 .scan_in(bfg6_scanin),
                 .scan_out(bfg6_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_rb),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_rb),
                 .ccx_aclk                (ccx_aclk_bfd_rb),
                 .ccx_bclk                (ccx_bclk_bfd_rb)
                 );

cpx_bfg_dp bfg7 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_sctag7_grant_cx[7:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_7_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_7_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_7_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_7_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_sctag7_grant_a_0[7:0]), // Templated
                 .scan_in(bfg7_scanin),
                 .scan_out(bfg7_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_b),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_b),
                 .ccx_aclk                (ccx_aclk_bfd_b),
                 .ccx_bclk                (ccx_bclk_bfd_b)
                 );

/*
 cpx_bfg_dp AUTO_TEMPLATE(
 .cpx_sctag_grant_cx (cpx_io_grant_cx_0[7:0]),
 .cpx_sctag_grant_ca (cpx_io_grant_a[7:0]));
  */

cpx_bfg_dp bfg8 (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (cpx_io_grant_cx[7:0]),  // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_8_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_8_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_8_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_8_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (cpx_io_grant_a_0[7:0]),   // Templated
                 .scan_in(bfg8_scanin),
                 .scan_out(bfg8_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfg_0),
                 .tcu_pce_ov              (tcu_pce_ov_bfg_0),
                 .ccx_aclk                (ccx_aclk_bfg_0),
                 .ccx_bclk                (ccx_bclk_bfg_0)
                 );


// flop data coming from NCU.
// Even though data signals are named data_ca, they are launched 1 cycle early.
// Flopping at pins, solves ccx timing path.
// use bfd_dp to do the flopping and buffering. This is an inverting flop (normally used to buffer outgoing signals)
// Signal polarity changes to active low.

// First pass through an isolation buffer
cpx_ob1_dp buf_io (
.cpx_spc_data_cx2_prebuf (io_cpx_data_ca[145:0]),
.cpx_spc_data_cx2       (io_cpx_data_ca_buf[145:0])
);
                   
cpx_bfd_dp bfd_io (
                 // Outputs
                 .cpx_spc_data_cx2      (io_cpx_data_ca_d1_[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_io_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_io_unused),
                 .ccx_aclk_out          (ccx_aclk_bfd_io_unused),
                 .ccx_bclk_out          (ccx_bclk_bfd_io_unused),
                 // Inputs
                 .cpx_spc_data_x_       (io_cpx_data_ca_buf[145:0]), // Templated
                 .scan_in(bfd_io_scanin),
                 .scan_out(bfd_io_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_lt),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_lt),
                 .ccx_aclk          (ccx_aclk_bfd_lt),
                 .ccx_bclk          (ccx_bclk_bfd_lt)
                 );


// buffer input data from  io at the pins
//buff_macro i_bufd_io_0 (dbuff=32x, width=146, stack=150c) (
//	.din	(io_cpx_data_ca[145:0]),
//	.dout	(io_cpx_data_ca_0[145:0]),
//);


// buffer req and atm signals at the pins
cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct0_l     (
	.din	({sctag0_cpx_req_cq[7:0],sctag0_cpx_atom_cq}),
	.dout	({sctag0_cpx_req_cq_0_l[7:0],sctag0_cpx_atom_cq_0_l})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct0_r     (
	.din	({sctag0_cpx_req_cq[7:0],sctag0_cpx_atom_cq}),
	.dout	({sctag0_cpx_req_cq_0_r[7:0],sctag0_cpx_atom_cq_0_r})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct1_l     (
	.din	({sctag1_cpx_req_cq[7:0],sctag1_cpx_atom_cq}),
	.dout	({sctag1_cpx_req_cq_0_l[7:0],sctag1_cpx_atom_cq_0_l})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct1_r     (
	.din	({sctag1_cpx_req_cq[7:0],sctag1_cpx_atom_cq}),
	.dout	({sctag1_cpx_req_cq_0_r[7:0],sctag1_cpx_atom_cq_0_r})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct2_l     (
	.din	({sctag2_cpx_req_cq[7:0],sctag2_cpx_atom_cq}),
	.dout	({sctag2_cpx_req_cq_0_l[7:0],sctag2_cpx_atom_cq_0_l})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct2_r     (
	.din	({sctag2_cpx_req_cq[7:0],sctag2_cpx_atom_cq}),
	.dout	({sctag2_cpx_req_cq_0_r[7:0],sctag2_cpx_atom_cq_0_r})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct3_l     (
	.din	({sctag3_cpx_req_cq[7:0],sctag3_cpx_atom_cq}),
	.dout	({sctag3_cpx_req_cq_0_l[7:0],sctag3_cpx_atom_cq_0_l})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct3_r     (
	.din	({sctag3_cpx_req_cq[7:0],sctag3_cpx_atom_cq}),
	.dout	({sctag3_cpx_req_cq_0_r[7:0],sctag3_cpx_atom_cq_0_r})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct4_l     (
	.din	({sctag4_cpx_req_cq[7:0],sctag4_cpx_atom_cq}),
	.dout	({sctag4_cpx_req_cq_0_l[7:0],sctag4_cpx_atom_cq_0_l})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct4_r     (
	.din	({sctag4_cpx_req_cq[7:0],sctag4_cpx_atom_cq}),
	.dout	({sctag4_cpx_req_cq_0_r[7:0],sctag4_cpx_atom_cq_0_r})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct5_l     (
	.din	({sctag5_cpx_req_cq[7:0],sctag5_cpx_atom_cq}),
	.dout	({sctag5_cpx_req_cq_0_l[7:0],sctag5_cpx_atom_cq_0_l})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct5_r     (
	.din	({sctag5_cpx_req_cq[7:0],sctag5_cpx_atom_cq}),
	.dout	({sctag5_cpx_req_cq_0_r[7:0],sctag5_cpx_atom_cq_0_r})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct6_l     (
	.din	({sctag6_cpx_req_cq[7:0],sctag6_cpx_atom_cq}),
	.dout	({sctag6_cpx_req_cq_0_l[7:0],sctag6_cpx_atom_cq_0_l})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct6_r     (
	.din	({sctag6_cpx_req_cq[7:0],sctag6_cpx_atom_cq}),
	.dout	({sctag6_cpx_req_cq_0_r[7:0],sctag6_cpx_atom_cq_0_r})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct7_l     (
	.din	({sctag7_cpx_req_cq[7:0],sctag7_cpx_atom_cq}),
	.dout	({sctag7_cpx_req_cq_0_l[7:0],sctag7_cpx_atom_cq_0_l})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct7_r     (
	.din	({sctag7_cpx_req_cq[7:0],sctag7_cpx_atom_cq}),
	.dout	({sctag7_cpx_req_cq_0_r[7:0],sctag7_cpx_atom_cq_0_r})
);


// flop req signal coming from NCU.
// Even though req signals are named req_cq, they are launched 1 cycle early.
// Flopping at pins, solves ccx timing path.
// use bfg_dp to do the flopping and buffering.

cpx_buff_macro__dbuff_16x__rep_1__stack_none__width_8 buf8_req     (
	.din	(io_cpx_req_cq[7:0]),
	.dout	(io_cpx_req_cq_buf[7:0])
);

cpx_bfg_dp bfg8_req (
/*AUTOINST*/
                 // Outputs
                 .cpx_sctag_grant_cx    (io_cpx_req_cq_d1[7:0]),  // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_req_8_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_req_8_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_req_8_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_req_8_unused),
                 // Inputs
                 .cpx_sctag_grant_ca    (io_cpx_req_cq_buf[7:0]),   // Templated
                 .scan_in(bfg8_req_scanin),
                 .scan_out(bfg8_req_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfg_0),
                 .tcu_pce_ov              (tcu_pce_ov_bfg_0),
                 .ccx_aclk                (ccx_aclk_bfg_0),
                 .ccx_bclk                (ccx_bclk_bfg_0)
                 );


// buffer all the inputs at the column
// changed the buffers to inverters to help timing
cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct0_0    (
	.din	({4'b0,sctag0_cpx_data_ca[145:0]}),
	.dout	(sctag0_cpx_data_a_[149:0])
);

cpx_inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct0_1    (
	.din	({sctag0_cpx_data_a_[149:0]}),
	.dout	(sctag0_cpx_data_a[149:0])
);

cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct1_0    (
	.din	({4'b0,sctag1_cpx_data_ca[145:0]}),
	.dout	(sctag1_cpx_data_a_[149:0])
);

cpx_inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct1_1    (
	.din	({sctag1_cpx_data_a_[149:0]}),
	.dout	(sctag1_cpx_data_a[149:0])
);

cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct2_0    (
	.din	({4'b0,sctag2_cpx_data_ca[145:0]}),
	.dout	(sctag2_cpx_data_a_[149:0])
);

cpx_inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct2_1    (
	.din	({sctag2_cpx_data_a_[149:0]}),
	.dout	(sctag2_cpx_data_a[149:0])
);

cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct3_0    (
	.din	({4'b0,sctag3_cpx_data_ca[145:0]}),
	.dout	(sctag3_cpx_data_a_[149:0])
);

cpx_inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct3_1    (
	.din	({sctag3_cpx_data_a_[149:0]}),
	.dout	(sctag3_cpx_data_a[149:0])
);

cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct4_0    (
	.din	({4'b0,sctag4_cpx_data_ca[145:0]}),
	.dout	(sctag4_cpx_data_a_[149:0])
);

cpx_inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct4_1    (
	.din	({sctag4_cpx_data_a_[149:0]}),
	.dout	(sctag4_cpx_data_a[149:0])
);

cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct5_0    (
	.din	({4'b0,sctag5_cpx_data_ca[145:0]}),
	.dout	(sctag5_cpx_data_a_[149:0])
);

cpx_inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct5_1    (
	.din	({sctag5_cpx_data_a_[149:0]}),
	.dout	(sctag5_cpx_data_a[149:0])
);

cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct6_0    (
	.din	({4'b0,sctag6_cpx_data_ca[145:0]}),
	.dout	(sctag6_cpx_data_a_[149:0])
);

cpx_inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct6_1    (
	.din	({sctag6_cpx_data_a_[149:0]}),
	.dout	(sctag6_cpx_data_a[149:0])
);

cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct7_0    (
	.din	({4'b0,sctag7_cpx_data_ca[145:0]}),
	.dout	(sctag7_cpx_data_a_[149:0])
);

cpx_inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct7_1    (
	.din	({sctag7_cpx_data_a_[149:0]}),
	.dout	(sctag7_cpx_data_a[149:0])
);

cpx_buff_macro__dbuff_8x__minbuff_1__stack_150c__width_150 i_bufd_io_1     (
	.din	({4'b0,io_cpx_data_ca_d1_[145:0]}),
	.dout	(io_cpx_data_a_[149:0])
);
cpx_inv_macro__dinv_32x__stack_150c__width_150 i_inv_io_1    (
	.din	({io_cpx_data_a_[149:0]}),
	.dout	(io_cpx_data_a[149:0])
);

//buffer the high fanout signals going to dpa top
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_dpa_t     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_dpa_t,ccx_bclk_dpa_t,tcu_pce_ov_dpa_t,tcu_scan_en_dpa_t})
);
//buffer the high fanout signals going to bfd_dp/bfg_dp top
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_bfd_t     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_bfd_t,ccx_bclk_bfd_t,tcu_pce_ov_bfd_t,tcu_scan_en_bfd_t})
);
//buffer the high fanout signals going to dpa bottom
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_dpa_b     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_dpa_b,ccx_bclk_dpa_b,tcu_pce_ov_dpa_b,tcu_scan_en_dpa_b})
);
//buffer the high fanout signals going to bfd_dp/bfg_dp bottom
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_bfd_b     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_bfd_b,ccx_bclk_bfd_b,tcu_pce_ov_bfd_b,tcu_scan_en_bfd_b})
);

 /*
  cpx_dpa AUTO_TEMPLATE(
  .io_cpx_data_a(io_cpx_data_a[149:0]),
  .scache0_cpx_data_a(sctag0_cpx_data_a[149:0]),  
  .scache1_cpx_data_a(sctag1_cpx_data_a[149:0]),  
  .scache2_cpx_data_a(sctag2_cpx_data_a[149:0]),  
  .scache3_cpx_data_a(sctag3_cpx_data_a[149:0]),  
  .scache4_cpx_data_a(sctag4_cpx_data_a[149:0]),  
  .scache5_cpx_data_a(sctag5_cpx_data_a[149:0]),  
  .scache7_cpx_data_a(sctag7_cpx_data_a[149:0]),
  .scache6_cpx_data_a(sctag6_cpx_data_a[149:0]),  
  );  
  */

assign cpx_spc0_data_x_unused[3:0] = cpx_spc0_data_x_[149:146];
assign cpx_spc1_data_x_unused[3:0] = cpx_spc1_data_x_[149:146];
assign cpx_spc2_data_x_unused[3:0] = cpx_spc2_data_x_[149:146];
assign cpx_spc3_data_x_unused[3:0] = cpx_spc3_data_x_[149:146];
assign cpx_spc4_data_x_unused[3:0] = cpx_spc4_data_x_[149:146];
assign cpx_spc5_data_x_unused[3:0] = cpx_spc5_data_x_[149:146];
assign cpx_spc6_data_x_unused[3:0] = cpx_spc6_data_x_[149:146];
assign cpx_spc7_data_x_unused[3:0] = cpx_spc7_data_x_[149:146];

cpx_dpa cpx_dpa (
   /*AUTOINST*/
                 // Outputs
                 .cpx_spc0_data_x_      (cpx_spc0_data_x_[149:0]),
                 .cpx_spc1_data_x_      (cpx_spc1_data_x_[149:0]),
                 .cpx_spc2_data_x_      (cpx_spc2_data_x_[149:0]),
                 .cpx_spc3_data_x_      (cpx_spc3_data_x_[149:0]),
                 .cpx_spc4_data_x_      (cpx_spc4_data_x_[149:0]),
                 .cpx_spc5_data_x_      (cpx_spc5_data_x_[149:0]),
                 .cpx_spc6_data_x_      (cpx_spc6_data_x_[149:0]),
                 .cpx_spc7_data_x_      (cpx_spc7_data_x_[149:0]),
                 // Inputs
                 .arb0_grant_l_a          (arb0_grant_l_a[8:0]),
                 .arb0_q0_holdbar_l_a     (arb0_q0_holdbar_l_a[8:0]),
                 .arb0_qsel0_l_a          (arb0_qsel0_l_a[8:0]),
                 .arb0_qsel1_l_a          (arb0_qsel1_l_a[8:0]),
                 .arb0_shift_l_a          (arb0_shift_l_a[8:0]),
                 .arb1_grant_l_a          (arb1_grant_l_a[8:0]),
                 .arb1_q0_holdbar_l_a     (arb1_q0_holdbar_l_a[8:0]),
                 .arb1_qsel0_l_a          (arb1_qsel0_l_a[8:0]),
                 .arb1_qsel1_l_a          (arb1_qsel1_l_a[8:0]),
                 .arb1_shift_l_a          (arb1_shift_l_a[8:0]),
                 .arb2_grant_l_a          (arb2_grant_l_a[8:0]),
                 .arb2_q0_holdbar_l_a     (arb2_q0_holdbar_l_a[8:0]),
                 .arb2_qsel0_l_a          (arb2_qsel0_l_a[8:0]),
                 .arb2_qsel1_l_a          (arb2_qsel1_l_a[8:0]),
                 .arb2_shift_l_a          (arb2_shift_l_a[8:0]),
                 .arb3_grant_l_a          (arb3_grant_l_a[8:0]),
                 .arb3_q0_holdbar_l_a     (arb3_q0_holdbar_l_a[8:0]),
                 .arb3_qsel0_l_a          (arb3_qsel0_l_a[8:0]),
                 .arb3_qsel1_l_a          (arb3_qsel1_l_a[8:0]),
                 .arb3_shift_l_a          (arb3_shift_l_a[8:0]),
                 .arb4_grant_l_a          (arb4_grant_l_a[8:0]),
                 .arb4_q0_holdbar_l_a     (arb4_q0_holdbar_l_a[8:0]),
                 .arb4_qsel0_l_a          (arb4_qsel0_l_a[8:0]),
                 .arb4_qsel1_l_a          (arb4_qsel1_l_a[8:0]),
                 .arb4_shift_l_a          (arb4_shift_l_a[8:0]),
                 .arb5_grant_l_a          (arb5_grant_l_a[8:0]),
                 .arb5_q0_holdbar_l_a     (arb5_q0_holdbar_l_a[8:0]),
                 .arb5_qsel0_l_a          (arb5_qsel0_l_a[8:0]),
                 .arb5_qsel1_l_a          (arb5_qsel1_l_a[8:0]),
                 .arb5_shift_l_a          (arb5_shift_l_a[8:0]),
                 .arb6_grant_l_a          (arb6_grant_l_a[8:0]),
                 .arb6_q0_holdbar_l_a     (arb6_q0_holdbar_l_a[8:0]),
                 .arb6_qsel0_l_a          (arb6_qsel0_l_a[8:0]),
                 .arb6_qsel1_l_a          (arb6_qsel1_l_a[8:0]),
                 .arb6_shift_l_a          (arb6_shift_l_a[8:0]),
                 .arb7_grant_l_a          (arb7_grant_l_a[8:0]),
                 .arb7_q0_holdbar_l_a     (arb7_q0_holdbar_l_a[8:0]),
                 .arb7_qsel0_l_a          (arb7_qsel0_l_a[8:0]),
                 .arb7_qsel1_l_a          (arb7_qsel1_l_a[8:0]),
                 .arb7_shift_l_a          (arb7_shift_l_a[8:0]),
                 .arb0_grant_r_a          (arb0_grant_r_a[8:0]),
                 .arb0_q0_holdbar_r_a     (arb0_q0_holdbar_r_a[8:0]),
                 .arb0_qsel0_r_a          (arb0_qsel0_r_a[8:0]),
                 .arb0_qsel1_r_a          (arb0_qsel1_r_a[8:0]),
                 .arb0_shift_r_a          (arb0_shift_r_a[8:0]),
                 .arb1_grant_r_a          (arb1_grant_r_a[8:0]),
                 .arb1_q0_holdbar_r_a     (arb1_q0_holdbar_r_a[8:0]),
                 .arb1_qsel0_r_a          (arb1_qsel0_r_a[8:0]),
                 .arb1_qsel1_r_a          (arb1_qsel1_r_a[8:0]),
                 .arb1_shift_r_a          (arb1_shift_r_a[8:0]),
                 .arb2_grant_r_a          (arb2_grant_r_a[8:0]),
                 .arb2_q0_holdbar_r_a     (arb2_q0_holdbar_r_a[8:0]),
                 .arb2_qsel0_r_a          (arb2_qsel0_r_a[8:0]),
                 .arb2_qsel1_r_a          (arb2_qsel1_r_a[8:0]),
                 .arb2_shift_r_a          (arb2_shift_r_a[8:0]),
                 .arb3_grant_r_a          (arb3_grant_r_a[8:0]),
                 .arb3_q0_holdbar_r_a     (arb3_q0_holdbar_r_a[8:0]),
                 .arb3_qsel0_r_a          (arb3_qsel0_r_a[8:0]),
                 .arb3_qsel1_r_a          (arb3_qsel1_r_a[8:0]),
                 .arb3_shift_r_a          (arb3_shift_r_a[8:0]),
                 .arb4_grant_r_a          (arb4_grant_r_a[8:0]),
                 .arb4_q0_holdbar_r_a     (arb4_q0_holdbar_r_a[8:0]),
                 .arb4_qsel0_r_a          (arb4_qsel0_r_a[8:0]),
                 .arb4_qsel1_r_a          (arb4_qsel1_r_a[8:0]),
                 .arb4_shift_r_a          (arb4_shift_r_a[8:0]),
                 .arb5_grant_r_a          (arb5_grant_r_a[8:0]),
                 .arb5_q0_holdbar_r_a     (arb5_q0_holdbar_r_a[8:0]),
                 .arb5_qsel0_r_a          (arb5_qsel0_r_a[8:0]),
                 .arb5_qsel1_r_a          (arb5_qsel1_r_a[8:0]),
                 .arb5_shift_r_a          (arb5_shift_r_a[8:0]),
                 .arb6_grant_r_a          (arb6_grant_r_a[8:0]),
                 .arb6_q0_holdbar_r_a     (arb6_q0_holdbar_r_a[8:0]),
                 .arb6_qsel0_r_a          (arb6_qsel0_r_a[8:0]),
                 .arb6_qsel1_r_a          (arb6_qsel1_r_a[8:0]),
                 .arb6_shift_r_a          (arb6_shift_r_a[8:0]),
                 .arb7_grant_r_a          (arb7_grant_r_a[8:0]),
                 .arb7_q0_holdbar_r_a     (arb7_q0_holdbar_r_a[8:0]),
                 .arb7_qsel0_r_a          (arb7_qsel0_r_a[8:0]),
                 .arb7_qsel1_r_a          (arb7_qsel1_r_a[8:0]),
                 .arb7_shift_r_a          (arb7_shift_r_a[8:0]),
                 .io_cpx_data_a           (io_cpx_data_a[149:0]), // Templated
                 .scache0_cpx_data_a      (sctag0_cpx_data_a[149:0]), // Templated
                 .scache1_cpx_data_a      (sctag1_cpx_data_a[149:0]), // Templated
                 .scache2_cpx_data_a      (sctag2_cpx_data_a[149:0]), // Templated
                 .scache3_cpx_data_a      (sctag3_cpx_data_a[149:0]), // Templated
                 .scache4_cpx_data_a      (sctag4_cpx_data_a[149:0]), // Templated
                 .scache5_cpx_data_a      (sctag5_cpx_data_a[149:0]), // Templated
                 .scache6_cpx_data_a      (sctag6_cpx_data_a[149:0]), // Templated
                 .scache7_cpx_data_a      (sctag7_cpx_data_a[149:0]), // Templated
                 .scan_in                 (cpx_dpa_scanin),
                 .scan_out                (cpx_dpa_scanout),
                 .l2clk                   (l2clk),
                 .tcu_scan_en_t             (tcu_scan_en_dpa_t),
                 .tcu_pce_ov_t              (tcu_pce_ov_dpa_t),
                 .ccx_aclk_t                (ccx_aclk_dpa_t),
                 .ccx_bclk_t                (ccx_bclk_dpa_t),
                 .tcu_scan_en_b             (tcu_scan_en_dpa_b),
                 .tcu_pce_ov_b              (tcu_pce_ov_dpa_b),
                 .ccx_aclk_b                (ccx_aclk_dpa_b),
                 .ccx_bclk_b                (ccx_bclk_dpa_b)
                 );

// invert and flop the output signals
// These are placed right next to the CCX core datapath

cpx_bfd_dp bfd0 (
                 // Outputs
                 .cpx_spc_data_cx2      (cpx_spc0_data_cx2_prebuf[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_lt),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_lt),
                 .ccx_aclk_out          (ccx_aclk_bfd_lt),
                 .ccx_bclk_out          (ccx_bclk_bfd_lt),
                 // Inputs
                 .cpx_spc_data_x_       (cpx_spc0_data_x_[145:0]), // Templated
                 .scan_in(bfd0_scanin),
                 .scan_out(bfd0_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_1),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_1),
                 .ccx_aclk          (ccx_aclk_bfd_1),
                 .ccx_bclk          (ccx_bclk_bfd_1)
                 );

// Output buffer at the pins
cpx_ob1_dp ob_0 (
                  .cpx_spc_data_cx2        (cpx_spc0_data_cx2[145:0]),
                  .cpx_spc_data_cx2_prebuf (cpx_spc0_data_cx2_prebuf[145:0])
                  );


cpx_bfd_dp bfd1 (
                 // Outputs
                 .cpx_spc_data_cx2      (cpx_spc1_data_cx2_prebuf[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_1),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_1),
                 .ccx_aclk_out          (ccx_aclk_bfd_1),
                 .ccx_bclk_out          (ccx_bclk_bfd_1),
                 // Inputs
                 .cpx_spc_data_x_       (cpx_spc1_data_x_[145:0]), // Templated
                 .scan_in(bfd1_scanin),
                 .scan_out(bfd1_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_t),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_t),
                 .ccx_aclk          (ccx_aclk_bfd_t),
                 .ccx_bclk          (ccx_bclk_bfd_t)
                 );

// Output buffer at the pins
cpx_ob1_dp ob_1 (
                  .cpx_spc_data_cx2        (cpx_spc1_data_cx2[145:0]),
                  .cpx_spc_data_cx2_prebuf (cpx_spc1_data_cx2_prebuf[145:0])
                  );

cpx_bfd_dp bfd2 (
                 // Outputs
                 .cpx_spc_data_cx2      (cpx_spc2_data_cx2_prebuf[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_lb),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_lb),
                 .ccx_aclk_out          (ccx_aclk_bfd_lb),
                 .ccx_bclk_out          (ccx_bclk_bfd_lb),
                 // Inputs
                 .cpx_spc_data_x_       (cpx_spc2_data_x_[145:0]), // Templated
                 .scan_in(bfd2_scanin),
                 .scan_out(bfd2_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_3),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_3),
                 .ccx_aclk          (ccx_aclk_bfd_3),
                 .ccx_bclk          (ccx_bclk_bfd_3)
                 );

// Output buffer at the pins
cpx_ob1_dp ob_2 (
                  .cpx_spc_data_cx2        (cpx_spc2_data_cx2[145:0]),
                  .cpx_spc_data_cx2_prebuf (cpx_spc2_data_cx2_prebuf[145:0])
                  );

cpx_bfd_dp bfd3 (
                 // Outputs
                 .cpx_spc_data_cx2      (cpx_spc3_data_cx2_prebuf[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_3),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_3),
                 .ccx_aclk_out          (ccx_aclk_bfd_3),
                 .ccx_bclk_out          (ccx_bclk_bfd_3),
                 // Inputs
                 .cpx_spc_data_x_       (cpx_spc3_data_x_[145:0]), // Templated
                 .scan_in(bfd3_scanin),
                 .scan_out(bfd3_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_b),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_b),
                 .ccx_aclk          (ccx_aclk_bfd_b),
                 .ccx_bclk          (ccx_bclk_bfd_b)
                 );

// Output buffer at the pins
cpx_ob1_dp ob_3 (
                  .cpx_spc_data_cx2        (cpx_spc3_data_cx2[145:0]),
                  .cpx_spc_data_cx2_prebuf (cpx_spc3_data_cx2_prebuf[145:0])
                  );

cpx_bfd_dp bfd4 (
                 // Outputs
                 .cpx_spc_data_cx2      (cpx_spc4_data_cx2_prebuf[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_rt),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_rt),
                 .ccx_aclk_out          (ccx_aclk_bfd_rt),
                 .ccx_bclk_out          (ccx_bclk_bfd_rt),
                 // Inputs
                 .cpx_spc_data_x_       (cpx_spc4_data_x_[145:0]), // Templated
                 .scan_in(bfd4_scanin),
                 .scan_out(bfd4_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_5),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_5),
                 .ccx_aclk          (ccx_aclk_bfd_5),
                 .ccx_bclk          (ccx_bclk_bfd_5)
                 );

// Output buffer at the pins
cpx_ob2_dp ob_4 (
                  .cpx_spc_data_cx2        (cpx_spc4_data_cx2[145:0]),
                  .cpx_spc_data_cx2_prebuf (cpx_spc4_data_cx2_prebuf[145:0])
                  );

cpx_bfd_dp bfd5 (
                 // Outputs
                 .cpx_spc_data_cx2      (cpx_spc5_data_cx2_prebuf[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_5),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_5),
                 .ccx_aclk_out          (ccx_aclk_bfd_5),
                 .ccx_bclk_out          (ccx_bclk_bfd_5),
                 // Inputs
                 .cpx_spc_data_x_       (cpx_spc5_data_x_[145:0]), // Templated
                 .scan_in(bfd5_scanin),
                 .scan_out(bfd5_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_t),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_t),
                 .ccx_aclk          (ccx_aclk_bfd_t),
                 .ccx_bclk          (ccx_bclk_bfd_t)
                 );

// Output buffer at the pins
cpx_ob2_dp ob_5 (
                  .cpx_spc_data_cx2        (cpx_spc5_data_cx2[145:0]),
                  .cpx_spc_data_cx2_prebuf (cpx_spc5_data_cx2_prebuf[145:0])
                  );

cpx_bfd_dp bfd6 (
                 // Outputs
                 .cpx_spc_data_cx2      (cpx_spc6_data_cx2_prebuf[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_rb),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_rb),
                 .ccx_aclk_out          (ccx_aclk_bfd_rb),
                 .ccx_bclk_out          (ccx_bclk_bfd_rb),
                 // Inputs
                 .cpx_spc_data_x_       (cpx_spc6_data_x_[145:0]), // Templated
                 .scan_in(bfd6_scanin),
                 .scan_out(bfd6_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_7),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_7),
                 .ccx_aclk          (ccx_aclk_bfd_7),
                 .ccx_bclk          (ccx_bclk_bfd_7)
                 );

// Output buffer at the pins
cpx_ob2_dp ob_6 (
                  .cpx_spc_data_cx2        (cpx_spc6_data_cx2[145:0]),
                  .cpx_spc_data_cx2_prebuf (cpx_spc6_data_cx2_prebuf[145:0])
                  );

cpx_bfd_dp bfd7 (
                 // Outputs
                 .cpx_spc_data_cx2      (cpx_spc7_data_cx2_prebuf[145:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_7),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_7),
                 .ccx_aclk_out          (ccx_aclk_bfd_7),
                 .ccx_bclk_out          (ccx_bclk_bfd_7),
                 // Inputs
                 .cpx_spc_data_x_       (cpx_spc7_data_x_[145:0]), // Templated
                 .scan_in(bfd7_scanin),
                 .scan_out(bfd7_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_b),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_b),
                 .ccx_aclk          (ccx_aclk_bfd_b),
                 .ccx_bclk          (ccx_bclk_bfd_b)
                 );

// Output buffer at the pins
cpx_ob2_dp ob_7 (
                  .cpx_spc_data_cx2        (cpx_spc7_data_cx2[145:0]),
                  .cpx_spc_data_cx2_prebuf (cpx_spc7_data_cx2_prebuf[145:0])
                  );


// buffer req signals feeding left arbiters
cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct0     (
	.din	({sctag0_cpx_req_cq_0_l[7:0],sctag0_cpx_atom_cq_0_l,sctag0_cpx_atom_cq_0_l}),
	.dout	({sctag0_cpx_req_lq[7:0],  sctag0_cpx_atom_lq_t,sctag0_cpx_atom_lq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct1     (
	.din	({sctag1_cpx_req_cq_0_l[7:0],sctag1_cpx_atom_cq_0_l,sctag1_cpx_atom_cq_0_l}),
	.dout	({sctag1_cpx_req_lq[7:0],  sctag1_cpx_atom_lq_t,sctag1_cpx_atom_lq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct2     (
	.din	({sctag2_cpx_req_cq_0_l[7:0],sctag2_cpx_atom_cq_0_l,sctag2_cpx_atom_cq_0_l}),
	.dout	({sctag2_cpx_req_lq[7:0],  sctag2_cpx_atom_lq_t,sctag2_cpx_atom_lq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct3     (
	.din	({sctag3_cpx_req_cq_0_l[7:0],sctag3_cpx_atom_cq_0_l,sctag3_cpx_atom_cq_0_l}),
	.dout	({sctag3_cpx_req_lq[7:0],  sctag3_cpx_atom_lq_t,sctag3_cpx_atom_lq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct4     (
	.din	({sctag4_cpx_req_cq_0_l[7:0],sctag4_cpx_atom_cq_0_l,sctag4_cpx_atom_cq_0_l}),
	.dout	({sctag4_cpx_req_lq[7:0],  sctag4_cpx_atom_lq_t,sctag4_cpx_atom_lq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct5     (
	.din	({sctag5_cpx_req_cq_0_l[7:0],sctag5_cpx_atom_cq_0_l,sctag5_cpx_atom_cq_0_l}),
	.dout	({sctag5_cpx_req_lq[7:0],  sctag5_cpx_atom_lq_t,sctag5_cpx_atom_lq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct6     (
	.din	({sctag6_cpx_req_cq_0_l[7:0],sctag6_cpx_atom_cq_0_l,sctag6_cpx_atom_cq_0_l}),
	.dout	({sctag6_cpx_req_lq[7:0],  sctag6_cpx_atom_lq_t,sctag6_cpx_atom_lq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct7     (
	.din	({sctag7_cpx_req_cq_0_l[7:0],sctag7_cpx_atom_cq_0_l,sctag7_cpx_atom_cq_0_l}),
	.dout	({sctag7_cpx_req_lq[7:0],  sctag7_cpx_atom_lq_t,sctag7_cpx_atom_lq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_8 i_bufq_l_io     (
	.din	({io_cpx_req_cq_d1[7:0]}),
	.dout	({io_cpx_req_lq[7:0]})
);


//buffer the high fanout signals going to arb top left
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_lt     (
	.din	({ccx_aclk_bfd_lt,ccx_bclk_bfd_lt, tcu_pce_ov_bfd_lt, tcu_scan_en_bfd_lt}),
	.dout	({ccx_aclk_arb_lt,ccx_bclk_arb_lt,tcu_pce_ov_arb_lt,tcu_scan_en_arb_lt})
);

//buffer the high fanout signals going to arb bot left
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_lb     (
	.din	({ccx_aclk_bfd_lb,ccx_bclk_bfd_lb, tcu_pce_ov_bfd_lb, tcu_scan_en_bfd_lb}),
	.dout	({ccx_aclk_arb_lb,ccx_bclk_arb_lb,tcu_pce_ov_arb_lb,tcu_scan_en_arb_lb})
);

//buffer the high fanout signals going to arb top right
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_rt     (
	.din	({ccx_aclk_bfd_rt,ccx_bclk_bfd_rt, tcu_pce_ov_bfd_rt, tcu_scan_en_bfd_rt}),
	.dout	({ccx_aclk_arb_rt,ccx_bclk_arb_rt,tcu_pce_ov_arb_rt,tcu_scan_en_arb_rt})
);

//buffer the high fanout signals going to arb bot right
cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_rb     (
	.din	({ccx_aclk_bfd_rb,ccx_bclk_bfd_rb, tcu_pce_ov_bfd_rb, tcu_scan_en_bfd_rb}),
	.dout	({ccx_aclk_arb_rb,ccx_bclk_arb_rb,tcu_pce_ov_arb_rb,tcu_scan_en_arb_rb})
);

/*
 ccx_arb  AUTO_TEMPLATE(
 // Outputs
 .arb_grant_a		(arb@_grant_l_a[8:0]),
 .arb_q0_holdbar_a		(arb@_q0_holdbar_l_a[8:0]),
 .arb_qsel0_a		(arb@_qsel0_l_a[8:0]),
 .arb_qsel1_a		(arb@_qsel1_l_a[8:0]),
 .arb_shift_a		(arb@_shift_l_a[8:0]),
 .arb_src0_grant_a		(cpx_sctag0_grant_a[@]),
 .arb_src1_grant_a		(cpx_sctag1_grant_a[@]),
 .arb_src2_grant_a		(cpx_sctag2_grant_a[@]),
 .arb_src3_grant_a		(cpx_sctag3_grant_a[@]),
 .arb_src4_grant_a		(cpx_sctag4_grant_a[@]),
 .arb_src5_grant_a		(cpx_sctag5_grant_a[@]),
 .arb_src6_grant_a		(cpx_sctag6_grant_a[@]),
 .arb_src7_grant_a		(cpx_sctag7_grant_a[@]),
 .arb_src8_grant_a		(cpx_io_grant_a[@]),
 .ccx_dest_data_rdy_a	(),
 .ccx_dest_atom_a	(),
 // Inputs
 .src0_arb_atom_q		(sctag0_cpx_atom_lq),
 .src0_arb_req_q		(sctag0_cpx_req_lq[@]),
 .src1_arb_atom_q		(sctag1_cpx_atom_lq),
 .src1_arb_req_q		(sctag1_cpx_req_lq[@]),
 .src2_arb_atom_q		(sctag2_cpx_atom_lq),
 .src2_arb_req_q		(sctag2_cpx_req_lq[@]),
 .src3_arb_atom_q		(sctag3_cpx_atom_lq),
 .src3_arb_req_q		(sctag3_cpx_req_lq[@]),
 .src4_arb_atom_q		(sctag4_cpx_atom_lq),
 .src4_arb_req_q		(sctag4_cpx_req_lq[@]),
 .src5_arb_atom_q		(sctag5_cpx_atom_lq),
 .src5_arb_req_q		(sctag5_cpx_req_lq[@]),
 .src6_arb_atom_q		(sctag6_cpx_atom_lq),
 .src6_arb_req_q		(sctag6_cpx_req_lq[@]),
 .src7_arb_atom_q		(sctag7_cpx_atom_lq),
 .src7_arb_req_q		(sctag7_cpx_req_lq[@]),
 .src8_arb_atom_q		(1'b0),
 .src8_arb_req_q		(io_cpx_req_lq[@]),
 .stall_q_d1			(1'b0));
 */
//

ccx_arb cpx_arbl0 (
                  // Outputs
                  .arb_grant_a          (arb0_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb0_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb0_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb0_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb0_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a[0]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a[0]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a[0]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a[0]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a_unused[0]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a_unused[0]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a_unused[0]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a_unused[0]), // Templated
                  .arb_src8_grant_a     (cpx_io_grant_a[0]),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_l_unused[0]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_l_unused[0]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_lq_t),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_lq[0]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_lq_t),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_lq[0]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_lq_t),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_lq[0]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_lq_t),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_lq[0]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_lq_t),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_lq[0]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_lq_t),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_lq[0]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_lq_t),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_lq[0]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_lq_t),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_lq[0]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_lq[0]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbl0_scanin),
                  .scan_out(cpx_arbl0_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );

ccx_arb cpx_arbl1 (
                  // Outputs
                  .arb_grant_a          (arb1_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb1_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb1_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb1_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb1_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a[1]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a[1]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a[1]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a[1]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a_unused[1]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a_unused[1]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a_unused[1]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a_unused[1]), // Templated
                  .arb_src8_grant_a     (cpx_io_grant_a[1]),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_l_unused[1]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_l_unused[1]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_lq_t),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_lq[1]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_lq_t),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_lq[1]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_lq_t),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_lq[1]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_lq_t),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_lq[1]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_lq_t),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_lq[1]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_lq_t),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_lq[1]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_lq_t),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_lq[1]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_lq_t),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_lq[1]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_lq[1]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbl1_scanin),
                  .scan_out(cpx_arbl1_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );


ccx_arb cpx_arbl2 (
                  // Outputs
                  .arb_grant_a          (arb2_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb2_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb2_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb2_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb2_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a[2]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a[2]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a[2]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a[2]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a_unused[2]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a_unused[2]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a_unused[2]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a_unused[2]), // Templated
                  .arb_src8_grant_a     (cpx_io_grant_a[2]),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_l_unused[2]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_l_unused[2]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_lq_b),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_lq[2]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_lq_b),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_lq[2]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_lq_b),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_lq[2]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_lq_b),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_lq[2]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_lq_b),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_lq[2]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_lq_b),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_lq[2]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_lq_b),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_lq[2]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_lq_b),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_lq[2]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_lq[2]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbl2_scanin),
                  .scan_out(cpx_arbl2_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lb),
                 .ccx_aclk                (ccx_aclk_arb_lb),
                 .ccx_bclk                (ccx_bclk_arb_lb)
                 );


ccx_arb cpx_arbl3 (
                  // Outputs
                  .arb_grant_a          (arb3_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb3_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb3_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb3_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb3_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a[3]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a[3]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a[3]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a[3]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a_unused[3]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a_unused[3]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a_unused[3]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a_unused[3]), // Templated
                  .arb_src8_grant_a     (cpx_io_grant_a[3]),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_l_unused[3]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_l_unused[3]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_lq_b),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_lq[3]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_lq_b),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_lq[3]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_lq_b),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_lq[3]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_lq_b),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_lq[3]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_lq_b),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_lq[3]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_lq_b),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_lq[3]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_lq_b),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_lq[3]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_lq_b),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_lq[3]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_lq[3]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbl3_scanin),
                  .scan_out(cpx_arbl3_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lb),
                 .ccx_aclk                (ccx_aclk_arb_lb),
                 .ccx_bclk                (ccx_bclk_arb_lb)
                 );


ccx_arb cpx_arbl4 (
                  // Outputs
                  .arb_grant_a          (arb4_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb4_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb4_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb4_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb4_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a[4]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a[4]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a[4]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a[4]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a_unused[4]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a_unused[4]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a_unused[4]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a_unused[4]), // Templated
                  .arb_src8_grant_a     (cpx_io_grant_a[4]),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_l_unused[4]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_l_unused[4]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_lq_t),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_lq[4]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_lq_t),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_lq[4]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_lq_t),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_lq[4]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_lq_t),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_lq[4]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_lq_t),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_lq[4]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_lq_t),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_lq[4]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_lq_t),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_lq[4]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_lq_t),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_lq[4]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_lq[4]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbl4_scanin),
                  .scan_out(cpx_arbl4_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );


ccx_arb cpx_arbl5 (
                  // Outputs
                  .arb_grant_a          (arb5_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb5_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb5_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb5_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb5_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a[5]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a[5]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a[5]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a[5]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a_unused[5]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a_unused[5]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a_unused[5]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a_unused[5]), // Templated
                  .arb_src8_grant_a     (cpx_io_grant_a[5]),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_l_unused[5]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_l_unused[5]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_lq_t),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_lq[5]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_lq_t),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_lq[5]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_lq_t),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_lq[5]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_lq_t),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_lq[5]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_lq_t),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_lq[5]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_lq_t),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_lq[5]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_lq_t),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_lq[5]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_lq_t),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_lq[5]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_lq[5]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbl5_scanin),
                  .scan_out(cpx_arbl5_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );


ccx_arb cpx_arbl6 (
                  // Outputs
                  .arb_grant_a          (arb6_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb6_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb6_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb6_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb6_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a[6]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a[6]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a[6]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a[6]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a_unused[6]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a_unused[6]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a_unused[6]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a_unused[6]), // Templated
                  .arb_src8_grant_a     (cpx_io_grant_a[6]),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_l_unused[6]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_l_unused[6]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_lq_b),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_lq[6]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_lq_b),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_lq[6]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_lq_b),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_lq[6]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_lq_b),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_lq[6]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_lq_b),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_lq[6]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_lq_b),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_lq[6]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_lq_b),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_lq[6]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_lq_b),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_lq[6]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_lq[6]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbl6_scanin),
                  .scan_out(cpx_arbl6_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lb),
                 .ccx_aclk                (ccx_aclk_arb_lb),
                 .ccx_bclk                (ccx_bclk_arb_lb)
                 );


ccx_arb cpx_arbl7 (
                  // Outputs
                  .arb_grant_a          (arb7_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb7_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb7_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb7_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb7_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a[7]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a[7]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a[7]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a[7]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a_unused[7]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a_unused[7]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a_unused[7]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a_unused[7]), // Templated
                  .arb_src8_grant_a     (cpx_io_grant_a[7]),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_l_unused[7]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_l_unused[7]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_lq_b),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_lq[7]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_lq_b),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_lq[7]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_lq_b),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_lq[7]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_lq_b),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_lq[7]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_lq_b),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_lq[7]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_lq_b),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_lq[7]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_lq_b),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_lq[7]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_lq_b),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_lq[7]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_lq[7]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbl7_scanin),
                  .scan_out(cpx_arbl7_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lb),
                 .ccx_aclk                (ccx_aclk_arb_lb),
                 .ccx_bclk                (ccx_bclk_arb_lb)
                 );

// buffer req signals feeding right arbiters
cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct0     (
	.din	({sctag0_cpx_req_cq_0_r[7:0],sctag0_cpx_atom_cq_0_r,sctag0_cpx_atom_cq_0_r}),
	.dout	({sctag0_cpx_req_rq[7:0],  sctag0_cpx_atom_rq_t,sctag0_cpx_atom_rq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct1     (
	.din	({sctag1_cpx_req_cq_0_r[7:0],sctag1_cpx_atom_cq_0_r,sctag1_cpx_atom_cq_0_r}),
	.dout	({sctag1_cpx_req_rq[7:0],  sctag1_cpx_atom_rq_t,sctag1_cpx_atom_rq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct2     (
	.din	({sctag2_cpx_req_cq_0_r[7:0],sctag2_cpx_atom_cq_0_r,sctag2_cpx_atom_cq_0_r}),
	.dout	({sctag2_cpx_req_rq[7:0],  sctag2_cpx_atom_rq_t,sctag2_cpx_atom_rq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct3     (
	.din	({sctag3_cpx_req_cq_0_r[7:0],sctag3_cpx_atom_cq_0_r,sctag3_cpx_atom_cq_0_r}),
	.dout	({sctag3_cpx_req_rq[7:0],  sctag3_cpx_atom_rq_t,sctag3_cpx_atom_rq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct4     (
	.din	({sctag4_cpx_req_cq_0_r[7:0],sctag4_cpx_atom_cq_0_r,sctag4_cpx_atom_cq_0_r}),
	.dout	({sctag4_cpx_req_rq[7:0],  sctag4_cpx_atom_rq_t,sctag4_cpx_atom_rq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct5     (
	.din	({sctag5_cpx_req_cq_0_r[7:0],sctag5_cpx_atom_cq_0_r,sctag5_cpx_atom_cq_0_r}),
	.dout	({sctag5_cpx_req_rq[7:0],  sctag5_cpx_atom_rq_t,sctag5_cpx_atom_rq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct6     (
	.din	({sctag6_cpx_req_cq_0_r[7:0],sctag6_cpx_atom_cq_0_r,sctag6_cpx_atom_cq_0_r}),
	.dout	({sctag6_cpx_req_rq[7:0],  sctag6_cpx_atom_rq_t,sctag6_cpx_atom_rq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct7     (
	.din	({sctag7_cpx_req_cq_0_r[7:0],sctag7_cpx_atom_cq_0_r,sctag7_cpx_atom_cq_0_r}),
	.dout	({sctag7_cpx_req_rq[7:0],  sctag7_cpx_atom_rq_t,sctag7_cpx_atom_rq_b})
);

cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_8 i_bufq_r_io     (
	.din	({io_cpx_req_cq_d1[7:0]}),
	.dout	({io_cpx_req_rq[7:0]})
);


/*
 ccx_arb  AUTO_TEMPLATE(
 // Outputs
 .arb_grant_a		(arb@_grant_r_a[8:0]),
 .arb_q0_holdbar_a		(arb@_q0_holdbar_r_a[8:0]),
 .arb_qsel0_a		(arb@_qsel0_r_a[8:0]),
 .arb_qsel1_a		(arb@_qsel1_r_a[8:0]),
 .arb_shift_a		(arb@_shift_r_a[8:0]),
 .arb_src0_grant_a		(),
 .arb_src1_grant_a		(),
 .arb_src2_grant_a		(),
 .arb_src3_grant_a		(),
 .arb_src4_grant_a		(),
 .arb_src5_grant_a		(),
 .arb_src6_grant_a		(),
 .arb_src7_grant_a		(),
 .arb_src8_grant_a		(),
 .ccx_dest_data_rdy_a	(),
 .ccx_dest_atom_a	(),
 // Inputs
 .src0_arb_atom_q		(sctag0_cpx_atom_rq),
 .src0_arb_req_q		(sctag0_cpx_req_rq[@]),
 .src1_arb_atom_q		(sctag1_cpx_atom_rq),
 .src1_arb_req_q		(sctag1_cpx_req_rq[@]),
 .src2_arb_atom_q		(sctag2_cpx_atom_rq),
 .src2_arb_req_q		(sctag2_cpx_req_rq[@]),
 .src3_arb_atom_q		(sctag3_cpx_atom_rq),
 .src3_arb_req_q		(sctag3_cpx_req_rq[@]),
 .src4_arb_atom_q		(sctag4_cpx_atom_rq),
 .src4_arb_req_q		(sctag4_cpx_req_rq[@]),
 .src5_arb_atom_q		(sctag5_cpx_atom_rq),
 .src5_arb_req_q		(sctag5_cpx_req_rq[@]),
 .src6_arb_atom_q		(sctag6_cpx_atom_rq),
 .src6_arb_req_q		(sctag6_cpx_req_rq[@]),
 .src7_arb_atom_q		(sctag7_cpx_atom_rq),
 .src7_arb_req_q		(sctag7_cpx_req_rq[@]),
 .src8_arb_atom_q		(1'b0),
 .src8_arb_req_q		(io_cpx_req_rq[@]),
 .stall_q_d1			(1'b0));
 */
//

ccx_arb cpx_arbr0 (
                  // Outputs
                  .arb_grant_a          (arb0_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb0_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb0_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb0_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb0_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a_unused[0]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a_unused[0]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a_unused[0]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a_unused[0]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a[0]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a[0]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a[0]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a[0]), // Templated
                  .arb_src8_grant_a     (cpx_sctag8_grant_a_unused[0]          ),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_r_unused[0]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_r_unused[0]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_rq_t),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_rq[0]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_rq_t),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_rq[0]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_rq_t),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_rq[0]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_rq_t),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_rq[0]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_rq_t),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_rq[0]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_rq_t),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_rq[0]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_rq_t),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_rq[0]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_rq_t),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_rq[0]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_rq[0]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbr0_scanin),
                  .scan_out(cpx_arbr0_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                 .ccx_aclk                (ccx_aclk_arb_rt),
                 .ccx_bclk                (ccx_bclk_arb_rt)
                 );


ccx_arb cpx_arbr1 (
                  // Outputs
                  .arb_grant_a          (arb1_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb1_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb1_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb1_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb1_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a_unused[1]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a_unused[1]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a_unused[1]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a_unused[1]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a[1]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a[1]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a[1]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a[1]), // Templated
                  .arb_src8_grant_a     (cpx_sctag8_grant_a_unused[1]   ),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_r_unused[1]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_r_unused[1]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_rq_t),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_rq[1]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_rq_t),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_rq[1]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_rq_t),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_rq[1]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_rq_t),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_rq[1]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_rq_t),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_rq[1]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_rq_t),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_rq[1]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_rq_t),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_rq[1]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_rq_t),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_rq[1]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_rq[1]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbr1_scanin),
                  .scan_out(cpx_arbr1_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                 .ccx_aclk                (ccx_aclk_arb_rt),
                 .ccx_bclk                (ccx_bclk_arb_rt)
                 );

ccx_arb cpx_arbr2 (
                  // Outputs
                  .arb_grant_a          (arb2_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb2_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb2_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb2_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb2_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a_unused[2]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a_unused[2]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a_unused[2]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a_unused[2]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a[2]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a[2]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a[2]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a[2]), // Templated
                  .arb_src8_grant_a     (cpx_sctag8_grant_a_unused[2]   ),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_r_unused[2]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_r_unused[2]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_rq_b),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_rq[2]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_rq_b),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_rq[2]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_rq_b),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_rq[2]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_rq_b),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_rq[2]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_rq_b),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_rq[2]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_rq_b),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_rq[2]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_rq_b),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_rq[2]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_rq_b),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_rq[2]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_rq[2]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbr2_scanin),
                  .scan_out(cpx_arbr2_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rb),
                 .ccx_aclk                (ccx_aclk_arb_rb),
                 .ccx_bclk                (ccx_bclk_arb_rb)
                 );

ccx_arb cpx_arbr3 (
                  // Outputs
                  .arb_grant_a          (arb3_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb3_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb3_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb3_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb3_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a_unused[3]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a_unused[3]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a_unused[3]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a_unused[3]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a[3]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a[3]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a[3]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a[3]), // Templated
                  .arb_src8_grant_a     (cpx_sctag8_grant_a_unused[3]   ),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_r_unused[3]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_r_unused[3]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_rq_b),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_rq[3]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_rq_b),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_rq[3]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_rq_b),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_rq[3]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_rq_b),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_rq[3]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_rq_b),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_rq[3]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_rq_b),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_rq[3]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_rq_b),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_rq[3]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_rq_b),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_rq[3]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_rq[3]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbr3_scanin),
                  .scan_out(cpx_arbr3_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rb),
                 .ccx_aclk                (ccx_aclk_arb_rb),
                 .ccx_bclk                (ccx_bclk_arb_rb)
                 );

ccx_arb cpx_arbr4 (
                  // Outputs
                  .arb_grant_a          (arb4_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb4_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb4_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb4_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb4_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a_unused[4]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a_unused[4]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a_unused[4]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a_unused[4]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a[4]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a[4]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a[4]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a[4]), // Templated
                  .arb_src8_grant_a     (cpx_sctag8_grant_a_unused[4]   ),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_r_unused[4]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_r_unused[4]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_rq_t),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_rq[4]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_rq_t),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_rq[4]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_rq_t),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_rq[4]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_rq_t),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_rq[4]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_rq_t),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_rq[4]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_rq_t),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_rq[4]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_rq_t),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_rq[4]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_rq_t),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_rq[4]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_rq[4]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbr4_scanin),
                  .scan_out(cpx_arbr4_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                 .ccx_aclk                (ccx_aclk_arb_rt),
                 .ccx_bclk                (ccx_bclk_arb_rt)
                 );

ccx_arb cpx_arbr5 (
                  // Outputs
                  .arb_grant_a          (arb5_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb5_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb5_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb5_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb5_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a_unused[5]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a_unused[5]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a_unused[5]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a_unused[5]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a[5]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a[5]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a[5]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a[5]), // Templated
                  .arb_src8_grant_a     (cpx_sctag8_grant_a_unused[5]   ),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_r_unused[5]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_r_unused[5]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_rq_t),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_rq[5]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_rq_t),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_rq[5]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_rq_t),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_rq[5]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_rq_t),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_rq[5]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_rq_t),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_rq[5]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_rq_t),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_rq[5]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_rq_t),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_rq[5]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_rq_t),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_rq[5]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_rq[5]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbr5_scanin),
                  .scan_out(cpx_arbr5_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                 .ccx_aclk                (ccx_aclk_arb_rt),
                 .ccx_bclk                (ccx_bclk_arb_rt)
                 );

ccx_arb cpx_arbr6 (
                  // Outputs
                  .arb_grant_a          (arb6_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb6_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb6_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb6_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb6_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a_unused[6]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a_unused[6]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a_unused[6]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a_unused[6]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a[6]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a[6]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a[6]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a[6]), // Templated
                  .arb_src8_grant_a     (cpx_sctag8_grant_a_unused[6]   ),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_r_unused[6]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_r_unused[6]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_rq_b),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_rq[6]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_rq_b),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_rq[6]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_rq_b),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_rq[6]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_rq_b),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_rq[6]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_rq_b),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_rq[6]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_rq_b),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_rq[6]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_rq_b),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_rq[6]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_rq_b),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_rq[6]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_rq[6]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbr6_scanin),
                  .scan_out(cpx_arbr6_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rb),
                 .ccx_aclk                (ccx_aclk_arb_rb),
                 .ccx_bclk                (ccx_bclk_arb_rb)
                 );

ccx_arb cpx_arbr7 (
                  // Outputs
                  .arb_grant_a          (arb7_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb7_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb7_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb7_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb7_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (cpx_sctag0_grant_a_unused[7]), // Templated
                  .arb_src1_grant_a     (cpx_sctag1_grant_a_unused[7]), // Templated
                  .arb_src2_grant_a     (cpx_sctag2_grant_a_unused[7]), // Templated
                  .arb_src3_grant_a     (cpx_sctag3_grant_a_unused[7]), // Templated
                  .arb_src4_grant_a     (cpx_sctag4_grant_a[7]), // Templated
                  .arb_src5_grant_a     (cpx_sctag5_grant_a[7]), // Templated
                  .arb_src6_grant_a     (cpx_sctag6_grant_a[7]), // Templated
                  .arb_src7_grant_a     (cpx_sctag7_grant_a[7]), // Templated
                  .arb_src8_grant_a     (cpx_sctag8_grant_a_unused[7]   ),     // Templated
                  .ccx_dest_atom_a      (ccx_dest_atom_a_r_unused[7]    ),                      // Templated
                  .ccx_dest_data_rdy_a  (ccx_dest_data_rdy_a_r_unused[7]),                      // Templated
                  // Inputs
                  .src0_arb_atom_q      (sctag0_cpx_atom_rq_b),    // Templated
                  .src0_arb_req_q       (sctag0_cpx_req_rq[7]),  // Templated
                  .src1_arb_atom_q      (sctag1_cpx_atom_rq_b),    // Templated
                  .src1_arb_req_q       (sctag1_cpx_req_rq[7]),  // Templated
                  .src2_arb_atom_q      (sctag2_cpx_atom_rq_b),    // Templated
                  .src2_arb_req_q       (sctag2_cpx_req_rq[7]),  // Templated
                  .src3_arb_atom_q      (sctag3_cpx_atom_rq_b),    // Templated
                  .src3_arb_req_q       (sctag3_cpx_req_rq[7]),  // Templated
                  .src4_arb_atom_q      (sctag4_cpx_atom_rq_b),    // Templated
                  .src4_arb_req_q       (sctag4_cpx_req_rq[7]),  // Templated
                  .src5_arb_atom_q      (sctag5_cpx_atom_rq_b),    // Templated
                  .src5_arb_req_q       (sctag5_cpx_req_rq[7]),  // Templated
                  .src6_arb_atom_q      (sctag6_cpx_atom_rq_b),    // Templated
                  .src6_arb_req_q       (sctag6_cpx_req_rq[7]),  // Templated
                  .src7_arb_atom_q      (sctag7_cpx_atom_rq_b),    // Templated
                  .src7_arb_req_q       (sctag7_cpx_req_rq[7]),  // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (io_cpx_req_rq[7]),      // Templated
                  .stall_q_d1              (1'b0),                  // Templated
                  .scan_in(cpx_arbr7_scanin),
                  .scan_out(cpx_arbr7_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rb),
                 .ccx_aclk                (ccx_aclk_arb_rb),
                 .ccx_bclk                (ccx_bclk_arb_rb)
                 );


//buffer scan out
cpx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_scanout     (
	.din	(scan_out_prebuf),
	.dout	(scan_out)
);

// fixscan start:
assign bfd4_scanin               = scan_in                  ;
assign bfd5_scanin               = bfd4_scanout             ;
assign bfg4_scanin               = bfd5_scanout             ;
assign bfg1_scanin               = bfg4_scanout             ;
assign bfd1_scanin               = bfg1_scanout             ;
assign bfd0_scanin               = bfd1_scanout             ;
assign bfg0_scanin               = bfd0_scanout           ;
assign bfg8_req_scanin           = bfg0_scanout             ;
assign bfg8_scanin               = bfg8_req_scanout         ;
assign bfd_io_scanin             = bfg8_scanout             ;
assign cpx_arbl0_scanin          = bfd_io_scanout             ;
assign cpx_arbl4_scanin          = cpx_arbl0_scanout        ;
assign cpx_arbl5_scanin          = cpx_arbl4_scanout        ;
assign cpx_arbl1_scanin          = cpx_arbl5_scanout        ;
assign cpx_arbl3_scanin          = cpx_arbl1_scanout        ;
assign cpx_arbl7_scanin          = cpx_arbl3_scanout        ;
assign cpx_arbl2_scanin          = cpx_arbl7_scanout        ;
assign cpx_arbl6_scanin          = cpx_arbl2_scanout        ;
assign bfg2_scanin               = cpx_arbl6_scanout        ;
assign bfd2_scanin               = bfg2_scanout             ;
assign bfd3_scanin               = bfd2_scanout             ;
assign bfg3_scanin               = bfd3_scanout             ;
assign bfg7_scanin               = bfg3_scanout             ;
assign bfd7_scanin               = bfg7_scanout             ;
assign bfd6_scanin               = bfd7_scanout             ;
assign bfg6_scanin               = bfd6_scanout             ;
assign cpx_arbr6_scanin          = bfg6_scanout             ;
assign cpx_arbr2_scanin          = cpx_arbr6_scanout        ;
assign cpx_arbr7_scanin          = cpx_arbr2_scanout        ;
assign cpx_arbr3_scanin          = cpx_arbr7_scanout        ;
assign cpx_arbr1_scanin          = cpx_arbr3_scanout        ;
assign cpx_arbr5_scanin          = cpx_arbr1_scanout        ;
assign cpx_arbr4_scanin          = cpx_arbr5_scanout        ;
assign cpx_arbr0_scanin          = cpx_arbr4_scanout        ;
assign bfg5_scanin               = cpx_arbr0_scanout        ;
assign cpx_dpa_scanin            = bfg5_scanout             ;
assign scan_out_prebuf           = cpx_dpa_scanout          ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   invert macro
//
//


module cpx_inv_diode_macro__dinv_16x__stack_150c__width_150 (
  din, 
  dout);
  input [149:0] din;
  output [149:0] dout;


inv #(150)  d0_0 (
.in(din[149:0]),
.out(dout[149:0])
);


endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_8x__minbuff_1__stack_150c__width_150 (
  din, 
  dout);
  input [149:0] din;
  output [149:0] dout;


buff #(150)  d0_0 (
.in(din[149:0]),
.out(dout[149:0])
);


endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_16x__rep_1__stack_none__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_48x__rep_1__stack_10r__width_10 (
  din, 
  dout);
  input [9:0] din;
  output [9:0] dout;


buff #(10)  d0_0 (
.in(din[9:0]),
.out(dout[9:0])
);


endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module cpx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module cpx_inv_macro__dinv_40x__stack_150c__width_150 (
  din, 
  dout);
  input [149:0] din;
  output [149:0] dout;


inv #(150)  d0_0 (
.in(din[149:0]),
.out(dout[149:0])
);


endmodule


//
//   invert macro
//
//


module cpx_inv_macro__dinv_32x__stack_150c__width_150 (
  din, 
  dout);
  input [149:0] din;
  output [149:0] dout;


inv #(150)  d0_0 (
.in(din[149:0]),
.out(dout[149:0])
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module cpx(cpx_io_grant_cx, cpx_sctag0_grant_cx, cpx_sctag1_grant_cx, 
	cpx_sctag2_grant_cx, cpx_sctag3_grant_cx, cpx_sctag4_grant_cx, 
	cpx_sctag5_grant_cx, cpx_sctag6_grant_cx, cpx_sctag7_grant_cx, 
	cpx_spc0_data_cx2, cpx_spc1_data_cx2, cpx_spc2_data_cx2, 
	cpx_spc3_data_cx2, cpx_spc4_data_cx2, cpx_spc5_data_cx2, 
	cpx_spc6_data_cx2, cpx_spc7_data_cx2, io_cpx_data_ca, io_cpx_req_cq, 
	sctag0_cpx_atom_cq, sctag0_cpx_data_ca, sctag0_cpx_req_cq, 
	sctag1_cpx_atom_cq, sctag1_cpx_data_ca, sctag1_cpx_req_cq, 
	sctag2_cpx_atom_cq, sctag2_cpx_data_ca, sctag2_cpx_req_cq, 
	sctag3_cpx_atom_cq, sctag3_cpx_data_ca, sctag3_cpx_req_cq, 
	sctag4_cpx_atom_cq, sctag4_cpx_data_ca, sctag4_cpx_req_cq, 
	sctag5_cpx_atom_cq, sctag5_cpx_data_ca, sctag5_cpx_req_cq, 
	sctag6_cpx_atom_cq, sctag6_cpx_data_ca, sctag6_cpx_req_cq, 
	sctag7_cpx_atom_cq, sctag7_cpx_data_ca, sctag7_cpx_req_cq, tcu_scan_en, 
	l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[7:0]		cpx_io_grant_cx;
	output	[7:0]		cpx_sctag0_grant_cx;
	output	[7:0]		cpx_sctag1_grant_cx;
	output	[7:0]		cpx_sctag2_grant_cx;
	output	[7:0]		cpx_sctag3_grant_cx;
	output	[7:0]		cpx_sctag4_grant_cx;
	output	[7:0]		cpx_sctag5_grant_cx;
	output	[7:0]		cpx_sctag6_grant_cx;
	output	[7:0]		cpx_sctag7_grant_cx;
	output	[145:0]		cpx_spc0_data_cx2;
	output	[145:0]		cpx_spc1_data_cx2;
	output	[145:0]		cpx_spc2_data_cx2;
	output	[145:0]		cpx_spc3_data_cx2;
	output	[145:0]		cpx_spc4_data_cx2;
	output	[145:0]		cpx_spc5_data_cx2;
	output	[145:0]		cpx_spc6_data_cx2;
	output	[145:0]		cpx_spc7_data_cx2;
	input	[145:0]		io_cpx_data_ca;
	input	[7:0]		io_cpx_req_cq;
	input			sctag0_cpx_atom_cq;
	input	[145:0]		sctag0_cpx_data_ca;
	input	[7:0]		sctag0_cpx_req_cq;
	input			sctag1_cpx_atom_cq;
	input	[145:0]		sctag1_cpx_data_ca;
	input	[7:0]		sctag1_cpx_req_cq;
	input			sctag2_cpx_atom_cq;
	input	[145:0]		sctag2_cpx_data_ca;
	input	[7:0]		sctag2_cpx_req_cq;
	input			sctag3_cpx_atom_cq;
	input	[145:0]		sctag3_cpx_data_ca;
	input	[7:0]		sctag3_cpx_req_cq;
	input			sctag4_cpx_atom_cq;
	input	[145:0]		sctag4_cpx_data_ca;
	input	[7:0]		sctag4_cpx_req_cq;
	input			sctag5_cpx_atom_cq;
	input	[145:0]		sctag5_cpx_data_ca;
	input	[7:0]		sctag5_cpx_req_cq;
	input			sctag6_cpx_atom_cq;
	input	[145:0]		sctag6_cpx_data_ca;
	input	[7:0]		sctag6_cpx_req_cq;
	input			sctag7_cpx_atom_cq;
	input	[145:0]		sctag7_cpx_data_ca;
	input	[7:0]		sctag7_cpx_req_cq;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[7:0]		cpx_sctag0_grant_a;
	wire	[7:0]		cpx_sctag0_grant_a_0;
	wire	[7:0]		cpx_sctag1_grant_a;
	wire	[7:0]		cpx_sctag1_grant_a_0;
	wire	[7:0]		cpx_sctag2_grant_a;
	wire	[7:0]		cpx_sctag2_grant_a_0;
	wire	[7:0]		cpx_sctag3_grant_a;
	wire	[7:0]		cpx_sctag3_grant_a_0;
	wire	[7:0]		cpx_sctag4_grant_a;
	wire	[7:0]		cpx_sctag4_grant_a_0;
	wire	[7:0]		cpx_sctag5_grant_a;
	wire	[7:0]		cpx_sctag5_grant_a_0;
	wire	[7:0]		cpx_sctag6_grant_a;
	wire	[7:0]		cpx_sctag6_grant_a_0;
	wire	[7:0]		cpx_sctag7_grant_a;
	wire	[7:0]		cpx_sctag7_grant_a_0;
	wire	[7:0]		cpx_io_grant_a;
	wire	[7:0]		cpx_io_grant_a_0;
	wire			tcu_scan_en_bfg_0;
	wire			tcu_pce_ov_bfg_0;
	wire			ccx_aclk_bfg_0;
	wire			ccx_bclk_bfg_0;
	wire			bfg0_scanin;
	wire			bfg0_scanout;
	wire			tcu_scan_en_bfd_lt;
	wire			tcu_pce_ov_bfd_lt;
	wire			ccx_aclk_bfd_lt;
	wire			ccx_bclk_bfd_lt;
	wire			tcu_scan_en_bfg_1_unused;
	wire			tcu_pce_ov_bfg_1_unused;
	wire			ccx_aclk_bfg_1_unused;
	wire			ccx_bclk_bfg_1_unused;
	wire			bfg1_scanin;
	wire			bfg1_scanout;
	wire			tcu_scan_en_bfd_t;
	wire			tcu_pce_ov_bfd_t;
	wire			ccx_aclk_bfd_t;
	wire			ccx_bclk_bfd_t;
	wire			tcu_scan_en_bfg_2_unused;
	wire			tcu_pce_ov_bfg_2_unused;
	wire			ccx_aclk_bfg_2_unused;
	wire			ccx_bclk_bfg_2_unused;
	wire			bfg2_scanin;
	wire			bfg2_scanout;
	wire			tcu_scan_en_bfd_lb;
	wire			tcu_pce_ov_bfd_lb;
	wire			ccx_aclk_bfd_lb;
	wire			ccx_bclk_bfd_lb;
	wire			tcu_scan_en_bfg_3_unused;
	wire			tcu_pce_ov_bfg_3_unused;
	wire			ccx_aclk_bfg_3_unused;
	wire			ccx_bclk_bfg_3_unused;
	wire			bfg3_scanin;
	wire			bfg3_scanout;
	wire			tcu_scan_en_bfd_b;
	wire			tcu_pce_ov_bfd_b;
	wire			ccx_aclk_bfd_b;
	wire			ccx_bclk_bfd_b;
	wire			tcu_scan_en_bfg_4_unused;
	wire			tcu_pce_ov_bfg_4_unused;
	wire			ccx_aclk_bfg_4_unused;
	wire			ccx_bclk_bfg_4_unused;
	wire			bfg4_scanin;
	wire			bfg4_scanout;
	wire			tcu_scan_en_bfd_rt;
	wire			tcu_pce_ov_bfd_rt;
	wire			ccx_aclk_bfd_rt;
	wire			ccx_bclk_bfd_rt;
	wire			tcu_scan_en_bfg_5_unused;
	wire			tcu_pce_ov_bfg_5_unused;
	wire			ccx_aclk_bfg_5_unused;
	wire			ccx_bclk_bfg_5_unused;
	wire			bfg5_scanin;
	wire			bfg5_scanout;
	wire			tcu_scan_en_bfg_6_unused;
	wire			tcu_pce_ov_bfg_6_unused;
	wire			ccx_aclk_bfg_6_unused;
	wire			ccx_bclk_bfg_6_unused;
	wire			bfg6_scanin;
	wire			bfg6_scanout;
	wire			tcu_scan_en_bfd_rb;
	wire			tcu_pce_ov_bfd_rb;
	wire			ccx_aclk_bfd_rb;
	wire			ccx_bclk_bfd_rb;
	wire			tcu_scan_en_bfg_7_unused;
	wire			tcu_pce_ov_bfg_7_unused;
	wire			ccx_aclk_bfg_7_unused;
	wire			ccx_bclk_bfg_7_unused;
	wire			bfg7_scanin;
	wire			bfg7_scanout;
	wire			tcu_scan_en_bfg_8_unused;
	wire			tcu_pce_ov_bfg_8_unused;
	wire			ccx_aclk_bfg_8_unused;
	wire			ccx_bclk_bfg_8_unused;
	wire			bfg8_scanin;
	wire			bfg8_scanout;
	wire	[145:0]		io_cpx_data_ca_buf;
	wire	[145:0]		io_cpx_data_ca_d1_;
	wire			tcu_scan_en_bfd_io_unused;
	wire			tcu_pce_ov_bfd_io_unused;
	wire			ccx_aclk_bfd_io_unused;
	wire			ccx_bclk_bfd_io_unused;
	wire			bfd_io_scanin;
	wire			bfd_io_scanout;
	wire	[7:0]		sctag0_cpx_req_cq_0_l;
	wire			sctag0_cpx_atom_cq_0_l;
	wire	[7:0]		sctag0_cpx_req_cq_0_r;
	wire			sctag0_cpx_atom_cq_0_r;
	wire	[7:0]		sctag1_cpx_req_cq_0_l;
	wire			sctag1_cpx_atom_cq_0_l;
	wire	[7:0]		sctag1_cpx_req_cq_0_r;
	wire			sctag1_cpx_atom_cq_0_r;
	wire	[7:0]		sctag2_cpx_req_cq_0_l;
	wire			sctag2_cpx_atom_cq_0_l;
	wire	[7:0]		sctag2_cpx_req_cq_0_r;
	wire			sctag2_cpx_atom_cq_0_r;
	wire	[7:0]		sctag3_cpx_req_cq_0_l;
	wire			sctag3_cpx_atom_cq_0_l;
	wire	[7:0]		sctag3_cpx_req_cq_0_r;
	wire			sctag3_cpx_atom_cq_0_r;
	wire	[7:0]		sctag4_cpx_req_cq_0_l;
	wire			sctag4_cpx_atom_cq_0_l;
	wire	[7:0]		sctag4_cpx_req_cq_0_r;
	wire			sctag4_cpx_atom_cq_0_r;
	wire	[7:0]		sctag5_cpx_req_cq_0_l;
	wire			sctag5_cpx_atom_cq_0_l;
	wire	[7:0]		sctag5_cpx_req_cq_0_r;
	wire			sctag5_cpx_atom_cq_0_r;
	wire	[7:0]		sctag6_cpx_req_cq_0_l;
	wire			sctag6_cpx_atom_cq_0_l;
	wire	[7:0]		sctag6_cpx_req_cq_0_r;
	wire			sctag6_cpx_atom_cq_0_r;
	wire	[7:0]		sctag7_cpx_req_cq_0_l;
	wire			sctag7_cpx_atom_cq_0_l;
	wire	[7:0]		sctag7_cpx_req_cq_0_r;
	wire			sctag7_cpx_atom_cq_0_r;
	wire	[7:0]		io_cpx_req_cq_buf;
	wire	[7:0]		io_cpx_req_cq_d1;
	wire			tcu_scan_en_bfg_req_8_unused;
	wire			tcu_pce_ov_bfg_req_8_unused;
	wire			ccx_aclk_bfg_req_8_unused;
	wire			ccx_bclk_bfg_req_8_unused;
	wire			bfg8_req_scanin;
	wire			bfg8_req_scanout;
	wire	[149:0]		sctag0_cpx_data_a_;
	wire	[149:0]		sctag0_cpx_data_a;
	wire	[149:0]		sctag1_cpx_data_a_;
	wire	[149:0]		sctag1_cpx_data_a;
	wire	[149:0]		sctag2_cpx_data_a_;
	wire	[149:0]		sctag2_cpx_data_a;
	wire	[149:0]		sctag3_cpx_data_a_;
	wire	[149:0]		sctag3_cpx_data_a;
	wire	[149:0]		sctag4_cpx_data_a_;
	wire	[149:0]		sctag4_cpx_data_a;
	wire	[149:0]		sctag5_cpx_data_a_;
	wire	[149:0]		sctag5_cpx_data_a;
	wire	[149:0]		sctag6_cpx_data_a_;
	wire	[149:0]		sctag6_cpx_data_a;
	wire	[149:0]		sctag7_cpx_data_a_;
	wire	[149:0]		sctag7_cpx_data_a;
	wire	[149:0]		io_cpx_data_a_;
	wire	[149:0]		io_cpx_data_a;
	wire			ccx_aclk_dpa_t;
	wire			ccx_bclk_dpa_t;
	wire			tcu_pce_ov_dpa_t;
	wire			tcu_scan_en_dpa_t;
	wire			ccx_aclk_dpa_b;
	wire			ccx_bclk_dpa_b;
	wire			tcu_pce_ov_dpa_b;
	wire			tcu_scan_en_dpa_b;
	wire	[3:0]		cpx_spc0_data_x_unused;
	wire	[149:0]		cpx_spc0_data_x_;
	wire	[3:0]		cpx_spc1_data_x_unused;
	wire	[149:0]		cpx_spc1_data_x_;
	wire	[3:0]		cpx_spc2_data_x_unused;
	wire	[149:0]		cpx_spc2_data_x_;
	wire	[3:0]		cpx_spc3_data_x_unused;
	wire	[149:0]		cpx_spc3_data_x_;
	wire	[3:0]		cpx_spc4_data_x_unused;
	wire	[149:0]		cpx_spc4_data_x_;
	wire	[3:0]		cpx_spc5_data_x_unused;
	wire	[149:0]		cpx_spc5_data_x_;
	wire	[3:0]		cpx_spc6_data_x_unused;
	wire	[149:0]		cpx_spc6_data_x_;
	wire	[3:0]		cpx_spc7_data_x_unused;
	wire	[149:0]		cpx_spc7_data_x_;
	wire	[8:0]		arb0_grant_l_a;
	wire	[8:0]		arb0_q0_holdbar_l_a;
	wire	[8:0]		arb0_qsel0_l_a;
	wire	[8:0]		arb0_qsel1_l_a;
	wire	[8:0]		arb0_shift_l_a;
	wire	[8:0]		arb1_grant_l_a;
	wire	[8:0]		arb1_q0_holdbar_l_a;
	wire	[8:0]		arb1_qsel0_l_a;
	wire	[8:0]		arb1_qsel1_l_a;
	wire	[8:0]		arb1_shift_l_a;
	wire	[8:0]		arb2_grant_l_a;
	wire	[8:0]		arb2_q0_holdbar_l_a;
	wire	[8:0]		arb2_qsel0_l_a;
	wire	[8:0]		arb2_qsel1_l_a;
	wire	[8:0]		arb2_shift_l_a;
	wire	[8:0]		arb3_grant_l_a;
	wire	[8:0]		arb3_q0_holdbar_l_a;
	wire	[8:0]		arb3_qsel0_l_a;
	wire	[8:0]		arb3_qsel1_l_a;
	wire	[8:0]		arb3_shift_l_a;
	wire	[8:0]		arb4_grant_l_a;
	wire	[8:0]		arb4_q0_holdbar_l_a;
	wire	[8:0]		arb4_qsel0_l_a;
	wire	[8:0]		arb4_qsel1_l_a;
	wire	[8:0]		arb4_shift_l_a;
	wire	[8:0]		arb5_grant_l_a;
	wire	[8:0]		arb5_q0_holdbar_l_a;
	wire	[8:0]		arb5_qsel0_l_a;
	wire	[8:0]		arb5_qsel1_l_a;
	wire	[8:0]		arb5_shift_l_a;
	wire	[8:0]		arb6_grant_l_a;
	wire	[8:0]		arb6_q0_holdbar_l_a;
	wire	[8:0]		arb6_qsel0_l_a;
	wire	[8:0]		arb6_qsel1_l_a;
	wire	[8:0]		arb6_shift_l_a;
	wire	[8:0]		arb7_grant_l_a;
	wire	[8:0]		arb7_q0_holdbar_l_a;
	wire	[8:0]		arb7_qsel0_l_a;
	wire	[8:0]		arb7_qsel1_l_a;
	wire	[8:0]		arb7_shift_l_a;
	wire	[8:0]		arb0_grant_r_a;
	wire	[8:0]		arb0_q0_holdbar_r_a;
	wire	[8:0]		arb0_qsel0_r_a;
	wire	[8:0]		arb0_qsel1_r_a;
	wire	[8:0]		arb0_shift_r_a;
	wire	[8:0]		arb1_grant_r_a;
	wire	[8:0]		arb1_q0_holdbar_r_a;
	wire	[8:0]		arb1_qsel0_r_a;
	wire	[8:0]		arb1_qsel1_r_a;
	wire	[8:0]		arb1_shift_r_a;
	wire	[8:0]		arb2_grant_r_a;
	wire	[8:0]		arb2_q0_holdbar_r_a;
	wire	[8:0]		arb2_qsel0_r_a;
	wire	[8:0]		arb2_qsel1_r_a;
	wire	[8:0]		arb2_shift_r_a;
	wire	[8:0]		arb3_grant_r_a;
	wire	[8:0]		arb3_q0_holdbar_r_a;
	wire	[8:0]		arb3_qsel0_r_a;
	wire	[8:0]		arb3_qsel1_r_a;
	wire	[8:0]		arb3_shift_r_a;
	wire	[8:0]		arb4_grant_r_a;
	wire	[8:0]		arb4_q0_holdbar_r_a;
	wire	[8:0]		arb4_qsel0_r_a;
	wire	[8:0]		arb4_qsel1_r_a;
	wire	[8:0]		arb4_shift_r_a;
	wire	[8:0]		arb5_grant_r_a;
	wire	[8:0]		arb5_q0_holdbar_r_a;
	wire	[8:0]		arb5_qsel0_r_a;
	wire	[8:0]		arb5_qsel1_r_a;
	wire	[8:0]		arb5_shift_r_a;
	wire	[8:0]		arb6_grant_r_a;
	wire	[8:0]		arb6_q0_holdbar_r_a;
	wire	[8:0]		arb6_qsel0_r_a;
	wire	[8:0]		arb6_qsel1_r_a;
	wire	[8:0]		arb6_shift_r_a;
	wire	[8:0]		arb7_grant_r_a;
	wire	[8:0]		arb7_q0_holdbar_r_a;
	wire	[8:0]		arb7_qsel0_r_a;
	wire	[8:0]		arb7_qsel1_r_a;
	wire	[8:0]		arb7_shift_r_a;
	wire			cpx_dpa_scanin;
	wire			cpx_dpa_scanout;
	wire	[145:0]		cpx_spc0_data_cx2_prebuf;
	wire			bfd0_scanin;
	wire			bfd0_scanout;
	wire			tcu_scan_en_bfd_1;
	wire			tcu_pce_ov_bfd_1;
	wire			ccx_aclk_bfd_1;
	wire			ccx_bclk_bfd_1;
	wire	[145:0]		cpx_spc1_data_cx2_prebuf;
	wire			bfd1_scanin;
	wire			bfd1_scanout;
	wire	[145:0]		cpx_spc2_data_cx2_prebuf;
	wire			bfd2_scanin;
	wire			bfd2_scanout;
	wire			tcu_scan_en_bfd_3;
	wire			tcu_pce_ov_bfd_3;
	wire			ccx_aclk_bfd_3;
	wire			ccx_bclk_bfd_3;
	wire	[145:0]		cpx_spc3_data_cx2_prebuf;
	wire			bfd3_scanin;
	wire			bfd3_scanout;
	wire	[145:0]		cpx_spc4_data_cx2_prebuf;
	wire			bfd4_scanin;
	wire			bfd4_scanout;
	wire			tcu_scan_en_bfd_5;
	wire			tcu_pce_ov_bfd_5;
	wire			ccx_aclk_bfd_5;
	wire			ccx_bclk_bfd_5;
	wire	[145:0]		cpx_spc5_data_cx2_prebuf;
	wire			bfd5_scanin;
	wire			bfd5_scanout;
	wire	[145:0]		cpx_spc6_data_cx2_prebuf;
	wire			bfd6_scanin;
	wire			bfd6_scanout;
	wire			tcu_scan_en_bfd_7;
	wire			tcu_pce_ov_bfd_7;
	wire			ccx_aclk_bfd_7;
	wire			ccx_bclk_bfd_7;
	wire	[145:0]		cpx_spc7_data_cx2_prebuf;
	wire			bfd7_scanin;
	wire			bfd7_scanout;
	wire	[7:0]		sctag0_cpx_req_lq;
	wire			sctag0_cpx_atom_lq_t;
	wire			sctag0_cpx_atom_lq_b;
	wire	[7:0]		sctag1_cpx_req_lq;
	wire			sctag1_cpx_atom_lq_t;
	wire			sctag1_cpx_atom_lq_b;
	wire	[7:0]		sctag2_cpx_req_lq;
	wire			sctag2_cpx_atom_lq_t;
	wire			sctag2_cpx_atom_lq_b;
	wire	[7:0]		sctag3_cpx_req_lq;
	wire			sctag3_cpx_atom_lq_t;
	wire			sctag3_cpx_atom_lq_b;
	wire	[7:0]		sctag4_cpx_req_lq;
	wire			sctag4_cpx_atom_lq_t;
	wire			sctag4_cpx_atom_lq_b;
	wire	[7:0]		sctag5_cpx_req_lq;
	wire			sctag5_cpx_atom_lq_t;
	wire			sctag5_cpx_atom_lq_b;
	wire	[7:0]		sctag6_cpx_req_lq;
	wire			sctag6_cpx_atom_lq_t;
	wire			sctag6_cpx_atom_lq_b;
	wire	[7:0]		sctag7_cpx_req_lq;
	wire			sctag7_cpx_atom_lq_t;
	wire			sctag7_cpx_atom_lq_b;
	wire	[7:0]		io_cpx_req_lq;
	wire			ccx_aclk_arb_lt;
	wire			ccx_bclk_arb_lt;
	wire			tcu_pce_ov_arb_lt;
	wire			tcu_scan_en_arb_lt;
	wire			ccx_aclk_arb_lb;
	wire			ccx_bclk_arb_lb;
	wire			tcu_pce_ov_arb_lb;
	wire			tcu_scan_en_arb_lb;
	wire			ccx_aclk_arb_rt;
	wire			ccx_bclk_arb_rt;
	wire			tcu_pce_ov_arb_rt;
	wire			tcu_scan_en_arb_rt;
	wire			ccx_aclk_arb_rb;
	wire			ccx_bclk_arb_rb;
	wire			tcu_pce_ov_arb_rb;
	wire			tcu_scan_en_arb_rb;
	wire	[7:0]		cpx_sctag4_grant_a_unused;
	wire	[7:0]		cpx_sctag5_grant_a_unused;
	wire	[7:0]		cpx_sctag6_grant_a_unused;
	wire	[7:0]		cpx_sctag7_grant_a_unused;
	wire	[7:0]		ccx_dest_atom_a_l_unused;
	wire	[7:0]		ccx_dest_data_rdy_a_l_unused;
	wire			cpx_arbl0_scanin;
	wire			cpx_arbl0_scanout;
	wire			cpx_arbl1_scanin;
	wire			cpx_arbl1_scanout;
	wire			cpx_arbl2_scanin;
	wire			cpx_arbl2_scanout;
	wire			cpx_arbl3_scanin;
	wire			cpx_arbl3_scanout;
	wire			cpx_arbl4_scanin;
	wire			cpx_arbl4_scanout;
	wire			cpx_arbl5_scanin;
	wire			cpx_arbl5_scanout;
	wire			cpx_arbl6_scanin;
	wire			cpx_arbl6_scanout;
	wire			cpx_arbl7_scanin;
	wire			cpx_arbl7_scanout;
	wire	[7:0]		sctag0_cpx_req_rq;
	wire			sctag0_cpx_atom_rq_t;
	wire			sctag0_cpx_atom_rq_b;
	wire	[7:0]		sctag1_cpx_req_rq;
	wire			sctag1_cpx_atom_rq_t;
	wire			sctag1_cpx_atom_rq_b;
	wire	[7:0]		sctag2_cpx_req_rq;
	wire			sctag2_cpx_atom_rq_t;
	wire			sctag2_cpx_atom_rq_b;
	wire	[7:0]		sctag3_cpx_req_rq;
	wire			sctag3_cpx_atom_rq_t;
	wire			sctag3_cpx_atom_rq_b;
	wire	[7:0]		sctag4_cpx_req_rq;
	wire			sctag4_cpx_atom_rq_t;
	wire			sctag4_cpx_atom_rq_b;
	wire	[7:0]		sctag5_cpx_req_rq;
	wire			sctag5_cpx_atom_rq_t;
	wire			sctag5_cpx_atom_rq_b;
	wire	[7:0]		sctag6_cpx_req_rq;
	wire			sctag6_cpx_atom_rq_t;
	wire			sctag6_cpx_atom_rq_b;
	wire	[7:0]		sctag7_cpx_req_rq;
	wire			sctag7_cpx_atom_rq_t;
	wire			sctag7_cpx_atom_rq_b;
	wire	[7:0]		io_cpx_req_rq;
	wire	[7:0]		cpx_sctag0_grant_a_unused;
	wire	[7:0]		cpx_sctag1_grant_a_unused;
	wire	[7:0]		cpx_sctag2_grant_a_unused;
	wire	[7:0]		cpx_sctag3_grant_a_unused;
	wire	[7:0]		cpx_sctag8_grant_a_unused;
	wire	[7:0]		ccx_dest_atom_a_r_unused;
	wire	[7:0]		ccx_dest_data_rdy_a_r_unused;
	wire			cpx_arbr0_scanin;
	wire			cpx_arbr0_scanout;
	wire			cpx_arbr1_scanin;
	wire			cpx_arbr1_scanout;
	wire			cpx_arbr2_scanin;
	wire			cpx_arbr2_scanout;
	wire			cpx_arbr3_scanin;
	wire			cpx_arbr3_scanout;
	wire			cpx_arbr4_scanin;
	wire			cpx_arbr4_scanout;
	wire			cpx_arbr5_scanin;
	wire			cpx_arbr5_scanout;
	wire			cpx_arbr6_scanin;
	wire			cpx_arbr6_scanout;
	wire			cpx_arbr7_scanin;
	wire			cpx_arbr7_scanout;
	wire			scan_out_prebuf;

	assign cpx_spc0_data_x_unused[3:0] = cpx_spc0_data_x_[149:146];
	assign cpx_spc1_data_x_unused[3:0] = cpx_spc1_data_x_[149:146];
	assign cpx_spc2_data_x_unused[3:0] = cpx_spc2_data_x_[149:146];
	assign cpx_spc3_data_x_unused[3:0] = cpx_spc3_data_x_[149:146];
	assign cpx_spc4_data_x_unused[3:0] = cpx_spc4_data_x_[149:146];
	assign cpx_spc5_data_x_unused[3:0] = cpx_spc5_data_x_[149:146];
	assign cpx_spc6_data_x_unused[3:0] = cpx_spc6_data_x_[149:146];
	assign cpx_spc7_data_x_unused[3:0] = cpx_spc7_data_x_[149:146];
	assign bfd4_scanin = scan_in;
	assign bfd5_scanin = bfd4_scanout;
	assign bfg4_scanin = bfd5_scanout;
	assign bfg1_scanin = bfg4_scanout;
	assign bfd1_scanin = bfg1_scanout;
	assign bfd0_scanin = bfd1_scanout;
	assign bfg0_scanin = bfd0_scanout;
	assign bfg8_req_scanin = bfg0_scanout;
	assign bfg8_scanin = bfg8_req_scanout;
	assign bfd_io_scanin = bfg8_scanout;
	assign cpx_arbl0_scanin = bfd_io_scanout;
	assign cpx_arbl4_scanin = cpx_arbl0_scanout;
	assign cpx_arbl5_scanin = cpx_arbl4_scanout;
	assign cpx_arbl1_scanin = cpx_arbl5_scanout;
	assign cpx_arbl3_scanin = cpx_arbl1_scanout;
	assign cpx_arbl7_scanin = cpx_arbl3_scanout;
	assign cpx_arbl2_scanin = cpx_arbl7_scanout;
	assign cpx_arbl6_scanin = cpx_arbl2_scanout;
	assign bfg2_scanin = cpx_arbl6_scanout;
	assign bfd2_scanin = bfg2_scanout;
	assign bfd3_scanin = bfd2_scanout;
	assign bfg3_scanin = bfd3_scanout;
	assign bfg7_scanin = bfg3_scanout;
	assign bfd7_scanin = bfg7_scanout;
	assign bfd6_scanin = bfd7_scanout;
	assign bfg6_scanin = bfd6_scanout;
	assign cpx_arbr6_scanin = bfg6_scanout;
	assign cpx_arbr2_scanin = cpx_arbr6_scanout;
	assign cpx_arbr7_scanin = cpx_arbr2_scanout;
	assign cpx_arbr3_scanin = cpx_arbr7_scanout;
	assign cpx_arbr1_scanin = cpx_arbr3_scanout;
	assign cpx_arbr5_scanin = cpx_arbr1_scanout;
	assign cpx_arbr4_scanin = cpx_arbr5_scanout;
	assign cpx_arbr0_scanin = cpx_arbr4_scanout;
	assign bfg5_scanin = cpx_arbr0_scanout;
	assign cpx_dpa_scanin = bfg5_scanout;
	assign scan_out_prebuf = cpx_dpa_scanout;

	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct0(
		.din				(cpx_sctag0_grant_a[7:0]), 
		.dout				(cpx_sctag0_grant_a_0[7:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct1(
		.din				(cpx_sctag1_grant_a[7:0]), 
		.dout				(cpx_sctag1_grant_a_0[7:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct2(
		.din				(cpx_sctag2_grant_a[7:0]), 
		.dout				(cpx_sctag2_grant_a_0[7:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct3(
		.din				(cpx_sctag3_grant_a[7:0]), 
		.dout				(cpx_sctag3_grant_a_0[7:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct4(
		.din				(cpx_sctag4_grant_a[7:0]), 
		.dout				(cpx_sctag4_grant_a_0[7:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct5(
		.din				(cpx_sctag5_grant_a[7:0]), 
		.dout				(cpx_sctag5_grant_a_0[7:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct6(
		.din				(cpx_sctag6_grant_a[7:0]), 
		.dout				(cpx_sctag6_grant_a_0[7:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_sct7(
		.din				(cpx_sctag7_grant_a[7:0]), 
		.dout				(cpx_sctag7_grant_a_0[7:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_bufg_io(
		.din				(cpx_io_grant_a[7:0]), 
		.dout				(cpx_io_grant_a_0[7:0]));
	cpx_bfg_dp bfg0(
		.cpx_sctag_grant_cx		(cpx_sctag0_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_0), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_0), 
		.ccx_aclk_out			(ccx_aclk_bfg_0), 
		.ccx_bclk_out			(ccx_bclk_bfg_0), 
		.cpx_sctag_grant_ca		(cpx_sctag0_grant_a_0[7:0]), 
		.scan_in			(bfg0_scanin), 
		.scan_out			(bfg0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_lt), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_lt), 
		.ccx_aclk			(ccx_aclk_bfd_lt), 
		.ccx_bclk			(ccx_bclk_bfd_lt));
	cpx_bfg_dp bfg1(
		.cpx_sctag_grant_cx		(cpx_sctag1_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_1_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_1_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_1_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_1_unused), 
		.cpx_sctag_grant_ca		(cpx_sctag1_grant_a_0[7:0]), 
		.scan_in			(bfg1_scanin), 
		.scan_out			(bfg1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_t), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_t), 
		.ccx_aclk			(ccx_aclk_bfd_t), 
		.ccx_bclk			(ccx_bclk_bfd_t));
	cpx_bfg_dp bfg2(
		.cpx_sctag_grant_cx		(cpx_sctag2_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_2_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_2_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_2_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_2_unused), 
		.cpx_sctag_grant_ca		(cpx_sctag2_grant_a_0[7:0]), 
		.scan_in			(bfg2_scanin), 
		.scan_out			(bfg2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_lb), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_lb), 
		.ccx_aclk			(ccx_aclk_bfd_lb), 
		.ccx_bclk			(ccx_bclk_bfd_lb));
	cpx_bfg_dp bfg3(
		.cpx_sctag_grant_cx		(cpx_sctag3_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_3_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_3_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_3_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_3_unused), 
		.cpx_sctag_grant_ca		(cpx_sctag3_grant_a_0[7:0]), 
		.scan_in			(bfg3_scanin), 
		.scan_out			(bfg3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_b), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_b), 
		.ccx_aclk			(ccx_aclk_bfd_b), 
		.ccx_bclk			(ccx_bclk_bfd_b));
	cpx_bfg_dp bfg4(
		.cpx_sctag_grant_cx		(cpx_sctag4_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_4_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_4_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_4_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_4_unused), 
		.cpx_sctag_grant_ca		(cpx_sctag4_grant_a_0[7:0]), 
		.scan_in			(bfg4_scanin), 
		.scan_out			(bfg4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_rt), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_rt), 
		.ccx_aclk			(ccx_aclk_bfd_rt), 
		.ccx_bclk			(ccx_bclk_bfd_rt));
	cpx_bfg_dp bfg5(
		.cpx_sctag_grant_cx		(cpx_sctag5_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_5_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_5_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_5_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_5_unused), 
		.cpx_sctag_grant_ca		(cpx_sctag5_grant_a_0[7:0]), 
		.scan_in			(bfg5_scanin), 
		.scan_out			(bfg5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_t), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_t), 
		.ccx_aclk			(ccx_aclk_bfd_t), 
		.ccx_bclk			(ccx_bclk_bfd_t));
	cpx_bfg_dp bfg6(
		.cpx_sctag_grant_cx		(cpx_sctag6_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_6_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_6_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_6_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_6_unused), 
		.cpx_sctag_grant_ca		(cpx_sctag6_grant_a_0[7:0]), 
		.scan_in			(bfg6_scanin), 
		.scan_out			(bfg6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_rb), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_rb), 
		.ccx_aclk			(ccx_aclk_bfd_rb), 
		.ccx_bclk			(ccx_bclk_bfd_rb));
	cpx_bfg_dp bfg7(
		.cpx_sctag_grant_cx		(cpx_sctag7_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_7_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_7_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_7_unused), 
		.cpx_sctag_grant_ca		(cpx_sctag7_grant_a_0[7:0]), 
		.scan_in			(bfg7_scanin), 
		.scan_out			(bfg7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_b), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_b), 
		.ccx_aclk			(ccx_aclk_bfd_b), 
		.ccx_bclk			(ccx_bclk_bfd_b));
	cpx_bfg_dp bfg8(
		.cpx_sctag_grant_cx		(cpx_io_grant_cx[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_8_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_8_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_8_unused), 
		.cpx_sctag_grant_ca		(cpx_io_grant_a_0[7:0]), 
		.scan_in			(bfg8_scanin), 
		.scan_out			(bfg8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfg_0), 
		.tcu_pce_ov			(tcu_pce_ov_bfg_0), 
		.ccx_aclk			(ccx_aclk_bfg_0), 
		.ccx_bclk			(ccx_bclk_bfg_0));
	cpx_ob1_dp buf_io(
		.cpx_spc_data_cx2_prebuf	(io_cpx_data_ca[145:0]), 
		.cpx_spc_data_cx2		(io_cpx_data_ca_buf[145:0]));
	cpx_bfd_dp bfd_io(
		.cpx_spc_data_cx2		(io_cpx_data_ca_d1_[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_io_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_io_unused), 
		.ccx_aclk_out			(ccx_aclk_bfd_io_unused), 
		.ccx_bclk_out			(ccx_bclk_bfd_io_unused), 
		.cpx_spc_data_x_		(io_cpx_data_ca_buf[145:0]), 
		.scan_in			(bfd_io_scanin), 
		.scan_out			(bfd_io_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_lt), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_lt), 
		.ccx_aclk			(ccx_aclk_bfd_lt), 
		.ccx_bclk			(ccx_bclk_bfd_lt));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct0_l(
		.din				({sctag0_cpx_req_cq[7:0],
		sctag0_cpx_atom_cq}), 
		.dout				({sctag0_cpx_req_cq_0_l[7:0],
		sctag0_cpx_atom_cq_0_l}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct0_r(
		.din				({sctag0_cpx_req_cq[7:0],
		sctag0_cpx_atom_cq}), 
		.dout				({sctag0_cpx_req_cq_0_r[7:0],
		sctag0_cpx_atom_cq_0_r}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct1_l(
		.din				({sctag1_cpx_req_cq[7:0],
		sctag1_cpx_atom_cq}), 
		.dout				({sctag1_cpx_req_cq_0_l[7:0],
		sctag1_cpx_atom_cq_0_l}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct1_r(
		.din				({sctag1_cpx_req_cq[7:0],
		sctag1_cpx_atom_cq}), 
		.dout				({sctag1_cpx_req_cq_0_r[7:0],
		sctag1_cpx_atom_cq_0_r}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct2_l(
		.din				({sctag2_cpx_req_cq[7:0],
		sctag2_cpx_atom_cq}), 
		.dout				({sctag2_cpx_req_cq_0_l[7:0],
		sctag2_cpx_atom_cq_0_l}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct2_r(
		.din				({sctag2_cpx_req_cq[7:0],
		sctag2_cpx_atom_cq}), 
		.dout				({sctag2_cpx_req_cq_0_r[7:0],
		sctag2_cpx_atom_cq_0_r}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct3_l(
		.din				({sctag3_cpx_req_cq[7:0],
		sctag3_cpx_atom_cq}), 
		.dout				({sctag3_cpx_req_cq_0_l[7:0],
		sctag3_cpx_atom_cq_0_l}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct3_r(
		.din				({sctag3_cpx_req_cq[7:0],
		sctag3_cpx_atom_cq}), 
		.dout				({sctag3_cpx_req_cq_0_r[7:0],
		sctag3_cpx_atom_cq_0_r}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct4_l(
		.din				({sctag4_cpx_req_cq[7:0],
		sctag4_cpx_atom_cq}), 
		.dout				({sctag4_cpx_req_cq_0_l[7:0],
		sctag4_cpx_atom_cq_0_l}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct4_r(
		.din				({sctag4_cpx_req_cq[7:0],
		sctag4_cpx_atom_cq}), 
		.dout				({sctag4_cpx_req_cq_0_r[7:0],
		sctag4_cpx_atom_cq_0_r}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct5_l(
		.din				({sctag5_cpx_req_cq[7:0],
		sctag5_cpx_atom_cq}), 
		.dout				({sctag5_cpx_req_cq_0_l[7:0],
		sctag5_cpx_atom_cq_0_l}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct5_r(
		.din				({sctag5_cpx_req_cq[7:0],
		sctag5_cpx_atom_cq}), 
		.dout				({sctag5_cpx_req_cq_0_r[7:0],
		sctag5_cpx_atom_cq_0_r}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct6_l(
		.din				({sctag6_cpx_req_cq[7:0],
		sctag6_cpx_atom_cq}), 
		.dout				({sctag6_cpx_req_cq_0_l[7:0],
		sctag6_cpx_atom_cq_0_l}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct6_r(
		.din				({sctag6_cpx_req_cq[7:0],
		sctag6_cpx_atom_cq}), 
		.dout				({sctag6_cpx_req_cq_0_r[7:0],
		sctag6_cpx_atom_cq_0_r}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct7_l(
		.din				({sctag7_cpx_req_cq[7:0],
		sctag7_cpx_atom_cq}), 
		.dout				({sctag7_cpx_req_cq_0_l[7:0],
		sctag7_cpx_atom_cq_0_l}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_9 i_bufq_sct7_r(
		.din				({sctag7_cpx_req_cq[7:0],
		sctag7_cpx_atom_cq}), 
		.dout				({sctag7_cpx_req_cq_0_r[7:0],
		sctag7_cpx_atom_cq_0_r}));
	buff_macro__dbuff_16x__rep_1__stack_none__width_8 buf8_req(
		.din				(io_cpx_req_cq[7:0]), 
		.dout				(io_cpx_req_cq_buf[7:0]));
	cpx_bfg_dp bfg8_req(
		.cpx_sctag_grant_cx		(io_cpx_req_cq_d1[7:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_req_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_req_8_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_req_8_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_req_8_unused), 
		.cpx_sctag_grant_ca		(io_cpx_req_cq_buf[7:0]), 
		.scan_in			(bfg8_req_scanin), 
		.scan_out			(bfg8_req_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfg_0), 
		.tcu_pce_ov			(tcu_pce_ov_bfg_0), 
		.ccx_aclk			(ccx_aclk_bfg_0), 
		.ccx_bclk			(ccx_bclk_bfg_0));
	inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct0_0(
		.din				({4'b0,
		sctag0_cpx_data_ca[145:0]}), 
		.dout				(sctag0_cpx_data_a_[149:0]));
	inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct0_1(
		.din				({sctag0_cpx_data_a_[149:0]}), 
		.dout				(sctag0_cpx_data_a[149:0]));
	inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct1_0(
		.din				({4'b0,
		sctag1_cpx_data_ca[145:0]}), 
		.dout				(sctag1_cpx_data_a_[149:0]));
	inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct1_1(
		.din				({sctag1_cpx_data_a_[149:0]}), 
		.dout				(sctag1_cpx_data_a[149:0]));
	inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct2_0(
		.din				({4'b0,
		sctag2_cpx_data_ca[145:0]}), 
		.dout				(sctag2_cpx_data_a_[149:0]));
	inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct2_1(
		.din				({sctag2_cpx_data_a_[149:0]}), 
		.dout				(sctag2_cpx_data_a[149:0]));
	inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct3_0(
		.din				({4'b0,
		sctag3_cpx_data_ca[145:0]}), 
		.dout				(sctag3_cpx_data_a_[149:0]));
	inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct3_1(
		.din				({sctag3_cpx_data_a_[149:0]}), 
		.dout				(sctag3_cpx_data_a[149:0]));
	inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct4_0(
		.din				({4'b0,
		sctag4_cpx_data_ca[145:0]}), 
		.dout				(sctag4_cpx_data_a_[149:0]));
	inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct4_1(
		.din				({sctag4_cpx_data_a_[149:0]}), 
		.dout				(sctag4_cpx_data_a[149:0]));
	inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct5_0(
		.din				({4'b0,
		sctag5_cpx_data_ca[145:0]}), 
		.dout				(sctag5_cpx_data_a_[149:0]));
	inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct5_1(
		.din				({sctag5_cpx_data_a_[149:0]}), 
		.dout				(sctag5_cpx_data_a[149:0]));
	inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct6_0(
		.din				({4'b0,
		sctag6_cpx_data_ca[145:0]}), 
		.dout				(sctag6_cpx_data_a_[149:0]));
	inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct6_1(
		.din				({sctag6_cpx_data_a_[149:0]}), 
		.dout				(sctag6_cpx_data_a[149:0]));
	inv_diode_macro__dinv_16x__stack_150c__width_150 i_inv_sct7_0(
		.din				({4'b0,
		sctag7_cpx_data_ca[145:0]}), 
		.dout				(sctag7_cpx_data_a_[149:0]));
	inv_macro__dinv_40x__stack_150c__width_150 i_inv_sct7_1(
		.din				({sctag7_cpx_data_a_[149:0]}), 
		.dout				(sctag7_cpx_data_a[149:0]));
	buff_macro__dbuff_8x__minbuff_1__stack_150c__width_150 i_bufd_io_1(
		.din				({4'b0,
		io_cpx_data_ca_d1_[145:0]}), 
		.dout				(io_cpx_data_a_[149:0]));
	inv_macro__dinv_32x__stack_150c__width_150 i_inv_io_1(
		.din				({io_cpx_data_a_[149:0]}), 
		.dout				(io_cpx_data_a[149:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_dpa_t(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_dpa_t,
		ccx_bclk_dpa_t, tcu_pce_ov_dpa_t, tcu_scan_en_dpa_t}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_bfd_t(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_bfd_t,
		ccx_bclk_bfd_t, tcu_pce_ov_bfd_t, tcu_scan_en_bfd_t}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_dpa_b(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_dpa_b,
		ccx_bclk_dpa_b, tcu_pce_ov_dpa_b, tcu_scan_en_dpa_b}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_bfd_b(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_bfd_b,
		ccx_bclk_bfd_b, tcu_pce_ov_bfd_b, tcu_scan_en_bfd_b}));
	cpx_dpa cpx_dpa(
		.cpx_spc0_data_x_		(cpx_spc0_data_x_[149:0]), 
		.cpx_spc1_data_x_		(cpx_spc1_data_x_[149:0]), 
		.cpx_spc2_data_x_		(cpx_spc2_data_x_[149:0]), 
		.cpx_spc3_data_x_		(cpx_spc3_data_x_[149:0]), 
		.cpx_spc4_data_x_		(cpx_spc4_data_x_[149:0]), 
		.cpx_spc5_data_x_		(cpx_spc5_data_x_[149:0]), 
		.cpx_spc6_data_x_		(cpx_spc6_data_x_[149:0]), 
		.cpx_spc7_data_x_		(cpx_spc7_data_x_[149:0]), 
		.arb0_grant_l_a			(arb0_grant_l_a[8:0]), 
		.arb0_q0_holdbar_l_a		(arb0_q0_holdbar_l_a[8:0]), 
		.arb0_qsel0_l_a			(arb0_qsel0_l_a[8:0]), 
		.arb0_qsel1_l_a			(arb0_qsel1_l_a[8:0]), 
		.arb0_shift_l_a			(arb0_shift_l_a[8:0]), 
		.arb1_grant_l_a			(arb1_grant_l_a[8:0]), 
		.arb1_q0_holdbar_l_a		(arb1_q0_holdbar_l_a[8:0]), 
		.arb1_qsel0_l_a			(arb1_qsel0_l_a[8:0]), 
		.arb1_qsel1_l_a			(arb1_qsel1_l_a[8:0]), 
		.arb1_shift_l_a			(arb1_shift_l_a[8:0]), 
		.arb2_grant_l_a			(arb2_grant_l_a[8:0]), 
		.arb2_q0_holdbar_l_a		(arb2_q0_holdbar_l_a[8:0]), 
		.arb2_qsel0_l_a			(arb2_qsel0_l_a[8:0]), 
		.arb2_qsel1_l_a			(arb2_qsel1_l_a[8:0]), 
		.arb2_shift_l_a			(arb2_shift_l_a[8:0]), 
		.arb3_grant_l_a			(arb3_grant_l_a[8:0]), 
		.arb3_q0_holdbar_l_a		(arb3_q0_holdbar_l_a[8:0]), 
		.arb3_qsel0_l_a			(arb3_qsel0_l_a[8:0]), 
		.arb3_qsel1_l_a			(arb3_qsel1_l_a[8:0]), 
		.arb3_shift_l_a			(arb3_shift_l_a[8:0]), 
		.arb4_grant_l_a			(arb4_grant_l_a[8:0]), 
		.arb4_q0_holdbar_l_a		(arb4_q0_holdbar_l_a[8:0]), 
		.arb4_qsel0_l_a			(arb4_qsel0_l_a[8:0]), 
		.arb4_qsel1_l_a			(arb4_qsel1_l_a[8:0]), 
		.arb4_shift_l_a			(arb4_shift_l_a[8:0]), 
		.arb5_grant_l_a			(arb5_grant_l_a[8:0]), 
		.arb5_q0_holdbar_l_a		(arb5_q0_holdbar_l_a[8:0]), 
		.arb5_qsel0_l_a			(arb5_qsel0_l_a[8:0]), 
		.arb5_qsel1_l_a			(arb5_qsel1_l_a[8:0]), 
		.arb5_shift_l_a			(arb5_shift_l_a[8:0]), 
		.arb6_grant_l_a			(arb6_grant_l_a[8:0]), 
		.arb6_q0_holdbar_l_a		(arb6_q0_holdbar_l_a[8:0]), 
		.arb6_qsel0_l_a			(arb6_qsel0_l_a[8:0]), 
		.arb6_qsel1_l_a			(arb6_qsel1_l_a[8:0]), 
		.arb6_shift_l_a			(arb6_shift_l_a[8:0]), 
		.arb7_grant_l_a			(arb7_grant_l_a[8:0]), 
		.arb7_q0_holdbar_l_a		(arb7_q0_holdbar_l_a[8:0]), 
		.arb7_qsel0_l_a			(arb7_qsel0_l_a[8:0]), 
		.arb7_qsel1_l_a			(arb7_qsel1_l_a[8:0]), 
		.arb7_shift_l_a			(arb7_shift_l_a[8:0]), 
		.arb0_grant_r_a			(arb0_grant_r_a[8:0]), 
		.arb0_q0_holdbar_r_a		(arb0_q0_holdbar_r_a[8:0]), 
		.arb0_qsel0_r_a			(arb0_qsel0_r_a[8:0]), 
		.arb0_qsel1_r_a			(arb0_qsel1_r_a[8:0]), 
		.arb0_shift_r_a			(arb0_shift_r_a[8:0]), 
		.arb1_grant_r_a			(arb1_grant_r_a[8:0]), 
		.arb1_q0_holdbar_r_a		(arb1_q0_holdbar_r_a[8:0]), 
		.arb1_qsel0_r_a			(arb1_qsel0_r_a[8:0]), 
		.arb1_qsel1_r_a			(arb1_qsel1_r_a[8:0]), 
		.arb1_shift_r_a			(arb1_shift_r_a[8:0]), 
		.arb2_grant_r_a			(arb2_grant_r_a[8:0]), 
		.arb2_q0_holdbar_r_a		(arb2_q0_holdbar_r_a[8:0]), 
		.arb2_qsel0_r_a			(arb2_qsel0_r_a[8:0]), 
		.arb2_qsel1_r_a			(arb2_qsel1_r_a[8:0]), 
		.arb2_shift_r_a			(arb2_shift_r_a[8:0]), 
		.arb3_grant_r_a			(arb3_grant_r_a[8:0]), 
		.arb3_q0_holdbar_r_a		(arb3_q0_holdbar_r_a[8:0]), 
		.arb3_qsel0_r_a			(arb3_qsel0_r_a[8:0]), 
		.arb3_qsel1_r_a			(arb3_qsel1_r_a[8:0]), 
		.arb3_shift_r_a			(arb3_shift_r_a[8:0]), 
		.arb4_grant_r_a			(arb4_grant_r_a[8:0]), 
		.arb4_q0_holdbar_r_a		(arb4_q0_holdbar_r_a[8:0]), 
		.arb4_qsel0_r_a			(arb4_qsel0_r_a[8:0]), 
		.arb4_qsel1_r_a			(arb4_qsel1_r_a[8:0]), 
		.arb4_shift_r_a			(arb4_shift_r_a[8:0]), 
		.arb5_grant_r_a			(arb5_grant_r_a[8:0]), 
		.arb5_q0_holdbar_r_a		(arb5_q0_holdbar_r_a[8:0]), 
		.arb5_qsel0_r_a			(arb5_qsel0_r_a[8:0]), 
		.arb5_qsel1_r_a			(arb5_qsel1_r_a[8:0]), 
		.arb5_shift_r_a			(arb5_shift_r_a[8:0]), 
		.arb6_grant_r_a			(arb6_grant_r_a[8:0]), 
		.arb6_q0_holdbar_r_a		(arb6_q0_holdbar_r_a[8:0]), 
		.arb6_qsel0_r_a			(arb6_qsel0_r_a[8:0]), 
		.arb6_qsel1_r_a			(arb6_qsel1_r_a[8:0]), 
		.arb6_shift_r_a			(arb6_shift_r_a[8:0]), 
		.arb7_grant_r_a			(arb7_grant_r_a[8:0]), 
		.arb7_q0_holdbar_r_a		(arb7_q0_holdbar_r_a[8:0]), 
		.arb7_qsel0_r_a			(arb7_qsel0_r_a[8:0]), 
		.arb7_qsel1_r_a			(arb7_qsel1_r_a[8:0]), 
		.arb7_shift_r_a			(arb7_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(sctag0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(sctag1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(sctag2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(sctag3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(sctag4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(sctag5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(sctag6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(sctag7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dpa_scanin), 
		.scan_out			(cpx_dpa_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en_t			(tcu_scan_en_dpa_t), 
		.tcu_pce_ov_t			(tcu_pce_ov_dpa_t), 
		.ccx_aclk_t			(ccx_aclk_dpa_t), 
		.ccx_bclk_t			(ccx_bclk_dpa_t), 
		.tcu_scan_en_b			(tcu_scan_en_dpa_b), 
		.tcu_pce_ov_b			(tcu_pce_ov_dpa_b), 
		.ccx_aclk_b			(ccx_aclk_dpa_b), 
		.ccx_bclk_b			(ccx_bclk_dpa_b));
	cpx_bfd_dp bfd0(
		.cpx_spc_data_cx2		
		(cpx_spc0_data_cx2_prebuf[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_lt), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_lt), 
		.ccx_aclk_out			(ccx_aclk_bfd_lt), 
		.ccx_bclk_out			(ccx_bclk_bfd_lt), 
		.cpx_spc_data_x_		(cpx_spc0_data_x_[145:0]), 
		.scan_in			(bfd0_scanin), 
		.scan_out			(bfd0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_1), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_1), 
		.ccx_aclk			(ccx_aclk_bfd_1), 
		.ccx_bclk			(ccx_bclk_bfd_1));
	cpx_ob1_dp ob_0(
		.cpx_spc_data_cx2		(cpx_spc0_data_cx2[145:0]), 
		.cpx_spc_data_cx2_prebuf	
		(cpx_spc0_data_cx2_prebuf[145:0]));
	cpx_bfd_dp bfd1(
		.cpx_spc_data_cx2		
		(cpx_spc1_data_cx2_prebuf[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_1), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_1), 
		.ccx_aclk_out			(ccx_aclk_bfd_1), 
		.ccx_bclk_out			(ccx_bclk_bfd_1), 
		.cpx_spc_data_x_		(cpx_spc1_data_x_[145:0]), 
		.scan_in			(bfd1_scanin), 
		.scan_out			(bfd1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_t), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_t), 
		.ccx_aclk			(ccx_aclk_bfd_t), 
		.ccx_bclk			(ccx_bclk_bfd_t));
	cpx_ob1_dp ob_1(
		.cpx_spc_data_cx2		(cpx_spc1_data_cx2[145:0]), 
		.cpx_spc_data_cx2_prebuf	
		(cpx_spc1_data_cx2_prebuf[145:0]));
	cpx_bfd_dp bfd2(
		.cpx_spc_data_cx2		
		(cpx_spc2_data_cx2_prebuf[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_lb), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_lb), 
		.ccx_aclk_out			(ccx_aclk_bfd_lb), 
		.ccx_bclk_out			(ccx_bclk_bfd_lb), 
		.cpx_spc_data_x_		(cpx_spc2_data_x_[145:0]), 
		.scan_in			(bfd2_scanin), 
		.scan_out			(bfd2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_3), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_3), 
		.ccx_aclk			(ccx_aclk_bfd_3), 
		.ccx_bclk			(ccx_bclk_bfd_3));
	cpx_ob1_dp ob_2(
		.cpx_spc_data_cx2		(cpx_spc2_data_cx2[145:0]), 
		.cpx_spc_data_cx2_prebuf	
		(cpx_spc2_data_cx2_prebuf[145:0]));
	cpx_bfd_dp bfd3(
		.cpx_spc_data_cx2		
		(cpx_spc3_data_cx2_prebuf[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_3), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_3), 
		.ccx_aclk_out			(ccx_aclk_bfd_3), 
		.ccx_bclk_out			(ccx_bclk_bfd_3), 
		.cpx_spc_data_x_		(cpx_spc3_data_x_[145:0]), 
		.scan_in			(bfd3_scanin), 
		.scan_out			(bfd3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_b), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_b), 
		.ccx_aclk			(ccx_aclk_bfd_b), 
		.ccx_bclk			(ccx_bclk_bfd_b));
	cpx_ob1_dp ob_3(
		.cpx_spc_data_cx2		(cpx_spc3_data_cx2[145:0]), 
		.cpx_spc_data_cx2_prebuf	
		(cpx_spc3_data_cx2_prebuf[145:0]));
	cpx_bfd_dp bfd4(
		.cpx_spc_data_cx2		
		(cpx_spc4_data_cx2_prebuf[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_rt), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_rt), 
		.ccx_aclk_out			(ccx_aclk_bfd_rt), 
		.ccx_bclk_out			(ccx_bclk_bfd_rt), 
		.cpx_spc_data_x_		(cpx_spc4_data_x_[145:0]), 
		.scan_in			(bfd4_scanin), 
		.scan_out			(bfd4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_5), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_5), 
		.ccx_aclk			(ccx_aclk_bfd_5), 
		.ccx_bclk			(ccx_bclk_bfd_5));
	cpx_ob2_dp ob_4(
		.cpx_spc_data_cx2		(cpx_spc4_data_cx2[145:0]), 
		.cpx_spc_data_cx2_prebuf	
		(cpx_spc4_data_cx2_prebuf[145:0]));
	cpx_bfd_dp bfd5(
		.cpx_spc_data_cx2		
		(cpx_spc5_data_cx2_prebuf[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_5), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_5), 
		.ccx_aclk_out			(ccx_aclk_bfd_5), 
		.ccx_bclk_out			(ccx_bclk_bfd_5), 
		.cpx_spc_data_x_		(cpx_spc5_data_x_[145:0]), 
		.scan_in			(bfd5_scanin), 
		.scan_out			(bfd5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_t), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_t), 
		.ccx_aclk			(ccx_aclk_bfd_t), 
		.ccx_bclk			(ccx_bclk_bfd_t));
	cpx_ob2_dp ob_5(
		.cpx_spc_data_cx2		(cpx_spc5_data_cx2[145:0]), 
		.cpx_spc_data_cx2_prebuf	
		(cpx_spc5_data_cx2_prebuf[145:0]));
	cpx_bfd_dp bfd6(
		.cpx_spc_data_cx2		
		(cpx_spc6_data_cx2_prebuf[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_rb), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_rb), 
		.ccx_aclk_out			(ccx_aclk_bfd_rb), 
		.ccx_bclk_out			(ccx_bclk_bfd_rb), 
		.cpx_spc_data_x_		(cpx_spc6_data_x_[145:0]), 
		.scan_in			(bfd6_scanin), 
		.scan_out			(bfd6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_7), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_7), 
		.ccx_aclk			(ccx_aclk_bfd_7), 
		.ccx_bclk			(ccx_bclk_bfd_7));
	cpx_ob2_dp ob_6(
		.cpx_spc_data_cx2		(cpx_spc6_data_cx2[145:0]), 
		.cpx_spc_data_cx2_prebuf	
		(cpx_spc6_data_cx2_prebuf[145:0]));
	cpx_bfd_dp bfd7(
		.cpx_spc_data_cx2		
		(cpx_spc7_data_cx2_prebuf[145:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_7), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_7), 
		.ccx_aclk_out			(ccx_aclk_bfd_7), 
		.ccx_bclk_out			(ccx_bclk_bfd_7), 
		.cpx_spc_data_x_		(cpx_spc7_data_x_[145:0]), 
		.scan_in			(bfd7_scanin), 
		.scan_out			(bfd7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_b), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_b), 
		.ccx_aclk			(ccx_aclk_bfd_b), 
		.ccx_bclk			(ccx_bclk_bfd_b));
	cpx_ob2_dp ob_7(
		.cpx_spc_data_cx2		(cpx_spc7_data_cx2[145:0]), 
		.cpx_spc_data_cx2_prebuf	
		(cpx_spc7_data_cx2_prebuf[145:0]));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct0(
		.din				({sctag0_cpx_req_cq_0_l[7:0],
		sctag0_cpx_atom_cq_0_l, sctag0_cpx_atom_cq_0_l}), 
		.dout				({sctag0_cpx_req_lq[7:0],
		sctag0_cpx_atom_lq_t, sctag0_cpx_atom_lq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct1(
		.din				({sctag1_cpx_req_cq_0_l[7:0],
		sctag1_cpx_atom_cq_0_l, sctag1_cpx_atom_cq_0_l}), 
		.dout				({sctag1_cpx_req_lq[7:0],
		sctag1_cpx_atom_lq_t, sctag1_cpx_atom_lq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct2(
		.din				({sctag2_cpx_req_cq_0_l[7:0],
		sctag2_cpx_atom_cq_0_l, sctag2_cpx_atom_cq_0_l}), 
		.dout				({sctag2_cpx_req_lq[7:0],
		sctag2_cpx_atom_lq_t, sctag2_cpx_atom_lq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct3(
		.din				({sctag3_cpx_req_cq_0_l[7:0],
		sctag3_cpx_atom_cq_0_l, sctag3_cpx_atom_cq_0_l}), 
		.dout				({sctag3_cpx_req_lq[7:0],
		sctag3_cpx_atom_lq_t, sctag3_cpx_atom_lq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct4(
		.din				({sctag4_cpx_req_cq_0_l[7:0],
		sctag4_cpx_atom_cq_0_l, sctag4_cpx_atom_cq_0_l}), 
		.dout				({sctag4_cpx_req_lq[7:0],
		sctag4_cpx_atom_lq_t, sctag4_cpx_atom_lq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct5(
		.din				({sctag5_cpx_req_cq_0_l[7:0],
		sctag5_cpx_atom_cq_0_l, sctag5_cpx_atom_cq_0_l}), 
		.dout				({sctag5_cpx_req_lq[7:0],
		sctag5_cpx_atom_lq_t, sctag5_cpx_atom_lq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct6(
		.din				({sctag6_cpx_req_cq_0_l[7:0],
		sctag6_cpx_atom_cq_0_l, sctag6_cpx_atom_cq_0_l}), 
		.dout				({sctag6_cpx_req_lq[7:0],
		sctag6_cpx_atom_lq_t, sctag6_cpx_atom_lq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_l_sct7(
		.din				({sctag7_cpx_req_cq_0_l[7:0],
		sctag7_cpx_atom_cq_0_l, sctag7_cpx_atom_cq_0_l}), 
		.dout				({sctag7_cpx_req_lq[7:0],
		sctag7_cpx_atom_lq_t, sctag7_cpx_atom_lq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_8 i_bufq_l_io(
		.din				({io_cpx_req_cq_d1[7:0]}), 
		.dout				({io_cpx_req_lq[7:0]}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_lt(
		.din				({ccx_aclk_bfd_lt,
		ccx_bclk_bfd_lt, tcu_pce_ov_bfd_lt, tcu_scan_en_bfd_lt}), 
		.dout				({ccx_aclk_arb_lt,
		ccx_bclk_arb_lt, tcu_pce_ov_arb_lt, tcu_scan_en_arb_lt}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_lb(
		.din				({ccx_aclk_bfd_lb,
		ccx_bclk_bfd_lb, tcu_pce_ov_bfd_lb, tcu_scan_en_bfd_lb}), 
		.dout				({ccx_aclk_arb_lb,
		ccx_bclk_arb_lb, tcu_pce_ov_arb_lb, tcu_scan_en_arb_lb}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_rt(
		.din				({ccx_aclk_bfd_rt,
		ccx_bclk_bfd_rt, tcu_pce_ov_bfd_rt, tcu_scan_en_bfd_rt}), 
		.dout				({ccx_aclk_arb_rt,
		ccx_bclk_arb_rt, tcu_pce_ov_arb_rt, tcu_scan_en_arb_rt}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_rb(
		.din				({ccx_aclk_bfd_rb,
		ccx_bclk_bfd_rb, tcu_pce_ov_bfd_rb, tcu_scan_en_bfd_rb}), 
		.dout				({ccx_aclk_arb_rb,
		ccx_bclk_arb_rb, tcu_pce_ov_arb_rb, tcu_scan_en_arb_rb}));
	ccx_arb cpx_arbl0(
		.arb_grant_a			(arb0_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb0_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb0_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb0_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb0_shift_l_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a[0]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a[0]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a[0]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a[0]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a_unused[0]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a_unused[0]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a_unused[0]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a_unused[0]), 
		.arb_src8_grant_a		(cpx_io_grant_a[0]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_l_unused[0]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_l_unused[0]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_lq_t), 
		.src0_arb_req_q			(sctag0_cpx_req_lq[0]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_lq_t), 
		.src1_arb_req_q			(sctag1_cpx_req_lq[0]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_lq_t), 
		.src2_arb_req_q			(sctag2_cpx_req_lq[0]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_lq_t), 
		.src3_arb_req_q			(sctag3_cpx_req_lq[0]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_lq_t), 
		.src4_arb_req_q			(sctag4_cpx_req_lq[0]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_lq_t), 
		.src5_arb_req_q			(sctag5_cpx_req_lq[0]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_lq_t), 
		.src6_arb_req_q			(sctag6_cpx_req_lq[0]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_lq_t), 
		.src7_arb_req_q			(sctag7_cpx_req_lq[0]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_lq[0]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbl0_scanin), 
		.scan_out			(cpx_arbl0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	ccx_arb cpx_arbl1(
		.arb_grant_a			(arb1_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb1_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb1_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb1_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb1_shift_l_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a[1]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a[1]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a[1]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a[1]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a_unused[1]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a_unused[1]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a_unused[1]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a_unused[1]), 
		.arb_src8_grant_a		(cpx_io_grant_a[1]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_l_unused[1]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_l_unused[1]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_lq_t), 
		.src0_arb_req_q			(sctag0_cpx_req_lq[1]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_lq_t), 
		.src1_arb_req_q			(sctag1_cpx_req_lq[1]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_lq_t), 
		.src2_arb_req_q			(sctag2_cpx_req_lq[1]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_lq_t), 
		.src3_arb_req_q			(sctag3_cpx_req_lq[1]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_lq_t), 
		.src4_arb_req_q			(sctag4_cpx_req_lq[1]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_lq_t), 
		.src5_arb_req_q			(sctag5_cpx_req_lq[1]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_lq_t), 
		.src6_arb_req_q			(sctag6_cpx_req_lq[1]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_lq_t), 
		.src7_arb_req_q			(sctag7_cpx_req_lq[1]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_lq[1]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbl1_scanin), 
		.scan_out			(cpx_arbl1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	ccx_arb cpx_arbl2(
		.arb_grant_a			(arb2_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb2_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb2_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb2_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb2_shift_l_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a[2]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a[2]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a[2]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a[2]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a_unused[2]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a_unused[2]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a_unused[2]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a_unused[2]), 
		.arb_src8_grant_a		(cpx_io_grant_a[2]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_l_unused[2]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_l_unused[2]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_lq_b), 
		.src0_arb_req_q			(sctag0_cpx_req_lq[2]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_lq_b), 
		.src1_arb_req_q			(sctag1_cpx_req_lq[2]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_lq_b), 
		.src2_arb_req_q			(sctag2_cpx_req_lq[2]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_lq_b), 
		.src3_arb_req_q			(sctag3_cpx_req_lq[2]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_lq_b), 
		.src4_arb_req_q			(sctag4_cpx_req_lq[2]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_lq_b), 
		.src5_arb_req_q			(sctag5_cpx_req_lq[2]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_lq_b), 
		.src6_arb_req_q			(sctag6_cpx_req_lq[2]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_lq_b), 
		.src7_arb_req_q			(sctag7_cpx_req_lq[2]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_lq[2]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbl2_scanin), 
		.scan_out			(cpx_arbl2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lb), 
		.ccx_aclk			(ccx_aclk_arb_lb), 
		.ccx_bclk			(ccx_bclk_arb_lb));
	ccx_arb cpx_arbl3(
		.arb_grant_a			(arb3_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb3_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb3_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb3_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb3_shift_l_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a[3]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a[3]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a[3]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a[3]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a_unused[3]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a_unused[3]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a_unused[3]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a_unused[3]), 
		.arb_src8_grant_a		(cpx_io_grant_a[3]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_l_unused[3]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_l_unused[3]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_lq_b), 
		.src0_arb_req_q			(sctag0_cpx_req_lq[3]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_lq_b), 
		.src1_arb_req_q			(sctag1_cpx_req_lq[3]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_lq_b), 
		.src2_arb_req_q			(sctag2_cpx_req_lq[3]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_lq_b), 
		.src3_arb_req_q			(sctag3_cpx_req_lq[3]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_lq_b), 
		.src4_arb_req_q			(sctag4_cpx_req_lq[3]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_lq_b), 
		.src5_arb_req_q			(sctag5_cpx_req_lq[3]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_lq_b), 
		.src6_arb_req_q			(sctag6_cpx_req_lq[3]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_lq_b), 
		.src7_arb_req_q			(sctag7_cpx_req_lq[3]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_lq[3]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbl3_scanin), 
		.scan_out			(cpx_arbl3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lb), 
		.ccx_aclk			(ccx_aclk_arb_lb), 
		.ccx_bclk			(ccx_bclk_arb_lb));
	ccx_arb cpx_arbl4(
		.arb_grant_a			(arb4_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb4_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb4_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb4_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb4_shift_l_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a[4]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a[4]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a[4]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a[4]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a_unused[4]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a_unused[4]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a_unused[4]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a_unused[4]), 
		.arb_src8_grant_a		(cpx_io_grant_a[4]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_l_unused[4]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_l_unused[4]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_lq_t), 
		.src0_arb_req_q			(sctag0_cpx_req_lq[4]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_lq_t), 
		.src1_arb_req_q			(sctag1_cpx_req_lq[4]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_lq_t), 
		.src2_arb_req_q			(sctag2_cpx_req_lq[4]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_lq_t), 
		.src3_arb_req_q			(sctag3_cpx_req_lq[4]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_lq_t), 
		.src4_arb_req_q			(sctag4_cpx_req_lq[4]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_lq_t), 
		.src5_arb_req_q			(sctag5_cpx_req_lq[4]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_lq_t), 
		.src6_arb_req_q			(sctag6_cpx_req_lq[4]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_lq_t), 
		.src7_arb_req_q			(sctag7_cpx_req_lq[4]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_lq[4]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbl4_scanin), 
		.scan_out			(cpx_arbl4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	ccx_arb cpx_arbl5(
		.arb_grant_a			(arb5_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb5_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb5_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb5_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb5_shift_l_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a[5]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a[5]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a[5]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a[5]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a_unused[5]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a_unused[5]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a_unused[5]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a_unused[5]), 
		.arb_src8_grant_a		(cpx_io_grant_a[5]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_l_unused[5]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_l_unused[5]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_lq_t), 
		.src0_arb_req_q			(sctag0_cpx_req_lq[5]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_lq_t), 
		.src1_arb_req_q			(sctag1_cpx_req_lq[5]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_lq_t), 
		.src2_arb_req_q			(sctag2_cpx_req_lq[5]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_lq_t), 
		.src3_arb_req_q			(sctag3_cpx_req_lq[5]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_lq_t), 
		.src4_arb_req_q			(sctag4_cpx_req_lq[5]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_lq_t), 
		.src5_arb_req_q			(sctag5_cpx_req_lq[5]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_lq_t), 
		.src6_arb_req_q			(sctag6_cpx_req_lq[5]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_lq_t), 
		.src7_arb_req_q			(sctag7_cpx_req_lq[5]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_lq[5]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbl5_scanin), 
		.scan_out			(cpx_arbl5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	ccx_arb cpx_arbl6(
		.arb_grant_a			(arb6_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb6_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb6_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb6_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb6_shift_l_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a[6]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a[6]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a[6]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a[6]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a_unused[6]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a_unused[6]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a_unused[6]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a_unused[6]), 
		.arb_src8_grant_a		(cpx_io_grant_a[6]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_l_unused[6]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_l_unused[6]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_lq_b), 
		.src0_arb_req_q			(sctag0_cpx_req_lq[6]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_lq_b), 
		.src1_arb_req_q			(sctag1_cpx_req_lq[6]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_lq_b), 
		.src2_arb_req_q			(sctag2_cpx_req_lq[6]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_lq_b), 
		.src3_arb_req_q			(sctag3_cpx_req_lq[6]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_lq_b), 
		.src4_arb_req_q			(sctag4_cpx_req_lq[6]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_lq_b), 
		.src5_arb_req_q			(sctag5_cpx_req_lq[6]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_lq_b), 
		.src6_arb_req_q			(sctag6_cpx_req_lq[6]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_lq_b), 
		.src7_arb_req_q			(sctag7_cpx_req_lq[6]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_lq[6]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbl6_scanin), 
		.scan_out			(cpx_arbl6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lb), 
		.ccx_aclk			(ccx_aclk_arb_lb), 
		.ccx_bclk			(ccx_bclk_arb_lb));
	ccx_arb cpx_arbl7(
		.arb_grant_a			(arb7_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb7_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb7_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb7_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb7_shift_l_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a[7]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a[7]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a[7]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a[7]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a_unused[7]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a_unused[7]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a_unused[7]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a_unused[7]), 
		.arb_src8_grant_a		(cpx_io_grant_a[7]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_l_unused[7]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_l_unused[7]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_lq_b), 
		.src0_arb_req_q			(sctag0_cpx_req_lq[7]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_lq_b), 
		.src1_arb_req_q			(sctag1_cpx_req_lq[7]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_lq_b), 
		.src2_arb_req_q			(sctag2_cpx_req_lq[7]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_lq_b), 
		.src3_arb_req_q			(sctag3_cpx_req_lq[7]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_lq_b), 
		.src4_arb_req_q			(sctag4_cpx_req_lq[7]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_lq_b), 
		.src5_arb_req_q			(sctag5_cpx_req_lq[7]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_lq_b), 
		.src6_arb_req_q			(sctag6_cpx_req_lq[7]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_lq_b), 
		.src7_arb_req_q			(sctag7_cpx_req_lq[7]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_lq[7]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbl7_scanin), 
		.scan_out			(cpx_arbl7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lb), 
		.ccx_aclk			(ccx_aclk_arb_lb), 
		.ccx_bclk			(ccx_bclk_arb_lb));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct0(
		.din				({sctag0_cpx_req_cq_0_r[7:0],
		sctag0_cpx_atom_cq_0_r, sctag0_cpx_atom_cq_0_r}), 
		.dout				({sctag0_cpx_req_rq[7:0],
		sctag0_cpx_atom_rq_t, sctag0_cpx_atom_rq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct1(
		.din				({sctag1_cpx_req_cq_0_r[7:0],
		sctag1_cpx_atom_cq_0_r, sctag1_cpx_atom_cq_0_r}), 
		.dout				({sctag1_cpx_req_rq[7:0],
		sctag1_cpx_atom_rq_t, sctag1_cpx_atom_rq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct2(
		.din				({sctag2_cpx_req_cq_0_r[7:0],
		sctag2_cpx_atom_cq_0_r, sctag2_cpx_atom_cq_0_r}), 
		.dout				({sctag2_cpx_req_rq[7:0],
		sctag2_cpx_atom_rq_t, sctag2_cpx_atom_rq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct3(
		.din				({sctag3_cpx_req_cq_0_r[7:0],
		sctag3_cpx_atom_cq_0_r, sctag3_cpx_atom_cq_0_r}), 
		.dout				({sctag3_cpx_req_rq[7:0],
		sctag3_cpx_atom_rq_t, sctag3_cpx_atom_rq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct4(
		.din				({sctag4_cpx_req_cq_0_r[7:0],
		sctag4_cpx_atom_cq_0_r, sctag4_cpx_atom_cq_0_r}), 
		.dout				({sctag4_cpx_req_rq[7:0],
		sctag4_cpx_atom_rq_t, sctag4_cpx_atom_rq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct5(
		.din				({sctag5_cpx_req_cq_0_r[7:0],
		sctag5_cpx_atom_cq_0_r, sctag5_cpx_atom_cq_0_r}), 
		.dout				({sctag5_cpx_req_rq[7:0],
		sctag5_cpx_atom_rq_t, sctag5_cpx_atom_rq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct6(
		.din				({sctag6_cpx_req_cq_0_r[7:0],
		sctag6_cpx_atom_cq_0_r, sctag6_cpx_atom_cq_0_r}), 
		.dout				({sctag6_cpx_req_rq[7:0],
		sctag6_cpx_atom_rq_t, sctag6_cpx_atom_rq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_10 i_bufq_r_sct7(
		.din				({sctag7_cpx_req_cq_0_r[7:0],
		sctag7_cpx_atom_cq_0_r, sctag7_cpx_atom_cq_0_r}), 
		.dout				({sctag7_cpx_req_rq[7:0],
		sctag7_cpx_atom_rq_t, sctag7_cpx_atom_rq_b}));
	buff_macro__dbuff_48x__rep_1__stack_10r__width_8 i_bufq_r_io(
		.din				({io_cpx_req_cq_d1[7:0]}), 
		.dout				({io_cpx_req_rq[7:0]}));
	ccx_arb cpx_arbr0(
		.arb_grant_a			(arb0_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb0_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb0_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb0_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb0_shift_r_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a_unused[0]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a_unused[0]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a_unused[0]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a_unused[0]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a[0]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a[0]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a[0]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a[0]), 
		.arb_src8_grant_a		(cpx_sctag8_grant_a_unused[0]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_r_unused[0]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_r_unused[0]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_rq_t), 
		.src0_arb_req_q			(sctag0_cpx_req_rq[0]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_rq_t), 
		.src1_arb_req_q			(sctag1_cpx_req_rq[0]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_rq_t), 
		.src2_arb_req_q			(sctag2_cpx_req_rq[0]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_rq_t), 
		.src3_arb_req_q			(sctag3_cpx_req_rq[0]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_rq_t), 
		.src4_arb_req_q			(sctag4_cpx_req_rq[0]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_rq_t), 
		.src5_arb_req_q			(sctag5_cpx_req_rq[0]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_rq_t), 
		.src6_arb_req_q			(sctag6_cpx_req_rq[0]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_rq_t), 
		.src7_arb_req_q			(sctag7_cpx_req_rq[0]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_rq[0]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbr0_scanin), 
		.scan_out			(cpx_arbr0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
	ccx_arb cpx_arbr1(
		.arb_grant_a			(arb1_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb1_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb1_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb1_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb1_shift_r_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a_unused[1]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a_unused[1]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a_unused[1]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a_unused[1]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a[1]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a[1]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a[1]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a[1]), 
		.arb_src8_grant_a		(cpx_sctag8_grant_a_unused[1]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_r_unused[1]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_r_unused[1]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_rq_t), 
		.src0_arb_req_q			(sctag0_cpx_req_rq[1]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_rq_t), 
		.src1_arb_req_q			(sctag1_cpx_req_rq[1]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_rq_t), 
		.src2_arb_req_q			(sctag2_cpx_req_rq[1]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_rq_t), 
		.src3_arb_req_q			(sctag3_cpx_req_rq[1]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_rq_t), 
		.src4_arb_req_q			(sctag4_cpx_req_rq[1]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_rq_t), 
		.src5_arb_req_q			(sctag5_cpx_req_rq[1]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_rq_t), 
		.src6_arb_req_q			(sctag6_cpx_req_rq[1]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_rq_t), 
		.src7_arb_req_q			(sctag7_cpx_req_rq[1]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_rq[1]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbr1_scanin), 
		.scan_out			(cpx_arbr1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
	ccx_arb cpx_arbr2(
		.arb_grant_a			(arb2_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb2_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb2_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb2_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb2_shift_r_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a_unused[2]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a_unused[2]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a_unused[2]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a_unused[2]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a[2]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a[2]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a[2]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a[2]), 
		.arb_src8_grant_a		(cpx_sctag8_grant_a_unused[2]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_r_unused[2]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_r_unused[2]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_rq_b), 
		.src0_arb_req_q			(sctag0_cpx_req_rq[2]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_rq_b), 
		.src1_arb_req_q			(sctag1_cpx_req_rq[2]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_rq_b), 
		.src2_arb_req_q			(sctag2_cpx_req_rq[2]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_rq_b), 
		.src3_arb_req_q			(sctag3_cpx_req_rq[2]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_rq_b), 
		.src4_arb_req_q			(sctag4_cpx_req_rq[2]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_rq_b), 
		.src5_arb_req_q			(sctag5_cpx_req_rq[2]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_rq_b), 
		.src6_arb_req_q			(sctag6_cpx_req_rq[2]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_rq_b), 
		.src7_arb_req_q			(sctag7_cpx_req_rq[2]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_rq[2]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbr2_scanin), 
		.scan_out			(cpx_arbr2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rb), 
		.ccx_aclk			(ccx_aclk_arb_rb), 
		.ccx_bclk			(ccx_bclk_arb_rb));
	ccx_arb cpx_arbr3(
		.arb_grant_a			(arb3_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb3_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb3_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb3_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb3_shift_r_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a_unused[3]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a_unused[3]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a_unused[3]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a_unused[3]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a[3]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a[3]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a[3]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a[3]), 
		.arb_src8_grant_a		(cpx_sctag8_grant_a_unused[3]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_r_unused[3]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_r_unused[3]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_rq_b), 
		.src0_arb_req_q			(sctag0_cpx_req_rq[3]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_rq_b), 
		.src1_arb_req_q			(sctag1_cpx_req_rq[3]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_rq_b), 
		.src2_arb_req_q			(sctag2_cpx_req_rq[3]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_rq_b), 
		.src3_arb_req_q			(sctag3_cpx_req_rq[3]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_rq_b), 
		.src4_arb_req_q			(sctag4_cpx_req_rq[3]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_rq_b), 
		.src5_arb_req_q			(sctag5_cpx_req_rq[3]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_rq_b), 
		.src6_arb_req_q			(sctag6_cpx_req_rq[3]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_rq_b), 
		.src7_arb_req_q			(sctag7_cpx_req_rq[3]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_rq[3]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbr3_scanin), 
		.scan_out			(cpx_arbr3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rb), 
		.ccx_aclk			(ccx_aclk_arb_rb), 
		.ccx_bclk			(ccx_bclk_arb_rb));
	ccx_arb cpx_arbr4(
		.arb_grant_a			(arb4_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb4_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb4_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb4_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb4_shift_r_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a_unused[4]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a_unused[4]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a_unused[4]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a_unused[4]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a[4]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a[4]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a[4]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a[4]), 
		.arb_src8_grant_a		(cpx_sctag8_grant_a_unused[4]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_r_unused[4]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_r_unused[4]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_rq_t), 
		.src0_arb_req_q			(sctag0_cpx_req_rq[4]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_rq_t), 
		.src1_arb_req_q			(sctag1_cpx_req_rq[4]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_rq_t), 
		.src2_arb_req_q			(sctag2_cpx_req_rq[4]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_rq_t), 
		.src3_arb_req_q			(sctag3_cpx_req_rq[4]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_rq_t), 
		.src4_arb_req_q			(sctag4_cpx_req_rq[4]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_rq_t), 
		.src5_arb_req_q			(sctag5_cpx_req_rq[4]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_rq_t), 
		.src6_arb_req_q			(sctag6_cpx_req_rq[4]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_rq_t), 
		.src7_arb_req_q			(sctag7_cpx_req_rq[4]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_rq[4]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbr4_scanin), 
		.scan_out			(cpx_arbr4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
	ccx_arb cpx_arbr5(
		.arb_grant_a			(arb5_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb5_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb5_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb5_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb5_shift_r_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a_unused[5]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a_unused[5]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a_unused[5]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a_unused[5]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a[5]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a[5]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a[5]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a[5]), 
		.arb_src8_grant_a		(cpx_sctag8_grant_a_unused[5]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_r_unused[5]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_r_unused[5]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_rq_t), 
		.src0_arb_req_q			(sctag0_cpx_req_rq[5]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_rq_t), 
		.src1_arb_req_q			(sctag1_cpx_req_rq[5]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_rq_t), 
		.src2_arb_req_q			(sctag2_cpx_req_rq[5]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_rq_t), 
		.src3_arb_req_q			(sctag3_cpx_req_rq[5]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_rq_t), 
		.src4_arb_req_q			(sctag4_cpx_req_rq[5]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_rq_t), 
		.src5_arb_req_q			(sctag5_cpx_req_rq[5]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_rq_t), 
		.src6_arb_req_q			(sctag6_cpx_req_rq[5]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_rq_t), 
		.src7_arb_req_q			(sctag7_cpx_req_rq[5]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_rq[5]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbr5_scanin), 
		.scan_out			(cpx_arbr5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
	ccx_arb cpx_arbr6(
		.arb_grant_a			(arb6_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb6_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb6_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb6_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb6_shift_r_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a_unused[6]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a_unused[6]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a_unused[6]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a_unused[6]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a[6]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a[6]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a[6]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a[6]), 
		.arb_src8_grant_a		(cpx_sctag8_grant_a_unused[6]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_r_unused[6]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_r_unused[6]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_rq_b), 
		.src0_arb_req_q			(sctag0_cpx_req_rq[6]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_rq_b), 
		.src1_arb_req_q			(sctag1_cpx_req_rq[6]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_rq_b), 
		.src2_arb_req_q			(sctag2_cpx_req_rq[6]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_rq_b), 
		.src3_arb_req_q			(sctag3_cpx_req_rq[6]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_rq_b), 
		.src4_arb_req_q			(sctag4_cpx_req_rq[6]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_rq_b), 
		.src5_arb_req_q			(sctag5_cpx_req_rq[6]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_rq_b), 
		.src6_arb_req_q			(sctag6_cpx_req_rq[6]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_rq_b), 
		.src7_arb_req_q			(sctag7_cpx_req_rq[6]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_rq[6]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbr6_scanin), 
		.scan_out			(cpx_arbr6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rb), 
		.ccx_aclk			(ccx_aclk_arb_rb), 
		.ccx_bclk			(ccx_bclk_arb_rb));
	ccx_arb cpx_arbr7(
		.arb_grant_a			(arb7_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb7_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb7_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb7_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb7_shift_r_a[8:0]), 
		.arb_src0_grant_a		(cpx_sctag0_grant_a_unused[7]), 
		.arb_src1_grant_a		(cpx_sctag1_grant_a_unused[7]), 
		.arb_src2_grant_a		(cpx_sctag2_grant_a_unused[7]), 
		.arb_src3_grant_a		(cpx_sctag3_grant_a_unused[7]), 
		.arb_src4_grant_a		(cpx_sctag4_grant_a[7]), 
		.arb_src5_grant_a		(cpx_sctag5_grant_a[7]), 
		.arb_src6_grant_a		(cpx_sctag6_grant_a[7]), 
		.arb_src7_grant_a		(cpx_sctag7_grant_a[7]), 
		.arb_src8_grant_a		(cpx_sctag8_grant_a_unused[7]), 
		.ccx_dest_atom_a		(ccx_dest_atom_a_r_unused[7]), 
		.ccx_dest_data_rdy_a		
		(ccx_dest_data_rdy_a_r_unused[7]), 
		.src0_arb_atom_q		(sctag0_cpx_atom_rq_b), 
		.src0_arb_req_q			(sctag0_cpx_req_rq[7]), 
		.src1_arb_atom_q		(sctag1_cpx_atom_rq_b), 
		.src1_arb_req_q			(sctag1_cpx_req_rq[7]), 
		.src2_arb_atom_q		(sctag2_cpx_atom_rq_b), 
		.src2_arb_req_q			(sctag2_cpx_req_rq[7]), 
		.src3_arb_atom_q		(sctag3_cpx_atom_rq_b), 
		.src3_arb_req_q			(sctag3_cpx_req_rq[7]), 
		.src4_arb_atom_q		(sctag4_cpx_atom_rq_b), 
		.src4_arb_req_q			(sctag4_cpx_req_rq[7]), 
		.src5_arb_atom_q		(sctag5_cpx_atom_rq_b), 
		.src5_arb_req_q			(sctag5_cpx_req_rq[7]), 
		.src6_arb_atom_q		(sctag6_cpx_atom_rq_b), 
		.src6_arb_req_q			(sctag6_cpx_req_rq[7]), 
		.src7_arb_atom_q		(sctag7_cpx_atom_rq_b), 
		.src7_arb_req_q			(sctag7_cpx_req_rq[7]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(io_cpx_req_rq[7]), 
		.stall_q_d1			(1'b0), 
		.scan_in			(cpx_arbr7_scanin), 
		.scan_out			(cpx_arbr7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rb), 
		.ccx_aclk			(ccx_aclk_arb_rb), 
		.ccx_bclk			(ccx_bclk_arb_rb));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_scanout(
		.din				(scan_out_prebuf), 
		.dout				(scan_out));
endmodule

module buff_macro__dbuff_48x__rep_1__stack_10r__width_10(din, dout);

        input   [9:0]           din;
        output  [9:0]           dout;

        buff #(10) d0_0(
                .in                             (din[9:0]),
                .out                            (dout[9:0]));
endmodule

module buff_macro__dbuff_48x__rep_1__stack_10r__width_8(din, dout);

        input   [7:0]           din;
        output  [7:0]           dout;

        buff #(8) d0_0(
                .in                             (din[7:0]),
                .out                            (dout[7:0]));
endmodule

module buff_macro__dbuff_32x__rep_1__stack_none__width_9(din, dout);

        input   [8:0]           din;
        output  [8:0]           dout;

        buff #(9) d0_0(
                .in                             (din[8:0]),
                .out                            (dout[8:0]));
endmodule

module inv_macro__dinv_40x__stack_150c__width_150(din, dout);

        input   [149:0]         din;
        output  [149:0]         dout;

        inv #(150) d0_0(
                .in                             (din[149:0]),
                .out                            (dout[149:0]));
endmodule

module inv_diode_macro__dinv_16x__stack_150c__width_150(din, dout);

        input   [149:0]         din;
        output  [149:0]         dout;

        inv #(150) d0_0(
                .in                             (din[149:0]),
                .out                            (dout[149:0]));
endmodule

module buff_macro__dbuff_48x__rep_1__stack_10r__width_9(din, dout);

        input   [8:0]           din;
        output  [8:0]           dout;

        buff #(9) d0_0(
                .in                             (din[8:0]),
                .out                            (dout[8:0]));
endmodule

module buff_macro__dbuff_16x__rep_1__stack_none__width_8(din, dout);

        input   [7:0]           din;
        output  [7:0]           dout;

        buff #(8) d0_0(
                .in                             (din[7:0]),
                .out                            (dout[7:0]));
endmodule

module buff_macro__dbuff_32x__rep_1__stack_none__width_8(din, dout);

        input   [7:0]           din;
        output  [7:0]           dout;

        buff #(8) d0_0(
                .in                             (din[7:0]),
                .out                            (dout[7:0]));
endmodule

module buff_macro__dbuff_8x__minbuff_1__stack_150c__width_150(din, dout);

        input   [149:0]         din;
        output  [149:0]         dout;

        buff #(150) d0_0(
                .in                             (din[149:0]),
                .out                            (dout[149:0]));
endmodule

module inv_macro__dinv_32x__stack_150c__width_150(din, dout);

        input   [149:0]         din;
        output  [149:0]         dout;

        inv #(150) d0_0(
                .in                             (din[149:0]),
                .out                            (dout[149:0]));
endmodule


`endif // `ifdef FPGA
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_bfd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_bfd_dp (
  cpx_spc_data_cx2, 
  cpx_spc_data_x_, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire [145:0] in;
wire [145:0] in_swz;
wire i_dff_data_0_scanin;
wire i_dff_data_0_scanout;
wire [145:0] in_x2;
wire i_dff_data_1_scanin;
wire i_dff_data_1_scanout;
wire i_dff_data_2_scanin;
wire i_dff_data_2_scanout;
wire i_dff_data_3_scanin;
wire i_dff_data_3_scanout;
wire [145:0] in_px2;
wire [145:0] out_swz;
wire scan_out_prebuf;


output [145:0] cpx_spc_data_cx2;

input [145:0] cpx_spc_data_x_;

//globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

// buffer the high fanout nets
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk = ccx_aclk_out;
assign soclk = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan


cpx_bfd_dp_buff_macro__dbuff_8x__stack_none__width_4 buf_hfn    (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

assign in[145:0] = cpx_spc_data_x_[145:0];

assign in_swz[72:0] =     {
                           in[144],in[142],in[140],
                           in[138],in[136],in[134],in[132],in[130],in[128],in[126],in[124],in[122],in[120],
                           in[118],in[116],in[114],in[112],in[110],in[108],in[106],in[104],in[102],in[100],
                           in[98],in[96],in[94],in[92],in[90],in[88],in[86],in[84],in[82],in[80],
                           in[78],in[76],in[74],in[72],in[70],in[68],in[66],in[64],in[62],in[60],
                           in[58],in[56],in[54],in[52],in[50],in[48],in[46],in[44],in[42],in[40],
                           in[38],in[36],in[34],in[32],in[30],in[28],in[26],in[24],in[22],in[20],
                           in[18],in[16],in[14],in[12],in[10],in[8],in[6],in[4],in[2],in[0]
                           };


assign in_swz[145:73] =   {
                           in[145],in[143],in[141],
                           in[139],in[137],in[135],in[133],in[131],in[129],in[127],in[125],in[123],in[121],
                           in[119],in[117],in[115],in[113],in[111],in[109],in[107],in[105],in[103],in[101],
                           in[99],in[97],in[95],in[93],in[91],in[89],in[87],in[85],in[83],in[81],
                           in[79],in[77],in[75],in[73],in[71],in[69],in[67],in[65],in[63],in[61],
                           in[59],in[57],in[55],in[53],in[51],in[49],in[47],in[45],in[43],in[41],
                           in[39],in[37],in[35],in[33],in[31],in[29],in[27],in[25],in[23],in[21],
                           in[19],in[17],in[15],in[13],in[11],in[9],in[7],in[5],in[3],in[1]
                           };


cpx_bfd_dp_msffiz_macro__dmsffi_32x__stack_64c__width_64 i_dff_data_0    (
	.scan_in(i_dff_data_0_scanin),
	.scan_out(i_dff_data_0_scanout),
	.clk	(l2clk),
	.din	({in_swz[63:0]}),
	.dout_l	({in_x2[63:0]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

cpx_bfd_dp_msffiz_macro__dmsffi_32x__scanreverse_1__stack_64c__width_64 i_dff_data_1     (
	.scan_in(i_dff_data_1_scanin),
	.scan_out(i_dff_data_1_scanout),
	.clk	(l2clk),
	.din	({in_swz[136:73]}),
	.dout_l	({in_x2[136:73]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

cpx_bfd_dp_msffiz_macro__dmsffi_32x__stack_10l__width_9 i_dff_data_2    (
	.scan_in(i_dff_data_2_scanin),
	.scan_out(i_dff_data_2_scanout),
	.clk	(l2clk),
	.din	({in_swz[72:64]}),
	.dout_l	({in_x2[72:64]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

cpx_bfd_dp_msffiz_macro__dmsffi_32x__stack_10l__width_9 i_dff_data_3    (
	.scan_in(i_dff_data_3_scanin),
	.scan_out(i_dff_data_3_scanout),
	.clk	(l2clk),
	.din	({in_swz[145:137]}),
	.dout_l	({in_x2[145:137]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

//buff_macro i_buf_data_0 (dbuff=32x, width=64, stack=64c) (
//	  .din	({in_x2[63:0] }),
//	  .dout	({in_px2[63:0]}),
//);
//
//buff_macro i_buf_data_1 (dbuff=32x, width=64, stack=64c) (
//	  .din	({in_x2[136:73]}),
//	  .dout	({in_px2[136:73]}),
//);
//
//buff_macro i_buf_data_2 (dbuff=32x, width=9, stack=none) (
//	  .din	({in_x2[72:64]}),
//	  .dout	({in_px2[72:64]}),
//);
//
//buff_macro i_buf_data_3 (dbuff=32x, width=9, stack=none) (
//	  .din	({in_x2[145:137]}),
//	  .dout	({in_px2[145:137]}),
//);

assign in_px2[145:0] = in_x2[145:0];

assign {
        out_swz[144],out_swz[142],out_swz[140],
        out_swz[138],out_swz[136],out_swz[134],out_swz[132],out_swz[130],out_swz[128],out_swz[126],out_swz[124],out_swz[122],out_swz[120],
        out_swz[118],out_swz[116],out_swz[114],out_swz[112],out_swz[110],out_swz[108],out_swz[106],out_swz[104],out_swz[102],out_swz[100],
        out_swz[98],out_swz[96],out_swz[94],out_swz[92],out_swz[90],out_swz[88],out_swz[86],out_swz[84],out_swz[82],out_swz[80],
        out_swz[78],out_swz[76],out_swz[74],out_swz[72],out_swz[70],out_swz[68],out_swz[66],out_swz[64],out_swz[62],out_swz[60],
        out_swz[58],out_swz[56],out_swz[54],out_swz[52],out_swz[50],out_swz[48],out_swz[46],out_swz[44],out_swz[42],out_swz[40],
        out_swz[38],out_swz[36],out_swz[34],out_swz[32],out_swz[30],out_swz[28],out_swz[26],out_swz[24],out_swz[22],out_swz[20],
        out_swz[18],out_swz[16],out_swz[14],out_swz[12],out_swz[10],out_swz[8],out_swz[6],out_swz[4],out_swz[2],out_swz[0]
        } = in_px2[72:0];


assign {
        out_swz[145],out_swz[143],out_swz[141],
        out_swz[139],out_swz[137],out_swz[135],out_swz[133],out_swz[131],out_swz[129],out_swz[127],out_swz[125],out_swz[123],out_swz[121],
        out_swz[119],out_swz[117],out_swz[115],out_swz[113],out_swz[111],out_swz[109],out_swz[107],out_swz[105],out_swz[103],out_swz[101],
        out_swz[99],out_swz[97],out_swz[95],out_swz[93],out_swz[91],out_swz[89],out_swz[87],out_swz[85],out_swz[83],out_swz[81],
        out_swz[79],out_swz[77],out_swz[75],out_swz[73],out_swz[71],out_swz[69],out_swz[67],out_swz[65],out_swz[63],out_swz[61],
        out_swz[59],out_swz[57],out_swz[55],out_swz[53],out_swz[51],out_swz[49],out_swz[47],out_swz[45],out_swz[43],out_swz[41],
        out_swz[39],out_swz[37],out_swz[35],out_swz[33],out_swz[31],out_swz[29],out_swz[27],out_swz[25],out_swz[23],out_swz[21],
        out_swz[19],out_swz[17],out_swz[15],out_swz[13],out_swz[11],out_swz[9],out_swz[7],out_swz[5],out_swz[3],out_swz[1]
        } = in_px2[145:73];


assign cpx_spc_data_cx2[145:0] = out_swz[145:0];

cpx_bfd_dp_buff_macro__dbuff_8x__stack_none__width_1 buf_scanout    (
	.din	(scan_out_prebuf),
	.dout	(scan_out)
);


// fixscan start:
assign i_dff_data_0_scanin       = scan_in                  ;
assign i_dff_data_1_scanin       = i_dff_data_0_scanout     ;
assign i_dff_data_2_scanin       = i_dff_data_1_scanout     ;
assign i_dff_data_3_scanin       = i_dff_data_2_scanout     ;
assign scan_out_prebuf           = i_dff_data_3_scanout     ;
// fixscan end:
endmodule // cpx_bfs_dp


//
//   buff macro
//
//


module cpx_bfd_dp_buff_macro__dbuff_8x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_bfd_dp_msffiz_macro__dmsffi_32x__stack_64c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout_l, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout_l;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
msffiz_dp #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q_l(dout_l[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_bfd_dp_msffiz_macro__dmsffi_32x__scanreverse_1__stack_64c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout_l, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout_l;


  output scan_out;


  wire [0:62] so;

cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
msffiz_dp #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({so[0:62],scan_in}),
.so({scan_out,so[0:62]}),
.q_l(dout_l[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_bfd_dp_msffiz_macro__dmsffi_32x__stack_10l__width_9 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout_l, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [7:0] so;

  input [8:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [8:0] dout_l;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
msffiz_dp #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q_l(dout_l[8:0])
);


endmodule


//
//   buff macro
//
//


module cpx_bfd_dp_buff_macro__dbuff_8x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_bfd_dp(cpx_spc_data_cx2, cpx_spc_data_x_, tcu_scan_en, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out, ccx_aclk_out, 
	ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[145:0]		cpx_spc_data_cx2;
	input	[145:0]		cpx_spc_data_x_;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk;
	wire			soclk;
	wire			se;
	wire	[145:0]		in;
	wire	[145:0]		in_swz;
	wire			i_dff_data_0_scanin;
	wire			i_dff_data_0_scanout;
	wire	[145:0]		in_x2;
	wire			i_dff_data_1_scanin;
	wire			i_dff_data_1_scanout;
	wire			i_dff_data_2_scanin;
	wire			i_dff_data_2_scanout;
	wire			i_dff_data_3_scanin;
	wire			i_dff_data_3_scanout;
	wire	[145:0]		in_px2;
	wire	[145:0]		out_swz;
	wire			scan_out_prebuf;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk = ccx_aclk_out;
	assign soclk = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign in[145:0] = cpx_spc_data_x_[145:0];
	assign in_swz[72:0] = {in[144], in[142], in[140], in[138], in[136], 
		in[134], in[132], in[130], in[128], in[126], in[124], in[122], 
		in[120], in[118], in[116], in[114], in[112], in[110], in[108], 
		in[106], in[104], in[102], in[100], in[98], in[96], in[94], 
		in[92], in[90], in[88], in[86], in[84], in[82], in[80], in[78], 
		in[76], in[74], in[72], in[70], in[68], in[66], in[64], in[62], 
		in[60], in[58], in[56], in[54], in[52], in[50], in[48], in[46], 
		in[44], in[42], in[40], in[38], in[36], in[34], in[32], in[30], 
		in[28], in[26], in[24], in[22], in[20], in[18], in[16], in[14], 
		in[12], in[10], in[8], in[6], in[4], in[2], in[0]};
	assign in_swz[145:73] = {in[145], in[143], in[141], in[139], in[137], 
		in[135], in[133], in[131], in[129], in[127], in[125], in[123], 
		in[121], in[119], in[117], in[115], in[113], in[111], in[109], 
		in[107], in[105], in[103], in[101], in[99], in[97], in[95], 
		in[93], in[91], in[89], in[87], in[85], in[83], in[81], in[79], 
		in[77], in[75], in[73], in[71], in[69], in[67], in[65], in[63], 
		in[61], in[59], in[57], in[55], in[53], in[51], in[49], in[47], 
		in[45], in[43], in[41], in[39], in[37], in[35], in[33], in[31], 
		in[29], in[27], in[25], in[23], in[21], in[19], in[17], in[15], 
		in[13], in[11], in[9], in[7], in[5], in[3], in[1]};
	assign in_px2[145:0] = in_x2[145:0];
	assign {out_swz[144], out_swz[142], out_swz[140], out_swz[138], 
		out_swz[136], out_swz[134], out_swz[132], out_swz[130], 
		out_swz[128], out_swz[126], out_swz[124], out_swz[122], 
		out_swz[120], out_swz[118], out_swz[116], out_swz[114], 
		out_swz[112], out_swz[110], out_swz[108], out_swz[106], 
		out_swz[104], out_swz[102], out_swz[100], out_swz[98], 
		out_swz[96], out_swz[94], out_swz[92], out_swz[90], out_swz[88],
		out_swz[86], out_swz[84], out_swz[82], out_swz[80], out_swz[78],
		out_swz[76], out_swz[74], out_swz[72], out_swz[70], out_swz[68],
		out_swz[66], out_swz[64], out_swz[62], out_swz[60], out_swz[58],
		out_swz[56], out_swz[54], out_swz[52], out_swz[50], out_swz[48],
		out_swz[46], out_swz[44], out_swz[42], out_swz[40], out_swz[38],
		out_swz[36], out_swz[34], out_swz[32], out_swz[30], out_swz[28],
		out_swz[26], out_swz[24], out_swz[22], out_swz[20], out_swz[18],
		out_swz[16], out_swz[14], out_swz[12], out_swz[10], out_swz[8], 
		out_swz[6], out_swz[4], out_swz[2], out_swz[0]} = in_px2[72:0];
	assign {out_swz[145], out_swz[143], out_swz[141], out_swz[139], 
		out_swz[137], out_swz[135], out_swz[133], out_swz[131], 
		out_swz[129], out_swz[127], out_swz[125], out_swz[123], 
		out_swz[121], out_swz[119], out_swz[117], out_swz[115], 
		out_swz[113], out_swz[111], out_swz[109], out_swz[107], 
		out_swz[105], out_swz[103], out_swz[101], out_swz[99], 
		out_swz[97], out_swz[95], out_swz[93], out_swz[91], out_swz[89],
		out_swz[87], out_swz[85], out_swz[83], out_swz[81], out_swz[79],
		out_swz[77], out_swz[75], out_swz[73], out_swz[71], out_swz[69],
		out_swz[67], out_swz[65], out_swz[63], out_swz[61], out_swz[59],
		out_swz[57], out_swz[55], out_swz[53], out_swz[51], out_swz[49],
		out_swz[47], out_swz[45], out_swz[43], out_swz[41], out_swz[39],
		out_swz[37], out_swz[35], out_swz[33], out_swz[31], out_swz[29],
		out_swz[27], out_swz[25], out_swz[23], out_swz[21], out_swz[19],
		out_swz[17], out_swz[15], out_swz[13], out_swz[11], out_swz[9], 
		out_swz[7], out_swz[5], out_swz[3], out_swz[1]} = in_px2[145:73]
		;
	assign cpx_spc_data_cx2[145:0] = out_swz[145:0];
	assign i_dff_data_0_scanin = scan_in;
	assign i_dff_data_1_scanin = i_dff_data_0_scanout;
	assign i_dff_data_2_scanin = i_dff_data_1_scanout;
	assign i_dff_data_3_scanin = i_dff_data_2_scanout;
	assign scan_out_prebuf = i_dff_data_3_scanout;

	buff_macro__dbuff_8x__stack_none__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	msffiz_macro__dmsffi_32x__stack_64c__width_64 i_dff_data_0(
		.scan_in			(i_dff_data_0_scanin), 
		.scan_out			(i_dff_data_0_scanout), 
		.clk				(l2clk), 
		.din				({in_swz[63:0]}), 
		.dout_l				({in_x2[63:0]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msffiz_macro__dmsffi_32x__scanreverse_1__stack_64c__width_64 
		i_dff_data_1(
		.scan_in			(i_dff_data_1_scanin), 
		.scan_out			(i_dff_data_1_scanout), 
		.clk				(l2clk), 
		.din				({in_swz[136:73]}), 
		.dout_l				({in_x2[136:73]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msffiz_macro__dmsffi_32x__stack_10l__width_9 i_dff_data_2(
		.scan_in			(i_dff_data_2_scanin), 
		.scan_out			(i_dff_data_2_scanout), 
		.clk				(l2clk), 
		.din				({in_swz[72:64]}), 
		.dout_l				({in_x2[72:64]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msffiz_macro__dmsffi_32x__stack_10l__width_9 i_dff_data_3(
		.scan_in			(i_dff_data_3_scanin), 
		.scan_out			(i_dff_data_3_scanout), 
		.clk				(l2clk), 
		.din				({in_swz[145:137]}), 
		.dout_l				({in_x2[145:137]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	buff_macro__dbuff_8x__stack_none__width_1 buf_scanout(
		.din				(scan_out_prebuf), 
		.dout				(scan_out));
endmodule

module msffiz_macro__dmsffi_32x__stack_10l__width_9(din, clk, en, se, scan_in,
        siclk, soclk, pce_ov, stop, dout_l, scan_out);

        input   [8:0]           din;
        input                   clk;
        input                   en;
        input                   se;
        input                   scan_in;
        input                   siclk;
        input                   soclk;
        input                   pce_ov;
        input                   stop;
        output  [8:0]           dout_l;
        output                  scan_out;

        wire                    l1clk;
        wire                    siclk_out;
        wire                    soclk_out;
        wire    [7:0]           so;

        cl_dp1_l1hdr_8x c0_0(
                .l2clk                          (clk),
                .pce                            (en),
                .aclk                           (siclk),
                .bclk                           (soclk),
                .l1clk                          (l1clk),
                .se                             (se),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out));

        msffiz_dp #(9) d0_0(
                .l1clk                          (l1clk),
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .d                              (din[8:0]),
                .si                             ({scan_in, so[7:0]}),
                .so                             ({so[7:0], scan_out}),
                .q_l                            (dout_l[8:0]));
endmodule

module buff_macro__dbuff_8x__stack_none__width_4(din, dout);

        input   [3:0]           din;
        output  [3:0]           dout;

        buff #(4) d0_0(
                .in                             (din[3:0]),
                .out                            (dout[3:0]));
endmodule

module msffiz_macro__dmsffi_32x__scanreverse_1__stack_64c__width_64(din, clk,
        en, se, scan_in, siclk, soclk, pce_ov, stop, dout_l, scan_out);

        input   [63:0]          din;
        input                   clk;
        input                   en;
        input                   se;
        input                   scan_in;
        input                   siclk;
        input                   soclk;
        input                   pce_ov;
        input                   stop;
        output  [63:0]          dout_l;
        output                  scan_out;

        wire                    l1clk;
        wire                    siclk_out;
        wire                    soclk_out;
        wire    [0:62]          so;

        cl_dp1_l1hdr_8x c0_0(
                .l2clk                          (clk),
                .pce                            (en),
                .aclk                           (siclk),
                .bclk                           (soclk),
                .l1clk                          (l1clk),
                .se                             (se),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out));
        msffiz_dp #(64) d0_0(
                .l1clk                          (l1clk),
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .d                              (din[63:0]),
                .si                             ({so[0:62], scan_in}),
                .so                             ({scan_out, so[0:62]}),
                .q_l                            (dout_l[63:0]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_bfg_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_bfg_dp (
  cpx_sctag_grant_cx, 
  cpx_sctag_grant_ca, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire i_dff_grant_x_scanin;
wire i_dff_grant_x_scanout;
wire [7:0] cpx_sctag_grant_x;
wire scan_out_prebuf;


output [7:0] cpx_sctag_grant_cx;

input [7:0] cpx_sctag_grant_ca;

//globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

// buffer the high fanout nets
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk = ccx_aclk_out;
assign soclk = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

cpx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_4 buf_hfn    (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);


cpx_bfg_dp_msff_macro__stack_8r__width_8 i_dff_grant_x   (
	.scan_in(i_dff_grant_x_scanin),
	.scan_out(i_dff_grant_x_scanout),
	.clk	(l2clk),
	.din	(cpx_sctag_grant_ca[7:0]),
	.dout	(cpx_sctag_grant_x[7:0]),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

cpx_bfg_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_buf_grant_x     (
	.din	(cpx_sctag_grant_x[7:0]),
	.dout	(cpx_sctag_grant_cx[7:0])
);

cpx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_1 buf_scanout    (
	.din	(scan_out_prebuf),
	.dout	(scan_out)
);

// fixscan start:
assign i_dff_grant_x_scanin      = scan_in                  ;
assign scan_out_prebuf                  = i_dff_grant_x_scanout    ;
// fixscan end:
endmodule // cpx_bfs_dp


//
//   buff macro
//
//


module cpx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_bfg_dp_msff_macro__stack_8r__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module cpx_bfg_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module cpx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module cpx_bfg_dp(cpx_sctag_grant_cx, cpx_sctag_grant_ca, tcu_scan_en, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out, ccx_aclk_out, 
	ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[7:0]		cpx_sctag_grant_cx;
	input	[7:0]		cpx_sctag_grant_ca;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk;
	wire			soclk;
	wire			se;
	wire			i_dff_grant_x_scanin;
	wire			i_dff_grant_x_scanout;
	wire	[7:0]		cpx_sctag_grant_x;
	wire			scan_out_prebuf;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk = ccx_aclk_out;
	assign soclk = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign i_dff_grant_x_scanin = scan_in;
	assign scan_out_prebuf = i_dff_grant_x_scanout;

	buff_macro__dbuff_8x__stack_none__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	msff_macro__stack_8r__width_8 i_dff_grant_x(
		.scan_in			(i_dff_grant_x_scanin), 
		.scan_out			(i_dff_grant_x_scanout), 
		.clk				(l2clk), 
		.din				(cpx_sctag_grant_ca[7:0]), 
		.dout				(cpx_sctag_grant_x[7:0]), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	buff_macro__dbuff_32x__rep_1__stack_none__width_8 i_buf_grant_x(
		.din				(cpx_sctag_grant_x[7:0]), 
		.dout				(cpx_sctag_grant_cx[7:0]));
	buff_macro__dbuff_8x__stack_none__width_1 buf_scanout(
		.din				(scan_out_prebuf), 
		.dout				(scan_out));
endmodule


module msff_macro__stack_8r__width_8(din, clk, en, se, scan_in, siclk, soclk,
        pce_ov, stop, dout, scan_out);

        input   [7:0]           din;
        input                   clk;
        input                   en;
        input                   se;
        input                   scan_in;
        input                   siclk;
        input                   soclk;
        input                   pce_ov;
        input                   stop;
        output  [7:0]           dout;
        output                  scan_out;

        wire                    l1clk;
        wire                    siclk_out;
        wire                    soclk_out;
        wire    [6:0]           so;

        cl_dp1_l1hdr_8x c0_0(
                .l2clk                          (clk),
                .pce                            (en),
                .aclk                           (siclk),
                .bclk                           (soclk),
                .l1clk                          (l1clk),
                .se                             (se),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out));
        dff #(8) d0_0(
                .l1clk                          (l1clk),
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .d                              (din[7:0]),
                .si                             ({scan_in, so[6:0]}),
                .so                             ({so[6:0], scan_out}),
                .q                              (dout[7:0]));
endmodule

`ifdef FPGA
`else 
`celldefine
module buff_macro__dbuff_8x__stack_none__width_1(din, dout);

        input   [0:0]           din;
        output  [0:0]           dout;

        buff #(1) d0_0(
                .in                             (din[0]),
                .out                            (dout[0]));
endmodule
`endcelldefine

`celldefine
module buff_macro__dbuff_8x__stack_none__width_1(din, dout);

        input   [0:0]           din;
        output  [0:0]           dout;

        buff #(1) d0_0(
                .in                             (din[0]),
                .out                            (dout[0]));
endmodule
`endcelldefine

`endif // `ifdef FPGA


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_dpa.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_dpa (
  cpx_spc0_data_x_, 
  cpx_spc1_data_x_, 
  cpx_spc2_data_x_, 
  cpx_spc3_data_x_, 
  cpx_spc4_data_x_, 
  cpx_spc5_data_x_, 
  cpx_spc6_data_x_, 
  cpx_spc7_data_x_, 
  arb0_grant_l_a, 
  arb0_q0_holdbar_l_a, 
  arb0_qsel0_l_a, 
  arb0_qsel1_l_a, 
  arb0_shift_l_a, 
  arb1_grant_l_a, 
  arb1_q0_holdbar_l_a, 
  arb1_qsel0_l_a, 
  arb1_qsel1_l_a, 
  arb1_shift_l_a, 
  arb2_grant_l_a, 
  arb2_q0_holdbar_l_a, 
  arb2_qsel0_l_a, 
  arb2_qsel1_l_a, 
  arb2_shift_l_a, 
  arb3_grant_l_a, 
  arb3_q0_holdbar_l_a, 
  arb3_qsel0_l_a, 
  arb3_qsel1_l_a, 
  arb3_shift_l_a, 
  arb4_grant_l_a, 
  arb4_q0_holdbar_l_a, 
  arb4_qsel0_l_a, 
  arb4_qsel1_l_a, 
  arb4_shift_l_a, 
  arb5_grant_l_a, 
  arb5_q0_holdbar_l_a, 
  arb5_qsel0_l_a, 
  arb5_qsel1_l_a, 
  arb5_shift_l_a, 
  arb6_grant_l_a, 
  arb6_q0_holdbar_l_a, 
  arb6_qsel0_l_a, 
  arb6_qsel1_l_a, 
  arb6_shift_l_a, 
  arb7_grant_l_a, 
  arb7_q0_holdbar_l_a, 
  arb7_qsel0_l_a, 
  arb7_qsel1_l_a, 
  arb7_shift_l_a, 
  arb0_grant_r_a, 
  arb0_q0_holdbar_r_a, 
  arb0_qsel0_r_a, 
  arb0_qsel1_r_a, 
  arb0_shift_r_a, 
  arb1_grant_r_a, 
  arb1_q0_holdbar_r_a, 
  arb1_qsel0_r_a, 
  arb1_qsel1_r_a, 
  arb1_shift_r_a, 
  arb2_grant_r_a, 
  arb2_q0_holdbar_r_a, 
  arb2_qsel0_r_a, 
  arb2_qsel1_r_a, 
  arb2_shift_r_a, 
  arb3_grant_r_a, 
  arb3_q0_holdbar_r_a, 
  arb3_qsel0_r_a, 
  arb3_qsel1_r_a, 
  arb3_shift_r_a, 
  arb4_grant_r_a, 
  arb4_q0_holdbar_r_a, 
  arb4_qsel0_r_a, 
  arb4_qsel1_r_a, 
  arb4_shift_r_a, 
  arb5_grant_r_a, 
  arb5_q0_holdbar_r_a, 
  arb5_qsel0_r_a, 
  arb5_qsel1_r_a, 
  arb5_shift_r_a, 
  arb6_grant_r_a, 
  arb6_q0_holdbar_r_a, 
  arb6_qsel0_r_a, 
  arb6_qsel1_r_a, 
  arb6_shift_r_a, 
  arb7_grant_r_a, 
  arb7_q0_holdbar_r_a, 
  arb7_qsel0_r_a, 
  arb7_qsel1_r_a, 
  arb7_shift_r_a, 
  io_cpx_data_a, 
  scache0_cpx_data_a, 
  scache1_cpx_data_a, 
  scache2_cpx_data_a, 
  scache3_cpx_data_a, 
  scache4_cpx_data_a, 
  scache5_cpx_data_a, 
  scache6_cpx_data_a, 
  scache7_cpx_data_a, 
  l2clk, 
  scan_in, 
  tcu_pce_ov_t, 
  tcu_scan_en_t, 
  ccx_aclk_t, 
  ccx_bclk_t, 
  tcu_pce_ov_b, 
  tcu_scan_en_b, 
  ccx_aclk_b, 
  ccx_bclk_b, 
  scan_out);
wire cpx_dps0_scanin;
wire cpx_dps0_scanout;
wire cpx_dps1_scanin;
wire cpx_dps1_scanout;
wire cpx_dps2_scanin;
wire cpx_dps2_scanout;
wire cpx_dps3_scanin;
wire cpx_dps3_scanout;
wire cpx_dps4_scanin;
wire cpx_dps4_scanout;
wire cpx_dps5_scanin;
wire cpx_dps5_scanout;
wire cpx_dps6_scanin;
wire cpx_dps6_scanout;
wire cpx_dps7_scanin;
wire cpx_dps7_scanout;


// Beginning of automatic outputs (from unused autoinst outputs)
output [149:0]          cpx_spc0_data_x_;       // From cpx_dp0 of cpx_dp.v
output [149:0]          cpx_spc1_data_x_;       // From cpx_dp1 of cpx_dp.v
output [149:0]          cpx_spc2_data_x_;       // From cpx_dp2 of cpx_dp.v
output [149:0]          cpx_spc3_data_x_;       // From cpx_dp3 of cpx_dp.v
output [149:0]          cpx_spc4_data_x_;       // From cpx_dp4 of cpx_dp.v
output [149:0]          cpx_spc5_data_x_;       // From cpx_dp5 of cpx_dp.v
output [149:0]          cpx_spc6_data_x_;       // From cpx_dp6 of cpx_dp.v
output [149:0]          cpx_spc7_data_x_;       // From cpx_dp7 of cpx_dp.v

// End of automatics


// Beginning of automatic inputs (from unused autoinst inputs)
input [8:0]             arb0_grant_l_a;           // To cpx_dp0 of cpx_dp.v
input [8:0]             arb0_q0_holdbar_l_a;         // To cpx_dp0 of cpx_dp.v
input [8:0]             arb0_qsel0_l_a;           // To cpx_dp0 of cpx_dp.v
input [8:0]             arb0_qsel1_l_a;           // To cpx_dp0 of cpx_dp.v
input [8:0]             arb0_shift_l_a;           // To cpx_dp0 of cpx_dp.v
input [8:0]             arb1_grant_l_a;           // To cpx_dp1 of cpx_dp.v
input [8:0]             arb1_q0_holdbar_l_a;         // To cpx_dp1 of cpx_dp.v
input [8:0]             arb1_qsel0_l_a;           // To cpx_dp1 of cpx_dp.v
input [8:0]             arb1_qsel1_l_a;           // To cpx_dp1 of cpx_dp.v
input [8:0]             arb1_shift_l_a;           // To cpx_dp1 of cpx_dp.v
input [8:0]             arb2_grant_l_a;           // To cpx_dp2 of cpx_dp.v
input [8:0]             arb2_q0_holdbar_l_a;         // To cpx_dp2 of cpx_dp.v
input [8:0]             arb2_qsel0_l_a;           // To cpx_dp2 of cpx_dp.v
input [8:0]             arb2_qsel1_l_a;           // To cpx_dp2 of cpx_dp.v
input [8:0]             arb2_shift_l_a;           // To cpx_dp2 of cpx_dp.v
input [8:0]             arb3_grant_l_a;           // To cpx_dp3 of cpx_dp.v
input [8:0]             arb3_q0_holdbar_l_a;         // To cpx_dp3 of cpx_dp.v
input [8:0]             arb3_qsel0_l_a;           // To cpx_dp3 of cpx_dp.v
input [8:0]             arb3_qsel1_l_a;           // To cpx_dp3 of cpx_dp.v
input [8:0]             arb3_shift_l_a;           // To cpx_dp3 of cpx_dp.v
input [8:0]             arb4_grant_l_a;           // To cpx_dp4 of cpx_dp.v
input [8:0]             arb4_q0_holdbar_l_a;         // To cpx_dp4 of cpx_dp.v
input [8:0]             arb4_qsel0_l_a;           // To cpx_dp4 of cpx_dp.v
input [8:0]             arb4_qsel1_l_a;           // To cpx_dp4 of cpx_dp.v
input [8:0]             arb4_shift_l_a;           // To cpx_dp4 of cpx_dp.v
input [8:0]             arb5_grant_l_a;           // To cpx_dp5 of cpx_dp.v
input [8:0]             arb5_q0_holdbar_l_a;         // To cpx_dp5 of cpx_dp.v
input [8:0]             arb5_qsel0_l_a;           // To cpx_dp5 of cpx_dp.v
input [8:0]             arb5_qsel1_l_a;           // To cpx_dp5 of cpx_dp.v
input [8:0]             arb5_shift_l_a;           // To cpx_dp5 of cpx_dp.v
input [8:0]             arb6_grant_l_a;           // To cpx_dp6 of cpx_dp.v
input [8:0]             arb6_q0_holdbar_l_a;         // To cpx_dp6 of cpx_dp.v
input [8:0]             arb6_qsel0_l_a;           // To cpx_dp6 of cpx_dp.v
input [8:0]             arb6_qsel1_l_a;           // To cpx_dp6 of cpx_dp.v
input [8:0]             arb6_shift_l_a;           // To cpx_dp6 of cpx_dp.v
input [8:0]             arb7_grant_l_a;           // To cpx_dp7 of cpx_dp.v
input [8:0]             arb7_q0_holdbar_l_a;         // To cpx_dp7 of cpx_dp.v
input [8:0]             arb7_qsel0_l_a;           // To cpx_dp7 of cpx_dp.v
input [8:0]             arb7_qsel1_l_a;           // To cpx_dp7 of cpx_dp.v
input [8:0]             arb7_shift_l_a;           // To cpx_dp7 of cpx_dp.v
input [8:0]             arb0_grant_r_a;           // To cpx_dp0 of cpx_dp.v
input [8:0]             arb0_q0_holdbar_r_a;         // To cpx_dp0 of cpx_dp.v
input [8:0]             arb0_qsel0_r_a;           // To cpx_dp0 of cpx_dp.v
input [8:0]             arb0_qsel1_r_a;           // To cpx_dp0 of cpx_dp.v
input [8:0]             arb0_shift_r_a;           // To cpx_dp0 of cpx_dp.v
input [8:0]             arb1_grant_r_a;           // To cpx_dp1 of cpx_dp.v
input [8:0]             arb1_q0_holdbar_r_a;         // To cpx_dp1 of cpx_dp.v
input [8:0]             arb1_qsel0_r_a;           // To cpx_dp1 of cpx_dp.v
input [8:0]             arb1_qsel1_r_a;           // To cpx_dp1 of cpx_dp.v
input [8:0]             arb1_shift_r_a;           // To cpx_dp1 of cpx_dp.v
input [8:0]             arb2_grant_r_a;           // To cpx_dp2 of cpx_dp.v
input [8:0]             arb2_q0_holdbar_r_a;         // To cpx_dp2 of cpx_dp.v
input [8:0]             arb2_qsel0_r_a;           // To cpx_dp2 of cpx_dp.v
input [8:0]             arb2_qsel1_r_a;           // To cpx_dp2 of cpx_dp.v
input [8:0]             arb2_shift_r_a;           // To cpx_dp2 of cpx_dp.v
input [8:0]             arb3_grant_r_a;           // To cpx_dp3 of cpx_dp.v
input [8:0]             arb3_q0_holdbar_r_a;         // To cpx_dp3 of cpx_dp.v
input [8:0]             arb3_qsel0_r_a;           // To cpx_dp3 of cpx_dp.v
input [8:0]             arb3_qsel1_r_a;           // To cpx_dp3 of cpx_dp.v
input [8:0]             arb3_shift_r_a;           // To cpx_dp3 of cpx_dp.v
input [8:0]             arb4_grant_r_a;           // To cpx_dp4 of cpx_dp.v
input [8:0]             arb4_q0_holdbar_r_a;         // To cpx_dp4 of cpx_dp.v
input [8:0]             arb4_qsel0_r_a;           // To cpx_dp4 of cpx_dp.v
input [8:0]             arb4_qsel1_r_a;           // To cpx_dp4 of cpx_dp.v
input [8:0]             arb4_shift_r_a;           // To cpx_dp4 of cpx_dp.v
input [8:0]             arb5_grant_r_a;           // To cpx_dp5 of cpx_dp.v
input [8:0]             arb5_q0_holdbar_r_a;         // To cpx_dp5 of cpx_dp.v
input [8:0]             arb5_qsel0_r_a;           // To cpx_dp5 of cpx_dp.v
input [8:0]             arb5_qsel1_r_a;           // To cpx_dp5 of cpx_dp.v
input [8:0]             arb5_shift_r_a;           // To cpx_dp5 of cpx_dp.v
input [8:0]             arb6_grant_r_a;           // To cpx_dp6 of cpx_dp.v
input [8:0]             arb6_q0_holdbar_r_a;         // To cpx_dp6 of cpx_dp.v
input [8:0]             arb6_qsel0_r_a;           // To cpx_dp6 of cpx_dp.v
input [8:0]             arb6_qsel1_r_a;           // To cpx_dp6 of cpx_dp.v
input [8:0]             arb6_shift_r_a;           // To cpx_dp6 of cpx_dp.v
input [8:0]             arb7_grant_r_a;           // To cpx_dp7 of cpx_dp.v
input [8:0]             arb7_q0_holdbar_r_a;         // To cpx_dp7 of cpx_dp.v
input [8:0]             arb7_qsel0_r_a;           // To cpx_dp7 of cpx_dp.v
input [8:0]             arb7_qsel1_r_a;           // To cpx_dp7 of cpx_dp.v
input [8:0]             arb7_shift_r_a;           // To cpx_dp7 of cpx_dp.v
input [149:0]           io_cpx_data_a;          // To cpx_dp0 of cpx_dp.v, ...
input [149:0]           scache0_cpx_data_a;     // To cpx_dp0 of cpx_dp.v, ...
input [149:0]           scache1_cpx_data_a;     // To cpx_dp0 of cpx_dp.v, ...
input [149:0]           scache2_cpx_data_a;     // To cpx_dp0 of cpx_dp.v, ...
input [149:0]           scache3_cpx_data_a;     // To cpx_dp0 of cpx_dp.v, ...
input [149:0]           scache4_cpx_data_a;     // To cpx_dp0 of cpx_dp.v, ...
input [149:0]           scache5_cpx_data_a;     // To cpx_dp0 of cpx_dp.v, ...
input [149:0]           scache6_cpx_data_a;     // To cpx_dp0 of cpx_dp.v, ...
input [149:0]           scache7_cpx_data_a;     // To cpx_dp0 of cpx_dp.v, ...
// End of automatics

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov_t;             // scan signals
input           tcu_scan_en_t ;
input           ccx_aclk_t;
input           ccx_bclk_t;
input           tcu_pce_ov_b;             // scan signals
input           tcu_scan_en_b ;
input           ccx_aclk_b;
input           ccx_bclk_b;
output          scan_out;


// slices are placed in the following order
//
//@cpx_dps4(cpx_dpsg)
//@cpx_dps0(cpx_dpsb)
//@cpx_dps5(cpx_dpsf)
//@cpx_dps1(cpx_dpsd)
//
//@cpx_dps3(cpx_dpsc)
//@cpx_dps7(cpx_dpse)
//@cpx_dps6(cpx_dpsg)
//@cpx_dps2(cpx_dpsa)

//
// cpx_dps AUTO_TEMPLATE
// (
// .cpx_spc_data_x_(cpx_spc@_data_x_[149:0]),
// .arb_grant_l_a  (arb@_grant_l_a[8:0]),
// .arb_q0_holdbar_l_a(arb@_q0_holdbar_l_a[8:0]),
// .arb_qsel0_l_a  (arb@_qsel0_l_a[8:0]),
// .arb_qsel1_l_a  (arb@_qsel1_l_a[8:0]),
// .arb_shift_l_a  (arb@_shift_l_a[8:0]),
// .arb_grant_r_a  (arb@_grant_r_a[8:0]),
// .arb_q0_holdbar_r_a(arb@_q0_holdbar_r_a[8:0]),
// .arb_qsel0_r_a  (arb@_qsel0_r_a[8:0]),
// .arb_qsel1_r_a  (arb@_qsel1_r_a[8:0]),
// .arb_shift_r_a  (arb@_shift_r_a[8:0]),
// );


// DATAPATH ORGANISATION(cpx_dps0)
//      io    scache0 scache2 scache1 scache3  scache7  scache5  scache6  scache4
//       |        |      |       |       |        |        |        |       |     
//       v        v      v       v       v        v        v        v       v    
//      mac8->  mac0 -> mac1 <- mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     cl      br      br       br       br       br      bl    
//                      |                                          
//       -buf------------
//      |                                                        
//      v                                                        
//    to spc0


cpx_dpsb cpx_dps0 (
                   /*AUTOINST*/
                   // Outputs
                   .cpx_spc_data_x_      (cpx_spc0_data_x_[149:0]), // Templated
                   // Inputs
                   .arb_grant_l_a         (arb0_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_l_a    (arb0_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_l_a         (arb0_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_l_a         (arb0_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_l_a         (arb0_shift_l_a[8:0]),     // Templated
                   .arb_grant_r_a         (arb0_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_r_a    (arb0_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_r_a         (arb0_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_r_a         (arb0_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_r_a         (arb0_shift_r_a[8:0]),     // Templated
                   .io_cpx_data_a        (io_cpx_data_a[149:0]),
                   .scache0_cpx_data_a   (scache0_cpx_data_a[149:0]),
                   .scache1_cpx_data_a   (scache1_cpx_data_a[149:0]),
                   .scache2_cpx_data_a   (scache2_cpx_data_a[149:0]),
                   .scache3_cpx_data_a   (scache3_cpx_data_a[149:0]),
                   .scache4_cpx_data_a   (scache4_cpx_data_a[149:0]),
                   .scache5_cpx_data_a   (scache5_cpx_data_a[149:0]),
                   .scache6_cpx_data_a   (scache6_cpx_data_a[149:0]),
                   .scache7_cpx_data_a   (scache7_cpx_data_a[149:0]),
                   .scan_in(cpx_dps0_scanin),
                   .scan_out(cpx_dps0_scanout),
                   .l2clk                (l2clk),
                   .ccx_aclk                (ccx_aclk_t),
                   .ccx_bclk                (ccx_bclk_t),
                   .tcu_scan_en             (tcu_scan_en_t),
                   .tcu_pce_ov              (tcu_pce_ov_t)
                   );


// DATAPATH ORGANISATION(cpx_dps1)
//
//      io    scache0 scache2 scache1 scache3  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  ->mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      cl       br       br       br      bl    
//                                      |                                          
//       --------buf--------------------                                         
//      |                                                        
//      v                                                        
//    to spc1

cpx_dpsd cpx_dps1 (
                   /*AUTOINST*/
                   // Outputs
                   .cpx_spc_data_x_      (cpx_spc1_data_x_[149:0]), // Templated
                   // Inputs
                   .arb_grant_l_a         (arb1_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_l_a    (arb1_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_l_a         (arb1_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_l_a         (arb1_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_l_a         (arb1_shift_l_a[8:0]),     // Templated
                   .arb_grant_r_a         (arb1_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_r_a    (arb1_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_r_a         (arb1_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_r_a         (arb1_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_r_a         (arb1_shift_r_a[8:0]),     // Templated
                   .io_cpx_data_a        (io_cpx_data_a[149:0]),
                   .scache0_cpx_data_a   (scache0_cpx_data_a[149:0]),
                   .scache1_cpx_data_a   (scache1_cpx_data_a[149:0]),
                   .scache2_cpx_data_a   (scache2_cpx_data_a[149:0]),
                   .scache3_cpx_data_a   (scache3_cpx_data_a[149:0]),
                   .scache4_cpx_data_a   (scache4_cpx_data_a[149:0]),
                   .scache5_cpx_data_a   (scache5_cpx_data_a[149:0]),
                   .scache6_cpx_data_a   (scache6_cpx_data_a[149:0]),
                   .scache7_cpx_data_a   (scache7_cpx_data_a[149:0]),
                   .scan_in(cpx_dps1_scanin),
                   .scan_out(cpx_dps1_scanout),
                   .l2clk                (l2clk),
                   .ccx_aclk                (ccx_aclk_t),
                   .ccx_bclk                (ccx_bclk_t),
                   .tcu_scan_en             (tcu_scan_en_t),
                   .tcu_pce_ov              (tcu_pce_ov_t)
                   );

// DATAPATH ORGANISATION(cpx_dps2)
//
//      io    scache0 scache2 scache1 scache3  scache7  scache5  scache6  scache4
//       |        |      |       |       |        |        |        |       |     
//       v        v      v       v       v        v        v        v       v    
//      mac8->  mac0 -> mac1 <- mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      bl       cl     br      br      br       br       br       br      ar    
//               |                                          
//       --buf---
//      |                                                        
//      v                                                        
//    to spc2

cpx_dpsa cpx_dps2 (
                   /*AUTOINST*/
                  // Outputs
                   .cpx_spc_data_x_      (cpx_spc2_data_x_[149:0]), // Templated
                   // Inputs
                   .arb_grant_l_a         (arb2_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_l_a    (arb2_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_l_a         (arb2_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_l_a         (arb2_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_l_a         (arb2_shift_l_a[8:0]),     // Templated
                   .arb_grant_r_a         (arb2_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_r_a    (arb2_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_r_a         (arb2_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_r_a         (arb2_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_r_a         (arb2_shift_r_a[8:0]),     // Templated
                   .io_cpx_data_a        (io_cpx_data_a[149:0]),
                   .scache0_cpx_data_a   (scache0_cpx_data_a[149:0]),
                   .scache1_cpx_data_a   (scache1_cpx_data_a[149:0]),
                   .scache2_cpx_data_a   (scache2_cpx_data_a[149:0]),
                   .scache3_cpx_data_a   (scache3_cpx_data_a[149:0]),
                   .scache4_cpx_data_a   (scache4_cpx_data_a[149:0]),
                   .scache5_cpx_data_a   (scache5_cpx_data_a[149:0]),
                   .scache6_cpx_data_a   (scache6_cpx_data_a[149:0]),
                   .scache7_cpx_data_a   (scache7_cpx_data_a[149:0]),
                   .scan_in(cpx_dps2_scanin),
                   .scan_out(cpx_dps2_scanout),
                   .l2clk                (l2clk),
                   .ccx_aclk                (ccx_aclk_b),
                   .ccx_bclk                (ccx_bclk_b),
                   .tcu_scan_en             (tcu_scan_en_b),
                   .tcu_pce_ov              (tcu_pce_ov_b)
);

// DATAPATH ORGANISATION(cpx_dps3)
//
//      io    scache0 scache2 scache1 scache3  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  ->mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      cl      br       br       br       br      ar
//                              |                                          
//       --------buf------------                                         
//      |                                                        
//      v                                                        
//    to spc3

cpx_dpsc cpx_dps3 (
                   /*AUTOINST*/
                   // Outputs
                   .cpx_spc_data_x_      (cpx_spc3_data_x_[149:0]), // Templated
                   // Inputs
                   .arb_grant_l_a         (arb3_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_l_a    (arb3_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_l_a         (arb3_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_l_a         (arb3_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_l_a         (arb3_shift_l_a[8:0]),     // Templated
                   .arb_grant_r_a         (arb3_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_r_a    (arb3_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_r_a         (arb3_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_r_a         (arb3_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_r_a         (arb3_shift_r_a[8:0]),     // Templated
                   .io_cpx_data_a        (io_cpx_data_a[149:0]),
                   .scache0_cpx_data_a   (scache0_cpx_data_a[149:0]),
                   .scache1_cpx_data_a   (scache1_cpx_data_a[149:0]),
                   .scache2_cpx_data_a   (scache2_cpx_data_a[149:0]),
                   .scache3_cpx_data_a   (scache3_cpx_data_a[149:0]),
                   .scache4_cpx_data_a   (scache4_cpx_data_a[149:0]),
                   .scache5_cpx_data_a   (scache5_cpx_data_a[149:0]),
                   .scache6_cpx_data_a   (scache6_cpx_data_a[149:0]),
                   .scache7_cpx_data_a   (scache7_cpx_data_a[149:0]),
                   .scan_in(cpx_dps3_scanin),
                   .scan_out(cpx_dps3_scanout),
                   .l2clk                (l2clk),
                   .ccx_aclk                (ccx_aclk_b),
                   .ccx_bclk                (ccx_bclk_b),
                   .tcu_scan_en             (tcu_scan_en_b),
                   .tcu_pce_ov              (tcu_pce_ov_b)
                   );

// DATAPATH ORGANISATION(cpx_dps4)
//
//      io    scache0 scache2 scache1 scache3  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  ->mac2 -> mac3 ->  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      bl       bl       bl       cr     br      
//                                                                  |                                                 
//                                                                 buf         
//                                                                  |               
//                                                                  v               
//                                                               to spc4       

cpx_dpsg cpx_dps4 (
                   /*AUTOINST*/
                   // Outputs
                   .cpx_spc_data_x_      (cpx_spc4_data_x_[149:0]), // Templated
                   // Inputs
                   .arb_grant_l_a         (arb4_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_l_a    (arb4_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_l_a         (arb4_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_l_a         (arb4_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_l_a         (arb4_shift_l_a[8:0]),     // Templated
                   .arb_grant_r_a         (arb4_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_r_a    (arb4_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_r_a         (arb4_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_r_a         (arb4_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_r_a         (arb4_shift_r_a[8:0]),     // Templated
                   .io_cpx_data_a        (io_cpx_data_a[149:0]),
                   .scache0_cpx_data_a   (scache0_cpx_data_a[149:0]),
                   .scache1_cpx_data_a   (scache1_cpx_data_a[149:0]),
                   .scache2_cpx_data_a   (scache2_cpx_data_a[149:0]),
                   .scache3_cpx_data_a   (scache3_cpx_data_a[149:0]),
                   .scache4_cpx_data_a   (scache4_cpx_data_a[149:0]),
                   .scache5_cpx_data_a   (scache5_cpx_data_a[149:0]),
                   .scache6_cpx_data_a   (scache6_cpx_data_a[149:0]),
                   .scache7_cpx_data_a   (scache7_cpx_data_a[149:0]),
                   .scan_in(cpx_dps4_scanin),
                   .scan_out(cpx_dps4_scanout),
                   .l2clk                (l2clk),
                   .ccx_aclk                (ccx_aclk_t),
                   .ccx_bclk                (ccx_bclk_t),
                   .tcu_scan_en             (tcu_scan_en_t),
                   .tcu_pce_ov              (tcu_pce_ov_t)
);

// DATAPATH ORGANISATION(cpx_dps5)
//
//      io    scache0 scache2 scache1 scache3  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  ->mac2 -> mac3 ->  mac4  -> mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      bl       bl       cr       br      bl    
//                                                         |                       
//                                                        buf   
//                                                         |                                     
//                                                         v     
//                                                       to spc5


cpx_dpsf cpx_dps5 (
                   /*AUTOINST*/
                   // Outputs
                   .cpx_spc_data_x_      (cpx_spc5_data_x_[149:0]), // Templated
                  // Inputs
                   .arb_grant_l_a         (arb5_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_l_a    (arb5_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_l_a         (arb5_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_l_a         (arb5_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_l_a         (arb5_shift_l_a[8:0]),     // Templated
                   .arb_grant_r_a         (arb5_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_r_a    (arb5_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_r_a         (arb5_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_r_a         (arb5_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_r_a         (arb5_shift_r_a[8:0]),     // Templated
                   .io_cpx_data_a        (io_cpx_data_a[149:0]),
                   .scache0_cpx_data_a   (scache0_cpx_data_a[149:0]),
                   .scache1_cpx_data_a   (scache1_cpx_data_a[149:0]),
                   .scache2_cpx_data_a   (scache2_cpx_data_a[149:0]),
                   .scache3_cpx_data_a   (scache3_cpx_data_a[149:0]),
                   .scache4_cpx_data_a   (scache4_cpx_data_a[149:0]),
                   .scache5_cpx_data_a   (scache5_cpx_data_a[149:0]),
                   .scache6_cpx_data_a   (scache6_cpx_data_a[149:0]),
                   .scache7_cpx_data_a   (scache7_cpx_data_a[149:0]),
                   .scan_in(cpx_dps5_scanin),
                   .scan_out(cpx_dps5_scanout),
                   .l2clk                (l2clk),
                   .ccx_aclk                (ccx_aclk_t),
                   .ccx_bclk                (ccx_bclk_t),
                   .tcu_scan_en             (tcu_scan_en_t),
                   .tcu_pce_ov              (tcu_pce_ov_t)
                   );

// DATAPATH ORGANISATION(cpx_dps6)
//
//      io    scache0 scache2 scache1 scache3  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  ->mac2 -> mac3 ->  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      bl       bl       bl       cr      br
//                                                                 |                                          
//                                                             -buf--
//                                                             |        
//                                                             v        
//                                                           to spc6


cpx_dpsg cpx_dps6 (
                   /*AUTOINST*/
                   // Outputs
                   .cpx_spc_data_x_      (cpx_spc6_data_x_[149:0]), // Templated
                   // Inputs
                   .arb_grant_l_a         (arb6_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_l_a    (arb6_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_l_a         (arb6_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_l_a         (arb6_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_l_a         (arb6_shift_l_a[8:0]),     // Templated
                   .arb_grant_r_a         (arb6_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_r_a    (arb6_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_r_a         (arb6_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_r_a         (arb6_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_r_a         (arb6_shift_r_a[8:0]),     // Templated
                   .io_cpx_data_a        (io_cpx_data_a[149:0]),
                   .scache0_cpx_data_a   (scache0_cpx_data_a[149:0]),
                   .scache1_cpx_data_a   (scache1_cpx_data_a[149:0]),
                   .scache2_cpx_data_a   (scache2_cpx_data_a[149:0]),
                   .scache3_cpx_data_a   (scache3_cpx_data_a[149:0]),
                   .scache4_cpx_data_a   (scache4_cpx_data_a[149:0]),
                   .scache5_cpx_data_a   (scache5_cpx_data_a[149:0]),
                   .scache6_cpx_data_a   (scache6_cpx_data_a[149:0]),
                   .scache7_cpx_data_a   (scache7_cpx_data_a[149:0]),
                   .scan_in(cpx_dps6_scanin),
                   .scan_out(cpx_dps6_scanout),
                   .l2clk                (l2clk),
                   .ccx_aclk                (ccx_aclk_b),
                   .ccx_bclk                (ccx_bclk_b),
                   .tcu_scan_en             (tcu_scan_en_b),
                   .tcu_pce_ov              (tcu_pce_ov_b)
);

// DATAPATH ORGANISATION(cpx_dps7)
//
//      io    scache0 scache2 scache1 scache3  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  ->mac2 -> mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      bl       cr       br       br      bl    
//                                               |                                          
//                                              buf
//                                               |                                                        
//                                               v                        
//                                             to spc7

cpx_dpse cpx_dps7 (
                   /*AUTOINST*/
                   // Outputs
                   .cpx_spc_data_x_      (cpx_spc7_data_x_[149:0]), // Templated
                  // Inputs
                   .arb_grant_l_a         (arb7_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_l_a    (arb7_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_l_a         (arb7_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_l_a         (arb7_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_l_a         (arb7_shift_l_a[8:0]),     // Templated
                   .arb_grant_r_a         (arb7_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_r_a    (arb7_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_r_a         (arb7_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_r_a         (arb7_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_r_a         (arb7_shift_r_a[8:0]),     // Templated
                   .io_cpx_data_a        (io_cpx_data_a[149:0]),
                   .scache0_cpx_data_a   (scache0_cpx_data_a[149:0]),
                   .scache1_cpx_data_a   (scache1_cpx_data_a[149:0]),
                   .scache2_cpx_data_a   (scache2_cpx_data_a[149:0]),
                   .scache3_cpx_data_a   (scache3_cpx_data_a[149:0]),
                   .scache4_cpx_data_a   (scache4_cpx_data_a[149:0]),
                   .scache5_cpx_data_a   (scache5_cpx_data_a[149:0]),
                   .scache6_cpx_data_a   (scache6_cpx_data_a[149:0]),
                   .scache7_cpx_data_a   (scache7_cpx_data_a[149:0]),
                   .scan_in(cpx_dps7_scanin),
                   .scan_out(cpx_dps7_scanout),
                   .l2clk                (l2clk),
                   .ccx_aclk                (ccx_aclk_b),
                   .ccx_bclk                (ccx_bclk_b),
                   .tcu_scan_en             (tcu_scan_en_b),
                   .tcu_pce_ov              (tcu_pce_ov_b)
                   );

// fixscan start:
assign cpx_dps4_scanin           = scan_in                  ;
assign cpx_dps0_scanin           = cpx_dps4_scanout         ;
assign cpx_dps5_scanin           = cpx_dps0_scanout         ;
assign cpx_dps1_scanin           = cpx_dps5_scanout         ;
assign cpx_dps3_scanin           = cpx_dps1_scanout         ;
assign cpx_dps7_scanin           = cpx_dps3_scanout         ;
assign cpx_dps6_scanin           = cpx_dps7_scanout         ;
assign cpx_dps2_scanin           = cpx_dps6_scanout         ;
assign scan_out                  = cpx_dps2_scanout         ;
// fixscan end:
endmodule 


// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module cpx_dpa_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpa_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpa_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_dpa_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_dpa_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpa_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpa_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpa_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[49:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[49:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[149:100]),
// .din1	(data_crit_x_[149:100]),
// .din2	(data_ncrit_x_[149:100]),
// .dout	(data_out_x[149:100])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[99:50]),
// .din1	(data_crit_x_[99:50]),
// .din2	(data_ncrit_x_[99:50]),
// .dout	(data_out_x[99:50])
//);
//
//nand_macro i_nand_data_crit_0 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[49:0]),
// .din1	(data_crit_x_[49:0]),
// .din2	(data_ncrit_x_[49:0]),
// .dout	(data_out_x[49:0])
//);
//
//inv_macro i_inv_data_out_2 (width=50, stack=50c) 
//(
// .din	(data_out_x[149:100]),
// .dout	(data_out_x_[149:100])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[99:50]),
// .dout	(data_out_x_[99:50])
// );
//
//inv_macro i_inv_data_out_0 (width=50, stack=50c) 
//(
// .din	(data_out_x[49:0]),
// .dout	(data_out_x_[49:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule


//
//   ccx macro
//
//


module cpx_dpa_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);

endmodule
`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_dpa(cpx_spc0_data_x_, cpx_spc1_data_x_, cpx_spc2_data_x_, 
	cpx_spc3_data_x_, cpx_spc4_data_x_, cpx_spc5_data_x_, cpx_spc6_data_x_, 
	cpx_spc7_data_x_, arb0_grant_l_a, arb0_q0_holdbar_l_a, arb0_qsel0_l_a, 
	arb0_qsel1_l_a, arb0_shift_l_a, arb1_grant_l_a, arb1_q0_holdbar_l_a, 
	arb1_qsel0_l_a, arb1_qsel1_l_a, arb1_shift_l_a, arb2_grant_l_a, 
	arb2_q0_holdbar_l_a, arb2_qsel0_l_a, arb2_qsel1_l_a, arb2_shift_l_a, 
	arb3_grant_l_a, arb3_q0_holdbar_l_a, arb3_qsel0_l_a, arb3_qsel1_l_a, 
	arb3_shift_l_a, arb4_grant_l_a, arb4_q0_holdbar_l_a, arb4_qsel0_l_a, 
	arb4_qsel1_l_a, arb4_shift_l_a, arb5_grant_l_a, arb5_q0_holdbar_l_a, 
	arb5_qsel0_l_a, arb5_qsel1_l_a, arb5_shift_l_a, arb6_grant_l_a, 
	arb6_q0_holdbar_l_a, arb6_qsel0_l_a, arb6_qsel1_l_a, arb6_shift_l_a, 
	arb7_grant_l_a, arb7_q0_holdbar_l_a, arb7_qsel0_l_a, arb7_qsel1_l_a, 
	arb7_shift_l_a, arb0_grant_r_a, arb0_q0_holdbar_r_a, arb0_qsel0_r_a, 
	arb0_qsel1_r_a, arb0_shift_r_a, arb1_grant_r_a, arb1_q0_holdbar_r_a, 
	arb1_qsel0_r_a, arb1_qsel1_r_a, arb1_shift_r_a, arb2_grant_r_a, 
	arb2_q0_holdbar_r_a, arb2_qsel0_r_a, arb2_qsel1_r_a, arb2_shift_r_a, 
	arb3_grant_r_a, arb3_q0_holdbar_r_a, arb3_qsel0_r_a, arb3_qsel1_r_a, 
	arb3_shift_r_a, arb4_grant_r_a, arb4_q0_holdbar_r_a, arb4_qsel0_r_a, 
	arb4_qsel1_r_a, arb4_shift_r_a, arb5_grant_r_a, arb5_q0_holdbar_r_a, 
	arb5_qsel0_r_a, arb5_qsel1_r_a, arb5_shift_r_a, arb6_grant_r_a, 
	arb6_q0_holdbar_r_a, arb6_qsel0_r_a, arb6_qsel1_r_a, arb6_shift_r_a, 
	arb7_grant_r_a, arb7_q0_holdbar_r_a, arb7_qsel0_r_a, arb7_qsel1_r_a, 
	arb7_shift_r_a, io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a, 
	scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a, 
	scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, l2clk, 
	scan_in, tcu_pce_ov_t, tcu_scan_en_t, ccx_aclk_t, ccx_bclk_t, 
	tcu_pce_ov_b, tcu_scan_en_b, ccx_aclk_b, ccx_bclk_b, scan_out);

	output	[149:0]		cpx_spc0_data_x_;
	output	[149:0]		cpx_spc1_data_x_;
	output	[149:0]		cpx_spc2_data_x_;
	output	[149:0]		cpx_spc3_data_x_;
	output	[149:0]		cpx_spc4_data_x_;
	output	[149:0]		cpx_spc5_data_x_;
	output	[149:0]		cpx_spc6_data_x_;
	output	[149:0]		cpx_spc7_data_x_;
	input	[8:0]		arb0_grant_l_a;
	input	[8:0]		arb0_q0_holdbar_l_a;
	input	[8:0]		arb0_qsel0_l_a;
	input	[8:0]		arb0_qsel1_l_a;
	input	[8:0]		arb0_shift_l_a;
	input	[8:0]		arb1_grant_l_a;
	input	[8:0]		arb1_q0_holdbar_l_a;
	input	[8:0]		arb1_qsel0_l_a;
	input	[8:0]		arb1_qsel1_l_a;
	input	[8:0]		arb1_shift_l_a;
	input	[8:0]		arb2_grant_l_a;
	input	[8:0]		arb2_q0_holdbar_l_a;
	input	[8:0]		arb2_qsel0_l_a;
	input	[8:0]		arb2_qsel1_l_a;
	input	[8:0]		arb2_shift_l_a;
	input	[8:0]		arb3_grant_l_a;
	input	[8:0]		arb3_q0_holdbar_l_a;
	input	[8:0]		arb3_qsel0_l_a;
	input	[8:0]		arb3_qsel1_l_a;
	input	[8:0]		arb3_shift_l_a;
	input	[8:0]		arb4_grant_l_a;
	input	[8:0]		arb4_q0_holdbar_l_a;
	input	[8:0]		arb4_qsel0_l_a;
	input	[8:0]		arb4_qsel1_l_a;
	input	[8:0]		arb4_shift_l_a;
	input	[8:0]		arb5_grant_l_a;
	input	[8:0]		arb5_q0_holdbar_l_a;
	input	[8:0]		arb5_qsel0_l_a;
	input	[8:0]		arb5_qsel1_l_a;
	input	[8:0]		arb5_shift_l_a;
	input	[8:0]		arb6_grant_l_a;
	input	[8:0]		arb6_q0_holdbar_l_a;
	input	[8:0]		arb6_qsel0_l_a;
	input	[8:0]		arb6_qsel1_l_a;
	input	[8:0]		arb6_shift_l_a;
	input	[8:0]		arb7_grant_l_a;
	input	[8:0]		arb7_q0_holdbar_l_a;
	input	[8:0]		arb7_qsel0_l_a;
	input	[8:0]		arb7_qsel1_l_a;
	input	[8:0]		arb7_shift_l_a;
	input	[8:0]		arb0_grant_r_a;
	input	[8:0]		arb0_q0_holdbar_r_a;
	input	[8:0]		arb0_qsel0_r_a;
	input	[8:0]		arb0_qsel1_r_a;
	input	[8:0]		arb0_shift_r_a;
	input	[8:0]		arb1_grant_r_a;
	input	[8:0]		arb1_q0_holdbar_r_a;
	input	[8:0]		arb1_qsel0_r_a;
	input	[8:0]		arb1_qsel1_r_a;
	input	[8:0]		arb1_shift_r_a;
	input	[8:0]		arb2_grant_r_a;
	input	[8:0]		arb2_q0_holdbar_r_a;
	input	[8:0]		arb2_qsel0_r_a;
	input	[8:0]		arb2_qsel1_r_a;
	input	[8:0]		arb2_shift_r_a;
	input	[8:0]		arb3_grant_r_a;
	input	[8:0]		arb3_q0_holdbar_r_a;
	input	[8:0]		arb3_qsel0_r_a;
	input	[8:0]		arb3_qsel1_r_a;
	input	[8:0]		arb3_shift_r_a;
	input	[8:0]		arb4_grant_r_a;
	input	[8:0]		arb4_q0_holdbar_r_a;
	input	[8:0]		arb4_qsel0_r_a;
	input	[8:0]		arb4_qsel1_r_a;
	input	[8:0]		arb4_shift_r_a;
	input	[8:0]		arb5_grant_r_a;
	input	[8:0]		arb5_q0_holdbar_r_a;
	input	[8:0]		arb5_qsel0_r_a;
	input	[8:0]		arb5_qsel1_r_a;
	input	[8:0]		arb5_shift_r_a;
	input	[8:0]		arb6_grant_r_a;
	input	[8:0]		arb6_q0_holdbar_r_a;
	input	[8:0]		arb6_qsel0_r_a;
	input	[8:0]		arb6_qsel1_r_a;
	input	[8:0]		arb6_shift_r_a;
	input	[8:0]		arb7_grant_r_a;
	input	[8:0]		arb7_q0_holdbar_r_a;
	input	[8:0]		arb7_qsel0_r_a;
	input	[8:0]		arb7_qsel1_r_a;
	input	[8:0]		arb7_shift_r_a;
	input	[149:0]		io_cpx_data_a;
	input	[149:0]		scache0_cpx_data_a;
	input	[149:0]		scache1_cpx_data_a;
	input	[149:0]		scache2_cpx_data_a;
	input	[149:0]		scache3_cpx_data_a;
	input	[149:0]		scache4_cpx_data_a;
	input	[149:0]		scache5_cpx_data_a;
	input	[149:0]		scache6_cpx_data_a;
	input	[149:0]		scache7_cpx_data_a;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov_t;
	input			tcu_scan_en_t;
	input			ccx_aclk_t;
	input			ccx_bclk_t;
	input			tcu_pce_ov_b;
	input			tcu_scan_en_b;
	input			ccx_aclk_b;
	input			ccx_bclk_b;
	output			scan_out;

	wire			cpx_dps0_scanin;
	wire			cpx_dps0_scanout;
	wire			cpx_dps1_scanin;
	wire			cpx_dps1_scanout;
	wire			cpx_dps2_scanin;
	wire			cpx_dps2_scanout;
	wire			cpx_dps3_scanin;
	wire			cpx_dps3_scanout;
	wire			cpx_dps4_scanin;
	wire			cpx_dps4_scanout;
	wire			cpx_dps5_scanin;
	wire			cpx_dps5_scanout;
	wire			cpx_dps6_scanin;
	wire			cpx_dps6_scanout;
	wire			cpx_dps7_scanin;
	wire			cpx_dps7_scanout;

	assign cpx_dps4_scanin = scan_in;
	assign cpx_dps0_scanin = cpx_dps4_scanout;
	assign cpx_dps5_scanin = cpx_dps0_scanout;
	assign cpx_dps1_scanin = cpx_dps5_scanout;
	assign cpx_dps3_scanin = cpx_dps1_scanout;
	assign cpx_dps7_scanin = cpx_dps3_scanout;
	assign cpx_dps6_scanin = cpx_dps7_scanout;
	assign cpx_dps2_scanin = cpx_dps6_scanout;
	assign scan_out = cpx_dps2_scanout;

	cpx_dpsb cpx_dps0(
		.cpx_spc_data_x_		(cpx_spc0_data_x_[149:0]), 
		.arb_grant_l_a			(arb0_grant_l_a[8:0]), 
		.arb_q0_holdbar_l_a		(arb0_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_l_a			(arb0_qsel0_l_a[8:0]), 
		.arb_qsel1_l_a			(arb0_qsel1_l_a[8:0]), 
		.arb_shift_l_a			(arb0_shift_l_a[8:0]), 
		.arb_grant_r_a			(arb0_grant_r_a[8:0]), 
		.arb_q0_holdbar_r_a		(arb0_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_r_a			(arb0_qsel0_r_a[8:0]), 
		.arb_qsel1_r_a			(arb0_qsel1_r_a[8:0]), 
		.arb_shift_r_a			(arb0_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(scache0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(scache1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(scache2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(scache3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(scache4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(scache5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(scache6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(scache7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dps0_scanin), 
		.scan_out			(cpx_dps0_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
	cpx_dpsd cpx_dps1(
		.cpx_spc_data_x_		(cpx_spc1_data_x_[149:0]), 
		.arb_grant_l_a			(arb1_grant_l_a[8:0]), 
		.arb_q0_holdbar_l_a		(arb1_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_l_a			(arb1_qsel0_l_a[8:0]), 
		.arb_qsel1_l_a			(arb1_qsel1_l_a[8:0]), 
		.arb_shift_l_a			(arb1_shift_l_a[8:0]), 
		.arb_grant_r_a			(arb1_grant_r_a[8:0]), 
		.arb_q0_holdbar_r_a		(arb1_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_r_a			(arb1_qsel0_r_a[8:0]), 
		.arb_qsel1_r_a			(arb1_qsel1_r_a[8:0]), 
		.arb_shift_r_a			(arb1_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(scache0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(scache1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(scache2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(scache3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(scache4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(scache5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(scache6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(scache7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dps1_scanin), 
		.scan_out			(cpx_dps1_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
	cpx_dpsa cpx_dps2(
		.cpx_spc_data_x_		(cpx_spc2_data_x_[149:0]), 
		.arb_grant_l_a			(arb2_grant_l_a[8:0]), 
		.arb_q0_holdbar_l_a		(arb2_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_l_a			(arb2_qsel0_l_a[8:0]), 
		.arb_qsel1_l_a			(arb2_qsel1_l_a[8:0]), 
		.arb_shift_l_a			(arb2_shift_l_a[8:0]), 
		.arb_grant_r_a			(arb2_grant_r_a[8:0]), 
		.arb_q0_holdbar_r_a		(arb2_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_r_a			(arb2_qsel0_r_a[8:0]), 
		.arb_qsel1_r_a			(arb2_qsel1_r_a[8:0]), 
		.arb_shift_r_a			(arb2_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(scache0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(scache1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(scache2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(scache3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(scache4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(scache5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(scache6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(scache7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dps2_scanin), 
		.scan_out			(cpx_dps2_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_b), 
		.ccx_bclk			(ccx_bclk_b), 
		.tcu_scan_en			(tcu_scan_en_b), 
		.tcu_pce_ov			(tcu_pce_ov_b));
	cpx_dpsc cpx_dps3(
		.cpx_spc_data_x_		(cpx_spc3_data_x_[149:0]), 
		.arb_grant_l_a			(arb3_grant_l_a[8:0]), 
		.arb_q0_holdbar_l_a		(arb3_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_l_a			(arb3_qsel0_l_a[8:0]), 
		.arb_qsel1_l_a			(arb3_qsel1_l_a[8:0]), 
		.arb_shift_l_a			(arb3_shift_l_a[8:0]), 
		.arb_grant_r_a			(arb3_grant_r_a[8:0]), 
		.arb_q0_holdbar_r_a		(arb3_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_r_a			(arb3_qsel0_r_a[8:0]), 
		.arb_qsel1_r_a			(arb3_qsel1_r_a[8:0]), 
		.arb_shift_r_a			(arb3_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(scache0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(scache1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(scache2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(scache3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(scache4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(scache5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(scache6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(scache7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dps3_scanin), 
		.scan_out			(cpx_dps3_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_b), 
		.ccx_bclk			(ccx_bclk_b), 
		.tcu_scan_en			(tcu_scan_en_b), 
		.tcu_pce_ov			(tcu_pce_ov_b));
	cpx_dpsg cpx_dps4(
		.cpx_spc_data_x_		(cpx_spc4_data_x_[149:0]), 
		.arb_grant_l_a			(arb4_grant_l_a[8:0]), 
		.arb_q0_holdbar_l_a		(arb4_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_l_a			(arb4_qsel0_l_a[8:0]), 
		.arb_qsel1_l_a			(arb4_qsel1_l_a[8:0]), 
		.arb_shift_l_a			(arb4_shift_l_a[8:0]), 
		.arb_grant_r_a			(arb4_grant_r_a[8:0]), 
		.arb_q0_holdbar_r_a		(arb4_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_r_a			(arb4_qsel0_r_a[8:0]), 
		.arb_qsel1_r_a			(arb4_qsel1_r_a[8:0]), 
		.arb_shift_r_a			(arb4_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(scache0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(scache1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(scache2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(scache3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(scache4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(scache5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(scache6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(scache7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dps4_scanin), 
		.scan_out			(cpx_dps4_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
	cpx_dpsf cpx_dps5(
		.cpx_spc_data_x_		(cpx_spc5_data_x_[149:0]), 
		.arb_grant_l_a			(arb5_grant_l_a[8:0]), 
		.arb_q0_holdbar_l_a		(arb5_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_l_a			(arb5_qsel0_l_a[8:0]), 
		.arb_qsel1_l_a			(arb5_qsel1_l_a[8:0]), 
		.arb_shift_l_a			(arb5_shift_l_a[8:0]), 
		.arb_grant_r_a			(arb5_grant_r_a[8:0]), 
		.arb_q0_holdbar_r_a		(arb5_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_r_a			(arb5_qsel0_r_a[8:0]), 
		.arb_qsel1_r_a			(arb5_qsel1_r_a[8:0]), 
		.arb_shift_r_a			(arb5_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(scache0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(scache1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(scache2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(scache3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(scache4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(scache5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(scache6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(scache7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dps5_scanin), 
		.scan_out			(cpx_dps5_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
	cpx_dpsg cpx_dps6(
		.cpx_spc_data_x_		(cpx_spc6_data_x_[149:0]), 
		.arb_grant_l_a			(arb6_grant_l_a[8:0]), 
		.arb_q0_holdbar_l_a		(arb6_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_l_a			(arb6_qsel0_l_a[8:0]), 
		.arb_qsel1_l_a			(arb6_qsel1_l_a[8:0]), 
		.arb_shift_l_a			(arb6_shift_l_a[8:0]), 
		.arb_grant_r_a			(arb6_grant_r_a[8:0]), 
		.arb_q0_holdbar_r_a		(arb6_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_r_a			(arb6_qsel0_r_a[8:0]), 
		.arb_qsel1_r_a			(arb6_qsel1_r_a[8:0]), 
		.arb_shift_r_a			(arb6_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(scache0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(scache1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(scache2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(scache3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(scache4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(scache5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(scache6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(scache7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dps6_scanin), 
		.scan_out			(cpx_dps6_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_b), 
		.ccx_bclk			(ccx_bclk_b), 
		.tcu_scan_en			(tcu_scan_en_b), 
		.tcu_pce_ov			(tcu_pce_ov_b));
	cpx_dpse cpx_dps7(
		.cpx_spc_data_x_		(cpx_spc7_data_x_[149:0]), 
		.arb_grant_l_a			(arb7_grant_l_a[8:0]), 
		.arb_q0_holdbar_l_a		(arb7_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_l_a			(arb7_qsel0_l_a[8:0]), 
		.arb_qsel1_l_a			(arb7_qsel1_l_a[8:0]), 
		.arb_shift_l_a			(arb7_shift_l_a[8:0]), 
		.arb_grant_r_a			(arb7_grant_r_a[8:0]), 
		.arb_q0_holdbar_r_a		(arb7_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_r_a			(arb7_qsel0_r_a[8:0]), 
		.arb_qsel1_r_a			(arb7_qsel1_r_a[8:0]), 
		.arb_shift_r_a			(arb7_shift_r_a[8:0]), 
		.io_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scache0_cpx_data_a		(scache0_cpx_data_a[149:0]), 
		.scache1_cpx_data_a		(scache1_cpx_data_a[149:0]), 
		.scache2_cpx_data_a		(scache2_cpx_data_a[149:0]), 
		.scache3_cpx_data_a		(scache3_cpx_data_a[149:0]), 
		.scache4_cpx_data_a		(scache4_cpx_data_a[149:0]), 
		.scache5_cpx_data_a		(scache5_cpx_data_a[149:0]), 
		.scache6_cpx_data_a		(scache6_cpx_data_a[149:0]), 
		.scache7_cpx_data_a		(scache7_cpx_data_a[149:0]), 
		.scan_in			(cpx_dps7_scanin), 
		.scan_out			(cpx_dps7_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_b), 
		.ccx_bclk			(ccx_bclk_b), 
		.tcu_scan_en			(tcu_scan_en_b), 
		.tcu_pce_ov			(tcu_pce_ov_b));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_dpsa.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_dpsa (
  cpx_spc_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  io_cpx_data_a, 
  scache0_cpx_data_a, 
  scache1_cpx_data_a, 
  scache2_cpx_data_a, 
  scache3_cpx_data_a, 
  scache4_cpx_data_a, 
  scache5_cpx_data_a, 
  scache6_cpx_data_a, 
  scache7_cpx_data_a, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [149:0] all_ones;
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:5] arb_grant_r_a_rep;
wire [7:5] arb_q0_holdbar_r_a_rep;
wire [7:5] arb_qsel0_r_a_rep;
wire [7:5] arb_qsel1_r_a_rep;
wire [7:5] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [149:0] col8_data_x_;
wire tcu_scan_en_out_8_unused;
wire tcu_pce_ov_out_8_unused;
wire ccx_aclk_out_8_unused;
wire ccx_bclk_out_8_unused;
wire cpx_mac8_scanin;
wire cpx_mac8_scanout;
wire [6:0] tcu_scan_en_out;
wire [6:0] tcu_pce_ov_out;
wire [6:0] ccx_aclk_out;
wire [6:0] ccx_bclk_out;
wire [149:0] col1_data_x_;
wire cpx_mac0_scanin;
wire cpx_mac0_scanout;
wire [149:0] col2_data_x_;
wire cpx_mac1_scanin;
wire cpx_mac1_scanout;
wire [149:0] col3_data_x_;
wire cpx_mac2_scanin;
wire cpx_mac2_scanout;
wire [149:0] col4_data_x_;
wire cpx_mac3_scanin;
wire cpx_mac3_scanout;
wire [149:0] col5_data_x_;
wire cpx_mac4_scanin;
wire cpx_mac4_scanout;
wire [149:0] col6_data_x_;
wire cpx_mac5_scanin;
wire cpx_mac5_scanout;
wire [149:0] col7_data_x_;
wire cpx_mac6_scanin;
wire cpx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire cpx_mac7_scanin;
wire cpx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [8:0] arb_grant_r_a_unused;
wire [8:0] arb_q0_holdbar_r_a_unused;
wire [8:0] arb_qsel0_r_a_unused;
wire [8:0] arb_qsel1_r_a_unused;
wire [8:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [149:0]          cpx_spc_data_x_;        // From mac4 of cpx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [8:0]             arb_grant_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_l_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_grant_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_r_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [149:0]           io_cpx_data_a;          // To mac8 of cpx_mal_dp.v
input [149:0]           scache0_cpx_data_a;     // To mac0 of cpx_mar_dp.v
input [149:0]           scache1_cpx_data_a;     // To mac1 of cpx_mbr_dp.v
input [149:0]           scache2_cpx_data_a;     // To mac2 of cpx_mbr_dp.v
input [149:0]           scache3_cpx_data_a;     // To mac3 of cpx_mbr_dp.v
input [149:0]           scache4_cpx_data_a;     // To mac4 of cpx_mcr_dp.v
input [149:0]           scache5_cpx_data_a;     // To mac5 of cpx_mbl_dp.v
input [149:0]           scache6_cpx_data_a;     // To mac6 of cpx_mbl_dp.v
input [149:0]           scache7_cpx_data_a;     // To cpx_mac7 of cpx_mbl_dp.v
// End of automatics

// globals
input                   tcu_scan_en ;
input                   l2clk;
input                   scan_in;
input                   tcu_pce_ov;             // scan signals
input                   ccx_aclk;
input                   ccx_bclk;
output                  scan_out;

//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 <- mac1  <-mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      bl       cl     br      br      br       br       br       br      bl    
//               |                                          
//       ---buf--                                         
//      |                                                        
//      v                                                        
//    to spccore                                                   

assign all_ones[149:0] = 150'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;


// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
                           arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
        arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
                           arb_qsel1_l_a[0],arb_shift_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
        arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                           arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                           arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                           arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                           arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
                           arb_qsel1_r_a[6],arb_shift_r_a[6]};

assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
        arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


/*
cpx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(io_cpx_data_a[149:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from io
cpx_mbl_dp cpx_mac8 (
                     // Outputs
                     .data_out_x_       (col8_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_8_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
                     .ccx_aclk_out (ccx_aclk_out_8_unused),
                     .ccx_bclk_out (ccx_bclk_out_8_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a[8]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a[8]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a[8]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a[8]),   // Templated
                     .arb_shift_a       (arb_shift_l_a[8]),        // Templated
                     .src_cpx_data_a    (io_cpx_data_a[149:0]),  // Templated
                     .data_prev_x_      (all_ones[149:0]),
                     .scan_in(cpx_mac8_scanin),
                     .scan_out(cpx_mac8_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[0]),
                     .tcu_pce_ov (tcu_pce_ov_out[0]),
                     .ccx_aclk (ccx_aclk_out[0]),
                     .ccx_bclk (ccx_bclk_out[0])
                     );

/*
 cpx_mcl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(cpx_spc_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
 */

// input from sctag2
cpx_mcl_dp cpx_mac0 (
                     // Outputs
                     .data_out_x_       (cpx_spc_data_x_[149:0]), // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[0]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[0]),
                     .ccx_aclk_out (ccx_aclk_out[0]),
                     .ccx_bclk_out (ccx_bclk_out[0]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[2]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[2]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[2]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[2]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[2]),        // Templated
                     .src_cpx_data_a    (scache2_cpx_data_a[149:0]), // Templated
                     .data_crit_x_      (col1_data_x_[149:0]),   // Templated
                     .data_ncrit_x_     (col8_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac0_scanin),
                     .scan_out(cpx_mac0_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[1]),
                     .tcu_pce_ov (tcu_pce_ov_out[1]),
                     .ccx_aclk (ccx_aclk_out[1]),
                     .ccx_bclk (ccx_bclk_out[1])
                     );


/*
   cpx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag0
cpx_mbr_dp cpx_mac1 (
                     // Outputs
                     .data_out_x_       (col1_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[1]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                     .ccx_aclk_out (ccx_aclk_out[1]),
                     .ccx_bclk_out (ccx_bclk_out[1]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                     .src_cpx_data_a    (scache0_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col2_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac1_scanin),
                     .scan_out(cpx_mac1_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[2]),
                     .tcu_pce_ov (tcu_pce_ov_out[2]),
                     .ccx_aclk (ccx_aclk_out[2]),
                     .ccx_bclk (ccx_bclk_out[2])
                     );


// input from sctag3
cpx_mbr_dp cpx_mac2 (
                     // Outputs
                     .data_out_x_       (col2_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[2]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                     .ccx_aclk_out (ccx_aclk_out[2]),
                     .ccx_bclk_out (ccx_bclk_out[2]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[3]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[3]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[3]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[3]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[3]),        // Templated
                     .src_cpx_data_a    (scache3_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col3_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac2_scanin),
                     .scan_out(cpx_mac2_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[3]),
                     .tcu_pce_ov (tcu_pce_ov_out[3]),
                     .ccx_aclk (ccx_aclk_out[3]),
                     .ccx_bclk (ccx_bclk_out[3])
                     );
 

// input from sctag1
cpx_mbr_dp cpx_mac3 (
                     // Outputs
                     .data_out_x_       (col3_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[3]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                     .ccx_aclk_out (ccx_aclk_out[3]),
                     .ccx_bclk_out (ccx_bclk_out[3]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[1]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[1]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[1]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[1]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[1]),        // Templated
                     .src_cpx_data_a    (scache1_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col4_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac3_scanin),
                     .scan_out(cpx_mac3_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en),
                     .tcu_pce_ov (tcu_pce_ov),
                     .ccx_aclk (ccx_aclk),
                     .ccx_bclk (ccx_bclk)
                     );


// input from sctag7
cpx_mbr_dp cpx_mac4 (
                     // Outputs
                     .data_out_x_       (col4_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[4]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                     .ccx_aclk_out (ccx_aclk_out[4]),
                     .ccx_bclk_out (ccx_bclk_out[4]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[7]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[7]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[7]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[7]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[7]),        // Templated
                     .src_cpx_data_a    (scache7_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col5_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac4_scanin),
                     .scan_out(cpx_mac4_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[3]),
                     .tcu_pce_ov (tcu_pce_ov_out[3]),
                     .ccx_aclk (ccx_aclk_out[3]),
                     .ccx_bclk (ccx_bclk_out[3])
                     );


// input from sctag5
cpx_mbr_dp cpx_mac5 (
                     // Outputs
                     .data_out_x_       (col5_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[5]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                     .ccx_aclk_out (ccx_aclk_out[5]),
                     .ccx_bclk_out (ccx_bclk_out[5]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[5]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[5]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[5]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[5]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[5]),        // Templated
                     .src_cpx_data_a    (scache5_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col6_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac5_scanin),
                     .scan_out(cpx_mac5_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[4]),
                     .tcu_pce_ov (tcu_pce_ov_out[4]),
                     .ccx_aclk (ccx_aclk_out[4]),
                     .ccx_bclk (ccx_bclk_out[4])
                     );
 
// input from sctag6
cpx_mbr_dp cpx_mac6 (
                     // Outputs
                     .data_out_x_       (col6_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[6]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                     .ccx_aclk_out (ccx_aclk_out[6]),
                     .ccx_bclk_out (ccx_bclk_out[6]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[6]),        // Templated
                     .src_cpx_data_a    (scache6_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col7_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac6_scanin),
                     .scan_out(cpx_mac6_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[5]),
                     .tcu_pce_ov (tcu_pce_ov_out[5]),
                     .ccx_aclk (ccx_aclk_out[5]),
                     .ccx_bclk (ccx_bclk_out[5])
                     );
 
 
/*
   cpx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag4
cpx_mar_dp cpx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out (ccx_aclk_out_7_unused),
                     .ccx_bclk_out (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[4]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[4]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[4]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[4]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[4]),        // Templated
                     .src_cpx_data_a    (scache4_cpx_data_a[149:0]), // Templated
                     .scan_in(cpx_mac7_scanin),
                     .scan_out(cpx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[6]),
                     .tcu_pce_ov (tcu_pce_ov_out[6]),
                     .ccx_aclk (ccx_aclk_out[6]),
                     .ccx_bclk (ccx_bclk_out[6])
                     );
 

assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];

// fixscan start:
assign cpx_mac8_scanin           = scan_rep_out                  ;
assign cpx_mac0_scanin           = cpx_mac8_scanout         ;
assign cpx_mac1_scanin           = cpx_mac0_scanout         ;
assign cpx_mac2_scanin           = cpx_mac1_scanout         ;
assign cpx_mac3_scanin           = cpx_mac2_scanout         ;
assign cpx_mac4_scanin           = cpx_mac3_scanout         ;
assign cpx_mac5_scanin           = cpx_mac4_scanout         ;
assign cpx_mac6_scanin           = cpx_mac5_scanout         ;
assign cpx_mac7_scanin           = cpx_mac6_scanout         ;
assign scan_out                  = cpx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module cpx_dpsa_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsa_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsa_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_dpsa_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsa_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsa_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsa_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsa_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_dpsa(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a, 
	scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a, 
	scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
	l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[149:0]		cpx_spc_data_x_;
	input	[8:0]		arb_grant_l_a;
	input	[8:0]		arb_q0_holdbar_l_a;
	input	[8:0]		arb_qsel0_l_a;
	input	[8:0]		arb_qsel1_l_a;
	input	[8:0]		arb_shift_l_a;
	input	[8:0]		arb_grant_r_a;
	input	[8:0]		arb_q0_holdbar_r_a;
	input	[8:0]		arb_qsel0_r_a;
	input	[8:0]		arb_qsel1_r_a;
	input	[8:0]		arb_shift_r_a;
	input	[149:0]		io_cpx_data_a;
	input	[149:0]		scache0_cpx_data_a;
	input	[149:0]		scache1_cpx_data_a;
	input	[149:0]		scache2_cpx_data_a;
	input	[149:0]		scache3_cpx_data_a;
	input	[149:0]		scache4_cpx_data_a;
	input	[149:0]		scache5_cpx_data_a;
	input	[149:0]		scache6_cpx_data_a;
	input	[149:0]		scache7_cpx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[149:0]		all_ones;
	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:5]		arb_grant_r_a_rep;
	wire	[7:5]		arb_q0_holdbar_r_a_rep;
	wire	[7:5]		arb_qsel0_r_a_rep;
	wire	[7:5]		arb_qsel1_r_a_rep;
	wire	[7:5]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[149:0]		col8_data_x_;
	wire			tcu_scan_en_out_8_unused;
	wire			tcu_pce_ov_out_8_unused;
	wire			ccx_aclk_out_8_unused;
	wire			ccx_bclk_out_8_unused;
	wire			cpx_mac8_scanin;
	wire			cpx_mac8_scanout;
	wire	[6:0]		tcu_scan_en_out;
	wire	[6:0]		tcu_pce_ov_out;
	wire	[6:0]		ccx_aclk_out;
	wire	[6:0]		ccx_bclk_out;
	wire	[149:0]		col1_data_x_;
	wire			cpx_mac0_scanin;
	wire			cpx_mac0_scanout;
	wire	[149:0]		col2_data_x_;
	wire			cpx_mac1_scanin;
	wire			cpx_mac1_scanout;
	wire	[149:0]		col3_data_x_;
	wire			cpx_mac2_scanin;
	wire			cpx_mac2_scanout;
	wire	[149:0]		col4_data_x_;
	wire			cpx_mac3_scanin;
	wire			cpx_mac3_scanout;
	wire	[149:0]		col5_data_x_;
	wire			cpx_mac4_scanin;
	wire			cpx_mac4_scanout;
	wire	[149:0]		col6_data_x_;
	wire			cpx_mac5_scanin;
	wire			cpx_mac5_scanout;
	wire	[149:0]		col7_data_x_;
	wire			cpx_mac6_scanin;
	wire			cpx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			cpx_mac7_scanin;
	wire			cpx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[8:0]		arb_grant_r_a_unused;
	wire	[8:0]		arb_q0_holdbar_r_a_unused;
	wire	[8:0]		arb_qsel0_r_a_unused;
	wire	[8:0]		arb_qsel1_r_a_unused;
	wire	[8:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign all_ones[149:0] = 150'h3fffffffffffffffffffffffffffffffffffff;
	assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2], 
		arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2], 
		arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2], 
		arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0], 
		arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0], 
		arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6], 
		arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
	assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6], 
		arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
	assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
	assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
	assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
	assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
	assign cpx_mac8_scanin = scan_rep_out;
	assign cpx_mac0_scanin = cpx_mac8_scanout;
	assign cpx_mac1_scanin = cpx_mac0_scanout;
	assign cpx_mac2_scanin = cpx_mac1_scanout;
	assign cpx_mac3_scanin = cpx_mac2_scanout;
	assign cpx_mac4_scanin = cpx_mac3_scanout;
	assign cpx_mac5_scanin = cpx_mac4_scanout;
	assign cpx_mac6_scanin = cpx_mac5_scanout;
	assign cpx_mac7_scanin = cpx_mac6_scanout;
	assign scan_out = cpx_mac7_scanout;

	cpx_rep_dp cpx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	cpx_mbl_dp cpx_mac8(
		.data_out_x_			(col8_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_8_unused), 
		.ccx_aclk_out			(ccx_aclk_out_8_unused), 
		.ccx_bclk_out			(ccx_bclk_out_8_unused), 
		.arb_grant_a			(arb_grant_l_a[8]), 
		.arb_qsel0_a			(arb_qsel0_l_a[8]), 
		.arb_qsel1_a			(arb_qsel1_l_a[8]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a[8]), 
		.arb_shift_a			(arb_shift_l_a[8]), 
		.src_cpx_data_a			(io_cpx_data_a[149:0]), 
		.data_prev_x_			(all_ones[149:0]), 
		.scan_in			(cpx_mac8_scanin), 
		.scan_out			(cpx_mac8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[0]), 
		.tcu_pce_ov			(tcu_pce_ov_out[0]), 
		.ccx_aclk			(ccx_aclk_out[0]), 
		.ccx_bclk			(ccx_bclk_out[0]));
	cpx_mcl_dp cpx_mac0(
		.data_out_x_			(cpx_spc_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[0]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[0]), 
		.ccx_aclk_out			(ccx_aclk_out[0]), 
		.ccx_bclk_out			(ccx_bclk_out[0]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_cpx_data_a			(scache2_cpx_data_a[149:0]), 
		.data_crit_x_			(col1_data_x_[149:0]), 
		.data_ncrit_x_			(col8_data_x_[149:0]), 
		.scan_in			(cpx_mac0_scanin), 
		.scan_out			(cpx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	cpx_mbr_dp cpx_mac1(
		.data_out_x_			(col1_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_cpx_data_a			(scache0_cpx_data_a[149:0]), 
		.data_prev_x_			(col2_data_x_[149:0]), 
		.scan_in			(cpx_mac1_scanin), 
		.scan_out			(cpx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	cpx_mbr_dp cpx_mac2(
		.data_out_x_			(col2_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_cpx_data_a			(scache3_cpx_data_a[149:0]), 
		.data_prev_x_			(col3_data_x_[149:0]), 
		.scan_in			(cpx_mac2_scanin), 
		.scan_out			(cpx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbr_dp cpx_mac3(
		.data_out_x_			(col3_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_cpx_data_a			(scache1_cpx_data_a[149:0]), 
		.data_prev_x_			(col4_data_x_[149:0]), 
		.scan_in			(cpx_mac3_scanin), 
		.scan_out			(cpx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	cpx_mbr_dp cpx_mac4(
		.data_out_x_			(col4_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_cpx_data_a			(scache7_cpx_data_a[149:0]), 
		.data_prev_x_			(col5_data_x_[149:0]), 
		.scan_in			(cpx_mac4_scanin), 
		.scan_out			(cpx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbr_dp cpx_mac5(
		.data_out_x_			(col5_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_cpx_data_a			(scache5_cpx_data_a[149:0]), 
		.data_prev_x_			(col6_data_x_[149:0]), 
		.scan_in			(cpx_mac5_scanin), 
		.scan_out			(cpx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	cpx_mbr_dp cpx_mac6(
		.data_out_x_			(col6_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[6]), 
		.arb_shift_a			(arb_shift_r_a_rep[6]), 
		.src_cpx_data_a			(scache6_cpx_data_a[149:0]), 
		.data_prev_x_			(col7_data_x_[149:0]), 
		.scan_in			(cpx_mac6_scanin), 
		.scan_out			(cpx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	cpx_mar_dp cpx_mac7(
		.data_out_x_			(col7_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[4]), 
		.arb_shift_a			(arb_shift_r_a[4]), 
		.src_cpx_data_a			(scache4_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac7_scanin), 
		.scan_out			(cpx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_dpsb.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_dpsb (
  cpx_spc_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  io_cpx_data_a, 
  scache0_cpx_data_a, 
  scache1_cpx_data_a, 
  scache2_cpx_data_a, 
  scache3_cpx_data_a, 
  scache4_cpx_data_a, 
  scache5_cpx_data_a, 
  scache6_cpx_data_a, 
  scache7_cpx_data_a, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:5] arb_grant_r_a_rep;
wire [7:5] arb_q0_holdbar_r_a_rep;
wire [7:5] arb_qsel0_r_a_rep;
wire [7:5] arb_qsel1_r_a_rep;
wire [7:5] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [149:0] col8_data_x_;
wire tcu_scan_en_out_8_unused;
wire tcu_pce_ov_out_8_unused;
wire ccx_aclk_out_8_unused;
wire ccx_bclk_out_8_unused;
wire cpx_mac8_scanin;
wire cpx_mac8_scanout;
wire [6:0] tcu_scan_en_out;
wire [6:0] tcu_pce_ov_out;
wire [6:0] ccx_aclk_out;
wire [6:0] ccx_bclk_out;
wire [149:0] col0_data_x_;
wire cpx_mac0_scanin;
wire cpx_mac0_scanout;
wire [149:0] col2_data_x_;
wire cpx_mac1_scanin;
wire cpx_mac1_scanout;
wire [149:0] col3_data_x_;
wire cpx_mac2_scanin;
wire cpx_mac2_scanout;
wire [149:0] col4_data_x_;
wire cpx_mac3_scanin;
wire cpx_mac3_scanout;
wire [149:0] col5_data_x_;
wire cpx_mac4_scanin;
wire cpx_mac4_scanout;
wire [149:0] col6_data_x_;
wire cpx_mac5_scanin;
wire cpx_mac5_scanout;
wire [149:0] col7_data_x_;
wire cpx_mac6_scanin;
wire cpx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire cpx_mac7_scanin;
wire cpx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [8:0] arb_grant_r_a_unused;
wire [8:0] arb_q0_holdbar_r_a_unused;
wire [8:0] arb_qsel0_r_a_unused;
wire [8:0] arb_qsel1_r_a_unused;
wire [8:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [149:0]          cpx_spc_data_x_;        // From mac4 of cpx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [8:0]             arb_grant_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_l_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_grant_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_r_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [149:0]           io_cpx_data_a;          // To mac8 of cpx_mal_dp.v
input [149:0]           scache0_cpx_data_a;     // To mac0 of cpx_mar_dp.v
input [149:0]           scache1_cpx_data_a;     // To mac1 of cpx_mbr_dp.v
input [149:0]           scache2_cpx_data_a;     // To mac2 of cpx_mbr_dp.v
input [149:0]           scache3_cpx_data_a;     // To mac3 of cpx_mbr_dp.v
input [149:0]           scache4_cpx_data_a;     // To mac4 of cpx_mcr_dp.v
input [149:0]           scache5_cpx_data_a;     // To mac5 of cpx_mbl_dp.v
input [149:0]           scache6_cpx_data_a;     // To mac6 of cpx_mbl_dp.v
input [149:0]           scache7_cpx_data_a;     // To cpx_mac7 of cpx_mbl_dp.v
// End of automatics

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;


//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  <-mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     cl      br      br       br       br       br      bl    
//                      |                                          
//       ---buf---------                                         
//      |                                                        
//      v                                                        
//    to spccore                                                   

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
                           arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
        arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
                       arb_qsel1_l_a[0],arb_shift_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
        arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
                       arb_qsel1_r_a[6],arb_shift_r_a[6]};

assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
        arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );

/*
   cpx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(io_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from io
cpx_mal_dp cpx_mac8 (
                     // Outputs
                     .data_out_x_       (col8_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_8_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
                     .ccx_aclk_out (ccx_aclk_out_8_unused),
                     .ccx_bclk_out (ccx_bclk_out_8_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a[8]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a[8]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a[8]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a[8]),   // Templated
                     .arb_shift_a       (arb_shift_l_a[8]),        // Templated
                     .src_cpx_data_a    (io_cpx_data_a[149:0]),  // Templated
                     .scan_in(cpx_mac8_scanin),
                     .scan_out(cpx_mac8_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[0]),
                     .tcu_pce_ov (tcu_pce_ov_out[0]),
                     .ccx_aclk (ccx_aclk_out[0]),
                     .ccx_bclk (ccx_bclk_out[0])
                     );


/*
cpx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag2
cpx_mbl_dp cpx_mac0 (
                     // Outputs
                     .data_out_x_       (col0_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[0]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[0]),
                     .ccx_aclk_out (ccx_aclk_out[0]),
                     .ccx_bclk_out (ccx_bclk_out[0]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[2]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[2]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[2]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[2]),
                     .arb_shift_a       (arb_shift_l_a_rep[2]),
                     .src_cpx_data_a    (scache2_cpx_data_a[149:0]),
                     .data_prev_x_      (col8_data_x_[149:0]),
                     .scan_in(cpx_mac0_scanin),
                     .scan_out(cpx_mac0_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en (tcu_scan_en_out[1]),
                     .tcu_pce_ov (tcu_pce_ov_out[1]),
                     .ccx_aclk (ccx_aclk_out[1]),
                     .ccx_bclk (ccx_bclk_out[1])
                     );


/*
   cpx_mcl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(cpx_spc_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag0
cpx_mcl_dp cpx_mac1 (
                     // Outputs
                     .data_out_x_       (cpx_spc_data_x_[149:0]), // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[1]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[1]),
                     .ccx_aclk_out    (ccx_aclk_out[1]),
                     .ccx_bclk_out    (ccx_bclk_out[1]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                     .src_cpx_data_a    (scache0_cpx_data_a[149:0]), // Templated
                     .data_crit_x_      (col2_data_x_[149:0]),   // Templated
                     .data_ncrit_x_     (col0_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac1_scanin),
                     .scan_out(cpx_mac1_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[2]),
                     .tcu_pce_ov     (tcu_pce_ov_out[2]),
                     .ccx_aclk       (ccx_aclk_out[2]),
                     .ccx_bclk       (ccx_bclk_out[2])
                     );


/*
   cpx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag3
cpx_mbr_dp cpx_mac2 (
                     // Outputs
                     .data_out_x_       (col2_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[2]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[2]),
                     .ccx_aclk_out    (ccx_aclk_out[2]),
                     .ccx_bclk_out    (ccx_bclk_out[2]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[3]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[3]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[3]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[3]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[3]),        // Templated
                     .src_cpx_data_a    (scache3_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col3_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac2_scanin),
                     .scan_out(cpx_mac2_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );


// input from sctag1
cpx_mbr_dp cpx_mac3 (
                     // Outputs
                     .data_out_x_       (col3_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[3]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[3]),
                     .ccx_aclk_out    (ccx_aclk_out[3]),
                     .ccx_bclk_out    (ccx_bclk_out[3]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[1]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[1]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[1]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[1]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[1]),        // Templated
                     .src_cpx_data_a    (scache1_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col4_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac3_scanin),
                     .scan_out(cpx_mac3_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en),
                     .tcu_pce_ov     (tcu_pce_ov),
                     .ccx_aclk       (ccx_aclk),
                     .ccx_bclk       (ccx_bclk)
                     );


// input from sctag7
cpx_mbr_dp cpx_mac4 (
                     // Outputs
                     .data_out_x_       (col4_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[4]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[4]),
                     .ccx_aclk_out    (ccx_aclk_out[4]),
                     .ccx_bclk_out    (ccx_bclk_out[4]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[7]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[7]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[7]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[7]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[7]),        // Templated
                     .src_cpx_data_a    (scache7_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col5_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac4_scanin),
                     .scan_out(cpx_mac4_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );


// input from sctag5
cpx_mbr_dp cpx_mac5 (
                     // Outputs
                     .data_out_x_       (col5_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[5]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[5]),
                     .ccx_aclk_out    (ccx_aclk_out[5]),
                     .ccx_bclk_out    (ccx_bclk_out[5]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[5]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[5]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[5]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[5]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[5]),        // Templated
                     .src_cpx_data_a    (scache5_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col6_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac5_scanin),
                     .scan_out(cpx_mac5_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[4]),
                     .tcu_pce_ov     (tcu_pce_ov_out[4]),
                     .ccx_aclk       (ccx_aclk_out[4]),
                     .ccx_bclk       (ccx_bclk_out[4])
                     );

// input from sctag6
cpx_mbr_dp cpx_mac6 (
                     // Outputs
                     .data_out_x_       (col6_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[6]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[6]),
                     .ccx_aclk_out    (ccx_aclk_out[6]),
                     .ccx_bclk_out    (ccx_bclk_out[6]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[6]),        // Templated
                     .src_cpx_data_a    (scache6_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col7_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac6_scanin),
                     .scan_out(cpx_mac6_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[5]),
                     .tcu_pce_ov     (tcu_pce_ov_out[5]),
                     .ccx_aclk       (ccx_aclk_out[5]),
                     .ccx_bclk       (ccx_bclk_out[5])
                     );
 
/*
   cpx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag4
cpx_mar_dp cpx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out  (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out    (ccx_aclk_out_7_unused),
                     .ccx_bclk_out    (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[4]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[4]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[4]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[4]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[4]),        // Templated
                     .src_cpx_data_a    (scache4_cpx_data_a[149:0]), // Templated
                     .scan_in(cpx_mac7_scanin),
                     .scan_out(cpx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[6]),
                     .tcu_pce_ov     (tcu_pce_ov_out[6]),
                     .ccx_aclk       (ccx_aclk_out[6]),
                     .ccx_bclk       (ccx_bclk_out[6])
                     );
 

assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];


// fixscan start:
assign cpx_mac8_scanin           = scan_rep_out                  ;
assign cpx_mac0_scanin           = cpx_mac8_scanout         ;
assign cpx_mac1_scanin           = cpx_mac0_scanout         ;
assign cpx_mac2_scanin           = cpx_mac1_scanout         ;
assign cpx_mac3_scanin           = cpx_mac2_scanout         ;
assign cpx_mac4_scanin           = cpx_mac3_scanout         ;
assign cpx_mac5_scanin           = cpx_mac4_scanout         ;
assign cpx_mac6_scanin           = cpx_mac5_scanout         ;
assign cpx_mac7_scanin           = cpx_mac6_scanout         ;
assign scan_out                  = cpx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module cpx_dpsb_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsb_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsb_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_dpsb_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsb_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsb_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsb_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsb_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[49:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_dpsb(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a, 
	scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a, 
	scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
	l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[149:0]		cpx_spc_data_x_;
	input	[8:0]		arb_grant_l_a;
	input	[8:0]		arb_q0_holdbar_l_a;
	input	[8:0]		arb_qsel0_l_a;
	input	[8:0]		arb_qsel1_l_a;
	input	[8:0]		arb_shift_l_a;
	input	[8:0]		arb_grant_r_a;
	input	[8:0]		arb_q0_holdbar_r_a;
	input	[8:0]		arb_qsel0_r_a;
	input	[8:0]		arb_qsel1_r_a;
	input	[8:0]		arb_shift_r_a;
	input	[149:0]		io_cpx_data_a;
	input	[149:0]		scache0_cpx_data_a;
	input	[149:0]		scache1_cpx_data_a;
	input	[149:0]		scache2_cpx_data_a;
	input	[149:0]		scache3_cpx_data_a;
	input	[149:0]		scache4_cpx_data_a;
	input	[149:0]		scache5_cpx_data_a;
	input	[149:0]		scache6_cpx_data_a;
	input	[149:0]		scache7_cpx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:5]		arb_grant_r_a_rep;
	wire	[7:5]		arb_q0_holdbar_r_a_rep;
	wire	[7:5]		arb_qsel0_r_a_rep;
	wire	[7:5]		arb_qsel1_r_a_rep;
	wire	[7:5]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[149:0]		col8_data_x_;
	wire			tcu_scan_en_out_8_unused;
	wire			tcu_pce_ov_out_8_unused;
	wire			ccx_aclk_out_8_unused;
	wire			ccx_bclk_out_8_unused;
	wire			cpx_mac8_scanin;
	wire			cpx_mac8_scanout;
	wire	[6:0]		tcu_scan_en_out;
	wire	[6:0]		tcu_pce_ov_out;
	wire	[6:0]		ccx_aclk_out;
	wire	[6:0]		ccx_bclk_out;
	wire	[149:0]		col0_data_x_;
	wire			cpx_mac0_scanin;
	wire			cpx_mac0_scanout;
	wire	[149:0]		col2_data_x_;
	wire			cpx_mac1_scanin;
	wire			cpx_mac1_scanout;
	wire	[149:0]		col3_data_x_;
	wire			cpx_mac2_scanin;
	wire			cpx_mac2_scanout;
	wire	[149:0]		col4_data_x_;
	wire			cpx_mac3_scanin;
	wire			cpx_mac3_scanout;
	wire	[149:0]		col5_data_x_;
	wire			cpx_mac4_scanin;
	wire			cpx_mac4_scanout;
	wire	[149:0]		col6_data_x_;
	wire			cpx_mac5_scanin;
	wire			cpx_mac5_scanout;
	wire	[149:0]		col7_data_x_;
	wire			cpx_mac6_scanin;
	wire			cpx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			cpx_mac7_scanin;
	wire			cpx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[8:0]		arb_grant_r_a_unused;
	wire	[8:0]		arb_q0_holdbar_r_a_unused;
	wire	[8:0]		arb_qsel0_r_a_unused;
	wire	[8:0]		arb_qsel1_r_a_unused;
	wire	[8:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2], 
		arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2], 
		arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2], 
		arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0], 
		arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0], 
		arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6], 
		arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
	assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6], 
		arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
	assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
	assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
	assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
	assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
	assign cpx_mac8_scanin = scan_rep_out;
	assign cpx_mac0_scanin = cpx_mac8_scanout;
	assign cpx_mac1_scanin = cpx_mac0_scanout;
	assign cpx_mac2_scanin = cpx_mac1_scanout;
	assign cpx_mac3_scanin = cpx_mac2_scanout;
	assign cpx_mac4_scanin = cpx_mac3_scanout;
	assign cpx_mac5_scanin = cpx_mac4_scanout;
	assign cpx_mac6_scanin = cpx_mac5_scanout;
	assign cpx_mac7_scanin = cpx_mac6_scanout;
	assign scan_out = cpx_mac7_scanout;

	cpx_rep_dp cpx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	cpx_mal_dp cpx_mac8(
		.data_out_x_			(col8_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_8_unused), 
		.ccx_aclk_out			(ccx_aclk_out_8_unused), 
		.ccx_bclk_out			(ccx_bclk_out_8_unused), 
		.arb_grant_a			(arb_grant_l_a[8]), 
		.arb_qsel0_a			(arb_qsel0_l_a[8]), 
		.arb_qsel1_a			(arb_qsel1_l_a[8]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a[8]), 
		.arb_shift_a			(arb_shift_l_a[8]), 
		.src_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac8_scanin), 
		.scan_out			(cpx_mac8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[0]), 
		.tcu_pce_ov			(tcu_pce_ov_out[0]), 
		.ccx_aclk			(ccx_aclk_out[0]), 
		.ccx_bclk			(ccx_bclk_out[0]));
	cpx_mbl_dp cpx_mac0(
		.data_out_x_			(col0_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[0]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[0]), 
		.ccx_aclk_out			(ccx_aclk_out[0]), 
		.ccx_bclk_out			(ccx_bclk_out[0]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_cpx_data_a			(scache2_cpx_data_a[149:0]), 
		.data_prev_x_			(col8_data_x_[149:0]), 
		.scan_in			(cpx_mac0_scanin), 
		.scan_out			(cpx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	cpx_mcl_dp cpx_mac1(
		.data_out_x_			(cpx_spc_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_cpx_data_a			(scache0_cpx_data_a[149:0]), 
		.data_crit_x_			(col2_data_x_[149:0]), 
		.data_ncrit_x_			(col0_data_x_[149:0]), 
		.scan_in			(cpx_mac1_scanin), 
		.scan_out			(cpx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	cpx_mbr_dp cpx_mac2(
		.data_out_x_			(col2_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_cpx_data_a			(scache3_cpx_data_a[149:0]), 
		.data_prev_x_			(col3_data_x_[149:0]), 
		.scan_in			(cpx_mac2_scanin), 
		.scan_out			(cpx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbr_dp cpx_mac3(
		.data_out_x_			(col3_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_cpx_data_a			(scache1_cpx_data_a[149:0]), 
		.data_prev_x_			(col4_data_x_[149:0]), 
		.scan_in			(cpx_mac3_scanin), 
		.scan_out			(cpx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	cpx_mbr_dp cpx_mac4(
		.data_out_x_			(col4_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_cpx_data_a			(scache7_cpx_data_a[149:0]), 
		.data_prev_x_			(col5_data_x_[149:0]), 
		.scan_in			(cpx_mac4_scanin), 
		.scan_out			(cpx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbr_dp cpx_mac5(
		.data_out_x_			(col5_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_cpx_data_a			(scache5_cpx_data_a[149:0]), 
		.data_prev_x_			(col6_data_x_[149:0]), 
		.scan_in			(cpx_mac5_scanin), 
		.scan_out			(cpx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	cpx_mbr_dp cpx_mac6(
		.data_out_x_			(col6_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[6]), 
		.arb_shift_a			(arb_shift_r_a_rep[6]), 
		.src_cpx_data_a			(scache6_cpx_data_a[149:0]), 
		.data_prev_x_			(col7_data_x_[149:0]), 
		.scan_in			(cpx_mac6_scanin), 
		.scan_out			(cpx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	cpx_mar_dp cpx_mac7(
		.data_out_x_			(col7_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[4]), 
		.arb_shift_a			(arb_shift_r_a[4]), 
		.src_cpx_data_a			(scache4_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac7_scanin), 
		.scan_out			(cpx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_dpsc.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_dpsc (
  cpx_spc_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  io_cpx_data_a, 
  scache0_cpx_data_a, 
  scache1_cpx_data_a, 
  scache2_cpx_data_a, 
  scache3_cpx_data_a, 
  scache4_cpx_data_a, 
  scache5_cpx_data_a, 
  scache6_cpx_data_a, 
  scache7_cpx_data_a, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:5] arb_grant_r_a_rep;
wire [7:5] arb_q0_holdbar_r_a_rep;
wire [7:5] arb_qsel0_r_a_rep;
wire [7:5] arb_qsel1_r_a_rep;
wire [7:5] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [149:0] col8_data_x_;
wire tcu_scan_en_out_8_unused;
wire tcu_pce_ov_out_8_unused;
wire ccx_aclk_out_8_unused;
wire ccx_bclk_out_8_unused;
wire cpx_mac8_scanin;
wire cpx_mac8_scanout;
wire [6:0] tcu_scan_en_out;
wire [6:0] tcu_pce_ov_out;
wire [6:0] ccx_aclk_out;
wire [6:0] ccx_bclk_out;
wire [149:0] col0_data_x_;
wire cpx_mac0_scanin;
wire cpx_mac0_scanout;
wire [149:0] col1_data_x_;
wire cpx_mac1_scanin;
wire cpx_mac1_scanout;
wire [149:0] col3_data_x_;
wire cpx_mac2_scanin;
wire cpx_mac2_scanout;
wire [149:0] col4_data_x_;
wire cpx_mac3_scanin;
wire cpx_mac3_scanout;
wire [149:0] col5_data_x_;
wire cpx_mac4_scanin;
wire cpx_mac4_scanout;
wire [149:0] col6_data_x_;
wire cpx_mac5_scanin;
wire cpx_mac5_scanout;
wire [149:0] col7_data_x_;
wire cpx_mac6_scanin;
wire cpx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire cpx_mac7_scanin;
wire cpx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [8:0] arb_grant_r_a_unused;
wire [8:0] arb_q0_holdbar_r_a_unused;
wire [8:0] arb_qsel0_r_a_unused;
wire [8:0] arb_qsel1_r_a_unused;
wire [8:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [149:0]          cpx_spc_data_x_;        // From mac4 of cpx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [8:0]             arb_grant_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_l_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_grant_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_r_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [149:0]           io_cpx_data_a;          // To mac8 of cpx_mal_dp.v
input [149:0]           scache0_cpx_data_a;     // To mac0 of cpx_mar_dp.v
input [149:0]           scache1_cpx_data_a;     // To mac1 of cpx_mbr_dp.v
input [149:0]           scache2_cpx_data_a;     // To mac2 of cpx_mbr_dp.v
input [149:0]           scache3_cpx_data_a;     // To mac3 of cpx_mbr_dp.v
input [149:0]           scache4_cpx_data_a;     // To mac4 of cpx_mcr_dp.v
input [149:0]           scache5_cpx_data_a;     // To mac5 of cpx_mbl_dp.v
input [149:0]           scache6_cpx_data_a;     // To mac6 of cpx_mbl_dp.v
input [149:0]           scache7_cpx_data_a;     // To cpx_mac7 of cpx_mbl_dp.v
// End of automatics

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;


//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  <-mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      cl      br       br       br       br      bl    
//                               |                                          
//       ---buf-------------------                                         
//      |                                                        
//      v                                                        
//    to spccore                                                   

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
                           arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
        arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
                       arb_qsel1_l_a[0],arb_shift_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
        arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
                       arb_qsel1_r_a[6],arb_shift_r_a[6]};

assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
        arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );

/*
   cpx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(io_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from io
cpx_mal_dp cpx_mac8 (
                     // Outputs
                     .data_out_x_       (col8_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_8_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
                     .ccx_aclk_out (ccx_aclk_out_8_unused),
                     .ccx_bclk_out (ccx_bclk_out_8_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a[8]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a[8]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a[8]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a[8]),   // Templated
                     .arb_shift_a       (arb_shift_l_a[8]),        // Templated
                     .src_cpx_data_a    (io_cpx_data_a[149:0]),  // Templated
                     .scan_in(cpx_mac8_scanin),
                     .scan_out(cpx_mac8_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[0]),
                     .tcu_pce_ov (tcu_pce_ov_out[0]),
                     .ccx_aclk (ccx_aclk_out[0]),
                     .ccx_bclk (ccx_bclk_out[0])
                     );


/*
 cpx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag2
cpx_mbl_dp cpx_mac0 (
                     // Outputs
                     .data_out_x_       (col0_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[0]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[0]),
                     .ccx_aclk_out (ccx_aclk_out[0]),
                     .ccx_bclk_out (ccx_bclk_out[0]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[2]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[2]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[2]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[2]),
                     .arb_shift_a       (arb_shift_l_a_rep[2]),
                     .src_cpx_data_a    (scache2_cpx_data_a[149:0]),
                     .data_prev_x_      (col8_data_x_[149:0]),
                     .scan_in(cpx_mac0_scanin),
                     .scan_out(cpx_mac0_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en (tcu_scan_en_out[1]),
                     .tcu_pce_ov (tcu_pce_ov_out[1]),
                     .ccx_aclk (ccx_aclk_out[1]),
                     .ccx_bclk (ccx_bclk_out[1])
                     );


// input from sctag0
cpx_mbl_dp cpx_mac1 (
                     // Outputs
                     .data_out_x_       (col1_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[1]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[1]),
                     .ccx_aclk_out    (ccx_aclk_out[1]),
                     .ccx_bclk_out    (ccx_bclk_out[1]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[0]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),
                     .arb_shift_a       (arb_shift_l_a_rep[0]),
                     .src_cpx_data_a    (scache0_cpx_data_a[149:0]),
                     .data_prev_x_      (col0_data_x_[149:0]),
                     .scan_in(cpx_mac1_scanin),
                     .scan_out(cpx_mac1_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[2]),
                     .tcu_pce_ov     (tcu_pce_ov_out[2]),
                     .ccx_aclk       (ccx_aclk_out[2]),
                     .ccx_bclk       (ccx_bclk_out[2])
                     );


/*
   cpx_mcl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(cpx_spc_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag3
cpx_mcl_dp cpx_mac2 (
                     // Outputs
                     .data_out_x_       (cpx_spc_data_x_[149:0]), // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[2]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[2]),
                     .ccx_aclk_out    (ccx_aclk_out[2]),
                     .ccx_bclk_out    (ccx_bclk_out[2]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[3]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[3]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[3]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[3]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[3]),        // Templated
                     .src_cpx_data_a    (scache3_cpx_data_a[149:0]), // Templated
                     .data_crit_x_      (col3_data_x_[149:0]),   // Templated
                     .data_ncrit_x_     (col1_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac2_scanin),
                     .scan_out(cpx_mac2_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );


/*
   cpx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag1
cpx_mbr_dp cpx_mac3 (
                     // Outputs
                     .data_out_x_       (col3_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[3]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[3]),
                     .ccx_aclk_out    (ccx_aclk_out[3]),
                     .ccx_bclk_out    (ccx_bclk_out[3]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[1]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[1]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[1]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[1]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[1]),        // Templated
                     .src_cpx_data_a    (scache1_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col4_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac3_scanin),
                     .scan_out(cpx_mac3_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en),
                     .tcu_pce_ov     (tcu_pce_ov),
                     .ccx_aclk       (ccx_aclk),
                     .ccx_bclk       (ccx_bclk)
                     );


// input from sctag7
cpx_mbr_dp cpx_mac4 (
                     // Outputs
                     .data_out_x_       (col4_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[4]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[4]),
                     .ccx_aclk_out    (ccx_aclk_out[4]),
                     .ccx_bclk_out    (ccx_bclk_out[4]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[7]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[7]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[7]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[7]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[7]),        // Templated
                     .src_cpx_data_a    (scache7_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col5_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac4_scanin),
                     .scan_out(cpx_mac4_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );


// input from sctag5
cpx_mbr_dp cpx_mac5 (
                     // Outputs
                     .data_out_x_       (col5_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[5]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[5]),
                     .ccx_aclk_out    (ccx_aclk_out[5]),
                     .ccx_bclk_out    (ccx_bclk_out[5]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[5]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[5]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[5]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[5]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[5]),        // Templated
                     .src_cpx_data_a    (scache5_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col6_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac5_scanin),
                     .scan_out(cpx_mac5_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[4]),
                     .tcu_pce_ov     (tcu_pce_ov_out[4]),
                     .ccx_aclk       (ccx_aclk_out[4]),
                     .ccx_bclk       (ccx_bclk_out[4])
                     );

// input from sctag6
cpx_mbr_dp cpx_mac6 (
                     // Outputs
                     .data_out_x_       (col6_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[6]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[6]),
                     .ccx_aclk_out    (ccx_aclk_out[6]),
                     .ccx_bclk_out    (ccx_bclk_out[6]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[6]),        // Templated
                     .src_cpx_data_a    (scache6_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col7_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac6_scanin),
                     .scan_out(cpx_mac6_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[5]),
                     .tcu_pce_ov     (tcu_pce_ov_out[5]),
                     .ccx_aclk       (ccx_aclk_out[5]),
                     .ccx_bclk       (ccx_bclk_out[5])
                     );
 
/*
   cpx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag4
cpx_mar_dp cpx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out  (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out    (ccx_aclk_out_7_unused),
                     .ccx_bclk_out    (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[4]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[4]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[4]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[4]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[4]),        // Templated
                     .src_cpx_data_a    (scache4_cpx_data_a[149:0]), // Templated
                     .scan_in(cpx_mac7_scanin),
                     .scan_out(cpx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[6]),
                     .tcu_pce_ov     (tcu_pce_ov_out[6]),
                     .ccx_aclk       (ccx_aclk_out[6]),
                     .ccx_bclk       (ccx_bclk_out[6])
                     );
 

assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];

// fixscan start:
assign cpx_mac8_scanin           = scan_rep_out                  ;
assign cpx_mac0_scanin           = cpx_mac8_scanout         ;
assign cpx_mac1_scanin           = cpx_mac0_scanout         ;
assign cpx_mac2_scanin           = cpx_mac1_scanout         ;
assign cpx_mac3_scanin           = cpx_mac2_scanout         ;
assign cpx_mac4_scanin           = cpx_mac3_scanout         ;
assign cpx_mac5_scanin           = cpx_mac4_scanout         ;
assign cpx_mac6_scanin           = cpx_mac5_scanout         ;
assign cpx_mac7_scanin           = cpx_mac6_scanout         ;
assign scan_out                  = cpx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module cpx_dpsc_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsc_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsc_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_dpsc_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsc_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsc_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsc_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsc_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[49:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_dpsc(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a, 
	scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a, 
	scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
	l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[149:0]		cpx_spc_data_x_;
	input	[8:0]		arb_grant_l_a;
	input	[8:0]		arb_q0_holdbar_l_a;
	input	[8:0]		arb_qsel0_l_a;
	input	[8:0]		arb_qsel1_l_a;
	input	[8:0]		arb_shift_l_a;
	input	[8:0]		arb_grant_r_a;
	input	[8:0]		arb_q0_holdbar_r_a;
	input	[8:0]		arb_qsel0_r_a;
	input	[8:0]		arb_qsel1_r_a;
	input	[8:0]		arb_shift_r_a;
	input	[149:0]		io_cpx_data_a;
	input	[149:0]		scache0_cpx_data_a;
	input	[149:0]		scache1_cpx_data_a;
	input	[149:0]		scache2_cpx_data_a;
	input	[149:0]		scache3_cpx_data_a;
	input	[149:0]		scache4_cpx_data_a;
	input	[149:0]		scache5_cpx_data_a;
	input	[149:0]		scache6_cpx_data_a;
	input	[149:0]		scache7_cpx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:5]		arb_grant_r_a_rep;
	wire	[7:5]		arb_q0_holdbar_r_a_rep;
	wire	[7:5]		arb_qsel0_r_a_rep;
	wire	[7:5]		arb_qsel1_r_a_rep;
	wire	[7:5]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[149:0]		col8_data_x_;
	wire			tcu_scan_en_out_8_unused;
	wire			tcu_pce_ov_out_8_unused;
	wire			ccx_aclk_out_8_unused;
	wire			ccx_bclk_out_8_unused;
	wire			cpx_mac8_scanin;
	wire			cpx_mac8_scanout;
	wire	[6:0]		tcu_scan_en_out;
	wire	[6:0]		tcu_pce_ov_out;
	wire	[6:0]		ccx_aclk_out;
	wire	[6:0]		ccx_bclk_out;
	wire	[149:0]		col0_data_x_;
	wire			cpx_mac0_scanin;
	wire			cpx_mac0_scanout;
	wire	[149:0]		col1_data_x_;
	wire			cpx_mac1_scanin;
	wire			cpx_mac1_scanout;
	wire	[149:0]		col3_data_x_;
	wire			cpx_mac2_scanin;
	wire			cpx_mac2_scanout;
	wire	[149:0]		col4_data_x_;
	wire			cpx_mac3_scanin;
	wire			cpx_mac3_scanout;
	wire	[149:0]		col5_data_x_;
	wire			cpx_mac4_scanin;
	wire			cpx_mac4_scanout;
	wire	[149:0]		col6_data_x_;
	wire			cpx_mac5_scanin;
	wire			cpx_mac5_scanout;
	wire	[149:0]		col7_data_x_;
	wire			cpx_mac6_scanin;
	wire			cpx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			cpx_mac7_scanin;
	wire			cpx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[8:0]		arb_grant_r_a_unused;
	wire	[8:0]		arb_q0_holdbar_r_a_unused;
	wire	[8:0]		arb_qsel0_r_a_unused;
	wire	[8:0]		arb_qsel1_r_a_unused;
	wire	[8:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2], 
		arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2], 
		arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2], 
		arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0], 
		arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0], 
		arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6], 
		arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
	assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6], 
		arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
	assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
	assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
	assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
	assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
	assign cpx_mac8_scanin = scan_rep_out;
	assign cpx_mac0_scanin = cpx_mac8_scanout;
	assign cpx_mac1_scanin = cpx_mac0_scanout;
	assign cpx_mac2_scanin = cpx_mac1_scanout;
	assign cpx_mac3_scanin = cpx_mac2_scanout;
	assign cpx_mac4_scanin = cpx_mac3_scanout;
	assign cpx_mac5_scanin = cpx_mac4_scanout;
	assign cpx_mac6_scanin = cpx_mac5_scanout;
	assign cpx_mac7_scanin = cpx_mac6_scanout;
	assign scan_out = cpx_mac7_scanout;

	cpx_rep_dp cpx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	cpx_mal_dp cpx_mac8(
		.data_out_x_			(col8_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_8_unused), 
		.ccx_aclk_out			(ccx_aclk_out_8_unused), 
		.ccx_bclk_out			(ccx_bclk_out_8_unused), 
		.arb_grant_a			(arb_grant_l_a[8]), 
		.arb_qsel0_a			(arb_qsel0_l_a[8]), 
		.arb_qsel1_a			(arb_qsel1_l_a[8]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a[8]), 
		.arb_shift_a			(arb_shift_l_a[8]), 
		.src_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac8_scanin), 
		.scan_out			(cpx_mac8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[0]), 
		.tcu_pce_ov			(tcu_pce_ov_out[0]), 
		.ccx_aclk			(ccx_aclk_out[0]), 
		.ccx_bclk			(ccx_bclk_out[0]));
	cpx_mbl_dp cpx_mac0(
		.data_out_x_			(col0_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[0]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[0]), 
		.ccx_aclk_out			(ccx_aclk_out[0]), 
		.ccx_bclk_out			(ccx_bclk_out[0]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_cpx_data_a			(scache2_cpx_data_a[149:0]), 
		.data_prev_x_			(col8_data_x_[149:0]), 
		.scan_in			(cpx_mac0_scanin), 
		.scan_out			(cpx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	cpx_mbl_dp cpx_mac1(
		.data_out_x_			(col1_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_cpx_data_a			(scache0_cpx_data_a[149:0]), 
		.data_prev_x_			(col0_data_x_[149:0]), 
		.scan_in			(cpx_mac1_scanin), 
		.scan_out			(cpx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	cpx_mcl_dp cpx_mac2(
		.data_out_x_			(cpx_spc_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_cpx_data_a			(scache3_cpx_data_a[149:0]), 
		.data_crit_x_			(col3_data_x_[149:0]), 
		.data_ncrit_x_			(col1_data_x_[149:0]), 
		.scan_in			(cpx_mac2_scanin), 
		.scan_out			(cpx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbr_dp cpx_mac3(
		.data_out_x_			(col3_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_cpx_data_a			(scache1_cpx_data_a[149:0]), 
		.data_prev_x_			(col4_data_x_[149:0]), 
		.scan_in			(cpx_mac3_scanin), 
		.scan_out			(cpx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	cpx_mbr_dp cpx_mac4(
		.data_out_x_			(col4_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_cpx_data_a			(scache7_cpx_data_a[149:0]), 
		.data_prev_x_			(col5_data_x_[149:0]), 
		.scan_in			(cpx_mac4_scanin), 
		.scan_out			(cpx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbr_dp cpx_mac5(
		.data_out_x_			(col5_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_cpx_data_a			(scache5_cpx_data_a[149:0]), 
		.data_prev_x_			(col6_data_x_[149:0]), 
		.scan_in			(cpx_mac5_scanin), 
		.scan_out			(cpx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	cpx_mbr_dp cpx_mac6(
		.data_out_x_			(col6_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[6]), 
		.arb_shift_a			(arb_shift_r_a_rep[6]), 
		.src_cpx_data_a			(scache6_cpx_data_a[149:0]), 
		.data_prev_x_			(col7_data_x_[149:0]), 
		.scan_in			(cpx_mac6_scanin), 
		.scan_out			(cpx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	cpx_mar_dp cpx_mac7(
		.data_out_x_			(col7_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[4]), 
		.arb_shift_a			(arb_shift_r_a[4]), 
		.src_cpx_data_a			(scache4_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac7_scanin), 
		.scan_out			(cpx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_dpsd.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_dpsd (
  cpx_spc_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  io_cpx_data_a, 
  scache0_cpx_data_a, 
  scache1_cpx_data_a, 
  scache2_cpx_data_a, 
  scache3_cpx_data_a, 
  scache4_cpx_data_a, 
  scache5_cpx_data_a, 
  scache6_cpx_data_a, 
  scache7_cpx_data_a, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:5] arb_grant_r_a_rep;
wire [7:5] arb_q0_holdbar_r_a_rep;
wire [7:5] arb_qsel0_r_a_rep;
wire [7:5] arb_qsel1_r_a_rep;
wire [7:5] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [149:0] col8_data_x_;
wire tcu_scan_en_out_8_unused;
wire tcu_pce_ov_out_8_unused;
wire ccx_aclk_out_8_unused;
wire ccx_bclk_out_8_unused;
wire cpx_mac8_scanin;
wire cpx_mac8_scanout;
wire [6:0] tcu_scan_en_out;
wire [6:0] tcu_pce_ov_out;
wire [6:0] ccx_aclk_out;
wire [6:0] ccx_bclk_out;
wire [149:0] col0_data_x_;
wire cpx_mac0_scanin;
wire cpx_mac0_scanout;
wire [149:0] col1_data_x_;
wire cpx_mac1_scanin;
wire cpx_mac1_scanout;
wire [149:0] col2_data_x_;
wire cpx_mac2_scanin;
wire cpx_mac2_scanout;
wire [149:0] col4_data_x_;
wire cpx_mac3_scanin;
wire cpx_mac3_scanout;
wire [149:0] col5_data_x_;
wire cpx_mac4_scanin;
wire cpx_mac4_scanout;
wire [149:0] col6_data_x_;
wire cpx_mac5_scanin;
wire cpx_mac5_scanout;
wire [149:0] col7_data_x_;
wire cpx_mac6_scanin;
wire cpx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire cpx_mac7_scanin;
wire cpx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [8:0] arb_grant_r_a_unused;
wire [8:0] arb_q0_holdbar_r_a_unused;
wire [8:0] arb_qsel0_r_a_unused;
wire [8:0] arb_qsel1_r_a_unused;
wire [8:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [149:0]          cpx_spc_data_x_;        // From mac4 of cpx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [8:0]             arb_grant_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_l_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_grant_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_r_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [149:0]           io_cpx_data_a;          // To mac8 of cpx_mal_dp.v
input [149:0]           scache0_cpx_data_a;     // To mac0 of cpx_mar_dp.v
input [149:0]           scache1_cpx_data_a;     // To mac1 of cpx_mbr_dp.v
input [149:0]           scache2_cpx_data_a;     // To mac2 of cpx_mbr_dp.v
input [149:0]           scache3_cpx_data_a;     // To mac3 of cpx_mbr_dp.v
input [149:0]           scache4_cpx_data_a;     // To mac4 of cpx_mcr_dp.v
input [149:0]           scache5_cpx_data_a;     // To mac5 of cpx_mbl_dp.v
input [149:0]           scache6_cpx_data_a;     // To mac6 of cpx_mbl_dp.v
input [149:0]           scache7_cpx_data_a;     // To cpx_mac7 of cpx_mbl_dp.v
// End of automatics

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;


//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  <-mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      cl       br       br       br      bl    
//                                      |                                          
//       ---buf-------------------------                                         
//      |                                                        
//      v                                                        
//    to spccore                                                   

/*
   cpx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(io_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
                           arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
        arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
                       arb_qsel1_l_a[0],arb_shift_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
        arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
                       arb_qsel1_r_a[6],arb_shift_r_a[6]};

assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
        arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from io
cpx_mal_dp cpx_mac8 (
                     // Outputs
                     .data_out_x_       (col8_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_8_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
                     .ccx_aclk_out (ccx_aclk_out_8_unused),
                     .ccx_bclk_out (ccx_bclk_out_8_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a[8]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a[8]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a[8]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a[8]),   // Templated
                     .arb_shift_a       (arb_shift_l_a[8]),        // Templated
                     .src_cpx_data_a    (io_cpx_data_a[149:0]),  // Templated
                     .scan_in(cpx_mac8_scanin),
                     .scan_out(cpx_mac8_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[0]),
                     .tcu_pce_ov (tcu_pce_ov_out[0]),
                     .ccx_aclk (ccx_aclk_out[0]),
                     .ccx_bclk (ccx_bclk_out[0])
                     );


/*
cpx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag2
cpx_mbl_dp cpx_mac0 (
                     // Outputs
                     .data_out_x_       (col0_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[0]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[0]),
                     .ccx_aclk_out (ccx_aclk_out[0]),
                     .ccx_bclk_out (ccx_bclk_out[0]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[2]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[2]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[2]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[2]),
                     .arb_shift_a       (arb_shift_l_a_rep[2]),
                     .src_cpx_data_a    (scache2_cpx_data_a[149:0]),
                     .data_prev_x_      (col8_data_x_[149:0]),
                     .scan_in(cpx_mac0_scanin),
                     .scan_out(cpx_mac0_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en (tcu_scan_en_out[1]),
                     .tcu_pce_ov (tcu_pce_ov_out[1]),
                     .ccx_aclk (ccx_aclk_out[1]),
                     .ccx_bclk (ccx_bclk_out[1])
                     );


// input from sctag0
cpx_mbl_dp cpx_mac1 (
                     // Outputs
                     .data_out_x_       (col1_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[1]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[1]),
                     .ccx_aclk_out    (ccx_aclk_out[1]),
                     .ccx_bclk_out    (ccx_bclk_out[1]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[0]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),
                     .arb_shift_a       (arb_shift_l_a_rep[0]),
                     .src_cpx_data_a    (scache0_cpx_data_a[149:0]),
                     .data_prev_x_      (col0_data_x_[149:0]),
                     .scan_in(cpx_mac1_scanin),
                     .scan_out(cpx_mac1_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[2]),
                     .tcu_pce_ov     (tcu_pce_ov_out[2]),
                     .ccx_aclk       (ccx_aclk_out[2]),
                     .ccx_bclk       (ccx_bclk_out[2])
                     );


// input from sctag3
cpx_mbl_dp cpx_mac2 (
                     // Outputs
                     .data_out_x_       (col2_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[2]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[2]),
                     .ccx_aclk_out    (ccx_aclk_out[2]),
                     .ccx_bclk_out    (ccx_bclk_out[2]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[3]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[3]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[3]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[3]),
                     .arb_shift_a       (arb_shift_l_a_rep[3]),
                     .src_cpx_data_a    (scache3_cpx_data_a[149:0]),
                     .data_prev_x_      (col1_data_x_[149:0]),
                     .scan_in(cpx_mac2_scanin),
                     .scan_out(cpx_mac2_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );


/*
   cpx_mcl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(cpx_spc_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag1
cpx_mcl_dp cpx_mac3 (
                     // Outputs
                     .data_out_x_       (cpx_spc_data_x_[149:0]), // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[3]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[3]),
                     .ccx_aclk_out    (ccx_aclk_out[3]),
                     .ccx_bclk_out    (ccx_bclk_out[3]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[1]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[1]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[1]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[1]),   // Templated
                     .arb_shift_a       (arb_shift_l_a_rep[1]),        // Templated
                     .src_cpx_data_a    (scache1_cpx_data_a[149:0]), // Templated
                     .data_crit_x_      (col4_data_x_[149:0]),   // Templated
                     .data_ncrit_x_     (col2_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac3_scanin),
                     .scan_out(cpx_mac3_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en),
                     .tcu_pce_ov     (tcu_pce_ov),
                     .ccx_aclk       (ccx_aclk),
                     .ccx_bclk       (ccx_bclk)
                     );


/*
   cpx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a_rep[@]),
 .arb_qsel0_a(arb_qsel0_l_a_rep[@]),
 .arb_qsel1_a(arb_qsel1_l_a_rep[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a_rep[@]),
 .arb_shift_a(arb_shift_l_a_rep[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag7
cpx_mbr_dp cpx_mac4 (
                     // Outputs
                     .data_out_x_       (col4_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[4]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[4]),
                     .ccx_aclk_out    (ccx_aclk_out[4]),
                     .ccx_bclk_out    (ccx_bclk_out[4]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[7]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[7]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[7]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[7]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[7]),        // Templated
                     .src_cpx_data_a    (scache7_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col5_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac4_scanin),
                     .scan_out(cpx_mac4_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );


// input from sctag5
cpx_mbr_dp cpx_mac5 (
                     // Outputs
                     .data_out_x_       (col5_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[5]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[5]),
                     .ccx_aclk_out    (ccx_aclk_out[5]),
                     .ccx_bclk_out    (ccx_bclk_out[5]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[5]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[5]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[5]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[5]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[5]),        // Templated
                     .src_cpx_data_a    (scache5_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col6_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac5_scanin),
                     .scan_out(cpx_mac5_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[4]),
                     .tcu_pce_ov     (tcu_pce_ov_out[4]),
                     .ccx_aclk       (ccx_aclk_out[4]),
                     .ccx_bclk       (ccx_bclk_out[4])
                     );

// input from sctag6
cpx_mbr_dp cpx_mac6 (
                     // Outputs
                     .data_out_x_       (col6_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[6]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[6]),
                     .ccx_aclk_out    (ccx_aclk_out[6]),
                     .ccx_bclk_out    (ccx_bclk_out[6]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[6]),        // Templated
                     .src_cpx_data_a    (scache6_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col7_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac6_scanin),
                     .scan_out(cpx_mac6_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[5]),
                     .tcu_pce_ov     (tcu_pce_ov_out[5]),
                     .ccx_aclk       (ccx_aclk_out[5]),
                     .ccx_bclk       (ccx_bclk_out[5])
                     );

/*
 cpx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag4
cpx_mar_dp cpx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out  (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out    (ccx_aclk_out_7_unused),
                     .ccx_bclk_out    (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[4]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[4]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[4]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[4]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[4]),        // Templated
                     .src_cpx_data_a    (scache4_cpx_data_a[149:0]), // Templated
                     .scan_in(cpx_mac7_scanin),
                     .scan_out(cpx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[6]),
                     .tcu_pce_ov     (tcu_pce_ov_out[6]),
                     .ccx_aclk       (ccx_aclk_out[6]),
                     .ccx_bclk       (ccx_bclk_out[6])
                     );
 

assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];

// fixscan start:
assign cpx_mac8_scanin           = scan_rep_out                  ;
assign cpx_mac0_scanin           = cpx_mac8_scanout         ;
assign cpx_mac1_scanin           = cpx_mac0_scanout         ;
assign cpx_mac2_scanin           = cpx_mac1_scanout         ;
assign cpx_mac3_scanin           = cpx_mac2_scanout         ;
assign cpx_mac4_scanin           = cpx_mac3_scanout         ;
assign cpx_mac5_scanin           = cpx_mac4_scanout         ;
assign cpx_mac6_scanin           = cpx_mac5_scanout         ;
assign cpx_mac7_scanin           = cpx_mac6_scanout         ;
assign scan_out                  = cpx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module cpx_dpsd_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsd_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsd_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_dpsd_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsd_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsd_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsd_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsd_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[49:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_dpsd(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a, 
	scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a, 
	scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
	l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[149:0]		cpx_spc_data_x_;
	input	[8:0]		arb_grant_l_a;
	input	[8:0]		arb_q0_holdbar_l_a;
	input	[8:0]		arb_qsel0_l_a;
	input	[8:0]		arb_qsel1_l_a;
	input	[8:0]		arb_shift_l_a;
	input	[8:0]		arb_grant_r_a;
	input	[8:0]		arb_q0_holdbar_r_a;
	input	[8:0]		arb_qsel0_r_a;
	input	[8:0]		arb_qsel1_r_a;
	input	[8:0]		arb_shift_r_a;
	input	[149:0]		io_cpx_data_a;
	input	[149:0]		scache0_cpx_data_a;
	input	[149:0]		scache1_cpx_data_a;
	input	[149:0]		scache2_cpx_data_a;
	input	[149:0]		scache3_cpx_data_a;
	input	[149:0]		scache4_cpx_data_a;
	input	[149:0]		scache5_cpx_data_a;
	input	[149:0]		scache6_cpx_data_a;
	input	[149:0]		scache7_cpx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:5]		arb_grant_r_a_rep;
	wire	[7:5]		arb_q0_holdbar_r_a_rep;
	wire	[7:5]		arb_qsel0_r_a_rep;
	wire	[7:5]		arb_qsel1_r_a_rep;
	wire	[7:5]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[149:0]		col8_data_x_;
	wire			tcu_scan_en_out_8_unused;
	wire			tcu_pce_ov_out_8_unused;
	wire			ccx_aclk_out_8_unused;
	wire			ccx_bclk_out_8_unused;
	wire			cpx_mac8_scanin;
	wire			cpx_mac8_scanout;
	wire	[6:0]		tcu_scan_en_out;
	wire	[6:0]		tcu_pce_ov_out;
	wire	[6:0]		ccx_aclk_out;
	wire	[6:0]		ccx_bclk_out;
	wire	[149:0]		col0_data_x_;
	wire			cpx_mac0_scanin;
	wire			cpx_mac0_scanout;
	wire	[149:0]		col1_data_x_;
	wire			cpx_mac1_scanin;
	wire			cpx_mac1_scanout;
	wire	[149:0]		col2_data_x_;
	wire			cpx_mac2_scanin;
	wire			cpx_mac2_scanout;
	wire	[149:0]		col4_data_x_;
	wire			cpx_mac3_scanin;
	wire			cpx_mac3_scanout;
	wire	[149:0]		col5_data_x_;
	wire			cpx_mac4_scanin;
	wire			cpx_mac4_scanout;
	wire	[149:0]		col6_data_x_;
	wire			cpx_mac5_scanin;
	wire			cpx_mac5_scanout;
	wire	[149:0]		col7_data_x_;
	wire			cpx_mac6_scanin;
	wire			cpx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			cpx_mac7_scanin;
	wire			cpx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[8:0]		arb_grant_r_a_unused;
	wire	[8:0]		arb_q0_holdbar_r_a_unused;
	wire	[8:0]		arb_qsel0_r_a_unused;
	wire	[8:0]		arb_qsel1_r_a_unused;
	wire	[8:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2], 
		arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2], 
		arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2], 
		arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0], 
		arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0], 
		arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6], 
		arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
	assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6], 
		arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
	assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
	assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
	assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
	assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
	assign cpx_mac8_scanin = scan_rep_out;
	assign cpx_mac0_scanin = cpx_mac8_scanout;
	assign cpx_mac1_scanin = cpx_mac0_scanout;
	assign cpx_mac2_scanin = cpx_mac1_scanout;
	assign cpx_mac3_scanin = cpx_mac2_scanout;
	assign cpx_mac4_scanin = cpx_mac3_scanout;
	assign cpx_mac5_scanin = cpx_mac4_scanout;
	assign cpx_mac6_scanin = cpx_mac5_scanout;
	assign cpx_mac7_scanin = cpx_mac6_scanout;
	assign scan_out = cpx_mac7_scanout;

	cpx_rep_dp cpx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	cpx_mal_dp cpx_mac8(
		.data_out_x_			(col8_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_8_unused), 
		.ccx_aclk_out			(ccx_aclk_out_8_unused), 
		.ccx_bclk_out			(ccx_bclk_out_8_unused), 
		.arb_grant_a			(arb_grant_l_a[8]), 
		.arb_qsel0_a			(arb_qsel0_l_a[8]), 
		.arb_qsel1_a			(arb_qsel1_l_a[8]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a[8]), 
		.arb_shift_a			(arb_shift_l_a[8]), 
		.src_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac8_scanin), 
		.scan_out			(cpx_mac8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[0]), 
		.tcu_pce_ov			(tcu_pce_ov_out[0]), 
		.ccx_aclk			(ccx_aclk_out[0]), 
		.ccx_bclk			(ccx_bclk_out[0]));
	cpx_mbl_dp cpx_mac0(
		.data_out_x_			(col0_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[0]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[0]), 
		.ccx_aclk_out			(ccx_aclk_out[0]), 
		.ccx_bclk_out			(ccx_bclk_out[0]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_cpx_data_a			(scache2_cpx_data_a[149:0]), 
		.data_prev_x_			(col8_data_x_[149:0]), 
		.scan_in			(cpx_mac0_scanin), 
		.scan_out			(cpx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	cpx_mbl_dp cpx_mac1(
		.data_out_x_			(col1_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_cpx_data_a			(scache0_cpx_data_a[149:0]), 
		.data_prev_x_			(col0_data_x_[149:0]), 
		.scan_in			(cpx_mac1_scanin), 
		.scan_out			(cpx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	cpx_mbl_dp cpx_mac2(
		.data_out_x_			(col2_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_cpx_data_a			(scache3_cpx_data_a[149:0]), 
		.data_prev_x_			(col1_data_x_[149:0]), 
		.scan_in			(cpx_mac2_scanin), 
		.scan_out			(cpx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mcl_dp cpx_mac3(
		.data_out_x_			(cpx_spc_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_cpx_data_a			(scache1_cpx_data_a[149:0]), 
		.data_crit_x_			(col4_data_x_[149:0]), 
		.data_ncrit_x_			(col2_data_x_[149:0]), 
		.scan_in			(cpx_mac3_scanin), 
		.scan_out			(cpx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	cpx_mbr_dp cpx_mac4(
		.data_out_x_			(col4_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_cpx_data_a			(scache7_cpx_data_a[149:0]), 
		.data_prev_x_			(col5_data_x_[149:0]), 
		.scan_in			(cpx_mac4_scanin), 
		.scan_out			(cpx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbr_dp cpx_mac5(
		.data_out_x_			(col5_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_cpx_data_a			(scache5_cpx_data_a[149:0]), 
		.data_prev_x_			(col6_data_x_[149:0]), 
		.scan_in			(cpx_mac5_scanin), 
		.scan_out			(cpx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	cpx_mbr_dp cpx_mac6(
		.data_out_x_			(col6_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[6]), 
		.arb_shift_a			(arb_shift_r_a_rep[6]), 
		.src_cpx_data_a			(scache6_cpx_data_a[149:0]), 
		.data_prev_x_			(col7_data_x_[149:0]), 
		.scan_in			(cpx_mac6_scanin), 
		.scan_out			(cpx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	cpx_mar_dp cpx_mac7(
		.data_out_x_			(col7_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[4]), 
		.arb_shift_a			(arb_shift_r_a[4]), 
		.src_cpx_data_a			(scache4_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac7_scanin), 
		.scan_out			(cpx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_dpse.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_dpse (
  cpx_spc_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  io_cpx_data_a, 
  scache0_cpx_data_a, 
  scache1_cpx_data_a, 
  scache2_cpx_data_a, 
  scache3_cpx_data_a, 
  scache4_cpx_data_a, 
  scache5_cpx_data_a, 
  scache6_cpx_data_a, 
  scache7_cpx_data_a, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:5] arb_grant_r_a_rep;
wire [7:5] arb_q0_holdbar_r_a_rep;
wire [7:5] arb_qsel0_r_a_rep;
wire [7:5] arb_qsel1_r_a_rep;
wire [7:5] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [149:0] col8_data_x_;
wire tcu_scan_en_out_8_unused;
wire tcu_pce_ov_out_8_unused;
wire ccx_aclk_out_8_unused;
wire ccx_bclk_out_8_unused;
wire cpx_mac8_scanin;
wire cpx_mac8_scanout;
wire [6:0] tcu_scan_en_out;
wire [6:0] tcu_pce_ov_out;
wire [6:0] ccx_aclk_out;
wire [6:0] ccx_bclk_out;
wire [149:0] col0_data_x_;
wire cpx_mac0_scanin;
wire cpx_mac0_scanout;
wire [149:0] col1_data_x_;
wire cpx_mac1_scanin;
wire cpx_mac1_scanout;
wire [149:0] col2_data_x_;
wire cpx_mac2_scanin;
wire cpx_mac2_scanout;
wire [149:0] col3_data_x_;
wire cpx_mac3_scanin;
wire cpx_mac3_scanout;
wire [149:0] col5_data_x_;
wire cpx_mac4_scanin;
wire cpx_mac4_scanout;
wire [149:0] col6_data_x_;
wire cpx_mac5_scanin;
wire cpx_mac5_scanout;
wire [149:0] col7_data_x_;
wire cpx_mac6_scanin;
wire cpx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire cpx_mac7_scanin;
wire cpx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [8:0] arb_grant_r_a_unused;
wire [8:0] arb_q0_holdbar_r_a_unused;
wire [8:0] arb_qsel0_r_a_unused;
wire [8:0] arb_qsel1_r_a_unused;
wire [8:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [149:0]          cpx_spc_data_x_;        // From mac4 of cpx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [8:0]             arb_grant_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_l_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_grant_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_r_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [149:0]           io_cpx_data_a;          // To mac8 of cpx_mal_dp.v
input [149:0]           scache0_cpx_data_a;     // To mac0 of cpx_mar_dp.v
input [149:0]           scache1_cpx_data_a;     // To mac1 of cpx_mbr_dp.v
input [149:0]           scache2_cpx_data_a;     // To mac2 of cpx_mbr_dp.v
input [149:0]           scache3_cpx_data_a;     // To mac3 of cpx_mbr_dp.v
input [149:0]           scache4_cpx_data_a;     // To mac4 of cpx_mcr_dp.v
input [149:0]           scache5_cpx_data_a;     // To mac5 of cpx_mbl_dp.v
input [149:0]           scache6_cpx_data_a;     // To mac6 of cpx_mbl_dp.v
input [149:0]           scache7_cpx_data_a;     // To cpx_mac7 of cpx_mbl_dp.v
// End of automatics

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  <-mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      bl       cl       br       br      bl    
//                                                |                              
//                   ---buf-----------------------                             
//                  |                                            
//                  v                                            
//                to spccore                                       

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
                           arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
        arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
                       arb_qsel1_l_a[0],arb_shift_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
        arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
                       arb_qsel1_r_a[6],arb_shift_r_a[6]};

assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
        arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );

/*
   cpx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(io_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from io
cpx_mal_dp cpx_mac8 (
                     // Outputs
                     .data_out_x_       (col8_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_8_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
                     .ccx_aclk_out (ccx_aclk_out_8_unused),
                     .ccx_bclk_out (ccx_bclk_out_8_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a[8]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a[8]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a[8]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a[8]),   // Templated
                     .arb_shift_a       (arb_shift_l_a[8]),        // Templated
                     .src_cpx_data_a    (io_cpx_data_a[149:0]),  // Templated
                     .scan_in(cpx_mac8_scanin),
                     .scan_out(cpx_mac8_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[0]),
                     .tcu_pce_ov (tcu_pce_ov_out[0]),
                     .ccx_aclk (ccx_aclk_out[0]),
                     .ccx_bclk (ccx_bclk_out[0])
                     );


/*
cpx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag2
cpx_mbl_dp cpx_mac0 (
                     // Outputs
                     .data_out_x_       (col0_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[0]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[0]),
                     .ccx_aclk_out (ccx_aclk_out[0]),
                     .ccx_bclk_out (ccx_bclk_out[0]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[2]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[2]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[2]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[2]),
                     .arb_shift_a       (arb_shift_l_a_rep[2]),
                     .src_cpx_data_a    (scache2_cpx_data_a[149:0]),
                     .data_prev_x_      (col8_data_x_[149:0]),
                     .scan_in(cpx_mac0_scanin),
                     .scan_out(cpx_mac0_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en (tcu_scan_en_out[1]),
                     .tcu_pce_ov (tcu_pce_ov_out[1]),
                     .ccx_aclk (ccx_aclk_out[1]),
                     .ccx_bclk (ccx_bclk_out[1])
                     );


// input from sctag0
cpx_mbl_dp cpx_mac1 (
                     // Outputs
                     .data_out_x_       (col1_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[1]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[1]),
                     .ccx_aclk_out    (ccx_aclk_out[1]),
                     .ccx_bclk_out    (ccx_bclk_out[1]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[0]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),
                     .arb_shift_a       (arb_shift_l_a_rep[0]),
                     .src_cpx_data_a    (scache0_cpx_data_a[149:0]),
                     .data_prev_x_      (col0_data_x_[149:0]),
                     .scan_in(cpx_mac1_scanin),
                     .scan_out(cpx_mac1_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[2]),
                     .tcu_pce_ov     (tcu_pce_ov_out[2]),
                     .ccx_aclk       (ccx_aclk_out[2]),
                     .ccx_bclk       (ccx_bclk_out[2])
                     );


// input from sctag3
cpx_mbl_dp cpx_mac2 (
                     // Outputs
                     .data_out_x_       (col2_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[2]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[2]),
                     .ccx_aclk_out    (ccx_aclk_out[2]),
                     .ccx_bclk_out    (ccx_bclk_out[2]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[3]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[3]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[3]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[3]),
                     .arb_shift_a       (arb_shift_l_a_rep[3]),
                     .src_cpx_data_a    (scache3_cpx_data_a[149:0]),
                     .data_prev_x_      (col1_data_x_[149:0]),
                     .scan_in(cpx_mac2_scanin),
                     .scan_out(cpx_mac2_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );

// input from sctag1
cpx_mbl_dp cpx_mac3 (
                     // Outputs
                     .data_out_x_       (col3_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[3]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[3]),
                     .ccx_aclk_out    (ccx_aclk_out[3]),
                     .ccx_bclk_out    (ccx_bclk_out[3]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[1]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[1]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[1]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[1]),
                     .arb_shift_a       (arb_shift_l_a_rep[1]),
                     .src_cpx_data_a    (scache1_cpx_data_a[149:0]),
                     .data_prev_x_      (col2_data_x_[149:0]),
                     .scan_in(cpx_mac3_scanin),
                     .scan_out(cpx_mac3_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en),
                     .tcu_pce_ov     (tcu_pce_ov),
                     .ccx_aclk       (ccx_aclk),
                     .ccx_bclk       (ccx_bclk)
                     );


/*
   cpx_mcr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(cpx_spc_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag7
cpx_mcr_dp cpx_mac4 (
                     // Outputs
                     .data_out_x_       (cpx_spc_data_x_[149:0]), // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[4]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[4]),
                     .ccx_aclk_out    (ccx_aclk_out[4]),
                     .ccx_bclk_out    (ccx_bclk_out[4]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[7]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[7]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[7]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[7]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[7]),        // Templated
                     .src_cpx_data_a    (scache7_cpx_data_a[149:0]), // Templated
                     .data_crit_x_      (col3_data_x_[149:0]),   // Templated
                     .data_ncrit_x_     (col5_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac4_scanin),
                     .scan_out(cpx_mac4_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );


/*
   cpx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag5
cpx_mbr_dp cpx_mac5 (
                     // Outputs
                     .data_out_x_       (col5_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[5]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[5]),
                     .ccx_aclk_out    (ccx_aclk_out[5]),
                     .ccx_bclk_out    (ccx_bclk_out[5]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[5]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[5]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[5]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[5]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[5]),        // Templated
                     .src_cpx_data_a    (scache5_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col6_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac5_scanin),
                     .scan_out(cpx_mac5_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[4]),
                     .tcu_pce_ov     (tcu_pce_ov_out[4]),
                     .ccx_aclk       (ccx_aclk_out[4]),
                     .ccx_bclk       (ccx_bclk_out[4])
                     );
 
// input from sctag6
cpx_mbr_dp cpx_mac6 (
                     // Outputs
                     .data_out_x_       (col6_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[6]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[6]),
                     .ccx_aclk_out    (ccx_aclk_out[6]),
                     .ccx_bclk_out    (ccx_bclk_out[6]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[6]),        // Templated
                     .src_cpx_data_a    (scache6_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col7_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac6_scanin),
                     .scan_out(cpx_mac6_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[5]),
                     .tcu_pce_ov     (tcu_pce_ov_out[5]),
                     .ccx_aclk       (ccx_aclk_out[5]),
                     .ccx_bclk       (ccx_bclk_out[5])
                     );
 
/*
   cpx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag4
cpx_mar_dp cpx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out  (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out    (ccx_aclk_out_7_unused),
                     .ccx_bclk_out    (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[4]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[4]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[4]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[4]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[4]),        // Templated
                     .src_cpx_data_a    (scache4_cpx_data_a[149:0]), // Templated
                     .scan_in(cpx_mac7_scanin),
                     .scan_out(cpx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[6]),
                     .tcu_pce_ov     (tcu_pce_ov_out[6]),
                     .ccx_aclk       (ccx_aclk_out[6]),
                     .ccx_bclk       (ccx_bclk_out[6])
                     );


assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];

// fixscan start:
assign cpx_mac8_scanin           = scan_rep_out                  ;
assign cpx_mac0_scanin           = cpx_mac8_scanout         ;
assign cpx_mac1_scanin           = cpx_mac0_scanout         ;
assign cpx_mac2_scanin           = cpx_mac1_scanout         ;
assign cpx_mac3_scanin           = cpx_mac2_scanout         ;
assign cpx_mac4_scanin           = cpx_mac3_scanout         ;
assign cpx_mac5_scanin           = cpx_mac4_scanout         ;
assign cpx_mac6_scanin           = cpx_mac5_scanout         ;
assign cpx_mac7_scanin           = cpx_mac6_scanout         ;
assign scan_out                  = cpx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module cpx_dpse_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpse_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpse_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_dpse_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_dpse_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpse_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[49:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[149:100]),
// .din1	(data_crit_x_[149:100]),
// .din2	(data_ncrit_x_[149:100]),
// .dout	(data_out_x[149:100])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[99:50]),
// .din1	(data_crit_x_[99:50]),
// .din2	(data_ncrit_x_[99:50]),
// .dout	(data_out_x[99:50])
//);
//
//nand_macro i_nand_data_crit_0 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[49:0]),
// .din1	(data_crit_x_[49:0]),
// .din2	(data_ncrit_x_[49:0]),
// .dout	(data_out_x[49:0])
//);
//
//inv_macro i_inv_data_out_2 (width=50, stack=50c) 
//(
// .din	(data_out_x[149:100]),
// .dout	(data_out_x_[149:100])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[99:50]),
// .dout	(data_out_x_[99:50])
// );
//
//inv_macro i_inv_data_out_0 (width=50, stack=50c) 
//(
// .din	(data_out_x[49:0]),
// .dout	(data_out_x_[49:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule


//
//   ccx macro
//
//


module cpx_dpse_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpse_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[49:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_dpse(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a, 
	scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a, 
	scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
	l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[149:0]		cpx_spc_data_x_;
	input	[8:0]		arb_grant_l_a;
	input	[8:0]		arb_q0_holdbar_l_a;
	input	[8:0]		arb_qsel0_l_a;
	input	[8:0]		arb_qsel1_l_a;
	input	[8:0]		arb_shift_l_a;
	input	[8:0]		arb_grant_r_a;
	input	[8:0]		arb_q0_holdbar_r_a;
	input	[8:0]		arb_qsel0_r_a;
	input	[8:0]		arb_qsel1_r_a;
	input	[8:0]		arb_shift_r_a;
	input	[149:0]		io_cpx_data_a;
	input	[149:0]		scache0_cpx_data_a;
	input	[149:0]		scache1_cpx_data_a;
	input	[149:0]		scache2_cpx_data_a;
	input	[149:0]		scache3_cpx_data_a;
	input	[149:0]		scache4_cpx_data_a;
	input	[149:0]		scache5_cpx_data_a;
	input	[149:0]		scache6_cpx_data_a;
	input	[149:0]		scache7_cpx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:5]		arb_grant_r_a_rep;
	wire	[7:5]		arb_q0_holdbar_r_a_rep;
	wire	[7:5]		arb_qsel0_r_a_rep;
	wire	[7:5]		arb_qsel1_r_a_rep;
	wire	[7:5]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[149:0]		col8_data_x_;
	wire			tcu_scan_en_out_8_unused;
	wire			tcu_pce_ov_out_8_unused;
	wire			ccx_aclk_out_8_unused;
	wire			ccx_bclk_out_8_unused;
	wire			cpx_mac8_scanin;
	wire			cpx_mac8_scanout;
	wire	[6:0]		tcu_scan_en_out;
	wire	[6:0]		tcu_pce_ov_out;
	wire	[6:0]		ccx_aclk_out;
	wire	[6:0]		ccx_bclk_out;
	wire	[149:0]		col0_data_x_;
	wire			cpx_mac0_scanin;
	wire			cpx_mac0_scanout;
	wire	[149:0]		col1_data_x_;
	wire			cpx_mac1_scanin;
	wire			cpx_mac1_scanout;
	wire	[149:0]		col2_data_x_;
	wire			cpx_mac2_scanin;
	wire			cpx_mac2_scanout;
	wire	[149:0]		col3_data_x_;
	wire			cpx_mac3_scanin;
	wire			cpx_mac3_scanout;
	wire	[149:0]		col5_data_x_;
	wire			cpx_mac4_scanin;
	wire			cpx_mac4_scanout;
	wire	[149:0]		col6_data_x_;
	wire			cpx_mac5_scanin;
	wire			cpx_mac5_scanout;
	wire	[149:0]		col7_data_x_;
	wire			cpx_mac6_scanin;
	wire			cpx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			cpx_mac7_scanin;
	wire			cpx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[8:0]		arb_grant_r_a_unused;
	wire	[8:0]		arb_q0_holdbar_r_a_unused;
	wire	[8:0]		arb_qsel0_r_a_unused;
	wire	[8:0]		arb_qsel1_r_a_unused;
	wire	[8:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2], 
		arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2], 
		arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2], 
		arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0], 
		arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0], 
		arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6], 
		arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
	assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6], 
		arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
	assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
	assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
	assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
	assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
	assign cpx_mac8_scanin = scan_rep_out;
	assign cpx_mac0_scanin = cpx_mac8_scanout;
	assign cpx_mac1_scanin = cpx_mac0_scanout;
	assign cpx_mac2_scanin = cpx_mac1_scanout;
	assign cpx_mac3_scanin = cpx_mac2_scanout;
	assign cpx_mac4_scanin = cpx_mac3_scanout;
	assign cpx_mac5_scanin = cpx_mac4_scanout;
	assign cpx_mac6_scanin = cpx_mac5_scanout;
	assign cpx_mac7_scanin = cpx_mac6_scanout;
	assign scan_out = cpx_mac7_scanout;

	cpx_rep_dp cpx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	cpx_mal_dp cpx_mac8(
		.data_out_x_			(col8_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_8_unused), 
		.ccx_aclk_out			(ccx_aclk_out_8_unused), 
		.ccx_bclk_out			(ccx_bclk_out_8_unused), 
		.arb_grant_a			(arb_grant_l_a[8]), 
		.arb_qsel0_a			(arb_qsel0_l_a[8]), 
		.arb_qsel1_a			(arb_qsel1_l_a[8]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a[8]), 
		.arb_shift_a			(arb_shift_l_a[8]), 
		.src_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac8_scanin), 
		.scan_out			(cpx_mac8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[0]), 
		.tcu_pce_ov			(tcu_pce_ov_out[0]), 
		.ccx_aclk			(ccx_aclk_out[0]), 
		.ccx_bclk			(ccx_bclk_out[0]));
	cpx_mbl_dp cpx_mac0(
		.data_out_x_			(col0_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[0]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[0]), 
		.ccx_aclk_out			(ccx_aclk_out[0]), 
		.ccx_bclk_out			(ccx_bclk_out[0]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_cpx_data_a			(scache2_cpx_data_a[149:0]), 
		.data_prev_x_			(col8_data_x_[149:0]), 
		.scan_in			(cpx_mac0_scanin), 
		.scan_out			(cpx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	cpx_mbl_dp cpx_mac1(
		.data_out_x_			(col1_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_cpx_data_a			(scache0_cpx_data_a[149:0]), 
		.data_prev_x_			(col0_data_x_[149:0]), 
		.scan_in			(cpx_mac1_scanin), 
		.scan_out			(cpx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	cpx_mbl_dp cpx_mac2(
		.data_out_x_			(col2_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_cpx_data_a			(scache3_cpx_data_a[149:0]), 
		.data_prev_x_			(col1_data_x_[149:0]), 
		.scan_in			(cpx_mac2_scanin), 
		.scan_out			(cpx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbl_dp cpx_mac3(
		.data_out_x_			(col3_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_cpx_data_a			(scache1_cpx_data_a[149:0]), 
		.data_prev_x_			(col2_data_x_[149:0]), 
		.scan_in			(cpx_mac3_scanin), 
		.scan_out			(cpx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	cpx_mcr_dp cpx_mac4(
		.data_out_x_			(cpx_spc_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_cpx_data_a			(scache7_cpx_data_a[149:0]), 
		.data_crit_x_			(col3_data_x_[149:0]), 
		.data_ncrit_x_			(col5_data_x_[149:0]), 
		.scan_in			(cpx_mac4_scanin), 
		.scan_out			(cpx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbr_dp cpx_mac5(
		.data_out_x_			(col5_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_cpx_data_a			(scache5_cpx_data_a[149:0]), 
		.data_prev_x_			(col6_data_x_[149:0]), 
		.scan_in			(cpx_mac5_scanin), 
		.scan_out			(cpx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	cpx_mbr_dp cpx_mac6(
		.data_out_x_			(col6_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[6]), 
		.arb_shift_a			(arb_shift_r_a_rep[6]), 
		.src_cpx_data_a			(scache6_cpx_data_a[149:0]), 
		.data_prev_x_			(col7_data_x_[149:0]), 
		.scan_in			(cpx_mac6_scanin), 
		.scan_out			(cpx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	cpx_mar_dp cpx_mac7(
		.data_out_x_			(col7_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[4]), 
		.arb_shift_a			(arb_shift_r_a[4]), 
		.src_cpx_data_a			(scache4_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac7_scanin), 
		.scan_out			(cpx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_dpsf.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_dpsf (
  cpx_spc_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  io_cpx_data_a, 
  scache0_cpx_data_a, 
  scache1_cpx_data_a, 
  scache2_cpx_data_a, 
  scache3_cpx_data_a, 
  scache4_cpx_data_a, 
  scache5_cpx_data_a, 
  scache6_cpx_data_a, 
  scache7_cpx_data_a, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:5] arb_grant_r_a_rep;
wire [7:5] arb_q0_holdbar_r_a_rep;
wire [7:5] arb_qsel0_r_a_rep;
wire [7:5] arb_qsel1_r_a_rep;
wire [7:5] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [149:0] col8_data_x_;
wire tcu_scan_en_out_8_unused;
wire tcu_pce_ov_out_8_unused;
wire ccx_aclk_out_8_unused;
wire ccx_bclk_out_8_unused;
wire cpx_mac8_scanin;
wire cpx_mac8_scanout;
wire [6:0] tcu_scan_en_out;
wire [6:0] tcu_pce_ov_out;
wire [6:0] ccx_aclk_out;
wire [6:0] ccx_bclk_out;
wire [149:0] col0_data_x_;
wire cpx_mac0_scanin;
wire cpx_mac0_scanout;
wire [149:0] col1_data_x_;
wire cpx_mac1_scanin;
wire cpx_mac1_scanout;
wire [149:0] col2_data_x_;
wire cpx_mac2_scanin;
wire cpx_mac2_scanout;
wire [149:0] col3_data_x_;
wire cpx_mac3_scanin;
wire cpx_mac3_scanout;
wire [149:0] col4_data_x_;
wire cpx_mac4_scanin;
wire cpx_mac4_scanout;
wire [149:0] col6_data_x_;
wire cpx_mac5_scanin;
wire cpx_mac5_scanout;
wire [149:0] col7_data_x_;
wire cpx_mac6_scanin;
wire cpx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire cpx_mac7_scanin;
wire cpx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [8:0] arb_grant_r_a_unused;
wire [8:0] arb_q0_holdbar_r_a_unused;
wire [8:0] arb_qsel0_r_a_unused;
wire [8:0] arb_qsel1_r_a_unused;
wire [8:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [149:0]          cpx_spc_data_x_;        // From mac4 of cpx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [8:0]             arb_grant_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_l_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_grant_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_r_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [149:0]           io_cpx_data_a;          // To mac8 of cpx_mal_dp.v
input [149:0]           scache0_cpx_data_a;     // To mac0 of cpx_mar_dp.v
input [149:0]           scache1_cpx_data_a;     // To mac1 of cpx_mbr_dp.v
input [149:0]           scache2_cpx_data_a;     // To mac2 of cpx_mbr_dp.v
input [149:0]           scache3_cpx_data_a;     // To mac3 of cpx_mbr_dp.v
input [149:0]           scache4_cpx_data_a;     // To mac4 of cpx_mcr_dp.v
input [149:0]           scache5_cpx_data_a;     // To mac5 of cpx_mbl_dp.v
input [149:0]           scache6_cpx_data_a;     // To mac6 of cpx_mbl_dp.v
input [149:0]           scache7_cpx_data_a;     // To cpx_mac7 of cpx_mbl_dp.v
// End of automatics

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;


//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  <-mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      bl       bl       cr       br      bl    
//                                                        |                              
//                   ---buf-------------------------------                             
//                  |                                            
//                  v                                            
//                to spccore                                       

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
                           arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
        arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
                       arb_qsel1_l_a[0],arb_shift_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
        arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
                       arb_qsel1_r_a[6],arb_shift_r_a[6]};

assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
        arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );

/*
   cpx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(io_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from io
cpx_mal_dp cpx_mac8 (
                     // Outputs
                     .data_out_x_       (col8_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_8_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
                     .ccx_aclk_out (ccx_aclk_out_8_unused),
                     .ccx_bclk_out (ccx_bclk_out_8_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a[8]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a[8]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a[8]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a[8]),   // Templated
                     .arb_shift_a       (arb_shift_l_a[8]),        // Templated
                     .src_cpx_data_a    (io_cpx_data_a[149:0]),  // Templated
                     .scan_in(cpx_mac8_scanin),
                     .scan_out(cpx_mac8_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[0]),
                     .tcu_pce_ov (tcu_pce_ov_out[0]),
                     .ccx_aclk (ccx_aclk_out[0]),
                     .ccx_bclk (ccx_bclk_out[0])
                     );


/*
cpx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag2
cpx_mbl_dp cpx_mac0 (
                     // Outputs
                     .data_out_x_       (col0_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[0]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[0]),
                     .ccx_aclk_out (ccx_aclk_out[0]),
                     .ccx_bclk_out (ccx_bclk_out[0]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[2]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[2]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[2]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[2]),
                     .arb_shift_a       (arb_shift_l_a_rep[2]),
                     .src_cpx_data_a    (scache2_cpx_data_a[149:0]),
                     .data_prev_x_      (col8_data_x_[149:0]),
                     .scan_in(cpx_mac0_scanin),
                     .scan_out(cpx_mac0_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en (tcu_scan_en_out[1]),
                     .tcu_pce_ov (tcu_pce_ov_out[1]),
                     .ccx_aclk (ccx_aclk_out[1]),
                     .ccx_bclk (ccx_bclk_out[1])
                     );


// input from sctag0
cpx_mbl_dp cpx_mac1 (
                     // Outputs
                     .data_out_x_       (col1_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[1]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[1]),
                     .ccx_aclk_out    (ccx_aclk_out[1]),
                     .ccx_bclk_out    (ccx_bclk_out[1]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[0]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),
                     .arb_shift_a       (arb_shift_l_a_rep[0]),
                     .src_cpx_data_a    (scache0_cpx_data_a[149:0]),
                     .data_prev_x_      (col0_data_x_[149:0]),
                     .scan_in(cpx_mac1_scanin),
                     .scan_out(cpx_mac1_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[2]),
                     .tcu_pce_ov     (tcu_pce_ov_out[2]),
                     .ccx_aclk       (ccx_aclk_out[2]),
                     .ccx_bclk       (ccx_bclk_out[2])
                     );


// input from sctag3
cpx_mbl_dp cpx_mac2 (
                     // Outputs
                     .data_out_x_       (col2_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[2]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[2]),
                     .ccx_aclk_out    (ccx_aclk_out[2]),
                     .ccx_bclk_out    (ccx_bclk_out[2]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[3]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[3]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[3]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[3]),
                     .arb_shift_a       (arb_shift_l_a_rep[3]),
                     .src_cpx_data_a    (scache3_cpx_data_a[149:0]),
                     .data_prev_x_      (col1_data_x_[149:0]),
                     .scan_in(cpx_mac2_scanin),
                     .scan_out(cpx_mac2_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );

// input from sctag1
cpx_mbl_dp cpx_mac3 (
                     // Outputs
                     .data_out_x_       (col3_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[3]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[3]),
                     .ccx_aclk_out    (ccx_aclk_out[3]),
                     .ccx_bclk_out    (ccx_bclk_out[3]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[1]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[1]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[1]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[1]),
                     .arb_shift_a       (arb_shift_l_a_rep[1]),
                     .src_cpx_data_a    (scache1_cpx_data_a[149:0]),
                     .data_prev_x_      (col2_data_x_[149:0]),
                     .scan_in(cpx_mac3_scanin),
                     .scan_out(cpx_mac3_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en),
                     .tcu_pce_ov     (tcu_pce_ov),
                     .ccx_aclk       (ccx_aclk),
                     .ccx_bclk       (ccx_bclk)
                     );

// input from sctag7
cpx_mbl_dp cpx_mac4 (
                     // Outputs
                     .data_out_x_       (col4_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[4]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[4]),
                     .ccx_aclk_out    (ccx_aclk_out[4]),
                     .ccx_bclk_out    (ccx_bclk_out[4]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[7]),
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[7]),
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[7]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[7]),
                     .arb_shift_a       (arb_shift_r_a_rep[7]),
                     .src_cpx_data_a    (scache7_cpx_data_a[149:0]),
                     .data_prev_x_      (col3_data_x_[149:0]),
                     .scan_in(cpx_mac4_scanin),
                     .scan_out(cpx_mac4_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
);


/*
   cpx_mcr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(cpx_spc_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a_rep[@]),
 .arb_qsel0_a(arb_qsel0_l_a_rep[@]),
 .arb_qsel1_a(arb_qsel1_l_a_rep[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a_rep[@]),
 .arb_shift_a(arb_shift_l_a_rep[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag5
cpx_mcr_dp cpx_mac5 (
                     // Outputs
                     .data_out_x_       (cpx_spc_data_x_[149:0]), // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[5]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[5]),
                     .ccx_aclk_out    (ccx_aclk_out[5]),
                     .ccx_bclk_out    (ccx_bclk_out[5]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[5]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[5]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[5]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[5]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[5]),        // Templated
                     .src_cpx_data_a    (scache5_cpx_data_a[149:0]), // Templated
                     .data_crit_x_      (col4_data_x_[149:0]),   // Templated
                     .data_ncrit_x_     (col6_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac5_scanin),
                     .scan_out(cpx_mac5_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[4]),
                     .tcu_pce_ov     (tcu_pce_ov_out[4]),
                     .ccx_aclk       (ccx_aclk_out[4]),
                     .ccx_bclk       (ccx_bclk_out[4])
                     );


/*
   cpx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a_rep[@]),
 .arb_qsel0_a(arb_qsel0_l_a_rep[@]),
 .arb_qsel1_a(arb_qsel1_l_a_rep[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a_rep[@]),
 .arb_shift_a(arb_shift_l_a_rep[@]),
 .src_cpx_data_a(scache@_cpx_data_a_rep[149:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag6
cpx_mbr_dp cpx_mac6 (
                     // Outputs
                     .data_out_x_       (col6_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[6]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[6]),
                     .ccx_aclk_out    (ccx_aclk_out[6]),
                     .ccx_bclk_out    (ccx_bclk_out[6]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[6]),        // Templated
                     .src_cpx_data_a    (scache6_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (col7_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac6_scanin),
                     .scan_out(cpx_mac6_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[5]),
                     .tcu_pce_ov     (tcu_pce_ov_out[5]),
                     .ccx_aclk       (ccx_aclk_out[5]),
                     .ccx_bclk       (ccx_bclk_out[5])
                     );
 
/*
   cpx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag4
cpx_mar_dp cpx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out  (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out    (ccx_aclk_out_7_unused),
                     .ccx_bclk_out    (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[4]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[4]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[4]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[4]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[4]),        // Templated
                     .src_cpx_data_a    (scache4_cpx_data_a[149:0]), // Templated
                     .scan_in(cpx_mac7_scanin),
                     .scan_out(cpx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[6]),
                     .tcu_pce_ov     (tcu_pce_ov_out[6]),
                     .ccx_aclk       (ccx_aclk_out[6]),
                     .ccx_bclk       (ccx_bclk_out[6])
                     );
 

assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];

// fixscan start:
assign cpx_mac8_scanin           = scan_rep_out                  ;
assign cpx_mac0_scanin           = cpx_mac8_scanout         ;
assign cpx_mac1_scanin           = cpx_mac0_scanout         ;
assign cpx_mac2_scanin           = cpx_mac1_scanout         ;
assign cpx_mac3_scanin           = cpx_mac2_scanout         ;
assign cpx_mac4_scanin           = cpx_mac3_scanout         ;
assign cpx_mac5_scanin           = cpx_mac4_scanout         ;
assign cpx_mac6_scanin           = cpx_mac5_scanout         ;
assign cpx_mac7_scanin           = cpx_mac6_scanout         ;
assign scan_out                  = cpx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module cpx_dpsf_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsf_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsf_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_dpsf_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsf_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsf_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[49:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[149:100]),
// .din1	(data_crit_x_[149:100]),
// .din2	(data_ncrit_x_[149:100]),
// .dout	(data_out_x[149:100])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[99:50]),
// .din1	(data_crit_x_[99:50]),
// .din2	(data_ncrit_x_[99:50]),
// .dout	(data_out_x[99:50])
//);
//
//nand_macro i_nand_data_crit_0 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[49:0]),
// .din1	(data_crit_x_[49:0]),
// .din2	(data_ncrit_x_[49:0]),
// .dout	(data_out_x[49:0])
//);
//
//inv_macro i_inv_data_out_2 (width=50, stack=50c) 
//(
// .din	(data_out_x[149:100]),
// .dout	(data_out_x_[149:100])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[99:50]),
// .dout	(data_out_x_[99:50])
// );
//
//inv_macro i_inv_data_out_0 (width=50, stack=50c) 
//(
// .din	(data_out_x[49:0]),
// .dout	(data_out_x_[49:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule


//
//   ccx macro
//
//


module cpx_dpsf_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsf_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[49:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:

`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module cpx_dpsf(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a, 
	scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a, 
	scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
	l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[149:0]		cpx_spc_data_x_;
	input	[8:0]		arb_grant_l_a;
	input	[8:0]		arb_q0_holdbar_l_a;
	input	[8:0]		arb_qsel0_l_a;
	input	[8:0]		arb_qsel1_l_a;
	input	[8:0]		arb_shift_l_a;
	input	[8:0]		arb_grant_r_a;
	input	[8:0]		arb_q0_holdbar_r_a;
	input	[8:0]		arb_qsel0_r_a;
	input	[8:0]		arb_qsel1_r_a;
	input	[8:0]		arb_shift_r_a;
	input	[149:0]		io_cpx_data_a;
	input	[149:0]		scache0_cpx_data_a;
	input	[149:0]		scache1_cpx_data_a;
	input	[149:0]		scache2_cpx_data_a;
	input	[149:0]		scache3_cpx_data_a;
	input	[149:0]		scache4_cpx_data_a;
	input	[149:0]		scache5_cpx_data_a;
	input	[149:0]		scache6_cpx_data_a;
	input	[149:0]		scache7_cpx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:5]		arb_grant_r_a_rep;
	wire	[7:5]		arb_q0_holdbar_r_a_rep;
	wire	[7:5]		arb_qsel0_r_a_rep;
	wire	[7:5]		arb_qsel1_r_a_rep;
	wire	[7:5]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[149:0]		col8_data_x_;
	wire			tcu_scan_en_out_8_unused;
	wire			tcu_pce_ov_out_8_unused;
	wire			ccx_aclk_out_8_unused;
	wire			ccx_bclk_out_8_unused;
	wire			cpx_mac8_scanin;
	wire			cpx_mac8_scanout;
	wire	[6:0]		tcu_scan_en_out;
	wire	[6:0]		tcu_pce_ov_out;
	wire	[6:0]		ccx_aclk_out;
	wire	[6:0]		ccx_bclk_out;
	wire	[149:0]		col0_data_x_;
	wire			cpx_mac0_scanin;
	wire			cpx_mac0_scanout;
	wire	[149:0]		col1_data_x_;
	wire			cpx_mac1_scanin;
	wire			cpx_mac1_scanout;
	wire	[149:0]		col2_data_x_;
	wire			cpx_mac2_scanin;
	wire			cpx_mac2_scanout;
	wire	[149:0]		col3_data_x_;
	wire			cpx_mac3_scanin;
	wire			cpx_mac3_scanout;
	wire	[149:0]		col4_data_x_;
	wire			cpx_mac4_scanin;
	wire			cpx_mac4_scanout;
	wire	[149:0]		col6_data_x_;
	wire			cpx_mac5_scanin;
	wire			cpx_mac5_scanout;
	wire	[149:0]		col7_data_x_;
	wire			cpx_mac6_scanin;
	wire			cpx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			cpx_mac7_scanin;
	wire			cpx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[8:0]		arb_grant_r_a_unused;
	wire	[8:0]		arb_q0_holdbar_r_a_unused;
	wire	[8:0]		arb_qsel0_r_a_unused;
	wire	[8:0]		arb_qsel1_r_a_unused;
	wire	[8:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2], 
		arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2], 
		arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2], 
		arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0], 
		arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0], 
		arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6], 
		arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
	assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6], 
		arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
	assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
	assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
	assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
	assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
	assign cpx_mac8_scanin = scan_rep_out;
	assign cpx_mac0_scanin = cpx_mac8_scanout;
	assign cpx_mac1_scanin = cpx_mac0_scanout;
	assign cpx_mac2_scanin = cpx_mac1_scanout;
	assign cpx_mac3_scanin = cpx_mac2_scanout;
	assign cpx_mac4_scanin = cpx_mac3_scanout;
	assign cpx_mac5_scanin = cpx_mac4_scanout;
	assign cpx_mac6_scanin = cpx_mac5_scanout;
	assign cpx_mac7_scanin = cpx_mac6_scanout;
	assign scan_out = cpx_mac7_scanout;

	cpx_rep_dp cpx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	cpx_mal_dp cpx_mac8(
		.data_out_x_			(col8_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_8_unused), 
		.ccx_aclk_out			(ccx_aclk_out_8_unused), 
		.ccx_bclk_out			(ccx_bclk_out_8_unused), 
		.arb_grant_a			(arb_grant_l_a[8]), 
		.arb_qsel0_a			(arb_qsel0_l_a[8]), 
		.arb_qsel1_a			(arb_qsel1_l_a[8]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a[8]), 
		.arb_shift_a			(arb_shift_l_a[8]), 
		.src_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac8_scanin), 
		.scan_out			(cpx_mac8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[0]), 
		.tcu_pce_ov			(tcu_pce_ov_out[0]), 
		.ccx_aclk			(ccx_aclk_out[0]), 
		.ccx_bclk			(ccx_bclk_out[0]));
	cpx_mbl_dp cpx_mac0(
		.data_out_x_			(col0_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[0]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[0]), 
		.ccx_aclk_out			(ccx_aclk_out[0]), 
		.ccx_bclk_out			(ccx_bclk_out[0]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_cpx_data_a			(scache2_cpx_data_a[149:0]), 
		.data_prev_x_			(col8_data_x_[149:0]), 
		.scan_in			(cpx_mac0_scanin), 
		.scan_out			(cpx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	cpx_mbl_dp cpx_mac1(
		.data_out_x_			(col1_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_cpx_data_a			(scache0_cpx_data_a[149:0]), 
		.data_prev_x_			(col0_data_x_[149:0]), 
		.scan_in			(cpx_mac1_scanin), 
		.scan_out			(cpx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	cpx_mbl_dp cpx_mac2(
		.data_out_x_			(col2_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_cpx_data_a			(scache3_cpx_data_a[149:0]), 
		.data_prev_x_			(col1_data_x_[149:0]), 
		.scan_in			(cpx_mac2_scanin), 
		.scan_out			(cpx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbl_dp cpx_mac3(
		.data_out_x_			(col3_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_cpx_data_a			(scache1_cpx_data_a[149:0]), 
		.data_prev_x_			(col2_data_x_[149:0]), 
		.scan_in			(cpx_mac3_scanin), 
		.scan_out			(cpx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	cpx_mbl_dp cpx_mac4(
		.data_out_x_			(col4_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_cpx_data_a			(scache7_cpx_data_a[149:0]), 
		.data_prev_x_			(col3_data_x_[149:0]), 
		.scan_in			(cpx_mac4_scanin), 
		.scan_out			(cpx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mcr_dp cpx_mac5(
		.data_out_x_			(cpx_spc_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_cpx_data_a			(scache5_cpx_data_a[149:0]), 
		.data_crit_x_			(col4_data_x_[149:0]), 
		.data_ncrit_x_			(col6_data_x_[149:0]), 
		.scan_in			(cpx_mac5_scanin), 
		.scan_out			(cpx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	cpx_mbr_dp cpx_mac6(
		.data_out_x_			(col6_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[6]), 
		.arb_shift_a			(arb_shift_r_a_rep[6]), 
		.src_cpx_data_a			(scache6_cpx_data_a[149:0]), 
		.data_prev_x_			(col7_data_x_[149:0]), 
		.scan_in			(cpx_mac6_scanin), 
		.scan_out			(cpx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	cpx_mar_dp cpx_mac7(
		.data_out_x_			(col7_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[4]), 
		.arb_shift_a			(arb_shift_r_a[4]), 
		.src_cpx_data_a			(scache4_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac7_scanin), 
		.scan_out			(cpx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_dpsg.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_dpsg (
  cpx_spc_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  io_cpx_data_a, 
  scache0_cpx_data_a, 
  scache1_cpx_data_a, 
  scache2_cpx_data_a, 
  scache3_cpx_data_a, 
  scache4_cpx_data_a, 
  scache5_cpx_data_a, 
  scache6_cpx_data_a, 
  scache7_cpx_data_a, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [149:0] all_ones;
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:5] arb_grant_r_a_rep;
wire [7:5] arb_q0_holdbar_r_a_rep;
wire [7:5] arb_qsel0_r_a_rep;
wire [7:5] arb_qsel1_r_a_rep;
wire [7:5] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [149:0] col8_data_x_;
wire tcu_scan_en_out_8_unused;
wire tcu_pce_ov_out_8_unused;
wire ccx_aclk_out_8_unused;
wire ccx_bclk_out_8_unused;
wire cpx_mac8_scanin;
wire cpx_mac8_scanout;
wire [6:0] tcu_scan_en_out;
wire [6:0] tcu_pce_ov_out;
wire [6:0] ccx_aclk_out;
wire [6:0] ccx_bclk_out;
wire [149:0] col0_data_x_;
wire cpx_mac0_scanin;
wire cpx_mac0_scanout;
wire [149:0] col1_data_x_;
wire cpx_mac1_scanin;
wire cpx_mac1_scanout;
wire [149:0] col2_data_x_;
wire cpx_mac2_scanin;
wire cpx_mac2_scanout;
wire [149:0] col3_data_x_;
wire cpx_mac3_scanin;
wire cpx_mac3_scanout;
wire [149:0] col4_data_x_;
wire cpx_mac4_scanin;
wire cpx_mac4_scanout;
wire [149:0] col5_data_x_;
wire cpx_mac5_scanin;
wire cpx_mac5_scanout;
wire [149:0] col7_data_x_;
wire cpx_mac6_scanin;
wire cpx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire cpx_mac7_scanin;
wire cpx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [8:0] arb_grant_r_a_unused;
wire [8:0] arb_q0_holdbar_r_a_unused;
wire [8:0] arb_qsel0_r_a_unused;
wire [8:0] arb_qsel1_r_a_unused;
wire [8:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [149:0]          cpx_spc_data_x_;        // From mac4 of cpx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [8:0]             arb_grant_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_l_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_l_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_grant_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_q0_holdbar_r_a;          // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel0_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_qsel1_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [8:0]             arb_shift_r_a;            // To mac0 of cpx_mar_dp.v, ...
input [149:0]           io_cpx_data_a;          // To mac8 of cpx_mal_dp.v
input [149:0]           scache0_cpx_data_a;     // To mac0 of cpx_mar_dp.v
input [149:0]           scache1_cpx_data_a;     // To mac1 of cpx_mbr_dp.v
input [149:0]           scache2_cpx_data_a;     // To mac2 of cpx_mbr_dp.v
input [149:0]           scache3_cpx_data_a;     // To mac3 of cpx_mbr_dp.v
input [149:0]           scache4_cpx_data_a;     // To mac4 of cpx_mcr_dp.v
input [149:0]           scache5_cpx_data_a;     // To mac5 of cpx_mbl_dp.v
input [149:0]           scache6_cpx_data_a;     // To mac6 of cpx_mbl_dp.v
input [149:0]           scache7_cpx_data_a;     // To cpx_mac7 of cpx_mbl_dp.v
// End of automatics

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;


//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-> mac0 -> mac1  <-mac2 <- mac3 <-  mac4  <- mac5 <- mac6  <- mac7   
//      al       bl     bl      bl      bl       bl       bl       cl      br    
//                                                                  |                              
//                              ---buf-------------------------------                             
//                             |                                            
//                             v                                            
//                        to spccore                                       

assign all_ones[149:0] = 150'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[2],arb_qsel0_l_a[2],arb_qsel1_l_a[2],
                           arb_shift_l_a[2],arb_q0_holdbar_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_qsel0_l_a_rep[2],arb_qsel1_l_a_rep[2],
        arb_shift_l_a_rep[2],arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[0],arb_q0_holdbar_l_a[0],arb_qsel0_l_a[0],
                       arb_qsel1_l_a[0],arb_shift_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_q0_holdbar_l_a_rep[0],arb_qsel0_l_a_rep[0],
        arb_qsel1_l_a_rep[0],arb_shift_l_a_rep[0]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[6],arb_q0_holdbar_r_a[6],arb_qsel0_r_a[6],
                       arb_qsel1_r_a[6],arb_shift_r_a[6]};

assign {arb_grant_r_a_rep[6],arb_q0_holdbar_r_a_rep[6],arb_qsel0_r_a_rep[6],
        arb_qsel1_r_a_rep[6],arb_shift_r_a_rep[6]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


cpx_rep_dp cpx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );

/*
   cpx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(io_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from io
cpx_mal_dp cpx_mac8 (
                     // Outputs
                     .data_out_x_       (col8_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_8_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_8_unused),
                     .ccx_aclk_out (ccx_aclk_out_8_unused),
                     .ccx_bclk_out (ccx_bclk_out_8_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a[8]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_l_a[8]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_l_a[8]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a[8]),   // Templated
                     .arb_shift_a       (arb_shift_l_a[8]),        // Templated
                     .src_cpx_data_a    (io_cpx_data_a[149:0]),  // Templated
                     .scan_in(cpx_mac8_scanin),
                     .scan_out(cpx_mac8_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[0]),
                     .tcu_pce_ov (tcu_pce_ov_out[0]),
                     .ccx_aclk (ccx_aclk_out[0]),
                     .ccx_bclk (ccx_bclk_out[0])
                     );


/*
 cpx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/


// input from sctag2
cpx_mbl_dp cpx_mac0 (
                     // Outputs
                     .data_out_x_       (col0_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[0]),
                     .tcu_pce_ov_out (tcu_pce_ov_out[0]),
                     .ccx_aclk_out (ccx_aclk_out[0]),
                     .ccx_bclk_out (ccx_bclk_out[0]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[2]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[2]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[2]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[2]),
                     .arb_shift_a       (arb_shift_l_a_rep[2]),
                     .src_cpx_data_a    (scache2_cpx_data_a[149:0]),
                     .data_prev_x_      (col8_data_x_[149:0]),
                     .scan_in(cpx_mac0_scanin),
                     .scan_out(cpx_mac0_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en (tcu_scan_en_out[1]),
                     .tcu_pce_ov (tcu_pce_ov_out[1]),
                     .ccx_aclk (ccx_aclk_out[1]),
                     .ccx_bclk (ccx_bclk_out[1])
                     );


// input from sctag0
cpx_mbl_dp cpx_mac1 (
                     // Outputs
                     .data_out_x_       (col1_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[1]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[1]),
                     .ccx_aclk_out    (ccx_aclk_out[1]),
                     .ccx_bclk_out    (ccx_bclk_out[1]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[0]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),
                     .arb_shift_a       (arb_shift_l_a_rep[0]),
                     .src_cpx_data_a    (scache0_cpx_data_a[149:0]),
                     .data_prev_x_      (col0_data_x_[149:0]),
                     .scan_in(cpx_mac1_scanin),
                     .scan_out(cpx_mac1_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[2]),
                     .tcu_pce_ov     (tcu_pce_ov_out[2]),
                     .ccx_aclk       (ccx_aclk_out[2]),
                     .ccx_bclk       (ccx_bclk_out[2])
                     );


// input from sctag3
cpx_mbl_dp cpx_mac2 (
                     // Outputs
                     .data_out_x_       (col2_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[2]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[2]),
                     .ccx_aclk_out    (ccx_aclk_out[2]),
                     .ccx_bclk_out    (ccx_bclk_out[2]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[3]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[3]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[3]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[3]),
                     .arb_shift_a       (arb_shift_l_a_rep[3]),
                     .src_cpx_data_a    (scache3_cpx_data_a[149:0]),
                     .data_prev_x_      (col1_data_x_[149:0]),
                     .scan_in(cpx_mac2_scanin),
                     .scan_out(cpx_mac2_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );

// input from sctag1
cpx_mbl_dp cpx_mac3 (
                     // Outputs
                     .data_out_x_       (col3_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[3]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[3]),
                     .ccx_aclk_out    (ccx_aclk_out[3]),
                     .ccx_bclk_out    (ccx_bclk_out[3]),
                     // Inputs
                     .arb_grant_a       (arb_grant_l_a_rep[1]),
                     .arb_qsel0_a       (arb_qsel0_l_a_rep[1]),
                     .arb_qsel1_a       (arb_qsel1_l_a_rep[1]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[1]),
                     .arb_shift_a       (arb_shift_l_a_rep[1]),
                     .src_cpx_data_a    (scache1_cpx_data_a[149:0]),
                     .data_prev_x_      (col2_data_x_[149:0]),
                     .scan_in(cpx_mac3_scanin),
                     .scan_out(cpx_mac3_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en),
                     .tcu_pce_ov     (tcu_pce_ov),
                     .ccx_aclk       (ccx_aclk),
                     .ccx_bclk       (ccx_bclk)
                     );

// input from sctag7
cpx_mbl_dp cpx_mac4 (
                     // Outputs
                     .data_out_x_       (col4_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[4]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[4]),
                     .ccx_aclk_out    (ccx_aclk_out[4]),
                     .ccx_bclk_out    (ccx_bclk_out[4]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[7]),
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[7]),
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[7]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[7]),
                     .arb_shift_a       (arb_shift_r_a_rep[7]),
                     .src_cpx_data_a    (scache7_cpx_data_a[149:0]),
                     .data_prev_x_      (col3_data_x_[149:0]),
                     .scan_in(cpx_mac4_scanin),
                     .scan_out(cpx_mac4_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[3]),
                     .tcu_pce_ov     (tcu_pce_ov_out[3]),
                     .ccx_aclk       (ccx_aclk_out[3]),
                     .ccx_bclk       (ccx_bclk_out[3])
                     );

// input from sctag5
cpx_mbl_dp cpx_mac5 (
                     // Outputs
                     .data_out_x_       (col5_data_x_[149:0]),
                     .tcu_scan_en_out (tcu_scan_en_out[5]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[5]),
                     .ccx_aclk_out    (ccx_aclk_out[5]),
                     .ccx_bclk_out    (ccx_bclk_out[5]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[5]),
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[5]),
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[5]),
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[5]),
                     .arb_shift_a       (arb_shift_r_a_rep[5]),
                     .src_cpx_data_a    (scache5_cpx_data_a[149:0]),
                     .data_prev_x_      (col4_data_x_[149:0]),
                     .scan_in(cpx_mac5_scanin),
                     .scan_out(cpx_mac5_scanout),
                     .l2clk             (l2clk),    
                     .tcu_scan_en    (tcu_scan_en_out[4]),
                     .tcu_pce_ov     (tcu_pce_ov_out[4]),
                     .ccx_aclk       (ccx_aclk_out[4]),
                     .ccx_bclk       (ccx_bclk_out[4])
                     );


/*
   cpx_mcr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(cpx_spc_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[149:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag6
cpx_mcr_dp cpx_mac6 (
                     // Outputs
                     .data_out_x_       (cpx_spc_data_x_[149:0]), // Templated
                     .tcu_scan_en_out (tcu_scan_en_out[6]),
                     .tcu_pce_ov_out  (tcu_pce_ov_out[6]),
                     .ccx_aclk_out    (ccx_aclk_out[6]),
                     .ccx_bclk_out    (ccx_bclk_out[6]),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a_rep[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a_rep[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a_rep[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a_rep[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a_rep[6]),        // Templated
                     .src_cpx_data_a    (scache6_cpx_data_a[149:0]), // Templated
                     .data_crit_x_      (col5_data_x_[149:0]),   // Templated
                     .data_ncrit_x_     (col7_data_x_[149:0]),   // Templated
                     .scan_in(cpx_mac6_scanin),
                     .scan_out(cpx_mac6_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[5]),
                     .tcu_pce_ov     (tcu_pce_ov_out[5]),
                     .ccx_aclk       (ccx_aclk_out[5]),
                     .ccx_bclk       (ccx_bclk_out[5])
                     );


/*
   cpx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[149:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_cpx_data_a(scache@_cpx_data_a[149:0]),
 .l2clk		(l2clk));
*/

// input from sctag4
cpx_mbr_dp cpx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[149:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out  (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out    (ccx_aclk_out_7_unused),
                     .ccx_bclk_out    (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[4]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[4]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[4]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[4]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[4]),        // Templated
                     .src_cpx_data_a    (scache4_cpx_data_a[149:0]), // Templated
                     .data_prev_x_      (all_ones[149:0]),
                     .scan_in(cpx_mac7_scanin),
                     .scan_out(cpx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en    (tcu_scan_en_out[6]),
                     .tcu_pce_ov     (tcu_pce_ov_out[6]),
                     .ccx_aclk       (ccx_aclk_out[6]),
                     .ccx_bclk       (ccx_bclk_out[6])
                     );
 

assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];

// fixscan start:
assign cpx_mac8_scanin           = scan_rep_out                  ;
assign cpx_mac0_scanin           = cpx_mac8_scanout         ;
assign cpx_mac1_scanin           = cpx_mac0_scanout         ;
assign cpx_mac2_scanin           = cpx_mac1_scanout         ;
assign cpx_mac3_scanin           = cpx_mac2_scanout         ;
assign cpx_mac4_scanin           = cpx_mac3_scanout         ;
assign cpx_mac5_scanin           = cpx_mac4_scanout         ;
assign cpx_mac6_scanin           = cpx_mac5_scanout         ;
assign cpx_mac7_scanin           = cpx_mac6_scanout         ;
assign scan_out                  = cpx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module cpx_dpsg_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsg_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module cpx_dpsg_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_dpsg_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsg_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsg_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[49:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[149:100]),
// .din1	(data_crit_x_[149:100]),
// .din2	(data_ncrit_x_[149:100]),
// .dout	(data_out_x[149:100])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[99:50]),
// .din1	(data_crit_x_[99:50]),
// .din2	(data_ncrit_x_[99:50]),
// .dout	(data_out_x[99:50])
//);
//
//nand_macro i_nand_data_crit_0 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[49:0]),
// .din1	(data_crit_x_[49:0]),
// .din2	(data_ncrit_x_[49:0]),
// .dout	(data_out_x[49:0])
//);
//
//inv_macro i_inv_data_out_2 (width=50, stack=50c) 
//(
// .din	(data_out_x[149:100]),
// .dout	(data_out_x_[149:100])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[99:50]),
// .dout	(data_out_x_[99:50])
// );
//
//inv_macro i_inv_data_out_0 (width=50, stack=50c) 
//(
// .din	(data_out_x[49:0]),
// .dout	(data_out_x_[49:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule


//
//   ccx macro
//
//


module cpx_dpsg_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module cpx_dpsg_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module cpx_dpsg(cpx_spc_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	io_cpx_data_a, scache0_cpx_data_a, scache1_cpx_data_a, 
	scache2_cpx_data_a, scache3_cpx_data_a, scache4_cpx_data_a, 
	scache5_cpx_data_a, scache6_cpx_data_a, scache7_cpx_data_a, tcu_scan_en,
	l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out);

	output	[149:0]		cpx_spc_data_x_;
	input	[8:0]		arb_grant_l_a;
	input	[8:0]		arb_q0_holdbar_l_a;
	input	[8:0]		arb_qsel0_l_a;
	input	[8:0]		arb_qsel1_l_a;
	input	[8:0]		arb_shift_l_a;
	input	[8:0]		arb_grant_r_a;
	input	[8:0]		arb_q0_holdbar_r_a;
	input	[8:0]		arb_qsel0_r_a;
	input	[8:0]		arb_qsel1_r_a;
	input	[8:0]		arb_shift_r_a;
	input	[149:0]		io_cpx_data_a;
	input	[149:0]		scache0_cpx_data_a;
	input	[149:0]		scache1_cpx_data_a;
	input	[149:0]		scache2_cpx_data_a;
	input	[149:0]		scache3_cpx_data_a;
	input	[149:0]		scache4_cpx_data_a;
	input	[149:0]		scache5_cpx_data_a;
	input	[149:0]		scache6_cpx_data_a;
	input	[149:0]		scache7_cpx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[149:0]		all_ones;
	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:5]		arb_grant_r_a_rep;
	wire	[7:5]		arb_q0_holdbar_r_a_rep;
	wire	[7:5]		arb_qsel0_r_a_rep;
	wire	[7:5]		arb_qsel1_r_a_rep;
	wire	[7:5]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[149:0]		col8_data_x_;
	wire			tcu_scan_en_out_8_unused;
	wire			tcu_pce_ov_out_8_unused;
	wire			ccx_aclk_out_8_unused;
	wire			ccx_bclk_out_8_unused;
	wire			cpx_mac8_scanin;
	wire			cpx_mac8_scanout;
	wire	[6:0]		tcu_scan_en_out;
	wire	[6:0]		tcu_pce_ov_out;
	wire	[6:0]		ccx_aclk_out;
	wire	[6:0]		ccx_bclk_out;
	wire	[149:0]		col0_data_x_;
	wire			cpx_mac0_scanin;
	wire			cpx_mac0_scanout;
	wire	[149:0]		col1_data_x_;
	wire			cpx_mac1_scanin;
	wire			cpx_mac1_scanout;
	wire	[149:0]		col2_data_x_;
	wire			cpx_mac2_scanin;
	wire			cpx_mac2_scanout;
	wire	[149:0]		col3_data_x_;
	wire			cpx_mac3_scanin;
	wire			cpx_mac3_scanout;
	wire	[149:0]		col4_data_x_;
	wire			cpx_mac4_scanin;
	wire			cpx_mac4_scanout;
	wire	[149:0]		col5_data_x_;
	wire			cpx_mac5_scanin;
	wire			cpx_mac5_scanout;
	wire	[149:0]		col7_data_x_;
	wire			cpx_mac6_scanin;
	wire			cpx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			cpx_mac7_scanin;
	wire			cpx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[8:0]		arb_grant_r_a_unused;
	wire	[8:0]		arb_q0_holdbar_r_a_unused;
	wire	[8:0]		arb_qsel0_r_a_unused;
	wire	[8:0]		arb_qsel1_r_a_unused;
	wire	[8:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign all_ones[149:0] = 150'h3fffffffffffffffffffffffffffffffffffff;
	assign mac0_rep_in[4:0] = {arb_grant_l_a[2], arb_qsel0_l_a[2], 
		arb_qsel1_l_a[2], arb_shift_l_a[2], arb_q0_holdbar_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_qsel0_l_a_rep[2], 
		arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2], 
		arb_q0_holdbar_l_a_rep[2]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[0], arb_q0_holdbar_l_a[0], 
		arb_qsel0_l_a[0], arb_qsel1_l_a[0], arb_shift_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_q0_holdbar_l_a_rep[0], 
		arb_qsel0_l_a_rep[0], arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[6], arb_q0_holdbar_r_a[6], 
		arb_qsel0_r_a[6], arb_qsel1_r_a[6], arb_shift_r_a[6]};
	assign {arb_grant_r_a_rep[6], arb_q0_holdbar_r_a_rep[6], 
		arb_qsel0_r_a_rep[6], arb_qsel1_r_a_rep[6], arb_shift_r_a_rep[6]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign arb_grant_r_a_unused[8] = arb_grant_r_a[8];
	assign arb_q0_holdbar_r_a_unused[8] = arb_q0_holdbar_r_a[8];
	assign arb_qsel0_r_a_unused[8] = arb_qsel0_r_a[8];
	assign arb_qsel1_r_a_unused[8] = arb_qsel1_r_a[8];
	assign arb_shift_r_a_unused[8] = arb_shift_r_a[8];
	assign cpx_mac8_scanin = scan_rep_out;
	assign cpx_mac0_scanin = cpx_mac8_scanout;
	assign cpx_mac1_scanin = cpx_mac0_scanout;
	assign cpx_mac2_scanin = cpx_mac1_scanout;
	assign cpx_mac3_scanin = cpx_mac2_scanout;
	assign cpx_mac4_scanin = cpx_mac3_scanout;
	assign cpx_mac5_scanin = cpx_mac4_scanout;
	assign cpx_mac6_scanin = cpx_mac5_scanout;
	assign cpx_mac7_scanin = cpx_mac6_scanout;
	assign scan_out = cpx_mac7_scanout;

	cpx_rep_dp cpx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	cpx_mal_dp cpx_mac8(
		.data_out_x_			(col8_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_8_unused), 
		.ccx_aclk_out			(ccx_aclk_out_8_unused), 
		.ccx_bclk_out			(ccx_bclk_out_8_unused), 
		.arb_grant_a			(arb_grant_l_a[8]), 
		.arb_qsel0_a			(arb_qsel0_l_a[8]), 
		.arb_qsel1_a			(arb_qsel1_l_a[8]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a[8]), 
		.arb_shift_a			(arb_shift_l_a[8]), 
		.src_cpx_data_a			(io_cpx_data_a[149:0]), 
		.scan_in			(cpx_mac8_scanin), 
		.scan_out			(cpx_mac8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[0]), 
		.tcu_pce_ov			(tcu_pce_ov_out[0]), 
		.ccx_aclk			(ccx_aclk_out[0]), 
		.ccx_bclk			(ccx_bclk_out[0]));
	cpx_mbl_dp cpx_mac0(
		.data_out_x_			(col0_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[0]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[0]), 
		.ccx_aclk_out			(ccx_aclk_out[0]), 
		.ccx_bclk_out			(ccx_bclk_out[0]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_cpx_data_a			(scache2_cpx_data_a[149:0]), 
		.data_prev_x_			(col8_data_x_[149:0]), 
		.scan_in			(cpx_mac0_scanin), 
		.scan_out			(cpx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	cpx_mbl_dp cpx_mac1(
		.data_out_x_			(col1_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_cpx_data_a			(scache0_cpx_data_a[149:0]), 
		.data_prev_x_			(col0_data_x_[149:0]), 
		.scan_in			(cpx_mac1_scanin), 
		.scan_out			(cpx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	cpx_mbl_dp cpx_mac2(
		.data_out_x_			(col2_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_cpx_data_a			(scache3_cpx_data_a[149:0]), 
		.data_prev_x_			(col1_data_x_[149:0]), 
		.scan_in			(cpx_mac2_scanin), 
		.scan_out			(cpx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbl_dp cpx_mac3(
		.data_out_x_			(col3_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_cpx_data_a			(scache1_cpx_data_a[149:0]), 
		.data_prev_x_			(col2_data_x_[149:0]), 
		.scan_in			(cpx_mac3_scanin), 
		.scan_out			(cpx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	cpx_mbl_dp cpx_mac4(
		.data_out_x_			(col4_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_cpx_data_a			(scache7_cpx_data_a[149:0]), 
		.data_prev_x_			(col3_data_x_[149:0]), 
		.scan_in			(cpx_mac4_scanin), 
		.scan_out			(cpx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	cpx_mbl_dp cpx_mac5(
		.data_out_x_			(col5_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_cpx_data_a			(scache5_cpx_data_a[149:0]), 
		.data_prev_x_			(col4_data_x_[149:0]), 
		.scan_in			(cpx_mac5_scanin), 
		.scan_out			(cpx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	cpx_mcr_dp cpx_mac6(
		.data_out_x_			(cpx_spc_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[6]), 
		.arb_shift_a			(arb_shift_r_a_rep[6]), 
		.src_cpx_data_a			(scache6_cpx_data_a[149:0]), 
		.data_crit_x_			(col5_data_x_[149:0]), 
		.data_ncrit_x_			(col7_data_x_[149:0]), 
		.scan_in			(cpx_mac6_scanin), 
		.scan_out			(cpx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	cpx_mbr_dp cpx_mac7(
		.data_out_x_			(col7_data_x_[149:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[4]), 
		.arb_shift_a			(arb_shift_r_a[4]), 
		.src_cpx_data_a			(scache4_cpx_data_a[149:0]), 
		.data_prev_x_			(all_ones[149:0]), 
		.scan_in			(cpx_mac7_scanin), 
		.scan_out			(cpx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_mal_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_mal_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_cpx_data_a, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [149:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;
wire i13_scanin;
wire i13_scanout;
wire i14_scanin;
wire i14_scanout;


output [149:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [149:0]   src_cpx_data_a;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

assign src_data_a[149:0] = src_cpx_data_a[149:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);

//l1clkhdr_dp_macro gkt_hdra 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

cpx_mal_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

cpx_mal_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

cpx_mal_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_a AUTO_TEMPLATE
// (
//.scan_in(AUTO_TEMPLATE_scanin),
//.scan_out(AUTO_TEMPLATE_scanout),
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);

cpx_mal_dp_ccx_new_macro__type_a i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),
  .se(se));   // Templated

cpx_mal_dp_ccx_new_macro__type_a i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),
  .se(se));  // Templated

cpx_mal_dp_ccx_new_macro__type_a i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i13  (
                 // Outputs
                 .data_x_l              (data_out_x_[139:130]),    // Templated
                 // Inputs
                 .scan_in(i13_scanin),
                 .scan_out(i13_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[139:130]),
  .se(se)); // Templated
cpx_mal_dp_ccx_new_macro__type_a i14  (
                 // Outputs
                 .data_x_l              (data_out_x_[149:140]),    // Templated
                 // Inputs
                 .scan_in(i14_scanin),
                 .scan_out(i14_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[149:140]),
  .se(se)); // Templated

// fixscan start:
assign i14_scanin                 = scan_in                  ;
assign i13_scanin                 = i14_scanout              ;
assign i12_scanin                 = i13_scanout              ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[49:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:


//
//   buff macro
//
//


module cpx_mal_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_mal_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_mal_dp_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module cpx_mal_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_cpx_data_a, l2clk, scan_in, 
	tcu_pce_ov, ccx_aclk, ccx_bclk, tcu_scan_en, scan_out, ccx_aclk_out, 
	ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[149:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[149:0]		src_cpx_data_a;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[149:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;
	wire			i13_scanin;
	wire			i13_scanout;
	wire			i14_scanin;
	wire			i14_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[149:0] = src_cpx_data_a[149:0];
	assign i14_scanin = scan_in;
	assign i13_scanin = i14_scanout;
	assign i12_scanin = i13_scanout;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_a i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.se				(se));
	ccx_new_macro__type_a i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.se				(se));
	ccx_new_macro__type_a i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.se				(se));
	ccx_new_macro__type_a i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.se				(se));
	ccx_new_macro__type_a i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.se				(se));
	ccx_new_macro__type_a i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.se				(se));
	ccx_new_macro__type_a i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.se				(se));
	ccx_new_macro__type_a i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.se				(se));
	ccx_new_macro__type_a i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.se				(se));
	ccx_new_macro__type_a i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.se				(se));
	ccx_new_macro__type_a i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.se				(se));
	ccx_new_macro__type_a i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.se				(se));
	ccx_new_macro__type_a i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.se				(se));
	ccx_new_macro__type_a i13(
		.data_x_l			(data_out_x_[139:130]), 
		.scan_in			(i13_scanin), 
		.scan_out			(i13_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[139:130]), 
		.se				(se));
	ccx_new_macro__type_a i14(
		.data_x_l			(data_out_x_[149:140]), 
		.scan_in			(i14_scanin), 
		.scan_out			(i14_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[149:140]), 
		.se				(se));
endmodule

module buff_macro__dbuff_8x__stack_none__vertical_1__width_4(din, dout);

        input   [3:0]           din;
        output  [3:0]           dout;

        buff #(4) d0_0(
                .in                             (din[3:0]),
                .out                            (dout[3:0]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_mar_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_mar_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_cpx_data_a, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [149:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;
wire i13_scanin;
wire i13_scanout;
wire i14_scanin;
wire i14_scanout;


output [149:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [149:0]   src_cpx_data_a;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

assign src_data_a[149:0] = src_cpx_data_a[149:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);

//l1clkhdr_dp_macro gkt_hdra 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

cpx_mar_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

cpx_mar_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

cpx_mar_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_a AUTO_TEMPLATE
// (
//.scan_in(AUTO_TEMPLATE_scanin),
//.scan_out(AUTO_TEMPLATE_scanout),
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);

cpx_mar_dp_ccx_new_macro__type_a i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),
  .se(se));   // Templated

cpx_mar_dp_ccx_new_macro__type_a i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),
  .se(se));  // Templated

cpx_mar_dp_ccx_new_macro__type_a i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i13  (
                 // Outputs
                 .data_x_l              (data_out_x_[139:130]),    // Templated
                 // Inputs
                 .scan_in(i13_scanin),
                 .scan_out(i13_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[139:130]),
  .se(se)); // Templated
cpx_mar_dp_ccx_new_macro__type_a i14  (
                 // Outputs
                 .data_x_l              (data_out_x_[149:140]),    // Templated
                 // Inputs
                 .scan_in(i14_scanin),
                 .scan_out(i14_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[149:140]),
  .se(se)); // Templated

// fixscan start:
assign i14_scanin                 = scan_in                  ;
assign i13_scanin                 = i14_scanout              ;
assign i12_scanin                 = i13_scanout              ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[49:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:


//
//   buff macro
//
//


module cpx_mar_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_mar_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_mar_dp_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_mar_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_cpx_data_a, l2clk, scan_in, 
	tcu_pce_ov, ccx_aclk, ccx_bclk, tcu_scan_en, scan_out, ccx_aclk_out, 
	ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[149:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[149:0]		src_cpx_data_a;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[149:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;
	wire			i13_scanin;
	wire			i13_scanout;
	wire			i14_scanin;
	wire			i14_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[149:0] = src_cpx_data_a[149:0];
	assign i14_scanin = scan_in;
	assign i13_scanin = i14_scanout;
	assign i12_scanin = i13_scanout;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_a i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.se				(se));
	ccx_new_macro__type_a i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.se				(se));
	ccx_new_macro__type_a i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.se				(se));
	ccx_new_macro__type_a i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.se				(se));
	ccx_new_macro__type_a i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.se				(se));
	ccx_new_macro__type_a i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.se				(se));
	ccx_new_macro__type_a i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.se				(se));
	ccx_new_macro__type_a i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.se				(se));
	ccx_new_macro__type_a i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.se				(se));
	ccx_new_macro__type_a i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.se				(se));
	ccx_new_macro__type_a i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.se				(se));
	ccx_new_macro__type_a i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.se				(se));
	ccx_new_macro__type_a i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.se				(se));
	ccx_new_macro__type_a i13(
		.data_x_l			(data_out_x_[139:130]), 
		.scan_in			(i13_scanin), 
		.scan_out			(i13_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[139:130]), 
		.se				(se));
	ccx_new_macro__type_a i14(
		.data_x_l			(data_out_x_[149:140]), 
		.scan_in			(i14_scanin), 
		.scan_out			(i14_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[149:140]), 
		.se				(se));
endmodule

/* Source file "cpx_pcx_fpga_files/ccx_tokens_frm_fpga_flist", line 16404 */
`timescale 1 ns / 100 ps
module ccx_new_macro__type_a(l2clk, l1clk, pce0, pce1, pce_ov, se, stop,
        siclk_in, soclk_in, scan_in, grant_a, qsel0, shift, data_a, data_x_l,
        scan_out);

        input                   l2clk;
        input                   l1clk;
        input                   pce0;
        input                   pce1;
        input                   pce_ov;
        input                   se;
        input                   stop;
        input                   siclk_in;
        input                   soclk_in;
        input                   scan_in;
        input                   grant_a;
        input                   qsel0;
        input                   shift;
        input   [9:0]           data_a;
        output  [9:0]           data_x_l;
        output                  scan_out;

        wire                    so5;
        wire                    siclk_out;
        wire                    soclk_out;
        wire                    l1clk0;
        wire                    l1clk1;
        wire                    grant_x;
        wire                    qsel0_buf;
        wire                    shift_buf;

        cl_dp1_ccxhdr c0(
                .si                             (scan_in),
                .so                             (so5),
                .l2clk                          (l2clk),

                .pce0                           (pce0),
                .pce1                           (pce1),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_in                       (siclk_in),
                .soclk_in                       (soclk_in),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .se                             (se),
                .l1clk                          (l1clk),
                .grant_a                        (grant_a),
                .grant_x                        (grant_x),
                .qsel0                          (qsel0),
                .qsel0_buf                      (qsel0_buf),
                .shift                          (shift),
                .shift_buf                      (shift_buf));
        ccx_mac_a #(10) mac_a(
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .data_a                         (data_a[9:0]),
                .data_x_l                       (data_x_l[9:0]),
                .si                             (so5),
                .so                             (scan_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .grant_x                        (grant_x),
                .qsel0_buf                      (qsel0_buf),
                .shift_buf                      (shift_buf));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_mbl_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_mbl_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_cpx_data_a, 
  data_prev_x_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [149:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;
wire i13_scanin;
wire i13_scanout;
wire i14_scanin;
wire i14_scanout;


output [149:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [149:0]   src_cpx_data_a;
input [149:0]   data_prev_x_;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

assign src_data_a[149:0] = src_cpx_data_a[149:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);
//

//l1clkhdr_dp_macro gkt_hdra 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

cpx_mbl_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

cpx_mbl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

cpx_mbl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_b AUTO_TEMPLATE
// (
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_prev_x_l   (data_prev_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);

cpx_mbl_dp_ccx_new_macro__type_b_l i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),   // Templated
                .data_prev_x_l          (data_prev_x_[9:0]),
  .se(se));     // Templated

cpx_mbl_dp_ccx_new_macro__type_b_l i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),  // Templated
                .data_prev_x_l          (data_prev_x_[19:10]),
  .se(se));    // Templated

cpx_mbl_dp_ccx_new_macro__type_b_l i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]), // Templated
                .data_prev_x_l          (data_prev_x_[29:20]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]), // Templated
                .data_prev_x_l          (data_prev_x_[39:30]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]), // Templated
                .data_prev_x_l          (data_prev_x_[49:40]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]), // Templated
                .data_prev_x_l          (data_prev_x_[59:50]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]), // Templated
                .data_prev_x_l          (data_prev_x_[69:60]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]), // Templated
                .data_prev_x_l          (data_prev_x_[79:70]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]), // Templated
                .data_prev_x_l          (data_prev_x_[89:80]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]), // Templated
                .data_prev_x_l          (data_prev_x_[99:90]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]), // Templated
                 .data_prev_x_l         (data_prev_x_[109:100]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]), // Templated
                 .data_prev_x_l         (data_prev_x_[119:110]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]), // Templated
                 .data_prev_x_l         (data_prev_x_[129:120]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i13  (
                 // Outputs
                 .data_x_l              (data_out_x_[139:130]),    // Templated
                 // Inputs
                 .scan_in(i13_scanin),
                 .scan_out(i13_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[139:130]), // Templated
                 .data_prev_x_l         (data_prev_x_[139:130]),
  .se(se));   // Templated
cpx_mbl_dp_ccx_new_macro__type_b_l i14  (
                 // Outputs
                 .data_x_l              (data_out_x_[149:140]),    // Templated
                 // Inputs
                 .scan_in(i14_scanin),
                 .scan_out(i14_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[149:140]), // Templated
                 .data_prev_x_l         (data_prev_x_[149:140]),
  .se(se));   // Templated

// fixscan start:
assign i14_scanin                 = scan_in                  ;
assign i13_scanin                 = i14_scanout              ;
assign i12_scanin                 = i13_scanout              ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[49:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[149:100]),
// .din1	(data_prev_x_[149:100]),
// .dout	(data_out_x[149:100])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[99:50]),
// .din1	(data_prev_x_[99:50]),
// .dout	(data_out_x[99:50])
// );
//
//nand_macro i_nand_data_prev_0 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[49:0]),
// .din1	(data_prev_x_[49:0]),
// .dout	(data_out_x[49:0])
// );
//
//inv_macro i_inv_data_out_2 (width=50, stack=50c) 
//(
// .din	(data_out_x[149:100]),
// .dout	(data_out_x_[149:100])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[99:50]),
// .dout	(data_out_x_[99:50])
// );
//
//inv_macro i_inv_data_out_0 (width=50, stack=50c) 
//(
// .din	(data_out_x[49:0]),
// .dout	(data_out_x_[49:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule


//
//   buff macro
//
//


module cpx_mbl_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_mbl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_mbl_dp_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_mbl_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_cpx_data_a, data_prev_x_, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, tcu_scan_en, scan_out, 
	ccx_aclk_out, ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[149:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[149:0]		src_cpx_data_a;
	input	[149:0]		data_prev_x_;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[149:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;
	wire			i13_scanin;
	wire			i13_scanout;
	wire			i14_scanin;
	wire			i14_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[149:0] = src_cpx_data_a[149:0];
	assign i14_scanin = scan_in;
	assign i13_scanin = i14_scanout;
	assign i12_scanin = i13_scanout;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_b_l i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.data_prev_x_l			(data_prev_x_[9:0]), 
		.se				(se));
	ccx_new_macro__type_b_l i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.data_prev_x_l			(data_prev_x_[19:10]), 
		.se				(se));
	ccx_new_macro__type_b_l i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.data_prev_x_l			(data_prev_x_[29:20]), 
		.se				(se));
	ccx_new_macro__type_b_l i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.data_prev_x_l			(data_prev_x_[39:30]), 
		.se				(se));
	ccx_new_macro__type_b_l i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.data_prev_x_l			(data_prev_x_[49:40]), 
		.se				(se));
	ccx_new_macro__type_b_l i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.data_prev_x_l			(data_prev_x_[59:50]), 
		.se				(se));
	ccx_new_macro__type_b_l i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.data_prev_x_l			(data_prev_x_[69:60]), 
		.se				(se));
	ccx_new_macro__type_b_l i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.data_prev_x_l			(data_prev_x_[79:70]), 
		.se				(se));
	ccx_new_macro__type_b_l i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.data_prev_x_l			(data_prev_x_[89:80]), 
		.se				(se));
	ccx_new_macro__type_b_l i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.data_prev_x_l			(data_prev_x_[99:90]), 
		.se				(se));
	ccx_new_macro__type_b_l i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.data_prev_x_l			(data_prev_x_[109:100]), 
		.se				(se));
	ccx_new_macro__type_b_l i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.data_prev_x_l			(data_prev_x_[119:110]), 
		.se				(se));
	ccx_new_macro__type_b_l i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.data_prev_x_l			(data_prev_x_[129:120]), 
		.se				(se));
	ccx_new_macro__type_b_l i13(
		.data_x_l			(data_out_x_[139:130]), 
		.scan_in			(i13_scanin), 
		.scan_out			(i13_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[139:130]), 
		.data_prev_x_l			(data_prev_x_[139:130]), 
		.se				(se));
	ccx_new_macro__type_b_l i14(
		.data_x_l			(data_out_x_[149:140]), 
		.scan_in			(i14_scanin), 
		.scan_out			(i14_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[149:140]), 
		.data_prev_x_l			(data_prev_x_[149:140]), 
		.se				(se));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_mbr_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_mbr_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_cpx_data_a, 
  data_prev_x_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [149:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;
wire i13_scanin;
wire i13_scanout;
wire i14_scanin;
wire i14_scanout;


output [149:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [149:0]   src_cpx_data_a;
input [149:0]   data_prev_x_;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

assign src_data_a[149:0] = src_cpx_data_a[149:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);
//

//l1clkhdr_dp_macro gkt_hdra 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

cpx_mbr_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

cpx_mbr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

cpx_mbr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_b AUTO_TEMPLATE
// (
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_prev_x_l   (data_prev_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);

cpx_mbr_dp_ccx_new_macro__type_b_r i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),   // Templated
                .data_prev_x_l          (data_prev_x_[9:0]),
  .se(se));     // Templated

cpx_mbr_dp_ccx_new_macro__type_b_r i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),  // Templated
                .data_prev_x_l          (data_prev_x_[19:10]),
  .se(se));    // Templated

cpx_mbr_dp_ccx_new_macro__type_b_r i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]), // Templated
                .data_prev_x_l          (data_prev_x_[29:20]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]), // Templated
                .data_prev_x_l          (data_prev_x_[39:30]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]), // Templated
                .data_prev_x_l          (data_prev_x_[49:40]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]), // Templated
                .data_prev_x_l          (data_prev_x_[59:50]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]), // Templated
                .data_prev_x_l          (data_prev_x_[69:60]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]), // Templated
                .data_prev_x_l          (data_prev_x_[79:70]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]), // Templated
                .data_prev_x_l          (data_prev_x_[89:80]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]), // Templated
                .data_prev_x_l          (data_prev_x_[99:90]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]), // Templated
                 .data_prev_x_l         (data_prev_x_[109:100]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]), // Templated
                 .data_prev_x_l         (data_prev_x_[119:110]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]), // Templated
                 .data_prev_x_l         (data_prev_x_[129:120]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i13  (
                 // Outputs
                 .data_x_l              (data_out_x_[139:130]),    // Templated
                 // Inputs
                 .scan_in(i13_scanin),
                 .scan_out(i13_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[139:130]), // Templated
                 .data_prev_x_l         (data_prev_x_[139:130]),
  .se(se));   // Templated
cpx_mbr_dp_ccx_new_macro__type_b_r i14  (
                 // Outputs
                 .data_x_l              (data_out_x_[149:140]),    // Templated
                 // Inputs
                 .scan_in(i14_scanin),
                 .scan_out(i14_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[149:140]), // Templated
                 .data_prev_x_l         (data_prev_x_[149:140]),
  .se(se));   // Templated

// fixscan start:
assign i14_scanin                 = scan_in                  ;
assign i13_scanin                 = i14_scanout              ;
assign i12_scanin                 = i13_scanout              ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[49:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[149:100]),
// .din1	(data_prev_x_[149:100]),
// .dout	(data_out_x[149:100])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[99:50]),
// .din1	(data_prev_x_[99:50]),
// .dout	(data_out_x[99:50])
// );
//
//nand_macro i_nand_data_prev_0 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[49:0]),
// .din1	(data_prev_x_[49:0]),
// .dout	(data_out_x[49:0])
// );
//
//inv_macro i_inv_data_out_2 (width=50, stack=50c) 
//(
// .din	(data_out_x[149:100]),
// .dout	(data_out_x_[149:100])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[99:50]),
// .dout	(data_out_x_[99:50])
// );
//
//inv_macro i_inv_data_out_0 (width=50, stack=50c) 
//(
// .din	(data_out_x[49:0]),
// .dout	(data_out_x_[49:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule


//
//   buff macro
//
//


module cpx_mbr_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_mbr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_mbr_dp_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA

module cpx_mbr_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_cpx_data_a, data_prev_x_, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, tcu_scan_en, scan_out, 
	ccx_aclk_out, ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[149:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[149:0]		src_cpx_data_a;
	input	[149:0]		data_prev_x_;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[149:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;
	wire			i13_scanin;
	wire			i13_scanout;
	wire			i14_scanin;
	wire			i14_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[149:0] = src_cpx_data_a[149:0];
	assign i14_scanin = scan_in;
	assign i13_scanin = i14_scanout;
	assign i12_scanin = i13_scanout;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_b_r i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.data_prev_x_l			(data_prev_x_[9:0]), 
		.se				(se));
	ccx_new_macro__type_b_r i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.data_prev_x_l			(data_prev_x_[19:10]), 
		.se				(se));
	ccx_new_macro__type_b_r i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.data_prev_x_l			(data_prev_x_[29:20]), 
		.se				(se));
	ccx_new_macro__type_b_r i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.data_prev_x_l			(data_prev_x_[39:30]), 
		.se				(se));
	ccx_new_macro__type_b_r i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.data_prev_x_l			(data_prev_x_[49:40]), 
		.se				(se));
	ccx_new_macro__type_b_r i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.data_prev_x_l			(data_prev_x_[59:50]), 
		.se				(se));
	ccx_new_macro__type_b_r i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.data_prev_x_l			(data_prev_x_[69:60]), 
		.se				(se));
	ccx_new_macro__type_b_r i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.data_prev_x_l			(data_prev_x_[79:70]), 
		.se				(se));
	ccx_new_macro__type_b_r i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.data_prev_x_l			(data_prev_x_[89:80]), 
		.se				(se));
	ccx_new_macro__type_b_r i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.data_prev_x_l			(data_prev_x_[99:90]), 
		.se				(se));
	ccx_new_macro__type_b_r i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.data_prev_x_l			(data_prev_x_[109:100]), 
		.se				(se));
	ccx_new_macro__type_b_r i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.data_prev_x_l			(data_prev_x_[119:110]), 
		.se				(se));
	ccx_new_macro__type_b_r i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.data_prev_x_l			(data_prev_x_[129:120]), 
		.se				(se));
	ccx_new_macro__type_b_r i13(
		.data_x_l			(data_out_x_[139:130]), 
		.scan_in			(i13_scanin), 
		.scan_out			(i13_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[139:130]), 
		.data_prev_x_l			(data_prev_x_[139:130]), 
		.se				(se));
	ccx_new_macro__type_b_r i14(
		.data_x_l			(data_out_x_[149:140]), 
		.scan_in			(i14_scanin), 
		.scan_out			(i14_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[149:140]), 
		.data_prev_x_l			(data_prev_x_[149:140]), 
		.se				(se));
endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_mcl_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_mcl_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_cpx_data_a, 
  data_crit_x_, 
  data_ncrit_x_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [149:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;
wire i13_scanin;
wire i13_scanout;
wire i14_scanin;
wire i14_scanout;


output [149:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [149:0]   src_cpx_data_a;
input [149:0]   data_crit_x_;
input [149:0]   data_ncrit_x_;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

assign src_data_a[149:0] = src_cpx_data_a[149:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);

//l1clkhdr_dp_macro gkt_hdra 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

cpx_mcl_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

cpx_mcl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

cpx_mcl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );


//   ccx_new_macro_c AUTO_TEMPLATE
// (
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.scan_in  (scan_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_crit_x_l   (data_crit_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_ncrit_x_l   (data_ncrit_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);


cpx_mcl_dp_ccx_new_macro__type_c_l i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),   // Templated
                .data_crit_x_l          (data_crit_x_[9:0]),     // Templated
                .data_ncrit_x_l         (data_ncrit_x_[9:0]),
  .se(se));    // Templated

cpx_mcl_dp_ccx_new_macro__type_c_l i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),  // Templated
                .data_crit_x_l          (data_crit_x_[19:10]),    // Templated
                .data_ncrit_x_l         (data_ncrit_x_[19:10]),
  .se(se));   // Templated

cpx_mcl_dp_ccx_new_macro__type_c_l i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]), // Templated
                .data_crit_x_l          (data_crit_x_[29:20]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[29:20]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]), // Templated
                .data_crit_x_l          (data_crit_x_[39:30]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[39:30]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]), // Templated
                .data_crit_x_l          (data_crit_x_[49:40]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[49:40]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]), // Templated
                .data_crit_x_l          (data_crit_x_[59:50]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[59:50]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]), // Templated
                .data_crit_x_l          (data_crit_x_[69:60]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[69:60]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]), // Templated
                .data_crit_x_l          (data_crit_x_[79:70]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[79:70]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]), // Templated
                .data_crit_x_l          (data_crit_x_[89:80]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[89:80]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]), // Templated
                .data_crit_x_l          (data_crit_x_[99:90]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[99:90]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]), // Templated
                 .data_crit_x_l         (data_crit_x_[109:100]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[109:100]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]), // Templated
                 .data_crit_x_l         (data_crit_x_[119:110]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[119:110]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]), // Templated
                 .data_crit_x_l         (data_crit_x_[129:120]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[129:120]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i13  (
                 // Outputs
                 .data_x_l              (data_out_x_[139:130]),    // Templated
                 // Inputs
                 .scan_in(i13_scanin),
                 .scan_out(i13_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[139:130]), // Templated
                 .data_crit_x_l         (data_crit_x_[139:130]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[139:130]),
  .se(se));  // Templated
cpx_mcl_dp_ccx_new_macro__type_c_l i14  (
                 // Outputs
                 .data_x_l              (data_out_x_[149:140]),    // Templated
                 // Inputs
                 .scan_in(i14_scanin),
                 .scan_out(i14_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[149:140]), // Templated
                 .data_crit_x_l         (data_crit_x_[149:140]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[149:140]),
  .se(se));  // Templated

// fixscan start:
assign i14_scanin                 = scan_in                  ;
assign i13_scanin                 = i14_scanout              ;
assign i12_scanin                 = i13_scanout              ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule // cpx_mcl_dp

//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[49:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[149:100]),
// .din1	(data_crit_x_[149:100]),
// .din2	(data_ncrit_x_[149:100]),
// .dout	(data_out_x[149:100])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[99:50]),
// .din1	(data_crit_x_[99:50]),
// .din2	(data_ncrit_x_[99:50]),
// .dout	(data_out_x[99:50])
//);
//
//nand_macro i_nand_data_crit_0 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[49:0]),
// .din1	(data_crit_x_[49:0]),
// .din2	(data_ncrit_x_[49:0]),
// .dout	(data_out_x[49:0])
//);
//
//inv_macro i_inv_data_out_2 (width=50, stack=50c) 
//(
// .din	(data_out_x[149:100]),
// .dout	(data_out_x_[149:100])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[99:50]),
// .dout	(data_out_x_[99:50])
// );
//
//inv_macro i_inv_data_out_0 (width=50, stack=50c) 
//(
// .din	(data_out_x[49:0]),
// .dout	(data_out_x_[49:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule


//
//   buff macro
//
//


module cpx_mcl_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_mcl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_mcl_dp_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module cpx_mcl_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_cpx_data_a, data_crit_x_, 
	data_ncrit_x_, l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, 
	tcu_scan_en, scan_out, ccx_aclk_out, ccx_bclk_out, tcu_pce_ov_out, 
	tcu_scan_en_out);

	output	[149:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[149:0]		src_cpx_data_a;
	input	[149:0]		data_crit_x_;
	input	[149:0]		data_ncrit_x_;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[149:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;
	wire			i13_scanin;
	wire			i13_scanout;
	wire			i14_scanin;
	wire			i14_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[149:0] = src_cpx_data_a[149:0];
	assign i14_scanin = scan_in;
	assign i13_scanin = i14_scanout;
	assign i12_scanin = i13_scanout;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_c_l i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.data_crit_x_l			(data_crit_x_[9:0]), 
		.data_ncrit_x_l			(data_ncrit_x_[9:0]), 
		.se				(se));
	ccx_new_macro__type_c_l i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.data_crit_x_l			(data_crit_x_[19:10]), 
		.data_ncrit_x_l			(data_ncrit_x_[19:10]), 
		.se				(se));
	ccx_new_macro__type_c_l i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.data_crit_x_l			(data_crit_x_[29:20]), 
		.data_ncrit_x_l			(data_ncrit_x_[29:20]), 
		.se				(se));
	ccx_new_macro__type_c_l i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.data_crit_x_l			(data_crit_x_[39:30]), 
		.data_ncrit_x_l			(data_ncrit_x_[39:30]), 
		.se				(se));
	ccx_new_macro__type_c_l i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.data_crit_x_l			(data_crit_x_[49:40]), 
		.data_ncrit_x_l			(data_ncrit_x_[49:40]), 
		.se				(se));
	ccx_new_macro__type_c_l i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.data_crit_x_l			(data_crit_x_[59:50]), 
		.data_ncrit_x_l			(data_ncrit_x_[59:50]), 
		.se				(se));
	ccx_new_macro__type_c_l i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.data_crit_x_l			(data_crit_x_[69:60]), 
		.data_ncrit_x_l			(data_ncrit_x_[69:60]), 
		.se				(se));
	ccx_new_macro__type_c_l i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.data_crit_x_l			(data_crit_x_[79:70]), 
		.data_ncrit_x_l			(data_ncrit_x_[79:70]), 
		.se				(se));
	ccx_new_macro__type_c_l i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.data_crit_x_l			(data_crit_x_[89:80]), 
		.data_ncrit_x_l			(data_ncrit_x_[89:80]), 
		.se				(se));
	ccx_new_macro__type_c_l i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.data_crit_x_l			(data_crit_x_[99:90]), 
		.data_ncrit_x_l			(data_ncrit_x_[99:90]), 
		.se				(se));
	ccx_new_macro__type_c_l i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.data_crit_x_l			(data_crit_x_[109:100]), 
		.data_ncrit_x_l			(data_ncrit_x_[109:100]), 
		.se				(se));
	ccx_new_macro__type_c_l i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.data_crit_x_l			(data_crit_x_[119:110]), 
		.data_ncrit_x_l			(data_ncrit_x_[119:110]), 
		.se				(se));
	ccx_new_macro__type_c_l i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.data_crit_x_l			(data_crit_x_[129:120]), 
		.data_ncrit_x_l			(data_ncrit_x_[129:120]), 
		.se				(se));
	ccx_new_macro__type_c_l i13(
		.data_x_l			(data_out_x_[139:130]), 
		.scan_in			(i13_scanin), 
		.scan_out			(i13_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[139:130]), 
		.data_crit_x_l			(data_crit_x_[139:130]), 
		.data_ncrit_x_l			(data_ncrit_x_[139:130]), 
		.se				(se));
	ccx_new_macro__type_c_l i14(
		.data_x_l			(data_out_x_[149:140]), 
		.scan_in			(i14_scanin), 
		.scan_out			(i14_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[149:140]), 
		.data_crit_x_l			(data_crit_x_[149:140]), 
		.data_ncrit_x_l			(data_ncrit_x_[149:140]), 
		.se				(se));
endmodule


module ccx_new_macro__type_c_l(l2clk, l1clk, pce0, pce1, pce_ov, se, stop,
        siclk_in, soclk_in, scan_in, grant_a, qsel0, shift, data_a,
        data_crit_x_l, data_ncrit_x_l, data_x_l, scan_out);

        input                   l2clk;
        input                   l1clk;
        input                   pce0;
        input                   pce1;
        input                   pce_ov;
        input                   se;
        input                   stop;
        input                   siclk_in;
        input                   soclk_in;
        input                   scan_in;
        input                   grant_a;
        input                   qsel0;
        input                   shift;
        input   [9:0]           data_a;
        input   [9:0]           data_crit_x_l;
        input   [9:0]           data_ncrit_x_l;
        output  [9:0]           data_x_l;
        output                  scan_out;

        wire                    so5;
        wire                    siclk_out;
        wire                    soclk_out;
        wire                    l1clk0;
        wire                    l1clk1;
        wire                    grant_x;
        wire                    qsel0_buf;
        wire                    shift_buf;

        cl_dp1_ccxhdr c0(
                .si                             (scan_in),
                .so                             (so5),
                .l2clk                          (l2clk),
                .pce0                           (pce0),
                .pce1                           (pce1),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_in                       (siclk_in),
                .soclk_in                       (soclk_in),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .se                             (se),
                .l1clk                          (l1clk),
                .grant_a                        (grant_a),
                .grant_x                        (grant_x),
                .qsel0                          (qsel0),
                .qsel0_buf                      (qsel0_buf),
                .shift                          (shift),
                .shift_buf                      (shift_buf));
        ccx_mac_c #(10) mac_c(
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .data_a                         (data_a[9:0]),
                .data_crit_x_l                  (data_crit_x_l[9:0]),
                .data_ncrit_x_l                 (data_ncrit_x_l[9:0]),
                .data_x_l                       (data_x_l[9:0]),
                .si                             (so5),
                .so                             (scan_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .grant_x                        (grant_x),
                .qsel0_buf                      (qsel0_buf),
                .shift_buf                      (shift_buf));
endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_mcr_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_mcr_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_cpx_data_a, 
  data_crit_x_, 
  data_ncrit_x_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [149:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;
wire i13_scanin;
wire i13_scanout;
wire i14_scanin;
wire i14_scanout;


output [149:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [149:0]   src_cpx_data_a;
input [149:0]   data_crit_x_;
input [149:0]   data_ncrit_x_;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

assign src_data_a[149:0] = src_cpx_data_a[149:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);
//

//l1clkhdr_dp_macro gkt_hdra 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

cpx_mcr_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

cpx_mcr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

cpx_mcr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_c AUTO_TEMPLATE
// (
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.scan_in  (scan_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_crit_x_l   (data_crit_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_ncrit_x_l   (data_ncrit_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);


cpx_mcr_dp_ccx_new_macro__type_c_r i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),   // Templated
                .data_crit_x_l          (data_crit_x_[9:0]),     // Templated
                .data_ncrit_x_l         (data_ncrit_x_[9:0]),
  .se(se));    // Templated

cpx_mcr_dp_ccx_new_macro__type_c_r i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),  // Templated
                .data_crit_x_l          (data_crit_x_[19:10]),    // Templated
                .data_ncrit_x_l         (data_ncrit_x_[19:10]),
  .se(se));   // Templated

cpx_mcr_dp_ccx_new_macro__type_c_r i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]), // Templated
                .data_crit_x_l          (data_crit_x_[29:20]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[29:20]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]), // Templated
                .data_crit_x_l          (data_crit_x_[39:30]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[39:30]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]), // Templated
                .data_crit_x_l          (data_crit_x_[49:40]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[49:40]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]), // Templated
                .data_crit_x_l          (data_crit_x_[59:50]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[59:50]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]), // Templated
                .data_crit_x_l          (data_crit_x_[69:60]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[69:60]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]), // Templated
                .data_crit_x_l          (data_crit_x_[79:70]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[79:70]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]), // Templated
                .data_crit_x_l          (data_crit_x_[89:80]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[89:80]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]), // Templated
                .data_crit_x_l          (data_crit_x_[99:90]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[99:90]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]), // Templated
                 .data_crit_x_l         (data_crit_x_[109:100]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[109:100]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]), // Templated
                 .data_crit_x_l         (data_crit_x_[119:110]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[119:110]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]), // Templated
                 .data_crit_x_l         (data_crit_x_[129:120]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[129:120]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i13  (
                 // Outputs
                 .data_x_l              (data_out_x_[139:130]),    // Templated
                 // Inputs
                 .scan_in(i13_scanin),
                 .scan_out(i13_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[139:130]), // Templated
                 .data_crit_x_l         (data_crit_x_[139:130]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[139:130]),
  .se(se));  // Templated
cpx_mcr_dp_ccx_new_macro__type_c_r i14  (
                 // Outputs
                 .data_x_l              (data_out_x_[149:140]),    // Templated
                 // Inputs
                 .scan_in(i14_scanin),
                 .scan_out(i14_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[149:140]), // Templated
                 .data_crit_x_l         (data_crit_x_[149:140]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[149:140]),
  .se(se));  // Templated

// fixscan start:
assign i14_scanin                 = scan_in                  ;
assign i13_scanin                 = i14_scanout              ;
assign i12_scanin                 = i13_scanout              ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule // cpx_mcl_dp

//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=50c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=50c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[149:100]),
// .dout          (q1_dataout[149:100]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[99:50]),
// .dout          (q1_dataout[99:50]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_cpx_data_a[49:0]),
// .dout          (q1_dataout[49:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_cpxdp_qsel0_ca ? src_cpx_data_ca[149:0] : 150'd0) |
////	     (arb_cpxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[149:100]),
// .din1   (q1_dataout[149:100]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[149:100]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[99:50]),
// .din1   (q1_dataout[99:50]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[99:50]),
// );
//
//mux_macro i_mux_q0_0 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_cpx_data_a[49:0]),
// .din1   (q1_dataout[49:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[49:0]),
// );
//
//msff_macro i_dff_q0_2 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[149:100]),
// .dout          (q0_dataout[149:100]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[99:50]),
// .dout          (q0_dataout[99:50]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[49:0]),
// .dout          (q0_dataout[49:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[149:100]),
// .din1   ({{10{grant_x[11]}},{15{grant_x[10]}},{15{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[149:100]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[99:50]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[99:50]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[49:0]),
// .din1   ({{10{grant_x[3]}},{15{grant_x[2]}},{15{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[49:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[149:100]),
// .din1	(data_crit_x_[149:100]),
// .din2	(data_ncrit_x_[149:100]),
// .dout	(data_out_x[149:100])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[99:50]),
// .din1	(data_crit_x_[99:50]),
// .din2	(data_ncrit_x_[99:50]),
// .dout	(data_out_x[99:50])
//);
//
//nand_macro i_nand_data_crit_0 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[49:0]),
// .din1	(data_crit_x_[49:0]),
// .din2	(data_ncrit_x_[49:0]),
// .dout	(data_out_x[49:0])
//);
//
//inv_macro i_inv_data_out_2 (width=50, stack=50c) 
//(
// .din	(data_out_x[149:100]),
// .dout	(data_out_x_[149:100])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[99:50]),
// .dout	(data_out_x_[99:50])
// );
//
//inv_macro i_inv_data_out_0 (width=50, stack=50c) 
//(
// .din	(data_out_x[49:0]),
// .dout	(data_out_x_[49:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule


//
//   buff macro
//
//


module cpx_mcr_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module cpx_mcr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module cpx_mcr_dp_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_mcr_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_cpx_data_a, data_crit_x_, 
	data_ncrit_x_, l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, 
	tcu_scan_en, scan_out, ccx_aclk_out, ccx_bclk_out, tcu_pce_ov_out, 
	tcu_scan_en_out);

	output	[149:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[149:0]		src_cpx_data_a;
	input	[149:0]		data_crit_x_;
	input	[149:0]		data_ncrit_x_;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[149:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;
	wire			i13_scanin;
	wire			i13_scanout;
	wire			i14_scanin;
	wire			i14_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[149:0] = src_cpx_data_a[149:0];
	assign i14_scanin = scan_in;
	assign i13_scanin = i14_scanout;
	assign i12_scanin = i13_scanout;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_c_r i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.data_crit_x_l			(data_crit_x_[9:0]), 
		.data_ncrit_x_l			(data_ncrit_x_[9:0]), 
		.se				(se));
	ccx_new_macro__type_c_r i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.data_crit_x_l			(data_crit_x_[19:10]), 
		.data_ncrit_x_l			(data_ncrit_x_[19:10]), 
		.se				(se));
	ccx_new_macro__type_c_r i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.data_crit_x_l			(data_crit_x_[29:20]), 
		.data_ncrit_x_l			(data_ncrit_x_[29:20]), 
		.se				(se));
	ccx_new_macro__type_c_r i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.data_crit_x_l			(data_crit_x_[39:30]), 
		.data_ncrit_x_l			(data_ncrit_x_[39:30]), 
		.se				(se));
	ccx_new_macro__type_c_r i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.data_crit_x_l			(data_crit_x_[49:40]), 
		.data_ncrit_x_l			(data_ncrit_x_[49:40]), 
		.se				(se));
	ccx_new_macro__type_c_r i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.data_crit_x_l			(data_crit_x_[59:50]), 
		.data_ncrit_x_l			(data_ncrit_x_[59:50]), 
		.se				(se));
	ccx_new_macro__type_c_r i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.data_crit_x_l			(data_crit_x_[69:60]), 
		.data_ncrit_x_l			(data_ncrit_x_[69:60]), 
		.se				(se));
	ccx_new_macro__type_c_r i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.data_crit_x_l			(data_crit_x_[79:70]), 
		.data_ncrit_x_l			(data_ncrit_x_[79:70]), 
		.se				(se));
	ccx_new_macro__type_c_r i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.data_crit_x_l			(data_crit_x_[89:80]), 
		.data_ncrit_x_l			(data_ncrit_x_[89:80]), 
		.se				(se));
	ccx_new_macro__type_c_r i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.data_crit_x_l			(data_crit_x_[99:90]), 
		.data_ncrit_x_l			(data_ncrit_x_[99:90]), 
		.se				(se));
	ccx_new_macro__type_c_r i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.data_crit_x_l			(data_crit_x_[109:100]), 
		.data_ncrit_x_l			(data_ncrit_x_[109:100]), 
		.se				(se));
	ccx_new_macro__type_c_r i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.data_crit_x_l			(data_crit_x_[119:110]), 
		.data_ncrit_x_l			(data_ncrit_x_[119:110]), 
		.se				(se));
	ccx_new_macro__type_c_r i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.data_crit_x_l			(data_crit_x_[129:120]), 
		.data_ncrit_x_l			(data_ncrit_x_[129:120]), 
		.se				(se));
	ccx_new_macro__type_c_r i13(
		.data_x_l			(data_out_x_[139:130]), 
		.scan_in			(i13_scanin), 
		.scan_out			(i13_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[139:130]), 
		.data_crit_x_l			(data_crit_x_[139:130]), 
		.data_ncrit_x_l			(data_ncrit_x_[139:130]), 
		.se				(se));
	ccx_new_macro__type_c_r i14(
		.data_x_l			(data_out_x_[149:140]), 
		.scan_in			(i14_scanin), 
		.scan_out			(i14_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[149:140]), 
		.data_crit_x_l			(data_crit_x_[149:140]), 
		.data_ncrit_x_l			(data_ncrit_x_[149:140]), 
		.se				(se));
endmodule

module ccx_new_macro__type_c_r(l2clk, l1clk, pce0, pce1, pce_ov, se, stop,
        siclk_in, soclk_in, scan_in, grant_a, qsel0, shift, data_a,
        data_crit_x_l, data_ncrit_x_l, data_x_l, scan_out);

        input                   l2clk;
        input                   l1clk;
        input                   pce0;
        input                   pce1;
        input                   pce_ov;
        input                   se;
        input                   stop;
        input                   siclk_in;
        input                   soclk_in;
        input                   scan_in;
        input                   grant_a;
        input                   qsel0;
        input                   shift;
        input   [9:0]           data_a;
        input   [9:0]           data_crit_x_l;
        input   [9:0]           data_ncrit_x_l;
        output  [9:0]           data_x_l;
        output                  scan_out;

        wire                    so5;
        wire                    siclk_out;
        wire                    soclk_out;
        wire                    l1clk0;
        wire                    l1clk1;
        wire                    grant_x;
        wire                    qsel0_buf;
        wire                    shift_buf;

        cl_dp1_ccxhdr c0(
                .si                             (scan_in),
                .so                             (so5),
                .l2clk                          (l2clk),
                .pce0                           (pce0),
                .pce1                           (pce1),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_in                       (siclk_in),
                .soclk_in                       (soclk_in),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .se                             (se),
                .l1clk                          (l1clk),
                .grant_a                        (grant_a),
                .grant_x                        (grant_x),
                .qsel0                          (qsel0),
                .qsel0_buf                      (qsel0_buf),
                .shift                          (shift),
                .shift_buf                      (shift_buf));
        ccx_mac_c #(10) mac_c(
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .data_a                         (data_a[9:0]),
                .data_crit_x_l                  (data_crit_x_l[9:0]),
                .data_ncrit_x_l                 (data_ncrit_x_l[9:0]),

                .data_x_l                       (data_x_l[9:0]),
                .si                             (so5),
                .so                             (scan_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .grant_x                        (grant_x),
                .qsel0_buf                      (qsel0_buf),
                .shift_buf                      (shift_buf));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_ob1_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_ob1_dp (
  cpx_spc_data_cx2, 
  cpx_spc_data_cx2_prebuf);
wire [145:0] in;
wire [145:0] in_swz;
wire [145:0] in_px2;
wire [145:0] out_swz;


output [145:0] cpx_spc_data_cx2;

input [145:0] cpx_spc_data_cx2_prebuf;


assign in[145:0] = cpx_spc_data_cx2_prebuf[145:0];
assign in_swz[72:0] =     {
                           in[144],in[142],in[140],
                           in[138],in[136],in[134],in[132],in[130],in[128],in[126],in[124],in[122],in[120],
                           in[118],in[116],in[114],in[112],in[110],in[108],in[106],in[104],in[102],in[100],
                           in[98],in[96],in[94],in[92],in[90],in[88],in[86],in[84],in[82],in[80],
                           in[78],in[76],in[74],in[72],in[70],in[68],in[66],in[64],in[62],in[60],
                           in[58],in[56],in[54],in[52],in[50],in[48],in[46],in[44],in[42],in[40],
                           in[38],in[36],in[34],in[32],in[30],in[28],in[26],in[24],in[22],in[20],
                           in[18],in[16],in[14],in[12],in[10],in[8],in[6],in[4],in[2],in[0]
                           };


assign in_swz[145:73] =   {
                           in[145],in[143],in[141],
                           in[139],in[137],in[135],in[133],in[131],in[129],in[127],in[125],in[123],in[121],
                           in[119],in[117],in[115],in[113],in[111],in[109],in[107],in[105],in[103],in[101],
                           in[99],in[97],in[95],in[93],in[91],in[89],in[87],in[85],in[83],in[81],
                           in[79],in[77],in[75],in[73],in[71],in[69],in[67],in[65],in[63],in[61],
                           in[59],in[57],in[55],in[53],in[51],in[49],in[47],in[45],in[43],in[41],
                           in[39],in[37],in[35],in[33],in[31],in[29],in[27],in[25],in[23],in[21],
                           in[19],in[17],in[15],in[13],in[11],in[9],in[7],in[5],in[3],in[1]
                           };


cpx_ob1_dp_buff_macro__dbuff_32x__rep_1__stack_74c__width_73 i_buf_data_0     (
	.din	({in_swz[72:0] }),
	.dout	({in_px2[72:0]})
);

cpx_ob1_dp_buff_macro__dbuff_32x__rep_1__stack_74c__width_73 i_buf_data_1     (
	.din	({in_swz[145:73]}),
	.dout	({in_px2[145:73]})
);


assign {
        out_swz[144],out_swz[142],out_swz[140],
        out_swz[138],out_swz[136],out_swz[134],out_swz[132],out_swz[130],out_swz[128],out_swz[126],out_swz[124],out_swz[122],out_swz[120],
        out_swz[118],out_swz[116],out_swz[114],out_swz[112],out_swz[110],out_swz[108],out_swz[106],out_swz[104],out_swz[102],out_swz[100],
        out_swz[98],out_swz[96],out_swz[94],out_swz[92],out_swz[90],out_swz[88],out_swz[86],out_swz[84],out_swz[82],out_swz[80],
        out_swz[78],out_swz[76],out_swz[74],out_swz[72],out_swz[70],out_swz[68],out_swz[66],out_swz[64],out_swz[62],out_swz[60],
        out_swz[58],out_swz[56],out_swz[54],out_swz[52],out_swz[50],out_swz[48],out_swz[46],out_swz[44],out_swz[42],out_swz[40],
        out_swz[38],out_swz[36],out_swz[34],out_swz[32],out_swz[30],out_swz[28],out_swz[26],out_swz[24],out_swz[22],out_swz[20],
        out_swz[18],out_swz[16],out_swz[14],out_swz[12],out_swz[10],out_swz[8],out_swz[6],out_swz[4],out_swz[2],out_swz[0]
        } = in_px2[72:0];


assign {
        out_swz[145],out_swz[143],out_swz[141],
        out_swz[139],out_swz[137],out_swz[135],out_swz[133],out_swz[131],out_swz[129],out_swz[127],out_swz[125],out_swz[123],out_swz[121],
        out_swz[119],out_swz[117],out_swz[115],out_swz[113],out_swz[111],out_swz[109],out_swz[107],out_swz[105],out_swz[103],out_swz[101],
        out_swz[99],out_swz[97],out_swz[95],out_swz[93],out_swz[91],out_swz[89],out_swz[87],out_swz[85],out_swz[83],out_swz[81],
        out_swz[79],out_swz[77],out_swz[75],out_swz[73],out_swz[71],out_swz[69],out_swz[67],out_swz[65],out_swz[63],out_swz[61],
        out_swz[59],out_swz[57],out_swz[55],out_swz[53],out_swz[51],out_swz[49],out_swz[47],out_swz[45],out_swz[43],out_swz[41],
        out_swz[39],out_swz[37],out_swz[35],out_swz[33],out_swz[31],out_swz[29],out_swz[27],out_swz[25],out_swz[23],out_swz[21],
        out_swz[19],out_swz[17],out_swz[15],out_swz[13],out_swz[11],out_swz[9],out_swz[7],out_swz[5],out_swz[3],out_swz[1]
        } = in_px2[145:73];


assign cpx_spc_data_cx2[145:0] = out_swz[145:0];

endmodule // cpx_bfs_dp


//
//   buff macro
//
//


module cpx_ob1_dp_buff_macro__dbuff_32x__rep_1__stack_74c__width_73 (
  din, 
  dout);
  input [72:0] din;
  output [72:0] dout;


buff #(73)  d0_0 (
.in(din[72:0]),
.out(dout[72:0])
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_ob1_dp(cpx_spc_data_cx2, cpx_spc_data_cx2_prebuf);

	output	[145:0]		cpx_spc_data_cx2;
	input	[145:0]		cpx_spc_data_cx2_prebuf;

	wire	[145:0]		in;
	wire	[145:0]		in_swz;
	wire	[145:0]		in_px2;
	wire	[145:0]		out_swz;

	assign in[145:0] = cpx_spc_data_cx2_prebuf[145:0];
	assign in_swz[72:0] = {in[144], in[142], in[140], in[138], in[136], 
		in[134], in[132], in[130], in[128], in[126], in[124], in[122], 
		in[120], in[118], in[116], in[114], in[112], in[110], in[108], 
		in[106], in[104], in[102], in[100], in[98], in[96], in[94], 
		in[92], in[90], in[88], in[86], in[84], in[82], in[80], in[78], 
		in[76], in[74], in[72], in[70], in[68], in[66], in[64], in[62], 
		in[60], in[58], in[56], in[54], in[52], in[50], in[48], in[46], 
		in[44], in[42], in[40], in[38], in[36], in[34], in[32], in[30], 
		in[28], in[26], in[24], in[22], in[20], in[18], in[16], in[14], 
		in[12], in[10], in[8], in[6], in[4], in[2], in[0]};
	assign in_swz[145:73] = {in[145], in[143], in[141], in[139], in[137], 
		in[135], in[133], in[131], in[129], in[127], in[125], in[123], 
		in[121], in[119], in[117], in[115], in[113], in[111], in[109], 
		in[107], in[105], in[103], in[101], in[99], in[97], in[95], 
		in[93], in[91], in[89], in[87], in[85], in[83], in[81], in[79], 
		in[77], in[75], in[73], in[71], in[69], in[67], in[65], in[63], 
		in[61], in[59], in[57], in[55], in[53], in[51], in[49], in[47], 
		in[45], in[43], in[41], in[39], in[37], in[35], in[33], in[31], 
		in[29], in[27], in[25], in[23], in[21], in[19], in[17], in[15], 
		in[13], in[11], in[9], in[7], in[5], in[3], in[1]};
	assign {out_swz[144], out_swz[142], out_swz[140], out_swz[138], 
		out_swz[136], out_swz[134], out_swz[132], out_swz[130], 
		out_swz[128], out_swz[126], out_swz[124], out_swz[122], 
		out_swz[120], out_swz[118], out_swz[116], out_swz[114], 
		out_swz[112], out_swz[110], out_swz[108], out_swz[106], 
		out_swz[104], out_swz[102], out_swz[100], out_swz[98], 
		out_swz[96], out_swz[94], out_swz[92], out_swz[90], out_swz[88],
		out_swz[86], out_swz[84], out_swz[82], out_swz[80], out_swz[78],
		out_swz[76], out_swz[74], out_swz[72], out_swz[70], out_swz[68],
		out_swz[66], out_swz[64], out_swz[62], out_swz[60], out_swz[58],
		out_swz[56], out_swz[54], out_swz[52], out_swz[50], out_swz[48],
		out_swz[46], out_swz[44], out_swz[42], out_swz[40], out_swz[38],
		out_swz[36], out_swz[34], out_swz[32], out_swz[30], out_swz[28],
		out_swz[26], out_swz[24], out_swz[22], out_swz[20], out_swz[18],
		out_swz[16], out_swz[14], out_swz[12], out_swz[10], out_swz[8], 
		out_swz[6], out_swz[4], out_swz[2], out_swz[0]} = in_px2[72:0];
	assign {out_swz[145], out_swz[143], out_swz[141], out_swz[139], 
		out_swz[137], out_swz[135], out_swz[133], out_swz[131], 
		out_swz[129], out_swz[127], out_swz[125], out_swz[123], 
		out_swz[121], out_swz[119], out_swz[117], out_swz[115], 
		out_swz[113], out_swz[111], out_swz[109], out_swz[107], 
		out_swz[105], out_swz[103], out_swz[101], out_swz[99], 
		out_swz[97], out_swz[95], out_swz[93], out_swz[91], out_swz[89],
		out_swz[87], out_swz[85], out_swz[83], out_swz[81], out_swz[79],
		out_swz[77], out_swz[75], out_swz[73], out_swz[71], out_swz[69],
		out_swz[67], out_swz[65], out_swz[63], out_swz[61], out_swz[59],
		out_swz[57], out_swz[55], out_swz[53], out_swz[51], out_swz[49],
		out_swz[47], out_swz[45], out_swz[43], out_swz[41], out_swz[39],
		out_swz[37], out_swz[35], out_swz[33], out_swz[31], out_swz[29],
		out_swz[27], out_swz[25], out_swz[23], out_swz[21], out_swz[19],
		out_swz[17], out_swz[15], out_swz[13], out_swz[11], out_swz[9], 
		out_swz[7], out_swz[5], out_swz[3], out_swz[1]} = in_px2[145:73]
		;
	assign cpx_spc_data_cx2[145:0] = out_swz[145:0];

	buff_macro__dbuff_32x__rep_1__stack_74c__width_73 i_buf_data_0(
		.din				({in_swz[72:0]}), 
		.dout				({in_px2[72:0]}));
	buff_macro__dbuff_32x__rep_1__stack_74c__width_73 i_buf_data_1(
		.din				({in_swz[145:73]}), 
		.dout				({in_px2[145:73]}));
endmodule

module buff_macro__dbuff_32x__rep_1__stack_74c__width_73(din, dout);

        input   [72:0]          din;
        output  [72:0]          dout;

        buff #(73) d0_0(
                .in                             (din[72:0]),
                .out                            (dout[72:0]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_ob2_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_ob2_dp (
  cpx_spc_data_cx2, 
  cpx_spc_data_cx2_prebuf);
wire [145:0] in;
wire [145:0] in_swz;
wire [145:0] in_px2;
wire [145:0] out_swz;


output [145:0] cpx_spc_data_cx2;

input [145:0] cpx_spc_data_cx2_prebuf;


assign in[145:0] = cpx_spc_data_cx2_prebuf[145:0];
assign in_swz[72:0] =     {
                           in[0],in[2],in[4],in[6],in[8],in[10],in[12],in[14],in[16],in[18],
                           in[20],in[22],in[24],in[26],in[28],in[30],in[32],in[34],in[36],in[38],
                           in[40],in[42],in[44],in[46],in[48],in[50],in[52],in[54],in[56],in[58],
                           in[60],in[62],in[64],in[66],in[68],in[70],in[72],in[74],in[76],in[78],
                           in[80],in[82],in[84],in[86],in[88],in[90],in[92],in[94],in[96],in[98],
                           in[100],in[102],in[104],in[106],in[108],in[110],in[112],in[114],in[116],in[118],
                           in[120],in[122],in[124],in[126],in[128],in[130],in[132],in[134],in[136],in[138],
                           in[140],in[142],in[144]                                                        
                           };


assign in_swz[145:73] =   {
                           in[1],in[3],in[5],in[7],in[9],in[11],in[13],in[15],in[17],in[19],
                           in[21],in[23],in[25],in[27],in[29],in[31],in[33],in[35],in[37],in[39],
                           in[41],in[43],in[45],in[47],in[49],in[51],in[53],in[55],in[57],in[59],
                           in[61],in[63],in[65],in[67],in[69],in[71],in[73],in[75],in[77],in[79],
                           in[81],in[83],in[85],in[87],in[89],in[91],in[93],in[95],in[97],in[99],
                           in[101],in[103],in[105],in[107],in[109],in[111],in[113],in[115],in[117],in[119],
                           in[121],in[123],in[125],in[127],in[129],in[131],in[133],in[135],in[137],in[139],
                           in[141],in[143],in[145]                                                                                   
                           };


cpx_ob2_dp_buff_macro__dbuff_32x__rep_1__stack_74c__width_73 i_buf_data_0     (
	.din	({in_swz[72:0] }),
	.dout	({in_px2[72:0]})
);

cpx_ob2_dp_buff_macro__dbuff_32x__rep_1__stack_74c__width_73 i_buf_data_1     (
	.din	({in_swz[145:73]}),
	.dout	({in_px2[145:73]})
);


assign {
        out_swz[0],out_swz[2],out_swz[4],out_swz[6],out_swz[8],out_swz[10],out_swz[12],out_swz[14],out_swz[16],out_swz[18],
        out_swz[20],out_swz[22],out_swz[24],out_swz[26],out_swz[28],out_swz[30],out_swz[32],out_swz[34],out_swz[36],out_swz[38],
        out_swz[40],out_swz[42],out_swz[44],out_swz[46],out_swz[48],out_swz[50],out_swz[52],out_swz[54],out_swz[56],out_swz[58],
        out_swz[60],out_swz[62],out_swz[64],out_swz[66],out_swz[68],out_swz[70],out_swz[72],out_swz[74],out_swz[76],out_swz[78],
        out_swz[80],out_swz[82],out_swz[84],out_swz[86],out_swz[88],out_swz[90],out_swz[92],out_swz[94],out_swz[96],out_swz[98],
        out_swz[100],out_swz[102],out_swz[104],out_swz[106],out_swz[108],out_swz[110],out_swz[112],out_swz[114],out_swz[116],out_swz[118],
        out_swz[120],out_swz[122],out_swz[124],out_swz[126],out_swz[128],out_swz[130],out_swz[132],out_swz[134],out_swz[136],out_swz[138],
        out_swz[140],out_swz[142],out_swz[144]                                                        
        } = in_px2[72:0];


assign {
        out_swz[1],out_swz[3],out_swz[5],out_swz[7],out_swz[9],out_swz[11],out_swz[13],out_swz[15],out_swz[17],out_swz[19],
        out_swz[21],out_swz[23],out_swz[25],out_swz[27],out_swz[29],out_swz[31],out_swz[33],out_swz[35],out_swz[37],out_swz[39],
        out_swz[41],out_swz[43],out_swz[45],out_swz[47],out_swz[49],out_swz[51],out_swz[53],out_swz[55],out_swz[57],out_swz[59],
        out_swz[61],out_swz[63],out_swz[65],out_swz[67],out_swz[69],out_swz[71],out_swz[73],out_swz[75],out_swz[77],out_swz[79],
        out_swz[81],out_swz[83],out_swz[85],out_swz[87],out_swz[89],out_swz[91],out_swz[93],out_swz[95],out_swz[97],out_swz[99],
        out_swz[101],out_swz[103],out_swz[105],out_swz[107],out_swz[109],out_swz[111],out_swz[113],out_swz[115],out_swz[117],out_swz[119],
        out_swz[121],out_swz[123],out_swz[125],out_swz[127],out_swz[129],out_swz[131],out_swz[133],out_swz[135],out_swz[137],out_swz[139],
        out_swz[141],out_swz[143],out_swz[145]                                                                                   
        } = in_px2[145:73];


assign cpx_spc_data_cx2[145:0] = out_swz[145:0];

endmodule // cpx_bfs_dp


//
//   buff macro
//
//


module cpx_ob2_dp_buff_macro__dbuff_32x__rep_1__stack_74c__width_73 (
  din, 
  dout);
  input [72:0] din;
  output [72:0] dout;


buff #(73)  d0_0 (
.in(din[72:0]),
.out(dout[72:0])
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_ob2_dp(cpx_spc_data_cx2, cpx_spc_data_cx2_prebuf);

	output	[145:0]		cpx_spc_data_cx2;
	input	[145:0]		cpx_spc_data_cx2_prebuf;

	wire	[145:0]		in;
	wire	[145:0]		in_swz;
	wire	[145:0]		in_px2;
	wire	[145:0]		out_swz;

	assign in[145:0] = cpx_spc_data_cx2_prebuf[145:0];
	assign in_swz[72:0] = {in[0], in[2], in[4], in[6], in[8], in[10], 
		in[12], in[14], in[16], in[18], in[20], in[22], in[24], in[26], 
		in[28], in[30], in[32], in[34], in[36], in[38], in[40], in[42], 
		in[44], in[46], in[48], in[50], in[52], in[54], in[56], in[58], 
		in[60], in[62], in[64], in[66], in[68], in[70], in[72], in[74], 
		in[76], in[78], in[80], in[82], in[84], in[86], in[88], in[90], 
		in[92], in[94], in[96], in[98], in[100], in[102], in[104], 
		in[106], in[108], in[110], in[112], in[114], in[116], in[118], 
		in[120], in[122], in[124], in[126], in[128], in[130], in[132], 
		in[134], in[136], in[138], in[140], in[142], in[144]};
	assign in_swz[145:73] = {in[1], in[3], in[5], in[7], in[9], in[11], 
		in[13], in[15], in[17], in[19], in[21], in[23], in[25], in[27], 
		in[29], in[31], in[33], in[35], in[37], in[39], in[41], in[43], 
		in[45], in[47], in[49], in[51], in[53], in[55], in[57], in[59], 
		in[61], in[63], in[65], in[67], in[69], in[71], in[73], in[75], 
		in[77], in[79], in[81], in[83], in[85], in[87], in[89], in[91], 
		in[93], in[95], in[97], in[99], in[101], in[103], in[105], 
		in[107], in[109], in[111], in[113], in[115], in[117], in[119], 
		in[121], in[123], in[125], in[127], in[129], in[131], in[133], 
		in[135], in[137], in[139], in[141], in[143], in[145]};
	assign {out_swz[0], out_swz[2], out_swz[4], out_swz[6], out_swz[8], 
		out_swz[10], out_swz[12], out_swz[14], out_swz[16], out_swz[18],
		out_swz[20], out_swz[22], out_swz[24], out_swz[26], out_swz[28],
		out_swz[30], out_swz[32], out_swz[34], out_swz[36], out_swz[38],
		out_swz[40], out_swz[42], out_swz[44], out_swz[46], out_swz[48],
		out_swz[50], out_swz[52], out_swz[54], out_swz[56], out_swz[58],
		out_swz[60], out_swz[62], out_swz[64], out_swz[66], out_swz[68],
		out_swz[70], out_swz[72], out_swz[74], out_swz[76], out_swz[78],
		out_swz[80], out_swz[82], out_swz[84], out_swz[86], out_swz[88],
		out_swz[90], out_swz[92], out_swz[94], out_swz[96], out_swz[98],
		out_swz[100], out_swz[102], out_swz[104], out_swz[106], 
		out_swz[108], out_swz[110], out_swz[112], out_swz[114], 
		out_swz[116], out_swz[118], out_swz[120], out_swz[122], 
		out_swz[124], out_swz[126], out_swz[128], out_swz[130], 
		out_swz[132], out_swz[134], out_swz[136], out_swz[138], 
		out_swz[140], out_swz[142], out_swz[144]} = in_px2[72:0];
	assign {out_swz[1], out_swz[3], out_swz[5], out_swz[7], out_swz[9], 
		out_swz[11], out_swz[13], out_swz[15], out_swz[17], out_swz[19],
		out_swz[21], out_swz[23], out_swz[25], out_swz[27], out_swz[29],
		out_swz[31], out_swz[33], out_swz[35], out_swz[37], out_swz[39],
		out_swz[41], out_swz[43], out_swz[45], out_swz[47], out_swz[49],
		out_swz[51], out_swz[53], out_swz[55], out_swz[57], out_swz[59],
		out_swz[61], out_swz[63], out_swz[65], out_swz[67], out_swz[69],
		out_swz[71], out_swz[73], out_swz[75], out_swz[77], out_swz[79],
		out_swz[81], out_swz[83], out_swz[85], out_swz[87], out_swz[89],
		out_swz[91], out_swz[93], out_swz[95], out_swz[97], out_swz[99],
		out_swz[101], out_swz[103], out_swz[105], out_swz[107], 
		out_swz[109], out_swz[111], out_swz[113], out_swz[115], 
		out_swz[117], out_swz[119], out_swz[121], out_swz[123], 
		out_swz[125], out_swz[127], out_swz[129], out_swz[131], 
		out_swz[133], out_swz[135], out_swz[137], out_swz[139], 
		out_swz[141], out_swz[143], out_swz[145]} = in_px2[145:73];
	assign cpx_spc_data_cx2[145:0] = out_swz[145:0];

	buff_macro__dbuff_32x__rep_1__stack_74c__width_73 i_buf_data_0(
		.din				({in_swz[72:0]}), 
		.dout				({in_px2[72:0]}));
	buff_macro__dbuff_32x__rep_1__stack_74c__width_73 i_buf_data_1(
		.din				({in_swz[145:73]}), 
		.dout				({in_px2[145:73]}));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpx_rep_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module cpx_rep_dp (
  mac0_rep_out, 
  mac1_rep_out, 
  mac2_rep_out, 
  mac3_rep_out, 
  mac4_rep_out, 
  mac5_rep_out, 
  mac6_rep_out, 
  scan_rep_out, 
  mac0_rep_in, 
  mac1_rep_in, 
  mac2_rep_in, 
  mac3_rep_in, 
  mac4_rep_in, 
  mac5_rep_in, 
  mac6_rep_in, 
  scan_rep_in);
wire [4:0] mac2_rep_0;
wire [4:0] mac3_rep_0;
wire [4:0] mac4_rep_0;
wire scan_rep7_out;
wire scan_rep5_out;
wire scan_rep3_out;
wire scan_rep1_out;


output [4:0]              mac0_rep_out;
output [4:0]              mac1_rep_out;
output [4:0]              mac2_rep_out;
output [4:0]              mac3_rep_out;
output [4:0]              mac4_rep_out;
output [4:0]              mac5_rep_out;
output [4:0]              mac6_rep_out;
output                    scan_rep_out;


input [4:0]              mac0_rep_in;
input [4:0]              mac1_rep_in;
input [4:0]              mac2_rep_in;
input [4:0]              mac3_rep_in;
input [4:0]              mac4_rep_in;
input [4:0]              mac5_rep_in;
input [4:0]              mac6_rep_in;
input                    scan_rep_in;


//      io    scache2 scache0 scache3 scache1  scache7  scache5  scache6  scache4
//       |       |      |       |       |        |        |        |       |     
//       v       v      v       v       v        v        v        v       v    
//      mac8-  mac0  - mac1   -mac2  - mac3  -  mac4   - mac5  - mac6   - mac7   


// mac0 input go through 1 buffer
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0    (
	.din	({mac0_rep_in[4:0]}),
   .dout	({mac0_rep_out[4:0]})
);

// mac1 input go through 1 buffer
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1    (
	.din	({mac1_rep_in[4:0]}),
   .dout	({mac1_rep_out[4:0]})
);


// mac2 input go through 2 buffers
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0    (
	.din	({mac2_rep_in[4:0]}),
   .dout	({mac2_rep_0[4:0]})
);

cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1    (
	.din	({mac2_rep_0[4:0]}),
   .dout	({mac2_rep_out[4:0]})
);

// mac3 input go through 2 buffers
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0    (
	.din	({mac3_rep_in[4:0]}),
   .dout	({mac3_rep_0[4:0]})
);

cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1    (
	.din	({mac3_rep_0[4:0]}),
   .dout	({mac3_rep_out[4:0]})
);

// mac4 input go through 2 buffers
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0    (
	.din	({mac4_rep_in[4:0]}),
   .dout	({mac4_rep_0[4:0]})
);

cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1    (
	.din	({mac4_rep_0[4:0]}),
   .dout	({mac4_rep_out[4:0]})
);

// mac5 input go through 1 buffer
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5    (
	.din	({mac5_rep_in[4:0]}),
   .dout	({mac5_rep_out[4:0]})
);

// mac6 input go through 1 buffer
cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6    (
	.din	({mac6_rep_in[4:0]}),
   .dout	({mac6_rep_out[4:0]})
);


// repeat the scan chain

// buffer on top of mac7
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan7    (
	.din	(scan_rep_in),
   .dout	(scan_rep7_out)
);

// buffer on top of mac5
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan5    (
	.din	(scan_rep7_out),
   .dout	(scan_rep5_out)
);

// buffer on top of mac3
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan3    (
	.din	(scan_rep5_out),
   .dout	(scan_rep3_out)
);

// buffer on top of mac1
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan1    (
	.din	(scan_rep3_out),
   .dout	(scan_rep1_out)
);

// buffer on top of mac8
cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan8    (
	.din	(scan_rep1_out),
   .dout	(scan_rep_out)
);

endmodule


//
//   buff macro
//
//


module cpx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module cpx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module cpx_rep_dp(mac0_rep_out, mac1_rep_out, mac2_rep_out, mac3_rep_out, 
	mac4_rep_out, mac5_rep_out, mac6_rep_out, scan_rep_out, mac0_rep_in, 
	mac1_rep_in, mac2_rep_in, mac3_rep_in, mac4_rep_in, mac5_rep_in, 
	mac6_rep_in, scan_rep_in);

	output	[4:0]		mac0_rep_out;
	output	[4:0]		mac1_rep_out;
	output	[4:0]		mac2_rep_out;
	output	[4:0]		mac3_rep_out;
	output	[4:0]		mac4_rep_out;
	output	[4:0]		mac5_rep_out;
	output	[4:0]		mac6_rep_out;
	output			scan_rep_out;
	input	[4:0]		mac0_rep_in;
	input	[4:0]		mac1_rep_in;
	input	[4:0]		mac2_rep_in;
	input	[4:0]		mac3_rep_in;
	input	[4:0]		mac4_rep_in;
	input	[4:0]		mac5_rep_in;
	input	[4:0]		mac6_rep_in;
	input			scan_rep_in;

	wire	[4:0]		mac2_rep_0;
	wire	[4:0]		mac3_rep_0;
	wire	[4:0]		mac4_rep_0;
	wire			scan_rep7_out;
	wire			scan_rep5_out;
	wire			scan_rep3_out;
	wire			scan_rep1_out;

	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0(
		.din				({mac0_rep_in[4:0]}), 
		.dout				({mac0_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1(
		.din				({mac1_rep_in[4:0]}), 
		.dout				({mac1_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0(
		.din				({mac2_rep_in[4:0]}), 
		.dout				({mac2_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1(
		.din				({mac2_rep_0[4:0]}), 
		.dout				({mac2_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0(
		.din				({mac3_rep_in[4:0]}), 
		.dout				({mac3_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1(
		.din				({mac3_rep_0[4:0]}), 
		.dout				({mac3_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0(
		.din				({mac4_rep_in[4:0]}), 
		.dout				({mac4_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1(
		.din				({mac4_rep_0[4:0]}), 
		.dout				({mac4_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5(
		.din				({mac5_rep_in[4:0]}), 
		.dout				({mac5_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6(
		.din				({mac6_rep_in[4:0]}), 
		.dout				({mac6_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan7(
		.din				(scan_rep_in), 
		.dout				(scan_rep7_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan5(
		.din				(scan_rep7_out), 
		.dout				(scan_rep5_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan3(
		.din				(scan_rep5_out), 
		.dout				(scan_rep3_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan1(
		.din				(scan_rep3_out), 
		.dout				(scan_rep1_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan8(
		.din				(scan_rep1_out), 
		.dout				(scan_rep_out));
endmodule

module buff_macro__dbuff_32x__stack_6l__width_5(din, dout);

        input   [4:0]           din;
        output  [4:0]           dout;

        buff #(5) d0_0(
                .in                             (din[4:0]),
                .out                            (dout[4:0]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx (
  pcx_fpio_data_px2, 
  pcx_fpio_data_rdy_px1, 
  pcx_sctag0_atm_px1, 
  pcx_sctag0_data_px2, 
  pcx_sctag0_data_rdy_px1, 
  pcx_sctag1_atm_px1, 
  pcx_sctag1_data_px2, 
  pcx_sctag1_data_rdy_px1, 
  pcx_sctag2_atm_px1, 
  pcx_sctag2_data_px2, 
  pcx_sctag2_data_rdy_px1, 
  pcx_sctag3_atm_px1, 
  pcx_sctag3_data_px2, 
  pcx_sctag3_data_rdy_px1, 
  pcx_sctag4_atm_px1, 
  pcx_sctag4_data_px2, 
  pcx_sctag4_data_rdy_px1, 
  pcx_sctag5_atm_px1, 
  pcx_sctag5_data_px2, 
  pcx_sctag5_data_rdy_px1, 
  pcx_sctag6_atm_px1, 
  pcx_sctag6_data_px2, 
  pcx_sctag6_data_rdy_px1, 
  pcx_sctag7_atm_px1, 
  pcx_sctag7_data_px2, 
  pcx_sctag7_data_rdy_px1, 
  pcx_spc0_grant_px, 
  pcx_spc1_grant_px, 
  pcx_spc2_grant_px, 
  pcx_spc3_grant_px, 
  pcx_spc4_grant_px, 
  pcx_spc5_grant_px, 
  pcx_spc6_grant_px, 
  pcx_spc7_grant_px, 
  io_pcx_stall_pq, 
  sctag0_pcx_stall_pq, 
  sctag1_pcx_stall_pq, 
  sctag2_pcx_stall_pq, 
  sctag3_pcx_stall_pq, 
  sctag4_pcx_stall_pq, 
  sctag5_pcx_stall_pq, 
  sctag6_pcx_stall_pq, 
  sctag7_pcx_stall_pq, 
  spc0_pcx_data_pa, 
  spc0_pcx_req_pq, 
  spc0_pcx_atm_pq, 
  spc1_pcx_data_pa, 
  spc1_pcx_req_pq, 
  spc1_pcx_atm_pq, 
  spc2_pcx_data_pa, 
  spc2_pcx_req_pq, 
  spc2_pcx_atm_pq, 
  spc3_pcx_data_pa, 
  spc3_pcx_req_pq, 
  spc3_pcx_atm_pq, 
  spc4_pcx_data_pa, 
  spc4_pcx_req_pq, 
  spc4_pcx_atm_pq, 
  spc5_pcx_data_pa, 
  spc5_pcx_req_pq, 
  spc5_pcx_atm_pq, 
  spc6_pcx_data_pa, 
  spc6_pcx_req_pq, 
  spc6_pcx_atm_pq, 
  spc7_pcx_data_pa, 
  spc7_pcx_req_pq, 
  spc7_pcx_atm_pq, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out);
wire [129:0] pcx_fpio_data_px2_0;
wire pcx_sctag1_data_rdy_px1_0;
wire pcx_sctag1_atm_px1_0;
wire pcx_sctag3_data_rdy_px1_0;
wire pcx_sctag3_atm_px1_0;
wire pcx_sctag5_data_rdy_px1_0;
wire pcx_sctag5_atm_px1_0;
wire pcx_sctag7_data_rdy_px1_0;
wire pcx_sctag7_atm_px1_0;
wire [8:0] pcx_spc0_grant_a;
wire [8:0] pcx_spc0_grant_a_0;
wire [8:0] pcx_spc1_grant_a;
wire [8:0] pcx_spc1_grant_a_0;
wire [8:0] pcx_spc2_grant_a;
wire [8:0] pcx_spc2_grant_a_0;
wire [8:0] pcx_spc3_grant_a;
wire [8:0] pcx_spc3_grant_a_0;
wire [8:0] pcx_spc4_grant_a;
wire [8:0] pcx_spc4_grant_a_0;
wire [8:0] pcx_spc5_grant_a;
wire [8:0] pcx_spc5_grant_a_0;
wire [8:0] pcx_spc6_grant_a;
wire [8:0] pcx_spc6_grant_a_0;
wire [8:0] pcx_spc7_grant_a;
wire [8:0] pcx_spc7_grant_a_0;
wire io_pcx_stall_pq_buf;
wire fpio_atm1_unused;
wire fpio_atm2_unused;
wire rdy8_1_unused;
wire io_pcx_stall_pq_d1;
wire [8:0] grant8_unused;
wire tcu_scan_en_bfg_8_unused;
wire tcu_pce_ov_bfg_8_unused;
wire ccx_aclk_bfg_8_unused;
wire ccx_bclk_bfg_8_unused;
wire pcx_fpio_data_rdy_a;
wire bfg8_scanin;
wire bfg8_scanout;
wire tcu_scan_en_bfd_lt;
wire tcu_pce_ov_bfd_lt;
wire ccx_aclk_bfd_lt;
wire ccx_bclk_bfd_lt;
wire sctag0_pcx_stall_pq_buf;
wire sctag0_pcx_stall_pq_d1;
wire tcu_scan_en_bfg_0_unused;
wire tcu_pce_ov_bfg_0_unused;
wire ccx_aclk_bfg_0_unused;
wire ccx_bclk_bfg_0_unused;
wire pcx_sctag0_atm_a;
wire pcx_sctag1_atm_a;
wire pcx_sctag0_data_rdy_a;
wire pcx_sctag1_data_rdy_a;
wire bfg0_scanin;
wire bfg0_scanout;
wire sctag1_pcx_stall_pq_buf;
wire atm10_unused;
wire atm11_unused;
wire rdy10_unused;
wire rdy11_unused;
wire sctag1_pcx_stall_pq_d1;
wire tcu_scan_en_bfg_1_unused;
wire tcu_pce_ov_bfg_1_unused;
wire ccx_aclk_bfg_1_unused;
wire ccx_bclk_bfg_1_unused;
wire bfg1_scanin;
wire bfg1_scanout;
wire tcu_scan_en_bfd_t;
wire tcu_pce_ov_bfd_t;
wire ccx_aclk_bfd_t;
wire ccx_bclk_bfd_t;
wire sctag2_pcx_stall_pq_buf;
wire sctag2_pcx_stall_pq_d1;
wire tcu_scan_en_bfg_2_unused;
wire tcu_pce_ov_bfg_2_unused;
wire ccx_aclk_bfg_2_unused;
wire ccx_bclk_bfg_2_unused;
wire pcx_sctag2_atm_a;
wire pcx_sctag3_atm_a;
wire pcx_sctag2_data_rdy_a;
wire pcx_sctag3_data_rdy_a;
wire bfg2_scanin;
wire bfg2_scanout;
wire tcu_scan_en_bfd_lb;
wire tcu_pce_ov_bfd_lb;
wire ccx_aclk_bfd_lb;
wire ccx_bclk_bfd_lb;
wire sctag3_pcx_stall_pq_buf;
wire atm30_unused;
wire atm31_unused;
wire rdy30_unused;
wire rdy31_unused;
wire sctag3_pcx_stall_pq_d1;
wire tcu_scan_en_bfg_3_unused;
wire tcu_pce_ov_bfg_3_unused;
wire ccx_aclk_bfg_3_unused;
wire ccx_bclk_bfg_3_unused;
wire bfg3_scanin;
wire bfg3_scanout;
wire tcu_scan_en_bfd_b;
wire tcu_pce_ov_bfd_b;
wire ccx_aclk_bfd_b;
wire ccx_bclk_bfd_b;
wire sctag4_pcx_stall_pq_buf;
wire sctag4_pcx_stall_pq_d1;
wire tcu_scan_en_bfg_4_unused;
wire tcu_pce_ov_bfg_4_unused;
wire ccx_aclk_bfg_4_unused;
wire ccx_bclk_bfg_4_unused;
wire pcx_sctag4_atm_a;
wire pcx_sctag5_atm_a;
wire pcx_sctag4_data_rdy_a;
wire pcx_sctag5_data_rdy_a;
wire bfg4_scanin;
wire bfg4_scanout;
wire tcu_scan_en_bfd_rt;
wire tcu_pce_ov_bfd_rt;
wire ccx_aclk_bfd_rt;
wire ccx_bclk_bfd_rt;
wire sctag5_pcx_stall_pq_buf;
wire atm50_unused;
wire atm51_unused;
wire rdy50_unused;
wire rdy51_unused;
wire sctag5_pcx_stall_pq_d1;
wire tcu_scan_en_bfg_5_unused;
wire tcu_pce_ov_bfg_5_unused;
wire ccx_aclk_bfg_5_unused;
wire ccx_bclk_bfg_5_unused;
wire bfg5_scanin;
wire bfg5_scanout;
wire sctag6_pcx_stall_pq_buf;
wire sctag6_pcx_stall_pq_d1;
wire tcu_scan_en_bfg_6_unused;
wire tcu_pce_ov_bfg_6_unused;
wire ccx_aclk_bfg_6_unused;
wire ccx_bclk_bfg_6_unused;
wire pcx_sctag6_atm_a;
wire pcx_sctag7_atm_a;
wire pcx_sctag6_data_rdy_a;
wire pcx_sctag7_data_rdy_a;
wire bfg6_scanin;
wire bfg6_scanout;
wire tcu_scan_en_bfd_rb;
wire tcu_pce_ov_bfd_rb;
wire ccx_aclk_bfd_rb;
wire ccx_bclk_bfd_rb;
wire sctag7_pcx_stall_pq_buf;
wire atm70_unused;
wire atm71_unused;
wire rdy70_unused;
wire rdy71_unused;
wire sctag7_pcx_stall_pq_d1;
wire tcu_scan_en_bfg_7_unused;
wire tcu_pce_ov_bfg_7_unused;
wire ccx_aclk_bfg_7_unused;
wire ccx_bclk_bfg_7_unused;
wire bfg7_scanin;
wire bfg7_scanout;
wire [8:0] spc0_pcx_req_pq_l_0;
wire [8:0] spc0_pcx_atm_pq_l_0;
wire [8:0] spc0_pcx_req_pq_r_0;
wire [8:0] spc0_pcx_atm_pq_r_0;
wire [8:0] spc1_pcx_req_pq_l_0;
wire [8:0] spc1_pcx_atm_pq_l_0;
wire [8:0] spc1_pcx_req_pq_r_0;
wire [8:0] spc1_pcx_atm_pq_r_0;
wire [8:0] spc2_pcx_req_pq_l_0;
wire [8:0] spc2_pcx_atm_pq_l_0;
wire [8:0] spc2_pcx_req_pq_r_0;
wire [8:0] spc2_pcx_atm_pq_r_0;
wire [8:0] spc3_pcx_req_pq_l_0;
wire [8:0] spc3_pcx_atm_pq_l_0;
wire [8:0] spc3_pcx_req_pq_r_0;
wire [8:0] spc3_pcx_atm_pq_r_0;
wire [8:0] spc4_pcx_req_pq_l_0;
wire [8:0] spc4_pcx_atm_pq_l_0;
wire [8:0] spc4_pcx_req_pq_r_0;
wire [8:0] spc4_pcx_atm_pq_r_0;
wire [8:0] spc5_pcx_req_pq_l_0;
wire [8:0] spc5_pcx_atm_pq_l_0;
wire [8:0] spc5_pcx_req_pq_r_0;
wire [8:0] spc5_pcx_atm_pq_r_0;
wire [8:0] spc6_pcx_req_pq_l_0;
wire [8:0] spc6_pcx_atm_pq_l_0;
wire [8:0] spc6_pcx_req_pq_r_0;
wire [8:0] spc6_pcx_atm_pq_r_0;
wire [8:0] spc7_pcx_req_pq_l_0;
wire [8:0] spc7_pcx_atm_pq_l_0;
wire [8:0] spc7_pcx_req_pq_r_0;
wire [8:0] spc7_pcx_atm_pq_r_0;
wire [129:0] spc0_pcx_data_a;
wire [129:0] spc1_pcx_data_a;
wire [129:0] spc2_pcx_data_a;
wire [129:0] spc3_pcx_data_a;
wire [129:0] spc4_pcx_data_a;
wire [129:0] spc5_pcx_data_a;
wire [129:0] spc6_pcx_data_a;
wire [129:0] spc7_pcx_data_a;
wire ccx_aclk_dpa_t;
wire ccx_bclk_dpa_t;
wire tcu_pce_ov_dpa_t;
wire tcu_scan_en_dpa_t;
wire ccx_aclk_dpa_b;
wire ccx_bclk_dpa_b;
wire tcu_pce_ov_dpa_b;
wire tcu_scan_en_dpa_b;
wire [129:0] pcx_fpio_data_x_l;
wire [129:0] pcx_scache0_data_x_l;
wire [129:0] pcx_scache1_data_x_l;
wire [129:0] pcx_scache2_data_x_l;
wire [129:0] pcx_scache3_data_x_l;
wire [129:0] pcx_scache4_data_x_l;
wire [129:0] pcx_scache5_data_x_l;
wire [129:0] pcx_scache6_data_x_l;
wire [129:0] pcx_scache7_data_x_l;
wire [8:0] arb0_grant_l_a;
wire [8:0] arb0_q0_holdbar_l_a;
wire [8:0] arb0_qsel0_l_a;
wire [8:0] arb0_qsel1_l_a;
wire [8:0] arb0_shift_l_a;
wire [8:0] arb1_grant_l_a;
wire [8:0] arb1_q0_holdbar_l_a;
wire [8:0] arb1_qsel0_l_a;
wire [8:0] arb1_qsel1_l_a;
wire [8:0] arb1_shift_l_a;
wire [8:0] arb2_grant_l_a;
wire [8:0] arb2_q0_holdbar_l_a;
wire [8:0] arb2_qsel0_l_a;
wire [8:0] arb2_qsel1_l_a;
wire [8:0] arb2_shift_l_a;
wire [8:0] arb3_grant_l_a;
wire [8:0] arb3_q0_holdbar_l_a;
wire [8:0] arb3_qsel0_l_a;
wire [8:0] arb3_qsel1_l_a;
wire [8:0] arb3_shift_l_a;
wire [8:0] arb4_grant_l_a;
wire [8:0] arb4_q0_holdbar_l_a;
wire [8:0] arb4_qsel0_l_a;
wire [8:0] arb4_qsel1_l_a;
wire [8:0] arb4_shift_l_a;
wire [8:0] arb5_grant_l_a;
wire [8:0] arb5_q0_holdbar_l_a;
wire [8:0] arb5_qsel0_l_a;
wire [8:0] arb5_qsel1_l_a;
wire [8:0] arb5_shift_l_a;
wire [8:0] arb6_grant_l_a;
wire [8:0] arb6_q0_holdbar_l_a;
wire [8:0] arb6_qsel0_l_a;
wire [8:0] arb6_qsel1_l_a;
wire [8:0] arb6_shift_l_a;
wire [8:0] arb7_grant_l_a;
wire [8:0] arb7_q0_holdbar_l_a;
wire [8:0] arb7_qsel0_l_a;
wire [8:0] arb7_qsel1_l_a;
wire [8:0] arb7_shift_l_a;
wire [8:0] arb8_grant_l_a;
wire [8:0] arb8_q0_holdbar_l_a;
wire [8:0] arb8_qsel0_l_a;
wire [8:0] arb8_qsel1_l_a;
wire [8:0] arb8_shift_l_a;
wire [8:0] arb0_grant_r_a;
wire [8:0] arb0_q0_holdbar_r_a;
wire [8:0] arb0_qsel0_r_a;
wire [8:0] arb0_qsel1_r_a;
wire [8:0] arb0_shift_r_a;
wire [8:0] arb1_grant_r_a;
wire [8:0] arb1_q0_holdbar_r_a;
wire [8:0] arb1_qsel0_r_a;
wire [8:0] arb1_qsel1_r_a;
wire [8:0] arb1_shift_r_a;
wire [8:0] arb2_grant_r_a;
wire [8:0] arb2_q0_holdbar_r_a;
wire [8:0] arb2_qsel0_r_a;
wire [8:0] arb2_qsel1_r_a;
wire [8:0] arb2_shift_r_a;
wire [8:0] arb3_grant_r_a;
wire [8:0] arb3_q0_holdbar_r_a;
wire [8:0] arb3_qsel0_r_a;
wire [8:0] arb3_qsel1_r_a;
wire [8:0] arb3_shift_r_a;
wire [8:0] arb4_grant_r_a;
wire [8:0] arb4_q0_holdbar_r_a;
wire [8:0] arb4_qsel0_r_a;
wire [8:0] arb4_qsel1_r_a;
wire [8:0] arb4_shift_r_a;
wire [8:0] arb5_grant_r_a;
wire [8:0] arb5_q0_holdbar_r_a;
wire [8:0] arb5_qsel0_r_a;
wire [8:0] arb5_qsel1_r_a;
wire [8:0] arb5_shift_r_a;
wire [8:0] arb6_grant_r_a;
wire [8:0] arb6_q0_holdbar_r_a;
wire [8:0] arb6_qsel0_r_a;
wire [8:0] arb6_qsel1_r_a;
wire [8:0] arb6_shift_r_a;
wire [8:0] arb7_grant_r_a;
wire [8:0] arb7_q0_holdbar_r_a;
wire [8:0] arb7_qsel0_r_a;
wire [8:0] arb7_qsel1_r_a;
wire [8:0] arb7_shift_r_a;
wire [8:0] arb8_grant_r_a;
wire [8:0] arb8_q0_holdbar_r_a;
wire [8:0] arb8_qsel0_r_a;
wire [8:0] arb8_qsel1_r_a;
wire [8:0] arb8_shift_r_a;
wire pcx_dpa_scanin;
wire pcx_dpa_scanout;
wire bfd_io_scanin;
wire bfd_io_scanout;
wire tcu_scan_en_bfd_0;
wire tcu_pce_ov_bfd_0;
wire ccx_aclk_bfd_0;
wire ccx_bclk_bfd_0;
wire [129:0] pcx_sctag0_data_px2_prebuf;
wire bfd0_scanin;
wire bfd0_scanout;
wire tcu_scan_en_bfd_1;
wire tcu_pce_ov_bfd_1;
wire ccx_aclk_bfd_1;
wire ccx_bclk_bfd_1;
wire [129:0] pcx_sctag1_data_px2_prebuf;
wire bfd1_scanin;
wire bfd1_scanout;
wire [129:0] pcx_sctag2_data_px2_prebuf;
wire bfd2_scanin;
wire bfd2_scanout;
wire tcu_scan_en_bfd_3;
wire tcu_pce_ov_bfd_3;
wire ccx_aclk_bfd_3;
wire ccx_bclk_bfd_3;
wire [129:0] pcx_sctag3_data_px2_prebuf;
wire bfd3_scanin;
wire bfd3_scanout;
wire [129:0] pcx_sctag4_data_px2_prebuf;
wire bfd4_scanin;
wire bfd4_scanout;
wire tcu_scan_en_bfd_5;
wire tcu_pce_ov_bfd_5;
wire ccx_aclk_bfd_5;
wire ccx_bclk_bfd_5;
wire [129:0] pcx_sctag5_data_px2_prebuf;
wire bfd5_scanin;
wire bfd5_scanout;
wire [129:0] pcx_sctag6_data_px2_prebuf;
wire bfd6_scanin;
wire bfd6_scanout;
wire tcu_scan_en_bfd_7;
wire tcu_pce_ov_bfd_7;
wire ccx_aclk_bfd_7;
wire ccx_bclk_bfd_7;
wire [129:0] pcx_sctag7_data_px2_prebuf;
wire bfd7_scanin;
wire bfd7_scanout;
wire [8:0] arb_grant_l_unused;
wire [8:0] arb_q0_hold_l_unused;
wire [8:0] arb_qsel0_l_unused;
wire [8:0] arb_qsel1_l_unused;
wire [8:0] arb_shift_l_unused;
wire [8:0] arb_grant_r_unused;
wire [8:0] arb_q0_hold_r_unused;
wire [8:0] arb_qsel0_r_unused;
wire [8:0] arb_qsel1_r_unused;
wire [8:0] arb_shift_r_unused;
wire sctag0_pcx_stall_lq_d1;
wire [8:0] spc0_pcx_req_lq;
wire [8:0] spc0_pcx_atm_lq;
wire sctag1_pcx_stall_lq_d1;
wire [8:0] spc1_pcx_req_lq;
wire [8:0] spc1_pcx_atm_lq;
wire io_pcx_stall_lq_d1;
wire sctag2_pcx_stall_lq_d1;
wire [8:0] spc2_pcx_req_lq;
wire [8:0] spc2_pcx_atm_lq;
wire sctag3_pcx_stall_lq_d1;
wire [8:0] spc3_pcx_req_lq;
wire [8:0] spc3_pcx_atm_lq;
wire sctag4_pcx_stall_lq_d1;
wire [8:0] spc4_pcx_req_lq;
wire [8:0] spc4_pcx_atm_lq;
wire sctag5_pcx_stall_lq_d1;
wire [8:0] spc5_pcx_req_lq;
wire [8:0] spc5_pcx_atm_lq;
wire sctag6_pcx_stall_lq_d1;
wire [8:0] spc6_pcx_req_lq;
wire [8:0] spc6_pcx_atm_lq;
wire sctag7_pcx_stall_lq_d1;
wire [8:0] spc7_pcx_req_lq;
wire [8:0] spc7_pcx_atm_lq;
wire ccx_aclk_arb_lt;
wire ccx_bclk_arb_lt;
wire tcu_pce_ov_arb_lt;
wire tcu_scan_en_arb_lt;
wire ccx_aclk_arb_lb;
wire ccx_bclk_arb_lb;
wire tcu_pce_ov_arb_lb;
wire tcu_scan_en_arb_lb;
wire ccx_aclk_arb_rt;
wire ccx_bclk_arb_rt;
wire tcu_pce_ov_arb_rt;
wire tcu_scan_en_arb_rt;
wire ccx_aclk_arb_rb;
wire ccx_bclk_arb_rb;
wire tcu_pce_ov_arb_rb;
wire tcu_scan_en_arb_rb;
wire [8:0] pcx_spc4_grant_a_unused;
wire [8:0] pcx_spc5_grant_a_unused;
wire [8:0] pcx_spc6_grant_a_unused;
wire [8:0] pcx_spc7_grant_a_unused;
wire arb0_src8_grant_l_unused;
wire pcx_arbl0_scanin;
wire pcx_arbl0_scanout;
wire arb1_src8_grant_l_unused;
wire pcx_arbl1_scanin;
wire pcx_arbl1_scanout;
wire arb2_src8_grant_l_unused;
wire pcx_arbl2_scanin;
wire pcx_arbl2_scanout;
wire arb3_src8_grant_l_unused;
wire pcx_arbl3_scanin;
wire pcx_arbl3_scanout;
wire arb4_src8_grant_l_unused;
wire pcx_sctag4_atm_a_unused;
wire pcx_sctag4_data_rdy_a_unused;
wire pcx_arbl4_scanin;
wire pcx_arbl4_scanout;
wire arb5_src8_grant_l_unused;
wire pcx_sctag5_atm_a_unused;
wire pcx_sctag5_data_rdy_a_unused;
wire pcx_arbl5_scanin;
wire pcx_arbl5_scanout;
wire arb6_src8_grant_l_unused;
wire pcx_sctag6_atm_a_unused;
wire pcx_sctag6_data_rdy_a_unused;
wire pcx_arbl6_scanin;
wire pcx_arbl6_scanout;
wire arb7_src8_grant_l_unused;
wire pcx_sctag7_atm_a_unused;
wire pcx_sctag7_data_rdy_a_unused;
wire pcx_arbl7_scanin;
wire pcx_arbl7_scanout;
wire arb8_src8_grant_l_unused;
wire arb8_dest_atom_l_unused;
wire pcx_arbl8_scanin;
wire pcx_arbl8_scanout;
wire sctag0_pcx_stall_rq_d1;
wire [8:0] spc0_pcx_req_rq;
wire [8:0] spc0_pcx_atm_rq;
wire sctag1_pcx_stall_rq_d1;
wire [8:0] spc1_pcx_req_rq;
wire [8:0] spc1_pcx_atm_rq;
wire io_pcx_stall_rq_d1;
wire sctag2_pcx_stall_rq_d1;
wire [8:0] spc2_pcx_req_rq;
wire [8:0] spc2_pcx_atm_rq;
wire sctag3_pcx_stall_rq_d1;
wire [8:0] spc3_pcx_req_rq;
wire [8:0] spc3_pcx_atm_rq;
wire sctag4_pcx_stall_rq_d1;
wire [8:0] spc4_pcx_req_rq;
wire [8:0] spc4_pcx_atm_rq;
wire sctag5_pcx_stall_rq_d1;
wire [8:0] spc5_pcx_req_rq;
wire [8:0] spc5_pcx_atm_rq;
wire sctag6_pcx_stall_rq_d1;
wire [8:0] spc6_pcx_req_rq;
wire [8:0] spc6_pcx_atm_rq;
wire sctag7_pcx_stall_rq_d1;
wire [8:0] spc7_pcx_req_rq;
wire [8:0] spc7_pcx_atm_rq;
wire [8:0] pcx_spc0_grant_a_unused;
wire [8:0] pcx_spc1_grant_a_unused;
wire [8:0] pcx_spc2_grant_a_unused;
wire [8:0] pcx_spc3_grant_a_unused;
wire arb0_src8_grant_r_unused;
wire pcx_sctag0_atm_a_unused;
wire pcx_sctag0_data_rdy_a_unused;
wire pcx_arbr0_scanin;
wire pcx_arbr0_scanout;
wire arb1_src8_grant_r_unused;
wire pcx_sctag1_atm_a_unused;
wire pcx_sctag1_data_rdy_a_unused;
wire pcx_arbr1_scanin;
wire pcx_arbr1_scanout;
wire arb2_src8_grant_r_unused;
wire pcx_sctag2_atm_a_unused;
wire pcx_sctag2_data_rdy_a_unused;
wire pcx_arbr2_scanin;
wire pcx_arbr2_scanout;
wire arb3_src8_grant_r_unused;
wire pcx_sctag3_atm_a_unused;
wire pcx_sctag3_data_rdy_a_unused;
wire pcx_arbr3_scanin;
wire pcx_arbr3_scanout;
wire arb4_src8_grant_r_unused;
wire pcx_arbr4_scanin;
wire pcx_arbr4_scanout;
wire arb5_src8_grant_r_unused;
wire pcx_arbr5_scanin;
wire pcx_arbr5_scanout;
wire arb6_src8_grant_r_unused;
wire pcx_arbr6_scanin;
wire pcx_arbr6_scanout;
wire arb7_src8_grant_r_unused;
wire pcx_arbr7_scanin;
wire pcx_arbr7_scanout;
wire arb8_src8_grant_r_unused;
wire arb8_dest_atom_r_unused;
wire pcx_fpio_data_rdy_a_unused;
wire pcx_arbr8_scanin;
wire pcx_arbr8_scanout;


output [129:0]          pcx_fpio_data_px2;      // From fpio_buf of pcx_bfd_dp.v
output                  pcx_fpio_data_rdy_px1;  // From arb8 of ccx_arb.v
output                  pcx_sctag0_atm_px1;     // From arb0 of ccx_arb.v
output [129:0]          pcx_sctag0_data_px2;    // From sc_buf0 of pcx_bfd_dp.v
output                  pcx_sctag0_data_rdy_px1;// From arb0 of ccx_arb.v
output                  pcx_sctag1_atm_px1;     // From arb1 of ccx_arb.v
output [129:0]          pcx_sctag1_data_px2;    // From sc_buf1 of pcx_bfd_dp.v
output                  pcx_sctag1_data_rdy_px1;// From arb1 of ccx_arb.v
output                  pcx_sctag2_atm_px1;     // From arb2 of ccx_arb.v
output [129:0]          pcx_sctag2_data_px2;    // From sc_buf2 of pcx_bfd_dp.v
output                  pcx_sctag2_data_rdy_px1;// From arb2 of ccx_arb.v
output                  pcx_sctag3_atm_px1;     // From arb3 of ccx_arb.v
output [129:0]          pcx_sctag3_data_px2;    // From sc_buf3 of pcx_bfd_dp.v
output                  pcx_sctag3_data_rdy_px1;// From arb3 of ccx_arb.v
output                  pcx_sctag4_atm_px1;     // From arb4 of ccx_arb.v
output [129:0]          pcx_sctag4_data_px2;    // From sc_buf4 of pcx_bfd_dp.v
output                  pcx_sctag4_data_rdy_px1;// From arb4 of ccx_arb.v
output                  pcx_sctag5_atm_px1;     // From arb5 of ccx_arb.v
output [129:0]          pcx_sctag5_data_px2;    // From sc_buf5 of pcx_bfd_dp.v
output                  pcx_sctag5_data_rdy_px1;// From arb5 of ccx_arb.v
output                  pcx_sctag6_atm_px1;     // From arb6 of ccx_arb.v
output [129:0]          pcx_sctag6_data_px2;    // From sc_buf6 of pcx_bfd_dp.v
output                  pcx_sctag6_data_rdy_px1;// From arb6 of ccx_arb.v
output                  pcx_sctag7_atm_px1;     // From arb7 of ccx_arb.v
output [129:0]          pcx_sctag7_data_px2;    // From sc_buf7 of pcx_bfd_dp.v
output                  pcx_sctag7_data_rdy_px1;// From arb7 of ccx_arb.v
output [8:0]            pcx_spc0_grant_px;      // From spc_buf0 of pcx_bfg_dp.v
output [8:0]            pcx_spc1_grant_px;      // From spc_buf1 of pcx_bfg_dp.v
output [8:0]            pcx_spc2_grant_px;      // From spc_buf2 of pcx_bfg_dp.v
output [8:0]            pcx_spc3_grant_px;      // From spc_buf3 of pcx_bfg_dp.v
output [8:0]            pcx_spc4_grant_px;      // From spc_buf4 of pcx_bfg_dp.v
output [8:0]            pcx_spc5_grant_px;      // From spc_buf5 of pcx_bfg_dp.v
output [8:0]            pcx_spc6_grant_px;      // From spc_buf6 of pcx_bfg_dp.v
output [8:0]            pcx_spc7_grant_px;      // From spc_buf7 of pcx_bfg_dp.v
// End of automatics


input                   io_pcx_stall_pq;        // To arb8 of ccx_arb.v
input                   sctag0_pcx_stall_pq;    // To arb0 of ccx_arb.v
input                   sctag1_pcx_stall_pq;    // To arb1 of ccx_arb.v
input                   sctag2_pcx_stall_pq;    // To arb2 of ccx_arb.v
input                   sctag3_pcx_stall_pq;    // To arb3 of ccx_arb.v
input                   sctag4_pcx_stall_pq;    // To arb4 of ccx_arb.v
input                   sctag5_pcx_stall_pq;    // To arb5 of ccx_arb.v
input                   sctag6_pcx_stall_pq;    // To arb6 of ccx_arb.v
input                   sctag7_pcx_stall_pq;    // To arb7 of ccx_arb.v
input [129:0]           spc0_pcx_data_pa;       // To pcx_dpa of pcx_dpa.v
input [8:0]             spc0_pcx_req_pq;        // To arb0 of ccx_arb.v, ...
input [8:0]             spc0_pcx_atm_pq;       // To arb0 of ccx_arb.v, ...
input [129:0]           spc1_pcx_data_pa;       // To pcx_dpa of pcx_dpa.v
input [8:0]             spc1_pcx_req_pq;        // To arb0 of ccx_arb.v, ...
input [8:0]             spc1_pcx_atm_pq;       // To arb0 of ccx_arb.v, ...
input [129:0]           spc2_pcx_data_pa;       // To pcx_dpa of pcx_dpa.v
input [8:0]             spc2_pcx_req_pq;        // To arb0 of ccx_arb.v, ...
input [8:0]             spc2_pcx_atm_pq;       // To arb0 of ccx_arb.v, ...
input [129:0]           spc3_pcx_data_pa;       // To pcx_dpa of pcx_dpa.v
input [8:0]             spc3_pcx_req_pq;        // To arb0 of ccx_arb.v, ...
input [8:0]             spc3_pcx_atm_pq;       // To arb0 of ccx_arb.v, ...
input [129:0]           spc4_pcx_data_pa;       // To pcx_dpa of pcx_dpa.v
input [8:0]             spc4_pcx_req_pq;        // To arb0 of ccx_arb.v, ...
input [8:0]             spc4_pcx_atm_pq;       // To arb0 of ccx_arb.v, ...
input [129:0]           spc5_pcx_data_pa;       // To pcx_dpa of pcx_dpa.v
input [8:0]             spc5_pcx_req_pq;        // To arb0 of ccx_arb.v, ...
input [8:0]             spc5_pcx_atm_pq;       // To arb0 of ccx_arb.v, ...
input [129:0]           spc6_pcx_data_pa;       // To pcx_dpa of pcx_dpa.v
input [8:0]             spc6_pcx_req_pq;        // To arb0 of ccx_arb.v, ...
input [8:0]             spc6_pcx_atm_pq;       // To arb0 of ccx_arb.v, ...
input [129:0]           spc7_pcx_data_pa;       // To pcx_dpa of pcx_dpa.v
input [8:0]             spc7_pcx_req_pq;        // To arb0 of ccx_arb.v, ...
input [8:0]             spc7_pcx_atm_pq;       // To arb0 of ccx_arb.v, ...
// End of automatics

//globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

// buffer io data
pcx_buff_macro__dbuff_32x__rep_1__stack_150c__width_130 i_bufd_io     (
	.din	(pcx_fpio_data_px2_0[129:0]),
	.dout	(pcx_fpio_data_px2[129:0])
);


// buffer data rdy and atm signals above the arbiters
// signals going to spc1, spc3, spc5, and spc7 will have an
// extra level off buffers

pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_bufd_sct1_1     (
	.din	({pcx_sctag1_data_rdy_px1_0, pcx_sctag1_atm_px1_0}),
	.dout	({pcx_sctag1_data_rdy_px1, pcx_sctag1_atm_px1})
);

pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_bufd_sct3_1     (
	.din	({pcx_sctag3_data_rdy_px1_0, pcx_sctag3_atm_px1_0}),
	.dout	({pcx_sctag3_data_rdy_px1, pcx_sctag3_atm_px1})
);

pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_bufd_sct5_1     (
	.din	({pcx_sctag5_data_rdy_px1_0, pcx_sctag5_atm_px1_0}),
	.dout	({pcx_sctag5_data_rdy_px1, pcx_sctag5_atm_px1})
);

pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_bufd_sct7_1     (
	.din	({pcx_sctag7_data_rdy_px1_0, pcx_sctag7_atm_px1_0}),
	.dout	({pcx_sctag7_data_rdy_px1, pcx_sctag7_atm_px1})
);


// buffer output grant signals
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc0     (
	.din	(pcx_spc0_grant_a[8:0]),
	.dout	(pcx_spc0_grant_a_0[8:0])
);
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc1     (
	.din	(pcx_spc1_grant_a[8:0]),
	.dout	(pcx_spc1_grant_a_0[8:0])
);
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc2     (
	.din	(pcx_spc2_grant_a[8:0]),
	.dout	(pcx_spc2_grant_a_0[8:0])
);
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc3     (
	.din	(pcx_spc3_grant_a[8:0]),
	.dout	(pcx_spc3_grant_a_0[8:0])
);
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc4     (
	.din	(pcx_spc4_grant_a[8:0]),
	.dout	(pcx_spc4_grant_a_0[8:0])
);
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc5     (
	.din	(pcx_spc5_grant_a[8:0]),
	.dout	(pcx_spc5_grant_a_0[8:0])
);
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc6     (
	.din	(pcx_spc6_grant_a[8:0]),
	.dout	(pcx_spc6_grant_a_0[8:0])
);
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc7     (
	.din	(pcx_spc7_grant_a[8:0]),
	.dout	(pcx_spc7_grant_a_0[8:0])
);


/*
 pcx_bfg_dp AUTO_TEMPLATE(
 .pcx_spc_grant_px (pcx_spc@_grant_px_0[8:0]),
 .pcx_spc_grant_pa (pcx_spc@_grant_a[8:0]),
);
   */

//To meet timing, stall_pq is being flopped.
pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_io_stall     (
.din (io_pcx_stall_pq),
.dout(io_pcx_stall_pq_buf)                                                                 
);
                                                                 
pcx_bfg_dp bfg8 (
                 .pcx_spc_grant_px      ({fpio_atm1_unused, fpio_atm2_unused, pcx_fpio_data_rdy_px1,rdy8_1_unused ,io_pcx_stall_pq_d1,grant8_unused[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_8_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_8_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_8_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_8_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({2'b0,pcx_fpio_data_rdy_a,1'b0,io_pcx_stall_pq_buf,9'b0}), // Templated
                 .scan_in(bfg8_scanin),
                 .scan_out(bfg8_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_lt),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_lt),
                 .ccx_aclk                (ccx_aclk_bfd_lt),
                 .ccx_bclk                (ccx_bclk_bfd_lt)
                 );

pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct0_stall     (
.din (sctag0_pcx_stall_pq),
.dout(sctag0_pcx_stall_pq_buf)                                                                 
);
pcx_bfg_dp bfg0 (/*AUTOINST*/
                 // Outputs
                 .pcx_spc_grant_px      ({pcx_sctag0_atm_px1, pcx_sctag1_atm_px1_0,pcx_sctag0_data_rdy_px1, pcx_sctag1_data_rdy_px1_0,sctag0_pcx_stall_pq_d1,pcx_spc0_grant_px[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_0_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_0_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_0_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_0_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({pcx_sctag0_atm_a,pcx_sctag1_atm_a,pcx_sctag0_data_rdy_a,pcx_sctag1_data_rdy_a,sctag0_pcx_stall_pq_buf,pcx_spc0_grant_a_0[8:0]}), // Templated
                 .scan_in(bfg0_scanin),
                 .scan_out(bfg0_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_lt),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_lt),
                 .ccx_aclk                (ccx_aclk_bfd_lt),
                 .ccx_bclk                (ccx_bclk_bfd_lt)
                 );

pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct1_stall     (
.din (sctag1_pcx_stall_pq),
.dout(sctag1_pcx_stall_pq_buf)                                                                 
);
pcx_bfg_dp bfg1 (/*AUTOINST*/
                 // Outputs
                 .pcx_spc_grant_px      ({atm10_unused, atm11_unused, rdy10_unused, rdy11_unused,sctag1_pcx_stall_pq_d1,pcx_spc1_grant_px[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_1_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_1_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_1_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_1_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({4'b0,sctag1_pcx_stall_pq_buf,pcx_spc1_grant_a_0[8:0]}), // Templated
                 .scan_in(bfg1_scanin),
                 .scan_out(bfg1_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_t),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_t),
                 .ccx_aclk                (ccx_aclk_bfd_t),
                 .ccx_bclk                (ccx_bclk_bfd_t)
                 );

pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct2_stall     (
.din (sctag2_pcx_stall_pq),
.dout(sctag2_pcx_stall_pq_buf)                                                                 
);
pcx_bfg_dp bfg2 (/*AUTOINST*/
                 // Outputs
                 .pcx_spc_grant_px      ({pcx_sctag2_atm_px1, pcx_sctag3_atm_px1_0,pcx_sctag2_data_rdy_px1, pcx_sctag3_data_rdy_px1_0,sctag2_pcx_stall_pq_d1,pcx_spc2_grant_px[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_2_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_2_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_2_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_2_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({pcx_sctag2_atm_a,pcx_sctag3_atm_a,pcx_sctag2_data_rdy_a,pcx_sctag3_data_rdy_a,sctag2_pcx_stall_pq_buf,pcx_spc2_grant_a_0[8:0]}), // Templated
                 .scan_in(bfg2_scanin),
                 .scan_out(bfg2_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_lb),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_lb),
                 .ccx_aclk                (ccx_aclk_bfd_lb),
                 .ccx_bclk                (ccx_bclk_bfd_lb)
                 );

pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct3_stall     (
.din (sctag3_pcx_stall_pq),
.dout(sctag3_pcx_stall_pq_buf)                                                                 
);
pcx_bfg_dp bfg3 (/*AUTOINST*/
                 // Outputs
                 .pcx_spc_grant_px      ({atm30_unused, atm31_unused, rdy30_unused, rdy31_unused,sctag3_pcx_stall_pq_d1,pcx_spc3_grant_px[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_3_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_3_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_3_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_3_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({4'b0,sctag3_pcx_stall_pq_buf,pcx_spc3_grant_a_0[8:0]}), // Templated
                 .scan_in(bfg3_scanin),
                 .scan_out(bfg3_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_b),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_b),
                 .ccx_aclk                (ccx_aclk_bfd_b),
                 .ccx_bclk                (ccx_bclk_bfd_b)
                 );


pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct4_stall     (
.din (sctag4_pcx_stall_pq),
.dout(sctag4_pcx_stall_pq_buf)                                                                 
);
pcx_bfg_dp bfg4 (/*AUTOINST*/
                 // Outputs
                 .pcx_spc_grant_px      ({pcx_sctag4_atm_px1, pcx_sctag5_atm_px1_0,pcx_sctag4_data_rdy_px1, pcx_sctag5_data_rdy_px1_0,sctag4_pcx_stall_pq_d1,pcx_spc4_grant_px[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_4_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_4_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_4_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_4_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({pcx_sctag4_atm_a,pcx_sctag5_atm_a,pcx_sctag4_data_rdy_a,pcx_sctag5_data_rdy_a,sctag4_pcx_stall_pq_buf,pcx_spc4_grant_a_0[8:0]}), // Templated
                 .scan_in(bfg4_scanin),
                 .scan_out(bfg4_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_rt),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_rt),
                 .ccx_aclk                (ccx_aclk_bfd_rt),
                 .ccx_bclk                (ccx_bclk_bfd_rt)
                 );


pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct5_stall     (
.din (sctag5_pcx_stall_pq),
.dout(sctag5_pcx_stall_pq_buf)                                                                 
);
pcx_bfg_dp bfg5 (/*AUTOINST*/
                 // Outputs
                 .pcx_spc_grant_px      ({atm50_unused, atm51_unused, rdy50_unused, rdy51_unused,sctag5_pcx_stall_pq_d1,pcx_spc5_grant_px[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_5_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_5_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_5_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_5_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({4'b0,sctag5_pcx_stall_pq_buf,pcx_spc5_grant_a_0[8:0]}), // Templated
                 .scan_in(bfg5_scanin),
                 .scan_out(bfg5_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_t),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_t),
                 .ccx_aclk                (ccx_aclk_bfd_t),
                 .ccx_bclk                (ccx_bclk_bfd_t)
                 );


pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct6_stall     (
.din (sctag6_pcx_stall_pq),
.dout(sctag6_pcx_stall_pq_buf)                                                                 
);
pcx_bfg_dp bfg6 (/*AUTOINST*/
                 // Outputs
                 .pcx_spc_grant_px      ({pcx_sctag6_atm_px1,pcx_sctag7_atm_px1_0,pcx_sctag6_data_rdy_px1,pcx_sctag7_data_rdy_px1_0,sctag6_pcx_stall_pq_d1,pcx_spc6_grant_px[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_6_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_6_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_6_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_6_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({pcx_sctag6_atm_a,pcx_sctag7_atm_a,pcx_sctag6_data_rdy_a,pcx_sctag7_data_rdy_a,sctag6_pcx_stall_pq_buf,pcx_spc6_grant_a_0[8:0]}), // Templated
                 .scan_in(bfg6_scanin),
                 .scan_out(bfg6_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_rb),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_rb),
                 .ccx_aclk                (ccx_aclk_bfd_rb),
                 .ccx_bclk                (ccx_bclk_bfd_rb)
                 );


pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct7_stall     (
.din (sctag7_pcx_stall_pq),
.dout (sctag7_pcx_stall_pq_buf)                                                                 
);
pcx_bfg_dp bfg7 (/*AUTOINST*/
                 // Outputs
                 .pcx_spc_grant_px      ({atm70_unused, atm71_unused, rdy70_unused, rdy71_unused,sctag7_pcx_stall_pq_d1,pcx_spc7_grant_px[8:0]}), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfg_7_unused),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfg_7_unused),
                 .ccx_aclk_out          (ccx_aclk_bfg_7_unused),
                 .ccx_bclk_out          (ccx_bclk_bfg_7_unused),
                 // Inputs
                 .pcx_spc_grant_pa      ({4'b0,sctag7_pcx_stall_pq_buf,pcx_spc7_grant_a_0[8:0]}), // Templated
                 .scan_in(bfg7_scanin),
                 .scan_out(bfg7_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_b),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_b),
                 .ccx_aclk                (ccx_aclk_bfd_b),
                 .ccx_bclk                (ccx_bclk_bfd_b)
                 );


// buffer req and atm signals at the pins
pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc0_l     (
	.din	({spc0_pcx_req_pq[8:0],spc0_pcx_atm_pq[8:0]}),
	.dout	({spc0_pcx_req_pq_l_0[8:0],spc0_pcx_atm_pq_l_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc0_r     (
	.din	({spc0_pcx_req_pq[8:0],spc0_pcx_atm_pq[8:0]}),
	.dout	({spc0_pcx_req_pq_r_0[8:0],spc0_pcx_atm_pq_r_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc1_l     (
	.din	({spc1_pcx_req_pq[8:0],spc1_pcx_atm_pq[8:0]}),
	.dout	({spc1_pcx_req_pq_l_0[8:0],spc1_pcx_atm_pq_l_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc1_r     (
	.din	({spc1_pcx_req_pq[8:0],spc1_pcx_atm_pq[8:0]}),
	.dout	({spc1_pcx_req_pq_r_0[8:0],spc1_pcx_atm_pq_r_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc2_l     (
	.din	({spc2_pcx_req_pq[8:0],spc2_pcx_atm_pq[8:0]}),
	.dout	({spc2_pcx_req_pq_l_0[8:0],spc2_pcx_atm_pq_l_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc2_r     (
	.din	({spc2_pcx_req_pq[8:0],spc2_pcx_atm_pq[8:0]}),
	.dout	({spc2_pcx_req_pq_r_0[8:0],spc2_pcx_atm_pq_r_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc3_l     (
	.din	({spc3_pcx_req_pq[8:0],spc3_pcx_atm_pq[8:0]}),
	.dout	({spc3_pcx_req_pq_l_0[8:0],spc3_pcx_atm_pq_l_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc3_r     (
	.din	({spc3_pcx_req_pq[8:0],spc3_pcx_atm_pq[8:0]}),
	.dout	({spc3_pcx_req_pq_r_0[8:0],spc3_pcx_atm_pq_r_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc4_l     (
	.din	({spc4_pcx_req_pq[8:0],spc4_pcx_atm_pq[8:0]}),
	.dout	({spc4_pcx_req_pq_l_0[8:0],spc4_pcx_atm_pq_l_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc4_r     (
	.din	({spc4_pcx_req_pq[8:0],spc4_pcx_atm_pq[8:0]}),
	.dout	({spc4_pcx_req_pq_r_0[8:0],spc4_pcx_atm_pq_r_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc5_l     (
	.din	({spc5_pcx_req_pq[8:0],spc5_pcx_atm_pq[8:0]}),
	.dout	({spc5_pcx_req_pq_l_0[8:0],spc5_pcx_atm_pq_l_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc5_r     (
	.din	({spc5_pcx_req_pq[8:0],spc5_pcx_atm_pq[8:0]}),
	.dout	({spc5_pcx_req_pq_r_0[8:0],spc5_pcx_atm_pq_r_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc6_l     (
	.din	({spc6_pcx_req_pq[8:0],spc6_pcx_atm_pq[8:0]}),
	.dout	({spc6_pcx_req_pq_l_0[8:0],spc6_pcx_atm_pq_l_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc6_r     (
	.din	({spc6_pcx_req_pq[8:0],spc6_pcx_atm_pq[8:0]}),
	.dout	({spc6_pcx_req_pq_r_0[8:0],spc6_pcx_atm_pq_r_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc7_l     (
	.din	({spc7_pcx_req_pq[8:0],spc7_pcx_atm_pq[8:0]}),
	.dout	({spc7_pcx_req_pq_l_0[8:0],spc7_pcx_atm_pq_l_0[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc7_r     (
	.din	({spc7_pcx_req_pq[8:0],spc7_pcx_atm_pq[8:0]}),
	.dout	({spc7_pcx_req_pq_r_0[8:0],spc7_pcx_atm_pq_r_0[8:0]})
);


// buffer all the inputs at the input column
pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc0_1     (
	.din	(spc0_pcx_data_pa[129:0]),
	.dout	(spc0_pcx_data_a[129:0])
);

pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc1_1     (
	.din	(spc1_pcx_data_pa[129:0]),
	.dout	(spc1_pcx_data_a[129:0])
);

pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc2_1     (
	.din	(spc2_pcx_data_pa[129:0]),
	.dout	(spc2_pcx_data_a[129:0])
);

pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc3_1     (
	.din	(spc3_pcx_data_pa[129:0]),
	.dout	(spc3_pcx_data_a[129:0])
);

pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc4_1     (
	.din	(spc4_pcx_data_pa[129:0]),
	.dout	(spc4_pcx_data_a[129:0])
);

pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc5_1     (
	.din	(spc5_pcx_data_pa[129:0]),
	.dout	(spc5_pcx_data_a[129:0])
);

pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc6_1     (
	.din	(spc6_pcx_data_pa[129:0]),
	.dout	(spc6_pcx_data_a[129:0])
);

pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc7_1     (
	.din	(spc7_pcx_data_pa[129:0]),
	.dout	(spc7_pcx_data_a[129:0])
);


//buffer the high fanout signals going to dpa top
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_dpa_t     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_dpa_t,ccx_bclk_dpa_t,tcu_pce_ov_dpa_t,tcu_scan_en_dpa_t})
);
//buffer the high fanout signals going to bfd_dp/bfg_dp top
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_bfd_t     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_bfd_t,ccx_bclk_bfd_t,tcu_pce_ov_bfd_t,tcu_scan_en_bfd_t})
);

//buffer the high fanout signals going to dpa bottom
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_dpa_b     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_dpa_b,ccx_bclk_dpa_b,tcu_pce_ov_dpa_b,tcu_scan_en_dpa_b})
);
//buffer the high fanout signals going to bfd_dp/bfg_dp bottom
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_bfd_b     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_bfd_b,ccx_bclk_bfd_b,tcu_pce_ov_bfd_b,tcu_scan_en_bfd_b})
);


// Beginning of automatic inputs (from unused autoinst inputs)

 /*
  pcx_dpa AUTO_TEMPLATE(
  .pcx_io_data_x_(pcx_fpio_data_x_l[129:0]),
  .pcx_scache0_data_x_(pcx_scache0_data_x_l[129:0]),
  .pcx_scache1_data_x_(pcx_scache1_data_x_l[129:0]),
  .pcx_scache2_data_x_(pcx_scache2_data_x_l[129:0]),
  .pcx_scache3_data_x_(pcx_scache3_data_x_l[129:0]),
  .pcx_scache4_data_x_(pcx_scache4_data_x_l[129:0]),
  .pcx_scache5_data_x_(pcx_scache5_data_x_l[129:0]),
  .pcx_scache6_data_x_(pcx_scache6_data_x_l[129:0]),
  .pcx_scache7_data_x_(pcx_scache7_data_x_l[129:0]));
  */

pcx_dpa pcx_dpa (
/*AUTOINST*/
                 // Outputs
                 .pcx_io_data_x_        (pcx_fpio_data_x_l[129:0]), // Templated
                 .pcx_scache0_data_x_   (pcx_scache0_data_x_l[129:0]), // Templated
                 .pcx_scache1_data_x_   (pcx_scache1_data_x_l[129:0]), // Templated
                 .pcx_scache2_data_x_   (pcx_scache2_data_x_l[129:0]), // Templated
                 .pcx_scache3_data_x_   (pcx_scache3_data_x_l[129:0]), // Templated
                 .pcx_scache4_data_x_   (pcx_scache4_data_x_l[129:0]), // Templated
                 .pcx_scache5_data_x_   (pcx_scache5_data_x_l[129:0]), // Templated
                 .pcx_scache6_data_x_   (pcx_scache6_data_x_l[129:0]), // Templated
                 .pcx_scache7_data_x_   (pcx_scache7_data_x_l[129:0]), // Templated
                 // Inputs
                 .arb0_grant_l_a          (arb0_grant_l_a[7:0]),
                 .arb0_q0_holdbar_l_a     (arb0_q0_holdbar_l_a[7:0]),
                 .arb0_qsel0_l_a          (arb0_qsel0_l_a[7:0]),
                 .arb0_qsel1_l_a          (arb0_qsel1_l_a[7:0]),
                 .arb0_shift_l_a          (arb0_shift_l_a[7:0]),
                 .arb1_grant_l_a          (arb1_grant_l_a[7:0]),
                 .arb1_q0_holdbar_l_a     (arb1_q0_holdbar_l_a[7:0]),
                 .arb1_qsel0_l_a          (arb1_qsel0_l_a[7:0]),
                 .arb1_qsel1_l_a          (arb1_qsel1_l_a[7:0]),
                 .arb1_shift_l_a          (arb1_shift_l_a[7:0]),
                 .arb2_grant_l_a          (arb2_grant_l_a[7:0]),
                 .arb2_q0_holdbar_l_a     (arb2_q0_holdbar_l_a[7:0]),
                 .arb2_qsel0_l_a          (arb2_qsel0_l_a[7:0]),
                 .arb2_qsel1_l_a          (arb2_qsel1_l_a[7:0]),
                 .arb2_shift_l_a          (arb2_shift_l_a[7:0]),
                 .arb3_grant_l_a          (arb3_grant_l_a[7:0]),
                 .arb3_q0_holdbar_l_a     (arb3_q0_holdbar_l_a[7:0]),
                 .arb3_qsel0_l_a          (arb3_qsel0_l_a[7:0]),
                 .arb3_qsel1_l_a          (arb3_qsel1_l_a[7:0]),
                 .arb3_shift_l_a          (arb3_shift_l_a[7:0]),
                 .arb4_grant_l_a          (arb4_grant_l_a[7:0]),
                 .arb4_q0_holdbar_l_a     (arb4_q0_holdbar_l_a[7:0]),
                 .arb4_qsel0_l_a          (arb4_qsel0_l_a[7:0]),
                 .arb4_qsel1_l_a          (arb4_qsel1_l_a[7:0]),
                 .arb4_shift_l_a          (arb4_shift_l_a[7:0]),
                 .arb5_grant_l_a          (arb5_grant_l_a[7:0]),
                 .arb5_q0_holdbar_l_a     (arb5_q0_holdbar_l_a[7:0]),
                 .arb5_qsel0_l_a          (arb5_qsel0_l_a[7:0]),
                 .arb5_qsel1_l_a          (arb5_qsel1_l_a[7:0]),
                 .arb5_shift_l_a          (arb5_shift_l_a[7:0]),
                 .arb6_grant_l_a          (arb6_grant_l_a[7:0]),
                 .arb6_q0_holdbar_l_a     (arb6_q0_holdbar_l_a[7:0]),
                 .arb6_qsel0_l_a          (arb6_qsel0_l_a[7:0]),
                 .arb6_qsel1_l_a          (arb6_qsel1_l_a[7:0]),
                 .arb6_shift_l_a          (arb6_shift_l_a[7:0]),
                 .arb7_grant_l_a          (arb7_grant_l_a[7:0]),
                 .arb7_q0_holdbar_l_a     (arb7_q0_holdbar_l_a[7:0]),
                 .arb7_qsel0_l_a          (arb7_qsel0_l_a[7:0]),
                 .arb7_qsel1_l_a          (arb7_qsel1_l_a[7:0]),
                 .arb7_shift_l_a          (arb7_shift_l_a[7:0]),
                 .arb8_grant_l_a          (arb8_grant_l_a[7:0]),
                 .arb8_q0_holdbar_l_a     (arb8_q0_holdbar_l_a[7:0]),
                 .arb8_qsel0_l_a          (arb8_qsel0_l_a[7:0]),
                 .arb8_qsel1_l_a          (arb8_qsel1_l_a[7:0]),
                 .arb8_shift_l_a          (arb8_shift_l_a[7:0]),
                 .arb0_grant_r_a          (arb0_grant_r_a[7:0]),
                 .arb0_q0_holdbar_r_a     (arb0_q0_holdbar_r_a[7:0]),
                 .arb0_qsel0_r_a          (arb0_qsel0_r_a[7:0]),
                 .arb0_qsel1_r_a          (arb0_qsel1_r_a[7:0]),
                 .arb0_shift_r_a          (arb0_shift_r_a[7:0]),
                 .arb1_grant_r_a          (arb1_grant_r_a[7:0]),
                 .arb1_q0_holdbar_r_a     (arb1_q0_holdbar_r_a[7:0]),
                 .arb1_qsel0_r_a          (arb1_qsel0_r_a[7:0]),
                 .arb1_qsel1_r_a          (arb1_qsel1_r_a[7:0]),
                 .arb1_shift_r_a          (arb1_shift_r_a[7:0]),
                 .arb2_grant_r_a          (arb2_grant_r_a[7:0]),
                 .arb2_q0_holdbar_r_a     (arb2_q0_holdbar_r_a[7:0]),
                 .arb2_qsel0_r_a          (arb2_qsel0_r_a[7:0]),
                 .arb2_qsel1_r_a          (arb2_qsel1_r_a[7:0]),
                 .arb2_shift_r_a          (arb2_shift_r_a[7:0]),
                 .arb3_grant_r_a          (arb3_grant_r_a[7:0]),
                 .arb3_q0_holdbar_r_a     (arb3_q0_holdbar_r_a[7:0]),
                 .arb3_qsel0_r_a          (arb3_qsel0_r_a[7:0]),
                 .arb3_qsel1_r_a          (arb3_qsel1_r_a[7:0]),
                 .arb3_shift_r_a          (arb3_shift_r_a[7:0]),
                 .arb4_grant_r_a          (arb4_grant_r_a[7:0]),
                 .arb4_q0_holdbar_r_a     (arb4_q0_holdbar_r_a[7:0]),
                 .arb4_qsel0_r_a          (arb4_qsel0_r_a[7:0]),
                 .arb4_qsel1_r_a          (arb4_qsel1_r_a[7:0]),
                 .arb4_shift_r_a          (arb4_shift_r_a[7:0]),
                 .arb5_grant_r_a          (arb5_grant_r_a[7:0]),
                 .arb5_q0_holdbar_r_a     (arb5_q0_holdbar_r_a[7:0]),
                 .arb5_qsel0_r_a          (arb5_qsel0_r_a[7:0]),
                 .arb5_qsel1_r_a          (arb5_qsel1_r_a[7:0]),
                 .arb5_shift_r_a          (arb5_shift_r_a[7:0]),
                 .arb6_grant_r_a          (arb6_grant_r_a[7:0]),
                 .arb6_q0_holdbar_r_a     (arb6_q0_holdbar_r_a[7:0]),
                 .arb6_qsel0_r_a          (arb6_qsel0_r_a[7:0]),
                 .arb6_qsel1_r_a          (arb6_qsel1_r_a[7:0]),
                 .arb6_shift_r_a          (arb6_shift_r_a[7:0]),
                 .arb7_grant_r_a          (arb7_grant_r_a[7:0]),
                 .arb7_q0_holdbar_r_a     (arb7_q0_holdbar_r_a[7:0]),
                 .arb7_qsel0_r_a          (arb7_qsel0_r_a[7:0]),
                 .arb7_qsel1_r_a          (arb7_qsel1_r_a[7:0]),
                 .arb7_shift_r_a          (arb7_shift_r_a[7:0]),
                 .arb8_grant_r_a          (arb8_grant_r_a[7:0]),
                 .arb8_q0_holdbar_r_a     (arb8_q0_holdbar_r_a[7:0]),
                 .arb8_qsel0_r_a          (arb8_qsel0_r_a[7:0]),
                 .arb8_qsel1_r_a          (arb8_qsel1_r_a[7:0]),
                 .arb8_shift_r_a          (arb8_shift_r_a[7:0]),
                 .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]), // Templated
                 .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]), // Templated
                 .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]), // Templated
                 .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]), // Templated
                 .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]), // Templated
                 .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]), // Templated
                 .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]), // Templated
                 .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]), // Templated
                 .scan_in                 (pcx_dpa_scanin),
                 .scan_out                (pcx_dpa_scanout),
                 .l2clk                   (l2clk),
                 .tcu_scan_en_t             (tcu_scan_en_dpa_t),
                 .tcu_pce_ov_t              (tcu_pce_ov_dpa_t),
                 .ccx_aclk_t                (ccx_aclk_dpa_t),
                 .ccx_bclk_t                (ccx_bclk_dpa_t),
                 .tcu_scan_en_b             (tcu_scan_en_dpa_b),
                 .tcu_pce_ov_b              (tcu_pce_ov_dpa_b),
                 .ccx_aclk_b                (ccx_aclk_dpa_b),
                 .ccx_bclk_b                (ccx_bclk_dpa_b)
                 );


// invert and flop the output signals
// These are placed right next to the CCX core datapath

pcx_bfd_dp bfd_io (
/*AUTOINST*/
                   // Outputs
                   .pcx_sctag_data_px2  (pcx_fpio_data_px2_0[129:0]), // Templated
                   .tcu_scan_en_out       (tcu_scan_en_bfd_lt),
                   .tcu_pce_ov_out        (tcu_pce_ov_bfd_lt),
                   .ccx_aclk_out          (ccx_aclk_bfd_lt),
                   .ccx_bclk_out          (ccx_bclk_bfd_lt),
                   // Inputs
                   .pcx_scache_data_px_ (pcx_fpio_data_x_l[129:0]), // Templated
                   .scan_in(bfd_io_scanin),
                   .scan_out(bfd_io_scanout),
                   .l2clk               (l2clk),
                   .tcu_scan_en       (tcu_scan_en_bfd_0),
                   .tcu_pce_ov       (tcu_pce_ov_bfd_0),
                   .ccx_aclk         (ccx_aclk_bfd_0),
                   .ccx_bclk          (ccx_bclk_bfd_0)
                   );


pcx_bfd_dp bfd0 (
                 // Outputs
                 .pcx_sctag_data_px2    (pcx_sctag0_data_px2_prebuf[129:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_0),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_0),
                 .ccx_aclk_out          (ccx_aclk_bfd_0),
                 .ccx_bclk_out          (ccx_bclk_bfd_0),
                 // Inputs
                 .pcx_scache_data_px_   (pcx_scache0_data_x_l[129:0]), // Templated
                 .scan_in(bfd0_scanin),
                 .scan_out(bfd0_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en       (tcu_scan_en_bfd_1),
                 .tcu_pce_ov        (tcu_pce_ov_bfd_1),
                 .ccx_aclk          (ccx_aclk_bfd_1),
                 .ccx_bclk          (ccx_bclk_bfd_1)
                 );


// Output buffer at the pins
pcx_ob1_dp ob_0 (
                  .pcx_sctag_data_px2        (pcx_sctag0_data_px2[129:0]),
                  .pcx_sctag_data_px2_prebuf (pcx_sctag0_data_px2_prebuf[129:0])
                  );


pcx_bfd_dp bfd1 (
                 // Outputs
                 .pcx_sctag_data_px2    (pcx_sctag1_data_px2_prebuf[129:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_1),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_1),
                 .ccx_aclk_out          (ccx_aclk_bfd_1),
                 .ccx_bclk_out          (ccx_bclk_bfd_1),
                 // Inputs
                 .pcx_scache_data_px_   (pcx_scache1_data_x_l[129:0]), // Templated
                 .scan_in(bfd1_scanin),
                 .scan_out(bfd1_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_t),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_t),
                 .ccx_aclk                (ccx_aclk_bfd_t),
                 .ccx_bclk                (ccx_bclk_bfd_t)
                 );

// Output buffer at the pins
pcx_ob1_dp ob_1 (
                  .pcx_sctag_data_px2        (pcx_sctag1_data_px2[129:0]),
                  .pcx_sctag_data_px2_prebuf (pcx_sctag1_data_px2_prebuf[129:0])
                  );

pcx_bfd_dp bfd2 (
                 // Outputs
                 .pcx_sctag_data_px2    (pcx_sctag2_data_px2_prebuf[129:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_lb),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_lb),
                 .ccx_aclk_out          (ccx_aclk_bfd_lb),
                 .ccx_bclk_out          (ccx_bclk_bfd_lb),
                 // Inputs
                 .pcx_scache_data_px_   (pcx_scache2_data_x_l[129:0]), // Templated
                 .scan_in(bfd2_scanin),
                 .scan_out(bfd2_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_3),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_3),
                 .ccx_aclk                (ccx_aclk_bfd_3),
                 .ccx_bclk                (ccx_bclk_bfd_3)
                 );

// Output buffer at the pins
pcx_ob1_dp ob_2 (
                  .pcx_sctag_data_px2        (pcx_sctag2_data_px2[129:0]),
                  .pcx_sctag_data_px2_prebuf (pcx_sctag2_data_px2_prebuf[129:0])
                  );

pcx_bfd_dp bfd3 (
                 // Outputs
                 .pcx_sctag_data_px2    (pcx_sctag3_data_px2_prebuf[129:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_3),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_3),
                 .ccx_aclk_out          (ccx_aclk_bfd_3),
                 .ccx_bclk_out          (ccx_bclk_bfd_3),
                 // Inputs
                 .pcx_scache_data_px_   (pcx_scache3_data_x_l[129:0]), // Templated
                 .scan_in(bfd3_scanin),
                 .scan_out(bfd3_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_b),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_b),
                 .ccx_aclk                (ccx_aclk_bfd_b),
                 .ccx_bclk                (ccx_bclk_bfd_b)
                 );

// Output buffer at the pins
pcx_ob1_dp ob_3 (
                  .pcx_sctag_data_px2        (pcx_sctag3_data_px2[129:0]),
                  .pcx_sctag_data_px2_prebuf (pcx_sctag3_data_px2_prebuf[129:0])
                  );

pcx_bfd_dp bfd4 (
                 // Outputs
                 .pcx_sctag_data_px2    (pcx_sctag4_data_px2_prebuf[129:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_rt),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_rt),
                 .ccx_aclk_out          (ccx_aclk_bfd_rt),
                 .ccx_bclk_out          (ccx_bclk_bfd_rt),
                 // Inputs
                 .pcx_scache_data_px_   (pcx_scache4_data_x_l[129:0]), // Templated
                 .scan_in(bfd4_scanin),
                 .scan_out(bfd4_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_5),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_5),
                 .ccx_aclk                (ccx_aclk_bfd_5),
                 .ccx_bclk                (ccx_bclk_bfd_5)
                 );


// Output buffer at the pins
pcx_ob1_dp ob_4 (
                  .pcx_sctag_data_px2        (pcx_sctag4_data_px2[129:0]),
                  .pcx_sctag_data_px2_prebuf (pcx_sctag4_data_px2_prebuf[129:0])
                  );

pcx_bfd_dp bfd5 (
                 // Outputs
                 .pcx_sctag_data_px2    (pcx_sctag5_data_px2_prebuf[129:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_5),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_5),
                 .ccx_aclk_out          (ccx_aclk_bfd_5),
                 .ccx_bclk_out          (ccx_bclk_bfd_5),
                 // Inputs
                 .pcx_scache_data_px_   (pcx_scache5_data_x_l[129:0]), // Templated
                 .scan_in(bfd5_scanin),
                 .scan_out(bfd5_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_t),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_t),
                 .ccx_aclk                (ccx_aclk_bfd_t),
                 .ccx_bclk                (ccx_bclk_bfd_t)
                 );


// Output buffer at the pins
pcx_ob1_dp ob_5 (
                  .pcx_sctag_data_px2        (pcx_sctag5_data_px2[129:0]),
                  .pcx_sctag_data_px2_prebuf (pcx_sctag5_data_px2_prebuf[129:0])
                  );

pcx_bfd_dp bfd6 (
                 // Outputs
                 .pcx_sctag_data_px2    (pcx_sctag6_data_px2_prebuf[129:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_rb),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_rb),
                 .ccx_aclk_out          (ccx_aclk_bfd_rb),
                 .ccx_bclk_out          (ccx_bclk_bfd_rb),
                 // Inputs
                 .pcx_scache_data_px_   (pcx_scache6_data_x_l[129:0]), // Templated
                 .scan_in(bfd6_scanin),
                 .scan_out(bfd6_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_7),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_7),
                 .ccx_aclk                (ccx_aclk_bfd_7),
                 .ccx_bclk                (ccx_bclk_bfd_7)
                 );

// Output buffer at the pins
pcx_ob1_dp ob_6 (
                  .pcx_sctag_data_px2        (pcx_sctag6_data_px2[129:0]),
                  .pcx_sctag_data_px2_prebuf (pcx_sctag6_data_px2_prebuf[129:0])
                  );

pcx_bfd_dp bfd7 (
                 // Outputs
                 .pcx_sctag_data_px2    (pcx_sctag7_data_px2_prebuf[129:0]), // Templated
                 .tcu_scan_en_out       (tcu_scan_en_bfd_7),
                 .tcu_pce_ov_out        (tcu_pce_ov_bfd_7),
                 .ccx_aclk_out          (ccx_aclk_bfd_7),
                 .ccx_bclk_out          (ccx_bclk_bfd_7),
                 // Inputs
                 .pcx_scache_data_px_   (pcx_scache7_data_x_l[129:0]), // Templated
                 .scan_in(bfd7_scanin),
                 .scan_out(bfd7_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_bfd_b),
                 .tcu_pce_ov              (tcu_pce_ov_bfd_b),
                 .ccx_aclk                (ccx_aclk_bfd_b),
                 .ccx_bclk                (ccx_bclk_bfd_b)
                 );

// Output buffer at the pins
pcx_ob1_dp ob_7 (
                  .pcx_sctag_data_px2        (pcx_sctag7_data_px2[129:0]),
                  .pcx_sctag_data_px2_prebuf (pcx_sctag7_data_px2_prebuf[129:0])
                  );


assign arb_grant_l_unused[8:0] = {arb8_grant_l_a[8],arb7_grant_l_a[8],arb6_grant_l_a[8],arb5_grant_l_a[8],
                                arb4_grant_l_a[8],arb3_grant_l_a[8],arb2_grant_l_a[8],arb1_grant_l_a[8],arb0_grant_l_a[8]};

assign arb_q0_hold_l_unused[8:0] = {arb8_q0_holdbar_l_a[8],arb7_q0_holdbar_l_a[8],arb6_q0_holdbar_l_a[8],arb5_q0_holdbar_l_a[8],
                                arb4_q0_holdbar_l_a[8],arb3_q0_holdbar_l_a[8],arb2_q0_holdbar_l_a[8],arb1_q0_holdbar_l_a[8],arb0_q0_holdbar_l_a[8]};

assign arb_qsel0_l_unused[8:0] = {arb8_qsel0_l_a[8],arb7_qsel0_l_a[8],arb6_qsel0_l_a[8],arb5_qsel0_l_a[8],
                                arb4_qsel0_l_a[8],arb3_qsel0_l_a[8],arb2_qsel0_l_a[8],arb1_qsel0_l_a[8],arb0_qsel0_l_a[8]};

assign arb_qsel1_l_unused[8:0] = {arb8_qsel1_l_a[8],arb7_qsel1_l_a[8],arb6_qsel1_l_a[8],arb5_qsel1_l_a[8],
                                arb4_qsel1_l_a[8],arb3_qsel1_l_a[8],arb2_qsel1_l_a[8],arb1_qsel1_l_a[8],arb0_qsel1_l_a[8]};

assign arb_shift_l_unused[8:0] = {arb8_shift_l_a[8],arb7_shift_l_a[8],arb6_shift_l_a[8],arb5_shift_l_a[8],
                                arb4_shift_l_a[8],arb3_shift_l_a[8],arb2_shift_l_a[8],arb1_shift_l_a[8],arb0_shift_l_a[8]};

assign arb_grant_r_unused[8:0] = {arb8_grant_r_a[8],arb7_grant_r_a[8],arb6_grant_r_a[8],arb5_grant_r_a[8],
                                arb4_grant_r_a[8],arb3_grant_r_a[8],arb2_grant_r_a[8],arb1_grant_r_a[8],arb0_grant_r_a[8]};

assign arb_q0_hold_r_unused[8:0] = {arb8_q0_holdbar_r_a[8],arb7_q0_holdbar_r_a[8],arb6_q0_holdbar_r_a[8],arb5_q0_holdbar_r_a[8],
                                arb4_q0_holdbar_r_a[8],arb3_q0_holdbar_r_a[8],arb2_q0_holdbar_r_a[8],arb1_q0_holdbar_r_a[8],arb0_q0_holdbar_r_a[8]};

assign arb_qsel0_r_unused[8:0] = {arb8_qsel0_r_a[8],arb7_qsel0_r_a[8],arb6_qsel0_r_a[8],arb5_qsel0_r_a[8],
                                arb4_qsel0_r_a[8],arb3_qsel0_r_a[8],arb2_qsel0_r_a[8],arb1_qsel0_r_a[8],arb0_qsel0_r_a[8]};

assign arb_qsel1_r_unused[8:0] = {arb8_qsel1_r_a[8],arb7_qsel1_r_a[8],arb6_qsel1_r_a[8],arb5_qsel1_r_a[8],
                                arb4_qsel1_r_a[8],arb3_qsel1_r_a[8],arb2_qsel1_r_a[8],arb1_qsel1_r_a[8],arb0_qsel1_r_a[8]};

assign arb_shift_r_unused[8:0] = {arb8_shift_r_a[8],arb7_shift_r_a[8],arb6_shift_r_a[8],arb5_shift_r_a[8],
                                arb4_shift_r_a[8],arb3_shift_r_a[8],arb2_shift_r_a[8],arb1_shift_r_a[8],arb0_shift_r_a[8]};


// buffer req signals feeding left arbiters
pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc0     (
	.din	({sctag0_pcx_stall_pq_d1, spc0_pcx_req_pq_l_0[8:0],spc0_pcx_atm_pq_l_0[8:0]}),
	.dout	({sctag0_pcx_stall_lq_d1,   spc0_pcx_req_lq[8:0],spc0_pcx_atm_lq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc1     (
	.din	({sctag1_pcx_stall_pq_d1, spc1_pcx_req_pq_l_0[8:0],spc1_pcx_atm_pq_l_0[8:0]}),
	.dout	({sctag1_pcx_stall_lq_d1,   spc1_pcx_req_lq[8:0],spc1_pcx_atm_lq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_20 i_bufq_l_spc2     (
	.din	({io_pcx_stall_pq_d1, sctag2_pcx_stall_pq_d1, spc2_pcx_req_pq_l_0[8:0],spc2_pcx_atm_pq_l_0[8:0]}),
	.dout	({io_pcx_stall_lq_d1,   sctag2_pcx_stall_lq_d1,   spc2_pcx_req_lq[8:0],spc2_pcx_atm_lq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc3     (
	.din	({sctag3_pcx_stall_pq_d1, spc3_pcx_req_pq_l_0[8:0],spc3_pcx_atm_pq_l_0[8:0]}),
	.dout	({sctag3_pcx_stall_lq_d1,   spc3_pcx_req_lq[8:0],spc3_pcx_atm_lq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc4     (
	.din	({sctag4_pcx_stall_pq_d1, spc4_pcx_req_pq_l_0[8:0],spc4_pcx_atm_pq_l_0[8:0]}),
	.dout	({sctag4_pcx_stall_lq_d1,   spc4_pcx_req_lq[8:0],spc4_pcx_atm_lq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc5     (
	.din	({sctag5_pcx_stall_pq_d1, spc5_pcx_req_pq_l_0[8:0],spc5_pcx_atm_pq_l_0[8:0]}),
	.dout	({sctag5_pcx_stall_lq_d1,   spc5_pcx_req_lq[8:0],spc5_pcx_atm_lq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc6     (
	.din	({sctag6_pcx_stall_pq_d1, spc6_pcx_req_pq_l_0[8:0],spc6_pcx_atm_pq_l_0[8:0]}),
	.dout	({sctag6_pcx_stall_lq_d1,   spc6_pcx_req_lq[8:0],spc6_pcx_atm_lq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc7     (
	.din	({sctag7_pcx_stall_pq_d1, spc7_pcx_req_pq_l_0[8:0],spc7_pcx_atm_pq_l_0[8:0]}),
	.dout	({sctag7_pcx_stall_lq_d1,   spc7_pcx_req_lq[8:0],spc7_pcx_atm_lq[8:0]})
);

//buffer the high fanout signals going to arb top left
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_lt     (
	.din	({ccx_aclk_bfd_lt,ccx_bclk_bfd_lt, tcu_pce_ov_bfd_lt, tcu_scan_en_bfd_lt}),
	.dout	({ccx_aclk_arb_lt,ccx_bclk_arb_lt,tcu_pce_ov_arb_lt,tcu_scan_en_arb_lt})
);

//buffer the high fanout signals going to arb bot left
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_lb     (
	.din	({ccx_aclk_bfd_lb,ccx_bclk_bfd_lb, tcu_pce_ov_bfd_lb, tcu_scan_en_bfd_lb}),
	.dout	({ccx_aclk_arb_lb,ccx_bclk_arb_lb,tcu_pce_ov_arb_lb,tcu_scan_en_arb_lb})
);

//buffer the high fanout signals going to arb top right
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_rt     (
	.din	({ccx_aclk_bfd_rt,ccx_bclk_bfd_rt, tcu_pce_ov_bfd_rt, tcu_scan_en_bfd_rt}),
	.dout	({ccx_aclk_arb_rt,ccx_bclk_arb_rt,tcu_pce_ov_arb_rt,tcu_scan_en_arb_rt})
);

//buffer the high fanout signals going to arb bot right
pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_rb     (
	.din	({ccx_aclk_bfd_rb,ccx_bclk_bfd_rb, tcu_pce_ov_bfd_rb, tcu_scan_en_bfd_rb}),
	.dout	({ccx_aclk_arb_rb,ccx_bclk_arb_rb,tcu_pce_ov_arb_rb,tcu_scan_en_arb_rb})
);


/*
 ccx_arb  AUTO_TEMPLATE(
 // Outputs
 .arb_grant_a		(arb@_grant_l_a[8:0]),
 .arb_q0_holdbar_a		(arb@_q0_holdbar_l_a[8:0]),
 .arb_qsel0_a		(arb@_qsel0_l_a[8:0]),
 .arb_qsel1_a		(arb@_qsel1_l_a[8:0]),
 .arb_shift_a		(arb@_shift_l_a[8:0]),
 .arb_src0_grant_a		(pcx_spc0_grant_a[@]),
 .arb_src1_grant_a		(pcx_spc1_grant_a[@]),
 .arb_src2_grant_a		(pcx_spc2_grant_a[@]),
 .arb_src3_grant_a		(pcx_spc3_grant_a[@]),
 .arb_src4_grant_a		(pcx_spc4_grant_a[@]),
 .arb_src5_grant_a		(pcx_spc5_grant_a[@]),
 .arb_src6_grant_a		(pcx_spc6_grant_a[@]),
 .arb_src7_grant_a		(pcx_spc7_grant_a[@]),
 .arb_src8_grant_a		(arb@_src8_grant_l_unused),
 .ccx_dest_data_rdy_a	(pcx_sctag@_data_rdy_a),
 .ccx_dest_atom_a	(pcx_sctag@_atm_a),
 // Inputs
 .src0_arb_atom_q		(spc0_pcx_atm_lq[@]),
 .src0_arb_req_q		(spc0_pcx_req_lq[@]),
 .src1_arb_atom_q		(spc1_pcx_atm_lq[@]),
 .src1_arb_req_q		(spc1_pcx_req_lq[@]),
 .src2_arb_atom_q		(spc2_pcx_atm_lq[@]),
 .src2_arb_req_q		(spc2_pcx_req_lq[@]),
 .src3_arb_atom_q		(spc3_pcx_atm_lq[@]),
 .src3_arb_req_q		(spc3_pcx_req_lq[@]),
 .src4_arb_atom_q		(spc4_pcx_atm_lq[@]),
 .src4_arb_req_q		(spc4_pcx_req_lq[@]),
 .src5_arb_atom_q		(spc5_pcx_atm_lq[@]),
 .src5_arb_req_q		(spc5_pcx_req_lq[@]),
 .src6_arb_atom_q		(spc6_pcx_atm_lq[@]),
 .src6_arb_req_q		(spc6_pcx_req_lq[@]),
 .src7_arb_atom_q		(spc7_pcx_atm_lq[@]),
 .src7_arb_req_q		(spc7_pcx_req_lq[@]),
 .src8_arb_atom_q		(1'b0),
 .src8_arb_req_q		(1'b0),
 .stall_q_d1			(sctag@_pcx_stall_lq_d1),
);
 */

ccx_arb pcx_arbl0 (
                  // Outputs
                  .arb_grant_a          (arb0_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb0_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb0_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb0_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb0_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (pcx_spc0_grant_a[0]),   // Templated
                  .arb_src1_grant_a     (pcx_spc1_grant_a[0]),   // Templated
                  .arb_src2_grant_a     (pcx_spc2_grant_a[0]),   // Templated
                  .arb_src3_grant_a     (pcx_spc3_grant_a[0]),   // Templated
                  .arb_src4_grant_a     (pcx_spc4_grant_a_unused[0]),   // Templated
                  .arb_src5_grant_a     (pcx_spc5_grant_a_unused[0]),   // Templated
                  .arb_src6_grant_a     (pcx_spc6_grant_a_unused[0]),   // Templated
                  .arb_src7_grant_a     (pcx_spc7_grant_a_unused[0]),   // Templated
                  .arb_src8_grant_a     (arb0_src8_grant_l_unused), // Templated
                  .ccx_dest_atom_a      (pcx_sctag0_atm_a),    // Templated
                  .ccx_dest_data_rdy_a  (pcx_sctag0_data_rdy_a), // Templated
                  // Inputs
                  .src0_arb_atom_q      (spc0_pcx_atm_lq[0]),    // Templated
                  .src0_arb_req_q       (spc0_pcx_req_lq[0]),    // Templated
                  .src1_arb_atom_q      (spc1_pcx_atm_lq[0]),    // Templated
                  .src1_arb_req_q       (spc1_pcx_req_lq[0]),    // Templated
                  .src2_arb_atom_q      (spc2_pcx_atm_lq[0]),    // Templated
                  .src2_arb_req_q       (spc2_pcx_req_lq[0]),    // Templated
                  .src3_arb_atom_q      (spc3_pcx_atm_lq[0]),    // Templated
                  .src3_arb_req_q       (spc3_pcx_req_lq[0]),    // Templated
                  .src4_arb_atom_q      (spc4_pcx_atm_lq[0]),    // Templated
                  .src4_arb_req_q       (spc4_pcx_req_lq[0]),    // Templated
                  .src5_arb_atom_q      (spc5_pcx_atm_lq[0]),    // Templated
                  .src5_arb_req_q       (spc5_pcx_req_lq[0]),    // Templated
                  .src6_arb_atom_q      (spc6_pcx_atm_lq[0]),    // Templated
                  .src6_arb_req_q       (spc6_pcx_req_lq[0]),    // Templated
                  .src7_arb_atom_q      (spc7_pcx_atm_lq[0]),    // Templated
                  .src7_arb_req_q       (spc7_pcx_req_lq[0]),    // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (1'b0),                  // Templated
                  .stall_q_d1              (sctag0_pcx_stall_lq_d1),   // Templated
                  .scan_in(pcx_arbl0_scanin),
                  .scan_out(pcx_arbl0_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );

ccx_arb pcx_arbl1(
                 // Outputs
                 .arb_grant_a           (arb1_grant_l_a[8:0]),     // Templated
                 .arb_q0_holdbar_a      (arb1_q0_holdbar_l_a[8:0]), // Templated
                 .arb_qsel0_a           (arb1_qsel0_l_a[8:0]),     // Templated
                 .arb_qsel1_a           (arb1_qsel1_l_a[8:0]),     // Templated
                 .arb_shift_a           (arb1_shift_l_a[8:0]),     // Templated
                 .arb_src0_grant_a      (pcx_spc0_grant_a[1]),   // Templated
                 .arb_src1_grant_a      (pcx_spc1_grant_a[1]),   // Templated
                 .arb_src2_grant_a      (pcx_spc2_grant_a[1]),   // Templated
                 .arb_src3_grant_a      (pcx_spc3_grant_a[1]),   // Templated
                 .arb_src4_grant_a      (pcx_spc4_grant_a_unused[1]),   // Templated
                 .arb_src5_grant_a      (pcx_spc5_grant_a_unused[1]),   // Templated
                 .arb_src6_grant_a      (pcx_spc6_grant_a_unused[1]),   // Templated
                 .arb_src7_grant_a      (pcx_spc7_grant_a_unused[1]),   // Templated
                 .arb_src8_grant_a      (arb1_src8_grant_l_unused), // Templated
                 .ccx_dest_atom_a       (pcx_sctag1_atm_a),    // Templated
                 .ccx_dest_data_rdy_a   (pcx_sctag1_data_rdy_a), // Templated
                 // Inputs
                 .src0_arb_atom_q       (spc0_pcx_atm_lq[1]),    // Templated
                 .src0_arb_req_q        (spc0_pcx_req_lq[1]),    // Templated
                 .src1_arb_atom_q       (spc1_pcx_atm_lq[1]),    // Templated
                 .src1_arb_req_q        (spc1_pcx_req_lq[1]),    // Templated
                 .src2_arb_atom_q       (spc2_pcx_atm_lq[1]),    // Templated
                 .src2_arb_req_q        (spc2_pcx_req_lq[1]),    // Templated
                 .src3_arb_atom_q       (spc3_pcx_atm_lq[1]),    // Templated
                 .src3_arb_req_q        (spc3_pcx_req_lq[1]),    // Templated
                 .src4_arb_atom_q       (spc4_pcx_atm_lq[1]),    // Templated
                 .src4_arb_req_q        (spc4_pcx_req_lq[1]),    // Templated
                 .src5_arb_atom_q       (spc5_pcx_atm_lq[1]),    // Templated
                 .src5_arb_req_q        (spc5_pcx_req_lq[1]),    // Templated
                 .src6_arb_atom_q       (spc6_pcx_atm_lq[1]),    // Templated
                 .src6_arb_req_q        (spc6_pcx_req_lq[1]),    // Templated
                 .src7_arb_atom_q       (spc7_pcx_atm_lq[1]),    // Templated
                 .src7_arb_req_q        (spc7_pcx_req_lq[1]),    // Templated
                 .src8_arb_atom_q       (1'b0),                  // Templated
                 .src8_arb_req_q        (1'b0),                  // Templated
                 .stall_q_d1               (sctag1_pcx_stall_lq_d1),   // Templated
                 .scan_in(pcx_arbl1_scanin),
                 .scan_out(pcx_arbl1_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );

ccx_arb pcx_arbl2(
                 // Outputs
                 .arb_grant_a           (arb2_grant_l_a[8:0]),     // Templated
                 .arb_q0_holdbar_a      (arb2_q0_holdbar_l_a[8:0]), // Templated
                 .arb_qsel0_a           (arb2_qsel0_l_a[8:0]),     // Templated
                 .arb_qsel1_a           (arb2_qsel1_l_a[8:0]),     // Templated
                 .arb_shift_a           (arb2_shift_l_a[8:0]),     // Templated
                 .arb_src0_grant_a      (pcx_spc0_grant_a[2]),   // Templated
                 .arb_src1_grant_a      (pcx_spc1_grant_a[2]),   // Templated
                 .arb_src2_grant_a      (pcx_spc2_grant_a[2]),   // Templated
                 .arb_src3_grant_a      (pcx_spc3_grant_a[2]),   // Templated
                 .arb_src4_grant_a      (pcx_spc4_grant_a_unused[2]),   // Templated
                 .arb_src5_grant_a      (pcx_spc5_grant_a_unused[2]),   // Templated
                 .arb_src6_grant_a      (pcx_spc6_grant_a_unused[2]),   // Templated
                 .arb_src7_grant_a      (pcx_spc7_grant_a_unused[2]),   // Templated
                 .arb_src8_grant_a      (arb2_src8_grant_l_unused), // Templated
                 .ccx_dest_atom_a       (pcx_sctag2_atm_a),    // Templated
                 .ccx_dest_data_rdy_a   (pcx_sctag2_data_rdy_a), // Templated
                 // Inputs
                 .src0_arb_atom_q       (spc0_pcx_atm_lq[2]),    // Templated
                 .src0_arb_req_q        (spc0_pcx_req_lq[2]),    // Templated
                 .src1_arb_atom_q       (spc1_pcx_atm_lq[2]),    // Templated
                 .src1_arb_req_q        (spc1_pcx_req_lq[2]),    // Templated
                 .src2_arb_atom_q       (spc2_pcx_atm_lq[2]),    // Templated
                 .src2_arb_req_q        (spc2_pcx_req_lq[2]),    // Templated
                 .src3_arb_atom_q       (spc3_pcx_atm_lq[2]),    // Templated
                 .src3_arb_req_q        (spc3_pcx_req_lq[2]),    // Templated
                 .src4_arb_atom_q       (spc4_pcx_atm_lq[2]),    // Templated
                 .src4_arb_req_q        (spc4_pcx_req_lq[2]),    // Templated
                 .src5_arb_atom_q       (spc5_pcx_atm_lq[2]),    // Templated
                 .src5_arb_req_q        (spc5_pcx_req_lq[2]),    // Templated
                 .src6_arb_atom_q       (spc6_pcx_atm_lq[2]),    // Templated
                 .src6_arb_req_q        (spc6_pcx_req_lq[2]),    // Templated
                 .src7_arb_atom_q       (spc7_pcx_atm_lq[2]),    // Templated
                 .src7_arb_req_q        (spc7_pcx_req_lq[2]),    // Templated
                 .src8_arb_atom_q       (1'b0),                  // Templated
                 .src8_arb_req_q        (1'b0),                  // Templated
                 .stall_q_d1               (sctag2_pcx_stall_lq_d1),   // Templated
                 .scan_in(pcx_arbl2_scanin),
                 .scan_out(pcx_arbl2_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lb),
                 .ccx_aclk                (ccx_aclk_arb_lb),
                 .ccx_bclk                (ccx_bclk_arb_lb)
                 );

ccx_arb pcx_arbl3(
                 // Outputs
                 .arb_grant_a           (arb3_grant_l_a[8:0]),     // Templated
                 .arb_q0_holdbar_a      (arb3_q0_holdbar_l_a[8:0]), // Templated
                 .arb_qsel0_a           (arb3_qsel0_l_a[8:0]),     // Templated
                 .arb_qsel1_a           (arb3_qsel1_l_a[8:0]),     // Templated
                 .arb_shift_a           (arb3_shift_l_a[8:0]),     // Templated
                 .arb_src0_grant_a      (pcx_spc0_grant_a[3]),   // Templated
                 .arb_src1_grant_a      (pcx_spc1_grant_a[3]),   // Templated
                 .arb_src2_grant_a      (pcx_spc2_grant_a[3]),   // Templated
                 .arb_src3_grant_a      (pcx_spc3_grant_a[3]),   // Templated
                 .arb_src4_grant_a      (pcx_spc4_grant_a_unused[3]),   // Templated
                 .arb_src5_grant_a      (pcx_spc5_grant_a_unused[3]),   // Templated
                 .arb_src6_grant_a      (pcx_spc6_grant_a_unused[3]),   // Templated
                 .arb_src7_grant_a      (pcx_spc7_grant_a_unused[3]),   // Templated
                 .arb_src8_grant_a      (arb3_src8_grant_l_unused), // Templated
                 .ccx_dest_atom_a       (pcx_sctag3_atm_a),    // Templated
                 .ccx_dest_data_rdy_a   (pcx_sctag3_data_rdy_a), // Templated
                 // Inputs
                 .src0_arb_atom_q       (spc0_pcx_atm_lq[3]),    // Templated
                 .src0_arb_req_q        (spc0_pcx_req_lq[3]),    // Templated
                 .src1_arb_atom_q       (spc1_pcx_atm_lq[3]),    // Templated
                 .src1_arb_req_q        (spc1_pcx_req_lq[3]),    // Templated
                 .src2_arb_atom_q       (spc2_pcx_atm_lq[3]),    // Templated
                 .src2_arb_req_q        (spc2_pcx_req_lq[3]),    // Templated
                 .src3_arb_atom_q       (spc3_pcx_atm_lq[3]),    // Templated
                 .src3_arb_req_q        (spc3_pcx_req_lq[3]),    // Templated
                 .src4_arb_atom_q       (spc4_pcx_atm_lq[3]),    // Templated
                 .src4_arb_req_q        (spc4_pcx_req_lq[3]),    // Templated
                 .src5_arb_atom_q       (spc5_pcx_atm_lq[3]),    // Templated
                 .src5_arb_req_q        (spc5_pcx_req_lq[3]),    // Templated
                 .src6_arb_atom_q       (spc6_pcx_atm_lq[3]),    // Templated
                 .src6_arb_req_q        (spc6_pcx_req_lq[3]),    // Templated
                 .src7_arb_atom_q       (spc7_pcx_atm_lq[3]),    // Templated
                 .src7_arb_req_q        (spc7_pcx_req_lq[3]),    // Templated
                 .src8_arb_atom_q       (1'b0),                  // Templated
                 .src8_arb_req_q        (1'b0),                  // Templated
                 .stall_q_d1               (sctag3_pcx_stall_lq_d1),   // Templated
                 .scan_in(pcx_arbl3_scanin),
                 .scan_out(pcx_arbl3_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lb),
                 .ccx_aclk                (ccx_aclk_arb_lb),
                 .ccx_bclk                (ccx_bclk_arb_lb)
                 );

ccx_arb pcx_arbl4(
                 // Outputs
                 .arb_grant_a           (arb4_grant_l_a[8:0]),     // Templated
                 .arb_q0_holdbar_a      (arb4_q0_holdbar_l_a[8:0]), // Templated
                 .arb_qsel0_a           (arb4_qsel0_l_a[8:0]),     // Templated
                 .arb_qsel1_a           (arb4_qsel1_l_a[8:0]),     // Templated
                 .arb_shift_a           (arb4_shift_l_a[8:0]),     // Templated
                 .arb_src0_grant_a      (pcx_spc0_grant_a[4]),   // Templated
                 .arb_src1_grant_a      (pcx_spc1_grant_a[4]),   // Templated
                 .arb_src2_grant_a      (pcx_spc2_grant_a[4]),   // Templated
                 .arb_src3_grant_a      (pcx_spc3_grant_a[4]),   // Templated
                 .arb_src4_grant_a      (pcx_spc4_grant_a_unused[4]),   // Templated
                 .arb_src5_grant_a      (pcx_spc5_grant_a_unused[4]),   // Templated
                 .arb_src6_grant_a      (pcx_spc6_grant_a_unused[4]),   // Templated
                 .arb_src7_grant_a      (pcx_spc7_grant_a_unused[4]),   // Templated
                 .arb_src8_grant_a      (arb4_src8_grant_l_unused), // Templated
                 .ccx_dest_atom_a       (pcx_sctag4_atm_a_unused),    // Templated
                 .ccx_dest_data_rdy_a   (pcx_sctag4_data_rdy_a_unused), // Templated
                 // Inputs
                 .src0_arb_atom_q       (spc0_pcx_atm_lq[4]),    // Templated
                 .src0_arb_req_q        (spc0_pcx_req_lq[4]),    // Templated
                 .src1_arb_atom_q       (spc1_pcx_atm_lq[4]),    // Templated
                 .src1_arb_req_q        (spc1_pcx_req_lq[4]),    // Templated
                 .src2_arb_atom_q       (spc2_pcx_atm_lq[4]),    // Templated
                 .src2_arb_req_q        (spc2_pcx_req_lq[4]),    // Templated
                 .src3_arb_atom_q       (spc3_pcx_atm_lq[4]),    // Templated
                 .src3_arb_req_q        (spc3_pcx_req_lq[4]),    // Templated
                 .src4_arb_atom_q       (spc4_pcx_atm_lq[4]),    // Templated
                 .src4_arb_req_q        (spc4_pcx_req_lq[4]),    // Templated
                 .src5_arb_atom_q       (spc5_pcx_atm_lq[4]),    // Templated
                 .src5_arb_req_q        (spc5_pcx_req_lq[4]),    // Templated
                 .src6_arb_atom_q       (spc6_pcx_atm_lq[4]),    // Templated
                 .src6_arb_req_q        (spc6_pcx_req_lq[4]),    // Templated
                 .src7_arb_atom_q       (spc7_pcx_atm_lq[4]),    // Templated
                 .src7_arb_req_q        (spc7_pcx_req_lq[4]),    // Templated
                 .src8_arb_atom_q       (1'b0),                  // Templated
                 .src8_arb_req_q        (1'b0),                  // Templated
                 .stall_q_d1               (sctag4_pcx_stall_lq_d1),   // Templated
                 .scan_in(pcx_arbl4_scanin),
                 .scan_out(pcx_arbl4_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );

ccx_arb pcx_arbl5  (
                   // Outputs
                   .arb_grant_a         (arb5_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_a    (arb5_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_a         (arb5_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_a         (arb5_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_a         (arb5_shift_l_a[8:0]),     // Templated
                   .arb_src0_grant_a    (pcx_spc0_grant_a[5]),   // Templated
                   .arb_src1_grant_a    (pcx_spc1_grant_a[5]),   // Templated
                   .arb_src2_grant_a    (pcx_spc2_grant_a[5]),   // Templated
                   .arb_src3_grant_a    (pcx_spc3_grant_a[5]),   // Templated
                   .arb_src4_grant_a    (pcx_spc4_grant_a_unused[5]),   // Templated
                   .arb_src5_grant_a    (pcx_spc5_grant_a_unused[5]),   // Templated
                   .arb_src6_grant_a    (pcx_spc6_grant_a_unused[5]),   // Templated
                   .arb_src7_grant_a    (pcx_spc7_grant_a_unused[5]),   // Templated
                   .arb_src8_grant_a    (arb5_src8_grant_l_unused), // Templated
                   .ccx_dest_atom_a     (pcx_sctag5_atm_a_unused),    // Templated
                   .ccx_dest_data_rdy_a (pcx_sctag5_data_rdy_a_unused), // Templated
                   // Inputs
                   .src0_arb_atom_q     (spc0_pcx_atm_lq[5]),    // Templated
                   .src0_arb_req_q      (spc0_pcx_req_lq[5]),    // Templated
                   .src1_arb_atom_q     (spc1_pcx_atm_lq[5]),    // Templated
                   .src1_arb_req_q      (spc1_pcx_req_lq[5]),    // Templated
                   .src2_arb_atom_q     (spc2_pcx_atm_lq[5]),    // Templated
                   .src2_arb_req_q      (spc2_pcx_req_lq[5]),    // Templated
                   .src3_arb_atom_q     (spc3_pcx_atm_lq[5]),    // Templated
                   .src3_arb_req_q      (spc3_pcx_req_lq[5]),    // Templated
                   .src4_arb_atom_q     (spc4_pcx_atm_lq[5]),    // Templated
                   .src4_arb_req_q      (spc4_pcx_req_lq[5]),    // Templated
                   .src5_arb_atom_q     (spc5_pcx_atm_lq[5]),    // Templated
                   .src5_arb_req_q      (spc5_pcx_req_lq[5]),    // Templated
                   .src6_arb_atom_q     (spc6_pcx_atm_lq[5]),    // Templated
                   .src6_arb_req_q      (spc6_pcx_req_lq[5]),    // Templated
                   .src7_arb_atom_q     (spc7_pcx_atm_lq[5]),    // Templated
                   .src7_arb_req_q      (spc7_pcx_req_lq[5]),    // Templated
                   .src8_arb_atom_q     (1'b0),                  // Templated
                   .src8_arb_req_q      (1'b0),                  // Templated
                   .stall_q_d1             (sctag5_pcx_stall_lq_d1),   // Templated
                   .scan_in(pcx_arbl5_scanin),
                   .scan_out(pcx_arbl5_scanout),
                   .l2clk               (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );

ccx_arb pcx_arbl6  (
                   // Outputs
                   .arb_grant_a         (arb6_grant_l_a[8:0]),     // Templated
                   .arb_q0_holdbar_a    (arb6_q0_holdbar_l_a[8:0]), // Templated
                   .arb_qsel0_a         (arb6_qsel0_l_a[8:0]),     // Templated
                   .arb_qsel1_a         (arb6_qsel1_l_a[8:0]),     // Templated
                   .arb_shift_a         (arb6_shift_l_a[8:0]),     // Templated
                   .arb_src0_grant_a    (pcx_spc0_grant_a[6]),   // Templated
                   .arb_src1_grant_a    (pcx_spc1_grant_a[6]),   // Templated
                   .arb_src2_grant_a    (pcx_spc2_grant_a[6]),   // Templated
                   .arb_src3_grant_a    (pcx_spc3_grant_a[6]),   // Templated
                   .arb_src4_grant_a    (pcx_spc4_grant_a_unused[6]),   // Templated
                   .arb_src5_grant_a    (pcx_spc5_grant_a_unused[6]),   // Templated
                   .arb_src6_grant_a    (pcx_spc6_grant_a_unused[6]),   // Templated
                   .arb_src7_grant_a    (pcx_spc7_grant_a_unused[6]),   // Templated
                   .arb_src8_grant_a    (arb6_src8_grant_l_unused), // Templated
                   .ccx_dest_atom_a     (pcx_sctag6_atm_a_unused),    // Templated
                   .ccx_dest_data_rdy_a (pcx_sctag6_data_rdy_a_unused), // Templated
                   // Inputs
                   .src0_arb_atom_q     (spc0_pcx_atm_lq[6]),    // Templated
                   .src0_arb_req_q      (spc0_pcx_req_lq[6]),    // Templated
                   .src1_arb_atom_q     (spc1_pcx_atm_lq[6]),    // Templated
                   .src1_arb_req_q      (spc1_pcx_req_lq[6]),    // Templated
                   .src2_arb_atom_q     (spc2_pcx_atm_lq[6]),    // Templated
                   .src2_arb_req_q      (spc2_pcx_req_lq[6]),    // Templated
                   .src3_arb_atom_q     (spc3_pcx_atm_lq[6]),    // Templated
                   .src3_arb_req_q      (spc3_pcx_req_lq[6]),    // Templated
                   .src4_arb_atom_q     (spc4_pcx_atm_lq[6]),    // Templated
                   .src4_arb_req_q      (spc4_pcx_req_lq[6]),    // Templated
                   .src5_arb_atom_q     (spc5_pcx_atm_lq[6]),    // Templated
                   .src5_arb_req_q      (spc5_pcx_req_lq[6]),    // Templated
                   .src6_arb_atom_q     (spc6_pcx_atm_lq[6]),    // Templated
                   .src6_arb_req_q      (spc6_pcx_req_lq[6]),    // Templated
                   .src7_arb_atom_q     (spc7_pcx_atm_lq[6]),    // Templated
                   .src7_arb_req_q      (spc7_pcx_req_lq[6]),    // Templated
                   .src8_arb_atom_q     (1'b0),                  // Templated
                   .src8_arb_req_q      (1'b0),                  // Templated
                   .stall_q_d1             (sctag6_pcx_stall_lq_d1),   // Templated
                   .scan_in(pcx_arbl6_scanin),
                   .scan_out(pcx_arbl6_scanout),
                   .l2clk               (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lb),
                 .ccx_aclk                (ccx_aclk_arb_lb),
                 .ccx_bclk                (ccx_bclk_arb_lb)
                 );

ccx_arb pcx_arbl7 (
                  // Outputs
                  .arb_grant_a          (arb7_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb7_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb7_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb7_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb7_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (pcx_spc0_grant_a[7]),   // Templated
                  .arb_src1_grant_a     (pcx_spc1_grant_a[7]),   // Templated
                  .arb_src2_grant_a     (pcx_spc2_grant_a[7]),   // Templated
                  .arb_src3_grant_a     (pcx_spc3_grant_a[7]),   // Templated
                  .arb_src4_grant_a     (pcx_spc4_grant_a_unused[7]),   // Templated
                  .arb_src5_grant_a     (pcx_spc5_grant_a_unused[7]),   // Templated
                  .arb_src6_grant_a     (pcx_spc6_grant_a_unused[7]),   // Templated
                  .arb_src7_grant_a     (pcx_spc7_grant_a_unused[7]),   // Templated
                  .arb_src8_grant_a     (arb7_src8_grant_l_unused), // Templated
                  .ccx_dest_atom_a      (pcx_sctag7_atm_a_unused),    // Templated
                  .ccx_dest_data_rdy_a  (pcx_sctag7_data_rdy_a_unused), // Templated
                  // Inputs
                  .src0_arb_atom_q      (spc0_pcx_atm_lq[7]),    // Templated
                  .src0_arb_req_q       (spc0_pcx_req_lq[7]),    // Templated
                  .src1_arb_atom_q      (spc1_pcx_atm_lq[7]),    // Templated
                  .src1_arb_req_q       (spc1_pcx_req_lq[7]),    // Templated
                  .src2_arb_atom_q      (spc2_pcx_atm_lq[7]),    // Templated
                  .src2_arb_req_q       (spc2_pcx_req_lq[7]),    // Templated
                  .src3_arb_atom_q      (spc3_pcx_atm_lq[7]),    // Templated
                  .src3_arb_req_q       (spc3_pcx_req_lq[7]),    // Templated
                  .src4_arb_atom_q      (spc4_pcx_atm_lq[7]),    // Templated
                  .src4_arb_req_q       (spc4_pcx_req_lq[7]),    // Templated
                  .src5_arb_atom_q      (spc5_pcx_atm_lq[7]),    // Templated
                  .src5_arb_req_q       (spc5_pcx_req_lq[7]),    // Templated
                  .src6_arb_atom_q      (spc6_pcx_atm_lq[7]),    // Templated
                  .src6_arb_req_q       (spc6_pcx_req_lq[7]),    // Templated
                  .src7_arb_atom_q      (spc7_pcx_atm_lq[7]),    // Templated
                  .src7_arb_req_q       (spc7_pcx_req_lq[7]),    // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (1'b0),                  // Templated
                  .stall_q_d1              (sctag7_pcx_stall_lq_d1),   // Templated
                  .scan_in(pcx_arbl7_scanin),
                  .scan_out(pcx_arbl7_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lb),
                 .ccx_aclk                (ccx_aclk_arb_lb),
                 .ccx_bclk                (ccx_bclk_arb_lb)
                 );

/*
 ccx_arb  AUTO_TEMPLATE(
 // Outputs
 .arb_grant_a		(arb@_grant_l_a[8:0]),
 .arb_q0_holdbar_a		(arb@_q0_holdbar_l_a[8:0]),
 .arb_qsel0_a		(arb@_qsel0_l_a[8:0]),
 .arb_qsel1_a		(arb@_qsel1_l_a[8:0]),
 .arb_shift_a		(arb@_shift_l_a[8:0]),
 .arb_src0_grant_a		(pcx_spc0_grant_a[@]),
 .arb_src1_grant_a		(pcx_spc1_grant_a[@]),
 .arb_src2_grant_a		(pcx_spc2_grant_a[@]),
 .arb_src3_grant_a		(pcx_spc3_grant_a[@]),
 .arb_src4_grant_a		(pcx_spc4_grant_a[@]),
 .arb_src5_grant_a		(pcx_spc5_grant_a[@]),
 .arb_src6_grant_a		(pcx_spc6_grant_a[@]),
 .arb_src7_grant_a		(pcx_spc7_grant_a[@]),
 .arb_src8_grant_a		(arb8_src8_grant_l_unused),
 .ccx_dest_data_rdy_a	(pcx_fpio_data_rdy_a),
 .ccx_dest_atom_x	(arb8_dest_atom_l_unused),
 // Inputs
 .src0_arb_atom_q		(spc0_pcx_atm_lq[@]),
 .src0_arb_req_q		(spc0_pcx_req_lq[@]),
 .src1_arb_atom_q		(spc1_pcx_atm_lq[@]),
 .src1_arb_req_q		(spc1_pcx_req_lq[@]),
 .src2_arb_atom_q		(spc2_pcx_atm_lq[@]),
 .src2_arb_req_q		(spc2_pcx_req_lq[@]),
 .src3_arb_atom_q		(spc3_pcx_atm_lq[@]),
 .src3_arb_req_q		(spc3_pcx_req_lq[@]),
 .src4_arb_atom_q		(spc4_pcx_atm_lq[@]),
 .src4_arb_req_q		(spc4_pcx_req_lq[@]),
 .src5_arb_atom_q		(spc5_pcx_atm_lq[@]),
 .src5_arb_req_q		(spc5_pcx_req_lq[@]),
 .src6_arb_atom_q		(spc6_pcx_atm_lq[@]),
 .src6_arb_req_q		(spc6_pcx_req_lq[@]),
 .src7_arb_atom_q		(spc7_pcx_atm_lq[@]),
 .src7_arb_req_q		(spc7_pcx_req_lq[@]),
 .src8_arb_atom_q		(1'b0),
 .src8_arb_req_q		(1'b0),
 .stall_q_d1			(io_pcx_stall_lq_d1),
);
 */
//
ccx_arb pcx_arbl8 (
                  // Outputs
                  .arb_grant_a          (arb8_grant_l_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb8_q0_holdbar_l_a[8:0]), // Templated
                  .arb_qsel0_a          (arb8_qsel0_l_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb8_qsel1_l_a[8:0]),     // Templated
                  .arb_shift_a          (arb8_shift_l_a[8:0]),     // Templated
                  .arb_src0_grant_a     (pcx_spc0_grant_a[8]),   // Templated
                  .arb_src1_grant_a     (pcx_spc1_grant_a[8]),   // Templated
                  .arb_src2_grant_a     (pcx_spc2_grant_a[8]),   // Templated
                  .arb_src3_grant_a     (pcx_spc3_grant_a[8]),   // Templated
                  .arb_src4_grant_a     (pcx_spc4_grant_a_unused[8]),   // Templated
                  .arb_src5_grant_a     (pcx_spc5_grant_a_unused[8]),   // Templated
                  .arb_src6_grant_a     (pcx_spc6_grant_a_unused[8]),   // Templated
                  .arb_src7_grant_a     (pcx_spc7_grant_a_unused[8]),   // Templated
                  .arb_src8_grant_a     (arb8_src8_grant_l_unused), // Templated
                  .ccx_dest_atom_a      (arb8_dest_atom_l_unused), // Templated
                  .ccx_dest_data_rdy_a  (pcx_fpio_data_rdy_a), // Templated
                  // Inputs
                  .src0_arb_atom_q      (spc0_pcx_atm_lq[8]),    // Templated
                  .src0_arb_req_q       (spc0_pcx_req_lq[8]),    // Templated
                  .src1_arb_atom_q      (spc1_pcx_atm_lq[8]),    // Templated
                  .src1_arb_req_q       (spc1_pcx_req_lq[8]),    // Templated
                  .src2_arb_atom_q      (spc2_pcx_atm_lq[8]),    // Templated
                  .src2_arb_req_q       (spc2_pcx_req_lq[8]),    // Templated
                  .src3_arb_atom_q      (spc3_pcx_atm_lq[8]),    // Templated
                  .src3_arb_req_q       (spc3_pcx_req_lq[8]),    // Templated
                  .src4_arb_atom_q      (spc4_pcx_atm_lq[8]),    // Templated
                  .src4_arb_req_q       (spc4_pcx_req_lq[8]),    // Templated
                  .src5_arb_atom_q      (spc5_pcx_atm_lq[8]),    // Templated
                  .src5_arb_req_q       (spc5_pcx_req_lq[8]),    // Templated
                  .src6_arb_atom_q      (spc6_pcx_atm_lq[8]),    // Templated
                  .src6_arb_req_q       (spc6_pcx_req_lq[8]),    // Templated
                  .src7_arb_atom_q      (spc7_pcx_atm_lq[8]),    // Templated
                  .src7_arb_req_q       (spc7_pcx_req_lq[8]),    // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (1'b0),                  // Templated
                  .stall_q_d1              (io_pcx_stall_lq_d1),       // Templated
                  .scan_in(pcx_arbl8_scanin),
                  .scan_out(pcx_arbl8_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_lt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_lt),
                 .ccx_aclk                (ccx_aclk_arb_lt),
                 .ccx_bclk                (ccx_bclk_arb_lt)
                 );


// buffer req signals feeding right arbiters
pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc0     (
	.din	({sctag0_pcx_stall_pq_d1, spc0_pcx_req_pq_r_0[8:0],spc0_pcx_atm_pq_r_0[8:0]}),
	.dout	({sctag0_pcx_stall_rq_d1,   spc0_pcx_req_rq[8:0],spc0_pcx_atm_rq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc1     (
	.din	({sctag1_pcx_stall_pq_d1, spc1_pcx_req_pq_r_0[8:0],spc1_pcx_atm_pq_r_0[8:0]}),
	.dout	({sctag1_pcx_stall_rq_d1,   spc1_pcx_req_rq[8:0],spc1_pcx_atm_rq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_20 i_bufq_r_spc2     (
	.din	({io_pcx_stall_pq_d1, sctag2_pcx_stall_pq_d1, spc2_pcx_req_pq_r_0[8:0],spc2_pcx_atm_pq_r_0[8:0]}),
	.dout	({io_pcx_stall_rq_d1,   sctag2_pcx_stall_rq_d1,   spc2_pcx_req_rq[8:0],spc2_pcx_atm_rq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc3     (
	.din	({sctag3_pcx_stall_pq_d1, spc3_pcx_req_pq_r_0[8:0],spc3_pcx_atm_pq_r_0[8:0]}),
	.dout	({sctag3_pcx_stall_rq_d1,   spc3_pcx_req_rq[8:0],spc3_pcx_atm_rq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc4     (
	.din	({sctag4_pcx_stall_pq_d1, spc4_pcx_req_pq_r_0[8:0],spc4_pcx_atm_pq_r_0[8:0]}),
	.dout	({sctag4_pcx_stall_rq_d1,   spc4_pcx_req_rq[8:0],spc4_pcx_atm_rq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc5     (
	.din	({sctag5_pcx_stall_pq_d1, spc5_pcx_req_pq_r_0[8:0],spc5_pcx_atm_pq_r_0[8:0]}),
	.dout	({sctag5_pcx_stall_rq_d1,   spc5_pcx_req_rq[8:0],spc5_pcx_atm_rq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc6     (
	.din	({sctag6_pcx_stall_pq_d1, spc6_pcx_req_pq_r_0[8:0],spc6_pcx_atm_pq_r_0[8:0]}),
	.dout	({sctag6_pcx_stall_rq_d1,   spc6_pcx_req_rq[8:0],spc6_pcx_atm_rq[8:0]})
);

pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc7     (
	.din	({sctag7_pcx_stall_pq_d1 , spc7_pcx_req_pq_r_0[8:0],spc7_pcx_atm_pq_r_0[8:0]}),
	.dout	({sctag7_pcx_stall_rq_d1,   spc7_pcx_req_rq[8:0],spc7_pcx_atm_rq[8:0]})
);


/*
 ccx_arb  AUTO_TEMPLATE(
 // Outputs
 .arb_grant_a		(arb@_grant_r_a[8:0]),
 .arb_q0_holdbar_a		(arb@_q0_holdbar_r_a[8:0]),
 .arb_qsel0_a		(arb@_qsel0_r_a[8:0]),
 .arb_qsel1_a		(arb@_qsel1_r_a[8:0]),
 .arb_shift_a		(arb@_shift_r_a[8:0]),
 .arb_src0_grant_a		(pcx_spc0_grant_a_unused[@]),
 .arb_src1_grant_a		(pcx_spc1_grant_a_unused[@]),
 .arb_src2_grant_a		(pcx_spc2_grant_a_unused[@]),
 .arb_src3_grant_a		(pcx_spc3_grant_a_unused[@]),
 .arb_src4_grant_a		(pcx_spc4_grant_a_unused[@]),
 .arb_src5_grant_a		(pcx_spc5_grant_a_unused[@]),
 .arb_src6_grant_a		(pcx_spc6_grant_a_unused[@]),
 .arb_src7_grant_a		(pcx_spc7_grant_a_unused[@]),
 .arb_src8_grant_a		(arb@_src8_grant_r_unused),
 .ccx_dest_data_rdy_a	(pcx_sctag@_data_rdy_a_unused),
 .ccx_dest_atom_x	(pcx_sctag@_atm_px1_unused),
 // Inputs
 .src0_arb_atom_q		(spc0_pcx_atm_rq[@]),
 .src0_arb_req_q		(spc0_pcx_req_rq[@]),
 .src1_arb_atom_q		(spc1_pcx_atm_rq[@]),
 .src1_arb_req_q		(spc1_pcx_req_rq[@]),
 .src2_arb_atom_q		(spc2_pcx_atm_rq[@]),
 .src2_arb_req_q		(spc2_pcx_req_rq[@]),
 .src3_arb_atom_q		(spc3_pcx_atm_rq[@]),
 .src3_arb_req_q		(spc3_pcx_req_rq[@]),
 .src4_arb_atom_q		(spc4_pcx_atm_rq[@]),
 .src4_arb_req_q		(spc4_pcx_req_rq[@]),
 .src5_arb_atom_q		(spc5_pcx_atm_rq[@]),
 .src5_arb_req_q		(spc5_pcx_req_rq[@]),
 .src6_arb_atom_q		(spc6_pcx_atm_rq[@]),
 .src6_arb_req_q		(spc6_pcx_req_rq[@]),
 .src7_arb_atom_q		(spc7_pcx_atm_rq[@]),
 .src7_arb_req_q		(spc7_pcx_req_rq[@]),
 .src8_arb_atom_q		(1'b0),
 .src8_arb_req_q		(1'b0),
 .stall_q_d1			(sctag@_pcx_stall_rq_d1),
);
 */

ccx_arb pcx_arbr0 (
                  // Outputs
                  .arb_grant_a          (arb0_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb0_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb0_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb0_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb0_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (pcx_spc0_grant_a_unused[0]),   // Templated
                  .arb_src1_grant_a     (pcx_spc1_grant_a_unused[0]),   // Templated
                  .arb_src2_grant_a     (pcx_spc2_grant_a_unused[0]),   // Templated
                  .arb_src3_grant_a     (pcx_spc3_grant_a_unused[0]),   // Templated
                  .arb_src4_grant_a     (pcx_spc4_grant_a[0]),   // Templated
                  .arb_src5_grant_a     (pcx_spc5_grant_a[0]),   // Templated
                  .arb_src6_grant_a     (pcx_spc6_grant_a[0]),   // Templated
                  .arb_src7_grant_a     (pcx_spc7_grant_a[0]),   // Templated
                  .arb_src8_grant_a     (arb0_src8_grant_r_unused), // Templated
                  .ccx_dest_atom_a      (pcx_sctag0_atm_a_unused),    // Templated
                  .ccx_dest_data_rdy_a  (pcx_sctag0_data_rdy_a_unused), // Templated
                  // Inputs
                  .src0_arb_atom_q      (spc0_pcx_atm_rq[0]),    // Templated
                  .src0_arb_req_q       (spc0_pcx_req_rq[0]),    // Templated
                  .src1_arb_atom_q      (spc1_pcx_atm_rq[0]),    // Templated
                  .src1_arb_req_q       (spc1_pcx_req_rq[0]),    // Templated
                  .src2_arb_atom_q      (spc2_pcx_atm_rq[0]),    // Templated
                  .src2_arb_req_q       (spc2_pcx_req_rq[0]),    // Templated
                  .src3_arb_atom_q      (spc3_pcx_atm_rq[0]),    // Templated
                  .src3_arb_req_q       (spc3_pcx_req_rq[0]),    // Templated
                  .src4_arb_atom_q      (spc4_pcx_atm_rq[0]),    // Templated
                  .src4_arb_req_q       (spc4_pcx_req_rq[0]),    // Templated
                  .src5_arb_atom_q      (spc5_pcx_atm_rq[0]),    // Templated
                  .src5_arb_req_q       (spc5_pcx_req_rq[0]),    // Templated
                  .src6_arb_atom_q      (spc6_pcx_atm_rq[0]),    // Templated
                  .src6_arb_req_q       (spc6_pcx_req_rq[0]),    // Templated
                  .src7_arb_atom_q      (spc7_pcx_atm_rq[0]),    // Templated
                  .src7_arb_req_q       (spc7_pcx_req_rq[0]),    // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (1'b0),                  // Templated
                  .stall_q_d1              (sctag0_pcx_stall_rq_d1),   // Templated
                  .scan_in(pcx_arbr0_scanin),
                  .scan_out(pcx_arbr0_scanout),
                  .l2clk                (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                 .ccx_aclk                (ccx_aclk_arb_rt),
                 .ccx_bclk                (ccx_bclk_arb_rt)
                 );

ccx_arb pcx_arbr1(
                 // Outputs
                 .arb_grant_a           (arb1_grant_r_a[8:0]),     // Templated
                 .arb_q0_holdbar_a      (arb1_q0_holdbar_r_a[8:0]), // Templated
                 .arb_qsel0_a           (arb1_qsel0_r_a[8:0]),     // Templated
                 .arb_qsel1_a           (arb1_qsel1_r_a[8:0]),     // Templated
                 .arb_shift_a           (arb1_shift_r_a[8:0]),     // Templated
                 .arb_src0_grant_a      (pcx_spc0_grant_a_unused[1]),   // Templated
                 .arb_src1_grant_a      (pcx_spc1_grant_a_unused[1]),   // Templated
                 .arb_src2_grant_a      (pcx_spc2_grant_a_unused[1]),   // Templated
                 .arb_src3_grant_a      (pcx_spc3_grant_a_unused[1]),   // Templated
                 .arb_src4_grant_a      (pcx_spc4_grant_a[1]),   // Templated
                 .arb_src5_grant_a      (pcx_spc5_grant_a[1]),   // Templated
                 .arb_src6_grant_a      (pcx_spc6_grant_a[1]),   // Templated
                 .arb_src7_grant_a      (pcx_spc7_grant_a[1]),   // Templated
                 .arb_src8_grant_a      (arb1_src8_grant_r_unused), // Templated
                 .ccx_dest_atom_a       (pcx_sctag1_atm_a_unused),    // Templated
                 .ccx_dest_data_rdy_a   (pcx_sctag1_data_rdy_a_unused), // Templated
                 // Inputs
                 .src0_arb_atom_q       (spc0_pcx_atm_rq[1]),    // Templated
                 .src0_arb_req_q        (spc0_pcx_req_rq[1]),    // Templated
                 .src1_arb_atom_q       (spc1_pcx_atm_rq[1]),    // Templated
                 .src1_arb_req_q        (spc1_pcx_req_rq[1]),    // Templated
                 .src2_arb_atom_q       (spc2_pcx_atm_rq[1]),    // Templated
                 .src2_arb_req_q        (spc2_pcx_req_rq[1]),    // Templated
                 .src3_arb_atom_q       (spc3_pcx_atm_rq[1]),    // Templated
                 .src3_arb_req_q        (spc3_pcx_req_rq[1]),    // Templated
                 .src4_arb_atom_q       (spc4_pcx_atm_rq[1]),    // Templated
                 .src4_arb_req_q        (spc4_pcx_req_rq[1]),    // Templated
                 .src5_arb_atom_q       (spc5_pcx_atm_rq[1]),    // Templated
                 .src5_arb_req_q        (spc5_pcx_req_rq[1]),    // Templated
                 .src6_arb_atom_q       (spc6_pcx_atm_rq[1]),    // Templated
                 .src6_arb_req_q        (spc6_pcx_req_rq[1]),    // Templated
                 .src7_arb_atom_q       (spc7_pcx_atm_rq[1]),    // Templated
                 .src7_arb_req_q        (spc7_pcx_req_rq[1]),    // Templated
                 .src8_arb_atom_q       (1'b0),                  // Templated
                 .src8_arb_req_q        (1'b0),                  // Templated
                 .stall_q_d1               (sctag1_pcx_stall_rq_d1),   // Templated
                 .scan_in(pcx_arbr1_scanin),
                 .scan_out(pcx_arbr1_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                 .ccx_aclk                (ccx_aclk_arb_rt),
                 .ccx_bclk                (ccx_bclk_arb_rt)
                 );

ccx_arb pcx_arbr2(
                 // Outputs
                 .arb_grant_a           (arb2_grant_r_a[8:0]),     // Templated
                 .arb_q0_holdbar_a      (arb2_q0_holdbar_r_a[8:0]), // Templated
                 .arb_qsel0_a           (arb2_qsel0_r_a[8:0]),     // Templated
                 .arb_qsel1_a           (arb2_qsel1_r_a[8:0]),     // Templated
                 .arb_shift_a           (arb2_shift_r_a[8:0]),     // Templated
                 .arb_src0_grant_a      (pcx_spc0_grant_a_unused[2]),   // Templated
                 .arb_src1_grant_a      (pcx_spc1_grant_a_unused[2]),   // Templated
                 .arb_src2_grant_a      (pcx_spc2_grant_a_unused[2]),   // Templated
                 .arb_src3_grant_a      (pcx_spc3_grant_a_unused[2]),   // Templated
                 .arb_src4_grant_a      (pcx_spc4_grant_a[2]),   // Templated
                 .arb_src5_grant_a      (pcx_spc5_grant_a[2]),   // Templated
                 .arb_src6_grant_a      (pcx_spc6_grant_a[2]),   // Templated
                 .arb_src7_grant_a      (pcx_spc7_grant_a[2]),   // Templated
                 .arb_src8_grant_a      (arb2_src8_grant_r_unused), // Templated
                 .ccx_dest_atom_a       (pcx_sctag2_atm_a_unused),    // Templated
                 .ccx_dest_data_rdy_a   (pcx_sctag2_data_rdy_a_unused), // Templated
                 // Inputs
                 .src0_arb_atom_q       (spc0_pcx_atm_rq[2]),    // Templated
                 .src0_arb_req_q        (spc0_pcx_req_rq[2]),    // Templated
                 .src1_arb_atom_q       (spc1_pcx_atm_rq[2]),    // Templated
                 .src1_arb_req_q        (spc1_pcx_req_rq[2]),    // Templated
                 .src2_arb_atom_q       (spc2_pcx_atm_rq[2]),    // Templated
                 .src2_arb_req_q        (spc2_pcx_req_rq[2]),    // Templated
                 .src3_arb_atom_q       (spc3_pcx_atm_rq[2]),    // Templated
                 .src3_arb_req_q        (spc3_pcx_req_rq[2]),    // Templated
                 .src4_arb_atom_q       (spc4_pcx_atm_rq[2]),    // Templated
                 .src4_arb_req_q        (spc4_pcx_req_rq[2]),    // Templated
                 .src5_arb_atom_q       (spc5_pcx_atm_rq[2]),    // Templated
                 .src5_arb_req_q        (spc5_pcx_req_rq[2]),    // Templated
                 .src6_arb_atom_q       (spc6_pcx_atm_rq[2]),    // Templated
                 .src6_arb_req_q        (spc6_pcx_req_rq[2]),    // Templated
                 .src7_arb_atom_q       (spc7_pcx_atm_rq[2]),    // Templated
                 .src7_arb_req_q        (spc7_pcx_req_rq[2]),    // Templated
                 .src8_arb_atom_q       (1'b0),                  // Templated
                 .src8_arb_req_q        (1'b0),                  // Templated
                 .stall_q_d1               (sctag2_pcx_stall_rq_d1),   // Templated
                 .scan_in(pcx_arbr2_scanin),
                 .scan_out(pcx_arbr2_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rb),
                 .ccx_aclk                (ccx_aclk_arb_rb),
                 .ccx_bclk                (ccx_bclk_arb_rb)
                 );

ccx_arb pcx_arbr3(
                 // Outputs
                 .arb_grant_a           (arb3_grant_r_a[8:0]),     // Templated
                 .arb_q0_holdbar_a      (arb3_q0_holdbar_r_a[8:0]), // Templated
                 .arb_qsel0_a           (arb3_qsel0_r_a[8:0]),     // Templated
                 .arb_qsel1_a           (arb3_qsel1_r_a[8:0]),     // Templated
                 .arb_shift_a           (arb3_shift_r_a[8:0]),     // Templated
                 .arb_src0_grant_a      (pcx_spc0_grant_a_unused[3]),   // Templated
                 .arb_src1_grant_a      (pcx_spc1_grant_a_unused[3]),   // Templated
                 .arb_src2_grant_a      (pcx_spc2_grant_a_unused[3]),   // Templated
                 .arb_src3_grant_a      (pcx_spc3_grant_a_unused[3]),   // Templated
                 .arb_src4_grant_a      (pcx_spc4_grant_a[3]),   // Templated
                 .arb_src5_grant_a      (pcx_spc5_grant_a[3]),   // Templated
                 .arb_src6_grant_a      (pcx_spc6_grant_a[3]),   // Templated
                 .arb_src7_grant_a      (pcx_spc7_grant_a[3]),   // Templated
                 .arb_src8_grant_a      (arb3_src8_grant_r_unused), // Templated
                 .ccx_dest_atom_a       (pcx_sctag3_atm_a_unused),    // Templated
                 .ccx_dest_data_rdy_a   (pcx_sctag3_data_rdy_a_unused), // Templated
                 // Inputs
                 .src0_arb_atom_q       (spc0_pcx_atm_rq[3]),    // Templated
                 .src0_arb_req_q        (spc0_pcx_req_rq[3]),    // Templated
                 .src1_arb_atom_q       (spc1_pcx_atm_rq[3]),    // Templated
                 .src1_arb_req_q        (spc1_pcx_req_rq[3]),    // Templated
                 .src2_arb_atom_q       (spc2_pcx_atm_rq[3]),    // Templated
                 .src2_arb_req_q        (spc2_pcx_req_rq[3]),    // Templated
                 .src3_arb_atom_q       (spc3_pcx_atm_rq[3]),    // Templated
                 .src3_arb_req_q        (spc3_pcx_req_rq[3]),    // Templated
                 .src4_arb_atom_q       (spc4_pcx_atm_rq[3]),    // Templated
                 .src4_arb_req_q        (spc4_pcx_req_rq[3]),    // Templated
                 .src5_arb_atom_q       (spc5_pcx_atm_rq[3]),    // Templated
                 .src5_arb_req_q        (spc5_pcx_req_rq[3]),    // Templated
                 .src6_arb_atom_q       (spc6_pcx_atm_rq[3]),    // Templated
                 .src6_arb_req_q        (spc6_pcx_req_rq[3]),    // Templated
                 .src7_arb_atom_q       (spc7_pcx_atm_rq[3]),    // Templated
                 .src7_arb_req_q        (spc7_pcx_req_rq[3]),    // Templated
                 .src8_arb_atom_q       (1'b0),                  // Templated
                 .src8_arb_req_q        (1'b0),                  // Templated
                 .stall_q_d1               (sctag3_pcx_stall_rq_d1),   // Templated
                 .scan_in(pcx_arbr3_scanin),
                 .scan_out(pcx_arbr3_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rb),
                 .ccx_aclk                (ccx_aclk_arb_rb),
                 .ccx_bclk                (ccx_bclk_arb_rb)
                 );

ccx_arb pcx_arbr4(
                 // Outputs
                 .arb_grant_a           (arb4_grant_r_a[8:0]),     // Templated
                 .arb_q0_holdbar_a      (arb4_q0_holdbar_r_a[8:0]), // Templated
                 .arb_qsel0_a           (arb4_qsel0_r_a[8:0]),     // Templated
                 .arb_qsel1_a           (arb4_qsel1_r_a[8:0]),     // Templated
                 .arb_shift_a           (arb4_shift_r_a[8:0]),     // Templated
                 .arb_src0_grant_a      (pcx_spc0_grant_a_unused[4]),   // Templated
                 .arb_src1_grant_a      (pcx_spc1_grant_a_unused[4]),   // Templated
                 .arb_src2_grant_a      (pcx_spc2_grant_a_unused[4]),   // Templated
                 .arb_src3_grant_a      (pcx_spc3_grant_a_unused[4]),   // Templated
                 .arb_src4_grant_a      (pcx_spc4_grant_a[4]),   // Templated
                 .arb_src5_grant_a      (pcx_spc5_grant_a[4]),   // Templated
                 .arb_src6_grant_a      (pcx_spc6_grant_a[4]),   // Templated
                 .arb_src7_grant_a      (pcx_spc7_grant_a[4]),   // Templated
                 .arb_src8_grant_a      (arb4_src8_grant_r_unused), // Templated
                 .ccx_dest_atom_a       (pcx_sctag4_atm_a),    // Templated
                 .ccx_dest_data_rdy_a   (pcx_sctag4_data_rdy_a), // Templated
                 // Inputs
                 .src0_arb_atom_q       (spc0_pcx_atm_rq[4]),    // Templated
                 .src0_arb_req_q        (spc0_pcx_req_rq[4]),    // Templated
                 .src1_arb_atom_q       (spc1_pcx_atm_rq[4]),    // Templated
                 .src1_arb_req_q        (spc1_pcx_req_rq[4]),    // Templated
                 .src2_arb_atom_q       (spc2_pcx_atm_rq[4]),    // Templated
                 .src2_arb_req_q        (spc2_pcx_req_rq[4]),    // Templated
                 .src3_arb_atom_q       (spc3_pcx_atm_rq[4]),    // Templated
                 .src3_arb_req_q        (spc3_pcx_req_rq[4]),    // Templated
                 .src4_arb_atom_q       (spc4_pcx_atm_rq[4]),    // Templated
                 .src4_arb_req_q        (spc4_pcx_req_rq[4]),    // Templated
                 .src5_arb_atom_q       (spc5_pcx_atm_rq[4]),    // Templated
                 .src5_arb_req_q        (spc5_pcx_req_rq[4]),    // Templated
                 .src6_arb_atom_q       (spc6_pcx_atm_rq[4]),    // Templated
                 .src6_arb_req_q        (spc6_pcx_req_rq[4]),    // Templated
                 .src7_arb_atom_q       (spc7_pcx_atm_rq[4]),    // Templated
                 .src7_arb_req_q        (spc7_pcx_req_rq[4]),    // Templated
                 .src8_arb_atom_q       (1'b0),                  // Templated
                 .src8_arb_req_q        (1'b0),                  // Templated
                 .stall_q_d1               (sctag4_pcx_stall_rq_d1),   // Templated
                 .scan_in(pcx_arbr4_scanin),
                 .scan_out(pcx_arbr4_scanout),
                 .l2clk                 (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                 .ccx_aclk                (ccx_aclk_arb_rt),
                 .ccx_bclk                (ccx_bclk_arb_rt)
                 );

ccx_arb pcx_arbr5  (
                   // Outputs
                   .arb_grant_a         (arb5_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_a    (arb5_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_a         (arb5_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_a         (arb5_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_a         (arb5_shift_r_a[8:0]),     // Templated
                   .arb_src0_grant_a    (pcx_spc0_grant_a_unused[5]),   // Templated
                   .arb_src1_grant_a    (pcx_spc1_grant_a_unused[5]),   // Templated
                   .arb_src2_grant_a    (pcx_spc2_grant_a_unused[5]),   // Templated
                   .arb_src3_grant_a    (pcx_spc3_grant_a_unused[5]),   // Templated
                   .arb_src4_grant_a    (pcx_spc4_grant_a[5]),   // Templated
                   .arb_src5_grant_a    (pcx_spc5_grant_a[5]),   // Templated
                   .arb_src6_grant_a    (pcx_spc6_grant_a[5]),   // Templated
                   .arb_src7_grant_a    (pcx_spc7_grant_a[5]),   // Templated
                   .arb_src8_grant_a    (arb5_src8_grant_r_unused), // Templated
                   .ccx_dest_atom_a     (pcx_sctag5_atm_a),    // Templated
                   .ccx_dest_data_rdy_a (pcx_sctag5_data_rdy_a), // Templated
                   // Inputs
                   .src0_arb_atom_q     (spc0_pcx_atm_rq[5]),    // Templated
                   .src0_arb_req_q      (spc0_pcx_req_rq[5]),    // Templated
                   .src1_arb_atom_q     (spc1_pcx_atm_rq[5]),    // Templated
                   .src1_arb_req_q      (spc1_pcx_req_rq[5]),    // Templated
                   .src2_arb_atom_q     (spc2_pcx_atm_rq[5]),    // Templated
                   .src2_arb_req_q      (spc2_pcx_req_rq[5]),    // Templated
                   .src3_arb_atom_q     (spc3_pcx_atm_rq[5]),    // Templated
                   .src3_arb_req_q      (spc3_pcx_req_rq[5]),    // Templated
                   .src4_arb_atom_q     (spc4_pcx_atm_rq[5]),    // Templated
                   .src4_arb_req_q      (spc4_pcx_req_rq[5]),    // Templated
                   .src5_arb_atom_q     (spc5_pcx_atm_rq[5]),    // Templated
                   .src5_arb_req_q      (spc5_pcx_req_rq[5]),    // Templated
                   .src6_arb_atom_q     (spc6_pcx_atm_rq[5]),    // Templated
                   .src6_arb_req_q      (spc6_pcx_req_rq[5]),    // Templated
                   .src7_arb_atom_q     (spc7_pcx_atm_rq[5]),    // Templated
                   .src7_arb_req_q      (spc7_pcx_req_rq[5]),    // Templated
                   .src8_arb_atom_q     (1'b0),                  // Templated
                   .src8_arb_req_q      (1'b0),                  // Templated
                   .stall_q_d1             (sctag5_pcx_stall_rq_d1),   // Templated
                   .scan_in(pcx_arbr5_scanin),
                   .scan_out(pcx_arbr5_scanout),
                   .l2clk               (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rt),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                 .ccx_aclk                (ccx_aclk_arb_rt),
                 .ccx_bclk                (ccx_bclk_arb_rt)
                 );

ccx_arb pcx_arbr6  (
                   // Outputs
                   .arb_grant_a         (arb6_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_a    (arb6_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_a         (arb6_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_a         (arb6_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_a         (arb6_shift_r_a[8:0]),     // Templated
                   .arb_src0_grant_a    (pcx_spc0_grant_a_unused[6]),   // Templated
                   .arb_src1_grant_a    (pcx_spc1_grant_a_unused[6]),   // Templated
                   .arb_src2_grant_a    (pcx_spc2_grant_a_unused[6]),   // Templated
                   .arb_src3_grant_a    (pcx_spc3_grant_a_unused[6]),   // Templated
                   .arb_src4_grant_a    (pcx_spc4_grant_a[6]),   // Templated
                   .arb_src5_grant_a    (pcx_spc5_grant_a[6]),   // Templated
                   .arb_src6_grant_a    (pcx_spc6_grant_a[6]),   // Templated
                   .arb_src7_grant_a    (pcx_spc7_grant_a[6]),   // Templated
                   .arb_src8_grant_a    (arb6_src8_grant_r_unused), // Templated
                   .ccx_dest_atom_a     (pcx_sctag6_atm_a),    // Templated
                   .ccx_dest_data_rdy_a (pcx_sctag6_data_rdy_a), // Templated
                   // Inputs
                   .src0_arb_atom_q     (spc0_pcx_atm_rq[6]),    // Templated
                   .src0_arb_req_q      (spc0_pcx_req_rq[6]),    // Templated
                   .src1_arb_atom_q     (spc1_pcx_atm_rq[6]),    // Templated
                   .src1_arb_req_q      (spc1_pcx_req_rq[6]),    // Templated
                   .src2_arb_atom_q     (spc2_pcx_atm_rq[6]),    // Templated
                   .src2_arb_req_q      (spc2_pcx_req_rq[6]),    // Templated
                   .src3_arb_atom_q     (spc3_pcx_atm_rq[6]),    // Templated
                   .src3_arb_req_q      (spc3_pcx_req_rq[6]),    // Templated
                   .src4_arb_atom_q     (spc4_pcx_atm_rq[6]),    // Templated
                   .src4_arb_req_q      (spc4_pcx_req_rq[6]),    // Templated
                   .src5_arb_atom_q     (spc5_pcx_atm_rq[6]),    // Templated
                   .src5_arb_req_q      (spc5_pcx_req_rq[6]),    // Templated
                   .src6_arb_atom_q     (spc6_pcx_atm_rq[6]),    // Templated
                   .src6_arb_req_q      (spc6_pcx_req_rq[6]),    // Templated
                   .src7_arb_atom_q     (spc7_pcx_atm_rq[6]),    // Templated
                   .src7_arb_req_q      (spc7_pcx_req_rq[6]),    // Templated
                   .src8_arb_atom_q     (1'b0),                  // Templated
                   .src8_arb_req_q      (1'b0),                  // Templated
                   .stall_q_d1             (sctag6_pcx_stall_rq_d1),   // Templated
                   .scan_in(pcx_arbr6_scanin),
                   .scan_out(pcx_arbr6_scanout),
                   .l2clk               (l2clk),
                 .tcu_scan_en             (tcu_scan_en_arb_rb),
                 .tcu_pce_ov              (tcu_pce_ov_arb_rb),
                 .ccx_aclk                (ccx_aclk_arb_rb),
                 .ccx_bclk                (ccx_bclk_arb_rb)
                 );

ccx_arb pcx_arbr7 (
                  // Outputs
                  .arb_grant_a          (arb7_grant_r_a[8:0]),     // Templated
                  .arb_q0_holdbar_a     (arb7_q0_holdbar_r_a[8:0]), // Templated
                  .arb_qsel0_a          (arb7_qsel0_r_a[8:0]),     // Templated
                  .arb_qsel1_a          (arb7_qsel1_r_a[8:0]),     // Templated
                  .arb_shift_a          (arb7_shift_r_a[8:0]),     // Templated
                  .arb_src0_grant_a     (pcx_spc0_grant_a_unused[7]),   // Templated
                  .arb_src1_grant_a     (pcx_spc1_grant_a_unused[7]),   // Templated
                  .arb_src2_grant_a     (pcx_spc2_grant_a_unused[7]),   // Templated
                  .arb_src3_grant_a     (pcx_spc3_grant_a_unused[7]),   // Templated
                  .arb_src4_grant_a     (pcx_spc4_grant_a[7]),   // Templated
                  .arb_src5_grant_a     (pcx_spc5_grant_a[7]),   // Templated
                  .arb_src6_grant_a     (pcx_spc6_grant_a[7]),   // Templated
                  .arb_src7_grant_a     (pcx_spc7_grant_a[7]),   // Templated
                  .arb_src8_grant_a     (arb7_src8_grant_r_unused), // Templated
                  .ccx_dest_atom_a      (pcx_sctag7_atm_a),    // Templated
                  .ccx_dest_data_rdy_a  (pcx_sctag7_data_rdy_a), // Templated
                  // Inputs
                  .src0_arb_atom_q      (spc0_pcx_atm_rq[7]),    // Templated
                  .src0_arb_req_q       (spc0_pcx_req_rq[7]),    // Templated
                  .src1_arb_atom_q      (spc1_pcx_atm_rq[7]),    // Templated
                  .src1_arb_req_q       (spc1_pcx_req_rq[7]),    // Templated
                  .src2_arb_atom_q      (spc2_pcx_atm_rq[7]),    // Templated
                  .src2_arb_req_q       (spc2_pcx_req_rq[7]),    // Templated
                  .src3_arb_atom_q      (spc3_pcx_atm_rq[7]),    // Templated
                  .src3_arb_req_q       (spc3_pcx_req_rq[7]),    // Templated
                  .src4_arb_atom_q      (spc4_pcx_atm_rq[7]),    // Templated
                  .src4_arb_req_q       (spc4_pcx_req_rq[7]),    // Templated
                  .src5_arb_atom_q      (spc5_pcx_atm_rq[7]),    // Templated
                  .src5_arb_req_q       (spc5_pcx_req_rq[7]),    // Templated
                  .src6_arb_atom_q      (spc6_pcx_atm_rq[7]),    // Templated
                  .src6_arb_req_q       (spc6_pcx_req_rq[7]),    // Templated
                  .src7_arb_atom_q      (spc7_pcx_atm_rq[7]),    // Templated
                  .src7_arb_req_q       (spc7_pcx_req_rq[7]),    // Templated
                  .src8_arb_atom_q      (1'b0),                  // Templated
                  .src8_arb_req_q       (1'b0),                  // Templated
                  .stall_q_d1              (sctag7_pcx_stall_rq_d1),   // Templated
                  .scan_in(pcx_arbr7_scanin),
                  .scan_out(pcx_arbr7_scanout),
                  .l2clk                (l2clk),
                   .tcu_scan_en             (tcu_scan_en_arb_rb),
                   .tcu_pce_ov              (tcu_pce_ov_arb_rb),
                   .ccx_aclk                (ccx_aclk_arb_rb),
                   .ccx_bclk                (ccx_bclk_arb_rb)
                   );

/*
 ccx_arb  AUTO_TEMPLATE(
 // Outputs
 .arb_grant_a		(arb@_grant_r_a[8:0]),
 .arb_q0_holdbar_a		(arb@_q0_holdbar_r_a[8:0]),
 .arb_qsel0_a		(arb@_qsel0_r_a[8:0]),
 .arb_qsel1_a		(arb@_qsel1_r_a[8:0]),
 .arb_shift_a		(arb@_shift_r_a[8:0]),
 .arb_src0_grant_a		(pcx_spc0_grant_a_unused[@]),
 .arb_src1_grant_a		(pcx_spc1_grant_a_unused[@]),
 .arb_src2_grant_a		(pcx_spc2_grant_a_unused[@]),
 .arb_src3_grant_a		(pcx_spc3_grant_a_unused[@]),
 .arb_src4_grant_a		(pcx_spc4_grant_a_unused[@]),
 .arb_src5_grant_a		(pcx_spc5_grant_a_unused[@]),
 .arb_src6_grant_a		(pcx_spc6_grant_a_unused[@]),
 .arb_src7_grant_a		(pcx_spc7_grant_a_unused[@]),
 .arb_src8_grant_a		(arb8_src8_grant_r_unused),
 .ccx_dest_data_rdy_a	(pcx_fpio_data_rdy_unused_px1),
 .ccx_dest_atom_x	(arb8_dest_atom_r_unused),
 // Inputs
 .src0_arb_atom_q		(spc0_pcx_atm_rq[@]),
 .src0_arb_req_q		(spc0_pcx_req_rq[@]),
 .src1_arb_atom_q		(spc1_pcx_atm_rq[@]),
 .src1_arb_req_q		(spc1_pcx_req_rq[@]),
 .src2_arb_atom_q		(spc2_pcx_atm_rq[@]),
 .src2_arb_req_q		(spc2_pcx_req_rq[@]),
 .src3_arb_atom_q		(spc3_pcx_atm_rq[@]),
 .src3_arb_req_q		(spc3_pcx_req_rq[@]),
 .src4_arb_atom_q		(spc4_pcx_atm_rq[@]),
 .src4_arb_req_q		(spc4_pcx_req_rq[@]),
 .src5_arb_atom_q		(spc5_pcx_atm_rq[@]),
 .src5_arb_req_q		(spc5_pcx_req_rq[@]),
 .src6_arb_atom_q		(spc6_pcx_atm_rq[@]),
 .src6_arb_req_q		(spc6_pcx_req_rq[@]),
 .src7_arb_atom_q		(spc7_pcx_atm_rq[@]),
 .src7_arb_req_q		(spc7_pcx_req_rq[@]),
 .src8_arb_atom_q		(1'b0),
 .src8_arb_req_q		(1'b0),
 .stall_q_d1			(io_pcx_stall_rq_d1),
);
 */
//
ccx_arb pcx_arbr8 (
                  // Outputs
                   .arb_grant_a          (arb8_grant_r_a[8:0]),     // Templated
                   .arb_q0_holdbar_a     (arb8_q0_holdbar_r_a[8:0]), // Templated
                   .arb_qsel0_a          (arb8_qsel0_r_a[8:0]),     // Templated
                   .arb_qsel1_a          (arb8_qsel1_r_a[8:0]),     // Templated
                   .arb_shift_a          (arb8_shift_r_a[8:0]),     // Templated
                   .arb_src0_grant_a     (pcx_spc0_grant_a_unused[8]),   // Templated
                   .arb_src1_grant_a     (pcx_spc1_grant_a_unused[8]),   // Templated
                   .arb_src2_grant_a     (pcx_spc2_grant_a_unused[8]),   // Templated
                   .arb_src3_grant_a     (pcx_spc3_grant_a_unused[8]),   // Templated
                   .arb_src4_grant_a     (pcx_spc4_grant_a[8]),   // Templated
                   .arb_src5_grant_a     (pcx_spc5_grant_a[8]),   // Templated
                   .arb_src6_grant_a     (pcx_spc6_grant_a[8]),   // Templated
                   .arb_src7_grant_a     (pcx_spc7_grant_a[8]),   // Templated
                   .arb_src8_grant_a     (arb8_src8_grant_r_unused), // Templated
                   .ccx_dest_atom_a      (arb8_dest_atom_r_unused), // Templated
                   .ccx_dest_data_rdy_a  (pcx_fpio_data_rdy_a_unused), // Templated
                   // Inputs
                   .src0_arb_atom_q      (spc0_pcx_atm_rq[8]),    // Templated
                   .src0_arb_req_q       (spc0_pcx_req_rq[8]),    // Templated
                   .src1_arb_atom_q      (spc1_pcx_atm_rq[8]),    // Templated
                   .src1_arb_req_q       (spc1_pcx_req_rq[8]),    // Templated
                   .src2_arb_atom_q      (spc2_pcx_atm_rq[8]),    // Templated
                   .src2_arb_req_q       (spc2_pcx_req_rq[8]),    // Templated
                   .src3_arb_atom_q      (spc3_pcx_atm_rq[8]),    // Templated
                   .src3_arb_req_q       (spc3_pcx_req_rq[8]),    // Templated
                   .src4_arb_atom_q      (spc4_pcx_atm_rq[8]),    // Templated
                   .src4_arb_req_q       (spc4_pcx_req_rq[8]),    // Templated
                   .src5_arb_atom_q      (spc5_pcx_atm_rq[8]),    // Templated
                   .src5_arb_req_q       (spc5_pcx_req_rq[8]),    // Templated
                   .src6_arb_atom_q      (spc6_pcx_atm_rq[8]),    // Templated
                   .src6_arb_req_q       (spc6_pcx_req_rq[8]),    // Templated
                   .src7_arb_atom_q      (spc7_pcx_atm_rq[8]),    // Templated
                   .src7_arb_req_q       (spc7_pcx_req_rq[8]),    // Templated
                   .src8_arb_atom_q      (1'b0),                  // Templated
                   .src8_arb_req_q       (1'b0),                  // Templated
                   .stall_q_d1              (io_pcx_stall_rq_d1),       // Templated
                   .scan_in(pcx_arbr8_scanin),
                   .scan_out(pcx_arbr8_scanout),
                   .l2clk                (l2clk),
                   .tcu_scan_en             (tcu_scan_en_arb_rt),
                   .tcu_pce_ov              (tcu_pce_ov_arb_rt),
                   .ccx_aclk                (ccx_aclk_arb_rt),
                   .ccx_bclk                (ccx_bclk_arb_rt)
                   );


// fixscan start:
assign bfd4_scanin               = scan_in                  ;
assign bfd5_scanin               = bfd4_scanout             ;
assign bfg4_scanin               = bfd5_scanout             ;
assign bfg1_scanin               = bfg4_scanout             ;
assign bfd1_scanin               = bfg1_scanout             ;
assign bfd0_scanin               = bfd1_scanout             ;
assign bfd_io_scanin             = bfd0_scanout             ;
assign bfg8_scanin               = bfd_io_scanout           ;
assign bfg0_scanin               = bfg8_scanout           ;
assign pcx_arbl0_scanin          = bfg0_scanout             ;
assign pcx_arbl4_scanin          = pcx_arbl0_scanout        ;
assign pcx_arbl8_scanin          = pcx_arbl4_scanout        ;
assign pcx_arbl3_scanin          = pcx_arbl8_scanout        ;
assign pcx_arbl5_scanin          = pcx_arbl3_scanout        ;
assign pcx_arbl1_scanin          = pcx_arbl5_scanout        ;
assign pcx_arbl7_scanin          = pcx_arbl1_scanout        ;
assign pcx_arbl2_scanin          = pcx_arbl7_scanout        ;
assign pcx_arbl6_scanin          = pcx_arbl2_scanout        ;
assign bfg2_scanin               = pcx_arbl6_scanout        ;
assign bfd2_scanin               = bfg2_scanout             ;
assign bfd3_scanin               = bfd2_scanout             ;
assign bfg3_scanin               = bfd3_scanout             ;
assign bfg7_scanin               = bfg3_scanout             ;
assign bfd7_scanin               = bfg7_scanout             ;
assign bfd6_scanin               = bfd7_scanout             ;
assign bfg6_scanin               = bfd6_scanout             ;
assign pcx_arbr6_scanin          = bfg6_scanout             ;
assign pcx_arbr2_scanin          = pcx_arbr6_scanout        ;
assign pcx_arbr7_scanin          = pcx_arbr2_scanout        ;
assign pcx_arbr1_scanin          = pcx_arbr7_scanout        ;
assign pcx_arbr5_scanin          = pcx_arbr1_scanout        ;
assign pcx_arbr3_scanin          = pcx_arbr5_scanout        ;
assign pcx_arbr8_scanin          = pcx_arbr3_scanout        ;
assign pcx_arbr4_scanin          = pcx_arbr8_scanout        ;
assign pcx_arbr0_scanin          = pcx_arbr4_scanout        ;
assign bfg5_scanin               = pcx_arbr0_scanout        ;
assign pcx_dpa_scanin            = bfg5_scanout             ;
assign scan_out                  = pcx_dpa_scanout          ;

// fixscan end:
endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_40x__rep_1__stack_130c__width_130 (
  din, 
  dout);
  input [129:0] din;
  output [129:0] dout;


buff #(130)  d0_0 (
.in(din[129:0]),
.out(dout[129:0])
);


endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_16x__rep_1__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_48x__rep_1__stack_none__width_18 (
  din, 
  dout);
  input [17:0] din;
  output [17:0] dout;


buff #(18)  d0_0 (
.in(din[17:0]),
.out(dout[17:0])
);


endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_32x__rep_1__stack_150c__width_130 (
  din, 
  dout);
  input [129:0] din;
  output [129:0] dout;


buff #(130)  d0_0 (
.in(din[129:0]),
.out(dout[129:0])
);


endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_19 (
  din, 
  dout);
  input [18:0] din;
  output [18:0] dout;


buff #(19)  d0_0 (
.in(din[18:0]),
.out(dout[18:0])
);


endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_48x__rep_1__stack_20r__width_20 (
  din, 
  dout);
  input [19:0] din;
  output [19:0] dout;


buff #(20)  d0_0 (
.in(din[19:0]),
.out(dout[19:0])
);


endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module pcx_buff_macro__dbuff_32x__rep_1__stack_none__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx(pcx_fpio_data_px2, pcx_fpio_data_rdy_px1, pcx_sctag0_atm_px1, 
	pcx_sctag0_data_px2, pcx_sctag0_data_rdy_px1, pcx_sctag1_atm_px1, 
	pcx_sctag1_data_px2, pcx_sctag1_data_rdy_px1, pcx_sctag2_atm_px1, 
	pcx_sctag2_data_px2, pcx_sctag2_data_rdy_px1, pcx_sctag3_atm_px1, 
	pcx_sctag3_data_px2, pcx_sctag3_data_rdy_px1, pcx_sctag4_atm_px1, 
	pcx_sctag4_data_px2, pcx_sctag4_data_rdy_px1, pcx_sctag5_atm_px1, 
	pcx_sctag5_data_px2, pcx_sctag5_data_rdy_px1, pcx_sctag6_atm_px1, 
	pcx_sctag6_data_px2, pcx_sctag6_data_rdy_px1, pcx_sctag7_atm_px1, 
	pcx_sctag7_data_px2, pcx_sctag7_data_rdy_px1, pcx_spc0_grant_px, 
	pcx_spc1_grant_px, pcx_spc2_grant_px, pcx_spc3_grant_px, 
	pcx_spc4_grant_px, pcx_spc5_grant_px, pcx_spc6_grant_px, 
	pcx_spc7_grant_px, io_pcx_stall_pq, sctag0_pcx_stall_pq, 
	sctag1_pcx_stall_pq, sctag2_pcx_stall_pq, sctag3_pcx_stall_pq, 
	sctag4_pcx_stall_pq, sctag5_pcx_stall_pq, sctag6_pcx_stall_pq, 
	sctag7_pcx_stall_pq, spc0_pcx_data_pa, spc0_pcx_req_pq, spc0_pcx_atm_pq,
	spc1_pcx_data_pa, spc1_pcx_req_pq, spc1_pcx_atm_pq, spc2_pcx_data_pa, 
	spc2_pcx_req_pq, spc2_pcx_atm_pq, spc3_pcx_data_pa, spc3_pcx_req_pq, 
	spc3_pcx_atm_pq, spc4_pcx_data_pa, spc4_pcx_req_pq, spc4_pcx_atm_pq, 
	spc5_pcx_data_pa, spc5_pcx_req_pq, spc5_pcx_atm_pq, spc6_pcx_data_pa, 
	spc6_pcx_req_pq, spc6_pcx_atm_pq, spc7_pcx_data_pa, spc7_pcx_req_pq, 
	spc7_pcx_atm_pq, tcu_scan_en, l2clk, scan_in, tcu_pce_ov, ccx_aclk, 
	ccx_bclk, scan_out);

	output	[129:0]		pcx_fpio_data_px2;
	output			pcx_fpio_data_rdy_px1;
	output			pcx_sctag0_atm_px1;
	output	[129:0]		pcx_sctag0_data_px2;
	output			pcx_sctag0_data_rdy_px1;
	output			pcx_sctag1_atm_px1;
	output	[129:0]		pcx_sctag1_data_px2;
	output			pcx_sctag1_data_rdy_px1;
	output			pcx_sctag2_atm_px1;
	output	[129:0]		pcx_sctag2_data_px2;
	output			pcx_sctag2_data_rdy_px1;
	output			pcx_sctag3_atm_px1;
	output	[129:0]		pcx_sctag3_data_px2;
	output			pcx_sctag3_data_rdy_px1;
	output			pcx_sctag4_atm_px1;
	output	[129:0]		pcx_sctag4_data_px2;
	output			pcx_sctag4_data_rdy_px1;
	output			pcx_sctag5_atm_px1;
	output	[129:0]		pcx_sctag5_data_px2;
	output			pcx_sctag5_data_rdy_px1;
	output			pcx_sctag6_atm_px1;
	output	[129:0]		pcx_sctag6_data_px2;
	output			pcx_sctag6_data_rdy_px1;
	output			pcx_sctag7_atm_px1;
	output	[129:0]		pcx_sctag7_data_px2;
	output			pcx_sctag7_data_rdy_px1;
	output	[8:0]		pcx_spc0_grant_px;
	output	[8:0]		pcx_spc1_grant_px;
	output	[8:0]		pcx_spc2_grant_px;
	output	[8:0]		pcx_spc3_grant_px;
	output	[8:0]		pcx_spc4_grant_px;
	output	[8:0]		pcx_spc5_grant_px;
	output	[8:0]		pcx_spc6_grant_px;
	output	[8:0]		pcx_spc7_grant_px;
	input			io_pcx_stall_pq;
	input			sctag0_pcx_stall_pq;
	input			sctag1_pcx_stall_pq;
	input			sctag2_pcx_stall_pq;
	input			sctag3_pcx_stall_pq;
	input			sctag4_pcx_stall_pq;
	input			sctag5_pcx_stall_pq;
	input			sctag6_pcx_stall_pq;
	input			sctag7_pcx_stall_pq;
	input	[129:0]		spc0_pcx_data_pa;
	input	[8:0]		spc0_pcx_req_pq;
	input	[8:0]		spc0_pcx_atm_pq;
	input	[129:0]		spc1_pcx_data_pa;
	input	[8:0]		spc1_pcx_req_pq;
	input	[8:0]		spc1_pcx_atm_pq;
	input	[129:0]		spc2_pcx_data_pa;
	input	[8:0]		spc2_pcx_req_pq;
	input	[8:0]		spc2_pcx_atm_pq;
	input	[129:0]		spc3_pcx_data_pa;
	input	[8:0]		spc3_pcx_req_pq;
	input	[8:0]		spc3_pcx_atm_pq;
	input	[129:0]		spc4_pcx_data_pa;
	input	[8:0]		spc4_pcx_req_pq;
	input	[8:0]		spc4_pcx_atm_pq;
	input	[129:0]		spc5_pcx_data_pa;
	input	[8:0]		spc5_pcx_req_pq;
	input	[8:0]		spc5_pcx_atm_pq;
	input	[129:0]		spc6_pcx_data_pa;
	input	[8:0]		spc6_pcx_req_pq;
	input	[8:0]		spc6_pcx_atm_pq;
	input	[129:0]		spc7_pcx_data_pa;
	input	[8:0]		spc7_pcx_req_pq;
	input	[8:0]		spc7_pcx_atm_pq;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;

	wire	[129:0]		pcx_fpio_data_px2_0;
	wire			pcx_sctag1_data_rdy_px1_0;
	wire			pcx_sctag1_atm_px1_0;
	wire			pcx_sctag3_data_rdy_px1_0;
	wire			pcx_sctag3_atm_px1_0;
	wire			pcx_sctag5_data_rdy_px1_0;
	wire			pcx_sctag5_atm_px1_0;
	wire			pcx_sctag7_data_rdy_px1_0;
	wire			pcx_sctag7_atm_px1_0;
	wire	[8:0]		pcx_spc0_grant_a;
	wire	[8:0]		pcx_spc0_grant_a_0;
	wire	[8:0]		pcx_spc1_grant_a;
	wire	[8:0]		pcx_spc1_grant_a_0;
	wire	[8:0]		pcx_spc2_grant_a;
	wire	[8:0]		pcx_spc2_grant_a_0;
	wire	[8:0]		pcx_spc3_grant_a;
	wire	[8:0]		pcx_spc3_grant_a_0;
	wire	[8:0]		pcx_spc4_grant_a;
	wire	[8:0]		pcx_spc4_grant_a_0;
	wire	[8:0]		pcx_spc5_grant_a;
	wire	[8:0]		pcx_spc5_grant_a_0;
	wire	[8:0]		pcx_spc6_grant_a;
	wire	[8:0]		pcx_spc6_grant_a_0;
	wire	[8:0]		pcx_spc7_grant_a;
	wire	[8:0]		pcx_spc7_grant_a_0;
	wire			io_pcx_stall_pq_buf;
	wire			fpio_atm1_unused;
	wire			fpio_atm2_unused;
	wire			rdy8_1_unused;
	wire			io_pcx_stall_pq_d1;
	wire	[8:0]		grant8_unused;
	wire			tcu_scan_en_bfg_8_unused;
	wire			tcu_pce_ov_bfg_8_unused;
	wire			ccx_aclk_bfg_8_unused;
	wire			ccx_bclk_bfg_8_unused;
	wire			pcx_fpio_data_rdy_a;
	wire			bfg8_scanin;
	wire			bfg8_scanout;
	wire			tcu_scan_en_bfd_lt;
	wire			tcu_pce_ov_bfd_lt;
	wire			ccx_aclk_bfd_lt;
	wire			ccx_bclk_bfd_lt;
	wire			sctag0_pcx_stall_pq_buf;
	wire			sctag0_pcx_stall_pq_d1;
	wire			tcu_scan_en_bfg_0_unused;
	wire			tcu_pce_ov_bfg_0_unused;
	wire			ccx_aclk_bfg_0_unused;
	wire			ccx_bclk_bfg_0_unused;
	wire			pcx_sctag0_atm_a;
	wire			pcx_sctag1_atm_a;
	wire			pcx_sctag0_data_rdy_a;
	wire			pcx_sctag1_data_rdy_a;
	wire			bfg0_scanin;
	wire			bfg0_scanout;
	wire			sctag1_pcx_stall_pq_buf;
	wire			atm10_unused;
	wire			atm11_unused;
	wire			rdy10_unused;
	wire			rdy11_unused;
	wire			sctag1_pcx_stall_pq_d1;
	wire			tcu_scan_en_bfg_1_unused;
	wire			tcu_pce_ov_bfg_1_unused;
	wire			ccx_aclk_bfg_1_unused;
	wire			ccx_bclk_bfg_1_unused;
	wire			bfg1_scanin;
	wire			bfg1_scanout;
	wire			tcu_scan_en_bfd_t;
	wire			tcu_pce_ov_bfd_t;
	wire			ccx_aclk_bfd_t;
	wire			ccx_bclk_bfd_t;
	wire			sctag2_pcx_stall_pq_buf;
	wire			sctag2_pcx_stall_pq_d1;
	wire			tcu_scan_en_bfg_2_unused;
	wire			tcu_pce_ov_bfg_2_unused;
	wire			ccx_aclk_bfg_2_unused;
	wire			ccx_bclk_bfg_2_unused;
	wire			pcx_sctag2_atm_a;
	wire			pcx_sctag3_atm_a;
	wire			pcx_sctag2_data_rdy_a;
	wire			pcx_sctag3_data_rdy_a;
	wire			bfg2_scanin;
	wire			bfg2_scanout;
	wire			tcu_scan_en_bfd_lb;
	wire			tcu_pce_ov_bfd_lb;
	wire			ccx_aclk_bfd_lb;
	wire			ccx_bclk_bfd_lb;
	wire			sctag3_pcx_stall_pq_buf;
	wire			atm30_unused;
	wire			atm31_unused;
	wire			rdy30_unused;
	wire			rdy31_unused;
	wire			sctag3_pcx_stall_pq_d1;
	wire			tcu_scan_en_bfg_3_unused;
	wire			tcu_pce_ov_bfg_3_unused;
	wire			ccx_aclk_bfg_3_unused;
	wire			ccx_bclk_bfg_3_unused;
	wire			bfg3_scanin;
	wire			bfg3_scanout;
	wire			tcu_scan_en_bfd_b;
	wire			tcu_pce_ov_bfd_b;
	wire			ccx_aclk_bfd_b;
	wire			ccx_bclk_bfd_b;
	wire			sctag4_pcx_stall_pq_buf;
	wire			sctag4_pcx_stall_pq_d1;
	wire			tcu_scan_en_bfg_4_unused;
	wire			tcu_pce_ov_bfg_4_unused;
	wire			ccx_aclk_bfg_4_unused;
	wire			ccx_bclk_bfg_4_unused;
	wire			pcx_sctag4_atm_a;
	wire			pcx_sctag5_atm_a;
	wire			pcx_sctag4_data_rdy_a;
	wire			pcx_sctag5_data_rdy_a;
	wire			bfg4_scanin;
	wire			bfg4_scanout;
	wire			tcu_scan_en_bfd_rt;
	wire			tcu_pce_ov_bfd_rt;
	wire			ccx_aclk_bfd_rt;
	wire			ccx_bclk_bfd_rt;
	wire			sctag5_pcx_stall_pq_buf;
	wire			atm50_unused;
	wire			atm51_unused;
	wire			rdy50_unused;
	wire			rdy51_unused;
	wire			sctag5_pcx_stall_pq_d1;
	wire			tcu_scan_en_bfg_5_unused;
	wire			tcu_pce_ov_bfg_5_unused;
	wire			ccx_aclk_bfg_5_unused;
	wire			ccx_bclk_bfg_5_unused;
	wire			bfg5_scanin;
	wire			bfg5_scanout;
	wire			sctag6_pcx_stall_pq_buf;
	wire			sctag6_pcx_stall_pq_d1;
	wire			tcu_scan_en_bfg_6_unused;
	wire			tcu_pce_ov_bfg_6_unused;
	wire			ccx_aclk_bfg_6_unused;
	wire			ccx_bclk_bfg_6_unused;
	wire			pcx_sctag6_atm_a;
	wire			pcx_sctag7_atm_a;
	wire			pcx_sctag6_data_rdy_a;
	wire			pcx_sctag7_data_rdy_a;
	wire			bfg6_scanin;
	wire			bfg6_scanout;
	wire			tcu_scan_en_bfd_rb;
	wire			tcu_pce_ov_bfd_rb;
	wire			ccx_aclk_bfd_rb;
	wire			ccx_bclk_bfd_rb;
	wire			sctag7_pcx_stall_pq_buf;
	wire			atm70_unused;
	wire			atm71_unused;
	wire			rdy70_unused;
	wire			rdy71_unused;
	wire			sctag7_pcx_stall_pq_d1;
	wire			tcu_scan_en_bfg_7_unused;
	wire			tcu_pce_ov_bfg_7_unused;
	wire			ccx_aclk_bfg_7_unused;
	wire			ccx_bclk_bfg_7_unused;
	wire			bfg7_scanin;
	wire			bfg7_scanout;
	wire	[8:0]		spc0_pcx_req_pq_l_0;
	wire	[8:0]		spc0_pcx_atm_pq_l_0;
	wire	[8:0]		spc0_pcx_req_pq_r_0;
	wire	[8:0]		spc0_pcx_atm_pq_r_0;
	wire	[8:0]		spc1_pcx_req_pq_l_0;
	wire	[8:0]		spc1_pcx_atm_pq_l_0;
	wire	[8:0]		spc1_pcx_req_pq_r_0;
	wire	[8:0]		spc1_pcx_atm_pq_r_0;
	wire	[8:0]		spc2_pcx_req_pq_l_0;
	wire	[8:0]		spc2_pcx_atm_pq_l_0;
	wire	[8:0]		spc2_pcx_req_pq_r_0;
	wire	[8:0]		spc2_pcx_atm_pq_r_0;
	wire	[8:0]		spc3_pcx_req_pq_l_0;
	wire	[8:0]		spc3_pcx_atm_pq_l_0;
	wire	[8:0]		spc3_pcx_req_pq_r_0;
	wire	[8:0]		spc3_pcx_atm_pq_r_0;
	wire	[8:0]		spc4_pcx_req_pq_l_0;
	wire	[8:0]		spc4_pcx_atm_pq_l_0;
	wire	[8:0]		spc4_pcx_req_pq_r_0;
	wire	[8:0]		spc4_pcx_atm_pq_r_0;
	wire	[8:0]		spc5_pcx_req_pq_l_0;
	wire	[8:0]		spc5_pcx_atm_pq_l_0;
	wire	[8:0]		spc5_pcx_req_pq_r_0;
	wire	[8:0]		spc5_pcx_atm_pq_r_0;
	wire	[8:0]		spc6_pcx_req_pq_l_0;
	wire	[8:0]		spc6_pcx_atm_pq_l_0;
	wire	[8:0]		spc6_pcx_req_pq_r_0;
	wire	[8:0]		spc6_pcx_atm_pq_r_0;
	wire	[8:0]		spc7_pcx_req_pq_l_0;
	wire	[8:0]		spc7_pcx_atm_pq_l_0;
	wire	[8:0]		spc7_pcx_req_pq_r_0;
	wire	[8:0]		spc7_pcx_atm_pq_r_0;
	wire	[129:0]		spc0_pcx_data_a;
	wire	[129:0]		spc1_pcx_data_a;
	wire	[129:0]		spc2_pcx_data_a;
	wire	[129:0]		spc3_pcx_data_a;
	wire	[129:0]		spc4_pcx_data_a;
	wire	[129:0]		spc5_pcx_data_a;
	wire	[129:0]		spc6_pcx_data_a;
	wire	[129:0]		spc7_pcx_data_a;
	wire			ccx_aclk_dpa_t;
	wire			ccx_bclk_dpa_t;
	wire			tcu_pce_ov_dpa_t;
	wire			tcu_scan_en_dpa_t;
	wire			ccx_aclk_dpa_b;
	wire			ccx_bclk_dpa_b;
	wire			tcu_pce_ov_dpa_b;
	wire			tcu_scan_en_dpa_b;
	wire	[129:0]		pcx_fpio_data_x_l;
	wire	[129:0]		pcx_scache0_data_x_l;
	wire	[129:0]		pcx_scache1_data_x_l;
	wire	[129:0]		pcx_scache2_data_x_l;
	wire	[129:0]		pcx_scache3_data_x_l;
	wire	[129:0]		pcx_scache4_data_x_l;
	wire	[129:0]		pcx_scache5_data_x_l;
	wire	[129:0]		pcx_scache6_data_x_l;
	wire	[129:0]		pcx_scache7_data_x_l;
	wire	[8:0]		arb0_grant_l_a;
	wire	[8:0]		arb0_q0_holdbar_l_a;
	wire	[8:0]		arb0_qsel0_l_a;
	wire	[8:0]		arb0_qsel1_l_a;
	wire	[8:0]		arb0_shift_l_a;
	wire	[8:0]		arb1_grant_l_a;
	wire	[8:0]		arb1_q0_holdbar_l_a;
	wire	[8:0]		arb1_qsel0_l_a;
	wire	[8:0]		arb1_qsel1_l_a;
	wire	[8:0]		arb1_shift_l_a;
	wire	[8:0]		arb2_grant_l_a;
	wire	[8:0]		arb2_q0_holdbar_l_a;
	wire	[8:0]		arb2_qsel0_l_a;
	wire	[8:0]		arb2_qsel1_l_a;
	wire	[8:0]		arb2_shift_l_a;
	wire	[8:0]		arb3_grant_l_a;
	wire	[8:0]		arb3_q0_holdbar_l_a;
	wire	[8:0]		arb3_qsel0_l_a;
	wire	[8:0]		arb3_qsel1_l_a;
	wire	[8:0]		arb3_shift_l_a;
	wire	[8:0]		arb4_grant_l_a;
	wire	[8:0]		arb4_q0_holdbar_l_a;
	wire	[8:0]		arb4_qsel0_l_a;
	wire	[8:0]		arb4_qsel1_l_a;
	wire	[8:0]		arb4_shift_l_a;
	wire	[8:0]		arb5_grant_l_a;
	wire	[8:0]		arb5_q0_holdbar_l_a;
	wire	[8:0]		arb5_qsel0_l_a;
	wire	[8:0]		arb5_qsel1_l_a;
	wire	[8:0]		arb5_shift_l_a;
	wire	[8:0]		arb6_grant_l_a;
	wire	[8:0]		arb6_q0_holdbar_l_a;
	wire	[8:0]		arb6_qsel0_l_a;
	wire	[8:0]		arb6_qsel1_l_a;
	wire	[8:0]		arb6_shift_l_a;
	wire	[8:0]		arb7_grant_l_a;
	wire	[8:0]		arb7_q0_holdbar_l_a;
	wire	[8:0]		arb7_qsel0_l_a;
	wire	[8:0]		arb7_qsel1_l_a;
	wire	[8:0]		arb7_shift_l_a;
	wire	[8:0]		arb8_grant_l_a;
	wire	[8:0]		arb8_q0_holdbar_l_a;
	wire	[8:0]		arb8_qsel0_l_a;
	wire	[8:0]		arb8_qsel1_l_a;
	wire	[8:0]		arb8_shift_l_a;
	wire	[8:0]		arb0_grant_r_a;
	wire	[8:0]		arb0_q0_holdbar_r_a;
	wire	[8:0]		arb0_qsel0_r_a;
	wire	[8:0]		arb0_qsel1_r_a;
	wire	[8:0]		arb0_shift_r_a;
	wire	[8:0]		arb1_grant_r_a;
	wire	[8:0]		arb1_q0_holdbar_r_a;
	wire	[8:0]		arb1_qsel0_r_a;
	wire	[8:0]		arb1_qsel1_r_a;
	wire	[8:0]		arb1_shift_r_a;
	wire	[8:0]		arb2_grant_r_a;
	wire	[8:0]		arb2_q0_holdbar_r_a;
	wire	[8:0]		arb2_qsel0_r_a;
	wire	[8:0]		arb2_qsel1_r_a;
	wire	[8:0]		arb2_shift_r_a;
	wire	[8:0]		arb3_grant_r_a;
	wire	[8:0]		arb3_q0_holdbar_r_a;
	wire	[8:0]		arb3_qsel0_r_a;
	wire	[8:0]		arb3_qsel1_r_a;
	wire	[8:0]		arb3_shift_r_a;
	wire	[8:0]		arb4_grant_r_a;
	wire	[8:0]		arb4_q0_holdbar_r_a;
	wire	[8:0]		arb4_qsel0_r_a;
	wire	[8:0]		arb4_qsel1_r_a;
	wire	[8:0]		arb4_shift_r_a;
	wire	[8:0]		arb5_grant_r_a;
	wire	[8:0]		arb5_q0_holdbar_r_a;
	wire	[8:0]		arb5_qsel0_r_a;
	wire	[8:0]		arb5_qsel1_r_a;
	wire	[8:0]		arb5_shift_r_a;
	wire	[8:0]		arb6_grant_r_a;
	wire	[8:0]		arb6_q0_holdbar_r_a;
	wire	[8:0]		arb6_qsel0_r_a;
	wire	[8:0]		arb6_qsel1_r_a;
	wire	[8:0]		arb6_shift_r_a;
	wire	[8:0]		arb7_grant_r_a;
	wire	[8:0]		arb7_q0_holdbar_r_a;
	wire	[8:0]		arb7_qsel0_r_a;
	wire	[8:0]		arb7_qsel1_r_a;
	wire	[8:0]		arb7_shift_r_a;
	wire	[8:0]		arb8_grant_r_a;
	wire	[8:0]		arb8_q0_holdbar_r_a;
	wire	[8:0]		arb8_qsel0_r_a;
	wire	[8:0]		arb8_qsel1_r_a;
	wire	[8:0]		arb8_shift_r_a;
	wire			pcx_dpa_scanin;
	wire			pcx_dpa_scanout;
	wire			bfd_io_scanin;
	wire			bfd_io_scanout;
	wire			tcu_scan_en_bfd_0;
	wire			tcu_pce_ov_bfd_0;
	wire			ccx_aclk_bfd_0;
	wire			ccx_bclk_bfd_0;
	wire	[129:0]		pcx_sctag0_data_px2_prebuf;
	wire			bfd0_scanin;
	wire			bfd0_scanout;
	wire			tcu_scan_en_bfd_1;
	wire			tcu_pce_ov_bfd_1;
	wire			ccx_aclk_bfd_1;
	wire			ccx_bclk_bfd_1;
	wire	[129:0]		pcx_sctag1_data_px2_prebuf;
	wire			bfd1_scanin;
	wire			bfd1_scanout;
	wire	[129:0]		pcx_sctag2_data_px2_prebuf;
	wire			bfd2_scanin;
	wire			bfd2_scanout;
	wire			tcu_scan_en_bfd_3;
	wire			tcu_pce_ov_bfd_3;
	wire			ccx_aclk_bfd_3;
	wire			ccx_bclk_bfd_3;
	wire	[129:0]		pcx_sctag3_data_px2_prebuf;
	wire			bfd3_scanin;
	wire			bfd3_scanout;
	wire	[129:0]		pcx_sctag4_data_px2_prebuf;
	wire			bfd4_scanin;
	wire			bfd4_scanout;
	wire			tcu_scan_en_bfd_5;
	wire			tcu_pce_ov_bfd_5;
	wire			ccx_aclk_bfd_5;
	wire			ccx_bclk_bfd_5;
	wire	[129:0]		pcx_sctag5_data_px2_prebuf;
	wire			bfd5_scanin;
	wire			bfd5_scanout;
	wire	[129:0]		pcx_sctag6_data_px2_prebuf;
	wire			bfd6_scanin;
	wire			bfd6_scanout;
	wire			tcu_scan_en_bfd_7;
	wire			tcu_pce_ov_bfd_7;
	wire			ccx_aclk_bfd_7;
	wire			ccx_bclk_bfd_7;
	wire	[129:0]		pcx_sctag7_data_px2_prebuf;
	wire			bfd7_scanin;
	wire			bfd7_scanout;
	wire	[8:0]		arb_grant_l_unused;
	wire	[8:0]		arb_q0_hold_l_unused;
	wire	[8:0]		arb_qsel0_l_unused;
	wire	[8:0]		arb_qsel1_l_unused;
	wire	[8:0]		arb_shift_l_unused;
	wire	[8:0]		arb_grant_r_unused;
	wire	[8:0]		arb_q0_hold_r_unused;
	wire	[8:0]		arb_qsel0_r_unused;
	wire	[8:0]		arb_qsel1_r_unused;
	wire	[8:0]		arb_shift_r_unused;
	wire			sctag0_pcx_stall_lq_d1;
	wire	[8:0]		spc0_pcx_req_lq;
	wire	[8:0]		spc0_pcx_atm_lq;
	wire			sctag1_pcx_stall_lq_d1;
	wire	[8:0]		spc1_pcx_req_lq;
	wire	[8:0]		spc1_pcx_atm_lq;
	wire			io_pcx_stall_lq_d1;
	wire			sctag2_pcx_stall_lq_d1;
	wire	[8:0]		spc2_pcx_req_lq;
	wire	[8:0]		spc2_pcx_atm_lq;
	wire			sctag3_pcx_stall_lq_d1;
	wire	[8:0]		spc3_pcx_req_lq;
	wire	[8:0]		spc3_pcx_atm_lq;
	wire			sctag4_pcx_stall_lq_d1;
	wire	[8:0]		spc4_pcx_req_lq;
	wire	[8:0]		spc4_pcx_atm_lq;
	wire			sctag5_pcx_stall_lq_d1;
	wire	[8:0]		spc5_pcx_req_lq;
	wire	[8:0]		spc5_pcx_atm_lq;
	wire			sctag6_pcx_stall_lq_d1;
	wire	[8:0]		spc6_pcx_req_lq;
	wire	[8:0]		spc6_pcx_atm_lq;
	wire			sctag7_pcx_stall_lq_d1;
	wire	[8:0]		spc7_pcx_req_lq;
	wire	[8:0]		spc7_pcx_atm_lq;
	wire			ccx_aclk_arb_lt;
	wire			ccx_bclk_arb_lt;
	wire			tcu_pce_ov_arb_lt;
	wire			tcu_scan_en_arb_lt;
	wire			ccx_aclk_arb_lb;
	wire			ccx_bclk_arb_lb;
	wire			tcu_pce_ov_arb_lb;
	wire			tcu_scan_en_arb_lb;
	wire			ccx_aclk_arb_rt;
	wire			ccx_bclk_arb_rt;
	wire			tcu_pce_ov_arb_rt;
	wire			tcu_scan_en_arb_rt;
	wire			ccx_aclk_arb_rb;
	wire			ccx_bclk_arb_rb;
	wire			tcu_pce_ov_arb_rb;
	wire			tcu_scan_en_arb_rb;
	wire	[8:0]		pcx_spc4_grant_a_unused;
	wire	[8:0]		pcx_spc5_grant_a_unused;
	wire	[8:0]		pcx_spc6_grant_a_unused;
	wire	[8:0]		pcx_spc7_grant_a_unused;
	wire			arb0_src8_grant_l_unused;
	wire			pcx_arbl0_scanin;
	wire			pcx_arbl0_scanout;
	wire			arb1_src8_grant_l_unused;
	wire			pcx_arbl1_scanin;
	wire			pcx_arbl1_scanout;
	wire			arb2_src8_grant_l_unused;
	wire			pcx_arbl2_scanin;
	wire			pcx_arbl2_scanout;
	wire			arb3_src8_grant_l_unused;
	wire			pcx_arbl3_scanin;
	wire			pcx_arbl3_scanout;
	wire			arb4_src8_grant_l_unused;
	wire			pcx_sctag4_atm_a_unused;
	wire			pcx_sctag4_data_rdy_a_unused;
	wire			pcx_arbl4_scanin;
	wire			pcx_arbl4_scanout;
	wire			arb5_src8_grant_l_unused;
	wire			pcx_sctag5_atm_a_unused;
	wire			pcx_sctag5_data_rdy_a_unused;
	wire			pcx_arbl5_scanin;
	wire			pcx_arbl5_scanout;
	wire			arb6_src8_grant_l_unused;
	wire			pcx_sctag6_atm_a_unused;
	wire			pcx_sctag6_data_rdy_a_unused;
	wire			pcx_arbl6_scanin;
	wire			pcx_arbl6_scanout;
	wire			arb7_src8_grant_l_unused;
	wire			pcx_sctag7_atm_a_unused;
	wire			pcx_sctag7_data_rdy_a_unused;
	wire			pcx_arbl7_scanin;
	wire			pcx_arbl7_scanout;
	wire			arb8_src8_grant_l_unused;
	wire			arb8_dest_atom_l_unused;
	wire			pcx_arbl8_scanin;
	wire			pcx_arbl8_scanout;
	wire			sctag0_pcx_stall_rq_d1;
	wire	[8:0]		spc0_pcx_req_rq;
	wire	[8:0]		spc0_pcx_atm_rq;
	wire			sctag1_pcx_stall_rq_d1;
	wire	[8:0]		spc1_pcx_req_rq;
	wire	[8:0]		spc1_pcx_atm_rq;
	wire			io_pcx_stall_rq_d1;
	wire			sctag2_pcx_stall_rq_d1;
	wire	[8:0]		spc2_pcx_req_rq;
	wire	[8:0]		spc2_pcx_atm_rq;
	wire			sctag3_pcx_stall_rq_d1;
	wire	[8:0]		spc3_pcx_req_rq;
	wire	[8:0]		spc3_pcx_atm_rq;
	wire			sctag4_pcx_stall_rq_d1;
	wire	[8:0]		spc4_pcx_req_rq;
	wire	[8:0]		spc4_pcx_atm_rq;
	wire			sctag5_pcx_stall_rq_d1;
	wire	[8:0]		spc5_pcx_req_rq;
	wire	[8:0]		spc5_pcx_atm_rq;
	wire			sctag6_pcx_stall_rq_d1;
	wire	[8:0]		spc6_pcx_req_rq;
	wire	[8:0]		spc6_pcx_atm_rq;
	wire			sctag7_pcx_stall_rq_d1;
	wire	[8:0]		spc7_pcx_req_rq;
	wire	[8:0]		spc7_pcx_atm_rq;
	wire	[8:0]		pcx_spc0_grant_a_unused;
	wire	[8:0]		pcx_spc1_grant_a_unused;
	wire	[8:0]		pcx_spc2_grant_a_unused;
	wire	[8:0]		pcx_spc3_grant_a_unused;
	wire			arb0_src8_grant_r_unused;
	wire			pcx_sctag0_atm_a_unused;
	wire			pcx_sctag0_data_rdy_a_unused;
	wire			pcx_arbr0_scanin;
	wire			pcx_arbr0_scanout;
	wire			arb1_src8_grant_r_unused;
	wire			pcx_sctag1_atm_a_unused;
	wire			pcx_sctag1_data_rdy_a_unused;
	wire			pcx_arbr1_scanin;
	wire			pcx_arbr1_scanout;
	wire			arb2_src8_grant_r_unused;
	wire			pcx_sctag2_atm_a_unused;
	wire			pcx_sctag2_data_rdy_a_unused;
	wire			pcx_arbr2_scanin;
	wire			pcx_arbr2_scanout;
	wire			arb3_src8_grant_r_unused;
	wire			pcx_sctag3_atm_a_unused;
	wire			pcx_sctag3_data_rdy_a_unused;
	wire			pcx_arbr3_scanin;
	wire			pcx_arbr3_scanout;
	wire			arb4_src8_grant_r_unused;
	wire			pcx_arbr4_scanin;
	wire			pcx_arbr4_scanout;
	wire			arb5_src8_grant_r_unused;
	wire			pcx_arbr5_scanin;
	wire			pcx_arbr5_scanout;
	wire			arb6_src8_grant_r_unused;
	wire			pcx_arbr6_scanin;
	wire			pcx_arbr6_scanout;
	wire			arb7_src8_grant_r_unused;
	wire			pcx_arbr7_scanin;
	wire			pcx_arbr7_scanout;
	wire			arb8_src8_grant_r_unused;
	wire			arb8_dest_atom_r_unused;
	wire			pcx_fpio_data_rdy_a_unused;
	wire			pcx_arbr8_scanin;
	wire			pcx_arbr8_scanout;

	assign arb_grant_l_unused[8:0] = {arb8_grant_l_a[8], arb7_grant_l_a[8], 
		arb6_grant_l_a[8], arb5_grant_l_a[8], arb4_grant_l_a[8], 
		arb3_grant_l_a[8], arb2_grant_l_a[8], arb1_grant_l_a[8], 
		arb0_grant_l_a[8]};
	assign arb_q0_hold_l_unused[8:0] = {arb8_q0_holdbar_l_a[8], 
		arb7_q0_holdbar_l_a[8], arb6_q0_holdbar_l_a[8], 
		arb5_q0_holdbar_l_a[8], arb4_q0_holdbar_l_a[8], 
		arb3_q0_holdbar_l_a[8], arb2_q0_holdbar_l_a[8], 
		arb1_q0_holdbar_l_a[8], arb0_q0_holdbar_l_a[8]};
	assign arb_qsel0_l_unused[8:0] = {arb8_qsel0_l_a[8], arb7_qsel0_l_a[8], 
		arb6_qsel0_l_a[8], arb5_qsel0_l_a[8], arb4_qsel0_l_a[8], 
		arb3_qsel0_l_a[8], arb2_qsel0_l_a[8], arb1_qsel0_l_a[8], 
		arb0_qsel0_l_a[8]};
	assign arb_qsel1_l_unused[8:0] = {arb8_qsel1_l_a[8], arb7_qsel1_l_a[8], 
		arb6_qsel1_l_a[8], arb5_qsel1_l_a[8], arb4_qsel1_l_a[8], 
		arb3_qsel1_l_a[8], arb2_qsel1_l_a[8], arb1_qsel1_l_a[8], 
		arb0_qsel1_l_a[8]};
	assign arb_shift_l_unused[8:0] = {arb8_shift_l_a[8], arb7_shift_l_a[8], 
		arb6_shift_l_a[8], arb5_shift_l_a[8], arb4_shift_l_a[8], 
		arb3_shift_l_a[8], arb2_shift_l_a[8], arb1_shift_l_a[8], 
		arb0_shift_l_a[8]};
	assign arb_grant_r_unused[8:0] = {arb8_grant_r_a[8], arb7_grant_r_a[8], 
		arb6_grant_r_a[8], arb5_grant_r_a[8], arb4_grant_r_a[8], 
		arb3_grant_r_a[8], arb2_grant_r_a[8], arb1_grant_r_a[8], 
		arb0_grant_r_a[8]};
	assign arb_q0_hold_r_unused[8:0] = {arb8_q0_holdbar_r_a[8], 
		arb7_q0_holdbar_r_a[8], arb6_q0_holdbar_r_a[8], 
		arb5_q0_holdbar_r_a[8], arb4_q0_holdbar_r_a[8], 
		arb3_q0_holdbar_r_a[8], arb2_q0_holdbar_r_a[8], 
		arb1_q0_holdbar_r_a[8], arb0_q0_holdbar_r_a[8]};
	assign arb_qsel0_r_unused[8:0] = {arb8_qsel0_r_a[8], arb7_qsel0_r_a[8], 
		arb6_qsel0_r_a[8], arb5_qsel0_r_a[8], arb4_qsel0_r_a[8], 
		arb3_qsel0_r_a[8], arb2_qsel0_r_a[8], arb1_qsel0_r_a[8], 
		arb0_qsel0_r_a[8]};
	assign arb_qsel1_r_unused[8:0] = {arb8_qsel1_r_a[8], arb7_qsel1_r_a[8], 
		arb6_qsel1_r_a[8], arb5_qsel1_r_a[8], arb4_qsel1_r_a[8], 
		arb3_qsel1_r_a[8], arb2_qsel1_r_a[8], arb1_qsel1_r_a[8], 
		arb0_qsel1_r_a[8]};
	assign arb_shift_r_unused[8:0] = {arb8_shift_r_a[8], arb7_shift_r_a[8], 
		arb6_shift_r_a[8], arb5_shift_r_a[8], arb4_shift_r_a[8], 
		arb3_shift_r_a[8], arb2_shift_r_a[8], arb1_shift_r_a[8], 
		arb0_shift_r_a[8]};
	assign bfd4_scanin = scan_in;
	assign bfd5_scanin = bfd4_scanout;
	assign bfg4_scanin = bfd5_scanout;
	assign bfg1_scanin = bfg4_scanout;
	assign bfd1_scanin = bfg1_scanout;
	assign bfd0_scanin = bfd1_scanout;
	assign bfd_io_scanin = bfd0_scanout;
	assign bfg8_scanin = bfd_io_scanout;
	assign bfg0_scanin = bfg8_scanout;
	assign pcx_arbl0_scanin = bfg0_scanout;
	assign pcx_arbl4_scanin = pcx_arbl0_scanout;
	assign pcx_arbl8_scanin = pcx_arbl4_scanout;
	assign pcx_arbl3_scanin = pcx_arbl8_scanout;
	assign pcx_arbl5_scanin = pcx_arbl3_scanout;
	assign pcx_arbl1_scanin = pcx_arbl5_scanout;
	assign pcx_arbl7_scanin = pcx_arbl1_scanout;
	assign pcx_arbl2_scanin = pcx_arbl7_scanout;
	assign pcx_arbl6_scanin = pcx_arbl2_scanout;
	assign bfg2_scanin = pcx_arbl6_scanout;
	assign bfd2_scanin = bfg2_scanout;
	assign bfd3_scanin = bfd2_scanout;
	assign bfg3_scanin = bfd3_scanout;
	assign bfg7_scanin = bfg3_scanout;
	assign bfd7_scanin = bfg7_scanout;
	assign bfd6_scanin = bfd7_scanout;
	assign bfg6_scanin = bfd6_scanout;
	assign pcx_arbr6_scanin = bfg6_scanout;
	assign pcx_arbr2_scanin = pcx_arbr6_scanout;
	assign pcx_arbr7_scanin = pcx_arbr2_scanout;
	assign pcx_arbr1_scanin = pcx_arbr7_scanout;
	assign pcx_arbr5_scanin = pcx_arbr1_scanout;
	assign pcx_arbr3_scanin = pcx_arbr5_scanout;
	assign pcx_arbr8_scanin = pcx_arbr3_scanout;
	assign pcx_arbr4_scanin = pcx_arbr8_scanout;
	assign pcx_arbr0_scanin = pcx_arbr4_scanout;
	assign bfg5_scanin = pcx_arbr0_scanout;
	assign pcx_dpa_scanin = bfg5_scanout;
	assign scan_out = pcx_dpa_scanout;

	buff_macro__dbuff_32x__rep_1__stack_150c__width_130 i_bufd_io(
		.din				(pcx_fpio_data_px2_0[129:0]), 
		.dout				(pcx_fpio_data_px2[129:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_bufd_sct1_1(
		.din				({pcx_sctag1_data_rdy_px1_0,
		pcx_sctag1_atm_px1_0}), 
		.dout				({pcx_sctag1_data_rdy_px1,
		pcx_sctag1_atm_px1}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_bufd_sct3_1(
		.din				({pcx_sctag3_data_rdy_px1_0,
		pcx_sctag3_atm_px1_0}), 
		.dout				({pcx_sctag3_data_rdy_px1,
		pcx_sctag3_atm_px1}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_bufd_sct5_1(
		.din				({pcx_sctag5_data_rdy_px1_0,
		pcx_sctag5_atm_px1_0}), 
		.dout				({pcx_sctag5_data_rdy_px1,
		pcx_sctag5_atm_px1}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_2 i_bufd_sct7_1(
		.din				({pcx_sctag7_data_rdy_px1_0,
		pcx_sctag7_atm_px1_0}), 
		.dout				({pcx_sctag7_data_rdy_px1,
		pcx_sctag7_atm_px1}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc0(
		.din				(pcx_spc0_grant_a[8:0]), 
		.dout				(pcx_spc0_grant_a_0[8:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc1(
		.din				(pcx_spc1_grant_a[8:0]), 
		.dout				(pcx_spc1_grant_a_0[8:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc2(
		.din				(pcx_spc2_grant_a[8:0]), 
		.dout				(pcx_spc2_grant_a_0[8:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc3(
		.din				(pcx_spc3_grant_a[8:0]), 
		.dout				(pcx_spc3_grant_a_0[8:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc4(
		.din				(pcx_spc4_grant_a[8:0]), 
		.dout				(pcx_spc4_grant_a_0[8:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc5(
		.din				(pcx_spc5_grant_a[8:0]), 
		.dout				(pcx_spc5_grant_a_0[8:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc6(
		.din				(pcx_spc6_grant_a[8:0]), 
		.dout				(pcx_spc6_grant_a_0[8:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_9 i_bufg_spc7(
		.din				(pcx_spc7_grant_a[8:0]), 
		.dout				(pcx_spc7_grant_a_0[8:0]));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_io_stall(
		.din				(io_pcx_stall_pq), 
		.dout				(io_pcx_stall_pq_buf));
	pcx_bfg_dp bfg8(
		.pcx_spc_grant_px		({fpio_atm1_unused,
		fpio_atm2_unused, pcx_fpio_data_rdy_px1, rdy8_1_unused,
		io_pcx_stall_pq_d1, grant8_unused[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_8_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_8_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_8_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_8_unused), 
		.pcx_spc_grant_pa		({2'b0, pcx_fpio_data_rdy_a,
		1'b0, io_pcx_stall_pq_buf, 9'b0}), 
		.scan_in			(bfg8_scanin), 
		.scan_out			(bfg8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_lt), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_lt), 
		.ccx_aclk			(ccx_aclk_bfd_lt), 
		.ccx_bclk			(ccx_bclk_bfd_lt));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct0_stall(
		.din				(sctag0_pcx_stall_pq), 
		.dout				(sctag0_pcx_stall_pq_buf));
	pcx_bfg_dp bfg0(
		.pcx_spc_grant_px		({pcx_sctag0_atm_px1,
		pcx_sctag1_atm_px1_0, pcx_sctag0_data_rdy_px1,
		pcx_sctag1_data_rdy_px1_0, sctag0_pcx_stall_pq_d1,
		pcx_spc0_grant_px[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_0_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_0_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_0_unused), 
		.pcx_spc_grant_pa		({pcx_sctag0_atm_a,
		pcx_sctag1_atm_a, pcx_sctag0_data_rdy_a, pcx_sctag1_data_rdy_a,
		sctag0_pcx_stall_pq_buf, pcx_spc0_grant_a_0[8:0]}), 
		.scan_in			(bfg0_scanin), 
		.scan_out			(bfg0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_lt), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_lt), 
		.ccx_aclk			(ccx_aclk_bfd_lt), 
		.ccx_bclk			(ccx_bclk_bfd_lt));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct1_stall(
		.din				(sctag1_pcx_stall_pq), 
		.dout				(sctag1_pcx_stall_pq_buf));
	pcx_bfg_dp bfg1(
		.pcx_spc_grant_px		({atm10_unused, atm11_unused,
		rdy10_unused, rdy11_unused, sctag1_pcx_stall_pq_d1,
		pcx_spc1_grant_px[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_1_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_1_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_1_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_1_unused), 
		.pcx_spc_grant_pa		({4'b0, sctag1_pcx_stall_pq_buf,
		pcx_spc1_grant_a_0[8:0]}), 
		.scan_in			(bfg1_scanin), 
		.scan_out			(bfg1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_t), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_t), 
		.ccx_aclk			(ccx_aclk_bfd_t), 
		.ccx_bclk			(ccx_bclk_bfd_t));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct2_stall(
		.din				(sctag2_pcx_stall_pq), 
		.dout				(sctag2_pcx_stall_pq_buf));
	pcx_bfg_dp bfg2(
		.pcx_spc_grant_px		({pcx_sctag2_atm_px1,
		pcx_sctag3_atm_px1_0, pcx_sctag2_data_rdy_px1,
		pcx_sctag3_data_rdy_px1_0, sctag2_pcx_stall_pq_d1,
		pcx_spc2_grant_px[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_2_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_2_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_2_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_2_unused), 
		.pcx_spc_grant_pa		({pcx_sctag2_atm_a,
		pcx_sctag3_atm_a, pcx_sctag2_data_rdy_a, pcx_sctag3_data_rdy_a,
		sctag2_pcx_stall_pq_buf, pcx_spc2_grant_a_0[8:0]}), 
		.scan_in			(bfg2_scanin), 
		.scan_out			(bfg2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_lb), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_lb), 
		.ccx_aclk			(ccx_aclk_bfd_lb), 
		.ccx_bclk			(ccx_bclk_bfd_lb));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct3_stall(
		.din				(sctag3_pcx_stall_pq), 
		.dout				(sctag3_pcx_stall_pq_buf));
	pcx_bfg_dp bfg3(
		.pcx_spc_grant_px		({atm30_unused, atm31_unused,
		rdy30_unused, rdy31_unused, sctag3_pcx_stall_pq_d1,
		pcx_spc3_grant_px[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_3_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_3_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_3_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_3_unused), 
		.pcx_spc_grant_pa		({4'b0, sctag3_pcx_stall_pq_buf,
		pcx_spc3_grant_a_0[8:0]}), 
		.scan_in			(bfg3_scanin), 
		.scan_out			(bfg3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_b), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_b), 
		.ccx_aclk			(ccx_aclk_bfd_b), 
		.ccx_bclk			(ccx_bclk_bfd_b));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct4_stall(
		.din				(sctag4_pcx_stall_pq), 
		.dout				(sctag4_pcx_stall_pq_buf));
	pcx_bfg_dp bfg4(
		.pcx_spc_grant_px		({pcx_sctag4_atm_px1,
		pcx_sctag5_atm_px1_0, pcx_sctag4_data_rdy_px1,
		pcx_sctag5_data_rdy_px1_0, sctag4_pcx_stall_pq_d1,
		pcx_spc4_grant_px[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_4_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_4_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_4_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_4_unused), 
		.pcx_spc_grant_pa		({pcx_sctag4_atm_a,
		pcx_sctag5_atm_a, pcx_sctag4_data_rdy_a, pcx_sctag5_data_rdy_a,
		sctag4_pcx_stall_pq_buf, pcx_spc4_grant_a_0[8:0]}), 
		.scan_in			(bfg4_scanin), 
		.scan_out			(bfg4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_rt), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_rt), 
		.ccx_aclk			(ccx_aclk_bfd_rt), 
		.ccx_bclk			(ccx_bclk_bfd_rt));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct5_stall(
		.din				(sctag5_pcx_stall_pq), 
		.dout				(sctag5_pcx_stall_pq_buf));
	pcx_bfg_dp bfg5(
		.pcx_spc_grant_px		({atm50_unused, atm51_unused,
		rdy50_unused, rdy51_unused, sctag5_pcx_stall_pq_d1,
		pcx_spc5_grant_px[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_5_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_5_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_5_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_5_unused), 
		.pcx_spc_grant_pa		({4'b0, sctag5_pcx_stall_pq_buf,
		pcx_spc5_grant_a_0[8:0]}), 
		.scan_in			(bfg5_scanin), 
		.scan_out			(bfg5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_t), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_t), 
		.ccx_aclk			(ccx_aclk_bfd_t), 
		.ccx_bclk			(ccx_bclk_bfd_t));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct6_stall(
		.din				(sctag6_pcx_stall_pq), 
		.dout				(sctag6_pcx_stall_pq_buf));
	pcx_bfg_dp bfg6(
		.pcx_spc_grant_px		({pcx_sctag6_atm_px1,
		pcx_sctag7_atm_px1_0, pcx_sctag6_data_rdy_px1,
		pcx_sctag7_data_rdy_px1_0, sctag6_pcx_stall_pq_d1,
		pcx_spc6_grant_px[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_6_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_6_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_6_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_6_unused), 
		.pcx_spc_grant_pa		({pcx_sctag6_atm_a,
		pcx_sctag7_atm_a, pcx_sctag6_data_rdy_a, pcx_sctag7_data_rdy_a,
		sctag6_pcx_stall_pq_buf, pcx_spc6_grant_a_0[8:0]}), 
		.scan_in			(bfg6_scanin), 
		.scan_out			(bfg6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_rb), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_rb), 
		.ccx_aclk			(ccx_aclk_bfd_rb), 
		.ccx_bclk			(ccx_bclk_bfd_rb));
	buff_macro__dbuff_16x__rep_1__stack_none__width_1 buf_sct7_stall(
		.din				(sctag7_pcx_stall_pq), 
		.dout				(sctag7_pcx_stall_pq_buf));
	pcx_bfg_dp bfg7(
		.pcx_spc_grant_px		({atm70_unused, atm71_unused,
		rdy70_unused, rdy71_unused, sctag7_pcx_stall_pq_d1,
		pcx_spc7_grant_px[8:0]}), 
		.tcu_scan_en_out		(tcu_scan_en_bfg_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfg_7_unused), 
		.ccx_aclk_out			(ccx_aclk_bfg_7_unused), 
		.ccx_bclk_out			(ccx_bclk_bfg_7_unused), 
		.pcx_spc_grant_pa		({4'b0, sctag7_pcx_stall_pq_buf,
		pcx_spc7_grant_a_0[8:0]}), 
		.scan_in			(bfg7_scanin), 
		.scan_out			(bfg7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_b), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_b), 
		.ccx_aclk			(ccx_aclk_bfd_b), 
		.ccx_bclk			(ccx_bclk_bfd_b));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc0_l(
		.din				({spc0_pcx_req_pq[8:0],
		spc0_pcx_atm_pq[8:0]}), 
		.dout				({spc0_pcx_req_pq_l_0[8:0],
		spc0_pcx_atm_pq_l_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc0_r(
		.din				({spc0_pcx_req_pq[8:0],
		spc0_pcx_atm_pq[8:0]}), 
		.dout				({spc0_pcx_req_pq_r_0[8:0],
		spc0_pcx_atm_pq_r_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc1_l(
		.din				({spc1_pcx_req_pq[8:0],
		spc1_pcx_atm_pq[8:0]}), 
		.dout				({spc1_pcx_req_pq_l_0[8:0],
		spc1_pcx_atm_pq_l_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc1_r(
		.din				({spc1_pcx_req_pq[8:0],
		spc1_pcx_atm_pq[8:0]}), 
		.dout				({spc1_pcx_req_pq_r_0[8:0],
		spc1_pcx_atm_pq_r_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc2_l(
		.din				({spc2_pcx_req_pq[8:0],
		spc2_pcx_atm_pq[8:0]}), 
		.dout				({spc2_pcx_req_pq_l_0[8:0],
		spc2_pcx_atm_pq_l_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc2_r(
		.din				({spc2_pcx_req_pq[8:0],
		spc2_pcx_atm_pq[8:0]}), 
		.dout				({spc2_pcx_req_pq_r_0[8:0],
		spc2_pcx_atm_pq_r_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc3_l(
		.din				({spc3_pcx_req_pq[8:0],
		spc3_pcx_atm_pq[8:0]}), 
		.dout				({spc3_pcx_req_pq_l_0[8:0],
		spc3_pcx_atm_pq_l_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc3_r(
		.din				({spc3_pcx_req_pq[8:0],
		spc3_pcx_atm_pq[8:0]}), 
		.dout				({spc3_pcx_req_pq_r_0[8:0],
		spc3_pcx_atm_pq_r_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc4_l(
		.din				({spc4_pcx_req_pq[8:0],
		spc4_pcx_atm_pq[8:0]}), 
		.dout				({spc4_pcx_req_pq_l_0[8:0],
		spc4_pcx_atm_pq_l_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc4_r(
		.din				({spc4_pcx_req_pq[8:0],
		spc4_pcx_atm_pq[8:0]}), 
		.dout				({spc4_pcx_req_pq_r_0[8:0],
		spc4_pcx_atm_pq_r_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc5_l(
		.din				({spc5_pcx_req_pq[8:0],
		spc5_pcx_atm_pq[8:0]}), 
		.dout				({spc5_pcx_req_pq_l_0[8:0],
		spc5_pcx_atm_pq_l_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc5_r(
		.din				({spc5_pcx_req_pq[8:0],
		spc5_pcx_atm_pq[8:0]}), 
		.dout				({spc5_pcx_req_pq_r_0[8:0],
		spc5_pcx_atm_pq_r_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc6_l(
		.din				({spc6_pcx_req_pq[8:0],
		spc6_pcx_atm_pq[8:0]}), 
		.dout				({spc6_pcx_req_pq_l_0[8:0],
		spc6_pcx_atm_pq_l_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc6_r(
		.din				({spc6_pcx_req_pq[8:0],
		spc6_pcx_atm_pq[8:0]}), 
		.dout				({spc6_pcx_req_pq_r_0[8:0],
		spc6_pcx_atm_pq_r_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc7_l(
		.din				({spc7_pcx_req_pq[8:0],
		spc7_pcx_atm_pq[8:0]}), 
		.dout				({spc7_pcx_req_pq_l_0[8:0],
		spc7_pcx_atm_pq_l_0[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_none__width_18 i_bufq_spc7_r(
		.din				({spc7_pcx_req_pq[8:0],
		spc7_pcx_atm_pq[8:0]}), 
		.dout				({spc7_pcx_req_pq_r_0[8:0],
		spc7_pcx_atm_pq_r_0[8:0]}));
	buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc0_1(
		.din				(spc0_pcx_data_pa[129:0]), 
		.dout				(spc0_pcx_data_a[129:0]));
	buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc1_1(
		.din				(spc1_pcx_data_pa[129:0]), 
		.dout				(spc1_pcx_data_a[129:0]));
	buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc2_1(
		.din				(spc2_pcx_data_pa[129:0]), 
		.dout				(spc2_pcx_data_a[129:0]));
	buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc3_1(
		.din				(spc3_pcx_data_pa[129:0]), 
		.dout				(spc3_pcx_data_a[129:0]));
	buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc4_1(
		.din				(spc4_pcx_data_pa[129:0]), 
		.dout				(spc4_pcx_data_a[129:0]));
	buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc5_1(
		.din				(spc5_pcx_data_pa[129:0]), 
		.dout				(spc5_pcx_data_a[129:0]));
	buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc6_1(
		.din				(spc6_pcx_data_pa[129:0]), 
		.dout				(spc6_pcx_data_a[129:0]));
	buff_macro__dbuff_40x__rep_1__stack_130c__width_130 i_bufd_spc7_1(
		.din				(spc7_pcx_data_pa[129:0]), 
		.dout				(spc7_pcx_data_a[129:0]));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_dpa_t(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_dpa_t,
		ccx_bclk_dpa_t, tcu_pce_ov_dpa_t, tcu_scan_en_dpa_t}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_bfd_t(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_bfd_t,
		ccx_bclk_bfd_t, tcu_pce_ov_bfd_t, tcu_scan_en_bfd_t}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_dpa_b(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_dpa_b,
		ccx_bclk_dpa_b, tcu_pce_ov_dpa_b, tcu_scan_en_dpa_b}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_bfd_b(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_bfd_b,
		ccx_bclk_bfd_b, tcu_pce_ov_bfd_b, tcu_scan_en_bfd_b}));
	pcx_dpa pcx_dpa(
		.pcx_io_data_x_			(pcx_fpio_data_x_l[129:0]), 
		.pcx_scache0_data_x_		(pcx_scache0_data_x_l[129:0]), 
		.pcx_scache1_data_x_		(pcx_scache1_data_x_l[129:0]), 
		.pcx_scache2_data_x_		(pcx_scache2_data_x_l[129:0]), 
		.pcx_scache3_data_x_		(pcx_scache3_data_x_l[129:0]), 
		.pcx_scache4_data_x_		(pcx_scache4_data_x_l[129:0]), 
		.pcx_scache5_data_x_		(pcx_scache5_data_x_l[129:0]), 
		.pcx_scache6_data_x_		(pcx_scache6_data_x_l[129:0]), 
		.pcx_scache7_data_x_		(pcx_scache7_data_x_l[129:0]), 
		.arb0_grant_l_a			(arb0_grant_l_a[7:0]), 
		.arb0_q0_holdbar_l_a		(arb0_q0_holdbar_l_a[7:0]), 
		.arb0_qsel0_l_a			(arb0_qsel0_l_a[7:0]), 
		.arb0_qsel1_l_a			(arb0_qsel1_l_a[7:0]), 
		.arb0_shift_l_a			(arb0_shift_l_a[7:0]), 
		.arb1_grant_l_a			(arb1_grant_l_a[7:0]), 
		.arb1_q0_holdbar_l_a		(arb1_q0_holdbar_l_a[7:0]), 
		.arb1_qsel0_l_a			(arb1_qsel0_l_a[7:0]), 
		.arb1_qsel1_l_a			(arb1_qsel1_l_a[7:0]), 
		.arb1_shift_l_a			(arb1_shift_l_a[7:0]), 
		.arb2_grant_l_a			(arb2_grant_l_a[7:0]), 
		.arb2_q0_holdbar_l_a		(arb2_q0_holdbar_l_a[7:0]), 
		.arb2_qsel0_l_a			(arb2_qsel0_l_a[7:0]), 
		.arb2_qsel1_l_a			(arb2_qsel1_l_a[7:0]), 
		.arb2_shift_l_a			(arb2_shift_l_a[7:0]), 
		.arb3_grant_l_a			(arb3_grant_l_a[7:0]), 
		.arb3_q0_holdbar_l_a		(arb3_q0_holdbar_l_a[7:0]), 
		.arb3_qsel0_l_a			(arb3_qsel0_l_a[7:0]), 
		.arb3_qsel1_l_a			(arb3_qsel1_l_a[7:0]), 
		.arb3_shift_l_a			(arb3_shift_l_a[7:0]), 
		.arb4_grant_l_a			(arb4_grant_l_a[7:0]), 
		.arb4_q0_holdbar_l_a		(arb4_q0_holdbar_l_a[7:0]), 
		.arb4_qsel0_l_a			(arb4_qsel0_l_a[7:0]), 
		.arb4_qsel1_l_a			(arb4_qsel1_l_a[7:0]), 
		.arb4_shift_l_a			(arb4_shift_l_a[7:0]), 
		.arb5_grant_l_a			(arb5_grant_l_a[7:0]), 
		.arb5_q0_holdbar_l_a		(arb5_q0_holdbar_l_a[7:0]), 
		.arb5_qsel0_l_a			(arb5_qsel0_l_a[7:0]), 
		.arb5_qsel1_l_a			(arb5_qsel1_l_a[7:0]), 
		.arb5_shift_l_a			(arb5_shift_l_a[7:0]), 
		.arb6_grant_l_a			(arb6_grant_l_a[7:0]), 
		.arb6_q0_holdbar_l_a		(arb6_q0_holdbar_l_a[7:0]), 
		.arb6_qsel0_l_a			(arb6_qsel0_l_a[7:0]), 
		.arb6_qsel1_l_a			(arb6_qsel1_l_a[7:0]), 
		.arb6_shift_l_a			(arb6_shift_l_a[7:0]), 
		.arb7_grant_l_a			(arb7_grant_l_a[7:0]), 
		.arb7_q0_holdbar_l_a		(arb7_q0_holdbar_l_a[7:0]), 
		.arb7_qsel0_l_a			(arb7_qsel0_l_a[7:0]), 
		.arb7_qsel1_l_a			(arb7_qsel1_l_a[7:0]), 
		.arb7_shift_l_a			(arb7_shift_l_a[7:0]), 
		.arb8_grant_l_a			(arb8_grant_l_a[7:0]), 
		.arb8_q0_holdbar_l_a		(arb8_q0_holdbar_l_a[7:0]), 
		.arb8_qsel0_l_a			(arb8_qsel0_l_a[7:0]), 
		.arb8_qsel1_l_a			(arb8_qsel1_l_a[7:0]), 
		.arb8_shift_l_a			(arb8_shift_l_a[7:0]), 
		.arb0_grant_r_a			(arb0_grant_r_a[7:0]), 
		.arb0_q0_holdbar_r_a		(arb0_q0_holdbar_r_a[7:0]), 
		.arb0_qsel0_r_a			(arb0_qsel0_r_a[7:0]), 
		.arb0_qsel1_r_a			(arb0_qsel1_r_a[7:0]), 
		.arb0_shift_r_a			(arb0_shift_r_a[7:0]), 
		.arb1_grant_r_a			(arb1_grant_r_a[7:0]), 
		.arb1_q0_holdbar_r_a		(arb1_q0_holdbar_r_a[7:0]), 
		.arb1_qsel0_r_a			(arb1_qsel0_r_a[7:0]), 
		.arb1_qsel1_r_a			(arb1_qsel1_r_a[7:0]), 
		.arb1_shift_r_a			(arb1_shift_r_a[7:0]), 
		.arb2_grant_r_a			(arb2_grant_r_a[7:0]), 
		.arb2_q0_holdbar_r_a		(arb2_q0_holdbar_r_a[7:0]), 
		.arb2_qsel0_r_a			(arb2_qsel0_r_a[7:0]), 
		.arb2_qsel1_r_a			(arb2_qsel1_r_a[7:0]), 
		.arb2_shift_r_a			(arb2_shift_r_a[7:0]), 
		.arb3_grant_r_a			(arb3_grant_r_a[7:0]), 
		.arb3_q0_holdbar_r_a		(arb3_q0_holdbar_r_a[7:0]), 
		.arb3_qsel0_r_a			(arb3_qsel0_r_a[7:0]), 
		.arb3_qsel1_r_a			(arb3_qsel1_r_a[7:0]), 
		.arb3_shift_r_a			(arb3_shift_r_a[7:0]), 
		.arb4_grant_r_a			(arb4_grant_r_a[7:0]), 
		.arb4_q0_holdbar_r_a		(arb4_q0_holdbar_r_a[7:0]), 
		.arb4_qsel0_r_a			(arb4_qsel0_r_a[7:0]), 
		.arb4_qsel1_r_a			(arb4_qsel1_r_a[7:0]), 
		.arb4_shift_r_a			(arb4_shift_r_a[7:0]), 
		.arb5_grant_r_a			(arb5_grant_r_a[7:0]), 
		.arb5_q0_holdbar_r_a		(arb5_q0_holdbar_r_a[7:0]), 
		.arb5_qsel0_r_a			(arb5_qsel0_r_a[7:0]), 
		.arb5_qsel1_r_a			(arb5_qsel1_r_a[7:0]), 
		.arb5_shift_r_a			(arb5_shift_r_a[7:0]), 
		.arb6_grant_r_a			(arb6_grant_r_a[7:0]), 
		.arb6_q0_holdbar_r_a		(arb6_q0_holdbar_r_a[7:0]), 
		.arb6_qsel0_r_a			(arb6_qsel0_r_a[7:0]), 
		.arb6_qsel1_r_a			(arb6_qsel1_r_a[7:0]), 
		.arb6_shift_r_a			(arb6_shift_r_a[7:0]), 
		.arb7_grant_r_a			(arb7_grant_r_a[7:0]), 
		.arb7_q0_holdbar_r_a		(arb7_q0_holdbar_r_a[7:0]), 
		.arb7_qsel0_r_a			(arb7_qsel0_r_a[7:0]), 
		.arb7_qsel1_r_a			(arb7_qsel1_r_a[7:0]), 
		.arb7_shift_r_a			(arb7_shift_r_a[7:0]), 
		.arb8_grant_r_a			(arb8_grant_r_a[7:0]), 
		.arb8_q0_holdbar_r_a		(arb8_q0_holdbar_r_a[7:0]), 
		.arb8_qsel0_r_a			(arb8_qsel0_r_a[7:0]), 
		.arb8_qsel1_r_a			(arb8_qsel1_r_a[7:0]), 
		.arb8_shift_r_a			(arb8_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dpa_scanin), 
		.scan_out			(pcx_dpa_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en_t			(tcu_scan_en_dpa_t), 
		.tcu_pce_ov_t			(tcu_pce_ov_dpa_t), 
		.ccx_aclk_t			(ccx_aclk_dpa_t), 
		.ccx_bclk_t			(ccx_bclk_dpa_t), 
		.tcu_scan_en_b			(tcu_scan_en_dpa_b), 
		.tcu_pce_ov_b			(tcu_pce_ov_dpa_b), 
		.ccx_aclk_b			(ccx_aclk_dpa_b), 
		.ccx_bclk_b			(ccx_bclk_dpa_b));
	pcx_bfd_dp bfd_io(
		.pcx_sctag_data_px2		(pcx_fpio_data_px2_0[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_lt), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_lt), 
		.ccx_aclk_out			(ccx_aclk_bfd_lt), 
		.ccx_bclk_out			(ccx_bclk_bfd_lt), 
		.pcx_scache_data_px_		(pcx_fpio_data_x_l[129:0]), 
		.scan_in			(bfd_io_scanin), 
		.scan_out			(bfd_io_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_0), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_0), 
		.ccx_aclk			(ccx_aclk_bfd_0), 
		.ccx_bclk			(ccx_bclk_bfd_0));
	pcx_bfd_dp bfd0(
		.pcx_sctag_data_px2		
		(pcx_sctag0_data_px2_prebuf[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_0), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_0), 
		.ccx_aclk_out			(ccx_aclk_bfd_0), 
		.ccx_bclk_out			(ccx_bclk_bfd_0), 
		.pcx_scache_data_px_		(pcx_scache0_data_x_l[129:0]), 
		.scan_in			(bfd0_scanin), 
		.scan_out			(bfd0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_1), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_1), 
		.ccx_aclk			(ccx_aclk_bfd_1), 
		.ccx_bclk			(ccx_bclk_bfd_1));
	pcx_ob1_dp ob_0(
		.pcx_sctag_data_px2		(pcx_sctag0_data_px2[129:0]), 
		.pcx_sctag_data_px2_prebuf	
		(pcx_sctag0_data_px2_prebuf[129:0]));
	pcx_bfd_dp bfd1(
		.pcx_sctag_data_px2		
		(pcx_sctag1_data_px2_prebuf[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_1), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_1), 
		.ccx_aclk_out			(ccx_aclk_bfd_1), 
		.ccx_bclk_out			(ccx_bclk_bfd_1), 
		.pcx_scache_data_px_		(pcx_scache1_data_x_l[129:0]), 
		.scan_in			(bfd1_scanin), 
		.scan_out			(bfd1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_t), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_t), 
		.ccx_aclk			(ccx_aclk_bfd_t), 
		.ccx_bclk			(ccx_bclk_bfd_t));
	pcx_ob1_dp ob_1(
		.pcx_sctag_data_px2		(pcx_sctag1_data_px2[129:0]), 
		.pcx_sctag_data_px2_prebuf	
		(pcx_sctag1_data_px2_prebuf[129:0]));
	pcx_bfd_dp bfd2(
		.pcx_sctag_data_px2		
		(pcx_sctag2_data_px2_prebuf[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_lb), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_lb), 
		.ccx_aclk_out			(ccx_aclk_bfd_lb), 
		.ccx_bclk_out			(ccx_bclk_bfd_lb), 
		.pcx_scache_data_px_		(pcx_scache2_data_x_l[129:0]), 
		.scan_in			(bfd2_scanin), 
		.scan_out			(bfd2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_3), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_3), 
		.ccx_aclk			(ccx_aclk_bfd_3), 
		.ccx_bclk			(ccx_bclk_bfd_3));
	pcx_ob1_dp ob_2(
		.pcx_sctag_data_px2		(pcx_sctag2_data_px2[129:0]), 
		.pcx_sctag_data_px2_prebuf	
		(pcx_sctag2_data_px2_prebuf[129:0]));
	pcx_bfd_dp bfd3(
		.pcx_sctag_data_px2		
		(pcx_sctag3_data_px2_prebuf[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_3), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_3), 
		.ccx_aclk_out			(ccx_aclk_bfd_3), 
		.ccx_bclk_out			(ccx_bclk_bfd_3), 
		.pcx_scache_data_px_		(pcx_scache3_data_x_l[129:0]), 
		.scan_in			(bfd3_scanin), 
		.scan_out			(bfd3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_b), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_b), 
		.ccx_aclk			(ccx_aclk_bfd_b), 
		.ccx_bclk			(ccx_bclk_bfd_b));
	pcx_ob1_dp ob_3(
		.pcx_sctag_data_px2		(pcx_sctag3_data_px2[129:0]), 
		.pcx_sctag_data_px2_prebuf	
		(pcx_sctag3_data_px2_prebuf[129:0]));
	pcx_bfd_dp bfd4(
		.pcx_sctag_data_px2		
		(pcx_sctag4_data_px2_prebuf[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_rt), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_rt), 
		.ccx_aclk_out			(ccx_aclk_bfd_rt), 
		.ccx_bclk_out			(ccx_bclk_bfd_rt), 
		.pcx_scache_data_px_		(pcx_scache4_data_x_l[129:0]), 
		.scan_in			(bfd4_scanin), 
		.scan_out			(bfd4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_5), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_5), 
		.ccx_aclk			(ccx_aclk_bfd_5), 
		.ccx_bclk			(ccx_bclk_bfd_5));
	pcx_ob1_dp ob_4(
		.pcx_sctag_data_px2		(pcx_sctag4_data_px2[129:0]), 
		.pcx_sctag_data_px2_prebuf	
		(pcx_sctag4_data_px2_prebuf[129:0]));
	pcx_bfd_dp bfd5(
		.pcx_sctag_data_px2		
		(pcx_sctag5_data_px2_prebuf[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_5), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_5), 
		.ccx_aclk_out			(ccx_aclk_bfd_5), 
		.ccx_bclk_out			(ccx_bclk_bfd_5), 
		.pcx_scache_data_px_		(pcx_scache5_data_x_l[129:0]), 
		.scan_in			(bfd5_scanin), 
		.scan_out			(bfd5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_t), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_t), 
		.ccx_aclk			(ccx_aclk_bfd_t), 
		.ccx_bclk			(ccx_bclk_bfd_t));
	pcx_ob1_dp ob_5(
		.pcx_sctag_data_px2		(pcx_sctag5_data_px2[129:0]), 
		.pcx_sctag_data_px2_prebuf	
		(pcx_sctag5_data_px2_prebuf[129:0]));
	pcx_bfd_dp bfd6(
		.pcx_sctag_data_px2		
		(pcx_sctag6_data_px2_prebuf[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_rb), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_rb), 
		.ccx_aclk_out			(ccx_aclk_bfd_rb), 
		.ccx_bclk_out			(ccx_bclk_bfd_rb), 
		.pcx_scache_data_px_		(pcx_scache6_data_x_l[129:0]), 
		.scan_in			(bfd6_scanin), 
		.scan_out			(bfd6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_7), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_7), 
		.ccx_aclk			(ccx_aclk_bfd_7), 
		.ccx_bclk			(ccx_bclk_bfd_7));
	pcx_ob1_dp ob_6(
		.pcx_sctag_data_px2		(pcx_sctag6_data_px2[129:0]), 
		.pcx_sctag_data_px2_prebuf	
		(pcx_sctag6_data_px2_prebuf[129:0]));
	pcx_bfd_dp bfd7(
		.pcx_sctag_data_px2		
		(pcx_sctag7_data_px2_prebuf[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_bfd_7), 
		.tcu_pce_ov_out			(tcu_pce_ov_bfd_7), 
		.ccx_aclk_out			(ccx_aclk_bfd_7), 
		.ccx_bclk_out			(ccx_bclk_bfd_7), 
		.pcx_scache_data_px_		(pcx_scache7_data_x_l[129:0]), 
		.scan_in			(bfd7_scanin), 
		.scan_out			(bfd7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_bfd_b), 
		.tcu_pce_ov			(tcu_pce_ov_bfd_b), 
		.ccx_aclk			(ccx_aclk_bfd_b), 
		.ccx_bclk			(ccx_bclk_bfd_b));
	pcx_ob1_dp ob_7(
		.pcx_sctag_data_px2		(pcx_sctag7_data_px2[129:0]), 
		.pcx_sctag_data_px2_prebuf	
		(pcx_sctag7_data_px2_prebuf[129:0]));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc0(
		.din				({sctag0_pcx_stall_pq_d1,
		spc0_pcx_req_pq_l_0[8:0], spc0_pcx_atm_pq_l_0[8:0]}), 
		.dout				({sctag0_pcx_stall_lq_d1,
		spc0_pcx_req_lq[8:0], spc0_pcx_atm_lq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc1(
		.din				({sctag1_pcx_stall_pq_d1,
		spc1_pcx_req_pq_l_0[8:0], spc1_pcx_atm_pq_l_0[8:0]}), 
		.dout				({sctag1_pcx_stall_lq_d1,
		spc1_pcx_req_lq[8:0], spc1_pcx_atm_lq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_20 i_bufq_l_spc2(
		.din				({io_pcx_stall_pq_d1,
		sctag2_pcx_stall_pq_d1, spc2_pcx_req_pq_l_0[8:0],
		spc2_pcx_atm_pq_l_0[8:0]}), 
		.dout				({io_pcx_stall_lq_d1,
		sctag2_pcx_stall_lq_d1, spc2_pcx_req_lq[8:0],
		spc2_pcx_atm_lq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc3(
		.din				({sctag3_pcx_stall_pq_d1,
		spc3_pcx_req_pq_l_0[8:0], spc3_pcx_atm_pq_l_0[8:0]}), 
		.dout				({sctag3_pcx_stall_lq_d1,
		spc3_pcx_req_lq[8:0], spc3_pcx_atm_lq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc4(
		.din				({sctag4_pcx_stall_pq_d1,
		spc4_pcx_req_pq_l_0[8:0], spc4_pcx_atm_pq_l_0[8:0]}), 
		.dout				({sctag4_pcx_stall_lq_d1,
		spc4_pcx_req_lq[8:0], spc4_pcx_atm_lq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc5(
		.din				({sctag5_pcx_stall_pq_d1,
		spc5_pcx_req_pq_l_0[8:0], spc5_pcx_atm_pq_l_0[8:0]}), 
		.dout				({sctag5_pcx_stall_lq_d1,
		spc5_pcx_req_lq[8:0], spc5_pcx_atm_lq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc6(
		.din				({sctag6_pcx_stall_pq_d1,
		spc6_pcx_req_pq_l_0[8:0], spc6_pcx_atm_pq_l_0[8:0]}), 
		.dout				({sctag6_pcx_stall_lq_d1,
		spc6_pcx_req_lq[8:0], spc6_pcx_atm_lq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_l_spc7(
		.din				({sctag7_pcx_stall_pq_d1,
		spc7_pcx_req_pq_l_0[8:0], spc7_pcx_atm_pq_l_0[8:0]}), 
		.dout				({sctag7_pcx_stall_lq_d1,
		spc7_pcx_req_lq[8:0], spc7_pcx_atm_lq[8:0]}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_lt(
		.din				({ccx_aclk_bfd_lt,
		ccx_bclk_bfd_lt, tcu_pce_ov_bfd_lt, tcu_scan_en_bfd_lt}), 
		.dout				({ccx_aclk_arb_lt,
		ccx_bclk_arb_lt, tcu_pce_ov_arb_lt, tcu_scan_en_arb_lt}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_lb(
		.din				({ccx_aclk_bfd_lb,
		ccx_bclk_bfd_lb, tcu_pce_ov_bfd_lb, tcu_scan_en_bfd_lb}), 
		.dout				({ccx_aclk_arb_lb,
		ccx_bclk_arb_lb, tcu_pce_ov_arb_lb, tcu_scan_en_arb_lb}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_rt(
		.din				({ccx_aclk_bfd_rt,
		ccx_bclk_bfd_rt, tcu_pce_ov_bfd_rt, tcu_scan_en_bfd_rt}), 
		.dout				({ccx_aclk_arb_rt,
		ccx_bclk_arb_rt, tcu_pce_ov_arb_rt, tcu_scan_en_arb_rt}));
	buff_macro__dbuff_32x__rep_1__stack_none__width_4 buf_hfn_arb_rb(
		.din				({ccx_aclk_bfd_rb,
		ccx_bclk_bfd_rb, tcu_pce_ov_bfd_rb, tcu_scan_en_bfd_rb}), 
		.dout				({ccx_aclk_arb_rb,
		ccx_bclk_arb_rb, tcu_pce_ov_arb_rb, tcu_scan_en_arb_rb}));
	ccx_arb pcx_arbl0(
		.arb_grant_a			(arb0_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb0_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb0_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb0_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb0_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[0]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[0]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[0]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[0]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[0]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[0]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[0]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[0]), 
		.arb_src8_grant_a		(arb0_src8_grant_l_unused), 
		.ccx_dest_atom_a		(pcx_sctag0_atm_a), 
		.ccx_dest_data_rdy_a		(pcx_sctag0_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[0]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[0]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[0]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[0]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[0]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[0]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[0]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[0]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[0]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[0]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[0]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[0]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[0]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[0]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[0]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[0]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag0_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl0_scanin), 
		.scan_out			(pcx_arbl0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	ccx_arb pcx_arbl1(
		.arb_grant_a			(arb1_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb1_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb1_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb1_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb1_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[1]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[1]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[1]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[1]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[1]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[1]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[1]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[1]), 
		.arb_src8_grant_a		(arb1_src8_grant_l_unused), 
		.ccx_dest_atom_a		(pcx_sctag1_atm_a), 
		.ccx_dest_data_rdy_a		(pcx_sctag1_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[1]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[1]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[1]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[1]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[1]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[1]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[1]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[1]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[1]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[1]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[1]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[1]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[1]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[1]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[1]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[1]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag1_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl1_scanin), 
		.scan_out			(pcx_arbl1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	ccx_arb pcx_arbl2(
		.arb_grant_a			(arb2_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb2_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb2_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb2_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb2_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[2]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[2]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[2]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[2]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[2]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[2]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[2]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[2]), 
		.arb_src8_grant_a		(arb2_src8_grant_l_unused), 
		.ccx_dest_atom_a		(pcx_sctag2_atm_a), 
		.ccx_dest_data_rdy_a		(pcx_sctag2_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[2]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[2]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[2]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[2]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[2]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[2]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[2]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[2]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[2]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[2]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[2]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[2]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[2]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[2]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[2]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[2]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag2_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl2_scanin), 
		.scan_out			(pcx_arbl2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lb), 
		.ccx_aclk			(ccx_aclk_arb_lb), 
		.ccx_bclk			(ccx_bclk_arb_lb));
	ccx_arb pcx_arbl3(
		.arb_grant_a			(arb3_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb3_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb3_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb3_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb3_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[3]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[3]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[3]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[3]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[3]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[3]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[3]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[3]), 
		.arb_src8_grant_a		(arb3_src8_grant_l_unused), 
		.ccx_dest_atom_a		(pcx_sctag3_atm_a), 
		.ccx_dest_data_rdy_a		(pcx_sctag3_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[3]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[3]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[3]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[3]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[3]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[3]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[3]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[3]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[3]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[3]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[3]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[3]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[3]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[3]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[3]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[3]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag3_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl3_scanin), 
		.scan_out			(pcx_arbl3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lb), 
		.ccx_aclk			(ccx_aclk_arb_lb), 
		.ccx_bclk			(ccx_bclk_arb_lb));
	ccx_arb pcx_arbl4(
		.arb_grant_a			(arb4_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb4_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb4_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb4_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb4_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[4]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[4]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[4]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[4]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[4]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[4]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[4]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[4]), 
		.arb_src8_grant_a		(arb4_src8_grant_l_unused), 
		.ccx_dest_atom_a		(pcx_sctag4_atm_a_unused), 
		.ccx_dest_data_rdy_a		(pcx_sctag4_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[4]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[4]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[4]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[4]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[4]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[4]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[4]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[4]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[4]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[4]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[4]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[4]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[4]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[4]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[4]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[4]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag4_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl4_scanin), 
		.scan_out			(pcx_arbl4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	ccx_arb pcx_arbl5(
		.arb_grant_a			(arb5_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb5_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb5_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb5_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb5_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[5]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[5]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[5]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[5]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[5]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[5]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[5]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[5]), 
		.arb_src8_grant_a		(arb5_src8_grant_l_unused), 
		.ccx_dest_atom_a		(pcx_sctag5_atm_a_unused), 
		.ccx_dest_data_rdy_a		(pcx_sctag5_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[5]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[5]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[5]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[5]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[5]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[5]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[5]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[5]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[5]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[5]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[5]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[5]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[5]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[5]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[5]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[5]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag5_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl5_scanin), 
		.scan_out			(pcx_arbl5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	ccx_arb pcx_arbl6(
		.arb_grant_a			(arb6_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb6_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb6_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb6_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb6_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[6]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[6]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[6]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[6]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[6]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[6]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[6]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[6]), 
		.arb_src8_grant_a		(arb6_src8_grant_l_unused), 
		.ccx_dest_atom_a		(pcx_sctag6_atm_a_unused), 
		.ccx_dest_data_rdy_a		(pcx_sctag6_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[6]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[6]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[6]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[6]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[6]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[6]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[6]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[6]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[6]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[6]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[6]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[6]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[6]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[6]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[6]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[6]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag6_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl6_scanin), 
		.scan_out			(pcx_arbl6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lb), 
		.ccx_aclk			(ccx_aclk_arb_lb), 
		.ccx_bclk			(ccx_bclk_arb_lb));
	ccx_arb pcx_arbl7(
		.arb_grant_a			(arb7_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb7_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb7_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb7_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb7_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[7]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[7]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[7]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[7]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[7]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[7]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[7]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[7]), 
		.arb_src8_grant_a		(arb7_src8_grant_l_unused), 
		.ccx_dest_atom_a		(pcx_sctag7_atm_a_unused), 
		.ccx_dest_data_rdy_a		(pcx_sctag7_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[7]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[7]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[7]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[7]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[7]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[7]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[7]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[7]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[7]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[7]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[7]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[7]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[7]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[7]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[7]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[7]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag7_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl7_scanin), 
		.scan_out			(pcx_arbl7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lb), 
		.ccx_aclk			(ccx_aclk_arb_lb), 
		.ccx_bclk			(ccx_bclk_arb_lb));
	ccx_arb pcx_arbl8(
		.arb_grant_a			(arb8_grant_l_a[8:0]), 
		.arb_q0_holdbar_a		(arb8_q0_holdbar_l_a[8:0]), 
		.arb_qsel0_a			(arb8_qsel0_l_a[8:0]), 
		.arb_qsel1_a			(arb8_qsel1_l_a[8:0]), 
		.arb_shift_a			(arb8_shift_l_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a[8]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a[8]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a[8]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a[8]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a_unused[8]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a_unused[8]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a_unused[8]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a_unused[8]), 
		.arb_src8_grant_a		(arb8_src8_grant_l_unused), 
		.ccx_dest_atom_a		(arb8_dest_atom_l_unused), 
		.ccx_dest_data_rdy_a		(pcx_fpio_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_lq[8]), 
		.src0_arb_req_q			(spc0_pcx_req_lq[8]), 
		.src1_arb_atom_q		(spc1_pcx_atm_lq[8]), 
		.src1_arb_req_q			(spc1_pcx_req_lq[8]), 
		.src2_arb_atom_q		(spc2_pcx_atm_lq[8]), 
		.src2_arb_req_q			(spc2_pcx_req_lq[8]), 
		.src3_arb_atom_q		(spc3_pcx_atm_lq[8]), 
		.src3_arb_req_q			(spc3_pcx_req_lq[8]), 
		.src4_arb_atom_q		(spc4_pcx_atm_lq[8]), 
		.src4_arb_req_q			(spc4_pcx_req_lq[8]), 
		.src5_arb_atom_q		(spc5_pcx_atm_lq[8]), 
		.src5_arb_req_q			(spc5_pcx_req_lq[8]), 
		.src6_arb_atom_q		(spc6_pcx_atm_lq[8]), 
		.src6_arb_req_q			(spc6_pcx_req_lq[8]), 
		.src7_arb_atom_q		(spc7_pcx_atm_lq[8]), 
		.src7_arb_req_q			(spc7_pcx_req_lq[8]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(io_pcx_stall_lq_d1), 
		.scan_in			(pcx_arbl8_scanin), 
		.scan_out			(pcx_arbl8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_lt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_lt), 
		.ccx_aclk			(ccx_aclk_arb_lt), 
		.ccx_bclk			(ccx_bclk_arb_lt));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc0(
		.din				({sctag0_pcx_stall_pq_d1,
		spc0_pcx_req_pq_r_0[8:0], spc0_pcx_atm_pq_r_0[8:0]}), 
		.dout				({sctag0_pcx_stall_rq_d1,
		spc0_pcx_req_rq[8:0], spc0_pcx_atm_rq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc1(
		.din				({sctag1_pcx_stall_pq_d1,
		spc1_pcx_req_pq_r_0[8:0], spc1_pcx_atm_pq_r_0[8:0]}), 
		.dout				({sctag1_pcx_stall_rq_d1,
		spc1_pcx_req_rq[8:0], spc1_pcx_atm_rq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_20 i_bufq_r_spc2(
		.din				({io_pcx_stall_pq_d1,
		sctag2_pcx_stall_pq_d1, spc2_pcx_req_pq_r_0[8:0],
		spc2_pcx_atm_pq_r_0[8:0]}), 
		.dout				({io_pcx_stall_rq_d1,
		sctag2_pcx_stall_rq_d1, spc2_pcx_req_rq[8:0],
		spc2_pcx_atm_rq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc3(
		.din				({sctag3_pcx_stall_pq_d1,
		spc3_pcx_req_pq_r_0[8:0], spc3_pcx_atm_pq_r_0[8:0]}), 
		.dout				({sctag3_pcx_stall_rq_d1,
		spc3_pcx_req_rq[8:0], spc3_pcx_atm_rq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc4(
		.din				({sctag4_pcx_stall_pq_d1,
		spc4_pcx_req_pq_r_0[8:0], spc4_pcx_atm_pq_r_0[8:0]}), 
		.dout				({sctag4_pcx_stall_rq_d1,
		spc4_pcx_req_rq[8:0], spc4_pcx_atm_rq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc5(
		.din				({sctag5_pcx_stall_pq_d1,
		spc5_pcx_req_pq_r_0[8:0], spc5_pcx_atm_pq_r_0[8:0]}), 
		.dout				({sctag5_pcx_stall_rq_d1,
		spc5_pcx_req_rq[8:0], spc5_pcx_atm_rq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc6(
		.din				({sctag6_pcx_stall_pq_d1,
		spc6_pcx_req_pq_r_0[8:0], spc6_pcx_atm_pq_r_0[8:0]}), 
		.dout				({sctag6_pcx_stall_rq_d1,
		spc6_pcx_req_rq[8:0], spc6_pcx_atm_rq[8:0]}));
	buff_macro__dbuff_48x__rep_1__stack_20r__width_19 i_bufq_r_spc7(
		.din				({sctag7_pcx_stall_pq_d1,
		spc7_pcx_req_pq_r_0[8:0], spc7_pcx_atm_pq_r_0[8:0]}), 
		.dout				({sctag7_pcx_stall_rq_d1,
		spc7_pcx_req_rq[8:0], spc7_pcx_atm_rq[8:0]}));
	ccx_arb pcx_arbr0(
		.arb_grant_a			(arb0_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb0_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb0_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb0_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb0_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[0]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[0]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[0]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[0]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[0]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[0]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[0]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[0]), 
		.arb_src8_grant_a		(arb0_src8_grant_r_unused), 
		.ccx_dest_atom_a		(pcx_sctag0_atm_a_unused), 
		.ccx_dest_data_rdy_a		(pcx_sctag0_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[0]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[0]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[0]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[0]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[0]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[0]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[0]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[0]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[0]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[0]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[0]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[0]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[0]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[0]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[0]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[0]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag0_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr0_scanin), 
		.scan_out			(pcx_arbr0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
	ccx_arb pcx_arbr1(
		.arb_grant_a			(arb1_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb1_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb1_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb1_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb1_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[1]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[1]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[1]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[1]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[1]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[1]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[1]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[1]), 
		.arb_src8_grant_a		(arb1_src8_grant_r_unused), 
		.ccx_dest_atom_a		(pcx_sctag1_atm_a_unused), 
		.ccx_dest_data_rdy_a		(pcx_sctag1_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[1]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[1]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[1]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[1]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[1]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[1]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[1]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[1]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[1]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[1]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[1]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[1]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[1]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[1]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[1]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[1]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag1_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr1_scanin), 
		.scan_out			(pcx_arbr1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
	ccx_arb pcx_arbr2(
		.arb_grant_a			(arb2_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb2_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb2_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb2_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb2_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[2]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[2]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[2]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[2]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[2]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[2]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[2]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[2]), 
		.arb_src8_grant_a		(arb2_src8_grant_r_unused), 
		.ccx_dest_atom_a		(pcx_sctag2_atm_a_unused), 
		.ccx_dest_data_rdy_a		(pcx_sctag2_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[2]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[2]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[2]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[2]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[2]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[2]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[2]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[2]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[2]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[2]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[2]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[2]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[2]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[2]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[2]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[2]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag2_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr2_scanin), 
		.scan_out			(pcx_arbr2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rb), 
		.ccx_aclk			(ccx_aclk_arb_rb), 
		.ccx_bclk			(ccx_bclk_arb_rb));
	ccx_arb pcx_arbr3(
		.arb_grant_a			(arb3_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb3_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb3_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb3_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb3_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[3]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[3]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[3]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[3]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[3]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[3]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[3]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[3]), 
		.arb_src8_grant_a		(arb3_src8_grant_r_unused), 
		.ccx_dest_atom_a		(pcx_sctag3_atm_a_unused), 
		.ccx_dest_data_rdy_a		(pcx_sctag3_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[3]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[3]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[3]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[3]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[3]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[3]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[3]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[3]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[3]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[3]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[3]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[3]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[3]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[3]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[3]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[3]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag3_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr3_scanin), 
		.scan_out			(pcx_arbr3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rb), 
		.ccx_aclk			(ccx_aclk_arb_rb), 
		.ccx_bclk			(ccx_bclk_arb_rb));
	ccx_arb pcx_arbr4(
		.arb_grant_a			(arb4_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb4_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb4_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb4_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb4_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[4]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[4]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[4]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[4]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[4]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[4]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[4]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[4]), 
		.arb_src8_grant_a		(arb4_src8_grant_r_unused), 
		.ccx_dest_atom_a		(pcx_sctag4_atm_a), 
		.ccx_dest_data_rdy_a		(pcx_sctag4_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[4]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[4]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[4]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[4]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[4]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[4]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[4]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[4]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[4]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[4]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[4]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[4]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[4]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[4]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[4]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[4]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag4_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr4_scanin), 
		.scan_out			(pcx_arbr4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
	ccx_arb pcx_arbr5(
		.arb_grant_a			(arb5_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb5_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb5_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb5_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb5_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[5]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[5]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[5]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[5]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[5]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[5]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[5]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[5]), 
		.arb_src8_grant_a		(arb5_src8_grant_r_unused), 
		.ccx_dest_atom_a		(pcx_sctag5_atm_a), 
		.ccx_dest_data_rdy_a		(pcx_sctag5_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[5]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[5]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[5]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[5]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[5]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[5]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[5]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[5]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[5]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[5]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[5]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[5]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[5]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[5]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[5]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[5]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag5_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr5_scanin), 
		.scan_out			(pcx_arbr5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
	ccx_arb pcx_arbr6(
		.arb_grant_a			(arb6_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb6_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb6_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb6_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb6_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[6]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[6]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[6]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[6]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[6]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[6]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[6]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[6]), 
		.arb_src8_grant_a		(arb6_src8_grant_r_unused), 
		.ccx_dest_atom_a		(pcx_sctag6_atm_a), 
		.ccx_dest_data_rdy_a		(pcx_sctag6_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[6]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[6]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[6]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[6]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[6]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[6]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[6]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[6]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[6]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[6]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[6]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[6]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[6]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[6]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[6]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[6]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag6_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr6_scanin), 
		.scan_out			(pcx_arbr6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rb), 
		.ccx_aclk			(ccx_aclk_arb_rb), 
		.ccx_bclk			(ccx_bclk_arb_rb));
	ccx_arb pcx_arbr7(
		.arb_grant_a			(arb7_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb7_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb7_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb7_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb7_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[7]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[7]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[7]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[7]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[7]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[7]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[7]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[7]), 
		.arb_src8_grant_a		(arb7_src8_grant_r_unused), 
		.ccx_dest_atom_a		(pcx_sctag7_atm_a), 
		.ccx_dest_data_rdy_a		(pcx_sctag7_data_rdy_a), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[7]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[7]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[7]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[7]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[7]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[7]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[7]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[7]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[7]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[7]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[7]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[7]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[7]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[7]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[7]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[7]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(sctag7_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr7_scanin), 
		.scan_out			(pcx_arbr7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rb), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rb), 
		.ccx_aclk			(ccx_aclk_arb_rb), 
		.ccx_bclk			(ccx_bclk_arb_rb));
	ccx_arb pcx_arbr8(
		.arb_grant_a			(arb8_grant_r_a[8:0]), 
		.arb_q0_holdbar_a		(arb8_q0_holdbar_r_a[8:0]), 
		.arb_qsel0_a			(arb8_qsel0_r_a[8:0]), 
		.arb_qsel1_a			(arb8_qsel1_r_a[8:0]), 
		.arb_shift_a			(arb8_shift_r_a[8:0]), 
		.arb_src0_grant_a		(pcx_spc0_grant_a_unused[8]), 
		.arb_src1_grant_a		(pcx_spc1_grant_a_unused[8]), 
		.arb_src2_grant_a		(pcx_spc2_grant_a_unused[8]), 
		.arb_src3_grant_a		(pcx_spc3_grant_a_unused[8]), 
		.arb_src4_grant_a		(pcx_spc4_grant_a[8]), 
		.arb_src5_grant_a		(pcx_spc5_grant_a[8]), 
		.arb_src6_grant_a		(pcx_spc6_grant_a[8]), 
		.arb_src7_grant_a		(pcx_spc7_grant_a[8]), 
		.arb_src8_grant_a		(arb8_src8_grant_r_unused), 
		.ccx_dest_atom_a		(arb8_dest_atom_r_unused), 
		.ccx_dest_data_rdy_a		(pcx_fpio_data_rdy_a_unused), 
		.src0_arb_atom_q		(spc0_pcx_atm_rq[8]), 
		.src0_arb_req_q			(spc0_pcx_req_rq[8]), 
		.src1_arb_atom_q		(spc1_pcx_atm_rq[8]), 
		.src1_arb_req_q			(spc1_pcx_req_rq[8]), 
		.src2_arb_atom_q		(spc2_pcx_atm_rq[8]), 
		.src2_arb_req_q			(spc2_pcx_req_rq[8]), 
		.src3_arb_atom_q		(spc3_pcx_atm_rq[8]), 
		.src3_arb_req_q			(spc3_pcx_req_rq[8]), 
		.src4_arb_atom_q		(spc4_pcx_atm_rq[8]), 
		.src4_arb_req_q			(spc4_pcx_req_rq[8]), 
		.src5_arb_atom_q		(spc5_pcx_atm_rq[8]), 
		.src5_arb_req_q			(spc5_pcx_req_rq[8]), 
		.src6_arb_atom_q		(spc6_pcx_atm_rq[8]), 
		.src6_arb_req_q			(spc6_pcx_req_rq[8]), 
		.src7_arb_atom_q		(spc7_pcx_atm_rq[8]), 
		.src7_arb_req_q			(spc7_pcx_req_rq[8]), 
		.src8_arb_atom_q		(1'b0), 
		.src8_arb_req_q			(1'b0), 
		.stall_q_d1			(io_pcx_stall_rq_d1), 
		.scan_in			(pcx_arbr8_scanin), 
		.scan_out			(pcx_arbr8_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_arb_rt), 
		.tcu_pce_ov			(tcu_pce_ov_arb_rt), 
		.ccx_aclk			(ccx_aclk_arb_rt), 
		.ccx_bclk			(ccx_bclk_arb_rt));
endmodule
`endcelldefine

module buff_macro__dbuff_48x__rep_1__stack_20r__width_19(din, dout);

        input   [18:0]          din;
        output  [18:0]          dout;

        buff #(19) d0_0(
                .in                             (din[18:0]),
                .out                            (dout[18:0]));
endmodule

module buff_macro__dbuff_32x__rep_1__stack_none__width_4(din, dout);

        input   [3:0]           din;
        output  [3:0]           dout;

        buff #(4) d0_0(
                .in                             (din[3:0]),
                .out                            (dout[3:0]));
endmodule
module buff_macro__dbuff_40x__rep_1__stack_130c__width_130(din, dout);

        input   [129:0]         din;
        output  [129:0]         dout;

        buff #(130) d0_0(
                .in                             (din[129:0]),
                .out                            (dout[129:0]));
endmodule


module buff_macro__dbuff_48x__rep_1__stack_none__width_18(din, dout);

        input   [17:0]          din;
        output  [17:0]          dout;

        buff #(18) d0_0(
                .in                             (din[17:0]),
                .out                            (dout[17:0]));
endmodule

module buff_macro__dbuff_16x__rep_1__stack_none__width_1(din, dout);

        input   [0:0]           din;
        output  [0:0]           dout;

        buff #(1) d0_0(
                .in                             (din[0]),
                .out                            (dout[0]));
endmodule

module buff_macro__dbuff_32x__rep_1__stack_none__width_2(din, dout);

        input   [1:0]           din;
        output  [1:0]           dout;

        buff #(2) d0_0(
                .in                             (din[1:0]),
                .out                            (dout[1:0]));
endmodule

module buff_macro__dbuff_48x__rep_1__stack_20r__width_20(din, dout);

        input   [19:0]          din;
        output  [19:0]          dout;

        buff #(20) d0_0(
                .in                             (din[19:0]),
                .out                            (dout[19:0]));
endmodule


module buff_macro__dbuff_32x__rep_1__stack_150c__width_130(din, dout);

        input   [129:0]         din;
        output  [129:0]         dout;

        buff #(130) d0_0(
                .in                             (din[129:0]),
                .out                            (dout[129:0]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_bfd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_bfd_dp (
  pcx_sctag_data_px2, 
  pcx_scache_data_px_, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire [129:0] in;
wire [129:0] in_swz;
wire i_dff_data_0_scanin;
wire i_dff_data_0_scanout;
wire [9:0] in_unused_x2;
wire [129:0] in_x2;
wire i_dff_data_1_scanin;
wire i_dff_data_1_scanout;
wire i_dff_data_2_scanin;
wire i_dff_data_2_scanout;
wire i_dff_data_3_scanin;
wire i_dff_data_3_scanout;
wire [129:0] in_px2;
wire [9:0] in_unused;
wire [129:0] out_swz;
wire scan_out_prebuf;


output [129:0] pcx_sctag_data_px2;

input [129:0] pcx_scache_data_px_;

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

// buffer the high fanout nets
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk = ccx_aclk_out;
assign soclk = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

pcx_bfd_dp_buff_macro__dbuff_8x__stack_none__width_4 buf_hfn    (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

assign in[129:0] = pcx_scache_data_px_[129:0];


assign in_swz[64:0] =     {
                           in[128],in[126],in[124],in[122],in[120],
                           in[118],in[116],in[114],in[112],in[110],in[108],in[106],in[104],in[102],in[100],
                           in[98],in[96],in[94],in[92],in[90],in[88],in[86],in[84],in[82],in[80],
                           in[78],in[76],in[74],in[72],in[70],in[68],in[66],in[64],in[62],in[60],
                           in[58],in[56],in[54],in[52],in[50],in[48],in[46],in[44],in[42],in[40],
                           in[38],in[36],in[34],in[32],in[30],in[28],in[26],in[24],in[22],in[20],
                           in[18],in[16],in[14],in[12],in[10],in[8],in[6],in[4],in[2],in[0]
                           };


assign in_swz[129:65] =   {
                           in[129],in[127],in[125],in[123],in[121],
                           in[119],in[117],in[115],in[113],in[111],in[109],in[107],in[105],in[103],in[101],
                           in[99],in[97],in[95],in[93],in[91],in[89],in[87],in[85],in[83],in[81],
                           in[79],in[77],in[75],in[73],in[71],in[69],in[67],in[65],in[63],in[61],
                           in[59],in[57],in[55],in[53],in[51],in[49],in[47],in[45],in[43],in[41],
                           in[39],in[37],in[35],in[33],in[31],in[29],in[27],in[25],in[23],in[21],
                           in[19],in[17],in[15],in[13],in[11],in[9],in[7],in[5],in[3],in[1]
                           };

  
//inv_macro i_inv_data_2 (width=40, stack=50c) (
//	.din	(pcx_scache_data_px_[129:90]),
//	.dout	(pcx_scache_data_px[129:90]),
//);
//
//inv_macro i_inv_data_1 (width=50, stack=50c) (
//	.din	(pcx_scache_data_px_[89:40]),
//	.dout	(pcx_scache_data_px[89:40]),
//);
//
//inv_macro i_inv_data_0 (width=40, stack=50c) (
//	.din	(pcx_scache_data_px_[39:0]),
//	.dout	(pcx_scache_data_px[39:0]),
//);
//
//msff_macro i_dff_data_2 (width=40, stack=50c) (
//	.scan_in(i_dff_sctag_l_scanin),
//	.scan_out(i_dff_sctag_l_scanout),
//	.clk	(l2clk),
//	.din	(pcx_scache_data_px[129:90]),
//	.dout	(pcx_sctag_data_x2[129:90]),
//	.en	(1'b1),
//);
//
//msff_macro i_dff_data_1 (width=50, stack=50c) (
//	.scan_in(i_dff_sctag_c_scanin),
//	.scan_out(i_dff_sctag_c_scanout),
//	.clk	(l2clk),
//	.din	(pcx_scache_data_px[89:40]),
//	.dout	(pcx_sctag_data_x2[89:40]),
//	.en	(1'b1),
//);
//
//msff_macro i_dff_data_0 (width=40, stack=50c) (
//	.scan_in(i_dff_sctag_r_scanin),
//	.scan_out(i_dff_sctag_r_scanout),
//	.clk	(l2clk),
//	.din	(pcx_scache_data_px[39:0]),
//	.dout	(pcx_sctag_data_x2[39:0]),
//	.en	(1'b1),
//);
//
//buff_macro i_buf_data_2 (width=40, stack=50c) (
//	.din	(pcx_sctag_data_x2[129:90]),
//	.dout	(pcx_sctag_data_px2[129:90]),
//);
//
//buff_macro i_buf_data_1 (width=50, stack=50c) (
//	.din	(pcx_sctag_data_x2[89:40]),
//	.dout	(pcx_sctag_data_px2[89:40]),
//);
//
//buff_macro i_buf_data_0 (width=40, stack=50c) (
//	.din	(pcx_sctag_data_x2[39:0]),
//	.dout	(pcx_sctag_data_px2[39:0]),
//);

//inv_macro i_inv_data_0 (width=64, stack=64c) (
//	.din	({2'b00,            in_swz[59:30],in_swz[29:0], 2'b00}),
//	.dout	({in_unused_px[3:2],in_px[59:30], in_px[29:0],  in_unused_px[1:0]}),
//);

//inv_macro i_inv_data_1 (width=64, stack=64c) (
//	.din	({2'b00,            in_swz[124:95],in_swz[94:65], 2'b00}),
//	.dout	({in_unused_px[7:6],in_px[124:95], in_px[94:65],  in_unused_px[5:4]}),
//);

//inv_macro i_inv_data_2 (width=6, stack=6l) (
//	.din	({1'b0,in_swz[64:60]}),
//	.dout	({in_unused_px[8],in_px[64:60]}),
//);

//inv_macro i_inv_data_3 (width=6, stack=6l) (
//	.din	({1'b0,in_swz[129:125]}),
//	.dout	({in_unused_px[9],in_px[129:125]}),
//);

pcx_bfd_dp_msffiz_macro__dmsffi_32x__stack_64c__width_64 i_dff_data_0    (
	.scan_in(i_dff_data_0_scanin),
	.scan_out(i_dff_data_0_scanout),
	.clk	(l2clk),
	.din	({2'b00,            in_swz[59:30], in_swz[29:0],  2'b00            }),
	.dout_l	({in_unused_x2[3:2],in_x2[59:30],  in_x2[29:0],   in_unused_x2[1:0]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

pcx_bfd_dp_msffiz_macro__dmsffi_32x__scanreverse_1__stack_64c__width_64 i_dff_data_1     (
	.scan_in(i_dff_data_1_scanin),
	.scan_out(i_dff_data_1_scanout),
	.clk	(l2clk),
	.din	({2'b00,            in_swz[124:95], in_swz[94:65],  2'b00}),
	.dout_l	({in_unused_x2[7:6],in_x2[124:95],  in_x2[94:65],   in_unused_x2[5:4]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

pcx_bfd_dp_msffiz_macro__dmsffi_32x__stack_6l__width_6 i_dff_data_2    (
	.scan_in(i_dff_data_2_scanin),
	.scan_out(i_dff_data_2_scanout),
	.clk	(l2clk),
	.din	({1'b0,           in_swz[64:60]}),
	.dout_l	({in_unused_x2[8],in_x2[64:60]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

pcx_bfd_dp_msffiz_macro__dmsffi_32x__stack_6l__width_6 i_dff_data_3    (
	.scan_in(i_dff_data_3_scanin),
	.scan_out(i_dff_data_3_scanout),
	.clk	(l2clk),
	.din	({1'b0,           in_swz[129:125]}),
	.dout_l	({in_unused_x2[9],in_x2[129:125]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

//buff_macro i_buf_data_0 (dbuff=32x, width=64, stack=64c) (
//	  .din	({in_unused_x2[3:2],in_x2[59:30], in_x2[29:0],  in_unused_x2[1:0]}),
//	  .dout	({in_unused[3:2],   in_px2[59:30],in_px2[29:0],  in_unused[1:0]}),
//);
//
//buff_macro i_buf_data_1 (dbuff=32x, width=64, stack=64c) (
//	  .din	({in_unused_x2[7:6],in_x2[124:95], in_x2[94:65],  in_unused_x2[5:4]}),
//	  .dout	({in_unused[7:6],   in_px2[124:95],in_px2[94:65], in_unused[5:4]}),
//);
//
//buff_macro i_buf_data_2 (dbuff=32x, width=6, stack=none) (
//	  .din	({in_unused_x2[8],in_x2[64:60]}),
//	  .dout	({in_unused[8],   in_px2[64:60]}),
//);
//
//buff_macro i_buf_data_3 (dbuff=32x, width=6, stack=none) (
//	  .din	({in_unused_x2[9],in_x2[129:125]}),
//	  .dout	({in_unused[9],in_px2[129:125]}),
//);

assign in_px2[129:0] = in_x2[129:0];
assign in_unused[9:0] = in_unused_x2[9:0];

assign {
        out_swz[128],out_swz[126],out_swz[124],out_swz[122],out_swz[120],
        out_swz[118],out_swz[116],out_swz[114],out_swz[112],out_swz[110],out_swz[108],out_swz[106],out_swz[104],out_swz[102],out_swz[100],
        out_swz[98],out_swz[96],out_swz[94],out_swz[92],out_swz[90],out_swz[88],out_swz[86],out_swz[84],out_swz[82],out_swz[80],
        out_swz[78],out_swz[76],out_swz[74],out_swz[72],out_swz[70],out_swz[68],out_swz[66],out_swz[64],out_swz[62],out_swz[60],
        out_swz[58],out_swz[56],out_swz[54],out_swz[52],out_swz[50],out_swz[48],out_swz[46],out_swz[44],out_swz[42],out_swz[40],
        out_swz[38],out_swz[36],out_swz[34],out_swz[32],out_swz[30],out_swz[28],out_swz[26],out_swz[24],out_swz[22],out_swz[20],
        out_swz[18],out_swz[16],out_swz[14],out_swz[12],out_swz[10],out_swz[8],out_swz[6],out_swz[4],out_swz[2],out_swz[0]
        } = in_px2[64:0];


assign  {
         out_swz[129],out_swz[127],out_swz[125],out_swz[123],out_swz[121],
         out_swz[119],out_swz[117],out_swz[115],out_swz[113],out_swz[111],out_swz[109],out_swz[107],out_swz[105],out_swz[103],out_swz[101],
         out_swz[99],out_swz[97],out_swz[95],out_swz[93],out_swz[91],out_swz[89],out_swz[87],out_swz[85],out_swz[83],out_swz[81],
         out_swz[79],out_swz[77],out_swz[75],out_swz[73],out_swz[71],out_swz[69],out_swz[67],out_swz[65],out_swz[63],out_swz[61],
         out_swz[59],out_swz[57],out_swz[55],out_swz[53],out_swz[51],out_swz[49],out_swz[47],out_swz[45],out_swz[43],out_swz[41],
         out_swz[39],out_swz[37],out_swz[35],out_swz[33],out_swz[31],out_swz[29],out_swz[27],out_swz[25],out_swz[23],out_swz[21],
         out_swz[19],out_swz[17],out_swz[15],out_swz[13],out_swz[11],out_swz[9],out_swz[7],out_swz[5],out_swz[3],out_swz[1]
         } = in_px2[129:65];


assign pcx_sctag_data_px2[129:0] = out_swz[129:0];

pcx_bfd_dp_buff_macro__dbuff_8x__stack_none__width_1 buf_scanout    (
	.din	(scan_out_prebuf),
	.dout	(scan_out)
);

// fixscan start:
assign i_dff_data_0_scanin       = scan_in                  ;
assign i_dff_data_1_scanin       = i_dff_data_0_scanout     ;
assign i_dff_data_2_scanin       = i_dff_data_1_scanout     ;
assign i_dff_data_3_scanin       = i_dff_data_2_scanout     ;
assign scan_out_prebuf           = i_dff_data_3_scanout     ;
// fixscan end:
endmodule // pcx_bfs_dp


//
//   buff macro
//
//


module pcx_bfd_dp_buff_macro__dbuff_8x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_bfd_dp_msffiz_macro__dmsffi_32x__stack_64c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout_l, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout_l;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
msffiz_dp #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q_l(dout_l[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_bfd_dp_msffiz_macro__dmsffi_32x__scanreverse_1__stack_64c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout_l, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout_l;


  output scan_out;


  wire [0:62] so;

cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
msffiz_dp #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({so[0:62],scan_in}),
.so({scan_out,so[0:62]}),
.q_l(dout_l[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_bfd_dp_msffiz_macro__dmsffi_32x__stack_6l__width_6 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout_l, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [4:0] so;

  input [5:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [5:0] dout_l;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
msffiz_dp #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q_l(dout_l[5:0])
);


endmodule


//
//   buff macro
//
//


module pcx_bfd_dp_buff_macro__dbuff_8x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module pcx_bfd_dp(pcx_sctag_data_px2, pcx_scache_data_px_, tcu_scan_en, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out, ccx_aclk_out, 
	ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[129:0]		pcx_sctag_data_px2;
	input	[129:0]		pcx_scache_data_px_;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk;
	wire			soclk;
	wire			se;
	wire	[129:0]		in;
	wire	[129:0]		in_swz;
	wire			i_dff_data_0_scanin;
	wire			i_dff_data_0_scanout;
	wire	[9:0]		in_unused_x2;
	wire	[129:0]		in_x2;
	wire			i_dff_data_1_scanin;
	wire			i_dff_data_1_scanout;
	wire			i_dff_data_2_scanin;
	wire			i_dff_data_2_scanout;
	wire			i_dff_data_3_scanin;
	wire			i_dff_data_3_scanout;
	wire	[129:0]		in_px2;
	wire	[9:0]		in_unused;
	wire	[129:0]		out_swz;
	wire			scan_out_prebuf;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk = ccx_aclk_out;
	assign soclk = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign in[129:0] = pcx_scache_data_px_[129:0];
	assign in_swz[64:0] = {in[128], in[126], in[124], in[122], in[120], 
		in[118], in[116], in[114], in[112], in[110], in[108], in[106], 
		in[104], in[102], in[100], in[98], in[96], in[94], in[92], 
		in[90], in[88], in[86], in[84], in[82], in[80], in[78], in[76], 
		in[74], in[72], in[70], in[68], in[66], in[64], in[62], in[60], 
		in[58], in[56], in[54], in[52], in[50], in[48], in[46], in[44], 
		in[42], in[40], in[38], in[36], in[34], in[32], in[30], in[28], 
		in[26], in[24], in[22], in[20], in[18], in[16], in[14], in[12], 
		in[10], in[8], in[6], in[4], in[2], in[0]};
	assign in_swz[129:65] = {in[129], in[127], in[125], in[123], in[121], 
		in[119], in[117], in[115], in[113], in[111], in[109], in[107], 
		in[105], in[103], in[101], in[99], in[97], in[95], in[93], 
		in[91], in[89], in[87], in[85], in[83], in[81], in[79], in[77], 
		in[75], in[73], in[71], in[69], in[67], in[65], in[63], in[61], 
		in[59], in[57], in[55], in[53], in[51], in[49], in[47], in[45], 
		in[43], in[41], in[39], in[37], in[35], in[33], in[31], in[29], 
		in[27], in[25], in[23], in[21], in[19], in[17], in[15], in[13], 
		in[11], in[9], in[7], in[5], in[3], in[1]};
	assign in_px2[129:0] = in_x2[129:0];
	assign in_unused[9:0] = in_unused_x2[9:0];
	assign {out_swz[128], out_swz[126], out_swz[124], out_swz[122], 
		out_swz[120], out_swz[118], out_swz[116], out_swz[114], 
		out_swz[112], out_swz[110], out_swz[108], out_swz[106], 
		out_swz[104], out_swz[102], out_swz[100], out_swz[98], 
		out_swz[96], out_swz[94], out_swz[92], out_swz[90], out_swz[88],
		out_swz[86], out_swz[84], out_swz[82], out_swz[80], out_swz[78],
		out_swz[76], out_swz[74], out_swz[72], out_swz[70], out_swz[68],
		out_swz[66], out_swz[64], out_swz[62], out_swz[60], out_swz[58],
		out_swz[56], out_swz[54], out_swz[52], out_swz[50], out_swz[48],
		out_swz[46], out_swz[44], out_swz[42], out_swz[40], out_swz[38],
		out_swz[36], out_swz[34], out_swz[32], out_swz[30], out_swz[28],
		out_swz[26], out_swz[24], out_swz[22], out_swz[20], out_swz[18],
		out_swz[16], out_swz[14], out_swz[12], out_swz[10], out_swz[8], 
		out_swz[6], out_swz[4], out_swz[2], out_swz[0]} = in_px2[64:0];
	assign {out_swz[129], out_swz[127], out_swz[125], out_swz[123], 
		out_swz[121], out_swz[119], out_swz[117], out_swz[115], 
		out_swz[113], out_swz[111], out_swz[109], out_swz[107], 
		out_swz[105], out_swz[103], out_swz[101], out_swz[99], 
		out_swz[97], out_swz[95], out_swz[93], out_swz[91], out_swz[89],
		out_swz[87], out_swz[85], out_swz[83], out_swz[81], out_swz[79],
		out_swz[77], out_swz[75], out_swz[73], out_swz[71], out_swz[69],
		out_swz[67], out_swz[65], out_swz[63], out_swz[61], out_swz[59],
		out_swz[57], out_swz[55], out_swz[53], out_swz[51], out_swz[49],
		out_swz[47], out_swz[45], out_swz[43], out_swz[41], out_swz[39],
		out_swz[37], out_swz[35], out_swz[33], out_swz[31], out_swz[29],
		out_swz[27], out_swz[25], out_swz[23], out_swz[21], out_swz[19],
		out_swz[17], out_swz[15], out_swz[13], out_swz[11], out_swz[9], 
		out_swz[7], out_swz[5], out_swz[3], out_swz[1]} = in_px2[129:65]
		;
	assign pcx_sctag_data_px2[129:0] = out_swz[129:0];
	assign i_dff_data_0_scanin = scan_in;
	assign i_dff_data_1_scanin = i_dff_data_0_scanout;
	assign i_dff_data_2_scanin = i_dff_data_1_scanout;
	assign i_dff_data_3_scanin = i_dff_data_2_scanout;
	assign scan_out_prebuf = i_dff_data_3_scanout;

	buff_macro__dbuff_8x__stack_none__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	msffiz_macro__dmsffi_32x__stack_64c__width_64 i_dff_data_0(
		.scan_in			(i_dff_data_0_scanin), 
		.scan_out			(i_dff_data_0_scanout), 
		.clk				(l2clk), 
		.din				({2'b0, in_swz[59:30],
		in_swz[29:0], 2'b0}), 
		.dout_l				({in_unused_x2[3:2],
		in_x2[59:30], in_x2[29:0], in_unused_x2[1:0]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msffiz_macro__dmsffi_32x__scanreverse_1__stack_64c__width_64 
		i_dff_data_1(
		.scan_in			(i_dff_data_1_scanin), 
		.scan_out			(i_dff_data_1_scanout), 
		.clk				(l2clk), 
		.din				({2'b0, in_swz[124:95],
		in_swz[94:65], 2'b0}), 
		.dout_l				({in_unused_x2[7:6],
		in_x2[124:95], in_x2[94:65], in_unused_x2[5:4]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msffiz_macro__dmsffi_32x__stack_6l__width_6 i_dff_data_2(
		.scan_in			(i_dff_data_2_scanin), 
		.scan_out			(i_dff_data_2_scanout), 
		.clk				(l2clk), 
		.din				({1'b0, in_swz[64:60]}), 
		.dout_l				({in_unused_x2[8],
		in_x2[64:60]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	msffiz_macro__dmsffi_32x__stack_6l__width_6 i_dff_data_3(
		.scan_in			(i_dff_data_3_scanin), 
		.scan_out			(i_dff_data_3_scanout), 
		.clk				(l2clk), 
		.din				({1'b0, in_swz[129:125]}), 
		.dout_l				({in_unused_x2[9],
		in_x2[129:125]}), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	buff_macro__dbuff_8x__stack_none__width_1 buf_scanout(
		.din				(scan_out_prebuf), 
		.dout				(scan_out));
endmodule

module msffiz_macro__dmsffi_32x__stack_6l__width_6(din, clk, en, se, scan_in,
        siclk, soclk, pce_ov, stop, dout_l, scan_out);

        input   [5:0]           din;
        input                   clk;
        input                   en;
        input                   se;
        input                   scan_in;
        input                   siclk;
        input                   soclk;
        input                   pce_ov;
        input                   stop;
        output  [5:0]           dout_l;
        output                  scan_out;

        wire                    l1clk;
        wire                    siclk_out;
        wire                    soclk_out;
        wire    [4:0]           so;

        cl_dp1_l1hdr_8x c0_0(
                .l2clk                          (clk),
                .pce                            (en),
                .aclk                           (siclk),
                .bclk                           (soclk),
                .l1clk                          (l1clk),
                .se                             (se),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out));
        msffiz_dp #(6) d0_0(
                .l1clk                          (l1clk),
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .d                              (din[5:0]),
                .si                             ({scan_in, so[4:0]}),
                .so                             ({so[4:0], scan_out}),
                .q_l                            (dout_l[5:0]));
endmodule

module msffiz_macro__dmsffi_32x__stack_64c__width_64(din, clk, en, se, scan_in,
        siclk, soclk, pce_ov, stop, dout_l, scan_out);

        input   [63:0]          din;
        input                   clk;
        input                   en;
        input                   se;
        input                   scan_in;
        input                   siclk;
        input                   soclk;
        input                   pce_ov;
        input                   stop;
        output  [63:0]          dout_l;
        output                  scan_out;

        wire                    l1clk;
        wire                    siclk_out;
        wire                    soclk_out;
        wire    [62:0]          so;

        cl_dp1_l1hdr_8x c0_0(
                .l2clk                          (clk),
                .pce                            (en),
                .aclk                           (siclk),
                .bclk                           (soclk),
                .l1clk                          (l1clk),
                .se                             (se),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out));
        msffiz_dp #(64) d0_0(
                .l1clk                          (l1clk),
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .d                              (din[63:0]),
                .si                             ({scan_in, so[62:0]}),
                .so                             ({so[62:0], scan_out}),
                .q_l                            (dout_l[63:0]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_bfg_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_bfg_dp (
  pcx_spc_grant_px, 
  pcx_spc_grant_pa, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire i_dff_grant_x_scanin;
wire i_dff_grant_x_scanout;
wire [13:0] pcx_spc_grant_x;
wire scan_out_prebuf;


output [13:0] pcx_spc_grant_px;

input [13:0] pcx_spc_grant_pa;

// globals
input tcu_scan_en ;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
output          scan_out;

// buffer the high fanout nets
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk = ccx_aclk_out;
assign soclk = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

pcx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_4 buf_hfn    (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);


pcx_bfg_dp_msff_macro__stack_14r__width_14 i_dff_grant_x   (
	.scan_in(i_dff_grant_x_scanin),
	.scan_out(i_dff_grant_x_scanout),
	.clk	(l2clk),
	.din	(pcx_spc_grant_pa[13:0]),
	.dout	(pcx_spc_grant_x[13:0]),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

pcx_bfg_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_14 i_buf_grant_x     (
	.din	(pcx_spc_grant_x[13:0]),
	.dout	(pcx_spc_grant_px[13:0])
);

pcx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_1 buf_scanout    (
	.din	(scan_out_prebuf),
	.dout	(scan_out)
);

// fixscan start:
assign i_dff_grant_x_scanin      = scan_in                  ;
assign scan_out_prebuf                  = i_dff_grant_x_scanout    ;
// fixscan end:
endmodule // pcx_bfc_dp


//
//   buff macro
//
//


module pcx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_bfg_dp_msff_macro__stack_14r__width_14 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [12:0] so;

  input [13:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [13:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


//
//   buff macro
//
//


module pcx_bfg_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_14 (
  din, 
  dout);
  input [13:0] din;
  output [13:0] dout;


buff #(14)  d0_0 (
.in(din[13:0]),
.out(dout[13:0])
);


endmodule


//
//   buff macro
//
//


module pcx_bfg_dp_buff_macro__dbuff_8x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_bfg_dp(pcx_spc_grant_px, pcx_spc_grant_pa, tcu_scan_en, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_out, ccx_aclk_out, 
	ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[13:0]		pcx_spc_grant_px;
	input	[13:0]		pcx_spc_grant_pa;
	input			tcu_scan_en;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk;
	wire			soclk;
	wire			se;
	wire			i_dff_grant_x_scanin;
	wire			i_dff_grant_x_scanout;
	wire	[13:0]		pcx_spc_grant_x;
	wire			scan_out_prebuf;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk = ccx_aclk_out;
	assign soclk = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign i_dff_grant_x_scanin = scan_in;
	assign scan_out_prebuf = i_dff_grant_x_scanout;

	buff_macro__dbuff_8x__stack_none__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	msff_macro__stack_14r__width_14 i_dff_grant_x(
		.scan_in			(i_dff_grant_x_scanin), 
		.scan_out			(i_dff_grant_x_scanout), 
		.clk				(l2clk), 
		.din				(pcx_spc_grant_pa[13:0]), 
		.dout				(pcx_spc_grant_x[13:0]), 
		.en				(1'b1), 
		.se				(se), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	buff_macro__dbuff_32x__rep_1__stack_none__width_14 i_buf_grant_x(
		.din				(pcx_spc_grant_x[13:0]), 
		.dout				(pcx_spc_grant_px[13:0]));
	buff_macro__dbuff_8x__stack_none__width_1 buf_scanout(
		.din				(scan_out_prebuf), 
		.dout				(scan_out));
endmodule

module buff_macro__dbuff_32x__rep_1__stack_none__width_14(din, dout);

        input   [13:0]          din;
        output  [13:0]          dout;

        buff #(14) d0_0(
                .in                             (din[13:0]),
                .out                            (dout[13:0]));
endmodule

module msff_macro__stack_14r__width_14(din, clk, en, se, scan_in, siclk, soclk,
        pce_ov, stop, dout, scan_out);

        input   [13:0]          din;
        input                   clk;
        input                   en;
        input                   se;
        input                   scan_in;
        input                   siclk;
        input                   soclk;
        input                   pce_ov;
        input                   stop;
        output  [13:0]          dout;
        output                  scan_out;

        wire                    l1clk;
        wire                    siclk_out;
        wire                    soclk_out;
        wire    [12:0]          so;

        cl_dp1_l1hdr_8x c0_0(
                .l2clk                          (clk),
                .pce                            (en),
                .aclk                           (siclk),
                .bclk                           (soclk),
                .l1clk                          (l1clk),
                .se                             (se),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out));
        dff #(14) d0_0(
                .l1clk                          (l1clk),
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .d                              (din[13:0]),
                .si                             ({scan_in, so[12:0]}),
                .so                             ({so[12:0], scan_out}),
                .q                              (dout[13:0]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpa.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpa (
  pcx_io_data_x_, 
  pcx_scache0_data_x_, 
  pcx_scache1_data_x_, 
  pcx_scache2_data_x_, 
  pcx_scache3_data_x_, 
  pcx_scache4_data_x_, 
  pcx_scache5_data_x_, 
  pcx_scache6_data_x_, 
  pcx_scache7_data_x_, 
  arb0_grant_l_a, 
  arb0_q0_holdbar_l_a, 
  arb0_qsel0_l_a, 
  arb0_qsel1_l_a, 
  arb0_shift_l_a, 
  arb1_grant_l_a, 
  arb1_q0_holdbar_l_a, 
  arb1_qsel0_l_a, 
  arb1_qsel1_l_a, 
  arb1_shift_l_a, 
  arb2_grant_l_a, 
  arb2_q0_holdbar_l_a, 
  arb2_qsel0_l_a, 
  arb2_qsel1_l_a, 
  arb2_shift_l_a, 
  arb3_grant_l_a, 
  arb3_q0_holdbar_l_a, 
  arb3_qsel0_l_a, 
  arb3_qsel1_l_a, 
  arb3_shift_l_a, 
  arb4_grant_l_a, 
  arb4_q0_holdbar_l_a, 
  arb4_qsel0_l_a, 
  arb4_qsel1_l_a, 
  arb4_shift_l_a, 
  arb5_grant_l_a, 
  arb5_q0_holdbar_l_a, 
  arb5_qsel0_l_a, 
  arb5_qsel1_l_a, 
  arb5_shift_l_a, 
  arb6_grant_l_a, 
  arb6_q0_holdbar_l_a, 
  arb6_qsel0_l_a, 
  arb6_qsel1_l_a, 
  arb6_shift_l_a, 
  arb7_grant_l_a, 
  arb7_q0_holdbar_l_a, 
  arb7_qsel0_l_a, 
  arb7_qsel1_l_a, 
  arb7_shift_l_a, 
  arb8_grant_l_a, 
  arb8_q0_holdbar_l_a, 
  arb8_qsel0_l_a, 
  arb8_qsel1_l_a, 
  arb8_shift_l_a, 
  arb0_grant_r_a, 
  arb0_q0_holdbar_r_a, 
  arb0_qsel0_r_a, 
  arb0_qsel1_r_a, 
  arb0_shift_r_a, 
  arb1_grant_r_a, 
  arb1_q0_holdbar_r_a, 
  arb1_qsel0_r_a, 
  arb1_qsel1_r_a, 
  arb1_shift_r_a, 
  arb2_grant_r_a, 
  arb2_q0_holdbar_r_a, 
  arb2_qsel0_r_a, 
  arb2_qsel1_r_a, 
  arb2_shift_r_a, 
  arb3_grant_r_a, 
  arb3_q0_holdbar_r_a, 
  arb3_qsel0_r_a, 
  arb3_qsel1_r_a, 
  arb3_shift_r_a, 
  arb4_grant_r_a, 
  arb4_q0_holdbar_r_a, 
  arb4_qsel0_r_a, 
  arb4_qsel1_r_a, 
  arb4_shift_r_a, 
  arb5_grant_r_a, 
  arb5_q0_holdbar_r_a, 
  arb5_qsel0_r_a, 
  arb5_qsel1_r_a, 
  arb5_shift_r_a, 
  arb6_grant_r_a, 
  arb6_q0_holdbar_r_a, 
  arb6_qsel0_r_a, 
  arb6_qsel1_r_a, 
  arb6_shift_r_a, 
  arb7_grant_r_a, 
  arb7_q0_holdbar_r_a, 
  arb7_qsel0_r_a, 
  arb7_qsel1_r_a, 
  arb7_shift_r_a, 
  arb8_grant_r_a, 
  arb8_q0_holdbar_r_a, 
  arb8_qsel0_r_a, 
  arb8_qsel1_r_a, 
  arb8_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  l2clk, 
  scan_in, 
  tcu_pce_ov_t, 
  tcu_scan_en_t, 
  ccx_aclk_t, 
  ccx_bclk_t, 
  tcu_pce_ov_b, 
  tcu_scan_en_b, 
  ccx_aclk_b, 
  ccx_bclk_b, 
  scan_out);
wire pcx_dps0_scanin;
wire pcx_dps0_scanout;
wire pcx_dps1_scanin;
wire pcx_dps1_scanout;
wire pcx_dps2_scanin;
wire pcx_dps2_scanout;
wire pcx_dps3_scanin;
wire pcx_dps3_scanout;
wire pcx_dps4_scanin;
wire pcx_dps4_scanout;
wire pcx_dps5_scanin;
wire pcx_dps5_scanout;
wire pcx_dps6_scanin;
wire pcx_dps6_scanout;
wire pcx_dps7_scanin;
wire pcx_dps7_scanout;
wire pcx_dps8_scanin;
wire pcx_dps8_scanout;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_io_data_x_;         // From pcx_dp8 of pcx_dp.v
output [129:0]          pcx_scache0_data_x_;    // From pcx_dp0 of pcx_dp.v
output [129:0]          pcx_scache1_data_x_;    // From pcx_dp1 of pcx_dp.v
output [129:0]          pcx_scache2_data_x_;    // From pcx_dp2 of pcx_dp.v
output [129:0]          pcx_scache3_data_x_;    // From pcx_dp3 of pcx_dp.v
output [129:0]          pcx_scache4_data_x_;    // From pcx_dp4 of pcx_dp.v
output [129:0]          pcx_scache5_data_x_;    // From pcx_dp5 of pcx_dp.v
output [129:0]          pcx_scache6_data_x_;    // From pcx_dp6 of pcx_dp.v
output [129:0]          pcx_scache7_data_x_;    // From pcx_dp7 of pcx_dp.v
// End of automatics


// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb0_grant_l_a;           // To pcx_dp0 of pcx_dp.v
input [7:0]             arb0_q0_holdbar_l_a;         // To pcx_dp0 of pcx_dp.v
input [7:0]             arb0_qsel0_l_a;           // To pcx_dp0 of pcx_dp.v
input [7:0]             arb0_qsel1_l_a;           // To pcx_dp0 of pcx_dp.v
input [7:0]             arb0_shift_l_a;           // To pcx_dp0 of pcx_dp.v
input [7:0]             arb1_grant_l_a;           // To pcx_dp1 of pcx_dp.v
input [7:0]             arb1_q0_holdbar_l_a;         // To pcx_dp1 of pcx_dp.v
input [7:0]             arb1_qsel0_l_a;           // To pcx_dp1 of pcx_dp.v
input [7:0]             arb1_qsel1_l_a;           // To pcx_dp1 of pcx_dp.v
input [7:0]             arb1_shift_l_a;           // To pcx_dp1 of pcx_dp.v
input [7:0]             arb2_grant_l_a;           // To pcx_dp2 of pcx_dp.v
input [7:0]             arb2_q0_holdbar_l_a;         // To pcx_dp2 of pcx_dp.v
input [7:0]             arb2_qsel0_l_a;           // To pcx_dp2 of pcx_dp.v
input [7:0]             arb2_qsel1_l_a;           // To pcx_dp2 of pcx_dp.v
input [7:0]             arb2_shift_l_a;           // To pcx_dp2 of pcx_dp.v
input [7:0]             arb3_grant_l_a;           // To pcx_dp3 of pcx_dp.v
input [7:0]             arb3_q0_holdbar_l_a;         // To pcx_dp3 of pcx_dp.v
input [7:0]             arb3_qsel0_l_a;           // To pcx_dp3 of pcx_dp.v
input [7:0]             arb3_qsel1_l_a;           // To pcx_dp3 of pcx_dp.v
input [7:0]             arb3_shift_l_a;           // To pcx_dp3 of pcx_dp.v
input [7:0]             arb4_grant_l_a;           // To pcx_dp4 of pcx_dp.v
input [7:0]             arb4_q0_holdbar_l_a;         // To pcx_dp4 of pcx_dp.v
input [7:0]             arb4_qsel0_l_a;           // To pcx_dp4 of pcx_dp.v
input [7:0]             arb4_qsel1_l_a;           // To pcx_dp4 of pcx_dp.v
input [7:0]             arb4_shift_l_a;           // To pcx_dp4 of pcx_dp.v
input [7:0]             arb5_grant_l_a;           // To pcx_dp5 of pcx_dp.v
input [7:0]             arb5_q0_holdbar_l_a;         // To pcx_dp5 of pcx_dp.v
input [7:0]             arb5_qsel0_l_a;           // To pcx_dp5 of pcx_dp.v
input [7:0]             arb5_qsel1_l_a;           // To pcx_dp5 of pcx_dp.v
input [7:0]             arb5_shift_l_a;           // To pcx_dp5 of pcx_dp.v
input [7:0]             arb6_grant_l_a;           // To pcx_dp6 of pcx_dp.v
input [7:0]             arb6_q0_holdbar_l_a;         // To pcx_dp6 of pcx_dp.v
input [7:0]             arb6_qsel0_l_a;           // To pcx_dp6 of pcx_dp.v
input [7:0]             arb6_qsel1_l_a;           // To pcx_dp6 of pcx_dp.v
input [7:0]             arb6_shift_l_a;           // To pcx_dp6 of pcx_dp.v
input [7:0]             arb7_grant_l_a;           // To pcx_dp7 of pcx_dp.v
input [7:0]             arb7_q0_holdbar_l_a;         // To pcx_dp7 of pcx_dp.v
input [7:0]             arb7_qsel0_l_a;           // To pcx_dp7 of pcx_dp.v
input [7:0]             arb7_qsel1_l_a;           // To pcx_dp7 of pcx_dp.v
input [7:0]             arb7_shift_l_a;           // To pcx_dp7 of pcx_dp.v
input [7:0]             arb8_grant_l_a;           // To pcx_dp8 of pcx_dp.v
input [7:0]             arb8_q0_holdbar_l_a;         // To pcx_dp8 of pcx_dp.v
input [7:0]             arb8_qsel0_l_a;           // To pcx_dp8 of pcx_dp.v
input [7:0]             arb8_qsel1_l_a;           // To pcx_dp8 of pcx_dp.v
input [7:0]             arb8_shift_l_a;           // To pcx_dp8 of pcx_dp.v
input [7:0]             arb0_grant_r_a;           // To pcx_dp0 of pcx_dp.v
input [7:0]             arb0_q0_holdbar_r_a;         // To pcx_dp0 of pcx_dp.v
input [7:0]             arb0_qsel0_r_a;           // To pcx_dp0 of pcx_dp.v
input [7:0]             arb0_qsel1_r_a;           // To pcx_dp0 of pcx_dp.v
input [7:0]             arb0_shift_r_a;           // To pcx_dp0 of pcx_dp.v
input [7:0]             arb1_grant_r_a;           // To pcx_dp1 of pcx_dp.v
input [7:0]             arb1_q0_holdbar_r_a;         // To pcx_dp1 of pcx_dp.v
input [7:0]             arb1_qsel0_r_a;           // To pcx_dp1 of pcx_dp.v
input [7:0]             arb1_qsel1_r_a;           // To pcx_dp1 of pcx_dp.v
input [7:0]             arb1_shift_r_a;           // To pcx_dp1 of pcx_dp.v
input [7:0]             arb2_grant_r_a;           // To pcx_dp2 of pcx_dp.v
input [7:0]             arb2_q0_holdbar_r_a;         // To pcx_dp2 of pcx_dp.v
input [7:0]             arb2_qsel0_r_a;           // To pcx_dp2 of pcx_dp.v
input [7:0]             arb2_qsel1_r_a;           // To pcx_dp2 of pcx_dp.v
input [7:0]             arb2_shift_r_a;           // To pcx_dp2 of pcx_dp.v
input [7:0]             arb3_grant_r_a;           // To pcx_dp3 of pcx_dp.v
input [7:0]             arb3_q0_holdbar_r_a;         // To pcx_dp3 of pcx_dp.v
input [7:0]             arb3_qsel0_r_a;           // To pcx_dp3 of pcx_dp.v
input [7:0]             arb3_qsel1_r_a;           // To pcx_dp3 of pcx_dp.v
input [7:0]             arb3_shift_r_a;           // To pcx_dp3 of pcx_dp.v
input [7:0]             arb4_grant_r_a;           // To pcx_dp4 of pcx_dp.v
input [7:0]             arb4_q0_holdbar_r_a;         // To pcx_dp4 of pcx_dp.v
input [7:0]             arb4_qsel0_r_a;           // To pcx_dp4 of pcx_dp.v
input [7:0]             arb4_qsel1_r_a;           // To pcx_dp4 of pcx_dp.v
input [7:0]             arb4_shift_r_a;           // To pcx_dp4 of pcx_dp.v
input [7:0]             arb5_grant_r_a;           // To pcx_dp5 of pcx_dp.v
input [7:0]             arb5_q0_holdbar_r_a;         // To pcx_dp5 of pcx_dp.v
input [7:0]             arb5_qsel0_r_a;           // To pcx_dp5 of pcx_dp.v
input [7:0]             arb5_qsel1_r_a;           // To pcx_dp5 of pcx_dp.v
input [7:0]             arb5_shift_r_a;           // To pcx_dp5 of pcx_dp.v
input [7:0]             arb6_grant_r_a;           // To pcx_dp6 of pcx_dp.v
input [7:0]             arb6_q0_holdbar_r_a;         // To pcx_dp6 of pcx_dp.v
input [7:0]             arb6_qsel0_r_a;           // To pcx_dp6 of pcx_dp.v
input [7:0]             arb6_qsel1_r_a;           // To pcx_dp6 of pcx_dp.v
input [7:0]             arb6_shift_r_a;           // To pcx_dp6 of pcx_dp.v
input [7:0]             arb7_grant_r_a;           // To pcx_dp7 of pcx_dp.v
input [7:0]             arb7_q0_holdbar_r_a;         // To pcx_dp7 of pcx_dp.v
input [7:0]             arb7_qsel0_r_a;           // To pcx_dp7 of pcx_dp.v
input [7:0]             arb7_qsel1_r_a;           // To pcx_dp7 of pcx_dp.v
input [7:0]             arb7_shift_r_a;           // To pcx_dp7 of pcx_dp.v
input [7:0]             arb8_grant_r_a;           // To pcx_dp8 of pcx_dp.v
input [7:0]             arb8_q0_holdbar_r_a;         // To pcx_dp8 of pcx_dp.v
input [7:0]             arb8_qsel0_r_a;           // To pcx_dp8 of pcx_dp.v
input [7:0]             arb8_qsel1_r_a;           // To pcx_dp8 of pcx_dp.v
input [7:0]             arb8_shift_r_a;           // To pcx_dp8 of pcx_dp.v
input [129:0]           spc0_pcx_data_a;        // To pcx_dp0 of pcx_dp.v, ...
input [129:0]           spc1_pcx_data_a;        // To pcx_dp0 of pcx_dp.v, ...
input [129:0]           spc2_pcx_data_a;        // To pcx_dp0 of pcx_dp.v, ...
input [129:0]           spc3_pcx_data_a;        // To pcx_dp0 of pcx_dp.v, ...
input [129:0]           spc4_pcx_data_a;        // To pcx_dp0 of pcx_dp.v, ...
input [129:0]           spc5_pcx_data_a;        // To pcx_dp0 of pcx_dp.v, ...
input [129:0]           spc6_pcx_data_a;        // To pcx_dp0 of pcx_dp.v, ...
input [129:0]           spc7_pcx_data_a;        // To pcx_dp0 of pcx_dp.v, ...
// End of automatics

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov_t;             // scan signals
input           tcu_scan_en_t ;
input           ccx_aclk_t;
input           ccx_bclk_t;
input           tcu_pce_ov_b;             // scan signals
input           tcu_scan_en_b ;
input           ccx_aclk_b;
input           ccx_bclk_b;
output          scan_out;

// slices are placed in the following order
//
//@pcx_dps0(pcx_dpsa)
//@pcx_dps4(pcx_dpsg)
//@pcx_dps8(pcx_dpsa)
//@pcx_dps1(pcx_dpsc)
//@pcx_dps5(pcx_dpse)
//
//@pcx_dps3(pcx_dpsd)
//@pcx_dps7(pcx_dpsf)
//@pcx_dps2(pcx_dpsb)
//@pcx_dps6(pcx_dpsh)


//
// pcx_dps AUTO_TEMPLATE (
// .pcx_scache_data_x_ (pcx_scache@_data_x_[129:0]),
// .arb_grant_l_a  (arb@_grant_l_a[7:0]),
// .arb_q0_holdbar_l_a(arb@_q0_holdbar_l_a[7:0]),
// .arb_qsel0_l_a  (arb@_qsel0_l_a[7:0]),
// .arb_qsel1_l_a  (arb@_qsel1_l_a[7:0]),
// .arb_shift_l_a  (arb@_shift_l_a[7:0]),
// .arb_grant_r_a  (arb@_grant_r_a[7:0]),
// .arb_q0_holdbar_r_a(arb@_q0_holdbar_r_a[7:0]),
// .arb_qsel0_r_a  (arb@_qsel0_r_a[7:0]),
// .arb_qsel1_r_a  (arb@_qsel1_r_a[7:0]),
// .arb_shift_r_a  (arb@_shift_r_a[7:0]),
// );


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    cl     br     br     br      br      br       br     ar
//     |
//      ---buf--
//              |
//              v
//           to sctag0 


// fixscan does not support "scan_in ());" syntax on last line of instantiation.
// For now, when making changes, turn on AUTOINST, C-x C-a,  turn off AUTOINST, fix last line,
// run fixscan.

pcx_dpsa pcx_dps0(
                  // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_scache0_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb0_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb0_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb0_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb0_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb0_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb0_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb0_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb0_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb0_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb0_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in (pcx_dps0_scanin),
                  .scan_out (pcx_dps0_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_t),
                  .ccx_bclk                (ccx_bclk_t),
                  .tcu_scan_en             (tcu_scan_en_t),
                  .tcu_pce_ov              (tcu_pce_ov_t)
                  );


// DATAPATH ORGANISATION(pcx_dps1)
//
//
//   sparc0 sparc2 sparc1 sparc3  sparc7  sparc5  sparc6  sparc4
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 <-mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    al     bl     cl     br      br      br       br     ar
//                  |
//            --buf--
//            |
//            v
//         to sctag1

pcx_dpsc pcx_dps1(
                  // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_scache1_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb1_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb1_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb1_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb1_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb1_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb1_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb1_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb1_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb1_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb1_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in(pcx_dps1_scanin),
                  .scan_out(pcx_dps1_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_t),
                  .ccx_bclk                (ccx_bclk_t),
                  .tcu_scan_en             (tcu_scan_en_t),
                  .tcu_pce_ov              (tcu_pce_ov_t)
                  );

// DATAPATH ORGANISATION(pcx_dps2)
//
//   sparc0 sparc2 sparc1 sparc3  sparc7  sparc5  sparc6  sparc4
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 <-mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    bl     cl     br     br      br      br       br     ar
//           |
//           buf
//            |
//            v
//         to sctag

pcx_dpsb pcx_dps2(
 // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_scache2_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb2_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb2_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb2_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb2_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb2_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb2_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb2_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb2_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb2_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb2_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in(pcx_dps2_scanin),
                  .scan_out(pcx_dps2_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_b),
                  .ccx_bclk                (ccx_bclk_b),
                  .tcu_scan_en             (tcu_scan_en_b),
                  .tcu_pce_ov              (tcu_pce_ov_b)
                  );


// DATAPATH ORGANISATION(pcx_dps3)
//
//   sparc0 sparc2 sparc1 sparc3  sparc7  sparc5  sparc6  sparc4
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 <-mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    al     bl     bl     cl      br      br       br     ar
//                         |
//                  --buf--
//                  |
//                  v
//               to sctag

pcx_dpsd pcx_dps3(
                  // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_scache3_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb3_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb3_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb3_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb3_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb3_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb3_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb3_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb3_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb3_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb3_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in(pcx_dps3_scanin),
                  .scan_out(pcx_dps3_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_b),
                  .ccx_bclk                (ccx_bclk_b),
                  .tcu_scan_en             (tcu_scan_en_b),
                  .tcu_pce_ov              (tcu_pce_ov_b)
                  );


// DATAPATH ORGANISATION(pcx_dps4)
//
//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    al     bl     bl     bl      bl      bl       cr     br
//                                                  |
//                                                  --buf--
//                                                        |     
//                                                        v     
//                                                      to sctag4


pcx_dpsg pcx_dps4(
                  // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_scache4_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb4_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb4_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb4_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb4_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb4_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb4_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb4_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb4_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb4_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb4_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in(pcx_dps4_scanin),
                  .scan_out(pcx_dps4_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_t),
                  .ccx_bclk                (ccx_bclk_t),
                  .tcu_scan_en             (tcu_scan_en_t),
                  .tcu_pce_ov              (tcu_pce_ov_t)
                  );


// DATAPATH ORGANISATION(pcx_dps5)
//
//   sparc0 sparc2 sparc1 sparc3  sparc7  sparc5  sparc6  sparc4
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 -> mac4 <- mac5 <- mac6 <- mac7 
//    al     bl     bl     bl      cr      br       br     ar
//                                 |
//                                 ------buf------
//                                                |     
//                                                v     
//                                             to sctag5

pcx_dpse pcx_dps5(
                  // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_scache5_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb5_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb5_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb5_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb5_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb5_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb5_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb5_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb5_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb5_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb5_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in(pcx_dps5_scanin),
                  .scan_out(pcx_dps5_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_t),
                  .ccx_bclk                (ccx_bclk_t),
                  .tcu_scan_en             (tcu_scan_en_t),
                  .tcu_pce_ov              (tcu_pce_ov_t)
                  );


// DATAPATH ORGANISATION(pcx_dps6)
//
//   sparc0 sparc2 sparc1 sparc3  sparc7  sparc5  sparc6  sparc4
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 -> mac4 -> mac5 <- mac6 <- mac7 
//    al     bl     bl     bl      bl      bl       bl     cr
//                                                         |
//                                                       buf
//                                                         |    
//                                                         v    
//                                                      to sctag6

pcx_dpsh pcx_dps6(
                  // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_scache6_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb6_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb6_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb6_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb6_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb6_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb6_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb6_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb6_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb6_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb6_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in(pcx_dps6_scanin),
                  .scan_out(pcx_dps6_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_b),
                  .ccx_bclk                (ccx_bclk_b),
                  .tcu_scan_en             (tcu_scan_en_b),
                  .tcu_pce_ov              (tcu_pce_ov_b)
                  );


// DATAPATH ORGANISATION(pcx_dps7)
//
//   sparc0 sparc2 sparc1 sparc3  sparc7  sparc5  sparc6  sparc4
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 -> mac4 -> mac5 <- mac6 <- mac7 
//    al     bl     bl     bl      bl      cr       br     ar
//                                          |
//                                         buf----
//                                               |    
//                                               v    
//                                            to sctag7

pcx_dpsf pcx_dps7(
                  // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_scache7_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb7_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb7_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb7_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb7_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb7_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb7_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb7_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb7_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb7_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb7_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in(pcx_dps7_scanin),
                  .scan_out(pcx_dps7_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_b),
                  .ccx_bclk                (ccx_bclk_b),
                  .tcu_scan_en             (tcu_scan_en_b),
                  .tcu_pce_ov              (tcu_pce_ov_b)
                  );


// DATAPATH ORGANISATION(pcx_dps8)
//
//   sparc0 sparc2 sparc1 sparc3  sparc7  sparc5  sparc6  sparc4
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 <- mac1 <-mac2 <-mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    cl     br     br     br      br      br       br     ar
//     |
//     buf
//      |
//      v
//   to IOBRIDGE


pcx_dpsa pcx_dps8(
                  // /*AUTOINST*/
                  // Outputs
                  .pcx_scache_data_x_      (pcx_io_data_x_[129:0]),
                  // Inputs
                  .arb_grant_l_a             (arb8_grant_l_a[7:0]),
                  .arb_q0_holdbar_l_a        (arb8_q0_holdbar_l_a[7:0]),
                  .arb_qsel0_l_a             (arb8_qsel0_l_a[7:0]),
                  .arb_qsel1_l_a             (arb8_qsel1_l_a[7:0]),
                  .arb_shift_l_a             (arb8_shift_l_a[7:0]),
                  .arb_grant_r_a             (arb8_grant_r_a[7:0]),
                  .arb_q0_holdbar_r_a        (arb8_q0_holdbar_r_a[7:0]),
                  .arb_qsel0_r_a             (arb8_qsel0_r_a[7:0]),
                  .arb_qsel1_r_a             (arb8_qsel1_r_a[7:0]),
                  .arb_shift_r_a             (arb8_shift_r_a[7:0]),
                  .spc0_pcx_data_a         (spc0_pcx_data_a[129:0]),
                  .spc1_pcx_data_a         (spc1_pcx_data_a[129:0]),
                  .spc2_pcx_data_a         (spc2_pcx_data_a[129:0]),
                  .spc3_pcx_data_a         (spc3_pcx_data_a[129:0]),
                  .spc4_pcx_data_a         (spc4_pcx_data_a[129:0]),
                  .spc5_pcx_data_a         (spc5_pcx_data_a[129:0]),
                  .spc6_pcx_data_a         (spc6_pcx_data_a[129:0]),
                  .spc7_pcx_data_a         (spc7_pcx_data_a[129:0]),
                  .scan_in(pcx_dps8_scanin),
                  .scan_out(pcx_dps8_scanout),
                  .l2clk                   (l2clk),
                  .ccx_aclk                (ccx_aclk_t),
                  .ccx_bclk                (ccx_bclk_t),
                  .tcu_scan_en             (tcu_scan_en_t),
                  .tcu_pce_ov              (tcu_pce_ov_t)
                  );


// fixscan start:
assign pcx_dps0_scanin           = scan_in                  ;
assign pcx_dps4_scanin           = pcx_dps0_scanout         ;
assign pcx_dps8_scanin           = pcx_dps4_scanout         ;
assign pcx_dps1_scanin           = pcx_dps8_scanout         ;
assign pcx_dps5_scanin           = pcx_dps1_scanout         ;
assign pcx_dps3_scanin           = pcx_dps5_scanout         ;
assign pcx_dps7_scanin           = pcx_dps3_scanout         ;
assign pcx_dps2_scanin           = pcx_dps7_scanout         ;
assign pcx_dps6_scanin           = pcx_dps2_scanout         ;
assign scan_out                  = pcx_dps6_scanout         ;
// fixscan end:
endmodule 


// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpa_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpa_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   buff macro
//
//


module pcx_dpa_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpa_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpa_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpa_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = ccx_aclk;
//assign soclk = ccx_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpa_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpa_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//   ccx macro
//
//


module pcx_dpa_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule
`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpa(pcx_io_data_x_, pcx_scache0_data_x_, pcx_scache1_data_x_, 
	pcx_scache2_data_x_, pcx_scache3_data_x_, pcx_scache4_data_x_, 
	pcx_scache5_data_x_, pcx_scache6_data_x_, pcx_scache7_data_x_, 
	arb0_grant_l_a, arb0_q0_holdbar_l_a, arb0_qsel0_l_a, arb0_qsel1_l_a, 
	arb0_shift_l_a, arb1_grant_l_a, arb1_q0_holdbar_l_a, arb1_qsel0_l_a, 
	arb1_qsel1_l_a, arb1_shift_l_a, arb2_grant_l_a, arb2_q0_holdbar_l_a, 
	arb2_qsel0_l_a, arb2_qsel1_l_a, arb2_shift_l_a, arb3_grant_l_a, 
	arb3_q0_holdbar_l_a, arb3_qsel0_l_a, arb3_qsel1_l_a, arb3_shift_l_a, 
	arb4_grant_l_a, arb4_q0_holdbar_l_a, arb4_qsel0_l_a, arb4_qsel1_l_a, 
	arb4_shift_l_a, arb5_grant_l_a, arb5_q0_holdbar_l_a, arb5_qsel0_l_a, 
	arb5_qsel1_l_a, arb5_shift_l_a, arb6_grant_l_a, arb6_q0_holdbar_l_a, 
	arb6_qsel0_l_a, arb6_qsel1_l_a, arb6_shift_l_a, arb7_grant_l_a, 
	arb7_q0_holdbar_l_a, arb7_qsel0_l_a, arb7_qsel1_l_a, arb7_shift_l_a, 
	arb8_grant_l_a, arb8_q0_holdbar_l_a, arb8_qsel0_l_a, arb8_qsel1_l_a, 
	arb8_shift_l_a, arb0_grant_r_a, arb0_q0_holdbar_r_a, arb0_qsel0_r_a, 
	arb0_qsel1_r_a, arb0_shift_r_a, arb1_grant_r_a, arb1_q0_holdbar_r_a, 
	arb1_qsel0_r_a, arb1_qsel1_r_a, arb1_shift_r_a, arb2_grant_r_a, 
	arb2_q0_holdbar_r_a, arb2_qsel0_r_a, arb2_qsel1_r_a, arb2_shift_r_a, 
	arb3_grant_r_a, arb3_q0_holdbar_r_a, arb3_qsel0_r_a, arb3_qsel1_r_a, 
	arb3_shift_r_a, arb4_grant_r_a, arb4_q0_holdbar_r_a, arb4_qsel0_r_a, 
	arb4_qsel1_r_a, arb4_shift_r_a, arb5_grant_r_a, arb5_q0_holdbar_r_a, 
	arb5_qsel0_r_a, arb5_qsel1_r_a, arb5_shift_r_a, arb6_grant_r_a, 
	arb6_q0_holdbar_r_a, arb6_qsel0_r_a, arb6_qsel1_r_a, arb6_shift_r_a, 
	arb7_grant_r_a, arb7_q0_holdbar_r_a, arb7_qsel0_r_a, arb7_qsel1_r_a, 
	arb7_shift_r_a, arb8_grant_r_a, arb8_q0_holdbar_r_a, arb8_qsel0_r_a, 
	arb8_qsel1_r_a, arb8_shift_r_a, spc0_pcx_data_a, spc1_pcx_data_a, 
	spc2_pcx_data_a, spc3_pcx_data_a, spc4_pcx_data_a, spc5_pcx_data_a, 
	spc6_pcx_data_a, spc7_pcx_data_a, l2clk, scan_in, tcu_pce_ov_t, 
	tcu_scan_en_t, ccx_aclk_t, ccx_bclk_t, tcu_pce_ov_b, tcu_scan_en_b, 
	ccx_aclk_b, ccx_bclk_b, scan_out);

	output	[129:0]		pcx_io_data_x_;
	output	[129:0]		pcx_scache0_data_x_;
	output	[129:0]		pcx_scache1_data_x_;
	output	[129:0]		pcx_scache2_data_x_;
	output	[129:0]		pcx_scache3_data_x_;
	output	[129:0]		pcx_scache4_data_x_;
	output	[129:0]		pcx_scache5_data_x_;
	output	[129:0]		pcx_scache6_data_x_;
	output	[129:0]		pcx_scache7_data_x_;
	input	[7:0]		arb0_grant_l_a;
	input	[7:0]		arb0_q0_holdbar_l_a;
	input	[7:0]		arb0_qsel0_l_a;
	input	[7:0]		arb0_qsel1_l_a;
	input	[7:0]		arb0_shift_l_a;
	input	[7:0]		arb1_grant_l_a;
	input	[7:0]		arb1_q0_holdbar_l_a;
	input	[7:0]		arb1_qsel0_l_a;
	input	[7:0]		arb1_qsel1_l_a;
	input	[7:0]		arb1_shift_l_a;
	input	[7:0]		arb2_grant_l_a;
	input	[7:0]		arb2_q0_holdbar_l_a;
	input	[7:0]		arb2_qsel0_l_a;
	input	[7:0]		arb2_qsel1_l_a;
	input	[7:0]		arb2_shift_l_a;
	input	[7:0]		arb3_grant_l_a;
	input	[7:0]		arb3_q0_holdbar_l_a;
	input	[7:0]		arb3_qsel0_l_a;
	input	[7:0]		arb3_qsel1_l_a;
	input	[7:0]		arb3_shift_l_a;
	input	[7:0]		arb4_grant_l_a;
	input	[7:0]		arb4_q0_holdbar_l_a;
	input	[7:0]		arb4_qsel0_l_a;
	input	[7:0]		arb4_qsel1_l_a;
	input	[7:0]		arb4_shift_l_a;
	input	[7:0]		arb5_grant_l_a;
	input	[7:0]		arb5_q0_holdbar_l_a;
	input	[7:0]		arb5_qsel0_l_a;
	input	[7:0]		arb5_qsel1_l_a;
	input	[7:0]		arb5_shift_l_a;
	input	[7:0]		arb6_grant_l_a;
	input	[7:0]		arb6_q0_holdbar_l_a;
	input	[7:0]		arb6_qsel0_l_a;
	input	[7:0]		arb6_qsel1_l_a;
	input	[7:0]		arb6_shift_l_a;
	input	[7:0]		arb7_grant_l_a;
	input	[7:0]		arb7_q0_holdbar_l_a;
	input	[7:0]		arb7_qsel0_l_a;
	input	[7:0]		arb7_qsel1_l_a;
	input	[7:0]		arb7_shift_l_a;
	input	[7:0]		arb8_grant_l_a;
	input	[7:0]		arb8_q0_holdbar_l_a;
	input	[7:0]		arb8_qsel0_l_a;
	input	[7:0]		arb8_qsel1_l_a;
	input	[7:0]		arb8_shift_l_a;
	input	[7:0]		arb0_grant_r_a;
	input	[7:0]		arb0_q0_holdbar_r_a;
	input	[7:0]		arb0_qsel0_r_a;
	input	[7:0]		arb0_qsel1_r_a;
	input	[7:0]		arb0_shift_r_a;
	input	[7:0]		arb1_grant_r_a;
	input	[7:0]		arb1_q0_holdbar_r_a;
	input	[7:0]		arb1_qsel0_r_a;
	input	[7:0]		arb1_qsel1_r_a;
	input	[7:0]		arb1_shift_r_a;
	input	[7:0]		arb2_grant_r_a;
	input	[7:0]		arb2_q0_holdbar_r_a;
	input	[7:0]		arb2_qsel0_r_a;
	input	[7:0]		arb2_qsel1_r_a;
	input	[7:0]		arb2_shift_r_a;
	input	[7:0]		arb3_grant_r_a;
	input	[7:0]		arb3_q0_holdbar_r_a;
	input	[7:0]		arb3_qsel0_r_a;
	input	[7:0]		arb3_qsel1_r_a;
	input	[7:0]		arb3_shift_r_a;
	input	[7:0]		arb4_grant_r_a;
	input	[7:0]		arb4_q0_holdbar_r_a;
	input	[7:0]		arb4_qsel0_r_a;
	input	[7:0]		arb4_qsel1_r_a;
	input	[7:0]		arb4_shift_r_a;
	input	[7:0]		arb5_grant_r_a;
	input	[7:0]		arb5_q0_holdbar_r_a;
	input	[7:0]		arb5_qsel0_r_a;
	input	[7:0]		arb5_qsel1_r_a;
	input	[7:0]		arb5_shift_r_a;
	input	[7:0]		arb6_grant_r_a;
	input	[7:0]		arb6_q0_holdbar_r_a;
	input	[7:0]		arb6_qsel0_r_a;
	input	[7:0]		arb6_qsel1_r_a;
	input	[7:0]		arb6_shift_r_a;
	input	[7:0]		arb7_grant_r_a;
	input	[7:0]		arb7_q0_holdbar_r_a;
	input	[7:0]		arb7_qsel0_r_a;
	input	[7:0]		arb7_qsel1_r_a;
	input	[7:0]		arb7_shift_r_a;
	input	[7:0]		arb8_grant_r_a;
	input	[7:0]		arb8_q0_holdbar_r_a;
	input	[7:0]		arb8_qsel0_r_a;
	input	[7:0]		arb8_qsel1_r_a;
	input	[7:0]		arb8_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov_t;
	input			tcu_scan_en_t;
	input			ccx_aclk_t;
	input			ccx_bclk_t;
	input			tcu_pce_ov_b;
	input			tcu_scan_en_b;
	input			ccx_aclk_b;
	input			ccx_bclk_b;
	output			scan_out;

	wire			pcx_dps0_scanin;
	wire			pcx_dps0_scanout;
	wire			pcx_dps1_scanin;
	wire			pcx_dps1_scanout;
	wire			pcx_dps2_scanin;
	wire			pcx_dps2_scanout;
	wire			pcx_dps3_scanin;
	wire			pcx_dps3_scanout;
	wire			pcx_dps4_scanin;
	wire			pcx_dps4_scanout;
	wire			pcx_dps5_scanin;
	wire			pcx_dps5_scanout;
	wire			pcx_dps6_scanin;
	wire			pcx_dps6_scanout;
	wire			pcx_dps7_scanin;
	wire			pcx_dps7_scanout;
	wire			pcx_dps8_scanin;
	wire			pcx_dps8_scanout;

	assign pcx_dps0_scanin = scan_in;
	assign pcx_dps4_scanin = pcx_dps0_scanout;
	assign pcx_dps8_scanin = pcx_dps4_scanout;
	assign pcx_dps1_scanin = pcx_dps8_scanout;
	assign pcx_dps5_scanin = pcx_dps1_scanout;
	assign pcx_dps3_scanin = pcx_dps5_scanout;
	assign pcx_dps7_scanin = pcx_dps3_scanout;
	assign pcx_dps2_scanin = pcx_dps7_scanout;
	assign pcx_dps6_scanin = pcx_dps2_scanout;
	assign scan_out = pcx_dps6_scanout;

	pcx_dpsa pcx_dps0(
		.pcx_scache_data_x_		(pcx_scache0_data_x_[129:0]), 
		.arb_grant_l_a			(arb0_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb0_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb0_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb0_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb0_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb0_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb0_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb0_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb0_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb0_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps0_scanin), 
		.scan_out			(pcx_dps0_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
	pcx_dpsc pcx_dps1(
		.pcx_scache_data_x_		(pcx_scache1_data_x_[129:0]), 
		.arb_grant_l_a			(arb1_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb1_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb1_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb1_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb1_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb1_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb1_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb1_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb1_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb1_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps1_scanin), 
		.scan_out			(pcx_dps1_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
	pcx_dpsb pcx_dps2(
		.pcx_scache_data_x_		(pcx_scache2_data_x_[129:0]), 
		.arb_grant_l_a			(arb2_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb2_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb2_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb2_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb2_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb2_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb2_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb2_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb2_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb2_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps2_scanin), 
		.scan_out			(pcx_dps2_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_b), 
		.ccx_bclk			(ccx_bclk_b), 
		.tcu_scan_en			(tcu_scan_en_b), 
		.tcu_pce_ov			(tcu_pce_ov_b));
	pcx_dpsd pcx_dps3(
		.pcx_scache_data_x_		(pcx_scache3_data_x_[129:0]), 
		.arb_grant_l_a			(arb3_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb3_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb3_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb3_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb3_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb3_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb3_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb3_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb3_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb3_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps3_scanin), 
		.scan_out			(pcx_dps3_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_b), 
		.ccx_bclk			(ccx_bclk_b), 
		.tcu_scan_en			(tcu_scan_en_b), 
		.tcu_pce_ov			(tcu_pce_ov_b));
	pcx_dpsg pcx_dps4(
		.pcx_scache_data_x_		(pcx_scache4_data_x_[129:0]), 
		.arb_grant_l_a			(arb4_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb4_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb4_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb4_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb4_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb4_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb4_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb4_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb4_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb4_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps4_scanin), 
		.scan_out			(pcx_dps4_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
	pcx_dpse pcx_dps5(
		.pcx_scache_data_x_		(pcx_scache5_data_x_[129:0]), 
		.arb_grant_l_a			(arb5_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb5_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb5_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb5_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb5_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb5_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb5_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb5_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb5_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb5_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps5_scanin), 
		.scan_out			(pcx_dps5_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
	pcx_dpsh pcx_dps6(
		.pcx_scache_data_x_		(pcx_scache6_data_x_[129:0]), 
		.arb_grant_l_a			(arb6_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb6_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb6_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb6_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb6_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb6_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb6_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb6_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb6_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb6_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps6_scanin), 
		.scan_out			(pcx_dps6_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_b), 
		.ccx_bclk			(ccx_bclk_b), 
		.tcu_scan_en			(tcu_scan_en_b), 
		.tcu_pce_ov			(tcu_pce_ov_b));
	pcx_dpsf pcx_dps7(
		.pcx_scache_data_x_		(pcx_scache7_data_x_[129:0]), 
		.arb_grant_l_a			(arb7_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb7_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb7_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb7_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb7_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb7_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb7_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb7_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb7_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb7_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps7_scanin), 
		.scan_out			(pcx_dps7_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_b), 
		.ccx_bclk			(ccx_bclk_b), 
		.tcu_scan_en			(tcu_scan_en_b), 
		.tcu_pce_ov			(tcu_pce_ov_b));
	pcx_dpsa pcx_dps8(
		.pcx_scache_data_x_		(pcx_io_data_x_[129:0]), 
		.arb_grant_l_a			(arb8_grant_l_a[7:0]), 
		.arb_q0_holdbar_l_a		(arb8_q0_holdbar_l_a[7:0]), 
		.arb_qsel0_l_a			(arb8_qsel0_l_a[7:0]), 
		.arb_qsel1_l_a			(arb8_qsel1_l_a[7:0]), 
		.arb_shift_l_a			(arb8_shift_l_a[7:0]), 
		.arb_grant_r_a			(arb8_grant_r_a[7:0]), 
		.arb_q0_holdbar_r_a		(arb8_q0_holdbar_r_a[7:0]), 
		.arb_qsel0_r_a			(arb8_qsel0_r_a[7:0]), 
		.arb_qsel1_r_a			(arb8_qsel1_r_a[7:0]), 
		.arb_shift_r_a			(arb8_shift_r_a[7:0]), 
		.spc0_pcx_data_a		(spc0_pcx_data_a[129:0]), 
		.spc1_pcx_data_a		(spc1_pcx_data_a[129:0]), 
		.spc2_pcx_data_a		(spc2_pcx_data_a[129:0]), 
		.spc3_pcx_data_a		(spc3_pcx_data_a[129:0]), 
		.spc4_pcx_data_a		(spc4_pcx_data_a[129:0]), 
		.spc5_pcx_data_a		(spc5_pcx_data_a[129:0]), 
		.spc6_pcx_data_a		(spc6_pcx_data_a[129:0]), 
		.spc7_pcx_data_a		(spc7_pcx_data_a[129:0]), 
		.scan_in			(pcx_dps8_scanin), 
		.scan_out			(pcx_dps8_scanout), 
		.l2clk				(l2clk), 
		.ccx_aclk			(ccx_aclk_t), 
		.ccx_bclk			(ccx_bclk_t), 
		.tcu_scan_en			(tcu_scan_en_t), 
		.tcu_pce_ov			(tcu_pce_ov_t));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpsa.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpsa (
  pcx_scache_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_in, 
  scan_out);
wire [129:0] all_ones;
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:4] arb_grant_r_a_rep;
wire [7:4] arb_q0_holdbar_r_a_rep;
wire [7:4] arb_qsel0_r_a_rep;
wire [7:4] arb_qsel1_r_a_rep;
wire [7:4] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire tcu_scan_en_out_0_unused;
wire tcu_pce_ov_out_0_unused;
wire ccx_aclk_out_0_unused;
wire ccx_bclk_out_0_unused;
wire [129:0] col1_data_x_;
wire pcx_mac0_scanin;
wire pcx_mac0_scanout;
wire [6:1] tcu_scan_en_out;
wire [6:1] tcu_pce_ov_out;
wire [6:1] ccx_aclk_out;
wire [6:1] ccx_bclk_out;
wire [129:0] col2_data_x_;
wire pcx_mac1_scanin;
wire pcx_mac1_scanout;
wire [129:0] col3_data_x_;
wire pcx_mac2_scanin;
wire pcx_mac2_scanout;
wire [129:0] col4_data_x_;
wire pcx_mac3_scanin;
wire pcx_mac3_scanout;
wire [129:0] col5_data_x_;
wire pcx_mac4_scanin;
wire pcx_mac4_scanout;
wire [129:0] col6_data_x_;
wire pcx_mac5_scanin;
wire pcx_mac5_scanout;
wire [129:0] col7_data_x_;
wire pcx_mac6_scanin;
wire pcx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire pcx_mac7_scanin;
wire pcx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [3:0] arb_grant_r_a_unused;
wire [3:0] arb_q0_holdbar_r_a_unused;
wire [3:0] arb_qsel0_r_a_unused;
wire [3:0] arb_qsel1_r_a_unused;
wire [3:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_scache_data_x_;     // From mac3 of pcx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb_grant_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_l_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_grant_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_r_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [129:0]           spc0_pcx_data_a;        // To mac0 of pcx_mar_dp.v
input [129:0]           spc1_pcx_data_a;        // To mac1 of pcx_mbr_dp.v
input [129:0]           spc2_pcx_data_a;        // To mac2 of pcx_mbr_dp.v
input [129:0]           spc3_pcx_data_a;        // To mac3 of pcx_mcr_dp.v
input [129:0]           spc4_pcx_data_a;        // To mac4 of pcx_mbl_dp.v
input [129:0]           spc5_pcx_data_a;        // To mac5 of pcx_mbl_dp.v
input [129:0]           spc6_pcx_data_a;        // To mac6 of pcx_mbl_dp.v
input [129:0]           spc7_pcx_data_a;        // To mac7 of pcx_mal_dp.v
// End of automatics
// globals
input tcu_scan_en ;
input           l2clk;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           scan_in;
output          scan_out;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    cl     br     br     br      br      br       br     ar
//    |
//    ---buf--
//            |
//            v
//          to sctag 

assign all_ones[129:0] = 130'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;


// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
                           arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
        arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
                       arb_qsel1_l_a[2],arb_shift_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
        arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
                       arb_qsel1_r_a[4],arb_shift_r_a[4]};

assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
        arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


// input from spc0
pcx_mcl_dp pcx_mac0(
                    // Outputs
                    .data_out_x_        (pcx_scache_data_x_[129:0]), // Templated
                    .tcu_scan_en_out (tcu_scan_en_out_0_unused),
                    .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
                    .ccx_aclk_out (ccx_aclk_out_0_unused),
                    .ccx_bclk_out (ccx_bclk_out_0_unused),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[0]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[0]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[0]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[0]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[0]),        // Templated
                    .src_pcx_data_a     (spc0_pcx_data_a[129:0]), // Templated
                    .data_crit_x_       (col1_data_x_[129:0]),   // Templated
                    .data_ncrit_x_      (all_ones[129:0]),   // Templated
                    .scan_in(pcx_mac0_scanin),
                    .scan_out(pcx_mac0_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[1]),
                    .tcu_pce_ov (tcu_pce_ov_out[1]),
                    .ccx_aclk (ccx_aclk_out[1]),
                    .ccx_bclk (ccx_bclk_out[1])
                    );


/*
   pcx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
 */

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.


// input from spc2
pcx_mbr_dp pcx_mac1(
                    // Outputs
                    .data_out_x_        (col1_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[1]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                    .ccx_aclk_out (ccx_aclk_out[1]),
                    .ccx_bclk_out (ccx_bclk_out[1]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[2]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[2]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[2]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[2]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[2]),        // Templated
                    .src_pcx_data_a     (spc2_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col2_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac1_scanin),
                    .scan_out(pcx_mac1_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[2]),
                    .tcu_pce_ov (tcu_pce_ov_out[2]),
                    .ccx_aclk (ccx_aclk_out[2]),
                    .ccx_bclk (ccx_bclk_out[2])
                    );


// input from spc1
pcx_mbr_dp pcx_mac2(
                    // Outputs
                    .data_out_x_        (col2_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[2]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                    .ccx_aclk_out (ccx_aclk_out[2]),
                    .ccx_bclk_out (ccx_bclk_out[2]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[1]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[1]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[1]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[1]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[1]),        // Templated
                    .src_pcx_data_a     (spc1_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col3_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac2_scanin),
                    .scan_out(pcx_mac2_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );
 
// input from spc3
pcx_mbr_dp pcx_mac3(
                    // Outputs
                    .data_out_x_        (col3_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[3]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                    .ccx_aclk_out (ccx_aclk_out[3]),
                    .ccx_bclk_out (ccx_bclk_out[3]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[3]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[3]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[3]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[3]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[3]),        // Templated
                    .src_pcx_data_a     (spc3_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col4_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac3_scanin),
                    .scan_out(pcx_mac3_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en),
                    .tcu_pce_ov (tcu_pce_ov),
                    .ccx_aclk (ccx_aclk),
                    .ccx_bclk (ccx_bclk)
                    );

 
// input from spc5
pcx_mbr_dp pcx_mac4(
                    // Outputs
                    .data_out_x_        (col4_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[4]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                    .ccx_aclk_out (ccx_aclk_out[4]),
                    .ccx_bclk_out (ccx_bclk_out[4]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[5]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[5]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[5]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[5]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[5]),        // Templated
                    .src_pcx_data_a     (spc5_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col5_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac4_scanin),
                    .scan_out(pcx_mac4_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

// input from spc7
pcx_mbr_dp pcx_mac5(
                    // Outputs
                    .data_out_x_        (col5_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[5]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                    .ccx_aclk_out (ccx_aclk_out[5]),
                    .ccx_bclk_out (ccx_bclk_out[5]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[7]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[7]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[7]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[7]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[7]),        // Templated
                    .src_pcx_data_a     (spc7_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col6_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac5_scanin),
                    .scan_out(pcx_mac5_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[4]),
                    .tcu_pce_ov (tcu_pce_ov_out[4]),
                    .ccx_aclk (ccx_aclk_out[4]),
                    .ccx_bclk (ccx_bclk_out[4])
                    );

 
// input from spc4
pcx_mbr_dp pcx_mac6(
                    // Outputs
                    .data_out_x_        (col6_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[6]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                    .ccx_aclk_out (ccx_aclk_out[6]),
                    .ccx_bclk_out (ccx_bclk_out[6]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[4]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[4]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[4]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[4]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[4]),        // Templated
                    .src_pcx_data_a     (spc4_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col7_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac6_scanin),
                    .scan_out(pcx_mac6_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[5]),
                    .tcu_pce_ov (tcu_pce_ov_out[5]),
                    .ccx_aclk (ccx_aclk_out[5]),
                    .ccx_bclk (ccx_bclk_out[5])
                    );
 

/*
   pcx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc6
pcx_mar_dp pcx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[129:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out (ccx_aclk_out_7_unused),
                     .ccx_bclk_out (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[6]),        // Templated
                     .src_pcx_data_a    (spc6_pcx_data_a[129:0]), // Templated
                     .scan_in(pcx_mac7_scanin),
                     .scan_out(pcx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[6]),
                     .tcu_pce_ov (tcu_pce_ov_out[6]),
                     .ccx_aclk (ccx_aclk_out[6]),
                     .ccx_bclk (ccx_bclk_out[6])
                     );


assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

// fixscan start:
assign pcx_mac0_scanin           = scan_rep_out             ;
assign pcx_mac1_scanin           = pcx_mac0_scanout         ;
assign pcx_mac2_scanin           = pcx_mac1_scanout         ;
assign pcx_mac3_scanin           = pcx_mac2_scanout         ;
assign pcx_mac4_scanin           = pcx_mac3_scanout         ;
assign pcx_mac5_scanin           = pcx_mac4_scanout         ;
assign pcx_mac6_scanin           = pcx_mac5_scanout         ;
assign pcx_mac7_scanin           = pcx_mac6_scanout         ;
assign scan_out                  = pcx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpsa_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsa_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsa_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpsa_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpsa_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsa_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = ccx_aclk;
//assign soclk = ccx_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsa_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpsa(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a, 
	spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a, 
	tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);

	output	[129:0]		pcx_scache_data_x_;
	input	[7:0]		arb_grant_l_a;
	input	[7:0]		arb_q0_holdbar_l_a;
	input	[7:0]		arb_qsel0_l_a;
	input	[7:0]		arb_qsel1_l_a;
	input	[7:0]		arb_shift_l_a;
	input	[7:0]		arb_grant_r_a;
	input	[7:0]		arb_q0_holdbar_r_a;
	input	[7:0]		arb_qsel0_r_a;
	input	[7:0]		arb_qsel1_r_a;
	input	[7:0]		arb_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			scan_in;
	output			scan_out;

	wire	[129:0]		all_ones;
	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:4]		arb_grant_r_a_rep;
	wire	[7:4]		arb_q0_holdbar_r_a_rep;
	wire	[7:4]		arb_qsel0_r_a_rep;
	wire	[7:4]		arb_qsel1_r_a_rep;
	wire	[7:4]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire			tcu_scan_en_out_0_unused;
	wire			tcu_pce_ov_out_0_unused;
	wire			ccx_aclk_out_0_unused;
	wire			ccx_bclk_out_0_unused;
	wire	[129:0]		col1_data_x_;
	wire			pcx_mac0_scanin;
	wire			pcx_mac0_scanout;
	wire	[6:1]		tcu_scan_en_out;
	wire	[6:1]		tcu_pce_ov_out;
	wire	[6:1]		ccx_aclk_out;
	wire	[6:1]		ccx_bclk_out;
	wire	[129:0]		col2_data_x_;
	wire			pcx_mac1_scanin;
	wire			pcx_mac1_scanout;
	wire	[129:0]		col3_data_x_;
	wire			pcx_mac2_scanin;
	wire			pcx_mac2_scanout;
	wire	[129:0]		col4_data_x_;
	wire			pcx_mac3_scanin;
	wire			pcx_mac3_scanout;
	wire	[129:0]		col5_data_x_;
	wire			pcx_mac4_scanin;
	wire			pcx_mac4_scanout;
	wire	[129:0]		col6_data_x_;
	wire			pcx_mac5_scanin;
	wire			pcx_mac5_scanout;
	wire	[129:0]		col7_data_x_;
	wire			pcx_mac6_scanin;
	wire			pcx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			pcx_mac7_scanin;
	wire			pcx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[3:0]		arb_grant_r_a_unused;
	wire	[3:0]		arb_q0_holdbar_r_a_unused;
	wire	[3:0]		arb_qsel0_r_a_unused;
	wire	[3:0]		arb_qsel1_r_a_unused;
	wire	[3:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign all_ones[129:0] = 130'h3ffffffffffffffffffffffffffffffff;
	assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0], 
		arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0], 
		arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0], 
		arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2], 
		arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2], 
		arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4], 
		arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
	assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4], 
		arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign pcx_mac0_scanin = scan_rep_out;
	assign pcx_mac1_scanin = pcx_mac0_scanout;
	assign pcx_mac2_scanin = pcx_mac1_scanout;
	assign pcx_mac3_scanin = pcx_mac2_scanout;
	assign pcx_mac4_scanin = pcx_mac3_scanout;
	assign pcx_mac5_scanin = pcx_mac4_scanout;
	assign pcx_mac6_scanin = pcx_mac5_scanout;
	assign pcx_mac7_scanin = pcx_mac6_scanout;
	assign scan_out = pcx_mac7_scanout;

	pcx_rep_dp pcx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	pcx_mcl_dp pcx_mac0(
		.data_out_x_			(pcx_scache_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_0_unused), 
		.ccx_aclk_out			(ccx_aclk_out_0_unused), 
		.ccx_bclk_out			(ccx_bclk_out_0_unused), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_pcx_data_a			(spc0_pcx_data_a[129:0]), 
		.data_crit_x_			(col1_data_x_[129:0]), 
		.data_ncrit_x_			(all_ones[129:0]), 
		.scan_in			(pcx_mac0_scanin), 
		.scan_out			(pcx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	pcx_mbr_dp pcx_mac1(
		.data_out_x_			(col1_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_pcx_data_a			(spc2_pcx_data_a[129:0]), 
		.data_prev_x_			(col2_data_x_[129:0]), 
		.scan_in			(pcx_mac1_scanin), 
		.scan_out			(pcx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	pcx_mbr_dp pcx_mac2(
		.data_out_x_			(col2_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_pcx_data_a			(spc1_pcx_data_a[129:0]), 
		.data_prev_x_			(col3_data_x_[129:0]), 
		.scan_in			(pcx_mac2_scanin), 
		.scan_out			(pcx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbr_dp pcx_mac3(
		.data_out_x_			(col3_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_pcx_data_a			(spc3_pcx_data_a[129:0]), 
		.data_prev_x_			(col4_data_x_[129:0]), 
		.scan_in			(pcx_mac3_scanin), 
		.scan_out			(pcx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	pcx_mbr_dp pcx_mac4(
		.data_out_x_			(col4_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_pcx_data_a			(spc5_pcx_data_a[129:0]), 
		.data_prev_x_			(col5_data_x_[129:0]), 
		.scan_in			(pcx_mac4_scanin), 
		.scan_out			(pcx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbr_dp pcx_mac5(
		.data_out_x_			(col5_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_pcx_data_a			(spc7_pcx_data_a[129:0]), 
		.data_prev_x_			(col6_data_x_[129:0]), 
		.scan_in			(pcx_mac5_scanin), 
		.scan_out			(pcx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	pcx_mbr_dp pcx_mac6(
		.data_out_x_			(col6_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[4]), 
		.arb_shift_a			(arb_shift_r_a_rep[4]), 
		.src_pcx_data_a			(spc4_pcx_data_a[129:0]), 
		.data_prev_x_			(col7_data_x_[129:0]), 
		.scan_in			(pcx_mac6_scanin), 
		.scan_out			(pcx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	pcx_mar_dp pcx_mac7(
		.data_out_x_			(col7_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[6]), 
		.arb_shift_a			(arb_shift_r_a[6]), 
		.src_pcx_data_a			(spc6_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac7_scanin), 
		.scan_out			(pcx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpsb.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpsb (
  pcx_scache_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_in, 
  scan_out);
wire [129:0] all_ones;
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:4] arb_grant_r_a_rep;
wire [7:4] arb_q0_holdbar_r_a_rep;
wire [7:4] arb_qsel0_r_a_rep;
wire [7:4] arb_qsel1_r_a_rep;
wire [7:4] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [129:0] col0_data_x_;
wire tcu_scan_en_out_0_unused;
wire tcu_pce_ov_out_0_unused;
wire ccx_aclk_out_0_unused;
wire ccx_bclk_out_0_unused;
wire pcx_mac0_scanin;
wire pcx_mac0_scanout;
wire [6:1] tcu_scan_en_out;
wire [6:1] tcu_pce_ov_out;
wire [6:1] ccx_aclk_out;
wire [6:1] ccx_bclk_out;
wire [129:0] col2_data_x_;
wire pcx_mac1_scanin;
wire pcx_mac1_scanout;
wire [129:0] col3_data_x_;
wire pcx_mac2_scanin;
wire pcx_mac2_scanout;
wire [129:0] col4_data_x_;
wire pcx_mac3_scanin;
wire pcx_mac3_scanout;
wire [129:0] col5_data_x_;
wire pcx_mac4_scanin;
wire pcx_mac4_scanout;
wire [129:0] col6_data_x_;
wire pcx_mac5_scanin;
wire pcx_mac5_scanout;
wire [129:0] col7_data_x_;
wire pcx_mac6_scanin;
wire pcx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire pcx_mac7_scanin;
wire pcx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [3:0] arb_grant_r_a_unused;
wire [3:0] arb_q0_holdbar_r_a_unused;
wire [3:0] arb_qsel0_r_a_unused;
wire [3:0] arb_qsel1_r_a_unused;
wire [3:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_scache_data_x_;     // From mac3 of pcx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb_grant_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_l_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_grant_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_r_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [129:0]           spc0_pcx_data_a;        // To mac0 of pcx_mar_dp.v
input [129:0]           spc1_pcx_data_a;        // To mac1 of pcx_mbr_dp.v
input [129:0]           spc2_pcx_data_a;        // To mac2 of pcx_mbr_dp.v
input [129:0]           spc3_pcx_data_a;        // To mac3 of pcx_mcr_dp.v
input [129:0]           spc4_pcx_data_a;        // To mac4 of pcx_mbl_dp.v
input [129:0]           spc5_pcx_data_a;        // To mac5 of pcx_mbl_dp.v
input [129:0]           spc6_pcx_data_a;        // To mac6 of pcx_mbl_dp.v
input [129:0]           spc7_pcx_data_a;        // To mac7 of pcx_mal_dp.v
// End of automatics
// globals
input tcu_scan_en ;
input           l2clk;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           scan_in;
output          scan_out;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 <-mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    bl     cl      br     br      br      br       br     ar
//            |
//            buf
//            |
//            v
//         to sctag

assign all_ones[129:0] = 130'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
                           arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
        arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
                       arb_qsel1_l_a[2],arb_shift_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
        arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
                       arb_qsel1_r_a[4],arb_shift_r_a[4]};

assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
        arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


/*
   pcx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from sp0
pcx_mbl_dp pcx_mac0 ( 
                      // Outputs
                      .data_out_x_       (col0_data_x_[129:0]),   // Templated
                      .tcu_scan_en_out (tcu_scan_en_out_0_unused),
                      .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
                      .ccx_aclk_out (ccx_aclk_out_0_unused),
                      .ccx_bclk_out (ccx_bclk_out_0_unused),
                      // Inputs
                      .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                      .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                      .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                      .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                      .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                      .src_pcx_data_a    (spc0_pcx_data_a[129:0]), // Templated
                      .data_prev_x_      (all_ones[129:0]),   // Templated
                      .scan_in(pcx_mac0_scanin),
                      .scan_out(pcx_mac0_scanout),
                      .l2clk             (l2clk),                 // Templated
                      .tcu_scan_en (tcu_scan_en_out[1]),
                      .tcu_pce_ov (tcu_pce_ov_out[1]),
                      .ccx_aclk (ccx_aclk_out[1]),
                      .ccx_bclk (ccx_bclk_out[1])
                      );


/*
   pcx_mcl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(pcx_scache_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/

// input from spc2
pcx_mcl_dp pcx_mac1(
                    // Outputs
                    .data_out_x_        (pcx_scache_data_x_[129:0]), // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[1]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                    .ccx_aclk_out (ccx_aclk_out[1]),
                    .ccx_bclk_out (ccx_bclk_out[1]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[2]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[2]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[2]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[2]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[2]),        // Templated
                    .src_pcx_data_a     (spc2_pcx_data_a[129:0]), // Templated
                    .data_crit_x_       (col2_data_x_[129:0]),   // Templated
                    .data_ncrit_x_      (col0_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac1_scanin),
                    .scan_out(pcx_mac1_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[2]),
                    .tcu_pce_ov (tcu_pce_ov_out[2]),
                    .ccx_aclk (ccx_aclk_out[2]),
                    .ccx_bclk (ccx_bclk_out[2])
                    );


/*
   pcx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc1
pcx_mbr_dp pcx_mac2(
                    // Outputs
                    .data_out_x_        (col2_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[2]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                    .ccx_aclk_out (ccx_aclk_out[2]),
                    .ccx_bclk_out (ccx_bclk_out[2]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[1] ),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[1]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[1]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[1]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[1]),        // Templated
                    .src_pcx_data_a     (spc1_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col3_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac2_scanin),
                    .scan_out(pcx_mac2_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

// input from spc3
pcx_mbr_dp pcx_mac3(
                    // Outputs
                    .data_out_x_        (col3_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[3]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                    .ccx_aclk_out (ccx_aclk_out[3]),
                    .ccx_bclk_out (ccx_bclk_out[3]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[3]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[3]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[3]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[3]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[3]),        // Templated
                    .src_pcx_data_a     (spc3_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col4_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac3_scanin),
                    .scan_out(pcx_mac3_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en),
                    .tcu_pce_ov (tcu_pce_ov),
                    .ccx_aclk (ccx_aclk),
                    .ccx_bclk (ccx_bclk)
                    );


// input from spc5
pcx_mbr_dp pcx_mac4(
                    // Outputs
                    .data_out_x_        (col4_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[4]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                    .ccx_aclk_out (ccx_aclk_out[4]),
                    .ccx_bclk_out (ccx_bclk_out[4]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[5]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[5]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[5]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[5]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[5]),        // Templated
                    .src_pcx_data_a     (spc5_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col5_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac4_scanin),
                    .scan_out(pcx_mac4_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

// input from spc7
pcx_mbr_dp pcx_mac5(
                    // Outputs
                    .data_out_x_        (col5_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[5]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                    .ccx_aclk_out (ccx_aclk_out[5]),
                    .ccx_bclk_out (ccx_bclk_out[5]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[7]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[7]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[7]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[7]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[7]),        // Templated
                    .src_pcx_data_a     (spc7_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col6_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac5_scanin),
                    .scan_out(pcx_mac5_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[4]),
                    .tcu_pce_ov (tcu_pce_ov_out[4]),
                    .ccx_aclk (ccx_aclk_out[4]),
                    .ccx_bclk (ccx_bclk_out[4])
                    );


// input from spc4
pcx_mbr_dp pcx_mac6(
                    // Outputs
                    .data_out_x_        (col6_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[6]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                    .ccx_aclk_out (ccx_aclk_out[6]),
                    .ccx_bclk_out (ccx_bclk_out[6]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[4]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[4]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[4]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[4]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[4]),        // Templated
                    .src_pcx_data_a     (spc4_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col7_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac6_scanin),
                    .scan_out(pcx_mac6_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[5]),
                    .tcu_pce_ov (tcu_pce_ov_out[5]),
                    .ccx_aclk (ccx_aclk_out[5]),
                    .ccx_bclk (ccx_bclk_out[5])
                    );
 

/*
   pcx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc6
pcx_mar_dp pcx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[129:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out (ccx_aclk_out_7_unused),
                     .ccx_bclk_out (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[6]),        // Templated
                     .src_pcx_data_a    (spc6_pcx_data_a[129:0]), // Templated
                     .scan_in(pcx_mac7_scanin),
                     .scan_out(pcx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[6]),
                     .tcu_pce_ov (tcu_pce_ov_out[6]),
                     .ccx_aclk (ccx_aclk_out[6]),
                     .ccx_bclk (ccx_bclk_out[6])
                     );


assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

// fixscan start:
assign pcx_mac0_scanin           = scan_rep_out                  ;
assign pcx_mac1_scanin           = pcx_mac0_scanout         ;
assign pcx_mac2_scanin           = pcx_mac1_scanout         ;
assign pcx_mac3_scanin           = pcx_mac2_scanout         ;
assign pcx_mac4_scanin           = pcx_mac3_scanout         ;
assign pcx_mac5_scanin           = pcx_mac4_scanout         ;
assign pcx_mac6_scanin           = pcx_mac5_scanout         ;
assign pcx_mac7_scanin           = pcx_mac6_scanout         ;
assign scan_out                  = pcx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpsb_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsb_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsb_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpsb_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpsb_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsb_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsb_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = ccx_aclk;
//assign soclk = ccx_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsb_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpsb(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a, 
	spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a, 
	tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);

	output	[129:0]		pcx_scache_data_x_;
	input	[7:0]		arb_grant_l_a;
	input	[7:0]		arb_q0_holdbar_l_a;
	input	[7:0]		arb_qsel0_l_a;
	input	[7:0]		arb_qsel1_l_a;
	input	[7:0]		arb_shift_l_a;
	input	[7:0]		arb_grant_r_a;
	input	[7:0]		arb_q0_holdbar_r_a;
	input	[7:0]		arb_qsel0_r_a;
	input	[7:0]		arb_qsel1_r_a;
	input	[7:0]		arb_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			scan_in;
	output			scan_out;

	wire	[129:0]		all_ones;
	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:4]		arb_grant_r_a_rep;
	wire	[7:4]		arb_q0_holdbar_r_a_rep;
	wire	[7:4]		arb_qsel0_r_a_rep;
	wire	[7:4]		arb_qsel1_r_a_rep;
	wire	[7:4]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[129:0]		col0_data_x_;
	wire			tcu_scan_en_out_0_unused;
	wire			tcu_pce_ov_out_0_unused;
	wire			ccx_aclk_out_0_unused;
	wire			ccx_bclk_out_0_unused;
	wire			pcx_mac0_scanin;
	wire			pcx_mac0_scanout;
	wire	[6:1]		tcu_scan_en_out;
	wire	[6:1]		tcu_pce_ov_out;
	wire	[6:1]		ccx_aclk_out;
	wire	[6:1]		ccx_bclk_out;
	wire	[129:0]		col2_data_x_;
	wire			pcx_mac1_scanin;
	wire			pcx_mac1_scanout;
	wire	[129:0]		col3_data_x_;
	wire			pcx_mac2_scanin;
	wire			pcx_mac2_scanout;
	wire	[129:0]		col4_data_x_;
	wire			pcx_mac3_scanin;
	wire			pcx_mac3_scanout;
	wire	[129:0]		col5_data_x_;
	wire			pcx_mac4_scanin;
	wire			pcx_mac4_scanout;
	wire	[129:0]		col6_data_x_;
	wire			pcx_mac5_scanin;
	wire			pcx_mac5_scanout;
	wire	[129:0]		col7_data_x_;
	wire			pcx_mac6_scanin;
	wire			pcx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			pcx_mac7_scanin;
	wire			pcx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[3:0]		arb_grant_r_a_unused;
	wire	[3:0]		arb_q0_holdbar_r_a_unused;
	wire	[3:0]		arb_qsel0_r_a_unused;
	wire	[3:0]		arb_qsel1_r_a_unused;
	wire	[3:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign all_ones[129:0] = 130'h3ffffffffffffffffffffffffffffffff;
	assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0], 
		arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0], 
		arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0], 
		arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2], 
		arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2], 
		arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4], 
		arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
	assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4], 
		arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign pcx_mac0_scanin = scan_rep_out;
	assign pcx_mac1_scanin = pcx_mac0_scanout;
	assign pcx_mac2_scanin = pcx_mac1_scanout;
	assign pcx_mac3_scanin = pcx_mac2_scanout;
	assign pcx_mac4_scanin = pcx_mac3_scanout;
	assign pcx_mac5_scanin = pcx_mac4_scanout;
	assign pcx_mac6_scanin = pcx_mac5_scanout;
	assign pcx_mac7_scanin = pcx_mac6_scanout;
	assign scan_out = pcx_mac7_scanout;

	pcx_rep_dp pcx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	pcx_mbl_dp pcx_mac0(
		.data_out_x_			(col0_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_0_unused), 
		.ccx_aclk_out			(ccx_aclk_out_0_unused), 
		.ccx_bclk_out			(ccx_bclk_out_0_unused), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_pcx_data_a			(spc0_pcx_data_a[129:0]), 
		.data_prev_x_			(all_ones[129:0]), 
		.scan_in			(pcx_mac0_scanin), 
		.scan_out			(pcx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	pcx_mcl_dp pcx_mac1(
		.data_out_x_			(pcx_scache_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_pcx_data_a			(spc2_pcx_data_a[129:0]), 
		.data_crit_x_			(col2_data_x_[129:0]), 
		.data_ncrit_x_			(col0_data_x_[129:0]), 
		.scan_in			(pcx_mac1_scanin), 
		.scan_out			(pcx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	pcx_mbr_dp pcx_mac2(
		.data_out_x_			(col2_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_pcx_data_a			(spc1_pcx_data_a[129:0]), 
		.data_prev_x_			(col3_data_x_[129:0]), 
		.scan_in			(pcx_mac2_scanin), 
		.scan_out			(pcx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbr_dp pcx_mac3(
		.data_out_x_			(col3_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_pcx_data_a			(spc3_pcx_data_a[129:0]), 
		.data_prev_x_			(col4_data_x_[129:0]), 
		.scan_in			(pcx_mac3_scanin), 
		.scan_out			(pcx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	pcx_mbr_dp pcx_mac4(
		.data_out_x_			(col4_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_pcx_data_a			(spc5_pcx_data_a[129:0]), 
		.data_prev_x_			(col5_data_x_[129:0]), 
		.scan_in			(pcx_mac4_scanin), 
		.scan_out			(pcx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbr_dp pcx_mac5(
		.data_out_x_			(col5_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_pcx_data_a			(spc7_pcx_data_a[129:0]), 
		.data_prev_x_			(col6_data_x_[129:0]), 
		.scan_in			(pcx_mac5_scanin), 
		.scan_out			(pcx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	pcx_mbr_dp pcx_mac6(
		.data_out_x_			(col6_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[4]), 
		.arb_shift_a			(arb_shift_r_a_rep[4]), 
		.src_pcx_data_a			(spc4_pcx_data_a[129:0]), 
		.data_prev_x_			(col7_data_x_[129:0]), 
		.scan_in			(pcx_mac6_scanin), 
		.scan_out			(pcx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	pcx_mar_dp pcx_mac7(
		.data_out_x_			(col7_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[6]), 
		.arb_shift_a			(arb_shift_r_a[6]), 
		.src_pcx_data_a			(spc6_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac7_scanin), 
		.scan_out			(pcx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpsc.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpsc (
  pcx_scache_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_in, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:4] arb_grant_r_a_rep;
wire [7:4] arb_q0_holdbar_r_a_rep;
wire [7:4] arb_qsel0_r_a_rep;
wire [7:4] arb_qsel1_r_a_rep;
wire [7:4] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [129:0] col0_data_x_;
wire tcu_scan_en_out_0_unused;
wire tcu_pce_ov_out_0_unused;
wire ccx_aclk_out_0_unused;
wire ccx_bclk_out_0_unused;
wire pcx_mac0_scanin;
wire pcx_mac0_scanout;
wire [6:1] tcu_scan_en_out;
wire [6:1] tcu_pce_ov_out;
wire [6:1] ccx_aclk_out;
wire [6:1] ccx_bclk_out;
wire [129:0] col1_data_x_;
wire pcx_mac1_scanin;
wire pcx_mac1_scanout;
wire [129:0] col3_data_x_;
wire pcx_mac2_scanin;
wire pcx_mac2_scanout;
wire [129:0] col4_data_x_;
wire pcx_mac3_scanin;
wire pcx_mac3_scanout;
wire [129:0] col5_data_x_;
wire pcx_mac4_scanin;
wire pcx_mac4_scanout;
wire [129:0] col6_data_x_;
wire pcx_mac5_scanin;
wire pcx_mac5_scanout;
wire [129:0] col7_data_x_;
wire pcx_mac6_scanin;
wire pcx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire pcx_mac7_scanin;
wire pcx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [3:0] arb_grant_r_a_unused;
wire [3:0] arb_q0_holdbar_r_a_unused;
wire [3:0] arb_qsel0_r_a_unused;
wire [3:0] arb_qsel1_r_a_unused;
wire [3:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_scache_data_x_;     // From mac3 of pcx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb_grant_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_l_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_grant_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_r_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [129:0]           spc0_pcx_data_a;        // To mac0 of pcx_mar_dp.v
input [129:0]           spc1_pcx_data_a;        // To mac1 of pcx_mbr_dp.v
input [129:0]           spc2_pcx_data_a;        // To mac2 of pcx_mbr_dp.v
input [129:0]           spc3_pcx_data_a;        // To mac3 of pcx_mcr_dp.v
input [129:0]           spc4_pcx_data_a;        // To mac4 of pcx_mbl_dp.v
input [129:0]           spc5_pcx_data_a;        // To mac5 of pcx_mbl_dp.v
input [129:0]           spc6_pcx_data_a;        // To mac6 of pcx_mbl_dp.v
input [129:0]           spc7_pcx_data_a;        // To mac7 of pcx_mal_dp.v
// End of automatics
// globals
input tcu_scan_en ;
input           l2clk;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           scan_in;
output          scan_out;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 <-mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    al     bl      cl     br      br      br       br     ar
//                    |      
//                    buf  
//                    |    
//                    v    
//                 to sctag

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
                           arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
        arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
                       arb_qsel1_l_a[2],arb_shift_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
        arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
                       arb_qsel1_r_a[4],arb_shift_r_a[4]};

assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
        arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


/*
   pcx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from sp0
pcx_mal_dp pcx_mac0 ( 
                      // Outputs
                      .data_out_x_       (col0_data_x_[129:0]),   // Templated
                      .tcu_scan_en_out (tcu_scan_en_out_0_unused),
                      .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
                      .ccx_aclk_out (ccx_aclk_out_0_unused),
                      .ccx_bclk_out (ccx_bclk_out_0_unused),
                      // Inputs
                      .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                      .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                      .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                      .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                      .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                      .src_pcx_data_a    (spc0_pcx_data_a[129:0]), // Templated
                      .scan_in(pcx_mac0_scanin),
                      .scan_out(pcx_mac0_scanout),
                      .l2clk             (l2clk),                 // Templated
                      .tcu_scan_en (tcu_scan_en_out[1]),
                      .tcu_pce_ov (tcu_pce_ov_out[1]),
                      .ccx_aclk (ccx_aclk_out[1]),
                      .ccx_bclk (ccx_bclk_out[1])
                      );


/*
 pcx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk));
*/


// input from spc2
pcx_mbl_dp pcx_mac1(
                    // Outputs
                    .data_out_x_        (col1_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[1]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                    .ccx_aclk_out (ccx_aclk_out[1]),
                    .ccx_bclk_out (ccx_bclk_out[1]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[2]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[2]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[2]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[2]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[2]),        // Templated
                    .src_pcx_data_a     (spc2_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col0_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac1_scanin),
                    .scan_out(pcx_mac1_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[2]),
                    .tcu_pce_ov (tcu_pce_ov_out[2]),
                    .ccx_aclk (ccx_aclk_out[2]),
                    .ccx_bclk (ccx_bclk_out[2])
                    );


/*
   pcx_mcl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(pcx_scache_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/

// input from spc1
pcx_mcl_dp pcx_mac2(
                    // Outputs
                    .data_out_x_        (pcx_scache_data_x_[129:0]), // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[2]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                    .ccx_aclk_out (ccx_aclk_out[2]),
                    .ccx_bclk_out (ccx_bclk_out[2]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[1]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[1]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[1]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[1]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[1]),        // Templated
                    .src_pcx_data_a     (spc1_pcx_data_a[129:0]), // Templated
                    .data_crit_x_       (col3_data_x_[129:0]),   // Templated
                    .data_ncrit_x_      (col1_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac2_scanin),
                    .scan_out(pcx_mac2_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

/*
   pcx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a_rep[@]),
 .arb_qsel0_a(arb_qsel0_r_a_rep[@]),
 .arb_qsel1_a(arb_qsel1_r_a_rep[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a_rep[@]),
 .arb_shift_a(arb_shift_r_a_rep[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc3
pcx_mbr_dp pcx_mac3(
                    // Outputs
                    .data_out_x_        (col3_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[3]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                    .ccx_aclk_out (ccx_aclk_out[3]),
                    .ccx_bclk_out (ccx_bclk_out[3]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[3]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[3]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[3]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[3]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[3]),        // Templated
                    .src_pcx_data_a     (spc3_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col4_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac3_scanin),
                    .scan_out(pcx_mac3_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en),
                    .tcu_pce_ov (tcu_pce_ov),
                    .ccx_aclk (ccx_aclk),
                    .ccx_bclk (ccx_bclk)
                    );

// input from spc5
pcx_mbr_dp pcx_mac4(
                    // Outputs
                    .data_out_x_        (col4_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[4]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                    .ccx_aclk_out (ccx_aclk_out[4]),
                    .ccx_bclk_out (ccx_bclk_out[4]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[5]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[5]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[5]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[5]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[5]),        // Templated
                    .src_pcx_data_a     (spc5_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col5_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac4_scanin),
                    .scan_out(pcx_mac4_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

// input from spc7
pcx_mbr_dp pcx_mac5(
                    // Outputs
                    .data_out_x_        (col5_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[5]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                    .ccx_aclk_out (ccx_aclk_out[5]),
                    .ccx_bclk_out (ccx_bclk_out[5]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[7]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[7]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[7]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[7]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[7]),        // Templated
                    .src_pcx_data_a     (spc7_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col6_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac5_scanin),
                    .scan_out(pcx_mac5_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[4]),
                    .tcu_pce_ov (tcu_pce_ov_out[4]),
                    .ccx_aclk (ccx_aclk_out[4]),
                    .ccx_bclk (ccx_bclk_out[4])
                    );

// input from spc4
pcx_mbr_dp pcx_mac6(
                    // Outputs
                    .data_out_x_        (col6_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[6]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                    .ccx_aclk_out (ccx_aclk_out[6]),
                    .ccx_bclk_out (ccx_bclk_out[6]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[4]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[4]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[4]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[4]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[4]),        // Templated
                    .src_pcx_data_a     (spc4_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col7_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac6_scanin),
                    .scan_out(pcx_mac6_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[5]),
                    .tcu_pce_ov (tcu_pce_ov_out[5]),
                    .ccx_aclk (ccx_aclk_out[5]),
                    .ccx_bclk (ccx_bclk_out[5])
                    );

/*
   pcx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc6
pcx_mar_dp pcx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[129:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out (ccx_aclk_out_7_unused),
                     .ccx_bclk_out (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[6]),        // Templated
                     .src_pcx_data_a    (spc6_pcx_data_a[129:0]), // Templated
                     .scan_in(pcx_mac7_scanin),
                     .scan_out(pcx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[6]),
                     .tcu_pce_ov (tcu_pce_ov_out[6]),
                     .ccx_aclk (ccx_aclk_out[6]),
                     .ccx_bclk (ccx_bclk_out[6])
                     );


assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

// fixscan start:
assign pcx_mac0_scanin           = scan_rep_out                  ;
assign pcx_mac1_scanin           = pcx_mac0_scanout         ;
assign pcx_mac2_scanin           = pcx_mac1_scanout         ;
assign pcx_mac3_scanin           = pcx_mac2_scanout         ;
assign pcx_mac4_scanin           = pcx_mac3_scanout         ;
assign pcx_mac5_scanin           = pcx_mac4_scanout         ;
assign pcx_mac6_scanin           = pcx_mac5_scanout         ;
assign pcx_mac7_scanin           = pcx_mac6_scanout         ;
assign scan_out                  = pcx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpsc_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsc_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsc_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpsc_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpsc_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsc_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsc_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsc_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = ccx_aclk;
//assign soclk = ccx_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpsc(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a, 
	spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a, 
	tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);

	output	[129:0]		pcx_scache_data_x_;
	input	[7:0]		arb_grant_l_a;
	input	[7:0]		arb_q0_holdbar_l_a;
	input	[7:0]		arb_qsel0_l_a;
	input	[7:0]		arb_qsel1_l_a;
	input	[7:0]		arb_shift_l_a;
	input	[7:0]		arb_grant_r_a;
	input	[7:0]		arb_q0_holdbar_r_a;
	input	[7:0]		arb_qsel0_r_a;
	input	[7:0]		arb_qsel1_r_a;
	input	[7:0]		arb_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			scan_in;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:4]		arb_grant_r_a_rep;
	wire	[7:4]		arb_q0_holdbar_r_a_rep;
	wire	[7:4]		arb_qsel0_r_a_rep;
	wire	[7:4]		arb_qsel1_r_a_rep;
	wire	[7:4]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[129:0]		col0_data_x_;
	wire			tcu_scan_en_out_0_unused;
	wire			tcu_pce_ov_out_0_unused;
	wire			ccx_aclk_out_0_unused;
	wire			ccx_bclk_out_0_unused;
	wire			pcx_mac0_scanin;
	wire			pcx_mac0_scanout;
	wire	[6:1]		tcu_scan_en_out;
	wire	[6:1]		tcu_pce_ov_out;
	wire	[6:1]		ccx_aclk_out;
	wire	[6:1]		ccx_bclk_out;
	wire	[129:0]		col1_data_x_;
	wire			pcx_mac1_scanin;
	wire			pcx_mac1_scanout;
	wire	[129:0]		col3_data_x_;
	wire			pcx_mac2_scanin;
	wire			pcx_mac2_scanout;
	wire	[129:0]		col4_data_x_;
	wire			pcx_mac3_scanin;
	wire			pcx_mac3_scanout;
	wire	[129:0]		col5_data_x_;
	wire			pcx_mac4_scanin;
	wire			pcx_mac4_scanout;
	wire	[129:0]		col6_data_x_;
	wire			pcx_mac5_scanin;
	wire			pcx_mac5_scanout;
	wire	[129:0]		col7_data_x_;
	wire			pcx_mac6_scanin;
	wire			pcx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			pcx_mac7_scanin;
	wire			pcx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[3:0]		arb_grant_r_a_unused;
	wire	[3:0]		arb_q0_holdbar_r_a_unused;
	wire	[3:0]		arb_qsel0_r_a_unused;
	wire	[3:0]		arb_qsel1_r_a_unused;
	wire	[3:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0], 
		arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0], 
		arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0], 
		arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2], 
		arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2], 
		arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4], 
		arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
	assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4], 
		arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign pcx_mac0_scanin = scan_rep_out;
	assign pcx_mac1_scanin = pcx_mac0_scanout;
	assign pcx_mac2_scanin = pcx_mac1_scanout;
	assign pcx_mac3_scanin = pcx_mac2_scanout;
	assign pcx_mac4_scanin = pcx_mac3_scanout;
	assign pcx_mac5_scanin = pcx_mac4_scanout;
	assign pcx_mac6_scanin = pcx_mac5_scanout;
	assign pcx_mac7_scanin = pcx_mac6_scanout;
	assign scan_out = pcx_mac7_scanout;

	pcx_rep_dp pcx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	pcx_mal_dp pcx_mac0(
		.data_out_x_			(col0_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_0_unused), 
		.ccx_aclk_out			(ccx_aclk_out_0_unused), 
		.ccx_bclk_out			(ccx_bclk_out_0_unused), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_pcx_data_a			(spc0_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac0_scanin), 
		.scan_out			(pcx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	pcx_mbl_dp pcx_mac1(
		.data_out_x_			(col1_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_pcx_data_a			(spc2_pcx_data_a[129:0]), 
		.data_prev_x_			(col0_data_x_[129:0]), 
		.scan_in			(pcx_mac1_scanin), 
		.scan_out			(pcx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	pcx_mcl_dp pcx_mac2(
		.data_out_x_			(pcx_scache_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_pcx_data_a			(spc1_pcx_data_a[129:0]), 
		.data_crit_x_			(col3_data_x_[129:0]), 
		.data_ncrit_x_			(col1_data_x_[129:0]), 
		.scan_in			(pcx_mac2_scanin), 
		.scan_out			(pcx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbr_dp pcx_mac3(
		.data_out_x_			(col3_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_pcx_data_a			(spc3_pcx_data_a[129:0]), 
		.data_prev_x_			(col4_data_x_[129:0]), 
		.scan_in			(pcx_mac3_scanin), 
		.scan_out			(pcx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	pcx_mbr_dp pcx_mac4(
		.data_out_x_			(col4_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_pcx_data_a			(spc5_pcx_data_a[129:0]), 
		.data_prev_x_			(col5_data_x_[129:0]), 
		.scan_in			(pcx_mac4_scanin), 
		.scan_out			(pcx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbr_dp pcx_mac5(
		.data_out_x_			(col5_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_pcx_data_a			(spc7_pcx_data_a[129:0]), 
		.data_prev_x_			(col6_data_x_[129:0]), 
		.scan_in			(pcx_mac5_scanin), 
		.scan_out			(pcx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	pcx_mbr_dp pcx_mac6(
		.data_out_x_			(col6_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[4]), 
		.arb_shift_a			(arb_shift_r_a_rep[4]), 
		.src_pcx_data_a			(spc4_pcx_data_a[129:0]), 
		.data_prev_x_			(col7_data_x_[129:0]), 
		.scan_in			(pcx_mac6_scanin), 
		.scan_out			(pcx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	pcx_mar_dp pcx_mac7(
		.data_out_x_			(col7_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[6]), 
		.arb_shift_a			(arb_shift_r_a[6]), 
		.src_pcx_data_a			(spc6_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac7_scanin), 
		.scan_out			(pcx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpsd.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpsd (
  pcx_scache_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_in, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:4] arb_grant_r_a_rep;
wire [7:4] arb_q0_holdbar_r_a_rep;
wire [7:4] arb_qsel0_r_a_rep;
wire [7:4] arb_qsel1_r_a_rep;
wire [7:4] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [129:0] col0_data_x_;
wire tcu_scan_en_out_0_unused;
wire tcu_pce_ov_out_0_unused;
wire ccx_aclk_out_0_unused;
wire ccx_bclk_out_0_unused;
wire pcx_mac0_scanin;
wire pcx_mac0_scanout;
wire [6:1] tcu_scan_en_out;
wire [6:1] tcu_pce_ov_out;
wire [6:1] ccx_aclk_out;
wire [6:1] ccx_bclk_out;
wire [129:0] col1_data_x_;
wire pcx_mac1_scanin;
wire pcx_mac1_scanout;
wire [129:0] col2_data_x_;
wire pcx_mac2_scanin;
wire pcx_mac2_scanout;
wire [129:0] col4_data_x_;
wire pcx_mac3_scanin;
wire pcx_mac3_scanout;
wire [129:0] col5_data_x_;
wire pcx_mac4_scanin;
wire pcx_mac4_scanout;
wire [129:0] col6_data_x_;
wire pcx_mac5_scanin;
wire pcx_mac5_scanout;
wire [129:0] col7_data_x_;
wire pcx_mac6_scanin;
wire pcx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire pcx_mac7_scanin;
wire pcx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [3:0] arb_grant_r_a_unused;
wire [3:0] arb_q0_holdbar_r_a_unused;
wire [3:0] arb_qsel0_r_a_unused;
wire [3:0] arb_qsel1_r_a_unused;
wire [3:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_scache_data_x_;     // From mac3 of pcx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb_grant_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_l_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_grant_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_r_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [129:0]           spc0_pcx_data_a;        // To mac0 of pcx_mar_dp.v
input [129:0]           spc1_pcx_data_a;        // To mac1 of pcx_mbr_dp.v
input [129:0]           spc2_pcx_data_a;        // To mac2 of pcx_mbr_dp.v
input [129:0]           spc3_pcx_data_a;        // To mac3 of pcx_mcr_dp.v
input [129:0]           spc4_pcx_data_a;        // To mac4 of pcx_mbl_dp.v
input [129:0]           spc5_pcx_data_a;        // To mac5 of pcx_mbl_dp.v
input [129:0]           spc6_pcx_data_a;        // To mac6 of pcx_mbl_dp.v
input [129:0]           spc7_pcx_data_a;        // To mac7 of pcx_mal_dp.v
// End of automatics
// globals
input tcu_scan_en ;
input           l2clk;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           scan_in;
output          scan_out;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 <-mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    al     bl      bl     cl      br      br       br     ar
//                          |      
//                         buf  
//                          |    
//                          v    
//                        to sctag

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
                           arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
        arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
                       arb_qsel1_l_a[2],arb_shift_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
        arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
                       arb_qsel1_r_a[4],arb_shift_r_a[4]};

assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
        arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


/*
   pcx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from sp0
pcx_mal_dp pcx_mac0 ( 
                     // Outputs
                      .data_out_x_       (col0_data_x_[129:0]),   // Templated
                      .tcu_scan_en_out (tcu_scan_en_out_0_unused),
                      .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
                      .ccx_aclk_out (ccx_aclk_out_0_unused),
                      .ccx_bclk_out (ccx_bclk_out_0_unused),
                      // Inputs
                      .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                      .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                      .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                      .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                      .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                      .src_pcx_data_a    (spc0_pcx_data_a[129:0]), // Templated
                      .scan_in(pcx_mac0_scanin),
                      .scan_out(pcx_mac0_scanout),
                      .l2clk             (l2clk),                 // Templated
                      .tcu_scan_en (tcu_scan_en_out[1]),
                      .tcu_pce_ov (tcu_pce_ov_out[1]),
                      .ccx_aclk (ccx_aclk_out[1]),
                      .ccx_bclk (ccx_bclk_out[1])
                      );

/*
   pcx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk));
*/


// input from spc2
pcx_mbl_dp pcx_mac1(
                    // Outputs
                    .data_out_x_        (col1_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[1]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                    .ccx_aclk_out (ccx_aclk_out[1]),
                    .ccx_bclk_out (ccx_bclk_out[1]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[2]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[2]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[2]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[2]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[2]),        // Templated
                    .src_pcx_data_a     (spc2_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col0_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac1_scanin),
                    .scan_out(pcx_mac1_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[2]),
                    .tcu_pce_ov (tcu_pce_ov_out[2]),
                    .ccx_aclk (ccx_aclk_out[2]),
                    .ccx_bclk (ccx_bclk_out[2])
                    );

// input from spc1
pcx_mbl_dp pcx_mac2(
                    // Outputs
                    .data_out_x_        (col2_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[2]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                    .ccx_aclk_out (ccx_aclk_out[2]),
                    .ccx_bclk_out (ccx_bclk_out[2]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[1]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[1]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[1]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[1]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[1]),        // Templated
                    .src_pcx_data_a     (spc1_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col1_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac2_scanin),
                    .scan_out(pcx_mac2_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

/*
   pcx_mcl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(pcx_scache_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a_rep[@]),
 .arb_qsel0_a(arb_qsel0_l_a_rep[@]),
 .arb_qsel1_a(arb_qsel1_l_a_rep[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a_rep[@]),
 .arb_shift_a(arb_shift_l_a_rep[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_crit_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .data_ncrit_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/

// input from spc3
pcx_mcl_dp pcx_mac3(
                    // Outputs
                    .data_out_x_        (pcx_scache_data_x_[129:0]), // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[3]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                    .ccx_aclk_out (ccx_aclk_out[3]),
                    .ccx_bclk_out (ccx_bclk_out[3]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[3]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[3]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[3]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[3]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[3]),        // Templated
                    .src_pcx_data_a     (spc3_pcx_data_a[129:0]), // Templated
                    .data_crit_x_       (col4_data_x_[129:0]),   // Templated
                    .data_ncrit_x_      (col2_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac3_scanin),
                    .scan_out(pcx_mac3_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en),
                    .tcu_pce_ov (tcu_pce_ov),
                    .ccx_aclk (ccx_aclk),
                    .ccx_bclk (ccx_bclk)
                    );

/*
   pcx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a_rep[@]),
 .arb_qsel0_a(arb_qsel0_r_a_rep[@]),
 .arb_qsel1_a(arb_qsel1_r_a_rep[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a_rep[@]),
 .arb_shift_a(arb_shift_r_a_rep[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc5
pcx_mbr_dp pcx_mac4(
                    // Outputs
                    .data_out_x_        (col4_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[4]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                    .ccx_aclk_out (ccx_aclk_out[4]),
                    .ccx_bclk_out (ccx_bclk_out[4]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[5]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[5]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[5]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[5]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[5]),        // Templated
                    .src_pcx_data_a     (spc5_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col5_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac4_scanin),
                    .scan_out(pcx_mac4_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

// input from spc7
pcx_mbr_dp pcx_mac5(
                    // Outputs
                    .data_out_x_        (col5_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[5]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                    .ccx_aclk_out (ccx_aclk_out[5]),
                    .ccx_bclk_out (ccx_bclk_out[5]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[7]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[7]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[7]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[7]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[7]),        // Templated
                    .src_pcx_data_a     (spc7_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col6_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac5_scanin),
                    .scan_out(pcx_mac5_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[4]),
                    .tcu_pce_ov (tcu_pce_ov_out[4]),
                    .ccx_aclk (ccx_aclk_out[4]),
                    .ccx_bclk (ccx_bclk_out[4])
                    );

// input from spc4
pcx_mbr_dp pcx_mac6(
                    // Outputs
                    .data_out_x_        (col6_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[6]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                    .ccx_aclk_out (ccx_aclk_out[6]),
                    .ccx_bclk_out (ccx_bclk_out[6]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[4]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[4]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[4]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[4]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[4]),        // Templated
                    .src_pcx_data_a     (spc4_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col7_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac6_scanin),
                    .scan_out(pcx_mac6_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[5]),
                    .tcu_pce_ov (tcu_pce_ov_out[5]),
                    .ccx_aclk (ccx_aclk_out[5]),
                    .ccx_bclk (ccx_bclk_out[5])
                    );

/*
   pcx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc6
pcx_mar_dp pcx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[129:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out (ccx_aclk_out_7_unused),
                     .ccx_bclk_out (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[6]),        // Templated
                     .src_pcx_data_a    (spc6_pcx_data_a[129:0]), // Templated
                     .scan_in(pcx_mac7_scanin),
                     .scan_out(pcx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[6]),
                     .tcu_pce_ov (tcu_pce_ov_out[6]),
                     .ccx_aclk (ccx_aclk_out[6]),
                     .ccx_bclk (ccx_bclk_out[6])
                     );


assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];

// fixscan start:
assign pcx_mac0_scanin           = scan_rep_out                  ;
assign pcx_mac1_scanin           = pcx_mac0_scanout         ;
assign pcx_mac2_scanin           = pcx_mac1_scanout         ;
assign pcx_mac3_scanin           = pcx_mac2_scanout         ;
assign pcx_mac4_scanin           = pcx_mac3_scanout         ;
assign pcx_mac5_scanin           = pcx_mac4_scanout         ;
assign pcx_mac6_scanin           = pcx_mac5_scanout         ;
assign pcx_mac7_scanin           = pcx_mac6_scanout         ;
assign scan_out                  = pcx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpsd_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsd_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsd_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpsd_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpsd_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsd_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsd_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsd_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = ccx_aclk;
//assign soclk = ccx_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpsd(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a, 
	spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a, 
	tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);

	output	[129:0]		pcx_scache_data_x_;
	input	[7:0]		arb_grant_l_a;
	input	[7:0]		arb_q0_holdbar_l_a;
	input	[7:0]		arb_qsel0_l_a;
	input	[7:0]		arb_qsel1_l_a;
	input	[7:0]		arb_shift_l_a;
	input	[7:0]		arb_grant_r_a;
	input	[7:0]		arb_q0_holdbar_r_a;
	input	[7:0]		arb_qsel0_r_a;
	input	[7:0]		arb_qsel1_r_a;
	input	[7:0]		arb_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			scan_in;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:4]		arb_grant_r_a_rep;
	wire	[7:4]		arb_q0_holdbar_r_a_rep;
	wire	[7:4]		arb_qsel0_r_a_rep;
	wire	[7:4]		arb_qsel1_r_a_rep;
	wire	[7:4]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[129:0]		col0_data_x_;
	wire			tcu_scan_en_out_0_unused;
	wire			tcu_pce_ov_out_0_unused;
	wire			ccx_aclk_out_0_unused;
	wire			ccx_bclk_out_0_unused;
	wire			pcx_mac0_scanin;
	wire			pcx_mac0_scanout;
	wire	[6:1]		tcu_scan_en_out;
	wire	[6:1]		tcu_pce_ov_out;
	wire	[6:1]		ccx_aclk_out;
	wire	[6:1]		ccx_bclk_out;
	wire	[129:0]		col1_data_x_;
	wire			pcx_mac1_scanin;
	wire			pcx_mac1_scanout;
	wire	[129:0]		col2_data_x_;
	wire			pcx_mac2_scanin;
	wire			pcx_mac2_scanout;
	wire	[129:0]		col4_data_x_;
	wire			pcx_mac3_scanin;
	wire			pcx_mac3_scanout;
	wire	[129:0]		col5_data_x_;
	wire			pcx_mac4_scanin;
	wire			pcx_mac4_scanout;
	wire	[129:0]		col6_data_x_;
	wire			pcx_mac5_scanin;
	wire			pcx_mac5_scanout;
	wire	[129:0]		col7_data_x_;
	wire			pcx_mac6_scanin;
	wire			pcx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			pcx_mac7_scanin;
	wire			pcx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[3:0]		arb_grant_r_a_unused;
	wire	[3:0]		arb_q0_holdbar_r_a_unused;
	wire	[3:0]		arb_qsel0_r_a_unused;
	wire	[3:0]		arb_qsel1_r_a_unused;
	wire	[3:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0], 
		arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0], 
		arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0], 
		arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2], 
		arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2], 
		arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4], 
		arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
	assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4], 
		arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign pcx_mac0_scanin = scan_rep_out;
	assign pcx_mac1_scanin = pcx_mac0_scanout;
	assign pcx_mac2_scanin = pcx_mac1_scanout;
	assign pcx_mac3_scanin = pcx_mac2_scanout;
	assign pcx_mac4_scanin = pcx_mac3_scanout;
	assign pcx_mac5_scanin = pcx_mac4_scanout;
	assign pcx_mac6_scanin = pcx_mac5_scanout;
	assign pcx_mac7_scanin = pcx_mac6_scanout;
	assign scan_out = pcx_mac7_scanout;

	pcx_rep_dp pcx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	pcx_mal_dp pcx_mac0(
		.data_out_x_			(col0_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_0_unused), 
		.ccx_aclk_out			(ccx_aclk_out_0_unused), 
		.ccx_bclk_out			(ccx_bclk_out_0_unused), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_pcx_data_a			(spc0_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac0_scanin), 
		.scan_out			(pcx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	pcx_mbl_dp pcx_mac1(
		.data_out_x_			(col1_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_pcx_data_a			(spc2_pcx_data_a[129:0]), 
		.data_prev_x_			(col0_data_x_[129:0]), 
		.scan_in			(pcx_mac1_scanin), 
		.scan_out			(pcx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	pcx_mbl_dp pcx_mac2(
		.data_out_x_			(col2_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_pcx_data_a			(spc1_pcx_data_a[129:0]), 
		.data_prev_x_			(col1_data_x_[129:0]), 
		.scan_in			(pcx_mac2_scanin), 
		.scan_out			(pcx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mcl_dp pcx_mac3(
		.data_out_x_			(pcx_scache_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_pcx_data_a			(spc3_pcx_data_a[129:0]), 
		.data_crit_x_			(col4_data_x_[129:0]), 
		.data_ncrit_x_			(col2_data_x_[129:0]), 
		.scan_in			(pcx_mac3_scanin), 
		.scan_out			(pcx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	pcx_mbr_dp pcx_mac4(
		.data_out_x_			(col4_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_pcx_data_a			(spc5_pcx_data_a[129:0]), 
		.data_prev_x_			(col5_data_x_[129:0]), 
		.scan_in			(pcx_mac4_scanin), 
		.scan_out			(pcx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbr_dp pcx_mac5(
		.data_out_x_			(col5_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_pcx_data_a			(spc7_pcx_data_a[129:0]), 
		.data_prev_x_			(col6_data_x_[129:0]), 
		.scan_in			(pcx_mac5_scanin), 
		.scan_out			(pcx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	pcx_mbr_dp pcx_mac6(
		.data_out_x_			(col6_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[4]), 
		.arb_shift_a			(arb_shift_r_a_rep[4]), 
		.src_pcx_data_a			(spc4_pcx_data_a[129:0]), 
		.data_prev_x_			(col7_data_x_[129:0]), 
		.scan_in			(pcx_mac6_scanin), 
		.scan_out			(pcx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	pcx_mar_dp pcx_mac7(
		.data_out_x_			(col7_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[6]), 
		.arb_shift_a			(arb_shift_r_a[6]), 
		.src_pcx_data_a			(spc6_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac7_scanin), 
		.scan_out			(pcx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpse.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpse (
  pcx_scache_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_in, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:4] arb_grant_r_a_rep;
wire [7:4] arb_q0_holdbar_r_a_rep;
wire [7:4] arb_qsel0_r_a_rep;
wire [7:4] arb_qsel1_r_a_rep;
wire [7:4] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [129:0] col0_data_x_;
wire tcu_scan_en_out_0_unused;
wire tcu_pce_ov_out_0_unused;
wire ccx_aclk_out_0_unused;
wire ccx_bclk_out_0_unused;
wire pcx_mac0_scanin;
wire pcx_mac0_scanout;
wire [6:1] tcu_scan_en_out;
wire [6:1] tcu_pce_ov_out;
wire [6:1] ccx_aclk_out;
wire [6:1] ccx_bclk_out;
wire [129:0] col1_data_x_;
wire pcx_mac1_scanin;
wire pcx_mac1_scanout;
wire [129:0] col2_data_x_;
wire pcx_mac2_scanin;
wire pcx_mac2_scanout;
wire [129:0] col3_data_x_;
wire pcx_mac3_scanin;
wire pcx_mac3_scanout;
wire [129:0] col5_data_x_;
wire pcx_mac4_scanin;
wire pcx_mac4_scanout;
wire [129:0] col6_data_x_;
wire pcx_mac5_scanin;
wire pcx_mac5_scanout;
wire [129:0] col7_data_x_;
wire pcx_mac6_scanin;
wire pcx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire pcx_mac7_scanin;
wire pcx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [3:0] arb_grant_r_a_unused;
wire [3:0] arb_q0_holdbar_r_a_unused;
wire [3:0] arb_qsel0_r_a_unused;
wire [3:0] arb_qsel1_r_a_unused;
wire [3:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_scache_data_x_;     // From mac3 of pcx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb_grant_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_l_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_grant_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_r_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [129:0]           spc0_pcx_data_a;        // To mac0 of pcx_mar_dp.v
input [129:0]           spc1_pcx_data_a;        // To mac1 of pcx_mbr_dp.v
input [129:0]           spc2_pcx_data_a;        // To mac2 of pcx_mbr_dp.v
input [129:0]           spc3_pcx_data_a;        // To mac3 of pcx_mcr_dp.v
input [129:0]           spc4_pcx_data_a;        // To mac4 of pcx_mbl_dp.v
input [129:0]           spc5_pcx_data_a;        // To mac5 of pcx_mbl_dp.v
input [129:0]           spc6_pcx_data_a;        // To mac6 of pcx_mbl_dp.v
input [129:0]           spc7_pcx_data_a;        // To mac7 of pcx_mal_dp.v
// End of automatics
// globals
input tcu_scan_en ;
input           l2clk;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           scan_in;
output          scan_out;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    al     bl     bl     bl      cr      br       br     ar
//                                 |
//            ------buf------------
//            |
//            v
//         to sctag 

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
                           arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
        arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
                       arb_qsel1_l_a[2],arb_shift_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
        arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
                       arb_qsel1_r_a[4],arb_shift_r_a[4]};

assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
        arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


/*
   pcx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

//input from spc0
pcx_mal_dp pcx_mac0 ( 
                      // Outputs
                      .data_out_x_       (col0_data_x_[129:0]),   // Templated
                      .tcu_scan_en_out (tcu_scan_en_out_0_unused),
                      .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
                      .ccx_aclk_out (ccx_aclk_out_0_unused),
                      .ccx_bclk_out (ccx_bclk_out_0_unused),
                      // Inputs
                      .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                      .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                      .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                      .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                      .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                      .src_pcx_data_a    (spc0_pcx_data_a[129:0]), // Templated
                      .scan_in(pcx_mac0_scanin),
                      .scan_out(pcx_mac0_scanout),
                      .l2clk             (l2clk),                 // Templated
                      .tcu_scan_en (tcu_scan_en_out[1]),
                      .tcu_pce_ov (tcu_pce_ov_out[1]),
                      .ccx_aclk (ccx_aclk_out[1]),
                      .ccx_bclk (ccx_bclk_out[1])
                      );

/*
   pcx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk));
*/


//input from spc2
pcx_mbl_dp pcx_mac1(
                    // Outputs
                    .data_out_x_        (col1_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[1]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                    .ccx_aclk_out (ccx_aclk_out[1]),
                    .ccx_bclk_out (ccx_bclk_out[1]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[2]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[2]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[2]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[2]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[2]),        // Templated
                    .src_pcx_data_a     (spc2_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col0_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac1_scanin),
                    .scan_out(pcx_mac1_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[2]),
                    .tcu_pce_ov (tcu_pce_ov_out[2]),
                    .ccx_aclk (ccx_aclk_out[2]),
                    .ccx_bclk (ccx_bclk_out[2])
                    );

//input from spc1
pcx_mbl_dp pcx_mac2(
                    // Outputs
                    .data_out_x_        (col2_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[2]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                    .ccx_aclk_out (ccx_aclk_out[2]),
                    .ccx_bclk_out (ccx_bclk_out[2]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[1]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[1]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[1]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[1]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[1]),        // Templated
                    .src_pcx_data_a     (spc1_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col1_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac2_scanin),
                    .scan_out(pcx_mac2_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

//input from spc3
pcx_mbl_dp pcx_mac3(
                    // Outputs
                    .data_out_x_        (col3_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[3]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                    .ccx_aclk_out (ccx_aclk_out[3]),
                    .ccx_bclk_out (ccx_bclk_out[3]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[3]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[3]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[3]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[3]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[3]),        // Templated
                    .src_pcx_data_a     (spc3_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col2_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac3_scanin),
                    .scan_out(pcx_mac3_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en),
                    .tcu_pce_ov (tcu_pce_ov),
                    .ccx_aclk (ccx_aclk),
                    .ccx_bclk (ccx_bclk)
                    );
/*
   pcx_mcr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(pcx_scache_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_crit_x_(col@"(- @ 1)"_data_x_[129:0]),
 .data_ncrit_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/
//input from spc5
pcx_mcr_dp pcx_mac4(
                    // Outputs
                    .data_out_x_        (pcx_scache_data_x_[129:0]), // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[4]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                    .ccx_aclk_out (ccx_aclk_out[4]),
                    .ccx_bclk_out (ccx_bclk_out[4]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[5]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[5]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[5]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[5]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[5]),        // Templated
                    .src_pcx_data_a     (spc5_pcx_data_a[129:0]), // Templated
                    .data_crit_x_       (col3_data_x_[129:0]),   // Templated
                    .data_ncrit_x_      (col5_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac4_scanin),
                    .scan_out(pcx_mac4_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );
 
/*
   pcx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a_rep[129:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/


//input from spc7
pcx_mbr_dp pcx_mac5(
                    // Outputs
                    .data_out_x_        (col5_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[5]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                    .ccx_aclk_out (ccx_aclk_out[5]),
                    .ccx_bclk_out (ccx_bclk_out[5]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[7]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[7]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[7]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[7]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[7]),        // Templated
                    .src_pcx_data_a     (spc7_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col6_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac5_scanin),
                    .scan_out(pcx_mac5_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[4]),
                    .tcu_pce_ov (tcu_pce_ov_out[4]),
                    .ccx_aclk (ccx_aclk_out[4]),
                    .ccx_bclk (ccx_bclk_out[4])
                    );
 
//input from spc4
pcx_mbr_dp pcx_mac6(
                    // Outputs
                    .data_out_x_        (col6_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[6]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                    .ccx_aclk_out (ccx_aclk_out[6]),
                    .ccx_bclk_out (ccx_bclk_out[6]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[4]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[4]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[4]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[4]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[4]),        // Templated
                    .src_pcx_data_a     (spc4_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col7_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac6_scanin),
                    .scan_out(pcx_mac6_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[5]),
                    .tcu_pce_ov (tcu_pce_ov_out[5]),
                    .ccx_aclk (ccx_aclk_out[5]),
                    .ccx_bclk (ccx_bclk_out[5])
                    );
 

/*
   pcx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

//input from spc6
pcx_mar_dp pcx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[129:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out (ccx_aclk_out_7_unused),
                     .ccx_bclk_out (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[6]),        // Templated
                     .src_pcx_data_a    (spc6_pcx_data_a[129:0]), // Templated
                     .scan_in(pcx_mac7_scanin),
                     .scan_out(pcx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[6]),
                     .tcu_pce_ov (tcu_pce_ov_out[6]),
                     .ccx_aclk (ccx_aclk_out[6]),
                     .ccx_bclk (ccx_bclk_out[6])
                     );


assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];


// fixscan start:
assign pcx_mac0_scanin           = scan_rep_out                  ;
assign pcx_mac1_scanin           = pcx_mac0_scanout         ;
assign pcx_mac2_scanin           = pcx_mac1_scanout         ;
assign pcx_mac3_scanin           = pcx_mac2_scanout         ;
assign pcx_mac4_scanin           = pcx_mac3_scanout         ;
assign pcx_mac5_scanin           = pcx_mac4_scanout         ;
assign pcx_mac6_scanin           = pcx_mac5_scanout         ;
assign pcx_mac7_scanin           = pcx_mac6_scanout         ;
assign scan_out                  = pcx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpse_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpse_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpse_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpse_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpse_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpse_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpse_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpse_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = ccx_aclk;
//assign soclk = ccx_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpse(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a, 
	spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a, 
	tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);

	output	[129:0]		pcx_scache_data_x_;
	input	[7:0]		arb_grant_l_a;
	input	[7:0]		arb_q0_holdbar_l_a;
	input	[7:0]		arb_qsel0_l_a;
	input	[7:0]		arb_qsel1_l_a;
	input	[7:0]		arb_shift_l_a;
	input	[7:0]		arb_grant_r_a;
	input	[7:0]		arb_q0_holdbar_r_a;
	input	[7:0]		arb_qsel0_r_a;
	input	[7:0]		arb_qsel1_r_a;
	input	[7:0]		arb_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			scan_in;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:4]		arb_grant_r_a_rep;
	wire	[7:4]		arb_q0_holdbar_r_a_rep;
	wire	[7:4]		arb_qsel0_r_a_rep;
	wire	[7:4]		arb_qsel1_r_a_rep;
	wire	[7:4]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[129:0]		col0_data_x_;
	wire			tcu_scan_en_out_0_unused;
	wire			tcu_pce_ov_out_0_unused;
	wire			ccx_aclk_out_0_unused;
	wire			ccx_bclk_out_0_unused;
	wire			pcx_mac0_scanin;
	wire			pcx_mac0_scanout;
	wire	[6:1]		tcu_scan_en_out;
	wire	[6:1]		tcu_pce_ov_out;
	wire	[6:1]		ccx_aclk_out;
	wire	[6:1]		ccx_bclk_out;
	wire	[129:0]		col1_data_x_;
	wire			pcx_mac1_scanin;
	wire			pcx_mac1_scanout;
	wire	[129:0]		col2_data_x_;
	wire			pcx_mac2_scanin;
	wire			pcx_mac2_scanout;
	wire	[129:0]		col3_data_x_;
	wire			pcx_mac3_scanin;
	wire			pcx_mac3_scanout;
	wire	[129:0]		col5_data_x_;
	wire			pcx_mac4_scanin;
	wire			pcx_mac4_scanout;
	wire	[129:0]		col6_data_x_;
	wire			pcx_mac5_scanin;
	wire			pcx_mac5_scanout;
	wire	[129:0]		col7_data_x_;
	wire			pcx_mac6_scanin;
	wire			pcx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			pcx_mac7_scanin;
	wire			pcx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[3:0]		arb_grant_r_a_unused;
	wire	[3:0]		arb_q0_holdbar_r_a_unused;
	wire	[3:0]		arb_qsel0_r_a_unused;
	wire	[3:0]		arb_qsel1_r_a_unused;
	wire	[3:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0], 
		arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0], 
		arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0], 
		arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2], 
		arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2], 
		arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4], 
		arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
	assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4], 
		arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign pcx_mac0_scanin = scan_rep_out;
	assign pcx_mac1_scanin = pcx_mac0_scanout;
	assign pcx_mac2_scanin = pcx_mac1_scanout;
	assign pcx_mac3_scanin = pcx_mac2_scanout;
	assign pcx_mac4_scanin = pcx_mac3_scanout;
	assign pcx_mac5_scanin = pcx_mac4_scanout;
	assign pcx_mac6_scanin = pcx_mac5_scanout;
	assign pcx_mac7_scanin = pcx_mac6_scanout;
	assign scan_out = pcx_mac7_scanout;

	pcx_rep_dp pcx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	pcx_mal_dp pcx_mac0(
		.data_out_x_			(col0_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_0_unused), 
		.ccx_aclk_out			(ccx_aclk_out_0_unused), 
		.ccx_bclk_out			(ccx_bclk_out_0_unused), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_pcx_data_a			(spc0_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac0_scanin), 
		.scan_out			(pcx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	pcx_mbl_dp pcx_mac1(
		.data_out_x_			(col1_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_pcx_data_a			(spc2_pcx_data_a[129:0]), 
		.data_prev_x_			(col0_data_x_[129:0]), 
		.scan_in			(pcx_mac1_scanin), 
		.scan_out			(pcx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	pcx_mbl_dp pcx_mac2(
		.data_out_x_			(col2_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_pcx_data_a			(spc1_pcx_data_a[129:0]), 
		.data_prev_x_			(col1_data_x_[129:0]), 
		.scan_in			(pcx_mac2_scanin), 
		.scan_out			(pcx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbl_dp pcx_mac3(
		.data_out_x_			(col3_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_pcx_data_a			(spc3_pcx_data_a[129:0]), 
		.data_prev_x_			(col2_data_x_[129:0]), 
		.scan_in			(pcx_mac3_scanin), 
		.scan_out			(pcx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	pcx_mcr_dp pcx_mac4(
		.data_out_x_			(pcx_scache_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_pcx_data_a			(spc5_pcx_data_a[129:0]), 
		.data_crit_x_			(col3_data_x_[129:0]), 
		.data_ncrit_x_			(col5_data_x_[129:0]), 
		.scan_in			(pcx_mac4_scanin), 
		.scan_out			(pcx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbr_dp pcx_mac5(
		.data_out_x_			(col5_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_pcx_data_a			(spc7_pcx_data_a[129:0]), 
		.data_prev_x_			(col6_data_x_[129:0]), 
		.scan_in			(pcx_mac5_scanin), 
		.scan_out			(pcx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	pcx_mbr_dp pcx_mac6(
		.data_out_x_			(col6_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[4]), 
		.arb_shift_a			(arb_shift_r_a_rep[4]), 
		.src_pcx_data_a			(spc4_pcx_data_a[129:0]), 
		.data_prev_x_			(col7_data_x_[129:0]), 
		.scan_in			(pcx_mac6_scanin), 
		.scan_out			(pcx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	pcx_mar_dp pcx_mac7(
		.data_out_x_			(col7_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[6]), 
		.arb_shift_a			(arb_shift_r_a[6]), 
		.src_pcx_data_a			(spc6_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac7_scanin), 
		.scan_out			(pcx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpsf.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpsf (
  pcx_scache_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_in, 
  scan_out);
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:4] arb_grant_r_a_rep;
wire [7:4] arb_q0_holdbar_r_a_rep;
wire [7:4] arb_qsel0_r_a_rep;
wire [7:4] arb_qsel1_r_a_rep;
wire [7:4] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [129:0] col0_data_x_;
wire tcu_scan_en_out_0_unused;
wire tcu_pce_ov_out_0_unused;
wire ccx_aclk_out_0_unused;
wire ccx_bclk_out_0_unused;
wire pcx_mac0_scanin;
wire pcx_mac0_scanout;
wire [6:1] tcu_scan_en_out;
wire [6:1] tcu_pce_ov_out;
wire [6:1] ccx_aclk_out;
wire [6:1] ccx_bclk_out;
wire [129:0] col1_data_x_;
wire pcx_mac1_scanin;
wire pcx_mac1_scanout;
wire [129:0] col2_data_x_;
wire pcx_mac2_scanin;
wire pcx_mac2_scanout;
wire [129:0] col3_data_x_;
wire pcx_mac3_scanin;
wire pcx_mac3_scanout;
wire [129:0] col4_data_x_;
wire pcx_mac4_scanin;
wire pcx_mac4_scanout;
wire [129:0] col6_data_x_;
wire pcx_mac5_scanin;
wire pcx_mac5_scanout;
wire [129:0] col7_data_x_;
wire pcx_mac6_scanin;
wire pcx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire pcx_mac7_scanin;
wire pcx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [3:0] arb_grant_r_a_unused;
wire [3:0] arb_q0_holdbar_r_a_unused;
wire [3:0] arb_qsel0_r_a_unused;
wire [3:0] arb_qsel1_r_a_unused;
wire [3:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_scache_data_x_;     // From mac3 of pcx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb_grant_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_l_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_grant_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_r_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [129:0]           spc0_pcx_data_a;        // To mac0 of pcx_mar_dp.v
input [129:0]           spc1_pcx_data_a;        // To mac1 of pcx_mbr_dp.v
input [129:0]           spc2_pcx_data_a;        // To mac2 of pcx_mbr_dp.v
input [129:0]           spc3_pcx_data_a;        // To mac3 of pcx_mcr_dp.v
input [129:0]           spc4_pcx_data_a;        // To mac4 of pcx_mbl_dp.v
input [129:0]           spc5_pcx_data_a;        // To mac5 of pcx_mbl_dp.v
input [129:0]           spc6_pcx_data_a;        // To mac6 of pcx_mbl_dp.v
input [129:0]           spc7_pcx_data_a;        // To mac7 of pcx_mal_dp.v
// End of automatics
// globals
input tcu_scan_en ;
input           l2clk;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           scan_in;
output          scan_out;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 <- mac4 <- mac5 <- mac6 <- mac7 
//    al     bl     bl     bl      bl      cr       br     ar
//                                         |
//                     ------buf------------
//                     |
//                     v
//                    to sctag 

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
                           arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
        arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
                       arb_qsel1_l_a[2],arb_shift_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
        arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
                       arb_qsel1_r_a[4],arb_shift_r_a[4]};

assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
        arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


/*
   pcx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

//input from spc0
pcx_mal_dp pcx_mac0 ( 
                      // Outputs
                      .data_out_x_       (col0_data_x_[129:0]),   // Templated
                      .tcu_scan_en_out (tcu_scan_en_out_0_unused),
                      .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
                      .ccx_aclk_out (ccx_aclk_out_0_unused),
                      .ccx_bclk_out (ccx_bclk_out_0_unused),
                      // Inputs
                      .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                      .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                      .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                      .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                      .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                      .src_pcx_data_a    (spc0_pcx_data_a[129:0]), // Templated
                      .scan_in(pcx_mac0_scanin),
                      .scan_out(pcx_mac0_scanout),
                      .l2clk             (l2clk),                 // Templated
                      .tcu_scan_en (tcu_scan_en_out[1]),
                      .tcu_pce_ov (tcu_pce_ov_out[1]),
                      .ccx_aclk (ccx_aclk_out[1]),
                      .ccx_bclk (ccx_bclk_out[1])
                      );

/*
   pcx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk));
*/


//input from spc2
pcx_mbl_dp pcx_mac1(
                    // Outputs
                    .data_out_x_        (col1_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[1]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                    .ccx_aclk_out (ccx_aclk_out[1]),
                    .ccx_bclk_out (ccx_bclk_out[1]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[2]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[2]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[2]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[2]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[2]),        // Templated
                    .src_pcx_data_a     (spc2_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col0_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac1_scanin),
                    .scan_out(pcx_mac1_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[2]),
                    .tcu_pce_ov (tcu_pce_ov_out[2]),
                    .ccx_aclk (ccx_aclk_out[2]),
                    .ccx_bclk (ccx_bclk_out[2])
                    );

//input from spc1
pcx_mbl_dp pcx_mac2(
                    // Outputs
                    .data_out_x_        (col2_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[2]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                    .ccx_aclk_out (ccx_aclk_out[2]),
                    .ccx_bclk_out (ccx_bclk_out[2]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[1]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[1]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[1]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[1]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[1]),        // Templated
                    .src_pcx_data_a     (spc1_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col1_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac2_scanin),
                    .scan_out(pcx_mac2_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

//input from spc3
pcx_mbl_dp pcx_mac3(
                    // Outputs
                    .data_out_x_        (col3_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[3]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                    .ccx_aclk_out (ccx_aclk_out[3]),
                    .ccx_bclk_out (ccx_bclk_out[3]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[3]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[3]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[3]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[3]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[3]),        // Templated
                    .src_pcx_data_a     (spc3_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col2_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac3_scanin),
                    .scan_out(pcx_mac3_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en),
                    .tcu_pce_ov (tcu_pce_ov),
                    .ccx_aclk (ccx_aclk),
                    .ccx_bclk (ccx_bclk)
                    );

//input from spc5
pcx_mbl_dp pcx_mac4(
                    // Outputs
                    .data_out_x_        (col4_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[4]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                    .ccx_aclk_out (ccx_aclk_out[4]),
                    .ccx_bclk_out (ccx_bclk_out[4]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[5]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[5]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[5]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[5]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[5]),        // Templated
                    .src_pcx_data_a     (spc5_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col3_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac4_scanin),
                    .scan_out(pcx_mac4_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );

/*
   pcx_mcr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(pcx_scache_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_crit_x_(col@"(- @ 1)"_data_x_[129:0]),
 .data_ncrit_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/
//input from spc7
pcx_mcr_dp pcx_mac5(
                    // Outputs
                    .data_out_x_        (pcx_scache_data_x_[129:0]), // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[5]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                    .ccx_aclk_out (ccx_aclk_out[5]),
                    .ccx_bclk_out (ccx_bclk_out[5]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[7]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[7]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[7]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[7]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[7]),        // Templated
                    .src_pcx_data_a     (spc7_pcx_data_a[129:0]), // Templated
                    .data_crit_x_       (col4_data_x_[129:0]),   // Templated
                    .data_ncrit_x_      (col6_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac5_scanin),
                    .scan_out(pcx_mac5_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[4]),
                    .tcu_pce_ov (tcu_pce_ov_out[4]),
                    .ccx_aclk (ccx_aclk_out[4]),
                    .ccx_bclk (ccx_bclk_out[4])
                    );

 
/*
   pcx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/


//input from spc4
pcx_mbr_dp pcx_mac6(
                    // Outputs
                    .data_out_x_        (col6_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[6]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                    .ccx_aclk_out (ccx_aclk_out[6]),
                    .ccx_bclk_out (ccx_bclk_out[6]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[4]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[4]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[4]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[4]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[4]),        // Templated
                    .src_pcx_data_a     (spc4_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col7_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac6_scanin),
                    .scan_out(pcx_mac6_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[5]),
                    .tcu_pce_ov (tcu_pce_ov_out[5]),
                    .ccx_aclk (ccx_aclk_out[5]),
                    .ccx_bclk (ccx_bclk_out[5])
                    );
 
 
/*
   pcx_mar_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

//input from spc6
pcx_mar_dp pcx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[129:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out (ccx_aclk_out_7_unused),
                     .ccx_bclk_out (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[6]),        // Templated
                     .src_pcx_data_a    (spc6_pcx_data_a[129:0]), // Templated
                     .scan_in(pcx_mac7_scanin),
                     .scan_out(pcx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[6]),
                     .tcu_pce_ov (tcu_pce_ov_out[6]),
                     .ccx_aclk (ccx_aclk_out[6]),
                     .ccx_bclk (ccx_bclk_out[6])
                     );

assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];


// fixscan start:
assign pcx_mac0_scanin           = scan_rep_out                  ;
assign pcx_mac1_scanin           = pcx_mac0_scanout         ;
assign pcx_mac2_scanin           = pcx_mac1_scanout         ;
assign pcx_mac3_scanin           = pcx_mac2_scanout         ;
assign pcx_mac4_scanin           = pcx_mac3_scanout         ;
assign pcx_mac5_scanin           = pcx_mac4_scanout         ;
assign pcx_mac6_scanin           = pcx_mac5_scanout         ;
assign pcx_mac7_scanin           = pcx_mac6_scanout         ;
assign scan_out                  = pcx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpsf_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsf_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsf_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpsf_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpsf_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsf_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsf_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsf_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = ccx_aclk;
//assign soclk = ccx_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpsf(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a, 
	spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a, 
	tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);

	output	[129:0]		pcx_scache_data_x_;
	input	[7:0]		arb_grant_l_a;
	input	[7:0]		arb_q0_holdbar_l_a;
	input	[7:0]		arb_qsel0_l_a;
	input	[7:0]		arb_qsel1_l_a;
	input	[7:0]		arb_shift_l_a;
	input	[7:0]		arb_grant_r_a;
	input	[7:0]		arb_q0_holdbar_r_a;
	input	[7:0]		arb_qsel0_r_a;
	input	[7:0]		arb_qsel1_r_a;
	input	[7:0]		arb_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			scan_in;
	output			scan_out;

	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:4]		arb_grant_r_a_rep;
	wire	[7:4]		arb_q0_holdbar_r_a_rep;
	wire	[7:4]		arb_qsel0_r_a_rep;
	wire	[7:4]		arb_qsel1_r_a_rep;
	wire	[7:4]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[129:0]		col0_data_x_;
	wire			tcu_scan_en_out_0_unused;
	wire			tcu_pce_ov_out_0_unused;
	wire			ccx_aclk_out_0_unused;
	wire			ccx_bclk_out_0_unused;
	wire			pcx_mac0_scanin;
	wire			pcx_mac0_scanout;
	wire	[6:1]		tcu_scan_en_out;
	wire	[6:1]		tcu_pce_ov_out;
	wire	[6:1]		ccx_aclk_out;
	wire	[6:1]		ccx_bclk_out;
	wire	[129:0]		col1_data_x_;
	wire			pcx_mac1_scanin;
	wire			pcx_mac1_scanout;
	wire	[129:0]		col2_data_x_;
	wire			pcx_mac2_scanin;
	wire			pcx_mac2_scanout;
	wire	[129:0]		col3_data_x_;
	wire			pcx_mac3_scanin;
	wire			pcx_mac3_scanout;
	wire	[129:0]		col4_data_x_;
	wire			pcx_mac4_scanin;
	wire			pcx_mac4_scanout;
	wire	[129:0]		col6_data_x_;
	wire			pcx_mac5_scanin;
	wire			pcx_mac5_scanout;
	wire	[129:0]		col7_data_x_;
	wire			pcx_mac6_scanin;
	wire			pcx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			pcx_mac7_scanin;
	wire			pcx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[3:0]		arb_grant_r_a_unused;
	wire	[3:0]		arb_q0_holdbar_r_a_unused;
	wire	[3:0]		arb_qsel0_r_a_unused;
	wire	[3:0]		arb_qsel1_r_a_unused;
	wire	[3:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0], 
		arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0], 
		arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0], 
		arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2], 
		arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2], 
		arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4], 
		arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
	assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4], 
		arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign pcx_mac0_scanin = scan_rep_out;
	assign pcx_mac1_scanin = pcx_mac0_scanout;
	assign pcx_mac2_scanin = pcx_mac1_scanout;
	assign pcx_mac3_scanin = pcx_mac2_scanout;
	assign pcx_mac4_scanin = pcx_mac3_scanout;
	assign pcx_mac5_scanin = pcx_mac4_scanout;
	assign pcx_mac6_scanin = pcx_mac5_scanout;
	assign pcx_mac7_scanin = pcx_mac6_scanout;
	assign scan_out = pcx_mac7_scanout;

	pcx_rep_dp pcx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	pcx_mal_dp pcx_mac0(
		.data_out_x_			(col0_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_0_unused), 
		.ccx_aclk_out			(ccx_aclk_out_0_unused), 
		.ccx_bclk_out			(ccx_bclk_out_0_unused), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_pcx_data_a			(spc0_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac0_scanin), 
		.scan_out			(pcx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	pcx_mbl_dp pcx_mac1(
		.data_out_x_			(col1_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_pcx_data_a			(spc2_pcx_data_a[129:0]), 
		.data_prev_x_			(col0_data_x_[129:0]), 
		.scan_in			(pcx_mac1_scanin), 
		.scan_out			(pcx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	pcx_mbl_dp pcx_mac2(
		.data_out_x_			(col2_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_pcx_data_a			(spc1_pcx_data_a[129:0]), 
		.data_prev_x_			(col1_data_x_[129:0]), 
		.scan_in			(pcx_mac2_scanin), 
		.scan_out			(pcx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbl_dp pcx_mac3(
		.data_out_x_			(col3_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_pcx_data_a			(spc3_pcx_data_a[129:0]), 
		.data_prev_x_			(col2_data_x_[129:0]), 
		.scan_in			(pcx_mac3_scanin), 
		.scan_out			(pcx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	pcx_mbl_dp pcx_mac4(
		.data_out_x_			(col4_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_pcx_data_a			(spc5_pcx_data_a[129:0]), 
		.data_prev_x_			(col3_data_x_[129:0]), 
		.scan_in			(pcx_mac4_scanin), 
		.scan_out			(pcx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mcr_dp pcx_mac5(
		.data_out_x_			(pcx_scache_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_pcx_data_a			(spc7_pcx_data_a[129:0]), 
		.data_crit_x_			(col4_data_x_[129:0]), 
		.data_ncrit_x_			(col6_data_x_[129:0]), 
		.scan_in			(pcx_mac5_scanin), 
		.scan_out			(pcx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	pcx_mbr_dp pcx_mac6(
		.data_out_x_			(col6_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[4]), 
		.arb_shift_a			(arb_shift_r_a_rep[4]), 
		.src_pcx_data_a			(spc4_pcx_data_a[129:0]), 
		.data_prev_x_			(col7_data_x_[129:0]), 
		.scan_in			(pcx_mac6_scanin), 
		.scan_out			(pcx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	pcx_mar_dp pcx_mac7(
		.data_out_x_			(col7_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[6]), 
		.arb_shift_a			(arb_shift_r_a[6]), 
		.src_pcx_data_a			(spc6_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac7_scanin), 
		.scan_out			(pcx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpsg.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpsg (
  pcx_scache_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_in, 
  scan_out);
wire [129:0] all_ones;
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:4] arb_grant_r_a_rep;
wire [7:4] arb_q0_holdbar_r_a_rep;
wire [7:4] arb_qsel0_r_a_rep;
wire [7:4] arb_qsel1_r_a_rep;
wire [7:4] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [129:0] col0_data_x_;
wire tcu_scan_en_out_0_unused;
wire tcu_pce_ov_out_0_unused;
wire ccx_aclk_out_0_unused;
wire ccx_bclk_out_0_unused;
wire pcx_mac0_scanin;
wire pcx_mac0_scanout;
wire [6:1] tcu_scan_en_out;
wire [6:1] tcu_pce_ov_out;
wire [6:1] ccx_aclk_out;
wire [6:1] ccx_bclk_out;
wire [129:0] col1_data_x_;
wire pcx_mac1_scanin;
wire pcx_mac1_scanout;
wire [129:0] col2_data_x_;
wire pcx_mac2_scanin;
wire pcx_mac2_scanout;
wire [129:0] col3_data_x_;
wire pcx_mac3_scanin;
wire pcx_mac3_scanout;
wire [129:0] col4_data_x_;
wire pcx_mac4_scanin;
wire pcx_mac4_scanout;
wire [129:0] col5_data_x_;
wire pcx_mac5_scanin;
wire pcx_mac5_scanout;
wire [129:0] col7_data_x_;
wire pcx_mac6_scanin;
wire pcx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire pcx_mac7_scanin;
wire pcx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [3:0] arb_grant_r_a_unused;
wire [3:0] arb_q0_holdbar_r_a_unused;
wire [3:0] arb_qsel0_r_a_unused;
wire [3:0] arb_qsel1_r_a_unused;
wire [3:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_scache_data_x_;     // From mac3 of pcx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb_grant_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_l_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_grant_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_r_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [129:0]           spc0_pcx_data_a;        // To mac0 of pcx_mar_dp.v
input [129:0]           spc1_pcx_data_a;        // To mac1 of pcx_mbr_dp.v
input [129:0]           spc2_pcx_data_a;        // To mac2 of pcx_mbr_dp.v
input [129:0]           spc3_pcx_data_a;        // To mac3 of pcx_mcr_dp.v
input [129:0]           spc4_pcx_data_a;        // To mac4 of pcx_mbl_dp.v
input [129:0]           spc5_pcx_data_a;        // To mac5 of pcx_mbl_dp.v
input [129:0]           spc6_pcx_data_a;        // To mac6 of pcx_mbl_dp.v
input [129:0]           spc7_pcx_data_a;        // To mac7 of pcx_mal_dp.v
// End of automatics
// globals
input tcu_scan_en ;
input           l2clk;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           scan_in;
output          scan_out;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 -> mac4 -> mac5 <- mac6 <- mac7 
//    al     bl     bl     bl      bl      bl        cr     br
//                                                   |
//            ------buf------------------------------
//            |
//            v
//         to sctag 

assign all_ones[129:0] = 130'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
                           arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
        arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
                       arb_qsel1_l_a[2],arb_shift_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
        arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
                       arb_qsel1_r_a[4],arb_shift_r_a[4]};

assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
        arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


/*
   pcx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc0
pcx_mal_dp pcx_mac0 ( 
                      // Outputs
                      .data_out_x_       (col0_data_x_[129:0]),   // Templated
                      .tcu_scan_en_out (tcu_scan_en_out_0_unused),
                      .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
                      .ccx_aclk_out (ccx_aclk_out_0_unused),
                      .ccx_bclk_out (ccx_bclk_out_0_unused),
                      // Inputs
                      .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                      .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                      .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                      .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                      .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                      .src_pcx_data_a    (spc0_pcx_data_a[129:0]), // Templated
                      .scan_in(pcx_mac0_scanin),
                      .scan_out(pcx_mac0_scanout),
                      .l2clk             (l2clk),                 // Templated
                      .tcu_scan_en (tcu_scan_en_out[1]),
                      .tcu_pce_ov (tcu_pce_ov_out[1]),
                      .ccx_aclk (ccx_aclk_out[1]),
                      .ccx_bclk (ccx_bclk_out[1])
                      );

/*
   pcx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk));
*/


// input from spc2
pcx_mbl_dp pcx_mac1(
                    // Outputs
                    .data_out_x_        (col1_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[1]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                    .ccx_aclk_out (ccx_aclk_out[1]),
                    .ccx_bclk_out (ccx_bclk_out[1]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[2]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[2]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[2]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[2]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[2]),        // Templated
                    .src_pcx_data_a     (spc2_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col0_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac1_scanin),
                    .scan_out(pcx_mac1_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[2]),
                    .tcu_pce_ov (tcu_pce_ov_out[2]),
                    .ccx_aclk (ccx_aclk_out[2]),
                    .ccx_bclk (ccx_bclk_out[2])
                    );


// input from spc1
pcx_mbl_dp pcx_mac2(
                    // Outputs
                    .data_out_x_        (col2_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[2]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                    .ccx_aclk_out (ccx_aclk_out[2]),
                    .ccx_bclk_out (ccx_bclk_out[2]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[1]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[1]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[1]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[1]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[1]),        // Templated
                    .src_pcx_data_a     (spc1_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col1_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac2_scanin),
                    .scan_out(pcx_mac2_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );
 

// input from spc3
pcx_mbl_dp pcx_mac3(
                    // Outputs
                    .data_out_x_        (col3_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[3]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                    .ccx_aclk_out (ccx_aclk_out[3]),
                    .ccx_bclk_out (ccx_bclk_out[3]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[3]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[3]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[3]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[3]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[3]),        // Templated
                    .src_pcx_data_a     (spc3_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col2_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac3_scanin),
                    .scan_out(pcx_mac3_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en),
                    .tcu_pce_ov (tcu_pce_ov),
                    .ccx_aclk (ccx_aclk),
                    .ccx_bclk (ccx_bclk)
                    );

// input from spc5
pcx_mbl_dp pcx_mac4(
                    // Outputs
                    .data_out_x_        (col4_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[4]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                    .ccx_aclk_out (ccx_aclk_out[4]),
                    .ccx_bclk_out (ccx_bclk_out[4]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[5]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[5]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[5]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[5]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[5]),        // Templated
                    .src_pcx_data_a     (spc5_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col3_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac4_scanin),
                    .scan_out(pcx_mac4_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );


// input from spc7
pcx_mbl_dp pcx_mac5(
                    // Outputs
                    .data_out_x_        (col5_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[5]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                    .ccx_aclk_out (ccx_aclk_out[5]),
                    .ccx_bclk_out (ccx_bclk_out[5]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[7]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[7]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[7]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[7]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[7]),        // Templated
                    .src_pcx_data_a     (spc7_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col4_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac5_scanin),
                    .scan_out(pcx_mac5_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[4]),
                    .tcu_pce_ov (tcu_pce_ov_out[4]),
                    .ccx_aclk (ccx_aclk_out[4]),
                    .ccx_bclk (ccx_bclk_out[4])
                    );


/*
   pcx_mcr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(pcx_scache_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_crit_x_(col@"(- @ 1)"_data_x_[129:0]),
 .data_ncrit_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/
// input from spc4
pcx_mcr_dp pcx_mac6(
                    // Outputs
                    .data_out_x_        (pcx_scache_data_x_[129:0]), // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[6]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                    .ccx_aclk_out (ccx_aclk_out[6]),
                    .ccx_bclk_out (ccx_bclk_out[6]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[4]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[4]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[4]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[4]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[4]),        // Templated
                    .src_pcx_data_a     (spc4_pcx_data_a[129:0]), // Templated
                    .data_crit_x_       (col5_data_x_[129:0]),   // Templated
                    .data_ncrit_x_      (col7_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac6_scanin),
                    .scan_out(pcx_mac6_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[5]),
                    .tcu_pce_ov (tcu_pce_ov_out[5]),
                    .ccx_aclk (ccx_aclk_out[5]),
                    .ccx_bclk (ccx_bclk_out[5])
                    );
 
/*
   pcx_mbr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// input from spc6
pcx_mbr_dp pcx_mac7 (
                     // Outputs
                     .data_out_x_       (col7_data_x_[129:0]),   // Templated
                     .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                     .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                     .ccx_aclk_out (ccx_aclk_out_7_unused),
                     .ccx_bclk_out (ccx_bclk_out_7_unused),
                     // Inputs
                     .arb_grant_a       (arb_grant_r_a[6]),        // Templated
                     .arb_qsel0_a       (arb_qsel0_r_a[6]),        // Templated
                     .arb_qsel1_a       (arb_qsel1_r_a[6]),        // Templated
                     .arb_q0_holdbar_a  (arb_q0_holdbar_r_a[6]),   // Templated
                     .arb_shift_a       (arb_shift_r_a[6]),        // Templated
                     .src_pcx_data_a    (spc6_pcx_data_a[129:0]), // Templated
                     .data_prev_x_      (all_ones[129:0]),   // Templated
                     .scan_in(pcx_mac7_scanin),
                     .scan_out(pcx_mac7_scanout),
                     .l2clk             (l2clk),                 // Templated
                     .tcu_scan_en (tcu_scan_en_out[6]),
                     .tcu_pce_ov (tcu_pce_ov_out[6]),
                     .ccx_aclk (ccx_aclk_out[6]),
                     .ccx_bclk (ccx_bclk_out[6])
                     );


assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];


// fixscan start:
assign pcx_mac0_scanin           = scan_rep_out                  ;
assign pcx_mac1_scanin           = pcx_mac0_scanout         ;
assign pcx_mac2_scanin           = pcx_mac1_scanout         ;
assign pcx_mac3_scanin           = pcx_mac2_scanout         ;
assign pcx_mac4_scanin           = pcx_mac3_scanout         ;
assign pcx_mac5_scanin           = pcx_mac4_scanout         ;
assign pcx_mac6_scanin           = pcx_mac5_scanout         ;
assign pcx_mac7_scanin           = pcx_mac6_scanout         ;
assign scan_out                  = pcx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpsg_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsg_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsg_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpsg_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpsg_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsg_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsg_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsg_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpsg(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a, 
	spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a, 
	tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);

	output	[129:0]		pcx_scache_data_x_;
	input	[7:0]		arb_grant_l_a;
	input	[7:0]		arb_q0_holdbar_l_a;
	input	[7:0]		arb_qsel0_l_a;
	input	[7:0]		arb_qsel1_l_a;
	input	[7:0]		arb_shift_l_a;
	input	[7:0]		arb_grant_r_a;
	input	[7:0]		arb_q0_holdbar_r_a;
	input	[7:0]		arb_qsel0_r_a;
	input	[7:0]		arb_qsel1_r_a;
	input	[7:0]		arb_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			scan_in;
	output			scan_out;

	wire	[129:0]		all_ones;
	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:4]		arb_grant_r_a_rep;
	wire	[7:4]		arb_q0_holdbar_r_a_rep;
	wire	[7:4]		arb_qsel0_r_a_rep;
	wire	[7:4]		arb_qsel1_r_a_rep;
	wire	[7:4]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[129:0]		col0_data_x_;
	wire			tcu_scan_en_out_0_unused;
	wire			tcu_pce_ov_out_0_unused;
	wire			ccx_aclk_out_0_unused;
	wire			ccx_bclk_out_0_unused;
	wire			pcx_mac0_scanin;
	wire			pcx_mac0_scanout;
	wire	[6:1]		tcu_scan_en_out;
	wire	[6:1]		tcu_pce_ov_out;
	wire	[6:1]		ccx_aclk_out;
	wire	[6:1]		ccx_bclk_out;
	wire	[129:0]		col1_data_x_;
	wire			pcx_mac1_scanin;
	wire			pcx_mac1_scanout;
	wire	[129:0]		col2_data_x_;
	wire			pcx_mac2_scanin;
	wire			pcx_mac2_scanout;
	wire	[129:0]		col3_data_x_;
	wire			pcx_mac3_scanin;
	wire			pcx_mac3_scanout;
	wire	[129:0]		col4_data_x_;
	wire			pcx_mac4_scanin;
	wire			pcx_mac4_scanout;
	wire	[129:0]		col5_data_x_;
	wire			pcx_mac5_scanin;
	wire			pcx_mac5_scanout;
	wire	[129:0]		col7_data_x_;
	wire			pcx_mac6_scanin;
	wire			pcx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			pcx_mac7_scanin;
	wire			pcx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[3:0]		arb_grant_r_a_unused;
	wire	[3:0]		arb_q0_holdbar_r_a_unused;
	wire	[3:0]		arb_qsel0_r_a_unused;
	wire	[3:0]		arb_qsel1_r_a_unused;
	wire	[3:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign all_ones[129:0] = 130'h3ffffffffffffffffffffffffffffffff;
	assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0], 
		arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0], 
		arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0], 
		arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2], 
		arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2], 
		arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4], 
		arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
	assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4], 
		arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign pcx_mac0_scanin = scan_rep_out;
	assign pcx_mac1_scanin = pcx_mac0_scanout;
	assign pcx_mac2_scanin = pcx_mac1_scanout;
	assign pcx_mac3_scanin = pcx_mac2_scanout;
	assign pcx_mac4_scanin = pcx_mac3_scanout;
	assign pcx_mac5_scanin = pcx_mac4_scanout;
	assign pcx_mac6_scanin = pcx_mac5_scanout;
	assign pcx_mac7_scanin = pcx_mac6_scanout;
	assign scan_out = pcx_mac7_scanout;

	pcx_rep_dp pcx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	pcx_mal_dp pcx_mac0(
		.data_out_x_			(col0_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_0_unused), 
		.ccx_aclk_out			(ccx_aclk_out_0_unused), 
		.ccx_bclk_out			(ccx_bclk_out_0_unused), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_pcx_data_a			(spc0_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac0_scanin), 
		.scan_out			(pcx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	pcx_mbl_dp pcx_mac1(
		.data_out_x_			(col1_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_pcx_data_a			(spc2_pcx_data_a[129:0]), 
		.data_prev_x_			(col0_data_x_[129:0]), 
		.scan_in			(pcx_mac1_scanin), 
		.scan_out			(pcx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	pcx_mbl_dp pcx_mac2(
		.data_out_x_			(col2_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_pcx_data_a			(spc1_pcx_data_a[129:0]), 
		.data_prev_x_			(col1_data_x_[129:0]), 
		.scan_in			(pcx_mac2_scanin), 
		.scan_out			(pcx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbl_dp pcx_mac3(
		.data_out_x_			(col3_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_pcx_data_a			(spc3_pcx_data_a[129:0]), 
		.data_prev_x_			(col2_data_x_[129:0]), 
		.scan_in			(pcx_mac3_scanin), 
		.scan_out			(pcx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	pcx_mbl_dp pcx_mac4(
		.data_out_x_			(col4_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_pcx_data_a			(spc5_pcx_data_a[129:0]), 
		.data_prev_x_			(col3_data_x_[129:0]), 
		.scan_in			(pcx_mac4_scanin), 
		.scan_out			(pcx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbl_dp pcx_mac5(
		.data_out_x_			(col5_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_pcx_data_a			(spc7_pcx_data_a[129:0]), 
		.data_prev_x_			(col4_data_x_[129:0]), 
		.scan_in			(pcx_mac5_scanin), 
		.scan_out			(pcx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	pcx_mcr_dp pcx_mac6(
		.data_out_x_			(pcx_scache_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[4]), 
		.arb_shift_a			(arb_shift_r_a_rep[4]), 
		.src_pcx_data_a			(spc4_pcx_data_a[129:0]), 
		.data_crit_x_			(col5_data_x_[129:0]), 
		.data_ncrit_x_			(col7_data_x_[129:0]), 
		.scan_in			(pcx_mac6_scanin), 
		.scan_out			(pcx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	pcx_mbr_dp pcx_mac7(
		.data_out_x_			(col7_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[6]), 
		.arb_shift_a			(arb_shift_r_a[6]), 
		.src_pcx_data_a			(spc6_pcx_data_a[129:0]), 
		.data_prev_x_			(all_ones[129:0]), 
		.scan_in			(pcx_mac7_scanin), 
		.scan_out			(pcx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_dpsh.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_dpsh (
  pcx_scache_data_x_, 
  arb_grant_l_a, 
  arb_q0_holdbar_l_a, 
  arb_qsel0_l_a, 
  arb_qsel1_l_a, 
  arb_shift_l_a, 
  arb_grant_r_a, 
  arb_q0_holdbar_r_a, 
  arb_qsel0_r_a, 
  arb_qsel1_r_a, 
  arb_shift_r_a, 
  spc0_pcx_data_a, 
  spc1_pcx_data_a, 
  spc2_pcx_data_a, 
  spc3_pcx_data_a, 
  spc4_pcx_data_a, 
  spc5_pcx_data_a, 
  spc6_pcx_data_a, 
  spc7_pcx_data_a, 
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  scan_in, 
  scan_out);
wire [129:0] all_ones;
wire [4:0] mac0_rep_in;
wire [3:0] arb_grant_l_a_rep;
wire [3:0] arb_qsel0_l_a_rep;
wire [3:0] arb_qsel1_l_a_rep;
wire [3:0] arb_shift_l_a_rep;
wire [3:0] arb_q0_holdbar_l_a_rep;
wire [4:0] mac0_rep_out;
wire [4:0] mac1_rep_in;
wire [4:0] mac1_rep_out;
wire [4:0] mac2_rep_in;
wire [4:0] mac2_rep_out;
wire [4:0] mac3_rep_in;
wire [4:0] mac3_rep_out;
wire [4:0] mac4_rep_in;
wire [7:4] arb_grant_r_a_rep;
wire [7:4] arb_q0_holdbar_r_a_rep;
wire [7:4] arb_qsel0_r_a_rep;
wire [7:4] arb_qsel1_r_a_rep;
wire [7:4] arb_shift_r_a_rep;
wire [4:0] mac4_rep_out;
wire [4:0] mac5_rep_in;
wire [4:0] mac5_rep_out;
wire [4:0] mac6_rep_in;
wire [4:0] mac6_rep_out;
wire scan_rep_in;
wire [129:0] col0_data_x_;
wire tcu_scan_en_out_0_unused;
wire tcu_pce_ov_out_0_unused;
wire ccx_aclk_out_0_unused;
wire ccx_bclk_out_0_unused;
wire pcx_mac0_scanin;
wire pcx_mac0_scanout;
wire [6:1] tcu_scan_en_out;
wire [6:1] tcu_pce_ov_out;
wire [6:1] ccx_aclk_out;
wire [6:1] ccx_bclk_out;
wire [129:0] col1_data_x_;
wire pcx_mac1_scanin;
wire pcx_mac1_scanout;
wire [129:0] col2_data_x_;
wire pcx_mac2_scanin;
wire pcx_mac2_scanout;
wire [129:0] col3_data_x_;
wire pcx_mac3_scanin;
wire pcx_mac3_scanout;
wire [129:0] col4_data_x_;
wire pcx_mac4_scanin;
wire pcx_mac4_scanout;
wire [129:0] col5_data_x_;
wire pcx_mac5_scanin;
wire pcx_mac5_scanout;
wire [129:0] col6_data_x_;
wire pcx_mac6_scanin;
wire pcx_mac6_scanout;
wire tcu_scan_en_out_7_unused;
wire tcu_pce_ov_out_7_unused;
wire ccx_aclk_out_7_unused;
wire ccx_bclk_out_7_unused;
wire pcx_mac7_scanin;
wire pcx_mac7_scanout;
wire [7:4] arb_grant_l_a_unused;
wire [7:4] arb_q0_holdbar_l_a_unused;
wire [7:4] arb_qsel0_l_a_unused;
wire [7:4] arb_qsel1_l_a_unused;
wire [7:4] arb_shift_l_a_unused;
wire [3:0] arb_grant_r_a_unused;
wire [3:0] arb_q0_holdbar_r_a_unused;
wire [3:0] arb_qsel0_r_a_unused;
wire [3:0] arb_qsel1_r_a_unused;
wire [3:0] arb_shift_r_a_unused;
wire scan_rep_out;


// Beginning of automatic outputs (from unused autoinst outputs)
output [129:0]          pcx_scache_data_x_;     // From mac3 of pcx_mcr_dp.v
// End of automatics

// Beginning of automatic inputs (from unused autoinst inputs)
input [7:0]             arb_grant_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_l_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_l_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_grant_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_q0_holdbar_r_a;          // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel0_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_qsel1_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [7:0]             arb_shift_r_a;            // To mac0 of pcx_mar_dp.v, ...
input [129:0]           spc0_pcx_data_a;        // To mac0 of pcx_mar_dp.v
input [129:0]           spc1_pcx_data_a;        // To mac1 of pcx_mbr_dp.v
input [129:0]           spc2_pcx_data_a;        // To mac2 of pcx_mbr_dp.v
input [129:0]           spc3_pcx_data_a;        // To mac3 of pcx_mcr_dp.v
input [129:0]           spc4_pcx_data_a;        // To mac4 of pcx_mbl_dp.v
input [129:0]           spc5_pcx_data_a;        // To mac5 of pcx_mbl_dp.v
input [129:0]           spc6_pcx_data_a;        // To mac6 of pcx_mbl_dp.v
input [129:0]           spc7_pcx_data_a;        // To mac7 of pcx_mal_dp.v
// End of automatics
// globals
input tcu_scan_en ;
input           l2clk;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           scan_in;
output          scan_out;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -> mac1 ->mac2 ->mac3 -> mac4 -> mac5 <- mac6 <- mac7 
//    al     bl     bl     bl      bl      bl        bl     cr
//                                                          |
//            ------buf-------------------------------------
//            |
//            v
//         to sctag 

assign all_ones[129:0] = 130'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

// mac0 arb inputs go through 1 buffer
assign mac0_rep_in[4:0] = {arb_grant_l_a[0],arb_qsel0_l_a[0],arb_qsel1_l_a[0],
                           arb_shift_l_a[0],arb_q0_holdbar_l_a[0]};

assign {arb_grant_l_a_rep[0],arb_qsel0_l_a_rep[0],arb_qsel1_l_a_rep[0],
        arb_shift_l_a_rep[0],arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];

// mac1 arb input go through 1 buffer
assign mac1_rep_in[4:0] = {arb_grant_l_a[2],arb_q0_holdbar_l_a[2],arb_qsel0_l_a[2],
                       arb_qsel1_l_a[2],arb_shift_l_a[2]};

assign {arb_grant_l_a_rep[2],arb_q0_holdbar_l_a_rep[2],arb_qsel0_l_a_rep[2],
        arb_qsel1_l_a_rep[2],arb_shift_l_a_rep[2]} = mac1_rep_out[4:0];

// mac2 arb inputs go through 2 buffers
assign mac2_rep_in[4:0] = {arb_grant_l_a[1],arb_q0_holdbar_l_a[1],arb_qsel0_l_a[1],
                       arb_qsel1_l_a[1],arb_shift_l_a[1]};

assign {arb_grant_l_a_rep[1],arb_q0_holdbar_l_a_rep[1],arb_qsel0_l_a_rep[1],
        arb_qsel1_l_a_rep[1],arb_shift_l_a_rep[1]} = mac2_rep_out[4:0];

// mac3 inputs go through 2 buffers
assign mac3_rep_in[4:0] = {arb_grant_l_a[3],arb_q0_holdbar_l_a[3],arb_qsel0_l_a[3],
                       arb_qsel1_l_a[3],arb_shift_l_a[3]};

assign {arb_grant_l_a_rep[3],arb_q0_holdbar_l_a_rep[3],arb_qsel0_l_a_rep[3],
        arb_qsel1_l_a_rep[3],arb_shift_l_a_rep[3]} = mac3_rep_out[4:0];

// mac4 inputs go through 2 buffers
assign mac4_rep_in[4:0] = {arb_grant_r_a[5],arb_q0_holdbar_r_a[5],arb_qsel0_r_a[5],
                       arb_qsel1_r_a[5],arb_shift_r_a[5]};

assign {arb_grant_r_a_rep[5],arb_q0_holdbar_r_a_rep[5],arb_qsel0_r_a_rep[5],
        arb_qsel1_r_a_rep[5],arb_shift_r_a_rep[5]} = mac4_rep_out[4:0];

// mac5 inputs go through 1 buffer
assign mac5_rep_in[4:0] = {arb_grant_r_a[7],arb_q0_holdbar_r_a[7],arb_qsel0_r_a[7],
                       arb_qsel1_r_a[7],arb_shift_r_a[7]};

assign {arb_grant_r_a_rep[7],arb_q0_holdbar_r_a_rep[7],arb_qsel0_r_a_rep[7],
        arb_qsel1_r_a_rep[7],arb_shift_r_a_rep[7]} = mac5_rep_out[4:0];

// mac6 inputs go through 1 buffer
assign mac6_rep_in[4:0] = {arb_grant_r_a[4],arb_q0_holdbar_r_a[4],arb_qsel0_r_a[4],
                       arb_qsel1_r_a[4],arb_shift_r_a[4]};

assign {arb_grant_r_a_rep[4],arb_q0_holdbar_r_a_rep[4],arb_qsel0_r_a_rep[4],
        arb_qsel1_r_a_rep[4],arb_shift_r_a_rep[4]} = mac6_rep_out[4:0];

assign scan_rep_in = scan_in;


pcx_rep_dp pcx_rep(.mac0_rep_out(mac0_rep_out[4:0]),
  .mac1_rep_out(mac1_rep_out[4:0]),
  .mac2_rep_out(mac2_rep_out[4:0]),
  .mac3_rep_out(mac3_rep_out[4:0]),
  .mac4_rep_out(mac4_rep_out[4:0]),
  .mac5_rep_out(mac5_rep_out[4:0]),
  .mac6_rep_out(mac6_rep_out[4:0]),
  .scan_rep_out(scan_rep_out),
  .mac0_rep_in(mac0_rep_in[4:0]),
  .mac1_rep_in(mac1_rep_in[4:0]),
  .mac2_rep_in(mac2_rep_in[4:0]),
  .mac3_rep_in(mac3_rep_in[4:0]),
  .mac4_rep_in(mac4_rep_in[4:0]),
  .mac5_rep_in(mac5_rep_in[4:0]),
  .mac6_rep_in(mac6_rep_in[4:0]),
  .scan_rep_in(scan_rep_in)
                   );


/*
   pcx_mal_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a[@]),
 .arb_qsel0_a(arb_qsel0_l_a[@]),
 .arb_qsel1_a(arb_qsel1_l_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a[@]),
 .arb_shift_a(arb_shift_l_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .l2clk		(l2clk));
*/

// do not use autoinstancing.
// connections have been modified to match the cpu floorplan
// src_pcx_data_a has to be manually connected.

// input from spc0
pcx_mal_dp pcx_mac0 ( 
                      // Outputs
                      .data_out_x_       (col0_data_x_[129:0]),   // Templated
                      .tcu_scan_en_out (tcu_scan_en_out_0_unused),
                      .tcu_pce_ov_out (tcu_pce_ov_out_0_unused),
                      .ccx_aclk_out (ccx_aclk_out_0_unused),
                      .ccx_bclk_out (ccx_bclk_out_0_unused),
                      // Inputs
                      .arb_grant_a       (arb_grant_l_a_rep[0]),        // Templated
                      .arb_qsel0_a       (arb_qsel0_l_a_rep[0]),        // Templated
                      .arb_qsel1_a       (arb_qsel1_l_a_rep[0]),        // Templated
                      .arb_q0_holdbar_a  (arb_q0_holdbar_l_a_rep[0]),   // Templated
                      .arb_shift_a       (arb_shift_l_a_rep[0]),        // Templated
                      .src_pcx_data_a    (spc0_pcx_data_a[129:0]), // Templated
                      .scan_in(pcx_mac0_scanin),
                      .scan_out(pcx_mac0_scanout),
                      .l2clk             (l2clk),                 // Templated
                      .tcu_scan_en (tcu_scan_en_out[1]),
                      .tcu_pce_ov (tcu_pce_ov_out[1]),
                      .ccx_aclk (ccx_aclk_out[1]),
                      .ccx_bclk (ccx_bclk_out[1])
                      );


/*
 pcx_mbl_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(col@_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_l_a_rep[@]),
 .arb_qsel0_a(arb_qsel0_l_a_rep[@]),
 .arb_qsel1_a(arb_qsel1_l_a_rep[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_l_a_rep[@]),
 .arb_shift_a(arb_shift_l_a_rep[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_prev_x_(col@"(- @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk));
*/


// input from spc2
pcx_mbl_dp pcx_mac1(
                    // Outputs
                    .data_out_x_        (col1_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[1]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[1]),
                    .ccx_aclk_out (ccx_aclk_out[1]),
                    .ccx_bclk_out (ccx_bclk_out[1]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[2]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[2]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[2]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[2]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[2]),        // Templated
                    .src_pcx_data_a     (spc2_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col0_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac1_scanin),
                    .scan_out(pcx_mac1_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[2]),
                    .tcu_pce_ov (tcu_pce_ov_out[2]),
                    .ccx_aclk (ccx_aclk_out[2]),
                    .ccx_bclk (ccx_bclk_out[2])
                    );


// input from spc1
pcx_mbl_dp pcx_mac2(
                    // Outputs
                    .data_out_x_        (col2_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[2]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[2]),
                    .ccx_aclk_out (ccx_aclk_out[2]),
                    .ccx_bclk_out (ccx_bclk_out[2]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[1]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[1]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[1]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[1]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[1]),        // Templated
                    .src_pcx_data_a     (spc1_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col1_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac2_scanin),
                    .scan_out(pcx_mac2_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );
 

// input from spc3
pcx_mbl_dp pcx_mac3(
                    // Outputs
                    .data_out_x_        (col3_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[3]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[3]),
                    .ccx_aclk_out (ccx_aclk_out[3]),
                    .ccx_bclk_out (ccx_bclk_out[3]),
                    // Inputs
                    .arb_grant_a        (arb_grant_l_a_rep[3]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_l_a_rep[3]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_l_a_rep[3]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_l_a_rep[3]),   // Templated
                    .arb_shift_a        (arb_shift_l_a_rep[3]),        // Templated
                    .src_pcx_data_a     (spc3_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col2_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac3_scanin),
                    .scan_out(pcx_mac3_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en),
                    .tcu_pce_ov (tcu_pce_ov),
                    .ccx_aclk (ccx_aclk),
                    .ccx_bclk (ccx_bclk)
                    );


// input from spc5
pcx_mbl_dp pcx_mac4(
                    // Outputs
                    .data_out_x_        (col4_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[4]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[4]),
                    .ccx_aclk_out (ccx_aclk_out[4]),
                    .ccx_bclk_out (ccx_bclk_out[4]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[5]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[5]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[5]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[5]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[5]),        // Templated
                    .src_pcx_data_a     (spc5_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col3_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac4_scanin),
                    .scan_out(pcx_mac4_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[3]),
                    .tcu_pce_ov (tcu_pce_ov_out[3]),
                    .ccx_aclk (ccx_aclk_out[3]),
                    .ccx_bclk (ccx_bclk_out[3])
                    );


// input from spc7
pcx_mbl_dp pcx_mac5(
                    // Outputs
                    .data_out_x_        (col5_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[5]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[5]),
                    .ccx_aclk_out (ccx_aclk_out[5]),
                    .ccx_bclk_out (ccx_bclk_out[5]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[7]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[7]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[7]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[7]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[7]),        // Templated
                    .src_pcx_data_a     (spc7_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col4_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac5_scanin),
                    .scan_out(pcx_mac5_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[4]),
                    .tcu_pce_ov (tcu_pce_ov_out[4]),
                    .ccx_aclk (ccx_aclk_out[4]),
                    .ccx_bclk (ccx_bclk_out[4])
                    );


// input from spc4
pcx_mbl_dp pcx_mac6(
                    // Outputs
                    .data_out_x_        (col6_data_x_[129:0]),   // Templated
                    .tcu_scan_en_out (tcu_scan_en_out[6]),
                    .tcu_pce_ov_out (tcu_pce_ov_out[6]),
                    .ccx_aclk_out (ccx_aclk_out[6]),
                    .ccx_bclk_out (ccx_bclk_out[6]),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a_rep[4]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a_rep[4]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a_rep[4]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a_rep[4]),   // Templated
                    .arb_shift_a        (arb_shift_r_a_rep[4]),        // Templated
                    .src_pcx_data_a     (spc4_pcx_data_a[129:0]), // Templated
                    .data_prev_x_       (col5_data_x_[129:0]),   // Templated
                    .scan_in(pcx_mac6_scanin),
                    .scan_out(pcx_mac6_scanout),
                    .l2clk              (l2clk),                 // Templated
                    .tcu_scan_en (tcu_scan_en_out[5]),
                    .tcu_pce_ov (tcu_pce_ov_out[5]),
                    .ccx_aclk (ccx_aclk_out[5]),
                    .ccx_bclk (ccx_bclk_out[5])
                    );
 

/*
   pcx_mcr_dp AUTO_TEMPLATE
 (
 // Outputs
 .data_out_x_	(pcx_scache_data_x_[129:0]),
 // Inputs
 .arb_grant_a(arb_grant_r_a[@]),
 .arb_qsel0_a(arb_qsel0_r_a[@]),
 .arb_qsel1_a(arb_qsel1_r_a[@]),
 .arb_q0_holdbar_a(arb_q0_holdbar_r_a[@]),
 .arb_shift_a(arb_shift_r_a[@]),
 .src_pcx_data_a(spc@_pcx_data_a[129:0]),
 .data_crit_x_(col@"(- @ 1)"_data_x_[129:0]),
 .data_ncrit_x_(col@"(+ @ 1)"_data_x_[129:0]),
 .l2clk		(l2clk))
*/
// input from spc6
pcx_mcr_dp pcx_mac7(
                    // Outputs
                    .data_out_x_        (pcx_scache_data_x_[129:0]), // Templated
                    .tcu_scan_en_out (tcu_scan_en_out_7_unused),
                    .tcu_pce_ov_out (tcu_pce_ov_out_7_unused),
                    .ccx_aclk_out (ccx_aclk_out_7_unused),
                    .ccx_bclk_out (ccx_bclk_out_7_unused),
                    // Inputs
                    .arb_grant_a        (arb_grant_r_a[6]),        // Templated
                    .arb_qsel0_a        (arb_qsel0_r_a[6]),        // Templated
                    .arb_qsel1_a        (arb_qsel1_r_a[6]),        // Templated
                    .arb_q0_holdbar_a   (arb_q0_holdbar_r_a[6]),   // Templated
                    .arb_shift_a        (arb_shift_r_a[6]),        // Templated
                    .src_pcx_data_a     (spc6_pcx_data_a[129:0]), // Templated
                    .data_crit_x_       (col6_data_x_[129:0]),   // Templated
                    .data_ncrit_x_      (all_ones[129:0]),       // Templated
                    .scan_in(pcx_mac7_scanin),
                    .scan_out(pcx_mac7_scanout),
                    .l2clk              (l2clk),
                    .tcu_scan_en (tcu_scan_en_out[6]),
                    .tcu_pce_ov (tcu_pce_ov_out[6]),
                    .ccx_aclk (ccx_aclk_out[6]),
                    .ccx_bclk (ccx_bclk_out[6])
                    );

 
assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];

assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];


// fixscan start:
assign pcx_mac0_scanin           = scan_rep_out                  ;
assign pcx_mac1_scanin           = pcx_mac0_scanout         ;
assign pcx_mac2_scanin           = pcx_mac1_scanout         ;
assign pcx_mac3_scanin           = pcx_mac2_scanout         ;
assign pcx_mac4_scanin           = pcx_mac3_scanout         ;
assign pcx_mac5_scanin           = pcx_mac4_scanout         ;
assign pcx_mac6_scanin           = pcx_mac5_scanout         ;
assign pcx_mac7_scanin           = pcx_mac6_scanout         ;
assign scan_out                  = pcx_mac7_scanout         ;
// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


//
//   buff macro
//
//


module pcx_dpsh_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsh_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module pcx_dpsh_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_dpsh_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_dpsh_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule


//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsh_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   ccx macro
//
//


module pcx_dpsh_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_dpsh(pcx_scache_data_x_, arb_grant_l_a, arb_q0_holdbar_l_a, 
	arb_qsel0_l_a, arb_qsel1_l_a, arb_shift_l_a, arb_grant_r_a, 
	arb_q0_holdbar_r_a, arb_qsel0_r_a, arb_qsel1_r_a, arb_shift_r_a, 
	spc0_pcx_data_a, spc1_pcx_data_a, spc2_pcx_data_a, spc3_pcx_data_a, 
	spc4_pcx_data_a, spc5_pcx_data_a, spc6_pcx_data_a, spc7_pcx_data_a, 
	tcu_scan_en, l2clk, tcu_pce_ov, ccx_aclk, ccx_bclk, scan_in, scan_out);

	output	[129:0]		pcx_scache_data_x_;
	input	[7:0]		arb_grant_l_a;
	input	[7:0]		arb_q0_holdbar_l_a;
	input	[7:0]		arb_qsel0_l_a;
	input	[7:0]		arb_qsel1_l_a;
	input	[7:0]		arb_shift_l_a;
	input	[7:0]		arb_grant_r_a;
	input	[7:0]		arb_q0_holdbar_r_a;
	input	[7:0]		arb_qsel0_r_a;
	input	[7:0]		arb_qsel1_r_a;
	input	[7:0]		arb_shift_r_a;
	input	[129:0]		spc0_pcx_data_a;
	input	[129:0]		spc1_pcx_data_a;
	input	[129:0]		spc2_pcx_data_a;
	input	[129:0]		spc3_pcx_data_a;
	input	[129:0]		spc4_pcx_data_a;
	input	[129:0]		spc5_pcx_data_a;
	input	[129:0]		spc6_pcx_data_a;
	input	[129:0]		spc7_pcx_data_a;
	input			tcu_scan_en;
	input			l2clk;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			scan_in;
	output			scan_out;

	wire	[129:0]		all_ones;
	wire	[4:0]		mac0_rep_in;
	wire	[3:0]		arb_grant_l_a_rep;
	wire	[3:0]		arb_qsel0_l_a_rep;
	wire	[3:0]		arb_qsel1_l_a_rep;
	wire	[3:0]		arb_shift_l_a_rep;
	wire	[3:0]		arb_q0_holdbar_l_a_rep;
	wire	[4:0]		mac0_rep_out;
	wire	[4:0]		mac1_rep_in;
	wire	[4:0]		mac1_rep_out;
	wire	[4:0]		mac2_rep_in;
	wire	[4:0]		mac2_rep_out;
	wire	[4:0]		mac3_rep_in;
	wire	[4:0]		mac3_rep_out;
	wire	[4:0]		mac4_rep_in;
	wire	[7:4]		arb_grant_r_a_rep;
	wire	[7:4]		arb_q0_holdbar_r_a_rep;
	wire	[7:4]		arb_qsel0_r_a_rep;
	wire	[7:4]		arb_qsel1_r_a_rep;
	wire	[7:4]		arb_shift_r_a_rep;
	wire	[4:0]		mac4_rep_out;
	wire	[4:0]		mac5_rep_in;
	wire	[4:0]		mac5_rep_out;
	wire	[4:0]		mac6_rep_in;
	wire	[4:0]		mac6_rep_out;
	wire			scan_rep_in;
	wire	[129:0]		col0_data_x_;
	wire			tcu_scan_en_out_0_unused;
	wire			tcu_pce_ov_out_0_unused;
	wire			ccx_aclk_out_0_unused;
	wire			ccx_bclk_out_0_unused;
	wire			pcx_mac0_scanin;
	wire			pcx_mac0_scanout;
	wire	[6:1]		tcu_scan_en_out;
	wire	[6:1]		tcu_pce_ov_out;
	wire	[6:1]		ccx_aclk_out;
	wire	[6:1]		ccx_bclk_out;
	wire	[129:0]		col1_data_x_;
	wire			pcx_mac1_scanin;
	wire			pcx_mac1_scanout;
	wire	[129:0]		col2_data_x_;
	wire			pcx_mac2_scanin;
	wire			pcx_mac2_scanout;
	wire	[129:0]		col3_data_x_;
	wire			pcx_mac3_scanin;
	wire			pcx_mac3_scanout;
	wire	[129:0]		col4_data_x_;
	wire			pcx_mac4_scanin;
	wire			pcx_mac4_scanout;
	wire	[129:0]		col5_data_x_;
	wire			pcx_mac5_scanin;
	wire			pcx_mac5_scanout;
	wire	[129:0]		col6_data_x_;
	wire			pcx_mac6_scanin;
	wire			pcx_mac6_scanout;
	wire			tcu_scan_en_out_7_unused;
	wire			tcu_pce_ov_out_7_unused;
	wire			ccx_aclk_out_7_unused;
	wire			ccx_bclk_out_7_unused;
	wire			pcx_mac7_scanin;
	wire			pcx_mac7_scanout;
	wire	[7:4]		arb_grant_l_a_unused;
	wire	[7:4]		arb_q0_holdbar_l_a_unused;
	wire	[7:4]		arb_qsel0_l_a_unused;
	wire	[7:4]		arb_qsel1_l_a_unused;
	wire	[7:4]		arb_shift_l_a_unused;
	wire	[3:0]		arb_grant_r_a_unused;
	wire	[3:0]		arb_q0_holdbar_r_a_unused;
	wire	[3:0]		arb_qsel0_r_a_unused;
	wire	[3:0]		arb_qsel1_r_a_unused;
	wire	[3:0]		arb_shift_r_a_unused;
	wire			scan_rep_out;

	assign all_ones[129:0] = 130'h3ffffffffffffffffffffffffffffffff;
	assign mac0_rep_in[4:0] = {arb_grant_l_a[0], arb_qsel0_l_a[0], 
		arb_qsel1_l_a[0], arb_shift_l_a[0], arb_q0_holdbar_l_a[0]};
	assign {arb_grant_l_a_rep[0], arb_qsel0_l_a_rep[0], 
		arb_qsel1_l_a_rep[0], arb_shift_l_a_rep[0], 
		arb_q0_holdbar_l_a_rep[0]} = mac0_rep_out[4:0];
	assign mac1_rep_in[4:0] = {arb_grant_l_a[2], arb_q0_holdbar_l_a[2], 
		arb_qsel0_l_a[2], arb_qsel1_l_a[2], arb_shift_l_a[2]};
	assign {arb_grant_l_a_rep[2], arb_q0_holdbar_l_a_rep[2], 
		arb_qsel0_l_a_rep[2], arb_qsel1_l_a_rep[2], arb_shift_l_a_rep[2]
		} = mac1_rep_out[4:0];
	assign mac2_rep_in[4:0] = {arb_grant_l_a[1], arb_q0_holdbar_l_a[1], 
		arb_qsel0_l_a[1], arb_qsel1_l_a[1], arb_shift_l_a[1]};
	assign {arb_grant_l_a_rep[1], arb_q0_holdbar_l_a_rep[1], 
		arb_qsel0_l_a_rep[1], arb_qsel1_l_a_rep[1], arb_shift_l_a_rep[1]
		} = mac2_rep_out[4:0];
	assign mac3_rep_in[4:0] = {arb_grant_l_a[3], arb_q0_holdbar_l_a[3], 
		arb_qsel0_l_a[3], arb_qsel1_l_a[3], arb_shift_l_a[3]};
	assign {arb_grant_l_a_rep[3], arb_q0_holdbar_l_a_rep[3], 
		arb_qsel0_l_a_rep[3], arb_qsel1_l_a_rep[3], arb_shift_l_a_rep[3]
		} = mac3_rep_out[4:0];
	assign mac4_rep_in[4:0] = {arb_grant_r_a[5], arb_q0_holdbar_r_a[5], 
		arb_qsel0_r_a[5], arb_qsel1_r_a[5], arb_shift_r_a[5]};
	assign {arb_grant_r_a_rep[5], arb_q0_holdbar_r_a_rep[5], 
		arb_qsel0_r_a_rep[5], arb_qsel1_r_a_rep[5], arb_shift_r_a_rep[5]
		} = mac4_rep_out[4:0];
	assign mac5_rep_in[4:0] = {arb_grant_r_a[7], arb_q0_holdbar_r_a[7], 
		arb_qsel0_r_a[7], arb_qsel1_r_a[7], arb_shift_r_a[7]};
	assign {arb_grant_r_a_rep[7], arb_q0_holdbar_r_a_rep[7], 
		arb_qsel0_r_a_rep[7], arb_qsel1_r_a_rep[7], arb_shift_r_a_rep[7]
		} = mac5_rep_out[4:0];
	assign mac6_rep_in[4:0] = {arb_grant_r_a[4], arb_q0_holdbar_r_a[4], 
		arb_qsel0_r_a[4], arb_qsel1_r_a[4], arb_shift_r_a[4]};
	assign {arb_grant_r_a_rep[4], arb_q0_holdbar_r_a_rep[4], 
		arb_qsel0_r_a_rep[4], arb_qsel1_r_a_rep[4], arb_shift_r_a_rep[4]
		} = mac6_rep_out[4:0];
	assign scan_rep_in = scan_in;
	assign arb_grant_l_a_unused[7:4] = arb_grant_l_a[7:4];
	assign arb_q0_holdbar_l_a_unused[7:4] = arb_q0_holdbar_l_a[7:4];
	assign arb_qsel0_l_a_unused[7:4] = arb_qsel0_l_a[7:4];
	assign arb_qsel1_l_a_unused[7:4] = arb_qsel1_l_a[7:4];
	assign arb_shift_l_a_unused[7:4] = arb_shift_l_a[7:4];
	assign arb_grant_r_a_unused[3:0] = arb_grant_r_a[3:0];
	assign arb_q0_holdbar_r_a_unused[3:0] = arb_q0_holdbar_r_a[3:0];
	assign arb_qsel0_r_a_unused[3:0] = arb_qsel0_r_a[3:0];
	assign arb_qsel1_r_a_unused[3:0] = arb_qsel1_r_a[3:0];
	assign arb_shift_r_a_unused[3:0] = arb_shift_r_a[3:0];
	assign pcx_mac0_scanin = scan_rep_out;
	assign pcx_mac1_scanin = pcx_mac0_scanout;
	assign pcx_mac2_scanin = pcx_mac1_scanout;
	assign pcx_mac3_scanin = pcx_mac2_scanout;
	assign pcx_mac4_scanin = pcx_mac3_scanout;
	assign pcx_mac5_scanin = pcx_mac4_scanout;
	assign pcx_mac6_scanin = pcx_mac5_scanout;
	assign pcx_mac7_scanin = pcx_mac6_scanout;
	assign scan_out = pcx_mac7_scanout;

	pcx_rep_dp pcx_rep(
		.mac0_rep_out			(mac0_rep_out[4:0]), 
		.mac1_rep_out			(mac1_rep_out[4:0]), 
		.mac2_rep_out			(mac2_rep_out[4:0]), 
		.mac3_rep_out			(mac3_rep_out[4:0]), 
		.mac4_rep_out			(mac4_rep_out[4:0]), 
		.mac5_rep_out			(mac5_rep_out[4:0]), 
		.mac6_rep_out			(mac6_rep_out[4:0]), 
		.scan_rep_out			(scan_rep_out), 
		.mac0_rep_in			(mac0_rep_in[4:0]), 
		.mac1_rep_in			(mac1_rep_in[4:0]), 
		.mac2_rep_in			(mac2_rep_in[4:0]), 
		.mac3_rep_in			(mac3_rep_in[4:0]), 
		.mac4_rep_in			(mac4_rep_in[4:0]), 
		.mac5_rep_in			(mac5_rep_in[4:0]), 
		.mac6_rep_in			(mac6_rep_in[4:0]), 
		.scan_rep_in			(scan_rep_in));
	pcx_mal_dp pcx_mac0(
		.data_out_x_			(col0_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_0_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_0_unused), 
		.ccx_aclk_out			(ccx_aclk_out_0_unused), 
		.ccx_bclk_out			(ccx_bclk_out_0_unused), 
		.arb_grant_a			(arb_grant_l_a_rep[0]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[0]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[0]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[0]), 
		.arb_shift_a			(arb_shift_l_a_rep[0]), 
		.src_pcx_data_a			(spc0_pcx_data_a[129:0]), 
		.scan_in			(pcx_mac0_scanin), 
		.scan_out			(pcx_mac0_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[1]), 
		.tcu_pce_ov			(tcu_pce_ov_out[1]), 
		.ccx_aclk			(ccx_aclk_out[1]), 
		.ccx_bclk			(ccx_bclk_out[1]));
	pcx_mbl_dp pcx_mac1(
		.data_out_x_			(col1_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[1]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[1]), 
		.ccx_aclk_out			(ccx_aclk_out[1]), 
		.ccx_bclk_out			(ccx_bclk_out[1]), 
		.arb_grant_a			(arb_grant_l_a_rep[2]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[2]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[2]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[2]), 
		.arb_shift_a			(arb_shift_l_a_rep[2]), 
		.src_pcx_data_a			(spc2_pcx_data_a[129:0]), 
		.data_prev_x_			(col0_data_x_[129:0]), 
		.scan_in			(pcx_mac1_scanin), 
		.scan_out			(pcx_mac1_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[2]), 
		.tcu_pce_ov			(tcu_pce_ov_out[2]), 
		.ccx_aclk			(ccx_aclk_out[2]), 
		.ccx_bclk			(ccx_bclk_out[2]));
	pcx_mbl_dp pcx_mac2(
		.data_out_x_			(col2_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[2]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[2]), 
		.ccx_aclk_out			(ccx_aclk_out[2]), 
		.ccx_bclk_out			(ccx_bclk_out[2]), 
		.arb_grant_a			(arb_grant_l_a_rep[1]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[1]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[1]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[1]), 
		.arb_shift_a			(arb_shift_l_a_rep[1]), 
		.src_pcx_data_a			(spc1_pcx_data_a[129:0]), 
		.data_prev_x_			(col1_data_x_[129:0]), 
		.scan_in			(pcx_mac2_scanin), 
		.scan_out			(pcx_mac2_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbl_dp pcx_mac3(
		.data_out_x_			(col3_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[3]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[3]), 
		.ccx_aclk_out			(ccx_aclk_out[3]), 
		.ccx_bclk_out			(ccx_bclk_out[3]), 
		.arb_grant_a			(arb_grant_l_a_rep[3]), 
		.arb_qsel0_a			(arb_qsel0_l_a_rep[3]), 
		.arb_qsel1_a			(arb_qsel1_l_a_rep[3]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_l_a_rep[3]), 
		.arb_shift_a			(arb_shift_l_a_rep[3]), 
		.src_pcx_data_a			(spc3_pcx_data_a[129:0]), 
		.data_prev_x_			(col2_data_x_[129:0]), 
		.scan_in			(pcx_mac3_scanin), 
		.scan_out			(pcx_mac3_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.ccx_aclk			(ccx_aclk), 
		.ccx_bclk			(ccx_bclk));
	pcx_mbl_dp pcx_mac4(
		.data_out_x_			(col4_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[4]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[4]), 
		.ccx_aclk_out			(ccx_aclk_out[4]), 
		.ccx_bclk_out			(ccx_bclk_out[4]), 
		.arb_grant_a			(arb_grant_r_a_rep[5]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[5]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[5]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[5]), 
		.arb_shift_a			(arb_shift_r_a_rep[5]), 
		.src_pcx_data_a			(spc5_pcx_data_a[129:0]), 
		.data_prev_x_			(col3_data_x_[129:0]), 
		.scan_in			(pcx_mac4_scanin), 
		.scan_out			(pcx_mac4_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[3]), 
		.tcu_pce_ov			(tcu_pce_ov_out[3]), 
		.ccx_aclk			(ccx_aclk_out[3]), 
		.ccx_bclk			(ccx_bclk_out[3]));
	pcx_mbl_dp pcx_mac5(
		.data_out_x_			(col5_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[5]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[5]), 
		.ccx_aclk_out			(ccx_aclk_out[5]), 
		.ccx_bclk_out			(ccx_bclk_out[5]), 
		.arb_grant_a			(arb_grant_r_a_rep[7]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[7]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[7]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[7]), 
		.arb_shift_a			(arb_shift_r_a_rep[7]), 
		.src_pcx_data_a			(spc7_pcx_data_a[129:0]), 
		.data_prev_x_			(col4_data_x_[129:0]), 
		.scan_in			(pcx_mac5_scanin), 
		.scan_out			(pcx_mac5_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[4]), 
		.tcu_pce_ov			(tcu_pce_ov_out[4]), 
		.ccx_aclk			(ccx_aclk_out[4]), 
		.ccx_bclk			(ccx_bclk_out[4]));
	pcx_mbl_dp pcx_mac6(
		.data_out_x_			(col6_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out[6]), 
		.tcu_pce_ov_out			(tcu_pce_ov_out[6]), 
		.ccx_aclk_out			(ccx_aclk_out[6]), 
		.ccx_bclk_out			(ccx_bclk_out[6]), 
		.arb_grant_a			(arb_grant_r_a_rep[4]), 
		.arb_qsel0_a			(arb_qsel0_r_a_rep[4]), 
		.arb_qsel1_a			(arb_qsel1_r_a_rep[4]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a_rep[4]), 
		.arb_shift_a			(arb_shift_r_a_rep[4]), 
		.src_pcx_data_a			(spc4_pcx_data_a[129:0]), 
		.data_prev_x_			(col5_data_x_[129:0]), 
		.scan_in			(pcx_mac6_scanin), 
		.scan_out			(pcx_mac6_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[5]), 
		.tcu_pce_ov			(tcu_pce_ov_out[5]), 
		.ccx_aclk			(ccx_aclk_out[5]), 
		.ccx_bclk			(ccx_bclk_out[5]));
	pcx_mcr_dp pcx_mac7(
		.data_out_x_			(pcx_scache_data_x_[129:0]), 
		.tcu_scan_en_out		(tcu_scan_en_out_7_unused), 
		.tcu_pce_ov_out			(tcu_pce_ov_out_7_unused), 
		.ccx_aclk_out			(ccx_aclk_out_7_unused), 
		.ccx_bclk_out			(ccx_bclk_out_7_unused), 
		.arb_grant_a			(arb_grant_r_a[6]), 
		.arb_qsel0_a			(arb_qsel0_r_a[6]), 
		.arb_qsel1_a			(arb_qsel1_r_a[6]), 
		.arb_q0_holdbar_a		(arb_q0_holdbar_r_a[6]), 
		.arb_shift_a			(arb_shift_r_a[6]), 
		.src_pcx_data_a			(spc6_pcx_data_a[129:0]), 
		.data_crit_x_			(col6_data_x_[129:0]), 
		.data_ncrit_x_			(all_ones[129:0]), 
		.scan_in			(pcx_mac7_scanin), 
		.scan_out			(pcx_mac7_scanout), 
		.l2clk				(l2clk), 
		.tcu_scan_en			(tcu_scan_en_out[6]), 
		.tcu_pce_ov			(tcu_pce_ov_out[6]), 
		.ccx_aclk			(ccx_aclk_out[6]), 
		.ccx_bclk			(ccx_bclk_out[6]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_mal_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_mal_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_pcx_data_a, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [129:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;


output [129:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [129:0]   src_pcx_data_a;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;


// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

assign src_data_a[129:0] = src_pcx_data_a[129:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);


//l1clkhdr_dp_macro gkt_hdra 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );

//l1clkhdr_dp_macro gkt_hdrb 
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

pcx_mal_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

pcx_mal_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

pcx_mal_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_a AUTO_TEMPLATE
// (
//.scan_in(AUTO_TEMPLATE_scanin),
//.scan_out(AUTO_TEMPLATE_scanout),
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);

pcx_mal_dp_ccx_new_macro__type_a i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),
  .se(se));   // Templated

pcx_mal_dp_ccx_new_macro__type_a i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),
  .se(se));  // Templated

pcx_mal_dp_ccx_new_macro__type_a i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]),
  .se(se)); // Templated
pcx_mal_dp_ccx_new_macro__type_a i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]),
  .se(se)); // Templated

// fixscan start:
assign i12_scanin                 = scan_in                  ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   buff macro
//
//


module pcx_mal_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_mal_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_mal_dp_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule
`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module pcx_mal_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_pcx_data_a, l2clk, scan_in, 
	tcu_pce_ov, ccx_aclk, ccx_bclk, tcu_scan_en, scan_out, ccx_aclk_out, 
	ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[129:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[129:0]		src_pcx_data_a;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[129:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[129:0] = src_pcx_data_a[129:0];
	assign i12_scanin = scan_in;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_a i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.se				(se));
	ccx_new_macro__type_a i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.se				(se));
	ccx_new_macro__type_a i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.se				(se));
	ccx_new_macro__type_a i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.se				(se));
	ccx_new_macro__type_a i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.se				(se));
	ccx_new_macro__type_a i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.se				(se));
	ccx_new_macro__type_a i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.se				(se));
	ccx_new_macro__type_a i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.se				(se));
	ccx_new_macro__type_a i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.se				(se));
	ccx_new_macro__type_a i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.se				(se));
	ccx_new_macro__type_a i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.se				(se));
	ccx_new_macro__type_a i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.se				(se));
	ccx_new_macro__type_a i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.se				(se));
endmodule

`endif // `ifdef FPGA


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_mar_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_mar_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_pcx_data_a, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [129:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;


output [129:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [129:0]   src_pcx_data_a;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan

assign src_data_a[129:0] = src_pcx_data_a[129:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);


//l1clkhdr_dp_macro gkt_hdra
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );

//l1clkhdr_dp_macro gkt_hdrb
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

pcx_mar_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

pcx_mar_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

pcx_mar_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );


//   ccx_new_macro_a AUTO_TEMPLATE
// (
//.scan_in(AUTO_TEMPLATE_scanin),
//.scan_out(AUTO_TEMPLATE_scanout),
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);

pcx_mar_dp_ccx_new_macro__type_a i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),
  .se(se));   // Templated

pcx_mar_dp_ccx_new_macro__type_a i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),
  .se(se));  // Templated

pcx_mar_dp_ccx_new_macro__type_a i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]),
  .se(se)); // Templated
pcx_mar_dp_ccx_new_macro__type_a i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]),
  .se(se)); // Templated

// fixscan start:
assign i12_scanin                 = scan_in                  ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = ccx_aclk;
//assign soclk = ccx_bclk;
//// end scan
//
//// buffer the grant signal
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[129:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[129:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[129:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
//// MUX
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_out_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_out_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_out_x_[39:0]),
// );
// 	 
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   buff macro
//
//


module pcx_mar_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_mar_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_mar_dp_ccx_new_macro__type_a (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_a #(10)  mac_a(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule
`endif // `ifndef FPGA

`ifdef FPGA

/* Source file "1_core_8_thrd_dut_rtl.v.edt.2", line 192751 */
`timescale 1 ns / 100 ps
module pcx_mar_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_pcx_data_a, l2clk, scan_in, 
	tcu_pce_ov, ccx_aclk, ccx_bclk, tcu_scan_en, scan_out, ccx_aclk_out, 
	ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[129:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[129:0]		src_pcx_data_a;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[129:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[129:0] = src_pcx_data_a[129:0];
	assign i12_scanin = scan_in;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_a i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.se				(se));
	ccx_new_macro__type_a i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.se				(se));
	ccx_new_macro__type_a i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.se				(se));
	ccx_new_macro__type_a i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.se				(se));
	ccx_new_macro__type_a i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.se				(se));
	ccx_new_macro__type_a i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.se				(se));
	ccx_new_macro__type_a i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.se				(se));
	ccx_new_macro__type_a i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.se				(se));
	ccx_new_macro__type_a i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.se				(se));
	ccx_new_macro__type_a i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.se				(se));
	ccx_new_macro__type_a i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.se				(se));
	ccx_new_macro__type_a i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.se				(se));
	ccx_new_macro__type_a i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.se				(se));
endmodule

module ccx_l1clkhdr_ctl_macro__dl1hdr_24x(l2clk, l1en, pce_ov, stop, se, l1clk);

        input                   l2clk;
        input                   l1en;
        input                   pce_ov;
        input                   stop;
        input                   se;
        output                  l1clk;

        cl_sc1_l1hdr_24x c_0(
                .l2clk                          (l2clk),
                .pce                            (l1en),
                .l1clk                          (l1clk),
                .se                             (se),
                .pce_ov                         (pce_ov),
                .stop                           (stop));
endmodule


`endif // `ifdef FPGA


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_mbl_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_mbl_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_pcx_data_a, 
  data_prev_x_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [129:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;


output [129:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [129:0]   src_pcx_data_a;
input [129:0]   data_prev_x_;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan
 
assign src_data_a[129:0] = src_pcx_data_a[129:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);


//l1clkhdr_dp_macro gkt_hdra
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

pcx_mbl_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

pcx_mbl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

pcx_mbl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_b AUTO_TEMPLATE
// (
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_prev_x_l   (data_prev_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);

pcx_mbl_dp_ccx_new_macro__type_b_l i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),   // Templated
                .data_prev_x_l          (data_prev_x_[9:0]),
  .se(se));     // Templated

pcx_mbl_dp_ccx_new_macro__type_b_l i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),  // Templated
                .data_prev_x_l          (data_prev_x_[19:10]),
  .se(se));    // Templated

pcx_mbl_dp_ccx_new_macro__type_b_l i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]), // Templated
                .data_prev_x_l          (data_prev_x_[29:20]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]), // Templated
                .data_prev_x_l          (data_prev_x_[39:30]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]), // Templated
                .data_prev_x_l          (data_prev_x_[49:40]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]), // Templated
                .data_prev_x_l          (data_prev_x_[59:50]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]), // Templated
                .data_prev_x_l          (data_prev_x_[69:60]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]), // Templated
                .data_prev_x_l          (data_prev_x_[79:70]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]), // Templated
                .data_prev_x_l          (data_prev_x_[89:80]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]), // Templated
                .data_prev_x_l          (data_prev_x_[99:90]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]), // Templated
                 .data_prev_x_l         (data_prev_x_[109:100]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]), // Templated
                 .data_prev_x_l         (data_prev_x_[119:110]),
  .se(se));   // Templated
pcx_mbl_dp_ccx_new_macro__type_b_l i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]), // Templated
                 .data_prev_x_l         (data_prev_x_[129:120]),
  .se(se));   // Templated
// fixscan start:
assign i12_scanin                 = scan_in                  ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   buff macro
//
//


module pcx_mbl_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_mbl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_mbl_dp_ccx_new_macro__type_b_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_mbl_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_pcx_data_a, data_prev_x_, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, tcu_scan_en, scan_out, 
	ccx_aclk_out, ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[129:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[129:0]		src_pcx_data_a;
	input	[129:0]		data_prev_x_;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[129:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[129:0] = src_pcx_data_a[129:0];
	assign i12_scanin = scan_in;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_b_l i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.data_prev_x_l			(data_prev_x_[9:0]), 
		.se				(se));
	ccx_new_macro__type_b_l i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.data_prev_x_l			(data_prev_x_[19:10]), 
		.se				(se));
	ccx_new_macro__type_b_l i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.data_prev_x_l			(data_prev_x_[29:20]), 
		.se				(se));
	ccx_new_macro__type_b_l i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.data_prev_x_l			(data_prev_x_[39:30]), 
		.se				(se));
	ccx_new_macro__type_b_l i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.data_prev_x_l			(data_prev_x_[49:40]), 
		.se				(se));
	ccx_new_macro__type_b_l i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.data_prev_x_l			(data_prev_x_[59:50]), 
		.se				(se));
	ccx_new_macro__type_b_l i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.data_prev_x_l			(data_prev_x_[69:60]), 
		.se				(se));
	ccx_new_macro__type_b_l i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.data_prev_x_l			(data_prev_x_[79:70]), 
		.se				(se));
	ccx_new_macro__type_b_l i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.data_prev_x_l			(data_prev_x_[89:80]), 
		.se				(se));
	ccx_new_macro__type_b_l i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.data_prev_x_l			(data_prev_x_[99:90]), 
		.se				(se));
	ccx_new_macro__type_b_l i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.data_prev_x_l			(data_prev_x_[109:100]), 
		.se				(se));
	ccx_new_macro__type_b_l i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.data_prev_x_l			(data_prev_x_[119:110]), 
		.se				(se));
	ccx_new_macro__type_b_l i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.data_prev_x_l			(data_prev_x_[129:120]), 
		.se				(se));
endmodule

module ccx_new_macro__type_b_l(l2clk, l1clk, pce0, pce1, pce_ov, se, stop,
        siclk_in, soclk_in, scan_in, grant_a, qsel0, shift, data_a,
        data_prev_x_l, data_x_l, scan_out);

        input                   l2clk;
        input                   l1clk;
        input                   pce0;
        input                   pce1;
        input                   pce_ov;
        input                   se;
        input                   stop;
        input                   siclk_in;
        input                   soclk_in;
        input                   scan_in;
        input                   grant_a;
        input                   qsel0;
        input                   shift;
        input   [9:0]           data_a;
        input   [9:0]           data_prev_x_l;
        output  [9:0]           data_x_l;
        output                  scan_out;

        wire                    so5;
        wire                    siclk_out;
        wire                    soclk_out;
        wire                    l1clk0;
        wire                    l1clk1;
        wire                    grant_x;
        wire                    qsel0_buf;
        wire                    shift_buf;

        cl_dp1_ccxhdr c0(
                .si                             (scan_in),
                .so                             (so5),
                .l2clk                          (l2clk),
                .pce0                           (pce0),
                .pce1                           (pce1),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_in                       (siclk_in),
                .soclk_in                       (soclk_in),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .se                             (se),
                .l1clk                          (l1clk),
                .grant_a                        (grant_a),
                .grant_x                        (grant_x),
                .qsel0                          (qsel0),
                .qsel0_buf                      (qsel0_buf),
                .shift                          (shift),
                .shift_buf                      (shift_buf));
        ccx_mac_b #(10) mac_b(
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .data_a                         (data_a[9:0]),
                .data_prev_x_l                  (data_prev_x_l[9:0]),
                .data_x_l                       (data_x_l[9:0]),
                .si                             (so5),
                .so                             (scan_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .grant_x                        (grant_x),
                .qsel0_buf                      (qsel0_buf),
                .shift_buf                      (shift_buf));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_mbr_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_mbr_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_pcx_data_a, 
  data_prev_x_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [129:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;


output [129:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [129:0]   src_pcx_data_a;
input [129:0]   data_prev_x_;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan
 
assign src_data_a[129:0] = src_pcx_data_a[129:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);


//l1clkhdr_dp_macro gkt_hdra
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

pcx_mbr_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

pcx_mbr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

pcx_mbr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_b AUTO_TEMPLATE
// (
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_prev_x_l   (data_prev_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);

pcx_mbr_dp_ccx_new_macro__type_b_r i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),   // Templated
                .data_prev_x_l          (data_prev_x_[9:0]),
  .se(se));     // Templated

pcx_mbr_dp_ccx_new_macro__type_b_r i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),  // Templated
                .data_prev_x_l          (data_prev_x_[19:10]),
  .se(se));    // Templated

pcx_mbr_dp_ccx_new_macro__type_b_r i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]), // Templated
                .data_prev_x_l          (data_prev_x_[29:20]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]), // Templated
                .data_prev_x_l          (data_prev_x_[39:30]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]), // Templated
                .data_prev_x_l          (data_prev_x_[49:40]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]), // Templated
                .data_prev_x_l          (data_prev_x_[59:50]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]), // Templated
                .data_prev_x_l          (data_prev_x_[69:60]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]), // Templated
                .data_prev_x_l          (data_prev_x_[79:70]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]), // Templated
                .data_prev_x_l          (data_prev_x_[89:80]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]), // Templated
                .data_prev_x_l          (data_prev_x_[99:90]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]), // Templated
                 .data_prev_x_l         (data_prev_x_[109:100]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]), // Templated
                 .data_prev_x_l         (data_prev_x_[119:110]),
  .se(se));   // Templated
pcx_mbr_dp_ccx_new_macro__type_b_r i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]), // Templated
                 .data_prev_x_l         (data_prev_x_[129:120]),
  .se(se));   // Templated
// fixscan start:
assign i12_scanin                 = scan_in                  ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//   
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//
//nand_macro i_nand_data_prev_2 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_prev_x_[129:90]),
// .dout	(data_out_x[129:90])
// );
//
//nand_macro i_nand_data_prev_1 (width=50, ports=2, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_prev_x_[89:40]),
// .dout	(data_out_x[89:40])
// );
//
//nand_macro i_nand_data_prev_0 (width=40, ports=2, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_prev_x_[39:0]),
// .dout	(data_out_x[39:0])
// );
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
//
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   buff macro
//
//


module pcx_mbr_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_mbr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_mbr_dp_ccx_new_macro__type_b_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_prev_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_prev_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_b #(10)  mac_b(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_prev_x_l(data_prev_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA

`timescale 1 ns / 100 ps
module pcx_mbr_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_pcx_data_a, data_prev_x_, l2clk, 
	scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, tcu_scan_en, scan_out, 
	ccx_aclk_out, ccx_bclk_out, tcu_pce_ov_out, tcu_scan_en_out);

	output	[129:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[129:0]		src_pcx_data_a;
	input	[129:0]		data_prev_x_;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[129:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[129:0] = src_pcx_data_a[129:0];
	assign i12_scanin = scan_in;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_b_r i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.data_prev_x_l			(data_prev_x_[9:0]), 
		.se				(se));
	ccx_new_macro__type_b_r i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.data_prev_x_l			(data_prev_x_[19:10]), 
		.se				(se));
	ccx_new_macro__type_b_r i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.data_prev_x_l			(data_prev_x_[29:20]), 
		.se				(se));
	ccx_new_macro__type_b_r i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.data_prev_x_l			(data_prev_x_[39:30]), 
		.se				(se));
	ccx_new_macro__type_b_r i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.data_prev_x_l			(data_prev_x_[49:40]), 
		.se				(se));
	ccx_new_macro__type_b_r i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.data_prev_x_l			(data_prev_x_[59:50]), 
		.se				(se));
	ccx_new_macro__type_b_r i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.data_prev_x_l			(data_prev_x_[69:60]), 
		.se				(se));
	ccx_new_macro__type_b_r i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.data_prev_x_l			(data_prev_x_[79:70]), 
		.se				(se));
	ccx_new_macro__type_b_r i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.data_prev_x_l			(data_prev_x_[89:80]), 
		.se				(se));
	ccx_new_macro__type_b_r i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.data_prev_x_l			(data_prev_x_[99:90]), 
		.se				(se));
	ccx_new_macro__type_b_r i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.data_prev_x_l			(data_prev_x_[109:100]), 
		.se				(se));
	ccx_new_macro__type_b_r i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.data_prev_x_l			(data_prev_x_[119:110]), 
		.se				(se));
	ccx_new_macro__type_b_r i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.data_prev_x_l			(data_prev_x_[129:120]), 
		.se				(se));
endmodule

module ccx_new_macro__type_b_r(l2clk, l1clk, pce0, pce1, pce_ov, se, stop,
        siclk_in, soclk_in, scan_in, grant_a, qsel0, shift, data_a,
        data_prev_x_l, data_x_l, scan_out);

        input                   l2clk;
        input                   l1clk;
        input                   pce0;
        input                   pce1;
        input                   pce_ov;
        input                   se;
        input                   stop;
        input                   siclk_in;
        input                   soclk_in;
        input                   scan_in;
        input                   grant_a;
        input                   qsel0;
        input                   shift;
        input   [9:0]           data_a;
        input   [9:0]           data_prev_x_l;
        output  [9:0]           data_x_l;
        output                  scan_out;

        wire                    so5;
        wire                    siclk_out;
        wire                    soclk_out;
        wire                    l1clk0;
        wire                    l1clk1;
        wire                    grant_x;
        wire                    qsel0_buf;
        wire                    shift_buf;

        cl_dp1_ccxhdr c0(
                .si                             (scan_in),
                .so                             (so5),
                .l2clk                          (l2clk),
                .pce0                           (pce0),
                .pce1                           (pce1),
                .pce_ov                         (pce_ov),
                .stop                           (stop),
                .siclk_in                       (siclk_in),
                .soclk_in                       (soclk_in),
                .siclk_out                      (siclk_out),
                .soclk_out                      (soclk_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .se                             (se),
                .l1clk                          (l1clk),
                .grant_a                        (grant_a),
                .grant_x                        (grant_x),
                .qsel0                          (qsel0),
                .qsel0_buf                      (qsel0_buf),
                .shift                          (shift),
                .shift_buf                      (shift_buf));
        ccx_mac_b #(10) mac_b(
                .siclk                          (siclk_out),
                .soclk                          (soclk_out),
                .data_a                         (data_a[9:0]),
                .data_prev_x_l                  (data_prev_x_l[9:0]),
                .data_x_l                       (data_x_l[9:0]),
                .si                             (so5),
                .so                             (scan_out),
                .l1clk0                         (l1clk0),
                .l1clk1                         (l1clk1),
                .grant_x                        (grant_x),
                .qsel0_buf                      (qsel0_buf),
                .shift_buf                      (shift_buf));
endmodule


`endif // `ifdef FPGA


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_mcl_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_mcl_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_pcx_data_a, 
  data_crit_x_, 
  data_ncrit_x_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [129:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;


output [129:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [129:0]   src_pcx_data_a;
input [129:0]   data_crit_x_;
input [129:0]   data_ncrit_x_;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan
 
assign src_data_a[129:0] = src_pcx_data_a[129:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);


//l1clkhdr_dp_macro gkt_hdra
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

pcx_mcl_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

pcx_mcl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

pcx_mcl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_c AUTO_TEMPLATE
// (
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.scan_in  (scan_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_crit_x_l   (data_crit_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_ncrit_x_l   (data_ncrit_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);


pcx_mcl_dp_ccx_new_macro__type_c_l i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),   // Templated
                .data_crit_x_l          (data_crit_x_[9:0]),     // Templated
                .data_ncrit_x_l         (data_ncrit_x_[9:0]),
  .se(se));    // Templated

pcx_mcl_dp_ccx_new_macro__type_c_l i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),  // Templated
                .data_crit_x_l          (data_crit_x_[19:10]),    // Templated
                .data_ncrit_x_l         (data_ncrit_x_[19:10]),
  .se(se));   // Templated

pcx_mcl_dp_ccx_new_macro__type_c_l i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]), // Templated
                .data_crit_x_l          (data_crit_x_[29:20]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[29:20]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]), // Templated
                .data_crit_x_l          (data_crit_x_[39:30]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[39:30]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]), // Templated
                .data_crit_x_l          (data_crit_x_[49:40]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[49:40]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]), // Templated
                .data_crit_x_l          (data_crit_x_[59:50]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[59:50]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]), // Templated
                .data_crit_x_l          (data_crit_x_[69:60]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[69:60]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]), // Templated
                .data_crit_x_l          (data_crit_x_[79:70]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[79:70]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]), // Templated
                .data_crit_x_l          (data_crit_x_[89:80]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[89:80]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]), // Templated
                .data_crit_x_l          (data_crit_x_[99:90]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[99:90]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]), // Templated
                 .data_crit_x_l         (data_crit_x_[109:100]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[109:100]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]), // Templated
                 .data_crit_x_l         (data_crit_x_[119:110]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[119:110]),
  .se(se));  // Templated
pcx_mcl_dp_ccx_new_macro__type_c_l i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]), // Templated
                 .data_crit_x_l         (data_crit_x_[129:120]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[129:120]),
  .se(se));  // Templated

// fixscan start:
assign i12_scanin                 = scan_in                  ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   buff macro
//
//


module pcx_mcl_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_mcl_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_mcl_dp_ccx_new_macro__type_c_l (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule
`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_mcl_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_pcx_data_a, data_crit_x_, 
	data_ncrit_x_, l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, 
	tcu_scan_en, scan_out, ccx_aclk_out, ccx_bclk_out, tcu_pce_ov_out, 
	tcu_scan_en_out);

	output	[129:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[129:0]		src_pcx_data_a;
	input	[129:0]		data_crit_x_;
	input	[129:0]		data_ncrit_x_;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[129:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[129:0] = src_pcx_data_a[129:0];
	assign i12_scanin = scan_in;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_c_l i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.data_crit_x_l			(data_crit_x_[9:0]), 
		.data_ncrit_x_l			(data_ncrit_x_[9:0]), 
		.se				(se));
	ccx_new_macro__type_c_l i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.data_crit_x_l			(data_crit_x_[19:10]), 
		.data_ncrit_x_l			(data_ncrit_x_[19:10]), 
		.se				(se));
	ccx_new_macro__type_c_l i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.data_crit_x_l			(data_crit_x_[29:20]), 
		.data_ncrit_x_l			(data_ncrit_x_[29:20]), 
		.se				(se));
	ccx_new_macro__type_c_l i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.data_crit_x_l			(data_crit_x_[39:30]), 
		.data_ncrit_x_l			(data_ncrit_x_[39:30]), 
		.se				(se));
	ccx_new_macro__type_c_l i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.data_crit_x_l			(data_crit_x_[49:40]), 
		.data_ncrit_x_l			(data_ncrit_x_[49:40]), 
		.se				(se));
	ccx_new_macro__type_c_l i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.data_crit_x_l			(data_crit_x_[59:50]), 
		.data_ncrit_x_l			(data_ncrit_x_[59:50]), 
		.se				(se));
	ccx_new_macro__type_c_l i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.data_crit_x_l			(data_crit_x_[69:60]), 
		.data_ncrit_x_l			(data_ncrit_x_[69:60]), 
		.se				(se));
	ccx_new_macro__type_c_l i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.data_crit_x_l			(data_crit_x_[79:70]), 
		.data_ncrit_x_l			(data_ncrit_x_[79:70]), 
		.se				(se));
	ccx_new_macro__type_c_l i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.data_crit_x_l			(data_crit_x_[89:80]), 
		.data_ncrit_x_l			(data_ncrit_x_[89:80]), 
		.se				(se));
	ccx_new_macro__type_c_l i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.data_crit_x_l			(data_crit_x_[99:90]), 
		.data_ncrit_x_l			(data_ncrit_x_[99:90]), 
		.se				(se));
	ccx_new_macro__type_c_l i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.data_crit_x_l			(data_crit_x_[109:100]), 
		.data_ncrit_x_l			(data_ncrit_x_[109:100]), 
		.se				(se));
	ccx_new_macro__type_c_l i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.data_crit_x_l			(data_crit_x_[119:110]), 
		.data_ncrit_x_l			(data_ncrit_x_[119:110]), 
		.se				(se));
	ccx_new_macro__type_c_l i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.data_crit_x_l			(data_crit_x_[129:120]), 
		.data_ncrit_x_l			(data_ncrit_x_[129:120]), 
		.se				(se));
endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_mcr_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_mcr_dp (
  data_out_x_, 
  arb_grant_a, 
  arb_qsel0_a, 
  arb_qsel1_a, 
  arb_q0_holdbar_a, 
  arb_shift_a, 
  src_pcx_data_a, 
  data_crit_x_, 
  data_ncrit_x_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  ccx_aclk, 
  ccx_bclk, 
  tcu_scan_en, 
  scan_out, 
  ccx_aclk_out, 
  ccx_bclk_out, 
  tcu_pce_ov_out, 
  tcu_scan_en_out);
wire pce_ov;
wire stop;
wire siclk_in;
wire soclk_in;
wire se;
wire [129:0] src_data_a;
wire l1clka;
wire l1clkb;
wire i0_scanin;
wire i0_scanout;
wire i1_scanin;
wire i1_scanout;
wire i2_scanin;
wire i2_scanout;
wire i3_scanin;
wire i3_scanout;
wire i4_scanin;
wire i4_scanout;
wire i5_scanin;
wire i5_scanout;
wire i6_scanin;
wire i6_scanout;
wire i7_scanin;
wire i7_scanout;
wire i8_scanin;
wire i8_scanout;
wire i9_scanin;
wire i9_scanout;
wire i10_scanin;
wire i10_scanout;
wire i11_scanin;
wire i11_scanout;
wire i12_scanin;
wire i12_scanout;


output [129:0] 	data_out_x_;

input           arb_grant_a;
input           arb_qsel0_a;
input           arb_qsel1_a;
input           arb_q0_holdbar_a;
input           arb_shift_a;


input [129:0]   src_pcx_data_a;
input [129:0]   data_crit_x_;
input [129:0]   data_ncrit_x_;

// globals
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           ccx_aclk;
input           ccx_bclk;
input           tcu_scan_en;

output          scan_out;

// buffer the high fanout nets 
output          ccx_aclk_out;
output          ccx_bclk_out;
output          tcu_pce_ov_out;
output          tcu_scan_en_out;

// scan renames
assign pce_ov = tcu_pce_ov_out;
assign stop = 1'b0;
assign siclk_in = ccx_aclk_out;
assign soclk_in = ccx_bclk_out;
assign se = tcu_scan_en_out ;
// end scan
 
assign src_data_a[129:0] = src_pcx_data_a[129:0];

//cl_dp1_l1hdr_24x gkt_hdr (
//.l2clk(l2clk),
//.pce(1'b1),
//.aclk(siclk),
//.bclk(soclk),
//.siclk_out(siclk_out_unused),
//.soclk_out(soclk_out_unused),
//.l1clk(l1clk),
//.pce_ov(pce_ov),
//.stop(stop)
//);


//l1clkhdr_dp_macro gkt_hdra
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sia_unused),
//   .soclk_out (soa_unused),
//   .l1clk  (l1clka)
//   );
  
//l1clkhdr_dp_macro gkt_hdrb
//  (
//   .l2clk  (l2clk),
//   .l1en   (1'b1 ),
//   .siclk_out (sib_unused),
//   .soclk_out (sob_unused),
//   .l1clk  (l1clkb)
//   );

pcx_mcr_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn     (
	.din	({ccx_aclk,ccx_bclk, tcu_pce_ov, tcu_scan_en}),
	.dout	({ccx_aclk_out,ccx_bclk_out,tcu_pce_ov_out,tcu_scan_en_out})
);

pcx_mcr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clka),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

pcx_mcr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb 
  (
   .l2clk  (l2clk),
   .l1en   (1'b1 ),
   .l1clk  (l1clkb),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

//   ccx_new_macro_c AUTO_TEMPLATE
// (
//.l2clk    (l2clk),
//.l1clk    (l1clk),                       
//.pce0     (arb_q0_holdbar_a),
//.pce1     (arb_qsel1_a),
//.pce_ov   (pce_ov),
//.stop     (stop),
//.siclk_in (siclk_in),
//.soclk_in (soclk_in),
//.scan_in  (scan_in),
//.grant_a  (arb_grant_a),
//.qsel0    (arb_qsel0_a),
//.shift    (arb_shift_a),
//.data_a   (src_data_a[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_crit_x_l   (data_crit_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_ncrit_x_l   (data_ncrit_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//.data_x_l (data_out_x_[@"(+ 9 (* 10 @))":@"(* 10 @)"]),
//);


pcx_mcr_dp_ccx_new_macro__type_c_r i0  (
                // Outputs
                .data_x_l               (data_out_x_[9:0]),      // Templated
                // Inputs
                .scan_in(i0_scanin),
                .scan_out(i0_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[9:0]),   // Templated
                .data_crit_x_l          (data_crit_x_[9:0]),     // Templated
                .data_ncrit_x_l         (data_ncrit_x_[9:0]),
  .se(se));    // Templated

pcx_mcr_dp_ccx_new_macro__type_c_r i1  (
                // Outputs
                .data_x_l               (data_out_x_[19:10]),     // Templated
                // Inputs
                .scan_in(i1_scanin),
                .scan_out(i1_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[19:10]),  // Templated
                .data_crit_x_l          (data_crit_x_[19:10]),    // Templated
                .data_ncrit_x_l         (data_ncrit_x_[19:10]),
  .se(se));   // Templated

pcx_mcr_dp_ccx_new_macro__type_c_r i2  (
                // Outputs
                .data_x_l               (data_out_x_[29:20]),    // Templated
                // Inputs
                .scan_in(i2_scanin),
                .scan_out(i2_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[29:20]), // Templated
                .data_crit_x_l          (data_crit_x_[29:20]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[29:20]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i3  (
                // Outputs
                .data_x_l               (data_out_x_[39:30]),    // Templated
                // Inputs
                .scan_in(i3_scanin),
                .scan_out(i3_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[39:30]), // Templated
                .data_crit_x_l          (data_crit_x_[39:30]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[39:30]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i4  (
                // Outputs
                .data_x_l               (data_out_x_[49:40]),    // Templated
                // Inputs
                .scan_in(i4_scanin),
                .scan_out(i4_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[49:40]), // Templated
                .data_crit_x_l          (data_crit_x_[49:40]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[49:40]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i5  (
                // Outputs
                .data_x_l               (data_out_x_[59:50]),    // Templated
                // Inputs
                .scan_in(i5_scanin),
                .scan_out(i5_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[59:50]), // Templated
                .data_crit_x_l          (data_crit_x_[59:50]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[59:50]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i6  (
                // Outputs
                .data_x_l               (data_out_x_[69:60]),    // Templated
                // Inputs
                .scan_in(i6_scanin),
                .scan_out(i6_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clka),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[69:60]), // Templated
                .data_crit_x_l          (data_crit_x_[69:60]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[69:60]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i7  (
                // Outputs
                .data_x_l               (data_out_x_[79:70]),    // Templated
                // Inputs
                .scan_in(i7_scanin),
                .scan_out(i7_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[79:70]), // Templated
                .data_crit_x_l          (data_crit_x_[79:70]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[79:70]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i8  (
                // Outputs
                .data_x_l               (data_out_x_[89:80]),    // Templated
                // Inputs
                .scan_in(i8_scanin),
                .scan_out(i8_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[89:80]), // Templated
                .data_crit_x_l          (data_crit_x_[89:80]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[89:80]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i9  (
                // Outputs
                .data_x_l               (data_out_x_[99:90]),    // Templated
                // Inputs
                .scan_in(i9_scanin),
                .scan_out(i9_scanout),
                .l2clk                  (l2clk),                 // Templated
                .l1clk                  (l1clkb),                 // Templated
                .pce0                   (arb_q0_holdbar_a),      // Templated
                .pce1                   (arb_qsel1_a),           // Templated
                .pce_ov                 (pce_ov),            // Templated
                .stop                   (stop),          // Templated
                .siclk_in               (siclk_in),          // Templated
                .soclk_in               (soclk_in),           // Templated
                .grant_a                (arb_grant_a),           // Templated
                .qsel0                  (arb_qsel0_a),           // Templated
                .shift                  (arb_shift_a),           // Templated
                .data_a                 (src_data_a[99:90]), // Templated
                .data_crit_x_l          (data_crit_x_[99:90]),   // Templated
                .data_ncrit_x_l         (data_ncrit_x_[99:90]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i10  (
                 // Outputs
                 .data_x_l              (data_out_x_[109:100]),    // Templated
                 // Inputs
                 .scan_in(i10_scanin),
                 .scan_out(i10_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[109:100]), // Templated
                 .data_crit_x_l         (data_crit_x_[109:100]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[109:100]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i11  (
                 // Outputs
                 .data_x_l              (data_out_x_[119:110]),    // Templated
                 // Inputs
                 .scan_in(i11_scanin),
                 .scan_out(i11_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[119:110]), // Templated
                 .data_crit_x_l         (data_crit_x_[119:110]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[119:110]),
  .se(se));  // Templated
pcx_mcr_dp_ccx_new_macro__type_c_r i12  (
                 // Outputs
                 .data_x_l              (data_out_x_[129:120]),    // Templated
                 // Inputs
                 .scan_in(i12_scanin),
                 .scan_out(i12_scanout),
                 .l2clk                 (l2clk),                 // Templated
                 .l1clk                 (l1clkb),                 // Templated
                 .pce0                  (arb_q0_holdbar_a),      // Templated
                 .pce1                  (arb_qsel1_a),           // Templated
                 .pce_ov                (pce_ov),            // Templated
                 .stop                  (stop),          // Templated
                 .siclk_in              (siclk_in),          // Templated
                 .soclk_in              (soclk_in),           // Templated
                 .grant_a               (arb_grant_a),           // Templated
                 .qsel0                 (arb_qsel0_a),           // Templated
                 .shift                 (arb_shift_a),           // Templated
                 .data_a                (src_data_a[129:120]), // Templated
                 .data_crit_x_l         (data_crit_x_[129:120]),   // Templated
                 .data_ncrit_x_l        (data_ncrit_x_[129:120]),
  .se(se));  // Templated

// fixscan start:
assign i12_scanin                 = scan_in                  ;
assign i11_scanin                 = i12_scanout              ;
assign i10_scanin                 = i11_scanout              ;
assign i9_scanin                  = i10_scanout              ;
assign i8_scanin                  = i9_scanout               ;
assign i7_scanin                  = i8_scanout               ;
assign i6_scanin                  = i7_scanout               ;
assign i5_scanin                  = i6_scanout               ;
assign i4_scanin                  = i5_scanout               ;
assign i3_scanin                  = i4_scanout               ;
assign i2_scanin                  = i3_scanout               ;
assign i1_scanin                  = i2_scanout               ;
assign i0_scanin                  = i1_scanout               ;
assign scan_out                   = i0_scanout               ;
// fixscan end:
endmodule

//
//// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = tcu_aclk;
//assign soclk = tcu_bclk;
//// end scan
//
//buff_macro i_buf_grant (width=1, stack=30c)
//(
// .din (arb_grant_a),
// .dout (grant_a),
// );
//
//msff_macro i_dff_grant_x (width=12, stack=30c) 
//(
// .scan_in(i_dff_grant_x_scanin),
// .scan_out(i_dff_grant_x_scanout),
// .clk	        (l2clk),
// .din           ({12{grant_a}}),
// .dout          (grant_x[11:0]),
// .en            (1'b1),
// );
//
//// DATAPATH SECTION
//
//msff_macro i_dff_q1_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_2_scanin),
// .scan_out(i_dff_q1_2_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[129:90]),
// .dout          (q1_dataout[129:90]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q1_1_scanin),
// .scan_out(i_dff_q1_1_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[89:40]),
// .dout          (q1_dataout[89:40]),
// .en            (arb_qsel1_a),
// );
//
//msff_macro i_dff_q1_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q1_0_scanin),
// .scan_out(i_dff_q1_0_scanout),
// .clk	        (l2clk),
// .din           (src_pcx_data_a[39:0]),
// .dout          (q1_dataout[39:0]),
// .en            (arb_qsel1_a),
// );
//
////assign q0_datain_ca[149:0] = 
////             (arb_pcxdp_qsel0_ca ? src_pcx_data_ca[149:0] : 150'd0) |
////	     (arb_pcxdp_shift_cx ? q1_dataout[149:0] : 150'd0) ;
//
//
//mux_macro i_mux_q0_2 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[129:90]),
// .din1   (q1_dataout[129:90]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[129:90]),
// );
//
//mux_macro i_mux_q0_1 (width=50, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[89:40]),
// .din1   (q1_dataout[89:40]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[89:40]),
// );
//
//mux_macro i_mux_q0_0 (width=40, mux=aonpe, ports=2, stack=50c) 
//(
// .din0   (src_pcx_data_a[39:0]),
// .din1   (q1_dataout[39:0]),
// .sel0   (arb_qsel0_a),
// .sel1   (arb_shift_a),
// .dout   (q0_datain_a[39:0]),
// );
//
//msff_macro i_dff_q0_2 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_2_scanin),
// .scan_out(i_dff_q0_2_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[129:90]),
// .dout          (q0_dataout[129:90]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_1 (width=50, stack=50c) 
//(
// .scan_in(i_dff_q0_1_scanin),
// .scan_out(i_dff_q0_1_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[89:40]),
// .dout          (q0_dataout[89:40]),
// .en            (arb_q0_holdbar_a),
// );
//
//msff_macro i_dff_q0_0 (width=40, stack=50c) 
//(
// .scan_in(i_dff_q0_0_scanin),
// .scan_out(i_dff_q0_0_scanout),
// .clk	        (l2clk),
// .din           (q0_datain_a[39:0]),
// .dout          (q0_dataout[39:0]),
// .en            (arb_q0_holdbar_a),
// );
//
////MUX
//
//nand_macro i_nand_data_g_2 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[129:90]),
// .din1   ({{10{grant_x[11]}},{10{grant_x[10]}},{10{grant_x[9]}},{10{grant_x[8]}}}),
// .dout   (data_x_[129:90]),
// );
// 	 
//nand_macro i_nand_data_g_1 (width=50, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[89:40]),
// .din1   ({{10{grant_x[7]}},{15{grant_x[6]}},{15{grant_x[5]}},{10{grant_x[4]}}}),
// .dout   (data_x_[89:40]),
// );
// 	 
//nand_macro i_nand_data_g_0 (width=40, ports=2, stack=50c) 
//(
// .din0   (q0_dataout[39:0]),
// .din1   ({{10{grant_x[3]}},{10{grant_x[2]}},{10{grant_x[1]}},{10{grant_x[0]}}}),
// .dout   (data_x_[39:0]),
// );
// 	 
//nand_macro i_nand_data_crit_2 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[129:90]),
// .din1	(data_crit_x_[129:90]),
// .din2	(data_ncrit_x_[129:90]),
// .dout	(data_out_x[129:90])
//);
//
//nand_macro i_nand_data_crit_1 (width=50, ports=3, stack=50c) 
//(
// .din0	(data_x_[89:40]),
// .din1	(data_crit_x_[89:40]),
// .din2	(data_ncrit_x_[89:40]),
// .dout	(data_out_x[89:40])
//);
//
//nand_macro i_nand_data_crit_0 (width=40, ports=3, stack=50c) 
//(
// .din0	(data_x_[39:0]),
// .din1	(data_crit_x_[39:0]),
// .din2	(data_ncrit_x_[39:0]),
// .dout	(data_out_x[39:0])
//);
//
//inv_macro i_inv_data_out_2 (width=40, stack=50c) 
//(
// .din	(data_out_x[129:90]),
// .dout	(data_out_x_[129:90])
// );
//
//inv_macro i_inv_data_out_1 (width=50, stack=50c) 
//(
// .din	(data_out_x[89:40]),
// .dout	(data_out_x_[89:40])
// );
//
//inv_macro i_inv_data_out_0 (width=40, stack=50c) 
//(
// .din	(data_out_x[39:0]),
// .dout	(data_out_x_[39:0])
// );
//
//// fixscan start:
//assign i_dff_grant_x_scanin      = scan_in                  ;
//assign i_dff_q1_2_scanin         = i_dff_grant_x_scanout    ;
//assign i_dff_q1_1_scanin         = i_dff_q1_2_scanout       ;
//assign i_dff_q1_0_scanin         = i_dff_q1_1_scanout       ;
//assign i_dff_q0_2_scanin         = i_dff_q1_0_scanout       ;
//assign i_dff_q0_1_scanin         = i_dff_q0_2_scanout       ;
//assign i_dff_q0_0_scanin         = i_dff_q0_1_scanout       ;
//assign scan_out                  = i_dff_q0_0_scanout       ;
//// fixscan end:
//endmodule
// Local Variables:
// verilog-library-directories:("." "v")
// verilog-library-files:("./v/ccx_new_macro.v")
// End:
//


//
//   buff macro
//
//


module pcx_mcr_dp_buff_macro__dbuff_8x__stack_none__vertical_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pcx_mcr_dp_ccx_l1clkhdr_ctl_macro__dl1hdr_24x (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_24x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   ccx macro
//
//


module pcx_mcr_dp_ccx_new_macro__type_c_r (
  l2clk, 
  l1clk, 
  pce0, 
  pce1, 
  pce_ov, 
  se, 
  stop, 
  siclk_in, 
  soclk_in, 
  scan_in, 
  grant_a, 
  qsel0, 
  shift, 
  data_a, 
  data_crit_x_l, 
  data_ncrit_x_l, 
  data_x_l, 
  scan_out);
wire so5;
wire siclk_out;
wire soclk_out;
wire l1clk0;
wire l1clk1;
wire grant_x;
wire qsel0_buf;
wire shift_buf;

input l2clk;
input l1clk;
input pce0;
input pce1;
input pce_ov;
input se;
input stop;
input siclk_in;
input soclk_in;
input scan_in;
input grant_a;
input qsel0;
input shift;
input [9:0] data_a;
input [9:0] data_crit_x_l;
input [9:0] data_ncrit_x_l;
output [9:0] data_x_l;
output       scan_out;
cl_dp1_ccxhdr c0 (			
.si(scan_in),    			
.so(so5),
  .l2clk(l2clk),
  .pce0(pce0),
  .pce1(pce1),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_in(siclk_in),
  .soclk_in(soclk_in),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .se(se),
  .l1clk(l1clk),
  .grant_a(grant_a),
  .grant_x(grant_x),
  .qsel0(qsel0),
  .qsel0_buf(qsel0_buf),
  .shift(shift),
  .shift_buf(shift_buf)    				
);					


ccx_mac_c #(10)  mac_c(
.siclk(siclk_out),			
.soclk(soclk_out),			
.data_a(data_a[9:0]),			
.data_crit_x_l(data_crit_x_l[9:0]),   
.data_ncrit_x_l(data_ncrit_x_l[9:0]),   
.data_x_l(data_x_l[9:0]),		
.si(so5),                         	
.so(scan_out),
  .l1clk0(l1clk0),
  .l1clk1(l1clk1),
  .grant_x(grant_x),
  .qsel0_buf(qsel0_buf),
  .shift_buf(shift_buf)		
);


endmodule
`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_mcr_dp(data_out_x_, arb_grant_a, arb_qsel0_a, arb_qsel1_a, 
	arb_q0_holdbar_a, arb_shift_a, src_pcx_data_a, data_crit_x_, 
	data_ncrit_x_, l2clk, scan_in, tcu_pce_ov, ccx_aclk, ccx_bclk, 
	tcu_scan_en, scan_out, ccx_aclk_out, ccx_bclk_out, tcu_pce_ov_out, 
	tcu_scan_en_out);

	output	[129:0]		data_out_x_;
	input			arb_grant_a;
	input			arb_qsel0_a;
	input			arb_qsel1_a;
	input			arb_q0_holdbar_a;
	input			arb_shift_a;
	input	[129:0]		src_pcx_data_a;
	input	[129:0]		data_crit_x_;
	input	[129:0]		data_ncrit_x_;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			ccx_aclk;
	input			ccx_bclk;
	input			tcu_scan_en;
	output			scan_out;
	output			ccx_aclk_out;
	output			ccx_bclk_out;
	output			tcu_pce_ov_out;
	output			tcu_scan_en_out;

	wire			pce_ov;
	wire			stop;
	wire			siclk_in;
	wire			soclk_in;
	wire			se;
	wire	[129:0]		src_data_a;
	wire			l1clka;
	wire			l1clkb;
	wire			i0_scanin;
	wire			i0_scanout;
	wire			i1_scanin;
	wire			i1_scanout;
	wire			i2_scanin;
	wire			i2_scanout;
	wire			i3_scanin;
	wire			i3_scanout;
	wire			i4_scanin;
	wire			i4_scanout;
	wire			i5_scanin;
	wire			i5_scanout;
	wire			i6_scanin;
	wire			i6_scanout;
	wire			i7_scanin;
	wire			i7_scanout;
	wire			i8_scanin;
	wire			i8_scanout;
	wire			i9_scanin;
	wire			i9_scanout;
	wire			i10_scanin;
	wire			i10_scanout;
	wire			i11_scanin;
	wire			i11_scanout;
	wire			i12_scanin;
	wire			i12_scanout;

	assign pce_ov = tcu_pce_ov_out;
	assign stop = 1'b0;
	assign siclk_in = ccx_aclk_out;
	assign soclk_in = ccx_bclk_out;
	assign se = tcu_scan_en_out;
	assign src_data_a[129:0] = src_pcx_data_a[129:0];
	assign i12_scanin = scan_in;
	assign i11_scanin = i12_scanout;
	assign i10_scanin = i11_scanout;
	assign i9_scanin = i10_scanout;
	assign i8_scanin = i9_scanout;
	assign i7_scanin = i8_scanout;
	assign i6_scanin = i7_scanout;
	assign i5_scanin = i6_scanout;
	assign i4_scanin = i5_scanout;
	assign i3_scanin = i4_scanout;
	assign i2_scanin = i3_scanout;
	assign i1_scanin = i2_scanout;
	assign i0_scanin = i1_scanout;
	assign scan_out = i0_scanout;

	buff_macro__dbuff_8x__stack_none__vertical_1__width_4 buf_hfn(
		.din				({ccx_aclk, ccx_bclk,
		tcu_pce_ov, tcu_scan_en}), 
		.dout				({ccx_aclk_out, ccx_bclk_out,
		tcu_pce_ov_out, tcu_scan_en_out}));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdra(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clka), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_l1clkhdr_ctl_macro__dl1hdr_24x gkt_hdrb(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.l1clk				(l1clkb), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.se				(se));
	ccx_new_macro__type_c_r i0(
		.data_x_l			(data_out_x_[9:0]), 
		.scan_in			(i0_scanin), 
		.scan_out			(i0_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[9:0]), 
		.data_crit_x_l			(data_crit_x_[9:0]), 
		.data_ncrit_x_l			(data_ncrit_x_[9:0]), 
		.se				(se));
	ccx_new_macro__type_c_r i1(
		.data_x_l			(data_out_x_[19:10]), 
		.scan_in			(i1_scanin), 
		.scan_out			(i1_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[19:10]), 
		.data_crit_x_l			(data_crit_x_[19:10]), 
		.data_ncrit_x_l			(data_ncrit_x_[19:10]), 
		.se				(se));
	ccx_new_macro__type_c_r i2(
		.data_x_l			(data_out_x_[29:20]), 
		.scan_in			(i2_scanin), 
		.scan_out			(i2_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[29:20]), 
		.data_crit_x_l			(data_crit_x_[29:20]), 
		.data_ncrit_x_l			(data_ncrit_x_[29:20]), 
		.se				(se));
	ccx_new_macro__type_c_r i3(
		.data_x_l			(data_out_x_[39:30]), 
		.scan_in			(i3_scanin), 
		.scan_out			(i3_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[39:30]), 
		.data_crit_x_l			(data_crit_x_[39:30]), 
		.data_ncrit_x_l			(data_ncrit_x_[39:30]), 
		.se				(se));
	ccx_new_macro__type_c_r i4(
		.data_x_l			(data_out_x_[49:40]), 
		.scan_in			(i4_scanin), 
		.scan_out			(i4_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[49:40]), 
		.data_crit_x_l			(data_crit_x_[49:40]), 
		.data_ncrit_x_l			(data_ncrit_x_[49:40]), 
		.se				(se));
	ccx_new_macro__type_c_r i5(
		.data_x_l			(data_out_x_[59:50]), 
		.scan_in			(i5_scanin), 
		.scan_out			(i5_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[59:50]), 
		.data_crit_x_l			(data_crit_x_[59:50]), 
		.data_ncrit_x_l			(data_ncrit_x_[59:50]), 
		.se				(se));
	ccx_new_macro__type_c_r i6(
		.data_x_l			(data_out_x_[69:60]), 
		.scan_in			(i6_scanin), 
		.scan_out			(i6_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clka), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[69:60]), 
		.data_crit_x_l			(data_crit_x_[69:60]), 
		.data_ncrit_x_l			(data_ncrit_x_[69:60]), 
		.se				(se));
	ccx_new_macro__type_c_r i7(
		.data_x_l			(data_out_x_[79:70]), 
		.scan_in			(i7_scanin), 
		.scan_out			(i7_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[79:70]), 
		.data_crit_x_l			(data_crit_x_[79:70]), 
		.data_ncrit_x_l			(data_ncrit_x_[79:70]), 
		.se				(se));
	ccx_new_macro__type_c_r i8(
		.data_x_l			(data_out_x_[89:80]), 
		.scan_in			(i8_scanin), 
		.scan_out			(i8_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[89:80]), 
		.data_crit_x_l			(data_crit_x_[89:80]), 
		.data_ncrit_x_l			(data_ncrit_x_[89:80]), 
		.se				(se));
	ccx_new_macro__type_c_r i9(
		.data_x_l			(data_out_x_[99:90]), 
		.scan_in			(i9_scanin), 
		.scan_out			(i9_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[99:90]), 
		.data_crit_x_l			(data_crit_x_[99:90]), 
		.data_ncrit_x_l			(data_ncrit_x_[99:90]), 
		.se				(se));
	ccx_new_macro__type_c_r i10(
		.data_x_l			(data_out_x_[109:100]), 
		.scan_in			(i10_scanin), 
		.scan_out			(i10_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[109:100]), 
		.data_crit_x_l			(data_crit_x_[109:100]), 
		.data_ncrit_x_l			(data_ncrit_x_[109:100]), 
		.se				(se));
	ccx_new_macro__type_c_r i11(
		.data_x_l			(data_out_x_[119:110]), 
		.scan_in			(i11_scanin), 
		.scan_out			(i11_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[119:110]), 
		.data_crit_x_l			(data_crit_x_[119:110]), 
		.data_ncrit_x_l			(data_ncrit_x_[119:110]), 
		.se				(se));
	ccx_new_macro__type_c_r i12(
		.data_x_l			(data_out_x_[129:120]), 
		.scan_in			(i12_scanin), 
		.scan_out			(i12_scanout), 
		.l2clk				(l2clk), 
		.l1clk				(l1clkb), 
		.pce0				(arb_q0_holdbar_a), 
		.pce1				(arb_qsel1_a), 
		.pce_ov				(pce_ov), 
		.stop				(stop), 
		.siclk_in			(siclk_in), 
		.soclk_in			(soclk_in), 
		.grant_a			(arb_grant_a), 
		.qsel0				(arb_qsel0_a), 
		.shift				(arb_shift_a), 
		.data_a				(src_data_a[129:120]), 
		.data_crit_x_l			(data_crit_x_[129:120]), 
		.data_ncrit_x_l			(data_ncrit_x_[129:120]), 
		.se				(se));
endmodule


`endif // `ifdef FPGA


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_ob1_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_ob1_dp (
  pcx_sctag_data_px2, 
  pcx_sctag_data_px2_prebuf);
wire [129:0] in;
wire [129:0] in_swz;
wire [129:0] in_px2;
wire [129:0] out_swz;


output [129:0]  pcx_sctag_data_px2;
input [129:0] pcx_sctag_data_px2_prebuf;


assign in[129:0] = pcx_sctag_data_px2_prebuf[129:0];

assign in_swz[64:0] =     {
                           in[128],in[126],in[124],in[122],in[120],
                           in[118],in[116],in[114],in[112],in[110],in[108],in[106],in[104],in[102],in[100],
                           in[98],in[96],in[94],in[92],in[90],in[88],in[86],in[84],in[82],in[80],
                           in[78],in[76],in[74],in[72],in[70],in[68],in[66],in[64],in[62],in[60],
                           in[58],in[56],in[54],in[52],in[50],in[48],in[46],in[44],in[42],in[40],
                           in[38],in[36],in[34],in[32],in[30],in[28],in[26],in[24],in[22],in[20],
                           in[18],in[16],in[14],in[12],in[10],in[8],in[6],in[4],in[2],in[0]
                           };


assign in_swz[129:65] =   {
                           in[129],in[127],in[125],in[123],in[121],
                           in[119],in[117],in[115],in[113],in[111],in[109],in[107],in[105],in[103],in[101],
                           in[99],in[97],in[95],in[93],in[91],in[89],in[87],in[85],in[83],in[81],
                           in[79],in[77],in[75],in[73],in[71],in[69],in[67],in[65],in[63],in[61],
                           in[59],in[57],in[55],in[53],in[51],in[49],in[47],in[45],in[43],in[41],
                           in[39],in[37],in[35],in[33],in[31],in[29],in[27],in[25],in[23],in[21],
                           in[19],in[17],in[15],in[13],in[11],in[9],in[7],in[5],in[3],in[1]
                           };

  
pcx_ob1_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_65 i_buf_data_0     (
	.din	(in_swz[64:0] ),
	.dout	(in_px2[64:0])
);

pcx_ob1_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_65 i_buf_data_1     (
	.din	(in_swz[129:65] ),
	.dout	(in_px2[129:65])
);

assign {
        out_swz[128],out_swz[126],out_swz[124],out_swz[122],out_swz[120],
        out_swz[118],out_swz[116],out_swz[114],out_swz[112],out_swz[110],out_swz[108],out_swz[106],out_swz[104],out_swz[102],out_swz[100],
        out_swz[98],out_swz[96],out_swz[94],out_swz[92],out_swz[90],out_swz[88],out_swz[86],out_swz[84],out_swz[82],out_swz[80],
        out_swz[78],out_swz[76],out_swz[74],out_swz[72],out_swz[70],out_swz[68],out_swz[66],out_swz[64],out_swz[62],out_swz[60],
        out_swz[58],out_swz[56],out_swz[54],out_swz[52],out_swz[50],out_swz[48],out_swz[46],out_swz[44],out_swz[42],out_swz[40],
        out_swz[38],out_swz[36],out_swz[34],out_swz[32],out_swz[30],out_swz[28],out_swz[26],out_swz[24],out_swz[22],out_swz[20],
        out_swz[18],out_swz[16],out_swz[14],out_swz[12],out_swz[10],out_swz[8],out_swz[6],out_swz[4],out_swz[2],out_swz[0]
        } = in_px2[64:0];


assign  {
         out_swz[129],out_swz[127],out_swz[125],out_swz[123],out_swz[121],
         out_swz[119],out_swz[117],out_swz[115],out_swz[113],out_swz[111],out_swz[109],out_swz[107],out_swz[105],out_swz[103],out_swz[101],
         out_swz[99],out_swz[97],out_swz[95],out_swz[93],out_swz[91],out_swz[89],out_swz[87],out_swz[85],out_swz[83],out_swz[81],
         out_swz[79],out_swz[77],out_swz[75],out_swz[73],out_swz[71],out_swz[69],out_swz[67],out_swz[65],out_swz[63],out_swz[61],
         out_swz[59],out_swz[57],out_swz[55],out_swz[53],out_swz[51],out_swz[49],out_swz[47],out_swz[45],out_swz[43],out_swz[41],
         out_swz[39],out_swz[37],out_swz[35],out_swz[33],out_swz[31],out_swz[29],out_swz[27],out_swz[25],out_swz[23],out_swz[21],
         out_swz[19],out_swz[17],out_swz[15],out_swz[13],out_swz[11],out_swz[9],out_swz[7],out_swz[5],out_swz[3],out_swz[1]
         } = in_px2[129:65];


assign pcx_sctag_data_px2[129:0] = out_swz[129:0];


endmodule // pcx_bfs_dp


//
//   buff macro
//
//


module pcx_ob1_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_65 (
  din, 
  dout);
  input [64:0] din;
  output [64:0] dout;


buff #(65)  d0_0 (
.in(din[64:0]),
.out(dout[64:0])
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_ob1_dp(pcx_sctag_data_px2, pcx_sctag_data_px2_prebuf);

	output	[129:0]		pcx_sctag_data_px2;
	input	[129:0]		pcx_sctag_data_px2_prebuf;

	wire	[129:0]		in;
	wire	[129:0]		in_swz;
	wire	[129:0]		in_px2;
	wire	[129:0]		out_swz;

	assign in[129:0] = pcx_sctag_data_px2_prebuf[129:0];
	assign in_swz[64:0] = {in[128], in[126], in[124], in[122], in[120], 
		in[118], in[116], in[114], in[112], in[110], in[108], in[106], 
		in[104], in[102], in[100], in[98], in[96], in[94], in[92], 
		in[90], in[88], in[86], in[84], in[82], in[80], in[78], in[76], 
		in[74], in[72], in[70], in[68], in[66], in[64], in[62], in[60], 
		in[58], in[56], in[54], in[52], in[50], in[48], in[46], in[44], 
		in[42], in[40], in[38], in[36], in[34], in[32], in[30], in[28], 
		in[26], in[24], in[22], in[20], in[18], in[16], in[14], in[12], 
		in[10], in[8], in[6], in[4], in[2], in[0]};
	assign in_swz[129:65] = {in[129], in[127], in[125], in[123], in[121], 
		in[119], in[117], in[115], in[113], in[111], in[109], in[107], 
		in[105], in[103], in[101], in[99], in[97], in[95], in[93], 
		in[91], in[89], in[87], in[85], in[83], in[81], in[79], in[77], 
		in[75], in[73], in[71], in[69], in[67], in[65], in[63], in[61], 
		in[59], in[57], in[55], in[53], in[51], in[49], in[47], in[45], 
		in[43], in[41], in[39], in[37], in[35], in[33], in[31], in[29], 
		in[27], in[25], in[23], in[21], in[19], in[17], in[15], in[13], 
		in[11], in[9], in[7], in[5], in[3], in[1]};
	assign {out_swz[128], out_swz[126], out_swz[124], out_swz[122], 
		out_swz[120], out_swz[118], out_swz[116], out_swz[114], 
		out_swz[112], out_swz[110], out_swz[108], out_swz[106], 
		out_swz[104], out_swz[102], out_swz[100], out_swz[98], 
		out_swz[96], out_swz[94], out_swz[92], out_swz[90], out_swz[88],
		out_swz[86], out_swz[84], out_swz[82], out_swz[80], out_swz[78],
		out_swz[76], out_swz[74], out_swz[72], out_swz[70], out_swz[68],
		out_swz[66], out_swz[64], out_swz[62], out_swz[60], out_swz[58],
		out_swz[56], out_swz[54], out_swz[52], out_swz[50], out_swz[48],
		out_swz[46], out_swz[44], out_swz[42], out_swz[40], out_swz[38],
		out_swz[36], out_swz[34], out_swz[32], out_swz[30], out_swz[28],
		out_swz[26], out_swz[24], out_swz[22], out_swz[20], out_swz[18],
		out_swz[16], out_swz[14], out_swz[12], out_swz[10], out_swz[8], 
		out_swz[6], out_swz[4], out_swz[2], out_swz[0]} = in_px2[64:0];
	assign {out_swz[129], out_swz[127], out_swz[125], out_swz[123], 
		out_swz[121], out_swz[119], out_swz[117], out_swz[115], 
		out_swz[113], out_swz[111], out_swz[109], out_swz[107], 
		out_swz[105], out_swz[103], out_swz[101], out_swz[99], 
		out_swz[97], out_swz[95], out_swz[93], out_swz[91], out_swz[89],
		out_swz[87], out_swz[85], out_swz[83], out_swz[81], out_swz[79],
		out_swz[77], out_swz[75], out_swz[73], out_swz[71], out_swz[69],
		out_swz[67], out_swz[65], out_swz[63], out_swz[61], out_swz[59],
		out_swz[57], out_swz[55], out_swz[53], out_swz[51], out_swz[49],
		out_swz[47], out_swz[45], out_swz[43], out_swz[41], out_swz[39],
		out_swz[37], out_swz[35], out_swz[33], out_swz[31], out_swz[29],
		out_swz[27], out_swz[25], out_swz[23], out_swz[21], out_swz[19],
		out_swz[17], out_swz[15], out_swz[13], out_swz[11], out_swz[9], 
		out_swz[7], out_swz[5], out_swz[3], out_swz[1]} = in_px2[129:65]
		;
	assign pcx_sctag_data_px2[129:0] = out_swz[129:0];

	buff_macro__dbuff_32x__rep_1__stack_66c__width_65 i_buf_data_0(
		.din				(in_swz[64:0]), 
		.dout				(in_px2[64:0]));
	buff_macro__dbuff_32x__rep_1__stack_66c__width_65 i_buf_data_1(
		.din				(in_swz[129:65]), 
		.dout				(in_px2[129:65]));
endmodule
module buff_macro__dbuff_32x__rep_1__stack_66c__width_65(din, dout);

        input   [64:0]          din;
        output  [64:0]          dout;

        buff #(65) d0_0(
                .in                             (din[64:0]),
                .out                            (dout[64:0]));
endmodule


`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pcx_rep_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module pcx_rep_dp (
  mac0_rep_out, 
  mac1_rep_out, 
  mac2_rep_out, 
  mac3_rep_out, 
  mac4_rep_out, 
  mac5_rep_out, 
  mac6_rep_out, 
  scan_rep_out, 
  mac0_rep_in, 
  mac1_rep_in, 
  mac2_rep_in, 
  mac3_rep_in, 
  mac4_rep_in, 
  mac5_rep_in, 
  mac6_rep_in, 
  scan_rep_in);
wire [4:0] mac2_rep_0;
wire [4:0] mac3_rep_0;
wire [4:0] mac4_rep_0;
wire scan_rep7_out;
wire scan_rep5_out;
wire scan_rep3_out;


output [4:0]              mac0_rep_out;
output [4:0]              mac1_rep_out;
output [4:0]              mac2_rep_out;
output [4:0]              mac3_rep_out;
output [4:0]              mac4_rep_out;
output [4:0]              mac5_rep_out;
output [4:0]              mac6_rep_out;
output                    scan_rep_out;


input [4:0]              mac0_rep_in;
input [4:0]              mac1_rep_in;
input [4:0]              mac2_rep_in;
input [4:0]              mac3_rep_in;
input [4:0]              mac4_rep_in;
input [4:0]              mac5_rep_in;
input [4:0]              mac6_rep_in;
input                    scan_rep_in;


//   sparc0 sparc2 sparc1 sparc3  sparc5  sparc7  sparc4  sparc6
//     |      |      |      |       |       |        |      |
//     v      v      v      v       v       v        v      v
//   mac0 -  mac1 - mac2 - mac3  - mac4  - mac5  - mac6  - mac7 


// mac0 input go through 1 buffer
pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0    (
	.din	({mac0_rep_in[4:0]}),
   .dout	({mac0_rep_out[4:0]})
);

// mac1 input go through 1 buffer
pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1    (
	.din	({mac1_rep_in[4:0]}),
   .dout	({mac1_rep_out[4:0]})
);


// mac2 input go through 2 buffers
pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0    (
	.din	({mac2_rep_in[4:0]}),
   .dout	({mac2_rep_0[4:0]})
);

pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1    (
	.din	({mac2_rep_0[4:0]}),
   .dout	({mac2_rep_out[4:0]})
);

// mac3 input go through 2 buffers
pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0    (
	.din	({mac3_rep_in[4:0]}),
   .dout	({mac3_rep_0[4:0]})
);

pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1    (
	.din	({mac3_rep_0[4:0]}),
   .dout	({mac3_rep_out[4:0]})
);

// mac4 input go through 2 buffers
pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0    (
	.din	({mac4_rep_in[4:0]}),
   .dout	({mac4_rep_0[4:0]})
);

pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1    (
	.din	({mac4_rep_0[4:0]}),
   .dout	({mac4_rep_out[4:0]})
);

// mac5 input go through 1 buffer
pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5    (
	.din	({mac5_rep_in[4:0]}),
   .dout	({mac5_rep_out[4:0]})
);

// mac6 input go through 1 buffer
pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6    (
	.din	({mac6_rep_in[4:0]}),
   .dout	({mac6_rep_out[4:0]})
);


// repeat the scan chain

// buffer on top of mac7
pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan7    (
	.din	(scan_rep_in),
   .dout	(scan_rep7_out)
);

// buffer on top of mac5
pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan5    (
	.din	(scan_rep7_out),
   .dout	(scan_rep5_out)
);

// buffer on top of mac3
pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan3    (
	.din	(scan_rep5_out),
   .dout	(scan_rep3_out)
);

// buffer on top of mac1
pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 buf_scan1    (
	.din	(scan_rep3_out),
   .dout	(scan_rep_out)
);

endmodule


//
//   buff macro
//
//


module pcx_rep_dp_buff_macro__dbuff_32x__stack_6l__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module pcx_rep_dp_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
`timescale 1 ns / 100 ps
module pcx_rep_dp(mac0_rep_out, mac1_rep_out, mac2_rep_out, mac3_rep_out, 
	mac4_rep_out, mac5_rep_out, mac6_rep_out, scan_rep_out, mac0_rep_in, 
	mac1_rep_in, mac2_rep_in, mac3_rep_in, mac4_rep_in, mac5_rep_in, 
	mac6_rep_in, scan_rep_in);

	output	[4:0]		mac0_rep_out;
	output	[4:0]		mac1_rep_out;
	output	[4:0]		mac2_rep_out;
	output	[4:0]		mac3_rep_out;
	output	[4:0]		mac4_rep_out;
	output	[4:0]		mac5_rep_out;
	output	[4:0]		mac6_rep_out;
	output			scan_rep_out;
	input	[4:0]		mac0_rep_in;
	input	[4:0]		mac1_rep_in;
	input	[4:0]		mac2_rep_in;
	input	[4:0]		mac3_rep_in;
	input	[4:0]		mac4_rep_in;
	input	[4:0]		mac5_rep_in;
	input	[4:0]		mac6_rep_in;
	input			scan_rep_in;

	wire	[4:0]		mac2_rep_0;
	wire	[4:0]		mac3_rep_0;
	wire	[4:0]		mac4_rep_0;
	wire			scan_rep7_out;
	wire			scan_rep5_out;
	wire			scan_rep3_out;

	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac0(
		.din				({mac0_rep_in[4:0]}), 
		.dout				({mac0_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac1(
		.din				({mac1_rep_in[4:0]}), 
		.dout				({mac1_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_0(
		.din				({mac2_rep_in[4:0]}), 
		.dout				({mac2_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac2_1(
		.din				({mac2_rep_0[4:0]}), 
		.dout				({mac2_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_0(
		.din				({mac3_rep_in[4:0]}), 
		.dout				({mac3_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac3_1(
		.din				({mac3_rep_0[4:0]}), 
		.dout				({mac3_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_0(
		.din				({mac4_rep_in[4:0]}), 
		.dout				({mac4_rep_0[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac4_1(
		.din				({mac4_rep_0[4:0]}), 
		.dout				({mac4_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac5(
		.din				({mac5_rep_in[4:0]}), 
		.dout				({mac5_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_6l__width_5 buf_mac6(
		.din				({mac6_rep_in[4:0]}), 
		.dout				({mac6_rep_out[4:0]}));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan7(
		.din				(scan_rep_in), 
		.dout				(scan_rep7_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan5(
		.din				(scan_rep7_out), 
		.dout				(scan_rep5_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan3(
		.din				(scan_rep5_out), 
		.dout				(scan_rep3_out));
	buff_macro__dbuff_32x__stack_none__width_1 buf_scan1(
		.din				(scan_rep3_out), 
		.dout				(scan_rep_out));
endmodule


`endif // `ifdef FPGA


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: l2t_dmo_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module l2t_dmo_dp (
  tcu_l2t_coresel, 
  l2t_tcu_dmo_out_prev, 
  mbist_dmo_data_out, 
  l2clk, 
  tcu_clk_stop, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  scan_in, 
  scan_out, 
  l2t_tcu_dmo_out, 
  io_cmp_sync_en, 
  tcu_l2t_shscan_clk_stop, 
  tcu_l2t_shscan_clk_stop_d2);
wire stop;
wire pce_ov;
wire siclk;
wire soclk;
wire se;
wire [38:0] l2t_tcu_dmo_out_unreg;
wire ff_dmo_data_scanin;
wire ff_dmo_data_scanout;
wire ff_dmo_data_1_scanin;
wire ff_dmo_data_1_scanout;
wire io_cmp_sync_en_r1;
wire ff_shadow_scan_clk_stop_scanin;
wire ff_shadow_scan_clk_stop_scanout;


input           tcu_l2t_coresel;        // 1= select current bank dmo out
input   [38:0]  l2t_tcu_dmo_out_prev;   // dmo output from prev bank
//input           tcu_l2t_tag_or_data_sel;        
//input	[38:0]  decc_ret_diag_data_c7;     // dmo data tag or data data
//input	[27:0]  tagd_evict_tag_c3;     // dmo data tag or data data
input	[38:0]	mbist_dmo_data_out;

input		l2clk;
input		tcu_clk_stop;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_scan_en;
input		scan_in;
output		scan_out;
output  [38:0]  l2t_tcu_dmo_out;        // dmo output from this bank

input		io_cmp_sync_en;
input		tcu_l2t_shscan_clk_stop;
output		tcu_l2t_shscan_clk_stop_d2;

assign stop = tcu_clk_stop;
assign pce_ov = tcu_pce_ov;
assign siclk = tcu_aclk;
assign soclk = tcu_bclk;
assign se = tcu_scan_en;

//mux_macro  mux_data_tag_dmo_data (width=39,ports=2,mux=aope,stack=39c)
//        (
//        .dout   (mbist_dmo_data_out[38:0]),
//        .din0   ({11'b0,tagd_evict_tag_c3[27:0]}),
//        .din1   (decc_ret_diag_data_c7[38:0]),
//        .sel0   (tcu_l2t_tag_or_data_sel)
//        );
//


l2t_mux_macro__dmux_8x__mux_aope__ports_2__stack_20r__width_19  mux_dmo_data	
	(
	.dout	(l2t_tcu_dmo_out_unreg[18:0]),
	.din0	(l2t_tcu_dmo_out_prev[18:0]),
	.din1	(mbist_dmo_data_out[18:0]),
	.sel0	(tcu_l2t_coresel)
	);

l2t_mux_macro__dmux_8x__mux_aope__ports_2__stack_20r__width_20  mux_dmo_data_1 
        (
        .dout   (l2t_tcu_dmo_out_unreg[38:19]),
        .din0   (l2t_tcu_dmo_out_prev[38:19]),
        .din1   (mbist_dmo_data_out[38:19]),
        .sel0   (tcu_l2t_coresel)
        );


l2t_msff_macro__dmsff_32x__stack_20r__width_19  ff_dmo_data     
	(
	.scan_in(ff_dmo_data_scanin),
	.scan_out(ff_dmo_data_scanout),
	.dout	(l2t_tcu_dmo_out[18:0]),
	.din	(l2t_tcu_dmo_out_unreg[18:0]),
	.clk	(l2clk),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
	);


l2t_msff_macro__dmsff_32x__stack_22r__width_21  ff_dmo_data_1     
        (
        .scan_in(ff_dmo_data_1_scanin),
        .scan_out(ff_dmo_data_1_scanout),
        .dout   ({io_cmp_sync_en_r1,l2t_tcu_dmo_out[38:19]}),
        .din    ({io_cmp_sync_en,l2t_tcu_dmo_out_unreg[38:19]}),
        .clk    (l2clk),
        .en     (1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );


l2t_msff_macro__dmsff_32x__stack_2r__width_1  ff_shadow_scan_clk_stop 
        (
        .scan_in(ff_shadow_scan_clk_stop_scanin),
        .scan_out(ff_shadow_scan_clk_stop_scanout),
        .dout   (tcu_l2t_shscan_clk_stop_d2),
        .din    (tcu_l2t_shscan_clk_stop),
        .clk    (l2clk),
        .en     (io_cmp_sync_en_r1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
        );


// fixscan start:
assign ff_dmo_data_scanin        = scan_in                  ;
assign ff_dmo_data_1_scanin      = ff_dmo_data_scanout      ;
assign ff_shadow_scan_clk_stop_scanin = ff_dmo_data_1_scanout    ;
assign scan_out                  = ff_shadow_scan_clk_stop_scanout;
// fixscan end:
endmodule

// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module l2t_mux_macro__dmux_8x__mux_aope__ports_2__stack_20r__width_19 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [18:0] din0;
  input [18:0] din1;
  input sel0;
  output [18:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(19)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[18:0]),
  .in1(din1[18:0]),
.dout(dout[18:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module l2t_mux_macro__dmux_8x__mux_aope__ports_2__stack_20r__width_20 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [19:0] din0;
  input [19:0] din1;
  input sel0;
  output [19:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(20)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[19:0]),
  .in1(din1[19:0]),
.dout(dout[19:0])
);


endmodule


// any PARAMS parms go into naming of macro

module l2t_msff_macro__dmsff_32x__stack_20r__width_19 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [17:0] so;

  input [18:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [18:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(19)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[18:0]),
.si({scan_in,so[17:0]}),
.so({so[17:0],scan_out}),
.q(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module l2t_msff_macro__dmsff_32x__stack_22r__width_21 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [19:0] so;

  input [20:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [20:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(21)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[20:0]),
.si({scan_in,so[19:0]}),
.so({so[19:0],scan_out}),
.q(dout[20:0])
);


endmodule


// any PARAMS parms go into naming of macro

module l2t_msff_macro__dmsff_32x__stack_2r__width_1 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;

  input [0:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [0:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: l2t_vuad_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module l2t_vuad_ctl (
  l2clk, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  tcu_clk_stop, 
  scan_in, 
  scan_out, 
  rd_addr1, 
  rd_addr2, 
  rd_addr_sel, 
  wr_addr, 
  wr_en0, 
  wr_en1, 
  array_rd_en, 
  bist_vuad_idx_c3, 
  evctag_vuad_idx_c3, 
  bist_wr_vd_c3, 
  arb_decdp_wr64_inst_c2, 
  arb_acc_vd_c2, 
  arb_acc_ua_c2, 
  arbadr_idx_c1c2comp_c1_n, 
  arbadr_idx_c1c3comp_c1_n, 
  arbadr_idx_c1c4comp_c1_n, 
  arbadr_idx_c1c5comp_c1_n, 
  arb_decdp_inst_int_c1, 
  csr_l2_bypass_mode_on, 
  arb_inst_diag_c1, 
  bist_vuad_wr_en, 
  arb_inst_vld_c2, 
  arb_inst_l2vuad_vld_c3, 
  arb_decdp_st_inst_c3, 
  arbdec_arbdp_inst_fb_c2, 
  vuadpm_vd_ue_c4, 
  vuadpm_ua_ue_c4, 
  arbdec_arbdp_inst_way_c2, 
  arb_arbdp_vuadctl_pst_no_ctrue_c2, 
  arb_decdp_cas1_inst_c2, 
  arb_arbdp_pst_with_ctrue_c2, 
  arb_decdp_cas2_inst_c2, 
  arbdec_arbdp_inst_mb_c2, 
  arb_vuadctl_no_bypass_px2, 
  vuaddp_vuad_sel_c2, 
  vuaddp_vuad_sel_c2_d1, 
  vuaddp_vuad_sel_c4, 
  vuaddp_vuad_sel_rd, 
  vuaddp_vuad_tagd_sel_c2_d1, 
  vuaddp_wr64_inst_c3, 
  vuaddp_alloc_set_cond_c3, 
  vuaddp_alloc_rst_cond_c3, 
  vuaddp_vuad_error_c8, 
  vuaddp_fill_way_c3, 
  vuaddp_bistordiag_wr_vd_c4, 
  vuaddp_bistordiag_wr_ua_c4, 
  vuaddp_sel_ua_wr_data_byp, 
  vuaddp_sel_vd_wr_data_byp, 
  vuaddp_sel_diag0_data_wr_c3, 
  vuaddp_sel_diag1_data_wr_c3, 
  vuaddp_vuad_array_wr_en0_c4, 
  vuaddp_vuad_array_wr_en1_c4, 
  vuaddp_vuad_idx_c4, 
  vuad_rd_addr1_r0, 
  vuad_rd_addr2_r0, 
  vuad_rd_addr_sel_r0, 
  vuad_wr_addr_r0, 
  vuad_word_en_r0, 
  vuad_wr_en_r0c0, 
  vuad_wr_en_r0c1, 
  vuad_mux1_h_sel_r0, 
  vuad_mux1_l_sel_r0, 
  vuad_mux2_sel_r0, 
  vuad_rd_en_r0, 
  vuad_rd_addr1_r1, 
  vuad_rd_addr2_r1, 
  vuad_rd_addr_sel_r1, 
  vuad_wr_addr_r1, 
  vuad_word_en_r1, 
  vuad_wr_en_r1c0, 
  vuad_wr_en_r1c1, 
  vuad_rd_en_r1, 
  vuad_rd_addr1_r2, 
  vuad_rd_addr2_r2, 
  vuad_rd_addr_sel_r2, 
  vuad_wr_addr_r2, 
  vuad_word_en_r2, 
  vuad_wr_en_r2c0, 
  vuad_wr_en_r2c1, 
  vuad_mux1_h_sel_r2, 
  vuad_mux1_l_sel_r2, 
  vuad_mux2_sel_r2, 
  vuad_rd_en_r2, 
  vuad_rd_addr1_r3, 
  vuad_rd_addr2_r3, 
  vuad_rd_addr_sel_r3, 
  vuad_wr_addr_r3, 
  vuad_word_en_r3, 
  vuad_wr_en_r3c0, 
  vuad_wr_en_r3c1, 
  vuad_rd_en_r3, 
  vuad_mux_sel, 
  mbist_run, 
  vuad_usaloc_mux_used_and_alloc_comb_sel0, 
  vuad_usaloc_mux_used_and_alloc_comb_sel1, 
  vuad_usaloc_mux_used_and_alloc_comb_sel2, 
  vuad_usaloc_mux_used_and_alloc_comb_sel3, 
  vuad_usaloc_mux_used_and_alloc_comb_sel4, 
  vuad_usaloc_mux_used_and_alloc_comb_sel5, 
  mux_valid_dirty_c1_sel0, 
  mux_valid_dirty_c1_sel1, 
  mux_valid_dirty_c1_sel2);
wire [4:0] wr_addr_entry;
wire [3:0] wr_word_en;
wire [3:0] wr_en;
wire rd_addr_sel_n;
wire [1:0] addr1to0_px2;
wire ff_addr1to0_c1_scanin;
wire ff_addr1to0_c1_scanout;
wire l1clk;
wire [1:0] addr1to0_c1;
wire addr8_px2;
wire ff_addr8_c1_scanin;
wire ff_addr8_c1_scanout;
wire addr8_c1;
wire addr7_px2;
wire ff_addr7_c1_scanin;
wire ff_addr7_c1_scanout;
wire addr7_c1;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire spares_scanin;
wire spares_scanout;
wire ff_vuadctl_no_bypass_c1_scanin;
wire ff_vuadctl_no_bypass_c1_scanout;
wire vuaddp_vuad_sel_c2orc3;
wire vuaddp_vuad_sel_rd_c2;
wire vuadctl_no_bypass_c1_1;
wire ff_vuadctl_no_bypass_c1_1_scanin;
wire ff_vuadctl_no_bypass_c1_1_scanout;
wire ff_vuaddp_vuad_sel_c2_scanin;
wire ff_vuaddp_vuad_sel_c2_scanout;
wire ff_vuaddp_vuad_sel_c2_d1_scanin;
wire ff_vuaddp_vuad_sel_c2_d1_scanout;
wire ff_vuad_sel_wr_d1_scanin;
wire ff_vuad_sel_wr_d1_scanout;
wire vuad_sel_wr_d1;
wire ff_vuad_tagd_sel_c2_d1_scanin;
wire ff_vuad_tagd_sel_c2_d1_scanout;
wire ff_wr64_inst_c3_scanin;
wire ff_wr64_inst_c3_scanout;
wire ff_arb_acc_vd_c3_scanin;
wire ff_arb_acc_vd_c3_scanout;
wire ff_arb_acc_ua_c3_scanin;
wire ff_arb_acc_ua_c3_scanout;
wire ff_inst_vld_c3_scanin;
wire ff_inst_vld_c3_scanout;
wire ff_inst_vld_c4_scanin;
wire ff_inst_vld_c4_scanout;
wire ff_inst_vld_c5_scanin;
wire ff_inst_vld_c5_scanout;
wire ff_arb_inst_diag_c2_scanin;
wire ff_arb_inst_diag_c2_scanout;
wire ff_arb_inst_diag_c3_scanin;
wire ff_arb_inst_diag_c3_scanout;
wire ff_arb_inst_diag_c4_scanin;
wire ff_arb_inst_diag_c4_scanout;
wire mbist_run_r1;
wire ff_mux_idx_c4_scanin;
wire ff_mux_idx_c4_scanout;
wire ff_l2_bypass_mode_on_d1_scanin;
wire ff_l2_bypass_mode_on_d1_scanout;
wire ff_bistordiag_wr_vd_c4_scanin;
wire ff_bistordiag_wr_vd_c4_scanout;
wire ff_bistordiag_wr_ua_c4_scanin;
wire ff_bistordiag_wr_ua_c4_scanout;
wire ff_vuad_array_wr_en0_c4_scanin;
wire ff_vuad_array_wr_en0_c4_scanout;
wire ff_vuad_array_wr_en1_c4_scanin;
wire ff_vuad_array_wr_en1_c4_scanout;
wire ff_vuad_array_wr_en0_c5_scanin;
wire ff_vuad_array_wr_en0_c5_scanout;
wire ff_vuad_array_wr_en1_c5_scanin;
wire ff_vuad_array_wr_en1_c5_scanout;
wire ff_vuad_array_wr_en0_c52_scanin;
wire ff_vuad_array_wr_en0_c52_scanout;
wire ff_vuad_array_wr_en1_c52_scanin;
wire ff_vuad_array_wr_en1_c52_scanout;
wire ff_inst_int_c2_scanin;
wire ff_inst_int_c2_scanout;
wire ff_inst_int_c3_scanin;
wire ff_inst_int_c3_scanout;
wire ff_inst_int_c4_scanin;
wire ff_inst_int_c4_scanout;
wire ff_inst_int_c5_scanin;
wire ff_inst_int_c5_scanout;
wire ff_vuad_error_c5_scanin;
wire ff_vuad_error_c5_scanout;
wire ff_vuad_error_c52_scanin;
wire ff_vuad_error_c52_scanout;
wire ff_vuad_error_c6_scanin;
wire ff_vuad_error_c6_scanout;
wire ff_vuad_error_c7_scanin;
wire ff_vuad_error_c7_scanout;
wire ff_vuad_error_c8_scanin;
wire ff_vuad_error_c8_scanout;
wire ff_fill_way_c3_scanin;
wire ff_fill_way_c3_scanout;
wire ff_alloc_set_cond_c3_scanin;
wire ff_alloc_set_cond_c3_scanout;
wire ff_alloc_rst_cond_c3_scanin;
wire ff_alloc_rst_cond_c3_scanout;


input            l2clk; 
input  		 tcu_pce_ov;
input  		 tcu_aclk;
input  		 tcu_bclk;
input  		 tcu_scan_en;
// l2t_vuad_ctl
input		 tcu_clk_stop;
 
input	 	 scan_in; 
output 		 scan_out; 

//////////////////////////////////////////////////////////////
// l2t_vuad_ctl
//////////////////////////////////////////////////////////////
input	[8:0]	 rd_addr1;
input	[8:0]	 rd_addr2;
input		 rd_addr_sel;
input	[8:0]	 wr_addr;
input		 wr_en0;
input		 wr_en1;
input		 array_rd_en;
//

 
input	[8:0]	bist_vuad_idx_c3 ;
input	[8:0]	evctag_vuad_idx_c3;
input		bist_wr_vd_c3 ;
 
//input	[15:0]	tag_hit_way_vld_c3;
//input	[15:0]	tagdp_lru_way_sel_c3;
//input		tag_st_to_data_array_c3;
input		arb_decdp_wr64_inst_c2;
 
input		arb_acc_vd_c2;	// Top // diagnostic access only 
input		arb_acc_ua_c2;	// Top // diagnostic access only 
 
// C1 outputs 
input  arbadr_idx_c1c2comp_c1_n ; // from arbaddr Top 
input  arbadr_idx_c1c3comp_c1_n ; // from arbaddr Top 
input  arbadr_idx_c1c4comp_c1_n ; // from arbaddr Top 
input  arbadr_idx_c1c5comp_c1_n ; // from arbaddr. POST_3.0 Top 
 
input		arb_decdp_inst_int_c1;	// Top // int 5.0 changes
input		csr_l2_bypass_mode_on;	// Top 
input		arb_inst_diag_c1;	// Top 
input		bist_vuad_wr_en;	// Top // This is a C3 signal. 
input		arb_inst_vld_c2;	// Top 
input		arb_inst_l2vuad_vld_c3; // Top 
input		arb_decdp_st_inst_c3; // Top 
input		arbdec_arbdp_inst_fb_c2; // Top 
 
input		vuadpm_vd_ue_c4;
input		vuadpm_ua_ue_c4;
//input		arb_vuad_ce_err_c3;

input	[3:0]	arbdec_arbdp_inst_way_c2; 
 
input		arb_arbdp_vuadctl_pst_no_ctrue_c2; // Top 
input		arb_decdp_cas1_inst_c2; // Top 
input		arb_arbdp_pst_with_ctrue_c2; // Top 
input		arb_decdp_cas2_inst_c2; // Top 
input		arbdec_arbdp_inst_mb_c2; // Top 
 
input		arb_vuadctl_no_bypass_px2; // Top 
 
 
output		vuaddp_vuad_sel_c2;	// Bottom 
output		vuaddp_vuad_sel_c2_d1;	// Bottom 
output		vuaddp_vuad_sel_c4;	// Bottom 
output		vuaddp_vuad_sel_rd;	// Bottom 
output		vuaddp_vuad_tagd_sel_c2_d1;	// Top 
 
//output		vuaddp_st_to_data_array_c3;	// Bottom 
output		vuaddp_wr64_inst_c3	; // Bottom 
 
 
output		vuaddp_alloc_set_cond_c3; // Bottom 
output		vuaddp_alloc_rst_cond_c3; // Bottom 
 
output		vuaddp_vuad_error_c8; // Bottom 
 
//output	[15:0]	vuaddp_hit_wayvld_c3; // Bottom 
output	[15:0]	vuaddp_fill_way_c3; // Bottom 
//output	[15:0]	vuaddp_lru_way_c3; // Bottom 
 
output		vuaddp_bistordiag_wr_vd_c4   ; // Bottom // bist or diag access 
output		vuaddp_bistordiag_wr_ua_c4   ; // Bottom // bist or diag access 
 
output		vuaddp_sel_ua_wr_data_byp;	// Bottom 
output		vuaddp_sel_vd_wr_data_byp;	// Bottom 
 
output		vuaddp_sel_diag0_data_wr_c3; // Bottom  sel between diagnostic and bist data 
output		vuaddp_sel_diag1_data_wr_c3; // Bottom  sel between diagnostic and bist data 
 
output		vuaddp_vuad_array_wr_en0_c4; // Bottom // Change to C4 
output		vuaddp_vuad_array_wr_en1_c4; // Bottom // Change to C4 
 
output	[8:0]	vuaddp_vuad_idx_c4; // NEW PIN 

// from l2t_vuad_ctl
output	[4:0]	 vuad_rd_addr1_r0;
output	[4:0]	 vuad_rd_addr2_r0;
output		 vuad_rd_addr_sel_r0;
output	[4:0]	 vuad_wr_addr_r0; // address bits 6:2
output	[3:0]	 vuad_word_en_r0; // decoded address bits 1:0
output		 vuad_wr_en_r0c0; // decoded address bits 8:7
output		 vuad_wr_en_r0c1; // decoded address bits 8:7
output	[3:0]	vuad_mux1_h_sel_r0;
output	[3:0]	vuad_mux1_l_sel_r0;
output		vuad_mux2_sel_r0;  //int 5.0 change
output	vuad_rd_en_r0;

output	[4:0]	 vuad_rd_addr1_r1;
output	[4:0]	 vuad_rd_addr2_r1;
output		 vuad_rd_addr_sel_r1;
output	[4:0]	 vuad_wr_addr_r1; // address bits 6:2
output	[3:0]	 vuad_word_en_r1; // decoded address bits 1:0
output		 vuad_wr_en_r1c0; // decoded address bits 8:7
output		 vuad_wr_en_r1c1; // decoded address bits 8:7
output	vuad_rd_en_r1;

output	[4:0]	 vuad_rd_addr1_r2;
output	[4:0]	 vuad_rd_addr2_r2;
output		 vuad_rd_addr_sel_r2;
output	[4:0]	 vuad_wr_addr_r2; // address bits 6:2
output	[3:0]	 vuad_word_en_r2; // decoded address bits 1:0
output		 vuad_wr_en_r2c0; // decoded address bits 8:7
output		 vuad_wr_en_r2c1; // decoded address bits 8:7
output	[3:0]	vuad_mux1_h_sel_r2;
output	[3:0]	vuad_mux1_l_sel_r2;
output		vuad_mux2_sel_r2;  // int 5.0 changes
output	vuad_rd_en_r2;

output	[4:0]	 vuad_rd_addr1_r3;
output	[4:0]	 vuad_rd_addr2_r3;
output		 vuad_rd_addr_sel_r3;
output	[4:0]	 vuad_wr_addr_r3; // address bits 6:2
output	[3:0]	 vuad_word_en_r3; // decoded address bits 1:0
output		 vuad_wr_en_r3c0; // decoded address bits 8:7
output		 vuad_wr_en_r3c1; // decoded address bits 8:7
output		vuad_rd_en_r3;

output	[1:0]	vuad_mux_sel; // middle mux select.
//

input	mbist_run;


//
//
//


output     vuad_usaloc_mux_used_and_alloc_comb_sel0;
output     vuad_usaloc_mux_used_and_alloc_comb_sel1;
output     vuad_usaloc_mux_used_and_alloc_comb_sel2;
output     vuad_usaloc_mux_used_and_alloc_comb_sel3;
output     vuad_usaloc_mux_used_and_alloc_comb_sel4;
output     vuad_usaloc_mux_used_and_alloc_comb_sel5;


output  mux_valid_dirty_c1_sel0;
output  mux_valid_dirty_c1_sel1;
output  mux_valid_dirty_c1_sel2;


wire 	vuad_array_wr_en0_c3, vuad_array_wr_en0_c5, vuad_array_wr_en0_c52; 
     // BS 03/11/04 extra cycle for mem access
wire	vuad_array_wr_en1_c3, vuad_array_wr_en1_c5, vuad_array_wr_en1_c52; 
     // BS 03/11/04 extra cycle for mem access
wire	vuad_sel_wr, vuad_sel_c4orc5; 
 
wire	inst_vld_c3; 
wire	inst_vld_c4; 
wire	inst_vld_c5; 
 
wire	arb_inst_diag_c2; 
wire	arb_inst_diag_c3; 
wire	arb_inst_diag_c4; 
 
wire	l2_bypass_mode_on_d1; 
wire	wr_disable_c3; 
wire	inst_int_c2; // int 5.0 changes 
wire	inst_int_c3;  // int 5.0 changes
wire	inst_int_c4;  // int 5.0 changes
wire	inst_int_c5;  // int 5.0 changes
wire	vuad_error_c4, vuad_error_c5, vuad_error_c52; // BS 03/11/04 extra cycle for mem access 
wire	vuad_error_c6, vuad_error_c7; 
 
 
wire	alloc_set_cond_c2; 
wire	alloc_rst_cond_c2; 
wire	fill_inst_vld_c2; 
wire	[3:0]	dec_lo_fill_way_c2; 
wire	[3:0]	dec_hi_fill_way_c2; 
wire	[15:0]	fill_way_c2; 
 
wire	acc_vd_c3; 
wire	acc_ua_c3; 
wire	bistordiag_wr_vd_c3, bistordiag_wr_ua_c3 ; 
wire	[8:0]	vuad_acc_idx_c3; 
wire	vuadctl_no_bypass_c1; 


//////////////////////////////////////////////////
// l2t_vuad_ctl
//////////////////////////////////////////////////
assign	wr_addr_entry = wr_addr[6:2] ;
assign	wr_word_en[0]  = ~wr_addr[1] & ~wr_addr[0] ;
assign	wr_word_en[1]  = ~wr_addr[1] & wr_addr[0] ;
assign	wr_word_en[2]  = wr_addr[1] & ~wr_addr[0] ;
assign	wr_word_en[3]  = wr_addr[1] & wr_addr[0] ;
assign	wr_en[0] =  ~wr_addr[8] & ~wr_addr[7] ;
assign	wr_en[1] =  ~wr_addr[8] & wr_addr[7] ;
assign	wr_en[2] =   wr_addr[8] & ~wr_addr[7] ;
assign	wr_en[3] =   wr_addr[8] & wr_addr[7] ;

assign rd_addr_sel_n = ~rd_addr_sel;

// LSb 1:0
l2t_vuad_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_addr1to0_px2 
		(.dout (addr1to0_px2[1:0] ) ,
       			.din0(rd_addr1[1:0]),
			.din1(rd_addr2[1:0]),
			.sel0(rd_addr_sel),
			.sel1(rd_addr_sel_n));

l2t_vuad_ctl_msff_ctl_macro__width_2 ff_addr1to0_c1  // int 5.0 change
		(.din(addr1to0_px2[1:0]),
		.scan_in(ff_addr1to0_c1_scanin),
		.scan_out(ff_addr1to0_c1_scanout),
		.l1clk(l1clk),
		.dout(addr1to0_c1[1:0]),
  .siclk(siclk),
  .soclk(soclk)
		);

// LSb 8
l2t_vuad_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_addr8_px2 
		(.dout (addr8_px2) ,
       			.din0(rd_addr1[8]),
			.din1(rd_addr2[8]),
			.sel0(rd_addr_sel),
			.sel1(rd_addr_sel_n));

l2t_vuad_ctl_msff_ctl_macro__width_1 ff_addr8_c1 
		(.din(addr8_px2),
		.scan_in(ff_addr8_c1_scanin),
		.scan_out(ff_addr8_c1_scanout),
		.l1clk(l1clk),
		.dout(addr8_c1),
  .siclk(siclk),
  .soclk(soclk)
);


// Lsb 7
l2t_vuad_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_1 mux_addr7_px2 
		(.dout (addr7_px2) ,
       			.din0(rd_addr1[7]),
			.din1(rd_addr2[7]),
			.sel0(rd_addr_sel),
			.sel1(rd_addr_sel_n));

l2t_vuad_ctl_msff_ctl_macro__width_1 ff_addr7_c1  // int 5.0 change
                           (.din(addr7_px2),
		.scan_in(ff_addr7_c1_scanin),
		.scan_out(ff_addr7_c1_scanout),
		.l1clk(l1clk),
		.dout(addr7_c1),
  .siclk(siclk),
  .soclk(soclk)
);


// Mux2 of the read address.
// Buffer appropriately to get the following
// signals.


// XY = 75 X 50
assign	vuad_rd_addr1_r0 = rd_addr1[6:2];
assign	vuad_rd_addr2_r0 = rd_addr2[6:2];
assign	vuad_rd_addr_sel_r0 = rd_addr_sel ;

assign	vuad_wr_addr_r0[4:0] = wr_addr_entry[4:0] ;
assign	vuad_word_en_r0 = wr_word_en ;
assign	vuad_wr_en_r0c0 = wr_en[0] & wr_en0 ;
assign	vuad_wr_en_r0c1 = wr_en[0] & wr_en1 ;

assign		vuad_mux1_h_sel_r0[0]  = ~addr1to0_c1[1] & ~addr1to0_c1[0] ;
assign		vuad_mux1_h_sel_r0[1]  = ~addr1to0_c1[1] & addr1to0_c1[0] ;
assign		vuad_mux1_h_sel_r0[2]  = addr1to0_c1[1] & ~addr1to0_c1[0] ;
assign		vuad_mux1_h_sel_r0[3]  = addr1to0_c1[1] & addr1to0_c1[0] ;

assign		vuad_mux1_l_sel_r0 = vuad_mux1_h_sel_r0 ;
assign		vuad_mux2_sel_r0= addr7_c1; // int 5.0 change
assign		vuad_rd_en_r0  = ~addr7_px2 & array_rd_en;

// XY = 75 X 50
assign	vuad_rd_addr1_r1 = rd_addr1[6:2];
assign	vuad_rd_addr2_r1 = rd_addr2[6:2];
assign	vuad_rd_addr_sel_r1 = rd_addr_sel ;
assign	vuad_wr_addr_r1[4:0] = wr_addr_entry[4:0] ;
assign	vuad_word_en_r1 = wr_word_en ;
assign	vuad_wr_en_r1c0 = wr_en[1] & wr_en0 ;
assign	vuad_wr_en_r1c1 = wr_en[1] & wr_en1 ;
assign	vuad_rd_en_r1  = addr7_px2 & array_rd_en ;

// XY = 75 X 50
assign	vuad_rd_addr1_r2 = rd_addr1[6:2];
assign	vuad_rd_addr2_r2 = rd_addr2[6:2];
assign	vuad_rd_addr_sel_r2 = rd_addr_sel ;
assign	vuad_wr_addr_r2[4:0] = wr_addr_entry[4:0] ;
assign	vuad_word_en_r2 = wr_word_en ;
assign	vuad_wr_en_r2c0 = wr_en[2] & wr_en0 ;
assign	vuad_wr_en_r2c1 = wr_en[2] & wr_en1 ;

assign	vuad_mux1_h_sel_r2[0]  = ~addr1to0_c1[1] & ~addr1to0_c1[0] ;
assign	vuad_mux1_h_sel_r2[1]  = ~addr1to0_c1[1] & addr1to0_c1[0] ;
assign	vuad_mux1_h_sel_r2[2]  = addr1to0_c1[1] & ~addr1to0_c1[0] ;
assign	vuad_mux1_h_sel_r2[3]  = addr1to0_c1[1] & addr1to0_c1[0] ;
assign	vuad_mux1_l_sel_r2 = vuad_mux1_h_sel_r2 ;
assign	vuad_mux2_sel_r2 = addr7_c1;
assign	vuad_rd_en_r2  = ~addr7_px2 & array_rd_en;


// XY = 75 X 50
assign	vuad_rd_addr1_r3 = rd_addr1[6:2];
assign	vuad_rd_addr2_r3 = rd_addr2[6:2];
assign	vuad_rd_addr_sel_r3 = rd_addr_sel ;
assign	vuad_wr_addr_r3[4:0] = wr_addr_entry[4:0] ;
assign	vuad_word_en_r3 = wr_word_en ;
assign	vuad_wr_en_r3c0 = wr_en[3] & wr_en0 ;
assign	vuad_wr_en_r3c1 = wr_en[3] & wr_en1 ;
assign	vuad_rd_en_r3  = addr7_px2 & array_rd_en;

// Middle Io = 75 X 50

assign	vuad_mux_sel[0]	 =  ~addr8_c1 ;
assign	vuad_mux_sel[1]	 =   addr8_c1 ;

//////////////////////////////////////////////////
// L1 clk header
//////////////////////////////////////////////////
assign pce_ov = tcu_pce_ov;
//assign stop = 1'b0;
assign stop = tcu_clk_stop;
assign siclk = tcu_aclk;
assign soclk = tcu_bclk;
assign se = tcu_scan_en;

l2t_vuad_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk(l2clk),
        .l1en(1'b1 ),
        .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

//////////////////////////////////////////////////

//////////////////////////////////////////
// Spare gate insertion
//////////////////////////////////////////
l2t_vuad_ctl_spare_ctl_macro__num_4 spares  (
        .scan_in(spares_scanin),
        .scan_out(spares_scanout),
        .l1clk  (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
//////////////////////////////////////////

 
//assign	vuaddp_st_to_data_array_c3 = tag_st_to_data_array_c3; 
//assign	vuaddp_lru_way_c3 = tagdp_lru_way_sel_c3; 
//assign	vuaddp_hit_wayvld_c3 = tag_hit_way_vld_c3  & ~{16{arb_vuad_ce_err_c3}}; 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuadctl_no_bypass_c1 
                           (.din(arb_vuadctl_no_bypass_px2),  
		 .scan_in(ff_vuadctl_no_bypass_c1_scanin),
		 .scan_out(ff_vuadctl_no_bypass_c1_scanout),
		 .l1clk(l1clk), 
                 .dout(vuadctl_no_bypass_c1),
  .siclk(siclk),
  .soclk(soclk)  
); 
 
//////////////////////////////////////////////////////////////////////// 
 // index compares to for vuad mux selects. 
 //////////////////////////////////////////////////////////////////////// 
 
 assign vuaddp_vuad_sel_c2 = ~arbadr_idx_c1c2comp_c1_n & arb_inst_vld_c2 &
                        ~( arb_decdp_inst_int_c1  | inst_int_c2  ) ;  // int 5.0 changes
 
 assign vuaddp_vuad_sel_c4 = ~arbadr_idx_c1c4comp_c1_n & inst_vld_c4 &
				~( arb_decdp_inst_int_c1  | inst_int_c4)  ; // int 5.0 changes
 
 assign vuaddp_vuad_sel_c2orc3 = ((( ~arbadr_idx_c1c3comp_c1_n & inst_vld_c3)  &
                                ~( arb_decdp_inst_int_c1  | inst_int_c3) ) |
                                vuaddp_vuad_sel_c2 ); // int 5.0 change
 
 assign vuad_sel_wr = ~arbadr_idx_c1c5comp_c1_n & inst_vld_c5 &
			~( arb_decdp_inst_int_c1  | inst_int_c5); // int 5.0 change
 
 assign vuad_sel_c4orc5 = vuaddp_vuad_sel_c4 | vuad_sel_wr ; 

 assign vuaddp_vuad_sel_rd = ~( vuaddp_vuad_sel_c2orc3 | vuad_sel_c4orc5 ) | // int 5.0 changes 
			vuadctl_no_bypass_c1; // BIST or DECC read of VUAD 


assign vuad_usaloc_mux_used_and_alloc_comb_sel0 = vuaddp_vuad_sel_rd_c2   & ~vuaddp_vuad_sel_c2_d1  &
						 vuaddp_vuad_sel_c2 & vuaddp_vuad_sel_c2orc3 & ~vuaddp_vuad_sel_rd;
assign vuad_usaloc_mux_used_and_alloc_comb_sel1 = ~vuaddp_vuad_sel_rd_c2 & ~vuaddp_vuad_sel_c2_d1 & 
						vuaddp_vuad_sel_c2 & vuaddp_vuad_sel_c2orc3 & ~vuaddp_vuad_sel_rd;
assign vuad_usaloc_mux_used_and_alloc_comb_sel2 = vuaddp_vuad_sel_c2_d1 & vuaddp_vuad_sel_c2 & vuaddp_vuad_sel_c2orc3   &
						 ~vuaddp_vuad_sel_rd;
assign vuad_usaloc_mux_used_and_alloc_comb_sel3 = ~vuaddp_vuad_sel_c2  & vuaddp_vuad_sel_c2orc3 & ~vuaddp_vuad_sel_rd ;
assign vuad_usaloc_mux_used_and_alloc_comb_sel4 = ~vuaddp_vuad_sel_c2orc3 & ~vuaddp_vuad_sel_rd;
assign vuad_usaloc_mux_used_and_alloc_comb_sel5 = vuaddp_vuad_sel_rd;


//assign mux_valid_dirty_c1_sel0 =  vuaddp_vuad_sel_rd;
//assign mux_valid_dirty_c1_sel1 = ~vuaddp_vuad_sel_rd & vuaddp_vuad_sel_c2orc3;
//assign mux_valid_dirty_c1_sel2 = ~vuaddp_vuad_sel_rd & ~vuaddp_vuad_sel_c2orc3;

assign mux_valid_dirty_c1_sel0 =  ~( vuaddp_vuad_sel_c2orc3 | vuad_sel_c4orc5 ) | vuadctl_no_bypass_c1_1;
assign mux_valid_dirty_c1_sel1 = ~(~( vuaddp_vuad_sel_c2orc3 | vuad_sel_c4orc5 ) | vuadctl_no_bypass_c1_1)  & vuaddp_vuad_sel_c2orc3;
assign mux_valid_dirty_c1_sel2 = ~(~( vuaddp_vuad_sel_c2orc3 | vuad_sel_c4orc5 ) | vuadctl_no_bypass_c1_1)  & ~vuaddp_vuad_sel_c2orc3;


l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuadctl_no_bypass_c1_1 
                           (.din(arb_vuadctl_no_bypass_px2),
                 .scan_in(ff_vuadctl_no_bypass_c1_1_scanin),
                 .scan_out(ff_vuadctl_no_bypass_c1_1_scanout),
                 .l1clk(l1clk),
                 .dout(vuadctl_no_bypass_c1_1),
  .siclk(siclk),
  .soclk(soclk)
);


l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuaddp_vuad_sel_c2 
                           (.din(vuaddp_vuad_sel_rd), .l1clk(l1clk),
                 .scan_in(ff_vuaddp_vuad_sel_c2_scanin),
                 .scan_out(ff_vuaddp_vuad_sel_c2_scanout),
                 .dout(vuaddp_vuad_sel_rd_c2),
  .siclk(siclk),
  .soclk(soclk)
);

			 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuaddp_vuad_sel_c2_d1 
                           (.din(vuaddp_vuad_sel_c2), .l1clk(l1clk), 
                 .scan_in(ff_vuaddp_vuad_sel_c2_d1_scanin),
                 .scan_out(ff_vuaddp_vuad_sel_c2_d1_scanout),
                 .dout(vuaddp_vuad_sel_c2_d1),
  .siclk(siclk),
  .soclk(soclk)  
); 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_sel_wr_d1 
                           (.din(vuad_sel_wr), .l1clk(l1clk), 
                 .scan_in(ff_vuad_sel_wr_d1_scanin),
                 .scan_out(ff_vuad_sel_wr_d1_scanout),
                 .dout(vuad_sel_wr_d1),
  .siclk(siclk),
  .soclk(soclk)  
); 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_tagd_sel_c2_d1 
                           (.din(vuaddp_vuad_sel_c2), .l1clk(l1clk), 
                 .scan_in(ff_vuad_tagd_sel_c2_d1_scanin),
                 .scan_out(ff_vuad_tagd_sel_c2_d1_scanout),
                 .dout(vuaddp_vuad_tagd_sel_c2_d1),
  .siclk(siclk),
  .soclk(soclk)  
); 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_wr64_inst_c3 
		(.din(arb_decdp_wr64_inst_c2), .l1clk(l1clk), 
               .scan_in(ff_wr64_inst_c3_scanin),
               .scan_out(ff_wr64_inst_c3_scanout),
               .dout(vuaddp_wr64_inst_c3),
  .siclk(siclk),
  .soclk(soclk)  
 
		); 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_arb_acc_vd_c3 
              (.dout   (acc_vd_c3), .din (arb_acc_vd_c2), 
               .scan_in(ff_arb_acc_vd_c3_scanin),
               .scan_out(ff_arb_acc_vd_c3_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_arb_acc_ua_c3 
              (.dout   (acc_ua_c3), .din (arb_acc_ua_c2), 
               .scan_in(ff_arb_acc_ua_c3_scanin),
               .scan_out(ff_arb_acc_ua_c3_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_inst_vld_c3 
              (.dout   (inst_vld_c3), .din (arb_inst_vld_c2), 
               .scan_in(ff_inst_vld_c3_scanin),
               .scan_out(ff_inst_vld_c3_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_inst_vld_c4 
              (.dout   (inst_vld_c4), .din (inst_vld_c3), 
               .scan_in(ff_inst_vld_c4_scanin),
               .scan_out(ff_inst_vld_c4_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_inst_vld_c5 
              (.dout   (inst_vld_c5), .din (inst_vld_c4), 
               .scan_in(ff_inst_vld_c5_scanin),
               .scan_out(ff_inst_vld_c5_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_arb_inst_diag_c2 
              (.dout   (arb_inst_diag_c2), .din (arb_inst_diag_c1), 
               .scan_in(ff_arb_inst_diag_c2_scanin),
               .scan_out(ff_arb_inst_diag_c2_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_arb_inst_diag_c3 
              (.dout   (arb_inst_diag_c3), .din (arb_inst_diag_c2), 
               .scan_in(ff_arb_inst_diag_c3_scanin),
               .scan_out(ff_arb_inst_diag_c3_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_arb_inst_diag_c4 
              (.dout   (arb_inst_diag_c4), .din (arb_inst_diag_c3), 
               .scan_in(ff_arb_inst_diag_c4_scanin),
               .scan_out(ff_arb_inst_diag_c4_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
// msff_ctl_macro ff_filbuf_vuad_bypassed_c3 (width=1)
              //(.dout   (filbuf_vuad_bypassed_c3), .din (filbuf_vuad_bypassed_c2), 
               //.l1clk (l1clk),  
	//	.scan_in  (), 
	//	.scan_out()
 
              //) ; 
 
l2t_vuad_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_9 mux_idx_c3 
		(.dout (vuad_acc_idx_c3[8:0]) , 
                                .din0(bist_vuad_idx_c3[8:0] ),  
                                .din1(evctag_vuad_idx_c3[8:0]),  
                                .sel0(bist_vuad_wr_en & mbist_run_r1),         
                                .sel1(~bist_vuad_wr_en & ~mbist_run_r1)) ; 
 
l2t_vuad_ctl_msff_ctl_macro__width_9 ff_mux_idx_c4 
              (.dout   (vuaddp_vuad_idx_c4[8:0]), .din (vuad_acc_idx_c3[8:0]), 
               .scan_in(ff_mux_idx_c4_scanin),
               .scan_out(ff_mux_idx_c4_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
 
////////////////////////////////////////////////////////////////////////////////////////// 
// Disable L2 VUAD writes if 
// 1. Instruction is an INT. 
// 2. L2 is OFF and the instruction is a non-diag instruction. 
// 3. diag instruction is not a VUAD store. 
//     (in implementation disable the write whenever there is Diag Inst and 
//    enable it if the inst is a Diag write to the VUAD array.) 
////////////////////////////////////////////////////////////////////////////////////////// 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_l2_bypass_mode_on_d1 
              (.dout   (l2_bypass_mode_on_d1), .din (csr_l2_bypass_mode_on), 
               .scan_in(ff_l2_bypass_mode_on_d1_scanin),
               .scan_out(ff_l2_bypass_mode_on_d1_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 


//////////////////////////////////////////////////////////////////////////////
//If a diagnostic access, normal write is disabled by wr_disable_c3. 
//If not a diagnostic access :
//      if bypass mode is on, write is disabled by wr_disable_c3
//      if bypass mode is off, write is always enabled ( even upon vuad CE)
//                  hence we dont need to use CE to force the write to happen ??
///////////////////////////////////////////////////////////////////////////////////// 
 
assign  wr_disable_c3  = inst_int_c3 | // int 5.0 changes	// VUAD ecc changes
                         (l2_bypass_mode_on_d1 & ~arb_inst_diag_c3) | 
                          arb_inst_diag_c3 ; 
 
////////////////////////// 
// access  PV, PD, V, P 
////////////////////////// 
assign  vuaddp_sel_diag0_data_wr_c3 = arb_inst_l2vuad_vld_c3 &  
			arb_decdp_st_inst_c3 &  acc_vd_c3 ; // sel diag over bist data 
 
assign	bistordiag_wr_vd_c3 =  (vuaddp_sel_diag0_data_wr_c3 & ~mbist_run_r1)| // diagorbist over normal data 
				( bist_vuad_wr_en & bist_wr_vd_c3 & mbist_run_r1 );  
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_bistordiag_wr_vd_c4 
              (.dout   (vuaddp_bistordiag_wr_vd_c4), .din (bistordiag_wr_vd_c3), 
               .scan_in(ff_bistordiag_wr_vd_c4_scanin),
               .scan_out(ff_bistordiag_wr_vd_c4_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
//assign  vuad_array_wr_en1_c3 = ((inst_vld_c3 & ~wr_disable_c3) &~mbist_run_r1) |  // normal write 
//				(bistordiag_wr_vd_c3 & mbist_run_r1); // bist or diag write 

assign  vuad_array_wr_en1_c3 = ((inst_vld_c3 & ~wr_disable_c3) &~mbist_run_r1) | // normal write
			bistordiag_wr_vd_c3;

////////////////////////// 
// access  PU, PA, U, A 
////////////////////////// 
assign  vuaddp_sel_diag1_data_wr_c3 = arb_inst_l2vuad_vld_c3 &  
			arb_decdp_st_inst_c3 & acc_ua_c3 ; // sel diag over bist data 
 
assign	bistordiag_wr_ua_c3 =  (vuaddp_sel_diag1_data_wr_c3  & ~mbist_run_r1)| // diagorbist over normal data 
				( mbist_run_r1 & bist_vuad_wr_en & ~bist_wr_vd_c3 ); 
 
l2t_vuad_ctl_msff_ctl_macro__width_2 ff_bistordiag_wr_ua_c4 
              (.dout ({mbist_run_r1,vuaddp_bistordiag_wr_ua_c4}), 
		.scan_in(ff_bistordiag_wr_ua_c4_scanin),
		.scan_out(ff_bistordiag_wr_ua_c4_scanout),
		.din ({mbist_run,bistordiag_wr_ua_c3}), 
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
              ) ; 

 
assign  vuad_array_wr_en0_c3 = (( inst_vld_c3 & ~wr_disable_c3) &~mbist_run_r1) | // normal write 
				bistordiag_wr_ua_c3; // bist or diag write 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_array_wr_en0_c4 
			(.din(vuad_array_wr_en0_c3), .l1clk(l1clk), 
                 	.scan_in(ff_vuad_array_wr_en0_c4_scanin),
                 	.scan_out(ff_vuad_array_wr_en0_c4_scanout),
                 	.dout(vuaddp_vuad_array_wr_en0_c4),
  .siclk(siclk),
  .soclk(soclk)  
 
			); 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_array_wr_en1_c4 
			(.din(vuad_array_wr_en1_c3), .l1clk(l1clk), 
                 	.scan_in(ff_vuad_array_wr_en1_c4_scanin),
                 	.scan_out(ff_vuad_array_wr_en1_c4_scanout),
                 	.dout(vuaddp_vuad_array_wr_en1_c4),
  .siclk(siclk),
  .soclk(soclk)  
 
			); 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_array_wr_en0_c5 
			(.din(vuaddp_vuad_array_wr_en0_c4), .l1clk(l1clk), 
                 	.scan_in(ff_vuad_array_wr_en0_c5_scanin),
                 	.scan_out(ff_vuad_array_wr_en0_c5_scanout),
                 	.dout(vuad_array_wr_en0_c5),
  .siclk(siclk),
  .soclk(soclk)  
 
			); 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_array_wr_en1_c5 
			(.din(vuaddp_vuad_array_wr_en1_c4), .l1clk(l1clk), 
                 	.scan_in(ff_vuad_array_wr_en1_c5_scanin),
                 	.scan_out(ff_vuad_array_wr_en1_c5_scanout),
                 	.dout(vuad_array_wr_en1_c5),
  .siclk(siclk),
  .soclk(soclk)  
 
			); 

// BS 03/11/04 extra cycle for mem access

l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_array_wr_en0_c52 
                        (.din(vuad_array_wr_en0_c5), .l1clk(l1clk),
                        .scan_in(ff_vuad_array_wr_en0_c52_scanin),
                        .scan_out(ff_vuad_array_wr_en0_c52_scanout),
                        .dout(vuad_array_wr_en0_c52),
  .siclk(siclk),
  .soclk(soclk)  

                        );


l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_array_wr_en1_c52 
                        (.din(vuad_array_wr_en1_c5), .l1clk(l1clk),
                        .scan_in(ff_vuad_array_wr_en1_c52_scanin),
                        .scan_out(ff_vuad_array_wr_en1_c52_scanout),
                        .dout(vuad_array_wr_en1_c52),
  .siclk(siclk),
  .soclk(soclk)  

                        );

// 
//msff_ctl_macro ff_vuad_array_wr_en0_c6 (width=1)
//			(.din(vuad_array_wr_en0_c52), .l1clk(l1clk), 
//                 	.scan_in(ff_vuad_array_wr_en0_c6_scanin),
//                 	.scan_out(ff_vuad_array_wr_en0_c6_scanout),
//                 	.dout(vuad_array_wr_en0_c6),  
// 
//			); 
// 
//msff_ctl_macro ff_vuad_array_wr_en1_c6 (width=1)
//			(.din(vuad_array_wr_en1_c52), .l1clk(l1clk), 
//                 	.scan_in(ff_vuad_array_wr_en1_c6_scanin),
//                 	.scan_out(ff_vuad_array_wr_en1_c6_scanout),
//                 	.dout(vuad_array_wr_en1_c6),  
// 
//			); 
// 
//assign	vuaddp_sel_ua_wr_data_byp = vuad_sel_wr_d1  
//				& vuad_array_wr_en1_c6 ; 
//assign	vuaddp_sel_vd_wr_data_byp = vuad_sel_wr_d1  
//				& vuad_array_wr_en0_c6 ; 
// 

assign        vuaddp_sel_ua_wr_data_byp = vuad_sel_wr_d1
				& vuad_array_wr_en1_c52 ;
assign        vuaddp_sel_vd_wr_data_byp = vuad_sel_wr_d1
                              & vuad_array_wr_en0_c52 ;

 
//* All errors are qualififed in the block that generates them 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_inst_int_c2  // int 5.0 changes
              (.dout   (inst_int_c2), .din (arb_decdp_inst_int_c1), 
               .scan_in(ff_inst_int_c2_scanin),
               .scan_out(ff_inst_int_c2_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 

l2t_vuad_ctl_msff_ctl_macro__width_1 ff_inst_int_c3  // int 5.0 changes
              (.dout   (inst_int_c3), .din (inst_int_c2),
               .scan_in(ff_inst_int_c3_scanin),
               .scan_out(ff_inst_int_c3_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  

              ) ;

l2t_vuad_ctl_msff_ctl_macro__width_1 ff_inst_int_c4  // int 5.0 changes
              (.dout   (inst_int_c4), .din (inst_int_c3),
               .scan_in(ff_inst_int_c4_scanin),
               .scan_out(ff_inst_int_c4_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  

              ) ;

l2t_vuad_ctl_msff_ctl_macro__width_1 ff_inst_int_c5  // int 5.0 changes
              (.dout   (inst_int_c5), .din (inst_int_c4),
               .scan_in(ff_inst_int_c5_scanin),
               .scan_out(ff_inst_int_c5_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  

              ) ;


// Used bit error will not be reported as they are harmless. 
 
assign	vuad_error_c4 = ~(arb_inst_diag_c4 | inst_int_c4) &  
			 (vuadpm_vd_ue_c4 | vuadpm_ua_ue_c4) &  // int 5.0 changes
                          inst_vld_c4; 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_error_c5 
              (.dout   (vuad_error_c5), .din (vuad_error_c4), 
               .scan_in(ff_vuad_error_c5_scanin),
               .scan_out(ff_vuad_error_c5_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 

// BS 03/11/04 extra cycle for mem access

l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_error_c52 
              (.dout   (vuad_error_c52), .din (vuad_error_c5),
               .scan_in(ff_vuad_error_c52_scanin),
               .scan_out(ff_vuad_error_c52_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  

              ) ;

 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_error_c6 
              (.dout   (vuad_error_c6), .din (vuad_error_c52), 
               .scan_in(ff_vuad_error_c6_scanin),
               .scan_out(ff_vuad_error_c6_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_error_c7 
              (.dout   (vuad_error_c7), .din (vuad_error_c6), 
               .scan_in(ff_vuad_error_c7_scanin),
               .scan_out(ff_vuad_error_c7_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_vuad_error_c8 
              (.dout   (vuaddp_vuad_error_c8), .din (vuad_error_c7), 
               .scan_in(ff_vuad_error_c8_scanin),
               .scan_out(ff_vuad_error_c8_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
//////////////////////////////////////////////////////////////////////////////// 
// 4-16 decoder for the fill way 
// Conditions for altering the VUAD bits. 
//////////////////////////////////////////////////////////////////////////////// 
assign  fill_inst_vld_c2 = arbdec_arbdp_inst_fb_c2 & arb_inst_vld_c2 ; 
 
 
assign	dec_lo_fill_way_c2[0] = ( arbdec_arbdp_inst_way_c2[1:0]==2'd0 )  
					& fill_inst_vld_c2 ; 
assign	dec_lo_fill_way_c2[1] = ( arbdec_arbdp_inst_way_c2[1:0]==2'd1 )  
					& fill_inst_vld_c2 ; 
assign	dec_lo_fill_way_c2[2] = ( arbdec_arbdp_inst_way_c2[1:0]==2'd2 )  
					& fill_inst_vld_c2 ; 
assign	dec_lo_fill_way_c2[3] = ( arbdec_arbdp_inst_way_c2[1:0]==2'd3 )  
					& fill_inst_vld_c2 ; 
 
 
assign	dec_hi_fill_way_c2[0] = ( arbdec_arbdp_inst_way_c2[3:2]==2'd0 ) ; 
 
assign	dec_hi_fill_way_c2[1] = ( arbdec_arbdp_inst_way_c2[3:2]==2'd1 ) ; 
 
assign	dec_hi_fill_way_c2[2] = ( arbdec_arbdp_inst_way_c2[3:2]==2'd2 ) ; 
 
assign	dec_hi_fill_way_c2[3] = ( arbdec_arbdp_inst_way_c2[3:2]==2'd3 ) ; 
 
 
assign	fill_way_c2[0] = dec_hi_fill_way_c2[0] & dec_lo_fill_way_c2[0] ; // 0000 
 
assign	fill_way_c2[1] = dec_hi_fill_way_c2[0] & dec_lo_fill_way_c2[1] ; // 0001 
 
assign	fill_way_c2[2] = dec_hi_fill_way_c2[0] & dec_lo_fill_way_c2[2] ; // 0010 
 
assign	fill_way_c2[3] = dec_hi_fill_way_c2[0] & dec_lo_fill_way_c2[3] ; // 0011 


assign  fill_way_c2[4] = dec_hi_fill_way_c2[1] & dec_lo_fill_way_c2[0] ; // 0100

assign  fill_way_c2[5] = dec_hi_fill_way_c2[1] & dec_lo_fill_way_c2[1] ; // 0101

assign  fill_way_c2[6] = dec_hi_fill_way_c2[1] & dec_lo_fill_way_c2[2] ; // 0110

assign  fill_way_c2[7] = dec_hi_fill_way_c2[1] & dec_lo_fill_way_c2[3] ; // 0111


assign  fill_way_c2[8] = dec_hi_fill_way_c2[2] & dec_lo_fill_way_c2[0] ; // 1000

assign  fill_way_c2[9] = dec_hi_fill_way_c2[2] & dec_lo_fill_way_c2[1] ; // 1001

assign  fill_way_c2[10] = dec_hi_fill_way_c2[2] & dec_lo_fill_way_c2[2] ; // 1010

assign  fill_way_c2[11] = dec_hi_fill_way_c2[2] & dec_lo_fill_way_c2[3] ; // 1011
 
 
assign	fill_way_c2[12] = dec_hi_fill_way_c2[3] & dec_lo_fill_way_c2[0] ; // 1100 
 
assign	fill_way_c2[13] = dec_hi_fill_way_c2[3] & dec_lo_fill_way_c2[1] ; // 1101 
 
assign	fill_way_c2[14] = dec_hi_fill_way_c2[3] & dec_lo_fill_way_c2[2] ; // 1110 
 
assign	fill_way_c2[15] = dec_hi_fill_way_c2[3] & dec_lo_fill_way_c2[3] ; // 1111 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_16 ff_fill_way_c3 
              (.dout   (vuaddp_fill_way_c3[15:0]), .din (fill_way_c2[15:0]), 
               .scan_in(ff_fill_way_c3_scanin),
               .scan_out(ff_fill_way_c3_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
 
assign  alloc_set_cond_c2 = (arb_arbdp_vuadctl_pst_no_ctrue_c2 | arb_decdp_cas1_inst_c2) ; 
 
 
assign  alloc_rst_cond_c2 = arb_arbdp_pst_with_ctrue_c2 | 
                            (arb_decdp_cas2_inst_c2 & arbdec_arbdp_inst_mb_c2) | 
                            (arbdec_arbdp_inst_mb_c2 & ~alloc_set_cond_c2) ; 
 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_alloc_set_cond_c3 
              (.dout   (vuaddp_alloc_set_cond_c3), .din (alloc_set_cond_c2), 
               .scan_in(ff_alloc_set_cond_c3_scanin),
               .scan_out(ff_alloc_set_cond_c3_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
l2t_vuad_ctl_msff_ctl_macro__width_1 ff_alloc_rst_cond_c3 
              (.dout   (vuaddp_alloc_rst_cond_c3), .din (alloc_rst_cond_c2), 
               .scan_in(ff_alloc_rst_cond_c3_scanin),
               .scan_out(ff_alloc_rst_cond_c3_scanout),
               .l1clk (l1clk),
  .siclk(siclk),
  .soclk(soclk)  
 
              ) ; 
 
 
// fixscan start:
assign ff_addr1to0_c1_scanin     = scan_in                  ;
assign ff_addr8_c1_scanin        = ff_addr1to0_c1_scanout   ;
assign ff_addr7_c1_scanin        = ff_addr8_c1_scanout      ;
assign spares_scanin             = ff_addr7_c1_scanout      ;
assign ff_vuadctl_no_bypass_c1_scanin = spares_scanout           ;
assign ff_vuadctl_no_bypass_c1_1_scanin = ff_vuadctl_no_bypass_c1_scanout;
assign ff_vuaddp_vuad_sel_c2_scanin = ff_vuadctl_no_bypass_c1_1_scanout;
assign ff_vuaddp_vuad_sel_c2_d1_scanin = ff_vuaddp_vuad_sel_c2_scanout;
assign ff_vuad_sel_wr_d1_scanin  = ff_vuaddp_vuad_sel_c2_d1_scanout;
assign ff_vuad_tagd_sel_c2_d1_scanin = ff_vuad_sel_wr_d1_scanout;
assign ff_wr64_inst_c3_scanin    = ff_vuad_tagd_sel_c2_d1_scanout;
assign ff_arb_acc_vd_c3_scanin   = ff_wr64_inst_c3_scanout  ;
assign ff_arb_acc_ua_c3_scanin   = ff_arb_acc_vd_c3_scanout ;
assign ff_inst_vld_c3_scanin     = ff_arb_acc_ua_c3_scanout ;
assign ff_inst_vld_c4_scanin     = ff_inst_vld_c3_scanout   ;
assign ff_inst_vld_c5_scanin     = ff_inst_vld_c4_scanout   ;
assign ff_arb_inst_diag_c2_scanin = ff_inst_vld_c5_scanout   ;
assign ff_arb_inst_diag_c3_scanin = ff_arb_inst_diag_c2_scanout;
assign ff_arb_inst_diag_c4_scanin = ff_arb_inst_diag_c3_scanout;
assign ff_mux_idx_c4_scanin      = ff_arb_inst_diag_c4_scanout;
assign ff_l2_bypass_mode_on_d1_scanin = ff_mux_idx_c4_scanout    ;
assign ff_bistordiag_wr_vd_c4_scanin = ff_l2_bypass_mode_on_d1_scanout;
assign ff_bistordiag_wr_ua_c4_scanin = ff_bistordiag_wr_vd_c4_scanout;
assign ff_vuad_array_wr_en0_c4_scanin = ff_bistordiag_wr_ua_c4_scanout;
assign ff_vuad_array_wr_en1_c4_scanin = ff_vuad_array_wr_en0_c4_scanout;
assign ff_vuad_array_wr_en0_c5_scanin = ff_vuad_array_wr_en1_c4_scanout;
assign ff_vuad_array_wr_en1_c5_scanin = ff_vuad_array_wr_en0_c5_scanout;
assign ff_vuad_array_wr_en0_c52_scanin = ff_vuad_array_wr_en1_c5_scanout;
assign ff_vuad_array_wr_en1_c52_scanin = ff_vuad_array_wr_en0_c52_scanout;
assign ff_inst_int_c2_scanin     = ff_vuad_array_wr_en1_c52_scanout;
assign ff_inst_int_c3_scanin     = ff_inst_int_c2_scanout   ;
assign ff_inst_int_c4_scanin     = ff_inst_int_c3_scanout   ;
assign ff_inst_int_c5_scanin     = ff_inst_int_c4_scanout   ;
assign ff_vuad_error_c5_scanin   = ff_inst_int_c5_scanout   ;
assign ff_vuad_error_c52_scanin  = ff_vuad_error_c5_scanout ;
assign ff_vuad_error_c6_scanin   = ff_vuad_error_c52_scanout;
assign ff_vuad_error_c7_scanin   = ff_vuad_error_c6_scanout ;
assign ff_vuad_error_c8_scanin   = ff_vuad_error_c7_scanout ;
assign ff_fill_way_c3_scanin     = ff_vuad_error_c8_scanout ;
assign ff_alloc_set_cond_c3_scanin = ff_fill_way_c3_scanout   ;
assign ff_alloc_rst_cond_c3_scanin = ff_alloc_set_cond_c3_scanout;
assign scan_out                  = ff_alloc_rst_cond_c3_scanout;
// fixscan end:
endmodule 


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module l2t_vuad_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [1:0] din0;
  input sel0;
  input [1:0] din1;
  input sel1;
  output [1:0] dout;


assign dout[1:0] = ( {2{sel0}} & din0[1:0] ) |
                       ( {2{sel1}} & din1[1:0]);


endmodule


// any PARAMS parms go into naming of macro

module l2t_vuad_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module l2t_vuad_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  output [0:0] dout;


assign dout[0:0] = ( {1{sel0}} & din0[0:0] ) |
                       ( {1{sel1}} & din1[0:0]);


endmodule


// any PARAMS parms go into naming of macro

module l2t_vuad_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module l2t_vuad_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module l2t_vuad_ctl_spare_ctl_macro__num_4 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));
assign scan_out = so_3;


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module l2t_vuad_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_9 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [8:0] din0;
  input sel0;
  input [8:0] din1;
  input sel1;
  output [8:0] dout;


assign dout[8:0] = ( {9{sel0}} & din0[8:0] ) |
                       ( {9{sel1}} & din1[8:0]);


endmodule


// any PARAMS parms go into naming of macro

module l2t_vuad_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module l2t_vuad_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dec.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dec (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  power_throttle, 
  lb_lbist_running, 
  lsu_dec_pmen, 
  lsu_exu_pmen, 
  spc_core_running_status, 
  exu_test_tid0, 
  exu_test_addr0, 
  exu_test_valid0, 
  exu_test_tid1, 
  exu_test_addr1, 
  exu_test_valid1, 
  tlu_cerer_icdp, 
  tlu_dec_pstate_pef, 
  fgu_fprs_fef, 
  tlu_dec_hpstate_hpriv, 
  tlu_dec_pstate_priv, 
  tlu_pstate_am, 
  tlu_window_block, 
  exu0_window_block, 
  exu1_window_block, 
  lsu_cpq_stall, 
  ifu_buf0_inst0, 
  ifu_buf0_inst1, 
  ifu_buf0_inst2, 
  ifu_buf0_inst3, 
  ifu_buf0_inst4, 
  ifu_buf0_inst5, 
  ifu_buf0_inst6, 
  ifu_buf0_inst7, 
  ifu_buf0_excp0, 
  ifu_buf0_excp1, 
  ifu_buf0_excp2, 
  ifu_buf0_excp3, 
  ifu_buf0_excp4, 
  ifu_buf0_excp5, 
  ifu_buf0_excp6, 
  ifu_buf0_excp7, 
  tlu_flush_ifu, 
  pku_load_flush_w, 
  pku_inst_cnt_brtaken00, 
  pku_inst_cnt_brtaken01, 
  pku_inst_cnt_brtaken02, 
  pku_inst_cnt_brtaken03, 
  pku_inst_cnt_brtaken04, 
  pku_inst_cnt_brtaken05, 
  pku_inst_cnt_brtaken06, 
  pku_inst_cnt_brtaken07, 
  pku_inst_cnt_brtaken10, 
  pku_inst_cnt_brtaken11, 
  pku_inst_cnt_brtaken12, 
  pku_inst_cnt_brtaken13, 
  pku_inst_cnt_brtaken14, 
  pku_inst_cnt_brtaken15, 
  pku_inst_cnt_brtaken16, 
  pku_inst_cnt_brtaken17, 
  pku_base_pick_p, 
  pku_raw_pick0_p, 
  pku_raw_pick1_p, 
  pku_annul_ds_dcti_brtaken0_e, 
  pku_annul_ds_dcti_brtaken1_e, 
  pku_valid_e, 
  pku_ds_e, 
  pku_lsu_p, 
  pku_fgu_p, 
  pku_pdist_p, 
  pku_twocycle_p, 
  pku_idest_p, 
  pku_fdest_p, 
  pku_fsrc_rd_p, 
  pku_isrc_rs1_p, 
  pku_isrc_rs2_p, 
  pku_isrc_rd_p, 
  pku_flush_f1, 
  pku_flush_f2, 
  pku_flush_lm, 
  pku_flush_lb, 
  pku_flush_m, 
  pku_flush_b, 
  spu_mult_request, 
  lsu_block_store_stall, 
  lsu_block_store_rd, 
  lsu_block_store_tid, 
  tlu_dtlb_reload_stall, 
  fgu_ecc_asi_stall, 
  exu0_oddwin_b, 
  exu1_oddwin_b, 
  fgu_idiv_stall, 
  fgu_fdiv_stall, 
  dec_br_taken_e1, 
  del_pick_d, 
  dec_inst0_rd_d, 
  dec_inst1_rd_d, 
  dec_rs1_addr0_e, 
  dec_rs1_addr1_e, 
  dec_inst0_d, 
  dec_inst1_d, 
  dec_decode0_d, 
  dec_decode1_d, 
  dec_valid0_d, 
  dec_valid1_d, 
  dec_true_valid_e, 
  dec_tid0_d, 
  dec_tid1_d, 
  dec_tid0_p, 
  dec_tid1_p, 
  dec_raw_pick_p, 
  dec_inst0_rs1_p, 
  dec_inst0_rs2_p, 
  dec_inst0_rs3_p, 
  dec_inst0_rs1_vld_p, 
  dec_inst0_rs2_vld_p, 
  dec_inst0_rs3_vld_p, 
  dec_inst1_rs1_p, 
  dec_inst1_rs2_p, 
  dec_inst1_rs3_p, 
  dec_inst1_rs1_vld_p, 
  dec_inst1_rs2_vld_p, 
  dec_inst1_rs3_vld_p, 
  dec_frf_r1_addr_d, 
  dec_frf_r2_addr_d, 
  dec_frf_r1_vld_d, 
  dec_frf_r2_vld_d, 
  dec_frf_r1_32b_d, 
  dec_frf_r2_32b_d, 
  dec_frf_r1_odd32b_d, 
  dec_frf_r2_odd32b_d, 
  dec_frf_w_addr_d, 
  dec_frf_w_vld_d, 
  dec_frf_w_32b_d, 
  dec_frf_w_odd32b_d, 
  dec_exu_src_vld_d, 
  dec_irf_w_addr_d, 
  dec_frf_store_d, 
  dec_fsr_store_d, 
  dec_fgu_op3_d, 
  dec_fgu_opf_d, 
  dec_fgu_decode_d, 
  dec_fgu_tid_d, 
  dec_flush_f1, 
  dec_flush_f2, 
  dec_flush_lm, 
  dec_flush_lb, 
  dec_flush_m, 
  dec_flush_b, 
  dec_spu_grant_d, 
  dec_spu_grant_fgu_d, 
  dec_block_store_b, 
  dec_load_flush_w, 
  dec_exc0_m, 
  dec_exc1_m, 
  dec_inst0_cnt, 
  dec_inst1_cnt, 
  dec_tid0_m, 
  dec_tid1_m, 
  dec_inst_valid_m, 
  dec_lsu_inst_m, 
  dec_fgu_inst_m, 
  dec_cti_inst_m, 
  dec_illegal_inst_m, 
  dec_icache_perr_m, 
  dec_priv_exc_m, 
  dec_hpriv_exc_m, 
  dec_fpdisable_exc_m, 
  dec_br_taken_m, 
  dec_done_inst_m, 
  dec_retry_inst_m, 
  dec_sir_inst_m, 
  dec_annul_ds_m, 
  dec_ds_m, 
  dec_fgu_sel_e, 
  dec_fgu_sel_m, 
  dec_lsu_sel0_e, 
  dec_lsu_sel1_e, 
  dec_lsu_sel0_lower_e, 
  dec_lsu_sel1_lower_e, 
  dec_lsu_sel0_upper_e, 
  dec_lsu_sel1_upper_e, 
  dec_rs1_addr0_upper_e, 
  dec_rs1_addr1_upper_e, 
  dec_ld_inst_e, 
  dec_st_inst_e, 
  dec_fsr_ldst_e, 
  dec_fpldst_inst_e, 
  dec_ldst_dbl_e, 
  dec_pref_inst_e, 
  dec_flush_inst_e, 
  dec_memstbar_inst_e, 
  dec_ldst_sz_e, 
  dec_frf_r2_addr_e, 
  dec_sr_inst_e, 
  dec_pr_inst_e, 
  dec_hpr_inst_e, 
  dec_casa_inst_e, 
  dec_ldstub_inst_e, 
  dec_swap_inst_e, 
  dec_altspace_d, 
  dec_sign_ext_e, 
  dec_sraddr_e, 
  dec_imm_asi_vld_d, 
  dec_imm_asi_d, 
  dec_lsu_tid0_d, 
  dec_lsu_tid1_d, 
  dec_lsu_tg_d, 
  dec_lsu_rd_e, 
  dec_ld_inst_d, 
  dec_instr0_type_d, 
  dec_instr1_type_d, 
  dec_valid_e, 
  dec_pmu_valid_e, 
  dec_fgu_valid_e, 
  dec_exu_clken, 
  dec_lsu_sel0_d, 
  dec_ierr_d, 
  dec_block_store_stall, 
  scan_out);
wire del_scanin;
wire del_scanout;
wire ded0_scanin;
wire ded0_scanout;
wire [1:0] del_tg_clken;
wire del_test0_sel_p;
wire del_twocycle0_std_p;
wire del_twocycle0_rs2_p;
wire del_default0_sel_p;
wire [4:0] del_test_addr0_p;
wire del_noshift0_d;
wire [1:0] ded_ferr_p;
wire [1:0] ded_perr_p;
wire [1:0] ded_ferr_d;
wire [1:0] ded_perr_d;
wire [1:0] ded_legal_p;
wire ded_oddwin0_d;
wire [4:0] ded_exc0_d;
wire ded1_scanin;
wire ded1_scanout;
wire del_test1_sel_p;
wire del_twocycle1_std_p;
wire del_twocycle1_rs2_p;
wire del_default1_sel_p;
wire [4:0] del_test_addr1_p;
wire del_noshift1_d;
wire ded_oddwin1_d;
wire [4:0] ded_exc1_d;
wire [1:0] dcd_sir_d;
wire [1:0] dcd_stdfa_d;
wire [1:0] dcd_save_restore_d;
wire [1:0] dcd_exu_src_d;
wire [1:0] dcd_killfgu_d;
wire [1:0] dcd_lsize0_d;
wire [1:0] dcd_lsu_sign_ext_d;
wire [1:0] dcd_load_d;
wire [1:0] dcd_store_d;
wire [1:0] dcd_lsdouble_d;
wire [1:0] dcd_prefetch_d;
wire [1:0] dcd_flush_d;
wire [1:0] dcd_memstbar_d;
wire [1:0] dcd_hpr_d;
wire [1:0] dcd_pr_d;
wire [1:0] dcd_priv_d;
wire [1:0] dcd_sr_d;
wire [1:0] dcd_casa_d;
wire [1:0] dcd_ldstub_d;
wire [1:0] dcd_alt_d;
wire [1:0] dcd_alti_d;
wire [1:0] dcd_swap_d;
wire [1:0] dcd_done_d;
wire [1:0] dcd_retry_d;
wire [1:0] dcd_fsrc_rs1_d;
wire [1:0] dcd_fsrc_rs2_d;
wire [1:0] dcd_fpdest_single_d;
wire [1:0] dcd_fp_rs1_single_d;
wire [1:0] dcd_fp_rs2_single_d;
wire [1:0] dcd_fsrsync_d;
wire [1:0] dcd_callclass_d;
wire [1:0] dcd_specbr_d;
wire [1:0] dcd_specfp_d;
wire [1:0] dcd_tcc_d;
wire [1:0] dcd_sethi_d;
wire [1:0] dcd_fpdisable_d;
wire [1:0] dcd_wrtick_d;
wire [1:0] dcd_lsize1_d;

   input l2clk;
   input scan_in;
   input tcu_pce_ov;		// scan signals
   input spc_aclk;
   input spc_bclk;
   input tcu_scan_en;

   input [2:0] power_throttle; // power throttle, [2:0] is encoded number of stalls in 8 cycle window
			       // 000 - no stalls, 001 - 1 stall, ... 111 - 7 stalls 

   input lb_lbist_running;

   input lsu_dec_pmen;		// power management enable for dec
   input lsu_exu_pmen;		// power management enable for exu

   input [7:0] spc_core_running_status;	// active bits for each of the threads

   input [1:0] exu_test_tid0;		// exu test interface to the irf (bist or ecc errors) 
   input [4:0] exu_test_addr0;
   input exu_test_valid0;

   input [1:0] exu_test_tid1;		// exu test interface to the irf (bist or ecc errors)
   input [4:0] exu_test_addr1;
   input exu_test_valid1;

   input tlu_cerer_icdp;		// enable for icdp perr

   input [7:0] tlu_dec_pstate_pef;     	// pstate enable fp bit
   input [7:0] fgu_fprs_fef;	       	// fprs enable fp bit
   input [7:0] tlu_dec_hpstate_hpriv;  	// hpriv bits
   input [7:0] tlu_dec_pstate_priv;    	// priv bits

   input [7:0] tlu_pstate_am;		// address mask bit from the pstate register

   input [1:0] tlu_window_block;	// tlu is doing a window operation and needs a hole created

   input exu0_window_block;		// exu0 is doing a window operation and needs a hole created
   input exu1_window_block;      	// exu1 is doing a window operation and needs a hole created

   input lsu_cpq_stall;			// lsu stalls all other lsu ops at decode

   input [32:0] ifu_buf0_inst0;		// instructions for each of the threads
   input [32:0] ifu_buf0_inst1;
   input [32:0] ifu_buf0_inst2;
   input [32:0] ifu_buf0_inst3;
   input [32:0] ifu_buf0_inst4;
   input [32:0] ifu_buf0_inst5;
   input [32:0] ifu_buf0_inst6;
   input [32:0] ifu_buf0_inst7;

   input [4:0] ifu_buf0_excp0;		// encoding of the various fetch exceptions that can occur
   input [4:0] ifu_buf0_excp1;
   input [4:0] ifu_buf0_excp2;
   input [4:0] ifu_buf0_excp3;
   input [4:0] ifu_buf0_excp4;
   input [4:0] ifu_buf0_excp5;
   input [4:0] ifu_buf0_excp6;
   input [4:0] ifu_buf0_excp7;

   input [7:0]  tlu_flush_ifu;

   input [7:0]  pku_load_flush_w;

   input [1:0]  pku_inst_cnt_brtaken00;		// count of instructions at e,m,b stages needed to compute the PC at decode (to tlu)
   input [1:0]  pku_inst_cnt_brtaken01;
   input [1:0]  pku_inst_cnt_brtaken02;
   input [1:0]  pku_inst_cnt_brtaken03;
   input [1:0]  pku_inst_cnt_brtaken04;
   input [1:0]  pku_inst_cnt_brtaken05;
   input [1:0]  pku_inst_cnt_brtaken06;
   input [1:0]  pku_inst_cnt_brtaken07;

   input [1:0]  pku_inst_cnt_brtaken10;		// count of instructions at e,m,b stages needed to compute the PC at decode (to tlu)
   input [1:0]  pku_inst_cnt_brtaken11;
   input [1:0]  pku_inst_cnt_brtaken12;
   input [1:0]  pku_inst_cnt_brtaken13;
   input [1:0]  pku_inst_cnt_brtaken14;
   input [1:0]  pku_inst_cnt_brtaken15;
   input [1:0]  pku_inst_cnt_brtaken16;
   input [1:0]  pku_inst_cnt_brtaken17;

   input [7:0]  pku_base_pick_p;   // base pick signals with swl_cancel_pick but not decode cancel

   input [3:0]  pku_raw_pick0_p;   // raw pick signals to ifu to mux pc addresses (no swl_cancel_pick or decode cancel)
   input [7:4]  pku_raw_pick1_p;   

   input [7:0]  pku_annul_ds_dcti_brtaken0_e;	// the DS of the dcti at the e stage is annulled this cycle
   input [7:0]  pku_annul_ds_dcti_brtaken1_e;	// the DS of the dcti at the e stage is annulled this cycle

   input [7:0] 	pku_valid_e;		// inst at e stage is valid (takes annul into account)

   input [7:0]  pku_ds_e;  		// inst at e stage is a DS (tlu)

   input [7:0] 	pku_lsu_p;		// lsu op at pick
   input [7:0] 	pku_fgu_p;		// fgu op at pick
   input [7:0] 	pku_pdist_p;		// pdist op at pick
   input [7:0] 	pku_twocycle_p;		// twocycle op at pick (std or casa)
   input [7:0] 	pku_idest_p;		// inst at p has int dest
   input [7:0] 	pku_fdest_p;		// inst at p has fp dest

   input [7:0] 	pku_fsrc_rd_p;		// inst at p has fp rd src
   input [7:0] 	pku_isrc_rs1_p;		// inst at p has rs1 src
   input [7:0] 	pku_isrc_rs2_p;		// inst at p has rs2 src
   input [7:0] 	pku_isrc_rd_p;		// inst at p has rd src

   input [7:0] 	pku_flush_f1;		// flush inst at f1 in the fgu pipe
   input [7:0] 	pku_flush_f2;		// flush inst at f2 in the fgu pipe
   input [7:0] 	pku_flush_lm;		// flush inst at m in the lsu pipe
   input [7:0] 	pku_flush_lb;		// flush inst at b in the lsu pipe
   input [7:0] 	pku_flush_m;		// flush inst at m in the integer pipe
   input [7:0] 	pku_flush_b;		// flush inst at b in the integer pipe

   input 	spu_mult_request;	// spu is requesting a hole be created for running a crypto multiply through the fgu pipe

   input       lsu_block_store_stall;   // stall decode to read the sources of the store
   input [4:3] lsu_block_store_rd;	// rd of the block store
   input [2:0] lsu_block_store_tid;	// tid of the block store

   input 	tlu_dtlb_reload_stall;  // stall decode of lsu ops due to dtlb fill operation
   
   input fgu_ecc_asi_stall;		// fgu ecc stall

   input [3:0]  exu0_oddwin_b;		// is the current window odd or not for TG0           
   input [3:0]  exu1_oddwin_b;		// is the current window odd or not for TG1           

   input [1:0]	fgu_idiv_stall;    	// integer divide stall; no int ops to FGU
   input fgu_fdiv_stall;    		// float divide stall; no float loads to the LSU

   input [1:0]  dec_br_taken_e1;

   // exu interface
   output [7:0]	del_pick_d;

   output [4:0] dec_inst0_rd_d;		// rd for TG0 at decode
   output [4:0] dec_inst1_rd_d;		// rd for TG1 at decode

   output dec_rs1_addr0_e;		// tell exu to put rs1 onto the lsu address bus for casa
   output dec_rs1_addr1_e;	

   output [32:0] dec_inst0_d;		// inst for TG0 at decode
   output [32:0] dec_inst1_d;		// inst for TG1 at decode

   output 	 dec_decode0_d;		// inst at d stage for TG0 is decoded this cycle
   output 	 dec_decode1_d;		// inst at d stage for TG1 is decoded this cycle
   output 	 dec_valid0_d;		// inst at d stage for TG0 is valid this cycle
   output 	 dec_valid1_d;		// inst at d stage for TG1 is valid this cycle

   output [1:0]	 dec_true_valid_e;	// inst at E are valid taking exceptions into account

   output [1:0]  dec_tid0_d;		// TID for exu0
   output [1:0]  dec_tid1_d;		// TID for exu1
   output [1:0]  dec_tid0_p;		// TID for IRF
   output [1:0]  dec_tid1_p;

   output [7:0]  dec_raw_pick_p;	// fast signals for tlu address calculations

   output [4:0]  dec_inst0_rs1_p;	// TG0 rs1      
   output [4:0]  dec_inst0_rs2_p;	// TG0 rs2      
   output [4:0]  dec_inst0_rs3_p;	// TG0 rs3      
   output 	 dec_inst0_rs1_vld_p;	// TG0 rs1 valid
   output 	 dec_inst0_rs2_vld_p;	// TG0 rs2 valid	
   output 	 dec_inst0_rs3_vld_p;	// TG0 rs3 valid

   output [4:0]  dec_inst1_rs1_p;	// TG1 rs1      
   output [4:0]  dec_inst1_rs2_p;	// TG1 rs2      
   output [4:0]  dec_inst1_rs3_p;	// TG1 rs3      
   output 	 dec_inst1_rs1_vld_p;	// TG1 rs1 valid
   output 	 dec_inst1_rs2_vld_p;	// TG1 rs2 valid
   output 	 dec_inst1_rs3_vld_p;	// TG1 rs3 valid

   // fgu interface
   output [4:0]  dec_frf_r1_addr_d;	// FRF r1 read addr
   output [4:0]  dec_frf_r2_addr_d;	// FRF r2 read addr (including store-floats)
   output 	 dec_frf_r1_vld_d;	// FRF r1 read valid
   output 	 dec_frf_r2_vld_d;	// FRF r2 read valid
   output 	 dec_frf_r1_32b_d;	// FRF rs1 source is single-precision
   output 	 dec_frf_r2_32b_d;	// FRF rs2 source is single-precision
   output 	 dec_frf_r1_odd32b_d;	// FRF rs1 source is single-precision and odd
   output 	 dec_frf_r2_odd32b_d;	// FRF rs2 source is single-precision and odd
   output [4:0]  dec_frf_w_addr_d;	// FRF write addr
   output 	 dec_frf_w_vld_d;	// FRF write addr is valid
   output 	 dec_frf_w_32b_d;	// FRF write is single precision
   output 	 dec_frf_w_odd32b_d;	// FRF write is single precision; rd is odd
   output 	 dec_exu_src_vld_d;	// FGU op has any valid exu src
   output [4:0]  dec_irf_w_addr_d;      // RD for an integer op executed by the FGU
   output 	 dec_frf_store_d;	// store-float of FRF data
   output 	 dec_fsr_store_d;	// store-float of FSR data
   output [5:0]  dec_fgu_op3_d;		// op3 field
   output [7:0]  dec_fgu_opf_d;		// opf field
   output 	 dec_fgu_decode_d;	// FGU op decoded this cycle
   output [2:0]  dec_fgu_tid_d;		// TID for FGU op
   output 	 dec_flush_f1;		// Flush f1 stage of the FGU
   output 	 dec_flush_f2;		// Flush f2 stage of the FGU
   output 	 dec_flush_lm;		// Flush the m stage of a load
   output 	 dec_flush_lb;		// Flush the bypass stage of a load
   output [1:0]  dec_flush_m;           // Flush the m stage of the exu's
   output [1:0]  dec_flush_b;           // Flush the b stage of the exu's
   output 	 dec_spu_grant_d;	// SPU grant for a crypto multiply
   output 	 dec_spu_grant_fgu_d;	// SPU grant for a crypto multiply
   output [7:0]  dec_block_store_b;     // to the TLU
   output [1:0]  dec_load_flush_w;	// to IFU
   
   
   // tlu interface
   output [4:0] dec_exc0_m;             // encoded exception status to tlu
   output [4:0] dec_exc1_m;

   output [1:0]  dec_inst0_cnt;	 		// count of instructions at e,m,b stages for inst at decode (TG0)
   output [1:0]  dec_inst1_cnt;     		// count of instructions at e,m,b stages for inst at decode (TG1)

   output [1:0]  dec_tid0_m;			// TID for inst TG0
   output [1:0]  dec_tid1_m;			// TID for inst TG1
   output [1:0]  dec_inst_valid_m;		// valid inst
   output [1:0]  dec_lsu_inst_m;		// lsu inst
   output [1:0]  dec_fgu_inst_m;		// fgu inst
   output [1:0]  dec_cti_inst_m;		// cti inst

   output [1:0]  dec_illegal_inst_m;		// illegal inst
   output [1:0]  dec_icache_perr_m;	        // icache parity error at m stage
   output [1:0]  dec_priv_exc_m;		// priv exception
   output [1:0]  dec_hpriv_exc_m;		// hpriv exception
   output [1:0]  dec_fpdisable_exc_m;   	// fp disable exception
   output [1:0]  dec_br_taken_m;		// br is taken at m stage	
   output [1:0]  dec_done_inst_m;		// DONE
   output [1:0]  dec_retry_inst_m;		// RETRY
   output [1:0]  dec_sir_inst_m;		// SIR

   output [1:0]  dec_annul_ds_m;		// DS of branch is annuled
   output [1:0]  dec_ds_m;			// this inst is DS

   output [1:0]  dec_fgu_sel_e;			// mux select between TG's for fgu ops
   output [1:0]	 dec_fgu_sel_m;			// mux select between TG's for fgu ops

   output 	 dec_lsu_sel0_e;		// mux select between TG's for lsu ops
   output 	 dec_lsu_sel1_e;

   output 	 dec_lsu_sel0_lower_e;		// mux selects taking pstate AM into account (exu)
   output 	 dec_lsu_sel1_lower_e;

   output 	 dec_lsu_sel0_upper_e;		// mux selects taking pstate AM into account (exu)
   output 	 dec_lsu_sel1_upper_e;

   output 	 dec_rs1_addr0_upper_e;
   output 	 dec_rs1_addr1_upper_e;

   // lsu interface
   output 	 dec_ld_inst_e;         	// operation is a load or load-like
   output 	 dec_st_inst_e;         	// operation is a store or store-like
   output 	 dec_fsr_ldst_e;         	// ldfsr, stfsr inst
   output 	 dec_fpldst_inst_e;     	// FP load or store
   output 	 dec_ldst_dbl_e;        	// ldd inst
   output 	 dec_pref_inst_e;       	// prefetch inst
   output 	 dec_flush_inst_e;      	// flush inst
   output 	 dec_memstbar_inst_e;		// membar, stbar inst
   output [1:0]  dec_ldst_sz_e;			// size of the memory reference
   output [4:3]  dec_frf_r2_addr_e;		// FRF r2 read addr 
   output 	 dec_sr_inst_e;        		// state register instruction
   output 	 dec_pr_inst_e;        		// privileged instruction
   output 	 dec_hpr_inst_e;        	// hypervisor instruction
   output 	 dec_casa_inst_e;       	// casa inst
   output 	 dec_ldstub_inst_e;     	// ldstub inst
   output 	 dec_swap_inst_e;       	// swap inst
   output 	 dec_altspace_d;		// is an alternate inst
   output 	 dec_sign_ext_e;        	// is a signed load
   output [4:0]  dec_sraddr_e;          	// register number for rdasr inst
   output 	 dec_imm_asi_vld_d;     	// immediate form of ASI's
   output [7:0]  dec_imm_asi_d;         	// value of ASI access
   output [1:0]  dec_lsu_tid0_d;		// lsu tid at d; real lsu
   output [1:0]  dec_lsu_tid1_d;		// lsu tid at d; real lsu
   output        dec_lsu_tg_d;			// lsu thread group at d
   output [4:0]  dec_lsu_rd_e;			// lsu rd at e
   output 	 dec_ld_inst_d;			// load inst decoded

   // pmu interface
   output [9:0] dec_instr0_type_d;		// pmu stuff thread group 0
   output [9:0] dec_instr1_type_d;		// pmu stuff thread group 1

   output [1:0]  dec_valid_e;			// valid for inst at e stage (takes annul into account)
   output [1:0]  dec_pmu_valid_e;		// valid for inst at e stage (takes annul into account); dont include ifetch_err
   output 	 dec_fgu_valid_e;		// fgu is valid at e stage (takes annul into account)


   output [1:0] dec_exu_clken;			// clk enable signals to the exu
   output       dec_lsu_sel0_d;                 // to the pmu to decide which tid to use for lsu at d stage

   output [1:0] dec_ierr_d;  		// tell pku that an inst error has occurred: illegal, parity error or ifetch error

   output [7:0] dec_block_store_stall;  // prevent window ops from coming too early after a block store 

   output        scan_out;

   dec_del_ctl del (
		    .scan_in(del_scanin),
		    .scan_out(del_scanout),
		    .l2clk(l2clk),
		    .dec_inst0_rs1_d(dec_inst0_d[18:14]),
		    .dec_inst0_rs2_d(dec_inst0_d[4:0]),
		    .dec_inst0_b31(dec_inst0_d[31]),
		    .dec_inst0_raw_rd_d(dec_inst0_d[29:25]),
		    .dec_inst0_op3_d(dec_inst0_d[24:19]),
		    .dec_inst0_opf_d(dec_inst0_d[12:5]),
		    .dec_inst1_rs1_d(dec_inst1_d[18:14]),
		    .dec_inst1_rs2_d(dec_inst1_d[4:0]),
		    .dec_inst1_b31(dec_inst1_d[31]),
		    .dec_inst1_raw_rd_d(dec_inst1_d[29:25]),
		    .dec_inst1_op3_d(dec_inst1_d[24:19]),
		    .dec_inst1_opf_d(dec_inst1_d[12:5]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .lsu_dec_pmen(lsu_dec_pmen),
  .lsu_exu_pmen(lsu_exu_pmen),
  .spc_core_running_status(spc_core_running_status[7:0]),
  .power_throttle(power_throttle[2:0]),
  .lb_lbist_running(lb_lbist_running),
  .pku_idest_p(pku_idest_p[7:0]),
  .pku_fdest_p(pku_fdest_p[7:0]),
  .pku_fsrc_rd_p(pku_fsrc_rd_p[7:0]),
  .pku_lsu_p(pku_lsu_p[7:0]),
  .pku_fgu_p(pku_fgu_p[7:0]),
  .pku_pdist_p(pku_pdist_p[7:0]),
  .pku_twocycle_p(pku_twocycle_p[7:0]),
  .pku_inst_cnt_brtaken00(pku_inst_cnt_brtaken00[1:0]),
  .pku_inst_cnt_brtaken01(pku_inst_cnt_brtaken01[1:0]),
  .pku_inst_cnt_brtaken02(pku_inst_cnt_brtaken02[1:0]),
  .pku_inst_cnt_brtaken03(pku_inst_cnt_brtaken03[1:0]),
  .pku_inst_cnt_brtaken04(pku_inst_cnt_brtaken04[1:0]),
  .pku_inst_cnt_brtaken05(pku_inst_cnt_brtaken05[1:0]),
  .pku_inst_cnt_brtaken06(pku_inst_cnt_brtaken06[1:0]),
  .pku_inst_cnt_brtaken07(pku_inst_cnt_brtaken07[1:0]),
  .pku_inst_cnt_brtaken10(pku_inst_cnt_brtaken10[1:0]),
  .pku_inst_cnt_brtaken11(pku_inst_cnt_brtaken11[1:0]),
  .pku_inst_cnt_brtaken12(pku_inst_cnt_brtaken12[1:0]),
  .pku_inst_cnt_brtaken13(pku_inst_cnt_brtaken13[1:0]),
  .pku_inst_cnt_brtaken14(pku_inst_cnt_brtaken14[1:0]),
  .pku_inst_cnt_brtaken15(pku_inst_cnt_brtaken15[1:0]),
  .pku_inst_cnt_brtaken16(pku_inst_cnt_brtaken16[1:0]),
  .pku_inst_cnt_brtaken17(pku_inst_cnt_brtaken17[1:0]),
  .exu_test_tid0(exu_test_tid0[1:0]),
  .exu_test_addr0(exu_test_addr0[4:0]),
  .exu_test_valid0(exu_test_valid0),
  .exu_test_tid1(exu_test_tid1[1:0]),
  .exu_test_addr1(exu_test_addr1[4:0]),
  .exu_test_valid1(exu_test_valid1),
  .ded_exc0_d(ded_exc0_d[4:0]),
  .ded_exc1_d(ded_exc1_d[4:0]),
  .tlu_dec_pstate_pef(tlu_dec_pstate_pef[7:0]),
  .fgu_fprs_fef(fgu_fprs_fef[7:0]),
  .tlu_dec_hpstate_hpriv(tlu_dec_hpstate_hpriv[7:0]),
  .tlu_dec_pstate_priv(tlu_dec_pstate_priv[7:0]),
  .dcd_wrtick_d(dcd_wrtick_d[1:0]),
  .lsu_cpq_stall(lsu_cpq_stall),
  .dcd_callclass_d(dcd_callclass_d[1:0]),
  .dcd_tcc_d(dcd_tcc_d[1:0]),
  .dcd_specbr_d(dcd_specbr_d[1:0]),
  .dcd_specfp_d(dcd_specfp_d[1:0]),
  .dcd_exu_src_d(dcd_exu_src_d[1:0]),
  .dcd_killfgu_d(dcd_killfgu_d[1:0]),
  .dcd_sir_d(dcd_sir_d[1:0]),
  .dcd_stdfa_d(dcd_stdfa_d[1:0]),
  .pku_valid_e(pku_valid_e[7:0]),
  .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[7:0]),
  .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[7:0]),
  .exu0_window_block(exu0_window_block),
  .exu1_window_block(exu1_window_block),
  .tlu_window_block(tlu_window_block[1:0]),
  .fgu_idiv_stall(fgu_idiv_stall[1:0]),
  .fgu_fdiv_stall(fgu_fdiv_stall),
  .fgu_ecc_asi_stall(fgu_ecc_asi_stall),
  .dcd_fpdisable_d(dcd_fpdisable_d[1:0]),
  .dcd_lsize0_d(dcd_lsize0_d[1:0]),
  .dcd_lsize1_d(dcd_lsize1_d[1:0]),
  .dcd_lsu_sign_ext_d(dcd_lsu_sign_ext_d[1:0]),
  .dcd_load_d(dcd_load_d[1:0]),
  .dcd_store_d(dcd_store_d[1:0]),
  .dcd_sethi_d(dcd_sethi_d[1:0]),
  .dcd_lsdouble_d(dcd_lsdouble_d[1:0]),
  .dcd_prefetch_d(dcd_prefetch_d[1:0]),
  .dcd_flush_d(dcd_flush_d[1:0]),
  .dcd_memstbar_d(dcd_memstbar_d[1:0]),
  .dcd_pr_d(dcd_pr_d[1:0]),
  .dcd_priv_d(dcd_priv_d[1:0]),
  .dcd_hpr_d(dcd_hpr_d[1:0]),
  .dcd_sr_d(dcd_sr_d[1:0]),
  .dcd_casa_d(dcd_casa_d[1:0]),
  .dcd_ldstub_d(dcd_ldstub_d[1:0]),
  .dcd_alt_d(dcd_alt_d[1:0]),
  .dcd_alti_d(dcd_alti_d[1:0]),
  .dcd_swap_d(dcd_swap_d[1:0]),
  .dcd_fsrc_rs1_d(dcd_fsrc_rs1_d[1:0]),
  .dcd_fsrc_rs2_d(dcd_fsrc_rs2_d[1:0]),
  .dcd_fpdest_single_d(dcd_fpdest_single_d[1:0]),
  .dcd_fp_rs1_single_d(dcd_fp_rs1_single_d[1:0]),
  .dcd_fp_rs2_single_d(dcd_fp_rs2_single_d[1:0]),
  .dcd_fsrsync_d(dcd_fsrsync_d[1:0]),
  .dcd_done_d(dcd_done_d[1:0]),
  .dcd_retry_d(dcd_retry_d[1:0]),
  .dcd_save_restore_d(dcd_save_restore_d[1:0]),
  .ded_oddwin0_d(ded_oddwin0_d),
  .ded_oddwin1_d(ded_oddwin1_d),
  .ded_perr_p(ded_perr_p[1:0]),
  .ded_ferr_p(ded_ferr_p[1:0]),
  .ded_legal_p(ded_legal_p[1:0]),
  .pku_base_pick_p(pku_base_pick_p[7:0]),
  .pku_raw_pick0_p(pku_raw_pick0_p[3:0]),
  .pku_raw_pick1_p(pku_raw_pick1_p[7:4]),
  .pku_ds_e(pku_ds_e[7:0]),
  .pku_load_flush_w(pku_load_flush_w[7:0]),
  .tlu_flush_ifu(tlu_flush_ifu[7:0]),
  .pku_flush_f1(pku_flush_f1[7:0]),
  .pku_flush_f2(pku_flush_f2[7:0]),
  .pku_flush_lm(pku_flush_lm[7:0]),
  .pku_flush_lb(pku_flush_lb[7:0]),
  .pku_flush_m(pku_flush_m[7:0]),
  .pku_flush_b(pku_flush_b[7:0]),
  .dec_br_taken_e1(dec_br_taken_e1[1:0]),
  .spu_mult_request(spu_mult_request),
  .lsu_block_store_stall(lsu_block_store_stall),
  .lsu_block_store_rd(lsu_block_store_rd[4:3]),
  .lsu_block_store_tid(lsu_block_store_tid[2:0]),
  .tlu_dtlb_reload_stall(tlu_dtlb_reload_stall),
  .tlu_pstate_am(tlu_pstate_am[7:0]),
  .dec_valid0_d(dec_valid0_d),
  .dec_valid1_d(dec_valid1_d),
  .dec_decode0_d(dec_decode0_d),
  .dec_decode1_d(dec_decode1_d),
  .del_noshift0_d(del_noshift0_d),
  .del_noshift1_d(del_noshift1_d),
  .dec_inst0_rd_d(dec_inst0_rd_d[4:0]),
  .dec_inst1_rd_d(dec_inst1_rd_d[4:0]),
  .dec_tid0_d(dec_tid0_d[1:0]),
  .dec_tid1_d(dec_tid1_d[1:0]),
  .dec_tid0_p(dec_tid0_p[1:0]),
  .dec_tid1_p(dec_tid1_p[1:0]),
  .dec_valid_e(dec_valid_e[1:0]),
  .dec_pmu_valid_e(dec_pmu_valid_e[1:0]),
  .dec_fgu_valid_e(dec_fgu_valid_e),
  .dec_frf_r1_addr_d(dec_frf_r1_addr_d[4:0]),
  .dec_frf_r2_addr_d(dec_frf_r2_addr_d[4:0]),
  .dec_frf_r2_addr_e(dec_frf_r2_addr_e[4:3]),
  .dec_frf_r1_vld_d(dec_frf_r1_vld_d),
  .dec_frf_r2_vld_d(dec_frf_r2_vld_d),
  .dec_frf_r1_32b_d(dec_frf_r1_32b_d),
  .dec_frf_r2_32b_d(dec_frf_r2_32b_d),
  .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d),
  .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d),
  .dec_frf_w_addr_d(dec_frf_w_addr_d[4:0]),
  .dec_frf_w_vld_d(dec_frf_w_vld_d),
  .dec_frf_w_32b_d(dec_frf_w_32b_d),
  .dec_frf_w_odd32b_d(dec_frf_w_odd32b_d),
  .dec_spu_grant_d(dec_spu_grant_d),
  .dec_spu_grant_fgu_d(dec_spu_grant_fgu_d),
  .dec_exu_src_vld_d(dec_exu_src_vld_d),
  .dec_irf_w_addr_d(dec_irf_w_addr_d[4:0]),
  .dec_frf_store_d(dec_frf_store_d),
  .dec_fsr_store_d(dec_fsr_store_d),
  .dec_fgu_op3_d(dec_fgu_op3_d[5:0]),
  .dec_fgu_opf_d(dec_fgu_opf_d[7:0]),
  .dec_fgu_decode_d(dec_fgu_decode_d),
  .dec_fgu_tid_d(dec_fgu_tid_d[2:0]),
  .dec_flush_f1(dec_flush_f1),
  .dec_flush_f2(dec_flush_f2),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .dec_flush_m(dec_flush_m[1:0]),
  .dec_flush_b(dec_flush_b[1:0]),
  .dec_block_store_b(dec_block_store_b[7:0]),
  .dec_exc0_m(dec_exc0_m[4:0]),
  .dec_exc1_m(dec_exc1_m[4:0]),
  .dec_inst0_cnt(dec_inst0_cnt[1:0]),
  .dec_inst1_cnt(dec_inst1_cnt[1:0]),
  .dec_tid0_m(dec_tid0_m[1:0]),
  .dec_tid1_m(dec_tid1_m[1:0]),
  .dec_inst_valid_m(dec_inst_valid_m[1:0]),
  .dec_lsu_inst_m(dec_lsu_inst_m[1:0]),
  .dec_fgu_inst_m(dec_fgu_inst_m[1:0]),
  .dec_cti_inst_m(dec_cti_inst_m[1:0]),
  .dec_illegal_inst_m(dec_illegal_inst_m[1:0]),
  .dec_icache_perr_m(dec_icache_perr_m[1:0]),
  .dec_priv_exc_m(dec_priv_exc_m[1:0]),
  .dec_hpriv_exc_m(dec_hpriv_exc_m[1:0]),
  .dec_fpdisable_exc_m(dec_fpdisable_exc_m[1:0]),
  .dec_br_taken_m(dec_br_taken_m[1:0]),
  .dec_done_inst_m(dec_done_inst_m[1:0]),
  .dec_retry_inst_m(dec_retry_inst_m[1:0]),
  .dec_sir_inst_m(dec_sir_inst_m[1:0]),
  .dec_ds_m(dec_ds_m[1:0]),
  .dec_annul_ds_m(dec_annul_ds_m[1:0]),
  .dec_fgu_sel_e(dec_fgu_sel_e[1:0]),
  .dec_fgu_sel_m(dec_fgu_sel_m[1:0]),
  .dec_lsu_sel0_e(dec_lsu_sel0_e),
  .dec_lsu_sel1_e(dec_lsu_sel1_e),
  .dec_rs1_addr0_e(dec_rs1_addr0_e),
  .dec_rs1_addr1_e(dec_rs1_addr1_e),
  .dec_lsu_sel0_upper_e(dec_lsu_sel0_upper_e),
  .dec_lsu_sel1_upper_e(dec_lsu_sel1_upper_e),
  .dec_lsu_sel0_lower_e(dec_lsu_sel0_lower_e),
  .dec_lsu_sel1_lower_e(dec_lsu_sel1_lower_e),
  .dec_rs1_addr0_upper_e(dec_rs1_addr0_upper_e),
  .dec_rs1_addr1_upper_e(dec_rs1_addr1_upper_e),
  .del_pick_d(del_pick_d[7:0]),
  .dec_ld_inst_e(dec_ld_inst_e),
  .dec_st_inst_e(dec_st_inst_e),
  .dec_fsr_ldst_e(dec_fsr_ldst_e),
  .dec_fpldst_inst_e(dec_fpldst_inst_e),
  .dec_ldst_dbl_e(dec_ldst_dbl_e),
  .dec_pref_inst_e(dec_pref_inst_e),
  .dec_flush_inst_e(dec_flush_inst_e),
  .dec_memstbar_inst_e(dec_memstbar_inst_e),
  .dec_sr_inst_e(dec_sr_inst_e),
  .dec_pr_inst_e(dec_pr_inst_e),
  .dec_hpr_inst_e(dec_hpr_inst_e),
  .dec_casa_inst_e(dec_casa_inst_e),
  .dec_ldstub_inst_e(dec_ldstub_inst_e),
  .dec_swap_inst_e(dec_swap_inst_e),
  .dec_altspace_d(dec_altspace_d),
  .dec_sign_ext_e(dec_sign_ext_e),
  .dec_sraddr_e(dec_sraddr_e[4:0]),
  .dec_imm_asi_vld_d(dec_imm_asi_vld_d),
  .dec_imm_asi_d(dec_imm_asi_d[7:0]),
  .dec_ldst_sz_e(dec_ldst_sz_e[1:0]),
  .dec_ld_inst_d(dec_ld_inst_d),
  .dec_lsu_tid0_d(dec_lsu_tid0_d[1:0]),
  .dec_lsu_tid1_d(dec_lsu_tid1_d[1:0]),
  .dec_lsu_tg_d(dec_lsu_tg_d),
  .dec_lsu_rd_e(dec_lsu_rd_e[4:0]),
  .del_test0_sel_p(del_test0_sel_p),
  .del_twocycle0_std_p(del_twocycle0_std_p),
  .del_twocycle0_rs2_p(del_twocycle0_rs2_p),
  .del_default0_sel_p(del_default0_sel_p),
  .del_test1_sel_p(del_test1_sel_p),
  .del_twocycle1_std_p(del_twocycle1_std_p),
  .del_twocycle1_rs2_p(del_twocycle1_rs2_p),
  .del_default1_sel_p(del_default1_sel_p),
  .del_test_addr0_p(del_test_addr0_p[4:0]),
  .del_test_addr1_p(del_test_addr1_p[4:0]),
  .dec_instr0_type_d(dec_instr0_type_d[9:0]),
  .dec_instr1_type_d(dec_instr1_type_d[9:0]),
  .dec_exu_clken(dec_exu_clken[1:0]),
  .del_tg_clken(del_tg_clken[1:0]),
  .dec_true_valid_e(dec_true_valid_e[1:0]),
  .dec_load_flush_w(dec_load_flush_w[1:0]),
  .dec_lsu_sel0_d(dec_lsu_sel0_d),
  .dec_raw_pick_p(dec_raw_pick_p[7:0]),
  .dec_ierr_d(dec_ierr_d[1:0]),
  .dec_block_store_stall(dec_block_store_stall[7:0])
		    );


   dec_ded_ctl ded0 (
		.scan_in(ded0_scanin),
		.scan_out(ded0_scanout),
		.l2clk(l2clk),
	        .clken(del_tg_clken[0]),
		.del_test_sel_p(del_test0_sel_p),	
		.del_twocycle_std_p(del_twocycle0_std_p),	
		.del_twocycle_rs2_p(del_twocycle0_rs2_p),	
		.del_default_sel_p(del_default0_sel_p),	
		.del_test_addr_p(del_test_addr0_p),	
		.ifu_buf0_inst0(ifu_buf0_inst0[32:0]),	
		.ifu_buf0_inst1(ifu_buf0_inst1[32:0]),	
		.ifu_buf0_inst2(ifu_buf0_inst2[32:0]),	
		.ifu_buf0_inst3(ifu_buf0_inst3[32:0]),	
		.ifu_buf0_excp0(ifu_buf0_excp0[4:0]),	
		.ifu_buf0_excp1(ifu_buf0_excp1[4:0]),	
		.ifu_buf0_excp2(ifu_buf0_excp2[4:0]),	
		.ifu_buf0_excp3(ifu_buf0_excp3[4:0]),	
		.del_noshift_d(del_noshift0_d),	
		.pku_raw_pick_p(pku_raw_pick0_p[3:0]),     	
		.pku_isrc_rs1_p(pku_isrc_rs1_p[3:0]),	
		.pku_isrc_rs2_p(pku_isrc_rs2_p[3:0]),	
		.pku_isrc_rd_p(pku_isrc_rd_p[3:0]),	
		.exu_oddwin_b(exu0_oddwin_b[3:0]),	
		.ded_ferr_p(ded_ferr_p[0]),	
		.ded_perr_p(ded_perr_p[0]),	
		.ded_ferr_d(ded_ferr_d[0]),	
		.ded_perr_d(ded_perr_d[0]),	
		.ded_legal_p(ded_legal_p[0]),
		.ded_oddwin_d(ded_oddwin0_d),	
		.dec_inst_d(dec_inst0_d[32:0]),
		.dec_inst_rs1_p(dec_inst0_rs1_p[4:0]),
		.dec_inst_rs2_p(dec_inst0_rs2_p[4:0]),
		.dec_inst_rs3_p(dec_inst0_rs3_p[4:0]),
		.dec_inst_rs1_vld_p(dec_inst0_rs1_vld_p),
		.dec_inst_rs2_vld_p(dec_inst0_rs2_vld_p),
		.dec_inst_rs3_vld_p(dec_inst0_rs3_vld_p),
		.ded_exc_d(ded_exc0_d[4:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tlu_cerer_icdp(tlu_cerer_icdp)
		);		

   dec_ded_ctl ded1 (
		.scan_in(ded1_scanin),
		.scan_out(ded1_scanout),
		.l2clk(l2clk),
	        .clken(del_tg_clken[1]),
		.del_test_sel_p(del_test1_sel_p),	
		.del_twocycle_std_p(del_twocycle1_std_p),	
		.del_twocycle_rs2_p(del_twocycle1_rs2_p),	
		.del_default_sel_p(del_default1_sel_p),	
		.del_test_addr_p(del_test_addr1_p),	
		.ifu_buf0_inst0(ifu_buf0_inst4[32:0]),	
		.ifu_buf0_inst1(ifu_buf0_inst5[32:0]),	
		.ifu_buf0_inst2(ifu_buf0_inst6[32:0]),	
		.ifu_buf0_inst3(ifu_buf0_inst7[32:0]),	
		.ifu_buf0_excp0(ifu_buf0_excp4[4:0]),	
		.ifu_buf0_excp1(ifu_buf0_excp5[4:0]),	
		.ifu_buf0_excp2(ifu_buf0_excp6[4:0]),	
		.ifu_buf0_excp3(ifu_buf0_excp7[4:0]),	
		.del_noshift_d(del_noshift1_d),	
		.pku_raw_pick_p(pku_raw_pick1_p[7:4]),     	
		.pku_isrc_rs1_p(pku_isrc_rs1_p[7:4]),	
		.pku_isrc_rs2_p(pku_isrc_rs2_p[7:4]),	
		.pku_isrc_rd_p(pku_isrc_rd_p[7:4]),	
		.exu_oddwin_b(exu1_oddwin_b[3:0]),	
		.ded_ferr_p(ded_ferr_p[1]),	
		.ded_perr_p(ded_perr_p[1]),	
		.ded_ferr_d(ded_ferr_d[1]),	
		.ded_perr_d(ded_perr_d[1]),	
		.ded_legal_p(ded_legal_p[1]),
		.ded_oddwin_d(ded_oddwin1_d),	
		.dec_inst_d(dec_inst1_d[32:0]),
		.dec_inst_rs1_p(dec_inst1_rs1_p[4:0]),
		.dec_inst_rs2_p(dec_inst1_rs2_p[4:0]),
		.dec_inst_rs3_p(dec_inst1_rs3_p[4:0]),
		.dec_inst_rs1_vld_p(dec_inst1_rs1_vld_p),
		.dec_inst_rs2_vld_p(dec_inst1_rs2_vld_p),
		.dec_inst_rs3_vld_p(dec_inst1_rs3_vld_p),
		.ded_exc_d(ded_exc1_d[4:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tlu_cerer_icdp(tlu_cerer_icdp)
		);		


   dec_dcd_ctl dcd0 (
		     .ded_ferr_d(ded_ferr_d[0]),	
		     .ded_perr_d(ded_perr_d[0]),	
		     .dec_inst_d(dec_inst0_d[31:0]),
		     .dcd_sir_d(dcd_sir_d[0]),
		     .dcd_stdfa_d(dcd_stdfa_d[0]),
		     .dcd_save_restore_d(dcd_save_restore_d[0]),
		     .dcd_exu_src_d(dcd_exu_src_d[0]),
		     .dcd_killfgu_d(dcd_killfgu_d[0]),
		     .dcd_lsize_d(dcd_lsize0_d[1:0]),
		     .dcd_lsu_sign_ext_d(dcd_lsu_sign_ext_d[0]),
		     .dcd_load_d(dcd_load_d[0]),
		     .dcd_store_d(dcd_store_d[0]),
		     .dcd_lsdouble_d(dcd_lsdouble_d[0]),
		     .dcd_prefetch_d(dcd_prefetch_d[0]),
		     .dcd_flush_d(dcd_flush_d[0]),
		     .dcd_memstbar_d(dcd_memstbar_d[0]),
		     .dcd_hpr_d(dcd_hpr_d[0]),
		     .dcd_pr_d(dcd_pr_d[0]),
		     .dcd_priv_d(dcd_priv_d[0]),
		     .dcd_sr_d(dcd_sr_d[0]),
		     .dcd_casa_d(dcd_casa_d[0]),
		     .dcd_ldstub_d(dcd_ldstub_d[0]),
		     .dcd_alt_d(dcd_alt_d[0]),
		     .dcd_alti_d(dcd_alti_d[0]),
		     .dcd_swap_d(dcd_swap_d[0]),
		     .dcd_done_d(dcd_done_d[0]),
		     .dcd_retry_d(dcd_retry_d[0]),
		     .dcd_fsrc_rs1_d(dcd_fsrc_rs1_d[0]),
		     .dcd_fsrc_rs2_d(dcd_fsrc_rs2_d[0]),
		     .dcd_fpdest_single_d(dcd_fpdest_single_d[0]),
		     .dcd_fp_rs1_single_d(dcd_fp_rs1_single_d[0]),
		     .dcd_fp_rs2_single_d(dcd_fp_rs2_single_d[0]),
		     .dcd_fsrsync_d(dcd_fsrsync_d[0]),
		     .dcd_callclass_d(dcd_callclass_d[0]),
		     .dcd_specbr_d(dcd_specbr_d[0]),
		     .dcd_specfp_d(dcd_specfp_d[0]),
		     .dcd_tcc_d(dcd_tcc_d[0]),
		     .dcd_sethi_d(dcd_sethi_d[0]),
		     .dcd_fpdisable_d(dcd_fpdisable_d[0]),
		     .dcd_wrtick_d(dcd_wrtick_d[0])
		     );

   dec_dcd_ctl dcd1 (
		     .ded_ferr_d(ded_ferr_d[1]),	
		     .ded_perr_d(ded_perr_d[1]),	
		     .dec_inst_d(dec_inst1_d[31:0]),
		     .dcd_sir_d(dcd_sir_d[1]),
		     .dcd_stdfa_d(dcd_stdfa_d[1]),
		     .dcd_save_restore_d(dcd_save_restore_d[1]),
		     .dcd_exu_src_d(dcd_exu_src_d[1]),
		     .dcd_killfgu_d(dcd_killfgu_d[1]),
		     .dcd_lsize_d(dcd_lsize1_d[1:0]),
		     .dcd_lsu_sign_ext_d(dcd_lsu_sign_ext_d[1]),
		     .dcd_load_d(dcd_load_d[1]),
		     .dcd_store_d(dcd_store_d[1]),
		     .dcd_lsdouble_d(dcd_lsdouble_d[1]),
		     .dcd_prefetch_d(dcd_prefetch_d[1]),
		     .dcd_flush_d(dcd_flush_d[1]),
		     .dcd_memstbar_d(dcd_memstbar_d[1]),
		     .dcd_hpr_d(dcd_hpr_d[1]),
		     .dcd_pr_d(dcd_pr_d[1]),
		     .dcd_priv_d(dcd_priv_d[1]),
		     .dcd_sr_d(dcd_sr_d[1]),
		     .dcd_casa_d(dcd_casa_d[1]),
		     .dcd_ldstub_d(dcd_ldstub_d[1]),
		     .dcd_alt_d(dcd_alt_d[1]),
		     .dcd_alti_d(dcd_alti_d[1]),
		     .dcd_swap_d(dcd_swap_d[1]),
		     .dcd_done_d(dcd_done_d[1]),
		     .dcd_retry_d(dcd_retry_d[1]),
		     .dcd_fsrc_rs1_d(dcd_fsrc_rs1_d[1]),
		     .dcd_fsrc_rs2_d(dcd_fsrc_rs2_d[1]),
		     .dcd_fpdest_single_d(dcd_fpdest_single_d[1]),
		     .dcd_fp_rs1_single_d(dcd_fp_rs1_single_d[1]),
		     .dcd_fp_rs2_single_d(dcd_fp_rs2_single_d[1]),
		     .dcd_fsrsync_d(dcd_fsrsync_d[1]),
		     .dcd_callclass_d(dcd_callclass_d[1]),
		     .dcd_specbr_d(dcd_specbr_d[1]),
		     .dcd_specfp_d(dcd_specfp_d[1]),
		     .dcd_tcc_d(dcd_tcc_d[1]),
		     .dcd_sethi_d(dcd_sethi_d[1]),
		     .dcd_fpdisable_d(dcd_fpdisable_d[1]),
		     .dcd_wrtick_d(dcd_wrtick_d[1])
		     );

// fixscan start:
assign del_scanin                = scan_in                  ;
assign ded0_scanin               = del_scanout              ;
assign ded1_scanin               = ded0_scanout             ;
assign scan_out                  = ded1_scanout             ;
// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dec_dcd_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dec_dcd_ctl (
  dec_inst_d, 
  ded_perr_d, 
  ded_ferr_d, 
  dcd_lsu_sign_ext_d, 
  dcd_sethi_d, 
  dcd_priv_d, 
  dcd_fsrc_rs1_d, 
  dcd_fsrc_rs2_d, 
  dcd_fpdest_single_d, 
  dcd_fp_rs1_single_d, 
  dcd_fp_rs2_single_d, 
  dcd_fsrsync_d, 
  dcd_callclass_d, 
  dcd_specbr_d, 
  dcd_specfp_d, 
  dcd_tcc_d, 
  dcd_done_d, 
  dcd_retry_d, 
  dcd_load_d, 
  dcd_store_d, 
  dcd_lsdouble_d, 
  dcd_prefetch_d, 
  dcd_flush_d, 
  dcd_memstbar_d, 
  dcd_sr_d, 
  dcd_pr_d, 
  dcd_hpr_d, 
  dcd_casa_d, 
  dcd_ldstub_d, 
  dcd_alt_d, 
  dcd_alti_d, 
  dcd_swap_d, 
  dcd_lsize_d, 
  dcd_killfgu_d, 
  dcd_exu_src_d, 
  dcd_save_restore_d, 
  dcd_sir_d, 
  dcd_stdfa_d, 
  dcd_fpdisable_d, 
  dcd_wrtick_d);
wire priv_u;
wire [31:0] i;
wire casa_u;
wire lsdouble_u;
wire fsrc_rs1_u;
wire fsrc_rs2_u;
wire fpdest_single_u;
wire fp_rs1_single_u;
wire fp_rs2_single_u;
wire fsrsync_u;
wire callclass_u;
wire specbr_u;
wire specfp_u;
wire tcc_u;
wire done_u;
wire retry_u;
wire load_u;
wire store_u;
wire prefetch_u;
wire flush_u;
wire memstbar_u;
wire sr_u;
wire pr_u;
wire hpr_u;
wire ldstub_u;
wire alt_u;
wire alti_u;
wire swap_u;
wire [1:0] lsize_u;
wire killfgu_u;
wire exu_src_u;
wire save_restore_u;
wire sir_u;
wire stdfa_u;
wire fpdisable_u;
wire wrtick_u;
wire kill_decode_d;
wire illegal_d;


 input [31:0] dec_inst_d;       // inst to decode

 input ded_perr_d;		// parity error
 
 input ded_ferr_d;		// ifetch error

 output dcd_lsu_sign_ext_d;	// is a signed load

 output dcd_sethi_d;		// inst is a special sethi inst

		
 output dcd_priv_d;		// autogenerated outputs
 output dcd_fsrc_rs1_d;		
 output dcd_fsrc_rs2_d;
 output dcd_fpdest_single_d;
 output dcd_fp_rs1_single_d;
 output dcd_fp_rs2_single_d;
 output dcd_fsrsync_d;
 output dcd_callclass_d;
 output dcd_specbr_d;
 output dcd_specfp_d;
 output dcd_tcc_d;
 output dcd_done_d;
 output dcd_retry_d;
 output dcd_load_d;
 output dcd_store_d;
 output dcd_lsdouble_d;
 output dcd_prefetch_d;
 output dcd_flush_d;
 output dcd_memstbar_d;
 output dcd_sr_d;
 output dcd_pr_d;
 output dcd_hpr_d;
 output dcd_casa_d;
 output dcd_ldstub_d;
 output dcd_alt_d;
 output dcd_alti_d;
 output dcd_swap_d;
 output [1:0] dcd_lsize_d;
 output dcd_killfgu_d;
 output dcd_exu_src_d;
 output dcd_save_restore_d;
 output dcd_sir_d;
 output dcd_stdfa_d;
 output dcd_fpdisable_d;
 output dcd_wrtick_d;

dec_dcd_ctl_spare_ctl_macro__flops_0__num_2 spares  (
);


// --- autogenerated by n2decode view=dec Wed Aug 10 15:04:27 CDT 2005

assign priv_u = (i[31]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[19]) | (i[31]&i[24]
    &!i[23]&i[22]&!i[21]&!i[19]&i[18]&i[16]) | (i[31]&i[24]&!i[23]&i[22]
    &!i[21]&!i[19]&i[17]&!i[15]&i[14]) | (i[31]&!i[30]&i[28]&!i[26]&i[25]
    &i[24]&i[23]&!i[22]&!i[21]&!i[19]) | (i[31]&!i[30]&i[29]&i[27]&i[24]
    &i[23]&!i[22]&!i[21]&!i[19]) | (i[31]&!i[30]&i[29]&!i[28]&!i[25]
    &i[24]&i[23]&!i[22]&!i[21]&!i[19]) | (!i[30]&i[24]&i[23]&i[22]&i[21]
    &i[20]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[19]&i[18]&!i[17]&!i[14]) | (
    i[31]&i[24]&!i[23]&i[22]&!i[21]&i[20]&!i[19]) | (i[31]&i[24]&i[23]
    &!i[22]&!i[21]&i[20]&!i[19]);

assign casa_u = (i[31]&i[30]&i[24]&i[22]&!i[19]);

assign lsdouble_u = (i[31]&i[30]&!i[22]&i[20]&i[19]);

assign fsrc_rs1_u = (i[31]&!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[7]&!i[6]) | (
    i[31]&!i[30]&!i[13]&!i[12]&i[9]&!i[8]&i[5]) | (i[31]&!i[30]&i[20]
    &!i[13]&i[10]&!i[9]&i[8]) | (i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[9]
    &i[8]&!i[5]) | (i[31]&!i[30]&!i[19]&!i[13]&i[11]&i[10]&i[7]&!i[6]) | (
    i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[7]&i[6]) | (i[31]&!i[30]&i[20]
    &!i[19]&!i[13]&!i[11]&i[10]&!i[5]) | (i[31]&!i[30]&!i[22]&!i[20]
    &!i[19]&!i[13]&!i[12]&i[11]) | (i[31]&!i[30]&!i[13]&!i[12]&i[11]&i[9]
    &!i[8]);

assign fsrc_rs2_u = (i[31]&!i[30]&!i[13]&i[11]&!i[8]&i[6]) | (i[31]&!i[30]&!i[13]
    &i[11]&i[9]&!i[7]) | (i[31]&!i[30]&!i[13]&i[11]&i[8]&!i[6]) | (i[31]
    &!i[30]&!i[19]&!i[13]&!i[11]&i[10]) | (i[31]&!i[30]&!i[13]&i[11]&!i[9]
    &i[7]) | (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[20]) | (i[31]
    &!i[30]&!i[22]&!i[13]&i[11]&!i[10]);

assign fpdest_single_u = (i[31]&!i[30]&!i[19]&!i[13]&i[12]&i[7]) | (i[31]&!i[30]
    &!i[13]&i[9]&i[8]&i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[9]&i[8]&i[7]
    &i[5]) | (i[31]&!i[30]&!i[20]&!i[13]&!i[11]&i[10]&i[5]) | (i[31]
    &!i[30]&!i[22]&!i[19]&!i[13]&i[12]&i[11]&!i[8]) | (i[31]&!i[30]&!i[19]
    &!i[13]&i[11]&!i[8]&i[5]) | (i[31]&i[24]&i[23]&!i[22]&!i[20]&i[19]
    &!i[9]&i[5]) | (i[31]&!i[30]&!i[20]&!i[19]&!i[13]&!i[12]&!i[10]&i[5]) | (
    i[31]&!i[30]&i[20]&!i[13]&i[11]&i[10]&i[5]) | (i[31]&i[30]&i[24]
    &!i[22]&!i[19]);

assign fp_rs1_single_u = (i[31]&!i[30]&!i[13]&!i[11]&i[9]&!i[8]&!i[7]&i[5]) | (
    i[31]&!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[7]&!i[6]) | (i[31]&!i[30]
    &i[20]&!i[13]&i[11]&i[9]&!i[8]&i[5]) | (i[31]&!i[30]&i[20]&!i[13]
    &i[10]&!i[9]&i[8]&i[5]) | (i[31]&!i[30]&!i[20]&!i[19]&!i[13]&!i[12]
    &i[11]&i[5]) | (i[31]&!i[30]&!i[19]&!i[13]&i[11]&i[10]&i[7]&!i[6]
    &i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[7]&i[6]&i[5]) | (i[31]&!i[30]
    &!i[13]&!i[12]&i[9]&!i[8]&!i[6]&i[5]) | (i[31]&i[30]&i[24]&!i[21]
    &!i[19]);

assign fp_rs2_single_u = (i[31]&!i[30]&!i[22]&!i[13]&i[12]&i[11]&!i[6]) | (
    i[31]&!i[30]&!i[13]&i[9]&!i[8]&!i[7]&i[6]&i[5]) | (i[31]&!i[30]&!i[13]
    &!i[11]&i[10]&!i[8]&i[7]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&!i[11]
    &i[10]&i[9]&i[8]&!i[7]&!i[6]) | (i[31]&!i[30]&!i[13]&i[11]&!i[9]&i[7]
    &i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[8]&i[6]&i[5]) | (i[31]&!i[30]
    &!i[13]&i[11]&i[8]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[11]&i[9]&!i[7]
    &i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[10]&i[5]) | (i[31]&i[24]&i[23]
    &!i[22]&i[21]&!i[20]&i[5]) | (i[31]&i[30]&i[24]&!i[22]&!i[19]) | (
    i[31]&i[30]&!i[25]&i[24]&!i[22]&i[21]&!i[20]);

assign fsrsync_u = (i[31]&!i[30]&!i[13]&!i[11]&i[9]&i[8]&i[7]&!i[5]) | (i[31]
    &i[30]&i[24]&!i[22]&!i[20]&i[19]);

assign callclass_u = (i[24]&i[23]&i[22]&!i[21]&!i[20]) | (!i[31]&i[30]);

assign specbr_u = (!i[31]&!i[30]&i[22]) | (!i[31]&!i[30]&i[23]);

assign specfp_u = (i[31]&!i[30]&!i[13]&i[12]&i[5]) | (i[31]&!i[30]&!i[13]&i[10]
    &i[9]) | (i[31]&!i[30]&!i[22]&!i[13]&i[11]) | (i[31]&!i[30]&i[24]
    &i[23]&!i[22]&i[21]&!i[20]);

assign tcc_u = (!i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]);

assign done_u = (!i[30]&!i[25]&i[24]&i[23]&i[22]&i[21]&i[20]);

assign retry_u = (!i[30]&i[25]&i[24]&i[23]&i[22]&i[21]&i[20]);

assign load_u = (i[31]&i[24]&!i[23]&i[22]&i[20]&!i[19]&i[16]) | (i[31]&i[24]
    &!i[23]&i[22]&!i[21]&!i[17]&i[16]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]
    &!i[20]&i[19]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[19]&!i[16]) | (
    i[31]&i[30]&i[24]&i[22]) | (i[31]&i[30]&i[22]&i[19]) | (i[31]&i[30]
    &!i[21]);

assign store_u = (i[31]&!i[30]&!i[26]&i[24]&i[23]&!i[22]&!i[21]&!i[19]) | (
    i[31]&i[30]&i[21]&!i[19]) | (i[31]&!i[30]&!i[28]&i[24]&i[23]&!i[22]
    &!i[21]&!i[19]) | (i[31]&!i[30]&i[24]&i[23]&!i[22]&!i[21]&i[20]) | (
    i[31]&i[30]&!i[22]&i[21]) | (i[31]&i[30]&!i[24]&i[21]);

assign prefetch_u = (i[31]&i[30]&i[24]&i[22]&i[19]);

assign flush_u = (!i[30]&i[24]&i[23]&i[22]&i[20]&i[19]);

assign memstbar_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[1]) | (i[31]&i[24]&!i[23]
    &i[22]&!i[21]&i[5]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[6]);

assign sr_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[20]&!i[19]&!i[17]) | (i[31]
    &i[24]&!i[23]&i[22]&!i[21]&!i[20]&!i[19]&!i[16]) | (i[31]&!i[30]
    &!i[28]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&!i[19]) | (i[31]&!i[30]
    &!i[27]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&!i[19]);

assign pr_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[20]&!i[19]) | (i[31]&i[24]
    &i[23]&!i[22]&!i[21]&i[20]&!i[19]);

assign hpr_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[20]&i[19]) | (i[31]&!i[30]
    &i[24]&i[23]&!i[22]&i[20]&i[19]);

assign ldstub_u = (i[31]&i[30]&!i[24]&i[22]&i[21]&!i[20]);

assign alt_u = (i[31]&i[30]&i[23]&!i[13]);

assign alti_u = (i[31]&i[30]&i[23]&i[13]);

assign swap_u = (i[31]&i[30]&i[22]&i[21]&i[20]&i[19]);

assign lsize_u[1] = (i[22]&i[21]&!i[19]) | (i[24]) | (i[20]&i[19]) | (!i[20]
    &!i[19]);

assign lsize_u[0] = (i[20]&!i[19]) | (!i[30]) | (i[25]&i[24]&i[19]) | (!i[22]
    &i[20]) | (!i[21]&i[20]);

assign killfgu_u = (i[31]&!i[30]&!i[13]&!i[10]&i[9]&i[8]);

assign exu_src_u = (i[31]&i[24]&!i[23]&i[22]&i[21]&i[20]&!i[19]) | (i[31]&!i[30]
    &i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]) | (!i[30]&i[24]&i[23]&i[22]
    &i[21]&!i[20]) | (i[31]&!i[30]&i[22]&i[21]&!i[20]&i[19]) | (i[31]
    &!i[30]&!i[24]&i[22]&i[20]) | (i[31]&!i[30]&!i[24]&i[22]&i[19]);

assign save_restore_u = (!i[30]&i[24]&i[23]&i[22]&i[21]&!i[20]);

assign sir_u = (i[31]&!i[30]&i[28]&i[26]&i[24]&i[23]&!i[22]&!i[21]&!i[20]);

assign stdfa_u = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]);

assign fpdisable_u = (i[31]&!i[30]&!i[13]&i[12]&i[5]) | (!i[30]&i[24]&!i[23]
    &i[22]&!i[21]&!i[20]&!i[19]&i[18]&!i[16]&i[15]) | (!i[30]&i[29]&!i[27]
    &i[26]&i[24]&i[23]&!i[22]&!i[20]) | (i[31]&!i[30]&!i[13]&i[9]&i[8]) | (
    i[31]&i[24]&!i[22]&!i[13]&i[11]) | (i[31]&i[24]&!i[22]&!i[13]&i[10]) | (
    !i[30]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]&!i[18]) | (!i[30]&i[24]
    &i[23]&!i[22]&i[21]&!i[20]) | (i[31]&i[30]&i[24]&!i[22]) | (!i[31]
    &!i[30]&i[24]&i[22]) | (!i[31]&!i[30]&i[24]&i[23]);

assign wrtick_u = (i[31]&!i[30]&i[28]&!i[25]&i[24]&i[23]&!i[22]&!i[21]&!i[20]) | (
    i[31]&!i[30]&!i[29]&i[27]&!i[26]&i[24]&i[23]&!i[22]&!i[21]&!i[20]
    &!i[19]);

// end autogeneration


// force decode to zeroes when the instruction is invalid
 assign kill_decode_d = illegal_d | ded_perr_d | ded_ferr_d;

 assign dcd_priv_d              = priv_u & ~kill_decode_d;
 assign dcd_fsrc_rs1_d		= fsrc_rs1_u & ~kill_decode_d;		
 assign dcd_fsrc_rs2_d		= fsrc_rs2_u & ~kill_decode_d;
 assign dcd_fpdest_single_d	= fpdest_single_u & ~kill_decode_d;
 assign dcd_fp_rs1_single_d	= fp_rs1_single_u & ~kill_decode_d;
 assign dcd_fp_rs2_single_d	= fp_rs2_single_u & ~kill_decode_d;
 assign dcd_fsrsync_d		= fsrsync_u & ~kill_decode_d;
 assign dcd_callclass_d		= callclass_u & ~kill_decode_d;
 assign dcd_specbr_d		= specbr_u & ~kill_decode_d;
 assign dcd_specfp_d		= specfp_u & ~kill_decode_d;
 assign dcd_tcc_d		= tcc_u & ~kill_decode_d;
 assign dcd_done_d		= done_u & ~kill_decode_d;
 assign dcd_retry_d		= retry_u & ~kill_decode_d;
 assign dcd_load_d              = load_u & ~kill_decode_d;         
 assign dcd_store_d             = store_u & ~kill_decode_d;        
 assign dcd_lsdouble_d          = lsdouble_u & ~kill_decode_d;    
 assign dcd_prefetch_d          = prefetch_u & ~kill_decode_d;     
 assign dcd_flush_d             = flush_u & ~kill_decode_d;        
 assign dcd_memstbar_d          = memstbar_u & ~kill_decode_d;     
 assign dcd_sr_d                = sr_u & ~kill_decode_d;           
 assign dcd_pr_d                = pr_u & ~kill_decode_d;           
 assign dcd_hpr_d               = hpr_u & ~kill_decode_d;          
 assign dcd_casa_d              = casa_u & ~kill_decode_d;         
 assign dcd_ldstub_d            = ldstub_u & ~kill_decode_d;       
 assign dcd_alt_d               = alt_u & ~kill_decode_d;          
 assign dcd_alti_d              = alti_u & ~kill_decode_d;         
 assign dcd_swap_d              = swap_u & ~kill_decode_d;         
 assign dcd_lsize_d[1:0]        = lsize_u[1:0] & {2{~kill_decode_d}};   
 assign dcd_killfgu_d           = killfgu_u & ~kill_decode_d;      
 assign dcd_exu_src_d           = exu_src_u & ~kill_decode_d;      
 assign dcd_save_restore_d 	= save_restore_u & ~kill_decode_d; 
 assign dcd_sir_d               = sir_u & ~kill_decode_d;          
 assign dcd_stdfa_d             = stdfa_u & ~kill_decode_d;        
 assign dcd_fpdisable_d         = fpdisable_u & ~kill_decode_d;    
 assign dcd_wrtick_d            = wrtick_u & ~kill_decode_d;       


assign dcd_sethi_d =  ~i[31] & ~i[30] & i[24] & ~i[23] & ~i[22] & i[21:0]==22'h0003f0;

assign i[31:0] = dec_inst_d[31:0];

// all illegals are mapped to this before they are written into the icache
assign illegal_d = ~i[31] & ~i[30] & ~i[24] & ~i[23] & ~i[22];

assign dcd_lsu_sign_ext_d = i[22] & ~i[21];   // op3[3:2]==10

supply0 vss;
supply1 vdd;

endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module dec_dcd_ctl_spare_ctl_macro__flops_0__num_2;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dec_ded_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dec_ded_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  clken, 
  tlu_cerer_icdp, 
  del_test_sel_p, 
  del_twocycle_std_p, 
  del_twocycle_rs2_p, 
  del_default_sel_p, 
  del_test_addr_p, 
  ifu_buf0_inst0, 
  ifu_buf0_inst1, 
  ifu_buf0_inst2, 
  ifu_buf0_inst3, 
  ifu_buf0_excp0, 
  ifu_buf0_excp1, 
  ifu_buf0_excp2, 
  ifu_buf0_excp3, 
  del_noshift_d, 
  pku_raw_pick_p, 
  pku_isrc_rs1_p, 
  pku_isrc_rs2_p, 
  pku_isrc_rd_p, 
  exu_oddwin_b, 
  ded_oddwin_d, 
  dec_inst_d, 
  dec_inst_rs1_p, 
  dec_inst_rs2_p, 
  dec_inst_rs3_p, 
  dec_inst_rs1_vld_p, 
  dec_inst_rs2_vld_p, 
  dec_inst_rs3_vld_p, 
  ded_exc_d, 
  ded_perr_p, 
  ded_ferr_p, 
  ded_perr_d, 
  ded_ferr_d, 
  ded_legal_p, 
  scan_out);
wire l1clk;
wire spares_scanin;
wire spares_scanout;
wire icdf_perr_f_scanin;
wire icdf_perr_f_scanout;
wire icdp_perr_en;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire oddwinf_scanin;
wire oddwinf_scanout;
wire [3:0] oddwin;
wire [2:0] xor0;
wire [2:0] xor1;
wire [2:0] xor2;
wire [2:0] xor3;
wire [3:0] window_in;
wire [2:0] xor_d;
wire windowf_scanin;
wire windowf_scanout;
wire twocyclef_scanin;
wire twocyclef_scanout;
wire [4:0] inst_rs2_d;
wire [4:1] inst_rs3_d;
wire [2:0] isrc_in;
wire [32:0] decode_mux;
wire [2:0] isrc0_in;
wire [2:0] isrc1_in;
wire [2:0] isrc2_in;
wire [2:0] isrc3_in;
wire [2:0] isrc_d;
wire isrcf_scanin;
wire isrcf_scanout;
wire [4:0] exc_in;
wire excf_scanin;
wire excf_scanout;
wire decodef_scanin;
wire decodef_scanout;
wire parityerrf_scanin;
wire parityerrf_scanout;
wire [3:0] ifetch_err_p;
wire ifetcherrf_scanin;
wire ifetcherrf_scanout;
wire illegal0_p;
wire illegal1_p;
wire illegal2_p;
wire illegal3_p;
wire legal_d;
wire legalf_scanin;
wire legalf_scanout;


input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;
input tcu_scan_en;

input clken;

input tlu_cerer_icdp;		// enable for icdp perr (0 then mask it)

input del_test_sel_p;		// mux selects for IRF read port rs3
input del_twocycle_std_p;
input del_twocycle_rs2_p;
input del_default_sel_p;


input [4:0] del_test_addr_p;	// address to read for exu test access

input [32:0] ifu_buf0_inst0;		// instructions for each of the threads at p stage
input [32:0] ifu_buf0_inst1;
input [32:0] ifu_buf0_inst2;
input [32:0] ifu_buf0_inst3;

input [4:0] ifu_buf0_excp0;		// exception info for each of the threads at p stage
input [4:0] ifu_buf0_excp1;
input [4:0] ifu_buf0_excp2;
input [4:0] ifu_buf0_excp3;

input del_noshift_d;			// dont shift anything into decode0 stage
input [3:0]  pku_raw_pick_p;     	// raw pick signals to ifu to mux pc addresses


input [3:0] pku_isrc_rs1_p;		// has rs1 source
input [3:0] pku_isrc_rs2_p;		// has rs2 source
input [3:0] pku_isrc_rd_p;		// has rd source

input [3:0] exu_oddwin_b;		// whether window for current thread is odd or not

output ded_oddwin_d;			// window is odd for decode0

output [32:0] dec_inst_d;

output [4:0] dec_inst_rs1_p;
output [4:0] dec_inst_rs2_p;
output [4:0] dec_inst_rs3_p;
output dec_inst_rs1_vld_p;
output dec_inst_rs2_vld_p;
output dec_inst_rs3_vld_p;


output [4:0] ded_exc_d;

output ded_perr_p;		// inst parity error at p stage; to del to squash predecodes
output ded_ferr_p;		// inst ifetch error at p stage; to del to squash predecodes
	   
output ded_perr_d;		// inst parity error at d stage; to dcd to squash main decode
output ded_ferr_d;		// inst ifetch error at d stage; to dcd to squash main decode

output ded_legal_p;		// illegal instruction at p stage

output scan_out;


dec_ded_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (clken),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

dec_ded_ctl_spare_ctl_macro__num_2 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

dec_ded_ctl_msff_ctl_macro__width_1 icdf_perr_f  (
 .scan_in(icdf_perr_f_scanin),
 .scan_out(icdf_perr_f_scanout),
 .l1clk(l1clk),
 .din  (tlu_cerer_icdp),
 .dout (icdp_perr_en),
  .siclk(siclk),
  .soclk(soclk)
);


// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
assign se = tcu_scan_en;
// end scan

// 0in value -var pku_raw_pick_p[3:0] -val 0 1 2 4 8


dec_ded_ctl_msff_ctl_macro__width_4 oddwinf  (
 .scan_in(oddwinf_scanin),
 .scan_out(oddwinf_scanout),
 .din(exu_oddwin_b[3:0]),
 .dout(oddwin[3:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// generate correct pointers for rd, rs1 and rs2 for each thread

assign xor0[2:0] = {ifu_buf0_inst0[29],ifu_buf0_inst0[18],ifu_buf0_inst0[4]} ^ ({3{oddwin[0]}} &  {ifu_buf0_inst0[28],ifu_buf0_inst0[17],ifu_buf0_inst0[3]});

assign xor1[2:0] = {ifu_buf0_inst1[29],ifu_buf0_inst1[18],ifu_buf0_inst1[4]} ^ ({3{oddwin[1]}} &  {ifu_buf0_inst1[28],ifu_buf0_inst1[17],ifu_buf0_inst1[3]});

assign xor2[2:0] = {ifu_buf0_inst2[29],ifu_buf0_inst2[18],ifu_buf0_inst2[4]} ^ ({3{oddwin[2]}} &  {ifu_buf0_inst2[28],ifu_buf0_inst2[17],ifu_buf0_inst2[3]});

assign xor3[2:0] = {ifu_buf0_inst3[29],ifu_buf0_inst3[18],ifu_buf0_inst3[4]} ^ ({3{oddwin[3]}} &  {ifu_buf0_inst3[28],ifu_buf0_inst3[17],ifu_buf0_inst3[3]});


assign window_in[3:0] =    ({4{del_noshift_d}} &                      {ded_oddwin_d,xor_d[2:0]}) |
			   ({4{~del_noshift_d & pku_raw_pick_p[0]}} & {oddwin[0],xor0[2:0]}) |
			   ({4{~del_noshift_d & pku_raw_pick_p[1]}} & {oddwin[1],xor1[2:0]}) |
			   ({4{~del_noshift_d & pku_raw_pick_p[2]}} & {oddwin[2],xor2[2:0]}) |
			   ({4{~del_noshift_d & pku_raw_pick_p[3]}} & {oddwin[3],xor3[2:0]});


dec_ded_ctl_msff_ctl_macro__width_4 windowf  (
 .scan_in(windowf_scanin),
 .scan_out(windowf_scanout),
 .din(window_in[3:0]),
 .dout({ded_oddwin_d,xor_d[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// twocycle operations use the rs3 port to the irf for the second read operation

dec_ded_ctl_msff_ctl_macro__width_9 twocyclef  (
 .scan_in(twocyclef_scanin),
 .scan_out(twocyclef_scanout),
 .din({dec_inst_rs2_p[4:0],dec_inst_rs3_p[4:1]}),
 .dout({inst_rs2_d[4:0],inst_rs3_d[4:1]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign {dec_inst_rs3_vld_p,dec_inst_rs3_p[4:0]} = ({6{del_test_sel_p}} & {1'b1,del_test_addr_p[4:0]}) |
						  ({6{del_twocycle_std_p}} & {1'b1,inst_rs3_d[4:1],1'b1}) |
					          ({6{del_twocycle_rs2_p}} & {1'b1,inst_rs2_d[4:0]}) |
						  ({6{del_default_sel_p}}  & {isrc_in[2],window_in[2],decode_mux[28:25]});


assign dec_inst_rs1_vld_p = isrc_in[1];
assign dec_inst_rs2_vld_p = isrc_in[0];

assign dec_inst_rs1_p[4:0] = {window_in[1],decode_mux[17:14]};
assign dec_inst_rs2_p[4:0] = {window_in[0],decode_mux[3:0]};


assign isrc0_in[2:0] = { pku_isrc_rd_p[0],pku_isrc_rs1_p[0],pku_isrc_rs2_p[0] };

assign isrc1_in[2:0] = { pku_isrc_rd_p[1],pku_isrc_rs1_p[1],pku_isrc_rs2_p[1] };

assign isrc2_in[2:0] = { pku_isrc_rd_p[2],pku_isrc_rs1_p[2],pku_isrc_rs2_p[2] };

assign isrc3_in[2:0] = { pku_isrc_rd_p[3],pku_isrc_rs1_p[3],pku_isrc_rs2_p[3] };


assign isrc_in[2:0] =      ({3{del_noshift_d}} & isrc_d[2:0]) |
			   ({3{~del_noshift_d & pku_raw_pick_p[0]}} & isrc0_in[2:0]) |
			   ({3{~del_noshift_d & pku_raw_pick_p[1]}} & isrc1_in[2:0]) |
			   ({3{~del_noshift_d & pku_raw_pick_p[2]}} & isrc2_in[2:0]) |
			   ({3{~del_noshift_d & pku_raw_pick_p[3]}} & isrc3_in[2:0]);


dec_ded_ctl_msff_ctl_macro__width_3 isrcf  (
 .scan_in(isrcf_scanin),
 .scan_out(isrcf_scanout),
 .din(isrc_in[2:0]),
 .dout(isrc_d[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign exc_in[4:0] =       ({5{del_noshift_d}} & ded_exc_d[4:0]) |
			   ({5{~del_noshift_d & pku_raw_pick_p[0]}} & ifu_buf0_excp0[4:0]) |
			   ({5{~del_noshift_d & pku_raw_pick_p[1]}} & ifu_buf0_excp1[4:0]) |
			   ({5{~del_noshift_d & pku_raw_pick_p[2]}} & ifu_buf0_excp2[4:0]) |
			   ({5{~del_noshift_d & pku_raw_pick_p[3]}} & ifu_buf0_excp3[4:0]);

dec_ded_ctl_msff_ctl_macro__width_5 excf  (
 .scan_in(excf_scanin),
 .scan_out(excf_scanout),
 .din(exc_in[4:0]),
 .dout(ded_exc_d[4:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign decode_mux[32:0] = ({33{del_noshift_d}} & dec_inst_d[32:0]) |
			   ({33{~del_noshift_d & pku_raw_pick_p[0]}} & ifu_buf0_inst0[32:0]) |
			   ({33{~del_noshift_d & pku_raw_pick_p[1]}} & ifu_buf0_inst1[32:0]) |
			   ({33{~del_noshift_d & pku_raw_pick_p[2]}} & ifu_buf0_inst2[32:0]) |
			   ({33{~del_noshift_d & pku_raw_pick_p[3]}} & ifu_buf0_inst3[32:0]);

dec_ded_ctl_msff_ctl_macro__width_33 decodef  (
 .scan_in(decodef_scanin),
 .scan_out(decodef_scanout),
 .din(decode_mux[32:0]),
 .dout(dec_inst_d[32:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// its only a parity error if its enabled
assign ded_perr_p =   ( del_noshift_d & ded_perr_d) |
			   (~del_noshift_d & pku_raw_pick_p[0] & icdp_perr_en & (ifu_buf0_inst0[32] ^ (^ifu_buf0_inst0[31:0]))) |
			   (~del_noshift_d & pku_raw_pick_p[1] & icdp_perr_en & (ifu_buf0_inst1[32] ^ (^ifu_buf0_inst1[31:0]))) |
			   (~del_noshift_d & pku_raw_pick_p[2] & icdp_perr_en & (ifu_buf0_inst2[32] ^ (^ifu_buf0_inst2[31:0]))) |
			   (~del_noshift_d & pku_raw_pick_p[3] & icdp_perr_en & (ifu_buf0_inst3[32] ^ (^ifu_buf0_inst3[31:0])));

dec_ded_ctl_msff_ctl_macro__width_1 parityerrf  (
 .scan_in(parityerrf_scanin),
 .scan_out(parityerrf_scanout),
 .din(ded_perr_p),
 .dout(ded_perr_d),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ifetch_err_p[0] = 	(ifu_buf0_excp0[4:0] == 5'b00001) |
				(ifu_buf0_excp0[4:0] == 5'b00010) |
				(ifu_buf0_excp0[4:0] == 5'b00011) |
				(ifu_buf0_excp0[4:0] == 5'b00100) |
				(ifu_buf0_excp0[4:0] == 5'b00111) |
				(ifu_buf0_excp0[4:0] == 5'b11111) |
				(ifu_buf0_excp0[4:0] == 5'b01001) |
				(ifu_buf0_excp0[4:0] == 5'b01010) |
				(ifu_buf0_excp0[4:0] == 5'b01011) |
				(ifu_buf0_excp0[4:0] == 5'b01100) |
				(ifu_buf0_excp0[4:0] == 5'b01101) |
				(ifu_buf0_excp0[4:0] == 5'b01111) |
				(ifu_buf0_excp0[4:0] == 5'b10000) |
				(ifu_buf0_excp0[4:0] == 5'b10001) |
				(ifu_buf0_excp0[4:0] == 5'b10011) |
				(ifu_buf0_excp0[4:0] == 5'b10111) |
				(ifu_buf0_excp0[4:0] == 5'b11000);

assign ifetch_err_p[1] = 	(ifu_buf0_excp1[4:0] == 5'b00001) |
				(ifu_buf0_excp1[4:0] == 5'b00010) |
				(ifu_buf0_excp1[4:0] == 5'b00011) |
				(ifu_buf0_excp1[4:0] == 5'b00100) |
				(ifu_buf0_excp1[4:0] == 5'b00111) |
				(ifu_buf0_excp1[4:0] == 5'b11111) |
				(ifu_buf0_excp1[4:0] == 5'b01001) |
				(ifu_buf0_excp1[4:0] == 5'b01010) |
				(ifu_buf0_excp1[4:0] == 5'b01011) |
				(ifu_buf0_excp1[4:0] == 5'b01100) |
				(ifu_buf0_excp1[4:0] == 5'b01101) |
				(ifu_buf0_excp1[4:0] == 5'b01111) |
				(ifu_buf0_excp1[4:0] == 5'b10000) |
				(ifu_buf0_excp1[4:0] == 5'b10001) |
				(ifu_buf0_excp1[4:0] == 5'b10011) |
				(ifu_buf0_excp1[4:0] == 5'b10111) |
				(ifu_buf0_excp1[4:0] == 5'b11000);

assign ifetch_err_p[2] = 	(ifu_buf0_excp2[4:0] == 5'b00001) |
				(ifu_buf0_excp2[4:0] == 5'b00010) |
				(ifu_buf0_excp2[4:0] == 5'b00011) |
				(ifu_buf0_excp2[4:0] == 5'b00100) |
				(ifu_buf0_excp2[4:0] == 5'b00111) |
				(ifu_buf0_excp2[4:0] == 5'b11111) |
				(ifu_buf0_excp2[4:0] == 5'b01001) |
				(ifu_buf0_excp2[4:0] == 5'b01010) |
				(ifu_buf0_excp2[4:0] == 5'b01011) |
				(ifu_buf0_excp2[4:0] == 5'b01100) |
				(ifu_buf0_excp2[4:0] == 5'b01101) |
				(ifu_buf0_excp2[4:0] == 5'b01111) |
				(ifu_buf0_excp2[4:0] == 5'b10000) |
				(ifu_buf0_excp2[4:0] == 5'b10001) |
				(ifu_buf0_excp2[4:0] == 5'b10011) |
				(ifu_buf0_excp2[4:0] == 5'b10111) |
				(ifu_buf0_excp2[4:0] == 5'b11000);

assign ifetch_err_p[3] = 	(ifu_buf0_excp3[4:0] == 5'b00001) |
				(ifu_buf0_excp3[4:0] == 5'b00010) |
				(ifu_buf0_excp3[4:0] == 5'b00011) |
				(ifu_buf0_excp3[4:0] == 5'b00100) |
				(ifu_buf0_excp3[4:0] == 5'b00111) |
				(ifu_buf0_excp3[4:0] == 5'b11111) |
				(ifu_buf0_excp3[4:0] == 5'b01001) |
				(ifu_buf0_excp3[4:0] == 5'b01010) |
				(ifu_buf0_excp3[4:0] == 5'b01011) |
				(ifu_buf0_excp3[4:0] == 5'b01100) |
				(ifu_buf0_excp3[4:0] == 5'b01101) |
				(ifu_buf0_excp3[4:0] == 5'b01111) |
				(ifu_buf0_excp3[4:0] == 5'b10000) |
				(ifu_buf0_excp3[4:0] == 5'b10001) |
				(ifu_buf0_excp3[4:0] == 5'b10011) |
				(ifu_buf0_excp3[4:0] == 5'b10111) |
				(ifu_buf0_excp3[4:0] == 5'b11000);

assign ded_ferr_p =   ( del_noshift_d & ded_ferr_d) |
			    (~del_noshift_d & pku_raw_pick_p[0] & ifetch_err_p[0]) |
			    (~del_noshift_d & pku_raw_pick_p[1] & ifetch_err_p[1] ) |
			    (~del_noshift_d & pku_raw_pick_p[2] & ifetch_err_p[2] ) |
			    (~del_noshift_d & pku_raw_pick_p[3] & ifetch_err_p[3] );

dec_ded_ctl_msff_ctl_macro__width_1 ifetcherrf  (
 .scan_in(ifetcherrf_scanin),
 .scan_out(ifetcherrf_scanout),
 .din(ded_ferr_p),
 .dout(ded_ferr_d),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign illegal0_p = ~ifu_buf0_inst0[31] & ~ifu_buf0_inst0[30] & ~ifu_buf0_inst0[24] & ~ifu_buf0_inst0[23] & ~ifu_buf0_inst0[22];
assign illegal1_p = ~ifu_buf0_inst1[31] & ~ifu_buf0_inst1[30] & ~ifu_buf0_inst1[24] & ~ifu_buf0_inst1[23] & ~ifu_buf0_inst1[22];
assign illegal2_p = ~ifu_buf0_inst2[31] & ~ifu_buf0_inst2[30] & ~ifu_buf0_inst2[24] & ~ifu_buf0_inst2[23] & ~ifu_buf0_inst2[22];
assign illegal3_p = ~ifu_buf0_inst3[31] & ~ifu_buf0_inst3[30] & ~ifu_buf0_inst3[24] & ~ifu_buf0_inst3[23] & ~ifu_buf0_inst3[22];


assign ded_legal_p =       ( del_noshift_d & legal_d) |
			   (~del_noshift_d & pku_raw_pick_p[0] & ~illegal0_p) |
			   (~del_noshift_d & pku_raw_pick_p[1] & ~illegal1_p) |
			   (~del_noshift_d & pku_raw_pick_p[2] & ~illegal2_p) |
			   (~del_noshift_d & pku_raw_pick_p[3] & ~illegal3_p);

dec_ded_ctl_msff_ctl_macro__width_1 legalf  (
 .scan_in(legalf_scanin),
 .scan_out(legalf_scanout),
 .din(ded_legal_p),
 .dout(legal_d),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// fixscan start:
assign spares_scanin             = scan_in                  ;
assign icdf_perr_f_scanin        = spares_scanout           ;
assign oddwinf_scanin            = icdf_perr_f_scanout      ;
assign windowf_scanin            = oddwinf_scanout          ;
assign twocyclef_scanin          = windowf_scanout          ;
assign isrcf_scanin              = twocyclef_scanout        ;
assign excf_scanin               = isrcf_scanout            ;
assign decodef_scanin            = excf_scanout             ;
assign parityerrf_scanin         = decodef_scanout          ;
assign ifetcherrf_scanin         = parityerrf_scanout       ;
assign legalf_scanin             = ifetcherrf_scanout       ;
assign scan_out                  = legalf_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module dec_ded_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module dec_ded_ctl_spare_ctl_macro__num_2 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));
assign scan_out = so_1;


endmodule


// any PARAMS parms go into naming of macro

module dec_ded_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_ded_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_ded_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_ded_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_ded_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_ded_ctl_msff_ctl_macro__width_33 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [32:0] fdin;
wire [31:0] so;

  input [32:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [32:0] dout;
  output scan_out;
assign fdin[32:0] = din[32:0];


dff #(33)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[32:0]),
.si({scan_in,so[31:0]}),
.so({so[31:0],scan_out}),
.q(dout[32:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dec_del_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dec_del_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  lsu_dec_pmen, 
  lsu_exu_pmen, 
  spc_core_running_status, 
  power_throttle, 
  lb_lbist_running, 
  pku_idest_p, 
  pku_fdest_p, 
  pku_fsrc_rd_p, 
  pku_lsu_p, 
  pku_fgu_p, 
  pku_pdist_p, 
  pku_twocycle_p, 
  pku_inst_cnt_brtaken00, 
  pku_inst_cnt_brtaken01, 
  pku_inst_cnt_brtaken02, 
  pku_inst_cnt_brtaken03, 
  pku_inst_cnt_brtaken04, 
  pku_inst_cnt_brtaken05, 
  pku_inst_cnt_brtaken06, 
  pku_inst_cnt_brtaken07, 
  pku_inst_cnt_brtaken10, 
  pku_inst_cnt_brtaken11, 
  pku_inst_cnt_brtaken12, 
  pku_inst_cnt_brtaken13, 
  pku_inst_cnt_brtaken14, 
  pku_inst_cnt_brtaken15, 
  pku_inst_cnt_brtaken16, 
  pku_inst_cnt_brtaken17, 
  exu_test_tid0, 
  exu_test_addr0, 
  exu_test_valid0, 
  exu_test_tid1, 
  exu_test_addr1, 
  exu_test_valid1, 
  ded_exc0_d, 
  ded_exc1_d, 
  tlu_dec_pstate_pef, 
  fgu_fprs_fef, 
  tlu_dec_hpstate_hpriv, 
  tlu_dec_pstate_priv, 
  dcd_wrtick_d, 
  lsu_cpq_stall, 
  dcd_callclass_d, 
  dcd_tcc_d, 
  dcd_specbr_d, 
  dcd_specfp_d, 
  dcd_exu_src_d, 
  dcd_killfgu_d, 
  dcd_sir_d, 
  dcd_stdfa_d, 
  pku_valid_e, 
  pku_annul_ds_dcti_brtaken0_e, 
  pku_annul_ds_dcti_brtaken1_e, 
  exu0_window_block, 
  exu1_window_block, 
  tlu_window_block, 
  fgu_idiv_stall, 
  fgu_fdiv_stall, 
  fgu_ecc_asi_stall, 
  dcd_fpdisable_d, 
  dcd_lsize0_d, 
  dcd_lsize1_d, 
  dcd_lsu_sign_ext_d, 
  dcd_load_d, 
  dcd_store_d, 
  dcd_sethi_d, 
  dcd_lsdouble_d, 
  dcd_prefetch_d, 
  dcd_flush_d, 
  dcd_memstbar_d, 
  dcd_pr_d, 
  dcd_priv_d, 
  dcd_hpr_d, 
  dcd_sr_d, 
  dcd_casa_d, 
  dcd_ldstub_d, 
  dcd_alt_d, 
  dcd_alti_d, 
  dcd_swap_d, 
  dcd_fsrc_rs1_d, 
  dcd_fsrc_rs2_d, 
  dcd_fpdest_single_d, 
  dcd_fp_rs1_single_d, 
  dcd_fp_rs2_single_d, 
  dcd_fsrsync_d, 
  dcd_done_d, 
  dcd_retry_d, 
  dec_inst0_rs1_d, 
  dec_inst0_rs2_d, 
  dec_inst0_raw_rd_d, 
  dec_inst1_rs1_d, 
  dec_inst1_rs2_d, 
  dec_inst1_raw_rd_d, 
  dcd_save_restore_d, 
  ded_oddwin0_d, 
  ded_oddwin1_d, 
  ded_perr_p, 
  ded_ferr_p, 
  ded_legal_p, 
  dec_inst0_b31, 
  dec_inst1_b31, 
  dec_inst0_op3_d, 
  dec_inst1_op3_d, 
  dec_inst0_opf_d, 
  dec_inst1_opf_d, 
  pku_base_pick_p, 
  pku_raw_pick0_p, 
  pku_raw_pick1_p, 
  pku_ds_e, 
  pku_load_flush_w, 
  tlu_flush_ifu, 
  pku_flush_f1, 
  pku_flush_f2, 
  pku_flush_lm, 
  pku_flush_lb, 
  pku_flush_m, 
  pku_flush_b, 
  dec_br_taken_e1, 
  spu_mult_request, 
  lsu_block_store_stall, 
  lsu_block_store_rd, 
  lsu_block_store_tid, 
  tlu_dtlb_reload_stall, 
  tlu_pstate_am, 
  dec_valid0_d, 
  dec_valid1_d, 
  dec_decode0_d, 
  dec_decode1_d, 
  del_noshift0_d, 
  del_noshift1_d, 
  dec_inst0_rd_d, 
  dec_inst1_rd_d, 
  dec_tid0_d, 
  dec_tid1_d, 
  dec_tid0_p, 
  dec_tid1_p, 
  dec_valid_e, 
  dec_pmu_valid_e, 
  dec_fgu_valid_e, 
  dec_frf_r1_addr_d, 
  dec_frf_r2_addr_d, 
  dec_frf_r2_addr_e, 
  dec_frf_r1_vld_d, 
  dec_frf_r2_vld_d, 
  dec_frf_r1_32b_d, 
  dec_frf_r2_32b_d, 
  dec_frf_r1_odd32b_d, 
  dec_frf_r2_odd32b_d, 
  dec_frf_w_addr_d, 
  dec_frf_w_vld_d, 
  dec_frf_w_32b_d, 
  dec_frf_w_odd32b_d, 
  dec_spu_grant_d, 
  dec_spu_grant_fgu_d, 
  dec_exu_src_vld_d, 
  dec_irf_w_addr_d, 
  dec_frf_store_d, 
  dec_fsr_store_d, 
  dec_fgu_op3_d, 
  dec_fgu_opf_d, 
  dec_fgu_decode_d, 
  dec_fgu_tid_d, 
  dec_flush_f1, 
  dec_flush_f2, 
  dec_flush_lm, 
  dec_flush_lb, 
  dec_flush_m, 
  dec_flush_b, 
  dec_block_store_b, 
  dec_exc0_m, 
  dec_exc1_m, 
  dec_inst0_cnt, 
  dec_inst1_cnt, 
  dec_tid0_m, 
  dec_tid1_m, 
  dec_inst_valid_m, 
  dec_lsu_inst_m, 
  dec_fgu_inst_m, 
  dec_cti_inst_m, 
  dec_illegal_inst_m, 
  dec_icache_perr_m, 
  dec_priv_exc_m, 
  dec_hpriv_exc_m, 
  dec_fpdisable_exc_m, 
  dec_br_taken_m, 
  dec_done_inst_m, 
  dec_retry_inst_m, 
  dec_sir_inst_m, 
  dec_ds_m, 
  dec_annul_ds_m, 
  dec_fgu_sel_e, 
  dec_fgu_sel_m, 
  dec_lsu_sel0_e, 
  dec_lsu_sel1_e, 
  dec_rs1_addr0_e, 
  dec_rs1_addr1_e, 
  dec_lsu_sel0_upper_e, 
  dec_lsu_sel1_upper_e, 
  dec_lsu_sel0_lower_e, 
  dec_lsu_sel1_lower_e, 
  dec_rs1_addr0_upper_e, 
  dec_rs1_addr1_upper_e, 
  del_pick_d, 
  dec_ld_inst_e, 
  dec_st_inst_e, 
  dec_fsr_ldst_e, 
  dec_fpldst_inst_e, 
  dec_ldst_dbl_e, 
  dec_pref_inst_e, 
  dec_flush_inst_e, 
  dec_memstbar_inst_e, 
  dec_sr_inst_e, 
  dec_pr_inst_e, 
  dec_hpr_inst_e, 
  dec_casa_inst_e, 
  dec_ldstub_inst_e, 
  dec_swap_inst_e, 
  dec_altspace_d, 
  dec_sign_ext_e, 
  dec_sraddr_e, 
  dec_imm_asi_vld_d, 
  dec_imm_asi_d, 
  dec_ldst_sz_e, 
  dec_ld_inst_d, 
  dec_lsu_tid0_d, 
  dec_lsu_tid1_d, 
  dec_lsu_tg_d, 
  dec_lsu_rd_e, 
  del_test0_sel_p, 
  del_twocycle0_std_p, 
  del_twocycle0_rs2_p, 
  del_default0_sel_p, 
  del_test1_sel_p, 
  del_twocycle1_std_p, 
  del_twocycle1_rs2_p, 
  del_default1_sel_p, 
  del_test_addr0_p, 
  del_test_addr1_p, 
  dec_instr0_type_d, 
  dec_instr1_type_d, 
  dec_exu_clken, 
  del_tg_clken, 
  scan_out, 
  dec_true_valid_e, 
  dec_load_flush_w, 
  dec_lsu_sel0_d, 
  dec_raw_pick_p, 
  dec_ierr_d, 
  dec_block_store_stall);
wire l1clk;
wire spares_scanin;
wire spares_scanout;
wire [1:0] pmu_valid_d;
wire [3:0] spare_5_0_lat_unused;
wire [1:0] pmu_valid_e;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire callinst0_d;
wire callinst1_d;
wire [6:0] pdecode0_in;
wire [6:0] pdecode1_in;
wire [6:0] pdecode2_in;
wire [6:0] pdecode3_in;
wire [6:0] pdec0_in;
wire [6:0] pdecode0_d;
wire pdecode0f_scanin;
wire pdecode0f_scanout;
wire idest0_d;
wire fdest0_d;
wire fsrc0_rd_d;
wire lsu0_d;
wire fgu0_d;
wire pdist0_d;
wire twocycle0_d;
wire [6:0] pdecode4_in;
wire [6:0] pdecode5_in;
wire [6:0] pdecode6_in;
wire [6:0] pdecode7_in;
wire [6:0] pdec1_in;
wire [6:0] pdecode1_d;
wire pdecode1f_scanin;
wire pdecode1f_scanout;
wire idest1_d;
wire fdest1_d;
wire fsrc1_rd_d;
wire lsu1_d;
wire fgu1_d;
wire pdist1_d;
wire twocycle1_d;
wire [7:0] final_pick_p;
wire shift0_d;
wire [3:0] raw_pick0_in;
wire [3:0] pick0_d;
wire [3:0] pick0_in;
wire pick0f_scanin;
wire pick0f_scanout;
wire shift1_d;
wire [3:0] raw_pick1_in;
wire [3:0] pick1_d;
wire [3:0] pick1_in;
wire pick1f_scanin;
wire pick1f_scanout;
wire privstatef_scanin;
wire privstatef_scanout;
wire [7:0] tlu_priv;
wire [7:0] tlu_hpriv;
wire fef_scanin;
wire fef_scanout;
wire [7:0] tlu_pef;
wire [7:0] fgu_fef;
wire [1:0] priv_d;
wire [1:0] hpriv_d;
wire [1:0] fpdis_d;
wire [1:0] inst0_cnt_brtaken0;
wire [1:0] inst0_cnt_brtaken1;
wire [1:0] inst1_cnt_brtaken0;
wire [1:0] inst1_cnt_brtaken1;
wire [1:0] br_taken_e;
wire [1:0] ifetch_err_e;
wire [1:0] inst0_cnt;
wire [1:0] inst1_cnt;
wire instcntf_scanin;
wire instcntf_scanout;
wire exutestf_scanin;
wire exutestf_scanout;
wire [1:0] ttid0_p;
wire [1:0] ttid1_p;
wire test_stall0_in;
wire test_stall1_in;
wire teststallf_scanin;
wire teststallf_scanout;
wire test_stall0;
wire test_stall1;
wire [1:0] twocycle_p;
wire twocycle0_sel_p;
wire twocycle1_sel_p;
wire [1:0] tid0_p;
wire [1:0] tid1_p;
wire [1:0] tid0_d;
wire [1:0] tid1_d;
wire [7:0] valid_d_in;
wire [7:0] valid_d;
wire val_df_scanin;
wire val_df_scanout;
wire valid0_d_in;
wire valid1_d_in;
wire valid_df_scanin;
wire valid_df_scanout;
wire valid0_d;
wire valid1_d;
wire dtlb_reloadf_scanin;
wire dtlb_reloadf_scanout;
wire [1:0] dtlb_reload;
wire dtlb_reload_stall;
wire block_store0f_scanin;
wire block_store0f_scanout;
wire pre_block_store_stall;
wire block_store_stall_in;
wire block_store_stall;
wire reset_block_store_stall;
wire block_storef_scanin;
wire block_storef_scanout;
wire [4:0] block_store_rd_in;
wire [4:0] block_store_rd;
wire block_store_rdhif_scanin;
wire block_store_rdhif_scanout;
wire block_store_rdlof_scanin;
wire block_store_rdlof_scanout;
wire [2:0] block_store_tid_in;
wire [2:0] block_store_tid;
wire block_store_tidf_scanin;
wire block_store_tidf_scanout;
wire block_store_stall0;
wire block_store_stall1;
wire cpq_stall_in;
wire cpq_stallf_scanin;
wire cpq_stallf_scanout;
wire cpq_stall;
wire fecc_stall_in;
wire fecc_stallf_scanin;
wire fecc_stallf_scanout;
wire fecc_stall;
wire block_resetf_scanin;
wire block_resetf_scanout;
wire [2:0] block_rst_cnt_in;
wire [2:0] block_rst_cnt;
wire block_store_e_scanin;
wire block_store_e_scanout;
wire block_store_stall_e;
wire [2:0] block_store_tid_e;
wire block_store_m_scanin;
wire block_store_m_scanout;
wire block_store_stall_m;
wire [2:0] block_store_tid_m;
wire block_store_b_scanin;
wire block_store_b_scanout;
wire block_store_stall_b;
wire [2:0] block_store_tid_b;
wire set_lfavor;
wire lsusel0_d;
wire reset_lfavor;
wire lfavor_in;
wire lfavor;
wire lfavorf_scanin;
wire lfavorf_scanout;
wire set_ffavor;
wire fgusel0_d;
wire reset_ffavor;
wire ffavor_in;
wire ffavor;
wire ffavorf_scanin;
wire ffavorf_scanout;
wire set_sffavor;
wire lsu_float_case;
wire reset_sffavor;
wire sffavor_in;
wire sffavor;
wire sffavorf_scanin;
wire sffavorf_scanout;
wire mult_request_in;
wire mult_request;
wire mulrequestf_scanin;
wire mulrequestf_scanout;
wire crypto_mult_case0;
wire crypto_mult_case1;
wire set_cmfavor;
wire reset_cmfavor;
wire cmfavor;
wire cmfavor_grant_d;
wire idiv_hole_d;
wire [1:0] idiv_stall_d;
wire pdistblock_d;
wire cmfavor_in;
wire cmfavorf_scanin;
wire cmfavorf_scanout;
wire [1:0] pdistblock_in;
wire pdistblockf_scanin;
wire pdistblockf_scanout;
wire [1:0] pdistblock;
wire pdistrdf_scanin;
wire pdistrdf_scanout;
wire [4:0] pdist_rd;
wire pdisttidf_scanin;
wire pdisttidf_scanout;
wire [2:0] pdist_tid;
wire twocycle0_d_in;
wire twocycle0_df_scanin;
wire twocycle0_df_scanout;
wire twocycle0_stall;
wire twocycle1_d_in;
wire twocycle1_df_scanin;
wire twocycle1_df_scanout;
wire twocycle1_stall;
wire int_hole0_in;
wire inthole0_df_scanin;
wire inthole0_df_scanout;
wire [2:0] int_hole0_stall;
wire int_hole1_in;
wire inthole1_df_scanin;
wire inthole1_df_scanout;
wire [2:0] int_hole1_stall;
wire divstall_df_scanin;
wire divstall_df_scanout;
wire fdiv_stall_d;
wire [1:0] window_stall_in;
wire windowstall_df_scanin;
wire windowstall_df_scanout;
wire [1:0] window_stall_d;
wire [1:0] exu_clken_in;
wire exu_clkenf_scanin;
wire exu_clkenf_scanout;
wire block0;
wire [7:0] power_stall;
wire block1;
wire legal_f_scanin;
wire legal_f_scanout;
wire [1:0] legal_d;
wire illegal0_d;
wire [1:0] ifetch_err_d;
wire illegal1_d;
wire [1:0] perr_d;
wire [1:0] illegal_d;
wire illegal_f_scanin;
wire illegal_f_scanout;
wire [1:0] illegal_e;
wire [1:0] fpdisable_exc_d;
wire fpdisable_exc_f_scanin;
wire fpdisable_exc_f_scanout;
wire [1:0] fpdisable_exc_e;
wire [1:0] priv_exc_d;
wire [1:0] hpriv_exc_d;
wire parity_err_f_scanin;
wire parity_err_f_scanout;
wire [1:0] icdp_perr_d;
wire exc_f_scanin;
wire exc_f_scanout;
wire [1:0] priv_exc_e;
wire [1:0] hpriv_exc_e;
wire [1:0] icdp_perr_e;
wire ffavor_real;
wire lfavor_real;
wire [1:0] fguselect_d;
wire tgsel_f_scanin;
wire tgsel_f_scanout;
wire twocycle0_stall_e;
wire twocycle1_stall_e;
wire decode_lsu0_e;
wire decode_lsu1_e;
wire [1:0] pstate_am_in;
wire rs1_addr0_d;
wire decode_lsu0_d;
wire casa_or_pst_d;
wire rs1_addr1_d;
wire decode_lsu1_d;
wire lsu_sel0_lower_d;
wire lsu_sel1_lower_d;
wire lsu_sel0_upper_d;
wire lsu_sel1_upper_d;
wire rs1_addr0_upper_d;
wire rs1_addr1_upper_d;
wire exuself_scanin;
wire exuself_scanout;
wire tgselm_f_scanin;
wire tgselm_f_scanout;
wire [1:0] store_float;
wire [4:0] i0_rd;
wire [4:0] i1_rd;
wire [4:0] i0_rd_remap_d;
wire [4:0] i1_rd_remap_d;
wire [4:0] f0_rs1;
wire [4:0] f0_rs2;
wire [4:0] f0_rd;
wire [4:0] f1_rs1;
wire [4:0] f1_rs2;
wire [4:0] f1_rd;
wire [4:0] inst0_rs2;
wire [4:0] inst1_rs2;
wire frf_r2addre_f_scanin;
wire frf_r2addre_f_scanout;
wire inst0_rs2_raw_bit0;
wire inst1_rs2_raw_bit0;
wire fsr_store0;
wire fsr_store1;
wire flush_lexc_m;
wire ifetch_err_f_scanin;
wire ifetch_err_f_scanout;
wire ifetcherr_f_scanin;
wire ifetcherr_f_scanout;
wire [1:0] true_valid_d;
wire truevalid_f_scanin;
wire truevalid_f_scanout;
wire illegal0_pmu_d;
wire illegal1_pmu_d;
wire [1:0] illegal_pmu_d;
wire [1:0] priv_exc_pmu_d;
wire [1:0] hpriv_exc_pmu_d;
wire [1:0] fpdisable_exc_pmu_d;
wire [1:0] valid_e;
wire [1:0] ls_valid_e;
wire decode_fgu0_d;
wire decode_fgu1_d;
wire fgudec_f_scanin;
wire fgudec_f_scanout;
wire decode_fgu0_e;
wire decode_fgu1_e;
wire lsudec_f_scanin;
wire lsudec_f_scanout;
wire st_inst_d;
wire fsr_ldst_d;
wire ldste_f_scanin;
wire ldste_f_scanout;
wire ld_inst_e;
wire st_inst_e;
wire fsr_ldst_e;
wire lsu_valid_e;
wire fpldst_d;
wire load_float0_d;
wire store_float0_d;
wire load_float1_d;
wire store_float1_d;
wire lsdouble_d;
wire prefetch_d;
wire flush_d;
wire memstbar_d;
wire pr_d;
wire hpr_d;
wire sr_d;
wire pst_d;
wire casa_d;
wire ldstub_d;
wire swap_d;
wire altspacei_d;
wire sign_ext_d;
wire [1:0] lsize_d;
wire ldme_f_scanin;
wire ldme_f_scanout;
wire fpldst_e;
wire lsdouble_e;
wire prefetch_e;
wire flush_e;
wire memstbar_e;
wire hpr_e;
wire pr_e;
wire sr_e;
wire casa_e;
wire ldstub_e;
wire swap_e;
wire sign_ext_e;
wire [1:0] lsize_e;
wire [4:0] sraddr_d;
wire sraddr_f_scanin;
wire sraddr_f_scanout;
wire [4:0] sraddr_e;
wire lsu_rd0_msb;
wire lsu_rd1_msb;
wire [4:0] lsu_rd_d;
wire lsurd_f_scanin;
wire lsurd_f_scanout;
wire [4:0] lsu_rd_e;
wire [1:0] ds_m_in;
wire ds_m_scanin;
wire ds_m_scanout;
wire [7:0] annul_ds_dcti_e;
wire [1:0] annul_ds_m_in;
wire annul_m_scanin;
wire annul_m_scanout;
wire tid_e_scanin;
wire tid_e_scanout;
wire [1:0] tid1_e;
wire [1:0] tid0_e;
wire tid_m_scanin;
wire tid_m_scanout;
wire dec_e_scanin;
wire dec_e_scanout;
wire decode1_raw_e;
wire decode0_raw_e;
wire decode1_e;
wire decode0_e;
wire dec_m_scanin;
wire dec_m_scanout;
wire [1:0] inst_valid_m;
wire is_lsu1_d;
wire is_lsu0_d;
wire is_fgu1_d;
wire is_fgu0_d;
wire [1:0] cti_d;
wire inst_e_scanin;
wire inst_e_scanout;
wire [4:0] exc1_e;
wire [4:0] exc0_e;
wire [1:0] is_lsu_e;
wire [1:0] is_fgu_e;
wire [1:0] cti_e;
wire inst_m_scanin;
wire inst_m_scanout;
wire [4:0] exc1_m;
wire [4:0] exc0_m;
wire flush_lexc_e;
wire flush_lexc_f_scanin;
wire flush_lexc_f_scanout;
wire illegal_priv_m_scanin;
wire illegal_priv_m_scanout;
wire [1:0] illegal_inst_m;
wire [1:0] priv_exc_m;
wire [1:0] hpriv_exc_m;
wire [1:0] fpdisable_exc_m;
wire [1:0] br_taken_m;
wire [1:0] icdp_perr_m;
wire [1:0] done_d;
wire [1:0] retry_d;
wire [1:0] sir_d;
wire done_retry_e_scanin;
wire done_retry_e_scanout;
wire [1:0] done_e;
wire [1:0] retry_e;
wire [1:0] sir_e;
wire done_retry_m_scanin;
wire done_retry_m_scanout;
wire [1:0] done_inst_m;
wire [1:0] retry_inst_m;
wire [1:0] sir_inst_m;
wire [1:0] atomic_d;
wire l2miss0_d;
wire l2miss1_d;
wire itlbmiss0_d;
wire itlbmiss1_d;
wire icmiss0_d;
wire icmiss1_d;
wire other0_d;
wire branch0_d;
wire other1_d;
wire branch1_d;
wire power_stall1f_scanin;
wire power_stall1f_scanout;
wire [7:0] power_stall_in;
wire thread_activef_scanin;
wire thread_activef_scanout;
wire [7:0] thread_active;
wire power_throttle1f_scanin;
wire power_throttle1f_scanout;
wire [2:0] power_throt0;
wire [2:0] power_throttle1;
wire power_throttle02_f_scanin;
wire power_throttle02_f_scanout;
wire [2:0] power_throttle0;
wire power_throttle01_f_scanin;
wire power_throttle01_f_scanout;
wire power_throttle00_f_scanin;
wire power_throttle00_f_scanout;
wire change_power_stall;
wire [7:0] new_power_stall;


   input l2clk;
   input scan_in;
   input tcu_pce_ov;		// scan signals
   input spc_aclk;
   input spc_bclk;
   input tcu_scan_en;


   input lsu_dec_pmen;		// power management enable for dec
   input lsu_exu_pmen;		// power management enable for exu
	
   input [7:0] spc_core_running_status;	// active bits for each of the threads


   input [2:0]  power_throttle;	// power throttle, [2:0] is encoded number of stalls in 8 cycle window
				        // 000 - no stalls, 001 - 1 stall, ... 111 - 7 stalls
   input lb_lbist_running;

   input [7:0] pku_idest_p;
   input [7:0] pku_fdest_p;
   input [7:0] pku_fsrc_rd_p;
   input [7:0] pku_lsu_p;
   input [7:0] pku_fgu_p;
   input [7:0] pku_pdist_p;
   input [7:0] pku_twocycle_p;

   input [1:0]  pku_inst_cnt_brtaken00;		// count of inst at e,m,b stages for each thread, for tlu to generate PC at decode
   input [1:0]  pku_inst_cnt_brtaken01;
   input [1:0]  pku_inst_cnt_brtaken02;
   input [1:0]  pku_inst_cnt_brtaken03;
   input [1:0]  pku_inst_cnt_brtaken04;
   input [1:0]  pku_inst_cnt_brtaken05;
   input [1:0]  pku_inst_cnt_brtaken06;
   input [1:0]  pku_inst_cnt_brtaken07;
   input [1:0]  pku_inst_cnt_brtaken10;		// count of inst at e,m,b stages for each thread, for tlu to generate PC at decode
   input [1:0]  pku_inst_cnt_brtaken11;
   input [1:0]  pku_inst_cnt_brtaken12;
   input [1:0]  pku_inst_cnt_brtaken13;
   input [1:0]  pku_inst_cnt_brtaken14;
   input [1:0]  pku_inst_cnt_brtaken15;
   input [1:0]  pku_inst_cnt_brtaken16;
   input [1:0]  pku_inst_cnt_brtaken17;

   input [1:0] exu_test_tid0;		// exu test interface to the irf (bist or ecc errors) 
   input [4:0] exu_test_addr0;
   input exu_test_valid0;

   input [1:0] exu_test_tid1;		// exu test interface to the irf (bist or ecc errors)
   input [4:0] exu_test_addr1;
   input exu_test_valid1;

   input [4:0] ded_exc0_d;		// ifetch related exceptions
   input [4:0] ded_exc1_d;

   input [7:0] tlu_dec_pstate_pef;     	// pstate enable fp bit
   input [7:0] fgu_fprs_fef;	       	// fprs enable fp bit
   input [7:0] tlu_dec_hpstate_hpriv;  	// hpriv bits
   input [7:0] tlu_dec_pstate_priv;    	// priv bits

   input [1:0] dcd_wrtick_d;	      	// write tick

   input lsu_cpq_stall;			// lsu cannot take any more lsu operations, stall decode
   input [1:0] dcd_callclass_d;		// JMPs,CALLs,RETs
   input [1:0] dcd_tcc_d;		// tcc instruction

   input [1:0] dcd_specbr_d;		// branch at decode
   input [1:0] dcd_specfp_d;		// FP at decode

   input [1:0] dcd_exu_src_d;  		// fgu sources will come from the integer unit
   input [1:0] dcd_killfgu_d;  		// dont really send alignaddr, bmask to the fgu

   input [1:0] dcd_sir_d;   		// SIR inst at decode
   input [1:0] dcd_stdfa_d;    		// for partial stores

   input [7:0] pku_valid_e;		// valid for inst at e stage
   input [7:0] pku_annul_ds_dcti_brtaken0_e;	// dcti at e stage has annulled its delay slot (DS)
   input [7:0] pku_annul_ds_dcti_brtaken1_e;	// dcti at e stage has annulled its delay slot (DS)

   input exu0_window_block;      	// for saves,restores,traps on saves,restores,wrpr to cwp
   input exu1_window_block;      
   input [1:0] tlu_window_block;      	// for dones and retries
   
   input [1:0] fgu_idiv_stall;    	// integer divide stall; no int ops to FGU
   input fgu_fdiv_stall;    		// float divide stall; no float loads to the LSU

   input fgu_ecc_asi_stall;		// fgu ecc stall

   input [1:0] dcd_fpdisable_d; 	// inst can cause a fpdisable exception


   // decodes needed by the lsu
   input [1:0] dcd_lsize0_d;		// size of the lsu operation (byte,half,word,dword)
   input [1:0] dcd_lsize1_d;
   input [1:0] dcd_lsu_sign_ext_d;	// lsu operation is a sign extended form
   input [1:0] dcd_load_d;		// op is load or load-like
   input [1:0] dcd_store_d;		// op is store or store-like
   input [1:0] dcd_sethi_d;		// op is special sethi 
   input [1:0] dcd_lsdouble_d;		// ldd inst
   input [1:0] dcd_prefetch_d;		// prefetch inst
   input [1:0] dcd_flush_d;		// flush inst
   input [1:0] dcd_memstbar_d;		// membar, stbar
   input [1:0] dcd_pr_d;		// is a WRPR or RDPR inst
   input [1:0] dcd_priv_d;		// is a privileged inst
   input [1:0] dcd_hpr_d;		// is a hypervisor priv inst
   input [1:0] dcd_sr_d;		// ASR operation
   input [1:0] dcd_casa_d;		// CASA inst
   input [1:0] dcd_ldstub_d;		// LDSTUB inst
   input [1:0] dcd_alt_d;		// alternate but not imm
   input [1:0] dcd_alti_d;		// imm alternate
   input [1:0] dcd_swap_d;		// SWAP inst
	
   input [1:0] dcd_fsrc_rs1_d;		// inst has rs1 FP source
   input [1:0] dcd_fsrc_rs2_d;		// inst has rs2 FP source
   input [1:0] dcd_fpdest_single_d;	// FP dest is single precision (SP)
   input [1:0] dcd_fp_rs1_single_d;	// FP rs1 source is SP
   input [1:0] dcd_fp_rs2_single_d;	// FP rs2 source is SP
   input [1:0] dcd_fsrsync_d;		// inst is LDFSR or STFSR
   input [1:0] dcd_done_d;		// inst is DONE inst
   input [1:0] dcd_retry_d;		// inst is a RETRY inst

   input [4:0] dec_inst0_rs1_d;		// RS1
   input [4:0] dec_inst0_rs2_d;		// RS2
   input [4:0] dec_inst0_raw_rd_d;	// RD
   input [4:0] dec_inst1_rs1_d;
   input [4:0] dec_inst1_rs2_d;
   input [4:0] dec_inst1_raw_rd_d;

   input [1:0] dcd_save_restore_d;	// SAVE or RESTORE
   input ded_oddwin0_d;			// window is odd or not
   input ded_oddwin1_d;

   input [1:0] ded_perr_p;		// inst parity error
   input [1:0] ded_ferr_p;		// inst fetch error
   input [1:0] ded_legal_p;		// inst is a legal instruction

   input dec_inst0_b31;			// bit 31 of instruction
   input dec_inst1_b31;

   input [5:0] dec_inst0_op3_d;		// op3 field of inst
   input [5:0] dec_inst1_op3_d;

   input [7:0] dec_inst0_opf_d;		// opf field of inst
   input [7:0] dec_inst1_opf_d;

   input [7:0] pku_base_pick_p;		// base pick without decode qualifications (includes cancel_pick, flush_buffer)
   input [3:0] pku_raw_pick0_p;		// pick with no qualifications (no cancel_pick, no flush_buffer)
   input [7:4] pku_raw_pick1_p;

   input [7:0] pku_ds_e;		// inst at e is a DS

   input [7:0] pku_load_flush_w;  	// load flush signals to IFU
   input [7:0] tlu_flush_ifu;		// trap flush
 
   input [7:0] pku_flush_f1;		// flush signals for FGU f1,f2 stages
   input [7:0] pku_flush_f2;

   input [7:0] pku_flush_lm;		// flush signals for LSU M,B stages
   input [7:0] pku_flush_lb;

   input [7:0] pku_flush_m;		// flush signals for TLU M,B stages
   input [7:0] pku_flush_b;

   input [1:0] dec_br_taken_e1;		// taken branches

   input       spu_mult_request;	// crypto multiply request

   input       lsu_block_store_stall;   // stall decode to read the sources of the store
   input [4:3] lsu_block_store_rd;	// RD for the block store
   input [2:0] lsu_block_store_tid;	// tid for the block store

   input       tlu_dtlb_reload_stall;	// stall decode for 2 cycles on a DTLB miss; LSU can't take any more lsu ops
   input [7:0] tlu_pstate_am;		// address mask bit

   output      dec_valid0_d;		// inst is valid at d stage
   output      dec_valid1_d;		
   output      dec_decode0_d;		// inst is decoded at d stage (implies a shift)
   output      dec_decode1_d;
   output      del_noshift0_d;		// inst is valid and not decoded (don't shift the decode stage)
   output      del_noshift1_d;

   // exu interface
   output [4:0] dec_inst0_rd_d;		// RD field (takes windows and calls into account)
   output [4:0] dec_inst1_rd_d;

   output [1:0] dec_tid0_d;		// TID for exu0
   output [1:0] dec_tid1_d;		// TID for exu1
   output [1:0] dec_tid0_p;		// TID for IRF
   output [1:0] dec_tid1_p;
   output [1:0] dec_valid_e;		// thread group [0,1] is valid at e stage
   output [1:0] dec_pmu_valid_e;	// thread group [0,1] is valid at e stage; dont include ifetch_err
   output 	dec_fgu_valid_e;        // fgu is valid at e

   // fgu interface
   output [4:0] dec_frf_r1_addr_d;	// FRF r1 read addr
   output [4:0] dec_frf_r2_addr_d;	// FRF r2 read addr (including store-floats)
   output [4:3] dec_frf_r2_addr_e;	// FRF r2 read addr (for LSU)
   output 	dec_frf_r1_vld_d;	// FRF r1 read valid
   output 	dec_frf_r2_vld_d;	// FRF r2 read valid
   output 	dec_frf_r1_32b_d;	// FRF rs1 source is single-precision
   output 	dec_frf_r2_32b_d;	// FRF rs2 source is single-precision
   output 	dec_frf_r1_odd32b_d;	// FRF rs1 source is single-precision and odd
   output 	dec_frf_r2_odd32b_d;	// FRF rs2 source is single-precision and odd
   output [4:0] dec_frf_w_addr_d;	// FRF write addr
   output 	dec_frf_w_vld_d;	// FRF write addr is valid
   output 	dec_frf_w_32b_d;	// FRF write is single precision
   output 	dec_frf_w_odd32b_d;	// FRF write is single precision; rd is odd
   output 	dec_spu_grant_d;	// SPU grant for a crypto multiply
   output 	dec_spu_grant_fgu_d;	// SPU grant for a crypto multiply to the fgu
   output 	dec_exu_src_vld_d;	// FGU op has any valid source
   output [4:0] dec_irf_w_addr_d;  	// RD for an integer op executed by the FGU
   output 	dec_frf_store_d;	// store-float of FRF data
   output 	dec_fsr_store_d;	// store-float of FSR data
   output [5:0] dec_fgu_op3_d;		// op3 field
   output [7:0] dec_fgu_opf_d;		// opf field
   output 	dec_fgu_decode_d;	// FGU op decoded this cycle
   output [2:0] dec_fgu_tid_d;		// TID for FGU op
   output 	dec_flush_f1;		// Flush f1 stage of the FGU
   output 	dec_flush_f2;		// Flush f2 stage of the FGU
   output 	dec_flush_lm;		// Flush the m stage of a load
   output 	dec_flush_lb;		// Flush the bypass stage of a load
   output [1:0] dec_flush_m;            // Flush the m stage of the ex units
   output [1:0] dec_flush_b;            // Flush the b stage of the ex units, also tlu

   output [7:0] dec_block_store_b;	// block store at b stage to tlu

   // tlu interface
   output [4:0] dec_exc0_m;             // encoded exception status to tlu
   output [4:0] dec_exc1_m;
   output [1:0] dec_inst0_cnt;		// inst cnt of e,m,b stage
   output [1:0] dec_inst1_cnt;
   output [1:0] dec_tid0_m;		// thread id
   output [1:0] dec_tid1_m;
   output [1:0] dec_inst_valid_m;	// inst is valid at m stage
   output [1:0] dec_lsu_inst_m;		// lsu inst at m stage
   output [1:0] dec_fgu_inst_m;		// fgu inst at m stage
   output [1:0] dec_cti_inst_m;		// fgu inst at m stage

   output [1:0] dec_illegal_inst_m;	// illegal at m stage
   output [1:0] dec_icache_perr_m;	// icache parity error at m stage
   output [1:0] dec_priv_exc_m;		// priv exception at m stage
   output [1:0] dec_hpriv_exc_m;	// hypervison priv exception at m stage
   output [1:0] dec_fpdisable_exc_m;	// fp disable exception at m stage
   output [1:0] dec_br_taken_m;		// br taken at m stage
   output [1:0] dec_done_inst_m;	// done inst at m stage
   output [1:0] dec_retry_inst_m;	// retry inst at m stage
   output [1:0] dec_sir_inst_m;		// sir inst a m stage

   output [1:0]	dec_ds_m;	        // this instruction is a DS
   output [1:0] dec_annul_ds_m;		// DS at m stage is annulled

   output [1:0]	dec_fgu_sel_e;		// mux select between TG's for fgu ops
   output [1:0]	dec_fgu_sel_m;		// mux select between TG's for fgu ops

   output 	dec_lsu_sel0_e;		// mux select between TG's for lsu ops
   output 	dec_lsu_sel1_e;		

   output 	dec_rs1_addr0_e;	
   output 	dec_rs1_addr1_e;	

   output 	dec_lsu_sel0_upper_e;	// mux select taking pstate AM into account
   output 	dec_lsu_sel1_upper_e;

   output 	dec_lsu_sel0_lower_e;	// mux select taking pstate AM into account
   output 	dec_lsu_sel1_lower_e;

   output 	dec_rs1_addr0_upper_e;
   output 	dec_rs1_addr1_upper_e;


   output [7:0] del_pick_d;		// picks to CCR logic       

   // lsu interface
   output 	dec_ld_inst_e;         	// load inst
   output 	dec_st_inst_e;         	// store inst
   output 	dec_fsr_ldst_e;         // LDFSR,STFSR
   output 	dec_fpldst_inst_e;     	// FP load or store inst
   output 	dec_ldst_dbl_e;        	// ldd inst
   output 	dec_pref_inst_e;       	// prefetch inst
   output 	dec_flush_inst_e;      	// flush inst
   output 	dec_memstbar_inst_e;	// membar, stbar
   
   output 	dec_sr_inst_e;        	// ASR inst
   output 	dec_pr_inst_e;        	// priv inst
   output 	dec_hpr_inst_e;        	// hypervisor inst
   output 	dec_casa_inst_e;       	// CASA inst
   output 	dec_ldstub_inst_e;     	// LDSTUB inst
   output 	dec_swap_inst_e;       	// SWAP inst
   output 	dec_altspace_d;        	// Alternate space access
   output 	dec_sign_ext_e;        	// Sign extend lsu op
   output [4:0] dec_sraddr_e;          	// source address for ASR access
   output 	dec_imm_asi_vld_d;     	// immediate form of alternate access
   output [7:0] dec_imm_asi_d;         	// 8-bit ASI access
   output [1:0] dec_ldst_sz_e;		// size of the ldst operation
   

   output 	dec_ld_inst_d;		// load inst decoded

   output [1:0] dec_lsu_tid0_d;		// tid for lsu operation
   output [1:0] dec_lsu_tid1_d;		// tid for lsu operation
   output       dec_lsu_tg_d;		// tid for lsu operation
   output [4:0] dec_lsu_rd_e;		// RD destination of lsu operation

   output del_test0_sel_p;		// mux selects for IRF read port rs3
   output del_twocycle0_std_p;
   output del_twocycle0_rs2_p;
   output del_default0_sel_p;

   output del_test1_sel_p;
   output del_twocycle1_std_p;
   output del_twocycle1_rs2_p;
   output del_default1_sel_p;

   output [4:0] del_test_addr0_p;	// address to read for exu test access
   output [4:0] del_test_addr1_p;

   output [9:0] dec_instr0_type_d;	// pmu stuff thread group 0
   output [9:0] dec_instr1_type_d;	// pmu stuff thread group 1

   output [1:0] dec_exu_clken;		// clk enable signals to the exu

   output [1:0] del_tg_clken;  		// clk enables for thread groups
   
   output scan_out;

   output [1:0] dec_true_valid_e;  	// take illegals and other exceptions into account

   output [1:0] dec_load_flush_w;

   output dec_lsu_sel0_d;      		// to the pmu to decide which tid to use for lsu at d stage

   output [7:0] dec_raw_pick_p;

   output [1:0] dec_ierr_d;  		// tell pku that an inst error has occurred: illegal, parity error or ifetch error

   output [7:0] dec_block_store_stall;  // prevent window ops from coming too early after a block store 

dec_del_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

dec_del_ctl_spare_ctl_macro__flops_0__num_6 spares  (
);

// bit 0 maps to spare0_flop
dec_del_ctl_msff_ctl_macro__scanreverse_1__width_6 spare_5_0_lat  (
        .scan_in(spares_scanin),
        .scan_out(spares_scanout),
	.l1clk	(l1clk),
        .din    ({{3{1'b0}},pmu_valid_d[0],1'b0,pmu_valid_d[1]}),
        .dout   ({spare_5_0_lat_unused[3:1],pmu_valid_e[0],spare_5_0_lat_unused[0],pmu_valid_e[1]}),
  .siclk(siclk),
  .soclk(soclk)
);

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
assign se    = tcu_scan_en;
// end scan


assign dec_load_flush_w[1:0] = { |pku_load_flush_w[7:4], |pku_load_flush_w[3:0] };

assign callinst0_d = dcd_callclass_d[0] & ~dec_inst0_b31;
assign callinst1_d = dcd_callclass_d[1] & ~dec_inst1_b31;

// for save/restore invert oddwin since rd is in the new window
assign dec_inst0_rd_d[4] = (dec_inst0_raw_rd_d[4] & ~callinst0_d) ^ ((dec_inst0_raw_rd_d[3] | callinst0_d) & (ded_oddwin0_d ^ dcd_save_restore_d[0]));
assign dec_inst0_rd_d[3:0] = dec_inst0_raw_rd_d[3:0] | {4{callinst0_d}};

assign dec_inst1_rd_d[4] = (dec_inst1_raw_rd_d[4] & ~callinst1_d) ^ ((dec_inst1_raw_rd_d[3] | callinst1_d) & (ded_oddwin1_d ^ dcd_save_restore_d[1]));
assign dec_inst1_rd_d[3:0] = dec_inst1_raw_rd_d[3:0] | {4{callinst1_d}};

// predecodes for timing (make dec_decode* fast)

// make sure twocycle is lsu to deal with illegal instructions (partial decodes)
assign pdecode0_in[6:0] = {  pku_idest_p[0],pku_fdest_p[0],pku_fsrc_rd_p[0],pku_lsu_p[0],pku_fgu_p[0],
			  pku_pdist_p[0],pku_twocycle_p[0] & pku_lsu_p[0] };
									    
assign pdecode1_in[6:0] = {  pku_idest_p[1],pku_fdest_p[1],pku_fsrc_rd_p[1],pku_lsu_p[1],pku_fgu_p[1],
			  pku_pdist_p[1],pku_twocycle_p[1] & pku_lsu_p[1] };
									    
assign pdecode2_in[6:0] = {  pku_idest_p[2],pku_fdest_p[2],pku_fsrc_rd_p[2],pku_lsu_p[2],pku_fgu_p[2],
			  pku_pdist_p[2],pku_twocycle_p[2] & pku_lsu_p[2] };
									    
assign pdecode3_in[6:0] = {  pku_idest_p[3],pku_fdest_p[3],pku_fsrc_rd_p[3],pku_lsu_p[3],pku_fgu_p[3],
			  pku_pdist_p[3],pku_twocycle_p[3] & pku_lsu_p[3] };


assign pdec0_in[6:0] =   ({7{del_noshift0_d}} & pdecode0_d[6:0]) |
			   ({7{~del_noshift0_d & pku_raw_pick0_p[0] & ded_legal_p[0] & ~ded_perr_p[0] & ~ded_ferr_p[0]}} & pdecode0_in[6:0]) |
			   ({7{~del_noshift0_d & pku_raw_pick0_p[1] & ded_legal_p[0] & ~ded_perr_p[0] & ~ded_ferr_p[0]}} & pdecode1_in[6:0]) |
			   ({7{~del_noshift0_d & pku_raw_pick0_p[2] & ded_legal_p[0] & ~ded_perr_p[0] & ~ded_ferr_p[0]}} & pdecode2_in[6:0]) |
			   ({7{~del_noshift0_d & pku_raw_pick0_p[3] & ded_legal_p[0] & ~ded_perr_p[0] & ~ded_ferr_p[0]}} & pdecode3_in[6:0]);


dec_del_ctl_msff_ctl_macro__width_7 pdecode0f  (
 .scan_in(pdecode0f_scanin),
 .scan_out(pdecode0f_scanout),
 .din(pdec0_in[6:0]),
 .dout(pdecode0_d[6:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign { idest0_d, fdest0_d, fsrc0_rd_d, lsu0_d, fgu0_d, pdist0_d, twocycle0_d } = pdecode0_d[6:0];

// make sure twocycle is lsu to deal with illegal instructions (partial decodes)
assign pdecode4_in[6:0] = {  pku_idest_p[4],pku_fdest_p[4],pku_fsrc_rd_p[4],pku_lsu_p[4],pku_fgu_p[4],
			  pku_pdist_p[4],pku_twocycle_p[4] & pku_lsu_p[4] };
									    
assign pdecode5_in[6:0] = {  pku_idest_p[5],pku_fdest_p[5],pku_fsrc_rd_p[5],pku_lsu_p[5],pku_fgu_p[5],
			  pku_pdist_p[5],pku_twocycle_p[5] & pku_lsu_p[5] };
									    
assign pdecode6_in[6:0] = {  pku_idest_p[6],pku_fdest_p[6],pku_fsrc_rd_p[6],pku_lsu_p[6],pku_fgu_p[6],
			  pku_pdist_p[6],pku_twocycle_p[6] & pku_lsu_p[6] };
									    
assign pdecode7_in[6:0] = {  pku_idest_p[7],pku_fdest_p[7],pku_fsrc_rd_p[7],pku_lsu_p[7],pku_fgu_p[7],
			  pku_pdist_p[7],pku_twocycle_p[7] & pku_lsu_p[7] };

assign pdec1_in[6:0] =   ({7{del_noshift1_d}} & pdecode1_d[6:0]) |
			   ({7{~del_noshift1_d & pku_raw_pick1_p[4] & ded_legal_p[1] & ~ded_perr_p[1] & ~ded_ferr_p[1]}} & pdecode4_in[6:0]) |
			   ({7{~del_noshift1_d & pku_raw_pick1_p[5] & ded_legal_p[1] & ~ded_perr_p[1] & ~ded_ferr_p[1]}} & pdecode5_in[6:0]) |
			   ({7{~del_noshift1_d & pku_raw_pick1_p[6] & ded_legal_p[1] & ~ded_perr_p[1] & ~ded_ferr_p[1]}} & pdecode6_in[6:0]) |
			   ({7{~del_noshift1_d & pku_raw_pick1_p[7] & ded_legal_p[1] & ~ded_perr_p[1] & ~ded_ferr_p[1]}} & pdecode7_in[6:0]);


dec_del_ctl_msff_ctl_macro__width_7 pdecode1f  (
 .scan_in(pdecode1f_scanin),
 .scan_out(pdecode1f_scanout),
 .din(pdec1_in[6:0]),
 .dout(pdecode1_d[6:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign { idest1_d, fdest1_d, fsrc1_rd_d, lsu1_d, fgu1_d, pdist1_d, twocycle1_d } = pdecode1_d[6:0];


assign final_pick_p[3:0] = pku_base_pick_p[3:0] & {4{~(dec_valid0_d & ~dec_decode0_d)}};
assign final_pick_p[7:4] = pku_base_pick_p[7:4] & {4{~(dec_valid1_d & ~dec_decode1_d)}};


assign shift0_d = ~del_noshift0_d;

assign raw_pick0_in[3:0] = ({4{shift0_d}} & pku_raw_pick0_p[3:0]) |
		           ({4{~shift0_d}} & pick0_d[3:0]);

assign pick0_in[3:0] = ({4{shift0_d}} & final_pick_p[3:0]) |
		       ({4{~shift0_d}} & pick0_d[3:0]);

dec_del_ctl_msff_ctl_macro__width_4 pick0f  (
 .scan_in(pick0f_scanin),
 .scan_out(pick0f_scanout),
 .l1clk(l1clk),
 .din  (pick0_in[3:0]),
 .dout (pick0_d[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign shift1_d = ~del_noshift1_d;

assign raw_pick1_in[3:0] = ({4{shift1_d}} & pku_raw_pick1_p[7:4]) |
		           ({4{~shift1_d}} & pick1_d[3:0]);

assign pick1_in[3:0] = ({4{shift1_d}} & final_pick_p[7:4]) |
		       ({4{~shift1_d}} & pick1_d[3:0]);

dec_del_ctl_msff_ctl_macro__width_4 pick1f  (
 .scan_in(pick1f_scanin),
 .scan_out(pick1f_scanout),
 .l1clk(l1clk),
 .din  (pick1_in[3:0]),
 .dout (pick1_d[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_raw_pick_p[7:0] = {raw_pick1_in[3:0], raw_pick0_in[3:0]};

dec_del_ctl_msff_ctl_macro__width_16 privstatef  (
 .scan_in(privstatef_scanin),
 .scan_out(privstatef_scanout),
 .l1clk(l1clk),
 .din  ({tlu_dec_pstate_priv[7:0],tlu_dec_hpstate_hpriv[7:0]}),
 .dout ({tlu_priv[7:0],tlu_hpriv[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_16 fef  (
 .scan_in(fef_scanin),
 .scan_out(fef_scanout),
 .l1clk(l1clk),
 .din  ({tlu_dec_pstate_pef[7:0],fgu_fprs_fef[7:0]}),
 .dout ({tlu_pef[7:0],fgu_fef[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// priv bits from the tlu
assign priv_d[0] = |(pick0_d[3:0] & tlu_priv[3:0]);
assign hpriv_d[0] = |(pick0_d[3:0] & tlu_hpriv[3:0]);
assign fpdis_d[0] = |(pick0_d[3:0] & ~(tlu_pef[3:0] & fgu_fef[3:0]));

assign priv_d[1] = |(pick1_d[3:0] & tlu_priv[7:4]);
assign hpriv_d[1] = |(pick1_d[3:0] & tlu_hpriv[7:4]);
assign fpdis_d[1] = |(pick1_d[3:0] & ~(tlu_pef[7:4] & fgu_fef[7:4]));

assign del_pick_d[3:0] = pick0_d[3:0];
assign del_pick_d[7:4] = pick1_d[3:0];


assign inst0_cnt_brtaken0[1:0] = ({2{raw_pick0_in[3]}} & pku_inst_cnt_brtaken03[1:0]) |
			         ({2{raw_pick0_in[2]}} & pku_inst_cnt_brtaken02[1:0]) |
			         ({2{raw_pick0_in[1]}} & pku_inst_cnt_brtaken01[1:0]) |	
                                 ({2{raw_pick0_in[0]}} & pku_inst_cnt_brtaken00[1:0]);

assign inst0_cnt_brtaken1[1:0] = ({2{raw_pick0_in[3]}} & pku_inst_cnt_brtaken13[1:0]) |
			         ({2{raw_pick0_in[2]}} & pku_inst_cnt_brtaken12[1:0]) |
			         ({2{raw_pick0_in[1]}} & pku_inst_cnt_brtaken11[1:0]) |	
                                 ({2{raw_pick0_in[0]}} & pku_inst_cnt_brtaken10[1:0]);

assign inst1_cnt_brtaken0[1:0] = ({2{raw_pick1_in[3]}} & pku_inst_cnt_brtaken07[1:0]) |
			         ({2{raw_pick1_in[2]}} & pku_inst_cnt_brtaken06[1:0]) |
			         ({2{raw_pick1_in[1]}} & pku_inst_cnt_brtaken05[1:0]) |	
                                 ({2{raw_pick1_in[0]}} & pku_inst_cnt_brtaken04[1:0]);

assign inst1_cnt_brtaken1[1:0] = ({2{raw_pick1_in[3]}} & pku_inst_cnt_brtaken17[1:0]) |
			         ({2{raw_pick1_in[2]}} & pku_inst_cnt_brtaken16[1:0]) |
			         ({2{raw_pick1_in[1]}} & pku_inst_cnt_brtaken15[1:0]) |	
                                 ({2{raw_pick1_in[0]}} & pku_inst_cnt_brtaken14[1:0]);

assign br_taken_e[1:0] = dec_br_taken_e1[1:0] & dec_valid_e[1:0] & ~ifetch_err_e[1:0];

assign inst0_cnt[1:0] = ({2{~br_taken_e[0]}} & inst0_cnt_brtaken0[1:0]) |
			({2{ br_taken_e[0]}} & inst0_cnt_brtaken1[1:0]);

assign inst1_cnt[1:0] = ({2{~br_taken_e[1]}} & inst1_cnt_brtaken0[1:0]) |
			({2{ br_taken_e[1]}} & inst1_cnt_brtaken1[1:0]);
	                

// send inst cnt directly off flop to tlu
dec_del_ctl_msff_ctl_macro__width_4 instcntf  (
 .scan_in(instcntf_scanin),
 .scan_out(instcntf_scanout),
 .l1clk(l1clk),
 .din  ({inst0_cnt[1:0],inst1_cnt[1:0]}),
 .dout ({dec_inst0_cnt[1:0],dec_inst1_cnt[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_16  exutestf  (
 .scan_in(exutestf_scanin),
 .scan_out(exutestf_scanout),
 .l1clk(l1clk),
 .din  ({exu_test_tid0[1:0],exu_test_tid1[1:0],exu_test_addr0[4:0],exu_test_addr1[4:0],exu_test_valid0,exu_test_valid1}),
 .dout ({ttid0_p[1:0],ttid1_p[1:0],del_test_addr0_p[4:0],del_test_addr1_p[4:0],test_stall0_in,test_stall1_in}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_2  teststallf  (
 .scan_in(teststallf_scanin),
 .scan_out(teststallf_scanout),
 .l1clk(l1clk),
 .din  ({test_stall0_in,test_stall1_in}),
 .dout ({test_stall0,test_stall1}),
  .siclk(siclk),
  .soclk(soclk)
);

// DEC must select the correct register to send to LSU in the second cycle of a twocycle op.
// For STD, the register is Rs3+1
// For CASA, the register is Rs2
assign del_test0_sel_p = test_stall0_in;
assign del_twocycle0_std_p = twocycle_p[0] & ~dec_inst0_op3_d[3] & ~test_stall0_in;
assign del_twocycle0_rs2_p = twocycle_p[0] &  dec_inst0_op3_d[3] & ~test_stall0_in;
assign twocycle0_sel_p = twocycle_p[0] & ~test_stall0_in;
assign del_default0_sel_p = ~test_stall0_in & ~twocycle_p[0];

assign del_test1_sel_p = test_stall1_in;
assign del_twocycle1_std_p = twocycle_p[1] & ~dec_inst1_op3_d[3] & ~test_stall1_in;
assign del_twocycle1_rs2_p = twocycle_p[1] &  dec_inst1_op3_d[3] & ~test_stall1_in;
assign twocycle1_sel_p = twocycle_p[1] & ~test_stall1_in;
assign del_default1_sel_p = ~test_stall1_in & ~twocycle_p[1];

// generate tid's to the EXU
assign tid0_p[1] = ~raw_pick0_in[1] & ~raw_pick0_in[0];
assign tid0_p[0] = ~raw_pick0_in[2] & ~raw_pick0_in[0];

assign tid1_p[1] = ~raw_pick1_in[1] & ~raw_pick1_in[0];
assign tid1_p[0] = ~raw_pick1_in[2] & ~raw_pick1_in[0];

// force the same tid for twocycle operations (std,casa,pst)
assign dec_tid0_p[1:0] = ({2{del_default0_sel_p}} & tid0_p[1:0]) |
		         ({2{twocycle0_sel_p}} & tid0_d[1:0]) |
			 ({2{del_test0_sel_p}} & ttid0_p[1:0]);

assign dec_tid1_p[1:0] = ({2{del_default1_sel_p}} & tid1_p[1:0]) |
		         ({2{twocycle1_sel_p}} & tid1_d[1:0]) |
			 ({2{del_test1_sel_p}} & ttid1_p[1:0]);

// technically we dont need to clear the valid_d's for br_mispredict, trap flush or load flush
// we will never get a dec_valid_e for these cases
// clear it anyway

// flop tlu_flush_ifu if it don't make timing
assign valid_d_in[3:0] = (pku_base_pick_p[3:0] | (valid_d[3:0] & ~{4{dec_decode0_d}})) & ~tlu_flush_ifu[3:0] & ~pku_load_flush_w[3:0];
assign valid_d_in[7:4] = (pku_base_pick_p[7:4] | (valid_d[7:4] & ~{4{dec_decode1_d}})) & ~tlu_flush_ifu[7:4] & ~pku_load_flush_w[7:4];

dec_del_ctl_msff_ctl_macro__width_8  val_df  (
 .scan_in(val_df_scanin),
 .scan_out(val_df_scanout),
 .l1clk(l1clk),
 .din  (valid_d_in[7:0]),
 .dout (valid_d[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// for speed, have dec_valid0,1_d come off flop
assign valid0_d_in = |valid_d_in[3:0];
assign valid1_d_in = |valid_d_in[7:4];

dec_del_ctl_msff_ctl_macro__width_2  valid_df  (
 .scan_in(valid_df_scanin),
 .scan_out(valid_df_scanout),
 .l1clk(l1clk),
 .din  ({valid0_d_in,valid1_d_in}),
 .dout ({valid0_d,valid1_d}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_valid0_d = valid0_d;
assign dec_valid1_d = valid1_d;

dec_del_ctl_msff_ctl_macro__width_2 dtlb_reloadf  (
 .scan_in(dtlb_reloadf_scanin),
 .scan_out(dtlb_reloadf_scanout),
 .l1clk(l1clk),
 .din  ({tlu_dtlb_reload_stall,dtlb_reload[1]}),
 .dout (dtlb_reload[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign dtlb_reload_stall = |dtlb_reload[1:0];


// we delay 1 cycle to give time to any STD's or PDIST's that might be going on
dec_del_ctl_msff_ctl_macro__width_1 block_store0f  (
 .scan_in(block_store0f_scanin),
 .scan_out(block_store0f_scanout),
 .l1clk(l1clk),
 .din  (lsu_block_store_stall),
 .dout (pre_block_store_stall),
  .siclk(siclk),
  .soclk(soclk)
);


assign block_store_stall_in = (block_store_stall | pre_block_store_stall) & ~reset_block_store_stall;

dec_del_ctl_msff_ctl_macro__width_1 block_storef  (
 .scan_in(block_storef_scanin),
 .scan_out(block_storef_scanout),
 .l1clk(l1clk),
 .din  (block_store_stall_in),
 .dout (block_store_stall),
  .siclk(siclk),
  .soclk(soclk)
);

assign block_store_rd_in[4:3] = ({2{lsu_block_store_stall}} & lsu_block_store_rd[4:3]) |
				({2{~lsu_block_store_stall}} & block_store_rd[4:3]);

dec_del_ctl_msff_ctl_macro__width_2 block_store_rdhif  (
 .scan_in(block_store_rdhif_scanin),
 .scan_out(block_store_rdhif_scanout),
 .l1clk(l1clk),
 .din  (block_store_rd_in[4:3]),
 .dout (block_store_rd[4:3]),
  .siclk(siclk),
  .soclk(soclk)
);

// pre_block_store_stall must reset the count for the case where the sequence is restarted
assign block_store_rd_in[2:0] = ({3{block_store_stall}} & (block_store_rd[2:0]+3'b001)) &
				({3{~pre_block_store_stall}});

dec_del_ctl_msff_ctl_macro__width_3 block_store_rdlof  (
 .scan_in(block_store_rdlof_scanin),
 .scan_out(block_store_rdlof_scanout),
 .l1clk(l1clk),
 .din  (block_store_rd_in[2:0]),
 .dout (block_store_rd[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign block_store_tid_in[2:0] = ({3{lsu_block_store_stall}} & lsu_block_store_tid[2:0]) |
				 ({3{~lsu_block_store_stall}} & block_store_tid[2:0]);

dec_del_ctl_msff_ctl_macro__width_3 block_store_tidf  (
 .scan_in(block_store_tidf_scanin),
 .scan_out(block_store_tidf_scanout),
 .l1clk(l1clk),
 .din  (block_store_tid_in[2:0]),
 .dout (block_store_tid[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign block_store_stall0 = (block_store_stall | pre_block_store_stall) & ~block_store_tid[2];

assign block_store_stall1 = (block_store_stall | pre_block_store_stall) & block_store_tid[2];

// prevent window ops from coming too early after a block store
// it is possible for the 8th beat to have an ecc exception
// for this type of exception, tlu may take an extra cycle before signalling flush

// must reset the dec_block_store_stall with pre_block_store_stall in case the sequence is restarted
assign dec_block_store_stall[7:0] = {8{block_store_stall}}  &  {block_store_tid[2:0] == 3'b111,
								block_store_tid[2:0] == 3'b110,
								block_store_tid[2:0] == 3'b101,
								block_store_tid[2:0] == 3'b100,
								block_store_tid[2:0] == 3'b011,
								block_store_tid[2:0] == 3'b010,
								block_store_tid[2:0] == 3'b001,
								block_store_tid[2:0] == 3'b000} & {8{~pre_block_store_stall}};


assign cpq_stall_in = lsu_cpq_stall;

dec_del_ctl_msff_ctl_macro__width_1 cpq_stallf  (
 .scan_in(cpq_stallf_scanin),
 .scan_out(cpq_stallf_scanout),
 .l1clk(l1clk),
 .din  (cpq_stall_in),
 .dout (cpq_stall),
  .siclk(siclk),
  .soclk(soclk)
);

assign fecc_stall_in = fgu_ecc_asi_stall;

dec_del_ctl_msff_ctl_macro__width_1 fecc_stallf  (
 .scan_in(fecc_stallf_scanin),
 .scan_out(fecc_stallf_scanout),
 .l1clk(l1clk),
 .din  (fecc_stall_in),
 .dout (fecc_stall),
  .siclk(siclk),
  .soclk(soclk)
);

// no need to make this flushable because it is not speculative ...
// we always wait 1 cycle before starting the block store to allow prior twocycle operations
dec_del_ctl_msff_ctl_macro__width_3 block_resetf  (
 .scan_in(block_resetf_scanin),
 .scan_out(block_resetf_scanout),
 .l1clk(l1clk),
 .din  (block_rst_cnt_in[2:0]),
 .dout (block_rst_cnt[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// pre_block_store_stall must reset the count for the case where the sequence is restarted
assign block_rst_cnt_in[2:0] = ({3{block_store_stall}} & (block_rst_cnt[2:0]+3'b001)) &
			       ({3{~pre_block_store_stall}});
assign reset_block_store_stall = &(block_rst_cnt[2:0]);

// generate dec_block_store_b[7:0] to tlu to reduce routes

dec_del_ctl_msff_ctl_macro__width_4 block_store_e  (
 .scan_in(block_store_e_scanin),
 .scan_out(block_store_e_scanout),
 .l1clk(l1clk),
 .din  ({block_store_stall,block_store_tid[2:0]}),
 .dout ({block_store_stall_e,block_store_tid_e[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_4 block_store_m  (
 .scan_in(block_store_m_scanin),
 .scan_out(block_store_m_scanout),
 .l1clk(l1clk),
 .din  ({block_store_stall_e,block_store_tid_e[2:0]}),
 .dout ({block_store_stall_m,block_store_tid_m[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_4 block_store_b  (
 .scan_in(block_store_b_scanin),
 .scan_out(block_store_b_scanout),
 .l1clk(l1clk),
 .din  ({block_store_stall_m,block_store_tid_m[2:0]}),
 .dout ({block_store_stall_b,block_store_tid_b[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_block_store_b[0] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b000);
assign dec_block_store_b[1] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b001);
assign dec_block_store_b[2] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b010);
assign dec_block_store_b[3] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b011);
assign dec_block_store_b[4] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b100);
assign dec_block_store_b[5] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b101);
assign dec_block_store_b[6] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b110);
assign dec_block_store_b[7] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b111);


// favor bits: only toggle when the relevant conflict is decided one way or the other

// load favor bit (which load to favor in case of two loads)
// harden illegals
assign set_lfavor = (dec_decode0_d & lsusel0_d & lsu0_d & lsu1_d & dec_valid1_d & ~(fgu0_d & fgu1_d));
assign reset_lfavor = (dec_decode1_d & ~lsusel0_d & lsu0_d & lsu1_d & dec_valid0_d & ~(fgu0_d & fgu1_d));

assign lfavor_in = (lfavor | set_lfavor) & ~reset_lfavor;
dec_del_ctl_msff_ctl_macro__width_1 lfavorf  (
 .scan_in(lfavorf_scanin),
 .scan_out(lfavorf_scanout),
 .l1clk(l1clk),
 .din  (lfavor_in),
 .dout (lfavor),
  .siclk(siclk),
  .soclk(soclk)
);

// fpu favor bit (which fpu to favor in case of two fpus)
// harden illegals
assign set_ffavor = (dec_decode0_d & fgusel0_d & fgu0_d & fgu1_d & dec_valid1_d & ~(lsu0_d & lsu1_d));
assign reset_ffavor = (dec_decode1_d & ~fgusel0_d & fgu0_d & fgu1_d & dec_valid0_d & ~(lsu0_d & lsu1_d));

assign ffavor_in = (ffavor | set_ffavor) & ~reset_ffavor;
dec_del_ctl_msff_ctl_macro__width_1 ffavorf  (
 .scan_in(ffavorf_scanin),
 .scan_out(ffavorf_scanout),
 .l1clk(l1clk),
 .din  (ffavor_in),
 .dout (ffavor),
  .siclk(siclk),
  .soclk(soclk)
);

// store-float favor bit (which store-float to favor in case of two store-floats)
assign set_sffavor = (dec_decode0_d & lsu_float_case & dec_valid1_d);
assign reset_sffavor = (dec_decode1_d & lsu_float_case & dec_valid0_d);

assign sffavor_in = (sffavor | set_sffavor) & ~reset_sffavor;
dec_del_ctl_msff_ctl_macro__width_1 sffavorf  (
 .scan_in(sffavorf_scanin),
 .scan_out(sffavorf_scanout),
 .l1clk(l1clk),
 .din  (sffavor_in),
 .dout (sffavor),
  .siclk(siclk),
  .soclk(soclk)
);

// remember mult request; not flushable
assign mult_request_in = (spu_mult_request & (~mult_request | (mult_request & dec_spu_grant_d))) | 
		         (mult_request & ~dec_spu_grant_d);

dec_del_ctl_msff_ctl_macro__width_1 mulrequestf  (
 .scan_in(mulrequestf_scanin),
 .scan_out(mulrequestf_scanout),
 .l1clk(l1clk),
 .din  (mult_request_in),
 .dout (mult_request),
  .siclk(siclk),
  .soclk(soclk)
);

// if you have crypto mult case and crypto mult is not favored; it must wait for cmfavor bit to toggle

// harden for illegals
assign crypto_mult_case0 = (mult_request & fgusel0_d & fgu0_d & dec_valid0_d);
assign crypto_mult_case1 = (mult_request & ~fgusel0_d & fgu1_d & dec_valid1_d);

// if the core wins; favor the crypto multiply next time
assign set_cmfavor = (dec_decode0_d & crypto_mult_case0) |
		     (dec_decode1_d & crypto_mult_case1);

// reset the cmfavor bit if you win it clean
assign reset_cmfavor = (cmfavor & cmfavor_grant_d & (crypto_mult_case0 | crypto_mult_case1));

// grant the mult_request if you are favored or ~favored but nothing else wants the fgu
// have we covered all things that want the fgu ????
// never grant spu if second cycle of a pdist
// never grant spu if we are doing a block store
// dont give spu_grant if fgu has created an idiv hole in the pipe

assign idiv_hole_d = |idiv_stall_d[1:0];

assign cmfavor_grant_d =  mult_request & ~idiv_hole_d & ~pdistblock_d & 
				    ~(block_store_stall | pre_block_store_stall);

assign dec_spu_grant_d = (cmfavor & cmfavor_grant_d) |
		        (~cmfavor & mult_request & ~idiv_hole_d & ~crypto_mult_case0 & 
                                    ~crypto_mult_case1 & ~pdistblock_d & 
				    ~(block_store_stall | pre_block_store_stall)); 

assign dec_spu_grant_fgu_d = dec_spu_grant_d; // clone copy to fgu

assign cmfavor_in = (cmfavor | set_cmfavor) & ~reset_cmfavor;

dec_del_ctl_msff_ctl_macro__width_1 cmfavorf  (
 .scan_in(cmfavorf_scanin),
 .scan_out(cmfavorf_scanout),
 .l1clk(l1clk),
 .din  (cmfavor_in),
 .dout (cmfavor),
  .siclk(siclk),
  .soclk(soclk)
);

// harden for illegals
assign pdistblock_in[1:0] = 	{ (pdist1_d & ~fgusel0_d & dec_decode1_d),
			          (pdist0_d &  fgusel0_d & dec_decode0_d) };

dec_del_ctl_msff_ctl_macro__width_2 pdistblockf  (
 .scan_in(pdistblockf_scanin),
 .scan_out(pdistblockf_scanout),
 .l1clk(l1clk),
 .din  (pdistblock_in[1:0]),
 .dout (pdistblock[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// pdist from either thread group
assign pdistblock_d = |pdistblock[1:0];

// remember the rd of the pdist
dec_del_ctl_msff_ctl_macro__width_5 pdistrdf  (
 .scan_in(pdistrdf_scanin),
 .scan_out(pdistrdf_scanout),
 .l1clk(l1clk),
 .din  (dec_frf_w_addr_d[4:0]),
 .dout (pdist_rd[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_3 pdisttidf  (
 .scan_in(pdisttidf_scanin),
 .scan_out(pdisttidf_scanout),
 .l1clk(l1clk),
 .din  (dec_fgu_tid_d[2:0]),
 .dout (pdist_tid[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// STD blocks on the second cycle
// STD is atomic; both reads are back-to-back
assign twocycle0_d_in = (twocycle0_d & dec_decode0_d);

dec_del_ctl_msff_ctl_macro__width_1 twocycle0_df  (
 .scan_in(twocycle0_df_scanin),
 .scan_out(twocycle0_df_scanout),
 .l1clk(l1clk),
 .din  (twocycle0_d_in),
 .dout (twocycle0_stall),
  .siclk(siclk),
  .soclk(soclk)
);

assign twocycle1_d_in = (twocycle1_d & dec_decode1_d);

dec_del_ctl_msff_ctl_macro__width_1 twocycle1_df  (
 .scan_in(twocycle1_df_scanin),
 .scan_out(twocycle1_df_scanout),
 .l1clk(l1clk),
 .din  (twocycle1_d_in),
 .dout (twocycle1_stall),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in assert -var (~(twocycle0_stall & twocycle1_stall)) -message "twocycle0_stall and twocycle1_stall must be mutually exclusive"

assign twocycle_p[1:0] = { twocycle1_d_in, twocycle0_d_in };

// create a "hole" for integer ops executed by the fgu
assign int_hole0_in = (fgu0_d & idest0_d & dec_decode0_d) | idiv_stall_d[0];

dec_del_ctl_msff_ctl_macro__width_3 inthole0_df  (
 .scan_in(inthole0_df_scanin),
 .scan_out(inthole0_df_scanout),
 .l1clk(l1clk),
 .din  ({int_hole0_in,int_hole0_stall[2:1]}),
 .dout (int_hole0_stall[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign int_hole1_in = (fgu1_d & idest1_d & dec_decode1_d) | idiv_stall_d[1];

dec_del_ctl_msff_ctl_macro__width_3 inthole1_df  (
 .scan_in(inthole1_df_scanin),
 .scan_out(inthole1_df_scanout),
 .l1clk(l1clk),
 .din  ({int_hole1_in,int_hole1_stall[2:1]}),
 .dout (int_hole1_stall[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_3 divstall_df  (
 .scan_in(divstall_df_scanin),
 .scan_out(divstall_df_scanout),
 .l1clk(l1clk),
 .din  ({fgu_idiv_stall[1:0],fgu_fdiv_stall}),
 .dout ({idiv_stall_d[1:0],fdiv_stall_d}),
  .siclk(siclk),
  .soclk(soclk)
);

assign window_stall_in[1:0] = { exu1_window_block | tlu_window_block[1],
	  		        exu0_window_block | tlu_window_block[0] };
dec_del_ctl_msff_ctl_macro__width_2 windowstall_df  (
 .scan_in(windowstall_df_scanin),
 .scan_out(windowstall_df_scanout),
 .l1clk(l1clk),
 .din  (window_stall_in[1:0]),
 .dout (window_stall_d[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// clken signals for the exu
// not sure about window_stall; leave it out for now

assign exu_clken_in[1:0] = { valid1_d_in | test_stall1_in | twocycle1_d_in | ~lsu_exu_pmen,
			     valid0_d_in | test_stall0_in | twocycle0_d_in | ~lsu_exu_pmen};

dec_del_ctl_msff_ctl_macro__width_2 exu_clkenf  (
 .scan_in(exu_clkenf_scanin),
 .scan_out(exu_clkenf_scanout),
 .l1clk(l1clk),
 .din  (exu_clken_in[1:0]),
 .dout (dec_exu_clken[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);


//
// for legal insts, this can only happen for stores
//
assign lsu_float_case = fgu0_d & lsu0_d & fgu1_d & lsu1_d; 

// pdist bug
// second beat of a pdist can cause an ECC exception; can't let any other op for that TG down the pipe;
// use pdistblock[] to make this happen
// for second beat of a pdist, no fgu op can go from either TG; use pdistblock_d to make this happen


// two STDs can come the same cycle but never do we have twocycle0_stall and twocycle1_stall at the same time
// better block0 would be twocycle0_stall | (twocycle1_stall & twocycle0_d)

// only a block if the other one is valid
assign block0 = (dec_valid1_d & lsu0_d & lsu1_d & lfavor & ~lsu_float_case) |
		(dec_valid1_d & fgu0_d & fgu1_d & ffavor & ~lsu_float_case) |
		(dec_valid1_d & lsu_float_case & sffavor) |
		(fgu0_d & (pdistblock_d | (cmfavor & mult_request) | fecc_stall)) |
		(lsu0_d & (cpq_stall | dtlb_reload_stall)) |
	        (block_store_stall0 | (block_store_stall1 & (lsu0_d | fgu0_d))) |
	        (twocycle0_stall | (twocycle1_stall & lsu0_d)) |  // twocycles can appear at decode0,1 at the same time
                pdistblock[0] |
		((|idiv_stall_d[1:0]) & fgu0_d & idest0_d) |    // hole for common fgu result bus 
		int_hole0_stall[0] |				// hole for int ops executed by fgu (irf write port)
		(fdiv_stall_d & lsu0_d & fdest0_d) |		// hole for frf write port (no load-float)
		window_stall_d[0] |
		power_stall[0] |
		test_stall0;


assign dec_decode0_d = dec_valid0_d & ~block0;

assign del_noshift0_d = dec_valid0_d & ~dec_decode0_d;

assign block1 = (dec_valid0_d & lsu0_d & lsu1_d & ~lfavor & ~lsu_float_case) |
		(dec_valid0_d & fgu0_d & fgu1_d & ~ffavor & ~lsu_float_case) |
		(dec_valid0_d & lsu_float_case & ~sffavor) |
		(fgu1_d & (pdistblock_d | (cmfavor & mult_request) | fecc_stall)) |
		(lsu1_d & (cpq_stall | dtlb_reload_stall)) |
	        (block_store_stall1 | (block_store_stall0 & (lsu1_d | fgu1_d))) |
	        (twocycle1_stall | (twocycle0_stall & lsu1_d)) |
		pdistblock[1] |
		((|idiv_stall_d[1:0]) & fgu1_d & idest1_d) |	// hole for common fgu result bus
		int_hole1_stall[0] |				// hole for int ops executed by fgu (irf write port)
		(fdiv_stall_d & lsu1_d & fdest1_d) |		// hole for frf write port (no load-float)
		window_stall_d[1] |
		power_stall[0] |	
		test_stall1;


assign dec_decode1_d = dec_valid1_d & ~block1;

assign del_noshift1_d = dec_valid1_d & ~dec_decode1_d;

dec_del_ctl_msff_ctl_macro__width_2 legal_f  (
 .scan_in(legal_f_scanin),
 .scan_out(legal_f_scanout),
 .l1clk(l1clk),
 .din  (ded_legal_p[1:0]),
 .dout (legal_d[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);


// 0in assert -var (~(idest0_d & fdest0_d & dec_valid0_d & dec_decode0_d)) -message "idest0_d and fdest0_d should be mutually exclusive"
// 0in assert -var (~(idest1_d & fdest1_d & dec_valid1_d & dec_decode1_d)) -message "idest1_d and fdest1_d should be mutually exclusive"


assign illegal0_d = (~legal_d[0] | (dcd_wrtick_d[0] & ~hpriv_d[0])) & ~ifetch_err_d[0];
assign illegal1_d = (~legal_d[1] | (dcd_wrtick_d[1] & ~hpriv_d[1])) & ~ifetch_err_d[1];


assign dec_ierr_d[1:0] = {   ~legal_d[1] | perr_d[1] | ifetch_err_d[1],
		      	     ~legal_d[0] | perr_d[0] | ifetch_err_d[0] };


// write tick in priv mode then it is illegal_instruction trap
assign illegal_d[1:0] = {dec_decode1_d & illegal1_d, 
			 dec_decode0_d & illegal0_d};

dec_del_ctl_msff_ctl_macro__width_2 illegal_f  (
 .scan_in(illegal_f_scanin),
 .scan_out(illegal_f_scanout),
 .l1clk(l1clk),
 .din  (illegal_d[1:0]),
 .dout (illegal_e[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign fpdisable_exc_d[1:0] =    {dec_decode1_d & ~ifetch_err_d[1] & dcd_fpdisable_d[1] & fpdis_d[1], 
	 		          dec_decode0_d & ~ifetch_err_d[0] & dcd_fpdisable_d[0] & fpdis_d[0]};

dec_del_ctl_msff_ctl_macro__width_2 fpdisable_exc_f  (
 .scan_in(fpdisable_exc_f_scanin),
 .scan_out(fpdisable_exc_f_scanout),
 .l1clk(l1clk),
 .din  (fpdisable_exc_d[1:0]),
 .dout (fpdisable_exc_e[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// only a priv exception if not hypervisor 
// 00 user
// 01 priv
// 1- hyper

// write tick in user mode then its a privileged_opcode trap
// there was a  bug in dcd_wrtick_d in the presence of an illegal - can it happen now?
assign priv_exc_d[1:0] =  {dec_decode1_d & ~ifetch_err_d[1] & ((dcd_priv_d[1] & ~priv_d[1] & ~hpriv_d[1]) | (dcd_wrtick_d[1] & ~priv_d[1] & ~hpriv_d[1])), 
			   dec_decode0_d & ~ifetch_err_d[0] & ((dcd_priv_d[0] & ~priv_d[0] & ~hpriv_d[0]) | (dcd_wrtick_d[0] & ~priv_d[0] & ~hpriv_d[0]))};

assign hpriv_exc_d[1:0] =  {dec_decode1_d & ~ifetch_err_d[1] & dcd_hpr_d[1] & ~hpriv_d[1], 
                            dec_decode0_d & ~ifetch_err_d[0] & dcd_hpr_d[0] & ~hpriv_d[0]};


dec_del_ctl_msff_ctl_macro__width_2 parity_err_f  (
 .scan_in(parity_err_f_scanin),
 .scan_out(parity_err_f_scanout),
 .l1clk(l1clk),
 .din  (ded_perr_p[1:0]),
 .dout (perr_d[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign icdp_perr_d[1:0] = {dec_decode1_d & perr_d[1],
	   		   dec_decode0_d & perr_d[0] };

dec_del_ctl_msff_ctl_macro__width_6 exc_f  (
 .scan_in(exc_f_scanin),
 .scan_out(exc_f_scanout),
 .l1clk(l1clk),
 .din  ({priv_exc_d[1:0],hpriv_exc_d[1:0],icdp_perr_d[1:0]}),
 .dout ({priv_exc_e[1:0],hpriv_exc_e[1:0],icdp_perr_e[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


assign ffavor_real = (~lsu_float_case & ffavor) | (lsu_float_case & sffavor);
assign lfavor_real = (~lsu_float_case & lfavor) | (lsu_float_case & sffavor);

assign fgusel0_d = ~ffavor_real & fgu0_d & dec_valid0_d | (ffavor_real & ~(fgu1_d & dec_valid1_d));

assign fguselect_d[0] =  fgusel0_d & dec_fgu_decode_d;
assign fguselect_d[1] = ~fgusel0_d & dec_fgu_decode_d;

// force this select to the right value for each STD in TG0 or 1
assign lsusel0_d = ((~lfavor_real & lsu0_d & dec_valid0_d | (lfavor_real & ~(lsu1_d & dec_valid1_d))) & ~twocycle1_stall) | twocycle0_stall;

// to the pmu to decide which tid to use for lsu at d stage
assign dec_lsu_sel0_d = lsusel0_d; 

dec_del_ctl_msff_ctl_macro__width_4 tgsel_f  (
 .scan_in(tgsel_f_scanin),
 .scan_out(tgsel_f_scanout),
 .l1clk(l1clk),
 .din  ({fguselect_d[1:0],twocycle0_stall,twocycle1_stall}),
 .dout ({dec_fgu_sel_e[1:0],twocycle0_stall_e,twocycle1_stall_e}),
  .siclk(siclk),
  .soclk(soclk)
);


// 0in value -var {dec_lsu_sel0_e,dec_lsu_sel1_e} -val 0 1 2 -message "{dec_lsu_sel0_e,dec_lsu_sel1_e} are mutually exclusive"

// can be off a flop if needed for timing
assign dec_lsu_sel0_e = decode_lsu0_e | twocycle0_stall_e;
assign dec_lsu_sel1_e = decode_lsu1_e | twocycle1_stall_e;

// put a little logic on the pstate_am signals (more flops if it doesn't make timing)
assign pstate_am_in[1:0] = { |(tlu_pstate_am[7:4] & pick1_d[3:0]), |(tlu_pstate_am[3:0] & pick0_d[3:0]) };


assign rs1_addr0_d       =  decode_lsu0_d &  casa_or_pst_d;
assign rs1_addr1_d       =  decode_lsu1_d &  casa_or_pst_d;
       
assign lsu_sel0_lower_d  =  decode_lsu0_d & ~casa_or_pst_d;
assign lsu_sel1_lower_d  =  decode_lsu1_d & ~casa_or_pst_d;


// quiet down these selects by using decode_lsu

assign lsu_sel0_upper_d  =  decode_lsu0_d & ~casa_or_pst_d & ~pstate_am_in[0];
assign lsu_sel1_upper_d  =  decode_lsu1_d & ~casa_or_pst_d & ~pstate_am_in[1];
       
assign rs1_addr0_upper_d =  decode_lsu0_d &  casa_or_pst_d & ~pstate_am_in[0];
assign rs1_addr1_upper_d =  decode_lsu1_d &  casa_or_pst_d & ~pstate_am_in[1];


// flop the selects to the exu for timing

dec_del_ctl_msff_ctl_macro__width_8 exuself  (
 .scan_in(exuself_scanin),
 .scan_out(exuself_scanout),
 .l1clk(l1clk),
 .din  ({ rs1_addr0_d, rs1_addr1_d, lsu_sel0_lower_d, lsu_sel1_lower_d, 
		lsu_sel0_upper_d, lsu_sel1_upper_d, rs1_addr0_upper_d, rs1_addr1_upper_d}),

 .dout ({ dec_rs1_addr0_e, dec_rs1_addr1_e, dec_lsu_sel0_lower_e, dec_lsu_sel1_lower_e, 
		dec_lsu_sel0_upper_e, dec_lsu_sel1_upper_e, dec_rs1_addr0_upper_e, dec_rs1_addr1_upper_e}),
  .siclk(siclk),
  .soclk(soclk)
);


// next 4 must be mutually exclusive (but not 1-hot)

// 0in value -var {dec_rs1_addr0_e,dec_rs1_addr1_e,dec_lsu_sel0_lower_e,dec_lsu_sel1_lower_e} -val 0 1 2 4 8 -message "{dec_rs1_addr0_e,dec_rs1_addr1_e,dec_lsu_sel0_lower_e,dec_lsu_sel1_lower_e} are mutually exclusive"

// next 4 are mutually exclusive (but not 1-hot)

// 0in value -var {dec_lsu_sel0_upper_e,dec_lsu_sel1_upper_e,dec_rs1_addr0_upper_e,dec_rs1_addr1_upper_e} -val 0 1 2 4 8 -message "{dec_lsu_sel0_upper_e,dec_lsu_sel1_upper_e,dec_rs1_addr0_upper_e,dec_rs1_addr1_upper_e} are mutually exclusive"


dec_del_ctl_msff_ctl_macro__width_2 tgselm_f  (
 .scan_in(tgselm_f_scanin),
 .scan_out(tgselm_f_scanout),
 .l1clk(l1clk),
 .din  (dec_fgu_sel_e[1:0]),
 .dout (dec_fgu_sel_m[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// generate interface needed by the fgu

assign store_float[0] = fsrc0_rd_d & fgu0_d;
assign store_float[1] = fsrc1_rd_d & fgu1_d;

// remap the integer destinations

assign i0_rd[4:0] = dec_inst0_raw_rd_d[4:0];
assign i1_rd[4:0] = dec_inst1_raw_rd_d[4:0];

assign i0_rd_remap_d[4:0] = ({5{idest0_d}} & {i0_rd[4] ^ (i0_rd[3] & (ded_oddwin0_d ^ dcd_save_restore_d[0])), i0_rd[3:0]}) |
		            ({5{~idest0_d}} & i0_rd[4:0]);

assign i1_rd_remap_d[4:0] = ({5{idest1_d}} & {i1_rd[4] ^ (i1_rd[3] & (ded_oddwin1_d ^ dcd_save_restore_d[1])), i1_rd[3:0]}) |
		            ({5{~idest1_d}} & i1_rd[4:0]);

assign dec_irf_w_addr_d[4:0] = ({5{fgusel0_d}} & i0_rd_remap_d[4:0]) |
		               ({5{~fgusel0_d}} & i1_rd_remap_d[4:0]);

// munge the address to always be double precision for fgu sources, dest
assign f0_rs1[4:0] = ({5{dcd_fp_rs1_single_d[0]}} & {1'b0,dec_inst0_rs1_d[4:1]}) |
		     ({5{~dcd_fp_rs1_single_d[0]}} & {dec_inst0_rs1_d[0],dec_inst0_rs1_d[4:1]});

assign f0_rs2[4:0] = ({5{dcd_fp_rs2_single_d[0]}} & {1'b0,dec_inst0_rs2_d[4:1]}) |
		     ({5{~dcd_fp_rs2_single_d[0]}} & {dec_inst0_rs2_d[0],dec_inst0_rs2_d[4:1]});

assign f0_rd[4:0] = ({5{dcd_fpdest_single_d[0]}} & {1'b0,dec_inst0_raw_rd_d[4:1]}) |
		    ({5{~dcd_fpdest_single_d[0]}} & {dec_inst0_raw_rd_d[0],dec_inst0_raw_rd_d[4:1]});

assign f1_rs1[4:0] = ({5{dcd_fp_rs1_single_d[1]}} & {1'b0,dec_inst1_rs1_d[4:1]}) |
		     ({5{~dcd_fp_rs1_single_d[1]}} & {dec_inst1_rs1_d[0],dec_inst1_rs1_d[4:1]});

assign f1_rs2[4:0] = ({5{dcd_fp_rs2_single_d[1]}} & {1'b0,dec_inst1_rs2_d[4:1]}) |
		     ({5{~dcd_fp_rs2_single_d[1]}} & {dec_inst1_rs2_d[0],dec_inst1_rs2_d[4:1]});

assign f1_rd[4:0] = ({5{dcd_fpdest_single_d[1]}} & {1'b0,dec_inst1_raw_rd_d[4:1]}) |
		    ({5{~dcd_fpdest_single_d[1]}} & {dec_inst1_raw_rd_d[0],dec_inst1_raw_rd_d[4:1]});


assign dec_frf_r1_addr_d[4:0] = ({5{fgusel0_d}} & f0_rs1[4:0]) |
				({5{~fgusel0_d}} & f1_rs1[4:0]);

assign inst0_rs2[4:0] = ({5{store_float[0]}} & f0_rd[4:0]) |
			({5{~store_float[0]}} & f0_rs2[4:0]);

assign inst1_rs2[4:0] = ({5{store_float[1]}} & f1_rd[4:0]) |
			({5{~store_float[1]}} & f1_rs2[4:0]);

assign dec_frf_r2_addr_d[4:0] = ({5{block_store_stall}} & block_store_rd[4:0]) |
				({5{~block_store_stall & pdistblock_d}} & pdist_rd[4:0]) |
				({5{~block_store_stall & fgusel0_d & ~pdistblock_d}} & inst0_rs2[4:0]) |
				({5{~block_store_stall & ~fgusel0_d & ~pdistblock_d}} & inst1_rs2[4:0]);
				
// Flop for LSU
dec_del_ctl_msff_ctl_macro__width_2 frf_r2addre_f  (
 .scan_in(frf_r2addre_f_scanin),
 .scan_out(frf_r2addre_f_scanout),
 .l1clk(l1clk),
 .din  (dec_frf_r2_addr_d[4:3]),
 .dout (dec_frf_r2_addr_e[4:3]),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_frf_w_addr_d[4:0] = ({5{ fgusel0_d}} & f0_rd[4:0]) |
			       ({5{~fgusel0_d}} & f1_rd[4:0]);

assign dec_frf_r1_vld_d = ((fgu0_d & dec_decode0_d & fgusel0_d & dcd_fsrc_rs1_d[0]) |
			   (fgu1_d & dec_decode1_d & ~fgusel0_d & dcd_fsrc_rs1_d[1])) & ~pdistblock_d & ~block_store_stall;

assign dec_frf_r2_vld_d = (fgu0_d & dec_decode0_d & fgusel0_d & (dcd_fsrc_rs2_d[0] | store_float[0])) | 
			  (fgu1_d & dec_decode1_d & ~fgusel0_d & (dcd_fsrc_rs2_d[1] | store_float[1])) |
			   pdistblock_d | block_store_stall;

assign dec_frf_w_vld_d =  ( fgusel0_d & (fdest0_d & ~pdistblock_d)) |
			  (~fgusel0_d & (fdest1_d & ~pdistblock_d));

assign dec_frf_r1_32b_d = ( fgusel0_d & dcd_fp_rs1_single_d[0]) |
		          (~fgusel0_d & dcd_fp_rs1_single_d[1]);

assign dec_frf_r2_32b_d = ( fgusel0_d & dcd_fp_rs2_single_d[0] & ~pdistblock_d & ~block_store_stall) |
		          (~fgusel0_d & dcd_fp_rs2_single_d[1] & ~pdistblock_d & ~block_store_stall);

assign dec_frf_r1_odd32b_d = ( fgusel0_d & dcd_fp_rs1_single_d[0] & dec_inst0_rs1_d[0]) |
			     (~fgusel0_d & dcd_fp_rs1_single_d[1] & dec_inst1_rs1_d[0]);

// before the munge
assign inst0_rs2_raw_bit0 = (store_float[0] & dec_inst0_raw_rd_d[0]) |
			    (~store_float[0] & dec_inst0_rs2_d[0]);

assign inst1_rs2_raw_bit0 = (store_float[1] & dec_inst1_raw_rd_d[0]) |
			    (~store_float[1] & dec_inst1_rs2_d[0]);

assign dec_frf_r2_odd32b_d = (fgusel0_d & dcd_fp_rs2_single_d[0] & inst0_rs2_raw_bit0 & ~pdistblock_d & ~block_store_stall) |
			      (~fgusel0_d & dcd_fp_rs2_single_d[1] & inst1_rs2_raw_bit0 & ~pdistblock_d & ~block_store_stall);

assign dec_frf_w_32b_d = (fgusel0_d & dcd_fpdest_single_d[0]) |
			 (~fgusel0_d & dcd_fpdest_single_d[1]);

assign dec_frf_w_odd32b_d = (fgusel0_d & dcd_fpdest_single_d[0] & dec_inst0_raw_rd_d[0]) |
			    (~fgusel0_d & dcd_fpdest_single_d[1] & dec_inst1_raw_rd_d[0]);

assign dec_exu_src_vld_d = (fgusel0_d & dcd_exu_src_d[0] & ~pdistblock_d & ~block_store_stall) |
			  (~fgusel0_d & dcd_exu_src_d[1] & ~pdistblock_d & ~block_store_stall); 

assign dec_frf_store_d = (fgusel0_d & store_float[0] & ~pdistblock_d) |
			 (~fgusel0_d & store_float[1] & ~pdistblock_d) |
			 block_store_stall; 

assign fsr_store0 =  dcd_store_d[0] & dcd_fsrsync_d[0];
assign fsr_store1 =  dcd_store_d[1] & dcd_fsrsync_d[1];

assign dec_fsr_store_d = (fgusel0_d & fsr_store0 & ~pdistblock_d & ~block_store_stall) |
			  (~fgusel0_d & fsr_store1 & ~pdistblock_d & ~block_store_stall); 


assign dec_fgu_op3_d[5:0] = ({6{fgusel0_d}} & dec_inst0_op3_d[5:0]) |
			    ({6{~fgusel0_d}} & dec_inst1_op3_d[5:0]);

assign dec_fgu_opf_d[7:0] = ({8{fgusel0_d}} & dec_inst0_opf_d[7:0]) |
			    ({8{~fgusel0_d}} & dec_inst1_opf_d[7:0]);


// dont fire if a lsu op unless it is a store-float (including stfsr)
// harden for illegals
assign dec_fgu_decode_d = (dec_decode0_d & fgusel0_d & fgu0_d & ~(lsu0_d & ~fgu0_d)) |
		          (dec_decode1_d & ~fgusel0_d & fgu1_d & ~(lsu1_d & ~fgu1_d)) |
			   block_store_stall;
// .i 4
// .o 2
// .ilb p[3] p[2] p[1] p[0]
// .ob tid[1] tid[0]
// .type fr
// 0001 00
// 0010 01
// 0100 10
// 1000 11

assign tid0_d[1] = ~pick0_d[1] & ~pick0_d[0];
assign tid0_d[0] = ~pick0_d[2] & ~pick0_d[0];

assign tid1_d[1] = ~pick1_d[1] & ~pick1_d[0];
assign tid1_d[0] = ~pick1_d[2] & ~pick1_d[0];

assign dec_tid0_d[1:0] = tid0_d[1:0];
assign dec_tid1_d[1:0] = tid1_d[1:0];

assign dec_fgu_tid_d[2:0] = ({3{block_store_stall}} & block_store_tid[2:0]) |
			    ({3{~block_store_stall &  pdistblock_d}} & pdist_tid[2:0]) |
		            ({3{~block_store_stall &  fgusel0_d & ~pdistblock_d}} & {1'b0,tid0_d[1:0]}) |
			    ({3{~block_store_stall & ~fgusel0_d & ~pdistblock_d}} & {1'b1,tid1_d[1:0]});

// 0in value -var pku_flush_f1[7:0] -val 0 1 2 4 8 16 32 64 128 
// 0in value -var pku_flush_f2[7:0] -val 0 1 2 4 8 16 32 64 128 
// 0in value -var pku_flush_lm[7:0] -val 0 1 2 4 8 16 32 64 128 
// 0in value -var pku_flush_lb[7:0] -val 0 1 2 4 8 16 32 64 128 

assign dec_flush_f1 = |pku_flush_f1[7:0];
assign dec_flush_f2 = |pku_flush_f2[7:0];

// Must flush lsu instructions which cause fp_disabled or priv or hpriv exc
assign dec_flush_lm = (|pku_flush_lm[7:0]) | flush_lexc_m;
assign dec_flush_lb = |pku_flush_lb[7:0];

// 0in value -var pku_flush_m[7:4] -val 0 1 2 4 8 
// 0in value -var pku_flush_m[3:0] -val 0 1 2 4 8 

assign dec_flush_m[1] = |pku_flush_m[7:4];
assign dec_flush_m[0] = |pku_flush_m[3:0];

// 0in value -var pku_flush_b[7:4] -val 0 1 2 4 8 
// 0in value -var pku_flush_b[3:0] -val 0 1 2 4 8 

assign dec_flush_b[1] = |pku_flush_b[7:4];
assign dec_flush_b[0] = |pku_flush_b[3:0];


dec_del_ctl_msff_ctl_macro__width_2 ifetch_err_f  (
 .scan_in(ifetch_err_f_scanin),
 .scan_out(ifetch_err_f_scanout),
 .l1clk(l1clk),
 .din  (ded_ferr_p[1:0]),
 .dout (ifetch_err_d[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_2 ifetcherr_f  (
 .scan_in(ifetcherr_f_scanin),
 .scan_out(ifetcherr_f_scanout),
 .l1clk(l1clk),
 .din  (ifetch_err_d[1:0]),
 .dout (ifetch_err_e[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);
			

assign true_valid_d[0] = ~illegal_d[0] & ~priv_exc_d[0] & ~hpriv_exc_d[0] & ~fpdisable_exc_d[0] & ~icdp_perr_d[0] & ~ifetch_err_d[0];
assign true_valid_d[1] = ~illegal_d[1] & ~priv_exc_d[1] & ~hpriv_exc_d[1] & ~fpdisable_exc_d[1] & ~icdp_perr_d[1] & ~ifetch_err_d[1];

// don't let exceptions into the machine
dec_del_ctl_msff_ctl_macro__width_2 truevalid_f  (
 .scan_in(truevalid_f_scanin),
 .scan_out(truevalid_f_scanout),
 .l1clk(l1clk),
 .din  (true_valid_d[1:0]),
 .dout (dec_true_valid_e[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// pmu eco; dont qualify valids with ifetch_err[1:0] so itlb misses will be counted
assign illegal0_pmu_d = (~legal_d[0] | (dcd_wrtick_d[0] & ~hpriv_d[0])) & ~ifetch_err_d[0];  // add this to gates, missing
assign illegal1_pmu_d = (~legal_d[1] | (dcd_wrtick_d[1] & ~hpriv_d[1])) & ~ifetch_err_d[1];


// write tick in priv mode then it is illegal_instruction trap
assign illegal_pmu_d[1:0] = {dec_decode1_d & illegal1_pmu_d, 
		   	     dec_decode0_d & illegal0_pmu_d};

assign priv_exc_pmu_d[1:0] =  {dec_decode1_d & ~ifetch_err_d[1] & ((dcd_priv_d[1] & ~priv_d[1] & ~hpriv_d[1]) | (dcd_wrtick_d[1] & ~priv_d[1] & ~hpriv_d[1])), 
			       dec_decode0_d & ~ifetch_err_d[0] & ((dcd_priv_d[0] & ~priv_d[0] & ~hpriv_d[0]) | (dcd_wrtick_d[0] & ~priv_d[0] & ~hpriv_d[0]))};

assign hpriv_exc_pmu_d[1:0] =  {dec_decode1_d & dcd_hpr_d[1] & ~hpriv_d[1], 
                                dec_decode0_d & dcd_hpr_d[0] & ~hpriv_d[0]};


assign fpdisable_exc_pmu_d[1:0] =    {dec_decode1_d & dcd_fpdisable_d[1] & fpdis_d[1], 
	 		              dec_decode0_d & dcd_fpdisable_d[0] & fpdis_d[0]};

assign pmu_valid_d[0] = ~illegal_pmu_d[0] & ~priv_exc_pmu_d[0] & ~hpriv_exc_pmu_d[0] & ~fpdisable_exc_pmu_d[0] & ~icdp_perr_d[0];

assign pmu_valid_d[1] = ~illegal_pmu_d[1] & ~priv_exc_pmu_d[1] & ~hpriv_exc_pmu_d[1] & ~fpdisable_exc_pmu_d[1] & ~icdp_perr_d[1];

// use spare flops (see above)

assign dec_pmu_valid_e[0] = valid_e[0] & pmu_valid_e[0];
assign dec_pmu_valid_e[1] = valid_e[1] & pmu_valid_e[1];
// end pmu eco

// 0in value -var pku_valid_e[7:4] -val 0 1 2 4 8 
// 0in value -var pku_valid_e[3:0] -val 0 1 2 4 8 

assign valid_e[0] = |pku_valid_e[3:0];
assign valid_e[1] = |pku_valid_e[7:4];

assign dec_valid_e[0] = valid_e[0] & dec_true_valid_e[0];
assign dec_valid_e[1] = valid_e[1] & dec_true_valid_e[1];

// Must send lsu_valid even when fpdisabled or priv or hpriv excs
assign ls_valid_e[0] = valid_e[0] & ~illegal_e[0] &  ~icdp_perr_e[0] & ~ifetch_err_e[0];
assign ls_valid_e[1] = valid_e[1] & ~illegal_e[1] &  ~icdp_perr_e[1] & ~ifetch_err_e[1];

// never fire dec_fgu_valid_e for a lsu operation

// harden for illegals
assign decode_fgu0_d = dec_decode0_d & fgusel0_d & fgu0_d & ~lsu0_d & ~dcd_killfgu_d[0];
assign decode_fgu1_d = dec_decode1_d & ~fgusel0_d & fgu1_d & ~lsu1_d & ~dcd_killfgu_d[1];

dec_del_ctl_msff_ctl_macro__width_2 fgudec_f  (
 .scan_in(fgudec_f_scanin),
 .scan_out(fgudec_f_scanout),
 .l1clk(l1clk),
 .din  ({decode_fgu0_d,decode_fgu1_d}),
 .dout ({decode_fgu0_e,decode_fgu1_e}),
  .siclk(siclk),
  .soclk(soclk)
);

// fgu operation at e and it is not a lsu operation
assign dec_fgu_valid_e = (decode_fgu0_e & dec_valid_e[0]) |
			 (decode_fgu1_e & dec_valid_e[1]);

// harden for illegals
assign decode_lsu0_d = dec_decode0_d & lsusel0_d & lsu0_d;
assign decode_lsu1_d = dec_decode1_d & ~lsusel0_d & lsu1_d;

dec_del_ctl_msff_ctl_macro__width_2 lsudec_f  (
 .scan_in(lsudec_f_scanin),
 .scan_out(lsudec_f_scanout),
 .l1clk(l1clk),
 .din  ({decode_lsu0_d,decode_lsu1_d}),
 .dout ({decode_lsu0_e,decode_lsu1_e}),
  .siclk(siclk),
  .soclk(soclk)
);


// lsu interface

// this bug is no longer valid since we gate off all decodes for an illegal instruction
//   wrong! if a parity error is present it can appear to be illegal ... harden the logic

// bug fix
// if illegal is in TG0 and a valid load is in TG1, then ld_inst_d can fire for TG0 and be misinterpreted by TG1 
// this case is for different threads and both decode same cycle
// add lsusel0_d to eliminate this case

assign dec_ld_inst_d = 	(dec_decode0_d & lsusel0_d & dcd_load_d[0]) |
			(dec_decode1_d & ~lsusel0_d & dcd_load_d[1]);


assign st_inst_d = 	(lsusel0_d & dcd_store_d[0]) |
			(~lsusel0_d & dcd_store_d[1]);

assign fsr_ldst_d = (lsusel0_d & dcd_fsrsync_d[0]) |
	            (~lsusel0_d & dcd_fsrsync_d[1]); 


dec_del_ctl_msff_ctl_macro__width_3 ldste_f  (
 .scan_in(ldste_f_scanin),
 .scan_out(ldste_f_scanout),
 .l1clk(l1clk),
 .din  ({dec_ld_inst_d,st_inst_d,fsr_ldst_d}),
 .dout ({ld_inst_e,st_inst_e,fsr_ldst_e}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_ld_inst_e =  ld_inst_e & lsu_valid_e;
assign dec_st_inst_e =  st_inst_e & lsu_valid_e;
assign dec_fsr_ldst_e =  fsr_ldst_e;

assign fpldst_d = 	(lsusel0_d &  (load_float0_d | store_float0_d)) |
		   	(~lsusel0_d & (load_float1_d | store_float1_d));

assign lsdouble_d = 	(lsusel0_d &  (dcd_load_d[0] | dcd_store_d[0]) & dcd_lsdouble_d[0]) |
		   	(~lsusel0_d & (dcd_load_d[1] | dcd_store_d[1]) & dcd_lsdouble_d[1]);

assign prefetch_d = 	(lsusel0_d & dcd_prefetch_d[0]) |
			(~lsusel0_d & dcd_prefetch_d[1]);

assign flush_d = 	(lsusel0_d & dcd_flush_d[0]) |
			(~lsusel0_d & dcd_flush_d[1]);

assign memstbar_d = 	(lsusel0_d & dcd_memstbar_d[0]) |
			(~lsusel0_d & dcd_memstbar_d[1]);

assign pr_d = 		(lsusel0_d & dcd_pr_d[0]) |
			(~lsusel0_d & dcd_pr_d[1]);

assign hpr_d = 		(lsusel0_d & dcd_hpr_d[0]) |
			(~lsusel0_d & dcd_hpr_d[1]);

assign sr_d = 		(lsusel0_d & dcd_sr_d[0]) |
			(~lsusel0_d & dcd_sr_d[1]);

// finish the decode of partial store
assign pst_d = 		(lsusel0_d & dcd_stdfa_d[0] & (dec_inst0_opf_d[7:4]==4'b1100) & (dec_inst0_opf_d[2:1] != 2'b11)) |
			(~lsusel0_d & dcd_stdfa_d[1] & (dec_inst1_opf_d[7:4]==4'b1100) & (dec_inst1_opf_d[2:1] != 2'b11));

assign casa_d = 	(lsusel0_d & dcd_casa_d[0]) |
			(~lsusel0_d & dcd_casa_d[1]);

assign ldstub_d = 	(lsusel0_d & dcd_ldstub_d[0]) |
			(~lsusel0_d & dcd_ldstub_d[1]);

assign swap_d = 	(lsusel0_d & dcd_swap_d[0]) |
			(~lsusel0_d & dcd_swap_d[1]);

// how to code 0in to find potential issues with illegals

// 0in assert -var (~(lsusel0_d & ~(dcd_alt_d[0] | dcd_alti_d[0]) & dec_altspace_d)) -message "unexpected dec_altspace_d for TG0"

// 0in assert -var (~(~lsusel0_d & ~(dcd_alt_d[1] | dcd_alti_d[1]) & dec_altspace_d)) -message "unexpected dec_altspace_d for TG1"

// add lsusel0_d for illegal case
assign dec_altspace_d = (dec_decode0_d &  lsusel0_d & (dcd_alt_d[0] | dcd_alti_d[0])) |
			(dec_decode1_d & ~lsusel0_d & (dcd_alt_d[1] | dcd_alti_d[1]));

assign altspacei_d = 	(lsusel0_d & dcd_alt_d[0]) |
			(~lsusel0_d & dcd_alt_d[1]);

assign sign_ext_d =	(lsusel0_d & dcd_lsu_sign_ext_d[0]) |
			(~lsusel0_d & dcd_lsu_sign_ext_d[1]);

assign lsize_d[1:0] =   ({2{lsusel0_d}} & dcd_lsize0_d[1:0]) |
			({2{~lsusel0_d}} & dcd_lsize1_d[1:0]);
   
			
assign dec_imm_asi_vld_d = altspacei_d;

assign casa_or_pst_d = (casa_d | pst_d);

dec_del_ctl_msff_ctl_macro__width_14 ldme_f  (
 .scan_in(ldme_f_scanin),
 .scan_out(ldme_f_scanout),
 .l1clk(l1clk),
 .din  ({ 	fpldst_d, lsdouble_d, prefetch_d, flush_d,
		memstbar_d, hpr_d, pr_d, sr_d, casa_d, ldstub_d, 
		swap_d, sign_ext_d, lsize_d[1:0]
	}),
 .dout  ({ 	fpldst_e, lsdouble_e, prefetch_e, flush_e,
		memstbar_e, hpr_e, pr_e, sr_e, casa_e, ldstub_e, 
		swap_e, sign_ext_e, lsize_e[1:0] 
	}),
  .siclk(siclk),
  .soclk(soclk)
);

// These don't need to be qualified.  They'll be used to qualify
// a valid load or store.  ML 10-26-04
assign dec_hpr_inst_e = hpr_e;
assign dec_pr_inst_e = pr_e;
assign dec_sr_inst_e = sr_e;
assign dec_ldst_sz_e[1:0] = lsize_e[1:0];
assign dec_ldst_dbl_e = lsdouble_e;
assign dec_casa_inst_e = casa_e;
assign dec_ldstub_inst_e = ldstub_e;
assign dec_swap_inst_e = swap_e;
assign dec_sign_ext_e = sign_ext_e;
assign dec_pref_inst_e = prefetch_e;
   
assign dec_fpldst_inst_e = fpldst_e & lsu_valid_e;
assign dec_flush_inst_e = flush_e & lsu_valid_e;
assign dec_memstbar_inst_e = memstbar_e & lsu_valid_e;

assign dec_imm_asi_d[7:0] =  	({8{lsusel0_d}} & dec_inst0_opf_d[7:0]) |
				({8{~lsusel0_d}} & dec_inst1_opf_d[7:0]);

assign sraddr_d[4:0] = 	({5{lsusel0_d}} & dec_inst0_rs1_d[4:0]) |
			({5{~lsusel0_d}} & dec_inst1_rs1_d[4:0]);

dec_del_ctl_msff_ctl_macro__width_5 sraddr_f  (
 .scan_in(sraddr_f_scanin),
 .scan_out(sraddr_f_scanout),
 .l1clk(l1clk),
 .din  (sraddr_d[4:0]),
 .dout (sraddr_e[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);
			
assign dec_sraddr_e[4:0] = sraddr_e[4:0];


// lsu has valid operation at e stage (take annul into account)
assign dec_lsu_tid0_d[1:0] = tid0_d[1:0];
assign dec_lsu_tid1_d[1:0] = tid1_d[1:0];
assign dec_lsu_tg_d = ~(~lfavor_real & lsu0_d & dec_valid0_d | (lfavor_real & ~(lsu1_d & dec_valid1_d)));


assign lsu_rd0_msb = (idest0_d & (dec_inst0_raw_rd_d[4] ^ (dec_inst0_raw_rd_d[3] & ded_oddwin0_d))) |
		     (~idest0_d & dec_inst0_raw_rd_d[4]);

assign lsu_rd1_msb = (idest1_d & (dec_inst1_raw_rd_d[4] ^ (dec_inst1_raw_rd_d[3] & ded_oddwin1_d))) |
		     (~idest1_d & dec_inst1_raw_rd_d[4]);

assign lsu_rd_d[4:0] = ({5{lsusel0_d}} & {lsu_rd0_msb,dec_inst0_raw_rd_d[3:0]}) |
		       ({5{~lsusel0_d}} & {lsu_rd1_msb,dec_inst1_raw_rd_d[3:0]}); 

dec_del_ctl_msff_ctl_macro__width_5 lsurd_f  (
 .scan_in(lsurd_f_scanin),
 .scan_out(lsurd_f_scanout),
 .l1clk(l1clk),
 .din  (lsu_rd_d[4:0]),
 .dout (lsu_rd_e[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// decode_lsu0_e, decode_lsu1_e are hardened for illegal cases
assign lsu_valid_e = (decode_lsu0_e & ls_valid_e[0]) |
	             (decode_lsu1_e & ls_valid_e[1]);

assign dec_lsu_rd_e[4:0] = lsu_rd_e[4:0];

// end lsu interface

assign ds_m_in[1:0] = { |pku_ds_e[7:4], |pku_ds_e[3:0]  } & ~ifetch_err_e[1:0];

dec_del_ctl_msff_ctl_macro__width_2 ds_m  (
 .scan_in(ds_m_scanin),
 .scan_out(ds_m_scanout),
 .l1clk(l1clk),
 .din  (ds_m_in[1:0]),
 .dout (dec_ds_m[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign annul_ds_dcti_e[7:4] = ({4{~br_taken_e[1]}} & pku_annul_ds_dcti_brtaken0_e[7:4]) |
			      ({4{ br_taken_e[1]}} & pku_annul_ds_dcti_brtaken1_e[7:4]);

assign annul_ds_dcti_e[3:0] = ({4{~br_taken_e[0]}} & pku_annul_ds_dcti_brtaken0_e[3:0]) |
			      ({4{ br_taken_e[0]}} & pku_annul_ds_dcti_brtaken1_e[3:0]);

assign annul_ds_m_in[1:0] = { |annul_ds_dcti_e[7:4], |annul_ds_dcti_e[3:0] } & ~ifetch_err_e[1:0];

dec_del_ctl_msff_ctl_macro__width_2 annul_m  (
 .scan_in(annul_m_scanin),
 .scan_out(annul_m_scanout),
 .l1clk(l1clk),
 .din  (annul_ds_m_in[1:0]),
 .dout (dec_annul_ds_m[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_4 tid_e  (
 .scan_in(tid_e_scanin),
 .scan_out(tid_e_scanout),
 .l1clk(l1clk),
 .din  ({tid1_d[1:0],tid0_d[1:0]}),
 .dout ({tid1_e[1:0],tid0_e[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_4 tid_m  (
 .scan_in(tid_m_scanin),
 .scan_out(tid_m_scanout),
 .l1clk(l1clk),
 .din  ({tid1_e[1:0],tid0_e[1:0]}),
 .dout ({dec_tid1_m[1:0],dec_tid0_m[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_2 dec_e  (
 .scan_in(dec_e_scanin),
 .scan_out(dec_e_scanout),
 .l1clk(l1clk),
 .din  ({dec_decode1_d,dec_decode0_d}),
 .dout ({decode1_raw_e,decode0_raw_e}),
  .siclk(siclk),
  .soclk(soclk)
);

// send illegals to trap unit
assign decode1_e = decode1_raw_e & valid_e[1];
assign decode0_e = decode0_raw_e & valid_e[0];

dec_del_ctl_msff_ctl_macro__width_2 dec_m  (
 .scan_in(dec_m_scanin),
 .scan_out(dec_m_scanout),
 .l1clk(l1clk),
 .din  ({decode1_e,decode0_e}),
 .dout (inst_valid_m[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_inst_valid_m[1:0] = { ~dec_flush_m[1] & inst_valid_m[1],
				 ~dec_flush_m[0] & inst_valid_m[0] };

assign store_float0_d = lsu0_d & fgu0_d;  	// only store-floats have both lsu and fgu asserted
assign load_float0_d = lsu0_d & fdest0_d; // load-float only has lsu asserted along with fdest

assign store_float1_d = lsu1_d & fgu1_d;
assign load_float1_d = lsu1_d & fdest1_d;

// fire this for all lsu ops and store-float
assign is_lsu1_d = lsu1_d & ~ifetch_err_d[1];
assign is_lsu0_d = lsu0_d & ~ifetch_err_d[0];

// fire this for all fgu ops and store-float
assign is_fgu1_d = fgu1_d & ~ifetch_err_d[1];
assign is_fgu0_d = fgu0_d & ~ifetch_err_d[0];


assign cti_d[1:0] = { 	dcd_callclass_d[1] | dcd_tcc_d[1] | dcd_specbr_d[1],
			dcd_callclass_d[0] | dcd_tcc_d[0] | dcd_specbr_d[0] };

dec_del_ctl_msff_ctl_macro__width_16 inst_e  (
 .scan_in(inst_e_scanin),
 .scan_out(inst_e_scanout),
 .l1clk(l1clk),
 .din  ({ded_exc1_d[4:0],ded_exc0_d[4:0],is_lsu1_d,is_lsu0_d,is_fgu1_d,is_fgu0_d,cti_d[1:0]}),
 .dout ({exc1_e[4:0],exc0_e[4:0],is_lsu_e[1:0],is_fgu_e[1:0],cti_e[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_16 inst_m  (
 .scan_in(inst_m_scanin),
 .scan_out(inst_m_scanout),
 .l1clk(l1clk),
 .din  ({exc1_e[4:0],exc0_e[4:0],is_lsu_e[1:0],is_fgu_e[1:0],cti_e[1:0]}),
 .dout ({exc1_m[4:0],exc0_m[4:0],dec_lsu_inst_m[1:0],dec_fgu_inst_m[1:0],dec_cti_inst_m[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_exc0_m[4:0] = exc0_m[4:0];
assign dec_exc1_m[4:0] = exc1_m[4:0];


assign flush_lexc_e= |((fpdisable_exc_e[1:0] | priv_exc_e[1:0] | hpriv_exc_e[1:0]) & is_lsu_e[1:0]);

dec_del_ctl_msff_ctl_macro__width_1 flush_lexc_f  (
 .scan_in(flush_lexc_f_scanin),
 .scan_out(flush_lexc_f_scanout),
 .l1clk(l1clk),
 .din  (flush_lexc_e),
 .dout (flush_lexc_m),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_12 illegal_priv_m  (
 .scan_in(illegal_priv_m_scanin),
 .scan_out(illegal_priv_m_scanout),
 .l1clk(l1clk),
 .din  ({illegal_e[1:0],priv_exc_e[1:0],hpriv_exc_e[1:0],fpdisable_exc_e[1:0],br_taken_e[1:0],icdp_perr_e[1:0]}),
 .dout ({illegal_inst_m[1:0],priv_exc_m[1:0],hpriv_exc_m[1:0],fpdisable_exc_m[1:0],br_taken_m[1:0],icdp_perr_m[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_illegal_inst_m[1:0] = { ~dec_flush_m[1] & illegal_inst_m[1],
			  	   ~dec_flush_m[0] & illegal_inst_m[0] };

assign dec_icache_perr_m[1:0] = { ~dec_flush_m[1] & icdp_perr_m[1],
			          ~dec_flush_m[0] & icdp_perr_m[0] };

assign dec_priv_exc_m[1:0] = { ~dec_flush_m[1] & priv_exc_m[1],
			       ~dec_flush_m[0] & priv_exc_m[0] };

assign dec_hpriv_exc_m[1:0] = { ~dec_flush_m[1] & hpriv_exc_m[1],
			        ~dec_flush_m[0] & hpriv_exc_m[0] };

assign dec_fpdisable_exc_m[1:0] = { ~dec_flush_m[1] & fpdisable_exc_m[1],
			            ~dec_flush_m[0] & fpdisable_exc_m[0] };

assign dec_br_taken_m[1:0] = { ~dec_flush_m[1] & br_taken_m[1],
			       ~dec_flush_m[0] & br_taken_m[0] };


assign done_d[1:0] = dcd_done_d[1:0] &   ~ifetch_err_d[1:0];
assign retry_d[1:0] = dcd_retry_d[1:0] & ~ifetch_err_d[1:0];
assign sir_d[1:0] = dcd_sir_d[1:0] &     ~ifetch_err_d[1:0];

dec_del_ctl_msff_ctl_macro__width_6 done_retry_e  (
 .scan_in(done_retry_e_scanin),
 .scan_out(done_retry_e_scanout),
 .l1clk(l1clk),
 .din  ({done_d[1:0],retry_d[1:0],sir_d[1:0]}),
 .dout ({done_e[1:0],retry_e[1:0],sir_e[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

dec_del_ctl_msff_ctl_macro__width_6 done_retry_m  (
 .scan_in(done_retry_m_scanin),
 .scan_out(done_retry_m_scanout),
 .l1clk(l1clk),
 .din  ({done_e[1:0],retry_e[1:0],sir_e[1:0]}),
 .dout ({done_inst_m[1:0],retry_inst_m[1:0],sir_inst_m[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_done_inst_m[1:0] = { ~dec_flush_m[1] & done_inst_m[1],
			        ~dec_flush_m[0] & done_inst_m[0] };

assign dec_retry_inst_m[1:0] = { ~dec_flush_m[1] & retry_inst_m[1],
			         ~dec_flush_m[0] & retry_inst_m[0] };

assign dec_sir_inst_m[1:0] = { ~dec_flush_m[1] & sir_inst_m[1],
			       ~dec_flush_m[0] & sir_inst_m[0] };

// encodings for ded_exc0_d[4:0], ded_exc1_d[4:0]

/////////////////////////////////////////////////////////////////
// no exception                  = 00000                       //
// tlb_miss (non-real)           = 00001   E                   //
// tlb_access_violation          = 00010   E                   //
// VA hole exception             = 00011   E                   //
// tlb real miss                 = 00100   E                   //
// L2 MISS (for PMU)             = 00101                       //
// IC MISS (for PMU)             = 00110                       //
// ITLB tag parity error         = 00111   E                   //
// ITLB data parity error        = 11111   E                   //
// ITLB multiple hit             = 01001   E                   //
// icache valid (parity error)   = 01010   E                   //
// icache tag parity error       = 01011   E                   //
// icache tag multiple hit       = 01100   E                   //
// icache data parity error      = 01101   E                   //
// icache L2 correctable error   = 01110                       //
// icache L2 uncorrectable error = 01111   E                   //
// icache L2 NotData error       = 10000   E                   //
// ITLB NFO excp                 = 10001   E                   //
// Real VA hole exception        = 10011   E                   //

/////////////////////////////////////////////////////////////////
// New codes added for fetching from I/O space that is not     //
// boot-rom area. Also added code points for l2_miss and errors//
// together to more accurately count l2_miss in PMU.           //
// The new codes were chosen in such a way to minimize         //
// changes to existing testbenches and testcases.              //

// L2 miss and correctable error = 11110                       //
// L2 miss and uncorrectable err = 10111   E                   //
// L2 miss and Notdata error     = 11000   E                   //
/////////////////////////////////////////////////////////////////


// pmu stuff
// {12 - valid; 11:10 - tid; 9:0 - {atomic, l2imiss, itmiss, icmiss, other, %sethi, store, load, FGU, branch}}

// pmu will use dec_valid_e[1:0] to qualify instructions; eliminate illegals

assign atomic_d[0] = dcd_casa_d[0] | dcd_ldstub_d[0] | dcd_swap_d[0];
assign atomic_d[1] = dcd_casa_d[1] | dcd_ldstub_d[1] | dcd_swap_d[1];

assign l2miss0_d   = 	(ded_exc0_d[4:0] == 5'b00101) | // l2miss
			(ded_exc0_d[4:0] == 5'b11110) | // l2 miss correctable error  
			(ded_exc0_d[4:0] == 5'b10111) | // l2 miss uncorrectable error  
			(ded_exc0_d[4:0] == 5'b11000);  // l2 miss not data error

assign l2miss1_d   = 	(ded_exc1_d[4:0] == 5'b00101) | // l2miss
			(ded_exc1_d[4:0] == 5'b11110) | // l2 miss correctable error  
			(ded_exc1_d[4:0] == 5'b10111) | // l2 miss uncorrectable error  
			(ded_exc1_d[4:0] == 5'b11000);  // l2 miss not data error


assign itlbmiss0_d = 	(ded_exc0_d[4:0] == 5'b00001) | // tlb miss non-real
			(ded_exc0_d[4:0] == 5'b00100);  // tlb miss real

assign itlbmiss1_d = 	(ded_exc1_d[4:0] == 5'b00001) | // tlb miss non-real
			(ded_exc1_d[4:0] == 5'b00100);  // tlb miss real

assign icmiss0_d   = 	(ded_exc0_d[4:0] == 5'b00110) |  // ic miss
			(ded_exc0_d[4:0] == 5'b01110) |	 // l2 correctable error
			(ded_exc0_d[4:0] == 5'b01111) |	 // l2 uncorrectable error
			(ded_exc0_d[4:0] == 5'b10000) |	 // l2 not data error
			(ded_exc0_d[4:0] == 5'b11110) |	 // l2 miss correctable error
			(ded_exc0_d[4:0] == 5'b10111) |	 // l2 miss uncorrectable error
			(ded_exc0_d[4:0] == 5'b11000) |	 // l2 miss notdata error
			(ded_exc0_d[4:0] == 5'b00101);	 // l2 miss

assign icmiss1_d   = 	(ded_exc1_d[4:0] == 5'b00110) |  // ic miss
			(ded_exc1_d[4:0] == 5'b01110) |	 // l2 correctable error
			(ded_exc1_d[4:0] == 5'b01111) |	 // l2 uncorrectable error
			(ded_exc1_d[4:0] == 5'b10000) |	 // l2 not data error
			(ded_exc1_d[4:0] == 5'b11110) |	 // l2 miss correctable error
			(ded_exc1_d[4:0] == 5'b10111) |	 // l2 miss uncorrectable error
			(ded_exc1_d[4:0] == 5'b11000) |	 // l2 miss notdata error
			(ded_exc1_d[4:0] == 5'b00101);	 // l2 miss


assign other0_d = ~(dcd_sethi_d[0] | dcd_store_d[0] | dcd_load_d[0] | dcd_specfp_d[0] | branch0_d);
assign other1_d = ~(dcd_sethi_d[1] | dcd_store_d[1] | dcd_load_d[1] | dcd_specfp_d[1] | branch1_d);

assign branch0_d = dcd_specbr_d[0] | dcd_callclass_d[0];
assign branch1_d = dcd_specbr_d[1] | dcd_callclass_d[1];

assign dec_instr0_type_d[9:0] = { atomic_d[0], l2miss0_d, itlbmiss0_d, icmiss0_d, other0_d, dcd_sethi_d[0], dcd_store_d[0], 
				  dcd_load_d[0], dcd_specfp_d[0], branch0_d };

assign dec_instr1_type_d[9:0] = { atomic_d[1], l2miss1_d, itlbmiss1_d, icmiss1_d, other1_d, dcd_sethi_d[1], dcd_store_d[1], 
			          dcd_load_d[1], dcd_specfp_d[1], branch1_d };

// power throttle

// por state is all all zeroes

dec_del_ctl_msff_ctl_macro__width_8 power_stall1f  (
 .scan_in(power_stall1f_scanin),
 .scan_out(power_stall1f_scanout),
 .l1clk(l1clk),
 .din  (power_stall_in[7:0]),
 .dout (power_stall[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);


dec_del_ctl_msff_ctl_macro__width_8 thread_activef  (
 .scan_in(thread_activef_scanin),
 .scan_out(thread_activef_scanout),
 .l1clk(l1clk),
 .din  (spc_core_running_status[7:0]),
 .dout (thread_active[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign del_tg_clken[1:0] = { (|thread_active[7:4]) | ~lsu_dec_pmen, (|thread_active[3:0]) | ~lsu_dec_pmen };

dec_del_ctl_msff_ctl_macro__width_3 power_throttle1f  (
 .scan_in(power_throttle1f_scanin),
 .scan_out(power_throttle1f_scanout),
 .l1clk(l1clk),
 .din  (power_throt0[2:0]),
 .dout (power_throttle1[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);


// special synchronizer for taking in primary inputs to chip
cl_sc1_clksyncff_4x power_throttle02_f (
 .l1clk(l1clk), 
 .si(power_throttle02_f_scanin), 
 .so(power_throttle02_f_scanout),
 .d(power_throttle[2]), 
 .q(power_throttle0[2]),
  .siclk(siclk),
  .soclk(soclk)
);

cl_sc1_clksyncff_4x power_throttle01_f (
 .l1clk(l1clk), 
 .si(power_throttle01_f_scanin), 
 .so(power_throttle01_f_scanout),
 .d(power_throttle[1]), 
 .q(power_throttle0[1]),
  .siclk(siclk),
  .soclk(soclk) 
);

cl_sc1_clksyncff_4x power_throttle00_f (
 .l1clk(l1clk), 
 .si(power_throttle00_f_scanin), 
 .so(power_throttle00_f_scanout),
 .d(power_throttle[0]), 
 .q(power_throttle0[0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign power_throt0[2:0] = ~{3 {lb_lbist_running}} & power_throttle0[2:0];

//// dont use power_throttle_unsafe[]; avoid metastable issue
//msff_ctl_macro power_throttle_unsafef (width=3) (
// .scan_in(power_throttle_unsafef_scanin),
// .scan_out(power_throttle_unsafef_scanout),
// .l1clk(l1clk),
// .din  (power_throttle[2:0]),
// .dout (power_throttle_unsafe[2:0])
//);
//
//msff_ctl_macro power_throttle0f (width=3) (
// .scan_in(power_throttle0f_scanin),
// .scan_out(power_throttle0f_scanout),
// .l1clk(l1clk),
// .din  (power_throttle_unsafe[2:0]),
// .dout (power_throttle0[2:0])
//);


assign change_power_stall = (power_throt0[2:0] != power_throttle1[2:0]);

assign new_power_stall[7:0] = (  ({8{power_throt0[2:0]==3'b000}} & 8'b00000000) |
				 ({8{power_throt0[2:0]==3'b001}} & 8'b00000001) |
				 ({8{power_throt0[2:0]==3'b010}} & 8'b00010001) |
				 ({8{power_throt0[2:0]==3'b011}} & 8'b00100101) |
				 ({8{power_throt0[2:0]==3'b100}} & 8'b01010101) |
				 ({8{power_throt0[2:0]==3'b101}} & 8'b11011010) |
				 ({8{power_throt0[2:0]==3'b110}} & 8'b11101110) |
				 ({8{power_throt0[2:0]==3'b111}} & 8'b11111110)  );

assign power_stall_in[7:0] = ({8{change_power_stall}} & new_power_stall[7:0]) |
			     ({8{~change_power_stall}} & {power_stall[6:0],power_stall[7]});


supply0 vss;
supply1 vdd;

// fixscan start:
assign spares_scanin             = scan_in                  ;
assign pdecode0f_scanin          = spares_scanout           ;
assign pdecode1f_scanin          = pdecode0f_scanout        ;
assign pick0f_scanin             = pdecode1f_scanout        ;
assign pick1f_scanin             = pick0f_scanout           ;
assign privstatef_scanin         = pick1f_scanout           ;
assign fef_scanin                = privstatef_scanout       ;
assign instcntf_scanin           = fef_scanout              ;
assign exutestf_scanin           = instcntf_scanout         ;
assign teststallf_scanin         = exutestf_scanout         ;
assign val_df_scanin             = teststallf_scanout       ;
assign valid_df_scanin           = val_df_scanout           ;
assign dtlb_reloadf_scanin       = valid_df_scanout         ;
assign block_store0f_scanin      = dtlb_reloadf_scanout     ;
assign block_storef_scanin       = block_store0f_scanout    ;
assign block_store_rdhif_scanin  = block_storef_scanout     ;
assign block_store_rdlof_scanin  = block_store_rdhif_scanout;
assign block_store_tidf_scanin   = block_store_rdlof_scanout;
assign cpq_stallf_scanin         = block_store_tidf_scanout ;
assign fecc_stallf_scanin        = cpq_stallf_scanout       ;
assign block_resetf_scanin       = fecc_stallf_scanout      ;
assign block_store_e_scanin      = block_resetf_scanout     ;
assign block_store_m_scanin      = block_store_e_scanout    ;
assign block_store_b_scanin      = block_store_m_scanout    ;
assign lfavorf_scanin            = block_store_b_scanout    ;
assign ffavorf_scanin            = lfavorf_scanout          ;
assign sffavorf_scanin           = ffavorf_scanout          ;
assign mulrequestf_scanin        = sffavorf_scanout         ;
assign cmfavorf_scanin           = mulrequestf_scanout      ;
assign pdistblockf_scanin        = cmfavorf_scanout         ;
assign pdistrdf_scanin           = pdistblockf_scanout      ;
assign pdisttidf_scanin          = pdistrdf_scanout         ;
assign twocycle0_df_scanin       = pdisttidf_scanout        ;
assign twocycle1_df_scanin       = twocycle0_df_scanout     ;
assign inthole0_df_scanin        = twocycle1_df_scanout     ;
assign inthole1_df_scanin        = inthole0_df_scanout      ;
assign divstall_df_scanin        = inthole1_df_scanout      ;
assign windowstall_df_scanin     = divstall_df_scanout      ;
assign exu_clkenf_scanin         = windowstall_df_scanout   ;
assign legal_f_scanin            = exu_clkenf_scanout       ;
assign illegal_f_scanin          = legal_f_scanout          ;
assign fpdisable_exc_f_scanin    = illegal_f_scanout        ;
assign parity_err_f_scanin       = fpdisable_exc_f_scanout  ;
assign exc_f_scanin              = parity_err_f_scanout     ;
assign tgsel_f_scanin            = exc_f_scanout            ;
assign exuself_scanin            = tgsel_f_scanout          ;
assign tgselm_f_scanin           = exuself_scanout          ;
assign frf_r2addre_f_scanin      = tgselm_f_scanout         ;
assign ifetch_err_f_scanin       = frf_r2addre_f_scanout    ;
assign ifetcherr_f_scanin        = ifetch_err_f_scanout     ;
assign truevalid_f_scanin        = ifetcherr_f_scanout      ;
assign fgudec_f_scanin           = truevalid_f_scanout       ;
assign lsudec_f_scanin           = fgudec_f_scanout         ;
assign ldste_f_scanin            = lsudec_f_scanout         ;
assign ldme_f_scanin             = ldste_f_scanout          ;
assign sraddr_f_scanin           = ldme_f_scanout           ;
assign lsurd_f_scanin            = sraddr_f_scanout         ;
assign ds_m_scanin               = lsurd_f_scanout          ;
assign annul_m_scanin            = ds_m_scanout             ;
assign tid_e_scanin              = annul_m_scanout          ;
assign tid_m_scanin              = tid_e_scanout            ;
assign dec_e_scanin              = tid_m_scanout            ;
assign dec_m_scanin              = dec_e_scanout            ;
assign inst_e_scanin             = dec_m_scanout            ;
assign inst_m_scanin             = inst_e_scanout           ;
assign flush_lexc_f_scanin       = inst_m_scanout           ;
assign illegal_priv_m_scanin     = flush_lexc_f_scanout     ;
assign done_retry_e_scanin       = illegal_priv_m_scanout   ;
assign done_retry_m_scanin       = done_retry_e_scanout     ;
assign power_stall1f_scanin      = done_retry_m_scanout     ;
assign thread_activef_scanin     = power_stall1f_scanout    ;
assign power_throttle1f_scanin   = thread_activef_scanout   ;
assign power_throttle02_f_scanin = power_throttle1f_scanout ;        
assign power_throttle01_f_scanin = power_throttle02_f_scanout ;  // these connections must be done by hand
assign power_throttle00_f_scanin = power_throttle01_f_scanout ;
assign scan_out                  = power_throttle00_f_scanout ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module dec_del_ctl_spare_ctl_macro__flops_0__num_6;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;


cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__scanreverse_1__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [0:4] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({so[0:4],scan_in}),
.so({scan_out,so[0:4]}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dec_del_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: exu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module exu (
  l2clk, 
  scan_in, 
  wmr_scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  spc_aclk_wmr, 
  tcu_scan_en, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  tcu_dectest, 
  tcu_muxtest, 
  in_rngl_cdbus, 
  dec_tid_p, 
  dec_inst_rs1_vld_p, 
  dec_inst_rs2_vld_p, 
  dec_inst_rs3_vld_p, 
  dec_inst_rs1_p, 
  dec_inst_rs2_p, 
  dec_inst_rs3_p, 
  dec_exu_clken, 
  dec_inst_rd_d, 
  dec_inst_d, 
  dec_decode_d, 
  dec_thread_group, 
  tlu_pc_d, 
  dec_valid_e, 
  tlu_itlb_bypass_e, 
  dec_flush_m, 
  dec_flush_b, 
  fgu_exu_icc_fx5, 
  fgu_exu_xcc_fx5, 
  fgu_exu_cc_vld_fx5, 
  fgu_exu_result_fx5, 
  fgu_result_tid_fx5, 
  fgu_irf_w_addr_fx5, 
  fgu_exu_w_vld_fx5, 
  lsu_exu_ld_data_b, 
  lsu_exu_ld_b, 
  lsu_exu_rd_m, 
  lsu_exu_tid_m, 
  lsu_exu_ld_vld_w, 
  tlu_flush_exu_b, 
  tlu_ccr, 
  tlu_cwp, 
  tlu_ccr_cwp_valid, 
  tlu_ccr_cwp_tid, 
  tlu_pstate_am, 
  tlu_gl_thr0, 
  tlu_gl_thr1, 
  tlu_gl_thr2, 
  tlu_gl_thr3, 
  tlu_cerer_irf, 
  tlu_ceter_pscce, 
  lsu_asi_error_inject_b31, 
  lsu_asi_error_inject_b25, 
  lsu_asi_error_inject, 
  lsu_exu_pmen, 
  lsu_asi_clken, 
  spc_core_running_status, 
  mbi_run, 
  mbi_addr, 
  mbi_write_data_p1, 
  mbi_irf_read_en, 
  mbi_irf_write_en, 
  mbi_irf_save_en, 
  mbi_irf_restore_en, 
  fgu_fld_fcc_fx3, 
  lsu_fgu_fld_tid_b, 
  fgu_fld_fcc_vld_fx3, 
  lsu_fgu_fld_vld_w, 
  fgu_cmp_fcc_fx3, 
  fgu_cmp_fcc_tid_fx2, 
  fgu_cmp_fcc_vld_fx3, 
  dec_pick_d, 
  exu_rngl_cdbus, 
  exu_oddwin_b, 
  exu_address_e, 
  exu_mdp_mux_sel_e, 
  exu_ms_icc_e, 
  exu_rs1_data_e, 
  exu_rs2_data_e, 
  exu_store_data_e, 
  exu_y_data_e, 
  exu_ecc_m, 
  exu_ecc_winop_flush_m, 
  exu_gsr_data_m, 
  exu_gsr_vld_m, 
  exu_lsu_va_error_m, 
  exu_ibp_m, 
  exu_ecc_addr_m, 
  exu_ecc_check_m, 
  exu_cecc_m, 
  exu_uecc_m, 
  exu_misalign_m, 
  exu_oor_va_m, 
  exu_tcc_m, 
  exu_tof_m, 
  exu_trap_number_b, 
  exu_spill_b, 
  exu_fill_m, 
  exu_normal_b, 
  exu_cleanwin_b, 
  exu_wstate_b, 
  exu_ccr0, 
  exu_ccr1, 
  exu_ccr2, 
  exu_ccr3, 
  exu_cwp_thr0, 
  exu_cwp_thr1, 
  exu_cwp_thr2, 
  exu_cwp_thr3, 
  exu_window_block_m, 
  exu_tlu_window_block, 
  exu_test_valid, 
  exu_test_tid, 
  exu_test_addr, 
  exu_mbi_irf_fail_, 
  exu_br_taken_e, 
  exu_br_taken_e1, 
  exu_cmov_true_m, 
  scan_out, 
  wmr_scan_out);
wire edp_scanin;
wire edp_scanout;
wire ect_wmr_scanin;
wire ect_wmr_scanout;
wire ect_scanin;
wire ect_scanout;
wire [64:0] edp_rng_in_ff;
wire ecc_scanin;
wire ecc_scanout;
wire rml_wmr_scanin;
wire rml_wmr_scanout;
wire rml_scanin;
wire rml_scanout;
wire irf_scanin;
wire irf_scanout;
wire ect_tg_clken;
wire ect_valid_lth_w;
wire [1:0] ect_tid_lth_w;
wire [4:0] ect_rd_lth_w;
wire [7:0] ecc_w_synd_w;
wire [63:0] edp_rd_ff_w;
wire ect_valid_in_w2;
wire [1:0] ect_tid_lth_w2;
wire [4:0] ect_rd_lth_w2;
wire [7:0] ecc_w2_synd_w2;
wire [63:0] edp_rd_ff_w2;
wire [1:0] rml_irf_cwpswap_tid_m;
wire [2:0] rml_irf_old_lo_cwp_m;
wire [2:1] rml_irf_old_e_cwp_m;
wire rml_irf_save_even_m;
wire rml_irf_save_odd_m;
wire rml_irf_save_local_m;
wire [1:0] rml_irf_cwpswap_tid_b;
wire [2:0] rml_irf_new_lo_cwp_b;
wire [2:1] rml_irf_new_e_cwp_b;
wire rml_irf_restore_even_b;
wire rml_irf_restore_odd_b;
wire rml_irf_restore_local_b;
wire rml_irf_save_global;
wire [1:0] rml_irf_global_tid;
wire [1:0] rml_irf_old_agp;
wire rml_irf_restore_global;
wire [1:0] rml_irf_global_tid_ff;
wire [1:0] rml_irf_new_agp_ff;
wire [71:0] irf_rs1_data_d;
wire [71:0] irf_rs2_data_d;
wire [71:0] irf_rs3_data_d;
wire [5:0] rml_rng_data_out;
wire [4:0] rml_rng_rd_ctl;
wire [1:0] rml_rng_ack_ctl;
wire [1:0] rml_rng_ack_cwp_tid;
wire [1:0] rml_rng_ack_ecc_tid;
wire rml_rng_ack_det_vld;
wire rml_rng_wt_imask_ctl;
wire [7:0] rml_irf_ecc_data;
wire rml_rng_ack_sel_ctl;
wire [31:0] rml_rng_y_data;
wire [7:0] ect_rng_ccr_data;
wire ect_mbist_sel;
wire [7:0] ecc_mbist_write_data_p4;
wire [4:0] ect_rs1_early_sel_d;
wire [4:0] ect_rs2_early_sel_d;
wire [4:0] ect_rs3_early_sel_d;
wire [7:0] ect_rs2_imm_sel_d;
wire [3:0] ect_rs1_late_sel_d;
wire [3:0] ect_rs2_late_sel_d;
wire [3:0] ect_rs3_late_sel_d;
wire [3:0] ect_logic_sel_d;
wire [6:0] ect_shift_sel_d;
wire ect_br_taken_z0_e;
wire ect_br_taken_z1_e;
wire ect_alignaddress_little_e;
wire ect_as_clip_e_;
wire ect_as_cin_e;
wire [1:0] ect_array_sel_e;
wire [7:0] ect_edge_lmask_e;
wire [7:0] ect_edge_lrmask_e;
wire ect_pstate_am_e;
wire [5:0] ect_rm_early_sel_e;
wire [2:0] ect_rm_late_sel_e;
wire ect_store_mux_sel_e;
wire ect_ex_emb_clken;
wire [1:0] edp_br_flag_e;
wire [63:0] edp_rcc_data_e;
wire [63:0] edp_rs3_data_e;
wire [7:0] edp_rcc_ecc_e;
wire [7:0] edp_rs2_ecc_e;
wire [7:0] edp_rs3_ecc_e;
wire edp_add_cout64_e;
wire edp_add_data_e_b63;
wire [1:0] edp_add_zdetect_e_;
wire edp_sub_cout64_e;
wire edp_sub_data_e_b63;
wire edp_sub_data_e_b31;
wire [1:0] edp_sub_zdetect_e_;
wire edp_logical_data_e_b63;
wire edp_logical_data_e_b31;
wire [1:0] edp_lg_zdetect_e;
wire [63:47] edp_address_m;
wire [63:47] edp_rd_ff_m;
wire rml_rng_wt_ccr_ctl;
wire rml_test_valid_d;
wire [1:0] ect_tid_lth_e;
wire [4:0] ect_rs1_addr_e;
wire [4:0] ect_rs2_addr_e;
wire [4:0] ect_rs3_addr_e;
wire ect_rs1_valid_e;
wire ect_rs2_valid_e;
wire ect_rs3_valid_e;
wire ect_two_cycle_m;
wire ect_yreg_wr_w;
wire ect_misaligned_error_m;


input		l2clk;
input         	scan_in;
input		wmr_scan_in;
input        	tcu_pce_ov;			// scan signals
input      	spc_aclk;
input     	spc_bclk;
input		spc_aclk_wmr;
input		tcu_scan_en;
input		tcu_array_wr_inhibit;
input		tcu_se_scancollar_in;
input		tcu_dectest;			// Passgate mux test control
input		tcu_muxtest;			// Passgate mux test control

input  [64:0]	in_rngl_cdbus;			// ASI Ring

input  [1:0]	dec_tid_p;
input		dec_inst_rs1_vld_p;
input		dec_inst_rs2_vld_p;
input		dec_inst_rs3_vld_p;
input  [4:0]	dec_inst_rs1_p;
input  [4:0]	dec_inst_rs2_p;
input  [4:0]	dec_inst_rs3_p;

input		dec_exu_clken;			// Powerdown for D->E Flops
input  [4:0]	dec_inst_rd_d;
input  [31:0]	dec_inst_d;
input		dec_decode_d;			// Instruction and TID are valid
input		dec_thread_group;		// Static Signal : Tie UP or DOWN where cloning occurs
input  [47:2]	tlu_pc_d;

input		dec_valid_e;			// Late "E" Stage Valid
input		tlu_itlb_bypass_e;		// Ignore Address Out-Of-Range

input		dec_flush_m;
input		dec_flush_b;

input  [3:0]	fgu_exu_icc_fx5;		// FGU int icc cond code {N,Z,V,C}
input  [1:0]	fgu_exu_xcc_fx5;		// FGU int xcc cond code {N,Z}
input		fgu_exu_cc_vld_fx5;		// FGU int icc/xcc cond code valid
input  [63:0]	fgu_exu_result_fx5;		// FGU Integer results
input  [1:0]	fgu_result_tid_fx5;
input  [4:0]	fgu_irf_w_addr_fx5;
input		fgu_exu_w_vld_fx5;

input  [63:0]	lsu_exu_ld_data_b;
input		lsu_exu_ld_b;
input  [4:0]	lsu_exu_rd_m;
input  [2:0]	lsu_exu_tid_m;
input		lsu_exu_ld_vld_w;

input		tlu_flush_exu_b;		// EXU to flush instr in B stage
input  [7:0]	tlu_ccr;
input  [2:0]	tlu_cwp;
input		tlu_ccr_cwp_valid;
input  [1:0]	tlu_ccr_cwp_tid;
input  [3:0]	tlu_pstate_am;			// 32-bit addressing mode if = 1

input  [1:0]	tlu_gl_thr0;			// From TLU : current GL value to update
input  [1:0]	tlu_gl_thr1;			// From TLU : current GL value to update
input  [1:0]	tlu_gl_thr2;			// From TLU : current GL value to update
input  [1:0]	tlu_gl_thr3;			// From TLU : current GL value to update

input		tlu_cerer_irf;			// IRF ecc error trap enable
input  [3:0]	tlu_ceter_pscce;		// core error trap enable reg precise enable


input		lsu_asi_error_inject_b31;	// [31]=global inject en
input		lsu_asi_error_inject_b25;	// [25]=IRF inject en
input  [7:0]	lsu_asi_error_inject;		// [7:0]=mask
input		lsu_exu_pmen;			// Power Management : Master Enable
input		lsu_asi_clken;			// Power Management : ASI ring
input  [3:0]	spc_core_running_status;	// Power Management : Thread active

input		mbi_run; 			// MBIST
input  [9:0]	mbi_addr; 			// MBIST
input  [7:0]	mbi_write_data_p1; 		// MBIST
input		mbi_irf_read_en; 		// MBIST
input		mbi_irf_write_en; 		// MBIST
input		mbi_irf_save_en;		// MBIST
input		mbi_irf_restore_en;		// MBIST

// *** DEC_CCR Inputs ***

input  [7:0]	fgu_fld_fcc_fx3;		// fcc's from the fgu
input  [2:0]	lsu_fgu_fld_tid_b;
input  [1:0]	fgu_fld_fcc_vld_fx3;
input		lsu_fgu_fld_vld_w;		// Float load valid

input  [1:0]	fgu_cmp_fcc_fx3;		// fcc's from the fgu
input  [2:0]	fgu_cmp_fcc_tid_fx2;
input  [3:0]	fgu_cmp_fcc_vld_fx3;

input  [3:0]	dec_pick_d;			// which stand is valid at d


output [64:0]	exu_rngl_cdbus;			// ASI Ring

output [3:0] 	exu_oddwin_b;			// To Decode
output [47:0]	exu_address_e;			// To IFU and LSU
output [5:0]	exu_mdp_mux_sel_e;		// To MDP
output		exu_ms_icc_e;
output [63:0]	exu_rs1_data_e;			// To MDP
output [63:0]	exu_rs2_data_e;			// To MDP
output [63:0]	exu_store_data_e;		// To LSU
output [31:0]	exu_y_data_e;			// To MDP

output		exu_ecc_m;			// To FGU
output		exu_ecc_winop_flush_m;		// To FGU : signal "1" when ECC or WINOP exception
                                                //          to flush FGU
output [31:0]	exu_gsr_data_m;			// To FGU
output [1:0]	exu_gsr_vld_m;			// To FGU
output		exu_lsu_va_error_m;		// To LSU : Address Out of Range

output		exu_ibp_m;			// To TLU : Raw Intruction Breakpoint
output [4:0]	exu_ecc_addr_m;			// To TLU :
output [7:0]	exu_ecc_check_m;		// To TLU :
output		exu_cecc_m;			// To TLU : Correctable ECC Error
output		exu_uecc_m;			// To TLU : Uncorrectable ECC Error

output		exu_misalign_m;			// To TLU : Misaligned address for Jump,Return
output		exu_oor_va_m;			// To TLU : Address Out of Range
output		exu_tcc_m;			// To TLU : Trap taken
output		exu_tof_m;			// To TLU : Tagged Add TV with overflow
output [7:0]	exu_trap_number_b;		// To TLU

output    	exu_spill_b;                    // To TLU : report window spill exception
output     	exu_fill_m;                     // To TLU : report window fill  exception
output     	exu_normal_b;                   // To TLU : report window spill/fill  exception type
output     	exu_cleanwin_b;	                // To TLU : report clean window exception
output [2:0]	exu_wstate_b;	                // To TLU : report fill/spill vector 

output [7:0]	exu_ccr0;			// To TLU : Architected CCR
output [7:0]	exu_ccr1;			// To TLU : Architected CCR
output [7:0]	exu_ccr2;			// To TLU : Architected CCR
output [7:0]	exu_ccr3;			// To TLU : Architected CCR

output [2:0]	exu_cwp_thr0;                   // To TLU : Current Window Pointer - thr0
output [2:0]	exu_cwp_thr1;                   // To TLU : Current Window Pointer - thr1
output [2:0]	exu_cwp_thr2;                   // To TLU : Current Window Pointer - thr2
output [2:0]	exu_cwp_thr3;                   // To TLU : Current Window Pointer - thr3

output		exu_window_block_m;		// create bubble for SWAP signal for IRF
output		exu_tlu_window_block;		// create bubble for SWAP signal for IRF

output 		exu_test_valid;                 // To PKU : read IRF data 
output [1:0]	exu_test_tid;
output [4:0]	exu_test_addr;

output [1:0]	exu_mbi_irf_fail_;		// MBIST [0] == [63:0];  [1] == [71:64]


// *** DEC_CCR Outputs ***

output		exu_br_taken_e;			// To IFU             : branch is taken
output		exu_br_taken_e1;		// To DEC_DEL and PKU : branch is taken
output		exu_cmov_true_m;

output 		scan_out;
output		wmr_scan_out;


exu_edp_dp   edp (
.scan_in(edp_scanin),
.scan_out(edp_scanout),
.l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .in_rngl_cdbus(in_rngl_cdbus[64:0]),
  .tlu_pc_d(tlu_pc_d[47:2]),
  .dec_inst_d(dec_inst_d[31:0]),
  .dec_thread_group(dec_thread_group),
  .dec_exu_clken(dec_exu_clken),
  .fgu_exu_w_vld_fx5(fgu_exu_w_vld_fx5),
  .fgu_exu_result_fx5(fgu_exu_result_fx5[63:0]),
  .irf_rs1_data_d(irf_rs1_data_d[71:0]),
  .irf_rs2_data_d(irf_rs2_data_d[71:0]),
  .irf_rs3_data_d(irf_rs3_data_d[71:0]),
  .lsu_asi_clken(lsu_asi_clken),
  .lsu_exu_ld_data_b(lsu_exu_ld_data_b[63:0]),
  .mbi_write_data_p1(mbi_write_data_p1[7:0]),
  .exu_y_data_e(exu_y_data_e[31:0]),
  .rml_rng_data_out(rml_rng_data_out[5:0]),
  .rml_rng_rd_ctl(rml_rng_rd_ctl[4:0]),
  .rml_rng_ack_ctl(rml_rng_ack_ctl[1:0]),
  .rml_rng_ack_cwp_tid(rml_rng_ack_cwp_tid[1:0]),
  .rml_rng_ack_ecc_tid(rml_rng_ack_ecc_tid[1:0]),
  .rml_rng_ack_det_vld(rml_rng_ack_det_vld),
  .rml_rng_wt_imask_ctl(rml_rng_wt_imask_ctl),
  .rml_irf_ecc_data(rml_irf_ecc_data[7:0]),
  .rml_rng_ack_sel_ctl(rml_rng_ack_sel_ctl),
  .rml_rng_y_data(rml_rng_y_data[31:0]),
  .ect_rng_ccr_data(ect_rng_ccr_data[7:0]),
  .ect_mbist_sel(ect_mbist_sel),
  .ecc_mbist_write_data_p4(ecc_mbist_write_data_p4[7:0]),
  .ect_rs1_early_sel_d(ect_rs1_early_sel_d[4:0]),
  .ect_rs2_early_sel_d(ect_rs2_early_sel_d[4:0]),
  .ect_rs3_early_sel_d(ect_rs3_early_sel_d[4:0]),
  .ect_rs2_imm_sel_d(ect_rs2_imm_sel_d[7:0]),
  .ect_rs1_late_sel_d(ect_rs1_late_sel_d[3:0]),
  .ect_rs2_late_sel_d(ect_rs2_late_sel_d[3:0]),
  .ect_rs3_late_sel_d(ect_rs3_late_sel_d[3:0]),
  .ect_logic_sel_d(ect_logic_sel_d[3:0]),
  .ect_shift_sel_d(ect_shift_sel_d[6:0]),
  .ect_br_taken_z0_e(ect_br_taken_z0_e),
  .ect_br_taken_z1_e(ect_br_taken_z1_e),
  .ect_alignaddress_little_e(ect_alignaddress_little_e),
  .ect_as_clip_e_(ect_as_clip_e_),
  .ect_as_cin_e(ect_as_cin_e),
  .ect_array_sel_e(ect_array_sel_e[1:0]),
  .ect_edge_lmask_e(ect_edge_lmask_e[7:0]),
  .ect_edge_lrmask_e(ect_edge_lrmask_e[7:0]),
  .ect_pstate_am_e(ect_pstate_am_e),
  .ect_rm_early_sel_e(ect_rm_early_sel_e[5:0]),
  .ect_rm_late_sel_e(ect_rm_late_sel_e[2:0]),
  .ect_store_mux_sel_e(ect_store_mux_sel_e),
  .ect_ex_emb_clken(ect_ex_emb_clken),
  .ect_tg_clken(ect_tg_clken),
  .exu_rngl_cdbus(exu_rngl_cdbus[64:0]),
  .exu_br_taken_e(exu_br_taken_e),
  .exu_br_taken_e1(exu_br_taken_e1),
  .exu_address_e(exu_address_e[47:0]),
  .exu_gsr_data_m(exu_gsr_data_m[31:0]),
  .exu_store_data_e(exu_store_data_e[63:0]),
  .exu_ibp_m(exu_ibp_m),
  .exu_trap_number_b(exu_trap_number_b[7:0]),
  .exu_mbi_irf_fail_(exu_mbi_irf_fail_[1:0]),
  .edp_rng_in_ff(edp_rng_in_ff[64:0]),
  .edp_br_flag_e(edp_br_flag_e[1:0]),
  .exu_rs1_data_e(exu_rs1_data_e[63:0]),
  .edp_rcc_data_e(edp_rcc_data_e[63:0]),
  .exu_rs2_data_e(exu_rs2_data_e[63:0]),
  .edp_rs3_data_e(edp_rs3_data_e[63:0]),
  .edp_rcc_ecc_e(edp_rcc_ecc_e[7:0]),
  .edp_rs2_ecc_e(edp_rs2_ecc_e[7:0]),
  .edp_rs3_ecc_e(edp_rs3_ecc_e[7:0]),
  .edp_add_cout64_e(edp_add_cout64_e),
  .edp_add_data_e_b63(edp_add_data_e_b63),
  .edp_add_zdetect_e_(edp_add_zdetect_e_[1:0]),
  .edp_sub_cout64_e(edp_sub_cout64_e),
  .edp_sub_data_e_b63(edp_sub_data_e_b63),
  .edp_sub_data_e_b31(edp_sub_data_e_b31),
  .edp_sub_zdetect_e_(edp_sub_zdetect_e_[1:0]),
  .edp_logical_data_e_b63(edp_logical_data_e_b63),
  .edp_logical_data_e_b31(edp_logical_data_e_b31),
  .edp_lg_zdetect_e(edp_lg_zdetect_e[1:0]),
  .edp_address_m(edp_address_m[63:47]),
  .edp_rd_ff_m(edp_rd_ff_m[63:47]),
  .edp_rd_ff_w(edp_rd_ff_w[63:0]),
  .edp_rd_ff_w2(edp_rd_ff_w2[63:0])
);

exu_ect_ctl  ect (		// FS:wmr_protect
.wmr_scan_in(ect_wmr_scanin),
.wmr_scan_out(ect_wmr_scanout),
.scan_in(ect_scanin),
.scan_out(ect_scanout),
.l2clk(l2clk),
.edp_add_data_e_b0 ( exu_address_e[0]	),
.edp_add_data_e_b1 ( exu_address_e[1]	),
.edp_add_data_e_b31( exu_address_e[31]	),
.edp_rng_in_ff_b57 ( edp_rng_in_ff[57]	),
.edp_rng_in_ff_b56 ( edp_rng_in_ff[56]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .spc_aclk_wmr(spc_aclk_wmr),
  .tcu_scan_en(tcu_scan_en),
  .dec_tid_p(dec_tid_p[1:0]),
  .dec_inst_rs1_vld_p(dec_inst_rs1_vld_p),
  .dec_inst_rs2_vld_p(dec_inst_rs2_vld_p),
  .dec_inst_rs3_vld_p(dec_inst_rs3_vld_p),
  .dec_inst_rs1_p(dec_inst_rs1_p[4:0]),
  .dec_inst_rs2_p(dec_inst_rs2_p[4:0]),
  .dec_inst_rs3_p(dec_inst_rs3_p[4:0]),
  .dec_inst_rd_d(dec_inst_rd_d[4:0]),
  .dec_inst_d(dec_inst_d[31:5]),
  .dec_decode_d(dec_decode_d),
  .dec_thread_group(dec_thread_group),
  .dec_valid_e(dec_valid_e),
  .tlu_itlb_bypass_e(tlu_itlb_bypass_e),
  .dec_flush_m(dec_flush_m),
  .dec_flush_b(dec_flush_b),
  .fgu_exu_icc_fx5(fgu_exu_icc_fx5[3:0]),
  .fgu_exu_xcc_fx5(fgu_exu_xcc_fx5[1:0]),
  .fgu_exu_cc_vld_fx5(fgu_exu_cc_vld_fx5),
  .fgu_result_tid_fx5(fgu_result_tid_fx5[1:0]),
  .fgu_irf_w_addr_fx5(fgu_irf_w_addr_fx5[4:0]),
  .fgu_exu_w_vld_fx5(fgu_exu_w_vld_fx5),
  .lsu_exu_ld_b(lsu_exu_ld_b),
  .lsu_exu_rd_m(lsu_exu_rd_m[4:0]),
  .lsu_exu_tid_m(lsu_exu_tid_m[2:0]),
  .lsu_exu_ld_vld_w(lsu_exu_ld_vld_w),
  .tlu_flush_exu_b(tlu_flush_exu_b),
  .tlu_ccr(tlu_ccr[7:0]),
  .tlu_ccr_cwp_valid(tlu_ccr_cwp_valid),
  .tlu_ccr_cwp_tid(tlu_ccr_cwp_tid[1:0]),
  .tlu_pstate_am(tlu_pstate_am[3:0]),
  .lsu_exu_pmen(lsu_exu_pmen),
  .spc_core_running_status(spc_core_running_status[3:0]),
  .mbi_run(mbi_run),
  .mbi_addr(mbi_addr[6:0]),
  .mbi_irf_write_en(mbi_irf_write_en),
  .edp_rng_in_ff(edp_rng_in_ff[7:0]),
  .rml_rng_wt_ccr_ctl(rml_rng_wt_ccr_ctl),
  .edp_br_flag_e(edp_br_flag_e[1:0]),
  .exu_rs1_data_e(exu_rs1_data_e[63:0]),
  .exu_rs2_data_e(exu_rs2_data_e[63:0]),
  .edp_add_cout64_e(edp_add_cout64_e),
  .edp_add_data_e_b63(edp_add_data_e_b63),
  .edp_add_zdetect_e_(edp_add_zdetect_e_[1:0]),
  .edp_sub_cout64_e(edp_sub_cout64_e),
  .edp_sub_data_e_b63(edp_sub_data_e_b63),
  .edp_sub_data_e_b31(edp_sub_data_e_b31),
  .edp_sub_zdetect_e_(edp_sub_zdetect_e_[1:0]),
  .edp_logical_data_e_b63(edp_logical_data_e_b63),
  .edp_logical_data_e_b31(edp_logical_data_e_b31),
  .edp_lg_zdetect_e(edp_lg_zdetect_e[1:0]),
  .edp_address_m(edp_address_m[63:47]),
  .edp_rd_ff_m(edp_rd_ff_m[63:47]),
  .exu_ecc_m(exu_ecc_m),
  .rml_test_valid_d(rml_test_valid_d),
  .fgu_fld_fcc_fx3(fgu_fld_fcc_fx3[7:0]),
  .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]),
  .fgu_fld_fcc_vld_fx3(fgu_fld_fcc_vld_fx3[1:0]),
  .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w),
  .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]),
  .fgu_cmp_fcc_tid_fx2(fgu_cmp_fcc_tid_fx2[2:0]),
  .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0]),
  .dec_pick_d(dec_pick_d[3:0]),
  .exu_mdp_mux_sel_e(exu_mdp_mux_sel_e[5:0]),
  .exu_ms_icc_e(exu_ms_icc_e),
  .exu_gsr_vld_m(exu_gsr_vld_m[1:0]),
  .exu_cmov_true_m(exu_cmov_true_m),
  .exu_lsu_va_error_m(exu_lsu_va_error_m),
  .exu_misalign_m(exu_misalign_m),
  .exu_oor_va_m(exu_oor_va_m),
  .exu_tcc_m(exu_tcc_m),
  .exu_tof_m(exu_tof_m),
  .exu_ccr0(exu_ccr0[7:0]),
  .exu_ccr1(exu_ccr1[7:0]),
  .exu_ccr2(exu_ccr2[7:0]),
  .exu_ccr3(exu_ccr3[7:0]),
  .ect_mbist_sel(ect_mbist_sel),
  .ect_rs1_early_sel_d(ect_rs1_early_sel_d[4:0]),
  .ect_rs2_early_sel_d(ect_rs2_early_sel_d[4:0]),
  .ect_rs3_early_sel_d(ect_rs3_early_sel_d[4:0]),
  .ect_rs2_imm_sel_d(ect_rs2_imm_sel_d[7:0]),
  .ect_rs1_late_sel_d(ect_rs1_late_sel_d[3:0]),
  .ect_rs2_late_sel_d(ect_rs2_late_sel_d[3:0]),
  .ect_rs3_late_sel_d(ect_rs3_late_sel_d[3:0]),
  .ect_logic_sel_d(ect_logic_sel_d[3:0]),
  .ect_shift_sel_d(ect_shift_sel_d[6:0]),
  .ect_br_taken_z0_e(ect_br_taken_z0_e),
  .ect_br_taken_z1_e(ect_br_taken_z1_e),
  .ect_alignaddress_little_e(ect_alignaddress_little_e),
  .ect_as_clip_e_(ect_as_clip_e_),
  .ect_as_cin_e(ect_as_cin_e),
  .ect_array_sel_e(ect_array_sel_e[1:0]),
  .ect_edge_lmask_e(ect_edge_lmask_e[7:0]),
  .ect_edge_lrmask_e(ect_edge_lrmask_e[7:0]),
  .ect_pstate_am_e(ect_pstate_am_e),
  .ect_rm_early_sel_e(ect_rm_early_sel_e[5:0]),
  .ect_rm_late_sel_e(ect_rm_late_sel_e[2:0]),
  .ect_store_mux_sel_e(ect_store_mux_sel_e),
  .ect_tid_lth_e(ect_tid_lth_e[1:0]),
  .ect_rs1_addr_e(ect_rs1_addr_e[4:0]),
  .ect_rs2_addr_e(ect_rs2_addr_e[4:0]),
  .ect_rs3_addr_e(ect_rs3_addr_e[4:0]),
  .ect_rs1_valid_e(ect_rs1_valid_e),
  .ect_rs2_valid_e(ect_rs2_valid_e),
  .ect_rs3_valid_e(ect_rs3_valid_e),
  .ect_two_cycle_m(ect_two_cycle_m),
  .ect_rd_lth_w(ect_rd_lth_w[4:0]),
  .ect_rd_lth_w2(ect_rd_lth_w2[4:0]),
  .ect_tid_lth_w(ect_tid_lth_w[1:0]),
  .ect_tid_lth_w2(ect_tid_lth_w2[1:0]),
  .ect_valid_lth_w(ect_valid_lth_w),
  .ect_valid_in_w2(ect_valid_in_w2),
  .ect_yreg_wr_w(ect_yreg_wr_w),
  .ect_rng_ccr_data(ect_rng_ccr_data[7:0]),
  .ect_misaligned_error_m(ect_misaligned_error_m),
  .ect_ex_emb_clken(ect_ex_emb_clken),
  .ect_tg_clken(ect_tg_clken)
);

exu_ecc_ctl  ecc (
.scan_in(ecc_scanin),
.scan_out(ecc_scanout),
.l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .ect_mbist_sel(ect_mbist_sel),
  .mbi_write_data_p1(mbi_write_data_p1[7:0]),
  .edp_rd_ff_w(edp_rd_ff_w[63:0]),
  .edp_rd_ff_w2(edp_rd_ff_w2[63:0]),
  .tlu_cerer_irf(tlu_cerer_irf),
  .tlu_ceter_pscce(tlu_ceter_pscce[3:0]),
  .lsu_asi_error_inject_b31(lsu_asi_error_inject_b31),
  .lsu_asi_error_inject_b25(lsu_asi_error_inject_b25),
  .lsu_asi_error_inject(lsu_asi_error_inject[7:0]),
  .ecc_w_synd_w(ecc_w_synd_w[7:0]),
  .ecc_w2_synd_w2(ecc_w2_synd_w2[7:0]),
  .ecc_mbist_write_data_p4(ecc_mbist_write_data_p4[7:0]),
  .ect_ex_emb_clken(ect_ex_emb_clken),
  .ect_tg_clken(ect_tg_clken),
  .ect_tid_lth_e(ect_tid_lth_e[1:0]),
  .ect_rs1_valid_e(ect_rs1_valid_e),
  .ect_rs2_valid_e(ect_rs2_valid_e),
  .ect_rs3_valid_e(ect_rs3_valid_e),
  .ect_two_cycle_m(ect_two_cycle_m),
  .ect_rs1_addr_e(ect_rs1_addr_e[4:0]),
  .ect_rs2_addr_e(ect_rs2_addr_e[4:0]),
  .ect_rs3_addr_e(ect_rs3_addr_e[4:0]),
  .edp_rcc_data_e(edp_rcc_data_e[63:0]),
  .exu_rs2_data_e(exu_rs2_data_e[63:0]),
  .edp_rs3_data_e(edp_rs3_data_e[63:0]),
  .edp_rcc_ecc_e(edp_rcc_ecc_e[7:0]),
  .edp_rs2_ecc_e(edp_rs2_ecc_e[7:0]),
  .edp_rs3_ecc_e(edp_rs3_ecc_e[7:0]),
  .dec_valid_e(dec_valid_e),
  .dec_flush_m(dec_flush_m),
  .exu_ecc_check_m(exu_ecc_check_m[7:0]),
  .exu_ecc_addr_m(exu_ecc_addr_m[4:0]),
  .exu_ecc_m(exu_ecc_m),
  .exu_cecc_m(exu_cecc_m),
  .exu_uecc_m(exu_uecc_m)
);

exu_rml_ctl  rml (		// FS:wmr_protect
.wmr_scan_in(rml_wmr_scanin),
.wmr_scan_out(rml_wmr_scanout),
.scan_in(rml_scanin),
.scan_out(rml_scanout),
.l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .spc_aclk_wmr(spc_aclk_wmr),
  .tcu_scan_en(tcu_scan_en),
  .dec_tid_p(dec_tid_p[1:0]),
  .dec_inst_d(dec_inst_d[31:13]),
  .dec_valid_e(dec_valid_e),
  .dec_thread_group(dec_thread_group),
  .tlu_flush_exu_b(tlu_flush_exu_b),
  .dec_flush_m(dec_flush_m),
  .dec_flush_b(dec_flush_b),
  .tlu_gl_thr0(tlu_gl_thr0[1:0]),
  .tlu_gl_thr1(tlu_gl_thr1[1:0]),
  .tlu_gl_thr2(tlu_gl_thr2[1:0]),
  .tlu_gl_thr3(tlu_gl_thr3[1:0]),
  .tlu_ccr_cwp_valid(tlu_ccr_cwp_valid),
  .tlu_ccr_cwp_tid(tlu_ccr_cwp_tid[1:0]),
  .tlu_cwp(tlu_cwp[2:0]),
  .mbi_run(mbi_run),
  .mbi_addr(mbi_addr[9:0]),
  .mbi_irf_read_en(mbi_irf_read_en),
  .mbi_irf_save_en(mbi_irf_save_en),
  .mbi_irf_restore_en(mbi_irf_restore_en),
  .edp_rng_in_ff(edp_rng_in_ff[64:0]),
  .edp_rd_ff_w(edp_rd_ff_w[63:32]),
  .ect_misaligned_error_m(ect_misaligned_error_m),
  .ect_yreg_wr_w(ect_yreg_wr_w),
  .ect_tid_lth_w(ect_tid_lth_w[1:0]),
  .exu_lsu_va_error_m(exu_lsu_va_error_m),
  .exu_ecc_m(exu_ecc_m),
  .edp_rs3_ecc_e(edp_rs3_ecc_e[7:0]),
  .ect_tg_clken(ect_tg_clken),
  .exu_y_data_e(exu_y_data_e[31:0]),
  .exu_fill_m(exu_fill_m),
  .exu_spill_b(exu_spill_b),
  .exu_normal_b(exu_normal_b),
  .exu_cleanwin_b(exu_cleanwin_b),
  .exu_wstate_b(exu_wstate_b[2:0]),
  .exu_cwp_thr0(exu_cwp_thr0[2:0]),
  .exu_cwp_thr1(exu_cwp_thr1[2:0]),
  .exu_cwp_thr2(exu_cwp_thr2[2:0]),
  .exu_cwp_thr3(exu_cwp_thr3[2:0]),
  .exu_oddwin_b(exu_oddwin_b[3:0]),
  .exu_window_block_m(exu_window_block_m),
  .exu_tlu_window_block(exu_tlu_window_block),
  .exu_ecc_winop_flush_m(exu_ecc_winop_flush_m),
  .exu_test_valid(exu_test_valid),
  .exu_test_tid(exu_test_tid[1:0]),
  .exu_test_addr(exu_test_addr[4:0]),
  .rml_test_valid_d(rml_test_valid_d),
  .rml_rng_data_out(rml_rng_data_out[5:0]),
  .rml_rng_rd_ctl(rml_rng_rd_ctl[4:0]),
  .rml_rng_ack_ctl(rml_rng_ack_ctl[1:0]),
  .rml_rng_ack_cwp_tid(rml_rng_ack_cwp_tid[1:0]),
  .rml_rng_ack_ecc_tid(rml_rng_ack_ecc_tid[1:0]),
  .rml_rng_ack_det_vld(rml_rng_ack_det_vld),
  .rml_rng_wt_imask_ctl(rml_rng_wt_imask_ctl),
  .rml_rng_wt_ccr_ctl(rml_rng_wt_ccr_ctl),
  .rml_irf_ecc_data(rml_irf_ecc_data[7:0]),
  .rml_rng_ack_sel_ctl(rml_rng_ack_sel_ctl),
  .rml_rng_y_data(rml_rng_y_data[31:0]),
  .rml_irf_cwpswap_tid_m(rml_irf_cwpswap_tid_m[1:0]),
  .rml_irf_old_lo_cwp_m(rml_irf_old_lo_cwp_m[2:0]),
  .rml_irf_old_e_cwp_m(rml_irf_old_e_cwp_m[2:1]),
  .rml_irf_cwpswap_tid_b(rml_irf_cwpswap_tid_b[1:0]),
  .rml_irf_new_lo_cwp_b(rml_irf_new_lo_cwp_b[2:0]),
  .rml_irf_new_e_cwp_b(rml_irf_new_e_cwp_b[2:1]),
  .rml_irf_save_even_m(rml_irf_save_even_m),
  .rml_irf_save_odd_m(rml_irf_save_odd_m),
  .rml_irf_save_local_m(rml_irf_save_local_m),
  .rml_irf_restore_even_b(rml_irf_restore_even_b),
  .rml_irf_restore_odd_b(rml_irf_restore_odd_b),
  .rml_irf_restore_local_b(rml_irf_restore_local_b),
  .rml_irf_global_tid(rml_irf_global_tid[1:0]),
  .rml_irf_global_tid_ff(rml_irf_global_tid_ff[1:0]),
  .rml_irf_old_agp(rml_irf_old_agp[1:0]),
  .rml_irf_new_agp_ff(rml_irf_new_agp_ff[1:0]),
  .rml_irf_save_global(rml_irf_save_global),
  .rml_irf_restore_global(rml_irf_restore_global)
);


//     Note    : All IRF READ/WRITE/SAVE/RESTORE pins are flopped inside the IRF.
//     Note    : The save and restore have one full cycle to decode.  The actual save or restore will occur in the 1st phase of the cycle after decode.
//     Note    : The READ and WRITE decode in the 1st phase and the actual read/write occurs in the 2nd phase.

//     Note    : To delay a signal in a 0in assertion : use    "$0in_delay(signal_name,# of cycles)"     example $0in_delay(a_wr_en_p0,1)


// 0. N2 : Read and Write without bypassing
// 1. N1 : WRITE p0 and WRITE p1 to the same TID in the same cycle
// 2. N2 : Any WRITE   port followed by a SAVE    in the 1st phase of next cycle (coded as the SAVE    pins the same  cycle as the WRITE pins)
// 3. N1 : Any WRITE   port followed by a RESTORE in the 1st phase of next cycle (coded as the RESTORE pins the same  cycle as the WRITE pins)
// 4. N1 : Any READ    port followed by a SAVE    in the 1st phase of next cycle (coded as the SAVE    pins the same  cycle as the READ  pins)
// 5. N1 : Any READ    port followed by a RESTORE in the 1st phase of next cycle (coded as the RESTORE pins the same  cycle as the READ  pins)
// 6. N2 : Any SAVE    port followed by a READ    in the              same cycle (coded as the SAVE    pins one cycle ahead of the READ  pins)
// 7. N2 : Any RESTORE port followed by a READ    in the              same cycle (coded as the RESTORE pins one cycle ahead of the READ  pins)
// 8. N2 : Any SAVE    port followed by a WRITE   in the              same cycle (coded as the SAVE    pins one cycle ahead as the WRITE pins)
// 9. N2 : Any RESTORE port followed by a WRITE   in the              same cycle (coded as the RESTORE pins one cycle ahead as the WRITE pins)


// #0
// 0in custom -fire ( $0in_delay((dec_inst_rs1_vld_p & ect_valid_lth_w & (dec_tid_p[1:0] == ect_tid_lth_w[1:0])  & (dec_inst_rs1_p[4:0] == ect_rd_lth_w[4:0] )),1) & (ect_rs1_late_sel_d[3:1] == 3'b000 )) -message "IRF p0 write & p0 read without bypass" -group core_array
// 0in custom -fire ( $0in_delay((dec_inst_rs2_vld_p & ect_valid_lth_w & (dec_tid_p[1:0] == ect_tid_lth_w[1:0])  & (dec_inst_rs2_p[4:0] == ect_rd_lth_w[4:0] )),1) & (ect_rs2_late_sel_d[3:0] == 4'b0000)) -message "IRF p0 write & p1 read without bypass" -group core_array
// 0in custom -fire ( $0in_delay((dec_inst_rs3_vld_p & ect_valid_lth_w & (dec_tid_p[1:0] == ect_tid_lth_w[1:0])  & (dec_inst_rs3_p[4:0] == ect_rd_lth_w[4:0] )),1) & (ect_rs3_late_sel_d[3:0] == 4'b0000)) -message "IRF p0 write & p2 read without bypass" -group core_array
// 0in custom -fire ( $0in_delay((dec_inst_rs1_vld_p & ect_valid_in_w2 & (dec_tid_p[1:0] == ect_tid_lth_w2[1:0]) & (dec_inst_rs1_p[4:0] == ect_rd_lth_w2[4:0])),1) & (ect_rs1_late_sel_d[3:1] == 3'b000 )) -message "IRF p1 write & p0 read without bypass" -group core_array
// 0in custom -fire ( $0in_delay((dec_inst_rs2_vld_p & ect_valid_in_w2 & (dec_tid_p[1:0] == ect_tid_lth_w2[1:0]) & (dec_inst_rs2_p[4:0] == ect_rd_lth_w2[4:0])),1) & (ect_rs2_late_sel_d[3:0] == 4'b0000)) -message "IRF p1 write & p1 read without bypass" -group core_array
// 0in custom -fire ( $0in_delay((dec_inst_rs3_vld_p & ect_valid_in_w2 & (dec_tid_p[1:0] == ect_tid_lth_w2[1:0]) & (dec_inst_rs3_p[4:0] == ect_rd_lth_w2[4:0])),1) & (ect_rs3_late_sel_d[3:0] == 4'b0000)) -message "IRF p1 write & p2 read without bypass" -group core_array

// #1
// 0in custom -fire (ect_valid_lth_w &  ect_valid_in_w2                                            & (ect_tid_lth_w[1:0]  == ect_tid_lth_w2[1:0])           ) -message "IRF p0 & p1 ports wrote to same TID" -group core_array

// #2
// 0in custom -fire (ect_valid_lth_w & (rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ) & (ect_tid_lth_w[1:0]  == rml_irf_cwpswap_tid_m[1:0])) -message "IRF p0 write & save            to same TID" -group core_array
// 0in custom -fire (ect_valid_in_w2 & (rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ) & (ect_tid_lth_w2[1:0] == rml_irf_cwpswap_tid_m[1:0])) -message "IRF p1 write & save            to same TID" -group core_array
// 0in custom -fire (ect_valid_lth_w &  rml_irf_save_global                                                       & (ect_tid_lth_w[1:0]  == rml_irf_global_tid[1:0])   ) -message "IRF p0 write & save     global to same TID" -group core_array
// 0in custom -fire (ect_valid_in_w2 &  rml_irf_save_global                                                       & (ect_tid_lth_w2[1:0] == rml_irf_global_tid[1:0])   ) -message "IRF p1 write & save     global to same TID" -group core_array

// #3
// 0in custom -fire (ect_valid_lth_w & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (ect_tid_lth_w[1:0]  == rml_irf_cwpswap_tid_b[1:0])) -message "IRF p0 write & restore        to same TID" -group core_array
// 0in custom -fire (ect_valid_in_w2 & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (ect_tid_lth_w2[1:0] == rml_irf_cwpswap_tid_b[1:0])) -message "IRF p1 write & restore        to same TID" -group core_array
// 0in custom -fire (ect_valid_lth_w &  rml_irf_restore_global                                                    & (ect_tid_lth_w[1:0]  == rml_irf_global_tid_ff[1:0])) -message "IRF p0 write & restore global to same TID" -group core_array
// 0in custom -fire (ect_valid_in_w2 &  rml_irf_restore_global                                                    & (ect_tid_lth_w2[1:0] == rml_irf_global_tid_ff[1:0])) -message "IRF p1 write & restore global to same TID" -group core_array

// #4
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & (rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_m[1:0])),2))) -message "IRF p0 read  & save           to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p &  rml_irf_save_global                                                       & (dec_tid_p[1:0] == rml_irf_global_tid[1:0]   )),2))) -message "IRF p0 read  & save    global to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & (rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_m[1:0])),2))) -message "IRF p1 read  & save           to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p &  rml_irf_save_global                                                       & (dec_tid_p[1:0] == rml_irf_global_tid[1:0]   )),2))) -message "IRF p1 read  & save    global to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & (rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_m[1:0])),2))) -message "IRF p2 read  & save           to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p &  rml_irf_save_global                                                       & (dec_tid_p[1:0] == rml_irf_global_tid[1:0]   )),2))) -message "IRF p2 read  & save    global to same TID" -group core_array


// #5
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_b[1:0])),2))) -message "IRF p0 read  & restore        to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p &  rml_irf_restore_global                                                    & (dec_tid_p[1:0] == rml_irf_global_tid_ff[1:0])),2))) -message "IRF p0 read  & restore global to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_b[1:0])),2))) -message "IRF p1 read  & restore        to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p &  rml_irf_restore_global                                                    & (dec_tid_p[1:0] == rml_irf_global_tid_ff[1:0])),2))) -message "IRF p1 read  & restore global to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & (rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b) & (dec_tid_p[1:0] == rml_irf_cwpswap_tid_b[1:0])),2))) -message "IRF p2 read  & restore        to same TID" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p &  rml_irf_restore_global                                                    & (dec_tid_p[1:0] == rml_irf_global_tid_ff[1:0])),2))) -message "IRF p2 read  & restore global to same TID" -group core_array


// #6
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & $0in_delay((rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))),2))) -message "IRF p0 read  & save           to same TID in same cycle" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & $0in_delay( rml_irf_save_global                                                      ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid[1:0]   ,1))),2))) -message "IRF p0 read  & save    global to same TID in same cycle" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & $0in_delay((rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))),2))) -message "IRF p1 read  & save           to same TID in same cycle" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & $0in_delay( rml_irf_save_global                                                      ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid[1:0]   ,1))),2))) -message "IRF p1 read  & save    global to same TID in same cycle" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & $0in_delay((rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))),2))) -message "IRF p2 read  & save           to same TID in same cycle" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & $0in_delay( rml_irf_save_global                                                      ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid[1:0]   ,1))),2))) -message "IRF p2 read  & save    global to same TID in same cycle" -group core_array


// #7    fails isa3_scratchpad_f2.s single thread at 130000
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))),2))) -message "IRF p0 read  & restore        to same TID in same cycle" -name "EXU_7a" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs1_vld_p & $0in_delay( rml_irf_restore_global                                                   ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))),2))) -message "IRF p0 read  & restore global to same TID in same cycle" -name "EXU_7b" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))),2))) -message "IRF p1 read  & restore        to same TID in same cycle" -name "EXU_7c" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs2_vld_p & $0in_delay( rml_irf_restore_global                                                   ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))),2))) -message "IRF p1 read  & restore global to same TID in same cycle" -name "EXU_7d" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))),2))) -message "IRF p2 read  & restore        to same TID in same cycle" -name "EXU_7e" -group core_array
// 0in custom -fire (dec_valid_e & ($0in_delay((dec_inst_rs3_vld_p & $0in_delay( rml_irf_restore_global                                                   ,1) & (dec_tid_p[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))),2))) -message "IRF p2 read  & restore global to same TID in same cycle" -name "EXU_7f" -group core_array


// #8
// 0in custom -fire (ect_valid_lth_w & $0in_delay((rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ),1) & (ect_tid_lth_w[1:0]  == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))) -message "IRF p0 write & save            to same TID in same cycle" -group core_array
// 0in custom -fire (ect_valid_in_w2 & $0in_delay((rml_irf_save_odd_m    | rml_irf_save_local_m    | rml_irf_save_even_m   ),1) & (ect_tid_lth_w2[1:0] == $0in_delay(rml_irf_cwpswap_tid_m[1:0],1))) -message "IRF p1 write & save            to same TID in same cycle" -group core_array
// 0in custom -fire (ect_valid_lth_w & $0in_delay( rml_irf_save_global                                                      ,1) & (ect_tid_lth_w[1:0]  == $0in_delay(rml_irf_global_tid[1:0]   ,1))) -message "IRF p0 write & save     global to same TID in same cycle" -group core_array
// 0in custom -fire (ect_valid_in_w2 & $0in_delay( rml_irf_save_global                                                      ,1) & (ect_tid_lth_w2[1:0] == $0in_delay(rml_irf_global_tid[1:0]   ,1))) -message "IRF p1 write & save     global to same TID in same cycle" -group core_array

// #9
// 0in custom -fire (ect_valid_lth_w & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (ect_tid_lth_w[1:0]  == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))) -message "IRF p0 write & restore        to same TID in same cycle" -group core_array
// 0in custom -fire (ect_valid_in_w2 & $0in_delay((rml_irf_restore_odd_b | rml_irf_restore_local_b | rml_irf_restore_even_b),1) & (ect_tid_lth_w2[1:0] == $0in_delay(rml_irf_cwpswap_tid_b[1:0],1))) -message "IRF p1 write & restore        to same TID in same cycle" -group core_array
// 0in custom -fire (ect_valid_lth_w & $0in_delay( rml_irf_restore_global                                                   ,1) & (ect_tid_lth_w[1:0]  == $0in_delay(rml_irf_global_tid_ff[1:0],1))) -message "IRF p0 write & restore global to same TID in same cycle" -group core_array
// 0in custom -fire (ect_valid_in_w2 & $0in_delay( rml_irf_restore_global                                                   ,1) & (ect_tid_lth_w2[1:0] == $0in_delay(rml_irf_global_tid_ff[1:0],1))) -message "IRF p1 write & restore global to same TID in same cycle" -group core_array


n2_irf_mp_128x72_cust irf (

  .scan_in(irf_scanin),
  .scan_out(irf_scanout),
  .l2clk			( l2clk							),
  .tcu_pce_ov			( tcu_pce_ov						),
  .tcu_aclk			( spc_aclk						),
  .tcu_bclk			( spc_bclk						),
  .clken			( ect_tg_clken						),

  .rd_tid			( dec_tid_p[1:0]					),
  .rd_addr_p0			( dec_inst_rs1_p[4:0]					),
  .rd_addr_p1			( dec_inst_rs2_p[4:0]					),
  .rd_addr_p2			( dec_inst_rs3_p[4:0]					),
  .rd_en_p0			( dec_inst_rs1_vld_p					),
  .rd_en_p1			( dec_inst_rs2_vld_p					),
  .rd_en_p2			( dec_inst_rs3_vld_p					),

  .wr_en_p0			( ect_valid_lth_w					),
  .wr_tid_p0			( ect_tid_lth_w[1:0]					),
  .wr_addr_p0			( ect_rd_lth_w[4:0]					),
  .wr_data_p0			({ecc_w_synd_w[7:0]   , edp_rd_ff_w[63:0]}		),
  .wr_en_p1			( ect_valid_in_w2					),
  .wr_tid_p1			( ect_tid_lth_w2[1:0]					),
  .wr_addr_p1			( ect_rd_lth_w2[4:0]					),
  .wr_data_p1			({ecc_w2_synd_w2[7:0] , edp_rd_ff_w2[63:0]}		),

  .save_tid			( rml_irf_cwpswap_tid_m[1:0]       			),
  .save_local_addr	 	( rml_irf_old_lo_cwp_m[2:0]           			),
  .save_even_addr       	( rml_irf_old_e_cwp_m[2:1]            			),
  .save_odd_addr	       	( rml_irf_old_lo_cwp_m[2:1]           			),
  .save_even_en		  	( rml_irf_save_even_m            			),
  .save_odd_en		   	( rml_irf_save_odd_m             			),
  .save_local_en	 	( rml_irf_save_local_m           			),

  .restore_tid			( rml_irf_cwpswap_tid_b[1:0]       			),
  .restore_local_addr		( rml_irf_new_lo_cwp_b[2:0]           			),
  .restore_even_addr       	( rml_irf_new_e_cwp_b[2:1]            			),
  .restore_odd_addr       	( rml_irf_new_lo_cwp_b[2:1]           			),
  .restore_even_en	  	( rml_irf_restore_even_b            			),
  .restore_odd_en	   	( rml_irf_restore_odd_b             			),
  .restore_local_en	 	( rml_irf_restore_local_b           			),

  .save_global_en	  	( rml_irf_save_global            			),
  .save_global_tid	   	( rml_irf_global_tid[1:0]             			),
  .save_global_addr     	( rml_irf_old_agp[1:0]                			),

  .restore_global_en	  	( rml_irf_restore_global            			),
  .restore_global_tid	   	( rml_irf_global_tid_ff[1:0]         			),
  .restore_global_addr      	( rml_irf_new_agp_ff[1:0]                		),


	.dout_p0			( irf_rs1_data_d[71:0]					),
	.dout_p1			( irf_rs2_data_d[71:0]					),
	.dout_p2			( irf_rs3_data_d[71:0]					),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_in(tcu_se_scancollar_in));


//********************************************************************************
//
//                             Instruction Notes
//
//
//  Opcode         Page   FUNCTION                     Comments                        Implementation
//  ------         ----   ------------------------     -----------------------         --------------
//	           
//                                       Add/Sub
//	           
//  ADD            135     rs1 +  rs2
//  ADDcc          135     rs1 +  rs2                              CCR.icc,xcc
//  ADDC           135     rs1 +  rs2       + icc.c    		    
//  ADDCcc         135     rs1 +  rs2       + icc.c                CCR.icc,xcc
//  ADDi           135     rs1 +  sext(imm)            imm=[12:0]	    
//  ADDcci         135     rs1 +  sext(imm)            imm=[12:0]  CCR.icc,xcc
//  ADDCi          135     rs1 +  sext(imm) + icc.c    imm=[12:0]	    
//  ADDCcci        135     rs1 +  sext(imm) + icc.c    imm=[12:0]  CCR.icc,xcc
//	           
//  SUB            230     rs1 -  rs2
//  SUBcc          230     rs1 -  rs2                              CCR.icc,xcc
//  SUBC           230     rs1 -  rs2       + icc.c    		    
//  SUBCcc         230     rs1 -  rs2       + icc.c                CCR.icc,xcc
//  SUBi           230     rs1 -  sext(imm)            imm=[12:0]	    
//  SUBcci         230     rs1 -  sext(imm)            imm=[12:0]  CCR.icc,xcc
//  SUBCi          230     rs1 -  sext(imm) + icc.c    imm=[12:0]	    
//  SUBCcci        230     rs1 -  sext(imm) + icc.c    imm=[12:0]  CCR.icc,xcc
//	           
//	           
//                                       Logical
//	           
//  AND            181     rs1 &  rs2                                                  lg_sel=1000
//  ANDcc          181     rs1 &  rs2                              CCR.icc,xcc         lg_sel=1000
//  ANDN           181     rs1 & ~rs2	                                                 lg_sel=0100
//  ANDNcc         181     rs1 & ~rs2                              CCR.icc,xcc         lg_sel=0100
//  OR             181     rs1 |  rs2                                                  lg_sel=1110
//  ORcc           181     rs1 |  rs2                              CCR.icc,xcc         lg_sel=1110
//  ORN            181     rs1 | ~rs2	                                                 lg_sel=1101
//  ORNcc          181     rs1 | ~rs2                              CCR.icc,xcc         lg_sel=1101
//  XOR            181     rs1 ^  rs2                           	                 lg_sel=0110
//  XORcc          181     rs1 ^  rs2                              CCR.icc,xcc         lg_sel=0110
//  XORN           181     rs1 ^ ~rs2                                                  lg_sel=1001
//  XORNcc         181     rs1 ^ ~rs2                              CCR.icc,xcc         lg_sel=1001
//  ANDi           181     rs1 &  sext(imm)            imm=[12:0]                      lg_sel=1000
//  ANDcci         181     rs1 &  sext(imm)            imm=[12:0]  CCR.icc,xcc         lg_sel=1000
//  ANDNi          181     rs1 & ~sext(imm)            imm=[12:0]                      lg_sel=0100
//  ANDNcci        181     rs1 & ~sext(imm)            imm=[12:0]  CCR.icc,xcc         lg_sel=0100
//  ORi            181     rs1 |  sext(imm)            imm=[12:0]                      lg_sel=1110
//  ORcci          181     rs1 |  sext(imm)            imm=[12:0]  CCR.icc,xcc         lg_sel=1110
//  ORNi           181     rs1 | ~sext(imm)            imm=[12:0]                      lg_sel=1101
//  ORNcci         181     rs1 | ~sext(imm)            imm=[12:0]  CCR.icc,xcc         lg_sel=1101
//  XORi           181     rs1 ^  sext(imm)            imm=[12:0] 	                 lg_sel=0110
//  XORcci         181     rs1 ^  sext(imm)            imm=[12:0]  CCR.icc,xcc         lg_sel=0110
//  XORNi          181     rs1 ^ ~sext(imm)            imm=[12:0]                      lg_sel=1001
//  XORNcci        181     rs1 ^ ~sext(imm)            imm=[12:0]  CCR.icc,xcc         lg_sel=1001
//	           
//  SETHI          217     {32'b0,imm[21:0],10'b0}     NOP if rd=0 & imm=0
//	           
//	           
//                                       Shift
//	           
//  SLL            218     shift_left(rs1)  fill w/ 0  sa=rs2[4:0]                     sh_sel=0100001
//  SRL            218     shift_right(rs1) fill w/ 0  sa=rs2[4:0] rd[63:32]=32'b0     sh_sel=1000001
//  SRA            218     shift_right(rs1) w/ sext    sa=rs2[4:0] rd[63:32]=rs1[31]   sh_sel=1001001
//  SLLX           218     shift_left(rs1)  fill w/ 0  sa=rs2[5:0]                     sh_sel=0100010
//  SRLX           218     shift_right(rs1) fill w/ 0  sa=rs2[5:0]                     sh_sel=1000100
//  SRAX           218     shift_right(rs1) w/ sext    sa=rs2[5:0]                     sh_sel=1010100
//	           
//  SLLi           218     shift_left(rs1)  fill w/ 0  sa=rs2[4:0]                     sh_sel=0100001
//  SRLi           218     shift_right(rs1) fill w/ 0  sa=rs2[4:0] rd[63:32]=32'b0     sh_sel=1000001
//  SRAi           218     shift_right(rs1) w/ sext    sa=rs2[4:0] rd[63:32]=rs1[31]   sh_sel=1001001
//  SLLXi          218     shift_left(rs1)  fill w/ 0  sa=rs2[5:0]                     sh_sel=0100010
//  SRLXi          218     shift_right(rs1) fill w/ 0  sa=rs2[5:0]                     sh_sel=1000100
//  SRAXi          218     shift_right(rs1) w/ sext    sa=rs2[5:0]                     sh_sel=1010100
//	           
//                 VIS
//  EDGE8          70      Eight  8-bit Edge
//  EDGE8N         70      Eight  8-bit Edge; no CC
//  EDGE8L         70      Eight  8-bit Edge;        Little-Endian
//  EDGE8LN        70      Eight  8-bit Edge; no CC; Little-Endian
//  EDGE16         70      Four  16-bit Edge
//  EDGE16N        70      Four  16-bit Edge; no CC
//  EDGE16L        70      Four  16-bit Edge;        Little-Endian
//  EDGE16LN       70      Four  16-bit Edge; no CC; Little-Endian
//  EDGE32         70      Two   32-bit Edge
//  EDGE32N        70      Two   32-bit Edge; no CC
//  EDGE32L        70      Two   32-bit Edge;        Little-Endian
//  EDGE32LN       70      Two   32-bit Edge; no CC; Little-Endian
//	           
//	           
//  ARRAY8         74      Convert  8-bit 3-D addres to blocked byte address
//  ARRAY16        74      Convert 16-bit 3-D addres to blocked byte address
//  ARRAY32        74      Convert 32-bit 3-D addres to blocked byte address
//
//
//  ALIGNADDRESS   55      RD = rs1 + rs2; clip low 3 bits;  GSR <-  low  3 bits
//  ALIGNADDRESS-little    RD = rs1 + rs2; clip low 3 bits;  GSR <- ~low  3 bits
//  BMASK          55      RD = rs1 + rs2; clip low 3 bits;  GSR <-  low 32 bits


// fixscan start:
assign edp_scanin                = scan_in                  ;
assign ect_scanin                = edp_scanout              ;
assign ecc_scanin                = ect_scanout              ;
assign rml_scanin                = ecc_scanout              ;
assign irf_scanin                = rml_scanout              ;
assign scan_out                  = irf_scanout              ;

assign ect_wmr_scanin            = wmr_scan_in              ;
assign rml_wmr_scanin            = ect_wmr_scanout          ;
assign wmr_scan_out              = rml_wmr_scanout          ;
// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: exu_ecc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module exu_ecc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  ect_mbist_sel, 
  mbi_write_data_p1, 
  edp_rd_ff_w, 
  edp_rd_ff_w2, 
  tlu_cerer_irf, 
  tlu_ceter_pscce, 
  lsu_asi_error_inject_b31, 
  lsu_asi_error_inject_b25, 
  lsu_asi_error_inject, 
  ecc_w_synd_w, 
  ecc_w2_synd_w2, 
  ecc_mbist_write_data_p4, 
  ect_ex_emb_clken, 
  ect_tg_clken, 
  ect_tid_lth_e, 
  ect_rs1_valid_e, 
  ect_rs2_valid_e, 
  ect_rs3_valid_e, 
  ect_two_cycle_m, 
  ect_rs1_addr_e, 
  ect_rs2_addr_e, 
  ect_rs3_addr_e, 
  edp_rcc_data_e, 
  exu_rs2_data_e, 
  edp_rs3_data_e, 
  edp_rcc_ecc_e, 
  edp_rs2_ecc_e, 
  edp_rs3_ecc_e, 
  dec_valid_e, 
  dec_flush_m, 
  exu_ecc_check_m, 
  exu_ecc_addr_m, 
  exu_ecc_m, 
  exu_cecc_m, 
  exu_uecc_m, 
  scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk_pm1;
wire l1clk_pm2;
wire mbist_ff_scanin;
wire mbist_ff_scanout;
wire [7:0] mbi_write_data_p2;
wire [7:0] mbi_write_data_p3;
wire ecc_mask_en_in;
wire debug_ff_scanin;
wire debug_ff_scanout;
wire cerer_irf_ff;
wire [3:0] ceter_pscce_ff;
wire [7:0] ecc_mask_data_ff;
wire ecc_mask_en_ff;
wire ecc_valid_e;
wire ecc_enable_e;
wire [63:0] d1_e;
wire [7:0] p1_e;
wire [63:0] d2_e;
wire [7:0] p2_e;
wire [63:0] d3_e;
wire [7:0] p3_e;
wire rs1_ne_e;
wire rs1_parity_e;
wire [6:0] q1_e;
wire rs1_ce_e;
wire rs1_ue_e;
wire rs2_ne_e;
wire rs2_parity_e;
wire [6:0] q2_e;
wire rs2_ce_e;
wire rs2_ue_e;
wire rs3_ce_e;
wire rs3_parity_e;
wire rs3_ue_e;
wire [6:0] q3_e;
wire [7:0] check_e;
wire [4:0] addr_e;
wire check_e_to_m_scanin;
wire check_e_to_m_scanout;
wire addr_e_to_m_scanin;
wire addr_e_to_m_scanout;
wire cecc_e;
wire uecc_e;
wire ecc_ecc_e;
wire ecc_uecc_e;
wire ecc_cecc_e;
wire ce_ue_ecc_flops_scanin;
wire ce_ue_ecc_flops_scanout;
wire [7:0] ecc_mask_b;
wire [63:0] w_d;
wire [7:0] w_p_b;
wire [63:0] w2_d;
wire [7:0] w2_p_w;
wire spares_scanin;
wire spares_scanout;


// *** Global Inputs ***

input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;			// scan signals
input 		spc_aclk;
input 		spc_bclk;
input 		tcu_scan_en;

input		ect_mbist_sel;			// MBIST
input  [7:0]	mbi_write_data_p1; 		// MBIST


// *** Generate ECC  Local  Inputs *** 

input  [63:0]	edp_rd_ff_w;			// w  port data
input  [63:0]	edp_rd_ff_w2;			// w2 port data 

input		tlu_cerer_irf;			// IRF ecc error trap enable
input  [3:0]	tlu_ceter_pscce;		// core error trap enable reg precise enable

input		lsu_asi_error_inject_b31;	// [31]=global inject en
input		lsu_asi_error_inject_b25;	// [25]=IRF inject en
input  [7:0]	lsu_asi_error_inject;		// [7:0]=mask


// *** Generate ECC  Local  Outputs *** 

output [7:0]	ecc_w_synd_w;			// Generated ECC to IRF W port
output [7:0]	ecc_w2_synd_w2;			// Generated ECC to IRF W2 port
output [7:0]	ecc_mbist_write_data_p4;	// MBIST

// *** Check ECC  Local  Inputs *** 

input		ect_ex_emb_clken;		// Power Management
input		ect_tg_clken;			// Power Management

input  [1:0]	ect_tid_lth_e;

input      	ect_rs1_valid_e;		// Source register valid bit
input      	ect_rs2_valid_e;		// - available at output of flop
input      	ect_rs3_valid_e;        	// - signals valid rs data 
input		ect_two_cycle_m;

input  [4:0]	ect_rs1_addr_e;			// Source register address
input  [4:0]	ect_rs2_addr_e;			// - available at output of flop
input  [4:0]	ect_rs3_addr_e;			// - addr for IRF physical active window

input  [63:0]	edp_rcc_data_e;			// Source register ECC and data bit
input  [63:0]	exu_rs2_data_e;			// - available at output of flop
input  [63:0]	edp_rs3_data_e;
input  [7:0]	edp_rcc_ecc_e;
input  [7:0]	edp_rs2_ecc_e;
input  [7:0]	edp_rs3_ecc_e;


input		dec_valid_e;
input		dec_flush_m;


// *** Global Outputs ***

output [7:0]	exu_ecc_check_m;
output [4:0]	exu_ecc_addr_m;

output		exu_ecc_m;

output 		exu_cecc_m;			// Flag for detected   correctable ECC error 
output 		exu_uecc_m;			// Flag for detected uncorrectable ECC error 


// *** Local  Outputs ***

output		scan_out;


// scan renames
assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se	= tcu_scan_en;
// end scan

exu_ecc_ctl_l1clkhdr_ctl_macro clkgen_pm1	(
 .l2clk( l2clk			),
 .l1en ( ect_tg_clken		),
 .l1clk( l1clk_pm1		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


exu_ecc_ctl_l1clkhdr_ctl_macro clkgen_pm2	(
 .l2clk( l2clk			),
 .l1en ( ect_ex_emb_clken	),
 .l1clk( l1clk_pm2		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


exu_ecc_ctl_msff_ctl_macro__width_24 mbist_ff 	 (
 .scan_in(mbist_ff_scanin),
 .scan_out(mbist_ff_scanout),
 .l1clk( l1clk_pm1										),
 .din  ({mbi_write_data_p1[7:0]    , mbi_write_data_p2[7:0] , mbi_write_data_p3[7:0]}		),
 .dout ({mbi_write_data_p2[7:0]    , mbi_write_data_p3[7:0] , ecc_mbist_write_data_p4[7:0]}	),
  .siclk(siclk),
  .soclk(soclk));


assign ecc_mask_en_in	= lsu_asi_error_inject_b31 & lsu_asi_error_inject_b25;

exu_ecc_ctl_msff_ctl_macro__width_14 debug_ff 	 (
 .scan_in(debug_ff_scanin),
 .scan_out(debug_ff_scanout),
 .l1clk( l1clk_pm1										),
 .din  ({tlu_cerer_irf , tlu_ceter_pscce[3:0] , lsu_asi_error_inject[7:0] , ecc_mask_en_in}	),
 .dout ({cerer_irf_ff  , ceter_pscce_ff[3:0]  , ecc_mask_data_ff[7:0]     , ecc_mask_en_ff}	),
  .siclk(siclk),
  .soclk(soclk));


assign ecc_valid_e	= dec_valid_e | (ect_two_cycle_m & ~dec_flush_m);

assign ecc_enable_e	= ( ecc_valid_e &  cerer_irf_ff & ceter_pscce_ff[0] & (ect_tid_lth_e[1:0] == 2'b00)) |
			  ( ecc_valid_e &  cerer_irf_ff & ceter_pscce_ff[1] & (ect_tid_lth_e[1:0] == 2'b01)) |
			  ( ecc_valid_e &  cerer_irf_ff & ceter_pscce_ff[2] & (ect_tid_lth_e[1:0] == 2'b10)) |
			  ( ecc_valid_e &  cerer_irf_ff & ceter_pscce_ff[3] & (ect_tid_lth_e[1:0] == 2'b11));


/////////////////////////////////////////////////////////////////////////////
// ECC Error Dectection Logic
//-----------------------------
// - Regenerate ECC [6:0] and compare against retrived ECC
// - Check ECC [7] with parity
// - Outputs the result of the detection:
//   - ne: no error - either no valid data to check, 
//                    or ECC [6:0] all matched 
//   - ce: correctable error
//                  - parity is 1, so an odd number of bits flipped,
//                    and ECC data is valid and regenerated ECC did not match
//   - ue: uncorrectable error
//                  - parity is 0, so an even number of bits flipped,
//                    and ECC data is valid and regenerated ECC did not match
//                  - implies more than one bit was corrupted
/////////////////////////////////////////////////////////////////////////////

// renaming inputs for shorter assign statements
assign d1_e[63:0] = edp_rcc_data_e[63:0];
assign p1_e[ 7:0] = edp_rcc_ecc_e[7:0];

assign d2_e[63:0] = exu_rs2_data_e[63:0];
assign p2_e[ 7:0] = edp_rs2_ecc_e[7:0];

assign d3_e[63:0] = edp_rs3_data_e[63:0];
assign p3_e[ 7:0] = edp_rs3_ecc_e[7:0];


// Detection for RS1
// -----------------------------------
assign rs1_ne_e = ~ect_rs1_valid_e |
		  ~(rs1_parity_e | q1_e[6] | q1_e[5] | q1_e[4] | q1_e[3] | q1_e[2] | q1_e[1] | q1_e[0]);

assign rs1_ce_e =  ect_rs1_valid_e & rs1_parity_e;

assign rs1_ue_e =  ect_rs1_valid_e & ~rs1_parity_e & 
		   (q1_e[6] | q1_e[5] | q1_e[4] | q1_e[3] | q1_e[2] | q1_e[1] | q1_e[0]);

assign q1_e[0] = d1_e[0]  ^ d1_e[1]  ^ d1_e[3]  ^ d1_e[4]  ^ d1_e[6]  
                          ^ d1_e[8]  ^ d1_e[10] ^ d1_e[11] ^ d1_e[13] ^ d1_e[15]  
                          ^ d1_e[17] ^ d1_e[19] ^ d1_e[21] ^ d1_e[23] ^ d1_e[25]  
                          ^ d1_e[26] ^ d1_e[28] ^ d1_e[30] ^ d1_e[32] ^ d1_e[34] 
                          ^ d1_e[36] ^ d1_e[38] ^ d1_e[40] ^ d1_e[42] ^ d1_e[44]  
                          ^ d1_e[46] ^ d1_e[48] ^ d1_e[50] ^ d1_e[52] ^ d1_e[54]  
                          ^ d1_e[56] ^ d1_e[57] ^ d1_e[59] ^ d1_e[61] ^ d1_e[63]
		          ^ p1_e[0] ; 

assign q1_e[1] = d1_e[0]  ^ d1_e[2]  ^ d1_e[3]  ^ d1_e[5]  ^ d1_e[6]  
                          ^ d1_e[9]  ^ d1_e[10] ^ d1_e[12] ^ d1_e[13] ^ d1_e[16]  
                          ^ d1_e[17] ^ d1_e[20] ^ d1_e[21] ^ d1_e[24] ^ d1_e[25] 
                          ^ d1_e[27] ^ d1_e[28] ^ d1_e[31] ^ d1_e[32] ^ d1_e[35]
                          ^ d1_e[36] ^ d1_e[39] ^ d1_e[40] ^ d1_e[43] ^ d1_e[44]
                          ^ d1_e[47] ^ d1_e[48] ^ d1_e[51] ^ d1_e[52] ^ d1_e[55] 
                          ^ d1_e[56] ^ d1_e[58] ^ d1_e[59] ^ d1_e[62] ^ d1_e[63]
		          ^ p1_e[1] ; 

assign q1_e[2] = d1_e[1]  ^ d1_e[2]  ^ d1_e[3]  ^ d1_e[7]  ^ d1_e[8]  
                          ^ d1_e[9]  ^ d1_e[10] ^ d1_e[14] ^ d1_e[15] ^ d1_e[16]  
                          ^ d1_e[17] ^ d1_e[22] ^ d1_e[23] ^ d1_e[24] ^ d1_e[25]
                          ^ d1_e[29] ^ d1_e[30] ^ d1_e[31] ^ d1_e[32] ^ d1_e[37]  
                          ^ d1_e[38] ^ d1_e[39] ^ d1_e[40] ^ d1_e[45] ^ d1_e[46]
                          ^ d1_e[47] ^ d1_e[48] ^ d1_e[53] ^ d1_e[54] ^ d1_e[55] 
                          ^ d1_e[56] ^ d1_e[60] ^ d1_e[61] ^ d1_e[62] ^ d1_e[63]
		          ^ p1_e[2] ; 

assign q1_e[3] = d1_e[4]  ^ d1_e[5]  ^ d1_e[6]  ^ d1_e[7]  ^ d1_e[8]  
                          ^ d1_e[9]  ^ d1_e[10] ^ d1_e[18] ^ d1_e[19] ^ d1_e[20]  
                          ^ d1_e[21] ^ d1_e[22] ^ d1_e[23] ^ d1_e[24] ^ d1_e[25]
                          ^ d1_e[33] ^ d1_e[34] ^ d1_e[35] ^ d1_e[36] ^ d1_e[37]
                          ^ d1_e[38] ^ d1_e[39] ^ d1_e[40] ^ d1_e[49] ^ d1_e[50]
                          ^ d1_e[51] ^ d1_e[52] ^ d1_e[53] ^ d1_e[54] ^ d1_e[55]
                          ^ d1_e[56]
                          ^ p1_e[3] ; 

assign q1_e[4] = d1_e[11] ^ d1_e[12] ^ d1_e[13] ^ d1_e[14] ^ d1_e[15]
                          ^ d1_e[16] ^ d1_e[17] ^ d1_e[18] ^ d1_e[19] ^ d1_e[20]
                          ^ d1_e[21] ^ d1_e[22] ^ d1_e[23] ^ d1_e[24] ^ d1_e[25]
                          ^ d1_e[41] ^ d1_e[42] ^ d1_e[43] ^ d1_e[44] ^ d1_e[45]
                          ^ d1_e[46] ^ d1_e[47] ^ d1_e[48] ^ d1_e[49] ^ d1_e[50]
                          ^ d1_e[51] ^ d1_e[52] ^ d1_e[53] ^ d1_e[54] ^ d1_e[55]
                          ^ d1_e[56]
                          ^ p1_e[4] ; 

assign q1_e[5] = d1_e[26] ^ d1_e[27] ^ d1_e[28] ^ d1_e[29] ^ d1_e[30] 
                          ^ d1_e[31] ^ d1_e[32] ^ d1_e[33] ^ d1_e[34] ^ d1_e[35]
                          ^ d1_e[36] ^ d1_e[37] ^ d1_e[38] ^ d1_e[39] ^ d1_e[40]
                          ^ d1_e[41] ^ d1_e[42] ^ d1_e[43] ^ d1_e[44] ^ d1_e[45]
                          ^ d1_e[46] ^ d1_e[47] ^ d1_e[48] ^ d1_e[49] ^ d1_e[50]
                          ^ d1_e[51] ^ d1_e[52] ^ d1_e[53] ^ d1_e[54] ^ d1_e[55]
                          ^ d1_e[56]  
                          ^ p1_e[5] ; 

assign q1_e[6] = d1_e[57] ^ d1_e[58] ^ d1_e[59] ^ d1_e[60] ^ d1_e[61] 
                          ^ d1_e[62] ^ d1_e[63]
                          ^ p1_e[6] ; 

assign rs1_parity_e = d1_e[0]  ^ d1_e[1]  ^ d1_e[2]  ^ d1_e[3]  ^ d1_e[4]
                          ^ d1_e[5]  ^ d1_e[6]  ^ d1_e[7]  ^ d1_e[8]  ^ d1_e[9]
                          ^ d1_e[10] ^ d1_e[11] ^ d1_e[12] ^ d1_e[13] ^ d1_e[14] 
                          ^ d1_e[15] ^ d1_e[16] ^ d1_e[17] ^ d1_e[18] ^ d1_e[19]
                          ^ d1_e[20] ^ d1_e[21] ^ d1_e[22] ^ d1_e[23] ^ d1_e[24]
                          ^ d1_e[25] ^ d1_e[26] ^ d1_e[27] ^ d1_e[28] ^ d1_e[29]
                          ^ d1_e[30] ^ d1_e[31] ^ d1_e[32] ^ d1_e[33] ^ d1_e[34]
                          ^ d1_e[35] ^ d1_e[36] ^ d1_e[37] ^ d1_e[38] ^ d1_e[39]
                          ^ d1_e[40] ^ d1_e[41] ^ d1_e[42] ^ d1_e[43] ^ d1_e[44]
                          ^ d1_e[45] ^ d1_e[46] ^ d1_e[47] ^ d1_e[48] ^ d1_e[49]
                          ^ d1_e[50] ^ d1_e[51] ^ d1_e[52] ^ d1_e[53] ^ d1_e[54]
                          ^ d1_e[55] ^ d1_e[56] ^ d1_e[57] ^ d1_e[58] ^ d1_e[59]
                          ^ d1_e[60] ^ d1_e[61] ^ d1_e[62] ^ d1_e[63]
                          ^ p1_e[0]  ^ p1_e[1]  ^ p1_e[2]  ^ p1_e[3]  ^ p1_e[4] 
                          ^ p1_e[5]  ^ p1_e[6]  ^ p1_e[7];


// Detection for RS2
// -----------------------------------
assign rs2_ne_e = ~ect_rs2_valid_e |
		  ~(rs2_parity_e | q2_e[6] | q2_e[5] | q2_e[4] | q2_e[3] | q2_e[2] | q2_e[1] | q2_e[0]);

assign rs2_ce_e =  ect_rs2_valid_e & rs2_parity_e;

assign rs2_ue_e =  ect_rs2_valid_e & ~rs2_parity_e & 
		   (q2_e[6] | q2_e[5] | q2_e[4] | q2_e[3] | q2_e[2] | q2_e[1] | q2_e[0]);

assign q2_e[0] = d2_e[0]  ^ d2_e[1]  ^ d2_e[3]  ^ d2_e[4]  ^ d2_e[6]  
                          ^ d2_e[8]  ^ d2_e[10] ^ d2_e[11] ^ d2_e[13] ^ d2_e[15]  
                          ^ d2_e[17] ^ d2_e[19] ^ d2_e[21] ^ d2_e[23] ^ d2_e[25]  
                          ^ d2_e[26] ^ d2_e[28] ^ d2_e[30] ^ d2_e[32] ^ d2_e[34] 
                          ^ d2_e[36] ^ d2_e[38] ^ d2_e[40] ^ d2_e[42] ^ d2_e[44]  
                          ^ d2_e[46] ^ d2_e[48] ^ d2_e[50] ^ d2_e[52] ^ d2_e[54]  
                          ^ d2_e[56] ^ d2_e[57] ^ d2_e[59] ^ d2_e[61] ^ d2_e[63]
		          ^ p2_e[0] ; 

assign q2_e[1] = d2_e[0]  ^ d2_e[2]  ^ d2_e[3]  ^ d2_e[5]  ^ d2_e[6]  
                          ^ d2_e[9]  ^ d2_e[10] ^ d2_e[12] ^ d2_e[13] ^ d2_e[16]  
                          ^ d2_e[17] ^ d2_e[20] ^ d2_e[21] ^ d2_e[24] ^ d2_e[25] 
                          ^ d2_e[27] ^ d2_e[28] ^ d2_e[31] ^ d2_e[32] ^ d2_e[35]
                          ^ d2_e[36] ^ d2_e[39] ^ d2_e[40] ^ d2_e[43] ^ d2_e[44]
                          ^ d2_e[47] ^ d2_e[48] ^ d2_e[51] ^ d2_e[52] ^ d2_e[55] 
                          ^ d2_e[56] ^ d2_e[58] ^ d2_e[59] ^ d2_e[62] ^ d2_e[63]
		          ^ p2_e[1] ; 

assign q2_e[2] = d2_e[1]  ^ d2_e[2]  ^ d2_e[3]  ^ d2_e[7]  ^ d2_e[8]  
                          ^ d2_e[9]  ^ d2_e[10] ^ d2_e[14] ^ d2_e[15] ^ d2_e[16]  
                          ^ d2_e[17] ^ d2_e[22] ^ d2_e[23] ^ d2_e[24] ^ d2_e[25]
                          ^ d2_e[29] ^ d2_e[30] ^ d2_e[31] ^ d2_e[32] ^ d2_e[37]  
                          ^ d2_e[38] ^ d2_e[39] ^ d2_e[40] ^ d2_e[45] ^ d2_e[46]
                          ^ d2_e[47] ^ d2_e[48] ^ d2_e[53] ^ d2_e[54] ^ d2_e[55] 
                          ^ d2_e[56] ^ d2_e[60] ^ d2_e[61] ^ d2_e[62] ^ d2_e[63]
		          ^ p2_e[2] ; 

assign q2_e[3] = d2_e[4]  ^ d2_e[5]  ^ d2_e[6]  ^ d2_e[7]  ^ d2_e[8]  
                          ^ d2_e[9]  ^ d2_e[10] ^ d2_e[18] ^ d2_e[19] ^ d2_e[20]  
                          ^ d2_e[21] ^ d2_e[22] ^ d2_e[23] ^ d2_e[24] ^ d2_e[25]
                          ^ d2_e[33] ^ d2_e[34] ^ d2_e[35] ^ d2_e[36] ^ d2_e[37]
                          ^ d2_e[38] ^ d2_e[39] ^ d2_e[40] ^ d2_e[49] ^ d2_e[50]
                          ^ d2_e[51] ^ d2_e[52] ^ d2_e[53] ^ d2_e[54] ^ d2_e[55]
                          ^ d2_e[56]
                          ^ p2_e[3] ; 

assign q2_e[4] = d2_e[11] ^ d2_e[12] ^ d2_e[13] ^ d2_e[14] ^ d2_e[15]
                          ^ d2_e[16] ^ d2_e[17] ^ d2_e[18] ^ d2_e[19] ^ d2_e[20]
                          ^ d2_e[21] ^ d2_e[22] ^ d2_e[23] ^ d2_e[24] ^ d2_e[25]
                          ^ d2_e[41] ^ d2_e[42] ^ d2_e[43] ^ d2_e[44] ^ d2_e[45]
                          ^ d2_e[46] ^ d2_e[47] ^ d2_e[48] ^ d2_e[49] ^ d2_e[50]
                          ^ d2_e[51] ^ d2_e[52] ^ d2_e[53] ^ d2_e[54] ^ d2_e[55]
                          ^ d2_e[56]
                          ^ p2_e[4] ; 

assign q2_e[5] = d2_e[26] ^ d2_e[27] ^ d2_e[28] ^ d2_e[29] ^ d2_e[30] 
                          ^ d2_e[31] ^ d2_e[32] ^ d2_e[33] ^ d2_e[34] ^ d2_e[35]
                          ^ d2_e[36] ^ d2_e[37] ^ d2_e[38] ^ d2_e[39] ^ d2_e[40]
                          ^ d2_e[41] ^ d2_e[42] ^ d2_e[43] ^ d2_e[44] ^ d2_e[45]
                          ^ d2_e[46] ^ d2_e[47] ^ d2_e[48] ^ d2_e[49] ^ d2_e[50]
                          ^ d2_e[51] ^ d2_e[52] ^ d2_e[53] ^ d2_e[54] ^ d2_e[55]
                          ^ d2_e[56]  
                          ^ p2_e[5] ; 

assign q2_e[6] = d2_e[57] ^ d2_e[58] ^ d2_e[59] ^ d2_e[60] ^ d2_e[61] 
                          ^ d2_e[62] ^ d2_e[63]
                          ^ p2_e[6] ; 

assign rs2_parity_e = d2_e[0]  ^ d2_e[1]  ^ d2_e[2]  ^ d2_e[3]  ^ d2_e[4]
                          ^ d2_e[5]  ^ d2_e[6]  ^ d2_e[7]  ^ d2_e[8]  ^ d2_e[9]
                          ^ d2_e[10] ^ d2_e[11] ^ d2_e[12] ^ d2_e[13] ^ d2_e[14] 
                          ^ d2_e[15] ^ d2_e[16] ^ d2_e[17] ^ d2_e[18] ^ d2_e[19]
                          ^ d2_e[20] ^ d2_e[21] ^ d2_e[22] ^ d2_e[23] ^ d2_e[24]
                          ^ d2_e[25] ^ d2_e[26] ^ d2_e[27] ^ d2_e[28] ^ d2_e[29]
                          ^ d2_e[30] ^ d2_e[31] ^ d2_e[32] ^ d2_e[33] ^ d2_e[34]
                          ^ d2_e[35] ^ d2_e[36] ^ d2_e[37] ^ d2_e[38] ^ d2_e[39]
                          ^ d2_e[40] ^ d2_e[41] ^ d2_e[42] ^ d2_e[43] ^ d2_e[44]
                          ^ d2_e[45] ^ d2_e[46] ^ d2_e[47] ^ d2_e[48] ^ d2_e[49]
                          ^ d2_e[50] ^ d2_e[51] ^ d2_e[52] ^ d2_e[53] ^ d2_e[54]
                          ^ d2_e[55] ^ d2_e[56] ^ d2_e[57] ^ d2_e[58] ^ d2_e[59]
                          ^ d2_e[60] ^ d2_e[61] ^ d2_e[62] ^ d2_e[63]
                          ^ p2_e[0]  ^ p2_e[1]  ^ p2_e[2]  ^ p2_e[3]  ^ p2_e[4] 
                          ^ p2_e[5]  ^ p2_e[6]  ^ p2_e[7];


// Detection for RS3
// -----------------------------------
//sign rs3_ne_e = ~ect_rs3_valid_e |
//		  ~(rs3_parity_e | q3_e[6] | q3_e[5] | q3_e[4] | q3_e[3] | q3_e[2] | q3_e[1] | q3_e[0]);

assign rs3_ce_e =  ect_rs3_valid_e & rs3_parity_e;

assign rs3_ue_e =  ect_rs3_valid_e & ~rs3_parity_e & 
		   (q3_e[6] | q3_e[5] | q3_e[4] | q3_e[3] | q3_e[2] | q3_e[1] | q3_e[0]);

assign q3_e[0] = d3_e[0]  ^ d3_e[1]  ^ d3_e[3]  ^ d3_e[4]  ^ d3_e[6]  
                          ^ d3_e[8]  ^ d3_e[10] ^ d3_e[11] ^ d3_e[13] ^ d3_e[15]  
                          ^ d3_e[17] ^ d3_e[19] ^ d3_e[21] ^ d3_e[23] ^ d3_e[25]  
                          ^ d3_e[26] ^ d3_e[28] ^ d3_e[30] ^ d3_e[32] ^ d3_e[34] 
                          ^ d3_e[36] ^ d3_e[38] ^ d3_e[40] ^ d3_e[42] ^ d3_e[44]  
                          ^ d3_e[46] ^ d3_e[48] ^ d3_e[50] ^ d3_e[52] ^ d3_e[54]  
                          ^ d3_e[56] ^ d3_e[57] ^ d3_e[59] ^ d3_e[61] ^ d3_e[63]
		          ^ p3_e[0] ; 

assign q3_e[1] = d3_e[0]  ^ d3_e[2]  ^ d3_e[3]  ^ d3_e[5]  ^ d3_e[6]  
                          ^ d3_e[9]  ^ d3_e[10] ^ d3_e[12] ^ d3_e[13] ^ d3_e[16]  
                          ^ d3_e[17] ^ d3_e[20] ^ d3_e[21] ^ d3_e[24] ^ d3_e[25] 
                          ^ d3_e[27] ^ d3_e[28] ^ d3_e[31] ^ d3_e[32] ^ d3_e[35]
                          ^ d3_e[36] ^ d3_e[39] ^ d3_e[40] ^ d3_e[43] ^ d3_e[44]
                          ^ d3_e[47] ^ d3_e[48] ^ d3_e[51] ^ d3_e[52] ^ d3_e[55] 
                          ^ d3_e[56] ^ d3_e[58] ^ d3_e[59] ^ d3_e[62] ^ d3_e[63]
		          ^ p3_e[1] ; 

assign q3_e[2] = d3_e[1]  ^ d3_e[2]  ^ d3_e[3]  ^ d3_e[7]  ^ d3_e[8]  
                          ^ d3_e[9]  ^ d3_e[10] ^ d3_e[14] ^ d3_e[15] ^ d3_e[16]  
                          ^ d3_e[17] ^ d3_e[22] ^ d3_e[23] ^ d3_e[24] ^ d3_e[25]
                          ^ d3_e[29] ^ d3_e[30] ^ d3_e[31] ^ d3_e[32] ^ d3_e[37]  
                          ^ d3_e[38] ^ d3_e[39] ^ d3_e[40] ^ d3_e[45] ^ d3_e[46]
                          ^ d3_e[47] ^ d3_e[48] ^ d3_e[53] ^ d3_e[54] ^ d3_e[55] 
                          ^ d3_e[56] ^ d3_e[60] ^ d3_e[61] ^ d3_e[62] ^ d3_e[63]
		          ^ p3_e[2] ; 

assign q3_e[3] = d3_e[4]  ^ d3_e[5]  ^ d3_e[6]  ^ d3_e[7]  ^ d3_e[8]  
                          ^ d3_e[9]  ^ d3_e[10] ^ d3_e[18] ^ d3_e[19] ^ d3_e[20]  
                          ^ d3_e[21] ^ d3_e[22] ^ d3_e[23] ^ d3_e[24] ^ d3_e[25]
                          ^ d3_e[33] ^ d3_e[34] ^ d3_e[35] ^ d3_e[36] ^ d3_e[37]
                          ^ d3_e[38] ^ d3_e[39] ^ d3_e[40] ^ d3_e[49] ^ d3_e[50]
                          ^ d3_e[51] ^ d3_e[52] ^ d3_e[53] ^ d3_e[54] ^ d3_e[55]
                          ^ d3_e[56]
                          ^ p3_e[3] ; 

assign q3_e[4] = d3_e[11] ^ d3_e[12] ^ d3_e[13] ^ d3_e[14] ^ d3_e[15]
                          ^ d3_e[16] ^ d3_e[17] ^ d3_e[18] ^ d3_e[19] ^ d3_e[20]
                          ^ d3_e[21] ^ d3_e[22] ^ d3_e[23] ^ d3_e[24] ^ d3_e[25]
                          ^ d3_e[41] ^ d3_e[42] ^ d3_e[43] ^ d3_e[44] ^ d3_e[45]
                          ^ d3_e[46] ^ d3_e[47] ^ d3_e[48] ^ d3_e[49] ^ d3_e[50]
                          ^ d3_e[51] ^ d3_e[52] ^ d3_e[53] ^ d3_e[54] ^ d3_e[55]
                          ^ d3_e[56]
                          ^ p3_e[4] ; 

assign q3_e[5] = d3_e[26] ^ d3_e[27] ^ d3_e[28] ^ d3_e[29] ^ d3_e[30] 
                          ^ d3_e[31] ^ d3_e[32] ^ d3_e[33] ^ d3_e[34] ^ d3_e[35]
                          ^ d3_e[36] ^ d3_e[37] ^ d3_e[38] ^ d3_e[39] ^ d3_e[40]
                          ^ d3_e[41] ^ d3_e[42] ^ d3_e[43] ^ d3_e[44] ^ d3_e[45]
                          ^ d3_e[46] ^ d3_e[47] ^ d3_e[48] ^ d3_e[49] ^ d3_e[50]
                          ^ d3_e[51] ^ d3_e[52] ^ d3_e[53] ^ d3_e[54] ^ d3_e[55]
                          ^ d3_e[56]  
                          ^ p3_e[5] ; 

assign q3_e[6] = d3_e[57] ^ d3_e[58] ^ d3_e[59] ^ d3_e[60] ^ d3_e[61] 
                          ^ d3_e[62] ^ d3_e[63]
                          ^ p3_e[6] ; 

assign rs3_parity_e = d3_e[0]  ^ d3_e[1]  ^ d3_e[2]  ^ d3_e[3]  ^ d3_e[4]
                          ^ d3_e[5]  ^ d3_e[6]  ^ d3_e[7]  ^ d3_e[8]  ^ d3_e[9]
                          ^ d3_e[10] ^ d3_e[11] ^ d3_e[12] ^ d3_e[13] ^ d3_e[14] 
                          ^ d3_e[15] ^ d3_e[16] ^ d3_e[17] ^ d3_e[18] ^ d3_e[19]
                          ^ d3_e[20] ^ d3_e[21] ^ d3_e[22] ^ d3_e[23] ^ d3_e[24]
                          ^ d3_e[25] ^ d3_e[26] ^ d3_e[27] ^ d3_e[28] ^ d3_e[29]
                          ^ d3_e[30] ^ d3_e[31] ^ d3_e[32] ^ d3_e[33] ^ d3_e[34]
                          ^ d3_e[35] ^ d3_e[36] ^ d3_e[37] ^ d3_e[38] ^ d3_e[39]
                          ^ d3_e[40] ^ d3_e[41] ^ d3_e[42] ^ d3_e[43] ^ d3_e[44]
                          ^ d3_e[45] ^ d3_e[46] ^ d3_e[47] ^ d3_e[48] ^ d3_e[49]
                          ^ d3_e[50] ^ d3_e[51] ^ d3_e[52] ^ d3_e[53] ^ d3_e[54]
                          ^ d3_e[55] ^ d3_e[56] ^ d3_e[57] ^ d3_e[58] ^ d3_e[59]
                          ^ d3_e[60] ^ d3_e[61] ^ d3_e[62] ^ d3_e[63]
                          ^ p3_e[0]  ^ p3_e[1]  ^ p3_e[2]  ^ p3_e[3]  ^ p3_e[4] 
                          ^ p3_e[5]  ^ p3_e[6]  ^ p3_e[7];


/////////////////////////////////////////////////////////////////////////////
// Operand selection for correction
//-----------------------------------
// - Only one operand can be corrected at a time
// - Selection based on hard coded priorty
//   - rs1 -> rs2 -> rs3
// - If no error, sel defaults to rs3
//
// NOTE: Doing operand selection in E stage adds timing pressure to E stage,
//       but saves about 150 flops.
//
//       If this does not make cycle time, need to pass sel signal to M stage,
//       must protect sel with rst_tri_en to ensure one-hot property.
//       
// - critical path1 is from (d1_e -> q1_e -> rs1_ne_e -> rs_to_correct)
//   
//   (d1_e->q1_e): xor3(fo1) -> xor3(fo1) -> xor2(fo1) -> xor2(fo4)  => 245ps
//   (q1_e -> rs1_ne_e): 
//                 nand3(fo1) -> nand3(fo4) -> inv(fo4) -> nand2(fo4)=> 120ps
//   (rs1_ne_e -> rs_to_correct):  
//                 buffer(fo4)(4 levels) -> nand3(fo1) -> nand3(fo4) => 165ps
//                                                                  ---------  
//                                                                      530ps
//
// - critical path2 is (d1_e -> rs1_parity_e -> rs1_ne_e -> rs_to_correct)
//   
//   (d1_e -> rs1_parity_e): 
//                 xor3(fo1) -> xor3(fo1) -> xor3(fo1) -> xor3(fo4)  => 275ps
//   (rs1_parity_e -> rs1_ne_e): inv(fo4) -> nand3(fo4)              =>  55ps
//   (rs1_ne_e -> rs_to_correct)
//                 buffer(fo4)(4 levels) -> nand3(fo1) -> nand3(fo4) => 165ps
//                                                                  ---------  
//                                                                      495ps
//
/////////////////////////////////////////////////////////////////////////////


assign check_e[7:0]	= ({8{~rs1_ne_e            }} & {rs1_parity_e,q1_e[6:0]}) |
			  ({8{ rs1_ne_e & ~rs2_ne_e}} & {rs2_parity_e,q2_e[6:0]}) |
			  ({8{ rs1_ne_e &  rs2_ne_e}} & {rs3_parity_e,q3_e[6:0]});

assign addr_e[4:0]	= ({5{~rs1_ne_e            }} & ect_rs1_addr_e[4:0]) |
			  ({5{ rs1_ne_e & ~rs2_ne_e}} & ect_rs2_addr_e[4:0]) |
			  ({5{ rs1_ne_e &  rs2_ne_e}} & ect_rs3_addr_e[4:0]);


exu_ecc_ctl_msff_ctl_macro__width_8 check_e_to_m	 (
 .scan_in(check_e_to_m_scanin),
 .scan_out(check_e_to_m_scanout),
 .l1clk( l1clk_pm2		),
 .din  ( check_e[7:0]		),
 .dout ( exu_ecc_check_m[7:0]	),
  .siclk(siclk),
  .soclk(soclk));


exu_ecc_ctl_msff_ctl_macro__width_5 addr_e_to_m	 (
 .scan_in(addr_e_to_m_scanin),
 .scan_out(addr_e_to_m_scanout),
 .l1clk( l1clk_pm2		),
 .din  ( addr_e[4:0]		),
 .dout ( exu_ecc_addr_m[4:0]	),
  .siclk(siclk),
  .soclk(soclk));


// control signals for other blocks
// -------------------------------------------
assign cecc_e  = rs1_ce_e | (rs1_ne_e & rs2_ce_e) | (rs1_ne_e & rs2_ne_e & rs3_ce_e);
assign uecc_e  = rs1_ue_e | (rs1_ne_e & rs2_ue_e) | (rs1_ne_e & rs2_ne_e & rs3_ue_e);

assign ecc_ecc_e	=  ecc_enable_e & (uecc_e | cecc_e);
assign ecc_uecc_e	=  ecc_enable_e &  uecc_e;
assign ecc_cecc_e   	=  ecc_enable_e &  cecc_e;

exu_ecc_ctl_msff_ctl_macro__width_3  ce_ue_ecc_flops  (
 .scan_in(ce_ue_ecc_flops_scanin),
 .scan_out(ce_ue_ecc_flops_scanout),
 .l1clk( l1clk_pm2						),
 .din  ({ecc_ecc_e, ecc_cecc_e, ecc_uecc_e}	),
 .dout ({exu_ecc_m, exu_cecc_m, exu_uecc_m}	),
  .siclk(siclk),
  .soclk(soclk));

/////////////////////////////////////////////////////////////////////////////
//***************************************************************************
//***** ECC Generation ******************************************************
//***************************************************************************
/////////////////////////////////////////////////////////////////////////////
// ECC Generation
//-----------------------------------
// - Encode the 64-bit write data into an 8-bit Error Correction Code 
// - Encode is first done in two stages:
//   - IRF write happens in phase 2 of write stage
//   - ECC will take longer than phase 1 of write stage
//   - ECC logic will spill over to phase 2 of the stage before write.
//   - WARNING: this may change as we explore ways to speed up ECC generation
//  
//   din= d0  d1  d2  d3  d4  d5  d6  d7  d8  d9 d10 d11 d12 d13 d14 d15 
//   p0 =  x   x       x   x       x       x       x   x       x       x
//   p1 =  x       x   x       x   x           x   x       x   x
//   p2 =      x   x   x               x   x   x   x               x   x
//   p3 =                  x   x   x   x   x   x   x                       
//   p4 =                                              x   x   x   x   x
//   p5 =
//   p6 =
//   p7 =  x   x   x       x   x       x           x   x   x       x
//   -------------------------------------------------------------------
//   Total 3   3   3   3   3   3   3   3   3   3   5   3   3   3   3   3 
//   
//   din=d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 
//   p0 =      x       x       x       x       x   x       x       x    
//   p1 =  x   x           x   x           x   x       x   x           x
//   p2 =  x   x                   x   x   x   x               x   x   x
//   p3 =          x   x   x   x   x   x   x   x
//   p4 =  x   x   x   x   x   x   x   x   x   x
//   p5 =                                          x   x   x   x   x   x
//   p6 =                                          
//   p7 =      x   x           x       x   x       x   x       x    
//   -------------------------------------------------------------------
//   total 3   5   3   3   3   5   3   5   5   5   3   3   3   3   3   3
// 
//   din=d32 d33 d34 d35 d36 d37 d38 d39 d40 d41 d42 d43 d44 d45 d46 d47 
//   p0 =  x       x       x       x       x       x       x       x    
//   p1 =  x           x   x           x   x           x   x           x
//   p2 =  x                   x   x   x   x                   x   x   x
//   p3 =      x   x   x   x   x   x   x   x
//   p4 =                                      x   x   x   x   x   x   x
//   p5 =  x   x   x   x   x   x   x   x   x   x   x   x   x   x   x   x
//   p6 =                                         
//   p7 =  x   x           x       x   x       x           x       x   x
//   -------------------------------------------------------------------
//   total 5   3   3   3   5   3   5   5   5   3   3   3   5   3   5   5
// 
//   din=d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 
//   p0 =  x       x       x       x       x   x       x       x       x
//   p1 =  x           x   x           x   x       x   x           x   x
//   p2 =  x                   x   x   x   x               x   x   x   x
//   p3 =      x   x   x   x   x   x   x   x
//   p4 =  x   x   x   x   x   x   x   x   x   
//   p5 =  x   x   x   x   x   x   x   x   x  
//   p6 =                                      x   x   x   x   x   x   x
//   p7 =          x   x       x           x   x   x       x           x
//   -------------------------------------------------------------------
//   total 5   3   5   5   5   5   5   5   7   3   3   3   3   3   3   5
// 
/////////////////////////////////////////////////////////////////////////////

// Error injection logic for ECC logic testing
// - inject error if it is enabled 
// - the 8-bit ecc_mask is only xored with W port, not W2 port
// - xor takes place as part of the W port ECC generation.

assign ecc_mask_b[7:0] = {8{ecc_mask_en_ff}} & ecc_mask_data_ff[7:0];


//  W port ECC Generation
// -------------------------------------------
// assign shorter name to w port write data to make later code more readable
assign w_d[63:0]         = edp_rd_ff_w[63:0];
assign ecc_w_synd_w[7:0] = ({8{~ect_mbist_sel}} & w_p_b[7:0]) | ({8{ ect_mbist_sel}} & mbi_write_data_p2[7:0]);


  // w_p_b[0]
  assign   w_p_b[0] = ((w_d[0]  ^ w_d[1])  ^ (w_d[3]  ^ w_d[4] )) ^
                      ((w_d[6]  ^ w_d[8])  ^ (w_d[10] ^ w_d[11])) ^ 
                      ((w_d[13] ^ w_d[15]) ^ (w_d[17] ^ w_d[19])) ^
                      ((w_d[21] ^ w_d[23]) ^ (w_d[25] ^ w_d[26])) ^
                      ((w_d[28] ^ w_d[30]) ^ (w_d[32] ^ w_d[34])) ^
                      ((w_d[36] ^ w_d[38]) ^ (w_d[40] ^ w_d[42])) ^
                      ((w_d[44] ^ w_d[46]) ^ (w_d[48] ^ w_d[50])) ^
                      ((w_d[52] ^ w_d[54]) ^ (w_d[56] ^ w_d[57])) ^
                      ((w_d[59] ^ w_d[61]) ^ (w_d[63] ^ ecc_mask_b[0])); 

  // w_p_b[1]
  assign   w_p_b[1] = ((w_d[0]  ^ w_d[2] ) ^ (w_d[3]  ^ w_d[5] )) ^  
                      ((w_d[6]  ^ w_d[9] ) ^ (w_d[10] ^ w_d[12])) ^
                      ((w_d[13] ^ w_d[16]) ^ (w_d[17] ^ w_d[20])) ^
                      ((w_d[21] ^ w_d[24]) ^ (w_d[25] ^ w_d[27])) ^
                      ((w_d[28] ^ w_d[31]) ^ (w_d[32] ^ w_d[35])) ^
                      ((w_d[36] ^ w_d[39]) ^ (w_d[40] ^ w_d[43])) ^
                      ((w_d[44] ^ w_d[47]) ^ (w_d[48] ^ w_d[51])) ^
                      ((w_d[52] ^ w_d[55]) ^ (w_d[56] ^ w_d[58])) ^
                      ((w_d[59] ^ w_d[62]) ^ (w_d[63] ^ ecc_mask_b[1]));

  // w_p_b[2]
  assign   w_p_b[2] = ((w_d[1]  ^ w_d[2] ) ^ (w_d[3]  ^ w_d[7] )) ^
                      ((w_d[8]  ^ w_d[9] ) ^ (w_d[10] ^ w_d[14])) ^
                      ((w_d[15] ^ w_d[16]) ^ (w_d[17] ^ w_d[22])) ^
                      ((w_d[23] ^ w_d[24]) ^ (w_d[25] ^ w_d[29])) ^
                      ((w_d[30] ^ w_d[31]) ^ (w_d[32] ^ w_d[37])) ^
                      ((w_d[38] ^ w_d[39]) ^ (w_d[40] ^ w_d[45])) ^
                      ((w_d[46] ^ w_d[47]) ^ (w_d[48] ^ w_d[53])) ^
                      ((w_d[54] ^ w_d[55]) ^ (w_d[56] ^ w_d[60])) ^
                      ((w_d[61] ^ w_d[62]) ^ (w_d[63] ^ ecc_mask_b[2]));
  
  // w_p_b[3]
  assign   w_p_b[3] = ((w_d[4]  ^ w_d[5] ) ^ (w_d[6]  ^ w_d[7] )) ^ 
                      ((w_d[8]  ^ w_d[9] ) ^ (w_d[10] ^ w_d[18])) ^ 
                      ((w_d[19] ^ w_d[20]) ^ (w_d[21] ^ w_d[22])) ^ 
                      ((w_d[23] ^ w_d[24]) ^ (w_d[25] ^ w_d[33])) ^ 
                      ((w_d[34] ^ w_d[35]) ^ (w_d[36] ^ w_d[37])) ^ 
                      ((w_d[38] ^ w_d[39]) ^ (w_d[40] ^ w_d[49])) ^ 
                      ((w_d[50] ^ w_d[51]) ^ (w_d[52] ^ w_d[53])) ^ 
                      ((w_d[54] ^ w_d[55]) ^ (w_d[56] ^ ecc_mask_b[3]));

  // w_p_b[4]
  assign   w_p_b[4] = ((w_d[11] ^ w_d[12]) ^ (w_d[13] ^ w_d[14])) ^
                      ((w_d[15] ^ w_d[16]) ^ (w_d[17] ^ w_d[18])) ^
                      ((w_d[19] ^ w_d[20]) ^ (w_d[21] ^ w_d[22])) ^
                      ((w_d[23] ^ w_d[24]) ^ (w_d[25] ^ w_d[41])) ^
                      ((w_d[42] ^ w_d[43]) ^ (w_d[44] ^ w_d[45])) ^
                      ((w_d[46] ^ w_d[47]) ^ (w_d[48] ^ w_d[49])) ^
                      ((w_d[50] ^ w_d[51]) ^ (w_d[52] ^ w_d[53])) ^
                      ((w_d[54] ^ w_d[55]) ^ (w_d[56] ^ ecc_mask_b[4])); 

  // w_p_b[5]
  assign   w_p_b[5] = ((w_d[26] ^ w_d[27]) ^ (w_d[28] ^ w_d[29])) ^
                      ((w_d[30] ^ w_d[31]) ^ (w_d[32] ^ w_d[33])) ^
                      ((w_d[34] ^ w_d[35]) ^ (w_d[36] ^ w_d[37])) ^
                      ((w_d[38] ^ w_d[39]) ^ (w_d[40] ^ w_d[41])) ^
                      ((w_d[42] ^ w_d[43]) ^ (w_d[44] ^ w_d[45])) ^
                      ((w_d[46] ^ w_d[47]) ^ (w_d[48] ^ w_d[49])) ^
                      ((w_d[50] ^ w_d[51]) ^ (w_d[52] ^ w_d[53])) ^
                      ((w_d[54] ^ w_d[55]) ^ (w_d[56] ^ ecc_mask_b[5])); 

  // w_p_b[6]
  assign   w_p_b[6] = ((w_d[57] ^ w_d[58]) ^ (w_d[59] ^ w_d[60])) ^
                      ((w_d[61] ^ w_d[62]) ^ (w_d[63] ^ ecc_mask_b[6])); 

  // w_p_b[7]
  assign   w_p_b[7] = ((w_d[0]  ^ w_d[1] ) ^ (w_d[2]  ^ w_d[4] )) ^
                      ((w_d[5]  ^ w_d[7] ) ^ (w_d[10] ^ w_d[11])) ^
                      ((w_d[12] ^ w_d[14]) ^ (w_d[17] ^ w_d[18])) ^
                      ((w_d[21] ^ w_d[23]) ^ (w_d[24] ^ w_d[26])) ^
                      ((w_d[27] ^ w_d[29]) ^ (w_d[32] ^ w_d[33])) ^
                      ((w_d[36] ^ w_d[38]) ^ (w_d[39] ^ w_d[41])) ^
                      ((w_d[44] ^ w_d[46]) ^ (w_d[47] ^ w_d[50])) ^
                      ((w_d[51] ^ w_d[53]) ^ (w_d[56] ^ w_d[57])) ^
                      ((w_d[58] ^ w_d[60]) ^ (w_d[63] ^ ecc_mask_b[7]));
       

//  W2 port ECC Generation
// -------------------------------------------
// assign shorter name to w port write data to make later code more readable
assign w2_d[63:0]         = edp_rd_ff_w2[63:0];
assign ecc_w2_synd_w2[7:0] = w2_p_w[7:0];


  // w2_p_w[0]
  assign   w2_p_w[0] = ((w2_d[0]  ^ w2_d[1])  ^ (w2_d[3]  ^ w2_d[4] )) ^
                       ((w2_d[6]  ^ w2_d[8])  ^ (w2_d[10] ^ w2_d[11])) ^ 
                       ((w2_d[13] ^ w2_d[15]) ^ (w2_d[17] ^ w2_d[19])) ^
                       ((w2_d[21] ^ w2_d[23]) ^ (w2_d[25] ^ w2_d[26])) ^
                       ((w2_d[28] ^ w2_d[30]) ^ (w2_d[32] ^ w2_d[34])) ^
                       ((w2_d[36] ^ w2_d[38]) ^ (w2_d[40] ^ w2_d[42])) ^
                       ((w2_d[44] ^ w2_d[46]) ^ (w2_d[48] ^ w2_d[50])) ^
                       ((w2_d[52] ^ w2_d[54]) ^ (w2_d[56] ^ w2_d[57])) ^
                       ((w2_d[59] ^ w2_d[61]) ^ (w2_d[63] ^ ecc_mask_b[0])); 

  // w2_p_w[1]
  assign   w2_p_w[1] = ((w2_d[0]  ^ w2_d[2] ) ^ (w2_d[3]  ^ w2_d[5] )) ^  
                       ((w2_d[6]  ^ w2_d[9] ) ^ (w2_d[10] ^ w2_d[12])) ^
                       ((w2_d[13] ^ w2_d[16]) ^ (w2_d[17] ^ w2_d[20])) ^
                       ((w2_d[21] ^ w2_d[24]) ^ (w2_d[25] ^ w2_d[27])) ^
                       ((w2_d[28] ^ w2_d[31]) ^ (w2_d[32] ^ w2_d[35])) ^
                       ((w2_d[36] ^ w2_d[39]) ^ (w2_d[40] ^ w2_d[43])) ^
                       ((w2_d[44] ^ w2_d[47]) ^ (w2_d[48] ^ w2_d[51])) ^
                       ((w2_d[52] ^ w2_d[55]) ^ (w2_d[56] ^ w2_d[58])) ^
                       ((w2_d[59] ^ w2_d[62]) ^ (w2_d[63] ^ ecc_mask_b[1]));

  // w2_p_w[2]
  assign   w2_p_w[2] = ((w2_d[1]  ^ w2_d[2] ) ^ (w2_d[3]  ^ w2_d[7] )) ^
                       ((w2_d[8]  ^ w2_d[9] ) ^ (w2_d[10] ^ w2_d[14])) ^
                       ((w2_d[15] ^ w2_d[16]) ^ (w2_d[17] ^ w2_d[22])) ^
                       ((w2_d[23] ^ w2_d[24]) ^ (w2_d[25] ^ w2_d[29])) ^
                       ((w2_d[30] ^ w2_d[31]) ^ (w2_d[32] ^ w2_d[37])) ^
                       ((w2_d[38] ^ w2_d[39]) ^ (w2_d[40] ^ w2_d[45])) ^
                       ((w2_d[46] ^ w2_d[47]) ^ (w2_d[48] ^ w2_d[53])) ^
                       ((w2_d[54] ^ w2_d[55]) ^ (w2_d[56] ^ w2_d[60])) ^
                       ((w2_d[61] ^ w2_d[62]) ^ (w2_d[63] ^ ecc_mask_b[2]));
  
  // w2_p_w[3]
  assign   w2_p_w[3] = ((w2_d[4]  ^ w2_d[5] ) ^ (w2_d[6]  ^ w2_d[7] )) ^ 
                       ((w2_d[8]  ^ w2_d[9] ) ^ (w2_d[10] ^ w2_d[18])) ^ 
                       ((w2_d[19] ^ w2_d[20]) ^ (w2_d[21] ^ w2_d[22])) ^ 
                       ((w2_d[23] ^ w2_d[24]) ^ (w2_d[25] ^ w2_d[33])) ^ 
                       ((w2_d[34] ^ w2_d[35]) ^ (w2_d[36] ^ w2_d[37])) ^ 
                       ((w2_d[38] ^ w2_d[39]) ^ (w2_d[40] ^ w2_d[49])) ^ 
                       ((w2_d[50] ^ w2_d[51]) ^ (w2_d[52] ^ w2_d[53])) ^ 
                       ((w2_d[54] ^ w2_d[55]) ^ (w2_d[56] ^ ecc_mask_b[3]));

  // w2_p_w[4]
  assign   w2_p_w[4] = ((w2_d[11] ^ w2_d[12]) ^ (w2_d[13] ^ w2_d[14])) ^
                       ((w2_d[15] ^ w2_d[16]) ^ (w2_d[17] ^ w2_d[18])) ^
                       ((w2_d[19] ^ w2_d[20]) ^ (w2_d[21] ^ w2_d[22])) ^
                       ((w2_d[23] ^ w2_d[24]) ^ (w2_d[25] ^ w2_d[41])) ^
                       ((w2_d[42] ^ w2_d[43]) ^ (w2_d[44] ^ w2_d[45])) ^
                       ((w2_d[46] ^ w2_d[47]) ^ (w2_d[48] ^ w2_d[49])) ^
                       ((w2_d[50] ^ w2_d[51]) ^ (w2_d[52] ^ w2_d[53])) ^
                       ((w2_d[54] ^ w2_d[55]) ^ (w2_d[56] ^ ecc_mask_b[4])); 

  // w2_p_w[5]
  assign   w2_p_w[5] = ((w2_d[26] ^ w2_d[27]) ^ (w2_d[28] ^ w2_d[29])) ^
                       ((w2_d[30] ^ w2_d[31]) ^ (w2_d[32] ^ w2_d[33])) ^
                       ((w2_d[34] ^ w2_d[35]) ^ (w2_d[36] ^ w2_d[37])) ^
                       ((w2_d[38] ^ w2_d[39]) ^ (w2_d[40] ^ w2_d[41])) ^
                       ((w2_d[42] ^ w2_d[43]) ^ (w2_d[44] ^ w2_d[45])) ^
                       ((w2_d[46] ^ w2_d[47]) ^ (w2_d[48] ^ w2_d[49])) ^
                       ((w2_d[50] ^ w2_d[51]) ^ (w2_d[52] ^ w2_d[53])) ^
                       ((w2_d[54] ^ w2_d[55]) ^ (w2_d[56] ^ ecc_mask_b[5])); 

  // w2_p_w[6]
  assign   w2_p_w[6] = ((w2_d[57] ^ w2_d[58]) ^ (w2_d[59] ^ w2_d[60])) ^
                       ((w2_d[61] ^ w2_d[62]) ^ (w2_d[63] ^ ecc_mask_b[6])); 

  // w2_p_w[7]
  assign   w2_p_w[7] = ((w2_d[0]  ^ w2_d[1] ) ^ (w2_d[2]  ^ w2_d[4] )) ^
                       ((w2_d[5]  ^ w2_d[7] ) ^ (w2_d[10] ^ w2_d[11])) ^
                       ((w2_d[12] ^ w2_d[14]) ^ (w2_d[17] ^ w2_d[18])) ^
                       ((w2_d[21] ^ w2_d[23]) ^ (w2_d[24] ^ w2_d[26])) ^
                       ((w2_d[27] ^ w2_d[29]) ^ (w2_d[32] ^ w2_d[33])) ^
                       ((w2_d[36] ^ w2_d[38]) ^ (w2_d[39] ^ w2_d[41])) ^
                       ((w2_d[44] ^ w2_d[46]) ^ (w2_d[47] ^ w2_d[50])) ^
                       ((w2_d[51] ^ w2_d[53]) ^ (w2_d[56] ^ w2_d[57])) ^
                       ((w2_d[58] ^ w2_d[60]) ^ (w2_d[63] ^ ecc_mask_b[7]));


exu_ecc_ctl_spare_ctl_macro__num_4 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk));

       
supply0 vss;
supply1 vdd;

// fixscan start:
assign mbist_ff_scanin           = scan_in                  ;
assign debug_ff_scanin           = mbist_ff_scanout         ;
assign check_e_to_m_scanin       = debug_ff_scanout         ;
assign addr_e_to_m_scanin        = check_e_to_m_scanout     ;
assign ce_ue_ecc_flops_scanin    = addr_e_to_m_scanout      ;
assign spares_scanin             = ce_ue_ecc_flops_scanout  ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module exu_ecc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ecc_ctl_msff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ecc_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ecc_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ecc_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ecc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module exu_ecc_ctl_spare_ctl_macro__num_4 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));
assign scan_out = so_3;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: exu_ect_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module exu_ect_ctl (
  l2clk, 
  scan_in, 
  wmr_scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  spc_aclk_wmr, 
  tcu_scan_en, 
  dec_tid_p, 
  dec_inst_rs1_vld_p, 
  dec_inst_rs2_vld_p, 
  dec_inst_rs3_vld_p, 
  dec_inst_rs1_p, 
  dec_inst_rs2_p, 
  dec_inst_rs3_p, 
  dec_inst_rd_d, 
  dec_inst_d, 
  dec_decode_d, 
  dec_thread_group, 
  dec_valid_e, 
  tlu_itlb_bypass_e, 
  dec_flush_m, 
  dec_flush_b, 
  fgu_exu_icc_fx5, 
  fgu_exu_xcc_fx5, 
  fgu_exu_cc_vld_fx5, 
  fgu_result_tid_fx5, 
  fgu_irf_w_addr_fx5, 
  fgu_exu_w_vld_fx5, 
  lsu_exu_ld_b, 
  lsu_exu_rd_m, 
  lsu_exu_tid_m, 
  lsu_exu_ld_vld_w, 
  tlu_flush_exu_b, 
  tlu_ccr, 
  tlu_ccr_cwp_valid, 
  tlu_ccr_cwp_tid, 
  tlu_pstate_am, 
  lsu_exu_pmen, 
  spc_core_running_status, 
  mbi_run, 
  mbi_addr, 
  mbi_irf_write_en, 
  edp_rng_in_ff, 
  edp_rng_in_ff_b56, 
  edp_rng_in_ff_b57, 
  rml_rng_wt_ccr_ctl, 
  edp_br_flag_e, 
  exu_rs1_data_e, 
  exu_rs2_data_e, 
  edp_add_cout64_e, 
  edp_add_data_e_b63, 
  edp_add_data_e_b31, 
  edp_add_data_e_b1, 
  edp_add_data_e_b0, 
  edp_add_zdetect_e_, 
  edp_sub_cout64_e, 
  edp_sub_data_e_b63, 
  edp_sub_data_e_b31, 
  edp_sub_zdetect_e_, 
  edp_logical_data_e_b63, 
  edp_logical_data_e_b31, 
  edp_lg_zdetect_e, 
  edp_address_m, 
  edp_rd_ff_m, 
  exu_ecc_m, 
  rml_test_valid_d, 
  fgu_fld_fcc_fx3, 
  lsu_fgu_fld_tid_b, 
  fgu_fld_fcc_vld_fx3, 
  lsu_fgu_fld_vld_w, 
  fgu_cmp_fcc_fx3, 
  fgu_cmp_fcc_tid_fx2, 
  fgu_cmp_fcc_vld_fx3, 
  dec_pick_d, 
  exu_mdp_mux_sel_e, 
  exu_ms_icc_e, 
  exu_gsr_vld_m, 
  exu_cmov_true_m, 
  exu_lsu_va_error_m, 
  exu_misalign_m, 
  exu_oor_va_m, 
  exu_tcc_m, 
  exu_tof_m, 
  exu_ccr0, 
  exu_ccr1, 
  exu_ccr2, 
  exu_ccr3, 
  ect_mbist_sel, 
  ect_rs1_early_sel_d, 
  ect_rs2_early_sel_d, 
  ect_rs3_early_sel_d, 
  ect_rs2_imm_sel_d, 
  ect_rs1_late_sel_d, 
  ect_rs2_late_sel_d, 
  ect_rs3_late_sel_d, 
  ect_logic_sel_d, 
  ect_shift_sel_d, 
  ect_br_taken_z0_e, 
  ect_br_taken_z1_e, 
  ect_alignaddress_little_e, 
  ect_as_clip_e_, 
  ect_as_cin_e, 
  ect_array_sel_e, 
  ect_edge_lmask_e, 
  ect_edge_lrmask_e, 
  ect_pstate_am_e, 
  ect_rm_early_sel_e, 
  ect_rm_late_sel_e, 
  ect_store_mux_sel_e, 
  ect_tid_lth_e, 
  ect_rs1_addr_e, 
  ect_rs2_addr_e, 
  ect_rs3_addr_e, 
  ect_rs1_valid_e, 
  ect_rs2_valid_e, 
  ect_rs3_valid_e, 
  ect_two_cycle_m, 
  ect_rd_lth_w, 
  ect_rd_lth_w2, 
  ect_tid_lth_w, 
  ect_tid_lth_w2, 
  ect_valid_lth_w, 
  ect_valid_in_w2, 
  ect_yreg_wr_w, 
  ect_rng_ccr_data, 
  ect_misaligned_error_m, 
  ect_ex_emb_clken, 
  ect_tg_clken, 
  scan_out, 
  wmr_scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire l1clk_pm1;
wire ex_dw1_clken;
wire l1clk_pm2;
wire tg_active;
wire i_pwr0_lth_scanin;
wire i_pwr0_lth_scanout;
wire [2:0] lsu_exu_tid_b;
wire pmen_lth_;
wire tg_active_lth;
wire mbi_run_lth;
wire [2:2] tid_lth_w2;
wire i_pwr1_lth_scanin;
wire i_pwr1_lth_scanout;
wire pwr_m;
wire pwr_b;
wire pwr_w;
wire pwr_e;
wire pwr_w_p1;
wire i_mbist_lth_scanin;
wire i_mbist_lth_scanout;
wire mbi_irf_write_en_p1;
wire [6:0] mbi_addr_p1;
wire as_cin_d;
wire as_cin_set_d;
wire as_cin_ccr0_d;
wire ccr_byp_data_b0;
wire as_cin_ccr1_d;
wire wrxx_d;
wire wrxx_raw_d;
wire rs1_m_cmp;
wire rs1_b_cmp;
wire rs1_w_cmp;
wire rs1_w2_cmp;
wire rs1_w_plus1_cmp;
wire branch_d;
wire rs1_e_cmp;
wire rs1_l_cmp;
wire rs1_byp_early;
wire rs2_imm_sel7_d;
wire rs2_imm_sel6_d;
wire rs2_imm_sel5_d;
wire rs2_imm_sel4_d;
wire rs2_imm_sel3_d;
wire rs2_imm_sel2_d;
wire rs2_imm_sel1_d;
wire rs2_imm_sel0_d;
wire rs2_m_cmp;
wire rs2_b_cmp;
wire rs2_w_cmp;
wire rs2_w2_cmp;
wire rs2_w_plus1_cmp;
wire rs2_imm_data_d;
wire rs2_e_cmp;
wire rs2_l_cmp;
wire rs2_byp_early;
wire rs3_m_cmp;
wire rs3_b_cmp;
wire rs3_w_cmp;
wire rs3_w2_cmp;
wire rs3_w_plus1_cmp;
wire rs1_late_sel4_d;
wire rs3_e_cmp;
wire rs3_l_cmp;
wire rs3_byp_early;
wire [31:5] i;
wire as_subtract_d;
wire as_cc_d;
wire tas_cc_d;
wire tas_tv_d;
wire logic_sel3_d;
wire logic_sel2_d;
wire logic_sel1_d;
wire logic_sel0_d;
wire lg_cc_d;
wire shift_sel6_d;
wire shift_sel5_d;
wire shift_sel4_d;
wire shift_sel3_d;
wire shift_sel2_d;
wire shift_sel1_d;
wire shift_sel0_d;
wire edgele_d;
wire edge08_d;
wire edge16_d;
wire edge32_d;
wire array08_d;
wire array16_d;
wire call_d;
wire mov_cond_d;
wire bmask_d;
wire alignaddress_d;
wire alignaddress_little_d;
wire mux_mdp_sel0_d;
wire mux_mdp_sel1_d;
wire mux_mdp_sel2_d;
wire mux_mdp_sel3_d;
wire mux_mdp_sel4_d;
wire mux_mdp_sel5_d;
wire tcc_d;
wire address_d;
wire exu_op_d;
wire rm_late_sel0_d;
wire rm_late_sel1_d;
wire rm_late_sel2_d;
wire rm_early_sel0_d;
wire rm_early_sel1_d;
wire rm_early_sel2_d;
wire rm_early_sel4_d;
wire misalign_d;
wire ls_special_sel_d;
wire cmov_d;
wire regop_d;
wire specbr_d;
wire callclass_d;
wire movcc_d;
wire movr_d;
wire br_or_tcc_d;
wire bcc_d;
wire bpcc_d;
wire fmov_d;
wire imov_d;
wire fp_d;
wire two_cycle_d;
wire i_estage_lth_scanin;
wire i_estage_lth_scanout;
wire address_e;
wire branch_e;
wire ls_special_sel_e;
wire two_cycle_e;
wire rm_early_sel34;
wire as_subtract_e;
wire as_cc_e;
wire lg_cc_e;
wire misalign_e;
wire mov_cond_e;
wire tas_cc_e;
wire tas_tv_e;
wire tcc_e;
wire bmask_e;
wire alignaddress_e;
wire edge08_e;
wire edge16_e;
wire edge32_e;
wire edgele_e;
wire [1:0] gsr_vld_e_in;
wire address_e_in;
wire br_special_sel_e;
wire two_cycle_e_in;
wire i_mstage_lth_scanin;
wire i_mstage_lth_scanout;
wire address_m;
wire ls_special_sel_m;
wire br_special_sel_m;
wire fgu_valid_b;
wire lsu_valid_w2;
wire lsu_exu_ld_w;
wire valid_in_d;
wire valid_in_e;
wire valid_out_e;
wire valid_in_m;
wire valid_lth_m;
wire address_error_m;
wire valid_in_b;
wire valid_lth_b;
wire tof_b;
wire misalign_b;
wire [1:0] ect_tid_in_b;
wire [1:0] tid_lth_b;
wire [4:0] rd_in_d;
wire [4:0] inst_rs3_d;
wire [4:0] rd_in_m;
wire [4:0] rd_lth_m;
wire [4:0] ect_rd_in_b;
wire [4:0] rd_lth_b;
wire rs1_valid_d;
wire rs1_rd_en_d;
wire rs2_valid_d;
wire rs2_rd_en_d;
wire rs3_valid_d;
wire rs3_rd_en_d;
wire ren_lth_scanin;
wire ren_lth_scanout;
wire rs_lth_scanin;
wire rs_lth_scanout;
wire [4:0] inst_rs1_d;
wire [4:0] inst_rs2_d;
wire i_byp_lth_scanin;
wire i_byp_lth_scanout;
wire [1:0] tid_lth_d;
wire [4:0] rd_lth_e;
wire movcc_true_e;
wire [1:0] tid_lth_m;
wire [4:0] lsu_exu_rd_b;
wire valid_lth_e;
wire valid_lth_w_plus1;
wire [1:0] tid_lth_w_plus1;
wire [4:0] rd_lth_w_plus1;
wire valid_lth_w2_plus1;
wire [1:0] tid_lth_w2_plus1;
wire [4:0] rd_lth_w2_plus1;
wire dec_cmov_z00_e;
wire dec_cmov_z01_e;
wire dec_cmov_z10_e;
wire tas_tv_overflow_e;
wire misalign_error_e;
wire raw_valid_out_e;
wire rs1_w2_plus1_cmp;
wire rs2_w2_plus1_cmp;
wire rs3_w2_plus1_cmp;
wire [7:0] lg_cc;
wire [7:0] as_cc;
wire [7:0] ccr_data_e;
wire [7:0] ccr_data_b;
wire fgu_ccr_valid_b;
wire [7:0] ccr_data_lth_b;
wire ccr_valid_in_d;
wire ccr_valid_in_e;
wire ccr_valid_out_e;
wire ccr_valid_in_m;
wire ccr_valid_lth_m;
wire ccr_valid_in_b;
wire ccr_valid_lth_b;
wire wr_ccr_w_tid0;
wire ccr_valid_lth_w;
wire wr_ccr_w_tid1;
wire wr_ccr_w_tid2;
wire wr_ccr_w_tid3;
wire wr_ccr_tlu0;
wire wr_ccr_tlu1;
wire wr_ccr_tlu2;
wire wr_ccr_tlu3;
wire wr_ccr_asi0;
wire [1:0] rng_tid;
wire wr_ccr_asi1;
wire wr_ccr_asi2;
wire wr_ccr_asi3;
wire [7:0] arch_ccr_tid0_in;
wire [7:0] ccr_data_lth_w;
wire [7:0] arch_ccr_tid0_lth;
wire [7:0] arch_ccr_tid1_in;
wire [7:0] arch_ccr_tid1_lth;
wire [7:0] arch_ccr_tid2_in;
wire [7:0] arch_ccr_tid2_lth;
wire [7:0] arch_ccr_tid3_in;
wire [7:0] arch_ccr_tid3_lth;
wire i_ccr_pipe_lth_scanin;
wire i_ccr_pipe_lth_scanout;
wire [7:0] ccr_data_lth_m;
wire ccr_valid_lth_e;
wire i_ccr_arch_lth_wmr_scanin;
wire i_ccr_arch_lth_wmr_scanout;
wire ccr_e_cmp;
wire ccr_m_cmp;
wire ccr_b_cmp;
wire ccr_w_cmp;
wire ccr_sel_e;
wire ccr_sel_m;
wire ccr_sel_b;
wire ccr_sel_w;
wire ccr_sel_a0;
wire ccr_sel_a1;
wire ccr_sel_a2;
wire ccr_sel_a3;
wire [7:0] exu_ccr_byp_data0;
wire [7:0] exu_ccr_byp_data1;
wire ccr_byp_data_b1;
wire ccr_byp_data_b3;
wire trap_taken_e;
wire tcc_taken_e;
wire trap_taken_m_lth;
wire ms_icc_in;
wire tas_tv_overflow_m_in;
wire tas_tv_overflow_m_lth;
wire normal_va_hole_m_;
wire special_ls_va_hole_m_;
wire special_br_va_hole_m_;
wire va_hole_m;
wire pstate_am_m;
wire itlb_bypass_m;
wire misalign_error_m_in;
wire pstate_am_d;
wire i_tlu_lth_scanin;
wire i_tlu_lth_scanout;
wire yreg_mwr_valid_em3_in;
wire yreg_mwr_valid_em2_in;
wire yreg_mwr_valid_em2_lth;
wire yreg_mwr_valid_em1_in;
wire yreg_mwr_valid_em1_lth;
wire yreg_mwr_valid_e_in;
wire yreg_mwr_valid_e_lth;
wire yreg_mwr_valid_m_in;
wire yreg_mwr_valid_m_lth;
wire yreg_swr_valid_e_in;
wire yreg_swr_valid_m_in;
wire yreg_swr_valid_m_lth;
wire yreg_wr_valid_b_in;
wire yreg_mwr_valid_b_lth;
wire yreg_swr_valid_b_lth;
wire i_yreg_mpipe_lth_scanin;
wire i_yreg_mpipe_lth_scanout;
wire i_yreg_spipe_lth_scanin;
wire i_yreg_spipe_lth_scanout;
wire [7:0] lmask_e;
wire [7:0] rmask_e;
wire [7:0] lrmask_e;
wire [7:0] lmask_le8;
wire [7:0] lmask_le16;
wire [7:0] lmask_le32;
wire [7:0] lrmask_le8;
wire [7:0] lrmask_le16;
wire [7:0] lrmask_le32;
wire [2:0] cctype_d;
wire [3:0] brcond_d;
wire fgu_tid_ff_scanin;
wire fgu_tid_ff_scanout;
wire [2:0] fgu_cmp_fcc_tid_fx3;
wire [2:0] fgu_fld_fcc_tid_fx3;
wire [3:0] fcc_cw_valid;
wire sel_ct0;
wire sel_ct1;
wire sel_ct2;
wire sel_ct3;
wire [3:0] fcc_cw_t0;
wire [3:0] fcc_cw_t1;
wire [3:0] fcc_cw_t2;
wire [3:0] fcc_cw_t3;
wire [1:0] fcc_lw_valid;
wire sel_lt0;
wire sel_lt1;
wire sel_lt2;
wire sel_lt3;
wire [1:0] fcc_lw_t0;
wire [1:0] fcc_lw_t1;
wire [1:0] fcc_lw_t2;
wire [1:0] fcc_lw_t3;
wire [7:0] t0_data_in;
wire [7:0] t0_hold_in;
wire [7:0] fcc_t0_d;
wire [7:0] fcc_nxt_t0;
wire fcc_t0_ff_wmr_scanin;
wire fcc_t0_ff_wmr_scanout;
wire [7:0] t1_data_in;
wire [7:0] t1_hold_in;
wire [7:0] fcc_t1_d;
wire [7:0] fcc_nxt_t1;
wire fcc_t1_ff_wmr_scanin;
wire fcc_t1_ff_wmr_scanout;
wire [7:0] t2_data_in;
wire [7:0] t2_hold_in;
wire [7:0] fcc_t2_d;
wire [7:0] fcc_nxt_t2;
wire fcc_t2_ff_wmr_scanin;
wire fcc_t2_ff_wmr_scanout;
wire [7:0] t3_data_in;
wire [7:0] t3_hold_in;
wire [7:0] fcc_t3_d;
wire [7:0] fcc_nxt_t3;
wire fcc_t3_ff_wmr_scanin;
wire fcc_t3_ff_wmr_scanout;
wire [7:0] fcc_d;
wire use_fcc0_d;
wire use_fcc1_d;
wire use_fcc2_d;
wire use_fcc3_d;
wire [1:0] curr_fcc_d;
wire [3:0] fcc_dec_d;
wire fcce_ff_scanin;
wire fcce_ff_scanout;
wire [3:0] fcc_dec_e;
wire brcond_e_reg_scanin;
wire brcond_e_reg_scanout;
wire [3:0] br_cond_e;
wire use_xcc_d;
wire [7:0] ccr_byp_data;
wire [3:0] cc_d;
wire ccreg_e_scanin;
wire ccreg_e_scanout;
wire [3:0] cc_e;
wire [3:0] brcond_e;
wire ltz_e;
wire [7:0] cc_breval_e;
wire cc_eval0;
wire cc_eval1;
wire [7:0] fp_breval_e;
wire fp_eval0;
wire fp_eval1;
wire cctype_reg_scanin;
wire cctype_reg_scanout;
wire [2:2] cctype_e;
wire fpcond_mvbr_e;
wire cc_eval;
wire cond_true_e;
wire misc_ff_scanin;
wire misc_ff_scanout;
wire callclass_e;
wire specbr_e;
wire cmov_e;
wire regop_e;
wire r_eval1;
wire r_eval0;
wire final_cond_true_z0_e;
wire final_cond_true_z1_e;
wire spares_scanin;
wire spares_scanout;


// *** Global Inputs ***

input		l2clk;
input 		scan_in;
input		wmr_scan_in;
input 		tcu_pce_ov;		// scan signals
input 		spc_aclk;
input 		spc_bclk;
input		spc_aclk_wmr;
input		tcu_scan_en;

input  [1:0]	dec_tid_p;

input		dec_inst_rs1_vld_p;
input		dec_inst_rs2_vld_p;
input		dec_inst_rs3_vld_p;
input  [4:0]	dec_inst_rs1_p;			// window operations must be taken into account
input  [4:0]	dec_inst_rs2_p;
input  [4:0]	dec_inst_rs3_p;
input  [4:0]	dec_inst_rd_d;
input  [31:5]	dec_inst_d;
input		dec_decode_d;			// Instruction and TID are valid
input		dec_thread_group;		// Static Signal : Tie UP or DOWN where cloning occurs

input		dec_valid_e;			// inst is truly valid at e (annul)
input		tlu_itlb_bypass_e;		// Ignore Address Out-Of-Range

input		dec_flush_m;
input		dec_flush_b;

input  [3:0]	fgu_exu_icc_fx5;		// FGU int icc cond code {N,Z,V,C}
input  [1:0]	fgu_exu_xcc_fx5;		// FGU int xcc cond code {N,Z}
input		fgu_exu_cc_vld_fx5;		// FGU int icc/xcc cond code valid
input  [1:0]	fgu_result_tid_fx5;
input  [4:0]	fgu_irf_w_addr_fx5;
input		fgu_exu_w_vld_fx5;

input		lsu_exu_ld_b;
input  [4:0]	lsu_exu_rd_m;
input  [2:0]	lsu_exu_tid_m;
input		lsu_exu_ld_vld_w;

input		tlu_flush_exu_b;		// EXU to flush instr in B stage
input  [7:0]	tlu_ccr;
input		tlu_ccr_cwp_valid;
input  [1:0]	tlu_ccr_cwp_tid;
input  [3:0]	tlu_pstate_am;			// 32-bit addressing mode if = 1

input		lsu_exu_pmen;			// Power Management : Master Enable
input  [3:0]	spc_core_running_status;	// Power Management : Thread active

input		mbi_run; 			// MBIST
input  [6:0]	mbi_addr; 			// MBIST
input		mbi_irf_write_en; 		// MBIST


// *** Local  Inputs ***

input  [7:0]	edp_rng_in_ff;			// ASI Ring : In data flopped
input		edp_rng_in_ff_b56;
input		edp_rng_in_ff_b57;
input		rml_rng_wt_ccr_ctl;

input  [1:0]	edp_br_flag_e;			// [1] : RS1 negative;  [0] : RS1 zero;
input  [63:0]	exu_rs1_data_e;
input  [63:0]	exu_rs2_data_e;

input		edp_add_cout64_e;
input		edp_add_data_e_b63;
input		edp_add_data_e_b31;
input		edp_add_data_e_b1;
input		edp_add_data_e_b0;
input  [1:0]	edp_add_zdetect_e_;

input		edp_sub_cout64_e;
input		edp_sub_data_e_b63;
input		edp_sub_data_e_b31;
input  [1:0]	edp_sub_zdetect_e_;

input		edp_logical_data_e_b63;
input		edp_logical_data_e_b31;
input  [1:0]	edp_lg_zdetect_e;

input  [63:47]	edp_address_m;
input  [63:47]	edp_rd_ff_m;

input		exu_ecc_m;

input 		rml_test_valid_d;


// *** DEC_CCR Inputs ***

input  [7:0]	fgu_fld_fcc_fx3;		// fcc's from the fgu
input  [2:0]	lsu_fgu_fld_tid_b;
input  [1:0]	fgu_fld_fcc_vld_fx3;
input		lsu_fgu_fld_vld_w;		// Float load valid

input  [1:0]	fgu_cmp_fcc_fx3;		// fcc's from the fgu
input  [2:0]	fgu_cmp_fcc_tid_fx2;
input  [3:0]	fgu_cmp_fcc_vld_fx3;

input  [3:0]	dec_pick_d;			// which stand is valid at d


// *** Global Outputs ***

output [5:0]	exu_mdp_mux_sel_e;		// To MDP
output		exu_ms_icc_e;

output [1:0]	exu_gsr_vld_m;
output		exu_cmov_true_m;

output		exu_lsu_va_error_m;		// To LSU : Address Out of Range

output		exu_misalign_m;			// To TLU : Misaligned address for Jump,Return
output		exu_oor_va_m;			// To TLU : Address Out of Range
output		exu_tcc_m;			// To TLU : Trap taken
output		exu_tof_m;			// To TLU : Tagged Add TV with overflow

output [7:0]	exu_ccr0;			// To TLU : Architected CCR 
output [7:0]	exu_ccr1;			// To TLU : Architected CCR 
output [7:0]	exu_ccr2;			// To TLU : Architected CCR 
output [7:0]	exu_ccr3;			// To TLU : Architected CCR 


// *** Local  Outputs ***

output		ect_mbist_sel;

output [4:0]	ect_rs1_early_sel_d;
output [4:0]	ect_rs2_early_sel_d;
output [4:0]	ect_rs3_early_sel_d;
output [7:0]	ect_rs2_imm_sel_d;
output [3:0]	ect_rs1_late_sel_d;
output [3:0]	ect_rs2_late_sel_d;
output [3:0]	ect_rs3_late_sel_d;
output [3:0]	ect_logic_sel_d;
output [6:0]	ect_shift_sel_d;

output		ect_br_taken_z0_e;
output		ect_br_taken_z1_e;
output		ect_alignaddress_little_e;
output		ect_as_clip_e_;			// ALIGNADDRESS clipping of bit [2:0]
output		ect_as_cin_e;
output [1:0]	ect_array_sel_e;
output [7:0]	ect_edge_lmask_e;
output [7:0]	ect_edge_lrmask_e;
output		ect_pstate_am_e;
output [5:0]	ect_rm_early_sel_e;
output [2:0]	ect_rm_late_sel_e;		//  [0] : Sub;  [1] : Add;  [2] : Shift;  Def : Early Mux
output		ect_store_mux_sel_e;
output [1:0]	ect_tid_lth_e;

output [4:0]	ect_rs1_addr_e;
output [4:0]	ect_rs2_addr_e;
output [4:0]	ect_rs3_addr_e;
output		ect_rs1_valid_e;		// Allow ECC checking on RS1
output		ect_rs2_valid_e;		// Allow ECC checking on RS2
output		ect_rs3_valid_e;		// Allow ECC checking on RS3
output		ect_two_cycle_m;		// Allow ECC checking on 2nd cycle of CASA+STD

output [4:0]	ect_rd_lth_w;
output [4:0]	ect_rd_lth_w2;
output [1:0]	ect_tid_lth_w;
output [1:0]	ect_tid_lth_w2;
output		ect_valid_lth_w;
output		ect_valid_in_w2;

output		ect_yreg_wr_w;
output [7:0]	ect_rng_ccr_data;

output 		ect_misaligned_error_m;		// To RML : assert when last 2 bit of address is non "00"

output		ect_ex_emb_clken;		// Power Management
output		ect_tg_clken;			// Power Management


output 		scan_out;
output		wmr_scan_out;


// scan renames
assign pce_ov		= tcu_pce_ov;
assign stop		= 1'b0;
assign siclk		= spc_aclk;
assign soclk		= spc_bclk;
assign se		= tcu_scan_en;
// end scan


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Power Management !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


exu_ect_ctl_l1clkhdr_ctl_macro clkgen 	(
 .l2clk( l2clk			),
 .l1en ( 1'b1 			),
 .l1clk( l1clk			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


exu_ect_ctl_l1clkhdr_ctl_macro clkgen_pm1	(
 .l2clk( l2clk			),
 .l1en ( ect_tg_clken		),
 .l1clk( l1clk_pm1		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


exu_ect_ctl_l1clkhdr_ctl_macro clkgen_pm2	(
 .l2clk( l2clk			),
 .l1en (     ex_dw1_clken	),
 .l1clk( l1clk_pm2		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


assign tg_active	= (spc_core_running_status[3:0] != 4'b0000);

exu_ect_ctl_msff_ctl_macro__width_5		i_pwr0_lth		 (
 .scan_in(i_pwr0_lth_scanin),
 .scan_out(i_pwr0_lth_scanout),
 .l1clk( l1clk											),
 .din  ({~lsu_exu_pmen , tg_active     , mbi_run     , lsu_exu_tid_m[2] , lsu_exu_tid_b[2]}	),
 .dout ({pmen_lth_     , tg_active_lth , mbi_run_lth , lsu_exu_tid_b[2] , tid_lth_w2[2]}	),
  .siclk(siclk),
  .soclk(soclk));


exu_ect_ctl_msff_ctl_macro__width_5		i_pwr1_lth		 (
 .scan_in(i_pwr1_lth_scanin),
 .scan_out(i_pwr1_lth_scanout),
 .l1clk( l1clk_pm1						),
 .din  ({dec_decode_d , dec_valid_e , pwr_m , pwr_b , pwr_w}	),
 .dout ({pwr_e        ,	pwr_m       , pwr_b , pwr_w , pwr_w_p1}	),
  .siclk(siclk),
  .soclk(soclk));


assign ect_tg_clken	= pmen_lth_ | tg_active_lth | mbi_run_lth;
assign ect_ex_emb_clken	= pmen_lth_ |                 mbi_run_lth |                pwr_e | pwr_m | pwr_b;
assign     ex_dw1_clken	= pmen_lth_ |                 mbi_run_lth | dec_decode_d | pwr_e | pwr_m | pwr_b | pwr_w | pwr_w_p1;

assign ect_mbist_sel	=                             mbi_run_lth;


exu_ect_ctl_msff_ctl_macro__width_8		i_mbist_lth		 (
 .scan_in(i_mbist_lth_scanin),
 .scan_out(i_mbist_lth_scanout),
 .l1clk( l1clk_pm1					),
 .din  ({mbi_irf_write_en    , mbi_addr[6:0]}		),
 .dout ({mbi_irf_write_en_p1 , mbi_addr_p1[6:0]}	),
  .siclk(siclk),
  .soclk(soclk));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Power Management !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Decode       !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!

// *** WARNING : Full decodes used until unit is functional - then use espresso


//	assign inst[29:25]		= dec_inst_d[29:25];


// *** ADD/SUB ***

//	assign d_add			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0000);
//	assign d_addcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0000);
//	assign d_addc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1000);
//	assign d_addccc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1000);
								      
//	assign d_sub			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0100);
//	assign d_subcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0100);
//	assign d_subc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1100);
//	assign d_subccc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1100);

//	assign d_taddcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0000);		 // pg 234 : Tagged Add
//	assign d_taddcctv		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0010);		 // pg 234 : Tagged Add
//	assign d_tsubcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0001);		 // pg 235 : Tagged Sub
//	assign d_tsubcctv		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0011);		 // pg 235 : Tagged Sub

//	assign d_save			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1100);		 // pg 214 : Save
//	assign d_restore		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1101);		 // pg 214 : Restore

//	assign add_d			= d_add | d_addcc | d_addc  | d_addccc       | d_taddcc | d_taddcctv | bmask_d | alignaddress_d | alignaddress_little_d;
//	assign sub_d			= d_sub | d_subcc | d_subc  | d_subccc       | d_tsubcc | d_tsubcctv;
//	assign addsub_d			= add_d | sub_d   | bmask_d | alignaddress_d | alignaddress_little_d;

//	assign as_subtract_d		= sub_d | edge_d;

//	assign as_cc_d			= d_addcc | d_addccc | d_subcc | d_subccc | d_taddcc | d_taddcctv | d_tsubcc | d_tsubcctv | edge_cc_d;
//	assign tas_cc_d			=                                           d_taddcc | d_taddcctv | d_tsubcc | d_tsubcctv;
//	assign tas_tv_d			=                                                      d_taddcctv |            d_tsubcctv;

//	assign as_cin_d			= ((d_sub    | d_subcc   )                   ) |
//					  ((d_tsubcc | d_tsubcctv)                   ) |
//					  ( edge_d                                   ) |
//					  ((d_subc   | d_subccc  ) & ~ccr_byp_data_b0) |
//					  ((d_addc   | d_addccc  ) &  ccr_byp_data_b0);

	assign as_cin_d			=  as_cin_set_d                      |
					  (as_cin_ccr0_d & ~ccr_byp_data_b0) |
					  (as_cin_ccr1_d &  ccr_byp_data_b0);


// *** LOGICAL
									      
//	assign d_and			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0001);
//	assign d_andcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0001);
//	assign d_andn			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0101);
//	assign d_andncc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0101);
//	assign d_or			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0010);
//	assign d_orcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0010);
//	assign d_orn			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0110);
//	assign d_orncc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0110);
//	assign d_xor			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0011);
//	assign d_xorcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0011);
//	assign d_xorn			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_0111);
//	assign d_xorncc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_0111);

//	assign logic_rs2_d		= sethi_d | mov_cond_d;

//	assign logic_d			= d_and | d_andcc | d_andn | d_andncc | d_or | d_orcc | d_orn | d_orncc | d_xor | d_xorcc | d_xorn | d_xorncc | logic_rs2_d;
//	assign logic_sel_d[3]		= d_and | d_andcc |                     d_or | d_orcc | d_orn | d_orncc |                   d_xorn | d_xorncc | logic_rs2_d | casa_d;
//	assign logic_sel_d[2]		=                   d_andn | d_andncc | d_or | d_orcc | d_orn | d_orncc | d_xor | d_xorcc                                   | casa_d;
//	assign logic_sel_d[1]		=                                       d_or | d_orcc |                   d_xor | d_xorcc                     | logic_rs2_d;
//	assign logic_sel_d[0]		=                                                       d_orn | d_orncc |                   d_xorn | d_xorncc              ;

//	assign lg_cc_d			= d_andcc | d_andncc | d_orcc | d_orncc | d_xorcc | d_xorncc;


// *** SHIFT ***

//	assign d_sll			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0101) & (inst[12] == 1'b0);
//	assign d_srl			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0110) & (inst[12] == 1'b0);
//	assign d_sra			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0111) & (inst[12] == 1'b0);
//	assign d_sllx			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0101) & (inst[12] == 1'b1);
//	assign d_srlx			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0110) & (inst[12] == 1'b1);
//	assign d_srax			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0111) & (inst[12] == 1'b1);

//	assign shift_d			= d_sll | d_srl | d_sra | d_sllx | d_srlx | d_srax;
//	assign shift_sel_d[6]		=         d_srl | d_sra |          d_srlx | d_srax;
//	assign shift_sel_d[5]		= d_sll |                 d_sllx                  ;
//	assign shift_sel_d[4]		=                                           d_srax;
//	assign shift_sel_d[3]		=                 d_sra                           ;
//	assign shift_sel_d[2]		=                                  d_srlx | d_srax;
//	assign shift_sel_d[1]		=                         d_sllx                  ;
//	assign shift_sel_d[0]		= d_sll | d_srl | d_sra                           ;


// *** EDGE ***

//	assign d_edge8			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0000);	// VIS pg. 70
//	assign d_edge8n			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0001);	// VIS pg. 70
//	assign d_edge8l			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0010);	// VIS pg. 70
//	assign d_edge8ln		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0011);	// VIS pg. 70
//	assign d_edge16			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0100);	// VIS pg. 70
//	assign d_edge16n		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0101);	// VIS pg. 70
//	assign d_edge16l		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0110);	// VIS pg. 70
//	assign d_edge16ln		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_0111);	// VIS pg. 70
//	assign d_edge32			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_1000);	// VIS pg. 70
//	assign d_edge32n		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_1001);	// VIS pg. 70
//	assign d_edge32l		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_1010);	// VIS pg. 70
//	assign d_edge32ln		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0000_1011);	// VIS pg. 70

//	assign edge08_d			= d_edge8   | d_edge8n  | d_edge8l  | d_edge8ln;
//	assign edge16_d			= d_edge16  | d_edge16n | d_edge16l | d_edge16ln;
//	assign edge32_d			= d_edge32  | d_edge32n | d_edge32l | d_edge32ln;
//	assign edge_d			= edge08_d  | edge16_d  | edge32_d;
//	assign edgele_d			= d_edge8l  | d_edge8ln | d_edge16l | d_edge16ln | d_edge32l | d_edge32ln;

//	assign edge_cc_d		= d_edge8   | d_edge8l  | d_edge16  | d_edge16l  | d_edge32  | d_edge32l;


// *** ARRAY ***

//	assign array08_d		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0001_0000);	// VIS pg. 74
//	assign array16_d		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0001_0010);	// VIS pg. 74
//	assign array32_d		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:05] == 9'b0_0001_0100);	// VIS pg. 74

//	assign array_d			= array08_d | array16_d | array32_d;


// *** BRANCH ***

//	assign bpr_d			= (inst[31:30] == 2'b00) & (inst[28] == 1'b0) & (inst[24:22] == 3'b011);	// pg 136 : sign_ext{[21:20],[13:0]}
//	assign bicc_d			= (inst[31:30] == 2'b00) &                      (inst[24:22] == 3'b010);	// pg 144 : sign_ext{[21:0]}
//	assign bpcc_d			= (inst[31:30] == 2'b00) &                      (inst[24:22] == 3'b001);	// pg 146 : sign_ext{[18:0]}
//	assign call_d			= (inst[31:30] == 2'b01);							// pg 149 : sign_ext{[29:0]}
//	assign fbfcc_d			= (inst[31:30] == 2'b00) &                      (inst[24:22] == 3'b110);	// pg 138 : sign_ext{[21:0]}
//	assign fbpfcc_d			= (inst[31:30] == 2'b00) &                      (inst[24:22] == 3'b101);	// pg 141 : sign_ext{[18:0]}

//	assign branch_d			= bpr_d | bicc_d | bpcc_d | call_d | fbfcc_d | fbpfcc_d;


// *** Conditional Move ***

//	assign fmovcc_d			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0101) & (inst[18] == 1'b0);	// pg 185 : Move FP  on Condition Code
//	assign fmovr_d			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0101) & (inst[13] == 1'b0);	// pg 189 : Move FP  on Integer reg
//	assign movcc_d			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1100);				// pg 189 : Move Int on Condition Code
//	assign movr_d			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1111);				// pg 189 : Move Int on Integer reg

//	assign mov_cond_d		= movcc_d | movr_d;

// *** LOAD & STORE ***

//	assign d_ldf			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0000);		// pg 171 : Load Floating Point
//	assign d_lddf			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0011);		// pg 171 : Load Floating Point
//	assign d_ldqf			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0010);		// pg 171 : Load Floating Point
//	assign d_ldfsr			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0001);		// pg 171 : Load Floating Point
//	assign d_ldxfsr			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0001);		// pg 171 : Load Floating Point

//	assign d_ldfa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0000);		// pg 173 : Load Floating Point from Alternate Space
//	assign d_lddfa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0011);		// pg 173 : Load Floating Point from Alternate Space
//	assign d_ldqfa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0010);		// pg 173 : Load Floating Point from Alternate Space

//	assign d_ldsb			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1001);		// pg 175 : Load Integer
//	assign d_ldsh			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1010);		// pg 175 : Load Integer
//	assign d_ldsw			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1000);		// pg 175 : Load Integer
//	assign d_ldub			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0001);		// pg 175 : Load Integer
//	assign d_lduh			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0010);		// pg 175 : Load Integer
//	assign d_lduw			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0000);		// pg 175 : Load Integer
//	assign d_ldx			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1011);		// pg 175 : Load Integer
//	assign d_ldd			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0011);		// pg 175 : Load Integer

//	assign d_ldsba			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1001);		// pg 177 : Load Integer from Alternate Space
//	assign d_ldsha			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1010);		// pg 177 : Load Integer from Alternate Space
//	assign d_ldswa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1000);		// pg 177 : Load Integer from Alternate Space
//	assign d_lduba			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0001);		// pg 177 : Load Integer from Alternate Space
//	assign d_lduha			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0010);		// pg 177 : Load Integer from Alternate Space
//	assign d_lduwa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0000);		// pg 177 : Load Integer from Alternate Space
//	assign d_ldxa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1011);		// pg 177 : Load Integer from Alternate Space
//	assign d_ldda			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0011);		// pg 177 : Load Integer from Alternate Space

//	assign d_ldstub			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1101);		// pg 179 : Load-Store
//	assign d_ldstuba		= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1101);		// pg 180 : Load-Store from Alternate Space

//	assign d_prefetch		= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_1101);		// pg 203 : Prefetch Data
//	assign d_prefetcha		= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_1101);		// pg 203 : Prefetch Data from Alternate Space


//	assign load_d			= d_ldf      | d_lddf    | d_ldfsr | d_ldxfsr |
//					  d_ldfa     | d_lddfa   |
//					  d_ldsb     | d_ldsh    | d_ldsw  | d_ldub   | d_lduh  | d_lduw  | d_ldx  |  d_ldd  |
//					  d_ldsba    | d_ldsha   | d_ldswa | d_lduba  | d_lduha | d_lduwa | d_ldxa |  d_ldda |
//					  d_ldstub   | d_ldstuba |
//					  d_prefetch | d_prefetcha;

//	assign int_load_d		= d_ldsb     | d_ldsh    | d_ldsw  | d_ldub   | d_lduh  | d_lduw  | d_ldx  |  d_ldd  |
//					  d_ldsba    | d_ldsha   | d_ldswa | d_lduba  | d_lduha | d_lduwa | d_ldxa |  d_ldda |
//					  d_ldstub   | d_ldstuba;


//	assign d_stf			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0100);		// pg 222 : Store Floating Point
//	assign d_stdf			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0111);		// pg 222 : Store Floating Point
//	assign d_stqf			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0110);		// pg 222 : Store Floating Point
//	assign d_stfsr			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0101);		// pg 222 : Store Floating Point
//	assign d_stxfsr			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b10_0101);		// pg 222 : Store Floating Point

//	assign d_stfa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0100);		// pg 224 : Store Floating Point from Alternate Space
//	assign d_stdfa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0111);		// pg 224 : Store Floating Point from Alternate Space
//	assign d_stqfa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_0110);		// pg 224 : Store Floating Point from Alternate Space

//	assign d_stb			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0101);		// pg 226 : Store Integer
//	assign d_sth			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0110);		// pg 226 : Store Integer
//	assign d_stw			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0100);		// pg 226 : Store Integer
//	assign d_stx			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1110);		// pg 226 : Store Integer
//	assign d_std			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_0111);		// pg 226 : Store Integer

//	assign d_stba			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0101);		// pg 226 : Store Integer from Alternate Space
//	assign d_stha			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0110);		// pg 226 : Store Integer from Alternate Space
//	assign d_stwa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0100);		// pg 226 : Store Integer from Alternate Space
//	assign d_stxa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1110);		// pg 226 : Store Integer from Alternate Space
//	assign d_stda			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_0111);		// pg 226 : Store Integer from Alternate Space

//	assign d_swap			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b00_1111);		// pg 231 : Swap Register with Memory
//	assign d_swapa			= (inst[31:30] == 2'b11) & (inst[24:19] == 6'b01_1111);		// pg 232 : Swap Register with Alt Space Memory


//	assign casa_d			=((inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_1100))|	// pg 150 : Compare and Swap
//					 ((inst[31:30] == 2'b11) & (inst[24:19] == 6'b11_1110));	// pg 150 : Compare and Swap


//	assign store_d			= d_stf    | d_stdf   | d_stfsr | d_stxfsr |
//					  d_stfa   | d_stdfa  |
//					  d_stb    | d_sth    | d_stw   |  d_stx   | d_std  |
//					  d_stba   | d_stha   | d_stwa  |  d_stxa  | d_stda |
//					  d_swap   | d_swapa;


// *** VIS ***

//	assign bmask_d			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:5] == 9'b0_0001_1001);
//	assign alignaddress_d		= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:5] == 9'b0_0001_1000);
//	assign alignaddress_little_d	= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0110) & (inst[13:5] == 9'b0_0001_1010);


// *** FGU ***

//	assign d_udiv			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1110);		// pg 152 : Unsigned Integer Division
//	assign d_sdiv			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1111);		// pg 152 :   Signed Integer Division
//	assign d_udivcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1110);		// pg 152 : Unsigned Integer Division
//	assign d_sdivcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1111);		// pg 152 :   Signed Integer Division

//	assign d_mulx			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1001);		// pg 196 : Multiply (signed or unsigned)
//	assign d_sdivx			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1101);		// pg 196 :   Signed Divide
//	assign d_udivx			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1101);		// pg 196 : Unsigned Divide

//	assign d_umul			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1010);		// pg 197 : Unsigned Integer Multiply
//	assign d_smul			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b00_1011);		// pg 197 :   Signed Integer Multiply
//	assign d_umulcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1010);		// pg 197 : Unsigned Integer Multiply
//	assign d_smulcc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b01_1011);		// pg 197 :   Signed Integer Multiply

//	assign d_mulscc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_0100);		// pg 199 : Multiply Step

//	assign d_popc			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1110);		// pg 202 : Population Count

//	assign int_to_fgu_d		= d_udiv   | d_sdiv  | d_udivcc | d_sdivcc |
//					  d_mulx   | d_sdivx | d_udivx  |
//					  d_umul   | d_smul  | d_umulcc | d_smulcc |
//					  d_mulscc | d_popc;

//	assign mux_mdp_sel_d[0]		= d_smul   | d_smulcc;
//	assign mux_mdp_sel_d[1]		= d_umul   | d_umulcc;
//	assign mux_mdp_sel_d[2]		= d_udiv   | d_sdiv   | d_udivcc | d_sdivcc;
//	assign mux_mdp_sel_d[3]		= d_mulscc;
//	assign mux_mdp_sel_d[4]		= d_sdiv   | d_sdivcc | d_smul   | d_smulcc;
//	assign mux_mdp_sel_d[5]		= d_udiv   | d_udivcc | d_umul   | d_umulcc | d_mulscc;


// *** MISC ***

//	assign jmpl_d			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1000);
//	assign return_d			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1001);
//	assign sethi_d			= (inst[31:30] == 2'b00) & (inst[24:22] == 3'b10_0   );
//	assign sir_d			= (inst[31:30] == 2'b10) & (inst[29:14] == 16'b01111_11_0000_00000);	// pg 220
//	assign tcc_d			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1010);			// pg 237 : Trap on Integer Condition
//	assign d_wrpr			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0010);			// pg 239 : Write Privileged Register
//	assign d_wry			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0000);			// pg 241 : Write State      Register
//	assign d_wrhpr			= (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_0011);			//
//	assign wrxx_d			= (d_wrpr  | d_wry  | d_wrhpr) & dec_decode_d;
	assign wrxx_d			=  wrxx_raw_d & dec_decode_d;

//	assign address_d		= branch_d | load_d | store_d | return_d | casa_d;

//	assign exu_op_d			= logic_d | shift_d | add_d | sub_d | jmpl_d | edge_d | array_d;


// *** Operand Selects ***

	assign ect_rs1_early_sel_d[0]	=  rs1_m_cmp;
	assign ect_rs1_early_sel_d[1]	=  rs1_b_cmp;
	assign ect_rs1_early_sel_d[2]	=  rs1_w_cmp;
 	assign ect_rs1_early_sel_d[3]	=  rs1_w2_cmp;
 	assign ect_rs1_early_sel_d[4]	=  rs1_w_plus1_cmp;

	assign ect_rs1_late_sel_d[0]	=  branch_d;								// PC
	assign ect_rs1_late_sel_d[1]	=  rs1_e_cmp;								// E Stage Bypass
	assign ect_rs1_late_sel_d[2]	=  rs1_l_cmp & ~rs1_m_cmp;						// Load    Bypass
	assign ect_rs1_late_sel_d[3]	=  rs1_byp_early;

//	assign ect_rs2_imm_sel_d[0]	=  bpr_d;								// immediate BPr = {[21:20],[13:0]}
//	assign ect_rs2_imm_sel_d[1]	=  bicc_d   | fbfcc_d;							// immediate disp22
//	assign ect_rs2_imm_sel_d[2]	=  bpcc_d   | fbpfcc_d;							// immediate disp19
//	assign ect_rs2_imm_sel_d[3]	=  call_d;								// immediate disp30
//	assign ect_rs2_imm_sel_d[4]	=  sethi_d;								// IMM22
//	assign ect_rs2_imm_sel_d[5]	=  movcc_d;								// SIMM11
//	assign ect_rs2_imm_sel_d[6]	=  movr_d;								// SIMM10
//	assign ect_rs2_imm_sel_d[7]	=  rs2_imm13_data_d;							// SIMM13
	assign ect_rs2_imm_sel_d[7:0]	= {rs2_imm_sel7_d,rs2_imm_sel6_d,rs2_imm_sel5_d,rs2_imm_sel4_d,rs2_imm_sel3_d,rs2_imm_sel2_d,rs2_imm_sel1_d,rs2_imm_sel0_d};


	assign ect_rs2_early_sel_d[0]	=  rs2_m_cmp;
	assign ect_rs2_early_sel_d[1]	=  rs2_b_cmp;
	assign ect_rs2_early_sel_d[2]	=  rs2_w_cmp;
 	assign ect_rs2_early_sel_d[3]	=  rs2_w2_cmp;
 	assign ect_rs2_early_sel_d[4]	=  rs2_w_plus1_cmp;

//	assign rs2_imm13_data_d		= (d_save   | d_restore | logic_d  | add_d  | sub_d   | shift_d | load_d | store_d | jmpl_d |
//					   return_d | sir_d     | tcc_d    | d_wrpr | d_wrhpr | d_wry   | int_to_fgu_d) & inst[13];

//	assign rs2_imm_data_d		=  branch_d | sethi_d | rs2_imm13_data_d;


	assign ect_rs2_late_sel_d[0]	=  rs2_imm_data_d;							// Immediate
	assign ect_rs2_late_sel_d[1]	=  rs2_e_cmp;								// E Stage Bypass
	assign ect_rs2_late_sel_d[2]	=  rs2_l_cmp & ~rs2_m_cmp;						// Load    Bypass
	assign ect_rs2_late_sel_d[3]	=  rs2_byp_early;


	assign ect_rs3_early_sel_d[0]	=  rs3_m_cmp;
	assign ect_rs3_early_sel_d[1]	=  rs3_b_cmp;
	assign ect_rs3_early_sel_d[2]	=  rs3_w_cmp;
 	assign ect_rs3_early_sel_d[3]	=  rs3_w2_cmp;
 	assign ect_rs3_early_sel_d[4]	=  rs3_w_plus1_cmp;

	assign ect_rs3_late_sel_d[0]	=  rs1_late_sel4_d &  dec_decode_d & ~rml_test_valid_d;			// call_d | jmpl_d
	assign ect_rs3_late_sel_d[1]	=  rs3_e_cmp                       & ~rml_test_valid_d;
	assign ect_rs3_late_sel_d[2]	=  rs3_l_cmp       & ~rs3_m_cmp    & ~rml_test_valid_d;
	assign ect_rs3_late_sel_d[3]	=  rs3_byp_early                   & ~rml_test_valid_d;


// *** RESULT MUX ***

//	assign rm_late_sel_d[0]		= sub_d;
//	assign rm_late_sel_d[1]		= add_d | tcc_d | load_d | store_d | return_d | bpr_d | bicc_d | bpcc_d | fbfcc_d | fbpfcc_d;
//	assign rm_late_sel_d[2]		= shift_d;

//	assign rm_early_sel_d[0]	= logic_d | casa_d;
//	assign rm_early_sel_d[1]	= array_d;
//	assign rm_early_sel_d[2]	= edge_d;
//	assign rm_early_sel_d[3]	= d_mulscc;
//	assign rm_early_sel_d[4]	= call_d | jmpl_d;


// The ESPRESSO code below was generated from the EXU's "decode" file using the following command :
//
//      ~rg131678/perl/n2decode -i decode -exu > decode.out
//

	assign i[31:5]		= dec_inst_d[31:5];

// --- autogenerated by n2decode view=exu Tue Aug 16 16:43:11 CDT 2005

assign as_subtract_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[12]&!i[11]
    &!i[10]&!i[9]) | (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[19]) | (
    i[31]&!i[30]&!i[24]&i[21]&!i[20]&!i[19]);

assign as_cc_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[11]&!i[10]&!i[9]
    &!i[5]) | (i[31]&!i[30]&!i[24]&i[23]&!i[20]&!i[19]) | (i[31]&!i[30]
    &i[24]&!i[23]&!i[22]&!i[21]);

assign tas_cc_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]);

assign tas_tv_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[20]);

assign as_cin_set_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[12]&!i[11]
    &!i[10]&!i[9]) | (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[19]) | (
    i[31]&!i[30]&!i[24]&!i[22]&i[21]&!i[20]&!i[19]);

assign as_cin_ccr0_d = (i[31]&!i[24]&i[22]&i[21]&!i[20]&!i[19]);

assign as_cin_ccr1_d = (i[31]&!i[30]&!i[24]&i[22]&!i[21]&!i[20]&!i[19]);

assign logic_sel3_d = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]&i[12]&i[11]
    &!i[10]&!i[9]) | (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&!i[30]
    &!i[24]&!i[22]&!i[21]&!i[20]&i[19]) | (i[31]&!i[30]&!i[24]&!i[22]
    &i[21]&i[20]) | (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | (
    i[31]&i[24]&i[22]&i[21]&i[20]&i[19]) | (i[31]&!i[30]&!i[24]&!i[22]
    &i[20]&!i[19]) | (!i[31]&!i[30]&!i[23]&!i[22]);

assign logic_sel2_d = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]&i[12]&i[11]
    &!i[10]&!i[9]) | (i[31]&!i[30]&!i[24]&!i[22]&i[21]&!i[20]&i[19]) | (
    i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&!i[30]&!i[24]&!i[22]&!i[21]
    &i[20]) | (i[31]&!i[30]&!i[24]&!i[22]&i[20]&!i[19]);

assign logic_sel1_d = (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | (i[31]
    &i[24]&i[22]&i[21]&i[20]&i[19]) | (i[31]&!i[30]&!i[24]&!i[22]&!i[21]
    &i[20]) | (!i[31]&!i[30]&!i[23]&!i[22]);

assign logic_sel0_d = (i[31]&!i[30]&!i[24]&!i[22]&i[21]&i[20]);

assign lg_cc_d = (i[31]&!i[30]&!i[24]&i[23]&!i[20]&i[19]) | (i[31]&!i[30]&!i[24]
    &i[23]&!i[22]&i[20]);

assign shift_sel6_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]&i[12]) | (
    i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[19]&i[12]);

assign shift_sel5_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]);

assign shift_sel4_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&i[19]);

assign shift_sel3_d = (i[31]&!i[30]&i[24]&!i[22]&i[21]&i[20]&i[19]&i[12]);

assign shift_sel2_d = (i[31]&!i[30]&i[24]&!i[22]&i[21]&i[20]&i[19]&!i[12]);

assign shift_sel1_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]&i[12]);

assign shift_sel0_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&i[19]&i[12]);

assign edgele_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[11]&!i[10]
    &!i[9]&i[6]);

assign edge08_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[12]&!i[10]
    &!i[9]&!i[8]&!i[7]);

assign edge16_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[10]&!i[9]&!i[8]
    &i[7]);

assign edge32_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[11]&!i[10]
    &!i[9]&i[8]);

assign array08_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[11]&i[9]&!i[8]&!i[7]
    &!i[6]&!i[5]);

assign array16_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[11]&!i[10]&i[9]
    &!i[8]&i[6]);

assign call_d = (!i[31]&i[30]);

assign branch_d = (!i[31]&i[23]) | (!i[31]&i[22]) | (!i[31]&i[30]);

assign mov_cond_d = (i[31]&i[24]&i[22]&i[21]&i[20]&i[19]) | (i[31]&i[24]&!i[23]
    &i[22]&i[21]&!i[20]&!i[19]);

assign bmask_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[10]&i[9]&i[8]&i[5]);

assign alignaddress_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[10]&i[9]&i[8]
    &!i[6]&!i[5]);

assign alignaddress_little_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[10]
    &i[9]&i[8]&i[6]);

assign mux_mdp_sel0_d = (i[31]&!i[30]&!i[24]&i[22]&!i[21]&i[20]&i[19]);

assign mux_mdp_sel1_d = (i[31]&!i[30]&!i[24]&i[22]&!i[21]&i[20]&!i[19]);

assign mux_mdp_sel2_d = (i[31]&!i[30]&!i[24]&i[22]&i[21]&i[20]);

assign mux_mdp_sel3_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]);

assign mux_mdp_sel4_d = (i[31]&!i[30]&!i[24]&i[22]&i[20]&i[19]);

assign mux_mdp_sel5_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]) | (
    i[31]&!i[30]&!i[24]&i[22]&i[20]&!i[19]);

assign tcc_d = (!i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]);

assign wrxx_raw_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[20]&i[19]) | (i[31]&!i[30]
    &i[24]&i[23]&!i[22]&!i[21]&!i[19]);

assign address_d = (i[30]&i[22]&!i[19]) | (i[30]&!i[22]&i[19]) | (i[30]&!i[20]
    &!i[19]) | (!i[31]&i[22]) | (!i[31]&i[23]) | (i[24]&i[23]&i[22]&!i[21]
    &!i[20]) | (i[30]&!i[24]) | (!i[31]&i[30]);

assign exu_op_d = (i[31]&!i[30]&!i[22]&i[21]&i[20]&!i[12]&!i[11]&!i[10]) | (
    i[31]&i[24]&i[23]&i[22]&!i[21]&!i[20]&!i[19]) | (i[31]&i[24]&i[22]
    &i[21]&i[20]&i[19]) | (i[31]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | (
    !i[30]&!i[23]&!i[22]&i[19]) | (i[31]&!i[30]&!i[24]&!i[20]&!i[19]) | (
    !i[30]&!i[23]&!i[22]&i[20]) | (i[31]&!i[30]&!i[24]&!i[22]) | (!i[30]
    &!i[23]&!i[22]&!i[21]) | (!i[31]&!i[30]&!i[23]&!i[22]);

assign rs1_late_sel4_d = (i[24]&i[23]&i[22]&!i[21]&!i[20]&!i[19]) | (!i[31]
    &i[30]);

assign rs2_imm_sel0_d = (!i[31]&!i[30]&i[23]&i[22]);

assign rs2_imm_sel1_d = (!i[31]&!i[30]&i[23]&!i[22]);

assign rs2_imm_sel2_d = (!i[31]&!i[30]&!i[23]&i[22]);

assign rs2_imm_sel3_d = (!i[31]&i[30]);

assign rs2_imm_sel4_d = (!i[31]&!i[30]&!i[23]&!i[22]);

assign rs2_imm_sel5_d = (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]);

assign rs2_imm_sel6_d = (i[31]&i[24]&i[22]&i[21]&i[20]&i[19]);

assign rs2_imm_sel7_d = (i[31]&!i[23]&i[22]&i[21]&i[20]&!i[19]&i[13]) | (i[31]
    &!i[30]&i[23]&!i[21]&!i[19]&i[13]) | (i[31]&i[22]&i[21]&!i[20]&i[19]
    &i[13]) | (!i[30]&i[24]&i[23]&i[22]&!i[20]&i[13]) | (i[31]&!i[22]
    &i[20]&i[19]&i[13]) | (i[31]&i[30]&!i[22]&!i[20]&i[13]) | (i[31]
    &!i[30]&!i[23]&!i[22]&i[13]) | (i[31]&!i[24]&i[13]);

assign rs2_imm_data_d = (i[23]&i[22]&!i[21]&!i[19]&i[13]) | (!i[23]&!i[22]&i[19]
    &i[13]) | (!i[30]&i[23]&i[22]&!i[20]&i[13]) | (!i[30]&!i[22]&i[20]
    &i[13]) | (!i[22]&!i[20]&!i[19]&i[13]) | (!i[30]&!i[23]&i[21]&i[13]) | (
    i[30]&i[19]&i[13]) | (!i[31]) | (!i[24]&i[13]);

assign rm_late_sel0_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[19]) | (
    i[31]&!i[30]&!i[24]&i[21]&!i[20]&!i[19]);

assign rm_late_sel1_d = (i[31]&i[30]&!i[20]&i[19]) | (i[31]&i[30]&i[19]&i[13]) | (
    !i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]) | (i[31]&i[30]&i[19]
    &!i[12]) | (!i[30]&!i[24]&!i[21]&!i[20]&!i[19]) | (!i[30]&i[23]&i[22]
    &!i[21]&!i[20]&i[19]) | (i[31]&i[30]&i[19]&!i[11]) | (i[31]&i[30]
    &i[19]&i[10]) | (i[31]&i[30]&i[19]&i[9]) | (!i[30]&i[24]&i[23]&!i[22]
    &i[21]&!i[10]&i[9]&i[8]) | (i[31]&i[30]&!i[23]&i[19]) | (!i[31]&!i[30]
    &i[22]) | (!i[31]&!i[30]&i[23]) | (i[31]&i[30]&!i[24]) | (i[31]&!i[30]
    &i[24]&!i[23]&!i[22]&!i[21]&!i[19]) | (i[31]&i[30]&!i[22]&!i[20]) | (
    i[31]&i[30]&!i[21]&i[19]);

assign rm_late_sel2_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]) | (i[31]
    &!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[19]);

assign rm_early_sel0_d = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]&i[12]&i[11]
    &!i[10]&!i[9]) | (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&!i[30]
    &!i[24]&!i[22]&i[19]) | (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | (
    i[31]&i[24]&i[22]&i[21]&i[20]&i[19]) | (i[31]&!i[30]&!i[24]&!i[22]
    &i[20]) | (!i[31]&!i[30]&!i[23]&!i[22]);

assign rm_early_sel1_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[11]&!i[10]
    &i[9]&!i[8]);

assign rm_early_sel2_d = (i[31]&!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]);

assign rm_early_sel4_d = (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[12]
    &!i[11]&!i[10]&!i[9]);

assign misalign_d = (!i[30]&i[24]&i[23]&i[22]&!i[21]&!i[20]);

assign ls_special_sel_d = (i[31]&i[24]&i[23]&i[21]&i[20]&i[19]&!i[13]&i[12]
    &i[11]&!i[10]&!i[9]) | (i[31]&i[30]&i[24]&i[22]&!i[19]);

assign cmov_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[5]) | (
    i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[6]) | (i[31]
    &i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]) | (i[31]&i[24]&i[22]&i[21]
    &i[20]&i[19]);

assign regop_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&i[7]&!i[5]) | (
    i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&i[7]&!i[6]) | (
    !i[31]&!i[30]&i[23]&i[22]) | (i[31]&i[24]&i[22]&i[21]&i[20]&i[19]);

assign specbr_d = (!i[31]&!i[30]&i[23]) | (!i[31]&!i[30]&i[22]);

assign callclass_d = (i[24]&i[23]&i[22]&!i[21]&!i[20]) | (!i[31]&i[30]);

assign movcc_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[7]&!i[5]) | (
    i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[7]&!i[6]) | (
    i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]);

assign movr_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&i[7]&!i[5]) | (
    i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&i[7]&!i[6]) | (
    i[31]&i[24]&i[22]&i[21]&i[20]&i[19]);

assign br_or_tcc_d = (!i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]) | (!i[31]
    &!i[30]&i[23]) | (!i[31]&!i[30]&i[22]);

assign bcc_d = (!i[31]&!i[30]&i[23]&!i[22]);

assign bpcc_d = (!i[31]&!i[30]&!i[23]&i[22]);

assign fmov_d = (i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[7]&!i[5]) | (
    i[31]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[9]&!i[7]&!i[6]) | (
    !i[30]&i[24]&i[23]&i[22]&!i[21]&i[20]&!i[19]);

assign imov_d = (i[31]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]);

assign fp_d = (!i[31]&!i[30]&i[24]&i[23]) | (!i[31]&!i[30]&i[24]&i[22]);

assign two_cycle_d = (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&i[30]&!i[24]
    &!i[22]&i[21]&i[20]&i[19]);

// end autogeneration


// *** Embed DECODE.OUT above here ***

assign ect_logic_sel_d[3:0]	= {logic_sel3_d,logic_sel2_d,logic_sel1_d,logic_sel0_d};
assign ect_shift_sel_d[6:0]	= {shift_sel6_d,shift_sel5_d,shift_sel4_d,shift_sel3_d,shift_sel2_d,shift_sel1_d,shift_sel0_d};


exu_ect_ctl_msff_ctl_macro__width_37	i_estage_lth		 (
 .scan_in(i_estage_lth_scanin),
 .scan_out(i_estage_lth_scanout),
 .l1clk( l1clk_pm2			 			),
 .din  ({address_d						,
	 branch_d						,
	 ls_special_sel_d					,
	 two_cycle_d						,
         (~mux_mdp_sel5_d & ~mux_mdp_sel4_d),mux_mdp_sel4_d,mux_mdp_sel3_d,mux_mdp_sel2_d,mux_mdp_sel1_d,mux_mdp_sel0_d,
         rm_early_sel4_d,rs1_late_sel4_d,rm_early_sel2_d,rm_early_sel1_d,rm_early_sel0_d,
         rm_late_sel2_d,rm_late_sel1_d,rm_late_sel0_d,
         as_cin_d						,
         as_subtract_d						,
         as_cc_d,lg_cc_d 					,
	 misalign_d						,
         mov_cond_d						,
         tas_cc_d,tas_tv_d					,
         tcc_d							,
         wrxx_d							,
         bmask_d,alignaddress_d,alignaddress_little_d		,
         array16_d,array08_d					,
         edge08_d,edge16_d,edge32_d ,edgele_d			}),
 .dout ({address_e						,
	 branch_e						,
	 ls_special_sel_e					,
	 two_cycle_e						,
         exu_mdp_mux_sel_e[5:0]					,
         ect_rm_early_sel_e[5],rm_early_sel34,ect_rm_early_sel_e[2:0],
         ect_rm_late_sel_e[2:0] 				,
         ect_as_cin_e						,
         as_subtract_e						,
         as_cc_e,lg_cc_e 					,
	 misalign_e						,
         mov_cond_e						,
         tas_cc_e,tas_tv_e					,
         tcc_e							,
         ect_store_mux_sel_e					,
         bmask_e,alignaddress_e,ect_alignaddress_little_e	,
         ect_array_sel_e[1:0]					,
         edge08_e,edge16_e,edge32_e ,edgele_e			}),
  .siclk(siclk),
  .soclk(soclk));


	assign ect_rm_early_sel_e[3]	= rm_early_sel34 & ~ect_pstate_am_e;
	assign ect_rm_early_sel_e[4]	= rm_early_sel34 &  ect_pstate_am_e;

	assign ect_as_clip_e_	= ~(alignaddress_e | ect_alignaddress_little_e);


	assign gsr_vld_e_in[1]	= dec_valid_e & (alignaddress_e | ect_alignaddress_little_e);
	assign gsr_vld_e_in[0]	= dec_valid_e & bmask_e;

	assign address_e_in	= address_e   & dec_valid_e;

	assign br_special_sel_e	= branch_e    & exu_rs1_data_e[47];

	assign two_cycle_e_in	= dec_valid_e & two_cycle_e;

exu_ect_ctl_msff_ctl_macro__width_6	i_mstage_lth		 (
 .scan_in(i_mstage_lth_scanin),
 .scan_out(i_mstage_lth_scanout),
 .l1clk( l1clk_pm2											),
 .din  ({gsr_vld_e_in[1:0]  , address_e_in , ls_special_sel_e , br_special_sel_e , two_cycle_e_in} 	),
 .dout ({exu_gsr_vld_m[1:0] , address_m    , ls_special_sel_m , br_special_sel_m , ect_two_cycle_m}	),
  .siclk(siclk),
  .soclk(soclk));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Decode       !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Bypass       !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


	assign fgu_valid_b	=  fgu_exu_w_vld_fx5  &                                       ~(fgu_irf_w_addr_fx5[4:0] == 5'b00000);
	assign lsu_valid_w2	=  lsu_exu_ld_w       & (dec_thread_group == tid_lth_w2[2]) & ~(ect_rd_lth_w2[4:0]      == 5'b00000);
	assign ect_valid_in_w2	=  lsu_exu_ld_vld_w   & (dec_thread_group == tid_lth_w2[2]) & ~(ect_rd_lth_w2[4:0]      == 5'b00000) & ~ect_mbist_sel;


// *** Valids ***


	assign     valid_in_d	= (exu_op_d & ~(dec_inst_d[29:25] == 5'b00000)) | call_d;	// see SPARC v9, page 30.
	assign     valid_in_e	=  valid_out_e;
	assign     valid_in_m	=  valid_lth_m  & ~dec_flush_m & ~exu_ecc_m       & ~address_error_m;
	assign     valid_in_b	= (valid_lth_b  & ~dec_flush_b & ~tlu_flush_exu_b & ~tof_b & ~misalign_b & ~ect_mbist_sel) |
				  (fgu_valid_b  &                                                          ~ect_mbist_sel) |
				   mbi_irf_write_en_p1;


// *** Tid ***

	assign ect_tid_in_b[1:0]= ({2{~ect_mbist_sel &  fgu_exu_w_vld_fx5}} & fgu_result_tid_fx5[1:0]) |
				  ({2{~ect_mbist_sel & ~fgu_exu_w_vld_fx5}} & tid_lth_b[1:0]         ) |
				  ({2{ ect_mbist_sel                     }} & mbi_addr_p1[6:5]       );

// *** RD ***
	assign rd_in_d[4:0]	= ({5{~two_cycle_e_in}} & dec_inst_rd_d[4:0]) |
				  ({5{ two_cycle_e_in}} & inst_rs3_d[4:0]   );

	assign rd_in_m[4:0]	= rd_lth_m[4:0];

	assign ect_rd_in_b[4:0]	= ({5{~ect_mbist_sel &  fgu_valid_b}} & fgu_irf_w_addr_fx5[4:0]) |
				  ({5{~ect_mbist_sel & ~fgu_valid_b}} & rd_lth_b[4:0]          ) |
				  ({5{ ect_mbist_sel               }} & mbi_addr_p1[4:0]       );


	assign rs1_valid_d	=  (ect_rs1_late_sel_d[3:1] == 3'b000 ) &  rs1_rd_en_d & ~two_cycle_e_in;
	assign rs2_valid_d	=  (ect_rs2_late_sel_d[3:0] == 4'b0000) &  rs2_rd_en_d & ~two_cycle_e_in;
	assign rs3_valid_d	=  (ect_rs3_late_sel_d[3:1] == 3'b000 ) &  rs3_rd_en_d;

exu_ect_ctl_msff_ctl_macro__width_6 ren_lth		 (
 .scan_in(ren_lth_scanin),
 .scan_out(ren_lth_scanout),
 .l1clk( l1clk_pm1						       ),
 .din  ({dec_inst_rs1_vld_p , dec_inst_rs2_vld_p , dec_inst_rs3_vld_p ,
	     rs1_valid_d    ,     rs2_valid_d    ,     rs3_valid_d    }),
 .dout ({rs1_rd_en_d        , rs2_rd_en_d        , rs3_rd_en_d        ,
	 ect_rs1_valid_e    , ect_rs2_valid_e    , ect_rs3_valid_e    }),
  .siclk(siclk),
  .soclk(soclk));


exu_ect_ctl_msff_ctl_macro__width_15	rs_lth			 (
 .scan_in(rs_lth_scanin),
 .scan_out(rs_lth_scanout),
 .l1clk( l1clk_pm1								),
 .din  ({dec_inst_rs1_p[4:0] , dec_inst_rs2_p[4:0] , dec_inst_rs3_p[4:0]}	),
 .dout ({    inst_rs1_d[4:0] ,     inst_rs2_d[4:0] ,     inst_rs3_d[4:0]}	),
  .siclk(siclk),
  .soclk(soclk));


exu_ect_ctl_msff_ctl_macro__width_76	i_byp_lth		 (
 .scan_in(i_byp_lth_scanin),
 .scan_out(i_byp_lth_scanout),
 .l1clk( l1clk_pm1									),
 .din  ({                	  dec_tid_p[1:0]		,
              valid_in_d	,     tid_lth_d[1:0]		,     rd_in_d[4:0]	, inst_rs1_d[4:0]	, inst_rs2_d[4:0]     ,
              valid_in_e	, ect_tid_lth_e[1:0]		,     rd_lth_e[4:0]	, movcc_true_e		,
              valid_in_m	,     tid_lth_m[1:0]		,     rd_in_m[4:0]	,
              valid_in_b	, ect_tid_in_b[1:0]		, ect_rd_in_b[4:0]	,
          ect_valid_lth_w	, ect_tid_lth_w[1:0]		, ect_rd_lth_w[4:0]	,
                                  lsu_exu_tid_m[1:0]		, lsu_exu_rd_m[4:0]	, 
                                  lsu_exu_tid_b[1:0]		, lsu_exu_rd_b[4:0]	, lsu_exu_ld_b		,
          ect_valid_in_w2	, ect_tid_lth_w2[1:0]		, ect_rd_lth_w2[4:0]	}),
 .dout ({                     	      tid_lth_d[1:0]		,
              valid_lth_e	, ect_tid_lth_e[1:0]		,     rd_lth_e[4:0]	, ect_rs1_addr_e[4:0]	, ect_rs2_addr_e[4:0] ,
              valid_lth_m	,     tid_lth_m[1:0]		,     rd_lth_m[4:0]	, exu_cmov_true_m	,
              valid_lth_b	,     tid_lth_b[1:0]		,     rd_lth_b[4:0]	,
          ect_valid_lth_w	, ect_tid_lth_w[1:0]		, ect_rd_lth_w[4:0]	,
              valid_lth_w_plus1	,     tid_lth_w_plus1[1:0]	,     rd_lth_w_plus1[4:0],
                                  lsu_exu_tid_b[1:0]		, lsu_exu_rd_b[4:0]	, 
                                  ect_tid_lth_w2[1:0]		, ect_rd_lth_w2[4:0]	, lsu_exu_ld_w		,
              valid_lth_w2_plus1,     tid_lth_w2_plus1[1:0]	,     rd_lth_w2_plus1[4:0]}),
  .siclk(siclk),
  .soclk(soclk));


	assign ect_rs3_addr_e[4:0] = rd_lth_e[4:0];


// M, B, W, and W2 priority built into the PGPE mux in the datapath

	//                                   ZN         RS1 zero            RS1 negative
	assign movcc_true_e	= (dec_cmov_z00_e & ~edp_br_flag_e[0] & ~edp_br_flag_e[1]) |
				  (dec_cmov_z01_e & ~edp_br_flag_e[0] &  edp_br_flag_e[1]) |
				  (dec_cmov_z10_e &  edp_br_flag_e[0] & ~edp_br_flag_e[1]);

	assign valid_out_e	=      valid_lth_e & dec_valid_e & ~(mov_cond_e & ~movcc_true_e) & ~tas_tv_overflow_e & ~misalign_error_e;
	assign raw_valid_out_e	=      valid_lth_e & dec_valid_e & ~(mov_cond_e & ~movcc_true_e);

	assign rs1_e_cmp	=  raw_valid_out_e        & (ect_tid_lth_e[1:0]        == tid_lth_d[1:0]) & (rd_lth_e[4:0]        == inst_rs1_d[4:0]);
	assign rs1_m_cmp	=      valid_lth_m        & (    tid_lth_m[1:0]        == tid_lth_d[1:0]) & (rd_lth_m[4:0]        == inst_rs1_d[4:0]);
	assign rs1_b_cmp	=      valid_lth_b        & (    tid_lth_b[1:0]        == tid_lth_d[1:0]) & (rd_lth_b[4:0]        == inst_rs1_d[4:0]);
	assign rs1_w_cmp	=  ect_valid_lth_w        & (ect_tid_lth_w[1:0]        == tid_lth_d[1:0]) & (ect_rd_lth_w[4:0]    == inst_rs1_d[4:0]);
	assign rs1_w2_cmp	=  lsu_valid_w2           & (ect_tid_lth_w2[1:0]       == tid_lth_d[1:0]) & (ect_rd_lth_w2[4:0]   == inst_rs1_d[4:0]);
	assign rs1_w_plus1_cmp	=      valid_lth_w_plus1  & (    tid_lth_w_plus1[1:0]  == tid_lth_d[1:0]) & (rd_lth_w_plus1[4:0]  == inst_rs1_d[4:0]);
	assign rs1_w2_plus1_cmp	=      valid_lth_w2_plus1 & (    tid_lth_w2_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w2_plus1[4:0] == inst_rs1_d[4:0]);
				   	      	       					 
	assign rs2_e_cmp	=  raw_valid_out_e        & (ect_tid_lth_e[1:0]        == tid_lth_d[1:0]) & (rd_lth_e[4:0]        == inst_rs2_d[4:0]);
	assign rs2_m_cmp	=      valid_lth_m        & (    tid_lth_m[1:0]        == tid_lth_d[1:0]) & (rd_lth_m[4:0]        == inst_rs2_d[4:0]);
	assign rs2_b_cmp	=      valid_lth_b        & (    tid_lth_b[1:0]        == tid_lth_d[1:0]) & (rd_lth_b[4:0]        == inst_rs2_d[4:0]);
	assign rs2_w_cmp	=  ect_valid_lth_w        & (ect_tid_lth_w[1:0]        == tid_lth_d[1:0]) & (ect_rd_lth_w[4:0]    == inst_rs2_d[4:0]);
	assign rs2_w2_cmp	=  lsu_valid_w2           & (ect_tid_lth_w2[1:0]       == tid_lth_d[1:0]) & (ect_rd_lth_w2[4:0]   == inst_rs2_d[4:0]);
	assign rs2_w_plus1_cmp	=      valid_lth_w_plus1  & (    tid_lth_w_plus1[1:0]  == tid_lth_d[1:0]) & (rd_lth_w_plus1[4:0]  == inst_rs2_d[4:0]);
	assign rs2_w2_plus1_cmp	=      valid_lth_w2_plus1 & (    tid_lth_w2_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w2_plus1[4:0] == inst_rs2_d[4:0]);
				   	      	       					 
	assign rs3_e_cmp	=  raw_valid_out_e        & (ect_tid_lth_e[1:0]        == tid_lth_d[1:0]) & (rd_lth_e[4:0]        == inst_rs3_d[4:0]);
	assign rs3_m_cmp	=      valid_lth_m        & (    tid_lth_m[1:0]        == tid_lth_d[1:0]) & (rd_lth_m[4:0]        == inst_rs3_d[4:0]);
	assign rs3_b_cmp	=      valid_lth_b        & (    tid_lth_b[1:0]        == tid_lth_d[1:0]) & (rd_lth_b[4:0]        == inst_rs3_d[4:0]);
	assign rs3_w_cmp	=  ect_valid_lth_w        & (ect_tid_lth_w[1:0]        == tid_lth_d[1:0]) & (ect_rd_lth_w[4:0]    == inst_rs3_d[4:0]);
	assign rs3_w2_cmp	=  lsu_valid_w2           & (ect_tid_lth_w2[1:0]       == tid_lth_d[1:0]) & (ect_rd_lth_w2[4:0]   == inst_rs3_d[4:0]);
	assign rs3_w_plus1_cmp	=      valid_lth_w_plus1  & (    tid_lth_w_plus1[1:0]  == tid_lth_d[1:0]) & (rd_lth_w_plus1[4:0]  == inst_rs3_d[4:0]);
	assign rs3_w2_plus1_cmp	=      valid_lth_w2_plus1 & (    tid_lth_w2_plus1[1:0] == tid_lth_d[1:0]) & (rd_lth_w2_plus1[4:0] == inst_rs3_d[4:0]);
				   
			
	assign rs1_l_cmp	=   lsu_exu_ld_b                                             &
				   (lsu_exu_tid_b[2:0] == {dec_thread_group,tid_lth_d[1:0]}) &
				   (lsu_exu_rd_b[4:0]  == inst_rs1_d[4:0]                  ) &
				  ~(lsu_exu_rd_b[4:0]  == 5'b00000                         );
						       
	assign rs2_l_cmp	=   lsu_exu_ld_b                                             &
				   (lsu_exu_tid_b[2:0] == {dec_thread_group,tid_lth_d[1:0]}) &
				   (lsu_exu_rd_b[4:0]  == inst_rs2_d[4:0]                  ) &
				  ~(lsu_exu_rd_b[4:0]  == 5'b00000                         );
						       
	assign rs3_l_cmp	=   lsu_exu_ld_b                                             &
				   (lsu_exu_tid_b[2:0] == {dec_thread_group,tid_lth_d[1:0]}) &
				   (lsu_exu_rd_b[4:0]  == inst_rs3_d[4:0]                  ) &
				  ~(lsu_exu_rd_b[4:0]  == 5'b00000                         );

	assign rs1_byp_early	= rs1_m_cmp | rs1_b_cmp | rs1_w_cmp | rs1_w2_cmp | rs1_w_plus1_cmp | rs1_w2_plus1_cmp;
	assign rs2_byp_early	= rs2_m_cmp | rs2_b_cmp | rs2_w_cmp | rs2_w2_cmp | rs2_w_plus1_cmp | rs2_w2_plus1_cmp;
	assign rs3_byp_early	= rs3_m_cmp | rs3_b_cmp | rs3_w_cmp | rs3_w2_cmp | rs3_w_plus1_cmp | rs3_w2_plus1_cmp;


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Bypass       !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Flags        !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


// *** E Stage Flag generation ***

	assign lg_cc[7]		=   edp_logical_data_e_b63;							// N
	assign lg_cc[6]		=   edp_lg_zdetect_e[1]    &  edp_lg_zdetect_e[0];				// Z : [63:0] == 0
	assign lg_cc[5]		=  1'b0;									// V : always 0
	assign lg_cc[4]		=  1'b0;									// C : always 0

	assign lg_cc[3]		=   edp_logical_data_e_b31;							// N
	assign lg_cc[2]		=                             edp_lg_zdetect_e[0];				// Z : [31:0] == 0
	assign lg_cc[1]		=  1'b0;									// V : always 0
	assign lg_cc[0]		=  1'b0;									// C : always 0


	assign as_cc[7]		= (    ~as_subtract_e &                                                  edp_add_data_e_b63   ) |	// N
				  (     as_subtract_e &                                                  edp_sub_data_e_b63   );
	assign as_cc[6]		= (    ~as_subtract_e &                        ~edp_add_zdetect_e_[1] & ~edp_add_zdetect_e_[0]) |	// Z : [63:0] == 0
				  (     as_subtract_e &                        ~edp_sub_zdetect_e_[1] & ~edp_sub_zdetect_e_[0]);
	assign as_cc[5]		= (    ~as_subtract_e &  ~exu_rs1_data_e[63] & ~exu_rs2_data_e[63]    &  edp_add_data_e_b63   ) |	// V
				  (    ~as_subtract_e &   exu_rs1_data_e[63] &  exu_rs2_data_e[63]    & ~edp_add_data_e_b63   ) |
				  (     as_subtract_e &  ~exu_rs1_data_e[63] &  exu_rs2_data_e[63]    &  edp_sub_data_e_b63   ) |
				  (     as_subtract_e &   exu_rs1_data_e[63] & ~exu_rs2_data_e[63]    & ~edp_sub_data_e_b63   );
	assign as_cc[4]		= (    ~as_subtract_e &                                                  edp_add_cout64_e     ) |	// C
				  (     as_subtract_e &                                                 ~edp_sub_cout64_e     );

	assign as_cc[3]		= (    ~as_subtract_e &                                                  edp_add_data_e_b31   ) |	// N
				  (     as_subtract_e &                                                  edp_sub_data_e_b31   );
	assign as_cc[2]		= (    ~as_subtract_e &                                                 ~edp_add_zdetect_e_[0]) |	// Z : [31:0] == 0
				  (     as_subtract_e &                                                 ~edp_sub_zdetect_e_[0]);
	assign as_cc[1]		= (    ~as_subtract_e &  ~exu_rs1_data_e[31] & ~exu_rs2_data_e[31]    &  edp_add_data_e_b31   ) |	// V
				  (    ~as_subtract_e &   exu_rs1_data_e[31] &  exu_rs2_data_e[31]    & ~edp_add_data_e_b31   ) |
				  (     as_subtract_e &  ~exu_rs1_data_e[31] &  exu_rs2_data_e[31]    &  edp_sub_data_e_b31   ) |
				  (     as_subtract_e &   exu_rs1_data_e[31] & ~exu_rs2_data_e[31]    & ~edp_sub_data_e_b31   ) |
				  (     tas_cc_e      & ( exu_rs1_data_e[0] |  exu_rs2_data_e[0])                           ) |
				  (     tas_cc_e      & ( exu_rs1_data_e[1] |  exu_rs2_data_e[1])                           );
        assign as_cc[0]		= (    ~as_subtract_e & ( exu_rs1_data_e[31] &  exu_rs2_data_e[31])                           ) |	// C
				  (    ~as_subtract_e & ( exu_rs1_data_e[31] |  exu_rs2_data_e[31])   & ~edp_add_data_e_b31   ) |
				  (     as_subtract_e & (~exu_rs1_data_e[31] &  exu_rs2_data_e[31])                          ) |
				  (     as_subtract_e & (~exu_rs1_data_e[31] |  exu_rs2_data_e[31])   &  edp_sub_data_e_b31   );


	assign ccr_data_e[7:0]	= ({8{as_cc_e  }} & as_cc[7:0]  ) |
				  ({8{lg_cc_e  }} & lg_cc[7:0]  );


	assign ccr_data_b[7:0]	= ({8{~fgu_ccr_valid_b}} & ccr_data_lth_b[7:0]                              ) |
				  ({8{ fgu_ccr_valid_b}} & {fgu_exu_xcc_fx5[1:0],2'b00,fgu_exu_icc_fx5[3:0]});

	assign fgu_ccr_valid_b	=  fgu_exu_cc_vld_fx5  & fgu_exu_w_vld_fx5;

	assign ccr_valid_in_d	= (as_cc_d | lg_cc_d);
	assign ccr_valid_in_e	=  ccr_valid_out_e;
	assign ccr_valid_in_m	=  ccr_valid_lth_m & ~dec_flush_m & ~exu_ecc_m       & ~address_error_m;
	assign ccr_valid_in_b	= (ccr_valid_lth_b & ~dec_flush_b & ~tlu_flush_exu_b & ~tof_b & ~misalign_b) | fgu_ccr_valid_b;


	assign wr_ccr_w_tid0		=  ccr_valid_lth_w    & (ect_tid_lth_w[1:0]   == 2'b00);
	assign wr_ccr_w_tid1		=  ccr_valid_lth_w    & (ect_tid_lth_w[1:0]   == 2'b01);
	assign wr_ccr_w_tid2		=  ccr_valid_lth_w    & (ect_tid_lth_w[1:0]   == 2'b10);
	assign wr_ccr_w_tid3		=  ccr_valid_lth_w    & (ect_tid_lth_w[1:0]   == 2'b11);

	assign wr_ccr_tlu0		=  tlu_ccr_cwp_valid  & (tlu_ccr_cwp_tid[1:0] == 2'b00);
	assign wr_ccr_tlu1		=  tlu_ccr_cwp_valid  & (tlu_ccr_cwp_tid[1:0] == 2'b01);
	assign wr_ccr_tlu2		=  tlu_ccr_cwp_valid  & (tlu_ccr_cwp_tid[1:0] == 2'b10);
	assign wr_ccr_tlu3		=  tlu_ccr_cwp_valid  & (tlu_ccr_cwp_tid[1:0] == 2'b11);

	assign wr_ccr_asi0		=  rml_rng_wt_ccr_ctl & (rng_tid[1:0]         == 2'b00);
	assign wr_ccr_asi1		=  rml_rng_wt_ccr_ctl & (rng_tid[1:0]         == 2'b01);
	assign wr_ccr_asi2		=  rml_rng_wt_ccr_ctl & (rng_tid[1:0]         == 2'b10);
	assign wr_ccr_asi3		=  rml_rng_wt_ccr_ctl & (rng_tid[1:0]         == 2'b11);


	assign arch_ccr_tid0_in[7:0]	= ({8{ wr_ccr_w_tid0                              }} & ccr_data_lth_w[7:0]   ) |
					  ({8{                  wr_ccr_tlu0               }} & tlu_ccr[7:0]          ) |
					  ({8{                                 wr_ccr_asi0}} & edp_rng_in_ff[7:0]    ) |
					  ({8{~wr_ccr_w_tid0 & ~wr_ccr_tlu0 & ~wr_ccr_asi0}} & arch_ccr_tid0_lth[7:0]);


	assign arch_ccr_tid1_in[7:0]	= ({8{ wr_ccr_w_tid1                              }} & ccr_data_lth_w[7:0]   ) |
					  ({8{                  wr_ccr_tlu1               }} & tlu_ccr[7:0]          ) |
					  ({8{                                 wr_ccr_asi1}} & edp_rng_in_ff[7:0]    ) |
					  ({8{~wr_ccr_w_tid1 & ~wr_ccr_tlu1 & ~wr_ccr_asi1}} & arch_ccr_tid1_lth[7:0]);


	assign arch_ccr_tid2_in[7:0]	= ({8{ wr_ccr_w_tid2                              }} & ccr_data_lth_w[7:0]   ) |
					  ({8{                  wr_ccr_tlu2               }} & tlu_ccr[7:0]          ) |
					  ({8{                                 wr_ccr_asi2}} & edp_rng_in_ff[7:0]    ) |
					  ({8{~wr_ccr_w_tid2 & ~wr_ccr_tlu2 & ~wr_ccr_asi2}} & arch_ccr_tid2_lth[7:0]);


	assign arch_ccr_tid3_in[7:0]	= ({8{ wr_ccr_w_tid3                              }} & ccr_data_lth_w[7:0]   ) |
					  ({8{                  wr_ccr_tlu3               }} & tlu_ccr[7:0]          ) |
					  ({8{                                 wr_ccr_asi3}} & edp_rng_in_ff[7:0]    ) |
					  ({8{~wr_ccr_w_tid3 & ~wr_ccr_tlu3 & ~wr_ccr_asi3}} & arch_ccr_tid3_lth[7:0]);


exu_ect_ctl_msff_ctl_macro__width_28	i_ccr_pipe_lth		 (
 .scan_in(i_ccr_pipe_lth_scanin),
 .scan_out(i_ccr_pipe_lth_scanout),
 .l1clk( l1clk_pm1					),
 .din  ({ ccr_valid_in_d   ,
          ccr_valid_in_e   ,     ccr_data_e[7:0]	,
          ccr_valid_in_m   ,     ccr_data_lth_m[7:0]	,
          ccr_valid_in_b   ,     ccr_data_b[7:0]	}),
 .dout ({ ccr_valid_lth_e  ,
          ccr_valid_lth_m  ,     ccr_data_lth_m[7:0]	,
          ccr_valid_lth_b  ,     ccr_data_lth_b[7:0]	,
          ccr_valid_lth_w  ,     ccr_data_lth_w[7:0]	}),
  .siclk(siclk),
  .soclk(soclk));


exu_ect_ctl_msff_ctl_macro__width_32	i_ccr_arch_lth		 (		// FS:wmr_protect
 .scan_in(i_ccr_arch_lth_wmr_scanin),
 .scan_out(i_ccr_arch_lth_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk_pm1											 ),
 .din  ({arch_ccr_tid0_in[7:0] , arch_ccr_tid1_in[7:0] , arch_ccr_tid2_in[7:0] , arch_ccr_tid3_in[7:0]	}),
 .dout ({arch_ccr_tid0_lth[7:0], arch_ccr_tid1_lth[7:0], arch_ccr_tid2_lth[7:0], arch_ccr_tid3_lth[7:0]	}),
  .soclk(soclk));


	assign ccr_valid_out_e		= ccr_valid_lth_e & dec_valid_e & ~tas_tv_overflow_e;

	assign ccr_e_cmp		= ccr_valid_lth_e & (tid_lth_d[1:0] == ect_tid_lth_e[1:0]);
	assign ccr_m_cmp		= ccr_valid_lth_m & (tid_lth_d[1:0] ==     tid_lth_m[1:0]);
	assign ccr_b_cmp		= ccr_valid_lth_b & (tid_lth_d[1:0] ==     tid_lth_b[1:0]);
	assign ccr_w_cmp		= ccr_valid_lth_w & (tid_lth_d[1:0] == ect_tid_lth_w[1:0]);

	assign ccr_sel_e		=  ccr_e_cmp;
	assign ccr_sel_m		=               ccr_m_cmp;
	assign ccr_sel_b		=              ~ccr_m_cmp &  ccr_b_cmp;
	assign ccr_sel_w		=              ~ccr_m_cmp & ~ccr_b_cmp &  ccr_w_cmp;
	assign ccr_sel_a0		=              ~ccr_m_cmp & ~ccr_b_cmp & ~ccr_w_cmp & (tid_lth_d[1:0] == 2'b00);
	assign ccr_sel_a1		=              ~ccr_m_cmp & ~ccr_b_cmp & ~ccr_w_cmp & (tid_lth_d[1:0] == 2'b01);
	assign ccr_sel_a2		=              ~ccr_m_cmp & ~ccr_b_cmp & ~ccr_w_cmp & (tid_lth_d[1:0] == 2'b10);
	assign ccr_sel_a3		=              ~ccr_m_cmp & ~ccr_b_cmp & ~ccr_w_cmp & (tid_lth_d[1:0] == 2'b11);

	assign exu_ccr_byp_data0[7:0]	= ({8{             ccr_sel_m }} & ccr_data_lth_m[7:0]   ) |
					  ({8{             ccr_sel_b }} & ccr_data_lth_b[7:0]   ) |
					  ({8{             ccr_sel_w }} & ccr_data_lth_w[7:0]   ) |
					  ({8{             ccr_sel_a0}} & arch_ccr_tid0_lth[7:0]) |
					  ({8{             ccr_sel_a1}} & arch_ccr_tid1_lth[7:0]) |
					  ({8{             ccr_sel_a2}} & arch_ccr_tid2_lth[7:0]) |
					  ({8{             ccr_sel_a3}} & arch_ccr_tid3_lth[7:0]);

	assign exu_ccr_byp_data1[7:0]	= ({8{ ccr_sel_e             }} & ccr_data_e[7:0]       ) |
					  ({8{~ccr_sel_e & ccr_sel_m }} & ccr_data_lth_m[7:0]   ) |
					  ({8{~ccr_sel_e & ccr_sel_b }} & ccr_data_lth_b[7:0]   ) |
					  ({8{~ccr_sel_e & ccr_sel_w }} & ccr_data_lth_w[7:0]   ) |
					  ({8{~ccr_sel_e & ccr_sel_a0}} & arch_ccr_tid0_lth[7:0]) |
					  ({8{~ccr_sel_e & ccr_sel_a1}} & arch_ccr_tid1_lth[7:0]) |
					  ({8{~ccr_sel_e & ccr_sel_a2}} & arch_ccr_tid2_lth[7:0]) |
					  ({8{~ccr_sel_e & ccr_sel_a3}} & arch_ccr_tid3_lth[7:0]);

	assign     ccr_byp_data_b0	= (  {~dec_valid_e}  & exu_ccr_byp_data0[0]) |
					  (  { dec_valid_e}  & exu_ccr_byp_data1[0]);

	assign     ccr_byp_data_b1	= (  {~dec_valid_e}  & exu_ccr_byp_data0[1]) |
					  (  { dec_valid_e}  & exu_ccr_byp_data1[1]);

	assign     ccr_byp_data_b3	= (  {~dec_valid_e}  & exu_ccr_byp_data0[3]) |
					  (  { dec_valid_e}  & exu_ccr_byp_data1[3]);


	assign exu_ccr0[7:0] =  arch_ccr_tid0_lth[7:0];
	assign exu_ccr1[7:0] =	arch_ccr_tid1_lth[7:0];
	assign exu_ccr2[7:0] =	arch_ccr_tid2_lth[7:0];
	assign exu_ccr3[7:0] =	arch_ccr_tid3_lth[7:0];

	assign ect_rng_ccr_data[7:0]	= ({8{rng_tid[1:0] == 2'b00}} & arch_ccr_tid0_lth[7:0]) |
					  ({8{rng_tid[1:0] == 2'b01}} & arch_ccr_tid1_lth[7:0]) |
					  ({8{rng_tid[1:0] == 2'b10}} & arch_ccr_tid2_lth[7:0]) |
					  ({8{rng_tid[1:0] == 2'b11}} & arch_ccr_tid3_lth[7:0]);


	assign trap_taken_e		=  dec_valid_e & tcc_e & tcc_taken_e;

	assign exu_tcc_m		=  trap_taken_m_lth;


// pg. 199 Multiply Step -> CCR.icc.n XOR CCR.icc.v

	assign ms_icc_in		= ccr_byp_data_b3 ^ ccr_byp_data_b1;

	assign tas_tv_overflow_e	= (dec_valid_e & tas_tv_e & as_cc[1]);		// Tagged Add TV with overflow
	assign tas_tv_overflow_m_in	=  tas_tv_overflow_m_lth & ~dec_flush_m;
	assign exu_tof_m		=  tas_tv_overflow_m_lth;


	assign normal_va_hole_m_	=   edp_address_m[63:48] == {16{edp_address_m[47]}};
	assign special_ls_va_hole_m_	=   edp_rd_ff_m[63:48]   == {16{edp_rd_ff_m[47]}};
	assign special_br_va_hole_m_	= ((edp_address_m[63:48] == 16'h0001) & ~edp_address_m[47]) |
					  ((edp_address_m[63:48] == 16'h0000) &  edp_address_m[47]);

	assign va_hole_m		= ( ls_special_sel_m                     & ~special_ls_va_hole_m_) |
					  (                     br_special_sel_m & ~special_br_va_hole_m_) |
					  (~ls_special_sel_m & ~br_special_sel_m & ~normal_va_hole_m_    );

	assign exu_lsu_va_error_m	= (va_hole_m & address_m & ~pstate_am_m                 );
	assign exu_oor_va_m		= (va_hole_m & address_m                                );
	assign address_error_m		= (va_hole_m & address_m & ~pstate_am_m & ~itlb_bypass_m);


	assign misalign_error_e		=  misalign_e  & dec_valid_e & (edp_add_data_e_b1 | edp_add_data_e_b0);

	assign misalign_error_m_in	=  ect_misaligned_error_m    & ~dec_flush_m;
	assign exu_misalign_m	 	=  ect_misaligned_error_m;

	assign pstate_am_d		= (tlu_pstate_am[0] & (tid_lth_d[1:0] == 2'b00)) |
					  (tlu_pstate_am[1] & (tid_lth_d[1:0] == 2'b01)) |
					  (tlu_pstate_am[2] & (tid_lth_d[1:0] == 2'b10)) |
					  (tlu_pstate_am[3] & (tid_lth_d[1:0] == 2'b11));


exu_ect_ctl_msff_ctl_macro__width_9	i_tlu_lth			 (
 .scan_in(i_tlu_lth_scanin),
 .scan_out(i_tlu_lth_scanout),
 .l1clk( l1clk_pm2		),
 .din  ({trap_taken_e		,
	 ms_icc_in		,
	 tas_tv_overflow_e	,
	 tas_tv_overflow_m_in	,
	 misalign_error_e	,
	 misalign_error_m_in	,
	 pstate_am_d		,
	 ect_pstate_am_e	,
	 tlu_itlb_bypass_e	}),
 .dout ({trap_taken_m_lth	,
	 exu_ms_icc_e		,
	 tas_tv_overflow_m_lth	,
	 tof_b			,
	 ect_misaligned_error_m	,
	 misalign_b		,
	 ect_pstate_am_e	,
	 pstate_am_m		,
	 itlb_bypass_m		}),
  .siclk(siclk),
  .soclk(soclk));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Flags        !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Y Register   !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!

	assign yreg_mwr_valid_em3_in	=  dec_valid_e            & (exu_mdp_mux_sel_e[0] | exu_mdp_mux_sel_e[1]);	// UMUL(cc), SMUL(cc)
	assign yreg_mwr_valid_em2_in	=  yreg_mwr_valid_em2_lth & ~dec_flush_m & ~exu_ecc_m;
	assign yreg_mwr_valid_em1_in	=  yreg_mwr_valid_em1_lth & ~dec_flush_b & ~tlu_flush_exu_b;
	assign yreg_mwr_valid_e_in	=  yreg_mwr_valid_e_lth;
	assign yreg_mwr_valid_m_in	=  yreg_mwr_valid_m_lth;

	assign yreg_swr_valid_e_in	=  dec_valid_e            &  exu_mdp_mux_sel_e[3];				// MULScc
	assign yreg_swr_valid_m_in	=  yreg_swr_valid_m_lth   & ~dec_flush_m & ~exu_ecc_m;

	assign yreg_wr_valid_b_in	=  yreg_mwr_valid_b_lth |
					  (yreg_swr_valid_b_lth   & ~dec_flush_b & ~tlu_flush_exu_b);


exu_ect_ctl_msff_ctl_macro__width_5	i_yreg_mpipe_lth	 (
 .scan_in(i_yreg_mpipe_lth_scanin),
 .scan_out(i_yreg_mpipe_lth_scanout),
 .l1clk( l1clk_pm1														),
 .din  ({yreg_mwr_valid_em3_in  , yreg_mwr_valid_em2_in  , yreg_mwr_valid_em1_in  , yreg_mwr_valid_e_in  , yreg_mwr_valid_m_in }),
 .dout ({yreg_mwr_valid_em2_lth , yreg_mwr_valid_em1_lth , yreg_mwr_valid_e_lth   , yreg_mwr_valid_m_lth , yreg_mwr_valid_b_lth}),
  .siclk(siclk),
  .soclk(soclk));

exu_ect_ctl_msff_ctl_macro__width_5	i_yreg_spipe_lth	 (
 .scan_in(i_yreg_spipe_lth_scanin),
 .scan_out(i_yreg_spipe_lth_scanout),
 .l1clk( l1clk_pm1													),
 .din  ({yreg_swr_valid_e_in  , yreg_swr_valid_m_in  , yreg_wr_valid_b_in , edp_rng_in_ff_b57,edp_rng_in_ff_b56}	),
 .dout ({yreg_swr_valid_m_lth , yreg_swr_valid_b_lth , ect_yreg_wr_w      , rng_tid[1:0]}				),
  .siclk(siclk),
  .soclk(soclk));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Y Register   !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Edge         !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!

//				   Edge Mask Specification
//
//                                        Big-endian                 Little-endian                    
//                                                                                     
//      Edge Size    A2..A0        Left Edge   Right Edge        Left Edge   Right Edge
//      ---------    ------        ---------   ----------        ---------   ----------
//          8          000         1111_1111    1000_0000        1111_1111    0000_0001
//          8          001         0111_1111    1100_0000        1111_1110    0000_0011
//          8          010         0011_1111    1110_0000        1111_1100    0000_0111
//          8          011         0001_1111    1111_0000        1111_1000    0000_1111
//          8          100         0000_1111    1111_1000        1111_0000    0001_1111
//          8          101         0000_0111    1111_1100        1110_0000    0011_1111
//          8          110         0000_0011    1111_1110        1100_0000    0111_1111
//          8          111         0000_0001    1111_1111        1000_0000    1111_1111
//                                                                                     
//         16          00x              1111         1000             1111         0001
//         16          01x              0111         1100             1110         0011
//         16          10x              0011         1110             1100         0111
//         16          11x              0001         1111             1000         1111
//                                                                                     
//         32          0xx                11           10               11           01
//         32          1xx                01           11               10           11


// 				   Algorithm
//
// 1. The left  edge is computed from the 3 least significant bits of RS1 and
//    the right edge is computed from the 3 least significant bits of RS2.
//
// 2. If 32-bit address masking is disabled (PSTATE.AM == 0, 64-bit addressing) and
//    the (RS1[63:3] == RS2[63:3]), then RD = right edge mask ANDed with the left edge mask.
//
//				   OR
//
//    If 32-bit address masking is  enabled (PSTATE.AM == 1, 32-bit addressing) and
//    the (RS1[31:3] == RS2[31:3]), then RD = right edge mask ANDed with the left edge mask.
//
// 3. Otherwise, RD = left edge mask.


// Format :
//
//  31:30   29:25   24:19    18:14   13:05   04:00
//  -----   -----   ------   -----   -----   -----
//    10      rd    110110    rs1     opf     rs2
//
//
// OPCODE         opf        comment
// --------   -----------    ----------------------------
// edge8      0 0000 0000
// edge8N     0 0000 0001    no icc,xcc update;
// edge8L     0 0000 0010			Little-Endian
// edge8LN    0 0000 0011    no icc,xcc update;	Little-Endian
// edge16     0 0000 0100
// edge16N    0 0000 0101    no icc,xcc update;
// edge16L    0 0000 0110			Little-Endian
// edge16LN   0 0000 0111    no icc,xcc update;	Little-Endian
// edge32     0 0000 1000
// edge32N    0 0000 1001    no icc,xcc update;
// edge32L    0 0000 1010			Little-Endian
// edge32LN   0 0000 1011    no icc,xcc update;	Little-Endian


	// E0: XOR rs1 rs2 for eq det. Also take pstate_am into account
//	assign zdet_in_e[63:32]	= {32{~ect_pstate_am_e}} & (exu_rs1_data_e[63:32] ^ exu_rs2_data_e[63:32]);
//	assign zdet_in_e[31:3]	=                           exu_rs1_data_e[31:3]  ^ exu_rs2_data_e[31:3];

//	assign neq_zdet_e	= | zdet_in_e[63:3];
//	assign neq_zdet_e	= ~(( edp_rs1_x_rs2_cmp_e[1] &  edp_rs1_x_rs2_cmp_e[0]) |
//				    ( ect_pstate_am_e        &  edp_rs1_x_rs2_cmp_e[0]));


// *** Generate left mask ***
											// EDGE8                             EDGE16             EDGE32
	assign lmask_e[7]	=  edge08_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[1] & ~exu_rs1_data_e[0] ;	// 000

	assign lmask_e[6]	=  edge08_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[1]                      ;	// 000 001

	assign lmask_e[5]	= (edge08_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[1]                     ) |	// 000 001
				  (edge08_e & ~exu_rs1_data_e[2] &                      ~exu_rs1_data_e[0]);	//         010

	assign lmask_e[4]	=  edge08_e & ~exu_rs1_data_e[2]                                           ;	// 000 001 010 011

	assign lmask_e[3]	= (edge08_e & ~exu_rs1_data_e[2]                                          ) |	// 000 001 010 011
				  (edge08_e &                      ~exu_rs1_data_e[1] & ~exu_rs1_data_e[0]) |	//                 100
				  (edge16_e & ~exu_rs1_data_e[2] & ~exu_rs1_data_e[1]                     );	//                                   00x

	assign lmask_e[2]	= (edge08_e & ~exu_rs1_data_e[2]                                          ) |	// 000 001 010 011
				  (edge08_e &                      ~exu_rs1_data_e[1]                     ) |	//                 100 101
				  (edge16_e & ~exu_rs1_data_e[2]                                          );	//                                   00x 01x

	assign lmask_e[1]	= (edge08_e & ~exu_rs1_data_e[2]                                          ) |	// 000 001 010 011
				  (edge08_e &                      ~exu_rs1_data_e[1]                     ) |	//                 100 101
				  (edge08_e &                                           ~exu_rs1_data_e[0]) |	//                         110
				  (edge16_e & ~exu_rs1_data_e[2]                                          ) |	//                                   00x 01x
				  (edge16_e &                      ~exu_rs1_data_e[1]                     ) |	//                                           10x
				  (edge32_e & ~exu_rs1_data_e[2]                                          );	//                                                      0xx

	assign lmask_e[0]	= 1'b1;


// *** Generate right mask ***
											// EDGE8                             EDGE16             EDGE32
	assign rmask_e[7]	= 1'b1;

	assign rmask_e[6]	= (edge08_e &  exu_rs2_data_e[2]                                          ) |	//                 100 101 110 111
				  (edge08_e &                       exu_rs2_data_e[1]                     ) |	//         010 011
				  (edge08_e &                                            exu_rs2_data_e[0]);	//     001

	assign rmask_e[5]	= (edge08_e &  exu_rs2_data_e[2]                                          ) |	//                 100 101 110 111
				  (edge08_e &                       exu_rs2_data_e[1]                     );	//         010 011

	assign rmask_e[4]	= (edge08_e &  exu_rs2_data_e[2]                                          ) |	//                 100 101 110 111
				  (edge08_e &                       exu_rs2_data_e[1] &  exu_rs2_data_e[0]);	//             011

	assign rmask_e[3]	= (edge08_e &  exu_rs2_data_e[2]                                          ) |	//                 100 101 110 111
				   edge16_e                                                                ;	//                                   00x 01x 10x 11x

	assign rmask_e[2]	= (edge08_e &  exu_rs2_data_e[2] &  exu_rs2_data_e[1]                     ) |	//                         110 111
				  (edge08_e &  exu_rs2_data_e[2] &                       exu_rs2_data_e[0]) |	//                     101
				  (edge16_e &  exu_rs2_data_e[2]                                          ) |	//                                           10x 11x
				  (edge16_e &                       exu_rs2_data_e[1]                     );	//                                       01x

	assign rmask_e[1]	= (edge08_e &  exu_rs2_data_e[2] &  exu_rs2_data_e[1]                     ) |	//                         110 111
				  (edge16_e &  exu_rs2_data_e[2]                                          ) |	//                                           10x 11x
				   edge32_e                                                                ;	//                                                      0xx 1xx

	assign rmask_e[0]	= (edge08_e &  exu_rs2_data_e[2] &  exu_rs2_data_e[1] &  exu_rs2_data_e[0]) |	//                             111
				  (edge16_e &  exu_rs2_data_e[2] &  exu_rs2_data_e[1]                     ) |	//                                               11x
				  (edge32_e &  exu_rs2_data_e[2]                                          );	//                                                          1xx


	assign lrmask_e[7:0]	=  lmask_e[7:0] & rmask_e[7:0];

	assign lmask_le8[7:0]	= { lmask_e[0],  lmask_e[1],  lmask_e[2],  lmask_e[3],  lmask_e[4],  lmask_e[5],  lmask_e[6],  lmask_e[7]};
	assign lmask_le16[7:0]	= { 1'b0      ,  1'b0      ,  1'b0      ,  1'b0      ,  lmask_e[0],  lmask_e[1],  lmask_e[2],  lmask_e[3]};
	assign lmask_le32[7:0]	= { 1'b0      ,  1'b0      ,  1'b0      ,  1'b0      ,  1'b0      ,  1'b0      ,  lmask_e[0],  lmask_e[1]};

	assign lrmask_le8[7:0]	= {lrmask_e[0], lrmask_e[1], lrmask_e[2], lrmask_e[3], lrmask_e[4], lrmask_e[5], lrmask_e[6], lrmask_e[7]};
	assign lrmask_le16[7:0]	= { 1'b0      ,  1'b0      ,  1'b0      ,  1'b0      , lrmask_e[0], lrmask_e[1], lrmask_e[2], lrmask_e[3]};
	assign lrmask_le32[7:0]	= { 1'b0      ,  1'b0      ,  1'b0      ,  1'b0      ,  1'b0      ,  1'b0      , lrmask_e[0], lrmask_e[1]};


	assign ect_edge_lmask_e[7:0]  = ({8{~edgele_e           }} & lmask_e[7:0]    ) |
				        ({8{ edgele_e & edge08_e}} & lmask_le8[7:0]  ) |
				        ({8{ edgele_e & edge16_e}} & lmask_le16[7:0] ) |
				        ({8{ edgele_e & edge32_e}} & lmask_le32[7:0] );

	assign ect_edge_lrmask_e[7:0] = ({8{~edgele_e           }} & lrmask_e[7:0]   ) |
				        ({8{ edgele_e & edge08_e}} & lrmask_le8[7:0] ) |
				        ({8{ edgele_e & edge16_e}} & lrmask_le16[7:0]) |
				        ({8{ edgele_e & edge32_e}} & lrmask_le32[7:0]);


//	assign ect_edge_res_e[7:0]  = ({8{ neq_zdet_e}} & lmask_endian_e[7:0] ) |
//				      ({8{~neq_zdet_e}} & lrmask_endian_e[7:0]);


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Edge         !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!

 
//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : DEC_CCR_CTL  !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!

//  Description:        Condition code resolution logic
//


//------------------
// CC Logic for BCC
//------------------
// Choose appropriate CCs
//
// cctype is 3 bits
// 10X  icc
// 11X  xcc
// 000  fcc0
// 001  fcc1
// 010  fcc2
// 011  fcc3

assign cctype_d[2:0]	= ({3{imov_d}} & {i[18], i[12:11]}        ) |
			  ({3{fmov_d}} & {i[13] | tcc_d, i[12:11]}) |
			  ({3{bpcc_d}} & {~fp_d, i[21:20]}        ) |
			  ({3{bcc_d}}  & {~fp_d, 2'b00}           );

assign brcond_d[3:0]	= ({4{movcc_d}}     & i[17:14]       ) |
			  ({4{movr_d}}      & {1'b0,i[12:10]}) |
			  ({4{br_or_tcc_d}} & i[28:25]       );


// cctype is 3 bits
// 10X  icc
// 11X  xcc
// 000  fcc0
// 001  fcc1
// 010  fcc2
// 011  fcc3


exu_ect_ctl_msff_ctl_macro__width_6 fgu_tid_ff  (
 .scan_in(fgu_tid_ff_scanin),
 .scan_out(fgu_tid_ff_scanout),
 .l1clk(l1clk),
 .din  ({fgu_cmp_fcc_tid_fx2[2:0] , lsu_fgu_fld_tid_b[2:0]}),
 .dout ({fgu_cmp_fcc_tid_fx3[2:0] , fgu_fld_fcc_tid_fx3[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


// fcc data

// modeled this after N1, it assumes the data is available 1 cycle earlier than POR

assign fcc_cw_valid[3:0] = fgu_cmp_fcc_vld_fx3[3:0];

assign sel_ct0 = (fgu_cmp_fcc_tid_fx3[2:0] == {dec_thread_group,2'b00});
assign sel_ct1 = (fgu_cmp_fcc_tid_fx3[2:0] == {dec_thread_group,2'b01});
assign sel_ct2 = (fgu_cmp_fcc_tid_fx3[2:0] == {dec_thread_group,2'b10});
assign sel_ct3 = (fgu_cmp_fcc_tid_fx3[2:0] == {dec_thread_group,2'b11});

assign fcc_cw_t0[3:0] = {4{sel_ct0}} & fcc_cw_valid[3:0];
assign fcc_cw_t1[3:0] = {4{sel_ct1}} & fcc_cw_valid[3:0];
assign fcc_cw_t2[3:0] = {4{sel_ct2}} & fcc_cw_valid[3:0];
assign fcc_cw_t3[3:0] = {4{sel_ct3}} & fcc_cw_valid[3:0];

assign fcc_lw_valid[1:0] = {2{lsu_fgu_fld_vld_w}} & fgu_fld_fcc_vld_fx3[1:0];

assign sel_lt0 = (fgu_fld_fcc_tid_fx3[2:0] == {dec_thread_group,2'b00});
assign sel_lt1 = (fgu_fld_fcc_tid_fx3[2:0] == {dec_thread_group,2'b01});
assign sel_lt2 = (fgu_fld_fcc_tid_fx3[2:0] == {dec_thread_group,2'b10});
assign sel_lt3 = (fgu_fld_fcc_tid_fx3[2:0] == {dec_thread_group,2'b11});

assign fcc_lw_t0[1:0] = {2{sel_lt0}} & fcc_lw_valid[1:0];
assign fcc_lw_t1[1:0] = {2{sel_lt1}} & fcc_lw_valid[1:0];
assign fcc_lw_t2[1:0] = {2{sel_lt2}} & fcc_lw_valid[1:0];
assign fcc_lw_t3[1:0] = {2{sel_lt3}} & fcc_lw_valid[1:0];


assign t0_data_in[7:0] = {
			  ({2{fcc_lw_t0[1]}} & fgu_fld_fcc_fx3[7:6]) | ({2{fcc_cw_t0[3]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t0[1]}} & fgu_fld_fcc_fx3[5:4]) | ({2{fcc_cw_t0[2]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t0[1]}} & fgu_fld_fcc_fx3[3:2]) | ({2{fcc_cw_t0[1]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t0[0]}} & fgu_fld_fcc_fx3[1:0]) | ({2{fcc_cw_t0[0]}} & fgu_cmp_fcc_fx3[1:0])
			 };
assign t0_hold_in[7:0] = {
			  {2{~fcc_lw_t0[1] & ~fcc_cw_t0[3]}} & fcc_t0_d[7:6],
			  {2{~fcc_lw_t0[1] & ~fcc_cw_t0[2]}} & fcc_t0_d[5:4],
			  {2{~fcc_lw_t0[1] & ~fcc_cw_t0[1]}} & fcc_t0_d[3:2],
			  {2{~fcc_lw_t0[0] & ~fcc_cw_t0[0]}} & fcc_t0_d[1:0]
			 };

assign fcc_nxt_t0[7:0] = t0_data_in[7:0] | t0_hold_in[7:0];

exu_ect_ctl_msff_ctl_macro__width_8 fcc_t0_ff  (		// FS:wmr_protect
 .scan_in(fcc_t0_ff_wmr_scanin),
 .scan_out(fcc_t0_ff_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  (fcc_nxt_t0[7:0]),
 .dout (fcc_t0_d[7:0]),
  .soclk(soclk)
);

assign t1_data_in[7:0] = {
			  ({2{fcc_lw_t1[1]}} & fgu_fld_fcc_fx3[7:6]) | ({2{fcc_cw_t1[3]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t1[1]}} & fgu_fld_fcc_fx3[5:4]) | ({2{fcc_cw_t1[2]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t1[1]}} & fgu_fld_fcc_fx3[3:2]) | ({2{fcc_cw_t1[1]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t1[0]}} & fgu_fld_fcc_fx3[1:0]) | ({2{fcc_cw_t1[0]}} & fgu_cmp_fcc_fx3[1:0])
			 };
assign t1_hold_in[7:0] = {
			  {2{~fcc_lw_t1[1] & ~fcc_cw_t1[3]}} & fcc_t1_d[7:6],
			  {2{~fcc_lw_t1[1] & ~fcc_cw_t1[2]}} & fcc_t1_d[5:4],
			  {2{~fcc_lw_t1[1] & ~fcc_cw_t1[1]}} & fcc_t1_d[3:2],
			  {2{~fcc_lw_t1[0] & ~fcc_cw_t1[0]}} & fcc_t1_d[1:0]
			 };

assign fcc_nxt_t1[7:0] = t1_data_in[7:0] | t1_hold_in[7:0];

exu_ect_ctl_msff_ctl_macro__width_8 fcc_t1_ff  (		// FS:wmr_protect
 .scan_in(fcc_t1_ff_wmr_scanin),
 .scan_out(fcc_t1_ff_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  (fcc_nxt_t1[7:0]),
 .dout (fcc_t1_d[7:0]),
  .soclk(soclk)
);

assign t2_data_in[7:0] = {
			  ({2{fcc_lw_t2[1]}} & fgu_fld_fcc_fx3[7:6]) | ({2{fcc_cw_t2[3]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t2[1]}} & fgu_fld_fcc_fx3[5:4]) | ({2{fcc_cw_t2[2]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t2[1]}} & fgu_fld_fcc_fx3[3:2]) | ({2{fcc_cw_t2[1]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t2[0]}} & fgu_fld_fcc_fx3[1:0]) | ({2{fcc_cw_t2[0]}} & fgu_cmp_fcc_fx3[1:0])
			 };
assign t2_hold_in[7:0] = {
			  {2{~fcc_lw_t2[1] & ~fcc_cw_t2[3]}} & fcc_t2_d[7:6],
			  {2{~fcc_lw_t2[1] & ~fcc_cw_t2[2]}} & fcc_t2_d[5:4],
			  {2{~fcc_lw_t2[1] & ~fcc_cw_t2[1]}} & fcc_t2_d[3:2],
			  {2{~fcc_lw_t2[0] & ~fcc_cw_t2[0]}} & fcc_t2_d[1:0]
			 };

assign fcc_nxt_t2[7:0] = t2_data_in[7:0] | t2_hold_in[7:0];

exu_ect_ctl_msff_ctl_macro__width_8 fcc_t2_ff  (		// FS:wmr_protect
 .scan_in(fcc_t2_ff_wmr_scanin),
 .scan_out(fcc_t2_ff_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  (fcc_nxt_t2[7:0]),
 .dout (fcc_t2_d[7:0]),
  .soclk(soclk)
);

assign t3_data_in[7:0] = {
			  ({2{fcc_lw_t3[1]}} & fgu_fld_fcc_fx3[7:6]) | ({2{fcc_cw_t3[3]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t3[1]}} & fgu_fld_fcc_fx3[5:4]) | ({2{fcc_cw_t3[2]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t3[1]}} & fgu_fld_fcc_fx3[3:2]) | ({2{fcc_cw_t3[1]}} & fgu_cmp_fcc_fx3[1:0]),
			  ({2{fcc_lw_t3[0]}} & fgu_fld_fcc_fx3[1:0]) | ({2{fcc_cw_t3[0]}} & fgu_cmp_fcc_fx3[1:0])
			 };
assign t3_hold_in[7:0] = {
			  {2{~fcc_lw_t3[1] & ~fcc_cw_t3[3]}} & fcc_t3_d[7:6],
			  {2{~fcc_lw_t3[1] & ~fcc_cw_t3[2]}} & fcc_t3_d[5:4],
			  {2{~fcc_lw_t3[1] & ~fcc_cw_t3[1]}} & fcc_t3_d[3:2],
			  {2{~fcc_lw_t3[0] & ~fcc_cw_t3[0]}} & fcc_t3_d[1:0]
			 };

assign fcc_nxt_t3[7:0] = t3_data_in[7:0] | t3_hold_in[7:0];

exu_ect_ctl_msff_ctl_macro__width_8 fcc_t3_ff  (		// FS:wmr_protect
 .scan_in(fcc_t3_ff_wmr_scanin),
 .scan_out(fcc_t3_ff_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  (fcc_nxt_t3[7:0]),
 .dout (fcc_t3_d[7:0]),
  .soclk(soclk)
);


// use current tid to pick the right thread

// 0in value -var dec_pick_d[3:0] -val 0 1 2 4 8

assign fcc_d[7:0] = ({8{dec_pick_d[0]}} & fcc_t0_d[7:0]) |
		    ({8{dec_pick_d[1]}} & fcc_t1_d[7:0]) |
		    ({8{dec_pick_d[2]}} & fcc_t2_d[7:0]) |
		    ({8{dec_pick_d[3]}} & fcc_t3_d[7:0]);

//---------------------------
// FCC Logic
//--------------------------
// choose current fcc
assign use_fcc0_d = ~cctype_d[1] & ~cctype_d[0];
assign use_fcc1_d = ~cctype_d[1] &  cctype_d[0];
assign use_fcc2_d =  cctype_d[1] & ~cctype_d[0];
assign use_fcc3_d =  cctype_d[1] &  cctype_d[0];

assign curr_fcc_d[1:0] = ({2{use_fcc0_d}} & fcc_d[1:0]) |
			 ({2{use_fcc1_d}} & fcc_d[3:2]) |
			 ({2{use_fcc2_d}} & fcc_d[5:4]) |
			 ({2{use_fcc3_d}} & fcc_d[7:6]);

// decode to make next step easier
assign fcc_dec_d[0] = ~curr_fcc_d[1] & ~curr_fcc_d[0];
assign fcc_dec_d[1] = ~curr_fcc_d[1] &  curr_fcc_d[0];
assign fcc_dec_d[2] =  curr_fcc_d[1] & ~curr_fcc_d[0];
assign fcc_dec_d[3] =  curr_fcc_d[1] &  curr_fcc_d[0];

exu_ect_ctl_msff_ctl_macro__width_4 fcce_ff  (
 .scan_in(fcce_ff_scanin),
 .scan_out(fcce_ff_scanout),
 .l1clk(l1clk_pm1),
 .din  (fcc_dec_d[3:0]),
 .dout (fcc_dec_e[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

exu_ect_ctl_msff_ctl_macro__width_4 brcond_e_reg  (
 .scan_in(brcond_e_reg_scanin),
 .scan_out(brcond_e_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (brcond_d[3:0]),
 .dout (br_cond_e[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign use_xcc_d = cctype_d[2] & cctype_d[1];


assign ccr_byp_data[7:0] = dec_valid_e ? exu_ccr_byp_data1[7:0] :
                                         exu_ccr_byp_data0[7:0];

// mux between xcc and icc
assign cc_d[3:0] =  use_xcc_d ?  ccr_byp_data[7:4] :      // xcc
			         ccr_byp_data[3:0];       // icc

exu_ect_ctl_msff_ctl_macro__width_4 ccreg_e  (
 .scan_in(ccreg_e_scanin),
 .scan_out(ccreg_e_scanout),
 .l1clk(l1clk_pm1),
 .din  (cc_d[3:0]),
 .dout (cc_e[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Branch Type Decode
assign brcond_e[0]  =  ~br_cond_e[1] & ~br_cond_e[0];
assign brcond_e[1]  =  ~br_cond_e[1] &  br_cond_e[0];
assign brcond_e[2]  =   br_cond_e[1] & ~br_cond_e[0];
assign brcond_e[3]  =   br_cond_e[1] &  br_cond_e[0];

// Evaluate potential integer CC branches
assign ltz_e = (cc_e[3] ^ cc_e[1]);

assign cc_breval_e[0] = 1'b0;			// BPN
assign cc_breval_e[1] = cc_e[2];		// BPE
assign cc_breval_e[2] = cc_e[2] | ltz_e;        // BPLE
assign cc_breval_e[3] = ltz_e;			// BPL
assign cc_breval_e[4] = cc_e[2] | cc_e[0];	// BPLEU
assign cc_breval_e[5] = cc_e[0];		// BPCS
assign cc_breval_e[6] = cc_e[3];		// BPNEG
assign cc_breval_e[7] = cc_e[1];		// BPVS 

// mux to choose right condition
assign cc_eval0 = cc_breval_e[0] & brcond_e[0] |
		  cc_breval_e[1] & brcond_e[1] |
		  cc_breval_e[2] & brcond_e[2] |
		  cc_breval_e[3] & brcond_e[3];

assign cc_eval1 = cc_breval_e[4] & brcond_e[0] |
		  cc_breval_e[5] & brcond_e[1] |
		  cc_breval_e[6] & brcond_e[2] |
		  cc_breval_e[7] & brcond_e[3];

// Evaluate FP CC branches
assign fp_breval_e[0] =  1'b0;				// FBN  / A
assign fp_breval_e[1] = ~fcc_dec_e[0];			// FBNE / E
assign fp_breval_e[2] =  fcc_dec_e[1] | fcc_dec_e[2];	// FBLG / UE
assign fp_breval_e[3] =  fcc_dec_e[1] | fcc_dec_e[3];	// FBUL / GE
assign fp_breval_e[4] =  fcc_dec_e[1];			// FBL  / UGE
assign fp_breval_e[5] =  fcc_dec_e[3] | fcc_dec_e[2];	// FBUG / LE
assign fp_breval_e[6] =  fcc_dec_e[2];			// FBG  / ULE
assign fp_breval_e[7] =  fcc_dec_e[3];			// FBU  / O

assign fp_eval0 = fp_breval_e[0] & brcond_e[0] |
		  fp_breval_e[1] & brcond_e[1] |
		  fp_breval_e[2] & brcond_e[2] |
		  fp_breval_e[3] & brcond_e[3];

assign fp_eval1 = fp_breval_e[4] & brcond_e[0] |
		  fp_breval_e[5] & brcond_e[1] |
		  fp_breval_e[6] & brcond_e[2] |
		  fp_breval_e[7] & brcond_e[3];


exu_ect_ctl_msff_ctl_macro__width_1 cctype_reg  (
 .scan_in(cctype_reg_scanin),
 .scan_out(cctype_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (cctype_d[2]),
 .dout (cctype_e[2]),
  .siclk(siclk),
  .soclk(soclk)
);

assign fpcond_mvbr_e = ~cctype_e[2];

// merge eval0, eval1 and fp condition codes
assign cc_eval = (~fpcond_mvbr_e & ~br_cond_e[2] & cc_eval0) |
		 (~fpcond_mvbr_e &  br_cond_e[2] & cc_eval1) | 
		 ( fpcond_mvbr_e & ~br_cond_e[2] & fp_eval0) | 
	         ( fpcond_mvbr_e &  br_cond_e[2] & fp_eval1);

// invert branch condition if this is an inverted br type
assign cond_true_e = cc_eval ^ br_cond_e[3];  

exu_ect_ctl_msff_ctl_macro__width_4 misc_ff  (
 .scan_in(misc_ff_scanin),
 .scan_out(misc_ff_scanout),
 .l1clk(l1clk_pm1),
 .din  ({callclass_d , specbr_d , cmov_d , regop_d}),
 .dout ({callclass_e , specbr_e , cmov_e , regop_e}),
  .siclk(siclk),
  .soclk(soclk)
);

//--------------
// For BRZ
// -------------
// Calculate Cond Assuming Z=1 And Z=0.  Then Mux
assign r_eval1 = (edp_br_flag_e[1] | ~br_cond_e[1]  | ~br_cond_e[0]) ^ br_cond_e[2];

assign r_eval0 = (edp_br_flag_e[1] &  br_cond_e[1]) ^ br_cond_e[2];


// Evaluate Final Branch condition
// 3:1 mux

assign final_cond_true_z0_e = 	(~regop_e & cond_true_e) |
				( regop_e & r_eval0    );

assign final_cond_true_z1_e = 	(~regop_e & cond_true_e) |
				( regop_e & r_eval1    );

// valid_e takes annul into account


// 0in value -var {callclass_e & dec_valid_e,cmov_e & dec_valid_e,tcc_e & dec_valid_e} -val 0 1 2 4 			

assign ect_br_taken_z0_e = (callclass_e | (specbr_e & final_cond_true_z0_e));
assign ect_br_taken_z1_e = (callclass_e | (specbr_e & final_cond_true_z1_e));


// 3 cases for {zero,neg} are 00, 01, 10 (11 illegal)

assign dec_cmov_z00_e = cmov_e & ((~regop_e & cond_true_e) | (regop_e & br_cond_e[2]));                 // 00 case

assign dec_cmov_z01_e = cmov_e & ((~regop_e & cond_true_e) | (regop_e & (br_cond_e[1] ^ br_cond_e[2])));  // 01 case

assign dec_cmov_z10_e = cmov_e & ((~regop_e & cond_true_e) | (regop_e & ((~br_cond_e[1] | ~br_cond_e[0]) ^ br_cond_e[2]))); // 10 case


assign tcc_taken_e    = (tcc_e & final_cond_true_z0_e & ~edp_br_flag_e[0]) |
                        (tcc_e & final_cond_true_z1_e &  edp_br_flag_e[0]);


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : DEC_CCR_CTL  !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


exu_ect_ctl_spare_ctl_macro__num_6 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk));


supply0 vss;
supply1 vdd;

// fixscan start:
assign i_pwr0_lth_scanin         = scan_in                  ;
assign i_pwr1_lth_scanin         = i_pwr0_lth_scanout       ;
assign i_mbist_lth_scanin        = i_pwr1_lth_scanout       ;
assign i_estage_lth_scanin       = i_mbist_lth_scanout      ;
assign i_mstage_lth_scanin       = i_estage_lth_scanout     ;
assign ren_lth_scanin            = i_mstage_lth_scanout     ;
assign rs_lth_scanin             = ren_lth_scanout          ;
assign i_byp_lth_scanin          = rs_lth_scanout           ;
assign i_ccr_pipe_lth_scanin     = i_byp_lth_scanout        ;
assign i_tlu_lth_scanin          = i_ccr_pipe_lth_scanout   ;
assign i_yreg_mpipe_lth_scanin   = i_tlu_lth_scanout        ;
assign i_yreg_spipe_lth_scanin   = i_yreg_mpipe_lth_scanout ;
assign fgu_tid_ff_scanin         = i_yreg_spipe_lth_scanout ;
assign fcce_ff_scanin            = fgu_tid_ff_scanout       ;
assign brcond_e_reg_scanin       = fcce_ff_scanout          ;
assign ccreg_e_scanin            = brcond_e_reg_scanout     ;
assign cctype_reg_scanin         = ccreg_e_scanout          ;
assign misc_ff_scanin            = cctype_reg_scanout       ;
assign spares_scanin             = misc_ff_scanout          ;
assign scan_out                  = spares_scanout           ;

assign i_ccr_arch_lth_wmr_scanin = wmr_scan_in              ;
assign fcc_t0_ff_wmr_scanin      = i_ccr_arch_lth_wmr_scanout;
assign fcc_t1_ff_wmr_scanin      = fcc_t0_ff_wmr_scanout    ;
assign fcc_t2_ff_wmr_scanin      = fcc_t1_ff_wmr_scanout    ;
assign fcc_t3_ff_wmr_scanin      = fcc_t2_ff_wmr_scanout    ;
assign wmr_scan_out              = fcc_t3_ff_wmr_scanout    ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_37 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [36:0] fdin;
wire [35:0] so;

  input [36:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [36:0] dout;
  output scan_out;
assign fdin[36:0] = din[36:0];


dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_15 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [14:0] fdin;
wire [13:0] so;

  input [14:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [14:0] dout;
  output scan_out;
assign fdin[14:0] = din[14:0];


dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[14:0]),
.si({scan_in,so[13:0]}),
.so({so[13:0],scan_out}),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_76 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [75:0] fdin;
wire [74:0] so;

  input [75:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [75:0] dout;
  output scan_out;
assign fdin[75:0] = din[75:0];


dff #(76)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[75:0]),
.si({scan_in,so[74:0]}),
.so({so[74:0],scan_out}),
.q(dout[75:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_28 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [27:0] fdin;
wire [26:0] so;

  input [27:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [27:0] dout;
  output scan_out;
assign fdin[27:0] = din[27:0];


dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_32 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [30:0] so;

  input [31:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = din[31:0];


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_ect_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module exu_ect_ctl_spare_ctl_macro__num_6 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));
assign scan_out = so_5;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: exu_edp_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module exu_edp_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  in_rngl_cdbus, 
  tlu_pc_d, 
  dec_inst_d, 
  dec_thread_group, 
  dec_exu_clken, 
  fgu_exu_w_vld_fx5, 
  fgu_exu_result_fx5, 
  irf_rs1_data_d, 
  irf_rs2_data_d, 
  irf_rs3_data_d, 
  lsu_asi_clken, 
  lsu_exu_ld_data_b, 
  mbi_write_data_p1, 
  exu_y_data_e, 
  rml_rng_data_out, 
  rml_rng_rd_ctl, 
  rml_rng_ack_ctl, 
  rml_rng_ack_cwp_tid, 
  rml_rng_ack_ecc_tid, 
  rml_rng_ack_det_vld, 
  rml_rng_wt_imask_ctl, 
  rml_irf_ecc_data, 
  rml_rng_ack_sel_ctl, 
  rml_rng_y_data, 
  ect_rng_ccr_data, 
  ect_mbist_sel, 
  ecc_mbist_write_data_p4, 
  ect_rs1_early_sel_d, 
  ect_rs2_early_sel_d, 
  ect_rs3_early_sel_d, 
  ect_rs2_imm_sel_d, 
  ect_rs1_late_sel_d, 
  ect_rs2_late_sel_d, 
  ect_rs3_late_sel_d, 
  ect_logic_sel_d, 
  ect_shift_sel_d, 
  ect_br_taken_z0_e, 
  ect_br_taken_z1_e, 
  ect_alignaddress_little_e, 
  ect_as_clip_e_, 
  ect_as_cin_e, 
  ect_array_sel_e, 
  ect_edge_lmask_e, 
  ect_edge_lrmask_e, 
  ect_pstate_am_e, 
  ect_rm_early_sel_e, 
  ect_rm_late_sel_e, 
  ect_store_mux_sel_e, 
  ect_ex_emb_clken, 
  ect_tg_clken, 
  exu_rngl_cdbus, 
  exu_br_taken_e, 
  exu_br_taken_e1, 
  exu_address_e, 
  exu_gsr_data_m, 
  exu_store_data_e, 
  exu_ibp_m, 
  exu_trap_number_b, 
  exu_mbi_irf_fail_, 
  edp_rng_in_ff, 
  edp_br_flag_e, 
  exu_rs1_data_e, 
  edp_rcc_data_e, 
  exu_rs2_data_e, 
  edp_rs3_data_e, 
  edp_rcc_ecc_e, 
  edp_rs2_ecc_e, 
  edp_rs3_ecc_e, 
  edp_add_cout64_e, 
  edp_add_data_e_b63, 
  edp_add_zdetect_e_, 
  edp_sub_cout64_e, 
  edp_sub_data_e_b63, 
  edp_sub_data_e_b31, 
  edp_sub_zdetect_e_, 
  edp_logical_data_e_b63, 
  edp_logical_data_e_b31, 
  edp_lg_zdetect_e, 
  edp_address_m, 
  edp_rd_ff_m, 
  edp_rd_ff_w, 
  edp_rd_ff_w2, 
  scan_out);
wire stop;
wire test;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [63:0] rd_ff_m;
wire [63:0] rd_ff_b;
wire [63:0] rd_ff_w_plus1;
wire [63:0] rd_ff_w2_plus1;
wire [63:0] early_rs1_data;
wire i_bp_ff_rcc_scanin;
wire i_bp_ff_rcc_scanout;
wire [63:0] rd_data_e;
wire [71:0] rcc_data_e;
wire [4:0] rs1_psel;
wire i_bp_ff_rs1_scanin;
wire i_bp_ff_rs1_scanout;
wire [63:0] rs1_data_e;
wire br_flag_e0_;
wire br_taken_nand0;
wire br_taken_nand1;
wire inst_d_09_buf;
wire inst_d_10_buf;
wire inst_d_12_buf;
wire inst_d_18_buf;
wire inst_d_21_buf0;
wire inst_d_21_buf1;
wire inst_d_29_buf;
wire [63:0] imm_rs2_data;
wire [63:0] early_byp_rs2_data;
wire i_bp_ff_rs2_scanin;
wire i_bp_ff_rs2_scanout;
wire [71:0] rs2_data_e;
wire [63:0] early_rs3_data;
wire [4:0] rs3_psel;
wire i_bp_ff_rs3_scanin;
wire i_bp_ff_rs3_scanout;
wire [71:0] rs3_data_e;
wire [63:0] wrxx_xor;
wire [63:0] store_data_e;
wire [1:0] rs1_x_rs2_cmp_e;
wire [1:0] rs1_x_rs2_cmp_e_;
wire pstate_am_e_;
wire [1:0] edge_lr_nand3_;
wire edge_l_nand3_;
wire edge_l_nand2_;
wire edge_lr_sel_e;
wire edge_l_sel_e;
wire [1:0] cmp_mbi_irf_fail_;
wire rs3_data_e_b47_buf;
wire [63:0] logical_data_e;
wire [32:0] array_res_e;
wire [63:0] early_rd_data;
wire [2:2] tcu_muxtest_rep0;
wire [63:0] sub_data_e;
wire [63:0] add_data_e;
wire [2:0] add_clip;
wire [63:0] shifter_data_e;
wire i_rm_ff_m_scanin;
wire i_rm_ff_m_scanout;
wire [2:0] addsub_inc;
wire [2:0] addsub_data_m;
wire i_rm_ff_b_scanin;
wire i_rm_ff_b_scanout;
wire i_rm_ff_w_scanin;
wire i_rm_ff_w_scanout;
wire [63:0] rd_ff_w;
wire i_rm_ff_w_plus1_scanin;
wire i_rm_ff_w_plus1_scanout;
wire i_rm_ff_w2_scanin;
wire i_rm_ff_w2_scanout;
wire ibe_trap_d;
wire ibe_trap_e;
wire ibp_m;
wire [63:0] rd_ff_w2;
wire i_rm_ff_w2_plus1_scanin;
wire i_rm_ff_w2_plus1_scanout;
wire [3:0] logic_sel_e;
wire [3:0] logic_hsel_e;
wire [3:0] logic_lsel_e;
wire [63:0] rs1_data_e_;
wire [63:0] log_rs2_data_e_;
wire [63:0] logical_11_;
wire [63:0] logical_10_;
wire [63:0] logical_01_;
wire [63:0] logical_00_;
wire i_misc_ff_scanin;
wire i_misc_ff_scanout;
wire [6:0] shift_sel_e;
wire sh_sel_rshift;
wire sh_sel_lshift;
wire sh_sel_rax;
wire sh_sel_ra;
wire sh_sel_rshiftx;
wire sh_sel_llx;
wire [63:0] sh_rs1_buf;
wire sh_rs1_63_;
wire sh_rs1_31_;
wire sel_rshift00;
wire sel_lshift00;
wire sel_rshiftx00;
wire sel_ra00;
wire sel_rax00;
wire sh_rs1_00_63;
wire sh_rs1_00_31;
wire [70:0] mask_mux00;
wire sel_rshift08;
wire sel_lshift08;
wire sel_rshiftx08;
wire sel_ra08;
wire sel_rax08;
wire sh_rs1_08_63;
wire sh_rs1_08_31;
wire [70:0] mask_mux08;
wire sel_rshift16;
wire sel_lshift16;
wire sel_rshiftx16;
wire sel_ra16;
wire sel_rax16;
wire sh_rs1_16_63;
wire sh_rs1_16_31;
wire [70:0] mask_mux16;
wire sel_rshift24;
wire sel_lshift24;
wire sel_rshiftx24;
wire sel_ra24;
wire sel_rax24;
wire sh_rs1_24_63;
wire sh_rs1_24_31;
wire [70:0] mask_mux24;
wire sel_rshiftx32;
wire sel_rax32;
wire sel_llx32;
wire sh_rs1_32_63;
wire [70:0] mask_mux32;
wire sel_rshiftx40;
wire sel_rax40;
wire sel_llx40;
wire sh_rs1_40_63;
wire [70:0] mask_mux40;
wire sel_rshiftx48;
wire sel_rax48;
wire sel_llx48;
wire sh_rs1_48_63;
wire [70:0] mask_mux48;
wire sel_rshiftx56;
wire sel_rax56;
wire sel_llx56;
wire sh_rs1_56_63;
wire [70:0] mask_mux56;
wire rs2_5;
wire [70:0] sht_by8;
wire [70:0] sht_by8_buf;
wire [2:0] rs2_;
wire [2:0] rs2_mux;
wire [63:0] rs2_data_e_;
wire [2:0] addsub_xor;
wire [1:0] i_as_cla_inc_unused;
wire [63:0] cla_ea;
wire i_asi0_ff_scanin;
wire i_asi0_ff_scanout;
wire [64:0] rng_ack_data;
wire i_asi1_ff_scanin;
wire i_asi1_ff_scanout;
wire [38:0] asi_inst_mask_reg;
wire [64:0] rng_out_ff;
wire i_asi_imask_ff_scanin;
wire i_asi_imask_ff_scanout;
wire [6:0] inst_mask_sel_;
wire [6:0] inst_mask_sel;
wire [31:0] imask_cmp_data;
wire ibe_cmp8_d_;
wire ibe_cmp32_d;
wire ibe_cmp8_d;
wire [8:0] zint_e;
wire [10:0] yint_e;
wire [10:0] xint_e;
wire [13:0] array_upper_data0;
wire [13:0] array_upper_data1;
wire [13:0] array_upper_data2;
wire [13:0] array_upper_data3;
wire [13:0] array_upper_data4;
wire [13:0] array_upper_data5;
wire [13:0] array_upper_e;
wire [11:0] array_middle_e;
wire [4:0] array_lower_e;
wire [32:0] array08_data;
wire [32:0] array16_data;
wire [32:0] array32_data;


// *** Global Inputs ***

input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;			// scan signals
input 		spc_aclk;
input 		spc_bclk;
input		tcu_scan_en;
input		tcu_dectest;			// Passgate mux test control
input		tcu_muxtest;			// Passgate mux test control

input  [64:0]	in_rngl_cdbus;			// ASI Ring

input  [47:2]	tlu_pc_d;
input  [31:0]	dec_inst_d;
input		dec_thread_group;		// Static Signal : Tie UP or DOWN where cloning occurs
input		dec_exu_clken;

input		fgu_exu_w_vld_fx5;
input  [63:0]	fgu_exu_result_fx5;		// FGU Integer results

input  [71:0]	irf_rs1_data_d;
input  [71:0]	irf_rs2_data_d;
input  [71:0]	irf_rs3_data_d;

input		lsu_asi_clken;
input  [63:0]	lsu_exu_ld_data_b;

input  [7:0]	mbi_write_data_p1;		// MBIST


// *** Local  Inputs ***

input  [31:0]	exu_y_data_e;

input  [5:0]	rml_rng_data_out;		// ASI Read data from RML
input  [4:0]	rml_rng_rd_ctl;			// ASI Read Select
input  [1:0]	rml_rng_ack_ctl;		// ASI Read Ack Select
input  [1:0]	rml_rng_ack_cwp_tid;		// ASI Write CWP tid
input  [1:0]	rml_rng_ack_ecc_tid;		// ASI Read ECC tid
input  		rml_rng_ack_det_vld;		// ASI Read Ack vld Select
input		rml_rng_wt_imask_ctl;		// Enable for ASI write to Instruction mask reg
input  [7:0]	rml_irf_ecc_data;               // Saved irf ECC data for indet. ASI access
input		rml_rng_ack_sel_ctl;            // Sel ack type onto ASI rng 
input [31:0]	rml_rng_y_data;
input [7:0]	ect_rng_ccr_data;

input		ect_mbist_sel;			// MBIST
input  [7:0]	ecc_mbist_write_data_p4;	// MBIST

input  [4:0]	ect_rs1_early_sel_d;
input  [4:0]	ect_rs2_early_sel_d;
input  [4:0]	ect_rs3_early_sel_d;
input  [7:0]	ect_rs2_imm_sel_d;
input  [3:0]	ect_rs1_late_sel_d;
input  [3:0]	ect_rs2_late_sel_d;
input  [3:0]	ect_rs3_late_sel_d;
input  [3:0]	ect_logic_sel_d;
input  [6:0]	ect_shift_sel_d;

input		ect_br_taken_z0_e;
input		ect_br_taken_z1_e;
input		ect_alignaddress_little_e;
input		ect_as_clip_e_;			// ALIGNADDRESS clipping of bit [2:0]
input		ect_as_cin_e;
input  [1:0]	ect_array_sel_e;
input  [7:0]	ect_edge_lmask_e;
input  [7:0]	ect_edge_lrmask_e;
input		ect_pstate_am_e;
input  [5:0]	ect_rm_early_sel_e;
input  [2:0]	ect_rm_late_sel_e;		//  [0] : AddSub;  [1] : Shift;  [2] : Logicals;  Def : Early Mux;
input		ect_store_mux_sel_e;

input		ect_ex_emb_clken;		// Power Management
input		ect_tg_clken;			// Power Management


// *** Global Outputs ***

output [64:0]	exu_rngl_cdbus;			// ASI Ring

output		exu_br_taken_e;			// To IFU             : branch is taken
output		exu_br_taken_e1;		// To DEC_DEL and PKU : branch is taken
output [47:0]	exu_address_e;			// To IFU and LSU
output [31:0]	exu_gsr_data_m;			// To FGU
output [63:0]	exu_store_data_e;		// To LSU

output		exu_ibp_m;			// To TLU : Raw Intruction Breakpoint
output [7:0]	exu_trap_number_b;		// To TLU

output [1:0]	exu_mbi_irf_fail_;		// MBIST


// *** Local  Outputs ***

output [64:0]	edp_rng_in_ff;			// ASI Ring : In data flopped

output [1:0]	edp_br_flag_e;			// To IFU    [1] : RS1 negative;  [0] : RS1 zero;
output [63:0]	exu_rs1_data_e;
output [63:0]	edp_rcc_data_e;			// To ECC: rs1 equivalent for ECC checks
output [63:0]	exu_rs2_data_e;
output [63:0]	edp_rs3_data_e;
output [7:0]	edp_rcc_ecc_e;			// To ECC: rs1 equivalent for ECC checks
output [7:0]	edp_rs2_ecc_e;
output [7:0]	edp_rs3_ecc_e;

output		edp_add_cout64_e;
output		edp_add_data_e_b63;
output [1:0]	edp_add_zdetect_e_;

output		edp_sub_cout64_e;
output		edp_sub_data_e_b63;
output		edp_sub_data_e_b31;
output [1:0]	edp_sub_zdetect_e_;

output		edp_logical_data_e_b63;
output		edp_logical_data_e_b31;
output [1:0]	edp_lg_zdetect_e;

output [63:47]	edp_address_m;			// Used for address_error checking
output [63:47]	edp_rd_ff_m;

output [63:0]	edp_rd_ff_w;
output [63:0]	edp_rd_ff_w2;

output		scan_out;


// scan/test renames
assign stop		= 1'b0;
assign test		= tcu_dectest;
// end scan/test renames


exu_edp_dp_buff_macro__dbuff_32x__stack_none__width_4	scan_rep0		 (
  .din ({tcu_scan_en , tcu_pce_ov , spc_aclk , spc_bclk}	),
  .dout({se          , pce_ov     , siclk    , soclk}		));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Bypass       !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


// *** RS1 ***

exu_edp_dp_mux_macro__mux_aope__ports_6__stack_72c__width_64	i_bp_mux_rs1_early	 (
  .din0 ( rd_ff_m[63:0]		 						),	// M  Stage
  .din1 ( rd_ff_b[63:0]			 					),	// B  Stage
  .din2 ( edp_rd_ff_w[63:0]						 	),	// W  Stage
  .din3 ( edp_rd_ff_w2[63:0]		 					),	// W2 Stage
  .din4 (     rd_ff_w_plus1[63:0]						),	// W_plus1  Stage
  .din5 (     rd_ff_w2_plus1[63:0]		 				),	// W2_plus2 Stage
  .sel0 ( ect_rs1_early_sel_d[0]	 					),
  .sel1 ( ect_rs1_early_sel_d[1]	 					),
  .sel2 ( ect_rs1_early_sel_d[2]	 					),
  .sel3 ( ect_rs1_early_sel_d[3]	 					),
  .sel4 ( ect_rs1_early_sel_d[4]	 					),
  .dout ( early_rs1_data[63:0]		 					));


exu_edp_dp_msff_macro__mux_aope__ports_4__stack_72c__width_72	i_bp_ff_rcc		 (
  .scan_in(i_bp_ff_rcc_scanin),
  .scan_out(i_bp_ff_rcc_scanout),
  .clk  ( l2clk									),
  .en   ( dec_exu_clken								),
  .din0 ({{8{1'b0}},rd_data_e[63:0]}						),	// Execute Stage
  .din1 ({{8{1'b0}},lsu_exu_ld_data_b[63:0]}					),	// Load Data
  .din2 ({{8{1'b0}},early_rs1_data[63:0]}					),	// Early Mux
  .din3 ( irf_rs1_data_d[71:0]							),
  .sel0 ( ect_rs1_late_sel_d[1]							),
  .sel1 ( ect_rs1_late_sel_d[2]							),
  .sel2 ( ect_rs1_late_sel_d[3]							),
  .dout ( rcc_data_e[71:0]							),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


cl_dp1_penc5_64x	i_bp_ff_rs1_penc (
  .sel0 ( ect_rs1_late_sel_d[0]							),
  .sel1 ( ect_rs1_late_sel_d[1]							),
  .sel2 ( ect_rs1_late_sel_d[2]							),
  .sel3 ( ect_rs1_late_sel_d[3]							),
  .psel0( rs1_psel[0]								),
  .psel1( rs1_psel[1]								),
  .psel2( rs1_psel[2]								),
  .psel3( rs1_psel[3]								),
  .psel4( rs1_psel[4]								),
  .test(test));


exu_edp_dp_msff_macro__buffsel_none__mux_aonpe__ports_5__stack_72c__width_64	i_bp_ff_rs1		 (
  .scan_in(i_bp_ff_rs1_scanin),
  .scan_out(i_bp_ff_rs1_scanout),
  .clk  ( l2clk									),
  .en   ( dec_exu_clken								),
  .din0 (            rd_data_e[63:0]						),	// Execute Stage
  .din1 (            lsu_exu_ld_data_b[63:0]					),	// Load Data
  .din2 (            early_rs1_data[63:0] 					),	// Early Mux
  .din3 (            irf_rs1_data_d[63:0]					),	// IRF
  .din4 (            {{16{1'b0}}, tlu_pc_d[47:2], 2'b00}			),	// PC
  .sel0 ( rs1_psel[1]								),
  .sel1 ( rs1_psel[2]								),
  .sel2 ( rs1_psel[3]								),
  .sel3 ( rs1_psel[4]								),
  .sel4 ( rs1_psel[0]								),
  .dout ( rs1_data_e[63:0]							),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_64	i_bp_buf_rs1		 (
  .din  ( rs1_data_e[63:0]							),
  .dout ( exu_rs1_data_e[63:0]							));

exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_72	i_bp_buf_rcc		 (
  .din  ({rcc_data_e[71:64]  , rcc_data_e[63:0]}				),
  .dout ({edp_rcc_ecc_e[7:0] , edp_rcc_data_e[63:0]}				));


exu_edp_dp_zero_macro__width_64	i_bp_cmp_rcc		 (
  .din ( rcc_data_e[63:0]							),
  .dout( edp_br_flag_e[0]							));


exu_edp_dp_inv_macro__dinv_12x__stack_72c__width_1	i_br_taken_inv		 (
  .din ( edp_br_flag_e[0]							),
  .dout(     br_flag_e0_							));

//mux_macro	i_br_taken_mux		(width=1,ports=2,mux=aonpe,buffsel=none,left=1,stack=72c) (
//  .din0( ect_br_taken_z0_e							),
//  .din1( ect_br_taken_z1_e							),
//  .sel0(     br_flag_e0_							),
//  .sel1( edp_br_flag_e[0]							),
//  .dout( br_taken_mux_e							));

exu_edp_dp_nand_macro__dnand_16x__left_1__ports_2__stack_72c__width_1	i_br_taken_nand0	 (
  .din0 ( br_flag_e0_								),
  .din1 ( ect_br_taken_z0_e							),
  .dout ( br_taken_nand0							));

exu_edp_dp_nand_macro__ports_2__stack_72c__width_1	i_br_taken_nand1	 (
  .din0 ( edp_br_flag_e[0]							),
  .din1 ( ect_br_taken_z1_e							),
  .dout ( br_taken_nand1							));

exu_edp_dp_nand_macro__dnand_32x__left_1__ports_2__stack_72c__width_2	i_br_taken_nand23	 (
  .din0 ({ br_taken_nand0 , br_taken_nand0} 					),
  .din1 ({ br_taken_nand1 , br_taken_nand1} 					),
  .dout ({ exu_br_taken_e , exu_br_taken_e1}					));


exu_edp_dp_buff_macro__stack_72c__width_1	i_bp_buf_flag		 (
  .din  ( rcc_data_e[63]							),
  .dout ( edp_br_flag_e[1]							));


// *** RS2 ***

exu_edp_dp_buff_macro__stack_72c__width_7	i_bp_imm_buf		 (
  .din ({ dec_inst_d[9] , dec_inst_d[10] , dec_inst_d[12] , 
          dec_inst_d[18] , dec_inst_d[21] , dec_inst_d[21] , dec_inst_d[29]}	),
  .dout({ inst_d_09_buf  , inst_d_10_buf  , inst_d_12_buf  , 
          inst_d_18_buf  , inst_d_21_buf0 , inst_d_21_buf1 , inst_d_29_buf}	));


exu_edp_dp_mux_macro__mux_aonpe__ports_8__stack_72c__width_64	i_bp_mux_rs2_imm	 (
  .din0 ({{46{inst_d_21_buf0}}, dec_inst_d[21:20],dec_inst_d[13:0] ,2'b00	}),	// BPr  = 4 * sign_ext{d16hi,d16lo} = 4 * sign_ext{inst[21:20],inst[13:0]}
  .din1 ({{40{inst_d_21_buf1}}, dec_inst_d[21:0] ,                  2'b00	}),	// Bicc = 4 * sign_ext{disp22}      = 4 * sign_ext{inst[21:0]}
  .din2 ({{43{inst_d_18_buf }}, dec_inst_d[18:0] ,                  2'b00	}),	// BPcc = 4 * sign_ext{disp19}      = 4 * sign_ext{inst[18:0]}
  .din3 ({{32{inst_d_29_buf }}, dec_inst_d[29:0] ,                  2'b00	}),	// Call = 4 * sign_ext{disp30}      = 4 * sign_ext{inst[29:0]}
  .din4 ({{32{1'b0}}          , dec_inst_d[21:0] ,                  {10{1'b0}}	}),	// IMM22
  .din5 ({{53{inst_d_10_buf }}, dec_inst_d[10:0]				}),	// SIMM11
  .din6 ({{54{inst_d_09_buf }}, dec_inst_d[9:0]				}),	// SIMM10
  .din7 ({{51{inst_d_12_buf }}, dec_inst_d[12:0]				}),	// SIMM13
  .sel0 ( ect_rs2_imm_sel_d[0]	 						 ),
  .sel1 ( ect_rs2_imm_sel_d[1]	 						 ),
  .sel2 ( ect_rs2_imm_sel_d[2]	 						 ),
  .sel3 ( ect_rs2_imm_sel_d[3]	 						 ),
  .sel4 ( ect_rs2_imm_sel_d[4]	 						 ),
  .sel5 ( ect_rs2_imm_sel_d[5]	 						 ),
  .sel6 ( ect_rs2_imm_sel_d[6]	 						 ),
  .sel7 ( ect_rs2_imm_sel_d[7]	 						 ),
  .dout ( imm_rs2_data[63:0]		 					 ));


exu_edp_dp_mux_macro__mux_aope__ports_6__stack_72c__width_64	i_bp_mux_rs2_early_byp	 (
  .din0 ( rd_ff_m[63:0]								),	// M  Stage
  .din1 ( rd_ff_b[63:0]			 					),	// B  Stage
  .din2 ( edp_rd_ff_w[63:0]			 				),	// W  Stage
  .din3 ( edp_rd_ff_w2[63:0]		 					),	// W2 Stage
  .din4 (     rd_ff_w_plus1[63:0]						),	// W_plus1  Stage
  .din5 (     rd_ff_w2_plus1[63:0]		 				),	// W2_plus1 Stage
  .sel0 ( ect_rs2_early_sel_d[0]	 					),
  .sel1 ( ect_rs2_early_sel_d[1]	 					),
  .sel2 ( ect_rs2_early_sel_d[2]	 					),
  .sel3 ( ect_rs2_early_sel_d[3]	 					),
  .sel4 ( ect_rs2_early_sel_d[4]	 					),
  .dout ( early_byp_rs2_data[63:0]		 				));


exu_edp_dp_msff_macro__mux_aope__ports_5__stack_72c__width_72	i_bp_ff_rs2		 (
  .scan_in(i_bp_ff_rs2_scanin),
  .scan_out(i_bp_ff_rs2_scanout),
  .clk  ( l2clk									),
  .en   ( dec_exu_clken								),
  .din0 ({{8{1'b0}} ,imm_rs2_data[63:0]}					),	// Immediate Data
  .din1 ({{8{1'b0}} ,rd_data_e[63:0]}						),	// Execute Stage
  .din2 ({{8{1'b0}} ,lsu_exu_ld_data_b[63:0]}					),	// Load Data
  .din3 ({{8{1'b0}} ,early_byp_rs2_data[63:0]}					),	// Early Mux
  .din4 ( irf_rs2_data_d[71:0]							),
  .sel0 ( ect_rs2_late_sel_d[0]							),
  .sel1 ( ect_rs2_late_sel_d[1]							),
  .sel2 ( ect_rs2_late_sel_d[2]							),
  .sel3 ( ect_rs2_late_sel_d[3]							),
  .dout ( rs2_data_e[71:0]							),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_72	i_bp_buf_rs2		 (
  .din ( rs2_data_e[71:0]							),
  .dout({edp_rs2_ecc_e[7:0] , exu_rs2_data_e[63:0]}				));


// *** RS3 ***

exu_edp_dp_mux_macro__mux_aope__ports_6__stack_72c__width_64	i_bp_mux_rs3_early	 (
  .din0 ( rd_ff_m[63:0]		 						),	// M  Stage
  .din1 ( rd_ff_b[63:0]						 		),	// B  Stage
  .din2 ( edp_rd_ff_w[63:0]						 	),	// W  Stage
  .din3 ( edp_rd_ff_w2[63:0]					 		),	// W2 Stage
  .din4 (     rd_ff_w_plus1[63:0]						),	// W_plus1  Stage
  .din5 (     rd_ff_w2_plus1[63:0]		 				),	// W2_plus1 Stage
  .sel0 ( ect_rs3_early_sel_d[0]				 		),
  .sel1 ( ect_rs3_early_sel_d[1]				 		),
  .sel2 ( ect_rs3_early_sel_d[2]				 		),
  .sel3 ( ect_rs3_early_sel_d[3]	 					),
  .sel4 ( ect_rs3_early_sel_d[4]	 					),
  .dout ( early_rs3_data[63:0]					 		));


cl_dp1_penc5_64x	i_bp_ff_rs3_penc (
  .sel0 ( ect_rs3_late_sel_d[0]							),
  .sel1 ( ect_rs3_late_sel_d[1]							),
  .sel2 ( ect_rs3_late_sel_d[2]							),
  .sel3 ( ect_rs3_late_sel_d[3]							),
  .psel0( rs3_psel[0]								),
  .psel1( rs3_psel[1]								),
  .psel2( rs3_psel[2]								),
  .psel3( rs3_psel[3]								),
  .psel4( rs3_psel[4]								),
  .test(test));


exu_edp_dp_msff_macro__buffsel_none__mux_aonpe__ports_5__stack_72c__width_72	i_bp_ff_rs3		 (
  .scan_in(i_bp_ff_rs3_scanin),
  .scan_out(i_bp_ff_rs3_scanout),
  .clk  ( l2clk									),
  .en   ( dec_exu_clken								),
  .din0 ({{8{1'b0}},rd_data_e[63:0]}						),	// Execute Stage
  .din1 ({{8{1'b0}},lsu_exu_ld_data_b[63:0]}					),	// Load Data
  .din2 ({{8{1'b0}},early_rs3_data[63:0]}					),	// Early Mux
  .din3 ( irf_rs3_data_d[71:0]							),	// IRF
  .din4 ({{8{1'b0}},{16{1'b0}}, tlu_pc_d[47:2], 2'b00}				),	// PC : CALL & JUMP
  .sel0 ( rs3_psel[1]								),
  .sel1 ( rs3_psel[2]								),
  .sel2 ( rs3_psel[3]								),
  .sel3 ( rs3_psel[4]								),
  .sel4 ( rs3_psel[0]								),
  .dout ( rs3_data_e[71:0]							),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_72	i_bp_buf_rs3		 (
  .din ( rs3_data_e[71:0]							),
  .dout({edp_rs3_ecc_e[7:0] , edp_rs3_data_e[63:0]}				));


exu_edp_dp_xor_macro__ports_2__stack_72c__width_64	i_bp_xor_wrxx		 (
  .din0( exu_rs1_data_e[63:0]							),
  .din1( exu_rs2_data_e[63:0]							),
  .dout( wrxx_xor[63:0]								));

exu_edp_dp_mux_macro__mux_aope__ports_2__stack_72c__width_64	i_bp_mux_store		 (
  .din0( wrxx_xor[63:0]								),	// Write Privileded (239) and Write State (241)
  .din1( edp_rs3_data_e[63:0]							),
  .sel0( ect_store_mux_sel_e							),
  .dout( store_data_e[63:0]							));

exu_edp_dp_buff_macro__stack_72c__width_64	i_bp_buf_store		 (
  .din ( store_data_e[63:0]							),
  .dout( exu_store_data_e[63:0]							));


exu_edp_dp_cmp_macro__width_32	i_bp_cmp1		 (
  .din0( rs1_data_e[63:32]							),
  .din1( rs2_data_e[63:32]							),
  .dout( rs1_x_rs2_cmp_e[1]							));

exu_edp_dp_cmp_macro__width_32	i_bp_cmp0		 (
  .din0({rs1_data_e[31:3] , 3'b000}						),
  .din1({rs2_data_e[31:3] , 3'b000}						),
  .dout( rs1_x_rs2_cmp_e[0]							));


exu_edp_dp_inv_macro__stack_72c__width_3	i_mask_inv		 (
  .din ({rs1_x_rs2_cmp_e[1:0]  , ect_pstate_am_e}				),
  .dout({rs1_x_rs2_cmp_e_[1:0] ,     pstate_am_e_}				));

exu_edp_dp_nand_macro__ports_3__stack_72c__width_3	i_mask_nand3		 (
  .din0({rs1_x_rs2_cmp_e[1]    , ect_pstate_am_e       ,     pstate_am_e_    }	),
  .din1({rs1_x_rs2_cmp_e[0]    , rs1_x_rs2_cmp_e[0]    , rs1_x_rs2_cmp_e_[1] }	),
  .din2({ect_rm_early_sel_e[5] , ect_rm_early_sel_e[5] , ect_rm_early_sel_e[5]}	),
  .dout({edge_lr_nand3_[1]     , edge_lr_nand3_[0]     , edge_l_nand3_       }	));

exu_edp_dp_nand_macro__ports_2__stack_72c__width_3	i_mask_nand2		 (
  .din0({edge_lr_nand3_[1]     , rs1_x_rs2_cmp_e_[0]   , edge_l_nand3_       }	),
  .din1({edge_lr_nand3_[0]     , ect_rm_early_sel_e[5] , edge_l_nand2_       }	),
  .dout({edge_lr_sel_e         , edge_l_nand2_         , edge_l_sel_e        }	));


exu_edp_dp_cmp_macro__width_64	i_mbist_cmp0		 (
  .din0 ({8{ecc_mbist_write_data_p4[7:0]}}					),
  .din1 ( edp_rs3_data_e[63:0]							),
  .dout ( cmp_mbi_irf_fail_[0]							));


exu_edp_dp_cmp_macro__width_8	i_mbist_cmp1		 (
  .din0 ( ecc_mbist_write_data_p4[7:0]						),
  .din1 ( edp_rs3_ecc_e[7:0]							),
  .dout ( cmp_mbi_irf_fail_[1]							));


exu_edp_dp_buff_macro__dbuff_32x__stack_72c__width_2	i_mbist_buf		 (
  .din  ( cmp_mbi_irf_fail_[1:0]						),
  .dout ( exu_mbi_irf_fail_[1:0]						));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Bypass       !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Result Mux/FF *!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!

exu_edp_dp_buff_macro__dbuff_32x__stack_72c__width_1	i_rm_mux_buf		 (
  .din  ( edp_rs3_data_e[47]					),
  .dout ( rs3_data_e_b47_buf					));

exu_edp_dp_mux_macro__mux_aonpe__ports_7__stack_72c__width_64	i_rm_mux_early		 (
  .din0 ( logical_data_e[63:0]			 		),	// Logical
  .din1 ({{31{1'b0}},array_res_e[32:0]}				),
  .din2 ({exu_rs1_data_e[0],exu_y_data_e[31:1],{32{1'b0}}}	),	// MULScc
  .din3 ({{17{rs3_data_e_b47_buf}} , edp_rs3_data_e[46:0]}	),	// CALL & JUMP - w/ pstate_am=0 + pc extension
  .din4 ({{32{1'b0}}               , edp_rs3_data_e[31:0]}	),	// CALL & JUMP - w/ pstate_am=1
  .din5 ({{56{1'b0}},ect_edge_lrmask_e[7:0]}			),
  .din6 ({{56{1'b0}},ect_edge_lmask_e[7:0]}			),
  .sel0 ( ect_rm_early_sel_e[0]		 			),
  .sel1 ( ect_rm_early_sel_e[1]		 			),
  .sel2 ( ect_rm_early_sel_e[2]		 			),
  .sel3 ( ect_rm_early_sel_e[3]					),
  .sel4 ( ect_rm_early_sel_e[4]					),
  .sel5 ( edge_lr_sel_e						),
  .sel6 ( edge_l_sel_e						),
  .dout ( early_rd_data[63:0]		 			));


exu_edp_dp_mux_macro__mux_pgpe__ports_4__stack_72c__width_64	i_rm_mux_late		 (
  .muxtst (tcu_muxtest_rep0				),
  .din0 ( sub_data_e[63:0]				),	// Sub
  .din1 ({add_data_e[63:3],add_clip[2:0]}		),	// Add
  .din2 ( shifter_data_e[63:0]		 		),	// Shift
  .din3 ( early_rd_data[63:0]		 		),	// Early Mux
  .sel0 ( ect_rm_late_sel_e[0]		 		),
  .sel1 ( ect_rm_late_sel_e[1]		 		),
  .sel2 ( ect_rm_late_sel_e[2]		 		),
  .dout ( rd_data_e[63:0]				),
  .test(test));


exu_edp_dp_msff_macro__stack_72c__width_67	i_rm_ff_m		 (
  .scan_in(i_rm_ff_m_scanin),
  .scan_out(i_rm_ff_m_scanout),
  .clk ( l2clk						),
  .en  ( ect_ex_emb_clken				),
  .din ({addsub_inc[2:0]    , rd_data_e[63:0]}		),
  .dout({addsub_data_m[2:0] , rd_ff_m[63:0]}		),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

  assign exu_gsr_data_m[31:0]	= {rd_ff_m[31:3],addsub_data_m[2:0]};
  assign edp_rd_ff_m[63:47]	= rd_ff_m[63:47];


exu_edp_dp_msff_macro__minbuff_1__stack_72c__width_64	i_rm_ff_b		 (
  .scan_in(i_rm_ff_b_scanin),
  .scan_out(i_rm_ff_b_scanout),
  .clk ( l2clk						),
  .en  ( ect_ex_emb_clken				),
  .din ( rd_ff_m[63:0]					),
  .dout( rd_ff_b[63:0]					),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

  assign exu_trap_number_b[7:0]	= rd_ff_b[7:0];


exu_edp_dp_msff_macro__mux_aope__ports_3__stack_72c__width_64	i_rm_ff_w		 (
  .scan_in(i_rm_ff_w_scanin),
  .scan_out(i_rm_ff_w_scanout),
  .clk ( l2clk						),
  .en  ( ect_tg_clken					),
  .din0({8{mbi_write_data_p1[7:0]}	}		),	// MBIST
  .din1( fgu_exu_result_fx5[63:0]			),	// Float point integer result
  .din2( rd_ff_b[63:0]					),	// Normal EXU data
  .sel0( ect_mbist_sel					),
  .sel1( fgu_exu_w_vld_fx5				),
  .dout(     rd_ff_w[63:0]				),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_64	i_rm_buf_w		 (
  .din (     rd_ff_w[63:0]				),
  .dout( edp_rd_ff_w[63:0]				));


exu_edp_dp_msff_macro__minbuff_1__stack_72c__width_64	i_rm_ff_w_plus1		 (
  .scan_in(i_rm_ff_w_plus1_scanin),
  .scan_out(i_rm_ff_w_plus1_scanout),
  .clk ( l2clk						),
  .en  ( ect_tg_clken					),
  .din ( edp_rd_ff_w[63:0]				),
  .dout( rd_ff_w_plus1[63:0]				),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


exu_edp_dp_msff_macro__stack_72c__width_66	i_rm_ff_w2		 (
  .scan_in(i_rm_ff_w2_scanin),
  .scan_out(i_rm_ff_w2_scanout),
  .clk ( l2clk							),
  .en  ( ect_tg_clken						),
  .din ({ibe_trap_d , ibe_trap_e , lsu_exu_ld_data_b[63:0]}	),	// Load Data
  .dout({ibe_trap_e , ibp_m      ,    rd_ff_w2[63:0]}		),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_65	i_rm_buf_w2		 (
  .din ({ibp_m     ,    rd_ff_w2[63:0]}				),
  .dout({exu_ibp_m , edp_rd_ff_w2[63:0]}			));


exu_edp_dp_msff_macro__minbuff_1__stack_72c__width_64	i_rm_ff_w2_plus1		 (
  .scan_in(i_rm_ff_w2_plus1_scanin),
  .scan_out(i_rm_ff_w2_plus1_scanout),
  .clk ( l2clk						),
  .en  ( ect_tg_clken					),
  .din ( edp_rd_ff_w2[63:0]				),	// Load Data Delayed
  .dout(     rd_ff_w2_plus1[63:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Result Mux/FF *!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Logicals     !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


exu_edp_dp_buff_macro__stack_72c__width_8	i_lg_buf_sel		 (
  .din ({2{logic_sel_e[3:0]}			       }),
  .dout({logic_hsel_e[3:0],logic_lsel_e[3:0]	       }));


exu_edp_dp_inv_macro__stack_72c__width_64	i_lg_inv_rs1		 (
  .din ( exu_rs1_data_e[63:0]				),
  .dout( rs1_data_e_[63:0]				));

exu_edp_dp_inv_macro__stack_72c__width_64	i_lg_inv_rs2		 (
  .din ( exu_rs2_data_e[63:0]				),
  .dout( log_rs2_data_e_[63:0]				));


exu_edp_dp_nand_macro__ports_3__stack_72c__width_64	i_lg_nand1_11		 (
  .din0( exu_rs1_data_e[63:0]				),
  .din1( exu_rs2_data_e[63:0]				),
  .din2({{32{logic_hsel_e[3]}}, {32{logic_lsel_e[3]}}  }),
  .dout( logical_11_[63:0]				));

exu_edp_dp_nand_macro__ports_3__stack_72c__width_64	i_lg_nand1_10		 (
  .din0( exu_rs1_data_e[63:0]				),
  .din1( log_rs2_data_e_[63:0]				),
  .din2({{32{logic_hsel_e[2]}}, {32{logic_lsel_e[2]}}  }),
  .dout( logical_10_[63:0]				));

exu_edp_dp_nand_macro__ports_3__stack_72c__width_64	i_lg_nand1_01		 (
  .din0( rs1_data_e_[63:0]				),
  .din1( exu_rs2_data_e[63:0]				),
  .din2({{32{logic_hsel_e[1]}}, {32{logic_lsel_e[1]}}  }),
  .dout( logical_01_[63:0]				));

exu_edp_dp_nand_macro__ports_3__stack_72c__width_64	i_lg_nand1_00		 (
  .din0( rs1_data_e_[63:0]				),
  .din1( log_rs2_data_e_[63:0]				),
  .din2({{32{logic_hsel_e[0]}}, {32{logic_lsel_e[0]}}  }),
  .dout( logical_00_[63:0]				));


exu_edp_dp_nand_macro__ports_4__stack_72c__width_64	i_lg_nand2		 (
  .din0( logical_00_[63:0]				),
  .din1( logical_01_[63:0]				),
  .din2( logical_10_[63:0]				),
  .din3( logical_11_[63:0]				),
  .dout( logical_data_e[63:0]				));


exu_edp_dp_buff_macro__stack_72c__width_2	i_lg_buf_data		 (
  .din ({logical_data_e[63],logical_data_e[31]}		),
  .dout({edp_logical_data_e_b63,edp_logical_data_e_b31}	));


exu_edp_dp_zero_macro__width_32	i_lg_cmp_upper		 (
  .din ( logical_data_e[63:32]				),
  .dout( edp_lg_zdetect_e[1]				));

exu_edp_dp_zero_macro__width_32	i_lg_cmp_lower		 (
  .din ( logical_data_e[31:0]				),
  .dout( edp_lg_zdetect_e[0]				));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Logicals     !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Shift        !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//
//  Operation    sel_rshift   sel_lshift   sel_rax   sel_ra   sel_rshiftx   sel_llx   sel_32shift
//  -----------|------------|------------|---------|--------|-------------|---------|------------
//     SLL     |     0      |     1      |    0    |   0    |    0        |    0    |     1
//     SLX     |     0      |     1      |    0    |   0    |    0        |    1    |     0
//     SRAX?   |     1      |     0      |    1    |   0    |    1        |    0    |     0
//     SRA     |     1      |     0      |    0    |   1    |    0        |    0    |     1
//     SRLX?   |     1      |     0      |    0    |   0    |    1        |    0    |     0
//     SRL     |     1      |     0      |    0    |   0    |    0        |    0    |     1
//      -      |     1      |     1      |    x    |   x    |    x        |    x    |     x
//      0 **   |     0      |     0      |    x    |   x    |    x        |    x    |     x
//
// ** This will only hold for a dynamic implementation

exu_edp_dp_msff_macro__left_32__stack_72c__width_28	i_misc_ff		 (
  .scan_in(i_misc_ff_scanin),
  .scan_out(i_misc_ff_scanout),
  .clk  ( l2clk									),
  .en   ( ect_tg_clken								),
  .din  ({add_data_e[63:47]    , ect_shift_sel_d[6:0] , ect_logic_sel_d[3:0]}	),
  .dout ({edp_address_m[63:47] ,     shift_sel_e[6:0] ,     logic_sel_e[3:0]}	),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


	assign sh_sel_rshift	= shift_sel_e[5];
	assign sh_sel_lshift	= shift_sel_e[4];
	assign sh_sel_rax	= shift_sel_e[3];
	assign sh_sel_ra	= shift_sel_e[2];
	assign sh_sel_rshiftx	= shift_sel_e[1];
	assign sh_sel_llx	= shift_sel_e[0];


exu_edp_dp_buff_macro__stack_72c__width_64	i_sh_buf_rs1		 (
  .din ( rs1_data_e[63:0]			),
  .dout( sh_rs1_buf[63:0]		 	));

exu_edp_dp_inv_macro__stack_72c__width_2	i_sh_inv_rs1		 (
  .din ({rs1_data_e[63] , rs1_data_e[31]}	),
  .dout({sh_rs1_63_     , sh_rs1_31_	      	}));


// *** MASK MUX ***


// The MASK MUXes are built using AO muxes with the highest number of ports being 3:1


// assign rs1z7[7:0] = {rs1[00],{7{1'b0}}};
//
//                                                     70:64         63:56         55:48         47:40         39:32     
// assign mask_mux00[70:32] = ({39{sel_rshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_lshift }} & {  rs1[63:57] ,  rs1[56:49] ,  rs1[48:41] ,  rs1[40:33] ,  rs1[32:25]  }) |
//                            ({39{sel_rshiftx}} & {  {7{1'b0}}  ,  rs1[63:56] ,  rs1[55:48] ,  rs1[47:40] ,  rs1[39:32]  }) |
//                            ({39{sel_ra     }} & { {7{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}} }) |
//                            ({39{sel_rax    }} & { {7{rs1[63]}},  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_llx    }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });

//                                                     31:24         23:16         15:08         07:00
// assign mask_mux00[31:00] = ({32{sel_rshift }} & {  rs1[31:24] ,  rs1[23:16] ,  rs1[15:08] ,  rs1[07:00] }) |
//                            ({32{sel_lshift }} & {  rs1[24:17] ,  rs1[16:09] ,  rs1[08:01] ,  rs1z7[7:0] }) |
//                            ({32{sel_rshiftx}} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_ra     }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_rax    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_llx    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  });


exu_edp_dp_buff_macro__width_5	i_sh_buf00		 (
  .din ({sh_sel_rshift,
         sh_sel_lshift,
         sh_sel_rshiftx,
         sh_sel_ra,
         sh_sel_rax			}),
  .dout({sel_rshift00,
         sel_lshift00,
         sel_rshiftx00,
         sel_ra00,
         sel_rax00			}));

exu_edp_dp_inv_macro__stack_72c__width_2	i_sh_inv00		 (
  .din ({sh_rs1_63_    ,sh_rs1_31_	}),
  .dout({sh_rs1_00_63  ,sh_rs1_00_31	}));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_7	i_sh_mux00_88		 (
  .din0( sh_rs1_buf[63:57]		 ),
  .din1({ 7{sh_rs1_00_31}		}),
  .din2({ 7{sh_rs1_00_63}		}),
  .sel0( sel_lshift00         		 ),
  .sel1( sel_ra00             		 ),
  .sel2( sel_rax00            		 ),
  .dout( mask_mux00[70:64]    		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_32	i_sh_mux00_74		 (
  .din0( sh_rs1_buf[56:25]		 ),
  .din1( sh_rs1_buf[63:32]		 ),
  .din2({32{sh_rs1_00_31}		}),
  .sel0( sel_lshift00			 ),
  .sel1( sel_rshiftx00			 ),
  .sel2( sel_ra00			 ),
  .dout( mask_mux00[63:32]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_32	i_sh_mux00_30		 (
  .din0( sh_rs1_buf[31:0]           	 ),
  .din1({sh_rs1_buf[24:0],{7{1'b0}}	}),
  .sel0( sel_rshift00			 ),
  .sel1( sel_lshift00			 ),
  .dout( mask_mux00[31:0]		 ));


//                                                     70:64         63:56         55:48         47:40         39:32     
// assign mask_mux08[70:32] = ({39{sel_rshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_lshift }} & {  rs1[55:49] ,  rs1[48:41] ,  rs1[40:33] ,  rs1[32:25] ,  rs1[24:17]  }) |
//                            ({39{sel_rshiftx}} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  rs1[63:56] ,  rs1[55:48] ,  rs1[47:40]  }) |
//                            ({39{sel_ra     }} & { {7{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}} }) |
//                            ({39{sel_rax    }} & { {7{rs1[63]}}, {8{rs1[63]}},  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_llx    }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });

//                                                     31:24         23:16         15:08         07:00
// assign mask_mux08[31:00] = ({32{sel_rshift }} & {  {8{1'b0}}  ,  rs1[31:24] ,  rs1[23:16] ,  rs1[15:08] }) |
//                            ({32{sel_lshift }} & {  rs1[16:09] ,  rs1[08:01] ,  rs1z7[7:0] ,  {8{1'b0}}  }) |
//                            ({32{sel_rshiftx}} & {  rs1[39:32] ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_ra     }} & { {8{rs1[31]}},  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_rax    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_llx    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  });


exu_edp_dp_buff_macro__width_5	i_sh_buf08		 (
  .din ({sh_sel_rshift,
         sh_sel_lshift,
         sh_sel_rshiftx,
         sh_sel_ra,
         sh_sel_rax		}),
  .dout({sel_rshift08,
         sel_lshift08,
         sel_rshiftx08,
         sel_ra08,
         sel_rax08			}));

exu_edp_dp_inv_macro__stack_72c__width_2	i_sh_inv08		 (
  .din ({sh_rs1_63_    ,sh_rs1_31_	}),
  .dout({sh_rs1_08_63  ,sh_rs1_08_31	}));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_15	i_sh_mux08_87		 (
  .din0( sh_rs1_buf[55:41]		 ),
  .din1({15{sh_rs1_08_31}		}),
  .din2({15{sh_rs1_08_63}		}),
  .sel0( sel_lshift08			 ),
  .sel1( sel_ra08			 ),
  .sel2( sel_rax08			 ),
  .dout( mask_mux08[70:56]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_32	i_sh_mux08_63		 (
  .din0( sh_rs1_buf[40:9]		 ),
  .din1( sh_rs1_buf[63:32]		 ),
  .din2({32{sh_rs1_08_31}		}),
  .sel0( sel_lshift08			 ),
  .sel1( sel_rshiftx08			 ),
  .sel2( sel_ra08			 ),
  .dout( mask_mux08[55:24]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_16	i_sh_mux08_21		 (
  .din0( sh_rs1_buf[31:16]		 ),
  .din1({sh_rs1_buf[8:0],{7{1'b0}}}),
  .sel0( sel_rshift08			 ),
  .sel1( sel_lshift08			 ),
  .dout( mask_mux08[23:8]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_8	i_sh_mux08_00		 (
  .din0( sh_rs1_buf[15:8]		 ),
  .din1({8{1'b0}			}),
  .sel0( sel_rshift08			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux08[7:0]		 ));

 
//                                                     70:64         63:56         55:48         47:40         39:32     
// assign mask_mux16[70:32] = ({39{sel_rshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_lshift }} & {  rs1[47:41] ,  rs1[40:33] ,  rs1[32:25] ,  rs1[24:17] ,  rs1[16:09]  }) |
//                            ({39{sel_rshiftx}} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  rs1[63:56] ,  rs1[55:48]  }) |
//                            ({39{sel_ra     }} & { {7{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}} }) |
//                            ({39{sel_rax    }} & { {7{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}},  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_llx    }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });

//                                                     31:24         23:16         15:08         07:00
// assign mask_mux16[31:00] = ({32{sel_rshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  rs1[31:24] ,  rs1[23:16] }) |
//                            ({32{sel_lshift }} & {  rs1[08:01] ,  rs1z7[7:0] ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_rshiftx}} & {  rs1[47:40] ,  rs1[39:32] ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_ra     }} & { {8{rs1[31]}}, {8{rs1[31]}},  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_rax    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_llx    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  });


exu_edp_dp_buff_macro__width_5	i_sh_buf16		 (
  .din ({sh_sel_rshift,
         sh_sel_lshift,
         sh_sel_rshiftx,
         sh_sel_ra,
         sh_sel_rax		}),
  .dout({sel_rshift16,
         sel_lshift16,
         sel_rshiftx16,
         sel_ra16,
         sel_rax16			}));

exu_edp_dp_inv_macro__stack_72c__width_2	i_sh_inv16		 (
  .din ({sh_rs1_63_    ,sh_rs1_31_	}),
  .dout({sh_rs1_16_63  ,sh_rs1_16_31	}));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_23	i_sh_mux16_86		 (
  .din0( sh_rs1_buf[47:25]		 ),
  .din1({23{sh_rs1_16_31}		}),
  .din2({23{sh_rs1_16_63}		}),
  .sel0( sel_lshift16			 ),
  .sel1( sel_ra16			 ),
  .sel2( sel_rax16			 ),
  .dout( mask_mux16[70:48]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_32	i_sh_mux16_52		 (
  .din0({sh_rs1_buf[24:0],{7{1'b0}}	}),
  .din1( sh_rs1_buf[63:32]		 ),
  .din2({32{sh_rs1_16_31}		}),
  .sel0( sel_lshift16			 ),
  .sel1( sel_rshiftx16			 ),
  .sel2( sel_ra16			 ),
  .dout( mask_mux16[47:16]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_16	i_sh_mux16_00		 (
  .din0( sh_rs1_buf[31:16]		 ),
  .din1({16{1'b0}			}),
  .sel0( sel_rshift16			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux16[15:0]		 ));

 
//                                                     70:64         63:56         55:48         47:40         39:32     
// assign mask_mux24[70:32] = ({39{sel_rshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_lshift }} & {  rs1[39:33] ,  rs1[32:25] ,  rs1[24:17] ,  rs1[16:09] ,  rs1[08:01]  }) |
//                            ({39{sel_rshiftx}} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  rs1[63:56]  }) |
//                            ({39{sel_ra     }} & { {7{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}} }) |
//                            ({39{sel_rax    }} & { {7{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}},  {8{1'b0}}   }) |
//                            ({39{sel_llx    }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });

//                                                     31:24         23:16         15:08         07:00
// assign mask_mux24[31:00] = ({32{sel_rshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  rs1[31:24] }) |
//                            ({32{sel_lshift }} & {  rs1z7[7:0] ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_rshiftx}} & {  rs1[55:48] ,  rs1[47:40] ,  rs1[39:32] ,  {8{1'b0}}  }) |
//                            ({32{sel_ra     }} & { {8{rs1[31]}}, {8{rs1[31]}}, {8{rs1[31]}},  {8{1'b0}}  }) |
//                            ({32{sel_rax    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  }) |
//                            ({32{sel_llx    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  });


exu_edp_dp_buff_macro__width_5	i_sh_buf24		 (
  .din ({sh_sel_rshift,
         sh_sel_lshift,
         sh_sel_rshiftx,
         sh_sel_ra,
         sh_sel_rax		}),
  .dout({sel_rshift24,
         sel_lshift24,
         sel_rshiftx24,
         sel_ra24,
         sel_rax24			}));

exu_edp_dp_inv_macro__stack_72c__width_2	i_sh_inv24		 (
  .din ({sh_rs1_63_    ,sh_rs1_31_	}),
  .dout({sh_rs1_24_63  ,sh_rs1_24_31	}));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_31	i_sh_mux24_85		 (
  .din0( sh_rs1_buf[39:9]		 ),
  .din1({31{sh_rs1_24_31}		}),
  .din2({31{sh_rs1_24_63}		}),
  .sel0( sel_lshift24			 ),
  .sel1( sel_ra24			 ),
  .sel2( sel_rax24			 ),
  .dout( mask_mux24[70:40]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_16	i_sh_mux24_43		 (
  .din0({sh_rs1_buf[8:0],{7{1'b0}}}),
  .din1( sh_rs1_buf[63:48]		 ),
  .din2({16{sh_rs1_24_31}		}),
  .sel0( sel_lshift24			 ),
  .sel1( sel_rshiftx24			 ),
  .sel2( sel_ra24			 ),
  .dout( mask_mux24[39:24]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_16	i_sh_mux24_21		 (
  .din0( sh_rs1_buf[47:32]		 ),
  .din1({16{sh_rs1_24_31}		}),
  .sel0( sel_rshiftx24			 ),
  .sel1( sel_ra24			 ),
  .dout( mask_mux24[23:8]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_8	i_sh_mux24_00		 (
  .din0( sh_rs1_buf[31:24]		 ),
  .din1({8{1'b0}			}),
  .sel0( sel_rshift24			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux24[7:0]		 ));

 
//                                                     70:64         63:56         55:48         47:40         39:32     
// assign mask_mux32[70:32] = ({39{sel_rshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_lshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_rshiftx}} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_ra     }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_rax    }} & { {7{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}} }) |
//                            ({39{sel_llx    }} & {  rs1[31:25] ,  rs1[24:17] ,  rs1[16:09] ,  rs1[08:01] ,  rs1z7[7:0]  });

//                                                     31:24         23:16         15:08         07:00
// assign mask_mux32[31:00] = ({32{sel_rshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_lshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_rshiftx}} & {  rs1[63:56] ,  rs1[55:48] ,  rs1[47:40] ,  rs1[39:32]  }) |
//                            ({32{sel_ra     }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_rax    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_llx    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });


exu_edp_dp_buff_macro__width_3	i_sh_buf32		 (
  .din ({sh_sel_rshiftx,
         sh_sel_rax,
         sh_sel_llx		}),
  .dout({sel_rshiftx32,
         sel_rax32,
         sel_llx32			}));

exu_edp_dp_inv_macro__stack_72c__width_1	i_sh_inv32		 (
  .din ( sh_rs1_63_			 ),
  .dout( sh_rs1_32_63			 ));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_39	i_sh_mux32_84		 (
  .din0({39{sh_rs1_32_63}		}),
  .din1({sh_rs1_buf[31:0],{7{1'b0}}	}),
  .sel0( sel_rax32			 ),
  .sel1( sel_llx32			 ),
  .dout( mask_mux32[70:32]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_32	i_sh_mux32_30		 (
  .din0( sh_rs1_buf[63:32]		 ),
  .din1({32{1'b0}			}),
  .sel0( sel_rshiftx32			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux32[31:0]		 ));

 
//                                                     70:64         63:56         55:48         47:40         39:32     
// assign mask_mux40[70:32] = ({39{sel_rshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_lshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_rshiftx}} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_ra     }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_rax    }} & { {7{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}} }) |
//                            ({39{sel_llx    }} & {  rs1[23:17] ,  rs1[16:09] ,  rs1[08:01] ,  rs1z7[7:0] ,  {8{1'b0}}   });

//                                                     31:24         23:16         15:08         07:00
// assign mask_mux40[31:00] = ({32{sel_rshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_lshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_rshiftx}} & {  {8{1'b0}}  ,  rs1[63:56] ,  rs1[55:48] ,  rs1[47:40]  }) |
//                            ({32{sel_ra     }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_rax    }} & { {8{rs1[63]}},  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_llx    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });


exu_edp_dp_buff_macro__width_3	i_sh_buf40		 (
  .din ({sh_sel_rshiftx,
         sh_sel_rax,
         sh_sel_llx		}),
  .dout({sel_rshiftx40,
         sel_rax40,
         sel_llx40			}));

exu_edp_dp_inv_macro__stack_72c__width_1	i_sh_inv40		 (
  .din ( sh_rs1_63_			 ),
  .dout( sh_rs1_40_63			 ));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_31	i_sh_mux40_85		 (
  .din0({31{sh_rs1_40_63}		}),
  .din1({sh_rs1_buf[23:0],{7{1'b0}}	}),
  .sel0( sel_rax40			 ),
  .sel1( sel_llx40			 ),
  .dout( mask_mux40[70:40]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_16	i_sh_mux40_43		 (
  .din0({16{sh_rs1_40_63}		}),
  .din1({16{1'b0}			}),
  .sel0( sel_rax40			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux40[39:24]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_24	i_sh_mux40_20		 (
  .din0( sh_rs1_buf[63:40]		 ),
  .din1({24{1'b0}			}),
  .sel0( sel_rshiftx40			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux40[23:0]		 ));

 
//                                                     70:64         63:56         55:48         47:40         39:32     
// assign mask_mux48[70:32] = ({39{sel_rshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_lshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_rshiftx}} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_ra     }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_rax    }} & { {7{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}} }) |
//                            ({39{sel_llx    }} & {  rs1[15:09] ,  rs1[08:01] ,  rs1z7[7:0] ,  {8{1'b0}}  ,  {8{1'b0}}   });

//                                                     31:24         23:16         15:08         07:00
// assign mask_mux48[31:00] = ({32{sel_rshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_lshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_rshiftx}} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  rs1[63:56] ,  rs1[55:48]  }) |
//                            ({32{sel_ra     }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_rax    }} & { {8{rs1[63]}}, {8{rs1[63]}},  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_llx    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });


exu_edp_dp_buff_macro__width_3	i_sh_buf48		 (
  .din ({sh_sel_rshiftx,
         sh_sel_rax,
         sh_sel_llx		}),
  .dout({sel_rshiftx48,
         sel_rax48,
         sel_llx48			}));

exu_edp_dp_inv_macro__stack_72c__width_1	i_sh_inv48		 (
  .din ( sh_rs1_63_			 ),
  .dout( sh_rs1_48_63			 ));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_23	i_sh_mux48_86		 (
  .din0({23{sh_rs1_48_63}		}),
  .din1({sh_rs1_buf[15:0],{7{1'b0}}	}),
  .sel0( sel_rax48			 ),
  .sel1( sel_llx48			 ),
  .dout( mask_mux48[70:48]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_32	i_sh_mux48_52		 (
  .din0({32{sh_rs1_48_63}		}),
  .din1({32{1'b0}			}),
  .sel0( sel_rax48			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux48[47:16]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_16	i_sh_mux48_10		 (
  .din0( sh_rs1_buf[63:48]		 ),
  .din1({16{1'b0}			}),
  .sel0( sel_rshiftx48			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux48[15:0]		 ));

 
//                                                     70:64         63:56         55:48         47:40         39:32     
// assign mask_mux56[70:32] = ({39{sel_rshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_lshift }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_rshiftx}} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_ra     }} & {  {7{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({39{sel_rax    }} & { {7{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}} }) |
//                            ({39{sel_llx    }} & {  rs1[07:01] ,  rs1z7[7:0] ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });

//                                                     31:24         23:16         15:08         07:00
// assign mask_mux56[31:00] = ({32{sel_rshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_lshift }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_rshiftx}} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  rs1[63:56]  }) |
//                            ({32{sel_ra     }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   }) |
//                            ({32{sel_rax    }} & { {8{rs1[63]}}, {8{rs1[63]}}, {8{rs1[63]}},  {8{1'b0}}   }) |
//                            ({32{sel_llx    }} & {  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}  ,  {8{1'b0}}   });


exu_edp_dp_buff_macro__width_3	i_sh_buf56		 (
  .din ({sh_sel_rshiftx,
         sh_sel_rax,
         sh_sel_llx		}),
  .dout({sel_rshiftx56,
         sel_rax56,
         sel_llx56			}));

exu_edp_dp_inv_macro__stack_72c__width_1	i_sh_inv56		 (
  .din ( sh_rs1_63_			 ),
  .dout( sh_rs1_56_63			 ));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_15	i_sh_mux56_87		 (
  .din0({15{sh_rs1_56_63}		}),
  .din1({sh_rs1_buf[7:0],{7{1'b0}}	}),
  .sel0( sel_rax56 			 ),
  .sel1( sel_llx56			 ),
  .dout( mask_mux56[70:56]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_48	i_sh_mux56_61		 (
  .din0({48{sh_rs1_56_63}		}),
  .din1({48{1'b0}			}),
  .sel0( sel_rax56			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux56[55:8]		 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_8	i_sh_mux56_10		 (
  .din0( sh_rs1_buf[63:56]		 ),
  .din1({8{1'b0}			}),
  .sel0( sel_rshiftx56			 ),
  .sel1( 1'b0				 ),
  .dout( mask_mux56[7:0]		 ));


// *** 1st Level Shifter (right by 8) ***


// If timing requires, we could use a 64/32 pin to replace the 2-way OR
// assign rs2_5     = rs2[5] & (sel_rshiftx | sel_llx);

exu_edp_dp_and_macro__dinv_16x__dnand_6x__ports_2__width_1	i_sh_sh8_mux5		 (
  .din0( exu_rs2_data_e[5]		 ),
  .din1( shift_sel_e[6]                  ),
  .dout( rs2_5				 ));


// assign sel1_sh00 = ~rs2_5 & ~rs2[4] & ~rs2[3];
// assign sel1_sh08 = ~rs2_5 & ~rs2[4] &  rs2[3];
// assign sel1_sh16 = ~rs2_5 &  rs2[4] & ~rs2[3];
// assign sel1_sh24 = ~rs2_5 &  rs2[4] &  rs2[3];
// assign sel1_sh32 =  rs2_5 & ~rs2[4] & ~rs2[3];
// assign sel1_sh40 =  rs2_5 & ~rs2[4] &  rs2[3];
// assign sel1_sh48 =  rs2_5 &  rs2[4] & ~rs2[3];
// assign sel1_sh56 =  rs2_5 &  rs2[4] &  rs2[3];
//
// assign sht_by8[70:00]    = ({71{sel1_sh00}} & mask_mux00[70:00]) |
//                            ({71{sel1_sh08}} & mask_mux08[70:00]) |
//                            ({71{sel1_sh16}} & mask_mux16[70:00]) |
//                            ({71{sel1_sh24}} & mask_mux24[70:00]) |
//                            ({71{sel1_sh32}} & mask_mux32[70:00]) |
//                            ({71{sel1_sh40}} & mask_mux40[70:00]) |
//                            ({71{sel1_sh48}} & mask_mux48[70:00]) |
//                            ({71{sel1_sh56}} & mask_mux56[70:00]);

exu_edp_dp_buff_macro__dbuff_48x__width_1	tst_mux_rep0		 (
  .din ( tcu_muxtest			 ),
  .dout( tcu_muxtest_rep0		 ));


exu_edp_dp_mux_macro__mux_aodec__ports_8__stack_72c__width_71	i_sh_sh8_mux		 (
  .din0 ( mask_mux00[70:0]		 ),
  .din1 ( mask_mux08[70:0]		 ),
  .din2 ( mask_mux16[70:0]		 ),
  .din3 ( mask_mux24[70:0]		 ),
  .din4 ( mask_mux32[70:0]		 ),
  .din5 ( mask_mux40[70:0]		 ),
  .din6 ( mask_mux48[70:0]		 ),
  .din7 ( mask_mux56[70:0]		 ),
  .sel  ({rs2_5,exu_rs2_data_e[4:3]	}),
  .dout ( sht_by8[70:0]		 ));

exu_edp_dp_buff_macro__stack_72c__width_71	i_sh_sh8_buf		 (
  .din  ( sht_by8[70:0]			 ),
  .dout ( sht_by8_buf[70:0]		 ));

 
// *** 2nd Level Shifter (by 1) ***

// assign sel2_sh0  = ( sel_rshift & ~rs2[2] & ~rs2[1] & ~rs2[0]) |
//                    ( sel_lshift &  rs2[2] &  rs2[1] &  rs2[0]);
// 
// assign sel2_sh1  = ( sel_rshift & ~rs2[2] & ~rs2[1] &  rs2[0]) |
//                    ( sel_lshift &  rs2[2] &  rs2[1] & ~rs2[0]);
// 
// assign sel2_sh2  = ( sel_rshift & ~rs2[2] &  rs2[1] & ~rs2[0]) |
//                    ( sel_lshift &  rs2[2] & ~rs2[1] &  rs2[0]);
// 
// assign sel2_sh3  = ( sel_rshift & ~rs2[2] &  rs2[1] &  rs2[0]) |
//                    ( sel_lshift &  rs2[2] & ~rs2[1] & ~rs2[0]);
// 
// assign sel2_sh4  = ( sel_rshift &  rs2[2] & ~rs2[1] & ~rs2[0]) |
//                    ( sel_lshift & ~rs2[2] &  rs2[1] &  rs2[0]);
// 
// assign sel2_sh5  = ( sel_rshift &  rs2[2] & ~rs2[1] &  rs2[0]) |
//                    ( sel_lshift & ~rs2[2] &  rs2[1] & ~rs2[0]);
// 
// assign sel2_sh6  = ( sel_rshift &  rs2[2] &  rs2[1] & ~rs2[0]) |
//                    ( sel_lshift & ~rs2[2] & ~rs2[1] &  rs2[0]);
// 
// assign sel2_sh7  = ( sel_rshift &  rs2[2] &  rs2[1] &  rs2[0]) |
//                    ( sel_lshift & ~rs2[2] & ~rs2[1] & ~rs2[0]);
// 
// 
// assign shifter_out_e0[63:0] = ({64{sel2_sh0}} & sht_by8[63:00]) |
//                               ({64{sel2_sh1}} & sht_by8[64:01]) |
//                               ({64{sel2_sh2}} & sht_by8[65:02]) |
//                               ({64{sel2_sh3}} & sht_by8[66:03]) |
//                               ({64{sel2_sh4}} & sht_by8[67:04]) |
//                               ({64{sel2_sh5}} & sht_by8[68:05]) |
//                               ({64{sel2_sh6}} & sht_by8[69:06]) |
//                               ({64{sel2_sh7}} & sht_by8[70:07]);

exu_edp_dp_inv_macro__dinv_6x__width_3	i_sh_rs2_inv		 (
  .din ( exu_rs2_data_e[2:0]		 ),
  .dout( rs2_[2:0]			 ));

exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3	i_sh_rs2l_mux		 (
  .din0( exu_rs2_data_e[2:0]		 ),
  .din1( rs2_[2:0]			 ),
  .sel0( sh_sel_rshift			 ),
  .sel1( sh_sel_lshift			 ),
  .dout( rs2_mux[2:0]			 ));

exu_edp_dp_mux_macro__mux_aodec__ports_8__stack_72c__width_64	i_sh_sh1_mux		 (
  .din0 ( sht_by8_buf[63:0]		 ),
  .din1 ( sht_by8_buf[64:1]		 ),
  .din2 ( sht_by8_buf[65:2]		 ),
  .din3 ( sht_by8_buf[66:3]		 ),
  .din4 ( sht_by8_buf[67:4]		 ),
  .din5 ( sht_by8_buf[68:5]		 ),
  .din6 ( sht_by8_buf[69:6]		 ),
  .din7 ( sht_by8_buf[70:7]		 ),
  .sel  ( rs2_mux[2:0]			 ),
  .dout ( shifter_data_e[63:0]		 ));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Shift        !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Add/Sub      !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


exu_edp_dp_inv_macro__stack_72c__width_64	i_as_inv_rs2		 (
  .din ( rs2_data_e[63:0]				 ),
  .dout( rs2_data_e_[63:0]				 ));


exu_edp_dp_cla_macro__width_64	i_as_cla		 (
  .din0( rs1_data_e[63:0]				 ),
  .din1( rs2_data_e_[63:0]				 ),
  .cin ( ect_as_cin_e					 ),
  .cout( edp_sub_cout64_e				 ),
  .dout( sub_data_e[63:0]				 ));


// NOTE : Since the 8 LSB's from the CLA are faster than the remaining bit,
//        this ALIGNADDRESS clipping should not be in the critical path.
//        If that is not the case, then add an additional port on to the
//        late result mux with the low 3 bits tied down.

exu_edp_dp_and_macro__ports_2__stack_72c__width_3	i_as_cla_clip		 (
  .din0( add_data_e[2:0]				 ),
  .din1({3{ect_as_clip_e_}				}),
  .dout( add_clip[2:0]					 ));


exu_edp_dp_xor_macro__ports_2__stack_72c__width_3	i_as_cla_xor		 (
  .din0( exu_address_e[2:0]				 ),
  .din1({3{ect_alignaddress_little_e}}			 ),
  .dout( addsub_xor[2:0]				 ));

exu_edp_dp_increment_macro__width_4	i_as_cla_inc		 (
  .din ({1'b0,addsub_xor[2:0]}				 ),
  .cin ( ect_alignaddress_little_e			 ),
  .cout( i_as_cla_inc_unused[0]				 ),
  .dout({i_as_cla_inc_unused[1],addsub_inc[2:0]}	 ));


exu_edp_dp_cla_macro__width_64	i_as_cla_ea		 (
  .din0( rs1_data_e[63:0]				 ),
  .din1( rs2_data_e[63:0]				 ),
  .cin ( ect_as_cin_e					 ),
  .cout( edp_add_cout64_e				 ),
  .dout( cla_ea[63:0]					 ));

exu_edp_dp_buff_macro__stack_64c__width_64	i_as_buf_ea		 (
  .din  ( cla_ea[63:0]					 ),
  .dout ( add_data_e[63:0]				 ));

assign exu_address_e[47:0]	= add_data_e[47:0];


cl_dp1_zdt64_8x	zdt_add			           (
  .din0( exu_rs1_data_e[63:0]				 ),
  .din1( exu_rs2_data_e[63:0]				 ),
  .cin ( ect_as_cin_e					 ),
    .zdt_z32_ ( edp_add_zdetect_e_[0]			 ),
    .zdt_z64_ ( edp_add_zdetect_e_[1]			 ));


cl_dp1_zdt64_8x	zdt_sub			           (
  .din0( exu_rs1_data_e[63:0]				 ),
  .din1( rs2_data_e_[63:0]				 ),
  .cin ( ect_as_cin_e					 ),
    .zdt_z32_ ( edp_sub_zdetect_e_[0]			 ),
    .zdt_z64_ ( edp_sub_zdetect_e_[1]			 ));


// To compute COUT32 : use XOR 3-port
//
//	rs1[32]		rs2[32]		result[32]	|	COUT32
//      -------         -------         ----------      |	------
//	   0		   0		    0		|	   0
//	   0		   0		    1		|	   1
//	   0		   1		    0		|	   1
//	   0		   1		    1		|	   0
//	   1		   0		    0		|	   1
//	   1		   0		    1		|	   0
//	   1		   1		    0		|	   0
//	   1		   1		    1		|	   1


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Add/Sub      !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : ASI Ring     !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


exu_edp_dp_msff_macro__stack_72c__width_65	i_asi0_ff		 (
  .scan_in(i_asi0_ff_scanin),
  .scan_out(i_asi0_ff_scanout),
  .clk ( l2clk						),
  .en  ( lsu_asi_clken					),
  .din ( in_rngl_cdbus[64:0]				),
  .dout( edp_rng_in_ff[64:0]				),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


exu_edp_dp_mux_macro__mux_aope__ports_3__stack_72c__width_65	i_asi_ack_mux		 (
  .din0 ({edp_rng_in_ff[64],rml_rng_ack_det_vld,1'b1,		// set ACK (bit 62)
         edp_rng_in_ff[61:56],8'h00,edp_rng_in_ff[47:0]}),	// clear exceptions (bits 55:48)
  .din1({6'b111100, dec_thread_group,	 			// ack for CWP write completion
         rml_rng_ack_cwp_tid[1:0],8'h00,edp_rng_in_ff[47:0]}),	// clear exceptions (bits 55:48)
  .din2({6'b111001, dec_thread_group,	 			// ack for IRF_ECC read completion
         rml_rng_ack_ecc_tid[1:0],56'h00000000000000}	),	// clear exceptions (bits 55:48)
  .sel0( rml_rng_ack_ctl[0]				),
  .sel1( rml_rng_ack_ctl[1]				),
  .dout( rng_ack_data[64:0]				));


exu_edp_dp_msff_macro__mux_aope__ports_7__stack_72c__width_65	i_asi1_ff		 (
  .scan_in(i_asi1_ff_scanin),
  .scan_out(i_asi1_ff_scanout),
  .clk ( l2clk						),
  .en  ( lsu_asi_clken					),
  .din0({{59{1'b0}} , rml_rng_data_out[5:0]}		),
  .din1({{57{1'b0}} , ect_rng_ccr_data[7:0]}		),
  .din2({{33{1'b0}} , rml_rng_y_data[31:0]}		),
  .din3({{26{1'b0}} , asi_inst_mask_reg[38:0]}		),
  .din4({{57{1'b0}} , rml_irf_ecc_data[7:0]}            ),
  .din5( rng_ack_data[64:0]                             ),
  .din6( edp_rng_in_ff[64:0]				),
  .sel0( rml_rng_rd_ctl[0]				),
  .sel1( rml_rng_rd_ctl[1]				),
  .sel2( rml_rng_rd_ctl[2]				),
  .sel3( rml_rng_rd_ctl[3]				),
  .sel4( rml_rng_rd_ctl[4]				),
  .sel5( rml_rng_ack_sel_ctl				),
  .dout( rng_out_ff[64:0]				),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_65	i_asi1_buf		 (
  .din ( rng_out_ff[64:0]				),
  .dout( exu_rngl_cdbus[64:0]				));


// *** Start : Instruction Break Point logic ***


exu_edp_dp_msff_macro__stack_72c__width_39	i_asi_imask_ff		 (
  .scan_in(i_asi_imask_ff_scanin),
  .scan_out(i_asi_imask_ff_scanout),
  .clk ( l2clk						),
  .en  ( rml_rng_wt_imask_ctl				),
  .din ( edp_rng_in_ff[38:0]				),
  .dout( asi_inst_mask_reg[38:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


exu_edp_dp_inv_macro__stack_72c__width_7	i_asi_imask_inv		 (
  .din ( asi_inst_mask_reg[38:32]			),
  .dout( inst_mask_sel_[6:0]				));


exu_edp_dp_buff_macro__stack_72c__width_7	i_asi_imask_buff	 (
  .din ( asi_inst_mask_reg[38:32]			),
  .dout( inst_mask_sel[6:0]				));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_2	i_asi_imask_mux31_30	 (
  .din0( dec_inst_d[31:30]				),
  .din1( asi_inst_mask_reg[31:30]			),
  .sel0( inst_mask_sel[6]				),
  .sel1( inst_mask_sel_[6]				),
  .dout( imask_cmp_data[31:30]				));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_5	i_asi_imask_mux29_25	 (
  .din0( dec_inst_d[29:25]				),
  .din1( asi_inst_mask_reg[29:25]			),
  .sel0( inst_mask_sel[5]				),
  .sel1( inst_mask_sel_[5]				),
  .dout( imask_cmp_data[29:25]				));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_6	i_asi_imask_mux24_19	 (
  .din0( dec_inst_d[24:19]				),
  .din1( asi_inst_mask_reg[24:19]			),
  .sel0( inst_mask_sel[4]				),
  .sel1( inst_mask_sel_[4]				),
  .dout( imask_cmp_data[24:19]				));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_5	i_asi_imask_mux18_14	 (
  .din0( dec_inst_d[18:14]				),
  .din1( asi_inst_mask_reg[18:14]			),
  .sel0( inst_mask_sel[3]				),
  .sel1( inst_mask_sel_[3]				),
  .dout( imask_cmp_data[18:14]				));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_1	i_asi_imask_mux13	 (
  .din0( dec_inst_d[13]					),
  .din1( asi_inst_mask_reg[13]				),
  .sel0( inst_mask_sel[2]				),
  .sel1( inst_mask_sel_[2]				),
  .dout( imask_cmp_data[13]				));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_8	i_asi_imask_mux12_5	 (
  .din0( dec_inst_d[12:5]				),
  .din1( asi_inst_mask_reg[12:5]			),
  .sel0( inst_mask_sel[1]				),
  .sel1( inst_mask_sel_[1]				),
  .dout( imask_cmp_data[12:5]				));


exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_5	i_asi_imask_mux4_0	 (
  .din0( dec_inst_d[4:0]				),
  .din1( asi_inst_mask_reg[4:0]				),
  .sel0( inst_mask_sel[0]				),
  .sel1( inst_mask_sel_[0]				),
  .dout( imask_cmp_data[4:0]				));


exu_edp_dp_zero_macro__width_8	i_asi_ibe_cmp8		 (
  .din ({1'b0 , inst_mask_sel[6:0]}			),
  .dout( ibe_cmp8_d_					));

exu_edp_dp_cmp_macro__width_32	i_asi_ibe_cmp32		 (
  .din0( imask_cmp_data[31:0]				),
  .din1( asi_inst_mask_reg[31:0]			),
  .dout( ibe_cmp32_d					));

exu_edp_dp_inv_macro__stack_72c__width_1	i_asi_ibe_inv		 (
  .din ( ibe_cmp8_d_					),
  .dout( ibe_cmp8_d					));

exu_edp_dp_and_macro__ports_2__stack_72c__width_1	i_asi_ibe_and		 (
  .din0( ibe_cmp32_d					),
  .din1( ibe_cmp8_d					),
  .dout( ibe_trap_d					));

// *** End   : Instruction Break Point logic ***


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : ASI Ring     !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Array        !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!

//			Three-Dimensional Array Addressing Instructions
//
// 3D Array Fixed-Point Address Format
//
//    63:55         54:44         43:33         32:22         21:11         10:00
//  ----------    ----------    ----------    ----------    ----------    ----------
//  Z integer     Z fraction    Y integer     Y fraction    X integer     X fraction
//
//
//    rs2      |
//  Size 'n'   |   Number of Elements
//  -----------|---------------------
//     0       |          64
//     1       |         128
//     2       |         256
//     3       |         512
//     4       |        1024
//     5       |        2048
//
//
// Result Format
//
//      Array8
//      
//      |           upper           |       middle       |       lower        |
//      |---------------------------|--------------------|--------------------|
//      |    Z    |   Y    |   X    |  Z   |  Y   |  X   |  Z   |  Y   |  X   |
//      | 20   17 |     17 |     17 |   13 |    9 |    5 |    4 |    2 |    0 |
//      |+2n  +2n |    + n |        |      |      |      |      |      |      |
//
//
//      Array16
//      
//      |           upper           |       middle       |       lower        |      |
//      |---------------------------|--------------------|--------------------|------|
//      |    Z    |   Y    |   X    |  Z   |  Y   |  X   |  Z   |  Y   |  X   | "0"  |
//      | 21   18 |     18 |     18 |   14 |   10 |    6 |    5 |    3 |    1 |    0 |
//      |+2n  +2n |    + n |        |      |      |      |      |      |      |      |
//
//
//      Array32
//      
//      |           upper           |       middle       |       lower        |      |
//      |---------------------------|--------------------|--------------------|------|
//      |    Z    |   Y    |   X    |  Z   |  Y   |  X   |  Z   |  Y   |  X   | "00" |
//      | 22   19 |     19 |     19 |   15 |   11 |    7 |    6 |    4 |    2 |    0 |
//      |+2n  +2n |    + n |        |      |      |      |      |      |      |      |


	// Split rs1 into fixed point address fields
	assign zint_e[8:0]		= exu_rs1_data_e[63:55];
	assign yint_e[10:0]		= exu_rs1_data_e[43:33];
	assign xint_e[10:0]		= exu_rs1_data_e[21:11];


	// decode n from rs2
	// VIS 2.04: implementation dep: cases 6, 7 are illegal and result is undefined,
	// but in accordance with previous implementations, we implement 6, 7 as case 5.

//	assign array_upper_sel_e[0] 	= ~exu_rs2_data_e[2] & ~exu_rs2_data_e[1] & ~exu_rs2_data_e[0];
//	assign array_upper_sel_e[1] 	= ~exu_rs2_data_e[2] & ~exu_rs2_data_e[1] &  exu_rs2_data_e[0];
//	assign array_upper_sel_e[2] 	= ~exu_rs2_data_e[2] &  exu_rs2_data_e[1] & ~exu_rs2_data_e[0];
//	assign array_upper_sel_e[3] 	= ~exu_rs2_data_e[2] &  exu_rs2_data_e[1] &  exu_rs2_data_e[0];
//	assign array_upper_sel_e[4] 	=  exu_rs2_data_e[2] & ~exu_rs2_data_e[1] & ~exu_rs2_data_e[0];
//	assign array_upper_sel_e[5] 	=  exu_rs2_data_e[2] & (exu_rs2_data_e[1] |  exu_rs2_data_e[0]);
//
	assign array_upper_data0[13:0]	= {10'b0000000000, zint_e[8:5]                            };
	assign array_upper_data1[13:0]	= {   8'b00000000, zint_e[8:5], yint_e[6]   , xint_e[6]   };
	assign array_upper_data2[13:0]	= {     6'b000000, zint_e[8:5], yint_e[7:6] , xint_e[7:6] };
	assign array_upper_data3[13:0]	= {       4'b0000, zint_e[8:5], yint_e[8:6] , xint_e[8:6] };
	assign array_upper_data4[13:0]	= {         2'b00, zint_e[8:5], yint_e[9:6] , xint_e[9:6] };
	assign array_upper_data5[13:0]	= {                zint_e[8:5], yint_e[10:6], xint_e[10:6]};
//
//
//	// select upper, middle, and lower fields
//	assign array_upper_e[13:0]	= ({14{array_upper_sel_e[0]}} & array_upper_data0[13:0]) |
//					  ({14{array_upper_sel_e[1]}} & array_upper_data1[13:0]) |
//					  ({14{array_upper_sel_e[2]}} & array_upper_data2[13:0]) |
//					  ({14{array_upper_sel_e[3]}} & array_upper_data3[13:0]) |
//					  ({14{array_upper_sel_e[4]}} & array_upper_data4[13:0]) |
//					  ({14{array_upper_sel_e[5]}} & array_upper_data5[13:0]);


exu_edp_dp_mux_macro__mux_pgdec__ports_8__stack_72c__width_14	i_array_mux1		 (
  .muxtst (tcu_muxtest_rep0[2]			),
  .din0 ( array_upper_data0[13:0]		),
  .din1 ( array_upper_data1[13:0]		),
  .din2 ( array_upper_data2[13:0]		),
  .din3 ( array_upper_data3[13:0]		),
  .din4 ( array_upper_data4[13:0]		),
  .din5 ( array_upper_data5[13:0]		),
  .din6 ( array_upper_data5[13:0]		),
  .din7 ( array_upper_data5[13:0]		),
  .sel  ( exu_rs2_data_e[2:0]			),
  .dout ( array_upper_e[13:0]			),
  .test(test));


	assign array_middle_e[11:0]	= {zint_e[4:1], yint_e[5:2], xint_e[5:2]};

	assign array_lower_e[4:0]	= {zint_e[0]  , yint_e[1:0], xint_e[1:0]};


	// shift array result based on array instruction type

	assign array08_data[32:0]	= {2'b00, array_upper_e[13:0], array_middle_e[11:0], array_lower_e[4:0]       };
	assign array16_data[32:0]	= {1'b0 , array_upper_e[13:0], array_middle_e[11:0], array_lower_e[4:0], 1'b0 };
	assign array32_data[32:0]	= {       array_upper_e[13:0], array_middle_e[11:0], array_lower_e[4:0], 2'b00};

//	assign ect_array_res_e[32:0]	= ({33{array08_e}} & array08_data[32:0]) |
//					  ({33{array16_e}} & array16_data[32:0]) |
//					  ({33{array32_e}} & array32_data[32:0]);


exu_edp_dp_mux_macro__mux_aope__ports_3__stack_72c__width_33	i_array_mux2		 (
  .din0 ( array08_data[32:0]			),
  .din1 ( array16_data[32:0]			),
  .din2 ( array32_data[32:0]			),
  .sel0 ( ect_array_sel_e[0]			),
  .sel1 ( ect_array_sel_e[1]			),
  .dout ( array_res_e[32:0]			));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Array        !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


// NOSINK rename section

assign edp_add_data_e_b63	= add_data_e[63];
assign edp_sub_data_e_b63	= sub_data_e[63];
assign edp_sub_data_e_b31	= sub_data_e[31];


// fixscan start:
assign i_bp_ff_rcc_scanin        = scan_in                  ;
assign i_bp_ff_rs1_scanin        = i_bp_ff_rcc_scanout      ;
assign i_bp_ff_rs2_scanin        = i_bp_ff_rs1_scanout      ;
assign i_bp_ff_rs3_scanin        = i_bp_ff_rs2_scanout      ;
assign i_rm_ff_m_scanin          = i_bp_ff_rs3_scanout      ;
assign i_rm_ff_b_scanin          = i_rm_ff_m_scanout        ;
assign i_rm_ff_w_scanin          = i_rm_ff_b_scanout        ;
assign i_rm_ff_w_plus1_scanin    = i_rm_ff_w_scanout        ;
assign i_rm_ff_w2_scanin         = i_rm_ff_w_plus1_scanout  ;
assign i_rm_ff_w2_plus1_scanin   = i_rm_ff_w2_scanout       ;
assign i_misc_ff_scanin          = i_rm_ff_w2_plus1_scanout ;
assign i_asi0_ff_scanin          = i_misc_ff_scanout        ;
assign i_asi1_ff_scanin          = i_asi0_ff_scanout        ;
assign i_asi_imask_ff_scanin     = i_asi1_ff_scanout        ;
assign scan_out                  = i_asi_imask_ff_scanout   ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__dbuff_32x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_aope__ports_6__stack_72c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  output [63:0] dout;


cl_dp1_penc6_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5)
);

mux6s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__mux_aope__ports_4__stack_72c__width_72 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire [71:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [70:0] so;

  input [71:0] din0;
  input [71:0] din1;
  input [71:0] din2;
  input [71:0] din3;
  input sel0;
  input sel1;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [71:0] dout;


  output scan_out;


cl_dp1_penc4_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(72)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[71:0]),
  .in1(din1[71:0]),
  .in2(din2[71:0]),
  .in3(din3[71:0]),
.dout(muxout[71:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(72)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[71:0]),
.si({scan_in,so[70:0]}),
.so({so[70:0],scan_out}),
.q(dout[71:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__buffsel_none__mux_aonpe__ports_5__stack_72c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


mux5s #(64)  d1_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .sel3(sel3),
  .sel4(sel4),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_72 (
  din, 
  dout);
  input [71:0] din;
  output [71:0] dout;


buff #(72)  d0_0 (
.in(din[71:0]),
.out(dout[71:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module exu_edp_dp_zero_macro__width_64 (
  din, 
  dout);
  input [63:0] din;
  output dout;


zero #(64)  m0_0 (
.in(din[63:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module exu_edp_dp_inv_macro__dinv_12x__stack_72c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module exu_edp_dp_nand_macro__dnand_16x__left_1__ports_2__stack_72c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module exu_edp_dp_nand_macro__ports_2__stack_72c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module exu_edp_dp_nand_macro__dnand_32x__left_1__ports_2__stack_72c__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


nand2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__stack_72c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__stack_72c__width_7 (
  din, 
  dout);
  input [6:0] din;
  output [6:0] dout;


buff #(7)  d0_0 (
.in(din[6:0]),
.out(dout[6:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_aonpe__ports_8__stack_72c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;
  input [63:0] din5;
  input sel5;
  input [63:0] din6;
  input sel6;
  input [63:0] din7;
  input sel7;
  output [63:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__mux_aope__ports_5__stack_72c__width_72 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [71:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [70:0] so;

  input [71:0] din0;
  input [71:0] din1;
  input [71:0] din2;
  input [71:0] din3;
  input [71:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [71:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(72)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[71:0]),
  .in1(din1[71:0]),
  .in2(din2[71:0]),
  .in3(din3[71:0]),
  .in4(din4[71:0]),
.dout(muxout[71:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(72)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[71:0]),
.si({scan_in,so[70:0]}),
.so({so[70:0],scan_out}),
.q(dout[71:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__buffsel_none__mux_aonpe__ports_5__stack_72c__width_72 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire [71:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [70:0] so;

  input [71:0] din0;
  input sel0;
  input [71:0] din1;
  input sel1;
  input [71:0] din2;
  input sel2;
  input [71:0] din3;
  input sel3;
  input [71:0] din4;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [71:0] dout;


  output scan_out;


mux5s #(72)  d1_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .sel3(sel3),
  .sel4(sel4),
  .in0(din0[71:0]),
  .in1(din1[71:0]),
  .in2(din2[71:0]),
  .in3(din3[71:0]),
  .in4(din4[71:0]),
.dout(muxout[71:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(72)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[71:0]),
.si({scan_in,so[70:0]}),
.so({so[70:0],scan_out}),
.q(dout[71:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module exu_edp_dp_xor_macro__ports_2__stack_72c__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;


xor2 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_aope__ports_2__stack_72c__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__stack_72c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module exu_edp_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module exu_edp_dp_inv_macro__stack_72c__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module exu_edp_dp_nand_macro__ports_3__stack_72c__width_3 (
  din0, 
  din1, 
  din2, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  output [2:0] dout;


nand3 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.in2(din2[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module exu_edp_dp_nand_macro__ports_2__stack_72c__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


nand2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module exu_edp_dp_cmp_macro__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output dout;


cmp #(64)  m0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module exu_edp_dp_cmp_macro__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output dout;


cmp #(8)  m0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__dbuff_32x__stack_72c__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__dbuff_32x__stack_72c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_aonpe__ports_7__stack_72c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;
  input [63:0] din5;
  input sel5;
  input [63:0] din6;
  input sel6;
  output [63:0] dout;


cl_dp1_muxbuff7_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6)
);
mux7s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_pgpe__ports_4__stack_72c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input sel0;
  input sel1;
  input sel2;
  input muxtst;
  input test;
  output [63:0] dout;


cl_dp1_penc4_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
  .test(test)
);

mux4 #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0]),
  .muxtst(muxtst)
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__stack_72c__width_67 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [65:0] so;

  input [66:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [66:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(67)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[66:0]),
.si({scan_in,so[65:0]}),
.so({so[65:0],scan_out}),
.q(dout[66:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__minbuff_1__stack_72c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__mux_aope__ports_3__stack_72c__width_64 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__stack_72c__width_66 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_65 (
  din, 
  dout);
  input [64:0] din;
  output [64:0] dout;


buff #(65)  d0_0 (
.in(din[64:0]),
.out(dout[64:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__stack_72c__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module exu_edp_dp_inv_macro__stack_72c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


inv #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module exu_edp_dp_nand_macro__ports_3__stack_72c__width_64 (
  din0, 
  din1, 
  din2, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  output [63:0] dout;


nand3 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.in2(din2[63:0]),
.out(dout[63:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module exu_edp_dp_nand_macro__ports_4__stack_72c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  output [63:0] dout;


nand4 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.in2(din2[63:0]),
.in3(din3[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__stack_72c__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module exu_edp_dp_zero_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


zero #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__left_32__stack_72c__width_28 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [26:0] so;

  input [27:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [27:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


//
//   invert macro
//
//


module exu_edp_dp_inv_macro__stack_72c__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


inv #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_7 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
  input [6:0] din0;
  input sel0;
  input [6:0] din1;
  input sel1;
  input [6:0] din2;
  input sel2;
  output [6:0] dout;


mux3s #(7)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
  .in2(din2[6:0]),
.dout(dout[6:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  input [31:0] din2;
  input sel2;
  output [31:0] dout;


mux3s #(32)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
.dout(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  output [31:0] dout;


mux2s #(32)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_15 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
  input [14:0] din0;
  input sel0;
  input [14:0] din1;
  input sel1;
  input [14:0] din2;
  input sel2;
  output [14:0] dout;


mux3s #(15)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .in0(din0[14:0]),
  .in1(din1[14:0]),
  .in2(din2[14:0]),
.dout(dout[14:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_16 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [15:0] din0;
  input sel0;
  input [15:0] din1;
  input sel1;
  output [15:0] dout;


mux2s #(16)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
.dout(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_8 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [7:0] din0;
  input sel0;
  input [7:0] din1;
  input sel1;
  output [7:0] dout;


mux2s #(8)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_23 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
  input [22:0] din0;
  input sel0;
  input [22:0] din1;
  input sel1;
  input [22:0] din2;
  input sel2;
  output [22:0] dout;


mux3s #(23)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .in0(din0[22:0]),
  .in1(din1[22:0]),
  .in2(din2[22:0]),
.dout(dout[22:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_31 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
  input [30:0] din0;
  input sel0;
  input [30:0] din1;
  input sel1;
  input [30:0] din2;
  input sel2;
  output [30:0] dout;


mux3s #(31)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .in0(din0[30:0]),
  .in1(din1[30:0]),
  .in2(din2[30:0]),
.dout(dout[30:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_16 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
  input [15:0] din0;
  input sel0;
  input [15:0] din1;
  input sel1;
  input [15:0] din2;
  input sel2;
  output [15:0] dout;


mux3s #(16)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
  .in2(din2[15:0]),
.dout(dout[15:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


buff #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


//
//   invert macro
//
//


module exu_edp_dp_inv_macro__stack_72c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_39 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [38:0] din0;
  input sel0;
  input [38:0] din1;
  input sel1;
  output [38:0] dout;


mux2s #(39)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[38:0]),
  .in1(din1[38:0]),
.dout(dout[38:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_31 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [30:0] din0;
  input sel0;
  input [30:0] din1;
  input sel1;
  output [30:0] dout;


mux2s #(31)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[30:0]),
  .in1(din1[30:0]),
.dout(dout[30:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_24 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [23:0] din0;
  input sel0;
  input [23:0] din1;
  input sel1;
  output [23:0] dout;


mux2s #(24)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[23:0]),
  .in1(din1[23:0]),
.dout(dout[23:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_23 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [22:0] din0;
  input sel0;
  input [22:0] din1;
  input sel1;
  output [22:0] dout;


mux2s #(23)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[22:0]),
  .in1(din1[22:0]),
.dout(dout[22:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_15 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [14:0] din0;
  input sel0;
  input [14:0] din1;
  input sel1;
  output [14:0] dout;


mux2s #(15)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[14:0]),
  .in1(din1[14:0]),
.dout(dout[14:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_48 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [47:0] din0;
  input sel0;
  input [47:0] din1;
  input sel1;
  output [47:0] dout;


mux2s #(48)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
.dout(dout[47:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module exu_edp_dp_and_macro__dinv_16x__dnand_6x__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__dbuff_48x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_aodec__ports_8__stack_72c__width_71 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [70:0] din0;
  input [70:0] din1;
  input [70:0] din2;
  input [70:0] din3;
  input [70:0] din4;
  input [70:0] din5;
  input [70:0] din6;
  input [70:0] din7;
  input [2:0] sel;
  output [70:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(71)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[70:0]),
  .in1(din1[70:0]),
  .in2(din2[70:0]),
  .in3(din3[70:0]),
  .in4(din4[70:0]),
  .in5(din5[70:0]),
  .in6(din6[70:0]),
  .in7(din7[70:0]),
.dout(dout[70:0])
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__stack_72c__width_71 (
  din, 
  dout);
  input [70:0] din;
  output [70:0] dout;


buff #(71)  d0_0 (
.in(din[70:0]),
.out(dout[70:0])
);


endmodule


//
//   invert macro
//
//


module exu_edp_dp_inv_macro__dinv_6x__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [2:0] din0;
  input sel0;
  input [2:0] din1;
  input sel1;
  output [2:0] dout;


mux2s #(3)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[2:0]),
  .in1(din1[2:0]),
.dout(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_aodec__ports_8__stack_72c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input [2:0] sel;
  output [63:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   cla macro
//
//


module exu_edp_dp_cla_macro__width_64 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;
  output cout;


cla #(64)  m0_0 (
.cin(cin),
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0]),
.cout(cout)
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module exu_edp_dp_and_macro__ports_2__stack_72c__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


and2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module exu_edp_dp_xor_macro__ports_2__stack_72c__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


xor2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


//
//   increment macro 
//
//


module exu_edp_dp_increment_macro__width_4 (
  din, 
  cin, 
  dout, 
  cout);
  input [3:0] din;
  input cin;
  output [3:0] dout;
  output cout;


incr #(4)  m0_0 (
.cin(cin),
.in(din[3:0]),
.out(dout[3:0]),
.cout(cout)
);


endmodule


//
//   buff macro
//
//


module exu_edp_dp_buff_macro__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__stack_72c__width_65 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_aope__ports_3__stack_72c__width_65 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [64:0] din0;
  input [64:0] din1;
  input [64:0] din2;
  input sel0;
  input sel1;
  output [64:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(65)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
.dout(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__mux_aope__ports_7__stack_72c__width_65 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire [64:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din0;
  input [64:0] din1;
  input [64:0] din2;
  input [64:0] din3;
  input [64:0] din4;
  input [64:0] din5;
  input [64:0] din6;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_penc7_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6)
);

mux7s #(65)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
  .in3(din3[64:0]),
  .in4(din4[64:0]),
  .in5(din5[64:0]),
  .in6(din6[64:0]),
.dout(muxout[64:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_edp_dp_msff_macro__stack_72c__width_39 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [37:0] so;

  input [38:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [38:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(39)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[38:0]),
.si({scan_in,so[37:0]}),
.so({so[37:0],scan_out}),
.q(dout[38:0])
);


endmodule


//
//   invert macro
//
//


module exu_edp_dp_inv_macro__stack_72c__width_7 (
  din, 
  dout);
  input [6:0] din;
  output [6:0] dout;


inv #(7)  d0_0 (
.in(din[6:0]),
.out(dout[6:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_2 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [1:0] din0;
  input sel0;
  input [1:0] din1;
  input sel1;
  output [1:0] dout;


mux2s #(2)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[1:0]),
  .in1(din1[1:0]),
.dout(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_5 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [4:0] din0;
  input sel0;
  input [4:0] din1;
  input sel1;
  output [4:0] dout;


mux2s #(5)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[4:0]),
  .in1(din1[4:0]),
.dout(dout[4:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_6 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [5:0] din0;
  input sel0;
  input [5:0] din1;
  input sel1;
  output [5:0] dout;


mux2s #(6)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[5:0]),
  .in1(din1[5:0]),
.dout(dout[5:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  output [0:0] dout;


mux2s #(1)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
.dout(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_72c__width_8 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [7:0] din0;
  input sel0;
  input [7:0] din1;
  input sel1;
  output [7:0] dout;


mux2s #(8)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module exu_edp_dp_zero_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


zero #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module exu_edp_dp_and_macro__ports_2__stack_72c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_pgdec__ports_8__stack_72c__width_14 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [13:0] din0;
  input [13:0] din1;
  input [13:0] din2;
  input [13:0] din3;
  input [13:0] din4;
  input [13:0] din5;
  input [13:0] din6;
  input [13:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [13:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(14)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[13:0]),
  .in1(din1[13:0]),
  .in2(din2[13:0]),
  .in3(din3[13:0]),
  .in4(din4[13:0]),
  .in5(din5[13:0]),
  .in6(din6[13:0]),
  .in7(din7[13:0]),
.dout(dout[13:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_edp_dp_mux_macro__mux_aope__ports_3__stack_72c__width_33 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [32:0] din0;
  input [32:0] din1;
  input [32:0] din2;
  input sel0;
  input sel1;
  output [32:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(33)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
  .in2(din2[32:0]),
.dout(dout[32:0])
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: exu_mdp_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module exu_mdp_dp (
  tcu_dectest, 
  tcu_muxtest, 
  dec_fgu_sel_e, 
  dec_fgu_sel_m, 
  dec_lsu_sel0_e, 
  dec_lsu_sel1_e, 
  dec_rs1_addr0_e, 
  dec_rs1_addr1_e, 
  dec_lsu_sel0_lower_e, 
  dec_lsu_sel1_lower_e, 
  dec_lsu_sel0_upper_e, 
  dec_lsu_sel1_upper_e, 
  dec_rs1_addr0_upper_e, 
  dec_rs1_addr1_upper_e, 
  exu0_mdp_mux_sel_e, 
  exu1_mdp_mux_sel_e, 
  exu_ms_icc0_e, 
  exu_ms_icc1_e, 
  exu_rs1_data0_e, 
  exu_rs1_data1_e, 
  exu_rs2_data0_e, 
  exu_rs2_data1_e, 
  exu_y_data0_e, 
  exu_y_data1_e, 
  exu_address0_e, 
  exu_address1_e, 
  exu_store_data0_e, 
  exu_store_data1_e, 
  exu_ecc_winop_flush_m, 
  exu_gsr_data0_m, 
  exu_gsr_data1_m, 
  exu_gsr_vld0_m, 
  exu_gsr_vld1_m, 
  exu_cmov_true_m, 
  lsu_exu_address_e, 
  lsu_sel_lsu_addr_e, 
  exu_fgu_rs1_e, 
  exu_fgu_rs2_e, 
  exu_fgu_gsr_m, 
  exu_fgu_gsr_vld_m, 
  exu_fgu_flush_m, 
  exu_fgu_fmov_vld_m, 
  exu_lsu_address_e, 
  exu_lsu_store_data_e, 
  exu_lsu_rs2_e);
wire test;
wire exu_rs1_data0_b31;
wire exu_rs2_data0_b31;
wire exu_rs1_data1_b31;
wire exu_rs2_data1_b31;
wire [63:0] rs1_data0_early_mux;
wire [63:0] rs1_data0_early;
wire [63:0] rs1_data1_early;
wire [63:32] rs2_data0_early_mux;
wire [63:0] rs2_data0_early;
wire [63:0] rs2_data1_early;
wire [63:0] rs1_e;
wire [63:0] rs2_e;
wire fmov_vld_m;
wire flush_m;
wire [1:0] gsr_vld_m;
wire [31:0] gsr_m;
wire tcu_muxtest_rep0;
wire [63:0] store_data_e;


input		tcu_dectest;		// Passgate mux test control
input		tcu_muxtest;		// Passgate mux test control

input  [1:0]	dec_fgu_sel_e;		// mux select between TG's for fgu ops
input  [1:0]	dec_fgu_sel_m;		// mux select between TG's for fgu ops
   
input 		dec_lsu_sel0_e;		// TG0 address         -> address
input 		dec_lsu_sel1_e;		// TG1 address         -> address

input		dec_rs1_addr0_e;	// CASA only : TG0 RS1 -> address
input		dec_rs1_addr1_e;	// CASA only : TG1 RS1 -> address

input 		dec_lsu_sel0_lower_e;	// TG0 address         -> address 
input 		dec_lsu_sel1_lower_e;	// TG1 address         -> address 

input 		dec_lsu_sel0_upper_e;	// TG0 address         -> address (zero when pstate.am = 1, ie 32-bit addressing)
input 		dec_lsu_sel1_upper_e;	// TG1 address         -> address (zero when pstate.am = 1, ie 32-bit addressing)

input		dec_rs1_addr0_upper_e;	// CASA only : TG0 RS1 -> address (zero when pstate.am = 1, ie 32-bit addressing)
input		dec_rs1_addr1_upper_e;	// CASA only : TG1 RS1 -> address (zero when pstate.am = 1, ie 32-bit addressing)

input  [5:0]	exu0_mdp_mux_sel_e;
input  [5:0]	exu1_mdp_mux_sel_e;

input		exu_ms_icc0_e;
input		exu_ms_icc1_e;

input  [63:0]	exu_rs1_data0_e;
input  [63:0]	exu_rs1_data1_e;
input  [63:0]	exu_rs2_data0_e;
input  [63:0]	exu_rs2_data1_e;

input  [31:0]	exu_y_data0_e;
input  [31:0]	exu_y_data1_e;

input  [47:0]	exu_address0_e;
input  [47:0]	exu_address1_e;

input  [63:0]	exu_store_data0_e;
input  [63:0]	exu_store_data1_e;

input  [1:0]	exu_ecc_winop_flush_m;  

input  [31:0]	exu_gsr_data0_m;
input  [31:0]	exu_gsr_data1_m;

input  [1:0]	exu_gsr_vld0_m;
input  [1:0]	exu_gsr_vld1_m;

input  [1:0]	exu_cmov_true_m;

input  [47:13]  lsu_exu_address_e;
input		lsu_sel_lsu_addr_e;


output [63:0]	exu_fgu_rs1_e;
output [63:0]	exu_fgu_rs2_e;
output [31:0]	exu_fgu_gsr_m;
output [1:0]	exu_fgu_gsr_vld_m;
output		exu_fgu_flush_m;
output		exu_fgu_fmov_vld_m;


output [47:0]	exu_lsu_address_e;
output [63:0]	exu_lsu_store_data_e;
output [7:0]	exu_lsu_rs2_e;			// Partial stores


// scan/test renames
assign test		= tcu_dectest;
// end scan/test renames


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : FGU Muxing   !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


exu_mdp_dp_buff_macro__width_2	i_fp_buff0		 (
  .din  ({exu_rs1_data0_e[31],exu_rs2_data0_e[31]}),
  .dout ({exu_rs1_data0_b31  ,exu_rs2_data0_b31  }));

exu_mdp_dp_buff_macro__width_2	i_fp_buff1		 (
  .din  ({exu_rs1_data1_e[31],exu_rs2_data1_e[31]}),
  .dout ({exu_rs1_data1_b31  ,exu_rs2_data1_b31}  ));


exu_mdp_dp_mux_macro__mux_aope__ports_5__stack_72c__width_64	i_fp_mux_rs1_early0	 (
  .din0 ({{32{exu_rs1_data0_b31}}		,exu_rs1_data0_e[31:0]}			),	// pg. 197 SMUL(cc)
  .din1 ({{32{1'b0             }}		,exu_rs1_data0_e[31:0]}			),	// pg. 197 UMUL(cc)
  .din2 ({exu_y_data0_e[31:0]      		,exu_rs1_data0_e[31:0]}			),	// pg. 152 SDIV(cc), UDIV(cc)
  .din3 ({{30{1'b0}},exu_y_data0_e[0],1'b0	,exu_ms_icc0_e,exu_rs1_data0_e[31:1]}	),	// pg. 199 MULScc
  .din4 ({exu_rs1_data0_e[63:32]		,exu_rs1_data0_e[31:0]}			),
  .sel0 ( exu0_mdp_mux_sel_e[0]								),
  .sel1 ( exu0_mdp_mux_sel_e[1]								),
  .sel2 ( exu0_mdp_mux_sel_e[2]								),
  .sel3 ( exu0_mdp_mux_sel_e[3]								),
  .dout ( rs1_data0_early_mux[63:0]							));

exu_mdp_dp_buff_macro__stack_72c__width_64	i_fp_buf_rs1_early0	 (
  .din  ( rs1_data0_early_mux[63:0]							),
  .dout ( rs1_data0_early[63:0]								));


exu_mdp_dp_mux_macro__mux_aope__ports_5__stack_72c__width_64	i_fp_mux_rs1_early1	 (
  .din0 ({{32{exu_rs1_data1_b31}}		,exu_rs1_data1_e[31:0]}			),	// pg. 197 SMUL(cc)
  .din1 ({{32{1'b0             }}		,exu_rs1_data1_e[31:0]}			),	// pg. 197 UMUL(cc)
  .din2 ({exu_y_data1_e[31:0]      		,exu_rs1_data1_e[31:0]}			),	// pg. 152 SDIV(cc), UDIV(cc)
  .din3 ({{30{1'b0}},exu_y_data1_e[0],1'b0	,exu_ms_icc1_e,exu_rs1_data1_e[31:1]}	),	// pg. 199 MULScc
  .din4 ({exu_rs1_data1_e[63:32]		,exu_rs1_data1_e[31:0]}			),
  .sel0 ( exu1_mdp_mux_sel_e[0]								),
  .sel1 ( exu1_mdp_mux_sel_e[1]								),
  .sel2 ( exu1_mdp_mux_sel_e[2]								),
  .sel3 ( exu1_mdp_mux_sel_e[3]								),
  .dout ( rs1_data1_early[63:0]								));


exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_32	i_fp_mux_rs2_early0	 (
  .din0 ( {32{exu_rs2_data0_b31}}							),	// pg. 197 SDIV(cc), SMUL(cc)
//.din1 ( {32{1'b0             }}							),	// pg. 197 UDIV(cc), UMUL(cc)  pg. 199 MULScc
  .din1 ( exu_rs2_data0_e[63:32]							),
  .sel0 ( exu0_mdp_mux_sel_e[4]								),
  .sel1 ( exu0_mdp_mux_sel_e[5]								),
  .dout ( rs2_data0_early_mux[63:32]							));

exu_mdp_dp_buff_macro__stack_72c__width_32	i_fp_buf_rs2_early0	 (
  .din  ( rs2_data0_early_mux[63:32]							),
  .dout ( rs2_data0_early[63:32]							));


exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_32	i_fp_mux_rs2_early1	 (
  .din0 ( {32{exu_rs2_data1_b31}}							),	// pg. 197 SDIV(cc), SMUL(cc)
//.din1 ( {32{1'b0             }}							),	// pg. 197 UDIV(cc), UMUL(cc)  pg. 199 MULScc
  .din1 ( exu_rs2_data1_e[63:32]							),
  .sel0 ( exu1_mdp_mux_sel_e[4]								),
  .sel1 ( exu1_mdp_mux_sel_e[5]								),
  .dout ( rs2_data1_early[63:32]							));

  assign rs2_data0_early[31:0]	= exu_rs2_data0_e[31:0];
  assign rs2_data1_early[31:0]	= exu_rs2_data1_e[31:0];


exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_64	i_fp_mux_rs1		 (
  .din0 ( rs1_data0_early[63:0]								),
  .din1 ( rs1_data1_early[63:0]								),
  .sel0 ( dec_fgu_sel_e[0]								),
  .sel1 ( dec_fgu_sel_e[1]								),
  .dout ( rs1_e[63:0]									));

exu_mdp_dp_buff_macro__stack_72c__width_64	i_fp_buf_rs1		 (
  .din  ( rs1_e[63:0]									),
  .dout ( exu_fgu_rs1_e[63:0]								));


exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_64	i_fp_mux_rs2		 (
  .din0 ( rs2_data0_early[63:0]								),
  .din1 ( rs2_data1_early[63:0]								),
  .sel0 ( dec_fgu_sel_e[0]								),
  .sel1 ( dec_fgu_sel_e[1]								),
  .dout ( rs2_e[63:0]									));

exu_mdp_dp_buff_macro__stack_72c__width_64	i_fp_buf_rs2		 (
  .din  ( rs2_e[63:0]									),
  .dout ( exu_fgu_rs2_e[63:0]								));


exu_mdp_dp_buff_macro__stack_72c__width_8	i_ls_buf_rs2		 (
  .din  ( exu_fgu_rs2_e[7:0]								),
  .dout ( exu_lsu_rs2_e[7:0]								));


exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_36	i_fp_mux_gsr		 (
  .din0 ({exu_cmov_true_m[0] , exu_ecc_winop_flush_m[0], exu_gsr_vld0_m[1:0]    , exu_gsr_data0_m[31:0]}	),
  .din1 ({exu_cmov_true_m[1] , exu_ecc_winop_flush_m[1], exu_gsr_vld1_m[1:0]    , exu_gsr_data1_m[31:0]}	),
  .sel0 ( dec_fgu_sel_m[0]											),
  .sel1 ( dec_fgu_sel_m[1]											),
  .dout ({        fmov_vld_m ,         flush_m         ,         gsr_vld_m[1:0] ,         gsr_m[31:0]}		));

exu_mdp_dp_buff_macro__stack_72c__width_36	i_fp_buf_gsr		 (
  .din  ({        fmov_vld_m ,         flush_m         ,         gsr_vld_m[1:0] ,         gsr_m[31:0]}		),
  .dout ({exu_fgu_fmov_vld_m , exu_fgu_flush_m         , exu_fgu_gsr_vld_m[1:0] , exu_fgu_gsr_m[31:0]}		));


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : LSU Muxing   !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!

exu_mdp_dp_buff_macro__dbuff_48x__width_1	tst_mux_rep0		 (
  .din ( tcu_muxtest									),
  .dout( tcu_muxtest_rep0								));

exu_mdp_dp_mux_macro__dmux_32x__mux_pgpe__ports_6__stack_72c__width_32	i_ls_mux_addr_l		 (
  .muxtst (tcu_muxtest_rep0								),
  .din0 ({lsu_exu_address_e[31:13],{13{1'b0}}}						),
  .din1 ( exu_rs1_data0_e[31:0]								),
  .din2 ( exu_rs1_data1_e[31:0]								),
  .din3 ( exu_address0_e[31:0]								),
  .din4 ( exu_address1_e[31:0]								),
  .din5 ({32{1'b0}}									),
  .sel0 ( lsu_sel_lsu_addr_e								),
  .sel1 ( dec_rs1_addr0_e								),
  .sel2 ( dec_rs1_addr1_e								),
  .sel3 ( dec_lsu_sel0_lower_e								),
  .sel4 ( dec_lsu_sel1_lower_e								),
  .dout ( exu_lsu_address_e[31:0]							),
  .test(test));

exu_mdp_dp_mux_macro__dmux_32x__mux_pgpe__ports_6__stack_72c__width_16	i_ls_mux_addr_h		 (
  .muxtst (tcu_muxtest_rep0								),
  .din0 ( lsu_exu_address_e[47:32]							),
  .din1 ( exu_rs1_data0_e[47:32]							),
  .din2 ( exu_rs1_data1_e[47:32]							),
  .din3 ( exu_address0_e[47:32]								),
  .din4 ( exu_address1_e[47:32]								),
  .din5 ({16{1'b0}}									),
  .sel0 ( lsu_sel_lsu_addr_e								),
  .sel1 ( dec_rs1_addr0_upper_e								),
  .sel2 ( dec_rs1_addr1_upper_e								),
  .sel3 ( dec_lsu_sel0_upper_e								),
  .sel4 ( dec_lsu_sel1_upper_e								),
  .dout ( exu_lsu_address_e[47:32]							),
  .test(test));	// Zero 47:32 when pstate.am = 1


exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_64	i_ls_mux_store		 (
  .din0 ( exu_store_data0_e[63:0]							),
  .din1 ( exu_store_data1_e[63:0]							),
  .sel0 ( dec_lsu_sel0_e								),
  .sel1 ( dec_lsu_sel1_e								),
  .dout ( store_data_e[63:0]								));

exu_mdp_dp_buff_macro__stack_72c__width_64	i_ls_buf_store		 (
  .din  ( store_data_e[63:0]								),
  .dout ( exu_lsu_store_data_e[63:0]							));


endmodule


//
//   buff macro
//
//


module exu_mdp_dp_buff_macro__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_mdp_dp_mux_macro__mux_aope__ports_5__stack_72c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  output [63:0] dout;


cl_dp1_penc5_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module exu_mdp_dp_buff_macro__stack_72c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  output [31:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(32)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module exu_mdp_dp_buff_macro__stack_72c__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  output [63:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module exu_mdp_dp_buff_macro__stack_72c__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_mdp_dp_mux_macro__mux_aonpe__ports_2__stack_72c__width_36 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [35:0] din0;
  input sel0;
  input [35:0] din1;
  input sel1;
  output [35:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(36)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[35:0]),
  .in1(din1[35:0]),
.dout(dout[35:0])
);


endmodule


//
//   buff macro
//
//


module exu_mdp_dp_buff_macro__stack_72c__width_36 (
  din, 
  dout);
  input [35:0] din;
  output [35:0] dout;


buff #(36)  d0_0 (
.in(din[35:0]),
.out(dout[35:0])
);


endmodule


//
//   buff macro
//
//


module exu_mdp_dp_buff_macro__dbuff_48x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_mdp_dp_mux_macro__dmux_32x__mux_pgpe__ports_6__stack_72c__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input [31:0] din4;
  input [31:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input muxtst;
  input test;
  output [31:0] dout;


cl_dp1_penc6_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
  .test(test)
);

mux6 #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
  .in5(din5[31:0]),
.dout(dout[31:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module exu_mdp_dp_mux_macro__dmux_32x__mux_pgpe__ports_6__stack_72c__width_16 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;

  input [15:0] din0;
  input [15:0] din1;
  input [15:0] din2;
  input [15:0] din3;
  input [15:0] din4;
  input [15:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input muxtst;
  input test;
  output [15:0] dout;


cl_dp1_penc6_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
  .test(test)
);

mux6 #(16)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
  .in2(din2[15:0]),
  .in3(din3[15:0]),
  .in4(din4[15:0]),
  .in5(din5[15:0]),
.dout(dout[15:0]),
  .muxtst(muxtst)
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: exu_rml_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`define BUS_CTL 64
`define BUS_VLD 63
`define BUS_ACK 62
`define BUS_REGID_END 61
`define BUS_REGID_ST 60
`define BUS_RD  59
`define BUS_TID_END 58
`define BUS_TID_ST 56
`define BUS_ASI_END 55
`define BUS_ASI_ST 48
`define ASI  2'b00
`define ASR  2'b01
`define PR   2'b10


module exu_rml_ctl (
  l2clk, 
  scan_in, 
  wmr_scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  spc_aclk_wmr, 
  tcu_scan_en, 
  dec_tid_p, 
  dec_inst_d, 
  dec_valid_e, 
  dec_thread_group, 
  tlu_flush_exu_b, 
  dec_flush_m, 
  dec_flush_b, 
  tlu_gl_thr0, 
  tlu_gl_thr1, 
  tlu_gl_thr2, 
  tlu_gl_thr3, 
  tlu_ccr_cwp_valid, 
  tlu_ccr_cwp_tid, 
  tlu_cwp, 
  mbi_run, 
  mbi_addr, 
  mbi_irf_read_en, 
  mbi_irf_save_en, 
  mbi_irf_restore_en, 
  edp_rng_in_ff, 
  edp_rd_ff_w, 
  ect_misaligned_error_m, 
  ect_yreg_wr_w, 
  ect_tid_lth_w, 
  exu_lsu_va_error_m, 
  exu_ecc_m, 
  edp_rs3_ecc_e, 
  ect_tg_clken, 
  exu_y_data_e, 
  exu_fill_m, 
  exu_spill_b, 
  exu_normal_b, 
  exu_cleanwin_b, 
  exu_wstate_b, 
  exu_cwp_thr0, 
  exu_cwp_thr1, 
  exu_cwp_thr2, 
  exu_cwp_thr3, 
  exu_oddwin_b, 
  exu_window_block_m, 
  exu_tlu_window_block, 
  exu_ecc_winop_flush_m, 
  exu_test_valid, 
  exu_test_tid, 
  exu_test_addr, 
  rml_test_valid_d, 
  rml_rng_data_out, 
  rml_rng_rd_ctl, 
  rml_rng_ack_ctl, 
  rml_rng_ack_cwp_tid, 
  rml_rng_ack_ecc_tid, 
  rml_rng_ack_det_vld, 
  rml_rng_wt_imask_ctl, 
  rml_rng_wt_ccr_ctl, 
  rml_irf_ecc_data, 
  rml_rng_ack_sel_ctl, 
  rml_rng_y_data, 
  rml_irf_cwpswap_tid_m, 
  rml_irf_old_lo_cwp_m, 
  rml_irf_old_e_cwp_m, 
  rml_irf_cwpswap_tid_b, 
  rml_irf_new_lo_cwp_b, 
  rml_irf_new_e_cwp_b, 
  rml_irf_save_even_m, 
  rml_irf_save_odd_m, 
  rml_irf_save_local_m, 
  rml_irf_restore_even_b, 
  rml_irf_restore_odd_b, 
  rml_irf_restore_local_b, 
  rml_irf_global_tid, 
  rml_irf_global_tid_ff, 
  rml_irf_old_agp, 
  rml_irf_new_agp_ff, 
  rml_irf_save_global, 
  rml_irf_restore_global, 
  scan_out, 
  wmr_scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk_pm1;
wire mbist_scanin;
wire mbist_scanout;
wire mbi_irf_save_en_p1;
wire mbi_irf_restore_en_p1;
wire mbi_run_lth;
wire mbi_irf_read_en_p1;
wire [9:0] mbi_addr_lth;
wire mbi_irf_save_en_p2;
wire mbi_irf_restore_en_p2;
wire cwp_trap_scanin;
wire cwp_trap_scanout;
wire trap_ccr_cwp_valid;
wire [1:0] trap_ccr_cwp_tid;
wire [2:0] trap_cwp;
wire [31:13] inst;
wire d_return;
wire d_save;
wire d_restore;
wire d_flushw;
wire d_saved;
wire d_restored;
wire d_allclean;
wire d_otherw;
wire d_normalw;
wire d_invalw;
wire decoded_inst_d2e_scanin;
wire decoded_inst_d2e_scanout;
wire return_e;
wire save_e;
wire restore_e;
wire flushw_e;
wire saved_e;
wire restored_e;
wire allclean_e;
wire otherw_e;
wire normalw_e;
wire invalw_e;
wire decoded_inst_e2m_scanin;
wire decoded_inst_e2m_scanout;
wire return_m;
wire save_m;
wire restore_m;
wire flushw_m;
wire saved_m;
wire restored_m;
wire allclean_m;
wire otherw_m;
wire normalw_m;
wire invalw_m;
wire decoded_inst_m2b_scanin;
wire decoded_inst_m2b_scanout;
wire return_b;
wire save_b;
wire restore_b;
wire saved_b;
wire restored_b;
wire allclean_b;
wire otherw_b;
wire normalw_b;
wire invalw_b;
wire decoded_inst_b2w_scanin;
wire decoded_inst_b2w_scanout;
wire return_w;
wire save_w;
wire restore_w;
wire saved_w;
wire restored_w;
wire allclean_w;
wire otherw_w;
wire normalw_w;
wire invalw_w;
wire [3:0] tid4_d;
wire [1:0] tid_d;
wire tid_p2d2e2m2b2w_scanin;
wire tid_p2d2e2m2b2w_scanout;
wire [1:0] tid_e;
wire [1:0] tid_m;
wire [1:0] tid_b;
wire [1:0] tid_w;
wire [3:0] tid4_e;
wire inst_vld_e2m2b2w_scanin;
wire inst_vld_e2m2b2w_scanout;
wire inst_vld_e;
wire inst_vld_m;
wire inst_vld_b;
wire inst_vld_noflush_m;
wire inst_vld_noflush_b;
wire inst_vld_w;
wire exception_detected_m;
wire spill_detected_m;
wire cleanwin_detected_m;
wire address_error_detected_m;
wire exception_detected_m2b_scanin;
wire exception_detected_m2b_scanout;
wire exception_detected_b;
wire flush_exu_b2w_scanin;
wire flush_exu_b2w_scanout;
wire flush_exu_w;
wire dec_flush_w;
wire cansave_is0_m;
wire [2:0] cansave_m;
wire canrestore_is0_m;
wire [2:0] canrestore_m;
wire otherwin_is0_m;
wire [2:0] otherwin_m;
wire cleanwin4save_is0_m;
wire [2:0] cleanwin_m;
wire noflushwin_m;
wire spill_m;
wire cleanwin_exception_m;
wire return_consider_m;
wire exception_report_m2b_scanin;
wire exception_report_m2b_scanout;
wire spill_b;
wire cleanwin_exception_b;
wire otherwin_is0_b;
wire [5:0] wstate_b;
wire block_wrcwp;
wire wrcwp_in_play_in;
wire detected_wrpr_cwp;
wire wrcwp_in_play;
wire wrcwp_in_playf_scanin;
wire wrcwp_in_playf_scanout;
wire actual_wrpr_cwp;
wire pr_wt_ff_scanin;
wire pr_wt_ff_scanout;
wire actual_wrpr_cwp_d;
wire actual_wrpr_cwp_e;
wire pr_wt_m;
wire trap_ccr_cwp_ff_scanin;
wire trap_ccr_cwp_ff_scanout;
wire trap_ccr_cwp_valid_d;
wire trap_ccr_cwp_valid_e;
wire trap_ccr_cwp_valid_m;
wire make_2nd_window_slot;
wire ack_wrpr_cwp_done;
wire rd_irf_ecc_valid;
wire rd_irf_ecc_valid_lth;
wire [2:0] cwp_dec1_m;
wire [2:0] cwp_m;
wire [2:0] cwp_inc1_m;
wire [2:1] cwp_inc2_m;
wire [2:0] cwp_inc2_cansave_m;
wire [1:0] slot_tid_m;
wire [1:0] wrpr_cwp_tid_hold;
wire winblock_slot_tid_m2d2e2m_scanin;
wire winblock_slot_tid_m2d2e2m_scanout;
wire [1:0] slot_tid_d;
wire [1:0] slot_tid_e;
wire [1:0] old_lo_tid_m;
wire old_lo_fetch_m;
wire [2:0] cwp_thr0;
wire [2:0] cwp_thr1;
wire [2:0] cwp_thr2;
wire [2:0] cwp_thr3;
wire [2:0] old_lo_cwp_inc1_m;
wire old_lo_cwp_inc1_m_unused;
wire [2:0] slot_old_cwp_inc1_m;
wire slot_old_cwp_inc1_m_unused;
wire [2:0] slot_new_cwp_inc1_m;
wire [2:0] rml_irf_new_lo_cwp_m;
wire slot_new_cwp_inc1_m_unused;
wire [2:0] pr_new_cwp_wt;
wire [2:1] new_e_cwp_m;
wire i_rml_restore_en_ff_scanin;
wire i_rml_restore_en_ff_scanout;
wire [1:0] rml_irf_new_agp;
wire rml_irf_restore_even_b_ff;
wire rml_irf_restore_odd_b_ff;
wire rml_irf_restore_local_b_ff;
wire rml_irf_restore_global_ff;
wire [1:0] raw_irf_cwpswap_tid_b;
wire [2:1] raw_irf_new_e_cwp_b;
wire [2:0] raw_irf_new_lo_cwp_b;
wire cwp_update_m;
wire [1:0] cwp_tid_m;
wire [2:0] cwp_new_m;
wire cwp_m2b_scanin;
wire cwp_m2b_scanout;
wire [1:0] cwp_tid_b;
wire [2:0] cwp_new_b;
wire cwp_update_b;
wire cwp_update_no_flush_exu_b;
wire cwp_b2w_scanin;
wire cwp_b2w_scanout;
wire [1:0] cwp_tid_w;
wire [2:0] cwp_new_w;
wire cwp_update_w;
wire [2:0] cwp_next_w;
wire [3:0] cwp_we_w;
wire [3:0] cwp_pr_we;
wire [2:0] cwp_thr0_next;
wire [2:0] cwp_thr1_next;
wire [2:0] cwp_thr2_next;
wire [2:0] cwp_thr3_next;
wire gl_changed_thr0;
wire [1:0] gl_thr0;
wire gl_changed_thr1;
wire [1:0] gl_thr1;
wire gl_changed_thr2;
wire [1:0] gl_thr2;
wire gl_changed_thr3;
wire [1:0] gl_thr3;
wire [3:0] gl_we;
wire [1:0] gl_tid;
wire gl_changed;
wire [1:0] gl_thr0_next;
wire [1:0] gl_thr1_next;
wire [1:0] gl_thr2_next;
wire [1:0] gl_thr3_next;
wire old_gl_ptr_wmr_scanin;
wire old_gl_ptr_wmr_scanout;
wire [2:0] cansave_dec1_w;
wire [2:0] cansave_w;
wire [2:0] cansave_inc1_w;
wire [2:0] canrestore_dec1_w;
wire [2:0] canrestore_w;
wire [2:0] canrestore_inc1_w;
wire [2:0] otherwin_dec1_w;
wire [2:0] otherwin_w;
wire [2:0] cleanwin_inc1_w;
wire [2:0] cleanwin_w;
wire otherwin_is0_w;
wire cleanwin_is111_w;
wire cansave_inc_w;
wire cansave_dec_w;
wire cansave_reset_w;
wire cansave_update_w;
wire [2:0] cansave_next_w;
wire [3:0] cansave_we_w;
wire [3:0] cansave_pr_we;
wire [1:0] pr_tid_ctl;
wire pr_wt_cansave_ctl;
wire canrestore_inc_w;
wire canrestore_dec_w;
wire canrestore_0_w;
wire canrestore_otherwin_w;
wire canrestore_update_w;
wire [2:0] canrestore_next_w;
wire [2:0] canrestore_normalwin_data_w;
wire [2:0] otherwin_thr0;
wire [2:0] otherwin_thr1;
wire [2:0] otherwin_thr2;
wire [2:0] otherwin_thr3;
wire [3:0] canrestore_we_w;
wire [3:0] canrestore_pr_we;
wire pr_wt_canrestore_ctl;
wire otherwin_dec_w;
wire otherwin_0_w;
wire otherwin_canrestore_w;
wire otherwin_update_w;
wire [2:0] otherwin_next_w;
wire [2:0] otherwin_otherw_data_w;
wire [3:0] otherwin_we_w;
wire [2:0] canrestore_thr0;
wire [2:0] canrestore_thr1;
wire [2:0] canrestore_thr2;
wire [2:0] canrestore_thr3;
wire [3:0] otherwin_pr_we;
wire pr_wt_otherwin_ctl;
wire cleanwin_inc_w;
wire cleanwin_reset_w;
wire cleanwin_update_w;
wire [2:0] cleanwin_next_w;
wire [3:0] cleanwin_we_w;
wire [3:0] cleanwin_pr_we;
wire pr_wt_cleanwin_ctl;
wire [3:0] wstate_pr_we;
wire pr_wt_wstate_ctl;
wire [3:0] cwp_new_update;
wire [3:0] cwp_flushed;
wire [3:0] cwp_oddwin_next;
wire [3:0] cwp_oddwin_b;
wire cwp_speculative_scanin;
wire cwp_speculative_scanout;
wire [2:0] cansave_thr0_next;
wire [63:0] data_1f;
wire [2:0] cansave_thr0;
wire [2:0] cansave_thr1_next;
wire [2:0] cansave_thr1;
wire [2:0] cansave_thr2_next;
wire [2:0] cansave_thr2;
wire [2:0] cansave_thr3_next;
wire [2:0] cansave_thr3;
wire [2:1] cansave_thr0_next_l;
wire [2:1] cansave_thr1_next_l;
wire [2:1] cansave_thr2_next_l;
wire [2:1] cansave_thr3_next_l;
wire cansave_pr_wmr_scanin;
wire cansave_pr_wmr_scanout;
wire [2:1] cansave_thr0_l;
wire [2:1] cansave_thr1_l;
wire [2:1] cansave_thr2_l;
wire [2:1] cansave_thr3_l;
wire [2:0] cansave_e;
wire [2:0] cansave_pr_rd;
wire cansave_e2m2b2w_scanin;
wire cansave_e2m2b2w_scanout;
wire [2:0] cansave_b;
wire [2:0] canrestore_thr0_next;
wire [2:0] canrestore_thr1_next;
wire [2:0] canrestore_thr2_next;
wire [2:0] canrestore_thr3_next;
wire canrestore_pr_wmr_scanin;
wire canrestore_pr_wmr_scanout;
wire [2:0] canrestore_e;
wire [2:0] canrestore_pr_rd;
wire canrestore_e2m2b2w_scanin;
wire canrestore_e2m2b2w_scanout;
wire [2:0] canrestore_b;
wire [2:0] otherwin_thr0_next;
wire [2:0] otherwin_thr1_next;
wire [2:0] otherwin_thr2_next;
wire [2:0] otherwin_thr3_next;
wire otherwin_pr_wmr_scanin;
wire otherwin_pr_wmr_scanout;
wire [2:0] otherwin_e;
wire [2:0] otherwin_pr_rd;
wire otherwin_e2m2b2w_scanin;
wire otherwin_e2m2b2w_scanout;
wire [2:0] otherwin_b;
wire [2:0] cleanwin_thr0_next;
wire [2:0] cleanwin_thr0;
wire [2:0] cleanwin_thr1_next;
wire [2:0] cleanwin_thr1;
wire [2:0] cleanwin_thr2_next;
wire [2:0] cleanwin_thr2;
wire [2:0] cleanwin_thr3_next;
wire [2:0] cleanwin_thr3;
wire [2:0] cleanwin_thr0_next_l;
wire [2:0] cleanwin_thr1_next_l;
wire [2:0] cleanwin_thr2_next_l;
wire [2:0] cleanwin_thr3_next_l;
wire cleanwin_pr_wmr_scanin;
wire cleanwin_pr_wmr_scanout;
wire [2:0] cleanwin_thr0_l;
wire [2:0] cleanwin_thr1_l;
wire [2:0] cleanwin_thr2_l;
wire [2:0] cleanwin_thr3_l;
wire [2:0] cleanwin_e;
wire [2:0] cleanwin_pr_rd;
wire cleanwin_e2m2b2w_scanin;
wire cleanwin_e2m2b2w_scanout;
wire [2:0] cleanwin_b;
wire [5:0] wstate_thr0_next;
wire [5:0] wstate_thr0;
wire [5:0] wstate_thr1_next;
wire [5:0] wstate_thr1;
wire [5:0] wstate_thr2_next;
wire [5:0] wstate_thr2;
wire [5:0] wstate_thr3_next;
wire [5:0] wstate_thr3;
wire wstate_pr_wmr_scanin;
wire wstate_pr_wmr_scanout;
wire [5:0] wstate_pr_rd;
wire cwp_pr_wmr_scanin;
wire cwp_pr_wmr_scanout;
wire [2:0] cwp_e;
wire [2:0] cwp_pr_rd;
wire cwp_e2m2b2w_scanin;
wire cwp_e2m2b2w_scanout;
wire ctl_1f;
wire pr_relevent;
wire asr_relevent;
wire asi_relevent;
wire detected_empty_pkt;
wire [1:0] pr_tid;
wire match_cwp;
wire match_cansave;
wire match_canrestore;
wire match_cleanwin;
wire match_otherwin;
wire match_wstate;
wire match_yreg;
wire match_ccr;
wire match_imask;
wire match_irf_ecc;
wire pr_rd;
wire [1:0] send_ack;
wire [5:0] pr_rd_src;
wire [5:0] pr_wt_src;
wire detected_rd_irf_ecc;
wire [4:0] rd_irf_ecc_addr;
wire [4:0] pr_addr_ctl;
wire pipe_rd_irf_ecc_valid_pp2p2d2e_scanin;
wire pipe_rd_irf_ecc_valid_pp2p2d2e_scanout;
wire test_valid_p;
wire ack_irf_ecc_done;
wire [1:0] wrpr_cwp_tid_next;
wire save_wrpr_cwp_tid_scanin;
wire save_wrpr_cwp_tid_scanout;
wire [1:0] rd_irf_tid_next;
wire [1:0] rd_irf_tid_hold;
wire save_rd_irf_tid_scanin;
wire save_rd_irf_tid_scanout;
wire pr_wt_cwp_ctl;
wire [2:0] pr_new_cwp_wt_hold;
wire save_wrpr_cwp_scanin;
wire save_wrpr_cwp_scanout;
wire send_ack_wrpr_cwp;
wire done_wrpr_cwp_hold;
wire done_wrpr_cwp;
wire save_done_wrpr_cwp_scanin;
wire save_done_wrpr_cwp_scanout;
wire send_ack_irf_ecc;
wire done_irf_ecc_hold;
wire done_irf_ecc;
wire save_done_irf_ecc_scanin;
wire save_done_irf_ecc_scanout;
wire [7:0] irf_ecc_data;
wire [7:0] irf_ecc_data_hold;
wire save_irf_ecc_data_scanin;
wire save_irf_ecc_data_scanout;
wire pipe_ack_irf_ecc_scanin;
wire pipe_ack_irf_ecc_scanout;
wire send_ack_irf_ecc_piped;
wire [2:0] asr_rd_src;
wire [2:0] asr_wt_src;
wire asr_ctl_scanin;
wire asr_ctl_scanout;
wire pr_rd_ctl;
wire [5:0] pr_rd_src_ctl;
wire asi_rd_imask_ctl;
wire asr_rd_ccr_ctl;
wire asr_rd_yreg_ctl;
wire asi_wt_imask_ctl;
wire asr_wt_ccr_ctl;
wire asr_wt_yreg_ctl;
wire l1clk_pm2;
wire [3:0] yreg_rng_we;
wire [3:0] yreg_w_we;
wire [31:0] arch_yreg_tid0_in;
wire [31:0] arch_yreg_tid0_ff;
wire [31:0] arch_yreg_tid1_in;
wire [31:0] arch_yreg_tid1_ff;
wire [31:0] arch_yreg_tid2_in;
wire [31:0] arch_yreg_tid2_ff;
wire [31:0] arch_yreg_tid3_in;
wire [31:0] arch_yreg_tid3_ff;
wire i_yreg0_ff_wmr_scanin;
wire i_yreg0_ff_wmr_scanout;
wire i_yreg1_ff_wmr_scanin;
wire i_yreg1_ff_wmr_scanout;
wire i_yreg2_ff_wmr_scanin;
wire i_yreg2_ff_wmr_scanout;
wire i_yreg3_ff_wmr_scanin;
wire i_yreg3_ff_wmr_scanout;
wire spares_scanin;
wire spares_scanout;


// *** Global Inputs ***

input		l2clk;
input 		scan_in;
input		wmr_scan_in;
input 		tcu_pce_ov;			// scan signals
input 		spc_aclk;
input 		spc_bclk;
input		spc_aclk_wmr;
input		tcu_scan_en;


input  [1:0]	dec_tid_p;			// thread ID in pick stage
input  [31:13]	dec_inst_d;			// WARNING: Instruction for full decode
input        	dec_valid_e;			// Inst is truly valid at e
input        	dec_thread_group;		// Static Signal : Tie 1 or 0 where cloning

input       	tlu_flush_exu_b;		// FROM TLU : flushes inst in B-stage   ===> late signal

input		dec_flush_m;			// flush signal to invalidate inst in M ===> late signal

input		dec_flush_b;			// flush signal to invalidate inst in B

input   [1:0]   tlu_gl_thr0;			// FROM TLU : current GL value to update
input   [1:0]   tlu_gl_thr1;			// FROM TLU : current GL value to update
input   [1:0]   tlu_gl_thr2;			// FROM TLU : current GL value to update
input   [1:0]   tlu_gl_thr3;			// FROM TLU : current GL value to update

input   	tlu_ccr_cwp_valid;		// FROM TLU : done/retry CWP updates
input   [1:0]	tlu_ccr_cwp_tid;		// FROM TLU : done/retry CWP updates
input   [2:0]   tlu_cwp;			// FROM TLU : done/retry CWP updates

input		mbi_run; 			// MBIST
input  [9:0]	mbi_addr; 			// MBIST
input		mbi_irf_read_en; 		// MBIST
input		mbi_irf_save_en;		// MBIST
input		mbi_irf_restore_en;		// MBIST


// *** Local  Inputs ***
input  [64:0] 	edp_rng_in_ff;			// 65 bit control/data bus to the ASI 

input  [63:32]	edp_rd_ff_w;			// Yreg write data

input 		ect_misaligned_error_m;		// assert when last 2 bit of address is non "00"

input		ect_yreg_wr_w;
input  [1:0]	ect_tid_lth_w;

input		exu_lsu_va_error_m;		// Address out-of-range

input		exu_ecc_m;			// exu ecc errors detected

input  [7:0]	edp_rs3_ecc_e;                  // ECC syndrom bits for irf_ecc ASI read

input		ect_tg_clken;			// Power Management


// *** Global Outputs ***

output [31:0]	exu_y_data_e;

output     	exu_fill_m;			// To TLU : report window fill  exception
output    	exu_spill_b;			// To TLU : report window spill exception 
output     	exu_normal_b;			// To TLU : report window spill/fill exception type
                                                //    (4 signals above: 1 gate after flop
                                                //                   early signals)
output     	exu_cleanwin_b;			// To TLU : report clean window exception
                                                //    (straight out of flop, early signal)
output	[2:0]	exu_wstate_b;			// To TLU : report fill/spill vector to use
						//          - if otherwin=0: wstate.normal
						//          - else         : wstate.other
                                                //    (2 gate after flop, early)
output	[2:0]	exu_cwp_thr0;			// To TLU : Current Window Pointer for thr0
output	[2:0]	exu_cwp_thr1;			// To TLU : Current Window Pointer for thr1
output	[2:0]	exu_cwp_thr2;			// To TLU : Current Window Pointer for thr2
output	[2:0]	exu_cwp_thr3;			// To TLU : Current Window Pointer for thr3
                                                // (4 signals above: straight out of flops)

output	[3:0]	exu_oddwin_b;			// To PKU : odd window indicator for 4 thrd

output		exu_window_block_m;		// create bubble for SWAP signal for IRF
output		exu_tlu_window_block;		// create bubble for SWAP signal for IRF

output 		exu_ecc_winop_flush_m;		// To MDP : flush FGU 
						//          ADD part of save/restore
						//          in case of exception 


output 		exu_test_valid;			// To PKU : ASI/BIST read of IRF
output 	[1:0]	exu_test_tid;
output 	[4:0]	exu_test_addr;


// *** Local  Outputs ***

output		rml_test_valid_d;

output  [5:0]   rml_rng_data_out;		// Data for PR read
output 	[4:0] 	rml_rng_rd_ctl;			// To EDP: Control for selecting PR/ASR read source
output 	[1:0] 	rml_rng_ack_ctl;		// To EDP: Control for selecting PR/ASR ack bit
output 	[1:0] 	rml_rng_ack_cwp_tid;		// To EDP: CWP write ack tid
output 	[1:0] 	rml_rng_ack_ecc_tid;		// To EDP: ECC read ack tid
output 	 	rml_rng_ack_det_vld;		// To EDP: Ack valid for deterministic access
output		rml_rng_wt_imask_ctl;		// Enable for ASI write to Instruction mask reg
output  	rml_rng_wt_ccr_ctl;		// Enable for ASR write to CCR
output	[7:0]	rml_irf_ecc_data;		// To EDP: saved irf ECC data for indet. ASI access
output		rml_rng_ack_sel_ctl;		// To EDP: select ack type onto ASI rng 
output	[31:0]	rml_rng_y_data;

output  [1:0]   rml_irf_cwpswap_tid_m;		// To IRF: local/odd/even reg swap thread ID
output	[2:0] 	rml_irf_old_lo_cwp_m;		// To IRF: old local/odd CWP
output  [2:1] 	rml_irf_old_e_cwp_m;		// To IRF: old even CWP

output  [1:0]   rml_irf_cwpswap_tid_b;		// To IRF: local/odd/even reg swap thread ID
output	[2:0] 	rml_irf_new_lo_cwp_b;		// To IRF: new local/odd CWP
output  [2:1] 	rml_irf_new_e_cwp_b;		// To IRF: old even CWP

output		rml_irf_save_even_m;		// To IRF: swap enable for even reg
output		rml_irf_save_odd_m;		// To IRF: swap enable for odd reg
output		rml_irf_save_local_m;		// To IRF: swap enable for local reg

output		rml_irf_restore_even_b;		// To IRF: swap enable for even reg
output		rml_irf_restore_odd_b;		// To IRF: swap enable for odd reg
output		rml_irf_restore_local_b;	// To IRF: swap enable for local reg

output  [1:0]   rml_irf_global_tid;		// To IRF: global reg swap thread ID
output  [1:0]   rml_irf_global_tid_ff;		// To IRF: global reg swap thread ID
output  [1:0]   rml_irf_old_agp;		// To IRF: old global CWP
output  [1:0]   rml_irf_new_agp_ff;		// To IRF: new global CWP
output          rml_irf_save_global;		// To IRF: swap enable for global reg
output          rml_irf_restore_global;		// To IRF: swap enable for global reg

output		scan_out;
output		wmr_scan_out;


// renames
assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se	= tcu_scan_en;


exu_rml_ctl_l1clkhdr_ctl_macro clkgen_pm1	(
 .l2clk( l2clk			),
 .l1en ( ect_tg_clken		),
 .l1clk( l1clk_pm1		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


// Make sure exception-input are for valid instructions


// Flop all inputs from Mbist engine

exu_rml_ctl_msff_ctl_macro__width_16	mbist			 (
 .scan_in(mbist_scanin),
 .scan_out(mbist_scanout),
 .l1clk( l1clk_pm1			),
 .din  ({mbi_run		,
	 mbi_irf_read_en	,
	 mbi_irf_save_en	,
	 mbi_irf_restore_en	,
	 mbi_addr[9:0]		,
	 mbi_irf_save_en_p1	,
	 mbi_irf_restore_en_p1}		),
 .dout ({mbi_run_lth  ,
	 mbi_irf_read_en_p1 ,
	 mbi_irf_save_en_p1 ,
	 mbi_irf_restore_en_p1 ,
	 mbi_addr_lth[9:0] ,
	 mbi_irf_save_en_p2 ,
	 mbi_irf_restore_en_p2}		),
  .siclk(siclk),
  .soclk(soclk));


// Flop all inputs from the TLU to have the expected timings

exu_rml_ctl_msff_ctl_macro__width_6	cwp_trap		 (
 .scan_in(cwp_trap_scanin),
 .scan_out(cwp_trap_scanout),
 .l1clk(l1clk_pm1),
 .din  ({tlu_ccr_cwp_valid,tlu_ccr_cwp_tid[1:0],tlu_cwp[2:0]}),
 .dout ({trap_ccr_cwp_valid,trap_ccr_cwp_tid[1:0],trap_cwp[2:0]}),
  .siclk(siclk),
  .soclk(soclk));


// Never have tlu assert valid in the same thread trailing each other within 3 cycles


// =============================================================================
// Instruction Flow
// -----------------------------------------------------------------------------
// D stage:       - decode instructions 
//
// E stage:       - read Privileged Registers
//                - acquires instruction valid signal
//                - generate IRF Control signals
//                - checks for Trap conditions
//
// M stage:       - generate IRF Control signals
//                - checks for Trap conditions
//
// B stage:       - report possible trap at beginning of the cycle 
//                - invalidate instruction if it causes a trap
//                - generate Priviledged Registers write-back values
//
// W stage:       - Write-back Priviledged Registers 
//
//                     |----D----|----E----|----M----|----B----|----W----|
//   
// Decode Inst         |<------->|         
// Read PR                     |<->|
// Inst_vld available            ---->]
// IRF ctl                       |<------------->|-> to IRF
// Trap Chk                      |<----------------->|--> to TLU
// Flash Trap                                        |<------->|
// Write-back Gen.                                             |<------->|
// Write back                                  Trap_kil -->|          |<->|


// =============================================================================
// Instrution Decode
// -----------------------------------------------------------------------------

//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Decode       !*!*!*!*!*!*!*!*!*!*
assign inst[31:19]              = dec_inst_d[31:19];
assign inst[13]                 = dec_inst_d[13];

// *** SAVE/RESTORE ***

assign d_return    = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1001);
assign d_save      = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1100);
assign d_restore   = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b11_1101);
assign d_flushw    = (inst[31:30] == 2'b10) & (inst[24:19] == 6'b10_1011) & 
                     (inst[13] == 1'b0);

assign d_saved     = (inst[31:19] == 13'b10_00000_11_0001);
assign d_restored  = (inst[31:19] == 13'b10_00001_11_0001);
assign d_allclean  = (inst[31:19] == 13'b10_00010_11_0001);
assign d_otherw    = (inst[31:19] == 13'b10_00011_11_0001);
assign d_normalw   = (inst[31:19] == 13'b10_00100_11_0001);
assign d_invalw    = (inst[31:19] == 13'b10_00101_11_0001);

exu_rml_ctl_msff_ctl_macro__width_10	decoded_inst_d2e	 (
 .scan_in(decoded_inst_d2e_scanin),
 .scan_out(decoded_inst_d2e_scanout),
 .l1clk(l1clk_pm1),
 .din  ({d_return, d_save, d_restore, d_flushw, d_saved, d_restored, d_allclean, d_otherw, d_normalw, d_invalw}),
 .dout ({return_e, save_e, restore_e, flushw_e, saved_e, restored_e, allclean_e, otherw_e, normalw_e, invalw_e}),
  .siclk(siclk),
  .soclk(soclk));

exu_rml_ctl_msff_ctl_macro__width_10	decoded_inst_e2m	 (
 .scan_in(decoded_inst_e2m_scanin),
 .scan_out(decoded_inst_e2m_scanout),
 .l1clk(l1clk_pm1),
 .din  ({return_e, save_e, restore_e, flushw_e, saved_e, restored_e, allclean_e, otherw_e, normalw_e, invalw_e}),
 .dout ({return_m, save_m, restore_m, flushw_m, saved_m, restored_m, allclean_m, otherw_m, normalw_m, invalw_m}),
  .siclk(siclk),
  .soclk(soclk));

exu_rml_ctl_msff_ctl_macro__width_9	decoded_inst_m2b	 (
 .scan_in(decoded_inst_m2b_scanin),
 .scan_out(decoded_inst_m2b_scanout),
 .l1clk(l1clk_pm1),
 .din  ({return_m, save_m, restore_m, saved_m, restored_m, allclean_m, otherw_m, normalw_m, invalw_m}),
 .dout ({return_b, save_b, restore_b, saved_b, restored_b, allclean_b, otherw_b, normalw_b, invalw_b}),
  .siclk(siclk),
  .soclk(soclk));

exu_rml_ctl_msff_ctl_macro__width_9	decoded_inst_b2w	 (
 .scan_in(decoded_inst_b2w_scanin),
 .scan_out(decoded_inst_b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({return_b, save_b, restore_b, saved_b, restored_b, allclean_b, otherw_b, normalw_b, invalw_b}),
 .dout ({return_w, save_w, restore_w, saved_w, restored_w, allclean_w, otherw_w, normalw_w, invalw_w}),
  .siclk(siclk),
  .soclk(soclk));

// check for decoding logic, make sure one opcode is not decoded into 2 inst

//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Decode       !*!*!*!*!*!*!*!*!*!*!


// =============================================================================
// Pass through the control signals
// -----------------------------------------------------------------------------
//                            Timing   vld_e  vld_m  vld_b  vld_w  vld_noflush_w
//  ----------------------------------------------------------------------------
//  
//   + internal exception 
//     - clean_window          early     1      1      0      0        1
//     - fill                  early     1      1      0      0        1
//     - spill                 early     1      1      0      0        1
//     - spill_flush           early     1      1      0      0        1
//
//   + external exceptions
//     - exu_ecc_m             early     1      1      0      0        1
//     - misaligned_noflush_m  early
//       - no other exceptions           1      1      0      0        1
//       - w/ fill exception             1      1   (fill)  (fill)     1
//       - w/ ecc exception              1      1   (ecc)   (ecc)      1
// 
//   + external flushes          
//     - tlu_flush_exu_b       late      1      1      0      0        1
//     - dec_flush_m           late      1      0      0      0        1
//     - dec_flush_b           early     1      1      0      0        1


assign tid4_d[3:0]	= {(tid_d[1:0] == 2'b11),(tid_d[1:0] == 2'b10),(tid_d[1:0] == 2'b01),(tid_d[1:0] == 2'b00)};

exu_rml_ctl_msff_ctl_macro__width_14	tid_p2d2e2m2b2w		 (
 .scan_in(tid_p2d2e2m2b2w_scanin),
 .scan_out(tid_p2d2e2m2b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({dec_tid_p[1:0], tid_d[1:0], tid_e[1:0], tid_m[1:0], tid_b[1:0], tid4_d[3:0]}),
 .dout ({    tid_d[1:0], tid_e[1:0], tid_m[1:0], tid_b[1:0], tid_w[1:0], tid4_e[3:0]}),
  .siclk(siclk),
  .soclk(soclk));

exu_rml_ctl_msff_ctl_macro__width_3	inst_vld_e2m2b2w	 (
 .scan_in(inst_vld_e2m2b2w_scanin),
 .scan_out(inst_vld_e2m2b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({inst_vld_e,         inst_vld_m,         inst_vld_b}),
 .dout ({inst_vld_noflush_m, inst_vld_noflush_b, inst_vld_w}),
  .siclk(siclk),
  .soclk(soclk));

assign inst_vld_e = dec_valid_e;
assign inst_vld_m = inst_vld_noflush_m & ~dec_flush_m;


// Flushing current instruction
// ------------------------------------------------------
assign exception_detected_m = (spill_detected_m | exu_fill_m | 
                              cleanwin_detected_m | address_error_detected_m |
                              exu_ecc_m) & ~dec_flush_m;

assign exu_ecc_winop_flush_m = ((spill_detected_m | cleanwin_detected_m | 
                               exu_fill_m) & (save_m | restore_m)) | 
                               exu_ecc_m;


exu_rml_ctl_msff_ctl_macro__width_1	exception_detected_m2b	 (
 .scan_in(exception_detected_m2b_scanin),
 .scan_out(exception_detected_m2b_scanout),
 .l1clk(l1clk_pm1),
 .din  ( exception_detected_m ),
 .dout ( exception_detected_b ),
  .siclk(siclk),
  .soclk(soclk));


// Flush current instruction if exception detected or tlu/dec trap flush 
assign inst_vld_b = inst_vld_noflush_b & ~exception_detected_b & ~tlu_flush_exu_b & ~dec_flush_b;


exu_rml_ctl_msff_ctl_macro__width_2	flush_exu_b2w		 (
 .scan_in(flush_exu_b2w_scanin),
 .scan_out(flush_exu_b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({tlu_flush_exu_b, dec_flush_b}),
 .dout ({flush_exu_w,     dec_flush_w}),
  .siclk(siclk),
  .soclk(soclk));


// =============================================================================
// Trap condition detection, flush, and trap vector generation
// -----------------------------------------------------------------------------
// flush window only if CANSAVE != NWINDOWS-2
// noflushwin_m if CANSAVE == NWINDOWS-2 = 6 = 3'b110
//
assign cansave_is0_m    = (~cansave_m[2]) & (~cansave_m[1]) & 
                          (~cansave_m[0]);

assign canrestore_is0_m = (~canrestore_m[2]) & (~canrestore_m[1]) & 
                          (~canrestore_m[0]);

assign otherwin_is0_m   = (~otherwin_m[2]) & (~otherwin_m[1]) & 
                          (~otherwin_m[0]);

assign cleanwin4save_is0_m =  (cleanwin_m[2] ~^ canrestore_m[2]) & 
                              (cleanwin_m[1] ~^ canrestore_m[1]) &
                              (cleanwin_m[0] ~^ canrestore_m[0]);

assign noflushwin_m     = ( cansave_m[2]) & ( cansave_m[1]) & 
                          (~cansave_m[0]);


// xxx_detected_m : exception condition detected, but not qualified with dec_flush_m
// xxx_m          : real exception, qualified with dec_flush_m
// exu_ecc_m exception pre-empt all other exceptions
// fill exception pre-empt misalign exception

// window_spill: no ecc errors detected
//               and:    cansave = 0,     and valid save instruction is issued
//                    or noflushwin_m = 0 and valid flushw instruction is issued
//
assign spill_detected_m = ~exu_ecc_m &
                          (( cansave_is0_m & inst_vld_noflush_m & save_m  ) |
                           (~noflushwin_m  & inst_vld_noflush_m & flushw_m));

// window_fill:  no ecc errors detected
//               and:    canrestore = 0,  and valid restore instruction is issued
//                    or canrestore = 0,  and valid return  instruction is issued
//
assign exu_fill_m  = ~exu_ecc_m &
                          canrestore_is0_m & inst_vld_noflush_m & (restore_m | return_m);

// misaligned_addr: no ecc errors detected
//                  and no fill condition detected
//                  and misalignment flagged by exu_ect_ctl 
//                  and return instruction is issued
//
assign address_error_detected_m = ~exu_ecc_m & ~exu_fill_m & return_m & inst_vld_noflush_m &
                                  (exu_lsu_va_error_m | ect_misaligned_error_m);

// clean_window: no ecc errors detected
//               and cansave != 0, (cleanwin - canrestore) = 0,
//               and a valid save instruction is issued
//
assign cleanwin_detected_m = ~exu_ecc_m &
                          (~cansave_is0_m & cleanwin4save_is0_m & 
                                        inst_vld_noflush_m & save_m);

assign spill_m     = spill_detected_m    & ~dec_flush_m;

assign cleanwin_exception_m  = cleanwin_detected_m & ~dec_flush_m;

// check for exception detection logic, only one exception detected at a time


assign return_consider_m = (return_m & ~ect_misaligned_error_m & ~exu_lsu_va_error_m) | 
                           (return_m &  exu_fill_m);


// Trap vector generation in M-stage and sent to TLU in B-stage
//-------------------------------------------------------------
exu_rml_ctl_msff_ctl_macro__width_3	exception_report_m2b	 (
 .scan_in(exception_report_m2b_scanin),
 .scan_out(exception_report_m2b_scanout),
 .l1clk(l1clk_pm1),
 .din  ({spill_m, cleanwin_exception_m, otherwin_is0_m}),
 .dout ({spill_b, cleanwin_exception_b, otherwin_is0_b}),
  .siclk(siclk),
  .soclk(soclk));

assign exu_cleanwin_b = cleanwin_exception_b;

assign exu_spill_b  = spill_b;
assign exu_normal_b = otherwin_is0_b;

assign exu_wstate_b[2:0] = ({3{ otherwin_is0_b}} & wstate_b[2:0]) |
                           ({3{~otherwin_is0_b}} & wstate_b[5:3]);


// =============================================================================
// Managing window block signal to decode
// -----------------------------------------------------------------------------
// Creating holes for full window swaps
// - first hole 
//   - available with any window ops
//   - need to create for WRPR to CWP
//   - cannot kick off a wrpr_cwp if tlu is initiating a window change the 
//     same cycle, second part of the tlu window change could conflict with 
//     the first part of the wrpr_cwp
//
// - second hole  
//   - conditions that triggers exu_window_block_m to block a potential conflicting 
//     window operation come down the pipeline in another thread
//     - spills caused by save and flushw
//   - WRPR to CWP
//   - TLU is taking care of all hole creation for done/retry
//
// - for a possible spill exception
//   - use spill_detected_m for block generation
//   - it will be a single cycle pulse, because the inst after save/flushw
//     in the same thread will be a NOP, garanteed by pick logic


// remember that a wrcwp is in play until it can be processed
// -------------------------------------------------------------
assign block_wrcwp = trap_ccr_cwp_valid | spill_detected_m;

assign wrcwp_in_play_in = (detected_wrpr_cwp & block_wrcwp) | (wrcwp_in_play & block_wrcwp);

exu_rml_ctl_msff_ctl_macro__width_1	wrcwp_in_playf		 (
 .scan_in(wrcwp_in_playf_scanin),
 .scan_out(wrcwp_in_playf_scanout),
 .l1clk	(l1clk_pm1),
 .din	(wrcwp_in_play_in),
 .dout	(wrcwp_in_play),
  .siclk(siclk),
  .soclk(soclk));

assign actual_wrpr_cwp = (detected_wrpr_cwp | wrcwp_in_play) & ~block_wrcwp;


exu_rml_ctl_msff_ctl_macro__width_3	pr_wt_ff		 (
 .scan_in(pr_wt_ff_scanin),
 .scan_out(pr_wt_ff_scanout),
 .l1clk(l1clk_pm1),
 .din  ({actual_wrpr_cwp   , actual_wrpr_cwp_d , actual_wrpr_cwp_e}),
 .dout ({actual_wrpr_cwp_d , actual_wrpr_cwp_e , pr_wt_m}),
  .siclk(siclk),
  .soclk(soclk));


exu_rml_ctl_msff_ctl_macro__width_3	trap_ccr_cwp_ff		 (
 .scan_in(trap_ccr_cwp_ff_scanin),
 .scan_out(trap_ccr_cwp_ff_scanout),
 .l1clk(l1clk_pm1),
 .din  ({trap_ccr_cwp_valid   , trap_ccr_cwp_valid_d , trap_ccr_cwp_valid_e }),
 .dout ({trap_ccr_cwp_valid_d , trap_ccr_cwp_valid_e , trap_ccr_cwp_valid_m }),
  .siclk(siclk),
  .soclk(soclk));


assign make_2nd_window_slot = spill_detected_m | pr_wt_m | trap_ccr_cwp_valid;
assign ack_wrpr_cwp_done = pr_wt_m;

assign exu_window_block_m	= actual_wrpr_cwp | rd_irf_ecc_valid | rd_irf_ecc_valid_lth;
assign exu_tlu_window_block	= exu_window_block_m; 


// =============================================================================
// Control signals to IRF 
// -----------------------------------------------------------------------------
// Three sources of control for local/even/odd register swaps:
// - window operation instruction
//   - normal window swaps w/o exception
//   - exception state preparation
// - WRPR to CWP from the ASI ring
// - CWP updates from TLU
//
// One source of control for Global register swap:
// - GL updates from TLU
//

// - generate control signals in M stage
// - send to IRF in B stage
//   - IRF decodes in B stage, saves in W stage, and restores in W2 stage
//
//
//                      old_lo   old_e   new_lo   new_e   l_en   o_en   e_en
//  --------------------------------------------------------------------------
//   window op inst
//   + no exception
//     - save           CWP      CWP+1   CWP+1    CWP+2   o/e     o      e
//     - restore        CWP      CWP+1   CWP-1    CWP     o/e     e      o
//     - saved          -	 -       -        -        -      -      -
//     - restored       -	 -       -        -        -      -      -
//     - flushw         -	 -       -        -        -      -      -
//     - return         CWP	 CWP+1   CWP-1    CWP     o/e     e      o
//
//   + exeption 
//     - clean_window   CWP      CWP+1   CWP+1    CWP+2   o/e     o      e
//     - fill           CWP      CWP+1   CWP-1    CWP     o/e     e      o
//
//     - spill_1        CWP      -       CWP+2    -       o/e    o/e     - 
//       spill_2        -        CWP+1   -        CWP+3    -      -     o/e
//
//     - spill_flush_1  CWP      -       CWP+2+   -       o/e    o/e     - 
//                                       CANSAVE
//
//       spill_flush_2  -        CWP+1   -        CWP+3+   -      -     o/e
//                                                CANSAVE 
//
//   WRPR to CWP
//     - WRPR_CWP_1     CWP      -       NEWCWP   -       o/e    o/e     - 
//       WRPR_CWP_2 	-	 CWP+1   -       NEWCWP+1  -      -     o/e
//
//   TLU CWP updates
//     - TLU_CWP_1      CWP      -       NEWCWP   -       o/e    o/e     - 
//	 TLU_CWP_2	-	 CWP+1   -       NEWCWP+1  -      -     o/e
//
//
// - speculatively controls IRF to do SWAP in case of exception
// - if TLU confirms with tlu_flush_exu_b signal, 
//        continue to restore-step in the swap process
// - if no TLU tlu_flush_exu_b
//        cancels the restore-step in the swap process
//   
//

// calculate possible CWP values
//---------------------------------------------
assign cwp_dec1_m[2:0] = cwp_m[2:0] - 3'b001;
assign cwp_inc1_m[2:0] = cwp_m[2:0] + 3'b001;
assign cwp_inc2_m[2:1] = cwp_m[2:1] + 2'b01 ;

// assign cwp_inc2_cansave_m[2:0] = cwp_m[2:0] + 3'b010 + cansave_m[2:0];
// Calculating increment by 2 plus cansave (logic mapped from espresso)
assign  cwp_inc2_cansave_m[2] = 
( cwp_m[2] &  cwp_m[1] &  cwp_m[0] & ~cansave_m[2] &  cansave_m[1] &  cansave_m[0]) | 
(~cwp_m[2] &  cwp_m[1] &  cwp_m[0] &  cansave_m[2] &  cansave_m[1] &  cansave_m[0]) | 
( cwp_m[2] & ~cwp_m[1] &             ~cansave_m[2] & ~cansave_m[1] & ~cansave_m[0]) | 
(~cwp_m[2] & ~cwp_m[1] &              cansave_m[2] & ~cansave_m[1] & ~cansave_m[0]) | 
(~cwp_m[2] &              cwp_m[0] & ~cansave_m[2] & ~cansave_m[1] &  cansave_m[0]) | 
( cwp_m[2] &              cwp_m[0] &  cansave_m[2] & ~cansave_m[1] &  cansave_m[0]) | 
(~cwp_m[2] &  cwp_m[1] & ~cwp_m[0] & ~cansave_m[2]                                ) | 
( cwp_m[2] &  cwp_m[1] & ~cwp_m[0] &  cansave_m[2]                                ) | 
( cwp_m[2] & ~cwp_m[1] & ~cwp_m[0] & ~cansave_m[2] & ~cansave_m[1]                ) | 
(~cwp_m[2] & ~cwp_m[1] & ~cwp_m[0] &  cansave_m[2] & ~cansave_m[1]                ) | 
(~cwp_m[2] &  cwp_m[1] &             ~cansave_m[2] &                 ~cansave_m[0]) | 
( cwp_m[2] &  cwp_m[1] &              cansave_m[2] &                 ~cansave_m[0]) | 
(~cwp_m[2] & ~cwp_m[1] &             ~cansave_m[2] &  cansave_m[1]                ) | 
( cwp_m[2] & ~cwp_m[1] &              cansave_m[2] &  cansave_m[1]                );

assign  cwp_inc2_cansave_m[1] = 
            (~cwp_m[1] &  cwp_m[0] &                  cansave_m[1] &  cansave_m[0]) | 
            ( cwp_m[1] &  cwp_m[0] &                 ~cansave_m[1] &  cansave_m[0]) | 
            ( cwp_m[1] &  cansave_m[1] &                             ~cansave_m[0]) | 
            ( cwp_m[1] & ~cwp_m[0] &                  cansave_m[1]                ) | 
            (~cwp_m[1] & ~cansave_m[1] &                             ~cansave_m[0]) | 
            (~cwp_m[1] & ~cwp_m[0] &                 ~cansave_m[1]                );

assign  cwp_inc2_cansave_m[0] = (cwp_m[0]& ~cansave_m[0]) | (~cwp_m[0]&  cansave_m[0]);


// setting IRF controls 
// --------------------------------------
// Thread ID is from
// - TLU in case of TLU CWP updates
// - in case of (trap_ccr_cwp_valid_m)
//   - the thread ID passed down the pipeline
// - WRPR ASI control in case of WRPR to CWP
//   - for the first slot, TID from ASI interface
// - current m-stage instruction ID in all other cases

assign rml_irf_cwpswap_tid_m[1:0]	= ( {2{~mbi_run_lth &  trap_ccr_cwp_valid                                   }} & trap_ccr_cwp_tid[1:0] ) |
					  ( {2{~mbi_run_lth & ~trap_ccr_cwp_valid &  trap_ccr_cwp_valid_m           }} & slot_tid_m[1:0]       ) |
					  ( {2{~mbi_run_lth & ~trap_ccr_cwp_valid & ~trap_ccr_cwp_valid_m &  pr_wt_m}} & wrpr_cwp_tid_hold[1:0]) |
					  ( {2{~mbi_run_lth & ~trap_ccr_cwp_valid & ~trap_ccr_cwp_valid_m & ~pr_wt_m}} & tid_m[1:0]            ) |
					  ( {2{ mbi_run_lth & ~mbi_irf_save_en_p2                                   }} & mbi_addr_lth[3:2]     ) |
					  ( {2{ mbi_run_lth &  mbi_irf_save_en_p2                                   }} & mbi_addr_lth[6:5]     );

exu_rml_ctl_msff_ctl_macro__width_6	winblock_slot_tid_m2d2e2m	 (
 .scan_in(winblock_slot_tid_m2d2e2m_scanin),
 .scan_out(winblock_slot_tid_m2d2e2m_scanout),
 .l1clk(l1clk_pm1),
 .din  ({rml_irf_cwpswap_tid_m[1:0], slot_tid_d[1:0], slot_tid_e[1:0] }),
 .dout ({slot_tid_d           [1:0], slot_tid_e[1:0], slot_tid_m[1:0] }),
  .siclk(siclk),
  .soclk(soclk));

/* 0in value -var {trap_ccr_cwp_valid, pr_wt_m, trap_ccr_cwp_valid_m} 
             -val 3'b000 3'b001 3'b010  3'b100 
             -message "TLU->CWP, WRPR->CWP & 2nd Full swap conflict in M stage exu.rml"*/


// Old CWP should always be the current CWP for the thread in processing
// - in case of WRPR of CWP
//   - get the correct old CWP from priviliged register file based on wrpr_cwp_tid_hold[1:0]
// - in case of done/retry 
//   - get the correct old CWP from priviliged register file based on trap_ccr_cwp_tid[1:0]
// - in case of (trap_ccr_cwp_valid_m):
//   - rml_irf_old_lo_cwp_m[2:0] = don't care, could just be cwp_m[2:0]
//   - rml_irf_old_e_cwp_m[2:0]  = the value passed down, incremented

assign old_lo_tid_m[1:0] 	= ({2{ trap_ccr_cwp_valid}}                 & trap_ccr_cwp_tid[1:0] ) |
				  ({2{~trap_ccr_cwp_valid}} & {2{ pr_wt_m}} & wrpr_cwp_tid_hold[1:0]) |
				  ({2{~trap_ccr_cwp_valid}} & {2{~pr_wt_m}} & tid_m[1:0]            );

assign old_lo_fetch_m    = trap_ccr_cwp_valid | pr_wt_m;

assign rml_irf_old_lo_cwp_m[2:0]= ({3{~mbi_run_lth & ~old_lo_fetch_m                                      }} & cwp_m[2:0]       ) |
				  ({3{~mbi_run_lth &  old_lo_fetch_m & ~old_lo_tid_m[1] & ~old_lo_tid_m[0]}} & cwp_thr0[2:0]    ) |
				  ({3{~mbi_run_lth &  old_lo_fetch_m & ~old_lo_tid_m[1] &  old_lo_tid_m[0]}} & cwp_thr1[2:0]    ) |
				  ({3{~mbi_run_lth &  old_lo_fetch_m &  old_lo_tid_m[1] & ~old_lo_tid_m[0]}} & cwp_thr2[2:0]    ) |
				  ({3{~mbi_run_lth &  old_lo_fetch_m &  old_lo_tid_m[1] &  old_lo_tid_m[0]}} & cwp_thr3[2:0]    ) |
				  ({3{ mbi_run_lth & ~mbi_irf_save_en_p2                                  }} & mbi_addr_lth[2:0]) |
				  ({3{ mbi_run_lth &  mbi_irf_save_en_p2                                  }} & mbi_addr_lth[9:7]);

assign old_lo_cwp_inc1_m[2:0] = rml_irf_old_lo_cwp_m[2:0] + 3'b001;
assign old_lo_cwp_inc1_m_unused = old_lo_cwp_inc1_m[0];

assign rml_irf_old_e_cwp_m[2:1]	= ({2{~mbi_run_lth &  old_lo_fetch_m                        }} & old_lo_cwp_inc1_m  [2:1]) |
				  ({2{~mbi_run_lth & ~old_lo_fetch_m &  make_2nd_window_slot}} & slot_old_cwp_inc1_m[2:1]) |
				  ({2{~mbi_run_lth & ~old_lo_fetch_m & ~make_2nd_window_slot}} & cwp_inc1_m[2:1]         ) |
				  ({2{ mbi_run_lth                   & ~mbi_irf_save_en_p2  }} & mbi_addr_lth[1:0]       ) |
				  ({2{ mbi_run_lth                   &  mbi_irf_save_en_p2  }} & mbi_addr_lth[9:8]       );

assign slot_old_cwp_inc1_m[2:0] = rml_irf_old_lo_cwp_m[2:0] + 3'b001;
assign slot_old_cwp_inc1_m_unused = slot_old_cwp_inc1_m[0];

assign slot_new_cwp_inc1_m[2:0] = rml_irf_new_lo_cwp_m[2:0] + 3'b001;
assign slot_new_cwp_inc1_m_unused = slot_new_cwp_inc1_m[0];

// New local/odd CWP should be:
// - (restore & (no_fill_exception | fill_exception):   CWP-1
// - (save & (no_exception | clean_window_exception)=
//   (save & (no_spill exception):                      CWP+1 
// - spill | spill_flush:                               CWP+2
// - WRPR_CWP:                                          NEWCWP from WRPR
// - TLU CWP updates:                                   NEWCWP from TLU
// - otherwise:                                         new CWP = old CWP

assign rml_irf_new_lo_cwp_m[2:0]= ({3{(inst_vld_m & (restore_m | return_consider_m))                                                        }} & cwp_dec1_m[2:0]        ) |
				  ({3{(inst_vld_m & save_m & ~spill_detected_m)                                                             }} & cwp_inc1_m[2:0]        ) |
				  ({3{(inst_vld_m & (save_m | flushw_m) & spill_detected_m)                                                 }} & cwp_inc2_cansave_m[2:0]) |
				  ({3{ pr_wt_m                                                                                              }} & pr_new_cwp_wt[2:0]     ) |
				  ({3{ trap_ccr_cwp_valid                                                                                   }} & trap_cwp[2:0]          ) |  
				  ({3{(~(inst_vld_m & (restore_m | return_consider_m | save_m | flushw_m)) & ~pr_wt_m & ~trap_ccr_cwp_valid)}} & cwp_m[2:0]             );

                     
// New even CWP should be:
// - restore/return & (no_fill_exception | fill_exception):    CWP
// - save & (no_exception | clean_window_exception)=
//   (save & (not_spill exception):                            CWP+2 
// - trap_ccr_cwp_valid_m:                                     (new CWP passed down)+1
// - otherwise:                                                new CWP = old CWP

assign new_e_cwp_m[2:1] = ({2{ (inst_vld_m & (restore_m | return_consider_m))}}                    & cwp_m[2:1]) |
                          ({2{ (inst_vld_m & save_m & ~spill_detected_m)}}                         & cwp_inc2_m[2:1]) |
                          ({2{  make_2nd_window_slot}}                                             & slot_new_cwp_inc1_m[2:1])|
                          ({2{~(inst_vld_m & save_m & ~spill_detected_m) & ~make_2nd_window_slot}} & cwp_m[2:1]);

// Local CWP, swap if:
// - valid save instruction, no exception
// - clean_window_exception
// - spill_exception  
//   ==> valid save instruction, with/without exceptions
//
// - valid restore/return instruction, no exception
// - fill_exception   
//   ==> valid restore/return instruction, with/without exceptions
//
// - spill_flush_exception, implies:
//   ==> spill_detected_m, since save is all covered
//   ==> inst_vld_m, since flushw must be valid to generate the exception
//
// - WRPR to CWP -> pr_wt_m asserted
// - TLU CPWP updates -> trap_ccr_cwp_valid asserted

assign rml_irf_save_local_m	= (~mbi_run_lth &  inst_vld_m & ~exu_ecc_m & (save_m  | restore_m | return_consider_m | spill_detected_m)) |
				  (~mbi_run_lth &                            (pr_wt_m | trap_ccr_cwp_valid                              )) |
				  ( mbi_run_lth &  mbi_irf_save_en_p2                                                                    );


// Odd CWP, swap if:
// - odd  current CWP, with a valid save instruction and no exception
// - odd  current CWP, with a clean_window exception
//   ==> odd  current CWP, a valid save inst (all spills are covered later)
//
// - even current CWP, with a valid restore/return instruction and no exception
// - even current CWP, with a fill_window  exception
//   ==> even current CWP, with a valid restore/return instruction, with/without exceptions
//
// - spill_exception
// - WRPR to CWP -> pr_wt_m asserted
// - TLU CPWP updates -> trap_ccr_cwp_valid asserted


assign rml_irf_save_odd_m	= (~mbi_run_lth &  inst_vld_m & ~exu_ecc_m &  save_m                               &  cwp_m[0]) | 
				  (~mbi_run_lth &  inst_vld_m & ~exu_ecc_m & (restore_m | return_consider_m)       & ~cwp_m[0]) |
				  (~mbi_run_lth &                            (spill_detected_m | pr_wt_m | trap_ccr_cwp_valid)) |
				  ( mbi_run_lth &  mbi_irf_save_en_p2                                                         );

// Even CWP, swap if:
// - even current CWP, with a valid save instruction and no exception
// - even current CWP, with a clean_window exception
//   ==> odd  current CWP, a valid save inst and no spill (~cansave_is0_m)
//
// - odd  current CWP, with a valid restore/return instruction and no exception
// - odd  current CWP, with a fill_window  exception
//   ==> even current CWP, with a valid restore/return instruction, with/without exceptions
//
// - second round of window swaps

assign rml_irf_save_even_m	= (~mbi_run_lth &  inst_vld_m & ~exu_ecc_m &  save_m  &   ~cansave_is0_m           & ~cwp_m[0]) | 
				  (~mbi_run_lth &  inst_vld_m & ~exu_ecc_m & (restore_m |  return_consider_m)      &  cwp_m[0]) |
				  (~mbi_run_lth &                            (spill_detected_m | pr_wt_m | trap_ccr_cwp_valid)) |
				  ( mbi_run_lth &  mbi_irf_save_en_p2                                                         );


exu_rml_ctl_msff_ctl_macro__width_15	i_rml_restore_en_ff	 (
 .scan_in(i_rml_restore_en_ff_scanin),
 .scan_out(i_rml_restore_en_ff_scanout),
 .l1clk(l1clk_pm1),
 .din  ({rml_irf_save_even_m		,
	 rml_irf_save_odd_m		,
	 rml_irf_save_local_m		,
	 rml_irf_save_global		,
	 rml_irf_global_tid[1:0]	,
	 rml_irf_cwpswap_tid_m[1:0]	,
	 new_e_cwp_m[2:1]		,
	 rml_irf_new_lo_cwp_m[2:0]	,
	 rml_irf_new_agp[1:0]}		),
 .dout ({rml_irf_restore_even_b_ff	,
	 rml_irf_restore_odd_b_ff	,
	 rml_irf_restore_local_b_ff	,
	 rml_irf_restore_global_ff	,
	 rml_irf_global_tid_ff[1:0]	,
	 raw_irf_cwpswap_tid_b[1:0]	,
	 raw_irf_new_e_cwp_b[2:1]	,
	 raw_irf_new_lo_cwp_b[2:0]	,
	 rml_irf_new_agp_ff[1:0]}	),
  .siclk(siclk),
  .soclk(soclk));

assign rml_irf_cwpswap_tid_b[1:0]	= ({2{~mbi_run_lth                         }} & raw_irf_cwpswap_tid_b[1:0]) |
					  ({2{ mbi_run_lth & ~mbi_irf_restore_en_p2}} & mbi_addr_lth[1:0]         ) |
					  ({2{ mbi_run_lth &  mbi_irf_restore_en_p2}} & mbi_addr_lth[6:5]         );

assign rml_irf_new_lo_cwp_b[2:0]	= ({3{~mbi_run_lth                         }} & raw_irf_new_lo_cwp_b[2:0] ) |
					  ({3{ mbi_run_lth & ~mbi_irf_restore_en_p2}} & mbi_addr_lth[3:1]         ) |
					  ({3{ mbi_run_lth &  mbi_irf_restore_en_p2}} & mbi_addr_lth[9:7]         );

assign rml_irf_new_e_cwp_b[2:1]		= ({2{~mbi_run_lth                         }} & raw_irf_new_e_cwp_b[2:1]  ) |
					  ({2{ mbi_run_lth & ~mbi_irf_restore_en_p2}} & mbi_addr_lth[4:3]         ) |
					  ({2{ mbi_run_lth &  mbi_irf_restore_en_p2}} & mbi_addr_lth[9:8]         );


assign rml_irf_restore_even_b		= (~mbi_run_lth &  rml_irf_restore_even_b_ff  & ~tlu_flush_exu_b) | ( mbi_run_lth &  mbi_irf_restore_en_p2);
assign rml_irf_restore_odd_b		= (~mbi_run_lth &  rml_irf_restore_odd_b_ff   & ~tlu_flush_exu_b) | ( mbi_run_lth &  mbi_irf_restore_en_p2);
assign rml_irf_restore_local_b		= (~mbi_run_lth &  rml_irf_restore_local_b_ff & ~tlu_flush_exu_b) | ( mbi_run_lth &  mbi_irf_restore_en_p2);
assign rml_irf_restore_global		= (~mbi_run_lth &  rml_irf_restore_global_ff                    ) | ( mbi_run_lth &  mbi_irf_restore_en_p2);

// Make sure no save/restore to the same thread at the same time


// generate next cycle CWP values
// -----------------------------------------------------
// replicate the window swap destination generated by IRF control

assign cwp_update_m   = rml_irf_save_local_m & ~exu_ecc_m;
assign cwp_tid_m[1:0] = rml_irf_cwpswap_tid_m[1:0];
assign cwp_new_m[2:0] = rml_irf_new_lo_cwp_m[2:0];

exu_rml_ctl_msff_ctl_macro__width_6	cwp_m2b		 (
 .scan_in(cwp_m2b_scanin),
 .scan_out(cwp_m2b_scanout),
 .l1clk(l1clk_pm1),
 .din  ({cwp_tid_m[1:0], cwp_new_m[2:0], cwp_update_m}),
 .dout ({cwp_tid_b[1:0], cwp_new_b[2:0], cwp_update_b}),
  .siclk(siclk),
  .soclk(soclk));

// Cancel CWP updates if the current instruction is being flushed
assign cwp_update_no_flush_exu_b = cwp_update_b & ~tlu_flush_exu_b & ~dec_flush_b;

exu_rml_ctl_msff_ctl_macro__width_6	cwp_b2w		 (
 .scan_in(cwp_b2w_scanin),
 .scan_out(cwp_b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({cwp_tid_b[1:0], cwp_new_b[2:0], cwp_update_no_flush_exu_b}),
 .dout ({cwp_tid_w[1:0], cwp_new_w[2:0], cwp_update_w}),
  .siclk(siclk),
  .soclk(soclk));

assign cwp_next_w[2:0] = cwp_new_w[2:0];

assign cwp_we_w[0] = (~cwp_tid_w[1]) & (~cwp_tid_w[0]) & (cwp_update_w);
assign cwp_we_w[1] = (~cwp_tid_w[1]) & ( cwp_tid_w[0]) & (cwp_update_w);
assign cwp_we_w[2] = ( cwp_tid_w[1]) & (~cwp_tid_w[0]) & (cwp_update_w);
assign cwp_we_w[3] = ( cwp_tid_w[1]) & ( cwp_tid_w[0]) & (cwp_update_w);

assign cwp_pr_we[0] = (~wrpr_cwp_tid_hold[1]) & (~wrpr_cwp_tid_hold[0]) & (pr_wt_m);
assign cwp_pr_we[1] = (~wrpr_cwp_tid_hold[1]) & ( wrpr_cwp_tid_hold[0]) & (pr_wt_m);
assign cwp_pr_we[2] = ( wrpr_cwp_tid_hold[1]) & (~wrpr_cwp_tid_hold[0]) & (pr_wt_m);
assign cwp_pr_we[3] = ( wrpr_cwp_tid_hold[1]) & ( wrpr_cwp_tid_hold[0]) & (pr_wt_m);

assign cwp_thr0_next[2:0]	= ({3{ cwp_we_w[0] }}                     & cwp_next_w[2:0]   ) |
				  ({3{ cwp_pr_we[0]}}                     & pr_new_cwp_wt[2:0]) |
				  ({3{~cwp_pr_we[0]}} & {3{~cwp_we_w[0]}} & cwp_thr0[2:0]     );

assign cwp_thr1_next[2:0]	= ({3{ cwp_we_w[1] }}                     & cwp_next_w[2:0]   ) |
				  ({3{ cwp_pr_we[1]}}                     & pr_new_cwp_wt[2:0]) |
				  ({3{~cwp_pr_we[1]}} & {3{~cwp_we_w[1]}} & cwp_thr1[2:0]     );

assign cwp_thr2_next[2:0]	= ({3{ cwp_we_w[2] }}                     & cwp_next_w[2:0]   ) |
				  ({3{ cwp_pr_we[2]}}                     & pr_new_cwp_wt[2:0]) |
				  ({3{~cwp_pr_we[2]}} & {3{~cwp_we_w[2]}} & cwp_thr2[2:0]     );

assign cwp_thr3_next[2:0]	= ({3{ cwp_we_w[3] }}                     & cwp_next_w[2:0]   ) |
				  ({3{ cwp_pr_we[3]}}                     & pr_new_cwp_wt[2:0]) |
				  ({3{~cwp_pr_we[3]}} & {3{~cwp_we_w[3]}} & cwp_thr3[2:0]     );


// Controls of Alternate Global Pointer
// -------------------------------------------------------

// Detect changes in thread being updated 
assign gl_changed_thr0 = (tlu_gl_thr0[1]^gl_thr0[1]) | (tlu_gl_thr0[0]^gl_thr0[0]);
assign gl_changed_thr1 = (tlu_gl_thr1[1]^gl_thr1[1]) | (tlu_gl_thr1[0]^gl_thr1[0]);
assign gl_changed_thr2 = (tlu_gl_thr2[1]^gl_thr2[1]) | (tlu_gl_thr2[0]^gl_thr2[0]);
assign gl_changed_thr3 = (tlu_gl_thr3[1]^gl_thr3[1]) | (tlu_gl_thr3[0]^gl_thr3[0]);

assign gl_we[0] =  gl_changed_thr0;
assign gl_we[1] =  gl_changed_thr1;
assign gl_we[2] =  gl_changed_thr2;
assign gl_we[3] =  gl_changed_thr3;

// No more than one GL changes per cycle to RML

// Never have GL changes in the same thread trailing each other within 3 cycles


assign gl_tid[0] = gl_we[1] | gl_we[3];
assign gl_tid[1] = gl_we[2] | gl_we[3];

assign gl_changed = gl_changed_thr0 | gl_changed_thr1 | gl_changed_thr2 |
                    gl_changed_thr3;

assign gl_thr0_next[1:0] = ({2{  gl_we[0]}} & tlu_gl_thr0[1:0]) | 
                           ({2{ ~gl_we[0]}} &     gl_thr0[1:0]);
assign gl_thr1_next[1:0] = ({2{  gl_we[1]}} & tlu_gl_thr1[1:0]) | 
                           ({2{ ~gl_we[1]}} &     gl_thr1[1:0]);
assign gl_thr2_next[1:0] = ({2{  gl_we[2]}} & tlu_gl_thr2[1:0]) | 
                           ({2{ ~gl_we[2]}} &     gl_thr2[1:0]);
assign gl_thr3_next[1:0] = ({2{  gl_we[3]}} & tlu_gl_thr3[1:0]) | 
                           ({2{ ~gl_we[3]}} &     gl_thr3[1:0]);


exu_rml_ctl_msff_ctl_macro__width_8	old_gl_ptr		 (		
 .scan_in(old_gl_ptr_wmr_scanin),
 .scan_out(old_gl_ptr_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  ({gl_thr0_next[1:0],
	 gl_thr1_next[1:0],
	 gl_thr2_next[1:0],
	 gl_thr3_next[1:0]}),
 .dout ({gl_thr0[1:0],
	 gl_thr1[1:0],
	 gl_thr2[1:0],
	 gl_thr3[1:0]}),
  .soclk(soclk));


// Set IRF controls
// - if no valid signal, rml_irf_old_agp & rml_irf_new_agp follows [tlu_gl]

assign rml_irf_save_global	= (   ~mbi_run_lth   &  gl_changed        ) |
				  (    mbi_run_lth   &  mbi_irf_save_en_p2);

assign rml_irf_global_tid[1:0]	= ({2{~mbi_run_lth}} &  gl_tid[1:0]       ) |
				  ({2{ mbi_run_lth}} &  mbi_addr_lth[6:5] );

assign rml_irf_old_agp[1:0] 	= ({2{~mbi_run_lth & gl_we[0]}} &     gl_thr0[1:0] ) |
				  ({2{~mbi_run_lth & gl_we[1]}} &     gl_thr1[1:0] ) |
				  ({2{~mbi_run_lth & gl_we[2]}} &     gl_thr2[1:0] ) |
				  ({2{~mbi_run_lth & gl_we[3]}} &     gl_thr3[1:0] ) |
				  ({2{ mbi_run_lth           }} & mbi_addr_lth[8:7]);

assign rml_irf_new_agp[1:0]	= ({2{~mbi_run_lth & gl_we[0]}} & tlu_gl_thr0[1:0] ) |
				  ({2{~mbi_run_lth & gl_we[1]}} & tlu_gl_thr1[1:0] ) |
				  ({2{~mbi_run_lth & gl_we[2]}} & tlu_gl_thr2[1:0] ) |
				  ({2{~mbi_run_lth & gl_we[3]}} & tlu_gl_thr3[1:0] ) |
				  ({2{ mbi_run_lth           }} & mbi_addr_lth[8:7]);


// =============================================================================
// State machines to keep track of priviledged register updates
// -----------------------------------------------------------------------------
// PR		   	CANSAVE     CANRESTORE   OTHERWIN   CLEANWIN      CWP
// -----------------------------------------------------------------------------
// Reset		3'b110      3'b000       3'b000     3'b111        3'b000
//
// Save                 dec	    inc            -          -            inc
//
// Restore		inc	    dec	           -          -            dec
//
// Saved 		inc         (OTHERWIN    (!=0)?dec    -             -
//                                   =0)?dec
//
// Restored		(OTHERWIN   inc          (!=0)?dec  (!=NWIN)?inc    -
//			 =0)?dec 
//
// Allclean (sun4v)     -           -              -          NWIN-1        -
//
// Otherw   (sun4v)     -           0            CANRESTORE   -             -
//
// Normalw  (sun4v)     -           OTHERWIN       0          -             -
//
// Invalw   (sun4v)     NWIN-2      0              0          -             -
//
// Return		inc         dec            -          -            dec
//
// Flushw               -           -              -          -             -
//
// fill_trap		      CWP <- (CWP + CANSAVE + 2) mod NWINDOWS
//
// spill_trap		      CWP <- (CWP - 1) mod NWINDOWS
//	     
// clean_window	    	      CWP <- (CWP + 1) mod NWINDOWS
// -----------------------------------------------------------------------------
// - Implemented in W stage, before it is written back at the end of W stage

assign cansave_dec1_w[2:0] = cansave_w[2:0] - 3'b001;
assign cansave_inc1_w[2:0] = cansave_w[2:0] + 3'b001;
assign canrestore_dec1_w[2:0] = canrestore_w[2:0] - 3'b001;
assign canrestore_inc1_w[2:0] = canrestore_w[2:0] + 3'b001;

assign otherwin_dec1_w[2:0] = otherwin_w[2:0] - 3'b001;
assign cleanwin_inc1_w[2:0] = cleanwin_w[2:0] + 3'b001;

assign otherwin_is0_w = ~(otherwin_w[2] | otherwin_w[1] | otherwin_w[0]);
assign cleanwin_is111_w = cleanwin_w[2] & cleanwin_w[1] & cleanwin_w[0] ;


// generate next cycle CANSAVE values
// ------------------------------------
// - use the table above to decide whether to inc/dec the counter
// - needs to mux in ASR data path to write to the PR

assign cansave_inc_w   = inst_vld_w & (restore_w | saved_w | return_w) ;
assign cansave_dec_w   = inst_vld_w & 
                         (save_w | (restored_w & otherwin_is0_w));
assign cansave_reset_w = inst_vld_w & invalw_w;
assign cansave_update_w = cansave_inc_w | cansave_dec_w | cansave_reset_w;

assign cansave_next_w[2:0] = ({3{ cansave_inc_w   }} & cansave_inc1_w[2:0]) |
			     ({3{ cansave_dec_w   }} & cansave_dec1_w[2:0]) |
                             ({3{ cansave_reset_w }} & 3'b110             ) |
                             ({3{~cansave_update_w}} & cansave_w     [2:0]) ;

assign cansave_we_w[0] = (tid_w[1:0] == 2'b00) & (cansave_update_w);
assign cansave_we_w[1] = (tid_w[1:0] == 2'b01) & (cansave_update_w);
assign cansave_we_w[2] = (tid_w[1:0] == 2'b10) & (cansave_update_w);
assign cansave_we_w[3] = (tid_w[1:0] == 2'b11) & (cansave_update_w);

assign cansave_pr_we[0] = (pr_tid_ctl[1:0] == 2'b00) & (pr_wt_cansave_ctl);
assign cansave_pr_we[1] = (pr_tid_ctl[1:0] == 2'b01) & (pr_wt_cansave_ctl);
assign cansave_pr_we[2] = (pr_tid_ctl[1:0] == 2'b10) & (pr_wt_cansave_ctl);
assign cansave_pr_we[3] = (pr_tid_ctl[1:0] == 2'b11) & (pr_wt_cansave_ctl);


// generate next cycle CANRESTORE values
// ---------------------------------------
// - use the table above to decide whether to inc/dec the counter
// - needs to mux in ASI data path to write to the PR

assign canrestore_inc_w = inst_vld_w & (save_w | restored_w);
assign canrestore_dec_w = inst_vld_w & 
			  (restore_w | (saved_w & otherwin_is0_w) | return_w);
assign canrestore_0_w   = inst_vld_w & (otherw_w | invalw_w);
assign canrestore_otherwin_w = inst_vld_w & normalw_w;
assign canrestore_update_w = canrestore_inc_w | canrestore_dec_w |
                             canrestore_0_w   | canrestore_otherwin_w;

assign canrestore_next_w[2:0] = ({3{ canrestore_inc_w     }}   & canrestore_inc1_w[2:0]) |
			        ({3{ canrestore_dec_w     }}   & canrestore_dec1_w[2:0]) |
			        ({3{ canrestore_0_w       }}   & 3'b000                ) |
			        ({3{ canrestore_otherwin_w}} & canrestore_normalwin_data_w[2:0]) |
                                ({3{~canrestore_update_w  }} & canrestore_w  [2:0]) ;

assign canrestore_normalwin_data_w[2:0] = {3{(~tid_w[1]) & (~tid_w[0])}} & (otherwin_thr0[2:0]) |
                                          {3{(~tid_w[1]) & ( tid_w[0])}} & (otherwin_thr1[2:0]) |
                                          {3{( tid_w[1]) & (~tid_w[0])}} & (otherwin_thr2[2:0]) |
                                          {3{( tid_w[1]) & ( tid_w[0])}} & (otherwin_thr3[2:0]) ;

assign canrestore_we_w[0] = (tid_w[1:0] == 2'b00) & (canrestore_update_w);
assign canrestore_we_w[1] = (tid_w[1:0] == 2'b01) & (canrestore_update_w);
assign canrestore_we_w[2] = (tid_w[1:0] == 2'b10) & (canrestore_update_w);
assign canrestore_we_w[3] = (tid_w[1:0] == 2'b11) & (canrestore_update_w);

assign canrestore_pr_we[0] = (pr_tid_ctl[1:0] == 2'b00) & (pr_wt_canrestore_ctl);
assign canrestore_pr_we[1] = (pr_tid_ctl[1:0] == 2'b01) & (pr_wt_canrestore_ctl);
assign canrestore_pr_we[2] = (pr_tid_ctl[1:0] == 2'b10) & (pr_wt_canrestore_ctl);
assign canrestore_pr_we[3] = (pr_tid_ctl[1:0] == 2'b11) & (pr_wt_canrestore_ctl);


// generate next cycle OTHERWIN values
// ---------------------------------------
assign otherwin_dec_w = inst_vld_w & (~otherwin_is0_w) & 
                        (saved_w | restored_w);
assign otherwin_0_w = inst_vld_w & (normalw_w | invalw_w);
assign otherwin_canrestore_w = inst_vld_w & otherw_w;
assign otherwin_update_w = otherwin_dec_w | otherwin_0_w | otherwin_canrestore_w;

assign otherwin_next_w[2:0] = ({3{ otherwin_dec_w       }}  & otherwin_dec1_w[2:0]      ) |
                              ({3{ otherwin_0_w         }}  & 3'b000                    ) |
                              ({3{ otherwin_canrestore_w}} & otherwin_otherw_data_w[2:0]) |
                              ({3{~otherwin_update_w    }} & otherwin_w[2:0]            ) ;

assign otherwin_we_w[0] = (~tid_w[1]) & (~tid_w[0]) & (otherwin_update_w);
assign otherwin_we_w[1] = (~tid_w[1]) & ( tid_w[0]) & (otherwin_update_w);
assign otherwin_we_w[2] = ( tid_w[1]) & (~tid_w[0]) & (otherwin_update_w);
assign otherwin_we_w[3] = ( tid_w[1]) & ( tid_w[0]) & (otherwin_update_w);

assign otherwin_otherw_data_w[2:0] = {3{tid_w[1:0] == 2'b00}} & (canrestore_thr0[2:0]) |
                                     {3{tid_w[1:0] == 2'b01}} & (canrestore_thr1[2:0]) |
                                     {3{tid_w[1:0] == 2'b10}} & (canrestore_thr2[2:0]) |
                                     {3{tid_w[1:0] == 2'b11}} & (canrestore_thr3[2:0]) ;

assign otherwin_pr_we[0] = (pr_tid_ctl[1:0] == 2'b00) & (pr_wt_otherwin_ctl);
assign otherwin_pr_we[1] = (pr_tid_ctl[1:0] == 2'b01) & (pr_wt_otherwin_ctl);
assign otherwin_pr_we[2] = (pr_tid_ctl[1:0] == 2'b10) & (pr_wt_otherwin_ctl);
assign otherwin_pr_we[3] = (pr_tid_ctl[1:0] == 2'b11) & (pr_wt_otherwin_ctl);


// generate next cycle CLEANWIN values
// ---------------------------------------
assign cleanwin_inc_w = inst_vld_w & (~cleanwin_is111_w) & restored_w;
assign cleanwin_reset_w = inst_vld_w & allclean_w;
assign cleanwin_update_w = cleanwin_inc_w | cleanwin_reset_w;

assign cleanwin_next_w[2:0] = ({3{ cleanwin_inc_w   }} & cleanwin_inc1_w[2:0]) |
                              ({3{ cleanwin_reset_w }} & 3'b111              ) |
                              ({3{~cleanwin_update_w}} & cleanwin_w     [2:0]) ;

assign cleanwin_we_w[0] = (tid_w[1:0] == 2'b00) & (cleanwin_update_w);
assign cleanwin_we_w[1] = (tid_w[1:0] == 2'b01) & (cleanwin_update_w);
assign cleanwin_we_w[2] = (tid_w[1:0] == 2'b10) & (cleanwin_update_w);
assign cleanwin_we_w[3] = (tid_w[1:0] == 2'b11) & (cleanwin_update_w);

assign cleanwin_pr_we[0] = (pr_tid_ctl[1:0] == 2'b00) & (pr_wt_cleanwin_ctl);
assign cleanwin_pr_we[1] = (pr_tid_ctl[1:0] == 2'b01) & (pr_wt_cleanwin_ctl);
assign cleanwin_pr_we[2] = (pr_tid_ctl[1:0] == 2'b10) & (pr_wt_cleanwin_ctl);
assign cleanwin_pr_we[3] = (pr_tid_ctl[1:0] == 2'b11) & (pr_wt_cleanwin_ctl);


// generate next cycle WSTATE values
// ---------------------------------------
assign wstate_pr_we[0] = (pr_tid_ctl[1:0] == 2'b00) & (pr_wt_wstate_ctl);
assign wstate_pr_we[1] = (pr_tid_ctl[1:0] == 2'b01) & (pr_wt_wstate_ctl);
assign wstate_pr_we[2] = (pr_tid_ctl[1:0] == 2'b10) & (pr_wt_wstate_ctl);
assign wstate_pr_we[3] = (pr_tid_ctl[1:0] == 2'b11) & (pr_wt_wstate_ctl);


// =============================================================================
// Specutively produce oddwin indicator for Pick-stage to translate 
// virtual architectural integer register address to physical address
// (involves swapping ins/outs registers for odd window pointers)
// ---------------------------------------------------------------------
// only requires LSB of CWPs
// - keeps a copy of CWP LSB in B stage
// - update oddwin indicator whenever CWP is updated 
// - revert oddwin indicator to architected state during a flush
// - otherwise, hold previous value

assign cwp_new_update[0] = cwp_update_m	& (~cwp_tid_m[1]) & (~cwp_tid_m[0]);
assign cwp_new_update[1] = cwp_update_m	& (~cwp_tid_m[1]) & ( cwp_tid_m[0]);
assign cwp_new_update[2] = cwp_update_m	& ( cwp_tid_m[1]) & (~cwp_tid_m[0]);
assign cwp_new_update[3] = cwp_update_m	& ( cwp_tid_m[1]) & ( cwp_tid_m[0]);

assign cwp_flushed   [0] = (flush_exu_w | dec_flush_w) & (~tid_w[1]) & (~tid_w[0]);
assign cwp_flushed   [1] = (flush_exu_w | dec_flush_w) & (~tid_w[1]) & ( tid_w[0]);
assign cwp_flushed   [2] = (flush_exu_w | dec_flush_w) & ( tid_w[1]) & (~tid_w[0]);
assign cwp_flushed   [3] = (flush_exu_w | dec_flush_w) & ( tid_w[1]) & ( tid_w[0]);

assign cwp_oddwin_next[0] = ( cwp_new_update[0] & ~cwp_flushed[0] & cwp_new_m   [0]) |
                            (~cwp_new_update[0] & ~cwp_flushed[0] & cwp_oddwin_b[0]) |
                            ( cwp_flushed   [0] &  cwp_thr0   [0]);

assign cwp_oddwin_next[1] = ( cwp_new_update[1] & ~cwp_flushed[1] & cwp_new_m   [0]) |
                            (~cwp_new_update[1] & ~cwp_flushed[1] & cwp_oddwin_b[1]) |
                            ( cwp_flushed   [1] &  cwp_thr1   [0]);

assign cwp_oddwin_next[2] = ( cwp_new_update[2] & ~cwp_flushed[2] & cwp_new_m   [0]) |
                            (~cwp_new_update[2] & ~cwp_flushed[2] & cwp_oddwin_b[2]) |
                            ( cwp_flushed   [2] &  cwp_thr2   [0]);

assign cwp_oddwin_next[3] = ( cwp_new_update[3] & ~cwp_flushed[3] & cwp_new_m   [0]) |
                            (~cwp_new_update[3] & ~cwp_flushed[3] & cwp_oddwin_b[3]) |
                            ( cwp_flushed   [3] &  cwp_thr3   [0]);


exu_rml_ctl_msff_ctl_macro__width_4	cwp_speculative		 (
 .scan_in(cwp_speculative_scanin),
 .scan_out(cwp_speculative_scanout),
 .l1clk(l1clk_pm1),
 .din  ({cwp_oddwin_next[3:0]}),
 .dout ({cwp_oddwin_b[3:0]}),
  .siclk(siclk),
  .soclk(soclk));

assign exu_oddwin_b[3:0] = cwp_oddwin_b[3:0];


// =============================================================================
// Privileged Registers
// -----------------------------------------------------------------------------
// - maintains legal state of interger-register-window  
//   related privileged registers (See pages 57-59)
// - allow RDPR/WRPR to read and write to these registers
// - PRs read in D stage, and written in W stage
// - 4 sets of PR, one set for each thread in EXU 
// - EXU only handles one thread's PR accesses per stage
// - needs to arbitrate between the threads
//
//     PR name          init. value
//   ------------------------------------------
//     CANSAVE		110
//     CANRESTORE	000
//     OTHERWIN		000
//     CLEANWIN		111
//     WSTATE		000000
//     CWP		000
//


// - CANSAVE Privileged Register
//   ----------------------------

// Only one thread can be writen each cycle
// Uses write enable to control which register to update

assign cansave_thr0_next[2:0] = ({3{ cansave_we_w[0] }}                         & cansave_next_w[2:0]) |
				({3{ cansave_pr_we[0]}}                         & data_1f[2:0]       ) |
                                ({3{~cansave_pr_we[0]}} & {3{~cansave_we_w[0]}} & cansave_thr0[2:0]  );

assign cansave_thr1_next[2:0] = ({3{ cansave_we_w[1] }}                         & cansave_next_w[2:0]) |
				({3{ cansave_pr_we[1]}}                         & data_1f[2:0]       ) |
                                ({3{~cansave_pr_we[1]}} & {3{~cansave_we_w[1]}} & cansave_thr1[2:0]  );

assign cansave_thr2_next[2:0] = ({3{ cansave_we_w[2] }}                         & cansave_next_w[2:0]) |
				({3{ cansave_pr_we[2]}}                         & data_1f[2:0]       ) |
                                ({3{~cansave_pr_we[2]}} & {3{~cansave_we_w[2]}} & cansave_thr2[2:0]  );

assign cansave_thr3_next[2:0] = ({3{ cansave_we_w[3] }}                         & cansave_next_w[2:0]) |
				({3{ cansave_pr_we[3]}}                         & data_1f[2:0]       ) |
                                ({3{~cansave_pr_we[3]}} & {3{~cansave_we_w[3]}} & cansave_thr3[2:0]  );

// Stores negated CANSAVE values
// - Use POR to reset the architectural PR values to 3'b110
assign cansave_thr0_next_l[2:1] = ~cansave_thr0_next[2:1];
assign cansave_thr1_next_l[2:1] = ~cansave_thr1_next[2:1];
assign cansave_thr2_next_l[2:1] = ~cansave_thr2_next[2:1];
assign cansave_thr3_next_l[2:1] = ~cansave_thr3_next[2:1];

exu_rml_ctl_msff_ctl_macro__width_12	cansave_pr		 (		
 .scan_in(cansave_pr_wmr_scanin),
 .scan_out(cansave_pr_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  ({cansave_thr0_next_l[2:1], cansave_thr0_next[0],
         cansave_thr1_next_l[2:1], cansave_thr1_next[0],
         cansave_thr2_next_l[2:1], cansave_thr2_next[0],
         cansave_thr3_next_l[2:1], cansave_thr3_next[0]}),
 .dout ({cansave_thr0_l[2:1],      cansave_thr0[0],
         cansave_thr1_l[2:1],      cansave_thr1[0],
         cansave_thr2_l[2:1],      cansave_thr2[0],
         cansave_thr3_l[2:1],      cansave_thr3[0]}),
  .soclk(soclk));

assign cansave_thr0[2:1] = ~cansave_thr0_l[2:1];
assign cansave_thr1[2:1] = ~cansave_thr1_l[2:1];
assign cansave_thr2[2:1] = ~cansave_thr2_l[2:1];
assign cansave_thr3[2:1] = ~cansave_thr3_l[2:1];

// Output the cansave value of the current thread
assign cansave_e[2:0] = ({3{tid_e[1:0] == 2'b00}} & cansave_thr0[2:0]) |
                        ({3{tid_e[1:0] == 2'b01}} & cansave_thr1[2:0]) | 
                        ({3{tid_e[1:0] == 2'b10}} & cansave_thr2[2:0]) | 
                        ({3{tid_e[1:0] == 2'b11}} & cansave_thr3[2:0]) ;

assign cansave_pr_rd[2:0] = ({3{pr_tid_ctl[1:0] == 2'b00}} & cansave_thr0[2:0]) |
                            ({3{pr_tid_ctl[1:0] == 2'b01}} & cansave_thr1[2:0]) | 
                            ({3{pr_tid_ctl[1:0] == 2'b10}} & cansave_thr2[2:0]) | 
                            ({3{pr_tid_ctl[1:0] == 2'b11}} & cansave_thr3[2:0]) ;

exu_rml_ctl_msff_ctl_macro__width_9	cansave_e2m2b2w		 (
 .scan_in(cansave_e2m2b2w_scanin),
 .scan_out(cansave_e2m2b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({cansave_e[2:0], cansave_m[2:0], cansave_b[2:0]}),
 .dout ({cansave_m[2:0], cansave_b[2:0], cansave_w[2:0]}),
  .siclk(siclk),
  .soclk(soclk));


// - CANRESTORE Privileged Register
//   -------------------------------

// Only one thread can be writen each cycle
// Uses write enable to control which register to update

assign canrestore_thr0_next[2:0] = ({3{ canrestore_we_w[0] }}                            & canrestore_next_w[2:0]) |
                                   ({3{ canrestore_pr_we[0]}}                            & data_1f[2:0]          ) |
                                   ({3{~canrestore_pr_we[0]}} & {3{~canrestore_we_w[0]}} & canrestore_thr0[2:0]  );

assign canrestore_thr1_next[2:0] = ({3{ canrestore_we_w[1] }}                            & canrestore_next_w[2:0]) |
                                   ({3{ canrestore_pr_we[1]}}                            & data_1f[2:0]          ) |
                                   ({3{~canrestore_pr_we[1]}} & {3{~canrestore_we_w[1]}} & canrestore_thr1[2:0]  );

assign canrestore_thr2_next[2:0] = ({3{ canrestore_we_w[2] }}                            & canrestore_next_w[2:0]) |
                                   ({3{ canrestore_pr_we[2]}}                            & data_1f[2:0]          ) |
                                   ({3{~canrestore_pr_we[2]}} & {3{~canrestore_we_w[2]}} & canrestore_thr2[2:0]  );

assign canrestore_thr3_next[2:0] = ({3{ canrestore_we_w[3] }}                            & canrestore_next_w[2:0]) |
                                   ({3{ canrestore_pr_we[3]}}                            & data_1f[2:0]          ) |
                                   ({3{~canrestore_pr_we[3]}} & {3{~canrestore_we_w[3]}} & canrestore_thr3[2:0]  );

exu_rml_ctl_msff_ctl_macro__width_12	canrestore_pr		 (	
 .scan_in(canrestore_pr_wmr_scanin),
 .scan_out(canrestore_pr_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  ({canrestore_thr0_next[2:0],
         canrestore_thr1_next[2:0],
         canrestore_thr2_next[2:0],
         canrestore_thr3_next[2:0]}),
 .dout ({canrestore_thr0[2:0],
         canrestore_thr1[2:0],
         canrestore_thr2[2:0],
         canrestore_thr3[2:0]}),
  .soclk(soclk));

// Output the canrestore value of the current thread
assign canrestore_e[2:0] = ({3{tid_e[1:0] == 2'b00}} & canrestore_thr0[2:0]) |
                           ({3{tid_e[1:0] == 2'b01}} & canrestore_thr1[2:0]) | 
                           ({3{tid_e[1:0] == 2'b10}} & canrestore_thr2[2:0]) | 
                           ({3{tid_e[1:0] == 2'b11}} & canrestore_thr3[2:0]) ;

assign canrestore_pr_rd[2:0] = ({3{pr_tid_ctl[1:0] == 2'b00}} & canrestore_thr0[2:0]) |
                               ({3{pr_tid_ctl[1:0] == 2'b01}} & canrestore_thr1[2:0]) | 
                               ({3{pr_tid_ctl[1:0] == 2'b10}} & canrestore_thr2[2:0]) | 
                               ({3{pr_tid_ctl[1:0] == 2'b11}} & canrestore_thr3[2:0]) ;

exu_rml_ctl_msff_ctl_macro__width_9	canrestore_e2m2b2w	 (
 .scan_in(canrestore_e2m2b2w_scanin),
 .scan_out(canrestore_e2m2b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({canrestore_e[2:0], canrestore_m[2:0], canrestore_b[2:0]}),
 .dout ({canrestore_m[2:0], canrestore_b[2:0], canrestore_w[2:0]}),
  .siclk(siclk),
  .soclk(soclk));


// - OTHERWIN Privileged Register
//   -----------------------------

// Only one thread can be writen each cycle
// Uses write enable to control which register to update

assign otherwin_thr0_next[2:0] = ({3{ otherwin_we_w[0] }}                          & otherwin_next_w[2:0]) |
                                 ({3{ otherwin_pr_we[0]}}                          & data_1f        [2:0]) |
                                 ({3{~otherwin_pr_we[0]}} & {3{~otherwin_we_w[0]}} & otherwin_thr0  [2:0]);

assign otherwin_thr1_next[2:0] = ({3{ otherwin_we_w[1] }}                          & otherwin_next_w[2:0]) |
                                 ({3{ otherwin_pr_we[1]}}                          & data_1f        [2:0]) |
                                 ({3{~otherwin_pr_we[1]}} & {3{~otherwin_we_w[1]}} & otherwin_thr1  [2:0]);

assign otherwin_thr2_next[2:0] = ({3{ otherwin_we_w[2] }}                          & otherwin_next_w[2:0]) |
                                 ({3{ otherwin_pr_we[2]}}                          & data_1f        [2:0]) |
                                 ({3{~otherwin_pr_we[2]}} & {3{~otherwin_we_w[2]}} & otherwin_thr2  [2:0]);

assign otherwin_thr3_next[2:0] = ({3{ otherwin_we_w[3] }}                          & otherwin_next_w[2:0]) |
                                 ({3{ otherwin_pr_we[3]}}                          & data_1f        [2:0]) |
                                 ({3{~otherwin_pr_we[3]}} & {3{~otherwin_we_w[3]}} & otherwin_thr3  [2:0]);

exu_rml_ctl_msff_ctl_macro__width_12	otherwin_pr		 (		
 .scan_in(otherwin_pr_wmr_scanin),
 .scan_out(otherwin_pr_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  ({otherwin_thr0_next[2:0],
         otherwin_thr1_next[2:0],
         otherwin_thr2_next[2:0],
         otherwin_thr3_next[2:0]}),
 .dout ({otherwin_thr0[2:0],
         otherwin_thr1[2:0],
         otherwin_thr2[2:0],
         otherwin_thr3[2:0]}),
  .soclk(soclk));

// Output the otherwin value of the current thread
assign otherwin_e[2:0] = ({3{tid_e[1:0] == 2'b00}} & otherwin_thr0[2:0]) |
                         ({3{tid_e[1:0] == 2'b01}} & otherwin_thr1[2:0]) | 
                         ({3{tid_e[1:0] == 2'b10}} & otherwin_thr2[2:0]) | 
                         ({3{tid_e[1:0] == 2'b11}} & otherwin_thr3[2:0]) ;

assign otherwin_pr_rd[2:0] = ({3{pr_tid_ctl[1:0] == 2'b00}} & otherwin_thr0[2:0]) |
                             ({3{pr_tid_ctl[1:0] == 2'b01}} & otherwin_thr1[2:0]) | 
                             ({3{pr_tid_ctl[1:0] == 2'b10}} & otherwin_thr2[2:0]) | 
                             ({3{pr_tid_ctl[1:0] == 2'b11}} & otherwin_thr3[2:0]) ;

exu_rml_ctl_msff_ctl_macro__width_9	otherwin_e2m2b2w	 (
 .scan_in(otherwin_e2m2b2w_scanin),
 .scan_out(otherwin_e2m2b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({otherwin_e[2:0], otherwin_m[2:0], otherwin_b[2:0]}),
 .dout ({otherwin_m[2:0], otherwin_b[2:0], otherwin_w[2:0]}),
  .siclk(siclk),
  .soclk(soclk));


// - CLEANWIN Privileged Register
//   ----------------------------
// Only one thread can be writen each cycle
// Uses write enable to control which register to update

assign cleanwin_thr0_next[2:0] = ({3{ cleanwin_we_w[0] }}                          & cleanwin_next_w[2:0]) |
                                 ({3{ cleanwin_pr_we[0]}}                          & data_1f        [2:0]) |
                                 ({3{~cleanwin_pr_we[0]}} & {3{~cleanwin_we_w[0]}} & cleanwin_thr0  [2:0]) ;

assign cleanwin_thr1_next[2:0] = ({3{ cleanwin_we_w[1] }}                          & cleanwin_next_w[2:0]) |
                                 ({3{ cleanwin_pr_we[1]}}                          & data_1f        [2:0]) |
                                 ({3{~cleanwin_pr_we[1]}} & {3{~cleanwin_we_w[1]}} & cleanwin_thr1  [2:0]) ;

assign cleanwin_thr2_next[2:0] = ({3{ cleanwin_we_w[2] }}                          & cleanwin_next_w[2:0]) |
                                 ({3{ cleanwin_pr_we[2]}}                          & data_1f        [2:0]) |
                                 ({3{~cleanwin_pr_we[2]}} & {3{~cleanwin_we_w[2]}} & cleanwin_thr2  [2:0]) ;

assign cleanwin_thr3_next[2:0] = ({3{ cleanwin_we_w[3] }}                          & cleanwin_next_w[2:0]) |
                                 ({3{ cleanwin_pr_we[3]}}                          & data_1f        [2:0]) |
                                 ({3{~cleanwin_pr_we[3]}} & {3{~cleanwin_we_w[3]}} & cleanwin_thr3  [2:0]) ;


// Stores negated CLEANWIN values
// - Use POR to reset the architectural PR values to 3'b111
assign cleanwin_thr0_next_l[2:0] = ~cleanwin_thr0_next[2:0];
assign cleanwin_thr1_next_l[2:0] = ~cleanwin_thr1_next[2:0];
assign cleanwin_thr2_next_l[2:0] = ~cleanwin_thr2_next[2:0];
assign cleanwin_thr3_next_l[2:0] = ~cleanwin_thr3_next[2:0];

exu_rml_ctl_msff_ctl_macro__width_12	cleanwin_pr		 (		
 .scan_in(cleanwin_pr_wmr_scanin),
 .scan_out(cleanwin_pr_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  ({cleanwin_thr0_next_l[2:0],
         cleanwin_thr1_next_l[2:0],
         cleanwin_thr2_next_l[2:0],
         cleanwin_thr3_next_l[2:0]}),
 .dout ({cleanwin_thr0_l[2:0],
         cleanwin_thr1_l[2:0],
         cleanwin_thr2_l[2:0],
         cleanwin_thr3_l[2:0]}),
  .soclk(soclk));

assign cleanwin_thr0[2:0] = ~cleanwin_thr0_l[2:0];
assign cleanwin_thr1[2:0] = ~cleanwin_thr1_l[2:0];
assign cleanwin_thr2[2:0] = ~cleanwin_thr2_l[2:0];
assign cleanwin_thr3[2:0] = ~cleanwin_thr3_l[2:0];

// Output the cleanwin value of the current thread
assign cleanwin_e[2:0] = ({3{tid_e[1:0] == 2'b00}} & cleanwin_thr0[2:0]) |
                         ({3{tid_e[1:0] == 2'b01}} & cleanwin_thr1[2:0]) | 
                         ({3{tid_e[1:0] == 2'b10}} & cleanwin_thr2[2:0]) | 
                         ({3{tid_e[1:0] == 2'b11}} & cleanwin_thr3[2:0]) ;

assign cleanwin_pr_rd[2:0] = ({3{pr_tid_ctl[1:0] == 2'b00}} & cleanwin_thr0[2:0]) |
                             ({3{pr_tid_ctl[1:0] == 2'b01}} & cleanwin_thr1[2:0]) | 
                             ({3{pr_tid_ctl[1:0] == 2'b10}} & cleanwin_thr2[2:0]) | 
                             ({3{pr_tid_ctl[1:0] == 2'b11}} & cleanwin_thr3[2:0]) ;


exu_rml_ctl_msff_ctl_macro__width_9	cleanwin_e2m2b2w	 (
 .scan_in(cleanwin_e2m2b2w_scanin),
 .scan_out(cleanwin_e2m2b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  ({cleanwin_e[2:0], cleanwin_m[2:0], cleanwin_b[2:0]}),
 .dout ({cleanwin_m[2:0], cleanwin_b[2:0], cleanwin_w[2:0]}),
  .siclk(siclk),
  .soclk(soclk));


// - WSTATE Privileged Register
//   -------------------------------

// Only one thread can be writen each cycle
// Uses write enable to control which register to update

assign wstate_thr0_next[5:0] = ({6{ wstate_pr_we[0]}} & data_1f      [5:0]) |
                               ({6{~wstate_pr_we[0]}} & wstate_thr0  [5:0]);

assign wstate_thr1_next[5:0] = ({6{ wstate_pr_we[1]}} & data_1f      [5:0]) |
                               ({6{~wstate_pr_we[1]}} & wstate_thr1  [5:0]);

assign wstate_thr2_next[5:0] = ({6{ wstate_pr_we[2]}} & data_1f      [5:0]) |
                               ({6{~wstate_pr_we[2]}} & wstate_thr2  [5:0]);

assign wstate_thr3_next[5:0] = ({6{ wstate_pr_we[3]}} & data_1f      [5:0]) |
                               ({6{~wstate_pr_we[3]}} & wstate_thr3  [5:0]);

exu_rml_ctl_msff_ctl_macro__width_24	wstate_pr	 (		
 .scan_in(wstate_pr_wmr_scanin),
 .scan_out(wstate_pr_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  ({wstate_thr0_next[5:0],
         wstate_thr1_next[5:0],
         wstate_thr2_next[5:0],
         wstate_thr3_next[5:0]}),
 .dout ({wstate_thr0[5:0],
         wstate_thr1[5:0],
         wstate_thr2[5:0],
         wstate_thr3[5:0]}),
  .soclk(soclk));

// Output the wstate value of the current thread
assign wstate_b[5:0] = ({6{tid_b[1:0] == 2'b00}} & wstate_thr0[5:0]) |
                       ({6{tid_b[1:0] == 2'b01}} & wstate_thr1[5:0]) | 
                       ({6{tid_b[1:0] == 2'b10}} & wstate_thr2[5:0]) | 
                       ({6{tid_b[1:0] == 2'b11}} & wstate_thr3[5:0]) ;


assign wstate_pr_rd[5:0] = ({6{pr_tid_ctl[1:0] == 2'b00}} & wstate_thr0[5:0]) |
                           ({6{pr_tid_ctl[1:0] == 2'b01}} & wstate_thr1[5:0]) | 
                           ({6{pr_tid_ctl[1:0] == 2'b10}} & wstate_thr2[5:0]) | 
                           ({6{pr_tid_ctl[1:0] == 2'b11}} & wstate_thr3[5:0]) ;


// - CWP Privileged Register
//   -------------------------------

// Only one thread can be writen each cycle
// Uses write enable to control which register to update

exu_rml_ctl_msff_ctl_macro__width_12	cwp_pr			 (		
 .scan_in(cwp_pr_wmr_scanin),
 .scan_out(cwp_pr_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk(l1clk_pm1),
 .din  ({cwp_thr0_next[2:0],
         cwp_thr1_next[2:0],
         cwp_thr2_next[2:0],
         cwp_thr3_next[2:0]}),
 .dout ({cwp_thr0[2:0],
         cwp_thr1[2:0],
         cwp_thr2[2:0],
         cwp_thr3[2:0]}),
  .soclk(soclk));

// Output the cwp value of the current thread
assign cwp_e[2:0] = ({3{tid_e[1:0] == 2'b00}} & cwp_thr0[2:0]) |
                    ({3{tid_e[1:0] == 2'b01}} & cwp_thr1[2:0]) | 
                    ({3{tid_e[1:0] == 2'b10}} & cwp_thr2[2:0]) | 
                    ({3{tid_e[1:0] == 2'b11}} & cwp_thr3[2:0]) ;

assign cwp_pr_rd[2:0] = ({3{pr_tid_ctl[1:0] == 2'b00}} & cwp_thr0[2:0]) |
                        ({3{pr_tid_ctl[1:0] == 2'b01}} & cwp_thr1[2:0]) | 
                        ({3{pr_tid_ctl[1:0] == 2'b10}} & cwp_thr2[2:0]) | 
                        ({3{pr_tid_ctl[1:0] == 2'b11}} & cwp_thr3[2:0]) ;

assign exu_cwp_thr0[2:0] = cwp_thr0[2:0];
assign exu_cwp_thr1[2:0] = cwp_thr1[2:0];
assign exu_cwp_thr2[2:0] = cwp_thr2[2:0];
assign exu_cwp_thr3[2:0] = cwp_thr3[2:0];

exu_rml_ctl_msff_ctl_macro__width_3	cwp_e2m2b2w		 (
 .scan_in(cwp_e2m2b2w_scanin),
 .scan_out(cwp_e2m2b2w_scanout),
 .l1clk(l1clk_pm1),
 .din  (cwp_e[2:0]),
 .dout (cwp_m[2:0]),
  .siclk(siclk),
  .soclk(soclk));


// =============================================================================
// Priviledged Registers ASI access
// =============================================================================
// - Control cycle and data cycles are interleaved
// - Control cycles are identified by a "1" in bit [64]
// - ASI reads and writes are single cycle operations
// - control is decoded in one cycle and data is directed in the next
// =============================================================================
// assertion: ASI access should not happen when there is valid instruction
//            in the pipeline.
// =============================================================================
// 
//
// Pipeline:
// --------------------------------------
// > latch incoming ctl/data packet
// --------------------------------------
// detect ctl relevence                |
// generate control                    |
//  (send ctl for IRF_ECC to pick)     |
// -------------------------          Data
// > Latch ctl                         |
// -------------------------           |
// setup read/write ctl in datapath    |
//                           <---------+
// -------------------------
// > read/write data
// -------------------------
// assemble return data packet
//
// -------------------------
// > ASI Data out
// -------------------------


// Packet parsing and recognition
// ---------------------------------------------
assign data_1f[63:48] =  edp_rng_in_ff[63:48];
assign data_1f[7:0]   =  edp_rng_in_ff[7:0];
assign ctl_1f = edp_rng_in_ff[64];

// decode the packet, packet must be:
// - a valid, control packet for reading/writing
// - a PR operation
// - for the current thread group
// - to one of the targeted PRs

assign pr_relevent = ctl_1f & data_1f[`BUS_VLD] & (~data_1f[`BUS_ACK]) &
                     (data_1f[`BUS_REGID_END:`BUS_REGID_ST] == `PR) & 
                     (data_1f[`BUS_TID_END] == dec_thread_group);

assign asr_relevent = ctl_1f & data_1f[`BUS_VLD] & (~data_1f[`BUS_ACK]) &
                     (data_1f[`BUS_REGID_END:`BUS_REGID_ST] == `ASR)& 
                     (data_1f[`BUS_TID_END] == dec_thread_group);

assign asi_relevent = ctl_1f & data_1f[`BUS_VLD] & (~data_1f[`BUS_ACK]) &
                     (data_1f[`BUS_REGID_END:`BUS_REGID_ST] == `ASI) & 
                     (data_1f[`BUS_TID_END] == dec_thread_group) &
                     (data_1f[54] & (data_1f[51] | data_1f[49]) );

assign detected_empty_pkt = ctl_1f & ~data_1f[`BUS_VLD];


// Computing controls in the current cycle
// ---------------------------------------------
// - then flop controls to the next cycle to control the next packet
// - the signals become *_ctl once they are flopped and appear in
//   in the data cycle
assign pr_tid[1:0] = data_1f[(`BUS_TID_END-1):`BUS_TID_ST];

assign match_cwp        = pr_relevent  & (data_1f[52:48]==5'b01001);
assign match_cansave    = pr_relevent  & (data_1f[52:48]==5'b01010);
assign match_canrestore = pr_relevent  & (data_1f[52:48]==5'b01011);
assign match_cleanwin   = pr_relevent  & (data_1f[52:48]==5'b01100);
assign match_otherwin   = pr_relevent  & (data_1f[52:48]==5'b01101);
assign match_wstate     = pr_relevent  & (data_1f[52:48]==5'b01110);

assign match_yreg       = asr_relevent & (data_1f[52:48]==5'b00000);
assign match_ccr        = asr_relevent & (data_1f[52:48]==5'b00010);

// ASI == 42;  VA == 08
// use assertion to check that when data_1f[3], VA == 0x08

assign match_imask	= asi_relevent & (data_1f[55:48] == 8'h42) & data_1f[3];
assign match_irf_ecc	= asi_relevent & (data_1f[55:48] == 8'h48);

assign pr_rd = ( data_1f[`BUS_RD]) &
                (match_cwp        |        
	     	 match_cansave    |   
		 match_canrestore |
		 match_cleanwin   |  
		 match_otherwin   |  
		 match_wstate     );  

assign send_ack[0] = match_cwp        |        
	     	     match_cansave    |   
		     match_canrestore |
		     match_cleanwin   |  
		     match_otherwin   |  
		     match_wstate     |  
                     match_yreg       |        
		     match_ccr        |
		     match_imask      |
		     match_irf_ecc;

assign pr_rd_src[0] = ( data_1f[`BUS_RD]) & match_cwp;        
assign pr_rd_src[1] = ( data_1f[`BUS_RD]) & match_cansave;    
assign pr_rd_src[2] = ( data_1f[`BUS_RD]) & match_canrestore; 
assign pr_rd_src[3] = ( data_1f[`BUS_RD]) & match_cleanwin;   
assign pr_rd_src[4] = ( data_1f[`BUS_RD]) & match_otherwin;   
assign pr_rd_src[5] = ( data_1f[`BUS_RD]) & match_wstate;     
				  					    
assign pr_wt_src[0] = (~data_1f[`BUS_RD]) & match_cwp;        
assign pr_wt_src[1] = (~data_1f[`BUS_RD]) & match_cansave;    
assign pr_wt_src[2] = (~data_1f[`BUS_RD]) & match_canrestore; 
assign pr_wt_src[3] = (~data_1f[`BUS_RD]) & match_cleanwin;   
assign pr_wt_src[4] = (~data_1f[`BUS_RD]) & match_otherwin;   
assign pr_wt_src[5] = (~data_1f[`BUS_RD]) & match_wstate;    


assign detected_wrpr_cwp = pr_wt_src[0];

// IRF ECC is a read-only indeterminate write
assign detected_rd_irf_ecc  = ( data_1f[`BUS_RD]) & match_irf_ecc;


// Set rd_irf_ecc controls
assign rd_irf_ecc_valid = detected_rd_irf_ecc;
assign rd_irf_ecc_addr[4:0] = data_1f[7:3];

// Output control to Pick 
// ---------------------------------------------
//  MUX-IN BIST FOR IRF TEST PORT HERE
assign exu_test_valid		=                      rd_irf_ecc_valid_lth  |                     mbi_irf_read_en_p1;
assign exu_test_tid[1:0]	= ({2{~mbi_run_lth}} & pr_tid_ctl[1:0]     ) | ({2{mbi_run_lth}} & mbi_addr_lth[6:5]);
assign exu_test_addr[4:0]	= ({5{~mbi_run_lth}} & pr_addr_ctl[4:0]    ) | ({5{mbi_run_lth}} & mbi_addr_lth[4:0]);

exu_rml_ctl_msff_ctl_macro__width_4	pipe_rd_irf_ecc_valid_pp2p2d2e	 (
 .scan_in(pipe_rd_irf_ecc_valid_pp2p2d2e_scanin),
 .scan_out(pipe_rd_irf_ecc_valid_pp2p2d2e_scanout),
 .l1clk	(l1clk_pm1),
 .din   ({rd_irf_ecc_valid     , exu_test_valid , test_valid_p     , rml_test_valid_d}),
 .dout  ({rd_irf_ecc_valid_lth , test_valid_p   , rml_test_valid_d , ack_irf_ecc_done}),
  .siclk(siclk),
  .soclk(soclk));


// Save thread ID for WRPR CWP
// ---------------------------------------------
// save control value in the first ASI stub cycle
 
assign wrpr_cwp_tid_next[1:0] = ({2{ detected_wrpr_cwp}} & pr_tid           [1:0]) |
                                ({2{~detected_wrpr_cwp}} & wrpr_cwp_tid_hold[1:0]) ;

exu_rml_ctl_msff_ctl_macro__width_2	save_wrpr_cwp_tid	 (
 .scan_in(save_wrpr_cwp_tid_scanin),
 .scan_out(save_wrpr_cwp_tid_scanout),
 .l1clk	(l1clk_pm1),
 .din   ({wrpr_cwp_tid_next[1:0]}),
 .dout  ({wrpr_cwp_tid_hold[1:0]}),
  .siclk(siclk),
  .soclk(soclk));


// Save thread ID for RD_IRF_ECC
// ---------------------------------------------
// save control value in the first ASI stub cycle
 
assign rd_irf_tid_next[1:0] = ({2{ detected_rd_irf_ecc}} & pr_tid         [1:0]) |
                              ({2{~detected_rd_irf_ecc}} & rd_irf_tid_hold[1:0]) ;

exu_rml_ctl_msff_ctl_macro__width_2	save_rd_irf_tid		 (
 .scan_in(save_rd_irf_tid_scanin),
 .scan_out(save_rd_irf_tid_scanout),
 .l1clk	(l1clk_pm1),
 .din   ({rd_irf_tid_next[1:0]}),
 .dout  ({rd_irf_tid_hold[1:0]}),
  .siclk(siclk),
  .soclk(soclk));


// Save new CWP when there is a write to CWP PR
// ---------------------------------------------
// save new CWP data in second ASI stub cycle

assign pr_new_cwp_wt[2:0] = ({3{ pr_wt_cwp_ctl}} & data_1f[2:0]) |
                            ({3{~pr_wt_cwp_ctl}} & pr_new_cwp_wt_hold[2:0]);

exu_rml_ctl_msff_ctl_macro__width_3	save_wrpr_cwp		 (
 .scan_in(save_wrpr_cwp_scanin),
 .scan_out(save_wrpr_cwp_scanout),
 .l1clk	(l1clk_pm1),
 .din	({pr_new_cwp_wt[2:0]}),
 .dout	({pr_new_cwp_wt_hold[2:0]     }),
  .siclk(siclk),
  .soclk(soclk));


// WRPR_done indicator to be sent out on the next empty packet
// ---------------------------------------------
assign send_ack_wrpr_cwp = (ack_wrpr_cwp_done  & detected_empty_pkt) |
                     (done_wrpr_cwp_hold & detected_empty_pkt) ;

assign done_wrpr_cwp = (~send_ack_wrpr_cwp) &     
                       ( ack_wrpr_cwp_done | done_wrpr_cwp_hold);

exu_rml_ctl_msff_ctl_macro__width_1	save_done_wrpr_cwp	 (
 .scan_in(save_done_wrpr_cwp_scanin),
 .scan_out(save_done_wrpr_cwp_scanout),
 .l1clk	(l1clk_pm1),
 .din   ({done_wrpr_cwp}),
 .dout  ({done_wrpr_cwp_hold}),
  .siclk(siclk),
  .soclk(soclk));

assign send_ack[1] = send_ack_wrpr_cwp;


// IRF_ECC done indicator to be sent out on the next empty packet 
// ---------------------------------------------
// - WRPR has higher priorty
// - need to hold back sending irf_ecc ack

assign send_ack_irf_ecc = ~send_ack_wrpr_cwp &
                          ((ack_irf_ecc_done  & detected_empty_pkt) |
                           (done_irf_ecc_hold & detected_empty_pkt));

assign done_irf_ecc = (~send_ack_irf_ecc) &     
                       ( ack_irf_ecc_done | done_irf_ecc_hold);

exu_rml_ctl_msff_ctl_macro__width_1	save_done_irf_ecc	 (
 .scan_in(save_done_irf_ecc_scanin),
 .scan_out(save_done_irf_ecc_scanout),
 .l1clk	(l1clk_pm1),
 .din   ({done_irf_ecc}),
 .dout  ({done_irf_ecc_hold}),
  .siclk(siclk),
  .soclk(soclk));

assign irf_ecc_data[7:0] = ({8{ ack_irf_ecc_done}} & edp_rs3_ecc_e[7:0]    ) |
                           ({8{~ack_irf_ecc_done}} & irf_ecc_data_hold[7:0]) ;

exu_rml_ctl_msff_ctl_macro__width_8	save_irf_ecc_data	 (
 .scan_in(save_irf_ecc_data_scanin),
 .scan_out(save_irf_ecc_data_scanout),
 .l1clk	(l1clk_pm1),
 .din   ({irf_ecc_data[7:0]}),
 .dout  ({irf_ecc_data_hold[7:0]}),
  .siclk(siclk),
  .soclk(soclk));

exu_rml_ctl_msff_ctl_macro__width_1	pipe_ack_irf_ecc	 (
 .scan_in(pipe_ack_irf_ecc_scanin),
 .scan_out(pipe_ack_irf_ecc_scanout),
 .l1clk	(l1clk_pm1),
 .din   ({send_ack_irf_ecc}),
 .dout  ({send_ack_irf_ecc_piped}),
  .siclk(siclk),
  .soclk(soclk));


assign rml_irf_ecc_data[7:0] = irf_ecc_data[7:0];

assign rml_rng_ack_sel_ctl = send_ack[0] | send_ack_irf_ecc | send_ack_wrpr_cwp;


// EDP control signals for passing down DATA/CTL packets
// ---------------------------------------------
assign asr_rd_src[0] = ( data_1f[`BUS_RD]) & match_yreg;        
assign asr_rd_src[1] = ( data_1f[`BUS_RD]) & match_ccr; 
assign asr_rd_src[2] = ( data_1f[`BUS_RD]) & match_imask;   

assign asr_wt_src[0] = (~data_1f[`BUS_RD]) & match_yreg;        
assign asr_wt_src[1] = (~data_1f[`BUS_RD]) & match_ccr;    
assign asr_wt_src[2] = (~data_1f[`BUS_RD]) & match_imask;  

// Flop controls for the next data packet
exu_rml_ctl_msff_ctl_macro__width_26	asr_ctl			 (
	.scan_in(asr_ctl_scanin),
	.scan_out(asr_ctl_scanout),
	.l1clk	(l1clk_pm1),

	.din	({pr_tid[1:0], 
		  rd_irf_ecc_addr[4:0],
                  pr_rd, 
                  pr_rd_src[5:0],
                  asr_rd_src[2:0],
                  pr_wt_src[5:0],
                  asr_wt_src[2:0]}),

	.dout	({pr_tid_ctl[1:0],
		  pr_addr_ctl[4:0],
                  pr_rd_ctl,
                  pr_rd_src_ctl[5:0],
		  asi_rd_imask_ctl,
                  asr_rd_ccr_ctl,
                  asr_rd_yreg_ctl,
                  pr_wt_wstate_ctl,
                  pr_wt_otherwin_ctl,
                  pr_wt_cleanwin_ctl,
                  pr_wt_canrestore_ctl,
                  pr_wt_cansave_ctl,
                  pr_wt_cwp_ctl,
		  asi_wt_imask_ctl,
                  asr_wt_ccr_ctl,
	  	  asr_wt_yreg_ctl	 }),
  .siclk(siclk),
  .soclk(soclk));


// ASR datapath
// ------------------------


assign rml_rng_data_out[2:0] = ({3{pr_rd_src_ctl[0]}} & cwp_pr_rd[2:0]       ) |
                               ({3{pr_rd_src_ctl[1]}} & cansave_pr_rd[2:0]   ) |
                               ({3{pr_rd_src_ctl[2]}} & canrestore_pr_rd[2:0]) |
                               ({3{pr_rd_src_ctl[3]}} & cleanwin_pr_rd[2:0]  ) |
                               ({3{pr_rd_src_ctl[4]}} & otherwin_pr_rd[2:0]  ) |
                               ({3{pr_rd_src_ctl[5]}} & wstate_pr_rd[2:0]    );

assign rml_rng_data_out[5:3] = ({3{pr_rd_src_ctl[5]}} & wstate_pr_rd[5:3]);

assign rml_rng_wt_imask_ctl	= asi_wt_imask_ctl;
assign rml_rng_wt_ccr_ctl	= asr_wt_ccr_ctl;
assign rml_rng_rd_ctl[4:0]	= {send_ack_irf_ecc_piped, asi_rd_imask_ctl,asr_rd_yreg_ctl, asr_rd_ccr_ctl, pr_rd_ctl};

assign rml_rng_ack_ctl[1:0] = send_ack[1:0];
assign rml_rng_ack_cwp_tid[1:0] = wrpr_cwp_tid_hold[1:0];
assign rml_rng_ack_ecc_tid[1:0] = rd_irf_tid_hold[1:0];

assign rml_rng_ack_det_vld  = ~detected_wrpr_cwp &  ~detected_rd_irf_ecc;


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! Start : Y Register   !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


exu_rml_ctl_l1clkhdr_ctl_macro clkgen_pm2	(
 .l2clk( l2clk					),
 .l1en ( asr_wt_yreg_ctl | ect_yreg_wr_w	),
 .l1clk( l1clk_pm2				),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

assign yreg_rng_we[0]		= asr_wt_yreg_ctl & (pr_tid_ctl[1:0] == 2'b00);
assign yreg_rng_we[1]		= asr_wt_yreg_ctl & (pr_tid_ctl[1:0] == 2'b01);
assign yreg_rng_we[2]		= asr_wt_yreg_ctl & (pr_tid_ctl[1:0] == 2'b10);
assign yreg_rng_we[3]		= asr_wt_yreg_ctl & (pr_tid_ctl[1:0] == 2'b11);

assign yreg_w_we[0]		= ect_yreg_wr_w   & (ect_tid_lth_w[1:0]   == 2'b00);
assign yreg_w_we[1]		= ect_yreg_wr_w   & (ect_tid_lth_w[1:0]   == 2'b01);
assign yreg_w_we[2]		= ect_yreg_wr_w   & (ect_tid_lth_w[1:0]   == 2'b10);
assign yreg_w_we[3]		= ect_yreg_wr_w   & (ect_tid_lth_w[1:0]   == 2'b11);


assign arch_yreg_tid0_in[31:0]	= ({32{ yreg_rng_we[0]                }} & edp_rng_in_ff[31:0]    ) |
				  ({32{                   yreg_w_we[0]}} & edp_rd_ff_w[63:32]     ) |
				  ({32{~yreg_rng_we[0] & ~yreg_w_we[0]}} & arch_yreg_tid0_ff[31:0]);

assign arch_yreg_tid1_in[31:0]	= ({32{ yreg_rng_we[1]                }} & edp_rng_in_ff[31:0]    ) |
				  ({32{                   yreg_w_we[1]}} & edp_rd_ff_w[63:32]     ) |
				  ({32{~yreg_rng_we[1] & ~yreg_w_we[1]}} & arch_yreg_tid1_ff[31:0]);

assign arch_yreg_tid2_in[31:0]	= ({32{ yreg_rng_we[2]                }} & edp_rng_in_ff[31:0]    ) |
				  ({32{                   yreg_w_we[2]}} & edp_rd_ff_w[63:32]     ) |
				  ({32{~yreg_rng_we[2] & ~yreg_w_we[2]}} & arch_yreg_tid2_ff[31:0]);

assign arch_yreg_tid3_in[31:0]	= ({32{ yreg_rng_we[3]                }} & edp_rng_in_ff[31:0]    ) |
				  ({32{                   yreg_w_we[3]}} & edp_rd_ff_w[63:32]     ) |
				  ({32{~yreg_rng_we[3] & ~yreg_w_we[3]}} & arch_yreg_tid3_ff[31:0]);


exu_rml_ctl_msff_ctl_macro__width_32	i_yreg0_ff	 (		
 .scan_in(i_yreg0_ff_wmr_scanin),
 .scan_out(i_yreg0_ff_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk_pm2			),
 .din  ( arch_yreg_tid0_in[31:0]	),
 .dout ( arch_yreg_tid0_ff[31:0]	),
  .soclk(soclk));

exu_rml_ctl_msff_ctl_macro__width_32	i_yreg1_ff	 (		
 .scan_in(i_yreg1_ff_wmr_scanin),
 .scan_out(i_yreg1_ff_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk_pm2			),
 .din  ( arch_yreg_tid1_in[31:0]	),
 .dout ( arch_yreg_tid1_ff[31:0]	),
  .soclk(soclk));

exu_rml_ctl_msff_ctl_macro__width_32	i_yreg2_ff	 (		
 .scan_in(i_yreg2_ff_wmr_scanin),
 .scan_out(i_yreg2_ff_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk_pm2			),
 .din  ( arch_yreg_tid2_in[31:0]	),
 .dout ( arch_yreg_tid2_ff[31:0]	),
  .soclk(soclk));

exu_rml_ctl_msff_ctl_macro__width_32	i_yreg3_ff	 (		
 .scan_in(i_yreg3_ff_wmr_scanin),
 .scan_out(i_yreg3_ff_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk_pm2			),
 .din  ( arch_yreg_tid3_in[31:0]	),
 .dout ( arch_yreg_tid3_ff[31:0]	),
  .soclk(soclk));


assign exu_y_data_e[31:0]	= ({32{tid4_e[0]}} & arch_yreg_tid0_ff[31:0]) |
				  ({32{tid4_e[1]}} & arch_yreg_tid1_ff[31:0]) |
				  ({32{tid4_e[2]}} & arch_yreg_tid2_ff[31:0]) |
				  ({32{tid4_e[3]}} & arch_yreg_tid3_ff[31:0]);

assign rml_rng_y_data[31:0]	= ({32{pr_tid_ctl[1:0] == 2'b00}} & arch_yreg_tid0_ff[31:0]) |
				  ({32{pr_tid_ctl[1:0] == 2'b01}} & arch_yreg_tid1_ff[31:0]) |
				  ({32{pr_tid_ctl[1:0] == 2'b10}} & arch_yreg_tid2_ff[31:0]) |
				  ({32{pr_tid_ctl[1:0] == 2'b11}} & arch_yreg_tid3_ff[31:0]);


//!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*! End   : Y Register   !*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!*!


exu_rml_ctl_spare_ctl_macro__num_6 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk));


supply0 vss;
supply1 vdd;

// fixscan start:
assign mbist_scanin              = scan_in                  ;
assign cwp_trap_scanin           = mbist_scanout            ;
assign decoded_inst_d2e_scanin   = cwp_trap_scanout         ;
assign decoded_inst_e2m_scanin   = decoded_inst_d2e_scanout ;
assign decoded_inst_m2b_scanin   = decoded_inst_e2m_scanout ;
assign decoded_inst_b2w_scanin   = decoded_inst_m2b_scanout ;
assign tid_p2d2e2m2b2w_scanin    = decoded_inst_b2w_scanout ;
assign inst_vld_e2m2b2w_scanin   = tid_p2d2e2m2b2w_scanout  ;
assign exception_detected_m2b_scanin = inst_vld_e2m2b2w_scanout ;
assign flush_exu_b2w_scanin      = exception_detected_m2b_scanout;
assign exception_report_m2b_scanin = flush_exu_b2w_scanout    ;
assign wrcwp_in_playf_scanin     = exception_report_m2b_scanout;
assign pr_wt_ff_scanin           = wrcwp_in_playf_scanout   ;
assign trap_ccr_cwp_ff_scanin    = pr_wt_ff_scanout         ;
assign winblock_slot_tid_m2d2e2m_scanin = trap_ccr_cwp_ff_scanout  ;
assign i_rml_restore_en_ff_scanin = winblock_slot_tid_m2d2e2m_scanout;
assign cwp_m2b_scanin            = i_rml_restore_en_ff_scanout;
assign cwp_b2w_scanin            = cwp_m2b_scanout          ;
assign cwp_speculative_scanin    = cwp_b2w_scanout          ;
assign cansave_e2m2b2w_scanin    = cwp_speculative_scanout  ;
assign canrestore_e2m2b2w_scanin = cansave_e2m2b2w_scanout  ;
assign otherwin_e2m2b2w_scanin   = canrestore_e2m2b2w_scanout;
assign cleanwin_e2m2b2w_scanin   = otherwin_e2m2b2w_scanout ;
assign cwp_e2m2b2w_scanin        = cleanwin_e2m2b2w_scanout ;
assign pipe_rd_irf_ecc_valid_pp2p2d2e_scanin = cwp_e2m2b2w_scanout      ;
assign save_wrpr_cwp_tid_scanin  = pipe_rd_irf_ecc_valid_pp2p2d2e_scanout;
assign save_rd_irf_tid_scanin    = save_wrpr_cwp_tid_scanout;
assign save_wrpr_cwp_scanin      = save_rd_irf_tid_scanout  ;
assign save_done_wrpr_cwp_scanin = save_wrpr_cwp_scanout    ;
assign save_done_irf_ecc_scanin  = save_done_wrpr_cwp_scanout;
assign save_irf_ecc_data_scanin  = save_done_irf_ecc_scanout;
assign pipe_ack_irf_ecc_scanin   = save_irf_ecc_data_scanout;
assign asr_ctl_scanin            = pipe_ack_irf_ecc_scanout ;
assign spares_scanin             = asr_ctl_scanout          ;
assign scan_out                  = spares_scanout           ;

assign old_gl_ptr_wmr_scanin     = wmr_scan_in              ;
assign cansave_pr_wmr_scanin     = old_gl_ptr_wmr_scanout   ;
assign canrestore_pr_wmr_scanin  = cansave_pr_wmr_scanout   ;
assign otherwin_pr_wmr_scanin    = canrestore_pr_wmr_scanout;
assign cleanwin_pr_wmr_scanin    = otherwin_pr_wmr_scanout  ;
assign wstate_pr_wmr_scanin      = cleanwin_pr_wmr_scanout  ;
assign cwp_pr_wmr_scanin         = wstate_pr_wmr_scanout    ;
assign i_yreg0_ff_wmr_scanin     = cwp_pr_wmr_scanout       ;
assign i_yreg1_ff_wmr_scanin     = i_yreg0_ff_wmr_scanout   ;
assign i_yreg2_ff_wmr_scanin     = i_yreg1_ff_wmr_scanout   ;
assign i_yreg3_ff_wmr_scanin     = i_yreg2_ff_wmr_scanout   ;
assign wmr_scan_out              = i_yreg3_ff_wmr_scanout   ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_15 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [14:0] fdin;
wire [13:0] so;

  input [14:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [14:0] dout;
  output scan_out;
assign fdin[14:0] = din[14:0];


dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[14:0]),
.si({scan_in,so[13:0]}),
.so({so[13:0],scan_out}),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_26 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [25:0] fdin;
wire [24:0] so;

  input [25:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [25:0] dout;
  output scan_out;
assign fdin[25:0] = din[25:0];


dff #(26)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[25:0]),
.si({scan_in,so[24:0]}),
.so({so[24:0],scan_out}),
.q(dout[25:0])
);


endmodule


// any PARAMS parms go into naming of macro

module exu_rml_ctl_msff_ctl_macro__width_32 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [30:0] so;

  input [31:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = din[31:0];


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module exu_rml_ctl_spare_ctl_macro__num_6 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));
assign scan_out = so_5;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu (
  dec_frf_r1_addr_d, 
  dec_frf_r2_addr_d, 
  dec_frf_r1_vld_d, 
  dec_frf_r2_vld_d, 
  dec_frf_r1_32b_d, 
  dec_frf_r2_32b_d, 
  dec_frf_r1_odd32b_d, 
  dec_frf_r2_odd32b_d, 
  dec_frf_w_vld_d, 
  dec_frf_w_addr_d, 
  dec_frf_w_32b_d, 
  dec_frf_w_odd32b_d, 
  dec_spu_grant_d, 
  dec_exu_src_vld_d, 
  dec_irf_w_addr_d, 
  dec_frf_store_d, 
  dec_fsr_store_d, 
  dec_valid_e, 
  dec_fgu_op3_d, 
  dec_fgu_opf_d, 
  dec_fgu_fmov_vld_m, 
  dec_fgu_decode_d, 
  dec_fgu_valid_e, 
  dec_fgu_tid_d, 
  dec_flush_f1, 
  dec_flush_f2, 
  fgu_cmp_fcc_fx3, 
  fgu_cmp_fcc_vld_fx3, 
  fgu_cmp_fcc_tid_fx2, 
  fgu_fld_fcc_fx3, 
  fgu_fld_fcc_vld_fx3, 
  fgu_fprs_fef, 
  fgu_fdiv_stall, 
  fgu_idiv_stall, 
  fgu_divide_completion, 
  tlu_flush_fgu_b, 
  tlu_ceter_pscce, 
  tlu_cerer_frf, 
  spc_core_running_status, 
  fgu_predict_fx2, 
  fgu_pdist_beat2_fx1, 
  fgu_cecc_fx2, 
  fgu_uecc_fx2, 
  fgu_ecc_addr_fx2, 
  fgu_ecc_check_fx2, 
  fgu_fpx_ieee_trap_fw, 
  fgu_fpd_ieee_trap_fw, 
  fgu_fpx_unfin_fw, 
  fgu_fpd_unfin_fw, 
  fgu_fpd_idiv0_trap_fw, 
  fgu_fpx_trap_tid_fw, 
  fgu_fpd_trap_tid_fw, 
  lsu_fgu_fld_data_b, 
  lsu_fgu_fld_addr_b, 
  lsu_fgu_fld_vld_w, 
  lsu_fgu_fld_b, 
  lsu_fgu_fld_tid_b, 
  lsu_fgu_fld_32b_b, 
  lsu_fgu_fld_odd32b_b, 
  lsu_fgu_fsr_load_b, 
  lsu_fgu_exception_w, 
  lsu_block_store_m, 
  lsu_asi_error_inject, 
  lsu_fgu_pmen, 
  lsu_asi_clken, 
  fgu_lsu_fst_data_fx1, 
  fgu_fst_ecc_error_fx2, 
  exu_fgu_rs1_e, 
  exu_fgu_rs2_e, 
  exu_fgu_gsr_m, 
  exu_fgu_gsr_vld_m, 
  exu_fgu_flush_m, 
  fgu_exu_icc_fx5, 
  fgu_exu_xcc_fx5, 
  fgu_exu_cc_vld_fx5, 
  fgu_exu_w_vld_fx5, 
  fgu_result_tid_fx5, 
  fgu_irf_w_addr_fx5, 
  fgu_exu_result_fx5, 
  spu_fgu_fpy_ctl_d, 
  spu_fgu_rs1_e, 
  spu_fgu_rs2_e, 
  fgu_accum_b0_fx5, 
  fgu_mul_result_fx5, 
  l2clk, 
  scan_in, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lb_scan_en_wmr, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_muxtest, 
  tcu_dectest, 
  tcu_scan_en, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  mbi_frf_read_en, 
  mbi_frf_write_en, 
  mbi_addr, 
  mbi_wdata, 
  mbi_run, 
  in_rngl_cdbus, 
  fgu_mbi_frf_fail, 
  fgu_rngl_cdbus, 
  scan_out, 
  wmr_scan_out);
wire fpf_scanin;
wire fpf_scanout;
wire [4:0] fad_fsr_tem_fx1;
wire fpy_scanin;
wire fpy_scanout;
wire fpe_scanin;
wire fpe_scanout;
wire fpc_wmr_scanin;
wire fpc_wmr_scanout;
wire fpc_scanin;
wire fpc_scanout;
wire [63:0] fad_rs1_fmt_fx1;
wire [63:0] fad_rs2_fmt_fx1;
wire fdc_finish_int_early_rep0;
wire fdc_finish_fltd_early_rep0;
wire fdc_finish_flts_early_rep0;
wire fpf_bze0_fx1;
wire fpf_boe0_fx1;
wire fpf_bzf0_fx1;
wire fpf_aze0_fx1;
wire fpf_aoe0_fx1;
wire fpf_azf0_fx1;
wire main_clken0;
wire fic_scanin;
wire fic_scanout;
wire fgd_wmr_scanin;
wire fgd_wmr_scanout;
wire fgd_scanin;
wire fgd_scanout;
wire fdd_scanin;
wire fdd_scanout;
wire fdc_scanin;
wire fdc_scanout;
wire fpf_hi_bof_fx1_rep0;
wire fpf_lo_bof_fx1_rep0;
wire fpe_rs2_fmt_fx1_b0_rep0;
wire div_clken_rep0;
wire fac_div_valid_fx1_rep0;
wire fac_divq_valid_fx1_rep0;
wire [4:0] fac_div_control_fx1_rep0;
wire fad_wmr_scanin;
wire fad_wmr_scanout;
wire fad_scanin;
wire fad_scanout;
wire fac_wmr_scanin;
wire fac_wmr_scanout;
wire fac_scanin;
wire fac_scanout;
wire fec_scanin;
wire fec_scanout;
wire frf_scanin;
wire frf_scanout;
wire [4:0] fac_w1_addr_fb;
wire [2:0] fac_w1_tid_fb;
wire [1:0] fpc_w1_vld_fb;
wire [4:0] fad_w2_addr_fw;
wire [2:0] fad_w2_tid_fw;
wire [1:0] fad_w2_vld_fw;
wire [63:0] fpf_w1_result_fb;
wire [13:0] fpf_w1_synd_fb;
wire [63:0] fad_w2_result_fw;
wire [13:0] fec_w2_synd_fw;
wire [2:0] fac_tid_d;
wire fac_frf_r1_vld_d;
wire [4:0] fac_frf_r1_addr_d;
wire [63:0] frf_r1_data_e;
wire [13:0] frf_r1_ecc_e;
wire [63:0] frf_r2_data_e;
wire [13:0] frf_r2_ecc_e;
wire [63:0] fad_rs1_fmt_fx1_rep0;
wire [63:0] fad_rs1_fmt_fx1_rep01;
wire [63:0] fad_rs2_fmt_fx1_rep0;
wire [63:0] fad_rs2_fmt_fx1_rep01;
wire [63:0] fad_rs2_fmt_fx1_rep1;
wire [63:0] fdd_result;
wire [62:11] fdd_result_rep0;
wire fpf_hi_bof_fx1;
wire fpf_lo_bof_fx1;
wire [10:0] fpe_rs2_fmt_fx1;
wire mul_clken;
wire div_clken;
wire mul_clken_rep0;
wire mul_clken_rep01;
wire fac_div_valid_fx1;
wire fac_divq_valid_fx1;
wire [4:0] fac_div_control_fx1;
wire fdc_finish_int_early;
wire fdc_finish_fltd_early;
wire fdc_finish_flts_early;
wire [63:0] fad_rs1_fx1;
wire [63:0] fad_rs2_fx1;
wire fad_r1_odd32b_fx1;
wire [63:0] fgd_result_fx5;
wire [5:1] fpc_int_res_sel_fx4;
wire [3:0] fpc_vis_cmp_result_fx5;
wire [5:0] fpc_result_sel_fx5;
wire [1:0] fpc_ovf_if_rcout_fx5;
wire [4:0] fpc_ma_fmt_sel_fx4;
wire [3:0] fpc_int_sel_fx5;
wire [4:0] fpc_fconst_sel_fx5;
wire fpc_fp_cin00_fx2;
wire fpc_cin00_fx2;
wire fpc_cin16_48_fx2;
wire fpc_cin32_fx2;
wire fpc_prop16_48_fx2;
wire fpc_prop32_fx2;
wire fpc_mle_sel_fx2;
wire [2:0] fpc_mse_sel_fx2;
wire fpc_sign_fx5;
wire fpc_sign_fb;
wire fpc_sp_dest_fx4;
wire fpc_fadd_eac_enable_fx2;
wire [3:2] fpc_i2f_sel_fx1;
wire fpc_rinc_sel_fx5;
wire fpc_qthenan_fx4;
wire fpc_den2nor_sp_fb;
wire fpc_den2nor_dp_fb;
wire [3:0] fpf_b_gteq_a_fx2;
wire [3:0] fpf_b_eq_a_fx2;
wire fpf_hi_aof_fx1;
wire fpf_lo_aof_fx1;
wire [63:0] fpf_ma_sum_fx4;
wire fpf_ma_cout_fx4;
wire fpf_cmp_swap_blta_fx2;
wire fpf_align_sticky_fx4_l;
wire [1:0] fpf_byte_unsure_x_sp_fx3;
wire [1:0] fpf_byte_unsure_x_dp_fx3;
wire [5:0] fic_norm_eadj_fx5;
wire [5:0] fic_i2f_align_sel_fx2;
wire [63:0] fpf_rs2_cmp_din_fx1;
wire [38:32] fpf_man_se_byte_fx3_b38_32;
wire [6:0] fpf_man_se_byte_fx3_b6_0;
wire fac_tlu_flush_fx3;
wire fac_fpx_sp_dest_fx1;
wire fac_fpx_sp_src_fx1;
wire [3:0] fac_pre_fcc_vld_fx2;
wire fac_fcmpe_fx1;
wire [4:0] fac_rs2_rotate_sel_e;
wire [1:0] fac_i2f_sel_e;
wire fac_force_swap_blta_fx1;
wire fac_force_noswap_blta_fx1;
wire main_clken;
wire fpy_fp_result_fx4_b63;
wire fpf_sa_xor_sb_fx1;
wire [10:0] fpe_exp_res_fb;
wire [10:0] fpe_align_sel_fx2;
wire fpf_rcout_fx5;
wire fpf_rcout_fb;
wire fpf_implied_bit_fx5;
wire [6:0] fec_w1_ecc_inject_fb;
wire fac_xr_mode_fx1;
wire [4:0] fac_rs1_sel_fx1;
wire [3:0] fac_rs2_sel_fx1;
wire [1:0] fac_8x16_rnd_fx3;
wire [3:0] fac_scff_sel_fx3;
wire [6:0] fac_accum_sel_fx3;
wire [5:0] fac_result_sel_fx4;
wire fac_ma_result_en_fx4;
wire fpy_sticky_dp_fx5;
wire fpy_sticky_sp_fx5;
wire [1:0] fpy_xicc_z_fx5;
wire [9:0] fac_aexp_fmt_sel_e;
wire [7:0] fac_bexp_fmt_sel_e;
wire fac_aux_cin_fx1;
wire fpc_exp_sel_mul_fx5;
wire [3:0] fpc_eintx_sel_fx2;
wire [2:0] fpc_eadjx_sel_fx2;
wire fpc_q_rinc_sel_fx5;
wire fpe_aux_rs2_fmt_fx1_b0;
wire [11:0] fpe_aux_eint_fx1;
wire [10:0] fpe_rs1_fmt_fx1;
wire fpe_einty_adj_cout_fx5;
wire fpe_einty_eq_eadj_fx5;
wire [5:0] fic_i2f_eadj_fx2;
wire fpc_fpd_ieee_trap_fb;
wire fpc_fpx_unfin_fb;
wire fpc_fpd_unfin_fb;
wire [1:0] fad_fsr_rd_fx1;
wire fad_fsr_ns_fx1;
wire [2:0] fad_gsr_imirnd_fx1;
wire fpc_w1_ul_vld_fb;
wire [1:0] fpc_fsr_w1_vld_fx5;
wire [11:0] fpc_fsr_w1_result_fw;
wire [11:0] fpc_fsr_w2_result_fw;
wire [10:0] fpc_fpd_exp_res;
wire fpc_fpd_sign_res;
wire [1:0] fpc_fpd_const_sel;
wire [1:0] fpc_fcc_fw;
wire [1:0] fpc_rd_mode_fx3;
wire fpc_emin_fx3;
wire [2:0] fac_tid_e;
wire fac_dec_valid_fx1;
wire [2:0] fac_fpx_itype_fx1;
wire [2:0] fac_fpx_dtype_fx1;
wire [1:0] fac_fpx_stype_fx1;
wire fac_fpx_sign_instr_fx1;
wire fac_fpx_rnd_trunc_fx1;
wire fac_fpx_mulscc_fx1;
wire fac_fpx_saverestore_fx1;
wire fac_fgx_pdist_fx1;
wire fac_fgx_popc_fx2;
wire fac_fgx_mvcond_fx2;
wire fac_fgx_mvucond_fx2;
wire fac_fgx_abs_fx2;
wire fac_fgx_neg_fx2;
wire fac_fpx_nv_vld_fx1;
wire fac_fpx_of_vld_fx1;
wire fac_fpx_uf_vld_fx1;
wire fac_fpx_dz_vld_fx1;
wire fac_fpx_nx_vld_fx1;
wire fac_fpx_unfin_vld_fx1;
wire fac_fgx_instr_fx4;
wire [1:0] fac_w1_vld_fx1;
wire fac_w1_odd32b_fx1;
wire [4:1] fac_opf_fx2;
wire fac_fgx_siam_fx2;
wire fac_fsr_store_fx2;
wire [2:0] fac_gsr_asr_tid_fx2;
wire fac_rng_wr_gsr_3f;
wire [1:0] fac_gsr_w_vld_fx2;
wire fac_dec_valid_noflush_fx5;
wire fac_exu_src_e;
wire coreon_clken;
wire [3:0] fpc_fcc_vld_fx5;
wire fpc_stfsr_en_fx3to5;
wire fic_mulscc_iccz_fx4;
wire fic_mulscc_xccz_fx4;
wire fic_convert_sticky_fx4;
wire fic_fxtod_sticky_fx4;
wire fic_ftoi_nx_fx4;
wire fic_ftox_nx_fx4;
wire fic_bzf31msb_fx2;
wire fic_bzf32lsb_fx2;
wire fic_bof22msb_fx2;
wire fpc_lzd_override_fx4;
wire fpc_sp_source_fx3;
wire fdc_flt_inexact;
wire [1:0] fdc_xicc_z_early;
wire fdc_icc_v_early;
wire fdc_dec_exp_early;
wire fpc_pre_div_flush_fx2;
wire fpc_div_default_res_fx2;
wire fdd_pte_cla_early_b63;
wire fec_cecc_fx2;
wire fec_uecc_fx2;
wire fpc_frf_store_vld_fx1;
wire [1:0] fpc_gsr0_mask_sel_fx3;
wire [1:0] fpc_gsr1_mask_sel_fx3;
wire [1:0] fpc_gsr2_mask_sel_fx3;
wire [1:0] fpc_gsr3_mask_sel_fx3;
wire [1:0] fpc_gsr4_mask_sel_fx3;
wire [1:0] fpc_gsr5_mask_sel_fx3;
wire [1:0] fpc_gsr6_mask_sel_fx3;
wire [1:0] fpc_gsr7_mask_sel_fx3;
wire [4:0] fpc_gsr_scale_fx4;
wire [2:0] fpc_gsr_align_fx4;
wire [10:0] fpc_gsr_asr_11bits_fx4;
wire [62:0] fgd_rngl_cdbus_3f;
wire vis_clken;
wire fac_fgx_logical_fx2;
wire fac_fgx_expand_fx2;
wire fac_fgx_merge_fx2;
wire fac_fgx_align_fx2;
wire fac_fgx_shuffle_fx2;
wire fac_fgx_pack16_fx2;
wire fac_fgx_pack32_fx2;
wire fac_fgx_packfix_fx2;
wire fac_fgx_pack_sel_fx2;
wire [2:0] fac_tid_fx2;
wire [2:0] fac_rng_fprs;
wire fac_rng_rd_fprs_4f;
wire fac_rng_rd_gsr_4f;
wire [13:0] fec_r1_ecc_fx1;
wire fac_rng_rd_ecc_4f;
wire fac_rng_rd_or_wr_3f;
wire asi_clken;
wire fgd_gsr_asr_mask_fx4_b31;
wire fdc_asign_lth;
wire fdc_bsign_lth;
wire fdc_bsign_lth_;
wire fdc_pe_cycle3;
wire fdc_pe_cmux_sel;
wire [2:0] fdc_pe_smux_sel;
wire [5:0] fdc_pe_xsht_ctl;
wire fdc_ie_fsqrt_valid_even;
wire fdc_ie_fsqrt_valid_even_;
wire fdc_ie_fsqrt_valid_odd;
wire fdc_ie_fsqrt_valid_odd_;
wire [4:0] fdc_ie_rmux_sel;
wire [2:0] fdc_ie_dmux_sel;
wire fdc_flt_increment;
wire [1:0] fdc_pte_clasel;
wire fdc_pte_csa_cin;
wire fdc_pte_cycle2;
wire fdc_emin_lth;
wire [2:0] fdc_pte_qsel;
wire fdc_pte_stall_;
wire [1:0] fdc_flt_round;
wire [4:0] fdc_idiv_ctl;
wire fdc_fdx_cin_in;
wire [2:0] fdc_qsel00;
wire [2:0] fdc_qsel1;
wire [1:0] fdc_q_in;
wire [1:0] fdc_qm1_in;
wire [63:0] fdd_pe_clth;
wire fdd_cla_zero32_;
wire fdd_cla_zero64_;
wire fdd_fdx_din0;
wire fdd_fdx_din1;
wire fdd_fdx_cin64;
wire [4:0] fdd_fdq00_10_sum;
wire [4:0] fdd_fdq00_10_carry;
wire [3:0] fdd_fdq1p_sum;
wire [3:0] fdd_fdq1p_carry;
wire [3:0] fdd_fdq1n_sum;
wire [3:0] fdd_fdq1n_carry;
wire fac_div_flush_fx3;
wire [4:0] fac_frf_r1_addr_e;
wire [4:0] fac_aman_fmt_sel_e;
wire [4:0] fac_bman_fmt_sel_e;
wire [3:0] fac_fst_fmt_sel_fx1;
wire [4:0] fac_fpd_addr_fb;
wire fac_w1_32b_fb;
wire fac_fpd_32b_fb;
wire fac_w1_odd32b_fb;
wire fac_fpd_odd32b_fb;
wire [2:0] fac_fpd_tid_fb;
wire [5:0] fac_fsr0_sel_fw;
wire [5:0] fac_fsr1_sel_fw;
wire [5:0] fac_fsr2_sel_fw;
wire [5:0] fac_fsr3_sel_fw;
wire [5:0] fac_fsr4_sel_fw;
wire [5:0] fac_fsr5_sel_fw;
wire [5:0] fac_fsr6_sel_fw;
wire [5:0] fac_fsr7_sel_fw;
wire fad_w2_addr_fw1_b4;
wire [2:0] fad_w2_tid_fw1;
wire [1:0] fad_w2_vld_fw1;
wire [2:0] fad_w1_tid_fw;
wire [1:0] fad_w1_vld_fw;
wire [63:0] fad_nombi_w2_result_fw;
wire fad_r1_byp_hit_fx1;
wire fad_r2_byp_hit_fx1;
wire fad_i_parity_2e_fx1;
wire fad_i_parity_2o_fx1;
wire fad_i_parity_1e_fx1;
wire fad_i_parity_1o_fx1;
wire [7:0] fac_mbist_addr_1f;
wire [7:0] fec_mbist_wdata_1f;
wire [7:0] fec_mbist_wdata_3f;
wire fad_mbist_cmp64_fx1;
wire [1:0] fac_r1_vld_fx1;
wire [1:0] fac_r2_vld_fx1;
wire fac_ecc_trap_en_fx1;


// ----------------------------------------------------------------------------
// Interface with DEC
// ----------------------------------------------------------------------------

input    [4:0] dec_frf_r1_addr_d;      // FRF r1 read addr
input    [4:0] dec_frf_r2_addr_d;      // FRF r2 read addr (incl. STF,STDF)
input          dec_frf_r1_vld_d;       // FRF r1 read valid
input          dec_frf_r2_vld_d;       // FRF r2 read valid (incl. STF,STDF)
input          dec_frf_r1_32b_d;       // FRF r1 is 32-bit source
input          dec_frf_r2_32b_d;       // FRF r2 is 32-bit source
input          dec_frf_r1_odd32b_d;    // 0in custom -fire (dec_frf_r1_odd32b_d & ~dec_frf_r1_32b_d)
				       // FRF r1 is odd 32-bit source (32 LSBs)
input          dec_frf_r2_odd32b_d;    // 0in custom -fire (dec_frf_r2_odd32b_d & ~dec_frf_r2_32b_d)
				       // FRF r2 is odd 32-bit source (32 LSBs) (incl. STF,STDF)

input          dec_frf_w_vld_d;        // FRF target
input    [4:0] dec_frf_w_addr_d;       // FRF write addr
input          dec_frf_w_32b_d;        // FRF write is 32-bit dest
input          dec_frf_w_odd32b_d;     // 0in custom -fire (dec_frf_w_odd32b_d & ~dec_frf_w_32b_d)
				       // FRF write is odd 32-bit dest (32 LSBs)

input          dec_spu_grant_d;        // 0in custom -fire (($0in_delay(dec_spu_grant_d,1)) & dec_fgu_valid_e)
				       // SPU sources are valid next cycle (frf/e)
input          dec_exu_src_vld_d;      // FGU instr issued has EXU{1,0} source(s)
input    [4:0] dec_irf_w_addr_d;       // IRF write addr for EXU{1,0}

input          dec_frf_store_d;        // FGU instr issued is a store of FRF data
input          dec_fsr_store_d;        // FGU instr issued is a store of FSR data
input    [1:0] dec_valid_e;            // used by FGU to qual store FSR update of FSR.ftt

input    [5:0] dec_fgu_op3_d;          // 6-bit op3 field = instr[24:19]
input    [7:0] dec_fgu_opf_d;          // 9-bit opf field = instr[13:5] = fpop type (bit 13 is unused)
input          dec_fgu_fmov_vld_m;     // FMOV condition is true
input          dec_fgu_decode_d;       // 0in known_driven; assert_leader -leader dec_fgu_decode_d -follower dec_fgu_valid_e -min 1 -max 1
				       // FGU instr issue valid (d stage), also asserts for ST(X)FSR
input          dec_fgu_valid_e;        // 0in known_driven
				       // FGU instr issue valid (e stage), doesn't assert for ST(X)FSR
input    [2:0] dec_fgu_tid_d;          // FGU instr TID

input          dec_flush_f1;           // flush fx2 (xmit in fx1/m)
input          dec_flush_f2;           // flush fx3 (xmit in fx2/b)

output   [1:0] fgu_cmp_fcc_fx3;        // fcmp  fcc data {fccX[1:0]}
output   [3:0] fgu_cmp_fcc_vld_fx3;    // 0in bits_on -max 1
				       // fcmp  fcc data valid {fcc3, fcc2, fcc1, fcc0}
output   [2:0] fgu_cmp_fcc_tid_fx2;    // fcmp  fcc data TID
output   [7:0] fgu_fld_fcc_fx3;        // ldfsr fcc data {fcc3[1:0], fcc2[1:0], fcc1[1:0], fcc0[1:0]}
output   [1:0] fgu_fld_fcc_vld_fx3;    // 0in value -val 2'b00 2'b01 2'b11
				       // ldfsr fcc data valid {fcc3, fcc2, fcc1}, fcc0
output   [7:0] fgu_fprs_fef;           // FPRS.fef for each TID

output         fgu_fdiv_stall;         // FPD needs bubble to avoid FRF w2 port conflict
output   [1:0] fgu_idiv_stall;         // 0in bits_on -max 1
				       // FPD needs bubble to avoid FGU/IRF result bus conflict
output   [7:0] fgu_divide_completion;  // 0in bits_on -max 2
				       // FPD completion/TID

// ----------------------------------------------------------------------------
// Interface with TLU
// ----------------------------------------------------------------------------

input          tlu_flush_fgu_b;        // flush fx3, non-load (xmit in fx2/b)
input    [7:0] tlu_ceter_pscce;        // core error trap enable reg precise enable
input          tlu_cerer_frf;          // FRF ecc error trap enable
input    [7:0] spc_core_running_status; // thread active

output         fgu_predict_fx2;        // exception trap predicted
output         fgu_pdist_beat2_fx1;    // 2nd beat (bubble) of PDIST instr
output         fgu_cecc_fx2;           // FRF ECC correctable error
output         fgu_uecc_fx2;           // FRF ECC uncorrectable error
output   [5:0] fgu_ecc_addr_fx2;       // FRF cecc/uecc address (6-bit reg number format)
output  [13:0] fgu_ecc_check_fx2;      // FRF ECC check bits {even[6:0],odd[6:0]}

output         fgu_fpx_ieee_trap_fw;   // FPX enabled ieee 754 exception detected
output         fgu_fpd_ieee_trap_fw;   // FPD enabled ieee 754 exception detected
output         fgu_fpx_unfin_fw;       // unfinished_FPop
output         fgu_fpd_unfin_fw;       // unfinished_FPop
output         fgu_fpd_idiv0_trap_fw;  // integer division by zero detected
output   [2:0] fgu_fpx_trap_tid_fw;    // FPX trap TID
output   [2:0] fgu_fpd_trap_tid_fw;    // FPD trap TID

// ----------------------------------------------------------------------------
// Interface with LSU
// ----------------------------------------------------------------------------

input   [63:0] lsu_fgu_fld_data_b;     // FRF/FSR load data
input    [4:0] lsu_fgu_fld_addr_b;     // FRF     w2 write addr (fload hit/miss)
input          lsu_fgu_fld_vld_w;      // 0in custom -fire (lsu_fgu_fld_vld_w & ($0in_delay((~lsu_fgu_fld_b),1)))
				       // FRF/FSR load data valid (fload hit/miss), LSU qualified with dec_flush_lb, tlu_flush_fld_b, lsu_ldhit_b
input          lsu_fgu_fld_b;          // FRF/FSR load data (unqualified)
input    [2:0] lsu_fgu_fld_tid_b;      // FRF/FSR load data TID (fload hit/miss)
input          lsu_fgu_fld_32b_b;      // FRF/FSR is 32-bit dest (fload hit/miss)
input          lsu_fgu_fld_odd32b_b;   // 0in custom -fire (lsu_fgu_fld_odd32b_b & ~lsu_fgu_fld_32b_b)
				       // FRF     w2 is odd 32-bit dest (32 LSBs) (fload hit/miss)
input          lsu_fgu_fsr_load_b;     //     FSR is target of the load (not FRF) (unqualified)
input          lsu_fgu_exception_w;    // store exception detected
input          lsu_block_store_m;      // block store in progress

input   [31:0] lsu_asi_error_inject;   // [31]=global inject en, [24]=FRF inject en, [7:0]=mask
input          lsu_fgu_pmen;           // FGU global power management enable
input          lsu_asi_clken;          // ASI ring clk enable

output  [63:0] fgu_lsu_fst_data_fx1;   // FRF/FSR store data
output         fgu_fst_ecc_error_fx2;  // store float FRF ECC correctable/uncorrectable error

// ----------------------------------------------------------------------------
// Interface with EXUs
// ----------------------------------------------------------------------------

input   [63:0] exu_fgu_rs1_e;          // rs1 source from EXU{1,0}
                                       //   MULScc format: {30'b0,Y[0],1'b0,icc.nXORicc.v,rs1[31:1]}
input   [63:0] exu_fgu_rs2_e;          // rs2 source from EXU{1,0}

input   [31:0] exu_fgu_gsr_m;          // GSR.align data:
                                       //   [31:3] = don't care
                                       //   [2:0]  = GSR.align
                                       //   GSR.mask data:
                                       //   [31:0] = GSR.mask
input    [1:0] exu_fgu_gsr_vld_m;      // 0in bits_on -max 1
				       // GSR data valid {align,mask}
input          exu_fgu_flush_m;        // EXU{1,0} src has bad ECC or exception, FGU must flush instr

output   [3:0] fgu_exu_icc_fx5;        // int icc cond code {N,Z,V,C}
output   [1:0] fgu_exu_xcc_fx5;        // int xcc cond code {N,Z}
output         fgu_exu_cc_vld_fx5;     // int icc/xcc cond code valid
output   [1:0] fgu_exu_w_vld_fx5;      // 0in bits_on -max 1
				       // FGU data result valid for EXU{1,0} w port
output   [1:0] fgu_result_tid_fx5;     // FGU result TID for EXU{1,0} or SPU
output   [4:0] fgu_irf_w_addr_fx5;     // IRF w1 write addr
output  [63:0] fgu_exu_result_fx5;     // FGU result for EXU{1,0}

// ----------------------------------------------------------------------------
// Interface with SPU
// ----------------------------------------------------------------------------

input    [6:0] spu_fgu_fpy_ctl_d;      // Mult control
input   [63:0] spu_fgu_rs1_e;          // rs1 source from SPU
input   [63:0] spu_fgu_rs2_e;          // rs2 source from SPU

output         fgu_accum_b0_fx5;
output  [63:0] fgu_mul_result_fx5;     // FGU result for SPU

// ----------------------------------------------------------------------------
// Global Signals
// ----------------------------------------------------------------------------

input          l2clk;                  // clock input
input	       scan_in;
input          spc_aclk_wmr;
input          wmr_scan_in;
input          lb_scan_en_wmr;
input	       tcu_pce_ov;	       // scan signals
input	       spc_aclk;
input	       spc_bclk;
input          tcu_muxtest;
input 	       tcu_dectest;
input 	       tcu_scan_en;
input          tcu_array_wr_inhibit;
input          tcu_se_scancollar_in;
input          tcu_se_scancollar_out;
input          mbi_frf_read_en;        // MBIST
input          mbi_frf_write_en;       // MBIST
input    [7:0] mbi_addr;               // MBIST
input    [7:0] mbi_wdata;              // MBIST
input          mbi_run;                // MBIST
input   [64:0] in_rngl_cdbus;          // ASI local ring

output         fgu_mbi_frf_fail;       // MBIST
output  [64:0] fgu_rngl_cdbus;         // ASI local ring
output 	       scan_out;
output         wmr_scan_out;

// ----------------------------------------------------------------------------
// Instantiate sub-units
// ----------------------------------------------------------------------------

fgu_rep_dp    rep (.fad_rs1_fmt_fx1(fad_rs1_fmt_fx1[63:0]),
  .fad_rs2_fmt_fx1(fad_rs2_fmt_fx1[63:0]),
  .fad_rs1_fmt_fx1_rep0(fad_rs1_fmt_fx1_rep0[63:0]),
  .fad_rs1_fmt_fx1_rep01(fad_rs1_fmt_fx1_rep01[63:0]),
  .fad_rs2_fmt_fx1_rep0(fad_rs2_fmt_fx1_rep0[63:0]),
  .fad_rs2_fmt_fx1_rep01(fad_rs2_fmt_fx1_rep01[63:0]),
  .fad_rs2_fmt_fx1_rep1(fad_rs2_fmt_fx1_rep1[63:0]),
  .fdd_result(fdd_result[62:11]),
  .fdd_result_rep0(fdd_result_rep0[62:11]),
  .fpf_hi_bof_fx1(fpf_hi_bof_fx1),
  .fpf_lo_bof_fx1(fpf_lo_bof_fx1),
  .fpf_hi_bof_fx1_rep0(fpf_hi_bof_fx1_rep0),
  .fpf_lo_bof_fx1_rep0(fpf_lo_bof_fx1_rep0),
  .fpe_rs2_fmt_fx1(fpe_rs2_fmt_fx1[0:0]),
  .fpe_rs2_fmt_fx1_b0_rep0(fpe_rs2_fmt_fx1_b0_rep0),
  .mul_clken(mul_clken),
  .div_clken(div_clken),
  .mul_clken_rep0(mul_clken_rep0),
  .mul_clken_rep01(mul_clken_rep01),
  .div_clken_rep0(div_clken_rep0),
  .fac_div_valid_fx1(fac_div_valid_fx1),
  .fac_divq_valid_fx1(fac_divq_valid_fx1),
  .fac_div_control_fx1(fac_div_control_fx1[4:0]),
  .fac_div_valid_fx1_rep0(fac_div_valid_fx1_rep0),
  .fac_divq_valid_fx1_rep0(fac_divq_valid_fx1_rep0),
  .fac_div_control_fx1_rep0(fac_div_control_fx1_rep0[4:0]),
  .fdc_finish_int_early(fdc_finish_int_early),
  .fdc_finish_fltd_early(fdc_finish_fltd_early),
  .fdc_finish_flts_early(fdc_finish_flts_early),
  .fdc_finish_int_early_rep0(fdc_finish_int_early_rep0),
  .fdc_finish_fltd_early_rep0(fdc_finish_fltd_early_rep0),
  .fdc_finish_flts_early_rep0(fdc_finish_flts_early_rep0)
 );

fgu_fpf_dp    fpf (
 .scan_in(fpf_scanin),
 .scan_out(fpf_scanout),
 .l2clk(l2clk),
 .fad_fsr_tem_fx1_b4     (fad_fsr_tem_fx1[4]),
  .fad_rs1_fmt_fx1(fad_rs1_fmt_fx1[63:0]),
  .fad_rs2_fmt_fx1(fad_rs2_fmt_fx1[63:0]),
  .fad_rs1_fx1(fad_rs1_fx1[63:0]),
  .fad_rs2_fx1(fad_rs2_fx1[63:0]),
  .fad_r1_odd32b_fx1(fad_r1_odd32b_fx1),
  .fpf_w1_result_fb(fpf_w1_result_fb[63:0]),
  .fgu_exu_result_fx5(fgu_exu_result_fx5[63:0]),
  .fgd_result_fx5(fgd_result_fx5[63:0]),
  .fpc_int_res_sel_fx4(fpc_int_res_sel_fx4[5:1]),
  .fpc_vis_cmp_result_fx5(fpc_vis_cmp_result_fx5[3:0]),
  .fpc_result_sel_fx5(fpc_result_sel_fx5[5:0]),
  .fpc_ovf_if_rcout_fx5(fpc_ovf_if_rcout_fx5[1:0]),
  .fpc_ma_fmt_sel_fx4(fpc_ma_fmt_sel_fx4[4:0]),
  .fpc_int_sel_fx5(fpc_int_sel_fx5[3:0]),
  .fpc_fconst_sel_fx5(fpc_fconst_sel_fx5[4:0]),
  .fpc_fp_cin00_fx2(fpc_fp_cin00_fx2),
  .fpc_cin00_fx2(fpc_cin00_fx2),
  .fpc_cin16_48_fx2(fpc_cin16_48_fx2),
  .fpc_cin32_fx2(fpc_cin32_fx2),
  .fpc_prop16_48_fx2(fpc_prop16_48_fx2),
  .fpc_prop32_fx2(fpc_prop32_fx2),
  .fpc_mle_sel_fx2(fpc_mle_sel_fx2),
  .fpc_mse_sel_fx2(fpc_mse_sel_fx2[2:0]),
  .fpc_sign_fx5(fpc_sign_fx5),
  .fpc_sign_fb(fpc_sign_fb),
  .fpc_sp_dest_fx4(fpc_sp_dest_fx4),
  .fpc_fadd_eac_enable_fx2(fpc_fadd_eac_enable_fx2),
  .fpc_i2f_sel_fx1(fpc_i2f_sel_fx1[3:2]),
  .fpc_rinc_sel_fx5(fpc_rinc_sel_fx5),
  .fpc_qthenan_fx4(fpc_qthenan_fx4),
  .fpc_den2nor_sp_fb(fpc_den2nor_sp_fb),
  .fpc_den2nor_dp_fb(fpc_den2nor_dp_fb),
  .fpf_b_gteq_a_fx2(fpf_b_gteq_a_fx2[3:0]),
  .fpf_b_eq_a_fx2(fpf_b_eq_a_fx2[3:0]),
  .fpf_hi_aof_fx1(fpf_hi_aof_fx1),
  .fpf_hi_bof_fx1(fpf_hi_bof_fx1),
  .fpf_lo_aof_fx1(fpf_lo_aof_fx1),
  .fpf_lo_bof_fx1(fpf_lo_bof_fx1),
  .fpf_azf0_fx1(fpf_azf0_fx1),
  .fpf_bzf0_fx1(fpf_bzf0_fx1),
  .fpf_aoe0_fx1(fpf_aoe0_fx1),
  .fpf_boe0_fx1(fpf_boe0_fx1),
  .fpf_aze0_fx1(fpf_aze0_fx1),
  .fpf_bze0_fx1(fpf_bze0_fx1),
  .fpf_ma_sum_fx4(fpf_ma_sum_fx4[63:0]),
  .fpf_ma_cout_fx4(fpf_ma_cout_fx4),
  .fpf_cmp_swap_blta_fx2(fpf_cmp_swap_blta_fx2),
  .fpf_align_sticky_fx4_l(fpf_align_sticky_fx4_l),
  .fpf_byte_unsure_x_sp_fx3(fpf_byte_unsure_x_sp_fx3[1:0]),
  .fpf_byte_unsure_x_dp_fx3(fpf_byte_unsure_x_dp_fx3[1:0]),
  .fic_norm_eadj_fx5(fic_norm_eadj_fx5[5:0]),
  .fic_i2f_align_sel_fx2(fic_i2f_align_sel_fx2[5:0]),
  .fpf_rs2_cmp_din_fx1(fpf_rs2_cmp_din_fx1[63:0]),
  .fpf_man_se_byte_fx3_b38_32(fpf_man_se_byte_fx3_b38_32[38:32]),
  .fpf_man_se_byte_fx3_b6_0(fpf_man_se_byte_fx3_b6_0[6:0]),
  .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]),
  .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0]),
  .fac_tlu_flush_fx3(fac_tlu_flush_fx3),
  .fac_fpx_sp_dest_fx1(fac_fpx_sp_dest_fx1),
  .fac_fpx_sp_src_fx1(fac_fpx_sp_src_fx1),
  .fac_pre_fcc_vld_fx2(fac_pre_fcc_vld_fx2[3:0]),
  .fac_fcmpe_fx1(fac_fcmpe_fx1),
  .fac_rs2_rotate_sel_e(fac_rs2_rotate_sel_e[4:0]),
  .fac_i2f_sel_e(fac_i2f_sel_e[1:0]),
  .fac_force_swap_blta_fx1(fac_force_swap_blta_fx1),
  .fac_force_noswap_blta_fx1(fac_force_noswap_blta_fx1),
  .main_clken(main_clken),
  .fgu_mul_result_fx5(fgu_mul_result_fx5[63:0]),
  .fpy_fp_result_fx4_b63(fpy_fp_result_fx4_b63),
  .fdc_finish_int_early(fdc_finish_int_early),
  .fdd_result(fdd_result[63:0]),
  .fpf_sa_xor_sb_fx1(fpf_sa_xor_sb_fx1),
  .fpe_exp_res_fb(fpe_exp_res_fb[10:0]),
  .fpe_align_sel_fx2(fpe_align_sel_fx2[5:0]),
  .fpf_rcout_fx5(fpf_rcout_fx5),
  .fpf_rcout_fb(fpf_rcout_fb),
  .fpf_implied_bit_fx5(fpf_implied_bit_fx5),
  .fec_w1_ecc_inject_fb(fec_w1_ecc_inject_fb[6:0]),
  .fpf_w1_synd_fb(fpf_w1_synd_fb[13:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en(tcu_scan_en)
 );

fgu_fpy_dp    fpy (
 .scan_in(fpy_scanin),
 .scan_out(fpy_scanout),
 .l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .mul_clken_rep0(mul_clken_rep0),
  .mul_clken_rep01(mul_clken_rep01),
  .spu_fgu_rs1_e(spu_fgu_rs1_e[63:0]),
  .spu_fgu_rs2_e(spu_fgu_rs2_e[63:0]),
  .fad_rs1_fmt_fx1_rep0(fad_rs1_fmt_fx1_rep0[63:0]),
  .fad_rs2_fmt_fx1_rep0(fad_rs2_fmt_fx1_rep0[63:0]),
  .fad_rs2_fmt_fx1_rep1(fad_rs2_fmt_fx1_rep1[63:0]),
  .fac_xr_mode_fx1(fac_xr_mode_fx1),
  .fac_rs1_sel_fx1(fac_rs1_sel_fx1[4:0]),
  .fac_rs2_sel_fx1(fac_rs2_sel_fx1[3:0]),
  .fac_8x16_rnd_fx3(fac_8x16_rnd_fx3[1:0]),
  .fac_scff_sel_fx3(fac_scff_sel_fx3[3:0]),
  .fac_accum_sel_fx3(fac_accum_sel_fx3[6:0]),
  .fac_result_sel_fx4(fac_result_sel_fx4[5:0]),
  .fac_ma_result_en_fx4(fac_ma_result_en_fx4),
  .fgu_mul_result_fx5(fgu_mul_result_fx5[63:0]),
  .fpy_sticky_dp_fx5(fpy_sticky_dp_fx5),
  .fpy_sticky_sp_fx5(fpy_sticky_sp_fx5),
  .fpy_fp_result_fx4_b63(fpy_fp_result_fx4_b63),
  .fpy_xicc_z_fx5(fpy_xicc_z_fx5[1:0]),
  .fgu_accum_b0_fx5(fgu_accum_b0_fx5)
 );

fgu_fpe_dp    fpe (
 .scan_in(fpe_scanin),
 .scan_out(fpe_scanout),
 .l2clk(l2clk),
 .fgu_mul_result_fx5_b63(fgu_mul_result_fx5[63]),
  .fad_rs1_fx1(fad_rs1_fx1[62:23]),
  .fad_rs2_fx1(fad_rs2_fx1[62:23]),
  .fac_aexp_fmt_sel_e(fac_aexp_fmt_sel_e[9:0]),
  .fac_bexp_fmt_sel_e(fac_bexp_fmt_sel_e[7:0]),
  .fac_aux_cin_fx1(fac_aux_cin_fx1),
  .main_clken(main_clken),
  .fpc_exp_sel_mul_fx5(fpc_exp_sel_mul_fx5),
  .fpc_eintx_sel_fx2(fpc_eintx_sel_fx2[3:0]),
  .fpc_eadjx_sel_fx2(fpc_eadjx_sel_fx2[2:0]),
  .fpc_ma_fmt_sel_fx4(fpc_ma_fmt_sel_fx4[1:0]),
  .fpc_rinc_sel_fx5(fpc_rinc_sel_fx5),
  .fpc_q_rinc_sel_fx5(fpc_q_rinc_sel_fx5),
  .fpe_aux_rs2_fmt_fx1_b0(fpe_aux_rs2_fmt_fx1_b0),
  .fpe_aux_eint_fx1(fpe_aux_eint_fx1[11:0]),
  .fpe_rs1_fmt_fx1(fpe_rs1_fmt_fx1[10:0]),
  .fpe_rs2_fmt_fx1(fpe_rs2_fmt_fx1[10:0]),
  .fpe_einty_adj_cout_fx5(fpe_einty_adj_cout_fx5),
  .fpe_einty_eq_eadj_fx5(fpe_einty_eq_eadj_fx5),
  .fpf_rcout_fx5(fpf_rcout_fx5),
  .fpe_exp_res_fb(fpe_exp_res_fb[10:0]),
  .fpe_align_sel_fx2(fpe_align_sel_fx2[10:0]),
  .fic_i2f_eadj_fx2(fic_i2f_eadj_fx2[5:0]),
  .fic_norm_eadj_fx5(fic_norm_eadj_fx5[5:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en(tcu_scan_en)
 );

fgu_fpc_ctl   fpc (							// FS:wmr_protect
 .wmr_scan_in(fpc_wmr_scanin),
 .wmr_scan_out(fpc_wmr_scanout),
 .scan_in(fpc_scanin),
 .scan_out(fpc_scanout),
 .l2clk(l2clk),
 .fad_rs1_fmt_fx1_b62    (fad_rs1_fmt_fx1[62]),
 .fad_rs2_fmt_fx1_b62    (fad_rs2_fmt_fx1[62]),
 .fdc_finish_int_early   (fdc_finish_int_early_rep0),    // fgu global buff rename
 .fdc_finish_fltd_early  (fdc_finish_fltd_early_rep0),   // fgu global buff rename
 .fdc_finish_flts_early  (fdc_finish_flts_early_rep0),   // fgu global buff rename
 .fpf_bze_fx1            (fpf_bze0_fx1),                 // fgu global buff rename
 .fpf_boe_fx1            (fpf_boe0_fx1),                 // fgu global buff rename
 .fpf_bzf_fx1            (fpf_bzf0_fx1),                 // fgu global buff rename
 .fpf_aze_fx1            (fpf_aze0_fx1),                 // fgu global buff rename
 .fpf_aoe_fx1            (fpf_aoe0_fx1),                 // fgu global buff rename
 .fpf_azf_fx1            (fpf_azf0_fx1),                 // fgu global buff rename
 .main_clken             (main_clken0),
  .fpc_fpd_ieee_trap_fb(fpc_fpd_ieee_trap_fb),
  .fpc_fpx_unfin_fb(fpc_fpx_unfin_fb),
  .fpc_fpd_unfin_fb(fpc_fpd_unfin_fb),
  .fgu_fpx_ieee_trap_fw(fgu_fpx_ieee_trap_fw),
  .fgu_fpd_ieee_trap_fw(fgu_fpd_ieee_trap_fw),
  .fgu_fpx_unfin_fw(fgu_fpx_unfin_fw),
  .fgu_fpd_unfin_fw(fgu_fpd_unfin_fw),
  .fgu_fpd_idiv0_trap_fw(fgu_fpd_idiv0_trap_fw),
  .fgu_predict_fx2(fgu_predict_fx2),
  .lsu_fgu_exception_w(lsu_fgu_exception_w),
  .lsu_block_store_m(lsu_block_store_m),
  .exu_fgu_flush_m(exu_fgu_flush_m),
  .exu_fgu_gsr_m(exu_fgu_gsr_m[2:0]),
  .fgu_exu_icc_fx5(fgu_exu_icc_fx5[3:0]),
  .fgu_exu_xcc_fx5(fgu_exu_xcc_fx5[1:0]),
  .fad_rs1_fx1(fad_rs1_fx1[63:15]),
  .fad_rs2_fx1(fad_rs2_fx1[63:15]),
  .fad_fsr_rd_fx1(fad_fsr_rd_fx1[1:0]),
  .fad_fsr_tem_fx1(fad_fsr_tem_fx1[4:0]),
  .fad_fsr_ns_fx1(fad_fsr_ns_fx1),
  .fad_gsr_imirnd_fx1(fad_gsr_imirnd_fx1[2:0]),
  .fpc_w1_vld_fb(fpc_w1_vld_fb[1:0]),
  .fpc_w1_ul_vld_fb(fpc_w1_ul_vld_fb),
  .fpc_fsr_w1_vld_fx5(fpc_fsr_w1_vld_fx5[1:0]),
  .fpc_fsr_w1_result_fw(fpc_fsr_w1_result_fw[11:0]),
  .fpc_fsr_w2_result_fw(fpc_fsr_w2_result_fw[11:0]),
  .fpc_fpd_exp_res(fpc_fpd_exp_res[10:0]),
  .fpc_fpd_sign_res(fpc_fpd_sign_res),
  .fpc_fpd_const_sel(fpc_fpd_const_sel[1:0]),
  .fpc_fcc_fw(fpc_fcc_fw[1:0]),
  .fpf_b_gteq_a_fx2(fpf_b_gteq_a_fx2[3:0]),
  .fpf_b_eq_a_fx2(fpf_b_eq_a_fx2[3:0]),
  .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]),
  .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0]),
  .fpf_hi_aof_fx1(fpf_hi_aof_fx1),
  .fpf_lo_aof_fx1(fpf_lo_aof_fx1),
  .fpf_ma_sum_fx4(fpf_ma_sum_fx4[63:9]),
  .fpf_ma_cout_fx4(fpf_ma_cout_fx4),
  .fpf_cmp_swap_blta_fx2(fpf_cmp_swap_blta_fx2),
  .fpf_align_sticky_fx4_l(fpf_align_sticky_fx4_l),
  .fpf_byte_unsure_x_sp_fx3(fpf_byte_unsure_x_sp_fx3[1:0]),
  .fpf_byte_unsure_x_dp_fx3(fpf_byte_unsure_x_dp_fx3[1:0]),
  .fpf_rcout_fb(fpf_rcout_fb),
  .fpf_implied_bit_fx5(fpf_implied_bit_fx5),
  .fpc_result_sel_fx5(fpc_result_sel_fx5[5:0]),
  .fpc_ovf_if_rcout_fx5(fpc_ovf_if_rcout_fx5[1:0]),
  .fpc_vis_cmp_result_fx5(fpc_vis_cmp_result_fx5[3:0]),
  .fpc_int_res_sel_fx4(fpc_int_res_sel_fx4[5:1]),
  .fpc_ma_fmt_sel_fx4(fpc_ma_fmt_sel_fx4[4:0]),
  .fpc_int_sel_fx5(fpc_int_sel_fx5[3:0]),
  .fpc_fconst_sel_fx5(fpc_fconst_sel_fx5[4:0]),
  .fpc_fp_cin00_fx2(fpc_fp_cin00_fx2),
  .fpc_cin00_fx2(fpc_cin00_fx2),
  .fpc_cin16_48_fx2(fpc_cin16_48_fx2),
  .fpc_cin32_fx2(fpc_cin32_fx2),
  .fpc_prop16_48_fx2(fpc_prop16_48_fx2),
  .fpc_prop32_fx2(fpc_prop32_fx2),
  .fpc_mle_sel_fx2(fpc_mle_sel_fx2),
  .fpc_mse_sel_fx2(fpc_mse_sel_fx2[2:0]),
  .fpc_sign_fx5(fpc_sign_fx5),
  .fpc_sign_fb(fpc_sign_fb),
  .fpc_rd_mode_fx3(fpc_rd_mode_fx3[1:0]),
  .fpc_emin_fx3(fpc_emin_fx3),
  .fpc_sp_dest_fx4(fpc_sp_dest_fx4),
  .fpc_fadd_eac_enable_fx2(fpc_fadd_eac_enable_fx2),
  .fpc_i2f_sel_fx1(fpc_i2f_sel_fx1[3:2]),
  .fpc_rinc_sel_fx5(fpc_rinc_sel_fx5),
  .fpc_qthenan_fx4(fpc_qthenan_fx4),
  .fpc_den2nor_sp_fb(fpc_den2nor_sp_fb),
  .fpc_den2nor_dp_fb(fpc_den2nor_dp_fb),
  .fpe_aux_rs2_fmt_fx1_b0(fpe_aux_rs2_fmt_fx1_b0),
  .fpe_aux_eint_fx1(fpe_aux_eint_fx1[11:0]),
  .fpe_align_sel_fx2(fpe_align_sel_fx2[10:0]),
  .fpe_rs1_fmt_fx1(fpe_rs1_fmt_fx1[10:0]),
  .fpe_rs2_fmt_fx1(fpe_rs2_fmt_fx1[10:0]),
  .fpe_einty_adj_cout_fx5(fpe_einty_adj_cout_fx5),
  .fpe_einty_eq_eadj_fx5(fpe_einty_eq_eadj_fx5),
  .fpc_exp_sel_mul_fx5(fpc_exp_sel_mul_fx5),
  .fpc_eintx_sel_fx2(fpc_eintx_sel_fx2[3:0]),
  .fpc_eadjx_sel_fx2(fpc_eadjx_sel_fx2[2:0]),
  .fpc_q_rinc_sel_fx5(fpc_q_rinc_sel_fx5),
  .fac_tlu_flush_fx3(fac_tlu_flush_fx3),
  .fac_tid_e(fac_tid_e[2:0]),
  .fac_dec_valid_fx1(fac_dec_valid_fx1),
  .fac_fpx_itype_fx1(fac_fpx_itype_fx1[2:0]),
  .fac_fpx_dtype_fx1(fac_fpx_dtype_fx1[2:0]),
  .fac_fpx_stype_fx1(fac_fpx_stype_fx1[1:0]),
  .fac_fpx_sign_instr_fx1(fac_fpx_sign_instr_fx1),
  .fac_fpx_rnd_trunc_fx1(fac_fpx_rnd_trunc_fx1),
  .fac_fcmpe_fx1(fac_fcmpe_fx1),
  .fac_fpx_mulscc_fx1(fac_fpx_mulscc_fx1),
  .fac_fpx_saverestore_fx1(fac_fpx_saverestore_fx1),
  .fac_fgx_pdist_fx1(fac_fgx_pdist_fx1),
  .fac_fgx_popc_fx2(fac_fgx_popc_fx2),
  .fac_fgx_mvcond_fx2(fac_fgx_mvcond_fx2),
  .fac_fgx_mvucond_fx2(fac_fgx_mvucond_fx2),
  .fac_fgx_abs_fx2(fac_fgx_abs_fx2),
  .fac_fgx_neg_fx2(fac_fgx_neg_fx2),
  .fac_fpx_nv_vld_fx1(fac_fpx_nv_vld_fx1),
  .fac_fpx_of_vld_fx1(fac_fpx_of_vld_fx1),
  .fac_fpx_uf_vld_fx1(fac_fpx_uf_vld_fx1),
  .fac_fpx_dz_vld_fx1(fac_fpx_dz_vld_fx1),
  .fac_fpx_nx_vld_fx1(fac_fpx_nx_vld_fx1),
  .fac_fpx_unfin_vld_fx1(fac_fpx_unfin_vld_fx1),
  .fac_fgx_instr_fx4(fac_fgx_instr_fx4),
  .fac_w1_vld_fx1(fac_w1_vld_fx1[1:0]),
  .fac_w1_odd32b_fx1(fac_w1_odd32b_fx1),
  .fac_opf_fx2(fac_opf_fx2[3:1]),
  .fac_fgx_siam_fx2(fac_fgx_siam_fx2),
  .fac_div_valid_fx1(fac_div_valid_fx1),
  .fac_divq_valid_fx1(fac_divq_valid_fx1),
  .fac_fsr_store_fx2(fac_fsr_store_fx2),
  .fac_gsr_asr_tid_fx2(fac_gsr_asr_tid_fx2[2:0]),
  .fac_rng_wr_gsr_3f(fac_rng_wr_gsr_3f),
  .fac_gsr_w_vld_fx2(fac_gsr_w_vld_fx2[1:0]),
  .fac_dec_valid_noflush_fx5(fac_dec_valid_noflush_fx5),
  .fac_exu_src_e(fac_exu_src_e),
  .coreon_clken(coreon_clken),
  .fpc_fcc_vld_fx5(fpc_fcc_vld_fx5[3:0]),
  .fpc_stfsr_en_fx3to5(fpc_stfsr_en_fx3to5),
  .fic_norm_eadj_fx5(fic_norm_eadj_fx5[5:0]),
  .fic_mulscc_iccz_fx4(fic_mulscc_iccz_fx4),
  .fic_mulscc_xccz_fx4(fic_mulscc_xccz_fx4),
  .fic_convert_sticky_fx4(fic_convert_sticky_fx4),
  .fic_fxtod_sticky_fx4(fic_fxtod_sticky_fx4),
  .fic_ftoi_nx_fx4(fic_ftoi_nx_fx4),
  .fic_ftox_nx_fx4(fic_ftox_nx_fx4),
  .fic_bzf31msb_fx2(fic_bzf31msb_fx2),
  .fic_bzf32lsb_fx2(fic_bzf32lsb_fx2),
  .fic_bof22msb_fx2(fic_bof22msb_fx2),
  .fpc_lzd_override_fx4(fpc_lzd_override_fx4),
  .fpc_sp_source_fx3(fpc_sp_source_fx3),
  .fdc_flt_inexact(fdc_flt_inexact),
  .fdc_xicc_z_early(fdc_xicc_z_early[1:0]),
  .fdc_icc_v_early(fdc_icc_v_early),
  .fdc_dec_exp_early(fdc_dec_exp_early),
  .fpc_pre_div_flush_fx2(fpc_pre_div_flush_fx2),
  .fpc_div_default_res_fx2(fpc_div_default_res_fx2),
  .fdd_result(fdd_result[63:31]),
  .fdd_pte_cla_early_b63(fdd_pte_cla_early_b63),
  .fgu_mul_result_fx5(fgu_mul_result_fx5[63:9]),
  .fpy_sticky_dp_fx5(fpy_sticky_dp_fx5),
  .fpy_sticky_sp_fx5(fpy_sticky_sp_fx5),
  .fpy_xicc_z_fx5(fpy_xicc_z_fx5[1:0]),
  .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d),
  .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d),
  .dec_flush_f1(dec_flush_f1),
  .dec_flush_f2(dec_flush_f2),
  .dec_fgu_fmov_vld_m(dec_fgu_fmov_vld_m),
  .dec_valid_e(dec_valid_e[1:0]),
  .dec_frf_store_d(dec_frf_store_d),
  .fec_cecc_fx2(fec_cecc_fx2),
  .fec_uecc_fx2(fec_uecc_fx2),
  .fpc_frf_store_vld_fx1(fpc_frf_store_vld_fx1),
  .fpc_gsr0_mask_sel_fx3(fpc_gsr0_mask_sel_fx3[1:0]),
  .fpc_gsr1_mask_sel_fx3(fpc_gsr1_mask_sel_fx3[1:0]),
  .fpc_gsr2_mask_sel_fx3(fpc_gsr2_mask_sel_fx3[1:0]),
  .fpc_gsr3_mask_sel_fx3(fpc_gsr3_mask_sel_fx3[1:0]),
  .fpc_gsr4_mask_sel_fx3(fpc_gsr4_mask_sel_fx3[1:0]),
  .fpc_gsr5_mask_sel_fx3(fpc_gsr5_mask_sel_fx3[1:0]),
  .fpc_gsr6_mask_sel_fx3(fpc_gsr6_mask_sel_fx3[1:0]),
  .fpc_gsr7_mask_sel_fx3(fpc_gsr7_mask_sel_fx3[1:0]),
  .fpc_gsr_scale_fx4(fpc_gsr_scale_fx4[4:0]),
  .fpc_gsr_align_fx4(fpc_gsr_align_fx4[2:0]),
  .fpc_gsr_asr_11bits_fx4(fpc_gsr_asr_11bits_fx4[10:0]),
  .spc_aclk_wmr(spc_aclk_wmr),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .mbi_run(mbi_run),
  .in_rngl_cdbus(in_rngl_cdbus[27:0])
 );

fgu_fic_ctl   fic (
 .scan_in(fic_scanin),
 .scan_out(fic_scanout),
 .l2clk(l2clk),
  .fpf_rs2_cmp_din_fx1(fpf_rs2_cmp_din_fx1[63:0]),
  .fpf_ma_sum_fx4(fpf_ma_sum_fx4[63:0]),
  .fpf_man_se_byte_fx3_b38_32(fpf_man_se_byte_fx3_b38_32[38:32]),
  .fpf_man_se_byte_fx3_b6_0(fpf_man_se_byte_fx3_b6_0[6:0]),
  .fic_norm_eadj_fx5(fic_norm_eadj_fx5[5:0]),
  .fic_i2f_align_sel_fx2(fic_i2f_align_sel_fx2[5:0]),
  .fpe_align_sel_fx2(fpe_align_sel_fx2[5:0]),
  .fic_i2f_eadj_fx2(fic_i2f_eadj_fx2[5:0]),
  .fpc_lzd_override_fx4(fpc_lzd_override_fx4),
  .fpc_sp_source_fx3(fpc_sp_source_fx3),
  .fic_mulscc_iccz_fx4(fic_mulscc_iccz_fx4),
  .fic_mulscc_xccz_fx4(fic_mulscc_xccz_fx4),
  .fic_convert_sticky_fx4(fic_convert_sticky_fx4),
  .fic_fxtod_sticky_fx4(fic_fxtod_sticky_fx4),
  .fic_ftoi_nx_fx4(fic_ftoi_nx_fx4),
  .fic_ftox_nx_fx4(fic_ftox_nx_fx4),
  .fic_bzf31msb_fx2(fic_bzf31msb_fx2),
  .fic_bzf32lsb_fx2(fic_bzf32lsb_fx2),
  .fic_bof22msb_fx2(fic_bof22msb_fx2),
  .main_clken(main_clken),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
 );

fgu_fgd_dp    fgd (							// FS:wmr_protect
 .wmr_scan_in(fgd_wmr_scanin),
 .wmr_scan_out(fgd_wmr_scanout),
 .scan_in(fgd_scanin),
 .scan_out(fgd_scanout),
 .l2clk(l2clk),
  .fad_rs1_fmt_fx1(fad_rs1_fmt_fx1[63:0]),
  .fad_rs2_fmt_fx1(fad_rs2_fmt_fx1[63:0]),
  .fgd_rngl_cdbus_3f(fgd_rngl_cdbus_3f[62:0]),
  .fgd_result_fx5(fgd_result_fx5[63:0]),
  .vis_clken(vis_clken),
  .coreon_clken(coreon_clken),
  .fac_fgx_abs_fx2(fac_fgx_abs_fx2),
  .fac_fgx_neg_fx2(fac_fgx_neg_fx2),
  .fac_fgx_logical_fx2(fac_fgx_logical_fx2),
  .fac_fgx_expand_fx2(fac_fgx_expand_fx2),
  .fac_fgx_merge_fx2(fac_fgx_merge_fx2),
  .fac_fgx_align_fx2(fac_fgx_align_fx2),
  .fac_fgx_shuffle_fx2(fac_fgx_shuffle_fx2),
  .fac_fgx_pack16_fx2(fac_fgx_pack16_fx2),
  .fac_fgx_pack32_fx2(fac_fgx_pack32_fx2),
  .fac_fgx_packfix_fx2(fac_fgx_packfix_fx2),
  .fac_fgx_pdist_fx1(fac_fgx_pdist_fx1),
  .fac_fgx_popc_fx2(fac_fgx_popc_fx2),
  .fac_fgx_pack_sel_fx2(fac_fgx_pack_sel_fx2),
  .fac_opf_fx2(fac_opf_fx2[4:1]),
  .fac_gsr_asr_tid_fx2(fac_gsr_asr_tid_fx2[2:0]),
  .fac_tid_fx2(fac_tid_fx2[2:0]),
  .fac_rng_fprs(fac_rng_fprs[2:0]),
  .fac_rng_rd_fprs_4f(fac_rng_rd_fprs_4f),
  .fac_rng_rd_gsr_4f(fac_rng_rd_gsr_4f),
  .fec_r1_ecc_fx1(fec_r1_ecc_fx1[13:0]),
  .fac_rng_rd_ecc_4f(fac_rng_rd_ecc_4f),
  .fac_rng_rd_or_wr_3f(fac_rng_rd_or_wr_3f),
  .asi_clken(asi_clken),
  .fgd_gsr_asr_mask_fx4_b31(fgd_gsr_asr_mask_fx4_b31),
  .fpc_gsr0_mask_sel_fx3(fpc_gsr0_mask_sel_fx3[1:0]),
  .fpc_gsr1_mask_sel_fx3(fpc_gsr1_mask_sel_fx3[1:0]),
  .fpc_gsr2_mask_sel_fx3(fpc_gsr2_mask_sel_fx3[1:0]),
  .fpc_gsr3_mask_sel_fx3(fpc_gsr3_mask_sel_fx3[1:0]),
  .fpc_gsr4_mask_sel_fx3(fpc_gsr4_mask_sel_fx3[1:0]),
  .fpc_gsr5_mask_sel_fx3(fpc_gsr5_mask_sel_fx3[1:0]),
  .fpc_gsr6_mask_sel_fx3(fpc_gsr6_mask_sel_fx3[1:0]),
  .fpc_gsr7_mask_sel_fx3(fpc_gsr7_mask_sel_fx3[1:0]),
  .fpc_gsr_scale_fx4(fpc_gsr_scale_fx4[4:0]),
  .fpc_gsr_align_fx4(fpc_gsr_align_fx4[2:0]),
  .fpc_gsr_asr_11bits_fx4(fpc_gsr_asr_11bits_fx4[10:0]),
  .exu_fgu_gsr_m(exu_fgu_gsr_m[31:0]),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lb_scan_en_wmr(lb_scan_en_wmr),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en(tcu_scan_en),
  .in_rngl_cdbus(in_rngl_cdbus[63:0])
 );

fgu_fdd_dp    fdd (
 .scan_in(fdd_scanin),
 .scan_out(fdd_scanout),
 .l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .div_clken_rep0(div_clken_rep0),
  .fad_rs1_fmt_fx1_rep01(fad_rs1_fmt_fx1_rep01[63:0]),
  .fad_rs2_fmt_fx1_rep01(fad_rs2_fmt_fx1_rep01[63:0]),
  .fac_div_valid_fx1_rep0(fac_div_valid_fx1_rep0),
  .fac_divq_valid_fx1_rep0(fac_divq_valid_fx1_rep0),
  .fdc_asign_lth(fdc_asign_lth),
  .fdc_bsign_lth(fdc_bsign_lth),
  .fdc_bsign_lth_(fdc_bsign_lth_),
  .fdc_pe_cycle3(fdc_pe_cycle3),
  .fdc_pe_cmux_sel(fdc_pe_cmux_sel),
  .fdc_pe_smux_sel(fdc_pe_smux_sel[2:0]),
  .fdc_pe_xsht_ctl(fdc_pe_xsht_ctl[5:0]),
  .fdc_ie_fsqrt_valid_even(fdc_ie_fsqrt_valid_even),
  .fdc_ie_fsqrt_valid_even_(fdc_ie_fsqrt_valid_even_),
  .fdc_ie_fsqrt_valid_odd(fdc_ie_fsqrt_valid_odd),
  .fdc_ie_fsqrt_valid_odd_(fdc_ie_fsqrt_valid_odd_),
  .fdc_ie_rmux_sel(fdc_ie_rmux_sel[4:0]),
  .fdc_ie_dmux_sel(fdc_ie_dmux_sel[2:0]),
  .fdc_flt_increment(fdc_flt_increment),
  .fdc_pte_clasel(fdc_pte_clasel[1:0]),
  .fdc_pte_csa_cin(fdc_pte_csa_cin),
  .fdc_pte_cycle2(fdc_pte_cycle2),
  .fdc_emin_lth(fdc_emin_lth),
  .fdc_pte_qsel(fdc_pte_qsel[2:0]),
  .fdc_pte_stall_(fdc_pte_stall_),
  .fdc_flt_round(fdc_flt_round[1:0]),
  .fdc_idiv_ctl(fdc_idiv_ctl[4:0]),
  .fdc_fdx_cin_in(fdc_fdx_cin_in),
  .fdc_qsel00(fdc_qsel00[2:0]),
  .fdc_qsel1(fdc_qsel1[2:0]),
  .fdc_q_in(fdc_q_in[1:0]),
  .fdc_qm1_in(fdc_qm1_in[1:0]),
  .fdd_result(fdd_result[63:0]),
  .fdd_pte_cla_early_b63(fdd_pte_cla_early_b63),
  .fdd_pe_clth(fdd_pe_clth[63:0]),
  .fdd_cla_zero32_(fdd_cla_zero32_),
  .fdd_cla_zero64_(fdd_cla_zero64_),
  .fdd_fdx_din0(fdd_fdx_din0),
  .fdd_fdx_din1(fdd_fdx_din1),
  .fdd_fdx_cin64(fdd_fdx_cin64),
  .fdd_fdq00_10_sum(fdd_fdq00_10_sum[4:0]),
  .fdd_fdq00_10_carry(fdd_fdq00_10_carry[4:0]),
  .fdd_fdq1p_sum(fdd_fdq1p_sum[3:0]),
  .fdd_fdq1p_carry(fdd_fdq1p_carry[3:0]),
  .fdd_fdq1n_sum(fdd_fdq1n_sum[3:0]),
  .fdd_fdq1n_carry(fdd_fdq1n_carry[3:0])
 );

fgu_fdc_ctl   fdc (
 .scan_in(fdc_scanin),
 .scan_out(fdc_scanout),
 .l2clk(l2clk),
 .fpf_hi_bof_fx1         (fpf_hi_bof_fx1_rep0),          // fgu global buff rename
 .fpf_lo_bof_fx1         (fpf_lo_bof_fx1_rep0),          // fgu global buff rename
 .fpe_rs2_fmt_fx1_b0     (fpe_rs2_fmt_fx1_b0_rep0),      // fgu global buff rename
 .div_clken              (div_clken_rep0),               // fgu global buff rename
 .fac_div_valid_fx1      (fac_div_valid_fx1_rep0),       // fgu global buff rename
 .fac_divq_valid_fx1     (fac_divq_valid_fx1_rep0),      // fgu global buff rename
 .fac_div_control_fx1    (fac_div_control_fx1_rep0[4:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .fac_div_flush_fx3(fac_div_flush_fx3),
  .fpf_sa_xor_sb_fx1(fpf_sa_xor_sb_fx1),
  .fpc_rd_mode_fx3(fpc_rd_mode_fx3[1:0]),
  .fpc_emin_fx3(fpc_emin_fx3),
  .fdd_pe_clth(fdd_pe_clth[63:0]),
  .fdd_cla_zero32_(fdd_cla_zero32_),
  .fdd_cla_zero64_(fdd_cla_zero64_),
  .fdd_result(fdd_result[63:9]),
  .fdd_fdx_din0(fdd_fdx_din0),
  .fdd_fdx_din1(fdd_fdx_din1),
  .fdd_fdx_cin64(fdd_fdx_cin64),
  .fdd_fdq00_10_sum(fdd_fdq00_10_sum[4:0]),
  .fdd_fdq00_10_carry(fdd_fdq00_10_carry[4:0]),
  .fdd_fdq1p_sum(fdd_fdq1p_sum[3:0]),
  .fdd_fdq1p_carry(fdd_fdq1p_carry[3:0]),
  .fdd_fdq1n_sum(fdd_fdq1n_sum[3:0]),
  .fdd_fdq1n_carry(fdd_fdq1n_carry[3:0]),
  .fgu_fdiv_stall(fgu_fdiv_stall),
  .fgu_idiv_stall(fgu_idiv_stall[1:0]),
  .fdc_dec_exp_early(fdc_dec_exp_early),
  .fdc_icc_v_early(fdc_icc_v_early),
  .fdc_xicc_z_early(fdc_xicc_z_early[1:0]),
  .fdc_finish_int_early(fdc_finish_int_early),
  .fdc_finish_fltd_early(fdc_finish_fltd_early),
  .fdc_finish_flts_early(fdc_finish_flts_early),
  .fdc_flt_inexact(fdc_flt_inexact),
  .fdc_asign_lth(fdc_asign_lth),
  .fdc_bsign_lth(fdc_bsign_lth),
  .fdc_bsign_lth_(fdc_bsign_lth_),
  .fdc_pe_cycle3(fdc_pe_cycle3),
  .fdc_pe_cmux_sel(fdc_pe_cmux_sel),
  .fdc_pe_smux_sel(fdc_pe_smux_sel[2:0]),
  .fdc_pe_xsht_ctl(fdc_pe_xsht_ctl[5:0]),
  .fdc_ie_fsqrt_valid_even(fdc_ie_fsqrt_valid_even),
  .fdc_ie_fsqrt_valid_even_(fdc_ie_fsqrt_valid_even_),
  .fdc_ie_fsqrt_valid_odd(fdc_ie_fsqrt_valid_odd),
  .fdc_ie_fsqrt_valid_odd_(fdc_ie_fsqrt_valid_odd_),
  .fdc_ie_rmux_sel(fdc_ie_rmux_sel[4:0]),
  .fdc_ie_dmux_sel(fdc_ie_dmux_sel[2:0]),
  .fdc_flt_increment(fdc_flt_increment),
  .fdc_pte_clasel(fdc_pte_clasel[1:0]),
  .fdc_pte_csa_cin(fdc_pte_csa_cin),
  .fdc_pte_cycle2(fdc_pte_cycle2),
  .fdc_emin_lth(fdc_emin_lth),
  .fdc_pte_qsel(fdc_pte_qsel[2:0]),
  .fdc_pte_stall_(fdc_pte_stall_),
  .fdc_flt_round(fdc_flt_round[1:0]),
  .fdc_idiv_ctl(fdc_idiv_ctl[4:0]),
  .fdc_fdx_cin_in(fdc_fdx_cin_in),
  .fdc_qsel00(fdc_qsel00[2:0]),
  .fdc_qsel1(fdc_qsel1[2:0]),
  .fdc_q_in(fdc_q_in[1:0]),
  .fdc_qm1_in(fdc_qm1_in[1:0]) // fgu global buff rename
 );

fgu_fad_dp    fad (							// FS:wmr_protect
 .wmr_scan_in(fad_wmr_scanin),
 .wmr_scan_out(fad_wmr_scanout),
 .scan_in(fad_scanin),
 .scan_out(fad_scanout),
 .l2clk(l2clk),
  .dec_frf_r2_addr_d(dec_frf_r2_addr_d[4:0]),
  .dec_frf_r1_32b_d(dec_frf_r1_32b_d),
  .dec_frf_r2_32b_d(dec_frf_r2_32b_d),
  .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d),
  .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d),
  .fgu_fld_fcc_fx3(fgu_fld_fcc_fx3[7:0]),
  .lsu_fgu_fld_data_b(lsu_fgu_fld_data_b[63:0]),
  .lsu_fgu_fld_addr_b(lsu_fgu_fld_addr_b[4:0]),
  .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w),
  .lsu_fgu_fld_b(lsu_fgu_fld_b),
  .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]),
  .lsu_fgu_fld_32b_b(lsu_fgu_fld_32b_b),
  .lsu_fgu_fld_odd32b_b(lsu_fgu_fld_odd32b_b),
  .lsu_fgu_fsr_load_b(lsu_fgu_fsr_load_b),
  .fgu_lsu_fst_data_fx1(fgu_lsu_fst_data_fx1[63:0]),
  .exu_fgu_rs1_e(exu_fgu_rs1_e[63:0]),
  .exu_fgu_rs2_e(exu_fgu_rs2_e[63:0]),
  .fac_frf_r1_addr_e(fac_frf_r1_addr_e[4:0]),
  .fac_tid_e(fac_tid_e[2:0]),
  .fac_aman_fmt_sel_e(fac_aman_fmt_sel_e[4:0]),
  .fac_bman_fmt_sel_e(fac_bman_fmt_sel_e[4:0]),
  .fac_fst_fmt_sel_fx1(fac_fst_fmt_sel_fx1[3:0]),
  .fac_exu_src_e(fac_exu_src_e),
  .fac_w1_addr_fb(fac_w1_addr_fb[4:0]),
  .fac_fpd_addr_fb(fac_fpd_addr_fb[4:0]),
  .fac_w1_32b_fb(fac_w1_32b_fb),
  .fac_fpd_32b_fb(fac_fpd_32b_fb),
  .fac_w1_odd32b_fb(fac_w1_odd32b_fb),
  .fac_fpd_odd32b_fb(fac_fpd_odd32b_fb),
  .fac_w1_tid_fb(fac_w1_tid_fb[2:0]),
  .fac_fpd_tid_fb(fac_fpd_tid_fb[2:0]),
  .fac_fsr0_sel_fw(fac_fsr0_sel_fw[5:0]),
  .fac_fsr1_sel_fw(fac_fsr1_sel_fw[5:0]),
  .fac_fsr2_sel_fw(fac_fsr2_sel_fw[5:0]),
  .fac_fsr3_sel_fw(fac_fsr3_sel_fw[5:0]),
  .fac_fsr4_sel_fw(fac_fsr4_sel_fw[5:0]),
  .fac_fsr5_sel_fw(fac_fsr5_sel_fw[5:0]),
  .fac_fsr6_sel_fw(fac_fsr6_sel_fw[5:0]),
  .fac_fsr7_sel_fw(fac_fsr7_sel_fw[5:0]),
  .main_clken(main_clken),
  .asi_clken(asi_clken),
  .coreon_clken(coreon_clken),
  .fad_w2_addr_fw1_b4(fad_w2_addr_fw1_b4),
  .fad_w2_tid_fw1(fad_w2_tid_fw1[2:0]),
  .fad_w2_vld_fw1(fad_w2_vld_fw1[1:0]),
  .fpc_w1_vld_fb(fpc_w1_vld_fb[1:0]),
  .fpc_w1_ul_vld_fb(fpc_w1_ul_vld_fb),
  .fpc_fsr_w1_result_fw(fpc_fsr_w1_result_fw[11:0]),
  .fpc_fsr_w2_result_fw(fpc_fsr_w2_result_fw[11:0]),
  .fpc_fpd_exp_res(fpc_fpd_exp_res[10:0]),
  .fpc_fpd_sign_res(fpc_fpd_sign_res),
  .fpc_fpd_const_sel(fpc_fpd_const_sel[1:0]),
  .fpc_fcc_fw(fpc_fcc_fw[1:0]),
  .fpc_fpd_ieee_trap_fb(fpc_fpd_ieee_trap_fb),
  .fpc_fpd_unfin_fb(fpc_fpd_unfin_fb),
  .fad_gsr_imirnd_fx1(fad_gsr_imirnd_fx1[2:0]),
  .frf_r1_data_e(frf_r1_data_e[63:0]),
  .frf_r2_data_e(frf_r2_data_e[63:0]),
  .fad_w1_tid_fw(fad_w1_tid_fw[2:0]),
  .fad_w1_vld_fw(fad_w1_vld_fw[1:0]),
  .fad_w2_result_fw(fad_w2_result_fw[63:0]),
  .fad_w2_addr_fw(fad_w2_addr_fw[4:0]),
  .fad_w2_tid_fw(fad_w2_tid_fw[2:0]),
  .fad_w2_vld_fw(fad_w2_vld_fw[1:0]),
  .fad_nombi_w2_result_fw(fad_nombi_w2_result_fw[63:0]),
  .fad_r1_byp_hit_fx1(fad_r1_byp_hit_fx1),
  .fad_r2_byp_hit_fx1(fad_r2_byp_hit_fx1),
  .fad_i_parity_2e_fx1(fad_i_parity_2e_fx1),
  .fad_i_parity_2o_fx1(fad_i_parity_2o_fx1),
  .fad_i_parity_1e_fx1(fad_i_parity_1e_fx1),
  .fad_i_parity_1o_fx1(fad_i_parity_1o_fx1),
  .fpf_w1_result_fb(fpf_w1_result_fb[63:0]),
  .fad_rs1_fmt_fx1(fad_rs1_fmt_fx1[63:0]),
  .fad_rs2_fmt_fx1(fad_rs2_fmt_fx1[63:0]),
  .fad_rs1_fx1(fad_rs1_fx1[63:0]),
  .fad_rs2_fx1(fad_rs2_fx1[63:0]),
  .fad_r1_odd32b_fx1(fad_r1_odd32b_fx1),
  .fad_fsr_rd_fx1(fad_fsr_rd_fx1[1:0]),
  .fad_fsr_tem_fx1(fad_fsr_tem_fx1[4:0]),
  .fad_fsr_ns_fx1(fad_fsr_ns_fx1),
  .fdd_result_rep0(fdd_result_rep0[62:11]),
  .fdc_finish_fltd_early_rep0(fdc_finish_fltd_early_rep0),
  .fdc_finish_flts_early_rep0(fdc_finish_flts_early_rep0),
  .fgd_rngl_cdbus_3f(fgd_rngl_cdbus_3f[62:0]),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lb_scan_en_wmr(lb_scan_en_wmr),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .mbi_run(mbi_run),
  .mbi_frf_write_en(mbi_frf_write_en),
  .fac_mbist_addr_1f(fac_mbist_addr_1f[7:0]),
  .fec_mbist_wdata_1f(fec_mbist_wdata_1f[7:0]),
  .fec_mbist_wdata_3f(fec_mbist_wdata_3f[7:0]),
  .fad_mbist_cmp64_fx1(fad_mbist_cmp64_fx1),
  .fgu_rngl_cdbus(fgu_rngl_cdbus[62:0])
 );

fgu_fac_ctl   fac (							// FS:wmr_protect
 .wmr_scan_in(fac_wmr_scanin),
 .wmr_scan_out(fac_wmr_scanout),
 .scan_in(fac_scanin),
 .scan_out(fac_scanout),
 .l2clk(l2clk),
 .fdc_finish_int_early   (fdc_finish_int_early_rep0),    // fgu global buff rename
 .fdc_finish_fltd_early  (fdc_finish_fltd_early_rep0),   // fgu global buff rename
 .fdc_finish_flts_early  (fdc_finish_flts_early_rep0),   // fgu global buff rename
 .fgu_rngl_cdbus_b64     (fgu_rngl_cdbus[64]),
 .fgu_rngl_cdbus_b63     (fgu_rngl_cdbus[63]),
  .dec_frf_r1_addr_d(dec_frf_r1_addr_d[4:0]),
  .dec_frf_r1_vld_d(dec_frf_r1_vld_d),
  .dec_frf_r2_vld_d(dec_frf_r2_vld_d),
  .dec_frf_r1_32b_d(dec_frf_r1_32b_d),
  .dec_frf_r2_32b_d(dec_frf_r2_32b_d),
  .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d),
  .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d),
  .dec_frf_w_vld_d(dec_frf_w_vld_d),
  .dec_frf_w_addr_d(dec_frf_w_addr_d[4:0]),
  .dec_frf_w_32b_d(dec_frf_w_32b_d),
  .dec_frf_w_odd32b_d(dec_frf_w_odd32b_d),
  .dec_fgu_valid_e(dec_fgu_valid_e),
  .dec_exu_src_vld_d(dec_exu_src_vld_d),
  .dec_irf_w_addr_d(dec_irf_w_addr_d[4:0]),
  .dec_spu_grant_d(dec_spu_grant_d),
  .dec_frf_store_d(dec_frf_store_d),
  .dec_fsr_store_d(dec_fsr_store_d),
  .dec_flush_f1(dec_flush_f1),
  .dec_flush_f2(dec_flush_f2),
  .dec_fgu_op3_d(dec_fgu_op3_d[5:0]),
  .dec_fgu_opf_d(dec_fgu_opf_d[7:0]),
  .dec_fgu_decode_d(dec_fgu_decode_d),
  .dec_fgu_tid_d(dec_fgu_tid_d[2:0]),
  .fgu_cmp_fcc_tid_fx2(fgu_cmp_fcc_tid_fx2[2:0]),
  .fgu_fld_fcc_vld_fx3(fgu_fld_fcc_vld_fx3[1:0]),
  .fgu_fprs_fef(fgu_fprs_fef[7:0]),
  .fgu_divide_completion(fgu_divide_completion[7:0]),
  .tlu_flush_fgu_b(tlu_flush_fgu_b),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .tlu_cerer_frf(tlu_cerer_frf),
  .spc_core_running_status(spc_core_running_status[7:0]),
  .fgu_fpx_trap_tid_fw(fgu_fpx_trap_tid_fw[2:0]),
  .fgu_fpd_trap_tid_fw(fgu_fpd_trap_tid_fw[2:0]),
  .fpc_pre_div_flush_fx2(fpc_pre_div_flush_fx2),
  .fpc_div_default_res_fx2(fpc_div_default_res_fx2),
  .fpc_fsr_w1_vld_fx5(fpc_fsr_w1_vld_fx5[1:0]),
  .fpc_fcc_vld_fx5(fpc_fcc_vld_fx5[3:0]),
  .fpc_fpx_unfin_fb(fpc_fpx_unfin_fb),
  .fpc_fpd_unfin_fb(fpc_fpd_unfin_fb),
  .fpc_stfsr_en_fx3to5(fpc_stfsr_en_fx3to5),
  .fac_tlu_flush_fx3(fac_tlu_flush_fx3),
  .fac_dec_valid_fx1(fac_dec_valid_fx1),
  .fac_fpx_itype_fx1(fac_fpx_itype_fx1[2:0]),
  .fac_fpx_dtype_fx1(fac_fpx_dtype_fx1[2:0]),
  .fac_fpx_stype_fx1(fac_fpx_stype_fx1[1:0]),
  .fac_fpx_sign_instr_fx1(fac_fpx_sign_instr_fx1),
  .fac_fpx_rnd_trunc_fx1(fac_fpx_rnd_trunc_fx1),
  .fac_fpx_mulscc_fx1(fac_fpx_mulscc_fx1),
  .fac_fpx_saverestore_fx1(fac_fpx_saverestore_fx1),
  .fac_fpx_nv_vld_fx1(fac_fpx_nv_vld_fx1),
  .fac_fpx_of_vld_fx1(fac_fpx_of_vld_fx1),
  .fac_fpx_uf_vld_fx1(fac_fpx_uf_vld_fx1),
  .fac_fpx_dz_vld_fx1(fac_fpx_dz_vld_fx1),
  .fac_fpx_nx_vld_fx1(fac_fpx_nx_vld_fx1),
  .fac_fpx_unfin_vld_fx1(fac_fpx_unfin_vld_fx1),
  .fac_fpx_sp_dest_fx1(fac_fpx_sp_dest_fx1),
  .fac_fpx_sp_src_fx1(fac_fpx_sp_src_fx1),
  .fac_fgx_instr_fx4(fac_fgx_instr_fx4),
  .fac_w1_vld_fx1(fac_w1_vld_fx1[1:0]),
  .fac_w1_odd32b_fx1(fac_w1_odd32b_fx1),
  .fac_gsr_w_vld_fx2(fac_gsr_w_vld_fx2[1:0]),
  .fac_dec_valid_noflush_fx5(fac_dec_valid_noflush_fx5),
  .fgd_gsr_asr_mask_fx4_b31(fgd_gsr_asr_mask_fx4_b31),
  .fac_fgx_mvcond_fx2(fac_fgx_mvcond_fx2),
  .fac_fgx_mvucond_fx2(fac_fgx_mvucond_fx2),
  .fac_fgx_abs_fx2(fac_fgx_abs_fx2),
  .fac_fgx_neg_fx2(fac_fgx_neg_fx2),
  .fac_fgx_logical_fx2(fac_fgx_logical_fx2),
  .fac_fgx_expand_fx2(fac_fgx_expand_fx2),
  .fac_fgx_merge_fx2(fac_fgx_merge_fx2),
  .fac_fgx_align_fx2(fac_fgx_align_fx2),
  .fac_fgx_shuffle_fx2(fac_fgx_shuffle_fx2),
  .fac_fgx_pack16_fx2(fac_fgx_pack16_fx2),
  .fac_fgx_pack32_fx2(fac_fgx_pack32_fx2),
  .fac_fgx_packfix_fx2(fac_fgx_packfix_fx2),
  .fac_fgx_pdist_fx1(fac_fgx_pdist_fx1),
  .fac_fgx_popc_fx2(fac_fgx_popc_fx2),
  .fac_fgx_siam_fx2(fac_fgx_siam_fx2),
  .fac_fgx_pack_sel_fx2(fac_fgx_pack_sel_fx2),
  .fac_opf_fx2(fac_opf_fx2[4:1]),
  .fac_gsr_asr_tid_fx2(fac_gsr_asr_tid_fx2[2:0]),
  .fac_tid_fx2(fac_tid_fx2[2:0]),
  .fac_rng_fprs(fac_rng_fprs[2:0]),
  .fac_rng_rd_fprs_4f(fac_rng_rd_fprs_4f),
  .fac_rng_wr_gsr_3f(fac_rng_wr_gsr_3f),
  .fac_rng_rd_gsr_4f(fac_rng_rd_gsr_4f),
  .fac_rng_rd_ecc_4f(fac_rng_rd_ecc_4f),
  .fac_rng_rd_or_wr_3f(fac_rng_rd_or_wr_3f),
  .fad_w1_tid_fw(fad_w1_tid_fw[2:0]),
  .fad_w1_vld_fw(fad_w1_vld_fw[1:0]),
  .fad_w2_addr_fw1_b4(fad_w2_addr_fw1_b4),
  .fad_w2_tid_fw1(fad_w2_tid_fw1[2:0]),
  .fad_w2_vld_fw1(fad_w2_vld_fw1[1:0]),
  .fac_frf_r1_addr_e(fac_frf_r1_addr_e[4:0]),
  .fac_tid_e(fac_tid_e[2:0]),
  .fac_aman_fmt_sel_e(fac_aman_fmt_sel_e[4:0]),
  .fac_bman_fmt_sel_e(fac_bman_fmt_sel_e[4:0]),
  .fac_fst_fmt_sel_fx1(fac_fst_fmt_sel_fx1[3:0]),
  .fac_w1_addr_fb(fac_w1_addr_fb[4:0]),
  .fac_fpd_addr_fb(fac_fpd_addr_fb[4:0]),
  .fac_w1_32b_fb(fac_w1_32b_fb),
  .fac_fpd_32b_fb(fac_fpd_32b_fb),
  .fac_w1_odd32b_fb(fac_w1_odd32b_fb),
  .fac_fpd_odd32b_fb(fac_fpd_odd32b_fb),
  .fac_w1_tid_fb(fac_w1_tid_fb[2:0]),
  .fac_fpd_tid_fb(fac_fpd_tid_fb[2:0]),
  .fac_fsr_store_fx2(fac_fsr_store_fx2),
  .fac_exu_src_e(fac_exu_src_e),
  .fac_fsr0_sel_fw(fac_fsr0_sel_fw[5:0]),
  .fac_fsr1_sel_fw(fac_fsr1_sel_fw[5:0]),
  .fac_fsr2_sel_fw(fac_fsr2_sel_fw[5:0]),
  .fac_fsr3_sel_fw(fac_fsr3_sel_fw[5:0]),
  .fac_fsr4_sel_fw(fac_fsr4_sel_fw[5:0]),
  .fac_fsr5_sel_fw(fac_fsr5_sel_fw[5:0]),
  .fac_fsr6_sel_fw(fac_fsr6_sel_fw[5:0]),
  .fac_fsr7_sel_fw(fac_fsr7_sel_fw[5:0]),
  .fac_pre_fcc_vld_fx2(fac_pre_fcc_vld_fx2[3:0]),
  .fac_fcmpe_fx1(fac_fcmpe_fx1),
  .fac_rs2_rotate_sel_e(fac_rs2_rotate_sel_e[4:0]),
  .fac_i2f_sel_e(fac_i2f_sel_e[1:0]),
  .fac_force_swap_blta_fx1(fac_force_swap_blta_fx1),
  .fac_force_noswap_blta_fx1(fac_force_noswap_blta_fx1),
  .fac_xr_mode_fx1(fac_xr_mode_fx1),
  .fac_rs1_sel_fx1(fac_rs1_sel_fx1[4:0]),
  .fac_rs2_sel_fx1(fac_rs2_sel_fx1[3:0]),
  .fac_8x16_rnd_fx3(fac_8x16_rnd_fx3[1:0]),
  .fac_scff_sel_fx3(fac_scff_sel_fx3[3:0]),
  .fac_accum_sel_fx3(fac_accum_sel_fx3[6:0]),
  .fac_result_sel_fx4(fac_result_sel_fx4[5:0]),
  .fac_ma_result_en_fx4(fac_ma_result_en_fx4),
  .fac_div_flush_fx3(fac_div_flush_fx3),
  .fac_div_valid_fx1(fac_div_valid_fx1),
  .fac_divq_valid_fx1(fac_divq_valid_fx1),
  .fac_div_control_fx1(fac_div_control_fx1[4:0]),
  .fac_aexp_fmt_sel_e(fac_aexp_fmt_sel_e[9:0]),
  .fac_bexp_fmt_sel_e(fac_bexp_fmt_sel_e[7:0]),
  .fac_aux_cin_fx1(fac_aux_cin_fx1),
  .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w),
  .lsu_fgu_fld_b(lsu_fgu_fld_b),
  .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]),
  .lsu_fgu_fld_32b_b(lsu_fgu_fld_32b_b),
  .lsu_fgu_fsr_load_b(lsu_fgu_fsr_load_b),
  .lsu_fgu_pmen(lsu_fgu_pmen),
  .lsu_asi_clken(lsu_asi_clken),
  .exu_fgu_gsr_vld_m(exu_fgu_gsr_vld_m[1:0]),
  .exu_fgu_flush_m(exu_fgu_flush_m),
  .fgu_result_tid_fx5(fgu_result_tid_fx5[1:0]),
  .fgu_irf_w_addr_fx5(fgu_irf_w_addr_fx5[4:0]),
  .fgu_exu_cc_vld_fx5(fgu_exu_cc_vld_fx5),
  .fgu_exu_w_vld_fx5(fgu_exu_w_vld_fx5[1:0]),
  .fec_cecc_fx2(fec_cecc_fx2),
  .fec_uecc_fx2(fec_uecc_fx2),
  .fac_r1_vld_fx1(fac_r1_vld_fx1[1:0]),
  .fac_r2_vld_fx1(fac_r2_vld_fx1[1:0]),
  .fac_ecc_trap_en_fx1(fac_ecc_trap_en_fx1),
  .fac_tid_d(fac_tid_d[2:0]),
  .fac_frf_r1_addr_d(fac_frf_r1_addr_d[4:0]),
  .fac_frf_r1_vld_d(fac_frf_r1_vld_d),
  .spu_fgu_fpy_ctl_d(spu_fgu_fpy_ctl_d[6:0]),
  .main_clken(main_clken),
  .main_clken0(main_clken0),
  .mul_clken(mul_clken),
  .div_clken(div_clken),
  .vis_clken(vis_clken),
  .asi_clken(asi_clken),
  .coreon_clken(coreon_clken),
  .spc_aclk_wmr(spc_aclk_wmr),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .mbi_frf_read_en(mbi_frf_read_en),
  .mbi_addr(mbi_addr[7:0]),
  .mbi_run(mbi_run),
  .in_rngl_cdbus(in_rngl_cdbus[64:0]),
  .fac_mbist_addr_1f(fac_mbist_addr_1f[7:0])
 );

fgu_fec_ctl   fec (
 .scan_in(fec_scanin),
 .scan_out(fec_scanout),
 .l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .mbi_frf_read_en(mbi_frf_read_en),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_run(mbi_run),
  .fad_mbist_cmp64_fx1(fad_mbist_cmp64_fx1),
  .lsu_asi_error_inject(lsu_asi_error_inject[31:0]),
  .fad_nombi_w2_result_fw(fad_nombi_w2_result_fw[63:0]),
  .fec_w1_ecc_inject_fb(fec_w1_ecc_inject_fb[6:0]),
  .fec_w2_synd_fw(fec_w2_synd_fw[13:0]),
  .fec_r1_ecc_fx1(fec_r1_ecc_fx1[13:0]),
  .fec_mbist_wdata_1f(fec_mbist_wdata_1f[7:0]),
  .fec_mbist_wdata_3f(fec_mbist_wdata_3f[7:0]),
  .main_clken(main_clken),
  .coreon_clken(coreon_clken),
  .fac_frf_r1_addr_e(fac_frf_r1_addr_e[4:0]),
  .fac_dec_valid_fx1(fac_dec_valid_fx1),
  .fac_fgx_pdist_fx1(fac_fgx_pdist_fx1),
  .fac_ecc_trap_en_fx1(fac_ecc_trap_en_fx1),
  .fac_r1_vld_fx1(fac_r1_vld_fx1[1:0]),
  .fac_r2_vld_fx1(fac_r2_vld_fx1[1:0]),
  .fad_r1_byp_hit_fx1(fad_r1_byp_hit_fx1),
  .fad_r2_byp_hit_fx1(fad_r2_byp_hit_fx1),
  .fpc_frf_store_vld_fx1(fpc_frf_store_vld_fx1),
  .dec_frf_r2_addr_d(dec_frf_r2_addr_d[4:0]),
  .dec_frf_r1_32b_d(dec_frf_r1_32b_d),
  .dec_frf_r2_32b_d(dec_frf_r2_32b_d),
  .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d),
  .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d),
  .dec_flush_f1(dec_flush_f1),
  .dec_flush_f2(dec_flush_f2),
  .tlu_flush_fgu_b(tlu_flush_fgu_b),
  .fad_rs1_fx1(fad_rs1_fx1[63:0]),
  .fad_rs2_fx1(fad_rs2_fx1[63:0]),
  .fad_i_parity_2e_fx1(fad_i_parity_2e_fx1),
  .fad_i_parity_2o_fx1(fad_i_parity_2o_fx1),
  .fad_i_parity_1e_fx1(fad_i_parity_1e_fx1),
  .fad_i_parity_1o_fx1(fad_i_parity_1o_fx1),
  .frf_r1_ecc_e(frf_r1_ecc_e[13:0]),
  .frf_r2_ecc_e(frf_r2_ecc_e[13:0]),
  .fgu_pdist_beat2_fx1(fgu_pdist_beat2_fx1),
  .fgu_ecc_addr_fx2(fgu_ecc_addr_fx2[5:0]),
  .fgu_ecc_check_fx2(fgu_ecc_check_fx2[13:0]),
  .fgu_cecc_fx2(fgu_cecc_fx2),
  .fec_cecc_fx2(fec_cecc_fx2),
  .fgu_uecc_fx2(fgu_uecc_fx2),
  .fec_uecc_fx2(fec_uecc_fx2),
  .fgu_fst_ecc_error_fx2(fgu_fst_ecc_error_fx2),
  .fgu_mbi_frf_fail(fgu_mbi_frf_fail)
 );

// ------------------------------------
// floating point regfile
// ------------------------------------


// 0in custom -fire ( $0in_delay((fpc_w1_vld_fb[0] & fac_frf_r1_vld_d & (fac_w1_tid_fb[2:0] == fac_tid_d[2:0]) & (fac_w1_addr_fb[4:0] == fac_frf_r1_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r1_fld_hit_fb | fad.r1_w1_hit_fb | fad.r1_w2_hit_fw | fad.r1_w2_hit_fw1 | fad.r1_w1_hit_fw | (fad.r1_32b_e & ~fad.r1_odd32b_e))) -message "FRF w1[0] = r1 without bypass" -group core_array

// 0in custom -fire ( $0in_delay((fpc_w1_vld_fb[1] & fac_frf_r1_vld_d & (fac_w1_tid_fb[2:0] == fac_tid_d[2:0]) & (fac_w1_addr_fb[4:0] == fac_frf_r1_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r1_fld_hit_fb | fad.r1_w1_hit_fb | fad.r1_w2_hit_fw | fad.r1_w2_hit_fw1 | fad.r1_w1_hit_fw | (fad.r1_32b_e &  fad.r1_odd32b_e))) -message "FRF w1[1] = r1 without bypass" -group core_array

// 0in custom -fire ( $0in_delay((fad_w2_vld_fw[0] & fac_frf_r1_vld_d & (fad_w2_tid_fw[2:0] == fac_tid_d[2:0]) & (fad_w2_addr_fw[4:0] == fac_frf_r1_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r1_fld_hit_fb | fad.r1_w1_hit_fb | fad.r1_w2_hit_fw | fad.r1_w2_hit_fw1 | fad.r1_w1_hit_fw | (fad.r1_32b_e & ~fad.r1_odd32b_e))) -message "FRF w2[0] = r1 without bypass" -group core_array

// 0in custom -fire ( $0in_delay((fad_w2_vld_fw[1] & fac_frf_r1_vld_d & (fad_w2_tid_fw[2:0] == fac_tid_d[2:0]) & (fad_w2_addr_fw[4:0] == fac_frf_r1_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r1_fld_hit_fb | fad.r1_w1_hit_fb | fad.r1_w2_hit_fw | fad.r1_w2_hit_fw1 | fad.r1_w1_hit_fw | (fad.r1_32b_e &  fad.r1_odd32b_e))) -message "FRF w2[1] = r1 without bypass" -group core_array


// 0in custom -fire ( $0in_delay((fpc_w1_vld_fb[0] & dec_frf_r2_vld_d & (fac_w1_tid_fb[2:0] == fac_tid_d[2:0]) & (fac_w1_addr_fb[4:0] == dec_frf_r2_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r2_fld_hit_fb | fad.r2_w1_hit_fb | fad.r2_w2_hit_fw | fad.r2_w2_hit_fw1 | fad.r2_w1_hit_fw | (fad.r2_32b_e & ~fad.r2_odd32b_e))) -message "FRF w1[0] = r2 without bypass" -group core_array

// 0in custom -fire ( $0in_delay((fpc_w1_vld_fb[1] & dec_frf_r2_vld_d & (fac_w1_tid_fb[2:0] == fac_tid_d[2:0]) & (fac_w1_addr_fb[4:0] == dec_frf_r2_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r2_fld_hit_fb | fad.r2_w1_hit_fb | fad.r2_w2_hit_fw | fad.r2_w2_hit_fw1 | fad.r2_w1_hit_fw | (fad.r2_32b_e &  fad.r2_odd32b_e))) -message "FRF w1[1] = r2 without bypass" -group core_array

// 0in custom -fire ( $0in_delay((fad_w2_vld_fw[0] & dec_frf_r2_vld_d & (fad_w2_tid_fw[2:0] == fac_tid_d[2:0]) & (fad_w2_addr_fw[4:0] == dec_frf_r2_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r2_fld_hit_fb | fad.r2_w1_hit_fb | fad.r2_w2_hit_fw | fad.r2_w2_hit_fw1 | fad.r2_w1_hit_fw | (fad.r2_32b_e & ~fad.r2_odd32b_e))) -message "FRF w2[0] = r2 without bypass" -group core_array

// 0in custom -fire ( $0in_delay((fad_w2_vld_fw[1] & dec_frf_r2_vld_d & (fad_w2_tid_fw[2:0] == fac_tid_d[2:0]) & (fad_w2_addr_fw[4:0] == dec_frf_r2_addr_d[4:0])),1) & ~(fad.fac_exu_src_e | fad.r2_fld_hit_fb | fad.r2_w1_hit_fb | fad.r2_w2_hit_fw | fad.r2_w2_hit_fw1 | fad.r2_w1_hit_fw | (fad.r2_32b_e &  fad.r2_odd32b_e))) -message "FRF w2[1] = r2 without bypass" -group core_array


n2_frf_mp_256x78_cust  frf (

 .scan_in(frf_scanin),
 .scan_out(frf_scanout),
 .l2clk		( l2clk				),
 .pce		( 1'b1				),

 .tcu_aclk	( spc_aclk			),
 .tcu_bclk	( spc_bclk			),

 .w1_addr	( fac_w1_addr_fb[4:0]		),
 .w1_tid	( fac_w1_tid_fb [2:0]		),
 .w1_valid	( fpc_w1_vld_fb [1:0]		),
 .w2_addr	( fad_w2_addr_fw[4:0]		),
 .w2_tid	( fad_w2_tid_fw[2:0]		),
 .w2_valid	( fad_w2_vld_fw[1:0]		),

 .w1_data	( fpf_w1_result_fb[63:0]	),
 .w1_ecc	( fpf_w1_synd_fb[13:0]		),
 .w2_data	( fad_w2_result_fw[63:0]	),
 .w2_ecc	( fec_w2_synd_fw[13:0]		),

 .r_tid		( fac_tid_d[2:0]		),
 .r1_valid	( fac_frf_r1_vld_d		),
 .r1_addr	( fac_frf_r1_addr_d[4:0]	),
 .r2_valid	( dec_frf_r2_vld_d		),
 .r2_addr	( dec_frf_r2_addr_d[4:0]	),

	       	 
   .frf_r1_data		( frf_r1_data_e[63:0]		),
   .frf_r1_ecc		( frf_r1_ecc_e[13:0]		),
   .frf_r2_data		( frf_r2_data_e[63:0]		),
   .frf_r2_ecc		( frf_r2_ecc_e[13:0]		),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .main_clken(main_clken)

 );


// fixscan start:
assign fpf_scanin                = scan_in                  ;
assign fpy_scanin                = fpf_scanout              ;
assign fpe_scanin                = fpy_scanout              ;
assign fpc_scanin                = fpe_scanout              ;
assign fic_scanin                = fpc_scanout              ;
assign fgd_scanin                = fic_scanout              ;
assign fdd_scanin                = fgd_scanout              ;
assign fdc_scanin                = fdd_scanout              ;
assign fad_scanin                = fdc_scanout              ;
assign fac_scanin                = fad_scanout              ;
assign fec_scanin                = fac_scanout              ;
assign frf_scanin                = fec_scanout              ;
assign scan_out                  = frf_scanout              ;

assign fpc_wmr_scanin            = wmr_scan_in              ;
assign fgd_wmr_scanin            = fpc_wmr_scanout          ;
assign fad_wmr_scanin            = fgd_wmr_scanout          ;
assign fac_wmr_scanin            = fad_wmr_scanout          ;
assign wmr_scan_out              = fac_wmr_scanout          ;
// fixscan end:
endmodule // fgu
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fac_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fac_ctl (
  dec_frf_r1_addr_d, 
  dec_frf_r1_vld_d, 
  dec_frf_r2_vld_d, 
  dec_frf_r1_32b_d, 
  dec_frf_r2_32b_d, 
  dec_frf_r1_odd32b_d, 
  dec_frf_r2_odd32b_d, 
  dec_frf_w_vld_d, 
  dec_frf_w_addr_d, 
  dec_frf_w_32b_d, 
  dec_frf_w_odd32b_d, 
  dec_fgu_valid_e, 
  dec_exu_src_vld_d, 
  dec_irf_w_addr_d, 
  dec_spu_grant_d, 
  dec_frf_store_d, 
  dec_fsr_store_d, 
  dec_flush_f1, 
  dec_flush_f2, 
  dec_fgu_op3_d, 
  dec_fgu_opf_d, 
  dec_fgu_decode_d, 
  dec_fgu_tid_d, 
  fgu_cmp_fcc_tid_fx2, 
  fgu_fld_fcc_vld_fx3, 
  fgu_fprs_fef, 
  fgu_divide_completion, 
  tlu_flush_fgu_b, 
  tlu_ceter_pscce, 
  tlu_cerer_frf, 
  spc_core_running_status, 
  fgu_fpx_trap_tid_fw, 
  fgu_fpd_trap_tid_fw, 
  fpc_pre_div_flush_fx2, 
  fpc_div_default_res_fx2, 
  fpc_fsr_w1_vld_fx5, 
  fpc_fcc_vld_fx5, 
  fpc_fpx_unfin_fb, 
  fpc_fpd_unfin_fb, 
  fpc_stfsr_en_fx3to5, 
  fac_tlu_flush_fx3, 
  fac_dec_valid_fx1, 
  fac_fpx_itype_fx1, 
  fac_fpx_dtype_fx1, 
  fac_fpx_stype_fx1, 
  fac_fpx_sign_instr_fx1, 
  fac_fpx_rnd_trunc_fx1, 
  fac_fpx_mulscc_fx1, 
  fac_fpx_saverestore_fx1, 
  fac_fpx_nv_vld_fx1, 
  fac_fpx_of_vld_fx1, 
  fac_fpx_uf_vld_fx1, 
  fac_fpx_dz_vld_fx1, 
  fac_fpx_nx_vld_fx1, 
  fac_fpx_unfin_vld_fx1, 
  fac_fpx_sp_dest_fx1, 
  fac_fpx_sp_src_fx1, 
  fac_fgx_instr_fx4, 
  fac_w1_vld_fx1, 
  fac_w1_odd32b_fx1, 
  fac_gsr_w_vld_fx2, 
  fac_dec_valid_noflush_fx5, 
  fgd_gsr_asr_mask_fx4_b31, 
  fac_fgx_mvcond_fx2, 
  fac_fgx_mvucond_fx2, 
  fac_fgx_abs_fx2, 
  fac_fgx_neg_fx2, 
  fac_fgx_logical_fx2, 
  fac_fgx_expand_fx2, 
  fac_fgx_merge_fx2, 
  fac_fgx_align_fx2, 
  fac_fgx_shuffle_fx2, 
  fac_fgx_pack16_fx2, 
  fac_fgx_pack32_fx2, 
  fac_fgx_packfix_fx2, 
  fac_fgx_pdist_fx1, 
  fac_fgx_popc_fx2, 
  fac_fgx_siam_fx2, 
  fac_fgx_pack_sel_fx2, 
  fac_opf_fx2, 
  fac_gsr_asr_tid_fx2, 
  fac_tid_fx2, 
  fac_rng_fprs, 
  fac_rng_rd_fprs_4f, 
  fac_rng_wr_gsr_3f, 
  fac_rng_rd_gsr_4f, 
  fac_rng_rd_ecc_4f, 
  fac_rng_rd_or_wr_3f, 
  fad_w1_tid_fw, 
  fad_w1_vld_fw, 
  fad_w2_addr_fw1_b4, 
  fad_w2_tid_fw1, 
  fad_w2_vld_fw1, 
  fac_frf_r1_addr_e, 
  fac_tid_e, 
  fac_aman_fmt_sel_e, 
  fac_bman_fmt_sel_e, 
  fac_fst_fmt_sel_fx1, 
  fac_w1_addr_fb, 
  fac_fpd_addr_fb, 
  fac_w1_32b_fb, 
  fac_fpd_32b_fb, 
  fac_w1_odd32b_fb, 
  fac_fpd_odd32b_fb, 
  fac_w1_tid_fb, 
  fac_fpd_tid_fb, 
  fac_fsr_store_fx2, 
  fac_exu_src_e, 
  fac_fsr0_sel_fw, 
  fac_fsr1_sel_fw, 
  fac_fsr2_sel_fw, 
  fac_fsr3_sel_fw, 
  fac_fsr4_sel_fw, 
  fac_fsr5_sel_fw, 
  fac_fsr6_sel_fw, 
  fac_fsr7_sel_fw, 
  fac_pre_fcc_vld_fx2, 
  fac_fcmpe_fx1, 
  fac_rs2_rotate_sel_e, 
  fac_i2f_sel_e, 
  fac_force_swap_blta_fx1, 
  fac_force_noswap_blta_fx1, 
  fac_xr_mode_fx1, 
  fac_rs1_sel_fx1, 
  fac_rs2_sel_fx1, 
  fac_8x16_rnd_fx3, 
  fac_scff_sel_fx3, 
  fac_accum_sel_fx3, 
  fac_result_sel_fx4, 
  fac_ma_result_en_fx4, 
  fdc_finish_int_early, 
  fdc_finish_fltd_early, 
  fdc_finish_flts_early, 
  fac_div_flush_fx3, 
  fac_div_valid_fx1, 
  fac_divq_valid_fx1, 
  fac_div_control_fx1, 
  fac_aexp_fmt_sel_e, 
  fac_bexp_fmt_sel_e, 
  fac_aux_cin_fx1, 
  lsu_fgu_fld_vld_w, 
  lsu_fgu_fld_b, 
  lsu_fgu_fld_tid_b, 
  lsu_fgu_fld_32b_b, 
  lsu_fgu_fsr_load_b, 
  lsu_fgu_pmen, 
  lsu_asi_clken, 
  exu_fgu_gsr_vld_m, 
  exu_fgu_flush_m, 
  fgu_result_tid_fx5, 
  fgu_irf_w_addr_fx5, 
  fgu_exu_cc_vld_fx5, 
  fgu_exu_w_vld_fx5, 
  fec_cecc_fx2, 
  fec_uecc_fx2, 
  fac_r1_vld_fx1, 
  fac_r2_vld_fx1, 
  fac_ecc_trap_en_fx1, 
  fac_tid_d, 
  fac_frf_r1_addr_d, 
  fac_frf_r1_vld_d, 
  spu_fgu_fpy_ctl_d, 
  main_clken, 
  main_clken0, 
  mul_clken, 
  div_clken, 
  vis_clken, 
  asi_clken, 
  coreon_clken, 
  l2clk, 
  scan_in, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  mbi_frf_read_en, 
  mbi_addr, 
  mbi_run, 
  in_rngl_cdbus, 
  fac_mbist_addr_1f, 
  fgu_rngl_cdbus_b64, 
  fgu_rngl_cdbus_b63, 
  scan_out, 
  wmr_scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire l1clk_pm2;
wire main_clken_local;
wire l1clk_pm1;
wire spares_scanin;
wire spares_scanout;
wire fgu_pmen_e;
wire mbist_run_1f;
wire [7:0] core_running_status_1f;
wire fgu_decode_e;
wire spu_grant_e;
wire frf_store_fx1;
wire frf_store_fx2;
wire fsr_store_fx1;
wire fpc_stfsr_en_fb;
wire fpc_stfsr_en_fw;
wire fgu_fld_fx3;
wire fgu_fld_fx4;
wire fgu_fld_fx5;
wire fgu_fld_fb;
wire fgu_decode_fx1;
wire gsr_w_vld_fx2;
wire gsr_w_vld_fx3;
wire gsr_w_vld_fx4;
wire rng_rd_or_wr_1f;
wire rng_rd_or_wr_2f;
wire rng_rd_or_wr_4f;
wire rng_rd_or_wr_5f;
wire dec_valid_fx2;
wire dec_valid_fx3;
wire dec_valid_noflush_fx4;
wire dec_valid_noflush_fb;
wire dec_valid_noflush_fw;
wire dec_valid_noflush_fw1;
wire dec_valid_noflush_fw2;
wire spu_grant_fx1;
wire spu_grant_fx2;
wire spu_grant_fx3;
wire spu_grant_fx4;
wire spu_grant_fx5;
wire div_engine_busy_fx1;
wire div_engine_busy_fx2;
wire divq_occupied_fx1;
wire div_finish_fb;
wire div_finish_fw;
wire div_finish_fw1;
wire div_finish_fw2;
wire div_finish_fw3;
wire fpx_itype_mul_e;
wire itype_mul_fx1;
wire itype_mul_fx2;
wire itype_mul_fx3;
wire dec_valid_imul_noflush_fx4;
wire dec_valid_imul_noflush_fx5;
wire dec_valid_imul_noflush_fb;
wire dec_valid_imul_noflush_fw;
wire dec_valid_imul_noflush_fw1;
wire dec_valid_imul_noflush_fw2;
wire fpx_itype_div_e;
wire fgx_instr_e;
wire fgx_instr_fx1;
wire fgx_instr_fx2;
wire fgx_instr_fx3;
wire fgx_instr_fx5;
wire fgx_instr_fb;
wire fgx_instr_fw;
wire fgx_instr_fw1;
wire fgx_instr_fw2;
wire global_asi_clken;
wire rng_rd_ecc_2f;
wire [2:0] rng_wr_tid_2f;
wire [7:0] rng_data_2f_b7_0;
wire mbist_frf_read_en_1f;
wire e_00_scanin;
wire e_00_scanout;
wire e_01_scanin;
wire e_01_scanout;
wire [5:0] op3_e;
wire [7:0] opf_e;
wire r1_vld_e;
wire r2_vld_e;
wire r1_32b_e;
wire r2_32b_e;
wire r1_odd32b_e;
wire r2_odd32b_e;
wire frf_store_e;
wire fsr_store_e;
wire [4:0] irf_w_addr_e;
wire [6:0] spu_fpy_ctl_e;
wire e_02_scanin;
wire e_02_scanout;
wire w1_vld_e;
wire [4:0] w1_addr_e;
wire w1_32b_e;
wire w1_odd32b_e;
wire exu_w_vld_e;
wire e_03_scanin;
wire e_03_scanout;
wire [24:5] i;
wire [4:0] aman_fmt_sel_e;
wire [3:0] bman_fmt_sel_e;
wire [9:0] aexp_fmt_sel_e;
wire [7:0] bexp_fmt_sel_e;
wire [2:0] fpx_itype_e;
wire [2:0] fpx_dtype_e;
wire [1:0] fpx_stype_e;
wire fpx_sign_instr_e;
wire fpx_rnd_trunc_e;
wire fpx_mulscc_e;
wire fpx_saverestore_e;
wire fpx_int_cc_vld_e;
wire fpx_fmul8x16_e;
wire fpx_fmul8x16au_e;
wire fpx_fmul8x16al_e;
wire fpx_fmul8sux16_e;
wire fpx_fmul8ulx16_e;
wire fpx_fmuld8sux16_e;
wire fpx_fmuld8ulx16_e;
wire fpx_nv_vld_e;
wire fpx_of_vld_e;
wire fpx_uf_vld_e;
wire fpx_dz_vld_e;
wire fpx_nx_vld_e;
wire fpx_unfin_vld_e;
wire fgx_mvcond_e;
wire fgx_mvucond_e;
wire fgx_abs_e;
wire fgx_neg_e;
wire fgx_logical_e;
wire fgx_expand_e;
wire fgx_merge_e;
wire fgx_align_e;
wire fgx_shuffle_e;
wire fgx_pack16_e;
wire fgx_pack32_e;
wire fgx_packfix_e;
wire fgx_pdist_e;
wire fgx_popc_e;
wire fgx_siam_e;
wire q_fgx_pdist_e;
wire [3:0] fst_fmt_sel_e;
wire [4:1] q_aman_fmt_sel_e;
wire [3:0] q_bman_fmt_sel_e;
wire [8:1] q_aexp_fmt_sel_e;
wire [3:1] q_bexp_fmt_sel_e;
wire fpx_sp_dest_e;
wire [1:0] q_w1_vld_e;
wire [1:0] cc_target_e;
wire [3:0] pre_fcc_vld_e;
wire [2:0] i_fsr_w2_vld_fb;
wire div_finish_fltd_fb;
wire div_finish_flts_fb;
wire fsr_w1_qvld_fb;
wire [1:0] fsr_w1_vld_fb;
wire pre_fcc_vld_fb;
wire [3:0] fcc_vld_fb;
wire fsr_w2_qvld_fb;
wire [5:0] fsr0_sel_fb;
wire [5:0] fsr1_sel_fb;
wire [5:0] fsr2_sel_fb;
wire [5:0] fsr3_sel_fb;
wire [5:0] fsr4_sel_fb;
wire [5:0] fsr5_sel_fb;
wire [5:0] fsr6_sel_fb;
wire [5:0] fsr7_sel_fb;
wire [1:0] q_r1_vld_e;
wire [1:0] q_r2_vld_e;
wire force_swap_blta_e;
wire force_noswap_blta_e;
wire xr_mode_e;
wire [4:0] rs1_sel_e;
wire [3:0] rs2_sel_e;
wire [1:0] rnd_8x16_e;
wire [5:0] result_sel_e;
wire div_valid_e;
wire pre_div_flush_fx3;
wire div_dec_issue_fx3;
wire divq_valid_e;
wire div_engine_busy_e;
wire div_finish_early;
wire div_dec_issue_e;
wire div_divq_issue_e;
wire div_divq_load_e;
wire div_hold_e;
wire divq_occupied_e;
wire [2:0] div_tid_in_e;
wire [2:0] divq_tid_fx1;
wire [2:0] div_tid_fx1;
wire [4:0] div_irf_addr_in_e;
wire [4:0] divq_irf_addr_fx1;
wire [4:0] div_irf_addr_fx1;
wire div_cc_vld_in_e;
wire divq_cc_vld_fx1;
wire div_cc_vld_fx1;
wire div_odd32b_in_e;
wire divq_odd32b_fx1;
wire div_odd32b_fx1;
wire div_32b_in_e;
wire divq_32b_fx1;
wire div_32b_fx1;
wire [4:0] div_frf_addr_in_e;
wire [4:0] divq_frf_addr_fx1;
wire [4:0] div_frf_addr_fx1;
wire [2:0] divq_tid_in_e;
wire [4:0] divq_irf_addr_in_e;
wire divq_cc_vld_in_e;
wire divq_odd32b_in_e;
wire divq_32b_in_e;
wire [4:0] divq_frf_addr_in_e;
wire [4:0] div_control_e;
wire fx1_00_scanin;
wire fx1_00_scanout;
wire [4:1] opf_fx1;
wire fpx_int_cc_vld_fx1;
wire fgx_mvcond_fx1;
wire fgx_mvucond_fx1;
wire fgx_abs_fx1;
wire fgx_neg_fx1;
wire fgx_logical_fx1;
wire fgx_expand_fx1;
wire fgx_merge_fx1;
wire fgx_align_fx1;
wire fgx_shuffle_fx1;
wire fgx_pack16_fx1;
wire fgx_pack32_fx1;
wire fgx_packfix_fx1;
wire fgx_popc_fx1;
wire i_fgx_siam_fx1;
wire [1:0] rnd_8x16_fx1;
wire [5:0] result_sel_fx1;
wire i_exu_w_vld_fx1;
wire [4:0] irf_w_addr_fx1;
wire div_dec_issue_fx1;
wire div_divq_issue_fx1;
wire [5:0] spu_fpy_ctl_fx1;
wire fx1_01_scanin;
wire fx1_01_scanout;
wire [4:0] w1_addr_fx1;
wire w1_32b_fx1;
wire [2:0] tid_fx1;
wire [1:0] q_w1_vld_fx1;
wire cerer_frf_fx1;
wire [7:0] ceter_pscce_fx1;
wire fx1_02_scanin;
wire fx1_02_scanout;
wire [3:0] pre_fcc_vld_fx1;
wire fgx_pack_sel_fx1;
wire fgx_moves_fx1;
wire fgx_siam_fx1;
wire exu_w_vld_fx1;
wire q_div_default_res_fx3;
wire div_default_res_fx3;
wire dec_flush_fx3;
wire [7:0] divide_completion_fx1;
wire [2:0] tid_fx3;
wire fx2_00_scanin;
wire fx2_00_scanout;
wire [4:0] w1_addr_fx2;
wire w1_32b_fx2;
wire w1_odd32b_fx2;
wire [2:0] tid_fx2;
wire i_exu_w_vld_fx2;
wire [4:0] irf_w_addr_fx2;
wire fx2_01_scanin;
wire fx2_01_scanout;
wire [1:0] rnd_8x16_fx2;
wire [5:0] result_sel_fx2;
wire fpx_int_cc_vld_fx2;
wire dec_flush_fx2;
wire [3:0] i_pre_fcc_vld_fx2;
wire div_dec_issue_fx2;
wire div_divq_issue_fx2;
wire [2:0] itype_fx2;
wire [5:0] spu_fpy_ctl_fx2;
wire rs2_sel_fx2_b2;
wire fx2_02_scanin;
wire fx2_02_scanout;
wire exu_flush_fx2;
wire [2:0] rng_wr_tid_3f;
wire dec_valid_noflush_fx2;
wire exu_w_vld_fx2;
wire pre_fcc_vld_fx2;
wire [1:0] i_fld_fcc_vld_fx2;
wire [3:0] scff_sel_fx2;
wire [6:0] accum_sel_fx2;
wire fx3_00_scanin;
wire fx3_00_scanout;
wire [4:0] w1_addr_fx3;
wire w1_32b_fx3;
wire w1_odd32b_fx3;
wire [5:0] result_sel_fx3;
wire i_exu_w_vld_fx3;
wire [4:0] irf_w_addr_fx3;
wire fpx_int_cc_vld_fx3;
wire i_pre_div_flush_fx3;
wire [2:0] itype_fx3;
wire [5:5] spu_fpy_ctl_fx3;
wire i_pre_fcc_vld_fx3;
wire i_dec_valid_noflush_fx3;
wire fx3_01_scanin;
wire fx3_01_scanout;
wire pre_fcc_vld_fx3;
wire dec_valid_noflush_fx3;
wire dec_valid_imul_noflush_fx3;
wire exu_w_vld_fx3;
wire fx4_00_scanin;
wire fx4_00_scanout;
wire [4:0] w1_addr_fx4;
wire w1_32b_fx4;
wire w1_odd32b_fx4;
wire [2:0] tid_fx4;
wire exu_w_vld_fx4;
wire [4:0] i_irf_w_addr_fx4;
wire i_int_cc_vld_fx4;
wire [5:5] spu_fpy_ctl_fx4;
wire pre_fcc_vld_fx4;
wire [2:0] irf_result_tid_fx4;
wire [4:0] irf_w_addr_fx4;
wire exu_cc_vld_fx4;
wire fx5_00_scanin;
wire fx5_00_scanout;
wire [4:0] w1_addr_fx5;
wire w1_32b_fx5;
wire w1_odd32b_fx5;
wire [2:0] tid_fx5;
wire i_exu_w_vld_fx5;
wire irf_result_tid_fx5_b2;
wire exu_cc_vld_fx5;
wire pre_fcc_vld_fx5;
wire div_finish_int_fb;
wire fb_00_scanin;
wire fb_00_scanout;
wire fw_00_scanin;
wire fw_00_scanout;
wire w1_addr_fw_b4;
wire fw_01_scanin;
wire fw_01_scanout;
wire [3:0] i_fsr0_sel_fw;
wire [3:0] i_fsr1_sel_fw;
wire [3:0] i_fsr2_sel_fw;
wire [3:0] i_fsr3_sel_fw;
wire [3:0] i_fsr4_sel_fw;
wire [3:0] i_fsr5_sel_fw;
wire [3:0] i_fsr6_sel_fw;
wire [3:0] i_fsr7_sel_fw;
wire [2:0] lsu_fgu_fld_tid_fw;
wire [1:0] i_fsr_w2_vld_fw;
wire [1:0] fsr_w2_vld_fw;
wire fprs_frf_ctl_scanin;
wire fprs_frf_ctl_scanout;
wire [4:4] fprs_w1_addr;
wire [2:0] fprs_w1_tid;
wire [1:0] fprs_w1_vld;
wire [4:4] fprs_w2_addr;
wire [2:0] fprs_w2_tid;
wire [1:0] fprs_w2_vld;
wire [3:0] fprs_tid0_sel;
wire rng_wr_fprs_3f;
wire [2:0] din_fprs_tid0;
wire [2:0] fprs_tid0;
wire fprstid0_wmr_scanin;
wire fprstid0_wmr_scanout;
wire [2:2] fprs_tid0_;
wire [3:0] fprs_tid1_sel;
wire [2:0] din_fprs_tid1;
wire [2:0] fprs_tid1;
wire fprstid1_wmr_scanin;
wire fprstid1_wmr_scanout;
wire [2:2] fprs_tid1_;
wire [3:0] fprs_tid2_sel;
wire [2:0] din_fprs_tid2;
wire [2:0] fprs_tid2;
wire fprstid2_wmr_scanin;
wire fprstid2_wmr_scanout;
wire [2:2] fprs_tid2_;
wire [3:0] fprs_tid3_sel;
wire [2:0] din_fprs_tid3;
wire [2:0] fprs_tid3;
wire fprstid3_wmr_scanin;
wire fprstid3_wmr_scanout;
wire [2:2] fprs_tid3_;
wire [3:0] fprs_tid4_sel;
wire [2:0] din_fprs_tid4;
wire [2:0] fprs_tid4;
wire fprstid4_wmr_scanin;
wire fprstid4_wmr_scanout;
wire [2:2] fprs_tid4_;
wire [3:0] fprs_tid5_sel;
wire [2:0] din_fprs_tid5;
wire [2:0] fprs_tid5;
wire fprstid5_wmr_scanin;
wire fprstid5_wmr_scanout;
wire [2:2] fprs_tid5_;
wire [3:0] fprs_tid6_sel;
wire [2:0] din_fprs_tid6;
wire [2:0] fprs_tid6;
wire fprstid6_wmr_scanin;
wire fprstid6_wmr_scanout;
wire [2:2] fprs_tid6_;
wire [3:0] fprs_tid7_sel;
wire [2:0] din_fprs_tid7;
wire [2:0] fprs_tid7;
wire fprstid7_wmr_scanin;
wire fprstid7_wmr_scanout;
wire [2:2] fprs_tid7_;
wire [2:0] din_rng_fprs;
wire fprs_rng_scanin;
wire fprs_rng_scanout;
wire rng_stg1_scanin;
wire rng_stg1_scanout;
wire rng_ctl_1f;
wire rng_valid_1f;
wire [62:48] rng_data_1f;
wire [7:0] rng_data_1f_b7_0;
wire rng_rd_1f;
wire rng_wr_1f;
wire rng_rd_gsr_1f;
wire rng_wr_gsr_1f;
wire rng_rd_fprs_1f;
wire rng_wr_fprs_1f;
wire rng_rd_ecc_1f;
wire rng_stg2_scanin;
wire rng_stg2_scanout;
wire rng_wr_gsr_2f;
wire rng_rd_gsr_2f;
wire rng_rd_fprs_2f;
wire rng_wr_fprs_2f;
wire rng_6463_scanin;
wire rng_6463_scanout;
wire rng_ctl_2f;
wire rng_valid_2f;
wire rng_ctl_3f;
wire rng_cdbus_3f_b63;
wire rng_valid_3f;
wire rng_stg3_scanin;
wire rng_stg3_scanout;
wire rng_rd_gsr_3f;
wire rng_rd_fprs_3f;
wire rng_rd_ecc_3f;
wire rng_b64_default_sel;
wire rng_stg4_scanin;
wire rng_stg4_scanout;


// ----------------------------------------------------------------------------
// Interface with DEC
// ----------------------------------------------------------------------------

input    [4:0] dec_frf_r1_addr_d;
input          dec_frf_r1_vld_d;
input          dec_frf_r2_vld_d;
input          dec_frf_r1_32b_d;
input          dec_frf_r2_32b_d;
input          dec_frf_r1_odd32b_d;
input          dec_frf_r2_odd32b_d;

input          dec_frf_w_vld_d;
input    [4:0] dec_frf_w_addr_d;
input          dec_frf_w_32b_d;
input          dec_frf_w_odd32b_d;

input          dec_fgu_valid_e;
input          dec_exu_src_vld_d;
input    [4:0] dec_irf_w_addr_d;

input          dec_spu_grant_d;
input          dec_frf_store_d;
input          dec_fsr_store_d;

input          dec_flush_f1;           // flush fx2 (xmit in fx1/m)
input          dec_flush_f2;           // flush fx3 (xmit in fx2/b)

input    [5:0] dec_fgu_op3_d;
input    [7:0] dec_fgu_opf_d;
input          dec_fgu_decode_d;       // FGU instr issue valid (d stage)
input    [2:0] dec_fgu_tid_d;

output   [2:0] fgu_cmp_fcc_tid_fx2;    // fcmp  fcc data TID
output   [1:0] fgu_fld_fcc_vld_fx3;    // ldfsr fcc data valid {fcc3, fcc2, fcc1}, fcc0
output   [7:0] fgu_fprs_fef;           // FPRS.fef for each TID

output   [7:0] fgu_divide_completion;  // FPD completion/TID

// ----------------------------------------------------------------------------
// Interface with TLU
// ----------------------------------------------------------------------------

input          tlu_flush_fgu_b;        // flush fx3, non-load (xmit in fx2/b)
input    [7:0] tlu_ceter_pscce;        // core error trap enable reg precise enable
input          tlu_cerer_frf;          // FRF ecc error trap enable
input    [7:0] spc_core_running_status; // thread active

output   [2:0] fgu_fpx_trap_tid_fw;
output   [2:0] fgu_fpd_trap_tid_fw;

// ----------------------------------------------------------------------------
// Interface with FPC
// ----------------------------------------------------------------------------

input          fpc_pre_div_flush_fx2;
input          fpc_div_default_res_fx2; // fdiv/fsqrt default result
input    [1:0] fpc_fsr_w1_vld_fx5;     // FSR w1 write valid
input    [3:0] fpc_fcc_vld_fx5;
input          fpc_fpx_unfin_fb;
input          fpc_fpd_unfin_fb;
input          fpc_stfsr_en_fx3to5;    // store FSR clears ftt

output         fac_tlu_flush_fx3;
output         fac_dec_valid_fx1;
output   [2:0] fac_fpx_itype_fx1;      // instr type:
                                       // add=000, fpfp=001, fpint=010, intfp=011, cmp=100, mul=101, div=110, sqrt=111
output   [2:0] fac_fpx_dtype_fx1;      // destination type:
                                       // sp=000, dp=001, 16bit=010, 32bit=011, 64bit=100
output   [1:0] fac_fpx_stype_fx1;      // source type (for conversions & FsMULd/FMULd):
                                       // sp=00, dp=01, 32bit=10, 64bit=11
output         fac_fpx_sign_instr_fx1; // sign of the instr (1 if: FSUB(s,d),
                                       // FPSUB{16,32}{s})
output         fac_fpx_rnd_trunc_fx1;  // force rnd mode to truncate
                                       // (1 if: F(s,d)TOi, F(s,d)TOx,
                                       // FPADD{16,32}{s}, FPSUB{16,32}{s},
                                       // IMUL, IDIV, MULScc, 8x16 mul, SAVE, RESTORE
output         fac_fpx_mulscc_fx1;     // MULScc
output         fac_fpx_saverestore_fx1;// SAVE or RESTORE
output         fac_fpx_nv_vld_fx1;     // set if instr updates invalid exception flag
output         fac_fpx_of_vld_fx1;     // set if instr updates overflow exception flag
output         fac_fpx_uf_vld_fx1;     // set if instr updates underflow exception flag
output         fac_fpx_dz_vld_fx1;     // set if instr updates divide by zero exception flag
output         fac_fpx_nx_vld_fx1;     // set if instr updates inexact exception flag
output         fac_fpx_unfin_vld_fx1;  // set if instr can generate unfinished_FPop

output         fac_fpx_sp_dest_fx1;    // sp destination
output         fac_fpx_sp_src_fx1;     // sp source
output         fac_fgx_instr_fx4;      // FGX instr decoded
output   [1:0] fac_w1_vld_fx1;
output         fac_w1_odd32b_fx1;
output   [1:0] fac_gsr_w_vld_fx2;
output         fac_dec_valid_noflush_fx5;

// ----------------------------------------------------------------------------
// Interface with FGD
// ----------------------------------------------------------------------------

input          fgd_gsr_asr_mask_fx4_b31;

output         fac_fgx_mvcond_fx2;     // FMOV (conditional upon cc or r)
output         fac_fgx_mvucond_fx2;    // FMOV (unconditional)
output         fac_fgx_abs_fx2;        // FABS
output         fac_fgx_neg_fx2;        // FNEG
output         fac_fgx_logical_fx2;    // logical instructions
output         fac_fgx_expand_fx2;     // FEXPAND
output         fac_fgx_merge_fx2;      // FPMERGE
output         fac_fgx_align_fx2;      // FALIGNDATA
output         fac_fgx_shuffle_fx2;    // BSHUFFLE
output         fac_fgx_pack16_fx2;     // FPACK16
output         fac_fgx_pack32_fx2;     // FPACK32
output         fac_fgx_packfix_fx2;    // FPACKFIX
output         fac_fgx_pdist_fx1;      // PDIST
output         fac_fgx_popc_fx2;       // POPC
output         fac_fgx_siam_fx2;       // SIAM

output         fac_fgx_pack_sel_fx2;   // FPACK16,FPACK32,FPACKFIX

output   [4:1] fac_opf_fx2;            // instr opf field
output   [2:0] fac_gsr_asr_tid_fx2;
output   [2:0] fac_tid_fx2;

output   [2:0] fac_rng_fprs;           // ASR FPRS read data
output         fac_rng_rd_fprs_4f;     // ASR FPRS read
output         fac_rng_wr_gsr_3f;      // ASR GSR  write valid
output         fac_rng_rd_gsr_4f;      // ASR GSR  read
output         fac_rng_rd_ecc_4f;      // ASI FRF ECC read
output         fac_rng_rd_or_wr_3f;    // ASR GSR/FPRS read or write decoded

// ----------------------------------------------------------------------------
// Interface with FAD
// ----------------------------------------------------------------------------

input    [2:0] fad_w1_tid_fw;          // FRF w1 write TID
input    [1:0] fad_w1_vld_fw;          // FRF w1 write valid (qualified)
input          fad_w2_addr_fw1_b4;     // FRF w2 write addr
input    [2:0] fad_w2_tid_fw1;         // FRF w2 write TID
input    [1:0] fad_w2_vld_fw1;         // FRF w2 write valid (qualified)

output   [4:0] fac_frf_r1_addr_e;
output   [2:0] fac_tid_e;
output   [4:0] fac_aman_fmt_sel_e;     // aop mantissa format mux select
output   [4:0] fac_bman_fmt_sel_e;     // bop mantissa format mux select
output   [3:0] fac_fst_fmt_sel_fx1;    // store format mux select

output   [4:0] fac_w1_addr_fb;         // FRF w1 write addr
output   [4:0] fac_fpd_addr_fb;        // FRF w2 write addr (div/sqrt)
output         fac_w1_32b_fb;          // FRF w1 is 32-bit dest
output         fac_fpd_32b_fb;         // FRF w2 is 32-bit dest (div/sqrt)
output         fac_w1_odd32b_fb;       // FRF w1 is odd 32-bit dest (32 LSBs)
output         fac_fpd_odd32b_fb;      // FRF w2 is odd 32-bit dest (32 LSBs) (div/sqrt)

output   [2:0] fac_w1_tid_fb;          // FRF w1 TID
output   [2:0] fac_fpd_tid_fb;         // FRF w2 TID (div/sqrt)

output         fac_fsr_store_fx2;

output         fac_exu_src_e;

output   [5:0] fac_fsr0_sel_fw;
output   [5:0] fac_fsr1_sel_fw;
output   [5:0] fac_fsr2_sel_fw;
output   [5:0] fac_fsr3_sel_fw;
output   [5:0] fac_fsr4_sel_fw;
output   [5:0] fac_fsr5_sel_fw;
output   [5:0] fac_fsr6_sel_fw;
output   [5:0] fac_fsr7_sel_fw;

// ----------------------------------------------------------------------------
// Interface with FPF
// ----------------------------------------------------------------------------

output   [3:0] fac_pre_fcc_vld_fx2;    // must clear fcc_vld if (nv & TEM)
output         fac_fcmpe_fx1;          // FCMPE, not FCMP
output   [4:0] fac_rs2_rotate_sel_e;   // 001=odd FiTO(s,d), 010=even FiTO(s,d), 100=FiTO(s,d)
output   [1:0] fac_i2f_sel_e;          // 01=F(i,x)TO(s,d), 10=~F(i,x)TO(s,d)
output         fac_force_swap_blta_fx1; // force the swap_blta condition
output         fac_force_noswap_blta_fx1; // force the ~swap_blta condition

// ----------------------------------------------------------------------------
// Interface with FPY
// ----------------------------------------------------------------------------

output	       fac_xr_mode_fx1;	       //  0  : Int or Float
			               //  1  : XOR mult

output   [4:0] fac_rs1_sel_fx1;	       // [0] : FMUL8SUx16 or FMULD8SUx16
				       // [1] : FMUL8x16   or FMUL8x16AU  or FMUL8x16AL
				       // [2] : FMUL8ULx16 or FMULD8ULx16
				       // [3] : MA Int / XOR   forward of last MA result
				       // [4] : MA Int / XOR unforwarded
				       // Def : 64 * 64 Multiply

output   [3:0] fac_rs2_sel_fx1;	       // [0] : FMUL8x16AU
				       // [1] : FMUL8x16AL
				       // [2] : all 8x16
				       // [3] : MA Int / XOR
				       // Def : 64 * 64 Multiply

output   [1:0] fac_8x16_rnd_fx3;       // [0] : FMUL8x16 or FMUL8x16AU or FMUL8x16AL or FMUL8SUx16
				       // [1] : FMUL8ULx16

output   [3:0] fac_scff_sel_fx3;       // [0] : Int, Float, MA Int
				       // [1] : all 8x16
				       // [2] : MA Int   * 2
				       // [3] : XOR mult
				       // Def : XOR mult * 2

output   [6:0] fac_accum_sel_fx3;      // [0] : Write ACCUM with result
				       // [1] : Add ACCUM to Mult product
				       // [2] : XOR Mult w/        ACCUM
				       // [3] : XOR Mult w/        ACCUM >> 64
				       // [4] : XOR Mult       w/o ACCUM
				       // [5] : XOR Mult       w/o ACCUM >> 64
				       // [6] : Int Mult w/ or w/o ACCUM
 				       // Def : Int Mult w/ or w/o ACCUM >> 64

output   [5:0] fac_result_sel_fx4;     // [0] : FMUL8x16   or FMUL8x16AU or FMUL8x16AL or FMUL8SUx16
				       // [1] : FMUL8ULx16
				       // [2] : FMULD8SUx16
				       // [3] : FMULD8ULx16
				       // [4] : XOR multiply w/ ACCUMUMATE
				       // [5] : Float
				       // Def : Integer, MA Integer w/ and w/o ACCUMULATE, XOR w/o ACCUMULATE

output	       fac_ma_result_en_fx4;   //  1  : Save last MA result in shadow flop

// ----------------------------------------------------------------------------
// Interface with FDC
// ----------------------------------------------------------------------------

input          fdc_finish_int_early;
input 	       fdc_finish_fltd_early;
input          fdc_finish_flts_early;
output         fac_div_flush_fx3;
output         fac_div_valid_fx1;
output         fac_divq_valid_fx1;
output   [4:0] fac_div_control_fx1;    // [4:0]  :
                                       //  0000  : Float Divide Single
                                       //  0010  : Float Divide Double
                                       //  0100  : Integer Unsigned - 32 bit
                                       //  0101  : Integer   Signed - 32 bit
                                       //  0110  : Integer Unsigned - 64 bit
                                       //  0111  : Integer   Signed - 64 bit
                                       //  1000  : Float SQRT   Single
                                       //  1010  : Float SQRT   Double

// ----------------------------------------------------------------------------
// Interface with FPE
// ----------------------------------------------------------------------------

output   [9:0] fac_aexp_fmt_sel_e;     // aop exponent format mux select
output   [7:0] fac_bexp_fmt_sel_e;     // bop exponent format mux select
output         fac_aux_cin_fx1;        // aux exp adder cin

// ----------------------------------------------------------------------------
// Interface with LSU
// ----------------------------------------------------------------------------

input          lsu_fgu_fld_vld_w;
input          lsu_fgu_fld_b;          // FRF load data (unqualified)
input    [2:0] lsu_fgu_fld_tid_b;
input          lsu_fgu_fld_32b_b;
input          lsu_fgu_fsr_load_b;
input          lsu_fgu_pmen;
input          lsu_asi_clken;

// ----------------------------------------------------------------------------
// Interface with EXU
// ----------------------------------------------------------------------------

input    [1:0] exu_fgu_gsr_vld_m;      // GSR data valid {align,mask}
input          exu_fgu_flush_m;        // EXU{1,0} src has bad ECC or exception, FGU must flush instr
output   [1:0] fgu_result_tid_fx5;
output   [4:0] fgu_irf_w_addr_fx5;
output         fgu_exu_cc_vld_fx5;
output   [1:0] fgu_exu_w_vld_fx5;

// ----------------------------------------------------------------------------
// Interface with FEC
// ----------------------------------------------------------------------------

input          fec_cecc_fx2;
input          fec_uecc_fx2;
output   [1:0] fac_r1_vld_fx1;         // FRF r1 read valid (unqualified)
output   [1:0] fac_r2_vld_fx1;         // FRF r2 read valid (unqualified)
output         fac_ecc_trap_en_fx1;

// ----------------------------------------------------------------------------
// Interface with FRF
// ----------------------------------------------------------------------------

output   [2:0] fac_tid_d;
output   [4:0] fac_frf_r1_addr_d;
output         fac_frf_r1_vld_d;

// ----------------------------------------------------------------------------
// Interface with SPU
// ----------------------------------------------------------------------------

input    [6:0] spu_fgu_fpy_ctl_d;      // Mult control

// ----------------------------------------------------------------------------
// Power Management Signals
// ----------------------------------------------------------------------------

output         main_clken;             // main clken: controls fad,fec,fpf,fpe,fac,fic,fpc
output         main_clken0;            // main clken: controls fad,fec,fpf,fpe,fac,fic,fpc
output         mul_clken;              // multiply clken: controls fpy
output         div_clken;              // divide clken: controls fdc,fdd
output         vis_clken;              // vis clken: controls fgd
output         asi_clken;              // asi clken: controls ASI ring stage flops in fgd
output         coreon_clken;           // coreon_clken: controls all "free running" flops in fac,fec,fpc,fad,fgd

// ----------------------------------------------------------------------------
// Global Signals
// ----------------------------------------------------------------------------

input          l2clk;                  // clock input
input	       scan_in;
input          spc_aclk_wmr;
input          wmr_scan_in;
input	       tcu_pce_ov;	       // scan signals
input	       spc_aclk;
input	       spc_bclk;
input          tcu_scan_en;
input          mbi_frf_read_en;        // MBIST
input    [7:0] mbi_addr;               // MBIST
input          mbi_run;                // MBIST
input   [64:0] in_rngl_cdbus;          // ASI local ring

output   [7:0] fac_mbist_addr_1f;      // MBIST
output         fgu_rngl_cdbus_b64;     // ASI local ring
output         fgu_rngl_cdbus_b63;     // ASI local ring
output 	       scan_out;
output         wmr_scan_out;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop   = 1'b0;
assign siclk  = spc_aclk;
assign soclk  = spc_bclk;
assign se     = tcu_scan_en;
// end scan


fgu_fac_ctl_l1clkhdr_ctl_macro clkgen_freerun (
  .l2clk(l2clk),
  .l1en (1'b1),
  .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fac_ctl_l1clkhdr_ctl_macro clkgen_coreon (
  .l2clk(l2clk),
  .l1en (coreon_clken),
  .l1clk(l1clk_pm2),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fac_ctl_l1clkhdr_ctl_macro clkgen_main (
  .l2clk(l2clk),
  .l1en (main_clken_local),
  .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fac_ctl_spare_ctl_macro__num_5 spares  (  // spares: 13 gates + 1 flop for each "num"
  .scan_in(spares_scanin),
  .scan_out(spares_scanout),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
  );


// ------------------------------------
// Power management
//   Wakeup conditions:
//   - DEC issues FGU instr (includes frf_store, fsr_store)
//   - DEC grants SPU access to FGU
//   - LSU presents frf_load or fsr_load data
//   - EXU presents bmask or alignaddress data
//   - ASI ring accesses FGU resource (FPRS, GSR, FRF ECC check bits)
//   - WARNING - wakeup for MBIST, Macro Test, other?
//   Remain active conditions:
//   - FGU instr active in any pipe stage
//   - SPU instr active in any pipe stage
//   - divide engine is busy (incl pre and post engine)
//   - ASI ring bypassing non-FGU ctl/data
//   Note: Generally, clks are allowed to remain active for 1 more cyc
//         than the min solution to ensure that any state which controls
//         the update of an architected facility is allowed to clear.
//         Otherwise, when clks are re-enabled, an extra write of the
//         architected facility may occur (but would write that same data).
// ------------------------------------

// coreon_clken: controls all "free running" flops in fac,fec,fpc,fad,fgd

assign  coreon_clken =

  ~fgu_pmen_e               |      // force clken=1 if FGU global power management isn't enabled
  mbist_run_1f              |      // MBIST
  (|core_running_status_1f[7:0]);  // any of the 8 threads are active

// 0in custom -fire ((mul_clken | div_clken | vis_clken) & ~main_clken) -message "Invalid FGU power management state"

// main clken: controls fad,fec,fpf,fpe,fac,fic,fpc

assign  main_clken =  // may be used to turn on fx1 flops

  ~fgu_pmen_e               |  // force clken=1 if FGU global power management isn't enabled

  mbist_run_1f              |  // MBIST

  fgu_decode_e              |  // includes frf_store, fsr_store, bmask, alignaddress
  spu_grant_e               |

  frf_store_fx1             |  // active 1 xtra cyc
  frf_store_fx2             |  // active 2nd xtra cyc to allow fgu_{u,c}ecc_fx2 to clear

  fsr_store_fx1             |
  fac_fsr_store_fx2         |
  fpc_stfsr_en_fx3to5       |  // store FSR clears ftt
  fpc_stfsr_en_fb           |  // allow FSR update
  fpc_stfsr_en_fw           |  // active 1 xtra cyc

  fgu_fld_fx3               |  // frf_load doesn't need to turn on bypass flops because the
                               //   instr in E needing the bypass will take care of that.
                               // fsr_load needs clks on the cyc following lsu_fgu_fsr_load_b
                               //   so the arch fsr is captured.
  fgu_fld_fx4               |  // allow FPRS update
  fgu_fld_fx5               |  // allow FPRS update
  fgu_fld_fb                |  // active 1 xtra cyc

  fgu_decode_fx1            |  // bmask or alignaddress
  gsr_w_vld_fx2             |  // exu_fgu_gsr_vld_m[1:0] needs fx3 and fx4 flop clks on so the
  gsr_w_vld_fx3             |  //   arch gsr (fx4 flop) is captured
  gsr_w_vld_fx4             |  // active 1 xtra cyc

  rng_rd_or_wr_1f           |  // ASI ring accesses FGU resource
  rng_rd_or_wr_2f           |
  fac_rng_rd_or_wr_3f       |  // FRF ECC check bits rd/wr occurs during 3f
  rng_rd_or_wr_4f           |
  rng_rd_or_wr_5f           |  // active 1 xtra cyc

  fac_dec_valid_fx1         |  // E stage is covered in this eq. by fgu_decode_e
  dec_valid_fx2             |
  dec_valid_fx3             |
  dec_valid_noflush_fx4     |
  fac_dec_valid_noflush_fx5 |
  dec_valid_noflush_fb      |
  dec_valid_noflush_fw      |  // allow FPRS update
  dec_valid_noflush_fw1     |  // allow FPRS update
  dec_valid_noflush_fw2     |  // active 1 xtra cyc

  spu_grant_fx1             |  // E stage is covered in this eq. by spu_grant_e
  spu_grant_fx2             |
  spu_grant_fx3             |
  spu_grant_fx4             |
  spu_grant_fx5             |  // active 1 xtra cyc

  div_engine_busy_fx1       |  // cyc prior to engine_busy are covered in this eq. by fgu_decode_e
  div_engine_busy_fx2       |  // ensure fdc internal engine_running_lth has 1 cyc to clear
  divq_occupied_fx1         |
  div_finish_fb             |
  div_finish_fw             |
  div_finish_fw1            |  // allow FPRS update
  div_finish_fw2            |  // allow FPRS update
  div_finish_fw3            ;  // active 1 xtra cyc

assign  main_clken0      = main_clken;
assign  main_clken_local = main_clken;

// multiply clken: controls fpy

assign  mul_clken =

  ~fgu_pmen_e               |  // force clken=1 if FGU global power management isn't enabled

  (fgu_decode_e              & fpx_itype_mul_e  ) |
  (fac_dec_valid_fx1         &     itype_mul_fx1) |
  (dec_valid_fx2             &     itype_mul_fx2) |
  (dec_valid_fx3             &     itype_mul_fx3) |
  dec_valid_imul_noflush_fx4 |
  dec_valid_imul_noflush_fx5 |
  dec_valid_imul_noflush_fb  |
  dec_valid_imul_noflush_fw  |  // allow FPRS update
  dec_valid_imul_noflush_fw1 |  // allow FPRS update
  dec_valid_imul_noflush_fw2 |  // active 1 xtra cyc

  spu_grant_e               |
  spu_grant_fx1             |
  spu_grant_fx2             |
  spu_grant_fx3             |
  spu_grant_fx4             |
  spu_grant_fx5             ;  // active 1 xtra cyc

// divide clken: controls fdc,fdd

assign  div_clken =

  ~fgu_pmen_e               |  // force clken=1 if FGU global power management isn't enabled

  (fgu_decode_e              &      fpx_itype_div_e              ) |
  div_engine_busy_fx1       |
  div_engine_busy_fx2       |  // ensure fdc internal engine_running_lth has 1 cyc to clear
  divq_occupied_fx1         |
  div_finish_fb             |
  div_finish_fw             |
  div_finish_fw1            |  // allow FPRS update
  div_finish_fw2            |  // allow FPRS update
  div_finish_fw3            ;  // active 1 xtra cyc

// vis clken: controls fgd

assign  vis_clken =

  ~fgu_pmen_e               |  // force clken=1 if FGU global power management isn't enabled

  fgu_decode_fx1            |  // bmask or alignaddress
  gsr_w_vld_fx2             |  // exu_fgu_gsr_vld_m[1:0] needs fx3 and fx4 flop clks on so the
  gsr_w_vld_fx3             |  //   arch gsr (fx4 flop) is captured
  gsr_w_vld_fx4             |  // active 1 xtra cyc

  rng_rd_or_wr_1f           |  // ASI ring accesses FGU resource
  rng_rd_or_wr_2f           |
  fac_rng_rd_or_wr_3f       |  // FRF ECC check bits rd/wr occurs during 3f
  rng_rd_or_wr_4f           |
  rng_rd_or_wr_5f           |  // active 1 xtra cyc

  (fgu_decode_e              &      fgx_instr_e                  ) |
  (fac_dec_valid_fx1         &      fgx_instr_fx1                ) |
  (dec_valid_fx2             &      fgx_instr_fx2                ) |
  (dec_valid_fx3             &      fgx_instr_fx3                ) |
  (dec_valid_noflush_fx4     &  fac_fgx_instr_fx4                ) |
  (fac_dec_valid_noflush_fx5 &      fgx_instr_fx5                ) |
  (dec_valid_noflush_fb      &      fgx_instr_fb                 ) |
  (dec_valid_noflush_fw      &      fgx_instr_fw                 ) |  // allow FPRS update
  (dec_valid_noflush_fw1     &      fgx_instr_fw1                ) |  // allow FPRS update
  (dec_valid_noflush_fw2     &      fgx_instr_fw2                ) ;  // active 1 xtra cyc


// ASI clken: controls ASI ring stage flops in fgd

assign  asi_clken = global_asi_clken;  // can be forced active via ASI_SPARC_PWR_MGMT.misc


// ----------------------------------------------------------------------------
//                               D stage
// ----------------------------------------------------------------------------

assign  fac_tid_d[2:0] =
  ({3{ mbist_run_1f                 }} & fac_mbist_addr_1f[7:5]) |  // MBIST
  ({3{~mbist_run_1f &  rng_rd_ecc_2f}} & rng_wr_tid_2f[2:0]    ) |  // ASI
  ({3{~mbist_run_1f & ~rng_rd_ecc_2f}} & dec_fgu_tid_d[2:0]    ) ;  // functional

assign  fac_frf_r1_addr_d[4:0] =
  ({5{ mbist_run_1f                 }} & fac_mbist_addr_1f[4:0]) |  // MBIST
  ({5{~mbist_run_1f &  rng_rd_ecc_2f}} & rng_data_2f_b7_0[7:3] ) |  // ASI
  ({5{~mbist_run_1f & ~rng_rd_ecc_2f}} & dec_frf_r1_addr_d[4:0]) ;  // functional

assign  fac_frf_r1_vld_d =
  (    mbist_run_1f                    & mbist_frf_read_en_1f  ) |  // MBIST
  (   ~mbist_run_1f &  rng_rd_ecc_2f                           ) |  // ASI
  (   ~mbist_run_1f & ~rng_rd_ecc_2f   & dec_frf_r1_vld_d      ) ;  // functional

// 0in custom -fire (rng_rd_ecc_2f & (dec_frf_r1_vld_d | dec_frf_r2_vld_d) & (dec_fgu_decode_d | dec_frf_store_d | (fgx_pdist_e & dec_fgu_valid_e))) -message "FRF_ECC ASI collision with FPop"


// ----------------------------------------------------------------------------
//                               E stage
// ----------------------------------------------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_10 e_00  (
  .scan_in(e_00_scanin),
  .scan_out(e_00_scanout),
  .l1clk(l1clk),
  .din ({mbi_run,      spc_core_running_status[7:0],    lsu_fgu_pmen  }),  // requires free running clk
  .dout({mbist_run_1f,     core_running_status_1f[7:0],     fgu_pmen_e}),
  .siclk(siclk),
  .soclk(soclk)  // requires free running clk
  );

fgu_fac_ctl_msff_ctl_macro__width_37 e_01  (
  .scan_in(e_01_scanin),
  .scan_out(e_01_scanout),
  .l1clk(l1clk_pm2),
  .din ({dec_fgu_op3_d[5:0],      // requires free running clk or dec_fgu_decode_d en
         dec_fgu_opf_d[7:0],      // requires free running clk or dec_fgu_decode_d en
         dec_frf_r1_vld_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_r2_vld_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_r1_32b_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_r2_32b_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_r1_odd32b_d,     // requires free running clk or dec_fgu_decode_d en
         dec_frf_r2_odd32b_d,     // requires free running clk or dec_fgu_decode_d en
         dec_frf_store_d,         // requires free running clk or dec_fgu_decode_d en
         dec_fsr_store_d,         // requires free running clk or dec_fgu_decode_d en
         dec_irf_w_addr_d[4:0],   // requires free running clk or dec_fgu_decode_d en
         dec_spu_grant_d,         // requires free running clk or dec_fgu_decode_d en
         spu_fgu_fpy_ctl_d[6:0],  // requires free running clk or dec_fgu_decode_d en
         dec_fgu_decode_d,        // requires free running clk or dec_fgu_decode_d en
         lsu_asi_clken}),         // requires free running clk
  .dout({        op3_e[5:0],
                 opf_e[7:0],
                 r1_vld_e,
                 r2_vld_e,
                 r1_32b_e,
                 r2_32b_e,
                 r1_odd32b_e,
                 r2_odd32b_e,
             frf_store_e,
             fsr_store_e,
             irf_w_addr_e[4:0],
             spu_grant_e,
             spu_fpy_ctl_e[6:0],
                 fgu_decode_e,
         global_asi_clken}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_17 e_02  (
  .scan_in(e_02_scanin),
  .scan_out(e_02_scanout),
  .l1clk(l1clk_pm2),
  .din ({dec_frf_w_vld_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_w_addr_d[4:0],  // requires free running clk or dec_fgu_decode_d en
         dec_frf_w_32b_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_w_odd32b_d,     // requires free running clk or dec_fgu_decode_d en
         dec_fgu_tid_d[2:0],     // requires free running clk or dec_fgu_decode_d en
         dec_frf_r1_addr_d[4:0], // requires free running clk or dec_fgu_decode_d en
         dec_exu_src_vld_d}),    // requires free running clk or dec_fgu_decode_d en
  .dout({        w1_vld_e,
                 w1_addr_e[4:0],
                 w1_32b_e,
                 w1_odd32b_e,
         fac_tid_e[2:0],
         fac_frf_r1_addr_e[4:0],
             exu_w_vld_e}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_9 e_03  (
  .scan_in(e_03_scanin),
  .scan_out(e_03_scanout),
  .l1clk(l1clk_pm1),
  .din ({mbi_frf_read_en,      mbi_addr[7:0]         }),
  .dout({mbist_frf_read_en_1f, fac_mbist_addr_1f[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign i[24:19] = op3_e[5:0];
assign i[12:5] = opf_e[7:0];

// ------------------------------------
// Begin auto/program generated code
// ------------------------------------

assign aman_fmt_sel_e[4] = (!i[12]&!i[11]&!i[10]) | (i[22]) | (i[19]&!i[9]) | (
    i[20]) | (!i[23]);

assign aman_fmt_sel_e[3] = (!i[22]&i[20]&!i[11]&i[9]&!i[7]&!i[6]) | (i[23]&!i[22]
    &!i[12]&!i[11]&!i[10]&i[5]) | (!i[22]&i[19]&!i[9]&i[5]) | (!i[22]
    &i[20]&i[11]&i[10]&i[5]) | (!i[22]&i[20]&!i[8]&i[7]&!i[6]&i[5]) | (
    !i[22]&i[20]&i[11]&i[6]&i[5]) | (!i[22]&i[20]&!i[12]&!i[8]&!i[7]&i[5]);

assign aman_fmt_sel_e[2] = (!i[22]&i[19]&i[9]&i[5]) | (i[23]&!i[22]&!i[20]&!i[19]
    &!i[12]&i[11]&i[5]);

assign aman_fmt_sel_e[1] = (!i[22]&i[19]&i[9]&i[5]) | (i[23]&!i[22]&!i[20]&!i[19]
    &!i[12]&i[11]&i[5]);

assign aman_fmt_sel_e[0] = (!i[22]&i[19]&i[9]&!i[5]) | (i[23]&!i[22]&!i[20]
    &!i[19]&!i[12]&i[11]&!i[5]);

// assign bman_fmt_sel_e[4] = (!i[6]&!i[5]) | (!i[12]&!i[11]&!i[10]) | (i[22]) | (
//     i[19]&!i[9]) | (i[20]) | (!i[23]);

assign bman_fmt_sel_e[3] = (!i[22]&i[20]&!i[8]&!i[7]&i[6]&i[5]) | (i[23]&!i[22]
    &i[12]&i[11]&!i[6]&!i[5]) | (!i[22]&i[20]&!i[8]&i[7]&!i[6]&i[5]) | (
    !i[22]&i[20]&!i[11]&i[9]&i[8]&!i[7]&!i[6]) | (i[23]&!i[22]&!i[12]
    &!i[11]&!i[10]&i[5]) | (!i[22]&i[19]&!i[9]&i[5]) | (!i[22]&i[20]
    &i[11]&i[5]);

assign bman_fmt_sel_e[2] = (!i[22]&i[19]&i[9]&i[5]) | (i[23]&!i[22]&!i[20]&!i[19]
    &i[12]&i[5]) | (i[23]&!i[22]&!i[20]&i[10]&!i[7]&i[5]) | (i[23]&!i[22]
    &!i[20]&!i[19]&i[11]&i[5]);

assign bman_fmt_sel_e[1] = (!i[22]&i[19]&i[9]&i[5]) | (i[23]&!i[22]&!i[20]&!i[19]
    &i[12]&i[5]) | (i[23]&!i[22]&!i[20]&i[10]&!i[7]&i[5]) | (i[23]&!i[22]
    &!i[20]&!i[19]&i[11]&i[5]);

assign bman_fmt_sel_e[0] = (!i[22]&i[19]&i[9]&!i[5]) | (i[23]&!i[22]&!i[20]
    &i[10]&!i[7]&!i[5]) | (i[23]&!i[22]&!i[19]&i[12]&i[6]) | (i[23]&!i[22]
    &!i[20]&!i[19]&i[11]&i[6]);

assign aexp_fmt_sel_e[6] = (!i[6]);

assign aexp_fmt_sel_e[5] = (!i[11]&i[6]);

assign aexp_fmt_sel_e[4] = (!i[11]&i[5]);

assign aexp_fmt_sel_e[3] = (!i[12]);

assign aexp_fmt_sel_e[2] = (!i[12]&i[5]);

assign aexp_fmt_sel_e[1] = (!i[12]&i[5]);

assign aexp_fmt_sel_e[0] = (i[12]&i[7]&i[6]) | (i[12]&i[8]&i[5]) | (i[22]) | (
    i[19]&!i[9]) | (i[20]) | (!i[12]&!i[11]) | (!i[23]);

assign bexp_fmt_sel_e[2] = (i[5]);

assign bexp_fmt_sel_e[1] = (i[5]);

assign bexp_fmt_sel_e[0] = (!i[6]&!i[5]) | (!i[12]&!i[11]&!i[10]) | (i[22]) | (
    i[19]&!i[9]) | (i[20]) | (!i[23]);

assign fpx_itype_e[2] = (!i[22]&i[19]&i[9]) | (i[23]&i[20]&!i[11]&i[9]&!i[7]
    &!i[6]) | (i[23]&i[20]&!i[11]&i[9]&!i[8]) | (i[23]&!i[22]&!i[20]
    &!i[12]&i[11]&i[8]) | (!i[23]&i[19]) | (i[23]&!i[22]&!i[19]&!i[11]
    &i[10]&!i[9]) | (!i[24]);

assign fpx_itype_e[1] = (i[23]&!i[22]&!i[20]&!i[11]&i[10]&!i[7]) | (i[23]&!i[22]
    &i[12]&!i[6]&!i[5]) | (i[23]&!i[22]&!i[20]&!i[19]&i[12]&!i[8]&!i[7]) | (
    !i[23]&i[21]&i[19]) | (i[23]&!i[22]&!i[20]&i[8]&i[7]) | (!i[24]&i[21]);

assign fpx_itype_e[0] = (i[23]&!i[22]&!i[19]&i[12]&i[7]) | (!i[22]&i[20]&!i[11]
    &i[9]&!i[7]&!i[6]) | (i[23]&!i[22]&i[12]&!i[6]&!i[5]) | (!i[22]&i[20]
    &!i[11]&i[9]&!i[8]) | (i[23]&!i[22]&!i[20]&i[10]&!i[7]) | (i[23]
    &!i[22]&!i[20]&i[11]&i[8]&!i[7]) | (!i[21]);

assign fpx_dtype_e[2] = (!i[20]&!i[11]&!i[8]&!i[7]) | (!i[22]&i[10]&i[9]) | (
    !i[23]&!i[20]) | (i[22]&!i[20]) | (!i[21]);

assign fpx_dtype_e[1] = (i[23]&!i[22]&!i[19]&!i[10]&i[9]) | (i[22]&i[21]&i[20]) | (
    i[21]&i[20]&!i[9]);

assign fpx_dtype_e[0] = (!i[22]&i[20]&!i[9]&i[7]) | (i[23]&!i[22]&i[12]&i[11]
    &!i[7]) | (i[23]&!i[22]&!i[12]&!i[10]&i[6]) | (i[23]&!i[22]&!i[20]
    &i[8]&!i[5]) | (i[22]&i[21]&i[20]) | (i[23]&!i[22]&i[11]&i[10]);

assign fpx_stype_e[1] = (!i[6]&!i[5]);

assign fpx_stype_e[0] = (!i[11]&!i[5]) | (i[6]);

assign fpx_sign_instr_e = (i[23]&!i[22]&!i[19]&!i[12]&!i[10]&i[7]);

assign fpx_rnd_trunc_e = (i[12]&!i[8]&!i[7]) | (!i[12]&!i[11]&!i[10]) | (i[22]) | (
    i[19]) | (i[20]) | (!i[23]);

assign fpx_mulscc_e = (!i[23]&!i[22]);

assign fpx_saverestore_e = (i[23]&i[22]&!i[20]);

assign fpx_int_cc_vld_e = (!i[23]&!i[22]) | (!i[24]&i[23]);

assign fpx_fmul8x16_e = (!i[22]&i[20]&!i[11]&i[9]&!i[8]&!i[7]&!i[6]);

assign fpx_fmul8x16au_e = (!i[22]&i[20]&!i[11]&!i[8]&!i[7]&i[6]&i[5]);

assign fpx_fmul8x16al_e = (!i[22]&i[20]&!i[11]&i[9]&!i[8]&i[7]&!i[6]);

assign fpx_fmul8sux16_e = (!i[22]&i[20]&!i[11]&i[9]&!i[8]&!i[5]);

assign fpx_fmul8ulx16_e = (!i[22]&i[20]&!i[11]&i[7]&i[6]&i[5]);

assign fpx_fmuld8sux16_e = (!i[22]&i[20]&!i[11]&i[9]&!i[6]&!i[5]);

assign fpx_fmuld8ulx16_e = (!i[22]&i[20]&!i[11]&i[8]&!i[7]&!i[6]&i[5]);

assign fpx_nv_vld_e = (!i[22]&i[19]&i[9]) | (i[23]&!i[22]&!i[20]&i[10]&!i[7]) | (
    i[23]&!i[22]&!i[20]&!i[19]&i[11]&i[6]) | (i[23]&!i[22]&!i[20]&!i[19]
    &i[11]&i[5]) | (i[23]&!i[22]&!i[20]&!i[19]&i[12]&!i[8]&!i[7]);

assign fpx_of_vld_e = (i[23]&!i[22]&!i[20]&!i[19]&!i[12]&i[11]&!i[10]) | (i[23]
    &!i[22]&!i[20]&!i[19]&i[11]&!i[9]&i[6]);

assign fpx_uf_vld_e = (i[23]&!i[22]&!i[20]&!i[19]&!i[12]&i[11]&!i[10]) | (i[23]
    &!i[22]&!i[20]&!i[19]&i[11]&!i[9]&i[6]);

assign fpx_dz_vld_e = (i[23]&!i[22]&!i[20]&i[8]&i[7]);

assign fpx_nx_vld_e = (i[23]&!i[22]&i[12]&i[8]&i[5]) | (i[23]&!i[22]&!i[20]
    &i[10]&!i[7]) | (i[23]&!i[22]&!i[20]&!i[19]&i[12]&!i[11]) | (i[23]
    &!i[22]&!i[20]&!i[19]&i[11]&!i[8]) | (i[23]&!i[22]&!i[20]&!i[12]
    &i[11]&i[8]);

assign fpx_unfin_vld_e = (i[23]&!i[22]&!i[20]&i[10]&!i[7]) | (i[23]&!i[22]&!i[20]
    &!i[19]&i[11]&i[6]) | (i[23]&!i[22]&!i[20]&!i[19]&i[12]&!i[8]&!i[7]) | (
    i[23]&!i[22]&!i[20]&!i[19]&i[11]&i[5]);

assign fgx_mvcond_e = (!i[22]&i[19]&!i[9]);

assign fgx_mvucond_e = (i[23]&!i[22]&!i[19]&!i[12]&!i[11]&!i[10]&!i[8]&!i[7]);

assign fgx_abs_e = (i[23]&!i[22]&!i[12]&!i[11]&!i[10]&i[8]);

assign fgx_neg_e = (i[23]&!i[22]&!i[12]&!i[11]&!i[10]&i[7]);

assign fgx_logical_e = (!i[22]&i[20]&i[11]&i[10]);

assign fgx_expand_e = (!i[22]&i[20]&!i[10]&i[8]&!i[6]&i[5]);

assign fgx_merge_e = (!i[22]&i[20]&!i[10]&i[8]&i[6]);

assign fgx_align_e = (!i[22]&i[20]&!i[10]&i[8]&!i[7]&!i[5]);

assign fgx_shuffle_e = (!i[22]&i[20]&!i[10]&i[8]&i[7]&!i[5]);

assign fgx_pack16_e = (!i[22]&i[20]&!i[11]&i[8]&i[6]&i[5]);

assign fgx_pack32_e = (!i[22]&i[20]&!i[11]&i[9]&!i[7]&i[6]&!i[5]);

assign fgx_packfix_e = (!i[22]&i[20]&!i[11]&i[8]&i[7]&i[5]);

assign fgx_pdist_e = (!i[22]&i[20]&!i[11]&i[9]&i[8]&i[7]&!i[5]);

assign fgx_popc_e = (i[24]&i[22]&i[20]);

assign fgx_siam_e = (!i[22]&i[20]&i[12]);

assign fpx_itype_mul_e = (!i[22]&i[20]&!i[11]&i[9]&!i[7]&!i[6]) | (i[23]&!i[22]
    &!i[20]&!i[12]&i[11]&i[8]&!i[7]) | (!i[22]&i[20]&!i[11]&i[9]&!i[8]) | (
    !i[21]);

assign fpx_itype_div_e = (i[23]&!i[22]&!i[20]&!i[11]&i[10]&!i[7]) | (!i[23]
    &i[21]&i[19]) | (i[23]&!i[22]&!i[20]&i[8]&i[7]) | (!i[24]&i[21]);

assign fgx_instr_e = (i[24]&i[22]&i[20]) | (!i[22]&i[20]&i[9]&i[8]&i[7]) | (
    !i[22]&i[20]&i[9]&i[8]&i[6]) | (i[23]&!i[22]&!i[12]&!i[11]&!i[10]) | (
    !i[22]&i[20]&i[11]&i[10]) | (!i[22]&i[20]&!i[10]&!i[9]) | (!i[22]
    &i[19]&!i[9]);

// ------------------------------------
// End auto/program generated code
// ------------------------------------

// For single source (or no source) fgu ops that read frf
// ensure that unneeded frf read port isn't enabled by DEC
// Note:
// dec_spu_grant_d, dec_exu_src_vld_d have no frf source
// dec_frf_store_d, dec_fsr_store_d   have rs2 only
//
// rs1 only: FSRC1{s}, FNOT1{s}
// rs2 only: FABS(s,d), FiTO(s,d), FMOV(s,d), FMOV(s,d)cc, FMOV(s,d)r, FNEG(s,d), FSQRT(s,d), F(s,d)TOi,
//           F(s,d)TO(d,s), F(s,d)TOx, FxTO(s,d), FSRC2{s}, FNOT2{s}, FEXPAND, FPACK16, FPACKFIX, PDIST(beat2)
// no frf source: FZERO{s}, FONE{s}, SIAM
//
// 0in custom -fire ( dec_fgu_valid_e & r2_vld_e & ((fgx_logical_e & (opf_e[7:1]==7'b0111010)) | (fgx_logical_e & (opf_e[7:1]==7'b0110101)) )) -message "Invalid FRF rs2 read enable"
//
// 0in custom -fire ( dec_fgu_valid_e & r1_vld_e & (fgx_abs_e | fgx_neg_e | fgx_mvcond_e | fgx_mvucond_e | (fpx_itype_e[2:0]==3'b001) | (fpx_itype_e[2:0]==3'b010) | (fpx_itype_e[2:0]==3'b011) | (fpx_itype_e[2:0]==3'b111) | fgx_expand_e | fgx_pack16_e | fgx_packfix_e | (fgx_logical_e & (opf_e[7:1]==7'b0111100)) | (fgx_logical_e & (opf_e[7:1]==7'b0110011)) )) -message "Invalid FRF rs1 read enable"
//
// 0in custom -fire ($0in_delay(fac_fgx_pdist_fx1,1) & dec_valid_fx2 & $0in_delay(r1_vld_e,1)) -message "Invalid FRF rs1 read enable during PDIST 2nd beat"
//
// 0in custom -fire ( dec_fgu_valid_e & (r1_vld_e | r2_vld_e) & ( fgx_siam_e | (fgx_logical_e & (opf_e[7:1]==7'b0110000)) | (fgx_logical_e & (opf_e[7:1]==7'b0111111)) )) -message "Invalid FRF rs1 or rs2 read enable"
//
// 0in custom -fire (exu_w_vld_e & dec_fgu_valid_e & (r1_vld_e | r2_vld_e)) -message "Invalid FRF read enable during EXU op"
//
// 0in custom -fire (spu_grant_e & (r1_vld_e | r2_vld_e)) -message "Invalid FRF read enable during SPU op"

assign  fac_exu_src_e   = exu_w_vld_e & ~mbist_run_1f;

assign  q_fgx_pdist_e = fgx_pdist_e & fgu_decode_e;  // pdist 2nd beat has fgu_decode_e=1'b0

assign  fst_fmt_sel_e[0] = frf_store_e &  r2_odd32b_e & fgu_decode_e;  // pwr mgmt: aomux free zeros
assign  fst_fmt_sel_e[1] = frf_store_e & ~r2_odd32b_e & fgu_decode_e;  // pwr mgmt: aomux free zeros
assign  fst_fmt_sel_e[2] = fsr_store_e & ~r2_32b_e    & fgu_decode_e;  // pwr mgmt: aomux free zeros
assign  fst_fmt_sel_e[3] = fsr_store_e &  r2_32b_e    & fgu_decode_e;  // pwr mgmt: aomux free zeros

// odd address and store handling equations
// these equations use predecode signals to qualify the auto/program generated format selects

assign  q_aman_fmt_sel_e[1] = aman_fmt_sel_e[1] &  r1_odd32b_e;
assign  q_aman_fmt_sel_e[2] = aman_fmt_sel_e[2] & ~r1_odd32b_e;
assign  q_aman_fmt_sel_e[3] = aman_fmt_sel_e[3] &  r1_odd32b_e;
assign  q_aman_fmt_sel_e[4] = aman_fmt_sel_e[4] & ~r1_odd32b_e;

assign  q_bman_fmt_sel_e[0] =
   fgu_decode_e &  // pdist 2nd beat has fgu_decode_e=1'b0
   bman_fmt_sel_e[0];

assign  q_bman_fmt_sel_e[1] =
   fgu_decode_e &  // pdist 2nd beat has fgu_decode_e=1'b0
   bman_fmt_sel_e[1] &  r2_odd32b_e;

assign  q_bman_fmt_sel_e[2] =
   fgu_decode_e &  // pdist 2nd beat has fgu_decode_e=1'b0
   bman_fmt_sel_e[2] & ~r2_odd32b_e;

assign  q_bman_fmt_sel_e[3] =
   fgu_decode_e &  // pdist 2nd beat has fgu_decode_e=1'b0
   bman_fmt_sel_e[3] &  r2_odd32b_e;

assign  fac_aman_fmt_sel_e[4:0] = {q_aman_fmt_sel_e[4:1], aman_fmt_sel_e[0]};
assign  fac_bman_fmt_sel_e[3:0] =  q_bman_fmt_sel_e[3:0];
assign  fac_bman_fmt_sel_e[4]   = ~(|fac_bman_fmt_sel_e[3:0]);

assign  q_aexp_fmt_sel_e[1] = aexp_fmt_sel_e[1] & r1_odd32b_e;
assign  q_bexp_fmt_sel_e[1] = bexp_fmt_sel_e[1] & r2_odd32b_e;

assign    aexp_fmt_sel_e[7] = (fpx_itype_e[2:0] == 3'b001);        // FdTOs

assign  q_aexp_fmt_sel_e[8] =
  aexp_fmt_sel_e[1] & r1_odd32b_e & (opf_e[6:5] == 2'b11);         // FsMULd

assign    aexp_fmt_sel_e[9] =
  aexp_fmt_sel_e[2]               & (opf_e[6:5] == 2'b11);         // FsMULd

assign  fac_aexp_fmt_sel_e[9:0] = 
  {  aexp_fmt_sel_e[9],
   q_aexp_fmt_sel_e[8],
     aexp_fmt_sel_e[7:2],
   q_aexp_fmt_sel_e[1],
     aexp_fmt_sel_e[0]   };

assign  q_bexp_fmt_sel_e[3] =
  bexp_fmt_sel_e[1] & r2_odd32b_e & (fpx_itype_e[2:0] == 3'b110);  // FDIV

assign    bexp_fmt_sel_e[4] =
  bexp_fmt_sel_e[2]               & (fpx_itype_e[2:0] == 3'b110);  // FDIV

assign    bexp_fmt_sel_e[5] =       (fpx_itype_e[2:0] == 3'b110);  // FDIV

assign    bexp_fmt_sel_e[6] =
  bexp_fmt_sel_e[1] & r2_odd32b_e & (opf_e[6:5] == 2'b11);         // FsMULd

assign    bexp_fmt_sel_e[7] =
  bexp_fmt_sel_e[2]               & (opf_e[6:5] == 2'b11);         // FsMULd

assign  fac_bexp_fmt_sel_e[7:0] = 
  {  bexp_fmt_sel_e[7:4],
   q_bexp_fmt_sel_e[3],
     bexp_fmt_sel_e[2],
   q_bexp_fmt_sel_e[1],
     bexp_fmt_sel_e[0]   };

assign  fpx_sp_dest_e =
  (fpx_dtype_e[2:0] == 3'b000) |  // sp
  (fpx_dtype_e[2:0] == 3'b011) ;  // 32-bit

assign  q_w1_vld_e[0] = w1_vld_e & (~w1_32b_e | (w1_32b_e &  w1_odd32b_e));
assign  q_w1_vld_e[1] = w1_vld_e & (~w1_32b_e | (w1_32b_e & ~w1_odd32b_e));

// for FCMP: w1_addr_e[4]=cc[0], w1_addr_e[0]=cc[1]
assign  cc_target_e[1:0] = {w1_addr_e[0], w1_addr_e[4]};

// must later clear fcc_vld if (nv & TEM) | flush

assign  pre_fcc_vld_e[3] =
  dec_fgu_valid_e &
  (cc_target_e[1:0] == 2'b11)  &
  (fpx_itype_e[2:0] == 3'b100) & (fpx_dtype_e[2:1] == 2'b00);          // FCMP,FCMPE

assign  pre_fcc_vld_e[2] =
  dec_fgu_valid_e &
  (cc_target_e[1:0] == 2'b10)  &
  (fpx_itype_e[2:0] == 3'b100) & (fpx_dtype_e[2:1] == 2'b00);          // FCMP,FCMPE

assign  pre_fcc_vld_e[1] =
  dec_fgu_valid_e &
  (cc_target_e[1:0] == 2'b01)  &
  (fpx_itype_e[2:0] == 3'b100) & (fpx_dtype_e[2:1] == 2'b00);          // FCMP,FCMPE

assign  pre_fcc_vld_e[0] =
  dec_fgu_valid_e &
  (cc_target_e[1:0] == 2'b00)  & 
  (fpx_itype_e[2:0] == 3'b100) & (fpx_dtype_e[2:1] == 2'b00);          // FCMP,FCMPE

assign  i_fsr_w2_vld_fb[0] =                                           // load FSR 32b
  lsu_fgu_fsr_load_b &  lsu_fgu_fld_32b_b;

assign  i_fsr_w2_vld_fb[1] =                                           // load FSR 64b
  lsu_fgu_fsr_load_b & ~lsu_fgu_fld_32b_b;

assign  i_fsr_w2_vld_fb[2] =
  div_finish_fltd_fb | div_finish_flts_fb;                             // div/sqrt, load FSR doesn't update ftt

// 0in custom -fire ((lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & div_engine_busy_e & (lsu_fgu_fld_tid_b[2:0]==div_tid_in_e[2:0])),1))) | (lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & (div_finish_fltd_fb | div_finish_flts_fb) & (lsu_fgu_fld_tid_b[2:0]==fac_fpd_tid_fb[2:0])),1))) | (lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & dec_fgu_valid_e & (lsu_fgu_fld_tid_b[2:0]==fac_tid_e[2:0])),1))) | (lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & fac_dec_valid_fx1 & (lsu_fgu_fld_tid_b[2:0]==tid_fx1[2:0])),1))) | (lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & dec_valid_fx2 & (lsu_fgu_fld_tid_b[2:0]==tid_fx2[2:0])),1))) | (lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & dec_valid_fx3 & (lsu_fgu_fld_tid_b[2:0]==tid_fx3[2:0])),1)))) -message "LDFSR collision with FPop"

assign  fsr_w1_qvld_fb =  // other FPop w1 or fcmp with trap, not unfin
  ~fpc_fpx_unfin_fb &
  (fsr_w1_vld_fb[0] | (pre_fcc_vld_fb & ~(|fcc_vld_fb[3:0])));

assign  fsr_w2_qvld_fb =
  ~fpc_fpd_unfin_fb &
   i_fsr_w2_vld_fb[2];

// ----------------
// FSR tid0 selects
// ----------------

assign  fsr0_sel_fb[5] =
      i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd0);

assign  fsr0_sel_fb[4] =    // select w1 {ftt,aexc,cexc}, not fpd {ftt,aexc,cexc}
  (( |fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd0);

assign  fsr0_sel_fb[3] =    // enable flop
  (   i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd0)) |
  (((|fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd0)) ;

assign  fsr0_sel_fb[2:0] =
  ({3{(fsr_w1_vld_fb[1] & (fac_w1_tid_fb[2:0]     == 3'd0))}} & 3'd2) |  // ST(X)FSR
  ({3{(fpc_fpx_unfin_fb & (fac_w1_tid_fb[2:0]     == 3'd0))}} & 3'd2) |  // unfin w1
  ({3{(fpc_fpd_unfin_fb & (fac_fpd_tid_fb[2:0]    == 3'd0))}} & 3'd2) |  // unfin FDIV/FSQRT
  ({3{(fcc_vld_fb[0]    & (fac_w1_tid_fb[2:0]     == 3'd0))}} & 3'd3) |  // FCMP(E) fcc0
  ({3{(fcc_vld_fb[1]    & (fac_w1_tid_fb[2:0]     == 3'd0))}} & 3'd4) |  // FCMP(E) fcc1
  ({3{(fcc_vld_fb[2]    & (fac_w1_tid_fb[2:0]     == 3'd0))}} & 3'd5) |  // FCMP(E) fcc2
  ({3{(fcc_vld_fb[3]    & (fac_w1_tid_fb[2:0]     == 3'd0))}} & 3'd6) |  // FCMP(E) fcc3
  ({3{(fsr_w1_qvld_fb   & (fac_w1_tid_fb[2:0]     == 3'd0))}} & 3'd7) |  // other FPop w1
  ({3{(fsr_w2_qvld_fb   & (fac_fpd_tid_fb[2:0]    == 3'd0))}} & 3'd7) ;  // other FPop FDIV/FSQRT

// ----------------
// FSR tid1 selects
// ----------------

assign  fsr1_sel_fb[5] =
      i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd1);

assign  fsr1_sel_fb[4] =    // select w1 {ftt,aexc,cexc}, not fpd {ftt,aexc,cexc}
  (( |fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd1);

assign  fsr1_sel_fb[3] =    // enable flop
  (   i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd1)) |
  (((|fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd1)) ;

assign  fsr1_sel_fb[2:0] =
  ({3{(fsr_w1_vld_fb[1] & (fac_w1_tid_fb[2:0]     == 3'd1))}} & 3'd2) |  // ST(X)FSR
  ({3{(fpc_fpx_unfin_fb & (fac_w1_tid_fb[2:0]     == 3'd1))}} & 3'd2) |  // unfin w1
  ({3{(fpc_fpd_unfin_fb & (fac_fpd_tid_fb[2:0]    == 3'd1))}} & 3'd2) |  // unfin FDIV/FSQRT
  ({3{(fcc_vld_fb[0]    & (fac_w1_tid_fb[2:0]     == 3'd1))}} & 3'd3) |  // FCMP(E) fcc0
  ({3{(fcc_vld_fb[1]    & (fac_w1_tid_fb[2:0]     == 3'd1))}} & 3'd4) |  // FCMP(E) fcc1
  ({3{(fcc_vld_fb[2]    & (fac_w1_tid_fb[2:0]     == 3'd1))}} & 3'd5) |  // FCMP(E) fcc2
  ({3{(fcc_vld_fb[3]    & (fac_w1_tid_fb[2:0]     == 3'd1))}} & 3'd6) |  // FCMP(E) fcc3
  ({3{(fsr_w1_qvld_fb   & (fac_w1_tid_fb[2:0]     == 3'd1))}} & 3'd7) |  // other FPop w1
  ({3{(fsr_w2_qvld_fb   & (fac_fpd_tid_fb[2:0]    == 3'd1))}} & 3'd7) ;  // other FPop FDIV/FSQRT

// ----------------
// FSR tid2 selects
// ----------------

assign  fsr2_sel_fb[5] =
      i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd2);

assign  fsr2_sel_fb[4] =    // select w1 {ftt,aexc,cexc}, not fpd {ftt,aexc,cexc}
  (( |fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd2);

assign  fsr2_sel_fb[3] =    // enable flop
  (   i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd2)) |
  (((|fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd2)) ;

assign  fsr2_sel_fb[2:0] =
  ({3{(fsr_w1_vld_fb[1] & (fac_w1_tid_fb[2:0]     == 3'd2))}} & 3'd2) |  // ST(X)FSR
  ({3{(fpc_fpx_unfin_fb & (fac_w1_tid_fb[2:0]     == 3'd2))}} & 3'd2) |  // unfin w1
  ({3{(fpc_fpd_unfin_fb & (fac_fpd_tid_fb[2:0]    == 3'd2))}} & 3'd2) |  // unfin FDIV/FSQRT
  ({3{(fcc_vld_fb[0]    & (fac_w1_tid_fb[2:0]     == 3'd2))}} & 3'd3) |  // FCMP(E) fcc0
  ({3{(fcc_vld_fb[1]    & (fac_w1_tid_fb[2:0]     == 3'd2))}} & 3'd4) |  // FCMP(E) fcc1
  ({3{(fcc_vld_fb[2]    & (fac_w1_tid_fb[2:0]     == 3'd2))}} & 3'd5) |  // FCMP(E) fcc2
  ({3{(fcc_vld_fb[3]    & (fac_w1_tid_fb[2:0]     == 3'd2))}} & 3'd6) |  // FCMP(E) fcc3
  ({3{(fsr_w1_qvld_fb   & (fac_w1_tid_fb[2:0]     == 3'd2))}} & 3'd7) |  // other FPop w1
  ({3{(fsr_w2_qvld_fb   & (fac_fpd_tid_fb[2:0]    == 3'd2))}} & 3'd7) ;  // other FPop FDIV/FSQRT

// ----------------
// FSR tid3 selects
// ----------------

assign  fsr3_sel_fb[5] =
      i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd3);

assign  fsr3_sel_fb[4] =    // select w1 {ftt,aexc,cexc}, not fpd {ftt,aexc,cexc}
  (( |fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd3);

assign  fsr3_sel_fb[3] =    // enable flop
  (   i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd3)) |
  (((|fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd3)) ;

assign  fsr3_sel_fb[2:0] =
  ({3{(fsr_w1_vld_fb[1] & (fac_w1_tid_fb[2:0]     == 3'd3))}} & 3'd2) |  // ST(X)FSR
  ({3{(fpc_fpx_unfin_fb & (fac_w1_tid_fb[2:0]     == 3'd3))}} & 3'd2) |  // unfin w1
  ({3{(fpc_fpd_unfin_fb & (fac_fpd_tid_fb[2:0]    == 3'd3))}} & 3'd2) |  // unfin FDIV/FSQRT
  ({3{(fcc_vld_fb[0]    & (fac_w1_tid_fb[2:0]     == 3'd3))}} & 3'd3) |  // FCMP(E) fcc0
  ({3{(fcc_vld_fb[1]    & (fac_w1_tid_fb[2:0]     == 3'd3))}} & 3'd4) |  // FCMP(E) fcc1
  ({3{(fcc_vld_fb[2]    & (fac_w1_tid_fb[2:0]     == 3'd3))}} & 3'd5) |  // FCMP(E) fcc2
  ({3{(fcc_vld_fb[3]    & (fac_w1_tid_fb[2:0]     == 3'd3))}} & 3'd6) |  // FCMP(E) fcc3
  ({3{(fsr_w1_qvld_fb   & (fac_w1_tid_fb[2:0]     == 3'd3))}} & 3'd7) |  // other FPop w1
  ({3{(fsr_w2_qvld_fb   & (fac_fpd_tid_fb[2:0]    == 3'd3))}} & 3'd7) ;  // other FPop FDIV/FSQRT

// ----------------
// FSR tid4 selects
// ----------------

assign  fsr4_sel_fb[5] =
      i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd4);

assign  fsr4_sel_fb[4] =    // select w1 {ftt,aexc,cexc}, not fpd {ftt,aexc,cexc}
  (( |fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd4);

assign  fsr4_sel_fb[3] =    // enable flop
  (   i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd4)) |
  (((|fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd4)) ;

assign  fsr4_sel_fb[2:0] =
  ({3{(fsr_w1_vld_fb[1] & (fac_w1_tid_fb[2:0]     == 3'd4))}} & 3'd2) |  // ST(X)FSR
  ({3{(fpc_fpx_unfin_fb & (fac_w1_tid_fb[2:0]     == 3'd4))}} & 3'd2) |  // unfin w1
  ({3{(fpc_fpd_unfin_fb & (fac_fpd_tid_fb[2:0]    == 3'd4))}} & 3'd2) |  // unfin FDIV/FSQRT
  ({3{(fcc_vld_fb[0]    & (fac_w1_tid_fb[2:0]     == 3'd4))}} & 3'd3) |  // FCMP(E) fcc0
  ({3{(fcc_vld_fb[1]    & (fac_w1_tid_fb[2:0]     == 3'd4))}} & 3'd4) |  // FCMP(E) fcc1
  ({3{(fcc_vld_fb[2]    & (fac_w1_tid_fb[2:0]     == 3'd4))}} & 3'd5) |  // FCMP(E) fcc2
  ({3{(fcc_vld_fb[3]    & (fac_w1_tid_fb[2:0]     == 3'd4))}} & 3'd6) |  // FCMP(E) fcc3
  ({3{(fsr_w1_qvld_fb   & (fac_w1_tid_fb[2:0]     == 3'd4))}} & 3'd7) |  // other FPop w1
  ({3{(fsr_w2_qvld_fb   & (fac_fpd_tid_fb[2:0]    == 3'd4))}} & 3'd7) ;  // other FPop FDIV/FSQRT

// ----------------
// FSR tid5 selects
// ----------------

assign  fsr5_sel_fb[5] =
      i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd5);

assign  fsr5_sel_fb[4] =    // select w1 {ftt,aexc,cexc}, not fpd {ftt,aexc,cexc}
  (( |fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd5);

assign  fsr5_sel_fb[3] =    // enable flop
  (   i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd5)) |
  (((|fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd5)) ;

assign  fsr5_sel_fb[2:0] =
  ({3{(fsr_w1_vld_fb[1] & (fac_w1_tid_fb[2:0]     == 3'd5))}} & 3'd2) |  // ST(X)FSR
  ({3{(fpc_fpx_unfin_fb & (fac_w1_tid_fb[2:0]     == 3'd5))}} & 3'd2) |  // unfin w1
  ({3{(fpc_fpd_unfin_fb & (fac_fpd_tid_fb[2:0]    == 3'd5))}} & 3'd2) |  // unfin FDIV/FSQRT
  ({3{(fcc_vld_fb[0]    & (fac_w1_tid_fb[2:0]     == 3'd5))}} & 3'd3) |  // FCMP(E) fcc0
  ({3{(fcc_vld_fb[1]    & (fac_w1_tid_fb[2:0]     == 3'd5))}} & 3'd4) |  // FCMP(E) fcc1
  ({3{(fcc_vld_fb[2]    & (fac_w1_tid_fb[2:0]     == 3'd5))}} & 3'd5) |  // FCMP(E) fcc2
  ({3{(fcc_vld_fb[3]    & (fac_w1_tid_fb[2:0]     == 3'd5))}} & 3'd6) |  // FCMP(E) fcc3
  ({3{(fsr_w1_qvld_fb   & (fac_w1_tid_fb[2:0]     == 3'd5))}} & 3'd7) |  // other FPop w1
  ({3{(fsr_w2_qvld_fb   & (fac_fpd_tid_fb[2:0]    == 3'd5))}} & 3'd7) ;  // other FPop FDIV/FSQRT

// ----------------
// FSR tid6 selects
// ----------------

assign  fsr6_sel_fb[5] =
      i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd6);

assign  fsr6_sel_fb[4] =    // select w1 {ftt,aexc,cexc}, not fpd {ftt,aexc,cexc}
  (( |fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd6);

assign  fsr6_sel_fb[3] =    // enable flop
  (   i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd6)) |
  (((|fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd6)) ;

assign  fsr6_sel_fb[2:0] =
  ({3{(fsr_w1_vld_fb[1] & (fac_w1_tid_fb[2:0]     == 3'd6))}} & 3'd2) |  // ST(X)FSR
  ({3{(fpc_fpx_unfin_fb & (fac_w1_tid_fb[2:0]     == 3'd6))}} & 3'd2) |  // unfin w1
  ({3{(fpc_fpd_unfin_fb & (fac_fpd_tid_fb[2:0]    == 3'd6))}} & 3'd2) |  // unfin FDIV/FSQRT
  ({3{(fcc_vld_fb[0]    & (fac_w1_tid_fb[2:0]     == 3'd6))}} & 3'd3) |  // FCMP(E) fcc0
  ({3{(fcc_vld_fb[1]    & (fac_w1_tid_fb[2:0]     == 3'd6))}} & 3'd4) |  // FCMP(E) fcc1
  ({3{(fcc_vld_fb[2]    & (fac_w1_tid_fb[2:0]     == 3'd6))}} & 3'd5) |  // FCMP(E) fcc2
  ({3{(fcc_vld_fb[3]    & (fac_w1_tid_fb[2:0]     == 3'd6))}} & 3'd6) |  // FCMP(E) fcc3
  ({3{(fsr_w1_qvld_fb   & (fac_w1_tid_fb[2:0]     == 3'd6))}} & 3'd7) |  // other FPop w1
  ({3{(fsr_w2_qvld_fb   & (fac_fpd_tid_fb[2:0]    == 3'd6))}} & 3'd7) ;  // other FPop FDIV/FSQRT

// ----------------
// FSR tid7 selects
// ----------------

assign  fsr7_sel_fb[5] =
      i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd7);

assign  fsr7_sel_fb[4] =    // select w1 {ftt,aexc,cexc}, not fpd {ftt,aexc,cexc}
  (( |fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd7);

assign  fsr7_sel_fb[3] =    // enable flop
  (   i_fsr_w2_vld_fb[2]                    & (fac_fpd_tid_fb[2:0]    == 3'd7)) |
  (((|fsr_w1_vld_fb[1:0]) | pre_fcc_vld_fb) & (fac_w1_tid_fb[2:0]     == 3'd7)) ;

assign  fsr7_sel_fb[2:0] =
  ({3{(fsr_w1_vld_fb[1] & (fac_w1_tid_fb[2:0]     == 3'd7))}} & 3'd2) |  // ST(X)FSR
  ({3{(fpc_fpx_unfin_fb & (fac_w1_tid_fb[2:0]     == 3'd7))}} & 3'd2) |  // unfin w1
  ({3{(fpc_fpd_unfin_fb & (fac_fpd_tid_fb[2:0]    == 3'd7))}} & 3'd2) |  // unfin FDIV/FSQRT
  ({3{(fcc_vld_fb[0]    & (fac_w1_tid_fb[2:0]     == 3'd7))}} & 3'd3) |  // FCMP(E) fcc0
  ({3{(fcc_vld_fb[1]    & (fac_w1_tid_fb[2:0]     == 3'd7))}} & 3'd4) |  // FCMP(E) fcc1
  ({3{(fcc_vld_fb[2]    & (fac_w1_tid_fb[2:0]     == 3'd7))}} & 3'd5) |  // FCMP(E) fcc2
  ({3{(fcc_vld_fb[3]    & (fac_w1_tid_fb[2:0]     == 3'd7))}} & 3'd6) |  // FCMP(E) fcc3
  ({3{(fsr_w1_qvld_fb   & (fac_w1_tid_fb[2:0]     == 3'd7))}} & 3'd7) |  // other FPop w1
  ({3{(fsr_w2_qvld_fb   & (fac_fpd_tid_fb[2:0]    == 3'd7))}} & 3'd7) ;  // other FPop FDIV/FSQRT

assign  q_r1_vld_e[0] = r1_vld_e & (~r1_32b_e | (r1_32b_e &  r1_odd32b_e));
assign  q_r1_vld_e[1] = r1_vld_e & (~r1_32b_e | (r1_32b_e & ~r1_odd32b_e));
assign  q_r2_vld_e[0] = r2_vld_e & (~r2_32b_e | (r2_32b_e &  r2_odd32b_e));
assign  q_r2_vld_e[1] = r2_vld_e & (~r2_32b_e | (r2_32b_e & ~r2_odd32b_e));

assign  fac_rs2_rotate_sel_e[0] =  // odd  FiTO(s,d)
  (fpx_itype_e[2:0] == 3'b011) & (fpx_stype_e[1:0] == 2'b10) &  r2_odd32b_e;

assign  fac_rs2_rotate_sel_e[1] =  // even FiTO(s,d)
  (fpx_itype_e[2:0] == 3'b011) & (fpx_stype_e[1:0] == 2'b10) & ~r2_odd32b_e;

assign  fac_rs2_rotate_sel_e[2] =  //      FiTO(s,d)
  (fpx_itype_e[2:0] == 3'b011) & (fpx_stype_e[1:0] == 2'b10);

assign  fac_rs2_rotate_sel_e[3] =  // odd
  ~fac_rs2_rotate_sel_e[2]                                   &  r2_odd32b_e;

assign  fac_rs2_rotate_sel_e[4] =  // even
  ~fac_rs2_rotate_sel_e[2]                                   & ~r2_odd32b_e;

assign  fac_i2f_sel_e[0] =         //      F(i,x)TO(s,d)
  (fpx_itype_e[2:0] == 3'b011);

assign  fac_i2f_sel_e[1] =         //     ~F(i,x)TO(s,d)
 ~(fpx_itype_e[2:0] == 3'b011);

// ------------------------------------
// Instructions which depend on appropriate steering
// of rs1/rs2 thru Mse/Mle:
//
// instr            desired behavior  default behavior
// ---------------------------------------------------
// F(i,x)TO(s,d)     rs2=Mse  (B<A)       ~(B<A) ??? <= rs1 is unknown
// F(s,d)TO(i,x)     rs2=Mse  (B<A)       ~(B<A) ??? <= rs1 is unknown
// MULScc            rs2=Mse  (B<A)       ~(B<A)
// SAVE              rs2=Mse  (B<A)       ~(B<A)
// RESTORE           rs2=Mse  (B<A)       ~(B<A)
// FPSUB{16,32}{s}   rs2=Mse  (B<A)       ~(B<A)
// F(s,d)TO(d,s)     rs2=Mle ~(B<A)       ~(B<A) ??? <= rs1 is unknown
// FADD(s,d)               src dependent             <= no action required
// FSUB(s,d)               src dependent             <= no action required
//
// These required for NaN steering only:
// FsMULd                  src dependent             <= no action required
// FMUL(s,d)               src dependent             <= no action required
// FDIV(s,d)               src dependent             <= no action required
// FSQRT(s,d)        rs2=Mle ~(B<A)       ~(B<A) ??? <= rs1 is unknown
//
// ------------------------------------

assign  force_swap_blta_e =
  (fpx_itype_e[2:0] == 3'b010) |                     // F(s,d)TO(i,x)
  (fpx_itype_e[2:0] == 3'b011) |                     // F(i,x)TO(s,d)
  (fpx_mulscc_e              ) |                     // MULScc
  (fpx_saverestore_e         ) |                     // SAVE or RESTORE
  ((fpx_dtype_e[2:1] == 2'b01) & fpx_sign_instr_e);  // FPSUB{16,32}{s}

assign  force_noswap_blta_e =
  (fpx_itype_e[2:0] == 3'b001) |                     // F(s,d)TO(d,s)
  (fpx_itype_e[2:0] == 3'b111) ;                     // FSQRT(s,d)

// ------------------------------------
// FPY control
// ------------------------------------

// spu_fgu_fpy_ctl_d[6:0]:
//
//            [0]     [1]             [2]             [3]             [4]     [5]                       [6]
//            ---     ------------    --------------  -----------     -----   -----------------------   --------------------
// if == 1    XOR     Add Accum       Write Accum     2*(rs1*rs2)     >> 64   write MA result flop      bypass result to rs1
// if == 0    Int     No Add Accum    No Write Accum    (rs1*rs2)     >> 0    no write MA result flop   no bypass result

assign  xr_mode_e    =  spu_grant_e & spu_fpy_ctl_e[0];

assign  rs1_sel_e[0] = ~spu_grant_e & (fpx_fmul8sux16_e | fpx_fmuld8sux16_e);
assign  rs1_sel_e[1] = ~spu_grant_e & (fpx_fmul8x16_e   | fpx_fmul8x16au_e | fpx_fmul8x16al_e);
assign  rs1_sel_e[2] = ~spu_grant_e & (fpx_fmul8ulx16_e | fpx_fmuld8ulx16_e);
assign  rs1_sel_e[3] =  spu_grant_e & spu_fpy_ctl_e[6];
assign  rs1_sel_e[4] =  spu_grant_e;

assign  rs2_sel_e[0] = ~spu_grant_e & fpx_fmul8x16au_e;
assign  rs2_sel_e[1] = ~spu_grant_e & fpx_fmul8x16al_e;

assign  rs2_sel_e[2] =  // all 8x16
  ~spu_grant_e & 
  (fpx_fmul8x16_e   | fpx_fmul8x16au_e | fpx_fmul8x16al_e  |
   fpx_fmul8sux16_e | fpx_fmul8ulx16_e | fpx_fmuld8sux16_e | fpx_fmuld8ulx16_e);

assign  rs2_sel_e[3] =  spu_grant_e;

assign  rnd_8x16_e[0] =
  ~spu_grant_e &
  (fpx_fmul8x16_e   | fpx_fmul8x16au_e | fpx_fmul8x16al_e  | fpx_fmul8sux16_e);

assign  rnd_8x16_e[1] = ~spu_grant_e & fpx_fmul8ulx16_e;

assign  result_sel_e[0] =
  ~spu_grant_e &
  (fpx_fmul8x16_e   | fpx_fmul8x16au_e | fpx_fmul8x16al_e  |
   fpx_fmul8sux16_e);

assign  result_sel_e[1] = ~spu_grant_e & fpx_fmul8ulx16_e;
assign  result_sel_e[2] = ~spu_grant_e & fpx_fmuld8sux16_e;
assign  result_sel_e[3] = ~spu_grant_e & fpx_fmuld8ulx16_e;
assign  result_sel_e[4] =  spu_grant_e & spu_fpy_ctl_e[0] & spu_fpy_ctl_e[1];  // XOR mult w/ ACCUM
assign  result_sel_e[5] = ~spu_grant_e & (fpx_dtype_e[2:1] == 2'b00);          // dp or sp float

// ------------------------------------
// FPD control
// ------------------------------------

assign  div_valid_e =   // start div engine
  (~div_engine_busy_fx1 &
   (fpx_itype_e[2:1] == 2'b11) & dec_fgu_valid_e) |  // DEC  issued div/sqrt
  (~div_engine_busy_fx1 & divq_occupied_fx1 &        // divq issued div/sqrt
   ~(pre_div_flush_fx3 & ~div_dec_issue_fx3)    ) ;  //        and divq not flushed

assign  divq_valid_e =  // load divq or start div engine from divq
  ( div_engine_busy_fx1 &
   (fpx_itype_e[2:1] == 2'b11) & dec_fgu_valid_e) |  // divq load
  (~div_engine_busy_fx1 & divq_occupied_fx1 &        // divq issued div/sqrt
   ~(pre_div_flush_fx3 & ~div_dec_issue_fx3)    ) ;  //        and divq not flushed

assign  div_engine_busy_e =
  ( div_valid_e                                 ) |  // set   (DEC/divq issued div/sqrt)
  ((~div_finish_early &                              // clear (if finish)
						     // clear (if flush)
    ~fac_div_flush_fx3 ) & div_engine_busy_fx1  ) ;

// 0in assert_timer -var div_engine_busy_e -max 50 -message "Divide engine busy > 50 cycles"; custom -fire ((dec_fgu_decode_d & div_engine_busy_e & (dec_fgu_tid_d[2:0]==div_tid_in_e[2:0])) | (dec_fgu_decode_d & (div_finish_fltd_fb | div_finish_flts_fb) & (dec_fgu_tid_d[2:0]==fac_fpd_tid_fb[2:0]))) -message "Divide engine collision with other FPop"

assign  div_dec_issue_e  =  div_valid_e & ~divq_valid_e;
assign  div_divq_issue_e =  div_valid_e &  divq_valid_e;
assign  div_divq_load_e  = ~div_valid_e &  divq_valid_e;
assign  div_hold_e       = ~div_dec_issue_e & ~div_divq_issue_e;

assign  divq_occupied_e =
  ( div_engine_busy_fx1 &
   (fpx_itype_e[2:1] == 2'b11) & dec_fgu_valid_e) |  // set   (divq load)
  ((~div_divq_issue_e &                              // clear (if divq issued div/sqrt)
                                                     // clear (if flush divq)
    ~(pre_div_flush_fx3 & ~div_dec_issue_fx3)) & divq_occupied_fx1);

// 0in custom -fire ((dec_fgu_decode_d & divq_occupied_e & (dec_fgu_tid_d[2:0]==divq_tid_in_e[2:0]))) -message "Divide queue collision with other FPop"

// ------------
// capture data for instr that is entering the div engine
// ------------

assign  div_tid_in_e[2:0] =
  ( {3{div_dec_issue_e }} & fac_tid_e[2:0]        ) |  // load from DEC  issue
  ( {3{div_divq_issue_e}} & divq_tid_fx1[2:0]     ) |  // load from divq issue
  ( {3{div_hold_e      }} & div_tid_fx1[2:0]      ) ;  // hold

assign  div_irf_addr_in_e[4:0] =
  ( {5{div_dec_issue_e }} & irf_w_addr_e[4:0]     ) |  // load from DEC  issue
  ( {5{div_divq_issue_e}} & divq_irf_addr_fx1[4:0]) |  // load from divq issue
  ( {5{div_hold_e      }} & div_irf_addr_fx1[4:0] ) ;  // hold

assign  div_cc_vld_in_e =
  (    div_dec_issue_e    & fpx_int_cc_vld_e      ) |  // load from DEC  issue
  (    div_divq_issue_e   & divq_cc_vld_fx1       ) |  // load from divq issue
  (    div_hold_e         & div_cc_vld_fx1        ) ;  // hold

assign  div_odd32b_in_e =
  (    div_dec_issue_e    & w1_odd32b_e           ) |  // load from DEC  issue
  (    div_divq_issue_e   & divq_odd32b_fx1       ) |  // load from divq issue
  (    div_hold_e         & div_odd32b_fx1        ) ;  // hold

assign  div_32b_in_e =
  (    div_dec_issue_e    & w1_32b_e              ) |  // load from DEC  issue
  (    div_divq_issue_e   & divq_32b_fx1          ) |  // load from divq issue
  (    div_hold_e         & div_32b_fx1           ) ;  // hold

assign  div_frf_addr_in_e[4:0] =
  ( {5{div_dec_issue_e }} & w1_addr_e[4:0]        ) |  // load from DEC  issue
  ( {5{div_divq_issue_e}} & divq_frf_addr_fx1[4:0]) |  // load from divq issue
  ( {5{div_hold_e      }} & div_frf_addr_fx1[4:0] ) ;  // hold

// ------------
// capture data for instr that is entering the div queue
// ------------

assign  divq_tid_in_e[2:0] =
  ( {3{ div_divq_load_e}} & fac_tid_e[2:0]        ) |  // load from DEC  issue
  ( {3{~div_divq_load_e}} & divq_tid_fx1[2:0]     ) ;  // hold

assign  divq_irf_addr_in_e[4:0] =
  ( {5{ div_divq_load_e}} & irf_w_addr_e[4:0]     ) |  // load from DEC  issue
  ( {5{~div_divq_load_e}} & divq_irf_addr_fx1[4:0]) ;  // hold

assign  divq_cc_vld_in_e =
  (     div_divq_load_e   & fpx_int_cc_vld_e      ) |  // load from DEC  issue
  (    ~div_divq_load_e   & divq_cc_vld_fx1       ) ;  // hold

assign  divq_odd32b_in_e =
  (     div_divq_load_e   & w1_odd32b_e           ) |  // load from DEC  issue
  (    ~div_divq_load_e   & divq_odd32b_fx1       ) ;  // hold

assign  divq_32b_in_e =
  (     div_divq_load_e   & w1_32b_e              ) |  // load from DEC  issue
  (    ~div_divq_load_e   & divq_32b_fx1          ) ;  // hold

assign  divq_frf_addr_in_e[4:0] =
  ( {5{ div_divq_load_e}} & w1_addr_e[4:0]        ) |  // load from DEC  issue
  ( {5{~div_divq_load_e}} & divq_frf_addr_fx1[4:0]) ;  // hold

// ------------
// FDC captures and holds these controls in the div queue as needed
// ------------

assign  div_control_e[4] = fac_tid_e[2];

assign  div_control_e[3] = (fpx_itype_e[2:0] == 3'b111);  // sqrt

assign  div_control_e[2] =
  (fpx_dtype_e[2:0] == 3'b100) |
  (fpx_dtype_e[2:0] == 3'b011) ;                          // idiv (32/64b dest)

assign  div_control_e[1] =
  (fpx_dtype_e[2:0] == 3'b001) |
  (fpx_dtype_e[2:0] == 3'b100) ;                          // DP/64b dest

assign  div_control_e[0] =
  ((fpx_dtype_e[2:0] == 3'b011) & op3_e[0]) |             // sdiv  (32b dest)
  ((fpx_dtype_e[2:0] == 3'b100) & op3_e[5]) ;             // sdivx (64b dest)


// ----------------------------------------------------------------------------
//                               FX1 stage
// ----------------------------------------------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_128 fx1_00  (
  .scan_in(fx1_00_scanin),
  .scan_out(fx1_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({opf_e[4:1],
         dec_fgu_valid_e,
         fpx_itype_e[2:0],
         fpx_dtype_e[2:0],
         fpx_stype_e[1:0],
         fpx_itype_mul_e,
         fpx_sign_instr_e,
         fpx_rnd_trunc_e,
         fpx_mulscc_e,
         fpx_saverestore_e,
         fpx_int_cc_vld_e,
         fpx_nv_vld_e,
         fpx_of_vld_e,
         fpx_uf_vld_e,
         fpx_dz_vld_e,
         fpx_nx_vld_e,
         fpx_unfin_vld_e,
         fgx_mvcond_e,
         fgx_mvucond_e,
         fgx_abs_e,
         fgx_neg_e,
         fgx_logical_e,
         fgx_expand_e,
         fgx_merge_e,
         fgx_align_e,
         fgx_shuffle_e,
         fgx_pack16_e,
         fgx_pack32_e,
         fgx_packfix_e,
         q_fgx_pdist_e,
         fgx_popc_e,
         fgx_siam_e,
         fpx_sp_dest_e,
         rs1_sel_e[4:0],
         rs2_sel_e[3:0],
         rnd_8x16_e[1:0],
         result_sel_e[5:0],
         exu_w_vld_e,
         irf_w_addr_e[4:0],
         q_r1_vld_e[1:0],
         q_r2_vld_e[1:0],
         spu_grant_e,
         div_valid_e,
         divq_valid_e,
         divq_occupied_e,
         div_control_e[4:0],
         div_tid_in_e[2:0],
         div_irf_addr_in_e[4:0],
         div_frf_addr_in_e[4:0],
         div_cc_vld_in_e,
         div_odd32b_in_e,
         div_32b_in_e,
         divq_tid_in_e[2:0],
         divq_irf_addr_in_e[4:0],
         divq_frf_addr_in_e[4:0],
         divq_cc_vld_in_e,
         divq_odd32b_in_e,
         divq_32b_in_e,
         div_engine_busy_e,
         div_dec_issue_e,
         div_divq_issue_e,
         force_swap_blta_e,
         force_noswap_blta_e,
         fsr_store_e,
         xr_mode_e,
         spu_fpy_ctl_e[5:0],
         frf_store_e,
             fst_fmt_sel_e[3:0],
         fgu_decode_e}),
  .dout({opf_fx1[4:1],
         fac_dec_valid_fx1,
         fac_fpx_itype_fx1[2:0],
         fac_fpx_dtype_fx1[2:0],
         fac_fpx_stype_fx1[1:0],
             itype_mul_fx1,
         fac_fpx_sign_instr_fx1,
         fac_fpx_rnd_trunc_fx1,
         fac_fpx_mulscc_fx1,
         fac_fpx_saverestore_fx1,
         fpx_int_cc_vld_fx1,
         fac_fpx_nv_vld_fx1,
         fac_fpx_of_vld_fx1,
         fac_fpx_uf_vld_fx1,
         fac_fpx_dz_vld_fx1,
         fac_fpx_nx_vld_fx1,
         fac_fpx_unfin_vld_fx1,
         fgx_mvcond_fx1,
         fgx_mvucond_fx1,
         fgx_abs_fx1,
         fgx_neg_fx1,
         fgx_logical_fx1,
         fgx_expand_fx1,
         fgx_merge_fx1,
         fgx_align_fx1,
         fgx_shuffle_fx1,
         fgx_pack16_fx1,
         fgx_pack32_fx1,
         fgx_packfix_fx1,
         fac_fgx_pdist_fx1,
         fgx_popc_fx1,
         i_fgx_siam_fx1,
         fac_fpx_sp_dest_fx1,
         fac_rs1_sel_fx1[4:0],
         fac_rs2_sel_fx1[3:0],
         rnd_8x16_fx1[1:0],
         result_sel_fx1[5:0],
         i_exu_w_vld_fx1,
         irf_w_addr_fx1[4:0],
         fac_r1_vld_fx1[1:0],
         fac_r2_vld_fx1[1:0],
         spu_grant_fx1,
         fac_div_valid_fx1,
         fac_divq_valid_fx1,
         divq_occupied_fx1,
         fac_div_control_fx1[4:0],
         div_tid_fx1[2:0],
         div_irf_addr_fx1[4:0],
         div_frf_addr_fx1[4:0],
         div_cc_vld_fx1,
         div_odd32b_fx1,
         div_32b_fx1,
         divq_tid_fx1[2:0],
         divq_irf_addr_fx1[4:0],
         divq_frf_addr_fx1[4:0],
         divq_cc_vld_fx1,
         divq_odd32b_fx1,
         divq_32b_fx1,
         div_engine_busy_fx1,
         div_dec_issue_fx1,
         div_divq_issue_fx1,
         fac_force_swap_blta_fx1,
         fac_force_noswap_blta_fx1,
         fsr_store_fx1,
         fac_xr_mode_fx1,
         spu_fpy_ctl_fx1[5:0],
         frf_store_fx1,
         fac_fst_fmt_sel_fx1[3:0],
         fgu_decode_fx1}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_21 fx1_01  (
  .scan_in(fx1_01_scanin),
  .scan_out(fx1_01_scanout),
  .l1clk(l1clk_pm1),
  .din ({w1_addr_e[4:0],
        w1_32b_e,
        w1_odd32b_e,
        fac_tid_e[2:0],
        q_w1_vld_e[1:0],
        tlu_cerer_frf,
        tlu_ceter_pscce[7:0]}),
  .dout({w1_addr_fx1[4:0],
        w1_32b_fx1,
        fac_w1_odd32b_fx1,
        tid_fx1[2:0],
        q_w1_vld_fx1[1:0],
            cerer_frf_fx1,
            ceter_pscce_fx1[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_4 fx1_02  (
  .scan_in(fx1_02_scanin),
  .scan_out(fx1_02_scanout),
  .l1clk(l1clk_pm1),
  .din (pre_fcc_vld_e[3:0]  ),
  .dout(pre_fcc_vld_fx1[3:0]),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fgx_instr_fx1 =  // note: this eq. doesn't include siam
      fgx_logical_fx1  |
      fgx_expand_fx1   |
      fgx_merge_fx1    |
      fgx_align_fx1    |
      fgx_shuffle_fx1  |
  fac_fgx_pdist_fx1    |
      fgx_pack_sel_fx1 |
      fgx_moves_fx1    |
      fgx_popc_fx1     ;

assign  fac_ecc_trap_en_fx1 =
  cerer_frf_fx1 &
  (((tid_fx1[2:0] == 3'd0) & ceter_pscce_fx1[0]) |
   ((tid_fx1[2:0] == 3'd1) & ceter_pscce_fx1[1]) |
   ((tid_fx1[2:0] == 3'd2) & ceter_pscce_fx1[2]) |
   ((tid_fx1[2:0] == 3'd3) & ceter_pscce_fx1[3]) |
   ((tid_fx1[2:0] == 3'd4) & ceter_pscce_fx1[4]) |
   ((tid_fx1[2:0] == 3'd5) & ceter_pscce_fx1[5]) |
   ((tid_fx1[2:0] == 3'd6) & ceter_pscce_fx1[6]) |
   ((tid_fx1[2:0] == 3'd7) & ceter_pscce_fx1[7])  );

assign  fgx_siam_fx1 = i_fgx_siam_fx1 & fac_dec_valid_fx1;

assign  fac_w1_vld_fx1[1:0] = q_w1_vld_fx1[1:0] & {2{fac_dec_valid_fx1}};

assign  exu_w_vld_fx1 =
  fac_dec_valid_fx1 &
  (fgx_popc_fx1            |                                   // popc
   fac_fpx_mulscc_fx1      |                                   // mulscc
   fac_fpx_saverestore_fx1 |                                   // save or restore
   ((fac_fpx_itype_fx1[2:0] == 3'b101) & i_exu_w_vld_fx1) |    // imul
   ((fac_fpx_itype_fx1[2:0] == 3'b100) &
    (fac_fpx_dtype_fx1[2:1] == 2'b01 )  )                  );  // vis fcmp

assign  fac_fcmpe_fx1 = opf_fx1[2];  // FCMPE, not FCMP

assign  fac_fpx_sp_src_fx1 =
  ((fac_fpx_dtype_fx1[2:0] == 3'b000) &
   ~((fac_fpx_itype_fx1[2:0] == 3'b001) &     // ~FdTOs
     (fac_fpx_stype_fx1[1:0] == 2'b01 )) ) |
  ((fac_fpx_itype_fx1[2:0] == 3'b001) &
   (fac_fpx_dtype_fx1[2:0] == 3'b001)    ) |  //  FsTOd
  ((fac_fpx_itype_fx1[2:0] == 3'b101) &
   (fac_fpx_stype_fx1[1:0] == 2'b00 ) &
   (fac_fpx_dtype_fx1[2:0] == 3'b001)    ) |  //  FsMULd
  ((fac_fpx_itype_fx1[2:0] == 3'b010) &
   (fac_fpx_stype_fx1[1:0] == 2'b00 )    ) ;  //  FsTO(i,x)

assign  fgx_moves_fx1    = fgx_mvcond_fx1 | fgx_mvucond_fx1 | fgx_abs_fx1 | fgx_neg_fx1;
assign  fgx_pack_sel_fx1 = fgx_pack16_fx1 | fgx_pack32_fx1 | fgx_packfix_fx1;


// ------------------------------------
// FPD control
// ------------------------------------

assign  fac_aux_cin_fx1 = ~(fac_fpx_itype_fx1[2:0] == 3'b110);  // ~div

assign  q_div_default_res_fx3 = 
   div_default_res_fx3 &
  ~dec_flush_fx3       &
  ~fac_tlu_flush_fx3   ;

assign  div_finish_early =
  fdc_finish_flts_early | fdc_finish_fltd_early | fdc_finish_int_early;

assign  divide_completion_fx1[0] =
  ((div_tid_fx1[2:0] == 3'b000) & div_finish_early     ) |
  ((    tid_fx3[2:0] == 3'b000) & q_div_default_res_fx3) ;
				  
assign  divide_completion_fx1[1] =	  
  ((div_tid_fx1[2:0] == 3'b001) & div_finish_early     ) |
  ((    tid_fx3[2:0] == 3'b001) & q_div_default_res_fx3) ;
				  
assign  divide_completion_fx1[2] =	  
  ((div_tid_fx1[2:0] == 3'b010) & div_finish_early     ) |
  ((    tid_fx3[2:0] == 3'b010) & q_div_default_res_fx3) ;
				  
assign  divide_completion_fx1[3] =	  
  ((div_tid_fx1[2:0] == 3'b011) & div_finish_early     ) |
  ((    tid_fx3[2:0] == 3'b011) & q_div_default_res_fx3) ;
				  
assign  divide_completion_fx1[4] =	  
  ((div_tid_fx1[2:0] == 3'b100) & div_finish_early     ) |
  ((    tid_fx3[2:0] == 3'b100) & q_div_default_res_fx3) ;
				  
assign  divide_completion_fx1[5] =	  
  ((div_tid_fx1[2:0] == 3'b101) & div_finish_early     ) |
  ((    tid_fx3[2:0] == 3'b101) & q_div_default_res_fx3) ;
				  
assign  divide_completion_fx1[6] =	  
  ((div_tid_fx1[2:0] == 3'b110) & div_finish_early     ) |
  ((    tid_fx3[2:0] == 3'b110) & q_div_default_res_fx3) ;
				  
assign  divide_completion_fx1[7] =	  
  ((div_tid_fx1[2:0] == 3'b111) & div_finish_early     ) |
  ((    tid_fx3[2:0] == 3'b111) & q_div_default_res_fx3) ;


// ----------------------------------------------------------------------------
//                               FX2 stage
// ----------------------------------------------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_16 fx2_00  (
  .scan_in(fx2_00_scanin),
  .scan_out(fx2_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({w1_addr_fx1[4:0],
         w1_32b_fx1,
         fac_w1_odd32b_fx1,
         tid_fx1[2:0],
         exu_w_vld_fx1,
         irf_w_addr_fx1[4:0]}),
  .dout({w1_addr_fx2[4:0],
         w1_32b_fx2,
         w1_odd32b_fx2,
         tid_fx2[2:0],
         i_exu_w_vld_fx2,
         irf_w_addr_fx2[4:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_60 fx2_01  (
  .scan_in(fx2_01_scanin),
  .scan_out(fx2_01_scanout),
  .l1clk(l1clk_pm1),
  .din ({opf_fx1[4:1],
         fgx_mvcond_fx1,
         fgx_mvucond_fx1,
         fgx_abs_fx1,
         fgx_neg_fx1,
         fgx_logical_fx1,
         fgx_expand_fx1,
         fgx_merge_fx1,
         fgx_align_fx1,
         fgx_shuffle_fx1,
         fgx_pack16_fx1,
         fgx_pack32_fx1,
         fgx_packfix_fx1,
         fgx_popc_fx1,
         fgx_siam_fx1,
         fgx_pack_sel_fx1,
         rnd_8x16_fx1[1:0],
         result_sel_fx1[5:0],
         divide_completion_fx1[7:0],
         fpx_int_cc_vld_fx1,
         dec_flush_f1,
         pre_fcc_vld_fx1[3:0],
         div_dec_issue_fx1,
         div_divq_issue_fx1,
         fac_dec_valid_fx1,
         fac_fpx_itype_fx1[2:0],
         itype_mul_fx1,
             fsr_store_fx1,
         spu_grant_fx1,
         spu_fpy_ctl_fx1[5:0],
         fac_rs2_sel_fx1[2],
         fgx_instr_fx1,
         div_engine_busy_fx1,
         frf_store_fx1}),
  .dout({fac_opf_fx2[4:1],
         fac_fgx_mvcond_fx2,
         fac_fgx_mvucond_fx2,
         fac_fgx_abs_fx2,
         fac_fgx_neg_fx2,
         fac_fgx_logical_fx2,
         fac_fgx_expand_fx2,
         fac_fgx_merge_fx2,
         fac_fgx_align_fx2,
         fac_fgx_shuffle_fx2,
         fac_fgx_pack16_fx2,
         fac_fgx_pack32_fx2,
         fac_fgx_packfix_fx2,
         fac_fgx_popc_fx2,
         fac_fgx_siam_fx2,
         fac_fgx_pack_sel_fx2,
         rnd_8x16_fx2[1:0],
         result_sel_fx2[5:0],
         fgu_divide_completion[7:0],
         fpx_int_cc_vld_fx2,
         dec_flush_fx2,
         i_pre_fcc_vld_fx2[3:0],
         div_dec_issue_fx2,
         div_divq_issue_fx2,
         dec_valid_fx2,
                 itype_fx2[2:0],
         itype_mul_fx2,
         fac_fsr_store_fx2,
         spu_grant_fx2,
         spu_fpy_ctl_fx2[5:0],
         rs2_sel_fx2_b2,
         fgx_instr_fx2,
         div_engine_busy_fx2,
         frf_store_fx2}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_3 fx2_02  (
  .scan_in(fx2_02_scanin),
  .scan_out(fx2_02_scanout),
  .l1clk(l1clk_pm2),
  .din ({exu_fgu_flush_m,           // requires free running clk
         exu_fgu_gsr_vld_m[1:0]}),  // requires free running clk
  .dout({exu_flush_fx2,
         fac_gsr_w_vld_fx2[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fac_gsr_asr_tid_fx2[2:0] = rng_wr_tid_3f[2:0];
assign  fac_tid_fx2[2:0]         = tid_fx2[2:0];
assign  gsr_w_vld_fx2 = |fac_gsr_w_vld_fx2[1:0];

assign  dec_valid_noflush_fx2 =
  dec_valid_fx2  &
  ~dec_flush_fx2 ;

// 0in custom -fire ($0in_delay(fac_fgx_pdist_fx1,1) & dec_valid_fx2 & fac_dec_valid_fx1) -message "PDIST 2nd beat collision with other FPop"

assign  exu_w_vld_fx2 =
  i_exu_w_vld_fx2 &
  ~dec_flush_fx2  &
  ~exu_flush_fx2  &
  ~(fec_uecc_fx2 | fec_cecc_fx2);

assign  fac_pre_fcc_vld_fx2[3] =
  i_pre_fcc_vld_fx2[3] &
  ~dec_flush_fx2       &
  ~exu_flush_fx2       &
  ~dec_flush_f2        &
//~tlu_flush_fgu_b     &
  ~(fec_uecc_fx2 | fec_cecc_fx2);

assign  fac_pre_fcc_vld_fx2[2] =
  i_pre_fcc_vld_fx2[2] &
  ~dec_flush_fx2       &
  ~exu_flush_fx2       &
  ~dec_flush_f2        &
//~tlu_flush_fgu_b     &
  ~(fec_uecc_fx2 | fec_cecc_fx2);

assign  fac_pre_fcc_vld_fx2[1] =
  i_pre_fcc_vld_fx2[1] &
  ~dec_flush_fx2       &
  ~exu_flush_fx2       &
  ~dec_flush_f2        &
//~tlu_flush_fgu_b     &
  ~(fec_uecc_fx2 | fec_cecc_fx2);

assign  fac_pre_fcc_vld_fx2[0] =
  i_pre_fcc_vld_fx2[0] &
  ~dec_flush_fx2       &
  ~exu_flush_fx2       &
  ~dec_flush_f2        &
//~tlu_flush_fgu_b     &
  ~(fec_uecc_fx2 | fec_cecc_fx2);

assign  pre_fcc_vld_fx2 = |fac_pre_fcc_vld_fx2[3:0];

assign  i_fld_fcc_vld_fx2[1] =  // load FSR 64b
  lsu_fgu_fsr_load_b &
  ~lsu_fgu_fld_32b_b ;

assign  i_fld_fcc_vld_fx2[0] =  // load FSR 32/64b
  lsu_fgu_fsr_load_b;

// ------------------------------------
// FPY control
// ------------------------------------

// spu_fgu_fpy_ctl_d[6:0]:
//
//            [0]     [1]             [2]             [3]             [4]     [5]                       [6]
//            ---     ------------    --------------  -----------     -----   -----------------------   --------------------
// if == 1    XOR     Add Accum       Write Accum     2*(rs1*rs2)     >> 64   write MA result flop      bypass result to rs1
// if == 0    Int     No Add Accum    No Write Accum    (rs1*rs2)     >> 0    no write MA result flop   no bypass result

assign  scff_sel_fx2[0] =
  (~spu_grant_fx2 & ~rs2_sel_fx2_b2) |                           // ~spu & ~8x16
  ( spu_grant_fx2 & ~spu_fpy_ctl_fx2[0] & ~spu_fpy_ctl_fx2[3]);  //  spu &  MA Int * 1

assign  scff_sel_fx2[1] =
  (~spu_grant_fx2 &  rs2_sel_fx2_b2);                            //  all 8x16

assign  scff_sel_fx2[2] =
  ( spu_grant_fx2 & ~spu_fpy_ctl_fx2[0] &  spu_fpy_ctl_fx2[3]);  //  spu &  MA Int * 2

assign  scff_sel_fx2[3] =
  ( spu_grant_fx2 &  spu_fpy_ctl_fx2[0] & ~spu_fpy_ctl_fx2[3]);  //  spu &  XOR    * 1

// fac_accum_sel_fx3[6:0]:
//
// [0] : Write ACCUM with result
// [1] : Add ACCUM to Mult product
// [2] : XOR Mult w/        ACCUM
// [3] : XOR Mult w/        ACCUM >> 64
// [4] : XOR Mult       w/o ACCUM
// [5] : XOR Mult       w/o ACCUM >> 64
// [6] : Int Mult w/ or w/o ACCUM
// Def : Int Mult w/ or w/o ACCUM >> 64

assign  accum_sel_fx2[0] = ( spu_grant_fx2 &  spu_fpy_ctl_fx2[2]);
assign  accum_sel_fx2[1] = ( spu_grant_fx2 &  spu_fpy_ctl_fx2[1]);
assign  accum_sel_fx2[2] = ( spu_grant_fx2 &  spu_fpy_ctl_fx2[0] &  spu_fpy_ctl_fx2[1] & ~spu_fpy_ctl_fx2[4]);
assign  accum_sel_fx2[3] = ( spu_grant_fx2 &  spu_fpy_ctl_fx2[0] &  spu_fpy_ctl_fx2[1] &  spu_fpy_ctl_fx2[4]);
assign  accum_sel_fx2[4] = ( spu_grant_fx2 &  spu_fpy_ctl_fx2[0] & ~spu_fpy_ctl_fx2[1] & ~spu_fpy_ctl_fx2[4]);
assign  accum_sel_fx2[5] = ( spu_grant_fx2 &  spu_fpy_ctl_fx2[0] & ~spu_fpy_ctl_fx2[1] &  spu_fpy_ctl_fx2[4]);
assign  accum_sel_fx2[6] = ( spu_grant_fx2 & ~spu_fpy_ctl_fx2[0] &                       ~spu_fpy_ctl_fx2[4]);


// ----------------------------------------------------------------------------
//                               FX3 stage
// ----------------------------------------------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_52 fx3_00  (
  .scan_in(fx3_00_scanin),
  .scan_out(fx3_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({w1_addr_fx2[4:0],
         w1_32b_fx2,
         w1_odd32b_fx2,
         tid_fx2[2:0],
             rnd_8x16_fx2[1:0],
             scff_sel_fx2[3:0],
         result_sel_fx2[5:0],
         exu_w_vld_fx2,
         irf_w_addr_fx2[4:0],
         fpx_int_cc_vld_fx2,
         dec_flush_f2,
         tlu_flush_fgu_b,
         div_dec_issue_fx2,
         fpc_pre_div_flush_fx2,
         fpc_div_default_res_fx2,
         dec_valid_fx2,
         itype_fx2[2:0],
         itype_mul_fx2,
         gsr_w_vld_fx2,
         spu_grant_fx2,
             accum_sel_fx2,
         spu_fpy_ctl_fx2[5],
         pre_fcc_vld_fx2,
         fgx_instr_fx2,
         dec_valid_noflush_fx2}),
  .dout({w1_addr_fx3[4:0],
         w1_32b_fx3,
         w1_odd32b_fx3,
         tid_fx3[2:0],
         fac_8x16_rnd_fx3[1:0],
         fac_scff_sel_fx3[3:0],
         result_sel_fx3[5:0],
         i_exu_w_vld_fx3,
         irf_w_addr_fx3[4:0],
         fpx_int_cc_vld_fx3,
         dec_flush_fx3,
         fac_tlu_flush_fx3,
         div_dec_issue_fx3,
           i_pre_div_flush_fx3,
             div_default_res_fx3,
         dec_valid_fx3,
         itype_fx3[2:0],
         itype_mul_fx3,
         gsr_w_vld_fx3,
         spu_grant_fx3,
         fac_accum_sel_fx3,
         spu_fpy_ctl_fx3[5],
         i_pre_fcc_vld_fx3,
         fgx_instr_fx3,
         i_dec_valid_noflush_fx3}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_3 fx3_01  (
  .scan_in(fx3_01_scanin),
  .scan_out(fx3_01_scanout),
  .l1clk(l1clk_pm2),
  .din ({lsu_fgu_fld_b,              // requires free running clk
         i_fld_fcc_vld_fx2[1:0]}),   // requires free running clk
  .dout({    fgu_fld_fx3,
             fgu_fld_fcc_vld_fx3[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  pre_fcc_vld_fx3 = i_pre_fcc_vld_fx3 & ~fac_tlu_flush_fx3;

assign  dec_valid_noflush_fx3 =
  i_dec_valid_noflush_fx3 &
  ~dec_flush_fx3          &
  ~fac_tlu_flush_fx3      ;

assign  dec_valid_imul_noflush_fx3 = dec_valid_noflush_fx3 & (itype_fx3[2:0] == 3'b101);  // mul

assign  fgu_cmp_fcc_tid_fx2[2:0] = tid_fx2[2:0];

assign  exu_w_vld_fx3 =
  i_exu_w_vld_fx3   &
  ~dec_flush_fx3    &
  ~fac_tlu_flush_fx3;

assign  pre_div_flush_fx3 =
  (itype_fx3[2:1] == 2'b11) &  // div/sqrt
  dec_valid_fx3 &
  (i_pre_div_flush_fx3 |
   div_default_res_fx3 |
   dec_flush_fx3       |
   fac_tlu_flush_fx3      ) ;

assign  fac_div_flush_fx3 =
  pre_div_flush_fx3 &
  (div_dec_issue_fx3  |    // DEC  issued div/sqrt
   div_divq_issue_fx1 |    // divq issued div/sqrt
   div_divq_issue_fx2  );  // divq issued div/sqrt


// ----------------------------------------------------------------------------
//                               FX4 stage
// ----------------------------------------------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_31 fx4_00  (
  .scan_in(fx4_00_scanin),
  .scan_out(fx4_00_scanout),
  .l1clk(l1clk_pm1), 
  .din ({w1_addr_fx3[4:0],
         w1_32b_fx3,
         w1_odd32b_fx3,
         tid_fx3[2:0],
             result_sel_fx3[5:0],
         exu_w_vld_fx3,
         irf_w_addr_fx3[4:0],
         fpx_int_cc_vld_fx3,
         spu_grant_fx3,
         spu_fpy_ctl_fx3[5],
         pre_fcc_vld_fx3,
         dec_valid_noflush_fx3,
         fgu_fld_fx3,
         gsr_w_vld_fx3,
         dec_valid_imul_noflush_fx3,
             fgx_instr_fx3}),
  .dout({w1_addr_fx4[4:0],
         w1_32b_fx4,
         w1_odd32b_fx4,
         tid_fx4[2:0],
         fac_result_sel_fx4[5:0],
         exu_w_vld_fx4,
         i_irf_w_addr_fx4[4:0],
         i_int_cc_vld_fx4,
         spu_grant_fx4,
         spu_fpy_ctl_fx4[5],
         pre_fcc_vld_fx4,
         dec_valid_noflush_fx4,
         fgu_fld_fx4,
         gsr_w_vld_fx4,
         dec_valid_imul_noflush_fx4,
         fac_fgx_instr_fx4}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fac_ma_result_en_fx4 = spu_grant_fx4 & spu_fpy_ctl_fx4[5];

assign  irf_result_tid_fx4[2:0] =
  ({3{~exu_w_vld_fx4}} & div_tid_fx1[2:0]     ) |
  ({3{ exu_w_vld_fx4}} & tid_fx4[2:0]         ) ;

assign  irf_w_addr_fx4[4:0] =
  ({5{~exu_w_vld_fx4}} & div_irf_addr_fx1[4:0]) |
  ({5{ exu_w_vld_fx4}} & i_irf_w_addr_fx4[4:0]) ;

assign  exu_cc_vld_fx4 =
  (   ~exu_w_vld_fx4   & div_cc_vld_fx1       ) |
  (    exu_w_vld_fx4   & i_int_cc_vld_fx4     ) ;


// ----------------------------------------------------------------------------
//                               FX5 stage
// ----------------------------------------------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_26 fx5_00  (
  .scan_in(fx5_00_scanin),
  .scan_out(fx5_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({w1_addr_fx4[4:0],
         w1_32b_fx4,
         w1_odd32b_fx4,
         tid_fx4[2:0],
         exu_w_vld_fx4,
         irf_w_addr_fx4[4:0],
         irf_result_tid_fx4[2:0],
         exu_cc_vld_fx4,
         pre_fcc_vld_fx4,
         dec_valid_noflush_fx4,
         spu_grant_fx4,
         fgu_fld_fx4,
         dec_valid_imul_noflush_fx4,
         fac_fgx_instr_fx4}),
  .dout({w1_addr_fx5[4:0],
         w1_32b_fx5,
         w1_odd32b_fx5,
         tid_fx5[2:0],
         i_exu_w_vld_fx5,
         fgu_irf_w_addr_fx5[4:0],
         irf_result_tid_fx5_b2, fgu_result_tid_fx5[1:0],
         exu_cc_vld_fx5,
         pre_fcc_vld_fx5,
         fac_dec_valid_noflush_fx5,
         spu_grant_fx5,
         fgu_fld_fx5,
         dec_valid_imul_noflush_fx5,
             fgx_instr_fx5}),
  .siclk(siclk),
  .soclk(soclk)
  );


// Note: no need for idiv0 to clear exu_w_vld or exu_cc_vld
//       since idiv0 clears fdc_finish_int_early

assign  fgu_exu_w_vld_fx5[0] =
  (i_exu_w_vld_fx5 | div_finish_int_fb) & ~irf_result_tid_fx5_b2;  // exu thread group 0

assign  fgu_exu_w_vld_fx5[1] =
  (i_exu_w_vld_fx5 | div_finish_int_fb) &  irf_result_tid_fx5_b2;  // exu thread group 1

assign  fgu_exu_cc_vld_fx5 = exu_cc_vld_fx5 & (i_exu_w_vld_fx5 | div_finish_int_fb);


// ----------------------------------------------------------------------------
//                               FB stage 
// ----------------------------------------------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_25 fb_00  (
  .scan_in(fb_00_scanin),
  .scan_out(fb_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({    w1_addr_fx5[4:0],
             w1_32b_fx5,
             w1_odd32b_fx5,
                tid_fx5[2:0],
         fpc_fsr_w1_vld_fx5[1:0],
         pre_fcc_vld_fx5,
         fpc_fcc_vld_fx5,
         fdc_finish_int_early,
         fdc_finish_flts_early,
         fdc_finish_fltd_early,
         fac_dec_valid_noflush_fx5,
         fgu_fld_fx5,
         dec_valid_imul_noflush_fx5,
         fgx_instr_fx5,
         fpc_stfsr_en_fx3to5}),
  .dout({fac_w1_addr_fb[4:0],
         fac_w1_32b_fb,
         fac_w1_odd32b_fb,
         fac_w1_tid_fb[2:0],
             fsr_w1_vld_fb[1:0],
         pre_fcc_vld_fb,
             fcc_vld_fb,
         div_finish_int_fb,
         div_finish_flts_fb,
         div_finish_fltd_fb,
             dec_valid_noflush_fb,
         fgu_fld_fb,
         dec_valid_imul_noflush_fb,
         fgx_instr_fb,
         fpc_stfsr_en_fb}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fac_fpd_addr_fb[4:0] = div_frf_addr_fx1[4:0];
assign  fac_fpd_32b_fb       = div_32b_fx1;
assign  fac_fpd_odd32b_fb    = div_odd32b_fx1;
assign  fac_fpd_tid_fb[2:0]  = div_tid_fx1[2:0];

assign  div_finish_fb = div_finish_int_fb | div_finish_flts_fb | div_finish_fltd_fb;


// ----------------------------------------------------------------------------
//                               FW stage 
// ----------------------------------------------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_21 fw_00  (
  .scan_in(fw_00_scanin),
  .scan_out(fw_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({fac_fpd_tid_fb[2:0],
         fac_w1_tid_fb[2:0],
         fac_w1_addr_fb[4],
         dec_valid_noflush_fb,
         dec_valid_noflush_fw,
         dec_valid_noflush_fw1,
         div_finish_fb,
         div_finish_fw,
         div_finish_fw1,
         div_finish_fw2,
         dec_valid_imul_noflush_fb,
         dec_valid_imul_noflush_fw,
         dec_valid_imul_noflush_fw1,
         fgx_instr_fb,
         fgx_instr_fw,
         fgx_instr_fw1,
         fpc_stfsr_en_fb}),
  .dout({fgu_fpd_trap_tid_fw[2:0],
         fgu_fpx_trap_tid_fw[2:0],
           w1_addr_fw_b4,
         dec_valid_noflush_fw,
         dec_valid_noflush_fw1,
         dec_valid_noflush_fw2,
         div_finish_fw,
         div_finish_fw1,
         div_finish_fw2,
         div_finish_fw3,
         dec_valid_imul_noflush_fw,
         dec_valid_imul_noflush_fw1,
         dec_valid_imul_noflush_fw2,
         fgx_instr_fw,
         fgx_instr_fw1,
         fgx_instr_fw2,
         fpc_stfsr_en_fw}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_53 fw_01  (
  .scan_in(fw_01_scanin),
  .scan_out(fw_01_scanout),
  .l1clk(l1clk_pm2),
  .din ({    fsr0_sel_fb[5:0],    // requires free running clk
             fsr1_sel_fb[5:0],    // requires free running clk
             fsr2_sel_fb[5:0],    // requires free running clk
             fsr3_sel_fb[5:0],    // requires free running clk
             fsr4_sel_fb[5:0],    // requires free running clk
             fsr5_sel_fb[5:0],    // requires free running clk
             fsr6_sel_fb[5:0],    // requires free running clk
             fsr7_sel_fb[5:0],    // requires free running clk
         lsu_fgu_fld_tid_b[2:0],  // requires free running clk
         i_fsr_w2_vld_fb[1:0]}),  // requires free running clk
  .dout({fac_fsr0_sel_fw[5:4], i_fsr0_sel_fw[3], fac_fsr0_sel_fw[2:1], i_fsr0_sel_fw[0],
         fac_fsr1_sel_fw[5:4], i_fsr1_sel_fw[3], fac_fsr1_sel_fw[2:1], i_fsr1_sel_fw[0],
         fac_fsr2_sel_fw[5:4], i_fsr2_sel_fw[3], fac_fsr2_sel_fw[2:1], i_fsr2_sel_fw[0],
         fac_fsr3_sel_fw[5:4], i_fsr3_sel_fw[3], fac_fsr3_sel_fw[2:1], i_fsr3_sel_fw[0],
         fac_fsr4_sel_fw[5:4], i_fsr4_sel_fw[3], fac_fsr4_sel_fw[2:1], i_fsr4_sel_fw[0],
         fac_fsr5_sel_fw[5:4], i_fsr5_sel_fw[3], fac_fsr5_sel_fw[2:1], i_fsr5_sel_fw[0],
         fac_fsr6_sel_fw[5:4], i_fsr6_sel_fw[3], fac_fsr6_sel_fw[2:1], i_fsr6_sel_fw[0],
         fac_fsr7_sel_fw[5:4], i_fsr7_sel_fw[3], fac_fsr7_sel_fw[2:1], i_fsr7_sel_fw[0],
         lsu_fgu_fld_tid_fw[2:0],
         i_fsr_w2_vld_fw[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fsr_w2_vld_fw[0] =                 // load FSR 32b
  i_fsr_w2_vld_fw[0] & lsu_fgu_fld_vld_w;

assign  fsr_w2_vld_fw[1] =                 // load FSR 64b
  i_fsr_w2_vld_fw[1] & lsu_fgu_fld_vld_w;

assign  fac_fsr0_sel_fw[3] =    // enable flop
  i_fsr0_sel_fw[3]                                             |
  (( |fsr_w2_vld_fw[1:0]) & (lsu_fgu_fld_tid_fw[2:0] == 3'd0)) ;

assign  fac_fsr1_sel_fw[3] =    // enable flop
  i_fsr1_sel_fw[3]                                             |
  (( |fsr_w2_vld_fw[1:0]) & (lsu_fgu_fld_tid_fw[2:0] == 3'd1)) ;

assign  fac_fsr2_sel_fw[3] =    // enable flop
  i_fsr2_sel_fw[3]                                             |
  (( |fsr_w2_vld_fw[1:0]) & (lsu_fgu_fld_tid_fw[2:0] == 3'd2)) ;

assign  fac_fsr3_sel_fw[3] =    // enable flop
  i_fsr3_sel_fw[3]                                             |
  (( |fsr_w2_vld_fw[1:0]) & (lsu_fgu_fld_tid_fw[2:0] == 3'd3)) ;

assign  fac_fsr4_sel_fw[3] =    // enable flop
  i_fsr4_sel_fw[3]                                             |
  (( |fsr_w2_vld_fw[1:0]) & (lsu_fgu_fld_tid_fw[2:0] == 3'd4)) ;

assign  fac_fsr5_sel_fw[3] =    // enable flop
  i_fsr5_sel_fw[3]                                             |
  (( |fsr_w2_vld_fw[1:0]) & (lsu_fgu_fld_tid_fw[2:0] == 3'd5)) ;

assign  fac_fsr6_sel_fw[3] =    // enable flop
  i_fsr6_sel_fw[3]                                             |
  (( |fsr_w2_vld_fw[1:0]) & (lsu_fgu_fld_tid_fw[2:0] == 3'd6)) ;

assign  fac_fsr7_sel_fw[3] =    // enable flop
  i_fsr7_sel_fw[3]                                             |
  (( |fsr_w2_vld_fw[1:0]) & (lsu_fgu_fld_tid_fw[2:0] == 3'd7)) ;

assign  fac_fsr0_sel_fw[0] =
  i_fsr0_sel_fw[0]                                                      |
//(   (fsr_w2_vld_fw[0] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd0))   & 1'b0) |  // LDFSR
  (   (fsr_w2_vld_fw[1] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd0))         ) ;  // LDXFSR

assign  fac_fsr1_sel_fw[0] =
  i_fsr1_sel_fw[0]                                                      |
//(   (fsr_w2_vld_fw[0] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd1))   & 1'b0) |  // LDFSR
  (   (fsr_w2_vld_fw[1] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd1))         ) ;  // LDXFSR

assign  fac_fsr2_sel_fw[0] =
  i_fsr2_sel_fw[0]                                                      |
//(   (fsr_w2_vld_fw[0] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd2))   & 1'b0) |  // LDFSR
  (   (fsr_w2_vld_fw[1] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd2))         ) ;  // LDXFSR

assign  fac_fsr3_sel_fw[0] =
  i_fsr3_sel_fw[0]                                                      |
//(   (fsr_w2_vld_fw[0] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd3))   & 1'b0) |  // LDFSR
  (   (fsr_w2_vld_fw[1] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd3))         ) ;  // LDXFSR

assign  fac_fsr4_sel_fw[0] =
  i_fsr4_sel_fw[0]                                                      |
//(   (fsr_w2_vld_fw[0] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd4))   & 1'b0) |  // LDFSR
  (   (fsr_w2_vld_fw[1] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd4))         ) ;  // LDXFSR

assign  fac_fsr5_sel_fw[0] =
  i_fsr5_sel_fw[0]                                                      |
//(   (fsr_w2_vld_fw[0] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd5))   & 1'b0) |  // LDFSR
  (   (fsr_w2_vld_fw[1] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd5))         ) ;  // LDXFSR

assign  fac_fsr6_sel_fw[0] =
  i_fsr6_sel_fw[0]                                                      |
//(   (fsr_w2_vld_fw[0] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd6))   & 1'b0) |  // LDFSR
  (   (fsr_w2_vld_fw[1] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd6))         ) ;  // LDXFSR

assign  fac_fsr7_sel_fw[0] =
  i_fsr7_sel_fw[0]                                                      |
//(   (fsr_w2_vld_fw[0] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd7))   & 1'b0) |  // LDFSR
  (   (fsr_w2_vld_fw[1] & (lsu_fgu_fld_tid_fw[2:0]  == 3'd7))         ) ;  // LDXFSR

// ------------------------------------
// FPRS
//
// FPRS[2:0] = {fef, du, dl}
// ------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_12 fprs_frf_ctl  (
  .scan_in(fprs_frf_ctl_scanin),
  .scan_out(fprs_frf_ctl_scanout),
  .l1clk(l1clk_pm1),
  .din ({w1_addr_fw_b4,
         fad_w1_tid_fw[2:0],
         fad_w1_vld_fw[1:0],
         fad_w2_addr_fw1_b4,
         fad_w2_tid_fw1[2:0],
         fad_w2_vld_fw1[1:0]}),
  .dout({fprs_w1_addr[4],
         fprs_w1_tid[2:0],
         fprs_w1_vld[1:0],
         fprs_w2_addr[4],
         fprs_w2_tid[2:0],
         fprs_w2_vld[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

// ----------
// FPRS tid0
// ----------

assign  fprs_tid0_sel[0] =  rng_wr_fprs_3f   & (rng_wr_tid_3f[2:0] == 3'd0);  // ASR FPRS write
assign  fprs_tid0_sel[1] = |fprs_w1_vld[1:0] & (fprs_w1_tid[2:0]   == 3'd0);  // FRF w1   write
assign  fprs_tid0_sel[2] = |fprs_w2_vld[1:0] & (fprs_w2_tid[2:0]   == 3'd0);  // FRF w2   write
assign  fprs_tid0_sel[3] = ~(|fprs_tid0_sel[2:0]);                            // hold

assign din_fprs_tid0[0] =  // dirty lower
  ( fprs_tid0_sel[0] &  rng_data_2f_b7_0[0]             ) |  // ASR FPRS write
  ( fprs_tid0_sel[1] & (fprs_tid0[0] | ~fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid0_sel[2] & (fprs_tid0[0] | ~fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid0_sel[3] &  fprs_tid0[0]                    ) ;  // hold

assign din_fprs_tid0[1] =  // dirty upper
  ( fprs_tid0_sel[0] &  rng_data_2f_b7_0[1]             ) |  // ASR FPRS write
  ( fprs_tid0_sel[1] & (fprs_tid0[1] |  fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid0_sel[2] & (fprs_tid0[1] |  fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid0_sel[3] &  fprs_tid0[1]                    ) ;  // hold

assign din_fprs_tid0[2] =  // enable fp (POR value is 1'b1)
  ~(( fprs_tid0_sel[0] &  rng_data_2f_b7_0[2]) |    // ASR FPRS write
    (~fprs_tid0_sel[0] &  fprs_tid0[2]       )  );  // hold

fgu_fac_ctl_msff_ctl_macro__width_3 fprstid0  (				// FS:wmr_protect
  .scan_in(fprstid0_wmr_scanin),
  .scan_out(fprstid0_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din (din_fprs_tid0[2:0]),
  .dout({fprs_tid0_[2], fprs_tid0[1:0]}),
  .soclk(soclk)
  );

assign  fprs_tid0[2] = ~fprs_tid0_[2];

// ----------
// FPRS tid1
// ----------

assign  fprs_tid1_sel[0] =  rng_wr_fprs_3f   & (rng_wr_tid_3f[2:0] == 3'd1);  // ASR FPRS write
assign  fprs_tid1_sel[1] = |fprs_w1_vld[1:0] & (fprs_w1_tid[2:0]   == 3'd1);  // FRF w1   write
assign  fprs_tid1_sel[2] = |fprs_w2_vld[1:0] & (fprs_w2_tid[2:0]   == 3'd1);  // FRF w2   write
assign  fprs_tid1_sel[3] = ~(|fprs_tid1_sel[2:0]);                            // hold

assign din_fprs_tid1[0] =  // dirty lower
  ( fprs_tid1_sel[0] &  rng_data_2f_b7_0[0]             ) |  // ASR FPRS write
  ( fprs_tid1_sel[1] & (fprs_tid1[0] | ~fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid1_sel[2] & (fprs_tid1[0] | ~fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid1_sel[3] &  fprs_tid1[0]                    ) ;  // hold

assign din_fprs_tid1[1] =  // dirty upper
  ( fprs_tid1_sel[0] &  rng_data_2f_b7_0[1]             ) |  // ASR FPRS write
  ( fprs_tid1_sel[1] & (fprs_tid1[1] |  fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid1_sel[2] & (fprs_tid1[1] |  fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid1_sel[3] &  fprs_tid1[1]                    ) ;  // hold

assign din_fprs_tid1[2] =  // enable fp (POR value is 1'b1)
  ~(( fprs_tid1_sel[0] &  rng_data_2f_b7_0[2]) |    // ASR FPRS write
    (~fprs_tid1_sel[0] &  fprs_tid1[2]       )  );  // hold

fgu_fac_ctl_msff_ctl_macro__width_3 fprstid1  (				// FS:wmr_protect
  .scan_in(fprstid1_wmr_scanin),
  .scan_out(fprstid1_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din (din_fprs_tid1[2:0]),
  .dout({fprs_tid1_[2], fprs_tid1[1:0]}),
  .soclk(soclk)
  );

assign  fprs_tid1[2] = ~fprs_tid1_[2];

// ----------
// FPRS tid2
// ----------

assign  fprs_tid2_sel[0] =  rng_wr_fprs_3f   & (rng_wr_tid_3f[2:0] == 3'd2);  // ASR FPRS write
assign  fprs_tid2_sel[1] = |fprs_w1_vld[1:0] & (fprs_w1_tid[2:0]   == 3'd2);  // FRF w1   write
assign  fprs_tid2_sel[2] = |fprs_w2_vld[1:0] & (fprs_w2_tid[2:0]   == 3'd2);  // FRF w2   write
assign  fprs_tid2_sel[3] = ~(|fprs_tid2_sel[2:0]);                            // hold

assign din_fprs_tid2[0] =  // dirty lower
  ( fprs_tid2_sel[0] &  rng_data_2f_b7_0[0]             ) |  // ASR FPRS write
  ( fprs_tid2_sel[1] & (fprs_tid2[0] | ~fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid2_sel[2] & (fprs_tid2[0] | ~fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid2_sel[3] &  fprs_tid2[0]                    ) ;  // hold

assign din_fprs_tid2[1] =  // dirty upper
  ( fprs_tid2_sel[0] &  rng_data_2f_b7_0[1]             ) |  // ASR FPRS write
  ( fprs_tid2_sel[1] & (fprs_tid2[1] |  fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid2_sel[2] & (fprs_tid2[1] |  fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid2_sel[3] &  fprs_tid2[1]                    ) ;  // hold

assign din_fprs_tid2[2] =  // enable fp (POR value is 1'b1)
  ~(( fprs_tid2_sel[0] &  rng_data_2f_b7_0[2]) |    // ASR FPRS write
    (~fprs_tid2_sel[0] &  fprs_tid2[2]       )  );  // hold

fgu_fac_ctl_msff_ctl_macro__width_3 fprstid2  (				// FS:wmr_protect
  .scan_in(fprstid2_wmr_scanin),
  .scan_out(fprstid2_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din (din_fprs_tid2[2:0]),
  .dout({fprs_tid2_[2], fprs_tid2[1:0]}),
  .soclk(soclk)
  );

assign  fprs_tid2[2] = ~fprs_tid2_[2];

// ----------
// FPRS tid3
// ----------

assign  fprs_tid3_sel[0] =  rng_wr_fprs_3f   & (rng_wr_tid_3f[2:0] == 3'd3);  // ASR FPRS write
assign  fprs_tid3_sel[1] = |fprs_w1_vld[1:0] & (fprs_w1_tid[2:0]   == 3'd3);  // FRF w1   write
assign  fprs_tid3_sel[2] = |fprs_w2_vld[1:0] & (fprs_w2_tid[2:0]   == 3'd3);  // FRF w2   write
assign  fprs_tid3_sel[3] = ~(|fprs_tid3_sel[2:0]);                            // hold

assign din_fprs_tid3[0] =  // dirty lower
  ( fprs_tid3_sel[0] &  rng_data_2f_b7_0[0]             ) |  // ASR FPRS write
  ( fprs_tid3_sel[1] & (fprs_tid3[0] | ~fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid3_sel[2] & (fprs_tid3[0] | ~fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid3_sel[3] &  fprs_tid3[0]                    ) ;  // hold

assign din_fprs_tid3[1] =  // dirty upper
  ( fprs_tid3_sel[0] &  rng_data_2f_b7_0[1]             ) |  // ASR FPRS write
  ( fprs_tid3_sel[1] & (fprs_tid3[1] |  fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid3_sel[2] & (fprs_tid3[1] |  fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid3_sel[3] &  fprs_tid3[1]                    ) ;  // hold

assign din_fprs_tid3[2] =  // enable fp (POR value is 1'b1)
  ~(( fprs_tid3_sel[0] &  rng_data_2f_b7_0[2]) |    // ASR FPRS write
    (~fprs_tid3_sel[0] &  fprs_tid3[2]       )  );  // hold

fgu_fac_ctl_msff_ctl_macro__width_3 fprstid3  (				// FS:wmr_protect
  .scan_in(fprstid3_wmr_scanin),
  .scan_out(fprstid3_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din (din_fprs_tid3[2:0]),
  .dout({fprs_tid3_[2], fprs_tid3[1:0]}),
  .soclk(soclk)
  );

assign  fprs_tid3[2] = ~fprs_tid3_[2];

// ----------
// FPRS tid4
// ----------

assign  fprs_tid4_sel[0] =  rng_wr_fprs_3f   & (rng_wr_tid_3f[2:0] == 3'd4);  // ASR FPRS write
assign  fprs_tid4_sel[1] = |fprs_w1_vld[1:0] & (fprs_w1_tid[2:0]   == 3'd4);  // FRF w1   write
assign  fprs_tid4_sel[2] = |fprs_w2_vld[1:0] & (fprs_w2_tid[2:0]   == 3'd4);  // FRF w2   write
assign  fprs_tid4_sel[3] = ~(|fprs_tid4_sel[2:0]);                            // hold

assign din_fprs_tid4[0] =  // dirty lower
  ( fprs_tid4_sel[0] &  rng_data_2f_b7_0[0]             ) |  // ASR FPRS write
  ( fprs_tid4_sel[1] & (fprs_tid4[0] | ~fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid4_sel[2] & (fprs_tid4[0] | ~fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid4_sel[3] &  fprs_tid4[0]                    ) ;  // hold

assign din_fprs_tid4[1] =  // dirty upper
  ( fprs_tid4_sel[0] &  rng_data_2f_b7_0[1]             ) |  // ASR FPRS write
  ( fprs_tid4_sel[1] & (fprs_tid4[1] |  fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid4_sel[2] & (fprs_tid4[1] |  fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid4_sel[3] &  fprs_tid4[1]                    ) ;  // hold

assign din_fprs_tid4[2] =  // enable fp (POR value is 1'b1)
  ~(( fprs_tid4_sel[0] &  rng_data_2f_b7_0[2]) |    // ASR FPRS write
    (~fprs_tid4_sel[0] &  fprs_tid4[2]       )  );  // hold

fgu_fac_ctl_msff_ctl_macro__width_3 fprstid4  (				// FS:wmr_protect
  .scan_in(fprstid4_wmr_scanin),
  .scan_out(fprstid4_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din (din_fprs_tid4[2:0]),
  .dout({fprs_tid4_[2], fprs_tid4[1:0]}),
  .soclk(soclk)
  );

assign  fprs_tid4[2] = ~fprs_tid4_[2];

// ----------
// FPRS tid5
// ----------

assign  fprs_tid5_sel[0] =  rng_wr_fprs_3f   & (rng_wr_tid_3f[2:0] == 3'd5);  // ASR FPRS write
assign  fprs_tid5_sel[1] = |fprs_w1_vld[1:0] & (fprs_w1_tid[2:0]   == 3'd5);  // FRF w1   write
assign  fprs_tid5_sel[2] = |fprs_w2_vld[1:0] & (fprs_w2_tid[2:0]   == 3'd5);  // FRF w2   write
assign  fprs_tid5_sel[3] = ~(|fprs_tid5_sel[2:0]);                            // hold

assign din_fprs_tid5[0] =  // dirty lower
  ( fprs_tid5_sel[0] &  rng_data_2f_b7_0[0]             ) |  // ASR FPRS write
  ( fprs_tid5_sel[1] & (fprs_tid5[0] | ~fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid5_sel[2] & (fprs_tid5[0] | ~fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid5_sel[3] &  fprs_tid5[0]                    ) ;  // hold

assign din_fprs_tid5[1] =  // dirty upper
  ( fprs_tid5_sel[0] &  rng_data_2f_b7_0[1]             ) |  // ASR FPRS write
  ( fprs_tid5_sel[1] & (fprs_tid5[1] |  fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid5_sel[2] & (fprs_tid5[1] |  fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid5_sel[3] &  fprs_tid5[1]                    ) ;  // hold

assign din_fprs_tid5[2] =  // enable fp (POR value is 1'b1)
  ~(( fprs_tid5_sel[0] &  rng_data_2f_b7_0[2]) |    // ASR FPRS write
    (~fprs_tid5_sel[0] &  fprs_tid5[2]       )  );  // hold

fgu_fac_ctl_msff_ctl_macro__width_3 fprstid5  (				// FS:wmr_protect
  .scan_in(fprstid5_wmr_scanin),
  .scan_out(fprstid5_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din (din_fprs_tid5[2:0]),
  .dout({fprs_tid5_[2], fprs_tid5[1:0]}),
  .soclk(soclk)
  );

assign  fprs_tid5[2] = ~fprs_tid5_[2];

// ----------
// FPRS tid6
// ----------

assign  fprs_tid6_sel[0] =  rng_wr_fprs_3f   & (rng_wr_tid_3f[2:0] == 3'd6);  // ASR FPRS write
assign  fprs_tid6_sel[1] = |fprs_w1_vld[1:0] & (fprs_w1_tid[2:0]   == 3'd6);  // FRF w1   write
assign  fprs_tid6_sel[2] = |fprs_w2_vld[1:0] & (fprs_w2_tid[2:0]   == 3'd6);  // FRF w2   write
assign  fprs_tid6_sel[3] = ~(|fprs_tid6_sel[2:0]);                            // hold

assign din_fprs_tid6[0] =  // dirty lower
  ( fprs_tid6_sel[0] &  rng_data_2f_b7_0[0]             ) |  // ASR FPRS write
  ( fprs_tid6_sel[1] & (fprs_tid6[0] | ~fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid6_sel[2] & (fprs_tid6[0] | ~fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid6_sel[3] &  fprs_tid6[0]                    ) ;  // hold

assign din_fprs_tid6[1] =  // dirty upper
  ( fprs_tid6_sel[0] &  rng_data_2f_b7_0[1]             ) |  // ASR FPRS write
  ( fprs_tid6_sel[1] & (fprs_tid6[1] |  fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid6_sel[2] & (fprs_tid6[1] |  fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid6_sel[3] &  fprs_tid6[1]                    ) ;  // hold

assign din_fprs_tid6[2] =  // enable fp (POR value is 1'b1)
  ~(( fprs_tid6_sel[0] &  rng_data_2f_b7_0[2]) |    // ASR FPRS write
    (~fprs_tid6_sel[0] &  fprs_tid6[2]       )  );  // hold

fgu_fac_ctl_msff_ctl_macro__width_3 fprstid6  (				// FS:wmr_protect
  .scan_in(fprstid6_wmr_scanin),
  .scan_out(fprstid6_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din (din_fprs_tid6[2:0]),
  .dout({fprs_tid6_[2], fprs_tid6[1:0]}),
  .soclk(soclk)
  );

assign  fprs_tid6[2] = ~fprs_tid6_[2];

// ----------
// FPRS tid7
// ----------

assign  fprs_tid7_sel[0] =  rng_wr_fprs_3f   & (rng_wr_tid_3f[2:0] == 3'd7);  // ASR FPRS write
assign  fprs_tid7_sel[1] = |fprs_w1_vld[1:0] & (fprs_w1_tid[2:0]   == 3'd7);  // FRF w1   write
assign  fprs_tid7_sel[2] = |fprs_w2_vld[1:0] & (fprs_w2_tid[2:0]   == 3'd7);  // FRF w2   write
assign  fprs_tid7_sel[3] = ~(|fprs_tid7_sel[2:0]);                            // hold

assign din_fprs_tid7[0] =  // dirty lower
  ( fprs_tid7_sel[0] &  rng_data_2f_b7_0[0]             ) |  // ASR FPRS write
  ( fprs_tid7_sel[1] & (fprs_tid7[0] | ~fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid7_sel[2] & (fprs_tid7[0] | ~fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid7_sel[3] &  fprs_tid7[0]                    ) ;  // hold

assign din_fprs_tid7[1] =  // dirty upper
  ( fprs_tid7_sel[0] &  rng_data_2f_b7_0[1]             ) |  // ASR FPRS write
  ( fprs_tid7_sel[1] & (fprs_tid7[1] |  fprs_w1_addr[4])) |  // FRF w1   write
  ( fprs_tid7_sel[2] & (fprs_tid7[1] |  fprs_w2_addr[4])) |  // FRF w2   write
  ( fprs_tid7_sel[3] &  fprs_tid7[1]                    ) ;  // hold

assign din_fprs_tid7[2] =  // enable fp (POR value is 1'b1)
  ~(( fprs_tid7_sel[0] &  rng_data_2f_b7_0[2]) |    // ASR FPRS write
    (~fprs_tid7_sel[0] &  fprs_tid7[2]       )  );  // hold

fgu_fac_ctl_msff_ctl_macro__width_3 fprstid7  (				// FS:wmr_protect
  .scan_in(fprstid7_wmr_scanin),
  .scan_out(fprstid7_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din (din_fprs_tid7[2:0]),
  .dout({fprs_tid7_[2], fprs_tid7[1:0]}),
  .soclk(soclk)
  );

assign  fprs_tid7[2] = ~fprs_tid7_[2];

assign  fgu_fprs_fef[7:0] =
  {fprs_tid7[2],
   fprs_tid6[2],
   fprs_tid5[2],
   fprs_tid4[2],
   fprs_tid3[2],
   fprs_tid2[2],
   fprs_tid1[2],
   fprs_tid0[2]};

// ----------
// ASR FPRS read data
// ----------

assign  din_rng_fprs[2:0] =
  ({3{(rng_wr_tid_3f[2:0] == 3'd0)}} & fprs_tid0[2:0]) |
  ({3{(rng_wr_tid_3f[2:0] == 3'd1)}} & fprs_tid1[2:0]) |
  ({3{(rng_wr_tid_3f[2:0] == 3'd2)}} & fprs_tid2[2:0]) |
  ({3{(rng_wr_tid_3f[2:0] == 3'd3)}} & fprs_tid3[2:0]) |
  ({3{(rng_wr_tid_3f[2:0] == 3'd4)}} & fprs_tid4[2:0]) |
  ({3{(rng_wr_tid_3f[2:0] == 3'd5)}} & fprs_tid5[2:0]) |
  ({3{(rng_wr_tid_3f[2:0] == 3'd6)}} & fprs_tid6[2:0]) |
  ({3{(rng_wr_tid_3f[2:0] == 3'd7)}} & fprs_tid7[2:0]) ;

fgu_fac_ctl_msff_ctl_macro__width_3 fprs_rng  (
  .scan_in(fprs_rng_scanin),
  .scan_out(fprs_rng_scanout),
  .l1clk(l1clk_pm1),
  .din (din_rng_fprs[2:0]),
  .dout(fac_rng_fprs[2:0]),
  .siclk(siclk),
  .soclk(soclk)
  );

// ----------------------------------------------------------------------------
//    FGU ASI local ring control - ASR GSR/FPRS access, ASI FRF ECC access
// ----------------------------------------------------------------------------
//
//
// ASI access should not happen for a given thread when there is a valid instr
// in the pipeline for that thread.
//
//   A packet is transmitted on the ring over 2 cycles. First cycle
//   carries control and address information. Second cycle carries data.
//   -Determinate write packets go through the pipe unmodified. The write data
//    is used by the unit.
//   -Determinate read packets have their data portion modified 
//    by the target unit.
//
//                    65-bit control/data bus output from the ring:
//                               64    - ctl/data
//                               63    - valid/hole
//                               62    - ack
//                               61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR   
//                               59    - rd/wr
//                               58:56 - Thread ID
//                               55:48 - ASI field
//                               47:0  - Virtual Address
//
////////////////////////////////////////////////////////////////////////////////
//
// PIPELINE STRUCTURE
//
//                                            rng_in_cdbus
//                                                 |
//                                                 |
//                                           -------------    
//                                          | stage1 reg  |   
//                                           -------------    
//                                                 |        
//                         ------------------------|---------> Store Data
//                         |                       v          
//                         |                 -------------  
//                         |                |    Decode   | 
//                         |                |             | ---------> Load request           
//                         |                |             | 
//                         |                 -------------  
//                         |                       |
//                         |                       |
//                         v                       v
//                 ---------------           -------------    
//                |stage2 data reg|        |stage2 ctl reg|   
//                 ---------------          ------------- 
//   load data             |                       |            
//       -------------     |                       |        
//indet load data     |    |                       |---------> Store control
//       ---------    |    |                       |          
//                |   |    |                       |
//                v   v    v                       |
//             ----------------                    |
//             \  input mux   /                    |
//              --------------    -----------------
//                    |          |
//                    |          |
//                    |          |
//                    v          v
//                  ----------------   
//                  \ data/ctl mux /   
//                   --------------    
//                          |            
//                          v            
//                    -------------      
//                   | stage3 reg  |     
//                    -------------       
//                          |            
//                          |
//                          v
//                    rng_out_cdbus
//
//////////////////////////////////////////////////////////////////////

`define FRF_ADDR  8'd73  // FRF ECC address
`define GSR_ADDR  8'd19  // GSR  address
`define FPRS_ADDR 8'd6   // FPRS address
`define ASI       2'b00
`define ASR       2'b01

// ------------------------------------
// STAGE 1
// ------------------------------------

// First cycle of the packet holds control and address information
// Second cycle holds the read/write data

// bit 64 indicates whether ctl packet or data packet
fgu_fac_ctl_msff_ctl_macro__width_25 rng_stg1  (
  .scan_in(rng_stg1_scanin),
  .scan_out(rng_stg1_scanout),
  .l1clk(l1clk_pm2),
  .din	({in_rngl_cdbus[64:48], in_rngl_cdbus[7:0]}),  // requires free running clk or rng_data_1f[63] en
  .dout	({rng_ctl_1f, rng_valid_1f, rng_data_1f[62:48], rng_data_1f_b7_0[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

// decode the packet for ASR GSR/FPRS read or ASI ECC read
assign  rng_rd_1f =
  rng_ctl_1f                   &  // ctl packet (not data)
  rng_valid_1f                 &  // valid
  ~rng_data_1f[62]             &  // ~ack
  rng_data_1f[59]              ;  // read (not write)

// decode the packet for ASR GSR/FPRS write
assign  rng_wr_1f =
  rng_ctl_1f                   &  // ctl packet (not data)
  rng_valid_1f                 &  // valid
  ~rng_data_1f[62]             &  // ~ack
  (rng_data_1f[61:60] == `ASR) &  // ASR
  ~rng_data_1f[59]             ;  // write (not read)

assign  rng_rd_gsr_1f  = rng_rd_1f & (rng_data_1f[61:60] == `ASR) & (rng_data_1f[55:48] == `GSR_ADDR );
assign  rng_wr_gsr_1f  = rng_wr_1f &                                (rng_data_1f[55:48] == `GSR_ADDR );
assign  rng_rd_fprs_1f = rng_rd_1f & (rng_data_1f[61:60] == `ASR) & (rng_data_1f[55:48] == `FPRS_ADDR);
assign  rng_wr_fprs_1f = rng_wr_1f &                                (rng_data_1f[55:48] == `FPRS_ADDR);
assign  rng_rd_ecc_1f  = rng_rd_1f & (rng_data_1f[61:60] == `ASI) & (rng_data_1f[55:48] == `FRF_ADDR );

assign  rng_rd_or_wr_1f =
  rng_rd_gsr_1f  | rng_wr_gsr_1f  |
  rng_rd_fprs_1f | rng_wr_fprs_1f |
  rng_rd_ecc_1f;

// 0in custom -fire ((rng_rd_or_wr_1f & div_engine_busy_e & (rng_data_1f[58:56]==div_tid_in_e[2:0])) | (rng_rd_or_wr_1f & (div_finish_fltd_fb | div_finish_flts_fb) & (rng_data_1f[58:56]==fac_fpd_tid_fb[2:0])) | (rng_rd_or_wr_1f & dec_fgu_valid_e & (rng_data_1f[58:56]==fac_tid_e[2:0])) | (rng_rd_or_wr_1f & fac_dec_valid_fx1 & (rng_data_1f[58:56]==tid_fx1[2:0])) | (rng_rd_or_wr_1f & dec_valid_fx2 & (rng_data_1f[58:56]==tid_fx2[2:0])) | (rng_rd_or_wr_1f & dec_valid_fx3 & (rng_data_1f[58:56]==tid_fx3[2:0])) | (rng_rd_or_wr_1f & (|fad_w1_vld_fw[1:0]) & (rng_data_1f[58:56]==fad_w1_tid_fw[2:0]))) -message "GSR or FPRS or FRF_ECC ASI collision with FPop"

// ------------------------------------
// STAGE 2
// ------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_17 rng_stg2  (
  .scan_in(rng_stg2_scanin),
  .scan_out(rng_stg2_scanout),
  .l1clk(l1clk_pm1),
  .din ({rng_data_1f[58:56],
         rng_wr_gsr_1f,
         rng_rd_or_wr_1f,
         rng_rd_gsr_1f,
         rng_rd_fprs_1f,
         rng_wr_fprs_1f,
         rng_rd_ecc_1f,
         rng_data_1f_b7_0[7:0]}),
  .dout({rng_wr_tid_2f[2:0],
         rng_wr_gsr_2f,
         rng_rd_or_wr_2f,
         rng_rd_gsr_2f,
         rng_rd_fprs_2f,
         rng_wr_fprs_2f,
         rng_rd_ecc_2f,
         rng_data_2f_b7_0[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fac_ctl_msff_ctl_macro__width_6 rng_6463  (
  .scan_in(rng_6463_scanin),
  .scan_out(rng_6463_scanout),
  .l1clk(l1clk_pm2),
  .din ({rng_ctl_1f,
         rng_valid_1f,
         rng_ctl_2f,
         rng_valid_2f,
             rng_ctl_3f,
             rng_cdbus_3f_b63}),
  .dout({rng_ctl_2f,                // requires free running clk
         rng_valid_2f,              // requires free running clk
         rng_ctl_3f,                // requires free running clk
         rng_valid_3f,              // requires free running clk
         fgu_rngl_cdbus_b64,        // requires free running clk
         fgu_rngl_cdbus_b63}),
  .siclk(siclk),
  .soclk(soclk)       // requires free running clk
  );

// ------------------------------------
// STAGE 3
// ------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_9 rng_stg3  (
  .scan_in(rng_stg3_scanin),
  .scan_out(rng_stg3_scanout),
  .l1clk(l1clk_pm1),
  .din ({rng_wr_tid_2f[2:0],
             rng_wr_gsr_2f,
             rng_rd_or_wr_2f,
         rng_rd_gsr_2f,
         rng_rd_fprs_2f,
         rng_wr_fprs_2f,
         rng_rd_ecc_2f}),
  .dout({rng_wr_tid_3f[2:0],
         fac_rng_wr_gsr_3f,
         fac_rng_rd_or_wr_3f,
         rng_rd_gsr_3f,
         rng_rd_fprs_3f,
         rng_wr_fprs_3f,
         rng_rd_ecc_3f}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  rng_b64_default_sel =
  ~fac_rng_rd_or_wr_3f &
  ~fac_rng_rd_gsr_4f   &
  ~fac_rng_rd_fprs_4f  &
  ~fac_rng_rd_ecc_4f   ;

assign  rng_cdbus_3f_b63 =
  (fac_rng_rd_or_wr_3f & rng_valid_3f            ) |
  (fac_rng_rd_gsr_4f   & fgd_gsr_asr_mask_fx4_b31) |
  (rng_b64_default_sel & rng_valid_3f            ) ;

// ------------------------------------
// STAGE 4
// ------------------------------------

fgu_fac_ctl_msff_ctl_macro__width_5 rng_stg4  (
  .scan_in(rng_stg4_scanin),
  .scan_out(rng_stg4_scanout),
  .l1clk(l1clk_pm1),
  .din ({    rng_rd_gsr_3f,
             rng_rd_fprs_3f,
             rng_rd_ecc_3f,
         fac_rng_rd_or_wr_3f,
         rng_rd_or_wr_4f}),
  .dout({fac_rng_rd_gsr_4f,
         fac_rng_rd_fprs_4f,
         fac_rng_rd_ecc_4f,
             rng_rd_or_wr_4f,
         rng_rd_or_wr_5f}),
  .siclk(siclk),
  .soclk(soclk)
  );


supply0 vss;
supply1 vdd;
// fixscan start:
assign spares_scanin             = scan_in                  ;
assign e_00_scanin               = spares_scanout           ;
assign e_01_scanin               = e_00_scanout             ;
assign e_02_scanin               = e_01_scanout             ;
assign e_03_scanin               = e_02_scanout             ;
assign fx1_00_scanin             = e_03_scanout             ;
assign fx1_01_scanin             = fx1_00_scanout           ;
assign fx1_02_scanin             = fx1_01_scanout           ;
assign fx2_00_scanin             = fx1_02_scanout           ;
assign fx2_01_scanin             = fx2_00_scanout           ;
assign fx2_02_scanin             = fx2_01_scanout           ;
assign fx3_00_scanin             = fx2_02_scanout           ;
assign fx3_01_scanin             = fx3_00_scanout           ;
assign fx4_00_scanin             = fx3_01_scanout           ;
assign fx5_00_scanin             = fx4_00_scanout           ;
assign fb_00_scanin              = fx5_00_scanout           ;
assign fw_00_scanin              = fb_00_scanout            ;
assign fw_01_scanin              = fw_00_scanout            ;
assign fprs_frf_ctl_scanin       = fw_01_scanout            ;
assign fprs_rng_scanin           = fprs_frf_ctl_scanout     ;
assign rng_stg1_scanin           = fprs_rng_scanout         ;
assign rng_stg2_scanin           = rng_stg1_scanout         ;
assign rng_6463_scanin           = rng_stg2_scanout         ;
assign rng_stg3_scanin           = rng_6463_scanout         ;
assign rng_stg4_scanin           = rng_stg3_scanout         ;
assign scan_out                  = rng_stg4_scanout         ;

assign fprstid0_wmr_scanin       = wmr_scan_in              ;
assign fprstid1_wmr_scanin       = fprstid0_wmr_scanout     ;
assign fprstid2_wmr_scanin       = fprstid1_wmr_scanout     ;
assign fprstid3_wmr_scanin       = fprstid2_wmr_scanout     ;
assign fprstid4_wmr_scanin       = fprstid3_wmr_scanout     ;
assign fprstid5_wmr_scanin       = fprstid4_wmr_scanout     ;
assign fprstid6_wmr_scanin       = fprstid5_wmr_scanout     ;
assign fprstid7_wmr_scanin       = fprstid6_wmr_scanout     ;
assign wmr_scan_out              = fprstid7_wmr_scanout     ;
// fixscan end:
endmodule  // fgu_fac_ctl


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module fgu_fac_ctl_spare_ctl_macro__num_5 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));
assign scan_out = so_4;


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_37 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [36:0] fdin;
wire [35:0] so;

  input [36:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [36:0] dout;
  output scan_out;
assign fdin[36:0] = din[36:0];


dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_17 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [16:0] fdin;
wire [15:0] so;

  input [16:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [16:0] dout;
  output scan_out;
assign fdin[16:0] = din[16:0];


dff #(17)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[16:0]),
.si({scan_in,so[15:0]}),
.so({so[15:0],scan_out}),
.q(dout[16:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_128 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [127:0] fdin;
wire [126:0] so;

  input [127:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [127:0] dout;
  output scan_out;
assign fdin[127:0] = din[127:0];


dff #(128)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[127:0]),
.si({scan_in,so[126:0]}),
.so({so[126:0],scan_out}),
.q(dout[127:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_21 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [20:0] fdin;
wire [19:0] so;

  input [20:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [20:0] dout;
  output scan_out;
assign fdin[20:0] = din[20:0];


dff #(21)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[20:0]),
.si({scan_in,so[19:0]}),
.so({so[19:0],scan_out}),
.q(dout[20:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_60 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [59:0] fdin;
wire [58:0] so;

  input [59:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [59:0] dout;
  output scan_out;
assign fdin[59:0] = din[59:0];


dff #(60)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[59:0]),
.si({scan_in,so[58:0]}),
.so({so[58:0],scan_out}),
.q(dout[59:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_52 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [51:0] fdin;
wire [50:0] so;

  input [51:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [51:0] dout;
  output scan_out;
assign fdin[51:0] = din[51:0];


dff #(52)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[51:0]),
.si({scan_in,so[50:0]}),
.so({so[50:0],scan_out}),
.q(dout[51:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_31 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [30:0] fdin;
wire [29:0] so;

  input [30:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [30:0] dout;
  output scan_out;
assign fdin[30:0] = din[30:0];


dff #(31)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[30:0]),
.si({scan_in,so[29:0]}),
.so({so[29:0],scan_out}),
.q(dout[30:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_26 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [25:0] fdin;
wire [24:0] so;

  input [25:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [25:0] dout;
  output scan_out;
assign fdin[25:0] = din[25:0];


dff #(26)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[25:0]),
.si({scan_in,so[24:0]}),
.so({so[24:0],scan_out}),
.q(dout[25:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_25 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [24:0] fdin;
wire [23:0] so;

  input [24:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [24:0] dout;
  output scan_out;
assign fdin[24:0] = din[24:0];


dff #(25)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[24:0]),
.si({scan_in,so[23:0]}),
.so({so[23:0],scan_out}),
.q(dout[24:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_53 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [52:0] fdin;
wire [51:0] so;

  input [52:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [52:0] dout;
  output scan_out;
assign fdin[52:0] = din[52:0];


dff #(53)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[52:0]),
.si({scan_in,so[51:0]}),
.so({so[51:0],scan_out}),
.q(dout[52:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fac_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fad_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fad_dp (
  dec_frf_r2_addr_d, 
  dec_frf_r1_32b_d, 
  dec_frf_r2_32b_d, 
  dec_frf_r1_odd32b_d, 
  dec_frf_r2_odd32b_d, 
  fgu_fld_fcc_fx3, 
  lsu_fgu_fld_data_b, 
  lsu_fgu_fld_addr_b, 
  lsu_fgu_fld_vld_w, 
  lsu_fgu_fld_b, 
  lsu_fgu_fld_tid_b, 
  lsu_fgu_fld_32b_b, 
  lsu_fgu_fld_odd32b_b, 
  lsu_fgu_fsr_load_b, 
  fgu_lsu_fst_data_fx1, 
  exu_fgu_rs1_e, 
  exu_fgu_rs2_e, 
  fac_frf_r1_addr_e, 
  fac_tid_e, 
  fac_aman_fmt_sel_e, 
  fac_bman_fmt_sel_e, 
  fac_fst_fmt_sel_fx1, 
  fac_exu_src_e, 
  fac_w1_addr_fb, 
  fac_fpd_addr_fb, 
  fac_w1_32b_fb, 
  fac_fpd_32b_fb, 
  fac_w1_odd32b_fb, 
  fac_fpd_odd32b_fb, 
  fac_w1_tid_fb, 
  fac_fpd_tid_fb, 
  fac_fsr0_sel_fw, 
  fac_fsr1_sel_fw, 
  fac_fsr2_sel_fw, 
  fac_fsr3_sel_fw, 
  fac_fsr4_sel_fw, 
  fac_fsr5_sel_fw, 
  fac_fsr6_sel_fw, 
  fac_fsr7_sel_fw, 
  main_clken, 
  asi_clken, 
  coreon_clken, 
  fad_w2_addr_fw1_b4, 
  fad_w2_tid_fw1, 
  fad_w2_vld_fw1, 
  fpc_w1_vld_fb, 
  fpc_w1_ul_vld_fb, 
  fpc_fsr_w1_result_fw, 
  fpc_fsr_w2_result_fw, 
  fpc_fpd_exp_res, 
  fpc_fpd_sign_res, 
  fpc_fpd_const_sel, 
  fpc_fcc_fw, 
  fpc_fpd_ieee_trap_fb, 
  fpc_fpd_unfin_fb, 
  fad_gsr_imirnd_fx1, 
  frf_r1_data_e, 
  frf_r2_data_e, 
  fad_w1_tid_fw, 
  fad_w1_vld_fw, 
  fad_w2_result_fw, 
  fad_w2_addr_fw, 
  fad_w2_tid_fw, 
  fad_w2_vld_fw, 
  fad_nombi_w2_result_fw, 
  fad_r1_byp_hit_fx1, 
  fad_r2_byp_hit_fx1, 
  fad_i_parity_2e_fx1, 
  fad_i_parity_2o_fx1, 
  fad_i_parity_1e_fx1, 
  fad_i_parity_1o_fx1, 
  fpf_w1_result_fb, 
  fad_rs1_fmt_fx1, 
  fad_rs2_fmt_fx1, 
  fad_rs1_fx1, 
  fad_rs2_fx1, 
  fad_r1_odd32b_fx1, 
  fad_fsr_rd_fx1, 
  fad_fsr_tem_fx1, 
  fad_fsr_ns_fx1, 
  fdd_result_rep0, 
  fdc_finish_fltd_early_rep0, 
  fdc_finish_flts_early_rep0, 
  fgd_rngl_cdbus_3f, 
  l2clk, 
  scan_in, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lb_scan_en_wmr, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_se_scancollar_out, 
  mbi_run, 
  mbi_frf_write_en, 
  fac_mbist_addr_1f, 
  fec_mbist_wdata_1f, 
  fec_mbist_wdata_3f, 
  fad_mbist_cmp64_fx1, 
  scan_out, 
  wmr_scan_out, 
  fgu_rngl_cdbus);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire e_01_scanin;
wire e_01_scanout;
wire [1:0] fpd_vld_fb;
wire r1_odd32b_e;
wire [4:0] r2_addr_e;
wire r1_byp_hit_e;
wire r2_byp_hit_e;
wire w2_32b_fw;
wire w2_odd32b_fw;
wire [3:0] w2_addr_fw1;
wire [1:0] fpd_vld_fw;
wire [4:0] w1_addr_fw;
wire w1_32b_fw;
wire w1_odd32b_fw;
wire w1_ul_vld_fw;
wire w2_32b_fw1;
wire w2_odd32b_fw1;
wire div_finish_flts_fb;
wire div_finish_fltd_fb;
wire mbist_run_1f;
wire mbist_frf_write_en_1f;
wire [4:0] aman_fmt_sel_fx1;
wire [4:0] bman_fmt_sel_fx1;
wire e_01_extra_scanin;
wire e_01_extra_scanout;
wire [4:0] w2_addr_fb;
wire [2:0] w2_tid_fb;
wire w2_32b_fb;
wire w2_odd32b_fb;
wire [1:0] pre_fld_vld_fb;
wire fld_fw;
wire r1_32b_e;
wire r2_32b_e;
wire r2_odd32b_e;
wire [4:0] w2_addr_fw;
wire [2:0] w2_tid_fw;
wire [1:0] pre_fld_vld_fw;
wire fld_fw1;
wire q2_r1_32b_e;
wire q2_r1_odd32b_e;
wire q3_r2_32b_e;
wire q3_r2_odd32b_e;
wire q6_r1_32b_e;
wire q6_r1_odd32b_e;
wire q7_r2_32b_e;
wire q7_r2_odd32b_e;
wire q8_r2_32b_e;
wire q8_r2_odd32b_e;
wire q9_r1_32b_e;
wire q9_r1_odd32b_e;
wire r1_w1_hit_fb;
wire r1_fld_hit_fb;
wire r1_w1_hit_fw;
wire r1_w2_hit_fw;
wire r1_w2_hit_fw1;
wire r2_w1_hit_fb;
wire r2_fld_hit_fb;
wire r2_w1_hit_fw;
wire r2_w2_hit_fw;
wire r2_w2_hit_fw1;
wire i1_r1_byp_hit_e;
wire i2_r1_byp_hit_e;
wire i1_r2_byp_hit_e;
wire i2_r2_byp_hit_e;
wire fx1_rs1byp_scanin;
wire fx1_rs1byp_scanout;
wire [63:0] w2_result_fw1;
wire [63:0] w1_result_fw;
wire fx1_rs2byp_scanin;
wire fx1_rs2byp_scanout;
wire [27:0] fsr0_fx1;
wire [11:0] fsr0_fttexc_merged_fw;
wire fx1_fsr0_wmr_scanin;
wire fx1_fsr0_wmr_scanout;
wire [27:0] ldfsr_data_fw;
wire [27:0] fsr1_fx1;
wire [11:0] fsr1_fttexc_merged_fw;
wire fx1_fsr1_wmr_scanin;
wire fx1_fsr1_wmr_scanout;
wire [27:0] fsr2_fx1;
wire [11:0] fsr2_fttexc_merged_fw;
wire fx1_fsr2_wmr_scanin;
wire fx1_fsr2_wmr_scanout;
wire [27:0] fsr3_fx1;
wire [11:0] fsr3_fttexc_merged_fw;
wire fx1_fsr3_wmr_scanin;
wire fx1_fsr3_wmr_scanout;
wire [27:0] fsr4_fx1;
wire [11:0] fsr4_fttexc_merged_fw;
wire fx1_fsr4_wmr_scanin;
wire fx1_fsr4_wmr_scanout;
wire [27:0] fsr5_fx1;
wire [11:0] fsr5_fttexc_merged_fw;
wire fx1_fsr5_wmr_scanin;
wire fx1_fsr5_wmr_scanout;
wire [27:0] fsr6_fx1;
wire [11:0] fsr6_fttexc_merged_fw;
wire fx1_fsr6_wmr_scanin;
wire fx1_fsr6_wmr_scanout;
wire [27:0] fsr7_fx1;
wire [11:0] fsr7_fttexc_merged_fw;
wire fx1_fsr7_wmr_scanin;
wire fx1_fsr7_wmr_scanout;
wire flop_rng1_4f_scanin;
wire flop_rng1_4f_scanout;
wire [62:0] rngl_cdbus_4f;
wire flop_rng0_4f_scanin;
wire flop_rng0_4f_scanout;
wire fx1_fsr_scanin;
wire fx1_fsr_scanout;
wire [1:0] fsr_ftt_fx1;
wire [4:0] fsr_aexc_fx1;
wire [4:0] fsr_cexc_fx1;
wire [1:0] fsr_fcc3_fx1;
wire [1:0] fsr_fcc2_fx1;
wire [1:0] fsr_fcc1_fx1;
wire [1:0] fsr_fcc0_fx1;
wire [63:0] rs1_fmt_fx1;
wire [63:0] rs2_fmt_fx1;
wire [63:0] fst_data_fx1;
wire [1:0] pre_fpd_vld_fb;
wire fpd_trap_fb;
wire lsu_fgu_fld_32b_b_;
wire lsu_fgu_fld_odd32b_b_;
wire lsu_fgu_fsr_load_b_;
wire fpd_trap_fb_;
wire fac_fpd_odd32b_fb_;
wire fld_w2_even_en_fb;
wire fld_w2_odd_en_fb;
wire mbist_run_1f_;
wire div_finish_flts_even_fb;
wire div_finish_flts_odd_fb;
wire fpd_vld_odd32b_fb;
wire [62:11] q_fdd_result_rep0;
wire [63:0] w2_result_fb;
wire fw_w2data_scanin;
wire fw_w2data_scanout;
wire fw_w1_scanin;
wire fw_w1_scanout;
wire fw_ldfsr_scanin;
wire fw_ldfsr_scanout;
wire [2:0] i_w2_tid_fw;
wire [4:0] i_w2_addr_fw;
wire fw1_w2data_scanin;
wire fw1_w2data_scanout;


// ----------------------------------------------------------------------------
// Interface with DEC
// ----------------------------------------------------------------------------

input    [4:0] dec_frf_r2_addr_d;
input          dec_frf_r1_32b_d;
input          dec_frf_r2_32b_d;
input          dec_frf_r1_odd32b_d;
input          dec_frf_r2_odd32b_d;

output   [7:0] fgu_fld_fcc_fx3;        // ldfsr fcc data {fcc3[1:0], fcc2[1:0], fcc1[1:0], fcc0[1:0]}

// ----------------------------------------------------------------------------
// Interface with LSU
// ----------------------------------------------------------------------------

input   [63:0] lsu_fgu_fld_data_b;
input    [4:0] lsu_fgu_fld_addr_b;
input          lsu_fgu_fld_vld_w;
input          lsu_fgu_fld_b;
input    [2:0] lsu_fgu_fld_tid_b;
input          lsu_fgu_fld_32b_b;
input          lsu_fgu_fld_odd32b_b;
input          lsu_fgu_fsr_load_b;

output  [63:0] fgu_lsu_fst_data_fx1;

// ----------------------------------------------------------------------------
// Interface with EXU
// ----------------------------------------------------------------------------

input   [63:0] exu_fgu_rs1_e;
input   [63:0] exu_fgu_rs2_e;

// ----------------------------------------------------------------------------
// Interface with FAC
// ----------------------------------------------------------------------------

input    [4:0] fac_frf_r1_addr_e;
input    [2:0] fac_tid_e;
input    [4:0] fac_aman_fmt_sel_e;     // aop mantissa format mux select
input    [4:0] fac_bman_fmt_sel_e;     // bop mantissa format mux select
input    [3:0] fac_fst_fmt_sel_fx1;    // store format mux select
input          fac_exu_src_e;

input    [4:0] fac_w1_addr_fb;         // FRF w1 write addr
input    [4:0] fac_fpd_addr_fb;        // FRF w2 write addr (div/sqrt)
input          fac_w1_32b_fb;          // FRF w1 is 32-bit dest
input          fac_fpd_32b_fb;         // FRF w2 is 32-bit dest (div/sqrt)
input          fac_w1_odd32b_fb;       // FRF w1 is odd 32-bit dest (32 LSBs)
input          fac_fpd_odd32b_fb;      // FRF w2 is odd 32-bit dest (32 LSBs) (div/sqrt)

input    [2:0] fac_w1_tid_fb;          // FRF w1 TID
input    [2:0] fac_fpd_tid_fb;         // FRF w2 TID (div/sqrt)

input    [5:0] fac_fsr0_sel_fw;
input    [5:0] fac_fsr1_sel_fw;
input    [5:0] fac_fsr2_sel_fw;
input    [5:0] fac_fsr3_sel_fw;
input    [5:0] fac_fsr4_sel_fw;
input    [5:0] fac_fsr5_sel_fw;
input    [5:0] fac_fsr6_sel_fw;
input    [5:0] fac_fsr7_sel_fw;

input          main_clken;             // main clken
input          asi_clken;              // asi clken: controls ASI ring stage flops in fgd/fad
input          coreon_clken;           // controls all "free running" flops

output         fad_w2_addr_fw1_b4;     // FRF w2 write addr (LSU->FRF path,
output   [2:0] fad_w2_tid_fw1;         // FRF w2 write TID   delayed to fw1)
output   [1:0] fad_w2_vld_fw1;         // FRF w2 write valid (qualified)

// ----------------------------------------------------------------------------
// Interface with FPC
// ----------------------------------------------------------------------------

input    [1:0] fpc_w1_vld_fb;          // FRF w1 write valid (qualified),            [63:32],[31:0]
input          fpc_w1_ul_vld_fb;       // FRF w1 write valid (qualified),            upper or lower
input   [11:0] fpc_fsr_w1_result_fw;   // FSR w1 write data  {ftt,aexc,cexc}
input   [11:0] fpc_fsr_w2_result_fw;   // FSR w2 write data  {ftt,aexc,cexc}
input   [10:0] fpc_fpd_exp_res;        // FPD exponent result
input          fpc_fpd_sign_res;       // FPD sign result
input    [1:0] fpc_fpd_const_sel;      // 10=ones frac, 01=fdd frac, 00=zero frac
input    [1:0] fpc_fcc_fw;
input          fpc_fpd_ieee_trap_fb;
input          fpc_fpd_unfin_fb;

// ----------------------------------------------------------------------------
// Interface with FSD
// ----------------------------------------------------------------------------

output   [2:0] fad_gsr_imirnd_fx1;     // {GSR.im,GSR.irnd[1:0]}

// ----------------------------------------------------------------------------
// Interface with FRF
// ----------------------------------------------------------------------------

input   [63:0] frf_r1_data_e;          // FRF rs1 read data
input   [63:0] frf_r2_data_e;          // FRF rs2 read data

output   [2:0] fad_w1_tid_fw;          // FRF w1 write TID
output   [1:0] fad_w1_vld_fw;          // FRF w1 write valid (qualified)

output  [63:0] fad_w2_result_fw;       // FRF w2 write data for FRF 
output   [4:0] fad_w2_addr_fw;         // FRF w2 write addr
output   [2:0] fad_w2_tid_fw;          // FRF w2 write TID    (LSU->FRF path,
output   [1:0] fad_w2_vld_fw;          // FRF w2 write valid   delayed to fw)

// ----------------------------------------------------------------------------
// Interface with FEC
// ----------------------------------------------------------------------------

output  [63:0] fad_nombi_w2_result_fw; // FRF w2 write data w/out mbist data muxed in
output         fad_r1_byp_hit_fx1;     // r1 is bypass data
output         fad_r2_byp_hit_fx1;     // r2 is bypass data
output         fad_i_parity_2e_fx1;    // partial ECC check (parity portion), rs2 even
output         fad_i_parity_2o_fx1;    // partial ECC check (parity portion), rs2 odd
output         fad_i_parity_1e_fx1;    // partial ECC check (parity portion), rs1 even
output         fad_i_parity_1o_fx1;    // partial ECC check (parity portion), rs1 odd

// ----------------------------------------------------------------------------
// Interface with FPF
// ----------------------------------------------------------------------------

input   [63:0] fpf_w1_result_fb;       // FPX result
output  [63:0] fad_rs1_fmt_fx1;        // rs1 formatted
output  [63:0] fad_rs2_fmt_fx1;        // rs2 formatted
output  [63:0] fad_rs1_fx1;            // rs1 unformatted
output  [63:0] fad_rs2_fx1;            // rs2 unformatted
output         fad_r1_odd32b_fx1;

output   [1:0] fad_fsr_rd_fx1;
output   [4:0] fad_fsr_tem_fx1;
output         fad_fsr_ns_fx1;

// ----------------------------------------------------------------------------
// Interface with FDD
// ----------------------------------------------------------------------------

input  [62:11] fdd_result_rep0;        // FDD result

// ----------------------------------------------------------------------------
// Interface with FDC
// ----------------------------------------------------------------------------

input 	       fdc_finish_fltd_early_rep0;
input 	       fdc_finish_flts_early_rep0;

// ----------------------------------------------------------------------------
// Interface with FGD
// ----------------------------------------------------------------------------

input   [62:0] fgd_rngl_cdbus_3f;

// ----------------------------------------------------------------------------
// Global Signals
// ----------------------------------------------------------------------------

input          l2clk;                  // clock input
input	       scan_in;
input          spc_aclk_wmr;
input          wmr_scan_in;
input          lb_scan_en_wmr;
input	       tcu_pce_ov;	       // scan signals
input	       spc_aclk;
input	       spc_bclk;
input	       tcu_scan_en;
input          tcu_se_scancollar_out;
input          mbi_run;                // MBIST
input          mbi_frf_write_en;       // MBIST
input    [7:0] fac_mbist_addr_1f;      // MBIST
input    [7:0] fec_mbist_wdata_1f;     // MBIST
input    [7:0] fec_mbist_wdata_3f;     // MBIST

output         fad_mbist_cmp64_fx1;    // MBIST
output	       scan_out;
output         wmr_scan_out;
output  [62:0] fgu_rngl_cdbus;         // ASI local ring

// scan renames
assign stop   = 1'b0;
// end scan

fgu_fad_dp_buff_macro__dbuff_32x__rep_1__width_4 test_rep0  (
  .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}),
  .dout({se,          pce_ov,     siclk,    soclk   })
  );


// ----------------------------------------------------------------------------
//                               E stage
// ----------------------------------------------------------------------------

fgu_fad_dp_msff_macro__width_47 e_01  (
  .scan_in(e_01_scanin),
  .scan_out(e_01_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din ({fad_w2_vld_fw[1:0],
         fad_w2_addr_fw[3:0],
         fpd_vld_fb[1:0],
         fac_w1_addr_fb[4:0],
         fac_w1_32b_fb,
         fac_w1_odd32b_fb,
         fac_w1_tid_fb[2:0],
         fpc_w1_vld_fb[1:0],
         fpc_w1_ul_vld_fb,
         r1_odd32b_e,
         r2_addr_e[1:0], 
         r2_addr_e[4],
         r1_byp_hit_e,
         r2_byp_hit_e,
         fad_w2_addr_fw[4],
         fad_w2_tid_fw[2:0],
             w2_32b_fw,
             w2_odd32b_fw,
         fdc_finish_flts_early_rep0,
         fdc_finish_fltd_early_rep0,
         mbi_run,
         mbi_frf_write_en,
         fac_aman_fmt_sel_e[4:0],
         fac_bman_fmt_sel_e[4:0]}),
  .dout({fad_w2_vld_fw1[1:0],
             w2_addr_fw1[3:0],
         fpd_vld_fw[1:0],
             w1_addr_fw[4:0],
             w1_32b_fw,
             w1_odd32b_fw,
         fad_w1_tid_fw[2:0],
         fad_w1_vld_fw[1:0],
             w1_ul_vld_fw,
         fad_r1_odd32b_fx1,
         fad_gsr_imirnd_fx1[2:0],
         fad_r1_byp_hit_fx1,
         fad_r2_byp_hit_fx1,
         fad_w2_addr_fw1_b4,
         fad_w2_tid_fw1[2:0],
             w2_32b_fw1,
             w2_odd32b_fw1,
         div_finish_flts_fb,
         div_finish_fltd_fb,
         mbist_run_1f,
         mbist_frf_write_en_1f,
             aman_fmt_sel_fx1[4:0],
             bman_fmt_sel_fx1[4:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fad_dp_msff_macro__width_23 e_01_extra  (
  .scan_in(e_01_extra_scanin),
  .scan_out(e_01_extra_scanout),
  .clk (l2clk),
  .en  (coreon_clken),
  .din ({dec_frf_r2_addr_d[4:0],  // requires free running clk or dec_fgu_decode_d en
         dec_frf_r1_32b_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_r2_32b_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_r1_odd32b_d,     // requires free running clk or dec_fgu_decode_d en
         dec_frf_r2_odd32b_d,     // requires free running clk or dec_fgu_decode_d en
         w2_addr_fb[4:0],         // requires free running clk
         w2_tid_fb[2:0],          // requires free running clk
         w2_32b_fb,               // requires free running clk
         w2_odd32b_fb,            // requires free running clk
         pre_fld_vld_fb[1:0],     // requires free running clk
         lsu_fgu_fld_b,           // requires free running clk
         fld_fw}),                // requires free running clk
  .dout({        r2_addr_e[4:0],
                 r1_32b_e,
                 r2_32b_e,
                 r1_odd32b_e,
                 r2_odd32b_e,
         w2_addr_fw[4:0],
         w2_tid_fw[2:0],
         w2_32b_fw,
         w2_odd32b_fw,
         pre_fld_vld_fw[1:0],
                 fld_fw,
         fld_fw1}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// Bypass detection
//
// ten compares total:
// r1_e == w1_fb
// r1_e == fld_fb
// r1_e == w1_fw
// r1_e == w2_fw
// r1_e == w2_fw1
// r2_e == w1_fb
// r2_e == fld_fb
// r2_e == w1_fw
// r2_e == w2_fw
// r2_e == w2_fw1
// ------------------------------------

// SP->DP bypass is not supported (evil-twin)
// DP->SP bypass is supported only for a DP load bypassing to a SP arith.
//        DP arith. bypassing to SP arith. isn't supported due to IFU considerations.
//
// If 64b result and 32b source then "32b" and "odd32b" signals are don't care,
// force the source "32b" and "odd32b" signals to zero to match the 64b result's
// "32b" and "odd32b" signals

fgu_fad_dp_and_macro__ports_2__width_2 and_q2  (
  .din0({lsu_fgu_fld_32b_b, lsu_fgu_fld_32b_b}),
  .din1({   r1_32b_e,          r1_odd32b_e   }),
  .dout({q2_r1_32b_e,       q2_r1_odd32b_e   })
  );

fgu_fad_dp_and_macro__ports_2__width_2 and_q3  (
  .din0({lsu_fgu_fld_32b_b, lsu_fgu_fld_32b_b}),
  .din1({   r2_32b_e,          r2_odd32b_e   }),
  .dout({q3_r2_32b_e,       q3_r2_odd32b_e   })
  );

fgu_fad_dp_and_macro__ports_2__width_2 and_q6  (
  .din0({w2_32b_fw,   w2_32b_fw     }),
  .din1({   r1_32b_e,    r1_odd32b_e}),
  .dout({q6_r1_32b_e, q6_r1_odd32b_e})
  );

fgu_fad_dp_and_macro__ports_2__width_2 and_q7  (
  .din0({w2_32b_fw,   w2_32b_fw     }),
  .din1({   r2_32b_e,    r2_odd32b_e}),
  .dout({q7_r2_32b_e, q7_r2_odd32b_e})
  );

fgu_fad_dp_and_macro__ports_2__width_2 and_q8  (
  .din0({w2_32b_fw1,   w2_32b_fw1     }),
  .din1({   r2_32b_e,    r2_odd32b_e}),
  .dout({q8_r2_32b_e, q8_r2_odd32b_e})
  );

fgu_fad_dp_and_macro__ports_2__width_2 and_q9  (
  .din0({w2_32b_fw1,   w2_32b_fw1     }),
  .din1({   r1_32b_e,    r1_odd32b_e}),
  .dout({q9_r1_32b_e, q9_r1_odd32b_e})
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r1a  (
  .din0({fac_frf_r1_addr_e[4:0],
         fac_tid_e[2:0],
         r1_32b_e,
         r1_odd32b_e,
         1'b1,
         mbist_run_1f}),
  .din1({fac_w1_addr_fb[4:0],
         fac_w1_tid_fb[2:0],
         fac_w1_32b_fb,
         fac_w1_odd32b_fb,
         fpc_w1_ul_vld_fb,
         1'b0}),
  .dout(r1_w1_hit_fb)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r1b  (
  .din0({fac_frf_r1_addr_e[4:0],
         fac_tid_e[2:0],
         q2_r1_32b_e,
         q2_r1_odd32b_e,
         1'b1,
         mbist_run_1f}),
  .din1({lsu_fgu_fld_addr_b[4:0],
         lsu_fgu_fld_tid_b[2:0],
         lsu_fgu_fld_32b_b,
         lsu_fgu_fld_odd32b_b,
         lsu_fgu_fld_b,  // load fsr is serializing, can't cause a fld_hit
         1'b0}),
  .dout(r1_fld_hit_fb)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r1c  (
  .din0({fac_frf_r1_addr_e[4:0],
         fac_tid_e[2:0],
         r1_32b_e,
         r1_odd32b_e,
         1'b1,
         mbist_run_1f}),
  .din1({w1_addr_fw[4:0],
         fad_w1_tid_fw[2:0],
         w1_32b_fw,
         w1_odd32b_fw,
         w1_ul_vld_fw,
         1'b0}),
  .dout(r1_w1_hit_fw)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r1d  (
  .din0({fac_frf_r1_addr_e[4:0],
         fac_tid_e[2:0],
         q6_r1_32b_e,
         q6_r1_odd32b_e,
         1'b1,
         mbist_run_1f}),
  .din1({fad_w2_addr_fw[4:0],
         fad_w2_tid_fw[2:0],
         w2_32b_fw,
         w2_odd32b_fw,
         fld_fw,   // load fsr is serializing, can't cause a fld_hit
         1'b0}),
  .dout(r1_w2_hit_fw)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r1e  (
  .din0({fac_frf_r1_addr_e[4:0],
         fac_tid_e[2:0],
         q9_r1_32b_e,
         q9_r1_odd32b_e,
         1'b1,
         mbist_run_1f}),
  .din1({fad_w2_addr_fw1_b4, w2_addr_fw1[3:0],
         fad_w2_tid_fw1[2:0],
         w2_32b_fw1,
         w2_odd32b_fw1,
         fld_fw1,  // load fsr is serializing, can't cause a fld_hit
         1'b0}),
  .dout(r1_w2_hit_fw1)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r2a  (
  .din0({r2_addr_e[4:0],
         fac_tid_e[2:0],
         r2_32b_e,
         r2_odd32b_e,
         1'b1,
         1'b0}),
  .din1({fac_w1_addr_fb[4:0],
         fac_w1_tid_fb[2:0],
         fac_w1_32b_fb,
         fac_w1_odd32b_fb,
         fpc_w1_ul_vld_fb,
         1'b0}),
  .dout(r2_w1_hit_fb)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r2b  (
  .din0({r2_addr_e[4:0],
         fac_tid_e[2:0],
         q3_r2_32b_e,
         q3_r2_odd32b_e,
         1'b1,
         1'b0}),
  .din1({lsu_fgu_fld_addr_b[4:0],
         lsu_fgu_fld_tid_b[2:0],
         lsu_fgu_fld_32b_b,
         lsu_fgu_fld_odd32b_b,
         lsu_fgu_fld_b,  // load fsr is serializing, can't cause a fld_hit
         1'b0}),
  .dout(r2_fld_hit_fb)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r2c  (
  .din0({r2_addr_e[4:0],
         fac_tid_e[2:0],
         r2_32b_e,
         r2_odd32b_e,
         1'b1,
         1'b0}),
  .din1({w1_addr_fw[4:0],
         fad_w1_tid_fw[2:0],
         w1_32b_fw,
         w1_odd32b_fw,
         w1_ul_vld_fw,
         1'b0}),
  .dout(r2_w1_hit_fw)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r2d  (
  .din0({r2_addr_e[4:0],
         fac_tid_e[2:0],
         q7_r2_32b_e,
         q7_r2_odd32b_e,
         1'b1,
         1'b0}),
  .din1({fad_w2_addr_fw[4:0],
         fad_w2_tid_fw[2:0],
         w2_32b_fw,
         w2_odd32b_fw,
         fld_fw,   // load fsr is serializing, can't cause a fld_hit
         1'b0}),
  .dout(r2_w2_hit_fw)
  );

fgu_fad_dp_cmp_macro__width_12 cmp_r2e  (
  .din0({r2_addr_e[4:0],
         fac_tid_e[2:0],
         q8_r2_32b_e,
         q8_r2_odd32b_e,
         1'b1,
         1'b0}),
  .din1({fad_w2_addr_fw1_b4, w2_addr_fw1[3:0],
         fad_w2_tid_fw1[2:0],
         w2_32b_fw1,
         w2_odd32b_fw1,
         fld_fw1,  // load fsr is serializing, can't cause a fld_hit
         1'b0}),
  .dout(r2_w2_hit_fw1)
  );

fgu_fad_dp_nor_macro__ports_3__width_4 rs_vld0  (
  .din0({r1_fld_hit_fb,   r1_w2_hit_fw1,   r2_fld_hit_fb,   r2_w2_hit_fw1  }),
  .din1({r1_w1_hit_fb,    r1_w1_hit_fw,    r2_w1_hit_fb,    r2_w1_hit_fw   }),
  .din2({r1_w2_hit_fw,    1'b0,            r2_w2_hit_fw,    1'b0           }),
  .dout({i1_r1_byp_hit_e, i2_r1_byp_hit_e, i1_r2_byp_hit_e, i2_r2_byp_hit_e})
  );

fgu_fad_dp_nand_macro__ports_2__width_2 rs_vld1  (
  .din0({i1_r1_byp_hit_e, i1_r2_byp_hit_e}),
  .din1({i2_r1_byp_hit_e, i2_r2_byp_hit_e}),
  .dout({r1_byp_hit_e,    r2_byp_hit_e   })
  );

// ------------------------------------
// Bypass muxes
// ------------------------------------

fgu_fad_dp_msff_macro__dmux_4x__mux_aope__ports_7__width_64 fx1_rs1byp  (
  .scan_in(fx1_rs1byp_scanin),
  .scan_out(fx1_rs1byp_scanout),
  .se  (tcu_se_scancollar_out),
  .clk (l2clk),
  .en  (main_clken),
  .din0(exu_fgu_rs1_e[63:0]),
  .din1(lsu_fgu_fld_data_b[63:0]),
  .din2(fpf_w1_result_fb[63:0]),
  .din3(fad_nombi_w2_result_fw[63:0]),
  .din4(w2_result_fw1[63:0]),
  .din5(w1_result_fw[63:0]),
  .din6(frf_r1_data_e[63:0]),  // functional or MBIST read data
  .sel0(fac_exu_src_e),
  .sel1(r1_fld_hit_fb),
  .sel2(r1_w1_hit_fb),
  .sel3(r1_w2_hit_fw),
  .sel4(r1_w2_hit_fw1),
  .sel5(r1_w1_hit_fw),
  .dout(fad_rs1_fx1[63:0]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fad_dp_cmp_macro__width_64 cmp_mbist  (
  .din0({8{fec_mbist_wdata_3f[7:0]}}),
  .din1(fad_rs1_fx1[63:0]),
  .dout(fad_mbist_cmp64_fx1)
  );

fgu_fad_dp_msff_macro__dmux_4x__mux_aope__ports_7__width_64 fx1_rs2byp  (
  .scan_in(fx1_rs2byp_scanin),
  .scan_out(fx1_rs2byp_scanout),
  .se  (tcu_se_scancollar_out),
  .clk (l2clk),
  .en  (main_clken),
  .din0(exu_fgu_rs2_e[63:0]),
  .din1(lsu_fgu_fld_data_b[63:0]),
  .din2(fpf_w1_result_fb[63:0]),
  .din3(fad_nombi_w2_result_fw[63:0]),
  .din4(w2_result_fw1[63:0]),
  .din5(w1_result_fw[63:0]),
  .din6(frf_r2_data_e[63:0]),
  .sel0(fac_exu_src_e),
  .sel1(r2_fld_hit_fb),
  .sel2(r2_w1_hit_fb),
  .sel3(r2_w2_hit_fw),
  .sel4(r2_w2_hit_fw1),
  .sel5(r2_w1_hit_fw),
  .dout(fad_rs2_fx1[63:0]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// Begin ECC check for rs1/rs2 here, complete it in FEC
// ------------------------------------

fgu_fad_dp_prty_macro__width_32 ecc_parity_2e  (
  .din (fad_rs2_fx1[63:32]),
  .dout(fad_i_parity_2e_fx1)
  );

fgu_fad_dp_prty_macro__width_32 ecc_parity_2o  (
  .din (fad_rs2_fx1[31:0]),
  .dout(fad_i_parity_2o_fx1)
  );

fgu_fad_dp_prty_macro__width_32 ecc_parity_1e  (
  .din (fad_rs1_fx1[63:32]),
  .dout(fad_i_parity_1e_fx1)
  );

fgu_fad_dp_prty_macro__width_32 ecc_parity_1o  (
  .din (fad_rs1_fx1[31:0]),
  .dout(fad_i_parity_1o_fx1)
  );

// ------------------------------------
// FSR w1,w2,hold mux/flop, threads 0-7
// ------------------------------------

// ----------
// FSR tid0
// ----------

fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr0_in  (
  .din0(fpc_fsr_w1_result_fw[11:0]),     // w1         {ftt,aexc,cexc}
  .din1(fpc_fsr_w2_result_fw[11:0]),     // fdiv/fsqrt {ftt,aexc,cexc}
  .din2({2'b0, fsr0_fx1[17:13], 5'b0}),  // accrued aexc
  .sel0(fac_fsr0_sel_fw[4]),
  .sel1(fac_fsr0_sel_fw[5]),
  .sel2(1'b1),
  .dout(fsr0_fttexc_merged_fw[11:0])
  );

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr0  (	// FS:wmr_protect
  .scan_in(fx1_fsr0_wmr_scanin),
  .scan_out(fx1_fsr0_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fac_fsr0_sel_fw[3]),
  .din0({ldfsr_data_fw[27:26],         // LDFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr0_fx1[19:18],              //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         fsr0_fx1[7:6],                //		fcc3
         fsr0_fx1[5:4],                //		fcc2
         fsr0_fx1[3:2],                //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din1({ldfsr_data_fw[27:26],         // LDXFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr0_fx1[19:18],	       //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         ldfsr_data_fw[7:6],           //		fcc3
         ldfsr_data_fw[5:4],           //		fcc2
         ldfsr_data_fw[3:2],           //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din2({fsr0_fx1[27:26],              // ST(X)FSR:	rd
         fsr0_fx1[25:21],	       //		tem
         fsr0_fx1[20],	               //		ns
         fsr0_fttexc_merged_fw[11:10], //		ftt
         fsr0_fx1[17:8],	       //		aexc,cexc
         fsr0_fx1[7:6],	               //		fcc3
         fsr0_fx1[5:4],	               //		fcc2
         fsr0_fx1[3:2],	               //		fcc1
         fsr0_fx1[1:0]}),	       //		fcc0
  .din3({fsr0_fx1[27:26],              // FCMP(E) fcc0: rd
         fsr0_fx1[25:21],              //		tem
         fsr0_fx1[20],		       //		ns
         fsr0_fttexc_merged_fw[11:10], //		ftt
         fsr0_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr0_fx1[7:6],		       //		fcc3
         fsr0_fx1[5:4],		       //		fcc2
         fsr0_fx1[3:2],		       //		fcc1
         fpc_fcc_fw[1:0]}),	       //		fcc0
  .din4({fsr0_fx1[27:26],              // FCMP(E) fcc1: rd
         fsr0_fx1[25:21],              //		tem
         fsr0_fx1[20],		       //		ns
         fsr0_fttexc_merged_fw[11:10], //		ftt
         fsr0_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr0_fx1[7:6],		       //		fcc3
         fsr0_fx1[5:4],	               //		fcc2
         fpc_fcc_fw[1:0],	       //		fcc1
         fsr0_fx1[1:0]}),              //		fcc0
  .din5({fsr0_fx1[27:26],              // FCMP(E) fcc2: rd
         fsr0_fx1[25:21],	       //		tem
         fsr0_fx1[20],		       //		ns
         fsr0_fttexc_merged_fw[11:10], //		ftt
         fsr0_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr0_fx1[7:6],		       //		fcc3
         fpc_fcc_fw[1:0],	       //		fcc2
         fsr0_fx1[3:2],	               //		fcc1
         fsr0_fx1[1:0]}),              //		fcc0
  .din6({fsr0_fx1[27:26],              // FCMP(E) fcc3: rd
         fsr0_fx1[25:21],	       //		tem
         fsr0_fx1[20],	               //		ns
         fsr0_fttexc_merged_fw[11:10], //		ftt
         fsr0_fttexc_merged_fw[9:0],   //		aexc,cexc
         fpc_fcc_fw[1:0],	       //		fcc3
         fsr0_fx1[5:4],		       //		fcc2
         fsr0_fx1[3:2],		       //		fcc1
         fsr0_fx1[1:0]}),              //		fcc0
  .din7({fsr0_fx1[27:26],              // other FPop:   rd
         fsr0_fx1[25:21],	       //		tem
         fsr0_fx1[20],		       //		ns
         fsr0_fttexc_merged_fw[11:10], //		ftt
         fsr0_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr0_fx1[7:6],                //		fcc3
         fsr0_fx1[5:4],		       //		fcc2
         fsr0_fx1[3:2],		       //		fcc1
         fsr0_fx1[1:0]}),              //		fcc0
  .sel (fac_fsr0_sel_fw[2:0]),
  .dout(fsr0_fx1[27:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------
// FSR tid1
// ----------

fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr1_in  (
  .din0(fpc_fsr_w1_result_fw[11:0]),     // w1         {ftt,aexc,cexc}
  .din1(fpc_fsr_w2_result_fw[11:0]),     // fdiv/fsqrt {ftt,aexc,cexc}
  .din2({2'b0, fsr1_fx1[17:13], 5'b0}),  // accrued aexc
  .sel0(fac_fsr1_sel_fw[4]),
  .sel1(fac_fsr1_sel_fw[5]),
  .sel2(1'b1),
  .dout(fsr1_fttexc_merged_fw[11:0])
  );

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr1  (	// FS:wmr_protect
  .scan_in(fx1_fsr1_wmr_scanin),
  .scan_out(fx1_fsr1_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fac_fsr1_sel_fw[3]),
  .din0({ldfsr_data_fw[27:26],         // LDFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr1_fx1[19:18],              //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         fsr1_fx1[7:6],                //		fcc3
         fsr1_fx1[5:4],                //		fcc2
         fsr1_fx1[3:2],                //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din1({ldfsr_data_fw[27:26],         // LDXFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr1_fx1[19:18],	       //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         ldfsr_data_fw[7:6],           //		fcc3
         ldfsr_data_fw[5:4],           //		fcc2
         ldfsr_data_fw[3:2],           //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din2({fsr1_fx1[27:26],              // ST(X)FSR:	rd
         fsr1_fx1[25:21],	       //		tem
         fsr1_fx1[20],	               //		ns
         fsr1_fttexc_merged_fw[11:10], //		ftt
         fsr1_fx1[17:8],	       //		aexc,cexc
         fsr1_fx1[7:6],	               //		fcc3
         fsr1_fx1[5:4],	               //		fcc2
         fsr1_fx1[3:2],	               //		fcc1
         fsr1_fx1[1:0]}),	       //		fcc0
  .din3({fsr1_fx1[27:26],              // FCMP(E) fcc0: rd
         fsr1_fx1[25:21],              //		tem
         fsr1_fx1[20],		       //		ns
         fsr1_fttexc_merged_fw[11:10], //		ftt
         fsr1_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr1_fx1[7:6],		       //		fcc3
         fsr1_fx1[5:4],		       //		fcc2
         fsr1_fx1[3:2],		       //		fcc1
         fpc_fcc_fw[1:0]}),	       //		fcc0
  .din4({fsr1_fx1[27:26],              // FCMP(E) fcc1: rd
         fsr1_fx1[25:21],              //		tem
         fsr1_fx1[20],		       //		ns
         fsr1_fttexc_merged_fw[11:10], //		ftt
         fsr1_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr1_fx1[7:6],		       //		fcc3
         fsr1_fx1[5:4],	               //		fcc2
         fpc_fcc_fw[1:0],	       //		fcc1
         fsr1_fx1[1:0]}),              //		fcc0
  .din5({fsr1_fx1[27:26],              // FCMP(E) fcc2: rd
         fsr1_fx1[25:21],	       //		tem
         fsr1_fx1[20],		       //		ns
         fsr1_fttexc_merged_fw[11:10], //		ftt
         fsr1_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr1_fx1[7:6],		       //		fcc3
         fpc_fcc_fw[1:0],	       //		fcc2
         fsr1_fx1[3:2],	               //		fcc1
         fsr1_fx1[1:0]}),              //		fcc0
  .din6({fsr1_fx1[27:26],              // FCMP(E) fcc3: rd
         fsr1_fx1[25:21],	       //		tem
         fsr1_fx1[20],	               //		ns
         fsr1_fttexc_merged_fw[11:10], //		ftt
         fsr1_fttexc_merged_fw[9:0],   //		aexc,cexc
         fpc_fcc_fw[1:0],	       //		fcc3
         fsr1_fx1[5:4],		       //		fcc2
         fsr1_fx1[3:2],		       //		fcc1
         fsr1_fx1[1:0]}),              //		fcc0
  .din7({fsr1_fx1[27:26],              // other FPop:   rd
         fsr1_fx1[25:21],	       //		tem
         fsr1_fx1[20],		       //		ns
         fsr1_fttexc_merged_fw[11:10], //		ftt
         fsr1_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr1_fx1[7:6],                //		fcc3
         fsr1_fx1[5:4],		       //		fcc2
         fsr1_fx1[3:2],		       //		fcc1
         fsr1_fx1[1:0]}),              //		fcc0
  .sel (fac_fsr1_sel_fw[2:0]),
  .dout(fsr1_fx1[27:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------
// FSR tid2
// ----------

fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr2_in  (
  .din0(fpc_fsr_w1_result_fw[11:0]),     // w1         {ftt,aexc,cexc}
  .din1(fpc_fsr_w2_result_fw[11:0]),     // fdiv/fsqrt {ftt,aexc,cexc}
  .din2({2'b0, fsr2_fx1[17:13], 5'b0}),  // accrued aexc
  .sel0(fac_fsr2_sel_fw[4]),
  .sel1(fac_fsr2_sel_fw[5]),
  .sel2(1'b1),
  .dout(fsr2_fttexc_merged_fw[11:0])
  );

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr2  (	// FS:wmr_protect
  .scan_in(fx1_fsr2_wmr_scanin),
  .scan_out(fx1_fsr2_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fac_fsr2_sel_fw[3]),
  .din0({ldfsr_data_fw[27:26],         // LDFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr2_fx1[19:18],              //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         fsr2_fx1[7:6],                //		fcc3
         fsr2_fx1[5:4],                //		fcc2
         fsr2_fx1[3:2],                //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din1({ldfsr_data_fw[27:26],         // LDXFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr2_fx1[19:18],	       //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         ldfsr_data_fw[7:6],           //		fcc3
         ldfsr_data_fw[5:4],           //		fcc2
         ldfsr_data_fw[3:2],           //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din2({fsr2_fx1[27:26],              // ST(X)FSR:	rd
         fsr2_fx1[25:21],	       //		tem
         fsr2_fx1[20],	               //		ns
         fsr2_fttexc_merged_fw[11:10], //		ftt
         fsr2_fx1[17:8],	       //		aexc,cexc
         fsr2_fx1[7:6],	               //		fcc3
         fsr2_fx1[5:4],	               //		fcc2
         fsr2_fx1[3:2],	               //		fcc1
         fsr2_fx1[1:0]}),	       //		fcc0
  .din3({fsr2_fx1[27:26],              // FCMP(E) fcc0: rd
         fsr2_fx1[25:21],              //		tem
         fsr2_fx1[20],		       //		ns
         fsr2_fttexc_merged_fw[11:10], //		ftt
         fsr2_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr2_fx1[7:6],		       //		fcc3
         fsr2_fx1[5:4],		       //		fcc2
         fsr2_fx1[3:2],		       //		fcc1
         fpc_fcc_fw[1:0]}),	       //		fcc0
  .din4({fsr2_fx1[27:26],              // FCMP(E) fcc1: rd
         fsr2_fx1[25:21],              //		tem
         fsr2_fx1[20],		       //		ns
         fsr2_fttexc_merged_fw[11:10], //		ftt
         fsr2_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr2_fx1[7:6],		       //		fcc3
         fsr2_fx1[5:4],	               //		fcc2
         fpc_fcc_fw[1:0],	       //		fcc1
         fsr2_fx1[1:0]}),              //		fcc0
  .din5({fsr2_fx1[27:26],              // FCMP(E) fcc2: rd
         fsr2_fx1[25:21],	       //		tem
         fsr2_fx1[20],		       //		ns
         fsr2_fttexc_merged_fw[11:10], //		ftt
         fsr2_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr2_fx1[7:6],		       //		fcc3
         fpc_fcc_fw[1:0],	       //		fcc2
         fsr2_fx1[3:2],	               //		fcc1
         fsr2_fx1[1:0]}),              //		fcc0
  .din6({fsr2_fx1[27:26],              // FCMP(E) fcc3: rd
         fsr2_fx1[25:21],	       //		tem
         fsr2_fx1[20],	               //		ns
         fsr2_fttexc_merged_fw[11:10], //		ftt
         fsr2_fttexc_merged_fw[9:0],   //		aexc,cexc
         fpc_fcc_fw[1:0],	       //		fcc3
         fsr2_fx1[5:4],		       //		fcc2
         fsr2_fx1[3:2],		       //		fcc1
         fsr2_fx1[1:0]}),              //		fcc0
  .din7({fsr2_fx1[27:26],              // other FPop:   rd
         fsr2_fx1[25:21],	       //		tem
         fsr2_fx1[20],		       //		ns
         fsr2_fttexc_merged_fw[11:10], //		ftt
         fsr2_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr2_fx1[7:6],                //		fcc3
         fsr2_fx1[5:4],		       //		fcc2
         fsr2_fx1[3:2],		       //		fcc1
         fsr2_fx1[1:0]}),              //		fcc0
  .sel (fac_fsr2_sel_fw[2:0]),
  .dout(fsr2_fx1[27:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------
// FSR tid3
// ----------

fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr3_in  (
  .din0(fpc_fsr_w1_result_fw[11:0]),     // w1         {ftt,aexc,cexc}
  .din1(fpc_fsr_w2_result_fw[11:0]),     // fdiv/fsqrt {ftt,aexc,cexc}
  .din2({2'b0, fsr3_fx1[17:13], 5'b0}),  // accrued aexc
  .sel0(fac_fsr3_sel_fw[4]),
  .sel1(fac_fsr3_sel_fw[5]),
  .sel2(1'b1),
  .dout(fsr3_fttexc_merged_fw[11:0])
  );

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr3  (	// FS:wmr_protect
  .scan_in(fx1_fsr3_wmr_scanin),
  .scan_out(fx1_fsr3_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fac_fsr3_sel_fw[3]),
  .din0({ldfsr_data_fw[27:26],         // LDFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr3_fx1[19:18],              //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         fsr3_fx1[7:6],                //		fcc3
         fsr3_fx1[5:4],                //		fcc2
         fsr3_fx1[3:2],                //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din1({ldfsr_data_fw[27:26],         // LDXFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr3_fx1[19:18],	       //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         ldfsr_data_fw[7:6],           //		fcc3
         ldfsr_data_fw[5:4],           //		fcc2
         ldfsr_data_fw[3:2],           //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din2({fsr3_fx1[27:26],              // ST(X)FSR:	rd
         fsr3_fx1[25:21],	       //		tem
         fsr3_fx1[20],	               //		ns
         fsr3_fttexc_merged_fw[11:10], //		ftt
         fsr3_fx1[17:8],	       //		aexc,cexc
         fsr3_fx1[7:6],	               //		fcc3
         fsr3_fx1[5:4],	               //		fcc2
         fsr3_fx1[3:2],	               //		fcc1
         fsr3_fx1[1:0]}),	       //		fcc0
  .din3({fsr3_fx1[27:26],              // FCMP(E) fcc0: rd
         fsr3_fx1[25:21],              //		tem
         fsr3_fx1[20],		       //		ns
         fsr3_fttexc_merged_fw[11:10], //		ftt
         fsr3_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr3_fx1[7:6],		       //		fcc3
         fsr3_fx1[5:4],		       //		fcc2
         fsr3_fx1[3:2],		       //		fcc1
         fpc_fcc_fw[1:0]}),	       //		fcc0
  .din4({fsr3_fx1[27:26],              // FCMP(E) fcc1: rd
         fsr3_fx1[25:21],              //		tem
         fsr3_fx1[20],		       //		ns
         fsr3_fttexc_merged_fw[11:10], //		ftt
         fsr3_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr3_fx1[7:6],		       //		fcc3
         fsr3_fx1[5:4],	               //		fcc2
         fpc_fcc_fw[1:0],	       //		fcc1
         fsr3_fx1[1:0]}),              //		fcc0
  .din5({fsr3_fx1[27:26],              // FCMP(E) fcc2: rd
         fsr3_fx1[25:21],	       //		tem
         fsr3_fx1[20],		       //		ns
         fsr3_fttexc_merged_fw[11:10], //		ftt
         fsr3_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr3_fx1[7:6],		       //		fcc3
         fpc_fcc_fw[1:0],	       //		fcc2
         fsr3_fx1[3:2],	               //		fcc1
         fsr3_fx1[1:0]}),              //		fcc0
  .din6({fsr3_fx1[27:26],              // FCMP(E) fcc3: rd
         fsr3_fx1[25:21],	       //		tem
         fsr3_fx1[20],	               //		ns
         fsr3_fttexc_merged_fw[11:10], //		ftt
         fsr3_fttexc_merged_fw[9:0],   //		aexc,cexc
         fpc_fcc_fw[1:0],	       //		fcc3
         fsr3_fx1[5:4],		       //		fcc2
         fsr3_fx1[3:2],		       //		fcc1
         fsr3_fx1[1:0]}),              //		fcc0
  .din7({fsr3_fx1[27:26],              // other FPop:   rd
         fsr3_fx1[25:21],	       //		tem
         fsr3_fx1[20],		       //		ns
         fsr3_fttexc_merged_fw[11:10], //		ftt
         fsr3_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr3_fx1[7:6],                //		fcc3
         fsr3_fx1[5:4],		       //		fcc2
         fsr3_fx1[3:2],		       //		fcc1
         fsr3_fx1[1:0]}),              //		fcc0
  .sel (fac_fsr3_sel_fw[2:0]),
  .dout(fsr3_fx1[27:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------
// FSR tid4
// ----------

fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr4_in  (
  .din0(fpc_fsr_w1_result_fw[11:0]),     // w1         {ftt,aexc,cexc}
  .din1(fpc_fsr_w2_result_fw[11:0]),     // fdiv/fsqrt {ftt,aexc,cexc}
  .din2({2'b0, fsr4_fx1[17:13], 5'b0}),  // accrued aexc
  .sel0(fac_fsr4_sel_fw[4]),
  .sel1(fac_fsr4_sel_fw[5]),
  .sel2(1'b1),
  .dout(fsr4_fttexc_merged_fw[11:0])
  );

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr4  (	// FS:wmr_protect
  .scan_in(fx1_fsr4_wmr_scanin),
  .scan_out(fx1_fsr4_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fac_fsr4_sel_fw[3]),
  .din0({ldfsr_data_fw[27:26],         // LDFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr4_fx1[19:18],              //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         fsr4_fx1[7:6],                //		fcc3
         fsr4_fx1[5:4],                //		fcc2
         fsr4_fx1[3:2],                //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din1({ldfsr_data_fw[27:26],         // LDXFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr4_fx1[19:18],	       //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         ldfsr_data_fw[7:6],           //		fcc3
         ldfsr_data_fw[5:4],           //		fcc2
         ldfsr_data_fw[3:2],           //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din2({fsr4_fx1[27:26],              // ST(X)FSR:	rd
         fsr4_fx1[25:21],	       //		tem
         fsr4_fx1[20],	               //		ns
         fsr4_fttexc_merged_fw[11:10], //		ftt
         fsr4_fx1[17:8],	       //		aexc,cexc
         fsr4_fx1[7:6],	               //		fcc3
         fsr4_fx1[5:4],	               //		fcc2
         fsr4_fx1[3:2],	               //		fcc1
         fsr4_fx1[1:0]}),	       //		fcc0
  .din3({fsr4_fx1[27:26],              // FCMP(E) fcc0: rd
         fsr4_fx1[25:21],              //		tem
         fsr4_fx1[20],		       //		ns
         fsr4_fttexc_merged_fw[11:10], //		ftt
         fsr4_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr4_fx1[7:6],		       //		fcc3
         fsr4_fx1[5:4],		       //		fcc2
         fsr4_fx1[3:2],		       //		fcc1
         fpc_fcc_fw[1:0]}),	       //		fcc0
  .din4({fsr4_fx1[27:26],              // FCMP(E) fcc1: rd
         fsr4_fx1[25:21],              //		tem
         fsr4_fx1[20],		       //		ns
         fsr4_fttexc_merged_fw[11:10], //		ftt
         fsr4_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr4_fx1[7:6],		       //		fcc3
         fsr4_fx1[5:4],	               //		fcc2
         fpc_fcc_fw[1:0],	       //		fcc1
         fsr4_fx1[1:0]}),              //		fcc0
  .din5({fsr4_fx1[27:26],              // FCMP(E) fcc2: rd
         fsr4_fx1[25:21],	       //		tem
         fsr4_fx1[20],		       //		ns
         fsr4_fttexc_merged_fw[11:10], //		ftt
         fsr4_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr4_fx1[7:6],		       //		fcc3
         fpc_fcc_fw[1:0],	       //		fcc2
         fsr4_fx1[3:2],	               //		fcc1
         fsr4_fx1[1:0]}),              //		fcc0
  .din6({fsr4_fx1[27:26],              // FCMP(E) fcc3: rd
         fsr4_fx1[25:21],	       //		tem
         fsr4_fx1[20],	               //		ns
         fsr4_fttexc_merged_fw[11:10], //		ftt
         fsr4_fttexc_merged_fw[9:0],   //		aexc,cexc
         fpc_fcc_fw[1:0],	       //		fcc3
         fsr4_fx1[5:4],		       //		fcc2
         fsr4_fx1[3:2],		       //		fcc1
         fsr4_fx1[1:0]}),              //		fcc0
  .din7({fsr4_fx1[27:26],              // other FPop:   rd
         fsr4_fx1[25:21],	       //		tem
         fsr4_fx1[20],		       //		ns
         fsr4_fttexc_merged_fw[11:10], //		ftt
         fsr4_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr4_fx1[7:6],                //		fcc3
         fsr4_fx1[5:4],		       //		fcc2
         fsr4_fx1[3:2],		       //		fcc1
         fsr4_fx1[1:0]}),              //		fcc0
  .sel (fac_fsr4_sel_fw[2:0]),
  .dout(fsr4_fx1[27:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------
// FSR tid5
// ----------

fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr5_in  (
  .din0(fpc_fsr_w1_result_fw[11:0]),     // w1         {ftt,aexc,cexc}
  .din1(fpc_fsr_w2_result_fw[11:0]),     // fdiv/fsqrt {ftt,aexc,cexc}
  .din2({2'b0, fsr5_fx1[17:13], 5'b0}),  // accrued aexc
  .sel0(fac_fsr5_sel_fw[4]),
  .sel1(fac_fsr5_sel_fw[5]),
  .sel2(1'b1),
  .dout(fsr5_fttexc_merged_fw[11:0])
  );

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr5  (	// FS:wmr_protect
  .scan_in(fx1_fsr5_wmr_scanin),
  .scan_out(fx1_fsr5_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fac_fsr5_sel_fw[3]),
  .din0({ldfsr_data_fw[27:26],         // LDFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr5_fx1[19:18],              //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         fsr5_fx1[7:6],                //		fcc3
         fsr5_fx1[5:4],                //		fcc2
         fsr5_fx1[3:2],                //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din1({ldfsr_data_fw[27:26],         // LDXFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr5_fx1[19:18],	       //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         ldfsr_data_fw[7:6],           //		fcc3
         ldfsr_data_fw[5:4],           //		fcc2
         ldfsr_data_fw[3:2],           //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din2({fsr5_fx1[27:26],              // ST(X)FSR:	rd
         fsr5_fx1[25:21],	       //		tem
         fsr5_fx1[20],	               //		ns
         fsr5_fttexc_merged_fw[11:10], //		ftt
         fsr5_fx1[17:8],	       //		aexc,cexc
         fsr5_fx1[7:6],	               //		fcc3
         fsr5_fx1[5:4],	               //		fcc2
         fsr5_fx1[3:2],	               //		fcc1
         fsr5_fx1[1:0]}),	       //		fcc0
  .din3({fsr5_fx1[27:26],              // FCMP(E) fcc0: rd
         fsr5_fx1[25:21],              //		tem
         fsr5_fx1[20],		       //		ns
         fsr5_fttexc_merged_fw[11:10], //		ftt
         fsr5_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr5_fx1[7:6],		       //		fcc3
         fsr5_fx1[5:4],		       //		fcc2
         fsr5_fx1[3:2],		       //		fcc1
         fpc_fcc_fw[1:0]}),	       //		fcc0
  .din4({fsr5_fx1[27:26],              // FCMP(E) fcc1: rd
         fsr5_fx1[25:21],              //		tem
         fsr5_fx1[20],		       //		ns
         fsr5_fttexc_merged_fw[11:10], //		ftt
         fsr5_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr5_fx1[7:6],		       //		fcc3
         fsr5_fx1[5:4],	               //		fcc2
         fpc_fcc_fw[1:0],	       //		fcc1
         fsr5_fx1[1:0]}),              //		fcc0
  .din5({fsr5_fx1[27:26],              // FCMP(E) fcc2: rd
         fsr5_fx1[25:21],	       //		tem
         fsr5_fx1[20],		       //		ns
         fsr5_fttexc_merged_fw[11:10], //		ftt
         fsr5_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr5_fx1[7:6],		       //		fcc3
         fpc_fcc_fw[1:0],	       //		fcc2
         fsr5_fx1[3:2],	               //		fcc1
         fsr5_fx1[1:0]}),              //		fcc0
  .din6({fsr5_fx1[27:26],              // FCMP(E) fcc3: rd
         fsr5_fx1[25:21],	       //		tem
         fsr5_fx1[20],	               //		ns
         fsr5_fttexc_merged_fw[11:10], //		ftt
         fsr5_fttexc_merged_fw[9:0],   //		aexc,cexc
         fpc_fcc_fw[1:0],	       //		fcc3
         fsr5_fx1[5:4],		       //		fcc2
         fsr5_fx1[3:2],		       //		fcc1
         fsr5_fx1[1:0]}),              //		fcc0
  .din7({fsr5_fx1[27:26],              // other FPop:   rd
         fsr5_fx1[25:21],	       //		tem
         fsr5_fx1[20],		       //		ns
         fsr5_fttexc_merged_fw[11:10], //		ftt
         fsr5_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr5_fx1[7:6],                //		fcc3
         fsr5_fx1[5:4],		       //		fcc2
         fsr5_fx1[3:2],		       //		fcc1
         fsr5_fx1[1:0]}),              //		fcc0
  .sel (fac_fsr5_sel_fw[2:0]),
  .dout(fsr5_fx1[27:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------
// FSR tid6
// ----------

fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr6_in  (
  .din0(fpc_fsr_w1_result_fw[11:0]),     // w1         {ftt,aexc,cexc}
  .din1(fpc_fsr_w2_result_fw[11:0]),     // fdiv/fsqrt {ftt,aexc,cexc}
  .din2({2'b0, fsr6_fx1[17:13], 5'b0}),  // accrued aexc
  .sel0(fac_fsr6_sel_fw[4]),
  .sel1(fac_fsr6_sel_fw[5]),
  .sel2(1'b1),
  .dout(fsr6_fttexc_merged_fw[11:0])
  );

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr6  (	// FS:wmr_protect
  .scan_in(fx1_fsr6_wmr_scanin),
  .scan_out(fx1_fsr6_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fac_fsr6_sel_fw[3]),
  .din0({ldfsr_data_fw[27:26],         // LDFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr6_fx1[19:18],              //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         fsr6_fx1[7:6],                //		fcc3
         fsr6_fx1[5:4],                //		fcc2
         fsr6_fx1[3:2],                //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din1({ldfsr_data_fw[27:26],         // LDXFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr6_fx1[19:18],	       //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         ldfsr_data_fw[7:6],           //		fcc3
         ldfsr_data_fw[5:4],           //		fcc2
         ldfsr_data_fw[3:2],           //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din2({fsr6_fx1[27:26],              // ST(X)FSR:	rd
         fsr6_fx1[25:21],	       //		tem
         fsr6_fx1[20],	               //		ns
         fsr6_fttexc_merged_fw[11:10], //		ftt
         fsr6_fx1[17:8],	       //		aexc,cexc
         fsr6_fx1[7:6],	               //		fcc3
         fsr6_fx1[5:4],	               //		fcc2
         fsr6_fx1[3:2],	               //		fcc1
         fsr6_fx1[1:0]}),	       //		fcc0
  .din3({fsr6_fx1[27:26],              // FCMP(E) fcc0: rd
         fsr6_fx1[25:21],              //		tem
         fsr6_fx1[20],		       //		ns
         fsr6_fttexc_merged_fw[11:10], //		ftt
         fsr6_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr6_fx1[7:6],		       //		fcc3
         fsr6_fx1[5:4],		       //		fcc2
         fsr6_fx1[3:2],		       //		fcc1
         fpc_fcc_fw[1:0]}),	       //		fcc0
  .din4({fsr6_fx1[27:26],              // FCMP(E) fcc1: rd
         fsr6_fx1[25:21],              //		tem
         fsr6_fx1[20],		       //		ns
         fsr6_fttexc_merged_fw[11:10], //		ftt
         fsr6_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr6_fx1[7:6],		       //		fcc3
         fsr6_fx1[5:4],	               //		fcc2
         fpc_fcc_fw[1:0],	       //		fcc1
         fsr6_fx1[1:0]}),              //		fcc0
  .din5({fsr6_fx1[27:26],              // FCMP(E) fcc2: rd
         fsr6_fx1[25:21],	       //		tem
         fsr6_fx1[20],		       //		ns
         fsr6_fttexc_merged_fw[11:10], //		ftt
         fsr6_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr6_fx1[7:6],		       //		fcc3
         fpc_fcc_fw[1:0],	       //		fcc2
         fsr6_fx1[3:2],	               //		fcc1
         fsr6_fx1[1:0]}),              //		fcc0
  .din6({fsr6_fx1[27:26],              // FCMP(E) fcc3: rd
         fsr6_fx1[25:21],	       //		tem
         fsr6_fx1[20],	               //		ns
         fsr6_fttexc_merged_fw[11:10], //		ftt
         fsr6_fttexc_merged_fw[9:0],   //		aexc,cexc
         fpc_fcc_fw[1:0],	       //		fcc3
         fsr6_fx1[5:4],		       //		fcc2
         fsr6_fx1[3:2],		       //		fcc1
         fsr6_fx1[1:0]}),              //		fcc0
  .din7({fsr6_fx1[27:26],              // other FPop:   rd
         fsr6_fx1[25:21],	       //		tem
         fsr6_fx1[20],		       //		ns
         fsr6_fttexc_merged_fw[11:10], //		ftt
         fsr6_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr6_fx1[7:6],                //		fcc3
         fsr6_fx1[5:4],		       //		fcc2
         fsr6_fx1[3:2],		       //		fcc1
         fsr6_fx1[1:0]}),              //		fcc0
  .sel (fac_fsr6_sel_fw[2:0]),
  .dout(fsr6_fx1[27:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------
// FSR tid7
// ----------

fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 fsr7_in  (
  .din0(fpc_fsr_w1_result_fw[11:0]),     // w1         {ftt,aexc,cexc}
  .din1(fpc_fsr_w2_result_fw[11:0]),     // fdiv/fsqrt {ftt,aexc,cexc}
  .din2({2'b0, fsr7_fx1[17:13], 5'b0}),  // accrued aexc
  .sel0(fac_fsr7_sel_fw[4]),
  .sel1(fac_fsr7_sel_fw[5]),
  .sel2(1'b1),
  .dout(fsr7_fttexc_merged_fw[11:0])
  );

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr7  (	// FS:wmr_protect
  .scan_in(fx1_fsr7_wmr_scanin),
  .scan_out(fx1_fsr7_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fac_fsr7_sel_fw[3]),
  .din0({ldfsr_data_fw[27:26],         // LDFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr7_fx1[19:18],              //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         fsr7_fx1[7:6],                //		fcc3
         fsr7_fx1[5:4],                //		fcc2
         fsr7_fx1[3:2],                //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din1({ldfsr_data_fw[27:26],         // LDXFSR:	rd
         ldfsr_data_fw[25:21],         //		tem
         ldfsr_data_fw[20],            //		ns
         fsr7_fx1[19:18],	       //		ftt
         ldfsr_data_fw[17:8],          //		aexc,cexc
         ldfsr_data_fw[7:6],           //		fcc3
         ldfsr_data_fw[5:4],           //		fcc2
         ldfsr_data_fw[3:2],           //		fcc1
         ldfsr_data_fw[1:0]}),         //		fcc0
  .din2({fsr7_fx1[27:26],              // ST(X)FSR:	rd
         fsr7_fx1[25:21],	       //		tem
         fsr7_fx1[20],	               //		ns
         fsr7_fttexc_merged_fw[11:10], //		ftt
         fsr7_fx1[17:8],	       //		aexc,cexc
         fsr7_fx1[7:6],	               //		fcc3
         fsr7_fx1[5:4],	               //		fcc2
         fsr7_fx1[3:2],	               //		fcc1
         fsr7_fx1[1:0]}),	       //		fcc0
  .din3({fsr7_fx1[27:26],              // FCMP(E) fcc0: rd
         fsr7_fx1[25:21],              //		tem
         fsr7_fx1[20],		       //		ns
         fsr7_fttexc_merged_fw[11:10], //		ftt
         fsr7_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr7_fx1[7:6],		       //		fcc3
         fsr7_fx1[5:4],		       //		fcc2
         fsr7_fx1[3:2],		       //		fcc1
         fpc_fcc_fw[1:0]}),	       //		fcc0
  .din4({fsr7_fx1[27:26],              // FCMP(E) fcc1: rd
         fsr7_fx1[25:21],              //		tem
         fsr7_fx1[20],		       //		ns
         fsr7_fttexc_merged_fw[11:10], //		ftt
         fsr7_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr7_fx1[7:6],		       //		fcc3
         fsr7_fx1[5:4],	               //		fcc2
         fpc_fcc_fw[1:0],	       //		fcc1
         fsr7_fx1[1:0]}),              //		fcc0
  .din5({fsr7_fx1[27:26],              // FCMP(E) fcc2: rd
         fsr7_fx1[25:21],	       //		tem
         fsr7_fx1[20],		       //		ns
         fsr7_fttexc_merged_fw[11:10], //		ftt
         fsr7_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr7_fx1[7:6],		       //		fcc3
         fpc_fcc_fw[1:0],	       //		fcc2
         fsr7_fx1[3:2],	               //		fcc1
         fsr7_fx1[1:0]}),              //		fcc0
  .din6({fsr7_fx1[27:26],              // FCMP(E) fcc3: rd
         fsr7_fx1[25:21],	       //		tem
         fsr7_fx1[20],	               //		ns
         fsr7_fttexc_merged_fw[11:10], //		ftt
         fsr7_fttexc_merged_fw[9:0],   //		aexc,cexc
         fpc_fcc_fw[1:0],	       //		fcc3
         fsr7_fx1[5:4],		       //		fcc2
         fsr7_fx1[3:2],		       //		fcc1
         fsr7_fx1[1:0]}),              //		fcc0
  .din7({fsr7_fx1[27:26],              // other FPop:   rd
         fsr7_fx1[25:21],	       //		tem
         fsr7_fx1[20],		       //		ns
         fsr7_fttexc_merged_fw[11:10], //		ftt
         fsr7_fttexc_merged_fw[9:0],   //		aexc,cexc
         fsr7_fx1[7:6],                //		fcc3
         fsr7_fx1[5:4],		       //		fcc2
         fsr7_fx1[3:2],		       //		fcc1
         fsr7_fx1[1:0]}),              //		fcc0
  .sel (fac_fsr7_sel_fw[2:0]),
  .dout(fsr7_fx1[27:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------------------------------------------------------------------------
// FGU ASI local ring datapath
// ----------------------------------------------------------------------------

fgu_fad_dp_msff_macro__stack_32l__width_31 flop_rng1_4f  (
  .scan_in(flop_rng1_4f_scanin),
  .scan_out(flop_rng1_4f_scanout),
  .clk (l2clk),
  .en  (asi_clken),
  .din (fgd_rngl_cdbus_3f[62:32]),
  .dout(    rngl_cdbus_4f[62:32]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fad_dp_msff_macro__stack_32l__width_32 flop_rng0_4f  (
  .scan_in(flop_rng0_4f_scanin),
  .scan_out(flop_rng0_4f_scanout),
  .clk (l2clk),
  .en  (asi_clken),
  .din (fgd_rngl_cdbus_3f[31:0]),
  .dout(    rngl_cdbus_4f[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fad_dp_buff_macro__rep_1__stack_32l__width_31 buf_rng1  (
  .din (    rngl_cdbus_4f[62:32]),
  .dout(fgu_rngl_cdbus[62:32])
  );

fgu_fad_dp_buff_macro__rep_1__stack_32l__width_32 buf_rng0  (
  .din (    rngl_cdbus_4f[31:0]),
  .dout(fgu_rngl_cdbus[31:0])
  );


// ----------------------------------------------------------------------------
//                               FX1 stage
// ----------------------------------------------------------------------------

// ------------------------------------
// FSR thread 0-7 mux
//
// ST(X)FSR has a presync. All preceeding instrs have completed
// FW+1 before ST(X)FSR reaches FX1.
//
// LD(X)FSR has same presync as ST(X)FSR. LD(X)FSR update of the
// architected FSR is available in FX4. Instrs following LD(X)FSR
// are in E when LD(X)FSR is in FX4.
//
// As a result, the mux below can be a mux/flop and still allow
// correct functionality. Making it a mux/flop helps storefmt timing
// for the ST(X)FSR path.
// ------------------------------------

fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 fx1_fsr  (
  .scan_in(fx1_fsr_scanin),
  .scan_out(fx1_fsr_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din0(fsr0_fx1[27:0]),
  .din1(fsr1_fx1[27:0]),
  .din2(fsr2_fx1[27:0]),
  .din3(fsr3_fx1[27:0]),
  .din4(fsr4_fx1[27:0]),
  .din5(fsr5_fx1[27:0]),
  .din6(fsr6_fx1[27:0]),
  .din7(fsr7_fx1[27:0]),
  .sel (fac_tid_e[2:0]),  // ST(X)FSR is in E when mux is selecting the FSR.
                          // Instr following LD(X)FSR is in E when mux is selecting the FSR.
  .dout({fad_fsr_rd_fx1[1:0],     // LD(X)FSR update only
         fad_fsr_tem_fx1[4:0],    // LD(X)FSR update only
         fad_fsr_ns_fx1,          // LD(X)FSR update only
             fsr_ftt_fx1[1:0],    // ST(X)FSR usage only
             fsr_aexc_fx1[4:0],   // ST(X)FSR usage only
             fsr_cexc_fx1[4:0],   // ST(X)FSR usage only
             fsr_fcc3_fx1[1:0],   // STXFSR   usage only
             fsr_fcc2_fx1[1:0],   // STXFSR   usage only
             fsr_fcc1_fx1[1:0],   // STXFSR   usage only
             fsr_fcc0_fx1[1:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)  // ST(X)FSR usage only
  );

// ------------------------------------
// Mantissa format muxes
// ------------------------------------

fgu_fad_dp_mux_macro__mux_aonpe__ports_5__width_64 rs1fmt  (
  .din0({1'b1,fad_rs1_fx1[51:0], 11'b0}),  // DP
  .din1({1'b1,fad_rs1_fx1[22:0], 40'b0}),  // SP odd (rotate)
  .din2({1'b1,fad_rs1_fx1[54:32],40'b0}),  // SP even
  .din3({fad_rs1_fx1[31:0],      32'b0}),  // Word odd (rotate)
  .din4( fad_rs1_fx1[63:0]             ),  // Dblword, Word even
                                           // else: Const 64'b0
  .sel0(aman_fmt_sel_fx1[0]),
  .sel1(aman_fmt_sel_fx1[1]),
  .sel2(aman_fmt_sel_fx1[2]),
  .sel3(aman_fmt_sel_fx1[3]),
  .sel4(aman_fmt_sel_fx1[4]),
  .dout(rs1_fmt_fx1[63:0])
  );

fgu_fad_dp_buff_macro__width_64 buf_rs1fmt  (
  .din (    rs1_fmt_fx1[63:0]),
  .dout(fad_rs1_fmt_fx1[63:0])
  );

fgu_fad_dp_mux_macro__mux_aonpe__ports_5__width_64 rs2fmt  (
  .din0({1'b1,fad_rs2_fx1[51:0], 11'b0}),  // DP
  .din1({1'b1,fad_rs2_fx1[22:0], 40'b0}),  // SP odd (rotate)
  .din2({1'b1,fad_rs2_fx1[54:32],40'b0}),  // SP even
  .din3({fad_rs2_fx1[31:0],      32'b0}),  // Word odd (rotate)
  .din4( fad_rs2_fx1[63:0]             ),  // Dblword, Word even
  .sel0(bman_fmt_sel_fx1[0]),
  .sel1(bman_fmt_sel_fx1[1]),
  .sel2(bman_fmt_sel_fx1[2]),
  .sel3(bman_fmt_sel_fx1[3]),
  .sel4(bman_fmt_sel_fx1[4]),
  .dout(rs2_fmt_fx1[63:0])
  );

fgu_fad_dp_buff_macro__width_64 buf_rs2fmt  (
  .din (    rs2_fmt_fx1[63:0]),
  .dout(fad_rs2_fmt_fx1[63:0])
  );

fgu_fad_dp_mux_macro__mux_aonpe__ports_4__width_64 storefmt  (
  .din0({fad_rs2_fx1[31:0],      32'b0}),  // STF odd (rotate)
  .din1( fad_rs2_fx1[63:0]             ),  // STF even, STDF
  .din2({26'b0,
             fsr_fcc3_fx1[1:0],
             fsr_fcc2_fx1[1:0],
             fsr_fcc1_fx1[1:0],
         fad_fsr_rd_fx1[1:0],
         2'b0,
         fad_fsr_tem_fx1[4:0],
         fad_fsr_ns_fx1,
         2'b0,
         3'b0,                             // FSR.ver    = 3'b0
	 1'b0,                             // FSR.ftt[2] = 1'b0
             fsr_ftt_fx1[1:0],
         2'b0,
             fsr_fcc0_fx1[1:0],
             fsr_aexc_fx1[4:0],
             fsr_cexc_fx1[4:0]
                                      }),  // STXFSR
  .din3({fad_fsr_rd_fx1[1:0],
         2'b0,
         fad_fsr_tem_fx1[4:0],
         fad_fsr_ns_fx1,
         2'b0,
         3'b0,                             // FSR.ver    = 3'b0
	 1'b0,                             // FSR.ftt[2] = 1'b0
             fsr_ftt_fx1[1:0],
         2'b0,
             fsr_fcc0_fx1[1:0],
             fsr_aexc_fx1[4:0],
             fsr_cexc_fx1[4:0],
         32'b0                        }),  // STFSR
  .sel0(fac_fst_fmt_sel_fx1[0]),
  .sel1(fac_fst_fmt_sel_fx1[1]),
  .sel2(fac_fst_fmt_sel_fx1[2]),
  .sel3(fac_fst_fmt_sel_fx1[3]),
  .dout(fst_data_fx1[63:0])                // pwr mgmt: aomux free zeros
  );

fgu_fad_dp_buff_macro__rep_1__width_64 buf_storefmt  (
  .din (        fst_data_fx1[63:0]),
  .dout(fgu_lsu_fst_data_fx1[63:0])
  );


// ----------------------------------------------------------------------------
//                               FB stage
// ----------------------------------------------------------------------------

fgu_fad_dp_mux_macro__mux_aope__ports_3__width_12 w2addr  (
  .din0({fac_fpd_addr_fb[4:0],
         fac_fpd_tid_fb[2:0],
         fac_fpd_32b_fb,
         fac_fpd_odd32b_fb,
         pre_fpd_vld_fb[1:0]}),
  .din1({fac_fpd_addr_fb[4:0],
         fac_fpd_tid_fb[2:0],
         fac_fpd_32b_fb,
         fac_fpd_odd32b_fb,
         pre_fpd_vld_fb[1:0]}),
  .din2({lsu_fgu_fld_addr_b[4:0],
         lsu_fgu_fld_tid_b[2:0],
         lsu_fgu_fld_32b_b,
         lsu_fgu_fld_odd32b_b,
         2'b0}),
  .sel0(div_finish_fltd_fb),
  .sel1(div_finish_flts_fb),
  .dout({w2_addr_fb[4:0],
         w2_tid_fb[2:0],
         w2_32b_fb,
         w2_odd32b_fb,
         fpd_vld_fb[1:0]})
  );

fgu_fad_dp_inv_macro__width_5 inv_vld  (
  .din ({lsu_fgu_fld_32b_b,
         lsu_fgu_fld_odd32b_b,
         lsu_fgu_fsr_load_b,
         fpd_trap_fb,
         fac_fpd_odd32b_fb}),
  .dout({lsu_fgu_fld_32b_b_,
         lsu_fgu_fld_odd32b_b_,
         lsu_fgu_fsr_load_b_,
         fpd_trap_fb_,
         fac_fpd_odd32b_fb_})
  );

fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 even_en_ld  ( 
  .din0(lsu_fgu_fld_32b_b    ),
  .din1(lsu_fgu_fld_32b_b_   ),
  .sel0(lsu_fgu_fld_odd32b_b_),
  .sel1(1'b1                 ),
  .dout(fld_w2_even_en_fb    )
  );

fgu_fad_dp_or_macro__ports_2__width_2 odd_en_ld  ( 
  .din0({lsu_fgu_fld_32b_b_,   fpc_fpd_ieee_trap_fb }),
  .din1({lsu_fgu_fld_odd32b_b, fpc_fpd_unfin_fb     }),
  .dout({fld_w2_odd_en_fb,     fpd_trap_fb          })
  );

// 0in custom -fire ((|fad_w2_vld_fw[1:0]) & ($0in_delay((fpc_fpd_ieee_trap_fb | fpc_fpd_unfin_fb),1))) -message "FRF written during FP trap"

// 0in custom -fire ((lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & (|fpc_w1_vld_fb[1:0]) & (lsu_fgu_fld_tid_b[2:0]==fac_w1_tid_fb[2:0])),1))) | (lsu_fgu_fld_vld_w & ($0in_delay((lsu_fgu_fsr_load_b & (|fad_w1_vld_fw[1:0]) & (lsu_fgu_fld_tid_b[2:0]==fad_w1_tid_fw[2:0])),1)))) -message "LDFSR collision with FPop"

fgu_fad_dp_and_macro__ports_3__width_2 and_vld  (
  .din0({fld_w2_even_en_fb,   fld_w2_odd_en_fb   }),
  .din1({lsu_fgu_fsr_load_b_, lsu_fgu_fsr_load_b_}),
  .din2({mbist_run_1f_,       mbist_run_1f_      }),
  .dout({pre_fld_vld_fb[1],   pre_fld_vld_fb[0]  })
  );

fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 fpd_vld  ( 
  .din0({div_finish_fltd_fb,      div_finish_fltd_fb    }),
  .din1({div_finish_flts_even_fb, div_finish_flts_odd_fb}),
  .sel0( fpd_trap_fb_),
  .sel1( fpd_trap_fb_),
  .dout({pre_fpd_vld_fb[1],       pre_fpd_vld_fb[0]     })
  );

fgu_fad_dp_and_macro__ports_2__width_3 fpd_odd  ( 
  .din0({div_finish_flts_fb, div_finish_flts_fb,     div_finish_flts_fb     }),
  .din1({fac_fpd_odd32b_fb,  fac_fpd_odd32b_fb,      fac_fpd_odd32b_fb_     }),
  .dout({fpd_vld_odd32b_fb,  div_finish_flts_odd_fb, div_finish_flts_even_fb})
  );

fgu_fad_dp_mux_macro__mux_aonpe__ports_2__width_52 div_const  (
  .din0(fdd_result_rep0[62:11]),  // FPD mantissa result
  .din1(52'hfffffffffffff),       // FPD mantissa constant result for fdiv overflow (max or inf)
  .sel0(fpc_fpd_const_sel[0]),    // Note: lack of sel0 or sel1 provides free zeros for aomux,
  .sel1(fpc_fpd_const_sel[1]),    //       fdiv underflow constant result is zero
  .dout(q_fdd_result_rep0[62:11])
  );

fgu_fad_dp_mux_macro__mux_aope__ports_4__width_64 mux_w2data  (
  .din0({       fpc_fpd_sign_res, fpc_fpd_exp_res[10:0], q_fdd_result_rep0[62:11]       }),  // FPD result DP
  .din1({32'b0, fpc_fpd_sign_res, fpc_fpd_exp_res[7:0], q_fdd_result_rep0[62:40]       }),  // FPD result SP odd
  .din2({       fpc_fpd_sign_res, fpc_fpd_exp_res[7:0], q_fdd_result_rep0[62:40], 32'b0}),  // FPD result SP even
  .din3(lsu_fgu_fld_data_b[63:0]),
  .sel0(div_finish_fltd_fb),
  .sel1(fpd_vld_odd32b_fb),
  .sel2(div_finish_flts_fb),
  .dout(w2_result_fb[63:0])
  );


// ----------------------------------------------------------------------------
//                               FW stage
// ----------------------------------------------------------------------------

fgu_fad_dp_msff_macro__width_64 fw_w2data  (
  .scan_in(fw_w2data_scanin),
  .scan_out(fw_w2data_scanout),
  .clk (l2clk),
  .en  (coreon_clken),
  .din (          w2_result_fb[63:0]),  // requires free running clk
  .dout(fad_nombi_w2_result_fw[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fad_dp_msff_macro__width_64 fw_w1  (
  .scan_in(fw_w1_scanin),
  .scan_out(fw_w1_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (fpf_w1_result_fb[63:0]),
  .dout(    w1_result_fw[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fad_dp_msff_macro__stack_32l__width_26 fw_ldfsr  (
  .scan_in(fw_ldfsr_scanin),
  .scan_out(fw_ldfsr_scanout),
  .clk (l2clk),
  .en  (lsu_fgu_fld_b),
  .din ({lsu_fgu_fld_data_b[31:30],    // requires free running clk or lsu_fgu_fld_b en
         lsu_fgu_fld_data_b[27:22],    // requires free running clk or lsu_fgu_fld_b en
         lsu_fgu_fld_data_b[9:0],      // requires free running clk or lsu_fgu_fld_b en
         lsu_fgu_fld_data_b[37:32],    // requires free running clk or lsu_fgu_fld_b en
         lsu_fgu_fld_data_b[11:10]}),  // requires free running clk or lsu_fgu_fld_b en
  .dout({ldfsr_data_fw[27:20], ldfsr_data_fw[17:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

assign  fgu_fld_fcc_fx3[7:0] = ldfsr_data_fw[7:0];

fgu_fad_dp_inv_macro__width_1 inv_mbist_run  (
  .din (mbist_run_1f),
  .dout(mbist_run_1f_)
  );

fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_2 w2_vld  ( 
  .din0({pre_fld_vld_fw[1],     pre_fld_vld_fw[0]    }),  // functional, pre qualified with mbist_run_1f_
  .din1({fpd_vld_fw[1],         fpd_vld_fw[0]        }),  // functional
  .din2({mbist_frf_write_en_1f, mbist_frf_write_en_1f}),  // MBIST
  .sel0(lsu_fgu_fld_vld_w),
  .sel1(mbist_run_1f_),
  .sel2(mbist_run_1f),
  .dout({fad_w2_vld_fw[1],      fad_w2_vld_fw[0]     })
  );

fgu_fad_dp_mux_macro__mux_pgpe__ports_2__width_64 mux_w2mbist1  (
  .din0({8{fec_mbist_wdata_1f[7:0]}}),  // MBIST
  .din1(fad_nombi_w2_result_fw[63:0]),  // functional
  .sel0(mbist_run_1f),
  .dout(fad_w2_result_fw[63:0]      )
  );

fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_8 mux_w2mbist2  (
  .din0({fac_mbist_addr_1f[7:5], fac_mbist_addr_1f[4:0]}),  // MBIST
  .din1({w2_tid_fw[2:0],         w2_addr_fw[4:0]       }),  // functional
  .sel0(mbist_run_1f),
  .sel1(mbist_run_1f_),
  .dout({i_w2_tid_fw[2:0],       i_w2_addr_fw[4:0]     })
  );

fgu_fad_dp_buff_macro__width_8 buf_w2mbist2  (
  .din ({  i_w2_tid_fw[2:0],   i_w2_addr_fw[4:0]}),
  .dout({fad_w2_tid_fw[2:0], fad_w2_addr_fw[4:0]})
  );


// ----------------------------------------------------------------------------
//                               FW1 stage
// ----------------------------------------------------------------------------

fgu_fad_dp_msff_macro__minbuff_1__width_64 fw1_w2data  (
  .scan_in(fw1_w2data_scanin),
  .scan_out(fw1_w2data_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (fad_nombi_w2_result_fw[63:0]),
  .dout(w2_result_fw1[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );


// fixscan start:
assign e_01_scanin               = scan_in                  ;
assign e_01_extra_scanin         = e_01_scanout             ;
assign fx1_rs1byp_scanin         = e_01_extra_scanout       ;
assign fx1_rs2byp_scanin         = fx1_rs1byp_scanout       ;
assign flop_rng1_4f_scanin       = fx1_rs2byp_scanout       ;
assign flop_rng0_4f_scanin       = flop_rng1_4f_scanout     ;
assign fx1_fsr_scanin            = flop_rng0_4f_scanout     ;
assign fw_w2data_scanin          = fx1_fsr_scanout          ;
assign fw_w1_scanin              = fw_w2data_scanout        ;
assign fw_ldfsr_scanin           = fw_w1_scanout            ;
assign fw1_w2data_scanin         = fw_ldfsr_scanout         ;
assign scan_out                  = fw1_w2data_scanout       ;

assign fx1_fsr0_wmr_scanin       = wmr_scan_in              ;
assign fx1_fsr1_wmr_scanin       = fx1_fsr0_wmr_scanout     ;
assign fx1_fsr2_wmr_scanin       = fx1_fsr1_wmr_scanout     ;
assign fx1_fsr3_wmr_scanin       = fx1_fsr2_wmr_scanout     ;
assign fx1_fsr4_wmr_scanin       = fx1_fsr3_wmr_scanout     ;
assign fx1_fsr5_wmr_scanin       = fx1_fsr4_wmr_scanout     ;
assign fx1_fsr6_wmr_scanin       = fx1_fsr5_wmr_scanout     ;
assign fx1_fsr7_wmr_scanin       = fx1_fsr6_wmr_scanout     ;
assign wmr_scan_out              = fx1_fsr7_wmr_scanout     ;
// fixscan end:
endmodule  // fgu_fad_dp


//
//   buff macro
//
//


module fgu_fad_dp_buff_macro__dbuff_32x__rep_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__width_47 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [45:0] so;

  input [46:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [46:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(47)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[46:0]),
.si({scan_in,so[45:0]}),
.so({so[45:0],scan_out}),
.q(dout[46:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__width_23 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [21:0] so;

  input [22:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [22:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(23)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[22:0]),
.si({scan_in,so[21:0]}),
.so({so[21:0],scan_out}),
.q(dout[22:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fad_dp_and_macro__ports_2__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


and2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fad_dp_cmp_macro__width_12 (
  din0, 
  din1, 
  dout);
  input [11:0] din0;
  input [11:0] din1;
  output dout;


cmp #(12)  m0_0 (
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout)
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module fgu_fad_dp_nor_macro__ports_3__width_4 (
  din0, 
  din1, 
  din2, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  input [3:0] din2;
  output [3:0] dout;


nor3 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.in2(din2[3:0]),
.out(dout[3:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fad_dp_nand_macro__ports_2__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


nand2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__dmux_4x__mux_aope__ports_7__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc7_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6)
);

mux7s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fad_dp_cmp_macro__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output dout;


cmp #(64)  m0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module fgu_fad_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__mux_aonpe__ports_3__stack_32l__width_12 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [11:0] din0;
  input sel0;
  input [11:0] din1;
  input sel1;
  input [11:0] din2;
  input sel2;
  output [11:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(12)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[11:0]),
  .in1(din1[11:0]),
  .in2(din2[11:0]),
.dout(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__mux_aodec__ports_8__stack_32l__width_28 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;
wire [27:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [26:0] so;

  input [27:0] din0;
  input [27:0] din1;
  input [27:0] din2;
  input [27:0] din3;
  input [27:0] din4;
  input [27:0] din5;
  input [27:0] din6;
  input [27:0] din7;
  input [2:0] sel;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [27:0] dout;


  output scan_out;


cl_dp1_pdec8_8x  c1_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(28)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[27:0]),
  .in1(din1[27:0]),
  .in2(din2[27:0]),
  .in3(din3[27:0]),
  .in4(din4[27:0]),
  .in5(din5[27:0]),
  .in6(din6[27:0]),
  .in7(din7[27:0]),
.dout(muxout[27:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__stack_32l__width_31 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [29:0] so;

  input [30:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [30:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(31)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[30:0]),
.si({scan_in,so[29:0]}),
.so({so[29:0],scan_out}),
.q(dout[30:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__stack_32l__width_32 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fad_dp_buff_macro__rep_1__stack_32l__width_31 (
  din, 
  dout);
  input [30:0] din;
  output [30:0] dout;


buff #(31)  d0_0 (
.in(din[30:0]),
.out(dout[30:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fad_dp_buff_macro__rep_1__stack_32l__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__mux_aonpe__ports_5__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;
  output [63:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fad_dp_buff_macro__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__mux_aonpe__ports_4__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  output [63:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fad_dp_buff_macro__rep_1__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__mux_aope__ports_3__width_12 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [11:0] din0;
  input [11:0] din1;
  input [11:0] din2;
  input sel0;
  input sel1;
  output [11:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(12)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[11:0]),
  .in1(din1[11:0]),
  .in2(din2[11:0]),
.dout(dout[11:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fad_dp_inv_macro__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


inv #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  output [0:0] dout;


mux2s #(1)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
.dout(dout[0:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module fgu_fad_dp_or_macro__ports_2__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


or2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fad_dp_and_macro__ports_3__width_2 (
  din0, 
  din1, 
  din2, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  input [1:0] din2;
  output [1:0] dout;


and3 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.in2(din2[1:0]),
.out(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [1:0] din0;
  input sel0;
  input [1:0] din1;
  input sel1;
  output [1:0] dout;


mux2s #(2)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[1:0]),
  .in1(din1[1:0]),
.dout(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fad_dp_and_macro__ports_2__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


and2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__mux_aonpe__ports_2__width_52 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [51:0] din0;
  input sel0;
  input [51:0] din1;
  input sel1;
  output [51:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(52)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[51:0]),
  .in1(din1[51:0]),
.dout(dout[51:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__mux_aope__ports_4__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [63:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__stack_32l__width_26 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [24:0] so;

  input [25:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [25:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(26)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[25:0]),
.si({scan_in,so[24:0]}),
.so({so[24:0],scan_out}),
.q(dout[25:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fad_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_3__width_2 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
  input [1:0] din0;
  input sel0;
  input [1:0] din1;
  input sel1;
  input [1:0] din2;
  input sel2;
  output [1:0] dout;


mux3s #(2)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .in0(din0[1:0]),
  .in1(din1[1:0]),
  .in2(din2[1:0]),
.dout(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__mux_pgpe__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(64)  d0_0 (
  .sel(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fad_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_8 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [7:0] din0;
  input sel0;
  input [7:0] din1;
  input sel1;
  output [7:0] dout;


mux2s #(8)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fad_dp_buff_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fad_dp_msff_macro__minbuff_1__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fdc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fdc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_out, 
  fac_div_flush_fx3, 
  fpe_rs2_fmt_fx1_b0, 
  fpf_hi_bof_fx1, 
  fpf_lo_bof_fx1, 
  fpf_sa_xor_sb_fx1, 
  fac_div_valid_fx1, 
  fac_divq_valid_fx1, 
  fac_div_control_fx1, 
  fpc_rd_mode_fx3, 
  fpc_emin_fx3, 
  div_clken, 
  fdd_pe_clth, 
  fdd_cla_zero32_, 
  fdd_cla_zero64_, 
  fdd_result, 
  fdd_fdx_din0, 
  fdd_fdx_din1, 
  fdd_fdx_cin64, 
  fdd_fdq00_10_sum, 
  fdd_fdq00_10_carry, 
  fdd_fdq1p_sum, 
  fdd_fdq1p_carry, 
  fdd_fdq1n_sum, 
  fdd_fdq1n_carry, 
  fgu_fdiv_stall, 
  fgu_idiv_stall, 
  fdc_dec_exp_early, 
  fdc_icc_v_early, 
  fdc_xicc_z_early, 
  fdc_finish_int_early, 
  fdc_finish_fltd_early, 
  fdc_finish_flts_early, 
  fdc_flt_inexact, 
  fdc_asign_lth, 
  fdc_bsign_lth, 
  fdc_bsign_lth_, 
  fdc_pe_cycle3, 
  fdc_pe_cmux_sel, 
  fdc_pe_smux_sel, 
  fdc_pe_xsht_ctl, 
  fdc_ie_fsqrt_valid_even, 
  fdc_ie_fsqrt_valid_even_, 
  fdc_ie_fsqrt_valid_odd, 
  fdc_ie_fsqrt_valid_odd_, 
  fdc_ie_rmux_sel, 
  fdc_ie_dmux_sel, 
  fdc_flt_increment, 
  fdc_pte_clasel, 
  fdc_pte_csa_cin, 
  fdc_pte_cycle2, 
  fdc_emin_lth, 
  fdc_pte_qsel, 
  fdc_pte_stall_, 
  fdc_flt_round, 
  fdc_idiv_ctl, 
  fdc_fdx_cin_in, 
  fdc_qsel00, 
  fdc_qsel1, 
  fdc_q_in, 
  fdc_qm1_in);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk_pm1;
wire spares_scanin;
wire spares_scanout;
wire incoming_sign_fx1;
wire [7:0] qcontrol_in;
wire fsqrt_fract_all_ones;
wire [7:0] qcontrol_fx1;
wire qdata_lth_scanin;
wire qdata_lth_scanout;
wire valid_in;
wire valid_lth;
wire [3:0] fdc_pte_cycle;
wire div_flush_lth;
wire [3:1] pe_cycle_in;
wire [3:1] fdc_pe_cycle;
wire engine_running_in;
wire engine_stop;
wire engine_running_lth;
wire engine_on;
wire [7:0] pe_ndq;
wire [3:0] pte_cycle_in;
wire [4:0] control_lth;
wire cntl_lth_scanin;
wire cntl_lth_scanout;
wire [2:0] pe_hmux_sel;
wire b_neg_one;
wire [7:0] pe_xsht_amt;
wire a_neg_max;
wire ovfl_64_in;
wire b_neg_one_lth;
wire finish_raw;
wire ovfl_64_lth;
wire flt_shift_sel_;
wire ovlf_lth_scanin;
wire ovlf_lth_scanout;
wire cla_zero64_lth_;
wire cla_zero32_lth_;
wire fdiv_stall_in;
wire stall_hold;
wire idiv_stall_in;
wire stall_hold_in;
wire [3:0] stall_cnt_raw;
wire [3:0] stall_cnt_in;
wire finish_lth;
wire [3:0] stall_cnt;
wire stall_lth_scanin;
wire stall_lth_scanout;
wire finish_lth_in;
wire idiv_stall_lth;
wire [4:0] control_in;
wire asign_in;
wire bsign_in;
wire ndq_odd_in;
wire data_lth_scanin;
wire data_lth_scanout;
wire ndq_odd_lth;
wire ndq_odd_2lth;
wire [63:0] clth;
wire b0_nor_76;
wire b0_nor_54;
wire b0_nor_32;
wire b0_nor_10;
wire b0_zeroh_;
wire b0_zerol_;
wire b0_zero_;
wire [1:0] b0_cnth;
wire [1:0] b0_cntl;
wire [2:0] b0_cnt;
wire b1_nor_76;
wire b1_nor_54;
wire b1_nor_32;
wire b1_nor_10;
wire b1_zeroh_;
wire b1_zerol_;
wire b1_zero_;
wire [1:0] b1_cnth;
wire [1:0] b1_cntl;
wire [2:0] b1_cnt;
wire b2_nor_76;
wire b2_nor_54;
wire b2_nor_32;
wire b2_nor_10;
wire b2_zeroh_;
wire b2_zerol_;
wire b2_zero_;
wire [1:0] b2_cnth;
wire [1:0] b2_cntl;
wire [2:0] b2_cnt;
wire b3_nor_76;
wire b3_nor_54;
wire b3_nor_32;
wire b3_nor_10;
wire b3_zeroh_;
wire b3_zerol_;
wire b3_zero_;
wire [1:0] b3_cnth;
wire [1:0] b3_cntl;
wire [2:0] b3_cnt;
wire b4_nor_76;
wire b4_nor_54;
wire b4_nor_32;
wire b4_nor_10;
wire b4_zeroh_;
wire b4_zerol_;
wire b4_zero_;
wire [1:0] b4_cnth;
wire [1:0] b4_cntl;
wire [2:0] b4_cnt;
wire b5_nor_76;
wire b5_nor_54;
wire b5_nor_32;
wire b5_nor_10;
wire b5_zeroh_;
wire b5_zerol_;
wire b5_zero_;
wire [1:0] b5_cnth;
wire [1:0] b5_cntl;
wire [2:0] b5_cnt;
wire b6_nor_76;
wire b6_nor_54;
wire b6_nor_32;
wire b6_nor_10;
wire b6_zeroh_;
wire b6_zerol_;
wire b6_zero_;
wire [1:0] b6_cnth;
wire [1:0] b6_cntl;
wire [2:0] b6_cnt;
wire b7_nor_76;
wire b7_nor_54;
wire b7_nor_32;
wire b7_nor_10;
wire b7_zeroh_;
wire b7_zerol_;
wire b7_zero_;
wire [1:0] b7_cnth;
wire [1:0] b7_cntl;
wire [2:0] b7_cnt;
wire b3_0sel;
wire b2_0sel;
wire b1_0sel;
wire b0_0sel;
wire [4:0] cntl0l;
wire b7_0sel;
wire b6_0sel;
wire b5_0sel;
wire b4_0sel;
wire [4:0] cntl0h;
wire cntl0_selh;
wire cntl0_sell;
wire [6:0] cntl0;
wire b7_nand_74;
wire b7_nand_30;
wire b7_ones;
wire b7_ones_;
wire [1:0] b7_cnt1h;
wire [1:0] b7_cnt1l;
wire [2:0] b7_cnt1;
wire b6_nand_74;
wire b6_nand_30;
wire b6_ones;
wire b6_ones_;
wire [1:0] b6_cnt1h;
wire [1:0] b6_cnt1l;
wire [2:0] b6_cnt1;
wire b5_nand_74;
wire b5_nand_30;
wire b5_ones;
wire b5_ones_;
wire [1:0] b5_cnt1h;
wire [1:0] b5_cnt1l;
wire [2:0] b5_cnt1;
wire b4_nand_74;
wire b4_nand_30;
wire b4_ones;
wire b4_ones_;
wire [1:0] b4_cnt1h;
wire [1:0] b4_cnt1l;
wire [2:0] b4_cnt1;
wire b3_nand_74;
wire b3_nand_30;
wire b3_ones;
wire b3_ones_;
wire [1:0] b3_cnt1h;
wire [1:0] b3_cnt1l;
wire [2:0] b3_cnt1;
wire b2_nand_74;
wire b2_nand_30;
wire b2_ones;
wire b2_ones_;
wire [1:0] b2_cnt1h;
wire [1:0] b2_cnt1l;
wire [2:0] b2_cnt1;
wire b1_nand_74;
wire b1_nand_30;
wire b1_ones;
wire b1_ones_;
wire [1:0] b1_cnt1h;
wire [1:0] b1_cnt1l;
wire [2:0] b1_cnt1;
wire b0_nand_74;
wire [1:0] b0_cnt1h;
wire [1:0] b0_cnt1l;
wire [2:0] b0_cnt1;
wire b3_1sel;
wire b2_1sel;
wire b1_1sel;
wire b0_1sel;
wire [4:0] cntl1l;
wire b7_1sel;
wire b6_1sel;
wire b5_1sel;
wire b4_1sel;
wire [4:0] cntl1h;
wire cntl1_selh;
wire [5:0] cntl1;
wire xsht_amt_sel10;
wire xsht_amt_sel11;
wire xsht_amt_sel20;
wire xsht_amt_sel21;
wire [7:0] xsht_amt_in;
wire [7:0] pe_hamt_lth;
wire [7:0] pe_hamt_in;
wire xsht_lth_scanin;
wire xsht_lth_scanout;
wire hamt_lth_scanin;
wire hamt_lth_scanout;
wire [5:0] xsht_ctl_in;
wire xcntl_lth_scanin;
wire xcntl_lth_scanout;
wire engine_valid_fx1;
wire engine_valid_fx2;
wire queue_valid_lth_fx2;
wire engine_valid_lth_fx2;
wire engine_valid_fx3;
wire queue_valid_lth_fx3;
wire engine_valid_lth_fx3;
wire queue_valid_fx1;
wire queue_valid_fx2;
wire q2e_fx3p;
wire xrnd_vld_lth_scanin;
wire xrnd_vld_lth_scanout;
wire [1:0] eround_mode_in;
wire [1:0] qround_mode_lth;
wire [1:0] eround_mode_lth;
wire e_emin_in;
wire q_emin_lth;
wire [1:0] qround_mode_in;
wire q_emin_in;
wire float_sign_in;
wire float_sign_lth;
wire flt_sqrte_kill_dec;
wire inexact_in;
wire final_sticky;
wire final_guard;
wire xrnd_lth_scanin;
wire xrnd_lth_scanout;
wire sticky_pte1;
wire sticky_pte0;
wire final_lsb;
wire flt_rnd00_en;
wire flt_rnd1x_en;
wire fsqrt_special_in;
wire fsqrt_special_lth;
wire spec_sqrt_lth_scanin;
wire spec_sqrt_lth_scanout;
wire cla_64;
wire cin_in_raw;
wire [3:0] fdq00_sum;
wire [3:0] fdq00_carry;
wire [3:0] pr00;
wire [3:0] pr1p;
wire [2:0] qsel1p;
wire [3:0] fdq10_sum;
wire [3:0] fdq10_carry;
wire [3:0] pr10;
wire [2:0] qsel10;
wire [3:0] pr1n;
wire [2:0] qsel1n;
wire engine_start;


// Timing constraints definition :
//   For Inputs  : Required setup to the end of the cycle
//   For Outputs : Actual time the signal leaves block measured from L1CLK rise
//   For pin location : I am assuming dataflow direction is vertical


// *** globals ***
input		l2clk;
input  		scan_in;
input  		tcu_pce_ov;		// scan signals
input  		spc_aclk;
input  		spc_bclk;
input           tcu_scan_en;
output 		scan_out;

input		fac_div_flush_fx3;
input        	fpe_rs2_fmt_fx1_b0;
input		fpf_hi_bof_fx1;
input		fpf_lo_bof_fx1;
input		fpf_sa_xor_sb_fx1;

input		fac_div_valid_fx1;	//  div_valid  divq_valid  |  action
input		fac_divq_valid_fx1;	//  ---------  ----------  |  ---------------------------------------
					//     1           0       |  start divide from FX1   RS1/RS2/control
					//     0           1       |  load  queue  from FX1   RS1/RS2/control
					//     1           1       |  start divide from queue RS1/RS2/control

input  [4:0]	fac_div_control_fx1;   // 0in value -var fac_div_control_fx1[3:0] -val 4'b0000 4'b0010 4'b0100 4'b0101 4'b0110 4'b0111 4'b1000 4'b1010 -active (fac_div_valid_fx1 ^ fac_divq_valid_fx1)
				       // [3:0]  :                            [4] : Thread Group
                                       //  0000  : Float Divide Single
                                       //  0010  : Float Divide Double
                                       //  0100  : Integer Unsigned - 32 bit
                                       //  0101  : Integer   Signed - 32 bit
                                       //  0110  : Integer Unsigned - 64 bit
                                       //  0111  : Integer   Signed - 64 bit
                                       //  1000  : Float SQRT   Single
                                       //  1010  : Float SQRT   Double

input  [1:0]	fpc_rd_mode_fx3;
input		fpc_emin_fx3;

input           div_clken;             // div clken


// *** locals  ***
input  [63:0]	fdd_pe_clth;
input		fdd_cla_zero32_;
input		fdd_cla_zero64_;
input  [63:9]	fdd_result;

input		fdd_fdx_din0;
input		fdd_fdx_din1;
input		fdd_fdx_cin64;

input  [4:0]	fdd_fdq00_10_sum;
input  [4:0]	fdd_fdq00_10_carry;
input  [3:0]	fdd_fdq1p_sum;
input  [3:0]	fdd_fdq1p_carry;
input  [3:0]	fdd_fdq1n_sum;
input  [3:0]	fdd_fdq1n_carry;


// *** globals ***
output		fgu_fdiv_stall;
output [1:0]	fgu_idiv_stall;		// Stall by Thread Group
output		fdc_dec_exp_early;
output		fdc_icc_v_early;
output [1:0]	fdc_xicc_z_early;
output		fdc_finish_int_early;
output		fdc_finish_fltd_early;
output		fdc_finish_flts_early;
output		fdc_flt_inexact;


// *** locals  ***
output		fdc_asign_lth;
output		fdc_bsign_lth;
output		fdc_bsign_lth_;
output		fdc_pe_cycle3;
output		fdc_pe_cmux_sel;
output [2:0]	fdc_pe_smux_sel;
output [5:0]	fdc_pe_xsht_ctl;
output		fdc_ie_fsqrt_valid_even;
output		fdc_ie_fsqrt_valid_even_;
output		fdc_ie_fsqrt_valid_odd;
output		fdc_ie_fsqrt_valid_odd_;
output [4:0]	fdc_ie_rmux_sel;
output [2:0]	fdc_ie_dmux_sel;
output		fdc_flt_increment;
output [1:0]	fdc_pte_clasel;
output		fdc_pte_csa_cin;
output		fdc_pte_cycle2;
output		fdc_emin_lth;
output [2:0]	fdc_pte_qsel;
output		fdc_pte_stall_;

output [1:0]	fdc_flt_round;
output [4:0]	fdc_idiv_ctl;           // 0in bits_on -max 1 -var fdc_idiv_ctl[3:0]
					//  3210   [4] = integer
                                        //  ----
                                        //  0001 : 8000 0000 0000 0000
                                        //  0010 : FFFF FFFF 8000 0000
                                        //  0100 : 0000 0000 7FFF FFFF
                                        //  1000 : 0000 0000 FFFF FFFF

output		fdc_fdx_cin_in;
output [2:0]	fdc_qsel00;
output [2:0]	fdc_qsel1;

output [1:0]	fdc_q_in;
output [1:0]	fdc_qm1_in;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop   = 1'b0;
assign siclk  = spc_aclk;
assign soclk  = spc_bclk;
assign se     = tcu_scan_en;
// end scan


fgu_fdc_ctl_l1clkhdr_ctl_macro clkgen_pm1 (
  .l2clk(l2clk),
  .l1en (div_clken),
  .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fdc_ctl_spare_ctl_macro__num_3 spares  (  // spares: 13 gates + 1 flop for each "num"
  .scan_in(spares_scanin),
  .scan_out(spares_scanout),
  .l1clk(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
  );


assign incoming_sign_fx1= fpf_sa_xor_sb_fx1 & ~fac_div_control_fx1[3];	// Turn off for Square Root

assign qcontrol_in[7:0]	= ({8{ fac_divq_valid_fx1}} & {fsqrt_fract_all_ones,incoming_sign_fx1,fpe_rs2_fmt_fx1_b0,fac_div_control_fx1[4:0]}) |
			  ({8{~fac_divq_valid_fx1}} & qcontrol_fx1[7:0]                                                                   );

fgu_fdc_ctl_msff_ctl_macro__width_8	qdata_lth	 (
 .scan_in(qdata_lth_scanin),
 .scan_out(qdata_lth_scanout),
 .l1clk( l1clk_pm1         ),
 .din  ({qcontrol_in[7:0] }),
 .dout ({qcontrol_fx1[7:0]}),
  .siclk(siclk),
  .soclk(soclk));


// * * * * * * * * * * * * Main Controller * * * * * * * * * * * * 


// *** State control ***

//* * * * * * * * * * * * "pre-engine" (integer only)* * * * *
//
// cycle  0   :  fac_div_valid_fx1  A&B are transmitted to divide hardware
//                                  A loaded into Slth
//                                  B loaded into Clth;
//
// cycle  1   :  pe_cycle[1]        B into CNTL0 and CNTL1 -> compute "lsb";
//                                  A loaded into Clth;
//                                  B loaded into Slth;
//
// cycle  2   :  pe_cycle[2]        A into CNTL0 and CNTL1 -> compute "lsa"; 
//                                  B shifts by "lsb" amount
//                                  A loaded into Slth; 
//                                  Xsht loaded into Clth;  (this is Bsh)
//
// cycle  3   :  pe_cycle[3]        A shifts by "lsa" amount;
//               engine_start       Bsh is XORed to produce positive divisor
//                                  compute ndq = lsb - lsa + 1;
//                                  finished if ndq <= 0;        (ie B > A)
//
//* * * * * * * * * * * * * "engine" * * * * * * * * * * * * * 
//
// See Integer "engine" run-time below for how ndq is computed.
//
// if (even ndq)
//    then X =  ndq / 2
//    else X = (ndq - 1) / 2
//
// for X cycles
//    perform loop
//
//  cycle X+3 :  engine_stop      last loop
//
//* * * * * * * * * * * * "post-engine" * * * * * * * * * * * *
//
//  cycle X+4 :  pte_cycle[3]       load "S0" and "C0" latches into adder latches
//                                  For an odd ndq, we actually compute the last Q and Qm1
//                                  and then load "C1" and "S1" into the adder latches.
//
//  cycle X+5 :  pte_cycle[2]       compute Sign of Remainder
//                                  compute zero remainder (used as Sticky and in correction)
//                                  load Q and Qm1 into adder latches
//                                  make correction if necessary
//                                  turn off valid_lth (new divide will NOT affect result)
//
//  cycle X+6 :  pte_cycle[1]       compute Qf = Q - Qm1 + correction;
//                                  64-bit Integer - load into Result latch
//
//  cycle X+7    pte_cycle[0]       32-bit Integer - Overflow detection and correction
//                                  Floating Point - Round
//
//  cycle X+7/8  fdc_finish         transmit Result
//
//
//* * * * * * * * * * * * Integer "engine" run-time * * * * * * * * * *
// 
// 
// Define : lsa  : number of Leading Sign bits in A (n-1 for negative)
//          lsb  : number of Leading Sign bits in B (n   for negative)
//          nda  : number of digits in A (nda=64-lsa)
//          ndb  : number of digits in B (ndb=64-lsb)
//          ndq  : number of digits in the Quotient Q  (MAX)
// 
// Then ndq = nda - (ndb - 1);
// 
// The minus one comes from the fact that dividing by '1' does not reduce
// the number of significant bits in the dividend (A operand).
// 
// By substitution :
// 
//      ndq = [64 - lsa] - ([64 - lsb] - 1);
//          = lsb - lsa + 1;
// 
// 
// Example :      A = 0000 1111 (+15)    lsa = 4
// (8-bit)        B = 0000 0010 (+2)     lsb = 6
//                ------------------
//                R = 0000 0111 (+7)     notice ndq=3
// 
//                compute ndq = lsb - lsa + 1
//                            =  6  -  4  + 1 
//                            =  3             (this is a MAX ndq computation)
// 
// 
// Example :      A = 0000 1000 (+8)     lsa = 4
// (8-bit)        B = 0000 0011 (+3)     lsb = 6
//                ------------------
//                R = 0000 0010 (+2)     notice ndq=2
// 
//                compute ndq = lsb - lsa + 1
//                            =  6  -  4  + 1 
//                            =  3             (this is a MAX ndq computation)
// 
// 
// Example :      A = 1111 0000 (-16)    lsa = 3  (n-1 for negative)
// (8-bit)        B = 0000 0010 (+2)     lsb = 6
//                ------------------
//                R = 1111 1000 (-8)     notice ndq=4
// 
//                compute ndq = lsb - lsa + 1
//                            =  6  -  3  + 1 
//                            =  4             (this is a MAX ndq computation)
// 
// 
// 
// 
// 
//* * * * * * * * * * * * * Total cycle count * * * * * * * * * * * *
// 
// *** 32-bit Integer Division***
// 
// FX1    transmit of RS1 and RS2
//  3     "pre-engine"
//  X     "engine"        where   X = (lsb-lsa)// 2; {0 to 32 cycles}
//  4     "post-engine"   where   4th cycle is Overflow detection and correction
//  S     "engine-stall"  where   S = 4 - X;  {0 to 4 cycles}  (needed to sync up with bubble)
// FX5    transmit to EXU
// W
// ---
// 10+X+S   {14 to 42 cycles}
//
//
// *** 64-bit Integer Division***
// 
// FX1    transmit of RS1 and RS2
//  3     "pre-engine"
//  X     "engine"        where   X = (lsb-lsa)// 2; {0 to 32 cycles}
//  3     "post-engine"
//  S     "engine-stall"  where   S = 4 - X;  {0 to 4 cycles}  (needed to sync up with bubble)
// FX5    transmit to EXU
// W
// ---
//  9+X+S   {13 to 41 cycles}
// 
// 
// *** Float Double Precision divide and square root***
// 
// FX1    transmit of RS1 and RS2
//  27    "engine"        need 53 mantissa + 1 guard + 1 for 0.1 = 55
//                        27 cycles compute 54 quotient digits.  The last bit is computed during pte_cycle[3].
//  4     "post-engine"
// FB
// FW
// FW1
// ---
// 35 cycles
// 
// 
// *** Float Single Precision divide and square root ***
// 
// FX1    transmit of RS1 and RS2
//  13    "engine"        need 24 mantissa + 1 guard + 1 for 0.1 = 26
//  4     "post-engine"
// FB
// FW
// FW1
// ---
// 21 cycles


assign valid_in           = (fac_div_valid_fx1                                            ) |
                            (valid_lth          & ~fdc_pte_cycle[2]       & ~div_flush_lth);

assign pe_cycle_in[1]     = (fac_div_valid_fx1  &  fac_div_control_fx1[2] & ~fac_divq_valid_fx1) |
                            (fac_div_valid_fx1  &         qcontrol_fx1[2] &  fac_divq_valid_fx1);

assign pe_cycle_in[3:2]   =  fdc_pe_cycle[2:1]                            & {2{~div_flush_lth}};

assign engine_running_in  = (fac_div_valid_fx1  & ~fac_div_control_fx1[2] & ~fac_divq_valid_fx1) |  // start FLT
                            (fac_div_valid_fx1  &        ~qcontrol_fx1[2] &  fac_divq_valid_fx1) |  // start FLT
                            (fdc_pe_cycle[3]    & ~engine_stop            & ~div_flush_lth     ) |  // start INT
                            (engine_running_lth & ~engine_stop            & ~div_flush_lth     );

assign engine_on          =  fdc_pe_cycle[3] | engine_running_lth;

// 0in assert_timer -var (engine_running_lth & (control_lth[2:0] == 3'b000)) -max 13 -message "FDIV/FSQRT engine running > 13 cycles for SP"
// 0in assert_timer -var (engine_running_lth & (control_lth[2:0] == 3'b010)) -max 27 -message "FDIV/FSQRT engine running > 27 cycles for DP"
// 0in assert_timer -var (engine_running_lth & (control_lth[3:2] == 2'b01 )) -max 32 -message "IDIV engine running > 32 cycles"

assign engine_stop        = ((pe_ndq[6:1] == 6'b000000) & engine_on) |
                            ( pe_ndq[7]                 & engine_on);

assign pte_cycle_in[3:1]  = {engine_stop,fdc_pte_cycle[3:2]}                       & {3{~div_flush_lth}};
assign pte_cycle_in[0]    =  fdc_pte_cycle[1] & ~(control_lth[2] & control_lth[1]) &    ~div_flush_lth;

fgu_fdc_ctl_msff_ctl_macro__width_10	cntl_lth	 (
 .scan_in(cntl_lth_scanin),
 .scan_out(cntl_lth_scanout),
 .l1clk( l1clk_pm1                                                                                   ),
 .din  ({valid_in  , pe_cycle_in[3:1]  , engine_running_in  , pte_cycle_in[3:0]  , fac_div_flush_fx3}),
 .dout ({valid_lth , fdc_pe_cycle[3:1] , engine_running_lth , fdc_pte_cycle[3:0] , div_flush_lth    }),
  .siclk(siclk),
  .soclk(soclk));

// 0in bits_on -max 1 -var {fdc_pe_cycle[3:1], engine_running_lth, fdc_pte_cycle[3:0], finish_lth}

// 0in state_transition -var {fac_div_valid_fx1, pe_cycle_in[3:1], engine_running_in} -val {1'b1, 3'b000, 1'b0} -next {1'b0, 3'b001, 1'b0} {1'b0, 3'b000, 1'b1} {1'b0, 3'b000, 1'b0} -match_by_cycle
// 0in state_transition -var  pe_cycle_in[3:1] -val 3'b000 -next 3'b001 3'b000
// 0in state_transition -var  pe_cycle_in[3:1] -val 3'b001 -next 3'b010 3'b000 -match_by_cycle
// 0in state_transition -var  pe_cycle_in[3:1] -val 3'b010 -next 3'b100 3'b000 -match_by_cycle
// 0in state_transition -var {engine_running_in, pe_cycle_in[3:1]} -val {1'b0, 3'b100} -next {1'b1, 3'b000} {1'b0, 3'b000} -match_by_cycle
// 0in state_transition -var {pte_cycle_in[3:0], engine_running_in} -val {4'b0000, 1'b1} -next {4'b1000, 1'b0} {4'b0000, 1'b0}
// 0in state_transition -var  pte_cycle_in[3:0] -val 4'b0000 -next 4'b1000
// 0in state_transition -var  pte_cycle_in[3:0] -val 4'b1000 -next 4'b0100 -match_by_cycle
// 0in state_transition -var  pte_cycle_in[3:0] -val 4'b0100 -next 4'b0010 -match_by_cycle
// 0in state_transition -var {pte_cycle_in[3:0], finish_lth_in} -val {4'b0010, 1'b0} -next {4'b0001, 1'b0} {4'b0000, 1'b1}
// 0in state_transition -var {pte_cycle_in[3:0], finish_lth_in} -val {4'b0001, 1'b0} -next {4'b0000, 1'b1}

assign fdc_pe_cycle3      = fdc_pe_cycle[3];	// Tools issues with single bit buses downstream
assign fdc_pte_cycle2     = fdc_pte_cycle[2];	// Tools issues with single bit buses downstream

assign fdc_pe_cmux_sel    =   fdc_pe_cycle[1]   | fdc_pe_cycle[2];

// For neg B, left shift by 1 to compensate for 'n-1' shift amount
assign fdc_pe_smux_sel[0] =   fdc_pe_cycle[1]   & fdd_pe_clth[63] & control_lth[0];
assign fdc_pe_smux_sel[1] =   fdc_pe_cycle[1]   | fdc_pe_cycle[2];
assign fdc_pe_smux_sel[2] =   fac_div_valid_fx1 & ~fac_divq_valid_fx1;

assign     pe_hmux_sel[0] = ( fac_div_valid_fx1 & ~fac_div_control_fx1[2] &  fac_div_control_fx1[1] & ~fac_divq_valid_fx1) |
                            ( fac_div_valid_fx1 &        ~qcontrol_fx1[2] &         qcontrol_fx1[1] &  fac_divq_valid_fx1);
assign     pe_hmux_sel[1] = ( fac_div_valid_fx1 & ~fac_div_control_fx1[2] & ~fac_div_control_fx1[1] & ~fac_divq_valid_fx1) |
                            ( fac_div_valid_fx1 &        ~qcontrol_fx1[2] &        ~qcontrol_fx1[1] &  fac_divq_valid_fx1);
assign     pe_hmux_sel[2] =  ~fdc_pe_cycle[1]   &  valid_lth;

 
// *** Integer Overflow Detection ***

// fdc_idiv_ctl
      //  3210
      //  ----
      //  0001 : 8000 0000 0000 0000  ovfl_64x
      //  0010 : FFFF FFFF 8000 0000  ovfl_32n
      //  0100 : 0000 0000 7FFF FFFF  ovfl_32p
      //  1000 : 0000 0000 FFFF FFFF  ovfl_32u


// For 64-bit divide, the only OVFL condition exits is :  neg max / -1 
// This results in a constant of "8000 0000 0000 0000" defined on pg 196.

assign b_neg_one       =  fdc_pe_cycle[2] & fdc_bsign_lth &
                         (pe_xsht_amt[6:0] == 7'b0111111);

assign a_neg_max       =  fdc_pe_cycle[3] & fdc_asign_lth &
                         (pe_xsht_amt[6:0] == 7'b1111111);  // xsht_amt is inverted by cycle[3]

assign ovfl_64_in      = ( a_neg_max      &  b_neg_one_lth & ~div_flush_lth) |  // 64-bit divide
                         (~finish_raw     &  ovfl_64_lth   & ~div_flush_lth);

assign fdc_idiv_ctl[0] =  fdc_pte_cycle[0] & ovfl_64_lth   & control_lth[1];

// For 64-bit/32-bit, three OVFL constants are possible.  (see pages 152-154)
// For - signed : if quotient <= (-2^31 - 1) then result = FFFF FFFF 8000 0000 (-2^31    )
// For + signed : if quotient >= ( 2^31    ) then result = 0000 0000 7FFF FFFF ( 2^31 - 1)
// For unsigned : if quotient >= ( 2^32    ) then result = 0000 0000 FFFF FFFF ( 2^32 - 1)

assign fdc_idiv_ctl[1] =  fdc_pte_cycle[0] &  (control_lth[2:0] == 3'b101) &
                          fdd_result[63]   &  (fdd_result[62:31] != 32'hFFFFFFFF)  & ~ovfl_64_lth;

assign fdc_idiv_ctl[2] =  fdc_pte_cycle[0] &  (control_lth[2:0] == 3'b101) &
                       ((~fdd_result[63]   &  (fdd_result[62:31] != 32'h00000000)) |  ovfl_64_lth);

assign fdc_idiv_ctl[3] =  fdc_pte_cycle[0] &  (control_lth[2:0] == 3'b100) &
                                              (fdd_result[63:32] != 32'h00000000);

assign fdc_idiv_ctl[4] =  fdc_pte_cycle[0] & ~control_lth[2] & ~flt_shift_sel_ & ~fdc_flt_increment;

assign fdc_icc_v_early = | fdc_idiv_ctl[3:0];


fgu_fdc_ctl_msff_ctl_macro__width_4	ovlf_lth	 (
 .scan_in(ovlf_lth_scanin),
 .scan_out(ovlf_lth_scanout),
 .l1clk( l1clk_pm1							 ),
 .din  ({ovfl_64_in  , b_neg_one     , fdd_cla_zero64_ , fdd_cla_zero32_}),
 .dout ({ovfl_64_lth , b_neg_one_lth , cla_zero64_lth_ , cla_zero32_lth_}),
  .siclk(siclk),
  .soclk(soclk));


assign fdc_xicc_z_early[1] = ~cla_zero64_lth_;
assign fdc_xicc_z_early[0] = ~cla_zero32_lth_ & ~fdc_icc_v_early;

 
// *** Engine stall ***

// The INTEGER divide has a variable timing dependent on the operand data.
// The divide must provide a STALL signal to the issue logic to ensure no
// collision on the shared FGU to EXU bus.  The timing of the IDIV_STALL
// is given below.
//
//  t-1     t     t+1    t+2    t+3    t+4    t+5    t+6    t+7 
//  -----|------|------|------|------|------|------|------|------|
// idiv  | idiv |  D   |  E   | fx1  | fx2  | fx3  | fx4  | fx5  |
// stall | stall|      |      |      |      |      |      |      |
// in    |      |      |      |engine|pte[3]|pte[2]|pte[1]|finish|
//       |      |      |      | stop |      |      |      |      |
//       |      |      |      |      |      |      |      |      |
//   8/9 | 6/7  | 4/5  | 2/3  | 0/1  |      |      |      |      |
//       |      |      |      |      |      |      |      |      |
//   +0  |  +1  |  +2  |  +3  |  +4  |      |      |      |      |
//
//
// The Floating Point Divide and Square Root has a fixed latency.
// The divide must provide a STALL signal to the issue logic to ensure no
// collision at the W2 port to the FRF.
//
//  t-1     t     t+1    t+2    t+3    t+4 
//  -----|------|------|------|------|------|
// fdiv  | fdiv |  D   |  E   |  M   | fb/B |
// stall | stall|      |      |      |      |
// in    |      |      |      |      |      |
//       |      |      |      |      |      |
//       |pte[3]|pte[2]|pte[1]|pte[0]|finish|
//       |      |      |      |      |      |
//       |      |      |      |      |      |
//   8/9 | 6/7  |      |      |      |      |
//       |      |      |      |      |      |
//   +0  |  +1  |      |      |      |      |
//
//
// at engine_start :
//                    stall_cnt
//                    3 2 1 0
//                    -------
//    ndq = neg   ->  1 1 1 1
//    ndq = 0/1   ->  1 1 1 1    [6:1] = 000 000
//    ndq = 2/3   ->  0 1 1 1          = 000 001
//    ndq = 4/5   ->  0 0 1 1          = 000 010
//    ndq = 6/7   ->  0 0 0 1          = 000 011
//    ndq >=8/9   ->  0 0 0 0          = 000 100   idiv_stall_in


assign fdiv_stall_in     = ((pe_ndq[6:1] == 6'b000000) & engine_on & ~control_lth[2]                  & ~stall_hold);

assign idiv_stall_in     = ((pe_ndq[6:1] == 6'b000100) & engine_on &  control_lth[2] & control_lth[1] & ~stall_hold & ~div_flush_lth) |
                           ((pe_ndq[6:3] == 4'b0000  ) & engine_on &  control_lth[2]                  & ~stall_hold & ~div_flush_lth) |
                           ( pe_ndq[7]                 & engine_on &  control_lth[2]                  & ~stall_hold & ~div_flush_lth);


assign stall_hold_in     = (fdiv_stall_in & ~div_flush_lth              ) |
                           (idiv_stall_in & ~div_flush_lth              ) |
                           (stall_hold    & ~div_flush_lth & ~finish_raw);


assign stall_cnt_raw[3]  = (pe_ndq[6:1] == 6'b000000) |
                           (pe_ndq[7]               );

assign stall_cnt_raw[2]  = (pe_ndq[6:2] == 5'b00000 ) |
                           (pe_ndq[7]               );

assign stall_cnt_raw[1]  = (pe_ndq[6:1] == 6'b000010) |
                           (pe_ndq[6:2] == 5'b00000 ) |
                           (pe_ndq[7]               );

assign stall_cnt_raw[0]  = (pe_ndq[6:3] == 4'b0000  ) |
                           (pe_ndq[7]               );

assign stall_cnt_in[3:0] = ({4{ fdc_pe_cycle[3] &  control_lth[1] & ~div_flush_lth}} &       stall_cnt_raw[3:0] ) |  // INT64 engine_start
                           ({4{ fdc_pe_cycle[3] & ~control_lth[1] & ~div_flush_lth}} & {1'b0,stall_cnt_raw[3:1]}) |  // INT32 engine_start
                           ({4{~fdc_pe_cycle[3] & ~finish_lth     & ~div_flush_lth}} &       stall_cnt[3:0]     ) |
                           ({4{                    finish_lth     & ~div_flush_lth}} & {1'b0,stall_cnt[3:1]    });

fgu_fdc_ctl_msff_ctl_macro__width_8	stall_lth	 (
 .scan_in(stall_lth_scanin),
 .scan_out(stall_lth_scanout),
 .l1clk( l1clk_pm1                                                                           ),
 .din  ({finish_lth_in , fdiv_stall_in  , idiv_stall_in  , stall_hold_in , stall_cnt_in[3:0]}),
 .dout ({finish_lth    , fgu_fdiv_stall , idiv_stall_lth , stall_hold    , stall_cnt[3:0]   }),
  .siclk(siclk),
  .soclk(soclk));


assign fgu_idiv_stall[1]   =   control_lth[4] & idiv_stall_lth;		// Threads 4-7
assign fgu_idiv_stall[0]   =  ~control_lth[4] & idiv_stall_lth;		// Threads 0-3


assign finish_lth_in         =  (fdc_pte_cycle[0]                                                                     & ~div_flush_lth) |
                                (fdc_pte_cycle[1] &                                  control_lth[2] &  control_lth[1] & ~div_flush_lth) |
                                (finish_lth       &  stall_cnt[0]                                                     & ~div_flush_lth);


assign finish_raw            =   finish_lth       & ~stall_cnt[0];

assign fdc_finish_int_early  =  (fdc_pte_cycle[0] & ~stall_cnt[0]                 &  control_lth[2]                  ) |
                                (fdc_pte_cycle[1] & ~stall_cnt[0]                 &  control_lth[2] &  control_lth[1]) |
                                (finish_lth       &  stall_cnt[0] & ~stall_cnt[1] &  control_lth[2]                  );

assign fdc_finish_fltd_early = fdc_pte_cycle[0] &                                   ~control_lth[2] &  control_lth[1];
assign fdc_finish_flts_early = fdc_pte_cycle[0] &                                   ~control_lth[2] & ~control_lth[1];


assign fdc_pte_stall_      =   fdc_pte_cycle[1] |
                               fdc_idiv_ctl[0]  |  fdc_idiv_ctl[1] |  fdc_idiv_ctl[2] |  fdc_idiv_ctl[3] |
                              (fdc_pte_cycle[0] & ~flt_shift_sel_ & ~control_lth[2]) |
                              (fdc_pte_cycle[0] &  fdc_flt_increment               );


// *** State data ***

assign control_in[4:0]    = ({5{ fac_div_valid_fx1 & ~fac_divq_valid_fx1}} & fac_div_control_fx1[4:0]) |
                            ({5{ fac_div_valid_fx1 &  fac_divq_valid_fx1}} &        qcontrol_fx1[4:0]) |
                            ({5{~fac_div_valid_fx1                      }} &         control_lth[4:0]);

assign asign_in           = ( fdc_pe_cycle[2] & fdd_pe_clth[63] &  control_lth[0]   ) |
                            (~fdc_pe_cycle[2] & fdc_asign_lth   & ~fac_div_valid_fx1);

assign bsign_in           = ( fdc_pe_cycle[1] & fdd_pe_clth[63] &  control_lth[0]   ) |
                            (~fdc_pe_cycle[1] & fdc_bsign_lth   & ~fac_div_valid_fx1);

assign ndq_odd_in         = ~pe_ndq[7] & pe_ndq[0];

fgu_fdc_ctl_msff_ctl_macro__width_9	data_lth	 (
 .scan_in(data_lth_scanin),
 .scan_out(data_lth_scanout),
 .l1clk( l1clk_pm1                                                              ),
 .din  ({control_in[4:0] ,asign_in     ,bsign_in     ,ndq_odd_in ,ndq_odd_lth  }),
 .dout ({control_lth[4:0],fdc_asign_lth,fdc_bsign_lth,ndq_odd_lth,ndq_odd_2lth }),
  .siclk(siclk),
  .soclk(soclk));

assign fdc_pte_clasel[0]  =  fdc_pte_cycle[3] & ~ndq_odd_lth;
assign fdc_pte_clasel[1]  =  fdc_pte_cycle[3] &  ndq_odd_lth;

assign fdc_pte_qsel[0]    =  control_lth[2] & ~ndq_odd_2lth;    // INT even
assign fdc_pte_qsel[1]    =  control_lth[2] &  ndq_odd_2lth;    // INT odd
assign fdc_pte_qsel[2]    = ~control_lth[2] &  control_lth[1];  // FLT DP 


assign fdc_bsign_lth_     = ~fdc_bsign_lth;
assign fdc_pte_csa_cin    =  fdc_asign_lth ^ fdc_bsign_lth;


// * * * * * * * * * * * Interface to engine * * * * * * * * * * * 

// integer select by "fdc_pe_cycle[3]" 

// fac_div_control_fx1[3:0] ==
//   [3:0]  :
//    0000  : Float Divide Single
//    0010  : Float Divide Double
//    0100  : Integer Unsigned - 32 bit
//    0101  : Integer   Signed - 32 bit
//    0110  : Integer Unsigned - 64 bit
//    0111  : Integer   Signed - 64 bit
//    1000  : Float SQRT   Single
//    1010  : Float SQRT   Double


assign fdc_ie_rmux_sel[0] = ~fac_div_valid_fx1;                                                  // integer
assign fdc_ie_rmux_sel[1] =  fac_div_valid_fx1 &  fac_div_control_fx1[3] & ~fac_divq_valid_fx1;  // float sqrt
assign fdc_ie_rmux_sel[2] =  fac_div_valid_fx1 & ~fac_div_control_fx1[3] & ~fac_divq_valid_fx1;  // float div
assign fdc_ie_rmux_sel[3] =  fac_div_valid_fx1 &         qcontrol_fx1[3] &  fac_divq_valid_fx1;  // float sqrt
assign fdc_ie_rmux_sel[4] =  fac_div_valid_fx1 &        ~qcontrol_fx1[3] &  fac_divq_valid_fx1;  // float div
											       
assign fdc_ie_dmux_sel[0] = ~fac_div_valid_fx1;                                                  // integer
assign fdc_ie_dmux_sel[1] =  fac_div_valid_fx1 & ~fac_div_control_fx1[3] & ~fac_divq_valid_fx1;  // float div
assign fdc_ie_dmux_sel[2] =  fac_div_valid_fx1 &        ~qcontrol_fx1[3] &  fac_divq_valid_fx1;  // float div


// must be qualified w/ valid so INT is not corrupted by garbage on bus during pe_cycle[3]
assign fdc_ie_fsqrt_valid_even  = (fac_div_valid_fx1 & fac_div_control_fx1[3] &  fpe_rs2_fmt_fx1_b0 & ~fac_divq_valid_fx1) |
                                  (fac_div_valid_fx1 &        qcontrol_fx1[3] &  qcontrol_fx1[5]    &  fac_divq_valid_fx1);

assign fdc_ie_fsqrt_valid_odd   = (fac_div_valid_fx1 & fac_div_control_fx1[3] & ~fpe_rs2_fmt_fx1_b0 & ~fac_divq_valid_fx1) |
                                  (fac_div_valid_fx1 &        qcontrol_fx1[3] & ~qcontrol_fx1[5]    &  fac_divq_valid_fx1);

assign fdc_ie_fsqrt_valid_even_ = ~fdc_ie_fsqrt_valid_even;
assign fdc_ie_fsqrt_valid_odd_  = ~fdc_ie_fsqrt_valid_odd;

 
// * * * * * * * * * * * * start : Integer CNTL0 * * * * * * * * * * * * * 

//reg [6:0] cntl0;
//
//always @ (fdd_pe_clth[63:0])
//
// begin
//
// casex (fdd_pe_clth[63:0])
//  64'b1???????????????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0000000;
//  64'b01??????????????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0000001;
//  64'b001?????????????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0000010;
//  64'b0001????????????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0000011;
//  64'b00001???????????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0000100;
//  64'b000001??????????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0000101;
//  64'b0000001?????????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0000110;
//  64'b00000001????????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0000111;
//
//  64'b000000001???????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0001000;
//  64'b0000000001??????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0001001;
//  64'b00000000001?????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0001010;
//  64'b000000000001????????????????????????????????????????????????????: cntl0[6:0]  =  7'b0001011;
//  64'b0000000000001???????????????????????????????????????????????????: cntl0[6:0]  =  7'b0001100;
//  64'b00000000000001??????????????????????????????????????????????????: cntl0[6:0]  =  7'b0001101;
//  64'b000000000000001?????????????????????????????????????????????????: cntl0[6:0]  =  7'b0001110;
//  64'b0000000000000001????????????????????????????????????????????????: cntl0[6:0]  =  7'b0001111;
//
//  64'b00000000000000001???????????????????????????????????????????????: cntl0[6:0]  =  7'b0010000;
//  64'b000000000000000001??????????????????????????????????????????????: cntl0[6:0]  =  7'b0010001;
//  64'b0000000000000000001?????????????????????????????????????????????: cntl0[6:0]  =  7'b0010010;
//  64'b00000000000000000001????????????????????????????????????????????: cntl0[6:0]  =  7'b0010011;
//  64'b000000000000000000001???????????????????????????????????????????: cntl0[6:0]  =  7'b0010100;
//  64'b0000000000000000000001??????????????????????????????????????????: cntl0[6:0]  =  7'b0010101;
//  64'b00000000000000000000001?????????????????????????????????????????: cntl0[6:0]  =  7'b0010110;
//  64'b000000000000000000000001????????????????????????????????????????: cntl0[6:0]  =  7'b0010111;
//
//  64'b0000000000000000000000001???????????????????????????????????????: cntl0[6:0]  =  7'b0011000;
//  64'b00000000000000000000000001??????????????????????????????????????: cntl0[6:0]  =  7'b0011001;
//  64'b000000000000000000000000001?????????????????????????????????????: cntl0[6:0]  =  7'b0011010;
//  64'b0000000000000000000000000001????????????????????????????????????: cntl0[6:0]  =  7'b0011011;
//  64'b00000000000000000000000000001???????????????????????????????????: cntl0[6:0]  =  7'b0011100;
//  64'b000000000000000000000000000001??????????????????????????????????: cntl0[6:0]  =  7'b0011101;
//  64'b0000000000000000000000000000001?????????????????????????????????: cntl0[6:0]  =  7'b0011110;
//  64'b00000000000000000000000000000001????????????????????????????????: cntl0[6:0]  =  7'b0011111;
//
//  64'b000000000000000000000000000000001???????????????????????????????: cntl0[6:0]  =  7'b0100000;
//  64'b0000000000000000000000000000000001??????????????????????????????: cntl0[6:0]  =  7'b0100001;
//  64'b00000000000000000000000000000000001?????????????????????????????: cntl0[6:0]  =  7'b0100010;
//  64'b000000000000000000000000000000000001????????????????????????????: cntl0[6:0]  =  7'b0100011;
//  64'b0000000000000000000000000000000000001???????????????????????????: cntl0[6:0]  =  7'b0100100;
//  64'b00000000000000000000000000000000000001??????????????????????????: cntl0[6:0]  =  7'b0100101;
//  64'b000000000000000000000000000000000000001?????????????????????????: cntl0[6:0]  =  7'b0100110;
//  64'b0000000000000000000000000000000000000001????????????????????????: cntl0[6:0]  =  7'b0100111;
//
//  64'b00000000000000000000000000000000000000001???????????????????????: cntl0[6:0]  =  7'b0101000;
//  64'b000000000000000000000000000000000000000001??????????????????????: cntl0[6:0]  =  7'b0101001;
//  64'b0000000000000000000000000000000000000000001?????????????????????: cntl0[6:0]  =  7'b0101010;
//  64'b00000000000000000000000000000000000000000001????????????????????: cntl0[6:0]  =  7'b0101011;
//  64'b000000000000000000000000000000000000000000001???????????????????: cntl0[6:0]  =  7'b0101100;
//  64'b0000000000000000000000000000000000000000000001??????????????????: cntl0[6:0]  =  7'b0101101;
//  64'b00000000000000000000000000000000000000000000001?????????????????: cntl0[6:0]  =  7'b0101110;
//  64'b000000000000000000000000000000000000000000000001????????????????: cntl0[6:0]  =  7'b0101111;
//
//  64'b0000000000000000000000000000000000000000000000001???????????????: cntl0[6:0]  =  7'b0110000;
//  64'b00000000000000000000000000000000000000000000000001??????????????: cntl0[6:0]  =  7'b0110001;
//  64'b000000000000000000000000000000000000000000000000001?????????????: cntl0[6:0]  =  7'b0110010;
//  64'b0000000000000000000000000000000000000000000000000001????????????: cntl0[6:0]  =  7'b0110011;
//  64'b00000000000000000000000000000000000000000000000000001???????????: cntl0[6:0]  =  7'b0110100;
//  64'b000000000000000000000000000000000000000000000000000001??????????: cntl0[6:0]  =  7'b0110101;
//  64'b0000000000000000000000000000000000000000000000000000001?????????: cntl0[6:0]  =  7'b0110110;
//  64'b00000000000000000000000000000000000000000000000000000001????????: cntl0[6:0]  =  7'b0110111;
//
//  64'b000000000000000000000000000000000000000000000000000000001???????: cntl0[6:0]  =  7'b0111000;
//  64'b0000000000000000000000000000000000000000000000000000000001??????: cntl0[6:0]  =  7'b0111001;
//  64'b00000000000000000000000000000000000000000000000000000000001?????: cntl0[6:0]  =  7'b0111010;
//  64'b000000000000000000000000000000000000000000000000000000000001????: cntl0[6:0]  =  7'b0111011;
//  64'b0000000000000000000000000000000000000000000000000000000000001???: cntl0[6:0]  =  7'b0111100;
//  64'b00000000000000000000000000000000000000000000000000000000000001??: cntl0[6:0]  =  7'b0111101;
//  64'b000000000000000000000000000000000000000000000000000000000000001?: cntl0[6:0]  =  7'b0111110;
//  64'b0000000000000000000000000000000000000000000000000000000000000001: cntl0[6:0]  =  7'b0111111;
//
//  64'b0000000000000000000000000000000000000000000000000000000000000000: cntl0[6:0]  =  7'b1000000;
//
//  default:                                                              cntl0[6:0]  =  7'bxxxxxxx;
//
// endcase
//
//end


// The real count leading zero (CNTL0) circuit must be coded at the gate level.
// For each 8-bit byte, a 3-bit count and an "all zero" will be computed.  The
// "all zero" will then be used to find which byte contains the leading 1.
// The 3-bit count from each byte will be muxed using those "all zero" controls
// to form the 3 LSB's of the CNTL0.  The upper 4 bits of the CNTL0 are 
// computed directly from the byte "all zero" controls.  See the truth tables
// below for more details.
//
//                                    byte
//         clth[7:0]    |  cnt[2:0]   zero
//     -----------------|-----------------
//     1 x x x x x x x  |   0 0 0      0
//     0 1 x x x x x x  |   0 0 1      0
//     0 0 1 x x x x x  |   0 1 0      0
//     0 0 0 1 x x x x  |   0 1 1      0
//     0 0 0 0 1 x x x  |   1 0 0      0
//     0 0 0 0 0 1 x x  |   1 0 1      0
//     0 0 0 0 0 0 1 x  |   1 1 0      0
//     0 0 0 0 0 0 0 1  |   1 1 1      0
//     0 0 0 0 0 0 0 0  |   0 0 0      1
//
//
//          Byte Zero_
//    z7 z6 z5 z4 z3 z2 z1 z0  |   cnt[6:3]
//    -------------------------|-------------
//    1  x  x  x  x  x  x  x   |   0 0 0 0
//    0  1  x  x  x  x  x  x   |   0 0 0 1
//    0  0  1  x  x  x  x  x   |   0 0 1 0
//    0  0  0  1  x  x  x  x   |   0 0 1 1
//    0  0  0  0  1  x  x  x   |   0 1 0 0
//    0  0  0  0  0  1  x  x   |   0 1 0 1
//    0  0  0  0  0  0  1  x   |   0 1 1 0
//    0  0  0  0  0  0  0  1   |   0 1 1 1
//    0  0  0  0  0  0  0  0   |   1 x x x (divide ENDS!)
//
//
// Byte Zero_ is an 8-way OR of all bits in that byte.
// This can be accomplished by 4 * Nor2 + Nand4
//
// In order to compute the 3-bit count, we must further
// divide the byte down into an upper and lower half.
//
// Estimated critical path :
//    NOR2 + NAND4 + PE(3->4) + MUX4 + MUX2 + MUX3(merge CNTL0 + CNTL1)


assign clth[63:0] = fdd_pe_clth[63:0];


// ************************ BYTE 0 => 07:00 **************************

assign b0_nor_76  = ~(clth[7] | clth[6]);
assign b0_nor_54  = ~(clth[5] | clth[4]);
assign b0_nor_32  = ~(clth[3] | clth[2]);
assign b0_nor_10  = ~(clth[1] | clth[0]);

assign b0_zeroh_  = ~(b0_nor_76 & b0_nor_54);
assign b0_zerol_  = ~(b0_nor_32 & b0_nor_10);
assign b0_zero_   = ~(b0_nor_76 & b0_nor_54 & b0_nor_32 & b0_nor_10);

assign b0_cnth[0] =  (~clth[7] &  clth[6]                        ) | 
                     (~clth[7] &             ~clth[5] &  clth[4]);

assign b0_cnth[1] =  (~clth[7] & ~clth[6] &  clth[5]            ) | 
                     (~clth[7] & ~clth[6] &              clth[4]);

assign b0_cntl[0] =  (~clth[3] &  clth[2]                        ) | 
                     (~clth[3] &             ~clth[1] &  clth[0]);

assign b0_cntl[1] =  (~clth[3] & ~clth[2] &  clth[1]            ) | 
                     (~clth[3] & ~clth[2] &              clth[0]);

assign b0_cnt[0]  =  ( b0_zeroh_ & b0_cnth[0]) |
                     (~b0_zeroh_ & b0_cntl[0]);

assign b0_cnt[1]  =  ( b0_zeroh_ & b0_cnth[1]) |
                     (~b0_zeroh_ & b0_cntl[1]);

assign b0_cnt[2]  =  (~b0_zeroh_ & b0_zerol_);


// ************************ BYTE 1 => 15:08 **************************

assign b1_nor_76  = ~(clth[15] | clth[14]);
assign b1_nor_54  = ~(clth[13] | clth[12]);
assign b1_nor_32  = ~(clth[11] | clth[10]);
assign b1_nor_10  = ~(clth[9] | clth[8]);

assign b1_zeroh_  = ~(b1_nor_76 & b1_nor_54);
assign b1_zerol_  = ~(b1_nor_32 & b1_nor_10);
assign b1_zero_   = ~(b1_nor_76 & b1_nor_54 & b1_nor_32 & b1_nor_10);

assign b1_cnth[0] =  (~clth[15] &  clth[14]                        ) | 
                     (~clth[15] &             ~clth[13] &  clth[12]);

assign b1_cnth[1] =  (~clth[15] & ~clth[14] &  clth[13]            ) | 
                     (~clth[15] & ~clth[14] &              clth[12]);

assign b1_cntl[0] =  (~clth[11] &  clth[10]                        ) | 
                     (~clth[11] &             ~clth[9] &  clth[8]);

assign b1_cntl[1] =  (~clth[11] & ~clth[10] &  clth[9]            ) | 
                     (~clth[11] & ~clth[10] &              clth[8]);

assign b1_cnt[0]  =  ( b1_zeroh_ & b1_cnth[0]) |
                     (~b1_zeroh_ & b1_cntl[0]);

assign b1_cnt[1]  =  ( b1_zeroh_ & b1_cnth[1]) |
                     (~b1_zeroh_ & b1_cntl[1]);

assign b1_cnt[2]  =  (~b1_zeroh_ & b1_zerol_);


// ************************ BYTE 2 => 23:16 **************************

assign b2_nor_76  = ~(clth[23] | clth[22]);
assign b2_nor_54  = ~(clth[21] | clth[20]);
assign b2_nor_32  = ~(clth[19] | clth[18]);
assign b2_nor_10  = ~(clth[17] | clth[16]);

assign b2_zeroh_  = ~(b2_nor_76 & b2_nor_54);
assign b2_zerol_  = ~(b2_nor_32 & b2_nor_10);
assign b2_zero_   = ~(b2_nor_76 & b2_nor_54 & b2_nor_32 & b2_nor_10);

assign b2_cnth[0] =  (~clth[23] &  clth[22]                        ) | 
                     (~clth[23] &             ~clth[21] &  clth[20]);

assign b2_cnth[1] =  (~clth[23] & ~clth[22] &  clth[21]            ) | 
                     (~clth[23] & ~clth[22] &              clth[20]);

assign b2_cntl[0] =  (~clth[19] &  clth[18]                        ) | 
                     (~clth[19] &             ~clth[17] &  clth[16]);

assign b2_cntl[1] =  (~clth[19] & ~clth[18] &  clth[17]            ) | 
                     (~clth[19] & ~clth[18] &              clth[16]);

assign b2_cnt[0]  =  ( b2_zeroh_ & b2_cnth[0]) |
                     (~b2_zeroh_ & b2_cntl[0]);

assign b2_cnt[1]  =  ( b2_zeroh_ & b2_cnth[1]) |
                     (~b2_zeroh_ & b2_cntl[1]);

assign b2_cnt[2]  =  (~b2_zeroh_ & b2_zerol_);


// ************************ BYTE 3 => 31:24 **************************

assign b3_nor_76  = ~(clth[31] | clth[30]);
assign b3_nor_54  = ~(clth[29] | clth[28]);
assign b3_nor_32  = ~(clth[27] | clth[26]);
assign b3_nor_10  = ~(clth[25] | clth[24]);

assign b3_zeroh_  = ~(b3_nor_76 & b3_nor_54);
assign b3_zerol_  = ~(b3_nor_32 & b3_nor_10);
assign b3_zero_   = ~(b3_nor_76 & b3_nor_54 & b3_nor_32 & b3_nor_10);

assign b3_cnth[0] =  (~clth[31] &  clth[30]                        ) | 
                     (~clth[31] &             ~clth[29] &  clth[28]);

assign b3_cnth[1] =  (~clth[31] & ~clth[30] &  clth[29]            ) | 
                     (~clth[31] & ~clth[30] &              clth[28]);

assign b3_cntl[0] =  (~clth[27] &  clth[26]                        ) | 
                     (~clth[27] &             ~clth[25] &  clth[24]);

assign b3_cntl[1] =  (~clth[27] & ~clth[26] &  clth[25]            ) | 
                     (~clth[27] & ~clth[26] &              clth[24]);

assign b3_cnt[0]  =  ( b3_zeroh_ & b3_cnth[0]) |
                     (~b3_zeroh_ & b3_cntl[0]);

assign b3_cnt[1]  =  ( b3_zeroh_ & b3_cnth[1]) |
                     (~b3_zeroh_ & b3_cntl[1]);

assign b3_cnt[2]  =  (~b3_zeroh_ & b3_zerol_);


// ************************ BYTE 4 => 39:32 **************************

assign b4_nor_76  = ~(clth[39] | clth[38]);
assign b4_nor_54  = ~(clth[37] | clth[36]);
assign b4_nor_32  = ~(clth[35] | clth[34]);
assign b4_nor_10  = ~(clth[33] | clth[32]);

assign b4_zeroh_  = ~(b4_nor_76 & b4_nor_54);
assign b4_zerol_  = ~(b4_nor_32 & b4_nor_10);
assign b4_zero_   = ~(b4_nor_76 & b4_nor_54 & b4_nor_32 & b4_nor_10);

assign b4_cnth[0] =  (~clth[39] &  clth[38]                        ) | 
                     (~clth[39] &             ~clth[37] &  clth[36]);

assign b4_cnth[1] =  (~clth[39] & ~clth[38] &  clth[37]            ) | 
                     (~clth[39] & ~clth[38] &              clth[36]);

assign b4_cntl[0] =  (~clth[35] &  clth[34]                        ) | 
                     (~clth[35] &             ~clth[33] &  clth[32]);

assign b4_cntl[1] =  (~clth[35] & ~clth[34] &  clth[33]            ) | 
                     (~clth[35] & ~clth[34] &              clth[32]);

assign b4_cnt[0]  =  ( b4_zeroh_ & b4_cnth[0]) |
                     (~b4_zeroh_ & b4_cntl[0]);

assign b4_cnt[1]  =  ( b4_zeroh_ & b4_cnth[1]) |
                     (~b4_zeroh_ & b4_cntl[1]);

assign b4_cnt[2]  =  (~b4_zeroh_ & b4_zerol_);


// ************************ BYTE 5 => 47:40 **************************

assign b5_nor_76  = ~(clth[47] | clth[46]);
assign b5_nor_54  = ~(clth[45] | clth[44]);
assign b5_nor_32  = ~(clth[43] | clth[42]);
assign b5_nor_10  = ~(clth[41] | clth[40]);

assign b5_zeroh_  = ~(b5_nor_76 & b5_nor_54);
assign b5_zerol_  = ~(b5_nor_32 & b5_nor_10);
assign b5_zero_   = ~(b5_nor_76 & b5_nor_54 & b5_nor_32 & b5_nor_10);

assign b5_cnth[0] =  (~clth[47] &  clth[46]                        ) | 
                     (~clth[47] &             ~clth[45] &  clth[44]);

assign b5_cnth[1] =  (~clth[47] & ~clth[46] &  clth[45]            ) | 
                     (~clth[47] & ~clth[46] &              clth[44]);

assign b5_cntl[0] =  (~clth[43] &  clth[42]                        ) | 
                     (~clth[43] &             ~clth[41] &  clth[40]);

assign b5_cntl[1] =  (~clth[43] & ~clth[42] &  clth[41]            ) | 
                     (~clth[43] & ~clth[42] &              clth[40]);

assign b5_cnt[0]  =  ( b5_zeroh_ & b5_cnth[0]) |
                     (~b5_zeroh_ & b5_cntl[0]);

assign b5_cnt[1]  =  ( b5_zeroh_ & b5_cnth[1]) |
                     (~b5_zeroh_ & b5_cntl[1]);

assign b5_cnt[2]  =  (~b5_zeroh_ & b5_zerol_);


// ************************ BYTE 6 => 55:48 **************************

assign b6_nor_76  = ~(clth[55] | clth[54]);
assign b6_nor_54  = ~(clth[53] | clth[52]);
assign b6_nor_32  = ~(clth[51] | clth[50]);
assign b6_nor_10  = ~(clth[49] | clth[48]);

assign b6_zeroh_  = ~(b6_nor_76 & b6_nor_54);
assign b6_zerol_  = ~(b6_nor_32 & b6_nor_10);
assign b6_zero_   = ~(b6_nor_76 & b6_nor_54 & b6_nor_32 & b6_nor_10);

assign b6_cnth[0] =  (~clth[55] &  clth[54]                        ) | 
                     (~clth[55] &             ~clth[53] &  clth[52]);

assign b6_cnth[1] =  (~clth[55] & ~clth[54] &  clth[53]            ) | 
                     (~clth[55] & ~clth[54] &              clth[52]);

assign b6_cntl[0] =  (~clth[51] &  clth[50]                        ) | 
                     (~clth[51] &             ~clth[49] &  clth[48]);

assign b6_cntl[1] =  (~clth[51] & ~clth[50] &  clth[49]            ) | 
                     (~clth[51] & ~clth[50] &              clth[48]);

assign b6_cnt[0]  =  ( b6_zeroh_ & b6_cnth[0]) |
                     (~b6_zeroh_ & b6_cntl[0]);

assign b6_cnt[1]  =  ( b6_zeroh_ & b6_cnth[1]) |
                     (~b6_zeroh_ & b6_cntl[1]);

assign b6_cnt[2]  =  (~b6_zeroh_ & b6_zerol_);


// ************************ BYTE 7 => 63:56 **************************

assign b7_nor_76  = ~(clth[63] | clth[62]);
assign b7_nor_54  = ~(clth[61] | clth[60]);
assign b7_nor_32  = ~(clth[59] | clth[58]);
assign b7_nor_10  = ~(clth[57] | clth[56]);

assign b7_zeroh_  = ~(b7_nor_76 & b7_nor_54);
assign b7_zerol_  = ~(b7_nor_32 & b7_nor_10);
assign b7_zero_   = ~(b7_nor_76 & b7_nor_54 & b7_nor_32 & b7_nor_10);

assign b7_cnth[0] =  (~clth[63] &  clth[62]                        ) | 
                     (~clth[63] &             ~clth[61] &  clth[60]);

assign b7_cnth[1] =  (~clth[63] & ~clth[62] &  clth[61]            ) | 
                     (~clth[63] & ~clth[62] &              clth[60]);

assign b7_cntl[0] =  (~clth[59] &  clth[58]                        ) | 
                     (~clth[59] &             ~clth[57] &  clth[56]);

assign b7_cntl[1] =  (~clth[59] & ~clth[58] &  clth[57]            ) | 
                     (~clth[59] & ~clth[58] &              clth[56]);

assign b7_cnt[0]  =  ( b7_zeroh_ & b7_cnth[0]) |
                     (~b7_zeroh_ & b7_cntl[0]);

assign b7_cnt[1]  =  ( b7_zeroh_ & b7_cnth[1]) |
                     (~b7_zeroh_ & b7_cntl[1]);

assign b7_cnt[2]  =  (~b7_zeroh_ & b7_zerol_);


// ************************  Global CNTL0   **************************

// When CNTL0[6] = 1   all other bits become a DON'T CARE

assign b3_0sel     =  b3_zero_                        ;
assign b2_0sel     = ~b3_zero_ &  b2_zero_            ;
assign b1_0sel     = ~b3_zero_ & ~b2_zero_ &  b1_zero_;
assign b0_0sel     = ~b3_zero_ & ~b2_zero_ & ~b1_zero_;

assign cntl0l[4:0] = ({5{b3_0sel}} & {2'b00,b3_cnt[2:0]}) |
                     ({5{b2_0sel}} & {2'b01,b2_cnt[2:0]}) |
                     ({5{b1_0sel}} & {2'b10,b1_cnt[2:0]}) |
                     ({5{b0_0sel}} & {2'b11,b0_cnt[2:0]});


assign b7_0sel     =  b7_zero_                        ;
assign b6_0sel     = ~b7_zero_ &  b6_zero_            ;
assign b5_0sel     = ~b7_zero_ & ~b6_zero_ &  b5_zero_;
assign b4_0sel     = ~b7_zero_ & ~b6_zero_ & ~b5_zero_;

assign cntl0h[4:0] = ({5{b7_0sel}} & {2'b00,b7_cnt[2:0]}) |
                     ({5{b6_0sel}} & {2'b01,b6_cnt[2:0]}) |
                     ({5{b5_0sel}} & {2'b10,b5_cnt[2:0]}) |
                     ({5{b4_0sel}} & {2'b11,b4_cnt[2:0]});

assign cntl0_selh  =  b7_zero_ | b6_zero_ | b5_zero_ | b4_zero_;
assign cntl0_sell  =  b3_zero_ | b2_zero_ | b1_zero_ | b0_zero_;
assign cntl0[6]    = ~(cntl0_selh | cntl0_sell);

assign cntl0[5:0]  = ({6{ cntl0_selh}} & {1'b0, cntl0h[4:0]}) |
                     ({6{~cntl0_selh}} & {1'b1, cntl0l[4:0]});


// * * * * * * * * * * * * End   : Integer CNTL0 * * * * * * * * * * * * * 

 
// * * * * * * * * * * * * Start : Integer CNTL1 * * * * * * * * * * * * * 

//reg [6:0] cntl1;
//
//always @ (fdd_pe_clth[63:0])
//
// begin
//
//
// casex (fdd_pe_clth[63:0])
//  64'b0???????????????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000000;
//
//  64'b10??????????????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000000;
//  64'b110?????????????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000001;
//  64'b1110????????????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000010;
//  64'b11110???????????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000011;
//  64'b111110??????????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000100;
//  64'b1111110?????????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000101;
//  64'b11111110????????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000110;
//  64'b111111110???????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0000111;
//
//  64'b1111111110??????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0001000;
//  64'b11111111110?????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0001001;
//  64'b111111111110????????????????????????????????????????????????????: cntl1[6:0]  =  7'b0001010;
//  64'b1111111111110???????????????????????????????????????????????????: cntl1[6:0]  =  7'b0001011;
//  64'b11111111111110??????????????????????????????????????????????????: cntl1[6:0]  =  7'b0001100;
//  64'b111111111111110?????????????????????????????????????????????????: cntl1[6:0]  =  7'b0001101;
//  64'b1111111111111110????????????????????????????????????????????????: cntl1[6:0]  =  7'b0001110;
//  64'b11111111111111110???????????????????????????????????????????????: cntl1[6:0]  =  7'b0001111;
//
//  64'b111111111111111110??????????????????????????????????????????????: cntl1[6:0]  =  7'b0010000;
//  64'b1111111111111111110?????????????????????????????????????????????: cntl1[6:0]  =  7'b0010001;
//  64'b11111111111111111110????????????????????????????????????????????: cntl1[6:0]  =  7'b0010010;
//  64'b111111111111111111110???????????????????????????????????????????: cntl1[6:0]  =  7'b0010011;
//  64'b1111111111111111111110??????????????????????????????????????????: cntl1[6:0]  =  7'b0010100;
//  64'b11111111111111111111110?????????????????????????????????????????: cntl1[6:0]  =  7'b0010101;
//  64'b111111111111111111111110????????????????????????????????????????: cntl1[6:0]  =  7'b0010110;
//  64'b1111111111111111111111110???????????????????????????????????????: cntl1[6:0]  =  7'b0010111;
//
//  64'b11111111111111111111111110??????????????????????????????????????: cntl1[6:0]  =  7'b0011000;
//  64'b111111111111111111111111110?????????????????????????????????????: cntl1[6:0]  =  7'b0011001;
//  64'b1111111111111111111111111110????????????????????????????????????: cntl1[6:0]  =  7'b0011010;
//  64'b11111111111111111111111111110???????????????????????????????????: cntl1[6:0]  =  7'b0011011;
//  64'b111111111111111111111111111110??????????????????????????????????: cntl1[6:0]  =  7'b0011100;
//  64'b1111111111111111111111111111110?????????????????????????????????: cntl1[6:0]  =  7'b0011101;
//  64'b11111111111111111111111111111110????????????????????????????????: cntl1[6:0]  =  7'b0011110;
//  64'b111111111111111111111111111111110???????????????????????????????: cntl1[6:0]  =  7'b0011111;
//
//  64'b1111111111111111111111111111111110??????????????????????????????: cntl1[6:0]  =  7'b0100000;
//  64'b11111111111111111111111111111111110?????????????????????????????: cntl1[6:0]  =  7'b0100001;
//  64'b111111111111111111111111111111111110????????????????????????????: cntl1[6:0]  =  7'b0100010;
//  64'b1111111111111111111111111111111111110???????????????????????????: cntl1[6:0]  =  7'b0100011;
//  64'b11111111111111111111111111111111111110??????????????????????????: cntl1[6:0]  =  7'b0100100;
//  64'b111111111111111111111111111111111111110?????????????????????????: cntl1[6:0]  =  7'b0100101;
//  64'b1111111111111111111111111111111111111110????????????????????????: cntl1[6:0]  =  7'b0100110;
//  64'b11111111111111111111111111111111111111110???????????????????????: cntl1[6:0]  =  7'b0100111;
//
//  64'b111111111111111111111111111111111111111110??????????????????????: cntl1[6:0]  =  7'b0101000;
//  64'b1111111111111111111111111111111111111111110?????????????????????: cntl1[6:0]  =  7'b0101001;
//  64'b11111111111111111111111111111111111111111110????????????????????: cntl1[6:0]  =  7'b0101010;
//  64'b111111111111111111111111111111111111111111110???????????????????: cntl1[6:0]  =  7'b0101011;
//  64'b1111111111111111111111111111111111111111111110??????????????????: cntl1[6:0]  =  7'b0101100;
//  64'b11111111111111111111111111111111111111111111110?????????????????: cntl1[6:0]  =  7'b0101101;
//  64'b111111111111111111111111111111111111111111111110????????????????: cntl1[6:0]  =  7'b0101110;
//  64'b1111111111111111111111111111111111111111111111110???????????????: cntl1[6:0]  =  7'b0101111;
//
//  64'b11111111111111111111111111111111111111111111111110??????????????: cntl1[6:0]  =  7'b0110000;
//  64'b111111111111111111111111111111111111111111111111110?????????????: cntl1[6:0]  =  7'b0110001;
//  64'b1111111111111111111111111111111111111111111111111110????????????: cntl1[6:0]  =  7'b0110010;
//  64'b11111111111111111111111111111111111111111111111111110???????????: cntl1[6:0]  =  7'b0110011;
//  64'b111111111111111111111111111111111111111111111111111110??????????: cntl1[6:0]  =  7'b0110100;
//  64'b1111111111111111111111111111111111111111111111111111110?????????: cntl1[6:0]  =  7'b0110101;
//  64'b11111111111111111111111111111111111111111111111111111110????????: cntl1[6:0]  =  7'b0110110;
//  64'b111111111111111111111111111111111111111111111111111111110???????: cntl1[6:0]  =  7'b0110111;
//
//  64'b1111111111111111111111111111111111111111111111111111111110??????: cntl1[6:0]  =  7'b0111000;
//  64'b11111111111111111111111111111111111111111111111111111111110?????: cntl1[6:0]  =  7'b0111001;
//  64'b111111111111111111111111111111111111111111111111111111111110????: cntl1[6:0]  =  7'b0111010;
//  64'b1111111111111111111111111111111111111111111111111111111111110???: cntl1[6:0]  =  7'b0111011;
//  64'b11111111111111111111111111111111111111111111111111111111111110??: cntl1[6:0]  =  7'b0111100;
//  64'b111111111111111111111111111111111111111111111111111111111111110?: cntl1[6:0]  =  7'b0111101;
//  64'b1111111111111111111111111111111111111111111111111111111111111110: cntl1[6:0]  =  7'b0111110;
//  64'b1111111111111111111111111111111111111111111111111111111111111111: cntl1[6:0]  =  7'b0111111;
//
//  default:                                                              cntl1[6:0]  =  7'b0000000;
//
// endcase
//
//end


// The count leading one (CNTL1) here must compute "n-1"
// leading 1's.  To do this, each local byte will receive
// an offset input.
// Note : If clth[63] = 0   then CNTL1 is a DON'T CARE

//                                    byte
//         clth[7:0]    |  cnt[2:0]   ones
//     -----------------|-----------------
//     0 x x x x x x x  |   0 0 0      0
//     1 0 x x x x x x  |   0 0 1      0
//     1 1 0 x x x x x  |   0 1 0      0
//     1 1 1 0 x x x x  |   0 1 1      0
//     1 1 1 1 0 x x x  |   1 0 0      0
//     1 1 1 1 1 0 x x  |   1 0 1      0
//     1 1 1 1 1 1 0 x  |   1 1 0      0
//     1 1 1 1 1 1 1 0  |   1 1 1      0
//     1 1 1 1 1 1 1 1  |   0 0 0      1    (byte 0 is '111' here)
//
//
//          Byte Ones_
//    z7 z6 z5 z4 z3 z2 z1 z0  |   cnt[6:3]
//    -------------------------|-------------
//    1  x  x  x  x  x  x  x   |   0 0 0 0
//    0  1  x  x  x  x  x  x   |   0 0 0 1
//    0  0  1  x  x  x  x  x   |   0 0 1 0
//    0  0  0  1  x  x  x  x   |   0 0 1 1
//    0  0  0  0  1  x  x  x   |   0 1 0 0
//    0  0  0  0  0  1  x  x   |   0 1 0 1
//    0  0  0  0  0  0  1  x   |   0 1 1 0
//    0  0  0  0  0  0  0  1   |   0 1 1 1
//    0  0  0  0  0  0  0  0   |   1 x x x  (divide ENDS!)
//
//
// Estimated critical path :
//    NAND4 + NOR2 + INV + PE(3->4) + MUX4 + MUX2 + MUX3(merge CNTL0 + CNTL1)


// ************************ BYTE 7 => 62:55 **************************

assign b7_nand_74  = ~(clth[62] & clth[61] & clth[60] & clth[59]);
assign b7_nand_30  = ~(clth[58] & clth[57] & clth[56] & clth[55]);

assign b7_ones     = ~(b7_nand_74 | b7_nand_30);
assign b7_ones_    = ~b7_ones;

assign b7_cnt1h[0] =  ( clth[62] & ~clth[61]                        ) | 
                      ( clth[62] &              clth[60] & ~clth[59]);

assign b7_cnt1h[1] =  ( clth[62] &  clth[61] & ~clth[60]            ) | 
                      ( clth[62] &  clth[61] &             ~clth[59]);

assign b7_cnt1l[0] =  ( clth[58] & ~clth[57]                        ) | 
                      ( clth[58] &              clth[56] & ~clth[55]);

assign b7_cnt1l[1] =  ( clth[58] &  clth[57] & ~clth[56]            ) | 
                      ( clth[58] &  clth[57] &             ~clth[55]);

assign b7_cnt1[0]  =  ( b7_nand_74 & b7_cnt1h[0]) |
                      (~b7_nand_74 & b7_cnt1l[0]);

assign b7_cnt1[1]  =  ( b7_nand_74 & b7_cnt1h[1]) |
                      (~b7_nand_74 & b7_cnt1l[1]);

assign b7_cnt1[2]  =  (~b7_nand_74 & b7_nand_30);


// ************************ BYTE 6 => 54:47 **************************

assign b6_nand_74  = ~(clth[54] & clth[53] & clth[52] & clth[51]);
assign b6_nand_30  = ~(clth[50] & clth[49] & clth[48] & clth[47]);

assign b6_ones     = ~(b6_nand_74 | b6_nand_30);
assign b6_ones_    = ~b6_ones;

assign b6_cnt1h[0] =  ( clth[54] & ~clth[53]                        ) | 
                      ( clth[54] &              clth[52] & ~clth[51]);

assign b6_cnt1h[1] =  ( clth[54] &  clth[53] & ~clth[52]            ) | 
                      ( clth[54] &  clth[53] &             ~clth[51]);

assign b6_cnt1l[0] =  ( clth[50] & ~clth[49]                        ) | 
                      ( clth[50] &              clth[48] & ~clth[47]);

assign b6_cnt1l[1] =  ( clth[50] &  clth[49] & ~clth[48]            ) | 
                      ( clth[50] &  clth[49] &             ~clth[47]);

assign b6_cnt1[0]  =  ( b6_nand_74 & b6_cnt1h[0]) |
                      (~b6_nand_74 & b6_cnt1l[0]);

assign b6_cnt1[1]  =  ( b6_nand_74 & b6_cnt1h[1]) |
                      (~b6_nand_74 & b6_cnt1l[1]);

assign b6_cnt1[2]  =  (~b6_nand_74 & b6_nand_30);


// ************************ BYTE 5 => 46:39 **************************

assign b5_nand_74  = ~(clth[46] & clth[45] & clth[44] & clth[43]);
assign b5_nand_30  = ~(clth[42] & clth[41] & clth[40] & clth[39]);

assign b5_ones     = ~(b5_nand_74 | b5_nand_30);
assign b5_ones_    = ~b5_ones;

assign b5_cnt1h[0] =  ( clth[46] & ~clth[45]                        ) | 
                      ( clth[46] &              clth[44] & ~clth[43]);

assign b5_cnt1h[1] =  ( clth[46] &  clth[45] & ~clth[44]            ) | 
                      ( clth[46] &  clth[45] &             ~clth[43]);

assign b5_cnt1l[0] =  ( clth[42] & ~clth[41]                        ) | 
                      ( clth[42] &              clth[40] & ~clth[39]);

assign b5_cnt1l[1] =  ( clth[42] &  clth[41] & ~clth[40]            ) | 
                      ( clth[42] &  clth[41] &             ~clth[39]);

assign b5_cnt1[0]  =  ( b5_nand_74 & b5_cnt1h[0]) |
                      (~b5_nand_74 & b5_cnt1l[0]);

assign b5_cnt1[1]  =  ( b5_nand_74 & b5_cnt1h[1]) |
                      (~b5_nand_74 & b5_cnt1l[1]);

assign b5_cnt1[2]  =  (~b5_nand_74 & b5_nand_30);


// ************************ BYTE 4 => 38:31 **************************

assign b4_nand_74  = ~(clth[38] & clth[37] & clth[36] & clth[35]);
assign b4_nand_30  = ~(clth[34] & clth[33] & clth[32] & clth[31]);

assign b4_ones     = ~(b4_nand_74 | b4_nand_30);
assign b4_ones_    = ~b4_ones;

assign b4_cnt1h[0] =  ( clth[38] & ~clth[37]                        ) | 
                      ( clth[38] &              clth[36] & ~clth[35]);

assign b4_cnt1h[1] =  ( clth[38] &  clth[37] & ~clth[36]            ) | 
                      ( clth[38] &  clth[37] &             ~clth[35]);

assign b4_cnt1l[0] =  ( clth[34] & ~clth[33]                        ) | 
                      ( clth[34] &              clth[32] & ~clth[31]);

assign b4_cnt1l[1] =  ( clth[34] &  clth[33] & ~clth[32]            ) | 
                      ( clth[34] &  clth[33] &             ~clth[31]);

assign b4_cnt1[0]  =  ( b4_nand_74 & b4_cnt1h[0]) |
                      (~b4_nand_74 & b4_cnt1l[0]);

assign b4_cnt1[1]  =  ( b4_nand_74 & b4_cnt1h[1]) |
                      (~b4_nand_74 & b4_cnt1l[1]);

assign b4_cnt1[2]  =  (~b4_nand_74 & b4_nand_30);


// ************************ BYTE 3 => 30:23 **************************

assign b3_nand_74  = ~(clth[30] & clth[29] & clth[28] & clth[27]);
assign b3_nand_30  = ~(clth[26] & clth[25] & clth[24] & clth[23]);

assign b3_ones     = ~(b3_nand_74 | b3_nand_30);
assign b3_ones_    = ~b3_ones;

assign b3_cnt1h[0] =  ( clth[30] & ~clth[29]                        ) | 
                      ( clth[30] &              clth[28] & ~clth[27]);

assign b3_cnt1h[1] =  ( clth[30] &  clth[29] & ~clth[28]            ) | 
                      ( clth[30] &  clth[29] &             ~clth[27]);

assign b3_cnt1l[0] =  ( clth[26] & ~clth[25]                        ) | 
                      ( clth[26] &              clth[24] & ~clth[23]);

assign b3_cnt1l[1] =  ( clth[26] &  clth[25] & ~clth[24]            ) | 
                      ( clth[26] &  clth[25] &             ~clth[23]);

assign b3_cnt1[0]  =  ( b3_nand_74 & b3_cnt1h[0]) |
                      (~b3_nand_74 & b3_cnt1l[0]);

assign b3_cnt1[1]  =  ( b3_nand_74 & b3_cnt1h[1]) |
                      (~b3_nand_74 & b3_cnt1l[1]);

assign b3_cnt1[2]  =  (~b3_nand_74 & b3_nand_30);


// ************************ BYTE 2 => 22:15 **************************

assign b2_nand_74  = ~(clth[22] & clth[21] & clth[20] & clth[19]);
assign b2_nand_30  = ~(clth[18] & clth[17] & clth[16] & clth[15]);

assign b2_ones     = ~(b2_nand_74 | b2_nand_30);
assign b2_ones_    = ~b2_ones;

assign b2_cnt1h[0] =  ( clth[22] & ~clth[21]                        ) | 
                      ( clth[22] &              clth[20] & ~clth[19]);

assign b2_cnt1h[1] =  ( clth[22] &  clth[21] & ~clth[20]            ) | 
                      ( clth[22] &  clth[21] &             ~clth[19]);

assign b2_cnt1l[0] =  ( clth[18] & ~clth[17]                        ) | 
                      ( clth[18] &              clth[16] & ~clth[15]);

assign b2_cnt1l[1] =  ( clth[18] &  clth[17] & ~clth[16]            ) | 
                      ( clth[18] &  clth[17] &             ~clth[15]);

assign b2_cnt1[0]  =  ( b2_nand_74 & b2_cnt1h[0]) |
                      (~b2_nand_74 & b2_cnt1l[0]);

assign b2_cnt1[1]  =  ( b2_nand_74 & b2_cnt1h[1]) |
                      (~b2_nand_74 & b2_cnt1l[1]);

assign b2_cnt1[2]  =  (~b2_nand_74 & b2_nand_30);


// ************************ BYTE 1 => 14:07 **************************

assign b1_nand_74  = ~(clth[14] & clth[13] & clth[12] & clth[11]);
assign b1_nand_30  = ~(clth[10] & clth[9] & clth[8] & clth[7]);

assign b1_ones     = ~(b1_nand_74 | b1_nand_30);
assign b1_ones_    = ~b1_ones;

assign b1_cnt1h[0] =  ( clth[14] & ~clth[13]                        ) | 
                      ( clth[14] &              clth[12] & ~clth[11]);

assign b1_cnt1h[1] =  ( clth[14] &  clth[13] & ~clth[12]            ) | 
                      ( clth[14] &  clth[13] &             ~clth[11]);

assign b1_cnt1l[0] =  ( clth[10] & ~clth[9]                        ) | 
                      ( clth[10] &              clth[8] & ~clth[7]);

assign b1_cnt1l[1] =  ( clth[10] &  clth[9] & ~clth[8]            ) | 
                      ( clth[10] &  clth[9] &             ~clth[7]);

assign b1_cnt1[0]  =  ( b1_nand_74 & b1_cnt1h[0]) |
                      (~b1_nand_74 & b1_cnt1l[0]);

assign b1_cnt1[1]  =  ( b1_nand_74 & b1_cnt1h[1]) |
                      (~b1_nand_74 & b1_cnt1l[1]);

assign b1_cnt1[2]  =  (~b1_nand_74 & b1_nand_30);


// ************************ BYTE 0 => 06:00 **************************

// Note : Byte 0 is unique since cnt1[2:0] must be 3'b111 for byte 'all ones' case!
//  64'b1111111111111111111111111111111111111111111111111111111110??????: cntl1[6:0]  =  7'b0111000;
//  64'b11111111111111111111111111111111111111111111111111111111110?????: cntl1[6:0]  =  7'b0111001;
//  64'b111111111111111111111111111111111111111111111111111111111110????: cntl1[6:0]  =  7'b0111010;
//  64'b1111111111111111111111111111111111111111111111111111111111110???: cntl1[6:0]  =  7'b0111011;
//  64'b11111111111111111111111111111111111111111111111111111111111110??: cntl1[6:0]  =  7'b0111100;
//  64'b111111111111111111111111111111111111111111111111111111111111110?: cntl1[6:0]  =  7'b0111101;
//  64'b1111111111111111111111111111111111111111111111111111111111111110: cntl1[6:0]  =  7'b0111110;
//  64'b1111111111111111111111111111111111111111111111111111111111111111: cntl1[6:0]  =  7'b0111111;


assign b0_nand_74  = ~(clth[6] & clth[5] & clth[4] & clth[3]);

assign b0_cnt1h[0] =  ( clth[6] & ~clth[5]                        ) | 
                      ( clth[6] &              clth[4] & ~clth[3]);

assign b0_cnt1h[1] =  ( clth[6] &  clth[5] & ~clth[4]            ) | 
                      ( clth[6] &  clth[5] &             ~clth[3]);

assign b0_cnt1l[0] =  ( clth[2] & ~clth[1]                        ) |
                      ( clth[2] &              clth[0]            );

assign b0_cnt1l[1] =  ( clth[2] &  clth[1]                        );

assign b0_cnt1[0]  =  ( b0_nand_74 & b0_cnt1h[0]) |
                      (~b0_nand_74 & b0_cnt1l[0]);

assign b0_cnt1[1]  =  ( b0_nand_74 & b0_cnt1h[1]) |
                      (~b0_nand_74 & b0_cnt1l[1]);

assign b0_cnt1[2]  =  (~b0_nand_74             );


// ************************  Global CNTL1   **************************

assign b3_1sel     =  b3_ones_                        ;
assign b2_1sel     = ~b3_ones_ &  b2_ones_            ;
assign b1_1sel     = ~b3_ones_ & ~b2_ones_ &  b1_ones_;
assign b0_1sel     = ~b3_ones_ & ~b2_ones_ & ~b1_ones_;

assign cntl1l[4:0] = ({5{b3_1sel}} & {2'b00,b3_cnt1[2:0]}) |
                     ({5{b2_1sel}} & {2'b01,b2_cnt1[2:0]}) |
                     ({5{b1_1sel}} & {2'b10,b1_cnt1[2:0]}) |
                     ({5{b0_1sel}} & {2'b11,b0_cnt1[2:0]});


assign b7_1sel     =  b7_ones_                        ;
assign b6_1sel     = ~b7_ones_ &  b6_ones_            ;
assign b5_1sel     = ~b7_ones_ & ~b6_ones_ &  b5_ones_;
assign b4_1sel     = ~b7_ones_ & ~b6_ones_ & ~b5_ones_;

assign cntl1h[4:0] = ({5{b7_1sel}} & {2'b00,b7_cnt1[2:0]}) |
                     ({5{b6_1sel}} & {2'b01,b6_cnt1[2:0]}) |
                     ({5{b5_1sel}} & {2'b10,b5_cnt1[2:0]}) |
                     ({5{b4_1sel}} & {2'b11,b4_cnt1[2:0]});


assign cntl1_selh  = b7_ones_ | b6_ones_ | b5_ones_ | b4_ones_;

assign cntl1[5:0]  = ({6{ cntl1_selh}} & {1'b0, cntl1h[4:0]}) |
                     ({6{~cntl1_selh}} & {1'b1, cntl1l[4:0]});


// * * * * * * * * * * * * End   : Integer CNTL1 * * * * * * * * * * * * * 


assign xsht_amt_sel10   = ~(fdd_pe_clth[63] & control_lth[0]) & fdc_pe_cycle[1];
assign xsht_amt_sel11   =  (fdd_pe_clth[63] & control_lth[0]) & fdc_pe_cycle[1];
assign xsht_amt_sel20   = ~(fdd_pe_clth[63] & control_lth[0]) & fdc_pe_cycle[2];
assign xsht_amt_sel21   =  (fdd_pe_clth[63] & control_lth[0]) & fdc_pe_cycle[2];

assign xsht_amt_in[7:0] = ({8{engine_on     }} &  8'b11111101       ) |
                          ({8{xsht_amt_sel10}} & {1'b0 , cntl0[6:0]}) |
                          ({8{xsht_amt_sel11}} & {2'b00, cntl1[5:0]}) |
                          ({8{xsht_amt_sel20}} & {1'b1 ,~cntl0[6:0]}) |
                          ({8{xsht_amt_sel21}} & {2'b11,~cntl1[5:0]});


assign pe_ndq[7:0]	= pe_hamt_lth[7:0] + pe_xsht_amt[7:0] + 8'b0000_0001;

assign pe_hamt_in[7:0]	= ({8{    pe_hmux_sel[0]}} & 8'b00110100) |	// FLT DP
			  ({8{    pe_hmux_sel[1]}} & 8'b00010111) |	// FLT SP
			  ({8{fdc_pe_smux_sel[0]}} & 8'b00000001) |	// INT neg B correction
			  ({8{    pe_hmux_sel[2]}} & pe_ndq[7:0]);	// SRT loop counter


fgu_fdc_ctl_msff_ctl_macro__width_8	xsht_lth	 (
 .scan_in(xsht_lth_scanin),
 .scan_out(xsht_lth_scanout),
 .l1clk( l1clk_pm1        ),
 .din  ( xsht_amt_in[7:0] ),
 .dout ( pe_xsht_amt[7:0] ),
  .siclk(siclk),
  .soclk(soclk));


fgu_fdc_ctl_msff_ctl_macro__width_8	hamt_lth	 (
 .scan_in(hamt_lth_scanin),
 .scan_out(hamt_lth_scanout),
 .l1clk( l1clk_pm1		),
 .din  ( pe_hamt_in[7:0]	),
 .dout ( pe_hamt_lth[7:0]	),
  .siclk(siclk),
  .soclk(soclk));


assign xsht_ctl_in[5:0] = ({6{xsht_amt_sel10}} & cntl0[5:0]) |
                          ({6{xsht_amt_sel11}} & cntl1[5:0]) |
                          ({6{xsht_amt_sel20}} & cntl0[5:0]) |
                          ({6{xsht_amt_sel21}} & cntl1[5:0]);

fgu_fdc_ctl_msff_ctl_macro__width_6	xcntl_lth	 (
 .scan_in(xcntl_lth_scanin),
 .scan_out(xcntl_lth_scanout),
 .l1clk( l1clk_pm1            ),
 .din  ( xsht_ctl_in[5:0]     ),
 .dout ( fdc_pe_xsht_ctl[5:0] ),
  .siclk(siclk),
  .soclk(soclk));


// *** Floating Point Rounding ***


assign engine_valid_fx1	=   fac_div_valid_fx1    &  ~fac_divq_valid_fx1;
assign engine_valid_fx2	=  (queue_valid_lth_fx2  &  (fac_div_valid_fx1 & fac_divq_valid_fx1)) | engine_valid_lth_fx2;
assign engine_valid_fx3	=  (queue_valid_lth_fx3  &  (fac_div_valid_fx1 & fac_divq_valid_fx1)) | engine_valid_lth_fx3;

assign queue_valid_fx1	=  ~fac_div_valid_fx1    &   fac_divq_valid_fx1;
assign queue_valid_fx2	=   queue_valid_lth_fx2  & ~(fac_div_valid_fx1 & fac_divq_valid_fx1);
//sign queue_valid_fx3	=   queue_valid_lth_fx3  & ~(fac_div_valid_fx1 & fac_divq_valid_fx1);

assign q2e_fx3p		=  (fac_div_valid_fx1 & fac_divq_valid_fx1) & ~queue_valid_lth_fx2 & ~queue_valid_lth_fx3;


fgu_fdc_ctl_msff_ctl_macro__width_4	xrnd_vld_lth	 (
 .scan_in(xrnd_vld_lth_scanin),
 .scan_out(xrnd_vld_lth_scanout),
 .l1clk( l1clk_pm1                                                                         ),
 .din  ({engine_valid_fx1    ,engine_valid_fx2    ,queue_valid_fx1    ,queue_valid_fx2}    ),
 .dout ({engine_valid_lth_fx2,engine_valid_lth_fx3,queue_valid_lth_fx2,queue_valid_lth_fx3}),
  .siclk(siclk),
  .soclk(soclk));


// SPARC v9 : pg 44
//
//   RD  |  Round toward
//  ---  |  ------------
//   00  |  Nearest (even if tie)
//   01  |     0
//   10  |  +INF
//   11  |  -INF


assign eround_mode_in[1:0]= ({2{ engine_valid_fx3            }} & fpc_rd_mode_fx3[1:0]) |
                            ({2{                     q2e_fx3p}} & qround_mode_lth[1:0]) |
                            ({2{~engine_valid_fx3 & ~q2e_fx3p}} & eround_mode_lth[1:0]);

assign e_emin_in          = (    engine_valid_fx3               & fpc_emin_fx3        ) |
                            (                        q2e_fx3p   & q_emin_lth          ) |
                            (   ~engine_valid_fx3 & ~q2e_fx3p   & fdc_emin_lth        );


assign qround_mode_in[1:0]= ({2{ queue_valid_lth_fx3}} & fpc_rd_mode_fx3[1:0]) |
                            ({2{~queue_valid_lth_fx3}} & qround_mode_lth[1:0]);

assign q_emin_in          = (    queue_valid_lth_fx3   & fpc_emin_fx3        ) |
                            (   ~queue_valid_lth_fx3   & q_emin_lth          );


assign float_sign_in      = (    fac_div_valid_fx1 & ~fac_divq_valid_fx1   & incoming_sign_fx1       ) |
                            (    fac_div_valid_fx1 &  fac_divq_valid_fx1   & qcontrol_fx1[6]         ) |
                            (   ~fac_div_valid_fx1                         & float_sign_lth          );

assign fdc_dec_exp_early  =  fdc_pte_cycle[0] & ~control_lth[2] & ~fdd_result[63] & ~flt_sqrte_kill_dec;

assign inexact_in         =  fdc_pte_cycle[0] & ~control_lth[2] & (final_sticky | final_guard);


fgu_fdc_ctl_msff_ctl_macro__width_10	xrnd_lth	 (
 .scan_in(xrnd_lth_scanin),
 .scan_out(xrnd_lth_scanout),
 .l1clk( l1clk_pm1                                                                                                                                  ),
 .din  ({float_sign_in  , eround_mode_in[1:0]  , qround_mode_in[1:0]  , fdd_cla_zero64_ , sticky_pte1 , inexact_in      , e_emin_in    , q_emin_in }),
 .dout ({float_sign_lth , eround_mode_lth[1:0] , qround_mode_lth[1:0] , sticky_pte1     , sticky_pte0 , fdc_flt_inexact , fdc_emin_lth , q_emin_lth}),
  .siclk(siclk),
  .soclk(soclk));


assign fdc_flt_round[1]   = ~control_lth[2] & ~control_lth[1];	// SP
assign fdc_flt_round[0]   = ~control_lth[2] &  control_lth[1];	// DP


assign flt_shift_sel_     =   fdd_result[63] |  fdc_emin_lth;


assign final_sticky       = ( control_lth[1] &  flt_shift_sel_ & (fdd_result[9] | sticky_pte0)) |	// DP "1."
                            ( control_lth[1] & ~flt_shift_sel_ & (                 sticky_pte0)) |	// DP "0."
                            (~control_lth[1] &  flt_shift_sel_ & (fdd_result[38] | sticky_pte0)) |	// SP "1."
                            (~control_lth[1] & ~flt_shift_sel_ & (                 sticky_pte0));	// SP "0."

assign final_guard        = ( control_lth[1] &  flt_shift_sel_ &  fdd_result[10]               ) |	// DP "1."
                            ( control_lth[1] & ~flt_shift_sel_ &  fdd_result[9]               ) |	// DP "0."
                            (~control_lth[1] &  flt_shift_sel_ &  fdd_result[39]               ) |	// SP "1."
                            (~control_lth[1] & ~flt_shift_sel_ &  fdd_result[38]               );	// SP "0."

assign final_lsb          = ( control_lth[1] &  flt_shift_sel_ &  fdd_result[11]               ) |	// DP "1."
                            ( control_lth[1] & ~flt_shift_sel_ &  fdd_result[10]               ) |	// DP "0."
                            (~control_lth[1] &  flt_shift_sel_ &  fdd_result[40]               ) |	// SP "1."
                            (~control_lth[1] & ~flt_shift_sel_ &  fdd_result[39]               );	// SP "0."


assign flt_rnd00_en       =  ~control_lth[2] & (eround_mode_lth[1:0] == 2'b00);
assign flt_rnd1x_en       = (~control_lth[2] & (eround_mode_lth[1:0] == 2'b10) & ~float_sign_lth) |
                            (~control_lth[2] & (eround_mode_lth[1:0] == 2'b11) &  float_sign_lth);

assign fdc_flt_increment  = ( flt_rnd00_en  & final_guard & final_sticky            ) |
                            ( flt_rnd00_en  & final_guard &                final_lsb) |
                            ( flt_rnd1x_en  & final_guard                           ) |
                            ( flt_rnd1x_en  &               final_sticky            );


// *** Floating Point Square Root Special Case ***

// For an odd exponent Square Root, the mantissa is shifted one bit position right.
// In most cases, the final result will end up in the form of "0.1".  We then normalize
// this result and decrement the result exponent.  However, if the mantissa is all ONES,
// this does not hold.  If you take the square root of 0.1111111...1 (after the 1-bit shift),
// the result will move closer to 1.00000000.  In the Round to +INF only,
// the rounded result will be 1.000000 and no decrementing of the exponent will occur.

//                                  1=DP , 0=SP              SQRTE
assign fsqrt_fract_all_ones	= (~fac_div_control_fx1[1] & fac_div_control_fx1[3] & fpf_hi_bof_fx1                 ) |
				  ( fac_div_control_fx1[1] & fac_div_control_fx1[3] & fpf_hi_bof_fx1 & fpf_lo_bof_fx1);

assign fsqrt_special_in		= ( fac_div_valid_fx1 & ~fac_divq_valid_fx1 & fsqrt_fract_all_ones) |
				  ( fac_div_valid_fx1 &  fac_divq_valid_fx1 & qcontrol_fx1[7]     ) |
				  (~fac_div_valid_fx1 &                       fsqrt_special_lth   );

fgu_fdc_ctl_msff_ctl_macro__width_1	spec_sqrt_lth	 (
 .scan_in(spec_sqrt_lth_scanin),
 .scan_out(spec_sqrt_lth_scanout),
 .l1clk( l1clk_pm1		),
 .din  ( fsqrt_special_in	),
 .dout ( fsqrt_special_lth	),
  .siclk(siclk),
  .soclk(soclk));

assign flt_sqrte_kill_dec	=   fsqrt_special_lth & (eround_mode_lth[1:0] == 2'b10);  // +inf


// *** FDX Custom ***


assign cla_64		= fdd_fdx_din0 ^ fdd_fdx_din1 ^ fdd_fdx_cin64;

assign cin_in_raw	= (~fdc_asign_lth & ~fdc_bsign_lth & ~cla_64                   ) |
			  (~fdc_asign_lth &  fdc_bsign_lth &  cla_64                   ) |
			  ( fdc_asign_lth & ~fdc_bsign_lth & ~cla_64 &  fdd_cla_zero64_) |
			  ( fdc_asign_lth &  fdc_bsign_lth &           ~fdd_cla_zero64_) |
			  ( fdc_asign_lth &  fdc_bsign_lth &  cla_64                   );

assign fdc_fdx_cin_in	= fdc_pte_cycle2 & cin_in_raw;


// *** FDQ00 Custom ***

assign fdq00_sum[3:0]   = fdd_fdq00_10_sum[4:1];    // s0[65:62]
assign fdq00_carry[3:0] = fdd_fdq00_10_carry[4:1];  // c0[65:62]

assign pr00[0]		= fdq00_sum[0]   | fdq00_carry[0];
assign pr00[3:1]	= fdq00_sum[3:1] + fdq00_carry[3:1];

assign fdc_qsel00[0]	= ( pr00[3] & ~pr00[2]) |			// 10.0x ; 10.1x
			  ( pr00[3] & ~pr00[1]) |			// 10.0x ; 11.0x
			  ( pr00[3] & ~pr00[0]);			// 11.10

assign fdc_qsel00[1]	= ( pr00[3] &  pr00[2] &  pr00[1] &  pr00[0]) |	// 11.11
			  (~pr00[3] & ~pr00[2] & ~pr00[1] & ~pr00[0]);	// 00.00


assign fdc_qsel00[2]	= (~pr00[3] &  pr00[2]) |			// 01.1x ; 01.0x
			  (~pr00[3] &  pr00[1]) |			// 01.1x ; 00.1x
			  (~pr00[3] &  pr00[0]);			// 00.01


// *** FDQ1p Custom ***

assign pr1p[0]		= fdd_fdq1p_sum[0]   | fdd_fdq1p_carry[0];
assign pr1p[3:1]	= fdd_fdq1p_sum[3:1] + fdd_fdq1p_carry[3:1];

assign qsel1p[0]	= ( pr1p[3] & ~pr1p[2]) |			// 10.0x ; 10.1x
			  ( pr1p[3] & ~pr1p[1]) |			// 10.0x ; 11.0x
			  ( pr1p[3] & ~pr1p[0]);			// 11.10

assign qsel1p[1]	= ( pr1p[3] &  pr1p[2] &  pr1p[1] &  pr1p[0]) |	// 11.11
			  (~pr1p[3] & ~pr1p[2] & ~pr1p[1] & ~pr1p[0]);	// 00.00


assign qsel1p[2]	= (~pr1p[3] &  pr1p[2]) |			// 01.1x ; 01.0x
			  (~pr1p[3] &  pr1p[1]) |			// 01.1x ; 00.1x
			  (~pr1p[3] &  pr1p[0]);			// 00.01


// *** FDQ10 Custom ***

assign fdq10_sum[3:0]   = fdd_fdq00_10_sum[3:0];    // s0[64:61]
assign fdq10_carry[3:0] = fdd_fdq00_10_carry[3:0];  // c0[64:61]

assign pr10[0]		= fdq10_sum[0]   | fdq10_carry[0];
assign pr10[3:1]	= fdq10_sum[3:1] + fdq10_carry[3:1];

assign qsel10[0]	= ( pr10[3] & ~pr10[2]) |			// 10.0x ; 10.1x
			  ( pr10[3] & ~pr10[1]) |			// 10.0x ; 11.0x
			  ( pr10[3] & ~pr10[0]);			// 11.10

assign qsel10[1]	= ( pr10[3] &  pr10[2] &  pr10[1] &  pr10[0]) |	// 11.11
			  (~pr10[3] & ~pr10[2] & ~pr10[1] & ~pr10[0]);	// 00.00


assign qsel10[2]	= (~pr10[3] &  pr10[2]) |			// 01.1x ; 01.0x
			  (~pr10[3] &  pr10[1]) |			// 01.1x ; 00.1x
			  (~pr10[3] &  pr10[0]);			// 00.01


// *** FDQ1n Custom ***

assign pr1n[0]		= fdd_fdq1n_sum[0]   | fdd_fdq1n_carry[0];
assign pr1n[3:1]	= fdd_fdq1n_sum[3:1] + fdd_fdq1n_carry[3:1];

assign qsel1n[0]	= ( pr1n[3] & ~pr1n[2]) |			// 10.0x ; 10.1x
			  ( pr1n[3] & ~pr1n[1]) |			// 10.0x ; 11.0x
			  ( pr1n[3] & ~pr1n[0]);			// 11.10

assign qsel1n[1]	= ( pr1n[3] &  pr1n[2] &  pr1n[1] &  pr1n[0]) |	// 11.11
			  (~pr1n[3] & ~pr1n[2] & ~pr1n[1] & ~pr1n[0]);	// 00.00


assign qsel1n[2]	= (~pr1n[3] &  pr1n[2]) |			// 01.1x ; 01.0x
			  (~pr1n[3] &  pr1n[1]) |			// 01.1x ; 00.1x
			  (~pr1n[3] &  pr1n[0]);			// 00.01


assign engine_start	= fac_div_valid_fx1 | fdc_pe_cycle3;

assign fdc_qsel1[2:0]	= ({3{~engine_start & fdc_qsel00[0]}} & qsel1p[2:0]) |
			  ({3{~engine_start & fdc_qsel00[1]}} & qsel10[2:0]) |
			  ({3{~engine_start & fdc_qsel00[2]}} & qsel1n[2:0]);


// *** Misc Logic from FDD ***

assign fdc_q_in[1]	= (   ~engine_start & fdc_qsel00[0]   & fdc_bsign_lth ) |
			  (   ~engine_start & fdc_qsel00[2]   & fdc_bsign_lth_);

assign fdc_qm1_in[1]	= (   ~engine_start & fdc_qsel00[0]   & fdc_bsign_lth_) |
			  (   ~engine_start & fdc_qsel00[2]   & fdc_bsign_lth );

assign fdc_q_in[0]	= (                   fdc_qsel1[0]    & fdc_bsign_lth ) |
			  (                   fdc_qsel1[2]    & fdc_bsign_lth_);

assign fdc_qm1_in[0]	= (                   fdc_qsel1[0]    & fdc_bsign_lth_) |
			  (                   fdc_qsel1[2]    & fdc_bsign_lth );


supply0 vss;
supply1 vdd;


// fixscan start:
assign spares_scanin             = scan_in                  ;
assign qdata_lth_scanin          = spares_scanout           ;
assign cntl_lth_scanin           = qdata_lth_scanout        ;
assign ovlf_lth_scanin           = cntl_lth_scanout         ;
assign stall_lth_scanin          = ovlf_lth_scanout         ;
assign data_lth_scanin           = stall_lth_scanout        ;
assign xsht_lth_scanin           = data_lth_scanout         ;
assign hamt_lth_scanin           = xsht_lth_scanout         ;
assign xcntl_lth_scanin          = hamt_lth_scanout         ;
assign xrnd_vld_lth_scanin       = xcntl_lth_scanout        ;
assign xrnd_lth_scanin           = xrnd_vld_lth_scanout     ;
assign spec_sqrt_lth_scanin      = xrnd_lth_scanout         ;
assign scan_out                  = spec_sqrt_lth_scanout    ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module fgu_fdc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module fgu_fdc_ctl_spare_ctl_macro__num_3 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));
assign scan_out = so_2;


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdc_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdc_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdc_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdc_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fdd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fdd_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_out, 
  div_clken_rep0, 
  fad_rs1_fmt_fx1_rep01, 
  fad_rs2_fmt_fx1_rep01, 
  fac_div_valid_fx1_rep0, 
  fac_divq_valid_fx1_rep0, 
  fdc_asign_lth, 
  fdc_bsign_lth, 
  fdc_bsign_lth_, 
  fdc_pe_cycle3, 
  fdc_pe_cmux_sel, 
  fdc_pe_smux_sel, 
  fdc_pe_xsht_ctl, 
  fdc_ie_fsqrt_valid_even, 
  fdc_ie_fsqrt_valid_even_, 
  fdc_ie_fsqrt_valid_odd, 
  fdc_ie_fsqrt_valid_odd_, 
  fdc_ie_rmux_sel, 
  fdc_ie_dmux_sel, 
  fdc_flt_increment, 
  fdc_pte_clasel, 
  fdc_pte_csa_cin, 
  fdc_pte_cycle2, 
  fdc_emin_lth, 
  fdc_pte_qsel, 
  fdc_pte_stall_, 
  fdc_flt_round, 
  fdc_idiv_ctl, 
  fdc_fdx_cin_in, 
  fdc_qsel00, 
  fdc_qsel1, 
  fdc_q_in, 
  fdc_qm1_in, 
  fdd_result, 
  fdd_pte_cla_early_b63, 
  fdd_pe_clth, 
  fdd_cla_zero32_, 
  fdd_cla_zero64_, 
  fdd_fdx_din0, 
  fdd_fdx_din1, 
  fdd_fdx_cin64, 
  fdd_fdq00_10_sum, 
  fdd_fdq00_10_carry, 
  fdd_fdq1p_sum, 
  fdd_fdq1p_carry, 
  fdd_fdq1n_sum, 
  fdd_fdq1n_carry);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire q_rs1_ff_scanin;
wire q_rs1_ff_scanout;
wire [63:0] q_rs1_fx1;
wire q_rs2_ff_scanin;
wire q_rs2_ff_scanout;
wire [63:0] q_rs2_fx1;
wire ipe_clth_scanin;
wire ipe_clth_scanout;
wire [63:0] pe_xsht1;
wire ipe_slth_scanin;
wire ipe_slth_scanout;
wire [63:0] pe_slth;
wire [63:0] pe_xsht0;
wire bsign_buff0;
wire bsign_buff1;
wire [65:0] pe_divisor;
wire [65:0] pe_aop_sh;
wire [65:0] sum_new;
wire [65:0] divisor_new;
wire engine_start;
wire engine_start_;
wire ie_s00lth_scanin;
wire ie_s00lth_scanout;
wire [64:0] s21;
wire [65:1] s1;
wire [64:0] s20;
wire [65:0] s0;
wire ie_c00lth_scanin;
wire ie_c00lth_scanout;
wire [64:1] c21;
wire [65:2] c1;
wire [64:1] c20;
wire [65:2] c0;
wire [65:0] d2_00_in;
wire [65:0] d1;
wire [65:0] sqe_cnt1;
wire [65:0] d2_p1_in;
wire [65:0] flip1;
wire [65:0] d2_m1xor;
wire [65:0] d2_m1_in;
wire ie_d00lth_scanin;
wire ie_d00lth_scanout;
wire [65:0] d0;
wire [64:0] sqe_cnt13;
wire [64:0] effd2_p1_p1in;
wire [64:0] sqe_cnt3;
wire [64:0] effd2_00_p1in;
wire [64:0] effd2_m1_p1in;
wire [64:0] effd2_xx_p1in;
wire ie_d00lthp1_scanin;
wire ie_d00lthp1_scanout;
wire [64:0] effd0_p1_;
wire [64:0] sqe_cnt23;
wire [64:0] effd2_p1_m1in;
wire [64:0] sqe_cnt123;
wire [64:0] effd2_00_m1in;
wire [64:0] effd2_m1_m1in;
wire ie_d00lthm1_scanin;
wire ie_d00lthm1_scanout;
wire [64:0] effd0_m1;
wire ie_csa11_unused;
wire [64:1] c11;
wire [64:0] s11;
wire ie_csa10_unused;
wire [64:1] c10;
wire [64:0] s10;
wire [65:0] d1_00_in;
wire [65:0] sqe_cnt0;
wire [65:0] d1_p1_in;
wire [65:0] flip0;
wire [65:0] d1_m1xor;
wire [65:0] d1_m1_in;
wire [65:0] sqe_cnt02;
wire [64:0] effd1_p1_p1in;
wire [64:0] sqe_cnt2;
wire [64:0] effd1_00_p1in;
wire [64:0] effd1_m1_p1in;
wire [64:0] effd1_p1_;
wire [64:0] sqe_cnt12;
wire [64:0] effd1_p1_m1in;
wire [65:0] sqe_cnt012;
wire [64:0] effd1_00_m1in;
wire [64:0] effd1_m1_m1in;
wire [64:0] effd1_m1;
wire ie_csa21_unused;
wire ie_csa20_unused;
wire [65:0] q_lth;
wire [65:2] q_in;
wire ie_qlth_scanin;
wire ie_qlth_scanout;
wire [65:0] qm1_lth;
wire [65:2] qm1_in;
wire ie_qm1lth_scanin;
wire ie_qm1lth_scanout;
wire [65:1] qm1_lth_;
wire [65:2] pte_q;
wire [65:2] pte_qm1_;
wire ipte_csa_unused;
wire [63:1] pte_carry;
wire [63:0] pte_sum;
wire ipte_clalth0_scanin;
wire ipte_clalth0_scanout;
wire [63:0] pte_cla;
wire [64:0] pte_clalth0;
wire ipte_clalth1_scanin;
wire ipte_clalth1_scanout;
wire [64:0] pte_clalth1;
wire pte_cla_cout;
wire ipte_result_scanin;
wire ipte_result_scanout;
wire isqe_cnt_scanin;
wire isqe_cnt_scanout;
wire [65:0] sqe_cnt2_;
wire [65:0] sqe_cnt0_;
wire isqe_flip_scanin;
wire isqe_flip_scanout;
wire [65:0] sqe_cnt1_;
wire [65:1] sqe_cnt01;


// *** globals ***
input		l2clk;
input  		scan_in;
input  		tcu_pce_ov;		// scan signals
input  		spc_aclk;
input  		spc_bclk;
input 		tcu_scan_en;
output 		scan_out;

input           div_clken_rep0;         // div clken

input  [63:0]	fad_rs1_fmt_fx1_rep01;
input  [63:0]	fad_rs2_fmt_fx1_rep01;

input		fac_div_valid_fx1_rep0;	//  div_valid  divq_valid  |  action
input		fac_divq_valid_fx1_rep0;//  ---------  ----------  |  ---------------------------------------
					//     1           0       |  start divide from FX1   RS1/RS2/control
					//     0           1       |  load  queue  from FX1   RS1/RS2/control
					//     1           1       |  start divide from queue RS1/RS2/control

// *** locals  ***
input		fdc_asign_lth;
input		fdc_bsign_lth;
input		fdc_bsign_lth_;
input		fdc_pe_cycle3;
input		fdc_pe_cmux_sel;
input  [2:0]	fdc_pe_smux_sel;
input  [5:0]	fdc_pe_xsht_ctl;
input		fdc_ie_fsqrt_valid_even;
input		fdc_ie_fsqrt_valid_even_;
input		fdc_ie_fsqrt_valid_odd;
input		fdc_ie_fsqrt_valid_odd_;
input  [4:0]	fdc_ie_rmux_sel;
input  [2:0]	fdc_ie_dmux_sel;
input		fdc_flt_increment;
input  [1:0]	fdc_pte_clasel;
input		fdc_pte_csa_cin;
input		fdc_pte_cycle2;
input		fdc_emin_lth;
input  [2:0]	fdc_pte_qsel;
input		fdc_pte_stall_;

input  [1:0]	fdc_flt_round;
input  [4:0]	fdc_idiv_ctl;           //  3210   [4] = integer
                                        //  ----
                                        //  0001 : 8000 0000 0000 0000
                                        //  0010 : FFFF FFFF 8000 0000
                                        //  0100 : 0000 0000 7FFF FFFF
                                        //  1000 : 0000 0000 FFFF FFFF


input		fdc_fdx_cin_in;
input  [2:0]	fdc_qsel00;
input  [2:0]	fdc_qsel1;

input  [1:0]	fdc_q_in;
input  [1:0]	fdc_qm1_in;


// *** globals ***
output [63:0]	fdd_result;
output		fdd_pte_cla_early_b63;


// *** locals  ***
output [63:0]	fdd_pe_clth;
output		fdd_cla_zero32_;
output		fdd_cla_zero64_;

output		fdd_fdx_din0;
output		fdd_fdx_din1;
output		fdd_fdx_cin64;

output [4:0]	fdd_fdq00_10_sum;
output [4:0]	fdd_fdq00_10_carry;
output [3:0]	fdd_fdq1p_sum;
output [3:0]	fdd_fdq1p_carry;
output [3:0]	fdd_fdq1n_sum;
output [3:0]	fdd_fdq1n_carry;


// scan renames
assign stop   = 1'b0;
// end scan

fgu_fdd_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_4 test_rep0  (
 .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}),
 .dout({se,          pce_ov,     siclk,    soclk   }));


// * * * * * * * * * * * 2nd Thread Group Queue * * * * * * * * * * 


fgu_fdd_dp_msff_macro__stack_66c__width_64	q_rs1_ff	 (
 .scan_in(q_rs1_ff_scanin),
 .scan_out(q_rs1_ff_scanout),
 .clk ( l2clk                      ),
 .en  ( fac_divq_valid_fx1_rep0    ),
 .din ( fad_rs1_fmt_fx1_rep01[63:0]),
 .dout( q_rs1_fx1[63:0]            ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fdd_dp_msff_macro__stack_66c__width_64	q_rs2_ff	 (
 .scan_in(q_rs2_ff_scanin),
 .scan_out(q_rs2_ff_scanout),
 .clk ( l2clk                      ),
 .en  ( fac_divq_valid_fx1_rep0    ),
 .din ( fad_rs2_fmt_fx1_rep01[63:0]),
 .dout( q_rs2_fx1[63:0]            ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// * * * * * * * * * * * Integer "pre-engine" * * * * * * * * * * * 


fgu_fdd_dp_msff_macro__mux_aope__ports_3__stack_66c__width_64	ipe_clth	 (
 .scan_in(ipe_clth_scanin),
 .scan_out(ipe_clth_scanout),
 .clk ( l2clk                      ),
 .en  ( div_clken_rep0             ),  // powerdown pin
 .din0( pe_xsht1[63:0]             ),
 .din1( fad_rs2_fmt_fx1_rep01[63:0]),
 .din2( q_rs2_fx1[63:0]            ),
 .sel0( fdc_pe_cmux_sel            ),
 .sel1( fdc_pe_smux_sel[2]         ),
 .dout( fdd_pe_clth[63:0]          ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fdd_dp_msff_macro__mux_aope__ports_4__stack_66c__width_64	ipe_slth	 (
 .scan_in(ipe_slth_scanin),
 .scan_out(ipe_slth_scanout),
 .clk ( l2clk                      ),
 .en  ( div_clken_rep0             ),  // powerdown pin
 .din0({fdd_pe_clth[62:0],1'b0    }),
 .din1( fdd_pe_clth[63:0]          ),
 .din2( fad_rs1_fmt_fx1_rep01[63:0]),
 .din3( q_rs1_fx1[63:0]            ),
 .sel0( fdc_pe_smux_sel[0]         ),
 .sel1( fdc_pe_smux_sel[1]         ),
 .sel2( fdc_pe_smux_sel[2]         ),
 .dout( pe_slth[63:0]              ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fdd_dp_mux_macro__mux_aodec__ports_8__stack_66c__width_64	ipe_xsht0	 (
 .din0( pe_slth[63:0]            ),
 .din1({pe_slth[55:0],{ 8{1'b0}}}),
 .din2({pe_slth[47:0],{16{1'b0}}}),
 .din3({pe_slth[39:0],{24{1'b0}}}),
 .din4({pe_slth[31:0],{32{1'b0}}}),
 .din5({pe_slth[23:0],{40{1'b0}}}),
 .din6({pe_slth[15:0],{48{1'b0}}}),
 .din7({pe_slth[7:0],{56{1'b0}}}),
 .sel ( fdc_pe_xsht_ctl[5:3]      ),
 .dout( pe_xsht0[63:0]            ));


fgu_fdd_dp_mux_macro__mux_aodec__ports_8__stack_66c__width_64	ipe_xsht1	 (
 .din0( pe_xsht0[63:0]           ),
 .din1({pe_xsht0[62:0],{1{1'b0}}}),
 .din2({pe_xsht0[61:0],{2{1'b0}}}),
 .din3({pe_xsht0[60:0],{3{1'b0}}}),
 .din4({pe_xsht0[59:0],{4{1'b0}}}),
 .din5({pe_xsht0[58:0],{5{1'b0}}}),
 .din6({pe_xsht0[57:0],{6{1'b0}}}),
 .din7({pe_xsht0[56:0],{7{1'b0}}}),
 .sel ( fdc_pe_xsht_ctl[2:0]      ),
 .dout( pe_xsht1[63:0]            ));


// Floorplan Info - install "ipe_bsign_buf" in clock bay of "ipe_divxor"

fgu_fdd_dp_buff_macro__stack_66c__width_2	ipe_bsign_buf	 (
 .din ({2{fdc_bsign_lth}          }),
 .dout({bsign_buff0,bsign_buff1   }));

fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_64	ipe_divxor	 (
 .din0( fdd_pe_clth[63:0]                   ),
 .din1({{32{bsign_buff0}},{32{bsign_buff1}}}),
 .dout( pe_divisor[63:0]                    ));

assign pe_aop_sh[65:0]   = {{2{fdc_asign_lth}},pe_xsht1[63:0]};
assign pe_divisor[65:64] = 2'b00;


// * * * * * * * * * * * Interface to engine * * * * * * * * * * * 


fgu_fdd_dp_mux_macro__mux_aonpe__ports_5__stack_66c__width_66	ie_rmux		 (
 .din0( pe_aop_sh[65:0]                                   ),  // integer
 .din1({{4'b0001},fad_rs2_fmt_fx1_rep01[62:11],{10{1'b0}}}),  // float sqrt
 .din2({{3'b001 },fad_rs1_fmt_fx1_rep01[62:11],{11{1'b0}}}),  // float div
 .din3({{4'b0001},q_rs2_fx1[62:11]            ,{10{1'b0}}}),  // float sqrt
 .din4({{3'b001 },q_rs1_fx1[62:11]            ,{11{1'b0}}}),  // float div
 .sel0( fdc_ie_rmux_sel[0]                                ),
 .sel1( fdc_ie_rmux_sel[1]                                ),
 .sel2( fdc_ie_rmux_sel[2]                                ),
 .sel3( fdc_ie_rmux_sel[3]                                ),
 .sel4( fdc_ie_rmux_sel[4]                                ),
 .dout( sum_new[65:0]                                     ));

fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_66	ie_dmux		 (
 .din0( pe_divisor[65:0]                                  ),  // integer
 .din1({{3'b001 },fad_rs2_fmt_fx1_rep01[62:11],{11{1'b0}}}),  // float div
 .din2({{3'b001 },q_rs2_fx1[62:11]            ,{11{1'b0}}}),  // float div
 .sel0( fdc_ie_dmux_sel[0]                                ),
 .sel1( fdc_ie_dmux_sel[1]                                ),
 .sel2( fdc_ie_dmux_sel[2]                                ),
 .dout( divisor_new[65:0]                                 ));


// * * * * * * * * * * * * * * "engine" * * * * * * * * * * * * * * 

fgu_fdd_dp_or_macro__ports_2__width_1	ie_engstart_or	 (
 .din0( fac_div_valid_fx1_rep0   ),
 .din1( fdc_pe_cycle3            ),
 .dout( engine_start             ));

fgu_fdd_dp_nor_macro__ports_2__width_1	ie_engstart_nor	 (
 .din0( fac_div_valid_fx1_rep0   ),
 .din1( fdc_pe_cycle3            ),
 .dout( engine_start_            ));


fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_66	ie_s00lth	 (
 .scan_in(ie_s00lth_scanin),
 .scan_out(ie_s00lth_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0({s21[64:0],1'b0          }),
 .din1({s1[64:1] ,2'b00         }),
 .din2({s20[64:0],1'b0          }),
 .din3( sum_new[65:0]            ),  // PR(i+1) = PR(i) - qD;
 .sel0( fdc_qsel1[0]             ),  // PR + D -> therefore q = -1
 .sel1( fdc_qsel1[1]             ),
 .sel2( fdc_qsel1[2]             ),  // PR - D -> therefore q = +1
 .sel3( engine_start             ),
 .dout( s0[65:0]                 ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_64	ie_c00lth	 (
 .scan_in(ie_c00lth_scanin),
 .scan_out(ie_c00lth_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0( c21[64:1]                ),
 .din1({c1[64:2] ,1'b0          }),
 .din2( c20[64:1]                ),
 .din3({64{1'b0}                }),  // PR(i+1) = PR(i) - qD;
 .sel0( fdc_qsel1[0]             ),  // PR + D -> therefore q = -1
 .sel1( fdc_qsel1[1]             ),
 .sel2( fdc_qsel1[2]             ),  // PR - D -> therefore q = +1
 .sel3( engine_start             ),
 .dout( c0[65:2]                 ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


//assign d2_p1_in[65:0]       =  d1[65:0]                | sqe_cnt1[65:0];
  assign d2_00_in[65:0]       =  d1[65:0]                                ;
//assign d2_m1_in[65:0]       = (d1[65:0] ^ flip1[65:0]) | sqe_cnt1[65:0];

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66	ie_d00lth_p1or	 (
 .din0( d1[65:0]                 ),
 .din1( sqe_cnt1[65:0]           ),
 .dout( d2_p1_in[65:0]           ));

fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_66	ie_d00lth_m1xor	 (
 .din0( d1[65:0]                 ),
 .din1( flip1[65:0]              ),
 .dout( d2_m1xor[65:0]           ));

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66	ie_d00lth_m1or	 (
 .din0( d2_m1xor[65:0]           ),
 .din1( sqe_cnt1[65:0]           ),
 .dout( d2_m1_in[65:0]           ));

fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_66	ie_d00lth	 (
 .scan_in(ie_d00lth_scanin),
 .scan_out(ie_d00lth_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0( d2_m1_in[65:0]           ),
 .din1( d2_00_in[65:0]           ),
 .din2( d2_p1_in[65:0]           ),
 .din3( divisor_new[65:0]        ),
 .sel0( fdc_qsel1[0]             ),
 .sel1( fdc_qsel1[1]             ),
 .sel2( fdc_qsel1[2]             ),
 .sel3( engine_start             ),
 .dout( d0[65:0]                 ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign effd0_00[65:0]      =   d0[65:0];  Not used


// Post-LTH version of the logic
// assign effd0_p1_[65:0]     = ~( d0[65:0]              | sqe_cnt1[65:0]);

// Pre-LTH version of the logic
// assign effd2_p1_p1in       = ~( ( d1 | cnt1         ) | cnt3);
// assign effd2_00_p1in       = ~( ( d1                ) | cnt3);
// assign effd1_m1_p1in       = ~( ((d1 ^ flip1) | cnt1) | cnt3);

// assign effd2_p1_p1in[65:0] = ~( d1[65:0]                | sqe_cnt13[65:0]);
// assign effd2_00_p1in[65:0] = ~( d1[65:0]                | sqe_cnt3[65:0] );
// assign effd2_m1_p1in[65:0] = ~((d1[65:0] ^ flip1[65:0]) | sqe_cnt13[65:0]);
// assign effd2_xx_p1in[65:0] = ~(divisor_new[65:0]        | {2'b00,fdc_ie_fsqrt_valid_odd,fdc_ie_fsqrt_valid_even,{62{1'b0}}});

fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65	ie_d00lthp1_p1nor	 (
 .din0( d1[64:0]                 ),
 .din1( sqe_cnt13[64:0]          ),
 .dout( effd2_p1_p1in[64:0]      ));

fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65	ie_d00lthp1_00nor	 (
 .din0( d1[64:0]                 ),
 .din1( sqe_cnt3[64:0]           ),
 .dout( effd2_00_p1in[64:0]      ));

fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65	ie_d00lthp1_m1nor	 (
 .din0( d2_m1xor[64:0]           ),
 .din1( sqe_cnt13[64:0]          ),
 .dout( effd2_m1_p1in[64:0]      ));

fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65	ie_d00lthp1_xxnor	 (
 .din0( divisor_new[64:0]        ),
 .din1({1'b0,fdc_ie_fsqrt_valid_odd,fdc_ie_fsqrt_valid_even,{62{1'b0}}}),
 .dout( effd2_xx_p1in[64:0]      ));


fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_65	ie_d00lthp1	 (
 .scan_in(ie_d00lthp1_scanin),
 .scan_out(ie_d00lthp1_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0( effd2_m1_p1in[64:0]      ),
 .din1( effd2_00_p1in[64:0]      ),
 .din2( effd2_p1_p1in[64:0]      ),
 .din3( effd2_xx_p1in[64:0]      ),
 .sel0( fdc_qsel1[0]             ),
 .sel1( fdc_qsel1[1]             ),
 .sel2( fdc_qsel1[2]             ),
 .sel3( engine_start             ),
 .dout( effd0_p1_[64:0]          ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// Post-LTH version of the logic
// assign effd0_m1[65:0]      =  (d0[65:0] ^ (flip0[65:0] | sqe_cnt0[65:0])) | sqe_cnt1[65:0];
// assign effd0_m1[65:0]      =  (d0[65:0] ^  flip0[65:0]                  ) | sqe_cnt01[65:0];   d0 has no overlap w/ cnt0

// Pre-LTH version of the logic
// assign effd2_p1_m1in       = ( (d1 | cnt1) ^ flip2 )         | cnt2 | cnt3;     flip2 = cnt1; for p1 select
// assign effd2_p1_m1in       = ( (d1 | cnt1) ^ cnt1  )         | cnt2 | cnt3;     d1 has no overlap w/ cnt1
// assign effd2_p1_m1in       = (  d1                 )         | cnt2 | cnt3;

// assign effd1_00_m1in       = (  d1         ^ flip2 )         | cnt2 | cnt3;     flip2 = flip1 | cnt1; for 00 select
// assign effd1_00_m1in       = (  d1         ^ (flip1  | cnt1) | cnt2 | cnt3;     d1 has no overlap w/ cnt1
// assign effd1_00_m1in       = (  d1         ^ flip1 ) | cnt1  | cnt2 | cnt3;

// assign effd1_m1_m1in       = ( ((d1 ^ flip1) | cnt1) ^ flip2) | cnt2 | cnt3;    flip2 = cnt1; for m1 select
// assign effd1_m1_m1in       = ( ((d1 ^ flip1) | cnt1) ^ cnt1 ) | cnt2 | cnt3;    d1 has no overlap w/ cnt1
// assign effd1_m1_m1in       = ( ((d1 ^ flip1)                ) | cnt2 | cnt3;

// assign effd2_p1_m1in[65:0] =   d1[65:0]                | sqe_cnt23[65:0] ;
// assign effd2_00_m1in[65:0] =  (d1[65:0] ^ flip1[65:0]) | sqe_cnt123[65:0];
// assign effd2_m1_m1in[65:0] =  (d1[65:0] ^ flip1[65:0]) | sqe_cnt23[65:0] ;

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65	ie_d00lthm1_p1or 	 (
 .din0( d1[64:0]                 ),
 .din1( sqe_cnt23[64:0]          ),
 .dout( effd2_p1_m1in[64:0]      ));

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65	ie_d00lthm1_00or 	 (
 .din0( d2_m1xor[64:0]           ),
 .din1( sqe_cnt123[64:0]         ),
 .dout( effd2_00_m1in[64:0]      ));

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65	ie_d00lthm1_m1or 	 (
 .din0( d2_m1xor[64:0]           ),
 .din1( sqe_cnt23[64:0]          ),
 .dout( effd2_m1_m1in[64:0]      ));


fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_65	ie_d00lthm1	 (
 .scan_in(ie_d00lthm1_scanin),
 .scan_out(ie_d00lthm1_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0( effd2_m1_m1in[64:0]      ),
 .din1( effd2_00_m1in[64:0]      ),
 .din2( effd2_p1_m1in[64:0]      ),
 .din3( divisor_new[64:0]        ),
 .sel0( fdc_qsel1[0]             ),
 .sel1( fdc_qsel1[1]             ),
 .sel2( fdc_qsel1[2]             ),
 .sel3( engine_start             ),
 .dout( effd0_m1[64:0]           ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// fgu_fdq_cust ie_qslc00 (
//  .sum  ( s0[65:62]            ),
//  .carry( c0[65:62]            ),
//  .fdq_qip1 ( qsel00[2:0]          )); // q(i+1) == +1, 0, -1


fgu_fdd_dp_csa32_macro__stack_66c__width_65	ie_csa11	 (
 .i0   ( s0[64:0]                     ),
 .i1   ({c0[64:2],1'b0,fdc_bsign_lth }),
 .i2   ( effd0_m1[64:0]               ),
 .carry({ie_csa11_unused,c11[64:1]   }),
 .sum  (                 s11[64:0]    ));


fgu_fdd_dp_csa32_macro__stack_66c__width_65	ie_csa10	 (
 .i0   ( s0[64:0]                     ),
 .i1   ({c0[64:2],1'b0,fdc_bsign_lth_}),
 .i2   ( effd0_p1_[64:0]              ),
 .carry({ie_csa10_unused,c10[64:1]   }),
 .sum  (                 s10[64:0]    ));


fgu_fdd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_66c__width_65	ie_s1mux	 (
 .din0( s11[64:0]                ),
 .din1( s0[64:0]                 ),
 .din2( s10[64:0]                ),
 .sel0( fdc_qsel00[0]            ),
 .sel1( fdc_qsel00[1]            ),
 .sel2( fdc_qsel00[2]            ),
 .dout( s1[65:1]                 ));
				 
fgu_fdd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_66c__width_64	ie_c1mux	 (
 .din0( c11[64:1]                ),
 .din1({c0[64:2],1'b0           }),
 .din2( c10[64:1]                ),
 .sel0( fdc_qsel00[0]            ),
 .sel1( fdc_qsel00[1]            ),
 .sel2( fdc_qsel00[2]            ),
 .dout( c1[65:2]                 ));


// assign d1_p1_in[65:0]     =  d0[65:0]                | sqe_cnt0[65:0];
   assign d1_00_in[65:0]     =  d0[65:0]                                ;
// assign d1_m1_in[65:0]     = (d0[65:0] ^ flip0[65:0]) | sqe_cnt0[65:0];

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66	ie_d1mux_p1or	 (
 .din0( d0[65:0]                 ),
 .din1( sqe_cnt0[65:0]           ),
 .dout( d1_p1_in[65:0]           ));

fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_66	ie_d1mux_m1xor	 (
 .din0( d0[65:0]                 ),
 .din1( flip0[65:0]              ),
 .dout( d1_m1xor[65:0]           ));

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66	ie_d1mux_m1or	 (
 .din0( d1_m1xor[65:0]           ),
 .din1( sqe_cnt0[65:0]           ),
 .dout( d1_m1_in[65:0]           ));

fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_66	ie_d1mux	 (
 .din0( d1_m1_in[65:0]           ),
 .din1( d1_00_in[65:0]           ),
 .din2( d1_p1_in[65:0]           ),
 .sel0( fdc_qsel00[0]            ),
 .sel1( fdc_qsel00[1]            ),
 .sel2( fdc_qsel00[2]            ),
 .dout( d1[65:0]                 ));

// assign effd1_00[65:0]      =   d1[65:0];  Not used


// Post-MUX version of the logic
// assign effd1_p1_[65:0]     = ~( d1[65:0]                | sqe_cnt2[65:1]);

// assign effd1_p1_p1in[65:0] = ~( d0[65:0]                | sqe_cnt02[65:0]);
// assign effd1_00_p1in[65:0] = ~( d0[65:0]                | sqe_cnt2[65:0] );
// assign effd1_m1_p1in[65:0] = ~((d0[65:0] ^ flip0[65:0]) | sqe_cnt02[65:0]);

fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65	ie_d1muxp1_p1nor	 (
 .din0( d0[64:0]                 ),
 .din1( sqe_cnt02[64:0]          ),
 .dout( effd1_p1_p1in[64:0]      ));

fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65	ie_d1muxp1_00nor	 (
 .din0( d0[64:0]                 ),
 .din1( sqe_cnt2[64:0]           ),
 .dout( effd1_00_p1in[64:0]      ));

fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65	ie_d1muxp1_m1nor	 (
 .din0( d1_m1xor[64:0]           ),
 .din1( sqe_cnt02[64:0]          ),
 .dout( effd1_m1_p1in[64:0]      ));

fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_65	ie_d1muxp1	 (
 .din0( effd1_m1_p1in[64:0]      ),
 .din1( effd1_00_p1in[64:0]      ),
 .din2( effd1_p1_p1in[64:0]      ),
 .sel0( fdc_qsel00[0]            ),
 .sel1( fdc_qsel00[1]            ),
 .sel2( fdc_qsel00[2]            ),
 .dout( effd1_p1_[64:0]          ));


// Post-MUX version of the logic
// assign effd1_m1[65:0]      =  (d1[65:0] ^ (flip1[65:0] | sqe_cnt1[65:0])) | sqe_cnt2[65:1] ;

// Pre-MUX intermediate version of logic (see 'effd2_XX_m1in' for simplication details)
// assign effd1_p1_m1in       =  ( (d0          | sqe_cnt0) ^ (flip1 | sqe_cnt1)) | sqe_cnt2;
// assign effd1_00_m1in       =  (  d0                      ^ (flip1 | sqe_cnt1)) | sqe_cnt2;
// assign effd1_m1_m1in       =  (((d0 ^ flip0) | sqe_cnt0) ^ (flip1 | sqe_cnt1)) | sqe_cnt2;

// assign effd1_p1_m1in[65:0] =    d0[65:0]                | sqe_cnt12[65:0] ;
// assign effd1_00_m1in[65:0] =   (d0[65:0] ^ flip0[65:0]) | sqe_cnt012[65:0];
// assign effd1_m1_m1in[65:0] =   (d0[65:0] ^ flip0[65:0]) | sqe_cnt12[65:0] ;

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65	ie_d1muxm1_p1or	 (
 .din0( d0[64:0]                 ),
 .din1( sqe_cnt12[64:0]          ),
 .dout( effd1_p1_m1in[64:0]      ));

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65	ie_d1muxm1_00or	 (
 .din0( d1_m1xor[64:0]           ),
 .din1( sqe_cnt012[64:0]         ),
 .dout( effd1_00_m1in[64:0]      ));

fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65	ie_d1muxm1_m1or	 (
 .din0( d1_m1xor[64:0]           ),
 .din1( sqe_cnt12[64:0]          ),
 .dout( effd1_m1_m1in[64:0]      ));

fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_65	ie_d1muxm1	 (
 .din0( effd1_m1_m1in[64:0]      ),
 .din1( effd1_00_m1in[64:0]      ),
 .din2( effd1_p1_m1in[64:0]      ),
 .sel0( fdc_qsel00[0]            ),
 .sel1( fdc_qsel00[1]            ),
 .sel2( fdc_qsel00[2]            ),
 .dout( effd1_m1[64:0]           ));


// fgu_fdq_cust ie_qslc1p (
//  .sum      ( s11[64:61]           ),
//  .carry    ( c11[64:61]           ),
//  .fdq_qip1 ( qsel1p[2:0]          )); // q(i+1) == +1, 0, -1

// fgu_fdq_cust ie_qslc10 (
//  .sum      ( s0_buf[64:61]        ),
//  .carry    ( c0_buf[64:61]        ),
//  .fdq_qip1 ( qsel10[2:0]          )); // q(i+1) == +1, 0, -1

// fgu_fdq_cust ie_qslc1n (
//  .sum      ( s10[64:61]           ),
//  .carry    ( c10[64:61]           ),
//  .fdq_qip1 ( qsel1n[2:0]          )); // q(i+1) == +1, 0, -1


assign fdd_fdq00_10_sum[4:0]	= s0[65:61];
assign fdd_fdq00_10_carry[4:0]	= c0[65:61];

assign fdd_fdq1p_sum[3:0]	= s11[64:61];
assign fdd_fdq1p_carry[3:0]	= c11[64:61];

assign fdd_fdq1n_sum[3:0]	= s10[64:61];
assign fdd_fdq1n_carry[3:0]	= c10[64:61];


// Timing change : 7-17-02
//
// and_macro	ie_qslc00a	(width=3,ports=2,stack=66c) (
//  .din0 ( fdc_qsel00[2:0]      ),
//  .din1 ({3{engine_start_    }}),
//  .dout ( gated_qsel00[2:0]    ));
//
// mux_macro	ie_qslcmux	(width=3,ports=3,mux=aonpe,buffsel=none,stack=66c) (
//  .din0( qsel1p[2:0]         ),
//  .din1( qsel10[2:0]         ),
//  .din2( qsel1n[2:0]         ),  // PR(i+1) = PR(i) - qD;
//  .sel0( gated_qsel00[0]     ),  // PR + D -> therefore q = -1
//  .sel1( gated_qsel00[1]     ),
//  .sel2( gated_qsel00[2]     ),  // PR - D -> therefore q = +1
//  .dout( qsel1[2:0]          ));


fgu_fdd_dp_csa32_macro__stack_66c__width_65	ie_csa21	 (
 .i0   ({s1[64:1],1'b0               }),
 .i1   ({c1[64:2],1'b0,fdc_bsign_lth }),
 .i2   ( effd1_m1[64:0]               ),
 .carry({ie_csa21_unused,c21[64:1]   }),
 .sum  (                 s21[64:0]    ));


fgu_fdd_dp_csa32_macro__stack_66c__width_65	ie_csa20	 (
 .i0   ({s1[64:1],1'b0               }),
 .i1   ({c1[64:2],1'b0,fdc_bsign_lth_}),
 .i2   ( effd1_p1_[64:0]              ),
 .carry({ie_csa20_unused,c20[64:1]   }),
 .sum  (                 s20[64:0]    ));


// During pte_cycle[3], an extra shift will occur in both q_lth and qm1_lth.
// Both latches are made 2-bits wider so no data is lost.


// Floorplan note : pack "ie_qmuxh" and "ie_qmuxl" on same row

fgu_fdd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64	ie_qmuxh	 (
 .din0({64{1'b0}                }),
 .din1( q_lth[63:0]              ),
 .sel0( engine_start             ),
 .dout( q_in[65:2]               ));


fgu_fdd_dp_msff_macro__stack_66c__width_66	ie_qlth		 (
 .scan_in(ie_qlth_scanin),
 .scan_out(ie_qlth_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din ({q_in[65:2],fdc_q_in[1:0]}),
 .dout( q_lth[65:0]              ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fdd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64	ie_qm1muxh	 (
 .din0({64{1'b0}                }),
 .din1( qm1_lth[63:0]            ),
 .sel0( engine_start             ),
 .dout( qm1_in[65:2]             ));


fgu_fdd_dp_msff_macro__stack_66c__width_66	ie_qm1lth	 (
 .scan_in(ie_qm1lth_scanin),
 .scan_out(ie_qm1lth_scanout),
 .clk ( l2clk                        ),
 .en  ( div_clken_rep0               ),  // powerdown pin
 .din ({qm1_in[65:2],fdc_qm1_in[1:0]}),
 .dout( qm1_lth[65:0]                ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fdd_dp_inv_macro__stack_66c__width_65	 ie_qm1inv	 (
 .din ( qm1_lth[65:1]            ),
 .dout( qm1_lth_[65:1]           ));


// * * * * * * * * * * * * * * "post-engine" * * * * * * * * * * * * * * 

// The CIN to the adder for the R = Q - Qm1 cycle is very confusing.
// For positive operands it is fairly straight forward.  When we
// invert Qm1, we should add the CIN to create the 2's complement.
// However, when the final remainder is negative, the Q is one too
// large.  To correct for this, we need to add one to Qm1 before
// we compute the final result.  By withholding the CIN, we effectively
// make Qm1 appear one larger than what we originally logged.  
//
// For a negative B operand, the situation is more complicated.
// When the final remainder is positive, we need to add the CIN
// so that R = Q - Qm1 is computed correctly.  For a negative
// remainder, not only do we need to add the CIN for the 2's
// complement of Qm1, but we must also add a one to the Q.
// Remember that the logging of the quotient digits is reversed
// for a negative B operand.  So, when the final remainder is 
// negative, that means that Qm1 is one larger than is should have
// been.  To correct, we need to add one to the Q to correct.
//
// Notice the the table has a symmetry around the A operand.
// The correction method (adding one to Q or to Qm1) becomes
// reversed when A is negative.
//
// The table below will summarize.  ('->' is a correction row)
//
//   Sign of   Sign of   Sign of    |   Zero                Method
//      A         B     Remainder   | Remainder  Action |  CSA   Cin
//   -------------------------------|-------------------|-----------
//      0         0         0       |            add 1  |   0     1
//  ->  0         0         1       |            add 0  |   0     0
//      0         1         0       |            add 1  |   1     0
//  ->  0         1         1       |            add 2  |   1     1
//      1         0         0       |  yes       add 1  |   1     0
//  ->  1         0         0       |  no        add 2  |   1     1
//      1         0         1       |            add 1  |   1     0
//      1         1         0       |  yes       add 1  |   0     1
//  ->  1         1         0       |  no        add 0  |   0     0
//      1         1         1       |            add 1  |   0     1


fgu_fdd_dp_mux_macro__mux_aope__ports_4__stack_66c__width_64	ipte_qmux	 (
 .din0( q_lth[65:2]               ),  // INT even ndp
 .din1( q_lth[64:1]               ),  // INT odd  ndq correction
 .din2({q_lth[55:1],{ 9{1'b0}}   }),  // FLT DP
 .din3({q_lth[27:2],{38{1'b0}}   }),  // FLT SP 
 .sel0( fdc_pte_qsel[0]           ),
 .sel1( fdc_pte_qsel[1]           ),
 .sel2( fdc_pte_qsel[2]           ),
 .dout( pte_q[65:2]               ));

fgu_fdd_dp_mux_macro__mux_aope__ports_4__stack_66c__width_64	ipte_qm1mux	 (
 .din0( qm1_lth_[65:2]            ),  // INT even ndq
 .din1( qm1_lth_[64:1]            ),  // INT odd  ndq correction
 .din2({qm1_lth_[55:1],{ 9{1'b1}}}),  // FLT DP
 .din3({qm1_lth_[27:2],{38{1'b1}}}),  // FLT SP 
 .sel0( fdc_pte_qsel[0]           ),
 .sel1( fdc_pte_qsel[1]           ),
 .sel2( fdc_pte_qsel[2]           ),
 .dout( pte_qm1_[65:2]            ));

fgu_fdd_dp_csa32_macro__stack_66c__width_64	ipte_csa	 (
 .i0   ( pte_q[65:2]                     ),
 .i1   ( pte_qm1_[65:2]                  ),
 .i2   ({{63{1'b0}}, fdc_pte_csa_cin    }),
 .carry({ipte_csa_unused,pte_carry[63:1]}),
 .sum  (                 pte_sum[63:0]   ));


fgu_fdd_dp_msff_macro__mux_aope__ports_6__stack_66c__width_65	ipte_clalth0	 (
 .scan_in(ipte_clalth0_scanin),
 .scan_out(ipte_clalth0_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0( s0[65:1]                 ),
 .din1( s1[65:1]                 ),  // odd ndq correction
 .din2({1'b0,pte_sum[63:0]}      ),  // append cin=1 for Q-Qm1 to din1
 .din3({1'b0,pte_cla[63:0]}      ),
 .din4({1'b0,pte_cla[63:0]}      ),
 .din5({1'b0,pte_cla[62:0],1'b0} ),
 .sel0( fdc_pte_clasel[0]        ),
 .sel1( fdc_pte_clasel[1]        ),
 .sel2( fdc_pte_cycle2           ),
 .sel3( pte_cla[63]              ),
 .sel4( fdc_emin_lth             ),
 .dout( pte_clalth0[64:0]        ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fdd_dp_msff_macro__mux_aope__ports_4__stack_66c__width_65	ipte_clalth1	 (
 .scan_in(ipte_clalth1_scanin),
 .scan_out(ipte_clalth1_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0({c0[65:2],1'b0}           ),
 .din1({c1[65:2],1'b0}           ),  // odd ndq correction
 .din2({1'b0,pte_carry[63:1],
        fdc_fdx_cin_in}          ),
 .din3({{24{1'b0}},
        fdc_flt_round[1],
        {28{1'b0}},
        fdc_flt_round[0],
        {11{1'b0}}}              ),
 .sel0( fdc_pte_clasel[0]        ),
 .sel1( fdc_pte_clasel[1]        ),
 .sel2( fdc_pte_cycle2           ),
 .dout( pte_clalth1[64:0]        ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// hnb_fg_claz65 fpd_cla (
//  .din0      ( pte_clalth0[64:0]      ),
//  .din1      ({pte_clalth1[64:1],1'b0}),
//  .cin       ( pte_cin                ),
//  .asign     ( fdc_asign_lth          ),
//  .bsign     ( fdc_bsign_lth          ),
//  .cin_enable( fdc_pte_cycle2         ),
//    .pte_cla    ( pte_cla[64:0]         ),
//    .pte_zdetect( pte_zerodetect        ),
//    .pte_cin_in ( pte_cin_in            ));


fgu_fdd_dp_cla_macro__width_64	ipte_cla	 (
  .din0      ( pte_clalth0[63:0]      ),
  .din1      ( pte_clalth1[63:0]      ),
  .cin       ( 1'b0                   ),
    .dout      ( pte_cla[63:0]          ),
    .cout      ( pte_cla_cout           ));

fgu_fdd_dp_and_macro__ports_2__stack_66c__width_1	ipte_cla63_and	 (
  .din0      ( pte_cla[63]            ),
  .din1      ( fdc_flt_increment      ),
    .dout      ( fdd_pte_cla_early_b63  ));

cl_dp1_zdt64_8x	ipte_claz	(
  .din0      ( pte_clalth0[63:0]      ),
  .din1      ( pte_clalth1[63:0]      ),
  .cin       ( 1'b0                   ),
    .zdt_z32_      ( fdd_cla_zero32_        ),
    .zdt_z64_      ( fdd_cla_zero64_        ));

// fgu_fdx_cust	ipte_cla65	(
//   .din0      ( pte_clalth0[64]        ),
//   .din1      ( pte_clalth1[64]        ),
//   .cin64     ( pte_cla_cout           ),
//   .asign     ( fdc_asign_lth          ),
//   .bsign     ( fdc_bsign_lth          ),
//   .cin_enable( fdc_pte_cycle2         ),
//   .z64_l     ( fdd_cla_zero64_        ),
//     .fdx_cin_in( pte_cin_in             ));


assign fdd_fdx_din0	= pte_clalth0[64];
assign fdd_fdx_din1	= pte_clalth1[64];
assign fdd_fdx_cin64	= pte_cla_cout;


fgu_fdd_dp_msff_macro__mux_aope__ports_6__stack_66c__width_64	ipte_result	 (
 .scan_in(ipte_result_scanin),
 .scan_out(ipte_result_scanout),
 .clk ( l2clk                                                  ),
 .en  ( fdc_pte_stall_                                         ),  // powerdown pin
 .din0( 64'h8000000000000000                                   ),
 .din1( 64'hffffffff80000000                                   ),
 .din2( 64'h000000007fffffff                                   ),
 .din3( 64'h00000000ffffffff                                   ),
 .din4({fdd_result[62:0],1'b0}                                 ),
 .din5( pte_cla[63:0]                                          ),
 .sel0( fdc_idiv_ctl[0]                                        ),
 .sel1( fdc_idiv_ctl[1]                                        ),
 .sel2( fdc_idiv_ctl[2]                                        ),
 .sel3( fdc_idiv_ctl[3]                                        ),
 .sel4( fdc_idiv_ctl[4]                                        ),
 .dout( fdd_result[63:0]                                       ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// * * * * * * * * * * * * * * square root * * * * * * * * * * * * * * 

// The CNT bit represents where the newest effective divisor digit will go.
// For divide instruction, this latch will be all 0's and the original divisor
//   will remain unchanged.
// The 'flip' register allows us to quickly compute the effect of a "-1" at position
//   "i" will have on the next effective divisor.

// Define cnt(i)  == single bit ON with position "i";
//        Q(0)    == 0;
//        flip(0) == 0;

// for "+1" -> Q(i+1)    =  Q(i)            | cnt(i);
//             flip(i+1) =  cnt(i)                  ;

// for "-1" -> Q(i+1)    = (Q(i) ^ flip(i)) | cnt(i);
//             flip(i+1) =  cnt(i)                  ;

// for " 0" -> Q(i+1)    =  Q(i)                    ;
//             flip(i+1) =  cnt(i) | flip(i)        ;


// Example :   let i    = 000000001
//             let Q    = 011010000
//            then flip = 000011110
//
// if we get a "-1" at i, then 
//                 Q    = (Q ^ flip) | cnt
//                 Q    = 011001111;      this is the same as a "-1" at "i" added to Q

fgu_fdd_dp_msff_macro__mux_aope__ports_2__stack_66c__width_66	isqe_cnt	 (
 .scan_in(isqe_cnt_scanin),
 .scan_out(isqe_cnt_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0({1'b1,
        fdc_ie_fsqrt_valid_odd_,
        fdc_ie_fsqrt_valid_even_,
        {63{1'b1}}              }),
 .din1( sqe_cnt2_[65:0]          ),
 .sel0( engine_start             ),  //
 .dout( sqe_cnt0_[65:0]          ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fdd_dp_inv_macro__stack_66c__width_66	 isqe_cntinv	 (
 .din ( sqe_cnt0_[65:0]          ),
 .dout( sqe_cnt0[65:0]           ));


fgu_fdd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66	isqe_flip	 (
 .scan_in(isqe_flip_scanin),
 .scan_out(isqe_flip_scanout),
 .clk ( l2clk                    ),
 .en  ( div_clken_rep0           ),  // powerdown pin
 .din0( flip1[65:0]              ),
 .din1( sqe_cnt1[65:0]           ),
 .sel0( fdc_qsel1[1]             ),
 .sel1( engine_start_            ),  // mux output == flip2
 .dout( flip0[65:0]              ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// assign flip1[65:0]       = sqe_cnt0[65:0] |               
//                            ({66{fdc_qsel00[1]}} & flip0[65:0]);

// assign flip2[65:0]       = sqe_cnt1[65:0] |               
//                            ({66{qsel1[1]}}  & flip1[65:0]);

fgu_fdd_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_66	isqe_flip1	 (
 .din0( flip0[65:0]              ),
 .din1( sqe_cnt0[65:0]           ),
 .sel0( fdc_qsel00[1]            ),
 .sel1( 1'b1                     ),
 .dout( flip1[65:0]              ));


assign sqe_cnt1[65:0]    = {1'b0  ,sqe_cnt0[65:1]};
assign sqe_cnt2[64:0]    = {1'b0  ,sqe_cnt0[65:2]};
assign sqe_cnt3[64:0]    = {2'b00 ,sqe_cnt0[65:3]};

assign sqe_cnt1_[65:0]   = {1'b1  ,sqe_cnt0_[65:1]};
assign sqe_cnt2_[65:0]   = {2'b11 ,sqe_cnt0_[65:2]};
// assign sqe_cnt3_[65:0]   = {3'b111,sqe_cnt0_[65:3]};

// assign sqe_cnt012[65:0]  = sqe_cnt0[65:0] | sqe_cnt1[65:0] | sqe_cnt2[65:0]                 ;
// assign sqe_cnt01[65:0]   = sqe_cnt0[65:0] | sqe_cnt1[65:0]                                  ;
// assign sqe_cnt02[65:0]   = sqe_cnt0[65:0] |                  sqe_cnt2[65:0]                 ;
// assign sqe_cnt12[65:0]   =                  sqe_cnt1[65:0] | sqe_cnt2[65:0]                 ;
// assign sqe_cnt123[65:0]  =                  sqe_cnt1[65:0] | sqe_cnt2[65:0] | sqe_cnt3[65:0];
// assign sqe_cnt13[65:0]   =                  sqe_cnt1[65:0] |                  sqe_cnt3[65:0];
// assign sqe_cnt23[65:0]   =                                   sqe_cnt2[65:0] | sqe_cnt3[65:0];


fgu_fdd_dp_nand_macro__ports_3__stack_66c__width_66	isqe_cnt012	 (
 .din0( sqe_cnt0_[65:0]          ),
 .din1( sqe_cnt1_[65:0]          ),
 .din2( sqe_cnt2_[65:0]          ),
 .dout( sqe_cnt012[65:0]         ));

fgu_fdd_dp_nand_macro__ports_2__stack_66c__width_65	isqe_cnt01 	 (
 .din0( sqe_cnt0_[65:1]          ),
 .din1( sqe_cnt1_[65:1]          ),
 .dout( sqe_cnt01[65:1]          ));

fgu_fdd_dp_nand_macro__ports_2__stack_66c__width_66	isqe_cnt02 	 (
 .din0( sqe_cnt0_[65:0]          ),
 .din1( sqe_cnt2_[65:0]          ),
 .dout( sqe_cnt02[65:0]          ));

assign sqe_cnt12[64:0]   =        sqe_cnt01[65:1];
assign sqe_cnt123[64:0]  =        sqe_cnt012[65:1];
assign sqe_cnt13[64:0]   =        sqe_cnt02[65:1];
assign sqe_cnt23[64:0]   = {1'b0 ,sqe_cnt01[65:2]};


// * * * * * * * * * * * * * * square root * * * * * * * * * * * * * * 
// 
//                     Float Square Root Example
//
// see ~co132877/design/doc/fsqrt_examples for additional examples
// 
// Notes :
// 
//   1. PR(i+1) = 2PR(i) - q(i+1) * Dnew
//   2. Dnew = 2*Q(i) + q(i+1) * 2^-(i+1)
//   3. Q(i) == estimate of sqrt(RB) after ith iteration
//   4. PR(0) == RB
//   5. Q(0)  == 0
// 
// 
// Example 1 : RB = 1.1000 0000 0000    (PR kept in non-redundant form)
// 
//             RD = sqrt(RB) = 1.0011 1001 1000 1000 ...   (from architectural simulator)
// 
// 
//  i      divisor                   qslc    engine                       Q// Qm1
//  -      ------------------------  ----    ------------------------     ---------------
//              v
//  1      00.0 1000 0000 0000 0000   +1     00.0 1100 0000 0000 0000     1.
//                                          +11.1 1000 0000 0000 0000    -0.
//                                           ------------------------     --
//                                           00.0 0100 0000 0000 0000     1.
// 
//               v
//  2      00.1 0100 0000 0000 0000   +1     00.0 1000 0000 0000 0000     1.1
//                                          +11.0 1100 0000 0000 0000    -0.0
//                                           ------------------------     ---
//                                           11.1 0100 0000 0000 0000     1.1
// 
//                v
//  3      00.1 10m0 0000 0000 0000   -1     11.0 1000 0000 0000 0000     1.10
//         00.1 0110 0000 0000 0000         +00.1 0110 0000 0000 0000    -0.01
//                                           ------------------------     ----
//                                           11.1 1110 0000 0000 0000     1.01
// 
//                 v
//  4      00.1 0100 0000 0000 0000    0     11.1 1100 0000 0000 0000     1.100
//                                          +00.0 0000 0000 0000 0000    -0.010
//                                           ------------------------     -----
//                                           11.1 1100 0000 0000 0000     1.010
// 
//                   v
//  5      00.1 0100 0000 0000 0000    0     11.1 1000 0000 0000 0000     1.1000
//                                          +00.0 0000 0000 0000 0000    -0.0100
//                                           ------------------------     ------
//                                           11.1 1000 0000 0000 0000     1.0100
// 
//                    v
//  6      00.1 0100 0m00 0000 0000   -1     11.1 0000 0000 0000 0000     1.1000 0
//         00.1 0011 1100 0000 0000         +00.1 0011 1100 0000 0000    -0.0100 1
//                                           ------------------------     --------
//                                           00.0 0011 1100 0000 0000     1.0011 1
// 
//                     v
//  7      00.1 0011 1000 0000 0000    0     00.0 0111 1000 0000 0000     1.1000 00
//                                          +00.0 0000 0000 0000 0000    -0.0100 10
//                                           ------------------------     ---------
//                                           00.0 0111 1000 0000 0000     1.0011 10
// 
//                      v
//  8      00.1 0011 1001 0000 0000   +1     00.0 1111 0000 0000 0000     1.1000 001
//                                          +11.0 1100 0111 0000 0000    -0.0100 100
//                                           ------------------------     ----------
//                                           11.1 1011 0111 0000 0000     1.0011 101
// 
//                        v
//  9      00.1 0011 1010 m000 0000   -1     11.1 0110 1110 0000 0000     1.1000 0010
//         00.1 0011 1001 1000 0000         +00.1 0011 1001 1000 0000    -0.0100 1001
//                                           ------------------------     -----------
//                                           00.0 1010 0111 1000 0000     1.0011 1001
// 
//                         v
//  10     00.1 0011 1001 0100 0000   +1     00.1 0100 1111 0000 0000     1.1000 0010 1
//                                          +11.0 1100 0110 1100 0000    -0.0100 1001 0
//                                           ------------------------     -------------
//                                           00.0 0001 0101 1100 0000     1.0011 1001 1
// 
//                          v
//  11     00.1 0011 1001 1000 0000    0     00.0 0010 1011 1000 0000     1.1000 0010 10
//                                          +00.0 0000 0000 0000 0000    -0.0100 1001 00
//                                           ------------------------     --------------
//                                           00.0 0010 1011 1000 0000     1.0011 1001 10
// 
//                           v
//  12     00.1 0011 1001 1000 0000    0     00.0 0101 0111 0000 0000     1.1000 0010 100
//                                          +00.0 0000 0000 0000 0000    -0.0100 1001 000
//                                           ------------------------     ---------------
//                                           00.0 0101 0111 0000 0000     1.0011 1001 100
// 
//                             v
//  13     00.1 0011 1001 1000 1000   +1     00.0 1010 1110 0000 0000     1.1000 0010 1001
//                                          +11.0 1100 0110 0111 1000    -0.0100 1001 0000
//                                           ------------------------     ----------------
//                                           11.1 0111 0100 0111 1000     1.0011 1001 1001
// 
//                              v
//  14     00.1 0011 1001 1001 0m00   -1     11.0 1110 1000 1111 0000     1.1000 0010 1001 0
//         00.1 0011 1001 1000 1100         +00.1 0011 1001 1000 1100    -0.0100 1001 0000 1
//                                           ------------------------     ------------------
//                                           00.0 0011 0010 0111 1100     1.0011 1001 1000 1
// 
// 
//                                                        RD = sqrt(RB) = 1.0011 1001 1000 1000 ...
// 
//  END EXAMPLE


// fixscan start:
assign q_rs1_ff_scanin           = scan_in                  ;
assign q_rs2_ff_scanin           = q_rs1_ff_scanout         ;
assign ipe_clth_scanin           = q_rs2_ff_scanout         ;
assign ipe_slth_scanin           = ipe_clth_scanout         ;
assign ie_s00lth_scanin          = ipe_slth_scanout         ;
assign ie_c00lth_scanin          = ie_s00lth_scanout        ;
assign ie_d00lth_scanin          = ie_c00lth_scanout        ;
assign ie_d00lthp1_scanin        = ie_d00lth_scanout        ;
assign ie_d00lthm1_scanin        = ie_d00lthp1_scanout      ;
assign ie_qlth_scanin            = ie_d00lthm1_scanout      ;
assign ie_qm1lth_scanin          = ie_qlth_scanout          ;
assign ipte_clalth0_scanin       = ie_qm1lth_scanout        ;
assign ipte_clalth1_scanin       = ipte_clalth0_scanout     ;
assign ipte_result_scanin        = ipte_clalth1_scanout     ;
assign isqe_cnt_scanin           = ipte_result_scanout      ;
assign isqe_flip_scanin          = isqe_cnt_scanout         ;
assign scan_out                  = isqe_flip_scanout        ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module fgu_fdd_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__stack_66c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aope__ports_3__stack_66c__width_64 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aope__ports_4__stack_66c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input sel0;
  input sel1;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc4_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__mux_aodec__ports_8__stack_66c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input [2:0] sel;
  output [63:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fdd_dp_buff_macro__stack_66c__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;


xor2 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__mux_aonpe__ports_5__stack_66c__width_66 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [65:0] din0;
  input sel0;
  input [65:0] din1;
  input sel1;
  input [65:0] din2;
  input sel2;
  input [65:0] din3;
  input sel3;
  input [65:0] din4;
  input sel4;
  output [65:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(66)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
  .in2(din2[65:0]),
  .in3(din3[65:0]),
  .in4(din4[65:0]),
.dout(dout[65:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_66 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [65:0] din0;
  input sel0;
  input [65:0] din1;
  input sel1;
  input [65:0] din2;
  input sel2;
  output [65:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(66)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
  .in2(din2[65:0]),
.dout(dout[65:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module fgu_fdd_dp_or_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module fgu_fdd_dp_nor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_66 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire [65:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din0;
  input sel0;
  input [65:0] din1;
  input sel1;
  input [65:0] din2;
  input sel2;
  input [65:0] din3;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_muxbuff4_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(66)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
  .in2(din2[65:0]),
  .in3(din3[65:0]),
.dout(muxout[65:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_muxbuff4_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66 (
  din0, 
  din1, 
  dout);
  input [65:0] din0;
  input [65:0] din1;
  output [65:0] dout;


or2 #(66)  d0_0 (
.in0(din0[65:0]),
.in1(din1[65:0]),
.out(dout[65:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_66 (
  din0, 
  din1, 
  dout);
  input [65:0] din0;
  input [65:0] din1;
  output [65:0] dout;


xor2 #(66)  d0_0 (
.in0(din0[65:0]),
.in1(din1[65:0]),
.out(dout[65:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 (
  din0, 
  din1, 
  dout);
  input [64:0] din0;
  input [64:0] din1;
  output [64:0] dout;


nor2 #(65)  d0_0 (
.in0(din0[64:0]),
.in1(din1[64:0]),
.out(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_65 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire [64:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din0;
  input sel0;
  input [64:0] din1;
  input sel1;
  input [64:0] din2;
  input sel2;
  input [64:0] din3;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_muxbuff4_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(65)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
  .in3(din3[64:0]),
.dout(muxout[64:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65 (
  din0, 
  din1, 
  dout);
  input [64:0] din0;
  input [64:0] din1;
  output [64:0] dout;


or2 #(65)  d0_0 (
.in0(din0[64:0]),
.in1(din1[64:0]),
.out(dout[64:0])
);


endmodule


//
//      3:2 Carry Save Adder
//
//


// any PARAMS parms go into naming of macro


module fgu_fdd_dp_csa32_macro__stack_66c__width_65 (
  i0, 
  i1, 
  i2, 
  carry, 
  sum);
  input  [64:0] i0;
  input  [64:0] i1;
  input  [64:0] i2;
  output [64:0] carry;
  output [64:0] sum;


csa32 #(65)  d0_0 (
.in0(i0[64:0]),
.in1(i1[64:0]),
.in2(i2[64:0]),
.carry(carry[64:0]),
.sum(sum[64:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_66c__width_65 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [64:0] din0;
  input sel0;
  input [64:0] din1;
  input sel1;
  input [64:0] din2;
  input sel2;
  output [64:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(65)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
.dout(dout[64:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_66c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  output [63:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_65 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [64:0] din0;
  input sel0;
  input [64:0] din1;
  input sel1;
  input [64:0] din2;
  input sel2;
  output [64:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(65)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
.dout(dout[64:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__stack_66c__width_66 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fdd_dp_inv_macro__stack_66c__width_65 (
  din, 
  dout);
  input [64:0] din;
  output [64:0] dout;


inv #(65)  d0_0 (
.in(din[64:0]),
.out(dout[64:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__mux_aope__ports_4__stack_66c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [63:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


//
//      3:2 Carry Save Adder
//
//


// any PARAMS parms go into naming of macro


module fgu_fdd_dp_csa32_macro__stack_66c__width_64 (
  i0, 
  i1, 
  i2, 
  carry, 
  sum);
  input  [63:0] i0;
  input  [63:0] i1;
  input  [63:0] i2;
  output [63:0] carry;
  output [63:0] sum;


csa32 #(64)  d0_0 (
.in0(i0[63:0]),
.in1(i1[63:0]),
.in2(i2[63:0]),
.carry(carry[63:0]),
.sum(sum[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aope__ports_6__stack_66c__width_65 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire [64:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din0;
  input [64:0] din1;
  input [64:0] din2;
  input [64:0] din3;
  input [64:0] din4;
  input [64:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_penc6_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5)
);

mux6s #(65)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
  .in3(din3[64:0]),
  .in4(din4[64:0]),
  .in5(din5[64:0]),
.dout(muxout[64:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aope__ports_4__stack_66c__width_65 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire [64:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din0;
  input [64:0] din1;
  input [64:0] din2;
  input [64:0] din3;
  input sel0;
  input sel1;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_penc4_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(65)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
  .in3(din3[64:0]),
.dout(muxout[64:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


//
//   cla macro
//
//


module fgu_fdd_dp_cla_macro__width_64 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;
  output cout;


cla #(64)  m0_0 (
.cin(cin),
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0]),
.cout(cout)
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fdd_dp_and_macro__ports_2__stack_66c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aope__ports_6__stack_66c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc6_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5)
);

mux6s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aope__ports_2__stack_66c__width_66 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [65:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din0;
  input [65:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(66)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
.dout(muxout[65:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fdd_dp_inv_macro__stack_66c__width_66 (
  din, 
  dout);
  input [65:0] din;
  output [65:0] dout;


inv #(66)  d0_0 (
.in(din[65:0]),
.out(dout[65:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire [65:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din0;
  input sel0;
  input [65:0] din1;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_muxbuff2_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(66)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
.dout(muxout[65:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fdd_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_66 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [65:0] din0;
  input sel0;
  input [65:0] din1;
  input sel1;
  output [65:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(66)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
.dout(dout[65:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fdd_dp_nand_macro__ports_3__stack_66c__width_66 (
  din0, 
  din1, 
  din2, 
  dout);
  input [65:0] din0;
  input [65:0] din1;
  input [65:0] din2;
  output [65:0] dout;


nand3 #(66)  d0_0 (
.in0(din0[65:0]),
.in1(din1[65:0]),
.in2(din2[65:0]),
.out(dout[65:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fdd_dp_nand_macro__ports_2__stack_66c__width_65 (
  din0, 
  din1, 
  dout);
  input [64:0] din0;
  input [64:0] din1;
  output [64:0] dout;


nand2 #(65)  d0_0 (
.in0(din0[64:0]),
.in1(din1[64:0]),
.out(dout[64:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fdd_dp_nand_macro__ports_2__stack_66c__width_66 (
  din0, 
  din1, 
  dout);
  input [65:0] din0;
  input [65:0] din1;
  output [65:0] dout;


nand2 #(66)  d0_0 (
.in0(din0[65:0]),
.in1(din1[65:0]),
.out(dout[65:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fec_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fec_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_se_scancollar_out, 
  mbi_frf_read_en, 
  mbi_wdata, 
  mbi_run, 
  fad_mbist_cmp64_fx1, 
  lsu_asi_error_inject, 
  scan_out, 
  fad_nombi_w2_result_fw, 
  fec_w1_ecc_inject_fb, 
  fec_w2_synd_fw, 
  fec_r1_ecc_fx1, 
  fec_mbist_wdata_1f, 
  fec_mbist_wdata_3f, 
  main_clken, 
  coreon_clken, 
  fac_frf_r1_addr_e, 
  fac_dec_valid_fx1, 
  fac_fgx_pdist_fx1, 
  fac_ecc_trap_en_fx1, 
  fac_r1_vld_fx1, 
  fac_r2_vld_fx1, 
  fad_r1_byp_hit_fx1, 
  fad_r2_byp_hit_fx1, 
  fpc_frf_store_vld_fx1, 
  dec_frf_r2_addr_d, 
  dec_frf_r1_32b_d, 
  dec_frf_r2_32b_d, 
  dec_frf_r1_odd32b_d, 
  dec_frf_r2_odd32b_d, 
  dec_flush_f1, 
  dec_flush_f2, 
  tlu_flush_fgu_b, 
  fad_rs1_fx1, 
  fad_rs2_fx1, 
  fad_i_parity_2e_fx1, 
  fad_i_parity_2o_fx1, 
  fad_i_parity_1e_fx1, 
  fad_i_parity_1o_fx1, 
  frf_r1_ecc_e, 
  frf_r2_ecc_e, 
  fgu_pdist_beat2_fx1, 
  fgu_ecc_addr_fx2, 
  fgu_ecc_check_fx2, 
  fgu_cecc_fx2, 
  fec_cecc_fx2, 
  fgu_uecc_fx2, 
  fec_uecc_fx2, 
  fgu_fst_ecc_error_fx2, 
  fgu_mbi_frf_fail);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk_pm2;
wire l1clk_pm1;
wire l1clk_sc;
wire spares_scanin;
wire spares_scanout;
wire rs1e_ecc_valid_fx1;
wire rs1o_ecc_valid_fx1;
wire rs2e_ecc_valid_fx1;
wire rs2o_ecc_valid_fx1;
wire frf_rs1_check_flops_e_fx1_scanin;
wire frf_rs1_check_flops_e_fx1_scanout;
wire [13:0] r1_ecc_check_fx1;
wire [13:0] r2_ecc_check_fx1;
wire [13:0] r1_ecc_check_fx2;
wire [13:0] r2_ecc_check_fx2;
wire frf_rs1_ecc_flops_e_fx1_scanin;
wire frf_rs1_ecc_flops_e_fx1_scanout;
wire pre_frf_fail;
wire mbist_frf_read_en_3f;
wire frf_rs2_ecc_flops_e_fx1_scanin;
wire frf_rs2_ecc_flops_e_fx1_scanout;
wire [13:0] r2_ecc_fx1;
wire [31:0] d1e;
wire [6:0] p1e;
wire [31:0] d1o;
wire [6:0] p1o;
wire [31:0] d2e;
wire [6:0] p2e;
wire [31:0] d2o;
wire [6:0] p2o;
wire rs1_ue_or_ce_fx1;
wire rs1e_ne;
wire rs1o_ne;
wire detect_ue_fx1;
wire rs1e_ue;
wire rs1o_ue;
wire rs2e_ue;
wire rs2o_ue;
wire detect_ce_fx1;
wire rs1e_ce;
wire rs1o_ce;
wire rs2e_ce;
wire rs2o_ce;
wire fst_ecc_error_fx1;
wire addr_flops_scanin;
wire addr_flops_scanout;
wire [4:0] r2_addr_e;
wire r1_32b_e;
wire r2_32b_e;
wire r1_odd32b_e;
wire r2_odd32b_e;
wire detect_ce_fx2;
wire detect_ue_fx2;
wire mbist_frf_read_en_1f;
wire mbist_frf_read_en_2f;
wire [7:0] mbist_wdata_2f;
wire [5:0] r1_expanded_addr_fx1;
wire [5:0] r2_expanded_addr_fx1;
wire [4:0] r1_addr_fx1;
wire [4:0] r2_addr_fx1;
wire r1_32b_fx1;
wire r2_32b_fx1;
wire r1_odd32b_fx1;
wire r2_odd32b_fx1;
wire fgx_pdist_fx2;
wire dec_valid_fx2;
wire dec_flush_fx2;
wire dec_flush_fx3;
wire frf_store_vld_fx2;
wire ecc_mask_global_en;
wire ecc_mask_frf_en;
wire [6:0] ecc_mask_data;
wire ecc_trap_en_fx2;
wire detect_ce_fx3;
wire detect_ue_fx3;
wire tlu_flush_fgu_fx3;
wire i_pdist_beat2_fx2;
wire mbist_run_1f;
wire rs1_ue_or_ce_fx2;
wire [5:0] r1_expanded_addr_fx2;
wire [5:0] r2_expanded_addr_fx2;
wire addr_flops2_scanin;
wire addr_flops2_scanout;
wire parity_1e;
wire [5:0] q1e;
wire parity_1o;
wire [5:0] q1o;
wire parity_2e;
wire [5:0] q2e;
wire parity_2o;
wire [5:0] q2o;
wire ce_ue_fec_flops_fx1_fx2_scanin;
wire ce_ue_fec_flops_fx1_fx2_scanout;
wire pdist_beat2_fx2;
wire frf_rd_vld_fx2;
wire [31:0] w2e;
wire [6:0] s2e;
wire [31:0] w2o;
wire [6:0] s2o;


// *** Global Inputs ***

input		l2clk;
input  		scan_in;
input  		tcu_pce_ov;		// scan signals
input  		spc_aclk;
input  		spc_bclk;
input           tcu_scan_en;
input           tcu_se_scancollar_out;
input           mbi_frf_read_en;        // MBIST
input    [7:0]  mbi_wdata;              // MBIST
input           mbi_run;                // MBIST
input           fad_mbist_cmp64_fx1;    // MBIST
input   [31:0]  lsu_asi_error_inject;   // [31]=global inject en, [24]=FRF inject en, [7:0]=mask

output 		scan_out;

// *** Generate ECC Local Inputs *** 

input 	[63:0]	fad_nombi_w2_result_fw;	// FRF w2 write data w/out mbist data muxed in

// *** Generate ECC Local Outputs *** 

output   [6:0]  fec_w1_ecc_inject_fb;   // ECC error injection
output	[13:0]	fec_w2_synd_fw;		// Generated ECC to FRF W2 port
output  [13:0]  fec_r1_ecc_fx1;         // ASI FRF ECC read data

output   [7:0]  fec_mbist_wdata_1f;     // MBIST
output   [7:0]  fec_mbist_wdata_3f;     // MBIST

// *** Check ECC Inputs *** 

input           main_clken;             // main clken
input           coreon_clken;           // controls all "free running" flops
input    [4:0]  fac_frf_r1_addr_e;
input           fac_dec_valid_fx1;
input           fac_fgx_pdist_fx1;      // PDIST
input           fac_ecc_trap_en_fx1;
input   [1:0] 	fac_r1_vld_fx1;         // FRF r1 read valid (unqualified)
input   [1:0] 	fac_r2_vld_fx1;         // FRF r2 read valid (unqualified)
input         	fad_r1_byp_hit_fx1;     // r1 is bypass data
input         	fad_r2_byp_hit_fx1;     // r2 is bypass data
input           fpc_frf_store_vld_fx1;

input   [4:0]   dec_frf_r2_addr_d;
input           dec_frf_r1_32b_d;       // FRF r1 is 32-bit source
input           dec_frf_r2_32b_d;       // FRF r2 is 32-bit source
input           dec_frf_r1_odd32b_d;    // FRF r1 is odd 32-bit source (32 LSBs)
input           dec_frf_r2_odd32b_d;    // FRF r2 is odd 32-bit source (32 LSBs) (incl. STF,STDF)
input           dec_flush_f1;           // flush fx2 (xmit in fx1/m)
input           dec_flush_f2;           // flush fx3 (xmit in fx2/b)
input           tlu_flush_fgu_b;        // flush fx3, non-load (xmit in fx2/b)

input  [63:0]	fad_rs1_fx1;		// Source register data bit
input  [63:0]	fad_rs2_fx1;		// - available at output of flop
input           fad_i_parity_2e_fx1;    // partial ECC check (parity portion), rs2 even
input           fad_i_parity_2o_fx1;    // partial ECC check (parity portion), rs2 odd
input           fad_i_parity_1e_fx1;    // partial ECC check (parity portion), rs1 even
input           fad_i_parity_1o_fx1;    // partial ECC check (parity portion), rs1 odd

input  [13:0]	frf_r1_ecc_e;		// Source register ECC bit 
input  [13:0]	frf_r2_ecc_e;		// - NOTE: E stage signal
					// - need to be flopped to Fx1
// *** Global Outputs ***

output          fgu_pdist_beat2_fx1;
output  [5:0]	fgu_ecc_addr_fx2;      	// FRF cecc/uecc address (6-bit reg number format)
output [13:0]   fgu_ecc_check_fx2;      // FRF ECC check bits {even[6:0],odd[6:0]}
output 		fgu_cecc_fx2;		// Flag: detected correctable ECC error
output 		fec_cecc_fx2;		// Flag: detected correctable ECC error
output 		fgu_uecc_fx2;		// Flag: detected uncorrectable ECC error
output 		fec_uecc_fx2;		// Flag: detected uncorrectable ECC error
output          fgu_fst_ecc_error_fx2;  // store float FRF ECC correctable/uncorrectable error

output          fgu_mbi_frf_fail;       // MBIST

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop   = 1'b0;
assign siclk  = spc_aclk;
assign soclk  = spc_bclk;
assign se     = tcu_scan_en;
// end scan


fgu_fec_ctl_l1clkhdr_ctl_macro clkgen_coreon (
  .l2clk(l2clk),
  .l1en (coreon_clken),
  .l1clk(l1clk_pm2),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fec_ctl_l1clkhdr_ctl_macro clkgen_main (
  .l2clk(l2clk),
  .l1en (main_clken),
  .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fec_ctl_l1clkhdr_ctl_macro clkgen_main_sco (
  .l2clk(l2clk),
  .l1en (main_clken),
  .se	(tcu_se_scancollar_out),
  .l1clk(l1clk_sc),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fec_ctl_spare_ctl_macro__num_2 spares  (  // spares: 13 gates + 1 flop for each "num"
  .scan_in(spares_scanin),
  .scan_out(spares_scanout),
  .l1clk(l1clk_pm2),
  .siclk(siclk),
  .soclk(soclk)
  );


/////////////////////////////////////////////////////////////////////////////
// ECC Error Dectection Logic
//-----------------------------
// - Regenerate ECC [5:0] and compare against retrived ECC
// - Check ECC [6] with parity
// - Outputs the result of the detection:
//   - ne: no error - either no valid data to check, 
//                    or ECC [6:0] all matched 
//   - ce: correctable error
//                  - parity is 1, so an odd number of bits flipped,
//                    and ECC data is valid and regenerated ECC did not match
//   - ue: uncorrectable error
//                  - parity is 0, so an even number of bits flipped,
//                    and ECC data is valid and regenerated ECC did not match
//                  - implies more than one bit was corrupted
//
//       1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17  18  19
//      P0  P1  d0  P2  d1  d2  d3  P3  d4  d5  d6  d7  d8  d9 d10  P4 d11 d12 d13 
// p0 =  o   	 x       x       x       x       x       x       x       x       x
// p1 =      o   x           x   x           x   x           x   x           x   x
// p2 =     	     o   x   x   x      	     x   x   x   x     	          
// p3 =     	          	     o   x   x   x   x   x   x   x      	  
// p4 =     	          	          			     o   x   x   x
// p5 =     	          	          			         	  
// p6 =          x       x   x           x   x       x           x       x   x    
// --------------------------------------------------------------------------------
// Total 1   1   3   1   3   3   3   1   3   3   3   3   3   3   5   1   3   3   3
//   
//      20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38
//     d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25  P5 d26 d27 d28 d29 d30 d31 
// p0=       x       x       x       x       x       x       x       x       x    
// p1=           x   x           x   x           x   x           x   x           x
// p2=   x   x   x   x                   x   x   x   x                   x   x   x
// p3=                   x   x   x   x   x   x   x   x
// p4=   x   x   x   x   x   x   x   x   x   x   x   x
// p5=                                                   o   x   x   x   x   x   x
// p6=   x           x   x           x       x   x           x   x       x   
// --------------------------------------------------------------------------------
// Total 3   3   3   5   3   3   3   5   3   5   5   5   1   3   3   3   3   3   3
//
/////////////////////////////////////////////////////////////////////////////

// Calculating valid ECCs to check
// - (reading out of frf rs1 even word) & (rs1 is not bypass data)
// - (reading out of frf rs1 odd  word) & (rs1 is not bypass data)
// - (reading out of frf rs2 even word) & (rs2 is not bypass data)
// - (reading out of frf rs2 odd  word) & (rs2 is not bypass data)
// ---------------------------------------------------
assign rs1e_ecc_valid_fx1 = fac_r1_vld_fx1[1] & ~fad_r1_byp_hit_fx1;
assign rs1o_ecc_valid_fx1 = fac_r1_vld_fx1[0] & ~fad_r1_byp_hit_fx1;
assign rs2e_ecc_valid_fx1 = fac_r2_vld_fx1[1] & ~fad_r2_byp_hit_fx1;
assign rs2o_ecc_valid_fx1 = fac_r2_vld_fx1[0] & ~fad_r2_byp_hit_fx1;

fgu_fec_ctl_msff_ctl_macro__width_28  frf_rs1_check_flops_e_fx1  (
 .scan_in(frf_rs1_check_flops_e_fx1_scanin),
 .scan_out(frf_rs1_check_flops_e_fx1_scanout),
 .l1clk(l1clk_pm1),
 .din  ({r1_ecc_check_fx1[13:0], r2_ecc_check_fx1[13:0]}),
 .dout ({r1_ecc_check_fx2[13:0], r2_ecc_check_fx2[13:0]}),
  .siclk(siclk),
  .soclk(soclk));


fgu_fec_ctl_msff_ctl_macro__width_14  frf_rs1_ecc_flops_e_fx1  (
 .scan_in(frf_rs1_ecc_flops_e_fx1_scanin),
 .scan_out(frf_rs1_ecc_flops_e_fx1_scanout),
 .l1clk(l1clk_sc),
 .din  (frf_r1_ecc_e  [13:0]),
 .dout (fec_r1_ecc_fx1[13:0]),
  .siclk(siclk),
  .soclk(soclk));

assign pre_frf_fail =
  mbist_frf_read_en_3f &
  (~fad_mbist_cmp64_fx1 |
   ({fec_mbist_wdata_3f[6:0], fec_mbist_wdata_3f[6:0]} != fec_r1_ecc_fx1[13:0]));

fgu_fec_ctl_msff_ctl_macro__width_14  frf_rs2_ecc_flops_e_fx1  (
 .scan_in(frf_rs2_ecc_flops_e_fx1_scanin),
 .scan_out(frf_rs2_ecc_flops_e_fx1_scanout),
 .l1clk(l1clk_sc),
 .din  (frf_r2_ecc_e  [13:0] ),
 .dout (    r2_ecc_fx1[13:0] ),
  .siclk(siclk),
  .soclk(soclk));


// Rename nets for shorter expressions
// -----------------------------------------
assign d1e[31:0] = fad_rs1_fx1[63:32];
assign p1e[ 6:0] = fec_r1_ecc_fx1[13:7];

assign d1o[31:0] = fad_rs1_fx1[31:0];
assign p1o[ 6:0] = fec_r1_ecc_fx1[ 6:0];

assign d2e[31:0] = fad_rs2_fx1[63:32];
assign p2e[ 6:0] = r2_ecc_fx1[13:7];

assign d2o[31:0] = fad_rs2_fx1[31:0];
assign p2o[ 6:0] = r2_ecc_fx1[ 6:0];


// Overall error detected flags
// -----------------------------------------

// Priority: (1) rs1_ue (2) rs1_ce (3) rs2_ue (4) rs2_ce (5) rs3_ue (6) rs3_ce

assign rs1_ue_or_ce_fx1 = ~(rs1e_ne & rs1o_ne);

assign detect_ue_fx1 =
  (                    (rs1e_ue | rs1o_ue)) |
  (~rs1_ue_or_ce_fx1 & (rs2e_ue | rs2o_ue)) ;

assign detect_ce_fx1 =
  (                    (rs1e_ce | rs1o_ce) & ~detect_ue_fx1) |
  (~rs1_ue_or_ce_fx1 & (rs2e_ce | rs2o_ce) & ~detect_ue_fx1) ;

// Note: lsu doesn't care about qual w/ flush, store data is rs2 only, lsu doesn't care whether error is cecc or uecc
assign fst_ecc_error_fx1 =
  fac_ecc_trap_en_fx1   &
  fpc_frf_store_vld_fx1 &
  (rs2e_ue | rs2o_ue | rs2e_ce | rs2o_ce);

fgu_fec_ctl_msff_ctl_macro__width_76  addr_flops  (
 .scan_in(addr_flops_scanin),
 .scan_out(addr_flops_scanout),
 .l1clk(l1clk_pm1),
 .din  ({fac_frf_r1_addr_e[4:0],
                 r2_addr_e[4:0],
                 r1_32b_e,
                 r2_32b_e,
                 r1_odd32b_e,
                 r2_odd32b_e,
         fac_fgx_pdist_fx1,
         fac_dec_valid_fx1,
         dec_flush_f1,
	 dec_flush_f2,
         fpc_frf_store_vld_fx1,
         lsu_asi_error_inject[31],
         lsu_asi_error_inject[24],
         lsu_asi_error_inject[6:0],
         fac_ecc_trap_en_fx1,
         detect_ce_fx2,
         detect_ue_fx2,
         tlu_flush_fgu_b,
         fgu_pdist_beat2_fx1,
         mbi_frf_read_en,
         mbi_wdata[7:0],
         mbi_run,
         mbist_frf_read_en_1f,
         mbist_frf_read_en_2f,
         fec_mbist_wdata_1f[7:0],
             mbist_wdata_2f[7:0],
         pre_frf_fail,
             fst_ecc_error_fx1,
         rs1_ue_or_ce_fx1,
         r1_expanded_addr_fx1[5:0],
         r2_expanded_addr_fx1[5:0]}),
 .dout ({        r1_addr_fx1[4:0],
                 r2_addr_fx1[4:0],
                 r1_32b_fx1,
                 r2_32b_fx1,
                 r1_odd32b_fx1,
                 r2_odd32b_fx1,
             fgx_pdist_fx2,
         dec_valid_fx2,
         dec_flush_fx2,
	 dec_flush_fx3,
             frf_store_vld_fx2,
             ecc_mask_global_en,
             ecc_mask_frf_en,
             ecc_mask_data[6:0],
             ecc_trap_en_fx2,
         detect_ce_fx3,
         detect_ue_fx3,
         tlu_flush_fgu_fx3,
         i_pdist_beat2_fx2,
         mbist_frf_read_en_1f,
         fec_mbist_wdata_1f[7:0],
         mbist_run_1f,
         mbist_frf_read_en_2f,
         mbist_frf_read_en_3f,
             mbist_wdata_2f[7:0],
         fec_mbist_wdata_3f[7:0],
         fgu_mbi_frf_fail,
         fgu_fst_ecc_error_fx2,
         rs1_ue_or_ce_fx2,
         r1_expanded_addr_fx2[5:0],
         r2_expanded_addr_fx2[5:0]}),
  .siclk(siclk),
  .soclk(soclk));

fgu_fec_ctl_msff_ctl_macro__width_9  addr_flops2  (
 .scan_in(addr_flops2_scanin),
 .scan_out(addr_flops2_scanout),
 .l1clk(l1clk_pm2),
 .din  ({dec_frf_r2_addr_d[4:0],  // requires free running clk or dec_fgu_decode_d en
         dec_frf_r1_32b_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_r2_32b_d,        // requires free running clk or dec_fgu_decode_d en
         dec_frf_r1_odd32b_d,     // requires free running clk or dec_fgu_decode_d en
         dec_frf_r2_odd32b_d}),   // requires free running clk or dec_fgu_decode_d en
 .dout ({        r2_addr_e[4:0],
                 r1_32b_e,
                 r2_32b_e,
                 r1_odd32b_e,
                 r2_odd32b_e}),
  .siclk(siclk),
  .soclk(soclk));

assign r1_expanded_addr_fx1[5:0] =  // expand addr to 6-bit reg number
  ({6{ r1_32b_fx1}} & {1'b0, r1_addr_fx1[3:0], r1_odd32b_fx1}) |
  ({6{~r1_32b_fx1}} & {      r1_addr_fx1[4:0], 1'b0         }) ;

assign r2_expanded_addr_fx1[5:0] =  // expand addr to 6-bit reg number
  ({6{ r2_32b_fx1}} & {1'b0, r2_addr_fx1[3:0], r2_odd32b_fx1}) |
  ({6{~r2_32b_fx1}} & {      r2_addr_fx1[4:0], 1'b0         }) ;

assign r1_ecc_check_fx1[13:0] = {parity_1e, q1e[5:0], parity_1o, q1o[5:0]};
assign r2_ecc_check_fx1[13:0] = {parity_2e, q2e[5:0], parity_2o, q2o[5:0]};

assign fgu_pdist_beat2_fx1 =
  dec_valid_fx2 &
  fgx_pdist_fx2 &
  ~dec_flush_fx2;

fgu_fec_ctl_msff_ctl_macro__width_2  ce_ue_fec_flops_fx1_fx2  (
 .scan_in(ce_ue_fec_flops_fx1_fx2_scanin),
 .scan_out(ce_ue_fec_flops_fx1_fx2_scanout),
 .l1clk(l1clk_pm1),
 .din  ({detect_ce_fx1, detect_ue_fx1}),
 .dout ({detect_ce_fx2, detect_ue_fx2}),
  .siclk(siclk),
  .soclk(soclk));

assign pdist_beat2_fx2 = i_pdist_beat2_fx2 & ~tlu_flush_fgu_fx3 & ~dec_flush_fx3;

assign frf_rd_vld_fx2 = (dec_valid_fx2 | frf_store_vld_fx2) & ~dec_flush_fx2;  // this eq. prevents FRF_ECC ASI diagnositc read from asserting fgu_{u,c}ecc_fx2

// For single source (or no source) fgu ops that read frf
// ensure that unneeded frf read port isn't enabled by DEC
// Note:
// dec_frf_store_d, dec_fsr_store_d   have rs2 only
// 0in custom -fire (fpc_frf_store_vld_fx1 & (|fac_r1_vld_fx1[1:0])) -message "Invalid FRF rs1 read enable during store"

assign fgu_cecc_fx2 =
  ecc_trap_en_fx2 &
  ((~pdist_beat2_fx2 & detect_ce_fx2 &  frf_rd_vld_fx2                 ) |
   ( pdist_beat2_fx2 & detect_ce_fx2 & ~(detect_ce_fx3 | detect_ue_fx3))  );  // pdist 2nd beat

assign fec_cecc_fx2 = fgu_cecc_fx2;  // for timing, isolate internal fgu sinks from external sinks

assign fgu_uecc_fx2 =
  ecc_trap_en_fx2 &
  ((~pdist_beat2_fx2 & detect_ue_fx2 &  frf_rd_vld_fx2                 ) |
   ( pdist_beat2_fx2 & detect_ue_fx2 & ~(detect_ce_fx3 | detect_ue_fx3))  );  // pdist 2nd beat

assign fec_uecc_fx2 = fgu_uecc_fx2;  // for timing, isolate internal fgu sinks from external sinks

assign fgu_ecc_addr_fx2[5:0] =
  ({6{ rs1_ue_or_ce_fx2}} & r1_expanded_addr_fx2[5:0]) |
  ({6{~rs1_ue_or_ce_fx2}} & r2_expanded_addr_fx2[5:0]) ;

assign fgu_ecc_check_fx2[13:0] =
  ({14{ rs1_ue_or_ce_fx2}} & r1_ecc_check_fx2[13:0]) |
  ({14{~rs1_ue_or_ce_fx2}} & r2_ecc_check_fx2[13:0]) ;

// 0in one_hot -var {rs1e_ne,rs1e_ce,rs1e_ue}
// 0in one_hot -var {rs1o_ne,rs1o_ce,rs1o_ue}
// 0in bits_on -max 1 -var {rs2e_ce,rs2e_ue}
// 0in bits_on -max 1 -var {rs2o_ce,rs2o_ue}

// Detection for RS1 even part [63:32]
// -----------------------------------

assign rs1e_ne = ~rs1e_ecc_valid_fx1 |
                     ~(parity_1e | q1e[5] | q1e[4] | q1e[3] | q1e[2] | q1e[1] | q1e[0]);

assign rs1e_ce = rs1e_ecc_valid_fx1 & parity_1e;

assign rs1e_ue = rs1e_ecc_valid_fx1 & ~parity_1e & 
	   	      (q1e[5] | q1e[4] | q1e[3] | q1e[2] | q1e[1] | q1e[0]);

assign q1e[0] = d1e[0]  ^ d1e[1]  ^ d1e[3]  ^ d1e[4]  ^ d1e[6]  
                        ^ d1e[8]  ^ d1e[10] ^ d1e[11] ^ d1e[13] ^ d1e[15]
                        ^ d1e[17] ^ d1e[19] ^ d1e[21] ^ d1e[23] ^ d1e[25] 
                        ^ d1e[26] ^ d1e[28] ^ d1e[30] ^ p1e[0];

assign q1e[1] = d1e[0]  ^ d1e[2]  ^ d1e[3]  ^ d1e[5]  ^ d1e[6] 
                        ^ d1e[9]  ^ d1e[10] ^ d1e[12] ^ d1e[13] ^ d1e[16]
                        ^ d1e[17] ^ d1e[20] ^ d1e[21] ^ d1e[24] ^ d1e[25]
                        ^ d1e[27] ^ d1e[28] ^ d1e[31] ^ p1e[1];

assign q1e[2] = d1e[1]  ^ d1e[2]  ^ d1e[3]  ^ d1e[7]  ^ d1e[8] 
                        ^ d1e[9]  ^ d1e[10] ^ d1e[14] ^ d1e[15] ^ d1e[16]
                        ^ d1e[17] ^ d1e[22] ^ d1e[23] ^ d1e[24] ^ d1e[25]
                        ^ d1e[29] ^ d1e[30] ^ d1e[31] ^ p1e[2];

assign q1e[3] = d1e[4]  ^ d1e[5]  ^ d1e[6]  ^ d1e[7]  ^ d1e[8]  
                        ^ d1e[9]  ^ d1e[10] ^ d1e[18] ^ d1e[19] ^ d1e[20]
                        ^ d1e[21] ^ d1e[22] ^ d1e[23] ^ d1e[24] ^ d1e[25]
                        ^ p1e[3];

assign q1e[4] = d1e[11] ^ d1e[12] ^ d1e[13] ^ d1e[14] ^ d1e[15] 
                        ^ d1e[16] ^ d1e[17] ^ d1e[18] ^ d1e[19] ^ d1e[20]
                        ^ d1e[21] ^ d1e[22] ^ d1e[23] ^ d1e[24] ^ d1e[25]
                        ^ p1e[4];

assign q1e[5] = d1e[26] ^ d1e[27] ^ d1e[28] ^ d1e[29] ^ d1e[30] ^ d1e[31]
                        ^ p1e[5];

assign parity_1e = fad_i_parity_1e_fx1 ^ p1e[0] ^ p1e[1] ^ p1e[2] ^ p1e[3] ^ p1e[4] ^ p1e[5] ^ p1e[6];


// Detection for RS1 odd part [31:00]
// -----------------------------------

assign rs1o_ne = ~rs1o_ecc_valid_fx1 |
                     ~(parity_1o | q1o[5] | q1o[4] | q1o[3] | q1o[2] | q1o[1] | q1o[0]);

assign rs1o_ce = rs1o_ecc_valid_fx1 & parity_1o;

assign rs1o_ue = rs1o_ecc_valid_fx1 & ~parity_1o & 
		      (q1o[5] | q1o[4] | q1o[3] | q1o[2] | q1o[1] | q1o[0]);

assign q1o[0] = d1o[0]  ^ d1o[1]  ^ d1o[3]  ^ d1o[4]  ^ d1o[6]  
                        ^ d1o[8]  ^ d1o[10] ^ d1o[11] ^ d1o[13] ^ d1o[15]
                        ^ d1o[17] ^ d1o[19] ^ d1o[21] ^ d1o[23] ^ d1o[25] 
                        ^ d1o[26] ^ d1o[28] ^ d1o[30] ^ p1o[0];

assign q1o[1] = d1o[0]  ^ d1o[2]  ^ d1o[3]  ^ d1o[5]  ^ d1o[6] 
                        ^ d1o[9]  ^ d1o[10] ^ d1o[12] ^ d1o[13] ^ d1o[16]
                        ^ d1o[17] ^ d1o[20] ^ d1o[21] ^ d1o[24] ^ d1o[25]
                        ^ d1o[27] ^ d1o[28] ^ d1o[31] ^ p1o[1];

assign q1o[2] = d1o[1]  ^ d1o[2]  ^ d1o[3]  ^ d1o[7]  ^ d1o[8] 
                        ^ d1o[9]  ^ d1o[10] ^ d1o[14] ^ d1o[15] ^ d1o[16]
                        ^ d1o[17] ^ d1o[22] ^ d1o[23] ^ d1o[24] ^ d1o[25]
                        ^ d1o[29] ^ d1o[30] ^ d1o[31] ^ p1o[2];

assign q1o[3] = d1o[4]  ^ d1o[5]  ^ d1o[6]  ^ d1o[7]  ^ d1o[8]  
                        ^ d1o[9]  ^ d1o[10] ^ d1o[18] ^ d1o[19] ^ d1o[20]
                        ^ d1o[21] ^ d1o[22] ^ d1o[23] ^ d1o[24] ^ d1o[25]
                        ^ p1o[3];

assign q1o[4] = d1o[11] ^ d1o[12] ^ d1o[13] ^ d1o[14] ^ d1o[15] 
                        ^ d1o[16] ^ d1o[17] ^ d1o[18] ^ d1o[19] ^ d1o[20]
                        ^ d1o[21] ^ d1o[22] ^ d1o[23] ^ d1o[24] ^ d1o[25]
                        ^ p1o[4];

assign q1o[5] = d1o[26] ^ d1o[27] ^ d1o[28] ^ d1o[29] ^ d1o[30] ^ d1o[31]
                        ^ p1o[5];

assign parity_1o = fad_i_parity_1o_fx1 ^ p1o[0] ^ p1o[1] ^ p1o[2] ^ p1o[3] ^ p1o[4] ^ p1o[5] ^ p1o[6];


// Detection for RS2 even part [63:32]
// -----------------------------------

assign rs2e_ce = rs2e_ecc_valid_fx1 & parity_2e;

assign rs2e_ue = rs2e_ecc_valid_fx1 & ~parity_2e & 
	   	      (q2e[5] | q2e[4] | q2e[3] | q2e[2] | q2e[1] | q2e[0]);

assign q2e[0] = d2e[0]  ^ d2e[1]  ^ d2e[3]  ^ d2e[4]  ^ d2e[6]  
                        ^ d2e[8]  ^ d2e[10] ^ d2e[11] ^ d2e[13] ^ d2e[15]
                        ^ d2e[17] ^ d2e[19] ^ d2e[21] ^ d2e[23] ^ d2e[25] 
                        ^ d2e[26] ^ d2e[28] ^ d2e[30] ^ p2e[0];

assign q2e[1] = d2e[0]  ^ d2e[2]  ^ d2e[3]  ^ d2e[5]  ^ d2e[6] 
                        ^ d2e[9]  ^ d2e[10] ^ d2e[12] ^ d2e[13] ^ d2e[16]
                        ^ d2e[17] ^ d2e[20] ^ d2e[21] ^ d2e[24] ^ d2e[25]
                        ^ d2e[27] ^ d2e[28] ^ d2e[31] ^ p2e[1];

assign q2e[2] = d2e[1]  ^ d2e[2]  ^ d2e[3]  ^ d2e[7]  ^ d2e[8] 
                        ^ d2e[9]  ^ d2e[10] ^ d2e[14] ^ d2e[15] ^ d2e[16]
                        ^ d2e[17] ^ d2e[22] ^ d2e[23] ^ d2e[24] ^ d2e[25]
                        ^ d2e[29] ^ d2e[30] ^ d2e[31] ^ p2e[2];

assign q2e[3] = d2e[4]  ^ d2e[5]  ^ d2e[6]  ^ d2e[7]  ^ d2e[8]  
                        ^ d2e[9]  ^ d2e[10] ^ d2e[18] ^ d2e[19] ^ d2e[20]
                        ^ d2e[21] ^ d2e[22] ^ d2e[23] ^ d2e[24] ^ d2e[25]
                        ^ p2e[3];

assign q2e[4] = d2e[11] ^ d2e[12] ^ d2e[13] ^ d2e[14] ^ d2e[15] 
                        ^ d2e[16] ^ d2e[17] ^ d2e[18] ^ d2e[19] ^ d2e[20]
                        ^ d2e[21] ^ d2e[22] ^ d2e[23] ^ d2e[24] ^ d2e[25]
                        ^ p2e[4];

assign q2e[5] = d2e[26] ^ d2e[27] ^ d2e[28] ^ d2e[29] ^ d2e[30] ^ d2e[31]
                        ^ p2e[5];

assign parity_2e = fad_i_parity_2e_fx1 ^ p2e[0] ^ p2e[1] ^ p2e[2] ^ p2e[3] ^ p2e[4] ^ p2e[5] ^ p2e[6];


// Detection for RS2 odd part [31:00]
// -----------------------------------

assign rs2o_ce = rs2o_ecc_valid_fx1 & parity_2o;

assign rs2o_ue = rs2o_ecc_valid_fx1 & ~parity_2o & 
		      (q2o[5] | q2o[4] | q2o[3] | q2o[2] | q2o[1] | q2o[0]);

assign q2o[0] = d2o[0]  ^ d2o[1]  ^ d2o[3]  ^ d2o[4]  ^ d2o[6]  
                        ^ d2o[8]  ^ d2o[10] ^ d2o[11] ^ d2o[13] ^ d2o[15]
                        ^ d2o[17] ^ d2o[19] ^ d2o[21] ^ d2o[23] ^ d2o[25] 
                        ^ d2o[26] ^ d2o[28] ^ d2o[30] ^ p2o[0];

assign q2o[1] = d2o[0]  ^ d2o[2]  ^ d2o[3]  ^ d2o[5]  ^ d2o[6] 
                        ^ d2o[9]  ^ d2o[10] ^ d2o[12] ^ d2o[13] ^ d2o[16]
                        ^ d2o[17] ^ d2o[20] ^ d2o[21] ^ d2o[24] ^ d2o[25]
                        ^ d2o[27] ^ d2o[28] ^ d2o[31] ^ p2o[1];

assign q2o[2] = d2o[1]  ^ d2o[2]  ^ d2o[3]  ^ d2o[7]  ^ d2o[8] 
                        ^ d2o[9]  ^ d2o[10] ^ d2o[14] ^ d2o[15] ^ d2o[16]
                        ^ d2o[17] ^ d2o[22] ^ d2o[23] ^ d2o[24] ^ d2o[25]
                        ^ d2o[29] ^ d2o[30] ^ d2o[31] ^ p2o[2];

assign q2o[3] = d2o[4]  ^ d2o[5]  ^ d2o[6]  ^ d2o[7]  ^ d2o[8]  
                        ^ d2o[9]  ^ d2o[10] ^ d2o[18] ^ d2o[19] ^ d2o[20]
                        ^ d2o[21] ^ d2o[22] ^ d2o[23] ^ d2o[24] ^ d2o[25]
                        ^ p2o[3];

assign q2o[4] = d2o[11] ^ d2o[12] ^ d2o[13] ^ d2o[14] ^ d2o[15] 
                        ^ d2o[16] ^ d2o[17] ^ d2o[18] ^ d2o[19] ^ d2o[20]
                        ^ d2o[21] ^ d2o[22] ^ d2o[23] ^ d2o[24] ^ d2o[25]
                        ^ p2o[4];

assign q2o[5] = d2o[26] ^ d2o[27] ^ d2o[28] ^ d2o[29] ^ d2o[30] ^ d2o[31]
                        ^ p2o[5];

assign parity_2o = fad_i_parity_2o_fx1 ^ p2o[0] ^ p2o[1] ^ p2o[2] ^ p2o[3] ^ p2o[4] ^ p2o[5] ^ p2o[6];


/////////////////////////////////////////////////////////////////////////////
//***************************************************************************
//***** ECC Generation ******************************************************
//***************************************************************************
/////////////////////////////////////////////////////////////////////////////
// W2 ECC Generation
//-----------------------------------
// - Encode the two 32-bit write data into two 7-bit Error Correction Code 
// - Trying to do encoding in one phase:
//   - FRF write happens in phase 2 of write stage
//   - If ECC takes longer than phase 1 of write stage, it could spill 
//     over to phase 2 of the stage before write.
// - W1 ECC generation is performed in FAD
//
/////////////////////////////////////////////////////////////////////////////

assign fec_w1_ecc_inject_fb[6:0] = ({7{ecc_mask_global_en & ecc_mask_frf_en}} & ecc_mask_data[6:0]);

// W2 port even word [63:32] ECC Generation
// ========================================
assign w2e[31:0] = fad_nombi_w2_result_fw[63:32];
assign fec_w2_synd_fw[13:7] =
  (s2e[6:0] & {7{~mbist_run_1f}}) ^
  (({7{ecc_mask_global_en & ecc_mask_frf_en & ~mbist_run_1f}} & ecc_mask_data[6:0]     ) |
   ({7{                                        mbist_run_1f}} & fec_mbist_wdata_1f[6:0])  );

assign s2e[0] = w2e[0]  ^ w2e[1]  ^ w2e[3]  ^ w2e[4]  ^ w2e[6]  
			  ^ w2e[8]  ^ w2e[10] ^ w2e[11] ^ w2e[13] ^ w2e[15]
			  ^ w2e[17] ^ w2e[19] ^ w2e[21] ^ w2e[23] ^ w2e[25] 
			  ^ w2e[26] ^ w2e[28] ^ w2e[30];

assign s2e[1] = w2e[0]  ^ w2e[2]  ^ w2e[3]  ^ w2e[5]  ^ w2e[6] 
			  ^ w2e[9]  ^ w2e[10] ^ w2e[12] ^ w2e[13] ^ w2e[16]
			  ^ w2e[17] ^ w2e[20] ^ w2e[21] ^ w2e[24] ^ w2e[25]
			  ^ w2e[27] ^ w2e[28] ^ w2e[31];

assign s2e[2] = w2e[1]  ^ w2e[2]  ^ w2e[3]  ^ w2e[7]  ^ w2e[8] 
			  ^ w2e[9]  ^ w2e[10] ^ w2e[14] ^ w2e[15] ^ w2e[16]
			  ^ w2e[17] ^ w2e[22] ^ w2e[23] ^ w2e[24] ^ w2e[25]
			  ^ w2e[29] ^ w2e[30] ^ w2e[31];

assign s2e[3] = w2e[4]  ^ w2e[5]  ^ w2e[6]  ^ w2e[7]  ^ w2e[8]  
			  ^ w2e[9]  ^ w2e[10] ^ w2e[18] ^ w2e[19] ^ w2e[20]
			  ^ w2e[21] ^ w2e[22] ^ w2e[23] ^ w2e[24] ^ w2e[25];

assign s2e[4] = w2e[11] ^ w2e[12] ^ w2e[13] ^ w2e[14] ^ w2e[15] 
			  ^ w2e[16] ^ w2e[17] ^ w2e[18] ^ w2e[19] ^ w2e[20]
			  ^ w2e[21] ^ w2e[22] ^ w2e[23] ^ w2e[24] ^ w2e[25];

assign s2e[5] = w2e[26] ^ w2e[27] ^ w2e[28] ^ w2e[29] ^ w2e[30] ^ w2e[31];

assign s2e[6] = w2e[0]  ^ w2e[1]  ^ w2e[2]  ^ w2e[4]  ^ w2e[5] 
			  ^ w2e[7]  ^ w2e[10] ^ w2e[11] ^ w2e[12] ^ w2e[14] 
			  ^ w2e[17] ^ w2e[18] ^ w2e[21] ^ w2e[23] ^ w2e[24] 
			  ^ w2e[26] ^ w2e[27] ^ w2e[29];


// W2 port odd word [31:00] ECC Generation
// ========================================
assign w2o[31:0] = fad_nombi_w2_result_fw[31:0];
assign fec_w2_synd_fw[6:0] =
  (s2o[6:0] & {7{~mbist_run_1f}}) ^
  (({7{ecc_mask_global_en & ecc_mask_frf_en & ~mbist_run_1f}} & ecc_mask_data[6:0]     ) |
   ({7{                                        mbist_run_1f}} & fec_mbist_wdata_1f[6:0])  );

assign s2o[0] = w2o[0]  ^ w2o[1]  ^ w2o[3]  ^ w2o[4]  ^ w2o[6]  
			  ^ w2o[8]  ^ w2o[10] ^ w2o[11] ^ w2o[13] ^ w2o[15]
			  ^ w2o[17] ^ w2o[19] ^ w2o[21] ^ w2o[23] ^ w2o[25] 
			  ^ w2o[26] ^ w2o[28] ^ w2o[30];

assign s2o[1] = w2o[0]  ^ w2o[2]  ^ w2o[3]  ^ w2o[5]  ^ w2o[6] 
			  ^ w2o[9]  ^ w2o[10] ^ w2o[12] ^ w2o[13] ^ w2o[16]
			  ^ w2o[17] ^ w2o[20] ^ w2o[21] ^ w2o[24] ^ w2o[25]
			  ^ w2o[27] ^ w2o[28] ^ w2o[31];

assign s2o[2] = w2o[1]  ^ w2o[2]  ^ w2o[3]  ^ w2o[7]  ^ w2o[8] 
			  ^ w2o[9]  ^ w2o[10] ^ w2o[14] ^ w2o[15] ^ w2o[16]
			  ^ w2o[17] ^ w2o[22] ^ w2o[23] ^ w2o[24] ^ w2o[25]
			  ^ w2o[29] ^ w2o[30] ^ w2o[31];

assign s2o[3] = w2o[4]  ^ w2o[5]  ^ w2o[6]  ^ w2o[7]  ^ w2o[8]  
			  ^ w2o[9]  ^ w2o[10] ^ w2o[18] ^ w2o[19] ^ w2o[20]
			  ^ w2o[21] ^ w2o[22] ^ w2o[23] ^ w2o[24] ^ w2o[25];

assign s2o[4] = w2o[11] ^ w2o[12] ^ w2o[13] ^ w2o[14] ^ w2o[15] 
			  ^ w2o[16] ^ w2o[17] ^ w2o[18] ^ w2o[19] ^ w2o[20]
			  ^ w2o[21] ^ w2o[22] ^ w2o[23] ^ w2o[24] ^ w2o[25];

assign s2o[5] = w2o[26] ^ w2o[27] ^ w2o[28] ^ w2o[29] ^ w2o[30] ^ w2o[31];

assign s2o[6] = w2o[0]  ^ w2o[1]  ^ w2o[2]  ^ w2o[4]  ^ w2o[5] 
			  ^ w2o[7]  ^ w2o[10] ^ w2o[11] ^ w2o[12] ^ w2o[14] 
			  ^ w2o[17] ^ w2o[18] ^ w2o[21] ^ w2o[23] ^ w2o[24] 
			  ^ w2o[26] ^ w2o[27] ^ w2o[29];


supply0 vss;
supply1 vdd;
// fixscan start:
assign spares_scanin             = scan_in                  ;
assign frf_rs1_check_flops_e_fx1_scanin = spares_scanout           ;
assign frf_rs1_ecc_flops_e_fx1_scanin = frf_rs1_check_flops_e_fx1_scanout;
assign frf_rs2_ecc_flops_e_fx1_scanin = frf_rs1_ecc_flops_e_fx1_scanout;
assign addr_flops_scanin         = frf_rs2_ecc_flops_e_fx1_scanout;
assign addr_flops2_scanin        = addr_flops_scanout       ;
assign ce_ue_fec_flops_fx1_fx2_scanin = addr_flops2_scanout      ;
assign scan_out                  = ce_ue_fec_flops_fx1_fx2_scanout;
// fixscan end:
endmodule  // fgu_fec_ctl


// any PARAMS parms go into naming of macro

module fgu_fec_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module fgu_fec_ctl_spare_ctl_macro__num_2 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));
assign scan_out = so_1;


endmodule


// any PARAMS parms go into naming of macro

module fgu_fec_ctl_msff_ctl_macro__width_28 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [27:0] fdin;
wire [26:0] so;

  input [27:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [27:0] dout;
  output scan_out;
assign fdin[27:0] = din[27:0];


dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fec_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fec_ctl_msff_ctl_macro__width_76 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [75:0] fdin;
wire [74:0] so;

  input [75:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [75:0] dout;
  output scan_out;
assign fdin[75:0] = din[75:0];


dff #(76)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[75:0]),
.si({scan_in,so[74:0]}),
.so({so[74:0],scan_out}),
.q(dout[75:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fec_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fec_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fgd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fgd_dp (
  fad_rs1_fmt_fx1, 
  fad_rs2_fmt_fx1, 
  fgd_rngl_cdbus_3f, 
  fgd_result_fx5, 
  vis_clken, 
  coreon_clken, 
  fac_fgx_abs_fx2, 
  fac_fgx_neg_fx2, 
  fac_fgx_logical_fx2, 
  fac_fgx_expand_fx2, 
  fac_fgx_merge_fx2, 
  fac_fgx_align_fx2, 
  fac_fgx_shuffle_fx2, 
  fac_fgx_pack16_fx2, 
  fac_fgx_pack32_fx2, 
  fac_fgx_packfix_fx2, 
  fac_fgx_pdist_fx1, 
  fac_fgx_popc_fx2, 
  fac_fgx_pack_sel_fx2, 
  fac_opf_fx2, 
  fac_gsr_asr_tid_fx2, 
  fac_tid_fx2, 
  fac_rng_fprs, 
  fac_rng_rd_fprs_4f, 
  fac_rng_rd_gsr_4f, 
  fec_r1_ecc_fx1, 
  fac_rng_rd_ecc_4f, 
  fac_rng_rd_or_wr_3f, 
  asi_clken, 
  fgd_gsr_asr_mask_fx4_b31, 
  fpc_gsr0_mask_sel_fx3, 
  fpc_gsr1_mask_sel_fx3, 
  fpc_gsr2_mask_sel_fx3, 
  fpc_gsr3_mask_sel_fx3, 
  fpc_gsr4_mask_sel_fx3, 
  fpc_gsr5_mask_sel_fx3, 
  fpc_gsr6_mask_sel_fx3, 
  fpc_gsr7_mask_sel_fx3, 
  fpc_gsr_scale_fx4, 
  fpc_gsr_align_fx4, 
  fpc_gsr_asr_11bits_fx4, 
  exu_fgu_gsr_m, 
  l2clk, 
  scan_in, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lb_scan_en_wmr, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_scan_en, 
  scan_out, 
  wmr_scan_out, 
  in_rngl_cdbus);
wire stop;
wire test;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire fx2_rs1_scanin;
wire fx2_rs1_scanout;
wire [63:0] rs1_fx2;
wire fx2_rs2_scanin;
wire fx2_rs2_scanout;
wire [63:0] rs2_fx2;
wire fx2_gsr_scanin;
wire fx2_gsr_scanout;
wire [31:0] gsr_fx2;
wire fgx_pdist_fx3;
wire fgx_popc_fx3;
wire [11:0] pdist_rs3_fx2;
wire popc_byte7a_cout_fx2;
wire popc_byte7a_carry_fx2;
wire popc_byte7a_sum_fx2;
wire popc_byte7b_cout_fx2;
wire popc_byte7b_carry_fx2;
wire popc_byte7b_sum_fx2;
wire popc_byte7c_cout_fx2;
wire popc_byte7c_carry_fx2;
wire popc_byte7c_sum_fx2;
wire [3:0] popc_byte7_sum_fx2;
wire popc_b7_unused;
wire popc_byte6a_cout_fx2;
wire popc_byte6a_carry_fx2;
wire popc_byte6a_sum_fx2;
wire popc_byte6b_cout_fx2;
wire popc_byte6b_carry_fx2;
wire popc_byte6b_sum_fx2;
wire popc_byte6c_cout_fx2;
wire popc_byte6c_carry_fx2;
wire popc_byte6c_sum_fx2;
wire [3:0] popc_byte6_sum_fx2;
wire popc_b6_unused;
wire popc_byte5a_cout_fx2;
wire popc_byte5a_carry_fx2;
wire popc_byte5a_sum_fx2;
wire popc_byte5b_cout_fx2;
wire popc_byte5b_carry_fx2;
wire popc_byte5b_sum_fx2;
wire popc_byte5c_cout_fx2;
wire popc_byte5c_carry_fx2;
wire popc_byte5c_sum_fx2;
wire [3:0] popc_byte5_sum_fx2;
wire popc_b5_unused;
wire popc_byte4a_cout_fx2;
wire popc_byte4a_carry_fx2;
wire popc_byte4a_sum_fx2;
wire popc_byte4b_cout_fx2;
wire popc_byte4b_carry_fx2;
wire popc_byte4b_sum_fx2;
wire popc_byte4c_cout_fx2;
wire popc_byte4c_carry_fx2;
wire popc_byte4c_sum_fx2;
wire [3:0] popc_byte4_sum_fx2;
wire popc_b4_unused;
wire popc_byte3a_cout_fx2;
wire popc_byte3a_carry_fx2;
wire popc_byte3a_sum_fx2;
wire popc_byte3b_cout_fx2;
wire popc_byte3b_carry_fx2;
wire popc_byte3b_sum_fx2;
wire popc_byte3c_cout_fx2;
wire popc_byte3c_carry_fx2;
wire popc_byte3c_sum_fx2;
wire [3:0] popc_byte3_sum_fx2;
wire popc_b3_unused;
wire popc_byte2a_cout_fx2;
wire popc_byte2a_carry_fx2;
wire popc_byte2a_sum_fx2;
wire popc_byte2b_cout_fx2;
wire popc_byte2b_carry_fx2;
wire popc_byte2b_sum_fx2;
wire popc_byte2c_cout_fx2;
wire popc_byte2c_carry_fx2;
wire popc_byte2c_sum_fx2;
wire [3:0] popc_byte2_sum_fx2;
wire popc_b2_unused;
wire popc_byte1a_cout_fx2;
wire popc_byte1a_carry_fx2;
wire popc_byte1a_sum_fx2;
wire popc_byte1b_cout_fx2;
wire popc_byte1b_carry_fx2;
wire popc_byte1b_sum_fx2;
wire popc_byte1c_cout_fx2;
wire popc_byte1c_carry_fx2;
wire popc_byte1c_sum_fx2;
wire [3:0] popc_byte1_sum_fx2;
wire popc_b1_unused;
wire popc_byte0a_cout_fx2;
wire popc_byte0a_carry_fx2;
wire popc_byte0a_sum_fx2;
wire popc_byte0b_cout_fx2;
wire popc_byte0b_carry_fx2;
wire popc_byte0b_sum_fx2;
wire popc_byte0c_cout_fx2;
wire popc_byte0c_carry_fx2;
wire popc_byte0c_sum_fx2;
wire [3:0] popc_byte0_sum_fx2;
wire popc_b0_unused;
wire fx3_rs1_scanin;
wire fx3_rs1_scanout;
wire [63:0] rs1_fx3;
wire [63:0] rs10_fx3;
wire fx3_rs2_scanin;
wire fx3_rs2_scanout;
wire [63:0] rs2_fx3;
wire [63:0] rs20_fx3;
wire fx3_gsr_mask_scanin;
wire fx3_gsr_mask_scanout;
wire [31:0] gsr_mask_fx3;
wire fx3_popc_scanin;
wire fx3_popc_scanout;
wire [3:0] popc_byte0_sum_fx3;
wire [3:0] popc_byte1_sum_fx3;
wire [3:0] popc_byte2_sum_fx3;
wire [3:0] popc_byte3_sum_fx3;
wire [3:0] popc_byte4_sum_fx3;
wire [3:0] popc_byte5_sum_fx3;
wire [3:0] popc_byte6_sum_fx3;
wire [3:0] popc_byte7_sum_fx3;
wire fx3_ctl_scanin;
wire fx3_ctl_scanout;
wire fgx_pdist_fx2;
wire fgx_pack_sel_fx3;
wire fgx_abs_fx3;
wire fgx_neg_fx3;
wire fgx_logical_fx3;
wire fgx_expand_fx3;
wire fgx_merge_fx3;
wire fgx_align_fx3;
wire fgx_shuffle_fx3;
wire fgx_pack16_fx3;
wire fgx_pack32_fx3;
wire fgx_packfix_fx3;
wire [4:1] opf_fx3;
wire fgx_pdist_fx4;
wire fgx_popc_fx4;
wire fgx_pack_sel_fx4;
wire [11:0] pdist_rs3_fx3;
wire [63:0] rs101_fx3;
wire [63:0] rs201_fx3;
wire [63:0] rs201_fx3_;
wire [63:0] rs101_fx3_;
wire [4:1] opf1_fx3;
wire [4:1] opf0_fx3;
wire [63:0] logical_int0_fx3;
wire [63:0] logical_int1_fx3;
wire [63:0] logical_int2_fx3;
wire [63:0] logical_int3_fx3;
wire [63:0] logical_result_fx3;
wire [31:0] gsr_mask0_fx4;
wire [63:0] rs1_shuf_fx3;
wire [63:0] rs2_shuf_fx3;
wire [63:0] shuf_result_fx3;
wire [63:0] align_result_fx3;
wire rs2_sign63_neg_fx3;
wire rs2_sign63_res_fx3;
wire fx4_simp_scanin;
wire fx4_simp_scanout;
wire [63:0] simp_result_fx4;
wire fgx_pack16_fx3_;
wire sh16_sel_fx3;
wire [63:0] shift16_fx3;
wire [23:0] gate16_fx3;
wire [63:0] shift04_fx3;
wire [5:0] gate04_fx3;
wire [63:7] shift01_fx3;
wire [6:0] pack_01_d2_unused;
wire [6:0] pack_01_d0_unused;
wire pack_sign63_fx3;
wire [15:0] clip16_c3_fx3;
wire [27:0] clip04_c3_fx3;
wire [30:0] clip01_c3_fx3;
wire [11:0] clip04_c2_fx3;
wire [14:0] clip01_c2_fx3;
wire pack_sign31_fx3;
wire [15:0] clip16_c1_fx3;
wire [27:0] clip04_c1_fx3;
wire [30:0] clip01_c1_fx3;
wire [11:0] clip04_c0_fx3;
wire [14:0] clip01_c0_fx3;
wire [63:0] pdist_amb_fx3;
wire pdist_amb_cout0_fx3;
wire pdist_amb_cout1_fx3;
wire pdist_amb_cout2_fx3;
wire pdist_amb_cout3_fx3;
wire pdist_amb_cout4_fx3;
wire pdist_amb_cout5_fx3;
wire pdist_amb_cout6_fx3;
wire pdist_amb_cout7_fx3;
wire [63:0] pdist_bma_fx3;
wire pdist_bma0_unused;
wire pdist_bma1_unused;
wire pdist_bma2_unused;
wire pdist_bma3_unused;
wire pdist_bma4_unused;
wire pdist_bma5_unused;
wire pdist_bma6_unused;
wire pdist_bma7_unused;
wire [63:0] pdist_mux_fx3;
wire pdist_42csa_cout0_fx3;
wire [8:1] pdist_42csa_carry0_fx3;
wire [7:0] pdist_42csa_sum0_fx3;
wire pdist_42csa_cout1_fx3;
wire [8:1] pdist_42csa_carry1_fx3;
wire [7:0] pdist_42csa_sum1_fx3;
wire fx4_rs1_scanin;
wire fx4_rs1_scanout;
wire [55:0] rs1_fx4;
wire fx4_shift_scanin;
wire fx4_shift_scanout;
wire [63:7] shift01_fx4;
wire fx4_clipa_scanin;
wire fx4_clipa_scanout;
wire [30:0] clip01_c3_fx4;
wire [30:0] clip01_c1_fx4;
wire fx4_clipb_scanin;
wire fx4_clipb_scanout;
wire rs2_fx4_b63;
wire rs2_fx4_b47;
wire [14:0] clip01_c2_fx4;
wire [14:0] clip01_c0_fx4;
wire rs2_fx4_b31;
wire rs2_fx4_b15;
wire fgx_packfix_fx4;
wire fgx_pack32_fx4;
wire fgx_pack16_fx4;
wire fx4_pdist_scanin;
wire fx4_pdist_scanout;
wire [33:0] pdist_42csa_data_fx4;
wire fx4_gsrtid_scanin;
wire fx4_gsrtid_scanout;
wire [2:0] gsr_asr_tid_fx3;
wire [2:0] tid_fx3;
wire fx4_gsr0mask_wmr_scanin;
wire fx4_gsr0mask_wmr_scanout;
wire [63:0] in_rngl_cdbus_3f;
wire [31:0] gsr0_mask_fx4;
wire fx4_gsr1mask_wmr_scanin;
wire fx4_gsr1mask_wmr_scanout;
wire [31:0] gsr1_mask_fx4;
wire fx4_gsr2mask_wmr_scanin;
wire fx4_gsr2mask_wmr_scanout;
wire [31:0] gsr2_mask_fx4;
wire fx4_gsr3mask_wmr_scanin;
wire fx4_gsr3mask_wmr_scanout;
wire [31:0] gsr3_mask_fx4;
wire fx4_gsr4mask_wmr_scanin;
wire fx4_gsr4mask_wmr_scanout;
wire [31:0] gsr4_mask_fx4;
wire fx4_gsr5mask_wmr_scanin;
wire fx4_gsr5mask_wmr_scanout;
wire [31:0] gsr5_mask_fx4;
wire fx4_gsr6mask_wmr_scanin;
wire fx4_gsr6mask_wmr_scanout;
wire [31:0] gsr6_mask_fx4;
wire fx4_gsr7mask_wmr_scanin;
wire fx4_gsr7mask_wmr_scanout;
wire [31:0] gsr7_mask_fx4;
wire [31:0] gsr_mask_fx4;
wire tcu_muxtest_a_rep0;
wire [30:0] gsr_asr_mask_fx4;
wire pack_b01_gt255_fx4_;
wire pack_b01_lt32768_fx4_;
wire pack_b23_gt255_fx4_;
wire pack_b45_gt255_fx4_;
wire pack_b45_lt32768_fx4_;
wire pack_b67_gt255_fx4_;
wire pack_b01_gt255_fx4;
wire pack_b01_lt32768_fx4;
wire pack_b23_gt255_fx4;
wire pack_b45_gt255_fx4;
wire pack_b45_lt32768_fx4;
wire pack_b67_gt255_fx4;
wire rs2_fx4_b63_;
wire rs2_fx4_b31_;
wire packfix_hi_lt32768_fx4;
wire packfix_lo_lt32768_fx4;
wire packfix_hi_gt32767_fx4;
wire packfix_lo_gt32767_fx4;
wire pack_b3_sign_fx4;
wire pack_b3_gt255_fx4;
wire [63:32] pack_result_fx4;
wire [7:0] pack_result_fx4_b7_0;
wire pdist_42csa_cout2_fx4;
wire [9:1] pdist_42csa_carry2_fx4;
wire [8:0] pdist_42csa_sum2_fx4;
wire [10:1] pdist_32csa_carry_fx4;
wire [9:0] pdist_32csa_sum_fx4;
wire q_pdist_rs3_fx3_b11;
wire [63:0] pdist_sum_fx4;
wire pdist_cout_fx4;
wire [12:0] pdist_inc_unused;
wire fx5_res_scanin;
wire fx5_res_scanout;
wire in_rng1_1f_scanin;
wire in_rng1_1f_scanout;
wire [63:0] in_rngl_cdbus_1f;
wire in_rng0_1f_scanin;
wire in_rng0_1f_scanout;
wire in_rng1_2f_scanin;
wire in_rng1_2f_scanout;
wire [63:0] in_rngl_cdbus_2f;
wire in_rng0_2f_scanin;
wire in_rng0_2f_scanout;
wire in_rng1_3f_scanin;
wire in_rng1_3f_scanout;
wire in_rng0_3f_scanin;
wire in_rng0_3f_scanout;
wire tcu_muxtest_b_rep0;
wire tcu_muxtest_c_rep0;


// ----------------------------------------------------------------------------
// Interface with FAD
// ----------------------------------------------------------------------------

input   [63:0] fad_rs1_fmt_fx1;        // rs1 formatted
input   [63:0] fad_rs2_fmt_fx1;        // rs2 formatted

output  [62:0] fgd_rngl_cdbus_3f;

// ----------------------------------------------------------------------------
// Interface with FPF
// ----------------------------------------------------------------------------

output  [63:0] fgd_result_fx5;         // FGX result

// ----------------------------------------------------------------------------
// Interface with FAC
// ----------------------------------------------------------------------------

input          vis_clken;              // vis clken
input          coreon_clken;           // controls all "free running" flops

input          fac_fgx_abs_fx2;        // FABS
input          fac_fgx_neg_fx2;        // FNEG
input          fac_fgx_logical_fx2;    // logical instructions
input          fac_fgx_expand_fx2;     // FEXPAND
input          fac_fgx_merge_fx2;      // FPMERGE
input          fac_fgx_align_fx2;      // FALIGNDATA
input          fac_fgx_shuffle_fx2;    // BSHUFFLE
input          fac_fgx_pack16_fx2;     // FPACK16
input          fac_fgx_pack32_fx2;     // FPACK32
input          fac_fgx_packfix_fx2;    // FPACKFIX
input          fac_fgx_pdist_fx1;      // PDIST
input          fac_fgx_popc_fx2;       // POPC

input          fac_fgx_pack_sel_fx2;   // FPACK16,FPACK32,FPACKFIX

input    [4:1] fac_opf_fx2;            // instr opf field
input    [2:0] fac_gsr_asr_tid_fx2;
input    [2:0] fac_tid_fx2;

input    [2:0] fac_rng_fprs;           // ASR FPRS read data
input          fac_rng_rd_fprs_4f;     // ASR FPRS read
input          fac_rng_rd_gsr_4f;      // ASR GSR  read
input   [13:0] fec_r1_ecc_fx1;         // ASI FRF ECC read data
input          fac_rng_rd_ecc_4f;      // ASI FRF ECC read
input          fac_rng_rd_or_wr_3f;    // ASR/ASI GSR/FPRS/FRF_ECC rd or wr decoded

input          asi_clken;              // asi clken: controls ASI ring stage flops

output         fgd_gsr_asr_mask_fx4_b31;

// ----------------------------------------------------------------------------
// Interface with FPC
// ----------------------------------------------------------------------------

input    [1:0] fpc_gsr0_mask_sel_fx3;
input    [1:0] fpc_gsr1_mask_sel_fx3;
input    [1:0] fpc_gsr2_mask_sel_fx3;
input    [1:0] fpc_gsr3_mask_sel_fx3;
input    [1:0] fpc_gsr4_mask_sel_fx3;
input    [1:0] fpc_gsr5_mask_sel_fx3;
input    [1:0] fpc_gsr6_mask_sel_fx3;
input    [1:0] fpc_gsr7_mask_sel_fx3;
input    [4:0] fpc_gsr_scale_fx4;
input    [2:0] fpc_gsr_align_fx4;
input   [10:0] fpc_gsr_asr_11bits_fx4;

// ----------------------------------------------------------------------------
// Interface with EXU
// ----------------------------------------------------------------------------

input   [31:0] exu_fgu_gsr_m;          // GSR.align data:
                                       //   [31:3] = don't care
                                       //   [2:0]  = GSR.align
                                       //   GSR.mask data:
                                       //   [31:0] = GSR.mask

// ----------------------------------------------------------------------------
// Global Signals
// ----------------------------------------------------------------------------

input          l2clk;                  // clock input
input  	       scan_in;
input          spc_aclk_wmr;
input          wmr_scan_in;
input          lb_scan_en_wmr;
input  	       tcu_pce_ov;		// scan signals
input  	       spc_aclk;
input  	       spc_bclk;
input 	       tcu_dectest;
input          tcu_muxtest;
input          tcu_scan_en;
output 	       scan_out;
output         wmr_scan_out;
input   [63:0] in_rngl_cdbus;          // ASI local ring


// scan renames
assign stop   = 1'b0;
assign test   = tcu_dectest;
// end scan

fgu_fgd_dp_buff_macro__dbuff_32x__rep_1__width_4 test_rep0  (
  .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}),
  .dout({se,          pce_ov,     siclk,    soclk   })
  );


// ----------------------------------------------------------------------------
//                               FX2 stage
// ----------------------------------------------------------------------------

fgu_fgd_dp_msff_macro__width_64 fx2_rs1  (
  .scan_in(fx2_rs1_scanin),
  .scan_out(fx2_rs1_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din (fad_rs1_fmt_fx1[63:0]),
  .dout(    rs1_fx2[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__width_64 fx2_rs2  (
  .scan_in(fx2_rs2_scanin),
  .scan_out(fx2_rs2_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din (fad_rs2_fmt_fx1[63:0]),
  .dout(    rs2_fx2[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__stack_32l__width_32 fx2_gsr  (
  .scan_in(fx2_gsr_scanin),
  .scan_out(fx2_gsr_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din (exu_fgu_gsr_m[31:0]  ),
  .dout(        gsr_fx2[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 pdist_rs3  ( 
  .din0(rs2_fx2[11:0]),
  .din1(12'b0),
  .sel0(fgx_pdist_fx3),  // since rs3 data skips a stage, selects skip a stage
  .sel1(fgx_popc_fx3),
  .dout(pdist_rs3_fx2[11:0])
  );

// ------------------------------------
// uniquie POPC frontend (fx2)
// ------------------------------------

//------
// byte7
//------

fgu_fgd_dp_csa42_macro__width_1 popc_b7a  (
  .i0   (rs2_fx2[0]),
  .i1   (rs2_fx2[1]),
  .i2   (rs2_fx2[2]),
  .i3   (rs2_fx2[3]),
  .cin  (1'b0       ),
  .cout (popc_byte7a_cout_fx2 ), 
  .carry(popc_byte7a_carry_fx2),
  .sum  (popc_byte7a_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b7b  (
  .i0   (rs2_fx2[4]),
  .i1   (rs2_fx2[5]),
  .i2   (rs2_fx2[6]),
  .i3   (rs2_fx2[7]),
  .cin  (1'b0       ),
  .cout (popc_byte7b_cout_fx2 ), 
  .carry(popc_byte7b_carry_fx2),
  .sum  (popc_byte7b_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b7c  (
  .i0   (popc_byte7a_cout_fx2 ),
  .i1   (popc_byte7a_carry_fx2),
  .i2   (popc_byte7b_cout_fx2 ),
  .i3   (popc_byte7b_carry_fx2),
  .cin  (1'b0                 ),
  .cout (popc_byte7c_cout_fx2 ), 
  .carry(popc_byte7c_carry_fx2),
  .sum  (popc_byte7c_sum_fx2  )  
  );

fgu_fgd_dp_cla_macro__width_4 popc_b7  (  // 0in maximum -val 8 -var {popc_b7_unused, popc_byte7_sum_fx2[3:0]}
  .din0({1'b0, popc_byte7c_carry_fx2, popc_byte7c_sum_fx2, popc_byte7a_sum_fx2}),
  .din1({1'b0, popc_byte7c_cout_fx2 , 1'b0               , popc_byte7b_sum_fx2}),
  .cin (1'b0),
  .dout(popc_byte7_sum_fx2[3:0]),
  .cout(popc_b7_unused         )
  );

//------
// byte6
//------

fgu_fgd_dp_csa42_macro__width_1 popc_b6a  (
  .i0   (rs2_fx2[8]),
  .i1   (rs2_fx2[9]),
  .i2   (rs2_fx2[10]),
  .i3   (rs2_fx2[11]),
  .cin  (1'b0       ),
  .cout (popc_byte6a_cout_fx2 ), 
  .carry(popc_byte6a_carry_fx2),
  .sum  (popc_byte6a_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b6b  (
  .i0   (rs2_fx2[12]),
  .i1   (rs2_fx2[13]),
  .i2   (rs2_fx2[14]),
  .i3   (rs2_fx2[15]),
  .cin  (1'b0       ),
  .cout (popc_byte6b_cout_fx2 ), 
  .carry(popc_byte6b_carry_fx2),
  .sum  (popc_byte6b_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b6c  (
  .i0   (popc_byte6a_cout_fx2 ),
  .i1   (popc_byte6a_carry_fx2),
  .i2   (popc_byte6b_cout_fx2 ),
  .i3   (popc_byte6b_carry_fx2),
  .cin  (1'b0                 ),
  .cout (popc_byte6c_cout_fx2 ), 
  .carry(popc_byte6c_carry_fx2),
  .sum  (popc_byte6c_sum_fx2  )  
  );

fgu_fgd_dp_cla_macro__width_4 popc_b6  (  // 0in maximum -val 8 -var {popc_b6_unused, popc_byte6_sum_fx2[3:0]}
  .din0({1'b0, popc_byte6c_carry_fx2, popc_byte6c_sum_fx2, popc_byte6a_sum_fx2}),
  .din1({1'b0, popc_byte6c_cout_fx2 , 1'b0               , popc_byte6b_sum_fx2}),
  .cin (1'b0),
  .dout(popc_byte6_sum_fx2[3:0]),
  .cout(popc_b6_unused         )
  );

//------
// byte5
//------

fgu_fgd_dp_csa42_macro__width_1 popc_b5a  (
  .i0   (rs2_fx2[16]),
  .i1   (rs2_fx2[17]),
  .i2   (rs2_fx2[18]),
  .i3   (rs2_fx2[19]),
  .cin  (1'b0       ),
  .cout (popc_byte5a_cout_fx2 ), 
  .carry(popc_byte5a_carry_fx2),
  .sum  (popc_byte5a_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b5b  (
  .i0   (rs2_fx2[20]),
  .i1   (rs2_fx2[21]),
  .i2   (rs2_fx2[22]),
  .i3   (rs2_fx2[23]),
  .cin  (1'b0       ),
  .cout (popc_byte5b_cout_fx2 ), 
  .carry(popc_byte5b_carry_fx2),
  .sum  (popc_byte5b_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b5c  (
  .i0   (popc_byte5a_cout_fx2 ),
  .i1   (popc_byte5a_carry_fx2),
  .i2   (popc_byte5b_cout_fx2 ),
  .i3   (popc_byte5b_carry_fx2),
  .cin  (1'b0                 ),
  .cout (popc_byte5c_cout_fx2 ), 
  .carry(popc_byte5c_carry_fx2),
  .sum  (popc_byte5c_sum_fx2  )  
  );

fgu_fgd_dp_cla_macro__width_4 popc_b5  (  // 0in maximum -val 8 -var {popc_b5_unused, popc_byte5_sum_fx2[3:0]}
  .din0({1'b0, popc_byte5c_carry_fx2, popc_byte5c_sum_fx2, popc_byte5a_sum_fx2}),
  .din1({1'b0, popc_byte5c_cout_fx2 , 1'b0               , popc_byte5b_sum_fx2}),
  .cin (1'b0),
  .dout(popc_byte5_sum_fx2[3:0]),
  .cout(popc_b5_unused         )
  );

//------
// byte4
//------

fgu_fgd_dp_csa42_macro__width_1 popc_b4a  (
  .i0   (rs2_fx2[24]),
  .i1   (rs2_fx2[25]),
  .i2   (rs2_fx2[26]),
  .i3   (rs2_fx2[27]),
  .cin  (1'b0       ),
  .cout (popc_byte4a_cout_fx2 ), 
  .carry(popc_byte4a_carry_fx2),
  .sum  (popc_byte4a_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b4b  (
  .i0   (rs2_fx2[28]),
  .i1   (rs2_fx2[29]),
  .i2   (rs2_fx2[30]),
  .i3   (rs2_fx2[31]),
  .cin  (1'b0       ),
  .cout (popc_byte4b_cout_fx2 ), 
  .carry(popc_byte4b_carry_fx2),
  .sum  (popc_byte4b_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b4c  (
  .i0   (popc_byte4a_cout_fx2 ),
  .i1   (popc_byte4a_carry_fx2),
  .i2   (popc_byte4b_cout_fx2 ),
  .i3   (popc_byte4b_carry_fx2),
  .cin  (1'b0                 ),
  .cout (popc_byte4c_cout_fx2 ), 
  .carry(popc_byte4c_carry_fx2),
  .sum  (popc_byte4c_sum_fx2  )  
  );

fgu_fgd_dp_cla_macro__width_4 popc_b4  (  // 0in maximum -val 8 -var {popc_b4_unused, popc_byte4_sum_fx2[3:0]}
  .din0({1'b0, popc_byte4c_carry_fx2, popc_byte4c_sum_fx2, popc_byte4a_sum_fx2}),
  .din1({1'b0, popc_byte4c_cout_fx2 , 1'b0               , popc_byte4b_sum_fx2}),
  .cin (1'b0),
  .dout(popc_byte4_sum_fx2[3:0]),
  .cout(popc_b4_unused         )
  );

//------
// byte3
//------

fgu_fgd_dp_csa42_macro__width_1 popc_b3a  (
  .i0   (rs2_fx2[32]),
  .i1   (rs2_fx2[33]),
  .i2   (rs2_fx2[34]),
  .i3   (rs2_fx2[35]),
  .cin  (1'b0       ),
  .cout (popc_byte3a_cout_fx2 ), 
  .carry(popc_byte3a_carry_fx2),
  .sum  (popc_byte3a_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b3b  (
  .i0   (rs2_fx2[36]),
  .i1   (rs2_fx2[37]),
  .i2   (rs2_fx2[38]),
  .i3   (rs2_fx2[39]),
  .cin  (1'b0       ),
  .cout (popc_byte3b_cout_fx2 ), 
  .carry(popc_byte3b_carry_fx2),
  .sum  (popc_byte3b_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b3c  (
  .i0   (popc_byte3a_cout_fx2 ),
  .i1   (popc_byte3a_carry_fx2),
  .i2   (popc_byte3b_cout_fx2 ),
  .i3   (popc_byte3b_carry_fx2),
  .cin  (1'b0                 ),
  .cout (popc_byte3c_cout_fx2 ), 
  .carry(popc_byte3c_carry_fx2),
  .sum  (popc_byte3c_sum_fx2  )  
  );

fgu_fgd_dp_cla_macro__width_4 popc_b3  (  // 0in maximum -val 8 -var {popc_b3_unused, popc_byte3_sum_fx2[3:0]}
  .din0({1'b0, popc_byte3c_carry_fx2, popc_byte3c_sum_fx2, popc_byte3a_sum_fx2}),
  .din1({1'b0, popc_byte3c_cout_fx2 , 1'b0               , popc_byte3b_sum_fx2}),
  .cin (1'b0),
  .dout(popc_byte3_sum_fx2[3:0]),
  .cout(popc_b3_unused         )
  );

//------
// byte2
//------

fgu_fgd_dp_csa42_macro__width_1 popc_b2a  (
  .i0   (rs2_fx2[40]),
  .i1   (rs2_fx2[41]),
  .i2   (rs2_fx2[42]),
  .i3   (rs2_fx2[43]),
  .cin  (1'b0       ),
  .cout (popc_byte2a_cout_fx2 ), 
  .carry(popc_byte2a_carry_fx2),
  .sum  (popc_byte2a_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b2b  (
  .i0   (rs2_fx2[44]),
  .i1   (rs2_fx2[45]),
  .i2   (rs2_fx2[46]),
  .i3   (rs2_fx2[47]),
  .cin  (1'b0       ),
  .cout (popc_byte2b_cout_fx2 ), 
  .carry(popc_byte2b_carry_fx2),
  .sum  (popc_byte2b_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b2c  (
  .i0   (popc_byte2a_cout_fx2 ),
  .i1   (popc_byte2a_carry_fx2),
  .i2   (popc_byte2b_cout_fx2 ),
  .i3   (popc_byte2b_carry_fx2),
  .cin  (1'b0                 ),
  .cout (popc_byte2c_cout_fx2 ), 
  .carry(popc_byte2c_carry_fx2),
  .sum  (popc_byte2c_sum_fx2  )  
  );

fgu_fgd_dp_cla_macro__width_4 popc_b2  (  // 0in maximum -val 8 -var {popc_b2_unused, popc_byte2_sum_fx2[3:0]}
  .din0({1'b0, popc_byte2c_carry_fx2, popc_byte2c_sum_fx2, popc_byte2a_sum_fx2}),
  .din1({1'b0, popc_byte2c_cout_fx2 , 1'b0               , popc_byte2b_sum_fx2}),
  .cin (1'b0),
  .dout(popc_byte2_sum_fx2[3:0]),
  .cout(popc_b2_unused         )
  );

//------
// byte1
//------

fgu_fgd_dp_csa42_macro__width_1 popc_b1a  (
  .i0   (rs2_fx2[48]),
  .i1   (rs2_fx2[49]),
  .i2   (rs2_fx2[50]),
  .i3   (rs2_fx2[51]),
  .cin  (1'b0       ),
  .cout (popc_byte1a_cout_fx2 ), 
  .carry(popc_byte1a_carry_fx2),
  .sum  (popc_byte1a_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b1b  (
  .i0   (rs2_fx2[52]),
  .i1   (rs2_fx2[53]),
  .i2   (rs2_fx2[54]),
  .i3   (rs2_fx2[55]),
  .cin  (1'b0       ),
  .cout (popc_byte1b_cout_fx2 ), 
  .carry(popc_byte1b_carry_fx2),
  .sum  (popc_byte1b_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b1c  (
  .i0   (popc_byte1a_cout_fx2 ),
  .i1   (popc_byte1a_carry_fx2),
  .i2   (popc_byte1b_cout_fx2 ),
  .i3   (popc_byte1b_carry_fx2),
  .cin  (1'b0                 ),
  .cout (popc_byte1c_cout_fx2 ), 
  .carry(popc_byte1c_carry_fx2),
  .sum  (popc_byte1c_sum_fx2  )  
  );

fgu_fgd_dp_cla_macro__width_4 popc_b1  (  // 0in maximum -val 8 -var {popc_b1_unused, popc_byte1_sum_fx2[3:0]}
  .din0({1'b0, popc_byte1c_carry_fx2, popc_byte1c_sum_fx2, popc_byte1a_sum_fx2}),
  .din1({1'b0, popc_byte1c_cout_fx2 , 1'b0               , popc_byte1b_sum_fx2}),
  .cin (1'b0),
  .dout(popc_byte1_sum_fx2[3:0]),
  .cout(popc_b1_unused         )
  );

//------
// byte0
//------

fgu_fgd_dp_csa42_macro__width_1 popc_b0a  (
  .i0   (rs2_fx2[56]),
  .i1   (rs2_fx2[57]),
  .i2   (rs2_fx2[58]),
  .i3   (rs2_fx2[59]),
  .cin  (1'b0       ),
  .cout (popc_byte0a_cout_fx2 ), 
  .carry(popc_byte0a_carry_fx2),
  .sum  (popc_byte0a_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b0b  (
  .i0   (rs2_fx2[60]),
  .i1   (rs2_fx2[61]),
  .i2   (rs2_fx2[62]),
  .i3   (rs2_fx2[63]),
  .cin  (1'b0       ),
  .cout (popc_byte0b_cout_fx2 ), 
  .carry(popc_byte0b_carry_fx2),
  .sum  (popc_byte0b_sum_fx2  )  
  );

fgu_fgd_dp_csa42_macro__width_1 popc_b0c  (
  .i0   (popc_byte0a_cout_fx2 ),
  .i1   (popc_byte0a_carry_fx2),
  .i2   (popc_byte0b_cout_fx2 ),
  .i3   (popc_byte0b_carry_fx2),
  .cin  (1'b0                 ),
  .cout (popc_byte0c_cout_fx2 ), 
  .carry(popc_byte0c_carry_fx2),
  .sum  (popc_byte0c_sum_fx2  )  
  );

fgu_fgd_dp_cla_macro__width_4 popc_b0  (  // 0in maximum -val 8 -var {popc_b0_unused, popc_byte0_sum_fx2[3:0]}
  .din0({1'b0, popc_byte0c_carry_fx2, popc_byte0c_sum_fx2, popc_byte0a_sum_fx2}),
  .din1({1'b0, popc_byte0c_cout_fx2 , 1'b0               , popc_byte0b_sum_fx2}),
  .cin (1'b0),
  .dout(popc_byte0_sum_fx2[3:0]),
  .cout(popc_b0_unused         )
  );


// ----------------------------------------------------------------------------
//                               FX3 stage
// ----------------------------------------------------------------------------

fgu_fgd_dp_msff_macro__width_64 fx3_rs1  (
  .scan_in(fx3_rs1_scanin),
  .scan_out(fx3_rs1_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din (rs1_fx2[63:0]),
  .dout(rs1_fx3[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_buff_macro__width_64 buf_rs1  (
  .din (rs1_fx3[63:0] ),
  .dout(rs10_fx3[63:0])
  );

fgu_fgd_dp_msff_macro__minbuff_1__width_64 fx3_rs2  (
  .scan_in(fx3_rs2_scanin),
  .scan_out(fx3_rs2_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din (rs2_fx2[63:0]),
  .dout(rs2_fx3[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_buff_macro__width_64 buf_rs2  (
  .din (rs2_fx3[63:0] ),
  .dout(rs20_fx3[63:0])
  );

fgu_fgd_dp_msff_macro__stack_32l__width_32 fx3_gsr_mask  (
  .scan_in(fx3_gsr_mask_scanin),
  .scan_out(fx3_gsr_mask_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din (gsr_fx2[31:0]),
  .dout(gsr_mask_fx3[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__width_32 fx3_popc  (
  .scan_in(fx3_popc_scanin),
  .scan_out(fx3_popc_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din ({popc_byte0_sum_fx2[3:0],
         popc_byte1_sum_fx2[3:0],
         popc_byte2_sum_fx2[3:0],
         popc_byte3_sum_fx2[3:0],
         popc_byte4_sum_fx2[3:0],
         popc_byte5_sum_fx2[3:0],
         popc_byte6_sum_fx2[3:0],
         popc_byte7_sum_fx2[3:0]}),
  .dout({popc_byte0_sum_fx3[3:0],
         popc_byte1_sum_fx3[3:0],
         popc_byte2_sum_fx3[3:0],
         popc_byte3_sum_fx3[3:0],
         popc_byte4_sum_fx3[3:0],
         popc_byte5_sum_fx3[3:0],
         popc_byte6_sum_fx3[3:0],
         popc_byte7_sum_fx3[3:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__width_33 fx3_ctl  (
  .scan_in(fx3_ctl_scanin),
  .scan_out(fx3_ctl_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din ({fac_fgx_abs_fx2,
         fac_fgx_neg_fx2,
         fac_fgx_logical_fx2,
         fac_fgx_expand_fx2,
         fac_fgx_merge_fx2,
         fac_fgx_align_fx2,
         fac_fgx_shuffle_fx2,
         fac_fgx_pack16_fx2,
         fac_fgx_pack32_fx2,
         fac_fgx_packfix_fx2,
         fac_fgx_pdist_fx1,
             fgx_pdist_fx2,
         fac_fgx_popc_fx2,
         fac_fgx_pack_sel_fx2,
         fac_opf_fx2[4:1],
             fgx_pdist_fx3,
             fgx_popc_fx3,
             fgx_pack_sel_fx3,
             pdist_rs3_fx2[11:0]}),
  .dout({    fgx_abs_fx3,
             fgx_neg_fx3,
             fgx_logical_fx3,
             fgx_expand_fx3,
             fgx_merge_fx3,
             fgx_align_fx3,
             fgx_shuffle_fx3,
             fgx_pack16_fx3,
             fgx_pack32_fx3,
             fgx_packfix_fx3,
             fgx_pdist_fx2,
             fgx_pdist_fx3,
             fgx_popc_fx3,
             fgx_pack_sel_fx3,
             opf_fx3[4:1],
             fgx_pdist_fx4,
             fgx_popc_fx4,
             fgx_pack_sel_fx4,
             pdist_rs3_fx3[11:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );


// ----------------------------------------------------------------------------
// Logical operations:
//
// Instr        opf bit: 4321               rs1   rs2
// --------------------------               sel1  sel0       out
// FZERO,    FZEROS      0000               -------------------------
// FNOR,     FNORS       0001                0     0      in0: opf[1]
// FANDNOT2, FANDNOT2S   0010                0     1      in1: opf[3]
// FNOT2,    FNOT2S      0011                1     0      in2: opf[2]
// FANDNOT1, FANDNOT1S   0100                1     1      in3: opf[4]
// FNOT1,    FNOT1S      0101
// FXOR,     FXORS       0110
// FNAND,    FNANDS      0111
// FAND,     FANDS       1000
// FXNOR,    FXNORS      1001
// FSRC1,    FSRC1S      1010
// FORNOT2,  FORNOT2S    1011
// FSRC2,    FSRC2S      1100
// FORNOT1,  FORNOT1S    1101
// FOR,      FORS        1110
// FONE,     FONES       1111
//
// Logical instr are implemented with a 4:1 mux structure built from a
// nand-nand (and-or) gate organization.
//
// ----------------------------------------------------------------------------

fgu_fgd_dp_buff_macro__width_64 buf_rs101  (
  .din (rs1_fx3[63:0]  ),
  .dout(rs101_fx3[63:0])
  );

fgu_fgd_dp_buff_macro__width_64 buf_rs201  (
  .din (rs2_fx3[63:0]  ),
  .dout(rs201_fx3[63:0])
  );

fgu_fgd_dp_inv_macro__width_64 inv_rs2  (
  .din (rs201_fx3[63:0] ),
  .dout(rs201_fx3_[63:0]) 
  );

fgu_fgd_dp_inv_macro__width_64 inv_rs1  (
  .din (rs101_fx3[63:0] ),
  .dout(rs101_fx3_[63:0]) 
  );

fgu_fgd_dp_buff_macro__width_8 buf_opf  (
  .din ({opf_fx3[4:1], opf_fx3[4:1] }),
  .dout({opf1_fx3[4:1],opf0_fx3[4:1]})
  );

fgu_fgd_dp_nand_macro__ports_3__width_64 log_00  (
  .din0(rs101_fx3_[63:0]),
  .din1(rs201_fx3_[63:0]),
  .din2({{32{opf1_fx3[1]}},{32{opf0_fx3[1]}}}),
  .dout(logical_int0_fx3[63:0]) 
  );

fgu_fgd_dp_nand_macro__ports_3__width_64 log_01  (
  .din0(rs101_fx3_[63:0]),
  .din1(rs201_fx3[63:0] ),
  .din2({{32{opf1_fx3[3]}},{32{opf0_fx3[3]}}}),
  .dout(logical_int1_fx3[63:0]) 
  );

fgu_fgd_dp_nand_macro__ports_3__width_64 log_02  (
  .din0(rs101_fx3[63:0] ),
  .din1(rs201_fx3_[63:0]),
  .din2({{32{opf1_fx3[2]}},{32{opf0_fx3[2]}}}),
  .dout(logical_int2_fx3[63:0]) 
  );

fgu_fgd_dp_nand_macro__ports_3__width_64 log_03  (
  .din0(rs101_fx3[63:0]),
  .din1(rs201_fx3[63:0]),
  .din2({{32{opf1_fx3[4]}},{32{opf0_fx3[4]}}}),
  .dout(logical_int3_fx3[63:0]) 
  );

fgu_fgd_dp_nand_macro__ports_4__width_64 log_04  (
  .din0(logical_int0_fx3[63:0]),
  .din1(logical_int1_fx3[63:0]),
  .din2(logical_int2_fx3[63:0]),
  .din3(logical_int3_fx3[63:0]),
  .dout(logical_result_fx3[63:0]) 
  );

// ------------------------------------
// bshuffle rs1 and rs2 byte muxes
// ------------------------------------

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b0  (
  .din0(rs10_fx3[63:56]),
  .din1(rs10_fx3[55:48]),
  .din2(rs10_fx3[47:40]),
  .din3(rs10_fx3[39:32]),
  .din4(rs10_fx3[31:24]),
  .din5(rs10_fx3[23:16]),
  .din6(rs10_fx3[15:8]),
  .din7(rs10_fx3[7:0]),
  .sel(gsr_mask0_fx4[30:28]),
  .dout(rs1_shuf_fx3[63:56]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b1  (
  .din0(rs10_fx3[63:56]),
  .din1(rs10_fx3[55:48]),
  .din2(rs10_fx3[47:40]),
  .din3(rs10_fx3[39:32]),
  .din4(rs10_fx3[31:24]),
  .din5(rs10_fx3[23:16]),
  .din6(rs10_fx3[15:8]),
  .din7(rs10_fx3[7:0]),
  .sel(gsr_mask0_fx4[26:24]),
  .dout(rs1_shuf_fx3[55:48]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b2  (
  .din0(rs10_fx3[63:56]),
  .din1(rs10_fx3[55:48]),
  .din2(rs10_fx3[47:40]),
  .din3(rs10_fx3[39:32]),
  .din4(rs10_fx3[31:24]),
  .din5(rs10_fx3[23:16]),
  .din6(rs10_fx3[15:8]),
  .din7(rs10_fx3[7:0]),
  .sel(gsr_mask0_fx4[22:20]),
  .dout(rs1_shuf_fx3[47:40]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b3  (
  .din0(rs10_fx3[63:56]),
  .din1(rs10_fx3[55:48]),
  .din2(rs10_fx3[47:40]),
  .din3(rs10_fx3[39:32]),
  .din4(rs10_fx3[31:24]),
  .din5(rs10_fx3[23:16]),
  .din6(rs10_fx3[15:8]),
  .din7(rs10_fx3[7:0]),
  .sel(gsr_mask0_fx4[18:16]),
  .dout(rs1_shuf_fx3[39:32]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b4  (
  .din0(rs10_fx3[63:56]),
  .din1(rs10_fx3[55:48]),
  .din2(rs10_fx3[47:40]),
  .din3(rs10_fx3[39:32]),
  .din4(rs10_fx3[31:24]),
  .din5(rs10_fx3[23:16]),
  .din6(rs10_fx3[15:8]),
  .din7(rs10_fx3[7:0]),
  .sel(gsr_mask0_fx4[14:12]),
  .dout(rs1_shuf_fx3[31:24]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b5  (
  .din0(rs10_fx3[63:56]),
  .din1(rs10_fx3[55:48]),
  .din2(rs10_fx3[47:40]),
  .din3(rs10_fx3[39:32]),
  .din4(rs10_fx3[31:24]),
  .din5(rs10_fx3[23:16]),
  .din6(rs10_fx3[15:8]),
  .din7(rs10_fx3[7:0]),
  .sel(gsr_mask0_fx4[10:8]),
  .dout(rs1_shuf_fx3[23:16]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b6  (
  .din0(rs10_fx3[63:56]),
  .din1(rs10_fx3[55:48]),
  .din2(rs10_fx3[47:40]),
  .din3(rs10_fx3[39:32]),
  .din4(rs10_fx3[31:24]),
  .din5(rs10_fx3[23:16]),
  .din6(rs10_fx3[15:8]),
  .din7(rs10_fx3[7:0]),
  .sel(gsr_mask0_fx4[6:4]),
  .dout(rs1_shuf_fx3[15:8]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b7  (
  .din0(rs10_fx3[63:56]),
  .din1(rs10_fx3[55:48]),
  .din2(rs10_fx3[47:40]),
  .din3(rs10_fx3[39:32]),
  .din4(rs10_fx3[31:24]),
  .din5(rs10_fx3[23:16]),
  .din6(rs10_fx3[15:8]),
  .din7(rs10_fx3[7:0]),
  .sel(gsr_mask0_fx4[2:0]),
  .dout(rs1_shuf_fx3[7:0]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b0  (
  .din0(rs20_fx3[63:56]),
  .din1(rs20_fx3[55:48]),
  .din2(rs20_fx3[47:40]),
  .din3(rs20_fx3[39:32]),
  .din4(rs20_fx3[31:24]),
  .din5(rs20_fx3[23:16]),
  .din6(rs20_fx3[15:8]),
  .din7(rs20_fx3[7:0]),
  .sel(gsr_mask0_fx4[30:28]),
  .dout(rs2_shuf_fx3[63:56]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b1  (
  .din0(rs20_fx3[63:56]),
  .din1(rs20_fx3[55:48]),
  .din2(rs20_fx3[47:40]),
  .din3(rs20_fx3[39:32]),
  .din4(rs20_fx3[31:24]),
  .din5(rs20_fx3[23:16]),
  .din6(rs20_fx3[15:8]),
  .din7(rs20_fx3[7:0]),
  .sel(gsr_mask0_fx4[26:24]),
  .dout(rs2_shuf_fx3[55:48]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b2  (
  .din0(rs20_fx3[63:56]),
  .din1(rs20_fx3[55:48]),
  .din2(rs20_fx3[47:40]),
  .din3(rs20_fx3[39:32]),
  .din4(rs20_fx3[31:24]),
  .din5(rs20_fx3[23:16]),
  .din6(rs20_fx3[15:8]),
  .din7(rs20_fx3[7:0]),
  .sel(gsr_mask0_fx4[22:20]),
  .dout(rs2_shuf_fx3[47:40]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b3  (
  .din0(rs20_fx3[63:56]),
  .din1(rs20_fx3[55:48]),
  .din2(rs20_fx3[47:40]),
  .din3(rs20_fx3[39:32]),
  .din4(rs20_fx3[31:24]),
  .din5(rs20_fx3[23:16]),
  .din6(rs20_fx3[15:8]),
  .din7(rs20_fx3[7:0]),
  .sel(gsr_mask0_fx4[18:16]),
  .dout(rs2_shuf_fx3[39:32]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b4  (
  .din0(rs20_fx3[63:56]),
  .din1(rs20_fx3[55:48]),
  .din2(rs20_fx3[47:40]),
  .din3(rs20_fx3[39:32]),
  .din4(rs20_fx3[31:24]),
  .din5(rs20_fx3[23:16]),
  .din6(rs20_fx3[15:8]),
  .din7(rs20_fx3[7:0]),
  .sel(gsr_mask0_fx4[14:12]),
  .dout(rs2_shuf_fx3[31:24]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b5  (
  .din0(rs20_fx3[63:56]),
  .din1(rs20_fx3[55:48]),
  .din2(rs20_fx3[47:40]),
  .din3(rs20_fx3[39:32]),
  .din4(rs20_fx3[31:24]),
  .din5(rs20_fx3[23:16]),
  .din6(rs20_fx3[15:8]),
  .din7(rs20_fx3[7:0]),
  .sel(gsr_mask0_fx4[10:8]),
  .dout(rs2_shuf_fx3[23:16]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b6  (
  .din0(rs20_fx3[63:56]),
  .din1(rs20_fx3[55:48]),
  .din2(rs20_fx3[47:40]),
  .din3(rs20_fx3[39:32]),
  .din4(rs20_fx3[31:24]),
  .din5(rs20_fx3[23:16]),
  .din6(rs20_fx3[15:8]),
  .din7(rs20_fx3[7:0]),
  .sel(gsr_mask0_fx4[6:4]),
  .dout(rs2_shuf_fx3[15:8]) 
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b7  (
  .din0(rs20_fx3[63:56]),
  .din1(rs20_fx3[55:48]),
  .din2(rs20_fx3[47:40]),
  .din3(rs20_fx3[39:32]),
  .din4(rs20_fx3[31:24]),
  .din5(rs20_fx3[23:16]),
  .din6(rs20_fx3[15:8]),
  .din7(rs20_fx3[7:0]),
  .sel(gsr_mask0_fx4[2:0]),
  .dout(rs2_shuf_fx3[7:0]) 
  );

// ------------------------------------
// bshuffle result muxes
// ------------------------------------

fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b0  (
  .din0(rs2_shuf_fx3[63:56]),
  .din1(rs1_shuf_fx3[63:56]),
  .sel0(gsr_mask0_fx4[31]),
  .dout(shuf_result_fx3[63:56]) 
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b1  (
  .din0(rs2_shuf_fx3[55:48]),
  .din1(rs1_shuf_fx3[55:48]),
  .sel0(gsr_mask0_fx4[27]),
  .dout(shuf_result_fx3[55:48]) 
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b2  (
  .din0(rs2_shuf_fx3[47:40]),
  .din1(rs1_shuf_fx3[47:40]),
  .sel0(gsr_mask0_fx4[23]),
  .dout(shuf_result_fx3[47:40]) 
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b3  (
  .din0(rs2_shuf_fx3[39:32]),
  .din1(rs1_shuf_fx3[39:32]),
  .sel0(gsr_mask0_fx4[19]),
  .dout(shuf_result_fx3[39:32]) 
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b4  (
  .din0(rs2_shuf_fx3[31:24]),
  .din1(rs1_shuf_fx3[31:24]),
  .sel0(gsr_mask0_fx4[15]),
  .dout(shuf_result_fx3[31:24]) 
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b5  (
  .din0(rs2_shuf_fx3[23:16]),
  .din1(rs1_shuf_fx3[23:16]),
  .sel0(gsr_mask0_fx4[11]),
  .dout(shuf_result_fx3[23:16]) 
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b6  (
  .din0(rs2_shuf_fx3[15:8]),
  .din1(rs1_shuf_fx3[15:8]),
  .sel0(gsr_mask0_fx4[7]),
  .dout(shuf_result_fx3[15:8]) 
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b7  (
  .din0(rs2_shuf_fx3[7:0]),
  .din1(rs1_shuf_fx3[7:0]),
  .sel0(gsr_mask0_fx4[3]),
  .dout(shuf_result_fx3[7:0]) 
  );

// ------------------------------------
// faligndata mux
// ------------------------------------

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_64 align  (
  .din0(rs10_fx3[63:0]),
  .din1({rs10_fx3[55:0],rs20_fx3[63:56]}),
  .din2({rs10_fx3[47:0],rs20_fx3[63:48]}),
  .din3({rs10_fx3[39:0],rs20_fx3[63:40]}),
  .din4({rs10_fx3[31:0],rs20_fx3[63:32]}),
  .din5({rs10_fx3[23:0],rs20_fx3[63:24]}),
  .din6({rs10_fx3[15:0],rs20_fx3[63:16]}),
  .din7({rs10_fx3[7:0], rs20_fx3[63:8] }),
  .sel (fpc_gsr_align_fx4[2:0]),
  .dout(align_result_fx3[63:0]) 
  );

// ------------------------------------
// generate sign bit for FNEG, FABS
// ------------------------------------

fgu_fgd_dp_xnor_macro__ports_2__width_1 sign63a  (
  .din0(fgx_neg_fx3),  // negate sign bit
  .din1(rs20_fx3[63]),
  .dout(rs2_sign63_neg_fx3)
  );

fgu_fgd_dp_nor_macro__ports_2__width_1 sign63b  (
  .din0(fgx_abs_fx3),  // clear sign bit
  .din1(rs2_sign63_neg_fx3),
  .dout(rs2_sign63_res_fx3)
  );

// ------------------------------------
// simple instruction intermediate result mux
// ------------------------------------

fgu_fgd_dp_msff_macro__mux_aope__ports_6__width_64 fx4_simp  (
  .scan_in(fx4_simp_scanin),
  .scan_out(fx4_simp_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din0(logical_result_fx3[63:0]),
  .din1({4'b0000,rs201_fx3[63:56],4'b0000,
         4'b0000,rs201_fx3[55:48],4'b0000,
         4'b0000,rs201_fx3[47:40],4'b0000,
         4'b0000,rs201_fx3[39:32],4'b0000 }),
  .din2({rs101_fx3[63:56],rs201_fx3[63:56],rs101_fx3[55:48],rs201_fx3[55:48],
         rs101_fx3[47:40],rs201_fx3[47:40],rs101_fx3[39:32],rs201_fx3[39:32] }),
  .din3(align_result_fx3[63:0]),
  .din4(shuf_result_fx3[63:0]),
  .din5({rs2_sign63_res_fx3,rs201_fx3[62:0]}),
  .sel0(fgx_logical_fx3),
  .sel1(fgx_expand_fx3),
  .sel2(fgx_merge_fx3),
  .sel3(fgx_align_fx3),
  .sel4(fgx_shuffle_fx3),
                           // else: FMOV(uncond/cond), FABS, FNEG
  .dout(simp_result_fx4[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// fpack left shifter (data result)
// partitioned into four 16b shifters: [63:48],[47:32],[31:16],[15:00]
// FPACK{16,32},FPACKFIX
// ------------------------------------

fgu_fgd_dp_inv_macro__width_1 ipack16  (
  .din (fgx_pack16_fx3 ),
  .dout(fgx_pack16_fx3_)
  );

fgu_fgd_dp_nand_macro__ports_2__width_1 gsr4  (
  .din0(fpc_gsr_scale_fx4[4]),
  .din1(fgx_pack16_fx3_),  // ignore gsr_scale_fx4[4] if FPACK16
  .dout(sh16_sel_fx3)
  );

// ------------------------------------
// fpack data result
// bits [63:32]
// ------------------------------------

fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_32 pack_16_d3d2  (
  .din0( rs201_fx3[63:32]        ),   
  .din1({rs201_fx3[47:32], 16'b0}),  
  .sel0(sh16_sel_fx3),        // shift 0,16 bits
  .dout(shift16_fx3[63:32])
  );

fgu_fgd_dp_and_macro__ports_2__width_12 gate16d3  (
  .din0(shift16_fx3[47:36]),
  .din1({12{fgx_pack16_fx3_}}),
  .dout(gate16_fx3[23:12])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_04_d3  ( 
  .din0( shift16_fx3[63:48]                    ),
  .din1({shift16_fx3[59:48], gate16_fx3[23:20]}), 
  .din2({shift16_fx3[55:48], gate16_fx3[23:16]}),
  .din3({shift16_fx3[51:48], gate16_fx3[23:12]}),
  .sel (fpc_gsr_scale_fx4[3:2]),  // shift 0,4,8,12 bits
  .dout(shift04_fx3[63:48])
  );

fgu_fgd_dp_and_macro__ports_2__width_3 gate04d3  (
  .din0(shift04_fx3[47:45]),
  .din1({3{fgx_pack16_fx3_}}),
  .dout(gate04_fx3[5:3])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_01_d3  ( 
  .din0( shift04_fx3[63:48]                    ), 
  .din1({shift04_fx3[62:48], gate04_fx3[5:5]}), 
  .din2({shift04_fx3[61:48], gate04_fx3[5:4]}), 
  .din3({shift04_fx3[60:48], gate04_fx3[5:3]}),  
  .sel (fpc_gsr_scale_fx4[1:0]),  // shift 0,1,2,3 bits
  .dout(shift01_fx3[63:48])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_04_d2  ( 
  .din0( shift16_fx3[47:32]        ),
  .din1({shift16_fx3[43:32],  4'b0}), 
  .din2({shift16_fx3[39:32],  8'b0}),
  .din3({shift16_fx3[35:32], 12'b0}),
  .sel (fpc_gsr_scale_fx4[3:2]),  // shift 0,4,8,12 bits
  .dout(shift04_fx3[47:32])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_01_d2  ( 
  .din0( shift04_fx3[47:32]       ), 
  .din1({shift04_fx3[46:32], 1'b0}),
  .din2({shift04_fx3[45:32], 2'b0}), 
  .din3({shift04_fx3[44:32], 3'b0}),  
  .sel (fpc_gsr_scale_fx4[1:0]),  // shift 0,1,2,3 bits
  .dout({shift01_fx3[47:39], pack_01_d2_unused[6:0]})
  );

// ------------------------------------
// fpack data result
// bits [31:00]
// ------------------------------------

fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_32 pack_16_d1d0  (
  .din0( rs201_fx3[31:0]        ),
  .din1({rs201_fx3[15:0], 16'b0}),  
  .sel0(sh16_sel_fx3),        // shift 0,16 bits
  .dout(shift16_fx3[31:0])
  );

fgu_fgd_dp_and_macro__ports_2__width_12 gate16d1  (
  .din0(shift16_fx3[15:4]),
  .din1({12{fgx_pack16_fx3_}}),
  .dout(gate16_fx3[11:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_04_d1  ( 
  .din0( shift16_fx3[31:16]                    ),
  .din1({shift16_fx3[27:16], gate16_fx3[11:8]}), 
  .din2({shift16_fx3[23:16], gate16_fx3[11:4]}),
  .din3({shift16_fx3[19:16], gate16_fx3[11:0]}),
  .sel (fpc_gsr_scale_fx4[3:2]),  // shift 0,4,8,12 bits
  .dout(shift04_fx3[31:16])
  );

fgu_fgd_dp_and_macro__ports_2__width_3 gate04d1  (
  .din0(shift04_fx3[15:13]),
  .din1({3{fgx_pack16_fx3_}}),
  .dout(gate04_fx3[2:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_01_d1  ( 
  .din0( shift04_fx3[31:16]                    ),
  .din1({shift04_fx3[30:16], gate04_fx3[2:2]}), 
  .din2({shift04_fx3[29:16], gate04_fx3[2:1]}), 
  .din3({shift04_fx3[28:16], gate04_fx3[2:0]}),  
  .sel (fpc_gsr_scale_fx4[1:0]),  // shift 0,1,2,3 bits
  .dout(shift01_fx3[31:16])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_04_d0  ( 
  .din0( shift16_fx3[15:0]        ),
  .din1({shift16_fx3[11:0],  4'b0}), 
  .din2({shift16_fx3[7:0],  8'b0}),
  .din3({shift16_fx3[3:0], 12'b0}),
  .sel (fpc_gsr_scale_fx4[3:2]),  // shift 0,4,8,12 bits
  .dout(shift04_fx3[15:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_01_d0  ( 
  .din0( shift04_fx3[15:0]       ),
  .din1({shift04_fx3[14:0], 1'b0}),
  .din2({shift04_fx3[13:0], 2'b0}), 
  .din3({shift04_fx3[12:0], 3'b0}),  
  .sel (fpc_gsr_scale_fx4[1:0]),  // shift 0,1,2,3 bits
  .dout({shift01_fx3[15:7], pack_01_d0_unused[6:0]})
  );

// ------------------------------------
// fpack collection of shifted off (clipping) data
// used to determine if const data output is required
// FPACK{16,32},FPACKFIX
// ------------------------------------

// ------------------------------------
// fpack clipping result
// bits [63:32]
// ------------------------------------

fgu_fgd_dp_and_macro__ports_2__width_1 packsign63  (
  .din0(rs201_fx3[63]),
  .din1(fgx_packfix_fx3),
  .dout(pack_sign63_fx3)
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_16 pack_16_c3c2  (
  .din0({16{pack_sign63_fx3}}),   
  .din1(rs201_fx3[63:48]),  
  .sel0(sh16_sel_fx3),        // shift 0,16 bits
  .dout(clip16_c3_fx3[15:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_28 pack_04_c3  ( 
  .din0({{12{pack_sign63_fx3}}, clip16_c3_fx3[15:0]                    }),
  .din1({{ 8{pack_sign63_fx3}}, clip16_c3_fx3[15:0], shift16_fx3[63:60]}), 
  .din2({{ 4{pack_sign63_fx3}}, clip16_c3_fx3[15:0], shift16_fx3[63:56]}),
  .din3({                       clip16_c3_fx3[15:0], shift16_fx3[63:52]}),
  .sel (fpc_gsr_scale_fx4[3:2]),  // shift 0,4,8,12 bits
  .dout(clip04_c3_fx3[27:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_31 pack_01_c3  ( 
  .din0({{3{pack_sign63_fx3}}, clip04_c3_fx3[27:0]                    }), 
  .din1({{2{pack_sign63_fx3}}, clip04_c3_fx3[27:0], shift04_fx3[63:63]}), 
  .din2({{1{pack_sign63_fx3}}, clip04_c3_fx3[27:0], shift04_fx3[63:62]}), 
  .din3({                      clip04_c3_fx3[27:0], shift04_fx3[63:61]}),  
  .sel (fpc_gsr_scale_fx4[1:0]),  // shift 0,1,2,3 bits
  .dout(clip01_c3_fx3[30:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_12 pack_04_c2  ( 
  .din0( 12'b0                     ),
  .din1({ 8'b0, shift16_fx3[47:44]}), 
  .din2({ 4'b0, shift16_fx3[47:40]}),
  .din3(        shift16_fx3[47:36] ),
  .sel (fpc_gsr_scale_fx4[3:2]),  // shift 0,4,8,12 bits
  .dout(clip04_c2_fx3[11:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_15 pack_01_c2  ( 
  .din0({3'b0, clip04_c2_fx3[11:0]                    }), 
  .din1({2'b0, clip04_c2_fx3[11:0], shift04_fx3[47:47]}),
  .din2({1'b0, clip04_c2_fx3[11:0], shift04_fx3[47:46]}), 
  .din3({      clip04_c2_fx3[11:0], shift04_fx3[47:45]}),  
  .sel (fpc_gsr_scale_fx4[1:0]),  // shift 0,1,2,3 bits
  .dout(clip01_c2_fx3[14:0])
  );

// ------------------------------------
// fpack clipping result
// bits [31:00]
// ------------------------------------

fgu_fgd_dp_and_macro__ports_2__width_1 packsign31  (
  .din0(rs201_fx3[31]),
  .din1(fgx_packfix_fx3),
  .dout(pack_sign31_fx3)
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_16 pack_16_c1c0  (
  .din0({16{pack_sign31_fx3}}),   
  .din1(rs201_fx3[31:16]),  
  .sel0(sh16_sel_fx3),        // shift 0,16 bits
  .dout(clip16_c1_fx3[15:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_28 pack_04_c1  ( 
  .din0({{12{pack_sign31_fx3}}, clip16_c1_fx3[15:0]                    }),
  .din1({{ 8{pack_sign31_fx3}}, clip16_c1_fx3[15:0], shift16_fx3[31:28]}), 
  .din2({{ 4{pack_sign31_fx3}}, clip16_c1_fx3[15:0], shift16_fx3[31:24]}),
  .din3({                       clip16_c1_fx3[15:0], shift16_fx3[31:20]}),
  .sel (fpc_gsr_scale_fx4[3:2]),  // shift 0,4,8,12 bits
  .dout(clip04_c1_fx3[27:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_31 pack_01_c1  ( 
  .din0({{3{pack_sign31_fx3}}, clip04_c1_fx3[27:0]                    }), 
  .din1({{2{pack_sign31_fx3}}, clip04_c1_fx3[27:0], shift04_fx3[31:31]}), 
  .din2({{1{pack_sign31_fx3}}, clip04_c1_fx3[27:0], shift04_fx3[31:30]}), 
  .din3({                      clip04_c1_fx3[27:0], shift04_fx3[31:29]}),  
  .sel (fpc_gsr_scale_fx4[1:0]),  // shift 0,1,2,3 bits
  .dout(clip01_c1_fx3[30:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_12 pack_04_c0  ( 
  .din0( 12'b0                     ),
  .din1({ 8'b0, shift16_fx3[15:12]}), 
  .din2({ 4'b0, shift16_fx3[15:8]}),
  .din3(        shift16_fx3[15:4] ),
  .sel (fpc_gsr_scale_fx4[3:2]),  // shift 0,4,8,12 bits
  .dout(clip04_c0_fx3[11:0])
  );

fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_15 pack_01_c0  ( 
  .din0({3'b0, clip04_c0_fx3[11:0]                    }), 
  .din1({2'b0, clip04_c0_fx3[11:0], shift04_fx3[15:15]}),
  .din2({1'b0, clip04_c0_fx3[11:0], shift04_fx3[15:14]}), 
  .din3({      clip04_c0_fx3[11:0], shift04_fx3[15:13]}),  
  .sel (fpc_gsr_scale_fx4[1:0]),  // shift 0,1,2,3 bits
  .dout(clip01_c0_fx3[14:0])
  );

// ------------------------------------
// PDIST,POPC
// ------------------------------------

// ------------------------------------
// uniquie PDIST frontend (fx3)
// subtract (rs1 - rs2)
// ------------------------------------

fgu_fgd_dp_cla_macro__width_8 pdist_amb0  (
  .din0(rs101_fx3[63:56] ),
  .din1(rs201_fx3_[63:56]),
  .cin (1'b1),
  .dout(pdist_amb_fx3[63:56]),
  .cout(pdist_amb_cout0_fx3)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_amb1  (
  .din0(rs101_fx3[55:48] ),
  .din1(rs201_fx3_[55:48]),
  .cin (1'b1),
  .dout(pdist_amb_fx3[55:48]),
  .cout(pdist_amb_cout1_fx3)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_amb2  (
  .din0(rs101_fx3[47:40] ),
  .din1(rs201_fx3_[47:40]),
  .cin (1'b1),
  .dout(pdist_amb_fx3[47:40]),
  .cout(pdist_amb_cout2_fx3)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_amb3  (
  .din0(rs101_fx3[39:32] ),
  .din1(rs201_fx3_[39:32]),
  .cin (1'b1),
  .dout(pdist_amb_fx3[39:32]),
  .cout(pdist_amb_cout3_fx3)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_amb4  (
  .din0(rs101_fx3[31:24] ),
  .din1(rs201_fx3_[31:24]),
  .cin (1'b1),
  .dout(pdist_amb_fx3[31:24]),
  .cout(pdist_amb_cout4_fx3)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_amb5  (
  .din0(rs101_fx3[23:16] ),
  .din1(rs201_fx3_[23:16]),
  .cin (1'b1),
  .dout(pdist_amb_fx3[23:16]),
  .cout(pdist_amb_cout5_fx3)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_amb6  (
  .din0(rs101_fx3[15:8] ),
  .din1(rs201_fx3_[15:8]),
  .cin (1'b1),
  .dout(pdist_amb_fx3[15:8]),
  .cout(pdist_amb_cout6_fx3)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_amb7  (
  .din0(rs101_fx3[7:0] ),
  .din1(rs201_fx3_[7:0]),
  .cin (1'b1),
  .dout(pdist_amb_fx3[7:0]),
  .cout(pdist_amb_cout7_fx3)
  );

// ------------------------------------
// uniquie PDIST frontend (fx3)
// subtract (rs2 - rs1)
// ------------------------------------

fgu_fgd_dp_cla_macro__width_8 pdist_bma0  (
  .din0(rs201_fx3[63:56] ),
  .din1(rs101_fx3_[63:56]),
  .cin (1'b1),
  .dout(pdist_bma_fx3[63:56]),
  .cout(pdist_bma0_unused)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_bma1  (
  .din0(rs201_fx3[55:48] ),
  .din1(rs101_fx3_[55:48]),
  .cin (1'b1),
  .dout(pdist_bma_fx3[55:48]),
  .cout(pdist_bma1_unused)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_bma2  (
  .din0(rs201_fx3[47:40] ),
  .din1(rs101_fx3_[47:40]),
  .cin (1'b1),
  .dout(pdist_bma_fx3[47:40]),
  .cout(pdist_bma2_unused)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_bma3  (
  .din0(rs201_fx3[39:32] ),
  .din1(rs101_fx3_[39:32]),
  .cin (1'b1),
  .dout(pdist_bma_fx3[39:32]),
  .cout(pdist_bma3_unused)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_bma4  (
  .din0(rs201_fx3[31:24] ),
  .din1(rs101_fx3_[31:24]),
  .cin (1'b1),
  .dout(pdist_bma_fx3[31:24]),
  .cout(pdist_bma4_unused)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_bma5  (
  .din0(rs201_fx3[23:16] ),
  .din1(rs101_fx3_[23:16]),
  .cin (1'b1),
  .dout(pdist_bma_fx3[23:16]),
  .cout(pdist_bma5_unused)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_bma6  (
  .din0(rs201_fx3[15:8] ),
  .din1(rs101_fx3_[15:8]),
  .cin (1'b1),
  .dout(pdist_bma_fx3[15:8]),
  .cout(pdist_bma6_unused)
  );

fgu_fgd_dp_cla_macro__width_8 pdist_bma7  (
  .din0(rs201_fx3[7:0] ),
  .din1(rs101_fx3_[7:0]),
  .cin (1'b1),
  .dout(pdist_bma_fx3[7:0]),
  .cout(pdist_bma7_unused)
  );

// ------------------------------------
// select PDIST or POPC
// to proceed to the common backend
// ------------------------------------

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux0  (
  .din0({4'b0, popc_byte0_sum_fx3[3:0]}),
  .din1(pdist_amb_fx3[63:56]),
  .din2(pdist_bma_fx3[63:56]),
  .sel0(fgx_popc_fx3),
  .sel1(pdist_amb_cout0_fx3),
  .dout(pdist_mux_fx3[63:56])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux1  (
  .din0({4'b0, popc_byte1_sum_fx3[3:0]}),
  .din1(pdist_amb_fx3[55:48]),
  .din2(pdist_bma_fx3[55:48]),
  .sel0(fgx_popc_fx3),
  .sel1(pdist_amb_cout1_fx3),
  .dout(pdist_mux_fx3[55:48])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux2  (
  .din0({4'b0, popc_byte2_sum_fx3[3:0]}),
  .din1(pdist_amb_fx3[47:40]),
  .din2(pdist_bma_fx3[47:40]),
  .sel0(fgx_popc_fx3),
  .sel1(pdist_amb_cout2_fx3),
  .dout(pdist_mux_fx3[47:40])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux3  (
  .din0({4'b0, popc_byte3_sum_fx3[3:0]}),
  .din1(pdist_amb_fx3[39:32]),
  .din2(pdist_bma_fx3[39:32]),
  .sel0(fgx_popc_fx3),
  .sel1(pdist_amb_cout3_fx3),
  .dout(pdist_mux_fx3[39:32])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux4  (
  .din0({4'b0, popc_byte4_sum_fx3[3:0]}),
  .din1(pdist_amb_fx3[31:24]),
  .din2(pdist_bma_fx3[31:24]),
  .sel0(fgx_popc_fx3),
  .sel1(pdist_amb_cout4_fx3),
  .dout(pdist_mux_fx3[31:24])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux5  (
  .din0({4'b0, popc_byte5_sum_fx3[3:0]}),
  .din1(pdist_amb_fx3[23:16]),
  .din2(pdist_bma_fx3[23:16]),
  .sel0(fgx_popc_fx3),
  .sel1(pdist_amb_cout5_fx3),
  .dout(pdist_mux_fx3[23:16])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux6  (
  .din0({4'b0, popc_byte6_sum_fx3[3:0]}),
  .din1(pdist_amb_fx3[15:8]),
  .din2(pdist_bma_fx3[15:8]),
  .sel0(fgx_popc_fx3),
  .sel1(pdist_amb_cout6_fx3),
  .dout(pdist_mux_fx3[15:8])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux7  (
  .din0({4'b0, popc_byte7_sum_fx3[3:0]}),
  .din1(pdist_amb_fx3[7:0]),
  .din2(pdist_bma_fx3[7:0]),
  .sel0(fgx_popc_fx3),
  .sel1(pdist_amb_cout7_fx3),
  .dout(pdist_mux_fx3[7:0])
  );

// ------------------------------------
// common PDIST,POPC backend (fx3)
// begin compression of 8 8-bit values
// ------------------------------------

fgu_fgd_dp_csa42_macro__width_8 pdist_42csa_0  (
  .i0   (pdist_mux_fx3[7:0]),
  .i1   (pdist_mux_fx3[15:8]),
  .i2   (pdist_mux_fx3[23:16]),
  .i3   (pdist_mux_fx3[31:24]),
  .cin  (1'b0                ),
  .cout (pdist_42csa_cout0_fx3        ), 
  .carry(pdist_42csa_carry0_fx3[8:1]),
  .sum  (pdist_42csa_sum0_fx3[7:0]  )  
  );

fgu_fgd_dp_csa42_macro__width_8 pdist_42csa_1  (
  .i0   (pdist_mux_fx3[39:32]),
  .i1   (pdist_mux_fx3[47:40]),
  .i2   (pdist_mux_fx3[55:48]),
  .i3   (pdist_mux_fx3[63:56]),
  .cin  (1'b0                ),
  .cout (pdist_42csa_cout1_fx3        ), 
  .carry(pdist_42csa_carry1_fx3[8:1]),
  .sum  (pdist_42csa_sum1_fx3[7:0]  )  
  );

// ----------------------------------------------------------------------------
//                               FX4 stage
// ----------------------------------------------------------------------------

fgu_fgd_dp_msff_macro__width_48 fx4_rs1  (
  .scan_in(fx4_rs1_scanin),
  .scan_out(fx4_rs1_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din ({rs101_fx3[55:32], rs101_fx3[23:0]}),
  .dout({rs1_fx4[55:32],   rs1_fx4[23:0] }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__width_50 fx4_shift  (
  .scan_in(fx4_shift_scanin),
  .scan_out(fx4_shift_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din ({shift01_fx3[63:39], shift01_fx3[31:7]}),
  .dout({shift01_fx4[63:39], shift01_fx4[31:7]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__width_62 fx4_clipa  (
  .scan_in(fx4_clipa_scanin),
  .scan_out(fx4_clipa_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din ({clip01_c3_fx3[30:0],clip01_c1_fx3[30:0]}),
  .dout({clip01_c3_fx4[30:0],clip01_c1_fx4[30:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__width_37 fx4_clipb  (
  .scan_in(fx4_clipb_scanin),
  .scan_out(fx4_clipb_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din ({rs201_fx3[63],
         rs201_fx3[47],
         clip01_c2_fx3[14:0],clip01_c0_fx3[14:0],
         rs201_fx3[31],
         rs201_fx3[15],
         fgx_packfix_fx3,fgx_pack32_fx3,fgx_pack16_fx3}),
  .dout({rs2_fx4_b63,
         rs2_fx4_b47,
         clip01_c2_fx4[14:0],clip01_c0_fx4[14:0],
         rs2_fx4_b31,
         rs2_fx4_b15,
         fgx_packfix_fx4,fgx_pack32_fx4,fgx_pack16_fx4}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__width_34 fx4_pdist  (
  .scan_in(fx4_pdist_scanin),
  .scan_out(fx4_pdist_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din ({pdist_42csa_cout0_fx3,
         pdist_42csa_cout1_fx3,
         pdist_42csa_carry0_fx3[8:1],
         pdist_42csa_sum0_fx3[7:0],
         pdist_42csa_carry1_fx3[8:1],
         pdist_42csa_sum1_fx3[7:0]   }),
  .dout( pdist_42csa_data_fx4[33:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)   
  );

// ------------------------------------
// GSR.mask flops, threads 0-7
// ------------------------------------

fgu_fgd_dp_msff_macro__stack_32l__width_6 fx4_gsrtid  (
  .scan_in(fx4_gsrtid_scanin),
  .scan_out(fx4_gsrtid_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din ({fac_gsr_asr_tid_fx2[2:0], fac_tid_fx2[2:0]}),
  .dout({    gsr_asr_tid_fx3[2:0],     tid_fx3[2:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr0mask  (	// FS:wmr_protect
  .scan_in(fx4_gsr0mask_wmr_scanin),
  .scan_out(fx4_gsr0mask_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fpc_gsr0_mask_sel_fx3[1]),
  .din0(gsr_mask_fx3[31:0]),
  .din1(in_rngl_cdbus_3f[63:32]),
  .sel0(fpc_gsr0_mask_sel_fx3[0]),
  .dout(gsr0_mask_fx4[31:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr1mask  (	// FS:wmr_protect
  .scan_in(fx4_gsr1mask_wmr_scanin),
  .scan_out(fx4_gsr1mask_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fpc_gsr1_mask_sel_fx3[1]),
  .din0(gsr_mask_fx3[31:0]),
  .din1(in_rngl_cdbus_3f[63:32]),
  .sel0(fpc_gsr1_mask_sel_fx3[0]),
  .dout(gsr1_mask_fx4[31:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr2mask  (	// FS:wmr_protect
  .scan_in(fx4_gsr2mask_wmr_scanin),
  .scan_out(fx4_gsr2mask_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fpc_gsr2_mask_sel_fx3[1]),
  .din0(gsr_mask_fx3[31:0]),
  .din1(in_rngl_cdbus_3f[63:32]),
  .sel0(fpc_gsr2_mask_sel_fx3[0]),
  .dout(gsr2_mask_fx4[31:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr3mask  (	// FS:wmr_protect
  .scan_in(fx4_gsr3mask_wmr_scanin),
  .scan_out(fx4_gsr3mask_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fpc_gsr3_mask_sel_fx3[1]),
  .din0(gsr_mask_fx3[31:0]),
  .din1(in_rngl_cdbus_3f[63:32]),
  .sel0(fpc_gsr3_mask_sel_fx3[0]),
  .dout(gsr3_mask_fx4[31:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr4mask  (	// FS:wmr_protect
  .scan_in(fx4_gsr4mask_wmr_scanin),
  .scan_out(fx4_gsr4mask_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fpc_gsr4_mask_sel_fx3[1]),
  .din0(gsr_mask_fx3[31:0]),
  .din1(in_rngl_cdbus_3f[63:32]),
  .sel0(fpc_gsr4_mask_sel_fx3[0]),
  .dout(gsr4_mask_fx4[31:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr5mask  (	// FS:wmr_protect
  .scan_in(fx4_gsr5mask_wmr_scanin),
  .scan_out(fx4_gsr5mask_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fpc_gsr5_mask_sel_fx3[1]),
  .din0(gsr_mask_fx3[31:0]),
  .din1(in_rngl_cdbus_3f[63:32]),
  .sel0(fpc_gsr5_mask_sel_fx3[0]),
  .dout(gsr5_mask_fx4[31:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr6mask  (	// FS:wmr_protect
  .scan_in(fx4_gsr6mask_wmr_scanin),
  .scan_out(fx4_gsr6mask_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fpc_gsr6_mask_sel_fx3[1]),
  .din0(gsr_mask_fx3[31:0]),
  .din1(in_rngl_cdbus_3f[63:32]),
  .sel0(fpc_gsr6_mask_sel_fx3[0]),
  .dout(gsr6_mask_fx4[31:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr7mask  (	// FS:wmr_protect
  .scan_in(fx4_gsr7mask_wmr_scanin),
  .scan_out(fx4_gsr7mask_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .se(lb_scan_en_wmr),
  .clk (l2clk),
  .en  (fpc_gsr7_mask_sel_fx3[1]),
  .din0(gsr_mask_fx3[31:0]),
  .din1(in_rngl_cdbus_3f[63:32]),
  .sel0(fpc_gsr7_mask_sel_fx3[0]),
  .dout(gsr7_mask_fx4[31:0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// GSR.mask thread 0-7 mux
// ------------------------------------

fgu_fgd_dp_mux_macro__mux_aodec__ports_8__stack_32l__width_32 mux_gsr  (
  .din0(gsr0_mask_fx4[31:0]),
  .din1(gsr1_mask_fx4[31:0]),
  .din2(gsr2_mask_fx4[31:0]),
  .din3(gsr3_mask_fx4[31:0]),
  .din4(gsr4_mask_fx4[31:0]),
  .din5(gsr5_mask_fx4[31:0]),
  .din6(gsr6_mask_fx4[31:0]),
  .din7(gsr7_mask_fx4[31:0]),
  .sel (tid_fx3[2:0]),
  .dout(gsr_mask_fx4[31:0])
  );

fgu_fgd_dp_buff_macro__stack_32l__width_32 buf_gsr  (
  .din (gsr_mask_fx4[31:0]),
  .dout(gsr_mask0_fx4[31:0])
  );

fgu_fgd_dp_buff_macro__dbuff_48x__stack_32l__width_1 muxtest_a_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_a_rep0)
  );

fgu_fgd_dp_mux_macro__mux_pgdec__ports_8__stack_32l__width_32 mux_gsrasr  (
  .muxtst(tcu_muxtest_a_rep0),
  .din0(gsr0_mask_fx4[31:0]),
  .din1(gsr1_mask_fx4[31:0]),
  .din2(gsr2_mask_fx4[31:0]),
  .din3(gsr3_mask_fx4[31:0]),
  .din4(gsr4_mask_fx4[31:0]),
  .din5(gsr5_mask_fx4[31:0]),
  .din6(gsr6_mask_fx4[31:0]),
  .din7(gsr7_mask_fx4[31:0]),
  .sel (gsr_asr_tid_fx3[2:0]),
  .dout({fgd_gsr_asr_mask_fx4_b31, gsr_asr_mask_fx4[30:0]}),
  .test(test)
  );

// ------------------------------------
// fpack result const detection
// FPACK{16,32},FPACKFIX
// ------------------------------------

fgu_fgd_dp_zero_macro__width_32 pack_cmp3  (
 .din ({clip01_c3_fx4[30:0],shift01_fx4[63]}),
 .dout(pack_b01_gt255_fx4_)   // FPACK16:  bits [30:15] == 0, not >    255
 );                           // FPACK32:  bits [62:31] == 0, not >    255
                              // FPACKFIX: bits [62:31] == 0, not >  32767

fgu_fgd_dp_cmp_macro__width_32 packfix_cmp3  (
 .din0({clip01_c3_fx4[30:0],shift01_fx4[63]}),
 .din1(32'hffffffff),
 .dout(pack_b01_lt32768_fx4_) // FPACKFIX: bits [62:31] == 1, not < -32768
 ); 

fgu_fgd_dp_zero_macro__width_16 pack_cmp2  (
 .din ({clip01_c2_fx4[14:0],shift01_fx4[47]}),
 .dout(pack_b23_gt255_fx4_)   // FPACK16:  bits [30:15] == 0, not >    255
 );

fgu_fgd_dp_zero_macro__width_32 pack_cmp1  (
 .din ({clip01_c1_fx4[30:0],shift01_fx4[31]}),
 .dout(pack_b45_gt255_fx4_)   // FPACK16:  bits [30:15] == 0, not >    255
 );                           // FPACK32:  bits [62:31] == 0, not >    255
                              // FPACKFIX: bits [62:31] == 0, not >  32767

fgu_fgd_dp_cmp_macro__width_32 packfix_cmp1  (
 .din0({clip01_c1_fx4[30:0],shift01_fx4[31]}),
 .din1(32'hffffffff),
 .dout(pack_b45_lt32768_fx4_) // FPACKFIX: bits [62:31] == 1, not < -32768
 ); 

fgu_fgd_dp_zero_macro__width_16 pack_cmp0  (
 .din ({clip01_c0_fx4[14:0],shift01_fx4[15]}),
 .dout(pack_b67_gt255_fx4_)   // FPACK16:  bits [30:15] == 0, not >    255
 );

fgu_fgd_dp_inv_macro__width_8 ipackcmp  (  // 0in bits_on -max 1 -var {packfix_hi_gt32767_fx4, packfix_hi_lt32768_fx4}; bits_on -max 1 -var {packfix_lo_gt32767_fx4, packfix_lo_lt32768_fx4}
  .din ({pack_b01_gt255_fx4_,
         pack_b01_lt32768_fx4_,
         pack_b23_gt255_fx4_,
         pack_b45_gt255_fx4_,
         pack_b45_lt32768_fx4_,
         pack_b67_gt255_fx4_,
         rs2_fx4_b63,
         rs2_fx4_b31}),
  .dout({pack_b01_gt255_fx4,
         pack_b01_lt32768_fx4,
         pack_b23_gt255_fx4,
         pack_b45_gt255_fx4,
         pack_b45_lt32768_fx4,
         pack_b67_gt255_fx4,
         rs2_fx4_b63_,
         rs2_fx4_b31_})
  );

fgu_fgd_dp_and_macro__ports_3__width_2 packsela  (
  .din0({fgx_packfix_fx4,        fgx_packfix_fx4       }),
  .din1({rs2_fx4_b63,            rs2_fx4_b31           }),  // negative
  .din2({pack_b01_lt32768_fx4,   pack_b45_lt32768_fx4  }),
  .dout({packfix_hi_lt32768_fx4, packfix_lo_lt32768_fx4})
  );

fgu_fgd_dp_and_macro__ports_3__width_2 packselb  (
  .din0({fgx_packfix_fx4,        fgx_packfix_fx4       }),
  .din1({rs2_fx4_b63_,           rs2_fx4_b31_          }),  // positive
  .din2({pack_b01_gt255_fx4,     pack_b45_gt255_fx4    }),
  .dout({packfix_hi_gt32767_fx4, packfix_lo_gt32767_fx4})
  );

fgu_fgd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 packselc  ( 
  .din0({rs2_fx4_b15,      pack_b67_gt255_fx4}),
  .din1({rs2_fx4_b63,      pack_b01_gt255_fx4}),
  .sel0(fgx_pack16_fx4),
  .sel1(fgx_pack32_fx4),
  .dout({pack_b3_sign_fx4, pack_b3_gt255_fx4})
  );

// ------------------------------------
// fpack result data/const selection
// FPACK{16,32},FPACKFIX
//
// only FPACK32 64b result updates 32 LSBs
// FPACK16/FPACKFIX 32b result updates 32 MSBs
// ------------------------------------

fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 pack_b0  ( 
  .din0(8'h80),               // portion of 16'h8000
  .din1(8'h7f),               // portion of 16'h7fff
  .din2(shift01_fx4[63:56]),  // portion of [63:48]
  .din3(rs1_fx4[55:48]),
  .din4(8'h00),
  .din5(8'hff),
  .din6(shift01_fx4[62:55]),
  .sel0(packfix_hi_lt32768_fx4),
  .sel1(packfix_hi_gt32767_fx4),
  .sel2(fgx_packfix_fx4),
  .sel3(fgx_pack32_fx4),
  .sel4(rs2_fx4_b63),         // negative
  .sel5(pack_b01_gt255_fx4),
  .dout(pack_result_fx4[63:56])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 pack_b1  ( 
  .din0(8'h00),               // portion of 16'h8000
  .din1(8'hff),               // portion of 16'h7fff
  .din2(shift01_fx4[55:48]),  // portion of [63:48]
  .din3(rs1_fx4[47:40]),
  .din4(8'h00),
  .din5(8'hff),
  .din6(shift01_fx4[46:39]),
  .sel0(packfix_hi_lt32768_fx4),
  .sel1(packfix_hi_gt32767_fx4),
  .sel2(fgx_packfix_fx4),
  .sel3(fgx_pack32_fx4),
  .sel4(rs2_fx4_b47),         // negative
  .sel5(pack_b23_gt255_fx4),
  .dout(pack_result_fx4[55:48])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 pack_b2  ( 
  .din0(8'h80),               // portion of 16'h8000
  .din1(8'h7f),               // portion of 16'h7fff
  .din2(shift01_fx4[31:24]),  // portion of [31:16]
  .din3(rs1_fx4[39:32]),
  .din4(8'h00),
  .din5(8'hff),
  .din6(shift01_fx4[30:23]),
  .sel0(packfix_lo_lt32768_fx4),
  .sel1(packfix_lo_gt32767_fx4),
  .sel2(fgx_packfix_fx4),
  .sel3(fgx_pack32_fx4),
  .sel4(rs2_fx4_b31),         // negative
  .sel5(pack_b45_gt255_fx4),
  .dout(pack_result_fx4[47:40])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 pack_b3  ( 
  .din0(8'h00),               // portion of 16'h8000
  .din1(8'hff),               // portion of 16'h7fff
  .din2(shift01_fx4[23:16]),  // portion of [31:16]
  .din3(8'h00),
  .din4(8'hff),
  .din5(shift01_fx4[62:55]),
  .din6(shift01_fx4[14:7]),
  .sel0(packfix_lo_lt32768_fx4),
  .sel1(packfix_lo_gt32767_fx4),
  .sel2(fgx_packfix_fx4),
  .sel3(pack_b3_sign_fx4),    // negative
  .sel4(pack_b3_gt255_fx4),
  .sel5(fgx_pack32_fx4),
  .dout(pack_result_fx4[39:32])
  );

fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pack_lo  ( 
  .din0(8'h00),
  .din1(8'hff),
  .din2(shift01_fx4[30:23]),
  .sel0(rs2_fx4_b31),         // negative
  .sel1(pack_b45_gt255_fx4),
  .dout(pack_result_fx4_b7_0[7:0])
  );

// ------------------------------------
// common PDIST,POPC backend (fx4)
// complete compression of 8 8-bit values (4 8-bit values remain),
// then add to rs3 if PDIST (rs3 arrives one cycle delayed on rs2)
// ------------------------------------

fgu_fgd_dp_csa42_macro__width_9 pdist_42csa_2  (
  .i0   ({      pdist_42csa_data_fx4[31:24], 1'b0              }),
  .i1   ({pdist_42csa_data_fx4[33], pdist_42csa_data_fx4[23:16]}),
  .i2   ({      pdist_42csa_data_fx4[15:8], 1'b0              }),
  .i3   ({pdist_42csa_data_fx4[32], pdist_42csa_data_fx4[7:0]}),
  .cin  ( 1'b0                         ),
  .cout ( pdist_42csa_cout2_fx4        ), 
  .carry( pdist_42csa_carry2_fx4[9:1]),
  .sum  ( pdist_42csa_sum2_fx4[8:0]  )  
  );

fgu_fgd_dp_csa32_macro__width_10 pdist_32csa  (
  .i0   ({                              pdist_rs3_fx3[9:0]}),
  .i1   ({               pdist_42csa_carry2_fx4[9:1], 1'b0}),
  .i2   ({pdist_42csa_cout2_fx4, pdist_42csa_sum2_fx4[8:0]}),
  .carry( pdist_32csa_carry_fx4[10:1]),
  .sum  ( pdist_32csa_sum_fx4[9:0]  )
  );

fgu_fgd_dp_and_macro__ports_2__width_1 pdist_and  (
  .din0(pdist_rs3_fx3[11]),
  .din1(fgx_pdist_fx4),
  .dout(q_pdist_rs3_fx3_b11) 
  );

fgu_fgd_dp_cla_macro__width_12 pdist_cla  (  // 0in maximum -val 64 -var {pdist_cout_fx4, pdist_sum_fx4[11:00]} -active (fgx_popc_fx4 & ~fgx_pdist_fx4)
  .din0({               1'b0,            pdist_32csa_carry_fx4[10:1], 1'b0}),
  .din1({q_pdist_rs3_fx3_b11, pdist_rs3_fx3[10], pdist_32csa_sum_fx4[9:0]}),
  .cin (1'b0),
  .dout(pdist_sum_fx4[11:0]),
  .cout(pdist_cout_fx4      )  // cout not possible if POPC (7-bit result max),
  );                           // cout not possible for any instr but pdist due to qual done on pdist_rs3_fx3[11]

// 0in custom -fire (pdist_cout_fx4 & ~fgx_pdist_fx4)

fgu_fgd_dp_increment_macro__width_64 pdist_inc  (
  .din ({rs201_fx3[63:12], 12'hfff}),
  .cin ( 1'b1                      ),
  .dout({pdist_sum_fx4[63:12], pdist_inc_unused[11:0]}),
  .cout( pdist_inc_unused[12]                         )
  );

// ------------------------------------
// FGD final result mux
// ------------------------------------

fgu_fgd_dp_msff_macro__mux_aope__ports_5__width_64 fx5_res  (
  .scan_in(fx5_res_scanin),
  .scan_out(fx5_res_scanout),
  .clk (l2clk),
  .en  (vis_clken),
  .din0({pack_result_fx4[63:32], rs1_fx4[23:0], pack_result_fx4_b7_0[7:0]}),
  .din1(pdist_sum_fx4[63:0]),
  .din2({rs201_fx3[63:12], pdist_sum_fx4[11:0]}),
  .din3({57'b0, pdist_sum_fx4[6:0]}),
  .din4(simp_result_fx4[63:0]),
  .sel0(fgx_pack_sel_fx4),  // FPACK16,FPACK32,FPACKFIX
  .sel1(pdist_cout_fx4  ),  // PDIST with cout from 12 LSBs
  .sel2(fgx_pdist_fx4   ),  // PDIST
  .sel3(fgx_popc_fx4    ),  // POPC
                            // else: other
  .dout(fgd_result_fx5[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------------------------------------------------------------------------
// FGU ASI local ring datapath
// - ASR GSR  access
// - ASR FPRS access
// - ASI FRF ECC access (read only)
// ----------------------------------------------------------------------------

fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng1_1f  (
  .scan_in(in_rng1_1f_scanin),
  .scan_out(in_rng1_1f_scanout),
  .clk (l2clk),
  .en  (coreon_clken),
  .din (in_rngl_cdbus[63:32]),  // requires free running clk or rng_data_1f[63] en
  .dout(in_rngl_cdbus_1f[63:32]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng0_1f  (
  .scan_in(in_rng0_1f_scanin),
  .scan_out(in_rng0_1f_scanout),
  .clk (l2clk),
  .en  (coreon_clken),
  .din (in_rngl_cdbus[31:0]),  // requires free running clk or rng_data_1f[63] en
  .dout(in_rngl_cdbus_1f[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng1_2f  (
  .scan_in(in_rng1_2f_scanin),
  .scan_out(in_rng1_2f_scanout),
  .clk (l2clk),
  .en  (asi_clken),
  .din (in_rngl_cdbus_1f[63:32]),
  .dout(in_rngl_cdbus_2f[63:32]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng0_2f  (
  .scan_in(in_rng0_2f_scanin),
  .scan_out(in_rng0_2f_scanout),
  .clk (l2clk),
  .en  (asi_clken),
  .din (in_rngl_cdbus_1f[31:0]),
  .dout(in_rngl_cdbus_2f[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng1_3f  (
  .scan_in(in_rng1_3f_scanin),
  .scan_out(in_rng1_3f_scanout),
  .clk (l2clk),
  .en  (asi_clken),
  .din (in_rngl_cdbus_2f[63:32]),
  .dout(in_rngl_cdbus_3f[63:32]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng0_3f  (
  .scan_in(in_rng0_3f_scanin),
  .scan_out(in_rng0_3f_scanout),
  .clk (l2clk),
  .en  (asi_clken),
  .din (in_rngl_cdbus_2f[31:0]),
  .dout(in_rngl_cdbus_3f[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fgd_dp_buff_macro__dbuff_48x__stack_32l__width_1 muxtest_b_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_b_rep0)
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_5__stack_32l__width_31 mux_rng1_3f  (
  .muxtst(tcu_muxtest_b_rep0),
  .din0({                            // ASR/ASI GSR/FPRS/FRF_ECC rd or wr   (ctl        )
         1'b1,                       //   set ack
         in_rngl_cdbus_3f[61:56],    //
         8'b0,                       //   clear ASI field (report no exceptions)
         in_rngl_cdbus_3f[47:32]}),  //
  .din1(gsr_asr_mask_fx4[30:0]),     // ASR GSR  read data                  (       data)
  .din2(31'b0),                      // ASR FPRS read data                  (       data)
  .din3(31'b0),                      // ASI FRF ECC read data               (       data)
  .din4(in_rngl_cdbus_3f[62:32]),    // bypass incoming ASI data unmodified (ctl or data)
  .sel0(fac_rng_rd_or_wr_3f),
  .sel1(fac_rng_rd_gsr_4f),
  .sel2(fac_rng_rd_fprs_4f),
  .sel3(fac_rng_rd_ecc_4f),
  .dout(fgd_rngl_cdbus_3f[62:32]),
  .test(test)
  );

fgu_fgd_dp_buff_macro__dbuff_48x__stack_32l__width_1 muxtest_c_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_c_rep0)
  );

fgu_fgd_dp_mux_macro__mux_pgpe__ports_4__stack_32l__width_32 mux_rng0_3f  (
  .muxtst(tcu_muxtest_c_rep0),
  .din0({4'b0,                       // ASR GSR read data                   (       data)
         fpc_gsr_asr_11bits_fx4[10],
         fpc_gsr_asr_11bits_fx4[9:8],
         17'b0,
         fpc_gsr_asr_11bits_fx4[7:3],
         fpc_gsr_asr_11bits_fx4[2:0]}),
  .din1({29'b0, fac_rng_fprs[2:0]}), // ASR FPRS read data                  (       data)
  .din2({18'b0, fec_r1_ecc_fx1[13:0]}), // ASI FRF ECC read data            (       data)
  .din3(in_rngl_cdbus_3f[31:0]),     // bypass incoming ASI data unmodified (ctl or data)
                                     // OR
                                     // ASR/ASI GSR/FPRS/FRF_ECC rd or wr   (ctl        )
  .sel0(fac_rng_rd_gsr_4f),
  .sel1(fac_rng_rd_fprs_4f),
  .sel2(fac_rng_rd_ecc_4f),
  .dout(fgd_rngl_cdbus_3f[31:0]),
  .test(test)
  );


// fixscan start:
assign fx2_rs1_scanin            = scan_in                  ;
assign fx2_rs2_scanin            = fx2_rs1_scanout          ;
assign fx2_gsr_scanin            = fx2_rs2_scanout          ;
assign fx3_rs1_scanin            = fx2_gsr_scanout          ;
assign fx3_rs2_scanin            = fx3_rs1_scanout          ;
assign fx3_gsr_mask_scanin       = fx3_rs2_scanout          ;
assign fx3_popc_scanin           = fx3_gsr_mask_scanout     ;
assign fx3_ctl_scanin            = fx3_popc_scanout         ;
assign fx4_simp_scanin           = fx3_ctl_scanout          ;
assign fx4_rs1_scanin            = fx4_simp_scanout         ;
assign fx4_shift_scanin          = fx4_rs1_scanout          ;
assign fx4_clipa_scanin          = fx4_shift_scanout        ;
assign fx4_clipb_scanin          = fx4_clipa_scanout        ;
assign fx4_pdist_scanin          = fx4_clipb_scanout        ;
assign fx4_gsrtid_scanin         = fx4_pdist_scanout        ;
assign fx5_res_scanin            = fx4_gsrtid_scanout       ;
assign in_rng1_1f_scanin         = fx5_res_scanout          ;
assign in_rng0_1f_scanin         = in_rng1_1f_scanout       ;
assign in_rng1_2f_scanin         = in_rng0_1f_scanout       ;
assign in_rng0_2f_scanin         = in_rng1_2f_scanout       ;
assign in_rng1_3f_scanin         = in_rng0_2f_scanout       ;
assign in_rng0_3f_scanin         = in_rng1_3f_scanout       ;
assign scan_out                  = in_rng0_3f_scanout       ;

assign fx4_gsr0mask_wmr_scanin   = wmr_scan_in              ;
assign fx4_gsr1mask_wmr_scanin   = fx4_gsr0mask_wmr_scanout ;
assign fx4_gsr2mask_wmr_scanin   = fx4_gsr1mask_wmr_scanout ;
assign fx4_gsr3mask_wmr_scanin   = fx4_gsr2mask_wmr_scanout ;
assign fx4_gsr4mask_wmr_scanin   = fx4_gsr3mask_wmr_scanout ;
assign fx4_gsr5mask_wmr_scanin   = fx4_gsr4mask_wmr_scanout ;
assign fx4_gsr6mask_wmr_scanin   = fx4_gsr5mask_wmr_scanout ;
assign fx4_gsr7mask_wmr_scanin   = fx4_gsr6mask_wmr_scanout ;
assign wmr_scan_out              = fx4_gsr7mask_wmr_scanout ;
// fixscan end:
endmodule  // fgu_fgd_dp


//
//   buff macro
//
//


module fgu_fgd_dp_buff_macro__dbuff_32x__rep_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__stack_32l__width_32 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [11:0] din0;
  input sel0;
  input [11:0] din1;
  input sel1;
  output [11:0] dout;


mux2s #(12)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[11:0]),
  .in1(din1[11:0]),
.dout(dout[11:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fgd_dp_csa42_macro__width_1 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [0:0]    i0;
  input  [0:0]    i1;
  input  [0:0]    i2;
  input  [0:0]    i3;
  input              cin;
  output             cout;
  output [0:0]    carry;
  output [0:0]    sum;


csa42 #(1)  d0_0 (
.cin(cin),
.in0(i0[0:0]),
.in1(i1[0:0]),
.in2(i2[0:0]),
.in3(i3[0:0]),
.cout(cout),
.carry(carry[0:0]),
.sum(sum[0:0])
);


endmodule


//
//   cla macro
//
//


module fgu_fgd_dp_cla_macro__width_4 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;
  output cout;


cla #(4)  m0_0 (
.cin(cin),
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0]),
.cout(cout)
);


endmodule


//
//   buff macro
//
//


module fgu_fgd_dp_buff_macro__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__minbuff_1__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__width_32 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__width_33 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [31:0] so;

  input [32:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [32:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(33)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[32:0]),
.si({scan_in,so[31:0]}),
.so({so[31:0],scan_out}),
.q(dout[32:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fgd_dp_inv_macro__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


inv #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fgd_dp_buff_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fgd_dp_nand_macro__ports_3__width_64 (
  din0, 
  din1, 
  din2, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  output [63:0] dout;


nand3 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.in2(din2[63:0]),
.out(dout[63:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fgd_dp_nand_macro__ports_4__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  output [63:0] dout;


nand4 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.in2(din2[63:0]),
.in3(din3[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  input [7:0] din3;
  input [7:0] din4;
  input [7:0] din5;
  input [7:0] din6;
  input [7:0] din7;
  input [2:0] sel;
  output [7:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
  .in4(din4[7:0]),
  .in5(din5[7:0]),
  .in6(din6[7:0]),
  .in7(din7[7:0]),
.dout(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [7:0] din0;
  input [7:0] din1;
  input sel0;
  output [7:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(8)  d0_0 (
  .sel(psel1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input [2:0] sel;
  output [63:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   xnor macro for ports = 2,3
//
//


module fgu_fgd_dp_xnor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xnor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module fgu_fgd_dp_nor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__mux_aope__ports_6__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc6_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5)
);

mux6s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fgd_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fgd_dp_nand_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_32 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;
  output [31:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fgd_dp_and_macro__ports_2__width_12 (
  din0, 
  din1, 
  dout);
  input [11:0] din0;
  input [11:0] din1;
  output [11:0] dout;


and2 #(12)  d0_0 (
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout[11:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [15:0] din0;
  input [15:0] din1;
  input [15:0] din2;
  input [15:0] din3;
  input [1:0] sel;
  output [15:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(16)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
  .in2(din2[15:0]),
  .in3(din3[15:0]),
.dout(dout[15:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fgd_dp_and_macro__ports_2__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


and2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fgd_dp_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_16 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [15:0] din0;
  input [15:0] din1;
  input sel0;
  output [15:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(16)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
.dout(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_28 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [27:0] din0;
  input [27:0] din1;
  input [27:0] din2;
  input [27:0] din3;
  input [1:0] sel;
  output [27:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(28)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[27:0]),
  .in1(din1[27:0]),
  .in2(din2[27:0]),
  .in3(din3[27:0]),
.dout(dout[27:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_31 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [30:0] din0;
  input [30:0] din1;
  input [30:0] din2;
  input [30:0] din3;
  input [1:0] sel;
  output [30:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(31)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[30:0]),
  .in1(din1[30:0]),
  .in2(din2[30:0]),
  .in3(din3[30:0]),
.dout(dout[30:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_12 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [11:0] din0;
  input [11:0] din1;
  input [11:0] din2;
  input [11:0] din3;
  input [1:0] sel;
  output [11:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(12)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[11:0]),
  .in1(din1[11:0]),
  .in2(din2[11:0]),
  .in3(din3[11:0]),
.dout(dout[11:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_15 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [14:0] din0;
  input [14:0] din1;
  input [14:0] din2;
  input [14:0] din3;
  input [1:0] sel;
  output [14:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(15)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[14:0]),
  .in1(din1[14:0]),
  .in2(din2[14:0]),
  .in3(din3[14:0]),
.dout(dout[14:0])
);


endmodule


//
//   cla macro
//
//


module fgu_fgd_dp_cla_macro__width_8 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;
  output cout;


cla #(8)  m0_0 (
.cin(cin),
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0]),
.cout(cout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  input sel0;
  input sel1;
  output [7:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
.dout(dout[7:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fgd_dp_csa42_macro__width_8 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [7:0]    i0;
  input  [7:0]    i1;
  input  [7:0]    i2;
  input  [7:0]    i3;
  input              cin;
  output             cout;
  output [7:0]    carry;
  output [7:0]    sum;


csa42 #(8)  d0_0 (
.cin(cin),
.in0(i0[7:0]),
.in1(i1[7:0]),
.in2(i2[7:0]),
.in3(i3[7:0]),
.cout(cout),
.carry(carry[7:0]),
.sum(sum[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__width_50 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [48:0] so;

  input [49:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [49:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(50)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[49:0]),
.si({scan_in,so[48:0]}),
.so({so[48:0],scan_out}),
.q(dout[49:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__width_62 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [60:0] so;

  input [61:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [61:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(62)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[61:0]),
.si({scan_in,so[60:0]}),
.so({so[60:0],scan_out}),
.q(dout[61:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__width_37 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [35:0] so;

  input [36:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [36:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__width_34 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [32:0] so;

  input [33:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [33:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(34)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[33:0]),
.si({scan_in,so[32:0]}),
.so({so[32:0],scan_out}),
.q(dout[33:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__stack_32l__width_6 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [4:0] so;

  input [5:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [5:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [31:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(32)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(muxout[31:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aodec__ports_8__stack_32l__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input [31:0] din4;
  input [31:0] din5;
  input [31:0] din6;
  input [31:0] din7;
  input [2:0] sel;
  output [31:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
  .in5(din5[31:0]),
  .in6(din6[31:0]),
  .in7(din7[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fgd_dp_buff_macro__stack_32l__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fgd_dp_buff_macro__dbuff_48x__stack_32l__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_pgdec__ports_8__stack_32l__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input [31:0] din4;
  input [31:0] din5;
  input [31:0] din6;
  input [31:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [31:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
  .in5(din5[31:0]),
  .in6(din6[31:0]),
  .in7(din7[31:0]),
.dout(dout[31:0]),
  .muxtst(muxtst)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fgd_dp_zero_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


zero #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fgd_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fgd_dp_zero_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


zero #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module fgu_fgd_dp_inv_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fgd_dp_and_macro__ports_3__width_2 (
  din0, 
  din1, 
  din2, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  input [1:0] din2;
  output [1:0] dout;


and3 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.in2(din2[1:0]),
.out(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [1:0] din0;
  input sel0;
  input [1:0] din1;
  input sel1;
  output [1:0] dout;


mux2s #(2)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[1:0]),
  .in1(din1[1:0]),
.dout(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;

  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  input [7:0] din3;
  input [7:0] din4;
  input [7:0] din5;
  input [7:0] din6;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  output [7:0] dout;


cl_dp1_penc7_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6)
);

mux7s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
  .in4(din4[7:0]),
  .in5(din5[7:0]),
  .in6(din6[7:0]),
.dout(dout[7:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fgd_dp_csa42_macro__width_9 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [8:0]    i0;
  input  [8:0]    i1;
  input  [8:0]    i2;
  input  [8:0]    i3;
  input              cin;
  output             cout;
  output [8:0]    carry;
  output [8:0]    sum;


csa42 #(9)  d0_0 (
.cin(cin),
.in0(i0[8:0]),
.in1(i1[8:0]),
.in2(i2[8:0]),
.in3(i3[8:0]),
.cout(cout),
.carry(carry[8:0]),
.sum(sum[8:0])
);


endmodule


//
//      3:2 Carry Save Adder
//
//


// any PARAMS parms go into naming of macro


module fgu_fgd_dp_csa32_macro__width_10 (
  i0, 
  i1, 
  i2, 
  carry, 
  sum);
  input  [9:0] i0;
  input  [9:0] i1;
  input  [9:0] i2;
  output [9:0] carry;
  output [9:0] sum;


csa32 #(10)  d0_0 (
.in0(i0[9:0]),
.in1(i1[9:0]),
.in2(i2[9:0]),
.carry(carry[9:0]),
.sum(sum[9:0])
);


endmodule


//
//   cla macro
//
//


module fgu_fgd_dp_cla_macro__width_12 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [11:0] din0;
  input [11:0] din1;
  output [11:0] dout;
  output cout;


cla #(12)  m0_0 (
.cin(cin),
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout[11:0]),
.cout(cout)
);


endmodule


//
//   increment macro 
//
//


module fgu_fgd_dp_increment_macro__width_64 (
  din, 
  cin, 
  dout, 
  cout);
  input [63:0] din;
  input cin;
  output [63:0] dout;
  output cout;


incr #(64)  m0_0 (
.cin(cin),
.in(din[63:0]),
.out(dout[63:0]),
.cout(cout)
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_msff_macro__mux_aope__ports_5__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_pgpe__ports_5__stack_32l__width_31 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;

  input [30:0] din0;
  input [30:0] din1;
  input [30:0] din2;
  input [30:0] din3;
  input [30:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input muxtst;
  input test;
  output [30:0] dout;


cl_dp1_penc5_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
  .test(test)
);

mux5 #(31)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[30:0]),
  .in1(din1[30:0]),
  .in2(din2[30:0]),
  .in3(din3[30:0]),
  .in4(din4[30:0]),
.dout(dout[30:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fgd_dp_mux_macro__mux_pgpe__ports_4__stack_32l__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input sel0;
  input sel1;
  input sel2;
  input muxtst;
  input test;
  output [31:0] dout;


cl_dp1_penc4_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
  .test(test)
);

mux4 #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
.dout(dout[31:0]),
  .muxtst(muxtst)
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fic_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fic_ctl (
  fpf_rs2_cmp_din_fx1, 
  fpf_ma_sum_fx4, 
  fpf_man_se_byte_fx3_b38_32, 
  fpf_man_se_byte_fx3_b6_0, 
  fic_norm_eadj_fx5, 
  fic_i2f_align_sel_fx2, 
  fpe_align_sel_fx2, 
  fic_i2f_eadj_fx2, 
  fpc_lzd_override_fx4, 
  fpc_sp_source_fx3, 
  fic_mulscc_iccz_fx4, 
  fic_mulscc_xccz_fx4, 
  fic_convert_sticky_fx4, 
  fic_fxtod_sticky_fx4, 
  fic_ftoi_nx_fx4, 
  fic_ftox_nx_fx4, 
  fic_bzf31msb_fx2, 
  fic_bzf32lsb_fx2, 
  fic_bof22msb_fx2, 
  main_clken, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk_pm1;
wire spares_scanin;
wire spares_scanout;
wire bzf31msb_fx1;
wire bzf32lsb_fx1;
wire bof22msb_fx1;
wire [7:2] dpint_nx_byte_fx1;
wire [7:6] spint_nx_byte_fx1;
wire [63:1] dini;
wire [6:0] ibyte_sel;
wire ib0_nor_76;
wire ib0_nor_54;
wire ib0_zeroh_l;
wire [1:0] ib0_cnth;
wire [1:0] ib0_cntl;
wire [2:0] eadj_ibyte0;
wire ib1_nor_76;
wire ib1_nor_54;
wire ib1_zeroh_l;
wire [1:0] ib1_cnth;
wire [1:0] ib1_cntl;
wire [2:0] eadj_ibyte1;
wire ib2_nor_76;
wire ib2_nor_54;
wire ib2_zeroh_l;
wire [1:0] ib2_cnth;
wire [1:0] ib2_cntl;
wire [2:0] eadj_ibyte2;
wire ib3_nor_76;
wire ib3_nor_54;
wire ib3_zeroh_l;
wire [1:0] ib3_cnth;
wire [1:0] ib3_cntl;
wire [2:0] eadj_ibyte3;
wire ib4_nor_76;
wire ib4_nor_54;
wire ib4_zeroh_l;
wire [1:0] ib4_cnth;
wire [1:0] ib4_cntl;
wire [2:0] eadj_ibyte4;
wire ib5_nor_76;
wire ib5_nor_54;
wire ib5_zeroh_l;
wire [1:0] ib5_cnth;
wire [1:0] ib5_cntl;
wire [2:0] eadj_ibyte5;
wire ib6_nor_76;
wire ib6_nor_54;
wire ib6_zeroh_l;
wire [1:0] ib6_cnth;
wire [1:0] ib6_cntl;
wire [2:0] eadj_ibyte6;
wire ib7_nor_76;
wire ib7_nor_54;
wire ib7_zeroh_l;
wire [1:0] ib7_cnth;
wire [1:0] ib7_cntl;
wire [2:0] eadj_ibyte7;
wire [7:0] i2f_eadj_sel_fx1;
wire fx2_00_scanin;
wire fx2_00_scanout;
wire [7:2] dpint_nx_byte_fx2;
wire [7:6] spint_nx_byte_fx2;
wire [7:0] i2f_eadj_sel_fx2;
wire [2:0] eadj_ibyte0_fx2;
wire [2:0] eadj_ibyte1_fx2;
wire [2:0] eadj_ibyte2_fx2;
wire [2:0] eadj_ibyte3_fx2;
wire [2:0] eadj_ibyte4_fx2;
wire [2:0] eadj_ibyte5_fx2;
wire [2:0] eadj_ibyte6_fx2;
wire [2:0] eadj_ibyte7_fx2;
wire fx3_00_scanin;
wire fx3_00_scanout;
wire [5:0] align_sel_fx3;
wire [7:2] dpint_nx_byte_fx3;
wire [7:6] spint_nx_byte_fx3;
wire fstoi_nx_byte_fx3;
wire fstox_nx_byte_fx3;
wire fdtoi_nx_byte_fx3;
wire fdtox_nx_byte_fx3;
wire ftox_nx_bit_fx3;
wire ftoi_nx_bit_fx3;
wire ftoi_nx_fx3;
wire ftox_nx_fx3;
wire fx4_00_scanin;
wire fx4_00_scanout;
wire [63:11] dina;
wire shift_00;
wire [6:0] nbyte_sel;
wire ab0_nor_76;
wire ab0_nor_54;
wire ab0_zeroh_l;
wire [1:0] ab0_cnth;
wire [1:0] ab0_cntl;
wire [2:0] eadj_nbyte0;
wire ab1_nor_76;
wire ab1_nor_54;
wire ab1_zeroh_l;
wire [1:0] ab1_cnth;
wire [1:0] ab1_cntl;
wire [2:0] eadj_nbyte1;
wire ab2_nor_76;
wire ab2_nor_54;
wire ab2_zeroh_l;
wire [1:0] ab2_cnth;
wire [1:0] ab2_cntl;
wire [2:0] eadj_nbyte2;
wire ab3_nor_76;
wire ab3_nor_54;
wire ab3_zeroh_l;
wire [1:0] ab3_cnth;
wire [1:0] ab3_cntl;
wire [2:0] eadj_nbyte3;
wire ab4_nor_76;
wire ab4_nor_54;
wire ab4_zeroh_l;
wire [1:0] ab4_cnth;
wire [1:0] ab4_cntl;
wire [2:0] eadj_nbyte4;
wire ab5_nor_76;
wire ab5_nor_54;
wire ab5_zeroh_l;
wire [1:0] ab5_cnth;
wire [1:0] ab5_cntl;
wire [2:0] eadj_nbyte5;
wire ab6_nor_76;
wire ab6_nor_54;
wire ab6_zeroh_l;
wire [1:0] ab6_cnth;
wire [0:0] ab6_cntl;
wire [2:0] eadj_nbyte6;
wire [5:0] norm_eadj_fx4;
wire fx5_00_scanin;
wire fx5_00_scanout;


// ----------------------------------------------------------------------------
// Interface with FPF
// ----------------------------------------------------------------------------

input   [63:0] fpf_rs2_cmp_din_fx1;    // rt. justified rs2 for FiTO(s,d)
input   [63:0] fpf_ma_sum_fx4;
input  [38:32] fpf_man_se_byte_fx3_b38_32;
input    [6:0] fpf_man_se_byte_fx3_b6_0;
output   [5:0] fic_norm_eadj_fx5;
output   [5:0] fic_i2f_align_sel_fx2;

// ----------------------------------------------------------------------------
// Interface with FPE
// ----------------------------------------------------------------------------

input    [5:0] fpe_align_sel_fx2;
output   [5:0] fic_i2f_eadj_fx2;

// ----------------------------------------------------------------------------
// Interface with FPC
// ----------------------------------------------------------------------------

input          fpc_lzd_override_fx4;
input          fpc_sp_source_fx3;
output         fic_mulscc_iccz_fx4;
output         fic_mulscc_xccz_fx4;
output         fic_convert_sticky_fx4; // sticky for FxTOs, FiTOs, FdTOs
output         fic_fxtod_sticky_fx4;   // sticky for FxTOd
output         fic_ftoi_nx_fx4;        // inexact for FsTOi, FdTOi
output         fic_ftox_nx_fx4;        // inexact for FsTOx, FdTOx
output         fic_bzf31msb_fx2;       // rs2 frac 31 MSBs all zeros
output         fic_bzf32lsb_fx2;       // rs2 frac 32 LSBs all zeros
output         fic_bof22msb_fx2;       // rs2 frac 22 MSBs all ones

// ----------------------------------------------------------------------------
// Interface with FAC
// ----------------------------------------------------------------------------

input          main_clken;             // main clken

// ----------------------------------------------------------------------------
// Global Signals
// ----------------------------------------------------------------------------

input          l2clk;                  // clock input
input  		scan_in;
input  		tcu_pce_ov;		// scan signals
input  		spc_aclk;
input  		spc_bclk;
input           tcu_scan_en;
output 		scan_out;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop   = 1'b0;
assign siclk  = spc_aclk;
assign soclk  = spc_bclk;
assign se     = tcu_scan_en;
// end scan


fgu_fic_ctl_l1clkhdr_ctl_macro clkgen_main (
  .l2clk(l2clk),
  .l1en (main_clken),
  .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fic_ctl_spare_ctl_macro__num_2 spares  (  // spares: 13 gates + 1 flop for each "num"
  .scan_in(spares_scanin),
  .scan_out(spares_scanout),
  .l1clk(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
  );


// ----------------------------------------------------------------------------
//                               FX1 stage
// ----------------------------------------------------------------------------

// required for FdTOi large_maxint_result calculation
assign  bzf31msb_fx1 = ~(|fpf_rs2_cmp_din_fx1[51:21]);  // frac 31 MSBs all zeros

// required for FiTO(s,d) zero_src_result calculation
// fpf_rs2_cmp_din_fx1 is rt. justified for FiTO(s,d)
// fpf_bzf_fx1 doesn't work for FiTO(s,d) zero detection because 32 LSBs are unknown
assign  bzf32lsb_fx1 = ~(|fpf_rs2_cmp_din_fx1[31:0]);   // int32        all zeros

// required for FdTOs denorm round to norm detection
assign  bof22msb_fx1 =   &fpf_rs2_cmp_din_fx1[51:30];   // frac 22 MSBs all ones

// ------------------------------------
// F(s,d)TO(i,x) inexact detection (byte)
// ------------------------------------

assign  dpint_nx_byte_fx1[7] = |fpf_rs2_cmp_din_fx1[44:37];
assign  dpint_nx_byte_fx1[6] = |fpf_rs2_cmp_din_fx1[36:29];
assign  dpint_nx_byte_fx1[5] = |fpf_rs2_cmp_din_fx1[28:21];
assign  dpint_nx_byte_fx1[4] = |fpf_rs2_cmp_din_fx1[20:13];
assign  dpint_nx_byte_fx1[3] = |fpf_rs2_cmp_din_fx1[12:5];
assign  dpint_nx_byte_fx1[2] = |fpf_rs2_cmp_din_fx1[4:0];

assign  spint_nx_byte_fx1[7] = |fpf_rs2_cmp_din_fx1[47:40];
assign  spint_nx_byte_fx1[6] = |fpf_rs2_cmp_din_fx1[39:32];

// ------------------------------------
// i2f LZD "XOR function"
// Convert negative signed integer source
// to sign-magnitude value
// ------------------------------------

assign  dini[63:1] = fpf_rs2_cmp_din_fx1[63:1] ^ {63{fpf_rs2_cmp_din_fx1[63]}};

// ------------------------------------
// i2f LZD Byte selects (not priority encoded)
// ------------------------------------

assign  ibyte_sel[0] = |dini[63:56];  // shift 00-bits
assign  ibyte_sel[1] = |dini[55:48];  // shift 08-bits
assign  ibyte_sel[2] = |dini[47:40];  // shift 16-bits
assign  ibyte_sel[3] = |dini[39:32];  // shift 24-bits
assign  ibyte_sel[4] = |dini[31:24];  // shift 32-bits
assign  ibyte_sel[5] = |dini[23:16];  // shift 40-bits
assign  ibyte_sel[6] = |dini[15:8];  // shift 48-bits

// ------------------------------------
// i2f LZD Eadj[2:0]
//
// - count leading zeros in a given byte
//   and encode into a 3-bit value (Eadj[2:0])
//
//   Bit shift:  [4] [2] [1]
//   Eadj bit:   [2] [1] [0]
//   ---------------------------
//                0   0   0
//                0   0   1
//                0   1   0
//                0   1   1
//                1   0   0
//                1   0   1
//                1   1   0
//                1   1   1
//
//          din[7:0]    | Eadj[2:0]
//     -----------------|------------
//     1 x x x x x x x  |   0 0 0  
//     0 1 x x x x x x  |   0 0 1  
//     0 0 1 x x x x x  |   0 1 0  
//     0 0 0 1 x x x x  |   0 1 1  
//     0 0 0 0 1 x x x  |   1 0 0  
//     0 0 0 0 0 1 x x  |   1 0 1  
//     0 0 0 0 0 0 1 x  |   1 1 0  
//     0 0 0 0 0 0 0 x  |   1 1 1  
//
// Note: force Eadj[2:0] to 3'b111
//       if din[7:1]==7'b0000000 (i.e. assume din[0]==1'b1) 
//       This has already been done for byte0-byte7 below.
//
// ------------------------------------

// ----------------------------------------------------------------------------
// i2f LZD dini byte0 => dini[63:56]
// assume dini[56] == 1'b1
// ----------------------------------------------------------------------------

assign  ib0_nor_76  = ~(dini[63] | dini[62]);
assign  ib0_nor_54  = ~(dini[61] | dini[60]);

assign  ib0_zeroh_l = ~(ib0_nor_76 & ib0_nor_54);

assign  ib0_cnth[0] =  (~dini[63] &  dini[62]                        ) |
                       (~dini[63] &             ~dini[61] &  dini[60]) ;
assign  ib0_cnth[1] =  (~dini[63] & ~dini[62] &  dini[61]            ) |
                       (~dini[63] & ~dini[62] &              dini[60]) ;
assign  ib0_cntl[0] =  (~dini[59] &  dini[58]                        ) |
                       (~dini[59] &             ~dini[57]            ) ;
assign  ib0_cntl[1] =  (~dini[59] & ~dini[58] &  dini[57]            ) |
                       (~dini[59] & ~dini[58]                        ) ;

assign  eadj_ibyte0[0] = ( ib0_zeroh_l & ib0_cnth[0]) |
                         (~ib0_zeroh_l & ib0_cntl[0]) ;
assign  eadj_ibyte0[1] = ( ib0_zeroh_l & ib0_cnth[1]) |
                         (~ib0_zeroh_l & ib0_cntl[1]) ;
assign  eadj_ibyte0[2] =  ~ib0_zeroh_l                ;

// ----------------------------------------------------------------------------
// i2f LZD dini byte1 => dini[55:48]
// assume dini[48] == 1'b1
// ----------------------------------------------------------------------------

assign  ib1_nor_76  = ~(dini[55] | dini[54]);
assign  ib1_nor_54  = ~(dini[53] | dini[52]);

assign  ib1_zeroh_l = ~(ib1_nor_76 & ib1_nor_54);

assign  ib1_cnth[0] =  (~dini[55] &  dini[54]                        ) |
                       (~dini[55] &             ~dini[53] &  dini[52]) ;
assign  ib1_cnth[1] =  (~dini[55] & ~dini[54] &  dini[53]            ) |
                       (~dini[55] & ~dini[54] &              dini[52]) ;
assign  ib1_cntl[0] =  (~dini[51] &  dini[50]                        ) |
                       (~dini[51] &             ~dini[49]            ) ;
assign  ib1_cntl[1] =  (~dini[51] & ~dini[50] &  dini[49]            ) |
                       (~dini[51] & ~dini[50]                        ) ;
 
assign  eadj_ibyte1[0] = ( ib1_zeroh_l & ib1_cnth[0]) |
                         (~ib1_zeroh_l & ib1_cntl[0]) ;
assign  eadj_ibyte1[1] = ( ib1_zeroh_l & ib1_cnth[1]) |
                         (~ib1_zeroh_l & ib1_cntl[1]) ;
assign  eadj_ibyte1[2] =  ~ib1_zeroh_l                ;

// ----------------------------------------------------------------------------
// i2f LZD dini byte2 => dini[47:40]
// assume dini[40] == 1'b1
// ----------------------------------------------------------------------------

assign  ib2_nor_76  = ~(dini[47] | dini[46]);
assign  ib2_nor_54  = ~(dini[45] | dini[44]);

assign  ib2_zeroh_l = ~(ib2_nor_76 & ib2_nor_54);

assign  ib2_cnth[0] =  (~dini[47] &  dini[46]                        ) |
                       (~dini[47] &             ~dini[45] &  dini[44]) ;
assign  ib2_cnth[1] =  (~dini[47] & ~dini[46] &  dini[45]            ) |
                       (~dini[47] & ~dini[46] &              dini[44]) ;
assign  ib2_cntl[0] =  (~dini[43] &  dini[42]                        ) |
                       (~dini[43] &             ~dini[41]            ) ;
assign  ib2_cntl[1] =  (~dini[43] & ~dini[42] &  dini[41]            ) |
                       (~dini[43] & ~dini[42]                        ) ;

assign  eadj_ibyte2[0] = ( ib2_zeroh_l & ib2_cnth[0]) |
                         (~ib2_zeroh_l & ib2_cntl[0]) ;
assign  eadj_ibyte2[1] = ( ib2_zeroh_l & ib2_cnth[1]) |
                         (~ib2_zeroh_l & ib2_cntl[1]) ;
assign  eadj_ibyte2[2] =  ~ib2_zeroh_l                ;

// ----------------------------------------------------------------------------
// i2f LZD dini byte3 => dini[39:32]
// assume dini[32] == 1'b1
// ----------------------------------------------------------------------------

assign  ib3_nor_76  = ~(dini[39] | dini[38]);
assign  ib3_nor_54  = ~(dini[37] | dini[36]);

assign  ib3_zeroh_l = ~(ib3_nor_76 & ib3_nor_54);

assign  ib3_cnth[0] =  (~dini[39] &  dini[38]                        ) |
                       (~dini[39] &             ~dini[37] &  dini[36]) ;
assign  ib3_cnth[1] =  (~dini[39] & ~dini[38] &  dini[37]            ) |
                       (~dini[39] & ~dini[38] &              dini[36]) ;
assign  ib3_cntl[0] =  (~dini[35] &  dini[34]                        ) |
                       (~dini[35] &             ~dini[33]            ) ;
assign  ib3_cntl[1] =  (~dini[35] & ~dini[34] &  dini[33]            ) |
                       (~dini[35] & ~dini[34]                        ) ;

assign  eadj_ibyte3[0] = ( ib3_zeroh_l & ib3_cnth[0]) |
                         (~ib3_zeroh_l & ib3_cntl[0]) ;
assign  eadj_ibyte3[1] = ( ib3_zeroh_l & ib3_cnth[1]) |
                         (~ib3_zeroh_l & ib3_cntl[1]) ;
assign  eadj_ibyte3[2] =  ~ib3_zeroh_l                ;

// ----------------------------------------------------------------------------
// i2f LZD dini byte4 => dini[31:24]
// assume dini[24] == 1'b1
// ----------------------------------------------------------------------------

assign  ib4_nor_76  = ~(dini[31] | dini[30]);
assign  ib4_nor_54  = ~(dini[29] | dini[28]);

assign  ib4_zeroh_l = ~(ib4_nor_76 & ib4_nor_54);

assign  ib4_cnth[0] =  (~dini[31] &  dini[30]                        ) |
                       (~dini[31] &             ~dini[29] &  dini[28]) ;
assign  ib4_cnth[1] =  (~dini[31] & ~dini[30] &  dini[29]            ) |
                       (~dini[31] & ~dini[30] &              dini[28]) ;
assign  ib4_cntl[0] =  (~dini[27] &  dini[26]                        ) |
                       (~dini[27] &             ~dini[25]            ) ;
assign  ib4_cntl[1] =  (~dini[27] & ~dini[26] &  dini[25]            ) |
                       (~dini[27] & ~dini[26]                        ) ;

assign  eadj_ibyte4[0] = ( ib4_zeroh_l & ib4_cnth[0]) |
                         (~ib4_zeroh_l & ib4_cntl[0]) ;
assign  eadj_ibyte4[1] = ( ib4_zeroh_l & ib4_cnth[1]) |
                         (~ib4_zeroh_l & ib4_cntl[1]) ;
assign  eadj_ibyte4[2] =  ~ib4_zeroh_l                ;

// ----------------------------------------------------------------------------
// i2f LZD dini byte5 => dini[23:16]
// assume dini[16] == 1'b1
// ----------------------------------------------------------------------------

assign  ib5_nor_76  = ~(dini[23] | dini[22]);
assign  ib5_nor_54  = ~(dini[21] | dini[20]);

assign  ib5_zeroh_l = ~(ib5_nor_76 & ib5_nor_54);

assign  ib5_cnth[0] =  (~dini[23] &  dini[22]                        ) |
                       (~dini[23] &             ~dini[21] &  dini[20]) ;
assign  ib5_cnth[1] =  (~dini[23] & ~dini[22] &  dini[21]            ) |
                       (~dini[23] & ~dini[22] &              dini[20]) ;
assign  ib5_cntl[0] =  (~dini[19] &  dini[18]                        ) |
                       (~dini[19] &             ~dini[17]            ) ;
assign  ib5_cntl[1] =  (~dini[19] & ~dini[18] &  dini[17]            ) |
                       (~dini[19] & ~dini[18]                        ) ;

assign  eadj_ibyte5[0] = ( ib5_zeroh_l & ib5_cnth[0]) |
                         (~ib5_zeroh_l & ib5_cntl[0]) ;
assign  eadj_ibyte5[1] = ( ib5_zeroh_l & ib5_cnth[1]) |
                         (~ib5_zeroh_l & ib5_cntl[1]) ;
assign  eadj_ibyte5[2] =  ~ib5_zeroh_l                ;

// ----------------------------------------------------------------------------
// i2f LZD dini byte6 => dini[15:08]
// assume dini[08] == 1'b1
// ----------------------------------------------------------------------------

assign  ib6_nor_76  = ~(dini[15] | dini[14]);
assign  ib6_nor_54  = ~(dini[13] | dini[12]);

assign  ib6_zeroh_l = ~(ib6_nor_76 & ib6_nor_54);

assign  ib6_cnth[0] =  (~dini[15] &  dini[14]                        ) |
                       (~dini[15] &             ~dini[13] &  dini[12]) ;
assign  ib6_cnth[1] =  (~dini[15] & ~dini[14] &  dini[13]            ) |
                       (~dini[15] & ~dini[14] &              dini[12]) ;
assign  ib6_cntl[0] =  (~dini[11] &  dini[10]                        ) |
                       (~dini[11] &             ~dini[9]            ) ;
assign  ib6_cntl[1] =  (~dini[11] & ~dini[10] &  dini[9]            ) |
                       (~dini[11] & ~dini[10]                        ) ;

assign  eadj_ibyte6[0] = ( ib6_zeroh_l & ib6_cnth[0]) |
                         (~ib6_zeroh_l & ib6_cntl[0]) ;
assign  eadj_ibyte6[1] = ( ib6_zeroh_l & ib6_cnth[1]) |
                         (~ib6_zeroh_l & ib6_cntl[1]) ;
assign  eadj_ibyte6[2] =  ~ib6_zeroh_l                ;

// ----------------------------------------------------------------------------
// i2f LZD dini byte7 => dini[07:00]
// assume dini[0] == 1'b1
// ----------------------------------------------------------------------------

assign  ib7_nor_76  = ~(dini[7] | dini[6]);
assign  ib7_nor_54  = ~(dini[5] | dini[4]);

assign  ib7_zeroh_l = ~(ib7_nor_76 & ib7_nor_54);

assign  ib7_cnth[0] =  (~dini[7] &  dini[6]                        ) |
                       (~dini[7] &             ~dini[5] &  dini[4]) ;
assign  ib7_cnth[1] =  (~dini[7] & ~dini[6] &  dini[5]            ) |
                       (~dini[7] & ~dini[6] &              dini[4]) ;
assign  ib7_cntl[0] =  (~dini[3] &  dini[2]                        ) |
                       (~dini[3] &             ~dini[1]            ) ;
assign  ib7_cntl[1] =  (~dini[3] & ~dini[2] &  dini[1]            ) |
                       (~dini[3] & ~dini[2]                        ) ;

assign  eadj_ibyte7[0] = ( ib7_zeroh_l & ib7_cnth[0]) |
                         (~ib7_zeroh_l & ib7_cntl[0]) ;
assign  eadj_ibyte7[1] = ( ib7_zeroh_l & ib7_cnth[1]) |
                         (~ib7_zeroh_l & ib7_cntl[1]) ;
assign  eadj_ibyte7[2] =  ~ib7_zeroh_l                ;

// ----------------------------------------------------------------------------
// i2f LZD Eadj[5:0] mux selects
// ----------------------------------------------------------------------------

assign  i2f_eadj_sel_fx1[0] =                      ibyte_sel[0];
assign  i2f_eadj_sel_fx1[1] = ~( ibyte_sel[0]  ) & ibyte_sel[1];
assign  i2f_eadj_sel_fx1[2] = ~(|ibyte_sel[1:0]) & ibyte_sel[2];
assign  i2f_eadj_sel_fx1[3] = ~(|ibyte_sel[2:0]) & ibyte_sel[3];
assign  i2f_eadj_sel_fx1[4] = ~(|ibyte_sel[3:0]) & ibyte_sel[4];
assign  i2f_eadj_sel_fx1[5] = ~(|ibyte_sel[4:0]) & ibyte_sel[5];
assign  i2f_eadj_sel_fx1[6] = ~(|ibyte_sel[5:0]) & ibyte_sel[6];
assign  i2f_eadj_sel_fx1[7] = ~(|ibyte_sel[6:0]);


// ----------------------------------------------------------------------------
//                               FX2 stage
// ----------------------------------------------------------------------------

fgu_fic_ctl_msff_ctl_macro__width_43 fx2_00  (
  .scan_in(fx2_00_scanin),
  .scan_out(fx2_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({    bzf31msb_fx1,
             bzf32lsb_fx1,
             bof22msb_fx1,
         dpint_nx_byte_fx1[7:2],
         spint_nx_byte_fx1[7:6],
         i2f_eadj_sel_fx1[7:0],
         eadj_ibyte0[2:0],
         eadj_ibyte1[2:0],
         eadj_ibyte2[2:0],
         eadj_ibyte3[2:0],
         eadj_ibyte4[2:0],
         eadj_ibyte5[2:0],
         eadj_ibyte6[2:0],
         eadj_ibyte7[2:0]}),
  .dout({fic_bzf31msb_fx2,
         fic_bzf32lsb_fx2,
         fic_bof22msb_fx2,
         dpint_nx_byte_fx2[7:2],
         spint_nx_byte_fx2[7:6],
         i2f_eadj_sel_fx2[7:0],
         eadj_ibyte0_fx2[2:0],
         eadj_ibyte1_fx2[2:0],
         eadj_ibyte2_fx2[2:0],
         eadj_ibyte3_fx2[2:0],
         eadj_ibyte4_fx2[2:0],
         eadj_ibyte5_fx2[2:0],
         eadj_ibyte6_fx2[2:0],
         eadj_ibyte7_fx2[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

// ----------------------------------------------------------------------------
// i2f LZD Eadj[5:0] mux
// ----------------------------------------------------------------------------

assign  fic_i2f_eadj_fx2[5:0] =
  ({6{i2f_eadj_sel_fx2[0]}} & ({3'b000, eadj_ibyte0_fx2[2:0]})) |
  ({6{i2f_eadj_sel_fx2[1]}} & ({3'b001, eadj_ibyte1_fx2[2:0]})) |
  ({6{i2f_eadj_sel_fx2[2]}} & ({3'b010, eadj_ibyte2_fx2[2:0]})) |
  ({6{i2f_eadj_sel_fx2[3]}} & ({3'b011, eadj_ibyte3_fx2[2:0]})) |
  ({6{i2f_eadj_sel_fx2[4]}} & ({3'b100, eadj_ibyte4_fx2[2:0]})) |
  ({6{i2f_eadj_sel_fx2[5]}} & ({3'b101, eadj_ibyte5_fx2[2:0]})) |
  ({6{i2f_eadj_sel_fx2[6]}} & ({3'b110, eadj_ibyte6_fx2[2:0]})) |
  ({6{i2f_eadj_sel_fx2[7]}} & ({3'b111, eadj_ibyte7_fx2[2:0]})) ;

assign  fic_i2f_align_sel_fx2[5:0] =
  (~fic_i2f_eadj_fx2[5:0]) + 6'b000001;  // 2's comp


// ----------------------------------------------------------------------------
//                               FX3 stage
// ----------------------------------------------------------------------------

fgu_fic_ctl_msff_ctl_macro__width_14 fx3_00  (
  .scan_in(fx3_00_scanin),
  .scan_out(fx3_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({fpe_align_sel_fx2[5:0], dpint_nx_byte_fx2[7:2], spint_nx_byte_fx2[7:6]}),
  .dout({    align_sel_fx3[5:0], dpint_nx_byte_fx3[7:2], spint_nx_byte_fx3[7:6]}),
  .siclk(siclk),
  .soclk(soclk)
  );

// ------------------------------------
// F(s,d)TO(i,x) inexact detection
//
//          -----------------------------------
// FsTOi   |     32          |      32         |
//          -----------------------------------
//          ------------     
//         |     24     |
//          ------------
//            4   3   2                  <= byte shift
//
//          -----------------------------------
// FsTOx   |                 64                |
//          -----------------------------------
//          ------------     
//         |     24     |
//          ------------
//            8   7   6                  <= byte shift
//
//          -----------------------------------
// FdTOi   |     32          |      32         |
//          -----------------------------------
//          --------------------------
//         |                 53       |
//          --------------------------
//            4   3   2   1   ---Any--   <= byte shift
// 
//          -----------------------------------
// FdTOx   |                 64                |
//          -----------------------------------
//          --------------------------
//         |                 53       |
//          --------------------------
//            8   7   6   5   4   3  2   <= byte shift
//
// ------------------------------------

assign  fstoi_nx_byte_fx3 =
  ((align_sel_fx3[4:3] == 2'd3) & (|spint_nx_byte_fx3[7:6])) |
  ((align_sel_fx3[4:3] == 2'd2) & ( spint_nx_byte_fx3[6]  )) ;

assign  fstox_nx_byte_fx3 =
  ((align_sel_fx3[5:3] == 3'd7) & (|spint_nx_byte_fx3[7:6])) |
  ((align_sel_fx3[5:3] == 3'd6) & ( spint_nx_byte_fx3[6]  )) ;

assign  fdtoi_nx_byte_fx3 =
  ((align_sel_fx3[5:3] == 3'd3) & (|dpint_nx_byte_fx3[7:5])) |
  ((align_sel_fx3[5:3] == 3'd2) & (|dpint_nx_byte_fx3[6:5])) |
  ((align_sel_fx3[5:3] == 3'd1) & ( dpint_nx_byte_fx3[5]  )) |
  (                               (|dpint_nx_byte_fx3[4:2])) ;

assign  fdtox_nx_byte_fx3 =
  ((align_sel_fx3[5:3] == 3'd7) & (|dpint_nx_byte_fx3[7:2])) |
  ((align_sel_fx3[5:3] == 3'd6) & (|dpint_nx_byte_fx3[6:2])) |
  ((align_sel_fx3[5:3] == 3'd5) & (|dpint_nx_byte_fx3[5:2])) |
  ((align_sel_fx3[5:3] == 3'd4) & (|dpint_nx_byte_fx3[4:2])) |
  ((align_sel_fx3[5:3] == 3'd3) & (|dpint_nx_byte_fx3[3:2])) |
  ((align_sel_fx3[5:3] == 3'd2) & ( dpint_nx_byte_fx3[2]  )) ;

assign  ftox_nx_bit_fx3 =
  ((align_sel_fx3[2:0] == 3'd7) & (|fpf_man_se_byte_fx3_b6_0[6:0])) |
  ((align_sel_fx3[2:0] == 3'd6) & (|fpf_man_se_byte_fx3_b6_0[5:0])) |
  ((align_sel_fx3[2:0] == 3'd5) & (|fpf_man_se_byte_fx3_b6_0[4:0])) |
  ((align_sel_fx3[2:0] == 3'd4) & (|fpf_man_se_byte_fx3_b6_0[3:0])) |
  ((align_sel_fx3[2:0] == 3'd3) & (|fpf_man_se_byte_fx3_b6_0[2:0])) |
  ((align_sel_fx3[2:0] == 3'd2) & (|fpf_man_se_byte_fx3_b6_0[1:0])) |
  ((align_sel_fx3[2:0] == 3'd1) & ( fpf_man_se_byte_fx3_b6_0[0]  )) ;

assign  ftoi_nx_bit_fx3 =
  ((align_sel_fx3[2:0] == 3'd7) & (|fpf_man_se_byte_fx3_b38_32[38:32])) |
  ((align_sel_fx3[2:0] == 3'd6) & (|fpf_man_se_byte_fx3_b38_32[37:32])) |
  ((align_sel_fx3[2:0] == 3'd5) & (|fpf_man_se_byte_fx3_b38_32[36:32])) |
  ((align_sel_fx3[2:0] == 3'd4) & (|fpf_man_se_byte_fx3_b38_32[35:32])) |
  ((align_sel_fx3[2:0] == 3'd3) & (|fpf_man_se_byte_fx3_b38_32[34:32])) |
  ((align_sel_fx3[2:0] == 3'd2) & (|fpf_man_se_byte_fx3_b38_32[33:32])) |
  ((align_sel_fx3[2:0] == 3'd1) & ( fpf_man_se_byte_fx3_b38_32[32]   )) ;

assign  ftoi_nx_fx3 =
  ftoi_nx_bit_fx3 |
  (fstoi_nx_byte_fx3 &  fpc_sp_source_fx3) |
  (fdtoi_nx_byte_fx3 & ~fpc_sp_source_fx3) ;

assign  ftox_nx_fx3 =
  ftox_nx_bit_fx3 |
  (fstox_nx_byte_fx3 &  fpc_sp_source_fx3) |
  (fdtox_nx_byte_fx3 & ~fpc_sp_source_fx3) ;


// ----------------------------------------------------------------------------
//                               FX4 stage
// ----------------------------------------------------------------------------

fgu_fic_ctl_msff_ctl_macro__width_2 fx4_00  (
  .scan_in(fx4_00_scanin),
  .scan_out(fx4_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({    ftoi_nx_fx3,     ftox_nx_fx3}),
  .dout({fic_ftoi_nx_fx4, fic_ftox_nx_fx4}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fic_mulscc_iccz_fx4 = (fpf_ma_sum_fx4[31:0] == 32'b0);
assign  fic_mulscc_xccz_fx4 = ~fpf_ma_sum_fx4[32] & fic_mulscc_iccz_fx4;

// ------------------------------------
// i2f and FdTOs sticky calculation
//
//          -----------------------------------
// FxTOs   |                 64                |
//          -----------------------------------
//          ------------ G   
//         |     24     |  7 |      32         |
//          ------------
//
//          -----------------------------------
// FxTOd   |                 64                |
//          -----------------------------------
//          -------------------------- G    
//         |                 53       |  7 | 3 |
//          --------------------------
//
//          -----------------------------------
// FiTOs   |     32          |      32         |
//          -----------------------------------
//          ------------ G    
//         |     24     |  7 |      32         |
//          ------------      
//
// FiTOd   never rounds (exact)
//
// i2f notes:
// - logically, LSB,G,X should be post-2comp for neg integers
// - X is equiv if calculated pre or post-2comp (post-2comp is used in
//   this design for simplicity)
// - The 2comp +1 function can't result in clearing all G,X bits and
//   blocking Rinc unless the post-2comp was b'00...00 in that region.
//   However, in that case a +1 was propagated to the LSB as if an Rinc
//   had taken place. Thus, effectively, a 2comp +1 can't block an Rinc,
//   and LSB,G need only reflect the 2comp invert function, not the
//   2comp +1 function.
//
// FdTOs notes:
// - the dp input (rs2) is always normalized
// - the dp mantissa resides in bits 63:11
// ------------------------------------

assign  fic_convert_sticky_fx4 = |fpf_ma_sum_fx4[38:0];  // FxTOs, FiTOs, FdTOs
assign  fic_fxtod_sticky_fx4   = |fpf_ma_sum_fx4[9:0];   // FxTOd

// ----------------------------------------------------------------------------
// Normalizer LZD
//
// data input format:
//
//         63                 32  31             8
//          -------------------    --------------
//         |      32-bits      |  |    24-bits   |
//          -------------------    --------------
//    Byte:  0    1    2    3       4    5    6
//
//
//      LSB pos.  G pos.
//      --------  ------
// DP     11        10
// SP     40        39
//
// ----------------------------------------------------------------------------

assign  dina[63:11] = fpf_ma_sum_fx4[63:11];

// ------------------------------------
// LZD override by setting dina bit 63 to
// force a Norm shift of 0-bits
//
// Override cases:
// - multiply (covered by ~logical_sub)
// - div/sqrt (covered by ~logical_sub)
// - 1X.XX    (covered by ~logical_sub)
// - 00.1X
// Note:
// - 1X.XX due to Rcout is unknown in fx4
// - 1X.XX not possible if logical_subtract
// - 00.1X is shifted 1-bit by the main adder output format mux
// ------------------------------------

assign  shift_00 =
  fpc_lzd_override_fx4 |   // mul | div | sqrt | 1X.XX
  (dina[63:62] == 2'b01);  // 00.1X

// ------------------------------------
// Norm LZD Byte selects (not priority encoded)
// ------------------------------------

assign  nbyte_sel[0] = shift_00;      // force eadj=0
assign  nbyte_sel[1] = |dina[63:56];  // shift 00-bits
assign  nbyte_sel[2] = |dina[55:48];  // shift 08-bits
assign  nbyte_sel[3] = |dina[47:40];  // shift 16-bits
assign  nbyte_sel[4] = |dina[39:32];  // shift 24-bits
assign  nbyte_sel[5] = |dina[31:24];  // shift 32-bits
assign  nbyte_sel[6] = |dina[23:16];  // shift 40-bits
	
// ------------------------------------
// Norm LZD Eadj[2:0]
//
// - count leading zeros in a given byte
//   and encode into a 3-bit value (Eadj[2:0])
//
//   Bit shift:  [4] [2] [1]
//   Eadj bit:   [2] [1] [0]
//   ---------------------------
//                0   0   0
//                0   0   1
//                0   1   0
//                0   1   1
//                1   0   0
//                1   0   1
//                1   1   0
//                1   1   1
//
//          din[7:0]    | Eadj[2:0]
//     -----------------|------------
//     1 x x x x x x x  |   0 0 0  
//     0 1 x x x x x x  |   0 0 1  
//     0 0 1 x x x x x  |   0 1 0  
//     0 0 0 1 x x x x  |   0 1 1  
//     0 0 0 0 1 x x x  |   1 0 0  
//     0 0 0 0 0 1 x x  |   1 0 1  
//     0 0 0 0 0 0 1 x  |   1 1 0  
//     0 0 0 0 0 0 0 x  |   1 1 1
//
// Note: force Eadj[2:0] to 3'b111
//       if din[7:1]==7'b0000000 (i.e. assume din[0]==1'b1) 
//       This has already been done for byte0-byte6 below.
//       Also, for DP operation, din[10] is assumed to be
//       1'b1 since bit 10 (the DP G pos.) isn't the LSB
//       position of byte6.
//
// ------------------------------------

// ----------------------------------------------------------------------------
// Norm LZD dina byte0 => dina[63:56]
// assume dina[56] == 1'b1
// ----------------------------------------------------------------------------

assign  ab0_nor_76  = ~(dina[63] | dina[62]);
assign  ab0_nor_54  = ~(dina[61] | dina[60]);

assign  ab0_zeroh_l = ~(ab0_nor_76 & ab0_nor_54);

assign  ab0_cnth[0] =  (~dina[63] &  dina[62]                        ) |
                       (~dina[63] &             ~dina[61] &  dina[60]) ;
assign  ab0_cnth[1] =  (~dina[63] & ~dina[62] &  dina[61]            ) |
                       (~dina[63] & ~dina[62] &              dina[60]) ;
assign  ab0_cntl[0] =  (~dina[59] &  dina[58]                        ) |
                       (~dina[59] &             ~dina[57]            ) ;
assign  ab0_cntl[1] =  (~dina[59] & ~dina[58] &  dina[57]            ) |
                       (~dina[59] & ~dina[58]                        ) ;

assign  eadj_nbyte0[0] = ( ab0_zeroh_l & ab0_cnth[0]) |
                         (~ab0_zeroh_l & ab0_cntl[0]) ;
assign  eadj_nbyte0[1] = ( ab0_zeroh_l & ab0_cnth[1]) |
                         (~ab0_zeroh_l & ab0_cntl[1]) ;
assign  eadj_nbyte0[2] =  ~ab0_zeroh_l                ;

// ----------------------------------------------------------------------------
// Norm LZD dina byte1 => dina[55:48]
// assume dina[48] == 1'b1
// ----------------------------------------------------------------------------

assign  ab1_nor_76  = ~(dina[55] | dina[54]);
assign  ab1_nor_54  = ~(dina[53] | dina[52]);

assign  ab1_zeroh_l = ~(ab1_nor_76 & ab1_nor_54);

assign  ab1_cnth[0] =  (~dina[55] &  dina[54]                        ) |
                       (~dina[55] &             ~dina[53] &  dina[52]) ;
assign  ab1_cnth[1] =  (~dina[55] & ~dina[54] &  dina[53]            ) |
                       (~dina[55] & ~dina[54] &              dina[52]) ;
assign  ab1_cntl[0] =  (~dina[51] &  dina[50]                        ) |
                       (~dina[51] &             ~dina[49]            ) ;
assign  ab1_cntl[1] =  (~dina[51] & ~dina[50] &  dina[49]            ) |
                       (~dina[51] & ~dina[50]                        ) ;
 
assign  eadj_nbyte1[0] = ( ab1_zeroh_l & ab1_cnth[0]) |
                         (~ab1_zeroh_l & ab1_cntl[0]) ;
assign  eadj_nbyte1[1] = ( ab1_zeroh_l & ab1_cnth[1]) |
                         (~ab1_zeroh_l & ab1_cntl[1]) ;
assign  eadj_nbyte1[2] =  ~ab1_zeroh_l                ;

// ----------------------------------------------------------------------------
// Norm LZD dina byte2 => dina[47:40]
// assume dina[40] == 1'b1
// ----------------------------------------------------------------------------

assign  ab2_nor_76  = ~(dina[47] | dina[46]);
assign  ab2_nor_54  = ~(dina[45] | dina[44]);

assign  ab2_zeroh_l = ~(ab2_nor_76 & ab2_nor_54);

assign  ab2_cnth[0] =  (~dina[47] &  dina[46]                        ) |
                       (~dina[47] &             ~dina[45] &  dina[44]) ;
assign  ab2_cnth[1] =  (~dina[47] & ~dina[46] &  dina[45]            ) |
                       (~dina[47] & ~dina[46] &              dina[44]) ;
assign  ab2_cntl[0] =  (~dina[43] &  dina[42]                        ) |
                       (~dina[43] &             ~dina[41]            ) ;
assign  ab2_cntl[1] =  (~dina[43] & ~dina[42] &  dina[41]            ) |
                       (~dina[43] & ~dina[42]                        ) ;

assign  eadj_nbyte2[0] = ( ab2_zeroh_l & ab2_cnth[0]) |
                         (~ab2_zeroh_l & ab2_cntl[0]) ;
assign  eadj_nbyte2[1] = ( ab2_zeroh_l & ab2_cnth[1]) |
                         (~ab2_zeroh_l & ab2_cntl[1]) ;
assign  eadj_nbyte2[2] =  ~ab2_zeroh_l                ;

// ----------------------------------------------------------------------------
// Norm LZD dina byte3 => dina[39:32]
// assume dina[32] == 1'b1
// ----------------------------------------------------------------------------

assign  ab3_nor_76  = ~(dina[39] | dina[38]);
assign  ab3_nor_54  = ~(dina[37] | dina[36]);

assign  ab3_zeroh_l = ~(ab3_nor_76 & ab3_nor_54);

assign  ab3_cnth[0] =  (~dina[39] &  dina[38]                        ) |
                       (~dina[39] &             ~dina[37] &  dina[36]) ;
assign  ab3_cnth[1] =  (~dina[39] & ~dina[38] &  dina[37]            ) |
                       (~dina[39] & ~dina[38] &              dina[36]) ;
assign  ab3_cntl[0] =  (~dina[35] &  dina[34]                        ) |
                       (~dina[35] &             ~dina[33]            ) ;
assign  ab3_cntl[1] =  (~dina[35] & ~dina[34] &  dina[33]            ) |
                       (~dina[35] & ~dina[34]                        ) ;

assign  eadj_nbyte3[0] = ( ab3_zeroh_l & ab3_cnth[0]) |
                         (~ab3_zeroh_l & ab3_cntl[0]) ;
assign  eadj_nbyte3[1] = ( ab3_zeroh_l & ab3_cnth[1]) |
                         (~ab3_zeroh_l & ab3_cntl[1]) ;
assign  eadj_nbyte3[2] =  ~ab3_zeroh_l                ;

// ----------------------------------------------------------------------------
// Norm LZD dina byte4 => dina[31:24]
// assume dina[24] == 1'b1
// ----------------------------------------------------------------------------

assign  ab4_nor_76  = ~(dina[31] | dina[30]);
assign  ab4_nor_54  = ~(dina[29] | dina[28]);

assign  ab4_zeroh_l = ~(ab4_nor_76 & ab4_nor_54);

assign  ab4_cnth[0] =  (~dina[31] &  dina[30]                        ) |
                       (~dina[31] &             ~dina[29] &  dina[28]) ;
assign  ab4_cnth[1] =  (~dina[31] & ~dina[30] &  dina[29]            ) |
                       (~dina[31] & ~dina[30] &              dina[28]) ;
assign  ab4_cntl[0] =  (~dina[27] &  dina[26]                        ) |
                       (~dina[27] &             ~dina[25]            ) ;
assign  ab4_cntl[1] =  (~dina[27] & ~dina[26] &  dina[25]            ) |
                       (~dina[27] & ~dina[26]                        ) ;

assign  eadj_nbyte4[0] = ( ab4_zeroh_l & ab4_cnth[0]) |
                         (~ab4_zeroh_l & ab4_cntl[0]) ;
assign  eadj_nbyte4[1] = ( ab4_zeroh_l & ab4_cnth[1]) |
                         (~ab4_zeroh_l & ab4_cntl[1]) ;
assign  eadj_nbyte4[2] =  ~ab4_zeroh_l                ;

// ----------------------------------------------------------------------------
// Norm LZD dina byte5 => dina[23:16]
// assume dina[16] == 1'b1
// ----------------------------------------------------------------------------

assign  ab5_nor_76  = ~(dina[23] | dina[22]);
assign  ab5_nor_54  = ~(dina[21] | dina[20]);

assign  ab5_zeroh_l = ~(ab5_nor_76 & ab5_nor_54);

assign  ab5_cnth[0] =  (~dina[23] &  dina[22]                        ) |
                       (~dina[23] &             ~dina[21] &  dina[20]) ;
assign  ab5_cnth[1] =  (~dina[23] & ~dina[22] &  dina[21]            ) |
                       (~dina[23] & ~dina[22] &              dina[20]) ;
assign  ab5_cntl[0] =  (~dina[19] &  dina[18]                        ) |
                       (~dina[19] &             ~dina[17]            ) ;
assign  ab5_cntl[1] =  (~dina[19] & ~dina[18] &  dina[17]            ) |
                       (~dina[19] & ~dina[18]                        ) ;

assign  eadj_nbyte5[0] = ( ab5_zeroh_l & ab5_cnth[0]) |
                         (~ab5_zeroh_l & ab5_cntl[0]) ;
assign  eadj_nbyte5[1] = ( ab5_zeroh_l & ab5_cnth[1]) |
                         (~ab5_zeroh_l & ab5_cntl[1]) ;
assign  eadj_nbyte5[2] =  ~ab5_zeroh_l                ;

// ----------------------------------------------------------------------------
// Norm LZD dina byte6 => dina[15:08]
// assume dina[10]  == 1'b1
// assume dina[9:8] == 2'b00
// ----------------------------------------------------------------------------

assign  ab6_nor_76  = ~(dina[15] | dina[14]);
assign  ab6_nor_54  = ~(dina[13] | dina[12]);

assign  ab6_zeroh_l = ~(ab6_nor_76 & ab6_nor_54);

assign  ab6_cnth[0] =  (~dina[15] &  dina[14]                        ) |
                       (~dina[15] &             ~dina[13] &  dina[12]) ;
assign  ab6_cnth[1] =  (~dina[15] & ~dina[14] &  dina[13]            ) |
                       (~dina[15] & ~dina[14] &              dina[12]) ;
assign  ab6_cntl[0] =  (~dina[11]                                    ) ;

assign  eadj_nbyte6[0] = ( ab6_zeroh_l & ab6_cnth[0]) |
                         (~ab6_zeroh_l & ab6_cntl[0]) ;
assign  eadj_nbyte6[1] = ( ab6_zeroh_l & ab6_cnth[1]) ;
assign  eadj_nbyte6[2] =  ~ab6_zeroh_l                ;

// ----------------------------------------------------------------------------
// Norm LZD Eadj[5:0] mux
// ----------------------------------------------------------------------------

assign  norm_eadj_fx4[5:0] =
//({6{(                     nbyte_sel[0])}} & ({3'b000, 3'b000          })) |
  ({6{(~( nbyte_sel[0]  ) & nbyte_sel[1])}} & ({3'b000, eadj_nbyte0[2:0]})) |
  ({6{(~(|nbyte_sel[1:0]) & nbyte_sel[2])}} & ({3'b001, eadj_nbyte1[2:0]})) |
  ({6{(~(|nbyte_sel[2:0]) & nbyte_sel[3])}} & ({3'b010, eadj_nbyte2[2:0]})) |
  ({6{(~(|nbyte_sel[3:0]) & nbyte_sel[4])}} & ({3'b011, eadj_nbyte3[2:0]})) |
  ({6{(~(|nbyte_sel[4:0]) & nbyte_sel[5])}} & ({3'b100, eadj_nbyte4[2:0]})) |
  ({6{(~(|nbyte_sel[5:0]) & nbyte_sel[6])}} & ({3'b101, eadj_nbyte5[2:0]})) |
  ({6{(~(|nbyte_sel[6:0])               )}} & ({3'b110, eadj_nbyte6[2:0]})) ;


// ----------------------------------------------------------------------------
//                               FX5 stage
// ----------------------------------------------------------------------------

fgu_fic_ctl_msff_ctl_macro__width_6 fx5_00  (
  .scan_in(fx5_00_scanin),
  .scan_out(fx5_00_scanout),
  .l1clk(l1clk_pm1),
  .din (    norm_eadj_fx4[5:0]),
  .dout(fic_norm_eadj_fx5[5:0]),
  .siclk(siclk),
  .soclk(soclk)
  );


supply0 vss;
supply1 vdd;
// fixscan start:
assign spares_scanin             = scan_in                  ;
assign fx2_00_scanin             = spares_scanout           ;
assign fx3_00_scanin             = fx2_00_scanout           ;
assign fx4_00_scanin             = fx3_00_scanout           ;
assign fx5_00_scanin             = fx4_00_scanout           ;
assign scan_out                  = fx5_00_scanout           ;
// fixscan end:
endmodule  // fgu_fic_ctl


// any PARAMS parms go into naming of macro

module fgu_fic_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module fgu_fic_ctl_spare_ctl_macro__num_2 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));
assign scan_out = so_1;


endmodule


// any PARAMS parms go into naming of macro

module fgu_fic_ctl_msff_ctl_macro__width_43 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [42:0] fdin;
wire [41:0] so;

  input [42:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [42:0] dout;
  output scan_out;
assign fdin[42:0] = din[42:0];


dff #(43)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[42:0]),
.si({scan_in,so[41:0]}),
.so({so[41:0],scan_out}),
.q(dout[42:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fic_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fic_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fic_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fpc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fpc_ctl (
  fpc_fpd_ieee_trap_fb, 
  fpc_fpx_unfin_fb, 
  fpc_fpd_unfin_fb, 
  fgu_fpx_ieee_trap_fw, 
  fgu_fpd_ieee_trap_fw, 
  fgu_fpx_unfin_fw, 
  fgu_fpd_unfin_fw, 
  fgu_fpd_idiv0_trap_fw, 
  fgu_predict_fx2, 
  lsu_fgu_exception_w, 
  lsu_block_store_m, 
  exu_fgu_flush_m, 
  exu_fgu_gsr_m, 
  fgu_exu_icc_fx5, 
  fgu_exu_xcc_fx5, 
  fad_rs1_fx1, 
  fad_rs2_fx1, 
  fad_fsr_rd_fx1, 
  fad_fsr_tem_fx1, 
  fad_fsr_ns_fx1, 
  fad_rs1_fmt_fx1_b62, 
  fad_rs2_fmt_fx1_b62, 
  fad_gsr_imirnd_fx1, 
  fpc_w1_vld_fb, 
  fpc_w1_ul_vld_fb, 
  fpc_fsr_w1_vld_fx5, 
  fpc_fsr_w1_result_fw, 
  fpc_fsr_w2_result_fw, 
  fpc_fpd_exp_res, 
  fpc_fpd_sign_res, 
  fpc_fpd_const_sel, 
  fpc_fcc_fw, 
  fpf_b_gteq_a_fx2, 
  fpf_b_eq_a_fx2, 
  fgu_cmp_fcc_fx3, 
  fgu_cmp_fcc_vld_fx3, 
  fpf_hi_aof_fx1, 
  fpf_lo_aof_fx1, 
  fpf_azf_fx1, 
  fpf_bzf_fx1, 
  fpf_aoe_fx1, 
  fpf_boe_fx1, 
  fpf_aze_fx1, 
  fpf_bze_fx1, 
  fpf_ma_sum_fx4, 
  fpf_ma_cout_fx4, 
  fpf_cmp_swap_blta_fx2, 
  fpf_align_sticky_fx4_l, 
  fpf_byte_unsure_x_sp_fx3, 
  fpf_byte_unsure_x_dp_fx3, 
  fpf_rcout_fb, 
  fpf_implied_bit_fx5, 
  fpc_result_sel_fx5, 
  fpc_ovf_if_rcout_fx5, 
  fpc_vis_cmp_result_fx5, 
  fpc_int_res_sel_fx4, 
  fpc_ma_fmt_sel_fx4, 
  fpc_int_sel_fx5, 
  fpc_fconst_sel_fx5, 
  fpc_fp_cin00_fx2, 
  fpc_cin00_fx2, 
  fpc_cin16_48_fx2, 
  fpc_cin32_fx2, 
  fpc_prop16_48_fx2, 
  fpc_prop32_fx2, 
  fpc_mle_sel_fx2, 
  fpc_mse_sel_fx2, 
  fpc_sign_fx5, 
  fpc_sign_fb, 
  fpc_rd_mode_fx3, 
  fpc_emin_fx3, 
  fpc_sp_dest_fx4, 
  fpc_fadd_eac_enable_fx2, 
  fpc_i2f_sel_fx1, 
  fpc_rinc_sel_fx5, 
  fpc_qthenan_fx4, 
  fpc_den2nor_sp_fb, 
  fpc_den2nor_dp_fb, 
  fpe_aux_rs2_fmt_fx1_b0, 
  fpe_aux_eint_fx1, 
  fpe_align_sel_fx2, 
  fpe_rs1_fmt_fx1, 
  fpe_rs2_fmt_fx1, 
  fpe_einty_adj_cout_fx5, 
  fpe_einty_eq_eadj_fx5, 
  fpc_exp_sel_mul_fx5, 
  fpc_eintx_sel_fx2, 
  fpc_eadjx_sel_fx2, 
  fpc_q_rinc_sel_fx5, 
  fac_tlu_flush_fx3, 
  fac_tid_e, 
  fac_dec_valid_fx1, 
  fac_fpx_itype_fx1, 
  fac_fpx_dtype_fx1, 
  fac_fpx_stype_fx1, 
  fac_fpx_sign_instr_fx1, 
  fac_fpx_rnd_trunc_fx1, 
  fac_fcmpe_fx1, 
  fac_fpx_mulscc_fx1, 
  fac_fpx_saverestore_fx1, 
  fac_fgx_pdist_fx1, 
  fac_fgx_popc_fx2, 
  fac_fgx_mvcond_fx2, 
  fac_fgx_mvucond_fx2, 
  fac_fgx_abs_fx2, 
  fac_fgx_neg_fx2, 
  fac_fpx_nv_vld_fx1, 
  fac_fpx_of_vld_fx1, 
  fac_fpx_uf_vld_fx1, 
  fac_fpx_dz_vld_fx1, 
  fac_fpx_nx_vld_fx1, 
  fac_fpx_unfin_vld_fx1, 
  fac_fgx_instr_fx4, 
  fac_w1_vld_fx1, 
  fac_w1_odd32b_fx1, 
  fac_opf_fx2, 
  fac_fgx_siam_fx2, 
  fac_div_valid_fx1, 
  fac_divq_valid_fx1, 
  fac_fsr_store_fx2, 
  fac_gsr_asr_tid_fx2, 
  fac_rng_wr_gsr_3f, 
  fac_gsr_w_vld_fx2, 
  fac_dec_valid_noflush_fx5, 
  fac_exu_src_e, 
  main_clken, 
  coreon_clken, 
  fpc_fcc_vld_fx5, 
  fpc_stfsr_en_fx3to5, 
  fic_norm_eadj_fx5, 
  fic_mulscc_iccz_fx4, 
  fic_mulscc_xccz_fx4, 
  fic_convert_sticky_fx4, 
  fic_fxtod_sticky_fx4, 
  fic_ftoi_nx_fx4, 
  fic_ftox_nx_fx4, 
  fic_bzf31msb_fx2, 
  fic_bzf32lsb_fx2, 
  fic_bof22msb_fx2, 
  fpc_lzd_override_fx4, 
  fpc_sp_source_fx3, 
  fdc_finish_fltd_early, 
  fdc_finish_flts_early, 
  fdc_finish_int_early, 
  fdc_flt_inexact, 
  fdc_xicc_z_early, 
  fdc_icc_v_early, 
  fdc_dec_exp_early, 
  fpc_pre_div_flush_fx2, 
  fpc_div_default_res_fx2, 
  fdd_result, 
  fdd_pte_cla_early_b63, 
  fgu_mul_result_fx5, 
  fpy_sticky_dp_fx5, 
  fpy_sticky_sp_fx5, 
  fpy_xicc_z_fx5, 
  dec_frf_r1_odd32b_d, 
  dec_frf_r2_odd32b_d, 
  dec_flush_f1, 
  dec_flush_f2, 
  dec_fgu_fmov_vld_m, 
  dec_valid_e, 
  dec_frf_store_d, 
  fec_cecc_fx2, 
  fec_uecc_fx2, 
  fpc_frf_store_vld_fx1, 
  fpc_gsr0_mask_sel_fx3, 
  fpc_gsr1_mask_sel_fx3, 
  fpc_gsr2_mask_sel_fx3, 
  fpc_gsr3_mask_sel_fx3, 
  fpc_gsr4_mask_sel_fx3, 
  fpc_gsr5_mask_sel_fx3, 
  fpc_gsr6_mask_sel_fx3, 
  fpc_gsr7_mask_sel_fx3, 
  fpc_gsr_scale_fx4, 
  fpc_gsr_align_fx4, 
  fpc_gsr_asr_11bits_fx4, 
  l2clk, 
  scan_in, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  mbi_run, 
  in_rngl_cdbus, 
  scan_out, 
  wmr_scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk_pm2;
wire l1clk_pm1;
wire spares_scanin;
wire spares_scanout;
wire e_00_scanin;
wire e_00_scanout;
wire r1_odd32b_e;
wire r2_odd32b_e;
wire frf_store_e;
wire fx1_00_scanin;
wire fx1_00_scanout;
wire [1:0] i_fst_valid_fx1;
wire fx1_01_scanin;
wire fx1_01_scanout;
wire r1_odd32b_fx1;
wire r2_odd32b_fx1;
wire [2:0] tid_fx1;
wire frf_store_fx1;
wire exu_src_fx1;
wire mbist_run_1f;
wire fst_valid_fx1;
wire int_rs2_zero_fx1;
wire idiv0_trap_fx1;
wire [3:0] eintx_sel_fx1;
wire fp_dual_source_fx1;
wire fp_source_fx1;
wire [2:0] eadjx_sel_fx1;
wire [1:0] rd_mode_fx1;
wire gsr_im_fx3;
wire [1:0] gsr_irnd_fx3;
wire ns_mode_fx1;
wire rs1_sign_fx1;
wire rs2_sign_fx1;
wire fadd_logical_sub_fx1;
wire logical_sub_fx1;
wire fadd_logical_add_fx1;
wire aux_enable_ovf_fx1;
wire fmul_enable_ovf_predict_fx1;
wire aux_eint_ovf_fx1;
wire aux_eint_emax_fx1;
wire aux_eint_emaxp1_fx1;
wire fadd_ovf_predict_fx1;
wire fdtos_ovf_predict_fx1;
wire fdtos_ovf_detect_fx1;
wire fmul_ovf_predict_fx1;
wire fmul_ovf_detect_fx1;
wire fdiv_ovf_predict_fx1;
wire fdiv_ovf_detect_fx1;
wire aux_enable_unf_fx1;
wire fdiv_enable_unf_predict_fx1;
wire aux_eint_unf_fx1;
wire aux_eint_emin_fx1;
wire aux_eint_eminm1_fx1;
wire aux_eint_eminm2_fx1;
wire fdtos_guf_detect_fx1;
wire fmul_guf_detect_fx1;
wire fdiv_guf_detect_fx1;
wire fdtos_unf_predict_fx1;
wire fdtos_unf_detect_fx1;
wire fmul_unf_predict_fx1;
wire fmul_unf_detect_fx1;
wire fdiv_unf_predict_fx1;
wire fdiv_unf_detect_fx1;
wire snan_or_inf_fx1;
wire nan_or_inf_fx1;
wire large_maxint_predict_fx1;
wire fadd_unf_predict_fx1;
wire fadd_fcvt_denorm_detect_fx1;
wire fmul_denorm_detect_fx1;
wire q_fmul_unf_predict_fx1;
wire i_predict_fx1;
wire fx2_00_scanin;
wire fx2_00_scanout;
wire [2:0] itype_fx2;
wire [2:0] dtype_fx2;
wire [1:0] stype_fx2;
wire sign_instr_fx2;
wire i_idiv0_trap_fx2;
wire dec_flush_fx2;
wire dec_valid_fx2;
wire fmov_vld_fx2;
wire div_valid_fx2;
wire divq_valid_fx2;
wire [0:0] aux_rs2_fmt_fx2;
wire fpx_nv_vld_fx2;
wire fpx_of_vld_fx2;
wire fpx_uf_vld_fx2;
wire fpx_dz_vld_fx2;
wire fpx_nx_vld_fx2;
wire fpx_unfin_vld_fx2;
wire fcmpe_fx2;
wire fp_source_fx2;
wire fp_dual_source_fx2;
wire rs1_sign_fx2;
wire rs2_sign_fx2;
wire fadd_logical_sub_fx2;
wire logical_sub_fx2;
wire fadd_logical_add_fx2;
wire hi_aof_fx2;
wire lo_aof_fx2;
wire aux_eint_eminm1_fx2;
wire aux_eint_eminm2_fx2;
wire aux_enable_unf_fx2;
wire [1:0] rd_mode_fx2;
wire ns_mode_fx2;
wire fst_valid_fx2;
wire [2:0] gsr_imirnd_fx2;
wire fgx_pdist_fx2;
wire exu_src_fx2;
wire fx2_01_scanin;
wire fx2_01_scanout;
wire mulscc_fx2;
wire mulscc_y_src_fx2_b0;
wire [10:0] rs2_exp_fx2;
wire saverestore_fx2;
wire fx2_02_scanin;
wire fx2_02_scanout;
wire [1:0] i_w1_vld_fx2;
wire w1_odd32b_fx2;
wire [10:0] aux_eint_fx2;
wire [2:0] tid_fx2;
wire fx2_03_scanin;
wire fx2_03_scanout;
wire rs1_fx2_b63;
wire rs1_fx2_b47;
wire rs1_fx2_b31;
wire rs1_fx2_b15;
wire fx2_04_scanin;
wire fx2_04_scanout;
wire rs2_fx2_b63;
wire rs2_fx2_b47;
wire rs2_fx2_b31;
wire rs2_fx2_b15;
wire fx2_05_scanin;
wire fx2_05_scanout;
wire azf_fx2;
wire bzf_fx2;
wire aoe_fx2;
wire boe_fx2;
wire aze_fx2;
wire bze_fx2;
wire fx2_06_scanin;
wire fx2_06_scanout;
wire [4:0] fsr_tem_fx2;
wire [62:62] rs1_fmt_fx2;
wire [62:62] rs2_fmt_fx2;
wire fx2_07_scanin;
wire fx2_07_scanout;
wire fadd_ovf_predict_fx2;
wire fdtos_ovf_predict_fx2;
wire fdtos_ovf_detect_fx2;
wire fmul_ovf_predict_fx2;
wire fmul_ovf_detect_fx2;
wire fdiv_ovf_predict_fx2;
wire fdiv_ovf_detect_fx2;
wire fdtos_unf_predict_fx2;
wire fdtos_unf_detect_fx2;
wire fmul_unf_predict_fx2;
wire fmul_unf_detect_fx2;
wire fdiv_unf_predict_fx2;
wire fdiv_unf_detect_fx2;
wire fdtos_guf_detect_fx2;
wire fmul_guf_detect_fx2;
wire fdiv_guf_detect_fx2;
wire i_predict_fx2;
wire fmul_denorm_detect_fx2;
wire q_fmul_unf_predict_fx2;
wire fadd_fcvt_denorm_detect_fx2;
wire fx2_08_scanin;
wire fx2_08_scanout;
wire [27:0] in_rngl_cdbus_1f;
wire exu_flush_fx2;
wire [2:0] gsr_align_fx2;
wire [1:0] w1_vld_fx2;
wire [1:0] fsr_w1_vld_fx2;
wire [1:0] gsr_w_vld_fx2;
wire fgx_siam_fx2;
wire sign_nan_fx2;
wire nan_rs2prop_fx2;
wire nan_rs1prop_fx2;
wire [4:0] sign_inter_sel_fx2;
wire a_nan_fx2;
wire b_nan_fx2;
wire sign_inter_fx2;
wire sp_odd_exp_fx2;
wire sp_even_exp_fx2;
wire dp_odd_exp_fx2;
wire dp_even_exp_fx2;
wire [10:0] fpd_eint_fx2;
wire [3:0] fcmpgt16_fx2;
wire [1:0] gt32_fx2;
wire [1:0] fcmpgt32_fx2;
wire [3:0] fcmple16_fx2;
wire [1:0] le32_fx2;
wire [1:0] fcmple32_fx2;
wire [3:0] fcmpeq16_fx2;
wire [1:0] fcmpeq32_fx2;
wire [3:0] fcmpne16_fx2;
wire [1:0] fcmpne32_fx2;
wire fcmpgt16_sel_fx2;
wire fcmpgt32_sel_fx2;
wire fcmple16_sel_fx2;
wire fcmple32_sel_fx2;
wire fcmpne16_sel_fx2;
wire fcmpne32_sel_fx2;
wire fcmpeq16_sel_fx2;
wire fcmpeq32_sel_fx2;
wire [3:0] vis_cmp_result_fx2;
wire a_zero_fx2;
wire a_denorm_fx2;
wire a_inf_fx2;
wire a_snan_fx2;
wire b_zero_fx2;
wire b_denorm_fx2;
wire b_inf_fx2;
wire b_snan_fx2;
wire b_qnan_fx2;
wire unfin_src_fx2;
wire inf_src_result_fx2;
wire zero_src_result_fx2;
wire inf_maxint_result_fx2;
wire nan_maxint_result_fx2;
wire nan_default_result_fx2;
wire fpx_dzc_fx2;
wire i_fxp_nvc_fx2;
wire fcmp_nvc_fx2;
wire local_predict_fx2;
wire qthenan_fx2;
wire rm_near_dp_fx2;
wire rm_directed_dp_fx2;
wire rm_near_sp_fx2;
wire rm_directed_sp_fx2;
wire fdiv_aof_bzf_fx2;
wire fmul_den2nor_m2_predict_fx2;
wire fdiv_den2nor_m1_predict_fx2;
wire fdiv_den2nor_sp_fx2;
wire fdiv_den2nor_dp_fx2;
wire mse_zeros_fx2;
wire mse_ones_fx2;
wire mle_zeros_fx2;
wire mass_align_fx2;
wire mass_align_sticky_fx2;
wire [5:1] int_res_sel_fx2;
wire i_pre_div_flush_fx2;
wire idiv0_trap_fx2;
wire aboe_fx2;
wire abze_fx2;
wire [1:0] gsr0_mask_sel_fx2;
wire [1:0] gsr1_mask_sel_fx2;
wire [1:0] gsr2_mask_sel_fx2;
wire [1:0] gsr3_mask_sel_fx2;
wire [1:0] gsr4_mask_sel_fx2;
wire [1:0] gsr5_mask_sel_fx2;
wire [1:0] gsr6_mask_sel_fx2;
wire [1:0] gsr7_mask_sel_fx2;
wire sp_source_fx2;
wire ecc_trap_fx2;
wire fx3_00_scanin;
wire fx3_00_scanout;
wire [1:0] i_w1_vld_fx3;
wire [2:0] itype_fx3;
wire [2:0] dtype_fx3;
wire [1:0] stype_fx3;
wire [2:0] tid_fx3;
wire fx3_01_scanin;
wire fx3_01_scanout;
wire [3:0] vis_cmp_result_fx3;
wire [5:1] int_res_sel_fx3;
wire [10:0] fpd_eint_fx3;
wire fx3_02_scanin;
wire fx3_02_scanout;
wire rs1_fx3_b31;
wire rs2_fx3_b31;
wire [10:0] rs2_exp_fx3;
wire fx3_03_scanin;
wire fx3_03_scanout;
wire bzf_fx3;
wire bze_fx3;
wire a_nan_fx3;
wire b_nan_fx3;
wire fx3_04_scanin;
wire fx3_04_scanout;
wire [4:0] fsr_tem_fx3;
wire fx3_05_scanin;
wire fx3_05_scanout;
wire inf_src_result_fx3;
wire zero_src_result_fx3;
wire inf_maxint_result_fx3;
wire nan_maxint_result_fx3;
wire nan_default_result_fx3;
wire qthenan_fx3;
wire bzf31msb_fx3;
wire fmul_den2nor_m2_predict_fx3;
wire fdiv_den2nor_sp_fx3;
wire fdiv_den2nor_dp_fx3;
wire fx3_06_scanin;
wire fx3_06_scanout;
wire i_idiv0_trap_fx3;
wire dec_flush_fx3;
wire sign_inter_fx3;
wire div_valid_fx3;
wire divq_valid_fx3;
wire logical_sub_fx3;
wire [1:0] i_fsr_w1_vld_fx3;
wire w1_odd32b_fx3;
wire mass_align_sticky_fx3;
wire fadd_logical_sub_fx3;
wire fsr_store_fx3;
wire i_fgx_siam_fx3;
wire [1:1] i_gsr_w_vld_fx3;
wire [2:0] gsr_asr_tid_fx3;
wire rm_near_sp_fx3;
wire rm_near_dp_fx3;
wire rm_directed_sp_fx3;
wire rm_directed_dp_fx3;
wire aboe_fx3;
wire abze_fx3;
wire div_default_res_fx3;
wire fgx_pdist_fx3;
wire fx3_07_scanin;
wire fx3_07_scanout;
wire fadd_ovf_predict_fx3;
wire fdtos_ovf_predict_fx3;
wire fdtos_ovf_detect_fx3;
wire fmul_ovf_predict_fx3;
wire fmul_ovf_detect_fx3;
wire fdiv_ovf_predict_fx3;
wire fdiv_ovf_detect_fx3;
wire fdtos_unf_predict_fx3;
wire fdtos_unf_detect_fx3;
wire fmul_unf_predict_fx3;
wire fmul_unf_detect_fx3;
wire fdiv_unf_predict_fx3;
wire fdiv_unf_detect_fx3;
wire bof22msb_fx3;
wire fdtos_guf_detect_fx3;
wire fmul_guf_detect_fx3;
wire fdiv_guf_detect_fx3;
wire unfin_src_fx3;
wire fx3_08_scanin;
wire fx3_08_scanout;
wire [1:0] gsr0_mask_sel_fx3;
wire [1:0] gsr1_mask_sel_fx3;
wire [1:0] gsr2_mask_sel_fx3;
wire [1:0] gsr3_mask_sel_fx3;
wire [1:0] gsr4_mask_sel_fx3;
wire [1:0] gsr5_mask_sel_fx3;
wire [1:0] gsr6_mask_sel_fx3;
wire [1:0] gsr7_mask_sel_fx3;
wire fx3_09_scanin;
wire fx3_09_scanout;
wire [2:0] in_rngl_cdbus_2f_b27_25;
wire [7:0] in_rngl_cdbus_2f;
wire [2:0] gsr_align_fx3;
wire [2:0] gsr_imirnd_fx3;
wire fx3_10_scanin;
wire fx3_10_scanout;
wire fpx_unfin_vld_fx3;
wire ns_mode_fx3;
wire fpx_of_vld_fx3;
wire fpx_uf_vld_fx3;
wire fpx_nx_vld_fx3;
wire ecc_trap_fx3;
wire fpx_dzc_fx3;
wire i_fxp_nvc_fx3;
wire rng_wr_gsr_4f;
wire [1:1] gsr_w_vld_fx3;
wire fgx_siam_fx3;
wire idiv0_trap_fx3;
wire [1:0] w1_vld_fx3;
wire [1:0] fsr_w1_vld_fx3;
wire lzd_override_fx3;
wire div_dec_issue_fx3;
wire div_divq_issue_fx3;
wire div_divq_load_fx3;
wire div_hold_fx3;
wire fdiv_ovf_predict_inf_fx3;
wire fdiv_ovf_predict_max_fx3;
wire [18:0] div_eint_in_fx3;
wire [18:0] divq_eint_fx4;
wire [18:0] div_eint_fx4;
wire [18:0] divq_eint_in_fx3;
wire dpint_zero_fx3;
wire spint_zero_fx3;
wire fpint_zero_fx3;
wire dp_large_maxint_result_fx3;
wire sp_large_maxint_result_fx3;
wire maxint_result_fx3;
wire fpx_nvc_fx3;
wire [10:0] gsr0_11bits_fx3;
wire [2:0] in_rngl_cdbus_3f_b27_25;
wire [7:0] in_rngl_cdbus_3f;
wire [10:0] gsr0_11bits_fx4;
wire [10:0] gsr1_11bits_fx3;
wire [10:0] gsr1_11bits_fx4;
wire [10:0] gsr2_11bits_fx3;
wire [10:0] gsr2_11bits_fx4;
wire [10:0] gsr3_11bits_fx3;
wire [10:0] gsr3_11bits_fx4;
wire [10:0] gsr4_11bits_fx3;
wire [10:0] gsr4_11bits_fx4;
wire [10:0] gsr5_11bits_fx3;
wire [10:0] gsr5_11bits_fx4;
wire [10:0] gsr6_11bits_fx3;
wire [10:0] gsr6_11bits_fx4;
wire [10:0] gsr7_11bits_fx3;
wire [10:0] gsr7_11bits_fx4;
wire [7:0] gsr_11bits_fx3;
wire [10:0] gsr_asr_11bits_fx3;
wire [2:0] gsr_imirnd_held_fx3;
wire siam_1ahead_sel_fx3;
wire siam_2ahead_sel_fx3;
wire siam_none_sel_fx3;
wire fx4_00_scanin;
wire fx4_00_scanout;
wire rs1_fx4_b31;
wire rs2_fx4_b31;
wire [1:0] rd_mode_fx4;
wire fx4_01_scanin;
wire fx4_01_scanout;
wire [1:0] i_w1_vld_fx4;
wire [1:0] fcc_fx4;
wire [3:0] fcc_vld_fx4;
wire idiv0_trap_fx4;
wire sign_inter_fx4;
wire logical_sub_fx4;
wire fpint_zero_fx4;
wire [1:0] i_fsr_w1_vld_fx4;
wire a_nan_fx4;
wire b_nan_fx4;
wire [1:0] byte_unsure_x_dp_fx4;
wire [1:0] byte_unsure_x_sp_fx4;
wire w1_odd32b_fx4;
wire mass_align_sticky_fx4;
wire fadd_logical_sub_fx4;
wire fsr_store_fx4;
wire fmul_den2nor_m2_predict_fx4;
wire fdiv_den2nor_sp_fx4;
wire fdiv_den2nor_dp_fx4;
wire rm_near_sp_fx4;
wire rm_near_dp_fx4;
wire rm_directed_sp_fx4;
wire rm_directed_dp_fx4;
wire aboe_fx4;
wire abze_fx4;
wire div_default_res_fx4;
wire dec_flush_fx4;
wire tlu_flush_fgu_fx4;
wire fx4_02_scanin;
wire fx4_02_scanout;
wire [3:0] vis_cmp_result_fx4;
wire [2:0] itype_fx4;
wire [2:0] dtype_fx4;
wire fx4_03_scanin;
wire fx4_03_scanout;
wire fx4_04_scanin;
wire fx4_04_scanout;
wire [4:0] fsr_tem_fx4;
wire fx4_05_scanin;
wire fx4_05_scanout;
wire inf_src_result_fx4;
wire zero_src_result_fx4;
wire nan_default_result_fx4;
wire maxint_result_fx4;
wire fx4_06_scanin;
wire fx4_06_scanout;
wire fadd_ovf_predict_fx4;
wire fdtos_ovf_predict_fx4;
wire fdtos_ovf_detect_fx4;
wire fmul_ovf_predict_fx4;
wire fmul_ovf_detect_fx4;
wire fdiv_ovf_detect_fx4;
wire fdtos_unf_predict_fx4;
wire fdtos_unf_detect_fx4;
wire fmul_unf_predict_fx4;
wire fmul_unf_detect_fx4;
wire fdiv_unf_detect_fx4;
wire bof22msb_fx4;
wire fdtos_guf_detect_fx4;
wire fmul_guf_detect_fx4;
wire fdiv_guf_detect_fx4;
wire unfin_src_fx4;
wire fx4_07_wmr_scanin;
wire fx4_07_wmr_scanout;
wire fx4_08_scanin;
wire fx4_08_scanout;
wire fpx_unfin_vld_fx4;
wire ns_mode_fx4;
wire fpx_of_vld_fx4;
wire fpx_uf_vld_fx4;
wire fpx_nx_vld_fx4;
wire ecc_trap_fx4;
wire fpx_dzc_fx4;
wire fpx_nvc_fx4;
wire fx4_09_scanin;
wire fx4_09_scanout;
wire fx4_10_scanin;
wire fx4_10_scanout;
wire stfsr_exception_fx4;
wire fx4_11_scanin;
wire fx4_11_scanout;
wire maxpos_result_fx4;
wire maxneg_result_fx4;
wire [3:0] int_sel_fx4;
wire mulscc_iccn_fx4;
wire mulscc_iccc_fx4;
wire mulscc_iccv_fx4;
wire exp_sel_mul_fx4;
wire [1:0] fpd_const_sel;
wire [10:0] fpd_exp_res;
wire sign_retain_zero_fx4;
wire sign_zero_fx4;
wire add_ma_cout_fx4;
wire convert_fmt_1xx_fx4;
wire convert_fmt_01x_fx4;
wire fxtod_fmt_1xx_fx4;
wire fxtod_fmt_01x_fx4;
wire add_fmt_1xx_fx4;
wire add_fmt_01x_fx4;
wire add_fmt_001_fx4;
wire aln_fmt_1xx_fx4;
wire aln_fmt_01x_fx4;
wire add_lsb_bit_dp_fx4;
wire add_g_bit_dp_fx4;
wire add_lsb_bit_sp_fx4;
wire add_g_bit_sp_fx4;
wire align_x_bit_dp_fx4;
wire align_x_bit_sp_fx4;
wire convert_x_bit_sp_fx4;
wire fxtod_x_bit_dp_fx4;
wire add_x_bit_dp_fx4;
wire add_x_bit_sp_fx4;
wire fpint_nxc_i_fx4;
wire fpint_nxc_x_fx4;
wire fpint_nxc_fx4;
wire fdtos_den2nor_fx4;
wire fdiv_fdtos_den2nor_sp_fx4;
wire [1:0] w1_vld_fx4;
wire [1:0] fsr_w1_vld_fx4;
wire fx5_00_scanin;
wire fx5_00_scanout;
wire [1:0] w1_vld_fx5;
wire [1:0] fcc_fx5;
wire fx5_01_scanin;
wire fx5_01_scanout;
wire [2:0] itype_fx5;
wire [2:0] dtype_fx5;
wire [1:0] rd_mode_fx5;
wire fx5_02_scanin;
wire fx5_02_scanout;
wire int_res_sel_fx5_b2;
wire ma_fmt_sel_fx5_b0;
wire idiv0_trap_fx5;
wire mulscc_iccn_fx5;
wire mulscc_iccz_fx5;
wire mulscc_iccv_fx5;
wire mulscc_iccc_fx5;
wire mulscc_xccz_fx5;
wire idiv_xccz_fx5;
wire idiv_iccz_fx5;
wire idiv_iccv_fx5;
wire sign_inter_fx5;
wire sign_zero_fx5;
wire ma_sum_fx5_b10;
wire fgx_instr_fx5;
wire w1_odd32b_fx5;
wire ma_cout_fx5;
wire fadd_logical_sub_fx5;
wire fsr_store_fx5;
wire fmul_den2nor_m2_predict_fx5;
wire fdiv_fdtos_den2nor_sp_fx5;
wire fdiv_den2nor_dp_fx5;
wire aboe_fx5;
wire fpint_nxc_fx5;
wire fx5_04_scanin;
wire fx5_04_scanout;
wire [4:0] fsr_tem_fx5;
wire fx5_05_scanin;
wire fx5_05_scanout;
wire rm_near_dp_fx5;
wire rm_near_sp_fx5;
wire rm_directed_dp_fx5;
wire rm_directed_sp_fx5;
wire fx5_06_scanin;
wire fx5_06_scanout;
wire add_g_bit_sp_fx5;
wire add_g_bit_dp_fx5;
wire add_lsb_bit_sp_fx5;
wire add_lsb_bit_dp_fx5;
wire add_x_bit_sp_fx5;
wire add_x_bit_dp_fx5;
wire fx5_07_scanin;
wire fx5_07_scanout;
wire inf_src_result_fx5;
wire zero_src_result_fx5;
wire nan_default_result_fx5;
wire maxint_result_fx5;
wire fx5_08_scanin;
wire fx5_08_scanout;
wire fadd_ovf_predict_fx5;
wire fdtos_ovf_predict_fx5;
wire fdtos_ovf_detect_fx5;
wire fmul_ovf_predict_fx5;
wire fmul_ovf_detect_fx5;
wire fdiv_ovf_detect_fx5;
wire fdtos_unf_predict_fx5;
wire fdtos_unf_detect_fx5;
wire fmul_unf_predict_fx5;
wire fmul_unf_detect_fx5;
wire fdiv_unf_detect_fx5;
wire fdtos_guf_detect_fx5;
wire fmul_guf_detect_fx5;
wire fdiv_guf_detect_fx5;
wire unfin_src_fx5;
wire fx5_09_scanin;
wire fx5_09_scanout;
wire fpx_unfin_vld_fx5;
wire ns_mode_fx5;
wire fpx_of_vld_fx5;
wire fpx_uf_vld_fx5;
wire fpx_nx_vld_fx5;
wire ecc_trap_fx5;
wire fpx_dzc_fx5;
wire fpx_nvc_fx5;
wire dp_zero_mant_fx5;
wire sp_zero_mant_fx5;
wire zero_mant_fx5;
wire ovf_detect_inf_fx5;
wire ovf_predict_inf_fx5;
wire ovf_detect_max_fx5;
wire ovf_predict_max_fx5;
wire unf_detect_fx5;
wire unf_predict_fx5;
wire unfin_early_fx5;
wire fpd_unfin_fx5;
wire fdiv_den2nor_m0_fx5;
wire i_fpx_ofc_fx5;
wire i_fpx_ufc_fx5;
wire eadj_unf_if_norcout_fx5;
wire mul_fmt_1xx_fx5;
wire mul_fmt_01x_fx5;
wire mul_fmt_m2_fx5;
wire mul_lsb_bit_dp_fx5;
wire mul_g_bit_dp_fx5;
wire mul_x_bit_dp_fx5;
wire mul_lsb_bit_sp_fx5;
wire mul_g_bit_sp_fx5;
wire mul_x_bit_sp_fx5;
wire mul_rinc_dp_fx5;
wire mul_rinc_sp_fx5;
wire mul_rinc_sel_fx5;
wire add_rinc_dp_fx5;
wire add_rinc_sp_fx5;
wire add_rinc_sel_fx5;
wire ovf_if_rcout_fx5;
wire fmul_unf_if_nocorl_fx5;
wire fmul_unf_if_nocorl_sp_fx5;
wire fmul_unf_if_nocorl_dp_fx5;
wire i_fpx_nxc_fx5;
wire div_finish_int_fb;
wire fb_00_scanin;
wire fb_00_scanout;
wire [1:0] fcc_fb;
wire idiv0_trap_fb;
wire ovf_if_rcout_fb;
wire fmul_unf_if_nocorl_sp_fb;
wire fmul_unf_if_nocorl_dp_fb;
wire fmul_unf_if_nocorl_fb;
wire eadj_unf_if_norcout_fb;
wire implied_bit_fb;
wire fsr_store_fb;
wire dec_valid_noflush_fb;
wire sp_zero_mant_fb;
wire dp_zero_mant_fb;
wire div_finish_fltd_fb;
wire div_finish_flts_fb;
wire fb_01_scanin;
wire fb_01_scanout;
wire [1:0] i_w1_vld_fb;
wire fb_03_scanin;
wire fb_03_scanout;
wire fpx_unfin_vld_fb;
wire ns_mode_fb;
wire unfin_early_fb;
wire fpx_of_vld_fb;
wire fpx_uf_vld_fb;
wire ecc_trap_fb;
wire fpx_dzc_fb;
wire fpx_nvc_fb;
wire i_fpx_ofc_fb;
wire i_fpx_ufc_fb;
wire i_fpx_nxc_fb;
wire fdiv_fdtos_den2nor_sp_fb;
wire fdiv_den2nor_dp_fb;
wire fdiv_den2nor_m0_fb;
wire div_dec_exp_fb;
wire fb_04_scanin;
wire fb_04_scanout;
wire [4:0] fsr_tem_fb;
wire fb_05_scanin;
wire fb_05_scanout;
wire i_fpc_fpd_exp_res_b0;
wire fpd_fsr_ofm_fb;
wire fpd_fsr_ufm_fb;
wire fpd_fsr_nxm_fb;
wire fpx_ofc_fb;
wire fpx_ufc_fb;
wire fpx_nxc_fb;
wire fpd_ofc_fb;
wire fpd_ufc_fb;
wire fpd_nxc_fb;
wire fpx_ieee_trap_fb;
wire [1:0] fpx_ftt_fb;
wire [1:0] fpd_ftt_fb;
wire [4:0] fpx_aexc_fb;
wire [4:0] fpd_aexc_fb;
wire [11:0] fsr_w1_result_fb;
wire [11:0] fsr_w2_result_fb;
wire fw_00_scanin;
wire fw_00_scanout;


// ----------------------------------------------------------------------------
// Interface with TLU
// ----------------------------------------------------------------------------

output         fpc_fpd_ieee_trap_fb;
output         fpc_fpx_unfin_fb;
output         fpc_fpd_unfin_fb;

output         fgu_fpx_ieee_trap_fw;
output         fgu_fpd_ieee_trap_fw;
output         fgu_fpx_unfin_fw;
output         fgu_fpd_unfin_fw;
output         fgu_fpd_idiv0_trap_fw;
output         fgu_predict_fx2;        // exception trap predicted

// ----------------------------------------------------------------------------
// Interface with LSU
// ----------------------------------------------------------------------------

input          lsu_fgu_exception_w;    // store exception detected
input          lsu_block_store_m;      // block store in progress

// ----------------------------------------------------------------------------
// Interface with EXU
// ----------------------------------------------------------------------------

input          exu_fgu_flush_m;        // EXU{1,0} src has bad ECC or exception, FGU must flush instr
input    [2:0] exu_fgu_gsr_m;          // GSR.align data:
                                       //   [31:3] = don't care
                                       //   [2:0]  = GSR.align
                                       //   GSR.mask data:
                                       //   [31:0] = GSR.mask

output   [3:0] fgu_exu_icc_fx5;
output   [1:0] fgu_exu_xcc_fx5;

// ----------------------------------------------------------------------------
// Interface with FAD
// ----------------------------------------------------------------------------

input  [63:15] fad_rs1_fx1;            // rs1 unformatted
input  [63:15] fad_rs2_fx1;            // rs2 unformatted
input    [1:0] fad_fsr_rd_fx1;
input    [4:0] fad_fsr_tem_fx1;
input          fad_fsr_ns_fx1;
input          fad_rs1_fmt_fx1_b62;
input          fad_rs2_fmt_fx1_b62;
input    [2:0] fad_gsr_imirnd_fx1;     // {GSR.im,GSR.irnd[1:0]}

output   [1:0] fpc_w1_vld_fb;          // FRF w1 write valid (qualified), [63:32],[31:0]
output         fpc_w1_ul_vld_fb;       // FRF w1 write valid (qualified), upper or lower
output   [1:0] fpc_fsr_w1_vld_fx5;     // FSR w1 write valid
output  [11:0] fpc_fsr_w1_result_fw;   // FSR w1 write data  {ftt,aexc,cexc}
output  [11:0] fpc_fsr_w2_result_fw;   // FSR w2 write data  {ftt,aexc,cexc}
output  [10:0] fpc_fpd_exp_res;        // FPD exponent result
output         fpc_fpd_sign_res;       // FPD sign result
output   [1:0] fpc_fpd_const_sel;      // 10=ones frac, 01=fdd frac, 00=zero frac
output   [1:0] fpc_fcc_fw;

// ----------------------------------------------------------------------------
// Interface with FPF
// ----------------------------------------------------------------------------

input    [3:0] fpf_b_gteq_a_fx2;       // FCMP (B-A) cout, doesn't account for MSB
input    [3:0] fpf_b_eq_a_fx2;         // FCMP (B=A), doesn't account for MSB
input    [1:0] fgu_cmp_fcc_fx3;        // fcmp  fcc data {fccX[1:0]}
input    [3:0] fgu_cmp_fcc_vld_fx3;    // fcmp  fcc data valid {fcc3, fcc2, fcc1, fcc0}
input          fpf_hi_aof_fx1;
input          fpf_lo_aof_fx1;
input          fpf_azf_fx1;            // rs1[62:0]==63'b0, must acct for rs1[63]
input          fpf_bzf_fx1;            // rs2[62:0]==63'b0, must acct for rs2[63]
input          fpf_aoe_fx1;
input          fpf_boe_fx1;
input          fpf_aze_fx1;
input          fpf_bze_fx1;
input   [63:9] fpf_ma_sum_fx4;         // main adder sum
input          fpf_ma_cout_fx4;        // main adder cout
input          fpf_cmp_swap_blta_fx2;
input          fpf_align_sticky_fx4_l;
input    [1:0] fpf_byte_unsure_x_sp_fx3;
input    [1:0] fpf_byte_unsure_x_dp_fx3;
input          fpf_rcout_fb;
input          fpf_implied_bit_fx5;

output   [5:0] fpc_result_sel_fx5;     // result select
output   [1:0] fpc_ovf_if_rcout_fx5;   // result select qualification for rcout
output   [3:0] fpc_vis_cmp_result_fx5; // vis cmp result data
output   [5:1] fpc_int_res_sel_fx4;    // select result for EXU{1,0}
output   [4:0] fpc_ma_fmt_sel_fx4;
output   [3:0] fpc_int_sel_fx5;        // 10=vis paritioned add or F(s,d)TO(i,x), 01=F(s,d)TO(i,x) zero result
output   [4:0] fpc_fconst_sel_fx5;
output         fpc_fp_cin00_fx2;       // main adder control
output         fpc_cin00_fx2;          // main adder control
output         fpc_cin16_48_fx2;       // main adder control
output         fpc_cin32_fx2;          // main adder control
output         fpc_prop16_48_fx2;      // main adder control
output         fpc_prop32_fx2;         // main adder control
output         fpc_mle_sel_fx2;
output   [2:0] fpc_mse_sel_fx2;
output         fpc_sign_fx5;           // result sign
output         fpc_sign_fb;            // result sign
output   [1:0] fpc_rd_mode_fx3;        // merged GSR.irnd, FSR.rd
output         fpc_emin_fx3;           // FDIV Eint=Emin
output         fpc_sp_dest_fx4;        // SP result dest
output         fpc_fadd_eac_enable_fx2;
output   [3:2] fpc_i2f_sel_fx1;        // 10=F(i,x)TO(s,d) 2's comp, 01=F(i,x)TO(s,d) not 2's comp
output         fpc_rinc_sel_fx5;
output         fpc_qthenan_fx4;        // quiet the propagating NaN, set frac MSB=1
output         fpc_den2nor_sp_fb;      // denorm intermediate result rounded to norm
output         fpc_den2nor_dp_fb;      // denorm intermediate result rounded to norm

// ----------------------------------------------------------------------------
// Interface with FPE
// ----------------------------------------------------------------------------

input          fpe_aux_rs2_fmt_fx1_b0;
input   [11:0] fpe_aux_eint_fx1;
input   [10:0] fpe_align_sel_fx2;
input   [10:0] fpe_rs1_fmt_fx1;
input   [10:0] fpe_rs2_fmt_fx1;
input          fpe_einty_adj_cout_fx5;
input          fpe_einty_eq_eadj_fx5;
output         fpc_exp_sel_mul_fx5;
output   [3:0] fpc_eintx_sel_fx2;      // FxTOs|FiTOs=001, FxTOd|FiTOd=010, F(s)MUL(s,d)=100
output   [2:0] fpc_eadjx_sel_fx2;      // F(i,x)TO(s,d)=001, FsTOd=010, FdTOs=100
output         fpc_q_rinc_sel_fx5;     // rinc_sel and ~logical_sub 00.1X

// ----------------------------------------------------------------------------
// Interface with FAC
// ----------------------------------------------------------------------------

input          fac_tlu_flush_fx3;
input    [2:0] fac_tid_e;
input          fac_dec_valid_fx1;
input    [2:0] fac_fpx_itype_fx1;      // instr type:
                                       // add=000, fpfp=001, fpint=010, intfp=011, cmp=100, mul=101, div=110, sqrt=111
input    [2:0] fac_fpx_dtype_fx1;      // destination type:
                                       // sp=000, dp=001, 16bit=010, 32bit=011, 64bit=100
input    [1:0] fac_fpx_stype_fx1;      // source type (for conversions & FsMULd/FMULd):
                                       // sp=00, dp=01, 32bit=10, 64bit=11
input          fac_fpx_sign_instr_fx1; // sign of the instr (1 if: FSUB(s,d),
                                       // FPSUB{16,32}{s})
input          fac_fpx_rnd_trunc_fx1;  // force rnd mode to truncate
                                       // (1 if: F(s,d)TOi, F(s,d)TOx,
                                       // FPADD{16,32}{s}, FPSUB{16,32}{s},
                                       // IMUL, IDIV, MULScc, 8x16 mul, SAVE, RESTORE
input          fac_fcmpe_fx1;          // FCMPE, not FCMP
input          fac_fpx_mulscc_fx1;     // MULScc
input          fac_fpx_saverestore_fx1;// SAVE or RESTORE
input          fac_fgx_pdist_fx1;      // PDIST
input          fac_fgx_popc_fx2;       // POPC
input          fac_fgx_mvcond_fx2;     // FMOV (conditional upon cc or r)
input          fac_fgx_mvucond_fx2;    // FMOV (unconditional)
input          fac_fgx_abs_fx2;        // FABS
input          fac_fgx_neg_fx2;        // FNEG
input          fac_fpx_nv_vld_fx1;     // set if instr updates invalid exception flag
input          fac_fpx_of_vld_fx1;     // set if instr updates overflow exception flag
input          fac_fpx_uf_vld_fx1;     // set if instr updates underflow exception flag
input          fac_fpx_dz_vld_fx1;     // set if instr updates divide by zero exception flag
input          fac_fpx_nx_vld_fx1;     // set if instr updates inexact exception flag
input          fac_fpx_unfin_vld_fx1;  // set if instr can generate unfinished_FPop

input          fac_fgx_instr_fx4;      // FGX instr decoded
input    [1:0] fac_w1_vld_fx1;
input          fac_w1_odd32b_fx1;

input    [3:1] fac_opf_fx2;            // instr opf field
input          fac_fgx_siam_fx2;       // SIAM
input          fac_div_valid_fx1;
input          fac_divq_valid_fx1;
input          fac_fsr_store_fx2;

input    [2:0] fac_gsr_asr_tid_fx2;
input          fac_rng_wr_gsr_3f;      // ASR GSR  write valid
input    [1:0] fac_gsr_w_vld_fx2;
input          fac_dec_valid_noflush_fx5;
input          fac_exu_src_e;

input          main_clken;             // main clken
input          coreon_clken;           // controls all "free running" flops

output   [3:0] fpc_fcc_vld_fx5;
output         fpc_stfsr_en_fx3to5;    // store FSR clears ftt

// ----------------------------------------------------------------------------
// Interface with FIC
// ----------------------------------------------------------------------------

input    [5:0] fic_norm_eadj_fx5;
input          fic_mulscc_iccz_fx4;
input          fic_mulscc_xccz_fx4;
input          fic_convert_sticky_fx4; // sticky for FxTOs, FiTOs, FdTOs
input          fic_fxtod_sticky_fx4;   // sticky for FxTOd
input          fic_ftoi_nx_fx4;        // inexact for FsTOi, FdTOi
input          fic_ftox_nx_fx4;        // inexact for FsTOx, FdTOx
input          fic_bzf31msb_fx2;       // rs2 frac 31 MSBs all zeros
input          fic_bzf32lsb_fx2;       // rs2 frac 32 LSBs all zeros
input          fic_bof22msb_fx2;       // rs2 frac 22 MSBs all ones
output         fpc_lzd_override_fx4;
output         fpc_sp_source_fx3;

// ----------------------------------------------------------------------------
// Interface with FDC
// ----------------------------------------------------------------------------

input 	       fdc_finish_fltd_early;
input          fdc_finish_flts_early;
input          fdc_finish_int_early;
input          fdc_flt_inexact;
input    [1:0] fdc_xicc_z_early;       // {xcc.z, icc.z} (one cyc before result data)
input          fdc_icc_v_early;        // icc.v          (one cyc before result data)
input          fdc_dec_exp_early;      // decrement Eint (one cyc before result data)
output         fpc_pre_div_flush_fx2;
output         fpc_div_default_res_fx2; // fdiv/fsqrt default result

// ----------------------------------------------------------------------------
// Interface with FDD
// ----------------------------------------------------------------------------

input  [63:31] fdd_result;
input          fdd_pte_cla_early_b63;

// ----------------------------------------------------------------------------
// Interface with FPY
// ----------------------------------------------------------------------------

input   [63:9] fgu_mul_result_fx5;
input          fpy_sticky_dp_fx5;
input          fpy_sticky_sp_fx5;
input    [1:0] fpy_xicc_z_fx5;         // {xcc.z, icc.z}

// ----------------------------------------------------------------------------
// Interface with DEC
// ----------------------------------------------------------------------------

input          dec_frf_r1_odd32b_d;
input          dec_frf_r2_odd32b_d;
input          dec_flush_f1;           // flush fx2 (xmit in fx1/m)
input          dec_flush_f2;           // flush fx3 (xmit in fx2/b)
input          dec_fgu_fmov_vld_m;     // FMOV condition is true
input    [1:0] dec_valid_e;            // used by FGU to qual store FSR update of FSR.ftt
input          dec_frf_store_d;

// ----------------------------------------------------------------------------
// Interface with FEC
// ----------------------------------------------------------------------------

input          fec_cecc_fx2;
input          fec_uecc_fx2;
output         fpc_frf_store_vld_fx1;

// ----------------------------------------------------------------------------
// Interface with FGD
// ----------------------------------------------------------------------------

output   [1:0] fpc_gsr0_mask_sel_fx3;
output   [1:0] fpc_gsr1_mask_sel_fx3;
output   [1:0] fpc_gsr2_mask_sel_fx3;
output   [1:0] fpc_gsr3_mask_sel_fx3;
output   [1:0] fpc_gsr4_mask_sel_fx3;
output   [1:0] fpc_gsr5_mask_sel_fx3;
output   [1:0] fpc_gsr6_mask_sel_fx3;
output   [1:0] fpc_gsr7_mask_sel_fx3;
output   [4:0] fpc_gsr_scale_fx4;
output   [2:0] fpc_gsr_align_fx4;
output  [10:0] fpc_gsr_asr_11bits_fx4;

// ----------------------------------------------------------------------------
// Global Signals
// ----------------------------------------------------------------------------

input          l2clk;                  // clock input
input  	       scan_in;
input          spc_aclk_wmr;
input          wmr_scan_in;
input  	       tcu_pce_ov;	       // scan signals
input  	       spc_aclk;
input  	       spc_bclk;
input	       tcu_scan_en;
input          mbi_run;                // MBIST
input   [27:0] in_rngl_cdbus;          // ASI local ring

output 	       scan_out;
output         wmr_scan_out;


// scan renames
assign pce_ov = tcu_pce_ov;
assign stop   = 1'b0;
assign siclk  = spc_aclk;
assign soclk  = spc_bclk;
assign se     = tcu_scan_en;
// end scan


fgu_fpc_ctl_l1clkhdr_ctl_macro clkgen_coreon (
  .l2clk(l2clk),
  .l1en (coreon_clken),
  .l1clk(l1clk_pm2),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fpc_ctl_l1clkhdr_ctl_macro clkgen_main (
  .l2clk(l2clk),
  .l1en (main_clken),
  .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
  );

fgu_fpc_ctl_spare_ctl_macro__num_9 spares  (  // spares: 13 gates + 1 flop for each "num"
  .scan_in(spares_scanin),
  .scan_out(spares_scanout),
  .l1clk(l1clk_pm2),
  .siclk(siclk),
  .soclk(soclk)
  );


// ----------------------------------------------------------------------------
//                               E stage
// ----------------------------------------------------------------------------

fgu_fpc_ctl_msff_ctl_macro__width_3 e_00  (
  .scan_in(e_00_scanin),
  .scan_out(e_00_scanout),
  .l1clk(l1clk_pm2),
  .din ({dec_frf_r1_odd32b_d,  // requires free running clk or dec_fgu_decode_d en
         dec_frf_r2_odd32b_d,  // requires free running clk or dec_fgu_decode_d en
         dec_frf_store_d}),    // requires free running clk or dec_fgu_decode_d en
  .dout({        r1_odd32b_e,
                 r2_odd32b_e,
             frf_store_e}),
  .siclk(siclk),
  .soclk(soclk)
  );


// ----------------------------------------------------------------------------
//                               FX1 stage
// ----------------------------------------------------------------------------

fgu_fpc_ctl_msff_ctl_macro__width_2 fx1_00  (
  .scan_in(fx1_00_scanin),
  .scan_out(fx1_00_scanout),
  .l1clk(l1clk_pm1),
  .din (dec_valid_e[1:0]    ),
  .dout(i_fst_valid_fx1[1:0]),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_8 fx1_01  (
  .scan_in(fx1_01_scanin),
  .scan_out(fx1_01_scanout),
  .l1clk(l1clk_pm1),
  .din ({r1_odd32b_e,
         r2_odd32b_e,
         fac_tid_e[2:0],
         frf_store_e,
         fac_exu_src_e,
         mbi_run}),
  .dout({r1_odd32b_fx1,
         r2_odd32b_fx1,
         tid_fx1[2:0],
         frf_store_fx1,
             exu_src_fx1,
         mbist_run_1f}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fst_valid_fx1 =
  (i_fst_valid_fx1[0] & (tid_fx1[2:0] <= 3'd3)) |
  (i_fst_valid_fx1[1] & (tid_fx1[2:0] >= 3'd4)) ;

assign  fpc_frf_store_vld_fx1 =  (fst_valid_fx1 | lsu_block_store_m) & frf_store_fx1;

assign  int_rs2_zero_fx1 = fpf_bzf_fx1 & ~fad_rs2_fx1[63];

assign  idiv0_trap_fx1 =
  fac_dec_valid_fx1 &
  int_rs2_zero_fx1  &
  (fac_fpx_itype_fx1[2:1] == 2'b11) &      // div/sqrt
  ((fac_fpx_dtype_fx1[2:0] == 3'b011) |
   (fac_fpx_dtype_fx1[2:0] == 3'b100)  );  // (32/64b dest)

assign  eintx_sel_fx1[3] =  // F(s)MUL(s,d)
  (fac_fpx_itype_fx1[2:0] == 3'b101);

assign  eintx_sel_fx1[2] =  // F(i,x)TOd
  (fac_fpx_itype_fx1[2:0] == 3'b011) &
  (fac_fpx_dtype_fx1[0]   == 1'b1  ) ;

assign  eintx_sel_fx1[1] =  // F(i,x)TOs
  (fac_fpx_itype_fx1[2:0] == 3'b011) &
  (fac_fpx_dtype_fx1[0]   == 1'b0  ) ;

assign  eintx_sel_fx1[0] =  // NaN (or inf)
  (fp_dual_source_fx1 & fpf_aoe_fx1) |
  (fp_source_fx1      & fpf_boe_fx1) ;

assign  eadjx_sel_fx1[2] =  // FdTOs
  (fac_fpx_itype_fx1[2:0] == 3'b001) &
  (fac_fpx_dtype_fx1[0]   == 1'b0  ) &
  (~fpf_boe_fx1                    ) ;  // don't adj exp if NaN (or inf)

assign  eadjx_sel_fx1[1] =  // FsTOd
  (fac_fpx_itype_fx1[2:0] == 3'b001) &
  (fac_fpx_dtype_fx1[0]   == 1'b1  ) &
  (~fpf_boe_fx1                    ) ;  // don't adj exp if NaN (or inf)

assign  eadjx_sel_fx1[0] =  // F(i,x)TO(s,d)
  (fac_fpx_itype_fx1[2:0] == 3'b011) ;

assign  fpc_i2f_sel_fx1[2] =  // F(i,x)TO(s,d) not 2's comp
  ~((~r2_odd32b_fx1 & fad_rs2_fx1[63]) |
    ( r2_odd32b_fx1 & fad_rs2_fx1[31])  ) &
  (fac_fpx_itype_fx1[2:0] == 3'b011);

assign  fpc_i2f_sel_fx1[3] =  // F(i,x)TO(s,d) 2's comp
   ((~r2_odd32b_fx1 & fad_rs2_fx1[63]) |
    ( r2_odd32b_fx1 & fad_rs2_fx1[31])  ) &
  (fac_fpx_itype_fx1[2:0] == 3'b011);

assign  fp_source_fx1 =
  ((fac_fpx_itype_fx1[2:0] == 3'b000) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) | // add/sub
  ((fac_fpx_itype_fx1[2:0] == 3'b100) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) | // cmp
  ((fac_fpx_itype_fx1[2:0] == 3'b110) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) | // div
  ((fac_fpx_itype_fx1[2:0] == 3'b111) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) | // sqrt
  ((fac_fpx_itype_fx1[2:0] == 3'b101) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) | // mul
  ((fac_fpx_itype_fx1[2:0] == 3'b001)                                    ) | // fpfp
  ((fac_fpx_itype_fx1[2:0] == 3'b010)                                    ) ; // fpint

assign  fp_dual_source_fx1 =
  ((fac_fpx_itype_fx1[2:0] == 3'b000) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) | // add/sub
  ((fac_fpx_itype_fx1[2:0] == 3'b100) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) | // cmp
  ((fac_fpx_itype_fx1[2:0] == 3'b110) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) | // div
  ((fac_fpx_itype_fx1[2:0] == 3'b101) & (fac_fpx_dtype_fx1[2:1] == 2'b00)) ; // mul

// ------------------------------------
// Merge GSR.irnd, FSR.rd
//   - force round mode to truncate (2'b01) if rnd_trunc
// ------------------------------------

assign  rd_mode_fx1[1:0] =
  ({2{ fac_fpx_rnd_trunc_fx1              }} & (2'b01              )) |
  ({2{~fac_fpx_rnd_trunc_fx1 &  gsr_im_fx3}} & (gsr_irnd_fx3[1:0]  )) |
  ({2{~fac_fpx_rnd_trunc_fx1 & ~gsr_im_fx3}} & (fad_fsr_rd_fx1[1:0])) ;

assign  ns_mode_fx1 =  // mask FSR.ns if GSR.im=1
  ~gsr_im_fx3 & fad_fsr_ns_fx1;

// ------------------------------------
// logical subtract (effective subtract)
// = ((Sa xor Sb) xor Si) and SP add/sub or DP add/sub
// OR fpint and negative source
// OR intfp and negative source
// OR partitioned subtract
// ------------------------------------

assign  rs1_sign_fx1 =
  (~r1_odd32b_fx1 & fad_rs1_fx1[63]) |
  ( r1_odd32b_fx1 & fad_rs1_fx1[31]) ;

assign  rs2_sign_fx1 =
  (~r2_odd32b_fx1 & fad_rs2_fx1[63]) |
  ( r2_odd32b_fx1 & fad_rs2_fx1[31]) ;

assign  fadd_logical_sub_fx1 =
  ((fac_fpx_itype_fx1[2:0] == 3'b000) &
   (fac_fpx_dtype_fx1[2:1] == 2'b00 ) &  // SP/DP add/sub
   ((rs1_sign_fx1 ^ rs2_sign_fx1) ^ fac_fpx_sign_instr_fx1));

assign  logical_sub_fx1 =
  fadd_logical_sub_fx1 |
  ((fac_fpx_itype_fx1[2:1] == 2'b01 ) &  // fpint/intfp
    rs2_sign_fx1                                 ) |
  ((fac_fpx_itype_fx1[2:0] == 3'b000) &
   (fac_fpx_dtype_fx1[2:1] == 2'b01 ) &  // 16/32b add/sub
                                    fac_fpx_sign_instr_fx1 );

assign  fadd_logical_add_fx1 =
  ((fac_fpx_itype_fx1[2:0] == 3'b000) &
   (fac_fpx_dtype_fx1[2:1] == 2'b00 ) &  // SP/DP add/sub
  ~((rs1_sign_fx1 ^ rs2_sign_fx1) ^ fac_fpx_sign_instr_fx1));

// ------------------------------------
// Exponent overflow prediction FADD/FSUB, FdTOs
// Exponent overflow detection  FdTOs
// Exponent overflow prediction FMUL
// Exponent overflow detection  FMUL
// Note: FDIV is not required to participate in exception trap prediction
// Exponent overflow prediction FDIV
// Exponent overflow detection  FDIV
// ------------------------------------

assign  aux_enable_ovf_fx1 =           // ensure overflow, not underflow
  (fad_rs1_fx1[62] & ~r1_odd32b_fx1) |
  (fad_rs1_fx1[30] &  r1_odd32b_fx1) ;

assign  fmul_enable_ovf_predict_fx1 =  // ensure overflow, not underflow
  ((fad_rs1_fx1[62:52] == 11'b01111111111) &  fac_fpx_dtype_fx1[0]                 ) |
  ((fad_rs1_fx1[62:55] ==  8'b01111111   ) & ~fac_fpx_dtype_fx1[0] & ~r1_odd32b_fx1) |
  ((fad_rs1_fx1[30:23] ==  8'b01111111   ) & ~fac_fpx_dtype_fx1[0] &  r1_odd32b_fx1) ;

assign  aux_eint_ovf_fx1 =  // FDIV/FMUL overflow detection
  aux_enable_ovf_fx1 &
  (( fpe_aux_eint_fx1[8] & ~fac_fpx_dtype_fx1[0]) |     // sp eint cout
   ( fpe_aux_eint_fx1[11] &  fac_fpx_dtype_fx1[0])  ) &  // dp eint cout
  ((~fpe_aux_eint_fx1[7] & ~fac_fpx_dtype_fx1[0]) |     // sp
   (~fpe_aux_eint_fx1[10] &  fac_fpx_dtype_fx1[0])  ) ;  // dp

assign  aux_eint_emax_fx1 =
  ((fpe_aux_eint_fx1[7:0] ==  8'b11111110   ) & ~fac_fpx_dtype_fx1[0]) |  // sp eint Emax
  ((fpe_aux_eint_fx1[10:0] == 11'b11111111110) &  fac_fpx_dtype_fx1[0]) ;  // dp eint Emax

assign  aux_eint_emaxp1_fx1 =
  ((fpe_aux_eint_fx1[7:0] ==  8'b11111111   ) & ~fac_fpx_dtype_fx1[0]) |  // sp eint Emax+1
  ((fpe_aux_eint_fx1[10:0] == 11'b11111111111) &  fac_fpx_dtype_fx1[0]) ;  // dp eint Emax+1

assign  fadd_ovf_predict_fx1 =
  fadd_logical_add_fx1                                &  // req. for correct dpmax-dpmax=0 result
  ~(fpf_aoe_fx1                                     ) &  // Ea != (nan | inf), req. for correct ofc result
  ~(fpf_boe_fx1                                     ) &  // Eb != (nan | inf), req. for correct ofc result
  ~(fpf_aze_fx1                                     ) &  // Ea != (zero| den)
  ~(fpf_bze_fx1                                     ) &  // Eb != (zero| den)
  (((~fac_fpx_dtype_fx1[0] | (&fpe_rs1_fmt_fx1[10:8])) &
    (fpe_rs1_fmt_fx1[7:0] == 8'b11111110)               ) |    // FADD/FSUB Ea=Emax
   ((~fac_fpx_dtype_fx1[0] | (&fpe_rs2_fmt_fx1[10:8])) &
    (fpe_rs2_fmt_fx1[7:0] == 8'b11111110)               )  );  // FADD/FSUB Eb=Emax

// 0in bits_on -max 1 -var {fadd_ovf_predict_fx1, fdtos_ovf_predict_fx1, fdtos_ovf_detect_fx1, fmul_ovf_predict_fx1, fmul_ovf_detect_fx1, fdiv_ovf_predict_fx1, fdiv_ovf_detect_fx1, fdtos_unf_detect_fx1, fmul_unf_predict_fx1, fmul_unf_detect_fx1, fdiv_unf_predict_fx1, fdiv_unf_detect_fx1} -active (fac_dec_valid_fx1 & fp_source_fx1)

assign  fdtos_ovf_predict_fx1 =
   (fpe_rs2_fmt_fx1[10:0]  == 11'b10001111110) &  // 2^(Emax_sp+896=1150)
   (fac_fpx_itype_fx1[2:0] ==  3'b001        ) ;  // fpfp

assign  fdtos_ovf_detect_fx1 =
   (fpe_rs2_fmt_fx1[10:0]  >  11'b10001111110) &  // 2^(Emax_sp+896>1150)
  ~(fpf_boe_fx1                              ) &  // Eb != (nan | inf)
   (fac_fpx_itype_fx1[2:0] ==  3'b001        ) ;  // fpfp

assign  fmul_ovf_predict_fx1 =
   (aux_eint_emax_fx1                               ) &  // FMUL Eint=Emax
   (aux_enable_ovf_fx1 | fmul_enable_ovf_predict_fx1) &  // ensure overflow, not underflow
  ~(fpf_aoe_fx1                                     ) &  // Ea != (nan | inf)
  ~(fpf_boe_fx1                                     ) &  // Eb != (nan | inf)
  ~(fpf_aze_fx1                                     ) &  // Ea != (zero| den)
  ~(fpf_bze_fx1                                     ) &  // Eb != (zero| den)
   (fac_fpx_itype_fx1[2:0]  ==  3'b101              ) ;  // mul

assign  fmul_ovf_detect_fx1 =
   (aux_eint_emaxp1_fx1 |                                // FMUL Eint=Emax+1
    aux_eint_ovf_fx1                                ) &  // FMUL Eint>Emax+1
   (aux_enable_ovf_fx1                              ) &  // ensure overflow, not underflow
  ~(fpf_aoe_fx1                                     ) &  // Ea != (nan | inf)
  ~(fpf_boe_fx1                                     ) &  // Eb != (nan | inf)
  ~(fpf_aze_fx1                                     ) &  // Ea != (zero| den)
  ~(fpf_bze_fx1                                     ) &  // Eb != (zero| den)
   (fac_fpx_itype_fx1[2:0]  ==  3'b101              ) ;  // mul

assign  fdiv_ovf_predict_fx1 =
    (aux_eint_emaxp1_fx1                      ) &     // FDIV Eint=Emax+1
    (aux_enable_ovf_fx1                       ) &     // ensure overflow, not underflow
   ~(fpf_aoe_fx1                              ) &     // Ea != (nan | inf)
   ~(fpf_boe_fx1                              ) &     // Eb != (nan | inf)
   ~(fpf_aze_fx1                              ) &     // Ea != (zero| den)
   ~(fpf_bze_fx1                              ) &     // Eb != (zero| den)
    (fac_fpx_itype_fx1[2:0] ==  3'b110        ) ;     // div

assign  fdiv_ovf_detect_fx1 =
  ( (aux_eint_ovf_fx1                         ) &     // FDIV Eint>Emax+1
   ~(fpf_aoe_fx1                              ) &     // Ea != (nan | inf)
   ~(fpf_boe_fx1                              ) &     // Eb != (nan | inf)
   ~(fpf_aze_fx1                              ) &     // Ea != (zero| den)
   ~(fpf_bze_fx1                              ) &     // Eb != (zero| den)
    (fac_fpx_itype_fx1[2:0] ==  3'b110        )  ) |  // div
// Note: norm divided by denorm will never produce 0.XX frac, thus Eint=Emax+1
//       prediction based on 0.XX frac is not required
  ( (fpf_bze_fx1 & ~fpf_bzf_fx1 & ~ns_mode_fx1) &     // FDIV Eb=den
    (fpe_rs1_fmt_fx1[10:0]  >= 11'b10000000001) &     // Ea = 11'h401
   ~(fpf_aoe_fx1                              ) &     // Ea != (nan | inf)
    (fac_fpx_dtype_fx1[0]   ==  1'b1          ) &     // dp
    (fac_fpx_itype_fx1[2:0] ==  3'b110        )  ) |  // div
  ( (fpf_bze_fx1 & ~fpf_bzf_fx1 & ~ns_mode_fx1) &     // FDIV Eb=den
    (fpe_rs1_fmt_fx1[7:0]  >=  8'b10000001   ) &     // Ea =  8'h81
   ~(fpf_aoe_fx1                              ) &     // Ea != (nan | inf)
    (fac_fpx_dtype_fx1[0]   ==  1'b0          ) &     // sp
    (fac_fpx_itype_fx1[2:0] ==  3'b110        )  ) ;  // div

// ------------------------------------
// Exponent       underflow prediction FdTOs
// Exponent       underflow detection  FdTOs
// Exponent gross underflow detection  FdTOs
// Exponent       underflow prediction FMUL
// Exponent       underflow detection  FMUL
// Note: FDIV is not required to participate in exception trap prediction
// Exponent       underflow prediction FDIV
// Exponent       underflow detection  FDIV
// ------------------------------------

assign  aux_enable_unf_fx1 =           // ensure underflow, not overflow
  (~fad_rs1_fx1[62] & ~r1_odd32b_fx1) |
  (~fad_rs1_fx1[30] &  r1_odd32b_fx1) ;

assign  fdiv_enable_unf_predict_fx1 =  // ensure underflow, not overflow
  ((fad_rs1_fx1[62:52] == 11'b10000000000) &  fac_fpx_dtype_fx1[0]                 ) |
  ((fad_rs1_fx1[62:55] ==  8'b10000000   ) & ~fac_fpx_dtype_fx1[0] & ~r1_odd32b_fx1) |
  ((fad_rs1_fx1[30:23] ==  8'b10000000   ) & ~fac_fpx_dtype_fx1[0] &  r1_odd32b_fx1) ;

assign  aux_eint_unf_fx1 =  // FDIV/FMUL underflow detection
  aux_enable_unf_fx1 &
  ((~fpe_aux_eint_fx1[8] & ~fac_fpx_dtype_fx1[0]) |     // sp eint ~cout
   (~fpe_aux_eint_fx1[11] &  fac_fpx_dtype_fx1[0])  ) &  // dp eint ~cout
  (( fpe_aux_eint_fx1[7] & ~fac_fpx_dtype_fx1[0]) |     // sp
   ( fpe_aux_eint_fx1[10] &  fac_fpx_dtype_fx1[0])  ) ;  // dp

assign  aux_eint_emin_fx1 =
  ((fpe_aux_eint_fx1[7:0] ==  8'b00000001   ) & ~fac_fpx_dtype_fx1[0]) |     // sp eint Emin
  ((fpe_aux_eint_fx1[10:0] == 11'b00000000001) &  fac_fpx_dtype_fx1[0]) ;     // dp eint Emin

assign  aux_eint_eminm1_fx1 =
  ((fpe_aux_eint_fx1[7:0] ==  8'b00000000   ) & ~fac_fpx_dtype_fx1[0]) |     // sp eint Emin-1
  ((fpe_aux_eint_fx1[10:0] == 11'b00000000000) &  fac_fpx_dtype_fx1[0]) ;     // dp eint Emin-1

assign  aux_eint_eminm2_fx1 =
  aux_eint_unf_fx1 &
  (((fpe_aux_eint_fx1[7:0] ==  8'b11111111   ) & ~fac_fpx_dtype_fx1[0]) |    // sp eint Emin-2
   ((fpe_aux_eint_fx1[10:0] == 11'b11111111111) &  fac_fpx_dtype_fx1[0])  );  // dp eint Emin-2

// Gross underflow detection:
// - Unnorm Eint is used for guf detection
// - For guf calculation, denorm Ea/Eb is treated as zero, not Emin
// - For fmul guf calculation, 1X.XX intermediate format has no effect
// - fdiv:  Eint=Ea-Eb+bias-1
// - fmul:  Eint=Ea+Eb-bias
// - fdtos: Eint=Eb-896
// - gross unf (sp exp <= -25, dp exp <= -54)

assign  fdtos_guf_detect_fx1 =
  (fpe_rs2_fmt_fx1[10:0]  <  11'b01101101000               ) &  // 2^(872), 871-896=-25
 ~((fpe_rs2_fmt_fx1[10:0] == 11'b00000000000) & fpf_bzf_fx1) &  // ~zero src
 ~((rd_mode_fx1[1:0]      ==  2'b10) & ~fad_rs2_fx1[63]    ) &  // ~(pos. & rnd=+inf)
 ~((rd_mode_fx1[1:0]      ==  2'b11) &  fad_rs2_fx1[63]    ) &  // ~(neg. & rnd=-inf)
 ~(ns_mode_fx1                                             ) &
  (fac_fpx_itype_fx1[2:0] ==  3'b001                       ) &  // fpfp
  (fac_fpx_dtype_fx1[0]   ==  1'b0                         ) ;  // sp

assign  fmul_guf_detect_fx1 =
  aux_eint_unf_fx1 &                                          // Eint<Emin-1
  (fac_fpx_itype_fx1[2:0]   ==  3'b101) &                     // mul
  (fac_fpx_dtype_fx1[2:1]   ==  2'b00 ) &                     // sp/dp
 ~(fpf_aoe_fx1                        ) &                     // Ea != (nan | inf)
 ~(fpf_boe_fx1                        ) &                     // Eb != (nan | inf)
 ~(fpf_aze_fx1 & fpf_azf_fx1          ) &                     //  a !=  zero
 ~(fpf_bze_fx1 & fpf_bzf_fx1          ) &                     //  b !=  zero
 ~((rd_mode_fx1[1:0] == 2'b10) & ~(rs1_sign_fx1 ^ rs2_sign_fx1)) &  // ~(pos. & rnd=+inf)
 ~((rd_mode_fx1[1:0] == 2'b11) &  (rs1_sign_fx1 ^ rs2_sign_fx1)) &  // ~(neg. & rnd=-inf)
 ~(ns_mode_fx1                                             ) &
  (((fpe_aux_eint_fx1[7:0] <=  8'b11100111   ) & ~fac_fpx_dtype_fx1[0]) |    // sp Eint<=-25 (Eint=Ea+Eb-bias)
   ((fpe_aux_eint_fx1[10:0] <= 11'b11111001010) &  fac_fpx_dtype_fx1[0])  );  // dp Eint<=-54 (Eint=Ea+Eb-bias)

assign  fdiv_guf_detect_fx1 =
  aux_eint_unf_fx1 &                                          // Eint<Emin-1
  (fac_fpx_itype_fx1[2:0]   ==  3'b110) &                     // div
  (fac_fpx_dtype_fx1[2:1]   ==  2'b00 ) &                     // sp/dp
 ~(fpf_aoe_fx1                        ) &                     // Ea != (nan | inf)
 ~(fpf_boe_fx1                        ) &                     // Eb != (nan | inf)
 ~(fpf_aze_fx1 & fpf_azf_fx1          ) &                     //  a !=  zero
 ~(fpf_bze_fx1 & fpf_bzf_fx1          ) &                     //  b !=  zero
 ~((rd_mode_fx1[1:0] == 2'b10) & ~(rs1_sign_fx1 ^ rs2_sign_fx1)) &  // ~(pos. & rnd=+inf)
 ~((rd_mode_fx1[1:0] == 2'b11) &  (rs1_sign_fx1 ^ rs2_sign_fx1)) &  // ~(neg. & rnd=-inf)
 ~(ns_mode_fx1                                             ) &
  (((fpe_aux_eint_fx1[7:0] <=  8'b11101000   ) & ~fac_fpx_dtype_fx1[0]) |    // sp Eint<=-24 (Eint=Ea-Eb+bias-1)
   ((fpe_aux_eint_fx1[10:0] <= 11'b11111001011) &  fac_fpx_dtype_fx1[0])  );  // dp Eint<=-53 (Eint=Ea-Eb+bias-1)

assign  fdtos_unf_predict_fx1 =
  (fpe_rs2_fmt_fx1[10:0]  == 11'b01110000000) &  // 2^(896)
  (fac_fpx_itype_fx1[2:0] ==  3'b001        ) ;  // fpfp

assign  fdtos_unf_detect_fx1 =
  (fpe_rs2_fmt_fx1[10:0]  <  11'b01110000000) &  // 2^(896)
 ~(fpe_rs2_fmt_fx1[10:0]  == 11'b00000000000) &  // ~(zero|denorm)
  (fac_fpx_itype_fx1[2:0] ==  3'b001        ) &  // fpfp
  (fac_fpx_dtype_fx1[0]   ==  1'b0          ) ;  // sp

assign  fmul_unf_predict_fx1 =
   (aux_eint_eminm1_fx1               ) &  // FMUL Eint=Emin-1
   (aux_enable_unf_fx1                ) &  // ensure underflow, not overflow
  ~(fpf_aoe_fx1                       ) &  // Ea != (nan | inf)
  ~(fpf_boe_fx1                       ) &  // Eb != (nan | inf)
  ~(fpf_aze_fx1                       ) &  // Ea != (zero| den)
  ~(fpf_bze_fx1                       ) &  // Eb != (zero| den)
   (fac_fpx_itype_fx1[2:0]  ==  3'b101) &  // mul
   (fac_fpx_dtype_fx1[2:1]  ==  2'b00 ) ;  // sp/dp

assign  fmul_unf_detect_fx1 =	        
   (aux_eint_unf_fx1                  ) &  // FMUL Eint<Emin-1
  ~(fpf_aoe_fx1                       ) &  // Ea != (nan | inf)
  ~(fpf_boe_fx1                       ) &  // Eb != (nan | inf)
  ~(fpf_aze_fx1                       ) &  // Ea != (zero| den)
  ~(fpf_bze_fx1                       ) &  // Eb != (zero| den)
   (fac_fpx_itype_fx1[2:0]  ==  3'b101) &  // mul
   (fac_fpx_dtype_fx1[2:1]  ==  2'b00 ) ;  // sp/dp

assign  fdiv_unf_predict_fx1 =			  
   (aux_eint_emin_fx1                               ) &  // FDIV Eint=Emin
   (aux_enable_unf_fx1 | fdiv_enable_unf_predict_fx1) &  // ensure underflow, not overflow
  ~(fpf_aoe_fx1                                     ) &  // Ea != (nan | inf)
  ~(fpf_boe_fx1                                     ) &  // Eb != (nan | inf)
  ~(fpf_aze_fx1                                     ) &  // Ea != (zero| den)
  ~(fpf_bze_fx1                                     ) &  // Eb != (zero| den)
   (fac_fpx_itype_fx1[2:0]  ==  3'b110              ) ;  // div
						  
assign  fdiv_unf_detect_fx1 =
   (aux_eint_eminm1_fx1 |                                // FDIV Eint=Emin-1
    aux_eint_unf_fx1                                ) &  // FDIV Eint<Emin-1
   (aux_enable_unf_fx1                              ) &  // ensure underflow, not overflow
  ~(fpf_aoe_fx1                                     ) &  // Ea != (nan | inf)
  ~(fpf_boe_fx1                                     ) &  // Eb != (nan | inf)
  ~(fpf_aze_fx1                                     ) &  // Ea != (zero| den)
  ~(fpf_bze_fx1                                     ) &  // Eb != (zero| den)
   (fac_fpx_itype_fx1[2:0]  ==  3'b110              ) ;  // div

// ------------------------------------
// Exception trap prediction
// - IDIV, FDIV, FSQRT do not participate in exception trap prediction.
//   Once an FPD instr has been issued, no other instr from that thread
//   can be issued until the older FPD instr has completed or has been flushed.
// ------------------------------------

assign  snan_or_inf_fx1 =
  (fpf_aoe_fx1 & fp_dual_source_fx1 & ~fad_rs1_fmt_fx1_b62) |
  (fpf_boe_fx1 &                      ~fad_rs2_fmt_fx1_b62) ;

assign  nan_or_inf_fx1 =
  (fac_fcmpe_fx1 &
   (fac_fpx_itype_fx1[2:0] == 3'b100) & (fac_fpx_dtype_fx1[2:1] == 2'b00) &     // FCMPE(s,d)
                                        (fpf_aoe_fx1 | fpf_boe_fx1)        ) |
  ((fac_fpx_itype_fx1[2:0] == 3'b010) &                fpf_boe_fx1         ) ;  // F(s,d)TO(i,x)

assign  large_maxint_predict_fx1 =

  ((fpe_rs2_fmt_fx1[10:0] >= 11'b10000111110) &     // 2^(63+1023)
   (fac_fpx_itype_fx1[2:0] == 3'b010) &
   (fac_fpx_stype_fx1[1:0] == 2'b01 ) &
   (fac_fpx_dtype_fx1[2:0] == 3'b100)          ) |  // FdTOx

  ((fpe_rs2_fmt_fx1[7:0]  >=     8'b10111110) &     // 2^(63+ 127)
   (fac_fpx_itype_fx1[2:0] == 3'b010) &
   (fac_fpx_stype_fx1[1:0] == 2'b00 ) &
   (fac_fpx_dtype_fx1[2:0] == 3'b100)          ) |  // FsTOx

  ((fpe_rs2_fmt_fx1[10:0] >= 11'b10000011110) &     // 2^(31+1023)
   (fac_fpx_itype_fx1[2:0] == 3'b010) &
   (fac_fpx_stype_fx1[1:0] == 2'b01 ) &
   (fac_fpx_dtype_fx1[2:0] == 3'b011)          ) |  // FdTOi

  ((fpe_rs2_fmt_fx1[7:0]  >=     8'b10011110) &     // 2^(31+ 127)
   (fac_fpx_itype_fx1[2:0] == 3'b010) &
   (fac_fpx_stype_fx1[1:0] == 2'b00 ) &
   (fac_fpx_dtype_fx1[2:0] == 3'b011)          ) ;  // FsTOi

assign  fadd_unf_predict_fx1 =

  fadd_logical_sub_fx1 &
  ~fpf_aze_fx1         &                        // Ea != (zero| den)
  ~fpf_bze_fx1         &                        // Eb != (zero| den)

  (( fpe_rs1_fmt_fx1[10:1]          ==
     fpe_rs2_fmt_fx1[10:1]              ) |     // shift count (SC) = 0 (or possibly 1)
   ((fpe_rs1_fmt_fx1[10:0] + 11'd1) ==
     fpe_rs2_fmt_fx1[10:0]              ) |     // Ea+1=Eb     (SC) = 1
   ((fpe_rs2_fmt_fx1[10:0] + 11'd1) ==
     fpe_rs1_fmt_fx1[10:0]              )  ) &  // Eb+1=Ea     (SC) = 1

  ((~fac_fpx_dtype_fx1[0]              &        // SP
    ~(fpe_rs1_fmt_fx1[7:0]  >=  8'd25) &        // Ea !>=25
    ~(fpe_rs2_fmt_fx1[7:0]  >=  8'd25)  ) |     // Eb !>=25

   ( fac_fpx_dtype_fx1[0]              &        // DP
    ~(fpe_rs1_fmt_fx1[10:0] >= 11'd54) &        // Ea !>=54
    ~(fpe_rs2_fmt_fx1[10:0] >= 11'd54)  )  ) ;  // Eb !>=54

assign  fadd_fcvt_denorm_detect_fx1 =
  ~ns_mode_fx1 &

  ((((fpf_aze_fx1 & ~fpf_azf_fx1) | (fpf_bze_fx1 & ~fpf_bzf_fx1)) &     // denorm a or b
    (fac_fpx_itype_fx1[2:0] == 3'b000) &
    (fac_fpx_dtype_fx1[2:1] == 2'b00 ) &                                // FADD/FSUB
    fac_fpx_unfin_vld_fx1                                          ) |  // must not include FMOV/FABS/FNEG
   
   (                                (fpf_bze_fx1 & ~fpf_bzf_fx1)  &     // denorm      b
    (fac_fpx_itype_fx1[2:0] == 3'b010)                             ) |  // F(s,d)TO(i,x)

   (                                (fpf_bze_fx1 & ~fpf_bzf_fx1)  &     // denorm      b
    ~(~fad_fsr_tem_fx1[2] & fdtos_guf_detect_fx1) &                     // ~(gross_unf and UFM=0)
    (fac_fpx_itype_fx1[2:0] == 3'b001)                             ));  // F(s,d)TO(d,s)

assign  fmul_denorm_detect_fx1 =
  ~ns_mode_fx1 &
   ( ((fpf_aze_fx1 & ~fpf_azf_fx1) | (fpf_bze_fx1 & ~fpf_bzf_fx1)) &    //   denorm a or b
    ~(~fad_fsr_tem_fx1[2] & fmul_guf_detect_fx1 ) &                     // ~(gross_unf & UFM=0)
    ~((fpf_aze_fx1 &  fpf_azf_fx1) | (fpf_bze_fx1 &  fpf_bzf_fx1)) &    // ~(zero   a or b)
    (fac_fpx_itype_fx1[2:0] == 3'b101) &                                // note: FsMULd never underflows
    (fac_fpx_dtype_fx1[2:1] == 2'b00 )                             );   // FsMULd, FMUL(s,d)

assign  q_fmul_unf_predict_fx1 =
   (                          ( fad_fsr_tem_fx1[2] | ~ns_mode_fx1)
                           &  (fmul_unf_predict_fx1 | fmul_unf_detect_fx1)
                           & ~(~fad_fsr_tem_fx1[2] & fmul_guf_detect_fx1 )    ) ;

assign  i_predict_fx1 =

  ( fac_fpx_nv_vld_fx1 & ~(fac_fpx_itype_fx1[2:1] == 2'b11)        // not div/sqrt
                          &    fad_fsr_tem_fx1[4] & snan_or_inf_fx1          ) |
  (                            fad_fsr_tem_fx1[4] &  nan_or_inf_fx1          ) |
  (                            fad_fsr_tem_fx1[4] & large_maxint_predict_fx1 ) |

  ( fac_fpx_of_vld_fx1    &    fad_fsr_tem_fx1[3] & fadd_ovf_predict_fx1     ) |
  ( fac_fpx_of_vld_fx1    &    fad_fsr_tem_fx1[3] & fmul_ovf_predict_fx1     ) |
  ( fac_fpx_of_vld_fx1    &    fad_fsr_tem_fx1[3] & fmul_ovf_detect_fx1      ) |
  ( fac_fpx_of_vld_fx1    &    fad_fsr_tem_fx1[3] & fdtos_ovf_predict_fx1    ) |
  ( fac_fpx_of_vld_fx1    &    fad_fsr_tem_fx1[3] & fdtos_ovf_detect_fx1     ) |
   
  ( fac_fpx_uf_vld_fx1    &  ( fad_fsr_tem_fx1[2] | ~ns_mode_fx1)
                                                  & fadd_unf_predict_fx1     ) |
  (                          ( fad_fsr_tem_fx1[2] | ~ns_mode_fx1)
                                                  & fdtos_unf_predict_fx1    ) |
  ((                         ( fad_fsr_tem_fx1[2] | ~ns_mode_fx1)
                                                  & fdtos_unf_detect_fx1    )
                          & ~(~fad_fsr_tem_fx1[2] & fdtos_guf_detect_fx1)    ) |

//( fac_fpx_dz_vld_fx1    &    fad_fsr_tem_fx1[1]                            ) |

  ( fac_fpx_nx_vld_fx1 & ~( fac_fpx_itype_fx1[2:1] == 2'b11  )     // not div/sqrt
                       & ~((fac_fpx_itype_fx1[2:0] == 3'b001)  &
                           (fac_fpx_dtype_fx1[0]   == 1'b1  ))     // not FsTOd
                       & ~((fac_fpx_itype_fx1[2:0] == 3'b101)  &
                           (fac_fpx_stype_fx1[1:0] == 2'b00 )  &
                           (fac_fpx_dtype_fx1[2:0] == 3'b001))     // not FsMULd
                          &    fad_fsr_tem_fx1[0]                            ) |
  ( fac_fpx_nx_vld_fx1 & (( fpf_bze_fx1                        &
                           (fac_fpx_itype_fx1[2:0] == 3'b001)  &
                           (fac_fpx_dtype_fx1[0]   == 1'b1  )) |   //     FsTOd
                          ((fpf_aze_fx1 | fpf_bze_fx1       )  &
                           (fac_fpx_itype_fx1[2:0] == 3'b101)  &
                           (fac_fpx_stype_fx1[1:0] == 2'b00 )  &
                           (fac_fpx_dtype_fx1[2:0] == 3'b001))  )  //     FsMULd
                          &    fad_fsr_tem_fx1[0] &  ns_mode_fx1             );


// ----------------------------------------------------------------------------
//                               FX2 stage
// ----------------------------------------------------------------------------

fgu_fpc_ctl_msff_ctl_macro__width_51 fx2_00  (
  .scan_in(fx2_00_scanin),
  .scan_out(fx2_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({fac_fpx_itype_fx1[2:0],
         fac_fpx_dtype_fx1[2:0],
         fac_fpx_stype_fx1[1:0],
         fac_fpx_sign_instr_fx1,
         idiv0_trap_fx1,
         dec_flush_f1,
         fac_dec_valid_fx1,
         dec_fgu_fmov_vld_m,
         fac_div_valid_fx1,
         fac_divq_valid_fx1,
         fpe_aux_rs2_fmt_fx1_b0,
             eintx_sel_fx1[3:0],
             eadjx_sel_fx1[2:0],
         fac_fpx_nv_vld_fx1,
         fac_fpx_of_vld_fx1,
         fac_fpx_uf_vld_fx1,
         fac_fpx_dz_vld_fx1,
         fac_fpx_nx_vld_fx1,
         fac_fpx_unfin_vld_fx1,
         fac_fcmpe_fx1,
         fp_source_fx1,
         fp_dual_source_fx1,
         rs1_sign_fx1,
         rs2_sign_fx1,
         fadd_logical_sub_fx1,
         logical_sub_fx1,
         fadd_logical_add_fx1,
         fpf_hi_aof_fx1,
         fpf_lo_aof_fx1,
         aux_eint_eminm1_fx1,
         aux_eint_eminm2_fx1,
         aux_enable_unf_fx1,
         rd_mode_fx1[1:0],
         ns_mode_fx1,
         fst_valid_fx1,
         fad_gsr_imirnd_fx1[2:0],
         fac_fgx_pdist_fx1,
         exu_src_fx1}),
  .dout({        itype_fx2[2:0],
                 dtype_fx2[2:0],
                 stype_fx2[1:0],
                 sign_instr_fx2,
         i_idiv0_trap_fx2,
         dec_flush_fx2,
         dec_valid_fx2,
         fmov_vld_fx2,
             div_valid_fx2,
             divq_valid_fx2,
             aux_rs2_fmt_fx2[0],
         fpc_eintx_sel_fx2[3:0],
         fpc_eadjx_sel_fx2[2:0],
             fpx_nv_vld_fx2,
             fpx_of_vld_fx2,
             fpx_uf_vld_fx2,
             fpx_dz_vld_fx2,
             fpx_nx_vld_fx2,
             fpx_unfin_vld_fx2,
             fcmpe_fx2,
         fp_source_fx2,
         fp_dual_source_fx2,
         rs1_sign_fx2,
         rs2_sign_fx2,
         fadd_logical_sub_fx2,
         logical_sub_fx2,
         fadd_logical_add_fx2,
             hi_aof_fx2,
             lo_aof_fx2,
         aux_eint_eminm1_fx2,
         aux_eint_eminm2_fx2,
         aux_enable_unf_fx2,
         rd_mode_fx2[1:0],
         ns_mode_fx2,
         fst_valid_fx2,
         gsr_imirnd_fx2[2:0],
             fgx_pdist_fx2,
         exu_src_fx2}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_14 fx2_01  (
  .scan_in(fx2_01_scanin),
  .scan_out(fx2_01_scanout),
  .l1clk(l1clk_pm1),
  .din ({fac_fpx_mulscc_fx1,
         fad_rs1_fx1[33],
         fpe_rs2_fmt_fx1[10:0],
         fac_fpx_saverestore_fx1}),
  .dout({        mulscc_fx2,
          mulscc_y_src_fx2_b0,
             rs2_exp_fx2[10:0],
                 saverestore_fx2}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_17 fx2_02  (
  .scan_in(fx2_02_scanin),
  .scan_out(fx2_02_scanout),
  .l1clk(l1clk_pm1),
  .din ({fac_w1_vld_fx1[1:0], fac_w1_odd32b_fx1, fpe_aux_eint_fx1[10:0], tid_fx1[2:0]}),
  .dout({  i_w1_vld_fx2[1:0],     w1_odd32b_fx2,     aux_eint_fx2[10:0], tid_fx2[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_4 fx2_03  (
  .scan_in(fx2_03_scanin),
  .scan_out(fx2_03_scanout),
  .l1clk(l1clk_pm1),
  .din ({fad_rs1_fx1[63], fad_rs1_fx1[47], fad_rs1_fx1[31], fad_rs1_fx1[15]}),
  .dout({    rs1_fx2_b63,     rs1_fx2_b47,     rs1_fx2_b31,     rs1_fx2_b15}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_4 fx2_04  (
  .scan_in(fx2_04_scanin),
  .scan_out(fx2_04_scanout),
  .l1clk(l1clk_pm1),
  .din ({fad_rs2_fx1[63], fad_rs2_fx1[47], fad_rs2_fx1[31], fad_rs2_fx1[15]}),
  .dout({    rs2_fx2_b63,     rs2_fx2_b47,     rs2_fx2_b31,     rs2_fx2_b15}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_6 fx2_05  (
  .scan_in(fx2_05_scanin),
  .scan_out(fx2_05_scanout),
  .l1clk(l1clk_pm1),
  .din ({fpf_azf_fx1, fpf_bzf_fx1, fpf_aoe_fx1, fpf_boe_fx1, fpf_aze_fx1, fpf_bze_fx1}),
  .dout({    azf_fx2,     bzf_fx2,     aoe_fx2,     boe_fx2,     aze_fx2,     bze_fx2}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_7 fx2_06  (
  .scan_in(fx2_06_scanin),
  .scan_out(fx2_06_scanout),
  .l1clk(l1clk_pm1),
  .din ({fad_fsr_tem_fx1[4:0],
         fad_rs1_fmt_fx1_b62,
         fad_rs2_fmt_fx1_b62}),
  .dout({    fsr_tem_fx2[4:0],
             rs1_fmt_fx2[62],
             rs2_fmt_fx2[62]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_20 fx2_07  (
  .scan_in(fx2_07_scanin),
  .scan_out(fx2_07_scanout),
  .l1clk(l1clk_pm1),
  .din ({fadd_ovf_predict_fx1,
         fdtos_ovf_predict_fx1,
         fdtos_ovf_detect_fx1,
         fmul_ovf_predict_fx1,
         fmul_ovf_detect_fx1,
         fdiv_ovf_predict_fx1,
         fdiv_ovf_detect_fx1,
         fdtos_unf_predict_fx1,
         fdtos_unf_detect_fx1,
         fmul_unf_predict_fx1,
         fmul_unf_detect_fx1,
         fdiv_unf_predict_fx1,
         fdiv_unf_detect_fx1,
         fdtos_guf_detect_fx1,
         fmul_guf_detect_fx1,
         fdiv_guf_detect_fx1,
         i_predict_fx1,
         fmul_denorm_detect_fx1,
         q_fmul_unf_predict_fx1,
         fadd_fcvt_denorm_detect_fx1}),
  .dout({fadd_ovf_predict_fx2,
         fdtos_ovf_predict_fx2,
         fdtos_ovf_detect_fx2,
         fmul_ovf_predict_fx2,
         fmul_ovf_detect_fx2,
         fdiv_ovf_predict_fx2,
         fdiv_ovf_detect_fx2,
         fdtos_unf_predict_fx2,
         fdtos_unf_detect_fx2,
         fmul_unf_predict_fx2,
         fmul_unf_detect_fx2,
         fdiv_unf_predict_fx2,
         fdiv_unf_detect_fx2,
         fdtos_guf_detect_fx2,
         fmul_guf_detect_fx2,
         fdiv_guf_detect_fx2,
         i_predict_fx2,
         fmul_denorm_detect_fx2,
         q_fmul_unf_predict_fx2,
         fadd_fcvt_denorm_detect_fx2}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_15 fx2_08  (
  .scan_in(fx2_08_scanin),
  .scan_out(fx2_08_scanout),
  .l1clk(l1clk_pm2),
  .din ({in_rngl_cdbus[27:25],  // requires free running clk or rng_data_1f[63] en
         in_rngl_cdbus[7:0],    // requires free running clk or rng_data_1f[63] en
         exu_fgu_flush_m,       // requires free running clk
         exu_fgu_gsr_m[2:0]}),  // requires free running clk
  .dout({in_rngl_cdbus_1f[27:25],
         in_rngl_cdbus_1f[7:0],
         exu_flush_fx2,
         gsr_align_fx2[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  w1_vld_fx2[1:0] =
  i_w1_vld_fx2[1:0] &
  {2{~(fac_fgx_mvcond_fx2 & ~fmov_vld_fx2)}} &
  {2{~dec_flush_fx2}} &
  {2{~exu_flush_fx2}} &        // required for conditional FMOV
  {2{~(fec_uecc_fx2 | fec_cecc_fx2)}};

assign  fsr_w1_vld_fx2[0] =    // fsr write valid, not cleared for mvcond with cond=false
  dec_valid_fx2             &
 ~(itype_fx2 == 3'b100)     &  // ~FCMP(E)
  (fpx_nv_vld_fx2        |
   fpx_of_vld_fx2        |
   fpx_uf_vld_fx2        |
   fpx_dz_vld_fx2        |
   fpx_nx_vld_fx2        |
   fpx_unfin_vld_fx2     |
   fac_fgx_mvcond_fx2    |
   fac_fgx_mvucond_fx2   |
   (itype_fx2 == 3'b011) |     // ensure FiTOd is included
   fac_fgx_abs_fx2       |
   fac_fgx_neg_fx2        ) &
  ~dec_flush_fx2            &
  ~exu_flush_fx2            &  // required for conditional FMOV
  ~(fec_uecc_fx2 | fec_cecc_fx2);

assign  fsr_w1_vld_fx2[1] =
  fst_valid_fx2     &         // store FSR 32/64b clears ftt in fw stage via w1      
  fac_fsr_store_fx2 &
  ~dec_flush_fx2    &
  ~exu_flush_fx2    &          // required for conditional FMOV
  ~(fec_uecc_fx2 | fec_cecc_fx2);

// 0in custom -fire (((fac_fsr_store_fx2 & fst_valid_fx2) & ($0in_delay(dec_valid_fx2,1)) & (tid_fx2[2:0]==tid_fx3[2:0])) | ((fac_fsr_store_fx2 & fst_valid_fx2) & ($0in_delay(dec_valid_fx2,2)) & (tid_fx2[2:0]==($0in_delay(tid_fx3[2:0],1)))) | ((fac_fsr_store_fx2 & fst_valid_fx2) & ($0in_delay(dec_valid_fx2,3)) & (tid_fx2[2:0]==($0in_delay(tid_fx3[2:0],2)))) | ((fac_fsr_store_fx2 & fst_valid_fx2) & ($0in_delay(dec_valid_fx2,4)) & (tid_fx2[2:0]==($0in_delay(tid_fx3[2:0],3))))) -message "STFSR collision with FPop"

assign gsr_w_vld_fx2[1:0] =  // gsr write valids
  fac_gsr_w_vld_fx2[1:0] &
  {2{~dec_flush_fx2}}    &
//{2{~dec_flush_f2}}     &
//{2{~tlu_flush_fgu_b}}  &
  {2{~exu_flush_fx2}}    ;

assign fgx_siam_fx2 =        // gsr write valids
  fac_fgx_siam_fx2       &
     ~dec_flush_fx2      &
//   ~dec_flush_f2       &
//   ~tlu_flush_fgu_b    &
     ~exu_flush_fx2      ;

// ------------------------------------
// floating point intermediate sign
// Note:
// (1) intermediate sign for sqrt is always 1'b0, unless rs2 is
//     -0 or -denorm
// (2) rs1 - rs2 = +norm - +nan = -nan is incorrect, must pass rs2[63,31]
//     if rs1 or rs2 is a nan
// (3) pass rs2[63,31] if fpfp instr (needed for rs2=0 case)
// ------------------------------------

assign  sign_nan_fx2 =
  (nan_rs2prop_fx2 & rs2_sign_fx2) |
  (nan_rs1prop_fx2 & rs1_sign_fx2) ;

assign  sign_inter_sel_fx2[0] =
  ~(itype_fx2[2:0] == 3'b101) &  // mul
  ~(itype_fx2[2:0] == 3'b110) &  // div
  ~(itype_fx2[2:0] == 3'b111) &  // sqrt
  ~(a_nan_fx2 | b_nan_fx2)    &
   (~fpf_cmp_swap_blta_fx2 |  (itype_fx2[2:0] == 3'b001)    // fpfp
                           |  (itype_fx2[2:0] == 3'b010)    // fpint
                           |  (itype_fx2[2:0] == 3'b011));  // intfp

assign  sign_inter_sel_fx2[1] =
  ~(itype_fx2[2:0] == 3'b101) &  // mul
  ~(itype_fx2[2:0] == 3'b110) &  // div
  ~(itype_fx2[2:0] == 3'b111) &  // sqrt
  ~(a_nan_fx2 | b_nan_fx2)    &
   ( fpf_cmp_swap_blta_fx2 & ~(itype_fx2[2:0] == 3'b001)    // fpfp
                           & ~(itype_fx2[2:0] == 3'b010)    // fpint
                           & ~(itype_fx2[2:0] == 3'b011));  // intfp

assign  sign_inter_sel_fx2[2] =
   ((itype_fx2[2:0] == 3'b101) |     // mul
    (itype_fx2[2:0] == 3'b110)  ) &  // div
  ~(a_nan_fx2 | b_nan_fx2);

assign  sign_inter_sel_fx2[3] =
   (itype_fx2[2:0] == 3'b111) &      // sqrt
  ~(a_nan_fx2 | b_nan_fx2);

assign  sign_inter_sel_fx2[4] =
   (a_nan_fx2 | b_nan_fx2);

assign  sign_inter_fx2 =
  (sign_inter_sel_fx2[0] & (rs2_sign_fx2 ^ sign_instr_fx2)) |
  (sign_inter_sel_fx2[1] & (rs1_sign_fx2                 )) |
  (sign_inter_sel_fx2[2] & (rs1_sign_fx2 ^ rs2_sign_fx2  )) |
  (sign_inter_sel_fx2[3] & (rs2_sign_fx2 & bze_fx2       )) |
  (sign_inter_sel_fx2[4] & (sign_nan_fx2                 )) ;  // 0in bits_on -max 1 -var sign_inter_sel_fx2[4:0] -active dec_valid_fx2

// ------------------------------------
// Final FSQRT intermediate exponent (Eint) calculation, and mux with FDIV Eint
// ------------------------------------

assign  sp_odd_exp_fx2  = itype_fx2[0] & ~dtype_fx2[0] & ~aux_rs2_fmt_fx2[0];  // fsqrts odd  exp
assign  sp_even_exp_fx2 = itype_fx2[0] & ~dtype_fx2[0] &  aux_rs2_fmt_fx2[0];  // fsqrts even exp
assign  dp_odd_exp_fx2  = itype_fx2[0] &  dtype_fx2[0] & ~aux_rs2_fmt_fx2[0];  // fsqrtd odd  exp
assign  dp_even_exp_fx2 = itype_fx2[0] &  dtype_fx2[0] &  aux_rs2_fmt_fx2[0];  // fsqrtd even exp

assign  fpd_eint_fx2[10:0] =
  ({11{dp_even_exp_fx2}} & ({        aux_eint_fx2[10], aux_eint_fx2[10:1]} + 11'b01111111111)) |  // fsqrt +bias
  ({11{dp_odd_exp_fx2 }} & ({        aux_eint_fx2[10], aux_eint_fx2[10:1]} + 11'b10000000000)) |  // fsqrt +bias+1
  ({11{sp_even_exp_fx2}} & ({3'b000, aux_eint_fx2[7], aux_eint_fx2[7:1]} + 11'b00001111111)) |  // fsqrt +bias
  ({11{sp_odd_exp_fx2 }} & ({3'b000, aux_eint_fx2[7], aux_eint_fx2[7:1]} + 11'b00010000000)) |  // fsqrt +bias+1
  ({11{~itype_fx2[0]  }} & (                           aux_eint_fx2[10:0]                   )) ;  // fdiv

// ------------------------------------
// VIS partitioned compares:
// FCMPEQ(16,32), FCMPGT(16,32), FCMPLE(16,32), FCMPNE(16,32)
//
// gt if rs1 >  rs2
// le if rs1 <= rs2
// ne if rs1 != rs2
// eq if rs1  = rs2
//
// Where rs1 and rs2 are signed values.
//
// Note: fpf_b_gteq_a_fx2[3] and fpf_b_eq_a_fx2[3] don't yet
//       account for rs1[63] and rs2[63]
// ------------------------------------

// ------------------------------------
// gt16, gt32
// ------------------------------------

assign  fcmpgt16_fx2[3] =
  (~rs1_fx2_b63 &  rs2_fx2_b63                       ) |
  ( rs1_fx2_b63 &  rs2_fx2_b63 & ~fpf_b_gteq_a_fx2[3]) |
  (~rs1_fx2_b63 & ~rs2_fx2_b63 & ~fpf_b_gteq_a_fx2[3]) ;

assign  fcmpgt16_fx2[2] =
  (~rs1_fx2_b47 &  rs2_fx2_b47                       ) |
  ( rs1_fx2_b47 &  rs2_fx2_b47 & ~fpf_b_gteq_a_fx2[2]) |
  (~rs1_fx2_b47 & ~rs2_fx2_b47 & ~fpf_b_gteq_a_fx2[2]) ;

assign  fcmpgt16_fx2[1] =
  (~rs1_fx2_b31 &  rs2_fx2_b31                       ) |
  ( rs1_fx2_b31 &  rs2_fx2_b31 & ~fpf_b_gteq_a_fx2[1]) |
  (~rs1_fx2_b31 & ~rs2_fx2_b31 & ~fpf_b_gteq_a_fx2[1]) ;

assign  fcmpgt16_fx2[0] =
  (~rs1_fx2_b15 &  rs2_fx2_b15                       ) |
  ( rs1_fx2_b15 &  rs2_fx2_b15 & ~fpf_b_gteq_a_fx2[0]) |
  (~rs1_fx2_b15 & ~rs2_fx2_b15 & ~fpf_b_gteq_a_fx2[0]) ;

assign  gt32_fx2[1] =
  ~fpf_b_gteq_a_fx2[3] | (fpf_b_eq_a_fx2[3] & ~fpf_b_gteq_a_fx2[2]);

assign  gt32_fx2[0] =
  ~fpf_b_gteq_a_fx2[1] | (fpf_b_eq_a_fx2[1] & ~fpf_b_gteq_a_fx2[0]);

assign  fcmpgt32_fx2[1] =
  (~rs1_fx2_b63 &  rs2_fx2_b63                       ) |
  ( rs1_fx2_b63 &  rs2_fx2_b63 &          gt32_fx2[1]) |
  (~rs1_fx2_b63 & ~rs2_fx2_b63 &          gt32_fx2[1]) ;

assign  fcmpgt32_fx2[0] =
  (~rs1_fx2_b31 &  rs2_fx2_b31                       ) |
  ( rs1_fx2_b31 &  rs2_fx2_b31 &          gt32_fx2[0]) |
  (~rs1_fx2_b31 & ~rs2_fx2_b31 &          gt32_fx2[0]) ;

// ------------------------------------
// le16, le32
// ------------------------------------

assign  fcmple16_fx2[3] =
  ( rs1_fx2_b63 & ~rs2_fx2_b63                       ) |
  ( rs1_fx2_b63 &  rs2_fx2_b63 &  fpf_b_gteq_a_fx2[3]) |
  (~rs1_fx2_b63 & ~rs2_fx2_b63 &  fpf_b_gteq_a_fx2[3]) ;

assign  fcmple16_fx2[2] =
  ( rs1_fx2_b47 & ~rs2_fx2_b47                       ) |
  ( rs1_fx2_b47 &  rs2_fx2_b47 &  fpf_b_gteq_a_fx2[2]) |
  (~rs1_fx2_b47 & ~rs2_fx2_b47 &  fpf_b_gteq_a_fx2[2]) ;

assign  fcmple16_fx2[1] =
  ( rs1_fx2_b31 & ~rs2_fx2_b31                       ) |
  ( rs1_fx2_b31 &  rs2_fx2_b31 &  fpf_b_gteq_a_fx2[1]) |
  (~rs1_fx2_b31 & ~rs2_fx2_b31 &  fpf_b_gteq_a_fx2[1]) ;

assign  fcmple16_fx2[0] =
  ( rs1_fx2_b15 & ~rs2_fx2_b15                       ) |
  ( rs1_fx2_b15 &  rs2_fx2_b15 &  fpf_b_gteq_a_fx2[0]) |
  (~rs1_fx2_b15 & ~rs2_fx2_b15 &  fpf_b_gteq_a_fx2[0]) ;

assign  le32_fx2[1] =
   fpf_b_gteq_a_fx2[3] & (~fpf_b_eq_a_fx2[3] |
                          (fpf_b_eq_a_fx2[3] & fpf_b_gteq_a_fx2[2]));

assign  le32_fx2[0] =
   fpf_b_gteq_a_fx2[1] & (~fpf_b_eq_a_fx2[1] |
                          (fpf_b_eq_a_fx2[1] & fpf_b_gteq_a_fx2[0]));

assign  fcmple32_fx2[1] =
  ( rs1_fx2_b63 & ~rs2_fx2_b63                       ) |
  ( rs1_fx2_b63 &  rs2_fx2_b63 &          le32_fx2[1]) |
  (~rs1_fx2_b63 & ~rs2_fx2_b63 &          le32_fx2[1]) ;

assign  fcmple32_fx2[0] =
  ( rs1_fx2_b31 & ~rs2_fx2_b31                       ) |
  ( rs1_fx2_b31 &  rs2_fx2_b31 &          le32_fx2[0]) |
  (~rs1_fx2_b31 & ~rs2_fx2_b31 &          le32_fx2[0]) ;

// ------------------------------------
// eq16, eq32
// ------------------------------------

assign  fcmpeq16_fx2[3] = fpf_b_eq_a_fx2[3] &
                          (rs1_fx2_b63 == rs2_fx2_b63);
assign  fcmpeq16_fx2[2] = fpf_b_eq_a_fx2[2];
assign  fcmpeq16_fx2[1] = fpf_b_eq_a_fx2[1];
assign  fcmpeq16_fx2[0] = fpf_b_eq_a_fx2[0];

assign  fcmpeq32_fx2[1] = fpf_b_eq_a_fx2[3] & fpf_b_eq_a_fx2[2] &
                          (rs1_fx2_b63 == rs2_fx2_b63);
assign  fcmpeq32_fx2[0] = fpf_b_eq_a_fx2[1] & fpf_b_eq_a_fx2[0];

// ------------------------------------
// ne16, ne32
// ------------------------------------

assign  fcmpne16_fx2[3] = ~fcmpeq16_fx2[3];
assign  fcmpne16_fx2[2] = ~fcmpeq16_fx2[2];
assign  fcmpne16_fx2[1] = ~fcmpeq16_fx2[1];
assign  fcmpne16_fx2[0] = ~fcmpeq16_fx2[0];
			  
assign  fcmpne32_fx2[1] = ~fcmpeq32_fx2[1];
assign  fcmpne32_fx2[0] = ~fcmpeq32_fx2[0];

// ------------------------------------
// mux vis compre results
// ------------------------------------

assign  fcmpgt16_sel_fx2 = (fac_opf_fx2[3:1] == 3'b100);
assign  fcmpgt32_sel_fx2 = (fac_opf_fx2[3:1] == 3'b110);
assign  fcmple16_sel_fx2 = (fac_opf_fx2[3:1] == 3'b000);
assign  fcmple32_sel_fx2 = (fac_opf_fx2[3:1] == 3'b010);
assign  fcmpne16_sel_fx2 = (fac_opf_fx2[3:1] == 3'b001);
assign  fcmpne32_sel_fx2 = (fac_opf_fx2[3:1] == 3'b011);
assign  fcmpeq16_sel_fx2 = (fac_opf_fx2[3:1] == 3'b101);
assign  fcmpeq32_sel_fx2 = (fac_opf_fx2[3:1] == 3'b111);

assign  vis_cmp_result_fx2[3:0] =
  ({4{fcmpgt16_sel_fx2}} &        fcmpgt16_fx2[3:0] ) |
  ({4{fcmpgt32_sel_fx2}} & {2'b0, fcmpgt32_fx2[1:0]}) |
  ({4{fcmple16_sel_fx2}} &        fcmple16_fx2[3:0] ) |
  ({4{fcmple32_sel_fx2}} & {2'b0, fcmple32_fx2[1:0]}) |
  ({4{fcmpne16_sel_fx2}} &        fcmpne16_fx2[3:0] ) |
  ({4{fcmpne32_sel_fx2}} & {2'b0, fcmpne32_fx2[1:0]}) |
  ({4{fcmpeq16_sel_fx2}} &        fcmpeq16_fx2[3:0] ) |
  ({4{fcmpeq32_sel_fx2}} & {2'b0, fcmpeq32_fx2[1:0]}) ;

// ------------------------------------
// Detect infinity result, NaN result,
//        zero source, denorm source,
//        unfinished_FPop due to denorm source
// - given from exp:  AZE, BZE, AOE, BOE
// - given from mant: AZF, BZF
// ------------------------------------

assign  a_zero_fx2   = (aze_fx2 &  azf_fx2 & fp_dual_source_fx2                   ) |
                       (aze_fx2            & fp_dual_source_fx2 &  ns_mode_fx2    ) ;
assign  a_denorm_fx2 = (aze_fx2 & ~azf_fx2 & fp_dual_source_fx2 & ~ns_mode_fx2    ) ;
assign  a_inf_fx2    = (aoe_fx2 &  azf_fx2 & fp_dual_source_fx2                   ) ;
assign  a_nan_fx2    = (aoe_fx2 & ~azf_fx2 & fp_dual_source_fx2                   ) ;
assign  a_snan_fx2   = (aoe_fx2 & ~azf_fx2 & fp_dual_source_fx2 & ~rs1_fmt_fx2[62]) ;
			       		  	           
assign  b_zero_fx2   = (bze_fx2 &  bzf_fx2 & fp_source_fx2                        ) |
                       (bze_fx2            & fp_source_fx2      &  ns_mode_fx2    ) ;
assign  b_denorm_fx2 = (bze_fx2 & ~bzf_fx2 & fp_source_fx2      & ~ns_mode_fx2    ) ;
assign  b_inf_fx2    = (boe_fx2 &  bzf_fx2 & fp_source_fx2                        ) ;
assign  b_nan_fx2    = (boe_fx2 & ~bzf_fx2 & fp_source_fx2                        ) ;
assign  b_snan_fx2   = (boe_fx2 & ~bzf_fx2 & fp_source_fx2      & ~rs2_fmt_fx2[62]) ;
assign  b_qnan_fx2   = (boe_fx2            & fp_source_fx2      &  rs2_fmt_fx2[62]) ;

// ------------------------------------
// Detect "unfinished source"
// - unfin_src will set unfinished_FPop if ~ns_mode and ~guf
// - unfin_src will set inexact flag if ~unfinished_FPop, independent of ns_mode
// ------------------------------------

assign  unfin_src_fx2 =

  ( (itype_fx2[2:0] == 3'b000) &           // FSUB(s,d),FADD(s,d)
    (dtype_fx2[2:1] == 2'b00 ) &
    ( (a_denorm_fx2 | b_denorm_fx2) &
     ~(a_inf_fx2  | b_inf_fx2 |            // not unifn if denrom +/- nan or inf
       a_nan_fx2  | b_nan_fx2  )     )) |

  ( (itype_fx2[2:0] == 3'b000) &           // FSUB(s,d),FADD(s,d)
    (dtype_fx2[2:1] == 2'b00 ) &
     ~(a_inf_fx2  | b_inf_fx2 |            // not inexact if rs1/rs2 is nan or inf
       a_nan_fx2  | b_nan_fx2  ) &
    ((aze_fx2 & ~azf_fx2 & ns_mode_fx2) |
     (bze_fx2 & ~bzf_fx2 & ns_mode_fx2)  )) |  // denorm rs1/rs2 in ns_mode may set inexact

  ( ((itype_fx2[2:0] == 3'b010) |          // fpint
     (itype_fx2[2:0] == 3'b001)  ) &       // fpfp
    ~fdtos_guf_detect_fx2          &
    b_denorm_fx2                      ) |

  ( ((itype_fx2[2:0] == 3'b010) |           // fpint
     (itype_fx2[2:0] == 3'b001)  ) &        // fpfp
    ( bze_fx2 & ~bzf_fx2 & ns_mode_fx2)   ) |  // denorm rs2 in ns_mode sets inexact

  ( (itype_fx2[2:0] == 3'b101) &           // f(s)mul
    (dtype_fx2[2:1] == 2'b00 ) &
    ~fmul_guf_detect_fx2       &
    ( (a_denorm_fx2 | b_denorm_fx2) &
     ~(a_inf_fx2  | b_inf_fx2 |            // not unifn if denrom * nan or inf or zero
       a_nan_fx2  | b_nan_fx2 |
       a_zero_fx2 | b_zero_fx2 )     )) |

  ( (itype_fx2[2:0] == 3'b101) &           // f(s)mul
    (dtype_fx2[2:1] == 2'b00 ) &
     ~(a_inf_fx2  | b_inf_fx2 |            // not inexact if rs1/rs2 is zero, nan, or inf
       a_nan_fx2  | b_nan_fx2 |
       (aze_fx2 & azf_fx2) |
       (bze_fx2 & bzf_fx2)     ) &
    ((aze_fx2 & ~azf_fx2 & ns_mode_fx2) |
     (bze_fx2 & ~bzf_fx2 & ns_mode_fx2)  )) |  // denorm rs1/rs2 in ns_mode may set inexact

  ( (itype_fx2[2:0] == 3'b110) &           // fdiv
    (dtype_fx2[2:1] == 2'b00 ) &
    ~fdiv_guf_detect_fx2       &
    ~(fdiv_ovf_detect_fx2 |
      fdiv_ovf_predict_fx2   ) &           // not fdiv overflow
    ( (a_denorm_fx2 | b_denorm_fx2) &
     ~(a_inf_fx2  | b_inf_fx2 |            // not unifn if nan, inf or zero src
       a_nan_fx2  | b_nan_fx2 |
       a_zero_fx2 | b_zero_fx2 )     )) |

  ( (itype_fx2[2:0] == 3'b110) &           // fdiv
    (dtype_fx2[2:1] == 2'b00 ) &
    ~(b_zero_fx2 | b_nan_fx2 | b_inf_fx2)  &  // not inexact if rs2 is zero, denorm, nan, or inf
    (aze_fx2 & ~azf_fx2 & ns_mode_fx2)) |  // denorm rs1 in ns_mode may set inexact

  ( (itype_fx2[2:0] == 3'b111)     &       // fsqrt
    ((b_denorm_fx2 & ~rs2_sign_fx2) |      // +denorm may signal unfin
     (bze_fx2 & ~bzf_fx2 & ns_mode_fx2))); // +/-denorm in ns_mode must set inexact

// 0in bits_on -max 1 -var {(unfin_src_fx2 | zero_src_result_fx2), inf_src_result_fx2, inf_maxint_result_fx2, nan_maxint_result_fx2, nan_default_result_fx2, fmul_den2nor_m2_predict_fx2, fdiv_den2nor_m1_predict_fx2} -active dec_valid_fx2

assign  inf_src_result_fx2 =

  ( ((itype_fx2[2:0] == 3'b000) |                    // add/sub
     (itype_fx2[2:0] == 3'b001)              ) &     // fpfp
    (a_inf_fx2  | b_inf_fx2                  ) &
   ~(a_inf_fx2  & b_inf_fx2 & logical_sub_fx2) &     // inf   - inf = nan (default)
   ~(a_nan_fx2  | b_nan_fx2                  )  ) |  // inf +/- nan = nan

  ( (itype_fx2[2:0] == 3'b101)                 &     // mul
    (a_inf_fx2  | b_inf_fx2                  ) &
   ~(a_zero_fx2 | b_zero_fx2                 ) &     // inf   * 0   = nan (default)
   ~(a_nan_fx2  | b_nan_fx2                  )  ) |  // inf   * nan = nan

  ( (itype_fx2[2:0] == 3'b110)                 &     // div
    (a_inf_fx2                               ) &     // inf   / b   = inf
   ~(             b_inf_fx2                  ) &     // inf   / inf = nan (default)
   ~(             b_nan_fx2                  )  ) |  // inf   / nan = nan

  ( (itype_fx2[2:0] == 3'b110)                 &     // div
    (             b_zero_fx2                 ) &     // a     / 0   = inf
   ~(a_zero_fx2                              ) &     // 0     / 0   = nan (default)
   ~(a_nan_fx2                               )  ) |  // nan   / 0   = nan

  ( (itype_fx2[2:0] == 3'b111)                 &     // sqrt
    (             b_inf_fx2                  ) &
   ~(                         rs2_sign_fx2   )  ) ;  // sqrt   -inf = nan (default)

assign  zero_src_result_fx2 =

  ( (itype_fx2[2:0] == 3'b011)                 &     // FxTO(s,d)
    (stype_fx2[1:0] == 2'b11 )                 &
    (bze_fx2 & bzf_fx2 & ~rs2_fx2_b63        )  ) |  //

  ( (itype_fx2[2:0] == 3'b011)                 &     // FiTO(s,d)
    (stype_fx2[1:0] == 2'b10 )                 &
    (fic_bzf32lsb_fx2                        )  ) |  //

  ( (itype_fx2[2:0] == 3'b110)                 &     // div
    (             b_inf_fx2                  ) &     // a     / inf = 0
   ~(a_inf_fx2                               ) &     // inf   / inf = nan (default)
   ~(a_nan_fx2                               )  ) |  // nan   / inf = nan

  ( (itype_fx2[2:0] == 3'b110)                 &     // div
    (a_zero_fx2                              ) &     // 0     / b   = 0
   ~(             b_zero_fx2                 ) &     // 0     / 0   = nan (default)
   ~(             b_nan_fx2                  )  ) |  // 0     / nan = nan

  ( (itype_fx2[2:0] == 3'b110)                 &     // div
    (a_denorm_fx2 | b_denorm_fx2             ) &     //
   ~(a_nan_fx2  | b_nan_fx2                  ) &     // den   / nan = nan
   ~(a_inf_fx2                               ) &     // inf   / den = inf
   ~(             b_zero_fx2                 ) &     // den   / 0   = inf
   ~(fdiv_ovf_detect_fx2 |
     fdiv_ovf_predict_fx2                    )  ) |  // not fdiv overflow

  ( (itype_fx2[2:0] == 3'b101)                 &     // mul
    (a_zero_fx2 | b_zero_fx2                 ) &     //
   ~(a_nan_fx2  | b_nan_fx2                  ) &     // 0     * nan = nan
   ~(a_inf_fx2  | b_inf_fx2                  )  ) |  // 0     * inf = nan (default)

  ( (itype_fx2[2:0] == 3'b101)                 &     // mul
    (a_denorm_fx2 | b_denorm_fx2             ) &     //
   ~(a_nan_fx2  | b_nan_fx2                  ) &     // den   * nan = nan
   ~(a_inf_fx2  | b_inf_fx2                  )  ) |  // den   * inf = inf

  ( (itype_fx2[2:0] == 3'b111)                 &     // sqrt
    (             b_zero_fx2                 )  ) |

  ( (itype_fx2[2:0] == 3'b111)                 &     // sqrt
    (             b_denorm_fx2 & ~rs2_sign_fx2) ) ;

assign  inf_maxint_result_fx2 =
  (itype_fx2[2:0] == 3'b011) &  // fpint
  (b_inf_fx2               ) ;  // rs2  =  inf

assign  nan_maxint_result_fx2 =
  (itype_fx2[2:0] == 3'b011) &  // fpint
  (b_nan_fx2               ) ;  // rs2  =  nan

assign  nan_default_result_fx2 =

  ( (itype_fx2[2:0] == 3'b000)                 &     // add/sub
    (a_inf_fx2  & b_inf_fx2 & logical_sub_fx2)  ) |  // inf   - inf = nan (default)

  ( (itype_fx2[2:0] == 3'b101)                 &     // mul
    (a_inf_fx2  | b_inf_fx2                  ) &
    (a_zero_fx2 | b_zero_fx2                 )  ) |  // inf   * 0   = nan (default)

  ( (itype_fx2[2:0] == 3'b110)                 &     // div
    ((a_inf_fx2  & b_inf_fx2 ) |                     // inf   / inf = nan (default)
     (a_zero_fx2 & b_zero_fx2)  )               ) |  // 0     / 0   = nan (default)

  ( (itype_fx2[2:0] == 3'b111)                 &     // sqrt
    (~b_nan_fx2 & ~b_zero_fx2 & rs2_sign_fx2 )  ) ;  // sqrt   -src = nan (default)

assign  nan_rs1prop_fx2 =
   (a_nan_fx2  & ~b_nan_fx2 ) |  // rs1 =  nan, rs2 != nan
   (a_snan_fx2 & ~b_snan_fx2) ;  // rs1 = snan, rs2 != snan

assign  nan_rs2prop_fx2 =
   (b_snan_fx2              ) |  // rs2 = snan
   (b_qnan_fx2 & ~a_snan_fx2) ;  // rs2 = qnan, rs1 != snan

// ------------------------------------
// floating point exception fields {cexc}
// ------------------------------------

assign  fpx_dzc_fx2 =
   fpx_dz_vld_fx2 &
   b_zero_fx2     &
  ~a_zero_fx2     &
  ~a_nan_fx2      &
  ~a_inf_fx2      ;

assign  i_fxp_nvc_fx2 =
  fcmp_nvc_fx2 |
  (fpx_nv_vld_fx2 &
   (a_snan_fx2 |
    b_snan_fx2 |
    nan_default_result_fx2));

// ------------------------------------
// Exception trap prediction
// ------------------------------------

assign  local_predict_fx2 =
  dec_valid_fx2 &
  (i_predict_fx2 | fmul_denorm_detect_fx2 | q_fmul_unf_predict_fx2 | fadd_fcvt_denorm_detect_fx2) &
  ~dec_flush_fx2 ;

assign  fgu_predict_fx2 = local_predict_fx2;

// Note: needs 0-In fix again? V2.1c fails vector FAIL_0in.tvo.
// zeroin assert_leader -leader local_predict_fx2 -follower ((fgu_fpx_ieee_trap_fw | fgu_fpx_unfin_fw) & $0in_delay((~(itype_fx5[2:1]==2'b11)),2)) -min 4 -max 4 -message "FP exception trap (non-FPD) w/out prediction"

// 0in assert -var $0in_delay(local_predict_fx2,5) -active ($0in_delay((~(itype_fx5[2:1]==2'b11)),2) & (fgu_fpx_ieee_trap_fw | fgu_fpx_unfin_fw)) -message "FP exception trap (non-FPD) w/out prediction"

// 0in assert -var $0in_delay((~local_predict_fx2),5) -active ($0in_delay((itype_fx5[2:1]==2'b11),2) & (fgu_fpx_ieee_trap_fw | fgu_fpx_unfin_fw | fgu_fpd_ieee_trap_fw | fgu_fpd_unfin_fw | fgu_fpd_idiv0_trap_fw)) -message "IDIV/FDIV/FSQRT exception trap w/ prediction"

// ------------------------------------
// Determine if the mantissa must quiet the
// propagating NaN (set frac MSB=1)
// ------------------------------------

assign  qthenan_fx2 = a_nan_fx2 | b_nan_fx2;

// ------------------------------------
// Round mode calculation
// - must force round mode to truncate if nan, otherwise
//   a propagating nan may attempt to round
// ------------------------------------

assign  rm_near_dp_fx2 =
   (dtype_fx2[2:0] == 3'b001   ) &  // dp
  ~(a_nan_fx2    | b_nan_fx2   ) &  // ~nan
  ~(a_zero_fx2   | b_zero_fx2  ) &  // ~zero
  ~(a_denorm_fx2 | b_denorm_fx2) &  // ~denorm
   (rd_mode_fx2[1:0] == 2'b00  ) ;  // nearest

assign  rm_directed_dp_fx2 =
   (dtype_fx2[2:0] == 3'b001   ) &  // dp
  ~(a_nan_fx2    | b_nan_fx2   ) &  // ~nan
  ~(a_zero_fx2   | b_zero_fx2  ) &  // ~zero
  ~(a_denorm_fx2 | b_denorm_fx2) &  // ~denorm
   (((rd_mode_fx2[1:0] == 2'b10) & ~sign_inter_fx2) |    // +inf
    ((rd_mode_fx2[1:0] == 2'b11) &  sign_inter_fx2)  );  // -inf

assign  rm_near_sp_fx2 =
   (dtype_fx2[2:0] == 3'b000   ) &  // sp
  ~(a_nan_fx2    | b_nan_fx2   ) &  // ~nan
  ~(a_zero_fx2   | b_zero_fx2  ) &  // ~zero
  ~(a_denorm_fx2 | b_denorm_fx2) &  // ~denorm
   (rd_mode_fx2[1:0] == 2'b00  ) ;  // nearest

assign  rm_directed_sp_fx2 =
   (dtype_fx2[2:0] == 3'b000   ) &  // sp
  ~(a_nan_fx2    | b_nan_fx2   ) &  // ~nan
  ~(a_zero_fx2   | b_zero_fx2  ) &  // ~zero
  ~(a_denorm_fx2 | b_denorm_fx2) &  // ~denorm
   (((rd_mode_fx2[1:0] == 2'b10) & ~sign_inter_fx2) |    // +inf
    ((rd_mode_fx2[1:0] == 2'b11) &  sign_inter_fx2)  );  // -inf

// ------------------------------------
// Detect if denorm fmul/fdiv intermediate
// result may round to norm
// ------------------------------------

assign  fdiv_aof_bzf_fx2 =
  ((dtype_fx2[2:0] == 3'b000) &
   (hi_aof_fx2 & bzf_fx2    )         ) |  // sp
  ((dtype_fx2[2:0] == 3'b001) &
   (hi_aof_fx2 & lo_aof_fx2 & bzf_fx2)) ;  // dp

assign  fmul_den2nor_m2_predict_fx2 =
   (aux_eint_eminm2_fx2     ) &  // FMUL Eint=Emin-2
  ~(aoe_fx2                 ) &  // Ea != (nan | inf)
  ~(boe_fx2                 ) &  // Eb != (nan | inf)
  ~(aze_fx2                 ) &  // Ea != (zero| den)
  ~(bze_fx2                 ) &  // Eb != (zero| den)
   (itype_fx2[2:0] == 3'b101) &  // fmul
   (dtype_fx2[2:1] == 2'b00 ) ;

assign  fdiv_den2nor_m1_predict_fx2 =
   (aux_eint_eminm1_fx2     ) &  // FDIV Eint=Emin-1
   (fdiv_aof_bzf_fx2        ) &  // FDIV ones frac / zero frac
   (aux_enable_unf_fx2      ) &  // ensure underflow, not overflow
  ~(aoe_fx2                 ) &  // Ea != (nan | inf)
  ~(boe_fx2                 ) &  // Eb != (nan | inf)
  ~(aze_fx2                 ) &  // Ea != (zero| den)
  ~(bze_fx2                 ) &  // Eb != (zero| den)
   (itype_fx2[2:0] == 3'b110) ;  // div

assign  fdiv_den2nor_sp_fx2 =
  (fdiv_den2nor_m1_predict_fx2 & rm_near_sp_fx2    ) |
  (fdiv_den2nor_m1_predict_fx2 & rm_directed_sp_fx2) ;

assign  fdiv_den2nor_dp_fx2 =
  (fdiv_den2nor_m1_predict_fx2 & rm_near_dp_fx2    ) |
  (fdiv_den2nor_m1_predict_fx2 & rm_directed_dp_fx2) ;

// ------------------------------------
// Force zero into Mle/Mse for zero/denorm source, or nan propagation
// set m{l,s}e_{zeros,ones}
// Note: (1) a non-fp source will always have a non-zero (1'b1) exponent
//       (2) a propagating NaN will enter the aligner (as Mse) only if
//           Ea=Eb=b'111...111', in which case SC=0.
//       (3) if rs1=rs2=NaN, the only case in which rs1 is chosen for the
//           propagating NaN (and not rs2) is if rs1=SNaN and rs2=QNaN.
//           See SPARC V9 manual section B.2.
// ------------------------------------

assign  mse_zeros_fx2 =
  (bze_fx2         & fp_source_fx2      & ~logical_sub_fx2 &  fpf_cmp_swap_blta_fx2) |
  (aze_fx2         & fp_dual_source_fx2 & ~logical_sub_fx2 & ~fpf_cmp_swap_blta_fx2) |
  (nan_rs2prop_fx2 &                      ~logical_sub_fx2 & ~fpf_cmp_swap_blta_fx2) |
  (nan_rs1prop_fx2 &                      ~logical_sub_fx2 &  fpf_cmp_swap_blta_fx2) ;

assign  mse_ones_fx2  =	       
  (bze_fx2         & fp_source_fx2      &  logical_sub_fx2 &  fpf_cmp_swap_blta_fx2) |
  (aze_fx2         & fp_dual_source_fx2 &  logical_sub_fx2 & ~fpf_cmp_swap_blta_fx2) |
  (nan_rs2prop_fx2 &                       logical_sub_fx2 & ~fpf_cmp_swap_blta_fx2) |
  (nan_rs1prop_fx2 &                       logical_sub_fx2 &  fpf_cmp_swap_blta_fx2) ;
				       
assign  mle_zeros_fx2 =
  (bze_fx2         & fp_source_fx2      &                    ~fpf_cmp_swap_blta_fx2) |
  (aze_fx2         & fp_dual_source_fx2 &                     fpf_cmp_swap_blta_fx2) |
  (nan_rs2prop_fx2 &                                          fpf_cmp_swap_blta_fx2) |
  (nan_rs1prop_fx2 &                                         ~fpf_cmp_swap_blta_fx2) ;

// ------------------------------------
// Mle/Mse format mux selects
// - logical subtract (fp,vis)
// - massive alignment shift
//   (entire mantissa shifted past G bit, actually we use past R bit due to 0.1X case)
// - NaN,zero handling
// - MULScc and Y[0]=0
// - SP/DP pad LSBs to prop. main adder cin
//
// Massive alignment shift detection is also used by align sticky calculation
// to force align sticky to one. However, if exp is zero then align sticky will
// not be one. If either exp is zero we know a zero mantissa proceeds thru aligner,
// and align sticky will not be one.
//
// Detect when the alignment sticky bit will be zero due to zero/denorm or nan
// source (even though a massive alignment shift may occur). Inf source is
// a don't care.
// ------------------------------------

assign  mass_align_fx2 =
  (~(itype_fx2[2:0] == 3'b011) &                                        // ~intfp
    (dtype_fx2[2:0] == 3'b000) & (fpe_align_sel_fx2[10:0] > 11'd25)) |  // sp
  (~(itype_fx2[2:0] == 3'b011) &                                        // ~intfp
    (dtype_fx2[2:0] == 3'b001) & (fpe_align_sel_fx2[10:0] > 11'd54)) ;  // dp

assign  mass_align_sticky_fx2 =
  mass_align_fx2               &
  ~(itype_fx2[2:0] == 3'b001)  &  // ~fpfp
  ~(aze_fx2 | bze_fx2 |
    aoe_fx2 | boe_fx2  );

assign  fpc_fadd_eac_enable_fx2 =
  fadd_logical_add_fx2  |  // required for proper sticky bit calculation
  (fadd_logical_sub_fx2 &
   ~(mass_align_fx2 & mass_align_sticky_fx2));  // 0in custom -fire (fadd_logical_sub_fx4 & ~fpf_ma_cout_fx4 & ~(a_nan_fx4 | b_nan_fx4) & ~fac_fgx_instr_fx4 & (|w1_vld_fx4[1:0]))

assign  fpc_mse_sel_fx2[0] =             // force Mse to zero
  mse_zeros_fx2 |                        // zero/denorm source or nan propagation
  (mulscc_fx2 & ~mulscc_y_src_fx2_b0) |  // MULScc and Y[0]=0
  (~logical_sub_fx2 & mass_align_fx2) ;  // add massive align shift

assign  fpc_mse_sel_fx2[1] =             // force Mse to one
  mse_ones_fx2 |                         // zero/denorm source or nan propagation
  ( logical_sub_fx2 & mass_align_fx2) ;  // sub massive align shift

assign  fpc_mse_sel_fx2[2] =             // pass inv aligner data thru
  logical_sub_fx2 &                      // logical subtract
  ~(itype_fx2[2:0] == 3'b011) &          // ~intfp
  ~(a_nan_fx2 | b_nan_fx2);              // ~NaN

assign  fpc_mle_sel_fx2 =                // force Mle to zero
  mle_zeros_fx2;                         // zero/denorm source or nan propagation

// ------------------------------------
// Main adder control
//
// For FADD/FSUB:
// EAC = logical_subtract & cout & ~align_sticky
// because a full exp and frac compare is performed, cout=1 if logical_subtract
// ------------------------------------

assign  fpc_fp_cin00_fx2 =
  (fadd_logical_sub_fx2 & (a_nan_fx2 | b_nan_fx2)) |                       //  FADD/FSUB logical_sub with nan propagation
  (fadd_logical_sub_fx2 & (aze_fx2   | bze_fx2  )) |                       //  FADD/FSUB logical_sub with zero source
  (logical_sub_fx2 &
   ~((itype_fx2[2:0] == 3'b000) & (dtype_fx2[2:1] == 2'b00 )));            // ~FADD/FSUB

assign  fpc_cin00_fx2    =
   logical_sub_fx2 &
   ~((itype_fx2[2:0] == 3'b010) & (dtype_fx2[2:0] == 3'b011));             // ~F(s,d)TOi

assign  fpc_cin16_48_fx2 =  logical_sub_fx2 & (dtype_fx2[2:0] == 3'b010);  // 16b sub
assign  fpc_cin32_fx2    =  logical_sub_fx2 & (dtype_fx2[2:1] == 2'b01 );  // 16/32b dest, incl. F(s,d)TOi

assign  fpc_prop16_48_fx2 = ~(dtype_fx2[2:0] == 3'b010);                   // ~16b    operation
assign  fpc_prop32_fx2 =    ~(dtype_fx2[2:1] == 2'b01 );                   // ~16/32b operation

// ------------------------------------
// FCMP(E) invalid detection
// ------------------------------------

assign  fcmp_nvc_fx2 =
  ((a_snan_fx2 | b_snan_fx2)  &
   (itype_fx2[2:0] == 3'b100) & (dtype_fx2[2:1] == 2'b00 ) & ~fcmpe_fx2) |  // FCMP(s,d)
  ((a_nan_fx2  | b_nan_fx2 )  &
   (itype_fx2[2:0] == 3'b100) & (dtype_fx2[2:1] == 2'b00 ) &  fcmpe_fx2) ;  // FCMPE(s,d)

assign  int_res_sel_fx2[1] = saverestore_fx2  & dec_valid_fx2;  // pwr mgmt: aomux free zeros
assign  int_res_sel_fx2[2] = mulscc_fx2       & dec_valid_fx2;  // pwr mgmt: aomux free zeros
assign  int_res_sel_fx2[3] = fac_fgx_popc_fx2 & dec_valid_fx2;  // pwr mgmt: aomux free zeros

                                   // pwr mgmt: aomux free zeros
assign  int_res_sel_fx2[4] =       // vis cmp
  (itype_fx2[2:0] == 3'b100) &     // cmp
  (dtype_fx2[2:1] == 2'b01 ) &     // 16bit or 32bit
  dec_valid_fx2              ;

                                   // pwr mgmt: aomux free zeros
assign  int_res_sel_fx2[5] =       // imul
  (itype_fx2[2:0] == 3'b101) &     // mul
  dec_valid_fx2              &
  exu_src_fx2                ;

assign  i_pre_div_flush_fx2 =
  dec_flush_fx2  |
  (fec_uecc_fx2 | fec_cecc_fx2) |
  exu_flush_fx2  ;

assign  idiv0_trap_fx2 =
  i_idiv0_trap_fx2 &
  ~dec_flush_fx2   &
  ~exu_flush_fx2   ;

assign  fpc_pre_div_flush_fx2 =
  idiv0_trap_fx2                |
  ((itype_fx2[2:1] == 2'b11) &
   dec_valid_fx2             &
   i_pre_div_flush_fx2        ) |
  ((itype_fx2[2:1] == 2'b11) &     // fdiv/fsqrt qualified unfin_src
   dec_valid_fx2             &
   fpx_unfin_vld_fx2         &
   unfin_src_fx2             &
   ~ns_mode_fx2               ) |
  ((itype_fx2[2:1] == 2'b11) &     // fdiv/fsqrt qualified unfin_early
   dec_valid_fx2             &
   fpx_unfin_vld_fx2         &
   fdiv_unf_detect_fx2       &
   ~fdiv_guf_detect_fx2      &
   ~fdiv_den2nor_sp_fx2      &
   ~fdiv_den2nor_dp_fx2      &
   ~ns_mode_fx2               ) ;

assign  fpc_div_default_res_fx2 =
  (itype_fx2[2:1] == 2'b11) &
  dec_valid_fx2        &
  ~i_pre_div_flush_fx2 &
  ((fp_source_fx2 &
    (inf_src_result_fx2     |
     nan_default_result_fx2 | zero_src_result_fx2 |
     nan_rs1prop_fx2        | nan_rs2prop_fx2     |
     fdiv_ovf_detect_fx2    | fdiv_unf_detect_fx2 |
                              fdiv_guf_detect_fx2  )) | idiv0_trap_fx2);

assign  aboe_fx2 = (aoe_fx2 & fp_dual_source_fx2) | boe_fx2;
assign  abze_fx2 = (aze_fx2 & fp_dual_source_fx2) | bze_fx2;

// ------------------------------------
// GSR.mask flop selects/enables
// ------------------------------------

assign  gsr0_mask_sel_fx2[0] =
  ((            tid_fx2[2:0] == 3'd0) & gsr_w_vld_fx2[0] ) ;

assign  gsr1_mask_sel_fx2[0] =
  ((            tid_fx2[2:0] == 3'd1) & gsr_w_vld_fx2[0] ) ;

assign  gsr2_mask_sel_fx2[0] =
  ((            tid_fx2[2:0] == 3'd2) & gsr_w_vld_fx2[0] ) ;

assign  gsr3_mask_sel_fx2[0] =
  ((            tid_fx2[2:0] == 3'd3) & gsr_w_vld_fx2[0] ) ;

assign  gsr4_mask_sel_fx2[0] =
  ((            tid_fx2[2:0] == 3'd4) & gsr_w_vld_fx2[0] ) ;

assign  gsr5_mask_sel_fx2[0] =
  ((            tid_fx2[2:0] == 3'd5) & gsr_w_vld_fx2[0] ) ;

assign  gsr6_mask_sel_fx2[0] =
  ((            tid_fx2[2:0] == 3'd6) & gsr_w_vld_fx2[0] ) ;

assign  gsr7_mask_sel_fx2[0] =
  ((            tid_fx2[2:0] == 3'd7) & gsr_w_vld_fx2[0] ) ;

assign  gsr0_mask_sel_fx2[1] =
  ((fac_gsr_asr_tid_fx2[2:0] == 3'd0) & fac_rng_wr_gsr_3f) |
  ((            tid_fx2[2:0] == 3'd0) & gsr_w_vld_fx2[0] ) ;

assign  gsr1_mask_sel_fx2[1] =
  ((fac_gsr_asr_tid_fx2[2:0] == 3'd1) & fac_rng_wr_gsr_3f) |
  ((            tid_fx2[2:0] == 3'd1) & gsr_w_vld_fx2[0] ) ;

assign  gsr2_mask_sel_fx2[1] =
  ((fac_gsr_asr_tid_fx2[2:0] == 3'd2) & fac_rng_wr_gsr_3f) |
  ((            tid_fx2[2:0] == 3'd2) & gsr_w_vld_fx2[0] ) ;

assign  gsr3_mask_sel_fx2[1] =
  ((fac_gsr_asr_tid_fx2[2:0] == 3'd3) & fac_rng_wr_gsr_3f) |
  ((            tid_fx2[2:0] == 3'd3) & gsr_w_vld_fx2[0] ) ;

assign  gsr4_mask_sel_fx2[1] =
  ((fac_gsr_asr_tid_fx2[2:0] == 3'd4) & fac_rng_wr_gsr_3f) |
  ((            tid_fx2[2:0] == 3'd4) & gsr_w_vld_fx2[0] ) ;

assign  gsr5_mask_sel_fx2[1] =
  ((fac_gsr_asr_tid_fx2[2:0] == 3'd5) & fac_rng_wr_gsr_3f) |
  ((            tid_fx2[2:0] == 3'd5) & gsr_w_vld_fx2[0] ) ;

assign  gsr6_mask_sel_fx2[1] =
  ((fac_gsr_asr_tid_fx2[2:0] == 3'd6) & fac_rng_wr_gsr_3f) |
  ((            tid_fx2[2:0] == 3'd6) & gsr_w_vld_fx2[0] ) ;

assign  gsr7_mask_sel_fx2[1] =
  ((fac_gsr_asr_tid_fx2[2:0] == 3'd7) & fac_rng_wr_gsr_3f) |
  ((            tid_fx2[2:0] == 3'd7) & gsr_w_vld_fx2[0] ) ;

assign  sp_source_fx2 = (stype_fx2[1:0] == 2'b00);

assign  ecc_trap_fx2 = (fec_uecc_fx2 | fec_cecc_fx2);


// ----------------------------------------------------------------------------
//                               FX3 stage
// ----------------------------------------------------------------------------

fgu_fpc_ctl_msff_ctl_macro__width_13 fx3_00  (
  .scan_in(fx3_00_scanin),
  .scan_out(fx3_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({  w1_vld_fx2[1:0], itype_fx2[2:0], dtype_fx2[2:0], stype_fx2[1:0], tid_fx2[2:0]}),
  .dout({i_w1_vld_fx3[1:0], itype_fx3[2:0], dtype_fx3[2:0], stype_fx3[1:0], tid_fx3[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_20 fx3_01  (
  .scan_in(fx3_01_scanin),
  .scan_out(fx3_01_scanout),
  .l1clk(l1clk_pm1),
  .din ({vis_cmp_result_fx2[3:0], int_res_sel_fx2[5:1], fpd_eint_fx2[10:0]}),
  .dout({vis_cmp_result_fx3[3:0], int_res_sel_fx3[5:1], fpd_eint_fx3[10:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_13 fx3_02  (
  .scan_in(fx3_02_scanin),
  .scan_out(fx3_02_scanout),
  .l1clk(l1clk_pm1),
  .din ({rs1_fx2_b31, rs2_fx2_b31, rs2_exp_fx2[10:0]}),
  .dout({rs1_fx3_b31, rs2_fx3_b31, rs2_exp_fx3[10:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_4 fx3_03  (
  .scan_in(fx3_03_scanin),
  .scan_out(fx3_03_scanout),
  .l1clk(l1clk_pm1),
  .din ({bzf_fx2,
         bze_fx2,
         a_nan_fx2,
         b_nan_fx2}),
  .dout({bzf_fx3,
         bze_fx3,
         a_nan_fx3,
         b_nan_fx3}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_5 fx3_04  (
  .scan_in(fx3_04_scanin),
  .scan_out(fx3_04_scanout),
  .l1clk(l1clk_pm1),
  .din (fsr_tem_fx2[4:0]),
  .dout(fsr_tem_fx3[4:0]),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_10 fx3_05  (
  .scan_in(fx3_05_scanin),
  .scan_out(fx3_05_scanout),
  .l1clk(l1clk_pm1),
  .din ({inf_src_result_fx2,
         zero_src_result_fx2,
         inf_maxint_result_fx2,
         nan_maxint_result_fx2,
         nan_default_result_fx2,
         qthenan_fx2,
         fic_bzf31msb_fx2,
         fmul_den2nor_m2_predict_fx2,
         fdiv_den2nor_sp_fx2,
         fdiv_den2nor_dp_fx2}),
  .dout({inf_src_result_fx3,
         zero_src_result_fx3,
         inf_maxint_result_fx3,
         nan_maxint_result_fx3,
         nan_default_result_fx3,
         qthenan_fx3,
             bzf31msb_fx3,
         fmul_den2nor_m2_predict_fx3,
         fdiv_den2nor_sp_fx3,
         fdiv_den2nor_dp_fx3}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_28 fx3_06  (
  .scan_in(fx3_06_scanin),
  .scan_out(fx3_06_scanout),
  .l1clk(l1clk_pm1),
  .din ({idiv0_trap_fx2,
         dec_flush_f2,
         sign_inter_fx2,
         div_valid_fx2,
         divq_valid_fx2,
         logical_sub_fx2,
         fsr_w1_vld_fx2[1:0],
         w1_odd32b_fx2,
         mass_align_sticky_fx2,
         fadd_logical_sub_fx2,
         fac_fsr_store_fx2,
         fgx_siam_fx2,
         gsr_w_vld_fx2[1],
         fac_gsr_asr_tid_fx2[2:0],
             rd_mode_fx2[1:0],
         rm_near_sp_fx2,
         rm_near_dp_fx2,
         rm_directed_sp_fx2,
         rm_directed_dp_fx2,
         aboe_fx2,
         abze_fx2,
             sp_source_fx2,
         fpc_div_default_res_fx2,
         fgx_pdist_fx2}),
  .dout({i_idiv0_trap_fx3,
         dec_flush_fx3,
         sign_inter_fx3,
         div_valid_fx3,
         divq_valid_fx3,
         logical_sub_fx3,
         i_fsr_w1_vld_fx3[1:0],
         w1_odd32b_fx3,
         mass_align_sticky_fx3,
         fadd_logical_sub_fx3,
         fsr_store_fx3,
         i_fgx_siam_fx3,
         i_gsr_w_vld_fx3[1],
             gsr_asr_tid_fx3[2:0],
         fpc_rd_mode_fx3[1:0],
         rm_near_sp_fx3,
         rm_near_dp_fx3,
         rm_directed_sp_fx3,
         rm_directed_dp_fx3,
         aboe_fx3,
         abze_fx3,
         fpc_sp_source_fx3,
             div_default_res_fx3,
         fgx_pdist_fx3}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_18 fx3_07  (
  .scan_in(fx3_07_scanin),
  .scan_out(fx3_07_scanout),
  .l1clk(l1clk_pm1),
  .din ({fadd_ovf_predict_fx2,
         fdtos_ovf_predict_fx2,
         fdtos_ovf_detect_fx2,
         fmul_ovf_predict_fx2,
         fmul_ovf_detect_fx2,
         fdiv_ovf_predict_fx2,
         fdiv_ovf_detect_fx2,
         fdtos_unf_predict_fx2,
         fdtos_unf_detect_fx2,
         fmul_unf_predict_fx2,
         fmul_unf_detect_fx2,
         fdiv_unf_predict_fx2,
         fdiv_unf_detect_fx2,
         fic_bof22msb_fx2,
         fdtos_guf_detect_fx2,
         fmul_guf_detect_fx2,
         fdiv_guf_detect_fx2,
         unfin_src_fx2}),
  .dout({fadd_ovf_predict_fx3,
         fdtos_ovf_predict_fx3,
         fdtos_ovf_detect_fx3,
         fmul_ovf_predict_fx3,
         fmul_ovf_detect_fx3,
         fdiv_ovf_predict_fx3,
         fdiv_ovf_detect_fx3,
         fdtos_unf_predict_fx3,
         fdtos_unf_detect_fx3,
         fmul_unf_predict_fx3,
         fmul_unf_detect_fx3,
         fdiv_unf_predict_fx3,
         fdiv_unf_detect_fx3,
             bof22msb_fx3,
         fdtos_guf_detect_fx3,
         fmul_guf_detect_fx3,
         fdiv_guf_detect_fx3,
         unfin_src_fx3}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_16 fx3_08  (
  .scan_in(fx3_08_scanin),
  .scan_out(fx3_08_scanout),
  .l1clk(l1clk_pm1),
  .din ({gsr0_mask_sel_fx2[1:0],
         gsr1_mask_sel_fx2[1:0],
         gsr2_mask_sel_fx2[1:0],
         gsr3_mask_sel_fx2[1:0],
         gsr4_mask_sel_fx2[1:0],
         gsr5_mask_sel_fx2[1:0],
         gsr6_mask_sel_fx2[1:0],
         gsr7_mask_sel_fx2[1:0]}),
  .dout({gsr0_mask_sel_fx3[1:0],
         gsr1_mask_sel_fx3[1:0],
         gsr2_mask_sel_fx3[1:0],
         gsr3_mask_sel_fx3[1:0],
         gsr4_mask_sel_fx3[1:0],
         gsr5_mask_sel_fx3[1:0],
         gsr6_mask_sel_fx3[1:0],
         gsr7_mask_sel_fx3[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_17 fx3_09  (
  .scan_in(fx3_09_scanin),
  .scan_out(fx3_09_scanout),
  .l1clk(l1clk_pm1),
  .din ({in_rngl_cdbus_1f[27:25],
         in_rngl_cdbus_1f[7:0],
         gsr_align_fx2[2:0],
         gsr_imirnd_fx2[2:0]}),
  .dout({in_rngl_cdbus_2f_b27_25[2:0],
         in_rngl_cdbus_2f[7:0],
         gsr_align_fx3[2:0],
         gsr_imirnd_fx3[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_8 fx3_10  (
  .scan_in(fx3_10_scanin),
  .scan_out(fx3_10_scanout),
  .l1clk(l1clk_pm1),
  .din ({fpx_unfin_vld_fx2,
         ns_mode_fx2,
         fpx_of_vld_fx2,
         fpx_uf_vld_fx2,
         fpx_nx_vld_fx2,
         ecc_trap_fx2,
         fpx_dzc_fx2,
         i_fxp_nvc_fx2}),
  .dout({fpx_unfin_vld_fx3,
         ns_mode_fx3,
         fpx_of_vld_fx3,
         fpx_uf_vld_fx3,
         fpx_nx_vld_fx3,
         ecc_trap_fx3,
         fpx_dzc_fx3,
         i_fxp_nvc_fx3}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fpc_emin_fx3 = fdiv_unf_predict_fx3;

assign  fpc_gsr0_mask_sel_fx3[1:0] =
  gsr0_mask_sel_fx3[1:0] & 
  {2{~((fac_tlu_flush_fx3 | dec_flush_fx3) & (~rng_wr_gsr_4f | (gsr_asr_tid_fx3[2:0] != 3'd0)))}};

assign  fpc_gsr1_mask_sel_fx3[1:0] =
  gsr1_mask_sel_fx3[1:0] &
  {2{~((fac_tlu_flush_fx3 | dec_flush_fx3) & (~rng_wr_gsr_4f | (gsr_asr_tid_fx3[2:0] != 3'd1)))}};

assign  fpc_gsr2_mask_sel_fx3[1:0] =
  gsr2_mask_sel_fx3[1:0] &
  {2{~((fac_tlu_flush_fx3 | dec_flush_fx3) & (~rng_wr_gsr_4f | (gsr_asr_tid_fx3[2:0] != 3'd2)))}};

assign  fpc_gsr3_mask_sel_fx3[1:0] =
  gsr3_mask_sel_fx3[1:0] &
  {2{~((fac_tlu_flush_fx3 | dec_flush_fx3) & (~rng_wr_gsr_4f | (gsr_asr_tid_fx3[2:0] != 3'd3)))}};

assign  fpc_gsr4_mask_sel_fx3[1:0] =
  gsr4_mask_sel_fx3[1:0] &
  {2{~((fac_tlu_flush_fx3 | dec_flush_fx3) & (~rng_wr_gsr_4f | (gsr_asr_tid_fx3[2:0] != 3'd4)))}};

assign  fpc_gsr5_mask_sel_fx3[1:0] =
  gsr5_mask_sel_fx3[1:0] &
  {2{~((fac_tlu_flush_fx3 | dec_flush_fx3) & (~rng_wr_gsr_4f | (gsr_asr_tid_fx3[2:0] != 3'd5)))}};

assign  fpc_gsr6_mask_sel_fx3[1:0] =
  gsr6_mask_sel_fx3[1:0] &
  {2{~((fac_tlu_flush_fx3 | dec_flush_fx3) & (~rng_wr_gsr_4f | (gsr_asr_tid_fx3[2:0] != 3'd6)))}};

assign  fpc_gsr7_mask_sel_fx3[1:0] =
  gsr7_mask_sel_fx3[1:0] &
  {2{~((fac_tlu_flush_fx3 | dec_flush_fx3) & (~rng_wr_gsr_4f | (gsr_asr_tid_fx3[2:0] != 3'd7)))}};

assign  gsr_w_vld_fx3[1] = i_gsr_w_vld_fx3[1] & ~fac_tlu_flush_fx3 & ~dec_flush_fx3;
assign  fgx_siam_fx3     = i_fgx_siam_fx3     & ~fac_tlu_flush_fx3 & ~dec_flush_fx3;

assign  idiv0_trap_fx3 =
  i_idiv0_trap_fx3   &
  ~dec_flush_fx3     &
  ~fac_tlu_flush_fx3 ;

assign  w1_vld_fx3[1:0] =
  i_w1_vld_fx3[1:0]       &
  {2{~dec_flush_fx3}}     &
  {2{~fac_tlu_flush_fx3}} &
  {2{~((fec_uecc_fx2 | fec_cecc_fx2) & fgx_pdist_fx3)}};  // pdist 2nd beat ecc error

assign  fsr_w1_vld_fx3[0] =
  i_fsr_w1_vld_fx3[0] &
  ~dec_flush_fx3      &
  ~fac_tlu_flush_fx3  ;

assign  fsr_w1_vld_fx3[1] =
  i_fsr_w1_vld_fx3[1] &
  ~dec_flush_fx3      &
  ~fac_tlu_flush_fx3  ;

assign  lzd_override_fx3 =
  (~logical_sub_fx3 &              // covers mul and logical_add with 1X.XX
   ~(itype_fx3[2:0] == 3'b001)) |  // never override if fpfp
  (itype_fx3[2:0] == 3'b011);      // intfp (prevent zero_mant detection due to 10.00 case.
                                   //        intfp 10.00 may result from 2's comp)

// ------------------------------------
// FDIV/FSQRT intermediate exponent (Eint) capture
//            result sign capture
// ------------------------------------

assign  div_dec_issue_fx3  =  div_valid_fx3 & ~divq_valid_fx3;
assign  div_divq_issue_fx3 =  div_valid_fx3 &  divq_valid_fx3;
assign  div_divq_load_fx3  = ~div_valid_fx3 &  divq_valid_fx3;
assign  div_hold_fx3       = ~div_dec_issue_fx3 & ~div_divq_issue_fx3;

assign  fdiv_ovf_predict_inf_fx3 =
  fdiv_ovf_predict_fx3 &
  ( (fpc_rd_mode_fx3[1:0] == 2'b00)                    |    // nearest
   ((fpc_rd_mode_fx3[1:0] == 2'b10) & ~sign_inter_fx3) |    // +inf
   ((fpc_rd_mode_fx3[1:0] == 2'b11) &  sign_inter_fx3)  );  // -inf

assign  fdiv_ovf_predict_max_fx3 =
  fdiv_ovf_predict_fx3 &
  ( (fpc_rd_mode_fx3[1:0] == 2'b01)                    |    // trunc
   ((fpc_rd_mode_fx3[1:0] == 2'b10) &  sign_inter_fx3) |    // +inf
   ((fpc_rd_mode_fx3[1:0] == 2'b11) & ~sign_inter_fx3)  );  // -inf

// ------------
// capture data for instr that is entering the div engine
// ------------

assign  div_eint_in_fx3[18:0] =
  ({19{div_dec_issue_fx3 }} & {fsr_tem_fx3[3], fsr_tem_fx3[2], fsr_tem_fx3[0],
                               ns_mode_fx3,
                               fdiv_ovf_predict_inf_fx3,
                               fdiv_ovf_predict_max_fx3,
                               fdiv_unf_predict_fx3,
                               sign_inter_fx3,
                                  fpd_eint_fx3[10:0]}) |  // load from DEC  issue
  ({19{div_divq_issue_fx3}} &    divq_eint_fx4[18:0] ) |  // load from divq issue
  ({19{div_hold_fx3      }} &     div_eint_fx4[18:0] ) ;  // hold

// ------------
// capture data for instr that is entering the div queue
// ------------

assign  divq_eint_in_fx3[18:0] =
  ({19{ div_divq_load_fx3}} & {fsr_tem_fx3[3], fsr_tem_fx3[2], fsr_tem_fx3[0],
                               ns_mode_fx3,
                               fdiv_ovf_predict_inf_fx3,
                               fdiv_ovf_predict_max_fx3,
                               fdiv_unf_predict_fx3,
                               sign_inter_fx3,
                                  fpd_eint_fx3[10:0]}) |  // load from DEC  issue
  ({19{~div_divq_load_fx3}} &    divq_eint_fx4[18:0] ) ;  // hold

// ------------------------------------
// Exponent fpint detection
// - fpint "small source" detection
//   If DP exp is < 11'h3ff, or SP exp is < 8'h7f
//   then fpint result must be forced to zero
// - fpint "large source" detection
//   max +DP source =  (2^63)-1
//   max +SP source =  (2^31)-1
//   max -DP source = -(2^63)
//   max -SP source = -(2^31)
// ------------------------------------

assign  dpint_zero_fx3 =
  ~rs2_exp_fx3[10]                        &
  ~(rs2_exp_fx3[10:0] == 11'b01111111111) &
  ~(bze_fx3 & bzf_fx3                   ) &  // ~zero src (simplifies inexact eq. later)
   (itype_fx3[2:0]    == 3'b010         ) &
					     // FdTO(i,x)
   (stype_fx3[0]      == 1'b1           ) ;  // 0in bits_on -max 1 -var {dpint_zero_fx3, spint_zero_fx3, dp_large_maxint_result_fx3, sp_large_maxint_result_fx3} -active (|w1_vld_fx3[1:0])

assign  spint_zero_fx3 =
  ~rs2_exp_fx3[7]                         &
  ~(rs2_exp_fx3[7:0] == 8'b01111111     ) &
  ~(bze_fx3 & bzf_fx3                   ) &  // ~zero src (simplifies inexact eq. later)
   (itype_fx3[2:0]   == 3'b010          ) &
   (stype_fx3[0]     == 1'b0            ) ;  // FsTO(i,x)

assign  fpint_zero_fx3 = dpint_zero_fx3 | spint_zero_fx3;

assign  dp_large_maxint_result_fx3 =

  ((((rs2_exp_fx3[10:0] >  11'b10000111110)                  ) |       // 2^(63+1023)
    ((rs2_exp_fx3[10:0] == 11'b10000111110) & ~sign_inter_fx3) |       // 2^(63+1023)
    ((rs2_exp_fx3[10:0] == 11'b10000111110) &  sign_inter_fx3          // 2^(63+1023)
                                            & ~bzf_fx3       )  ) &
   ((itype_fx3[2:0] == 3'b010) &
    (stype_fx3[1:0] == 2'b01 ) &
    (dtype_fx3[2:0] == 3'b100)                                  )  ) | // FdTOx

  ((((rs2_exp_fx3[7:0]  >      8'b10111110)                  ) |       // 2^(63+ 127)
    ((rs2_exp_fx3[7:0]  ==     8'b10111110) & ~sign_inter_fx3) |       // 2^(63+ 127)
    ((rs2_exp_fx3[7:0]  ==     8'b10111110) &  sign_inter_fx3          // 2^(63+ 127)
                                            & ~bzf_fx3       )  ) &
   ((itype_fx3[2:0] == 3'b010) &
    (stype_fx3[1:0] == 2'b00 ) &
    (dtype_fx3[2:0] == 3'b100)                                  )  ) | // FsTOx

  ((((rs2_exp_fx3[10:0] >  11'b10000011110)                  ) |       // 2^(31+1023)
    ((rs2_exp_fx3[10:0] == 11'b10000011110) & ~sign_inter_fx3) |       // 2^(31+1023)
    ((rs2_exp_fx3[10:0] == 11'b10000011110) &  sign_inter_fx3          // 2^(31+1023)
// Note: must return inexact (not invalid) as long as most signif 31-bits of frac are zero
                                            & ~bzf31msb_fx3  )  ) &
   ((itype_fx3[2:0] == 3'b010) &
    (stype_fx3[1:0] == 2'b01 ) &
    (dtype_fx3[2:0] == 3'b011)                                  )  ) ; // FdTOi

assign  sp_large_maxint_result_fx3 =

  ((((rs2_exp_fx3[7:0]  >      8'b10011110)                  ) |       // 2^(31+ 127)
    ((rs2_exp_fx3[7:0]  ==     8'b10011110) & ~sign_inter_fx3) |       // 2^(31+ 127)
    ((rs2_exp_fx3[7:0]  ==     8'b10011110) &  sign_inter_fx3          // 2^(31+ 127)
                                            & ~bzf_fx3       )  ) &
   ((itype_fx3[2:0] == 3'b010) &
    (stype_fx3[1:0] == 2'b00 ) &
    (dtype_fx3[2:0] == 3'b011)                                  )  ) ; // FsTOi

assign  maxint_result_fx3  =
  (nan_maxint_result_fx3      | inf_maxint_result_fx3 |
   dp_large_maxint_result_fx3 | sp_large_maxint_result_fx3);

assign  fpx_nvc_fx3 = i_fxp_nvc_fx3 | maxint_result_fx3;

// ------------------------------------
// GSR{im,irnd,scale,align} ASR/SIAM/ALIGNADDRESS/hold mux
//
// - architected GSR is an fx4 flop
// - the ASR/SIAM/ALIGNADDRESS/hold mux function is done in fx3
// - the instr performing the read uses the fx4 data during fx3
// ------------------------------------

assign  gsr0_11bits_fx3[10:0] =
  ({11{rng_wr_gsr_4f    & (gsr_asr_tid_fx3[2:0] == 3'd0)}}                                      // ASR
    & {in_rngl_cdbus_3f_b27_25[2:0], in_rngl_cdbus_3f[7:3], in_rngl_cdbus_3f[2:0] }) |
  ({11{fgx_siam_fx3     & (        tid_fx3[2:0] == 3'd0)}}                                      // SIAM
    & {gsr_imirnd_fx3[2:0],          gsr0_11bits_fx4[7:3],  gsr0_11bits_fx4[2:0]  }) |
  ({11{gsr_w_vld_fx3[1] & (        tid_fx3[2:0] == 3'd0)}}                                      // ALIGNADDRESS
    & {gsr0_11bits_fx4[10:8],        gsr0_11bits_fx4[7:3],  gsr_align_fx3[2:0]    }) |
  ({11{(~rng_wr_gsr_4f | (rng_wr_gsr_4f & (gsr_asr_tid_fx3[2:0] != 3'd0))) &
       ((~fgx_siam_fx3 & ~gsr_w_vld_fx3[1]) | ((fgx_siam_fx3 | gsr_w_vld_fx3[1]) & (tid_fx3[2:0] != 3'd0)))}}  // hold
    & {gsr0_11bits_fx4[10:8],        gsr0_11bits_fx4[7:3],  gsr0_11bits_fx4[2:0]  }) ;

assign  gsr1_11bits_fx3[10:0] =
  ({11{rng_wr_gsr_4f    & (gsr_asr_tid_fx3[2:0] == 3'd1)}}                                      // ASR
    & {in_rngl_cdbus_3f_b27_25[2:0], in_rngl_cdbus_3f[7:3], in_rngl_cdbus_3f[2:0] }) |
  ({11{fgx_siam_fx3     & (        tid_fx3[2:0] == 3'd1)}}                                      // SIAM
    & {gsr_imirnd_fx3[2:0],          gsr1_11bits_fx4[7:3],  gsr1_11bits_fx4[2:0]  }) |
  ({11{gsr_w_vld_fx3[1] & (        tid_fx3[2:0] == 3'd1)}}                                      // ALIGNADDRESS
    & {gsr1_11bits_fx4[10:8],        gsr1_11bits_fx4[7:3],  gsr_align_fx3[2:0]    }) |
  ({11{(~rng_wr_gsr_4f | (rng_wr_gsr_4f & (gsr_asr_tid_fx3[2:0] != 3'd1))) &
       ((~fgx_siam_fx3 & ~gsr_w_vld_fx3[1]) | ((fgx_siam_fx3 | gsr_w_vld_fx3[1]) & (tid_fx3[2:0] != 3'd1)))}}  // hold
    & {gsr1_11bits_fx4[10:8],        gsr1_11bits_fx4[7:3],  gsr1_11bits_fx4[2:0]  }) ;

assign  gsr2_11bits_fx3[10:0] =
  ({11{rng_wr_gsr_4f    & (gsr_asr_tid_fx3[2:0] == 3'd2)}}                                      // ASR
    & {in_rngl_cdbus_3f_b27_25[2:0], in_rngl_cdbus_3f[7:3], in_rngl_cdbus_3f[2:0] }) |
  ({11{fgx_siam_fx3     & (        tid_fx3[2:0] == 3'd2)}}                                      // SIAM
    & {gsr_imirnd_fx3[2:0],          gsr2_11bits_fx4[7:3],  gsr2_11bits_fx4[2:0]  }) |
  ({11{gsr_w_vld_fx3[1] & (        tid_fx3[2:0] == 3'd2)}}                                      // ALIGNADDRESS
    & {gsr2_11bits_fx4[10:8],        gsr2_11bits_fx4[7:3],  gsr_align_fx3[2:0]    }) |
  ({11{(~rng_wr_gsr_4f | (rng_wr_gsr_4f & (gsr_asr_tid_fx3[2:0] != 3'd2))) &
       ((~fgx_siam_fx3 & ~gsr_w_vld_fx3[1]) | ((fgx_siam_fx3 | gsr_w_vld_fx3[1]) & (tid_fx3[2:0] != 3'd2)))}}  // hold
    & {gsr2_11bits_fx4[10:8],        gsr2_11bits_fx4[7:3],  gsr2_11bits_fx4[2:0]  }) ;

assign  gsr3_11bits_fx3[10:0] =
  ({11{rng_wr_gsr_4f    & (gsr_asr_tid_fx3[2:0] == 3'd3)}}                                      // ASR
    & {in_rngl_cdbus_3f_b27_25[2:0], in_rngl_cdbus_3f[7:3], in_rngl_cdbus_3f[2:0] }) |
  ({11{fgx_siam_fx3     & (        tid_fx3[2:0] == 3'd3)}}                                      // SIAM
    & {gsr_imirnd_fx3[2:0],          gsr3_11bits_fx4[7:3],  gsr3_11bits_fx4[2:0]  }) |
  ({11{gsr_w_vld_fx3[1] & (        tid_fx3[2:0] == 3'd3)}}                                      // ALIGNADDRESS
    & {gsr3_11bits_fx4[10:8],        gsr3_11bits_fx4[7:3],  gsr_align_fx3[2:0]    }) |
  ({11{(~rng_wr_gsr_4f | (rng_wr_gsr_4f & (gsr_asr_tid_fx3[2:0] != 3'd3))) &
       ((~fgx_siam_fx3 & ~gsr_w_vld_fx3[1]) | ((fgx_siam_fx3 | gsr_w_vld_fx3[1]) & (tid_fx3[2:0] != 3'd3)))}}  // hold
    & {gsr3_11bits_fx4[10:8],        gsr3_11bits_fx4[7:3],  gsr3_11bits_fx4[2:0]  }) ;

assign  gsr4_11bits_fx3[10:0] =
  ({11{rng_wr_gsr_4f    & (gsr_asr_tid_fx3[2:0] == 3'd4)}}                                      // ASR
    & {in_rngl_cdbus_3f_b27_25[2:0], in_rngl_cdbus_3f[7:3], in_rngl_cdbus_3f[2:0] }) |
  ({11{fgx_siam_fx3     & (        tid_fx3[2:0] == 3'd4)}}                                      // SIAM
    & {gsr_imirnd_fx3[2:0],          gsr4_11bits_fx4[7:3],  gsr4_11bits_fx4[2:0]  }) |
  ({11{gsr_w_vld_fx3[1] & (        tid_fx3[2:0] == 3'd4)}}                                      // ALIGNADDRESS
    & {gsr4_11bits_fx4[10:8],        gsr4_11bits_fx4[7:3],  gsr_align_fx3[2:0]    }) |
  ({11{(~rng_wr_gsr_4f | (rng_wr_gsr_4f & (gsr_asr_tid_fx3[2:0] != 3'd4))) &
       ((~fgx_siam_fx3 & ~gsr_w_vld_fx3[1]) | ((fgx_siam_fx3 | gsr_w_vld_fx3[1]) & (tid_fx3[2:0] != 3'd4)))}}  // hold
    & {gsr4_11bits_fx4[10:8],        gsr4_11bits_fx4[7:3],  gsr4_11bits_fx4[2:0]  }) ;

assign  gsr5_11bits_fx3[10:0] =
  ({11{rng_wr_gsr_4f    & (gsr_asr_tid_fx3[2:0] == 3'd5)}}                                      // ASR
    & {in_rngl_cdbus_3f_b27_25[2:0], in_rngl_cdbus_3f[7:3], in_rngl_cdbus_3f[2:0] }) |
  ({11{fgx_siam_fx3     & (        tid_fx3[2:0] == 3'd5)}}                                      // SIAM
    & {gsr_imirnd_fx3[2:0],          gsr5_11bits_fx4[7:3],  gsr5_11bits_fx4[2:0]  }) |
  ({11{gsr_w_vld_fx3[1] & (        tid_fx3[2:0] == 3'd5)}}                                      // ALIGNADDRESS
    & {gsr5_11bits_fx4[10:8],        gsr5_11bits_fx4[7:3],  gsr_align_fx3[2:0]    }) |
  ({11{(~rng_wr_gsr_4f | (rng_wr_gsr_4f & (gsr_asr_tid_fx3[2:0] != 3'd5))) &
       ((~fgx_siam_fx3 & ~gsr_w_vld_fx3[1]) | ((fgx_siam_fx3 | gsr_w_vld_fx3[1]) & (tid_fx3[2:0] != 3'd5)))}}  // hold
    & {gsr5_11bits_fx4[10:8],       gsr5_11bits_fx4[7:3],  gsr5_11bits_fx4[2:0]  }) ;

assign  gsr6_11bits_fx3[10:0] =
  ({11{rng_wr_gsr_4f    & (gsr_asr_tid_fx3[2:0] == 3'd6)}}                                      // ASR
    & {in_rngl_cdbus_3f_b27_25[2:0], in_rngl_cdbus_3f[7:3], in_rngl_cdbus_3f[2:0] }) |
  ({11{fgx_siam_fx3     & (        tid_fx3[2:0] == 3'd6)}}                                      // SIAM
    & {gsr_imirnd_fx3[2:0],          gsr6_11bits_fx4[7:3],  gsr6_11bits_fx4[2:0]  }) |
  ({11{gsr_w_vld_fx3[1] & (        tid_fx3[2:0] == 3'd6)}}                                      // ALIGNADDRESS
    & {gsr6_11bits_fx4[10:8],        gsr6_11bits_fx4[7:3],  gsr_align_fx3[2:0]    }) |
  ({11{(~rng_wr_gsr_4f | (rng_wr_gsr_4f & (gsr_asr_tid_fx3[2:0] != 3'd6))) &
       ((~fgx_siam_fx3 & ~gsr_w_vld_fx3[1]) | ((fgx_siam_fx3 | gsr_w_vld_fx3[1]) & (tid_fx3[2:0] != 3'd6)))}}  // hold
    & {gsr6_11bits_fx4[10:8],        gsr6_11bits_fx4[7:3],  gsr6_11bits_fx4[2:0]  }) ;

assign  gsr7_11bits_fx3[10:0] =
  ({11{rng_wr_gsr_4f    & (gsr_asr_tid_fx3[2:0] == 3'd7)}}                                      // ASR
    & {in_rngl_cdbus_3f_b27_25[2:0], in_rngl_cdbus_3f[7:3], in_rngl_cdbus_3f[2:0] }) |
  ({11{fgx_siam_fx3     & (        tid_fx3[2:0] == 3'd7)}}                                      // SIAM
    & {gsr_imirnd_fx3[2:0],          gsr7_11bits_fx4[7:3],  gsr7_11bits_fx4[2:0]  }) |
  ({11{gsr_w_vld_fx3[1] & (        tid_fx3[2:0] == 3'd7)}}                                      // ALIGNADDRESS
    & {gsr7_11bits_fx4[10:8],        gsr7_11bits_fx4[7:3],  gsr_align_fx3[2:0]    }) |
  ({11{(~rng_wr_gsr_4f | (rng_wr_gsr_4f & (gsr_asr_tid_fx3[2:0] != 3'd7))) &
       ((~fgx_siam_fx3 & ~gsr_w_vld_fx3[1]) | ((fgx_siam_fx3 | gsr_w_vld_fx3[1]) & (tid_fx3[2:0] != 3'd7)))}}  // hold
    & {gsr7_11bits_fx4[10:8],        gsr7_11bits_fx4[7:3],  gsr7_11bits_fx4[2:0]  }) ;

assign  gsr_11bits_fx3[7:0] =
  ({ 8{(            tid_fx2[2:0] == 3'd0)}} & gsr0_11bits_fx3[7:0] ) |
  ({ 8{(            tid_fx2[2:0] == 3'd1)}} & gsr1_11bits_fx3[7:0] ) |
  ({ 8{(            tid_fx2[2:0] == 3'd2)}} & gsr2_11bits_fx3[7:0] ) |
  ({ 8{(            tid_fx2[2:0] == 3'd3)}} & gsr3_11bits_fx3[7:0] ) |
  ({ 8{(            tid_fx2[2:0] == 3'd4)}} & gsr4_11bits_fx3[7:0] ) |
  ({ 8{(            tid_fx2[2:0] == 3'd5)}} & gsr5_11bits_fx3[7:0] ) |
  ({ 8{(            tid_fx2[2:0] == 3'd6)}} & gsr6_11bits_fx3[7:0] ) |
  ({ 8{(            tid_fx2[2:0] == 3'd7)}} & gsr7_11bits_fx3[7:0] ) ;

assign  gsr_asr_11bits_fx3[10:0] =
  ({11{(fac_gsr_asr_tid_fx2[2:0] == 3'd0)}} & gsr0_11bits_fx3[10:0]) |
  ({11{(fac_gsr_asr_tid_fx2[2:0] == 3'd1)}} & gsr1_11bits_fx3[10:0]) |
  ({11{(fac_gsr_asr_tid_fx2[2:0] == 3'd2)}} & gsr2_11bits_fx3[10:0]) |
  ({11{(fac_gsr_asr_tid_fx2[2:0] == 3'd3)}} & gsr3_11bits_fx3[10:0]) |
  ({11{(fac_gsr_asr_tid_fx2[2:0] == 3'd4)}} & gsr4_11bits_fx3[10:0]) |
  ({11{(fac_gsr_asr_tid_fx2[2:0] == 3'd5)}} & gsr5_11bits_fx3[10:0]) |
  ({11{(fac_gsr_asr_tid_fx2[2:0] == 3'd6)}} & gsr6_11bits_fx3[10:0]) |
  ({11{(fac_gsr_asr_tid_fx2[2:0] == 3'd7)}} & gsr7_11bits_fx3[10:0]) ;

assign  gsr_imirnd_held_fx3[2:0] =
  ({ 3{(            tid_fx1[2:0] == 3'd0)}} & gsr0_11bits_fx4[10:8]) |
  ({ 3{(            tid_fx1[2:0] == 3'd1)}} & gsr1_11bits_fx4[10:8]) |
  ({ 3{(            tid_fx1[2:0] == 3'd2)}} & gsr2_11bits_fx4[10:8]) |
  ({ 3{(            tid_fx1[2:0] == 3'd3)}} & gsr3_11bits_fx4[10:8]) |
  ({ 3{(            tid_fx1[2:0] == 3'd4)}} & gsr4_11bits_fx4[10:8]) |
  ({ 3{(            tid_fx1[2:0] == 3'd5)}} & gsr5_11bits_fx4[10:8]) |
  ({ 3{(            tid_fx1[2:0] == 3'd6)}} & gsr6_11bits_fx4[10:8]) |
  ({ 3{(            tid_fx1[2:0] == 3'd7)}} & gsr7_11bits_fx4[10:8]) ;

assign  siam_1ahead_sel_fx3 =
  fac_fgx_siam_fx2 & (tid_fx1[2:0] == tid_fx2[2:0]);  // note: this siam not qual by flushes

assign  siam_2ahead_sel_fx3 =
  ~siam_1ahead_sel_fx3 &
  fgx_siam_fx3     & (tid_fx1[2:0] == tid_fx3[2:0]);

assign  siam_none_sel_fx3 =
  ~siam_1ahead_sel_fx3 &
  ~siam_2ahead_sel_fx3 ;

assign  {gsr_im_fx3, gsr_irnd_fx3[1:0]} =
  ({3{siam_1ahead_sel_fx3}} & gsr_imirnd_fx2[2:0]     ) |
  ({3{siam_2ahead_sel_fx3}} & gsr_imirnd_fx3[2:0]     ) |
  ({3{siam_none_sel_fx3  }} & gsr_imirnd_held_fx3[2:0]) ;


// ----------------------------------------------------------------------------
//                               FX4 stage
// ----------------------------------------------------------------------------

fgu_fpc_ctl_msff_ctl_macro__width_4 fx4_00  (
  .scan_in(fx4_00_scanin),
  .scan_out(fx4_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({rs1_fx3_b31, rs2_fx3_b31, fpc_rd_mode_fx3[1:0]}),
  .dout({rs1_fx4_b31, rs2_fx4_b31,     rd_mode_fx4[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_37 fx4_01  (
  .scan_in(fx4_01_scanin),
  .scan_out(fx4_01_scanout),
  .l1clk(l1clk_pm1),
  .din ({w1_vld_fx3[1:0],
         fgu_cmp_fcc_fx3[1:0],
         fgu_cmp_fcc_vld_fx3[3:0],
         idiv0_trap_fx3,
         sign_inter_fx3,
             lzd_override_fx3,
         logical_sub_fx3,
         fpint_zero_fx3,
         fsr_w1_vld_fx3[1:0],
         a_nan_fx3,
         b_nan_fx3,
         fpf_byte_unsure_x_dp_fx3[1:0],
         fpf_byte_unsure_x_sp_fx3[1:0],
         w1_odd32b_fx3,
         mass_align_sticky_fx3,
         fadd_logical_sub_fx3,
         fsr_store_fx3,
         fmul_den2nor_m2_predict_fx3,
         fdiv_den2nor_sp_fx3,
         fdiv_den2nor_dp_fx3,
         rm_near_sp_fx3,
         rm_near_dp_fx3,
         rm_directed_sp_fx3,
         rm_directed_dp_fx3,
         aboe_fx3,
         abze_fx3,
         div_default_res_fx3,
         dec_flush_fx3,
         fac_tlu_flush_fx3}),
  .dout({i_w1_vld_fx4[1:0],
                 fcc_fx4[1:0],
                 fcc_vld_fx4[3:0],
         idiv0_trap_fx4,
         sign_inter_fx4,
         fpc_lzd_override_fx4,
         logical_sub_fx4,
         fpint_zero_fx4,
         i_fsr_w1_vld_fx4[1:0],
         a_nan_fx4,
         b_nan_fx4,
             byte_unsure_x_dp_fx4[1:0],
             byte_unsure_x_sp_fx4[1:0],
         w1_odd32b_fx4,
         mass_align_sticky_fx4,
         fadd_logical_sub_fx4,
         fsr_store_fx4,
         fmul_den2nor_m2_predict_fx4,
         fdiv_den2nor_sp_fx4,
         fdiv_den2nor_dp_fx4,
         rm_near_sp_fx4,
         rm_near_dp_fx4,
         rm_directed_sp_fx4,
         rm_directed_dp_fx4,
         aboe_fx4,
         abze_fx4,
         div_default_res_fx4,
         dec_flush_fx4,
         tlu_flush_fgu_fx4}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_15 fx4_02  (
  .scan_in(fx4_02_scanin),
  .scan_out(fx4_02_scanout),
  .l1clk(l1clk_pm1),
  .din ({vis_cmp_result_fx3[3:0],     int_res_sel_fx3[5:1], itype_fx3[2:0], dtype_fx3[2:0]}),
  .dout({vis_cmp_result_fx4[3:0], fpc_int_res_sel_fx4[5:1], itype_fx4[2:0], dtype_fx4[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_38 fx4_03  (
  .scan_in(fx4_03_scanin),
  .scan_out(fx4_03_scanout),
  .l1clk(l1clk_pm1),
  .din ({div_eint_in_fx3[18:0], divq_eint_in_fx3[18:0]}),
  .dout({div_eint_fx4[18:0],    divq_eint_fx4[18:0]   }),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_5 fx4_04  (
  .scan_in(fx4_04_scanin),
  .scan_out(fx4_04_scanout),
  .l1clk(l1clk_pm1),
  .din (fsr_tem_fx3[4:0]),
  .dout(fsr_tem_fx4[4:0]),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_5 fx4_05  (
  .scan_in(fx4_05_scanin),
  .scan_out(fx4_05_scanout),
  .l1clk(l1clk_pm1),
  .din ({inf_src_result_fx3,
         zero_src_result_fx3,
         nan_default_result_fx3,
         qthenan_fx3,
         maxint_result_fx3}),
  .dout({inf_src_result_fx4,
         zero_src_result_fx4,
         nan_default_result_fx4,
         fpc_qthenan_fx4,
         maxint_result_fx4}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_16 fx4_06  (
  .scan_in(fx4_06_scanin),
  .scan_out(fx4_06_scanout),
  .l1clk(l1clk_pm1),
  .din ({fadd_ovf_predict_fx3,
         fdtos_ovf_predict_fx3,
         fdtos_ovf_detect_fx3,
         fmul_ovf_predict_fx3,
         fmul_ovf_detect_fx3,
         fdiv_ovf_detect_fx3,
         fdtos_unf_predict_fx3,
         fdtos_unf_detect_fx3,
         fmul_unf_predict_fx3,
         fmul_unf_detect_fx3,
         fdiv_unf_detect_fx3,
         bof22msb_fx3,
         fdtos_guf_detect_fx3,
         fmul_guf_detect_fx3,
         fdiv_guf_detect_fx3,
         unfin_src_fx3}),
  .dout({fadd_ovf_predict_fx4,
         fdtos_ovf_predict_fx4,
         fdtos_ovf_detect_fx4,
         fmul_ovf_predict_fx4,
         fmul_ovf_detect_fx4,
         fdiv_ovf_detect_fx4,
         fdtos_unf_predict_fx4,
         fdtos_unf_detect_fx4,
         fmul_unf_predict_fx4,
         fmul_unf_detect_fx4,
         fdiv_unf_detect_fx4,
         bof22msb_fx4,
         fdtos_guf_detect_fx4,
         fmul_guf_detect_fx4,
         fdiv_guf_detect_fx4,
         unfin_src_fx4}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_88 fx4_07  (				// FS:wmr_protect
  .scan_in(fx4_07_wmr_scanin),
  .scan_out(fx4_07_wmr_scanout),
  .siclk(spc_aclk_wmr),
  .l1clk(l1clk_pm1),
  .din ({gsr0_11bits_fx3[10:0],
         gsr1_11bits_fx3[10:0],
         gsr2_11bits_fx3[10:0],
         gsr3_11bits_fx3[10:0],
         gsr4_11bits_fx3[10:0],
         gsr5_11bits_fx3[10:0],
         gsr6_11bits_fx3[10:0],
         gsr7_11bits_fx3[10:0]}),
  .dout({gsr0_11bits_fx4[10:0],
         gsr1_11bits_fx4[10:0],
         gsr2_11bits_fx4[10:0],
         gsr3_11bits_fx4[10:0],
         gsr4_11bits_fx4[10:0],
         gsr5_11bits_fx4[10:0],
         gsr6_11bits_fx4[10:0],
         gsr7_11bits_fx4[10:0]}),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_8 fx4_08  (
  .scan_in(fx4_08_scanin),
  .scan_out(fx4_08_scanout),
  .l1clk(l1clk_pm1),
  .din ({fpx_unfin_vld_fx3,
         ns_mode_fx3,
         fpx_of_vld_fx3,
         fpx_uf_vld_fx3,
         fpx_nx_vld_fx3,
         ecc_trap_fx3,
         fpx_dzc_fx3,
         fpx_nvc_fx3}),
  .dout({fpx_unfin_vld_fx4,
         ns_mode_fx4,
         fpx_of_vld_fx4,
         fpx_uf_vld_fx4,
         fpx_nx_vld_fx4,
         ecc_trap_fx4,
         fpx_dzc_fx4,
         fpx_nvc_fx4}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_11 fx4_09  (
  .scan_in(fx4_09_scanin),
  .scan_out(fx4_09_scanout),
  .l1clk(l1clk_pm1),
  .din ({in_rngl_cdbus_2f_b27_25[2:0],
         in_rngl_cdbus_2f[7:0]}),
  .dout({in_rngl_cdbus_3f_b27_25[2:0],
         in_rngl_cdbus_3f[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_1 fx4_10  (
  .scan_in(fx4_10_scanin),
  .scan_out(fx4_10_scanout),
  .l1clk(l1clk_pm2),
  .din ({lsu_fgu_exception_w}),  // requires free running clk
  .dout({stfsr_exception_fx4}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_19 fx4_11  (
  .scan_in(fx4_11_scanin),
  .scan_out(fx4_11_scanout),
  .l1clk(l1clk_pm1),
  .din ({gsr_11bits_fx3[7:0],
             gsr_asr_11bits_fx3[10:0]}),
  .dout({fpc_gsr_scale_fx4[4:0], fpc_gsr_align_fx4[2:0],
         fpc_gsr_asr_11bits_fx4[10:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

// ------------------------------------
// Main adder output format mux selects
// ------------------------------------

assign  fpc_ma_fmt_sel_fx4[0] =    // logical_sub 00.1X, not possible for logical_add
  ( logical_sub_fx4        ) &
  (itype_fx4[2:0] == 3'b000) &
  (dtype_fx4[2:1] == 2'b00 ) &
  (fpf_ma_sum_fx4[63:62] == 2'b01);

assign  fpc_ma_fmt_sel_fx4[1] =
  ((~logical_sub_fx4        ) &    // logical_add 1X.XX
   (itype_fx4[2:0] == 3'b000) &
   (dtype_fx4[2:1] == 2'b00 ) &
   (fpf_ma_cout_fx4         )  ) |
  ((itype_fx4[2:0] == 3'b011) &    // intfp 10.00 (may result from 2's comp)
   (fpf_ma_cout_fx4         )  ) ;

assign  fpc_ma_fmt_sel_fx4[2] =    // default for non fmul
  fpc_qthenan_fx4                | // ensure nan propagation for fmul, fdiv, fsqrt
  ~(itype_fx4[2:0] == 3'b101);     // ~mul

assign  fpc_ma_fmt_sel_fx4[3] =
  fmul_den2nor_m2_predict_fx4;     // fmul 11.XX, Eint=Emin-2, denorm inter. result may rnd to norm

assign  fpc_ma_fmt_sel_fx4[4] =
  fmul_unf_predict_fx4;            // fmul 01.XX, Eint=Emin-1, denorm inter. result may rnd to norm

// ------------------------------------
// Integer output constant mux selects
// ------------------------------------

assign  maxpos_result_fx4  = maxint_result_fx4  & ~sign_inter_fx4;
assign  maxneg_result_fx4  = maxint_result_fx4  &  sign_inter_fx4;

assign  int_sel_fx4[0] =                                      // 64'h0000000000000000
  (itype_fx4[2:0] == 3'b010) &                                // F(s,d)TO(i,x)
  fpint_zero_fx4;                                             // zero result

assign  int_sel_fx4[1] = maxneg_result_fx4;                   // 64'h8000000000000000

assign  int_sel_fx4[2] =                                      // 64'h7fffffffffffffff
  nan_default_result_fx4 | maxpos_result_fx4;

assign  int_sel_fx4[3] =
  ((itype_fx4[2:0] == 3'b000) & (dtype_fx4[2:1] == 2'b01)) |  // vis partitioned add
  ((itype_fx4[2:0] == 3'b010)                            ) ;  // F(s,d)TO(i,x)

assign  mulscc_iccn_fx4 =  fpf_ma_sum_fx4[31];
assign  mulscc_iccc_fx4 =  fpf_ma_sum_fx4[32];

// overflow if both oprands have same sign and sign of sum is different
assign  mulscc_iccv_fx4 =
  ( rs1_fx4_b31 &  rs2_fx4_b31 & ~fpf_ma_sum_fx4[31]) |
  (~rs1_fx4_b31 & ~rs2_fx4_b31 &  fpf_ma_sum_fx4[31]) ;

assign  exp_sel_mul_fx4 = (itype_fx4[2:0] == 3'b101) & ~(a_nan_fx4 | b_nan_fx4);  // mul
assign  fpc_sp_dest_fx4 = (dtype_fx4[2:0] == 3'b000);  // sp

// ------------------------------------
// FDIV/FSQRT result exponent (Eresult)
//   Eresult=Eint-Eadj
// ------------------------------------

assign  fpc_fpd_sign_res = div_eint_fx4[11];

assign  fpd_const_sel[0] =  // select fdd frac and not fdiv underflow/overflow
  ~( div_eint_fx4[12]    &  fdc_dec_exp_early) &  // ~(fdiv_unf_predict => detect)
  ~(|div_eint_fx4[14:13] & ~fdc_dec_exp_early) ;  // ~(fdiv_ovf_predict => detect)

assign  fpd_const_sel[1] =  // select fdiv overflow +/-max (frac=ff..ff)
   ( div_eint_fx4[13]    & ~fdc_dec_exp_early) ;  //  (fdiv_ovf_predict => detect)

// 0in bits_on -max 1 -var fpd_const_sel[1:0]

assign  fpd_exp_res[10:0] =
  ({11{~fdc_dec_exp_early     & fpd_const_sel[0]}} & (div_eint_fx4[10:0]                  )) |  // Eresult=Eint-0
  ({11{ fdc_dec_exp_early     & fpd_const_sel[0]}} & (div_eint_fx4[10:0] + 11'b11111111111)) |  // Eresult=Eint-1
  ({11{~(|fpd_const_sel[1:0]) & div_eint_fx4[12]}} & (                     11'b00000000000)) |  // Eresult=zero
  ({11{~(|fpd_const_sel[1:0]) & div_eint_fx4[14]}} & (                     11'b11111111111)) |  // Eresult=inf
  ({11{ fpd_const_sel[1]                        }} & (                     11'b11111111110)) ;  // Eresult=max

// ------------------------------------
// floating point zero sign
// ------------------------------------

assign  sign_retain_zero_fx4 = ~logical_sub_fx4;

assign  sign_zero_fx4 =
  (~sign_retain_zero_fx4 & (rd_mode_fx4[1:0] == 2'b11)) |  // rnd -inf
  ( sign_retain_zero_fx4 &  sign_inter_fx4            ) ;

// ------------------------------------
// Add pipe Rinc calculation
// - FADD(s,d), FSUB(s,d), FiTOs, FxTO(s,d), FdTOs
// - Determine if LSB should be inc due to round
//
// Rounding equations:
//
// Rinc = 
//   (near &  G    & (LSB | X)) |
//   (+inf & ~sign & (G   | X)) |
//   (-inf &  sign & (G   | X)) ;
//
// directed = 
//   (+inf & ~sign) |
//   (-inf &  sign) ;
//
// Rinc =  // nand3-nand4 delay
//   (near     & G & LSB) |
//   (near     & G & X  ) |
//   (directed & G      ) |
//   (directed     & X  ) ;
//
// ------------------------------------

// ignore cout if logical_sub
assign  add_ma_cout_fx4 = ~(logical_sub_fx4 & (itype_fx4 == 3'b000)) & fpf_ma_cout_fx4;

assign  convert_fmt_1xx_fx4 =
   fpf_ma_cout_fx4 &                                         // 1X.XX
  (((itype_fx4[2:0] == 3'b011) |                             // FxTOs, FiTOs, FdTOs
    (itype_fx4[2:0] == 3'b001)  ) &
   (dtype_fx4       == 3'b000)     );

assign  convert_fmt_01x_fx4 =
  ~fpf_ma_cout_fx4 &                                         // 01.XX
  (((itype_fx4[2:0] == 3'b011) |                             // FxTOs, FiTOs, FdTOs
    (itype_fx4[2:0] == 3'b001)  ) &
   (dtype_fx4       == 3'b000)     );

assign  fxtod_fmt_1xx_fx4 =
   fpf_ma_cout_fx4 &                                         // 1X.XX
  ((itype_fx4[2:0]  == 3'b011) &                             // FxTOd
   (dtype_fx4       == 3'b001)     );

assign  fxtod_fmt_01x_fx4 =
  ~fpf_ma_cout_fx4 &                                         // 01.XX
  ((itype_fx4[2:0]  == 3'b011) &                             // FxTOd
   (dtype_fx4       == 3'b001)     );

assign  add_fmt_1xx_fx4 =
  convert_fmt_1xx_fx4 | fxtod_fmt_1xx_fx4 |                  // FxTOs, FiTOs, FdTOs, FxTOd
  (({add_ma_cout_fx4                       } == 1'b1  ) &    // 1X.XX
   (itype_fx4[2:0] == 3'b000)                            );  // add

assign  add_fmt_01x_fx4 =
  convert_fmt_01x_fx4 | fxtod_fmt_01x_fx4 |                  // FxTOs, FiTOs, FdTOs, FxTOd
  (({add_ma_cout_fx4, fpf_ma_sum_fx4[63]   } == 2'b01 ) &    // 01.XX
   (itype_fx4[2:0] == 3'b000)                            );  // add

assign  add_fmt_001_fx4 =
  (({add_ma_cout_fx4, fpf_ma_sum_fx4[63:62]} == 3'b001) &    // 00.1X
   (itype_fx4[2:0] == 3'b000)                            );  // add

assign  aln_fmt_1xx_fx4 =
  (({add_ma_cout_fx4                       } == 1'b1  ) &    // 1X.XX
   (itype_fx4[2:0] == 3'b000)                            );  // add

assign  aln_fmt_01x_fx4 =
  (({add_ma_cout_fx4, fpf_ma_sum_fx4[63]   } == 2'b01 ) &    // 01.XX
   (itype_fx4[2:0] == 3'b000)                            );  // add

assign  add_lsb_bit_dp_fx4 =
  (add_fmt_1xx_fx4 &   fpf_ma_sum_fx4[12]   ) |  // 1X.XX
  (add_fmt_01x_fx4 &   fpf_ma_sum_fx4[11]   ) |  // 01.XX
  (add_fmt_001_fx4 &   fpf_ma_sum_fx4[10]   ) ;  // 00.1X

assign  add_g_bit_dp_fx4 =
  (add_fmt_1xx_fx4 &   fpf_ma_sum_fx4[11]   ) |  // 1X.XX
  (add_fmt_01x_fx4 &   fpf_ma_sum_fx4[10]   ) |  // 01.XX
  (add_fmt_001_fx4 &   fpf_ma_sum_fx4[9]   ) ;  // 00.1X

assign  add_lsb_bit_sp_fx4 =
  (add_fmt_1xx_fx4 &   fpf_ma_sum_fx4[41]   ) |  // 1X.XX
  (add_fmt_01x_fx4 &   fpf_ma_sum_fx4[40]   ) |  // 01.XX
  (add_fmt_001_fx4 &   fpf_ma_sum_fx4[39]   ) ;  // 00.1X

assign  add_g_bit_sp_fx4 =
  (add_fmt_1xx_fx4 &   fpf_ma_sum_fx4[40]   ) |  // 1X.XX
  (add_fmt_01x_fx4 &   fpf_ma_sum_fx4[39]   ) |  // 01.XX
  (add_fmt_001_fx4 &   fpf_ma_sum_fx4[38]   ) ;  // 00.1X

assign  align_x_bit_dp_fx4 =
  (aln_fmt_1xx_fx4 & ( byte_unsure_x_dp_fx4[1] |   // 1X.XX
                       byte_unsure_x_dp_fx4[0] |
                       fpf_ma_sum_fx4[10]      |
                       fpf_ma_sum_fx4[9]      |
                      ~fpf_align_sticky_fx4_l)) |
  (aln_fmt_01x_fx4 & ( mass_align_sticky_fx4   |   // 01.XX
                       byte_unsure_x_dp_fx4[0] |
                       fpf_ma_sum_fx4[9]      |
                      (~fpf_align_sticky_fx4_l & ~abze_fx4))) |  // ignore sticky if zero exp (must be fmt_01x)
  (add_fmt_001_fx4 & (~fpf_align_sticky_fx4_l)) ;  // 00.1X

assign  align_x_bit_sp_fx4 =
  (aln_fmt_1xx_fx4 & ( byte_unsure_x_sp_fx4[1] |   // 1X.XX
                       byte_unsure_x_sp_fx4[0] |
                       fpf_ma_sum_fx4[39]      |
                       fpf_ma_sum_fx4[38]      |
                      ~fpf_align_sticky_fx4_l)) |
  (aln_fmt_01x_fx4 & ( mass_align_sticky_fx4   |   // 01.XX
                       byte_unsure_x_sp_fx4[0] |
                       fpf_ma_sum_fx4[38]      |
                      (~fpf_align_sticky_fx4_l & ~abze_fx4))) |  // ignore sticky if zero exp (must be fmt_01x)
  (add_fmt_001_fx4 & (~fpf_align_sticky_fx4_l)) ;  // 00.1X

assign  convert_x_bit_sp_fx4 =
  (convert_fmt_1xx_fx4 & (fpf_ma_sum_fx4[39] |        // 1X.XX
                          fic_convert_sticky_fx4)) |
  (convert_fmt_01x_fx4 & (fic_convert_sticky_fx4)) ;  // 01.XX

assign  fxtod_x_bit_dp_fx4 =
  (fxtod_fmt_1xx_fx4   & (fpf_ma_sum_fx4[10] |        // 1X.XX
                          fic_fxtod_sticky_fx4  )) |
  (fxtod_fmt_01x_fx4   & (fic_fxtod_sticky_fx4  )) ;  // 01.XX

assign  add_x_bit_dp_fx4 = align_x_bit_dp_fx4 | fxtod_x_bit_dp_fx4;
assign  add_x_bit_sp_fx4 = align_x_bit_sp_fx4 | convert_x_bit_sp_fx4;

// ------------------------------------
// fpint inexact result calculation
// - inexact = G | (R | X)
// - set inexact for fpint "small source" detection
//   If DP exp is < 11'h3ff, or SP exp is < 8'h7f
//   then fpint result must be forced to zero and
//   inexact set
// ------------------------------------

assign  fpint_nxc_i_fx4 =
  ~maxint_result_fx4         &  // ~invalid (nan,inf,large)
  (dtype_fx4[2:0] == 3'b011) &
  (itype_fx4[2:0] == 3'b010) &  // FsTOi, FdTOi
  fic_ftoi_nx_fx4            ;

assign  fpint_nxc_x_fx4 =
  ~maxint_result_fx4         &  // ~invalid (nan,inf,large)
  (dtype_fx4[2:0] == 3'b100) &
  (itype_fx4[2:0] == 3'b010) &  // FsTOx, FdTOx
  fic_ftox_nx_fx4            ;

assign  fpint_nxc_fx4 =
  fpint_nxc_i_fx4 |
  fpint_nxc_x_fx4 |
  fpint_zero_fx4;               // fpint "small source"

// ------------------------------------
// Detect all cases where intermediate denorm rounds to norm
// ------------------------------------

assign  fdtos_den2nor_fx4 =
  fdtos_unf_predict_fx4 &
                                           // post-denorm LSB is included in bof22msb
   ((rm_near_sp_fx4     & (bof22msb_fx4 &   fpf_ma_sum_fx4[40]                             )) |
    (rm_directed_sp_fx4 & (bof22msb_fx4 & (|fpf_ma_sum_fx4[40:39] | fic_convert_sticky_fx4)))  );

assign  fdiv_fdtos_den2nor_sp_fx4 = fdiv_den2nor_sp_fx4 | fdtos_den2nor_fx4;

assign  w1_vld_fx4[1:0] =
  i_w1_vld_fx4[1:0] &
  ({2{~(itype_fx4[2:1] == 2'b11) |        // ~div/sqrt
       ((itype_fx4[2:1] == 2'b11) &
         div_default_res_fx4      &
         ~dec_flush_fx4           &
         ~tlu_flush_fgu_fx4        )}});  //  div/sqrt and default result

assign  fsr_w1_vld_fx4[0] =
  i_fsr_w1_vld_fx4[0] &
  (   ~(itype_fx4[2:1] == 2'b11) |        // ~div/sqrt
       ((itype_fx4[2:1] == 2'b11) &
         div_default_res_fx4      &
         ~dec_flush_fx4           &
         ~tlu_flush_fgu_fx4        )  );  //  div/sqrt and default result

assign  fsr_w1_vld_fx4[1] =
  i_fsr_w1_vld_fx4[1] &
  ~(fsr_store_fx4 & stfsr_exception_fx4);  // ensure stfsr completes without error


// ----------------------------------------------------------------------------
//                               FX5 stage
// ----------------------------------------------------------------------------

fgu_fpc_ctl_msff_ctl_macro__width_8 fx5_00  (
  .scan_in(fx5_00_scanin),
  .scan_out(fx5_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({w1_vld_fx4[1:0], fcc_fx4[1:0],     fcc_vld_fx4[3:0]}),
  .dout({w1_vld_fx5[1:0], fcc_fx5[1:0], fpc_fcc_vld_fx5[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_8 fx5_01  (
  .scan_in(fx5_01_scanin),
  .scan_out(fx5_01_scanout),
  .l1clk(l1clk_pm1),
  .din ({itype_fx4[2:0], dtype_fx4[2:0], rd_mode_fx4[1:0]}),
  .dout({itype_fx5[2:0], dtype_fx5[2:0], rd_mode_fx5[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_36 fx5_02  (
  .scan_in(fx5_02_scanin),
  .scan_out(fx5_02_scanout),
  .l1clk(l1clk_pm1),
  .din ({    int_sel_fx4[3:0],
             vis_cmp_result_fx4[3:0],
         fpc_int_res_sel_fx4[2],
         fpc_ma_fmt_sel_fx4[0],
         idiv0_trap_fx4,
         mulscc_iccn_fx4,
         fic_mulscc_iccz_fx4,
         mulscc_iccv_fx4,
         mulscc_iccc_fx4,
         fic_mulscc_xccz_fx4,
         fdc_xicc_z_early[1:0],
         fdc_icc_v_early,
         exp_sel_mul_fx4,
         sign_inter_fx4,
         sign_zero_fx4,
         fpf_ma_sum_fx4[10],
         fsr_w1_vld_fx4[1:0],
         fac_fgx_instr_fx4,
         w1_odd32b_fx4,
         fpf_ma_cout_fx4,
         fadd_logical_sub_fx4,
         fsr_store_fx4,
         fmul_den2nor_m2_predict_fx4,
         fdiv_fdtos_den2nor_sp_fx4,
         fdiv_den2nor_dp_fx4,
         aboe_fx4,
         fpint_nxc_fx4,
         fac_rng_wr_gsr_3f}),
  .dout({fpc_int_sel_fx5[3:0],
         fpc_vis_cmp_result_fx5[3:0],
             int_res_sel_fx5_b2,
             ma_fmt_sel_fx5_b0,
         idiv0_trap_fx5,
         mulscc_iccn_fx5,
         mulscc_iccz_fx5,
         mulscc_iccv_fx5,
         mulscc_iccc_fx5,
         mulscc_xccz_fx5,
         idiv_xccz_fx5, idiv_iccz_fx5,
         idiv_iccv_fx5,
         fpc_exp_sel_mul_fx5,
         sign_inter_fx5,
         sign_zero_fx5,
             ma_sum_fx5_b10,
         fpc_fsr_w1_vld_fx5[1:0],
             fgx_instr_fx5,
         w1_odd32b_fx5,
             ma_cout_fx5,
         fadd_logical_sub_fx5,
         fsr_store_fx5,
         fmul_den2nor_m2_predict_fx5,
         fdiv_fdtos_den2nor_sp_fx5,
         fdiv_den2nor_dp_fx5,
         aboe_fx5,
         fpint_nxc_fx5,
         rng_wr_gsr_4f}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_5 fx5_04  (
  .scan_in(fx5_04_scanin),
  .scan_out(fx5_04_scanout),
  .l1clk(l1clk_pm1),
  .din (fsr_tem_fx4[4:0]),
  .dout(fsr_tem_fx5[4:0]),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_4 fx5_05  (
  .scan_in(fx5_05_scanin),
  .scan_out(fx5_05_scanout),
  .l1clk(l1clk_pm1),
  .din ({rm_near_dp_fx4, rm_near_sp_fx4, rm_directed_dp_fx4, rm_directed_sp_fx4}),
  .dout({rm_near_dp_fx5, rm_near_sp_fx5, rm_directed_dp_fx5, rm_directed_sp_fx5}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_6 fx5_06  (
  .scan_in(fx5_06_scanin),
  .scan_out(fx5_06_scanout),
  .l1clk(l1clk_pm1),
  .din ({add_g_bit_sp_fx4,
         add_g_bit_dp_fx4,
         add_lsb_bit_sp_fx4,
         add_lsb_bit_dp_fx4,
         add_x_bit_sp_fx4,
         add_x_bit_dp_fx4}),
  .dout({add_g_bit_sp_fx5,
         add_g_bit_dp_fx5,
         add_lsb_bit_sp_fx5,
         add_lsb_bit_dp_fx5,
         add_x_bit_sp_fx5,
         add_x_bit_dp_fx5}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_4 fx5_07  (
  .scan_in(fx5_07_scanin),
  .scan_out(fx5_07_scanout),
  .l1clk(l1clk_pm1),
  .din ({inf_src_result_fx4,
         zero_src_result_fx4,
         nan_default_result_fx4,
         maxint_result_fx4}),
  .dout({inf_src_result_fx5,
         zero_src_result_fx5,
         nan_default_result_fx5,
         maxint_result_fx5}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_15 fx5_08  (
  .scan_in(fx5_08_scanin),
  .scan_out(fx5_08_scanout),
  .l1clk(l1clk_pm1),
  .din ({fadd_ovf_predict_fx4,
         fdtos_ovf_predict_fx4,
         fdtos_ovf_detect_fx4,
         fmul_ovf_predict_fx4,
         fmul_ovf_detect_fx4,
         fdiv_ovf_detect_fx4,
         fdtos_unf_predict_fx4,
         fdtos_unf_detect_fx4,
         fmul_unf_predict_fx4,
         fmul_unf_detect_fx4,
         fdiv_unf_detect_fx4,
         fdtos_guf_detect_fx4,
         fmul_guf_detect_fx4,
         fdiv_guf_detect_fx4,
         unfin_src_fx4}),
  .dout({fadd_ovf_predict_fx5,
         fdtos_ovf_predict_fx5,
         fdtos_ovf_detect_fx5,
         fmul_ovf_predict_fx5,
         fmul_ovf_detect_fx5,
         fdiv_ovf_detect_fx5,
         fdtos_unf_predict_fx5,
         fdtos_unf_detect_fx5,
         fmul_unf_predict_fx5,
         fmul_unf_detect_fx5,
         fdiv_unf_detect_fx5,
         fdtos_guf_detect_fx5,
         fmul_guf_detect_fx5,
         fdiv_guf_detect_fx5,
         unfin_src_fx5}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_8 fx5_09  (
  .scan_in(fx5_09_scanin),
  .scan_out(fx5_09_scanout),
  .l1clk(l1clk_pm1),
  .din ({fpx_unfin_vld_fx4,
         ns_mode_fx4,
         fpx_of_vld_fx4,
         fpx_uf_vld_fx4,
         fpx_nx_vld_fx4,
         ecc_trap_fx4,
         fpx_dzc_fx4,
         fpx_nvc_fx4}),
  .dout({fpx_unfin_vld_fx5,
         ns_mode_fx5,
         fpx_of_vld_fx5,
         fpx_uf_vld_fx5,
         fpx_nx_vld_fx5,
         ecc_trap_fx5,
         fpx_dzc_fx5,
         fpx_nvc_fx5}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fpc_stfsr_en_fx3to5 =
  fsr_store_fx3 | i_fsr_w1_vld_fx4[1] | fpc_fsr_w1_vld_fx5[1];

// ------------------------------------
// Determine if zero result
// - exponent related detection won't apply to fmul/fdiv/fsqrt
//   because eadj is forced to zero
// ------------------------------------

assign  dp_zero_mant_fx5 =
    ( dtype_fx5[2:0]         == 3'b001) &     // DP
    ( fic_norm_eadj_fx5[5:4] == 2'b11 ) &
    ( fic_norm_eadj_fx5[2]            ) &
    ( fic_norm_eadj_fx5[0]            ) &     // massive norm shift, mant bits C,63:11 are 0
    (~ma_sum_fx5_b10                  ) &     // mantissa bit 10 is zero (G)
    (~nan_default_result_fx5          ) &     // avoid improper inf-inf=0
    (~inf_src_result_fx5              ) ;     // avoid improper max-inf=0

assign  sp_zero_mant_fx5 =
    ( dtype_fx5[2:0]         == 3'b000) &     // SP
    ( fic_norm_eadj_fx5[5:0] >  6'd24 ) &     // massive norm shift, mant bits C,63:40,G are 0
    (~nan_default_result_fx5          ) &     // avoid improper inf-inf=0
    (~inf_src_result_fx5              ) ;     // avoid improper max-inf=0

assign  zero_mant_fx5 =
  zero_src_result_fx5 | dp_zero_mant_fx5 | sp_zero_mant_fx5;

// ------------------------------------
// floating point result sign
// ------------------------------------

assign  fpc_sign_fx5 =
  (~zero_mant_fx5 & sign_inter_fx5) |
  ( zero_mant_fx5 & sign_zero_fx5 ) ;

// ------------------------------------
// Exponent overflow prediction & detection
// - does not include Rcout qualification
// ------------------------------------

assign  ovf_detect_inf_fx5 =
  ((fadd_ovf_predict_fx5 & ma_cout_fx5           ) |
   (fmul_ovf_predict_fx5 & fgu_mul_result_fx5[63]) |
   fdtos_ovf_detect_fx5 | fmul_ovf_detect_fx5 | fdiv_ovf_detect_fx5) &
  (  (rd_mode_fx5[1:0] == 2'b00)                    |    // nearest
    ((rd_mode_fx5[1:0] == 2'b10) & ~sign_inter_fx5) |    // +inf
    ((rd_mode_fx5[1:0] == 2'b11) &  sign_inter_fx5)  );  // -inf

assign  ovf_predict_inf_fx5 =
  (fadd_ovf_predict_fx5 | fdtos_ovf_predict_fx5 | fmul_ovf_predict_fx5) &
  (  (rd_mode_fx5[1:0] == 2'b00)                    |    // nearest
    ((rd_mode_fx5[1:0] == 2'b10) & ~sign_inter_fx5) |    // +inf
    ((rd_mode_fx5[1:0] == 2'b11) &  sign_inter_fx5)  );  // -inf

assign  ovf_detect_max_fx5 =
  ((fadd_ovf_predict_fx5 & ma_cout_fx5       ) |
   (fmul_ovf_predict_fx5 & fgu_mul_result_fx5[63]) |
   fdtos_ovf_detect_fx5 | fmul_ovf_detect_fx5 | fdiv_ovf_detect_fx5) &
  (  (rd_mode_fx5[1:0] == 2'b01)                    |    // trunc
    ((rd_mode_fx5[1:0] == 2'b10) &  sign_inter_fx5) |    // +inf
    ((rd_mode_fx5[1:0] == 2'b11) & ~sign_inter_fx5)  );  // -inf

assign  ovf_predict_max_fx5 =
  (fadd_ovf_predict_fx5 | fdtos_ovf_predict_fx5 | fmul_ovf_predict_fx5) &
  (  (rd_mode_fx5[1:0] == 2'b01)                    |    // trunc
    ((rd_mode_fx5[1:0] == 2'b10) &  sign_inter_fx5) |    // +inf
    ((rd_mode_fx5[1:0] == 2'b11) & ~sign_inter_fx5)  );  // -inf

assign  unf_detect_fx5 =
  fdtos_unf_detect_fx5  |
  fmul_unf_detect_fx5   | fdiv_unf_detect_fx5  |
  fdtos_guf_detect_fx5  | fmul_guf_detect_fx5  |
  fdiv_guf_detect_fx5;

assign  unf_predict_fx5 =
  fdtos_unf_predict_fx5 |
  (fmul_unf_predict_fx5        & ~fgu_mul_result_fx5[63]) |  // FMUL Eint=Emin-1
  (fmul_den2nor_m2_predict_fx5                          ) ;  // FMUL Eint=Emin-2

assign  unfin_early_fx5 =

  unfin_src_fx5 |

  (fmul_unf_predict_fx5        & ~fgu_mul_result_fx5[63] & ~fpc_rinc_sel_fx5    ) |  // fmul
  (fmul_unf_detect_fx5         & ~fmul_guf_detect_fx5                                // fmul
                               & ~fmul_den2nor_m2_predict_fx5                   ) |
  (fmul_den2nor_m2_predict_fx5                           & ~fpc_rinc_sel_fx5    ) |  // fmul

  ((fdtos_unf_predict_fx5 | fdtos_unf_detect_fx5) &                               // fdtos
   ~fdtos_guf_detect_fx5 &
   ~fdiv_fdtos_den2nor_sp_fx5                                                ) |

  (fdiv_unf_detect_fx5   &                                                        // fdiv
   ~fdiv_guf_detect_fx5  &
   ~fdiv_fdtos_den2nor_sp_fx5 &
   ~fdiv_den2nor_dp_fx5                                                      ) |

  (~(dp_zero_mant_fx5 | sp_zero_mant_fx5) &
   ((~fpe_einty_adj_cout_fx5 &                     fadd_logical_sub_fx5  ) |      // fadd/fsub eadj unf
    ( fpe_einty_eq_eadj_fx5  & ~fpc_rinc_sel_fx5 & fadd_logical_sub_fx5  )  )) ;  // fadd/fsub eadj unf

assign  fpd_unfin_fx5 =  // if (Eint=Emin & 0.1X intermediate result & 1.XX rounded result & fdiv) then override fpd_unfin
  div_eint_fx4[12]       &                           // unf_predict   (Eint=Emin)
  fdc_dec_exp_early      &                           // decrement exp (0.1X intermediate result)
  ~fdd_pte_cla_early_b63 &                           //              ~(1.XX rounded      result)
  (fdc_finish_fltd_early | fdc_finish_flts_early) &  // FDIV  finished
  ~div_eint_fx4[15]      ;                           // ~ns_mode

// ------------------------------------
// Detect if denorm fdiv intermediate
// result rounds to norm
// ------------------------------------

assign  fdiv_den2nor_m0_fx5 =
  div_eint_fx4[12]       &                           // unf_predict   (Eint=Emin)
  fdc_dec_exp_early      &                           // decrement exp (0.1X intermediate result)
  fdd_pte_cla_early_b63  &                           //               (1.XX rounded      result)
  (fdc_finish_fltd_early | fdc_finish_flts_early);   // FDIV  finished

// ------------------------------------
// floating point exception fields {cexc}
// ------------------------------------

assign  i_fpx_ofc_fx5 = ovf_detect_inf_fx5 | ovf_detect_max_fx5;

assign  i_fpx_ufc_fx5 =
   unf_detect_fx5  |
   unf_predict_fx5 |                                      // ufc is detected before round
   (~(dp_zero_mant_fx5 | sp_zero_mant_fx5) &
    (eadj_unf_if_norcout_fx5 |                            // fadd/fsub eadj unf detected before round
     (~fpe_einty_adj_cout_fx5 & fadd_logical_sub_fx5)));  // fadd/fsub eadj unf

// ------------------------------------
// Integer/Float_Constant mux selects
// ------------------------------------

assign  fpc_fconst_sel_fx5[0] =				// SP inf
  (inf_src_result_fx5 |
   ovf_detect_inf_fx5 |
   ovf_predict_inf_fx5 ) & (dtype_fx5[2:0] == 3'b000);

assign  fpc_fconst_sel_fx5[1] =                         // DP inf
  (inf_src_result_fx5 |
   ovf_detect_inf_fx5 |
   ovf_predict_inf_fx5 ) & (dtype_fx5[2:0] == 3'b001);

assign  fpc_fconst_sel_fx5[2] =                         // SP max
  (ovf_detect_max_fx5 |
   ovf_predict_max_fx5 ) & (dtype_fx5[2:0] == 3'b000);

assign  fpc_fconst_sel_fx5[3] =                         // DP max
  (ovf_detect_max_fx5 |
   ovf_predict_max_fx5 ) & (dtype_fx5[2:0] == 3'b001);

assign  fpc_fconst_sel_fx5[4] =                         // SP/DP zero
  zero_mant_fx5 | unf_detect_fx5 | unf_predict_fx5 |
  (fadd_logical_sub_fx5 & ~fpc_int_sel_fx5[2]);  // choose zero fconst in case
                                                 // of eadj unf, unless default NaN

// ------------------------------------
// Final result mux selects
// ------------------------------------

assign  fpc_result_sel_fx5[0] = fgx_instr_fx5 & w1_odd32b_fx5;
assign  fpc_result_sel_fx5[1] = fgx_instr_fx5;

// Note: fpc_result_sel_fx5[2] must still be conditioned during fb stage as follows:
//       i_result_sel_fb[2] | (rcout_fb & ovf_if_rcout_fb & w1_odd32b_fb);
assign  fpc_result_sel_fx5[2] =
  ((dtype_fx5[2:1] == 2'b01 ) & w1_odd32b_fx5) |         // odd 32b int/const (non-float) result
  ( inf_src_result_fx5        & w1_odd32b_fx5) |         // odd SP inf  result
  ( nan_default_result_fx5    & w1_odd32b_fx5) |         // odd SP nan  result
  ( zero_mant_fx5             & w1_odd32b_fx5) |         // odd SP zero result
  ( maxint_result_fx5         & w1_odd32b_fx5) |         // odd maxint  result
  ( ovf_detect_inf_fx5        & w1_odd32b_fx5) |         // odd SP inf  result
  ( ovf_detect_max_fx5        & w1_odd32b_fx5) |         // odd SP max  result
  ( unf_detect_fx5            & w1_odd32b_fx5) |         // odd SP zero result
  ( unf_predict_fx5           & w1_odd32b_fx5) |         // odd SP min  result (or unfin/dont_care)
  ( eadj_unf_if_norcout_fx5   & w1_odd32b_fx5) |         // odd SP min  result (or unfin/dont_care)
  (~fpe_einty_adj_cout_fx5 &
    fadd_logical_sub_fx5      & w1_odd32b_fx5) |         // odd SP zero result (eadj unf)
  ( fpe_einty_eq_eadj_fx5  &
   ~fpc_rinc_sel_fx5       &
    fadd_logical_sub_fx5      & w1_odd32b_fx5) ;         // odd SP zero result (eadj unf)

assign  fpc_result_sel_fx5[3] =
   (dtype_fx5[2:0] == 3'b000) & w1_odd32b_fx5;           // odd SP result

// Note: fpc_result_sel_fx5[4] must still be conditioned during fb stage as follows:
//       i_result_sel_fb[4] | (rcout_fb & ovf_if_rcout_fb);
assign  fpc_result_sel_fx5[4] =
  ((dtype_fx5[2:1] == 2'b01) |
   (dtype_fx5[2:1] == 2'b10)                 ) |         // 32b or 64b int/const (non-float) result
  ( inf_src_result_fx5                       ) |         // SP/DP  inf  result
  ( nan_default_result_fx5                   ) |         // SP/DP  nan  result
  ( zero_mant_fx5                            ) |         // SP/DP  zero result
  ( maxint_result_fx5                        ) |         // maxint      result
  ( ovf_detect_inf_fx5                       ) |         // SP/DP  inf  result
  ( ovf_detect_max_fx5                       ) |         // SP/DP  max  result
  ( unf_detect_fx5                           ) |         // SP/DP  zero result
  ( unf_predict_fx5                          ) |         // SP/DP  min  result (or unfin/dont_care)
  ( eadj_unf_if_norcout_fx5                  ) |         // SP/DP  min  result (or unfin/dont_care)
  (~fpe_einty_adj_cout_fx5 &
    fadd_logical_sub_fx5                     ) |         // SP/DP  zero result (eadj unf)
  ( fpe_einty_eq_eadj_fx5  &
   ~fpc_rinc_sel_fx5       &
    fadd_logical_sub_fx5                     ) ;         // SP/DP  zero result (eadj unf)

assign  fpc_result_sel_fx5[5] = (dtype_fx5[2:0] == 3'b001);  // DP

// ------------------------------------
// Mul pipe Rinc calculation
// - FMUL(s,d), FsMULd
// - Determine if LSB should be inc due to round
//
// Rounding equations:
//
// Rinc = 
//   (near &  G    & (LSB | X)) |
//   (+inf & ~sign & (G   | X)) |
//   (-inf &  sign & (G   | X)) ;
//
// directed = 
//   (+inf & ~sign) |
//   (-inf &  sign) ;
//
// Rinc =  // nand3-nand4 delay
//   (near     & G & LSB) |
//   (near     & G & X  ) |
//   (directed & G      ) |
//   (directed     & X  ) ;
//
// ------------------------------------

assign  mul_fmt_1xx_fx5 = 
   (fgu_mul_result_fx5[63] |    // 1X.XX
    fmul_unf_predict_fx5) &     // 01.XX, Eint=Emin-1, denorm inter. result may rnd to norm
   (itype_fx5[2:0] == 3'b101);  // mul

assign  mul_fmt_01x_fx5 =       // 01.XX
  ~fgu_mul_result_fx5[63] &
  ~fmul_unf_predict_fx5   &
   (itype_fx5[2:0] == 3'b101);  // mul

assign  mul_fmt_m2_fx5 =        // 11.XX, Eint=Emin-2, denorm inter. result may rnd to norm
   fmul_den2nor_m2_predict_fx5;

assign  mul_lsb_bit_dp_fx5 =
  (mul_fmt_m2_fx5  &   fgu_mul_result_fx5[12]   ) |  //          Eint=Emin-2
  (mul_fmt_1xx_fx5 &   fgu_mul_result_fx5[11]   ) |  // 1X.XX or Eint=Emin-1
  (mul_fmt_01x_fx5 &   fgu_mul_result_fx5[10]   ) ;  // 01.XX

assign  mul_g_bit_dp_fx5 =
  (mul_fmt_m2_fx5  &   fgu_mul_result_fx5[11]   ) |  //          Eint=Emin-2
  (mul_fmt_1xx_fx5 &   fgu_mul_result_fx5[10]   ) |  // 1X.XX or Eint=Emin-1
  (mul_fmt_01x_fx5 &   fgu_mul_result_fx5[9]   ) ;  // 01.XX

assign  mul_x_bit_dp_fx5 =
  (mul_fmt_m2_fx5  & ( fgu_mul_result_fx5[10] |      //          Eint=Emin-2
                       fgu_mul_result_fx5[9] |
                       fpy_sticky_dp_fx5   )) |
  (mul_fmt_1xx_fx5 & ( fgu_mul_result_fx5[9] |      // 1X.XX or Eint=Emin-1
                       fpy_sticky_dp_fx5   )) |
  (mul_fmt_01x_fx5 & ( fpy_sticky_dp_fx5   )) ;      // 01.XX

assign  mul_lsb_bit_sp_fx5 =
  (mul_fmt_m2_fx5  &   fgu_mul_result_fx5[41]   ) |  //          Eint=Emin-2
  (mul_fmt_1xx_fx5 &   fgu_mul_result_fx5[40]   ) |  // 1X.XX or Eint=Emin-1
  (mul_fmt_01x_fx5 &   fgu_mul_result_fx5[39]   ) ;  // 01.XX

assign  mul_g_bit_sp_fx5 =
  (mul_fmt_m2_fx5  &   fgu_mul_result_fx5[40]   ) |  //          Eint=Emin-2
  (mul_fmt_1xx_fx5 &   fgu_mul_result_fx5[39]   ) |  // 1X.XX or Eint=Emin-1
  (mul_fmt_01x_fx5 &   fgu_mul_result_fx5[38]   ) ;  // 01.XX

assign  mul_x_bit_sp_fx5 =
  (mul_fmt_m2_fx5  & ( fgu_mul_result_fx5[39] |      //          Eint=Emin-2
                       fgu_mul_result_fx5[38] |
                       fpy_sticky_sp_fx5   )) |
  (mul_fmt_1xx_fx5 & ( fgu_mul_result_fx5[38] |      // 1X.XX or Eint=Emin-1
                       fpy_sticky_sp_fx5   )) |
  (mul_fmt_01x_fx5 & ( fpy_sticky_sp_fx5   )) ;      // 01.XX

assign  mul_rinc_dp_fx5 =
  (rm_near_dp_fx5     & mul_g_bit_dp_fx5 & mul_lsb_bit_dp_fx5) |
  (rm_near_dp_fx5     & mul_g_bit_dp_fx5 &   mul_x_bit_dp_fx5) |
  (rm_directed_dp_fx5 & mul_g_bit_dp_fx5                     ) |
  (rm_directed_dp_fx5                    &   mul_x_bit_dp_fx5) ;

assign  mul_rinc_sp_fx5 =
  (rm_near_sp_fx5     & mul_g_bit_sp_fx5 & mul_lsb_bit_sp_fx5) |
  (rm_near_sp_fx5     & mul_g_bit_sp_fx5 &   mul_x_bit_sp_fx5) |
  (rm_directed_sp_fx5 & mul_g_bit_sp_fx5                     ) |
  (rm_directed_sp_fx5                    &   mul_x_bit_sp_fx5) ;

assign  mul_rinc_sel_fx5   = mul_rinc_dp_fx5  | mul_rinc_sp_fx5;

// ------------------------------------
// Add pipe Rinc calculation
// - FADD(s,d), FSUB(s,d), FiTOs, FxTO(s,d), FdTOs
// - Determine if LSB should be inc due to round
//
// Rounding equations:
//
// Rinc = 
//   (near &  G    & (LSB | X)) |
//   (+inf & ~sign & (G   | X)) |
//   (-inf &  sign & (G   | X)) ;
//
// directed = 
//   (+inf & ~sign) |
//   (-inf &  sign) ;
//
// Rinc =  // nand3-nand4 delay
//   (near     & G & LSB) |
//   (near     & G & X  ) |
//   (directed & G      ) |
//   (directed     & X  ) ;
//
// ------------------------------------

assign  add_rinc_dp_fx5 =
  (rm_near_dp_fx5     & add_g_bit_dp_fx5 & add_lsb_bit_dp_fx5) |
  (rm_near_dp_fx5     & add_g_bit_dp_fx5 &   add_x_bit_dp_fx5) |
  (rm_directed_dp_fx5 & add_g_bit_dp_fx5                     ) |
  (rm_directed_dp_fx5                    &   add_x_bit_dp_fx5) ;

assign  add_rinc_sp_fx5 =
  (rm_near_sp_fx5     & add_g_bit_sp_fx5 & add_lsb_bit_sp_fx5) |
  (rm_near_sp_fx5     & add_g_bit_sp_fx5 &   add_x_bit_sp_fx5) |
  (rm_directed_sp_fx5 & add_g_bit_sp_fx5                     ) |
  (rm_directed_sp_fx5                    &   add_x_bit_sp_fx5) ;

assign  add_rinc_sel_fx5 = add_rinc_dp_fx5 | add_rinc_sp_fx5;

assign  fpc_rinc_sel_fx5 = add_rinc_sel_fx5 | mul_rinc_sel_fx5;

assign  fpc_q_rinc_sel_fx5 =
  mul_rinc_sel_fx5 |
  (add_rinc_sel_fx5 & ~ma_fmt_sel_fx5_b0);  // ~logical_sub 00.1X

assign  ovf_if_rcout_fx5 =
  fpc_rinc_sel_fx5 &
  (fadd_ovf_predict_fx5  |
   fdtos_ovf_predict_fx5 |
   fmul_ovf_predict_fx5   );

assign  fpc_ovf_if_rcout_fx5[1] = ovf_if_rcout_fx5;
assign  fpc_ovf_if_rcout_fx5[0] = ovf_if_rcout_fx5 & w1_odd32b_fx5;

assign  fmul_unf_if_nocorl_fx5 =  // No C or L, where C=Rcout, L=implied_bit
  (fmul_unf_predict_fx5 & ~fgu_mul_result_fx5[63]) | fmul_den2nor_m2_predict_fx5;

assign  fmul_unf_if_nocorl_sp_fx5 =
  fmul_unf_if_nocorl_fx5 & ~dtype_fx5[0] & fpc_rinc_sel_fx5;

assign  fmul_unf_if_nocorl_dp_fx5 =
  fmul_unf_if_nocorl_fx5 &  dtype_fx5[0] & fpc_rinc_sel_fx5;

assign  eadj_unf_if_norcout_fx5 =
  fpe_einty_eq_eadj_fx5 & fadd_logical_sub_fx5;

// ------------------------------------
// Inexact result calculation
// - inexact = G | (R | X)
// - must force inexact to zero if nan, otherwise
//   a propagating nan may signal inexact
// - must force inexact to zero if inf source, otherwise
//   inexact may by improperly signaled
// - unfin_src will set inexact flag if ~unfinished_FPop, independent of ns_mode
// ------------------------------------

assign  i_fpx_nxc_fx5 =

  fpx_nx_vld_fx5 &
  ~(aboe_fx5 & ~(itype_fx5[2:0] == 3'b011)) &  // sources aren't ones exp (inf or nan) if ~intfp

  (((dtype_fx5[2:0] == 3'b000) &  // sp
    (add_g_bit_sp_fx5 | add_x_bit_sp_fx5 | mul_g_bit_sp_fx5 | mul_x_bit_sp_fx5)) |
   ((dtype_fx5[2:0] == 3'b001) &  // dp
    (add_g_bit_dp_fx5 | add_x_bit_dp_fx5 | mul_g_bit_dp_fx5 | mul_x_bit_dp_fx5)) |

   fdtos_guf_detect_fx5 | fmul_guf_detect_fx5 | fdiv_guf_detect_fx5 |
   unfin_src_fx5 |
   fpint_nxc_fx5);

// ------------------------------------
// icc/xcc final result mux
// ------------------------------------

assign  fgu_exu_icc_fx5[3:0] =  // icc cond code {N,Z,V,C}
  ({4{ div_finish_int_fb}}  & {fdd_result[31],          // idiv   icc.n
                               idiv_iccz_fx5,           // idiv   icc.z
                               idiv_iccv_fx5,           // idiv   icc.v
                               1'b0               }) |  // idiv   icc.c
  ({4{~div_finish_int_fb &
       int_res_sel_fx5_b2}} & {mulscc_iccn_fx5,         // mulscc icc.n
                               mulscc_iccz_fx5,         // mulscc icc.z
                               mulscc_iccv_fx5,         // mulscc icc.v
                               mulscc_iccc_fx5    }) |  // mulscc icc.c
  ({4{~div_finish_int_fb &
      ~int_res_sel_fx5_b2}} & {fgu_mul_result_fx5[31],  // imul   icc.n
                               fpy_xicc_z_fx5[0],       // imul   icc.z
                               1'b0,                    // imul   icc.v
                               1'b0               }) ;  // imul   icc.c

assign  fgu_exu_xcc_fx5[1:0] =                          // xcc cond code {N,Z}
  ({2{ div_finish_int_fb}}  & {fdd_result[63],          // idiv   xcc.n
                               idiv_xccz_fx5      }) |  // idiv   xcc.z
  ({2{~div_finish_int_fb &
       int_res_sel_fx5_b2}} & {1'b0,                    // mulscc xcc.n
                               mulscc_xccz_fx5    }) |  // mulscc xcc.z
  ({2{~div_finish_int_fb &
      ~int_res_sel_fx5_b2}} & {fgu_mul_result_fx5[63],  // imul   xcc.n
                               fpy_xicc_z_fx5[1]  }) ;  // imul   xcc.z


// ----------------------------------------------------------------------------
//                               FB stage 
// ----------------------------------------------------------------------------

fgu_fpc_ctl_msff_ctl_macro__width_16 fb_00  (
  .scan_in(fb_00_scanin),
  .scan_out(fb_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({fcc_fx5[1:0],
         idiv0_trap_fx5,
         ovf_if_rcout_fx5,
         fmul_unf_if_nocorl_sp_fx5,
         fmul_unf_if_nocorl_dp_fx5,
         fmul_unf_if_nocorl_fx5,
         eadj_unf_if_norcout_fx5,
         fpf_implied_bit_fx5,
         fsr_store_fx5,
         fac_dec_valid_noflush_fx5,
         sp_zero_mant_fx5,
         dp_zero_mant_fx5,
         fdc_finish_fltd_early,
         fdc_finish_flts_early,
         fdc_finish_int_early}),
  .dout({fcc_fb[1:0],
         idiv0_trap_fb,
         ovf_if_rcout_fb,
         fmul_unf_if_nocorl_sp_fb,
         fmul_unf_if_nocorl_dp_fb,
         fmul_unf_if_nocorl_fb,
         eadj_unf_if_norcout_fb,
         implied_bit_fb,
         fsr_store_fb,
             dec_valid_noflush_fb,
         sp_zero_mant_fb,
         dp_zero_mant_fb,
         div_finish_fltd_fb,
         div_finish_flts_fb,
         div_finish_int_fb}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_3 fb_01  (
  .scan_in(fb_01_scanin),
  .scan_out(fb_01_scanout),
  .l1clk(l1clk_pm1),
  .din ({  w1_vld_fx5[1:0], fpc_sign_fx5}),
  .dout({i_w1_vld_fb[1:0],  fpc_sign_fb }),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_16 fb_03  (
  .scan_in(fb_03_scanin),
  .scan_out(fb_03_scanout),
  .l1clk(l1clk_pm1),
  .din ({fpx_unfin_vld_fx5,
         ns_mode_fx5,
         unfin_early_fx5,
         fpd_unfin_fx5,
         fpx_of_vld_fx5,
         fpx_uf_vld_fx5,
         ecc_trap_fx5,
         fpx_dzc_fx5,
         fpx_nvc_fx5,
         i_fpx_ofc_fx5,
         i_fpx_ufc_fx5,
         i_fpx_nxc_fx5,
         fdiv_fdtos_den2nor_sp_fx5,
         fdiv_den2nor_dp_fx5,
         fdiv_den2nor_m0_fx5,
         fdc_dec_exp_early}),
  .dout({fpx_unfin_vld_fb,
         ns_mode_fb,
         unfin_early_fb,
         fpc_fpd_unfin_fb,
         fpx_of_vld_fb,
         fpx_uf_vld_fb,
         ecc_trap_fb,
         fpx_dzc_fb,
         fpx_nvc_fb,
         i_fpx_ofc_fb,
         i_fpx_ufc_fb,
         i_fpx_nxc_fb,
         fdiv_fdtos_den2nor_sp_fb,
         fdiv_den2nor_dp_fb,
         fdiv_den2nor_m0_fb,
         div_dec_exp_fb}),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_5 fb_04  (
  .scan_in(fb_04_scanin),
  .scan_out(fb_04_scanout),
  .l1clk(l1clk_pm1),
  .din (fsr_tem_fx5[4:0]),
  .dout(fsr_tem_fb[4:0]),
  .siclk(siclk),
  .soclk(soclk)
  );

fgu_fpc_ctl_msff_ctl_macro__width_13 fb_05  (
  .scan_in(fb_05_scanin),
  .scan_out(fb_05_scanout),
  .l1clk(l1clk_pm1),
  .din ({    fpd_exp_res[10:1],       fpd_exp_res[0],     fpd_const_sel[1:0]}),
  .dout({fpc_fpd_exp_res[10:1], i_fpc_fpd_exp_res_b0, fpc_fpd_const_sel[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );

assign  fpc_fpd_exp_res[0] = i_fpc_fpd_exp_res_b0 | fdiv_den2nor_m0_fb;

assign  fpc_den2nor_sp_fb =     //     32b min result
  fdiv_fdtos_den2nor_sp_fb |
  ((fpf_rcout_fb | implied_bit_fb) & fmul_unf_if_nocorl_sp_fb);

assign  fpc_den2nor_dp_fb =     // 64b     min result
  fdiv_den2nor_dp_fb       |
  ((fpf_rcout_fb | implied_bit_fb) & fmul_unf_if_nocorl_dp_fb);

// ------------------------------------
// Determine if unfinished_FPop trap
// ------------------------------------

assign  fpc_fpx_unfin_fb =
  ~ecc_trap_fb          &
   dec_valid_noflush_fb &
   fpx_unfin_vld_fb     &
  ~ns_mode_fb           &
  (unfin_early_fb |
   (~fpf_rcout_fb & ~implied_bit_fb & fmul_unf_if_nocorl_fb) |    // fmul
   (~fpf_rcout_fb & eadj_unf_if_norcout_fb &                      // fadd/fsub eadj unf
    ~(dp_zero_mant_fb | sp_zero_mant_fb))                 );

// ------------------------------------
// floating point exception fields {ftt,aexc,cexc}
// - must clear FSR.ofc (FSR.ufc) if overflow (underflow) exception traps
//   and FSR.OFM (FSR.UFM) is not set and FSR.NXM is set
// - must clear FSR.nxc if overflow (underflow) exception does trap
//   because FSR.OFM (FSR.UFM) is set, regardless of whether FSR.NXM is set
// ------------------------------------

assign  fpd_fsr_ofm_fb = div_eint_fx4[18];
assign  fpd_fsr_ufm_fb = div_eint_fx4[17];
assign  fpd_fsr_nxm_fb = div_eint_fx4[16];

assign  fpx_ofc_fb =
  ~(~fsr_tem_fb[3] & fsr_tem_fb[0])   &  // disabled of and enabled nx
  fpx_of_vld_fb &
  (i_fpx_ofc_fb | (fpf_rcout_fb & ovf_if_rcout_fb));

assign  fpx_ufc_fb =
  ~(~fsr_tem_fb[2] & fsr_tem_fb[0])   &  // disabled uf and enabled nx
  fpx_uf_vld_fb &
  ~fpc_fpx_unfin_fb &
  i_fpx_ufc_fb;

assign  fpx_nxc_fb =
  ~((fpx_ofc_fb & fsr_tem_fb[3]) | (fpx_ufc_fb & fsr_tem_fb[2])) &    // enabled of or enabled uf
  ((~fpc_fpx_unfin_fb & i_fpx_nxc_fb)              |    // inexact
   (fpx_of_vld_fb &                                     // of
    (i_fpx_ofc_fb | (fpf_rcout_fb & ovf_if_rcout_fb))) |
   (fpx_uf_vld_fb &                                     // uf
    ~fpc_fpx_unfin_fb &
    i_fpx_ufc_fb)                                   );

assign  fpd_ofc_fb =  // fdiv_ovf_predict => detect
  ~(~fpd_fsr_ofm_fb & fpd_fsr_nxm_fb) &  // disabled of and enabled nx
  ((|div_eint_fx4[14:13] & ~div_dec_exp_fb) & (div_finish_fltd_fb | div_finish_flts_fb));

assign  fpd_ufc_fb =  // fdiv_unf_predict => detect
  ~(~fpd_fsr_ufm_fb & fpd_fsr_nxm_fb) &  // disabled of and enabled nx
  ~fpc_fpd_unfin_fb &
  ((  div_eint_fx4[12]    &  div_dec_exp_fb) & (div_finish_fltd_fb | div_finish_flts_fb));

assign  fpd_nxc_fb =
  ~((fpd_ofc_fb & fpd_fsr_ofm_fb) | (fpd_ufc_fb & fpd_fsr_ufm_fb)) &  // enabled of or enabled uf
  ~fpc_fpd_unfin_fb &
  ((fdc_flt_inexact                          & (div_finish_fltd_fb | div_finish_flts_fb)) |    // inexact
   ((|div_eint_fx4[14:13] & ~div_dec_exp_fb) & (div_finish_fltd_fb | div_finish_flts_fb)) |    // of
   (( div_eint_fx4[12]    &  div_dec_exp_fb) & (div_finish_fltd_fb | div_finish_flts_fb))  );  // uf

assign  fpx_ieee_trap_fb =   // FPX enabled ieee 754 exception detected
  ~ecc_trap_fb         &
  dec_valid_noflush_fb &
  ((    fsr_tem_fb[4] & fpx_nvc_fb) |
   (    fsr_tem_fb[3] & fpx_ofc_fb) |
   (    fsr_tem_fb[2] & fpx_ufc_fb) |
   (    fsr_tem_fb[1] & fpx_dzc_fb) |
   (    fsr_tem_fb[0] & fpx_nxc_fb)  );

assign  fpc_fpd_ieee_trap_fb =   // FPD enabled ieee 754 exception detected
  ((fpd_fsr_ofm_fb    & fpd_ofc_fb) |
   (fpd_fsr_ufm_fb    & fpd_ufc_fb) |
   (fpd_fsr_nxm_fb    & fpd_nxc_fb)  );

// 0in bits_on -max 1 -var {    fpx_ieee_trap_fb, fpc_fpx_unfin_fb}
// 0in bits_on -max 1 -var {fpc_fpd_ieee_trap_fb, fpc_fpd_unfin_fb}

assign  fpx_ftt_fb[1:0] =
  ({2{    fpx_ieee_trap_fb}} & 2'd1) |  // IEEE_754_exception
  ({2{fpc_fpx_unfin_fb    }} & 2'd2) ;  // unfinished_FPop

assign  fpd_ftt_fb[1:0] =
  ({2{fpc_fpd_ieee_trap_fb}} & 2'd1) |  // IEEE_754_exception
  ({2{fpc_fpd_unfin_fb    }} & 2'd2) ;  // unfinished_FPop

assign  fpx_aexc_fb[4:0] =
  {(    ~fsr_tem_fb[4] & fpx_nvc_fb),    // nva
   (    ~fsr_tem_fb[3] & fpx_ofc_fb),    // ofa
   (    ~fsr_tem_fb[2] & fpx_ufc_fb),    // ufa
   (    ~fsr_tem_fb[1] & fpx_dzc_fb),    // dza
   (    ~fsr_tem_fb[0] & fpx_nxc_fb) };  // nxa

assign  fpd_aexc_fb[4:0] =
  {1'b0,                                 // nva
   (~fpd_fsr_ofm_fb    & fpd_ofc_fb),    // ofa
   (~fpd_fsr_ufm_fb    & fpd_ufc_fb),    // ufa
   1'b0,                                 // dza
   (~fpd_fsr_nxm_fb    & fpd_nxc_fb) };  // nxa

assign  fsr_w1_result_fb[11:0] =
  // ST(X)FSR clears ftt, {aexc,cexc} aren't written by ST(X)FSR because those enables are off
  {(fpx_ftt_fb[1:0] & {2{~fsr_store_fb}}),
   fpx_aexc_fb[4:0],
   fpx_nvc_fb,
   fpx_ofc_fb,
   fpx_ufc_fb,
   fpx_dzc_fb,
   fpx_nxc_fb};

assign  fsr_w2_result_fb[11:0] =
  {fpd_ftt_fb[1:0],
   fpd_aexc_fb[4:0],
   1'b0,         // fpd nvc always uses w1 port
   fpd_ofc_fb,
   fpd_ufc_fb,
   1'b0,         // fpd dzc always uses w1 port
   fpd_nxc_fb};

assign  fpc_w1_vld_fb[1:0] =
  {2{~mbist_run_1f     &
     ~fpx_ieee_trap_fb &
     ~fpc_fpx_unfin_fb  }} & i_w1_vld_fb[1:0];

// 0in custom -fire ((|fpc_w1_vld_fb[1:0]) & (fpx_ieee_trap_fb | fpc_fpx_unfin_fb)) -message "FRF written during FP trap"
// 0in custom -fire (($0in_delay((|fpc_fcc_vld_fx5[3:0]),1)) & (fpx_ieee_trap_fb | fpc_fpx_unfin_fb)) -message "FSR.fcc written during FP trap"

assign  fpc_w1_ul_vld_fb   = |fpc_w1_vld_fb[1:0];


// ----------------------------------------------------------------------------
//                               FW stage 
// ----------------------------------------------------------------------------

fgu_fpc_ctl_msff_ctl_macro__width_31 fw_00  (
  .scan_in(fw_00_scanin),
  .scan_out(fw_00_scanout),
  .l1clk(l1clk_pm1),
  .din ({    fpx_ieee_trap_fb,
         fpc_fpd_ieee_trap_fb,
         fpc_fpx_unfin_fb,
         fpc_fpd_unfin_fb,
                 idiv0_trap_fb,
             fcc_fb[1:0],
             fsr_w1_result_fb[11:0],
             fsr_w2_result_fb[11:0]}),
  .dout({fgu_fpx_ieee_trap_fw,
         fgu_fpd_ieee_trap_fw,
         fgu_fpx_unfin_fw,
         fgu_fpd_unfin_fw,
         fgu_fpd_idiv0_trap_fw,
         fpc_fcc_fw[1:0],
         fpc_fsr_w1_result_fw[11:0],
         fpc_fsr_w2_result_fw[11:0]}),
  .siclk(siclk),
  .soclk(soclk)
  );


supply0 vss;
supply1 vdd;
// fixscan start:
assign spares_scanin             = scan_in                  ;
assign e_00_scanin               = spares_scanout           ;
assign fx1_00_scanin             = e_00_scanout             ;
assign fx1_01_scanin             = fx1_00_scanout           ;
assign fx2_00_scanin             = fx1_01_scanout           ;
assign fx2_01_scanin             = fx2_00_scanout           ;
assign fx2_02_scanin             = fx2_01_scanout           ;
assign fx2_03_scanin             = fx2_02_scanout           ;
assign fx2_04_scanin             = fx2_03_scanout           ;
assign fx2_05_scanin             = fx2_04_scanout           ;
assign fx2_06_scanin             = fx2_05_scanout           ;
assign fx2_07_scanin             = fx2_06_scanout           ;
assign fx2_08_scanin             = fx2_07_scanout           ;
assign fx3_00_scanin             = fx2_08_scanout           ;
assign fx3_01_scanin             = fx3_00_scanout           ;
assign fx3_02_scanin             = fx3_01_scanout           ;
assign fx3_03_scanin             = fx3_02_scanout           ;
assign fx3_04_scanin             = fx3_03_scanout           ;
assign fx3_05_scanin             = fx3_04_scanout           ;
assign fx3_06_scanin             = fx3_05_scanout           ;
assign fx3_07_scanin             = fx3_06_scanout           ;
assign fx3_08_scanin             = fx3_07_scanout           ;
assign fx3_09_scanin             = fx3_08_scanout           ;
assign fx3_10_scanin             = fx3_09_scanout           ;
assign fx4_00_scanin             = fx3_10_scanout           ;
assign fx4_01_scanin             = fx4_00_scanout           ;
assign fx4_02_scanin             = fx4_01_scanout           ;
assign fx4_03_scanin             = fx4_02_scanout           ;
assign fx4_04_scanin             = fx4_03_scanout           ;
assign fx4_05_scanin             = fx4_04_scanout           ;
assign fx4_06_scanin             = fx4_05_scanout           ;
assign fx4_08_scanin             = fx4_06_scanout           ;
assign fx4_09_scanin             = fx4_08_scanout           ;
assign fx4_10_scanin             = fx4_09_scanout           ;
assign fx4_11_scanin             = fx4_10_scanout           ;
assign fx5_00_scanin             = fx4_11_scanout           ;
assign fx5_01_scanin             = fx5_00_scanout           ;
assign fx5_02_scanin             = fx5_01_scanout           ;
assign fx5_04_scanin             = fx5_02_scanout           ;
assign fx5_05_scanin             = fx5_04_scanout           ;
assign fx5_06_scanin             = fx5_05_scanout           ;
assign fx5_07_scanin             = fx5_06_scanout           ;
assign fx5_08_scanin             = fx5_07_scanout           ;
assign fx5_09_scanin             = fx5_08_scanout           ;
assign fb_00_scanin              = fx5_09_scanout           ;
assign fb_01_scanin              = fb_00_scanout            ;
assign fb_03_scanin              = fb_01_scanout            ;
assign fb_04_scanin              = fb_03_scanout            ;
assign fb_05_scanin              = fb_04_scanout            ;
assign fw_00_scanin              = fb_05_scanout            ;
assign scan_out                  = fw_00_scanout            ;

assign fx4_07_wmr_scanin         = wmr_scan_in              ;
assign wmr_scan_out              = fx4_07_wmr_scanout       ;
// fixscan end:
endmodule  // fgu_fpc_ctl


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module fgu_fpc_ctl_spare_ctl_macro__num_9 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire si_8;
wire so_8;
wire spare8_flop_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));

cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_8),
                               .so(so_8),
                               .d(1'b0),
                               .q(spare8_flop_unused));
assign si_8 = so_7;

cl_u1_buf_32x   spare8_buf_32x (.in(1'b1),
                                   .out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare8_nand3_8x_unused));
cl_u1_inv_8x    spare8_inv_8x (.in(1'b1),
                                  .out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_aoi22_4x_unused));
cl_u1_buf_8x    spare8_buf_8x (.in(1'b1),
                                  .out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_oai22_4x_unused));
cl_u1_inv_16x   spare8_inv_16x (.in(1'b1),
                                   .out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare8_nand2_8x_unused));
cl_u1_buf_16x   spare8_buf_16x (.in(1'b1),
                                   .out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare8_nor2_16x_unused));
cl_u1_inv_32x   spare8_inv_32x (.in(1'b1),
                                   .out(spare8_inv_32x_unused));
assign scan_out = so_8;


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_51 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [50:0] fdin;
wire [49:0] so;

  input [50:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [50:0] dout;
  output scan_out;
assign fdin[50:0] = din[50:0];


dff #(51)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[50:0]),
.si({scan_in,so[49:0]}),
.so({so[49:0],scan_out}),
.q(dout[50:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_17 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [16:0] fdin;
wire [15:0] so;

  input [16:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [16:0] dout;
  output scan_out;
assign fdin[16:0] = din[16:0];


dff #(17)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[16:0]),
.si({scan_in,so[15:0]}),
.so({so[15:0],scan_out}),
.q(dout[16:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_20 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [19:0] fdin;
wire [18:0] so;

  input [19:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [19:0] dout;
  output scan_out;
assign fdin[19:0] = din[19:0];


dff #(20)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[19:0]),
.si({scan_in,so[18:0]}),
.so({so[18:0],scan_out}),
.q(dout[19:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_15 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [14:0] fdin;
wire [13:0] so;

  input [14:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [14:0] dout;
  output scan_out;
assign fdin[14:0] = din[14:0];


dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[14:0]),
.si({scan_in,so[13:0]}),
.so({so[13:0],scan_out}),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_13 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [12:0] fdin;
wire [11:0] so;

  input [12:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [12:0] dout;
  output scan_out;
assign fdin[12:0] = din[12:0];


dff #(13)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[12:0]),
.si({scan_in,so[11:0]}),
.so({so[11:0],scan_out}),
.q(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_28 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [27:0] fdin;
wire [26:0] so;

  input [27:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [27:0] dout;
  output scan_out;
assign fdin[27:0] = din[27:0];


dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_18 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [17:0] fdin;
wire [16:0] so;

  input [17:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [17:0] dout;
  output scan_out;
assign fdin[17:0] = din[17:0];


dff #(18)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[17:0]),
.si({scan_in,so[16:0]}),
.so({so[16:0],scan_out}),
.q(dout[17:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_37 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [36:0] fdin;
wire [35:0] so;

  input [36:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [36:0] dout;
  output scan_out;
assign fdin[36:0] = din[36:0];


dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_38 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [37:0] fdin;
wire [36:0] so;

  input [37:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [37:0] dout;
  output scan_out;
assign fdin[37:0] = din[37:0];


dff #(38)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[37:0]),
.si({scan_in,so[36:0]}),
.so({so[36:0],scan_out}),
.q(dout[37:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_88 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [87:0] fdin;
wire [86:0] so;

  input [87:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [87:0] dout;
  output scan_out;
assign fdin[87:0] = din[87:0];


dff #(88)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[87:0]),
.si({scan_in,so[86:0]}),
.so({so[86:0],scan_out}),
.q(dout[87:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_11 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [10:0] fdin;
wire [9:0] so;

  input [10:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [10:0] dout;
  output scan_out;
assign fdin[10:0] = din[10:0];


dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_19 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [18:0] fdin;
wire [17:0] so;

  input [18:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [18:0] dout;
  output scan_out;
assign fdin[18:0] = din[18:0];


dff #(19)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[18:0]),
.si({scan_in,so[17:0]}),
.so({so[17:0],scan_out}),
.q(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_36 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [35:0] fdin;
wire [34:0] so;

  input [35:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [35:0] dout;
  output scan_out;
assign fdin[35:0] = din[35:0];


dff #(36)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[35:0]),
.si({scan_in,so[34:0]}),
.so({so[34:0],scan_out}),
.q(dout[35:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpc_ctl_msff_ctl_macro__width_31 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [30:0] fdin;
wire [29:0] so;

  input [30:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [30:0] dout;
  output scan_out;
assign fdin[30:0] = din[30:0];


dff #(31)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[30:0]),
.si({scan_in,so[29:0]}),
.so({so[29:0],scan_out}),
.q(dout[30:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fpe_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fpe_dp (
  fad_rs1_fx1, 
  fad_rs2_fx1, 
  fac_aexp_fmt_sel_e, 
  fac_bexp_fmt_sel_e, 
  fac_aux_cin_fx1, 
  main_clken, 
  fpc_exp_sel_mul_fx5, 
  fpc_eintx_sel_fx2, 
  fpc_eadjx_sel_fx2, 
  fpc_ma_fmt_sel_fx4, 
  fpc_rinc_sel_fx5, 
  fpc_q_rinc_sel_fx5, 
  fpe_aux_rs2_fmt_fx1_b0, 
  fpe_aux_eint_fx1, 
  fpe_rs1_fmt_fx1, 
  fpe_rs2_fmt_fx1, 
  fpe_einty_adj_cout_fx5, 
  fpe_einty_eq_eadj_fx5, 
  fgu_mul_result_fx5_b63, 
  fpf_rcout_fx5, 
  fpe_exp_res_fb, 
  fpe_align_sel_fx2, 
  fic_i2f_eadj_fx2, 
  fic_norm_eadj_fx5, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_scan_en, 
  scan_out);
wire stop;
wire test;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire fx1_fmtsel_scanin;
wire fx1_fmtsel_scanout;
wire [9:0] aexp_fmt_sel_fx1;
wire [7:0] bexp_fmt_sel_fx1;
wire tcu_muxtest_a_rep0;
wire tcu_muxtest_b_rep0;
wire [10:0] rs1_fmt_fx1_;
wire [10:0] rs2_fmt_fx1_;
wire amb_unused;
wire [10:0] ea_minus_eb_fx1;
wire ea_gteq_eb_fx1;
wire bma_unused;
wire [10:0] eb_minus_ea_fx1;
wire eb_gteq_ea_fx1;
wire fx2_swp_sel_scanin;
wire fx2_swp_sel_scanout;
wire [10:0] eintw_fx2;
wire rs1_fx1_b62_;
wire [10:0] rs2_fx1_b62_52_;
wire rs1_fx1_b30_;
wire [7:0] rs2_fx1_b30_23_;
wire tcu_muxtest_c_rep0;
wire [10:0] aux_rs1_fmt_fx1;
wire tcu_muxtest_d_rep0;
wire [10:1] aux_rs2_fmt_fx1;
wire [11:0] aux_eint_fx1;
wire aux_add_unused;
wire fx2_aux_scanin;
wire fx2_aux_scanout;
wire [10:0] aux_eint_fx2;
wire [10:0] eintx_fx2;
wire [5:0] i2f_eadj_fx2_;
wire [11:0] eadjx_fx2;
wire [1:0] einty_unused;
wire [10:0] einty_fx2;
wire fx3_einty_scanin;
wire fx3_einty_scanout;
wire [10:0] einty_fx3;
wire fx4_einty_scanin;
wire fx4_einty_scanout;
wire [10:0] einty_fx4;
wire [1:0] ma_fmt_sel_fx5;
wire [10:0] einty_fx5;
wire [1:0] einty_inc_unused;
wire [10:0] einty_inc_fx5;
wire i_exp_inc_sel_fx5;
wire enoinc_i1_fx5_;
wire enoinc_i1_fx5;
wire einty_adj_cin_fx5;
wire [5:0] eadj_fx5_;
wire einty_adj_unused;
wire [10:0] einty_adj_fx5;
wire [0:0] cmp_exp_eadj;
wire i_exp_inc_sel_fx5_;
wire fpc_exp_sel_mul_fx5_;
wire einc_i0_fx5;
wire einc_i1_fx5;
wire exp_inc_sel_fx5;
wire exp_noinc_sel_fx5;
wire [10:0] exp_res_fx5;
wire fb_exp_res_scanin;
wire fb_exp_res_scanout;


// ----------------------------------------------------------------------------
// Interface with FAD
// ----------------------------------------------------------------------------

input  [62:23] fad_rs1_fx1;            // rs1 unformatted
input  [62:23] fad_rs2_fx1;            // rs2 unformatted

// ----------------------------------------------------------------------------
// Interface with FAC
// ----------------------------------------------------------------------------

input    [9:0] fac_aexp_fmt_sel_e;     // aop exponent format mux select
input    [7:0] fac_bexp_fmt_sel_e;     // bop exponent format mux select
input          fac_aux_cin_fx1;        // aux exp adder cin

input          main_clken;             // main clken

// ----------------------------------------------------------------------------
// Interface with FPC
// ----------------------------------------------------------------------------

input          fpc_exp_sel_mul_fx5;
input    [3:0] fpc_eintx_sel_fx2;      // FxTOs=0001, FxTOd=0010, FiTO(s,d)=0100, F(s)MUL(s,d)=1000
input    [2:0] fpc_eadjx_sel_fx2;      // F(i,x)TO(s,d)=001, FsTOd=010, FdTOs=100
input    [1:0] fpc_ma_fmt_sel_fx4;     // FADD/FSUB: 001=00.1X, 010=1X.XX, 100=default
input          fpc_rinc_sel_fx5;
input          fpc_q_rinc_sel_fx5;     // rinc_sel and ~logical_sub 00.1X
output         fpe_aux_rs2_fmt_fx1_b0;
output  [11:0] fpe_aux_eint_fx1;
output  [10:0] fpe_rs1_fmt_fx1;
output  [10:0] fpe_rs2_fmt_fx1;
output         fpe_einty_adj_cout_fx5;
output         fpe_einty_eq_eadj_fx5;

// ----------------------------------------------------------------------------
// Interface with FPY
// ----------------------------------------------------------------------------

input          fgu_mul_result_fx5_b63;

// ----------------------------------------------------------------------------
// Interface with FPF
// ----------------------------------------------------------------------------

input          fpf_rcout_fx5;
output  [10:0] fpe_exp_res_fb;
output  [10:0] fpe_align_sel_fx2;

// ----------------------------------------------------------------------------
// Interface with FIC
// ----------------------------------------------------------------------------

input    [5:0] fic_i2f_eadj_fx2;
input    [5:0] fic_norm_eadj_fx5;

// ----------------------------------------------------------------------------
// Global Signals
// ----------------------------------------------------------------------------

input           l2clk;                  // clock input
input  	        scan_in;
input  		tcu_pce_ov;		// scan signals
input  		spc_aclk;
input  		spc_bclk;
input 	        tcu_dectest;
input           tcu_muxtest;
input           tcu_scan_en;
output 		scan_out;

// scan renames
assign stop   = 1'b0;
assign test   = tcu_dectest;
// end scan

fgu_fpe_dp_buff_macro__dbuff_32x__rep_1__stack_32l__width_4 test_rep0  (
  .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}),
  .dout({se,          pce_ov,     siclk,    soclk   })
  );


// ----------------------------------------------------------------------------
//                               FX1 stage
// ----------------------------------------------------------------------------

fgu_fpe_dp_msff_macro__stack_32l__width_18 fx1_fmtsel  (
  .scan_in(fx1_fmtsel_scanin),
  .scan_out(fx1_fmtsel_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din ({fac_aexp_fmt_sel_e[9:0],   fac_bexp_fmt_sel_e[7:0]  }),
  .dout({    aexp_fmt_sel_fx1[9:0],     bexp_fmt_sel_fx1[7:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// Add exponent input format muxes
//
// FADD: IF (Eb>=Ea) THEN (SC=(Eb-Ea)); ELSE (SC=(Ea-Eb))
//       IF (Eb>=Ea) THEN (Eint=Eb);    ELSE (Eint=Ea)
// ------------------------------------

fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 muxtest_a_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_a_rep0)
  );

fgu_fpe_dp_mux_macro__mux_pgpe__ports_8__stack_32l__width_11 add_fmt1  (
  .muxtst(tcu_muxtest_a_rep0),
  .din0( 11'b00000000001            ),  // FGX, F(s,d)TO(d,s), FSQRT(s,d)
  .din1({3'b000, fad_rs1_fx1[30:23]}),  // SP odd
  .din2({3'b000, fad_rs1_fx1[62:55]}),  // SP even
  .din3(         fad_rs1_fx1[62:52] ),  // DP
  .din4( 11'b00010111110            ),  // FsTOx                2^(63+127) =2^190
  .din5( 11'b10000111110            ),  // FdTOx                2^(63+1023)=2^1086
  .din6( 11'b00010011110            ),  // FsTOi,F(i,x)TO(s,d)  2^(31+127) =2^158
  .din7( 11'b10000011110            ),  // FdTOi                2^(31+1023)=2^1054
  .sel0(aexp_fmt_sel_fx1[0]),
  .sel1(aexp_fmt_sel_fx1[1]),
  .sel2(aexp_fmt_sel_fx1[2]),
  .sel3(aexp_fmt_sel_fx1[3]),
  .sel4(aexp_fmt_sel_fx1[4]),
  .sel5(aexp_fmt_sel_fx1[5]),
  .sel6(aexp_fmt_sel_fx1[6]),
  .dout(fpe_rs1_fmt_fx1[10:0]  ),
  .test(test)
  );

fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 muxtest_b_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_b_rep0)
  );

fgu_fpe_dp_mux_macro__mux_pgpe__ports_4__stack_32l__width_11 add_fmt2  (
  .muxtst(tcu_muxtest_b_rep0),
  .din0( 11'b00000000001            ),  // FGX, F(i,x)TO(s,d)
  .din1({3'b000, fad_rs2_fx1[30:23]}),  // SP odd
  .din2({3'b000, fad_rs2_fx1[62:55]}),  // SP even
  .din3(         fad_rs2_fx1[62:52] ),  // DP
  .sel0(bexp_fmt_sel_fx1[0]),
  .sel1(bexp_fmt_sel_fx1[1]),
  .sel2(bexp_fmt_sel_fx1[2]),
  .dout(fpe_rs2_fmt_fx1[10:0]  ),
  .test(test)
  );

// ------------------------------------
// Ea-Eb, Eb-Ea
// ------------------------------------

fgu_fpe_dp_inv_macro__stack_32l__width_11 inv_a  (
  .din (fpe_rs1_fmt_fx1[10:0] ),
  .dout(    rs1_fmt_fx1_[10:0]) 
  );

fgu_fpe_dp_inv_macro__stack_32l__width_11 inv_b  (
  .din (fpe_rs2_fmt_fx1[10:0] ),
  .dout(    rs2_fmt_fx1_[10:0]) 
  );

fgu_fpe_dp_cla_macro__width_12 amb  (
  .din0({1'b1,     rs2_fmt_fx1_[10:0]}),
  .din1({1'b0, fpe_rs1_fmt_fx1[10:0] }),
  .cin ( 1'b1                         ),
  .dout({amb_unused, ea_minus_eb_fx1[10:0]}),
  .cout( ea_gteq_eb_fx1               )
  );

fgu_fpe_dp_cla_macro__width_12 bma  (
  .din0({1'b0, fpe_rs2_fmt_fx1[10:0] }),
  .din1({1'b1,     rs1_fmt_fx1_[10:0]}),
  .cin ( 1'b1                         ),
  .dout({bma_unused, eb_minus_ea_fx1[10:0]}),
  .cout( eb_gteq_ea_fx1               )
  );

// ------------------------------------
// {generate aligner shift selects, Eintw}
// ------------------------------------

fgu_fpe_dp_msff_macro__mux_aonpe__ports_2__stack_32l__width_22 fx2_swp_sel  (
  .scan_in(fx2_swp_sel_scanin),
  .scan_out(fx2_swp_sel_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din0({eb_minus_ea_fx1[10:0],   fpe_rs2_fmt_fx1[10:0]}),
  .din1({ea_minus_eb_fx1[10:0],   fpe_rs1_fmt_fx1[10:0]}),
  .sel0(eb_gteq_ea_fx1),
  .sel1(ea_gteq_eb_fx1),
  .dout({fpe_align_sel_fx2[10:0], eintw_fx2[10:0]      }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// Multiply/Divide exponent input format muxes
//
// FMUL:  Eint=Ea+Eb-bias
//          -bias is accomplished by inverting Ea MSB and setting CPA cin=1
//
// FSQRT: Eint= 0+Eb-bias
//          -bias is accomplished by inverting Ea MSB and setting CPA cin=1
//
// FDIV:  Eint=Ea-Eb+bias=Ea+~Eb+1+bias
//          +bias+1 is accomplished by inverting Ea MSB, must invert Eb
// ------------------------------------

fgu_fpe_dp_inv_macro__stack_32l__width_21 inv_ab  (
  .din ({fad_rs1_fx1[62],  fad_rs2_fx1[62:52],        fad_rs1_fx1[30],  fad_rs2_fx1[30:23]      }),
  .dout({    rs1_fx1_b62_,     rs2_fx1_b62_52_[10:0],     rs1_fx1_b30_,     rs2_fx1_b30_23_[7:0]}) 
  );

fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 muxtest_c_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_c_rep0)
  );

fgu_fpe_dp_mux_macro__mux_pgpe__ports_7__stack_32l__width_11 aux_fmt1  (
  .muxtst(tcu_muxtest_c_rep0),
  .din0({3'b100, bexp_fmt_sel_fx1[2] , 7'b0         }),  // FSQRT (~bias),
                                                         //   bexp_fmt_sel_fx1[2] asserts if SP
  .din1(11'b11110000001                              ),  // FdTOs (-896-1=-897)
  .din2({     {4{rs1_fx1_b30_}}, fad_rs1_fx1[29:23] }),  // bias extended SP odd  -> DP
  .din3({     {4{rs1_fx1_b62_}}, fad_rs1_fx1[61:55] }),  // bias extended SP even -> DP
  .din4({3'b000, rs1_fx1_b30_,   fad_rs1_fx1[29:23] }),  // SP odd
  .din5({3'b000, rs1_fx1_b62_,   fad_rs1_fx1[61:55] }),  // SP even
  .din6({        rs1_fx1_b62_,   fad_rs1_fx1[61:52] }),  // DP
  .sel0(aexp_fmt_sel_fx1[0]),
  .sel1(aexp_fmt_sel_fx1[7]),
  .sel2(aexp_fmt_sel_fx1[8]),
  .sel3(aexp_fmt_sel_fx1[9]),
  .sel4(aexp_fmt_sel_fx1[1]),
  .sel5(aexp_fmt_sel_fx1[2]),
  .dout(aux_rs1_fmt_fx1[10:0]),
  .test(test)
  );

fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 muxtest_d_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_d_rep0)
  );

fgu_fpe_dp_mux_macro__mux_pgpe__ports_8__stack_32l__width_11 aux_fmt2  (
  .muxtst(tcu_muxtest_d_rep0),
  .din0({3'b000,                     rs2_fx1_b30_23_[7:0] }),  // SP odd  FDIV
  .din1({3'b000,                     rs2_fx1_b62_52_[10:3]}),  // SP even FDIV
  .din2({                            rs2_fx1_b62_52_[10:0]}),  // DP      FDIV
  .din3({fad_rs2_fx1[30],
              {3{rs2_fx1_b30_23_[7] }}, fad_rs2_fx1[29:23]}),  // bias extended SP odd  -> DP
  .din4({fad_rs2_fx1[62],
              {3{rs2_fx1_b62_52_[10]}}, fad_rs2_fx1[61:55]}),  // bias extended SP even -> DP
  .din5({3'b000,                 fad_rs2_fx1[30:23]       }),  // SP odd
  .din6({3'b000,                 fad_rs2_fx1[62:55]       }),  // SP even
  .din7({                        fad_rs2_fx1[62:52]       }),  // DP
  .sel0(bexp_fmt_sel_fx1[3]),
  .sel1(bexp_fmt_sel_fx1[4]),
  .sel2(bexp_fmt_sel_fx1[5]),
  .sel3(bexp_fmt_sel_fx1[6]),
  .sel4(bexp_fmt_sel_fx1[7]),
  .sel5(bexp_fmt_sel_fx1[1]),
  .sel6(bexp_fmt_sel_fx1[2]),
  .dout({aux_rs2_fmt_fx1[10:1], fpe_aux_rs2_fmt_fx1_b0}),
  .test(test)
  );

// ------------------------------------
// Auxiliary exponent adder
// ------------------------------------

fgu_fpe_dp_cla_macro__width_12 aux_add  (
  .din0({1'b0, aux_rs1_fmt_fx1[10:0]                        }),
  .din1({1'b0, aux_rs2_fmt_fx1[10:1], fpe_aux_rs2_fmt_fx1_b0}),
  .cin ( fac_aux_cin_fx1                 ),
  .dout(     aux_eint_fx1[11:0]          ),
  .cout(     aux_add_unused              )
  );

fgu_fpe_dp_buff_macro__width_12 buf_aux_add  (
  .din (    aux_eint_fx1[11:0]),
  .dout(fpe_aux_eint_fx1[11:0])
  );

// ----------------------------------------------------------------------------
//                               FX2 stage
// ----------------------------------------------------------------------------

fgu_fpe_dp_msff_macro__stack_32l__width_11 fx2_aux  (
  .scan_in(fx2_aux_scanin),
  .scan_out(fx2_aux_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (fpe_aux_eint_fx1[10:0]),
  .dout(    aux_eint_fx2[10:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// Eintx
// ------------------------------------

fgu_fpe_dp_mux_macro__mux_aope__ports_5__stack_32l__width_11 eintx  (
  .din0(11'b11111111111   ),  // NaN
  .din1(11'b00010111110   ),  // F(i,x)TOs  2^(63+127) =2^190
  .din2(11'b10000111110   ),  // F(i,x)TOd  2^(63+1023)=2^1086
  .din3(aux_eint_fx2[10:0]),  // F(s)MUL(s,d)
  .din4(eintw_fx2[10:0]   ),  // other
  .sel0(fpc_eintx_sel_fx2[0]),
  .sel1(fpc_eintx_sel_fx2[1]),
  .sel2(fpc_eintx_sel_fx2[2]),
  .sel3(fpc_eintx_sel_fx2[3]),
  .dout(eintx_fx2[10:0] )
  );

// ------------------------------------
// Eadjx for F(i,x)TO(s,d), FsTOd, FdTOs
// ------------------------------------

fgu_fpe_dp_inv_macro__stack_32l__width_6 inv_i2f  (
  .din (fic_i2f_eadj_fx2[5:0]  ),
  .dout(    i2f_eadj_fx2_[5:0]) 
  );

fgu_fpe_dp_mux_macro__mux_aope__ports_4__stack_32l__width_12 eadjx  (
  .din0({ 6'b111111, i2f_eadj_fx2_[5:0]}),  // F(i,x)TO(s,d),    ~(i2f norm amount)
  .din1( 12'b001101111111),                 // FsTOd, 2^(896-1), note: cin=1 in adder below
  .din2( 12'b110001111111),                 // FdTOs, ~(2^896),  note: cin=1 in adder below
  .din3( 12'b111111111111),                 // other, ~zero
  .sel0(fpc_eadjx_sel_fx2[0]),
  .sel1(fpc_eadjx_sel_fx2[1]),
  .sel2(fpc_eadjx_sel_fx2[2]),
  .dout(eadjx_fx2[11:0])
  );

// ------------------------------------
// Einty=Eintx-Eadjx
// ------------------------------------

fgu_fpe_dp_cla_macro__width_12 einty  (
  .din0({1'b0, eintx_fx2[10:0]}),
  .din1(       eadjx_fx2[11:0] ),
  .cin ( 1'b1                  ),
  .dout({einty_unused[0], einty_fx2[10:0]}),
  .cout( einty_unused[1]       )
  );

// ----------------------------------------------------------------------------
//                               FX3 stage
// ----------------------------------------------------------------------------

fgu_fpe_dp_msff_macro__stack_32l__width_11 fx3_einty  (
  .scan_in(fx3_einty_scanin),
  .scan_out(fx3_einty_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (einty_fx2[10:0]),
  .dout(einty_fx3[10:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------------------------------------------------------------------------
//                               FX4 stage
// ----------------------------------------------------------------------------

fgu_fpe_dp_msff_macro__stack_32l__width_24 fx4_einty  (
  .scan_in(fx4_einty_scanin),
  .scan_out(fx4_einty_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din ({fpc_ma_fmt_sel_fx4[1:0], einty_fx4[10:0], einty_fx3[10:0]}),
  .dout({    ma_fmt_sel_fx5[1:0], einty_fx5[10:0], einty_fx4[10:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------------------------------------------------------------------------
//                               FX5 stage
// ----------------------------------------------------------------------------

// ------------------------------------
// Einty_inc=Einty+(1X.XX|Rcout)
// ------------------------------------

fgu_fpe_dp_increment_macro__width_12 einty_inc  (
  .din ({1'b0, einty_fx5[10:0]}),
  .cin ( 1'b1                  ),
  .dout({einty_inc_unused[0], einty_inc_fx5[10:0] }),
  .cout( einty_inc_unused[1]   )
  );

fgu_fpe_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_32l__width_1 i_einc  ( 
  .din0(fgu_mul_result_fx5_b63),  // fpy 1X.XX (fmul)
  .din1(ma_fmt_sel_fx5[1]     ),  // logical_add 1X.XX, intfp 10.00
  .sel0(fpc_exp_sel_mul_fx5   ),  // fmul instr
  .sel1(1'b1                  ),
  .dout(i_exp_inc_sel_fx5     )   // exp inc detected
  );

// ------------------------------------
// Einty_adj=Einty-Eadj
// - cin not asserted if logical_sub and 00.1X.
//   In this case LZD gets overridden and eadj=0, when correct eadj=1.
//   This is accounted for by effectively subtracting 1 by not asserting cin.
// - If logical_sub and 00.1X, followed by Rcout, then
//   Eint-Eadj+Rcout=Eint-1+1=Eint
// ------------------------------------

fgu_fpe_dp_inv_macro__stack_32l__width_8 inv_eadj  (
  .din ({enoinc_i1_fx5_, ma_fmt_sel_fx5[0], fic_norm_eadj_fx5[5:0] }),
  .dout({enoinc_i1_fx5,  einty_adj_cin_fx5,          eadj_fx5_[5:0]})
  );

fgu_fpe_dp_cla_macro__width_12 einty_adj  (
  .din0({1'b0,      einty_fx5[10:0]}),
  .din1({6'b111111, eadj_fx5_[5:0] }),
  .cin ( einty_adj_cin_fx5          ),
  .dout({einty_adj_unused, einty_adj_fx5[10:0]}),
  .cout( fpe_einty_adj_cout_fx5     )
  );

// ------------------------------------
// Einty=Eadj
// ------------------------------------

fgu_fpe_dp_cmp_macro__width_12 cmp_exp  (
  .din0({6'b0, fic_norm_eadj_fx5[5:1], cmp_exp_eadj[0]}),  // [0] must acct for logical_sub and 00.1X case
  .din1({1'b0, einty_fx5[10:0]                        }),
  .dout(fpe_einty_eq_eadj_fx5                          )
  );

// exp_noinc_sel_fx5 =
//   (logical_sub 00.1X &
//    Rinc output selected &
//    Rinc output format 01.XX) |  // since 00.1X first gets normalized, actually check for Rcout
//   fmul instr

fgu_fpe_dp_nand_macro__ports_2__stack_32l__width_2 enoinc  (
  .din0({ma_fmt_sel_fx5[0], eadj_fx5_[0]     }),
  .din1({fpc_rinc_sel_fx5,  einty_adj_cin_fx5}),
  .dout({enoinc_i1_fx5_,    cmp_exp_eadj[0]  })
  );

fgu_fpe_dp_inv_macro__stack_32l__width_2 inv_einc  (
  .din ({i_exp_inc_sel_fx5,  fpc_exp_sel_mul_fx5 }),
  .dout({i_exp_inc_sel_fx5_, fpc_exp_sel_mul_fx5_})
  );

fgu_fpe_dp_nand_macro__dnand_8x__ports_2__stack_32l__width_4 einc  (
  .din0({fpc_q_rinc_sel_fx5, einc_i0_fx5,        enoinc_i1_fx5, einc_i1_fx5         }),  // fpc_q_rinc_sel_fx5 <= Rinc output selected & ~(logical_sub 00.1X)
  .din1({fpf_rcout_fx5,      i_exp_inc_sel_fx5_, fpf_rcout_fx5, fpc_exp_sel_mul_fx5_}),
  .dout({einc_i0_fx5,        exp_inc_sel_fx5,    einc_i1_fx5,   exp_noinc_sel_fx5   })
  );

// ------------------------------------
// Eres
// ------------------------------------

fgu_fpe_dp_mux_macro__mux_aope__ports_3__stack_32l__width_11 einty_mux  (
  .din0(einty_inc_fx5[10:0]),
  .din1(einty_fx5[10:0]    ),
  .din2(einty_adj_fx5[10:0]),
  .sel0(exp_inc_sel_fx5),
  .sel1(exp_noinc_sel_fx5),
  .dout(exp_res_fx5[10:0])
  );

// ----------------------------------------------------------------------------
//                               FB stage
// ----------------------------------------------------------------------------

fgu_fpe_dp_msff_macro__stack_32l__width_11 fb_exp_res  (
  .scan_in(fb_exp_res_scanin),
  .scan_out(fb_exp_res_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (    exp_res_fx5[10:0]),
  .dout(fpe_exp_res_fb[10:0] ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );


// fixscan start:
assign fx1_fmtsel_scanin         = scan_in                  ;
assign fx2_swp_sel_scanin        = fx1_fmtsel_scanout       ;
assign fx2_aux_scanin            = fx2_swp_sel_scanout      ;
assign fx3_einty_scanin          = fx2_aux_scanout          ;
assign fx4_einty_scanin          = fx3_einty_scanout        ;
assign fb_exp_res_scanin         = fx4_einty_scanout        ;
assign scan_out                  = fb_exp_res_scanout       ;
// fixscan end:
endmodule  // fgu_fpe_dp


//
//   buff macro
//
//


module fgu_fpe_dp_buff_macro__dbuff_32x__rep_1__stack_32l__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_msff_macro__stack_32l__width_18 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [16:0] so;

  input [17:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [17:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(18)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[17:0]),
.si({scan_in,so[16:0]}),
.so({so[16:0],scan_out}),
.q(dout[17:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpe_dp_buff_macro__dbuff_32x__stack_32l__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_mux_macro__mux_pgpe__ports_8__stack_32l__width_11 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [10:0] din0;
  input [10:0] din1;
  input [10:0] din2;
  input [10:0] din3;
  input [10:0] din4;
  input [10:0] din5;
  input [10:0] din6;
  input [10:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;
  input muxtst;
  input test;
  output [10:0] dout;


cl_dp1_penc8_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(11)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[10:0]),
  .in1(din1[10:0]),
  .in2(din2[10:0]),
  .in3(din3[10:0]),
  .in4(din4[10:0]),
  .in5(din5[10:0]),
  .in6(din6[10:0]),
  .in7(din7[10:0]),
.dout(dout[10:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_mux_macro__mux_pgpe__ports_4__stack_32l__width_11 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [10:0] din0;
  input [10:0] din1;
  input [10:0] din2;
  input [10:0] din3;
  input sel0;
  input sel1;
  input sel2;
  input muxtst;
  input test;
  output [10:0] dout;


cl_dp1_penc4_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
  .test(test)
);

mux4 #(11)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[10:0]),
  .in1(din1[10:0]),
  .in2(din2[10:0]),
  .in3(din3[10:0]),
.dout(dout[10:0]),
  .muxtst(muxtst)
);


endmodule


//
//   invert macro
//
//


module fgu_fpe_dp_inv_macro__stack_32l__width_11 (
  din, 
  dout);
  input [10:0] din;
  output [10:0] dout;


inv #(11)  d0_0 (
.in(din[10:0]),
.out(dout[10:0])
);


endmodule


//
//   cla macro
//
//


module fgu_fpe_dp_cla_macro__width_12 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [11:0] din0;
  input [11:0] din1;
  output [11:0] dout;
  output cout;


cla #(12)  m0_0 (
.cin(cin),
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout[11:0]),
.cout(cout)
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_msff_macro__mux_aonpe__ports_2__stack_32l__width_22 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire [21:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [20:0] so;

  input [21:0] din0;
  input sel0;
  input [21:0] din1;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [21:0] dout;


  output scan_out;


cl_dp1_muxbuff2_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(22)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[21:0]),
  .in1(din1[21:0]),
.dout(muxout[21:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(22)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[21:0]),
.si({scan_in,so[20:0]}),
.so({so[20:0],scan_out}),
.q(dout[21:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpe_dp_inv_macro__stack_32l__width_21 (
  din, 
  dout);
  input [20:0] din;
  output [20:0] dout;


inv #(21)  d0_0 (
.in(din[20:0]),
.out(dout[20:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_mux_macro__mux_pgpe__ports_7__stack_32l__width_11 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;

  input [10:0] din0;
  input [10:0] din1;
  input [10:0] din2;
  input [10:0] din3;
  input [10:0] din4;
  input [10:0] din5;
  input [10:0] din6;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input muxtst;
  input test;
  output [10:0] dout;


cl_dp1_penc7_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
  .test(test)
);

mux7 #(11)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .in0(din0[10:0]),
  .in1(din1[10:0]),
  .in2(din2[10:0]),
  .in3(din3[10:0]),
  .in4(din4[10:0]),
  .in5(din5[10:0]),
  .in6(din6[10:0]),
.dout(dout[10:0]),
  .muxtst(muxtst)
);


endmodule


//
//   buff macro
//
//


module fgu_fpe_dp_buff_macro__width_12 (
  din, 
  dout);
  input [11:0] din;
  output [11:0] dout;


buff #(12)  d0_0 (
.in(din[11:0]),
.out(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_msff_macro__stack_32l__width_11 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [9:0] so;

  input [10:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [10:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_mux_macro__mux_aope__ports_5__stack_32l__width_11 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;

  input [10:0] din0;
  input [10:0] din1;
  input [10:0] din2;
  input [10:0] din3;
  input [10:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  output [10:0] dout;


cl_dp1_penc5_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(11)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[10:0]),
  .in1(din1[10:0]),
  .in2(din2[10:0]),
  .in3(din3[10:0]),
  .in4(din4[10:0]),
.dout(dout[10:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpe_dp_inv_macro__stack_32l__width_6 (
  din, 
  dout);
  input [5:0] din;
  output [5:0] dout;


inv #(6)  d0_0 (
.in(din[5:0]),
.out(dout[5:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_mux_macro__mux_aope__ports_4__stack_32l__width_12 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [11:0] din0;
  input [11:0] din1;
  input [11:0] din2;
  input [11:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [11:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(12)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[11:0]),
  .in1(din1[11:0]),
  .in2(din2[11:0]),
  .in3(din3[11:0]),
.dout(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_msff_macro__stack_32l__width_24 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [22:0] so;

  input [23:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [23:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


//
//   increment macro 
//
//


module fgu_fpe_dp_increment_macro__width_12 (
  din, 
  cin, 
  dout, 
  cout);
  input [11:0] din;
  input cin;
  output [11:0] dout;
  output cout;


incr #(12)  m0_0 (
.cin(cin),
.in(din[11:0]),
.out(dout[11:0]),
.cout(cout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_32l__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  output [0:0] dout;


mux2s #(1)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
.dout(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpe_dp_inv_macro__stack_32l__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fpe_dp_cmp_macro__width_12 (
  din0, 
  din1, 
  dout);
  input [11:0] din0;
  input [11:0] din1;
  output dout;


cmp #(12)  m0_0 (
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout)
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fpe_dp_nand_macro__ports_2__stack_32l__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


nand2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpe_dp_inv_macro__stack_32l__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


inv #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fpe_dp_nand_macro__dnand_8x__ports_2__stack_32l__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


nand2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpe_dp_mux_macro__mux_aope__ports_3__stack_32l__width_11 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [10:0] din0;
  input [10:0] din1;
  input [10:0] din2;
  input sel0;
  input sel1;
  output [10:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(11)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[10:0]),
  .in1(din1[10:0]),
  .in2(din2[10:0]),
.dout(dout[10:0])
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fpf_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fpf_dp (
  fad_rs1_fmt_fx1, 
  fad_rs2_fmt_fx1, 
  fad_rs1_fx1, 
  fad_rs2_fx1, 
  fad_r1_odd32b_fx1, 
  fad_fsr_tem_fx1_b4, 
  fpf_w1_result_fb, 
  fgu_exu_result_fx5, 
  fgd_result_fx5, 
  fpc_int_res_sel_fx4, 
  fpc_vis_cmp_result_fx5, 
  fpc_result_sel_fx5, 
  fpc_ovf_if_rcout_fx5, 
  fpc_ma_fmt_sel_fx4, 
  fpc_int_sel_fx5, 
  fpc_fconst_sel_fx5, 
  fpc_fp_cin00_fx2, 
  fpc_cin00_fx2, 
  fpc_cin16_48_fx2, 
  fpc_cin32_fx2, 
  fpc_prop16_48_fx2, 
  fpc_prop32_fx2, 
  fpc_mle_sel_fx2, 
  fpc_mse_sel_fx2, 
  fpc_sign_fx5, 
  fpc_sign_fb, 
  fpc_sp_dest_fx4, 
  fpc_fadd_eac_enable_fx2, 
  fpc_i2f_sel_fx1, 
  fpc_rinc_sel_fx5, 
  fpc_qthenan_fx4, 
  fpc_den2nor_sp_fb, 
  fpc_den2nor_dp_fb, 
  fpf_b_gteq_a_fx2, 
  fpf_b_eq_a_fx2, 
  fpf_hi_aof_fx1, 
  fpf_hi_bof_fx1, 
  fpf_lo_aof_fx1, 
  fpf_lo_bof_fx1, 
  fpf_azf0_fx1, 
  fpf_bzf0_fx1, 
  fpf_aoe0_fx1, 
  fpf_boe0_fx1, 
  fpf_aze0_fx1, 
  fpf_bze0_fx1, 
  fpf_ma_sum_fx4, 
  fpf_ma_cout_fx4, 
  fpf_cmp_swap_blta_fx2, 
  fpf_align_sticky_fx4_l, 
  fpf_byte_unsure_x_sp_fx3, 
  fpf_byte_unsure_x_dp_fx3, 
  fic_norm_eadj_fx5, 
  fic_i2f_align_sel_fx2, 
  fpf_rs2_cmp_din_fx1, 
  fpf_man_se_byte_fx3_b38_32, 
  fpf_man_se_byte_fx3_b6_0, 
  fgu_cmp_fcc_fx3, 
  fgu_cmp_fcc_vld_fx3, 
  fac_tlu_flush_fx3, 
  fac_fpx_sp_dest_fx1, 
  fac_fpx_sp_src_fx1, 
  fac_pre_fcc_vld_fx2, 
  fac_fcmpe_fx1, 
  fac_rs2_rotate_sel_e, 
  fac_i2f_sel_e, 
  fac_force_swap_blta_fx1, 
  fac_force_noswap_blta_fx1, 
  main_clken, 
  fgu_mul_result_fx5, 
  fpy_fp_result_fx4_b63, 
  fdc_finish_int_early, 
  fdd_result, 
  fpf_sa_xor_sb_fx1, 
  fpe_exp_res_fb, 
  fpe_align_sel_fx2, 
  fpf_rcout_fx5, 
  fpf_rcout_fb, 
  fpf_implied_bit_fx5, 
  fec_w1_ecc_inject_fb, 
  fpf_w1_synd_fb, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_scan_en, 
  scan_out);
wire stop;
wire test;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [63:32] rs1_cmp_din_fx1;
wire fad_rs20_fx1_b63;
wire fad_rs20_fx1_b31;
wire [4:0] rs2_rotate_sel_fx1;
wire [63:0] rs2_cmp_din_fx1;
wire [63:0] rs1_cmp_din_fx1_;
wire fac_force_swap_blta_fx1_;
wire [15:0] cmp_bma3_unused;
wire cmp_bma_cout3_fx1;
wire [15:0] cmp_bma2_unused;
wire cmp_bma_cout2_fx1;
wire [15:0] cmp_bma1_unused;
wire cmp_bma_cout1_fx1;
wire [15:0] cmp_bma0_unused;
wire cmp_bma_cout0_fx1;
wire cmp_eq3_fx1;
wire cmp_eq2_fx1;
wire cmp_eq1_fx1;
wire cmp_eq0_fx1;
wire [2:0] cmp_i0_fx1;
wire cmp_eq30_fx1;
wire [2:0] cmp_i1_fx1;
wire cmp_swap_blta_fx1;
wire q_sign_beqa_fx1;
wire [1:0] cmp_i3_fx1;
wire cmp_i4_fx1;
wire cmp_beqa_fx1;
wire azf_fx1;
wire bzf_fx1;
wire bze_fx1;
wire boe_fx1;
wire aze_fx1;
wire aoe_fx1;
wire fpf_azf0_fx1_;
wire fpf_bzf0_fx1_;
wire fac_fpx_sp_src_fx1_;
wire fad_rs1_fmt_fx1_b62_;
wire fad_rs2_fmt_fx1_b62_;
wire [54:52] rs2_exp_qual1_fx1;
wire [54:52] rs1_exp_qual1_fx1;
wire [54:52] rs2_exp_qual0_fx1;
wire [54:52] rs1_exp_qual0_fx1;
wire i_rs1_snan_src_fx1;
wire i_rs2_snan_src_fx1;
wire nan_src_fx1;
wire snan_src_fx1;
wire zero_eq_zero_fx1_;
wire cmp_swap_blta_fx1_;
wire fcmpe_fx1_;
wire [63:63] fpf_rs2_cmp_din_fx1_;
wire cmp_i7_1_fx1;
wire cmp_i8_fx1;
wire cmp_i7_0_fx1;
wire cmp_blta_fx1;
wire cmp_bgta_fx1;
wire fx2_swp_le_scanin;
wire fx2_swp_le_scanout;
wire [63:0] man_le_fx2;
wire fx2_swp_se_scanin;
wire fx2_swp_se_scanout;
wire [63:0] man_se_fx2;
wire fx2_fcc_scanin;
wire fx2_fcc_scanout;
wire [1:0] i2f_sel_fx1;
wire nan_src_fx2;
wire cmp_blta_fx2;
wire cmp_bgta_fx2;
wire zero_eq_zero_fx2_;
wire fcmpe_fx2_;
wire snan_src_fx2;
wire fsr_tem_nvm_fx2;
wire fcmpe_fx2;
wire [3:0] i2f_sel_fx2;
wire sp_dest_fx2;
wire [1:0] fcc_fx2;
wire fcmp_nv_trap_fx2_;
wire fcmpe_nv_trap_fx2_;
wire v9cmp_nv_trap_fx2;
wire [63:0] man_se_byte_fx2;
wire [6:0] man_se_byte_fx2_;
wire [55:0] man_se_fx2_;
wire [6:0] q_man_se_byte_fx2;
wire [55:0] q_man_se_fx2;
wire [5:0] asel_i0_fx2;
wire [5:0] asel_i1_fx2;
wire [5:0] merged_align_sel_fx2;
wire tcu_muxtest_b_rep0;
wire [63:0] man_se_bit_fx2;
wire [63:40] q2_man_se_fx2;
wire [44:38] q2_man_se_byte_fx2;
wire [52:0] man_se_byte_sticky_fx2;
wire [1:0] byte_unsure_x_sp_fx2;
wire [1:0] byte_unsure_x_dp_fx2;
wire tcu_muxtest_c_rep0;
wire [13:0] man_se_bit_sticky_fx2;
wire add_byte_sticky_fx2_l;
wire fx3_mle_scanin;
wire fx3_mle_scanout;
wire [63:0] man_le_fx3;
wire fx3_mse_scanin;
wire fx3_mse_scanout;
wire [63:0] man_se_bit_fx3;
wire fx3_fcc_scanin;
wire fx3_fcc_scanout;
wire ma_cout_fx3;
wire prop32_fx3;
wire align_sticky_fx3_l;
wire fadd_eac_enable_fx3;
wire fp_cin00_fx3;
wire cin00_fx3;
wire cin16_48_fx3;
wire cin32_fx3;
wire prop16_48_fx3;
wire prop32_fx4;
wire mle_sel_fx3;
wire [2:0] mse_sel_fx3;
wire [3:0] pre_fcc_vld_fx3;
wire v9cmp_nv_trap_fx3;
wire add_byte_sticky_fx3_l;
wire [13:0] man_se_bit_sticky_fx3;
wire v9cmp_nv_trap_fx3_;
wire fac_tlu_flush_fx3_;
wire [63:0] man_se_bit_fx3_;
wire [63:0] final_man_le_fx3;
wire tcu_muxtest_d_rep0;
wire [63:0] final_man_se_fx3;
wire final_fp_cin00_fx3;
wire ma16_cout07_fx3;
wire final_cin16_48_i0_fx3;
wire ma16_cout47_fx3;
wire final_cin16_48_i2_fx3;
wire final_cin16_48_i1_fx3;
wire final_cin16_48_i3_fx3;
wire final_cin16_fx3;
wire final_cin48_fx3;
wire [63:0] ma16_sum_fx3;
wire ma16_cout31_unused;
wire ma16_cout63_unused;
wire [63:0] ma64_sum_fx3;
wire fx4_ma64_sum_scanin;
wire fx4_ma64_sum_scanout;
wire fx4_ma16_sum_scanin;
wire fx4_ma16_sum_scanout;
wire [63:0] ma16_sum_fx4;
wire [63:0] final_ma_sum_fx4;
wire [62:62] ma_sum_quiet_fx4;
wire fx5_sum_scanin;
wire fx5_sum_scanout;
wire [63:0] ma_sum_fx5;
wire fx5_ma_fmt_sel_scanin;
wire fx5_ma_fmt_sel_scanout;
wire [5:0] int_res_sel_fx5;
wire [4:0] ma_fmt_sel_fx5;
wire fp_result_fx5_b63;
wire sp_dest_fx5;
wire tcu_muxtest_e_rep0;
wire [63:0] unnorm_inter_res_fx5;
wire tcu_muxtest_f_rep0;
wire [39:11] pad_inc_fx5;
wire tcu_muxtest_g_rep0;
wire [62:4] norm_byte_fx5;
wire tcu_muxtest_h_rep0;
wire [62:11] norm_bit_fx5;
wire [10:0] minc_unused;
wire [51:0] inc_inter_res_fx5;
wire [62:11] nrd_res_fx5;
wire [63:0] int_data_fx5;
wire fb_int_fconst_scanin;
wire fb_int_fconst_scanout;
wire [63:0] int_fconst_res_fb;
wire [63:0] int_result_fx5;
wire [63:0] int_result0_fx5;
wire [4:2] q_result_sel_fx5;
wire fb_nrd_scanin;
wire fb_nrd_scanout;
wire [5:0] result_sel_fb;
wire [62:11] nrd_res_fb;
wire fb_fgd_scanin;
wire fb_fgd_scanout;
wire [63:0] fgd_result_fb;
wire emin_sp_fb;
wire emin_dp_fb;
wire tcu_muxtest_i_rep0;
wire [63:0] w1_result_fb;
wire [13:0] w1_synd_fb;


// ----------------------------------------------------------------------------
// Interface with FAD
// ----------------------------------------------------------------------------

input   [63:0] fad_rs1_fmt_fx1;        // rs1 formatted
input   [63:0] fad_rs2_fmt_fx1;        // rs2 formatted
input   [63:0] fad_rs1_fx1;            // rs1 unformatted
input   [63:0] fad_rs2_fx1;            // rs2 unformatted
input          fad_r1_odd32b_fx1;
input          fad_fsr_tem_fx1_b4;     // NVM

output  [63:0] fpf_w1_result_fb;       // FPX result

// ----------------------------------------------------------------------------
// Interface with EXU
// ----------------------------------------------------------------------------

output  [63:0] fgu_exu_result_fx5;     // FGU result for EXU{1,0}

// ----------------------------------------------------------------------------
// Interface with FGD
// ----------------------------------------------------------------------------

input   [63:0] fgd_result_fx5;         // FGX result

// ----------------------------------------------------------------------------
// Interface with FPC
// ----------------------------------------------------------------------------

input    [5:1] fpc_int_res_sel_fx4;
input    [3:0] fpc_vis_cmp_result_fx5; // vis cmp result data
input    [5:0] fpc_result_sel_fx5;     // result select
input    [1:0] fpc_ovf_if_rcout_fx5;   // result select qualification for rcout
input    [4:0] fpc_ma_fmt_sel_fx4;
input    [3:0] fpc_int_sel_fx5;
input    [4:0] fpc_fconst_sel_fx5;
input          fpc_fp_cin00_fx2;       // main adder control
input          fpc_cin00_fx2;          // main adder control
input          fpc_cin16_48_fx2;       // main adder control
input          fpc_cin32_fx2;          // main adder control
input          fpc_prop16_48_fx2;      // main adder control
input          fpc_prop32_fx2;         // main adder control
input          fpc_mle_sel_fx2;
input    [2:0] fpc_mse_sel_fx2;
input          fpc_sign_fx5;           // result sign
input          fpc_sign_fb;            // result sign
input          fpc_sp_dest_fx4;        // SP result dest
input          fpc_fadd_eac_enable_fx2;
input    [3:2] fpc_i2f_sel_fx1;        // 10=F(i,x)TO(s,d) 2's comp, 01=F(i,x)TO(s,d) not 2's comp
input          fpc_rinc_sel_fx5;
input          fpc_qthenan_fx4;        // quiet the propagating NaN, set frac MSB=1
input          fpc_den2nor_sp_fb;      // denorm intermediate result rounded to norm
input          fpc_den2nor_dp_fb;      // denorm intermediate result rounded to norm
output   [3:0] fpf_b_gteq_a_fx2;       // FCMP (B-A) cout, doesn't account for MSB
output   [3:0] fpf_b_eq_a_fx2;         // FCMP (B=A), doesn't account for MSB
output         fpf_hi_aof_fx1;
output         fpf_hi_bof_fx1;
output         fpf_lo_aof_fx1;
output         fpf_lo_bof_fx1;
output         fpf_azf0_fx1;           // rs1[62:0]==63'b0, must acct for rs1[63]
output         fpf_bzf0_fx1;           // rs2[62:0]==63'b0, must acct for rs2[63]
output         fpf_aoe0_fx1;
output         fpf_boe0_fx1;
output         fpf_aze0_fx1;
output         fpf_bze0_fx1;
output  [63:0] fpf_ma_sum_fx4;         // main adder sum
output         fpf_ma_cout_fx4;        // main adder cout
output         fpf_cmp_swap_blta_fx2;
output         fpf_align_sticky_fx4_l;
output   [1:0] fpf_byte_unsure_x_sp_fx3;
output   [1:0] fpf_byte_unsure_x_dp_fx3;

// ----------------------------------------------------------------------------
// Interface with FIC
// ----------------------------------------------------------------------------

input    [5:0] fic_norm_eadj_fx5;
input    [5:0] fic_i2f_align_sel_fx2;
output  [63:0] fpf_rs2_cmp_din_fx1;    // rt. justified rs2 for F(i,x)TO(s,d)
output [38:32] fpf_man_se_byte_fx3_b38_32;
output   [6:0] fpf_man_se_byte_fx3_b6_0;

// ----------------------------------------------------------------------------
// Interface with DEC
// ----------------------------------------------------------------------------

output   [1:0] fgu_cmp_fcc_fx3;        // fcc data {fcc3, fcc2, fcc1, fcc0}
output   [3:0] fgu_cmp_fcc_vld_fx3;    // fcc data valid

// ----------------------------------------------------------------------------
// Interface with FAC
// ----------------------------------------------------------------------------

input          fac_tlu_flush_fx3;
input          fac_fpx_sp_dest_fx1;    // SP result dest
input          fac_fpx_sp_src_fx1;     // SP source
input    [3:0] fac_pre_fcc_vld_fx2;    // must clear fcc_vld if (nv & TEM) | flush
input          fac_fcmpe_fx1;          // FCMPE, not FCMP
input    [4:0] fac_rs2_rotate_sel_e;   // 00001=odd FiTO(s,d), 00010=even FiTO(s,d), 00100=FiTO(s,d), 01000=rs2_odd32b, 10000=~rs2_odd32b
input    [1:0] fac_i2f_sel_e;          // 01=F(i,x)TO(s,d), 10=~F(i,x)TO(s,d)
input          fac_force_swap_blta_fx1; // force the swap_blta condition
input          fac_force_noswap_blta_fx1; // force the ~swap_blta condition

input          main_clken;             // main clken

// ----------------------------------------------------------------------------
// Interface with FPY
// ----------------------------------------------------------------------------

input   [63:0] fgu_mul_result_fx5;
input 	       fpy_fp_result_fx4_b63;

// ----------------------------------------------------------------------------
// Interface with FDC
// ----------------------------------------------------------------------------

input          fdc_finish_int_early;

// ----------------------------------------------------------------------------
// Interface with FDD
// ----------------------------------------------------------------------------

input   [63:0] fdd_result;
output         fpf_sa_xor_sb_fx1;

// ----------------------------------------------------------------------------
// Interface with FPE
// ----------------------------------------------------------------------------

input   [10:0] fpe_exp_res_fb;
input    [5:0] fpe_align_sel_fx2;
output         fpf_rcout_fx5;
output         fpf_rcout_fb;
output         fpf_implied_bit_fx5;

// ----------------------------------------------------------------------------
// Interface with FEC
// ----------------------------------------------------------------------------

input    [6:0] fec_w1_ecc_inject_fb;   // ECC error injection

// ----------------------------------------------------------------------------
// Interface with FRF
// ----------------------------------------------------------------------------

output  [13:0] fpf_w1_synd_fb;         // ECC generation for w1 result

// ----------------------------------------------------------------------------
// Global Signals
// ----------------------------------------------------------------------------

input          l2clk;                  // clock input
input  	       scan_in;
input  	       tcu_pce_ov;	       // scan signals
input  	       spc_aclk;
input  	       spc_bclk;
input 	       tcu_dectest;
input          tcu_muxtest;
input 	       tcu_scan_en;

output 	       scan_out;

// scan renames
assign stop   = 1'b0;
assign test   = tcu_dectest;
// end scan

fgu_fpf_dp_buff_macro__dbuff_32x__rep_1__width_4 test_rep0  (
  .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}),
  .dout({se,          pce_ov,     siclk,    soclk   })
  );


// ----------------------------------------------------------------------------
//                               FX1 stage
// ----------------------------------------------------------------------------

// ------------------------------------
// rs1/rs2 compare logic
// - V9 fp compares (generate fcc): FCMP(s,d), FCMPE(s,d)
// - VIS partitioned compares: FCMPEQ(16,32), FCMPGT(16,32), FCMPLE(16,32), FCMPNE(16,32)
// - V9 swap determination
// ------------------------------------

fgu_fpf_dp_mux_macro__mux_pgpe__ports_2__width_32 rs1_rotate  ( 
  .din0(fad_rs1_fx1[31:0]),
  .din1(fad_rs1_fx1[63:32]),
  .sel0(fad_r1_odd32b_fx1),
  .dout(rs1_cmp_din_fx1[63:32])
  );

fgu_fpf_dp_buff_macro__width_2 buf_sign  (
  .din ({fad_rs2_fx1[63],  fad_rs2_fx1[31] }),
  .dout({fad_rs20_fx1_b63, fad_rs20_fx1_b31})
  );

fgu_fpf_dp_mux_macro__dmux_6x__mux_aonpe__ports_4__width_64 rs2_rotate  (
  .din0({{32{fad_rs20_fx1_b31}}, fad_rs2_fx1[31:0]}),  // odd  FiTO(s,d), rt. justified & sign extended rs2
  .din1({{32{fad_rs20_fx1_b63}}, fad_rs2_fx1[63:32]}),  // even FiTO(s,d), rt. justified & sign extended rs2
  .din2({fad_rs2_fx1[31:0], 32'b0}),
  .din3( fad_rs2_fx1[63:0]        ),
  .sel0(rs2_rotate_sel_fx1[0]),
  .sel1(rs2_rotate_sel_fx1[1]),
  .sel2(rs2_rotate_sel_fx1[3]),
  .sel3(rs2_rotate_sel_fx1[4]),
  .dout(    rs2_cmp_din_fx1[63:0])
  );

fgu_fpf_dp_buff_macro__width_64 buf_rs2_rotate  (
  .din (    rs2_cmp_din_fx1[63:0]),
  .dout(fpf_rs2_cmp_din_fx1[63:0])
  );

fgu_fpf_dp_inv_macro__width_64 inv_rs1  (
  .din ({rs1_cmp_din_fx1[63:32], fad_rs1_fx1[31:0]}),
  .dout(rs1_cmp_din_fx1_[63:0]) 
  );

fgu_fpf_dp_cla_macro__width_16 cmp_bma3  (
  .din0({fac_force_swap_blta_fx1_,      rs1_cmp_din_fx1_[62:48]}),  // ignore sign bit for swap calculation
  .din1({fac_force_noswap_blta_fx1, fpf_rs2_cmp_din_fx1[62:48] }),  // ignore sign bit for swap calculation
  .cin (1'b1),
  .dout(cmp_bma3_unused[15:0]),
  .cout(cmp_bma_cout3_fx1)
  );

fgu_fpf_dp_cla_macro__width_16 cmp_bma2  (
  .din0(    rs1_cmp_din_fx1_[47:32]),
  .din1(fpf_rs2_cmp_din_fx1[47:32] ),
  .cin (1'b1),
  .dout(cmp_bma2_unused[15:0]),
  .cout(cmp_bma_cout2_fx1)
  );

fgu_fpf_dp_cla_macro__width_16 cmp_bma1  (
  .din0(rs1_cmp_din_fx1_[31:16]),
  .din1(fad_rs2_fx1[31:16]     ),
  .cin (1'b1),
  .dout(cmp_bma1_unused[15:0]),
  .cout(cmp_bma_cout1_fx1)
  );

fgu_fpf_dp_cla_macro__width_16 cmp_bma0  (
  .din0(rs1_cmp_din_fx1_[15:0]),
  .din1(fad_rs2_fx1[15:0]     ),
  .cin (1'b1),
  .dout(cmp_bma0_unused[15:0]),
  .cout(cmp_bma_cout0_fx1)
  );

fgu_fpf_dp_cmp_macro__width_16 cmp_eq3  (
  .din0({fac_force_swap_blta_fx1,       rs1_cmp_din_fx1[62:48]}),  // ignore sign bit for swap calculation
  .din1({fac_force_noswap_blta_fx1, fpf_rs2_cmp_din_fx1[62:48]}),  // ignore sign bit for swap calculation
  .dout(cmp_eq3_fx1)
  );

fgu_fpf_dp_cmp_macro__width_16 cmp_eq2  (
  .din0(    rs1_cmp_din_fx1[47:32]),
  .din1(fpf_rs2_cmp_din_fx1[47:32]),
  .dout(cmp_eq2_fx1)
  );

fgu_fpf_dp_cmp_macro__width_16 cmp_eq1  (
  .din0(fad_rs1_fx1[31:16]),
  .din1(fad_rs2_fx1[31:16]),
  .dout(cmp_eq1_fx1)
  );

fgu_fpf_dp_cmp_macro__width_16 cmp_eq0  (
  .din0(fad_rs1_fx1[15:0]),
  .din1(fad_rs2_fx1[15:0]),
  .dout(cmp_eq0_fx1)
  );

// ------------------------------------
// V9 swap determination (B<A)
// - doesn't account for sign bits or nan source(s)
// ------------------------------------

fgu_fpf_dp_nor_macro__ports_2__width_3 cmp_i0  (
  .din0({1'b0,              fac_fpx_sp_dest_fx1, fac_fpx_sp_dest_fx1}),
  .din1({cmp_bma_cout2_fx1, cmp_bma_cout1_fx1,   cmp_bma_cout0_fx1  }),
  .dout(cmp_i0_fx1[2:0]) 
  );

fgu_fpf_dp_nand_macro__ports_4__width_4 cmp_i1  (
  .din0({cmp_bma_cout3_fx1, cmp_eq30_fx1,  cmp_eq30_fx1,  cmp_eq30_fx1 }),
  .din1({cmp_i1_fx1[0],     cmp_i0_fx1[2], cmp_eq2_fx1,   cmp_eq2_fx1  }),
  .din2({cmp_i1_fx1[1],     1'b1,          cmp_i0_fx1[1], cmp_eq1_fx1  }),
  .din3({cmp_i1_fx1[2],     1'b1,          1'b1,          cmp_i0_fx1[0]}),
  .dout({cmp_swap_blta_fx1,  // not yet qual w/ sign bits and nan source(s)
         cmp_i1_fx1[2:0]})
  );

// ------------------------------------
// V9 equal determination (A=B)
// - doesn't account nan source(s)
// ------------------------------------

fgu_fpf_dp_xnor_macro__ports_2__width_1 cmp_i2  (
  .din0(    rs1_cmp_din_fx1[63]),
  .din1(fpf_rs2_cmp_din_fx1[63]),
  .dout(q_sign_beqa_fx1) 
  );

fgu_fpf_dp_inv_macro__width_1 div_i1  (
  .din (q_sign_beqa_fx1),
  .dout(fpf_sa_xor_sb_fx1)  // required by fdd
  );

fgu_fpf_dp_or_macro__ports_2__width_2 cmp_i3  (
  .din0({cmp_eq1_fx1,         cmp_eq0_fx1        }),
  .din1({fac_fpx_sp_dest_fx1, fac_fpx_sp_dest_fx1}),
  .dout(cmp_i3_fx1[1:0]) 
  );

fgu_fpf_dp_and_macro__ports_4__width_2 cmp_i4  (
  .din0({cmp_eq2_fx1,  cmp_i3_fx1[0]  }),
  .din1({cmp_eq30_fx1, cmp_i3_fx1[1]  }),
  .din2({1'b1,         cmp_i4_fx1     }),
  .din3({1'b1,         q_sign_beqa_fx1}),
  .dout({cmp_i4_fx1,   cmp_beqa_fx1   })  // not yet qual w/ nan source(s)
  );

// ------------------------------------
// Detect all zeros fraction (OF) (for intermediate denorm round to norm cases only)
//        all zeros fraction (ZF)
//        all ones  exponent (OE)
//        all zeros exponent (ZE)
// for each source (rs1,rs2)
// ------------------------------------

fgu_fpf_dp_cmp_macro__width_32 hi_aof  (
  .din0({fad_rs1_fmt_fx1[62:40], 9'b0}),  // exclude implied bit
  .din1({23'h7fffff,             9'b0}),
  .dout(fpf_hi_aof_fx1)
  );

fgu_fpf_dp_cmp_macro__width_32 hi_bof  (
  .din0({fad_rs2_fmt_fx1[62:40], 9'b0}),  // exclude implied bit
  .din1({23'h7fffff,             9'b0}),
  .dout(fpf_hi_bof_fx1)
  );

fgu_fpf_dp_cmp_macro__width_32 lo_aof  (
  .din0({fad_rs1_fmt_fx1[39:11], 3'b0}),  // exclude implied bit
  .din1({29'h1fffffff,           3'b0}),
  .dout(fpf_lo_aof_fx1)
  );

fgu_fpf_dp_cmp_macro__width_32 lo_bof  (
  .din0({fad_rs2_fmt_fx1[39:11], 3'b0}),  // exclude implied bit
  .din1({29'h1fffffff,           3'b0}),
  .dout(fpf_lo_bof_fx1)
  );

fgu_fpf_dp_zero_macro__width_64 azf  (
  .din ({1'b0, fad_rs1_fmt_fx1[62:0]}),  // exclude implied bit
  .dout(azf_fx1)
  );

fgu_fpf_dp_zero_macro__width_64 bzf  (
  .din ({1'b0, fad_rs2_fmt_fx1[62:0]}),  // exclude implied bit
  .dout(bzf_fx1)
  );

fgu_fpf_dp_buff_macro__width_7 buff_cmp  (
  .din ({    bze_fx1,      boe_fx1,      bzf_fx1,      aze_fx1,      aoe_fx1,      azf_fx1,  cmp_eq3_fx1 }),
  .dout({fpf_bze0_fx1, fpf_boe0_fx1, fpf_bzf0_fx1, fpf_aze0_fx1, fpf_aoe0_fx1, fpf_azf0_fx1, cmp_eq30_fx1})
  );

fgu_fpf_dp_inv_macro__width_6 inv_zf  (
  .din ({fpf_azf0_fx1,
         fpf_bzf0_fx1,
         fac_fpx_sp_src_fx1,
         fac_force_swap_blta_fx1,
         fad_rs1_fmt_fx1[62],
         fad_rs2_fmt_fx1[62]}),
  .dout({fpf_azf0_fx1_,
         fpf_bzf0_fx1_,
         fac_fpx_sp_src_fx1_,
         fac_force_swap_blta_fx1_,
         fad_rs1_fmt_fx1_b62_,
         fad_rs2_fmt_fx1_b62_})
  );

fgu_fpf_dp_or_macro__ports_2__width_6 cmp_i5a  (  // set 3 exponent LSBs to 3'b111 if SP
  .din0({fpf_rs2_cmp_din_fx1[54:52], rs1_cmp_din_fx1[54:52]  }),
  .din1({6{fac_fpx_sp_src_fx1}                               }),
  .dout({rs2_exp_qual1_fx1[54:52],   rs1_exp_qual1_fx1[54:52]}) 
  );

fgu_fpf_dp_cmp_macro__width_12 aoe  (
  .din0({1'b1, rs1_cmp_din_fx1[62:55], rs1_exp_qual1_fx1[54:52]}),
  .din1(12'b111111111111),
  .dout(aoe_fx1)
  );

fgu_fpf_dp_cmp_macro__width_12 boe  (
  .din0({1'b1, fpf_rs2_cmp_din_fx1[62:55], rs2_exp_qual1_fx1[54:52]}),
  .din1(12'b111111111111),
  .dout(boe_fx1)
  );

fgu_fpf_dp_and_macro__ports_2__width_8 cmp_i5b  (  // set 3 exponent LSBs to 3'b000 if SP
  .din0({fpf_rs2_cmp_din_fx1[54:52], rs1_cmp_din_fx1[54:52],   fad_rs1_fmt_fx1_b62_, fad_rs2_fmt_fx1_b62_}),
  .din1({{6{fac_fpx_sp_src_fx1_}},                             fpf_aoe0_fx1,         fpf_boe0_fx1        }),
  .dout({rs2_exp_qual0_fx1[54:52],   rs1_exp_qual0_fx1[54:52], i_rs1_snan_src_fx1,   i_rs2_snan_src_fx1  })
  );

fgu_fpf_dp_zero_macro__width_12 aze  (
  .din ({1'b0, rs1_cmp_din_fx1[62:55], rs1_exp_qual0_fx1[54:52]}),
  .dout(aze_fx1)
  );

fgu_fpf_dp_zero_macro__width_12 bze  (
  .din ({1'b0, fpf_rs2_cmp_din_fx1[62:55], rs2_exp_qual0_fx1[54:52]}),
  .dout(bze_fx1)
  );

fgu_fpf_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 nan  ( 
  .din0(fpf_aoe0_fx1),
  .din1(fpf_boe0_fx1),
  .sel0(fpf_azf0_fx1_),
  .sel1(fpf_bzf0_fx1_),
  .dout(nan_src_fx1)
  );

fgu_fpf_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 qnan  ( 
  .din0(fpf_azf0_fx1_),
  .din1(fpf_bzf0_fx1_),
  .sel0(i_rs1_snan_src_fx1),
  .sel1(i_rs2_snan_src_fx1),
  .dout(snan_src_fx1)
  );

fgu_fpf_dp_nand_macro__ports_4__width_1 twozeros  (
  .din0(fpf_azf0_fx1),
  .din1(fpf_bzf0_fx1),
  .din2(fpf_aze0_fx1),
  .din3(fpf_bze0_fx1),
  .dout(zero_eq_zero_fx1_)
  );

// ------------------------------------
// V9 fp compares (generate fcc)
// 
// fcc[1:0]  relation
// -------------------
//   00      rs1=rs2 (A=B)
//   01      rs1<rs2 (A<B, B>A)
//   10      rs1>rs2 (A>B, B<A)
//   11      NaN source(s)
//
// first qualify V9 swap determination (swap_blta) with sign bits (Sa,Sb)
// to generate true B<A (blta) for fcc usage
// 
// Sb  Sa  beqa  swap_blta  blta
// -----------------------------
//  0   0    x       0       0
//  0   1    0*      0       0
//  1   0    0*      0       1   (set blta if Sb>Sa)
//  1   1    0       0       1   (flip swap_blta if Sa=Sb=1 & B!=A)
//  1   1    1       0       0
//  0   0    x       1       1
//  0   1    0*      1       0   (clear blta if Sb not >= Sa)
//  1   0    0*      1       1
//  1   1    x       1       0   (flip swap_blta if Sa=Sb=1)
//
// * must be 0 by definition of beqa
// ------------------------------------

fgu_fpf_dp_inv_macro__width_3 cmp_i6  (
  .din ({cmp_swap_blta_fx1,
         fac_fcmpe_fx1,
         fpf_rs2_cmp_din_fx1[63]}),
  .dout({cmp_swap_blta_fx1_,
         fcmpe_fx1_,
         fpf_rs2_cmp_din_fx1_[63]})
  );

fgu_fpf_dp_nand_macro__ports_2__width_3 cmp_i7  (  // equiv function: width=1,ports=2,mux=aonpe,buffsel=none
  .din0({cmp_swap_blta_fx1_, cmp_swap_blta_fx1,    cmp_i7_1_fx1}),
  .din1({cmp_i8_fx1,         rs1_cmp_din_fx1_[63], cmp_i7_0_fx1}),
  .dout({cmp_i7_1_fx1,       cmp_i7_0_fx1,         cmp_blta_fx1})
  );

fgu_fpf_dp_nor_macro__ports_2__width_2 cmp_i8  (
  .din0({cmp_blta_fx1, fpf_rs2_cmp_din_fx1_[63]}),
  .din1({cmp_beqa_fx1, cmp_beqa_fx1        }),
  .dout({cmp_bgta_fx1,      // B>A = ~(B<A) & ~(B=A), not yet qual w/ nan source(s)
         cmp_i8_fx1})
  );

// ------------------------------------
// Mantissa swap muxes
// ------------------------------------

// produce mantissa with larger exp (man_le)

fgu_fpf_dp_msff_macro__mux_aope__ports_2__width_64 fx2_swp_le  (
  .scan_in(fx2_swp_le_scanin),
  .scan_out(fx2_swp_le_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din0(fad_rs1_fmt_fx1[63:0]),
  .din1(fad_rs2_fmt_fx1[63:0]),
  .sel0(cmp_swap_blta_fx1),   // if (B<A) then rs1=man_le
  .dout(man_le_fx2[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// produce mantissa with smaller exp (man_se)
fgu_fpf_dp_msff_macro__mux_aope__ports_3__width_64 fx2_swp_se  (
  .scan_in(fx2_swp_se_scanin),
  .scan_out(fx2_swp_se_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din0(fpf_rs2_cmp_din_fx1[63:0]),
  .din1(fad_rs2_fmt_fx1[63:0]),
  .din2(fad_rs1_fmt_fx1[63:0]),
  .sel0(rs2_rotate_sel_fx1[2]),  // FiTO(s,d) selects rt. justified rs2
  .sel1(cmp_swap_blta_fx1),      // if (B<A) then rs2=man_se
  .dout(man_se_fx2[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ----------------------------------------------------------------------------
//                               FX2 stage
// ----------------------------------------------------------------------------

fgu_fpf_dp_msff_macro__width_29 fx2_fcc  (
  .scan_in(fx2_fcc_scanin),
  .scan_out(fx2_fcc_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din ({cmp_bma_cout3_fx1, cmp_bma_cout2_fx1, cmp_bma_cout1_fx1, cmp_bma_cout0_fx1,
         cmp_eq30_fx1, cmp_eq2_fx1, cmp_eq1_fx1, cmp_eq0_fx1,
         nan_src_fx1, cmp_blta_fx1, cmp_bgta_fx1,
         zero_eq_zero_fx1_,
         fcmpe_fx1_, snan_src_fx1, fad_fsr_tem_fx1_b4, fac_fcmpe_fx1,
         i2f_sel_fx1[1:0], fpc_i2f_sel_fx1[3:2],     cmp_swap_blta_fx1,
         fac_fpx_sp_dest_fx1, fac_i2f_sel_e[1:0], fac_rs2_rotate_sel_e[4:0]}),
  .dout({fpf_b_gteq_a_fx2[3:0],
         fpf_b_eq_a_fx2[3:0],
         nan_src_fx2, cmp_blta_fx2, cmp_bgta_fx2,
         zero_eq_zero_fx2_,
         fcmpe_fx2_, snan_src_fx2, fsr_tem_nvm_fx2,        fcmpe_fx2,
         i2f_sel_fx2[1:0],     i2f_sel_fx2[3:2], fpf_cmp_swap_blta_fx2,
                 sp_dest_fx2,     i2f_sel_fx1[1:0],   rs2_rotate_sel_fx1[4:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// generate final V9 fp compares data result and valid
// - clear fcc valid if (nv & TEM)
// - clear fcc valid if flush (handled in FAC)
// ------------------------------------

fgu_fpf_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 cmp_fcc  ( 
  .din0({nan_src_fx2,  nan_src_fx2 }),  // NaN source(s) detected
  .din1({cmp_blta_fx2, cmp_bgta_fx2}),  // fcmp data
  .sel0(zero_eq_zero_fx2_),             // must clear fcc[1:0] if A=B=0 (+0=-0)
  .sel1(zero_eq_zero_fx2_),             // must clear fcc[1:0] if A=B=0 (+0=-0)
  .dout(fcc_fx2[1:0])
  );

fgu_fpf_dp_nand_macro__ports_4__width_3 cmp_i10  (
  .din0({fcmpe_fx2_,        fcmpe_fx2,          fcmp_nv_trap_fx2_ }),
  .din1({nan_src_fx2,       nan_src_fx2,        fcmpe_nv_trap_fx2_}),
  .din2({snan_src_fx2,      1'b1,               1'b1              }),
  .din3({fsr_tem_nvm_fx2,   fsr_tem_nvm_fx2,    1'b1              }),
  .dout({fcmp_nv_trap_fx2_, fcmpe_nv_trap_fx2_, v9cmp_nv_trap_fx2 })
  );

// ------------------------------------
// Aligner
//
// Note: i2f uses aligner to perform a left shift
// by organizing the aligner as a rotator.
// If i2f then bring shifted off bits into msb.
// If not i2f then shift 0s into msb.
// ------------------------------------

fgu_fpf_dp_inv_macro__width_63 inv_i2f  (
  .din ({man_se_byte_fx2[6:0],  man_se_fx2[55:0] }),
  .dout({man_se_byte_fx2_[6:0], man_se_fx2_[55:0]})
  );

fgu_fpf_dp_mux_macro__dmux_6x__mux_aonpe__ports_2__width_63 mux_i2f  (
  .din0({  man_se_byte_fx2[6:0],   man_se_fx2[55:0] }),
  .din1({  man_se_byte_fx2_[6:0],  man_se_fx2_[55:0]}),
  .sel0(i2f_sel_fx2[2]),
  .sel1(i2f_sel_fx2[3]),
  .dout({q_man_se_byte_fx2[6:0], q_man_se_fx2[55:0] })
  );

fgu_fpf_dp_nand_macro__ports_2__width_18 asel  (  // equiv function: width=6,ports=2,mux=aonpe,buffsel=none
  .din0({fpe_align_sel_fx2[5:0], fic_i2f_align_sel_fx2[5:0], asel_i0_fx2[5:0]         }),
  .din1({{6{i2f_sel_fx2[1]}},    {6{i2f_sel_fx2[0]}},        asel_i1_fx2[5:0]         }),
  .dout({asel_i0_fx2[5:0],       asel_i1_fx2[5:0],           merged_align_sel_fx2[5:0]})
  );

fgu_fpf_dp_buff_macro__dbuff_48x__width_1 muxtest_b_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_b_rep0)
  );

// byte mux
fgu_fpf_dp_mux_macro__mux_pgdec__ports_8__width_64 abyte  (
  .muxtst(tcu_muxtest_b_rep0),
  .din0(                         man_se_fx2[63:0] ),       // shift  0-bits
  .din1({q_man_se_fx2[7:0],     man_se_fx2[63:8]}),       // shift  8-bits
  .din2({q_man_se_fx2[15:0],     man_se_fx2[63:16]}),       // shift 16-bits
  .din3({q_man_se_fx2[23:0],     man_se_fx2[63:24]}),       // shift 24-bits
  .din4({q_man_se_fx2[31:0],     man_se_fx2[63:32]}),       // shift 32-bits
  .din5({q_man_se_fx2[39:0],     man_se_fx2[63:40]}),       // shift 40-bits
  .din6({q_man_se_fx2[47:0],     man_se_fx2[63:48]}),       // shift 48-bits
  .din7({q_man_se_fx2[55:0],     man_se_fx2[63:56]}),       // shift 56-bits
  .sel (merged_align_sel_fx2[5:3]),
  .dout(man_se_byte_fx2[63:0]),
  .test(test)
  );

// bit  mux
fgu_fpf_dp_mux_macro__mux_aodec__ports_8__width_64 abit  (
  .din0(                         man_se_byte_fx2[63:0] ),  // shift  0-bits
  .din1({q_man_se_byte_fx2[0],   man_se_byte_fx2[63:1]}),  // shift  1-bits
  .din2({q_man_se_byte_fx2[1:0], man_se_byte_fx2[63:2]}),  // shift  2-bits
  .din3({q_man_se_byte_fx2[2:0], man_se_byte_fx2[63:3]}),  // shift  3-bits
  .din4({q_man_se_byte_fx2[3:0], man_se_byte_fx2[63:4]}),  // shift  4-bits
  .din5({q_man_se_byte_fx2[4:0], man_se_byte_fx2[63:5]}),  // shift  5-bits
  .din6({q_man_se_byte_fx2[5:0], man_se_byte_fx2[63:6]}),  // shift  6-bits
  .din7({q_man_se_byte_fx2[6:0], man_se_byte_fx2[63:7]}),  // shift  7-bits
  .sel (merged_align_sel_fx2[2:0]),
  .dout(man_se_bit_fx2[63:0])
  );

//--------------------
// Aligner sticky
// - Must not capture G bit
//   SP format 1X.XX G bit is [40]
//   SP format 01.XX G bit is [39]
//   SP format 00.1X G bit is [38]
//   DP format 1X.XX G bit is [11]
//   DP format 01.XX G bit is [10]
//   DP format 00.1X G bit is [09]
//--------------------

fgu_fpf_dp_and_macro__ports_2__width_31 and_abyte_sticky  (
  .din0({   man_se_fx2[63:40],    man_se_byte_fx2[44:38]}),
  .din1({31{sp_dest_fx2}}),
  .dout({q2_man_se_fx2[63:40], q2_man_se_byte_fx2[44:38]})
  );

// byte sticky mux
fgu_fpf_dp_mux_macro__mux_aodec__ports_8__width_57 abyte_sticky  (
//                                                       SP uncertain G bits   DP uncertain G bits   //
  .din0({53'b0,                                          2'b0,                 2'b0             }),  // shift  0-bits
  .din1({41'b0, q2_man_se_fx2[45:40], man_se_fx2[16:11], q2_man_se_fx2[47:46], man_se_fx2[18:17]}),  // shift  8-bits
  .din2({25'b0, q2_man_se_fx2[53:40], man_se_fx2[24:11], q2_man_se_fx2[55:54], man_se_fx2[26:25]}),  // shift 16-bits
  .din3({ 9'b0, q2_man_se_fx2[61:40], man_se_fx2[32:11], q2_man_se_fx2[63:62], man_se_fx2[34:33]}),  // shift 24-bits
  .din4({       q2_man_se_fx2[63:41], man_se_fx2[40:11], 2'b0,                 man_se_fx2[42:41]}),  // shift 32-bits
  .din5({       q2_man_se_fx2[63:49], man_se_fx2[48:11], 2'b0,                 man_se_fx2[50:49]}),  // shift 40-bits
  .din6({       q2_man_se_fx2[63:57], man_se_fx2[56:11], 2'b0,                 man_se_fx2[58:57]}),  // shift 48-bits
  .din7({                             man_se_fx2[63:11], 2'b0,                 2'b0             }),  // shift 56-bits
  .sel (fpe_align_sel_fx2[5:3]),
  .dout({man_se_byte_sticky_fx2[52:0], byte_unsure_x_sp_fx2[1:0], byte_unsure_x_dp_fx2[1:0]})
  );

fgu_fpf_dp_buff_macro__dbuff_32x__width_1 muxtest_c_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_c_rep0)
  );

// bit  sticky mux
fgu_fpf_dp_mux_macro__mux_pgdec__ports_8__width_14 abit_sticky  (
  .muxtst(tcu_muxtest_c_rep0),
  .din0( 14'b0                                                    ),  // shift  0-bits
  .din1({12'b0, q2_man_se_byte_fx2[38:38], man_se_byte_fx2[9:9]}),  // shift  1-bits
  .din2({10'b0, q2_man_se_byte_fx2[39:38], man_se_byte_fx2[10:9]}),  // shift  2-bits
  .din3({ 8'b0, q2_man_se_byte_fx2[40:38], man_se_byte_fx2[11:9]}),  // shift  3-bits
  .din4({ 6'b0, q2_man_se_byte_fx2[41:38], man_se_byte_fx2[12:9]}),  // shift  4-bits
  .din5({ 4'b0, q2_man_se_byte_fx2[42:38], man_se_byte_fx2[13:9]}),  // shift  5-bits
  .din6({ 2'b0, q2_man_se_byte_fx2[43:38], man_se_byte_fx2[14:9]}),  // shift  6-bits
  .din7({       q2_man_se_byte_fx2[44:38], man_se_byte_fx2[15:9]}),  // shift  7-bits
  .sel (fpe_align_sel_fx2[2:0]),
  .dout(man_se_bit_sticky_fx2[13:0]),
  .test(test)
  );

fgu_fpf_dp_zero_macro__width_64 cmp_byte_sticky  (
  .din ({11'h000, man_se_byte_sticky_fx2[52:0]}),
  .dout(add_byte_sticky_fx2_l)
  );


// ----------------------------------------------------------------------------
//                               FX3 stage
// ----------------------------------------------------------------------------

fgu_fpf_dp_msff_macro__width_64 fx3_mle  (
  .scan_in(fx3_mle_scanin),
  .scan_out(fx3_mle_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (man_le_fx2[63:0]),
  .dout(man_le_fx3[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fpf_dp_msff_macro__width_64 fx3_mse  (
  .scan_in(fx3_mse_scanin),
  .scan_out(fx3_mse_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (man_se_bit_fx2[63:0]),
  .dout(man_se_bit_fx3[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fpf_dp_msff_macro__width_54 fx3_fcc  (
  .scan_in(fx3_fcc_scanin),
  .scan_out(fx3_fcc_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din ({    ma_cout_fx3,
         fpc_fadd_eac_enable_fx2,
         fpc_fp_cin00_fx2,
         fpc_cin00_fx2,
         fpc_cin16_48_fx2,
         fpc_cin32_fx2,
         fpc_prop16_48_fx2,
         fpc_prop32_fx2,
             prop32_fx3,
             man_se_byte_fx2[38:32],
             align_sticky_fx3_l,
                 fcc_fx2[1:0],
         fpc_mle_sel_fx2,
         fpc_mse_sel_fx2[2:0],
         fac_pre_fcc_vld_fx2[3:0],
         v9cmp_nv_trap_fx2,
         add_byte_sticky_fx2_l,
         man_se_bit_sticky_fx2[13:0],
             byte_unsure_x_sp_fx2[1:0],
             byte_unsure_x_dp_fx2[1:0],
             man_se_byte_fx2[6:0]}),
  .dout({fpf_ma_cout_fx4,
             fadd_eac_enable_fx3,
             fp_cin00_fx3,
             cin00_fx3,
             cin16_48_fx3,
             cin32_fx3,
             prop16_48_fx3,
             prop32_fx3,
             prop32_fx4,
         fpf_man_se_byte_fx3_b38_32[38:32],
         fpf_align_sticky_fx4_l,
         fgu_cmp_fcc_fx3[1:0],
             mle_sel_fx3,
             mse_sel_fx3[2:0],
             pre_fcc_vld_fx3[3:0],
         v9cmp_nv_trap_fx3,
         add_byte_sticky_fx3_l,
         man_se_bit_sticky_fx3[13:0],
         fpf_byte_unsure_x_sp_fx3[1:0],
         fpf_byte_unsure_x_dp_fx3[1:0],
         fpf_man_se_byte_fx3_b6_0[6:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fpf_dp_inv_macro__width_2 cmp_i12  (
  .din ({v9cmp_nv_trap_fx3,  fac_tlu_flush_fx3 }),
  .dout({v9cmp_nv_trap_fx3_, fac_tlu_flush_fx3_})
  );

// Note: for timing improvement this and_macro can be changed to a nor_macro,
//       however, be careful to avoid an unwanted assertion of fcc_vld_fx3 right after por 
fgu_fpf_dp_and_macro__ports_3__width_4 cmp_i11  (
  .din0(    pre_fcc_vld_fx3[3:0]  ),
  .din1({4{ v9cmp_nv_trap_fx3_  }}),
  .din2({4{ fac_tlu_flush_fx3_  }}),
  .dout(fgu_cmp_fcc_vld_fx3[3:0]  )
  );

// ------------------------------------
// Mle/Mse format muxes
// ------------------------------------

fgu_fpf_dp_inv_macro__width_64 inv_mse  (
  .din (man_se_bit_fx3[63:0]),
  .dout(man_se_bit_fx3_[63:0])
  );

fgu_fpf_dp_mux_macro__mux_pgpe__ports_2__width_64 mux_mle  (
  .din0(64'b0),
  .din1(man_le_fx3[63:0]),
  .sel0(mle_sel_fx3),
  .dout(final_man_le_fx3[63:0])
  );

fgu_fpf_dp_buff_macro__dbuff_48x__width_1 muxtest_d_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_d_rep0)
  );

fgu_fpf_dp_mux_macro__mux_pgpe__ports_4__width_64 mux_mse  (
  .muxtst(tcu_muxtest_d_rep0),
  .din0(64'b0),
  .din1(64'hffffffffffffffff),
  .din2(man_se_bit_fx3_[63:0]),
  .din3(man_se_bit_fx3[63:0]),
  .sel0(mse_sel_fx3[0]),
  .sel1(mse_sel_fx3[1]),
  .sel2(mse_sel_fx3[2]),
  .dout(final_man_se_fx3[63:0]),
  .test(test)
  );

// Note: can optimize to zero detect for improved timing
fgu_fpf_dp_cmp_macro__width_16 cmp_bit_sticky  (
  .din0({1'b1,                1'b1,                  14'b0                      }),
  .din1({fadd_eac_enable_fx3, add_byte_sticky_fx3_l, man_se_bit_sticky_fx3[13:0]}),
  .dout(align_sticky_fx3_l)
  );

fgu_fpf_dp_or_macro__ports_2__width_1 eac  ( 
  .din0(fp_cin00_fx3),
  .din1(align_sticky_fx3_l),
  .dout(final_fp_cin00_fx3)
  );

fgu_fpf_dp_nand_macro__ports_2__width_6 nand_final_cin16_48  ( 
  .din0({ma16_cout07_fx3,       cin16_48_fx3,          final_cin16_48_i0_fx3, ma16_cout47_fx3,       cin16_48_fx3,          final_cin16_48_i2_fx3}),
  .din1({prop16_48_fx3,         1'b1,                  final_cin16_48_i1_fx3, prop16_48_fx3,         1'b1,                  final_cin16_48_i3_fx3}),
  .dout({final_cin16_48_i0_fx3, final_cin16_48_i1_fx3, final_cin16_fx3,       final_cin16_48_i2_fx3, final_cin16_48_i3_fx3, final_cin48_fx3      })
  );

// ------------------------------------
// Main adder
// ------------------------------------

//fgu_ffa_cust ma (
//  .din0      (final_man_se_fx3[63:0]),
//  .din1      (final_man_le_fx3[63:0]),
//  .cin00     (final_fp_cin00_fx3    ),
//  .cin16_48  (    cin16_48_fx3      ),
//  .cin32     (    cin32_fx3         ),
//  .prop16_48 (    prop16_48_fx3     ),
//  .prop32    (    prop32_fx3        ),
//  .dout      (ma_sum_fx3[63:0]      ),
//  .cout64    (ma_cout_fx3           )
//  );

fgu_fpf_dp_cla_macro__width_16 ma16_0  (
  .din0(final_man_se_fx3[15:0]),
  .din1(final_man_le_fx3[15:0]),
  .cin (cin00_fx3),
  .dout(ma16_sum_fx3[15:0]),
  .cout(ma16_cout07_fx3)
  );

fgu_fpf_dp_cla_macro__width_16 ma16_1  (
  .din0(final_man_se_fx3[31:16]),
  .din1(final_man_le_fx3[31:16]),
  .cin (final_cin16_fx3),
  .dout(ma16_sum_fx3[31:16]),
  .cout(ma16_cout31_unused)
  );

fgu_fpf_dp_cla_macro__width_16 ma16_2  (
  .din0(final_man_se_fx3[47:32]),
  .din1(final_man_le_fx3[47:32]),
  .cin (cin32_fx3),
  .dout(ma16_sum_fx3[47:32]),
  .cout(ma16_cout47_fx3)
  );

fgu_fpf_dp_cla_macro__width_16 ma16_3  (
  .din0(final_man_se_fx3[63:48]),
  .din1(final_man_le_fx3[63:48]),
  .cin (final_cin48_fx3),
  .dout(ma16_sum_fx3[63:48]),
  .cout(ma16_cout63_unused)
  );

fgu_fpf_dp_cla_macro__width_64 ma64    (
  .din0(final_man_se_fx3[63:0]),
  .din1(final_man_le_fx3[63:0]),
  .cin (final_fp_cin00_fx3),
  .dout(ma64_sum_fx3[63:0]),
  .cout(ma_cout_fx3)
  );

// ----------------------------------------------------------------------------
//                               FX4 stage
// ----------------------------------------------------------------------------

fgu_fpf_dp_msff_macro__width_64 fx4_ma64_sum  (
  .scan_in(fx4_ma64_sum_scanin),
  .scan_out(fx4_ma64_sum_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (ma64_sum_fx3[63:0]),
  .dout(fpf_ma_sum_fx4[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fpf_dp_msff_macro__width_64 fx4_ma16_sum  (
  .scan_in(fx4_ma16_sum_scanin),
  .scan_out(fx4_ma16_sum_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (ma16_sum_fx3[63:0]),
  .dout(ma16_sum_fx4[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fpf_dp_mux_macro__mux_pgpe__ports_2__width_64 mux_ma_sum  (
  .din0(fpf_ma_sum_fx4[63:0]),
  .din1(ma16_sum_fx4[63:0]),
  .sel0(prop32_fx4),
  .dout(final_ma_sum_fx4[63:0])
  );

// ------------------------------------
// quiet the propagating NaN (set frac MSB=1)
// ------------------------------------

fgu_fpf_dp_or_macro__ports_2__width_1 qthenan  (
  .din0(final_ma_sum_fx4[62]),
  .din1(fpc_qthenan_fx4),
  .dout(ma_sum_quiet_fx4[62])
  );

// ----------------------------------------------------------------------------
//                               FX5 stage
// ----------------------------------------------------------------------------

fgu_fpf_dp_msff_macro__width_64 fx5_sum  (
  .scan_in(fx5_sum_scanin),
  .scan_out(fx5_sum_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din ({final_ma_sum_fx4[63], ma_sum_quiet_fx4[62], final_ma_sum_fx4[61:0]}),
  .dout(ma_sum_fx5[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fpf_dp_msff_macro__width_14 fx5_ma_fmt_sel  (
  .scan_in(fx5_ma_fmt_sel_scanin),
  .scan_out(fx5_ma_fmt_sel_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din ({fpf_rcout_fx5, fpc_int_res_sel_fx4[5:1], fdc_finish_int_early, fpc_ma_fmt_sel_fx4[4:0], fpy_fp_result_fx4_b63, fpc_sp_dest_fx4}),
  .dout({fpf_rcout_fb,      int_res_sel_fx5[5:1], int_res_sel_fx5[0],       ma_fmt_sel_fx5[4:0],     fp_result_fx5_b63,     sp_dest_fx5}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// Main adder output format mux
// - FPY fmul result enters norm/rnd here
// - SP inc position 40,
//   must pad bits [39:11] to propagate inc cin
// ------------------------------------

fgu_fpf_dp_buff_macro__dbuff_48x__width_1 muxtest_e_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_e_rep0)
  );

fgu_fpf_dp_mux_macro__mux_pgpe__ports_7__width_64 ma_fmt  (
  .muxtst(tcu_muxtest_e_rep0),
  .din0({      ma_sum_fx5[62:0], 1'b0          }),
  .din1({1'b1, ma_sum_fx5[63:1]                }),
  .din2(       ma_sum_fx5[63:0]                 ),
  .din3({1'b0, fgu_mul_result_fx5[63:12], 11'b0}),
  .din4({      fgu_mul_result_fx5[63:11], 11'b0}),
  .din5({      fgu_mul_result_fx5[63:11], 11'b0}),
  .din6({      fgu_mul_result_fx5[62:10], 11'b0}),
  .sel0(ma_fmt_sel_fx5[0]                       ),  // fadd/fsub 00.1X
  .sel1(ma_fmt_sel_fx5[1]                       ),  // fadd/fsub 1X.XX
  .sel2(ma_fmt_sel_fx5[2]                       ),  // default for non fmul
  .sel3(ma_fmt_sel_fx5[3]                       ),  // fmul 11.XX, Eint=Emin-2, denorm inter. result may rnd to norm
  .sel4(ma_fmt_sel_fx5[4]                       ),  // fmul 01.XX, Eint=Emin-1, denorm inter. result may rnd to norm
  .sel5(fp_result_fx5_b63                       ),  // fmul 1X.XX
  .dout(unnorm_inter_res_fx5[63:0]              ),
  .test(test)   //       X.XX
  );

fgu_fpf_dp_buff_macro__dbuff_48x__width_1 muxtest_f_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_f_rep0)
  );

fgu_fpf_dp_mux_macro__mux_pgpe__ports_8__width_29 ma_fmt_pad  (
  .muxtst(tcu_muxtest_f_rep0),
  .din0({1'b1, 28'hfffffff        }),
  .din1(       ma_sum_fx5[38:10]   ),
  .din2(       ma_sum_fx5[40:12]   ),
  .din3(       ma_sum_fx5[39:11]   ),
  .din4( fgu_mul_result_fx5[40:12] ),
  .din5( fgu_mul_result_fx5[39:11] ),
  .din6( fgu_mul_result_fx5[39:11] ),
  .din7( fgu_mul_result_fx5[38:10] ),
  .sel0(sp_dest_fx5                ),  // SP, pad bits [39:11]
  .sel1(ma_fmt_sel_fx5[0]          ),  // fadd/fsub 00.1X
  .sel2(ma_fmt_sel_fx5[1]          ),  // fadd/fsub 1X.XX
  .sel3(ma_fmt_sel_fx5[2]          ),  // default for non fmul
  .sel4(ma_fmt_sel_fx5[3]          ),  // fmul 11.XX, Eint=Emin-2, denorm inter. result may rnd to norm
  .sel5(ma_fmt_sel_fx5[4]          ),  // fmul 01.XX, Eint=Emin-1, denorm inter. result may rnd to norm
  .sel6(fp_result_fx5_b63          ),  // fmul 1X.XX
  .dout(pad_inc_fx5[39:11]         ),
  .test(test)
  );

// ------------------------------------
// Normalizer
// ------------------------------------

fgu_fpf_dp_buff_macro__dbuff_48x__width_1 muxtest_g_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_g_rep0)
  );

// byte mux
fgu_fpf_dp_mux_macro__mux_pgdec__ports_8__width_59 nbyte  (
  .muxtst(tcu_muxtest_g_rep0),
  .din0( unnorm_inter_res_fx5[62:4]        ),  // shift  0-bits
  .din1({unnorm_inter_res_fx5[54:0],  4'b0}),  // shift  8-bits
  .din2({unnorm_inter_res_fx5[46:0], 12'b0}),  // shift 16-bits
  .din3({unnorm_inter_res_fx5[38:0], 20'b0}),  // shift 24-bits
  .din4({unnorm_inter_res_fx5[30:0], 28'b0}),  // shift 32-bits
  .din5({unnorm_inter_res_fx5[22:0], 36'b0}),  // shift 40-bits
  .din6({unnorm_inter_res_fx5[14:0], 44'b0}),  // shift 48-bits
  .din7(                             59'b0 ),  // unused
  .sel (fic_norm_eadj_fx5[5:3]),
  .dout(norm_byte_fx5[62:4]),
  .test(test)
  );

fgu_fpf_dp_buff_macro__dbuff_48x__width_1 muxtest_h_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_h_rep0)
  );

// bit  mux
fgu_fpf_dp_mux_macro__mux_pgdec__ports_8__width_52 nbit  (
  .muxtst(tcu_muxtest_h_rep0),
  .din0(norm_byte_fx5[62:11]),  // shift  0-bits
  .din1(norm_byte_fx5[61:10]),  // shift  1-bits
  .din2(norm_byte_fx5[60:9]),  // shift  2-bits
  .din3(norm_byte_fx5[59:8]),  // shift  3-bits
  .din4(norm_byte_fx5[58:7]),  // shift  4-bits
  .din5(norm_byte_fx5[57:6]),  // shift  5-bits
  .din6(norm_byte_fx5[56:5]),  // shift  6-bits
  .din7(norm_byte_fx5[55:4]),  // shift  7-bits
  .sel (fic_norm_eadj_fx5[2:0]),
  .dout(norm_bit_fx5[62:11]),
  .test(test)
  );

// ------------------------------------
// Incrementer
//
// DP inc position 11
// SP inc position 40,
//    must pad bits [39:11] to propagate inc cin
// ------------------------------------

fgu_fpf_dp_increment_macro__width_64 minc  (
  .din ({11'b0, unnorm_inter_res_fx5[63:40], pad_inc_fx5[39:11]}),
  .cin (  1'b1),
  .dout({minc_unused[9:0], fpf_rcout_fx5, fpf_implied_bit_fx5, inc_inter_res_fx5[51:0]}),
  .cout( minc_unused[10])
  );

// ------------------------------------
// Norm/Round selection
// ------------------------------------

fgu_fpf_dp_mux_macro__mux_aope__ports_2__width_52 mux_nrd  (
  .din0(inc_inter_res_fx5[51:0]),
  .din1(norm_bit_fx5[62:11]),
  .sel0(fpc_rinc_sel_fx5),
  .dout(nrd_res_fx5[62:11])
  );

// ------------------------------------
// Integer output constant mux
// - FPY 8x16 result enters here
// ------------------------------------

fgu_fpf_dp_mux_macro__mux_aope__ports_5__width_64 idata  (
  .din0(64'h0000000000000000      ),
  .din1(64'h8000000000000000      ),
  .din2(64'h7fffffffffffffff      ),
  .din3(unnorm_inter_res_fx5[63:0]),  // vis parititioned add, F(s,d)TO(i,x)
  .din4(fgu_mul_result_fx5[63:0]  ),  // vis 8x16
  .sel0(fpc_int_sel_fx5[0]        ),
  .sel1(fpc_int_sel_fx5[1]        ),
  .sel2(fpc_int_sel_fx5[2]        ),
  .sel3(fpc_int_sel_fx5[3]        ),
  .dout(int_data_fx5[63:0]        )
  );

// ------------------------------------
// Integer/Float_Constant mux
// ------------------------------------

fgu_fpf_dp_msff_macro__mux_aope__ports_6__width_64 fb_int_fconst  (
  .scan_in(fb_int_fconst_scanin),
  .scan_out(fb_int_fconst_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din0({fpc_sign_fx5,  8'hff,          55'b0             }),  // SP inf
  .din1({fpc_sign_fx5, 11'b11111111111, 52'b0             }),  // DP inf
  .din2({fpc_sign_fx5,  8'hfe,          55'h7fffffffffffff}),  // SP max
  .din3({fpc_sign_fx5, 11'b11111111110, 52'hfffffffffffff }),  // DP max
  .din4({fpc_sign_fx5, 63'b0                              }),  // SP/DP zero
  .din5( int_data_fx5[63:0]                                ),
  .sel0(fpc_fconst_sel_fx5[0]),
  .sel1(fpc_fconst_sel_fx5[1]),
  .sel2(fpc_fconst_sel_fx5[2]),
  .sel3(fpc_fconst_sel_fx5[3]),
  .sel4(fpc_fconst_sel_fx5[4]),
  .dout(int_fconst_res_fb[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

// ------------------------------------
// EXU final result mux
// - FPY imul result enters here
// - FDD idiv result enters here
// ------------------------------------

fgu_fpf_dp_mux_macro__mux_aonpe__ports_6__width_64 exu_res  (
  .din0(fdd_result[63:0]                    ),  // idiv     result
  .din1(ma_sum_fx5[63:0]                    ),  // save/restore 64b add result
  .din2({31'b0, ma_sum_fx5[32:0]           }),  // mulscc   result
  .din3({57'b0, fgd_result_fx5[6:0]        }),  // popc     result
  .din4({60'b0, fpc_vis_cmp_result_fx5[3:0]}),  // vis fcmp result
  .din5(fgu_mul_result_fx5[63:0]            ),  // imul     result
  .sel0(int_res_sel_fx5[0]                  ),  // idiv
  .sel1(int_res_sel_fx5[1]                  ),  // save/restore
  .sel2(int_res_sel_fx5[2]                  ),  // mulscc
  .sel3(int_res_sel_fx5[3]                  ),  // popc
  .sel4(int_res_sel_fx5[4]                  ),  // vis fcmp
  .sel5(int_res_sel_fx5[5]                  ),  // imul
  .dout(int_result_fx5[63:0]                )   // pwr mgmt: aomux free zeros
  );

fgu_fpf_dp_buff_macro__width_64 buf_exu_res0  (
  .din (    int_result_fx5[63:0] ),
  .dout(    int_result0_fx5[63:0])
  );

fgu_fpf_dp_buff_macro__rep_1__width_64 buf_exu_res1  (
  .din (    int_result0_fx5[63:0]),
  .dout(fgu_exu_result_fx5[63:0] )
  );

fgu_fpf_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 sel_res  ( 
  .din0({fpc_ovf_if_rcout_fx5[1], fpc_ovf_if_rcout_fx5[0]}),
  .din1({fpc_result_sel_fx5[4],   fpc_result_sel_fx5[2]  }),
  .sel0(fpf_rcout_fx5),
  .sel1(1'b1),
  .dout({q_result_sel_fx5[4],     q_result_sel_fx5[2]    })
  );


// ----------------------------------------------------------------------------
//                               FB stage
// ----------------------------------------------------------------------------

fgu_fpf_dp_msff_macro__width_58 fb_nrd  (
  .scan_in(fb_nrd_scanin),
  .scan_out(fb_nrd_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din ({fpc_result_sel_fx5[5], q_result_sel_fx5[4], fpc_result_sel_fx5[3], q_result_sel_fx5[2], fpc_result_sel_fx5[1:0],
         nrd_res_fx5[62:11]}),
  .dout({result_sel_fb[5:0],
         nrd_res_fb[62:11]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fpf_dp_msff_macro__width_64 fb_fgd  (
  .scan_in(fb_fgd_scanin),
  .scan_out(fb_fgd_scanout),
  .clk (l2clk),
  .en  (main_clken),
  .din (fgd_result_fx5[63:0]),
  .dout(fgd_result_fb[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
  );

fgu_fpf_dp_or_macro__ports_2__width_2 or_min  (  // force result to min norm if needed
  .din0({fpc_den2nor_sp_fb,     fpc_den2nor_dp_fb    }),
  .din1({int_fconst_res_fb[55], int_fconst_res_fb[52]}),
  .dout({emin_sp_fb,            emin_dp_fb           }) 
  );

fgu_fpf_dp_buff_macro__dbuff_48x__width_1 muxtest_i_rep0  (
  .din (tcu_muxtest       ),
  .dout(tcu_muxtest_i_rep0)
  );

fgu_fpf_dp_mux_macro__mux_pgpe__ports_7__width_64 fb_res  (
  .muxtst(tcu_muxtest_i_rep0),
  .din0({32'b0, fgd_result_fb[63:32]                                          }),
  .din1(        fgd_result_fb[63:0]                                            ),
  .din2({32'b0, int_fconst_res_fb[63:56], emin_sp_fb, int_fconst_res_fb[54:32]}),
  .din3({32'b0, fpc_sign_fb, fpe_exp_res_fb[7:0],  nrd_res_fb[62:40]          }),
  .din4({       int_fconst_res_fb[63:56], emin_sp_fb, int_fconst_res_fb[54:53], emin_dp_fb, int_fconst_res_fb[51:0]}),
  .din5({       fpc_sign_fb, fpe_exp_res_fb[10:0], nrd_res_fb[62:11]          }),
  .din6({       fpc_sign_fb, fpe_exp_res_fb[7:0],  nrd_res_fb[62:40], 32'b0   }),
  .sel0(result_sel_fb[0]),  // FGA               rotate
  .sel1(result_sel_fb[1]),  // FGA
  .sel2(result_sel_fb[2]),  // 32b     int/const rotate
  .sel3(result_sel_fb[3]),  // SP                rotate
  .sel4(result_sel_fb[4]),  // 64b/32b int/const
  .sel5(result_sel_fb[5]),  // DP
                            // else: SP no rotate
  .dout(w1_result_fb[63:0]),
  .test(test)
  );

fgu_fpf_dp_buff_macro__width_64 buf_w1_result  (
  .din (    w1_result_fb[63:0]),
  .dout(fpf_w1_result_fb[63:0])
  );

// ------------------------------------
// ECC generation for w1 result (even word)
// ------------------------------------

fgu_fpf_dp_prty_macro__width_32 ecc_s1e7  (
  .din({1'b0,
  	w1_result_fb[62],
        1'b0,
  	w1_result_fb[60],
        1'b0,
	w1_result_fb[58:57],
        1'b0,
	w1_result_fb[55],
        1'b0,
	w1_result_fb[53],
        1'b0,
	w1_result_fb[51],
        1'b0,
	w1_result_fb[49],
        1'b0,
        w1_result_fb[47],
        1'b0,
	w1_result_fb[45],
        1'b0,
	w1_result_fb[43:42],
        1'b0,
	w1_result_fb[40],
        1'b0,
	w1_result_fb[38],
        1'b0,
	w1_result_fb[36:35],
        fec_w1_ecc_inject_fb[0],
	w1_result_fb[33:32]}),
  .dout(w1_synd_fb[7])
  );

fgu_fpf_dp_prty_macro__width_32 ecc_s1e8  (
  .din({w1_result_fb[63],
        2'b0,
  	w1_result_fb[60:59],
        1'b0,
	w1_result_fb[57:56],
        2'b0,
	w1_result_fb[53:52],
        2'b0,
	w1_result_fb[49:48],
        2'b0,
	w1_result_fb[45:44],
        1'b0,
	w1_result_fb[42:41],
        2'b0,
	w1_result_fb[38:37],
        1'b0,
	w1_result_fb[35:34],
        fec_w1_ecc_inject_fb[1],
	w1_result_fb[32]}),
  .dout(w1_synd_fb[8])
  );

fgu_fpf_dp_prty_macro__width_32 ecc_s1e9  (
  .din({w1_result_fb[63:61],
        3'b0,
	w1_result_fb[57:54],
        4'b0,
	w1_result_fb[49:46],
        3'b0,
	w1_result_fb[42:39],
        3'b0,
	w1_result_fb[35:33],
        fec_w1_ecc_inject_fb[2]}),
  .dout(w1_synd_fb[9])
  );

fgu_fpf_dp_prty_macro__width_16 ecc_s1e10  (
  .din({fec_w1_ecc_inject_fb[3],
	w1_result_fb[57:50],
	w1_result_fb[42:36]}),
  .dout(w1_synd_fb[10])
  );

fgu_fpf_dp_prty_macro__width_16 ecc_s1e11  (
  .din({fec_w1_ecc_inject_fb[4],
	w1_result_fb[57:43]}),
  .dout(w1_synd_fb[11])
  );

fgu_fpf_dp_prty_macro__width_8 ecc_s1e12  (
  .din({w1_result_fb[63:58],
        1'b0,
        fec_w1_ecc_inject_fb[5]}),
  .dout(w1_synd_fb[12])
  );

fgu_fpf_dp_prty_macro__width_32 ecc_s1e13  (
  .din({2'b0,
  	w1_result_fb[61],
        1'b0,
  	w1_result_fb[59:58],
        1'b0,
	w1_result_fb[56:55],
        1'b0,
	w1_result_fb[53],
        2'b0,
	w1_result_fb[50:49],
        2'b0,
	w1_result_fb[46],
        1'b0,
	w1_result_fb[44:42],
        2'b0,
	w1_result_fb[39],
        1'b0,
	w1_result_fb[37:36],
        fec_w1_ecc_inject_fb[6],
	w1_result_fb[34:32]}),
  .dout(w1_synd_fb[13])
  );

fgu_fpf_dp_buff_macro__width_7 buf_ecce  (
  .din (    w1_synd_fb[13:7]),
  .dout(fpf_w1_synd_fb[13:7])
  );

// ------------------------------------
// ECC generation for w1 result (odd word)
// ------------------------------------

fgu_fpf_dp_prty_macro__width_32 ecc_s1o0  (
  .din({fec_w1_ecc_inject_fb[0],
  	w1_result_fb[30],
        1'b0,
  	w1_result_fb[28],
        1'b0,
	w1_result_fb[26:25],
        1'b0,
	w1_result_fb[23],
        1'b0,
	w1_result_fb[21],
        1'b0,
	w1_result_fb[19],
        1'b0,
	w1_result_fb[17],
        1'b0,
        w1_result_fb[15],
        1'b0,
	w1_result_fb[13],
        1'b0,
	w1_result_fb[11:10],
        1'b0,
	w1_result_fb[8],
        1'b0,
	w1_result_fb[6],
        1'b0,
	w1_result_fb[4:3],
        1'b0,
	w1_result_fb[1:0]}),
  .dout(w1_synd_fb[0])
  );

fgu_fpf_dp_prty_macro__width_32 ecc_s1o1  (
  .din({w1_result_fb[31],
        fec_w1_ecc_inject_fb[1],
        1'b0,
  	w1_result_fb[28:27],
        1'b0,
	w1_result_fb[25:24],
        2'b0,
	w1_result_fb[21:20],
        2'b0,
	w1_result_fb[17:16],
        2'b0,
	w1_result_fb[13:12],
        1'b0,
	w1_result_fb[10:9],
        2'b0,
	w1_result_fb[6:5],
        1'b0,
	w1_result_fb[3:2],
        1'b0,
	w1_result_fb[0]}),
  .dout(w1_synd_fb[1])
  );

fgu_fpf_dp_prty_macro__width_32 ecc_s1o2  (
  .din({w1_result_fb[31:29],
        fec_w1_ecc_inject_fb[2],
        2'b0,
	w1_result_fb[25:22],
        4'b0,
	w1_result_fb[17:14],
        3'b0,
	w1_result_fb[10:7],
        3'b0,
	w1_result_fb[3:1],
        1'b0}),
  .dout(w1_synd_fb[2])
  );

fgu_fpf_dp_prty_macro__width_16 ecc_s1o3  (
  .din({fec_w1_ecc_inject_fb[3],
	w1_result_fb[25:18],
	w1_result_fb[10:4]}),
  .dout(w1_synd_fb[3])
  );

fgu_fpf_dp_prty_macro__width_16 ecc_s1o4  (
  .din({fec_w1_ecc_inject_fb[4],
	w1_result_fb[25:11]}),
  .dout(w1_synd_fb[4])
  );

fgu_fpf_dp_prty_macro__width_8 ecc_s1o5  (
  .din({fec_w1_ecc_inject_fb[5],
        1'b0,
        w1_result_fb[31:26]}),
  .dout(w1_synd_fb[5])
  );

fgu_fpf_dp_prty_macro__width_32 ecc_s1o6  (
  .din({fec_w1_ecc_inject_fb[6],
        1'b0,
  	w1_result_fb[29],
        1'b0,
  	w1_result_fb[27:26],
        1'b0,
	w1_result_fb[24:23],
        1'b0,
	w1_result_fb[21],
        2'b0,
	w1_result_fb[18:17],
        2'b0,
	w1_result_fb[14],
        1'b0,
	w1_result_fb[12:10],
        2'b0,
	w1_result_fb[7],
        1'b0,
	w1_result_fb[5:4],
        1'b0,
	w1_result_fb[2:0]}),
  .dout(w1_synd_fb[6])
  );

fgu_fpf_dp_buff_macro__width_7 buf_ecco  (
  .din (    w1_synd_fb[6:0]),
  .dout(fpf_w1_synd_fb[6:0])
  );


// fixscan start:
assign fx2_swp_le_scanin         = scan_in                  ;
assign fx2_swp_se_scanin         = fx2_swp_le_scanout       ;
assign fx2_fcc_scanin            = fx2_swp_se_scanout       ;
assign fx3_mle_scanin            = fx2_fcc_scanout          ;
assign fx3_mse_scanin            = fx3_mle_scanout          ;
assign fx3_fcc_scanin            = fx3_mse_scanout          ;
assign fx4_ma64_sum_scanin       = fx3_fcc_scanout          ;
assign fx4_ma16_sum_scanin       = fx4_ma64_sum_scanout     ;
assign fx5_sum_scanin            = fx4_ma16_sum_scanout     ;
assign fx5_ma_fmt_sel_scanin     = fx5_sum_scanout          ;
assign fb_nrd_scanin             = fx5_ma_fmt_sel_scanout   ;
assign fb_int_fconst_scanin      = fb_nrd_scanout           ;
assign fb_fgd_scanin             = fb_int_fconst_scanout    ;
assign scan_out                  = fb_fgd_scanout           ;
// fixscan end:
endmodule  // fgu_fpf_dp


//
//   buff macro
//
//


module fgu_fpf_dp_buff_macro__dbuff_32x__rep_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgpe__ports_2__width_32 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;
  output [31:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(32)  d0_0 (
  .sel(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpf_dp_buff_macro__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__dmux_6x__mux_aonpe__ports_4__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  output [63:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpf_dp_buff_macro__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpf_dp_inv_macro__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


inv #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   cla macro
//
//


module fgu_fpf_dp_cla_macro__width_16 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [15:0] din0;
  input [15:0] din1;
  output [15:0] dout;
  output cout;


cla #(16)  m0_0 (
.cin(cin),
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout[15:0]),
.cout(cout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fpf_dp_cmp_macro__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output dout;


cmp #(16)  m0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout)
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module fgu_fpf_dp_nor_macro__ports_2__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


nor2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fpf_dp_nand_macro__ports_4__width_4 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  input [3:0] din2;
  input [3:0] din3;
  output [3:0] dout;


nand4 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.in2(din2[3:0]),
.in3(din3[3:0]),
.out(dout[3:0])
);


endmodule


//
//   xnor macro for ports = 2,3
//
//


module fgu_fpf_dp_xnor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xnor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpf_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module fgu_fpf_dp_or_macro__ports_2__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


or2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fpf_dp_and_macro__ports_4__width_2 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  input [1:0] din2;
  input [1:0] din3;
  output [1:0] dout;


and4 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.in2(din2[1:0]),
.in3(din3[1:0]),
.out(dout[1:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fpf_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fpf_dp_zero_macro__width_64 (
  din, 
  dout);
  input [63:0] din;
  output dout;


zero #(64)  m0_0 (
.in(din[63:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module fgu_fpf_dp_buff_macro__width_7 (
  din, 
  dout);
  input [6:0] din;
  output [6:0] dout;


buff #(7)  d0_0 (
.in(din[6:0]),
.out(dout[6:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpf_dp_inv_macro__width_6 (
  din, 
  dout);
  input [5:0] din;
  output [5:0] dout;


inv #(6)  d0_0 (
.in(din[5:0]),
.out(dout[5:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module fgu_fpf_dp_or_macro__ports_2__width_6 (
  din0, 
  din1, 
  dout);
  input [5:0] din0;
  input [5:0] din1;
  output [5:0] dout;


or2 #(6)  d0_0 (
.in0(din0[5:0]),
.in1(din1[5:0]),
.out(dout[5:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fpf_dp_cmp_macro__width_12 (
  din0, 
  din1, 
  dout);
  input [11:0] din0;
  input [11:0] din1;
  output dout;


cmp #(12)  m0_0 (
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout)
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fpf_dp_and_macro__ports_2__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


and2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module fgu_fpf_dp_zero_macro__width_12 (
  din, 
  dout);
  input [11:0] din;
  output dout;


zero #(12)  m0_0 (
.in(din[11:0]),
.out(dout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  output [0:0] dout;


mux2s #(1)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
.dout(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fpf_dp_nand_macro__ports_4__width_1 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  input [0:0] din3;
  output [0:0] dout;


nand4 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.in3(din3[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpf_dp_inv_macro__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fpf_dp_nand_macro__ports_2__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


nand2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module fgu_fpf_dp_nor_macro__ports_2__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


nor2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_msff_macro__mux_aope__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_msff_macro__mux_aope__ports_3__width_64 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_msff_macro__width_29 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [27:0] so;

  input [28:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [28:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(29)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[28:0]),
.si({scan_in,so[27:0]}),
.so({so[27:0],scan_out}),
.q(dout[28:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [1:0] din0;
  input sel0;
  input [1:0] din1;
  input sel1;
  output [1:0] dout;


mux2s #(2)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[1:0]),
  .in1(din1[1:0]),
.dout(dout[1:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fpf_dp_nand_macro__ports_4__width_3 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  input [2:0] din3;
  output [2:0] dout;


nand4 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.in2(din2[2:0]),
.in3(din3[2:0]),
.out(dout[2:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpf_dp_inv_macro__width_63 (
  din, 
  dout);
  input [62:0] din;
  output [62:0] dout;


inv #(63)  d0_0 (
.in(din[62:0]),
.out(dout[62:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__dmux_6x__mux_aonpe__ports_2__width_63 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [62:0] din0;
  input sel0;
  input [62:0] din1;
  input sel1;
  output [62:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(63)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[62:0]),
  .in1(din1[62:0]),
.dout(dout[62:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fpf_dp_nand_macro__ports_2__width_18 (
  din0, 
  din1, 
  dout);
  input [17:0] din0;
  input [17:0] din1;
  output [17:0] dout;


nand2 #(18)  d0_0 (
.in0(din0[17:0]),
.in1(din1[17:0]),
.out(dout[17:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpf_dp_buff_macro__dbuff_48x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgdec__ports_8__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [63:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_aodec__ports_8__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input [2:0] sel;
  output [63:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fpf_dp_and_macro__ports_2__width_31 (
  din0, 
  din1, 
  dout);
  input [30:0] din0;
  input [30:0] din1;
  output [30:0] dout;


and2 #(31)  d0_0 (
.in0(din0[30:0]),
.in1(din1[30:0]),
.out(dout[30:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_aodec__ports_8__width_57 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [56:0] din0;
  input [56:0] din1;
  input [56:0] din2;
  input [56:0] din3;
  input [56:0] din4;
  input [56:0] din5;
  input [56:0] din6;
  input [56:0] din7;
  input [2:0] sel;
  output [56:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(57)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[56:0]),
  .in1(din1[56:0]),
  .in2(din2[56:0]),
  .in3(din3[56:0]),
  .in4(din4[56:0]),
  .in5(din5[56:0]),
  .in6(din6[56:0]),
  .in7(din7[56:0]),
.dout(dout[56:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpf_dp_buff_macro__dbuff_32x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgdec__ports_8__width_14 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [13:0] din0;
  input [13:0] din1;
  input [13:0] din2;
  input [13:0] din3;
  input [13:0] din4;
  input [13:0] din5;
  input [13:0] din6;
  input [13:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [13:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(14)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[13:0]),
  .in1(din1[13:0]),
  .in2(din2[13:0]),
  .in3(din3[13:0]),
  .in4(din4[13:0]),
  .in5(din5[13:0]),
  .in6(din6[13:0]),
  .in7(din7[13:0]),
.dout(dout[13:0]),
  .muxtst(muxtst)
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_msff_macro__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_msff_macro__width_54 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [52:0] so;

  input [53:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [53:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(54)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[53:0]),
.si({scan_in,so[52:0]}),
.so({so[52:0],scan_out}),
.q(dout[53:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpf_dp_inv_macro__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


inv #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module fgu_fpf_dp_and_macro__ports_3__width_4 (
  din0, 
  din1, 
  din2, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  input [3:0] din2;
  output [3:0] dout;


and3 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.in2(din2[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgpe__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(64)  d0_0 (
  .sel(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgpe__ports_4__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input sel0;
  input sel1;
  input sel2;
  input muxtst;
  input test;
  output [63:0] dout;


cl_dp1_penc4_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
  .test(test)
);

mux4 #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0]),
  .muxtst(muxtst)
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module fgu_fpf_dp_or_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module fgu_fpf_dp_nand_macro__ports_2__width_6 (
  din0, 
  din1, 
  dout);
  input [5:0] din0;
  input [5:0] din1;
  output [5:0] dout;


nand2 #(6)  d0_0 (
.in0(din0[5:0]),
.in1(din1[5:0]),
.out(dout[5:0])
);


endmodule


//
//   cla macro
//
//


module fgu_fpf_dp_cla_macro__width_64 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;
  output cout;


cla #(64)  m0_0 (
.cin(cin),
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0]),
.cout(cout)
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_msff_macro__width_14 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [12:0] so;

  input [13:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [13:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgpe__ports_7__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input muxtst;
  input test;
  output [63:0] dout;


cl_dp1_penc7_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
  .test(test)
);

mux7 #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
.dout(dout[63:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgpe__ports_8__width_29 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [28:0] din0;
  input [28:0] din1;
  input [28:0] din2;
  input [28:0] din3;
  input [28:0] din4;
  input [28:0] din5;
  input [28:0] din6;
  input [28:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;
  input muxtst;
  input test;
  output [28:0] dout;


cl_dp1_penc8_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(29)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[28:0]),
  .in1(din1[28:0]),
  .in2(din2[28:0]),
  .in3(din3[28:0]),
  .in4(din4[28:0]),
  .in5(din5[28:0]),
  .in6(din6[28:0]),
  .in7(din7[28:0]),
.dout(dout[28:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgdec__ports_8__width_59 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [58:0] din0;
  input [58:0] din1;
  input [58:0] din2;
  input [58:0] din3;
  input [58:0] din4;
  input [58:0] din5;
  input [58:0] din6;
  input [58:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [58:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(59)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[58:0]),
  .in1(din1[58:0]),
  .in2(din2[58:0]),
  .in3(din3[58:0]),
  .in4(din4[58:0]),
  .in5(din5[58:0]),
  .in6(din6[58:0]),
  .in7(din7[58:0]),
.dout(dout[58:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_pgdec__ports_8__width_52 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [51:0] din0;
  input [51:0] din1;
  input [51:0] din2;
  input [51:0] din3;
  input [51:0] din4;
  input [51:0] din5;
  input [51:0] din6;
  input [51:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [51:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(52)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[51:0]),
  .in1(din1[51:0]),
  .in2(din2[51:0]),
  .in3(din3[51:0]),
  .in4(din4[51:0]),
  .in5(din5[51:0]),
  .in6(din6[51:0]),
  .in7(din7[51:0]),
.dout(dout[51:0]),
  .muxtst(muxtst)
);


endmodule


//
//   increment macro 
//
//


module fgu_fpf_dp_increment_macro__width_64 (
  din, 
  cin, 
  dout, 
  cout);
  input [63:0] din;
  input cin;
  output [63:0] dout;
  output cout;


incr #(64)  m0_0 (
.cin(cin),
.in(din[63:0]),
.out(dout[63:0]),
.cout(cout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_aope__ports_2__width_52 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [51:0] din0;
  input [51:0] din1;
  input sel0;
  output [51:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(52)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[51:0]),
  .in1(din1[51:0]),
.dout(dout[51:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_aope__ports_5__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  output [63:0] dout;


cl_dp1_penc5_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_msff_macro__mux_aope__ports_6__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc6_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5)
);

mux6s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_mux_macro__mux_aonpe__ports_6__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;
  input [63:0] din5;
  input sel5;
  output [63:0] dout;


cl_dp1_muxbuff6_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5)
);
mux6s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpf_dp_buff_macro__rep_1__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpf_dp_msff_macro__width_58 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [56:0] so;

  input [57:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [57:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(58)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[57:0]),
.si({scan_in,so[56:0]}),
.so({so[56:0],scan_out}),
.q(dout[57:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module fgu_fpf_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module fgu_fpf_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module fgu_fpf_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_fpy_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_fpy_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  scan_out, 
  mul_clken_rep0, 
  mul_clken_rep01, 
  spu_fgu_rs1_e, 
  spu_fgu_rs2_e, 
  fad_rs1_fmt_fx1_rep0, 
  fad_rs2_fmt_fx1_rep0, 
  fad_rs2_fmt_fx1_rep1, 
  fac_xr_mode_fx1, 
  fac_rs1_sel_fx1, 
  fac_rs2_sel_fx1, 
  fac_8x16_rnd_fx3, 
  fac_scff_sel_fx3, 
  fac_accum_sel_fx3, 
  fac_result_sel_fx4, 
  fac_ma_result_en_fx4, 
  fgu_mul_result_fx5, 
  fpy_sticky_dp_fx5, 
  fpy_sticky_sp_fx5, 
  fpy_fp_result_fx4_b63, 
  fpy_xicc_z_fx5, 
  fgu_accum_b0_fx5);
wire stop;
wire test;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire i_spu_rs1_ff_scanin;
wire i_spu_rs1_ff_scanout;
wire [63:0] spu_fgu_rs1_fx1;
wire i_spu_rs2_ff_scanin;
wire i_spu_rs2_ff_scanout;
wire [63:0] spu_fgu_rs2_fx1;
wire [63:15] rs2_fx1_ebf;
wire xr_mode_fx1_;
wire [1:0] xr_mode_fx1_bf;
wire tcu_muxtest_a_rep0;
wire [63:0] ma_result_ff;
wire [12:0] rs1_fmt_a0;
wire [18:0] rs1_fmt_a1;
wire [18:0] rs1_fmt_a2;
wire [18:0] rs1_fmt_a3;
wire [4:0] be00;
wire [31:0] be_pout;
wire [31:0] be_hout;
wire [4:0] be01;
wire [4:0] be02;
wire [4:0] be03;
wire [4:0] be04;
wire [4:0] be05;
wire [4:0] be06;
wire [4:0] be07;
wire [4:0] be08;
wire [4:0] be09;
wire [4:0] be10;
wire [4:0] be11;
wire [4:0] be12;
wire [4:0] be13;
wire [4:0] be14;
wire [4:0] be15;
wire [4:0] be16;
wire [4:0] be17;
wire [4:0] be18;
wire [4:0] be19;
wire [4:0] be20;
wire [4:0] be21;
wire [4:0] be22;
wire [4:0] be23;
wire [4:0] be24;
wire [4:0] be25;
wire [4:0] be26;
wire [4:0] be27;
wire [4:0] be28;
wire [4:0] be29;
wire [4:0] be30;
wire [4:0] be31;
wire [5:0] i_be32_unused;
wire be32_b0;
wire [64:0] rs2_3x_fx1;
wire i_3x_ff_scanin;
wire i_3x_ff_scanout;
wire [64:0] rs2_3x_ff;
wire [64:0] rs2_3x;
wire i_a3_be_ff_scanin;
wire i_a3_be_ff_scanout;
wire a3_xr_mode_fx2_;
wire [31:0] be_pout_ff;
wire [4:0] be_ff08;
wire [4:0] be_ff07;
wire [4:0] be_ff06;
wire [4:0] be_ff05;
wire [4:0] be_ff04;
wire [4:0] be_ff03;
wire [4:0] be_ff02;
wire [4:0] be_ff01;
wire [4:0] be_ff00;
wire [31:0] be_hout_ff;
wire [63:15] rs2_fx1_ebf3;
wire i_a3_rs2_ff_scanin;
wire i_a3_rs2_ff_scanout;
wire [63:0] a3_rs2_ff;
wire [63:0] a3_rs2;
wire [63:0] a3_rs2_;
wire [67:0] bm00;
wire [68:0] bm01;
wire [70:2] bm02;
wire [72:4] bm03;
wire [74:6] bm04;
wire [76:8] bm05;
wire [78:10] bm06;
wire [80:12] bm07;
wire [82:14] bm08;
wire [69:1] a3_csa1_1_c;
wire [70:0] a3_csa1_1_s;
wire [75:7] a3_csa1_2_c;
wire [76:4] a3_csa1_2_s;
wire [81:13] a3_csa1_3_c;
wire [82:10] a3_csa1_3_s;
wire [77:5] a3_csa2_1_c;
wire [82:0] a3_csa2_1_s;
wire [76:8] a3_csa2_2_c;
wire [81:1] a3_csa2_2_s;
wire a3_csa3_1_unused;
wire [82:2] a3_csa3_1_c;
wire [82:0] a3_csa3_1_s;
wire i_a3_s_ff_a_scanin;
wire i_a3_s_ff_a_scanout;
wire [82:0] a3_csa3_1_s_ff;
wire i_a3_s_ff_b_scanin;
wire i_a3_s_ff_b_scanout;
wire i_a3_c_ff_a_scanin;
wire i_a3_c_ff_a_scanout;
wire [82:2] a3_csa3_1_c_ff;
wire i_a3_c_ff_b_scanin;
wire i_a3_c_ff_b_scanout;
wire [100:16] a2_csa2_3_s;
wire [98:0] a32_xr4_1;
wire i_a32_x_ff_a_scanin;
wire i_a32_x_ff_a_scanout;
wire [98:0] a32_xr_ff;
wire i_a32_x_ff_b_scanin;
wire i_a32_x_ff_b_scanout;
wire i_a2_be_ff_a_scanin;
wire i_a2_be_ff_a_scanout;
wire a2_xr_mode_fx2_;
wire [4:0] be_ff17;
wire [4:0] be_ff16;
wire i_a2_be_ff_b_scanin;
wire i_a2_be_ff_b_scanout;
wire [4:0] be_ff15;
wire [4:0] be_ff14;
wire [4:0] be_ff13;
wire [4:0] be_ff12;
wire [4:0] be_ff11;
wire [4:0] be_ff10;
wire [4:0] be_ff09;
wire [63:31] rs2_fx1_ebf2;
wire i_a2_rs2_ff_scanin;
wire i_a2_rs2_ff_scanout;
wire [63:0] a2_rs2_ff;
wire [63:0] a2_rs2;
wire [63:0] a2_rs2_;
wire [84:16] bm09;
wire [86:18] bm10;
wire [88:20] bm11;
wire [90:22] bm12;
wire [92:24] bm13;
wire [94:26] bm14;
wire [96:28] bm15;
wire [98:30] bm16;
wire [100:32] bm17;
wire [87:19] a2_csa1_4_c;
wire [88:16] a2_csa1_4_s;
wire [93:25] a2_csa1_5_c;
wire [94:22] a2_csa1_5_s;
wire [99:31] a2_csa1_6_c;
wire [100:28] a2_csa1_6_s;
wire [95:23] a2_csa2_3_c;
wire [94:26] a2_csa2_4_c;
wire [99:19] a2_csa2_4_s;
wire a2_csa3_2_unused;
wire [100:20] a2_csa3_2_c;
wire [100:16] a2_csa3_2_s;
wire i_a2_s_ff_a_scanin;
wire i_a2_s_ff_a_scanout;
wire [100:16] a2_csa3_2_s_ff;
wire i_a2_s_ff_b_scanin;
wire i_a2_s_ff_b_scanout;
wire i_a2_c_ff_a_scanin;
wire i_a2_c_ff_a_scanout;
wire [100:20] a2_csa3_2_c_ff;
wire i_a2_c_ff_b_scanin;
wire i_a2_c_ff_b_scanout;
wire i_a1_be_ff_scanin;
wire i_a1_be_ff_scanout;
wire a1_xr_mode_fx2_;
wire [4:0] be_ff26;
wire [4:0] be_ff25;
wire [4:0] be_ff24;
wire [4:0] be_ff23;
wire [4:0] be_ff22;
wire [4:0] be_ff21;
wire [4:0] be_ff20;
wire [4:0] be_ff19;
wire [4:0] be_ff18;
wire [63:47] rs2_fx1_ebf1;
wire i_a1_rs2_ff_scanin;
wire i_a1_rs2_ff_scanout;
wire [63:0] a1_rs2_ff;
wire [63:0] a1_rs2;
wire [63:0] a1_rs2_;
wire [102:34] bm18;
wire [104:36] bm19;
wire [106:38] bm20;
wire [108:40] bm21;
wire [110:42] bm22;
wire [112:44] bm23;
wire [114:46] bm24;
wire [116:48] bm25;
wire [118:50] bm26;
wire [105:37] a1_csa1_7_c;
wire [106:34] a1_csa1_7_s;
wire [111:43] a1_csa1_8_c;
wire [112:40] a1_csa1_8_s;
wire [117:49] a1_csa1_9_c;
wire [118:46] a1_csa1_9_s;
wire [113:41] a1_csa2_5_c;
wire [118:34] a1_csa2_5_s;
wire [112:44] a1_csa2_6_c;
wire [117:37] a1_csa2_6_s;
wire a1_csa3_3_unused;
wire [118:38] a1_csa3_3_c;
wire [118:34] a1_csa3_3_s;
wire i_a1_s_ff_a_scanin;
wire i_a1_s_ff_a_scanout;
wire [118:34] a1_csa3_3_s_ff;
wire i_a1_s_ff_b_scanin;
wire i_a1_s_ff_b_scanout;
wire i_a1_c_ff_a_scanin;
wire i_a1_c_ff_a_scanout;
wire [118:38] a1_csa3_3_c_ff;
wire i_a1_c_ff_b_scanin;
wire i_a1_c_ff_b_scanout;
wire [126:54] a0_xr_in;
wire [126:36] a10_xr4_2;
wire i_a10_x_ff_a_scanin;
wire i_a10_x_ff_a_scanout;
wire [126:36] a10_xr_ff;
wire i_a10_x_ff_b_scanin;
wire i_a10_x_ff_b_scanout;
wire i_a0_be_ff_scanin;
wire i_a0_be_ff_scanout;
wire a0_xr_mode_fx2_;
wire be_ff32_b0;
wire [4:0] be_ff31;
wire [4:0] be_ff30;
wire [4:0] be_ff29;
wire [4:0] be_ff28;
wire [4:0] be_ff27;
wire [63:47] rs2_fx1_ebf0;
wire i_a0_rs2_ff_scanin;
wire i_a0_rs2_ff_scanout;
wire [63:0] a0_rs2_ff;
wire [63:0] a0_rs2;
wire [63:0] a0_rs2_;
wire [120:52] bm27;
wire [122:54] bm28;
wire [124:56] bm29;
wire [126:58] bm30;
wire [127:60] bm31;
wire [135:62] bm32;
wire [123:55] a0_csa2_7_c;
wire [124:52] a0_csa2_7_s;
wire [128:61] a0_csa2_8_c;
wire [135:58] a0_csa2_8_s;
wire a0_csa3_4_unused;
wire [129:56] a0_csa3_4_c;
wire [135:52] a0_csa3_4_s;
wire i_a0_s_ff_a_scanin;
wire i_a0_s_ff_a_scanout;
wire [135:52] a0_csa3_4_s_ff;
wire i_a0_s_ff_b_scanin;
wire i_a0_s_ff_b_scanout;
wire i_a0_c_ff_a_scanin;
wire i_a0_c_ff_a_scanout;
wire [129:56] a0_csa3_4_c_ff;
wire i_a0_c_ff_b_scanin;
wire i_a0_c_ff_b_scanout;
wire [6:2] accum_sel_fx4;
wire accum_sel_fx4_b0;
wire a4_8x16csa4_1_unused;
wire [31:2] a4_8x16csa4_1_c;
wire [31:0] a4_8x16csa4_1_s;
wire a4_8x16csa4_2_unused;
wire [49:20] a4_8x16csa4_2_c;
wire [49:18] a4_8x16csa4_2_s;
wire a4_8x16csa4_3_unused;
wire [67:38] a4_8x16csa4_3_c;
wire [67:36] a4_8x16csa4_3_s;
wire a4_8x16csa4_4_unused;
wire [85:56] a4_8x16csa4_4_c;
wire [85:54] a4_8x16csa4_4_s;
wire [126:0] a4_xr5_1;
wire a4_csa4_1b_cout;
wire a4_csa4_1a_unused;
wire [101:3] a4_csa4_1_c;
wire [100:0] a4_csa4_1_s;
wire a4_csa4_2_unused;
wire [130:39] a4_csa4_2_c;
wire [135:34] a4_csa4_2_s;
wire a4_csa5_1b_cout;
wire a4_csa5_1a_unused;
wire [131:4] a4_csa5_1_c;
wire [135:0] a4_csa5_1_s;
wire i_a4_s_lo_ff_scanin;
wire i_a4_s_lo_ff_scanout;
wire [135:0] a4_csa5_1_s_ff;
wire i_a4_s_hi_ff_scanin;
wire i_a4_s_hi_ff_scanout;
wire i_a4_c_lo_ff_scanin;
wire i_a4_c_lo_ff_scanout;
wire [132:0] a4_csa5_1_c_ff;
wire i_a4_c_hi_ff_scanin;
wire i_a4_c_hi_ff_scanout;
wire [135:0] accum_ff;
wire [126:0] xr_fx4;
wire i_accum_ff0_scanin;
wire i_accum_ff0_scanout;
wire [135:0] fya_add_result;
wire i_accum_ff1_scanin;
wire i_accum_ff1_scanout;
wire i_accum_sel_b1_ff_scanin;
wire i_accum_sel_b1_ff_scanout;
wire [3:0] accum_sel_fx4_b1;
wire fya_sticky_dp;
wire fya_sticky_sp;
wire [1:0] fya_xicc_z;
wire i_fx5_ff_scanin;
wire i_fx5_ff_scanout;
wire i_ma_result_ff_scanin;
wire i_ma_result_ff_scanout;


input		l2clk;
input  		scan_in;
input  		tcu_pce_ov;		// scan signals
input  		spc_aclk;
input  		spc_bclk;
input 		tcu_scan_en;
input 	        tcu_dectest;
input           tcu_muxtest;
output 		scan_out;

input           mul_clken_rep0;         // multiply clken
input           mul_clken_rep01;        // multiply clken

input  [63:0]	spu_fgu_rs1_e;          // rs1 source from SPU
input  [63:0]	spu_fgu_rs2_e;          // rs2 source from SPU

input  [63:0]	fad_rs1_fmt_fx1_rep0;
input  [63:0]	fad_rs2_fmt_fx1_rep0;
input  [63:0]	fad_rs2_fmt_fx1_rep1;

input		fac_xr_mode_fx1;	//  0  : Int or Float
					//  1  : XOR mult

input  [4:0]	fac_rs1_sel_fx1;	// [0] : FMUL8SUx16 or FMULD8SUx16
					// [1] : FMUL8x16   or FMUL8x16AU  or FMUL8x16AL
					// [2] : FMUL8ULx16 or FMULD8ULx16
					// [3] : MA Int / XOR   forward of last MA result
					// [4] : MA Int / XOR unforwarded
					// Def : 64 * 64 Multiply

input  [3:0]	fac_rs2_sel_fx1;	// [0] : FMUL8x16AU
					// [1] : FMUL8x16AL
					// [2] : all 8x16
					// [3] : MA Int / XOR
					// Def : 64 * 64 Multiply

input  [1:0]	fac_8x16_rnd_fx3;	// [0] : FMUL8x16 or FMUL8x16AU or FMUL8x16AL or FMUL8SUx16
					// [1] : FMUL8ULx16

input  [3:0]	fac_scff_sel_fx3;	// [0] : Int, Float, MA Int
					// [1] : all 8x16
					// [2] : MA Int   * 2
					// [3] : XOR mult
					// Def : XOR mult * 2

input  [6:0]	fac_accum_sel_fx3;	// [0] : Write ACCUM with result
					// [1] : Add ACCUM to Mult product
					// [2] : XOR Mult w/        ACCUM
					// [3] : XOR Mult w/        ACCUM >> 64
					// [4] : XOR Mult       w/o ACCUM
					// [5] : XOR Mult       w/o ACCUM >> 64
					// [6] : Int Mult w/ or w/o ACCUM
					// Def : Int Mult w/ or w/o ACCUM >> 64

input  [5:0]	fac_result_sel_fx4;	// [0] : FMUL8x16   or FMUL8x16AU or FMUL8x16AL or FMUL8SUx16
					// [1] : FMUL8ULx16
					// [2] : FMULD8SUx16
					// [3] : FMULD8ULx16
					// [4] : XOR multiply w/ ACCUMUMATE
					// [5] : Float
					// Def : Integer, MA Integer w/ and w/o ACCUMULATE, XOR w/o ACCUMULATE

input		fac_ma_result_en_fx4;	//  1  : Save last MA result in shadow flop

output [63:0]	fgu_mul_result_fx5;
output		fpy_sticky_dp_fx5;
output		fpy_sticky_sp_fx5;
output		fpy_fp_result_fx4_b63;
output [1:0]	fpy_xicc_z_fx5;

output		fgu_accum_b0_fx5;	// To SPU MA


// scan renames
assign stop   = 1'b0;
assign test   = tcu_dectest;
// end scan

fgu_fpy_dp_buff_macro__dbuff_32x__rep_1__stack_88c__width_4 test_rep0  (
  .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}),
  .dout({se,          pce_ov,     siclk,    soclk   })
  );


fgu_fpy_dp_msff_macro__minbuff_1__stack_88c__width_64	i_spu_rs1_ff		 (
  .scan_in(i_spu_rs1_ff_scanin),
  .scan_out(i_spu_rs1_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( spu_fgu_rs1_e[63:0]			),
  .dout( spu_fgu_rs1_fx1[63:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__stack_88c__width_64	i_spu_rs2_ff		 (
  .scan_in(i_spu_rs2_ff_scanin),
  .scan_out(i_spu_rs2_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( spu_fgu_rs2_e[63:0]			),
  .dout( spu_fgu_rs2_fx1[63:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_4	i_rs2_fx1_ebuf		 (
  .din ({fad_rs2_fmt_fx1_rep0[63],fad_rs2_fmt_fx1_rep0[47],fad_rs2_fmt_fx1_rep0[31],fad_rs2_fmt_fx1_rep0[15]}),
  .dout({    rs2_fx1_ebf[63]     ,    rs2_fx1_ebf[47]     ,    rs2_fx1_ebf[31]     ,    rs2_fx1_ebf[15]}     ));


// *** *** *** *** *** *** *** *** Start : RS1 Format *** *** *** *** *** *** *** ***


fgu_fpy_dp_inv_macro__stack_88c__width_1	i_xr_mode_fx1_inv	 (
  .din ( fac_xr_mode_fx1	),
  .dout( xr_mode_fx1_   	));

fgu_fpy_dp_buff_macro__stack_88c__width_2	i_xr_mode_fx1_buf	 (
  .din ({2{fac_xr_mode_fx1}}	),
  .dout( xr_mode_fx1_bf[1:0]	));

fgu_fpy_dp_buff_macro__dbuff_48x__stack_88c__width_1 muxtest_a_rep0  (
  .din (tcu_muxtest	  ),
  .dout(tcu_muxtest_a_rep0)
  );

fgu_fpy_dp_mux_macro__mux_pgpe__ports_6__stack_88c__width_69	i_rs1_fmt_mux		  (
  .muxtst(tcu_muxtest_a_rep0),
  .din0({{ 4{fad_rs1_fmt_fx1_rep0[63]}},fad_rs1_fmt_fx1_rep0[63:56],1'b0,	// a0 12:0
         {10{fad_rs1_fmt_fx1_rep0[47]}},fad_rs1_fmt_fx1_rep0[47:40],1'b0,	// a1 18:0
         {10{fad_rs1_fmt_fx1_rep0[31]}},fad_rs1_fmt_fx1_rep0[31:24],1'b0,	// a2 18:0
         {10{fad_rs1_fmt_fx1_rep0[15]}},fad_rs1_fmt_fx1_rep0[15:8]     }),	// a3 18:1

  .din1({{ 4{    1'b0                }},fad_rs1_fmt_fx1_rep0[63:56],1'b0,	// a0 12:0
         {10{    1'b0                }},fad_rs1_fmt_fx1_rep0[55:48],1'b0,	// a1 18:0
         {10{    1'b0                }},fad_rs1_fmt_fx1_rep0[47:40],1'b0,	// a2 18:0
         {10{    1'b0                }},fad_rs1_fmt_fx1_rep0[39:32]     }),	// a3 18:1

  .din2({{ 4{    1'b0                }},fad_rs1_fmt_fx1_rep0[55:48],1'b0,	// a0 12:0
         {10{    1'b0                }},fad_rs1_fmt_fx1_rep0[39:32],1'b0,	// a1 18:0
         {10{    1'b0                }},fad_rs1_fmt_fx1_rep0[23:16],1'b0,	// a2 18:0
         {10{    1'b0                }},fad_rs1_fmt_fx1_rep0[7:0]     }),	// a3 18:1

  .din3({2'b00,ma_result_ff[63:53],						// a0 12:0
         ma_result_ff[53:35]	,		  				// a1 18:0
         ma_result_ff[35:17]	,						// a2 18:0
         ma_result_ff[17:0]	}			  	         ),	// a3 18:1

  .din4({2'b00,spu_fgu_rs1_fx1[63:53],						// a0 12:0
         spu_fgu_rs1_fx1[53:35],						// a1 18:0
         spu_fgu_rs1_fx1[35:17],						// a2 18:0
         spu_fgu_rs1_fx1[17:0]}					 ),	// a3 18:1

  .din5({2'b00,fad_rs1_fmt_fx1_rep0[63:53],					// a0 12:0
         fad_rs1_fmt_fx1_rep0[53:35],						// a1 18:0
         fad_rs1_fmt_fx1_rep0[35:17],						// a2 18:0
         fad_rs1_fmt_fx1_rep0[17:0]}					 ),	// a3 18:1

  .sel0( fac_rs1_sel_fx1[0]						 ),
  .sel1( fac_rs1_sel_fx1[1]						 ),
  .sel2( fac_rs1_sel_fx1[2]						 ),
  .sel3( fac_rs1_sel_fx1[3]						 ),
  .sel4( fac_rs1_sel_fx1[4]						 ),
  .dout({rs1_fmt_a0[12:0]	,
         rs1_fmt_a1[18:0]	,
         rs1_fmt_a2[18:0]	,
         rs1_fmt_a3[18:1]	}					 ),
  .test(test));


  assign rs1_fmt_a3[0]	= 1'b0;		// 1st back bit is always '0'


fgu_fpy_dp_booth_encode_macro	i_be00	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[2:0]	),
  .dout    ( be00[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[0]	),	// P,H
  .hout    ( be_hout[0]	));


fgu_fpy_dp_booth_encode_macro	i_be01	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[4:2]	),
  .dout    ( be01[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[1]	),	// P,H
  .hout    ( be_hout[1]	));


fgu_fpy_dp_booth_encode_macro	i_be02	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[6:4]	),
  .dout    ( be02[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[2]	),	// P,H
  .hout    ( be_hout[2]	));


fgu_fpy_dp_booth_encode_macro	i_be03	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[8:6]	),
  .dout    ( be03[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[3]	),	// P,H
  .hout    ( be_hout[3]	));


fgu_fpy_dp_booth_encode_macro	i_be04	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[10:8]	),
  .dout    ( be04[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[4]	),	// P,H
  .hout    ( be_hout[4]	));


fgu_fpy_dp_booth_encode_macro	i_be05	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[12:10]	),
  .dout    ( be05[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[5]	),	// P,H
  .hout    ( be_hout[5]	));


fgu_fpy_dp_booth_encode_macro	i_be06	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[14:12]	),
  .dout    ( be06[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[6]	),	// P,H
  .hout    ( be_hout[6]	));


fgu_fpy_dp_booth_encode_macro	i_be07	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[16:14]	),
  .dout    ( be07[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[7]	),	// P,H
  .hout    ( be_hout[7]	));


fgu_fpy_dp_booth_encode_macro	i_be08	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a3[18:16]	),
  .dout    ( be08[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[8]	),	// P,H
  .hout    ( be_hout[8]	));


fgu_fpy_dp_booth_encode_macro	i_be09	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[2:0]	),
  .dout    ( be09[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[9]	),	// P,H
  .hout    ( be_hout[9]	));


fgu_fpy_dp_booth_encode_macro	i_be10	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[4:2]	),
  .dout    ( be10[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[10]	),	// P,H
  .hout    ( be_hout[10]	));


fgu_fpy_dp_booth_encode_macro	i_be11	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[6:4]	),
  .dout    ( be11[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[11]	),	// P,H
  .hout    ( be_hout[11]	));


fgu_fpy_dp_booth_encode_macro	i_be12	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[8:6]	),
  .dout    ( be12[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[12]	),	// P,H
  .hout    ( be_hout[12]	));


fgu_fpy_dp_booth_encode_macro	i_be13	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[10:8]	),
  .dout    ( be13[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[13]	),	// P,H
  .hout    ( be_hout[13]	));


fgu_fpy_dp_booth_encode_macro	i_be14	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[12:10]	),
  .dout    ( be14[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[14]	),	// P,H
  .hout    ( be_hout[14]	));


fgu_fpy_dp_booth_encode_macro	i_be15	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[14:12]	),
  .dout    ( be15[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[15]	),	// P,H
  .hout    ( be_hout[15]	));


fgu_fpy_dp_booth_encode_macro	i_be16	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[16:14]	),
  .dout    ( be16[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[16]	),	// P,H
  .hout    ( be_hout[16]	));


fgu_fpy_dp_booth_encode_macro	i_be17	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a2[18:16]	),
  .dout    ( be17[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[17]	),	// P,H
  .hout    ( be_hout[17]	));


fgu_fpy_dp_booth_encode_macro	i_be18	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a1[2:0]	),
  .dout    ( be18[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[18]	),	// P,H
  .hout    ( be_hout[18]	));


fgu_fpy_dp_booth_encode_macro	i_be19	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a1[4:2]	),
  .dout    ( be19[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[19]	),	// P,H
  .hout    ( be_hout[19]	));


fgu_fpy_dp_booth_encode_macro	i_be20	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a1[6:4]	),
  .dout    ( be20[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[20]	),	// P,H
  .hout    ( be_hout[20]	));


fgu_fpy_dp_booth_encode_macro	i_be21	(
  .xr_mode ( xr_mode_fx1_bf[0]	),
  .din     ( rs1_fmt_a1[8:6]	),
  .dout    ( be21[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[21]	),	// P,H
  .hout    ( be_hout[21]	));


fgu_fpy_dp_booth_encode_macro	i_be22	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a1[10:8]	),
  .dout    ( be22[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[22]	),	// P,H
  .hout    ( be_hout[22]	));


fgu_fpy_dp_booth_encode_macro	i_be23	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a1[12:10]	),
  .dout    ( be23[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[23]	),	// P,H
  .hout    ( be_hout[23]	));


fgu_fpy_dp_booth_encode_macro	i_be24	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a1[14:12]	),
  .dout    ( be24[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[24]	),	// P,H
  .hout    ( be_hout[24]	));


fgu_fpy_dp_booth_encode_macro	i_be25	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a1[16:14]	),
  .dout    ( be25[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[25]	),	// P,H
  .hout    ( be_hout[25]	));


fgu_fpy_dp_booth_encode_macro	i_be26	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a1[18:16]	),
  .dout    ( be26[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[26]	),	// P,H
  .hout    ( be_hout[26]	));


fgu_fpy_dp_booth_encode_macro	i_be27	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a0[2:0]	),
  .dout    ( be27[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[27]	),	// P,H
  .hout    ( be_hout[27]	));


fgu_fpy_dp_booth_encode_macro	i_be28	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a0[4:2]	),
  .dout    ( be28[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[28]	),	// P,H
  .hout    ( be_hout[28]	));


fgu_fpy_dp_booth_encode_macro	i_be29	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a0[6:4]	),
  .dout    ( be29[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[29]	),	// P,H
  .hout    ( be_hout[29]	));


fgu_fpy_dp_booth_encode_macro	i_be30	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a0[8:6]	),
  .dout    ( be30[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[30]	),	// P,H
  .hout    ( be_hout[30]	));


fgu_fpy_dp_booth_encode_macro	i_be31	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a0[10:8]	),
  .dout    ( be31[4:0]		),	// +3,-1,-2,+2,+1
  .pout    ( be_pout[31]	),	// P,H
  .hout    ( be_hout[31]	));


fgu_fpy_dp_booth_encode_macro	i_be32	(
  .xr_mode ( xr_mode_fx1_bf[1]	),
  .din     ( rs1_fmt_a0[12:10]	),
  .dout    ({i_be32_unused[3:0],
             be32_b0}		),	// +3,-1,-2,+2,+1
  .pout    ( i_be32_unused[4]	),	// P,H
  .hout    ( i_be32_unused[5]	));


// *** *** *** *** *** *** *** *** End   : RS1 Format *** *** *** *** *** *** *** ***


// *** *** *** *** *** *** *** *** Start : XOR multiply specific  *** *** *** *** ***


fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_63	i_3x_xor		 (
  .din0( spu_fgu_rs2_fx1[63:1]		),	// XOR 1x
  .din1( spu_fgu_rs2_fx1[62:0]		),	// XOR 2x
  .dout( rs2_3x_fx1[63:1]			));

  assign rs2_3x_fx1[0]	= spu_fgu_rs2_fx1[0];
  assign rs2_3x_fx1[64]	= spu_fgu_rs2_fx1[63];


fgu_fpy_dp_msff_macro__stack_88c__width_65	i_3x_ff			 (
  .scan_in(i_3x_ff_scanin),
  .scan_out(i_3x_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( rs2_3x_fx1[64:0]			),
  .dout( rs2_3x_ff[64:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_65	i_3x_buf		 (
  .din ( rs2_3x_ff[64:0]			),
  .dout( rs2_3x[64:0]				));


// *** *** *** *** *** *** *** *** End   : XOR multiply specific  *** *** *** *** ***


// *** *** *** *** *** *** *** *** Start : "A3" 9:2 CSA Tree  *** *** *** *** *** ***

fgu_fpy_dp_msff_macro__stack_88c__width_63	i_a3_be_ff		 (
  .scan_in(i_a3_be_ff_scanin),
  .scan_out(i_a3_be_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ({xr_mode_fx1_		,
         be_pout[8:0]		,
         be08[4:0]		,
         be07[4:0]		,
         be06[4:0]		,
         be05[4:0]		,
         be04[4:0]		,
         be03[4:0]		,
         be02[4:0]		,
         be01[4:0]		,
         be00[4:0]		,
         be_hout[7:0]}			),
  .dout({a3_xr_mode_fx2_	,
         be_pout_ff[8:0]	,
         be_ff08[4:0]		,
         be_ff07[4:0]		,
         be_ff06[4:0]		,
         be_ff05[4:0]		,
         be_ff04[4:0]		,
         be_ff03[4:0]		,
         be_ff02[4:0]		,
         be_ff01[4:0]		,
         be_ff00[4:0]		,
         be_hout_ff[7:0]}			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_3	i_a3_rs2_fx1_ebuf	 (
  .din ({rs2_fx1_ebf[63]    ,rs2_fx1_ebf[47]    ,rs2_fx1_ebf[15]}		),
  .dout({rs2_fx1_ebf3[63]   ,rs2_fx1_ebf3[47]   ,rs2_fx1_ebf3[15]}		));


fgu_fpy_dp_msff_macro__mux_aope__ports_5__stack_88c__width_64	i_a3_rs2_ff		 (
  .scan_in(i_a3_rs2_ff_scanin),
  .scan_out(i_a3_rs2_ff_scanout),
  .clk ( l2clk								),
  .en  ( mul_clken_rep0					 	 	),
  .din0({{32{1'b0}},{17{rs2_fx1_ebf3[63]}},fad_rs2_fmt_fx1_rep1[62:48]}	),
  .din1({{32{1'b0}},{17{rs2_fx1_ebf3[47]}},fad_rs2_fmt_fx1_rep1[46:32]}	),
  .din2({{32{1'b0}},{17{rs2_fx1_ebf3[15]}},fad_rs2_fmt_fx1_rep1[14:0]}	),
  .din3( spu_fgu_rs2_fx1[63:0]						),
  .din4( fad_rs2_fmt_fx1_rep1[63:0]					),
  .sel0( fac_rs2_sel_fx1[0]						),
  .sel1( fac_rs2_sel_fx1[1]						),
  .sel2( fac_rs2_sel_fx1[2]						),
  .sel3( fac_rs2_sel_fx1[3]						),
  .dout( a3_rs2_ff[63:0]						),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_64	i_a3_rs2_buf		 (
  .din ( a3_rs2_ff[63:0]			),
  .dout( a3_rs2[63:0]				));

fgu_fpy_dp_inv_macro__stack_88c__width_64	i_a3_rs2_inv		 (
  .din ( a3_rs2_ff[63:0]			),
  .dout( a3_rs2_[63:0]				));


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_00		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff00[0]                          ),
  .sel1( be_ff00[1]                          ),
  .sel2( be_ff00[2]                          ),
  .sel3( be_ff00[3]                          ),
  .sel4( be_ff00[4]                          ),
  .dout( bm00[64:0]                         ));

  assign bm00[67:65]	= { be_pout_ff[0] , be_hout_ff[0] , be_hout_ff[0]};	// PNN


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_01		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff01[0]                          ),
  .sel1( be_ff01[1]                          ),
  .sel2( be_ff01[2]                          ),
  .sel3( be_ff01[3]                          ),
  .sel4( be_ff01[4]                          ),
  .dout( bm01[66:2]                         ));

  assign bm01[68:67]	= { a3_xr_mode_fx2_ , be_pout_ff[1] };	// 1P
  assign bm01[1:0]	= { 1'b0            , be_hout_ff[0] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_02		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff02[0]                          ),
  .sel1( be_ff02[1]                          ),
  .sel2( be_ff02[2]                          ),
  .sel3( be_ff02[3]                          ),
  .sel4( be_ff02[4]                          ),
  .dout( bm02[68:4]                         ));

  assign bm02[70:69]	= { a3_xr_mode_fx2_ , be_pout_ff[2] };	// 1P
  assign bm02[3:2]	= { 1'b0            , be_hout_ff[1] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_03		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff03[0]                          ),
  .sel1( be_ff03[1]                          ),
  .sel2( be_ff03[2]                          ),
  .sel3( be_ff03[3]                          ),
  .sel4( be_ff03[4]                          ),
  .dout( bm03[70:6]                         ));

  assign bm03[72:71]	= { a3_xr_mode_fx2_ , be_pout_ff[3] };	// 1P
  assign bm03[5:4]	= { 1'b0            , be_hout_ff[2] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_04		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff04[0]                          ),
  .sel1( be_ff04[1]                          ),
  .sel2( be_ff04[2]                          ),
  .sel3( be_ff04[3]                          ),
  .sel4( be_ff04[4]                          ),
  .dout( bm04[72:8]                         ));

  assign bm04[74:73]	= { a3_xr_mode_fx2_ , be_pout_ff[4] };	// 1P
  assign bm04[7:6]	= { 1'b0            , be_hout_ff[3] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_05		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff05[0]                          ),
  .sel1( be_ff05[1]                          ),
  .sel2( be_ff05[2]                          ),
  .sel3( be_ff05[3]                          ),
  .sel4( be_ff05[4]                          ),
  .dout( bm05[74:10]                         ));

  assign bm05[76:75]	= { a3_xr_mode_fx2_ , be_pout_ff[5] };	// 1P
  assign bm05[9:8]	= { 1'b0            , be_hout_ff[4] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_06		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff06[0]                          ),
  .sel1( be_ff06[1]                          ),
  .sel2( be_ff06[2]                          ),
  .sel3( be_ff06[3]                          ),
  .sel4( be_ff06[4]                          ),
  .dout( bm06[76:12]                         ));

  assign bm06[78:77]	= { a3_xr_mode_fx2_ , be_pout_ff[6] };	// 1P
  assign bm06[11:10]	= { 1'b0            , be_hout_ff[5] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_07		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff07[0]                          ),
  .sel1( be_ff07[1]                          ),
  .sel2( be_ff07[2]                          ),
  .sel3( be_ff07[3]                          ),
  .sel4( be_ff07[4]                          ),
  .dout( bm07[78:14]                         ));

  assign bm07[80:79]	= { a3_xr_mode_fx2_ , be_pout_ff[7] };	// 1P
  assign bm07[13:12]	= { 1'b0            , be_hout_ff[6] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a3_bm_08		  (
  .din0({1'b0        , a3_rs2[63:0]         }),		// +1 * rs2
  .din1({              a3_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a3_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a3_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff08[0]                          ),
  .sel1( be_ff08[1]                          ),
  .sel2( be_ff08[2]                          ),
  .sel3( be_ff08[3]                          ),
  .sel4( be_ff08[4]                          ),
  .dout( bm08[80:16]                         ));

  assign bm08[82:81]	= { a3_xr_mode_fx2_ , be_pout_ff[8] };	// 1P
  assign bm08[15:14]	= { 1'b0            , be_hout_ff[7] };


fgu_fpy_dp_csa32_macro__stack_88c__width_69	a3_csa1_1		 (
 .i0   ({ { 1{1'b0}}, bm00[67:0]                    }),
 .i1   ({             bm01[68:0]                    }),
 .i2   ({             bm02[68:2]       , { 2{1'b0}} }),
 .carry(              a3_csa1_1_c[69:1]              ),
 .sum  (              a3_csa1_1_s[68:0]              ));

  assign a3_csa1_1_s[70:69]	= bm02[70:69];


fgu_fpy_dp_csa32_macro__stack_88c__width_69	a3_csa1_2		 (
 .i0   ({ { 2{1'b0}}, bm03[72:6]                    }),
 .i1   ({             bm04[74:6]                    }),
 .i2   ({             bm05[74:8]       , { 2{1'b0}} }),
 .carry(              a3_csa1_2_c[75:7]              ),
 .sum  (              a3_csa1_2_s[74:6]              ));

  assign a3_csa1_2_s[5:4]	= bm03[5:4];
  assign a3_csa1_2_s[76:75]	= bm05[76:75];


fgu_fpy_dp_csa32_macro__stack_88c__width_69	a3_csa1_3		 (
 .i0   ({ { 2{1'b0}}, bm06[78:12]                    }),
 .i1   ({             bm07[80:12]                    }),
 .i2   ({             bm08[80:14]       , { 2{1'b0}} }),
 .carry(              a3_csa1_3_c[81:13]              ),
 .sum  (              a3_csa1_3_s[80:12]              ));

  assign a3_csa1_3_s[11:10]	= bm06[11:10];
  assign a3_csa1_3_s[82:81]	= bm08[82:81];


//		*** 1st level to 2nd level ***
//
//	csa1_1_s[70:00]		csa1_1_c[69:01]
//	csa1_2_s[76:04]		csa1_2_c[75:07]
//	csa1_3_s[82:10]		csa1_3_c[81:13]


fgu_fpy_dp_csa32_macro__stack_88c__width_73	a3_csa2_1		 (
 .i0   ({ { 6{1'b0}}, a3_csa1_1_s[70:4]             }),
 .i1   ({             a3_csa1_2_s[76:4]             }),
 .i2   ({             a3_csa1_3_s[76:10], { 6{1'b0}} }),
 .carry(              a3_csa2_1_c[77:5]              ),
 .sum  (              a3_csa2_1_s[76:4]              ));

  assign a3_csa2_1_s[3:0]	= a3_csa1_1_s[3:0];
  assign a3_csa2_1_s[82:77]	= a3_csa1_3_s[82:77];


fgu_fpy_dp_csa32_macro__stack_88c__width_69	a3_csa2_2		 (
 .i0   ({ { 6{1'b0}}, a3_csa1_1_c[69:7]             }),
 .i1   ({             a3_csa1_2_c[75:7]             }),
 .i2   ({             a3_csa1_3_c[75:13], { 6{1'b0}} }),
 .carry(              a3_csa2_2_c[76:8]              ),
 .sum  (              a3_csa2_2_s[75:7]              ));

  assign a3_csa2_2_s[6:1]	= a3_csa1_1_c[6:1];
  assign a3_csa2_2_s[81:76]	= a3_csa1_3_c[81:76];


//		*** 2nd level to 3rd level ***
//
//	csa2_1_s[82:00]		csa2_1_c[77:05]
//	csa2_2_s[81:01]		csa2_2_c[76:08]


fgu_fpy_dp_csa42_macro__stack_88c__width_81	a3_csa3_1		 (
 .i0   ({             a3_csa2_1_s[81:1]              }),
 .i1   ({ { 4{1'b0}}, a3_csa2_1_c[77:5] , { 4{1'b0}} }),
 .i2   ({ { 5{1'b0}}, a3_csa2_2_c[76:8] , { 7{1'b0}} }),
 .i3   ({             a3_csa2_2_s[81:1]              }),
 .cin  (     1'b0                                      ), // 1 bit
 .cout ( a3_csa3_1_unused                              ), // 1 bit
 .carry( a3_csa3_1_c[82:2]                            ),
 .sum  ( a3_csa3_1_s[81:1]                            ));

  assign a3_csa3_1_s[0]	= a3_csa2_1_s[0];
  assign a3_csa3_1_s[82]	= a3_csa2_1_s[82];


fgu_fpy_dp_msff_macro__stack_88c__width_39	i_a3_s_ff_a		 (
  .scan_in(i_a3_s_ff_a_scanin),
  .scan_out(i_a3_s_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a3_csa3_1_s[82:44]			),	// [82] and [00] are early
  .dout( a3_csa3_1_s_ff[82:44]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a3_s_ff_b		 (
  .scan_in(i_a3_s_ff_b_scanin),
  .scan_out(i_a3_s_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( a3_csa3_1_s[43:0]			),	// [82] and [00] are early
  .dout( a3_csa3_1_s_ff[43:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__stack_88c__width_37	i_a3_c_ff_a		 (
  .scan_in(i_a3_c_ff_a_scanin),
  .scan_out(i_a3_c_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a3_csa3_1_c[82:46]			),
  .dout( a3_csa3_1_c_ff[82:46]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a3_c_ff_b		 (
  .scan_in(i_a3_c_ff_b_scanin),
  .scan_out(i_a3_c_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( a3_csa3_1_c[45:2]			),
  .dout( a3_csa3_1_c_ff[45:2]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// *** *** *** *** *** *** *** *** End   : "A3" 9:2 CSA Tree  *** *** *** *** *** ***


fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_63	a32_xor4_1		 (
  .din0( a3_csa2_1_s[80:18]			),
  .din1( a2_csa2_3_s[80:18]			),
  .dout( a32_xr4_1[80:18]			));

  assign a32_xr4_1[17:0]	= a3_csa2_1_s[17:0];
  assign a32_xr4_1[98:81]	= a2_csa2_3_s[98:81];


fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a32_x_ff_a		 (
  .scan_in(i_a32_x_ff_a_scanin),
  .scan_out(i_a32_x_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a32_xr4_1[87:44]			),
  .dout( a32_xr_ff[87:44]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a32_x_ff_b		 (
  .scan_in(i_a32_x_ff_b_scanin),
  .scan_out(i_a32_x_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( a32_xr4_1[43:0]			),
  .dout( a32_xr_ff[43:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// *** *** *** *** *** *** *** *** Start : "A2" 9:2 CSA Tree  *** *** *** *** *** ***

fgu_fpy_dp_msff_macro__stack_88c__width_31	i_a2_be_ff_a		 (
  .scan_in(i_a2_be_ff_a_scanin),
  .scan_out(i_a2_be_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ({a32_xr4_1[98:88]	,
         xr_mode_fx1_		,
         be_pout[17:9]		,
         be17[4:0]		,
         be16[4:0]}                             ),
  .dout({a32_xr_ff[98:88]	,
         a2_xr_mode_fx2_	,
         be_pout_ff[17:9]	,
         be_ff17[4:0]		,
         be_ff16[4:0]}                          ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a2_be_ff_b		 (
  .scan_in(i_a2_be_ff_b_scanin),
  .scan_out(i_a2_be_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ({be15[4:0]		,
         be14[4:0]		,
         be13[4:0]		,
         be12[4:0]		,
         be11[4:0]		,
         be10[4:0]		,
         be09[4:0]		,
         be_hout[16:8]}			),
  .dout({be_ff15[4:0]		,
         be_ff14[4:0]		,
         be_ff13[4:0]		,
         be_ff12[4:0]		,
         be_ff11[4:0]		,
         be_ff10[4:0]		,
         be_ff09[4:0]		,
         be_hout_ff[16:8]}			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_3	i_a2_rs2_fx1_ebuf	 (
  .din ({rs2_fx1_ebf[63]    ,rs2_fx1_ebf[47]    ,rs2_fx1_ebf[31]}		),
  .dout({rs2_fx1_ebf2[63]   ,rs2_fx1_ebf2[47]   ,rs2_fx1_ebf2[31]}		));


fgu_fpy_dp_msff_macro__mux_aope__ports_5__stack_88c__width_64	i_a2_rs2_ff		 (
  .scan_in(i_a2_rs2_ff_scanin),
  .scan_out(i_a2_rs2_ff_scanout),
  .clk ( l2clk								),
  .en  ( mul_clken_rep0							),
  .din0({{32{1'b0}},{17{rs2_fx1_ebf2[63]}},fad_rs2_fmt_fx1_rep1[62:48]}	),
  .din1({{32{1'b0}},{17{rs2_fx1_ebf2[47]}},fad_rs2_fmt_fx1_rep1[46:32]}	),
  .din2({{32{1'b0}},{17{rs2_fx1_ebf2[31]}},fad_rs2_fmt_fx1_rep1[30:16]}	),
  .din3( spu_fgu_rs2_fx1[63:0]						),
  .din4( fad_rs2_fmt_fx1_rep1[63:0]					),
  .sel0( fac_rs2_sel_fx1[0]						),
  .sel1( fac_rs2_sel_fx1[1]						),
  .sel2( fac_rs2_sel_fx1[2]						),
  .sel3( fac_rs2_sel_fx1[3]						),
  .dout( a2_rs2_ff[63:0]						),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_64	i_a2_rs2_buf		 (
  .din ( a2_rs2_ff[63:0]			),
  .dout( a2_rs2[63:0]				));

fgu_fpy_dp_inv_macro__stack_88c__width_64	i_a2_rs2_inv		 (
  .din ( a2_rs2_ff[63:0]			),
  .dout( a2_rs2_[63:0]				));


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_09		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff09[0]                          ),
  .sel1( be_ff09[1]                          ),
  .sel2( be_ff09[2]                          ),
  .sel3( be_ff09[3]                          ),
  .sel4( be_ff09[4]                          ),
  .dout( bm09[82:18]                         ));

  assign bm09[84:83]	= { a2_xr_mode_fx2_ , be_pout_ff[9] };	// 1P
  assign bm09[17:16]	= { 1'b0            , be_hout_ff[8] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_10		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff10[0]                          ),
  .sel1( be_ff10[1]                          ),
  .sel2( be_ff10[2]                          ),
  .sel3( be_ff10[3]                          ),
  .sel4( be_ff10[4]                          ),
  .dout( bm10[84:20]                         ));

  assign bm10[86:85]	= { a2_xr_mode_fx2_ , be_pout_ff[10]};	// 1P
  assign bm10[19:18]	= { 1'b0            , be_hout_ff[9] };


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_11		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff11[0]                          ),
  .sel1( be_ff11[1]                          ),
  .sel2( be_ff11[2]                          ),
  .sel3( be_ff11[3]                          ),
  .sel4( be_ff11[4]                          ),
  .dout( bm11[86:22]                         ));

  assign bm11[88:87]	= { a2_xr_mode_fx2_ , be_pout_ff[11]};	// 1P
  assign bm11[21:20]	= { 1'b0            , be_hout_ff[10]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_12		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff12[0]                          ),
  .sel1( be_ff12[1]                          ),
  .sel2( be_ff12[2]                          ),
  .sel3( be_ff12[3]                          ),
  .sel4( be_ff12[4]                          ),
  .dout( bm12[88:24]                         ));

  assign bm12[90:89]	= { a2_xr_mode_fx2_ , be_pout_ff[12]};	// 1P
  assign bm12[23:22]	= { 1'b0            , be_hout_ff[11]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_13		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff13[0]                          ),
  .sel1( be_ff13[1]                          ),
  .sel2( be_ff13[2]                          ),
  .sel3( be_ff13[3]                          ),
  .sel4( be_ff13[4]                          ),
  .dout( bm13[90:26]                         ));

  assign bm13[92:91]	= { a2_xr_mode_fx2_ , be_pout_ff[13]};	// 1P
  assign bm13[25:24]	= { 1'b0            , be_hout_ff[12]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_14		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff14[0]                          ),
  .sel1( be_ff14[1]                          ),
  .sel2( be_ff14[2]                          ),
  .sel3( be_ff14[3]                          ),
  .sel4( be_ff14[4]                          ),
  .dout( bm14[92:28]                         ));

  assign bm14[94:93]	= { a2_xr_mode_fx2_ , be_pout_ff[14]};	// 1P
  assign bm14[27:26]	= { 1'b0            , be_hout_ff[13]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_15		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff15[0]                          ),
  .sel1( be_ff15[1]                          ),
  .sel2( be_ff15[2]                          ),
  .sel3( be_ff15[3]                          ),
  .sel4( be_ff15[4]                          ),
  .dout( bm15[94:30]                         ));

  assign bm15[96:95]	= { a2_xr_mode_fx2_ , be_pout_ff[15]};	// 1P
  assign bm15[29:28]	= { 1'b0            , be_hout_ff[14]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_16		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff16[0]                          ),
  .sel1( be_ff16[1]                          ),
  .sel2( be_ff16[2]                          ),
  .sel3( be_ff16[3]                          ),
  .sel4( be_ff16[4]                          ),
  .dout( bm16[96:32]                         ));

  assign bm16[98:97]	= { a2_xr_mode_fx2_ , be_pout_ff[16]};	// 1P
  assign bm16[31:30]	= { 1'b0            , be_hout_ff[15]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a2_bm_17		  (
  .din0({1'b0        , a2_rs2[63:0]         }),		// +1 * rs2
  .din1({              a2_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a2_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a2_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff17[0]                          ),
  .sel1( be_ff17[1]                          ),
  .sel2( be_ff17[2]                          ),
  .sel3( be_ff17[3]                          ),
  .sel4( be_ff17[4]                          ),
  .dout( bm17[98:34]                         ));

  assign bm17[100:99]	= { a2_xr_mode_fx2_ , be_pout_ff[17]};	// 1P
  assign bm17[33:32]	= { 1'b0            , be_hout_ff[16]};


//	bm09[84:16]	bm10[86:18]	bm11[88:20]

fgu_fpy_dp_csa32_macro__stack_88c__width_69	a2_csa1_4		 (
 .i0   ({ { 2{1'b0}}, bm09[84:18]                    }),
 .i1   ({             bm10[86:18]                    }),
 .i2   ({             bm11[86:20]       , { 2{1'b0}} }),
 .carry(              a2_csa1_4_c[87:19]              ),
 .sum  (              a2_csa1_4_s[86:18]              ));

  assign a2_csa1_4_s[17:16]	= bm09[17:16];
  assign a2_csa1_4_s[88:87]	= bm11[88:87];


//	bm12[90:22]	bm13[92:24]	bm14[94:26]

fgu_fpy_dp_csa32_macro__stack_88c__width_69	a2_csa1_5		 (
 .i0   ({ { 2{1'b0}}, bm12[90:24]                    }),
 .i1   ({             bm13[92:24]                    }),
 .i2   ({             bm14[92:26]       , { 2{1'b0}} }),
 .carry(              a2_csa1_5_c[93:25]              ),
 .sum  (              a2_csa1_5_s[92:24]              ));

  assign a2_csa1_5_s[23:22]	= bm12[23:22];
  assign a2_csa1_5_s[94:93]	= bm14[94:93];


//	bm15[96:28]	bm16[98:30]	bm17[100:32]

fgu_fpy_dp_csa32_macro__stack_88c__width_69	a2_csa1_6		 (
 .i0   ({ { 2{1'b0}}, bm15[96:30]                    }),
 .i1   ({             bm16[98:30]                    }),
 .i2   ({             bm17[98:32]       , { 2{1'b0}} }),
 .carry(              a2_csa1_6_c[99:31]              ),
 .sum  (              a2_csa1_6_s[98:30]              ));

  assign a2_csa1_6_s[29:28]	= bm15[29:28];
  assign a2_csa1_6_s[100:99]	= bm17[100:99];


//		*** 1st level to 2nd level ***
//
//	csa1_4_s[88:16]		csa1_4_c[87:19]
//	csa1_5_s[94:22]		csa1_5_c[93:25]
//	csa1_6_s[100:28]	csa1_6_c[99:31]


fgu_fpy_dp_csa32_macro__stack_88c__width_73	a2_csa2_3		 (
 .i0   ({ { 6{1'b0}}, a2_csa1_4_s[88:22]             }),
 .i1   ({             a2_csa1_5_s[94:22]             }),
 .i2   ({             a2_csa1_6_s[94:28], { 6{1'b0}} }),
 .carry(              a2_csa2_3_c[95:23]              ),
 .sum  (              a2_csa2_3_s[94:22]              ));

  assign a2_csa2_3_s[21:16]	= a2_csa1_4_s[21:16];
  assign a2_csa2_3_s[100:95]	= a2_csa1_6_s[100:95];


fgu_fpy_dp_csa32_macro__stack_88c__width_69	a2_csa2_4		 (
 .i0   ({ { 6{1'b0}}, a2_csa1_4_c[87:25]             }),
 .i1   ({             a2_csa1_5_c[93:25]             }),
 .i2   ({             a2_csa1_6_c[93:31], { 6{1'b0}} }),
 .carry(              a2_csa2_4_c[94:26]              ),
 .sum  (              a2_csa2_4_s[93:25]              ));

  assign a2_csa2_4_s[24:19]	= a2_csa1_4_c[24:19];
  assign a2_csa2_4_s[99:94]	= a2_csa1_6_c[99:94];


//		*** 2nd level to 3rd level ***
//
//	csa2_3_s[100:16]	csa2_3_c[95:23]
//	csa2_4_s[99:19]		csa2_4_c[94:26]


fgu_fpy_dp_csa42_macro__stack_88c__width_81	a2_csa3_2		 (
 .i0   ({             a2_csa2_3_s[99:19]              }),
 .i1   ({ { 4{1'b0}}, a2_csa2_3_c[95:23] , { 4{1'b0}} }),
 .i2   ({ { 5{1'b0}}, a2_csa2_4_c[94:26] , { 7{1'b0}} }),
 .i3   ({             a2_csa2_4_s[99:19]              }),
 .cin  (     1'b0                                      ), // 1 bit
 .cout ( a2_csa3_2_unused                              ), // 1 bit
 .carry( a2_csa3_2_c[100:20]                           ),
 .sum  ( a2_csa3_2_s[99:19]                            ));

  assign a2_csa3_2_s[18:16]	= a2_csa2_3_s[18:16];
  assign a2_csa3_2_s[100]	= a2_csa2_3_s[100];


fgu_fpy_dp_msff_macro__stack_88c__width_41	i_a2_s_ff_a		 (
  .scan_in(i_a2_s_ff_a_scanin),
  .scan_out(i_a2_s_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a2_csa3_2_s[100:60]			),	// [100] and [18:16] are early
  .dout( a2_csa3_2_s_ff[100:60]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a2_s_ff_b		 (
  .scan_in(i_a2_s_ff_b_scanin),
  .scan_out(i_a2_s_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( a2_csa3_2_s[59:16]			),	// [100] and [18:16] are early
  .dout( a2_csa3_2_s_ff[59:16]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__stack_88c__width_37	i_a2_c_ff_a		 (
  .scan_in(i_a2_c_ff_a_scanin),
  .scan_out(i_a2_c_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a2_csa3_2_c[100:64]			),
  .dout( a2_csa3_2_c_ff[100:64]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a2_c_ff_b		 (
  .scan_in(i_a2_c_ff_b_scanin),
  .scan_out(i_a2_c_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( a2_csa3_2_c[63:20]			),
  .dout( a2_csa3_2_c_ff[63:20]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// *** *** *** *** *** *** *** *** End   : "A2" 9:2 CSA Tree  *** *** *** *** *** ***


// *** *** *** *** *** *** *** *** Start : "A1" 9:2 CSA Tree  *** *** *** *** *** ***

fgu_fpy_dp_msff_macro__stack_88c__width_64	i_a1_be_ff		 (
  .scan_in(i_a1_be_ff_scanin),
  .scan_out(i_a1_be_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ({xr_mode_fx1_		,
         be_pout[26:18]		,
         be26[4:0]		,
         be25[4:0]		,
         be24[4:0]		,
         be23[4:0]		,
         be22[4:0]		,
         be21[4:0]		,
         be20[4:0]		,
         be19[4:0]		,
         be18[4:0]		,
         be_hout[25:17]}			),
  .dout({a1_xr_mode_fx2_	,
         be_pout_ff[26:18]	,
         be_ff26[4:0]		,
         be_ff25[4:0]		,
         be_ff24[4:0]		,
         be_ff23[4:0]		,
         be_ff22[4:0]		,
         be_ff21[4:0]		,
         be_ff20[4:0]		,
         be_ff19[4:0]		,
         be_ff18[4:0]		,
         be_hout_ff[25:17]}			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_2	i_a1_rs2_fx1_ebuf	 (
  .din ({rs2_fx1_ebf[63]    ,rs2_fx1_ebf[47]}		),
  .dout({rs2_fx1_ebf1[63]   ,rs2_fx1_ebf1[47]}		));


fgu_fpy_dp_msff_macro__mux_aope__ports_4__stack_88c__width_64	i_a1_rs2_ff		 (
  .scan_in(i_a1_rs2_ff_scanin),
  .scan_out(i_a1_rs2_ff_scanout),
  .clk ( l2clk								),
  .en  ( mul_clken_rep0							),
  .din0({{32{1'b0}},{17{rs2_fx1_ebf1[63]}},fad_rs2_fmt_fx1_rep0[62:48]}	),
  .din1({{32{1'b0}},{17{rs2_fx1_ebf1[47]}},fad_rs2_fmt_fx1_rep0[46:32]}	),
  .din2( spu_fgu_rs2_fx1[63:0]						),
  .din3( fad_rs2_fmt_fx1_rep0[63:0]					),
  .sel0( fac_rs2_sel_fx1[0]						),
  .sel1( fac_rs2_sel_fx1[2]						),
  .sel2( fac_rs2_sel_fx1[3]						),
  .dout( a1_rs2_ff[63:0]						),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_64	i_a1_rs2_buf		 (
  .din ( a1_rs2_ff[63:0]			),
  .dout( a1_rs2[63:0]				));

fgu_fpy_dp_inv_macro__stack_88c__width_64	i_a1_rs2_inv		 (
  .din ( a1_rs2_ff[63:0]			),
  .dout( a1_rs2_[63:0]				));


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_18		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff18[0]                          ),
  .sel1( be_ff18[1]                          ),
  .sel2( be_ff18[2]                          ),
  .sel3( be_ff18[3]                          ),
  .sel4( be_ff18[4]                          ),
  .dout( bm18[100:36]                        ));

  assign bm18[102:101]	= { a1_xr_mode_fx2_ , be_pout_ff[18]};	// 1P
  assign bm18[35:34]	= { 1'b0            , be_hout_ff[17]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_19		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff19[0]                          ),
  .sel1( be_ff19[1]                          ),
  .sel2( be_ff19[2]                          ),
  .sel3( be_ff19[3]                          ),
  .sel4( be_ff19[4]                          ),
  .dout( bm19[102:38]                        ));

  assign bm19[104:103]	= { a1_xr_mode_fx2_ , be_pout_ff[19]};	// 1P
  assign bm19[37:36]	= { 1'b0            , be_hout_ff[18]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_20		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff20[0]                          ),
  .sel1( be_ff20[1]                          ),
  .sel2( be_ff20[2]                          ),
  .sel3( be_ff20[3]                          ),
  .sel4( be_ff20[4]                          ),
  .dout( bm20[104:40]                        ));

  assign bm20[106:105]	= { a1_xr_mode_fx2_ , be_pout_ff[20]};	// 1P
  assign bm20[39:38]	= { 1'b0            , be_hout_ff[19]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_21		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff21[0]                          ),
  .sel1( be_ff21[1]                          ),
  .sel2( be_ff21[2]                          ),
  .sel3( be_ff21[3]                          ),
  .sel4( be_ff21[4]                          ),
  .dout( bm21[106:42]                        ));

  assign bm21[108:107]	= { a1_xr_mode_fx2_ , be_pout_ff[21]};	// 1P
  assign bm21[41:40]	= { 1'b0            , be_hout_ff[20]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_22		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff22[0]                          ),
  .sel1( be_ff22[1]                          ),
  .sel2( be_ff22[2]                          ),
  .sel3( be_ff22[3]                          ),
  .sel4( be_ff22[4]                          ),
  .dout( bm22[108:44]                        ));

  assign bm22[110:109]	= { a1_xr_mode_fx2_ , be_pout_ff[22]};	// 1P
  assign bm22[43:42]	= { 1'b0            , be_hout_ff[21]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_23		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff23[0]                          ),
  .sel1( be_ff23[1]                          ),
  .sel2( be_ff23[2]                          ),
  .sel3( be_ff23[3]                          ),
  .sel4( be_ff23[4]                          ),
  .dout( bm23[110:46]                        ));

  assign bm23[112:111]	= { a1_xr_mode_fx2_ , be_pout_ff[23]};	// 1P
  assign bm23[45:44]	= { 1'b0            , be_hout_ff[22]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_24		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff24[0]                          ),
  .sel1( be_ff24[1]                          ),
  .sel2( be_ff24[2]                          ),
  .sel3( be_ff24[3]                          ),
  .sel4( be_ff24[4]                          ),
  .dout( bm24[112:48]                        ));

  assign bm24[114:113]	= { a1_xr_mode_fx2_ , be_pout_ff[24]};	// 1P
  assign bm24[47:46]	= { 1'b0            , be_hout_ff[23]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_25		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff25[0]                          ),
  .sel1( be_ff25[1]                          ),
  .sel2( be_ff25[2]                          ),
  .sel3( be_ff25[3]                          ),
  .sel4( be_ff25[4]                          ),
  .dout( bm25[114:50]                        ));

  assign bm25[116:115]	= { a1_xr_mode_fx2_ , be_pout_ff[25]};	// 1P
  assign bm25[49:48]	= { 1'b0            , be_hout_ff[24]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a1_bm_26		  (
  .din0({1'b0        , a1_rs2[63:0]         }),		// +1 * rs2
  .din1({              a1_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a1_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a1_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff26[0]                          ),
  .sel1( be_ff26[1]                          ),
  .sel2( be_ff26[2]                          ),
  .sel3( be_ff26[3]                          ),
  .sel4( be_ff26[4]                          ),
  .dout( bm26[116:52]                        ));

  assign bm26[118:117]	= { a1_xr_mode_fx2_ , be_pout_ff[26]};	// 1P
  assign bm26[51:50]	= { 1'b0            , be_hout_ff[25]};


//	bm18[102:34]	bm19[104:36]	bm20[106:38]

fgu_fpy_dp_csa32_macro__stack_88c__width_69	a1_csa1_7		 (
 .i0   ({ { 2{1'b0}}, bm18[102:36]                   }),
 .i1   ({             bm19[104:36]                   }),
 .i2   ({             bm20[104:38]      , { 2{1'b0}} }),
 .carry(              a1_csa1_7_c[105:37]             ),
 .sum  (              a1_csa1_7_s[104:36]             ));

  assign a1_csa1_7_s[35:34]	= bm18[35:34];
  assign a1_csa1_7_s[106:105]	= bm20[106:105];


//	bm21[108:40]	bm22[110:42]	bm23[112:44]

fgu_fpy_dp_csa32_macro__stack_88c__width_69	a1_csa1_8		 (
 .i0   ({ { 2{1'b0}}, bm21[108:42]                   }),
 .i1   ({             bm22[110:42]                   }),
 .i2   ({             bm23[110:44]      , { 2{1'b0}} }),
 .carry(              a1_csa1_8_c[111:43]             ),
 .sum  (              a1_csa1_8_s[110:42]             ));

  assign a1_csa1_8_s[41:40]	= bm21[41:40];
  assign a1_csa1_8_s[112:111]	= bm23[112:111];


//	bm24[114:46]	bm25[116:48]	bm26[118:50]

fgu_fpy_dp_csa32_macro__stack_88c__width_69	a1_csa1_9		 (
 .i0   ({ { 2{1'b0}}, bm24[114:48]                   }),
 .i1   ({             bm25[116:48]                   }),
 .i2   ({             bm26[116:50]      , { 2{1'b0}} }),
 .carry(              a1_csa1_9_c[117:49]             ),
 .sum  (              a1_csa1_9_s[116:48]             ));

  assign a1_csa1_9_s[47:46]	= bm24[47:46];
  assign a1_csa1_9_s[118:117]	= bm26[118:117];


//		*** 1st level to 2nd level ***
//
//	csa1_7_s[106:34]	csa1_7_c[105:37]
//	csa1_8_s[112:40]	csa1_8_c[111:43]
//	csa1_9_s[118:46]	csa1_9_c[117:49]


fgu_fpy_dp_csa32_macro__stack_88c__width_73	a1_csa2_5		 (
 .i0   ({ { 6{1'b0}}, a1_csa1_7_s[106:40]            }),
 .i1   ({             a1_csa1_8_s[112:40]            }),
 .i2   ({             a1_csa1_9_s[112:46],{ 6{1'b0}} }),
 .carry(              a1_csa2_5_c[113:41]             ),
 .sum  (              a1_csa2_5_s[112:40]             ));

  assign a1_csa2_5_s[39:34]	= a1_csa1_7_s[39:34];
  assign a1_csa2_5_s[118:113]	= a1_csa1_9_s[118:113];


fgu_fpy_dp_csa32_macro__stack_88c__width_69	a1_csa2_6		 (
 .i0   ({ { 6{1'b0}}, a1_csa1_7_c[105:43]            }),
 .i1   ({             a1_csa1_8_c[111:43]            }),
 .i2   ({             a1_csa1_9_c[111:49],{ 6{1'b0}} }),
 .carry(              a1_csa2_6_c[112:44]             ),
 .sum  (              a1_csa2_6_s[111:43]             ));

  assign a1_csa2_6_s[42:37]	= a1_csa1_7_c[42:37];
  assign a1_csa2_6_s[117:112]	= a1_csa1_9_c[117:112];


//		*** 2nd level to 3rd level ***
//
//	csa2_5_s[118:34]	csa2_5_c[113:41]
//	csa2_6_s[117:37]	csa2_6_c[112:44]


fgu_fpy_dp_csa42_macro__stack_88c__width_81	a1_csa3_3		 (
 .i0   ({             a1_csa2_5_s[117:37]             }),
 .i1   ({ { 4{1'b0}}, a1_csa2_5_c[113:41], { 4{1'b0}} }),
 .i2   ({ { 5{1'b0}}, a1_csa2_6_c[112:44], { 7{1'b0}} }),
 .i3   ({             a1_csa2_6_s[117:37]             }),
 .cin  (     1'b0                                      ), // 1 bit
 .cout ( a1_csa3_3_unused                              ), // 1 bit
 .carry( a1_csa3_3_c[118:38]                           ),
 .sum  ( a1_csa3_3_s[117:37]                           ));

  assign a1_csa3_3_s[36:34]	= a1_csa2_5_s[36:34];
  assign a1_csa3_3_s[118]	= a1_csa2_5_s[118];


fgu_fpy_dp_msff_macro__stack_88c__width_41	i_a1_s_ff_a		 (
  .scan_in(i_a1_s_ff_a_scanin),
  .scan_out(i_a1_s_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a1_csa3_3_s[118:78]			),	// [118] and [36:34] are early
  .dout( a1_csa3_3_s_ff[118:78]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a1_s_ff_b		 (
  .scan_in(i_a1_s_ff_b_scanin),
  .scan_out(i_a1_s_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( a1_csa3_3_s[77:34]			),	// [118] and [36:34] are early
  .dout( a1_csa3_3_s_ff[77:34]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__stack_88c__width_37	i_a1_c_ff_a		 (
  .scan_in(i_a1_c_ff_a_scanin),
  .scan_out(i_a1_c_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a1_csa3_3_c[118:82]			),
  .dout( a1_csa3_3_c_ff[118:82]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a1_c_ff_b		 (
  .scan_in(i_a1_c_ff_b_scanin),
  .scan_out(i_a1_c_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( a1_csa3_3_c[81:38]			),
  .dout( a1_csa3_3_c_ff[81:38]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// *** *** *** *** *** *** *** *** End   : "A1" 9:2 CSA Tree  *** *** *** *** *** ***


fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_63	a10_xor4_2		 (
  .din0( a1_csa2_5_s[116:54]			),
  .din1( a0_xr_in[116:54]			),
  .dout( a10_xr4_2[116:54]			));

  assign a10_xr4_2[53:36]	= a1_csa2_5_s[53:36];
  assign a10_xr4_2[126:117]	= a0_xr_in[126:117];


fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a10_x_ff_a		 (
  .scan_in(i_a10_x_ff_a_scanin),
  .scan_out(i_a10_x_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a10_xr4_2[123:80]			),
  .dout( a10_xr_ff[123:80]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a10_x_ff_b		 (
  .scan_in(i_a10_x_ff_b_scanin),
  .scan_out(i_a10_x_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ( a10_xr4_2[79:36]			),
  .dout( a10_xr_ff[79:36]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// *** *** *** *** *** *** *** *** Start : "A0" 6:2 CSA Tree  *** *** *** *** *** ***

fgu_fpy_dp_msff_macro__stack_88c__width_41	i_a0_be_ff		 (
  .scan_in(i_a0_be_ff_scanin),
  .scan_out(i_a0_be_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din ({a10_xr4_2[126:124]	,
         xr_mode_fx1_		,
         be_pout[31:27]		,
         be32_b0		,
         be31[4:0]		,
         be30[4:0]		,
         be29[4:0]		,
         be28[4:0]		,
         be27[4:0]		,
         be_hout[31:26]}			),
  .dout({a10_xr_ff[126:124]	,
         a0_xr_mode_fx2_	,
         be_pout_ff[31:27]	,
         be_ff32_b0		,
         be_ff31[4:0]		,
         be_ff30[4:0]		,
         be_ff29[4:0]		,
         be_ff28[4:0]		,
         be_ff27[4:0]		,
         be_hout_ff[31:26]}			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_2	i_a0_rs2_fx1_ebuf	 (
  .din ({rs2_fx1_ebf[63]    ,rs2_fx1_ebf[47]}		),
  .dout({rs2_fx1_ebf0[63]   ,rs2_fx1_ebf0[47]}		));


fgu_fpy_dp_msff_macro__mux_aope__ports_4__stack_88c__width_64	i_a0_rs2_ff		 (
  .scan_in(i_a0_rs2_ff_scanin),
  .scan_out(i_a0_rs2_ff_scanout),
  .clk ( l2clk								),
  .en  ( mul_clken_rep0							),
  .din0({{32{1'b0}},{17{rs2_fx1_ebf0[47]}},fad_rs2_fmt_fx1_rep0[46:32]}	),
  .din1({{32{1'b0}},{17{rs2_fx1_ebf0[63]}},fad_rs2_fmt_fx1_rep0[62:48]}	),
  .din2( spu_fgu_rs2_fx1[63:0]						),
  .din3( fad_rs2_fmt_fx1_rep0[63:0]					),
  .sel0( fac_rs2_sel_fx1[1]						),
  .sel1( fac_rs2_sel_fx1[2]						),
  .sel2( fac_rs2_sel_fx1[3]						),
  .dout( a0_rs2_ff[63:0]						),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_buff_macro__stack_88c__width_64	i_a0_rs2_buf		 (
  .din ( a0_rs2_ff[63:0]			),
  .dout( a0_rs2[63:0]				));

fgu_fpy_dp_inv_macro__stack_88c__width_64	i_a0_rs2_inv		 (
  .din ( a0_rs2_ff[63:0]			),
  .dout( a0_rs2_[63:0]				));


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a0_bm_27		  (
  .din0({1'b0        , a0_rs2[63:0]         }),		// +1 * rs2
  .din1({              a0_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a0_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a0_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff27[0]                          ),
  .sel1( be_ff27[1]                          ),
  .sel2( be_ff27[2]                          ),
  .sel3( be_ff27[3]                          ),
  .sel4( be_ff27[4]                          ),
  .dout( bm27[118:54]                        ));

  assign bm27[120:119]	= { a0_xr_mode_fx2_ , be_pout_ff[27]};	// 1P
  assign bm27[53:52]	= { 1'b0            , be_hout_ff[26]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a0_bm_28		  (
  .din0({1'b0        , a0_rs2[63:0]         }),		// +1 * rs2
  .din1({              a0_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a0_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a0_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff28[0]                          ),
  .sel1( be_ff28[1]                          ),
  .sel2( be_ff28[2]                          ),
  .sel3( be_ff28[3]                          ),
  .sel4( be_ff28[4]                          ),
  .dout( bm28[120:56]                        ));

  assign bm28[122:121]	= { a0_xr_mode_fx2_ , be_pout_ff[28]};	// 1P
  assign bm28[55:54]	= { 1'b0            , be_hout_ff[27]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a0_bm_29		  (
  .din0({1'b0        , a0_rs2[63:0]         }),		// +1 * rs2
  .din1({              a0_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a0_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a0_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff29[0]                          ),
  .sel1( be_ff29[1]                          ),
  .sel2( be_ff29[2]                          ),
  .sel3( be_ff29[3]                          ),
  .sel4( be_ff29[4]                          ),
  .dout( bm29[122:58]                        ));

  assign bm29[124:123]	= { a0_xr_mode_fx2_ , be_pout_ff[29]};	// 1P
  assign bm29[57:56]	= { 1'b0            , be_hout_ff[28]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a0_bm_30		  (
  .din0({1'b0        , a0_rs2[63:0]         }),		// +1 * rs2
  .din1({              a0_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a0_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a0_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff30[0]                          ),
  .sel1( be_ff30[1]                          ),
  .sel2( be_ff30[2]                          ),
  .sel3( be_ff30[3]                          ),
  .sel4( be_ff30[4]                          ),
  .dout( bm30[124:60]                        ));

  assign bm30[126:125]	= { a0_xr_mode_fx2_ , be_pout_ff[30]};	// 1P
  assign bm30[59:58]	= { 1'b0            , be_hout_ff[29]};


fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65	i_a0_bm_31		  (
  .din0({1'b0        , a0_rs2[63:0]         }),		// +1 * rs2
  .din1({              a0_rs2[63:0]  , 1'b0 }),		// +2 * rs2
  .din2({              a0_rs2_[63:0] , 1'b1 }),		// -2 * rs2
  .din3({1'b1        , a0_rs2_[63:0]        }),		// -1 * rs2
  .din4( rs2_3x[64:0]                        ),		// +3 * rs2
  .sel0( be_ff31[0]                          ),
  .sel1( be_ff31[1]                          ),
  .sel2( be_ff31[2]                          ),
  .sel3( be_ff31[3]                          ),
  .sel4( be_ff31[4]                          ),
  .dout( bm31[126:62]                        ));

  assign bm31[127]	= {                   be_pout_ff[31]};	// 1P
  assign bm31[61:60]	= { 1'b0            , be_hout_ff[30]};


fgu_fpy_dp_mux_macro__mux_aope__ports_2__stack_88c__width_64	i_a0_bm_32		  (
  .din0({              a0_rs2[63:0]         }),		// +1 * rs2
  .din1( {64{1'b0}}                          ),
  .sel0( be_ff32_b0                          ),
  .dout( bm32[127:64]                        ));

  assign bm32[135:128]	= {8{a0_xr_mode_fx2_}                };	// Extend beyond ACCUM range
  assign bm32[63:62]	= { 1'b0            , be_hout_ff[31]};


//	bm27[120:52]	bm28[122:54]	bm29[124:56]

fgu_fpy_dp_csa32_macro__stack_88c__width_69	a0_csa2_7		 (
 .i0   ({ { 2{1'b0}}, bm27[120:54]                   }),
 .i1   ({             bm28[122:54]                   }),
 .i2   ({             bm29[122:56]      , { 2{1'b0}} }),
 .carry(              a0_csa2_7_c[123:55]             ),
 .sum  (              a0_csa2_7_s[122:54]             ));

  assign a0_csa2_7_s[53:52]	= bm27[53:52];
  assign a0_csa2_7_s[124:123]	= bm29[124:123];


//	bm30[126:58]	bm31[127:60]	bm32[135:62]

fgu_fpy_dp_csa32_macro__stack_88c__width_68	a0_csa2_8		 (
 .i0   ({ { 1{1'b0}}, bm30[126:60]                   }),
 .i1   ({             bm31[127:60]                   }),
 .i2   ({             bm32[127:62]      , { 2{1'b0}} }),
 .carry(                      a0_csa2_8_c[128:61]     ),
 .sum  (                      a0_csa2_8_s[127:60]     ));

  assign a0_csa2_8_s[59:58]	= bm30[59:58];
  assign a0_csa2_8_s[135:128]	= bm32[135:128];


//		*** 2nd level to 3rd level ***
//
//	csa2_7_s[124:52]	csa2_7_c[123:55]
//	csa2_8_s[135:58]	csa2_8_c[128:61]


fgu_fpy_dp_csa42_macro__stack_88c__width_74	a0_csa3_4		 (
 .i0   ({ { 4{1'b0}}, a0_csa2_7_s[124:55]             }),
 .i1   ({ { 5{1'b0}}, a0_csa2_7_c[123:55]             }),
 .i2   ({             a0_csa2_8_c[128:61], { 6{1'b0}} }),
 .i3   ({             a0_csa2_8_s[128:58], { 3{1'b0}} }),
 .cin  (     1'b0                                      ), // 1 bit
 .cout ( a0_csa3_4_unused                              ), // 1 bit
 .carry(                      a0_csa3_4_c[129:56]      ),
 .sum  (                      a0_csa3_4_s[128:55]      ));

  assign a0_csa3_4_s[54:52]	= a0_csa2_7_s[54:52];
  assign a0_csa3_4_s[135:129]	= a0_csa2_8_s[135:129];


// a0_csa2_7_s[122:54]	a0_csa2_8_s[126:60]

fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_63	a0_xor3_0		 (
  .din0( a0_csa2_7_s[122:60]			),
  .din1( a0_csa2_8_s[122:60]			),
  .dout( a0_xr_in[122:60]			));

  assign a0_xr_in[59:54]	= a0_csa2_7_s[59:54];
  assign a0_xr_in[126:123]	= a0_csa2_8_s[126:123];


fgu_fpy_dp_msff_macro__stack_88c__width_40	i_a0_s_ff_a		 (
  .scan_in(i_a0_s_ff_a_scanin),
  .scan_out(i_a0_s_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din ( a0_csa3_4_s[135:96]			),
  .dout( a0_csa3_4_s_ff[135:96]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a0_s_ff_b		 (
  .scan_in(i_a0_s_ff_b_scanin),
  .scan_out(i_a0_s_ff_b_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0 			),
  .din ( a0_csa3_4_s[95:52]			),
  .dout( a0_csa3_4_s_ff[95:52]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__stack_88c__width_36	i_a0_c_ff_a		 (
  .scan_in(i_a0_c_ff_a_scanin),
  .scan_out(i_a0_c_ff_a_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep01			),
  .din (a0_csa3_4_c[129:94]                     ),
  .dout(a0_csa3_4_c_ff[129:94]                  ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

fgu_fpy_dp_msff_macro__stack_88c__width_44	i_a0_c_ff_b		 (
  .scan_in(i_a0_c_ff_b_scanin),
  .scan_out(i_a0_c_ff_b_scanout),
  .clk ( l2clk							),
  .en  ( mul_clken_rep0						),
  .din ({a0_csa3_4_c[93:87]    , fac_accum_sel_fx3[6:2] , fac_accum_sel_fx3[0] , a0_csa3_4_c[86:56]}    ),
  .dout({a0_csa3_4_c_ff[93:87] ,     accum_sel_fx4[6:2] ,     accum_sel_fx4_b0 , a0_csa3_4_c_ff[86:56]} ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));
 

// *** *** *** *** *** *** *** *** End   : "A0" 6:2 CSA Tree  *** *** *** *** *** ***


// *** *** *** *** *** *** *** *** Start : "A4" 8:2 CSA Tree  *** *** *** *** *** ***


//			*** 8x16 3rd level to 4th level ***
//
// Define Raw Result = {M3,M2,M1,M0}
//
// M0 =		a3_csa3_1_s_ff[31:0]		a3_csa3_1_c_ff[31:2]
// M1 =		a2_csa3_2_s_ff[49:18]		a2_csa3_2_c_ff[49:20]
// M2 =		a1_csa3_3_s_ff[67:36]		a1_csa3_3_c_ff[67:38]
// M3 =		a0_csa3_4_s_ff[85:54]		a0_csa3_4_c_ff[85:56]


fgu_fpy_dp_csa32_macro__stack_88c__width_25	a4_8x16csa4_1		 (
 .i0   ({             a3_csa3_1_s_ff[31:7]             }),
 .i1   ({             a3_csa3_1_c_ff[31:7]             }),
 .i2   ({ {16{1'b0}}, fac_8x16_rnd_fx3[1],
          { 7{1'b0}}, fac_8x16_rnd_fx3[0]              }),
 .carry({ a4_8x16csa4_1_unused , a4_8x16csa4_1_c[31:8]}),
 .sum  (                         a4_8x16csa4_1_s[31:7] ));

  assign a4_8x16csa4_1_s[6:0]	= a3_csa3_1_s_ff[6:0];
  assign a4_8x16csa4_1_c[7]	= 1'b0;
  assign a4_8x16csa4_1_c[6:2]	= a3_csa3_1_c_ff[6:2];


fgu_fpy_dp_csa32_macro__stack_88c__width_25	a4_8x16csa4_2		 (
 .i0   ({             a2_csa3_2_s_ff[49:25]            }),
 .i1   ({             a2_csa3_2_c_ff[49:25]            }),
 .i2   ({ {16{1'b0}}, fac_8x16_rnd_fx3[1],
          { 7{1'b0}}, fac_8x16_rnd_fx3[0]              }),
 .carry({ a4_8x16csa4_2_unused , a4_8x16csa4_2_c[49:26]}),
 .sum  (                         a4_8x16csa4_2_s[49:25] ));

  assign a4_8x16csa4_2_s[24:18]	= a2_csa3_2_s_ff[24:18];
  assign a4_8x16csa4_2_c[25]	= 1'b0;
  assign a4_8x16csa4_2_c[24:20]	= a2_csa3_2_c_ff[24:20];


fgu_fpy_dp_csa32_macro__stack_88c__width_25	a4_8x16csa4_3		 (
 .i0   ({             a1_csa3_3_s_ff[67:43]            }),
 .i1   ({             a1_csa3_3_c_ff[67:43]            }),
 .i2   ({ {16{1'b0}}, fac_8x16_rnd_fx3[1],
          { 7{1'b0}}, fac_8x16_rnd_fx3[0]              }),
 .carry({ a4_8x16csa4_3_unused , a4_8x16csa4_3_c[67:44]}),
 .sum  (                         a4_8x16csa4_3_s[67:43] ));

  assign a4_8x16csa4_3_s[42:36]	= a1_csa3_3_s_ff[42:36];
  assign a4_8x16csa4_3_c[43]	= 1'b0;
  assign a4_8x16csa4_3_c[42:38]	= a1_csa3_3_c_ff[42:38];


fgu_fpy_dp_csa32_macro__stack_88c__width_25	a4_8x16csa4_4		 (
 .i0   ({             a0_csa3_4_s_ff[85:61]            }),
 .i1   ({             a0_csa3_4_c_ff[85:61]            }),
 .i2   ({ {16{1'b0}}, fac_8x16_rnd_fx3[1],
          { 7{1'b0}}, fac_8x16_rnd_fx3[0]              }),
 .carry({ a4_8x16csa4_4_unused , a4_8x16csa4_4_c[85:62]}),
 .sum  (                         a4_8x16csa4_4_s[85:61] ));

  assign a4_8x16csa4_4_s[60:54]	= a0_csa3_4_s_ff[60:54];
  assign a4_8x16csa4_4_c[61]	= 1'b0;
  assign a4_8x16csa4_4_c[60:56]	= a0_csa3_4_c_ff[60:56];


//			*** XOR 4th level to 5th level ***
//


fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_63	a4_xor5_1		 (
  .din0( a32_xr_ff[98:36]			),
  .din1( a10_xr_ff[98:36]			),
  .dout( a4_xr5_1[98:36]			));

  assign a4_xr5_1[35:0]	= a32_xr_ff[35:0];
  assign a4_xr5_1[126:99]	= a10_xr_ff[126:99];


//			*** 4th level to 5th level ***
//
//	a3_csa3_1_s_ff[82:0]		a3_csa3_1_c_ff[82:2]
//	a2_csa3_2_s_ff[100:16]		a2_csa3_1_c_ff[100:20]
//
//	a1_csa3_3_s_ff[118:34]		a1_csa3_3_c_ff[118:38]
//	a0_csa3_4_s_ff[135:52]		a0_csa3_4_c_ff[129:56]


fgu_fpy_dp_csa42_macro__stack_88c__width_3	a4_csa4_1a		 (
 .i0   ({ { 3{1'b0}}                                     }),
 .i1   ({ { 3{1'b0}}                                     }),
 .i2   ({             a2_csa3_2_c_ff[100:98]             }),
 .i3   ({             a2_csa3_2_s_ff[100:98]             }),
 .cin  ( a4_csa4_1b_cout                                  ), // 1 bit
 .cout ( a4_csa4_1a_unused                                ), // 1 bit
 .carry(                      a4_csa4_1_c[101:99]         ),
 .sum  (                      a4_csa4_1_s[100:98]         ));


fgu_fpy_dp_csa42_macro__stack_96c__width_96	a4_csa4_1b		 (
 .i0   ({ {15{1'b0}}, a3_csa3_1_s_ff[82:2]              }),
 .i1   ({ {15{1'b0}}, a3_csa3_1_c_ff[82:2]              }),
 .i2   ({             a2_csa3_2_c_ff[97:20] , {18{1'b0}} }),
 .i3   ({             a2_csa3_2_s_ff[97:16] , {14{1'b0}} }),
 .cin  (     1'b0                                         ), // 1 bit
 .cout ( a4_csa4_1b_cout                                  ), // 1 bit
 .carry(                      a4_csa4_1_c[98:3]          ),
 .sum  (                      a4_csa4_1_s[97:2]          ));

  assign a4_csa4_1_s[1:0]	= a3_csa3_1_s_ff[1:0];


fgu_fpy_dp_csa42_macro__stack_96c__width_92	a4_csa4_2		 (
 .i0   ({ {11{1'b0}}, a1_csa3_3_s_ff[118:38]             }),
 .i1   ({ {11{1'b0}}, a1_csa3_3_c_ff[118:38]             }),
 .i2   ({             a0_csa3_4_c_ff[129:56], {18{1'b0}} }),
 .i3   ({             a0_csa3_4_s_ff[129:52], {14{1'b0}} }),
 .cin  (     1'b0                                         ), // 1 bit
 .cout ( a4_csa4_2_unused                                 ), // 1 bit
 .carry(                      a4_csa4_2_c[130:39]         ),
 .sum  (                      a4_csa4_2_s[129:38]         ));

  assign a4_csa4_2_s[37:34]	= a1_csa3_3_s_ff[37:34];
  assign a4_csa4_2_s[135:130]	= a0_csa3_4_s_ff[135:130];


fgu_fpy_dp_csa42_macro__stack_88c__width_32	a4_csa5_1a		 (
 .i0   ({ {30{1'b0}}, a4_csa4_1_s[100:99]                }),
 .i1   ({ {29{1'b0}}, a4_csa4_1_c[101:99]                }),
 .i2   (              a4_csa4_2_c[130:99]                 ),
 .i3   (              a4_csa4_2_s[130:99]                 ),
 .cin  ( a4_csa5_1b_cout                                  ), // 1 bit
 .cout ( a4_csa5_1a_unused                                ), // 1 bit
 .carry(                      a4_csa5_1_c[131:100]        ),
 .sum  (                      a4_csa5_1_s[130:99]         ));


fgu_fpy_dp_csa42_macro__stack_96c__width_96	a4_csa5_1b		 (
 .i0   (              a4_csa4_1_s[98:3]                  ),
 .i1   (              a4_csa4_1_c[98:3]                  ),
 .i2   ({             a4_csa4_2_c[98:39],     {36{1'b0}} }),
 .i3   ({             a4_csa4_2_s[98:34],     {31{1'b0}} }),
 .cin  (     1'b0                                         ), // 1 bit
 .cout ( a4_csa5_1b_cout                                  ), // 1 bit
 .carry(                      a4_csa5_1_c[99:4]          ),
 .sum  (                      a4_csa5_1_s[98:3]          ));

  assign a4_csa5_1_s[2:0]	= a4_csa4_1_s[2:0];
  assign a4_csa5_1_s[135:131]	= a4_csa4_2_s[135:131];


fgu_fpy_dp_msff_macro__mux_aope__ports_5__stack_88c__width_64	i_a4_s_lo_ff		 (
  .scan_in(i_a4_s_lo_ff_scanin),
  .scan_out(i_a4_s_lo_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din0( a4_csa5_1_s[63:0]			),	// Integer, Float, MA Integer
  .din1({a4_8x16csa4_2_s[48:18],
         1'b0,
         a4_8x16csa4_1_s[31:0]}			),	// 8x16
  .din2({a4_csa5_1_s[62:0] , 1'b0}		),	// MA Integer   * 2
  .din3( a4_xr5_1[63:0]				),	// XOR multiply
  .din4({a4_xr5_1[62:0]    , 1'b0}		),	// XOR multiply * 2
  .sel0( fac_scff_sel_fx3[0]			),
  .sel1( fac_scff_sel_fx3[1]			),
  .sel2( fac_scff_sel_fx3[2]			),
  .sel3( fac_scff_sel_fx3[3]			),
  .dout( a4_csa5_1_s_ff[63:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__mux_aope__ports_5__stack_88c__width_72	i_a4_s_hi_ff		 (
  .scan_in(i_a4_s_hi_ff_scanin),
  .scan_out(i_a4_s_hi_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din0({a4_csa5_1_s[135:134],
	 a4_csa5_1_s[133:64]}			),	// Integer, Float, MA Integer
  .din1({2'b00,
	 3'b000,
         a4_8x16csa4_4_s[85:54],
         1'b0,
         a4_8x16csa4_3_s[67:36],
         1'b0,
         a4_8x16csa4_2_s[49]}			),	// 8x16
  .din2({a4_csa5_1_s[134:133],
	 a4_csa5_1_s[132:63]}			),	// MA Integer   * 2
  .din3({2'b00,
	 3'b000,
         4'b0000,a4_xr5_1[126:64]}		),	// XOR multiply
  .din4({2'b00,
	 3'b000,
         3'b000 ,a4_xr5_1[126:63]}		),	// XOR multiply * 2
  .sel0( fac_scff_sel_fx3[0]			),
  .sel1( fac_scff_sel_fx3[1]			),
  .sel2( fac_scff_sel_fx3[2]			),
  .sel3( fac_scff_sel_fx3[3]			),
  .dout( a4_csa5_1_s_ff[135:64] 		),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__mux_aonpe__ports_3__stack_88c__width_62	i_a4_c_lo_ff		 (
  .scan_in(i_a4_c_lo_ff_scanin),
  .scan_out(i_a4_c_lo_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din0({a4_csa5_1_c[63:4],2'b00}		),	// Integer, Float, MA Integer
  .din1({a4_8x16csa4_2_c[48:20],2'b00,
         1'b0,
         a4_8x16csa4_1_c[31:2]}		),	// 8x16
  .din2({a4_csa5_1_c[62:4],3'b000}		),	// MA Integer   * 2
  .sel0( fac_scff_sel_fx3[0]			),
  .sel1( fac_scff_sel_fx3[1]			),
  .sel2( fac_scff_sel_fx3[2]			),
  .dout( a4_csa5_1_c_ff[63:2]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

  assign a4_csa5_1_c_ff[1:0]	= 2'b00;


fgu_fpy_dp_msff_macro__mux_aonpe__ports_3__stack_88c__width_69	i_a4_c_hi_ff		 (
  .scan_in(i_a4_c_hi_ff_scanin),
  .scan_out(i_a4_c_hi_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din0({1'b0,
	 a4_csa5_1_c[131:64]}			),	// Integer, Float, MA Integer
  .din1({1'b0,
	 1'b0,a4_8x16csa4_4_c[85:56],2'b00,
         1'b0,
	 a4_8x16csa4_3_c[67:38],3'b000,
	 a4_8x16csa4_2_c[49]}			),	// 8x16
  .din2({a4_csa5_1_c[131],
	 a4_csa5_1_c[130:63]}			),	// MA Integer   * 2
  .sel0( fac_scff_sel_fx3[0]			),
  .sel1( fac_scff_sel_fx3[1]			),
  .sel2( fac_scff_sel_fx3[2]			),
  .dout( a4_csa5_1_c_ff[132:64]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// *** *** *** *** *** *** *** *** End   : "A4" 8:2 CSA Tree  *** *** *** *** *** ***


// *** *** *** *** *** *** *** *** Start : Accumulator        *** *** *** *** *** ***


fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_63	i_fx4_xor0		 (
  .din0( a4_csa5_1_s_ff[126:64]			),
  .din1( accum_ff[126:64]			),
  .dout( xr_fx4[126:64]				));


fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_64	i_fx4_xor1		 (
  .din0( a4_csa5_1_s_ff[63:0]			),
  .din1( accum_ff[63:0]				),
  .dout( xr_fx4[63:0]				));


fgu_fpy_dp_msff_macro__mux_aope__ports_6__stack_88c__width_72	i_accum_ff0		 (
  .scan_in(i_accum_ff0_scanin),
  .scan_out(i_accum_ff0_scanout),
  .clk ( l2clk					),
  .en  ( accum_sel_fx4_b0			),
  .din0({{ 9{1'b0}},xr_fx4[126:64]}		),	// XOR w/        ACCUM and >> 0
  .din1( {72{1'b0}}                  		),	// XOR w/        ACCUM and >> 64
  .din2({{ 9{1'b0}},xr_fx4[126:64]}		),	// XOR       w/o ACCUM and >> 0
  .din3( {72{1'b0}}                 		),	// XOR       w/o ACCUM and >> 64
  .din4( fya_add_result[135:64]			),	// Int w/ or w/o ACCUM and >> 0
  .din5({{64{1'b0}},fya_add_result[135:128]}	),	// Int w/ or w/o ACCUM and >> 64
  .sel0( accum_sel_fx4[2]			),
  .sel1( accum_sel_fx4[3]			),
  .sel2( accum_sel_fx4[4]			),
  .sel3( accum_sel_fx4[5]			),
  .sel4( accum_sel_fx4[6]			),
  .dout( accum_ff[135:64]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__mux_aope__ports_6__stack_88c__width_64	i_accum_ff1		 (
  .scan_in(i_accum_ff1_scanin),
  .scan_out(i_accum_ff1_scanout),
  .clk ( l2clk					),
  .en  ( accum_sel_fx4_b0			),
  .din0( xr_fx4[63:0]				),	// XOR w/        ACCUM and >> 0
  .din1({1'b0,xr_fx4[126:64]}			),	// XOR w/        ACCUM and >> 64
  .din2( xr_fx4[63:0]				),	// XOR       w/o ACCUM and >> 0
  .din3({1'b0,xr_fx4[126:64]}			),	// XOR       w/o ACCUM and >> 64
  .din4( fya_add_result[63:0]			),	// Int w/ or w/o ACCUM and >> 0
  .din5( fya_add_result[127:64]			),	// Int w/ or w/o ACCUM and >> 64
  .sel0( accum_sel_fx4[2]			),
  .sel1( accum_sel_fx4[3]			),
  .sel2( accum_sel_fx4[4]			),
  .sel3( accum_sel_fx4[5]			),
  .sel4( accum_sel_fx4[6]			),
  .dout( accum_ff[63:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


assign fgu_accum_b0_fx5	= accum_ff[0];

// *** *** *** *** *** *** *** *** End   : Accumulator        *** *** *** *** *** ***


fgu_fpy_dp_msff_macro__stack_88c__width_4	i_accum_sel_b1_ff	 (
  .scan_in(i_accum_sel_b1_ff_scanin),
  .scan_out(i_accum_sel_b1_ff_scanout),
  .clk ( l2clk			    ),
  .en  ( mul_clken_rep0		    ),
  .din ({4{fac_accum_sel_fx3[1]}}   ),
  .dout(       accum_sel_fx4_b1[3:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// *** *** *** *** *** *** *** *** Start : Custom add136      *** *** *** *** *** ***


cl_dp1_add136_8x	fya		(
  .din0     ( a4_csa5_1_s_ff[135:0]		),
  .din1     ( a4_csa5_1_c_ff[132:0]		),
  .din2     ( accum_ff[135:0]			),
  .sel_din2 ( accum_sel_fx4_b1[3:0]		),
     .sum            ( fya_add_result[135:0]		),
     .fya_sticky_dp  ( fya_sticky_dp			),
     .fya_sticky_sp  ( fya_sticky_sp			),
     .fya_xicc_z     ( fya_xicc_z[1:0]                  ));


// *** *** *** *** *** *** *** *** End   : Custom add136      *** *** *** *** *** ***


// *** *** *** *** *** *** *** *** Start : Output Flop        *** *** *** *** *** ***


fgu_fpy_dp_buff_macro__stack_88c__width_1  i_fpy_fp_result_fx4_b63_buf	 (
  .din (fya_add_result[127]  ),
  .dout(fpy_fp_result_fx4_b63));

// 8x16 data is packed in FYA_ADD_RESULT as follows :
//
//     103:99  98  97:66  65  64:33  32  31:00
//     ------      -----      -----      -----
//       M3         M2         M1         M0


fgu_fpy_dp_msff_macro__mux_aope__ports_7__stack_88c__width_68	i_fx5_ff		 (
  .scan_in(i_fx5_ff_scanin),
  .scan_out(i_fx5_ff_scanout),
  .clk ( l2clk					),
  .en  ( mul_clken_rep0				),
  .din0({   2'b00			,
	    1'b0			,
	    1'b0			,
	 fya_add_result[122:107]	,
         fya_add_result[89:74]		,
         fya_add_result[56:41]		,
         fya_add_result[23:8]		}	),	// [0] : FMUL8x16   or FMUL8x16AU or FMUL8x16AL or FMUL8SUx16
  .din1({   2'b00			,
	    1'b0			,
	    1'b0			,
	 fya_add_result[130:115]	,
         fya_add_result[97:82]		,
         fya_add_result[64:49]		,
         fya_add_result[31:16]		}	),	// [1] : FMUL8ULx16
  .din2({   2'b00			,
	    1'b0			,
	    1'b0			,
	 fya_add_result[122:99],8'h00	,
         fya_add_result[89:66] ,8'h00	}	),	// [2] : FMULD8SUx16
  .din3({   2'b00			,
	    1'b0			,
	    1'b0			,
	 fya_add_result[130:99]		,
         fya_add_result[97:66]		}	),	// [3] : FMULD8ULx16
  .din4({   2'b00			,
	    1'b0			,
	    1'b0			,
	 xr_fx4[63:0]			}	),	// [4] : XOR multiply w/ ACCUMUMATE
  .din5({   2'b00			,
	 fya_sticky_sp			,
	 fya_sticky_dp			,
	 fya_add_result[127:73]		,
	 {9{1'b0}}			}	),	// [5] : Float
  .din6({fya_xicc_z[1:0]		,
	    1'b0			,
	    1'b0			,
	 fya_add_result[63:0]		}	),	// Def : Integer, MA Integer w/ and w/o ACCUMULATE, XOR w/o ACCUMULATE;
  .sel0( fac_result_sel_fx4[0]			),
  .sel1( fac_result_sel_fx4[1]			),
  .sel2( fac_result_sel_fx4[2]			),
  .sel3( fac_result_sel_fx4[3]			),
  .sel4( fac_result_sel_fx4[4]			),
  .sel5( fac_result_sel_fx4[5]			),
  .dout({fpy_xicc_z_fx5[1:0]		,
	 fpy_sticky_sp_fx5		,
	 fpy_sticky_dp_fx5		,
	 fgu_mul_result_fx5[63:0]	}	),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


fgu_fpy_dp_msff_macro__mux_aope__ports_2__stack_88c__width_64	i_ma_result_ff		 (
  .scan_in(i_ma_result_ff_scanin),
  .scan_out(i_ma_result_ff_scanout),
  .clk ( l2clk					),
  .en  ( fac_ma_result_en_fx4			),
  .din0( xr_fx4[63:0]				),	// [4] : XOR multiply w/ ACCUMUMATE
  .din1( fya_add_result[63:0]			),	// Def : MA Integer w/ and w/o ACCUMULATE, XOR w/o ACCUMULATE;
  .sel0( fac_result_sel_fx4[4]			),
  .dout( ma_result_ff[63:0]			),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// *** *** *** *** *** *** *** *** End   : Output Flop        *** *** *** *** *** ***


// fixscan start:
assign i_spu_rs1_ff_scanin       = scan_in                  ;
assign i_spu_rs2_ff_scanin       = i_spu_rs1_ff_scanout     ;
assign i_3x_ff_scanin            = i_spu_rs2_ff_scanout     ;
assign i_a3_be_ff_scanin         = i_3x_ff_scanout          ;
assign i_a3_rs2_ff_scanin        = i_a3_be_ff_scanout       ;
assign i_a3_s_ff_a_scanin        = i_a3_rs2_ff_scanout      ;
assign i_a3_s_ff_b_scanin        = i_a3_s_ff_a_scanout      ;
assign i_a3_c_ff_a_scanin        = i_a3_s_ff_b_scanout      ;
assign i_a3_c_ff_b_scanin        = i_a3_c_ff_a_scanout      ;
assign i_a32_x_ff_a_scanin       = i_a3_c_ff_b_scanout      ;
assign i_a32_x_ff_b_scanin       = i_a32_x_ff_a_scanout     ;
assign i_a2_be_ff_a_scanin       = i_a32_x_ff_b_scanout     ;
assign i_a2_be_ff_b_scanin       = i_a2_be_ff_a_scanout     ;
assign i_a2_rs2_ff_scanin        = i_a2_be_ff_b_scanout     ;
assign i_a2_s_ff_a_scanin        = i_a2_rs2_ff_scanout      ;
assign i_a2_s_ff_b_scanin        = i_a2_s_ff_a_scanout      ;
assign i_a2_c_ff_a_scanin        = i_a2_s_ff_b_scanout      ;
assign i_a2_c_ff_b_scanin        = i_a2_c_ff_a_scanout      ;
assign i_a1_be_ff_scanin         = i_a2_c_ff_b_scanout      ;
assign i_a1_rs2_ff_scanin        = i_a1_be_ff_scanout       ;
assign i_a1_s_ff_a_scanin        = i_a1_rs2_ff_scanout      ;
assign i_a1_s_ff_b_scanin        = i_a1_s_ff_a_scanout      ;
assign i_a1_c_ff_a_scanin        = i_a1_s_ff_b_scanout      ;
assign i_a1_c_ff_b_scanin        = i_a1_c_ff_a_scanout      ;
assign i_a10_x_ff_a_scanin       = i_a1_c_ff_b_scanout      ;
assign i_a10_x_ff_b_scanin       = i_a10_x_ff_a_scanout     ;
assign i_a0_be_ff_scanin         = i_a10_x_ff_b_scanout     ;
assign i_a0_rs2_ff_scanin        = i_a0_be_ff_scanout       ;
assign i_a0_s_ff_a_scanin        = i_a0_rs2_ff_scanout      ;
assign i_a0_s_ff_b_scanin        = i_a0_s_ff_a_scanout      ;
assign i_a0_c_ff_a_scanin        = i_a0_s_ff_b_scanout      ;
assign i_a0_c_ff_b_scanin        = i_a0_c_ff_a_scanout      ;
assign i_a4_s_lo_ff_scanin       = i_a0_c_ff_b_scanout      ;
assign i_a4_s_hi_ff_scanin       = i_a4_s_lo_ff_scanout     ;
assign i_a4_c_lo_ff_scanin       = i_a4_s_hi_ff_scanout     ;
assign i_a4_c_hi_ff_scanin       = i_a4_c_lo_ff_scanout     ;
assign i_accum_ff0_scanin        = i_a4_c_hi_ff_scanout     ;
assign i_accum_ff1_scanin        = i_accum_ff0_scanout      ;
assign i_accum_sel_b1_ff_scanin  = i_accum_ff1_scanout      ;
assign i_fx5_ff_scanin           = i_accum_sel_b1_ff_scanout;
assign i_ma_result_ff_scanin     = i_fx5_ff_scanout         ;
assign scan_out                  = i_ma_result_ff_scanout   ;
// fixscan end:
endmodule  // fgu_fpy_dp


//
//   buff macro
//
//


module fgu_fpy_dp_buff_macro__dbuff_32x__rep_1__stack_88c__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__minbuff_1__stack_88c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpy_dp_buff_macro__stack_88c__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpy_dp_inv_macro__stack_88c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpy_dp_buff_macro__stack_88c__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpy_dp_buff_macro__dbuff_48x__stack_88c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_mux_macro__mux_pgpe__ports_6__stack_88c__width_69 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;

  input [68:0] din0;
  input [68:0] din1;
  input [68:0] din2;
  input [68:0] din3;
  input [68:0] din4;
  input [68:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input muxtst;
  input test;
  output [68:0] dout;


cl_dp1_penc6_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
  .test(test)
);

mux6 #(69)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[68:0]),
  .in1(din1[68:0]),
  .in2(din2[68:0]),
  .in3(din3[68:0]),
  .in4(din4[68:0]),
  .in5(din5[68:0]),
.dout(dout[68:0]),
  .muxtst(muxtst)
);


endmodule


//
//      Booth Encoder with XOR multiply control
//
//


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_booth_encode_macro (
  din, 
  xr_mode, 
  dout, 
  pout, 
  hout);
  input  [2:0]	din;
  input		xr_mode;
  output [4:0]	dout;
  output		pout;
  output		hout;


  cl_dp1_boothenc_4x m0_0 (
  .din(din),
  .xr_mode(xr_mode),
  .dout(dout),
  .pout(pout),
  .hout(hout)
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_63 (
  din0, 
  din1, 
  dout);
  input [62:0] din0;
  input [62:0] din1;
  output [62:0] dout;


xor2 #(63)  d0_0 (
.in0(din0[62:0]),
.in1(din1[62:0]),
.out(dout[62:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_65 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpy_dp_buff_macro__stack_88c__width_65 (
  din, 
  dout);
  input [64:0] din;
  output [64:0] dout;


buff #(65)  d0_0 (
.in(din[64:0]),
.out(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_63 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [61:0] so;

  input [62:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [62:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(63)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[62:0]),
.si({scan_in,so[61:0]}),
.so({so[61:0],scan_out}),
.q(dout[62:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpy_dp_buff_macro__stack_88c__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


buff #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aope__ports_5__stack_88c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpy_dp_buff_macro__stack_88c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   invert macro
//
//


module fgu_fpy_dp_inv_macro__stack_88c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


inv #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_mux_macro__mux_aonpe__ports_5__stack_88c__width_65 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [64:0] din0;
  input sel0;
  input [64:0] din1;
  input sel1;
  input [64:0] din2;
  input sel2;
  input [64:0] din3;
  input sel3;
  input [64:0] din4;
  input sel4;
  output [64:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(65)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
  .in3(din3[64:0]),
  .in4(din4[64:0]),
.dout(dout[64:0])
);


endmodule


//
//      3:2 Carry Save Adder
//
//


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa32_macro__stack_88c__width_69 (
  i0, 
  i1, 
  i2, 
  carry, 
  sum);
  input  [68:0] i0;
  input  [68:0] i1;
  input  [68:0] i2;
  output [68:0] carry;
  output [68:0] sum;


csa32 #(69)  d0_0 (
.in0(i0[68:0]),
.in1(i1[68:0]),
.in2(i2[68:0]),
.carry(carry[68:0]),
.sum(sum[68:0])
);


endmodule


//
//      3:2 Carry Save Adder
//
//


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa32_macro__stack_88c__width_73 (
  i0, 
  i1, 
  i2, 
  carry, 
  sum);
  input  [72:0] i0;
  input  [72:0] i1;
  input  [72:0] i2;
  output [72:0] carry;
  output [72:0] sum;


csa32 #(73)  d0_0 (
.in0(i0[72:0]),
.in1(i1[72:0]),
.in2(i2[72:0]),
.carry(carry[72:0]),
.sum(sum[72:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa42_macro__stack_88c__width_81 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [80:0]    i0;
  input  [80:0]    i1;
  input  [80:0]    i2;
  input  [80:0]    i3;
  input              cin;
  output             cout;
  output [80:0]    carry;
  output [80:0]    sum;


csa42 #(81)  d0_0 (
.cin(cin),
.in0(i0[80:0]),
.in1(i1[80:0]),
.in2(i2[80:0]),
.in3(i3[80:0]),
.cout(cout),
.carry(carry[80:0]),
.sum(sum[80:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_39 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [37:0] so;

  input [38:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [38:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(39)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[38:0]),
.si({scan_in,so[37:0]}),
.so({so[37:0],scan_out}),
.q(dout[38:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_44 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [42:0] so;

  input [43:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [43:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(44)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[43:0]),
.si({scan_in,so[42:0]}),
.so({so[42:0],scan_out}),
.q(dout[43:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_37 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [35:0] so;

  input [36:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [36:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_31 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [29:0] so;

  input [30:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [30:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(31)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[30:0]),
.si({scan_in,so[29:0]}),
.so({so[29:0],scan_out}),
.q(dout[30:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_41 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [39:0] so;

  input [40:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [40:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(41)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[40:0]),
.si({scan_in,so[39:0]}),
.so({so[39:0],scan_out}),
.q(dout[40:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aope__ports_4__stack_88c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input sel0;
  input sel1;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc4_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_mux_macro__mux_aope__ports_2__stack_88c__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


//
//      3:2 Carry Save Adder
//
//


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa32_macro__stack_88c__width_68 (
  i0, 
  i1, 
  i2, 
  carry, 
  sum);
  input  [67:0] i0;
  input  [67:0] i1;
  input  [67:0] i2;
  output [67:0] carry;
  output [67:0] sum;


csa32 #(68)  d0_0 (
.in0(i0[67:0]),
.in1(i1[67:0]),
.in2(i2[67:0]),
.carry(carry[67:0]),
.sum(sum[67:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa42_macro__stack_88c__width_74 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [73:0]    i0;
  input  [73:0]    i1;
  input  [73:0]    i2;
  input  [73:0]    i3;
  input              cin;
  output             cout;
  output [73:0]    carry;
  output [73:0]    sum;


csa42 #(74)  d0_0 (
.cin(cin),
.in0(i0[73:0]),
.in1(i1[73:0]),
.in2(i2[73:0]),
.in3(i3[73:0]),
.cout(cout),
.carry(carry[73:0]),
.sum(sum[73:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_40 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [38:0] so;

  input [39:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [39:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(40)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[39:0]),
.si({scan_in,so[38:0]}),
.so({so[38:0],scan_out}),
.q(dout[39:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_36 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [34:0] so;

  input [35:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [35:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(36)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[35:0]),
.si({scan_in,so[34:0]}),
.so({so[34:0],scan_out}),
.q(dout[35:0])
);


endmodule


//
//      3:2 Carry Save Adder
//
//


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa32_macro__stack_88c__width_25 (
  i0, 
  i1, 
  i2, 
  carry, 
  sum);
  input  [24:0] i0;
  input  [24:0] i1;
  input  [24:0] i2;
  output [24:0] carry;
  output [24:0] sum;


csa32 #(25)  d0_0 (
.in0(i0[24:0]),
.in1(i1[24:0]),
.in2(i2[24:0]),
.carry(carry[24:0]),
.sum(sum[24:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa42_macro__stack_88c__width_3 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [2:0]    i0;
  input  [2:0]    i1;
  input  [2:0]    i2;
  input  [2:0]    i3;
  input              cin;
  output             cout;
  output [2:0]    carry;
  output [2:0]    sum;


csa42 #(3)  d0_0 (
.cin(cin),
.in0(i0[2:0]),
.in1(i1[2:0]),
.in2(i2[2:0]),
.in3(i3[2:0]),
.cout(cout),
.carry(carry[2:0]),
.sum(sum[2:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa42_macro__stack_96c__width_96 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [95:0]    i0;
  input  [95:0]    i1;
  input  [95:0]    i2;
  input  [95:0]    i3;
  input              cin;
  output             cout;
  output [95:0]    carry;
  output [95:0]    sum;


csa42 #(96)  d0_0 (
.cin(cin),
.in0(i0[95:0]),
.in1(i1[95:0]),
.in2(i2[95:0]),
.in3(i3[95:0]),
.cout(cout),
.carry(carry[95:0]),
.sum(sum[95:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa42_macro__stack_96c__width_92 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [91:0]    i0;
  input  [91:0]    i1;
  input  [91:0]    i2;
  input  [91:0]    i3;
  input              cin;
  output             cout;
  output [91:0]    carry;
  output [91:0]    sum;


csa42 #(92)  d0_0 (
.cin(cin),
.in0(i0[91:0]),
.in1(i1[91:0]),
.in2(i2[91:0]),
.in3(i3[91:0]),
.cout(cout),
.carry(carry[91:0]),
.sum(sum[91:0])
);


endmodule


//
//           4:2 Carry Save Adder
//
//
//     i0 i1 i2 i3 | co | carry  sum
//     ------------|----|-----------
//      0  0  0  0 |  0 |   0    cin
//      0  0  0  1 |  0 |  cin  ~cin
//      0  0  1  0 |  0 |  cin  ~cin
//      0  0  1  1 |  0 |   1    cin
//   
//      0  1  0  0 |  0 |  cin  ~cin
//      0  1  0  1 |  0 |   1    cin
//      0  1  1  0 |  1 |   0    cin
//      0  1  1  1 |  1 |  cin  ~cin
//   
//      1  0  0  0 |  0 |  cin  ~cin
//      1  0  0  1 |  0 |   1    cin
//      1  0  1  0 |  1 |   0    cin
//      1  0  1  1 |  1 |  cin  ~cin
//   
//      1  1  0  0 |  1 |   0    cin
//      1  1  0  1 |  1 |  cin  ~cin
//      1  1  1  0 |  1 |  cin  ~cin
//      1  1  1  1 |  1 |   1    cin


// This circuit looks like a compression of 5 terms down
// to 3 term on an individual bit basis.  However, the fast
// output "co" from bit position "n" is actually the late input
// "cin" on bit position "n+1".  Once a wrapper is written
// around multiple bits, this circuit will give the 
// appearance of compressing 4 inputs down to 2 outputs.


// any PARAMS parms go into naming of macro


module fgu_fpy_dp_csa42_macro__stack_88c__width_32 (
  i0, 
  i1, 
  i2, 
  i3, 
  cin, 
  cout, 
  carry, 
  sum);
  input  [31:0]    i0;
  input  [31:0]    i1;
  input  [31:0]    i2;
  input  [31:0]    i3;
  input              cin;
  output             cout;
  output [31:0]    carry;
  output [31:0]    sum;


csa42 #(32)  d0_0 (
.cin(cin),
.in0(i0[31:0]),
.in1(i1[31:0]),
.in2(i2[31:0]),
.in3(i3[31:0]),
.cout(cout),
.carry(carry[31:0]),
.sum(sum[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aope__ports_5__stack_88c__width_72 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [71:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [70:0] so;

  input [71:0] din0;
  input [71:0] din1;
  input [71:0] din2;
  input [71:0] din3;
  input [71:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [71:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(72)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[71:0]),
  .in1(din1[71:0]),
  .in2(din2[71:0]),
  .in3(din3[71:0]),
  .in4(din4[71:0]),
.dout(muxout[71:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(72)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[71:0]),
.si({scan_in,so[70:0]}),
.so({so[70:0],scan_out}),
.q(dout[71:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aonpe__ports_3__stack_88c__width_62 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire [61:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [60:0] so;

  input [61:0] din0;
  input sel0;
  input [61:0] din1;
  input sel1;
  input [61:0] din2;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [61:0] dout;


  output scan_out;


cl_dp1_muxbuff3_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(62)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[61:0]),
  .in1(din1[61:0]),
  .in2(din2[61:0]),
.dout(muxout[61:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(62)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[61:0]),
.si({scan_in,so[60:0]}),
.so({so[60:0],scan_out}),
.q(dout[61:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aonpe__ports_3__stack_88c__width_69 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire [68:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [67:0] so;

  input [68:0] din0;
  input sel0;
  input [68:0] din1;
  input sel1;
  input [68:0] din2;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [68:0] dout;


  output scan_out;


cl_dp1_muxbuff3_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(69)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[68:0]),
  .in1(din1[68:0]),
  .in2(din2[68:0]),
.dout(muxout[68:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(69)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[68:0]),
.si({scan_in,so[67:0]}),
.so({so[67:0],scan_out}),
.q(dout[68:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module fgu_fpy_dp_xor_macro__ports_2__stack_88c__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;


xor2 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aope__ports_6__stack_88c__width_72 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire [71:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [70:0] so;

  input [71:0] din0;
  input [71:0] din1;
  input [71:0] din2;
  input [71:0] din3;
  input [71:0] din4;
  input [71:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [71:0] dout;


  output scan_out;


cl_dp1_penc6_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5)
);

mux6s #(72)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[71:0]),
  .in1(din1[71:0]),
  .in2(din2[71:0]),
  .in3(din3[71:0]),
  .in4(din4[71:0]),
  .in5(din5[71:0]),
.dout(muxout[71:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(72)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[71:0]),
.si({scan_in,so[70:0]}),
.so({so[70:0],scan_out}),
.q(dout[71:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aope__ports_6__stack_88c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc6_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5)
);

mux6s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__stack_88c__width_4 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [2:0] so;

  input [3:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [3:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module fgu_fpy_dp_buff_macro__stack_88c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aope__ports_7__stack_88c__width_68 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire [67:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [66:0] so;

  input [67:0] din0;
  input [67:0] din1;
  input [67:0] din2;
  input [67:0] din3;
  input [67:0] din4;
  input [67:0] din5;
  input [67:0] din6;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [67:0] dout;


  output scan_out;


cl_dp1_penc7_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6)
);

mux7s #(68)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .in0(din0[67:0]),
  .in1(din1[67:0]),
  .in2(din2[67:0]),
  .in3(din3[67:0]),
  .in4(din4[67:0]),
  .in5(din5[67:0]),
  .in6(din6[67:0]),
.dout(muxout[67:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(68)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[67:0]),
.si({scan_in,so[66:0]}),
.so({so[66:0],scan_out}),
.q(dout[67:0])
);


endmodule


// any PARAMS parms go into naming of macro

module fgu_fpy_dp_msff_macro__mux_aope__ports_2__stack_88c__width_64 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fgu_rep_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module fgu_rep_dp (
  fad_rs1_fmt_fx1, 
  fad_rs2_fmt_fx1, 
  fad_rs1_fmt_fx1_rep0, 
  fad_rs1_fmt_fx1_rep01, 
  fad_rs2_fmt_fx1_rep0, 
  fad_rs2_fmt_fx1_rep01, 
  fad_rs2_fmt_fx1_rep1, 
  fdd_result, 
  fdd_result_rep0, 
  fpf_hi_bof_fx1, 
  fpf_lo_bof_fx1, 
  fpf_hi_bof_fx1_rep0, 
  fpf_lo_bof_fx1_rep0, 
  fpe_rs2_fmt_fx1, 
  fpe_rs2_fmt_fx1_b0_rep0, 
  mul_clken, 
  div_clken, 
  mul_clken_rep0, 
  mul_clken_rep01, 
  div_clken_rep0, 
  fac_div_valid_fx1, 
  fac_divq_valid_fx1, 
  fac_div_control_fx1, 
  fac_div_valid_fx1_rep0, 
  fac_divq_valid_fx1_rep0, 
  fac_div_control_fx1_rep0, 
  fdc_finish_int_early, 
  fdc_finish_fltd_early, 
  fdc_finish_flts_early, 
  fdc_finish_int_early_rep0, 
  fdc_finish_fltd_early_rep0, 
  fdc_finish_flts_early_rep0);


// ----------------------------------------------------------------------------
// 
// ----------------------------------------------------------------------------

input   [63:0] fad_rs1_fmt_fx1;
input   [63:0] fad_rs2_fmt_fx1;
output  [63:0] fad_rs1_fmt_fx1_rep0;
output  [63:0] fad_rs1_fmt_fx1_rep01;
output  [63:0] fad_rs2_fmt_fx1_rep0;
output  [63:0] fad_rs2_fmt_fx1_rep01;
output  [63:0] fad_rs2_fmt_fx1_rep1;

input  [62:11] fdd_result;
output [62:11] fdd_result_rep0;

input          fpf_hi_bof_fx1;
input          fpf_lo_bof_fx1;
output         fpf_hi_bof_fx1_rep0;
output         fpf_lo_bof_fx1_rep0;

input    [0:0] fpe_rs2_fmt_fx1;
output         fpe_rs2_fmt_fx1_b0_rep0;

input          mul_clken;
input          div_clken;
output         mul_clken_rep0;
output         mul_clken_rep01;
output         div_clken_rep0;

input          fac_div_valid_fx1;
input          fac_divq_valid_fx1;
input    [4:0] fac_div_control_fx1;
output         fac_div_valid_fx1_rep0;
output         fac_divq_valid_fx1_rep0;
output   [4:0] fac_div_control_fx1_rep0;

input          fdc_finish_int_early;
input 	       fdc_finish_fltd_early;
input          fdc_finish_flts_early;
output         fdc_finish_int_early_rep0;
output	       fdc_finish_fltd_early_rep0;
output         fdc_finish_flts_early_rep0;


// ----------------------------------------------------------------------------
// 
// ----------------------------------------------------------------------------


fgu_rep_dp_buff_macro__rep_1__width_64 rs1_fmt_rep0  (
  .din (fad_rs1_fmt_fx1[63:0]     ),
  .dout(fad_rs1_fmt_fx1_rep0[63:0])
  );

fgu_rep_dp_buff_macro__rep_1__width_64 rs1_fmt_rep01  (
  .din (fad_rs1_fmt_fx1[63:0]     ),
  .dout(fad_rs1_fmt_fx1_rep01[63:0])
  );

fgu_rep_dp_buff_macro__rep_1__width_64 rs2_fmt_rep0  (
  .din (fad_rs2_fmt_fx1[63:0]     ),
  .dout(fad_rs2_fmt_fx1_rep0[63:0])
  );

fgu_rep_dp_buff_macro__rep_1__width_64 rs2_fmt_rep01  (
  .din (fad_rs2_fmt_fx1[63:0]     ),
  .dout(fad_rs2_fmt_fx1_rep01[63:0])
  );

fgu_rep_dp_buff_macro__rep_1__stack_88c__width_64 rs2_fmt_rep1  (  // placed in fpy, so stack width set to match
  .din (fad_rs2_fmt_fx1_rep0[63:0]),
  .dout(fad_rs2_fmt_fx1_rep1[63:0])
  );

fgu_rep_dp_buff_macro__rep_1__width_52 fdd_res_rep0  (
  .din (fdd_result[62:11]     ),
  .dout(fdd_result_rep0[62:11])
  );

fgu_rep_dp_buff_macro__rep_1__width_2 bof_rep0  (
  .din ({fpf_hi_bof_fx1,      fpf_lo_bof_fx1     }),
  .dout({fpf_hi_bof_fx1_rep0, fpf_lo_bof_fx1_rep0})
  );

fgu_rep_dp_buff_macro__rep_1__width_1 fpe_fmt_rep0  (
  .din (fpe_rs2_fmt_fx1[0]     ),
  .dout(fpe_rs2_fmt_fx1_b0_rep0)
  );

fgu_rep_dp_buff_macro__rep_1__width_2 mul_clkenable_rep0  (
  .din ({mul_clken,       mul_clken     }),
  .dout({mul_clken_rep01, mul_clken_rep0})
  );

fgu_rep_dp_buff_macro__rep_1__width_8 div_control_rep0  (
  .din ({div_clken,
         fac_div_valid_fx1,
         fac_divq_valid_fx1,
         fac_div_control_fx1[4:0]}),
  .dout({div_clken_rep0,
         fac_div_valid_fx1_rep0,
         fac_divq_valid_fx1_rep0,
         fac_div_control_fx1_rep0[4:0]})
  );

fgu_rep_dp_buff_macro__rep_1__width_3 finish_early_rep0  (
  .din ({fdc_finish_int_early,
         fdc_finish_fltd_early,
         fdc_finish_flts_early}),
  .dout({fdc_finish_int_early_rep0,
         fdc_finish_fltd_early_rep0,
         fdc_finish_flts_early_rep0})
  );


endmodule  // fgu_rep_dp


//
//   buff macro
//
//


module fgu_rep_dp_buff_macro__rep_1__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_rep_dp_buff_macro__rep_1__stack_88c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module fgu_rep_dp_buff_macro__rep_1__width_52 (
  din, 
  dout);
  input [51:0] din;
  output [51:0] dout;


buff #(52)  d0_0 (
.in(din[51:0]),
.out(dout[51:0])
);


endmodule


//
//   buff macro
//
//


module fgu_rep_dp_buff_macro__rep_1__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module fgu_rep_dp_buff_macro__rep_1__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module fgu_rep_dp_buff_macro__rep_1__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module fgu_rep_dp_buff_macro__rep_1__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


buff #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: gkt.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  gkt (
  tcu_scan_en, 
  tcu_se_scancollar_out, 
  lbist_run, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  core_isolate, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  slow_cmp_sync_en, 
  const_cpuid, 
  lsu_gkt_pmen, 
  ifu_l15_valid, 
  mmu_l15_valid, 
  lsu_l15_valid, 
  spu_l15_valid, 
  lsu_l15_lock, 
  ifu_l15_addr, 
  mmu_l15_addr, 
  lsu_l15_addr, 
  spu_l15_addr, 
  ifu_l15_cpkt, 
  mmu_l15_cpkt, 
  lsu_l15_cpkt, 
  spu_l15_cpkt, 
  lsu_l15_data, 
  spu_l15_data, 
  ncu_spc_pm, 
  ncu_spc_ba01, 
  ncu_spc_ba23, 
  ncu_spc_ba45, 
  ncu_spc_ba67, 
  ncu_spc_l2_idx_hash_en, 
  cpx_spc_data_cx, 
  pcx_spc_grant_px, 
  l15_spc_cpkt, 
  l15_spc_data1, 
  cpx_spc_data_cx_rep0, 
  l15_mmu_valid, 
  l15_spu_valid, 
  l15_ifu_grant, 
  l15_mmu_grant, 
  l15_lsu_grant, 
  l15_spu_grant, 
  gkt_ifu_legal, 
  gkt_ifu_flip_parity, 
  l15_pmu_xbar_optype, 
  spc_pcx_req_pq, 
  spc_pcx_atm_pq, 
  spc_pcx_data_pa);
wire ipc_v0_ifu_new;
wire ipc_v0_ifu_shft;
wire ipc_v0_ifu_hold;
wire ipc_v1_ifu_new;
wire ipc_v1_ifu_hold;
wire ipc_v0_mmu_new;
wire ipc_v0_mmu_shft;
wire ipc_v0_mmu_hold;
wire ipc_v1_mmu_new;
wire ipc_v1_mmu_hold;
wire ipc_v0_lsu_new;
wire ipc_v0_lsu_shft;
wire ipc_v0_lsu_hold;
wire ipc_v1_lsu_new;
wire ipc_v1_lsu_hold;
wire ipc_v0_spu_new;
wire ipc_v0_spu_shft;
wire ipc_v0_spu_hold;
wire ipc_v1_spu_new;
wire ipc_v1_spu_hold;
wire [3:0] ipc_dropreg_wen;
wire ipc_pq_clken;
wire ipc_scanin;
wire ipc_scanout;
wire [8:0] pcx_spc_grant_px_buf;
wire [8:0] ipd_optype;
wire ipd_scanin;
wire ipd_scanout;
wire ncu_pm_ff;
wire ncu_ba01_ff;
wire ncu_ba23_ff;
wire ncu_ba45_ff;
wire ncu_ba67_ff;
wire ipc_sel_ndrop_ifu_l1;
wire ipc_sel_ndrop_mmu_l1;
wire ipc_sel_ndrop_lsu_l1;
wire ipc_sel_ndrop_spu_l1;
wire ipc_sel_drop_ifu_l1;
wire ipc_sel_drop_mmu_l1;
wire ipc_sel_drop_lsu_l1;
wire ipc_sel_drop_spu_l1;
wire [8:0] ipc_op_req_li;
wire [8:0] ipc_atm_req_li;


// globals
input		tcu_scan_en;
input		tcu_se_scancollar_out;
input		lbist_run;
input       l2clk;
input       scan_in;
input       tcu_pce_ov;             // scan signals
input       core_isolate;

input       spc_aclk;
input       spc_bclk;
output      scan_out;
input       slow_cmp_sync_en;


input [2:0] const_cpuid;


input       lsu_gkt_pmen;

// inputs from core
input       ifu_l15_valid;
input       mmu_l15_valid;
input       lsu_l15_valid;
input       spu_l15_valid;


input       lsu_l15_lock;


input [39:0] ifu_l15_addr;
input [39:4] mmu_l15_addr;
input [39:0] lsu_l15_addr;
input [38:3] spu_l15_addr;


input [7:0]  ifu_l15_cpkt;
input [4:0]  mmu_l15_cpkt;
input [25:0] lsu_l15_cpkt;
input [12:0] spu_l15_cpkt;

input [63:0] lsu_l15_data;
input [63:0] spu_l15_data;

// inputs from ncu
input        ncu_spc_pm;
input        ncu_spc_ba01;
input        ncu_spc_ba23;
input        ncu_spc_ba45;
input        ncu_spc_ba67;
input        ncu_spc_l2_idx_hash_en;

// inputs from CPX crossbar
input [145:0] cpx_spc_data_cx;

// input from PCX crossbar
input [8:0]   pcx_spc_grant_px;


// output to SPARC core
output [17:0] l15_spc_cpkt;

output [127:0] l15_spc_data1;
output [145:0]  cpx_spc_data_cx_rep0;


output        l15_mmu_valid;
output        l15_spu_valid;

output        l15_ifu_grant;
output        l15_mmu_grant;
output        l15_lsu_grant;
output        l15_spu_grant;

// output legal opcode decode and flip parity

output [3:0]  gkt_ifu_legal;
output [3:0]  gkt_ifu_flip_parity;


// output to pmu
output [6:0]  l15_pmu_xbar_optype;

// output to PCX crossbar
output [8:0]  spc_pcx_req_pq;
output [8:0]  spc_pcx_atm_pq;
output [129:0] spc_pcx_data_pa;


// assertions
// lock has to be asserted only on CAS1 packet
/* 0in assert_together -leader (lsu_l15_valid & (lsu_l15_cpkt[24:20] == 5'b0010)) -follower lsu_l15_lock
 -message "l1g: CAS1 packet does not have lock asserted" */
/* 0in assert_together -leader (~lsu_l15_valid  | (lsu_l15_cpkt[24:20] != 5'b0010)) -follower !lsu_l15_lock
 -message "l1g: Non CAS1 packet has lock asserted" */
/* 0in assert_follower -leader lsu_l15_lock -follower !lsu_l15_lock -max 1 
 -message "l1g: lsu_l15_lock asserted for more than one cycle"*/

////////////////////////////////////////////////////////////////////////////////
/* 
 gkt_ipc_ctl AUTO_TEMPLATE
 (
 .pcx_grant (pcx_spc_grant_px_buf[8:0]),
 .ifu_l15_addr39_37 (ifu_l15_addr[39:37]),
 .mmu_l15_addr39_37 (mmu_l15_addr[39:37]),
 .lsu_l15_addr39_37 (lsu_l15_addr[39:37]),
 .spu_l15_addr39_37 (spu_l15_addr[39:37]),
 .ifu_l15_addr8_6 (ifu_l15_addr[8:6]),
 .mmu_l15_addr8_6 (mmu_l15_addr[8:6]),
 .lsu_l15_addr8_6 (lsu_l15_addr[8:6]),
 .spu_l15_addr8_6 (spu_l15_addr[8:6]),
 )
 */

gkt_ipc_ctl ipc (/*AUTOINST*/
                 // Outputs
                 .ipc_v0_ifu_new        (ipc_v0_ifu_new),
                 .ipc_v0_ifu_shft       (ipc_v0_ifu_shft),
                 .ipc_v0_ifu_hold       (ipc_v0_ifu_hold),
                 .ipc_v1_ifu_new        (ipc_v1_ifu_new),
                 .ipc_v1_ifu_hold       (ipc_v1_ifu_hold),
                 .ipc_v0_mmu_new        (ipc_v0_mmu_new),
                 .ipc_v0_mmu_shft       (ipc_v0_mmu_shft),
                 .ipc_v0_mmu_hold       (ipc_v0_mmu_hold),
                 .ipc_v1_mmu_new        (ipc_v1_mmu_new),
                 .ipc_v1_mmu_hold       (ipc_v1_mmu_hold),
                 .ipc_v0_lsu_new        (ipc_v0_lsu_new),
                 .ipc_v0_lsu_shft       (ipc_v0_lsu_shft),
                 .ipc_v0_lsu_hold       (ipc_v0_lsu_hold),
                 .ipc_v1_lsu_new        (ipc_v1_lsu_new),
                 .ipc_v1_lsu_hold       (ipc_v1_lsu_hold),
                 .ipc_v0_spu_new        (ipc_v0_spu_new),
                 .ipc_v0_spu_shft       (ipc_v0_spu_shft),
                 .ipc_v0_spu_hold       (ipc_v0_spu_hold),
                 .ipc_v1_spu_new        (ipc_v1_spu_new),
                 .ipc_v1_spu_hold       (ipc_v1_spu_hold),
                 .l15_ifu_grant         (l15_ifu_grant),
                 .l15_mmu_grant         (l15_mmu_grant),
                 .l15_lsu_grant         (l15_lsu_grant),
                 .l15_spu_grant         (l15_spu_grant),
                 .ipc_dropreg_wen       (ipc_dropreg_wen[3:0]),
                 .ipc_pq_clken          (ipc_pq_clken),
                 // Inputs
                 .scan_in(ipc_scanin),
                 .scan_out(ipc_scanout),
                 .l2clk                 (l2clk),
                 .ifu_l15_valid         (ifu_l15_valid),
                 .mmu_l15_valid         (mmu_l15_valid),
                 .lsu_l15_valid         (lsu_l15_valid),
                 .spu_l15_valid         (spu_l15_valid),
                 .ifu_l15_addr39_37     (ifu_l15_addr[39:37]),   // Templated
                 .ifu_l15_addr8_6       (ifu_l15_addr[8:6]),     // Templated
                 .mmu_l15_addr39_37     (mmu_l15_addr[39:37]),   // Templated
                 .mmu_l15_addr8_6       (mmu_l15_addr[8:6]),     // Templated
                 .lsu_l15_addr39_37     (lsu_l15_addr[39:37]),   // Templated
                 .lsu_l15_addr8_6       (lsu_l15_addr[8:6]),     // Templated
                 .spu_l15_addr39_37     ({1'b0,spu_l15_addr[38:37]}),   // Templated
                 .spu_l15_addr8_6       (spu_l15_addr[8:6]),     // Templated
                 .lsu_l15_lock          (lsu_l15_lock),
                 .pcx_grant             (pcx_spc_grant_px_buf[8:0]), // Templated
                 .ipd_optype            (ipd_optype[8:0]),
  .tcu_scan_en(tcu_scan_en),
  .lbist_run(lbist_run),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .lsu_gkt_pmen(lsu_gkt_pmen),
  .ncu_pm_ff(ncu_pm_ff),
  .ncu_ba01_ff(ncu_ba01_ff),
  .ncu_ba23_ff(ncu_ba23_ff),
  .ncu_ba45_ff(ncu_ba45_ff),
  .ncu_ba67_ff(ncu_ba67_ff),
  .ipc_sel_ndrop_ifu_l1(ipc_sel_ndrop_ifu_l1),
  .ipc_sel_ndrop_mmu_l1(ipc_sel_ndrop_mmu_l1),
  .ipc_sel_ndrop_lsu_l1(ipc_sel_ndrop_lsu_l1),
  .ipc_sel_ndrop_spu_l1(ipc_sel_ndrop_spu_l1),
  .ipc_sel_drop_ifu_l1(ipc_sel_drop_ifu_l1),
  .ipc_sel_drop_mmu_l1(ipc_sel_drop_mmu_l1),
  .ipc_sel_drop_lsu_l1(ipc_sel_drop_lsu_l1),
  .ipc_sel_drop_spu_l1(ipc_sel_drop_spu_l1),
  .ipc_op_req_li(ipc_op_req_li[8:0]),
  .ipc_atm_req_li(ipc_atm_req_li[8:0]),
  .l15_pmu_xbar_optype(l15_pmu_xbar_optype[6:0]));

/* 
 gkt_ipd_dp AUTO_TEMPLATE 
 (
 .l15_spc_cpkt (l15_spu_cpkt[17:0]),
 .l15_spc_valid (l15_spu_valid),
 );
 */

gkt_ipd_dp ipd (/*AUTOINST*/
                // Outputs
                .spc_pcx_req_pq        (spc_pcx_req_pq[8:0]),
                .spc_pcx_atm_pq        (spc_pcx_atm_pq[8:0]),
                .spc_pcx_data_pa        (spc_pcx_data_pa[129:0]),
                .l15_spc_data1          (l15_spc_data1[127:0]),
                .l15_spc_cpkt           (l15_spc_cpkt[17:0]),
                .l15_mmu_valid          (l15_mmu_valid),
                .l15_spu_valid          (l15_spu_valid),
                .ipd_optype             (ipd_optype[8:0]),
                // Inputs
                .scan_in(ipd_scanin),
                .scan_out(ipd_scanout),
                .l2clk                  (l2clk),
                .ipc_v0_ifu_new         (ipc_v0_ifu_new),
                .ipc_v0_ifu_shft        (ipc_v0_ifu_shft),
                .ipc_v0_ifu_hold        (ipc_v0_ifu_hold),
                .ipc_v1_ifu_new         (ipc_v1_ifu_new),
                .ipc_v1_ifu_hold        (ipc_v1_ifu_hold),
                .ipc_v0_mmu_new         (ipc_v0_mmu_new),
                .ipc_v0_mmu_shft        (ipc_v0_mmu_shft),
                .ipc_v0_mmu_hold        (ipc_v0_mmu_hold),
                .ipc_v1_mmu_new         (ipc_v1_mmu_new),
                .ipc_v1_mmu_hold        (ipc_v1_mmu_hold),
                .ipc_v0_lsu_new         (ipc_v0_lsu_new),
                .ipc_v0_lsu_shft        (ipc_v0_lsu_shft),
                .ipc_v0_lsu_hold        (ipc_v0_lsu_hold),
                .ipc_v1_lsu_new         (ipc_v1_lsu_new),
                .ipc_v1_lsu_hold        (ipc_v1_lsu_hold),
                .ipc_v0_spu_new         (ipc_v0_spu_new),
                .ipc_v0_spu_shft        (ipc_v0_spu_shft),
                .ipc_v0_spu_hold        (ipc_v0_spu_hold),
                .ipc_v1_spu_new         (ipc_v1_spu_new),
                .ipc_v1_spu_hold        (ipc_v1_spu_hold),
                .ipc_pq_clken           (ipc_pq_clken),
                .ipc_dropreg_wen        (ipc_dropreg_wen[3:0]),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .tcu_pce_ov(tcu_pce_ov),
  .core_isolate(core_isolate),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .slow_cmp_sync_en(slow_cmp_sync_en),
  .const_cpuid(const_cpuid[2:0]),
  .ncu_spc_pm(ncu_spc_pm),
  .ncu_spc_ba01(ncu_spc_ba01),
  .ncu_spc_ba23(ncu_spc_ba23),
  .ncu_spc_ba45(ncu_spc_ba45),
  .ncu_spc_ba67(ncu_spc_ba67),
  .ncu_pm_ff(ncu_pm_ff),
  .ncu_ba01_ff(ncu_ba01_ff),
  .ncu_ba23_ff(ncu_ba23_ff),
  .ncu_ba45_ff(ncu_ba45_ff),
  .ncu_ba67_ff(ncu_ba67_ff),
  .cpx_spc_data_cx_rep0(cpx_spc_data_cx_rep0[145:0]),
  .pcx_spc_grant_px_buf(pcx_spc_grant_px_buf[8:0]),
  .cpx_spc_data_cx(cpx_spc_data_cx[145:0]),
  .pcx_spc_grant_px(pcx_spc_grant_px[8:0]),
  .ifu_l15_addr(ifu_l15_addr[39:0]),
  .mmu_l15_addr(mmu_l15_addr[39:4]),
  .lsu_l15_addr(lsu_l15_addr[39:0]),
  .spu_l15_addr(spu_l15_addr[38:3]),
  .ifu_l15_valid(ifu_l15_valid),
  .mmu_l15_valid(mmu_l15_valid),
  .spu_l15_valid(spu_l15_valid),
  .ifu_l15_cpkt(ifu_l15_cpkt[7:0]),
  .mmu_l15_cpkt(mmu_l15_cpkt[4:0]),
  .lsu_l15_cpkt(lsu_l15_cpkt[25:0]),
  .spu_l15_cpkt(spu_l15_cpkt[12:0]),
  .lsu_l15_data(lsu_l15_data[63:0]),
  .spu_l15_data(spu_l15_data[63:0]),
  .ipc_sel_ndrop_ifu_l1(ipc_sel_ndrop_ifu_l1),
  .ipc_sel_ndrop_mmu_l1(ipc_sel_ndrop_mmu_l1),
  .ipc_sel_ndrop_lsu_l1(ipc_sel_ndrop_lsu_l1),
  .ipc_sel_ndrop_spu_l1(ipc_sel_ndrop_spu_l1),
  .ipc_sel_drop_ifu_l1(ipc_sel_drop_ifu_l1),
  .ipc_sel_drop_mmu_l1(ipc_sel_drop_mmu_l1),
  .ipc_sel_drop_lsu_l1(ipc_sel_drop_lsu_l1),
  .ipc_sel_drop_spu_l1(ipc_sel_drop_spu_l1),
  .ipc_op_req_li(ipc_op_req_li[8:0]),
  .ipc_atm_req_li(ipc_atm_req_li[8:0]),
  .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en));


gkt_leg_ctl leg0 (
                  .instr (l15_spc_data1[31:0]),
                  .legal (gkt_ifu_legal[0]),
                  .flip_parity (gkt_ifu_flip_parity[0])
                  );

gkt_leg_ctl leg1 (
                  .instr (l15_spc_data1[63:32]),
                  .legal (gkt_ifu_legal[1]),
                  .flip_parity (gkt_ifu_flip_parity[1])
                  );

gkt_leg_ctl leg2 (
                  .instr (l15_spc_data1[95:64]),
                  .legal (gkt_ifu_legal[2]),
                  .flip_parity (gkt_ifu_flip_parity[2])
                  );

gkt_leg_ctl leg3 (
                  .instr (l15_spc_data1[127:96]),
                  .legal (gkt_ifu_legal[3]),
                  .flip_parity (gkt_ifu_flip_parity[3])
                  );


// fixscan start:
assign ipc_scanin                = scan_in                  ;
assign ipd_scanin                = ipc_scanout              ;
assign scan_out                  = ipd_scanout              ;
// fixscan end:
endmodule
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: gkt_ipc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
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// CA 95054 USA or visit www.sun.com if you need additional information or 
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// ========== Copyright Header End ============================================
module  gkt_ipc_ctl (
  tcu_scan_en, 
  l2clk, 
  lbist_run, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  lsu_gkt_pmen, 
  ifu_l15_valid, 
  mmu_l15_valid, 
  lsu_l15_valid, 
  spu_l15_valid, 
  ifu_l15_addr39_37, 
  ifu_l15_addr8_6, 
  mmu_l15_addr39_37, 
  mmu_l15_addr8_6, 
  lsu_l15_addr39_37, 
  lsu_l15_addr8_6, 
  spu_l15_addr39_37, 
  spu_l15_addr8_6, 
  lsu_l15_lock, 
  pcx_grant, 
  ipd_optype, 
  ncu_pm_ff, 
  ncu_ba01_ff, 
  ncu_ba23_ff, 
  ncu_ba45_ff, 
  ncu_ba67_ff, 
  ipc_v0_ifu_new, 
  ipc_v0_ifu_shft, 
  ipc_v0_ifu_hold, 
  ipc_v1_ifu_new, 
  ipc_v1_ifu_hold, 
  ipc_v0_mmu_new, 
  ipc_v0_mmu_shft, 
  ipc_v0_mmu_hold, 
  ipc_v1_mmu_new, 
  ipc_v1_mmu_hold, 
  ipc_v0_lsu_new, 
  ipc_v0_lsu_shft, 
  ipc_v0_lsu_hold, 
  ipc_v1_lsu_new, 
  ipc_v1_lsu_hold, 
  ipc_v0_spu_new, 
  ipc_v0_spu_shft, 
  ipc_v0_spu_hold, 
  ipc_v1_spu_new, 
  ipc_v1_spu_hold, 
  l15_ifu_grant, 
  l15_mmu_grant, 
  l15_lsu_grant, 
  l15_spu_grant, 
  ipc_sel_ndrop_ifu_l1, 
  ipc_sel_ndrop_mmu_l1, 
  ipc_sel_ndrop_lsu_l1, 
  ipc_sel_ndrop_spu_l1, 
  ipc_sel_drop_ifu_l1, 
  ipc_sel_drop_mmu_l1, 
  ipc_sel_drop_lsu_l1, 
  ipc_sel_drop_spu_l1, 
  ipc_dropreg_wen, 
  ipc_pq_clken, 
  ipc_op_req_li, 
  ipc_atm_req_li, 
  l15_pmu_xbar_optype);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire pmen_reg_scanin;
wire pmen_reg_scanout;
wire gkt_pmen;
wire dff_ncu_pb_scanin;
wire dff_ncu_pb_scanout;
wire pm;
wire ba01;
wire ba23;
wire ba45;
wire ba67;
wire sel8_pa8_in;
wire sel8_pa7_in;
wire sel8_1_in;
wire sel7_pa7_in;
wire sel7_pa7b_in;
wire sel7_1_in;
wire dff_pb_sel_scanin;
wire dff_pb_sel_scanout;
wire sel8_pa8;
wire sel8_pa7;
wire sel8_1;
wire sel7_pa7;
wire sel7_pa7b;
wire sel7_1;
wire v0_ifu_in;
wire v0_ifu;
wire ifu_shift;
wire v1_ifu;
wire v1_ifu_in;
wire ifu_eff_addr_8;
wire ifu_eff_addr_7;
wire ifu_l15_io;
wire [8:0] ifu_l15_bank;
wire [8:0] v0_ifu_req_in;
wire [8:0] v1_ifu_req;
wire [8:0] v0_ifu_req;
wire [8:0] v1_ifu_req_in;
wire dff_ifu_req_v0_scanin;
wire dff_ifu_req_v0_scanout;
wire dff_ifu_req_v1_scanin;
wire dff_ifu_req_v1_scanout;
wire dff_ifu_v0_scanin;
wire dff_ifu_v0_scanout;
wire dff_ifu_v1_scanin;
wire dff_ifu_v1_scanout;
wire v0_mmu_in;
wire v0_mmu;
wire mmu_shift;
wire v1_mmu;
wire v1_mmu_in;
wire mmu_eff_addr_8;
wire mmu_eff_addr_7;
wire mmu_l15_io;
wire [8:0] mmu_l15_bank;
wire [8:0] v0_mmu_req_in;
wire [8:0] v1_mmu_req;
wire [8:0] v0_mmu_req;
wire [8:0] v1_mmu_req_in;
wire dff_mmu_req_v0_scanin;
wire dff_mmu_req_v0_scanout;
wire dff_mmu_req_v1_scanin;
wire dff_mmu_req_v1_scanout;
wire dff_mmu_v0_scanin;
wire dff_mmu_v0_scanout;
wire dff_mmu_v1_scanin;
wire dff_mmu_v1_scanout;
wire v0_lsu_in;
wire v0_lsu;
wire lsu_shift;
wire v1_lsu;
wire v1_lsu_in;
wire v0_lsu_lock_in;
wire v1_lsu_lock;
wire v0_lsu_lock;
wire v1_lsu_lock_in;
wire lsu_eff_addr_8;
wire lsu_eff_addr_7;
wire lsu_l15_io;
wire [8:0] lsu_l15_bank;
wire [8:0] v0_lsu_req_in;
wire [8:0] v1_lsu_req;
wire [8:0] v0_lsu_req;
wire [8:0] v1_lsu_req_in;
wire dff_lsu_req_v0_scanin;
wire dff_lsu_req_v0_scanout;
wire dff_lsu_req_v1_scanin;
wire dff_lsu_req_v1_scanout;
wire dff_lsu_v0_scanin;
wire dff_lsu_v0_scanout;
wire dff_lsu_v1_scanin;
wire dff_lsu_v1_scanout;
wire dff_lsu_lock_v0_scanin;
wire dff_lsu_lock_v0_scanout;
wire dff_lsu_lock_v1_scanin;
wire dff_lsu_lock_v1_scanout;
wire v0_spu_in;
wire v0_spu;
wire spu_shift;
wire v1_spu;
wire v1_spu_in;
wire spu_eff_addr_8;
wire spu_eff_addr_7;
wire spu_l15_io;
wire [8:0] spu_l15_bank;
wire [8:0] v0_spu_req_in;
wire [8:0] v1_spu_req;
wire [8:0] v0_spu_req;
wire [8:0] v1_spu_req_in;
wire dff_spu_req_v0_scanin;
wire dff_spu_req_v0_scanout;
wire dff_spu_req_v1_scanin;
wire dff_spu_req_v1_scanout;
wire dff_spu_v0_scanin;
wire dff_spu_v0_scanout;
wire dff_spu_v1_scanin;
wire dff_spu_v1_scanout;
wire f_im_in;
wire f_im;
wire sel_ifu_l1;
wire sel_mmu_l1;
wire force_ifu;
wire force_mmu;
wire f_ls_in;
wire f_ls;
wire sel_lsu_l1;
wire sel_spu_l1;
wire force_lsu;
wire force_spu;
wire f_i_in;
wire f_i;
wire sel_ifu_mmu_l1;
wire sel_lsu_spu_l1;
wire force_ifu_mmu;
wire force_lsu_spu;
wire ifu_v;
wire [3:0] ipc_dropreg_valid;
wire mmu_v;
wire lsu_v;
wire spu_v;
wire ipc_sel_ifu;
wire lock_acc;
wire ipc_sel_mmu;
wire ipc_sel_lsu;
wire ipc_sel_spu;
wire ipc_sel_ifu_mmu;
wire ipc_sel_lsu_spu;
wire lock_acc_in;
wire [3:0] unit_sel_li;
wire [8:0] pcxbuf_empty;
wire [8:0] pqm_empty;
wire [8:0] op_req_l1;
wire [8:0] kill_lsu_atm_req;
wire kill_lsu_req;
wire [8:0] atm_req_li;
wire [3:0] ipc_unit_sel_l1;
wire sel_repeat_li;
wire sel_nrepeat_drop_li;
wire sel_nrepeat_ndrop_li;
wire sel_nrepeat_drop_unused;
wire sel_nrepeat_ndrop_unused;
wire [8:0] req_nrepeat_drop_li;
wire [8:0] dropreg0;
wire [8:0] dropreg1;
wire [8:0] dropreg2;
wire [8:0] dropreg3;
wire [8:0] req_nrepeat_ndrop_li;
wire [8:0] atm_pq;
wire [8:0] req_repeat_drop_li;
wire [8:0] req_repeat_ndrop_li;
wire ifu_grant_li;
wire mmu_grant_li;
wire lsu_grant_li;
wire spu_grant_li;
wire lock_reg_scanin;
wire lock_reg_scanout;
wire favori_reg_scanin;
wire favori_reg_scanout;
wire favorim_reg_scanin;
wire favorim_reg_scanout;
wire favorls_reg_scanin;
wire favorls_reg_scanout;
wire sel_reg_scanin;
wire sel_reg_scanout;
wire grant_reg_scanin;
wire grant_reg_scanout;
wire ifu_grant_l1;
wire mmu_grant_l1;
wire lsu_grant_l1;
wire spu_grant_l1;
wire l1_atm_req_reg_scanin;
wire l1_atm_req_reg_scanout;
wire [8:0] ipc_atm_l1;
wire req_nrepeat_drop_reg_scanin;
wire req_nrepeat_drop_reg_scanout;
wire [8:0] req_nrepeat_drop_l1;
wire req_nrepeat_ndrop_reg_scanin;
wire req_nrepeat_ndrop_reg_scanout;
wire [8:0] req_nrepeat_ndrop_l1;
wire req_repeat_drop_reg_scanin;
wire req_repeat_drop_reg_scanout;
wire [8:0] ipc_req_repeat_drop_l1;
wire req_repeat_ndrop_reg_scanin;
wire req_repeat_ndrop_reg_scanout;
wire [8:0] ipc_req_repeat_ndrop_l1;
wire ifu_ndropped_pa;
wire mmu_ndropped_pa;
wire lsu_ndropped_pa;
wire spu_ndropped_pa;
wire req_dropped;
wire [8:0] pqm_req_drop;
wire req_dropped_;
wire req_dropped_lat;
wire [3:0] ipc_unit_sel_pa;
wire [3:0] ipc_dropreg_valid_pa;
wire req_dropped_lat_;
wire [8:0] dropreg0_in;
wire [8:0] dropreg1_in;
wire [8:0] dropreg2_in;
wire [8:0] dropreg3_in;
wire [8:0] req_pq;
wire [8:0] atm_pa;
wire ipc_pq_valid;
wire ifu_ndropped_l1;
wire mmu_ndropped_l1;
wire lsu_ndropped_l1;
wire spu_ndropped_l1;
wire ifu_dropped_pa;
wire mmu_dropped_pa;
wire lsu_dropped_pa;
wire spu_dropped_pa;
wire ifu_success_pa;
wire mmu_success_pa;
wire lsu_success_pa;
wire spu_success_pa;
wire inc_ifu;
wire max_count_reached;
wire clear_ifu;
wire hold_ifu;
wire [2:0] ifu_drop_cnt;
wire [2:0] ifu_drop_cnt_lat;
wire inc_mmu;
wire clear_mmu;
wire hold_mmu;
wire [2:0] mmu_drop_cnt;
wire [2:0] mmu_drop_cnt_lat;
wire inc_lsu;
wire clear_lsu;
wire hold_lsu;
wire [2:0] lsu_drop_cnt;
wire [2:0] lsu_drop_cnt_lat;
wire inc_spu;
wire clear_spu;
wire hold_spu;
wire [2:0] spu_drop_cnt;
wire [2:0] spu_drop_cnt_lat;
wire max_count_reached_in;
wire force_ifu_in;
wire force_mmu_in;
wire force_lsu_in;
wire force_spu_in;
wire force_ifu_mmu_in;
wire force_lsu_spu_in;
wire drop_cnt_scanin;
wire drop_cnt_scanout;
wire force_req_scanin;
wire force_req_scanout;
wire ifetch_pkt;
wire dload_pkt;
wire dstore_pkt;
wire sload_pkt;
wire sstore_pkt;
wire mmu_pkt;
wire ma_pkt;
wire [2:0] pcx_pkt;
wire [2:0] tid_pkt;
wire valid_pkt;
wire [8:0] req_pa;
wire [6:0] xbar_optype;
wire dff_xbar_type_scanin;
wire dff_xbar_type_scanout;
wire dff_unit_sel_pa_type_scanin;
wire dff_unit_sel_pa_type_scanout;
wire dff_unit_ndrop_pa_scanin;
wire dff_unit_ndrop_pa_scanout;
wire dff_req_drop_lat_scanin;
wire dff_req_drop_lat_scanout;
wire dff_req_drop_latx_scanin;
wire dff_req_drop_latx_scanout;
wire dff_dropreg_valid_scanin;
wire dff_dropreg_valid_scanout;
wire dff_dropreg0_scanin;
wire dff_dropreg0_scanout;
wire dff_dropreg1_scanin;
wire dff_dropreg1_scanout;
wire dff_dropreg2_scanin;
wire dff_dropreg2_scanout;
wire dff_dropreg3_scanin;
wire dff_dropreg3_scanout;
wire dff_req_pa_scanin;
wire dff_req_pa_scanout;
wire dff_atm_pa_scanin;
wire dff_atm_pa_scanout;
wire [8:0] pcx_grant_lb;
wire pqm0_scanin;
wire pqm0_scanout;
wire pqm1_scanin;
wire pqm1_scanout;
wire pqm2_scanin;
wire pqm2_scanout;
wire pqm3_scanin;
wire pqm3_scanout;
wire pqm4_scanin;
wire pqm4_scanout;
wire pqm5_scanin;
wire pqm5_scanout;
wire pqm6_scanin;
wire pqm6_scanout;
wire pqm7_scanin;
wire pqm7_scanout;
wire pqm8_scanin;
wire pqm8_scanout;
wire spares_scanin;
wire spares_scanout;


// globals
input		tcu_scan_en;
input           l2clk;
input		lbist_run;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           spc_aclk;
input           spc_bclk;
output          scan_out;


input           lsu_gkt_pmen;

input           ifu_l15_valid; // 0in known_driven
input           mmu_l15_valid; // 0in known_driven
input           lsu_l15_valid; // 0in known_driven
input           spu_l15_valid; // 0in known_driven

input [39:37]   ifu_l15_addr39_37;
input [8:6]     ifu_l15_addr8_6;
input [39:37]   mmu_l15_addr39_37;
input [8:6]     mmu_l15_addr8_6;
input [39:37]   lsu_l15_addr39_37;
input [8:6]     lsu_l15_addr8_6;
input [39:37]   spu_l15_addr39_37;
input [8:6]     spu_l15_addr8_6;

input           lsu_l15_lock; // 0in known_driven

input [8:0]     pcx_grant;

input [8:0]     ipd_optype;

input           ncu_pm_ff;
input           ncu_ba01_ff;
input           ncu_ba23_ff;
input           ncu_ba45_ff;
input           ncu_ba67_ff;


output          ipc_v0_ifu_new;
output          ipc_v0_ifu_shft;
output          ipc_v0_ifu_hold;

output          ipc_v1_ifu_new;
output          ipc_v1_ifu_hold;

output          ipc_v0_mmu_new;
output          ipc_v0_mmu_shft;
output          ipc_v0_mmu_hold;

output          ipc_v1_mmu_new;
output          ipc_v1_mmu_hold;

output          ipc_v0_lsu_new;
output          ipc_v0_lsu_shft;
output          ipc_v0_lsu_hold;

output          ipc_v1_lsu_new;
output          ipc_v1_lsu_hold;

output          ipc_v0_spu_new;
output          ipc_v0_spu_shft;
output          ipc_v0_spu_hold;

output          ipc_v1_spu_new;
output          ipc_v1_spu_hold;

output          l15_ifu_grant;
output          l15_mmu_grant;
output          l15_lsu_grant;
output          l15_spu_grant;

output          ipc_sel_ndrop_ifu_l1;
output          ipc_sel_ndrop_mmu_l1;
output          ipc_sel_ndrop_lsu_l1;
output          ipc_sel_ndrop_spu_l1;

output          ipc_sel_drop_ifu_l1;
output          ipc_sel_drop_mmu_l1;
output          ipc_sel_drop_lsu_l1;
output          ipc_sel_drop_spu_l1;

output [3:0]    ipc_dropreg_wen;
output          ipc_pq_clken;

output [8:0]    ipc_op_req_li;
output [8:0]    ipc_atm_req_li;


output [6:0]    l15_pmu_xbar_optype;


// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
assign se = tcu_scan_en ;
// end scan


////////////////////////////////////////////////////////
gkt_ipc_ctl_l1clkhdr_ctl_macro clkgen 
  (
   .l2clk(l2clk),
   .l1en (1'b1 ),
   .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));
////////////////////////////////////////////////////////
gkt_ipc_ctl_msff_ctl_macro__width_1 pmen_reg  
(
 .scan_in(pmen_reg_scanin),
 .scan_out(pmen_reg_scanout),
 .l1clk	(l1clk),
 .din	(lsu_gkt_pmen),
 .dout	(gkt_pmen),
  .siclk(siclk),
  .soclk(soclk)
 );

////////////////////////////////////////////////////////
// Partial bank support
// N2 supports partial L2 banks.
// Following truth table is used by all spc cores and sii to
// route the request to the correct bank
//
//PM          avaialble banks           req[2] req[1] req[0]
//        ba67 ba45 ba23 ba01
//-----------------------------------------------------------
//0        x   x   x   x                pa[8]  pa[7]  pa[6]
//1        0   0   0   0   illegal      0      0      pa[6]
//1        0   0   0   1                0      0      pa[6]
//1        0   0   1   0                0      1      pa[6]
//1        0   0   1   1                0      pa[7]  pa[6]
//1        0   1   0   0                1      0      pa[6]
//1        0   1   0   1                pa[7]  0      pa[6]
//1        0   1   1   0                pa[7] ~pa[7]  pa[6]
//1        0   1   1   1   illegal      0      pa[7]  pa[6]
//1        1   0   0   0                1      1      pa[6]
//1        1   0   0   1                pa[7]  pa[7]  pa[6]
//1        1   0   1   0                pa[7]  1      pa[6]
//1        1   0   1   1   illegal      0      pa[7]  pa[6]
//1        1   1   0   0                1      pa[7]  pa[6]
//1        1   1   0   1   illegal      1      pa[7]  pa[6]
//1        1   1   1   0   illegal      1      pa[7]  pa[6]
//1        1   1   1   1                pa[8]  pa[7]  pa[6]

//.i 5
//.o 8
//.ilb pm ba67 ba45 ba23 ba01 
//.olb sel8_pa8 sel8_pa7 sel8_1 sel8_0 sel7_pa7 sel_pa7b sel7_1 sel7_0
//.type fr
//0 - - - -     1 0 0 0    1 0 0 0
//1 0 0 0 0     0 0 0 1    0 0 0 1
//1 0 0 0 1     0 0 0 1    0 0 0 1
//1 0 0 1 0     0 0 0 1    0 0 1 0
//1 0 0 1 1     0 0 0 1    1 0 0 0
//1 0 1 0 0     0 0 1 0    0 0 0 1
//1 0 1 0 1     0 1 0 0    0 0 0 1
//1 0 1 1 0     0 1 0 0    0 1 0 0
//1 0 1 1 1     0 0 0 1    1 0 0 0
//1 1 0 0 0     0 0 1 0    0 0 1 0
//1 1 0 0 1     0 1 0 0    1 0 0 0
//1 1 0 1 0     0 1 0 0    0 0 1 0
//1 1 0 1 1     0 0 0 1    1 0 0 0
//1 1 1 0 0     0 0 1 0    1 0 0 0
//1 1 1 0 1     0 0 1 0    1 0 0 0
//1 1 1 1 0     0 0 1 0    1 0 0 0
//1 1 1 1 1     1 0 0 0    1 0 0 0
//v5.0 = (ba67&ba45&ba23&ba01) | (!pm);

//v5.1 = (pm&ba67&!ba45&ba23&!ba01) | (pm&!ba67&ba45&ba23&!ba01) | (pm&ba67
//    &!ba45&!ba23&ba01) | (pm&!ba67&ba45&!ba23&ba01);

//v5.2 = (pm&ba67&!ba23&!ba01) | (pm&ba45&!ba23&!ba01) | (pm&ba67&ba45&!ba01) | (
//    pm&ba67&ba45&!ba23);

//v5.3 = (pm&!ba67&!ba45) | (pm&!ba45&ba23&ba01) | (pm&!ba67&ba23&ba01);

//v5.4 = (ba67&ba45) | (ba23&ba01) | (ba67&ba01) | (!pm);

//v5.5 = (pm&!ba67&ba45&ba23&!ba01);

//v5.6 = (pm&ba67&!ba45&!ba01) | (pm&!ba45&ba23&!ba01);

//v5.7 = (pm&!ba67&!ba23);
gkt_ipc_ctl_msff_ctl_macro__width_5 dff_ncu_pb 
(
 .scan_in(dff_ncu_pb_scanin),
 .scan_out(dff_ncu_pb_scanout),
 .l1clk(l1clk),
 .din  ({ncu_pm_ff,ncu_ba01_ff,ncu_ba23_ff,ncu_ba45_ff,ncu_ba67_ff}),
 .dout ({pm,ba01,ba23,ba45,ba67}),
  .siclk(siclk),
  .soclk(soclk)
 );

assign sel8_pa8_in = (ba67 & ba45 & ba23 & ba01) | (!pm);

assign sel8_pa7_in = (pm & ba67 & !ba45 & ba23 & !ba01) | 
                      (pm & !ba67 & ba45 & ba23 & !ba01) | 
                      (pm & ba67 & !ba45 & !ba23 & ba01) | 
                      (pm & !ba67 & ba45 & !ba23 & ba01);

assign sel8_1_in = (pm & ba67 & !ba23 & !ba01) | 
                    (pm & ba45 & !ba23 & !ba01) | 
                    (pm & ba67 & ba45 & !ba01) | 
                    (pm & ba67 & ba45 & !ba23);

assign sel7_pa7_in = (ba67 & ba45) | 
                      (ba23 & ba01) | 
                      (ba67 & ba01) | 
                      (!pm);

assign sel7_pa7b_in = (pm & !ba67 & ba45 & ba23 & !ba01);

assign sel7_1_in = (pm & ba67 & !ba45 & !ba01) | 
                    (pm & !ba45 & ba23 & !ba01);


gkt_ipc_ctl_msff_ctl_macro__width_6 dff_pb_sel 
(
 .scan_in(dff_pb_sel_scanin),
 .scan_out(dff_pb_sel_scanout),
 .l1clk(l1clk),
 .din  ({sel8_pa8_in, sel8_pa7_in, sel8_1_in, sel7_pa7_in, sel7_pa7b_in, sel7_1_in}),
 .dout ({sel8_pa8, sel8_pa7, sel8_1, sel7_pa7, sel7_pa7b, sel7_1}),
  .siclk(siclk),
  .soclk(soclk)
 );

////////////////////////////////////////////////////////


// Latch ifu data in 2-entry FIFO

assign v0_ifu_in = (v0_ifu & !ifu_shift) |  ifu_l15_valid | v1_ifu;
assign v1_ifu_in = (v1_ifu & !ifu_shift) | (v1_ifu & ifu_l15_valid) | (v0_ifu & ifu_l15_valid & !ifu_shift);

assign ipc_v0_ifu_new = (!v0_ifu) | (v0_ifu & !v1_ifu & ifu_shift);
assign ipc_v0_ifu_shft = v1_ifu & ifu_shift;
assign ipc_v0_ifu_hold = (v0_ifu & !ifu_shift);
// 0in one_hot -var {ipc_v0_ifu_new,ipc_v0_ifu_shft,ipc_v0_ifu_hold}

//assign ipc_v1_ifu_new = (~v1_ifu | ifu_shift);
//assign ipc_v1_ifu_hold = (v1_ifu & !ifu_shift);
// changed for power
assign ipc_v1_ifu_new = (~v1_ifu | ifu_shift) & v1_ifu_in;
assign ipc_v1_ifu_hold = (v1_ifu & !ifu_shift) | ~v1_ifu_in;

assign ifu_eff_addr_8 = (sel8_pa8 & ifu_l15_addr8_6[8]) |
                        (sel8_pa7 & ifu_l15_addr8_6[7]) |
                        (sel8_1);

assign ifu_eff_addr_7 = (sel7_pa7 & ifu_l15_addr8_6[7]) |
                        (sel7_pa7b & ~ifu_l15_addr8_6[7]) |
                        (sel7_1);

// determine bank being requested by ifu and latch it in two-entry fifo.
assign ifu_l15_io = ifu_l15_addr39_37[39] & ~(~ifu_l15_addr39_37[38] & ifu_l15_addr39_37[37]);
assign ifu_l15_bank[0] = ~ifu_l15_io & ~ifu_eff_addr_8 & ~ifu_eff_addr_7 & ~ifu_l15_addr8_6[6];
assign ifu_l15_bank[1] = ~ifu_l15_io & ~ifu_eff_addr_8 & ~ifu_eff_addr_7 &  ifu_l15_addr8_6[6];
assign ifu_l15_bank[2] = ~ifu_l15_io & ~ifu_eff_addr_8 &  ifu_eff_addr_7 & ~ifu_l15_addr8_6[6];
assign ifu_l15_bank[3] = ~ifu_l15_io & ~ifu_eff_addr_8 &  ifu_eff_addr_7 &  ifu_l15_addr8_6[6];
assign ifu_l15_bank[4] = ~ifu_l15_io &  ifu_eff_addr_8 & ~ifu_eff_addr_7 & ~ifu_l15_addr8_6[6];
assign ifu_l15_bank[5] = ~ifu_l15_io &  ifu_eff_addr_8 & ~ifu_eff_addr_7 &  ifu_l15_addr8_6[6];
assign ifu_l15_bank[6] = ~ifu_l15_io &  ifu_eff_addr_8 &  ifu_eff_addr_7 & ~ifu_l15_addr8_6[6];
assign ifu_l15_bank[7] = ~ifu_l15_io &  ifu_eff_addr_8 &  ifu_eff_addr_7 &  ifu_l15_addr8_6[6];
assign ifu_l15_bank[8] = ifu_l15_io;

assign v0_ifu_req_in[8:0] = ({9{ipc_v0_ifu_new & ifu_l15_valid}} & ifu_l15_bank[8:0]) |
                            ({9{ipc_v0_ifu_shft}} & v1_ifu_req[8:0]) |
                            ({9{ipc_v0_ifu_hold}} & v0_ifu_req[8:0]);

assign v1_ifu_req_in[8:0] = ({9{ipc_v1_ifu_new & ifu_l15_valid}} & ifu_l15_bank[8:0]) |
                            ({9{ipc_v1_ifu_hold}} & v1_ifu_req[8:0]);

gkt_ipc_ctl_msff_ctl_macro__width_9 dff_ifu_req_v0 
(
 .scan_in(dff_ifu_req_v0_scanin),
 .scan_out(dff_ifu_req_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_ifu_req_in[8:0]),
 .dout (v0_ifu_req[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_9 dff_ifu_req_v1 
(
 .scan_in(dff_ifu_req_v1_scanin),
 .scan_out(dff_ifu_req_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_ifu_req_in[8:0]),
 .dout (v1_ifu_req[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_1 dff_ifu_v0 
(
 .scan_in(dff_ifu_v0_scanin),
 .scan_out(dff_ifu_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_ifu_in),
 .dout (v0_ifu),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_1 dff_ifu_v1 
(
 .scan_in(dff_ifu_v1_scanin),
 .scan_out(dff_ifu_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_ifu_in),
 .dout (v1_ifu),
  .siclk(siclk),
  .soclk(soclk)
 );

////////////////////////////////////////////////////////
// Latch mmu data in 2-entry FIFO

assign v0_mmu_in = (v0_mmu & !mmu_shift) |  mmu_l15_valid | v1_mmu;
assign v1_mmu_in = (v1_mmu & !mmu_shift) | (v1_mmu & mmu_l15_valid) | (v0_mmu & mmu_l15_valid & !mmu_shift);

assign ipc_v0_mmu_new = (!v0_mmu) | (v0_mmu & !v1_mmu & mmu_shift);
assign ipc_v0_mmu_shft = v1_mmu & mmu_shift;
assign ipc_v0_mmu_hold = (v0_mmu & !mmu_shift);
// 0in one_hot -var {ipc_v0_mmu_new,ipc_v0_mmu_shft,ipc_v0_mmu_hold}

//assign ipc_v1_mmu_new = (~v1_mmu | mmu_shift);
//assign ipc_v1_mmu_hold = (v1_mmu & !mmu_shift);
// changed for power
assign ipc_v1_mmu_new = (~v1_mmu | mmu_shift) & v1_mmu_in;
assign ipc_v1_mmu_hold = (v1_mmu & !mmu_shift) | ~v1_mmu_in;

assign mmu_eff_addr_8 = (sel8_pa8 & mmu_l15_addr8_6[8]) |
                        (sel8_pa7 & mmu_l15_addr8_6[7]) |
                        (sel8_1);

assign mmu_eff_addr_7 = (sel7_pa7 & mmu_l15_addr8_6[7]) |
                        (sel7_pa7b & ~mmu_l15_addr8_6[7]) |
                        (sel7_1);

// determine bank being requested by mmu and latch it in two-entry fifo.
assign mmu_l15_io = mmu_l15_addr39_37[39] & ~(~mmu_l15_addr39_37[38] & mmu_l15_addr39_37[37]);
assign mmu_l15_bank[0] = ~mmu_l15_io & ~mmu_eff_addr_8 & ~mmu_eff_addr_7 & ~mmu_l15_addr8_6[6];
assign mmu_l15_bank[1] = ~mmu_l15_io & ~mmu_eff_addr_8 & ~mmu_eff_addr_7 &  mmu_l15_addr8_6[6];
assign mmu_l15_bank[2] = ~mmu_l15_io & ~mmu_eff_addr_8 &  mmu_eff_addr_7 & ~mmu_l15_addr8_6[6];
assign mmu_l15_bank[3] = ~mmu_l15_io & ~mmu_eff_addr_8 &  mmu_eff_addr_7 &  mmu_l15_addr8_6[6];
assign mmu_l15_bank[4] = ~mmu_l15_io &  mmu_eff_addr_8 & ~mmu_eff_addr_7 & ~mmu_l15_addr8_6[6];
assign mmu_l15_bank[5] = ~mmu_l15_io &  mmu_eff_addr_8 & ~mmu_eff_addr_7 &  mmu_l15_addr8_6[6];
assign mmu_l15_bank[6] = ~mmu_l15_io &  mmu_eff_addr_8 &  mmu_eff_addr_7 & ~mmu_l15_addr8_6[6];
assign mmu_l15_bank[7] = ~mmu_l15_io &  mmu_eff_addr_8 &  mmu_eff_addr_7 &  mmu_l15_addr8_6[6];
assign mmu_l15_bank[8] = mmu_l15_io;

assign v0_mmu_req_in[8:0] = ({9{ipc_v0_mmu_new & mmu_l15_valid}} & mmu_l15_bank[8:0]) |
                            ({9{ipc_v0_mmu_shft}} & v1_mmu_req[8:0]) |
                            ({9{ipc_v0_mmu_hold}} & v0_mmu_req[8:0]);

assign v1_mmu_req_in[8:0] = ({9{ipc_v1_mmu_new & mmu_l15_valid}} & mmu_l15_bank[8:0]) |
                            ({9{ipc_v1_mmu_hold}} & v1_mmu_req[8:0]);

gkt_ipc_ctl_msff_ctl_macro__width_9 dff_mmu_req_v0 
(
 .scan_in(dff_mmu_req_v0_scanin),
 .scan_out(dff_mmu_req_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_mmu_req_in[8:0]),
 .dout (v0_mmu_req[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_9 dff_mmu_req_v1 
(
 .scan_in(dff_mmu_req_v1_scanin),
 .scan_out(dff_mmu_req_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_mmu_req_in[8:0]),
 .dout (v1_mmu_req[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_1 dff_mmu_v0 
(
 .scan_in(dff_mmu_v0_scanin),
 .scan_out(dff_mmu_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_mmu_in),
 .dout (v0_mmu),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_1 dff_mmu_v1 
(
 .scan_in(dff_mmu_v1_scanin),
 .scan_out(dff_mmu_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_mmu_in),
 .dout (v1_mmu),
  .siclk(siclk),
  .soclk(soclk)
 );

////////////////////////////////////////////////////////
// Latch lsu data in 2-entry FIFO
assign v0_lsu_in = (v0_lsu & ~lsu_shift) | lsu_l15_valid | v1_lsu ;
assign v1_lsu_in = (v1_lsu & ~lsu_shift) | (v1_lsu & lsu_l15_valid) | (v0_lsu & lsu_l15_valid & ~lsu_shift);

assign ipc_v0_lsu_new = (~v0_lsu) | (v0_lsu & ~v1_lsu & lsu_shift);
assign ipc_v0_lsu_shft = v1_lsu & lsu_shift;
assign ipc_v0_lsu_hold = (v0_lsu & ~lsu_shift);
// 0in one_hot -var {ipc_v0_lsu_new,ipc_v0_lsu_shft,ipc_v0_lsu_hold}


//assign ipc_v1_lsu_new = (~v1_lsu | lsu_shift);
//assign ipc_v1_lsu_hold = (v1_lsu & !lsu_shift);
//changed for power saving 
assign ipc_v1_lsu_new = (~v1_lsu | lsu_shift) & v1_lsu_in;
assign ipc_v1_lsu_hold = (v1_lsu & !lsu_shift) | ~v1_lsu_in;


assign v0_lsu_lock_in = (ipc_v0_lsu_new & lsu_l15_lock & lsu_l15_valid) | 
                        (ipc_v0_lsu_shft & v1_lsu_lock) | 
                        (ipc_v0_lsu_hold & v0_lsu_lock);

assign v1_lsu_lock_in = (ipc_v1_lsu_new & lsu_l15_lock & lsu_l15_valid) | 
                        (ipc_v1_lsu_hold & v1_lsu_lock);

assign lsu_eff_addr_8 = (sel8_pa8 & lsu_l15_addr8_6[8]) |
                        (sel8_pa7 & lsu_l15_addr8_6[7]) |
                        (sel8_1);

assign lsu_eff_addr_7 = (sel7_pa7 & lsu_l15_addr8_6[7]) |
                        (sel7_pa7b & ~lsu_l15_addr8_6[7]) |
                        (sel7_1);

// determine bank being requested by lsu and latch it in two-entry fifo.
assign lsu_l15_io = lsu_l15_addr39_37[39] & ~(~lsu_l15_addr39_37[38] & lsu_l15_addr39_37[37]);
assign lsu_l15_bank[0] = ~lsu_l15_io & ~lsu_eff_addr_8 & ~lsu_eff_addr_7 & ~lsu_l15_addr8_6[6];
assign lsu_l15_bank[1] = ~lsu_l15_io & ~lsu_eff_addr_8 & ~lsu_eff_addr_7 &  lsu_l15_addr8_6[6];
assign lsu_l15_bank[2] = ~lsu_l15_io & ~lsu_eff_addr_8 &  lsu_eff_addr_7 & ~lsu_l15_addr8_6[6];
assign lsu_l15_bank[3] = ~lsu_l15_io & ~lsu_eff_addr_8 &  lsu_eff_addr_7 &  lsu_l15_addr8_6[6];
assign lsu_l15_bank[4] = ~lsu_l15_io &  lsu_eff_addr_8 & ~lsu_eff_addr_7 & ~lsu_l15_addr8_6[6];
assign lsu_l15_bank[5] = ~lsu_l15_io &  lsu_eff_addr_8 & ~lsu_eff_addr_7 &  lsu_l15_addr8_6[6];
assign lsu_l15_bank[6] = ~lsu_l15_io &  lsu_eff_addr_8 &  lsu_eff_addr_7 & ~lsu_l15_addr8_6[6];
assign lsu_l15_bank[7] = ~lsu_l15_io &  lsu_eff_addr_8 &  lsu_eff_addr_7 &  lsu_l15_addr8_6[6];
assign lsu_l15_bank[8] = lsu_l15_io;

assign v0_lsu_req_in[8:0] = ({9{ipc_v0_lsu_new & lsu_l15_valid}} & lsu_l15_bank[8:0]) |
                            ({9{ipc_v0_lsu_shft}} & v1_lsu_req[8:0]) |
                            ({9{ipc_v0_lsu_hold}} & v0_lsu_req[8:0]);

assign v1_lsu_req_in[8:0] = ({9{ipc_v1_lsu_new & lsu_l15_valid}} & lsu_l15_bank[8:0]) |
                            ({9{ipc_v1_lsu_hold}} & v1_lsu_req[8:0]);

gkt_ipc_ctl_msff_ctl_macro__width_9 dff_lsu_req_v0 
(
 .scan_in(dff_lsu_req_v0_scanin),
 .scan_out(dff_lsu_req_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_lsu_req_in[8:0]),
 .dout (v0_lsu_req[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_9 dff_lsu_req_v1 
(
 .scan_in(dff_lsu_req_v1_scanin),
 .scan_out(dff_lsu_req_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_lsu_req_in[8:0]),
 .dout (v1_lsu_req[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_1 dff_lsu_v0 
(
 .scan_in(dff_lsu_v0_scanin),
 .scan_out(dff_lsu_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_lsu_in),
 .dout (v0_lsu),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_1 dff_lsu_v1 
(
 .scan_in(dff_lsu_v1_scanin),
 .scan_out(dff_lsu_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_lsu_in),
 .dout (v1_lsu),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_1 dff_lsu_lock_v0 
(
 .scan_in(dff_lsu_lock_v0_scanin),
 .scan_out(dff_lsu_lock_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_lsu_lock_in),
 .dout (v0_lsu_lock),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_1 dff_lsu_lock_v1 
(
 .scan_in(dff_lsu_lock_v1_scanin),
 .scan_out(dff_lsu_lock_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_lsu_lock_in),
 .dout (v1_lsu_lock),
  .siclk(siclk),
  .soclk(soclk)
 );

////////////////////////////////////////////////////////
// Latch spu data in 2-entry FIFO

assign v0_spu_in = (v0_spu & !spu_shift) |  spu_l15_valid | v1_spu;
assign v1_spu_in = (v1_spu & !spu_shift) | (v1_spu & spu_l15_valid) | (v0_spu & spu_l15_valid & !spu_shift);

assign ipc_v0_spu_new = (!v0_spu) | (v0_spu & !v1_spu & spu_shift);
assign ipc_v0_spu_shft = v1_spu & spu_shift;
assign ipc_v0_spu_hold = (v0_spu & !spu_shift);
// 0in one_hot -var {ipc_v0_spu_new,ipc_v0_spu_shft,ipc_v0_spu_hold}

//assign ipc_v1_spu_new = (~v1_spu | spu_shift);
//assign ipc_v1_spu_hold = (v1_spu & !spu_shift);
// changed for power
assign ipc_v1_spu_new = (~v1_spu | spu_shift) & v1_spu_in;
assign ipc_v1_spu_hold = (v1_spu & !spu_shift) | ~v1_spu_in;

assign spu_eff_addr_8 = (sel8_pa8 & spu_l15_addr8_6[8]) |
                        (sel8_pa7 & spu_l15_addr8_6[7]) |
                        (sel8_1);

assign spu_eff_addr_7 = (sel7_pa7 & spu_l15_addr8_6[7]) |
                        (sel7_pa7b & ~spu_l15_addr8_6[7]) |
                        (sel7_1);

// determine bank being requested by spu and latch it in two-entry fifo.
assign spu_l15_io = spu_l15_addr39_37[39] & ~(~spu_l15_addr39_37[38] & spu_l15_addr39_37[37]);
assign spu_l15_bank[0] = ~spu_l15_io & ~spu_eff_addr_8 & ~spu_eff_addr_7 & ~spu_l15_addr8_6[6];
assign spu_l15_bank[1] = ~spu_l15_io & ~spu_eff_addr_8 & ~spu_eff_addr_7 &  spu_l15_addr8_6[6];
assign spu_l15_bank[2] = ~spu_l15_io & ~spu_eff_addr_8 &  spu_eff_addr_7 & ~spu_l15_addr8_6[6];
assign spu_l15_bank[3] = ~spu_l15_io & ~spu_eff_addr_8 &  spu_eff_addr_7 &  spu_l15_addr8_6[6];
assign spu_l15_bank[4] = ~spu_l15_io &  spu_eff_addr_8 & ~spu_eff_addr_7 & ~spu_l15_addr8_6[6];
assign spu_l15_bank[5] = ~spu_l15_io &  spu_eff_addr_8 & ~spu_eff_addr_7 &  spu_l15_addr8_6[6];
assign spu_l15_bank[6] = ~spu_l15_io &  spu_eff_addr_8 &  spu_eff_addr_7 & ~spu_l15_addr8_6[6];
assign spu_l15_bank[7] = ~spu_l15_io &  spu_eff_addr_8 &  spu_eff_addr_7 &  spu_l15_addr8_6[6];
assign spu_l15_bank[8] = spu_l15_io;

assign v0_spu_req_in[8:0] = ({9{ipc_v0_spu_new & spu_l15_valid}} & spu_l15_bank[8:0]) |
                            ({9{ipc_v0_spu_shft}} & v1_spu_req[8:0]) |
                            ({9{ipc_v0_spu_hold}} & v0_spu_req[8:0]);

assign v1_spu_req_in[8:0] = ({9{ipc_v1_spu_new & spu_l15_valid}} & spu_l15_bank[8:0]) |
                            ({9{ipc_v1_spu_hold}} & v1_spu_req[8:0]);

gkt_ipc_ctl_msff_ctl_macro__width_9 dff_spu_req_v0 
(
 .scan_in(dff_spu_req_v0_scanin),
 .scan_out(dff_spu_req_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_spu_req_in[8:0]),
 .dout (v0_spu_req[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_9 dff_spu_req_v1 
(
 .scan_in(dff_spu_req_v1_scanin),
 .scan_out(dff_spu_req_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_spu_req_in[8:0]),
 .dout (v1_spu_req[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );


gkt_ipc_ctl_msff_ctl_macro__width_1 dff_spu_v0 
(
 .scan_in(dff_spu_v0_scanin),
 .scan_out(dff_spu_v0_scanout),
 .l1clk(l1clk),
 .din  (v0_spu_in),
 .dout (v0_spu),
  .siclk(siclk),
  .soclk(soclk)
 );
gkt_ipc_ctl_msff_ctl_macro__width_1 dff_spu_v1 
(
 .scan_in(dff_spu_v1_scanin),
 .scan_out(dff_spu_v1_scanout),
 .l1clk(l1clk),
 .din  (v1_spu_in),
 .dout (v1_spu),
  .siclk(siclk),
  .soclk(soclk)
 );


////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// generate selects for mux feeding input flop
// 3 favor bits
// f_im selects between ifu and mmu
// f_ls selects between lsu and spu
// f_i selects between ifu/mmu and lsu/spu

assign f_im_in = (((f_im & ~sel_ifu_l1) | sel_mmu_l1) | force_ifu) & ~force_mmu;
assign f_ls_in = (((f_ls & ~sel_lsu_l1) | sel_spu_l1) | force_lsu) & ~force_spu;
assign f_i_in = (((f_i & ~sel_ifu_mmu_l1) | sel_lsu_spu_l1) | force_ifu_mmu) & ~force_lsu_spu;

//If a request from a unit A  gets dropped, and no other unit has a valid request,
//(including unit A), then the dropped req will not be tried for 1 clk. i.e there
// will be a one cycle hole because the unit_v will not be set.

assign ifu_v = v0_ifu_in | ipc_dropreg_valid[0];
assign mmu_v = v0_mmu_in | ipc_dropreg_valid[1];
assign lsu_v = v0_lsu_in | ipc_dropreg_valid[2];
assign spu_v = v0_spu_in | ipc_dropreg_valid[3];

assign ipc_sel_ifu = (ifu_v&!mmu_v&!lsu_v&!spu_v&!lock_acc) | 
                     (f_im_in&ifu_v&!lsu_v&!spu_v&!lock_acc) | 
                     (f_i_in&ifu_v&!mmu_v&!lock_acc) | 
                     (f_i_in&f_im_in&ifu_v&!lock_acc);

assign ipc_sel_mmu = (!ifu_v&mmu_v&!lsu_v&!spu_v&!lock_acc) | 
                     (!f_im_in&mmu_v&!lsu_v&!spu_v&!lock_acc) | 
                     (f_i_in&!ifu_v&mmu_v&!lock_acc) | 
                     (f_i_in&!f_im_in&mmu_v&!lock_acc);

assign ipc_sel_lsu = (!ifu_v&!mmu_v&lsu_v&!spu_v) | 
                     (f_ls_in&!ifu_v&!mmu_v&lsu_v) | 
                     (!f_i_in&lsu_v&!spu_v) | 
                     (!f_i_in&f_ls_in&lsu_v) |  (lsu_v&lock_acc);

assign ipc_sel_spu = (!ifu_v&!mmu_v&!lsu_v&spu_v&!lock_acc) | 
                     (!f_ls_in&!ifu_v&!mmu_v&spu_v&!lock_acc) | 
                     (!f_i_in&!lsu_v&spu_v&!lock_acc) | 
                     (!f_i_in&!f_ls_in&spu_v&!lock_acc);
                     
// 0in bits_on -var {ipc_sel_ifu,ipc_sel_mmu,ipc_sel_lsu,ipc_sel_spu} -max 1 

assign ipc_sel_ifu_mmu = ipc_sel_ifu | ipc_sel_mmu;
assign ipc_sel_lsu_spu = ipc_sel_lsu | ipc_sel_spu;

// set lock access when lsu selected and lock bit is set.
// it remains set until the next time lsu is selected with lock bit not set.
assign lock_acc_in = ((ipc_sel_lsu & v0_lsu_lock_in) | (lock_acc)) & ~(ipc_sel_lsu & ~v0_lsu_lock_in);
assign unit_sel_li[3:0] = {ipc_sel_spu,ipc_sel_lsu,ipc_sel_mmu,ipc_sel_ifu};


// pcxbuf is empty if pqm_empty and no request in flight
assign pcxbuf_empty[8:0] = pqm_empty[8:0] & ~op_req_l1[8:0];

// kill the lsu request if it is atomic and the buffers are not empty in pcx
assign kill_lsu_atm_req[8:0] = ({9{v0_lsu_lock_in}} & v0_lsu_req_in[8:0] & ~pcxbuf_empty[8:0]);
assign kill_lsu_req = |(kill_lsu_atm_req[8:0]);


assign atm_req_li[8:0] =  ({9{ipc_sel_lsu & v0_lsu_lock_in & ~(ipc_dropreg_valid[2] & ~ipc_unit_sel_l1[2])}} & v0_lsu_req_in[8:0] & pcxbuf_empty[8:0]);

// 0in bits_on -var {sel_nrepeat_drop_li, sel_nrepeat_ndrop_li, (sel_repeat_li & req_dropped), (sel_repeat_li & ~req_dropped)} -max 1 

assign sel_repeat_li = unit_sel_li[0] & ipc_unit_sel_l1[0] |
                       unit_sel_li[1] & ipc_unit_sel_l1[1] |
                       unit_sel_li[2] & ipc_unit_sel_l1[2] |
                       unit_sel_li[3] & ipc_unit_sel_l1[3];

//assign sel_repeat_drop_li = sel_repeat_li & req_dropped;
//assign sel_repeat_ndrop_li = sel_repeat_li & ~req_dropped;


assign sel_nrepeat_drop_li = unit_sel_li[0] & ~ipc_unit_sel_l1[0] & ipc_dropreg_valid[0] |
                             unit_sel_li[1] & ~ipc_unit_sel_l1[1] & ipc_dropreg_valid[1] |
                             unit_sel_li[2] & ~ipc_unit_sel_l1[2] & ipc_dropreg_valid[2] |
                             unit_sel_li[3] & ~ipc_unit_sel_l1[3] & ipc_dropreg_valid[3];

assign sel_nrepeat_ndrop_li = unit_sel_li[0] & ~ipc_unit_sel_l1[0] & ~ipc_dropreg_valid[0] |
                              unit_sel_li[1] & ~ipc_unit_sel_l1[1] & ~ipc_dropreg_valid[1] |
                              unit_sel_li[2] & ~ipc_unit_sel_l1[2] & ~ipc_dropreg_valid[2] |
                              unit_sel_li[3] & ~ipc_unit_sel_l1[3] & ~ipc_dropreg_valid[3];

assign sel_nrepeat_drop_unused = sel_nrepeat_drop_li;
assign sel_nrepeat_ndrop_unused = sel_nrepeat_ndrop_li;


// fold the select into the request so that the mux is simplified

assign req_nrepeat_drop_li[8:0] = ({9{unit_sel_li[0] & ~ipc_unit_sel_l1[0] & ipc_dropreg_valid[0]}} & dropreg0[8:0]) | 
                                  ({9{unit_sel_li[1] & ~ipc_unit_sel_l1[1] & ipc_dropreg_valid[1]}} & dropreg1[8:0]) |
                                  ({9{unit_sel_li[2] & ~ipc_unit_sel_l1[2] & ipc_dropreg_valid[2]}} & dropreg2[8:0]) |
                                  ({9{unit_sel_li[3] & ~ipc_unit_sel_l1[3] & ipc_dropreg_valid[3]}} & dropreg3[8:0]);

assign req_nrepeat_ndrop_li[8:0] = ({9{unit_sel_li[0] & ~ipc_unit_sel_l1[0] & ~ipc_dropreg_valid[0]}} & v0_ifu_req_in[8:0]) | 
                                   ({9{unit_sel_li[1] & ~ipc_unit_sel_l1[1] & ~ipc_dropreg_valid[1]}} & v0_mmu_req_in[8:0]) |
                                   ({9{unit_sel_li[2] & ~ipc_unit_sel_l1[2] & ~ipc_dropreg_valid[2]}} & v0_lsu_req_in[8:0] & ~kill_lsu_atm_req[8:0] & ~atm_pq[8:0]) |
                                   ({9{unit_sel_li[3] & ~ipc_unit_sel_l1[3] & ~ipc_dropreg_valid[3]}} & v0_spu_req_in[8:0]);


// this still needs to be qualified by req_dropped in next cycle
assign req_repeat_drop_li[8:0] = ({9{sel_repeat_li}} & op_req_l1[8:0]);

// this still needs to be qualified by req_dropped in next cycle
assign req_repeat_ndrop_li[8:0] = ({9{unit_sel_li[0] & ipc_unit_sel_l1[0]}} & v0_ifu_req_in[8:0]) | 
                                  ({9{unit_sel_li[1] & ipc_unit_sel_l1[1]}} & v0_mmu_req_in[8:0]) |
                                  ({9{unit_sel_li[2] & ipc_unit_sel_l1[2]}} & v0_lsu_req_in[8:0] & ~kill_lsu_atm_req[8:0] & ~atm_pq[8:0]) |
                                  ({9{unit_sel_li[3] & ipc_unit_sel_l1[3]}} & v0_spu_req_in[8:0]);


// optimize generation of grant
// l15_ifu_grant = sel_ifu_l1 & v0_ifu & ~ipc_dropreg_valid[0]
// l15_lsu_grant = sel_lsu_l1 & v0_lsu & ~ipc_dropreg_valid[2] & ~kill_lsu_req_l1;

assign ifu_grant_li = ipc_sel_ifu & v0_ifu_in & ~(ipc_dropreg_valid[0] & ~ipc_unit_sel_l1[0]);
assign mmu_grant_li = ipc_sel_mmu & v0_mmu_in & ~(ipc_dropreg_valid[1] & ~ipc_unit_sel_l1[1]);
assign lsu_grant_li = ipc_sel_lsu & v0_lsu_in & ~kill_lsu_req & ~(ipc_dropreg_valid[2] & ~ipc_unit_sel_l1[2]);
assign spu_grant_li = ipc_sel_spu & v0_spu_in & ~(ipc_dropreg_valid[3] & ~ipc_unit_sel_l1[3]);


gkt_ipc_ctl_msff_ctl_macro__width_1 lock_reg  
(
 .scan_in(lock_reg_scanin),
 .scan_out(lock_reg_scanout),
 .l1clk	(l1clk),
 .din	(lock_acc_in),
 .dout	(lock_acc),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_1 favori_reg  
(
 .scan_in(favori_reg_scanin),
 .scan_out(favori_reg_scanout),
 .l1clk	(l1clk),
	.din	(f_i_in),
 .dout	(f_i),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_1 favorim_reg  
(
 .scan_in(favorim_reg_scanin),
 .scan_out(favorim_reg_scanout),
 .l1clk	(l1clk),
 .din	(f_im_in),
 .dout	(f_im),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_1 favorls_reg  
(
 .scan_in(favorls_reg_scanin),
 .scan_out(favorls_reg_scanout),
 .l1clk	(l1clk),
 .din	(f_ls_in),
 .dout	(f_ls),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_6 sel_reg  
(
 .scan_in(sel_reg_scanin),
 .scan_out(sel_reg_scanout),
 .l1clk	(l1clk),
 .din	({ipc_sel_ifu,ipc_sel_mmu,ipc_sel_lsu,ipc_sel_spu,ipc_sel_ifu_mmu, ipc_sel_lsu_spu}),
 .dout	({sel_ifu_l1,sel_mmu_l1,sel_lsu_l1,sel_spu_l1,sel_ifu_mmu_l1,sel_lsu_spu_l1}),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_4 grant_reg  
(
 .scan_in(grant_reg_scanin),
 .scan_out(grant_reg_scanout),
 .l1clk	(l1clk),
 .din	({ifu_grant_li,mmu_grant_li,lsu_grant_li,spu_grant_li}),
 .dout	({ifu_grant_l1,mmu_grant_l1,lsu_grant_l1,spu_grant_l1}),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_9 l1_atm_req_reg  
(
 .scan_in(l1_atm_req_reg_scanin),
 .scan_out(l1_atm_req_reg_scanout),
 .l1clk	(l1clk),
 .din	(atm_req_li[8:0]),
 .dout	(ipc_atm_l1[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );


gkt_ipc_ctl_msff_ctl_macro__width_9 req_nrepeat_drop_reg  
(
 .scan_in(req_nrepeat_drop_reg_scanin),
 .scan_out(req_nrepeat_drop_reg_scanout),
 .l1clk	(l1clk),
 .din	(req_nrepeat_drop_li[8:0]),
 .dout	(req_nrepeat_drop_l1[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_9 req_nrepeat_ndrop_reg  
(
 .scan_in(req_nrepeat_ndrop_reg_scanin),
 .scan_out(req_nrepeat_ndrop_reg_scanout),
 .l1clk	(l1clk),
 .din	(req_nrepeat_ndrop_li[8:0]),
 .dout	(req_nrepeat_ndrop_l1[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_9 req_repeat_drop_reg  
(
 .scan_in(req_repeat_drop_reg_scanin),
 .scan_out(req_repeat_drop_reg_scanout),
 .l1clk	(l1clk),
 .din	(req_repeat_drop_li[8:0]),
 .dout	(ipc_req_repeat_drop_l1[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

gkt_ipc_ctl_msff_ctl_macro__width_9 req_repeat_ndrop_reg  
(
 .scan_in(req_repeat_ndrop_reg_scanin),
 .scan_out(req_repeat_ndrop_reg_scanout),
 .l1clk	(l1clk),
 .din	(req_repeat_ndrop_li[8:0]),
 .dout	(ipc_req_repeat_ndrop_l1[8:0]),
  .siclk(siclk),
  .soclk(soclk)
 );


assign l15_ifu_grant = ifu_grant_l1 & ifu_ndropped_pa;
assign l15_mmu_grant = mmu_grant_l1 & mmu_ndropped_pa;
assign l15_lsu_grant = lsu_grant_l1 & lsu_ndropped_pa;
assign l15_spu_grant = spu_grant_l1 & spu_ndropped_pa;


assign ifu_shift = l15_ifu_grant;
assign mmu_shift = l15_mmu_grant;
assign lsu_shift = l15_lsu_grant;
assign spu_shift = l15_spu_grant;

// do not use sel_lsu_l1 &~kill_lsu_req_l1 over here. If there are any lsu requests
// in the drop registers we want them to empty out.

assign ipc_unit_sel_l1[3:0] = {sel_spu_l1,sel_lsu_l1,sel_mmu_l1,sel_ifu_l1};


/////////////////////////////////////////////////////////////////////////
// PQ cycle
////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
// requests are sent speculatively to PCX. They can get dropped by PCX if it does
// not have room.
assign req_dropped = (|(pqm_req_drop[8:0]));
assign req_dropped_ = ~(|(pqm_req_drop[8:0]));


// atomic request should never be dropped. They are sent only when there is room for
// two entries.
// 0in bits_on -var {req_dropped, (|atm_pq[8:0])} -max 1

// dropped requests are saved off in drop registers.
// They are cleared when the corresponding unit gets sent out and not dropped.

assign ipc_dropreg_valid[0]  = (req_dropped_lat & ipc_unit_sel_pa[0]) | 
                               (ipc_dropreg_valid_pa[0] & ~(ipc_unit_sel_pa[0] & req_dropped_lat_));

assign ipc_dropreg_valid[1]  = (req_dropped_lat & ipc_unit_sel_pa[1]) | 
                               (ipc_dropreg_valid_pa[1] & ~(ipc_unit_sel_pa[1] & req_dropped_lat_));

assign ipc_dropreg_valid[2]  = (req_dropped_lat & ipc_unit_sel_pa[2]) | 
                               (ipc_dropreg_valid_pa[2] & ~(ipc_unit_sel_pa[2] & req_dropped_lat_));

assign ipc_dropreg_valid[3]  = (req_dropped_lat & ipc_unit_sel_pa[3]) | 
                               (ipc_dropreg_valid_pa[3] & ~(ipc_unit_sel_pa[3] & req_dropped_lat_));


// enables for writing into drop regs
// write into drop regs when they are not valid. If valid then we need to hold their values, until
// the req is sent out and not dropped

assign ipc_dropreg_wen[3:0] = ~ipc_dropreg_valid[3:0];

assign dropreg0_in[8:0] = ({9{ipc_unit_sel_l1[0]}} & op_req_l1[8:0]) |
                          ({9{~ipc_unit_sel_l1[0]}} & dropreg0[8:0]);

assign dropreg1_in[8:0] = ({9{ipc_unit_sel_l1[1]}} & op_req_l1[8:0]) |
                          ({9{~ipc_unit_sel_l1[1]}} & dropreg1[8:0]);

assign dropreg2_in[8:0] = ({9{ipc_unit_sel_l1[2]}} & op_req_l1[8:0]) |
                          ({9{~ipc_unit_sel_l1[2]}} & dropreg2[8:0]);

assign dropreg3_in[8:0] = ({9{ipc_unit_sel_l1[3]}} & op_req_l1[8:0]) |
                          ({9{~ipc_unit_sel_l1[3]}} & dropreg3[8:0]);

// generate the request to PCX. This get latched in PCX before being used.


//assign op_req_l1[8:0] = ({9{sel_repeat_drop_l1}} & req_pa[8:0]) |
//                     ({9{sel_repeat_ndrop_l1}} & req_l1[8:0]) |
//                     ({9{sel_nrepeat_drop_l1}} & req_nrepeat_drop_l1[8:0]) |
//                     ({9{sel_nrepeat_ndrop_l1}} & req_nrepeat_ndrop_l1[8:0]);

assign op_req_l1[8:0] = ({9{req_dropped_lat}} & ipc_req_repeat_drop_l1[8:0]) |
                     ({9{req_dropped_lat_}} & ipc_req_repeat_ndrop_l1[8:0]) |
                     (req_nrepeat_drop_l1[8:0]) |
                     (req_nrepeat_ndrop_l1[8:0]);

// for timing reasons, generate an early version of op_req_l1 in li stage, send to dp where it is latched and
// sent to ccx.
assign ipc_op_req_li[8:0] = ({9{req_dropped}} & req_repeat_drop_li[8:0]) |
                            ({9{req_dropped_}} & req_repeat_ndrop_li[8:0]) |
                            (req_nrepeat_drop_li[8:0]) |
                            (req_nrepeat_ndrop_li[8:0]);

assign atm_pq[8:0] = ipc_atm_l1[8:0] & {9{~(ipc_unit_sel_pa[2] & req_dropped_lat)}};

// for timing reasons, generate an early version of atm_pq in li stage, send to dp where it is latched and
// sent to ccx.

assign ipc_atm_req_li[8:0] = atm_req_li[8:0] & {9{~(ipc_unit_sel_l1[2] & req_dropped)}};


// on an atomic request, the second packet is sent out without req_pq.
// l15_pqm_ctl still needs to know about this request.
assign req_pq[8:0] = op_req_l1[8:0] | atm_pa[8:0];


// enable for sending data out in PA, for power saving
assign ipc_pq_valid = |(req_pq[8:0]);
assign ipc_pq_clken = ipc_pq_valid | ~gkt_pmen;


// determine requests being dropped in l1.

assign ifu_ndropped_l1 = ~(ipc_unit_sel_l1[0] & req_dropped);
assign mmu_ndropped_l1 = ~(ipc_unit_sel_l1[1] & req_dropped);
assign lsu_ndropped_l1 = ~(ipc_unit_sel_l1[2] & req_dropped);
assign spu_ndropped_l1 = ~(ipc_unit_sel_l1[3] & req_dropped);


// drive selects to ipd datapath

assign ipc_sel_ndrop_ifu_l1 = ipc_unit_sel_l1[0] & ~ipc_dropreg_valid[0];
assign ipc_sel_ndrop_mmu_l1 = ipc_unit_sel_l1[1] & ~ipc_dropreg_valid[1];
assign ipc_sel_ndrop_lsu_l1 = ipc_unit_sel_l1[2] & ~ipc_dropreg_valid[2];
assign ipc_sel_ndrop_spu_l1 = ipc_unit_sel_l1[3] & ~ipc_dropreg_valid[3];
assign ipc_sel_drop_ifu_l1 = ipc_unit_sel_l1[0] & ipc_dropreg_valid[0];
assign ipc_sel_drop_mmu_l1 = ipc_unit_sel_l1[1] & ipc_dropreg_valid[1];
assign ipc_sel_drop_lsu_l1 = ipc_unit_sel_l1[2] & ipc_dropreg_valid[2];
assign ipc_sel_drop_spu_l1 = ipc_unit_sel_l1[3] & ipc_dropreg_valid[3];

///////////////////////////////////////////////////////////////////////
// PA CYCLE
///////////////////////////////////////////////////////////////////////
// count number of dropped requests for each unit

// increment the counter on every dropped request,
// clear the counter when the requests succeeds  (not dropped),
// hold the counter when not incrementing or not clearing
assign ifu_dropped_pa = (ipc_unit_sel_pa[0] & req_dropped_lat);
assign mmu_dropped_pa = (ipc_unit_sel_pa[1] & req_dropped_lat);
assign lsu_dropped_pa = (ipc_unit_sel_pa[2] & req_dropped_lat);
assign spu_dropped_pa = (ipc_unit_sel_pa[3] & req_dropped_lat);

assign ifu_success_pa = (ipc_unit_sel_pa[0] & ~req_dropped_lat);
assign mmu_success_pa = (ipc_unit_sel_pa[1] & ~req_dropped_lat);
assign lsu_success_pa = (ipc_unit_sel_pa[2] & ~req_dropped_lat);
assign spu_success_pa = (ipc_unit_sel_pa[3] & ~req_dropped_lat);


assign inc_ifu = ifu_dropped_pa & ~max_count_reached;
assign clear_ifu = ifu_success_pa;
assign hold_ifu = ~inc_ifu & ~clear_ifu;


assign ifu_drop_cnt[2:0] = ({3{inc_ifu}} & (ifu_drop_cnt_lat[2:0] + 3'b001)) |
                           ({3{clear_ifu}} & 3'b000) |
                           ({3{hold_ifu}} & ifu_drop_cnt_lat[2:0]);

assign inc_mmu = mmu_dropped_pa & ~max_count_reached;
assign clear_mmu = mmu_success_pa;
assign hold_mmu = ~inc_mmu & ~clear_mmu;


assign mmu_drop_cnt[2:0] = ({3{inc_mmu}} & (mmu_drop_cnt_lat[2:0] + 3'b001)) |
                           ({3{clear_mmu}} & 3'b000) |
                           ({3{hold_mmu}} & mmu_drop_cnt_lat[2:0]);

assign inc_lsu = lsu_dropped_pa & ~max_count_reached;
assign clear_lsu = lsu_success_pa;
assign hold_lsu = ~inc_lsu & ~clear_lsu;


assign lsu_drop_cnt[2:0] = ({3{inc_lsu}} & (lsu_drop_cnt_lat[2:0] + 3'b001)) |
                           ({3{clear_lsu}} & 3'b000) |
                           ({3{hold_lsu}} & lsu_drop_cnt_lat[2:0]);

assign inc_spu = spu_dropped_pa & ~max_count_reached;
assign clear_spu = spu_success_pa;
assign hold_spu = ~inc_spu & ~clear_spu;


assign spu_drop_cnt[2:0] = ({3{inc_spu}} & (spu_drop_cnt_lat[2:0] + 3'b001)) |
                           ({3{clear_spu}} & 3'b000) |
                           ({3{hold_spu}} & spu_drop_cnt_lat[2:0]);


assign max_count_reached_in = (ifu_drop_cnt[2:0] == 3'b111) |
                              (mmu_drop_cnt[2:0] == 3'b111) |
                              (lsu_drop_cnt[2:0] == 3'b111) |
                              (spu_drop_cnt[2:0] == 3'b111);

                              
assign force_ifu_in = ifu_drop_cnt[2:0] == 3'b111;
assign force_mmu_in = mmu_drop_cnt[2:0] == 3'b111;
assign force_lsu_in = lsu_drop_cnt[2:0] == 3'b111;
assign force_spu_in = spu_drop_cnt[2:0] == 3'b111;

assign force_ifu_mmu_in = force_ifu_in | force_mmu_in;
assign force_lsu_spu_in = force_lsu_in | force_spu_in;


gkt_ipc_ctl_msff_ctl_macro__width_13 drop_cnt
  (
   .scan_in(drop_cnt_scanin),
   .scan_out(drop_cnt_scanout),
   .din     ({max_count_reached_in, ifu_drop_cnt[2:0],mmu_drop_cnt[2:0],lsu_drop_cnt[2:0],spu_drop_cnt[2:0]}),
   .dout    ({max_count_reached, ifu_drop_cnt_lat[2:0], mmu_drop_cnt_lat[2:0], lsu_drop_cnt_lat[2:0], spu_drop_cnt_lat[2:0]}),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_6 force_req
  (
   .scan_in(force_req_scanin),
   .scan_out(force_req_scanout),
   .din     ({force_ifu_in, force_mmu_in, force_lsu_in, force_spu_in, force_ifu_mmu_in, force_lsu_spu_in}),
   .dout    ({force_ifu, force_mmu, force_lsu, force_spu, force_ifu_mmu, force_lsu_spu}),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// At any time, only one unit can reach max drop count, and so only one unit can be forced.
// 0in bits_on -var {force_ifu, force_mmu, force_lsu, force_spu} -max 1 


///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// PERFORMANCE MONITOR COUNTER SIGNALS
// {8 - valid; 7:5 - tid; 4:0 - { mmu_pkt, dstore_pkt, ifetch_pkt, dload_pkt, sstore_pkt, sload_pkt}
/////////////////////////////////////////////////////////////////////
// decode the pcx packet
assign ifetch_pkt = ipd_optype[7];
assign dload_pkt = ~ipd_optype[7] & ~ipd_optype[6] & ~ipd_optype[5] & ~ipd_optype[4] & ~ipd_optype[3];
assign dstore_pkt = ~ipd_optype[7] & ~ipd_optype[6] & ~ipd_optype[5] & ~ipd_optype[4] & ipd_optype[3];
assign sload_pkt =  ~ipd_optype[7] & ~ipd_optype[6] & ipd_optype[5] & ~ipd_optype[4] & ~ipd_optype[3];
assign sstore_pkt =  ~ipd_optype[7] & ~ipd_optype[6] & ipd_optype[5] & ~ipd_optype[4] & ipd_optype[3];
assign mmu_pkt = ipd_optype[6] & ~ipd_optype[3];
assign ma_pkt = ipd_optype[8];


// encode the packet type into 3 bits

assign pcx_pkt[2:0] = ({3{dload_pkt}}  & 3'b000) |
                      ({3{dstore_pkt}} & 3'b001) |
                      ({3{sload_pkt & ~ma_pkt}}  & 3'b010) |
                      ({3{sstore_pkt & ~ma_pkt}} & 3'b011) |
                      ({3{mmu_pkt}}    & 3'b100) |
                      ({3{ifetch_pkt}} & 3'b101) |
                      ({3{sload_pkt & ma_pkt}}  & 3'b110) |
                      ({3{sstore_pkt & ma_pkt}} & 3'b111);


assign tid_pkt[2:0] = ipd_optype[2:0];
assign valid_pkt = (|req_pa[8:0]) & ~req_dropped_lat;
assign xbar_optype[6:0] = {valid_pkt, tid_pkt[2:0], pcx_pkt[2:0]};


gkt_ipc_ctl_msff_ctl_macro__width_7 dff_xbar_type
  (
   .scan_in(dff_xbar_type_scanin),
   .scan_out(dff_xbar_type_scanout),
   .din           (xbar_optype[6:0]),
   .dout             (l15_pmu_xbar_optype[6:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_4 dff_unit_sel_pa_type
  (
   .scan_in(dff_unit_sel_pa_type_scanin),
   .scan_out(dff_unit_sel_pa_type_scanout),
   .din           (ipc_unit_sel_l1[3:0]),
   .dout             (ipc_unit_sel_pa[3:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_4 dff_unit_ndrop_pa
  (
   .scan_in(dff_unit_ndrop_pa_scanin),
   .scan_out(dff_unit_ndrop_pa_scanout),
   .din           ({ifu_ndropped_l1, mmu_ndropped_l1, lsu_ndropped_l1, spu_ndropped_l1}),
   .dout          ({ifu_ndropped_pa, mmu_ndropped_pa, lsu_ndropped_pa, spu_ndropped_pa}),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


gkt_ipc_ctl_msff_ctl_macro__width_1 dff_req_drop_lat
  (
   .scan_in(dff_req_drop_lat_scanin),
   .scan_out(dff_req_drop_lat_scanout),
   .din           (req_dropped),
   .dout             (req_dropped_lat),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


gkt_ipc_ctl_msff_ctl_macro__width_1 dff_req_drop_latx
  (
   .scan_in(dff_req_drop_latx_scanin),
   .scan_out(dff_req_drop_latx_scanout),
   .din           (req_dropped_),
   .dout             (req_dropped_lat_),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_4 dff_dropreg_valid
  (
   .scan_in(dff_dropreg_valid_scanin),
   .scan_out(dff_dropreg_valid_scanout),
   .din           (ipc_dropreg_valid[3:0]),
   .dout             (ipc_dropreg_valid_pa[3:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_9 dff_dropreg0
  (
   .scan_in(dff_dropreg0_scanin),
   .scan_out(dff_dropreg0_scanout),
   .din           (dropreg0_in[8:0]),
   .dout             (dropreg0[8:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_9 dff_dropreg1
  (
   .scan_in(dff_dropreg1_scanin),
   .scan_out(dff_dropreg1_scanout),
   .din           (dropreg1_in[8:0]),
   .dout             (dropreg1[8:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
gkt_ipc_ctl_msff_ctl_macro__width_9 dff_dropreg2
  (
   .scan_in(dff_dropreg2_scanin),
   .scan_out(dff_dropreg2_scanout),
   .din           (dropreg2_in[8:0]),
   .dout             (dropreg2[8:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
gkt_ipc_ctl_msff_ctl_macro__width_9 dff_dropreg3
  (
   .scan_in(dff_dropreg3_scanin),
   .scan_out(dff_dropreg3_scanout),
   .din           (dropreg3_in[8:0]),
   .dout             (dropreg3[8:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_9 dff_req_pa
  (
   .scan_in(dff_req_pa_scanin),
   .scan_out(dff_req_pa_scanout),
   .din           (op_req_l1[8:0]),
   .dout             (req_pa[8:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

gkt_ipc_ctl_msff_ctl_macro__width_9 dff_atm_pa
  (
   .scan_in(dff_atm_pa_scanin),
   .scan_out(dff_atm_pa_scanout),
   .din           (atm_pq[8:0]),
   .dout             (atm_pa[8:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign pcx_grant_lb[8:0] = {9{~lbist_run}} & pcx_grant[8:0];


///*
//gkt_pqm_ctl AUTO_TEMPLATE
//  (
//   // Outputs
//   .scan_in(AUTO_TEMPLATE_scanin),
//   .scan_out(AUTO_TEMPLATE_scanout),
//   .pqm_req_drop (pqm_req_drop[@]),
//   .pqm_empty (pqm_empty[@]),
//   // Inputs
//   .spc_pcx_req_pq (req_pq[@]),
//   .pcx_grant (pcx_grant_lb[@]));
//*/

gkt_pqm_ctl pqm0 (/*AUTOINST*/ 
                  // Outputs
                  .pqm_req_drop         (pqm_req_drop[0]),       // Templated
                  .pqm_empty            (pqm_empty[0]),          // Templated
                  // Inputs
                  .scan_in(pqm0_scanin),
                  .scan_out(pqm0_scanout),
                  .l1clk                (l1clk),
                  .spc_pcx_req_pq       (req_pq[0]),             // Templated
                  .pcx_grant            (pcx_grant_lb[0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

gkt_pqm_ctl pqm1 (/*AUTOINST*/ 
                  // Outputs
                  .pqm_req_drop         (pqm_req_drop[1]),       // Templated
                  .pqm_empty            (pqm_empty[1]),          // Templated
                  // Inputs
                  .scan_in(pqm1_scanin),
                  .scan_out(pqm1_scanout),
                  .l1clk                (l1clk),
                  .spc_pcx_req_pq       (req_pq[1]),             // Templated
                  .pcx_grant            (pcx_grant_lb[1]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

gkt_pqm_ctl pqm2 (/*AUTOINST*/ 
                  // Outputs
                  .pqm_req_drop         (pqm_req_drop[2]),       // Templated
                  .pqm_empty            (pqm_empty[2]),          // Templated
                  // Inputs
                  .scan_in(pqm2_scanin),
                  .scan_out(pqm2_scanout),
                  .l1clk                (l1clk),
                  .spc_pcx_req_pq       (req_pq[2]),             // Templated
                  .pcx_grant            (pcx_grant_lb[2]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

gkt_pqm_ctl pqm3  (/*AUTOINST*/ 
                   // Outputs
                   .pqm_req_drop        (pqm_req_drop[3]),       // Templated
                   .pqm_empty           (pqm_empty[3]),          // Templated
                   // Inputs
                   .scan_in(pqm3_scanin),
                   .scan_out(pqm3_scanout),
                   .l1clk               (l1clk),
                   .spc_pcx_req_pq      (req_pq[3]),             // Templated
                   .pcx_grant           (pcx_grant_lb[3]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

gkt_pqm_ctl pqm4 (/*AUTOINST*/ 
                  // Outputs
                  .pqm_req_drop         (pqm_req_drop[4]),       // Templated
                  .pqm_empty            (pqm_empty[4]),          // Templated
                  // Inputs
                  .scan_in(pqm4_scanin),
                  .scan_out(pqm4_scanout),
                  .l1clk                (l1clk),
                  .spc_pcx_req_pq       (req_pq[4]),             // Templated
                  .pcx_grant            (pcx_grant_lb[4]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

gkt_pqm_ctl pqm5 (/*AUTOINST*/ 
                  // Outputs
                  .pqm_req_drop         (pqm_req_drop[5]),       // Templated
                  .pqm_empty            (pqm_empty[5]),          // Templated
                  // Inputs
                  .scan_in(pqm5_scanin),
                  .scan_out(pqm5_scanout),
                  .l1clk                (l1clk),
                  .spc_pcx_req_pq       (req_pq[5]),             // Templated
                  .pcx_grant            (pcx_grant_lb[5]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

gkt_pqm_ctl pqm6 (/*AUTOINST*/ 
                  // Outputs
                  .pqm_req_drop         (pqm_req_drop[6]),       // Templated
                  .pqm_empty            (pqm_empty[6]),          // Templated
                  // Inputs
                  .scan_in(pqm6_scanin),
                  .scan_out(pqm6_scanout),
                  .l1clk                (l1clk),
                  .spc_pcx_req_pq       (req_pq[6]),             // Templated
                  .pcx_grant            (pcx_grant_lb[6]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

gkt_pqm_ctl pqm7 (/*AUTOINST*/ 
                  // Outputs
                  .pqm_req_drop         (pqm_req_drop[7]),       // Templated
                  .pqm_empty            (pqm_empty[7]),          // Templated
                  // Inputs
                  .scan_in(pqm7_scanin),
                  .scan_out(pqm7_scanout),
                  .l1clk                (l1clk),
                  .spc_pcx_req_pq       (req_pq[7]),             // Templated
                  .pcx_grant            (pcx_grant_lb[7]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

gkt_pqm_ctl pqm8 (/*AUTOINST*/ 
                  // Outputs
                  .pqm_req_drop         (pqm_req_drop[8]),       // Templated
                  .pqm_empty            (pqm_empty[8]),          // Templated
                  // Inputs
                  .scan_in(pqm8_scanin),
                  .scan_out(pqm8_scanout),
                  .l1clk                (l1clk),
                  .spc_pcx_req_pq       (req_pq[8]),             // Templated
                  .pcx_grant            (pcx_grant_lb[8]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated


////////////////////////////////////////////////////////
// SPARE CELLS
////////////////////////////////////////////////////////
gkt_ipc_ctl_spare_ctl_macro__num_5 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
////////////////////////////////////////////////////////

// fixscan start:
assign pmen_reg_scanin           = scan_in                  ;
assign dff_ncu_pb_scanin         = pmen_reg_scanout         ;
assign dff_pb_sel_scanin         = dff_ncu_pb_scanout       ;
assign dff_ifu_req_v0_scanin     = dff_pb_sel_scanout       ;
assign dff_ifu_req_v1_scanin     = dff_ifu_req_v0_scanout   ;
assign dff_ifu_v0_scanin         = dff_ifu_req_v1_scanout   ;
assign dff_ifu_v1_scanin         = dff_ifu_v0_scanout       ;
assign dff_mmu_req_v0_scanin     = dff_ifu_v1_scanout       ;
assign dff_mmu_req_v1_scanin     = dff_mmu_req_v0_scanout   ;
assign dff_mmu_v0_scanin         = dff_mmu_req_v1_scanout   ;
assign dff_mmu_v1_scanin         = dff_mmu_v0_scanout       ;
assign dff_lsu_req_v0_scanin     = dff_mmu_v1_scanout       ;
assign dff_lsu_req_v1_scanin     = dff_lsu_req_v0_scanout   ;
assign dff_lsu_v0_scanin         = dff_lsu_req_v1_scanout   ;
assign dff_lsu_v1_scanin         = dff_lsu_v0_scanout       ;
assign dff_lsu_lock_v0_scanin    = dff_lsu_v1_scanout       ;
assign dff_lsu_lock_v1_scanin    = dff_lsu_lock_v0_scanout  ;
assign dff_spu_req_v0_scanin     = dff_lsu_lock_v1_scanout  ;
assign dff_spu_req_v1_scanin     = dff_spu_req_v0_scanout   ;
assign dff_spu_v0_scanin         = dff_spu_req_v1_scanout   ;
assign dff_spu_v1_scanin         = dff_spu_v0_scanout       ;
assign lock_reg_scanin           = dff_spu_v1_scanout       ;
assign favori_reg_scanin         = lock_reg_scanout         ;
assign favorim_reg_scanin        = favori_reg_scanout       ;
assign favorls_reg_scanin        = favorim_reg_scanout      ;
assign sel_reg_scanin            = favorls_reg_scanout      ;
assign grant_reg_scanin          = sel_reg_scanout          ;
assign l1_atm_req_reg_scanin     = grant_reg_scanout        ;
assign req_nrepeat_drop_reg_scanin = l1_atm_req_reg_scanout   ;
assign req_nrepeat_ndrop_reg_scanin = req_nrepeat_drop_reg_scanout;
assign req_repeat_drop_reg_scanin = req_nrepeat_ndrop_reg_scanout;
assign req_repeat_ndrop_reg_scanin = req_repeat_drop_reg_scanout;
assign drop_cnt_scanin             = req_repeat_ndrop_reg_scanout;
assign force_req_scanin            = drop_cnt_scanout;
assign dff_xbar_type_scanin      = force_req_scanout;
assign dff_unit_sel_pa_type_scanin = dff_xbar_type_scanout    ;
assign dff_unit_ndrop_pa_scanin = dff_unit_sel_pa_type_scanout;
assign dff_req_drop_lat_scanin   = dff_unit_ndrop_pa_scanout;
assign dff_req_drop_latx_scanin  = dff_req_drop_lat_scanout ;
assign dff_dropreg_valid_scanin  = dff_req_drop_latx_scanout;
assign dff_dropreg0_scanin       = dff_dropreg_valid_scanout;
assign dff_dropreg1_scanin       = dff_dropreg0_scanout     ;
assign dff_dropreg2_scanin       = dff_dropreg1_scanout     ;
assign dff_dropreg3_scanin       = dff_dropreg2_scanout     ;
assign dff_req_pa_scanin         = dff_dropreg3_scanout     ;
assign dff_atm_pa_scanin         = dff_req_pa_scanout       ;
assign pqm0_scanin               = dff_atm_pa_scanout       ;
assign pqm1_scanin               = pqm0_scanout             ;
assign pqm2_scanin               = pqm1_scanout             ;
assign pqm3_scanin               = pqm2_scanout             ;
assign pqm4_scanin               = pqm3_scanout             ;
assign pqm5_scanin               = pqm4_scanout             ;
assign pqm6_scanin               = pqm5_scanout             ;
assign pqm7_scanin               = pqm6_scanout             ;
assign pqm8_scanin               = pqm7_scanout             ;

assign spares_scanin             = pqm8_scanout             ;
assign scan_out                  = spares_scanout           ;


// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_msff_ctl_macro__width_13 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [12:0] fdin;
wire [11:0] so;

  input [12:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [12:0] dout;
  output scan_out;
assign fdin[12:0] = din[12:0];


dff #(13)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[12:0]),
.si({scan_in,so[11:0]}),
.so({so[11:0],scan_out}),
.q(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipc_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module gkt_ipc_ctl_spare_ctl_macro__num_5 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));
assign scan_out = so_4;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: gkt_ipd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  gkt_ipd_dp (
  tcu_scan_en, 
  tcu_se_scancollar_out, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  core_isolate, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  slow_cmp_sync_en, 
  const_cpuid, 
  ncu_spc_pm, 
  ncu_spc_ba01, 
  ncu_spc_ba23, 
  ncu_spc_ba45, 
  ncu_spc_ba67, 
  ncu_pm_ff, 
  ncu_ba01_ff, 
  ncu_ba23_ff, 
  ncu_ba45_ff, 
  ncu_ba67_ff, 
  spc_pcx_data_pa, 
  spc_pcx_req_pq, 
  spc_pcx_atm_pq, 
  l15_spc_data1, 
  cpx_spc_data_cx_rep0, 
  l15_spc_cpkt, 
  l15_mmu_valid, 
  l15_spu_valid, 
  ipd_optype, 
  pcx_spc_grant_px_buf, 
  cpx_spc_data_cx, 
  pcx_spc_grant_px, 
  ifu_l15_addr, 
  mmu_l15_addr, 
  lsu_l15_addr, 
  spu_l15_addr, 
  ifu_l15_valid, 
  mmu_l15_valid, 
  spu_l15_valid, 
  ifu_l15_cpkt, 
  mmu_l15_cpkt, 
  lsu_l15_cpkt, 
  spu_l15_cpkt, 
  lsu_l15_data, 
  spu_l15_data, 
  ipc_v0_ifu_new, 
  ipc_v0_ifu_shft, 
  ipc_v0_ifu_hold, 
  ipc_v1_ifu_new, 
  ipc_v1_ifu_hold, 
  ipc_v0_mmu_new, 
  ipc_v0_mmu_shft, 
  ipc_v0_mmu_hold, 
  ipc_v1_mmu_new, 
  ipc_v1_mmu_hold, 
  ipc_v0_lsu_new, 
  ipc_v0_lsu_shft, 
  ipc_v0_lsu_hold, 
  ipc_v1_lsu_new, 
  ipc_v1_lsu_hold, 
  ipc_v0_spu_new, 
  ipc_v0_spu_shft, 
  ipc_v0_spu_hold, 
  ipc_v1_spu_new, 
  ipc_v1_spu_hold, 
  ipc_sel_ndrop_ifu_l1, 
  ipc_sel_ndrop_mmu_l1, 
  ipc_sel_ndrop_lsu_l1, 
  ipc_sel_ndrop_spu_l1, 
  ipc_sel_drop_ifu_l1, 
  ipc_sel_drop_mmu_l1, 
  ipc_sel_drop_lsu_l1, 
  ipc_sel_drop_spu_l1, 
  ipc_pq_clken, 
  ipc_dropreg_wen, 
  ipc_op_req_li, 
  ipc_atm_req_li, 
  ncu_spc_l2_idx_hash_en);
wire stop;
wire cpuid_reg_scanin;
wire cpuid_reg_scanout;
wire [2:0] cpuid;
wire ncu_spc_l2_idx_hash_en_buf;
wire ncu_spc_pm_buf;
wire ncu_spc_ba01_buf;
wire ncu_spc_ba23_buf;
wire ncu_spc_ba45_buf;
wire ncu_spc_ba67_buf;
wire i_ncu_reg_scanin;
wire i_ncu_reg_scanout;
wire slow_cmp_sync_en_ff;
wire idx_hash_en_ff;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [39:0] mmu_l15_addr1;
wire [25:0] lsu_l15_cpkt1;
wire [25:0] spu_l15_cpkt1;
wire [39:0] spu_l15_addr1;
wire [25:0] mmu_l15_cpkt1;
wire [25:0] ifu_l15_cpkt1;
wire i_cpx_data1lo_reg_scanin;
wire i_cpx_data1lo_reg_scanout;
wire [145:0] l15_spc_data;
wire i_cpx_data1hi_reg_scanin;
wire i_cpx_data1hi_reg_scanout;
wire i_cpx_cpkt_reg_scanin;
wire i_cpx_cpkt_reg_scanout;
wire [18:0] cpx_cpkt;
wire i_req_li_reg_scanin;
wire i_req_li_reg_scanout;
wire [8:0] op_req;
wire [8:0] atm_req;
wire core_isolate_;
wire [8:0] pcx_req_pq_;
wire [8:0] pcx_atm_pq_;
wire i_ifu_addr_v1_muxreg_scanin;
wire i_ifu_addr_v1_muxreg_scanout;
wire [25:0] v1_ifu_cpkt;
wire [39:0] v1_ifu_addr;
wire i_ifu_addr_v0_muxreg_scanin;
wire i_ifu_addr_v0_muxreg_scanout;
wire [25:0] v0_ifu_cpkt;
wire [39:0] v0_ifu_addr;
wire i_mmu_addr_v1_muxreg_scanin;
wire i_mmu_addr_v1_muxreg_scanout;
wire [25:0] v1_mmu_cpkt;
wire [39:0] v1_mmu_addr;
wire i_mmu_addr_v0_muxreg_scanin;
wire i_mmu_addr_v0_muxreg_scanout;
wire [25:0] v0_mmu_cpkt;
wire [39:0] v0_mmu_addr;
wire i_lsu_addr_v1_muxreg_scanin;
wire i_lsu_addr_v1_muxreg_scanout;
wire [25:0] v1_lsu_cpkt;
wire [39:0] v1_lsu_addr;
wire i_lsu_addr_v0_muxreg_scanin;
wire i_lsu_addr_v0_muxreg_scanout;
wire [25:0] v0_lsu_cpkt;
wire [39:0] v0_lsu_addr;
wire i_lsu_data_v1_muxreg_scanin;
wire i_lsu_data_v1_muxreg_scanout;
wire [63:0] v1_lsu_data;
wire i_lsu_data_v0_muxreg_scanin;
wire i_lsu_data_v0_muxreg_scanout;
wire [63:0] v0_lsu_data;
wire i_spu_addr_v1_muxreg_scanin;
wire i_spu_addr_v1_muxreg_scanout;
wire [25:0] v1_spu_cpkt;
wire [39:0] v1_spu_addr;
wire i_spu_addr_v0_muxreg_scanin;
wire i_spu_addr_v0_muxreg_scanout;
wire [25:0] v0_spu_cpkt;
wire [39:0] v0_spu_addr;
wire i_spu_data_v1_muxreg_scanin;
wire i_spu_data_v1_muxreg_scanout;
wire [63:0] v1_spu_data;
wire i_spu_data_v0_muxreg_scanin;
wire i_spu_data_v0_muxreg_scanout;
wire [63:0] v0_spu_data;
wire i_ifu_addr_drop_reg_scanin;
wire i_ifu_addr_drop_reg_scanout;
wire [25:0] ipd_cpkt_l1;
wire [39:0] ipd_addr_l1;
wire [25:0] drop_ifu_cpkt;
wire [39:0] drop_ifu_addr;
wire i_mmu_addr_drop_reg_scanin;
wire i_mmu_addr_drop_reg_scanout;
wire [25:0] drop_mmu_cpkt;
wire [39:0] drop_mmu_addr;
wire i_lsu_addr_drop_reg_scanin;
wire i_lsu_addr_drop_reg_scanout;
wire [25:0] drop_lsu_cpkt;
wire [39:0] drop_lsu_addr;
wire i_spu_addr_drop_reg_scanin;
wire i_spu_addr_drop_reg_scanout;
wire [25:0] drop_spu_cpkt;
wire [39:0] drop_spu_addr;
wire i_lsu_data_drop_reg_scanin;
wire i_lsu_data_drop_reg_scanout;
wire [63:0] ipd_data_l1;
wire [63:0] drop_lsu_data;
wire i_spu_data_drop_reg_scanin;
wire i_spu_data_drop_reg_scanout;
wire [63:0] drop_spu_data;
wire [39:0] ipd_addr_l1_prebuf;
wire i_hash_en_ff2_scanin;
wire i_hash_en_ff2_scanout;
wire idx_hash_en_ff2;
wire idx_hash_en_;
wire enable_hash;
wire [17:11] ipd_addr_hashed_l1;
wire [17:11] ipd_addr_out_l1;
wire i_pcx_addr_pa_reg_scanin;
wire i_pcx_addr_pa_reg_scanout;
wire [25:0] pcx_cpkt_pa;
wire [39:0] pcx_addr_pa;
wire i_pcx_data_pa_reg_scanin;
wire i_pcx_data_pa_reg_scanout;
wire [63:0] pcx_data_pa;


// globals
input tcu_scan_en ;
input		tcu_se_scancollar_out;
input           l2clk;
input           scan_in;
input           tcu_pce_ov;             // scan signals
input           core_isolate;
input           spc_aclk;
input           spc_bclk;
output          scan_out;

input           slow_cmp_sync_en;

input [2:0]     const_cpuid;

input           ncu_spc_pm;
input           ncu_spc_ba01;
input           ncu_spc_ba23;
input           ncu_spc_ba45;
input           ncu_spc_ba67;

output           ncu_pm_ff;
output           ncu_ba01_ff;
output           ncu_ba23_ff;
output           ncu_ba45_ff;
output           ncu_ba67_ff;

output [129:0]  spc_pcx_data_pa;
output [8:0]    spc_pcx_req_pq;
output [8:0]    spc_pcx_atm_pq;


output [127:0]  l15_spc_data1;
output [145:0]  cpx_spc_data_cx_rep0;

output [17:0]   l15_spc_cpkt;
output          l15_mmu_valid;
output          l15_spu_valid;

output [8:0]    ipd_optype;
output [8:0]    pcx_spc_grant_px_buf;


input [145:0]   cpx_spc_data_cx;
input [8:0]     pcx_spc_grant_px;


input [39:0]   ifu_l15_addr;
input [39:4]   mmu_l15_addr;
input [39:0]   lsu_l15_addr;
input [38:3]   spu_l15_addr;

input          ifu_l15_valid;
input          mmu_l15_valid;
input          spu_l15_valid;


input [7:0]   ifu_l15_cpkt;
input [4:0]    mmu_l15_cpkt;
input [25:0]   lsu_l15_cpkt;
input [12:0]   spu_l15_cpkt;


input [63:0]   lsu_l15_data;
input [63:0]   spu_l15_data;


input          ipc_v0_ifu_new;
input          ipc_v0_ifu_shft;
input          ipc_v0_ifu_hold;

input          ipc_v1_ifu_new;
input          ipc_v1_ifu_hold;

input          ipc_v0_mmu_new;
input          ipc_v0_mmu_shft;
input          ipc_v0_mmu_hold;

input          ipc_v1_mmu_new;
input          ipc_v1_mmu_hold;

input          ipc_v0_lsu_new;
input          ipc_v0_lsu_shft;
input          ipc_v0_lsu_hold;

input          ipc_v1_lsu_new;
input          ipc_v1_lsu_hold;


input          ipc_v0_spu_new;
input          ipc_v0_spu_shft;
input          ipc_v0_spu_hold;

input          ipc_v1_spu_new;
input          ipc_v1_spu_hold;


input          ipc_sel_ndrop_ifu_l1;
input          ipc_sel_ndrop_mmu_l1;
input          ipc_sel_ndrop_lsu_l1;
input          ipc_sel_ndrop_spu_l1;

input          ipc_sel_drop_ifu_l1;
input          ipc_sel_drop_mmu_l1;
input          ipc_sel_drop_lsu_l1;
input          ipc_sel_drop_spu_l1;

input          ipc_pq_clken;


input [3:0]    ipc_dropreg_wen;


input [8:0]    ipc_op_req_li;
input [8:0]    ipc_atm_req_li;


input          ncu_spc_l2_idx_hash_en;


// scan renames
assign stop = 1'b0;
// end scan

// flop cpuid

gkt_ipd_dp_msff_macro__stack_66c__width_3 cpuid_reg   
(
 .scan_in(cpuid_reg_scanin),
 .scan_out(cpuid_reg_scanout),
 .clk( l2clk ),
 .en  (1'b1),
 .din  ({const_cpuid[2:0]}),
 .dout (cpuid[2:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
 );

// ISOLATION BUFFER for grant signals
gkt_ipd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_9 isolate_grant_buf 
(
 .din({pcx_spc_grant_px[8:0]}),
 .dout({pcx_spc_grant_px_buf[8:0]})
 );

//flop ncu signals
// They are launched in iol2clk domain, and captured in cmp domain using sync enable
// Also since these are primary inputs to sparc core, se port is connected to scancollar_out.
// This stops the flops from capturing state during logic bist.

// ISOLATION BUFFER
gkt_ipd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_6 isolate_ncu_buf 
(
 .din({ncu_spc_l2_idx_hash_en,ncu_spc_pm,ncu_spc_ba01,ncu_spc_ba23,ncu_spc_ba45,ncu_spc_ba67}),
 .dout({ncu_spc_l2_idx_hash_en_buf,ncu_spc_pm_buf,ncu_spc_ba01_buf,ncu_spc_ba23_buf,ncu_spc_ba45_buf,ncu_spc_ba67_buf})

 );

gkt_ipd_dp_msff_macro__stack_64c__width_6 i_ncu_reg  
(
 .scan_in(i_ncu_reg_scanin),
 .scan_out(i_ncu_reg_scanout),
 .se(tcu_se_scancollar_out),
 .clk (l2clk),
 .en  (slow_cmp_sync_en_ff),
 .din({ncu_spc_l2_idx_hash_en_buf,ncu_spc_pm_buf,ncu_spc_ba01_buf,ncu_spc_ba23_buf,ncu_spc_ba45_buf,ncu_spc_ba67_buf}),
 .dout({idx_hash_en_ff, ncu_pm_ff, ncu_ba01_ff, ncu_ba23_ff, ncu_ba45_ff, ncu_ba67_ff}),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0   (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);


assign mmu_l15_addr1[39:0] = {mmu_l15_addr[39:4],4'b0};


// form the cpkts
assign lsu_l15_cpkt1[25:0] = lsu_l15_cpkt[25:0];


// actual spu pkt format:
//assign spu_l15_cpkt[25] = spu_l15_valid;
//assign spu_l15_cpkt[24:21] = 4'b0010;                    //rqtyp
// assign spu_l15_cpkt[20] = req_type
//assign spu_l15_cpkt[19] = 1'b1;                           //nc
//assign spu_l15_cpkt[18:16] = cpuid[2:0];                  //cpuid
//assign spu_l15_cpkt[15:13] = tid 
//assign spu_l15_cpkt[12:11] = 2'b00;                      //inv,pf,bis
//assign spu_l15_cpkt[10] = maid
//assign spu_l15_cpkt[9:8] =  2'b00
//assign spu_l15_cpkt[7:0] = byte valids                          //size

assign spu_l15_cpkt1[25:0] = {spu_l15_valid, 4'b0010, spu_l15_cpkt[4], 1'b1, cpuid[2:0], spu_l15_cpkt[2:0], 2'b0, spu_l15_cpkt[3], 2'b0, spu_l15_cpkt[12:5]};

assign spu_l15_addr1[39:0] = {1'b0, spu_l15_addr[38:3], 3'b000};

// actual mmu pkt format:
//assign mmu_l15_cpkt[25] = mmu_l15_valid;
//assign mmu_l15_cpkt[24:20] = 5'b01000;                    //rqtyp
//assign mmu_l15_cpkt[19] = 1'b1;                           //nc
//assign mmu_l15_cpkt[18:16] = cpuid[2:0];                  //cpuid
//assign mmu_l15_cpkt[15:13] = tid 
//assign mmu_l15_cpkt[12:10] = 3'b000;                      //inv,pf,bis
//assign mmu_l15_cpkt[9:7] =  mmuid
//assign mmu_l15_cpkt[7:0] = 8'b0;                          //size

assign mmu_l15_cpkt1[25:0] = {mmu_l15_valid,5'b01000,1'b1,cpuid[2:0],mmu_l15_cpkt[2:0],3'b0,mmu_l15_cpkt[4:3],8'b0};

// Actual ifu_l15_cpkt has following fields
// ifu_l15_cpkt[25]   = ifu_l15_valid
// ifu_l15_cpkt[24:20] = ifu_l15_req_type[4:0] = 5'b10000
// ifu_l15_cpkt[19]   = ifu_l15_nc
// ifu_l15_cpkt[18:16] = ifu_l15_cpuid[2:0]
// ifu_l15_cpkt[15:13] = ifu_l15_tid[2:0]
// ifu_l15_cpkt[12]    = ifu_l15_inv
// ifu_l15_cpkt[11]    = ifu_l15_pf = 0
// ifu_l15_cpkt[10:8] = ifu_l15_rway[2:0]
// ifu_l15_cpkt[7:0] = ifu_l15_size[7:0] = 0

assign ifu_l15_cpkt1[25:0] = {ifu_l15_valid,5'b10000,ifu_l15_cpkt[7],cpuid[2:0],
                              ifu_l15_cpkt[2:0],ifu_l15_cpkt[6],1'b0,ifu_l15_cpkt[5:3],8'b0};


///////////////////////////////////////////////////////////////////
// PIPE the CPX data and cpkt to SPARC core
// Also since these are primary inputs to sparc core, se port is connected to scancollar_out.
// This stops the flops from capturing state during logic bist.
///////////////////////////////////////////////////////////////////
// ISOLATION BUFFER 
gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 gkt_lsu_datalo_rep0  (
.din (cpx_spc_data_cx[63:0]),
  .dout(cpx_spc_data_cx_rep0[63:0])
  );

gkt_ipd_dp_msff_macro__stack_64c__width_64 i_cpx_data1lo_reg  
(
 .scan_in(i_cpx_data1lo_reg_scanin),
 .scan_out(i_cpx_data1lo_reg_scanout),
 .se(tcu_se_scancollar_out),
 .clk (l2clk),
 .en  (1'b1),
 .din(cpx_spc_data_cx_rep0[63:0]),          
 .dout(l15_spc_data[63:0]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 i_buf_data1lo_spc    (
	.din	(l15_spc_data[63:0]),
	.dout	(l15_spc_data1[63:0])
);

//ISOLATION BUFFER 
gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 gkt_lsu_datahi_rep0  (
  .din (cpx_spc_data_cx[127:64]),
  .dout(cpx_spc_data_cx_rep0[127:64])
  );

gkt_ipd_dp_msff_macro__stack_64c__width_64 i_cpx_data1hi_reg  
(
 .scan_in(i_cpx_data1hi_reg_scanin),
 .scan_out(i_cpx_data1hi_reg_scanout),
 .se(tcu_se_scancollar_out),
 .clk (l2clk),
 .en  (1'b1),
 .din(cpx_spc_data_cx_rep0[127:64]),          
 .dout(l15_spc_data[127:64]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 i_buf_data1hi_spc    (
	.din	(l15_spc_data[127:64]),
	.dout	(l15_spc_data1[127:64])
);

//ISOLATION BUFFER 
gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_none__width_18 gkt_lsu_cpkt_rep0  (
  .din (cpx_spc_data_cx[145:128]),
  .dout(cpx_spc_data_cx_rep0[145:128])
);

gkt_ipd_dp_msff_macro__stack_64c__width_18 i_cpx_cpkt_reg  
(
 .scan_in(i_cpx_cpkt_reg_scanin),
 .scan_out(i_cpx_cpkt_reg_scanout),
 .se(tcu_se_scancollar_out),
 .clk (l2clk),
 .en  (1'b1),
 .din({cpx_spc_data_cx_rep0[145:128]}),
 .dout({l15_spc_data[145:128]}),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign cpx_cpkt[18:0] = {l15_spc_data[145:140],1'b0,l15_spc_data[139:128]};

gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_20 i_buf_cpkt_spc    (
	.din	({cpx_cpkt[18],cpx_cpkt[18:0]}),
	.dout	({l15_spu_valid,l15_mmu_valid,l15_spc_cpkt[17:0]})
);

///////////////////////////////////////////////////////////////////
// Generate request and atomic signals going to PCX
///////////////////////////////////////////////////////////////////
//assign op_req[8:0] = ({9{req_dropped_lat}} & req_repeat_drop_l1[8:0]) |
//                     ({9{req_dropped_lat_}} & req_repeat_ndrop_l1[8:0]) |
//                     (req_nrepeat_drop_l1[8:0]) |
//                     (req_nrepeat_ndrop_l1[8:0]);
//assign spc_pcx_req_pq[8:0] = op_req[8:0] & {9{~core_isolate}};

// flop op_req_li and atm_req_li


gkt_ipd_dp_msff_macro__dmsff_8x__stack_64c__width_19 i_req_li_reg  
(
 .scan_in(i_req_li_reg_scanin),
 .scan_out(i_req_li_reg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din({slow_cmp_sync_en,ipc_op_req_li[8:0],ipc_atm_req_li[8:0]}),
 .dout({slow_cmp_sync_en_ff, op_req[8:0], atm_req[8:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


gkt_ipd_dp_inv_macro__dinv_8x__stack_64c__width_1 i_clk_stop_inv    (
.din (core_isolate),
.dout (core_isolate_)
);
                                               
gkt_ipd_dp_nand_macro__dnand_16x__ports_2__stack_64c__width_9 i_pcx_req_nand_w9    
(
 .din0(op_req[8:0]),
 .din1({9{core_isolate_}}),
 .dout(pcx_req_pq_[8:0])
 );

gkt_ipd_dp_inv_macro__dinv_48x__stack_64c__width_9 i_pcx_req_inv_w9   
(
 .din({pcx_req_pq_[8:0]}),
 .dout({spc_pcx_req_pq[8:0]})
 );


//assign atm_req[8:0] = {9{~ipc_dropreg_valid[2]}} & ipc_atm_l1[8:0];
//assign spc_pcx_atm_pq[8:0] = atm_req[8:0] & {9{~core_isolate}};

gkt_ipd_dp_nand_macro__dnand_16x__ports_2__stack_64c__width_9 i_atm_nand     (
.din0 (atm_req[8:0]),
.din1 ({9{core_isolate_}}),
.dout (pcx_atm_pq_[8:0])
);
                                                            
gkt_ipd_dp_inv_macro__dinv_48x__stack_64c__width_9 i_pcx_atm_inv_w9   
(
 .din({pcx_atm_pq_[8:0]}),
 .dout({spc_pcx_atm_pq[8:0]})
 );


// assertion, atomic request cannot be asserted without valid request
/* 0in assert -var (~(|(spc_pcx_atm_pq[8:0] & ~(spc_pcx_req_pq[8:0]))))
 -message "l15_ipc_ctl: spc_pcx_atm_pq asserted without spc_pcx_req_pq" */


///////////////////////////////////////////////////////////////////
// Latch ifu pkt in 2-entry FIFO
///////////////////////////////////////////////////////////////////
gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 i_ifu_addr_v1_muxreg  
(
 .scan_in(i_ifu_addr_v1_muxreg_scanin),
 .scan_out(i_ifu_addr_v1_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0({ifu_l15_cpkt1[25:0],ifu_l15_addr[39:0]}),          
 .din1({v1_ifu_cpkt[25:0],v1_ifu_addr[39:0]}),                     
 .sel0(ipc_v1_ifu_new),
 .sel1(ipc_v1_ifu_hold),
 .dout({v1_ifu_cpkt[25:0],v1_ifu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 i_ifu_addr_v0_muxreg  
(
 .scan_in(i_ifu_addr_v0_muxreg_scanin),
 .scan_out(i_ifu_addr_v0_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0({ifu_l15_cpkt1[25:0],ifu_l15_addr[39:0]}),          
 .din1({v1_ifu_cpkt[25:0],v1_ifu_addr[39:0]}),                     
 .din2({v0_ifu_cpkt[25:0],v0_ifu_addr[39:0]}),                     
 .sel0(ipc_v0_ifu_new),
 .sel1(ipc_v0_ifu_shft),
 .sel2(ipc_v0_ifu_hold),
 .dout({v0_ifu_cpkt[25:0],v0_ifu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


///////////////////////////////////////////////////////////////////
// Latch mmu pkt in 2-entry FIFO
///////////////////////////////////////////////////////////////////
gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 i_mmu_addr_v1_muxreg  
(
 .scan_in(i_mmu_addr_v1_muxreg_scanin),
 .scan_out(i_mmu_addr_v1_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0({mmu_l15_cpkt1[25:0],mmu_l15_addr1[39:0]}),          
 .din1({v1_mmu_cpkt[25:0],v1_mmu_addr[39:0]}),                     
 .sel0(ipc_v1_mmu_new),
 .sel1(ipc_v1_mmu_hold),
 .dout({v1_mmu_cpkt[25:0],v1_mmu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 i_mmu_addr_v0_muxreg  
(
 .scan_in(i_mmu_addr_v0_muxreg_scanin),
 .scan_out(i_mmu_addr_v0_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0({mmu_l15_cpkt1[25:0],mmu_l15_addr1[39:0]}),          
 .din1({v1_mmu_cpkt[25:0],v1_mmu_addr[39:0]}),                     
 .din2({v0_mmu_cpkt[25:0],v0_mmu_addr[39:0]}),                     
 .sel0(ipc_v0_mmu_new),
 .sel1(ipc_v0_mmu_shft),
 .sel2(ipc_v0_mmu_hold),
 .dout({v0_mmu_cpkt[25:0],v0_mmu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

///////////////////////////////////////////////////////////////////
// Latch lsu pkt in 2-entry FIFO
///////////////////////////////////////////////////////////////////
gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 i_lsu_addr_v1_muxreg  
(
 .scan_in(i_lsu_addr_v1_muxreg_scanin),
 .scan_out(i_lsu_addr_v1_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0({lsu_l15_cpkt1[25:0],lsu_l15_addr[39:0]}),          
 .din1({v1_lsu_cpkt[25:0],v1_lsu_addr[39:0]}),                     
 .sel0(ipc_v1_lsu_new),
 .sel1(ipc_v1_lsu_hold),
 .dout({v1_lsu_cpkt[25:0],v1_lsu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 i_lsu_addr_v0_muxreg  
(
 .scan_in(i_lsu_addr_v0_muxreg_scanin),
 .scan_out(i_lsu_addr_v0_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0({lsu_l15_cpkt1[25:0],lsu_l15_addr[39:0]}),          
 .din1({v1_lsu_cpkt[25:0],v1_lsu_addr[39:0]}),                     
 .din2({v0_lsu_cpkt[25:0],v0_lsu_addr[39:0]}),                     
 .sel0(ipc_v0_lsu_new),
 .sel1(ipc_v0_lsu_shft),
 .sel2(ipc_v0_lsu_hold),
 .dout({v0_lsu_cpkt[25:0],v0_lsu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_64c__width_64 i_lsu_data_v1_muxreg  
(
 .scan_in(i_lsu_data_v1_muxreg_scanin),
 .scan_out(i_lsu_data_v1_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0(lsu_l15_data[63:0]),          
 .din1(v1_lsu_data[63:0]),                     
 .sel0(ipc_v1_lsu_new),
 .sel1(ipc_v1_lsu_hold),
 .dout(v1_lsu_data[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_64c__width_64 i_lsu_data_v0_muxreg  
(
 .scan_in(i_lsu_data_v0_muxreg_scanin),
 .scan_out(i_lsu_data_v0_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0(lsu_l15_data[63:0]),          
 .din1(v1_lsu_data[63:0]),                     
 .din2(v0_lsu_data[63:0]),                     
 .sel0(ipc_v0_lsu_new),
 .sel1(ipc_v0_lsu_shft),
 .sel2(ipc_v0_lsu_hold),
 .dout(v0_lsu_data[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

///////////////////////////////////////////////////////////////////
// Latch spu pkt in 2-entry FIFO
///////////////////////////////////////////////////////////////////
gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 i_spu_addr_v1_muxreg  
(
 .scan_in(i_spu_addr_v1_muxreg_scanin),
 .scan_out(i_spu_addr_v1_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0({spu_l15_cpkt1[25:0],spu_l15_addr1[39:0]}),          
 .din1({v1_spu_cpkt[25:0],v1_spu_addr[39:0]}),                     
 .sel0(ipc_v1_spu_new),
 .sel1(ipc_v1_spu_hold),
 .dout({v1_spu_cpkt[25:0],v1_spu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 i_spu_addr_v0_muxreg  
(
 .scan_in(i_spu_addr_v0_muxreg_scanin),
 .scan_out(i_spu_addr_v0_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0({spu_l15_cpkt1[25:0],spu_l15_addr1[39:0]}),          
 .din1({v1_spu_cpkt[25:0],v1_spu_addr[39:0]}),                     
 .din2({v0_spu_cpkt[25:0],v0_spu_addr[39:0]}),                     
 .sel0(ipc_v0_spu_new),
 .sel1(ipc_v0_spu_shft),
 .sel2(ipc_v0_spu_hold),
 .dout({v0_spu_cpkt[25:0],v0_spu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_64c__width_64 i_spu_data_v1_muxreg  
(
 .scan_in(i_spu_data_v1_muxreg_scanin),
 .scan_out(i_spu_data_v1_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0(spu_l15_data[63:0]),          
 .din1(v1_spu_data[63:0]),                     
 .sel0(ipc_v1_spu_new),
 .sel1(ipc_v1_spu_hold),
 .dout(v1_spu_data[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_64c__width_64 i_spu_data_v0_muxreg  
(
 .scan_in(i_spu_data_v0_muxreg_scanin),
 .scan_out(i_spu_data_v0_muxreg_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din0(spu_l15_data[63:0]),          
 .din1(v1_spu_data[63:0]),                     
 .din2(v0_spu_data[63:0]),                     
 .sel0(ipc_v0_spu_new),
 .sel1(ipc_v0_spu_shft),
 .sel2(ipc_v0_spu_hold),
 .dout(v0_spu_data[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

///////////////////////////////////////////////////////////////////
// L1/PQ cycle. Mux the pcx packets from all sources and corresponding
// DROP registers
///////////////////////////////////////////////////////////////////

// save Muxed data into drop registers
gkt_ipd_dp_msff_macro__stack_66c__width_66 i_ifu_addr_drop_reg  
(
 .scan_in(i_ifu_addr_drop_reg_scanin),
 .scan_out(i_ifu_addr_drop_reg_scanout),
 .clk (l2clk),
 .en  (ipc_dropreg_wen[0]),
 .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:0]}),          
 .dout({drop_ifu_cpkt[25:0],drop_ifu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__stack_66c__width_66 i_mmu_addr_drop_reg  
(
 .scan_in(i_mmu_addr_drop_reg_scanin),
 .scan_out(i_mmu_addr_drop_reg_scanout),
 .clk (l2clk),
 .en  (ipc_dropreg_wen[1]),
 .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:0]}),          
 .dout({drop_mmu_cpkt[25:0],drop_mmu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__stack_66c__width_66 i_lsu_addr_drop_reg  
(
 .scan_in(i_lsu_addr_drop_reg_scanin),
 .scan_out(i_lsu_addr_drop_reg_scanout),
 .clk (l2clk),
 .en  (ipc_dropreg_wen[2]),
 .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:0]}),          
 .dout({drop_lsu_cpkt[25:0],drop_lsu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__stack_66c__width_66 i_spu_addr_drop_reg  
(
 .scan_in(i_spu_addr_drop_reg_scanin),
 .scan_out(i_spu_addr_drop_reg_scanout),
 .clk (l2clk),
 .en  (ipc_dropreg_wen[3]),
 .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:0]}),          
 .dout({drop_spu_cpkt[25:0],drop_spu_addr[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__stack_64c__width_64 i_lsu_data_drop_reg  
(
 .scan_in(i_lsu_data_drop_reg_scanin),
 .scan_out(i_lsu_data_drop_reg_scanout),
 .clk (l2clk),
 .en  (ipc_dropreg_wen[2]),
 .din(ipd_data_l1[63:0]),          
 .dout(drop_lsu_data[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_msff_macro__stack_64c__width_64 i_spu_data_drop_reg  
(
 .scan_in(i_spu_data_drop_reg_scanin),
 .scan_out(i_spu_data_drop_reg_scanout),
 .clk (l2clk),
 .en  (ipc_dropreg_wen[3]),
 .din(ipd_data_l1[63:0]),          
 .dout(drop_spu_data[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// MUX the PCX packet out

gkt_ipd_dp_mux_macro__mux_aonpe__ports_8__stack_66c__width_66 i_l1_addr_mux  
(
 .din0({v0_ifu_cpkt[25:0],v0_ifu_addr[39:0]}),          
 .din1({v0_mmu_cpkt[25:0],v0_mmu_addr[39:0]}),          
 .din2({v0_lsu_cpkt[25:0],v0_lsu_addr[39:0]}),          
 .din3({v0_spu_cpkt[25:0],v0_spu_addr[39:0]}),
 .din4({drop_ifu_cpkt[25:0],drop_ifu_addr[39:0]}),          
 .din5({drop_mmu_cpkt[25:0],drop_mmu_addr[39:0]}),          
 .din6({drop_lsu_cpkt[25:0],drop_lsu_addr[39:0]}),          
 .din7({drop_spu_cpkt[25:0],drop_spu_addr[39:0]}),
 .sel0(ipc_sel_ndrop_ifu_l1),
 .sel1(ipc_sel_ndrop_mmu_l1),
 .sel2(ipc_sel_ndrop_lsu_l1),
 .sel3(ipc_sel_ndrop_spu_l1),
 .sel4(ipc_sel_drop_ifu_l1),
 .sel5(ipc_sel_drop_mmu_l1),
 .sel6(ipc_sel_drop_lsu_l1),
 .sel7(ipc_sel_drop_spu_l1),
 .dout({ipd_cpkt_l1[25:0],ipd_addr_l1_prebuf[39:0]})
);

gkt_ipd_dp_buff_macro__stack_66c__width_40 i_l1_addr_buf 
(
 .din ({ipd_addr_l1_prebuf[39:0]}),
 .dout({ipd_addr_l1[39:0]})
 );

// IF Address Hashing is enabled and Bit 39 of the address is not set (not an I/O,
// or L2 diagnostic access) then hash the addresses in following manner:
//PA[17:11]  = {(PA[32:28] ^ PA[17:13]), (PA[19:18] ^ PA[12:11])}
// enable_hash = lsu_hash_en & ~PA[39]
//             = ~(~lsu_hash_en | PA[39])
gkt_ipd_dp_msff_macro__stack_64c__width_1 i_hash_en_ff2  
(
 .scan_in(i_hash_en_ff2_scanin),
 .scan_out(i_hash_en_ff2_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din(idx_hash_en_ff),          
 .dout(idx_hash_en_ff2),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_inv_macro__stack_64c__width_1 i_hash_en_inv
(
 .din(idx_hash_en_ff2),
 .dout(idx_hash_en_)
 );

gkt_ipd_dp_nor_macro__stack_66c__width_1 i_enable_hash_nor
(
 .din0(ipd_addr_l1[39]),
 .din1(idx_hash_en_),
 .dout(enable_hash)
 );

gkt_ipd_dp_xor_macro__ports_2__stack_66c__width_7 i_l1_hash_xor 
(
 .din0({ipd_addr_l1[32:28],ipd_addr_l1[19:18]}),
 .din1({ipd_addr_l1[17:13],ipd_addr_l1[12:11]}),
 .dout(ipd_addr_hashed_l1[17:11])
 );


gkt_ipd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_7 i_l1_hash_mux  
(
 .din0(ipd_addr_hashed_l1[17:11]),
 .din1(ipd_addr_l1[17:11]),
 .sel0(enable_hash),
 .dout(ipd_addr_out_l1[17:11])
);

 
// mux the store data out
gkt_ipd_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 i_l1_data_mux  
(
 .din0(v0_lsu_data[63:0]),          
 .din1(v0_spu_data[63:0]),          
 .din2(drop_lsu_data[63:0]),          
 .din3(drop_spu_data[63:0]),          
 .sel0(ipc_sel_ndrop_lsu_l1),
 .sel1(ipc_sel_ndrop_spu_l1),
 .sel2(ipc_sel_drop_lsu_l1),
 .sel3(ipc_sel_drop_spu_l1),
 .dout(ipd_data_l1[63:0])
);


// pipe the data out to PCX in PA
gkt_ipd_dp_msff_macro__dmsff_8x__stack_66c__width_66 i_pcx_addr_pa_reg   
(
 .scan_in(i_pcx_addr_pa_reg_scanin),
 .scan_out(i_pcx_addr_pa_reg_scanout),
 .clk (l2clk),
 .en  (ipc_pq_clken),
 .din({ipd_cpkt_l1[25:0],ipd_addr_l1[39:18],ipd_addr_out_l1[17:11],ipd_addr_l1[10:0]}),          
 .dout({pcx_cpkt_pa[25:0],pcx_addr_pa[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_66 i_pcx_addr_buf   
(
 .din({pcx_cpkt_pa[25:0],pcx_addr_pa[39:0]}),
 .dout({spc_pcx_data_pa[129:64]})
 );

gkt_ipd_dp_buff_macro__stack_none__width_9 i_optype_buf 
(
 .din({pcx_cpkt_pa[10],pcx_cpkt_pa[24:20],pcx_cpkt_pa[15:13]}),
 .dout({ipd_optype[8:0]})
 );


gkt_ipd_dp_msff_macro__dmsff_8x__stack_64c__width_64 i_pcx_data_pa_reg   
(
 .scan_in(i_pcx_data_pa_reg_scanin),
 .scan_out(i_pcx_data_pa_reg_scanout),
 .clk (l2clk),
 .en  (ipc_pq_clken),
 .din(ipd_data_l1[63:0]),          
 .dout(pcx_data_pa[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 i_pcx_data_buf   
(
 .din(pcx_data_pa[63:0]),
 .dout(spc_pcx_data_pa[63:0])
 );


// fixscan start:
assign cpuid_reg_scanin          = scan_in                  ;
assign i_ncu_reg_scanin          = cpuid_reg_scanout        ;
assign i_cpx_data1lo_reg_scanin  = i_ncu_reg_scanout        ;
assign i_cpx_data1hi_reg_scanin  = i_cpx_data1lo_reg_scanout;
assign i_cpx_cpkt_reg_scanin     = i_cpx_data1hi_reg_scanout;
assign i_req_li_reg_scanin       = i_cpx_cpkt_reg_scanout   ;
assign i_ifu_addr_v1_muxreg_scanin = i_req_li_reg_scanout     ;
assign i_ifu_addr_v0_muxreg_scanin = i_ifu_addr_v1_muxreg_scanout;
assign i_mmu_addr_v1_muxreg_scanin = i_ifu_addr_v0_muxreg_scanout;
assign i_mmu_addr_v0_muxreg_scanin = i_mmu_addr_v1_muxreg_scanout;
assign i_lsu_addr_v1_muxreg_scanin = i_mmu_addr_v0_muxreg_scanout;
assign i_lsu_addr_v0_muxreg_scanin = i_lsu_addr_v1_muxreg_scanout;
assign i_lsu_data_v1_muxreg_scanin = i_lsu_addr_v0_muxreg_scanout;
assign i_lsu_data_v0_muxreg_scanin = i_lsu_data_v1_muxreg_scanout;
assign i_spu_addr_v1_muxreg_scanin = i_lsu_data_v0_muxreg_scanout;
assign i_spu_addr_v0_muxreg_scanin = i_spu_addr_v1_muxreg_scanout;
assign i_spu_data_v1_muxreg_scanin = i_spu_addr_v0_muxreg_scanout;
assign i_spu_data_v0_muxreg_scanin = i_spu_data_v1_muxreg_scanout;
assign i_ifu_addr_drop_reg_scanin = i_spu_data_v0_muxreg_scanout;
assign i_mmu_addr_drop_reg_scanin = i_ifu_addr_drop_reg_scanout;
assign i_lsu_addr_drop_reg_scanin = i_mmu_addr_drop_reg_scanout;
assign i_spu_addr_drop_reg_scanin = i_lsu_addr_drop_reg_scanout;
assign i_lsu_data_drop_reg_scanin = i_spu_addr_drop_reg_scanout;
assign i_spu_data_drop_reg_scanin = i_lsu_data_drop_reg_scanout;
assign i_hash_en_ff2_scanin      = i_spu_data_drop_reg_scanout;
assign i_pcx_addr_pa_reg_scanin  = i_hash_en_ff2_scanout    ;
assign i_pcx_data_pa_reg_scanin  = i_pcx_addr_pa_reg_scanout;
assign scan_out                  = i_pcx_data_pa_reg_scanout;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__stack_66c__width_3 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [1:0] so;

  input [2:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [2:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_6 (
  din, 
  dout);
  input [5:0] din;
  output [5:0] dout;


buff #(6)  d0_0 (
.in(din[5:0]),
.out(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__stack_64c__width_6 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [4:0] so;

  input [5:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [5:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__stack_64c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__dbuff_48x__rep_1__stack_none__width_18 (
  din, 
  dout);
  input [17:0] din;
  output [17:0] dout;


buff #(18)  d0_0 (
.in(din[17:0]),
.out(dout[17:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__stack_64c__width_18 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [16:0] so;

  input [17:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [17:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(18)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[17:0]),
.si({scan_in,so[16:0]}),
.so({so[16:0],scan_out}),
.q(dout[17:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_20 (
  din, 
  dout);
  input [19:0] din;
  output [19:0] dout;


buff #(20)  d0_0 (
.in(din[19:0]),
.out(dout[19:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__dmsff_8x__stack_64c__width_19 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [17:0] so;

  input [18:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [18:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(19)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[18:0]),
.si({scan_in,so[17:0]}),
.so({so[17:0],scan_out}),
.q(dout[18:0])
);


endmodule


//
//   invert macro
//
//


module gkt_ipd_dp_inv_macro__dinv_8x__stack_64c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module gkt_ipd_dp_nand_macro__dnand_16x__ports_2__stack_64c__width_9 (
  din0, 
  din1, 
  dout);
  input [8:0] din0;
  input [8:0] din1;
  output [8:0] dout;


nand2 #(9)  d0_0 (
.in0(din0[8:0]),
.in1(din1[8:0]),
.out(dout[8:0])
);


endmodule


//
//   invert macro
//
//


module gkt_ipd_dp_inv_macro__dinv_48x__stack_64c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


inv #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire [65:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din0;
  input sel0;
  input [65:0] din1;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_muxbuff2_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(66)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
.dout(muxout[65:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_66c__width_66 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire [65:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din0;
  input sel0;
  input [65:0] din1;
  input sel1;
  input [65:0] din2;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_muxbuff3_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(66)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
  .in2(din2[65:0]),
.dout(muxout[65:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__mux_aonpe__ports_2__stack_64c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_muxbuff2_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(64)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__mux_aonpe__ports_3__stack_64c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_muxbuff3_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(64)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__stack_66c__width_66 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_mux_macro__mux_aonpe__ports_8__stack_66c__width_66 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [65:0] din0;
  input sel0;
  input [65:0] din1;
  input sel1;
  input [65:0] din2;
  input sel2;
  input [65:0] din3;
  input sel3;
  input [65:0] din4;
  input sel4;
  input [65:0] din5;
  input sel5;
  input [65:0] din6;
  input sel6;
  input [65:0] din7;
  input sel7;
  output [65:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(66)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
  .in2(din2[65:0]),
  .in3(din3[65:0]),
  .in4(din4[65:0]),
  .in5(din5[65:0]),
  .in6(din6[65:0]),
  .in7(din7[65:0]),
.dout(dout[65:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__stack_66c__width_40 (
  din, 
  dout);
  input [39:0] din;
  output [39:0] dout;


buff #(40)  d0_0 (
.in(din[39:0]),
.out(dout[39:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__stack_64c__width_1 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;

  input [0:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [0:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module gkt_ipd_dp_inv_macro__stack_64c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module gkt_ipd_dp_nor_macro__stack_66c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module gkt_ipd_dp_xor_macro__ports_2__stack_66c__width_7 (
  din0, 
  din1, 
  dout);
  input [6:0] din0;
  input [6:0] din1;
  output [6:0] dout;


xor2 #(7)  d0_0 (
.in0(din0[6:0]),
.in1(din1[6:0]),
.out(dout[6:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_7 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [6:0] din0;
  input [6:0] din1;
  input sel0;
  output [6:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(7)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
.dout(dout[6:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  output [63:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__dmsff_8x__stack_66c__width_66 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_66 (
  din, 
  dout);
  input [65:0] din;
  output [65:0] dout;


buff #(66)  d0_0 (
.in(din[65:0]),
.out(dout[65:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__stack_none__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module gkt_ipd_dp_msff_macro__dmsff_8x__stack_64c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module gkt_ipd_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: gkt_leg_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module gkt_leg_ctl (
  instr, 
  legal, 
  flip_parity);
wire [31:0] i;
wire odd_parity;


input [31:0] instr;

output legal;
output flip_parity;


gkt_leg_ctl_spare_ctl_macro__flops_0__num_2 spares  (
);


assign i[31:0] = instr[31:0];

assign odd_parity = i[31] ^ i[30] ^ i[24] ^ i[23] ^ i[22];

assign flip_parity = ~legal & odd_parity;

// --- autogenerated by n2decode view=full Wed Aug 10 12:06:49 CDT 2005


assign legal = (!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[23]&i[22]&!i[20]
    &!i[19]&!i[18]&i[17]&i[16]&i[15]&i[14]&!i[12]&!i[11]&!i[10]&!i[9]
    &!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[1]&!i[0]) | (!i[30]
    &!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&i[24]&!i[23]&!i[21]&!i[18]&!i[17]
    &!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]
    &!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[1]&!i[0]) | (!i[30]&!i[29]&!i[28]
    &!i[27]&i[23]&!i[22]&!i[21]&i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]
    &!i[13]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]
    &!i[2]&!i[1]&!i[0]) | (i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&i[20]
    &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&!i[11]&!i[10]
    &!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[1]&!i[0]) | (
    !i[30]&!i[29]&!i[28]&!i[26]&i[23]&!i[22]&!i[21]&i[19]&!i[18]&!i[17]
    &!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]
    &!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[1]&!i[0]) | (!i[30]&!i[23]&i[22]
    &!i[20]&!i[18]&!i[17]&i[16]&!i[15]&!i[13]&!i[12]&!i[11]&!i[10]&!i[9]
    &!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[1]&!i[0]) | (!i[30]
    &!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[23]&i[22]&!i[20]&!i[19]&!i[18]
    &i[17]&i[16]&i[15]&i[14]&i[13]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]) | (
    !i[30]&!i[23]&i[22]&!i[20]&i[18]&!i[17]&i[16]&i[15]&!i[13]&!i[12]
    &!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[1]
    &!i[0]) | (!i[30]&!i[23]&i[22]&!i[20]&!i[17]&!i[16]&i[15]&i[14]&!i[13]
    &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]
    &!i[1]&!i[0]) | (!i[30]&!i[23]&i[22]&!i[20]&i[18]&!i[16]&!i[15]&!i[13]
    &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]
    &!i[1]&!i[0]) | (!i[30]&!i[23]&i[22]&!i[20]&!i[18]&!i[17]&!i[14]
    &!i[13]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]
    &!i[2]&!i[1]&!i[0]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]
    &!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&i[10]&i[9]&i[8]
    &!i[6]&i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]
    &!i[12]&i[11]&i[10]&i[7]&!i[6]&!i[4]&!i[3]&!i[2]&!i[1]&!i[0]) | (
    !i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[18]&!i[17]&!i[16]
    &!i[15]&!i[14]&!i[13]&!i[12]&i[11]&!i[9]&i[8]&i[7]&!i[6]) | (i[24]
    &i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]
    &!i[13]&i[11]&!i[10]&!i[9]&!i[8]&i[7]&i[6]&!i[5]) | (!i[30]&i[24]
    &i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]&i[11]&i[10]&!i[7]&i[6]
    &!i[4]&!i[3]&!i[2]&!i[1]&!i[0]) | (i[24]&i[23]&!i[22]&i[21]&!i[20]
    &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&i[11]&!i[10]&!i[9]
    &i[8]&!i[7]&!i[6]&i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]
    &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&i[11]&i[10]
    &!i[8]&i[6]) | (!i[28]&!i[26]&!i[25]&!i[23]&i[22]&i[21]&!i[20]&i[19]
    &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (!i[29]&i[28]
    &i[27]&i[26]&i[25]&i[23]&!i[22]&!i[21]&!i[20]&!i[19]&!i[18]&!i[17]
    &!i[16]&!i[15]&!i[14]&i[13]) | (!i[30]&!i[23]&i[22]&!i[20]&i[19]
    &!i[13]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]
    &!i[2]&!i[1]&!i[0]) | (!i[30]&i[24]&!i[23]&!i[21]&i[20]&!i[19]&!i[13]
    &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]
    &!i[1]&!i[0]) | (i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]
    &!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&!i[10]&!i[9]&!i[8]&i[6]&!i[5]) | (
    i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]
    &!i[14]&!i[13]&!i[12]&!i[10]&!i[9]&!i[8]&!i[6]&i[5]) | (!i[30]&i[24]
    &!i[23]&i[21]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[12]&!i[11]
    &!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (i[24]&i[23]&!i[22]&i[21]
    &!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&!i[11]
    &!i[9]&i[8]&!i[7]&i[6]&!i[5]) | (i[31]&!i[30]&!i[29]&!i[28]&!i[27]
    &!i[26]&!i[25]&i[24]&i[23]&i[22]&!i[21]&!i[12]&!i[11]&!i[10]&!i[9]
    &!i[8]&!i[7]&!i[6]&!i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]
    &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&i[10]&i[9]
    &i[8]&!i[7]) | (i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]
    &!i[16]&!i[15]&!i[14]&!i[13]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&i[6]
    &!i[5]) | (i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]
    &!i[15]&!i[14]&!i[13]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&i[5]) | (
    !i[28]&!i[27]&i[26]&i[25]&i[23]&!i[22]&!i[21]&!i[20]&!i[19]&!i[12]
    &!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (!i[29]&!i[28]&!i[27]
    &!i[26]&i[24]&!i[23]&!i[22]&!i[20]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]
    &!i[7]&!i[6]&!i[5]) | (!i[28]&!i[27]&!i[23]&i[22]&i[21]&!i[20]&i[19]
    &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (i[29]&!i[28]
    &i[27]&i[23]&!i[22]&!i[21]&!i[20]&!i[19]&!i[12]&!i[11]&!i[10]&!i[9]
    &!i[8]&!i[7]&!i[6]&!i[5]) | (i[29]&!i[27]&!i[26]&i[23]&!i[22]&!i[21]
    &!i[20]&!i[19]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (
    !i[30]&!i[29]&!i[28]&!i[25]&i[23]&!i[22]&!i[21]&!i[19]&!i[12]&!i[11]
    &!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (i[30]&!i[25]&!i[24]&i[19]
    &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (i[29]&!i[23]
    &i[22]&i[21]&!i[20]&i[19]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]
    &!i[5]) | (i[30]&!i[24]&!i[21]&!i[19]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]
    &!i[7]&!i[6]&!i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]
    &!i[13]&!i[12]&!i[11]&i[10]&i[8]&i[6]&!i[5]) | (!i[30]&i[23]&!i[22]
    &i[21]&!i[20]&i[19]&!i[18]&i[13]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&i[6]
    &!i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[19]&!i[13]&!i[12]&i[11]
    &i[10]&!i[9]&i[8]&!i[7]&!i[6]&i[5]) | (!i[30]&i[23]&!i[22]&i[21]
    &!i[20]&i[19]&!i[18]&i[13]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&i[5]) | (
    !i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]&!i[10]
    &i[9]&!i[8]&!i[6]&!i[5]) | (i[30]&!i[28]&!i[26]&!i[25]&i[23]&i[22]
    &i[21]&!i[20]&i[19]) | (i[30]&!i[28]&!i[26]&!i[25]&i[22]&i[21]&!i[20]
    &i[19]&i[13]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]
    &!i[12]&!i[11]&!i[10]&i[8]&!i[7]&!i[6]) | (!i[30]&i[24]&i[23]&!i[22]
    &i[21]&i[20]&!i[19]&!i[13]&!i[12]&i[10]&i[9]&!i[8]&i[7]&i[6]) | (
    !i[30]&i[24]&!i[23]&i[22]&i[21]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]
    &!i[14]&i[13]) | (i[31]&!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]
    &i[24]&i[23]&i[22]&!i[21]&i[19]&i[13]) | (i[24]&!i[23]&!i[22]&i[20]
    &i[19]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (!i[30]
    &i[24]&!i[23]&!i[22]&i[13]&i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]) | (
    i[30]&i[24]&i[23]&i[22]&i[21]&!i[19]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]
    &!i[7]&!i[6]&!i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]
    &!i[18]&!i[13]&!i[10]&!i[9]&!i[8]&!i[7]&i[6]&!i[5]) | (i[31]&!i[30]
    &!i[24]&!i[19]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (
    !i[30]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[18]&!i[13]&!i[10]
    &!i[9]&!i[8]&!i[7]&!i[6]&i[5]) | (!i[28]&!i[27]&i[26]&i[25]&i[23]
    &!i[22]&!i[21]&!i[20]&!i[19]&i[13]) | (!i[30]&i[24]&i[23]&!i[22]
    &i[21]&i[20]&!i[19]&!i[13]&!i[12]&!i[11]&i[9]&i[8]&!i[7]&!i[6]) | (
    i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[23]&!i[22]&!i[20]&i[13]) | (
    !i[30]&i[23]&!i[22]&!i[21]&i[20]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]
    &!i[7]&!i[6]&!i[5]) | (i[31]&!i[24]&!i[23]&i[22]&i[19]&!i[12]&!i[11]
    &!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (i[31]&!i[30]&!i[29]&i[23]
    &!i[21]&i[20]&!i[19]&i[13]&!i[11]&!i[10]&!i[9]&!i[8]) | (i[31]&!i[30]
    &!i[24]&i[20]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (
    !i[30]&i[24]&!i[23]&!i[22]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]
    &!i[6]&!i[5]) | (i[24]&!i[23]&!i[22]&!i[20]&!i[19]&!i[12]&!i[11]
    &!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (i[30]&!i[28]&!i[27]&i[23]
    &i[22]&i[21]&!i[20]&i[19]) | (i[29]&!i[28]&i[27]&i[23]&!i[22]&!i[21]
    &!i[20]&!i[19]&i[13]) | (i[29]&!i[27]&!i[26]&i[23]&!i[22]&!i[21]
    &!i[20]&!i[19]&i[13]) | (i[30]&!i[28]&!i[27]&i[22]&i[21]&!i[20]&i[19]
    &i[13]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]
    &!i[11]&i[10]&!i[9]&!i[5]) | (!i[29]&!i[28]&!i[25]&i[23]&!i[22]&!i[21]
    &!i[20]&!i[19]&i[13]) | (i[31]&!i[24]&i[20]&!i[19]&!i[12]&!i[11]
    &!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (i[31]&!i[24]&!i[22]&!i[20]
    &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (!i[30]&i[24]
    &i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]&!i[11]&!i[10]&!i[7]
    &!i[5]) | (!i[30]&i[24]&!i[23]&i[22]&i[21]&i[19]&i[13]&i[11]) | (
    !i[30]&!i[23]&i[22]&i[21]&!i[20]&!i[18]&i[13]) | (!i[30]&i[24]&!i[23]
    &i[22]&i[21]&i[19]&i[13]&i[10]) | (i[30]&!i[25]&!i[24]&i[23]&i[19]) | (
    i[30]&i[29]&i[23]&i[22]&i[21]&!i[20]&i[19]) | (i[30]&!i[25]&!i[24]
    &i[19]&i[13]) | (i[30]&i[29]&i[22]&i[21]&!i[20]&i[19]&i[13]) | (
    i[30]&!i[24]&i[23]&!i[21]&!i[19]) | (i[30]&!i[24]&!i[21]&!i[19]&i[13]) | (
    !i[30]&!i[23]&i[22]&i[21]&!i[20]&i[13]&!i[11]) | (i[30]&!i[24]&i[23]
    &i[22]&i[19]) | (i[31]&!i[30]&!i[24]&!i[23]&i[13]) | (i[30]&!i[24]
    &i[22]&i[19]&i[13]) | (!i[30]&i[23]&!i[22]&!i[21]&i[20]&i[13]) | (
    i[30]&!i[24]&i[23]&!i[20]&i[19]) | (i[30]&!i[24]&i[23]&i[20]&!i[19]) | (
    i[31]&!i[30]&i[24]&i[22]&i[21]&!i[20]&i[19]&i[13]) | (i[30]&!i[24]
    &i[20]&!i[19]&i[13]) | (i[30]&i[24]&i[23]&i[22]&i[21]&!i[19]&!i[13]) | (
    !i[30]&i[24]&!i[23]&!i[22]&!i[21]&i[13]) | (i[24]&!i[23]&!i[22]&!i[20]
    &!i[19]&i[13]) | (i[31]&!i[30]&!i[24]&i[20]&i[13]) | (i[31]&!i[24]
    &!i[22]&!i[20]&i[13]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]
    &!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&!i[12]&i[11]&i[10]&!i[4]
    &!i[3]&!i[2]&!i[1]&!i[0]) | (!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]
    &i[24]&i[23]&!i[22]&i[21]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]
    &!i[13]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&i[5]&!i[4]&!i[3]) | (
    i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]
    &!i[14]&!i[13]&i[12]&i[11]&!i[10]&i[9]&!i[8]&!i[7]&i[6]&!i[5]) | (
    i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]
    &!i[14]&!i[13]&i[12]&i[11]&!i[10]&i[9]&!i[8]&!i[7]&!i[6]&i[5]) | (
    i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]
    &!i[14]&!i[13]&!i[12]&!i[9]&i[8]&!i[7]&!i[6]&i[5]) | (i[24]&i[23]
    &!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]
    &i[12]&!i[10]&!i[9]&i[8]&!i[7]&!i[6]&!i[5]) | (i[24]&i[23]&!i[22]
    &i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[13]&i[12]
    &!i[10]&!i[9]&!i[8]&i[7]&!i[6]&!i[5]) | (!i[30]&!i[29]&!i[28]&!i[27]
    &i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[13]&!i[12]&i[11]&!i[10]
    &i[9]&!i[8]&i[6]&!i[5]) | (!i[30]&!i[29]&!i[28]&!i[27]&i[24]&i[23]
    &!i[22]&i[21]&!i[20]&i[19]&!i[13]&!i[12]&i[11]&!i[10]&i[9]&!i[8]&!i[6]
    &i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]
    &i[11]&i[10]&i[8]&i[7]&!i[6]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]
    &i[20]&!i[19]&!i[13]&!i[12]&i[11]&i[10]&i[9]&!i[7]&i[6]) | (!i[30]
    &i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]&i[11]&i[10]&!i[9]
    &i[8]&i[7]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]
    &!i[12]&!i[11]&i[10]&i[9]&!i[8]&i[5]) | (!i[30]&i[24]&i[23]&!i[22]
    &i[21]&i[20]&!i[19]&!i[13]&!i[12]&i[11]&!i[10]&i[9]&!i[8]) | (!i[30]
    &i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]&i[11]&i[9]&!i[8]
    &!i[7]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]
    &!i[10]&!i[9]&i[8]&!i[7]&i[6]&i[5]) | (i[24]&i[23]&!i[22]&i[21]&!i[20]
    &!i[19]&!i[13]&!i[12]&i[11]&!i[10]&!i[9]&i[6]&!i[5]) | (!i[30]&i[24]
    &i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]&i[11]&i[10]&!i[9]&i[7]
    &!i[6]) | (i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[19]&!i[13]&!i[12]&i[11]
    &!i[10]&!i[9]&!i[6]&i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[20]
    &!i[19]&!i[13]&!i[12]&i[11]&i[10]&!i[8]&!i[7]&i[6]) | (!i[30]&i[24]
    &!i[23]&i[22]&i[21]&!i[20]&!i[19]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]
    &!i[6]&!i[5]) | (!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[19]&!i[11]&!i[10]
    &!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]
    &i[20]&!i[19]&!i[13]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]) | (!i[30]
    &i[24]&i[23]&!i[22]&i[21]&i[20]&!i[19]&!i[13]&!i[12]&i[11]&!i[9]&i[8]
    &!i[6]&!i[5]) | (i[31]&!i[30]&!i[29]&i[24]&i[23]&i[22]&!i[21]&i[20]
    &!i[19]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (i[31]&!i[30]
    &i[24]&i[22]&i[21]&!i[20]&!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]
    &!i[5]) | (!i[30]&i[24]&!i[23]&!i[22]&i[21]&i[20]&!i[11]&!i[10]&!i[9]
    &!i[8]&!i[7]&!i[6]&!i[5]) | (i[31]&!i[30]&i[23]&i[22]&!i[20]&!i[19]
    &!i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]) | (!i[30]&i[24]
    &!i[23]&i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[10]&!i[9]&!i[8]&!i[7]
    &!i[6]&!i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[13]
    &i[10]&!i[9]&!i[8]&i[7]&i[6]&!i[5]) | (!i[30]&i[24]&i[23]&!i[22]
    &i[21]&!i[20]&i[19]&!i[13]&i[10]&!i[9]&!i[8]&i[7]&!i[6]&i[5]) | (
    !i[30]&i[24]&!i[23]&i[22]&i[21]&i[20]&i[19]&i[10]&!i[9]&!i[8]&!i[7]
    &!i[6]&!i[5]) | (!i[30]&i[24]&i[23]&!i[22]&i[21]&!i[20]&i[19]&!i[13]
    &i[11]&!i[9]&!i[8]&i[7]&i[6]&!i[5]) | (!i[30]&i[24]&i[23]&!i[22]
    &i[21]&!i[20]&i[19]&!i[13]&i[11]&!i[9]&!i[8]&i[7]&!i[6]&i[5]) | (
    !i[30]&i[24]&!i[23]&i[22]&i[21]&i[20]&i[19]&i[11]&!i[9]&!i[8]&!i[7]
    &!i[6]&!i[5]) | (!i[31]&!i[23]&i[22]&!i[20]) | (!i[31]&i[24]&!i[23]) | (
    !i[31]&i[23]&!i[22]) | (!i[31]&!i[28]&i[26]&!i[24]&i[23]) | (!i[31]
    &!i[28]&i[25]&!i[24]&i[23]) | (i[30]&i[24]&!i[22]&i[20]&i[19]&i[13]) | (
    i[30]&i[24]&i[23]&!i[22]&i[20]&i[19]) | (i[31]&!i[30]&i[23]&i[22]
    &!i[20]&!i[19]&i[13]) | (i[30]&i[23]&!i[22]&!i[20]&!i[19]) | (!i[31]
    &i[30]);

// end autogeneration

endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module gkt_leg_ctl_spare_ctl_macro__flops_0__num_2;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: gkt_pqm_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module gkt_pqm_ctl (
  l1clk, 
  scan_in, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  pqm_req_drop, 
  pqm_empty, 
  spc_pcx_req_pq, 
  pcx_grant);
wire siclk;
wire soclk;
wire [1:0] qcnt_inc;
wire [1:0] qcnt;
wire [1:0] qcnt_dec;
wire qfull;
wire incr;
wire decr;
wire hold;
wire [1:0] qcnt_next;
wire dff_qcnt_scanin;
wire dff_qcnt_scanout;


// globals
input           l1clk;
input           scan_in;
input           spc_aclk;
input           spc_bclk;
output          scan_out;

output pqm_req_drop;
output pqm_empty;


input spc_pcx_req_pq;
input pcx_grant;

// scan renames
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan


////////////////////////////////////////////////////////
// keep track of ccx fifo
// l15 can send 2 requests followed by a 3rd speculative req.
// If a grant is not seen in the cycle when 3rd req is launched,
// then it is dropped by ccx, and l15 has to resend it.

assign qcnt_inc[1:0] = qcnt[1:0] + 2'b01;
assign qcnt_dec[1:0] = (qcnt[1:0] == 2'b00)? 2'b00: (qcnt[1:0] - 2'b01);

assign qfull = qcnt[1];
assign pqm_empty = ~qcnt[1] & ~qcnt[0];

// do not increment if qfull, the req is going to get dropped.

assign incr = spc_pcx_req_pq & ~qfull & ~pcx_grant;
assign decr = ~spc_pcx_req_pq & pcx_grant;
assign hold = ~incr & ~decr;
//assign qcnt_next[1:0] = incr? qcnt_inc[1:0]: decr ? qcnt_dec[1:0] : qcnt[1:0];

assign qcnt_next[1:0] = ({2{incr}} & qcnt_inc[1:0]) |
                        ({2{decr}} & qcnt_dec[1:0]) |
                        ({2{hold}} & qcnt[1:0]);

// pcx_grant is a very late signal.
//


// 0in overflow -var qcnt_next[1:0] -min 0 -max 2

assign pqm_req_drop = qcnt[1] & spc_pcx_req_pq & ~pcx_grant;

gkt_pqm_ctl_msff_ctl_macro__width_2 dff_qcnt
  (
   .scan_in(dff_qcnt_scanin),
   .scan_out(dff_qcnt_scanout),
   .din           (qcnt_next[1:0]),
   .dout             (qcnt[1:0]),
   .l1clk         (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// fixscan start:
assign dff_qcnt_scanin           = scan_in                  ;
assign scan_out                  = dff_qcnt_scanout         ;
// fixscan end:
endmodule // gkt_pqm_ctl


// any PARAMS parms go into naming of macro

module gkt_pqm_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_cmu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_cmu (
  tcu_scan_en, 
  l2clk, 
  spc_aclk, 
  spc_bclk, 
  tcu_pce_ov, 
  scan_in, 
  const_cpuid, 
  lsu_ifu_cmu_pmen, 
  ftu_paddr, 
  ftu_rep_way, 
  ftu_thrx_un_cacheable, 
  ftu_curr_fetch_thr_f, 
  ftu_agc_thr0_cmiss_c, 
  ftu_agc_thr1_cmiss_c, 
  ftu_agc_thr2_cmiss_c, 
  ftu_agc_thr3_cmiss_c, 
  ftu_agc_thr4_cmiss_c, 
  ftu_agc_thr5_cmiss_c, 
  ftu_agc_thr6_cmiss_c, 
  ftu_agc_thr7_cmiss_c, 
  ftu_thr0_inv_req_c, 
  ftu_thr1_inv_req_c, 
  ftu_thr2_inv_req_c, 
  ftu_thr3_inv_req_c, 
  ftu_thr4_inv_req_c, 
  ftu_thr5_inv_req_c, 
  ftu_thr6_inv_req_c, 
  ftu_thr7_inv_req_c, 
  ftu_thr0_redirect_bf, 
  ftu_thr1_redirect_bf, 
  ftu_thr2_redirect_bf, 
  ftu_thr3_redirect_bf, 
  ftu_thr4_redirect_bf, 
  ftu_thr5_redirect_bf, 
  ftu_thr6_redirect_bf, 
  ftu_thr7_redirect_bf, 
  lsu_ifu_ld_index, 
  l15_spc_cpkt, 
  l15_spc_data1, 
  l15_ifu_valid, 
  l15_ifu_grant, 
  gkt_ifu_legal, 
  gkt_ifu_flip_parity, 
  cmu_l2miss, 
  cmu_any_data_ready, 
  cmu_thr0_data_ready, 
  cmu_thr1_data_ready, 
  cmu_thr2_data_ready, 
  cmu_thr3_data_ready, 
  cmu_thr4_data_ready, 
  cmu_thr5_data_ready, 
  cmu_thr6_data_ready, 
  cmu_thr7_data_ready, 
  cmu_any_un_cacheable, 
  cmu_null_st, 
  cmu_dupmiss_st, 
  cmu_rst_dupmiss, 
  cmu_inst0_v, 
  cmu_inst1_v, 
  cmu_inst2_v, 
  cmu_inst3_v, 
  cmu_fill_wrway, 
  cmu_fill_paddr, 
  cmu_fill_inst0, 
  cmu_fill_inst1, 
  cmu_fill_inst2, 
  cmu_fill_inst3, 
  cmu_ic_data, 
  cmu_icache_invalidate, 
  cmu_icache_invalidate_way, 
  cmu_icache_invalidate_index, 
  cmu_icache_inv_way1, 
  cmu_evic_invalidate, 
  cmu_inval_ack, 
  cmu_l2_err, 
  ifu_l15_valid, 
  ifu_l15_cpkt, 
  ifu_l15_addr, 
  ifu_lsu_if_vld, 
  ifu_lsu_if_tid, 
  ifu_lsu_if_addr, 
  scan_out) ;
wire [7:0] ftu_cmiss;
wire [7:0] ftu_inv_req;
wire [7:0] ftu_redirect;
wire [7:0] cmu_data_ready;
wire [7:0] mct_rst_dupmiss;
wire [7:0] ftu_fetch_f;
wire [7:0] csm_valid_req;
wire [7:0] cmu_req_st;
wire [7:0] cmu_canleave_st;
wire cmsm_top_scanin;
wire cmsm_top_scanout;
wire [7:0] mct_fill_complete;
wire [7:0] lsc_l15_valid;
wire [7:0] cmu_has_dup_miss;
wire mct_ignore_cmiss;
wire lsc_fill_rtn1;
wire lsc_fill_rtn2;
wire [7:0] lsc_req_sel;
wire lsc_pending_req;
wire lsi_ctl_scanin;
wire lsi_ctl_scanout;
wire mct_early_req;
wire mdp_lsi_nc_bit;
wire mdp_lsi_inv_bit;
wire [2:0] mdp_lsi_rway;
wire lsi_dp_scanin;
wire lsi_dp_scanout;
wire [7:0] mct_clken;
wire [7:0] mct_upd_addr;
wire [7:0] mct_real_wom;
wire missbuff_ctl_scanin;
wire missbuff_ctl_scanout;
wire [7:0] mdp_mbhit_q;
wire missbuff_dp_scanin;
wire missbuff_dp_scanout;
wire [7:0] lsc_data_sel;
wire lsc_clken;


input tcu_scan_en ;
input l2clk;
input spc_aclk;
input spc_bclk;
input tcu_pce_ov;
input scan_in;

input [2:0] const_cpuid;
input       lsu_ifu_cmu_pmen;

input [39:0] ftu_paddr;
input [2:0]  ftu_rep_way;  
input        ftu_thrx_un_cacheable;

input [7:0]  ftu_curr_fetch_thr_f;


input        ftu_agc_thr0_cmiss_c;
input        ftu_agc_thr1_cmiss_c;
input        ftu_agc_thr2_cmiss_c;
input        ftu_agc_thr3_cmiss_c;
input        ftu_agc_thr4_cmiss_c;
input        ftu_agc_thr5_cmiss_c;
input        ftu_agc_thr6_cmiss_c;
input        ftu_agc_thr7_cmiss_c;

input        ftu_thr0_inv_req_c;  
input        ftu_thr1_inv_req_c;  
input        ftu_thr2_inv_req_c;  
input        ftu_thr3_inv_req_c;  
input        ftu_thr4_inv_req_c;  
input        ftu_thr5_inv_req_c;  
input        ftu_thr6_inv_req_c;  
input        ftu_thr7_inv_req_c;  


input        ftu_thr0_redirect_bf;
input        ftu_thr1_redirect_bf;
input        ftu_thr2_redirect_bf;
input        ftu_thr3_redirect_bf;
input        ftu_thr4_redirect_bf;
input        ftu_thr5_redirect_bf;
input        ftu_thr6_redirect_bf;
input        ftu_thr7_redirect_bf;


input [10:5] lsu_ifu_ld_index;

input [17:0] l15_spc_cpkt;                                               
input [127:0] l15_spc_data1;                                               
input         l15_ifu_valid;                                               
input         l15_ifu_grant;
input [3:0]   gkt_ifu_legal;
input [3:0]   gkt_ifu_flip_parity;


output        cmu_l2miss;


output        cmu_any_data_ready;
output        cmu_thr0_data_ready;   
output        cmu_thr1_data_ready;  
output        cmu_thr2_data_ready;  
output        cmu_thr3_data_ready;  
output        cmu_thr4_data_ready;  
output        cmu_thr5_data_ready;  
output        cmu_thr6_data_ready;  
output        cmu_thr7_data_ready;

output        cmu_any_un_cacheable;


output [7:0] cmu_null_st;
output [7:0] cmu_dupmiss_st;
output [7:0] cmu_rst_dupmiss;
   
output        cmu_inst0_v;                            
output        cmu_inst1_v;                            
output        cmu_inst2_v;                            
output        cmu_inst3_v;                            

output [2:0]  cmu_fill_wrway;                    //MB to ??
output [39:0] cmu_fill_paddr;
output [32:0] cmu_fill_inst0;
output [32:0] cmu_fill_inst1;
output [32:0] cmu_fill_inst2;
output [32:0] cmu_fill_inst3;
output [263:0] cmu_ic_data;

output         cmu_icache_invalidate;
output [2:0]   cmu_icache_invalidate_way;
output [10:5]  cmu_icache_invalidate_index;
output [2:0]   cmu_icache_inv_way1;
output         cmu_evic_invalidate;
output [7:0]   cmu_inval_ack;
output [1:0]   cmu_l2_err;

// **** gkt Interface ****
output        ifu_l15_valid;                   // Valid to L15
output [7:0] ifu_l15_cpkt;                    // Control packet to L15
output [39:0] ifu_l15_addr;                    // Address to L15


// **** LSU Interface ****
output         ifu_lsu_if_vld;
output [2:0]   ifu_lsu_if_tid;
output [10:5]  ifu_lsu_if_addr;


output         scan_out;


assign ftu_cmiss[7:0] = {ftu_agc_thr7_cmiss_c,ftu_agc_thr6_cmiss_c,ftu_agc_thr5_cmiss_c,ftu_agc_thr4_cmiss_c,
                         ftu_agc_thr3_cmiss_c,ftu_agc_thr2_cmiss_c,ftu_agc_thr1_cmiss_c,ftu_agc_thr0_cmiss_c};

assign ftu_inv_req[7:0] = {ftu_thr7_inv_req_c,ftu_thr6_inv_req_c,ftu_thr5_inv_req_c,ftu_thr4_inv_req_c,
                           ftu_thr3_inv_req_c,ftu_thr2_inv_req_c,ftu_thr1_inv_req_c,ftu_thr0_inv_req_c};

assign ftu_redirect[7:0] = {ftu_thr7_redirect_bf,ftu_thr6_redirect_bf,ftu_thr5_redirect_bf,ftu_thr4_redirect_bf,
                            ftu_thr3_redirect_bf,ftu_thr2_redirect_bf,ftu_thr1_redirect_bf,ftu_thr0_redirect_bf};

assign {cmu_thr7_data_ready,cmu_thr6_data_ready,cmu_thr5_data_ready,cmu_thr4_data_ready,
        cmu_thr3_data_ready,cmu_thr2_data_ready,cmu_thr1_data_ready,cmu_thr0_data_ready} = cmu_data_ready[7:0];

assign cmu_rst_dupmiss[7:0] = mct_rst_dupmiss[7:0];

assign ftu_fetch_f[7:0] = ftu_curr_fetch_thr_f[7:0];

   
ifu_cmu_cmt_ctl cmt (
                          /*AUTOINST*/
                          // Outputs
                          .csm_valid_req(csm_valid_req[7:0]),
                          .cmu_null_st(cmu_null_st[7:0]),
                          .cmu_req_st(cmu_req_st[7:0]),
                          .cmu_canleave_st(cmu_canleave_st[7:0]),
                          .cmu_dupmiss_st(cmu_dupmiss_st[7:0]),
                          // Inputs
                          .tcu_pce_ov   (tcu_pce_ov),
                          .spc_aclk (spc_aclk),
                          .spc_bclk (spc_bclk),
                          .scan_in(cmsm_top_scanin),
                          .scan_out(cmsm_top_scanout),
                          .l2clk        (l2clk),
                          .ftu_cmiss    (ftu_cmiss[7:0]),
                          .ftu_redirect (ftu_redirect[7:0]),
                          .mct_fill_complete(mct_fill_complete[7:0]),
                          .ftu_inv_req  (ftu_inv_req[7:0]),
                          .lsc_l15_valid(lsc_l15_valid[7:0]),
                          .cmu_data_ready(cmu_data_ready[7:0]),
                          .cmu_has_dup_miss(cmu_has_dup_miss[7:0]),
                          .mct_rst_dupmiss(mct_rst_dupmiss[7:0]),
                          .mct_ignore_cmiss(mct_ignore_cmiss),
  .tcu_scan_en(tcu_scan_en),
  .mdp_mbhit_q(mdp_mbhit_q[7:0]));


ifu_cmu_lsi_ctl lsc (
                         /*AUTOINST*/
                         // Outputs
                         .lsc_fill_rtn1 (lsc_fill_rtn1),
                         .lsc_fill_rtn2 (lsc_fill_rtn2),
                         .lsc_req_sel   (lsc_req_sel[7:0]),
                         .lsc_pending_req(lsc_pending_req),
                         .lsc_l15_valid (lsc_l15_valid[7:0]),
                         .cmu_any_data_ready(cmu_any_data_ready),
                         .cmu_any_un_cacheable(cmu_any_un_cacheable),
                         .cmu_data_ready(cmu_data_ready[7:0]),
                         .cmu_inst0_v   (cmu_inst0_v),
                         .cmu_inst1_v   (cmu_inst1_v),
                         .cmu_inst2_v   (cmu_inst2_v),
                         .cmu_inst3_v   (cmu_inst3_v),
                         .cmu_icache_invalidate(cmu_icache_invalidate),
                         .cmu_icache_invalidate_way(cmu_icache_invalidate_way[2:0]),
                         .cmu_icache_invalidate_index(cmu_icache_invalidate_index[10:5]),
                         .cmu_evic_invalidate(cmu_evic_invalidate),
                         .cmu_icache_inv_way1(cmu_icache_inv_way1[2:0]),
                         .cmu_inval_ack (cmu_inval_ack[7:0]),
                         .cmu_l2_err    (cmu_l2_err[1:0]),
                         .cmu_l2miss    (cmu_l2miss),
                         .ifu_l15_valid (ifu_l15_valid),
                         .ifu_l15_cpkt  (ifu_l15_cpkt[7:0]),
                         .ifu_lsu_if_vld(ifu_lsu_if_vld),
                         .ifu_lsu_if_tid(ifu_lsu_if_tid[2:0]),
                         .ifu_lsu_if_addr(ifu_lsu_if_addr[10:5]),
                         // Inputs
                         .scan_in(lsi_ctl_scanin),
                         .scan_out(lsi_ctl_scanout),
                         .l2clk         (l2clk),
                         .tcu_pce_ov    (tcu_pce_ov),
                         .spc_aclk  (spc_aclk),
                         .spc_bclk  (spc_bclk),
                         .const_cpuid   (const_cpuid[2:0]),
                         .lsu_ifu_cmu_pmen   (lsu_ifu_cmu_pmen),
                         .ftu_cmiss(ftu_cmiss[7:0]),
                         .mct_early_req (mct_early_req),
                         .ftu_rep_way   (ftu_rep_way[2:0]),
                         .ftu_thrx_un_cacheable(ftu_thrx_un_cacheable),
                         .ifu_l15_addr  (ifu_l15_addr[10:5]),
                         .csm_valid_req (csm_valid_req[7:0]),
                         .l15_spc_data1 (l15_spc_data1[127:0]),
                         .l15_spc_cpkt  (l15_spc_cpkt[17:0]),
                         .l15_ifu_valid (l15_ifu_valid),
                         .l15_ifu_grant (l15_ifu_grant),
                         .lsu_ifu_ld_index(lsu_ifu_ld_index[10:5]),
                         .cmu_fill_paddr(cmu_fill_paddr[4:2]),
                         .mdp_lsi_nc_bit(mdp_lsi_nc_bit),
                         .mdp_lsi_inv_bit(mdp_lsi_inv_bit),
                         .mdp_lsi_rway  (mdp_lsi_rway[2:0]),
  .tcu_scan_en(tcu_scan_en),
  .lsc_data_sel(lsc_data_sel[7:0]),
  .lsc_clken(lsc_clken));


ifu_cmu_lsi_dp  lsd (
                        /*AUTOINST*/
                        // Outputs
                        .cmu_ic_data    (cmu_ic_data[263:0]),
                        .cmu_fill_inst0 (cmu_fill_inst0[32:0]),
                        .cmu_fill_inst1 (cmu_fill_inst1[32:0]),
                        .cmu_fill_inst2 (cmu_fill_inst2[32:0]),
                        .cmu_fill_inst3 (cmu_fill_inst3[32:0]),
                        // Inputs
                        .scan_in(lsi_dp_scanin),
                        .scan_out(lsi_dp_scanout),
                        .l2clk          (l2clk),
                        .spc_aclk   (spc_aclk),
                        .spc_bclk   (spc_bclk),
                        .tcu_pce_ov     (tcu_pce_ov),
                        .l15_spc_data1  (l15_spc_data1[127:0]),
                        .lsc_fill_rtn1  (lsc_fill_rtn1),
                     .lsc_fill_rtn2  (lsc_fill_rtn2),
  .tcu_scan_en(tcu_scan_en),
  .lsc_clken(lsc_clken),
  .lsc_data_sel(lsc_data_sel[7:0]),
  .gkt_ifu_legal(gkt_ifu_legal[3:0]),
  .gkt_ifu_flip_parity(gkt_ifu_flip_parity[3:0]));


ifu_cmu_msb_ctl mct (
                              /*AUTOINST*/
                              // Outputs
                              .mct_clken(mct_clken[7:0]),
                              .mct_early_req(mct_early_req),
                              .mct_upd_addr(mct_upd_addr[7:0]),
                              .mct_real_wom(mct_real_wom[7:0]),
                              .cmu_has_dup_miss(cmu_has_dup_miss[7:0]),
                              .mct_rst_dupmiss(mct_rst_dupmiss[7:0]),
                              .mct_fill_complete(mct_fill_complete[7:0]),
                              .mct_ignore_cmiss(mct_ignore_cmiss),
                              // Inputs
                              .scan_in(missbuff_ctl_scanin),
                              .scan_out(missbuff_ctl_scanout),
                              .l2clk    (l2clk),
                              .tcu_pce_ov(tcu_pce_ov),
                              .spc_aclk(spc_aclk),
                              .spc_bclk(spc_bclk),
                              .lsu_ifu_cmu_pmen   (lsu_ifu_cmu_pmen),
                              .ftu_cmiss(ftu_cmiss[7:0]),
                              .ftu_fetch_f(ftu_fetch_f[7:0]),
                              .ftu_inv_req(ftu_inv_req[7:0]),
                              .ftu_redirect(ftu_redirect[7:0]),
                              .l15_spc_cpkt(l15_spc_cpkt[8:6]),
                              .cmu_req_st(cmu_req_st[7:0]),
                              .cmu_canleave_st(cmu_canleave_st[7:0]),
                              .lsc_l15_valid(lsc_l15_valid[7:0]),
                              .cmu_data_ready(cmu_data_ready[7:0]),
                              .lsc_fill_rtn2(lsc_fill_rtn2),
                              .mdp_mbhit_q(mdp_mbhit_q[7:0]),
  .tcu_scan_en(tcu_scan_en));


ifu_cmu_msb_dp mdp (
                            /*AUTOINST*/
                            // Outputs
                            .mdp_mbhit_q(mdp_mbhit_q[7:0]),
                            .mdp_lsi_rway(mdp_lsi_rway[2:0]),
                            .ifu_l15_addr(ifu_l15_addr[39:0]),
                            .mdp_lsi_nc_bit(mdp_lsi_nc_bit),
                            .mdp_lsi_inv_bit(mdp_lsi_inv_bit),
                            .cmu_fill_wrway(cmu_fill_wrway[2:0]),
                            .cmu_fill_paddr(cmu_fill_paddr[39:0]),
                            // Inputs
                            .scan_in(missbuff_dp_scanin),
                            .scan_out(missbuff_dp_scanout),
                            .l2clk      (l2clk),
                            .tcu_pce_ov (tcu_pce_ov),
                            .spc_aclk(spc_aclk),
                            .spc_bclk(spc_bclk),
                            .l15_spc_cpkt(l15_spc_cpkt[8:6]),
                            .ftu_paddr  (ftu_paddr[39:0]),
                            .ftu_rep_way(ftu_rep_way[2:0]),
                            .ftu_inv_req(ftu_inv_req[7:0]),
                            .ftu_thrx_un_cacheable(ftu_thrx_un_cacheable),
                            .lsc_pending_req(lsc_pending_req),
                            .lsc_req_sel(lsc_req_sel[7:0]),
                              .mct_real_wom(mct_real_wom[7:0]),
                    .mct_upd_addr(mct_upd_addr[7:0]),
  .tcu_scan_en(tcu_scan_en),
  .mct_clken(mct_clken[7:0]));


// fixscan start:
assign cmsm_top_scanin           = scan_in                  ;
assign lsi_ctl_scanin            = cmsm_top_scanout         ;
assign lsi_dp_scanin             = lsi_ctl_scanout          ;
assign missbuff_ctl_scanin       = lsi_dp_scanout           ;
assign missbuff_dp_scanin        = missbuff_ctl_scanout     ;
assign scan_out                  = missbuff_dp_scanout      ;
// fixscan end:
endmodule
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_cmu_cmt_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_cmu_cmt_ctl (
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  l2clk, 
  ftu_cmiss, 
  ftu_redirect, 
  mct_fill_complete, 
  ftu_inv_req, 
  lsc_l15_valid, 
  cmu_data_ready, 
  cmu_has_dup_miss, 
  mct_rst_dupmiss, 
  mdp_mbhit_q, 
  mct_ignore_cmiss, 
  csm_valid_req, 
  cmu_null_st, 
  cmu_dupmiss_st, 
  cmu_req_st, 
  cmu_canleave_st, 
  scan_out) ;
wire pce_ov;
wire stop;
wire se;
wire siclk;
wire soclk;
wire l1clk;
wire cmu_mbhit_c;
wire csm0_scanin;
wire csm0_scanout;
wire csm1_scanin;
wire csm1_scanout;
wire csm2_scanin;
wire csm2_scanout;
wire csm3_scanin;
wire csm3_scanout;
wire csm4_scanin;
wire csm4_scanout;
wire csm5_scanin;
wire csm5_scanout;
wire csm6_scanin;
wire csm6_scanout;
wire csm7_scanin;
wire csm7_scanout;
wire spares_scanin;
wire spares_scanout;


input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;
input tcu_scan_en ;
input l2clk;

input [7:0] ftu_cmiss;
input [7:0] ftu_redirect;
input [7:0] mct_fill_complete;
input [7:0] ftu_inv_req;

input [7:0] lsc_l15_valid;

input [7:0] cmu_data_ready;
input [7:0] cmu_has_dup_miss;

input [7:0] mct_rst_dupmiss;
input [7:0] mdp_mbhit_q;
input       mct_ignore_cmiss;

output [7:0] csm_valid_req;
//output [7:0] cmu_cmiss_is_sent;
output [7:0] cmu_null_st;
output [7:0] cmu_dupmiss_st;
output [7:0] cmu_req_st;
output [7:0] cmu_canleave_st;
   
output scan_out;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign se = tcu_scan_en ;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

///////////////////////////////////////////////////
// clock header
///////////////////////////////////////////////////
ifu_cmu_cmt_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

assign cmu_mbhit_c = |(mdp_mbhit_q[7:0]);

/*
// ifu_cmu_csm_ctl AUTO_TEMPLATE
 (
.ftu_inv_req(ftu_inv_req[@]),                      
.ftu_cmiss(ftu_cmiss[@]),
.lsc_l15_valid(lsc_l15_valid[@]),
.mct_fill_complete(mct_fill_complete[@]),
.cmu_data_ready(cmu_data_ready[@]),
.cmu_has_dup_miss(cmu_has_dup_miss[@]),
.cmu_mbhit_c(cmu_mbhit_c),
.ftu_redirect(ftu_redirect[@]),
.mct_rst_dupmiss(mct_rst_dupmiss[@]),
.mdp_mbhit_q(mdp_mbhit_q[@]),
.csm_valid_req(csm_valid_req[@]),
.cmu_null_st(cmu_null_st[@]),
.cmu_req_st(cmu_req_st[@]),
.cmu_canleave_st(cmu_canleave_st[@]),
.cmu_dupmiss_st(cmu_dupmiss_st[@]),
 );
 */

ifu_cmu_csm_ctl csm0 (
                      /*AUTOINST*/
                      // Outputs
                      .csm_valid_req      (csm_valid_req[0]),        // Templated
                      .cmu_null_st(cmu_null_st[0]),  // Templated
                      .cmu_req_st(cmu_req_st[0]),  // Templated
                      .cmu_canleave_st(cmu_canleave_st[0]),  // Templated
                      .cmu_dupmiss_st(cmu_dupmiss_st[0]),  // Templated
                      // Inputs
                      .scan_in(csm0_scanin),
                      .scan_out(csm0_scanout),
                      .l1clk            (l1clk),
                      .spc_aclk     (spc_aclk),
                      .spc_bclk     (spc_bclk),
                      .ftu_cmiss        (ftu_cmiss[0]),          // Templated
                      .ftu_inv_req      (ftu_inv_req[0]),        // Templated
                      .lsc_l15_valid      (lsc_l15_valid[0]),        // Templated
                      .mct_fill_complete(mct_fill_complete[0]),  // Templated
                      .cmu_data_ready   (cmu_data_ready[0]),     // Templated
                      .cmu_has_dup_miss (cmu_has_dup_miss[0]),   // Templated
                      .cmu_mbhit_c      (cmu_mbhit_c),           // Templated
                      .ftu_redirect     (ftu_redirect[0]),       // Templated
                      .mct_rst_dupmiss  (mct_rst_dupmiss[0]),    // Templated
                      .mdp_mbhit_q      (mdp_mbhit_q[0]),        // Templated
                      .mct_ignore_cmiss (mct_ignore_cmiss));

ifu_cmu_csm_ctl csm1 (
                      /*AUTOINST*/
                      // Outputs
                      .csm_valid_req      (csm_valid_req[1]),        // Templated
                      .cmu_null_st(cmu_null_st[1]),  // Templated
                      .cmu_req_st(cmu_req_st[1]),  // Templated
                      .cmu_canleave_st(cmu_canleave_st[1]),  // Templated
                      .cmu_dupmiss_st(cmu_dupmiss_st[1]),  // Templated
                      // Inputs
                      .scan_in(csm1_scanin),
                      .scan_out(csm1_scanout),
                      .l1clk            (l1clk),
                      .spc_aclk     (spc_aclk),
                      .spc_bclk     (spc_bclk),
                      .ftu_cmiss        (ftu_cmiss[1]),          // Templated
                      .ftu_inv_req      (ftu_inv_req[1]),        // Templated
                      .lsc_l15_valid      (lsc_l15_valid[1]),        // Templated
                      .mct_fill_complete(mct_fill_complete[1]),  // Templated
                      .cmu_data_ready   (cmu_data_ready[1]),     // Templated
                      .cmu_has_dup_miss (cmu_has_dup_miss[1]),   // Templated
                      .cmu_mbhit_c      (cmu_mbhit_c),           // Templated
                      .ftu_redirect     (ftu_redirect[1]),       // Templated
                      .mct_rst_dupmiss  (mct_rst_dupmiss[1]),    // Templated
                      .mdp_mbhit_q      (mdp_mbhit_q[1]),        // Templated
                      .mct_ignore_cmiss (mct_ignore_cmiss));

ifu_cmu_csm_ctl csm2 (
                      /*AUTOINST*/
                      // Outputs
                      .csm_valid_req      (csm_valid_req[2]),        // Templated
                      .cmu_null_st(cmu_null_st[2]),  // Templated
                      .cmu_req_st(cmu_req_st[2]),  // Templated
                      .cmu_canleave_st(cmu_canleave_st[2]),  // Templated
                      .cmu_dupmiss_st(cmu_dupmiss_st[2]),  // Templated
                      // Inputs
                      .scan_in(csm2_scanin),
                      .scan_out(csm2_scanout),
                      .l1clk            (l1clk),
                      .spc_aclk     (spc_aclk),
                      .spc_bclk     (spc_bclk),
                      .ftu_cmiss        (ftu_cmiss[2]),          // Templated
                      .ftu_inv_req      (ftu_inv_req[2]),        // Templated
                      .lsc_l15_valid      (lsc_l15_valid[2]),        // Templated
                      .mct_fill_complete(mct_fill_complete[2]),  // Templated
                      .cmu_data_ready   (cmu_data_ready[2]),     // Templated
                      .cmu_has_dup_miss (cmu_has_dup_miss[2]),   // Templated
                      .cmu_mbhit_c      (cmu_mbhit_c),           // Templated
                      .ftu_redirect     (ftu_redirect[2]),       // Templated
                      .mct_rst_dupmiss  (mct_rst_dupmiss[2]),    // Templated
                      .mdp_mbhit_q      (mdp_mbhit_q[2]),        // Templated
                      .mct_ignore_cmiss (mct_ignore_cmiss));

ifu_cmu_csm_ctl csm3 (
                      /*AUTOINST*/
                      // Outputs
                      .csm_valid_req      (csm_valid_req[3]),        // Templated
                      .cmu_null_st(cmu_null_st[3]),  // Templated
                      .cmu_req_st(cmu_req_st[3]),  // Templated
                      .cmu_canleave_st(cmu_canleave_st[3]),  // Templated
                      .cmu_dupmiss_st(cmu_dupmiss_st[3]),  // Templated
                      // Inputs
                      .scan_in(csm3_scanin),
                      .scan_out(csm3_scanout),
                      .l1clk            (l1clk),
                      .spc_aclk     (spc_aclk),
                      .spc_bclk     (spc_bclk),
                      .ftu_cmiss        (ftu_cmiss[3]),          // Templated
                      .ftu_inv_req      (ftu_inv_req[3]),        // Templated
                      .lsc_l15_valid      (lsc_l15_valid[3]),        // Templated
                      .mct_fill_complete(mct_fill_complete[3]),  // Templated
                      .cmu_data_ready   (cmu_data_ready[3]),     // Templated
                      .cmu_has_dup_miss (cmu_has_dup_miss[3]),   // Templated
                      .cmu_mbhit_c      (cmu_mbhit_c),           // Templated
                      .ftu_redirect     (ftu_redirect[3]),       // Templated
                      .mct_rst_dupmiss  (mct_rst_dupmiss[3]),    // Templated
                      .mdp_mbhit_q      (mdp_mbhit_q[3]),        // Templated
                      .mct_ignore_cmiss (mct_ignore_cmiss));

ifu_cmu_csm_ctl csm4 (
                      /*AUTOINST*/
                      // Outputs
                      .csm_valid_req      (csm_valid_req[4]),        // Templated
                      .cmu_null_st(cmu_null_st[4]),  // Templated
                      .cmu_req_st(cmu_req_st[4]),  // Templated
                      .cmu_canleave_st(cmu_canleave_st[4]),  // Templated
                      .cmu_dupmiss_st(cmu_dupmiss_st[4]),  // Templated
                      // Inputs
                      .scan_in(csm4_scanin),
                      .scan_out(csm4_scanout),
                      .l1clk            (l1clk),
                      .spc_aclk     (spc_aclk),
                      .spc_bclk     (spc_bclk),
                      .ftu_cmiss        (ftu_cmiss[4]),          // Templated
                      .ftu_inv_req      (ftu_inv_req[4]),        // Templated
                      .lsc_l15_valid      (lsc_l15_valid[4]),        // Templated
                      .mct_fill_complete(mct_fill_complete[4]),  // Templated
                      .cmu_data_ready   (cmu_data_ready[4]),     // Templated
                      .cmu_has_dup_miss (cmu_has_dup_miss[4]),   // Templated
                      .cmu_mbhit_c      (cmu_mbhit_c),           // Templated
                      .ftu_redirect     (ftu_redirect[4]),       // Templated
                      .mct_rst_dupmiss  (mct_rst_dupmiss[4]),    // Templated
                      .mdp_mbhit_q      (mdp_mbhit_q[4]),        // Templated
                      .mct_ignore_cmiss (mct_ignore_cmiss));

ifu_cmu_csm_ctl csm5 (
                      /*AUTOINST*/
                      // Outputs
                      .csm_valid_req      (csm_valid_req[5]),        // Templated
                      .cmu_null_st(cmu_null_st[5]),  // Templated
                      .cmu_req_st(cmu_req_st[5]),  // Templated
                      .cmu_canleave_st(cmu_canleave_st[5]),  // Templated
                      .cmu_dupmiss_st(cmu_dupmiss_st[5]),  // Templated
                      // Inputs
                      .scan_in(csm5_scanin),
                      .scan_out(csm5_scanout),
                      .l1clk            (l1clk),
                      .spc_aclk     (spc_aclk),
                      .spc_bclk     (spc_bclk),
                      .ftu_cmiss        (ftu_cmiss[5]),          // Templated
                      .ftu_inv_req      (ftu_inv_req[5]),        // Templated
                      .lsc_l15_valid      (lsc_l15_valid[5]),        // Templated
                      .mct_fill_complete(mct_fill_complete[5]),  // Templated
                      .cmu_data_ready   (cmu_data_ready[5]),     // Templated
                      .cmu_has_dup_miss (cmu_has_dup_miss[5]),   // Templated
                      .cmu_mbhit_c      (cmu_mbhit_c),           // Templated
                      .ftu_redirect     (ftu_redirect[5]),       // Templated
                      .mct_rst_dupmiss  (mct_rst_dupmiss[5]),    // Templated
                      .mdp_mbhit_q      (mdp_mbhit_q[5]),        // Templated
                      .mct_ignore_cmiss (mct_ignore_cmiss));

ifu_cmu_csm_ctl csm6 (
                      /*AUTOINST*/
                      // Outputs
                      .csm_valid_req      (csm_valid_req[6]),        // Templated
                      .cmu_null_st(cmu_null_st[6]),  // Templated
                      .cmu_req_st(cmu_req_st[6]),  // Templated
                      .cmu_canleave_st(cmu_canleave_st[6]),  // Templated
                      .cmu_dupmiss_st(cmu_dupmiss_st[6]),  // Templated
                      // Inputs
                      .scan_in(csm6_scanin),
                      .scan_out(csm6_scanout),
                      .l1clk            (l1clk),
                      .spc_aclk     (spc_aclk),
                      .spc_bclk     (spc_bclk),
                      .ftu_cmiss        (ftu_cmiss[6]),          // Templated
                      .ftu_inv_req      (ftu_inv_req[6]),        // Templated
                      .lsc_l15_valid      (lsc_l15_valid[6]),        // Templated
                      .mct_fill_complete(mct_fill_complete[6]),  // Templated
                      .cmu_data_ready   (cmu_data_ready[6]),     // Templated
                      .cmu_has_dup_miss (cmu_has_dup_miss[6]),   // Templated
                      .cmu_mbhit_c      (cmu_mbhit_c),           // Templated
                      .ftu_redirect     (ftu_redirect[6]),       // Templated
                      .mct_rst_dupmiss  (mct_rst_dupmiss[6]),    // Templated
                      .mdp_mbhit_q      (mdp_mbhit_q[6]),        // Templated
                      .mct_ignore_cmiss (mct_ignore_cmiss));

ifu_cmu_csm_ctl csm7 (
                      /*AUTOINST*/
                      // Outputs
                      .csm_valid_req      (csm_valid_req[7]),        // Templated
                      .cmu_null_st(cmu_null_st[7]),  // Templated
                      .cmu_req_st(cmu_req_st[7]),  // Templated
                      .cmu_canleave_st(cmu_canleave_st[7]),  // Templated
                      .cmu_dupmiss_st(cmu_dupmiss_st[7]),  // Templated
                      // Inputs
                      .scan_in(csm7_scanin),
                      .scan_out(csm7_scanout),
                      .l1clk            (l1clk),
                      .spc_aclk     (spc_aclk),
                      .spc_bclk     (spc_bclk),
                      .ftu_cmiss        (ftu_cmiss[7]),          // Templated
                      .ftu_inv_req      (ftu_inv_req[7]),        // Templated
                      .lsc_l15_valid      (lsc_l15_valid[7]),        // Templated
                      .mct_fill_complete(mct_fill_complete[7]),  // Templated
                      .cmu_data_ready   (cmu_data_ready[7]),     // Templated
                      .cmu_has_dup_miss (cmu_has_dup_miss[7]),   // Templated
                      .cmu_mbhit_c      (cmu_mbhit_c),           // Templated
                      .ftu_redirect     (ftu_redirect[7]),       // Templated
                      .mct_rst_dupmiss  (mct_rst_dupmiss[7]),    // Templated
                      .mdp_mbhit_q      (mdp_mbhit_q[7]),        // Templated
                      .mct_ignore_cmiss (mct_ignore_cmiss));


////////////////////////////////////////////////////////
// SPARE CELLS
////////////////////////////////////////////////////////
ifu_cmu_cmt_ctl_spare_ctl_macro__num_1 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
////////////////////////////////////////////////////////

supply0 vss;
supply1 vdd;
// fixscan start:
assign csm0_scanin               = scan_in                  ;
assign csm1_scanin               = csm0_scanout             ;
assign csm2_scanin               = csm1_scanout             ;
assign csm3_scanin               = csm2_scanout             ;
assign csm4_scanin               = csm3_scanout             ;
assign csm5_scanin               = csm4_scanout             ;
assign csm6_scanin               = csm5_scanout             ;
assign csm7_scanin               = csm6_scanout             ;
assign spares_scanin             = csm7_scanout             ;
assign scan_out                  = spares_scanout           ;

// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


// any PARAMS parms go into naming of macro

module ifu_cmu_cmt_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_cmt_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_cmu_cmt_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_cmu_csm_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_cmu_csm_ctl (
  l1clk, 
  scan_in, 
  spc_aclk, 
  spc_bclk, 
  ftu_cmiss, 
  ftu_redirect, 
  ftu_inv_req, 
  lsc_l15_valid, 
  mct_fill_complete, 
  cmu_data_ready, 
  cmu_has_dup_miss, 
  cmu_mbhit_c, 
  mct_rst_dupmiss, 
  mct_ignore_cmiss, 
  mdp_mbhit_q, 
  csm_valid_req, 
  cmu_null_st, 
  cmu_dupmiss_st, 
  cmu_req_st, 
  cmu_canleave_st, 
  scan_out) ;
wire siclk;
wire soclk;
wire inv_req_reg_scanin;
wire inv_req_reg_scanout;
wire inv_req_ff;
wire redirect_reg_scanin;
wire redirect_reg_scanout;
wire ftu_redirect_lat;
wire go_to_null_state;
wire null_state;
wire req_state;
wire canleave_state;
wire fillwait_state;
wire dupmiss_state;
wire invreq_state;
wire next_null_state_;
wire null_state_;
wire null_state_reg_scanin;
wire null_state_reg_scanout;
wire go_to_req_state;
wire next_req_state;
wire req_state_reg_scanin;
wire req_state_reg_scanout;
wire go_to_canleave_state;
wire next_canleave_state;
wire canleave_state_reg_scanin;
wire canleave_state_reg_scanout;
wire go_to_retwait_state;
wire retwait_state;
wire next_retwait_state;
wire retwait_state_reg_scanin;
wire retwait_state_reg_scanout;
wire go_to_fillwait_state;
wire next_fillwait_state;
wire fillwait_state_reg_scanin;
wire fillwait_state_reg_scanout;
wire go_to_dupmiss_state;
wire next_dupmiss_state;
wire dupmiss_state_reg_scanin;
wire dupmiss_state_reg_scanout;
wire go_to_invreq_state;
wire next_invreq_state;
wire invreq_state_reg_scanin;
wire invreq_state_reg_scanout;


input l1clk;
input scan_in;
input spc_aclk;
input spc_bclk;

input ftu_cmiss;            // cmiss request
input ftu_redirect;         // indicates the thread is flushed/redirected
input ftu_inv_req;          // invalidation request
input lsc_l15_valid;        // req sent to gkt
input mct_fill_complete;    // indicates that fill has been completed

input cmu_data_ready;       // gkt rtn data and is ready to be written to I$
input cmu_has_dup_miss;     // from MB ctl logic, current thread has outstanding duplicate miss.
input cmu_mbhit_c;          // from MB ctl logic, current thread hits in missbuff, it is not real miss

input mct_rst_dupmiss;      // comes on with data_ready, all dup miss waiting on current thread are reset.
input mct_ignore_cmiss;     // current cmiss is a duplicate miss which needs to be ignored, data sent to I$.
input mdp_mbhit_q;          // A qualified mbhit


output csm_valid_req;         // valid request indicator
output cmu_null_st;
output    cmu_dupmiss_st;
output    cmu_req_st;
output    cmu_canleave_st;

   
output scan_out;

// scan renames
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan


// flop inv_req.
// It means that inv_req will not take part in arbitration for
// two cycles after it arrives.
ifu_cmu_csm_ctl_msff_ctl_macro__width_1 inv_req_reg  (
 .scan_in(inv_req_reg_scanin),
 .scan_out(inv_req_reg_scanout),
 .l1clk(l1clk),
 .din  (ftu_inv_req),
 .dout (inv_req_ff),
  .siclk(siclk),
  .soclk(soclk)
);

// flop ftu_redirect
// use the delayed version for qualifying valid req.
// clearing of wom bits in mct should also use delayed version.
// use raw version to clear dup miss states

ifu_cmu_csm_ctl_msff_ctl_macro__width_1 redirect_reg  (
 .scan_in(redirect_reg_scanin),
 .scan_out(redirect_reg_scanout),
 .l1clk(l1clk),
 .din  (ftu_redirect),
 .dout (ftu_redirect_lat),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// CASE STATEMENT DESCRIPTION OF TSM MACHINE
///////////////////////////////////////////////////
//case(`CSM_STATE)
//  `NULL_ST:
//    if (~(ftu_cmiss & ~mct_ignore_cmiss) & ~inv_req_ff)
//      next_state = `NULL_ST;
//    if (ftu_cmiss & ~cmu_mbhit_c)
//      next_state = `REQ_ST;
//    if (ftu_cmiss & cmu_mbhit_c & ~ignore_cmiss)
//      next_state = `DUPMISS_ST;
//    if (inv_req_ff)
//      next_state = `INVREQ_ST;
//
//  `REQ_ST:
//    if (lsc_l15_valid)
//      next_state = `RETWAIT_ST;
//    if (~lsc_l15_valid & ftu_redirect_lat & cmu_has_dup_miss)
//      next_state = `CANLEAVE_ST;
//    if (~lsc_l15_valid & ftu_redirect_lat & ~cmu_has_dup_miss & mdp_mbhit_q)
//      next_state = `CANLEAVE_ST;
//    if (~lsc_l15_valid & ftu_redirect_lat & ~cmu_has_dup_miss & ~mdp_mbhit_q)
//      next_state = `NULL_ST;
//    if (~lsc_l15_valid & ~ftu_redirect_lat)
//      next_state = `REQ_ST;
//
//  `CANLEAVE_ST:
//    if (lsc_l15_valid)
//      next_state = `RETWAIT_ST;
//    if (~lsc_l15_valid & ~cmu_has_dup_miss & ~mdp_mbhit_q)
//      next_state = `NULL_ST;
//    if (~lsc_l15_valid & cmu_has_dup_miss)
//      next_state = `CANLEAVE_ST;
//    if (~lsc_l15_valid & mdp_mbhit_q)
//      next_state = `CANLEAVE_ST;
//
//  `RETWAIT_ST:
//    if (~cmu_data_ready)
//      next_state = `RETWAIT_ST;
//    if (cmu_data_ready)
//      next_state = `FILLWAIT_ST;
//
//  `FILLWAIT_ST:
//    if (~mct_fill_complete)
//      next_state = `FILLWAIT_ST;
//    if (mct_fill_complete)
//      next_state = `NULL_ST;
//
//  `DUPMISS_ST:
//    if (~ftu_redirect & ~mct_rst_dupmiss)
//      next_state = `DUPMISS_ST;
//    if (ftu_redirect | mct_rst_dupmiss)
//      next_state = `NULL_ST;
//
//  `INVREQ_ST:
//    if (lsc_l15_valid)
//      next_state = `NULL_ST;
//    if (~lsc_l15_valid)
//      next_state = `INVREQ_ST;
//
// endcase
//
// 

// 0in one_hot -var {null_state,req_state,canleave_state,retwait_state,fillwait_state,dupmiss_state,invreq_state}
////////////////////////////////////////////////////////
// NULL STATE
////////////////////////////////////////////////////////
// cmu_mbhit_c indicates a duplicate miss
// ignore_cmiss indicates a duplicate miss which needs to be ignored
//
// null_st is default state.
// 
assign go_to_null_state = (null_state & ~(ftu_cmiss & ~mct_ignore_cmiss) & ~inv_req_ff)  | 
                          (req_state & ~lsc_l15_valid & ftu_redirect_lat & ~cmu_has_dup_miss & ~mdp_mbhit_q) |
                          (canleave_state & ~lsc_l15_valid & ~cmu_has_dup_miss & ~mdp_mbhit_q) |
                          (fillwait_state & mct_fill_complete)  |
                          (dupmiss_state & (ftu_redirect | mct_rst_dupmiss)) |
                          (invreq_state & lsc_l15_valid);

assign next_null_state_ = ~go_to_null_state;

assign null_state       = ~null_state_;

ifu_cmu_csm_ctl_msff_ctl_macro__width_1 null_state_reg  (
 .scan_in(null_state_reg_scanin),
 .scan_out(null_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_null_state_),
 .dout (null_state_),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////
// REQUEST STATE
////////////////////////////////////////////////////////
// Go to request state on a real miss
// Stay in request state until the request is sent out or redirect.
assign go_to_req_state  = (null_state & ftu_cmiss & ~cmu_mbhit_c) | 
                          (req_state & ~lsc_l15_valid & ~ftu_redirect_lat) ;

assign next_req_state   = go_to_req_state;

ifu_cmu_csm_ctl_msff_ctl_macro__width_1 req_state_reg  (
 .scan_in(req_state_reg_scanin),
 .scan_out(req_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_req_state),
 .dout (req_state),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////
// CANLEAVE STATE
////////////////////////////////////////////////////////
// Go to canleave_st when a real miss is flushed, but it has
// other outstanding duplicate misses waiting on it.
// Leave canleave_st when the request is sent out, or it has no
// other duplicate misses waiting on it (This can happen if
// all duplicate misses get flushed out).
assign go_to_canleave_state = (req_state & ftu_redirect_lat & cmu_has_dup_miss & ~lsc_l15_valid) |
                              (req_state & ftu_redirect_lat & mdp_mbhit_q & ~lsc_l15_valid) |
                              (canleave_state & cmu_has_dup_miss & ~lsc_l15_valid) |
                              (canleave_state & mdp_mbhit_q & ~lsc_l15_valid);

assign next_canleave_state = go_to_canleave_state;

ifu_cmu_csm_ctl_msff_ctl_macro__width_1 canleave_state_reg  (
 .scan_in(canleave_state_reg_scanin),
 .scan_out(canleave_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_canleave_state),
 .dout (canleave_state),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////
// Return Wait State
////////////////////////////////////////////////////////
// Go to return wait state when a request is sent to gkt/xbar.
// Stay in this state until data comes back and data_ready is
// signalled to ifu.
assign go_to_retwait_state  = (req_state & lsc_l15_valid) | 
                              (canleave_state & lsc_l15_valid) |
                              (retwait_state & ~cmu_data_ready);

assign next_retwait_state   = go_to_retwait_state;


ifu_cmu_csm_ctl_msff_ctl_macro__width_1 retwait_state_reg  (
 .scan_in(retwait_state_reg_scanin),
 .scan_out(retwait_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_retwait_state),
 .dout (retwait_state),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////
// Fill Wait State
////////////////////////////////////////////////////////
// Fillwait_st indicates that data_ready has been sent, wait
// until fill_complete is  signalled by ifu
assign go_to_fillwait_state = (retwait_state & cmu_data_ready ) | 
                              (fillwait_state & ~mct_fill_complete);
assign next_fillwait_state  = go_to_fillwait_state;

ifu_cmu_csm_ctl_msff_ctl_macro__width_1 fillwait_state_reg  (
 .scan_in(fillwait_state_reg_scanin),
 .scan_out(fillwait_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_fillwait_state),
 .dout (fillwait_state),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////
// DupMiss State
////////////////////////////////////////////////////////
// go to dupmiss_st on a dup miss.
assign go_to_dupmiss_state = (null_state & ftu_cmiss & cmu_mbhit_c & ~mct_ignore_cmiss) |
                             (dupmiss_state & ~ftu_redirect & ~mct_rst_dupmiss);

assign next_dupmiss_state = go_to_dupmiss_state;

ifu_cmu_csm_ctl_msff_ctl_macro__width_1 dupmiss_state_reg  (
 .scan_in(dupmiss_state_reg_scanin),
 .scan_out(dupmiss_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_dupmiss_state),
 .dout (dupmiss_state),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////
// INVREQ STATE
////////////////////////////////////////////////////////
// go to invreq state on a invalidation request.
assign go_to_invreq_state = (null_state & inv_req_ff) |
                            (invreq_state & ~lsc_l15_valid);

assign next_invreq_state = go_to_invreq_state;

ifu_cmu_csm_ctl_msff_ctl_macro__width_1 invreq_state_reg  (
 .scan_in(invreq_state_reg_scanin),
 .scan_out(invreq_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_invreq_state),
 .dout (invreq_state),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////
// State Machine output signals
////////////////////////////////////////////////////////
// csm_valid_req indicates that a valid request exists which
// takes part in arbitration
// If a request was sent out previous cycle, then the thread
// will still be in REQ state this cycle. Validreq will still come
// on for this thread, but it will get killed in lsi_ctl before
// it takes part in arbitration.

// To ease timing, mbhit_q is not used to generate the valid req.
// valid_req comes on if
//  1. in req state, and no flush or has_dup_miss.
//     if a flush happens and there are no dup misses, then the thread
//     will not take part in arb, even though a new dup miss could be
//     happening at the same time. The new dup miss will show up in
//     can_leave state the next cycle.
// 2.  in canleave state and has_dup_miss. Again, if in canleave state
//     and no dup miss, then thread will not take part in arb even though
//     a dup miss could be happening in same cycle. The dup miss will
//     force the state the stay in can_leave and it will set the has_dup
//     signal next cycle. So the thread will take part in arb next cycle.
// 3.  In inv_req state.


assign csm_valid_req = (req_state & ~(ftu_redirect_lat & ~cmu_has_dup_miss)) |
                       (canleave_state & cmu_has_dup_miss) |
                       (invreq_state);  


// cmu_cmiss_is_sent
// Indicates that a request has been sent.
// This signal serves two purposes:
// 1. used in conjunction with has_dup_miss in msb_ctl and ifu_ftu to
//    qualify missbuffer hits.
//    If a parent thread has not been sent, and it has a redirect, and
//    it does not have other dup misses outstanding, then an incoming
//    thread cannot hit on it.
// 2. Used by ifu to get out of no_new_miss state.
//assign cmu_cmiss_is_sent = lsc_l15_valid | retwait_state | fillwait_state;

// wom_valid bit for each thread comes on when the thread is in dupmiss_st or the req
// has been sent and thread has not been redirected.
// wom_valid is used to qualify bypass for the thread. 
// Bypass to a thread only if its wom_valid bit is set.
// dup WOM bit is not reset if there is redirect and req. is already sent. In this scenario,
// bypass is not valid. Hence generating this wom_valid signal to ignore the wom bit.

//assign csm_wom_valid = ~null_state & ~reqredirect_state ;

assign cmu_null_st = null_state;
assign cmu_dupmiss_st = dupmiss_state;
assign cmu_req_st = req_state;
assign cmu_canleave_st = canleave_state;

   
supply0 vss;
supply1 vdd;
// fixscan start:
assign inv_req_reg_scanin        = scan_in                  ;
assign redirect_reg_scanin       = inv_req_reg_scanout      ;
assign null_state_reg_scanin     = redirect_reg_scanout     ;
assign req_state_reg_scanin      = null_state_reg_scanout   ;
assign canleave_state_reg_scanin = req_state_reg_scanout    ;
assign retwait_state_reg_scanin  = canleave_state_reg_scanout;
assign fillwait_state_reg_scanin = retwait_state_reg_scanout;
assign dupmiss_state_reg_scanin  = fillwait_state_reg_scanout;
assign invreq_state_reg_scanin   = dupmiss_state_reg_scanout;
assign scan_out                  = invreq_state_reg_scanout ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_csm_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_cmu_lsi_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_cmu_lsi_ctl (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  const_cpuid, 
  mct_early_req, 
  ftu_cmiss, 
  ftu_rep_way, 
  ftu_thrx_un_cacheable, 
  ifu_l15_addr, 
  csm_valid_req, 
  l15_spc_data1, 
  l15_spc_cpkt, 
  l15_ifu_valid, 
  l15_ifu_grant, 
  lsu_ifu_ld_index, 
  cmu_fill_paddr, 
  mdp_lsi_nc_bit, 
  mdp_lsi_inv_bit, 
  mdp_lsi_rway, 
  lsu_ifu_cmu_pmen, 
  lsc_fill_rtn1, 
  lsc_fill_rtn2, 
  lsc_req_sel, 
  lsc_pending_req, 
  lsc_l15_valid, 
  lsc_data_sel, 
  cmu_any_data_ready, 
  cmu_any_un_cacheable, 
  cmu_data_ready, 
  cmu_inst0_v, 
  cmu_inst1_v, 
  cmu_inst2_v, 
  cmu_inst3_v, 
  cmu_icache_invalidate, 
  cmu_icache_invalidate_way, 
  cmu_icache_invalidate_index, 
  cmu_evic_invalidate, 
  cmu_icache_inv_way1, 
  cmu_inval_ack, 
  cmu_l2_err, 
  cmu_l2miss, 
  ifu_l15_valid, 
  ifu_l15_cpkt, 
  lsc_clken, 
  ifu_lsu_if_vld, 
  ifu_lsu_if_tid, 
  ifu_lsu_if_addr, 
  scan_out) ;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire go_to_l15_empty;
wire l15_one_buff_state;
wire l15_empty_state;
wire leave_l15_empty;
wire next_l15_empty;
wire next_l15_empty_;
wire empty_state_reg_scanin;
wire empty_state_reg_scanout;
wire l15_empty_state_;
wire go_to_l15_one_buff;
wire l15_hold_state;
wire leave_l15_one_buff;
wire next_l15_one_buff;
wire one_buff_state_reg_scanin;
wire one_buff_state_reg_scanout;
wire go_to_l15_hold;
wire leave_l15_hold;
wire next_l15_hold;
wire l15_hold_state_reg_scanin;
wire l15_hold_state_reg_scanout;
wire gkt_room_avail_in;
wire [7:0] csm_rqv;
wire lsc_early_req;
wire [2:0] req_sel_tid;
wire [2:0] cmiss_tid;
wire ifu_l15_valid_in;
wire [7:0] lsc_l15_valid_in;
wire [2:0] ifu_l15_tid_in;
wire [2:0] ifu_l15_rway_in;
wire ifu_l15_nc_in;
wire ifu_l15_inv_in;
wire tg0_selected_in;
wire tg1_selected_in;
wire ifu_l15_valid_reg_scanin;
wire ifu_l15_valid_reg_scanout;
wire tg0_selected;
wire tg1_selected;
wire lsc_l15_valid_reg_scanin;
wire lsc_l15_valid_reg_scanout;
wire [7:0] lsc_l15_pre_valid;
wire lsc_req_sel_reg_scanin;
wire lsc_req_sel_reg_scanout;
wire [7:0] lsc_req_sel_lat;
wire lsc_cpkt_reg_scanin;
wire lsc_cpkt_reg_scanout;
wire [2:0] cpuid;
wire [2:0] ifu_l15_rway;
wire ifu_l15_nc;
wire ifu_l15_inv;
wire [2:0] ifu_l15_tid;
wire ifu_lsu_lat_scanin;
wire ifu_lsu_lat_scanout;
wire favor_tg1_in;
wire favor_tg1;
wire favour_bit_reg_scanin;
wire favour_bit_reg_scanout;
wire [3:0] thr_ptr0;
wire [3:0] thr_ptr0_lat;
wire thr_ptr0_lat_0_;
wire [7:4] thr_ptr1;
wire [7:4] thr_ptr1_lat;
wire thr_ptr1_lat_4_;
wire thr_ptr0_0_;
wire thr_ptr1_4_;
wire ptr0_reg_scanin;
wire ptr0_reg_scanout;
wire ptr1_reg_scanin;
wire ptr1_reg_scanout;
wire [7:0] req_bit;
wire tg0_valid;
wire tg1_valid;
wire sel_tg1;
wire reg_pmen_scanin;
wire reg_pmen_scanout;
wire ifu_pmen;
wire [3:0] l15_rtn_type;
wire fill_return;
wire cmu_nc_f4b;
wire second_pkt;
wire second_pkt_in;
wire sec_pkt_lat_scanin;
wire sec_pkt_lat_scanout;
wire [1:0] cmu_l2_err_pkt1_in;
wire stg_r1_lat0_scanin;
wire stg_r1_lat0_scanout;
wire [1:0] cmu_l2_err_pkt1;
wire cmu_l2miss_in;
wire cmu_inst0_v_in;
wire cmu_inst1_v_in;
wire cmu_inst2_v_in;
wire cmu_inst3_v_in;
wire cmu_inst_reg_scanin;
wire cmu_inst_reg_scanout;
wire [31:0] store_inval_vector;
wire [31:0] evic_inv_vec_0;
wire [31:0] evic_inv_vec_1;
wire take_strm_store_ack;
wire take_store_ack;
wire take_inval_ack;
wire take_load_return;
wire take_evic_inv;
wire [7:0] cmu_inval_ack_din;
wire [3:0] inv_vector;
wire evic_i_inv_0_true;
wire [2:0] evic_inv_way0;
wire evic_i_inv_1_true;
wire [2:0] evic_inv_way1;
wire str_strm_invalidate;
wire cross_invalidate;
wire evic_invalidate_w0;
wire evic_invalidate_w1;
wire evic_invalidate_w01;
wire evic_invalidate_any;
wire [2:0] evic_way0;
wire [10:5] evic_index;
wire cmu_icache_invalidate_din;
wire [2:0] cmu_icache_invalidate_way_din;
wire [10:5] cmu_icache_invalidate_index_din;
wire cmu_evic_invalidate_din;
wire [2:0] cmu_icache_inv_way1_din;
wire stg_r1_lat_scanin;
wire stg_r1_lat_scanout;
wire [23:0] l15_spc_data_55_32_unused;
wire [15:0] l15_spc_data_111_96_unused;
wire [4:0] l15_spc_data_121_117_unused;
wire [2:0] l15_spc_data_127_125_unused;
wire [1:0] l15_spc_cpkt_1_0_unused;
wire l15_spc_cpkt_13_unused;
wire spares_so_0;
wire spares_scanout;
wire spares_scanin;
wire out;
wire q;


input tcu_scan_en ;
input l2clk;
input scan_in;
input tcu_pce_ov;               // scan signals
input spc_aclk;
input spc_bclk;

input [2:0]   const_cpuid;
input mct_early_req;
input [7:0] ftu_cmiss;                //from ftu tsm
input [2:0]   ftu_rep_way;            // incoming replacement way from ftu
input         ftu_thrx_un_cacheable;  // incoming cacheable bit from ftu


input [10:5]  ifu_l15_addr;
input [7:0]   csm_valid_req;


input [127:0] l15_spc_data1;
input [17:0]  l15_spc_cpkt;
input         l15_ifu_valid;
input         l15_ifu_grant;           //ACK from gkt when req is accepted

input [10:5]  lsu_ifu_ld_index;        // on a load retn, lsu sends load index for cross invalidates, 

input [4:2]   cmu_fill_paddr;      //bits {4,3,2} of the fill phys addr

input         mdp_lsi_nc_bit;          // Cacheable bit from Missbuffer
input         mdp_lsi_inv_bit;         // Inv req bit from Missbuffer
input [2:0]   mdp_lsi_rway;            // way information from missbuffer

input         lsu_ifu_cmu_pmen;


output        lsc_fill_rtn1;            //enable for fill ready data to lsi_dp
output        lsc_fill_rtn2;            //enable for fill ready data to lsi_dp
output [7:0]  lsc_req_sel;              // selected thread from pending requests
output        lsc_pending_req;
output [7:0]  lsc_l15_valid;             //req for thr0 ACKed by LSU, to TSM (indicates req accepted)

output [7:0]  lsc_data_sel;            // decoded selects for muxing out instructions


output        cmu_any_data_ready;
output        cmu_any_un_cacheable;

output [7:0]  cmu_data_ready;          //data ready for thr0

output        cmu_inst0_v;          // valid for instruction 0
output        cmu_inst1_v;          // valid for instruction 1
output        cmu_inst2_v;          // valid for instruction 2
output        cmu_inst3_v;          // valid for instruction 3

output        cmu_icache_invalidate;                     //invalidate icache request
output [2:0]  cmu_icache_invalidate_way;          
output [10:5] cmu_icache_invalidate_index;

output        cmu_evic_invalidate;                      // eviction invalidation
output [2:0]  cmu_icache_inv_way1;

output [7:0]  cmu_inval_ack;
output [1:0]  cmu_l2_err;
output        cmu_l2miss;                              // l2miss indicator on rtn pkt

output        ifu_l15_valid;             // ifu_l15_valid, valid pcx pkt
output [7:0] ifu_l15_cpkt;

output        lsc_clken;

// **** LSU Interface ****
output        ifu_lsu_if_vld;
output [2:0]  ifu_lsu_if_tid;
output [10:5] ifu_lsu_if_addr;

output        scan_out;


// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
assign se = tcu_scan_en ;
// end scan


///////////////////////////////////////////////////
// clock header
///////////////////////////////////////////////////
ifu_cmu_lsi_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

/////////////////////////////////////////////////////////
// Create a state_machine to keep track of L15 buffers //
/////////////////////////////////////////////////////////
// Empty state: L15 has both IFU buffers empty. IFU    //
// can send two requests back to back.                 //
/////////////////////////////////////////////////////////
assign go_to_l15_empty = (l15_one_buff_state & l15_ifu_grant & ~ifu_l15_valid) | 
                         (l15_empty_state    & ~ifu_l15_valid) ;
assign leave_l15_empty = (l15_empty_state    &  ifu_l15_valid) ;

assign next_l15_empty = (go_to_l15_empty & ~leave_l15_empty) ;
assign next_l15_empty_ = ~next_l15_empty ;

ifu_cmu_lsi_ctl_msff_ctl_macro__width_1 empty_state_reg  (
 .scan_in(empty_state_reg_scanin),
 .scan_out(empty_state_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_l15_empty_),
 .dout (l15_empty_state_),
  .siclk(siclk),
  .soclk(soclk)
);

assign l15_empty_state = ~l15_empty_state_ ;

/////////////////////////////////////////////////////////
// One buffer state: L15 has one buffer empty. We can  //
// send only one more request before we get grants.    //
/////////////////////////////////////////////////////////
assign go_to_l15_one_buff = (l15_hold_state  & l15_ifu_grant & ~ifu_l15_valid)     |  // Coming back from hold state
                            (l15_empty_state & ifu_l15_valid)                      |  // Coming from empty state
                            (l15_one_buff_state & ~ifu_l15_valid & ~l15_ifu_grant) |  // Nothing happened: stay in this state
                            (l15_one_buff_state &  ifu_l15_valid &  l15_ifu_grant) ;  // Request accepted and new one issued

assign leave_l15_one_buff = (l15_one_buff_state &  l15_ifu_grant & ~ifu_l15_valid) |
                            (l15_one_buff_state & ~l15_ifu_grant &  ifu_l15_valid) ;                         

assign next_l15_one_buff = go_to_l15_one_buff & ~leave_l15_one_buff ;

ifu_cmu_lsi_ctl_msff_ctl_macro__width_1 one_buff_state_reg  (
 .scan_in(one_buff_state_reg_scanin),
 .scan_out(one_buff_state_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_l15_one_buff),
 .dout (l15_one_buff_state),
  .siclk(siclk),
  .soclk(soclk)
);

/////////////////////////////////////////////////////////
// Hold state: L15 has no more room for IFU requests.  //
// Do not send any more requests until l15_ifu_grant is//
// recieved.                                           //
/////////////////////////////////////////////////////////
assign go_to_l15_hold = (l15_one_buff_state & ifu_l15_valid & ~l15_ifu_grant) |
                        (l15_hold_state     & ifu_l15_valid &  l15_ifu_grant) |
                        (l15_hold_state     & ~l15_ifu_grant) ;

assign leave_l15_hold = (l15_hold_state & ~ifu_l15_valid & l15_ifu_grant) ;

assign next_l15_hold  =  go_to_l15_hold & ~leave_l15_hold ;
ifu_cmu_lsi_ctl_msff_ctl_macro__width_1 l15_hold_state_reg  (
 .scan_in(l15_hold_state_reg_scanin),
 .scan_out(l15_hold_state_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_l15_hold),
 .dout (l15_hold_state),
  .siclk(siclk),
  .soclk(soclk)
);

// ok to send a request to gkt next cycle.
assign gkt_room_avail_in   = next_l15_empty | next_l15_one_buff ;

///////////////////////////////////////////////////
// Select request sent  to gkt.
// If there are no pending requests, and a new request is coming
// in this cycle, then the new request can be sent out to
// gasket next cycle (cycle after C stage).
// This is called "early_request".
// Only cmiss can be an early request. Inval req cannot be sent out
// early.
// If there are pending requests, then the pending request will
// have higher priority and it will get sent out.
// On reset, select_pending_req will be 0.
///////////////////////////////////////////////////

// Qualify the pending requests with the request sent last cycle.
// Thread remains in REQ_ST the cycle it is being launched to
// gkt.
// We do not want it to take part in arbitration again.

//0in bits_on -var {lsc_l15_valid_in[7:0]} -max 1

assign csm_rqv[7:0] = csm_valid_req[7:0] & ~lsc_l15_valid[7:0] ; 

assign lsc_pending_req = |(csm_rqv[7:0]);
assign lsc_early_req = mct_early_req;

assign req_sel_tid[0] = lsc_req_sel[1] | lsc_req_sel[3] | lsc_req_sel[5] | lsc_req_sel[7];
assign req_sel_tid[1] = lsc_req_sel[2] | lsc_req_sel[3] | lsc_req_sel[6] | lsc_req_sel[7];
assign req_sel_tid[2] = lsc_req_sel[4] | lsc_req_sel[5] | lsc_req_sel[6] | lsc_req_sel[7];

assign cmiss_tid[0] = ftu_cmiss[1] | ftu_cmiss[3] | ftu_cmiss[5] | ftu_cmiss[7];
assign cmiss_tid[1] = ftu_cmiss[2] | ftu_cmiss[3] | ftu_cmiss[6] | ftu_cmiss[7];
assign cmiss_tid[2] = ftu_cmiss[4] | ftu_cmiss[5] | ftu_cmiss[6] | ftu_cmiss[7];

assign ifu_l15_valid_in = (lsc_pending_req | lsc_early_req) & gkt_room_avail_in;

assign lsc_l15_valid_in[7:0] = ({8{lsc_pending_req }} & lsc_req_sel[7:0]) |
                               ({8{~lsc_pending_req}} & ftu_cmiss[7:0]);

assign ifu_l15_tid_in[2:0]  =  ({3{lsc_pending_req }} & req_sel_tid[2:0]) |
                               ({3{~lsc_pending_req}} & cmiss_tid[2:0]);

assign ifu_l15_rway_in[2:0] =  ({3{lsc_pending_req }} & mdp_lsi_rway[2:0]) |
                               ({3{~lsc_pending_req}} & ftu_rep_way[2:0]);

assign ifu_l15_nc_in = (lsc_pending_req  & mdp_lsi_nc_bit) |
                       (~lsc_pending_req & ftu_thrx_un_cacheable);

// inval req cannot be sent early
assign ifu_l15_inv_in = lsc_pending_req & mdp_lsi_inv_bit;

assign tg0_selected_in = |(lsc_req_sel[3:0]) & gkt_room_avail_in;
assign tg1_selected_in = |(lsc_req_sel[7:4]) & gkt_room_avail_in;

ifu_cmu_lsi_ctl_msff_ctl_macro__width_3 ifu_l15_valid_reg  (
 .scan_in(ifu_l15_valid_reg_scanin),
 .scan_out(ifu_l15_valid_reg_scanout),
 .l1clk( l1clk ),
 .din  ({ifu_l15_valid_in, tg0_selected_in, tg1_selected_in}),
 .dout ({ifu_l15_valid, tg0_selected, tg1_selected}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_lsi_ctl_msff_ctl_macro__width_8 lsc_l15_valid_reg  (
 .scan_in(lsc_l15_valid_reg_scanin),
 .scan_out(lsc_l15_valid_reg_scanout),
 .l1clk( l1clk ),
 .din  (lsc_l15_valid_in[7:0]),
 .dout (lsc_l15_pre_valid[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_lsi_ctl_msff_ctl_macro__width_8 lsc_req_sel_reg  (
 .scan_in(lsc_req_sel_reg_scanin),
 .scan_out(lsc_req_sel_reg_scanout),
 .l1clk( l1clk ),
 .din  (lsc_req_sel[7:0]),
 .dout (lsc_req_sel_lat[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_lsi_ctl_msff_ctl_macro__width_11 lsc_cpkt_reg  (
 .scan_in(lsc_cpkt_reg_scanin),
 .scan_out(lsc_cpkt_reg_scanout),
 .l1clk( l1clk ),
 .din  ({const_cpuid[2:0],  ifu_l15_rway_in[2:0], ifu_l15_nc_in, ifu_l15_inv_in, ifu_l15_tid_in[2:0]}),
 .dout ({cpuid[2:0], ifu_l15_rway[2:0], ifu_l15_nc, ifu_l15_inv, ifu_l15_tid[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsc_l15_valid[7:0] = lsc_l15_pre_valid[7:0] & {8{ifu_l15_valid}};

//assign ifu_l15_cpkt[25:0] = {ifu_l15_valid, ifu_l15_req_type[4:0], ifu_l15_nc, ifu_l15_cpuid[2:0], 
//                             ifu_l15_tid[2:0], ifu_l15_inv, ifu_l15_pf, ifu_l15_rway[2:0], ifu_l15_size[7:0]};

// Actual ifu_l15_cpkt has following fields
// ifu_l15_cpkt[25]   = ifu_l15_valid
// ifu_l15_cpkt[24:20] = ifu_l15_req_type[4:0] = 5'b10000
// ifu_l15_cpkt[19]   = ifu_l15_nc
// ifu_l15_cpkt[18:16] = ifu_l15_cpuid[2:0]
// ifu_l15_cpkt[15:13] = ifu_l15_tid[2:0]
// ifu_l15_cpkt[12]    = ifu_l15_inv
// ifu_l15_cpkt[11]    = ifu_l15_pf = 0
// ifu_l15_cpkt[10:8] = ifu_l15_rway[2:0]
// ifu_l15_cpkt[7:0] = ifu_l15_size[7:0] = 0

// ifu_l15_cpkt is compressed to 8 bits. gkt converts this to final ifu packet
assign ifu_l15_cpkt[7:0] = {ifu_l15_nc, ifu_l15_inv, ifu_l15_rway[2:0], ifu_l15_tid[2:0]};


///////////////////////////////////////////////////
// Generating following signals for LSU cross_invalidate
///////////////////////////////////////////////////
ifu_cmu_lsi_ctl_msff_ctl_macro__width_10 ifu_lsu_lat  (
 .scan_in(ifu_lsu_lat_scanin),
 .scan_out(ifu_lsu_lat_scanout),
 .l1clk( l1clk ),
 .din  ({ifu_l15_valid,
         ifu_l15_tid[2:0],
         ifu_l15_addr[10:5]}),
 .dout ({ifu_lsu_if_vld,
         ifu_lsu_if_tid[2:0],
         ifu_lsu_if_addr[10:5]}),
  .siclk(siclk),
  .soclk(soclk)
);


///////////////////////////////////////////////////
// Logic for selecting pending request
///////////////////////////////////////////////////
// Thread are divided into two groups.
// A single favor bit will select alternatingly between the 2 groups.
// Within a group, the threads will be prioritized based on a 4-bit rotating pointer.
// The pointer always points to the thread with highest priority, and it gets updated
// when a thread gets selected. The pointer updates such that the selected thread will
// have the least priority.

// The group is selected based on a favor bit.
// The favor bit is updated based on what was selected last cycle

assign favor_tg1_in = (favor_tg1 & ~tg1_selected) | tg0_selected;

ifu_cmu_lsi_ctl_msff_ctl_macro__width_1 favour_bit_reg  (
 .scan_in(favour_bit_reg_scanin),
 .scan_out(favour_bit_reg_scanout),
 .l1clk( l1clk ),
 .din  (favor_tg1_in),
 .dout (favor_tg1),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// Form the rotating pointer used to prioritize among threads
// The pointer is updated when a thread group is selected, in a way that
// gives the selected thread the least priority
///////////////////////////////////////////////////
assign thr_ptr0[3:0] = tg0_selected ? ({lsc_req_sel_lat[2:0],lsc_req_sel_lat[3]}): {thr_ptr0_lat[3:1],thr_ptr0_lat_0_};
assign thr_ptr1[7:4] = tg1_selected ? ({lsc_req_sel_lat[6:4],lsc_req_sel_lat[7]}): {thr_ptr1_lat[7:5],thr_ptr1_lat_4_};

assign thr_ptr0_0_ = ~thr_ptr0[0];
assign thr_ptr1_4_ = ~thr_ptr1[4];

ifu_cmu_lsi_ctl_msff_ctl_macro__width_4 ptr0_reg  (
 .scan_in(ptr0_reg_scanin),
 .scan_out(ptr0_reg_scanout),
 .l1clk( l1clk ),
 .din  ({thr_ptr0[3:1],thr_ptr0_0_}),
 .dout ({thr_ptr0_lat[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_lsi_ctl_msff_ctl_macro__width_4 ptr1_reg  (
 .scan_in(ptr1_reg_scanin),
 .scan_out(ptr1_reg_scanout),
 .l1clk( l1clk ),
 .din  ({thr_ptr1[7:5],thr_ptr1_4_}),
 .dout ({thr_ptr1_lat[7:4]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign thr_ptr0_lat_0_ = ~thr_ptr0_lat[0];
assign thr_ptr1_lat_4_ = ~thr_ptr1_lat[4];

///////////////////////////////////////////////////
// select a thread based on the pointer value
///////////////////////////////////////////////////
assign req_bit[0] = (thr_ptr0[1] & ~csm_rqv[1] & ~csm_rqv[2] & ~csm_rqv[3] & csm_rqv[0]) |
                    (thr_ptr0[2] &               ~csm_rqv[2] & ~csm_rqv[3] & csm_rqv[0]) |
                    (thr_ptr0[3] &                             ~csm_rqv[3] & csm_rqv[0]) |
                    (thr_ptr0[0] &                                           csm_rqv[0]);

                    
assign req_bit[1] = (thr_ptr0[2] & ~csm_rqv[2] & ~csm_rqv[3] & ~csm_rqv[0] & csm_rqv[1]) |
                    (thr_ptr0[3] &               ~csm_rqv[3] & ~csm_rqv[0] & csm_rqv[1]) | 
                    (thr_ptr0[0] &                             ~csm_rqv[0] & csm_rqv[1]) |
                    (thr_ptr0[1] &                                           csm_rqv[1]);

                    
assign req_bit[2] = (thr_ptr0[3] & ~csm_rqv[3] & ~csm_rqv[0] & ~csm_rqv[1] & csm_rqv[2]) |
                    (thr_ptr0[0] &               ~csm_rqv[0] & ~csm_rqv[1] & csm_rqv[2]) |
                    (thr_ptr0[1] &                             ~csm_rqv[1] & csm_rqv[2]) |
                    (thr_ptr0[2] &                                           csm_rqv[2]);
                    

assign req_bit[3] = (thr_ptr0[0] & ~csm_rqv[0] & ~csm_rqv[1] & ~csm_rqv[2] & csm_rqv[3]) |
                    (thr_ptr0[1] &               ~csm_rqv[1] & ~csm_rqv[2] & csm_rqv[3]) |
                    (thr_ptr0[2] &                             ~csm_rqv[2] & csm_rqv[3]) |
                    (thr_ptr0[3] &                                           csm_rqv[3]);

                    
assign req_bit[4] = (thr_ptr1[5] & ~csm_rqv[5] & ~csm_rqv[6] & ~csm_rqv[7] & csm_rqv[4]) |
                    (thr_ptr1[6] &               ~csm_rqv[6] & ~csm_rqv[7] & csm_rqv[4]) |
                    (thr_ptr1[7] &                             ~csm_rqv[7] & csm_rqv[4]) |
                    (thr_ptr1[4] &                                           csm_rqv[4]);


assign req_bit[5] = (thr_ptr1[6] & ~csm_rqv[6] & ~csm_rqv[7] & ~csm_rqv[4] & csm_rqv[5]) |
                    (thr_ptr1[7] &               ~csm_rqv[7] & ~csm_rqv[4] & csm_rqv[5]) | 
                    (thr_ptr1[4] &                             ~csm_rqv[4] & csm_rqv[5]) |
                    (thr_ptr1[5] &                                           csm_rqv[5]);
                    

assign req_bit[6] = (thr_ptr1[7] & ~csm_rqv[7] & ~csm_rqv[4] & ~csm_rqv[5] & csm_rqv[6]) |
                    (thr_ptr1[4] &               ~csm_rqv[4] & ~csm_rqv[5] & csm_rqv[6]) |
                    (thr_ptr1[5] &                             ~csm_rqv[5] & csm_rqv[6]) |
                    (thr_ptr1[6] &                                           csm_rqv[6]);
 

assign req_bit[7] = (thr_ptr1[4] & ~csm_rqv[4] & ~csm_rqv[5] & ~csm_rqv[6] & csm_rqv[7]) |
                    (thr_ptr1[5] &               ~csm_rqv[5] & ~csm_rqv[6] & csm_rqv[7]) |
                    (thr_ptr1[6] &                             ~csm_rqv[6] & csm_rqv[7]) |
                    (thr_ptr1[7] &                                           csm_rqv[7]);


// select the req based on favor bits
assign tg0_valid = |(csm_rqv[3:0]);
assign tg1_valid = |(csm_rqv[7:4]);

assign sel_tg1 = (favor_tg1_in & tg1_valid) | ~tg0_valid;

assign lsc_req_sel[7:0] = ({8{sel_tg1}} & {req_bit[7:4],4'b0000}) |
                          ({8{~sel_tg1}} & {4'b0000,req_bit[3:0]});

// update tg0/tg1 pointers

///////////////////////////////////////////////////
///////////////////////////////////////////////////

///////////////////////////////////////////////////
// RETURN DATA TO IFU
///////////////////////////////////////////////////
// Decode l15_rtn_type opcode and generate enables
// for fill data registers in DP block.
///////////////////////////////////////////////////
ifu_cmu_lsi_ctl_msff_ctl_macro__width_1 reg_pmen  (
 .scan_in(reg_pmen_scanin),
 .scan_out(reg_pmen_scanout),
 .l1clk( l1clk ),
 .din  (lsu_ifu_cmu_pmen),
 .dout (ifu_pmen),
  .siclk(siclk),
  .soclk(soclk)
);

// decode return pkt

assign lsc_clken = l15_ifu_valid | ~ifu_pmen;

assign l15_rtn_type[3:0] = l15_spc_cpkt[17:14];

assign fill_return = ~l15_rtn_type[2] & ~l15_rtn_type[1] & l15_rtn_type[0] & l15_ifu_valid; 

assign cmu_nc_f4b = l15_spc_cpkt[9] & l15_spc_cpkt[2];

assign lsc_fill_rtn1 = fill_return & ~second_pkt;
assign lsc_fill_rtn2 = (fill_return & second_pkt) | (fill_return & cmu_nc_f4b);

// set up state for second pkt of a two pkt ifill return.
// non-cacheable and f4b ifill returns (nc_f4b_r0) are single pkt.
assign second_pkt_in = ((second_pkt & ~fill_return) | (~second_pkt & fill_return & ~cmu_nc_f4b)) & ~(second_pkt & fill_return);
 
ifu_cmu_lsi_ctl_msff_ctl_macro__width_1 sec_pkt_lat  (
 .scan_in(sec_pkt_lat_scanin),
 .scan_out(sec_pkt_lat_scanout),
 .l1clk(l1clk),
 .din  (second_pkt_in),
 .dout (second_pkt),
  .siclk(siclk),
  .soclk(soclk)
);
 

assign cmu_data_ready[0] = ~l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & ~l15_spc_cpkt[6] & lsc_fill_rtn2;
assign cmu_data_ready[1] = ~l15_spc_cpkt[8] & ~l15_spc_cpkt[7] &  l15_spc_cpkt[6] & lsc_fill_rtn2;
assign cmu_data_ready[2] = ~l15_spc_cpkt[8] &  l15_spc_cpkt[7] & ~l15_spc_cpkt[6] & lsc_fill_rtn2;
assign cmu_data_ready[3] = ~l15_spc_cpkt[8] &  l15_spc_cpkt[7] &  l15_spc_cpkt[6] & lsc_fill_rtn2;
assign cmu_data_ready[4] =  l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & ~l15_spc_cpkt[6] & lsc_fill_rtn2;
assign cmu_data_ready[5] =  l15_spc_cpkt[8] & ~l15_spc_cpkt[7] &  l15_spc_cpkt[6] & lsc_fill_rtn2;
assign cmu_data_ready[6] =  l15_spc_cpkt[8] &  l15_spc_cpkt[7] & ~l15_spc_cpkt[6] & lsc_fill_rtn2;
assign cmu_data_ready[7] =  l15_spc_cpkt[8] &  l15_spc_cpkt[7] &  l15_spc_cpkt[6] & lsc_fill_rtn2;


assign cmu_any_data_ready = lsc_fill_rtn2;
assign cmu_any_un_cacheable = l15_spc_cpkt[9];

///////////////////////////////////////////////////
// decode l2 err and l2 miss and send to ifu
///////////////////////////////////////////////////
//assign cmu_l2_err[1:0] = l15_spc_cpkt[11:10];

assign cmu_l2_err_pkt1_in[1:0] = ({2{lsc_fill_rtn1}} & l15_spc_cpkt[11:10]) & ~{2{lsc_fill_rtn2}};


ifu_cmu_lsi_ctl_msff_ctl_macro__width_2 stg_r1_lat0  (
 .scan_in(stg_r1_lat0_scanin),
 .scan_out(stg_r1_lat0_scanout),
 .l1clk( l1clk ),
 .din  (cmu_l2_err_pkt1_in[1:0]),
 .dout (cmu_l2_err_pkt1[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// l2 err
// 00 - no err, 01 - correctable, 10 - uncorrectable, 11 - not data
// report the worst offense if the two packets have different errors
// not_data > uncorrectable > correctable > no err


assign cmu_l2_err[1] = l15_spc_cpkt[11] | cmu_l2_err_pkt1[1];
assign cmu_l2_err[0] = ( l15_spc_cpkt[11]   &  l15_spc_cpkt[10]) |
                       ( cmu_l2_err_pkt1[1] &  cmu_l2_err_pkt1[0]) |
                       (~l15_spc_cpkt[11]   &  cmu_l2_err_pkt1[0]) |
                       ( l15_spc_cpkt[10]   & ~cmu_l2_err_pkt1[1]);


//assign cmu_l2_err[1:0] = (l15_spc_cpkt[11:10] | cmu_l2_err_pkt1[1:0]);


// l2miss is asserted on the first packet only.

assign cmu_l2miss_in = lsc_fill_rtn1 & l15_spc_cpkt[12];


///////////////////////////////////////////////////
// Word selects for muxing out instructions
///////////////////////////////////////////////////
assign cmu_inst0_v_in = lsc_fill_rtn2;
assign cmu_inst1_v_in = ~(cmu_fill_paddr[4] & cmu_fill_paddr[3] & cmu_fill_paddr[2]) & ~cmu_nc_f4b & lsc_fill_rtn2;
assign cmu_inst2_v_in = ~(cmu_fill_paddr[4] & cmu_fill_paddr[3]) & ~cmu_nc_f4b & lsc_fill_rtn2;
assign cmu_inst3_v_in = ~((cmu_fill_paddr[4] & cmu_fill_paddr[2]) | (cmu_fill_paddr[4] & cmu_fill_paddr[3])) & 
                        ~cmu_nc_f4b & lsc_fill_rtn2;


ifu_cmu_lsi_ctl_msff_ctl_macro__width_4 cmu_inst_reg  (
 .scan_in(cmu_inst_reg_scanin),
 .scan_out(cmu_inst_reg_scanout),
 .l1clk( l1clk ),
 .din  ({cmu_inst0_v_in, cmu_inst1_v_in, cmu_inst2_v_in, cmu_inst3_v_in}),
 .dout ({cmu_inst0_v, cmu_inst1_v, cmu_inst2_v, cmu_inst3_v}),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// Generate decodes for muxing out instructions
///////////////////////////////////////////////////
assign lsc_data_sel[0] = ~cmu_fill_paddr[4] & ~cmu_fill_paddr[3] & ~cmu_fill_paddr[2];
assign lsc_data_sel[1] = ~cmu_fill_paddr[4] & ~cmu_fill_paddr[3] &  cmu_fill_paddr[2];
assign lsc_data_sel[2] = ~cmu_fill_paddr[4] &  cmu_fill_paddr[3] & ~cmu_fill_paddr[2];
assign lsc_data_sel[3] = ~cmu_fill_paddr[4] &  cmu_fill_paddr[3] &  cmu_fill_paddr[2];
assign lsc_data_sel[4] =  cmu_fill_paddr[4] & ~cmu_fill_paddr[3] & ~cmu_fill_paddr[2];
assign lsc_data_sel[5] =  cmu_fill_paddr[4] & ~cmu_fill_paddr[3] &  cmu_fill_paddr[2];
assign lsc_data_sel[6] =  cmu_fill_paddr[4] &  cmu_fill_paddr[3] & ~cmu_fill_paddr[2];
assign lsc_data_sel[7] =  cmu_fill_paddr[4] &  cmu_fill_paddr[3] &  cmu_fill_paddr[2];


///////////////////////////////////////////////////
// Cache Invalidation 
///////////////////////////////////////////////////
assign store_inval_vector[31:0] = l15_spc_data1[95:64];
assign evic_inv_vec_0[31:0] = l15_spc_data1[31:0];
assign evic_inv_vec_1[31:0] = l15_spc_data1[87:56];


assign take_strm_store_ack = (~l15_rtn_type[3] &  l15_rtn_type[2] &  l15_rtn_type[1] & ~l15_rtn_type[0]) & l15_ifu_valid;
assign take_store_ack      = (~l15_rtn_type[3] &  l15_rtn_type[2] & ~l15_rtn_type[1] & ~l15_rtn_type[0] & 
                              ~l15_spc_data1[124] & ~l15_spc_data1[123]) & l15_ifu_valid;
assign take_inval_ack      = (~l15_rtn_type[3] &  l15_rtn_type[2] & ~l15_rtn_type[1] & ~l15_rtn_type[0] & 
                              l15_spc_data1[124] & ~l15_spc_data1[123]) & l15_ifu_valid;
assign take_load_return    = (~l15_rtn_type[3] & ~l15_rtn_type[2] & ~l15_rtn_type[1] & ~l15_rtn_type[0]) & l15_ifu_valid;
assign take_evic_inv       = (~l15_rtn_type[3] & ~l15_rtn_type[2] &  l15_rtn_type[1] &  l15_rtn_type[0]) & l15_ifu_valid;


assign cmu_inval_ack_din[0] = take_inval_ack & (~l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & ~l15_spc_cpkt[6]);
assign cmu_inval_ack_din[1] = take_inval_ack & (~l15_spc_cpkt[8] & ~l15_spc_cpkt[7] &  l15_spc_cpkt[6]);
assign cmu_inval_ack_din[2] = take_inval_ack & (~l15_spc_cpkt[8] &  l15_spc_cpkt[7] & ~l15_spc_cpkt[6]);
assign cmu_inval_ack_din[3] = take_inval_ack & (~l15_spc_cpkt[8] &  l15_spc_cpkt[7] &  l15_spc_cpkt[6]);
assign cmu_inval_ack_din[4] = take_inval_ack & ( l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & ~l15_spc_cpkt[6]);
assign cmu_inval_ack_din[5] = take_inval_ack & ( l15_spc_cpkt[8] & ~l15_spc_cpkt[7] &  l15_spc_cpkt[6]);
assign cmu_inval_ack_din[6] = take_inval_ack & ( l15_spc_cpkt[8] &  l15_spc_cpkt[7] & ~l15_spc_cpkt[6]);
assign cmu_inval_ack_din[7] = take_inval_ack & ( l15_spc_cpkt[8] &  l15_spc_cpkt[7] &  l15_spc_cpkt[6]);

assign inv_vector[0] =  ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & store_inval_vector[0]
                        | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & store_inval_vector[4]
                        | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & store_inval_vector[8]
                        | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & store_inval_vector[12]
                        | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & store_inval_vector[16]
                        | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & store_inval_vector[20]
                        | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & store_inval_vector[24]
                        | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & store_inval_vector[28]);

assign inv_vector[1] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & store_inval_vector[1]
                       | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & store_inval_vector[5]
                       | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & store_inval_vector[9]
                       | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & store_inval_vector[13]
                       | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & store_inval_vector[17]
                       | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & store_inval_vector[21]
                       | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & store_inval_vector[25]
                       | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & store_inval_vector[29]);

assign inv_vector[2] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & store_inval_vector[2]
                       | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & store_inval_vector[6]
                       | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & store_inval_vector[10]
                       | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & store_inval_vector[14]
                       | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & store_inval_vector[18]
                       | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & store_inval_vector[22]
                       | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & store_inval_vector[26]
                       | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & store_inval_vector[30]);

assign inv_vector[3] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & store_inval_vector[3]
                       | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & store_inval_vector[7]
                       | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & store_inval_vector[11]
                       | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & store_inval_vector[15]
                       | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & store_inval_vector[19]
                       | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & store_inval_vector[23]
                       | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & store_inval_vector[27]
                       | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & store_inval_vector[31]);

// **************************************************

assign evic_i_inv_0_true =  ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[0]
                            | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_0[4]
                            | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[8]
                            | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_0[12]
                            | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[16]
                            | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_0[20]
                            | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[24]
                            | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_0[28]);

assign evic_inv_way0[0] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[1]
                            | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_0[5]
                            | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[9]
                            | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_0[13]
                            | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[17]
                            | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_0[21]
                            | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[25]
                            | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_0[29]);

assign evic_inv_way0[1] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[2]
                            | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_0[6]
                            | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[10]
                            | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_0[14]
                            | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[18]
                            | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_0[22]
                            | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[26]
                            | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_0[30]);

assign evic_inv_way0[2] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[3]
                            | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_0[7]
                            | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[11]
                            | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_0[15]
                            | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[19]
                            | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_0[23]
                            | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_0[27]
                            | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_0[31]);

// **************************************************
assign evic_i_inv_1_true =  ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[0]
                            | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_1[4]
                            | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[8]
                            | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_1[12]
                            | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[16]
                            | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_1[20]
                            | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[24]
                            | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_1[28]);

assign evic_inv_way1[0] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[1]
                          | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_1[5]
                          | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[9]
                          | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_1[13]
                          | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[17]
                          | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_1[21]
                          | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[25]
                          | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_1[29]);

assign evic_inv_way1[1] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[2]
                          | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_1[6]
                          | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[10]
                          | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_1[14]
                          | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[18]
                          | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_1[22]
                          | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[26]
                          | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_1[30]);

assign evic_inv_way1[2] = ( (~cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[3]
                          | (~cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_1[7]
                          | (~cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[11]
                          | (~cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_1[15]
                          | ( cpuid[2] & ~cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[19]
                          | ( cpuid[2] & ~cpuid[1] &  cpuid[0]) & evic_inv_vec_1[23]
                          | ( cpuid[2] &  cpuid[1] & ~cpuid[0]) & evic_inv_vec_1[27]
                          | ( cpuid[2] &  cpuid[1] &  cpuid[0]) & evic_inv_vec_1[31]);

//0in bits_on -var {str_strm_invalidate, cross_invalidate} -max 1
assign str_strm_invalidate = (take_strm_store_ack | take_store_ack) & inv_vector[0];
assign cross_invalidate = take_load_return & l15_spc_cpkt[5];       // way valid


assign evic_invalidate_w0  = take_evic_inv &  evic_i_inv_0_true & ~evic_i_inv_1_true;
assign evic_invalidate_w1  = take_evic_inv & ~evic_i_inv_0_true &  evic_i_inv_1_true;
assign evic_invalidate_w01 = take_evic_inv &  evic_i_inv_0_true &  evic_i_inv_1_true;
assign evic_invalidate_any = take_evic_inv & (evic_i_inv_0_true | evic_i_inv_1_true);

assign evic_way0[2:0] = (evic_inv_way0[2:0] & {3{evic_invalidate_w0}}) |
                        (evic_inv_way1[2:0] & {3{evic_invalidate_w1}}) |
                        (evic_inv_way0[2:0] & {3{evic_invalidate_w01}});

assign evic_index[10:5] = ({l15_spc_data1[116:112], 1'b0} & {6{evic_invalidate_w01}}) |
                          ({l15_spc_data1[116:112], 1'b0} & {6{evic_invalidate_w0}}) |
                          ({l15_spc_data1[116:112], 1'b1} & {6{evic_invalidate_w1}}) ;

assign cmu_icache_invalidate_din = str_strm_invalidate | cross_invalidate | evic_invalidate_any;
assign cmu_icache_invalidate_way_din[2:0] = (inv_vector[3:1] & {3{str_strm_invalidate}}) |
                                            (l15_spc_cpkt[4:2] & {3{cross_invalidate}}) |
                                            (evic_way0[2:0] & {3{evic_invalidate_any}});
assign cmu_icache_invalidate_index_din[10:5] = ({l15_spc_data1[116:112], l15_spc_data1[122]} & {6{str_strm_invalidate}}) |
                                               ({l15_spc_data1[116:112], l15_spc_data1[122]} & {6{take_inval_ack}}) |
                                               (lsu_ifu_ld_index[10:5] & {6{cross_invalidate}}) |
                                               (evic_index[10:5] & {6{evic_invalidate_any}});

assign cmu_evic_invalidate_din = evic_invalidate_w01;
assign cmu_icache_inv_way1_din[2:0] = evic_inv_way1[2:0];

ifu_cmu_lsi_ctl_msff_ctl_macro__width_22 stg_r1_lat  (
 .scan_in(stg_r1_lat_scanin),
 .scan_out(stg_r1_lat_scanout),
 .l1clk(l1clk ),
 .din  ({cmu_icache_invalidate_din,
         cmu_icache_invalidate_way_din[2:0],
         cmu_icache_invalidate_index_din[10:5],
         cmu_icache_inv_way1_din[2:0],
         cmu_evic_invalidate_din,
         cmu_inval_ack_din[7:0]}),
 .dout  ({cmu_icache_invalidate,
         cmu_icache_invalidate_way[2:0],
         cmu_icache_invalidate_index[10:5],
         cmu_icache_inv_way1[2:0],
         cmu_evic_invalidate,
          cmu_inval_ack[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign l15_spc_data_55_32_unused[23:0] = l15_spc_data1[55:32];
assign l15_spc_data_111_96_unused[15:0] = l15_spc_data1[111:96];
assign l15_spc_data_121_117_unused[4:0] = l15_spc_data1[121:117];
assign l15_spc_data_127_125_unused[2:0] = l15_spc_data1[127:125];
assign l15_spc_cpkt_1_0_unused[1:0] = l15_spc_cpkt[1:0];
assign l15_spc_cpkt_13_unused = l15_spc_cpkt[13];

                                                      
////////////////////////////////////////////////////////
// SPARE CELLS
////////////////////////////////////////////////////////
//spare_ctl_macro spares (num=2) (
//	.scan_in(spares_scanin),
//	.scan_out(spares_scanout),
//	.l1clk	(l1clk)
//);
////////////////////////////////////////////////////////
// Flatten spare cells
  cl_sc1_msff_8x spares_spare0_flop ( .l1clk(l1clk), .siclk(siclk), .soclk(soclk), 
        .d(cmu_l2miss_in), .q(cmu_l2miss), .si(stg_r1_lat_scanout), .so(spares_so_0) );
  cl_u1_buf_32x spares_spare0_buf_32x ( .in(1'b1),
  .out(out) );
  cl_u1_nand3_8x spares_spare0_nand3_8x ( .in0(1'b1), .in1(1'b1), .in2(1'b1),
  .out(out) );
  cl_u1_inv_8x spares_spare0_inv_8x ( .in(1'b1),
  .out(out) );
  cl_u1_aoi22_4x spares_spare0_aoi22_4x ( .in00(1'b1), .in01(1'b1), .in10(1'b1), .in11(1'b1),
  .out(out) );
  cl_u1_buf_8x spares_spare0_buf_8x ( .in(1'b1),
  .out(out) );
  cl_u1_oai22_4x spares_spare0_oai22_4x ( .in00(1'b1), .in01(1'b1), .in10(1'b1), .in11(1'b1),
  .out(out) );
  cl_u1_inv_16x spares_spare0_inv_16x ( .in(1'b1),
  .out(out) );
  cl_u1_nand2_16x spares_spare0_nand2_16x ( .in0(1'b1), .in1(1'b1),
  .out(out) );
  cl_u1_nor3_4x spares_spare0_nor3_4x ( .in0(1'b0), .in1(1'b0), .in2(1'b0),
  .out(out) );
  cl_u1_nand2_8x spares_spare0_nand2_8x ( .in0(1'b1), .in1(1'b1),
  .out(out) );
  cl_u1_buf_16x spares_spare0_buf_16x ( .in(1'b1),
  .out(out) );
  cl_u1_nor2_16x spares_spare0_nor2_16x ( .in0(1'b0), .in1(1'b0),
  .out(out) );
  cl_u1_inv_32x spares_spare0_inv_32x ( .in(1'b1),
  .out(out) );
  cl_sc1_msff_8x spares_spare1_flop ( .l1clk(l1clk), .siclk(siclk), .soclk(soclk), 
        .d(1'b0), .si(spares_so_0), .so(spares_scanout),
  .q(q) );
  cl_u1_buf_32x spares_spare1_buf_32x ( .in(1'b1),
  .out(out) );
  cl_u1_nand3_8x spares_spare1_nand3_8x ( .in0(1'b1), .in1(1'b1), .in2(1'b1),
  .out(out) );
  cl_u1_inv_8x spares_spare1_inv_8x ( .in(1'b1),
  .out(out) );
  cl_u1_aoi22_4x spares_spare1_aoi22_4x ( .in00(1'b1), .in01(1'b1), .in10(1'b1), .in11(1'b1),
  .out(out) );
  cl_u1_buf_8x spares_spare1_buf_8x ( .in(1'b1),
  .out(out) );
  cl_u1_oai22_4x spares_spare1_oai22_4x ( .in00(1'b1), .in01(1'b1), .in10(1'b1), .in11(1'b1),
  .out(out) );
  cl_u1_inv_16x spares_spare1_inv_16x ( .in(1'b1),
  .out(out) );
  cl_u1_nand2_16x spares_spare1_nand2_16x ( .in0(1'b1), .in1(1'b1),
  .out(out) );
  cl_u1_nor3_4x spares_spare1_nor3_4x ( .in0(1'b0), .in1(1'b0), .in2(1'b0),
  .out(out) );
  cl_u1_nand2_8x spares_spare1_nand2_8x ( .in0(1'b1), .in1(1'b1),
  .out(out) );
  cl_u1_buf_16x spares_spare1_buf_16x ( .in(1'b1),
  .out(out) );
  cl_u1_nor2_16x spares_spare1_nor2_16x ( .in0(1'b0), .in1(1'b0),
  .out(out) );
  cl_u1_inv_32x spares_spare1_inv_32x ( .in(1'b1),
  .out(out) );
////////////////////////////////////////////////////////

supply0 vss;
supply1 vdd;

// fixscan start:
assign empty_state_reg_scanin    = scan_in                  ;
assign one_buff_state_reg_scanin = empty_state_reg_scanout  ;
assign l15_hold_state_reg_scanin = one_buff_state_reg_scanout;
assign ifu_l15_valid_reg_scanin  = l15_hold_state_reg_scanout;
assign lsc_l15_valid_reg_scanin  = ifu_l15_valid_reg_scanout;
assign lsc_req_sel_reg_scanin    = lsc_l15_valid_reg_scanout;
assign lsc_cpkt_reg_scanin       = lsc_req_sel_reg_scanout  ;
assign ifu_lsu_lat_scanin        = lsc_cpkt_reg_scanout     ;
assign favour_bit_reg_scanin     = ifu_lsu_lat_scanout      ;
assign ptr0_reg_scanin           = favour_bit_reg_scanout   ;
assign ptr1_reg_scanin           = ptr0_reg_scanout         ;
assign reg_pmen_scanin           = ptr1_reg_scanout         ;
assign sec_pkt_lat_scanin        = reg_pmen_scanout         ;
assign stg_r1_lat0_scanin        = sec_pkt_lat_scanout      ;
assign cmu_inst_reg_scanin       = stg_r1_lat0_scanout      ;
assign stg_r1_lat_scanin         = cmu_inst_reg_scanout     ;
assign spares_scanin             = stg_r1_lat_scanout       ;
assign scan_out                  = spares_scanout           ;

// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_msff_ctl_macro__width_11 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [10:0] fdin;
wire [9:0] so;

  input [10:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [10:0] dout;
  output scan_out;
assign fdin[10:0] = din[10:0];


dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_ctl_msff_ctl_macro__width_22 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [21:0] fdin;
wire [20:0] so;

  input [21:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [21:0] dout;
  output scan_out;
assign fdin[21:0] = din[21:0];


dff #(22)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[21:0]),
.si({scan_in,so[20:0]}),
.so({so[20:0],scan_out}),
.q(dout[21:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_cmu_lsi_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_cmu_lsi_dp (
  tcu_scan_en, 
  l2clk, 
  spc_aclk, 
  spc_bclk, 
  tcu_pce_ov, 
  scan_in, 
  lsc_clken, 
  lsc_data_sel, 
  l15_spc_data1, 
  lsc_fill_rtn1, 
  lsc_fill_rtn2, 
  gkt_ifu_legal, 
  gkt_ifu_flip_parity, 
  cmu_ic_data, 
  cmu_fill_inst0, 
  cmu_fill_inst1, 
  cmu_fill_inst2, 
  cmu_fill_inst3, 
  scan_out) ;
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire l15_w0_parity_pre;
wire l15_w0_parity;
wire l15_w1_parity_pre;
wire l15_w1_parity;
wire l15_w2_parity_pre;
wire l15_w2_parity;
wire l15_w3_parity_pre;
wire l15_w3_parity;
wire [127:0] gkt_data;
wire [32:0] w0_data_r1_buf;
wire [32:0] w0_data_in;
wire [32:0] w1_data_r1_buf;
wire [32:0] w1_data_in;
wire [32:0] w2_data_r1_buf;
wire [32:0] w2_data_in;
wire [32:0] w3_data_r1_buf;
wire [32:0] w3_data_in;
wire [32:0] w4_data_r1_buf;
wire [32:0] w4_data_in;
wire [32:0] w5_data_r1_buf;
wire [32:0] w5_data_in;
wire [32:0] w6_data_r1_buf;
wire [32:0] w6_data_in;
wire [32:0] w7_data_r1_buf;
wire [32:0] w7_data_in;
wire fill_data_w0_reg_scanin;
wire fill_data_w0_reg_scanout;
wire [32:0] w0_data_r1;
wire fill_data_w1_reg_scanin;
wire fill_data_w1_reg_scanout;
wire [32:0] w1_data_r1;
wire fill_data_w2_reg_scanin;
wire fill_data_w2_reg_scanout;
wire [32:0] w2_data_r1;
wire fill_data_w3_reg_scanin;
wire fill_data_w3_reg_scanout;
wire [32:0] w3_data_r1;
wire fill_data_w4_reg_scanin;
wire fill_data_w4_reg_scanout;
wire [32:0] w4_data_r1;
wire fill_data_w5_reg_scanin;
wire fill_data_w5_reg_scanout;
wire [32:0] w5_data_r1;
wire fill_data_w6_reg_scanin;
wire fill_data_w6_reg_scanout;
wire [32:0] w6_data_r1;
wire fill_data_w7_reg_scanin;
wire fill_data_w7_reg_scanout;
wire [32:0] w7_data_r1;
wire paddr_lat_scanin;
wire paddr_lat_scanout;
wire [7:0] lsc_data_sel_lat;
wire [32:0] cmu_fill_inst0_prebuf;
wire [32:0] cmu_fill_inst1_prebuf;
wire [32:0] cmu_fill_inst2_prebuf;
wire [32:0] cmu_fill_inst3_prebuf;


input tcu_scan_en ;
input l2clk;
input spc_aclk;                 
input spc_bclk;                 
input tcu_pce_ov ;
input scan_in;

input lsc_clken;
input [7:0] lsc_data_sel;

                                
input [127:0] l15_spc_data1;
input         lsc_fill_rtn1;
input         lsc_fill_rtn2;
input [3:0]   gkt_ifu_legal;
input [3:0]   gkt_ifu_flip_parity;


output [263:0] cmu_ic_data;

output [32:0]  cmu_fill_inst0;
output [32:0]  cmu_fill_inst1;
output [32:0]  cmu_fill_inst2;
output [32:0]  cmu_fill_inst3;


output         scan_out;

// scan renames
assign stop = 1'b0;
// end scan

ifu_cmu_lsi_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0   (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);


////////////////////////////////////////////////////////
// Compute parity on input data from gkt
// Data from gkt arrives at ~350ps, parity should be 250 ps.
////////////////////////////////////////////////////////

ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 w0_parity   (
    .din(l15_spc_data1[127:96]),
    .dout(l15_w0_parity_pre)
);
ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 w0_parity_final    (
    .din0(l15_w0_parity_pre),
    .din1(gkt_ifu_flip_parity[3]),
    .dout(l15_w0_parity)                                                     
);
                                                         
ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 w1_parity   (
    .din(l15_spc_data1[95:64]),
    .dout(l15_w1_parity_pre)
);
ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 w1_parity_final    (
    .din0(l15_w1_parity_pre),
    .din1(gkt_ifu_flip_parity[2]),
    .dout(l15_w1_parity)                                                     
);
                                                         

ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 w2_parity   (
    .din(l15_spc_data1[63:32]),
    .dout(l15_w2_parity_pre)
);
ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 w2_parity_final    (
    .din0(l15_w2_parity_pre),
    .din1(gkt_ifu_flip_parity[1]),
    .dout(l15_w2_parity)                                                     
);
                                                         

ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 w3_parity   (
    .din(l15_spc_data1[31:0]),
    .dout(l15_w3_parity_pre)
);
ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 w3_parity_final    (
    .din0(l15_w3_parity_pre),
    .din1(gkt_ifu_flip_parity[0]),
    .dout(l15_w3_parity)                                                     
);
                                                         

////////////////////////////////////////////////////////
// For illegal instructions, 0 out bits 31,30,24,23,22 of instruction
////////////////////////////////////////////////////////
ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 zero_opc_and0   (
.din0 ({l15_spc_data1[31],l15_spc_data1[30],l15_spc_data1[24],l15_spc_data1[23],l15_spc_data1[22]}),
.din1 ({5{gkt_ifu_legal[0]}}),                                
.dout ({gkt_data[31],gkt_data[30],gkt_data[24],gkt_data[23],gkt_data[22]})                               
);

ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 zero_opc_and1   (
.din0 ({l15_spc_data1[63],l15_spc_data1[62],l15_spc_data1[56],l15_spc_data1[55],l15_spc_data1[54]}),
.din1 ({5{gkt_ifu_legal[1]}}),                                
.dout ({gkt_data[63],gkt_data[62],gkt_data[56],gkt_data[55],gkt_data[54]})                               
);

ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 zero_opc_and2   (
.din0 ({l15_spc_data1[95],l15_spc_data1[94],l15_spc_data1[88],l15_spc_data1[87],l15_spc_data1[86]}),
.din1 ({5{gkt_ifu_legal[2]}}),                                
.dout ({gkt_data[95],gkt_data[94],gkt_data[88],gkt_data[87],gkt_data[86]})                               
);

ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 zero_opc_and3   (
.din0 ({l15_spc_data1[127],l15_spc_data1[126],l15_spc_data1[120],l15_spc_data1[119],l15_spc_data1[118]}),
.din1 ({5{gkt_ifu_legal[3]}}),                                
.dout ({gkt_data[127],gkt_data[126],gkt_data[120],gkt_data[119],gkt_data[118]})                               
);

assign gkt_data[29:25] = l15_spc_data1[29:25];
assign gkt_data[21:0] = l15_spc_data1[21:0];

assign gkt_data[61:57] = l15_spc_data1[61:57];
assign gkt_data[53:32] = l15_spc_data1[53:32];

assign gkt_data[93:89] = l15_spc_data1[93:89];
assign gkt_data[85:64] = l15_spc_data1[85:64];

assign gkt_data[125:121] = l15_spc_data1[125:121];
assign gkt_data[117:96] = l15_spc_data1[117:96];


////////////////////////////////////////////////////////
// Flopping input data from gkt
////////////////////////////////////////////////////////

ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w0_data_mux  (
    .din1(w0_data_r1_buf[32:0]),
    .din0({l15_w0_parity,gkt_data[127:96]}),
    .sel0(lsc_fill_rtn1),
    .dout(w0_data_in[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w1_data_mux  (
    .din1(w1_data_r1_buf[32:0]),
    .din0({l15_w1_parity,gkt_data[95:64]}),
    .sel0(lsc_fill_rtn1),
    .dout(w1_data_in[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w2_data_mux  (
    .din1(w2_data_r1_buf[32:0]),
    .din0({l15_w2_parity,gkt_data[63:32]}),
    .sel0(lsc_fill_rtn1),
    .dout(w2_data_in[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w3_data_mux  (
    .din1(w3_data_r1_buf[32:0]),
    .din0({l15_w3_parity,gkt_data[31:0]}),
    .sel0(lsc_fill_rtn1),
    .dout(w3_data_in[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w4_data_mux  (
    .din1(w4_data_r1_buf[32:0]),
    .din0({l15_w0_parity,gkt_data[127:96]}),
    .sel0(lsc_fill_rtn2),
    .dout(w4_data_in[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w5_data_mux  (
    .din1(w5_data_r1_buf[32:0]),
    .din0({l15_w1_parity,gkt_data[95:64]}),
    .sel0(lsc_fill_rtn2),
    .dout(w5_data_in[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w6_data_mux  (
    .din1(w6_data_r1_buf[32:0]),
    .din0({l15_w2_parity,gkt_data[63:32]}),
    .sel0(lsc_fill_rtn2),
    .dout(w6_data_in[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w7_data_mux  (
    .din1(w7_data_r1_buf[32:0]),
    .din0({l15_w3_parity,gkt_data[31:0]}),
    .sel0(lsc_fill_rtn2),
    .dout(w7_data_in[32:0])
);

ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w0_reg  (
    .scan_in(fill_data_w0_reg_scanin),
    .scan_out(fill_data_w0_reg_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (w0_data_in[32:0]),
    .dout(w0_data_r1[32:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w1_reg  (
    .scan_in(fill_data_w1_reg_scanin),
    .scan_out(fill_data_w1_reg_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (w1_data_in[32:0]),
    .dout(w1_data_r1[32:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w2_reg  (
    .scan_in(fill_data_w2_reg_scanin),
    .scan_out(fill_data_w2_reg_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (w2_data_in[32:0]),
    .dout(w2_data_r1[32:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w3_reg  (
    .scan_in(fill_data_w3_reg_scanin),
    .scan_out(fill_data_w3_reg_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (w3_data_in[32:0]),
    .dout(w3_data_r1[32:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w4_reg  (
    .scan_in(fill_data_w4_reg_scanin),
    .scan_out(fill_data_w4_reg_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (w4_data_in[32:0]),
    .dout(w4_data_r1[32:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w5_reg  (
    .scan_in(fill_data_w5_reg_scanin),
    .scan_out(fill_data_w5_reg_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (w5_data_in[32:0]),
    .dout(w5_data_r1[32:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w6_reg  (
    .scan_in(fill_data_w6_reg_scanin),
    .scan_out(fill_data_w6_reg_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (w6_data_in[32:0]),
    .dout(w6_data_r1[32:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w7_reg  (
    .scan_in(fill_data_w7_reg_scanin),
    .scan_out(fill_data_w7_reg_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (w7_data_in[32:0]),
    .dout(w7_data_r1[32:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

////////////////////////////////////////////////////////
// Instruction Mux
////////////////////////////////////////////////////////
ifu_cmu_lsi_dp_msff_macro__left_8__stack_16l__width_8 paddr_lat   (
    .scan_in(paddr_lat_scanin),
    .scan_out(paddr_lat_scanout),
    .clk (l2clk),
    .en  (lsc_clken),
    .din (lsc_data_sel[7:0]),
    .dout(lsc_data_sel_lat[7:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 inst0_mux  (
    .din0(w0_data_r1_buf[32:0]),
    .din1(w1_data_r1_buf[32:0]),
    .din2(w2_data_r1_buf[32:0]),
    .din3(w3_data_r1_buf[32:0]),
    .din4(w4_data_r1_buf[32:0]),
    .din5(w5_data_r1_buf[32:0]),
    .din6(w6_data_r1_buf[32:0]),
    .din7(w7_data_r1_buf[32:0]),
    .sel0(lsc_data_sel_lat[0]),
    .sel1(lsc_data_sel_lat[1]),
    .sel2(lsc_data_sel_lat[2]),
    .sel3(lsc_data_sel_lat[3]),
    .sel4(lsc_data_sel_lat[4]),
    .sel5(lsc_data_sel_lat[5]),
    .sel6(lsc_data_sel_lat[6]),
    .sel7(lsc_data_sel_lat[7]),
    .dout(cmu_fill_inst0_prebuf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 inst0_buf   (
	.din	(cmu_fill_inst0_prebuf[32:0]),
	.dout	(cmu_fill_inst0[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 inst1_mux  (
    .din0(w1_data_r1_buf[32:0]),
    .din1(w2_data_r1_buf[32:0]),
    .din2(w3_data_r1_buf[32:0]),
    .din3(w4_data_r1_buf[32:0]),
    .din4(w5_data_r1_buf[32:0]),
    .din5(w6_data_r1_buf[32:0]),
    .din6(w7_data_r1_buf[32:0]),
    .din7(w0_data_r1_buf[32:0]),
    .sel0(lsc_data_sel_lat[0]),
    .sel1(lsc_data_sel_lat[1]),
    .sel2(lsc_data_sel_lat[2]),
    .sel3(lsc_data_sel_lat[3]),
    .sel4(lsc_data_sel_lat[4]),
    .sel5(lsc_data_sel_lat[5]),
    .sel6(lsc_data_sel_lat[6]),
    .sel7(lsc_data_sel_lat[7]),
    .dout(cmu_fill_inst1_prebuf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 inst1_buf   (
	.din	(cmu_fill_inst1_prebuf[32:0]),
	.dout	(cmu_fill_inst1[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 inst2_mux  (
    .din0(w2_data_r1_buf[32:0]),
    .din1(w3_data_r1_buf[32:0]),
    .din2(w4_data_r1_buf[32:0]),
    .din3(w5_data_r1_buf[32:0]),
    .din4(w6_data_r1_buf[32:0]),
    .din5(w7_data_r1_buf[32:0]),
    .din6(w0_data_r1_buf[32:0]),
    .din7(w1_data_r1_buf[32:0]),
    .sel0(lsc_data_sel_lat[0]),
    .sel1(lsc_data_sel_lat[1]),
    .sel2(lsc_data_sel_lat[2]),
    .sel3(lsc_data_sel_lat[3]),
    .sel4(lsc_data_sel_lat[4]),
    .sel5(lsc_data_sel_lat[5]),
    .sel6(lsc_data_sel_lat[6]),
    .sel7(lsc_data_sel_lat[7]),
    .dout(cmu_fill_inst2_prebuf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 inst2_buf   (
	.din	(cmu_fill_inst2_prebuf[32:0]),
	.dout	(cmu_fill_inst2[32:0])
);

ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 inst3_mux  (
    .din0(w3_data_r1_buf[32:0]),
    .din1(w4_data_r1_buf[32:0]),
    .din2(w5_data_r1_buf[32:0]),
    .din3(w6_data_r1_buf[32:0]),
    .din4(w7_data_r1_buf[32:0]),
    .din5(w0_data_r1_buf[32:0]),
    .din6(w1_data_r1_buf[32:0]),
    .din7(w2_data_r1_buf[32:0]),
    .sel0(lsc_data_sel_lat[0]),
    .sel1(lsc_data_sel_lat[1]),
    .sel2(lsc_data_sel_lat[2]),
    .sel3(lsc_data_sel_lat[3]),
    .sel4(lsc_data_sel_lat[4]),
    .sel5(lsc_data_sel_lat[5]),
    .sel6(lsc_data_sel_lat[6]),
    .sel7(lsc_data_sel_lat[7]),
    .dout(cmu_fill_inst3_prebuf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 inst3_buf   (
	.din	(cmu_fill_inst3_prebuf[32:0]),
	.dout	(cmu_fill_inst3[32:0])
);


////////////////////////////////////////////////////////
// Buffer Cache data
////////////////////////////////////////////////////////
ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w0_data_buf   (
    .din	(w0_data_r1[32:0]),
	.dout	(w0_data_r1_buf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w1_data_buf   (
    .din	(w1_data_r1[32:0]),
	.dout	(w1_data_r1_buf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w2_data_buf   (
    .din	(w2_data_r1[32:0]),
	.dout	(w2_data_r1_buf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w3_data_buf   (
    .din	(w3_data_r1[32:0]),
	.dout	(w3_data_r1_buf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w4_data_buf   (
    .din	(w4_data_r1[32:0]),
	.dout	(w4_data_r1_buf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w5_data_buf   (
    .din	(w5_data_r1[32:0]),
	.dout	(w5_data_r1_buf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w6_data_buf   (
    .din	(w6_data_r1[32:0]),
	.dout	(w6_data_r1_buf[32:0])
);

ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w7_data_buf   (
    .din	(w7_data_r1[32:0]),
	.dout	(w7_data_r1_buf[32:0])
);

////////////////////////////////////////////////////////
// Cache Data Line
////////////////////////////////////////////////////////
assign cmu_ic_data[32:0] = w0_data_r1_buf[32:0];
assign cmu_ic_data[65:33] = w1_data_r1_buf[32:0];
assign cmu_ic_data[98:66] = w2_data_r1_buf[32:0];
assign cmu_ic_data[131:99] = w3_data_r1_buf[32:0];
assign cmu_ic_data[164:132] = w4_data_r1_buf[32:0];
assign cmu_ic_data[197:165] = w5_data_r1_buf[32:0];
assign cmu_ic_data[230:198] = w6_data_r1_buf[32:0];
assign cmu_ic_data[263:231] = w7_data_r1_buf[32:0];


// fixscan start:
assign fill_data_w0_reg_scanin   = scan_in                  ;
assign fill_data_w1_reg_scanin   = fill_data_w0_reg_scanout ;
assign fill_data_w2_reg_scanin   = fill_data_w1_reg_scanout ;
assign fill_data_w3_reg_scanin   = fill_data_w2_reg_scanout ;
assign fill_data_w4_reg_scanin   = fill_data_w3_reg_scanout ;
assign fill_data_w5_reg_scanin   = fill_data_w4_reg_scanout ;
assign fill_data_w6_reg_scanin   = fill_data_w5_reg_scanout ;
assign fill_data_w7_reg_scanin   = fill_data_w6_reg_scanout ;
assign paddr_lat_scanin          = fill_data_w7_reg_scanout ;
assign scan_out                  = paddr_lat_scanout        ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module ifu_cmu_lsi_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 (
  din0, 
  din1, 
  dout);
  input [4:0] din0;
  input [4:0] din1;
  output [4:0] dout;


and2 #(5)  d0_0 (
.in0(din0[4:0]),
.in1(din1[4:0]),
.out(dout[4:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [32:0] din0;
  input [32:0] din1;
  input sel0;
  output [32:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(33)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
.dout(dout[32:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [31:0] so;

  input [32:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [32:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(33)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[32:0]),
.si({scan_in,so[31:0]}),
.so({so[31:0],scan_out}),
.q(dout[32:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_dp_msff_macro__left_8__stack_16l__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [32:0] din0;
  input sel0;
  input [32:0] din1;
  input sel1;
  input [32:0] din2;
  input sel2;
  input [32:0] din3;
  input sel3;
  input [32:0] din4;
  input sel4;
  input [32:0] din5;
  input sel5;
  input [32:0] din6;
  input sel6;
  input [32:0] din7;
  input sel7;
  output [32:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(33)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
  .in2(din2[32:0]),
  .in3(din3[32:0]),
  .in4(din4[32:0]),
  .in5(din5[32:0]),
  .in6(din6[32:0]),
  .in7(din7[32:0]),
.dout(dout[32:0])
);


endmodule


//
//   buff macro
//
//


module ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 (
  din, 
  dout);
  input [32:0] din;
  output [32:0] dout;


buff #(33)  d0_0 (
.in(din[32:0]),
.out(dout[32:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_cmu_msb_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_cmu_msb_ctl (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  lsu_ifu_cmu_pmen, 
  l15_spc_cpkt, 
  ftu_fetch_f, 
  ftu_cmiss, 
  ftu_inv_req, 
  ftu_redirect, 
  cmu_req_st, 
  cmu_canleave_st, 
  lsc_l15_valid, 
  cmu_data_ready, 
  lsc_fill_rtn2, 
  mdp_mbhit_q, 
  mct_early_req, 
  mct_real_wom, 
  mct_upd_addr, 
  cmu_has_dup_miss, 
  mct_rst_dupmiss, 
  mct_fill_complete, 
  mct_ignore_cmiss, 
  mct_clken, 
  scan_out) ;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire pmen_lat_scanin;
wire pmen_lat_scanout;
wire [7:0] ftu_fetch_c;
wire ifu_pmen;
wire [7:0] cmu_has_dup_miss_din;
wire [7:0] mct_e0_wom;
wire [7:0] mct_e1_wom;
wire [7:0] mct_e2_wom;
wire [7:0] mct_e3_wom;
wire [7:0] mct_e4_wom;
wire [7:0] mct_e5_wom;
wire [7:0] mct_e6_wom;
wire [7:0] mct_e7_wom;
wire dup_miss_lat_scanin;
wire dup_miss_lat_scanout;
wire [7:0] mct_real_miss;
wire cmu_mbhit_c;
wire redirect_reg_scanin;
wire redirect_reg_scanout;
wire [7:0] ftu_redirect_lat;
wire [7:0] csm_rmwbit_reset;
wire set_e0wom_bit0;
wire [7:0] mdp_e0_wom;
wire reset_e0wom_bit0;
wire next_e0wom_bit0;
wire set_e1wom_bit0;
wire [7:0] mdp_e1_wom;
wire reset_e1wom_bit0;
wire next_e1wom_bit0;
wire set_e2wom_bit0;
wire [7:0] mdp_e2_wom;
wire reset_e2wom_bit0;
wire next_e2wom_bit0;
wire set_e3wom_bit0;
wire [7:0] mdp_e3_wom;
wire reset_e3wom_bit0;
wire next_e3wom_bit0;
wire set_e4wom_bit0;
wire [7:0] mdp_e4_wom;
wire reset_e4wom_bit0;
wire next_e4wom_bit0;
wire set_e5wom_bit0;
wire [7:0] mdp_e5_wom;
wire reset_e5wom_bit0;
wire next_e5wom_bit0;
wire set_e6wom_bit0;
wire [7:0] mdp_e6_wom;
wire reset_e6wom_bit0;
wire next_e6wom_bit0;
wire set_e7wom_bit0;
wire [7:0] mdp_e7_wom;
wire reset_e7wom_bit0;
wire next_e7wom_bit0;
wire set_e0wom_bit1;
wire reset_e0wom_bit1;
wire next_e0wom_bit1;
wire set_e1wom_bit1;
wire reset_e1wom_bit1;
wire next_e1wom_bit1;
wire set_e2wom_bit1;
wire reset_e2wom_bit1;
wire next_e2wom_bit1;
wire set_e3wom_bit1;
wire reset_e3wom_bit1;
wire next_e3wom_bit1;
wire set_e4wom_bit1;
wire reset_e4wom_bit1;
wire next_e4wom_bit1;
wire set_e5wom_bit1;
wire reset_e5wom_bit1;
wire next_e5wom_bit1;
wire set_e6wom_bit1;
wire reset_e6wom_bit1;
wire next_e6wom_bit1;
wire set_e7wom_bit1;
wire reset_e7wom_bit1;
wire next_e7wom_bit1;
wire set_e0wom_bit2;
wire reset_e0wom_bit2;
wire next_e0wom_bit2;
wire set_e1wom_bit2;
wire reset_e1wom_bit2;
wire next_e1wom_bit2;
wire set_e2wom_bit2;
wire reset_e2wom_bit2;
wire next_e2wom_bit2;
wire set_e3wom_bit2;
wire reset_e3wom_bit2;
wire next_e3wom_bit2;
wire set_e4wom_bit2;
wire reset_e4wom_bit2;
wire next_e4wom_bit2;
wire set_e5wom_bit2;
wire reset_e5wom_bit2;
wire next_e5wom_bit2;
wire set_e6wom_bit2;
wire reset_e6wom_bit2;
wire next_e6wom_bit2;
wire set_e7wom_bit2;
wire reset_e7wom_bit2;
wire next_e7wom_bit2;
wire set_e0wom_bit3;
wire reset_e0wom_bit3;
wire next_e0wom_bit3;
wire set_e1wom_bit3;
wire reset_e1wom_bit3;
wire next_e1wom_bit3;
wire set_e2wom_bit3;
wire reset_e2wom_bit3;
wire next_e2wom_bit3;
wire set_e3wom_bit3;
wire reset_e3wom_bit3;
wire next_e3wom_bit3;
wire set_e4wom_bit3;
wire reset_e4wom_bit3;
wire next_e4wom_bit3;
wire set_e5wom_bit3;
wire reset_e5wom_bit3;
wire next_e5wom_bit3;
wire set_e6wom_bit3;
wire reset_e6wom_bit3;
wire next_e6wom_bit3;
wire set_e7wom_bit3;
wire reset_e7wom_bit3;
wire next_e7wom_bit3;
wire set_e0wom_bit4;
wire reset_e0wom_bit4;
wire next_e0wom_bit4;
wire set_e1wom_bit4;
wire reset_e1wom_bit4;
wire next_e1wom_bit4;
wire set_e2wom_bit4;
wire reset_e2wom_bit4;
wire next_e2wom_bit4;
wire set_e3wom_bit4;
wire reset_e3wom_bit4;
wire next_e3wom_bit4;
wire set_e4wom_bit4;
wire reset_e4wom_bit4;
wire next_e4wom_bit4;
wire set_e5wom_bit4;
wire reset_e5wom_bit4;
wire next_e5wom_bit4;
wire set_e6wom_bit4;
wire reset_e6wom_bit4;
wire next_e6wom_bit4;
wire set_e7wom_bit4;
wire reset_e7wom_bit4;
wire next_e7wom_bit4;
wire set_e0wom_bit5;
wire reset_e0wom_bit5;
wire next_e0wom_bit5;
wire set_e1wom_bit5;
wire reset_e1wom_bit5;
wire next_e1wom_bit5;
wire set_e2wom_bit5;
wire reset_e2wom_bit5;
wire next_e2wom_bit5;
wire set_e3wom_bit5;
wire reset_e3wom_bit5;
wire next_e3wom_bit5;
wire set_e4wom_bit5;
wire reset_e4wom_bit5;
wire next_e4wom_bit5;
wire set_e5wom_bit5;
wire reset_e5wom_bit5;
wire next_e5wom_bit5;
wire set_e6wom_bit5;
wire reset_e6wom_bit5;
wire next_e6wom_bit5;
wire set_e7wom_bit5;
wire reset_e7wom_bit5;
wire next_e7wom_bit5;
wire set_e0wom_bit6;
wire reset_e0wom_bit6;
wire next_e0wom_bit6;
wire set_e1wom_bit6;
wire reset_e1wom_bit6;
wire next_e1wom_bit6;
wire set_e2wom_bit6;
wire reset_e2wom_bit6;
wire next_e2wom_bit6;
wire set_e3wom_bit6;
wire reset_e3wom_bit6;
wire next_e3wom_bit6;
wire set_e4wom_bit6;
wire reset_e4wom_bit6;
wire next_e4wom_bit6;
wire set_e5wom_bit6;
wire reset_e5wom_bit6;
wire next_e5wom_bit6;
wire set_e6wom_bit6;
wire reset_e6wom_bit6;
wire next_e6wom_bit6;
wire set_e7wom_bit6;
wire reset_e7wom_bit6;
wire next_e7wom_bit6;
wire set_e0wom_bit7;
wire reset_e0wom_bit7;
wire next_e0wom_bit7;
wire set_e1wom_bit7;
wire reset_e1wom_bit7;
wire next_e1wom_bit7;
wire set_e2wom_bit7;
wire reset_e2wom_bit7;
wire next_e2wom_bit7;
wire set_e3wom_bit7;
wire reset_e3wom_bit7;
wire next_e3wom_bit7;
wire set_e4wom_bit7;
wire reset_e4wom_bit7;
wire next_e4wom_bit7;
wire set_e5wom_bit7;
wire reset_e5wom_bit7;
wire next_e5wom_bit7;
wire set_e6wom_bit7;
wire reset_e6wom_bit7;
wire next_e6wom_bit7;
wire set_e7wom_bit7;
wire reset_e7wom_bit7;
wire next_e7wom_bit7;
wire e0_wom_reg_f_scanin;
wire e0_wom_reg_f_scanout;
wire e1_wom_reg_f_scanin;
wire e1_wom_reg_f_scanout;
wire e2_wom_reg_f_scanin;
wire e2_wom_reg_f_scanout;
wire e3_wom_reg_f_scanin;
wire e3_wom_reg_f_scanout;
wire e4_wom_reg_f_scanin;
wire e4_wom_reg_f_scanout;
wire e5_wom_reg_f_scanin;
wire e5_wom_reg_f_scanout;
wire e6_wom_reg_f_scanin;
wire e6_wom_reg_f_scanout;
wire e7_wom_reg_f_scanin;
wire e7_wom_reg_f_scanout;
wire [7:0] cmu_fill_wom;
wire [7:0] data_ready_bf;
wire data_ready_reg_f_scanin;
wire data_ready_reg_f_scanout;
wire [7:0] data_ready_f;
wire data_ready_reg_c_scanin;
wire data_ready_reg_c_scanout;
wire [7:0] data_ready_c;
wire spares_scanin;
wire spares_scanout;


input tcu_scan_en ;
input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;

input lsu_ifu_cmu_pmen;

input [8:6] l15_spc_cpkt;

input [7:0] ftu_fetch_f;         //from ftu tsm
input [7:0] ftu_cmiss;         //from ftu tsm
input [7:0] ftu_inv_req;         //from ftu tsm
input [7:0] ftu_redirect;      //from ftu tsm

input [7:0] cmu_req_st;
input [7:0] cmu_canleave_st;
input [7:0] lsc_l15_valid;


input [7:0] cmu_data_ready;    // rtn pkt ready
input       lsc_fill_rtn2;      // second pkt being returned, any data rdy
                              
input [7:0]      mdp_mbhit_q;           // Raw hit in miss buffer
                              

output       mct_early_req;

output [7:0] mct_real_wom;   // real wom bits


output [7:0] mct_upd_addr;    //one-hot signal, selects one MB line to be updated


output [7:0] cmu_has_dup_miss;   //indicates thr0 dup miss exists, goes to CMSM0
output [7:0] mct_rst_dupmiss;    // reset duplicate miss wait state
output [7:0] mct_fill_complete;  // signal fill complete 2 cycles after data ready
output       mct_ignore_cmiss;       // ignore cmiss for 3 cycles when data is being returned


output [7:0] mct_clken;

output       scan_out;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
assign se = tcu_scan_en ;
// end scan

//output mdp_cache_bit;       //cacheable bit from MB to CMSB
//output mdp_par_bit;         //parity bit from MB to ??
//assign l2clk = clk;

///////////////////////////////////////////////////
// clock header
///////////////////////////////////////////////////
ifu_cmu_msb_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);
////////////////////////////////////////////////////////
//
// Form clk enable for misbuffer
ifu_cmu_msb_ctl_msff_ctl_macro__width_9 pmen_lat  (
 .scan_in(pmen_lat_scanin),
 .scan_out(pmen_lat_scanout),
 .l1clk ( l1clk ),
 .din   ({  ftu_fetch_f[7:0],lsu_ifu_cmu_pmen}),
 .dout  ({  ftu_fetch_c[7:0], ifu_pmen}),
  .siclk(siclk),
  .soclk(soclk)
);


assign mct_clken[7:0] = ftu_fetch_c[7:0] | ~{8{ifu_pmen}};


////////////////////////////////////////////////////////
// Duplicate miss logic
// Detect whether there exists a duplicate miss for 
// current thread (or PA). WOM bit entries are used
// to detect this duplicate miss. Diagonal bits are ignored
// because they indicate REAL MISS.
// mct_e*_wom are next_wom bits 
// mdp_e*_wom are latched wom bits 
////////////////////////////////////////////////////////
assign cmu_has_dup_miss_din[0] = (mct_e0_wom[7] | mct_e0_wom[6] | mct_e0_wom[5] | mct_e0_wom[4] | 
                                  mct_e0_wom[3] | mct_e0_wom[2] | mct_e0_wom[1]);
assign cmu_has_dup_miss_din[1] = (mct_e1_wom[7] | mct_e1_wom[6] | mct_e1_wom[5] | mct_e1_wom[4] | 
                                  mct_e1_wom[3] | mct_e1_wom[2] | mct_e1_wom[0]);
assign cmu_has_dup_miss_din[2] = (mct_e2_wom[7] | mct_e2_wom[6] | mct_e2_wom[5] | mct_e2_wom[4] | 
                                  mct_e2_wom[3] | mct_e2_wom[1] | mct_e2_wom[0]);
assign cmu_has_dup_miss_din[3] = (mct_e3_wom[7] | mct_e3_wom[6] | mct_e3_wom[5] | mct_e3_wom[4] | 
                                  mct_e3_wom[2] | mct_e3_wom[1] | mct_e3_wom[0]);
assign cmu_has_dup_miss_din[4] = (mct_e4_wom[7] | mct_e4_wom[6] | mct_e4_wom[5] | mct_e4_wom[3] | 
                                  mct_e4_wom[2] | mct_e4_wom[1] | mct_e4_wom[0]);
assign cmu_has_dup_miss_din[5] = (mct_e5_wom[7] | mct_e5_wom[6] | mct_e5_wom[4] | mct_e5_wom[3] | 
                                  mct_e5_wom[2] | mct_e5_wom[1] | mct_e5_wom[0]);
assign cmu_has_dup_miss_din[6] = (mct_e6_wom[7] | mct_e6_wom[5] | mct_e6_wom[4] | mct_e6_wom[3] | 
                                  mct_e6_wom[2] | mct_e6_wom[1] | mct_e6_wom[0]);
assign cmu_has_dup_miss_din[7] = (mct_e7_wom[6] | mct_e7_wom[5] | mct_e7_wom[4] | mct_e7_wom[3] | 
                                  mct_e7_wom[2] | mct_e7_wom[1] | mct_e7_wom[0]);


ifu_cmu_msb_ctl_msff_ctl_macro__width_8 dup_miss_lat  (
 .scan_in(dup_miss_lat_scanin),
 .scan_out(dup_miss_lat_scanout),
 .l1clk ( l1clk ),
 .din   ({  cmu_has_dup_miss_din[7:0]}),
 .dout  ({  cmu_has_dup_miss[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////
// Generate update signal for address, cacheable bit,
// parity and replace way bits.
////////////////////////////////////////////////////////
// enables for miss buffer
assign mct_upd_addr[7:0] = (ftu_cmiss[7:0] | ftu_inv_req[7:0]);

assign mct_real_miss[7:0] = ftu_cmiss[7:0] & {8{~cmu_mbhit_c}};
////////////////////////////////////////////////////////
// WOM bits to be filled in the WOM field of MB
// If there is a flush, set the whole column to '0'.
// If there is a cmiss, then use mbhit signal to select
// the bit to be set.
////////////////////////////////////////////////////////

// raw mbhit is generated if incoming address bits 39:5 match the
// missbuffer entry and
// neither incoming nor the missbuffer entries are non-cacheable and
// neither incoming nor the missbuffer entries are inval_req


assign cmu_mbhit_c = mdp_mbhit_q[0] | mdp_mbhit_q[1] | mdp_mbhit_q[2] | mdp_mbhit_q[3]
                   | mdp_mbhit_q[4] | mdp_mbhit_q[5] | mdp_mbhit_q[6] | mdp_mbhit_q[7];


assign mct_early_req = |(ftu_cmiss[7:0]) & ~cmu_mbhit_c;


////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// SET the WOM bits
// Each thread sets an entire column in WOM array
////////////////////////////////////////////////////////

// Reset the diagonal WOM bits which are the real miss bits 
// 1.When a Real Miss is flushed and it has no dup misses and no mbhit_q,
// 2.When in canleave state, and has no dup misses and no mbhit_q
// 3.Fill complete

// use delayed version of ftu_redirect for resetting real miss wom bit, but use raw
// version to reset dup miss wom bit.
ifu_cmu_msb_ctl_msff_ctl_macro__width_8 redirect_reg  (
 .scan_in(redirect_reg_scanin),
 .scan_out(redirect_reg_scanout),
 .l1clk(l1clk),
 .din  (ftu_redirect[7:0]),
 .dout (ftu_redirect_lat[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign csm_rmwbit_reset[7:0] = (cmu_req_st[7:0] & ftu_redirect_lat[7:0] & ~lsc_l15_valid[7:0] & ~cmu_has_dup_miss[7:0] & ~mdp_mbhit_q[7:0]) |
                               (cmu_canleave_st[7:0] & ~lsc_l15_valid[7:0] & ~cmu_has_dup_miss[7:0] & ~mdp_mbhit_q[7:0]) |
                               mct_fill_complete[7:0];

// Thread0
////////////////////////////////////////////////////////
assign set_e0wom_bit0 = mdp_e0_wom[0] | mct_real_miss[0];
assign reset_e0wom_bit0 = csm_rmwbit_reset[0];
assign next_e0wom_bit0 = set_e0wom_bit0 & ~reset_e0wom_bit0;

assign set_e1wom_bit0 = mdp_e1_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[1]);
assign reset_e1wom_bit0 = ftu_redirect[0] | mct_fill_complete[1];
assign next_e1wom_bit0 = set_e1wom_bit0 & ~reset_e1wom_bit0;

assign set_e2wom_bit0 = mdp_e2_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[2]);
assign reset_e2wom_bit0 = ftu_redirect[0] | mct_fill_complete[2];
assign next_e2wom_bit0 = set_e2wom_bit0 & ~reset_e2wom_bit0;

assign set_e3wom_bit0 = mdp_e3_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[3]);
assign reset_e3wom_bit0 = ftu_redirect[0] | mct_fill_complete[3];
assign next_e3wom_bit0 = set_e3wom_bit0 & ~reset_e3wom_bit0;

assign set_e4wom_bit0 = mdp_e4_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[4]);
assign reset_e4wom_bit0 = ftu_redirect[0] | mct_fill_complete[4];
assign next_e4wom_bit0 = set_e4wom_bit0 & ~reset_e4wom_bit0;

assign set_e5wom_bit0 = mdp_e5_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[5]);
assign reset_e5wom_bit0 = ftu_redirect[0] | mct_fill_complete[5];
assign next_e5wom_bit0 = set_e5wom_bit0 & ~reset_e5wom_bit0;

assign set_e6wom_bit0 = mdp_e6_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[6]);
assign reset_e6wom_bit0 = ftu_redirect[0] | mct_fill_complete[6];
assign next_e6wom_bit0 = set_e6wom_bit0 & ~reset_e6wom_bit0;

assign set_e7wom_bit0 = mdp_e7_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[7]);
assign reset_e7wom_bit0 = ftu_redirect[0] | mct_fill_complete[7];
assign next_e7wom_bit0 = set_e7wom_bit0 & ~reset_e7wom_bit0;

////////////////////////////////////////////////////////
// Thread1
////////////////////////////////////////////////////////
assign set_e0wom_bit1 = mdp_e0_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[0]);
assign reset_e0wom_bit1 = ftu_redirect[1] | mct_fill_complete[0];
assign next_e0wom_bit1 = set_e0wom_bit1 & ~reset_e0wom_bit1;

assign set_e1wom_bit1 = mdp_e1_wom[1] | mct_real_miss[1];
assign reset_e1wom_bit1 = csm_rmwbit_reset[1];
assign next_e1wom_bit1 = set_e1wom_bit1 & ~reset_e1wom_bit1;

assign set_e2wom_bit1 = mdp_e2_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[2]);
assign reset_e2wom_bit1 = ftu_redirect[1] | mct_fill_complete[2];
assign next_e2wom_bit1 = set_e2wom_bit1 & ~reset_e2wom_bit1;

assign set_e3wom_bit1 = mdp_e3_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[3]);
assign reset_e3wom_bit1 = ftu_redirect[1] | mct_fill_complete[3];
assign next_e3wom_bit1 = set_e3wom_bit1 & ~reset_e3wom_bit1;

assign set_e4wom_bit1 = mdp_e4_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[4]);
assign reset_e4wom_bit1 = ftu_redirect[1] | mct_fill_complete[4];
assign next_e4wom_bit1 = set_e4wom_bit1 & ~reset_e4wom_bit1;

assign set_e5wom_bit1 = mdp_e5_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[5]);
assign reset_e5wom_bit1 = ftu_redirect[1] | mct_fill_complete[5];
assign next_e5wom_bit1 = set_e5wom_bit1 & ~reset_e5wom_bit1;

assign set_e6wom_bit1 = mdp_e6_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[6]);
assign reset_e6wom_bit1 = ftu_redirect[1] | mct_fill_complete[6];
assign next_e6wom_bit1 = set_e6wom_bit1 & ~reset_e6wom_bit1;

assign set_e7wom_bit1 = mdp_e7_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[7]);
assign reset_e7wom_bit1 = ftu_redirect[1] | mct_fill_complete[7];
assign next_e7wom_bit1 = set_e7wom_bit1 & ~reset_e7wom_bit1;

////////////////////////////////////////////////////////
// Thread2
////////////////////////////////////////////////////////
assign set_e0wom_bit2 = mdp_e0_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[0]);
assign reset_e0wom_bit2 = ftu_redirect[2] | mct_fill_complete[0];
assign next_e0wom_bit2 = set_e0wom_bit2 & ~reset_e0wom_bit2;

assign set_e1wom_bit2 = mdp_e1_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[1]);
assign reset_e1wom_bit2 = ftu_redirect[2] | mct_fill_complete[1];
assign next_e1wom_bit2 = set_e1wom_bit2 & ~reset_e1wom_bit2;

assign set_e2wom_bit2 = mdp_e2_wom[2] | mct_real_miss[2];
assign reset_e2wom_bit2 = csm_rmwbit_reset[2];
assign next_e2wom_bit2 = set_e2wom_bit2 & ~reset_e2wom_bit2;

assign set_e3wom_bit2 = mdp_e3_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[3]);
assign reset_e3wom_bit2 = ftu_redirect[2] | mct_fill_complete[3];
assign next_e3wom_bit2 = set_e3wom_bit2 & ~reset_e3wom_bit2;

assign set_e4wom_bit2 = mdp_e4_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[4]);
assign reset_e4wom_bit2 = ftu_redirect[2] | mct_fill_complete[4];
assign next_e4wom_bit2 = set_e4wom_bit2 & ~reset_e4wom_bit2;

assign set_e5wom_bit2 = mdp_e5_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[5]);
assign reset_e5wom_bit2 = ftu_redirect[2] | mct_fill_complete[5];
assign next_e5wom_bit2 = set_e5wom_bit2 & ~reset_e5wom_bit2;

assign set_e6wom_bit2 = mdp_e6_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[6]);
assign reset_e6wom_bit2 = ftu_redirect[2] | mct_fill_complete[6];
assign next_e6wom_bit2 = set_e6wom_bit2 & ~reset_e6wom_bit2;

assign set_e7wom_bit2 = mdp_e7_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[7]);
assign reset_e7wom_bit2 = ftu_redirect[2] | mct_fill_complete[7];
assign next_e7wom_bit2 = set_e7wom_bit2 & ~reset_e7wom_bit2;

////////////////////////////////////////////////////////
// Thread3
////////////////////////////////////////////////////////
assign set_e0wom_bit3 = mdp_e0_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[0]);
assign reset_e0wom_bit3 = ftu_redirect[3] | mct_fill_complete[0];
assign next_e0wom_bit3 = set_e0wom_bit3 & ~reset_e0wom_bit3;

assign set_e1wom_bit3 = mdp_e1_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[1]);
assign reset_e1wom_bit3 = ftu_redirect[3] | mct_fill_complete[1];
assign next_e1wom_bit3 = set_e1wom_bit3 & ~reset_e1wom_bit3;

assign set_e2wom_bit3 = mdp_e2_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[2]);
assign reset_e2wom_bit3 = ftu_redirect[3] | mct_fill_complete[2];
assign next_e2wom_bit3 = set_e2wom_bit3 & ~reset_e2wom_bit3;

assign set_e3wom_bit3 = mdp_e3_wom[3] | mct_real_miss[3];
assign reset_e3wom_bit3 = csm_rmwbit_reset[3];
assign next_e3wom_bit3 = set_e3wom_bit3 & ~reset_e3wom_bit3;

assign set_e4wom_bit3 = mdp_e4_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[4]);
assign reset_e4wom_bit3 = ftu_redirect[3] | mct_fill_complete[4];
assign next_e4wom_bit3 = set_e4wom_bit3 & ~reset_e4wom_bit3;

assign set_e5wom_bit3 = mdp_e5_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[5]);
assign reset_e5wom_bit3 = ftu_redirect[3] | mct_fill_complete[5];
assign next_e5wom_bit3 = set_e5wom_bit3 & ~reset_e5wom_bit3;

assign set_e6wom_bit3 = mdp_e6_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[6]);
assign reset_e6wom_bit3 = ftu_redirect[3] | mct_fill_complete[6];
assign next_e6wom_bit3 = set_e6wom_bit3 & ~reset_e6wom_bit3;

assign set_e7wom_bit3 = mdp_e7_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[7]);
assign reset_e7wom_bit3 = ftu_redirect[3] | mct_fill_complete[7];
assign next_e7wom_bit3 = set_e7wom_bit3 & ~reset_e7wom_bit3;

////////////////////////////////////////////////////////
// Thread4
////////////////////////////////////////////////////////
assign set_e0wom_bit4 = mdp_e0_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[0]);
assign reset_e0wom_bit4 = ftu_redirect[4] | mct_fill_complete[0];
assign next_e0wom_bit4 = set_e0wom_bit4 & ~reset_e0wom_bit4;

assign set_e1wom_bit4 = mdp_e1_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[1]);
assign reset_e1wom_bit4 = ftu_redirect[4] | mct_fill_complete[1];
assign next_e1wom_bit4 = set_e1wom_bit4 & ~reset_e1wom_bit4;

assign set_e2wom_bit4 = mdp_e2_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[2]);
assign reset_e2wom_bit4 = ftu_redirect[4] | mct_fill_complete[2];
assign next_e2wom_bit4 = set_e2wom_bit4 & ~reset_e2wom_bit4;

assign set_e3wom_bit4 = mdp_e3_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[3]);
assign reset_e3wom_bit4 = ftu_redirect[4] | mct_fill_complete[3];
assign next_e3wom_bit4 = set_e3wom_bit4 & ~reset_e3wom_bit4;

assign set_e4wom_bit4 = mdp_e4_wom[4] | mct_real_miss[4];
assign reset_e4wom_bit4 = csm_rmwbit_reset[4];
assign next_e4wom_bit4 = set_e4wom_bit4 & ~reset_e4wom_bit4;

assign set_e5wom_bit4 = mdp_e5_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[5]);
assign reset_e5wom_bit4 = ftu_redirect[4] | mct_fill_complete[5];
assign next_e5wom_bit4 = set_e5wom_bit4 & ~reset_e5wom_bit4;

assign set_e6wom_bit4 = mdp_e6_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[6]);
assign reset_e6wom_bit4 = ftu_redirect[4] | mct_fill_complete[6];
assign next_e6wom_bit4 = set_e6wom_bit4 & ~reset_e6wom_bit4;

assign set_e7wom_bit4 = mdp_e7_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[7]);
assign reset_e7wom_bit4 = ftu_redirect[4] | mct_fill_complete[7];
assign next_e7wom_bit4 = set_e7wom_bit4 & ~reset_e7wom_bit4;

////////////////////////////////////////////////////////
// Thread5
////////////////////////////////////////////////////////
assign set_e0wom_bit5 = mdp_e0_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[0]);
assign reset_e0wom_bit5 = ftu_redirect[5] | mct_fill_complete[0];
assign next_e0wom_bit5 = set_e0wom_bit5 & ~reset_e0wom_bit5;

assign set_e1wom_bit5 = mdp_e1_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[1]);
assign reset_e1wom_bit5 = ftu_redirect[5] | mct_fill_complete[1];
assign next_e1wom_bit5 = set_e1wom_bit5 & ~reset_e1wom_bit5;

assign set_e2wom_bit5 = mdp_e2_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[2]);
assign reset_e2wom_bit5 = ftu_redirect[5] | mct_fill_complete[2];
assign next_e2wom_bit5 = set_e2wom_bit5 & ~reset_e2wom_bit5;

assign set_e3wom_bit5 = mdp_e3_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[3]);
assign reset_e3wom_bit5 = ftu_redirect[5] | mct_fill_complete[3];
assign next_e3wom_bit5 = set_e3wom_bit5 & ~reset_e3wom_bit5;

assign set_e4wom_bit5 = mdp_e4_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[4]);
assign reset_e4wom_bit5 = ftu_redirect[5] | mct_fill_complete[4];
assign next_e4wom_bit5 = set_e4wom_bit5 & ~reset_e4wom_bit5;

assign set_e5wom_bit5 = mdp_e5_wom[5] | mct_real_miss[5];
assign reset_e5wom_bit5 = csm_rmwbit_reset[5];
assign next_e5wom_bit5 = set_e5wom_bit5 & ~reset_e5wom_bit5;

assign set_e6wom_bit5 = mdp_e6_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[6]);
assign reset_e6wom_bit5 = ftu_redirect[5] | mct_fill_complete[6];
assign next_e6wom_bit5 = set_e6wom_bit5 & ~reset_e6wom_bit5;

assign set_e7wom_bit5 = mdp_e7_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[7]);
assign reset_e7wom_bit5 = ftu_redirect[5] | mct_fill_complete[7];
assign next_e7wom_bit5 = set_e7wom_bit5 & ~reset_e7wom_bit5;

////////////////////////////////////////////////////////
// Thread6
////////////////////////////////////////////////////////
assign set_e0wom_bit6 = mdp_e0_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[0]);
assign reset_e0wom_bit6 = ftu_redirect[6] | mct_fill_complete[0];
assign next_e0wom_bit6 = set_e0wom_bit6 & ~reset_e0wom_bit6;

assign set_e1wom_bit6 = mdp_e1_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[1]);
assign reset_e1wom_bit6 = ftu_redirect[6] | mct_fill_complete[1];
assign next_e1wom_bit6 = set_e1wom_bit6 & ~reset_e1wom_bit6;

assign set_e2wom_bit6 = mdp_e2_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[2]);
assign reset_e2wom_bit6 = ftu_redirect[6] | mct_fill_complete[2];
assign next_e2wom_bit6 = set_e2wom_bit6 & ~reset_e2wom_bit6;

assign set_e3wom_bit6 = mdp_e3_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[3]);
assign reset_e3wom_bit6 = ftu_redirect[6] | mct_fill_complete[3];
assign next_e3wom_bit6 = set_e3wom_bit6 & ~reset_e3wom_bit6;

assign set_e4wom_bit6 = mdp_e4_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[4]);
assign reset_e4wom_bit6 = ftu_redirect[6] | mct_fill_complete[4];
assign next_e4wom_bit6 = set_e4wom_bit6 & ~reset_e4wom_bit6;

assign set_e5wom_bit6 = mdp_e5_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[5]);
assign reset_e5wom_bit6 = ftu_redirect[6] | mct_fill_complete[5];
assign next_e5wom_bit6 = set_e5wom_bit6 & ~reset_e5wom_bit6;

assign set_e6wom_bit6 = mdp_e6_wom[6] | mct_real_miss[6];
assign reset_e6wom_bit6 = csm_rmwbit_reset[6];
assign next_e6wom_bit6 = set_e6wom_bit6 & ~reset_e6wom_bit6;

assign set_e7wom_bit6 = mdp_e7_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[7]);
assign reset_e7wom_bit6 = ftu_redirect[6] | mct_fill_complete[7];
assign next_e7wom_bit6 = set_e7wom_bit6 & ~reset_e7wom_bit6;

////////////////////////////////////////////////////////
// Thread7
////////////////////////////////////////////////////////
assign set_e0wom_bit7 = mdp_e0_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[0]);
assign reset_e0wom_bit7 = ftu_redirect[7] | mct_fill_complete[0];
assign next_e0wom_bit7 = set_e0wom_bit7 & ~reset_e0wom_bit7;

assign set_e1wom_bit7 = mdp_e1_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[1]);
assign reset_e1wom_bit7 = ftu_redirect[7] | mct_fill_complete[1];
assign next_e1wom_bit7 = set_e1wom_bit7 & ~reset_e1wom_bit7;

assign set_e2wom_bit7 = mdp_e2_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[2]);
assign reset_e2wom_bit7 = ftu_redirect[7] | mct_fill_complete[2];
assign next_e2wom_bit7 = set_e2wom_bit7 & ~reset_e2wom_bit7;

assign set_e3wom_bit7 = mdp_e3_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[3]);
assign reset_e3wom_bit7 = ftu_redirect[7] | mct_fill_complete[3];
assign next_e3wom_bit7 = set_e3wom_bit7 & ~reset_e3wom_bit7;

assign set_e4wom_bit7 = mdp_e4_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[4]);
assign reset_e4wom_bit7 = ftu_redirect[7] | mct_fill_complete[4];
assign next_e4wom_bit7 = set_e4wom_bit7 & ~reset_e4wom_bit7;

assign set_e5wom_bit7 = mdp_e5_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[5]);
assign reset_e5wom_bit7 = ftu_redirect[7] | mct_fill_complete[5];
assign next_e5wom_bit7 = set_e5wom_bit7 & ~reset_e5wom_bit7;

assign set_e6wom_bit7 = mdp_e6_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[6]);
assign reset_e6wom_bit7 = ftu_redirect[7] | mct_fill_complete[6];
assign next_e6wom_bit7 = set_e6wom_bit7 & ~reset_e6wom_bit7;

assign set_e7wom_bit7 = mdp_e7_wom[7] | mct_real_miss[7];
assign reset_e7wom_bit7 = csm_rmwbit_reset[7];
assign next_e7wom_bit7 = set_e7wom_bit7 & ~reset_e7wom_bit7;

assign mct_e0_wom[7:0] = ({next_e0wom_bit7, next_e0wom_bit6, next_e0wom_bit5, next_e0wom_bit4,
                           next_e0wom_bit3, next_e0wom_bit2, next_e0wom_bit1, next_e0wom_bit0});
assign mct_e1_wom[7:0] = ({next_e1wom_bit7, next_e1wom_bit6, next_e1wom_bit5, next_e1wom_bit4,
                           next_e1wom_bit3, next_e1wom_bit2, next_e1wom_bit1, next_e1wom_bit0});
assign mct_e2_wom[7:0] = ({next_e2wom_bit7, next_e2wom_bit6, next_e2wom_bit5, next_e2wom_bit4,
                           next_e2wom_bit3, next_e2wom_bit2, next_e2wom_bit1, next_e2wom_bit0});
assign mct_e3_wom[7:0] = ({next_e3wom_bit7, next_e3wom_bit6, next_e3wom_bit5, next_e3wom_bit4,
                           next_e3wom_bit3, next_e3wom_bit2, next_e3wom_bit1, next_e3wom_bit0});
assign mct_e4_wom[7:0] = ({next_e4wom_bit7, next_e4wom_bit6, next_e4wom_bit5, next_e4wom_bit4,
                           next_e4wom_bit3, next_e4wom_bit2, next_e4wom_bit1, next_e4wom_bit0});
assign mct_e5_wom[7:0] = ({next_e5wom_bit7, next_e5wom_bit6, next_e5wom_bit5, next_e5wom_bit4,
                           next_e5wom_bit3, next_e5wom_bit2, next_e5wom_bit1, next_e5wom_bit0});
assign mct_e6_wom[7:0] = ({next_e6wom_bit7, next_e6wom_bit6, next_e6wom_bit5, next_e6wom_bit4,
                           next_e6wom_bit3, next_e6wom_bit2, next_e6wom_bit1, next_e6wom_bit0});
assign mct_e7_wom[7:0] = ({next_e7wom_bit7, next_e7wom_bit6, next_e7wom_bit5, next_e7wom_bit4,
                           next_e7wom_bit3, next_e7wom_bit2, next_e7wom_bit1, next_e7wom_bit0});

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e0_wom_reg_f  (
 .scan_in(e0_wom_reg_f_scanin),
 .scan_out(e0_wom_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({mct_e0_wom[7:0]}),
 .dout  ({mdp_e0_wom[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e1_wom_reg_f  (
 .scan_in(e1_wom_reg_f_scanin),
 .scan_out(e1_wom_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({mct_e1_wom[7:0]}),
 .dout  ({mdp_e1_wom[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e2_wom_reg_f  (
 .scan_in(e2_wom_reg_f_scanin),
 .scan_out(e2_wom_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({mct_e2_wom[7:0]}),
 .dout  ({mdp_e2_wom[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e3_wom_reg_f  (
 .scan_in(e3_wom_reg_f_scanin),
 .scan_out(e3_wom_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({mct_e3_wom[7:0]}),
 .dout  ({mdp_e3_wom[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e4_wom_reg_f  (
 .scan_in(e4_wom_reg_f_scanin),
 .scan_out(e4_wom_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({mct_e4_wom[7:0]}),
 .dout  ({mdp_e4_wom[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e5_wom_reg_f  (
 .scan_in(e5_wom_reg_f_scanin),
 .scan_out(e5_wom_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({mct_e5_wom[7:0]}),
 .dout  ({mdp_e5_wom[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e6_wom_reg_f  (
 .scan_in(e6_wom_reg_f_scanin),
 .scan_out(e6_wom_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({mct_e6_wom[7:0]}),
 .dout  ({mdp_e6_wom[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e7_wom_reg_f  (
 .scan_in(e7_wom_reg_f_scanin),
 .scan_out(e7_wom_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({mct_e7_wom[7:0]}),
 .dout  ({mdp_e7_wom[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign mct_real_wom[7:0] = {mdp_e7_wom[7],mdp_e6_wom[6],mdp_e5_wom[5],mdp_e4_wom[4],
                            mdp_e3_wom[3],mdp_e2_wom[2],mdp_e1_wom[1],mdp_e0_wom[0]};

assign cmu_fill_wom[7:0] = ({8{~l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & ~l15_spc_cpkt[6]}} & mdp_e0_wom[7:0]) |
                           ({8{~l15_spc_cpkt[8] & ~l15_spc_cpkt[7] &  l15_spc_cpkt[6]}} & mdp_e1_wom[7:0]) |
                           ({8{~l15_spc_cpkt[8] &  l15_spc_cpkt[7] & ~l15_spc_cpkt[6]}} & mdp_e2_wom[7:0]) |
                           ({8{~l15_spc_cpkt[8] &  l15_spc_cpkt[7] &  l15_spc_cpkt[6]}} & mdp_e3_wom[7:0]) |
                           ({8{ l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & ~l15_spc_cpkt[6]}} & mdp_e4_wom[7:0]) |
                           ({8{ l15_spc_cpkt[8] & ~l15_spc_cpkt[7] &  l15_spc_cpkt[6]}} & mdp_e5_wom[7:0]) |
                           ({8{ l15_spc_cpkt[8] &  l15_spc_cpkt[7] & ~l15_spc_cpkt[6]}} & mdp_e6_wom[7:0]) |
                           ({8{ l15_spc_cpkt[8] &  l15_spc_cpkt[7] &  l15_spc_cpkt[6]}} & mdp_e7_wom[7:0]);
                          
assign mct_rst_dupmiss[7:0]  = cmu_fill_wom[7:0] & {8{lsc_fill_rtn2}};

////////////////////////////////////////////////////////////////
// Ignore CMISS
////////////////////////////////////////////////////////////////
// Ignore cmiss, if cmiss occurs in either of following three cycles 
// |        bf          |        f        |        C        |
// |---------------------------------------------------------
// |     DATA_READY     |  CMISS          |    CMISS        |
// |       CMISS        | (same line)     |   (same line)   |
// | (cmiss on same line|                 |                 |
// |  as data_ready)    |                 |                 |
//

assign data_ready_bf[7:0] = cmu_data_ready[7:0];

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 data_ready_reg_f  (
 .scan_in(data_ready_reg_f_scanin),
 .scan_out(data_ready_reg_f_scanout),
 .l1clk( l1clk ),
 .din  ({data_ready_bf[7:0]}),
 .dout  ({data_ready_f[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_cmu_msb_ctl_msff_ctl_macro__width_8 data_ready_reg_c  (
 .scan_in(data_ready_reg_c_scanin),
 .scan_out(data_ready_reg_c_scanout),
 .l1clk( l1clk ),
 .din  ({data_ready_f[7:0]}),
 .dout  ({data_ready_c[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


// ignore cache miss if it is a dup miss and a data ready for the parent thread has been sent
// on one of prev 3 cycles.
assign mct_ignore_cmiss = (mdp_mbhit_q[0] & (data_ready_bf[0] | data_ready_f[0] | data_ready_c[0])) |
                          (mdp_mbhit_q[1] & (data_ready_bf[1] | data_ready_f[1] | data_ready_c[1])) |
                          (mdp_mbhit_q[2] & (data_ready_bf[2] | data_ready_f[2] | data_ready_c[2])) |
                          (mdp_mbhit_q[3] & (data_ready_bf[3] | data_ready_f[3] | data_ready_c[3])) |
                          (mdp_mbhit_q[4] & (data_ready_bf[4] | data_ready_f[4] | data_ready_c[4])) |
                          (mdp_mbhit_q[5] & (data_ready_bf[5] | data_ready_f[5] | data_ready_c[5])) |
                          (mdp_mbhit_q[6] & (data_ready_bf[6] | data_ready_f[6] | data_ready_c[6])) |
                          (mdp_mbhit_q[7] & (data_ready_bf[7] | data_ready_f[7] | data_ready_c[7])) ;


// signal fill complete 2 cycles after data ready
assign mct_fill_complete[7:0] = data_ready_c[7:0];

////////////////////////////////////////////////////////
// SPARE CELLS
////////////////////////////////////////////////////////
ifu_cmu_msb_ctl_spare_ctl_macro__num_2 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
////////////////////////////////////////////////////////

supply0 vss;
supply1 vdd;
// fixscan start:
assign pmen_lat_scanin           = scan_in                  ;
assign dup_miss_lat_scanin       = pmen_lat_scanout         ;
assign redirect_reg_scanin       = dup_miss_lat_scanout     ;
assign e0_wom_reg_f_scanin       = redirect_reg_scanout     ;
assign e1_wom_reg_f_scanin       = e0_wom_reg_f_scanout     ;
assign e2_wom_reg_f_scanin       = e1_wom_reg_f_scanout     ;
assign e3_wom_reg_f_scanin       = e2_wom_reg_f_scanout     ;
assign e4_wom_reg_f_scanin       = e3_wom_reg_f_scanout     ;
assign e5_wom_reg_f_scanin       = e4_wom_reg_f_scanout     ;
assign e6_wom_reg_f_scanin       = e5_wom_reg_f_scanout     ;
assign e7_wom_reg_f_scanin       = e6_wom_reg_f_scanout     ;
assign data_ready_reg_f_scanin   = e7_wom_reg_f_scanout     ;
assign data_ready_reg_c_scanin   = data_ready_reg_f_scanout ;
assign spares_scanin             = data_ready_reg_c_scanout ;
assign scan_out                  = spares_scanout           ;

// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_cmu_msb_ctl_spare_ctl_macro__num_2 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));
assign scan_out = so_1;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_cmu_msb_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_cmu_msb_dp (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  mct_clken, 
  l15_spc_cpkt, 
  ftu_paddr, 
  ftu_rep_way, 
  ftu_inv_req, 
  ftu_thrx_un_cacheable, 
  lsc_pending_req, 
  lsc_req_sel, 
  mct_upd_addr, 
  mct_real_wom, 
  mdp_mbhit_q, 
  mdp_lsi_rway, 
  ifu_l15_addr, 
  mdp_lsi_nc_bit, 
  mdp_lsi_inv_bit, 
  cmu_fill_wrway, 
  cmu_fill_paddr, 
  scan_out) ;
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire ftu_thrx_un_cacheable_buf;
wire [2:0] ftu_rep_way_buf;
wire [39:0] ftu_paddr_buf;
wire [44:0] e0_misc_dout;
wire [44:0] e0_misc_din;
wire [44:0] e1_misc_dout;
wire [44:0] e1_misc_din;
wire [44:0] e2_misc_dout;
wire [44:0] e2_misc_din;
wire [44:0] e3_misc_dout;
wire [44:0] e3_misc_din;
wire [44:0] e4_misc_dout;
wire [44:0] e4_misc_din;
wire [44:0] e5_misc_dout;
wire [44:0] e5_misc_din;
wire [44:0] e6_misc_dout;
wire [44:0] e6_misc_din;
wire [44:0] e7_misc_dout;
wire [44:0] e7_misc_din;
wire e0_phyaddr_reg_scanin;
wire e0_phyaddr_reg_scanout;
wire e1_phyaddr_reg_scanin;
wire e1_phyaddr_reg_scanout;
wire e2_phyaddr_reg_scanin;
wire e2_phyaddr_reg_scanout;
wire e3_phyaddr_reg_scanin;
wire e3_phyaddr_reg_scanout;
wire e4_phyaddr_reg_scanin;
wire e4_phyaddr_reg_scanout;
wire e5_phyaddr_reg_scanin;
wire e5_phyaddr_reg_scanout;
wire e6_phyaddr_reg_scanin;
wire e6_phyaddr_reg_scanout;
wire e7_phyaddr_reg_scanin;
wire e7_phyaddr_reg_scanout;
wire [7:0] cmp1_hit;
wire [7:0] cmp2_hit;
wire [2:0] cmu_fill_wrway_prebuf;
wire [39:0] cmu_fill_paddr_prebuf;
wire mdp_lsi_nc_bit_prebuf;
wire mdp_lsi_inv_bit_prebuf;
wire [2:0] mdp_lsi_rway_prebuf;
wire [39:0] ifu_l15_addr_din;
wire [39:0] ifu_l15_addr_mux;
wire [39:39] ifu_l15_addr_muxbuf;
wire [4:0] ifu_l15_addr_mux_bit4_0;
wire [38:5] ifu_l15_addr_mux_minbuf;
wire ifu_l15_lat0_scanin;
wire ifu_l15_lat0_scanout;
wire [39:0] ifu_l15_addr_prebuf;


input tcu_scan_en ;
input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;

input [7:0]  mct_clken;

input [8:6] l15_spc_cpkt;

input [39:0] ftu_paddr;
input [2:0]  ftu_rep_way;    
input [7:0]  ftu_inv_req;         //from ftu tsm
input        ftu_thrx_un_cacheable;

input        lsc_pending_req;
input [7:0]  lsc_req_sel;     //selected pending requests

input [7:0]  mct_upd_addr;    //one-hot signal, selects one MB line to be updated for phys addr
input [7:0]  mct_real_wom;    // real wom bits


output [7:0] mdp_mbhit_q;     // misbuffer hit


output [2:0] mdp_lsi_rway;   //MB to LSU
output [39:0] ifu_l15_addr; //MB to lsu
output        mdp_lsi_nc_bit;    //cacheable bit from MB to CMSB
output        mdp_lsi_inv_bit;    //cacheable bit from MB to CMSB
//output mdp_lsu_par_bit;      //parity bit from MB to ??

output [2:0]  cmu_fill_wrway;  //MB to ??
output [39:0] cmu_fill_paddr;//MB to lsu
//output mdp_fill_par_bit;     //parity bit from MB to ??

output        scan_out;

// scan renames
assign stop = 1'b0 ;
// end scan

//assign l2clk = clk;
ifu_cmu_msb_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0   (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);

// buffer ftu data before using it
ifu_cmu_msb_dp_buff_macro__stack_60c__width_44 ftu_data  (
	.din	({ftu_thrx_un_cacheable, ftu_rep_way[2:0], ftu_paddr[39:0]}),
	.dout	({ftu_thrx_un_cacheable_buf, ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]})
);

////////////////////////////////////////////////////////////////
// Miss buffers
// physical adress, cacheable bit, parity bit and replace way
// registers for all entries
////////////////////////////////////////////////////////////////
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux0  (
    .din1({e0_misc_dout[44:0]}),
    .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[0], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
    .sel0(mct_upd_addr[0]),
    .dout({e0_misc_din[44:0]})
);

ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux1  (
    .din1({e1_misc_dout[44:0]}),
    .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[1], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
    .sel0(mct_upd_addr[1]),
    .dout({e1_misc_din[44:0]})
);

ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux2  (
    .din1({e2_misc_dout[44:0]}),
    .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[2], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
    .sel0(mct_upd_addr[2]),
    .dout({e2_misc_din[44:0]})
);

ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux3  (
    .din1({e3_misc_dout[44:0]}),
    .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[3], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
    .sel0(mct_upd_addr[3]),
    .dout({e3_misc_din[44:0]})
);

ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux4  (
    .din1({e4_misc_dout[44:0]}),
    .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[4], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
    .sel0(mct_upd_addr[4]),
    .dout({e4_misc_din[44:0]})
);

ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux5  (
    .din1({e5_misc_dout[44:0]}),
    .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[5], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
    .sel0(mct_upd_addr[5]),
    .dout({e5_misc_din[44:0]})
);

ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux6  (
    .din1({e6_misc_dout[44:0]}),
    .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[6], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
    .sel0(mct_upd_addr[6]),
    .dout({e6_misc_din[44:0]})
);

ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux7  (
    .din1({e7_misc_dout[44:0]}),
    .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[7], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}),
    .sel0(mct_upd_addr[7]),
    .dout({e7_misc_din[44:0]})
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e0_phyaddr_reg  (
    .scan_in(e0_phyaddr_reg_scanin),
    .scan_out(e0_phyaddr_reg_scanout),
    .clk (l2clk),
    .en  (mct_clken[0]),
    .din ({e0_misc_din[44:0]}),
    .dout({e0_misc_dout[44:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e1_phyaddr_reg  (
    .scan_in(e1_phyaddr_reg_scanin),
    .scan_out(e1_phyaddr_reg_scanout),
    .clk (l2clk),
    .en  (mct_clken[1]),
    .din ({e1_misc_din[44:0]}),
    .dout({e1_misc_dout[44:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e2_phyaddr_reg  (
    .scan_in(e2_phyaddr_reg_scanin),
    .scan_out(e2_phyaddr_reg_scanout),
    .clk (l2clk),
    .en  (mct_clken[2]),
    .din ({e2_misc_din[44:0]}),
    .dout({e2_misc_dout[44:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e3_phyaddr_reg  (
    .scan_in(e3_phyaddr_reg_scanin),
    .scan_out(e3_phyaddr_reg_scanout),
    .clk (l2clk),
    .en  (mct_clken[3]),
    .din ({e3_misc_din[44:0]}),
    .dout({e3_misc_dout[44:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e4_phyaddr_reg  (
    .scan_in(e4_phyaddr_reg_scanin),
    .scan_out(e4_phyaddr_reg_scanout),
    .clk (l2clk),
    .en  (mct_clken[4]),
    .din ({e4_misc_din[44:0]}),
    .dout({e4_misc_dout[44:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e5_phyaddr_reg  (
    .scan_in(e5_phyaddr_reg_scanin),
    .scan_out(e5_phyaddr_reg_scanout),
    .clk (l2clk),
    .en  (mct_clken[5]),
    .din ({e5_misc_din[44:0]}),
    .dout({e5_misc_dout[44:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e6_phyaddr_reg  (
    .scan_in(e6_phyaddr_reg_scanin),
    .scan_out(e6_phyaddr_reg_scanout),
    .en  (mct_clken[6]),
    .clk (l2clk),
    .din ({e6_misc_din[44:0]}),
    .dout({e6_misc_dout[44:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e7_phyaddr_reg  (
    .scan_in(e7_phyaddr_reg_scanin),
    .scan_out(e7_phyaddr_reg_scanout),
    .clk (l2clk),
    .en  (mct_clken[7]),
    .din ({e7_misc_din[44:0]}), // ifu_lsu_nc_bit_mux, ifu_lsu_rway_mux[2:0]}),
    .dout({e7_misc_dout[44:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)  // ifu_lsu_nc_bit    ,     ifu_lsu_rway[2:0]})
);

////////////////////////////////////////////////////////////////
// hit/miss logic
// never generate a hit if the incoming request is non-cacheable.
// This is taken care of in cmp1.
// never generate a hit if stored entry is non-cacheable, or
// it is a inv_req. This is taken care of in cmp2
////////////////////////////////////////////////////////////////
ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e0_addrhit_cmp1  (
    .dout( cmp1_hit[0]), 
    .din1( {1'b0, e0_misc_dout[35:5]}), 
    .din0( {1'b0, ftu_paddr_buf[35:5]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e1_addrhit_cmp1  (
    .dout( cmp1_hit[1]), 
    .din1( {1'b0, e1_misc_dout[35:5]}), 
    .din0( {1'b0, ftu_paddr_buf[35:5]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e2_addrhit_cmp1  (
    .dout( cmp1_hit[2]), 
    .din1( {1'b0, e2_misc_dout[35:5]}), 
    .din0( {1'b0, ftu_paddr_buf[35:5]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e3_addrhit_cmp1  (
    .dout( cmp1_hit[3]), 
    .din1( {1'b0, e3_misc_dout[35:5]}), 
    .din0( {1'b0, ftu_paddr_buf[35:5]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e4_addrhit_cmp1  (
    .dout( cmp1_hit[4]), 
    .din1( {1'b0, e4_misc_dout[35:5]}), 
    .din0( {1'b0, ftu_paddr_buf[35:5]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e5_addrhit_cmp1  (
    .dout( cmp1_hit[5]), 
    .din1( {1'b0, e5_misc_dout[35:5]}), 
    .din0( {1'b0, ftu_paddr_buf[35:5]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e6_addrhit_cmp1  (
    .dout( cmp1_hit[6]), 
    .din1( {1'b0, e6_misc_dout[35:5]}), 
    .din0( {1'b0, ftu_paddr_buf[35:5]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e7_addrhit_cmp1  (
    .dout( cmp1_hit[7]), 
    .din1( {1'b0, e7_misc_dout[35:5]}), 
    .din0( {1'b0, ftu_paddr_buf[35:5]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e0_addrhit_cmp2  (
    .dout(cmp2_hit[0]), 
    .din1({e0_misc_dout[44:43], 1'b0, 1'b0,                  e0_misc_dout[39:36]}), 
    .din0({2'b00,               1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e1_addrhit_cmp2  (
    .dout(cmp2_hit[1]), 
    .din1({e1_misc_dout[44:43], 1'b0, 1'b0,                  e1_misc_dout[39:36]}), 
    .din0({2'b00,               1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e2_addrhit_cmp2  (
    .dout(cmp2_hit[2]), 
    .din1({e2_misc_dout[44:43], 1'b0, 1'b0,                  e2_misc_dout[39:36]}), 
    .din0({2'b00,               1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e3_addrhit_cmp2  (
    .dout(cmp2_hit[3]), 
    .din1({e3_misc_dout[44:43], 1'b0, 1'b0,                  e3_misc_dout[39:36]}), 
    .din0({2'b00,               1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e4_addrhit_cmp2  (
    .dout(cmp2_hit[4]), 
    .din1({e4_misc_dout[44:43], 1'b0, 1'b0,                  e4_misc_dout[39:36]}), 
    .din0({2'b00,               1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e5_addrhit_cmp2  (
    .dout(cmp2_hit[5]), 
    .din1({e5_misc_dout[44:43], 1'b0, 1'b0,                  e5_misc_dout[39:36]}), 
    .din0({2'b00,               1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e6_addrhit_cmp2  (
    .dout(cmp2_hit[6]), 
    .din1({e6_misc_dout[44:43], 1'b0, 1'b0,                  e6_misc_dout[39:36]}), 
    .din0({2'b00,               1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
); 

ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e7_addrhit_cmp2  (
    .dout(cmp2_hit[7]), 
    .din1({e7_misc_dout[44:43], 1'b0, 1'b0,                  e7_misc_dout[39:36]}), 
    .din0({2'b00,               1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]})
); 

ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and0  (
    .din0(cmp1_hit[0]),
    .din1(cmp2_hit[0]),
    .din2(mct_real_wom[0]),
    .dout(mdp_mbhit_q[0])
);

ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and1  (
    .din0(cmp1_hit[1]),
    .din1(cmp2_hit[1]),
    .din2(mct_real_wom[1]),
    .dout(mdp_mbhit_q[1])
);

ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and2  (
    .din0(cmp1_hit[2]),
    .din1(cmp2_hit[2]),
    .din2(mct_real_wom[2]),
    .dout(mdp_mbhit_q[2])
);

ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and3  (
    .din0(cmp1_hit[3]),
    .din1(cmp2_hit[3]),
    .din2(mct_real_wom[3]),
    .dout(mdp_mbhit_q[3])
);

ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and4  (
    .din0(cmp1_hit[4]),
    .din1(cmp2_hit[4]),
    .din2(mct_real_wom[4]),
    .dout(mdp_mbhit_q[4])
);

ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and5  (
    .din0(cmp1_hit[5]),
    .din1(cmp2_hit[5]),
    .din2(mct_real_wom[5]),
    .dout(mdp_mbhit_q[5])
);

ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and6  (
    .din0(cmp1_hit[6]),
    .din1(cmp2_hit[6]),
    .din2(mct_real_wom[6]),
    .dout(mdp_mbhit_q[6])
);

ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and7  (
    .din0(cmp1_hit[7]),
    .din1(cmp2_hit[7]),
    .din2(mct_real_wom[7]),
    .dout(mdp_mbhit_q[7])
);

////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
// MUX OUT MB data and send it to ftu
////////////////////////////////////////////////////////////////
// Mux out remaing bits based on the return thread id
// sent to ftu
ifu_cmu_msb_dp_mux_macro__mux_aodec__ports_8__stack_60c__width_43 fillwait_data_mux2  (
    .din0({e0_misc_dout[42:0]}),
    .din1({e1_misc_dout[42:0]}),
    .din2({e2_misc_dout[42:0]}),
    .din3({e3_misc_dout[42:0]}),
    .din4({e4_misc_dout[42:0]}),
    .din5({e5_misc_dout[42:0]}),
    .din6({e6_misc_dout[42:0]}),
    .din7({e7_misc_dout[42:0]}),
    .sel(l15_spc_cpkt[8:6]),
    .dout({cmu_fill_wrway_prebuf[2:0], cmu_fill_paddr_prebuf[39:0]})
);

ifu_cmu_msb_dp_buff_macro__stack_60c__width_43 fillwait_data_buf2  (
	.din	({cmu_fill_wrway_prebuf[2:0], cmu_fill_paddr_prebuf[39:0]}),
	.dout	({cmu_fill_wrway[2:0], cmu_fill_paddr[39:0]})
);

// mux out MB data to send request out to gkt
// select based on pending req selected
ifu_cmu_msb_dp_mux_macro__mux_aonpe__ports_8__stack_60c__width_45 cmu_data_mux1  (
    .din0(e0_misc_dout[44:0]),
    .din1(e1_misc_dout[44:0]),
    .din2(e2_misc_dout[44:0]),
    .din3(e3_misc_dout[44:0]),
    .din4(e4_misc_dout[44:0]),
    .din5(e5_misc_dout[44:0]),
    .din6(e6_misc_dout[44:0]),
    .din7(e7_misc_dout[44:0]),
    .sel0(lsc_req_sel[0]),
    .sel1(lsc_req_sel[1]),
    .sel2(lsc_req_sel[2]),
    .sel3(lsc_req_sel[3]),
    .sel4(lsc_req_sel[4]),
    .sel5(lsc_req_sel[5]),
    .sel6(lsc_req_sel[6]),
    .sel7(lsc_req_sel[7]),
    .dout({mdp_lsi_nc_bit_prebuf, mdp_lsi_inv_bit_prebuf, mdp_lsi_rway_prebuf[2:0], ifu_l15_addr_din[39:0]})
);

// Mux out incoming request if no pending req
ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_40 ifu_l15_mux0  (
    .din1(ftu_paddr_buf[39:0]),
    .din0(ifu_l15_addr_din[39:0]),
    .sel0(lsc_pending_req),
    .dout(ifu_l15_addr_mux[39:0])
);

// if bit 39 = 1, it indicates a NCU or L2 CSR request.
// if bit 39 = 0, it is a l2 request, and bits 4:0 need to be
// cleared in this case.
ifu_cmu_msb_dp_and_macro__ports_2__stack_60c__width_5 ifu_l15_and_4_0 
(
 .din1({5{ifu_l15_addr_muxbuf[39]}}),
 .din0(ifu_l15_addr_mux[4:0]),
 .dout(ifu_l15_addr_mux_bit4_0[4:0])
 );

ifu_cmu_msb_dp_buff_macro__minbuff_1__stack_60c__width_34 ifu_l15_minbuf    (
	.din	({ifu_l15_addr_mux[38:5]}),
	.dout	({ifu_l15_addr_mux_minbuf[38:5]})
);

ifu_cmu_msb_dp_msff_macro__stack_60c__width_40 ifu_l15_lat0  (
    .scan_in(ifu_l15_lat0_scanin),
    .scan_out(ifu_l15_lat0_scanout),
    .clk (l2clk),
    .en  (1'b1),
    .din ({ifu_l15_addr_muxbuf[39],ifu_l15_addr_mux_minbuf[38:5], ifu_l15_addr_mux_bit4_0[4:0]}),
    .dout({ifu_l15_addr_prebuf[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_cmu_msb_dp_buff_macro__stack_60c__width_46 ifu_l15_buf0  (
	.din	({ifu_l15_addr_mux[39],    mdp_lsi_nc_bit_prebuf, mdp_lsi_inv_bit_prebuf, mdp_lsi_rway_prebuf[2:0], ifu_l15_addr_prebuf[39:0]}),
	.dout	({ifu_l15_addr_muxbuf[39], mdp_lsi_nc_bit, mdp_lsi_inv_bit, mdp_lsi_rway[2:0], ifu_l15_addr[39:0]})
);
                                              

// fixscan start:
assign e0_phyaddr_reg_scanin     = scan_in                  ;
assign e1_phyaddr_reg_scanin     = e0_phyaddr_reg_scanout   ;
assign e2_phyaddr_reg_scanin     = e1_phyaddr_reg_scanout   ;
assign e3_phyaddr_reg_scanin     = e2_phyaddr_reg_scanout   ;
assign e4_phyaddr_reg_scanin     = e3_phyaddr_reg_scanout   ;
assign e5_phyaddr_reg_scanin     = e4_phyaddr_reg_scanout   ;
assign e6_phyaddr_reg_scanin     = e5_phyaddr_reg_scanout   ;
assign e7_phyaddr_reg_scanin     = e6_phyaddr_reg_scanout   ;
assign ifu_l15_lat0_scanin       = e7_phyaddr_reg_scanout   ;
assign scan_out                  = ifu_l15_lat0_scanout     ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module ifu_cmu_msb_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module ifu_cmu_msb_dp_buff_macro__stack_60c__width_44 (
  din, 
  dout);
  input [43:0] din;
  output [43:0] dout;


buff #(44)  d0_0 (
.in(din[43:0]),
.out(dout[43:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [44:0] din0;
  input [44:0] din1;
  input sel0;
  output [44:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(45)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[44:0]),
  .in1(din1[44:0]),
.dout(dout[44:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [43:0] so;

  input [44:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [44:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(45)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[44:0]),
.si({scan_in,so[43:0]}),
.so({so[43:0],scan_out}),
.q(dout[44:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output dout;


cmp #(8)  m0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout)
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


and3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_dp_mux_macro__mux_aodec__ports_8__stack_60c__width_43 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [42:0] din0;
  input [42:0] din1;
  input [42:0] din2;
  input [42:0] din3;
  input [42:0] din4;
  input [42:0] din5;
  input [42:0] din6;
  input [42:0] din7;
  input [2:0] sel;
  output [42:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(43)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[42:0]),
  .in1(din1[42:0]),
  .in2(din2[42:0]),
  .in3(din3[42:0]),
  .in4(din4[42:0]),
  .in5(din5[42:0]),
  .in6(din6[42:0]),
  .in7(din7[42:0]),
.dout(dout[42:0])
);


endmodule


//
//   buff macro
//
//


module ifu_cmu_msb_dp_buff_macro__stack_60c__width_43 (
  din, 
  dout);
  input [42:0] din;
  output [42:0] dout;


buff #(43)  d0_0 (
.in(din[42:0]),
.out(dout[42:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_dp_mux_macro__mux_aonpe__ports_8__stack_60c__width_45 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [44:0] din0;
  input sel0;
  input [44:0] din1;
  input sel1;
  input [44:0] din2;
  input sel2;
  input [44:0] din3;
  input sel3;
  input [44:0] din4;
  input sel4;
  input [44:0] din5;
  input sel5;
  input [44:0] din6;
  input sel6;
  input [44:0] din7;
  input sel7;
  output [44:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(45)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[44:0]),
  .in1(din1[44:0]),
  .in2(din2[44:0]),
  .in3(din3[44:0]),
  .in4(din4[44:0]),
  .in5(din5[44:0]),
  .in6(din6[44:0]),
  .in7(din7[44:0]),
.dout(dout[44:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_40 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [39:0] din0;
  input [39:0] din1;
  input sel0;
  output [39:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(40)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[39:0]),
  .in1(din1[39:0]),
.dout(dout[39:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_cmu_msb_dp_and_macro__ports_2__stack_60c__width_5 (
  din0, 
  din1, 
  dout);
  input [4:0] din0;
  input [4:0] din1;
  output [4:0] dout;


and2 #(5)  d0_0 (
.in0(din0[4:0]),
.in1(din1[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module ifu_cmu_msb_dp_buff_macro__minbuff_1__stack_60c__width_34 (
  din, 
  dout);
  input [33:0] din;
  output [33:0] dout;


buff #(34)  d0_0 (
.in(din[33:0]),
.out(dout[33:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_cmu_msb_dp_msff_macro__stack_60c__width_40 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [38:0] so;

  input [39:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [39:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(40)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[39:0]),
.si({scan_in,so[38:0]}),
.so({so[38:0],scan_out}),
.q(dout[39:0])
);


endmodule


//
//   buff macro
//
//


module ifu_cmu_msb_dp_buff_macro__stack_60c__width_46 (
  din, 
  dout);
  input [45:0] din;
  output [45:0] dout;


buff #(46)  d0_0 (
.in(din[45:0]),
.out(dout[45:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`define  IC_ARR_HI      63   // (16Kb / 8 ways) / 32 bytes/line = 64 lines/way
`define  IC_ARR_INDX_HI 10   // log2(IC_SZ/IC_WAYS)-1=log2(16Kb/8ways)-1=log2(2048)-1 = 11-1 =10;
`define  IC_ARR_INDX_LO  5   // log2(IC_LINE_SZ)    = log2(32)  = 5
`define  IC_NUM_WAYS     8   // Number of ways;
`define  IC_WAY_HI       2   // log2(IC_NUM_WAYS) - 1 = log2(8)-1 = 3-1 = 2
`define  IC_TAG_SZ      29   


module ifu_ftu (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  wmr_scan_out, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_muxtest, 
  tcu_dectest, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  lbist_run, 
  mbi_run, 
  mbi_ict_write_en, 
  mbi_ict_read_en, 
  mbi_icd_write_en, 
  mbi_icd_read_en, 
  mbi_itb_write_en, 
  mbi_itb_read_en, 
  mbi_icv_write_en, 
  mbi_icv_read_en, 
  mbi_cambist_run, 
  mbi_cambist_shift, 
  mbi_dis_clr_ubit, 
  mbi_init_to_zero, 
  mbi_itb_cam_en_pre, 
  mbi_repl_write, 
  mbi_itb_demap_en, 
  mbi_demap_type, 
  ftu_mbi_tlb_data_cmp, 
  ftu_mbi_tlb_cam_hit, 
  ftu_mbi_tlb_cam_mhit, 
  ftu_mbi_tlb_ctxt0_hit, 
  ftu_mbi_tlb_valid, 
  ftu_mbi_tlb_used, 
  lsu_asi_error_inject, 
  lsu_ifu_direct_map, 
  mbi_addr, 
  mbi_wdata, 
  mbi_cmpsel, 
  ftu_mbi_ict_fail, 
  ftu_mbi_icd_fail, 
  ftu_mbi_itb_fail, 
  ftu_mbi_icv_fail, 
  spc_core_running_status, 
  in_rngl_cdbus, 
  exu_address0_e, 
  exu_address1_e, 
  tlu_retry, 
  tlu_ceter_pscce, 
  tlu_trap_pc_0, 
  tlu_trap_pc_1, 
  tlu_npc_w, 
  tlu_ifu_hpstate_hpriv, 
  tlu_ifu_pstate_priv, 
  tlu_pstate_am, 
  tlu_ifu_invalidate, 
  cmu_fill_paddr, 
  cmu_inval_ack, 
  cmu_l2_err, 
  cmu_l2miss, 
  tlu_cerer_ittp, 
  tlu_cerer_itdp, 
  tlu_cerer_ittm, 
  tlu_cerer_icl2c, 
  tlu_cerer_icl2u, 
  tlu_cerer_icl2nd, 
  tlu_cerer_icvp, 
  tlu_cerer_ictp, 
  tlu_cerer_ictm, 
  cmu_icache_invalidate, 
  cmu_evic_invalidate, 
  cmu_icache_invalidate_way, 
  cmu_icache_inv_way1, 
  cmu_icache_invalidate_index, 
  dec_load_flush_w, 
  dec_tid0_d, 
  dec_tid1_d, 
  dec_br_taken_e, 
  dec_valid_e, 
  tlu_trap_pc_0_valid, 
  tlu_trap_pc_1_valid, 
  tlu_trap_0_tid, 
  tlu_trap_1_tid, 
  tlu_flush_ifu, 
  tlu_itlb_reload, 
  tlu_itlb_bypass, 
  tlu_tl_gt_0, 
  ibu_empty, 
  ibu_room_4ormore, 
  cmu_null_st, 
  cmu_dupmiss_st, 
  cmu_rst_dupmiss, 
  cmu_any_un_cacheable, 
  cmu_any_data_ready, 
  cmu_thr0_data_ready, 
  cmu_thr1_data_ready, 
  cmu_thr2_data_ready, 
  cmu_thr3_data_ready, 
  cmu_thr4_data_ready, 
  cmu_thr5_data_ready, 
  cmu_thr6_data_ready, 
  cmu_thr7_data_ready, 
  cmu_fill_inst0, 
  cmu_fill_inst1, 
  cmu_fill_inst2, 
  cmu_fill_inst3, 
  lsu_ic_enable, 
  lsu_ifu_no_miss, 
  lsu_ifu_ctxt_data, 
  lsu_ifu_tid_w, 
  lsu_ifu_wr_p0ctxt, 
  lsu_ifu_wr_p1ctxt, 
  lsu_ifu_wr_pid, 
  lsu_immu_enable, 
  lsu_ifu_ftu_pmen, 
  lsu_ic_pmen, 
  cmu_fill_wrway, 
  cmu_instr_v, 
  cmu_ic_data, 
  mmu_index, 
  ftu_buffer_wr_en_f, 
  ifu_rngl_cdbus, 
  ftu_rep_way, 
  ftu_paddr, 
  ftu_instr_0_c, 
  ftu_instr_1_c, 
  ftu_instr_2_c, 
  ftu_instr_3_c, 
  ftu_exception_valid_c, 
  ftu_instr_exceptions_c, 
  ftu_instr_valid_c, 
  ftu_fetch_thr_c, 
  ftu_curr_fetch_thr_f, 
  ftu_ifu_quiesce, 
  ifu_ibuffer_write_c, 
  ftu_ic_no_err_c, 
  ftu_bus_0_is_first, 
  ftu_bus_1_is_first, 
  ftu_bus_2_is_first, 
  ftu_bus_3_is_first, 
  ftu_instr_sf_valid_c, 
  ftu_excp_way_d, 
  ftu_excp_tid_d, 
  ftu_excp_way_valid_d, 
  ftu_thrx_un_cacheable, 
  ftu_agc_thr0_cmiss_c, 
  ftu_agc_thr1_cmiss_c, 
  ftu_agc_thr2_cmiss_c, 
  ftu_agc_thr3_cmiss_c, 
  ftu_agc_thr4_cmiss_c, 
  ftu_agc_thr5_cmiss_c, 
  ftu_agc_thr6_cmiss_c, 
  ftu_agc_thr7_cmiss_c, 
  ftu_thr0_inv_req_c, 
  ftu_thr1_inv_req_c, 
  ftu_thr2_inv_req_c, 
  ftu_thr3_inv_req_c, 
  ftu_thr4_inv_req_c, 
  ftu_thr5_inv_req_c, 
  ftu_thr6_inv_req_c, 
  ftu_thr7_inv_req_c, 
  ftu_ibu_redirect_bf, 
  ftu_thr0_redirect_bf, 
  ftu_thr1_redirect_bf, 
  ftu_thr2_redirect_bf, 
  ftu_thr3_redirect_bf, 
  ftu_thr4_redirect_bf, 
  ftu_thr5_redirect_bf, 
  ftu_thr6_redirect_bf, 
  ftu_thr7_redirect_bf, 
  ic_dmo_rd_data, 
  scan_out, 
  efu_spc_fuse_data, 
  efu_spc_fuse_ixfer_en, 
  slow_cmp_sync_en, 
  cmp_slow_sync_en, 
  efu_spc_fuse_iclr, 
  spc_efu_fuse_idata, 
  spc_efu_fuse_ixfer_en, 
  vnw_ary);
wire pce;
wire io_cmp_sync_en;
wire cmp_io_sync_en;
wire [10:0] ifu_ftu_agd_pc_bf_unused;
wire [47:0] ifu_agd_pc_bf;
wire ftu_agd_dp_scanin;
wire ftu_agd_dp_scanout;
wire [68:0] itd_tag;
wire ftu_ctx_dp_wmr_scanin;
wire ftu_ctx_dp_wmr_scanout;
wire ftu_ctx_dp_scanin;
wire ftu_ctx_dp_scanout;
wire ftu_agc_ctl_scanin;
wire ftu_agc_ctl_scanout;
wire [37:0] itb_tte_data;
wire [39:37] ftu_paddr_unq;
wire [32:0] asi_wr_data;
wire ftu_cms_ctl_scanin;
wire ftu_cms_ctl_scanout;
wire [32:0] word2_reordered;
wire [7:0] cms_ic_modified_parity;
wire [32:0] word3_reordered;
wire [32:0] word6_reordered;
wire [32:0] word7_reordered;
wire [5:0] hdr_sram_rvalue;
wire [3:0] hdr_sram_rid;
wire hdr_sram_wr_en;
wire hdr_sram_red_clr;
wire [5:0] sram_hdr_read_data;
wire red_en_unused;
wire [32:0] icd_bus_2_instr_c;
wire [32:0] icd_bus_3_instr_c;
wire ftu_icd_cust_scanin;
wire ftu_icd_cust_scanout;
wire hdr_scanin;
wire hdr_scanout;
wire [10:5] agd_ict_index_bf;
wire ftu_ict_cust_scanin;
wire ftu_ict_cust_scanout;
wire ftu_icv_cust_scanin;
wire ftu_icv_cust_scanout;
wire [31:0] agc_icv_wren_bf;
wire agc_icv_wr_req_bf;
wire ftp_iv_rd_req_bf;
wire [10:2] agd_ic_index_bf;
wire [10:6] agd_icv_windex_bf;
wire [31:0] agc_icv_wrdata_bf;
wire [31:0] icv_valid_f;
wire tte_ubit;
wire itc_tte_ubit;
wire ftu_itb_cust_scanin;
wire ftu_itb_cust_scanout;
wire itc_dis_clr_ubit;
wire itc_bypass_bf;
wire itc_wr_u_en;
wire itc_itlb_rd_vld_bf;
wire ftp_itlb_cam_vld_bf;
wire [5:0] itd_rw_index;
wire itc_rw_index_vld;
wire itc_demap;
wire itc_demap_context;
wire itc_demap_all;
wire itc_demap_real;
wire [37:0] itd_data;
wire [28:0] ict_itlb_way_0_tag_f_rep0;
wire [28:0] ict_itlb_way_1_tag_f_rep0;
wire [28:0] ict_itlb_way_2_tag_f_rep0;
wire [28:0] ict_itlb_way_3_tag_f_rep0;
wire [28:0] ict_itlb_way_4_tag_f_rep0;
wire [28:0] ict_itlb_way_5_tag_f_rep0;
wire [28:0] ict_itlb_way_6_tag_f_rep0;
wire [28:0] ict_itlb_way_7_tag_f_rep0;
wire [7:0] agd_itlb_valid_fast_f;
wire [7:0] itb_icd_waysel_c;
wire itb_chit_c;
wire itb_cam_hit_c;
wire itb_itb_mhit_c;
wire [39:13] pa_unflopped_unused;
wire [65:0] itb_tte_tag;
wire itb_tte_u_bit;
wire itb_tte_data_parity;
wire itb_tte_p_c;
wire [39:3] asi_addr_bf;
wire ftu_itc_ctl_scanin;
wire ftu_itc_ctl_scanout;
wire ftu_itd_dp_scanin;
wire ftu_itd_dp_scanout;
wire [2:0] ftp_curr_pid_bf;
wire itc_ra_to_pa_bf;
wire [13:0] ctx_cntx_0_to_write_bf;
wire [13:0] ctx_cntx_1_to_write_bf;
wire [12:0] ctx_curr_cntx_0_bf;
wire [12:0] ctx_curr_cntx_1_bf;
wire ftu_ftp_ctl_scanin;
wire ftu_ftp_ctl_scanout;
wire ftu_tfc_ctl_scanin;
wire ftu_tfc_ctl_scanout;
wire ftu_byp_dp_scanin;
wire ftu_byp_dp_scanout;
wire ftu_asi_ctl_scanin;
wire ftu_asi_ctl_scanout;
wire [2:0] ftp_thr0_trprdpc_sel_bf;
wire [2:0] ftp_thr1_trprdpc_sel_bf;
wire [2:0] ftp_thr2_trprdpc_sel_bf;
wire [2:0] ftp_thr3_trprdpc_sel_bf;
wire [2:0] ftp_thr4_trprdpc_sel_bf;
wire [2:0] ftp_thr5_trprdpc_sel_bf;
wire [2:0] ftp_thr6_trprdpc_sel_bf;
wire [2:0] ftp_thr7_trprdpc_sel_bf;
wire [3:0] agc_thr0_pcf_sel_bf;
wire [3:0] agc_thr1_pcf_sel_bf;
wire [3:0] agc_thr2_pcf_sel_bf;
wire [3:0] agc_thr3_pcf_sel_bf;
wire [3:0] agc_thr4_pcf_sel_bf;
wire [3:0] agc_thr5_pcf_sel_bf;
wire [3:0] agc_thr6_pcf_sel_bf;
wire [3:0] agc_thr7_pcf_sel_bf;
wire [1:0] agc_thr0_pcf_sel_last_bf;
wire [1:0] agc_thr1_pcf_sel_last_bf;
wire [1:0] agc_thr2_pcf_sel_last_bf;
wire [1:0] agc_thr3_pcf_sel_last_bf;
wire [1:0] agc_thr4_pcf_sel_last_bf;
wire [1:0] agc_thr5_pcf_sel_last_bf;
wire [1:0] agc_thr6_pcf_sel_last_bf;
wire [1:0] agc_thr7_pcf_sel_last_bf;
wire ftp_thr0_sel_br_bf;
wire ftp_thr1_sel_br_bf;
wire ftp_thr2_sel_br_bf;
wire ftp_thr3_sel_br_bf;
wire ftp_thr4_sel_br_bf;
wire ftp_thr5_sel_br_bf;
wire ftp_thr6_sel_br_bf;
wire ftp_thr7_sel_br_bf;
wire [3:0] agc_sel_inv_index;
wire [3:0] agc_pc_sel_for_c;
wire agc_thr0_byp_incr_bit5;
wire agc_thr1_byp_incr_bit5;
wire agc_thr2_byp_incr_bit5;
wire agc_thr3_byp_incr_bit5;
wire agc_thr4_byp_incr_bit5;
wire agc_thr5_byp_incr_bit5;
wire agc_thr6_byp_incr_bit5;
wire agc_thr7_byp_incr_bit5;
wire [4:2] agc_thr0_byp_pc_update_bf;
wire [4:2] agc_thr1_byp_pc_update_bf;
wire [4:2] agc_thr2_byp_pc_update_bf;
wire [4:2] agc_thr3_byp_pc_update_bf;
wire [4:2] agc_thr4_byp_pc_update_bf;
wire [4:2] agc_thr5_byp_pc_update_bf;
wire [4:2] agc_thr6_byp_pc_update_bf;
wire [4:2] agc_thr7_byp_pc_update_bf;
wire [7:0] ftp_new_thr_sel_bf;
wire [2:0] ftp_ict_data_sel_bf;
wire [5:0] ftp_pc_sel_am;
wire [2:0] ftp_pc_sel_tag_part1;
wire [3:0] ftp_pc_sel_tag_part2;
wire [1:0] ftp_pc_sel_tag_pc_bot;
wire [1:0] ftp_pc_sel_tag_pc_top;
wire ftp_any_thr_clken;
wire ftp_sel_icv_mbist_addr;
wire [4:0] ftp_icaddr_sel_first_mux;
wire [2:0] agd_direct_map_rep_way;
wire [7:0] agd_itlb_valid_f;
wire [7:0] agd_itlb_valid_dupl_f;
wire [47:2] ifu_agd_pc_f;
wire [4:2] agd_thr0_pc_4_2_f;
wire [4:2] agd_thr1_pc_4_2_f;
wire [4:2] agd_thr2_pc_4_2_f;
wire [4:2] agd_thr3_pc_4_2_f;
wire [4:2] agd_thr4_pc_4_2_f;
wire [4:2] agd_thr5_pc_4_2_f;
wire [4:2] agd_thr6_pc_4_2_f;
wire [4:2] agd_thr7_pc_4_2_f;
wire [29:0] agd_ict_wrtag_bf;
wire [32:0] agd_asi_bist_wrdata;
wire [7:0] agd_mbist_wdata_bf;
wire agd_va_hole_excp_f;
wire [4:2] agd_address0_m;
wire [4:2] agd_address1_m;
wire agc_thr0_cntx_0_sel_ff;
wire agc_thr0_cntx_1_sel_ff;
wire agc_thr1_cntx_0_sel_ff;
wire agc_thr1_cntx_1_sel_ff;
wire agc_thr2_cntx_0_sel_ff;
wire agc_thr2_cntx_1_sel_ff;
wire agc_thr3_cntx_0_sel_ff;
wire agc_thr3_cntx_1_sel_ff;
wire agc_thr4_cntx_0_sel_ff;
wire agc_thr4_cntx_1_sel_ff;
wire agc_thr5_cntx_0_sel_ff;
wire agc_thr5_cntx_1_sel_ff;
wire agc_thr6_cntx_0_sel_ff;
wire agc_thr6_cntx_1_sel_ff;
wire agc_thr7_cntx_0_sel_ff;
wire agc_thr7_cntx_1_sel_ff;
wire [1:0] agc_thr0_cntx_0_sel;
wire [1:0] agc_thr0_cntx_1_sel;
wire [1:0] agc_thr1_cntx_0_sel;
wire [1:0] agc_thr1_cntx_1_sel;
wire [1:0] agc_thr2_cntx_0_sel;
wire [1:0] agc_thr2_cntx_1_sel;
wire [1:0] agc_thr3_cntx_0_sel;
wire [1:0] agc_thr3_cntx_1_sel;
wire [1:0] agc_thr4_cntx_0_sel;
wire [1:0] agc_thr4_cntx_1_sel;
wire [1:0] agc_thr5_cntx_0_sel;
wire [1:0] agc_thr5_cntx_1_sel;
wire [1:0] agc_thr6_cntx_0_sel;
wire [1:0] agc_thr6_cntx_1_sel;
wire [1:0] agc_thr7_cntx_0_sel;
wire [1:0] agc_thr7_cntx_1_sel;
wire [7:0] ftp_itb_fetch_thr_bf;
wire [7:0] itc_thr_to_write;
wire ftp_itlb_probe_req_l;
wire asi_ith_det_req;
wire ftp_asi_tg_wr_req_hold;
wire ftp_itlb_cam_vld_f;
wire [2:0] asi_way_bf;
wire itc_demap_next;
wire [7:0] ftp_curr_fetch_thr_f;
wire [7:0] ftp_fetch_thr_q_f;
wire ftp_fill_req_q_bf;
wire [3:0] err_w0_8b_parity_f;
wire [3:0] err_w1_8b_parity_f;
wire [3:0] err_w2_8b_parity_f;
wire [3:0] err_w3_8b_parity_f;
wire [3:0] err_w4_8b_parity_f;
wire [3:0] err_w5_8b_parity_f;
wire [3:0] err_w6_8b_parity_f;
wire [3:0] err_w7_8b_parity_f;
wire tsm_thr0_ignore_by_pass;
wire tsm_thr1_ignore_by_pass;
wire tsm_thr2_ignore_by_pass;
wire tsm_thr3_ignore_by_pass;
wire tsm_thr4_ignore_by_pass;
wire tsm_thr5_ignore_by_pass;
wire tsm_thr6_ignore_by_pass;
wire tsm_thr7_ignore_by_pass;
wire tsm_thr0_no_new_miss;
wire tsm_thr1_no_new_miss;
wire tsm_thr2_no_new_miss;
wire tsm_thr3_no_new_miss;
wire tsm_thr4_no_new_miss;
wire tsm_thr5_no_new_miss;
wire tsm_thr6_no_new_miss;
wire tsm_thr7_no_new_miss;
wire [1:0] ftp_tid0_e;
wire [1:0] ftp_tid1_e;
wire ftp_fetch_v_f;
wire ftp_asi_mbist_access_bf;
wire itd_prty_256m;
wire itd_prty_4m;
wire itd_prty_64k;
wire itd_prty_8k;
wire itd_prty_ctxt0;
wire itd_prty_ctxt1;
wire tlb_context0_hit;
wire agc_itb_tag_perr_c;
wire [1:0] agc_vl_data_c;
wire [3:0] agc_asi_sel_word_c;
wire [7:0] agc_sel_tg_data_f;
wire [7:0] agc_word_en_bf;
wire [7:0] agc_by_pass_update_lru_bf;
wire [7:0] agc_invalidation_req_ff;
wire agc_any_invalidation_req_f;
wire agc_thr0_sf_valid_f;
wire agc_thr1_sf_valid_f;
wire agc_thr2_sf_valid_f;
wire agc_thr3_sf_valid_f;
wire agc_thr4_sf_valid_f;
wire agc_thr5_sf_valid_f;
wire agc_thr6_sf_valid_f;
wire agc_thr7_sf_valid_f;
wire agc_thr0_micro_flush_unq_c;
wire agc_thr1_micro_flush_unq_c;
wire agc_thr2_micro_flush_unq_c;
wire agc_thr3_micro_flush_unq_c;
wire agc_thr4_micro_flush_unq_c;
wire agc_thr5_micro_flush_unq_c;
wire agc_thr6_micro_flush_unq_c;
wire agc_thr7_micro_flush_unq_c;
wire agc_thr0_err_detect_c;
wire agc_thr1_err_detect_c;
wire agc_thr2_err_detect_c;
wire agc_thr3_err_detect_c;
wire agc_thr4_err_detect_c;
wire agc_thr5_err_detect_c;
wire agc_thr6_err_detect_c;
wire agc_thr7_err_detect_c;
wire agc_thr0_cmiss_stm_c;
wire agc_thr1_cmiss_stm_c;
wire agc_thr2_cmiss_stm_c;
wire agc_thr3_cmiss_stm_c;
wire agc_thr4_cmiss_stm_c;
wire agc_thr5_cmiss_stm_c;
wire agc_thr6_cmiss_stm_c;
wire agc_thr7_cmiss_stm_c;
wire [2:0] agc_fill_wrway_bf;
wire agc_thr0_lsu_no_ic_miss;
wire agc_thr1_lsu_no_ic_miss;
wire agc_thr2_lsu_no_ic_miss;
wire agc_thr3_lsu_no_ic_miss;
wire agc_thr4_lsu_no_ic_miss;
wire agc_thr5_lsu_no_ic_miss;
wire agc_thr6_lsu_no_ic_miss;
wire agc_thr7_lsu_no_ic_miss;
wire agc_thr0_itb_miss_c;
wire agc_thr1_itb_miss_c;
wire agc_thr2_itb_miss_c;
wire agc_thr3_itb_miss_c;
wire agc_thr4_itb_miss_c;
wire agc_thr5_itb_miss_c;
wire agc_thr6_itb_miss_c;
wire agc_thr7_itb_miss_c;
wire agc_thr0_tlu_redirect_bf;
wire agc_thr1_tlu_redirect_bf;
wire agc_thr2_tlu_redirect_bf;
wire agc_thr3_tlu_redirect_bf;
wire agc_thr4_tlu_redirect_bf;
wire agc_thr5_tlu_redirect_bf;
wire agc_thr6_tlu_redirect_bf;
wire agc_thr7_tlu_redirect_bf;
wire agc_kill_fetch_cv_c;
wire [2:0] agc_instr_bp_sel_c;
wire ftp_icd_quad_0_en_bf;
wire ftp_icd_quad_1_en_bf;
wire ftp_icd_quad_2_en_bf;
wire ftp_icd_quad_3_en_bf;
wire ftp_ic_rd_req_bf;
wire ftp_ic_wr_req_bf;
wire ftp_ic_wr_ps_en_bf;
wire [32:0] icd_bus_0_instr_c;
wire [32:0] icd_bus_1_instr_c;
wire ftp_tg_rd_req_bf;
wire ftp_tg_wr_req_bf;
wire ftp_tg_clk_en;
wire [29:0] ict_itlb_way_0_tag_f;
wire [29:0] ict_itlb_way_1_tag_f;
wire [29:0] ict_itlb_way_2_tag_f;
wire [29:0] ict_itlb_way_3_tag_f;
wire [29:0] ict_itlb_way_4_tag_f;
wire [29:0] ict_itlb_way_5_tag_f;
wire [29:0] ict_itlb_way_6_tag_f;
wire [29:0] ict_itlb_way_7_tag_f;
wire itd_index_valid_in;
wire ftp_itt_rd_req_bf;
wire ftp_itd_rd_req_bf;
wire ftp_ith_det_req_bf;
wire itc_sel_trap_pc_0;
wire itc_sel_trap_pc_1;
wire itc_sel_demap_tag_d;
wire itc_sel_demap_tag_c0;
wire itc_sel_demap_tag_c1;
wire itc_sel_write_tag;
wire itc_sel_write_tag_indexed;
wire itc_sel_default;
wire itc_tag_error_inj;
wire itc_data_error_inj;
wire itc_write_next;
wire itc_sel_mbist;
wire itc_mbi_itb_read_en;
wire itc_itb_data_sz_1;
wire [2:0] ftp_thr0_pid_data;
wire [2:0] ftp_thr1_pid_data;
wire [2:0] ftp_thr2_pid_data;
wire [2:0] ftp_thr3_pid_data;
wire [2:0] ftp_thr4_pid_data;
wire [2:0] ftp_thr5_pid_data;
wire [2:0] ftp_thr6_pid_data;
wire [2:0] ftp_thr7_pid_data;
wire tsm_thr0_ready_hp_bf_in;
wire tsm_thr1_ready_hp_bf_in;
wire tsm_thr2_ready_hp_bf_in;
wire tsm_thr3_ready_hp_bf_in;
wire tsm_thr4_ready_hp_bf_in;
wire tsm_thr5_ready_hp_bf_in;
wire tsm_thr6_ready_hp_bf_in;
wire tsm_thr7_ready_hp_bf_in;
wire tsm_thr0_fill_rdy0;
wire tsm_thr1_fill_rdy0;
wire tsm_thr2_fill_rdy0;
wire tsm_thr3_fill_rdy0;
wire tsm_thr4_fill_rdy0;
wire tsm_thr5_fill_rdy0;
wire tsm_thr6_fill_rdy0;
wire tsm_thr7_fill_rdy0;
wire asi_ic_wr_req;
wire asi_ic_rd_req;
wire asi_tg_wr_req;
wire asi_tg_rd_req;
wire asi_itd_rd_req;
wire asi_itt_rd_req;
wire [2:0] asi_tid;
wire ftp_asi_rd_done;
wire ftp_asi_wr_done;
wire ftp_reset_fill_wait;
wire ftp_sel_mbist_itb_cycle0;
wire ftp_sel_mbist_itb_cycle1;
wire ftp_sel_mbist_itb_cycle2;
wire ftp_sel_mbist_itb_cycle3;
wire ftp_sel_itlb_tag_cntx0_c;
wire ftp_sel_itlb_tag_cntx1_c;
wire ftp_sel_itlb_data_c;
wire ftp_sel_itlb_pa_c;
wire ftp_asi_it_rd_done;
wire ftp_asi_ic_rd_done;
wire ftp_asi_ic_wr_done;
wire ftp_asi_tg_rd_done;
wire ftp_asi_tg_wr_done;
wire ftp_thr0_room_is_less_t_3;
wire ftp_thr1_room_is_less_t_3;
wire ftp_thr2_room_is_less_t_3;
wire ftp_thr3_room_is_less_t_3;
wire ftp_thr4_room_is_less_t_3;
wire ftp_thr5_room_is_less_t_3;
wire ftp_thr6_room_is_less_t_3;
wire ftp_thr7_room_is_less_t_3;
wire ftp_thr0_go_to_sf_wait;
wire ftp_thr1_go_to_sf_wait;
wire ftp_thr2_go_to_sf_wait;
wire ftp_thr3_go_to_sf_wait;
wire ftp_thr4_go_to_sf_wait;
wire ftp_thr5_go_to_sf_wait;
wire ftp_thr6_go_to_sf_wait;
wire ftp_thr7_go_to_sf_wait;
wire ftp_mbi_icd_read_en_bf;
wire ftp_mbi_ict_read_en_bf;
wire asi_wr_request;
wire asi_rd_request;
wire [32:0] ic_rd_data;
wire [29:0] tg_rd_data;
wire [63:0] it_rd_data;

 input        tcu_scan_en;
 input        l2clk;
 input        scan_in;		

 input           spc_aclk_wmr;
 input           wmr_scan_in;
 output          wmr_scan_out;


 input tcu_pce_ov;		// scan signals
 input spc_aclk;
 input spc_bclk;
 input tcu_muxtest;
 input tcu_dectest;
 input tcu_array_wr_inhibit;
 input tcu_se_scancollar_in;
 input tcu_se_scancollar_out;

 input	lbist_run;
 input	mbi_run;
 input	mbi_ict_write_en;
 input	mbi_ict_read_en;
 input	mbi_icd_write_en;
 input	mbi_icd_read_en;
 input	mbi_itb_write_en;
 input	mbi_itb_read_en;
 input	mbi_icv_write_en; 
 input	mbi_icv_read_en;

 input            mbi_cambist_run;
 input            mbi_cambist_shift;
 input            mbi_dis_clr_ubit;
 input            mbi_init_to_zero;
 input            mbi_itb_cam_en_pre;

 input            mbi_repl_write;
 input            mbi_itb_demap_en;
 input     [1:0]  mbi_demap_type;


 output       ftu_mbi_tlb_data_cmp;
 output       ftu_mbi_tlb_cam_hit;
 output       ftu_mbi_tlb_cam_mhit;
 output       ftu_mbi_tlb_ctxt0_hit;
 output       ftu_mbi_tlb_valid;
 output       ftu_mbi_tlb_used;

 input [31:28]  lsu_asi_error_inject;
 input  lsu_ifu_direct_map;

 input [8:0]	   mbi_addr;
 input [7:0]	   mbi_wdata;
 input [2:0] 	   mbi_cmpsel;


 output	  ftu_mbi_ict_fail;
 output	  ftu_mbi_icd_fail;
 output	  ftu_mbi_itb_fail;
 output	  ftu_mbi_icv_fail;


input [7:0] spc_core_running_status;


 input [64:0] in_rngl_cdbus;
 input [47:0] exu_address0_e;
 input [47:0] exu_address1_e;
 input [1:0]  tlu_retry ;
 input [7:0]  tlu_ceter_pscce ;
 input [47:0] tlu_trap_pc_0;
 input [47:0] tlu_trap_pc_1;
 input [47:2] tlu_npc_w;
 input [7:0]  tlu_ifu_hpstate_hpriv;
 input [7:0]  tlu_ifu_pstate_priv;
 input [7:0]  tlu_pstate_am;
 input [1:0] tlu_ifu_invalidate     ;

 input [39:5] cmu_fill_paddr;
  input [7:0]  cmu_inval_ack;
 input  [1:0] cmu_l2_err;
 input        cmu_l2miss;
// Error enables                      //
 input        tlu_cerer_ittp         ;
 input        tlu_cerer_itdp         ;
 input        tlu_cerer_ittm         ;
 input        tlu_cerer_icl2c     ;
 input        tlu_cerer_icl2u     ; 
 input        tlu_cerer_icl2nd    ; 
 input        tlu_cerer_icvp         ;
 input        tlu_cerer_ictp         ;
 input        tlu_cerer_ictm         ;

 input cmu_icache_invalidate;
 input cmu_evic_invalidate;

 input [2:0] cmu_icache_invalidate_way;
 input [2:0] cmu_icache_inv_way1;
 input [10:5] cmu_icache_invalidate_index;


 input [1:0]  dec_load_flush_w;


 input [1:0]  dec_tid0_d;
 input [1:0]  dec_tid1_d;
 input [1:0]  dec_br_taken_e;
 input [1:0]  dec_valid_e;


 input       tlu_trap_pc_0_valid;
 input       tlu_trap_pc_1_valid;
 input [1:0] tlu_trap_0_tid;
 input [1:0] tlu_trap_1_tid;
 input [7:0] tlu_flush_ifu;
 input [1:0] tlu_itlb_reload;
 input [7:0] tlu_itlb_bypass;
 input [7:0] tlu_tl_gt_0;


 input [7:0] ibu_empty;
 input [7:0] ibu_room_4ormore;

 input [7:0] cmu_null_st;
 input [7:0] cmu_dupmiss_st;
 input [7:0] cmu_rst_dupmiss;

   
 input       cmu_any_un_cacheable;

 input       cmu_any_data_ready;
 input       cmu_thr0_data_ready;
 input       cmu_thr1_data_ready;
 input       cmu_thr2_data_ready;
 input       cmu_thr3_data_ready;
 input       cmu_thr4_data_ready;
 input       cmu_thr5_data_ready;
 input       cmu_thr6_data_ready;
 input       cmu_thr7_data_ready;
 input       [32:0] cmu_fill_inst0;
 input       [32:0] cmu_fill_inst1;
 input       [32:0] cmu_fill_inst2;
 input       [32:0] cmu_fill_inst3;

 input  [7:0]	lsu_ic_enable;
 input  [7:0]	lsu_ifu_no_miss;
 input  [12:0]  lsu_ifu_ctxt_data;
 input  [2:0]   lsu_ifu_tid_w;
 input          lsu_ifu_wr_p0ctxt;
 input          lsu_ifu_wr_p1ctxt;
 input          lsu_ifu_wr_pid;
 input	[7:0]	lsu_immu_enable;
 input 	        lsu_ifu_ftu_pmen;
 input 	        lsu_ic_pmen;

input        [2:0] cmu_fill_wrway;
input        [3:0] cmu_instr_v;

 input [263:0] cmu_ic_data;

input	[6:0]	mmu_index;		// valid and index from data_access

output [7:0]  ftu_buffer_wr_en_f ;

output [64:0] ifu_rngl_cdbus;
output [2:0]  ftu_rep_way ;
output [39:0] ftu_paddr ;
output [32:0] ftu_instr_0_c ;
output [32:0] ftu_instr_1_c ;
output [32:0] ftu_instr_2_c ;
output [32:0] ftu_instr_3_c ;
output        ftu_exception_valid_c ;
output [4:0]  ftu_instr_exceptions_c ;
output [3:0]  ftu_instr_valid_c ;
output [7:0]  ftu_fetch_thr_c ;
output [7:0]  ftu_curr_fetch_thr_f ;
output [7:0]  ftu_ifu_quiesce ;
output [7:0]  ifu_ibuffer_write_c ;
output	      ftu_ic_no_err_c   ;	     // Data being by_passed does not have an error
output        ftu_bus_0_is_first ;           // bus 0 contains first instr
output        ftu_bus_1_is_first ;           // bus 1 contains first instr
output        ftu_bus_2_is_first ;           // bus 2 contains first instr
output        ftu_bus_3_is_first ;           // bus 3 contains first instr
output        ftu_instr_sf_valid_c ;         


output [2:0] ftu_excp_way_d;
output [2:0] ftu_excp_tid_d;
output       ftu_excp_way_valid_d;


output        ftu_thrx_un_cacheable ;

output        ftu_agc_thr0_cmiss_c ;
output        ftu_agc_thr1_cmiss_c ;
output        ftu_agc_thr2_cmiss_c ;
output        ftu_agc_thr3_cmiss_c ;
output        ftu_agc_thr4_cmiss_c ;
output        ftu_agc_thr5_cmiss_c ;
output        ftu_agc_thr6_cmiss_c ;
output        ftu_agc_thr7_cmiss_c ;

output        ftu_thr0_inv_req_c ;
output        ftu_thr1_inv_req_c ;
output        ftu_thr2_inv_req_c ;
output        ftu_thr3_inv_req_c ;
output        ftu_thr4_inv_req_c ;
output        ftu_thr5_inv_req_c ;
output        ftu_thr6_inv_req_c ;
output        ftu_thr7_inv_req_c ;


output [7:0]  ftu_ibu_redirect_bf;
output        ftu_thr0_redirect_bf ;
output        ftu_thr1_redirect_bf ;
output        ftu_thr2_redirect_bf ;
output        ftu_thr3_redirect_bf ;
output        ftu_thr4_redirect_bf ;
output        ftu_thr5_redirect_bf ;
output        ftu_thr6_redirect_bf ;
output        ftu_thr7_redirect_bf ;

output	[32:0]	ic_dmo_rd_data;

output		scan_out;

// EFU interface

input		efu_spc_fuse_data;
input		efu_spc_fuse_ixfer_en;

input           slow_cmp_sync_en;
input           cmp_slow_sync_en;
input		efu_spc_fuse_iclr;
output		spc_efu_fuse_idata;
output		spc_efu_fuse_ixfer_en;

input		vnw_ary;

assign pce = 1'b1;

assign     io_cmp_sync_en = slow_cmp_sync_en;
assign     cmp_io_sync_en = cmp_slow_sync_en;
assign     ifu_ftu_agd_pc_bf_unused[10:0] = ifu_agd_pc_bf[10:0] ;


ifu_ftu_agd_dp ftu_agd_dp (
  .scan_in(ftu_agd_dp_scanin),
  .scan_out(ftu_agd_dp_scanout),
  .l2clk(l2clk),
  .itc_va({itd_tag[51:32],
	   itd_tag[31:26],
	   itd_tag[23:18],
	   itd_tag[16:14]}),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_muxtest(tcu_muxtest),
  .mbi_addr(mbi_addr[5:0]),
  .mbi_cmpsel(mbi_cmpsel[2:0]),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_icv_read_en(mbi_icv_read_en),
  .ftp_thr0_trprdpc_sel_bf(ftp_thr0_trprdpc_sel_bf[2:0]),
  .ftp_thr1_trprdpc_sel_bf(ftp_thr1_trprdpc_sel_bf[2:0]),
  .ftp_thr2_trprdpc_sel_bf(ftp_thr2_trprdpc_sel_bf[2:0]),
  .ftp_thr3_trprdpc_sel_bf(ftp_thr3_trprdpc_sel_bf[2:0]),
  .ftp_thr4_trprdpc_sel_bf(ftp_thr4_trprdpc_sel_bf[2:0]),
  .ftp_thr5_trprdpc_sel_bf(ftp_thr5_trprdpc_sel_bf[2:0]),
  .ftp_thr6_trprdpc_sel_bf(ftp_thr6_trprdpc_sel_bf[2:0]),
  .ftp_thr7_trprdpc_sel_bf(ftp_thr7_trprdpc_sel_bf[2:0]),
  .agc_thr0_pcf_sel_bf(agc_thr0_pcf_sel_bf[3:0]),
  .agc_thr1_pcf_sel_bf(agc_thr1_pcf_sel_bf[3:0]),
  .agc_thr2_pcf_sel_bf(agc_thr2_pcf_sel_bf[3:0]),
  .agc_thr3_pcf_sel_bf(agc_thr3_pcf_sel_bf[3:0]),
  .agc_thr4_pcf_sel_bf(agc_thr4_pcf_sel_bf[3:0]),
  .agc_thr5_pcf_sel_bf(agc_thr5_pcf_sel_bf[3:0]),
  .agc_thr6_pcf_sel_bf(agc_thr6_pcf_sel_bf[3:0]),
  .agc_thr7_pcf_sel_bf(agc_thr7_pcf_sel_bf[3:0]),
  .agc_thr0_pcf_sel_last_bf(agc_thr0_pcf_sel_last_bf[1:0]),
  .agc_thr1_pcf_sel_last_bf(agc_thr1_pcf_sel_last_bf[1:0]),
  .agc_thr2_pcf_sel_last_bf(agc_thr2_pcf_sel_last_bf[1:0]),
  .agc_thr3_pcf_sel_last_bf(agc_thr3_pcf_sel_last_bf[1:0]),
  .agc_thr4_pcf_sel_last_bf(agc_thr4_pcf_sel_last_bf[1:0]),
  .agc_thr5_pcf_sel_last_bf(agc_thr5_pcf_sel_last_bf[1:0]),
  .agc_thr6_pcf_sel_last_bf(agc_thr6_pcf_sel_last_bf[1:0]),
  .agc_thr7_pcf_sel_last_bf(agc_thr7_pcf_sel_last_bf[1:0]),
  .ftp_thr0_sel_br_bf(ftp_thr0_sel_br_bf),
  .ftp_thr1_sel_br_bf(ftp_thr1_sel_br_bf),
  .ftp_thr2_sel_br_bf(ftp_thr2_sel_br_bf),
  .ftp_thr3_sel_br_bf(ftp_thr3_sel_br_bf),
  .ftp_thr4_sel_br_bf(ftp_thr4_sel_br_bf),
  .ftp_thr5_sel_br_bf(ftp_thr5_sel_br_bf),
  .ftp_thr6_sel_br_bf(ftp_thr6_sel_br_bf),
  .ftp_thr7_sel_br_bf(ftp_thr7_sel_br_bf),
  .agc_sel_inv_index(agc_sel_inv_index[3:0]),
  .agc_pc_sel_for_c(agc_pc_sel_for_c[3:0]),
  .icv_valid_f(icv_valid_f[31:0]),
  .asi_addr_bf(asi_addr_bf[39:3]),
  .agc_thr0_byp_incr_bit5(agc_thr0_byp_incr_bit5),
  .agc_thr1_byp_incr_bit5(agc_thr1_byp_incr_bit5),
  .agc_thr2_byp_incr_bit5(agc_thr2_byp_incr_bit5),
  .agc_thr3_byp_incr_bit5(agc_thr3_byp_incr_bit5),
  .agc_thr4_byp_incr_bit5(agc_thr4_byp_incr_bit5),
  .agc_thr5_byp_incr_bit5(agc_thr5_byp_incr_bit5),
  .agc_thr6_byp_incr_bit5(agc_thr6_byp_incr_bit5),
  .agc_thr7_byp_incr_bit5(agc_thr7_byp_incr_bit5),
  .agc_thr0_byp_pc_update_bf(agc_thr0_byp_pc_update_bf[4:2]),
  .agc_thr1_byp_pc_update_bf(agc_thr1_byp_pc_update_bf[4:2]),
  .agc_thr2_byp_pc_update_bf(agc_thr2_byp_pc_update_bf[4:2]),
  .agc_thr3_byp_pc_update_bf(agc_thr3_byp_pc_update_bf[4:2]),
  .agc_thr4_byp_pc_update_bf(agc_thr4_byp_pc_update_bf[4:2]),
  .agc_thr5_byp_pc_update_bf(agc_thr5_byp_pc_update_bf[4:2]),
  .agc_thr6_byp_pc_update_bf(agc_thr6_byp_pc_update_bf[4:2]),
  .agc_thr7_byp_pc_update_bf(agc_thr7_byp_pc_update_bf[4:2]),
  .ftp_new_thr_sel_bf(ftp_new_thr_sel_bf[7:0]),
  .ftp_ict_data_sel_bf(ftp_ict_data_sel_bf[2:0]),
  .ftp_pc_sel_am(ftp_pc_sel_am[5:0]),
  .ftp_pc_sel_tag_part1(ftp_pc_sel_tag_part1[2:0]),
  .ftp_pc_sel_tag_part2(ftp_pc_sel_tag_part2[3:0]),
  .ftp_pc_sel_tag_pc_bot(ftp_pc_sel_tag_pc_bot[1:0]),
  .ftp_pc_sel_tag_pc_top(ftp_pc_sel_tag_pc_top[1:0]),
  .ftp_any_thr_clken(ftp_any_thr_clken),
  .ftp_sel_icv_mbist_addr(ftp_sel_icv_mbist_addr),
  .ftp_icaddr_sel_first_mux(ftp_icaddr_sel_first_mux[4:0]),
  .tlu_trap_pc_0(tlu_trap_pc_0[47:2]),
  .tlu_trap_pc_1(tlu_trap_pc_1[47:2]),
  .exu_address0_e(exu_address0_e[47:0]),
  .exu_address1_e(exu_address1_e[47:0]),
  .tlu_npc_w(tlu_npc_w[47:2]),
  .cmu_fill_paddr(cmu_fill_paddr[39:5]),
  .asi_wr_data(asi_wr_data[32:0]),
  .cmu_icache_invalidate_index(cmu_icache_invalidate_index[10:6]),
  .cmu_thr0_data_ready(cmu_thr0_data_ready),
  .cmu_thr1_data_ready(cmu_thr1_data_ready),
  .cmu_thr2_data_ready(cmu_thr2_data_ready),
  .cmu_thr3_data_ready(cmu_thr3_data_ready),
  .cmu_thr4_data_ready(cmu_thr4_data_ready),
  .cmu_thr5_data_ready(cmu_thr5_data_ready),
  .cmu_thr6_data_ready(cmu_thr6_data_ready),
  .cmu_thr7_data_ready(cmu_thr7_data_ready),
  .agd_direct_map_rep_way(agd_direct_map_rep_way[2:0]),
  .agd_itlb_valid_f(agd_itlb_valid_f[7:0]),
  .agd_itlb_valid_fast_f(agd_itlb_valid_fast_f[7:0]),
  .agd_itlb_valid_dupl_f(agd_itlb_valid_dupl_f[7:0]),
  .ifu_agd_pc_bf(ifu_agd_pc_bf[47:0]),
  .agd_ict_index_bf(agd_ict_index_bf[10:5]),
  .agd_ic_index_bf(agd_ic_index_bf[10:2]),
  .agd_icv_windex_bf(agd_icv_windex_bf[10:6]),
  .ifu_agd_pc_f(ifu_agd_pc_f[47:2]),
  .agd_thr0_pc_4_2_f(agd_thr0_pc_4_2_f[4:2]),
  .agd_thr1_pc_4_2_f(agd_thr1_pc_4_2_f[4:2]),
  .agd_thr2_pc_4_2_f(agd_thr2_pc_4_2_f[4:2]),
  .agd_thr3_pc_4_2_f(agd_thr3_pc_4_2_f[4:2]),
  .agd_thr4_pc_4_2_f(agd_thr4_pc_4_2_f[4:2]),
  .agd_thr5_pc_4_2_f(agd_thr5_pc_4_2_f[4:2]),
  .agd_thr6_pc_4_2_f(agd_thr6_pc_4_2_f[4:2]),
  .agd_thr7_pc_4_2_f(agd_thr7_pc_4_2_f[4:2]),
  .agd_ict_wrtag_bf(agd_ict_wrtag_bf[29:0]),
  .agd_asi_bist_wrdata(agd_asi_bist_wrdata[32:0]),
  .agd_mbist_wdata_bf(agd_mbist_wdata_bf[7:0]),
  .ftu_paddr(ftu_paddr[12:0]),
  .ftu_mbi_icv_fail(ftu_mbi_icv_fail),
  .agd_va_hole_excp_f(agd_va_hole_excp_f),
  .agd_address0_m(agd_address0_m[4:2]),
  .agd_address1_m(agd_address1_m[4:2])
);
                                                          
ifu_ftu_ctx_dp ftu_ctx_dp ( 
  .wmr_scan_in(ftu_ctx_dp_wmr_scanin),
  .wmr_scan_out(ftu_ctx_dp_wmr_scanout),
  .scan_in(ftu_ctx_dp_scanin),
  .scan_out(ftu_ctx_dp_scanout),
  .l2clk(l2clk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_ifu_ctxt_data(lsu_ifu_ctxt_data[12:0]),
  .agc_thr0_cntx_0_sel_ff(agc_thr0_cntx_0_sel_ff),
  .agc_thr0_cntx_1_sel_ff(agc_thr0_cntx_1_sel_ff),
  .agc_thr1_cntx_0_sel_ff(agc_thr1_cntx_0_sel_ff),
  .agc_thr1_cntx_1_sel_ff(agc_thr1_cntx_1_sel_ff),
  .agc_thr2_cntx_0_sel_ff(agc_thr2_cntx_0_sel_ff),
  .agc_thr2_cntx_1_sel_ff(agc_thr2_cntx_1_sel_ff),
  .agc_thr3_cntx_0_sel_ff(agc_thr3_cntx_0_sel_ff),
  .agc_thr3_cntx_1_sel_ff(agc_thr3_cntx_1_sel_ff),
  .agc_thr4_cntx_0_sel_ff(agc_thr4_cntx_0_sel_ff),
  .agc_thr4_cntx_1_sel_ff(agc_thr4_cntx_1_sel_ff),
  .agc_thr5_cntx_0_sel_ff(agc_thr5_cntx_0_sel_ff),
  .agc_thr5_cntx_1_sel_ff(agc_thr5_cntx_1_sel_ff),
  .agc_thr6_cntx_0_sel_ff(agc_thr6_cntx_0_sel_ff),
  .agc_thr6_cntx_1_sel_ff(agc_thr6_cntx_1_sel_ff),
  .agc_thr7_cntx_0_sel_ff(agc_thr7_cntx_0_sel_ff),
  .agc_thr7_cntx_1_sel_ff(agc_thr7_cntx_1_sel_ff),
  .agc_thr0_cntx_0_sel(agc_thr0_cntx_0_sel[1:0]),
  .agc_thr0_cntx_1_sel(agc_thr0_cntx_1_sel[1:0]),
  .agc_thr1_cntx_0_sel(agc_thr1_cntx_0_sel[1:0]),
  .agc_thr1_cntx_1_sel(agc_thr1_cntx_1_sel[1:0]),
  .agc_thr2_cntx_0_sel(agc_thr2_cntx_0_sel[1:0]),
  .agc_thr2_cntx_1_sel(agc_thr2_cntx_1_sel[1:0]),
  .agc_thr3_cntx_0_sel(agc_thr3_cntx_0_sel[1:0]),
  .agc_thr3_cntx_1_sel(agc_thr3_cntx_1_sel[1:0]),
  .agc_thr4_cntx_0_sel(agc_thr4_cntx_0_sel[1:0]),
  .agc_thr4_cntx_1_sel(agc_thr4_cntx_1_sel[1:0]),
  .agc_thr5_cntx_0_sel(agc_thr5_cntx_0_sel[1:0]),
  .agc_thr5_cntx_1_sel(agc_thr5_cntx_1_sel[1:0]),
  .agc_thr6_cntx_0_sel(agc_thr6_cntx_0_sel[1:0]),
  .agc_thr6_cntx_1_sel(agc_thr6_cntx_1_sel[1:0]),
  .agc_thr7_cntx_0_sel(agc_thr7_cntx_0_sel[1:0]),
  .agc_thr7_cntx_1_sel(agc_thr7_cntx_1_sel[1:0]),
  .ftp_itb_fetch_thr_bf(ftp_itb_fetch_thr_bf[7:0]),
  .itc_thr_to_write(itc_thr_to_write[7:0]),
  .tlu_tl_gt_0(tlu_tl_gt_0[7:0]),
  .ftp_itlb_probe_req_l(ftp_itlb_probe_req_l),
  .ctx_curr_cntx_0_bf(ctx_curr_cntx_0_bf[12:0]),
  .ctx_curr_cntx_1_bf(ctx_curr_cntx_1_bf[12:0]),
  .ctx_cntx_0_to_write_bf(ctx_cntx_0_to_write_bf[13:0]),
  .ctx_cntx_1_to_write_bf(ctx_cntx_1_to_write_bf[13:0])
);
                                                          
ifu_ftu_agc_ctl ftu_agc_ctl( 
  .scan_in(ftu_agc_ctl_scanin),
  .scan_out(ftu_agc_ctl_scanout),
  .l2clk(l2clk),
  .tlb_pgsize({itb_tte_data[17],itb_tte_data[10],itb_tte_data[6]}),
  .itb_tte_tag_parity(itb_tte_data[37]),
  .fill_paddr_bit_5(cmu_fill_paddr[5]) ,
  .tlb_nfo(itb_tte_data[5]) ,
  .itc_real_bf(itd_tag[52]) ,
  .ftu_paddr_unq_39(ftu_paddr_unq[39]) ,
  .asi_vl_arr_data(asi_wr_data[31:30]) ,
  .inv_paddr_bit_5(cmu_icache_invalidate_index[5]),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tlu_trap_pc_0_valid(tlu_trap_pc_0_valid),
  .tlu_retry(tlu_retry[1:0]),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .tlu_trap_pc_1_valid(tlu_trap_pc_1_valid),
  .tlu_ifu_invalidate(tlu_ifu_invalidate[1:0]),
  .tlu_trap_0_tid(tlu_trap_0_tid[1:0]),
  .tlu_trap_1_tid(tlu_trap_1_tid[1:0]),
  .spc_core_running_status(spc_core_running_status[7:0]),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_addr(mbi_addr[8:6]),
  .mbi_cmpsel(mbi_cmpsel[2:0]),
  .mbi_run(mbi_run),
  .mbi_icv_write_en(mbi_icv_write_en),
  .tlu_flush_ifu(tlu_flush_ifu[7:0]),
  .tlu_ifu_hpstate_hpriv(tlu_ifu_hpstate_hpriv[7:0]),
  .tlu_ifu_pstate_priv(tlu_ifu_pstate_priv[7:0]),
  .tlu_cerer_ittp(tlu_cerer_ittp),
  .tlu_cerer_itdp(tlu_cerer_itdp),
  .tlu_cerer_ittm(tlu_cerer_ittm),
  .tlu_cerer_icl2c(tlu_cerer_icl2c),
  .tlu_cerer_icl2u(tlu_cerer_icl2u),
  .tlu_cerer_icl2nd(tlu_cerer_icl2nd),
  .tlu_cerer_icvp(tlu_cerer_icvp),
  .tlu_cerer_ictp(tlu_cerer_ictp),
  .tlu_cerer_ictm(tlu_cerer_ictm),
  .agd_va_hole_excp_f(agd_va_hole_excp_f),
  .agd_itlb_valid_f(agd_itlb_valid_f[7:0]),
  .agd_itlb_valid_dupl_f(agd_itlb_valid_dupl_f[7:0]),
  .asi_ith_det_req(asi_ith_det_req),
  .ftp_asi_tg_wr_req_hold(ftp_asi_tg_wr_req_hold),
  .ftp_itlb_cam_vld_f(ftp_itlb_cam_vld_f),
  .asi_addr_bf(asi_addr_bf[6:3]),
  .asi_way_bf(asi_way_bf[2:0]),
  .ifu_agd_pc_f(ifu_agd_pc_f[47:2]),
  .agd_thr0_pc_4_2_f(agd_thr0_pc_4_2_f[4:2]),
  .agd_thr1_pc_4_2_f(agd_thr1_pc_4_2_f[4:2]),
  .agd_thr2_pc_4_2_f(agd_thr2_pc_4_2_f[4:2]),
  .agd_thr3_pc_4_2_f(agd_thr3_pc_4_2_f[4:2]),
  .agd_thr4_pc_4_2_f(agd_thr4_pc_4_2_f[4:2]),
  .agd_thr5_pc_4_2_f(agd_thr5_pc_4_2_f[4:2]),
  .agd_thr6_pc_4_2_f(agd_thr6_pc_4_2_f[4:2]),
  .agd_thr7_pc_4_2_f(agd_thr7_pc_4_2_f[4:2]),
  .dec_load_flush_w(dec_load_flush_w[1:0]),
  .itc_bypass_bf(itc_bypass_bf),
  .itc_demap_next(itc_demap_next),
  .ftp_curr_fetch_thr_f(ftp_curr_fetch_thr_f[7:0]),
  .ftp_fetch_thr_q_f(ftp_fetch_thr_q_f[7:0]),
  .ftp_fill_req_q_bf(ftp_fill_req_q_bf),
  .ftp_any_thr_clken(ftp_any_thr_clken),
  .err_w0_8b_parity_f(err_w0_8b_parity_f[3:0]),
  .err_w1_8b_parity_f(err_w1_8b_parity_f[3:0]),
  .err_w2_8b_parity_f(err_w2_8b_parity_f[3:0]),
  .err_w3_8b_parity_f(err_w3_8b_parity_f[3:0]),
  .err_w4_8b_parity_f(err_w4_8b_parity_f[3:0]),
  .err_w5_8b_parity_f(err_w5_8b_parity_f[3:0]),
  .err_w6_8b_parity_f(err_w6_8b_parity_f[3:0]),
  .err_w7_8b_parity_f(err_w7_8b_parity_f[3:0]),
  .tsm_thr0_ignore_by_pass(tsm_thr0_ignore_by_pass),
  .tsm_thr1_ignore_by_pass(tsm_thr1_ignore_by_pass),
  .tsm_thr2_ignore_by_pass(tsm_thr2_ignore_by_pass),
  .tsm_thr3_ignore_by_pass(tsm_thr3_ignore_by_pass),
  .tsm_thr4_ignore_by_pass(tsm_thr4_ignore_by_pass),
  .tsm_thr5_ignore_by_pass(tsm_thr5_ignore_by_pass),
  .tsm_thr6_ignore_by_pass(tsm_thr6_ignore_by_pass),
  .tsm_thr7_ignore_by_pass(tsm_thr7_ignore_by_pass),
  .tsm_thr0_no_new_miss(tsm_thr0_no_new_miss),
  .tsm_thr1_no_new_miss(tsm_thr1_no_new_miss),
  .tsm_thr2_no_new_miss(tsm_thr2_no_new_miss),
  .tsm_thr3_no_new_miss(tsm_thr3_no_new_miss),
  .tsm_thr4_no_new_miss(tsm_thr4_no_new_miss),
  .tsm_thr5_no_new_miss(tsm_thr5_no_new_miss),
  .tsm_thr6_no_new_miss(tsm_thr6_no_new_miss),
  .tsm_thr7_no_new_miss(tsm_thr7_no_new_miss),
  .cmu_any_data_ready(cmu_any_data_ready),
  .cmu_any_un_cacheable(cmu_any_un_cacheable),
  .cmu_l2_err(cmu_l2_err[1:0]),
  .cmu_l2miss(cmu_l2miss),
  .cmu_thr0_data_ready(cmu_thr0_data_ready),
  .cmu_thr1_data_ready(cmu_thr1_data_ready),
  .cmu_thr2_data_ready(cmu_thr2_data_ready),
  .cmu_thr3_data_ready(cmu_thr3_data_ready),
  .cmu_thr4_data_ready(cmu_thr4_data_ready),
  .cmu_thr5_data_ready(cmu_thr5_data_ready),
  .cmu_thr6_data_ready(cmu_thr6_data_ready),
  .cmu_thr7_data_ready(cmu_thr7_data_ready),
  .cmu_fill_wrway(cmu_fill_wrway[2:0]),
  .cmu_icache_invalidate(cmu_icache_invalidate),
  .cmu_evic_invalidate(cmu_evic_invalidate),
  .cmu_icache_invalidate_way(cmu_icache_invalidate_way[2:0]),
  .cmu_icache_inv_way1(cmu_icache_inv_way1[2:0]),
  .cmu_instr_v(cmu_instr_v[3:0]),
  .dec_br_taken_e(dec_br_taken_e[1:0]),
  .dec_valid_e(dec_valid_e[1:0]),
  .ftp_tid0_e(ftp_tid0_e[1:0]),
  .ftp_tid1_e(ftp_tid1_e[1:0]),
  .ftp_fetch_v_f(ftp_fetch_v_f),
  .itb_chit_c(itb_chit_c),
  .itb_cam_hit_c(itb_cam_hit_c),
  .itb_tte_p_c(itb_tte_p_c),
  .itb_itb_mhit_c(itb_itb_mhit_c),
  .itb_tte_data_parity(itb_tte_data_parity),
  .itb_icd_waysel_c(itb_icd_waysel_c[7:0]),
  .lsu_ifu_tid_w(lsu_ifu_tid_w[2:0]),
  .lsu_ifu_wr_p0ctxt(lsu_ifu_wr_p0ctxt),
  .lsu_ifu_wr_p1ctxt(lsu_ifu_wr_p1ctxt),
  .lsu_ifu_no_miss(lsu_ifu_no_miss[7:0]),
  .lsu_ic_enable(lsu_ic_enable[7:0]),
  .cmu_inval_ack(cmu_inval_ack[7:0]),
  .ftp_asi_mbist_access_bf(ftp_asi_mbist_access_bf),
  .itd_prty_256m(itd_prty_256m),
  .itd_prty_4m(itd_prty_4m),
  .itd_prty_64k(itd_prty_64k),
  .itd_prty_8k(itd_prty_8k),
  .itd_prty_ctxt0(itd_prty_ctxt0),
  .itd_prty_ctxt1(itd_prty_ctxt1),
  .tlb_context0_hit(tlb_context0_hit),
  .ftu_buffer_wr_en_f(ftu_buffer_wr_en_f[7:0]),
  .agc_itb_tag_perr_c(agc_itb_tag_perr_c),
  .agc_vl_data_c(agc_vl_data_c[1:0]),
  .agc_asi_sel_word_c(agc_asi_sel_word_c[3:0]),
  .agc_sel_tg_data_f(agc_sel_tg_data_f[7:0]),
  .agc_word_en_bf(agc_word_en_bf[7:0]),
  .agc_by_pass_update_lru_bf(agc_by_pass_update_lru_bf[7:0]),
  .agc_invalidation_req_ff(agc_invalidation_req_ff[7:0]),
  .agc_any_invalidation_req_f(agc_any_invalidation_req_f),
  .agc_thr0_sf_valid_f(agc_thr0_sf_valid_f),
  .agc_thr1_sf_valid_f(agc_thr1_sf_valid_f),
  .agc_thr2_sf_valid_f(agc_thr2_sf_valid_f),
  .agc_thr3_sf_valid_f(agc_thr3_sf_valid_f),
  .agc_thr4_sf_valid_f(agc_thr4_sf_valid_f),
  .agc_thr5_sf_valid_f(agc_thr5_sf_valid_f),
  .agc_thr6_sf_valid_f(agc_thr6_sf_valid_f),
  .agc_thr7_sf_valid_f(agc_thr7_sf_valid_f),
  .agc_thr0_micro_flush_unq_c(agc_thr0_micro_flush_unq_c),
  .agc_thr1_micro_flush_unq_c(agc_thr1_micro_flush_unq_c),
  .agc_thr2_micro_flush_unq_c(agc_thr2_micro_flush_unq_c),
  .agc_thr3_micro_flush_unq_c(agc_thr3_micro_flush_unq_c),
  .agc_thr4_micro_flush_unq_c(agc_thr4_micro_flush_unq_c),
  .agc_thr5_micro_flush_unq_c(agc_thr5_micro_flush_unq_c),
  .agc_thr6_micro_flush_unq_c(agc_thr6_micro_flush_unq_c),
  .agc_thr7_micro_flush_unq_c(agc_thr7_micro_flush_unq_c),
  .agc_thr0_err_detect_c(agc_thr0_err_detect_c),
  .agc_thr1_err_detect_c(agc_thr1_err_detect_c),
  .agc_thr2_err_detect_c(agc_thr2_err_detect_c),
  .agc_thr3_err_detect_c(agc_thr3_err_detect_c),
  .agc_thr4_err_detect_c(agc_thr4_err_detect_c),
  .agc_thr5_err_detect_c(agc_thr5_err_detect_c),
  .agc_thr6_err_detect_c(agc_thr6_err_detect_c),
  .agc_thr7_err_detect_c(agc_thr7_err_detect_c),
  .agc_thr0_cmiss_stm_c(agc_thr0_cmiss_stm_c),
  .agc_thr1_cmiss_stm_c(agc_thr1_cmiss_stm_c),
  .agc_thr2_cmiss_stm_c(agc_thr2_cmiss_stm_c),
  .agc_thr3_cmiss_stm_c(agc_thr3_cmiss_stm_c),
  .agc_thr4_cmiss_stm_c(agc_thr4_cmiss_stm_c),
  .agc_thr5_cmiss_stm_c(agc_thr5_cmiss_stm_c),
  .agc_thr6_cmiss_stm_c(agc_thr6_cmiss_stm_c),
  .agc_thr7_cmiss_stm_c(agc_thr7_cmiss_stm_c),
  .ftu_agc_thr0_cmiss_c(ftu_agc_thr0_cmiss_c),
  .ftu_agc_thr1_cmiss_c(ftu_agc_thr1_cmiss_c),
  .ftu_agc_thr2_cmiss_c(ftu_agc_thr2_cmiss_c),
  .ftu_agc_thr3_cmiss_c(ftu_agc_thr3_cmiss_c),
  .ftu_agc_thr4_cmiss_c(ftu_agc_thr4_cmiss_c),
  .ftu_agc_thr5_cmiss_c(ftu_agc_thr5_cmiss_c),
  .ftu_agc_thr6_cmiss_c(ftu_agc_thr6_cmiss_c),
  .ftu_agc_thr7_cmiss_c(ftu_agc_thr7_cmiss_c),
  .ftu_thr0_inv_req_c(ftu_thr0_inv_req_c),
  .ftu_thr1_inv_req_c(ftu_thr1_inv_req_c),
  .ftu_thr2_inv_req_c(ftu_thr2_inv_req_c),
  .ftu_thr3_inv_req_c(ftu_thr3_inv_req_c),
  .ftu_thr4_inv_req_c(ftu_thr4_inv_req_c),
  .ftu_thr5_inv_req_c(ftu_thr5_inv_req_c),
  .ftu_thr6_inv_req_c(ftu_thr6_inv_req_c),
  .ftu_thr7_inv_req_c(ftu_thr7_inv_req_c),
  .ifu_ibuffer_write_c(ifu_ibuffer_write_c[7:0]),
  .ftu_fetch_thr_c(ftu_fetch_thr_c[7:0]),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .ftu_excp_way_d(ftu_excp_way_d[2:0]),
  .ftu_excp_tid_d(ftu_excp_tid_d[2:0]),
  .ftu_excp_way_valid_d(ftu_excp_way_valid_d),
  .agc_fill_wrway_bf(agc_fill_wrway_bf[2:0]),
  .agc_sel_inv_index(agc_sel_inv_index[3:0]),
  .agc_thr0_lsu_no_ic_miss(agc_thr0_lsu_no_ic_miss),
  .agc_thr1_lsu_no_ic_miss(agc_thr1_lsu_no_ic_miss),
  .agc_thr2_lsu_no_ic_miss(agc_thr2_lsu_no_ic_miss),
  .agc_thr3_lsu_no_ic_miss(agc_thr3_lsu_no_ic_miss),
  .agc_thr4_lsu_no_ic_miss(agc_thr4_lsu_no_ic_miss),
  .agc_thr5_lsu_no_ic_miss(agc_thr5_lsu_no_ic_miss),
  .agc_thr6_lsu_no_ic_miss(agc_thr6_lsu_no_ic_miss),
  .agc_thr7_lsu_no_ic_miss(agc_thr7_lsu_no_ic_miss),
  .agc_thr0_itb_miss_c(agc_thr0_itb_miss_c),
  .agc_thr1_itb_miss_c(agc_thr1_itb_miss_c),
  .agc_thr2_itb_miss_c(agc_thr2_itb_miss_c),
  .agc_thr3_itb_miss_c(agc_thr3_itb_miss_c),
  .agc_thr4_itb_miss_c(agc_thr4_itb_miss_c),
  .agc_thr5_itb_miss_c(agc_thr5_itb_miss_c),
  .agc_thr6_itb_miss_c(agc_thr6_itb_miss_c),
  .agc_thr7_itb_miss_c(agc_thr7_itb_miss_c),
  .ftu_ic_no_err_c(ftu_ic_no_err_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first),
  .ftu_instr_valid_c(ftu_instr_valid_c[3:0]),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_instr_exceptions_c(ftu_instr_exceptions_c[4:0]),
  .agc_thr0_pcf_sel_bf(agc_thr0_pcf_sel_bf[3:0]),
  .agc_thr1_pcf_sel_bf(agc_thr1_pcf_sel_bf[3:0]),
  .agc_thr2_pcf_sel_bf(agc_thr2_pcf_sel_bf[3:0]),
  .agc_thr3_pcf_sel_bf(agc_thr3_pcf_sel_bf[3:0]),
  .agc_thr4_pcf_sel_bf(agc_thr4_pcf_sel_bf[3:0]),
  .agc_thr5_pcf_sel_bf(agc_thr5_pcf_sel_bf[3:0]),
  .agc_thr6_pcf_sel_bf(agc_thr6_pcf_sel_bf[3:0]),
  .agc_thr7_pcf_sel_bf(agc_thr7_pcf_sel_bf[3:0]),
  .agc_thr0_pcf_sel_last_bf(agc_thr0_pcf_sel_last_bf[1:0]),
  .agc_thr1_pcf_sel_last_bf(agc_thr1_pcf_sel_last_bf[1:0]),
  .agc_thr2_pcf_sel_last_bf(agc_thr2_pcf_sel_last_bf[1:0]),
  .agc_thr3_pcf_sel_last_bf(agc_thr3_pcf_sel_last_bf[1:0]),
  .agc_thr4_pcf_sel_last_bf(agc_thr4_pcf_sel_last_bf[1:0]),
  .agc_thr5_pcf_sel_last_bf(agc_thr5_pcf_sel_last_bf[1:0]),
  .agc_thr6_pcf_sel_last_bf(agc_thr6_pcf_sel_last_bf[1:0]),
  .agc_thr7_pcf_sel_last_bf(agc_thr7_pcf_sel_last_bf[1:0]),
  .agc_icv_wr_req_bf(agc_icv_wr_req_bf),
  .agc_icv_wrdata_bf(agc_icv_wrdata_bf[31:0]),
  .agc_icv_wren_bf(agc_icv_wren_bf[31:0]),
  .ftu_thr0_redirect_bf(ftu_thr0_redirect_bf),
  .ftu_thr1_redirect_bf(ftu_thr1_redirect_bf),
  .ftu_thr2_redirect_bf(ftu_thr2_redirect_bf),
  .ftu_thr3_redirect_bf(ftu_thr3_redirect_bf),
  .ftu_thr4_redirect_bf(ftu_thr4_redirect_bf),
  .ftu_thr5_redirect_bf(ftu_thr5_redirect_bf),
  .ftu_thr6_redirect_bf(ftu_thr6_redirect_bf),
  .ftu_thr7_redirect_bf(ftu_thr7_redirect_bf),
  .ftu_ibu_redirect_bf(ftu_ibu_redirect_bf[7:0]),
  .agc_thr0_tlu_redirect_bf(agc_thr0_tlu_redirect_bf),
  .agc_thr1_tlu_redirect_bf(agc_thr1_tlu_redirect_bf),
  .agc_thr2_tlu_redirect_bf(agc_thr2_tlu_redirect_bf),
  .agc_thr3_tlu_redirect_bf(agc_thr3_tlu_redirect_bf),
  .agc_thr4_tlu_redirect_bf(agc_thr4_tlu_redirect_bf),
  .agc_thr5_tlu_redirect_bf(agc_thr5_tlu_redirect_bf),
  .agc_thr6_tlu_redirect_bf(agc_thr6_tlu_redirect_bf),
  .agc_thr7_tlu_redirect_bf(agc_thr7_tlu_redirect_bf),
  .agc_kill_fetch_cv_c(agc_kill_fetch_cv_c),
  .agc_pc_sel_for_c(agc_pc_sel_for_c[3:0]),
  .agc_instr_bp_sel_c(agc_instr_bp_sel_c[2:0]),
  .agc_thr0_byp_incr_bit5(agc_thr0_byp_incr_bit5),
  .agc_thr1_byp_incr_bit5(agc_thr1_byp_incr_bit5),
  .agc_thr2_byp_incr_bit5(agc_thr2_byp_incr_bit5),
  .agc_thr3_byp_incr_bit5(agc_thr3_byp_incr_bit5),
  .agc_thr4_byp_incr_bit5(agc_thr4_byp_incr_bit5),
  .agc_thr5_byp_incr_bit5(agc_thr5_byp_incr_bit5),
  .agc_thr6_byp_incr_bit5(agc_thr6_byp_incr_bit5),
  .agc_thr7_byp_incr_bit5(agc_thr7_byp_incr_bit5),
  .agc_thr0_byp_pc_update_bf(agc_thr0_byp_pc_update_bf[4:2]),
  .agc_thr1_byp_pc_update_bf(agc_thr1_byp_pc_update_bf[4:2]),
  .agc_thr2_byp_pc_update_bf(agc_thr2_byp_pc_update_bf[4:2]),
  .agc_thr3_byp_pc_update_bf(agc_thr3_byp_pc_update_bf[4:2]),
  .agc_thr4_byp_pc_update_bf(agc_thr4_byp_pc_update_bf[4:2]),
  .agc_thr5_byp_pc_update_bf(agc_thr5_byp_pc_update_bf[4:2]),
  .agc_thr6_byp_pc_update_bf(agc_thr6_byp_pc_update_bf[4:2]),
  .agc_thr7_byp_pc_update_bf(agc_thr7_byp_pc_update_bf[4:2]),
  .agc_thr0_cntx_0_sel(agc_thr0_cntx_0_sel[1:0]),
  .agc_thr0_cntx_1_sel(agc_thr0_cntx_1_sel[1:0]),
  .agc_thr1_cntx_0_sel(agc_thr1_cntx_0_sel[1:0]),
  .agc_thr1_cntx_1_sel(agc_thr1_cntx_1_sel[1:0]),
  .agc_thr2_cntx_0_sel(agc_thr2_cntx_0_sel[1:0]),
  .agc_thr2_cntx_1_sel(agc_thr2_cntx_1_sel[1:0]),
  .agc_thr3_cntx_0_sel(agc_thr3_cntx_0_sel[1:0]),
  .agc_thr3_cntx_1_sel(agc_thr3_cntx_1_sel[1:0]),
  .agc_thr4_cntx_0_sel(agc_thr4_cntx_0_sel[1:0]),
  .agc_thr4_cntx_1_sel(agc_thr4_cntx_1_sel[1:0]),
  .agc_thr5_cntx_0_sel(agc_thr5_cntx_0_sel[1:0]),
  .agc_thr5_cntx_1_sel(agc_thr5_cntx_1_sel[1:0]),
  .agc_thr6_cntx_0_sel(agc_thr6_cntx_0_sel[1:0]),
  .agc_thr6_cntx_1_sel(agc_thr6_cntx_1_sel[1:0]),
  .agc_thr7_cntx_0_sel(agc_thr7_cntx_0_sel[1:0]),
  .agc_thr7_cntx_1_sel(agc_thr7_cntx_1_sel[1:0]),
  .agc_thr0_cntx_0_sel_ff(agc_thr0_cntx_0_sel_ff),
  .agc_thr0_cntx_1_sel_ff(agc_thr0_cntx_1_sel_ff),
  .agc_thr1_cntx_0_sel_ff(agc_thr1_cntx_0_sel_ff),
  .agc_thr1_cntx_1_sel_ff(agc_thr1_cntx_1_sel_ff),
  .agc_thr2_cntx_0_sel_ff(agc_thr2_cntx_0_sel_ff),
  .agc_thr2_cntx_1_sel_ff(agc_thr2_cntx_1_sel_ff),
  .agc_thr3_cntx_0_sel_ff(agc_thr3_cntx_0_sel_ff),
  .agc_thr3_cntx_1_sel_ff(agc_thr3_cntx_1_sel_ff),
  .agc_thr4_cntx_0_sel_ff(agc_thr4_cntx_0_sel_ff),
  .agc_thr4_cntx_1_sel_ff(agc_thr4_cntx_1_sel_ff),
  .agc_thr5_cntx_0_sel_ff(agc_thr5_cntx_0_sel_ff),
  .agc_thr5_cntx_1_sel_ff(agc_thr5_cntx_1_sel_ff),
  .agc_thr6_cntx_0_sel_ff(agc_thr6_cntx_0_sel_ff),
  .agc_thr6_cntx_1_sel_ff(agc_thr6_cntx_1_sel_ff),
  .agc_thr7_cntx_0_sel_ff(agc_thr7_cntx_0_sel_ff),
  .agc_thr7_cntx_1_sel_ff(agc_thr7_cntx_1_sel_ff),
  .ftu_mbi_tlb_cam_hit(ftu_mbi_tlb_cam_hit),
  .ftu_mbi_tlb_ctxt0_hit(ftu_mbi_tlb_ctxt0_hit),
  .ftu_mbi_tlb_cam_mhit(ftu_mbi_tlb_cam_mhit));                                                        

ifu_ftu_cms_ctl ftu_cms_ctl( 
  .scan_in(ftu_cms_ctl_scanin),
  .scan_out(ftu_cms_ctl_scanout),
  .l2clk(l2clk),
  .itb_tte_cp_c(itb_tte_data[3]),
  .cmu_ic_data_parity({cmu_ic_data[263],cmu_ic_data[230],cmu_ic_data[197],cmu_ic_data[164],
                       cmu_ic_data[131],cmu_ic_data[98],cmu_ic_data[65],cmu_ic_data[32]}),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .lsu_ic_enable(lsu_ic_enable[7:0]),
  .lsu_ifu_direct_map(lsu_ifu_direct_map),
  .agd_direct_map_rep_way(agd_direct_map_rep_way[2:0]),
  .ftp_curr_fetch_thr_f(ftp_curr_fetch_thr_f[7:0]),
  .ftu_agc_thr0_cmiss_c(ftu_agc_thr0_cmiss_c),
  .ftu_agc_thr1_cmiss_c(ftu_agc_thr1_cmiss_c),
  .ftu_agc_thr2_cmiss_c(ftu_agc_thr2_cmiss_c),
  .ftu_agc_thr3_cmiss_c(ftu_agc_thr3_cmiss_c),
  .ftu_agc_thr4_cmiss_c(ftu_agc_thr4_cmiss_c),
  .ftu_agc_thr5_cmiss_c(ftu_agc_thr5_cmiss_c),
  .ftu_agc_thr6_cmiss_c(ftu_agc_thr6_cmiss_c),
  .ftu_agc_thr7_cmiss_c(ftu_agc_thr7_cmiss_c),
  .ftu_paddr_unq(ftu_paddr_unq[39:37]),
  .agc_any_invalidation_req_f(agc_any_invalidation_req_f),
  .itc_bypass_bf(itc_bypass_bf),
  .cmu_l2_err(cmu_l2_err[1:0]),
  .tlu_cerer_icl2u(tlu_cerer_icl2u),
  .tlu_cerer_icl2nd(tlu_cerer_icl2nd),
  .ftu_thrx_un_cacheable(ftu_thrx_un_cacheable),
  .ftu_rep_way(ftu_rep_way[2:0]),
  .cms_ic_modified_parity(cms_ic_modified_parity[7:0]),
  .ftu_paddr(ftu_paddr[39:37])) ;


////////////////////////////////////////////////////////////////////////
// Icache Data                                                        //
////////////////////////////////////////////////////////////////////////

assign word2_reordered[32:0] = {cmu_ic_data[66],cmu_ic_data[67],cmu_ic_data[68],cmu_ic_data[69],
                                cmu_ic_data[70],cmu_ic_data[71],cmu_ic_data[72],cmu_ic_data[73],
                                cmu_ic_data[74],cmu_ic_data[75],cmu_ic_data[76],cmu_ic_data[77],
                                cmu_ic_data[78],cmu_ic_data[79],cmu_ic_data[80],cmu_ic_data[81],
                                cmu_ic_data[82],cmu_ic_data[83],cmu_ic_data[84],cmu_ic_data[85],
                                cmu_ic_data[86],cmu_ic_data[87],cmu_ic_data[88],cmu_ic_data[89],
                                cmu_ic_data[90],cmu_ic_data[91],cmu_ic_data[92],cmu_ic_data[93],
                                cmu_ic_data[94],cmu_ic_data[95],cmu_ic_data[96],cmu_ic_data[97],
                                cms_ic_modified_parity[2]};

assign word3_reordered[32:0] = {cmu_ic_data[99],cmu_ic_data[100],cmu_ic_data[101],cmu_ic_data[102],
                                cmu_ic_data[103],cmu_ic_data[104],cmu_ic_data[105],cmu_ic_data[106],
                                cmu_ic_data[107],cmu_ic_data[108],cmu_ic_data[109],cmu_ic_data[110],
                                cmu_ic_data[111],cmu_ic_data[112],cmu_ic_data[113],cmu_ic_data[114],
                                cmu_ic_data[115],cmu_ic_data[116],cmu_ic_data[117],cmu_ic_data[118],
                                cmu_ic_data[119],cmu_ic_data[120],cmu_ic_data[121],cmu_ic_data[122],
                                cmu_ic_data[123],cmu_ic_data[124],cmu_ic_data[125],cmu_ic_data[126],
                                cmu_ic_data[127],cmu_ic_data[128],cmu_ic_data[129],cmu_ic_data[130],
                                cms_ic_modified_parity[3]};

assign word6_reordered[32:0] = {cmu_ic_data[198],cmu_ic_data[199],cmu_ic_data[200],cmu_ic_data[201],
                                cmu_ic_data[202],cmu_ic_data[203],cmu_ic_data[204],cmu_ic_data[205],
                                cmu_ic_data[206],cmu_ic_data[207],cmu_ic_data[208],cmu_ic_data[209],
                                cmu_ic_data[210],cmu_ic_data[211],cmu_ic_data[212],cmu_ic_data[213],
                                cmu_ic_data[214],cmu_ic_data[215],cmu_ic_data[216],cmu_ic_data[217],
                                cmu_ic_data[218],cmu_ic_data[219],cmu_ic_data[220],cmu_ic_data[221],
                                cmu_ic_data[222],cmu_ic_data[223],cmu_ic_data[224],cmu_ic_data[225],
                                cmu_ic_data[226],cmu_ic_data[227],cmu_ic_data[228],cmu_ic_data[229],
                                cms_ic_modified_parity[6]};

assign word7_reordered[32:0] = {cmu_ic_data[231],cmu_ic_data[232],cmu_ic_data[233],cmu_ic_data[234],
                                cmu_ic_data[235],cmu_ic_data[236],cmu_ic_data[237],cmu_ic_data[238],
                                cmu_ic_data[239],cmu_ic_data[240],cmu_ic_data[241],cmu_ic_data[242],
                                cmu_ic_data[243],cmu_ic_data[244],cmu_ic_data[245],cmu_ic_data[246],
                                cmu_ic_data[247],cmu_ic_data[248],cmu_ic_data[249],cmu_ic_data[250],
                                cmu_ic_data[251],cmu_ic_data[252],cmu_ic_data[253],cmu_ic_data[254],
                                cmu_ic_data[255],cmu_ic_data[256],cmu_ic_data[257],cmu_ic_data[258],
                                cmu_ic_data[259],cmu_ic_data[260],cmu_ic_data[261],cmu_ic_data[262],
                                cms_ic_modified_parity[7]};

n2_icd_sp_16p5kb_cust ftu_icd_cust( 
   .red_en_in({2{hdr_sram_rvalue[0]}}) ,
   .red_d_in(hdr_sram_rvalue[5:1]) ,
   .rid_in(hdr_sram_rid[3:0]) ,
   .red_wen(hdr_sram_wr_en) ,
   .red_arst(hdr_sram_red_clr) ,
   .red_d_out(sram_hdr_read_data[5:1]),
   .red_en_out({red_en_unused,sram_hdr_read_data[0]}),
   .tcu_aclk(spc_aclk),
   .tcu_bclk(spc_bclk),
   .cmu_ic_data({word7_reordered[32:0],
                 word6_reordered[32:0],
                 cms_ic_modified_parity[5],cmu_ic_data[196:165],
                 cms_ic_modified_parity[4],cmu_ic_data[163:132],
                 word3_reordered[32:0],
                 word2_reordered[32:0],
                 cms_ic_modified_parity[1],cmu_ic_data[64:33]  ,
                 cms_ic_modified_parity[0],cmu_ic_data[31:0]  }),
   .icd_bus_2_instr_c({icd_bus_2_instr_c [0],icd_bus_2_instr_c [1],icd_bus_2_instr_c [2],icd_bus_2_instr_c [3],
                       icd_bus_2_instr_c [4],icd_bus_2_instr_c [5],icd_bus_2_instr_c [6],icd_bus_2_instr_c [7],
                       icd_bus_2_instr_c [8],icd_bus_2_instr_c [9],icd_bus_2_instr_c[10],icd_bus_2_instr_c[11],
                       icd_bus_2_instr_c[12],icd_bus_2_instr_c[13],icd_bus_2_instr_c[14],icd_bus_2_instr_c[15],
                       icd_bus_2_instr_c[16],icd_bus_2_instr_c[17],icd_bus_2_instr_c[18],icd_bus_2_instr_c[19],
                       icd_bus_2_instr_c[20],icd_bus_2_instr_c[21],icd_bus_2_instr_c[22],icd_bus_2_instr_c[23],
                       icd_bus_2_instr_c[24],icd_bus_2_instr_c[25],icd_bus_2_instr_c[26],icd_bus_2_instr_c[27],
                       icd_bus_2_instr_c[28],icd_bus_2_instr_c[29],icd_bus_2_instr_c[30],icd_bus_2_instr_c[31],
                       icd_bus_2_instr_c[32]}),
   .icd_bus_3_instr_c({icd_bus_3_instr_c [0],icd_bus_3_instr_c [1],icd_bus_3_instr_c [2],icd_bus_3_instr_c [3],
                       icd_bus_3_instr_c [4],icd_bus_3_instr_c [5],icd_bus_3_instr_c [6],icd_bus_3_instr_c [7],
                       icd_bus_3_instr_c [8],icd_bus_3_instr_c [9],icd_bus_3_instr_c[10],icd_bus_3_instr_c[11],
                       icd_bus_3_instr_c[12],icd_bus_3_instr_c[13],icd_bus_3_instr_c[14],icd_bus_3_instr_c[15],
                       icd_bus_3_instr_c[16],icd_bus_3_instr_c[17],icd_bus_3_instr_c[18],icd_bus_3_instr_c[19],
                       icd_bus_3_instr_c[20],icd_bus_3_instr_c[21],icd_bus_3_instr_c[22],icd_bus_3_instr_c[23],
                       icd_bus_3_instr_c[24],icd_bus_3_instr_c[25],icd_bus_3_instr_c[26],icd_bus_3_instr_c[27],
                       icd_bus_3_instr_c[28],icd_bus_3_instr_c[29],icd_bus_3_instr_c[30],icd_bus_3_instr_c[31],
                       icd_bus_3_instr_c[32]}),
   .scan_in(ftu_icd_cust_scanin),
   .scan_out(ftu_icd_cust_scanout),
   .l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .tcu_scan_en(tcu_scan_en),
  .ftp_icd_quad_0_en_bf(ftp_icd_quad_0_en_bf),
  .ftp_icd_quad_1_en_bf(ftp_icd_quad_1_en_bf),
  .ftp_icd_quad_2_en_bf(ftp_icd_quad_2_en_bf),
  .ftp_icd_quad_3_en_bf(ftp_icd_quad_3_en_bf),
  .agd_ic_index_bf(agd_ic_index_bf[10:2]),
  .agc_fill_wrway_bf(agc_fill_wrway_bf[2:0]),
  .agd_asi_bist_wrdata(agd_asi_bist_wrdata[32:0]),
  .itb_icd_waysel_c(itb_icd_waysel_c[7:0]),
  .agc_word_en_bf(agc_word_en_bf[7:0]),
  .ftp_ic_rd_req_bf(ftp_ic_rd_req_bf),
  .ftp_ic_wr_req_bf(ftp_ic_wr_req_bf),
  .ftp_ic_wr_ps_en_bf(ftp_ic_wr_ps_en_bf),
  .ftp_asi_mbist_access_bf(ftp_asi_mbist_access_bf),
  .vnw_ary(vnw_ary),
  .icd_bus_0_instr_c(icd_bus_0_instr_c[32:0]),
  .icd_bus_1_instr_c(icd_bus_1_instr_c[32:0]) 
) ;

////////////////////////////////////////////////////////////////////////
// Redundancy header for I$
////////////////////////////////////////////////////////////////////////
ifu_ftu_red_ctl hdr (
   .scan_in(hdr_scanin),
   .scan_out(hdr_scanout),
   .l2clk		(l2clk),
  .efu_spc_fuse_data(efu_spc_fuse_data),
  .efu_spc_fuse_ixfer_en(efu_spc_fuse_ixfer_en),
  .efu_spc_fuse_iclr(efu_spc_fuse_iclr),
  .io_cmp_sync_en(io_cmp_sync_en),
  .cmp_io_sync_en(cmp_io_sync_en),
  .spc_efu_fuse_idata(spc_efu_fuse_idata),
  .spc_efu_fuse_ixfer_en(spc_efu_fuse_ixfer_en),
  .hdr_sram_rvalue(hdr_sram_rvalue[5:0]),
  .hdr_sram_rid(hdr_sram_rid[3:0]),
  .hdr_sram_wr_en(hdr_sram_wr_en),
  .hdr_sram_red_clr(hdr_sram_red_clr),
  .sram_hdr_read_data(sram_hdr_read_data[5:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en) 
);

////////////////////////////////////////////////////////////////////////
// tag ARRAYS                                                      //
////////////////////////////////////////////////////////////////////////
n2_ict_sp_1920b_cust  ftu_ict_cust  (
   .tcu_aclk(spc_aclk),
   .tcu_bclk(spc_bclk),
   .agd_ic_index_bf(agd_ict_index_bf[10:5]), 
   .scan_in(ftu_ict_cust_scanin),
   .scan_out(ftu_ict_cust_scanout),
   .l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .agc_fill_wrway_bf(agc_fill_wrway_bf[2:0]),
  .ftp_tg_rd_req_bf(ftp_tg_rd_req_bf),
  .ftp_tg_wr_req_bf(ftp_tg_wr_req_bf),
  .ftp_tg_clk_en(ftp_tg_clk_en),
  .agd_ict_wrtag_bf(agd_ict_wrtag_bf[29:0]),
  .ict_itlb_way_0_tag_f(ict_itlb_way_0_tag_f[29:0]),
  .ict_itlb_way_1_tag_f(ict_itlb_way_1_tag_f[29:0]),
  .ict_itlb_way_2_tag_f(ict_itlb_way_2_tag_f[29:0]),
  .ict_itlb_way_3_tag_f(ict_itlb_way_3_tag_f[29:0]),
  .ict_itlb_way_4_tag_f(ict_itlb_way_4_tag_f[29:0]),
  .ict_itlb_way_5_tag_f(ict_itlb_way_5_tag_f[29:0]),
  .ict_itlb_way_6_tag_f(ict_itlb_way_6_tag_f[29:0]),
  .ict_itlb_way_7_tag_f(ict_itlb_way_7_tag_f[29:0]) 
  );


////////////////////////////////////////////////////////////////////////
// icache valid bits.                                              //
////////////////////////////////////////////////////////////////////////
n2_dva_dp_32x32_cust  ftu_icv_cust ( 
   .tcu_aclk(spc_aclk),
   .tcu_bclk(spc_bclk),
   .scan_in(ftu_icv_cust_scanin),
   .scan_out(ftu_icv_cust_scanout),
   .l2clk(l2clk),
   .bit_wen(agc_icv_wren_bf[31:0]),
   .wr_en(agc_icv_wr_req_bf),
   .rd_en(ftp_iv_rd_req_bf),
   .rd_addr(agd_ic_index_bf[`IC_ARR_INDX_HI:6]) ,
   .wr_addr(agd_icv_windex_bf[`IC_ARR_INDX_HI:6]), 
   .din(agc_icv_wrdata_bf[31:0]),
   .dout(icv_valid_f[31:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_scan_en(tcu_scan_en),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .pce(pce) 
  
   );


////////////////////////////////////////////////////////////////////////
// ITLB                                                               //
////////////////////////////////////////////////////////////////////////
assign tte_ubit = itc_tte_ubit;


n2_tlb_tl_64x59_cust ftu_itb_cust ( 
   .tcu_aclk(spc_aclk),
   .tcu_bclk(spc_bclk),
   .scan_in(ftu_itb_cust_scanin),
   .scan_out(ftu_itb_cust_scanout),
   .l2clk(l2clk),
// Inputs

   .disable_clear_ubit  (itc_dis_clr_ubit),
   .tlb_bypass		(itc_bypass_bf),
   .tlb_wr_vld		(itc_wr_u_en),
   .tlb_rd_vld		(itc_itlb_rd_vld_bf),
   .tlb_cam_vld		(ftp_itlb_cam_vld_bf),
   .tlb_rw_index	(itd_rw_index[5:0]),
   .tlb_rw_index_vld	(itc_rw_index_vld),
   .tlb_demap		(itc_demap),
   .tlb_demap_context	(itc_demap_context),
   .tlb_demap_all	(itc_demap_all),
   .tlb_demap_real	(itc_demap_real),
   // Separate page size mask from tag proper
   .tte_tag		({itd_tag[68:52],ifu_agd_pc_bf[47:22],itd_tag[24],
			  ifu_agd_pc_bf[21:16],ifu_agd_pc_bf[15:13],
			  itd_tag[12:0]}),
   .tte_page_size_mask	({itd_tag[25],itd_tag[17],itd_tag[13]}),
   .tte_data		(itd_data[37:0]),
   .tlb_va		(ifu_agd_pc_bf[12:11]),
   .cache_ptag_w0	(ict_itlb_way_0_tag_f_rep0[28:0]),
   .cache_ptag_w1	(ict_itlb_way_1_tag_f_rep0[28:0]),
   .cache_ptag_w2	(ict_itlb_way_2_tag_f_rep0[28:0]),
   .cache_ptag_w3	(ict_itlb_way_3_tag_f_rep0[28:0]),
   .cache_ptag_w4	(ict_itlb_way_4_tag_f_rep0[28:0]),
   .cache_ptag_w5	(ict_itlb_way_5_tag_f_rep0[28:0]),
   .cache_ptag_w6	(ict_itlb_way_6_tag_f_rep0[28:0]),
   .cache_ptag_w7	(ict_itlb_way_7_tag_f_rep0[28:0]),
   .cache_set_vld	(agd_itlb_valid_fast_f[7:0]),
// Outputs
   .cache_way_hit	(itb_icd_waysel_c[7:0]),
   .cache_hit		(itb_chit_c),
   .tlb_cam_hit		(itb_cam_hit_c),
   .tlb_cam_mhit	(itb_itb_mhit_c),
   .tlb_pgnum_crit	(pa_unflopped_unused[39:13]),
   .tlb_pgnum		({ftu_paddr_unq[39:37],ftu_paddr[36:13]}),
   .tlb_tte_data	(itb_tte_data[37:0]),
   .tlb_tte_tag		(itb_tte_tag[65:0]),
   .tlb_tte_u_bit       (itb_tte_u_bit),
   .tlb_tte_data_parity	(itb_tte_data_parity),
  .tcu_pce_ov(tcu_pce_ov),
  .pce(pce),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_scan_en(tcu_scan_en),
  .tte_ubit(tte_ubit),
  .tlb_context0_hit(tlb_context0_hit)
);

assign itb_tte_p_c = itb_tte_data[1];


ifu_ftu_itc_ctl ftu_itc_ctl (
   .asi_real_bf(asi_addr_bf[4]),
   .mbi_wdata_6(mbi_wdata[6]),
   .mbi_wdata_0(mbi_wdata[0]),
   .tlu_trap_pc_0_45_43(tlu_trap_pc_0[45:43]) ,
   .tlu_trap_pc_1_45_43(tlu_trap_pc_1[45:43]) ,
   .itb_tte_data_v_27_22(itb_tte_data[17]) ,
   .itb_tte_data_v_21_16(itb_tte_data[10]) ,
   .lsu_asi_error_inject_b31(lsu_asi_error_inject[31]),
   .lsu_asi_error_inject_b29(lsu_asi_error_inject[29]),
   .lsu_asi_error_inject_b28(lsu_asi_error_inject[28]),
   .tlu_trap_pc_0(tlu_trap_pc_0[37:35]),
   .tlu_trap_pc_1(tlu_trap_pc_1[37:35]),
   .scan_in(ftu_itc_ctl_scanin),
   .scan_out(ftu_itc_ctl_scanout),
   .l2clk(l2clk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tlu_itlb_reload(tlu_itlb_reload[1:0]),
  .itd_index_valid_in(itd_index_valid_in),
  .ftp_itt_rd_req_bf(ftp_itt_rd_req_bf),
  .ftp_itd_rd_req_bf(ftp_itd_rd_req_bf),
  .tlu_itlb_bypass(tlu_itlb_bypass[7:0]),
  .lsu_immu_enable(lsu_immu_enable[7:0]),
  .ftp_itb_fetch_thr_bf(ftp_itb_fetch_thr_bf[7:0]),
  .ftp_ith_det_req_bf(ftp_ith_det_req_bf),
  .mbi_run(mbi_run),
  .lbist_run(lbist_run),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_itb_demap_en(mbi_itb_demap_en),
  .mbi_demap_type(mbi_demap_type[1:0]),
  .mbi_dis_clr_ubit(mbi_dis_clr_ubit),
  .mbi_repl_write(mbi_repl_write),
  .mbi_itb_cam_en_pre(mbi_itb_cam_en_pre),
  .mbi_itb_write_en(mbi_itb_write_en),
  .mbi_itb_read_en(mbi_itb_read_en),
  .itc_wr_u_en(itc_wr_u_en),
  .itc_rw_index_vld(itc_rw_index_vld),
  .itc_demap(itc_demap),
  .itc_demap_context(itc_demap_context),
  .itc_demap_all(itc_demap_all),
  .itc_demap_real(itc_demap_real),
  .itc_tte_ubit(itc_tte_ubit),
  .itc_sel_trap_pc_0(itc_sel_trap_pc_0),
  .itc_sel_trap_pc_1(itc_sel_trap_pc_1),
  .itc_sel_demap_tag_d(itc_sel_demap_tag_d),
  .itc_sel_demap_tag_c0(itc_sel_demap_tag_c0),
  .itc_sel_demap_tag_c1(itc_sel_demap_tag_c1),
  .itc_sel_write_tag(itc_sel_write_tag),
  .itc_sel_write_tag_indexed(itc_sel_write_tag_indexed),
  .itc_sel_default(itc_sel_default),
  .itc_itlb_rd_vld_bf(itc_itlb_rd_vld_bf),
  .itc_bypass_bf(itc_bypass_bf),
  .itc_ra_to_pa_bf(itc_ra_to_pa_bf),
  .itc_tag_error_inj(itc_tag_error_inj),
  .itc_data_error_inj(itc_data_error_inj),
  .itc_dis_clr_ubit(itc_dis_clr_ubit),
  .itc_write_next(itc_write_next),
  .itc_demap_next(itc_demap_next),
  .itc_sel_mbist(itc_sel_mbist),
  .itc_mbi_itb_read_en(itc_mbi_itb_read_en),
  .itc_thr_to_write(itc_thr_to_write[7:0]),
  .itc_itb_data_sz_1(itc_itb_data_sz_1)
);
	     
ifu_ftu_itd_dp ftu_itd_dp (
   .scan_in(ftu_itd_dp_scanin),
   .scan_out(ftu_itd_dp_scanout),
   .l2clk(l2clk),
   .default_pid(ftp_curr_pid_bf[2:0]),
   .default_r(itc_ra_to_pa_bf),
   .write_context_0(ctx_cntx_0_to_write_bf[13:0]),
   .write_context_1(ctx_cntx_1_to_write_bf[13:0]),
   .default_context_0(ctx_curr_cntx_0_bf[12:0]),
   .default_context_1(ctx_curr_cntx_1_bf[12:0]),
  .tcu_scan_en(tcu_scan_en),
  .tcu_muxtest(tcu_muxtest),
  .tcu_dectest(tcu_dectest),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .itc_sel_trap_pc_0(itc_sel_trap_pc_0),
  .itc_sel_trap_pc_1(itc_sel_trap_pc_1),
  .itc_sel_demap_tag_d(itc_sel_demap_tag_d),
  .itc_sel_demap_tag_c0(itc_sel_demap_tag_c0),
  .itc_sel_demap_tag_c1(itc_sel_demap_tag_c1),
  .itc_sel_write_tag(itc_sel_write_tag),
  .itc_sel_default(itc_sel_default),
  .itc_sel_write_tag_indexed(itc_sel_write_tag_indexed),
  .itc_tag_error_inj(itc_tag_error_inj),
  .itc_data_error_inj(itc_data_error_inj),
  .ifu_agd_pc_bf(ifu_agd_pc_bf[47:13]),
  .tlu_trap_pc_0(tlu_trap_pc_0[47:0]),
  .tlu_trap_pc_1(tlu_trap_pc_1[47:0]),
  .mmu_index(mmu_index[6:0]),
  .ftp_thr0_pid_data(ftp_thr0_pid_data[2:0]),
  .ftp_thr1_pid_data(ftp_thr1_pid_data[2:0]),
  .ftp_thr2_pid_data(ftp_thr2_pid_data[2:0]),
  .ftp_thr3_pid_data(ftp_thr3_pid_data[2:0]),
  .ftp_thr4_pid_data(ftp_thr4_pid_data[2:0]),
  .ftp_thr5_pid_data(ftp_thr5_pid_data[2:0]),
  .ftp_thr6_pid_data(ftp_thr6_pid_data[2:0]),
  .ftp_thr7_pid_data(ftp_thr7_pid_data[2:0]),
  .asi_addr_bf(asi_addr_bf[8:3]),
  .mbi_addr(mbi_addr[5:0]),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_run(mbi_run),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_cambist_shift(mbi_cambist_shift),
  .mbi_init_to_zero(mbi_init_to_zero),
  .itc_sel_mbist(itc_sel_mbist),
  .itc_write_next(itc_write_next),
  .itd_tag(itd_tag[68:0]),
  .itd_data(itd_data[37:0]),
  .itd_index_valid_in(itd_index_valid_in),
  .itd_rw_index(itd_rw_index[5:0]),
  .itd_prty_256m(itd_prty_256m),
  .itd_prty_4m(itd_prty_4m),
  .itd_prty_64k(itd_prty_64k),
  .itd_prty_8k(itd_prty_8k),
  .itd_prty_ctxt0(itd_prty_ctxt0),
  .itd_prty_ctxt1(itd_prty_ctxt1)
);	     

////////////////////////////////////////////////////////////////////////
// Fetch pick logic
////////////////////////////////////////////////////////////////////////
ifu_ftu_ftp_ctl ftu_ftp_ctl (
   .lsu_ifu_pid_data(lsu_ifu_ctxt_data[2:0]),
   .asi_sel_cntx_0(asi_addr_bf[10]),
   .scan_in(ftu_ftp_ctl_scanin),
   .scan_out(ftu_ftp_ctl_scanout),
   .l2clk(l2clk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .spc_core_running_status(spc_core_running_status[7:0]),
  .tlu_pstate_am(tlu_pstate_am[7:0]),
  .tlu_flush_ifu(tlu_flush_ifu[7:0]),
  .tlu_itlb_bypass(tlu_itlb_bypass[7:0]),
  .tlu_trap_0_tid(tlu_trap_0_tid[1:0]),
  .tlu_trap_1_tid(tlu_trap_1_tid[1:0]),
  .tlu_trap_pc_0_valid(tlu_trap_pc_0_valid),
  .tlu_trap_pc_1_valid(tlu_trap_pc_1_valid),
  .dec_br_taken_e(dec_br_taken_e[1:0]),
  .dec_valid_e(dec_valid_e[1:0]),
  .dec_tid0_d(dec_tid0_d[1:0]),
  .dec_tid1_d(dec_tid1_d[1:0]),
  .itc_demap_next(itc_demap_next),
  .mbi_run(mbi_run),
  .mbi_itb_cam_en_pre(mbi_itb_cam_en_pre),
  .mbi_cmpsel(mbi_cmpsel[1:0]),
  .mbi_ict_read_en(mbi_ict_read_en),
  .mbi_ict_write_en(mbi_ict_write_en),
  .mbi_icd_read_en(mbi_icd_read_en),
  .mbi_icd_write_en(mbi_icd_write_en),
  .mbi_icv_read_en(mbi_icv_read_en),
  .mbi_icv_write_en(mbi_icv_write_en),
  .cmu_thr0_data_ready(cmu_thr0_data_ready),
  .cmu_thr1_data_ready(cmu_thr1_data_ready),
  .cmu_thr2_data_ready(cmu_thr2_data_ready),
  .cmu_thr3_data_ready(cmu_thr3_data_ready),
  .cmu_thr4_data_ready(cmu_thr4_data_ready),
  .cmu_thr5_data_ready(cmu_thr5_data_ready),
  .cmu_thr6_data_ready(cmu_thr6_data_ready),
  .cmu_thr7_data_ready(cmu_thr7_data_ready),
  .tsm_thr0_ignore_by_pass(tsm_thr0_ignore_by_pass),
  .tsm_thr1_ignore_by_pass(tsm_thr1_ignore_by_pass),
  .tsm_thr2_ignore_by_pass(tsm_thr2_ignore_by_pass),
  .tsm_thr3_ignore_by_pass(tsm_thr3_ignore_by_pass),
  .tsm_thr4_ignore_by_pass(tsm_thr4_ignore_by_pass),
  .tsm_thr5_ignore_by_pass(tsm_thr5_ignore_by_pass),
  .tsm_thr6_ignore_by_pass(tsm_thr6_ignore_by_pass),
  .tsm_thr7_ignore_by_pass(tsm_thr7_ignore_by_pass),
  .dec_load_flush_w(dec_load_flush_w[1:0]),
  .tsm_thr0_ready_hp_bf_in(tsm_thr0_ready_hp_bf_in),
  .tsm_thr1_ready_hp_bf_in(tsm_thr1_ready_hp_bf_in),
  .tsm_thr2_ready_hp_bf_in(tsm_thr2_ready_hp_bf_in),
  .tsm_thr3_ready_hp_bf_in(tsm_thr3_ready_hp_bf_in),
  .tsm_thr4_ready_hp_bf_in(tsm_thr4_ready_hp_bf_in),
  .tsm_thr5_ready_hp_bf_in(tsm_thr5_ready_hp_bf_in),
  .tsm_thr6_ready_hp_bf_in(tsm_thr6_ready_hp_bf_in),
  .tsm_thr7_ready_hp_bf_in(tsm_thr7_ready_hp_bf_in),
  .tsm_thr0_fill_rdy0(tsm_thr0_fill_rdy0),
  .tsm_thr1_fill_rdy0(tsm_thr1_fill_rdy0),
  .tsm_thr2_fill_rdy0(tsm_thr2_fill_rdy0),
  .tsm_thr3_fill_rdy0(tsm_thr3_fill_rdy0),
  .tsm_thr4_fill_rdy0(tsm_thr4_fill_rdy0),
  .tsm_thr5_fill_rdy0(tsm_thr5_fill_rdy0),
  .tsm_thr6_fill_rdy0(tsm_thr6_fill_rdy0),
  .tsm_thr7_fill_rdy0(tsm_thr7_fill_rdy0),
  .cmu_icache_invalidate(cmu_icache_invalidate),
  .cmu_any_un_cacheable(cmu_any_un_cacheable),
  .cmu_any_data_ready(cmu_any_data_ready),
  .ibu_empty(ibu_empty[7:0]),
  .ibu_room_4ormore(ibu_room_4ormore[7:0]),
  .agc_by_pass_update_lru_bf(agc_by_pass_update_lru_bf[7:0]),
  .agc_invalidation_req_ff(agc_invalidation_req_ff[7:0]),
  .agc_kill_fetch_cv_c(agc_kill_fetch_cv_c),
  .agc_thr0_micro_flush_unq_c(agc_thr0_micro_flush_unq_c),
  .agc_thr1_micro_flush_unq_c(agc_thr1_micro_flush_unq_c),
  .agc_thr2_micro_flush_unq_c(agc_thr2_micro_flush_unq_c),
  .agc_thr3_micro_flush_unq_c(agc_thr3_micro_flush_unq_c),
  .agc_thr4_micro_flush_unq_c(agc_thr4_micro_flush_unq_c),
  .agc_thr5_micro_flush_unq_c(agc_thr5_micro_flush_unq_c),
  .agc_thr6_micro_flush_unq_c(agc_thr6_micro_flush_unq_c),
  .agc_thr7_micro_flush_unq_c(agc_thr7_micro_flush_unq_c),
  .agc_thr0_sf_valid_f(agc_thr0_sf_valid_f),
  .agc_thr1_sf_valid_f(agc_thr1_sf_valid_f),
  .agc_thr2_sf_valid_f(agc_thr2_sf_valid_f),
  .agc_thr3_sf_valid_f(agc_thr3_sf_valid_f),
  .agc_thr4_sf_valid_f(agc_thr4_sf_valid_f),
  .agc_thr5_sf_valid_f(agc_thr5_sf_valid_f),
  .agc_thr6_sf_valid_f(agc_thr6_sf_valid_f),
  .agc_thr7_sf_valid_f(agc_thr7_sf_valid_f),
  .asi_ic_wr_req(asi_ic_wr_req),
  .asi_ic_rd_req(asi_ic_rd_req),
  .asi_tg_wr_req(asi_tg_wr_req),
  .asi_tg_rd_req(asi_tg_rd_req),
  .asi_itd_rd_req(asi_itd_rd_req),
  .asi_itt_rd_req(asi_itt_rd_req),
  .asi_ith_det_req(asi_ith_det_req),
  .asi_tid(asi_tid[2:0]),
  .agd_address0_m(agd_address0_m[4:2]),
  .agd_address1_m(agd_address1_m[4:2]),
  .agd_thr0_pc_4_2_f(agd_thr0_pc_4_2_f[4:2]),
  .agd_thr1_pc_4_2_f(agd_thr1_pc_4_2_f[4:2]),
  .agd_thr2_pc_4_2_f(agd_thr2_pc_4_2_f[4:2]),
  .agd_thr3_pc_4_2_f(agd_thr3_pc_4_2_f[4:2]),
  .agd_thr4_pc_4_2_f(agd_thr4_pc_4_2_f[4:2]),
  .agd_thr5_pc_4_2_f(agd_thr5_pc_4_2_f[4:2]),
  .agd_thr6_pc_4_2_f(agd_thr6_pc_4_2_f[4:2]),
  .agd_thr7_pc_4_2_f(agd_thr7_pc_4_2_f[4:2]),
  .ifu_agd_pc_f(ifu_agd_pc_f[4:2]),
  .asi_addr_bf(asi_addr_bf[5:3]),
  .lsu_ifu_ftu_pmen(lsu_ifu_ftu_pmen),
  .lsu_ic_pmen(lsu_ic_pmen),
  .lsu_ifu_wr_pid(lsu_ifu_wr_pid),
  .lsu_ifu_tid_w(lsu_ifu_tid_w[2:0]),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .ftp_reset_fill_wait(ftp_reset_fill_wait),
  .ftp_ic_rd_req_bf(ftp_ic_rd_req_bf),
  .ftp_ic_wr_ps_en_bf(ftp_ic_wr_ps_en_bf),
  .ftp_ic_wr_req_bf(ftp_ic_wr_req_bf),
  .ftp_tg_rd_req_bf(ftp_tg_rd_req_bf),
  .ftp_tg_wr_req_bf(ftp_tg_wr_req_bf),
  .ftp_iv_rd_req_bf(ftp_iv_rd_req_bf),
  .ftp_itt_rd_req_bf(ftp_itt_rd_req_bf),
  .ftp_itd_rd_req_bf(ftp_itd_rd_req_bf),
  .ftp_itlb_cam_vld_bf(ftp_itlb_cam_vld_bf),
  .ftp_itlb_cam_vld_f(ftp_itlb_cam_vld_f),
  .ftp_ith_det_req_bf(ftp_ith_det_req_bf),
  .ftp_itlb_probe_req_l(ftp_itlb_probe_req_l),
  .ftp_sel_icv_mbist_addr(ftp_sel_icv_mbist_addr),
  .ftp_sel_mbist_itb_cycle0(ftp_sel_mbist_itb_cycle0),
  .ftp_sel_mbist_itb_cycle1(ftp_sel_mbist_itb_cycle1),
  .ftp_sel_mbist_itb_cycle2(ftp_sel_mbist_itb_cycle2),
  .ftp_sel_mbist_itb_cycle3(ftp_sel_mbist_itb_cycle3),
  .ftp_sel_itlb_tag_cntx0_c(ftp_sel_itlb_tag_cntx0_c),
  .ftp_sel_itlb_tag_cntx1_c(ftp_sel_itlb_tag_cntx1_c),
  .ftp_sel_itlb_data_c(ftp_sel_itlb_data_c),
  .ftp_sel_itlb_pa_c(ftp_sel_itlb_pa_c),
  .ftp_asi_mbist_access_bf(ftp_asi_mbist_access_bf),
  .ftp_asi_it_rd_done(ftp_asi_it_rd_done),
  .ftp_asi_ic_rd_done(ftp_asi_ic_rd_done),
  .ftp_asi_ic_wr_done(ftp_asi_ic_wr_done),
  .ftp_asi_tg_rd_done(ftp_asi_tg_rd_done),
  .ftp_asi_tg_wr_done(ftp_asi_tg_wr_done),
  .ftp_asi_tg_wr_req_hold(ftp_asi_tg_wr_req_hold),
  .ftp_thr0_room_is_less_t_3(ftp_thr0_room_is_less_t_3),
  .ftp_thr1_room_is_less_t_3(ftp_thr1_room_is_less_t_3),
  .ftp_thr2_room_is_less_t_3(ftp_thr2_room_is_less_t_3),
  .ftp_thr3_room_is_less_t_3(ftp_thr3_room_is_less_t_3),
  .ftp_thr4_room_is_less_t_3(ftp_thr4_room_is_less_t_3),
  .ftp_thr5_room_is_less_t_3(ftp_thr5_room_is_less_t_3),
  .ftp_thr6_room_is_less_t_3(ftp_thr6_room_is_less_t_3),
  .ftp_thr7_room_is_less_t_3(ftp_thr7_room_is_less_t_3),
  .ftp_thr0_go_to_sf_wait(ftp_thr0_go_to_sf_wait),
  .ftp_thr1_go_to_sf_wait(ftp_thr1_go_to_sf_wait),
  .ftp_thr2_go_to_sf_wait(ftp_thr2_go_to_sf_wait),
  .ftp_thr3_go_to_sf_wait(ftp_thr3_go_to_sf_wait),
  .ftp_thr4_go_to_sf_wait(ftp_thr4_go_to_sf_wait),
  .ftp_thr5_go_to_sf_wait(ftp_thr5_go_to_sf_wait),
  .ftp_thr6_go_to_sf_wait(ftp_thr6_go_to_sf_wait),
  .ftp_thr7_go_to_sf_wait(ftp_thr7_go_to_sf_wait),
  .ftp_thr0_trprdpc_sel_bf(ftp_thr0_trprdpc_sel_bf[2:0]),
  .ftp_thr1_trprdpc_sel_bf(ftp_thr1_trprdpc_sel_bf[2:0]),
  .ftp_thr2_trprdpc_sel_bf(ftp_thr2_trprdpc_sel_bf[2:0]),
  .ftp_thr3_trprdpc_sel_bf(ftp_thr3_trprdpc_sel_bf[2:0]),
  .ftp_thr4_trprdpc_sel_bf(ftp_thr4_trprdpc_sel_bf[2:0]),
  .ftp_thr5_trprdpc_sel_bf(ftp_thr5_trprdpc_sel_bf[2:0]),
  .ftp_thr6_trprdpc_sel_bf(ftp_thr6_trprdpc_sel_bf[2:0]),
  .ftp_thr7_trprdpc_sel_bf(ftp_thr7_trprdpc_sel_bf[2:0]),
  .ftp_thr0_sel_br_bf(ftp_thr0_sel_br_bf),
  .ftp_thr1_sel_br_bf(ftp_thr1_sel_br_bf),
  .ftp_thr2_sel_br_bf(ftp_thr2_sel_br_bf),
  .ftp_thr3_sel_br_bf(ftp_thr3_sel_br_bf),
  .ftp_thr4_sel_br_bf(ftp_thr4_sel_br_bf),
  .ftp_thr5_sel_br_bf(ftp_thr5_sel_br_bf),
  .ftp_thr6_sel_br_bf(ftp_thr6_sel_br_bf),
  .ftp_thr7_sel_br_bf(ftp_thr7_sel_br_bf),
  .ftp_icd_quad_0_en_bf(ftp_icd_quad_0_en_bf),
  .ftp_icd_quad_1_en_bf(ftp_icd_quad_1_en_bf),
  .ftp_icd_quad_2_en_bf(ftp_icd_quad_2_en_bf),
  .ftp_icd_quad_3_en_bf(ftp_icd_quad_3_en_bf),
  .ftp_tg_clk_en(ftp_tg_clk_en),
  .ftp_pc_sel_am(ftp_pc_sel_am[5:0]),
  .ftp_pc_sel_tag_part1(ftp_pc_sel_tag_part1[2:0]),
  .ftp_pc_sel_tag_part2(ftp_pc_sel_tag_part2[3:0]),
  .ftp_pc_sel_tag_pc_bot(ftp_pc_sel_tag_pc_bot[1:0]),
  .ftp_pc_sel_tag_pc_top(ftp_pc_sel_tag_pc_top[1:0]),
  .ftp_icaddr_sel_first_mux(ftp_icaddr_sel_first_mux[4:0]),
  .ftp_itb_fetch_thr_bf(ftp_itb_fetch_thr_bf[7:0]),
  .ftp_new_thr_sel_bf(ftp_new_thr_sel_bf[7:0]),
  .ftu_curr_fetch_thr_f(ftu_curr_fetch_thr_f[7:0]),
  .ftp_curr_fetch_thr_f(ftp_curr_fetch_thr_f[7:0]),
  .ftp_fetch_thr_q_f(ftp_fetch_thr_q_f[7:0]),
  .ftp_tid0_e(ftp_tid0_e[1:0]),
  .ftp_tid1_e(ftp_tid1_e[1:0]),
  .ftp_fetch_v_f(ftp_fetch_v_f),
  .ftp_fill_req_q_bf(ftp_fill_req_q_bf),
  .ftp_mbi_icd_read_en_bf(ftp_mbi_icd_read_en_bf),
  .ftp_mbi_ict_read_en_bf(ftp_mbi_ict_read_en_bf),
  .ftp_ict_data_sel_bf(ftp_ict_data_sel_bf[2:0]),
  .ftp_any_thr_clken(ftp_any_thr_clken),
  .ftp_curr_pid_bf(ftp_curr_pid_bf[2:0]),
  .ftp_thr7_pid_data(ftp_thr7_pid_data[2:0]),
  .ftp_thr6_pid_data(ftp_thr6_pid_data[2:0]),
  .ftp_thr5_pid_data(ftp_thr5_pid_data[2:0]),
  .ftp_thr4_pid_data(ftp_thr4_pid_data[2:0]),
  .ftp_thr3_pid_data(ftp_thr3_pid_data[2:0]),
  .ftp_thr2_pid_data(ftp_thr2_pid_data[2:0]),
  .ftp_thr1_pid_data(ftp_thr1_pid_data[2:0]),
  .ftp_thr0_pid_data(ftp_thr0_pid_data[2:0])
);


//////////////////////////////////////////////////////
// Thread fetch control has all the logic to control//
// which threads are eligible for fetch.            //
//////////////////////////////////////////////////////
ifu_ftu_tfc_ctl ftu_tfc_ctl (
   .scan_in(ftu_tfc_ctl_scanin),
   .scan_out(ftu_tfc_ctl_scanout),
   .l2clk(l2clk),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_pce_ov(tcu_pce_ov),
  .ftu_thr0_redirect_bf(ftu_thr0_redirect_bf),
  .ftu_thr1_redirect_bf(ftu_thr1_redirect_bf),
  .ftu_thr2_redirect_bf(ftu_thr2_redirect_bf),
  .ftu_thr3_redirect_bf(ftu_thr3_redirect_bf),
  .ftu_thr4_redirect_bf(ftu_thr4_redirect_bf),
  .ftu_thr5_redirect_bf(ftu_thr5_redirect_bf),
  .ftu_thr6_redirect_bf(ftu_thr6_redirect_bf),
  .ftu_thr7_redirect_bf(ftu_thr7_redirect_bf),
  .agc_thr0_err_detect_c(agc_thr0_err_detect_c),
  .agc_thr1_err_detect_c(agc_thr1_err_detect_c),
  .agc_thr2_err_detect_c(agc_thr2_err_detect_c),
  .agc_thr3_err_detect_c(agc_thr3_err_detect_c),
  .agc_thr4_err_detect_c(agc_thr4_err_detect_c),
  .agc_thr5_err_detect_c(agc_thr5_err_detect_c),
  .agc_thr6_err_detect_c(agc_thr6_err_detect_c),
  .agc_thr7_err_detect_c(agc_thr7_err_detect_c),
  .ftu_thr0_inv_req_c(ftu_thr0_inv_req_c),
  .ftu_thr1_inv_req_c(ftu_thr1_inv_req_c),
  .ftu_thr2_inv_req_c(ftu_thr2_inv_req_c),
  .ftu_thr3_inv_req_c(ftu_thr3_inv_req_c),
  .ftu_thr4_inv_req_c(ftu_thr4_inv_req_c),
  .ftu_thr5_inv_req_c(ftu_thr5_inv_req_c),
  .ftu_thr6_inv_req_c(ftu_thr6_inv_req_c),
  .ftu_thr7_inv_req_c(ftu_thr7_inv_req_c),
  .agc_thr0_lsu_no_ic_miss(agc_thr0_lsu_no_ic_miss),
  .agc_thr1_lsu_no_ic_miss(agc_thr1_lsu_no_ic_miss),
  .agc_thr2_lsu_no_ic_miss(agc_thr2_lsu_no_ic_miss),
  .agc_thr3_lsu_no_ic_miss(agc_thr3_lsu_no_ic_miss),
  .agc_thr4_lsu_no_ic_miss(agc_thr4_lsu_no_ic_miss),
  .agc_thr5_lsu_no_ic_miss(agc_thr5_lsu_no_ic_miss),
  .agc_thr6_lsu_no_ic_miss(agc_thr6_lsu_no_ic_miss),
  .agc_thr7_lsu_no_ic_miss(agc_thr7_lsu_no_ic_miss),
  .agc_thr0_tlu_redirect_bf(agc_thr0_tlu_redirect_bf),
  .agc_thr1_tlu_redirect_bf(agc_thr1_tlu_redirect_bf),
  .agc_thr2_tlu_redirect_bf(agc_thr2_tlu_redirect_bf),
  .agc_thr3_tlu_redirect_bf(agc_thr3_tlu_redirect_bf),
  .agc_thr4_tlu_redirect_bf(agc_thr4_tlu_redirect_bf),
  .agc_thr5_tlu_redirect_bf(agc_thr5_tlu_redirect_bf),
  .agc_thr6_tlu_redirect_bf(agc_thr6_tlu_redirect_bf),
  .agc_thr7_tlu_redirect_bf(agc_thr7_tlu_redirect_bf),
  .ftp_thr0_go_to_sf_wait(ftp_thr0_go_to_sf_wait),
  .ftp_thr1_go_to_sf_wait(ftp_thr1_go_to_sf_wait),
  .ftp_thr2_go_to_sf_wait(ftp_thr2_go_to_sf_wait),
  .ftp_thr3_go_to_sf_wait(ftp_thr3_go_to_sf_wait),
  .ftp_thr4_go_to_sf_wait(ftp_thr4_go_to_sf_wait),
  .ftp_thr5_go_to_sf_wait(ftp_thr5_go_to_sf_wait),
  .ftp_thr6_go_to_sf_wait(ftp_thr6_go_to_sf_wait),
  .ftp_thr7_go_to_sf_wait(ftp_thr7_go_to_sf_wait),
  .cmu_inval_ack(cmu_inval_ack[7:0]),
  .cmu_rst_dupmiss(cmu_rst_dupmiss[7:0]),
  .cmu_null_st(cmu_null_st[7:0]),
  .cmu_dupmiss_st(cmu_dupmiss_st[7:0]),
  .cmu_thr0_data_ready(cmu_thr0_data_ready),
  .cmu_thr1_data_ready(cmu_thr1_data_ready),
  .cmu_thr2_data_ready(cmu_thr2_data_ready),
  .cmu_thr3_data_ready(cmu_thr3_data_ready),
  .cmu_thr4_data_ready(cmu_thr4_data_ready),
  .cmu_thr5_data_ready(cmu_thr5_data_ready),
  .cmu_thr6_data_ready(cmu_thr6_data_ready),
  .cmu_thr7_data_ready(cmu_thr7_data_ready),
  .agc_thr0_cmiss_stm_c(agc_thr0_cmiss_stm_c),
  .agc_thr1_cmiss_stm_c(agc_thr1_cmiss_stm_c),
  .agc_thr2_cmiss_stm_c(agc_thr2_cmiss_stm_c),
  .agc_thr3_cmiss_stm_c(agc_thr3_cmiss_stm_c),
  .agc_thr4_cmiss_stm_c(agc_thr4_cmiss_stm_c),
  .agc_thr5_cmiss_stm_c(agc_thr5_cmiss_stm_c),
  .agc_thr6_cmiss_stm_c(agc_thr6_cmiss_stm_c),
  .agc_thr7_cmiss_stm_c(agc_thr7_cmiss_stm_c),
  .agc_thr0_itb_miss_c(agc_thr0_itb_miss_c),
  .agc_thr1_itb_miss_c(agc_thr1_itb_miss_c),
  .agc_thr2_itb_miss_c(agc_thr2_itb_miss_c),
  .agc_thr3_itb_miss_c(agc_thr3_itb_miss_c),
  .agc_thr4_itb_miss_c(agc_thr4_itb_miss_c),
  .agc_thr5_itb_miss_c(agc_thr5_itb_miss_c),
  .agc_thr6_itb_miss_c(agc_thr6_itb_miss_c),
  .agc_thr7_itb_miss_c(agc_thr7_itb_miss_c),
  .cmu_any_data_ready(cmu_any_data_ready),
  .ftp_reset_fill_wait(ftp_reset_fill_wait),
  .ftp_thr0_room_is_less_t_3(ftp_thr0_room_is_less_t_3),
  .ftp_thr1_room_is_less_t_3(ftp_thr1_room_is_less_t_3),
  .ftp_thr2_room_is_less_t_3(ftp_thr2_room_is_less_t_3),
  .ftp_thr3_room_is_less_t_3(ftp_thr3_room_is_less_t_3),
  .ftp_thr4_room_is_less_t_3(ftp_thr4_room_is_less_t_3),
  .ftp_thr5_room_is_less_t_3(ftp_thr5_room_is_less_t_3),
  .ftp_thr6_room_is_less_t_3(ftp_thr6_room_is_less_t_3),
  .ftp_thr7_room_is_less_t_3(ftp_thr7_room_is_less_t_3),
  .itc_demap_next(itc_demap_next),
  .tlu_flush_ifu(tlu_flush_ifu[7:0]),
  .asi_wr_request(asi_wr_request),
  .asi_rd_request(asi_rd_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .tsm_thr0_fill_rdy0(tsm_thr0_fill_rdy0),
  .tsm_thr1_fill_rdy0(tsm_thr1_fill_rdy0),
  .tsm_thr2_fill_rdy0(tsm_thr2_fill_rdy0),
  .tsm_thr3_fill_rdy0(tsm_thr3_fill_rdy0),
  .tsm_thr4_fill_rdy0(tsm_thr4_fill_rdy0),
  .tsm_thr5_fill_rdy0(tsm_thr5_fill_rdy0),
  .tsm_thr6_fill_rdy0(tsm_thr6_fill_rdy0),
  .tsm_thr7_fill_rdy0(tsm_thr7_fill_rdy0),
  .tsm_thr0_no_new_miss(tsm_thr0_no_new_miss),
  .tsm_thr1_no_new_miss(tsm_thr1_no_new_miss),
  .tsm_thr2_no_new_miss(tsm_thr2_no_new_miss),
  .tsm_thr3_no_new_miss(tsm_thr3_no_new_miss),
  .tsm_thr4_no_new_miss(tsm_thr4_no_new_miss),
  .tsm_thr5_no_new_miss(tsm_thr5_no_new_miss),
  .tsm_thr6_no_new_miss(tsm_thr6_no_new_miss),
  .tsm_thr7_no_new_miss(tsm_thr7_no_new_miss),
  .tsm_thr0_ignore_by_pass(tsm_thr0_ignore_by_pass),
  .tsm_thr1_ignore_by_pass(tsm_thr1_ignore_by_pass),
  .tsm_thr2_ignore_by_pass(tsm_thr2_ignore_by_pass),
  .tsm_thr3_ignore_by_pass(tsm_thr3_ignore_by_pass),
  .tsm_thr4_ignore_by_pass(tsm_thr4_ignore_by_pass),
  .tsm_thr5_ignore_by_pass(tsm_thr5_ignore_by_pass),
  .tsm_thr6_ignore_by_pass(tsm_thr6_ignore_by_pass),
  .tsm_thr7_ignore_by_pass(tsm_thr7_ignore_by_pass),
  .tsm_thr0_ready_hp_bf_in(tsm_thr0_ready_hp_bf_in),
  .tsm_thr1_ready_hp_bf_in(tsm_thr1_ready_hp_bf_in),
  .tsm_thr2_ready_hp_bf_in(tsm_thr2_ready_hp_bf_in),
  .tsm_thr3_ready_hp_bf_in(tsm_thr3_ready_hp_bf_in),
  .tsm_thr4_ready_hp_bf_in(tsm_thr4_ready_hp_bf_in),
  .tsm_thr5_ready_hp_bf_in(tsm_thr5_ready_hp_bf_in),
  .tsm_thr6_ready_hp_bf_in(tsm_thr6_ready_hp_bf_in),
  .tsm_thr7_ready_hp_bf_in(tsm_thr7_ready_hp_bf_in),
  .ftu_ifu_quiesce(ftu_ifu_quiesce[7:0])
); 

////////////////////////////////////////////////////////////
// Bypass data to IB buffers.
// This file muxes the instructions from the IC and the
// Instruction being by_passed from the cache_miss unit. 
////////////////////////////////////////////////////////////
ifu_ftu_byp_dp  ftu_byp_dp (
   .scan_in(ftu_byp_dp_scanin),
   .scan_out(ftu_byp_dp_scanout),
   .l2clk(l2clk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_muxtest(tcu_muxtest),
  .tcu_dectest(tcu_dectest),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_addr(mbi_addr[5:0]),
  .agd_mbist_wdata_bf(agd_mbist_wdata_bf[7:0]),
  .ftp_mbi_icd_read_en_bf(ftp_mbi_icd_read_en_bf),
  .ftp_mbi_ict_read_en_bf(ftp_mbi_ict_read_en_bf),
  .itc_mbi_itb_read_en(itc_mbi_itb_read_en),
  .cmu_fill_inst0(cmu_fill_inst0[32:0]),
  .cmu_fill_inst1(cmu_fill_inst1[32:0]),
  .cmu_fill_inst2(cmu_fill_inst2[32:0]),
  .cmu_fill_inst3(cmu_fill_inst3[32:0]),
  .icd_bus_0_instr_c(icd_bus_0_instr_c[32:0]),
  .icd_bus_1_instr_c(icd_bus_1_instr_c[32:0]),
  .icd_bus_2_instr_c(icd_bus_2_instr_c[32:0]),
  .icd_bus_3_instr_c(icd_bus_3_instr_c[32:0]),
  .agc_instr_bp_sel_c(agc_instr_bp_sel_c[2:0]),
  .agc_asi_sel_word_c(agc_asi_sel_word_c[3:0]),
  .agc_sel_tg_data_f(agc_sel_tg_data_f[7:0]),
  .ict_itlb_way_0_tag_f(ict_itlb_way_0_tag_f[29:0]),
  .ict_itlb_way_1_tag_f(ict_itlb_way_1_tag_f[29:0]),
  .ict_itlb_way_2_tag_f(ict_itlb_way_2_tag_f[29:0]),
  .ict_itlb_way_3_tag_f(ict_itlb_way_3_tag_f[29:0]),
  .ict_itlb_way_4_tag_f(ict_itlb_way_4_tag_f[29:0]),
  .ict_itlb_way_5_tag_f(ict_itlb_way_5_tag_f[29:0]),
  .ict_itlb_way_6_tag_f(ict_itlb_way_6_tag_f[29:0]),
  .ict_itlb_way_7_tag_f(ict_itlb_way_7_tag_f[29:0]),
  .itb_tte_data(itb_tte_data[37:0]),
  .itb_tte_tag(itb_tte_tag[65:0]),
  .itb_tte_u_bit(itb_tte_u_bit),
  .ftu_paddr(ftu_paddr[39:13]),
  .itb_cam_hit_c(itb_cam_hit_c),
  .itb_itb_mhit_c(itb_itb_mhit_c),
  .itb_tte_data_parity(itb_tte_data_parity),
  .agc_itb_tag_perr_c(agc_itb_tag_perr_c),
  .itc_itb_data_sz_1(itc_itb_data_sz_1),
  .ftp_sel_mbist_itb_cycle0(ftp_sel_mbist_itb_cycle0),
  .ftp_sel_mbist_itb_cycle1(ftp_sel_mbist_itb_cycle1),
  .ftp_sel_mbist_itb_cycle2(ftp_sel_mbist_itb_cycle2),
  .ftp_sel_mbist_itb_cycle3(ftp_sel_mbist_itb_cycle3),
  .ftp_sel_itlb_tag_cntx0_c(ftp_sel_itlb_tag_cntx0_c),
  .ftp_sel_itlb_tag_cntx1_c(ftp_sel_itlb_tag_cntx1_c),
  .ftp_sel_itlb_data_c(ftp_sel_itlb_data_c),
  .ftp_sel_itlb_pa_c(ftp_sel_itlb_pa_c),
  .ftu_instr_0_c(ftu_instr_0_c[32:0]),
  .ftu_instr_1_c(ftu_instr_1_c[32:0]),
  .ftu_instr_2_c(ftu_instr_2_c[32:0]),
  .ftu_instr_3_c(ftu_instr_3_c[32:0]),
  .ic_rd_data(ic_rd_data[32:0]),
  .ic_dmo_rd_data(ic_dmo_rd_data[32:0]),
  .tg_rd_data(tg_rd_data[29:0]),
  .it_rd_data(it_rd_data[63:0]),
  .ftu_mbi_ict_fail(ftu_mbi_ict_fail),
  .ftu_mbi_icd_fail(ftu_mbi_icd_fail),
  .ftu_mbi_itb_fail(ftu_mbi_itb_fail),
  .ftu_mbi_tlb_data_cmp(ftu_mbi_tlb_data_cmp),
  .ftu_mbi_tlb_used(ftu_mbi_tlb_used),
  .ftu_mbi_tlb_valid(ftu_mbi_tlb_valid),
  .ict_itlb_way_0_tag_f_rep0(ict_itlb_way_0_tag_f_rep0[28:0]),
  .ict_itlb_way_1_tag_f_rep0(ict_itlb_way_1_tag_f_rep0[28:0]),
  .ict_itlb_way_2_tag_f_rep0(ict_itlb_way_2_tag_f_rep0[28:0]),
  .ict_itlb_way_3_tag_f_rep0(ict_itlb_way_3_tag_f_rep0[28:0]),
  .ict_itlb_way_4_tag_f_rep0(ict_itlb_way_4_tag_f_rep0[28:0]),
  .ict_itlb_way_5_tag_f_rep0(ict_itlb_way_5_tag_f_rep0[28:0]),
  .ict_itlb_way_6_tag_f_rep0(ict_itlb_way_6_tag_f_rep0[28:0]),
  .ict_itlb_way_7_tag_f_rep0(ict_itlb_way_7_tag_f_rep0[28:0])
);
        

////////////////////////////////////////////////////////////
// parity error generation block                          //
////////////////////////////////////////////////////////////
ifu_ftu_err_dp ftu_err_dp (.ict_itlb_way_0_tag_f(ict_itlb_way_0_tag_f[29:0]),
  .ict_itlb_way_1_tag_f(ict_itlb_way_1_tag_f[29:0]),
  .ict_itlb_way_2_tag_f(ict_itlb_way_2_tag_f[29:0]),
  .ict_itlb_way_3_tag_f(ict_itlb_way_3_tag_f[29:0]),
  .ict_itlb_way_4_tag_f(ict_itlb_way_4_tag_f[29:0]),
  .ict_itlb_way_5_tag_f(ict_itlb_way_5_tag_f[29:0]),
  .ict_itlb_way_6_tag_f(ict_itlb_way_6_tag_f[29:0]),
  .ict_itlb_way_7_tag_f(ict_itlb_way_7_tag_f[29:0]),
  .err_w0_8b_parity_f(err_w0_8b_parity_f[3:0]),
  .err_w1_8b_parity_f(err_w1_8b_parity_f[3:0]),
  .err_w2_8b_parity_f(err_w2_8b_parity_f[3:0]),
  .err_w3_8b_parity_f(err_w3_8b_parity_f[3:0]),
  .err_w4_8b_parity_f(err_w4_8b_parity_f[3:0]),
  .err_w5_8b_parity_f(err_w5_8b_parity_f[3:0]),
  .err_w6_8b_parity_f(err_w6_8b_parity_f[3:0]),
  .err_w7_8b_parity_f(err_w7_8b_parity_f[3:0])
 );

ifu_ftu_asi_ctl ftu_asi_ctl (
   .scan_in(ftu_asi_ctl_scanin),
   .scan_out(ftu_asi_ctl_scanout),
   .l2clk(l2clk),
   .rng_in_cdbus(in_rngl_cdbus),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ic_rd_data(ic_rd_data[32:0]),
  .tg_rd_data(tg_rd_data[29:0]),
  .it_rd_data(it_rd_data[63:0]),
  .agc_vl_data_c(agc_vl_data_c[1:0]),
  .ftp_asi_ic_rd_done(ftp_asi_ic_rd_done),
  .ftp_asi_ic_wr_done(ftp_asi_ic_wr_done),
  .ftp_asi_tg_rd_done(ftp_asi_tg_rd_done),
  .ftp_asi_tg_wr_done(ftp_asi_tg_wr_done),
  .ftp_asi_it_rd_done(ftp_asi_it_rd_done),
  .asi_wr_data(asi_wr_data[32:0]),
  .asi_ic_rd_req(asi_ic_rd_req),
  .asi_ic_wr_req(asi_ic_wr_req),
  .asi_tg_rd_req(asi_tg_rd_req),
  .asi_tg_wr_req(asi_tg_wr_req),
  .asi_itd_rd_req(asi_itd_rd_req),
  .asi_itt_rd_req(asi_itt_rd_req),
  .asi_ith_det_req(asi_ith_det_req),
  .asi_wr_request(asi_wr_request),
  .asi_rd_request(asi_rd_request),
  .asi_addr_bf(asi_addr_bf[39:3]),
  .asi_way_bf(asi_way_bf[2:0]),
  .asi_tid(asi_tid[2:0]),
  .ifu_rngl_cdbus(ifu_rngl_cdbus[64:0]));
  

// fixscan start:
assign ftu_agd_dp_scanin         = scan_in                  ;
assign ftu_ctx_dp_scanin         = ftu_agd_dp_scanout       ;
assign ftu_agc_ctl_scanin        = ftu_ctx_dp_scanout       ;
assign ftu_cms_ctl_scanin        = ftu_agc_ctl_scanout      ;
assign ftu_icd_cust_scanin       = ftu_cms_ctl_scanout      ;
assign hdr_scanin                = ftu_icd_cust_scanout     ;
assign ftu_ict_cust_scanin       = hdr_scanout              ;
assign ftu_icv_cust_scanin       = ftu_ict_cust_scanout     ;
assign ftu_itb_cust_scanin       = ftu_icv_cust_scanout     ;
assign ftu_itc_ctl_scanin        = ftu_itb_cust_scanout     ;
assign ftu_itd_dp_scanin         = ftu_itc_ctl_scanout      ;
assign ftu_ftp_ctl_scanin        = ftu_itd_dp_scanout       ;
assign ftu_tfc_ctl_scanin        = ftu_ftp_ctl_scanout      ;
assign ftu_byp_dp_scanin         = ftu_tfc_ctl_scanout      ;
assign ftu_asi_ctl_scanin        = ftu_byp_dp_scanout       ;
assign scan_out                  = ftu_asi_ctl_scanout      ;

assign ftu_ctx_dp_wmr_scanin     = wmr_scan_in              ;
assign wmr_scan_out              = ftu_ctx_dp_wmr_scanout   ;
// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_agc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_agc_ctl (
  tcu_se_scancollar_out, 
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tlu_trap_pc_0_valid, 
  tlu_retry, 
  tlu_ceter_pscce, 
  tlu_trap_pc_1_valid, 
  tlu_ifu_invalidate, 
  tlu_trap_0_tid, 
  tlu_trap_1_tid, 
  spc_core_running_status, 
  mbi_wdata, 
  mbi_addr, 
  mbi_cmpsel, 
  mbi_run, 
  mbi_icv_write_en, 
  tlu_flush_ifu, 
  tlu_ifu_hpstate_hpriv, 
  tlu_ifu_pstate_priv, 
  tlu_cerer_ittp, 
  tlu_cerer_itdp, 
  tlu_cerer_ittm, 
  tlu_cerer_icl2c, 
  tlu_cerer_icl2u, 
  tlu_cerer_icl2nd, 
  tlu_cerer_icvp, 
  tlu_cerer_ictp, 
  tlu_cerer_ictm, 
  tlb_nfo, 
  agd_va_hole_excp_f, 
  agd_itlb_valid_f, 
  agd_itlb_valid_dupl_f, 
  asi_ith_det_req, 
  asi_vl_arr_data, 
  ftp_asi_tg_wr_req_hold, 
  ftp_itlb_cam_vld_f, 
  asi_addr_bf, 
  asi_way_bf, 
  ifu_agd_pc_f, 
  agd_thr0_pc_4_2_f, 
  agd_thr1_pc_4_2_f, 
  agd_thr2_pc_4_2_f, 
  agd_thr3_pc_4_2_f, 
  agd_thr4_pc_4_2_f, 
  agd_thr5_pc_4_2_f, 
  agd_thr6_pc_4_2_f, 
  agd_thr7_pc_4_2_f, 
  dec_load_flush_w, 
  itc_bypass_bf, 
  itc_real_bf, 
  itc_demap_next, 
  ftp_curr_fetch_thr_f, 
  ftp_fetch_thr_q_f, 
  ftp_fill_req_q_bf, 
  ftp_any_thr_clken, 
  err_w0_8b_parity_f, 
  err_w1_8b_parity_f, 
  err_w2_8b_parity_f, 
  err_w3_8b_parity_f, 
  err_w4_8b_parity_f, 
  err_w5_8b_parity_f, 
  err_w6_8b_parity_f, 
  err_w7_8b_parity_f, 
  tsm_thr0_ignore_by_pass, 
  tsm_thr1_ignore_by_pass, 
  tsm_thr2_ignore_by_pass, 
  tsm_thr3_ignore_by_pass, 
  tsm_thr4_ignore_by_pass, 
  tsm_thr5_ignore_by_pass, 
  tsm_thr6_ignore_by_pass, 
  tsm_thr7_ignore_by_pass, 
  tsm_thr0_no_new_miss, 
  tsm_thr1_no_new_miss, 
  tsm_thr2_no_new_miss, 
  tsm_thr3_no_new_miss, 
  tsm_thr4_no_new_miss, 
  tsm_thr5_no_new_miss, 
  tsm_thr6_no_new_miss, 
  tsm_thr7_no_new_miss, 
  cmu_any_data_ready, 
  cmu_any_un_cacheable, 
  cmu_l2_err, 
  cmu_l2miss, 
  cmu_thr0_data_ready, 
  cmu_thr1_data_ready, 
  cmu_thr2_data_ready, 
  cmu_thr3_data_ready, 
  cmu_thr4_data_ready, 
  cmu_thr5_data_ready, 
  cmu_thr6_data_ready, 
  cmu_thr7_data_ready, 
  cmu_fill_wrway, 
  cmu_icache_invalidate, 
  cmu_evic_invalidate, 
  cmu_icache_invalidate_way, 
  cmu_icache_inv_way1, 
  fill_paddr_bit_5, 
  inv_paddr_bit_5, 
  ftu_paddr_unq_39, 
  cmu_instr_v, 
  dec_br_taken_e, 
  dec_valid_e, 
  ftp_tid0_e, 
  ftp_tid1_e, 
  ftp_fetch_v_f, 
  itb_chit_c, 
  itb_cam_hit_c, 
  itb_tte_p_c, 
  itb_itb_mhit_c, 
  itb_tte_tag_parity, 
  itb_tte_data_parity, 
  itb_icd_waysel_c, 
  lsu_ifu_tid_w, 
  lsu_ifu_wr_p0ctxt, 
  lsu_ifu_wr_p1ctxt, 
  lsu_ifu_no_miss, 
  lsu_ic_enable, 
  cmu_inval_ack, 
  ftp_asi_mbist_access_bf, 
  itd_prty_256m, 
  itd_prty_4m, 
  itd_prty_64k, 
  itd_prty_8k, 
  itd_prty_ctxt0, 
  itd_prty_ctxt1, 
  tlb_pgsize, 
  tlb_context0_hit, 
  ftu_buffer_wr_en_f, 
  agc_itb_tag_perr_c, 
  agc_vl_data_c, 
  agc_asi_sel_word_c, 
  agc_sel_tg_data_f, 
  agc_word_en_bf, 
  agc_by_pass_update_lru_bf, 
  agc_invalidation_req_ff, 
  agc_any_invalidation_req_f, 
  agc_thr0_sf_valid_f, 
  agc_thr1_sf_valid_f, 
  agc_thr2_sf_valid_f, 
  agc_thr3_sf_valid_f, 
  agc_thr4_sf_valid_f, 
  agc_thr5_sf_valid_f, 
  agc_thr6_sf_valid_f, 
  agc_thr7_sf_valid_f, 
  agc_thr0_micro_flush_unq_c, 
  agc_thr1_micro_flush_unq_c, 
  agc_thr2_micro_flush_unq_c, 
  agc_thr3_micro_flush_unq_c, 
  agc_thr4_micro_flush_unq_c, 
  agc_thr5_micro_flush_unq_c, 
  agc_thr6_micro_flush_unq_c, 
  agc_thr7_micro_flush_unq_c, 
  agc_thr0_err_detect_c, 
  agc_thr1_err_detect_c, 
  agc_thr2_err_detect_c, 
  agc_thr3_err_detect_c, 
  agc_thr4_err_detect_c, 
  agc_thr5_err_detect_c, 
  agc_thr6_err_detect_c, 
  agc_thr7_err_detect_c, 
  agc_thr0_cmiss_stm_c, 
  agc_thr1_cmiss_stm_c, 
  agc_thr2_cmiss_stm_c, 
  agc_thr3_cmiss_stm_c, 
  agc_thr4_cmiss_stm_c, 
  agc_thr5_cmiss_stm_c, 
  agc_thr6_cmiss_stm_c, 
  agc_thr7_cmiss_stm_c, 
  ftu_agc_thr0_cmiss_c, 
  ftu_agc_thr1_cmiss_c, 
  ftu_agc_thr2_cmiss_c, 
  ftu_agc_thr3_cmiss_c, 
  ftu_agc_thr4_cmiss_c, 
  ftu_agc_thr5_cmiss_c, 
  ftu_agc_thr6_cmiss_c, 
  ftu_agc_thr7_cmiss_c, 
  ftu_thr0_inv_req_c, 
  ftu_thr1_inv_req_c, 
  ftu_thr2_inv_req_c, 
  ftu_thr3_inv_req_c, 
  ftu_thr4_inv_req_c, 
  ftu_thr5_inv_req_c, 
  ftu_thr6_inv_req_c, 
  ftu_thr7_inv_req_c, 
  ifu_ibuffer_write_c, 
  ftu_fetch_thr_c, 
  ftu_instr_sf_valid_c, 
  ftu_excp_way_d, 
  ftu_excp_tid_d, 
  ftu_excp_way_valid_d, 
  agc_fill_wrway_bf, 
  agc_sel_inv_index, 
  agc_thr0_lsu_no_ic_miss, 
  agc_thr1_lsu_no_ic_miss, 
  agc_thr2_lsu_no_ic_miss, 
  agc_thr3_lsu_no_ic_miss, 
  agc_thr4_lsu_no_ic_miss, 
  agc_thr5_lsu_no_ic_miss, 
  agc_thr6_lsu_no_ic_miss, 
  agc_thr7_lsu_no_ic_miss, 
  agc_thr0_itb_miss_c, 
  agc_thr1_itb_miss_c, 
  agc_thr2_itb_miss_c, 
  agc_thr3_itb_miss_c, 
  agc_thr4_itb_miss_c, 
  agc_thr5_itb_miss_c, 
  agc_thr6_itb_miss_c, 
  agc_thr7_itb_miss_c, 
  ftu_ic_no_err_c, 
  ftu_bus_0_is_first, 
  ftu_bus_1_is_first, 
  ftu_bus_2_is_first, 
  ftu_bus_3_is_first, 
  ftu_instr_valid_c, 
  ftu_exception_valid_c, 
  ftu_instr_exceptions_c, 
  agc_thr0_pcf_sel_bf, 
  agc_thr1_pcf_sel_bf, 
  agc_thr2_pcf_sel_bf, 
  agc_thr3_pcf_sel_bf, 
  agc_thr4_pcf_sel_bf, 
  agc_thr5_pcf_sel_bf, 
  agc_thr6_pcf_sel_bf, 
  agc_thr7_pcf_sel_bf, 
  agc_thr0_pcf_sel_last_bf, 
  agc_thr1_pcf_sel_last_bf, 
  agc_thr2_pcf_sel_last_bf, 
  agc_thr3_pcf_sel_last_bf, 
  agc_thr4_pcf_sel_last_bf, 
  agc_thr5_pcf_sel_last_bf, 
  agc_thr6_pcf_sel_last_bf, 
  agc_thr7_pcf_sel_last_bf, 
  agc_icv_wr_req_bf, 
  agc_icv_wrdata_bf, 
  agc_icv_wren_bf, 
  ftu_thr0_redirect_bf, 
  ftu_thr1_redirect_bf, 
  ftu_thr2_redirect_bf, 
  ftu_thr3_redirect_bf, 
  ftu_thr4_redirect_bf, 
  ftu_thr5_redirect_bf, 
  ftu_thr6_redirect_bf, 
  ftu_thr7_redirect_bf, 
  ftu_ibu_redirect_bf, 
  agc_thr0_tlu_redirect_bf, 
  agc_thr1_tlu_redirect_bf, 
  agc_thr2_tlu_redirect_bf, 
  agc_thr3_tlu_redirect_bf, 
  agc_thr4_tlu_redirect_bf, 
  agc_thr5_tlu_redirect_bf, 
  agc_thr6_tlu_redirect_bf, 
  agc_thr7_tlu_redirect_bf, 
  agc_kill_fetch_cv_c, 
  agc_pc_sel_for_c, 
  agc_instr_bp_sel_c, 
  agc_thr0_byp_incr_bit5, 
  agc_thr1_byp_incr_bit5, 
  agc_thr2_byp_incr_bit5, 
  agc_thr3_byp_incr_bit5, 
  agc_thr4_byp_incr_bit5, 
  agc_thr5_byp_incr_bit5, 
  agc_thr6_byp_incr_bit5, 
  agc_thr7_byp_incr_bit5, 
  agc_thr0_byp_pc_update_bf, 
  agc_thr1_byp_pc_update_bf, 
  agc_thr2_byp_pc_update_bf, 
  agc_thr3_byp_pc_update_bf, 
  agc_thr4_byp_pc_update_bf, 
  agc_thr5_byp_pc_update_bf, 
  agc_thr6_byp_pc_update_bf, 
  agc_thr7_byp_pc_update_bf, 
  agc_thr0_cntx_0_sel, 
  agc_thr0_cntx_1_sel, 
  agc_thr1_cntx_0_sel, 
  agc_thr1_cntx_1_sel, 
  agc_thr2_cntx_0_sel, 
  agc_thr2_cntx_1_sel, 
  agc_thr3_cntx_0_sel, 
  agc_thr3_cntx_1_sel, 
  agc_thr4_cntx_0_sel, 
  agc_thr4_cntx_1_sel, 
  agc_thr5_cntx_0_sel, 
  agc_thr5_cntx_1_sel, 
  agc_thr6_cntx_0_sel, 
  agc_thr6_cntx_1_sel, 
  agc_thr7_cntx_0_sel, 
  agc_thr7_cntx_1_sel, 
  agc_thr0_cntx_0_sel_ff, 
  agc_thr0_cntx_1_sel_ff, 
  agc_thr1_cntx_0_sel_ff, 
  agc_thr1_cntx_1_sel_ff, 
  agc_thr2_cntx_0_sel_ff, 
  agc_thr2_cntx_1_sel_ff, 
  agc_thr3_cntx_0_sel_ff, 
  agc_thr3_cntx_1_sel_ff, 
  agc_thr4_cntx_0_sel_ff, 
  agc_thr4_cntx_1_sel_ff, 
  agc_thr5_cntx_0_sel_ff, 
  agc_thr5_cntx_1_sel_ff, 
  agc_thr6_cntx_0_sel_ff, 
  agc_thr6_cntx_1_sel_ff, 
  agc_thr7_cntx_0_sel_ff, 
  agc_thr7_cntx_1_sel_ff, 
  ftu_mbi_tlb_cam_hit, 
  ftu_mbi_tlb_ctxt0_hit, 
  ftu_mbi_tlb_cam_mhit, 
  scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire l1clk_pm1;
wire l1clk_out;
wire thr0_first_level_sel_bf;
wire thr0_trap_pcaddr_is_valid_bf;
wire thr0_lsu_sync_bf;
wire thr0_replay_pc;
wire last_fetch_was_thr0_bf;
wire agc_by_pass_valid_bf;
wire [7:0] agc_by_pass_sel_bf;
wire thr0_br_misp_f;
wire thr0_matches_curr_f;
wire agc_thr0_br_misp_f;
wire thr1_first_level_sel_bf;
wire thr1_trap_pcaddr_is_valid_bf;
wire thr1_lsu_sync_bf;
wire thr1_replay_pc;
wire last_fetch_was_thr1_bf;
wire thr1_br_misp_f;
wire thr1_matches_curr_f;
wire agc_thr1_br_misp_f;
wire thr2_first_level_sel_bf;
wire thr2_trap_pcaddr_is_valid_bf;
wire thr2_lsu_sync_bf;
wire thr2_replay_pc;
wire last_fetch_was_thr2_bf;
wire thr2_br_misp_f;
wire thr2_matches_curr_f;
wire agc_thr2_br_misp_f;
wire thr3_first_level_sel_bf;
wire thr3_trap_pcaddr_is_valid_bf;
wire thr3_lsu_sync_bf;
wire thr3_replay_pc;
wire last_fetch_was_thr3_bf;
wire thr3_br_misp_f;
wire thr3_matches_curr_f;
wire agc_thr3_br_misp_f;
wire thr4_first_level_sel_bf;
wire thr4_trap_pcaddr_is_valid_bf;
wire thr4_lsu_sync_bf;
wire thr4_replay_pc;
wire last_fetch_was_thr4_bf;
wire thr4_br_misp_f;
wire thr4_matches_curr_f;
wire agc_thr4_br_misp_f;
wire thr5_first_level_sel_bf;
wire thr5_trap_pcaddr_is_valid_bf;
wire thr5_lsu_sync_bf;
wire thr5_replay_pc;
wire last_fetch_was_thr5_bf;
wire thr5_br_misp_f;
wire thr5_matches_curr_f;
wire agc_thr5_br_misp_f;
wire thr6_first_level_sel_bf;
wire thr6_trap_pcaddr_is_valid_bf;
wire thr6_lsu_sync_bf;
wire thr6_replay_pc;
wire last_fetch_was_thr6_bf;
wire thr6_br_misp_f;
wire thr6_matches_curr_f;
wire agc_thr6_br_misp_f;
wire thr7_first_level_sel_bf;
wire thr7_trap_pcaddr_is_valid_bf;
wire thr7_lsu_sync_bf;
wire thr7_replay_pc;
wire last_fetch_was_thr7_bf;
wire thr7_br_misp_f;
wire thr7_matches_curr_f;
wire agc_thr7_br_misp_f;
wire [3:0] trap_thread_g0;
wire [3:0] trap_thread_g1;
wire thr0_sf_is_valid_bf;
wire thr1_sf_is_valid_bf;
wire thr2_sf_is_valid_bf;
wire thr3_sf_is_valid_bf;
wire thr4_sf_is_valid_bf;
wire thr5_sf_is_valid_bf;
wire thr6_sf_is_valid_bf;
wire thr7_sf_is_valid_bf;
wire [7:0] load_flush_w;
wire [7:0] tid_dec_w;
wire tlu_ceter_pscce_reg_scanin;
wire tlu_ceter_pscce_reg_scanout;
wire [7:0] ceter_pscce_ff;
wire br_misp_data_reg_scanin;
wire br_misp_data_reg_scanout;
wire [1:0] tid1_m;
wire [1:0] tid0_m;
wire [1:0] agc_br_taken_m;
wire [1:0] agc_valid_m;
wire [1:0] br_taken_ff;
wire [1:0] br_taken_dup_ff;
wire [1:0] agc_br_taken_dup_m;
wire [1:0] agc_valid_dup_m;
wire br_misp_data_dup_reg_scanin;
wire br_misp_data_dup_reg_scanout;
wire [1:0] tid1_dup_m;
wire [1:0] tid0_dup_m;
wire [1:0] tid1_dup_b;
wire [1:0] tid0_dup_b;
wire [7:0] next_tid_dec_b;
wire tid_dec_w_reg_scanin;
wire tid_dec_w_reg_scanout;
wire curr_fetch_thr_c_reg_scanin;
wire curr_fetch_thr_c_reg_scanout;
wire [7:0] curr_fetch_thr_c;
wire cms_curr_fetch_thr_c_reg_scanin;
wire cms_curr_fetch_thr_c_reg_scanout;
wire [7:0] cms_curr_fetch_thr_c;
wire thr0_matches_curr_c;
wire thr1_matches_curr_c;
wire thr2_matches_curr_c;
wire thr3_matches_curr_c;
wire thr4_matches_curr_c;
wire thr5_matches_curr_c;
wire thr6_matches_curr_c;
wire thr7_matches_curr_c;
wire set_thr0_sf_valid_bf;
wire agc_thr0_reset_sf_c;
wire sf_valid_c;
wire reset_thr0_sf_valid_bf;
wire invalidation_req_f;
wire [7:0] agc_by_pass_sel_f;
wire agc_by_pass_valid_f;
wire [7:0] tlu_flush_ifu_f;
wire hold_thr0_sf_valid_bf;
wire next_thr0_sf_valid_bf;
wire thr0_sf_valid_f;
wire set_thr1_sf_valid_bf;
wire agc_thr1_reset_sf_c;
wire reset_thr1_sf_valid_bf;
wire hold_thr1_sf_valid_bf;
wire next_thr1_sf_valid_bf;
wire thr1_sf_valid_f;
wire set_thr2_sf_valid_bf;
wire agc_thr2_reset_sf_c;
wire reset_thr2_sf_valid_bf;
wire hold_thr2_sf_valid_bf;
wire next_thr2_sf_valid_bf;
wire thr2_sf_valid_f;
wire set_thr3_sf_valid_bf;
wire agc_thr3_reset_sf_c;
wire reset_thr3_sf_valid_bf;
wire hold_thr3_sf_valid_bf;
wire next_thr3_sf_valid_bf;
wire thr3_sf_valid_f;
wire set_thr4_sf_valid_bf;
wire agc_thr4_reset_sf_c;
wire reset_thr4_sf_valid_bf;
wire hold_thr4_sf_valid_bf;
wire next_thr4_sf_valid_bf;
wire thr4_sf_valid_f;
wire set_thr5_sf_valid_bf;
wire agc_thr5_reset_sf_c;
wire reset_thr5_sf_valid_bf;
wire hold_thr5_sf_valid_bf;
wire next_thr5_sf_valid_bf;
wire thr5_sf_valid_f;
wire set_thr6_sf_valid_bf;
wire agc_thr6_reset_sf_c;
wire reset_thr6_sf_valid_bf;
wire hold_thr6_sf_valid_bf;
wire next_thr6_sf_valid_bf;
wire thr6_sf_valid_f;
wire set_thr7_sf_valid_bf;
wire agc_thr7_reset_sf_c;
wire reset_thr7_sf_valid_bf;
wire hold_thr7_sf_valid_bf;
wire next_thr7_sf_valid_bf;
wire thr7_sf_valid_f;
wire sf_valid_reg_scanin;
wire sf_valid_reg_scanout;
wire sf_valid_dup_reg_scanin;
wire sf_valid_dup_reg_scanout;
wire instr_sf_valid_f;
wire sf_valid_by_pass_bf;
wire sf_valid_by_pass_f_reg_scanin;
wire sf_valid_by_pass_f_reg_scanout;
wire sf_valid_by_pass_f;
wire sf_valid_by_pass_c_reg_scanin;
wire sf_valid_by_pass_c_reg_scanout;
wire sf_valid_by_pass_c;
wire sf_v_c_scanin;
wire sf_v_c_scanout;
wire instr_sf_valid_c;
wire set_thr0_unc_valid_bf;
wire thr0_unc_is_valid;
wire reset_thr0_unc_valid_bf;
wire hold_thr0_unc_valid_bf;
wire next_thr0_unc_valid_bf;
wire thr0_unc_valid_f;
wire set_thr1_unc_valid_bf;
wire thr1_unc_is_valid;
wire reset_thr1_unc_valid_bf;
wire hold_thr1_unc_valid_bf;
wire next_thr1_unc_valid_bf;
wire thr1_unc_valid_f;
wire set_thr2_unc_valid_bf;
wire thr2_unc_is_valid;
wire reset_thr2_unc_valid_bf;
wire hold_thr2_unc_valid_bf;
wire next_thr2_unc_valid_bf;
wire thr2_unc_valid_f;
wire set_thr3_unc_valid_bf;
wire thr3_unc_is_valid;
wire reset_thr3_unc_valid_bf;
wire hold_thr3_unc_valid_bf;
wire next_thr3_unc_valid_bf;
wire thr3_unc_valid_f;
wire set_thr4_unc_valid_bf;
wire thr4_unc_is_valid;
wire reset_thr4_unc_valid_bf;
wire hold_thr4_unc_valid_bf;
wire next_thr4_unc_valid_bf;
wire thr4_unc_valid_f;
wire set_thr5_unc_valid_bf;
wire thr5_unc_is_valid;
wire reset_thr5_unc_valid_bf;
wire hold_thr5_unc_valid_bf;
wire next_thr5_unc_valid_bf;
wire thr5_unc_valid_f;
wire set_thr6_unc_valid_bf;
wire thr6_unc_is_valid;
wire reset_thr6_unc_valid_bf;
wire hold_thr6_unc_valid_bf;
wire next_thr6_unc_valid_bf;
wire thr6_unc_valid_f;
wire set_thr7_unc_valid_bf;
wire thr7_unc_is_valid;
wire reset_thr7_unc_valid_bf;
wire hold_thr7_unc_valid_bf;
wire next_thr7_unc_valid_bf;
wire thr7_unc_valid_f;
wire unc_valid_reg_scanin;
wire unc_valid_reg_scanout;
wire thr0_by_pass_pc_incr_bit5;
wire [4:2] thr0_by_pass_inc_pc_bf;
wire thr0_pc_f_inc_reg_scanin;
wire thr0_pc_f_inc_reg_scanout;
wire thr1_by_pass_pc_incr_bit5;
wire [4:2] thr1_by_pass_inc_pc_bf;
wire thr1_pc_f_inc_reg_scanin;
wire thr1_pc_f_inc_reg_scanout;
wire thr2_by_pass_pc_incr_bit5;
wire [4:2] thr2_by_pass_inc_pc_bf;
wire thr2_pc_f_inc_reg_scanin;
wire thr2_pc_f_inc_reg_scanout;
wire thr3_by_pass_pc_incr_bit5;
wire [4:2] thr3_by_pass_inc_pc_bf;
wire thr3_pc_f_inc_reg_scanin;
wire thr3_pc_f_inc_reg_scanout;
wire thr4_by_pass_pc_incr_bit5;
wire [4:2] thr4_by_pass_inc_pc_bf;
wire thr4_pc_f_inc_reg_scanin;
wire thr4_pc_f_inc_reg_scanout;
wire thr5_by_pass_pc_incr_bit5;
wire [4:2] thr5_by_pass_inc_pc_bf;
wire thr5_pc_f_inc_reg_scanin;
wire thr5_pc_f_inc_reg_scanout;
wire thr6_by_pass_pc_incr_bit5;
wire [4:2] thr6_by_pass_inc_pc_bf;
wire thr6_pc_f_inc_reg_scanin;
wire thr6_pc_f_inc_reg_scanout;
wire thr7_by_pass_pc_incr_bit5;
wire [4:2] thr7_by_pass_inc_pc_bf;
wire thr7_pc_f_inc_reg_scanin;
wire thr7_pc_f_inc_reg_scanout;
wire tlu_flush_ifu_reg_scanin;
wire tlu_flush_ifu_reg_scanout;
wire tlu_flush_ifu_d_reg_scanin;
wire tlu_flush_ifu_d_reg_scanout;
wire [7:0] tlu_flush_ifu_f_d;
wire [7:0] tlu_flush_ifu_f_dd;
wire cms_tlu_flush_ifu_reg_scanin;
wire cms_tlu_flush_ifu_reg_scanout;
wire [7:0] cms_tlu_flush_f;
wire load_flush_reg_scanin;
wire load_flush_reg_scanout;
wire [7:0] load_flush_f;
wire agc_kill_fetch_cv_f;
wire ftu_thr0_redirect_int_bf;
wire thr0_sf_kill;
wire thr0_sf_kill_d;
wire thr0_br_misp_no_match_f;
wire thr0_kill_after_invalidation;
wire thr0_kill_after_invalidation_d;
wire thr0_exception_valid_kill_c2;
wire ftu_thr1_redirect_int_bf;
wire thr1_sf_kill;
wire thr1_sf_kill_d;
wire thr1_br_misp_no_match_f;
wire thr1_kill_after_invalidation;
wire thr1_kill_after_invalidation_d;
wire thr1_exception_valid_kill_c2;
wire ftu_thr2_redirect_int_bf;
wire thr2_sf_kill;
wire thr2_sf_kill_d;
wire thr2_br_misp_no_match_f;
wire thr2_kill_after_invalidation;
wire thr2_kill_after_invalidation_d;
wire thr2_exception_valid_kill_c2;
wire ftu_thr3_redirect_int_bf;
wire thr3_sf_kill;
wire thr3_sf_kill_d;
wire thr3_br_misp_no_match_f;
wire thr3_kill_after_invalidation;
wire thr3_kill_after_invalidation_d;
wire thr3_exception_valid_kill_c2;
wire ftu_thr4_redirect_int_bf;
wire thr4_sf_kill;
wire thr4_sf_kill_d;
wire thr4_br_misp_no_match_f;
wire thr4_kill_after_invalidation;
wire thr4_kill_after_invalidation_d;
wire thr4_exception_valid_kill_c2;
wire ftu_thr5_redirect_int_bf;
wire thr5_sf_kill;
wire thr5_sf_kill_d;
wire thr5_br_misp_no_match_f;
wire thr5_kill_after_invalidation;
wire thr5_kill_after_invalidation_d;
wire thr5_exception_valid_kill_c2;
wire ftu_thr6_redirect_int_bf;
wire thr6_sf_kill;
wire thr6_sf_kill_d;
wire thr6_br_misp_no_match_f;
wire thr6_kill_after_invalidation;
wire thr6_kill_after_invalidation_d;
wire thr6_exception_valid_kill_c2;
wire ftu_thr7_redirect_int_bf;
wire thr7_sf_kill;
wire thr7_sf_kill_d;
wire thr7_br_misp_no_match_f;
wire thr7_kill_after_invalidation;
wire thr7_kill_after_invalidation_d;
wire thr7_exception_valid_kill_c2;
wire next_br_misp_match;
wire next_br_misp_match_int;
wire kill_fetch_vc_reg_scanin;
wire kill_fetch_vc_reg_scanout;
wire kill_fetch_cv_c_unq;
wire kill_fetch_vc_2_reg_scanin;
wire kill_fetch_vc_2_reg_scanout;
wire kill_fetch_cv_c_unq2;
wire exception_valid_kill_in;
wire exception_valid_c;
wire exception_valid_kill_reg_scanin;
wire exception_valid_kill_reg_scanout;
wire exception_valid_kill_c;
wire exception_valid_kill1_reg_scanin;
wire exception_valid_kill1_reg_scanout;
wire exception_valid_kill_int_c;
wire agc_kill_fetch_cv_int1_c;
wire agc_kill_fetch_cv_int2_c;
wire thr0_exception_valid_kill_in;
wire thr1_exception_valid_kill_in;
wire thr2_exception_valid_kill_in;
wire thr3_exception_valid_kill_in;
wire thr4_exception_valid_kill_in;
wire thr5_exception_valid_kill_in;
wire thr6_exception_valid_kill_in;
wire thr7_exception_valid_kill_in;
wire thrx_exception_valid_kill_reg_scanin;
wire thrx_exception_valid_kill_reg_scanout;
wire thr7_exception_valid_kill_c2_in;
wire thr6_exception_valid_kill_c2_in;
wire thr5_exception_valid_kill_c2_in;
wire thr4_exception_valid_kill_c2_in;
wire thr3_exception_valid_kill_c2_in;
wire thr2_exception_valid_kill_c2_in;
wire thr1_exception_valid_kill_c2_in;
wire thr0_exception_valid_kill_c2_in;
wire thr7_exception_valid_kill_c;
wire thr6_exception_valid_kill_c;
wire thr5_exception_valid_kill_c;
wire thr4_exception_valid_kill_c;
wire thr3_exception_valid_kill_c;
wire thr2_exception_valid_kill_c;
wire thr1_exception_valid_kill_c;
wire thr0_exception_valid_kill_c;
wire thrx_redirect_reg_scanin;
wire thrx_redirect_reg_scanout;
wire ftu_thr7_redirect_part_bf;
wire ftu_thr6_redirect_part_bf;
wire ftu_thr5_redirect_part_bf;
wire ftu_thr4_redirect_part_bf;
wire ftu_thr3_redirect_part_bf;
wire ftu_thr2_redirect_part_bf;
wire ftu_thr1_redirect_part_bf;
wire ftu_thr0_redirect_part_bf;
wire thrx_ibu_redirect_reg_scanin;
wire thrx_ibu_redirect_reg_scanout;
wire [7:0] to_ibu_redirect_part_bf;
wire single_thread_active;
wire [7:0] other_flushes_in;
wire other_flushes_reg_scanin;
wire other_flushes_reg_scanout;
wire [7:0] other_flushes_del;
wire [7:0] redirect_ibu_int_bf;
wire [7:0] next_by_pass_sel_bbf;
wire cmu_fill_byp_thread_reg_scanin;
wire cmu_fill_byp_thread_reg_scanout;
wire by_pass_thread_bf_reg_scanin;
wire by_pass_thread_bf_reg_scanout;
wire [7:0] by_pass_thread_bf;
wire by_pass_sel_f_reg_scanin;
wire by_pass_sel_f_reg_scanout;
wire by_pass_sel_c_reg_scanin;
wire by_pass_sel_c_reg_scanout;
wire [7:0] by_pass_thread_c;
wire by_pass_thread_f_reg_scanin;
wire by_pass_thread_f_reg_scanout;
wire [7:0] by_pass_thread_f;
wire fetchalid_cnq_reg_scanin;
wire fetchalid_cnq_reg_scanout;
wire agc_fetch_v_c_unq;
wire fetch_v_dup_c_reg_scanin;
wire fetch_v_dup_c_reg_scanout;
wire agc_fetch_v_c_dup_unq;
wire prev_by_pass_at_cycle_1;
wire agc_cycle_2_by_pass_ok_f;
wire agc_cycle_3_by_pass_ok_c;
wire prev_by_pass_at_cycle_2;
wire agc_cycle_3_by_pass_ok_f;
wire agc_fetch_v_int_c;
wire agc_fetch_v_c;
wire agc_cycle_2_by_pass_ok_bf;
wire agc_cycle_3_by_pass_ok_bf;
wire cycle_2_by_pass_f_reg_scanin;
wire cycle_2_by_pass_f_reg_scanout;
wire cycle_3_by_pass_f_reg_scanin;
wire cycle_3_by_pass_f_reg_scanout;
wire cycle_3_by_pass_c_reg_scanin;
wire cycle_3_by_pass_c_reg_scanout;
wire byp_valid_in;
wire thr0_kill_by_pass_bbf;
wire thr1_kill_by_pass_bbf;
wire thr2_kill_by_pass_bbf;
wire thr3_kill_by_pass_bbf;
wire thr4_kill_by_pass_bbf;
wire thr5_kill_by_pass_bbf;
wire thr6_kill_by_pass_bbf;
wire thr7_kill_by_pass_bbf;
wire cmu_any_data_ready_reg_scanin;
wire cmu_any_data_ready_reg_scanout;
wire agc_byp_valid;
wire tsm_thrx_kill_by_pass_reg_scanin;
wire tsm_thrx_kill_by_pass_reg_scanout;
wire thr7_kill_by_pass_bf;
wire thr6_kill_by_pass_bf;
wire thr5_kill_by_pass_bf;
wire thr4_kill_by_pass_bf;
wire thr3_kill_by_pass_bf;
wire thr2_kill_by_pass_bf;
wire thr1_kill_by_pass_bf;
wire thr0_kill_by_pass_bf;
wire kill2_by_pass_bf;
wire bypass_thread_killed;
wire next_by_pass_f_valid;
wire by_pass_v_f_reg_scanin;
wire by_pass_v_f_reg_scanout;
wire agc_by_pass_valid_unq_f;
wire bypass_thread_redirected_p_f;
wire bypass_thread_redirected_f;
wire agc_sel_by_pass_cycle_2_f;
wire agc_sel_by_pass_cycle_3_c;
wire agc_by_pass_valid_c;
wire next_by_pass_c_valid;
wire by_pass_v_c_reg_scanin;
wire by_pass_v_c_reg_scanout;
wire agc_sel_by_pass_cycle_2_int_f;
wire agc_sel_by_pass_cycle_3_int_c;
wire [2:0] agc_bypass_selects;
wire [3:0] by_pass_valid_instr_bf;
wire by_pass_instr_v_f_reg_scanin;
wire by_pass_instr_v_f_reg_scanout;
wire [3:0] by_pass_valid_instr_f;
wire by_pass_instr_v_c_reg_scanin;
wire by_pass_instr_v_c_reg_scanout;
wire [3:0] by_pass_valid_instr_c;
wire instr_0_v_q_c;
wire instr_1_v_q_c;
wire instr_2_v_q_c;
wire instr_3_v_q_c;
wire bus_3_is_first_in;
wire bus_2_is_first_in;
wire bus_1_is_first_in;
wire bus_0_is_first_in;
wire bus_first_reg_scanin;
wire bus_first_reg_scanout;
wire exception_valid_int_c;
wire thr0_byp_bf_kill_sf;
wire thr0_byp_f_kill_sf;
wire thr0_byp_c_kill_sf;
wire thr0_instr_kill_sf;
wire thr1_byp_bf_kill_sf;
wire thr1_byp_f_kill_sf;
wire thr1_byp_c_kill_sf;
wire thr1_instr_kill_sf;
wire thr2_byp_bf_kill_sf;
wire thr2_byp_f_kill_sf;
wire thr2_byp_c_kill_sf;
wire thr2_instr_kill_sf;
wire thr3_byp_bf_kill_sf;
wire thr3_byp_f_kill_sf;
wire thr3_byp_c_kill_sf;
wire thr3_instr_kill_sf;
wire thr4_byp_bf_kill_sf;
wire thr4_byp_f_kill_sf;
wire thr4_byp_c_kill_sf;
wire thr4_instr_kill_sf;
wire thr5_byp_bf_kill_sf;
wire thr5_byp_f_kill_sf;
wire thr5_byp_c_kill_sf;
wire thr5_instr_kill_sf;
wire thr6_byp_bf_kill_sf;
wire thr6_byp_f_kill_sf;
wire thr6_byp_c_kill_sf;
wire thr6_instr_kill_sf;
wire thr7_byp_bf_kill_sf;
wire thr7_byp_f_kill_sf;
wire thr7_byp_c_kill_sf;
wire thr7_instr_kill_sf;
wire thrx_sf_kill_reg_scanin;
wire thrx_sf_kill_reg_scanout;
wire any_instr_v_q_c;
wire mbist_data_in_reg_scanin;
wire mbist_data_in_reg_scanout;
wire [2:0] mbi_bist_way_bf;
wire [2:0] mbi_bist_word_en_bf;
wire mbi_run_bf;
wire mbi_icv_write_en_bf;
wire [7:0] mbi_wdata_bf;
wire agc_data_ready_bf;
wire [2:0] agc_cmu_fill_wrway_bf;
wire cmu_fill_wrway_reg_scanin;
wire cmu_fill_wrway_reg_scanout;
wire asi_mbist_way_f_reg_scanin;
wire asi_mbist_way_f_reg_scanout;
wire [2:0] agc_asi_mbist_way_f;
wire [7:0] next_wrway_bbf;
wire [1:0] vl_data;
wire vl_data_reg_scanin;
wire vl_data_reg_scanout;
wire itlb_valid_reg_scanin;
wire itlb_valid_reg_scanout;
wire [7:0] itlb_valid_c;
wire itlb_valid_dupl_reg_scanin;
wire itlb_valid_dupl_reg_scanout;
wire [7:0] itlb_valid_dupl_c;
wire va_hole_excp_extra;
wire next_va_hole_excp;
wire agc_itb_bypass_f;
wire va_hole_excp_c_reg_scanin;
wire va_hole_excp_c_reg_scanout;
wire va_hole_excp_c;
wire inv_ack;
wire [7:0] next_inv_way_bbf;
wire [7:0] next_inv_way1_bbf;
wire [7:0] asi_way_dec_bf;
wire addr_bit_5_bf_reg_scanin;
wire addr_bit_5_bf_reg_scanout;
wire phys_addr_bit_5_bf;
wire inv_bit_5_bf_reg_scanin;
wire inv_bit_5_bf_reg_scanout;
wire inv_addr_bit_5_bf;
wire inv_or_phys_addr_bit_5_bf;
wire agc_inv_line_bf;
wire wrway_bf_reg_scanin;
wire wrway_bf_reg_scanout;
wire [7:0] wrway_bf;
wire inv_way_bf_reg_scanin;
wire inv_way_bf_reg_scanout;
wire [7:0] inv_way_bf;
wire inv_way1_bf_reg_scanin;
wire inv_way1_bf_reg_scanout;
wire [7:0] inv_way1_bf;
wire [7:0] inv_or_wrway_bf;
wire [7:0] way1_inv;
wire agc_evic_line_bf;
wire next_inv_line;
wire inv_line_bf_reg_scanin;
wire inv_line_bf_reg_scanout;
wire evic_line_bf_reg_scanin;
wire evic_line_bf_reg_scanout;
wire [1:0] icv_wrdata;
wire next_data_ready_bbf;
wire data_ready_bf_reg_scanin;
wire data_ready_bf_reg_scanout;
wire l2_cache_miss_in_reg_scanin;
wire l2_cache_miss_in_reg_scanout;
wire l1_miss_in;
wire l2_miss_in;
wire l2_err_corr_in;
wire l2_err_ucorr_in;
wire l2_err_ndata_in;
wire l1_cache_1_miss;
wire l2_cache_1_miss;
wire l2_err_corr_1_ff;
wire l2_err_ucorr_1_ff;
wire l2_err_ndata_1_ff;
wire l2_cache_miss_1_reg_scanin;
wire l2_cache_miss_1_reg_scanout;
wire l1_cache_2_miss;
wire l2_cache_2_miss;
wire l2_err_corr_2_ff;
wire l2_err_ucorr_2_ff;
wire l2_err_ndata_2_ff;
wire l2_cache_miss_2_reg_scanin;
wire l2_cache_miss_2_reg_scanout;
wire l1_cache_3_miss;
wire l2_cache_3_miss;
wire l2_err_corr_3_ff;
wire l2_err_ucorr_3_ff;
wire l2_err_ndata_3_ff;
wire precise_en_bp_in;
wire cerer_icl2c_ff;
wire cerer_icl2u_ff;
wire cerer_icl2nd_ff;
wire l2_ucorr_err_byp_1;
wire l2_ucorr_err_byp_2;
wire l2_ucorr_err_byp_3;
wire l2_ucorr_err;
wire l2_corr_err_byp_1;
wire l2_corr_err_byp_2;
wire l2_corr_err_byp_3;
wire l2_corr_err;
wire l2_ndata_err_byp_1;
wire l2_ndata_err_byp_2;
wire l2_ndata_err_byp_3;
wire l2_ndata_err;
wire l2_cache_miss_byp_1;
wire l2_cache_miss_byp_2;
wire l2_cache_miss_byp_3;
wire l2_cache_miss;
wire l1_cache_miss;
wire itb_cmiss_c;
wire agc_ic_disable_thr_c;
wire itb_itb_miss_c;
wire agc_itb_cmiss_c_q;
wire ic_valid_err_no_priority;
wire itb_itb_acc_viol_c;
wire invalidation_req_c;
wire itb_tag_perr;
wire cerer_ittp_ff;
wire cerer_itdp_ff;
wire agc_tag_perror_c;
wire cerer_ictp_ff;
wire itb_mhit_en_c;
wire agc_qualify_cmiss;
wire agc_thrx_un_cacheable;
wire bus_0_valid_f;
wire bus_1_valid_f;
wire bus_2_valid_f;
wire bus_3_valid_f;
wire ic_instr_v_reg_scanin;
wire ic_instr_v_reg_scanout;
wire bus_3_valid_c;
wire bus_2_valid_c;
wire bus_1_valid_c;
wire bus_0_valid_c;
wire next_any_instr_v_c;
wire any_instr_v_c_reg_scanin;
wire any_instr_v_c_reg_scanout;
wire any_instr_v_c;
wire agc_itb_itb_miss_c_q;
wire agc_itb_itb_miss_c_int_q;
wire itb_itb_acc_viol_no_priority;
wire va_hole_exception_c;
wire nfo_tlb_exception_no_priority;
wire tag_perror_no_priority;
wire itb_mhit_no_priority;
wire tte_tag_parity_no_priority;
wire tag_multiple_hit_no_priority;
wire tte_data_parity_no_priority;
wire itb_itb_acc_viol_int_c;
wire va_hole_exception_int_c;
wire hpstate_reg_scanin;
wire hpstate_reg_scanout;
wire [7:0] hpstate_hpriv_ff;
wire [7:0] pstate_priv_ff;
wire next_priv_state;
wire priv_state_c_reg_scanin;
wire priv_state_c_reg_scanout;
wire agc_priv_state_c;
wire tlb_parity_reg_scanin;
wire tlb_parity_reg_scanout;
wire prty_256m_c;
wire prty_4m_c;
wire prty_64k_c;
wire prty_8k_c;
wire prty_ctxt0_c;
wire prty_ctxt1_c;
wire prty_ctxt;
wire tag_parity_gen;
wire agc_itc_real_c;
wire itlb_cam_vld_c_reg_scanin;
wire itlb_cam_vld_c_reg_scanout;
wire itlb_cam_vld_c;
wire cerer_en_reg_scanin;
wire cerer_en_reg_scanout;
wire cerer_ittm_ff;
wire cerer_icvp_ff;
wire cerer_ictm_ff;
wire tte_tag_parity_en_c;
wire tte_data_parity_en_c;
wire nfo_tlb_exception;
wire ic_valid_err_c_en;
wire ic_valid_err_c;
wire tag_perror_en_c;
wire tag_multiple_hit_en;
wire ic_tag_multiple_hit;
wire agc_ic_enable_thr_c;
wire l2_ucorr_err_en;
wire l2_corr_err_en;
wire l2_ndata_err_en;
wire l2_cache_miss_no_error;
wire l2_uncorr_err_en_no_l2_miss;
wire l2_cache_miss_n_corr;
wire l2_cache_miss_n_uncorr;
wire l2_cache_miss_n_ndata;
wire agc_itc_real_c_q;
wire va_hole_exception_c_r;
wire way_sel_all_but_0;
wire way_sel_all_but_1;
wire way_sel_all_but_2;
wire way_sel_all_but_3;
wire way_sel_all_but_4;
wire way_sel_all_but_5;
wire way_sel_all_but_6;
wire way_sel_all_but_7;
wire itc_real_f_reg_scanin;
wire itc_real_f_reg_scanout;
wire agc_itc_real_f;
wire itc_real_c_reg_scanin;
wire itc_real_c_reg_scanout;
wire cntx_sel_reg_scanin;
wire cntx_sel_reg_scanout;
wire lsu_no_icm_reg_scanin;
wire lsu_no_icm_reg_scanout;
wire ic_enable_reg_scanin;
wire ic_enable_reg_scanout;
wire [7:0] agc_icache_enable;
wire next_ic_enable_thr_c;
wire thr_c_ic_enable_reg_scanin;
wire thr_c_ic_enable_reg_scanout;
wire next_ic_enable_thr_c_l;
wire thr_c_ic_disable_reg_scanin;
wire thr_c_ic_disable_reg_scanout;
wire ic_valid_err_unq;
wire dff_8b_prty_7_scanin;
wire dff_8b_prty_7_scanout;
wire [3:0] w7_8b_parity_c;
wire [3:0] w6_8b_parity_c;
wire dff_8b_prty_5_scanin;
wire dff_8b_prty_5_scanout;
wire [3:0] w5_8b_parity_c;
wire [3:0] w4_8b_parity_c;
wire dff_8b_prty_3_scanin;
wire dff_8b_prty_3_scanout;
wire [3:0] w3_8b_parity_c;
wire [3:0] w2_8b_parity_c;
wire dff_8b_prty_1_scanin;
wire dff_8b_prty_1_scanout;
wire [3:0] w1_8b_parity_c;
wire [3:0] w0_8b_parity_c;
wire err_tag_w0_parity_c;
wire err_tag_w1_parity_c;
wire err_tag_w2_parity_c;
wire err_tag_w3_parity_c;
wire err_tag_w4_parity_c;
wire err_tag_w5_parity_c;
wire err_tag_w6_parity_c;
wire err_tag_w7_parity_c;
wire [7:0] agc_tag_pe_c;
wire err_excp_set;
wire [5:3] asi_mbist_addr_bf;
wire [7:0] word_en_asi;
wire asi_sel_word_reg_scanin;
wire asi_sel_word_reg_scanout;
wire [4:3] asi_mbist_addr_f;
wire [4:3] asi_mbist_addr_c;
wire thr0_valid_exception_p;
wire thr1_valid_exception_p;
wire thr2_valid_exception_p;
wire thr3_valid_exception_p;
wire thr4_valid_exception_p;
wire thr5_valid_exception_p;
wire thr6_valid_exception_p;
wire thr7_valid_exception_p;
wire thr0_way_write_en;
wire thr1_way_write_en;
wire thr2_way_write_en;
wire thr3_way_write_en;
wire thr4_way_write_en;
wire thr5_way_write_en;
wire thr6_way_write_en;
wire thr7_way_write_en;
wire [2:0] error_way_muxed_p;
wire ic_valid_err_p_en;
wire [2:0] valid_err_way_p;
wire tag_perror_en_p;
wire [2:0] perr_way_p;
wire tag_multiple_hit_en_p;
wire [2:0] fetch_way_p;
wire [2:0] thr0_excp_way_in;
wire [2:0] ftu_thr0_excp_way;
wire [2:0] thr1_excp_way_in;
wire [2:0] ftu_thr1_excp_way;
wire [2:0] thr2_excp_way_in;
wire [2:0] ftu_thr2_excp_way;
wire [2:0] thr3_excp_way_in;
wire [2:0] ftu_thr3_excp_way;
wire [2:0] thr4_excp_way_in;
wire [2:0] ftu_thr4_excp_way;
wire [2:0] thr5_excp_way_in;
wire [2:0] ftu_thr5_excp_way;
wire [2:0] thr6_excp_way_in;
wire [2:0] ftu_thr6_excp_way;
wire [2:0] thr7_excp_way_in;
wire [2:0] ftu_thr7_excp_way;
wire [2:0] fetch_way_p_in;
wire fetch_way_p_reg_scanin;
wire fetch_way_p_reg_scanout;
wire [7:0] valid_err_way;
wire [2:0] valid_err_way_p_in;
wire valid_err_way_p_reg_scanin;
wire valid_err_way_p_reg_scanout;
wire [2:0] perr_way_p_in;
wire tag_pe_way_scanin;
wire tag_pe_way_scanout;
wire tag_perror_en_reg_scanin;
wire tag_perror_en_reg_scanout;
wire way_thr0_keep_reg_scanin;
wire way_thr0_keep_reg_scanout;
wire way_thr1_keep_reg_scanin;
wire way_thr1_keep_reg_scanout;
wire way_thr2_keep_reg_scanin;
wire way_thr2_keep_reg_scanout;
wire way_thr3_keep_reg_scanin;
wire way_thr3_keep_reg_scanout;
wire way_thr4_keep_reg_scanin;
wire way_thr4_keep_reg_scanout;
wire way_thr5_keep_reg_scanin;
wire way_thr5_keep_reg_scanout;
wire way_thr6_keep_reg_scanin;
wire way_thr6_keep_reg_scanout;
wire way_thr7_keep_reg_scanin;
wire way_thr7_keep_reg_scanout;
wire excp_way_valid_in;
wire excp_way_d_reg_scanin;
wire excp_way_d_reg_scanout;
wire [2:0] excp_tid_d_in;
wire excp_tid_d_reg_scanin;
wire excp_tid_d_reg_scanout;
wire next_itlb_busy;
wire itlb_busy_reg_scanin;
wire itlb_busy_reg_scanout;
wire itlb_busy_bf;
wire itlb_busy_f_reg_scanin;
wire itlb_busy_f_reg_scanout;
wire itlb_busy_f;
wire ith_det_req_bbf;
wire ith_det_req_ff;
wire ith_det_req_ff_reg_scanin;
wire ith_det_req_ff_reg_scanout;
wire [7:0] next_enabled_thread;
wire enabled_thr_reg_dup_scanin;
wire enabled_thr_reg_dup_scanout;
wire [7:0] enabled_threads_dup;
wire next_single_thread_active;
wire single_thread_active_reg_scanin;
wire single_thread_active_reg_scanout;
wire [7:0] reset_invalidation_req;
wire [7:0] new_invalidation_req;
wire [7:0] set_invalidation_req;
wire [7:0] next_invalidation_req;
wire [7:0] invalidation_req_ff;
wire invalidation_req_reg_scanin;
wire invalidation_req_reg_scanout;
wire invalidation_req_dup_reg_scanin;
wire invalidation_req_dup_reg_scanout;
wire invalidation_req_c_reg_scanin;
wire invalidation_req_c_reg_scanout;
wire thrx_inv_kill_reg_scanin;
wire thrx_inv_kill_reg_scanout;
wire cms_itb_cmiss_c_q;
wire spares_scanin;
wire spares_scanout;
wire mbist_output_scanin;
wire mbist_output_scanout;
wire itb_cam_hit_c_1;
wire tlb_context0_hit_1;
wire itb_itb_mhit_c_1;
wire se;
 

input tcu_se_scancollar_out ;
input tcu_scan_en ;
input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;

input       tlu_trap_pc_0_valid    ;
input [1:0] tlu_retry    ;
input [7:0] tlu_ceter_pscce    ;

input       tlu_trap_pc_1_valid    ;
input [1:0] tlu_ifu_invalidate     ;

input [1:0] tlu_trap_0_tid    ;
input [1:0] tlu_trap_1_tid    ;

input [7:0]  spc_core_running_status;

input [7:0]  mbi_wdata;
input [8:6]  mbi_addr;
input [2:0]  mbi_cmpsel;
input        mbi_run;
input        mbi_icv_write_en;


input [7:0] tlu_flush_ifu    ;
input [7:0] tlu_ifu_hpstate_hpriv    ;
input [7:0] tlu_ifu_pstate_priv    ;

input         tlu_cerer_ittp         ;
input         tlu_cerer_itdp         ;
input         tlu_cerer_ittm         ;
input         tlu_cerer_icl2c     ;
input         tlu_cerer_icl2u     ; 
input         tlu_cerer_icl2nd    ; 
input         tlu_cerer_icvp         ;
input         tlu_cerer_ictp         ;
input         tlu_cerer_ictm         ;

input       tlb_nfo           ;
input       agd_va_hole_excp_f;
input [7:0] agd_itlb_valid_f     ;
input [7:0] agd_itlb_valid_dupl_f     ;

input       asi_ith_det_req        ;
input [1:0] asi_vl_arr_data        ; 
input       ftp_asi_tg_wr_req_hold ;
input       ftp_itlb_cam_vld_f ;
input [6:3] asi_addr_bf     ;
input [2:0] asi_way_bf     ;
input [47:2] ifu_agd_pc_f   ;
input [4:2] agd_thr0_pc_4_2_f     ;
input [4:2] agd_thr1_pc_4_2_f     ;
input [4:2] agd_thr2_pc_4_2_f     ;
input [4:2] agd_thr3_pc_4_2_f     ;
input [4:2] agd_thr4_pc_4_2_f     ;
input [4:2] agd_thr5_pc_4_2_f     ;
input [4:2] agd_thr6_pc_4_2_f     ;
input [4:2] agd_thr7_pc_4_2_f     ;

input  [1:0] dec_load_flush_w;     


input        itc_bypass_bf   ;
input        itc_real_bf   ;
input        itc_demap_next   ;

input [7:0] ftp_curr_fetch_thr_f    ; 
input [7:0] ftp_fetch_thr_q_f   ;


input       ftp_fill_req_q_bf            ;
input       ftp_any_thr_clken;

input [3:0] err_w0_8b_parity_f;
input [3:0] err_w1_8b_parity_f;
input [3:0] err_w2_8b_parity_f;
input [3:0] err_w3_8b_parity_f;
input [3:0] err_w4_8b_parity_f;
input [3:0] err_w5_8b_parity_f;
input [3:0] err_w6_8b_parity_f;
input [3:0] err_w7_8b_parity_f;


input	    tsm_thr0_ignore_by_pass;
input	    tsm_thr1_ignore_by_pass;
input	    tsm_thr2_ignore_by_pass;
input	    tsm_thr3_ignore_by_pass;
input	    tsm_thr4_ignore_by_pass;
input	    tsm_thr5_ignore_by_pass;
input       tsm_thr6_ignore_by_pass;
input       tsm_thr7_ignore_by_pass;

input       tsm_thr0_no_new_miss;
input       tsm_thr1_no_new_miss;
input       tsm_thr2_no_new_miss;
input       tsm_thr3_no_new_miss;
input       tsm_thr4_no_new_miss;
input       tsm_thr5_no_new_miss;
input       tsm_thr6_no_new_miss;
input       tsm_thr7_no_new_miss;

input       cmu_any_data_ready     ;   
input       cmu_any_un_cacheable    ;


input [1:0] cmu_l2_err     ;
input       cmu_l2miss     ;

input   cmu_thr0_data_ready;
input   cmu_thr1_data_ready;
input   cmu_thr2_data_ready;
input   cmu_thr3_data_ready;
input   cmu_thr4_data_ready;
input   cmu_thr5_data_ready;
input   cmu_thr6_data_ready;
input   cmu_thr7_data_ready;


input [2:0] cmu_fill_wrway            ;
input       cmu_icache_invalidate;
input       cmu_evic_invalidate;
input [2:0] cmu_icache_invalidate_way;
input [2:0] cmu_icache_inv_way1;
      
input       fill_paddr_bit_5    ;
input       inv_paddr_bit_5    ;
input       ftu_paddr_unq_39   ;
input [3:0] cmu_instr_v            ;


input [1:0] dec_br_taken_e ;
input [1:0] dec_valid_e;
input [1:0] ftp_tid0_e;
input [1:0] ftp_tid1_e;


input       ftp_fetch_v_f;
input       itb_chit_c;
input       itb_cam_hit_c;
input       itb_tte_p_c;
input       itb_itb_mhit_c;
input       itb_tte_tag_parity;
input       itb_tte_data_parity;
input [7:0] itb_icd_waysel_c;


input  [2:0]   lsu_ifu_tid_w;
input          lsu_ifu_wr_p0ctxt;
input          lsu_ifu_wr_p1ctxt;
input  [7:0]   lsu_ifu_no_miss;

input  [7:0]   lsu_ic_enable;
input  [7:0]   cmu_inval_ack;
input          ftp_asi_mbist_access_bf;

input		itd_prty_256m;
input		itd_prty_4m;
input		itd_prty_64k;
input		itd_prty_8k;
input		itd_prty_ctxt0;
input		itd_prty_ctxt1;
input [2:0]     tlb_pgsize;
input           tlb_context0_hit;


output [7:0] ftu_buffer_wr_en_f;


output       agc_itb_tag_perr_c ;

output [1:0] agc_vl_data_c;

output [3:0] agc_asi_sel_word_c;
output [7:0] agc_sel_tg_data_f;
output [7:0] agc_word_en_bf;
output [7:0] agc_by_pass_update_lru_bf;
output [7:0] agc_invalidation_req_ff;
output       agc_any_invalidation_req_f ;
output       agc_thr0_sf_valid_f ;
output       agc_thr1_sf_valid_f ;
output       agc_thr2_sf_valid_f ;
output       agc_thr3_sf_valid_f ;
output       agc_thr4_sf_valid_f ;
output       agc_thr5_sf_valid_f ;
output       agc_thr6_sf_valid_f ;
output       agc_thr7_sf_valid_f ;


output       agc_thr0_micro_flush_unq_c ;
output       agc_thr1_micro_flush_unq_c ;
output       agc_thr2_micro_flush_unq_c ;
output       agc_thr3_micro_flush_unq_c ;
output       agc_thr4_micro_flush_unq_c ;
output       agc_thr5_micro_flush_unq_c ;
output       agc_thr6_micro_flush_unq_c ;
output       agc_thr7_micro_flush_unq_c ;


output       agc_thr0_err_detect_c;
output       agc_thr1_err_detect_c;
output       agc_thr2_err_detect_c;
output       agc_thr3_err_detect_c;
output       agc_thr4_err_detect_c;
output       agc_thr5_err_detect_c;
output       agc_thr6_err_detect_c;
output       agc_thr7_err_detect_c;

output       agc_thr0_cmiss_stm_c;
output       agc_thr1_cmiss_stm_c;
output       agc_thr2_cmiss_stm_c;
output       agc_thr3_cmiss_stm_c;
output       agc_thr4_cmiss_stm_c;
output       agc_thr5_cmiss_stm_c;
output       agc_thr6_cmiss_stm_c;
output       agc_thr7_cmiss_stm_c;


output       ftu_agc_thr0_cmiss_c; 
output       ftu_agc_thr1_cmiss_c; 
output       ftu_agc_thr2_cmiss_c; 
output       ftu_agc_thr3_cmiss_c; 
output       ftu_agc_thr4_cmiss_c; 
output       ftu_agc_thr5_cmiss_c; 
output       ftu_agc_thr6_cmiss_c; 
output       ftu_agc_thr7_cmiss_c; 

output       ftu_thr0_inv_req_c ;
output       ftu_thr1_inv_req_c ;
output       ftu_thr2_inv_req_c ;
output       ftu_thr3_inv_req_c ;
output       ftu_thr4_inv_req_c ;
output       ftu_thr5_inv_req_c ;
output       ftu_thr6_inv_req_c ;
output       ftu_thr7_inv_req_c ;

output [7:0] ifu_ibuffer_write_c;
output [7:0] ftu_fetch_thr_c;
output       ftu_instr_sf_valid_c;

output [2:0] ftu_excp_way_d;
output [2:0] ftu_excp_tid_d;
output       ftu_excp_way_valid_d;


output [2:0] agc_fill_wrway_bf;
output [3:0] agc_sel_inv_index ;

output       agc_thr0_lsu_no_ic_miss;
output       agc_thr1_lsu_no_ic_miss;
output       agc_thr2_lsu_no_ic_miss;
output       agc_thr3_lsu_no_ic_miss;
output       agc_thr4_lsu_no_ic_miss;
output       agc_thr5_lsu_no_ic_miss;
output       agc_thr6_lsu_no_ic_miss;
output       agc_thr7_lsu_no_ic_miss;

output       agc_thr0_itb_miss_c;
output       agc_thr1_itb_miss_c;
output       agc_thr2_itb_miss_c;
output       agc_thr3_itb_miss_c;
output       agc_thr4_itb_miss_c;
output       agc_thr5_itb_miss_c;
output       agc_thr6_itb_miss_c;
output       agc_thr7_itb_miss_c;

output       ftu_ic_no_err_c   ;            // Data being by_passed does not have an error 

output       ftu_bus_0_is_first ;           // bus 0 contains first instr
output       ftu_bus_1_is_first ;           // bus 1 contains first instr
output       ftu_bus_2_is_first ;           // bus 2 contains first instr
output       ftu_bus_3_is_first ;           // bus 3 contains first instr

output [3:0] ftu_instr_valid_c;
output       ftu_exception_valid_c ;

output [4:0] ftu_instr_exceptions_c;

            
output [3:0] agc_thr0_pcf_sel_bf;
output [3:0] agc_thr1_pcf_sel_bf;
output [3:0] agc_thr2_pcf_sel_bf;
output [3:0] agc_thr3_pcf_sel_bf;
output [3:0] agc_thr4_pcf_sel_bf;
output [3:0] agc_thr5_pcf_sel_bf;
output [3:0] agc_thr6_pcf_sel_bf;
output [3:0] agc_thr7_pcf_sel_bf;

output [1:0] agc_thr0_pcf_sel_last_bf;
output [1:0] agc_thr1_pcf_sel_last_bf;
output [1:0] agc_thr2_pcf_sel_last_bf;
output [1:0] agc_thr3_pcf_sel_last_bf;
output [1:0] agc_thr4_pcf_sel_last_bf;
output [1:0] agc_thr5_pcf_sel_last_bf;
output [1:0] agc_thr6_pcf_sel_last_bf;
output [1:0] agc_thr7_pcf_sel_last_bf;
            

output        agc_icv_wr_req_bf;    
output [31:0] agc_icv_wrdata_bf;    
output [31:0] agc_icv_wren_bf;     

            
output       ftu_thr0_redirect_bf;
output       ftu_thr1_redirect_bf;
output       ftu_thr2_redirect_bf;
output       ftu_thr3_redirect_bf;
output       ftu_thr4_redirect_bf;
output       ftu_thr5_redirect_bf;
output       ftu_thr6_redirect_bf;
output       ftu_thr7_redirect_bf;

output [7:0] ftu_ibu_redirect_bf  ;

output       agc_thr0_tlu_redirect_bf;
output       agc_thr1_tlu_redirect_bf;
output       agc_thr2_tlu_redirect_bf;
output       agc_thr3_tlu_redirect_bf;
output       agc_thr4_tlu_redirect_bf;
output       agc_thr5_tlu_redirect_bf;
output       agc_thr6_tlu_redirect_bf;
output       agc_thr7_tlu_redirect_bf;


output       agc_kill_fetch_cv_c;

output [3:0] agc_pc_sel_for_c ;
output [2:0] agc_instr_bp_sel_c ;

output       agc_thr0_byp_incr_bit5 ;
output       agc_thr1_byp_incr_bit5 ;
output       agc_thr2_byp_incr_bit5 ;
output       agc_thr3_byp_incr_bit5 ;
output       agc_thr4_byp_incr_bit5 ;
output       agc_thr5_byp_incr_bit5 ;
output       agc_thr6_byp_incr_bit5 ;
output       agc_thr7_byp_incr_bit5 ;

output [4:2] agc_thr0_byp_pc_update_bf ;
output [4:2] agc_thr1_byp_pc_update_bf ;
output [4:2] agc_thr2_byp_pc_update_bf ;
output [4:2] agc_thr3_byp_pc_update_bf ;
output [4:2] agc_thr4_byp_pc_update_bf ;
output [4:2] agc_thr5_byp_pc_update_bf ;
output [4:2] agc_thr6_byp_pc_update_bf ;
output [4:2] agc_thr7_byp_pc_update_bf ;

output  [1:0]    agc_thr0_cntx_0_sel;
output  [1:0]    agc_thr0_cntx_1_sel;
output  [1:0]    agc_thr1_cntx_0_sel;
output  [1:0]    agc_thr1_cntx_1_sel;
output  [1:0]    agc_thr2_cntx_0_sel;
output  [1:0]    agc_thr2_cntx_1_sel;
output  [1:0]    agc_thr3_cntx_0_sel;
output  [1:0]    agc_thr3_cntx_1_sel;
output  [1:0]    agc_thr4_cntx_0_sel;
output  [1:0]    agc_thr4_cntx_1_sel;
output  [1:0]    agc_thr5_cntx_0_sel;
output  [1:0]    agc_thr5_cntx_1_sel;
output  [1:0]    agc_thr6_cntx_0_sel;
output  [1:0]    agc_thr6_cntx_1_sel;
output  [1:0]    agc_thr7_cntx_0_sel;
output  [1:0]    agc_thr7_cntx_1_sel;

output           agc_thr0_cntx_0_sel_ff;
output           agc_thr0_cntx_1_sel_ff;

output           agc_thr1_cntx_0_sel_ff;
output           agc_thr1_cntx_1_sel_ff;

output           agc_thr2_cntx_0_sel_ff;
output           agc_thr2_cntx_1_sel_ff;

output           agc_thr3_cntx_0_sel_ff;
output           agc_thr3_cntx_1_sel_ff;

output           agc_thr4_cntx_0_sel_ff;
output           agc_thr4_cntx_1_sel_ff;

output           agc_thr5_cntx_0_sel_ff;
output           agc_thr5_cntx_1_sel_ff;

output           agc_thr6_cntx_0_sel_ff;
output           agc_thr6_cntx_1_sel_ff;

output           agc_thr7_cntx_0_sel_ff;
output           agc_thr7_cntx_1_sel_ff;

output		ftu_mbi_tlb_cam_hit;
output		ftu_mbi_tlb_ctxt0_hit;
output		ftu_mbi_tlb_cam_mhit;	
output   scan_out;

// renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0 ;
assign siclk = spc_aclk;
assign soclk = spc_bclk;


ifu_ftu_agc_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

ifu_ftu_agc_ctl_l1clkhdr_ctl_macro clkgen_pm (
 .l2clk(l2clk),
 .l1en (ftp_any_thr_clken ),
 .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


ifu_ftu_agc_ctl_l1clkhdr_ctl_macro scancollar_out_clkgen (
        .l2clk  (l2clk),
        .l1en   (1'b1),
        .se     (tcu_se_scancollar_out),
        .l1clk  (l1clk_out),
  .pce_ov(pce_ov),
  .stop(stop)
);


///////////////////////////////////////////////////////////////////////
// Generate selects for the second level of redirection muxing for   //
// thread_0 to thread_7                                              //
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// Second level of redirection muxing                                //
///////////////////////////////////////////////////////////////////////
assign thr0_first_level_sel_bf    = thr0_trap_pcaddr_is_valid_bf | thr0_lsu_sync_bf |
                                    thr0_replay_pc ;  
assign agc_thr0_pcf_sel_bf[0] =  thr0_replay_pc | thr0_trap_pcaddr_is_valid_bf | 
                                 thr0_lsu_sync_bf ;
assign agc_thr0_pcf_sel_bf[1] = ~thr0_first_level_sel_bf & last_fetch_was_thr0_bf ;
assign agc_thr0_pcf_sel_bf[2] = ~thr0_first_level_sel_bf & ~last_fetch_was_thr0_bf &  (agc_by_pass_valid_bf & agc_by_pass_sel_bf[0]);
assign agc_thr0_pcf_sel_bf[3] = ~thr0_first_level_sel_bf & ~last_fetch_was_thr0_bf & ~(agc_by_pass_valid_bf & agc_by_pass_sel_bf[0]);

assign agc_thr0_pcf_sel_last_bf[0] =  thr0_br_misp_f & ~(thr0_matches_curr_f & ftp_fetch_v_f) & 
                                     ~thr0_lsu_sync_bf & ~thr0_trap_pcaddr_is_valid_bf ;  
assign agc_thr0_pcf_sel_last_bf[1] = ~agc_thr0_pcf_sel_last_bf[0]  ;  

assign agc_thr0_br_misp_f          =  thr0_br_misp_f   ;

assign thr1_first_level_sel_bf    = thr1_trap_pcaddr_is_valid_bf | thr1_lsu_sync_bf |
                                    thr1_replay_pc ;  
assign agc_thr1_pcf_sel_bf[0] =  thr1_replay_pc | thr1_trap_pcaddr_is_valid_bf | 
                                 thr1_lsu_sync_bf  ;
assign agc_thr1_pcf_sel_bf[1] = ~thr1_first_level_sel_bf & last_fetch_was_thr1_bf ;
assign agc_thr1_pcf_sel_bf[2] = ~thr1_first_level_sel_bf & ~last_fetch_was_thr1_bf &  (agc_by_pass_valid_bf & agc_by_pass_sel_bf[1]);
assign agc_thr1_pcf_sel_bf[3] = ~thr1_first_level_sel_bf & ~last_fetch_was_thr1_bf & ~(agc_by_pass_valid_bf & agc_by_pass_sel_bf[1]);

assign agc_thr1_pcf_sel_last_bf[0] =  thr1_br_misp_f & ~(thr1_matches_curr_f & ftp_fetch_v_f) &  
                                     ~thr1_lsu_sync_bf & ~thr1_trap_pcaddr_is_valid_bf ;  
assign agc_thr1_pcf_sel_last_bf[1] = ~agc_thr1_pcf_sel_last_bf[0]  ;  

assign agc_thr1_br_misp_f          =  thr1_br_misp_f   ;

assign thr2_first_level_sel_bf    = thr2_trap_pcaddr_is_valid_bf | thr2_lsu_sync_bf |
                                    thr2_replay_pc ;  
assign agc_thr2_pcf_sel_bf[0] =  thr2_replay_pc | thr2_trap_pcaddr_is_valid_bf | 
                                 thr2_lsu_sync_bf ;
assign agc_thr2_pcf_sel_bf[1] = ~thr2_first_level_sel_bf & last_fetch_was_thr2_bf ;
assign agc_thr2_pcf_sel_bf[2] = ~thr2_first_level_sel_bf & ~last_fetch_was_thr2_bf &  (agc_by_pass_valid_bf & agc_by_pass_sel_bf[2]);
assign agc_thr2_pcf_sel_bf[3] = ~thr2_first_level_sel_bf & ~last_fetch_was_thr2_bf & ~(agc_by_pass_valid_bf & agc_by_pass_sel_bf[2]);

assign agc_thr2_pcf_sel_last_bf[0] =  thr2_br_misp_f & ~(thr2_matches_curr_f & ftp_fetch_v_f) &   
                                     ~thr2_lsu_sync_bf & ~thr2_trap_pcaddr_is_valid_bf ;  
assign agc_thr2_pcf_sel_last_bf[1] = ~agc_thr2_pcf_sel_last_bf[0]  ;  


assign agc_thr2_br_misp_f          =  thr2_br_misp_f   ;

assign thr3_first_level_sel_bf    = thr3_trap_pcaddr_is_valid_bf | thr3_lsu_sync_bf |
                                    thr3_replay_pc ;  
assign agc_thr3_pcf_sel_bf[0] =  thr3_replay_pc | thr3_trap_pcaddr_is_valid_bf | 
                                 thr3_lsu_sync_bf ;
assign agc_thr3_pcf_sel_bf[1] = ~thr3_first_level_sel_bf & last_fetch_was_thr3_bf ;
assign agc_thr3_pcf_sel_bf[2] = ~thr3_first_level_sel_bf & ~last_fetch_was_thr3_bf &  (agc_by_pass_valid_bf & agc_by_pass_sel_bf[3]);
assign agc_thr3_pcf_sel_bf[3] = ~thr3_first_level_sel_bf & ~last_fetch_was_thr3_bf & ~(agc_by_pass_valid_bf & agc_by_pass_sel_bf[3]);

assign agc_thr3_pcf_sel_last_bf[0] =  thr3_br_misp_f & ~(thr3_matches_curr_f & ftp_fetch_v_f) &  
                                     ~thr3_lsu_sync_bf & ~thr3_trap_pcaddr_is_valid_bf ;  
assign agc_thr3_pcf_sel_last_bf[1] = ~agc_thr3_pcf_sel_last_bf[0]  ;  

assign agc_thr3_br_misp_f          =  thr3_br_misp_f   ;

assign thr4_first_level_sel_bf    = thr4_trap_pcaddr_is_valid_bf | thr4_lsu_sync_bf |
                                    thr4_replay_pc ;  
assign agc_thr4_pcf_sel_bf[0] =  thr4_replay_pc | thr4_trap_pcaddr_is_valid_bf | 
                                 thr4_lsu_sync_bf ;
assign agc_thr4_pcf_sel_bf[1] = ~thr4_first_level_sel_bf & last_fetch_was_thr4_bf ;
assign agc_thr4_pcf_sel_bf[2] = ~thr4_first_level_sel_bf & ~last_fetch_was_thr4_bf &  (agc_by_pass_valid_bf & agc_by_pass_sel_bf[4]);
assign agc_thr4_pcf_sel_bf[3] = ~thr4_first_level_sel_bf & ~last_fetch_was_thr4_bf & ~(agc_by_pass_valid_bf & agc_by_pass_sel_bf[4]);

assign agc_thr4_pcf_sel_last_bf[0] =  thr4_br_misp_f  & ~(thr4_matches_curr_f & ftp_fetch_v_f) &   
                                     ~thr4_lsu_sync_bf & ~thr4_trap_pcaddr_is_valid_bf ;  
assign agc_thr4_pcf_sel_last_bf[1] = ~agc_thr4_pcf_sel_last_bf[0]  ;  

assign agc_thr4_br_misp_f          =  thr4_br_misp_f   ;

assign thr5_first_level_sel_bf    = thr5_trap_pcaddr_is_valid_bf | thr5_lsu_sync_bf |
                                    thr5_replay_pc ;  
assign agc_thr5_pcf_sel_bf[0] =  thr5_replay_pc | thr5_trap_pcaddr_is_valid_bf | 
                                 thr5_lsu_sync_bf ;
assign agc_thr5_pcf_sel_bf[1] = ~thr5_first_level_sel_bf & last_fetch_was_thr5_bf ;
assign agc_thr5_pcf_sel_bf[2] = ~thr5_first_level_sel_bf & ~last_fetch_was_thr5_bf &  (agc_by_pass_valid_bf & agc_by_pass_sel_bf[5]);
assign agc_thr5_pcf_sel_bf[3] = ~thr5_first_level_sel_bf & ~last_fetch_was_thr5_bf & ~(agc_by_pass_valid_bf & agc_by_pass_sel_bf[5]);

assign agc_thr5_pcf_sel_last_bf[0] =  thr5_br_misp_f  & ~(thr5_matches_curr_f & ftp_fetch_v_f) &   
                                     ~thr5_lsu_sync_bf & ~thr5_trap_pcaddr_is_valid_bf ;  
assign agc_thr5_pcf_sel_last_bf[1] = ~agc_thr5_pcf_sel_last_bf[0]  ;  

assign agc_thr5_br_misp_f          =  thr5_br_misp_f   ;

assign thr6_first_level_sel_bf    = thr6_trap_pcaddr_is_valid_bf | thr6_lsu_sync_bf |
                                    thr6_replay_pc ;  
assign agc_thr6_pcf_sel_bf[0] =  thr6_replay_pc | thr6_trap_pcaddr_is_valid_bf | 
                                 thr6_lsu_sync_bf ;
assign agc_thr6_pcf_sel_bf[1] = ~thr6_first_level_sel_bf & last_fetch_was_thr6_bf ;
assign agc_thr6_pcf_sel_bf[2] = ~thr6_first_level_sel_bf & ~last_fetch_was_thr6_bf &  (agc_by_pass_valid_bf & agc_by_pass_sel_bf[6]);
assign agc_thr6_pcf_sel_bf[3] = ~thr6_first_level_sel_bf & ~last_fetch_was_thr6_bf & ~(agc_by_pass_valid_bf & agc_by_pass_sel_bf[6]);

assign agc_thr6_pcf_sel_last_bf[0] =  thr6_br_misp_f  & ~(thr6_matches_curr_f & ftp_fetch_v_f) &   
                                     ~thr6_lsu_sync_bf & ~thr6_trap_pcaddr_is_valid_bf ;  
assign agc_thr6_pcf_sel_last_bf[1] = ~agc_thr6_pcf_sel_last_bf[0]  ;  

assign agc_thr6_br_misp_f          =  thr6_br_misp_f   ;


assign thr7_first_level_sel_bf    = thr7_trap_pcaddr_is_valid_bf | thr7_lsu_sync_bf |
                                    thr7_replay_pc ;  
assign agc_thr7_pcf_sel_bf[0] =  thr7_replay_pc | thr7_trap_pcaddr_is_valid_bf | 
                                 thr7_lsu_sync_bf ;
assign agc_thr7_pcf_sel_bf[1] = ~thr7_first_level_sel_bf & last_fetch_was_thr7_bf ;
assign agc_thr7_pcf_sel_bf[2] = ~thr7_first_level_sel_bf & ~last_fetch_was_thr7_bf &  (agc_by_pass_valid_bf & agc_by_pass_sel_bf[7]);
assign agc_thr7_pcf_sel_bf[3] = ~thr7_first_level_sel_bf & ~last_fetch_was_thr7_bf & ~(agc_by_pass_valid_bf & agc_by_pass_sel_bf[7]);

assign agc_thr7_pcf_sel_last_bf[0] =  thr7_br_misp_f  & ~(thr7_matches_curr_f & ftp_fetch_v_f) &   
                                     ~thr7_lsu_sync_bf & ~thr7_trap_pcaddr_is_valid_bf ;  
assign agc_thr7_pcf_sel_last_bf[1] = ~agc_thr7_pcf_sel_last_bf[0]  ;  

assign agc_thr7_br_misp_f          =  thr7_br_misp_f   ;


///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// Decode which thread is trapping                                   //
// Note: two threads can be trapping at the same time; One from each //
// Thread group.                                                     //
///////////////////////////////////////////////////////////////////////
assign trap_thread_g0[0] = ~tlu_trap_0_tid[1] & ~tlu_trap_0_tid[0] ; 
assign trap_thread_g0[1] = ~tlu_trap_0_tid[1] &  tlu_trap_0_tid[0] ; 
assign trap_thread_g0[2] =  tlu_trap_0_tid[1] & ~tlu_trap_0_tid[0] ; 
assign trap_thread_g0[3] =  tlu_trap_0_tid[1] &  tlu_trap_0_tid[0] ; 

assign trap_thread_g1[0] = ~tlu_trap_1_tid[1] & ~tlu_trap_1_tid[0] ; 
assign trap_thread_g1[1] = ~tlu_trap_1_tid[1] &  tlu_trap_1_tid[0] ; 
assign trap_thread_g1[2] =  tlu_trap_1_tid[1] & ~tlu_trap_1_tid[0] ; 
assign trap_thread_g1[3] =  tlu_trap_1_tid[1] &  tlu_trap_1_tid[0] ; 

assign thr0_trap_pcaddr_is_valid_bf  = tlu_trap_pc_0_valid  & trap_thread_g0[0] ; 
assign thr1_trap_pcaddr_is_valid_bf  = tlu_trap_pc_0_valid  & trap_thread_g0[1] ; 
assign thr2_trap_pcaddr_is_valid_bf  = tlu_trap_pc_0_valid  & trap_thread_g0[2] ; 
assign thr3_trap_pcaddr_is_valid_bf  = tlu_trap_pc_0_valid  & trap_thread_g0[3] ; 

assign thr4_trap_pcaddr_is_valid_bf  = tlu_trap_pc_1_valid  & trap_thread_g1[0] ; 
assign thr5_trap_pcaddr_is_valid_bf  = tlu_trap_pc_1_valid  & trap_thread_g1[1] ; 
assign thr6_trap_pcaddr_is_valid_bf  = tlu_trap_pc_1_valid  & trap_thread_g1[2] ; 
assign thr7_trap_pcaddr_is_valid_bf  = tlu_trap_pc_1_valid  & trap_thread_g1[3] ; 

assign thr0_sf_is_valid_bf = tlu_retry[0] & trap_thread_g0[0] & tlu_trap_pc_0_valid;
assign thr1_sf_is_valid_bf = tlu_retry[0] & trap_thread_g0[1] & tlu_trap_pc_0_valid;
assign thr2_sf_is_valid_bf = tlu_retry[0] & trap_thread_g0[2] & tlu_trap_pc_0_valid;
assign thr3_sf_is_valid_bf = tlu_retry[0] & trap_thread_g0[3] & tlu_trap_pc_0_valid;
			     
assign thr4_sf_is_valid_bf = tlu_retry[1] & trap_thread_g1[0] & tlu_trap_pc_1_valid;
assign thr5_sf_is_valid_bf = tlu_retry[1] & trap_thread_g1[1] & tlu_trap_pc_1_valid;
assign thr6_sf_is_valid_bf = tlu_retry[1] & trap_thread_g1[2] & tlu_trap_pc_1_valid;
assign thr7_sf_is_valid_bf = tlu_retry[1] & trap_thread_g1[3] & tlu_trap_pc_1_valid;
///////////////////////////////////////////////////////////////////////
// Decode which thread has LSU sync                                  //
// Note: two threads can be synced by LSU at the same time;          //
// One from each thread group.                                       //
///////////////////////////////////////////////////////////////////////
assign load_flush_w[0] = dec_load_flush_w[0] & tid_dec_w[0] ; 
assign load_flush_w[1] = dec_load_flush_w[0] & tid_dec_w[1] ; 
assign load_flush_w[2] = dec_load_flush_w[0] & tid_dec_w[2] ; 
assign load_flush_w[3] = dec_load_flush_w[0] & tid_dec_w[3] ; 
assign load_flush_w[4] = dec_load_flush_w[1] & tid_dec_w[4] ; 
assign load_flush_w[5] = dec_load_flush_w[1] & tid_dec_w[5] ; 
assign load_flush_w[6] = dec_load_flush_w[1] & tid_dec_w[6] ; 
assign load_flush_w[7] = dec_load_flush_w[1] & tid_dec_w[7] ; 

assign thr0_lsu_sync_bf  = load_flush_w[0] ; 
assign thr1_lsu_sync_bf  = load_flush_w[1] ; 
assign thr2_lsu_sync_bf  = load_flush_w[2] ; 
assign thr3_lsu_sync_bf  = load_flush_w[3] ; 

assign thr4_lsu_sync_bf  = load_flush_w[4] ; 
assign thr5_lsu_sync_bf  = load_flush_w[5] ; 
assign thr6_lsu_sync_bf  = load_flush_w[6] ; 
assign thr7_lsu_sync_bf  = load_flush_w[7] ; 

///////////////////////////////////////////////////////////////////////


///////////////////////////////////////////////////////////////////////

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 tlu_ceter_pscce_reg  (
  .scan_in(tlu_ceter_pscce_reg_scanin),
  .scan_out(tlu_ceter_pscce_reg_scanout),
  .l1clk( l1clk  ),
  .din  (tlu_ceter_pscce[7:0]),
  .dout (ceter_pscce_ff[7:0]),
  .siclk(siclk),
  .soclk(soclk));
 
///////////////////////////////////////////////////////////////////////
// Decode which thread has a branch misprediction this cycle         //
// Note two threads can have branch misprediction at the same time;  //
// One from each thread group.                                       // 
///////////////////////////////////////////////////////////////////////


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 br_misp_data_reg  (
 .scan_in(br_misp_data_reg_scanin),
 .scan_out(br_misp_data_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({ftp_tid1_e[1:0], ftp_tid0_e[1:0] , dec_br_taken_e[1:0],dec_valid_e[1:0]}),
 .dout ({tid1_m[1:0], tid0_m[1:0] , agc_br_taken_m[1:0],agc_valid_m[1:0]}),
  .siclk(siclk),
  .soclk(soclk));

assign br_taken_ff[1:0] = agc_br_taken_m[1:0] & agc_valid_m[1:0] ;
assign br_taken_dup_ff[1:0] = agc_br_taken_dup_m[1:0] & agc_valid_dup_m[1:0] ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_12 br_misp_data_dup_reg  (
 .scan_in(br_misp_data_dup_reg_scanin),
 .scan_out(br_misp_data_dup_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({ftp_tid1_e[1:0], ftp_tid0_e[1:0], tid1_dup_m[1:0] , tid0_dup_m[1:0], dec_br_taken_e[1:0],dec_valid_e[1:0]}),
 .dout ({tid1_dup_m[1:0], tid0_dup_m[1:0], tid1_dup_b[1:0] , tid0_dup_b[1:0],agc_br_taken_dup_m[1:0], agc_valid_dup_m[1:0]}),
  .siclk(siclk),
  .soclk(soclk));

assign next_tid_dec_b[0] = ~tid0_dup_b[1] & ~tid0_dup_b[0] ;
assign next_tid_dec_b[1] = ~tid0_dup_b[1] &  tid0_dup_b[0] ;
assign next_tid_dec_b[2] =  tid0_dup_b[1] & ~tid0_dup_b[0] ;
assign next_tid_dec_b[3] =  tid0_dup_b[1] &  tid0_dup_b[0] ;
assign next_tid_dec_b[4] = ~tid1_dup_b[1] & ~tid1_dup_b[0] ;
assign next_tid_dec_b[5] = ~tid1_dup_b[1] &  tid1_dup_b[0] ;
assign next_tid_dec_b[6] =  tid1_dup_b[1] & ~tid1_dup_b[0] ;
assign next_tid_dec_b[7] =  tid1_dup_b[1] &  tid1_dup_b[0] ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 tid_dec_w_reg  (
 .scan_in(tid_dec_w_reg_scanin),
 .scan_out(tid_dec_w_reg_scanout),
 .l1clk(l1clk),
 .din  (next_tid_dec_b[7:0]),
 .dout (tid_dec_w[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 curr_fetch_thr_c_reg  (
 .scan_in(curr_fetch_thr_c_reg_scanin),
 .scan_out(curr_fetch_thr_c_reg_scanout),
 .l1clk(l1clk),
 .din  (ftp_curr_fetch_thr_f[7:0]),
 .dout (curr_fetch_thr_c[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 cms_curr_fetch_thr_c_reg  (
 .scan_in(cms_curr_fetch_thr_c_reg_scanin),
 .scan_out(cms_curr_fetch_thr_c_reg_scanout),
 .l1clk(l1clk),
 .din  (ftp_curr_fetch_thr_f[7:0]),
 .dout (cms_curr_fetch_thr_c[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);


assign thr0_matches_curr_f = (~tid0_m[1] & ~tid0_m[0] & ftp_curr_fetch_thr_f[0]   ) ;
assign thr1_matches_curr_f = (~tid0_m[1] &  tid0_m[0] & ftp_curr_fetch_thr_f[1]   ) ;
assign thr2_matches_curr_f = ( tid0_m[1] & ~tid0_m[0] & ftp_curr_fetch_thr_f[2]   ) ;
assign thr3_matches_curr_f = ( tid0_m[1] &  tid0_m[0] & ftp_curr_fetch_thr_f[3]   ) ;
assign thr4_matches_curr_f = (~tid1_m[1] & ~tid1_m[0] & ftp_curr_fetch_thr_f[4]   ) ;
assign thr5_matches_curr_f = (~tid1_m[1] &  tid1_m[0] & ftp_curr_fetch_thr_f[5]   ) ;
assign thr6_matches_curr_f = ( tid1_m[1] & ~tid1_m[0] & ftp_curr_fetch_thr_f[6]   ) ;
assign thr7_matches_curr_f = ( tid1_m[1] &  tid1_m[0] & ftp_curr_fetch_thr_f[7]   ) ;

assign thr0_matches_curr_c = (~tid0_m[1] & ~tid0_m[0] & curr_fetch_thr_c[0]   ) ;
assign thr1_matches_curr_c = (~tid0_m[1] &  tid0_m[0] & curr_fetch_thr_c[1]   ) ;
assign thr2_matches_curr_c = ( tid0_m[1] & ~tid0_m[0] & curr_fetch_thr_c[2]   ) ;
assign thr3_matches_curr_c = ( tid0_m[1] &  tid0_m[0] & curr_fetch_thr_c[3]   ) ;
assign thr4_matches_curr_c = (~tid1_m[1] & ~tid1_m[0] & curr_fetch_thr_c[4]   ) ;
assign thr5_matches_curr_c = (~tid1_m[1] &  tid1_m[0] & curr_fetch_thr_c[5]   ) ;
assign thr6_matches_curr_c = ( tid1_m[1] & ~tid1_m[0] & curr_fetch_thr_c[6]   ) ;
assign thr7_matches_curr_c = ( tid1_m[1] &  tid1_m[0] & curr_fetch_thr_c[7]   ) ;


assign thr0_br_misp_f    = ~tid0_dup_m[1] & ~tid0_dup_m[0] & br_taken_dup_ff[0]; 
assign thr1_br_misp_f    = ~tid0_dup_m[1] &  tid0_dup_m[0] & br_taken_dup_ff[0]; 
assign thr2_br_misp_f    =  tid0_dup_m[1] & ~tid0_dup_m[0] & br_taken_dup_ff[0]; 
assign thr3_br_misp_f    =  tid0_dup_m[1] &  tid0_dup_m[0] & br_taken_dup_ff[0]; 

assign thr4_br_misp_f    = ~tid1_dup_m[1] & ~tid1_dup_m[0] & br_taken_dup_ff[1]; 
assign thr5_br_misp_f    = ~tid1_dup_m[1] &  tid1_dup_m[0] & br_taken_dup_ff[1]; 
assign thr6_br_misp_f    =  tid1_dup_m[1] & ~tid1_dup_m[0] & br_taken_dup_ff[1]; 
assign thr7_br_misp_f    =  tid1_dup_m[1] &  tid1_dup_m[0] & br_taken_dup_ff[1]; 


///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// This is the scheme to take out NPCs                               //
// We need to main a signal which tells us to fetch only one         //
// instruction. The source for this signal is the TLU or C stage     //
// incase we have to replay from fetches in C stage.                 //
// There one bit per thread.                                         //
///////////////////////////////////////////////////////////////////////
// Thread 0 single fetch bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr0_sf_valid_bf   = thr0_sf_is_valid_bf | (agc_thr0_reset_sf_c & sf_valid_c) ;
assign reset_thr0_sf_valid_bf = (ftp_fetch_thr_q_f[0] & ~invalidation_req_f) |
                                 (agc_by_pass_sel_f[0]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[0] ;   
assign hold_thr0_sf_valid_bf  = ~set_thr0_sf_valid_bf  & ~reset_thr0_sf_valid_bf ;
assign next_thr0_sf_valid_bf  = (set_thr0_sf_valid_bf ) |  (hold_thr0_sf_valid_bf &  thr0_sf_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 1 single fetch bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr1_sf_valid_bf   = thr1_sf_is_valid_bf | (agc_thr1_reset_sf_c & sf_valid_c) ;
assign reset_thr1_sf_valid_bf = (ftp_fetch_thr_q_f[1]  & ~invalidation_req_f) |
                                 (agc_by_pass_sel_f[1]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[1] ;   
assign hold_thr1_sf_valid_bf  = ~set_thr1_sf_valid_bf  & ~reset_thr1_sf_valid_bf ;
assign next_thr1_sf_valid_bf  = (set_thr1_sf_valid_bf ) |  (hold_thr1_sf_valid_bf &  thr1_sf_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 2 single fetch bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr2_sf_valid_bf   = thr2_sf_is_valid_bf | (agc_thr2_reset_sf_c & sf_valid_c) ;
assign reset_thr2_sf_valid_bf = (ftp_fetch_thr_q_f[2]  & ~invalidation_req_f) |
                                 (agc_by_pass_sel_f[2]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[2] ;   
assign hold_thr2_sf_valid_bf  = ~set_thr2_sf_valid_bf  & ~reset_thr2_sf_valid_bf ;
assign next_thr2_sf_valid_bf  = (set_thr2_sf_valid_bf ) |  (hold_thr2_sf_valid_bf &  thr2_sf_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 3 single fetch bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr3_sf_valid_bf   = thr3_sf_is_valid_bf | (agc_thr3_reset_sf_c & sf_valid_c) ;
assign reset_thr3_sf_valid_bf = (ftp_fetch_thr_q_f[3]  & ~invalidation_req_f) |
                                 (agc_by_pass_sel_f[3]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[3] ;   
assign hold_thr3_sf_valid_bf  = ~set_thr3_sf_valid_bf  & ~reset_thr3_sf_valid_bf ;
assign next_thr3_sf_valid_bf  = (set_thr3_sf_valid_bf ) |  (hold_thr3_sf_valid_bf &  thr3_sf_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 4 single fetch bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr4_sf_valid_bf   = thr4_sf_is_valid_bf | (agc_thr4_reset_sf_c & sf_valid_c) ;
assign reset_thr4_sf_valid_bf = (ftp_fetch_thr_q_f[4]  & ~invalidation_req_f) |
                                 (agc_by_pass_sel_f[4]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[4] ;   
assign hold_thr4_sf_valid_bf  = ~set_thr4_sf_valid_bf  & ~reset_thr4_sf_valid_bf ;
assign next_thr4_sf_valid_bf  = (set_thr4_sf_valid_bf ) |  (hold_thr4_sf_valid_bf &  thr4_sf_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 5 single fetch bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr5_sf_valid_bf   = thr5_sf_is_valid_bf | (agc_thr5_reset_sf_c & sf_valid_c) ;
assign reset_thr5_sf_valid_bf = (ftp_fetch_thr_q_f[5]  & ~invalidation_req_f) |
                                 (agc_by_pass_sel_f[5]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[5] ;   
assign hold_thr5_sf_valid_bf  = ~set_thr5_sf_valid_bf  & ~reset_thr5_sf_valid_bf ;
assign next_thr5_sf_valid_bf  = (set_thr5_sf_valid_bf ) |  (hold_thr5_sf_valid_bf &  thr5_sf_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 6 single fetch bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr6_sf_valid_bf   = thr6_sf_is_valid_bf | (agc_thr6_reset_sf_c & sf_valid_c) ;
assign reset_thr6_sf_valid_bf = (ftp_fetch_thr_q_f[6]  & ~invalidation_req_f) |
                                 (agc_by_pass_sel_f[6]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[6] ;   
assign hold_thr6_sf_valid_bf  = ~set_thr6_sf_valid_bf  & ~reset_thr6_sf_valid_bf ;
assign next_thr6_sf_valid_bf  = (set_thr6_sf_valid_bf ) |  (hold_thr6_sf_valid_bf &  thr6_sf_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 7 single fetch bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr7_sf_valid_bf   = thr7_sf_is_valid_bf | (agc_thr7_reset_sf_c & sf_valid_c) ;
assign reset_thr7_sf_valid_bf = (ftp_fetch_thr_q_f[7]  & ~invalidation_req_f) |
                                 (agc_by_pass_sel_f[7]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[7] ;   
assign hold_thr7_sf_valid_bf  = ~set_thr7_sf_valid_bf  & ~reset_thr7_sf_valid_bf ;
assign next_thr7_sf_valid_bf  = (set_thr7_sf_valid_bf ) |  (hold_thr7_sf_valid_bf &  thr7_sf_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Flop the single fetch bits                                        //
///////////////////////////////////////////////////////////////////////
ifu_ftu_agc_ctl_msff_ctl_macro__width_8 sf_valid_reg  (
 .scan_in(sf_valid_reg_scanin),
 .scan_out(sf_valid_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({next_thr7_sf_valid_bf,next_thr6_sf_valid_bf,next_thr5_sf_valid_bf,
         next_thr4_sf_valid_bf,next_thr3_sf_valid_bf,next_thr2_sf_valid_bf,
         next_thr1_sf_valid_bf,next_thr0_sf_valid_bf}),
 .dout ({thr7_sf_valid_f,thr6_sf_valid_f,thr5_sf_valid_f,thr4_sf_valid_f,
         thr3_sf_valid_f,thr2_sf_valid_f,thr1_sf_valid_f,thr0_sf_valid_f}),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 sf_valid_dup_reg  (
 .scan_in(sf_valid_dup_reg_scanin),
 .scan_out(sf_valid_dup_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({next_thr7_sf_valid_bf,next_thr6_sf_valid_bf,next_thr5_sf_valid_bf,
         next_thr4_sf_valid_bf,next_thr3_sf_valid_bf,next_thr2_sf_valid_bf,
         next_thr1_sf_valid_bf,next_thr0_sf_valid_bf}),
 .dout ({agc_thr7_sf_valid_f,agc_thr6_sf_valid_f,agc_thr5_sf_valid_f,agc_thr4_sf_valid_f,
         agc_thr3_sf_valid_f,agc_thr2_sf_valid_f,agc_thr1_sf_valid_f,agc_thr0_sf_valid_f}),
  .siclk(siclk),
  .soclk(soclk));


////////////////////////////////////////////////////////////////////////////
// single fetch bit with out the by_pass case.                            //
////////////////////////////////////////////////////////////////////////////
assign instr_sf_valid_f   =  (ftp_fetch_thr_q_f[0] & thr0_sf_valid_f) |
                             (ftp_fetch_thr_q_f[1] & thr1_sf_valid_f) |
                             (ftp_fetch_thr_q_f[2] & thr2_sf_valid_f) |
                             (ftp_fetch_thr_q_f[3] & thr3_sf_valid_f) |
                             (ftp_fetch_thr_q_f[4] & thr4_sf_valid_f) |
                             (ftp_fetch_thr_q_f[5] & thr5_sf_valid_f) |
                             (ftp_fetch_thr_q_f[6] & thr6_sf_valid_f) |
                             (ftp_fetch_thr_q_f[7] & thr7_sf_valid_f) ;
 

////////////////////////////////////////////////////////////////////////////
// Note the thrx_sf_valid_f has been set when the miss was detected.      //
////////////////////////////////////////////////////////////////////////////
assign sf_valid_by_pass_bf = (thr0_sf_valid_f & agc_by_pass_sel_bf[0] ) |
                             (thr1_sf_valid_f & agc_by_pass_sel_bf[1] ) |
                             (thr2_sf_valid_f & agc_by_pass_sel_bf[2] ) |
                             (thr3_sf_valid_f & agc_by_pass_sel_bf[3] ) |
                             (thr4_sf_valid_f & agc_by_pass_sel_bf[4] ) |
                             (thr5_sf_valid_f & agc_by_pass_sel_bf[5] ) |
                             (thr6_sf_valid_f & agc_by_pass_sel_bf[6] ) |
                             (thr7_sf_valid_f & agc_by_pass_sel_bf[7] ) ;

 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 sf_valid_by_pass_f_reg  (
  .scan_in(sf_valid_by_pass_f_reg_scanin),
  .scan_out(sf_valid_by_pass_f_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (sf_valid_by_pass_bf),
  .dout (sf_valid_by_pass_f),
  .siclk(siclk),
  .soclk(soclk));
 
 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 sf_valid_by_pass_c_reg  (
  .scan_in(sf_valid_by_pass_c_reg_scanin),
  .scan_out(sf_valid_by_pass_c_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (sf_valid_by_pass_f),
  .dout (sf_valid_by_pass_c),
  .siclk(siclk),
  .soclk(soclk));

 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 sf_v_c  (
  .scan_in(sf_v_c_scanin),
  .scan_out(sf_v_c_scanout),
  .l1clk( l1clk_pm1),
  .din  (instr_sf_valid_f),
  .dout (instr_sf_valid_c),
  .siclk(siclk),
  .soclk(soclk));
assign ftu_instr_sf_valid_c = instr_sf_valid_c ; 

///////////////////////////////////////////////////////////////////////
// Thread 0 uncacheable bit                                          //
///////////////////////////////////////////////////////////////////////
assign set_thr0_unc_valid_bf   = thr0_unc_is_valid  ;
assign reset_thr0_unc_valid_bf = (ftp_fetch_thr_q_f[0] ) |
                                 (agc_by_pass_sel_f[0]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[0] ;   
assign hold_thr0_unc_valid_bf  = ~set_thr0_unc_valid_bf  & ~reset_thr0_unc_valid_bf ;
assign next_thr0_unc_valid_bf  = (set_thr0_unc_valid_bf ) |  (hold_thr0_unc_valid_bf &  thr0_unc_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 1 uncacheable bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr1_unc_valid_bf   = thr1_unc_is_valid  ;
assign reset_thr1_unc_valid_bf = (ftp_fetch_thr_q_f[1] ) |
                                 (agc_by_pass_sel_f[1]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[1] ;   
assign hold_thr1_unc_valid_bf  = ~set_thr1_unc_valid_bf  & ~reset_thr1_unc_valid_bf ;
assign next_thr1_unc_valid_bf  = (set_thr1_unc_valid_bf ) |  (hold_thr1_unc_valid_bf &  thr1_unc_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 2 uncacheable bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr2_unc_valid_bf   = thr2_unc_is_valid  ;
assign reset_thr2_unc_valid_bf = (ftp_fetch_thr_q_f[2] ) |
                                 (agc_by_pass_sel_f[2]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[2] ;   
assign hold_thr2_unc_valid_bf  = ~set_thr2_unc_valid_bf  & ~reset_thr2_unc_valid_bf ;
assign next_thr2_unc_valid_bf  = (set_thr2_unc_valid_bf ) |  (hold_thr2_unc_valid_bf &  thr2_unc_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 3 uncacheable bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr3_unc_valid_bf   = thr3_unc_is_valid  ;
assign reset_thr3_unc_valid_bf = (ftp_fetch_thr_q_f[3] ) |
                                 (agc_by_pass_sel_f[3]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[3] ;   
assign hold_thr3_unc_valid_bf  = ~set_thr3_unc_valid_bf  & ~reset_thr3_unc_valid_bf ;
assign next_thr3_unc_valid_bf  = (set_thr3_unc_valid_bf ) |  (hold_thr3_unc_valid_bf &  thr3_unc_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 4 uncacheable bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr4_unc_valid_bf   = thr4_unc_is_valid  ;
assign reset_thr4_unc_valid_bf = (ftp_fetch_thr_q_f[4] ) |
                                 (agc_by_pass_sel_f[4]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[4] ;   
assign hold_thr4_unc_valid_bf  = ~set_thr4_unc_valid_bf  & ~reset_thr4_unc_valid_bf ;
assign next_thr4_unc_valid_bf  = (set_thr4_unc_valid_bf ) |  (hold_thr4_unc_valid_bf &  thr4_unc_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 5 uncacheable bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr5_unc_valid_bf   = thr5_unc_is_valid  ;
assign reset_thr5_unc_valid_bf = (ftp_fetch_thr_q_f[5] ) |
                                 (agc_by_pass_sel_f[5]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[5] ;   
assign hold_thr5_unc_valid_bf  = ~set_thr5_unc_valid_bf  & ~reset_thr5_unc_valid_bf ;
assign next_thr5_unc_valid_bf  = (set_thr5_unc_valid_bf ) |  (hold_thr5_unc_valid_bf &  thr5_unc_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 6 uncacheable bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr6_unc_valid_bf   = thr6_unc_is_valid  ;
assign reset_thr6_unc_valid_bf = (ftp_fetch_thr_q_f[6] ) |
                                 (agc_by_pass_sel_f[6]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[6] ;   
assign hold_thr6_unc_valid_bf  = ~set_thr6_unc_valid_bf  & ~reset_thr6_unc_valid_bf ;
assign next_thr6_unc_valid_bf  = (set_thr6_unc_valid_bf ) |  (hold_thr6_unc_valid_bf &  thr6_unc_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Thread 7 uncacheable bit                                         //
///////////////////////////////////////////////////////////////////////
assign set_thr7_unc_valid_bf   = thr7_unc_is_valid  ;
assign reset_thr7_unc_valid_bf = (ftp_fetch_thr_q_f[7] ) |
                                 (agc_by_pass_sel_f[7]    &  agc_by_pass_valid_f ) | tlu_flush_ifu_f[7] ;   
assign hold_thr7_unc_valid_bf  = ~set_thr7_unc_valid_bf  & ~reset_thr7_unc_valid_bf ;
assign next_thr7_unc_valid_bf  = (set_thr7_unc_valid_bf ) |  (hold_thr7_unc_valid_bf &  thr7_unc_valid_f) ; 

///////////////////////////////////////////////////////////////////////
// Flop the uncacheable bits                                        //
///////////////////////////////////////////////////////////////////////
ifu_ftu_agc_ctl_msff_ctl_macro__width_8 unc_valid_reg  (
 .scan_in(unc_valid_reg_scanin),
 .scan_out(unc_valid_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({next_thr7_unc_valid_bf,next_thr6_unc_valid_bf,next_thr5_unc_valid_bf,
         next_thr4_unc_valid_bf,next_thr3_unc_valid_bf,next_thr2_unc_valid_bf,
         next_thr1_unc_valid_bf,next_thr0_unc_valid_bf}),
 .dout ({thr7_unc_valid_f,thr6_unc_valid_f,thr5_unc_valid_f,thr4_unc_valid_f,
         thr3_unc_valid_f,thr2_unc_valid_f,thr1_unc_valid_f,thr0_unc_valid_f}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
// thr0 by_pass lower bits incrementining. This is done early and    //
// flopped to fix timing problems.                                   //
///////////////////////////////////////////////////////////////////////

assign thr0_by_pass_pc_incr_bit5 = ( agd_thr0_pc_4_2_f[4] &  agd_thr0_pc_4_2_f[3] &  agd_thr0_pc_4_2_f[2]) | 
                                   (!thr0_unc_valid_f     &  agd_thr0_pc_4_2_f[4]);

assign thr0_by_pass_inc_pc_bf[4] = ( thr0_unc_valid_f      &  agd_thr0_pc_4_2_f[4] & !agd_thr0_pc_4_2_f[2]) | 
                                   ( thr0_unc_valid_f      &  agd_thr0_pc_4_2_f[4] & !agd_thr0_pc_4_2_f[3]) | 
                                   (!thr0_unc_valid_f      & !agd_thr0_pc_4_2_f[4]) | 
                                   (!agd_thr0_pc_4_2_f[4]  &  agd_thr0_pc_4_2_f[3] &  agd_thr0_pc_4_2_f[2]);

assign thr0_by_pass_inc_pc_bf[3] = ( thr0_unc_valid_f      & !agd_thr0_pc_4_2_f[3] &  agd_thr0_pc_4_2_f[2]) | 
                                   (!thr0_unc_valid_f      & !agd_thr0_pc_4_2_f[4] &  agd_thr0_pc_4_2_f[3]) | 
                                   ( thr0_unc_valid_f      &  agd_thr0_pc_4_2_f[3] & !agd_thr0_pc_4_2_f[2]);

assign thr0_by_pass_inc_pc_bf[2] = (!thr0_unc_valid_f      & !agd_thr0_pc_4_2_f[4] &  agd_thr0_pc_4_2_f[2]) | 
                                   ( thr0_unc_valid_f      & !agd_thr0_pc_4_2_f[2]);


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 thr0_pc_f_inc_reg  (
 .scan_in(thr0_pc_f_inc_reg_scanin),
 .scan_out(thr0_pc_f_inc_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ( {thr0_by_pass_inc_pc_bf[4:2], thr0_by_pass_pc_incr_bit5}),
 .dout ( {agc_thr0_byp_pc_update_bf[4:2],agc_thr0_byp_incr_bit5}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
// thr1 by_pass lower bits incrementining. This is done early and    //
// flopped to fix timing problems.                                   //
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
assign thr1_by_pass_pc_incr_bit5 = ( agd_thr1_pc_4_2_f[4] &  agd_thr1_pc_4_2_f[3] &  agd_thr1_pc_4_2_f[2]) | 
                                   (!thr1_unc_valid_f     &  agd_thr1_pc_4_2_f[4]);

assign thr1_by_pass_inc_pc_bf[4] = ( thr1_unc_valid_f      &  agd_thr1_pc_4_2_f[4] & !agd_thr1_pc_4_2_f[2]) | 
                                   ( thr1_unc_valid_f      &  agd_thr1_pc_4_2_f[4] & !agd_thr1_pc_4_2_f[3]) | 
                                   (!thr1_unc_valid_f      & !agd_thr1_pc_4_2_f[4]) | 
                                   (!agd_thr1_pc_4_2_f[4]  &  agd_thr1_pc_4_2_f[3] &  agd_thr1_pc_4_2_f[2]);

assign thr1_by_pass_inc_pc_bf[3] = ( thr1_unc_valid_f      & !agd_thr1_pc_4_2_f[3] &  agd_thr1_pc_4_2_f[2]) | 
                                   (!thr1_unc_valid_f      & !agd_thr1_pc_4_2_f[4] &  agd_thr1_pc_4_2_f[3]) | 
                                   ( thr1_unc_valid_f      &  agd_thr1_pc_4_2_f[3] & !agd_thr1_pc_4_2_f[2]);

assign thr1_by_pass_inc_pc_bf[2] = (!thr1_unc_valid_f      & !agd_thr1_pc_4_2_f[4] &  agd_thr1_pc_4_2_f[2]) | 
                                   ( thr1_unc_valid_f      & !agd_thr1_pc_4_2_f[2]);


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 thr1_pc_f_inc_reg  (
 .scan_in(thr1_pc_f_inc_reg_scanin),
 .scan_out(thr1_pc_f_inc_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ( {thr1_by_pass_inc_pc_bf[4:2], thr1_by_pass_pc_incr_bit5}),
 .dout ( {agc_thr1_byp_pc_update_bf[4:2],agc_thr1_byp_incr_bit5}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
// thr2 by_pass lower bits incrementining. This is done early and    //
// flopped to fix timing problems.                                   //
///////////////////////////////////////////////////////////////////////
assign thr2_by_pass_pc_incr_bit5 = ( agd_thr2_pc_4_2_f[4] &  agd_thr2_pc_4_2_f[3] &  agd_thr2_pc_4_2_f[2]) | 
                                   (!thr2_unc_valid_f     &  agd_thr2_pc_4_2_f[4]);

assign thr2_by_pass_inc_pc_bf[4] = ( thr2_unc_valid_f      &  agd_thr2_pc_4_2_f[4] & !agd_thr2_pc_4_2_f[2]) | 
                                   ( thr2_unc_valid_f      &  agd_thr2_pc_4_2_f[4] & !agd_thr2_pc_4_2_f[3]) | 
                                   (!thr2_unc_valid_f      & !agd_thr2_pc_4_2_f[4]) | 
                                   (!agd_thr2_pc_4_2_f[4]  &  agd_thr2_pc_4_2_f[3] &  agd_thr2_pc_4_2_f[2]);

assign thr2_by_pass_inc_pc_bf[3] = ( thr2_unc_valid_f      & !agd_thr2_pc_4_2_f[3] &  agd_thr2_pc_4_2_f[2]) | 
                                   (!thr2_unc_valid_f      & !agd_thr2_pc_4_2_f[4] &  agd_thr2_pc_4_2_f[3]) | 
                                   ( thr2_unc_valid_f      &  agd_thr2_pc_4_2_f[3] & !agd_thr2_pc_4_2_f[2]);

assign thr2_by_pass_inc_pc_bf[2] = (!thr2_unc_valid_f      & !agd_thr2_pc_4_2_f[4] &  agd_thr2_pc_4_2_f[2]) | 
                                   ( thr2_unc_valid_f      & !agd_thr2_pc_4_2_f[2]);


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 thr2_pc_f_inc_reg  (
 .scan_in(thr2_pc_f_inc_reg_scanin),
 .scan_out(thr2_pc_f_inc_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ( {thr2_by_pass_inc_pc_bf[4:2], thr2_by_pass_pc_incr_bit5}),
 .dout ( {agc_thr2_byp_pc_update_bf[4:2],agc_thr2_byp_incr_bit5}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
// thr3 by_pass lower bits incrementining. This is done early and    //
// flopped to fix timing problems.                                   //
///////////////////////////////////////////////////////////////////////
assign thr3_by_pass_pc_incr_bit5 = ( agd_thr3_pc_4_2_f[4] &  agd_thr3_pc_4_2_f[3] &  agd_thr3_pc_4_2_f[2]) | 
                                   (!thr3_unc_valid_f     &  agd_thr3_pc_4_2_f[4]);

assign thr3_by_pass_inc_pc_bf[4] = ( thr3_unc_valid_f      &  agd_thr3_pc_4_2_f[4] & !agd_thr3_pc_4_2_f[2]) | 
                                   ( thr3_unc_valid_f      &  agd_thr3_pc_4_2_f[4] & !agd_thr3_pc_4_2_f[3]) | 
                                   (!thr3_unc_valid_f      & !agd_thr3_pc_4_2_f[4]) | 
                                   (!agd_thr3_pc_4_2_f[4]  &  agd_thr3_pc_4_2_f[3] &  agd_thr3_pc_4_2_f[2]);

assign thr3_by_pass_inc_pc_bf[3] = ( thr3_unc_valid_f      & !agd_thr3_pc_4_2_f[3] &  agd_thr3_pc_4_2_f[2]) | 
                                   (!thr3_unc_valid_f      & !agd_thr3_pc_4_2_f[4] &  agd_thr3_pc_4_2_f[3]) | 
                                   ( thr3_unc_valid_f      &  agd_thr3_pc_4_2_f[3] & !agd_thr3_pc_4_2_f[2]);

assign thr3_by_pass_inc_pc_bf[2] = (!thr3_unc_valid_f      & !agd_thr3_pc_4_2_f[4] &  agd_thr3_pc_4_2_f[2]) | 
                                   ( thr3_unc_valid_f      & !agd_thr3_pc_4_2_f[2]);


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 thr3_pc_f_inc_reg  (
 .scan_in(thr3_pc_f_inc_reg_scanin),
 .scan_out(thr3_pc_f_inc_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ( {thr3_by_pass_inc_pc_bf[4:2], thr3_by_pass_pc_incr_bit5}),
 .dout ( {agc_thr3_byp_pc_update_bf[4:2],agc_thr3_byp_incr_bit5}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
// thr4 by_pass lower bits incrementining. This is done early and    //
// flopped to fix timing problems.                                   //
///////////////////////////////////////////////////////////////////////
assign thr4_by_pass_pc_incr_bit5 = ( agd_thr4_pc_4_2_f[4] &  agd_thr4_pc_4_2_f[3] &  agd_thr4_pc_4_2_f[2]) | 
                                   (!thr4_unc_valid_f     &  agd_thr4_pc_4_2_f[4]);

assign thr4_by_pass_inc_pc_bf[4] = ( thr4_unc_valid_f      &  agd_thr4_pc_4_2_f[4] & !agd_thr4_pc_4_2_f[2]) | 
                                   ( thr4_unc_valid_f      &  agd_thr4_pc_4_2_f[4] & !agd_thr4_pc_4_2_f[3]) | 
                                   (!thr4_unc_valid_f      & !agd_thr4_pc_4_2_f[4]) | 
                                   (!agd_thr4_pc_4_2_f[4]  &  agd_thr4_pc_4_2_f[3] &  agd_thr4_pc_4_2_f[2]);

assign thr4_by_pass_inc_pc_bf[3] = ( thr4_unc_valid_f      & !agd_thr4_pc_4_2_f[3] &  agd_thr4_pc_4_2_f[2]) | 
                                   (!thr4_unc_valid_f      & !agd_thr4_pc_4_2_f[4] &  agd_thr4_pc_4_2_f[3]) | 
                                   ( thr4_unc_valid_f      &  agd_thr4_pc_4_2_f[3] & !agd_thr4_pc_4_2_f[2]);

assign thr4_by_pass_inc_pc_bf[2] = (!thr4_unc_valid_f      & !agd_thr4_pc_4_2_f[4] &  agd_thr4_pc_4_2_f[2]) | 
                                   ( thr4_unc_valid_f      & !agd_thr4_pc_4_2_f[2]);


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 thr4_pc_f_inc_reg  (
 .scan_in(thr4_pc_f_inc_reg_scanin),
 .scan_out(thr4_pc_f_inc_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ( {thr4_by_pass_inc_pc_bf[4:2], thr4_by_pass_pc_incr_bit5}),
 .dout ( {agc_thr4_byp_pc_update_bf[4:2],agc_thr4_byp_incr_bit5}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
// thr5 by_pass lower bits incrementining. This is done early and    //
// flopped to fix timing problems.                                   //
///////////////////////////////////////////////////////////////////////
assign thr5_by_pass_pc_incr_bit5 = ( agd_thr5_pc_4_2_f[4] &  agd_thr5_pc_4_2_f[3] &  agd_thr5_pc_4_2_f[2]) | 
                                   (!thr5_unc_valid_f     &  agd_thr5_pc_4_2_f[4]);

assign thr5_by_pass_inc_pc_bf[4] = ( thr5_unc_valid_f      &  agd_thr5_pc_4_2_f[4] & !agd_thr5_pc_4_2_f[2]) | 
                                   ( thr5_unc_valid_f      &  agd_thr5_pc_4_2_f[4] & !agd_thr5_pc_4_2_f[3]) | 
                                   (!thr5_unc_valid_f      & !agd_thr5_pc_4_2_f[4]) | 
                                   (!agd_thr5_pc_4_2_f[4]  &  agd_thr5_pc_4_2_f[3] &  agd_thr5_pc_4_2_f[2]);

assign thr5_by_pass_inc_pc_bf[3] = ( thr5_unc_valid_f      & !agd_thr5_pc_4_2_f[3] &  agd_thr5_pc_4_2_f[2]) | 
                                   (!thr5_unc_valid_f      & !agd_thr5_pc_4_2_f[4] &  agd_thr5_pc_4_2_f[3]) | 
                                   ( thr5_unc_valid_f      &  agd_thr5_pc_4_2_f[3] & !agd_thr5_pc_4_2_f[2]);

assign thr5_by_pass_inc_pc_bf[2] = (!thr5_unc_valid_f      & !agd_thr5_pc_4_2_f[4] &  agd_thr5_pc_4_2_f[2]) | 
                                   ( thr5_unc_valid_f      & !agd_thr5_pc_4_2_f[2]);


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 thr5_pc_f_inc_reg  (
 .scan_in(thr5_pc_f_inc_reg_scanin),
 .scan_out(thr5_pc_f_inc_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ( {thr5_by_pass_inc_pc_bf[4:2], thr5_by_pass_pc_incr_bit5}),
 .dout ( {agc_thr5_byp_pc_update_bf[4:2],agc_thr5_byp_incr_bit5}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
// thr6 by_pass lower bits incrementining. This is done early and    //
// flopped to fix timing problems.                                   //
///////////////////////////////////////////////////////////////////////
assign thr6_by_pass_pc_incr_bit5 = ( agd_thr6_pc_4_2_f[4] &  agd_thr6_pc_4_2_f[3] &  agd_thr6_pc_4_2_f[2]) | 
                                   (!thr6_unc_valid_f     &  agd_thr6_pc_4_2_f[4]);

assign thr6_by_pass_inc_pc_bf[4] = ( thr6_unc_valid_f      &  agd_thr6_pc_4_2_f[4] & !agd_thr6_pc_4_2_f[2]) | 
                                   ( thr6_unc_valid_f      &  agd_thr6_pc_4_2_f[4] & !agd_thr6_pc_4_2_f[3]) | 
                                   (!thr6_unc_valid_f      & !agd_thr6_pc_4_2_f[4]) | 
                                   (!agd_thr6_pc_4_2_f[4]  &  agd_thr6_pc_4_2_f[3] &  agd_thr6_pc_4_2_f[2]);

assign thr6_by_pass_inc_pc_bf[3] = ( thr6_unc_valid_f      & !agd_thr6_pc_4_2_f[3] &  agd_thr6_pc_4_2_f[2]) | 
                                   (!thr6_unc_valid_f      & !agd_thr6_pc_4_2_f[4] &  agd_thr6_pc_4_2_f[3]) | 
                                   ( thr6_unc_valid_f      &  agd_thr6_pc_4_2_f[3] & !agd_thr6_pc_4_2_f[2]);

assign thr6_by_pass_inc_pc_bf[2] = (!thr6_unc_valid_f      & !agd_thr6_pc_4_2_f[4] &  agd_thr6_pc_4_2_f[2]) | 
                                   ( thr6_unc_valid_f      & !agd_thr6_pc_4_2_f[2]);


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 thr6_pc_f_inc_reg  (
 .scan_in(thr6_pc_f_inc_reg_scanin),
 .scan_out(thr6_pc_f_inc_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ( {thr6_by_pass_inc_pc_bf[4:2], thr6_by_pass_pc_incr_bit5}),
 .dout ( {agc_thr6_byp_pc_update_bf[4:2],agc_thr6_byp_incr_bit5}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
// thr7 by_pass lower bits incrementining. This is done early and    //
// flopped to fix timing problems.                                   //
///////////////////////////////////////////////////////////////////////
assign thr7_by_pass_pc_incr_bit5 = ( agd_thr7_pc_4_2_f[4] &  agd_thr7_pc_4_2_f[3] &  agd_thr7_pc_4_2_f[2]) | 
                                   (!thr7_unc_valid_f     &  agd_thr7_pc_4_2_f[4]);

assign thr7_by_pass_inc_pc_bf[4] = ( thr7_unc_valid_f      &  agd_thr7_pc_4_2_f[4] & !agd_thr7_pc_4_2_f[2]) | 
                                   ( thr7_unc_valid_f      &  agd_thr7_pc_4_2_f[4] & !agd_thr7_pc_4_2_f[3]) | 
                                   (!thr7_unc_valid_f      & !agd_thr7_pc_4_2_f[4]) | 
                                   (!agd_thr7_pc_4_2_f[4]  &  agd_thr7_pc_4_2_f[3] &  agd_thr7_pc_4_2_f[2]);

assign thr7_by_pass_inc_pc_bf[3] = ( thr7_unc_valid_f      & !agd_thr7_pc_4_2_f[3] &  agd_thr7_pc_4_2_f[2]) | 
                                   (!thr7_unc_valid_f      & !agd_thr7_pc_4_2_f[4] &  agd_thr7_pc_4_2_f[3]) | 
                                   ( thr7_unc_valid_f      &  agd_thr7_pc_4_2_f[3] & !agd_thr7_pc_4_2_f[2]);

assign thr7_by_pass_inc_pc_bf[2] = (!thr7_unc_valid_f      & !agd_thr7_pc_4_2_f[4] &  agd_thr7_pc_4_2_f[2]) | 
                                   ( thr7_unc_valid_f      & !agd_thr7_pc_4_2_f[2]);


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 thr7_pc_f_inc_reg  (
 .scan_in(thr7_pc_f_inc_reg_scanin),
 .scan_out(thr7_pc_f_inc_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ( {thr7_by_pass_inc_pc_bf[4:2], thr7_by_pass_pc_incr_bit5}),
 .dout ( {agc_thr7_byp_pc_update_bf[4:2],agc_thr7_byp_incr_bit5}),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////

assign last_fetch_was_thr0_bf = ftp_fetch_thr_q_f[0] & ~agc_by_pass_valid_f;
assign last_fetch_was_thr1_bf = ftp_fetch_thr_q_f[1] & ~agc_by_pass_valid_f;
assign last_fetch_was_thr2_bf = ftp_fetch_thr_q_f[2] & ~agc_by_pass_valid_f;
assign last_fetch_was_thr3_bf = ftp_fetch_thr_q_f[3] & ~agc_by_pass_valid_f;
assign last_fetch_was_thr4_bf = ftp_fetch_thr_q_f[4] & ~agc_by_pass_valid_f;
assign last_fetch_was_thr5_bf = ftp_fetch_thr_q_f[5] & ~agc_by_pass_valid_f;
assign last_fetch_was_thr6_bf = ftp_fetch_thr_q_f[6] & ~agc_by_pass_valid_f;
assign last_fetch_was_thr7_bf = ftp_fetch_thr_q_f[7] & ~agc_by_pass_valid_f;

///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 tlu_flush_ifu_reg  (
 .scan_in(tlu_flush_ifu_reg_scanin),
 .scan_out(tlu_flush_ifu_reg_scanout),
 .l1clk( l1clk),
 .din  (tlu_flush_ifu[7:0]),
 .dout (tlu_flush_ifu_f[7:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_16 tlu_flush_ifu_d_reg  (
 .scan_in(tlu_flush_ifu_d_reg_scanin),
 .scan_out(tlu_flush_ifu_d_reg_scanout),
 .l1clk( l1clk),
 .din  ({tlu_flush_ifu_f[7:0],tlu_flush_ifu_f_d[7:0]}),
 .dout ({tlu_flush_ifu_f_d[7:0],tlu_flush_ifu_f_dd[7:0]}),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 cms_tlu_flush_ifu_reg  (
 .scan_in(cms_tlu_flush_ifu_reg_scanin),
 .scan_out(cms_tlu_flush_ifu_reg_scanout),
 .l1clk( l1clk),
 .din  (tlu_flush_ifu[7:0]),
 .dout (cms_tlu_flush_f[7:0]),
  .siclk(siclk),
  .soclk(soclk));


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 load_flush_reg  (
 .scan_in(load_flush_reg_scanin),
 .scan_out(load_flush_reg_scanout),
 .l1clk( l1clk_pm1),
 .din  (load_flush_w[7:0]),
 .dout (load_flush_f[7:0]),
  .siclk(siclk),
  .soclk(soclk));


assign agc_kill_fetch_cv_f =  (((ftu_thr0_redirect_int_bf | agc_thr0_micro_flush_unq_c |  tlu_flush_ifu_f[0] | load_flush_f[0] |
                                 tlu_flush_ifu_f_d[0] | tlu_flush_ifu_f_dd[0] | thr0_sf_kill | 
                                 thr0_sf_kill_d | thr0_br_misp_no_match_f | thr0_kill_after_invalidation |
                                 thr0_kill_after_invalidation_d | thr0_exception_valid_kill_c2) & ftp_curr_fetch_thr_f[0])| 
                                ((ftu_thr1_redirect_int_bf | agc_thr1_micro_flush_unq_c | tlu_flush_ifu_f[1] | load_flush_f[1] | 
                                 tlu_flush_ifu_f_d[1] | tlu_flush_ifu_f_dd[1] | thr1_sf_kill | 
                                 thr1_sf_kill_d | thr1_br_misp_no_match_f | thr1_kill_after_invalidation |
                                 thr1_kill_after_invalidation_d | thr1_exception_valid_kill_c2) & ftp_curr_fetch_thr_f[1])| 
                                ((ftu_thr2_redirect_int_bf | agc_thr2_micro_flush_unq_c | tlu_flush_ifu_f[2] | load_flush_f[2] | 
                                 tlu_flush_ifu_f_d[2] | tlu_flush_ifu_f_dd[2] | thr2_sf_kill | 
                                 thr2_sf_kill_d | thr2_br_misp_no_match_f | thr2_kill_after_invalidation |
                                 thr2_kill_after_invalidation_d | thr2_exception_valid_kill_c2) & ftp_curr_fetch_thr_f[2])| 
                                ((ftu_thr3_redirect_int_bf | agc_thr3_micro_flush_unq_c | tlu_flush_ifu_f[3] | load_flush_f[3] | 
                                 tlu_flush_ifu_f_d[3] | tlu_flush_ifu_f_dd[3] | thr3_sf_kill | 
                                 thr3_sf_kill_d | thr3_br_misp_no_match_f | thr3_kill_after_invalidation |
                                 thr3_kill_after_invalidation_d | thr3_exception_valid_kill_c2) & ftp_curr_fetch_thr_f[3])| 
                                ((ftu_thr4_redirect_int_bf | agc_thr4_micro_flush_unq_c | tlu_flush_ifu_f[4] | load_flush_f[4] | 
                                 tlu_flush_ifu_f_d[4] | tlu_flush_ifu_f_dd[4] | thr4_sf_kill | 
                                 thr4_sf_kill_d | thr4_br_misp_no_match_f | thr4_kill_after_invalidation |
                                 thr4_kill_after_invalidation_d | thr4_exception_valid_kill_c2) & ftp_curr_fetch_thr_f[4])| 
                                ((ftu_thr5_redirect_int_bf | agc_thr5_micro_flush_unq_c | tlu_flush_ifu_f[5] | load_flush_f[5] | 
                                 tlu_flush_ifu_f_d[5] | tlu_flush_ifu_f_dd[5] | thr5_sf_kill | 
                                 thr5_sf_kill_d | thr5_br_misp_no_match_f | thr5_kill_after_invalidation |
                                 thr5_kill_after_invalidation_d | thr5_exception_valid_kill_c2) & ftp_curr_fetch_thr_f[5])| 
                                ((ftu_thr6_redirect_int_bf | agc_thr6_micro_flush_unq_c | tlu_flush_ifu_f[6] | load_flush_f[6] | 
                                 tlu_flush_ifu_f_d[6] | tlu_flush_ifu_f_dd[6] | thr6_sf_kill | 
                                 thr6_sf_kill_d | thr6_br_misp_no_match_f | thr6_kill_after_invalidation |
                                 thr6_kill_after_invalidation_d | thr6_exception_valid_kill_c2) & ftp_curr_fetch_thr_f[6])| 
                                ((ftu_thr7_redirect_int_bf | agc_thr7_micro_flush_unq_c | tlu_flush_ifu_f[7] | load_flush_f[7] | 
                                 tlu_flush_ifu_f_d[7] | tlu_flush_ifu_f_dd[7] | thr7_sf_kill | 
                                 thr7_sf_kill_d | thr7_br_misp_no_match_f | thr7_kill_after_invalidation |
                                 thr7_kill_after_invalidation_d | thr7_exception_valid_kill_c2) & ftp_curr_fetch_thr_f[7])) ;
                            

assign next_br_misp_match = (br_taken_ff[0] & ~tid0_m[1] & ~tid0_m[0] & thr0_matches_curr_c) |
                            (br_taken_ff[0] & ~tid0_m[1] &  tid0_m[0] & thr1_matches_curr_c) |
                            (br_taken_ff[0] &  tid0_m[1] & ~tid0_m[0] & thr2_matches_curr_c) |
                            (br_taken_ff[0] &  tid0_m[1] &  tid0_m[0] & thr3_matches_curr_c) |
                            (br_taken_ff[1] & ~tid1_m[1] & ~tid1_m[0] & thr4_matches_curr_c) |
                            (br_taken_ff[1] & ~tid1_m[1] &  tid1_m[0] & thr5_matches_curr_c) |
                            (br_taken_ff[1] &  tid1_m[1] & ~tid1_m[0] & thr6_matches_curr_c) |
                            (br_taken_ff[1] &  tid1_m[1] &  tid1_m[0] & thr7_matches_curr_c) ;
  
assign next_br_misp_match_int = (br_taken_ff[0] & ~tid0_m[1] & ~tid0_m[0] & thr0_matches_curr_c) |
                                (br_taken_ff[0] & ~tid0_m[1] &  tid0_m[0] & thr1_matches_curr_c) |
                                (br_taken_ff[0] &  tid0_m[1] & ~tid0_m[0] & thr2_matches_curr_c) |
                                (br_taken_ff[0] &  tid0_m[1] &  tid0_m[0] & thr3_matches_curr_c) |
                                (br_taken_ff[1] & ~tid1_m[1] & ~tid1_m[0] & thr4_matches_curr_c) |
                                (br_taken_ff[1] & ~tid1_m[1] &  tid1_m[0] & thr5_matches_curr_c) |
                                (br_taken_ff[1] &  tid1_m[1] & ~tid1_m[0] & thr6_matches_curr_c) |
                                (br_taken_ff[1] &  tid1_m[1] &  tid1_m[0] & thr7_matches_curr_c) ;
  

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 kill_fetch_vc_reg  (
 .scan_in(kill_fetch_vc_reg_scanin),
 .scan_out(kill_fetch_vc_reg_scanout),
 .l1clk( l1clk_pm1),
 .din  (agc_kill_fetch_cv_f),
 .dout (kill_fetch_cv_c_unq),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 kill_fetch_vc_2_reg  (
 .scan_in(kill_fetch_vc_2_reg_scanin),
 .scan_out(kill_fetch_vc_2_reg_scanout),
 .l1clk( l1clk_pm1),
 .din  (agc_kill_fetch_cv_f),
 .dout (kill_fetch_cv_c_unq2),
  .siclk(siclk),
  .soclk(soclk));

assign exception_valid_kill_in = exception_valid_c & (curr_fetch_thr_c[7:0] == ftp_curr_fetch_thr_f[7:0]) ; 
ifu_ftu_agc_ctl_msff_ctl_macro__width_1 exception_valid_kill_reg  (
 .scan_in(exception_valid_kill_reg_scanin),
 .scan_out(exception_valid_kill_reg_scanout),
 .l1clk( l1clk_pm1),
 .din  (exception_valid_kill_in),
 .dout (exception_valid_kill_c),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 exception_valid_kill1_reg  (
 .scan_in(exception_valid_kill1_reg_scanin),
 .scan_out(exception_valid_kill1_reg_scanout),
 .l1clk( l1clk_pm1),
 .din  (exception_valid_kill_in),
 .dout (exception_valid_kill_int_c),
  .siclk(siclk),
  .soclk(soclk));

assign agc_kill_fetch_cv_c = kill_fetch_cv_c_unq | next_br_misp_match | exception_valid_kill_c;
assign agc_kill_fetch_cv_int1_c = kill_fetch_cv_c_unq2 | next_br_misp_match_int | exception_valid_kill_int_c;
assign agc_kill_fetch_cv_int2_c = kill_fetch_cv_c_unq2 | next_br_misp_match_int | exception_valid_kill_int_c;


assign thr0_exception_valid_kill_in = exception_valid_c & curr_fetch_thr_c[0] & ~ftu_ibu_redirect_bf[0];
assign thr1_exception_valid_kill_in = exception_valid_c & curr_fetch_thr_c[1] & ~ftu_ibu_redirect_bf[1];
assign thr2_exception_valid_kill_in = exception_valid_c & curr_fetch_thr_c[2] & ~ftu_ibu_redirect_bf[2];
assign thr3_exception_valid_kill_in = exception_valid_c & curr_fetch_thr_c[3] & ~ftu_ibu_redirect_bf[3];
assign thr4_exception_valid_kill_in = exception_valid_c & curr_fetch_thr_c[4] & ~ftu_ibu_redirect_bf[4];
assign thr5_exception_valid_kill_in = exception_valid_c & curr_fetch_thr_c[5] & ~ftu_ibu_redirect_bf[5];
assign thr6_exception_valid_kill_in = exception_valid_c & curr_fetch_thr_c[6] & ~ftu_ibu_redirect_bf[6];
assign thr7_exception_valid_kill_in = exception_valid_c & curr_fetch_thr_c[7] & ~ftu_ibu_redirect_bf[7];

ifu_ftu_agc_ctl_msff_ctl_macro__width_16 thrx_exception_valid_kill_reg  (
 .scan_in(thrx_exception_valid_kill_reg_scanin),
 .scan_out(thrx_exception_valid_kill_reg_scanout),
 .l1clk( l1clk_pm1),
 .din  ({thr7_exception_valid_kill_in,thr6_exception_valid_kill_in,
         thr5_exception_valid_kill_in,thr4_exception_valid_kill_in,
         thr3_exception_valid_kill_in,thr2_exception_valid_kill_in,
         thr1_exception_valid_kill_in,thr0_exception_valid_kill_in,
         thr7_exception_valid_kill_c2_in, thr6_exception_valid_kill_c2_in, 
         thr5_exception_valid_kill_c2_in, thr4_exception_valid_kill_c2_in, 
         thr3_exception_valid_kill_c2_in, thr2_exception_valid_kill_c2_in, 
         thr1_exception_valid_kill_c2_in, thr0_exception_valid_kill_c2_in  
        }),
 .dout ({thr7_exception_valid_kill_c,thr6_exception_valid_kill_c,
         thr5_exception_valid_kill_c,thr4_exception_valid_kill_c,
         thr3_exception_valid_kill_c,thr2_exception_valid_kill_c,
         thr1_exception_valid_kill_c,thr0_exception_valid_kill_c, 
         thr7_exception_valid_kill_c2,thr6_exception_valid_kill_c2,
         thr5_exception_valid_kill_c2,thr4_exception_valid_kill_c2,
         thr3_exception_valid_kill_c2,thr2_exception_valid_kill_c2,
         thr1_exception_valid_kill_c2,thr0_exception_valid_kill_c2 
        }),
  .siclk(siclk),
  .soclk(soclk));

assign thr0_exception_valid_kill_c2_in = exception_valid_c & curr_fetch_thr_c[0] & ~ftu_thr0_redirect_bf;
assign thr1_exception_valid_kill_c2_in = exception_valid_c & curr_fetch_thr_c[1] & ~ftu_thr1_redirect_bf;
assign thr2_exception_valid_kill_c2_in = exception_valid_c & curr_fetch_thr_c[2] & ~ftu_thr2_redirect_bf;
assign thr3_exception_valid_kill_c2_in = exception_valid_c & curr_fetch_thr_c[3] & ~ftu_thr3_redirect_bf;
assign thr4_exception_valid_kill_c2_in = exception_valid_c & curr_fetch_thr_c[4] & ~ftu_thr4_redirect_bf;
assign thr5_exception_valid_kill_c2_in = exception_valid_c & curr_fetch_thr_c[5] & ~ftu_thr5_redirect_bf;
assign thr6_exception_valid_kill_c2_in = exception_valid_c & curr_fetch_thr_c[6] & ~ftu_thr6_redirect_bf;
assign thr7_exception_valid_kill_c2_in = exception_valid_c & curr_fetch_thr_c[7] & ~ftu_thr7_redirect_bf;

//////////////////////////////////////////////////////////////////////////////


assign ftu_thr0_redirect_int_bf = thr0_trap_pcaddr_is_valid_bf |  thr0_lsu_sync_bf ; 
assign ftu_thr1_redirect_int_bf = thr1_trap_pcaddr_is_valid_bf |  thr1_lsu_sync_bf ; 
assign ftu_thr2_redirect_int_bf = thr2_trap_pcaddr_is_valid_bf |  thr2_lsu_sync_bf ; 
assign ftu_thr3_redirect_int_bf = thr3_trap_pcaddr_is_valid_bf |  thr3_lsu_sync_bf ; 
assign ftu_thr4_redirect_int_bf = thr4_trap_pcaddr_is_valid_bf |  thr4_lsu_sync_bf ; 
assign ftu_thr5_redirect_int_bf = thr5_trap_pcaddr_is_valid_bf |  thr5_lsu_sync_bf ; 
assign ftu_thr6_redirect_int_bf = thr6_trap_pcaddr_is_valid_bf |  thr6_lsu_sync_bf ; 
assign ftu_thr7_redirect_int_bf = thr7_trap_pcaddr_is_valid_bf |  thr7_lsu_sync_bf ; 

assign agc_thr0_tlu_redirect_bf =  thr0_trap_pcaddr_is_valid_bf ;  
assign agc_thr1_tlu_redirect_bf =  thr1_trap_pcaddr_is_valid_bf ;  
assign agc_thr2_tlu_redirect_bf =  thr2_trap_pcaddr_is_valid_bf ;  
assign agc_thr3_tlu_redirect_bf =  thr3_trap_pcaddr_is_valid_bf ;  
assign agc_thr4_tlu_redirect_bf =  thr4_trap_pcaddr_is_valid_bf ;  
assign agc_thr5_tlu_redirect_bf =  thr5_trap_pcaddr_is_valid_bf ;  
assign agc_thr6_tlu_redirect_bf =  thr6_trap_pcaddr_is_valid_bf ;  
assign agc_thr7_tlu_redirect_bf =  thr7_trap_pcaddr_is_valid_bf ;  


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 thrx_redirect_reg  (
 .scan_in(thrx_redirect_reg_scanin),
 .scan_out(thrx_redirect_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({ftu_thr7_redirect_int_bf,ftu_thr6_redirect_int_bf,ftu_thr5_redirect_int_bf,ftu_thr4_redirect_int_bf,
         ftu_thr3_redirect_int_bf,ftu_thr2_redirect_int_bf,ftu_thr1_redirect_int_bf,ftu_thr0_redirect_int_bf}),
 .dout ({ftu_thr7_redirect_part_bf,ftu_thr6_redirect_part_bf,ftu_thr5_redirect_part_bf,ftu_thr4_redirect_part_bf,
         ftu_thr3_redirect_part_bf,ftu_thr2_redirect_part_bf,ftu_thr1_redirect_part_bf,ftu_thr0_redirect_part_bf}),
  .siclk(siclk),
  .soclk(soclk));

assign ftu_thr0_redirect_bf = ftu_thr0_redirect_part_bf | tlu_flush_ifu_f[0] | thr0_br_misp_f ;
assign ftu_thr1_redirect_bf = ftu_thr1_redirect_part_bf | tlu_flush_ifu_f[1] | thr1_br_misp_f ;
assign ftu_thr2_redirect_bf = ftu_thr2_redirect_part_bf | tlu_flush_ifu_f[2] | thr2_br_misp_f ;
assign ftu_thr3_redirect_bf = ftu_thr3_redirect_part_bf | tlu_flush_ifu_f[3] | thr3_br_misp_f ;
assign ftu_thr4_redirect_bf = ftu_thr4_redirect_part_bf | tlu_flush_ifu_f[4] | thr4_br_misp_f ;
assign ftu_thr5_redirect_bf = ftu_thr5_redirect_part_bf | tlu_flush_ifu_f[5] | thr5_br_misp_f ;
assign ftu_thr6_redirect_bf = ftu_thr6_redirect_part_bf | tlu_flush_ifu_f[6] | thr6_br_misp_f ;
assign ftu_thr7_redirect_bf = ftu_thr7_redirect_part_bf | tlu_flush_ifu_f[7] | thr7_br_misp_f ;


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 thrx_ibu_redirect_reg  (
 .scan_in(thrx_ibu_redirect_reg_scanin),
 .scan_out(thrx_ibu_redirect_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({ftu_thr7_redirect_int_bf,ftu_thr6_redirect_int_bf,ftu_thr5_redirect_int_bf,ftu_thr4_redirect_int_bf,
         ftu_thr3_redirect_int_bf,ftu_thr2_redirect_int_bf,ftu_thr1_redirect_int_bf,ftu_thr0_redirect_int_bf}),
 .dout ( to_ibu_redirect_part_bf[7:0]),
  .siclk(siclk),
  .soclk(soclk));


assign thr0_br_misp_no_match_f = (thr0_br_misp_f & ~(thr0_matches_curr_f & ftp_fetch_v_f & single_thread_active));
assign thr1_br_misp_no_match_f = (thr1_br_misp_f & ~(thr1_matches_curr_f & ftp_fetch_v_f & single_thread_active));
assign thr2_br_misp_no_match_f = (thr2_br_misp_f & ~(thr2_matches_curr_f & ftp_fetch_v_f & single_thread_active));
assign thr3_br_misp_no_match_f = (thr3_br_misp_f & ~(thr3_matches_curr_f & ftp_fetch_v_f & single_thread_active));
assign thr4_br_misp_no_match_f = (thr4_br_misp_f & ~(thr4_matches_curr_f & ftp_fetch_v_f & single_thread_active));
assign thr5_br_misp_no_match_f = (thr5_br_misp_f & ~(thr5_matches_curr_f & ftp_fetch_v_f & single_thread_active));
assign thr6_br_misp_no_match_f = (thr6_br_misp_f & ~(thr6_matches_curr_f & ftp_fetch_v_f & single_thread_active));
assign thr7_br_misp_no_match_f = (thr7_br_misp_f & ~(thr7_matches_curr_f & ftp_fetch_v_f & single_thread_active));

assign other_flushes_in[0] =  agc_thr0_micro_flush_unq_c | load_flush_f[0]  | thr0_sf_kill | 
                              thr0_sf_kill_d | tlu_flush_ifu_f[0] | tlu_flush_ifu_f_d[0] | tlu_flush_ifu_f_dd[0] | 
                              thr0_br_misp_no_match_f | 
                              thr0_kill_after_invalidation | thr0_kill_after_invalidation_d |
                              thr0_exception_valid_kill_c;
assign other_flushes_in[1] =  agc_thr1_micro_flush_unq_c | load_flush_f[1]  | thr1_sf_kill | 
                              thr1_sf_kill_d | tlu_flush_ifu_f[1] | tlu_flush_ifu_f_d[1] | tlu_flush_ifu_f_dd[1] | 
                              thr1_br_misp_no_match_f |
                              thr1_kill_after_invalidation | thr1_kill_after_invalidation_d  |
                              thr1_exception_valid_kill_c;
assign other_flushes_in[2] =  agc_thr2_micro_flush_unq_c | load_flush_f[2]  | thr2_sf_kill | 
                              thr2_sf_kill_d | tlu_flush_ifu_f[2] | tlu_flush_ifu_f_d[2] | tlu_flush_ifu_f_dd[2] | 
                              thr2_br_misp_no_match_f|
                              thr2_kill_after_invalidation | thr2_kill_after_invalidation_d  |
                              thr2_exception_valid_kill_c ;
assign other_flushes_in[3] =  agc_thr3_micro_flush_unq_c | load_flush_f[3]  | thr3_sf_kill | 
                              thr3_sf_kill_d | tlu_flush_ifu_f[3] | tlu_flush_ifu_f_d[3] | tlu_flush_ifu_f_dd[3] | 
                              thr3_br_misp_no_match_f|
                              thr3_kill_after_invalidation | thr3_kill_after_invalidation_d  |
                              thr3_exception_valid_kill_c ;
assign other_flushes_in[4] =  agc_thr4_micro_flush_unq_c | load_flush_f[4]  | thr4_sf_kill | 
                              thr4_sf_kill_d | tlu_flush_ifu_f[4] | tlu_flush_ifu_f_d[4] | tlu_flush_ifu_f_dd[4] | 
                              thr4_br_misp_no_match_f|
                              thr4_kill_after_invalidation | thr4_kill_after_invalidation_d  |
                              thr4_exception_valid_kill_c ;
assign other_flushes_in[5] =  agc_thr5_micro_flush_unq_c | load_flush_f[5]  | thr5_sf_kill | 
                              thr5_sf_kill_d | tlu_flush_ifu_f[5] | tlu_flush_ifu_f_d[5] | tlu_flush_ifu_f_dd[5] | 
                              thr5_br_misp_no_match_f|
                              thr5_kill_after_invalidation | thr5_kill_after_invalidation_d  |
                              thr5_exception_valid_kill_c ;
assign other_flushes_in[6] =  agc_thr6_micro_flush_unq_c | load_flush_f[6]  | thr6_sf_kill | 
                              thr6_sf_kill_d | tlu_flush_ifu_f[6] | tlu_flush_ifu_f_d[6] | tlu_flush_ifu_f_dd[6] | 
                              thr6_br_misp_no_match_f|
                              thr6_kill_after_invalidation | thr6_kill_after_invalidation_d  |
                              thr6_exception_valid_kill_c ;
assign other_flushes_in[7] =  agc_thr7_micro_flush_unq_c | load_flush_f[7]  | thr7_sf_kill | 
                              thr7_sf_kill_d | tlu_flush_ifu_f[7] | tlu_flush_ifu_f_d[7] | tlu_flush_ifu_f_dd[7] | 
                              thr7_br_misp_no_match_f|
                              thr7_kill_after_invalidation | thr7_kill_after_invalidation_d   |
                              thr7_exception_valid_kill_c;

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 other_flushes_reg  (
 .scan_in(other_flushes_reg_scanin),
 .scan_out(other_flushes_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (other_flushes_in[7:0]),
 .dout (other_flushes_del[7:0]),
  .siclk(siclk),
  .soclk(soclk));

assign ftu_ibu_redirect_bf[0] = to_ibu_redirect_part_bf[0] | tlu_flush_ifu_f[0] | other_flushes_del[0] | thr0_br_misp_f | thr0_exception_valid_kill_c ;
assign ftu_ibu_redirect_bf[1] = to_ibu_redirect_part_bf[1] | tlu_flush_ifu_f[1] | other_flushes_del[1] | thr1_br_misp_f | thr1_exception_valid_kill_c; 
assign ftu_ibu_redirect_bf[2] = to_ibu_redirect_part_bf[2] | tlu_flush_ifu_f[2] | other_flushes_del[2] | thr2_br_misp_f | thr2_exception_valid_kill_c;
assign ftu_ibu_redirect_bf[3] = to_ibu_redirect_part_bf[3] | tlu_flush_ifu_f[3] | other_flushes_del[3] | thr3_br_misp_f | thr3_exception_valid_kill_c; 
assign ftu_ibu_redirect_bf[4] = to_ibu_redirect_part_bf[4] | tlu_flush_ifu_f[4] | other_flushes_del[4] | thr4_br_misp_f | thr4_exception_valid_kill_c;
assign ftu_ibu_redirect_bf[5] = to_ibu_redirect_part_bf[5] | tlu_flush_ifu_f[5] | other_flushes_del[5] | thr5_br_misp_f | thr5_exception_valid_kill_c;
assign ftu_ibu_redirect_bf[6] = to_ibu_redirect_part_bf[6] | tlu_flush_ifu_f[6] | other_flushes_del[6] | thr6_br_misp_f | thr6_exception_valid_kill_c;
assign ftu_ibu_redirect_bf[7] = to_ibu_redirect_part_bf[7] | tlu_flush_ifu_f[7] | other_flushes_del[7] | thr7_br_misp_f | thr7_exception_valid_kill_c;

assign redirect_ibu_int_bf[0] = to_ibu_redirect_part_bf[0] | tlu_flush_ifu_f[0] | other_flushes_del[0] | thr0_br_misp_f | thr0_exception_valid_kill_c;
assign redirect_ibu_int_bf[1] = to_ibu_redirect_part_bf[1] | tlu_flush_ifu_f[1] | other_flushes_del[1] | thr1_br_misp_f | thr1_exception_valid_kill_c;
assign redirect_ibu_int_bf[2] = to_ibu_redirect_part_bf[2] | tlu_flush_ifu_f[2] | other_flushes_del[2] | thr2_br_misp_f | thr2_exception_valid_kill_c;
assign redirect_ibu_int_bf[3] = to_ibu_redirect_part_bf[3] | tlu_flush_ifu_f[3] | other_flushes_del[3] | thr3_br_misp_f | thr3_exception_valid_kill_c;
assign redirect_ibu_int_bf[4] = to_ibu_redirect_part_bf[4] | tlu_flush_ifu_f[4] | other_flushes_del[4] | thr4_br_misp_f | thr4_exception_valid_kill_c;
assign redirect_ibu_int_bf[5] = to_ibu_redirect_part_bf[5] | tlu_flush_ifu_f[5] | other_flushes_del[5] | thr5_br_misp_f | thr5_exception_valid_kill_c;
assign redirect_ibu_int_bf[6] = to_ibu_redirect_part_bf[6] | tlu_flush_ifu_f[6] | other_flushes_del[6] | thr6_br_misp_f | thr6_exception_valid_kill_c;
assign redirect_ibu_int_bf[7] = to_ibu_redirect_part_bf[7] | tlu_flush_ifu_f[7] | other_flushes_del[7] | thr7_br_misp_f | thr7_exception_valid_kill_c;


assign next_by_pass_sel_bbf[0] = cmu_thr0_data_ready;
assign next_by_pass_sel_bbf[1] = cmu_thr1_data_ready;
assign next_by_pass_sel_bbf[2] = cmu_thr2_data_ready;
assign next_by_pass_sel_bbf[3] = cmu_thr3_data_ready;
assign next_by_pass_sel_bbf[4] = cmu_thr4_data_ready;
assign next_by_pass_sel_bbf[5] = cmu_thr5_data_ready;
assign next_by_pass_sel_bbf[6] = cmu_thr6_data_ready;
assign next_by_pass_sel_bbf[7] = cmu_thr7_data_ready;

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 cmu_fill_byp_thread_reg  (
 .scan_in(cmu_fill_byp_thread_reg_scanin),
 .scan_out(cmu_fill_byp_thread_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_by_pass_sel_bbf[7:0]),
 .dout (agc_by_pass_sel_bf[7:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 by_pass_thread_bf_reg  (
 .scan_in(by_pass_thread_bf_reg_scanin),
 .scan_out(by_pass_thread_bf_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_by_pass_sel_bbf[7:0]),
 .dout (by_pass_thread_bf[7:0]),
  .siclk(siclk),
  .soclk(soclk));


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 by_pass_sel_f_reg  (
 .scan_in(by_pass_sel_f_reg_scanin),
 .scan_out(by_pass_sel_f_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (agc_by_pass_sel_bf[7:0]),
 .dout (agc_by_pass_sel_f[7:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 by_pass_sel_c_reg  (
 .scan_in(by_pass_sel_c_reg_scanin),
 .scan_out(by_pass_sel_c_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (agc_by_pass_sel_f[7:0]),
 .dout (by_pass_thread_c[7:0]),
  .siclk(siclk),
  .soclk(soclk));


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 by_pass_thread_f_reg  (
 .scan_in(by_pass_thread_f_reg_scanin),
 .scan_out(by_pass_thread_f_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (agc_by_pass_sel_bf[7:0]),
 .dout (by_pass_thread_f[7:0]),
  .siclk(siclk),
  .soclk(soclk));

 
ifu_ftu_agc_ctl_msff_ctl_macro__width_1 fetchalid_cnq_reg  (
 .scan_in(fetchalid_cnq_reg_scanin),
 .scan_out(fetchalid_cnq_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (ftp_fetch_v_f),
 .dout (agc_fetch_v_c_unq),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 fetch_v_dup_c_reg  (
 .scan_in(fetch_v_dup_c_reg_scanin),
 .scan_out(fetch_v_dup_c_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (ftp_fetch_v_f),
 .dout (agc_fetch_v_c_dup_unq),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// Generate instruction bypass mux selects 
///////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////////
// Create signals that show which cycle the by_pass is possible.                   //
// NOTE: If previous by_pass occupies the slot which the new by_pass may take, it  //
//       has to be scheduled for the next available cycle (slot).                  //
/////////////////////////////////////////////////////////////////////////////////////
assign prev_by_pass_at_cycle_1 = agc_cycle_2_by_pass_ok_f | agc_cycle_3_by_pass_ok_c ;
assign prev_by_pass_at_cycle_2 = agc_cycle_3_by_pass_ok_f ;

assign agc_fetch_v_int_c = agc_fetch_v_c_unq & ~agc_kill_fetch_cv_int1_c ; 
assign agc_fetch_v_c = agc_fetch_v_c_unq  ; // & ~agc_kill_fetch_cv_c ;

assign agc_cycle_2_by_pass_ok_bf=  ((agc_fetch_v_c | prev_by_pass_at_cycle_1) & ~(ftp_fetch_v_f | prev_by_pass_at_cycle_2) & agc_by_pass_valid_bf);  
assign agc_cycle_3_by_pass_ok_bf=  ((agc_fetch_v_c | prev_by_pass_at_cycle_1)  &  (ftp_fetch_v_f | prev_by_pass_at_cycle_2)   & agc_by_pass_valid_bf) ;


// Cycle_2
 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 cycle_2_by_pass_f_reg  (
  .scan_in(cycle_2_by_pass_f_reg_scanin),
  .scan_out(cycle_2_by_pass_f_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (agc_cycle_2_by_pass_ok_bf),
  .dout (agc_cycle_2_by_pass_ok_f),
  .siclk(siclk),
  .soclk(soclk));
 
// Cycle_3
 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 cycle_3_by_pass_f_reg  (
  .scan_in(cycle_3_by_pass_f_reg_scanin),
  .scan_out(cycle_3_by_pass_f_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (agc_cycle_3_by_pass_ok_bf),
  .dout (agc_cycle_3_by_pass_ok_f),
  .siclk(siclk),
  .soclk(soclk));
 
 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 cycle_3_by_pass_c_reg  (
  .scan_in(cycle_3_by_pass_c_reg_scanin),
  .scan_out(cycle_3_by_pass_c_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (agc_cycle_3_by_pass_ok_f),
  .dout (agc_cycle_3_by_pass_ok_c),
  .siclk(siclk),
  .soclk(soclk));


assign byp_valid_in = cmu_any_data_ready & ~( thr0_kill_by_pass_bbf |
                                              thr1_kill_by_pass_bbf |
                                              thr2_kill_by_pass_bbf |
                                              thr3_kill_by_pass_bbf |
                                              thr4_kill_by_pass_bbf |
                                              thr5_kill_by_pass_bbf |
                                              thr6_kill_by_pass_bbf |
                                              thr7_kill_by_pass_bbf ) ;
 
ifu_ftu_agc_ctl_msff_ctl_macro__width_1 cmu_any_data_ready_reg  (
  .scan_in(cmu_any_data_ready_reg_scanin),
  .scan_out(cmu_any_data_ready_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (byp_valid_in),
  .dout (agc_byp_valid),
  .siclk(siclk),
  .soclk(soclk));

assign thr0_kill_by_pass_bbf = next_by_pass_sel_bbf[0] & (tsm_thr0_ignore_by_pass | ftu_thr0_redirect_bf) ;  
assign thr1_kill_by_pass_bbf = next_by_pass_sel_bbf[1] & (tsm_thr1_ignore_by_pass | ftu_thr1_redirect_bf) ;  
assign thr2_kill_by_pass_bbf = next_by_pass_sel_bbf[2] & (tsm_thr2_ignore_by_pass | ftu_thr2_redirect_bf) ;  
assign thr3_kill_by_pass_bbf = next_by_pass_sel_bbf[3] & (tsm_thr3_ignore_by_pass | ftu_thr3_redirect_bf) ;  
assign thr4_kill_by_pass_bbf = next_by_pass_sel_bbf[4] & (tsm_thr4_ignore_by_pass | ftu_thr4_redirect_bf) ;  
assign thr5_kill_by_pass_bbf = next_by_pass_sel_bbf[5] & (tsm_thr5_ignore_by_pass | ftu_thr5_redirect_bf) ;  
assign thr6_kill_by_pass_bbf = next_by_pass_sel_bbf[6] & (tsm_thr6_ignore_by_pass | ftu_thr6_redirect_bf) ;  
assign thr7_kill_by_pass_bbf = next_by_pass_sel_bbf[7] & (tsm_thr7_ignore_by_pass | ftu_thr7_redirect_bf) ;  

 ifu_ftu_agc_ctl_msff_ctl_macro__width_8 tsm_thrx_kill_by_pass_reg  (
  .scan_in(tsm_thrx_kill_by_pass_reg_scanin),
  .scan_out(tsm_thrx_kill_by_pass_reg_scanout),
  .l1clk( l1clk  ),
  .din  ({thr7_kill_by_pass_bbf,thr6_kill_by_pass_bbf,thr5_kill_by_pass_bbf,thr4_kill_by_pass_bbf,
          thr3_kill_by_pass_bbf,thr2_kill_by_pass_bbf,thr1_kill_by_pass_bbf,thr0_kill_by_pass_bbf}),
  .dout ({thr7_kill_by_pass_bf,thr6_kill_by_pass_bf,thr5_kill_by_pass_bf,thr4_kill_by_pass_bf,
          thr3_kill_by_pass_bf,thr2_kill_by_pass_bf,thr1_kill_by_pass_bf,thr0_kill_by_pass_bf}),
  .siclk(siclk),
  .soclk(soclk));

assign kill2_by_pass_bf  = (agc_by_pass_sel_bf[0] & ftu_thr0_redirect_bf) |
                           (agc_by_pass_sel_bf[1] & ftu_thr1_redirect_bf) |
                           (agc_by_pass_sel_bf[2] & ftu_thr2_redirect_bf) |
                           (agc_by_pass_sel_bf[3] & ftu_thr3_redirect_bf) |
                           (agc_by_pass_sel_bf[4] & ftu_thr4_redirect_bf) |
                           (agc_by_pass_sel_bf[5] & ftu_thr5_redirect_bf) |
                           (agc_by_pass_sel_bf[6] & ftu_thr6_redirect_bf) |
                           (agc_by_pass_sel_bf[7] & ftu_thr7_redirect_bf) ;

assign bypass_thread_killed = thr7_kill_by_pass_bf | thr6_kill_by_pass_bf | thr5_kill_by_pass_bf |
                              thr4_kill_by_pass_bf | thr3_kill_by_pass_bf | thr2_kill_by_pass_bf |
                              thr1_kill_by_pass_bf | thr0_kill_by_pass_bf | kill2_by_pass_bf     ;

assign agc_by_pass_valid_bf = agc_byp_valid & ~bypass_thread_killed ;


assign next_by_pass_f_valid = agc_by_pass_valid_bf ; 

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 by_pass_v_f_reg  (
 .scan_in(by_pass_v_f_reg_scanin),
 .scan_out(by_pass_v_f_reg_scanout),
 .l1clk( l1clk_pm1  ),
 .din  (next_by_pass_f_valid),
 .dout (agc_by_pass_valid_unq_f),
  .siclk(siclk),
  .soclk(soclk));

assign agc_by_pass_valid_f = agc_by_pass_valid_unq_f & ~bypass_thread_redirected_p_f ; 
assign bypass_thread_redirected_p_f = ((ftu_thr0_redirect_bf) & agc_by_pass_sel_f[0]) |
                                      ((ftu_thr1_redirect_bf) & agc_by_pass_sel_f[1]) |
                                      ((ftu_thr2_redirect_bf) & agc_by_pass_sel_f[2]) |
                                      ((ftu_thr3_redirect_bf) & agc_by_pass_sel_f[3]) |
                                      ((ftu_thr4_redirect_bf) & agc_by_pass_sel_f[4]) |
                                      ((ftu_thr5_redirect_bf) & agc_by_pass_sel_f[5]) |
                                      ((ftu_thr6_redirect_bf) & agc_by_pass_sel_f[6]) |
                                      ((ftu_thr7_redirect_bf) & agc_by_pass_sel_f[7]) ;


assign bypass_thread_redirected_f = ((ftu_thr0_redirect_int_bf | ftu_thr0_redirect_bf) & agc_by_pass_sel_f[0]) |
                                    ((ftu_thr1_redirect_int_bf | ftu_thr1_redirect_bf) & agc_by_pass_sel_f[1]) |
                                    ((ftu_thr2_redirect_int_bf | ftu_thr2_redirect_bf) & agc_by_pass_sel_f[2]) |
                                    ((ftu_thr3_redirect_int_bf | ftu_thr3_redirect_bf) & agc_by_pass_sel_f[3]) |
                                    ((ftu_thr4_redirect_int_bf | ftu_thr4_redirect_bf) & agc_by_pass_sel_f[4]) |
                                    ((ftu_thr5_redirect_int_bf | ftu_thr5_redirect_bf) & agc_by_pass_sel_f[5]) |
                                    ((ftu_thr6_redirect_int_bf | ftu_thr6_redirect_bf) & agc_by_pass_sel_f[6]) |
                                    ((ftu_thr7_redirect_int_bf | ftu_thr7_redirect_bf) & agc_by_pass_sel_f[7]) ;

/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Update the LRU for the fetching mechanism if by_pass is valid.                                      //
/////////////////////////////////////////////////////////////////////////////////////////////////////////
assign agc_by_pass_update_lru_bf[0]     = agc_by_pass_sel_bf[0] & agc_byp_valid & ~thr0_kill_by_pass_bf ;  
assign agc_by_pass_update_lru_bf[1]     = agc_by_pass_sel_bf[1] & agc_byp_valid & ~thr1_kill_by_pass_bf ;  
assign agc_by_pass_update_lru_bf[2]     = agc_by_pass_sel_bf[2] & agc_byp_valid & ~thr2_kill_by_pass_bf ;  
assign agc_by_pass_update_lru_bf[3]     = agc_by_pass_sel_bf[3] & agc_byp_valid & ~thr3_kill_by_pass_bf ;  
assign agc_by_pass_update_lru_bf[4]     = agc_by_pass_sel_bf[4] & agc_byp_valid & ~thr4_kill_by_pass_bf ;  
assign agc_by_pass_update_lru_bf[5]     = agc_by_pass_sel_bf[5] & agc_byp_valid & ~thr5_kill_by_pass_bf ;  
assign agc_by_pass_update_lru_bf[6]     = agc_by_pass_sel_bf[6] & agc_byp_valid & ~thr6_kill_by_pass_bf ;  
assign agc_by_pass_update_lru_bf[7]     = agc_by_pass_sel_bf[7] & agc_byp_valid & ~thr7_kill_by_pass_bf ;  


assign agc_sel_by_pass_cycle_2_f  = (agc_cycle_2_by_pass_ok_f  & agc_by_pass_valid_unq_f) ; 
assign agc_sel_by_pass_cycle_3_c  = (agc_cycle_3_by_pass_ok_c  & agc_by_pass_valid_c) ; 
 
 assign next_by_pass_c_valid = agc_by_pass_valid_f & ~bypass_thread_redirected_f ;
 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 by_pass_v_c_reg  (
  .scan_in(by_pass_v_c_reg_scanin),
  .scan_out(by_pass_v_c_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (next_by_pass_c_valid),
  .dout (agc_by_pass_valid_c),
  .siclk(siclk),
  .soclk(soclk));
 
assign agc_sel_by_pass_cycle_2_int_f  = (agc_cycle_2_by_pass_ok_f  & agc_by_pass_valid_unq_f) ; 
assign agc_sel_by_pass_cycle_3_int_c  = (agc_cycle_3_by_pass_ok_c  & agc_by_pass_valid_c) ; 


assign agc_pc_sel_for_c[0] = agc_fetch_v_c ; 
assign agc_pc_sel_for_c[1] = ~agc_pc_sel_for_c[0]  & ~agc_pc_sel_for_c[2] & ~agc_pc_sel_for_c[3] ;
assign agc_pc_sel_for_c[2] = agc_sel_by_pass_cycle_2_int_f ;
assign agc_pc_sel_for_c[3] = agc_sel_by_pass_cycle_3_int_c ;


///////////////////////////////////////////////////////////////////////////////
// NOTE:
// Exceptions can happen during by_pass too (L2ECC errors)                   //
///////////////////////////////////////////////////////////////////////////////

assign agc_instr_bp_sel_c[0] =  agc_fetch_v_c_dup_unq  ; // & ~io_is_not_boot_rom_c; 
assign agc_instr_bp_sel_c[1] =  (!agc_fetch_v_c_dup_unq  &  agc_sel_by_pass_cycle_2_f ) ; 
assign agc_instr_bp_sel_c[2] =  (!agc_fetch_v_c_dup_unq  &  agc_sel_by_pass_cycle_3_c ) ; 

assign agc_bypass_selects[0] = (!agc_fetch_v_c_dup_unq  &  agc_byp_valid & !prev_by_pass_at_cycle_1 ) ; 
assign agc_bypass_selects[1] = (!agc_fetch_v_c_dup_unq  &  agc_sel_by_pass_cycle_2_f ) ; 
assign agc_bypass_selects[2] = (!agc_fetch_v_c_dup_unq  &  agc_sel_by_pass_cycle_3_c ) ; 


///////////////////////////////////////////////////////////////////////////////
// Generate the instruction valid signal for C stage.                        //
///////////////////////////////////////////////////////////////////////////////

assign by_pass_valid_instr_bf[3]  = cmu_instr_v[3] & ~sf_valid_by_pass_bf ;  
assign by_pass_valid_instr_bf[2]  = cmu_instr_v[2] & ~sf_valid_by_pass_bf ;  
assign by_pass_valid_instr_bf[1]  = cmu_instr_v[1] & ~sf_valid_by_pass_bf ; 
assign by_pass_valid_instr_bf[0]  = cmu_instr_v[0] ; 


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 by_pass_instr_v_f_reg  (
 .scan_in(by_pass_instr_v_f_reg_scanin),
 .scan_out(by_pass_instr_v_f_reg_scanout),
 .l1clk( l1clk_pm1  ),
 .din  (by_pass_valid_instr_bf[3:0]),
 .dout (by_pass_valid_instr_f[3:0]),
  .siclk(siclk),
  .soclk(soclk));


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 by_pass_instr_v_c_reg  (
 .scan_in(by_pass_instr_v_c_reg_scanin),
 .scan_out(by_pass_instr_v_c_reg_scanout),
 .l1clk( l1clk_pm1  ),
 .din  (by_pass_valid_instr_f[3:0]),
 .dout (by_pass_valid_instr_c[3:0]),
  .siclk(siclk),
  .soclk(soclk));

//////////////////////////////////////////////////////////
// Number of instructions valid can come from one of    //
// four source:                                         //
// 1-   Normal fetching                                 //
// 2-   By_pass in the first cycle when C stage is      //
//      empty when the data is recieved.                //
// 3-   By_pass in the second cycle when C stage is not //
//      empty but the F stage is.                       //
// 4-   By_pass in the third cycle when C and F stages  //
//      are not empty when the bypass data arrives.     //
//////////////////////////////////////////////////////////

assign ftu_instr_valid_c[0] = (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_valid_instr_bf[0]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_valid_instr_f[0]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_valid_instr_c[0]) | 
                              ( agc_fetch_v_c             & instr_0_v_q_c) ;  

assign ftu_instr_valid_c[1] = (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_valid_instr_bf[1]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_valid_instr_f[1]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_valid_instr_c[1]) | 
                              ( agc_fetch_v_c             & instr_1_v_q_c) ; 

assign ftu_instr_valid_c[2] = (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_valid_instr_bf[2]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_valid_instr_f[2]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_valid_instr_c[2]) | 
                              ( agc_fetch_v_c             & instr_2_v_q_c)  ; 

assign ftu_instr_valid_c[3] = (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_valid_instr_bf[3]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_valid_instr_f[3]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_valid_instr_c[3]) | 
                              ( agc_fetch_v_c             & instr_3_v_q_c) ; 

                                     
assign bus_3_is_first_in = ( ifu_agd_pc_f[3] &  ifu_agd_pc_f[2]) & ftp_fetch_v_f;
assign bus_2_is_first_in = ( ifu_agd_pc_f[3] & !ifu_agd_pc_f[2]) & ftp_fetch_v_f;
assign bus_1_is_first_in = (!ifu_agd_pc_f[3] &  ifu_agd_pc_f[2]) & ftp_fetch_v_f;
assign bus_0_is_first_in = (!ifu_agd_pc_f[3] & !ifu_agd_pc_f[2]) | ~ftp_fetch_v_f;

ifu_ftu_agc_ctl_msff_ctl_macro__width_4 bus_first_reg  (
 .scan_in(bus_first_reg_scanin),
 .scan_out(bus_first_reg_scanout),
 .l1clk( l1clk_pm1 ),
 .din  ({bus_3_is_first_in,bus_2_is_first_in,bus_1_is_first_in,bus_0_is_first_in}),
 .dout ({ftu_bus_3_is_first,ftu_bus_2_is_first,ftu_bus_1_is_first,ftu_bus_0_is_first}),
  .siclk(siclk),
  .soclk(soclk));

assign ftu_fetch_thr_c[0] =   (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_thread_bf[0]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_thread_f[0]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_thread_c[0]) | 
                              ( agc_fetch_v_c             & curr_fetch_thr_c[0]) ; 

assign ftu_fetch_thr_c[1] =   (!agc_fetch_v_c & agc_byp_valid &
                               !prev_by_pass_at_cycle_1   &  by_pass_thread_bf[1]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_thread_f[1]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_thread_c[1]) | 
                              ( agc_fetch_v_c             & curr_fetch_thr_c[1]) ; 

assign ftu_fetch_thr_c[2] =   (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_thread_bf[2]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_thread_f[2]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_thread_c[2]) | 
                              ( agc_fetch_v_c             & curr_fetch_thr_c[2]) ; 

assign ftu_fetch_thr_c[3] =   (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_thread_bf[3]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_thread_f[3]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_thread_c[3]) | 
                              ( agc_fetch_v_c             & curr_fetch_thr_c[3]) ; 

assign ftu_fetch_thr_c[4] =   (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_thread_bf[4]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_thread_f[4]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_thread_c[4]) | 
                              ( agc_fetch_v_c             & curr_fetch_thr_c[4]) ; 

assign ftu_fetch_thr_c[5] =   (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_thread_bf[5]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_thread_f[5]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_thread_c[5]) | 
                              ( agc_fetch_v_c             & curr_fetch_thr_c[5]) ; 

assign ftu_fetch_thr_c[6] =   (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_thread_bf[6]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_thread_f[6]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_thread_c[6]) | 
                              ( agc_fetch_v_c             & curr_fetch_thr_c[6]) ; 

assign ftu_fetch_thr_c[7] =   (!agc_fetch_v_c & agc_byp_valid & 
                               !prev_by_pass_at_cycle_1   &  by_pass_thread_bf[7]) | 
                              ( agc_sel_by_pass_cycle_2_f & by_pass_thread_f[7]) | 
                              ( agc_sel_by_pass_cycle_3_c & by_pass_thread_c[7]) | 
                              ( agc_fetch_v_c             & curr_fetch_thr_c[7]) ; 

 
assign sf_valid_c         =   (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  sf_valid_by_pass_bf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & sf_valid_by_pass_f) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & sf_valid_by_pass_c) | 
                              ( agc_fetch_v_int_c           &  instr_sf_valid_c) | 
                              ( exception_valid_int_c       &  instr_sf_valid_c);

assign thr0_sf_kill         = (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  thr0_byp_bf_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & thr0_byp_f_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & thr0_byp_c_kill_sf) | 
                              ( agc_fetch_v_int_c           & thr0_instr_kill_sf) | 
                              ( exception_valid_int_c       & thr0_instr_kill_sf);
 
assign thr1_sf_kill         = (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  thr1_byp_bf_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & thr1_byp_f_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & thr1_byp_c_kill_sf) | 
                              ( agc_fetch_v_int_c           & thr1_instr_kill_sf) | 
                              ( exception_valid_int_c       & thr1_instr_kill_sf);
 
assign thr2_sf_kill         = (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  thr2_byp_bf_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & thr2_byp_f_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & thr2_byp_c_kill_sf) | 
                              ( agc_fetch_v_int_c           & thr2_instr_kill_sf) | 
                              ( exception_valid_int_c       & thr2_instr_kill_sf);
 
assign thr3_sf_kill         = (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  thr3_byp_bf_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & thr3_byp_f_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & thr3_byp_c_kill_sf) | 
                              ( agc_fetch_v_int_c           & thr3_instr_kill_sf) | 
                              ( exception_valid_int_c       & thr3_instr_kill_sf);
 
assign thr4_sf_kill         = (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  thr4_byp_bf_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & thr4_byp_f_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & thr4_byp_c_kill_sf) | 
                              ( agc_fetch_v_int_c           & thr4_instr_kill_sf) | 
                              ( exception_valid_int_c       & thr4_instr_kill_sf);
 
assign thr5_sf_kill         = (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  thr5_byp_bf_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & thr5_byp_f_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & thr5_byp_c_kill_sf) | 
                              ( agc_fetch_v_int_c           & thr5_instr_kill_sf) | 
                              ( exception_valid_int_c       & thr5_instr_kill_sf);
 
assign thr6_sf_kill         = (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  thr6_byp_bf_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & thr6_byp_f_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & thr6_byp_c_kill_sf) | 
                              ( agc_fetch_v_int_c           & thr6_instr_kill_sf) | 
                              ( exception_valid_int_c       & thr6_instr_kill_sf);
 
assign thr7_sf_kill         = (!exception_valid_int_c       & !agc_fetch_v_c & agc_byp_valid &!bypass_thread_killed & 
                               !prev_by_pass_at_cycle_1 &  thr7_byp_bf_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_2_int_f & thr7_byp_f_kill_sf) | 
                              (!exception_valid_int_c       &  agc_sel_by_pass_cycle_3_int_c & thr7_byp_c_kill_sf) | 
                              ( agc_fetch_v_int_c           & thr7_instr_kill_sf) | 
                              ( exception_valid_int_c       & thr7_instr_kill_sf);
 
 ifu_ftu_agc_ctl_msff_ctl_macro__width_8 thrx_sf_kill_reg  (
  .scan_in(thrx_sf_kill_reg_scanin),
  .scan_out(thrx_sf_kill_reg_scanout),
  .l1clk( l1clk                                                             ),
  .din  ({thr7_sf_kill,thr6_sf_kill,thr5_sf_kill,thr4_sf_kill,
          thr3_sf_kill,thr2_sf_kill,thr1_sf_kill,thr0_sf_kill}),
  .dout ({thr7_sf_kill_d,thr6_sf_kill_d,thr5_sf_kill_d,thr4_sf_kill_d,
          thr3_sf_kill_d,thr2_sf_kill_d,thr1_sf_kill_d,thr0_sf_kill_d}),
  .siclk(siclk),
  .soclk(soclk)) ;

assign thr0_instr_kill_sf   = instr_sf_valid_c    & curr_fetch_thr_c[0] & any_instr_v_q_c ;       
assign thr0_byp_bf_kill_sf  = sf_valid_by_pass_bf & by_pass_thread_bf[0]    & by_pass_valid_instr_bf[0] ;       
assign thr0_byp_f_kill_sf   = sf_valid_by_pass_f  & by_pass_thread_f[0]     & by_pass_valid_instr_f[0] ;       
assign thr0_byp_c_kill_sf   = sf_valid_by_pass_c  & by_pass_thread_c[0]     & by_pass_valid_instr_c[0] ;       


assign thr1_instr_kill_sf   = instr_sf_valid_c    & curr_fetch_thr_c[1] & any_instr_v_q_c ;       
assign thr1_byp_bf_kill_sf  = sf_valid_by_pass_bf & by_pass_thread_bf[1]    & by_pass_valid_instr_bf[0] ;       
assign thr1_byp_f_kill_sf   = sf_valid_by_pass_f  & by_pass_thread_f[1]     & by_pass_valid_instr_f[0] ;       
assign thr1_byp_c_kill_sf   = sf_valid_by_pass_c  & by_pass_thread_c[1]     & by_pass_valid_instr_c[0] ;       

assign thr2_instr_kill_sf   = instr_sf_valid_c    & curr_fetch_thr_c[2] & any_instr_v_q_c ;       
assign thr2_byp_bf_kill_sf  = sf_valid_by_pass_bf & by_pass_thread_bf[2]    & by_pass_valid_instr_bf[0] ;       
assign thr2_byp_f_kill_sf   = sf_valid_by_pass_f  & by_pass_thread_f[2]     & by_pass_valid_instr_f[0] ;       
assign thr2_byp_c_kill_sf   = sf_valid_by_pass_c  & by_pass_thread_c[2]     & by_pass_valid_instr_c[0] ;       

assign thr3_instr_kill_sf   = instr_sf_valid_c    & curr_fetch_thr_c[3] & any_instr_v_q_c ;       
assign thr3_byp_bf_kill_sf  = sf_valid_by_pass_bf & by_pass_thread_bf[3]    & by_pass_valid_instr_bf[0] ;       
assign thr3_byp_f_kill_sf   = sf_valid_by_pass_f  & by_pass_thread_f[3]     & by_pass_valid_instr_f[0] ;       
assign thr3_byp_c_kill_sf   = sf_valid_by_pass_c  & by_pass_thread_c[3]     & by_pass_valid_instr_c[0] ;       

assign thr4_instr_kill_sf   = instr_sf_valid_c    & curr_fetch_thr_c[4] & any_instr_v_q_c ;       
assign thr4_byp_bf_kill_sf  = sf_valid_by_pass_bf & by_pass_thread_bf[4]    & by_pass_valid_instr_bf[0] ;       
assign thr4_byp_f_kill_sf   = sf_valid_by_pass_f  & by_pass_thread_f[4]     & by_pass_valid_instr_f[0] ;       
assign thr4_byp_c_kill_sf   = sf_valid_by_pass_c  & by_pass_thread_c[4]     & by_pass_valid_instr_c[0] ;       


assign thr5_instr_kill_sf   = instr_sf_valid_c    & curr_fetch_thr_c[5] & any_instr_v_q_c ;       
assign thr5_byp_bf_kill_sf  = sf_valid_by_pass_bf & by_pass_thread_bf[5]    & by_pass_valid_instr_bf[0] ;       
assign thr5_byp_f_kill_sf   = sf_valid_by_pass_f  & by_pass_thread_f[5]     & by_pass_valid_instr_f[0] ;       
assign thr5_byp_c_kill_sf   = sf_valid_by_pass_c  & by_pass_thread_c[5]     & by_pass_valid_instr_c[0] ;       

assign thr6_instr_kill_sf   = instr_sf_valid_c    & curr_fetch_thr_c[6] & any_instr_v_q_c ;       
assign thr6_byp_bf_kill_sf  = sf_valid_by_pass_bf & by_pass_thread_bf[6]    & by_pass_valid_instr_bf[0] ;       
assign thr6_byp_f_kill_sf   = sf_valid_by_pass_f  & by_pass_thread_f[6]     & by_pass_valid_instr_f[0] ;       
assign thr6_byp_c_kill_sf   = sf_valid_by_pass_c  & by_pass_thread_c[6]     & by_pass_valid_instr_c[0] ;       

assign thr7_instr_kill_sf   = instr_sf_valid_c    & curr_fetch_thr_c[7] & any_instr_v_q_c ;       
assign thr7_byp_bf_kill_sf  = sf_valid_by_pass_bf & by_pass_thread_bf[7]    & by_pass_valid_instr_bf[0] ;       
assign thr7_byp_f_kill_sf   = sf_valid_by_pass_f  & by_pass_thread_f[7]     & by_pass_valid_instr_f[0] ;       
assign thr7_byp_c_kill_sf   = sf_valid_by_pass_c  & by_pass_thread_c[7]     & by_pass_valid_instr_c[0] ;       


///////////////////////////////////////////////////////////
// Generate the write enable for the V bits.             //
///////////////////////////////////////////////////////////
 ifu_ftu_agc_ctl_msff_ctl_macro__width_16 mbist_data_in_reg  (
  .scan_in(mbist_data_in_reg_scanin),
  .scan_out(mbist_data_in_reg_scanout),
  .l1clk( l1clk                                                             ),
  .din  ({mbi_addr[8:6], mbi_cmpsel[2:0],  mbi_run, mbi_icv_write_en,mbi_wdata[7:0]}),
  .dout ({mbi_bist_way_bf[2:0], mbi_bist_word_en_bf[2:0],  mbi_run_bf, mbi_icv_write_en_bf, mbi_wdata_bf[7:0]}),
  .siclk(siclk),
  .soclk(soclk));

 assign agc_fill_wrway_bf[2:0] = ({3{agc_data_ready_bf & !mbi_run_bf}} &  agc_cmu_fill_wrway_bf[2:0] ) |
                                 ({3{mbi_run_bf}} & mbi_bist_way_bf[2:0]) |
                                 ({3{(!agc_data_ready_bf & !mbi_run_bf)}} &  asi_way_bf[2:0] ) ;

 ifu_ftu_agc_ctl_msff_ctl_macro__width_3 cmu_fill_wrway_reg  (
  .scan_in(cmu_fill_wrway_reg_scanin),
  .scan_out(cmu_fill_wrway_reg_scanout),
  .l1clk( l1clk                                                             ),
  .din  (cmu_fill_wrway[2:0]),
  .dout (agc_cmu_fill_wrway_bf[2:0]),
  .siclk(siclk),
  .soclk(soclk));

 ifu_ftu_agc_ctl_msff_ctl_macro__width_3 asi_mbist_way_f_reg  (
  .scan_in(asi_mbist_way_f_reg_scanin),
  .scan_out(asi_mbist_way_f_reg_scanout),
  .l1clk( l1clk_pm1                                                             ),
  .din  (agc_fill_wrway_bf[2:0]),
  .dout (agc_asi_mbist_way_f[2:0]),
  .siclk(siclk),
  .soclk(soclk));


assign agc_sel_tg_data_f[0] = ~agc_asi_mbist_way_f[2] & ~agc_asi_mbist_way_f[1] & ~agc_asi_mbist_way_f[0] ; 
assign agc_sel_tg_data_f[1] = ~agc_asi_mbist_way_f[2] & ~agc_asi_mbist_way_f[1] &  agc_asi_mbist_way_f[0] ; 
assign agc_sel_tg_data_f[2] = ~agc_asi_mbist_way_f[2] &  agc_asi_mbist_way_f[1] & ~agc_asi_mbist_way_f[0] ; 
assign agc_sel_tg_data_f[3] = ~agc_asi_mbist_way_f[2] &  agc_asi_mbist_way_f[1] &  agc_asi_mbist_way_f[0] ; 
assign agc_sel_tg_data_f[4] =  agc_asi_mbist_way_f[2] & ~agc_asi_mbist_way_f[1] & ~agc_asi_mbist_way_f[0] ; 
assign agc_sel_tg_data_f[5] =  agc_asi_mbist_way_f[2] & ~agc_asi_mbist_way_f[1] &  agc_asi_mbist_way_f[0] ; 
assign agc_sel_tg_data_f[6] =  agc_asi_mbist_way_f[2] &  agc_asi_mbist_way_f[1] & ~agc_asi_mbist_way_f[0] ; 
assign agc_sel_tg_data_f[7] =  agc_asi_mbist_way_f[2] &  agc_asi_mbist_way_f[1] &  agc_asi_mbist_way_f[0] ; 

assign next_wrway_bbf[0]     = ~cmu_fill_wrway[2] & ~cmu_fill_wrway[1] & ~cmu_fill_wrway[0] ; 
assign next_wrway_bbf[1]     = ~cmu_fill_wrway[2] & ~cmu_fill_wrway[1] &  cmu_fill_wrway[0] ; 
assign next_wrway_bbf[2]     = ~cmu_fill_wrway[2] &  cmu_fill_wrway[1] & ~cmu_fill_wrway[0] ; 
assign next_wrway_bbf[3]     = ~cmu_fill_wrway[2] &  cmu_fill_wrway[1] &  cmu_fill_wrway[0] ; 
assign next_wrway_bbf[4]     =  cmu_fill_wrway[2] & ~cmu_fill_wrway[1] & ~cmu_fill_wrway[0] ; 
assign next_wrway_bbf[5]     =  cmu_fill_wrway[2] & ~cmu_fill_wrway[1] &  cmu_fill_wrway[0] ; 
assign next_wrway_bbf[6]     =  cmu_fill_wrway[2] &  cmu_fill_wrway[1] & ~cmu_fill_wrway[0] ; 
assign next_wrway_bbf[7]     =  cmu_fill_wrway[2] &  cmu_fill_wrway[1] &  cmu_fill_wrway[0] ; 

assign vl_data[1]        = (agc_sel_tg_data_f[0] & agd_itlb_valid_f[0] ) | 
                               (agc_sel_tg_data_f[1] & agd_itlb_valid_f[1] ) | 
                               (agc_sel_tg_data_f[2] & agd_itlb_valid_f[2] ) | 
                               (agc_sel_tg_data_f[3] & agd_itlb_valid_f[3] ) | 
                               (agc_sel_tg_data_f[4] & agd_itlb_valid_f[4] ) | 
                               (agc_sel_tg_data_f[5] & agd_itlb_valid_f[5] ) | 
                               (agc_sel_tg_data_f[6] & agd_itlb_valid_f[6] ) | 
                               (agc_sel_tg_data_f[7] & agd_itlb_valid_f[7] ) ; 

assign vl_data[0]        = (agc_sel_tg_data_f[0] & agd_itlb_valid_dupl_f[0] ) | 
                               (agc_sel_tg_data_f[1] & agd_itlb_valid_dupl_f[1] ) | 
                               (agc_sel_tg_data_f[2] & agd_itlb_valid_dupl_f[2] ) | 
                               (agc_sel_tg_data_f[3] & agd_itlb_valid_dupl_f[3] ) | 
                               (agc_sel_tg_data_f[4] & agd_itlb_valid_dupl_f[4] ) | 
                               (agc_sel_tg_data_f[5] & agd_itlb_valid_dupl_f[5] ) | 
                               (agc_sel_tg_data_f[6] & agd_itlb_valid_dupl_f[6] ) | 
                               (agc_sel_tg_data_f[7] & agd_itlb_valid_dupl_f[7] ) ; 

 ifu_ftu_agc_ctl_msff_ctl_macro__width_2 vl_data_reg  (
  .scan_in(vl_data_reg_scanin),
  .scan_out(vl_data_reg_scanout),
  .l1clk( l1clk_pm1                                                             ),
  .din  (vl_data[1:0]),
  .dout (agc_vl_data_c[1:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 itlb_valid_reg  (
 .scan_in(itlb_valid_reg_scanin),
 .scan_out(itlb_valid_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (agd_itlb_valid_f[7:0]),
 .dout (itlb_valid_c[7:0]),
  .siclk(siclk),
  .soclk(soclk));


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 itlb_valid_dupl_reg  (
 .scan_in(itlb_valid_dupl_reg_scanin),
 .scan_out(itlb_valid_dupl_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (agd_itlb_valid_dupl_f[7:0]),
 .dout (itlb_valid_dupl_c[7:0]),
  .siclk(siclk),
  .soclk(soclk));

assign va_hole_excp_extra = ~ifu_agd_pc_f[47] & (&ifu_agd_pc_f[46:5]) ;
assign next_va_hole_excp = (agd_va_hole_excp_f | va_hole_excp_extra) & ~agc_itb_bypass_f ;
 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 va_hole_excp_c_reg  (
  .scan_in(va_hole_excp_c_reg_scanin),
  .scan_out(va_hole_excp_c_reg_scanout),
  .l1clk( l1clk_pm1                                                             ),
  .din  (next_va_hole_excp),
  .dout (va_hole_excp_c),
  .siclk(siclk),
  .soclk(soclk));


assign inv_ack               =  |cmu_inval_ack[7:0] ; 
assign next_inv_way_bbf[0]     = (~cmu_icache_invalidate_way[2] & ~cmu_icache_invalidate_way[1] & ~cmu_icache_invalidate_way[0]) | inv_ack ; 
assign next_inv_way_bbf[1]     = (~cmu_icache_invalidate_way[2] & ~cmu_icache_invalidate_way[1] &  cmu_icache_invalidate_way[0]) | inv_ack ; 
assign next_inv_way_bbf[2]     = (~cmu_icache_invalidate_way[2] &  cmu_icache_invalidate_way[1] & ~cmu_icache_invalidate_way[0]) | inv_ack ; 
assign next_inv_way_bbf[3]     = (~cmu_icache_invalidate_way[2] &  cmu_icache_invalidate_way[1] &  cmu_icache_invalidate_way[0]) | inv_ack ; 
assign next_inv_way_bbf[4]     = ( cmu_icache_invalidate_way[2] & ~cmu_icache_invalidate_way[1] & ~cmu_icache_invalidate_way[0]) | inv_ack ; 
assign next_inv_way_bbf[5]     = ( cmu_icache_invalidate_way[2] & ~cmu_icache_invalidate_way[1] &  cmu_icache_invalidate_way[0]) | inv_ack ; 
assign next_inv_way_bbf[6]     = ( cmu_icache_invalidate_way[2] &  cmu_icache_invalidate_way[1] & ~cmu_icache_invalidate_way[0]) | inv_ack ; 
assign next_inv_way_bbf[7]     = ( cmu_icache_invalidate_way[2] &  cmu_icache_invalidate_way[1] &  cmu_icache_invalidate_way[0]) | inv_ack ; 

assign next_inv_way1_bbf[0]     = (~cmu_icache_inv_way1[2] & ~cmu_icache_inv_way1[1] & ~cmu_icache_inv_way1[0]) | inv_ack ; 
assign next_inv_way1_bbf[1]     = (~cmu_icache_inv_way1[2] & ~cmu_icache_inv_way1[1] &  cmu_icache_inv_way1[0]) | inv_ack ; 
assign next_inv_way1_bbf[2]     = (~cmu_icache_inv_way1[2] &  cmu_icache_inv_way1[1] & ~cmu_icache_inv_way1[0]) | inv_ack ; 
assign next_inv_way1_bbf[3]     = (~cmu_icache_inv_way1[2] &  cmu_icache_inv_way1[1] &  cmu_icache_inv_way1[0]) | inv_ack ; 
assign next_inv_way1_bbf[4]     = ( cmu_icache_inv_way1[2] & ~cmu_icache_inv_way1[1] & ~cmu_icache_inv_way1[0]) | inv_ack ; 
assign next_inv_way1_bbf[5]     = ( cmu_icache_inv_way1[2] & ~cmu_icache_inv_way1[1] &  cmu_icache_inv_way1[0]) | inv_ack ; 
assign next_inv_way1_bbf[6]     = ( cmu_icache_inv_way1[2] &  cmu_icache_inv_way1[1] & ~cmu_icache_inv_way1[0]) | inv_ack ; 
assign next_inv_way1_bbf[7]     = ( cmu_icache_inv_way1[2] &  cmu_icache_inv_way1[1] &  cmu_icache_inv_way1[0]) | inv_ack ; 

assign asi_way_dec_bf[0]       = ~asi_way_bf[2]  & ~asi_way_bf[1]  & ~asi_way_bf[0] ;
assign asi_way_dec_bf[1]       = ~asi_way_bf[2]  & ~asi_way_bf[1]  &  asi_way_bf[0] ;
assign asi_way_dec_bf[2]       = ~asi_way_bf[2]  &  asi_way_bf[1]  & ~asi_way_bf[0] ;
assign asi_way_dec_bf[3]       = ~asi_way_bf[2]  &  asi_way_bf[1]  &  asi_way_bf[0] ;
assign asi_way_dec_bf[4]       =  asi_way_bf[2]  & ~asi_way_bf[1]  & ~asi_way_bf[0] ;
assign asi_way_dec_bf[5]       =  asi_way_bf[2]  & ~asi_way_bf[1]  &  asi_way_bf[0] ;
assign asi_way_dec_bf[6]       =  asi_way_bf[2]  &  asi_way_bf[1]  & ~asi_way_bf[0] ;
assign asi_way_dec_bf[7]       =  asi_way_bf[2]  &  asi_way_bf[1]  &  asi_way_bf[0] ;

//////////////// Address staging /////////////////////////////////////////
ifu_ftu_agc_ctl_msff_ctl_macro__width_1 addr_bit_5_bf_reg  (
 .scan_in(addr_bit_5_bf_reg_scanin),
 .scan_out(addr_bit_5_bf_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (fill_paddr_bit_5),
 .dout (phys_addr_bit_5_bf),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 inv_bit_5_bf_reg  (
 .scan_in(inv_bit_5_bf_reg_scanin),
 .scan_out(inv_bit_5_bf_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (inv_paddr_bit_5),
 .dout (inv_addr_bit_5_bf),
  .siclk(siclk),
  .soclk(soclk));

assign  inv_or_phys_addr_bit_5_bf = ( agc_inv_line_bf & inv_addr_bit_5_bf) |
                                    (~agc_inv_line_bf & ftp_fill_req_q_bf & phys_addr_bit_5_bf) |
                                    (~agc_inv_line_bf & ftp_asi_tg_wr_req_hold  & asi_addr_bf[6] & ~ftp_fill_req_q_bf) ;  

//////////////// Write way staging /////////////////////////////////////////
ifu_ftu_agc_ctl_msff_ctl_macro__width_8 wrway_bf_reg  (
 .scan_in(wrway_bf_reg_scanin),
 .scan_out(wrway_bf_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_wrway_bbf[7:0]),
 .dout (wrway_bf[7:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 inv_way_bf_reg  (
 .scan_in(inv_way_bf_reg_scanin),
 .scan_out(inv_way_bf_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (next_inv_way_bbf[7:0]),
 .dout (inv_way_bf[7:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 inv_way1_bf_reg  (
 .scan_in(inv_way1_bf_reg_scanin),
 .scan_out(inv_way1_bf_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (next_inv_way1_bbf[7:0]),
 .dout (inv_way1_bf[7:0]),
  .siclk(siclk),
  .soclk(soclk));

assign  inv_or_wrway_bf[7:0] =      ({8{ agc_inv_line_bf  & ~ftp_fill_req_q_bf     }} &  inv_way_bf[7:0]) |
                                    ({8{~agc_inv_line_bf  &  ftp_fill_req_q_bf     }} & wrway_bf[7:0]) |
                                    ({8{~agc_inv_line_bf  & ~ftp_fill_req_q_bf & ftp_asi_tg_wr_req_hold}} & asi_way_dec_bf[7:0]) ;  

assign  way1_inv[7:0]        = agc_evic_line_bf ? inv_way1_bf[7:0] : 8'b0 ;

assign agc_icv_wren_bf[31:0]  = ({32{ inv_or_phys_addr_bit_5_bf & !mbi_run_bf}} &  {inv_or_wrway_bf[7:0],8'b0,inv_or_wrway_bf[7:0],8'b0}) |
                                ({32{~inv_or_phys_addr_bit_5_bf & !mbi_run_bf}} &  {way1_inv[7:0], inv_or_wrway_bf[7:0],way1_inv[7:0],inv_or_wrway_bf[7:0] }) |
                                ({32{ mbi_run_bf}}                &  32'hFFFFFFFF) ; 
//////////////// Invalidate staging /////////////////////////////////////////
assign next_inv_line = cmu_icache_invalidate | inv_ack ;
ifu_ftu_agc_ctl_msff_ctl_macro__width_1 inv_line_bf_reg  (
 .scan_in(inv_line_bf_reg_scanin),
 .scan_out(inv_line_bf_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (next_inv_line),
 .dout (agc_inv_line_bf),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 evic_line_bf_reg  (
 .scan_in(evic_line_bf_reg_scanin),
 .scan_out(evic_line_bf_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (cmu_evic_invalidate),
 .dout (agc_evic_line_bf),
  .siclk(siclk),
  .soclk(soclk));

assign icv_wrdata[1]  = ftp_fill_req_q_bf |
                        (asi_vl_arr_data[1] & ~agc_inv_line_bf  & ftp_asi_tg_wr_req_hold ) ;

assign icv_wrdata[0]  = ftp_fill_req_q_bf |
                        (asi_vl_arr_data[0] & ~agc_inv_line_bf  & ftp_asi_tg_wr_req_hold) ;

assign agc_icv_wrdata_bf[31:0] = mbi_run_bf ? {mbi_wdata_bf[7:0],mbi_wdata_bf[7:0],mbi_wdata_bf[7:0],mbi_wdata_bf[7:0]} : 
                                              {{8{icv_wrdata[0]}},{8{icv_wrdata[0]}},{8{icv_wrdata[1]}},{8{icv_wrdata[1]}}}  ;
assign agc_icv_wr_req_bf = (~mbi_run_bf & (ftp_fill_req_q_bf | agc_inv_line_bf | ftp_asi_tg_wr_req_hold)) |
                           ( mbi_run_bf &  mbi_icv_write_en_bf) ;
///////////////////////////////////////////////////////////
// Generate duplicate miss reset signal from WOB bits.   //
///////////////////////////////////////////////////////////
assign next_data_ready_bbf = cmu_any_data_ready & ~cmu_any_un_cacheable    ;
                       
ifu_ftu_agc_ctl_msff_ctl_macro__width_1 data_ready_bf_reg  (
 .scan_in(data_ready_bf_reg_scanin),
 .scan_out(data_ready_bf_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_data_ready_bbf),
 .dout (agc_data_ready_bf),
  .siclk(siclk),
  .soclk(soclk));


ifu_ftu_agc_ctl_msff_ctl_macro__width_5 l2_cache_miss_in_reg  (
 .scan_in(l2_cache_miss_in_reg_scanin),
 .scan_out(l2_cache_miss_in_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ({l1_miss_in,l2_miss_in,l2_err_corr_in,l2_err_ucorr_in,l2_err_ndata_in}),
 .dout ({l1_cache_1_miss,l2_cache_1_miss,l2_err_corr_1_ff,l2_err_ucorr_1_ff,l2_err_ndata_1_ff}),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_5 l2_cache_miss_1_reg  (
 .scan_in(l2_cache_miss_1_reg_scanin),
 .scan_out(l2_cache_miss_1_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ({l1_cache_1_miss,l2_cache_1_miss,l2_err_corr_1_ff,l2_err_ucorr_1_ff,l2_err_ndata_1_ff}),
 .dout ({l1_cache_2_miss,l2_cache_2_miss,l2_err_corr_2_ff,l2_err_ucorr_2_ff,l2_err_ndata_2_ff}),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_5 l2_cache_miss_2_reg  (
 .scan_in(l2_cache_miss_2_reg_scanin),
 .scan_out(l2_cache_miss_2_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ({l1_cache_2_miss,l2_cache_2_miss,l2_err_corr_2_ff,l2_err_ucorr_2_ff,l2_err_ndata_2_ff}),
 .dout ({l1_cache_3_miss,l2_cache_3_miss,l2_err_corr_3_ff,l2_err_ucorr_3_ff,l2_err_ndata_3_ff}),
  .siclk(siclk),
  .soclk(soclk));

assign precise_en_bp_in    =  (ceter_pscce_ff[0] & next_by_pass_sel_bbf[0]) | 
                              (ceter_pscce_ff[1] & next_by_pass_sel_bbf[1]) | 
                              (ceter_pscce_ff[2] & next_by_pass_sel_bbf[2]) | 
                              (ceter_pscce_ff[3] & next_by_pass_sel_bbf[3]) | 
                              (ceter_pscce_ff[4] & next_by_pass_sel_bbf[4]) | 
                              (ceter_pscce_ff[5] & next_by_pass_sel_bbf[5]) | 
                              (ceter_pscce_ff[6] & next_by_pass_sel_bbf[6]) | 
                              (ceter_pscce_ff[7] & next_by_pass_sel_bbf[7]) ; 

assign l2_err_corr_in      = ~cmu_l2_err[1] &  cmu_l2_err[0] & cerer_icl2c_ff;
assign l2_err_ucorr_in     =  cmu_l2_err[1] & ~cmu_l2_err[0] &  precise_en_bp_in & cerer_icl2u_ff;
assign l2_err_ndata_in     =  cmu_l2_err[1] &  cmu_l2_err[0] &  precise_en_bp_in & cerer_icl2nd_ff;
assign l2_miss_in          =  cmu_l2miss    & ~l2_err_corr_in & ~l2_err_ucorr_in & ~l2_err_ndata_in ;
assign l1_miss_in          = ~cmu_l2miss    & ~l2_err_corr_in & ~l2_err_ucorr_in & ~l2_err_ndata_in ; 

assign l2_ucorr_err_byp_1  =  agc_bypass_selects[0] & l2_err_ucorr_1_ff; 
assign l2_ucorr_err_byp_2  =  agc_bypass_selects[1] & l2_err_ucorr_2_ff; 
assign l2_ucorr_err_byp_3  =  agc_bypass_selects[2] & l2_err_ucorr_3_ff; 
assign l2_ucorr_err        =  l2_ucorr_err_byp_1 | l2_ucorr_err_byp_2 | l2_ucorr_err_byp_3 ;

assign l2_corr_err_byp_1  =  agc_bypass_selects[0] & l2_err_corr_1_ff; 
assign l2_corr_err_byp_2  =  agc_bypass_selects[1] & l2_err_corr_2_ff; 
assign l2_corr_err_byp_3  =  agc_bypass_selects[2] & l2_err_corr_3_ff; 
assign l2_corr_err        =  l2_corr_err_byp_1 | l2_corr_err_byp_2 | l2_corr_err_byp_3 ;

assign l2_ndata_err_byp_1  =  agc_bypass_selects[0] & l2_err_ndata_1_ff; 
assign l2_ndata_err_byp_2  =  agc_bypass_selects[1] & l2_err_ndata_2_ff; 
assign l2_ndata_err_byp_3  =  agc_bypass_selects[2] & l2_err_ndata_3_ff; 
assign l2_ndata_err        =  l2_ndata_err_byp_1 | l2_ndata_err_byp_2 | l2_ndata_err_byp_3 ;

assign l2_cache_miss_byp_1 = agc_bypass_selects[0] & l2_cache_1_miss;
assign l2_cache_miss_byp_2 = agc_bypass_selects[1] & l2_cache_2_miss ;
assign l2_cache_miss_byp_3 = agc_bypass_selects[2] & l2_cache_3_miss ;

assign l2_cache_miss = l2_cache_miss_byp_1   | l2_cache_miss_byp_2   | l2_cache_miss_byp_3 ;
assign l1_cache_miss = (agc_bypass_selects[0] & l1_cache_1_miss) |
                       (agc_bypass_selects[1] & l1_cache_2_miss) | 
                       (agc_bypass_selects[2] & l1_cache_3_miss) ;


/////////////////////////////////////////////////////////////////////////////
// Cache miss signals.                                                   //
///////////////////////////////////////////////////////////////////////////

assign itb_cmiss_c = ~itb_chit_c | agc_ic_disable_thr_c;
assign itb_itb_miss_c = ~itb_cam_hit_c;


assign agc_itb_cmiss_c_q     =  itb_cmiss_c & agc_fetch_v_c     & ~itb_itb_miss_c & ~ic_valid_err_no_priority & 
                               ~va_hole_excp_c & ~itb_itb_acc_viol_c & ~invalidation_req_c &  
                               ~(itb_tag_perr & cerer_ittp_ff) & ~(itb_tte_data_parity & agc_fetch_v_c_unq & cerer_itdp_ff) &
                                ~(agc_tag_perror_c & cerer_ictp_ff) & ~(tlb_nfo & itb_cam_hit_c) & ~itb_mhit_en_c; 

assign agc_qualify_cmiss     = ~itb_itb_miss_c & ~ic_valid_err_no_priority & ~va_hole_excp_c & ~itb_itb_acc_viol_c  & ~invalidation_req_c &
                                ~(itb_tag_perr & cerer_ittp_ff)  & 
                                ~(itb_tte_data_parity & agc_fetch_v_c_unq & cerer_itdp_ff) & 
                                ~(agc_tag_perror_c & cerer_ictp_ff) & ~(tlb_nfo & itb_cam_hit_c) & ~itb_mhit_en_c;  


assign agc_thr0_micro_flush_unq_c =  (itb_cmiss_c | invalidation_req_c) & 
                                      curr_fetch_thr_c[0]  & agc_fetch_v_int_c ; 
assign agc_thr1_micro_flush_unq_c =  (itb_cmiss_c | invalidation_req_c) & 
                                      curr_fetch_thr_c[1]  & agc_fetch_v_int_c; 
assign agc_thr2_micro_flush_unq_c =  (itb_cmiss_c | invalidation_req_c) & 
                                      curr_fetch_thr_c[2]  & agc_fetch_v_int_c; 
assign agc_thr3_micro_flush_unq_c =  (itb_cmiss_c | invalidation_req_c) & 
                                      curr_fetch_thr_c[3]  & agc_fetch_v_int_c; 
assign agc_thr4_micro_flush_unq_c =  (itb_cmiss_c | invalidation_req_c) & 
                                      curr_fetch_thr_c[4]  & agc_fetch_v_int_c; 
assign agc_thr5_micro_flush_unq_c =  (itb_cmiss_c | invalidation_req_c) & 
                                      curr_fetch_thr_c[5]  & agc_fetch_v_int_c; 
assign agc_thr6_micro_flush_unq_c =  (itb_cmiss_c | invalidation_req_c) & 
                                      curr_fetch_thr_c[6]  & agc_fetch_v_int_c; 
assign agc_thr7_micro_flush_unq_c =  (itb_cmiss_c | invalidation_req_c) & 
                                      curr_fetch_thr_c[7]  & agc_fetch_v_int_c; 

assign thr0_replay_pc   = (itb_cmiss_c | invalidation_req_c) & curr_fetch_thr_c[0]  & agc_fetch_v_int_c ; 
assign thr1_replay_pc   = (itb_cmiss_c | invalidation_req_c) & curr_fetch_thr_c[1]  & agc_fetch_v_int_c ; 
assign thr2_replay_pc   = (itb_cmiss_c | invalidation_req_c) & curr_fetch_thr_c[2]  & agc_fetch_v_int_c ; 
assign thr3_replay_pc   = (itb_cmiss_c | invalidation_req_c) & curr_fetch_thr_c[3]  & agc_fetch_v_int_c ; 
assign thr4_replay_pc   = (itb_cmiss_c | invalidation_req_c) & curr_fetch_thr_c[4]  & agc_fetch_v_int_c ; 
assign thr5_replay_pc   = (itb_cmiss_c | invalidation_req_c) & curr_fetch_thr_c[5]  & agc_fetch_v_int_c ; 
assign thr6_replay_pc   = (itb_cmiss_c | invalidation_req_c) & curr_fetch_thr_c[6]  & agc_fetch_v_int_c ; 
assign thr7_replay_pc   = (itb_cmiss_c | invalidation_req_c) & curr_fetch_thr_c[7]  & agc_fetch_v_int_c ; 

assign agc_thr0_reset_sf_c = agc_thr0_micro_flush_unq_c ; 
assign agc_thr1_reset_sf_c = agc_thr1_micro_flush_unq_c ; 
assign agc_thr2_reset_sf_c = agc_thr2_micro_flush_unq_c ; 
assign agc_thr3_reset_sf_c = agc_thr3_micro_flush_unq_c ; 
assign agc_thr4_reset_sf_c = agc_thr4_micro_flush_unq_c ; 
assign agc_thr5_reset_sf_c = agc_thr5_micro_flush_unq_c ; 
assign agc_thr6_reset_sf_c = agc_thr6_micro_flush_unq_c ; 
assign agc_thr7_reset_sf_c = agc_thr7_micro_flush_unq_c ; 


assign agc_thr0_cmiss_stm_c = agc_itb_cmiss_c_q & curr_fetch_thr_c[0] & ~redirect_ibu_int_bf[0]; 
assign agc_thr1_cmiss_stm_c = agc_itb_cmiss_c_q & curr_fetch_thr_c[1] & ~redirect_ibu_int_bf[1]; 
assign agc_thr2_cmiss_stm_c = agc_itb_cmiss_c_q & curr_fetch_thr_c[2] & ~redirect_ibu_int_bf[2]; 
assign agc_thr3_cmiss_stm_c = agc_itb_cmiss_c_q & curr_fetch_thr_c[3] & ~redirect_ibu_int_bf[3]; 
assign agc_thr4_cmiss_stm_c = agc_itb_cmiss_c_q & curr_fetch_thr_c[4] & ~redirect_ibu_int_bf[4]; 
assign agc_thr5_cmiss_stm_c = agc_itb_cmiss_c_q & curr_fetch_thr_c[5] & ~redirect_ibu_int_bf[5]; 
assign agc_thr6_cmiss_stm_c = agc_itb_cmiss_c_q & curr_fetch_thr_c[6] & ~redirect_ibu_int_bf[6]; 
assign agc_thr7_cmiss_stm_c = agc_itb_cmiss_c_q & curr_fetch_thr_c[7] & ~redirect_ibu_int_bf[7]; 

assign thr0_unc_is_valid    = agc_thr0_cmiss_stm_c & agc_thrx_un_cacheable ;
assign thr1_unc_is_valid    = agc_thr1_cmiss_stm_c & agc_thrx_un_cacheable ;
assign thr2_unc_is_valid    = agc_thr2_cmiss_stm_c & agc_thrx_un_cacheable ;
assign thr3_unc_is_valid    = agc_thr3_cmiss_stm_c & agc_thrx_un_cacheable ;
assign thr4_unc_is_valid    = agc_thr4_cmiss_stm_c & agc_thrx_un_cacheable ;
assign thr5_unc_is_valid    = agc_thr5_cmiss_stm_c & agc_thrx_un_cacheable ;
assign thr6_unc_is_valid    = agc_thr6_cmiss_stm_c & agc_thrx_un_cacheable ;
assign thr7_unc_is_valid    = agc_thr7_cmiss_stm_c & agc_thrx_un_cacheable ;


///////////////////////////////////////////////////////////////////////
// Generate which instructions are valid and to be sent to the IB.   //
///////////////////////////////////////////////////////////////////////
assign bus_0_valid_f = (~ifu_agd_pc_f[4] &  ifu_agd_pc_f[3] & ~instr_sf_valid_f & ~invalidation_req_f)  |
                     (~ifu_agd_pc_f[4] & ~ifu_agd_pc_f[3] &  ifu_agd_pc_f[2] & ~instr_sf_valid_f & ~invalidation_req_f)  |
                     (~ifu_agd_pc_f[3] & ~ifu_agd_pc_f[2] & ~invalidation_req_f) ;

assign bus_1_valid_f = (~ifu_agd_pc_f[3] &  ifu_agd_pc_f[2] & ~invalidation_req_f)  |
                     (~ifu_agd_pc_f[3] & ~ifu_agd_pc_f[2] & ~instr_sf_valid_f & ~invalidation_req_f)  |
                     (~ifu_agd_pc_f[4] &  ifu_agd_pc_f[3] & ~instr_sf_valid_f & ~invalidation_req_f) ;

assign bus_2_valid_f = ( ifu_agd_pc_f[3] & ~ifu_agd_pc_f[2] & ~invalidation_req_f)  |
                     (~ifu_agd_pc_f[3] &  ifu_agd_pc_f[2] & ~instr_sf_valid_f & ~invalidation_req_f) |
                     (~ifu_agd_pc_f[3] & ~ifu_agd_pc_f[2] & ~instr_sf_valid_f & ~invalidation_req_f) |
                     (~ifu_agd_pc_f[4] &  ifu_agd_pc_f[2] & ~instr_sf_valid_f & ~invalidation_req_f) ;

assign bus_3_valid_f = ( ifu_agd_pc_f[3] &  ifu_agd_pc_f[2]  & ~invalidation_req_f) |
                     ( ifu_agd_pc_f[3] & ~ifu_agd_pc_f[2] & ~instr_sf_valid_f & ~invalidation_req_f) |
                     (~ifu_agd_pc_f[3] &  ifu_agd_pc_f[2] & ~instr_sf_valid_f & ~invalidation_req_f) |
                     (~ifu_agd_pc_f[3] & ~ifu_agd_pc_f[2] & ~instr_sf_valid_f & ~invalidation_req_f) ;


ifu_ftu_agc_ctl_msff_ctl_macro__width_4 ic_instr_v_reg  (
 .scan_in(ic_instr_v_reg_scanin),
 .scan_out(ic_instr_v_reg_scanout),
 .l1clk( l1clk_pm1 ),
 .din  ({bus_3_valid_f,bus_2_valid_f,bus_1_valid_f,bus_0_valid_f}),
 .dout ({bus_3_valid_c,bus_2_valid_c,bus_1_valid_c,bus_0_valid_c}),
  .siclk(siclk),
  .soclk(soclk));

assign next_any_instr_v_c = bus_3_valid_f | bus_2_valid_f | bus_1_valid_f | bus_0_valid_f ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 any_instr_v_c_reg  (
 .scan_in(any_instr_v_c_reg_scanin),
 .scan_out(any_instr_v_c_reg_scanout),
 .l1clk( l1clk_pm1 ),
 .din  (next_any_instr_v_c),
 .dout (any_instr_v_c),
  .siclk(siclk),
  .soclk(soclk));

assign any_instr_v_q_c =  any_instr_v_c & ~itb_cmiss_c & agc_fetch_v_c ;

assign agc_itb_itb_miss_c_q        = itb_itb_miss_c & agc_fetch_v_c_dup_unq & ~va_hole_excp_c & ~invalidation_req_c;
assign agc_itb_itb_miss_c_int_q    = itb_itb_miss_c & agc_fetch_v_int_c     & ~va_hole_excp_c & ~invalidation_req_c;

assign exception_valid_c            = agc_itb_itb_miss_c_q          | ((itb_itb_acc_viol_no_priority   | va_hole_exception_c  | 
                                      nfo_tlb_exception_no_priority | tag_perror_no_priority           | itb_mhit_no_priority | 
                                      tte_tag_parity_no_priority    | ic_valid_err_no_priority         | tag_multiple_hit_no_priority | 
                                      tte_data_parity_no_priority   ) & agc_fetch_v_c_dup_unq ); 

assign ftu_exception_valid_c        = agc_itb_itb_miss_c_q          | ((itb_itb_acc_viol_no_priority   | va_hole_exception_c  | 
                                      nfo_tlb_exception_no_priority | tag_perror_no_priority           | itb_mhit_no_priority | 
                                      tte_tag_parity_no_priority    | ic_valid_err_no_priority         | tag_multiple_hit_no_priority | 
                                      tte_data_parity_no_priority   ) & agc_fetch_v_c_dup_unq ); 
assign exception_valid_int_c    = agc_itb_itb_miss_c_int_q | itb_itb_acc_viol_int_c | va_hole_exception_int_c; 

assign instr_3_v_q_c = (bus_3_valid_c & ~itb_cmiss_c & agc_fetch_v_c) ;  
assign instr_2_v_q_c = (bus_2_valid_c & ~itb_cmiss_c & agc_fetch_v_c) ;  
assign instr_1_v_q_c = (bus_1_valid_c & ~itb_cmiss_c & agc_fetch_v_c) ; 
assign instr_0_v_q_c = (bus_0_valid_c & ~itb_cmiss_c & agc_fetch_v_c) ; 

ifu_ftu_agc_ctl_msff_ctl_macro__width_16 hpstate_reg  (
 .scan_in(hpstate_reg_scanin),
 .scan_out(hpstate_reg_scanout),
 .l1clk( l1clk ),
 .din  ({tlu_ifu_hpstate_hpriv[7:0], tlu_ifu_pstate_priv[7:0]}),
 .dout ({hpstate_hpriv_ff[7:0], pstate_priv_ff[7:0]}),
  .siclk(siclk),
  .soclk(soclk));

assign next_priv_state = ftp_fetch_v_f & ( 
                  (ftp_curr_fetch_thr_f[0] & (hpstate_hpriv_ff[0] | pstate_priv_ff[0])) |   
                  (ftp_curr_fetch_thr_f[1] & (hpstate_hpriv_ff[1] | pstate_priv_ff[1])) |   
                  (ftp_curr_fetch_thr_f[2] & (hpstate_hpriv_ff[2] | pstate_priv_ff[2])) |   
                  (ftp_curr_fetch_thr_f[3] & (hpstate_hpriv_ff[3] | pstate_priv_ff[3])) |   
                  (ftp_curr_fetch_thr_f[4] & (hpstate_hpriv_ff[4] | pstate_priv_ff[4])) |   
                  (ftp_curr_fetch_thr_f[5] & (hpstate_hpriv_ff[5] | pstate_priv_ff[5])) |   
                  (ftp_curr_fetch_thr_f[6] & (hpstate_hpriv_ff[6] | pstate_priv_ff[6])) |   
                  (ftp_curr_fetch_thr_f[7] & (hpstate_hpriv_ff[7] | pstate_priv_ff[7])) )  ;  

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 priv_state_c_reg  (
 .scan_in(priv_state_c_reg_scanin),
 .scan_out(priv_state_c_reg_scanout),
 .l1clk( l1clk_pm1 ),
 .din  (next_priv_state),
 .dout (agc_priv_state_c),
  .siclk(siclk),
  .soclk(soclk));


///////////////////////////////////////////////////////////////////////
ifu_ftu_agc_ctl_msff_ctl_macro__width_6 tlb_parity_reg  (
 .scan_in(tlb_parity_reg_scanin),
 .scan_out(tlb_parity_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({itd_prty_256m,itd_prty_4m,itd_prty_64k,itd_prty_8k, itd_prty_ctxt0,itd_prty_ctxt1}),
 .dout ({prty_256m_c,prty_4m_c,prty_64k_c,prty_8k_c, prty_ctxt0_c,prty_ctxt1_c}),
  .siclk(siclk),
  .soclk(soclk)) ;


///////////////////////
// TLB errors
// Code from LSU
// 
// Resolve TLB tag parity error here.  Select the proper parity bit based
// on the page size and compare it to the stored parity.
// 
 assign prty_ctxt = tlb_context0_hit ? prty_ctxt0_c : prty_ctxt1_c;
 
 assign tag_parity_gen = (( tlb_pgsize[2] &                               prty_256m_c) |
                      (~tlb_pgsize[2] &  tlb_pgsize[1] &                  prty_4m_c) |
                      (~tlb_pgsize[2] & ~tlb_pgsize[1] &  tlb_pgsize[0] & prty_64k_c) |
                      (~tlb_pgsize[2] & ~tlb_pgsize[1] & ~tlb_pgsize[0] & prty_8k_c)) ^
                     ( prty_ctxt & ~agc_itc_real_c);
 
 
ifu_ftu_agc_ctl_msff_ctl_macro__width_1 itlb_cam_vld_c_reg  (
 .scan_in(itlb_cam_vld_c_reg_scanin),
 .scan_out(itlb_cam_vld_c_reg_scanout),
 .l1clk( l1clk_pm1 ),
 .din  (ftp_itlb_cam_vld_f),
 .dout (itlb_cam_vld_c),
  .siclk(siclk),
  .soclk(soclk));

 
/////////////////////////////////////////////////////////////////
// no exception                  = 00000                       //
// tlb_miss (non-real)           = 00001                       //
// tlb_access_violation          = 00010                       //
// VA hole exception             = 00011                       //
// tlb real miss                 = 00100                       //
// L2 MISS (for PMU)             = 00101                       //
// IC MISS (for PMU)             = 00110                       // 
// ITLB tag parity error         = 00111                       //
// ITLB data parity error        = 11111                       //
// ITLB multiple hit             = 01001                       //
// icache valid (parity error)   = 01010                       //
// icache tag parity error       = 01011                       //
// icache tag multiple hit       = 01100                       //
// icache L2 correctable error   = 01110                       //
// icache L2 uncorrectable error = 01111                       //
// icache L2 NotData error       = 10000                       //
// ITLB NFO excp                 = 10001                       //
// Real VA hole exception        = 10011                       //
/////////////////////////////////////////////////////////////////
// New codes added for fetching from I/O space that is not     //
// boot-rom area. Also added code points for l2_miss and errors//
// together to more accurately count l2_miss in PMU.           //
// The new codes were chosen in such a way to minimize         //
// changes to existing testbenches and testcases.              //
// not boot rom fetch            = 10100 (Not-taken)           //
// L2 miss and correctable error = 11110                       //
// L2 miss and uncorrectable err = 10111                       //
// L2 miss and Notdata error     = 11000                       //
/////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////
ifu_ftu_agc_ctl_msff_ctl_macro__width_9 cerer_en_reg  (
 .scan_in(cerer_en_reg_scanin),
 .scan_out(cerer_en_reg_scanout),
 .l1clk( l1clk ),
 .din  ({tlu_cerer_ittp  ,tlu_cerer_itdp,tlu_cerer_ittm,tlu_cerer_icl2c,tlu_cerer_icl2u,
         tlu_cerer_icl2nd,tlu_cerer_icvp,tlu_cerer_ictp,tlu_cerer_ictm }),
 .dout ({cerer_ittp_ff  ,cerer_itdp_ff,cerer_ittm_ff,cerer_icl2c_ff,cerer_icl2u_ff,
         cerer_icl2nd_ff,cerer_icvp_ff,cerer_ictp_ff,cerer_ictm_ff }),
  .siclk(siclk),
  .soclk(soclk));

assign agc_itb_tag_perr_c   = itlb_cam_vld_c & (tag_parity_gen  ^ itb_tte_tag_parity) & agc_fetch_v_c_unq;
assign itb_tag_perr         = itlb_cam_vld_c & (tag_parity_gen  ^ itb_tte_tag_parity) & agc_fetch_v_c_unq;

/// Exception generation ////////////////////////////////////////////////////////
assign itb_mhit_en_c           = itb_itb_mhit_c      & cerer_ittm_ff          & ~va_hole_exception_c &  agc_fetch_v_c_dup_unq & 
                                 ~invalidation_req_c ;
assign tte_tag_parity_en_c     = itb_tag_perr        & cerer_ittp_ff          & ~itb_itb_miss_c      & ~itb_mhit_en_c & 
                                 ~va_hole_exception_c & agc_fetch_v_c_dup_unq & ~invalidation_req_c ; 
assign tte_data_parity_en_c    = itb_tte_data_parity & cerer_itdp_ff          & ~tte_tag_parity_en_c & ~itb_mhit_en_c & 
                                 agc_fetch_v_c_unq   & itb_cam_hit_c          & ~va_hole_exception_c  & ~invalidation_req_c ;
assign itb_itb_acc_viol_c      = itb_tte_p_c         & agc_fetch_v_c_dup_unq  & ~agc_priv_state_c    & ~itb_itb_miss_c & 
                                ~invalidation_req_c  & ~va_hole_excp_c        & ~itb_mhit_en_c       & ~tte_tag_parity_en_c ; 
assign itb_itb_acc_viol_int_c  = itb_tte_p_c         & agc_fetch_v_int_c      & ~agc_priv_state_c    & ~itb_itb_miss_c & 
                                ~invalidation_req_c  & ~va_hole_excp_c        & ~itb_mhit_en_c       & ~tte_tag_parity_en_c ; 
assign nfo_tlb_exception       = tlb_nfo             & itb_cam_hit_c          & agc_fetch_v_c_dup_unq &  
                                ~invalidation_req_c  & ~va_hole_excp_c        & ~(itb_tte_p_c        & ~agc_priv_state_c) & 
                                ~itb_mhit_en_c       & ~tte_tag_parity_en_c   ;
assign ic_valid_err_c_en       = ic_valid_err_c      & cerer_icvp_ff          & ~invalidation_req_c  & agc_fetch_v_c_unq  & ~va_hole_exception_c  &
                                ~itb_mhit_en_c       & ~tte_tag_parity_en_c   & ~itb_itb_acc_viol_c  & 
                                ~nfo_tlb_exception   & itb_cam_hit_c         ;
assign tag_perror_en_c         = agc_tag_perror_c    & cerer_ictp_ff          & ~invalidation_req_c  &  agc_fetch_v_c_unq    & 
                                ~va_hole_exception_c & ~ic_valid_err_c_en     & ~itb_mhit_en_c       & ~tte_tag_parity_en_c  & 
                                ~itb_itb_acc_viol_c  & ~nfo_tlb_exception     &  itb_cam_hit_c       ;
assign tag_multiple_hit_en     = ic_tag_multiple_hit & cerer_ictm_ff          & ~invalidation_req_c  & agc_fetch_v_c_unq     & 
                                ~ic_valid_err_c_en   & ~va_hole_exception_c   & ~tag_perror_en_c     & agc_ic_enable_thr_c   &
                                ~itb_mhit_en_c       & ~tte_tag_parity_en_c   & ~itb_itb_acc_viol_c  & ~nfo_tlb_exception    & itb_cam_hit_c ;
assign l2_ucorr_err_en         = l2_ucorr_err        & cerer_icl2u_ff  ;
assign l2_corr_err_en          = l2_corr_err         & cerer_icl2c_ff  ;
assign l2_ndata_err_en         = l2_ndata_err        & cerer_icl2nd_ff ;

assign ftu_ic_no_err_c                = l2_ucorr_err_en | l2_ndata_err_en | agc_fetch_v_c_dup_unq;

assign l2_cache_miss_no_error      = l2_cache_miss & ~l2_ucorr_err_en & ~l2_corr_err_en & ~l2_ndata_err_en ;
assign l2_uncorr_err_en_no_l2_miss = l2_ucorr_err  &  cerer_icl2u_ff  & ~l2_cache_miss ; 

assign l2_cache_miss_n_corr        = l2_cache_miss &  l2_corr_err_en ;
assign l2_cache_miss_n_uncorr      = l2_cache_miss &  l2_ucorr_err_en ;
assign l2_cache_miss_n_ndata       = l2_cache_miss &  l2_ndata_err_en ;

// NFO is lower priority than access (privilege violation)

assign ftu_instr_exceptions_c[0] = (agc_itb_itb_miss_c_q & ~agc_itc_real_c_q) | va_hole_exception_c | l2_cache_miss_no_error      | tte_tag_parity_en_c |
                                     itb_mhit_en_c        | tag_perror_en_c     | l2_ucorr_err_en   | nfo_tlb_exception |
                                     tte_data_parity_en_c ; 

assign ftu_instr_exceptions_c[1] = itb_itb_acc_viol_c   | va_hole_exception_c | l1_cache_miss      | tte_tag_parity_en_c |
                                   ic_valid_err_c_en    | tag_perror_en_c     | l2_corr_err_en     | l2_ucorr_err_en     |
                                   tte_data_parity_en_c   ; 

assign ftu_instr_exceptions_c[2] = agc_itc_real_c_q     | l2_cache_miss_no_error      | l1_cache_miss     | tte_tag_parity_en_c  |
                                   tag_multiple_hit_en  | l2_corr_err_en     | l2_ucorr_err_en   | 
                                   tte_data_parity_en_c  ; 

assign ftu_instr_exceptions_c[3] = tte_data_parity_en_c  | itb_mhit_en_c    | ic_valid_err_c_en     | tag_perror_en_c | 
                                   tag_multiple_hit_en   | l2_corr_err_en   | l2_uncorr_err_en_no_l2_miss       | 
                                   tag_perror_en_c       | l2_cache_miss_n_ndata ;  
 
assign ftu_instr_exceptions_c[4] =  tte_data_parity_en_c | l2_ndata_err_en  | nfo_tlb_exception | va_hole_exception_c_r | 
                                    l2_cache_miss_n_uncorr | l2_cache_miss_n_corr ; 


//////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////

assign way_sel_all_but_0   = |itb_icd_waysel_c[7:1] ;
assign way_sel_all_but_1   = (|itb_icd_waysel_c[7:2]) | itb_icd_waysel_c[0] ;
assign way_sel_all_but_2   = (|itb_icd_waysel_c[7:3]) | (|itb_icd_waysel_c[1:0]) ;
assign way_sel_all_but_3   = (|itb_icd_waysel_c[7:4]) | (|itb_icd_waysel_c[2:0]) ;
assign way_sel_all_but_4   = (|itb_icd_waysel_c[7:5]) | (|itb_icd_waysel_c[3:0]) ;
assign way_sel_all_but_5   = (|itb_icd_waysel_c[7:6]) | (|itb_icd_waysel_c[4:0]) ;
assign way_sel_all_but_6   =  itb_icd_waysel_c[7]     | (|itb_icd_waysel_c[5:0]) ;
assign way_sel_all_but_7   = |itb_icd_waysel_c[6:0] ;

assign ic_tag_multiple_hit = (itb_icd_waysel_c[0] & way_sel_all_but_0) |
                             (itb_icd_waysel_c[1] & way_sel_all_but_1) |
                             (itb_icd_waysel_c[2] & way_sel_all_but_2) |
                             (itb_icd_waysel_c[3] & way_sel_all_but_3) |
                             (itb_icd_waysel_c[4] & way_sel_all_but_4) |
                             (itb_icd_waysel_c[5] & way_sel_all_but_5) |
                             (itb_icd_waysel_c[6] & way_sel_all_but_6) |
                             (itb_icd_waysel_c[7] & way_sel_all_but_7) ;

assign va_hole_exception_c     = va_hole_excp_c & agc_fetch_v_c_dup_unq & ~invalidation_req_c ;
assign va_hole_exception_int_c = va_hole_excp_c & agc_fetch_v_int_c     & ~invalidation_req_c;

/////////////////////////////////////////////////////////////////
// TLB_MISS per thread
/////////////////////////////////////////////////////////////////
assign agc_thr0_itb_miss_c = agc_itb_itb_miss_c_q & curr_fetch_thr_c[0] & ~redirect_ibu_int_bf[0] ; 
assign agc_thr1_itb_miss_c = agc_itb_itb_miss_c_q & curr_fetch_thr_c[1] & ~redirect_ibu_int_bf[1] ; 
assign agc_thr2_itb_miss_c = agc_itb_itb_miss_c_q & curr_fetch_thr_c[2] & ~redirect_ibu_int_bf[2] ; 
assign agc_thr3_itb_miss_c = agc_itb_itb_miss_c_q & curr_fetch_thr_c[3] & ~redirect_ibu_int_bf[3] ; 
assign agc_thr4_itb_miss_c = agc_itb_itb_miss_c_q & curr_fetch_thr_c[4] & ~redirect_ibu_int_bf[4] ; 
assign agc_thr5_itb_miss_c = agc_itb_itb_miss_c_q & curr_fetch_thr_c[5] & ~redirect_ibu_int_bf[5] ; 
assign agc_thr6_itb_miss_c = agc_itb_itb_miss_c_q & curr_fetch_thr_c[6] & ~redirect_ibu_int_bf[6] ; 
assign agc_thr7_itb_miss_c = agc_itb_itb_miss_c_q & curr_fetch_thr_c[7] & ~redirect_ibu_int_bf[7] ; 

ifu_ftu_agc_ctl_msff_ctl_macro__width_2 itc_real_f_reg  (
 .scan_in(itc_real_f_reg_scanin),
 .scan_out(itc_real_f_reg_scanout),
 .l1clk( l1clk_pm1 ),
 .din  ({itc_real_bf,itc_bypass_bf}),
 .dout ({agc_itc_real_f,agc_itb_bypass_f}),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 itc_real_c_reg  (
 .scan_in(itc_real_c_reg_scanin),
 .scan_out(itc_real_c_reg_scanout),
 .l1clk( l1clk_pm1 ),
 .din  (agc_itc_real_f),
 .dout (agc_itc_real_c),
  .siclk(siclk),
  .soclk(soclk));

assign agc_itc_real_c_q = agc_itc_real_c & agc_fetch_v_c & agc_itb_itb_miss_c_q ;
assign va_hole_exception_c_r = va_hole_exception_c & agc_itc_real_c  ;


assign agc_sel_inv_index[0] = ~agc_inv_line_bf & ftp_fill_req_q_bf & ~mbi_run_bf; 
assign agc_sel_inv_index[1] =  agc_inv_line_bf & ~mbi_run_bf & ~ftp_fill_req_q_bf; 
assign agc_sel_inv_index[2] =  ~agc_inv_line_bf & ftp_asi_tg_wr_req_hold & ~mbi_run_bf & ~ftp_fill_req_q_bf;
assign agc_sel_inv_index[3] =  mbi_run_bf ; 

assign agc_thr0_cntx_0_sel[0] = lsu_ifu_wr_p0ctxt & (lsu_ifu_tid_w[2:0] == 3'b000);
assign agc_thr0_cntx_0_sel[1] = ~agc_thr0_cntx_0_sel[0] ; 
assign agc_thr1_cntx_0_sel[0] = lsu_ifu_wr_p0ctxt & (lsu_ifu_tid_w[2:0] == 3'b001);
assign agc_thr1_cntx_0_sel[1] = ~agc_thr1_cntx_0_sel[0] ; 
assign agc_thr2_cntx_0_sel[0] = lsu_ifu_wr_p0ctxt & (lsu_ifu_tid_w[2:0] == 3'b010);
assign agc_thr2_cntx_0_sel[1] = ~agc_thr2_cntx_0_sel[0] ; 
assign agc_thr3_cntx_0_sel[0] = lsu_ifu_wr_p0ctxt & (lsu_ifu_tid_w[2:0] == 3'b011);
assign agc_thr3_cntx_0_sel[1] = ~agc_thr3_cntx_0_sel[0] ; 
assign agc_thr4_cntx_0_sel[0] = lsu_ifu_wr_p0ctxt & (lsu_ifu_tid_w[2:0] == 3'b100);
assign agc_thr4_cntx_0_sel[1] = ~agc_thr4_cntx_0_sel[0] ; 
assign agc_thr5_cntx_0_sel[0] = lsu_ifu_wr_p0ctxt & (lsu_ifu_tid_w[2:0] == 3'b101);
assign agc_thr5_cntx_0_sel[1] = ~agc_thr5_cntx_0_sel[0] ; 
assign agc_thr6_cntx_0_sel[0] = lsu_ifu_wr_p0ctxt & (lsu_ifu_tid_w[2:0] == 3'b110);
assign agc_thr6_cntx_0_sel[1] = ~agc_thr6_cntx_0_sel[0] ; 
assign agc_thr7_cntx_0_sel[0] = lsu_ifu_wr_p0ctxt & (lsu_ifu_tid_w[2:0] == 3'b111);
assign agc_thr7_cntx_0_sel[1] = ~agc_thr7_cntx_0_sel[0] ; 

assign agc_thr0_cntx_1_sel[0] = lsu_ifu_wr_p1ctxt & (lsu_ifu_tid_w[2:0] == 3'b000);
assign agc_thr0_cntx_1_sel[1] = ~agc_thr0_cntx_1_sel[0] ; 
assign agc_thr1_cntx_1_sel[0] = lsu_ifu_wr_p1ctxt & (lsu_ifu_tid_w[2:0] == 3'b001);
assign agc_thr1_cntx_1_sel[1] = ~agc_thr1_cntx_1_sel[0] ; 
assign agc_thr2_cntx_1_sel[0] = lsu_ifu_wr_p1ctxt & (lsu_ifu_tid_w[2:0] == 3'b010);
assign agc_thr2_cntx_1_sel[1] = ~agc_thr2_cntx_1_sel[0] ; 
assign agc_thr3_cntx_1_sel[0] = lsu_ifu_wr_p1ctxt & (lsu_ifu_tid_w[2:0] == 3'b011);
assign agc_thr3_cntx_1_sel[1] = ~agc_thr3_cntx_1_sel[0] ; 
assign agc_thr4_cntx_1_sel[0] = lsu_ifu_wr_p1ctxt & (lsu_ifu_tid_w[2:0] == 3'b100);
assign agc_thr4_cntx_1_sel[1] = ~agc_thr4_cntx_1_sel[0] ; 
assign agc_thr5_cntx_1_sel[0] = lsu_ifu_wr_p1ctxt & (lsu_ifu_tid_w[2:0] == 3'b101);
assign agc_thr5_cntx_1_sel[1] = ~agc_thr5_cntx_1_sel[0] ; 
assign agc_thr6_cntx_1_sel[0] = lsu_ifu_wr_p1ctxt & (lsu_ifu_tid_w[2:0] == 3'b110);
assign agc_thr6_cntx_1_sel[1] = ~agc_thr6_cntx_1_sel[0] ; 
assign agc_thr7_cntx_1_sel[0] = lsu_ifu_wr_p1ctxt & (lsu_ifu_tid_w[2:0] == 3'b111);
assign agc_thr7_cntx_1_sel[1] = ~agc_thr7_cntx_1_sel[0] ; 

ifu_ftu_agc_ctl_msff_ctl_macro__width_16 cntx_sel_reg  (
 .scan_in(cntx_sel_reg_scanin),
 .scan_out(cntx_sel_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({agc_thr0_cntx_0_sel[0], agc_thr0_cntx_1_sel[0],
         agc_thr1_cntx_0_sel[0], agc_thr1_cntx_1_sel[0],
         agc_thr2_cntx_0_sel[0], agc_thr2_cntx_1_sel[0],
         agc_thr3_cntx_0_sel[0], agc_thr3_cntx_1_sel[0],
         agc_thr4_cntx_0_sel[0], agc_thr4_cntx_1_sel[0],
         agc_thr5_cntx_0_sel[0], agc_thr5_cntx_1_sel[0],
         agc_thr6_cntx_0_sel[0], agc_thr6_cntx_1_sel[0],
         agc_thr7_cntx_0_sel[0], agc_thr7_cntx_1_sel[0]}),

 .dout ({agc_thr0_cntx_0_sel_ff, agc_thr0_cntx_1_sel_ff,
         agc_thr1_cntx_0_sel_ff, agc_thr1_cntx_1_sel_ff,
         agc_thr2_cntx_0_sel_ff, agc_thr2_cntx_1_sel_ff,
         agc_thr3_cntx_0_sel_ff, agc_thr3_cntx_1_sel_ff,
         agc_thr4_cntx_0_sel_ff, agc_thr4_cntx_1_sel_ff,
         agc_thr5_cntx_0_sel_ff, agc_thr5_cntx_1_sel_ff,
         agc_thr6_cntx_0_sel_ff, agc_thr6_cntx_1_sel_ff,
         agc_thr7_cntx_0_sel_ff, agc_thr7_cntx_1_sel_ff}),
  .siclk(siclk),
  .soclk(soclk));


assign agc_thrx_un_cacheable = ftu_paddr_unq_39  ; 

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 lsu_no_icm_reg  (
 .scan_in(lsu_no_icm_reg_scanin),
 .scan_out(lsu_no_icm_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (lsu_ifu_no_miss[7:0]),
 .dout ({agc_thr7_lsu_no_ic_miss,agc_thr6_lsu_no_ic_miss,agc_thr5_lsu_no_ic_miss,agc_thr4_lsu_no_ic_miss,
         agc_thr3_lsu_no_ic_miss,agc_thr2_lsu_no_ic_miss,agc_thr1_lsu_no_ic_miss,agc_thr0_lsu_no_ic_miss}),
  .siclk(siclk),
  .soclk(soclk));


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 ic_enable_reg  (
 .scan_in(ic_enable_reg_scanin),
 .scan_out(ic_enable_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (lsu_ic_enable[7:0]),
 .dout (agc_icache_enable[7:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

assign next_ic_enable_thr_c =  |(agc_icache_enable[7:0] & ftp_curr_fetch_thr_f[7:0] ) ; 

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 thr_c_ic_enable_reg  (
 .scan_in(thr_c_ic_enable_reg_scanin),
 .scan_out(thr_c_ic_enable_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_ic_enable_thr_c),
 .dout (agc_ic_enable_thr_c),
  .siclk(siclk),
  .soclk(soclk)) ;

assign next_ic_enable_thr_c_l = ~next_ic_enable_thr_c;
ifu_ftu_agc_ctl_msff_ctl_macro__width_1 thr_c_ic_disable_reg  (
 .scan_in(thr_c_ic_disable_reg_scanin),
 .scan_out(thr_c_ic_disable_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_ic_enable_thr_c_l),
 .dout (agc_ic_disable_thr_c),
  .siclk(siclk),
  .soclk(soclk)) ;


assign ic_valid_err_unq = (itlb_valid_dupl_c[7:0] != itlb_valid_c[7:0] ) ; 
assign ic_valid_err_c = ic_valid_err_unq & ~agc_ic_disable_thr_c ;


ifu_ftu_agc_ctl_msff_ctl_macro__width_8 dff_8b_prty_7   (
        .scan_in(dff_8b_prty_7_scanin),
        .scan_out(dff_8b_prty_7_scanout),
        .l1clk(l1clk_out                ),
	.din	({err_w7_8b_parity_f[3:0],err_w6_8b_parity_f[3:0]}),
	.dout	({w7_8b_parity_c[3:0],w6_8b_parity_c[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 dff_8b_prty_5   (
        .scan_in(dff_8b_prty_5_scanin),
        .scan_out(dff_8b_prty_5_scanout),
        .l1clk(l1clk_out                ),
	.din	({err_w5_8b_parity_f[3:0],err_w4_8b_parity_f[3:0]}),
	.dout	({w5_8b_parity_c[3:0],w4_8b_parity_c[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 dff_8b_prty_3   (
        .scan_in(dff_8b_prty_3_scanin),
        .scan_out(dff_8b_prty_3_scanout),
        .l1clk(l1clk_out                ),
	.din	({err_w3_8b_parity_f[3:0],err_w2_8b_parity_f[3:0]}),
	.dout	({w3_8b_parity_c[3:0],w2_8b_parity_c[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 dff_8b_prty_1   (
        .scan_in(dff_8b_prty_1_scanin),
        .scan_out(dff_8b_prty_1_scanout),
        .l1clk(l1clk_out                ),
	.din	({err_w1_8b_parity_f[3:0],err_w0_8b_parity_f[3:0]}),
	.dout	({w1_8b_parity_c[3:0],w0_8b_parity_c[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


assign err_tag_w0_parity_c = ^(w0_8b_parity_c[3:0]);
assign err_tag_w1_parity_c = ^(w1_8b_parity_c[3:0]);
assign err_tag_w2_parity_c = ^(w2_8b_parity_c[3:0]);
assign err_tag_w3_parity_c = ^(w3_8b_parity_c[3:0]);
assign err_tag_w4_parity_c = ^(w4_8b_parity_c[3:0]);
assign err_tag_w5_parity_c = ^(w5_8b_parity_c[3:0]);
assign err_tag_w6_parity_c = ^(w6_8b_parity_c[3:0]);
assign err_tag_w7_parity_c = ^(w7_8b_parity_c[3:0]);


assign agc_tag_pe_c[0] = err_tag_w0_parity_c & agc_ic_enable_thr_c & agc_fetch_v_c & itlb_valid_c[0];
assign agc_tag_pe_c[1] = err_tag_w1_parity_c & agc_ic_enable_thr_c & agc_fetch_v_c & itlb_valid_c[1];
assign agc_tag_pe_c[2] = err_tag_w2_parity_c & agc_ic_enable_thr_c & agc_fetch_v_c & itlb_valid_c[2];
assign agc_tag_pe_c[3] = err_tag_w3_parity_c & agc_ic_enable_thr_c & agc_fetch_v_c & itlb_valid_c[3];
assign agc_tag_pe_c[4] = err_tag_w4_parity_c & agc_ic_enable_thr_c & agc_fetch_v_c & itlb_valid_c[4];
assign agc_tag_pe_c[5] = err_tag_w5_parity_c & agc_ic_enable_thr_c & agc_fetch_v_c & itlb_valid_c[5];
assign agc_tag_pe_c[6] = err_tag_w6_parity_c & agc_ic_enable_thr_c & agc_fetch_v_c & itlb_valid_c[6];
assign agc_tag_pe_c[7] = err_tag_w7_parity_c & agc_ic_enable_thr_c & agc_fetch_v_c & itlb_valid_c[7];


assign ftu_thr0_inv_req_c = invalidation_req_c & curr_fetch_thr_c[0] & ~tsm_thr0_no_new_miss & agc_fetch_v_int_c;
assign ftu_thr1_inv_req_c = invalidation_req_c & curr_fetch_thr_c[1] & ~tsm_thr1_no_new_miss & agc_fetch_v_int_c;
assign ftu_thr2_inv_req_c = invalidation_req_c & curr_fetch_thr_c[2] & ~tsm_thr2_no_new_miss & agc_fetch_v_int_c;
assign ftu_thr3_inv_req_c = invalidation_req_c & curr_fetch_thr_c[3] & ~tsm_thr3_no_new_miss & agc_fetch_v_int_c;
assign ftu_thr4_inv_req_c = invalidation_req_c & curr_fetch_thr_c[4] & ~tsm_thr4_no_new_miss & agc_fetch_v_int_c;
assign ftu_thr5_inv_req_c = invalidation_req_c & curr_fetch_thr_c[5] & ~tsm_thr5_no_new_miss & agc_fetch_v_int_c;
assign ftu_thr6_inv_req_c = invalidation_req_c & curr_fetch_thr_c[6] & ~tsm_thr6_no_new_miss & agc_fetch_v_int_c;
assign ftu_thr7_inv_req_c = invalidation_req_c & curr_fetch_thr_c[7] & ~tsm_thr7_no_new_miss & agc_fetch_v_int_c;

assign agc_tag_perror_c = |agc_tag_pe_c[7:0] ;


assign itb_mhit_no_priority          = itb_itb_mhit_c      & cerer_ittm_ff & ~invalidation_req_c ; 
assign tte_tag_parity_no_priority    = itb_tag_perr        & cerer_ittp_ff &  itb_cam_hit_c    & ~itb_itb_mhit_c & ~invalidation_req_c ; 
assign tte_data_parity_no_priority   = itb_tte_data_parity & cerer_itdp_ff &  itb_cam_hit_c    & ~itb_itb_mhit_c & ~invalidation_req_c ; 
assign itb_itb_acc_viol_no_priority  = itb_tte_p_c         & ~agc_priv_state_c    & ~itb_itb_miss_c & ~invalidation_req_c & ~itb_itb_mhit_c; 
assign nfo_tlb_exception_no_priority = tlb_nfo             & itb_cam_hit_c          & ~invalidation_req_c   & ~itb_itb_mhit_c; 
assign ic_valid_err_no_priority      = ic_valid_err_c      & cerer_icvp_ff          & ~invalidation_req_c   & ~itb_itb_mhit_c & itb_cam_hit_c;
assign tag_perror_no_priority        = agc_tag_perror_c    & cerer_ictp_ff          & ~invalidation_req_c   &  itb_cam_hit_c ;
assign tag_multiple_hit_no_priority  = ic_tag_multiple_hit & cerer_ictm_ff          & ~invalidation_req_c   &  agc_ic_enable_thr_c & itb_cam_hit_c ;


assign err_excp_set =      itb_mhit_no_priority     | va_hole_exception_c           | nfo_tlb_exception_no_priority   |
                           tag_perror_no_priority   | itb_itb_acc_viol_no_priority  | tte_tag_parity_no_priority      | 
                           ic_valid_err_no_priority | tag_multiple_hit_no_priority  | tte_data_parity_no_priority     ;

assign agc_thr0_err_detect_c = err_excp_set  & curr_fetch_thr_c[0] & agc_fetch_v_int_c;
assign agc_thr1_err_detect_c = err_excp_set  & curr_fetch_thr_c[1] & agc_fetch_v_int_c;
assign agc_thr2_err_detect_c = err_excp_set  & curr_fetch_thr_c[2] & agc_fetch_v_int_c;
assign agc_thr3_err_detect_c = err_excp_set  & curr_fetch_thr_c[3] & agc_fetch_v_int_c;
assign agc_thr4_err_detect_c = err_excp_set  & curr_fetch_thr_c[4] & agc_fetch_v_int_c;
assign agc_thr5_err_detect_c = err_excp_set  & curr_fetch_thr_c[5] & agc_fetch_v_int_c;
assign agc_thr6_err_detect_c = err_excp_set  & curr_fetch_thr_c[6] & agc_fetch_v_int_c;
assign agc_thr7_err_detect_c = err_excp_set  & curr_fetch_thr_c[7] & agc_fetch_v_int_c;

assign asi_mbist_addr_bf[5:3] = mbi_run_bf ? mbi_bist_word_en_bf[2:0] : asi_addr_bf[5:3] ;

assign word_en_asi[0]      = ~asi_addr_bf[5] & ~asi_addr_bf[4] & ~asi_addr_bf[3] ;
assign word_en_asi[1]      = ~asi_addr_bf[5] & ~asi_addr_bf[4] &  asi_addr_bf[3] ;
assign word_en_asi[2]      = ~asi_addr_bf[5] &  asi_addr_bf[4] & ~asi_addr_bf[3] ;
assign word_en_asi[3]      = ~asi_addr_bf[5] &  asi_addr_bf[4] &  asi_addr_bf[3] ;
assign word_en_asi[4]      =  asi_addr_bf[5] & ~asi_addr_bf[4] & ~asi_addr_bf[3] ;
assign word_en_asi[5]      =  asi_addr_bf[5] & ~asi_addr_bf[4] &  asi_addr_bf[3] ;
assign word_en_asi[6]      =  asi_addr_bf[5] &  asi_addr_bf[4] & ~asi_addr_bf[3] ;
assign word_en_asi[7]      =  asi_addr_bf[5] &  asi_addr_bf[4] &  asi_addr_bf[3] ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_4 asi_sel_word_reg  (
 .scan_in(asi_sel_word_reg_scanin),
 .scan_out(asi_sel_word_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({asi_mbist_addr_bf[4:3],asi_mbist_addr_f[4:3]}),
 .dout ({asi_mbist_addr_f[4:3], asi_mbist_addr_c[4:3]}),
  .siclk(siclk),
  .soclk(soclk)) ;

assign agc_asi_sel_word_c[0]     = ~asi_mbist_addr_c[4] & ~asi_mbist_addr_c[3] ;
assign agc_asi_sel_word_c[1]     = ~asi_mbist_addr_c[4] &  asi_mbist_addr_c[3] ;
assign agc_asi_sel_word_c[2]     =  asi_mbist_addr_c[4] & ~asi_mbist_addr_c[3] ;
assign agc_asi_sel_word_c[3]     =  asi_mbist_addr_c[4] &  asi_mbist_addr_c[3] ;

assign agc_word_en_bf[7:0] = (ftp_asi_mbist_access_bf & ~mbi_run_bf) ? word_en_asi[7:0] : 8'hFF;


///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// NOTE: Qualify the bypass more with the Thread ID.                                                         //
///////////////////////////////////////////////////////////////////////////////////////////////////////////////    
assign ftu_buffer_wr_en_f[0] = ftp_fetch_thr_q_f[0] | agc_byp_valid | agc_by_pass_valid_unq_f;
assign ftu_buffer_wr_en_f[1] = ftp_fetch_thr_q_f[1] | agc_byp_valid | agc_by_pass_valid_unq_f;
assign ftu_buffer_wr_en_f[2] = ftp_fetch_thr_q_f[2] | agc_byp_valid | agc_by_pass_valid_unq_f;
assign ftu_buffer_wr_en_f[3] = ftp_fetch_thr_q_f[3] | agc_byp_valid | agc_by_pass_valid_unq_f;
assign ftu_buffer_wr_en_f[4] = ftp_fetch_thr_q_f[4] | agc_byp_valid | agc_by_pass_valid_unq_f;
assign ftu_buffer_wr_en_f[5] = ftp_fetch_thr_q_f[5] | agc_byp_valid | agc_by_pass_valid_unq_f;
assign ftu_buffer_wr_en_f[6] = ftp_fetch_thr_q_f[6] | agc_byp_valid | agc_by_pass_valid_unq_f;
assign ftu_buffer_wr_en_f[7] = ftp_fetch_thr_q_f[7] | agc_byp_valid | agc_by_pass_valid_unq_f;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Add logic to keep track of which has the ERROR condition                                                   //
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
assign thr0_valid_exception_p = thr0_exception_valid_kill_c ;
assign thr1_valid_exception_p = thr1_exception_valid_kill_c ;
assign thr2_valid_exception_p = thr2_exception_valid_kill_c ;
assign thr3_valid_exception_p = thr3_exception_valid_kill_c ;
assign thr4_valid_exception_p = thr4_exception_valid_kill_c ;
assign thr5_valid_exception_p = thr5_exception_valid_kill_c ;
assign thr6_valid_exception_p = thr6_exception_valid_kill_c ;
assign thr7_valid_exception_p = thr7_exception_valid_kill_c ;

assign thr0_way_write_en = (thr0_valid_exception_p ) ; 
assign thr1_way_write_en = (thr1_valid_exception_p ) ; 
assign thr2_way_write_en = (thr2_valid_exception_p ) ; 
assign thr3_way_write_en = (thr3_valid_exception_p ) ; 
assign thr4_way_write_en = (thr4_valid_exception_p ) ; 
assign thr5_way_write_en = (thr5_valid_exception_p ) ; 
assign thr6_way_write_en = (thr6_valid_exception_p ) ; 
assign thr7_way_write_en = (thr7_valid_exception_p ) ; 

assign error_way_muxed_p[2:0] = ({3{ic_valid_err_p_en}}       &   valid_err_way_p[2:0]) |
                                ({3{tag_perror_en_p}}         &   perr_way_p[2:0]     ) |
                                ({3{tag_multiple_hit_en_p}}   &   fetch_way_p[2:0]    ) ;
 
assign thr0_excp_way_in[2:0] = thr0_way_write_en ? error_way_muxed_p[2:0] : ftu_thr0_excp_way[2:0] ;
assign thr1_excp_way_in[2:0] = thr1_way_write_en ? error_way_muxed_p[2:0] : ftu_thr1_excp_way[2:0] ;
assign thr2_excp_way_in[2:0] = thr2_way_write_en ? error_way_muxed_p[2:0] : ftu_thr2_excp_way[2:0] ;
assign thr3_excp_way_in[2:0] = thr3_way_write_en ? error_way_muxed_p[2:0] : ftu_thr3_excp_way[2:0] ;
assign thr4_excp_way_in[2:0] = thr4_way_write_en ? error_way_muxed_p[2:0] : ftu_thr4_excp_way[2:0] ;
assign thr5_excp_way_in[2:0] = thr5_way_write_en ? error_way_muxed_p[2:0] : ftu_thr5_excp_way[2:0] ;
assign thr6_excp_way_in[2:0] = thr6_way_write_en ? error_way_muxed_p[2:0] : ftu_thr6_excp_way[2:0] ;
assign thr7_excp_way_in[2:0] = thr7_way_write_en ? error_way_muxed_p[2:0] : ftu_thr7_excp_way[2:0] ;

/////////////////////////////////////////////////////////////////////////////////////////////////////
// If multiple errors report the LEAST way.                                                        //
/////////////////////////////////////////////////////////////////////////////////////////////////////
assign fetch_way_p_in[0] = (itb_icd_waysel_c[7] & ~itb_icd_waysel_c[6] & ~itb_icd_waysel_c[4] & ~itb_icd_waysel_c[2] & ~itb_icd_waysel_c[0]) | 
                           (itb_icd_waysel_c[5] & ~itb_icd_waysel_c[4] & ~itb_icd_waysel_c[2] & ~itb_icd_waysel_c[0]                       ) | 
                           (itb_icd_waysel_c[3] & ~itb_icd_waysel_c[2] & ~itb_icd_waysel_c[0]                                              ) |
                           (itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) ;
assign fetch_way_p_in[1] = (itb_icd_waysel_c[7] & ~itb_icd_waysel_c[5] & ~itb_icd_waysel_c[4] & ~itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) |
                           (itb_icd_waysel_c[6] & ~itb_icd_waysel_c[5] & ~itb_icd_waysel_c[4] & ~itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) | 
                           (itb_icd_waysel_c[3] & ~itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) | 
                           (itb_icd_waysel_c[2] & ~itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) ;
assign fetch_way_p_in[2] = (itb_icd_waysel_c[7] & ~itb_icd_waysel_c[3] & ~itb_icd_waysel_c[2] & ~itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) | 
                           (itb_icd_waysel_c[6] & ~itb_icd_waysel_c[3] & ~itb_icd_waysel_c[2] & ~itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) |
                           (itb_icd_waysel_c[5] & ~itb_icd_waysel_c[3] & ~itb_icd_waysel_c[2] & ~itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) | 
                           (itb_icd_waysel_c[4] & ~itb_icd_waysel_c[3] & ~itb_icd_waysel_c[2] & ~itb_icd_waysel_c[1] & ~itb_icd_waysel_c[0]) ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_3 fetch_way_p_reg  (
 .scan_in(fetch_way_p_reg_scanin),
 .scan_out(fetch_way_p_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (fetch_way_p_in[2:0]),
 .dout (fetch_way_p[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

assign valid_err_way[0] = itlb_valid_c[0] ^ itlb_valid_dupl_c[0] ;
assign valid_err_way[1] = itlb_valid_c[1] ^ itlb_valid_dupl_c[1] ;
assign valid_err_way[2] = itlb_valid_c[2] ^ itlb_valid_dupl_c[2] ;
assign valid_err_way[3] = itlb_valid_c[3] ^ itlb_valid_dupl_c[3] ;
assign valid_err_way[4] = itlb_valid_c[4] ^ itlb_valid_dupl_c[4] ;
assign valid_err_way[5] = itlb_valid_c[5] ^ itlb_valid_dupl_c[5] ;
assign valid_err_way[6] = itlb_valid_c[6] ^ itlb_valid_dupl_c[6] ;
assign valid_err_way[7] = itlb_valid_c[7] ^ itlb_valid_dupl_c[7] ;

assign valid_err_way_p_in[0] = (valid_err_way[7] & ~valid_err_way[6] & ~valid_err_way[4] & ~valid_err_way[2] & ~valid_err_way[0]) | 
                               (valid_err_way[5] & ~valid_err_way[4] & ~valid_err_way[2] & ~valid_err_way[0]                       ) | 
                               (valid_err_way[3] & ~valid_err_way[2] & ~valid_err_way[0]                                              ) |
                               (valid_err_way[1] & ~valid_err_way[0]) ;
assign valid_err_way_p_in[1] = (valid_err_way[7] & ~valid_err_way[5] & ~valid_err_way[4] & ~valid_err_way[1] & ~valid_err_way[0]) |
                               (valid_err_way[6] & ~valid_err_way[5] & ~valid_err_way[4] & ~valid_err_way[1] & ~valid_err_way[0]) | 
                               (valid_err_way[3] & ~valid_err_way[1] & ~valid_err_way[0]) | 
                               (valid_err_way[2] & ~valid_err_way[1] & ~valid_err_way[0]) ;
assign valid_err_way_p_in[2] = (valid_err_way[7] & ~valid_err_way[3] & ~valid_err_way[2] & ~valid_err_way[1] & ~valid_err_way[0]) | 
                               (valid_err_way[6] & ~valid_err_way[3] & ~valid_err_way[2] & ~valid_err_way[1] & ~valid_err_way[0]) |
                               (valid_err_way[5] & ~valid_err_way[3] & ~valid_err_way[2] & ~valid_err_way[1] & ~valid_err_way[0]) | 
                               (valid_err_way[4] & ~valid_err_way[3] & ~valid_err_way[2] & ~valid_err_way[1] & ~valid_err_way[0]) ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_3 valid_err_way_p_reg  (
 .scan_in(valid_err_way_p_reg_scanin),
 .scan_out(valid_err_way_p_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (valid_err_way_p_in[2:0]),
 .dout (valid_err_way_p[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

 
assign perr_way_p_in[0] = (agc_tag_pe_c[7] & ~agc_tag_pe_c[6] & ~agc_tag_pe_c[4] & ~agc_tag_pe_c[2] & ~agc_tag_pe_c[0]) | 
                          (agc_tag_pe_c[5] & ~agc_tag_pe_c[4] & ~agc_tag_pe_c[2] & ~agc_tag_pe_c[0]                       ) | 
                          (agc_tag_pe_c[3] & ~agc_tag_pe_c[2] & ~agc_tag_pe_c[0]                                              ) |
                          (agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) ;
assign perr_way_p_in[1] = (agc_tag_pe_c[7] & ~agc_tag_pe_c[5] & ~agc_tag_pe_c[4] & ~agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) |
                          (agc_tag_pe_c[6] & ~agc_tag_pe_c[5] & ~agc_tag_pe_c[4] & ~agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) | 
                          (agc_tag_pe_c[3] & ~agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) | 
                          (agc_tag_pe_c[2] & ~agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) ;
assign perr_way_p_in[2] = (agc_tag_pe_c[7] & ~agc_tag_pe_c[3] & ~agc_tag_pe_c[2] & ~agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) | 
                          (agc_tag_pe_c[6] & ~agc_tag_pe_c[3] & ~agc_tag_pe_c[2] & ~agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) |
                          (agc_tag_pe_c[5] & ~agc_tag_pe_c[3] & ~agc_tag_pe_c[2] & ~agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) | 
                          (agc_tag_pe_c[4] & ~agc_tag_pe_c[3] & ~agc_tag_pe_c[2] & ~agc_tag_pe_c[1] & ~agc_tag_pe_c[0]) ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_3 tag_pe_way  (
 .scan_in(tag_pe_way_scanin),
 .scan_out(tag_pe_way_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (perr_way_p_in[2:0]),
 .dout (perr_way_p[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

/////////////////////////////////////////////////////////////////////////////////////////////////////

ifu_ftu_agc_ctl_msff_ctl_macro__width_3 tag_perror_en_reg  (
 .scan_in(tag_perror_en_reg_scanin),
 .scan_out(tag_perror_en_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ({tag_perror_en_c , ic_valid_err_c_en , tag_multiple_hit_en}),
 .dout ({tag_perror_en_p , ic_valid_err_p_en , tag_multiple_hit_en_p}),
  .siclk(siclk),
  .soclk(soclk)) ;

 
ifu_ftu_agc_ctl_msff_ctl_macro__width_3 way_thr0_keep_reg  (
 .scan_in(way_thr0_keep_reg_scanin),
 .scan_out(way_thr0_keep_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (thr0_excp_way_in[2:0]),
 .dout (ftu_thr0_excp_way[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

 
ifu_ftu_agc_ctl_msff_ctl_macro__width_3 way_thr1_keep_reg  (
 .scan_in(way_thr1_keep_reg_scanin),
 .scan_out(way_thr1_keep_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (thr1_excp_way_in[2:0]),
 .dout (ftu_thr1_excp_way[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

 
ifu_ftu_agc_ctl_msff_ctl_macro__width_3 way_thr2_keep_reg  (
 .scan_in(way_thr2_keep_reg_scanin),
 .scan_out(way_thr2_keep_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (thr2_excp_way_in[2:0]),
 .dout (ftu_thr2_excp_way[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

 
ifu_ftu_agc_ctl_msff_ctl_macro__width_3 way_thr3_keep_reg  (
 .scan_in(way_thr3_keep_reg_scanin),
 .scan_out(way_thr3_keep_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (thr3_excp_way_in[2:0]),
 .dout (ftu_thr3_excp_way[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

 
ifu_ftu_agc_ctl_msff_ctl_macro__width_3 way_thr4_keep_reg  (
 .scan_in(way_thr4_keep_reg_scanin),
 .scan_out(way_thr4_keep_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (thr4_excp_way_in[2:0]),
 .dout (ftu_thr4_excp_way[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

 
ifu_ftu_agc_ctl_msff_ctl_macro__width_3 way_thr5_keep_reg  (
 .scan_in(way_thr5_keep_reg_scanin),
 .scan_out(way_thr5_keep_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (thr5_excp_way_in[2:0]),
 .dout (ftu_thr5_excp_way[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

 
ifu_ftu_agc_ctl_msff_ctl_macro__width_3 way_thr6_keep_reg  (
 .scan_in(way_thr6_keep_reg_scanin),
 .scan_out(way_thr6_keep_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (thr6_excp_way_in[2:0]),
 .dout (ftu_thr6_excp_way[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;


ifu_ftu_agc_ctl_msff_ctl_macro__width_3 way_thr7_keep_reg  (
 .scan_in(way_thr7_keep_reg_scanin),
 .scan_out(way_thr7_keep_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (thr7_excp_way_in[2:0]),
 .dout (ftu_thr7_excp_way[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
assign excp_way_valid_in = thr7_way_write_en | thr6_way_write_en | thr5_way_write_en | thr4_way_write_en |
                           thr3_way_write_en | thr2_way_write_en | thr1_way_write_en | thr0_way_write_en ;
 

ifu_ftu_agc_ctl_msff_ctl_macro__width_4 excp_way_d_reg  (
 .scan_in(excp_way_d_reg_scanin),
 .scan_out(excp_way_d_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  ({error_way_muxed_p[2:0],excp_way_valid_in}),
 .dout ({ftu_excp_way_d[2:0],ftu_excp_way_valid_d}),
  .siclk(siclk),
  .soclk(soclk)) ;


assign excp_tid_d_in[0] = thr1_way_write_en | thr3_way_write_en | thr5_way_write_en | thr7_way_write_en ; 
assign excp_tid_d_in[1] = thr2_way_write_en | thr3_way_write_en | thr6_way_write_en | thr7_way_write_en ; 
assign excp_tid_d_in[2] = thr4_way_write_en | thr5_way_write_en | thr6_way_write_en | thr7_way_write_en ; 

ifu_ftu_agc_ctl_msff_ctl_macro__width_3 excp_tid_d_reg  (
 .scan_in(excp_tid_d_reg_scanin),
 .scan_out(excp_tid_d_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (excp_tid_d_in[2:0]),
 .dout (ftu_excp_tid_d[2:0]),
  .siclk(siclk),
  .soclk(soclk)) ;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
assign next_itlb_busy = itc_demap_next ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 itlb_busy_reg  (
 .scan_in(itlb_busy_reg_scanin),
 .scan_out(itlb_busy_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_itlb_busy),
 .dout (itlb_busy_bf),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 itlb_busy_f_reg  (
 .scan_in(itlb_busy_f_reg_scanin),
 .scan_out(itlb_busy_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (itlb_busy_bf),
 .dout (itlb_busy_f),
  .siclk(siclk),
  .soclk(soclk)
);

assign ith_det_req_bbf = asi_ith_det_req | (ith_det_req_ff  & (itlb_busy_bf | itlb_busy_f)) ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_1 ith_det_req_ff_reg  (
 .scan_in(ith_det_req_ff_reg_scanin),
 .scan_out(ith_det_req_ff_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (ith_det_req_bbf),
 .dout (ith_det_req_ff),
  .siclk(siclk),
  .soclk(soclk)
 );


assign next_enabled_thread[7:0] =  spc_core_running_status[7:0] ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 enabled_thr_reg_dup  (
 .scan_in(enabled_thr_reg_dup_scanin),
 .scan_out(enabled_thr_reg_dup_scanout),
 .l1clk(l1clk),
 .din  (next_enabled_thread[7:0]),
 .dout (enabled_threads_dup[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign next_single_thread_active = (enabled_threads_dup[0] & ~(|enabled_threads_dup[7:1])) |
                                   (enabled_threads_dup[1] & ~(|enabled_threads_dup[7:2]) & ~(enabled_threads_dup[0]))    |
                                   (enabled_threads_dup[2] & ~(|enabled_threads_dup[7:3]) & ~(|enabled_threads_dup[1:0])) |
                                   (enabled_threads_dup[3] & ~(|enabled_threads_dup[7:4]) & ~(|enabled_threads_dup[2:0])) |
                                   (enabled_threads_dup[4] & ~(|enabled_threads_dup[7:5]) & ~(|enabled_threads_dup[3:0])) |
                                   (enabled_threads_dup[5] & ~(|enabled_threads_dup[7:6]) & ~(|enabled_threads_dup[4:0])) |
                                   (enabled_threads_dup[6] & ~( enabled_threads_dup[7])   & ~(|enabled_threads_dup[5:0])) |
                                   (enabled_threads_dup[7] & ~(|enabled_threads_dup[6:0])) ;


ifu_ftu_agc_ctl_msff_ctl_macro__width_1 single_thread_active_reg  (
 .scan_in(single_thread_active_reg_scanin),
 .scan_out(single_thread_active_reg_scanout),
 .l1clk(l1clk),
 .din  (next_single_thread_active),
 .dout (single_thread_active),
  .siclk(siclk),
  .soclk(soclk));


////////////////////////////////////////////////////////////////////////////////////////
// Invalidation request from TLU                                                      //
////////////////////////////////////////////////////////////////////////////////////////
assign reset_invalidation_req[0] = (agc_fetch_v_int_c & curr_fetch_thr_c[0] & ~tsm_thr0_no_new_miss) | tlu_flush_ifu_f[0] ;
assign reset_invalidation_req[1] = (agc_fetch_v_int_c & curr_fetch_thr_c[1] & ~tsm_thr1_no_new_miss) | tlu_flush_ifu_f[1] ;
assign reset_invalidation_req[2] = (agc_fetch_v_int_c & curr_fetch_thr_c[2] & ~tsm_thr2_no_new_miss) | tlu_flush_ifu_f[2] ;
assign reset_invalidation_req[3] = (agc_fetch_v_int_c & curr_fetch_thr_c[3] & ~tsm_thr3_no_new_miss) | tlu_flush_ifu_f[3] ;
assign reset_invalidation_req[4] = (agc_fetch_v_int_c & curr_fetch_thr_c[4] & ~tsm_thr4_no_new_miss) | tlu_flush_ifu_f[4] ;
assign reset_invalidation_req[5] = (agc_fetch_v_int_c & curr_fetch_thr_c[5] & ~tsm_thr5_no_new_miss) | tlu_flush_ifu_f[5] ;
assign reset_invalidation_req[6] = (agc_fetch_v_int_c & curr_fetch_thr_c[6] & ~tsm_thr6_no_new_miss) | tlu_flush_ifu_f[6] ;
assign reset_invalidation_req[7] = (agc_fetch_v_int_c & curr_fetch_thr_c[7] & ~tsm_thr7_no_new_miss) | tlu_flush_ifu_f[7] ;

assign new_invalidation_req[0] = tlu_ifu_invalidate[0] & trap_thread_g0[0] ; 
assign new_invalidation_req[1] = tlu_ifu_invalidate[0] & trap_thread_g0[1] ; 
assign new_invalidation_req[2] = tlu_ifu_invalidate[0] & trap_thread_g0[2] ; 
assign new_invalidation_req[3] = tlu_ifu_invalidate[0] & trap_thread_g0[3] ; 
assign new_invalidation_req[4] = tlu_ifu_invalidate[1] & trap_thread_g1[0] ; 
assign new_invalidation_req[5] = tlu_ifu_invalidate[1] & trap_thread_g1[1] ; 
assign new_invalidation_req[6] = tlu_ifu_invalidate[1] & trap_thread_g1[2] ; 
assign new_invalidation_req[7] = tlu_ifu_invalidate[1] & trap_thread_g1[3] ; 

assign set_invalidation_req[0] = new_invalidation_req[0] | (invalidation_req_c & curr_fetch_thr_c[0] & tsm_thr0_no_new_miss) ; 
assign set_invalidation_req[1] = new_invalidation_req[1] | (invalidation_req_c & curr_fetch_thr_c[1] & tsm_thr1_no_new_miss) ; 
assign set_invalidation_req[2] = new_invalidation_req[2] | (invalidation_req_c & curr_fetch_thr_c[2] & tsm_thr2_no_new_miss) ; 
assign set_invalidation_req[3] = new_invalidation_req[3] | (invalidation_req_c & curr_fetch_thr_c[3] & tsm_thr3_no_new_miss) ; 
assign set_invalidation_req[4] = new_invalidation_req[4] | (invalidation_req_c & curr_fetch_thr_c[4] & tsm_thr4_no_new_miss) ; 
assign set_invalidation_req[5] = new_invalidation_req[5] | (invalidation_req_c & curr_fetch_thr_c[5] & tsm_thr5_no_new_miss) ; 
assign set_invalidation_req[6] = new_invalidation_req[6] | (invalidation_req_c & curr_fetch_thr_c[6] & tsm_thr6_no_new_miss) ; 
assign set_invalidation_req[7] = new_invalidation_req[7] | (invalidation_req_c & curr_fetch_thr_c[7] & tsm_thr7_no_new_miss) ; 

assign next_invalidation_req[0] = set_invalidation_req[0] | (invalidation_req_ff[0] & ~reset_invalidation_req[0]) ;
assign next_invalidation_req[1] = set_invalidation_req[1] | (invalidation_req_ff[1] & ~reset_invalidation_req[1]) ;
assign next_invalidation_req[2] = set_invalidation_req[2] | (invalidation_req_ff[2] & ~reset_invalidation_req[2]) ;
assign next_invalidation_req[3] = set_invalidation_req[3] | (invalidation_req_ff[3] & ~reset_invalidation_req[3]) ;
assign next_invalidation_req[4] = set_invalidation_req[4] | (invalidation_req_ff[4] & ~reset_invalidation_req[4]) ;
assign next_invalidation_req[5] = set_invalidation_req[5] | (invalidation_req_ff[5] & ~reset_invalidation_req[5]) ;
assign next_invalidation_req[6] = set_invalidation_req[6] | (invalidation_req_ff[6] & ~reset_invalidation_req[6]) ;
assign next_invalidation_req[7] = set_invalidation_req[7] | (invalidation_req_ff[7] & ~reset_invalidation_req[7]) ;

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 invalidation_req_reg  (
 .scan_in(invalidation_req_reg_scanin),
 .scan_out(invalidation_req_reg_scanout),
 .l1clk(l1clk),
 .din  (next_invalidation_req[7:0]),
 .dout (invalidation_req_ff[7:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_agc_ctl_msff_ctl_macro__width_8 invalidation_req_dup_reg  (
 .scan_in(invalidation_req_dup_reg_scanin),
 .scan_out(invalidation_req_dup_reg_scanout),
 .l1clk(l1clk),
 .din  (next_invalidation_req[7:0]),
 .dout (agc_invalidation_req_ff[7:0]),
  .siclk(siclk),
  .soclk(soclk));


assign invalidation_req_f =  (ftp_fetch_thr_q_f[0] & invalidation_req_ff[0]) |
                             (ftp_fetch_thr_q_f[1] & invalidation_req_ff[1]) |
                             (ftp_fetch_thr_q_f[2] & invalidation_req_ff[2]) |
                             (ftp_fetch_thr_q_f[3] & invalidation_req_ff[3]) |
                             (ftp_fetch_thr_q_f[4] & invalidation_req_ff[4]) |
                             (ftp_fetch_thr_q_f[5] & invalidation_req_ff[5]) |
                             (ftp_fetch_thr_q_f[6] & invalidation_req_ff[6]) |
                             (ftp_fetch_thr_q_f[7] & invalidation_req_ff[7]) ;
 

 ifu_ftu_agc_ctl_msff_ctl_macro__width_1 invalidation_req_c_reg  (
  .scan_in(invalidation_req_c_reg_scanin),
  .scan_out(invalidation_req_c_reg_scanout),
  .l1clk( l1clk),
  .din  (invalidation_req_f),
  .dout (invalidation_req_c),
  .siclk(siclk),
  .soclk(soclk));

assign agc_any_invalidation_req_f = invalidation_req_f ;

assign thr0_kill_after_invalidation   = invalidation_req_c    & curr_fetch_thr_c[0]  ; 
assign thr1_kill_after_invalidation   = invalidation_req_c    & curr_fetch_thr_c[1]  ; 
assign thr2_kill_after_invalidation   = invalidation_req_c    & curr_fetch_thr_c[2]  ; 
assign thr3_kill_after_invalidation   = invalidation_req_c    & curr_fetch_thr_c[3]  ; 
assign thr4_kill_after_invalidation   = invalidation_req_c    & curr_fetch_thr_c[4]  ; 
assign thr5_kill_after_invalidation   = invalidation_req_c    & curr_fetch_thr_c[5]  ; 
assign thr6_kill_after_invalidation   = invalidation_req_c    & curr_fetch_thr_c[6]  ; 
assign thr7_kill_after_invalidation   = invalidation_req_c    & curr_fetch_thr_c[7]  ; 

 ifu_ftu_agc_ctl_msff_ctl_macro__width_8 thrx_inv_kill_reg  (
  .scan_in(thrx_inv_kill_reg_scanin),
  .scan_out(thrx_inv_kill_reg_scanout),
  .l1clk( l1clk                                                             ),
  .din  ({thr7_kill_after_invalidation,thr6_kill_after_invalidation,
          thr5_kill_after_invalidation,thr4_kill_after_invalidation,
          thr3_kill_after_invalidation,thr2_kill_after_invalidation,
          thr1_kill_after_invalidation,thr0_kill_after_invalidation}),
  .dout ({thr7_kill_after_invalidation_d,thr6_kill_after_invalidation_d,
          thr5_kill_after_invalidation_d,thr4_kill_after_invalidation_d,
          thr3_kill_after_invalidation_d,thr2_kill_after_invalidation_d,
          thr1_kill_after_invalidation_d,thr0_kill_after_invalidation_d}),
  .siclk(siclk),
  .soclk(soclk)) ;


///////////////////////////////////////////////////////////////////////////
// Cache miss signals.                                                   //
///////////////////////////////////////////////////////////////////////////


assign cms_itb_cmiss_c_q =  itb_cmiss_c & agc_fetch_v_c_unq & ~itb_itb_miss_c & ~agc_kill_fetch_cv_int2_c & agc_qualify_cmiss;


assign ftu_agc_thr0_cmiss_c = cms_itb_cmiss_c_q & cms_curr_fetch_thr_c[0] & ~tsm_thr0_no_new_miss  & ~cms_tlu_flush_f[0] & ~agc_thr0_br_misp_f;
assign ftu_agc_thr1_cmiss_c = cms_itb_cmiss_c_q & cms_curr_fetch_thr_c[1] & ~tsm_thr1_no_new_miss  & ~cms_tlu_flush_f[1] & ~agc_thr1_br_misp_f;
assign ftu_agc_thr2_cmiss_c = cms_itb_cmiss_c_q & cms_curr_fetch_thr_c[2] & ~tsm_thr2_no_new_miss  & ~cms_tlu_flush_f[2] & ~agc_thr2_br_misp_f;
assign ftu_agc_thr3_cmiss_c = cms_itb_cmiss_c_q & cms_curr_fetch_thr_c[3] & ~tsm_thr3_no_new_miss  & ~cms_tlu_flush_f[3] & ~agc_thr3_br_misp_f;
assign ftu_agc_thr4_cmiss_c = cms_itb_cmiss_c_q & cms_curr_fetch_thr_c[4] & ~tsm_thr4_no_new_miss  & ~cms_tlu_flush_f[4] & ~agc_thr4_br_misp_f;
assign ftu_agc_thr5_cmiss_c = cms_itb_cmiss_c_q & cms_curr_fetch_thr_c[5] & ~tsm_thr5_no_new_miss  & ~cms_tlu_flush_f[5] & ~agc_thr5_br_misp_f;
assign ftu_agc_thr6_cmiss_c = cms_itb_cmiss_c_q & cms_curr_fetch_thr_c[6] & ~tsm_thr6_no_new_miss  & ~cms_tlu_flush_f[6] & ~agc_thr6_br_misp_f;
assign ftu_agc_thr7_cmiss_c = cms_itb_cmiss_c_q & cms_curr_fetch_thr_c[7] & ~tsm_thr7_no_new_miss  & ~cms_tlu_flush_f[7] & ~agc_thr7_br_misp_f;

///////////////////////////////////////////////////////////////////////
// Spare circuits                                                    //
///////////////////////////////////////////////////////////////////////
ifu_ftu_agc_ctl_spare_ctl_macro__num_8 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


///////////////////////////////////////////////////////////////////////
// Cambist outputs for the ITLB
///////////////////////////////////////////////////////////////////////


ifu_ftu_agc_ctl_msff_ctl_macro__width_6 mbist_output  (
 .scan_in(mbist_output_scanin),
 .scan_out(mbist_output_scanout),
 .l1clk( l1clk                                                             ),
        .din    ({itb_cam_hit_c,          tlb_context0_hit,     itb_itb_mhit_c,
                  itb_cam_hit_c_1,        tlb_context0_hit_1,     itb_itb_mhit_c_1}),
        .dout   ({itb_cam_hit_c_1,        tlb_context0_hit_1,     itb_itb_mhit_c_1,
                  ftu_mbi_tlb_cam_hit,ftu_mbi_tlb_ctxt0_hit,ftu_mbi_tlb_cam_mhit}),
  .siclk(siclk),
  .soclk(soclk));


assign ifu_ibuffer_write_c[0]  = ftu_fetch_thr_c[0] & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] |
                                                       ftu_instr_valid_c[3] | ftu_exception_valid_c) & ~ftu_ibu_redirect_bf[0];

assign ifu_ibuffer_write_c[1]  = ftu_fetch_thr_c[1] & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] |
                                                       ftu_instr_valid_c[3] | ftu_exception_valid_c) & ~ftu_ibu_redirect_bf[1];

assign ifu_ibuffer_write_c[2]  = ftu_fetch_thr_c[2] & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] |
                                                       ftu_instr_valid_c[3] | ftu_exception_valid_c) & ~ftu_ibu_redirect_bf[2];

assign ifu_ibuffer_write_c[3]  = ftu_fetch_thr_c[3] & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] |
                                                       ftu_instr_valid_c[3] | ftu_exception_valid_c) & ~ftu_ibu_redirect_bf[3];


assign ifu_ibuffer_write_c[4]  = ftu_fetch_thr_c[4] & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] |
                                                       ftu_instr_valid_c[3] | ftu_exception_valid_c) & ~ftu_ibu_redirect_bf[4];

assign ifu_ibuffer_write_c[5]  = ftu_fetch_thr_c[5] & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] |
                                                       ftu_instr_valid_c[3] | ftu_exception_valid_c) & ~ftu_ibu_redirect_bf[5];

assign ifu_ibuffer_write_c[6]  = ftu_fetch_thr_c[6] & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] |
                                                       ftu_instr_valid_c[3] | ftu_exception_valid_c) & ~ftu_ibu_redirect_bf[6];

assign ifu_ibuffer_write_c[7]  = ftu_fetch_thr_c[7] & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] |
                                                       ftu_instr_valid_c[3] | ftu_exception_valid_c) & ~ftu_ibu_redirect_bf[7];


supply0 vss;
supply1 vdd;
assign se = tcu_scan_en ;
// fixscan start:
assign tlu_ceter_pscce_reg_scanin = scan_in                  ;
assign br_misp_data_reg_scanin   = tlu_ceter_pscce_reg_scanout;
assign br_misp_data_dup_reg_scanin = br_misp_data_reg_scanout ;
assign tid_dec_w_reg_scanin      = br_misp_data_dup_reg_scanout;
assign curr_fetch_thr_c_reg_scanin = tid_dec_w_reg_scanout    ;
assign cms_curr_fetch_thr_c_reg_scanin = curr_fetch_thr_c_reg_scanout;
assign sf_valid_reg_scanin       = cms_curr_fetch_thr_c_reg_scanout;
assign sf_valid_dup_reg_scanin   = sf_valid_reg_scanout     ;
assign sf_valid_by_pass_f_reg_scanin = sf_valid_dup_reg_scanout ;
assign sf_valid_by_pass_c_reg_scanin = sf_valid_by_pass_f_reg_scanout;
assign sf_v_c_scanin             = sf_valid_by_pass_c_reg_scanout;
assign unc_valid_reg_scanin      = sf_v_c_scanout           ;
assign thr0_pc_f_inc_reg_scanin  = unc_valid_reg_scanout    ;
assign thr1_pc_f_inc_reg_scanin  = thr0_pc_f_inc_reg_scanout;
assign thr2_pc_f_inc_reg_scanin  = thr1_pc_f_inc_reg_scanout;
assign thr3_pc_f_inc_reg_scanin  = thr2_pc_f_inc_reg_scanout;
assign thr4_pc_f_inc_reg_scanin  = thr3_pc_f_inc_reg_scanout;
assign thr5_pc_f_inc_reg_scanin  = thr4_pc_f_inc_reg_scanout;
assign thr6_pc_f_inc_reg_scanin  = thr5_pc_f_inc_reg_scanout;
assign thr7_pc_f_inc_reg_scanin  = thr6_pc_f_inc_reg_scanout;
assign tlu_flush_ifu_reg_scanin  = thr7_pc_f_inc_reg_scanout;
assign tlu_flush_ifu_d_reg_scanin = tlu_flush_ifu_reg_scanout;
assign cms_tlu_flush_ifu_reg_scanin = tlu_flush_ifu_d_reg_scanout;
assign load_flush_reg_scanin     = cms_tlu_flush_ifu_reg_scanout;
assign kill_fetch_vc_reg_scanin  = load_flush_reg_scanout   ;
assign kill_fetch_vc_2_reg_scanin = kill_fetch_vc_reg_scanout;
assign exception_valid_kill_reg_scanin = kill_fetch_vc_2_reg_scanout;
assign exception_valid_kill1_reg_scanin = exception_valid_kill_reg_scanout;
assign thrx_exception_valid_kill_reg_scanin = exception_valid_kill1_reg_scanout;
assign thrx_redirect_reg_scanin  = thrx_exception_valid_kill_reg_scanout;
assign thrx_ibu_redirect_reg_scanin = thrx_redirect_reg_scanout;
assign other_flushes_reg_scanin  = thrx_ibu_redirect_reg_scanout;
assign cmu_fill_byp_thread_reg_scanin = other_flushes_reg_scanout;
assign by_pass_thread_bf_reg_scanin = cmu_fill_byp_thread_reg_scanout;
assign by_pass_sel_f_reg_scanin  = by_pass_thread_bf_reg_scanout;
assign by_pass_sel_c_reg_scanin  = by_pass_sel_f_reg_scanout;
assign by_pass_thread_f_reg_scanin = by_pass_sel_c_reg_scanout;
assign fetchalid_cnq_reg_scanin  = by_pass_thread_f_reg_scanout;
assign fetch_v_dup_c_reg_scanin  = fetchalid_cnq_reg_scanout;
assign cycle_2_by_pass_f_reg_scanin = fetch_v_dup_c_reg_scanout;
assign cycle_3_by_pass_f_reg_scanin = cycle_2_by_pass_f_reg_scanout;
assign cycle_3_by_pass_c_reg_scanin = cycle_3_by_pass_f_reg_scanout;
assign cmu_any_data_ready_reg_scanin = cycle_3_by_pass_c_reg_scanout;
assign tsm_thrx_kill_by_pass_reg_scanin = cmu_any_data_ready_reg_scanout;
assign by_pass_v_f_reg_scanin    = tsm_thrx_kill_by_pass_reg_scanout;
assign by_pass_v_c_reg_scanin    = by_pass_v_f_reg_scanout  ;
assign by_pass_instr_v_f_reg_scanin = by_pass_v_c_reg_scanout  ;
assign by_pass_instr_v_c_reg_scanin = by_pass_instr_v_f_reg_scanout;
assign bus_first_reg_scanin      = by_pass_instr_v_c_reg_scanout;
assign thrx_sf_kill_reg_scanin   = bus_first_reg_scanout    ;
assign mbist_data_in_reg_scanin  = thrx_sf_kill_reg_scanout ;
assign cmu_fill_wrway_reg_scanin = mbist_data_in_reg_scanout;
assign asi_mbist_way_f_reg_scanin = cmu_fill_wrway_reg_scanout;
assign vl_data_reg_scanin        = asi_mbist_way_f_reg_scanout;
assign itlb_valid_reg_scanin     = vl_data_reg_scanout      ;
assign itlb_valid_dupl_reg_scanin = itlb_valid_reg_scanout   ;
assign va_hole_excp_c_reg_scanin = itlb_valid_dupl_reg_scanout;
assign addr_bit_5_bf_reg_scanin  = va_hole_excp_c_reg_scanout;
assign inv_bit_5_bf_reg_scanin   = addr_bit_5_bf_reg_scanout;
assign wrway_bf_reg_scanin       = inv_bit_5_bf_reg_scanout ;
assign inv_way_bf_reg_scanin     = wrway_bf_reg_scanout     ;
assign inv_way1_bf_reg_scanin    = inv_way_bf_reg_scanout   ;
assign inv_line_bf_reg_scanin    = inv_way1_bf_reg_scanout  ;
assign evic_line_bf_reg_scanin   = inv_line_bf_reg_scanout  ;
assign data_ready_bf_reg_scanin  = evic_line_bf_reg_scanout ;
assign l2_cache_miss_in_reg_scanin = data_ready_bf_reg_scanout;
assign l2_cache_miss_1_reg_scanin = l2_cache_miss_in_reg_scanout;
assign l2_cache_miss_2_reg_scanin = l2_cache_miss_1_reg_scanout;
assign ic_instr_v_reg_scanin     = l2_cache_miss_2_reg_scanout;
assign any_instr_v_c_reg_scanin  = ic_instr_v_reg_scanout   ;
assign hpstate_reg_scanin        = any_instr_v_c_reg_scanout;
assign priv_state_c_reg_scanin   = hpstate_reg_scanout      ;
assign tlb_parity_reg_scanin     = priv_state_c_reg_scanout ;
assign itlb_cam_vld_c_reg_scanin = tlb_parity_reg_scanout   ;
assign cerer_en_reg_scanin       = itlb_cam_vld_c_reg_scanout;
assign itc_real_f_reg_scanin     = cerer_en_reg_scanout     ;
assign itc_real_c_reg_scanin     = itc_real_f_reg_scanout   ;
assign cntx_sel_reg_scanin       = itc_real_c_reg_scanout   ;
assign lsu_no_icm_reg_scanin     = cntx_sel_reg_scanout     ;
assign ic_enable_reg_scanin      = lsu_no_icm_reg_scanout   ;
assign thr_c_ic_enable_reg_scanin = ic_enable_reg_scanout    ;
assign thr_c_ic_disable_reg_scanin = thr_c_ic_enable_reg_scanout;
assign dff_8b_prty_7_scanin      = thr_c_ic_disable_reg_scanout;
assign dff_8b_prty_5_scanin      = dff_8b_prty_7_scanout    ;
assign dff_8b_prty_3_scanin      = dff_8b_prty_5_scanout    ;
assign dff_8b_prty_1_scanin      = dff_8b_prty_3_scanout    ;
assign asi_sel_word_reg_scanin   = dff_8b_prty_1_scanout    ;
assign fetch_way_p_reg_scanin    = asi_sel_word_reg_scanout ;
assign valid_err_way_p_reg_scanin = fetch_way_p_reg_scanout  ;
assign tag_pe_way_scanin         = valid_err_way_p_reg_scanout;
assign tag_perror_en_reg_scanin  = tag_pe_way_scanout       ;
assign way_thr0_keep_reg_scanin  = tag_perror_en_reg_scanout;
assign way_thr1_keep_reg_scanin  = way_thr0_keep_reg_scanout;
assign way_thr2_keep_reg_scanin  = way_thr1_keep_reg_scanout;
assign way_thr3_keep_reg_scanin  = way_thr2_keep_reg_scanout;
assign way_thr4_keep_reg_scanin  = way_thr3_keep_reg_scanout;
assign way_thr5_keep_reg_scanin  = way_thr4_keep_reg_scanout;
assign way_thr6_keep_reg_scanin  = way_thr5_keep_reg_scanout;
assign way_thr7_keep_reg_scanin  = way_thr6_keep_reg_scanout;
assign excp_way_d_reg_scanin     = way_thr7_keep_reg_scanout;
assign excp_tid_d_reg_scanin     = excp_way_d_reg_scanout   ;
assign itlb_busy_reg_scanin      = excp_tid_d_reg_scanout   ;
assign itlb_busy_f_reg_scanin    = itlb_busy_reg_scanout    ;
assign ith_det_req_ff_reg_scanin = itlb_busy_f_reg_scanout  ;
assign enabled_thr_reg_dup_scanin = ith_det_req_ff_reg_scanout;
assign single_thread_active_reg_scanin = enabled_thr_reg_dup_scanout;
assign invalidation_req_reg_scanin = single_thread_active_reg_scanout;
assign invalidation_req_dup_reg_scanin = invalidation_req_reg_scanout;
assign invalidation_req_c_reg_scanin = invalidation_req_dup_reg_scanout;
assign thrx_inv_kill_reg_scanin  = invalidation_req_c_reg_scanout;
assign spares_scanin             = thrx_inv_kill_reg_scanout;
assign mbist_output_scanin       = spares_scanout           ;
assign scan_out                  = mbist_output_scanout     ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agc_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ftu_agc_ctl_spare_ctl_macro__num_8 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));
assign scan_out = so_7;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_agd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_agd_dp (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_muxtest, 
  mbi_addr, 
  mbi_cmpsel, 
  mbi_wdata, 
  mbi_icv_read_en, 
  ftp_thr0_trprdpc_sel_bf, 
  ftp_thr1_trprdpc_sel_bf, 
  ftp_thr2_trprdpc_sel_bf, 
  ftp_thr3_trprdpc_sel_bf, 
  ftp_thr4_trprdpc_sel_bf, 
  ftp_thr5_trprdpc_sel_bf, 
  ftp_thr6_trprdpc_sel_bf, 
  ftp_thr7_trprdpc_sel_bf, 
  agc_thr0_pcf_sel_bf, 
  agc_thr1_pcf_sel_bf, 
  agc_thr2_pcf_sel_bf, 
  agc_thr3_pcf_sel_bf, 
  agc_thr4_pcf_sel_bf, 
  agc_thr5_pcf_sel_bf, 
  agc_thr6_pcf_sel_bf, 
  agc_thr7_pcf_sel_bf, 
  agc_thr0_pcf_sel_last_bf, 
  agc_thr1_pcf_sel_last_bf, 
  agc_thr2_pcf_sel_last_bf, 
  agc_thr3_pcf_sel_last_bf, 
  agc_thr4_pcf_sel_last_bf, 
  agc_thr5_pcf_sel_last_bf, 
  agc_thr6_pcf_sel_last_bf, 
  agc_thr7_pcf_sel_last_bf, 
  ftp_thr0_sel_br_bf, 
  ftp_thr1_sel_br_bf, 
  ftp_thr2_sel_br_bf, 
  ftp_thr3_sel_br_bf, 
  ftp_thr4_sel_br_bf, 
  ftp_thr5_sel_br_bf, 
  ftp_thr6_sel_br_bf, 
  ftp_thr7_sel_br_bf, 
  agc_sel_inv_index, 
  agc_pc_sel_for_c, 
  icv_valid_f, 
  asi_addr_bf, 
  agc_thr0_byp_incr_bit5, 
  agc_thr1_byp_incr_bit5, 
  agc_thr2_byp_incr_bit5, 
  agc_thr3_byp_incr_bit5, 
  agc_thr4_byp_incr_bit5, 
  agc_thr5_byp_incr_bit5, 
  agc_thr6_byp_incr_bit5, 
  agc_thr7_byp_incr_bit5, 
  agc_thr0_byp_pc_update_bf, 
  agc_thr1_byp_pc_update_bf, 
  agc_thr2_byp_pc_update_bf, 
  agc_thr3_byp_pc_update_bf, 
  agc_thr4_byp_pc_update_bf, 
  agc_thr5_byp_pc_update_bf, 
  agc_thr6_byp_pc_update_bf, 
  agc_thr7_byp_pc_update_bf, 
  ftp_new_thr_sel_bf, 
  ftp_ict_data_sel_bf, 
  ftp_pc_sel_am, 
  ftp_pc_sel_tag_part1, 
  ftp_pc_sel_tag_part2, 
  ftp_pc_sel_tag_pc_bot, 
  ftp_pc_sel_tag_pc_top, 
  ftp_any_thr_clken, 
  ftp_sel_icv_mbist_addr, 
  ftp_icaddr_sel_first_mux, 
  tlu_trap_pc_0, 
  tlu_trap_pc_1, 
  itc_va, 
  exu_address0_e, 
  exu_address1_e, 
  tlu_npc_w, 
  cmu_fill_paddr, 
  asi_wr_data, 
  cmu_icache_invalidate_index, 
  cmu_thr0_data_ready, 
  cmu_thr1_data_ready, 
  cmu_thr2_data_ready, 
  cmu_thr3_data_ready, 
  cmu_thr4_data_ready, 
  cmu_thr5_data_ready, 
  cmu_thr6_data_ready, 
  cmu_thr7_data_ready, 
  agd_direct_map_rep_way, 
  agd_itlb_valid_f, 
  agd_itlb_valid_fast_f, 
  agd_itlb_valid_dupl_f, 
  ifu_agd_pc_bf, 
  agd_ict_index_bf, 
  agd_ic_index_bf, 
  agd_icv_windex_bf, 
  ifu_agd_pc_f, 
  agd_thr0_pc_4_2_f, 
  agd_thr1_pc_4_2_f, 
  agd_thr2_pc_4_2_f, 
  agd_thr3_pc_4_2_f, 
  agd_thr4_pc_4_2_f, 
  agd_thr5_pc_4_2_f, 
  agd_thr6_pc_4_2_f, 
  agd_thr7_pc_4_2_f, 
  agd_ict_wrtag_bf, 
  agd_asi_bist_wrdata, 
  agd_mbist_wdata_bf, 
  ftu_paddr, 
  ftu_mbi_icv_fail, 
  agd_va_hole_excp_f, 
  agd_address0_m, 
  agd_address1_m, 
  scan_out);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire br_address0_m_reg0_scanin;
wire br_address0_m_reg0_scanout;
wire [47:0] address0_m;
wire br_address0_m_reg1_scanin;
wire br_address0_m_reg1_scanout;
wire [47:0] address0_m_rep0;
wire br_address1_m_reg0_scanin;
wire br_address1_m_reg0_scanout;
wire [47:0] address1_m;
wire br_address1_m_reg1_scanin;
wire br_address1_m_reg1_scanout;
wire [47:0] address1_m_rep0;
wire [48:0] pc_c;
wire [48:0] thr0_trap_rd_pc_bf;
wire [48:0] thr1_trap_rd_pc_bf;
wire [48:0] thr2_trap_rd_pc_bf;
wire [48:0] thr3_trap_rd_pc_bf;
wire [48:0] thr4_trap_rd_pc_bf;
wire [48:0] thr5_trap_rd_pc_bf;
wire [48:0] thr6_trap_rd_pc_bf;
wire [48:0] thr7_trap_rd_pc_bf;
wire [48:0] curr_thr_pc_bf;
wire [48:0] by_pass_pc_update_bf;
wire [48:0] thr0_pc_f;
wire [48:0] thr0_pc_before_last_bf;
wire [48:0] next_thr0_pc_bf;
wire [48:0] thr1_pc_f;
wire [48:0] thr1_pc_before_last_bf;
wire [48:0] next_thr1_pc_bf;
wire [48:0] thr2_pc_f;
wire [48:0] thr2_pc_before_last_bf;
wire [48:0] next_thr2_pc_bf;
wire [48:0] thr3_pc_f;
wire [48:0] thr3_pc_before_last_bf;
wire [48:0] next_thr3_pc_bf;
wire [48:0] thr4_pc_f;
wire [48:0] thr4_pc_before_last_bf;
wire [48:0] next_thr4_pc_bf;
wire [48:0] thr5_pc_f;
wire [48:0] thr5_pc_before_last_bf;
wire [48:0] next_thr5_pc_bf;
wire [48:0] thr6_pc_f;
wire [48:0] thr6_pc_before_last_bf;
wire [48:0] next_thr6_pc_bf;
wire [48:0] thr7_pc_f;
wire [48:0] thr7_pc_before_last_bf;
wire [48:0] next_thr7_pc_bf;
wire thr0_pc_f_reg_scanin;
wire thr0_pc_f_reg_scanout;
wire thr1_pc_f_reg_scanin;
wire thr1_pc_f_reg_scanout;
wire thr2_pc_f_reg_scanin;
wire thr2_pc_f_reg_scanout;
wire thr3_pc_f_reg_scanin;
wire thr3_pc_f_reg_scanout;
wire thr4_pc_f_reg_scanin;
wire thr4_pc_f_reg_scanout;
wire thr5_pc_f_reg_scanin;
wire thr5_pc_f_reg_scanout;
wire thr6_pc_f_reg_scanin;
wire thr6_pc_f_reg_scanout;
wire thr7_pc_f_reg_scanin;
wire thr7_pc_f_reg_scanout;
wire [48:2] inc_pc_bf;
wire [10:5] curr_thr_pc_crit_bf;
wire [10:5] inc_pc_crit_bf;
wire [48:0] thr0_pc_muxed_f;
wire [48:0] thr1_pc_muxed_f;
wire [48:0] thr2_pc_muxed_f;
wire [48:0] thr3_pc_muxed_f;
wire [48:0] thr4_pc_muxed_f;
wire [48:0] thr5_pc_muxed_f;
wire [48:0] thr6_pc_muxed_f;
wire [48:0] thr7_pc_muxed_f;
wire [48:0] new_thr_pc_bf;
wire tcu_muxtest_rep1;
wire [48:0] next_pc_bf;
wire [47:13] pc_tag_1;
wire [47:13] pc_tag;
wire [47:13] pc_tag_buf;
wire pc_f_reg_scanin;
wire pc_f_reg_scanout;
wire [48:0] pc_f;
wire [1:0] pc_f_unused;
wire pc_f_incr;
wire inc_pc_f_top_data;
wire [1:0] nc_crit_unused;
wire inc_crit_cout_unused;
wire [52:48] pc_f_1_unused;
wire [48:37] inc_pc_bf_top_inc;
wire pc_f_2_unused;
wire [47:47] pc_f_;
wire [52:49] pc_f_3_unused;
wire [48:2] by_pass_pc_addr_to_buf;
wire by_pass_pc_addr_bf_incr_to_buf;
wire [48:2] by_pass_inc_pc_bf;
wire inc_by_pass_pc_addr_bf_top_data;
wire [52:48] by_pass_pc_addr_bf_1_unused;
wire [48:37] by_pass_inc_pc_bf_top_inc;
wire by_pass_pc_addr_bf_2_unused;
wire [48:2] by_pass_pc_addr_bf;
wire [47:47] by_pass_pc_addr_bf_;
wire [52:49] by_pass_pc_addr_bf_3_unused;
wire [5:0] agd_mbist_addr_bf;
wire [2:0] agd_mbist_cmpsel_bf;
wire [10:0] mbist_addr_muxed;
wire tcu_muxtest_rep2;
wire [10:2] curr_thr_pc_bf_del;
wire [39:5] phys_addr_bf;
wire [1:0] agd_ic_index_bf_unused;
wire tcu_muxtest_rep4;
wire mbist_in_reg_scanin;
wire mbist_in_reg_scanout;
wire [7:0] agd_mbist_wdata_f;
wire mbi_icv_read_en_bf;
wire mbi_icv_read_en_f;
wire [7:0] agd_mbist_wdata_c;
wire mbi_icv_read_en_c;
wire [10:6] inv_addr_bf;
wire [48:0] pc_wo_by_pass_c;
wire [48:2] by_pass_pc_addr_f;
wire [48:2] by_pass_pc_addr_c;
wire [48:2] pc_c_to_buf;
wire pc_wo_by_pass_c_reg_scanin;
wire pc_wo_by_pass_c_reg_scanout;
wire by_pass_sel_reg_scanin;
wire by_pass_sel_reg_scanout;
wire [7:0] by_pass_sel_bf;
wire [4:2] by_pass_inc_pc_to_buf;
wire by_pass_pc_f_reg_scanin;
wire by_pass_pc_f_reg_scanout;
wire by_pass_pc_c_reg_scanin;
wire by_pass_pc_c_reg_scanout;
wire phys_addr_bf_reg_scanin;
wire phys_addr_bf_reg_scanout;
wire [3:0] tag_parity;
wire ic_tag_parity;
wire inv_addr_bf_reg_scanin;
wire inv_addr_bf_reg_scanout;
wire [5:5] agd_ic_index_f;
wire [7:0] itlb_valid_dupl_f;
wire tcu_muxtest_rep3;
wire tag_data_29_nand_0;
wire tag_data_29_nand_1;
wire tag_data_29_nand_2;
wire tag_data_29;
wire valid_c_reg_a_scanin;
wire valid_c_reg_a_scanout;
wire [31:0] icv_valid_c;
wire valid_c_reg_b_scanin;
wire valid_c_reg_b_scanout;
wire agd_icv_fail_l;
wire agd_icv_fail;


input tcu_scan_en;
input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;
input tcu_muxtest;
input [5:0] mbi_addr;
input [2:0] mbi_cmpsel;
input [7:0] mbi_wdata;
input       mbi_icv_read_en;

input [2:0] ftp_thr0_trprdpc_sel_bf;  // 0in bits_on -max 1 
input [2:0] ftp_thr1_trprdpc_sel_bf;  // 0in bits_on -max 1 
input [2:0] ftp_thr2_trprdpc_sel_bf;  // 0in bits_on -max 1 
input [2:0] ftp_thr3_trprdpc_sel_bf;  // 0in bits_on -max 1 
input [2:0] ftp_thr4_trprdpc_sel_bf;  // 0in bits_on -max 1 
input [2:0] ftp_thr5_trprdpc_sel_bf;  // 0in bits_on -max 1 
input [2:0] ftp_thr6_trprdpc_sel_bf;  // 0in bits_on -max 1 
input [2:0] ftp_thr7_trprdpc_sel_bf;  // 0in bits_on -max 1 
            
input [3:0] agc_thr0_pcf_sel_bf;     // 0in one_hot
input [3:0] agc_thr1_pcf_sel_bf;     // 0in one_hot
input [3:0] agc_thr2_pcf_sel_bf;     // 0in one_hot
input [3:0] agc_thr3_pcf_sel_bf;     // 0in one_hot
input [3:0] agc_thr4_pcf_sel_bf;     // 0in one_hot
input [3:0] agc_thr5_pcf_sel_bf;     // 0in one_hot
input [3:0] agc_thr6_pcf_sel_bf;     // 0in one_hot
input [3:0] agc_thr7_pcf_sel_bf;     // 0in one_hot
            
input [1:0] agc_thr0_pcf_sel_last_bf;     // 0in one_hot
input [1:0] agc_thr1_pcf_sel_last_bf;     // 0in one_hot
input [1:0] agc_thr2_pcf_sel_last_bf;     // 0in one_hot
input [1:0] agc_thr3_pcf_sel_last_bf;     // 0in one_hot
input [1:0] agc_thr4_pcf_sel_last_bf;     // 0in one_hot
input [1:0] agc_thr5_pcf_sel_last_bf;     // 0in one_hot
input [1:0] agc_thr6_pcf_sel_last_bf;     // 0in one_hot
input [1:0] agc_thr7_pcf_sel_last_bf;     // 0in one_hot

input       ftp_thr0_sel_br_bf      ;
input       ftp_thr1_sel_br_bf      ;
input       ftp_thr2_sel_br_bf      ;
input       ftp_thr3_sel_br_bf      ;
input       ftp_thr4_sel_br_bf      ;
input       ftp_thr5_sel_br_bf      ;
input       ftp_thr6_sel_br_bf      ;
input       ftp_thr7_sel_br_bf      ;

input [3:0] agc_sel_inv_index;     // 0in bits_on -max 1

input [3:0] agc_pc_sel_for_c;     // 0in bits_on -max 1

input [31:0] icv_valid_f;     
input [39:3] asi_addr_bf;     

input       agc_thr0_byp_incr_bit5 ;
input       agc_thr1_byp_incr_bit5 ;
input       agc_thr2_byp_incr_bit5 ;
input       agc_thr3_byp_incr_bit5 ;
input       agc_thr4_byp_incr_bit5 ;
input       agc_thr5_byp_incr_bit5 ;
input       agc_thr6_byp_incr_bit5 ;
input       agc_thr7_byp_incr_bit5 ;

input [4:2] agc_thr0_byp_pc_update_bf ;
input [4:2] agc_thr1_byp_pc_update_bf ;
input [4:2] agc_thr2_byp_pc_update_bf ;
input [4:2] agc_thr3_byp_pc_update_bf ;
input [4:2] agc_thr4_byp_pc_update_bf ;
input [4:2] agc_thr5_byp_pc_update_bf ;
input [4:2] agc_thr6_byp_pc_update_bf ;
input [4:2] agc_thr7_byp_pc_update_bf ;

input [7:0] ftp_new_thr_sel_bf;
input [2:0] ftp_ict_data_sel_bf; 
input [5:0] ftp_pc_sel_am;
input [2:0] ftp_pc_sel_tag_part1;
input [3:0] ftp_pc_sel_tag_part2;
input [1:0] ftp_pc_sel_tag_pc_bot;
input [1:0] ftp_pc_sel_tag_pc_top;
// input [4:0] agc_pc_sel_am_final;
input       ftp_any_thr_clken;


input       ftp_sel_icv_mbist_addr;
input [4:0] ftp_icaddr_sel_first_mux;
// input [3:0] ftp_icaddr_sel_final_mux;
// input  [4:0] ftp_icaddr_sel_nb0_nb1;
// input  [4:0] ftp_icaddr_sel_b0_nb1;
// input  [4:0] ftp_icaddr_sel_nb0_b1;
// input  [4:0] ftp_icaddr_sel_b0_b1;

// input        dec_nb0_nb1_bf;
// input        dec_b0_nb1_bf;
// input        dec_nb0_b1_bf;
// input        dec_b0_b1_bf;

            
input [47:2] tlu_trap_pc_0;
input [47:2] tlu_trap_pc_1;

input [47:13] itc_va        ;
            
input [47:0] exu_address0_e;
input [47:0] exu_address1_e;
            
input [47:2] tlu_npc_w;
            
input [39:5] cmu_fill_paddr ;
input [32:0] asi_wr_data ;
input [10:6] cmu_icache_invalidate_index ;
input        cmu_thr0_data_ready;
input        cmu_thr1_data_ready;
input        cmu_thr2_data_ready;
input        cmu_thr3_data_ready;
input        cmu_thr4_data_ready;
input        cmu_thr5_data_ready;
input        cmu_thr6_data_ready;
input        cmu_thr7_data_ready;


output [2:0]  agd_direct_map_rep_way;
output [7:0]  agd_itlb_valid_f;
output [7:0]  agd_itlb_valid_fast_f;
output [7:0]  agd_itlb_valid_dupl_f;
output [47:0] ifu_agd_pc_bf ;

output [10:5] agd_ict_index_bf ;
output [10:2] agd_ic_index_bf ;
output [10:6] agd_icv_windex_bf ;

output [47:2] ifu_agd_pc_f ;
output [4:2] agd_thr0_pc_4_2_f ;
output [4:2] agd_thr1_pc_4_2_f ;
output [4:2] agd_thr2_pc_4_2_f ;
output [4:2] agd_thr3_pc_4_2_f ;
output [4:2] agd_thr4_pc_4_2_f ;
output [4:2] agd_thr5_pc_4_2_f ;
output [4:2] agd_thr6_pc_4_2_f ;
output [4:2] agd_thr7_pc_4_2_f ;

output [29:0] agd_ict_wrtag_bf;
output [32:0] agd_asi_bist_wrdata;
output [7:0]  agd_mbist_wdata_bf;
output [12:0] ftu_paddr;

output        ftu_mbi_icv_fail;
output        agd_va_hole_excp_f;

output [4:2]  agd_address0_m ;
output [4:2]  agd_address1_m ;

output scan_out;

// assign pce_ov = tcu_pce_ov;
// assign stop = tcu_clk_stop;
assign stop = 1'b0 ;
// assign siclk = spc_aclk;
// assign soclk = spc_bclk;

ifu_ftu_agd_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0  (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);
///////////////////////////////////////////////////////////////////////
// Flop exu_addresses                                                //
///////////////////////////////////////////////////////////////////////
ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 br_address0_m_reg0  (
 .scan_in(br_address0_m_reg0_scanin),
 .scan_out(br_address0_m_reg0_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( exu_address0_e[47:24]),
 .dout( address0_m[47:24]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));
ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 br_address0_m_reg1  (
 .scan_in(br_address0_m_reg1_scanin),
 .scan_out(br_address0_m_reg1_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( exu_address0_e[23:0]),
 .dout( address0_m[23:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_agd_dp_buff_macro__dbuff_48x__rep_1__stack_50c__width_48 br_address0_m_rep0  (
 .din ( address0_m[47:0]     ),
 .dout( address0_m_rep0[47:0]     ));

// buff_macro br_address0_m_rep01 (width=48,stack=50c,dbuff=32x) (
//  .din ( address0_m_rep0[47:0]     ),
//  .dout( address0_m_rep01[47:0]     ));

ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 br_address1_m_reg0  (
 .scan_in(br_address1_m_reg0_scanin),
 .scan_out(br_address1_m_reg0_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( exu_address1_e[47:24]),
 .dout( address1_m[47:24]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));
ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 br_address1_m_reg1  (
 .scan_in(br_address1_m_reg1_scanin),
 .scan_out(br_address1_m_reg1_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( exu_address1_e[23:0]),
 .dout( address1_m[23:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_agd_dp_buff_macro__dbuff_48x__rep_1__stack_50c__width_48 br_address1_m_rep0  (
 .din ( address1_m[47:0]     ),
 .dout( address1_m_rep0[47:0]     ));

// buff_macro br_address1_m_rep01 (width=48,stack=50c,dbuff=32x) (
//  .din ( address1_m_rep0[47:0]     ),
//  .dout( address1_m_rep01[47:0]     ));

assign agd_address0_m[4:2] = address0_m_rep0[4:2] ;
assign agd_address1_m[4:2] = address1_m_rep0[4:2] ;
///////////////////////////////////////////////////////////////////////
// First level of redirection muxing for thread_0 to thread_7        //
///////////////////////////////////////////////////////////////////////

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr0_trp_rd_pc_mux  (
 .din0( {1'b0,tlu_trap_pc_0[47:2],2'b00}),      // trap pc from thread_g_0
 .din1( {1'b0,tlu_npc_w[47:2],2'b00}),         // npc at w stage,thread_g_0 
 .din2( pc_c[48:0]),                 // pc  at c stage 
 .sel0( ftp_thr0_trprdpc_sel_bf[0]),
 .sel1( ftp_thr0_trprdpc_sel_bf[1]),
 .sel2( ftp_thr0_trprdpc_sel_bf[2]),
 .dout( thr0_trap_rd_pc_bf[48:0]                               ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr1_trp_rd_pc_mux  (
 .din0( {1'b0,tlu_trap_pc_0[47:2],2'b00}),      // trap pc from thread_g_0
 .din1( {1'b0,tlu_npc_w[47:2],2'b00}),         // npc at w stage,thread_g_0 
 .din2( pc_c[48:0]),                 // pc  at c stage 
 .sel0( ftp_thr1_trprdpc_sel_bf[0]),
 .sel1( ftp_thr1_trprdpc_sel_bf[1]),
 .sel2( ftp_thr1_trprdpc_sel_bf[2]),
 .dout( thr1_trap_rd_pc_bf[48:0]                               ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr2_trp_rd_pc_mux  (
 .din0( {1'b0,tlu_trap_pc_0[47:2],2'b00}),      // trap pc from thread_g_0
 .din1( {1'b0,tlu_npc_w[47:2],2'b00}),         // npc at w stage,thread_g_0 
 .din2( pc_c[48:0]),                 // pc  at c stage 
 .sel0( ftp_thr2_trprdpc_sel_bf[0]),
 .sel1( ftp_thr2_trprdpc_sel_bf[1]),
 .sel2( ftp_thr2_trprdpc_sel_bf[2]),
 .dout( thr2_trap_rd_pc_bf[48:0]                               ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr3_trp_rd_pc_mux  (
 .din0( {1'b0,tlu_trap_pc_0[47:2],2'b00}),      // trap pc from thread_g_0
 .din1( {1'b0,tlu_npc_w[47:2],2'b00}),         // npc at w stage,thread_g_0 
 .din2( pc_c[48:0]),                 // pc  at c stage 
 .sel0( ftp_thr3_trprdpc_sel_bf[0]),
 .sel1( ftp_thr3_trprdpc_sel_bf[1]),
 .sel2( ftp_thr3_trprdpc_sel_bf[2]),
 .dout( thr3_trap_rd_pc_bf[48:0]                               ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr4_trp_rd_pc_mux  (
 .din0( {1'b0,tlu_trap_pc_1[47:2],2'b00}),      // trap pc from thread_g_1
 .din1( {1'b0,tlu_npc_w[47:2],2'b00}),         // npc at w stage,thread_g_1 
 .din2( pc_c[48:0]),                 // pc  at c stage 
 .sel0( ftp_thr4_trprdpc_sel_bf[0]),
 .sel1( ftp_thr4_trprdpc_sel_bf[1]),
 .sel2( ftp_thr4_trprdpc_sel_bf[2]),
 .dout( thr4_trap_rd_pc_bf[48:0]                               ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr5_trp_rd_pc_mux  (
 .din0( {1'b0,tlu_trap_pc_1[47:2],2'b00}),      // trap pc from thread_g_1
 .din1( {1'b0,tlu_npc_w[47:2],2'b00}),         // npc at w stage,thread_g_1 
 .din2( pc_c[48:0]),                 // pc  at c stage 
 .sel0( ftp_thr5_trprdpc_sel_bf[0]),
 .sel1( ftp_thr5_trprdpc_sel_bf[1]),
 .sel2( ftp_thr5_trprdpc_sel_bf[2]),
 .dout( thr5_trap_rd_pc_bf[48:0]                               ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr6_trp_rd_pc_mux  (
 .din0( {1'b0,tlu_trap_pc_1[47:2],2'b00}),      // trap pc from thread_g_1
 .din1( {1'b0,tlu_npc_w[47:2],2'b00}),         // npc at w stage,thread_g_1 
 .din2( pc_c[48:0]),                 // pc  at c stage 
 .sel0( ftp_thr6_trprdpc_sel_bf[0]),
 .sel1( ftp_thr6_trprdpc_sel_bf[1]),
 .sel2( ftp_thr6_trprdpc_sel_bf[2]),
 .dout( thr6_trap_rd_pc_bf[48:0]                               ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 thr7_trp_rd_pc_mux  (
 .din0( {1'b0,tlu_trap_pc_1[47:2],2'b00}),      // trap pc from thread_g_1
 .din1( {1'b0,tlu_npc_w[47:2],2'b00}),         // npc at w stage,thread_g_1 
 .din2( pc_c[48:0]),                 // pc  at c stage 
 .sel0( ftp_thr7_trprdpc_sel_bf[0]),
 .sel1( ftp_thr7_trprdpc_sel_bf[1]),
 .sel2( ftp_thr7_trprdpc_sel_bf[2]),
 .dout( thr7_trap_rd_pc_bf[48:0]                               ));

///////////////////////////////////////////////////////////////////////
// Second level of redirection muxing                                //
///////////////////////////////////////////////////////////////////////
ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr0_pc_bf_mux  (
 .din0( thr0_trap_rd_pc_bf[48:0]),       // redirection pc from 1st level of muxing
 .din1( curr_thr_pc_bf[48:0]),           // Current thread incr  pc. 
 .din2( by_pass_pc_update_bf[48:0]),      // select bypass incremented addr. 
 .din3( thr0_pc_f[48:0]),                // Hold the pc_f for the this thread
 .sel0( agc_thr0_pcf_sel_bf[0]),
 .sel1( agc_thr0_pcf_sel_bf[1]),
 .sel2( agc_thr0_pcf_sel_bf[2]),
 .sel3( agc_thr0_pcf_sel_bf[3]),
 .dout( thr0_pc_before_last_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr0_pc_bf_last_mux  (
 .din0( {1'b0,address0_m_rep0[47:0]}),    // br misprediction pc from thread_g_0
 .din1( thr0_pc_before_last_bf[48:0]),       // redirection pc from 1st level of muxing
 .sel0( agc_thr0_pcf_sel_last_bf[0]),
 .sel1( agc_thr0_pcf_sel_last_bf[1]),
 .dout( next_thr0_pc_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr1_pc_bf_mux  (
 .din0( thr1_trap_rd_pc_bf[48:0]),       // redirection pc from 1st level of muxing
 .din1( curr_thr_pc_bf[48:0]),           // Current thread incr  pc. 
 .din2( by_pass_pc_update_bf[48:0]),         // select bypass incremented addr. 
 .din3( thr1_pc_f[48:0]),                // Hold the pc_f for the this thread
 .sel0( agc_thr1_pcf_sel_bf[0]),
 .sel1( agc_thr1_pcf_sel_bf[1]),
 .sel2( agc_thr1_pcf_sel_bf[2]),
 .sel3( agc_thr1_pcf_sel_bf[3]),
 .dout( thr1_pc_before_last_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr1_pc_bf_last_mux  (
 .din0( {1'b0,address0_m_rep0[47:0]}),    // br misprediction pc from thread_g_0
 .din1( thr1_pc_before_last_bf[48:0]),       // redirection pc from 1st level of muxing
 .sel0( agc_thr1_pcf_sel_last_bf[0]),
 .sel1( agc_thr1_pcf_sel_last_bf[1]),
 .dout( next_thr1_pc_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr2_pc_bf_mux  (
 .din0( thr2_trap_rd_pc_bf[48:0]),       // redirection pc from 1st level of muxing
 .din1( curr_thr_pc_bf[48:0]),           // Current thread incr  pc. 
 .din2( by_pass_pc_update_bf[48:0]),         // select bypass incremented addr. 
 .din3( thr2_pc_f[48:0]),                // Hold the pc_f for the this thread
 .sel0( agc_thr2_pcf_sel_bf[0]),
 .sel1( agc_thr2_pcf_sel_bf[1]),
 .sel2( agc_thr2_pcf_sel_bf[2]),
 .sel3( agc_thr2_pcf_sel_bf[3]),
 .dout( thr2_pc_before_last_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr2_pc_bf_last_mux  (
 .din0( {1'b0,address0_m_rep0[47:0]}),    // br misprediction pc from thread_g_0
 .din1( thr2_pc_before_last_bf[48:0]),       // redirection pc from 1st level of muxing
 .sel0( agc_thr2_pcf_sel_last_bf[0]),
 .sel1( agc_thr2_pcf_sel_last_bf[1]),
 .dout( next_thr2_pc_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr3_pc_bf_mux  (
 .din0( thr3_trap_rd_pc_bf[48:0]),       // redirection pc from 1st level of muxing
 .din1( curr_thr_pc_bf[48:0]),           // Current thread incr  pc. 
 .din2( by_pass_pc_update_bf[48:0]),         // select bypass incremented addr. 
 .din3( thr3_pc_f[48:0]),                // Hold the pc_f for the this thread
 .sel0( agc_thr3_pcf_sel_bf[0]),
 .sel1( agc_thr3_pcf_sel_bf[1]),
 .sel2( agc_thr3_pcf_sel_bf[2]),
 .sel3( agc_thr3_pcf_sel_bf[3]),
 .dout( thr3_pc_before_last_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr3_pc_bf_last_mux  (
 .din0( {1'b0,address0_m_rep0[47:0]}),    // br misprediction pc from thread_g_0
 .din1( thr3_pc_before_last_bf[48:0]),       // redirection pc from 1st level of muxing
 .sel0( agc_thr3_pcf_sel_last_bf[0]),
 .sel1( agc_thr3_pcf_sel_last_bf[1]),
 .dout( next_thr3_pc_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr4_pc_bf_mux  (
 .din0( thr4_trap_rd_pc_bf[48:0]),       // redirection pc from 1st level of muxing
 .din1( curr_thr_pc_bf[48:0]),           // Current thread incr  pc. 
 .din2( by_pass_pc_update_bf[48:0]),         // select bypass incremented addr. 
 .din3( thr4_pc_f[48:0]),                // Hold the pc_f for the this thread
 .sel0( agc_thr4_pcf_sel_bf[0]),
 .sel1( agc_thr4_pcf_sel_bf[1]),
 .sel2( agc_thr4_pcf_sel_bf[2]),
 .sel3( agc_thr4_pcf_sel_bf[3]),
 .dout( thr4_pc_before_last_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr4_pc_bf_last_mux  (
 .din0( {1'b0,address1_m_rep0[47:0]}),    // br misprediction pc from thread_g_1
 .din1( thr4_pc_before_last_bf[48:0]),       // redirection pc from 1st level of muxing
 .sel0( agc_thr4_pcf_sel_last_bf[0]),
 .sel1( agc_thr4_pcf_sel_last_bf[1]),
 .dout( next_thr4_pc_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr5_pc_bf_mux  (
 .din0( thr5_trap_rd_pc_bf[48:0]),       // redirection pc from 1st level of muxing
 .din1( curr_thr_pc_bf[48:0]),           // Current thread incr  pc. 
 .din2( by_pass_pc_update_bf[48:0]),         // select bypass incremented addr. 
 .din3( thr5_pc_f[48:0]),                // Hold the pc_f for the this thread
 .sel0( agc_thr5_pcf_sel_bf[0]),
 .sel1( agc_thr5_pcf_sel_bf[1]),
 .sel2( agc_thr5_pcf_sel_bf[2]),
 .sel3( agc_thr5_pcf_sel_bf[3]),
 .dout( thr5_pc_before_last_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr5_pc_bf_last_mux  (
 .din0( {1'b0,address1_m_rep0[47:0]}),    // br misprediction pc from thread_g_1
 .din1( thr5_pc_before_last_bf[48:0]),       // redirection pc from 1st level of muxing
 .sel0( agc_thr5_pcf_sel_last_bf[0]),
 .sel1( agc_thr5_pcf_sel_last_bf[1]),
 .dout( next_thr5_pc_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr6_pc_bf_mux  (
 .din0( thr6_trap_rd_pc_bf[48:0]),       // redirection pc from 1st level of muxing
 .din1( curr_thr_pc_bf[48:0]),           // Current thread incr  pc. 
 .din2( by_pass_pc_update_bf[48:0]),         // select bypass incremented addr. 
 .din3( thr6_pc_f[48:0]),                // Hold the pc_f for the this thread
 .sel0( agc_thr6_pcf_sel_bf[0]),
 .sel1( agc_thr6_pcf_sel_bf[1]),
 .sel2( agc_thr6_pcf_sel_bf[2]),
 .sel3( agc_thr6_pcf_sel_bf[3]),
 .dout( thr6_pc_before_last_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr6_pc_bf_last_mux  (
 .din0( {1'b0,address1_m_rep0[47:0]}),    // br misprediction pc from thread_g_1
 .din1( thr6_pc_before_last_bf[48:0]),       // redirection pc from 1st level of muxing
 .sel0( agc_thr6_pcf_sel_last_bf[0]),
 .sel1( agc_thr6_pcf_sel_last_bf[1]),
 .dout( next_thr6_pc_bf[48:0]           ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 thr7_pc_bf_mux  (
 .din0( thr7_trap_rd_pc_bf[48:0]),       // redirection pc from 1st level of muxing
 .din1( curr_thr_pc_bf[48:0]),           // Current thread incr  pc. 
 .din2( by_pass_pc_update_bf[48:0]),         // select bypass incremented addr. 
 .din3( thr7_pc_f[48:0]),                // Hold the pc_f for the this thread
 .sel0( agc_thr7_pcf_sel_bf[0]),
 .sel1( agc_thr7_pcf_sel_bf[1]),
 .sel2( agc_thr7_pcf_sel_bf[2]),
 .sel3( agc_thr7_pcf_sel_bf[3]),
 .dout( thr7_pc_before_last_bf[48:0]           ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 thr7_pc_bf_last_mux  (
 .din0( {1'b0,address1_m_rep0[47:0]}),    // br misprediction pc from thread_g_1
 .din1( thr7_pc_before_last_bf[48:0]),       // redirection pc from 1st level of muxing
 .sel0( agc_thr7_pcf_sel_last_bf[0]),
 .sel1( agc_thr7_pcf_sel_last_bf[1]),
 .dout( next_thr7_pc_bf[48:0]           ));

///////////////////////////////////////////////////////////////////////
// Thread 0 to thread 7 pc_f registers                               //
///////////////////////////////////////////////////////////////////////
ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr0_pc_f_reg  (
 .scan_in(thr0_pc_f_reg_scanin),
 .scan_out(thr0_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken                 ),  
 .din ( next_thr0_pc_bf[48:0]),
 .dout( thr0_pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));
 
// buff_macro thr0_pc_f_reg_buf (width=49,stack=50c,dbuff=32x) (
//  .din ( thr0_pc_f_to_buf[48:0]     ),
//  .dout( thr0_pc_f[48:0]     ));

assign agd_thr0_pc_4_2_f[4:2] = thr0_pc_f[4:2] ;

ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr1_pc_f_reg  (
 .scan_in(thr1_pc_f_reg_scanin),
 .scan_out(thr1_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken                 ),  
 .din ( next_thr1_pc_bf[48:0]),
 .dout( thr1_pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign agd_thr1_pc_4_2_f[4:2] = thr1_pc_f[4:2] ;


ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr2_pc_f_reg  (
 .scan_in(thr2_pc_f_reg_scanin),
 .scan_out(thr2_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ( next_thr2_pc_bf[48:0]),
 .dout( thr2_pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign agd_thr2_pc_4_2_f[4:2] = thr2_pc_f[4:2] ;


ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr3_pc_f_reg  (
 .scan_in(thr3_pc_f_reg_scanin),
 .scan_out(thr3_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ( next_thr3_pc_bf[48:0]),
 .dout( thr3_pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign agd_thr3_pc_4_2_f[4:2] = thr3_pc_f[4:2] ;


ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr4_pc_f_reg  (
 .scan_in(thr4_pc_f_reg_scanin),
 .scan_out(thr4_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ( next_thr4_pc_bf[48:0]),
 .dout( thr4_pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign agd_thr4_pc_4_2_f[4:2] = thr4_pc_f[4:2] ;


ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr5_pc_f_reg  (
 .scan_in(thr5_pc_f_reg_scanin),
 .scan_out(thr5_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ( next_thr5_pc_bf[48:0]),
 .dout( thr5_pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign agd_thr5_pc_4_2_f[4:2] = thr5_pc_f[4:2] ;


ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr6_pc_f_reg  (
 .scan_in(thr6_pc_f_reg_scanin),
 .scan_out(thr6_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ( next_thr6_pc_bf[48:0]),
 .dout( thr6_pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign agd_thr6_pc_4_2_f[4:2] = thr6_pc_f[4:2] ;

ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 thr7_pc_f_reg  (
 .scan_in(thr7_pc_f_reg_scanin),
 .scan_out(thr7_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ( next_thr7_pc_bf[48:0]),
 .dout( thr7_pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign agd_thr7_pc_4_2_f[4:2] = thr7_pc_f[4:2] ;

assign curr_thr_pc_bf[48:0] = {inc_pc_bf[48:2], 2'b00} ;
assign curr_thr_pc_crit_bf[10:5] = inc_pc_crit_bf[10:5] ;
///////////////////////////////////////////////////////////////////////
// Mux between the branch address flopped and the thread pc register //
///////////////////////////////////////////////////////////////////////
ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr0_pc_reg_mux  (
 .din0( {1'b0,address0_m_rep0[47:0]}),     // branch address 0 flopped
 .din1( thr0_pc_f[48:0]),      // thread 0 pc_f
 .sel0( ftp_thr0_sel_br_bf),
 .dout( thr0_pc_muxed_f[48:0]         ));

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr1_pc_reg_mux  (
 .din0( {1'b0,address0_m_rep0[47:0]}),     // branch address 0 flopped
 .din1( thr1_pc_f[48:0]),      // thread 1 pc_f
 .sel0( ftp_thr1_sel_br_bf),
 .dout( thr1_pc_muxed_f[48:0]         ));

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr2_pc_reg_mux  (
 .din0( {1'b0,address0_m_rep0[47:0]}),     // branch address 0 flopped
 .din1( thr2_pc_f[48:0]),      // thread 2 pc_f
 .sel0( ftp_thr2_sel_br_bf),
 .dout( thr2_pc_muxed_f[48:0]         ));

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr3_pc_reg_mux  (
 .din0( {1'b0,address0_m_rep0[47:0]}),     // branch address 0 flopped
 .din1( thr3_pc_f[48:0]),      // thread 3 pc_f
 .sel0( ftp_thr3_sel_br_bf),
 .dout( thr3_pc_muxed_f[48:0]         ));

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr4_pc_reg_mux  (
 .din0( {1'b0,address1_m_rep0[47:0]}),     // branch address 1 flopped
 .din1( thr4_pc_f[48:0]),      // thread 4 pc_f
 .sel0( ftp_thr4_sel_br_bf),
 .dout( thr4_pc_muxed_f[48:0]         ));

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr5_pc_reg_mux  (
 .din0( {1'b0,address1_m_rep0[47:0]}),     // branch address 1 flopped
 .din1( thr5_pc_f[48:0]),      // thread 5 pc_f
 .sel0( ftp_thr5_sel_br_bf),
 .dout( thr5_pc_muxed_f[48:0]         ));

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr6_pc_reg_mux  (
 .din0( {1'b0,address1_m_rep0[47:0]}),     // branch address 1 flopped
 .din1( thr6_pc_f[48:0]),      // thread 6 pc_f
 .sel0( ftp_thr6_sel_br_bf),
 .dout( thr6_pc_muxed_f[48:0]         ));

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 thr7_pc_reg_mux  (
 .din0( {1'b0,address1_m_rep0[47:0]}),     // branch address 1 flopped
 .din1( thr7_pc_f[48:0]),      // thread 7 pc_f
 .sel0( ftp_thr7_sel_br_bf),
 .dout( thr7_pc_muxed_f[48:0]         ));


///////////////////////////////////////////////////////////////////////
// One mux for all eight PCs from the different threads.             //
///////////////////////////////////////////////////////////////////////

// buff_macro tst_mux_rep0 (width=1,dbuff=48x) (
//  .din ( tcu_muxtest     ),
//  .dout( tcu_muxtest_rep0     ));

ifu_ftu_agd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__stack_50c__width_49 new_thr_pc_mux  (
 .din0( thr0_pc_muxed_f[48:0]),      // thread 0 pc_f
 .din1( thr1_pc_muxed_f[48:0]),      // thread 1 pc_f
 .din2( thr2_pc_muxed_f[48:0]),      // thread 2 pc_f
 .din3( thr3_pc_muxed_f[48:0]),      // thread 3 pc_f
 .din4( thr4_pc_muxed_f[48:0]),      // thread 4 pc_f
 .din5( thr5_pc_muxed_f[48:0]),      // thread 5 pc_f
 .din6( thr6_pc_muxed_f[48:0]),      // thread 6 pc_f
 .din7( thr7_pc_muxed_f[48:0]),      // thread 7 pc_f
//  .muxtst (tcu_muxtest_rep0),
 .sel0( ftp_new_thr_sel_bf[0]),
 .sel1( ftp_new_thr_sel_bf[1]),
 .sel2( ftp_new_thr_sel_bf[2]),
 .sel3( ftp_new_thr_sel_bf[3]),
 .sel4( ftp_new_thr_sel_bf[4]),
 .sel5( ftp_new_thr_sel_bf[5]),
 .sel6( ftp_new_thr_sel_bf[6]),
 .sel7( ftp_new_thr_sel_bf[7]),
 .dout( new_thr_pc_bf[48:0]         ));

// mux_macro new_thr_pc_crit_mux (width=6,ports=8,mux=aonpe,stack=6l,dmux=8x,buffsel=none) (
//  .din0( thr0_pc_muxed_f[10:5]),      // thread 0 pc_f
//  .din1( thr1_pc_muxed_f[10:5]),      // thread 1 pc_f
//  .din2( thr2_pc_muxed_f[10:5]),      // thread 2 pc_f
//  .din3( thr3_pc_muxed_f[10:5]),      // thread 3 pc_f
//  .din4( thr4_pc_muxed_f[10:5]),      // thread 4 pc_f
//  .din5( thr5_pc_muxed_f[10:5]),      // thread 5 pc_f
//  .din6( thr6_pc_muxed_f[10:5]),      // thread 6 pc_f
//  .din7( thr7_pc_muxed_f[10:5]),      // thread 7 pc_f
//  .sel0( ftp_new_thr_sel_bf[0]),
//  .sel1( ftp_new_thr_sel_bf[1]),
//  .sel2( ftp_new_thr_sel_bf[2]),
//  .sel3( ftp_new_thr_sel_bf[3]),
//  .sel4( ftp_new_thr_sel_bf[4]),
//  .sel5( ftp_new_thr_sel_bf[5]),
//  .sel6( ftp_new_thr_sel_bf[6]),
//  .sel7( ftp_new_thr_sel_bf[7]),
//  .dout( new_thr_pc_crit_bf[10:5]         ));

// buff_macro new_thr_pc_buf (width=49,stack=50c) (
//  .din( new_thr_pc_to_buf[48:0]         ) ,
//  .dout( new_thr_pc_bf[48:0]         ));

///////////////////////////////////////////////////////////////////////
// Final mux for the PC_F                                            //
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////

ifu_ftu_agd_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep1  (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep1     ));

ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_6__stack_50c__width_49 pc_f_am_mux  (
 .din0( new_thr_pc_bf[48:0]),             // new fetch thread pc 
 .din1( curr_thr_pc_bf[48:0]),            // current thread incr pc.  
 .din2( {17'b0, new_thr_pc_bf[31:0]}),    // new fetch thread pc am=1 
 .din3( {17'b0, curr_thr_pc_bf[31:0]}),   // current thread next pc. am=1  
 .din4( {1'b0, itc_va[47:13],13'b0}),     // itlb va address 
 .din5( {1'b0, asi_addr_bf[39:5],13'b0}), // itlb asi=53 translation request 
 .muxtst (tcu_muxtest_rep1),
 .sel0( ftp_pc_sel_am[0]),
 .sel1( ftp_pc_sel_am[1]),
 .sel2( ftp_pc_sel_am[2]),
 .sel3( ftp_pc_sel_am[3]),
 .sel4( ftp_pc_sel_am[4]),
 .sel5( ftp_pc_sel_am[5]),
 .dout( next_pc_bf[48:0]         ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_20r__width_19 pc_bf_to_itb_part1  (
 .din0( curr_thr_pc_bf[31:13]),            // current thread incr pc.  
 .din1( itc_va[31:13]),                    // itlb va address 
 .din2( asi_addr_bf[23:5]),                // itlb asi=53 translation request 
 .sel0( ftp_pc_sel_tag_part1[0]),
 .sel1( ftp_pc_sel_tag_part1[1]),
 .sel2( ftp_pc_sel_tag_part1[2]),
 .dout( pc_tag_1[31:13]         ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_20c__width_16 pc_bf_to_itb_part2  (
 .din0( curr_thr_pc_bf[47:32]),            // current thread incr pc.  
 .din1( itc_va[47:32]),                    // itlb va address 
 .din2( asi_addr_bf[39:24]),               // itlb asi=53 translation request 
 .din3( 16'h0000),                         // itlb asi=53 translation request 
 .sel0( ftp_pc_sel_tag_part2[0]),
 .sel1( ftp_pc_sel_tag_part2[1]),
 .sel2( ftp_pc_sel_tag_part2[2]),
 .sel3( ftp_pc_sel_tag_part2[3]),
 .dout( pc_tag_1[47:32]         ));

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_20c__width_19 pc_bf_to_itb_bot  (
 .din0( new_thr_pc_bf[31:13]),            // current thread incr pc.  
 .din1( pc_tag_1[31:13]),                 // itlb va address 
 .sel0( ftp_pc_sel_tag_pc_bot[0]),
 .sel1( ftp_pc_sel_tag_pc_bot[1]),
 .dout( pc_tag[31:13]         ));


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_16c__width_16 pc_bf_to_itb_top  (
 .din0( new_thr_pc_bf[47:32]),            // current thread incr pc.  
 .din1( pc_tag_1[47:32]),     // itlb va address 
 .sel0( ftp_pc_sel_tag_pc_top[0]),
 .sel1( ftp_pc_sel_tag_pc_top[1]),
 .dout( pc_tag[47:32]         ));

ifu_ftu_agd_dp_buff_macro__dbuff_40x__rep_1__width_35 pc_tag_buffer  (
  .din ( pc_tag[47:13]         ),
  .dout( pc_tag_buf[47:13]         ));

// mux_macro pc_f_mux (width=49,ports=5,mux=aonpe,stack=50c,dmux=8x) (
//  .din0( next_am_pc_bf[48:0]),             // Normal path 
//  .din1( {1'b0, exu_address0_e[47:0]}),    // br0 misprediction pc am=0 
//  .din2( {17'b0, exu_address0_e[31:0]}),   // br0 target address am=1 
//  .din3( {1'b0, exu_address1_e[47:0]}),    // br1 misprediction pc am=0 
//  .din4( {17'b0, exu_address1_e[31:0]}),   // br1 target address am=1 
//  .sel0( agc_pc_sel_am_final[0]),
//  .sel1( agc_pc_sel_am_final[1]),
//  .sel2( agc_pc_sel_am_final[2]),
//  .sel3( agc_pc_sel_am_final[3]),
//  .sel4( agc_pc_sel_am_final[4]),
//  .dout( next_pc_bf[48:0]         ));

// buff_macro pc_f_mux_buf (width=49,stack=50c) (
//  .din ( next_pc_bf_to_buf[48:0]         ),
//  .dout( next_pc_bf[48:0]         ));

assign ifu_agd_pc_bf[47:0] = {pc_tag_buf[47:13],next_pc_bf[12:0]} ;

///////////////////////////////////////////////////////////////////////
// PC_F (fetch address at F stage)                                   //
///////////////////////////////////////////////////////////////////////
ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 pc_f_reg  (
 .scan_in(pc_f_reg_scanin),
 .scan_out(pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ( next_pc_bf[48:0]),
 .dout( pc_f[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign ifu_agd_pc_f[47:2] = pc_f[47:2] ;
assign pc_f_unused[1:0] = pc_f[1:0] ;
assign agd_direct_map_rep_way[2:0] = pc_f[13:11] ;
///////////////////////////////////////////////////////////////////////
// Custom incrementor.                                               //
///////////////////////////////////////////////////////////////////////


////////////////////////////////////////////
// pc_f[47:4] is incremented depending // 
// on the bits [3:0]                      //
////////////////////////////////////////////

// assign inc_pc_bf[4] = (!pc_f[4]);
// assign inc_pc_bf[3] = (!pc_f[4]&pc_f[3]);
// assign inc_pc_bf[2] = (!pc_f[4]&pc_f[2]);
// assign pc_f_incr = (pc_f[4]);

ifu_ftu_agd_dp_inv_macro__stack_2c__width_1 pc_f_incr_b4   (
    .din(pc_f[4]),
    .dout(inc_pc_bf[4])
);

ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 pc_f_incr_b3    (
    .din0(inc_pc_bf[4]),
    .din1(pc_f[3]),
    .dout(inc_pc_bf[3])
);

ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 pc_f_incr_b2    (
    .din0(inc_pc_bf[4]),
    .din1(pc_f[2]),
    .dout(inc_pc_bf[2])
);
assign pc_f_incr = pc_f[4] ;


ifu_ftu_agd_dp_increment_macro__dincr_8x__width_32 pc_f_data_32b_inc   (
  .din( pc_f[36:5] ) ,
  .cin(pc_f_incr ) ,
  .dout(inc_pc_bf[36:5] ) ,
  .cout(inc_pc_f_top_data )) ;

ifu_ftu_agd_dp_increment_macro__dincr_8x__width_8 pc_f_data_8b_crit_inc   (
  .din( {2'b00,pc_f[10:5]} ) ,
  .cin(pc_f_incr) ,
  .dout({nc_crit_unused[1:0],inc_pc_crit_bf[10:5]} ) ,
  .cout(inc_crit_cout_unused )) ;

ifu_ftu_agd_dp_increment_macro__dincr_8x__width_16 pc_f_plus_4_16b_at_f   (
  .din( {5'b00000,pc_f[47:37]} ) ,
  .cin(1'b1 ) ,
  .dout({pc_f_1_unused[52:48], inc_pc_bf_top_inc[47:37] }) ,
  .cout(pc_f_2_unused )) ;

// assign inc_pc_bf_top_inc[48] = inc_pc_bf_top_inc[47] & ~pc_f[47] ;
ifu_ftu_agd_dp_inv_macro__stack_2c__width_1 pc_f_b47_l   (
    .din(pc_f[47]),
    .dout(pc_f_[47])
);

ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 pc_f_incr_b48    (
    .din0(pc_f_[47]),
    .din1(inc_pc_bf_top_inc[47]),
    .dout(inc_pc_bf_top_inc[48])
);


ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_16c__width_16 pc_f_p_plus4_mux  (
 .din0( {4'b0000,inc_pc_bf_top_inc[48:37]}),
 .din1( {4'b0000,pc_f[48:37]}),
 .sel0( inc_pc_f_top_data),
 .dout( {pc_f_3_unused[52:49],inc_pc_bf[48:37]}         ));


ifu_ftu_agd_dp_increment_macro__dincr_8x__width_32 by_p_data_32b_inc   (
  .din( by_pass_pc_addr_to_buf[36:5] ) ,
  .cin(by_pass_pc_addr_bf_incr_to_buf ) ,
  .dout(by_pass_inc_pc_bf[36:5] ) ,
  .cout(inc_by_pass_pc_addr_bf_top_data )) ;

ifu_ftu_agd_dp_increment_macro__dincr_8x__width_16 by_p_pc_plus_4_16b_at_bf   (
  .din( {5'b00000,by_pass_pc_addr_to_buf[47:37]} ) ,
  .cin(1'b1 ) ,
  .dout({by_pass_pc_addr_bf_1_unused[52:48], by_pass_inc_pc_bf_top_inc[47:37] }) ,
  .cout(by_pass_pc_addr_bf_2_unused )) ;

ifu_ftu_agd_dp_inv_macro__stack_2c__width_1 by_pass_pc_f_b47_l   (
    .din(by_pass_pc_addr_bf[47]),
    .dout(by_pass_pc_addr_bf_[47])
);

ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 by_pass_pc_f_incr_b48    (
    .din0(by_pass_pc_addr_bf_[47]),
    .din1(by_pass_inc_pc_bf_top_inc[47]),
    .dout(by_pass_inc_pc_bf_top_inc[48])
);


ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_16c__width_16 by_p_pc_p_plus4_mux  (
 .din0( {4'b0000,by_pass_inc_pc_bf_top_inc[48:37]}),
 .din1( {5'b00000,by_pass_pc_addr_bf[47:37]}),
 .sel0( inc_by_pass_pc_addr_bf_top_data),
 .dout( {by_pass_pc_addr_bf_3_unused[52:49],by_pass_inc_pc_bf[48:37]}         ));


ifu_ftu_agd_dp_buff_macro__dbuff_32x__rep_1__stack_50c__width_49 by_pass_inc_pc_reg_buf  (
 .din ( {by_pass_inc_pc_bf[48:2],2'b00}     ),
 .dout( by_pass_pc_update_bf[48:0]     ));

//  assign by_pass_pc_update_bf[48:0] = {by_pass_inc_pc_bf[48:2],2'b00} ;


///////////////////////////////////////////////////////////////////////
// Final mux for the ICADDR                                          //
///////////////////////////////////////////////////////////////////////

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_12c__width_11 mbist_addr_mux  (
 .din0( {agd_mbist_addr_bf[4:0],6'b0}),    // 
 .din1( {agd_mbist_addr_bf[5:0],agd_mbist_cmpsel_bf[2:0],2'b0}),    // 
 .sel0( ftp_sel_icv_mbist_addr),
 .dout( mbist_addr_muxed[10:0]                               ));

ifu_ftu_agd_dp_buff_macro__dbuff_24x__width_1 tst_mux_rep2  (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep2     ));

ifu_ftu_agd_dp_buff_macro__minbuff_1__width_9 curr_thr_pc_bf_minbuf  (
 .din ( curr_thr_pc_bf[10:2]),
 .dout( curr_thr_pc_bf_del[10:2])
);

ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_5__stack_12c__width_11 icaddr_first_mux  (
 .din0( new_thr_pc_bf[10:0]),             // new fetch thread pc 
 .din1( {curr_thr_pc_bf_del[10:2],2'b00}),// current thread incr pc.  
 .din2( {phys_addr_bf[10:5],5'b00000}),   // Icache fill write index. 
 .din3( {asi_addr_bf[11:3],2'b00}),            // Icache asi  write index. 
 .din4( mbist_addr_muxed[10:0]),    // 
 .muxtst (tcu_muxtest_rep2),
 .sel0( ftp_icaddr_sel_first_mux[0]),
 .sel1( ftp_icaddr_sel_first_mux[1]),
 .sel2( ftp_icaddr_sel_first_mux[2]),
 .sel3( ftp_icaddr_sel_first_mux[3]),
 .sel4( ftp_icaddr_sel_first_mux[4]),
.dout( {agd_ic_index_bf[10:2],agd_ic_index_bf_unused[1:0]}         ));

ifu_ftu_agd_dp_buff_macro__dbuff_24x__width_1 tst_mux_rep4  (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep4     ));

ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_5__stack_6l__width_6 ict_addr_first_mux  (
 .din0( new_thr_pc_bf[10:5]),             // new fetch thread pc 
 .din1( curr_thr_pc_crit_bf[10:5]),       // current thread incr pc.  
 .din2( phys_addr_bf[10:5]),              // Icache fill write index. 
 .din3( asi_addr_bf[11:6]),               // Icache asi  write index. 
 .din4( agd_mbist_addr_bf[5:0]),          // bist address 
 .muxtst (tcu_muxtest_rep4),
 .sel0( ftp_icaddr_sel_first_mux[0]),
 .sel1( ftp_icaddr_sel_first_mux[1]),
 .sel2( ftp_icaddr_sel_first_mux[2]),
 .sel3( ftp_icaddr_sel_first_mux[3]),
 .sel4( ftp_icaddr_sel_first_mux[4]),
.dout( agd_ict_index_bf[10:5]         ));

ifu_ftu_agd_dp_msff_macro__stack_50c__width_36 mbist_in_reg  (
 .scan_in(mbist_in_reg_scanin),
 .scan_out(mbist_in_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1    ),  
 .din ( {mbi_addr[5:0],mbi_cmpsel[2:0],mbi_wdata[7:0],agd_mbist_wdata_bf[7:0],agd_mbist_wdata_f[7:0],mbi_icv_read_en,
         mbi_icv_read_en_bf, mbi_icv_read_en_f}),
 .dout( {agd_mbist_addr_bf[5:0],agd_mbist_cmpsel_bf[2:0],agd_mbist_wdata_bf[7:0],agd_mbist_wdata_f[7:0],
         agd_mbist_wdata_c[7:0],mbi_icv_read_en_bf,mbi_icv_read_en_f, mbi_icv_read_en_c}     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// mux_macro icaddr_mux (width=11,ports=4,mux=aonpe,stack=12c,dmux=8x) (
//  .din0( agd_ic_index_first_bf[10:0]),   // 
//  .din1( exu_address0_e[10:0]),    //
//  .din2( exu_address1_e[10:0]),    // 
//  .din3( {agd_mbist_addr_bf[8:0],2'b0}),    // 
//  .sel0( ftp_icaddr_sel_final_mux[0]),
//  .sel1( ftp_icaddr_sel_final_mux[1]),
//  .sel2( ftp_icaddr_sel_final_mux[2]),
//  .sel3( ftp_icaddr_sel_final_mux[3]), 
// .dout( {agd_ic_index_bf[10:2],agd_ic_index_bf_unused[1:0]}         ));

///////////////////////////////////////////////////////////////////////
// ICache ADDR Index                                                 // 
///////////////////////////////////////////////////////////////////////


ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_12c__width_5 icv_indx_mux  (
 .din0( phys_addr_bf[10:6]),   //
 .din1( inv_addr_bf[10:6] ),    //
 .din2( asi_addr_bf[11:7] ),    //
 .din3( agd_mbist_addr_bf[4:0]),    // 
 .sel0( agc_sel_inv_index[0]),
 .sel1( agc_sel_inv_index[1]),
 .sel2( agc_sel_inv_index[2]),
 .sel3( agc_sel_inv_index[3]),
 .dout( agd_icv_windex_bf[10:6]         ));


//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
// PC at C stage.                           //
//////////////////////////////////////////////

ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_47 pc_c_mux  (
 .din0( pc_wo_by_pass_c[48:2]),                            
 .din1( by_pass_pc_addr_bf[48:2]),        
 .din2( by_pass_pc_addr_f[48:2]),        
 .din3( by_pass_pc_addr_c[48:2]),        
 .sel0( agc_pc_sel_for_c[0]),
 .sel1( agc_pc_sel_for_c[1]),
 .sel2( agc_pc_sel_for_c[2]),
 .sel3( agc_pc_sel_for_c[3]),
 .dout( pc_c_to_buf[48:2]         ));

ifu_ftu_agd_dp_buff_macro__stack_50c__width_47 pc_c_mux_buf  (
 .din ( pc_c_to_buf[48:2]         ),
 .dout( pc_c[48:2]         ));

assign pc_c[1:0]  = 2'b00 ;
ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_50c__width_49 pc_wo_by_pass_c_reg  (
 .scan_in(pc_wo_by_pass_c_reg_scanin),
 .scan_out(pc_wo_by_pass_c_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ({pc_f[48:2],2'b00}),
 .dout(pc_wo_by_pass_c[48:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign ftu_paddr[12:0] = pc_wo_by_pass_c[12:0];
assign agd_va_hole_excp_f = pc_f[48] ;


//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////

ifu_ftu_agd_dp_msff_macro__stack_8c__width_8 by_pass_sel_reg  (
 .scan_in(by_pass_sel_reg_scanin),
 .scan_out(by_pass_sel_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din ({cmu_thr7_data_ready,cmu_thr6_data_ready,cmu_thr5_data_ready,cmu_thr4_data_ready,
        cmu_thr3_data_ready,cmu_thr2_data_ready,cmu_thr1_data_ready,cmu_thr0_data_ready}),
 .dout(by_pass_sel_bf[7:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


ifu_ftu_agd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__stack_52c__width_51 by_pass_pc_mux  (
 .din0( {thr0_pc_f[48:2],agc_thr0_byp_pc_update_bf[4:2],agc_thr0_byp_incr_bit5}),
 .din1( {thr1_pc_f[48:2],agc_thr1_byp_pc_update_bf[4:2],agc_thr1_byp_incr_bit5}),
 .din2( {thr2_pc_f[48:2],agc_thr2_byp_pc_update_bf[4:2],agc_thr2_byp_incr_bit5}),
 .din3( {thr3_pc_f[48:2],agc_thr3_byp_pc_update_bf[4:2],agc_thr3_byp_incr_bit5}),
 .din4( {thr4_pc_f[48:2],agc_thr4_byp_pc_update_bf[4:2],agc_thr4_byp_incr_bit5}),
 .din5( {thr5_pc_f[48:2],agc_thr5_byp_pc_update_bf[4:2],agc_thr5_byp_incr_bit5}),
 .din6( {thr6_pc_f[48:2],agc_thr6_byp_pc_update_bf[4:2],agc_thr6_byp_incr_bit5}),
 .din7( {thr7_pc_f[48:2],agc_thr7_byp_pc_update_bf[4:2],agc_thr7_byp_incr_bit5}),
 .sel0( by_pass_sel_bf[0]),
 .sel1( by_pass_sel_bf[1]),
 .sel2( by_pass_sel_bf[2]),
 .sel3( by_pass_sel_bf[3]),
 .sel4( by_pass_sel_bf[4]),
 .sel5( by_pass_sel_bf[5]),
 .sel6( by_pass_sel_bf[6]),
 .sel7( by_pass_sel_bf[7]),
 .dout( {by_pass_pc_addr_to_buf[48:2],by_pass_inc_pc_to_buf[4:2], by_pass_pc_addr_bf_incr_to_buf}));

// buff_macro by_pass_pc_mux_buf (width=51,stack=52c) (
//  .din ( {by_pass_pc_addr_to_buf[48:2],by_pass_inc_pc_to_buf[4:2], by_pass_pc_addr_bf_incr_to_buf}),
//  .dout( {by_pass_pc_addr_bf[48:2],by_pass_inc_pc_bf[4:2], by_pass_pc_addr_bf_incr}));

ifu_ftu_agd_dp_buff_macro__stack_52c__width_50 by_pass_pc_mux_buf  (
 .din ( {by_pass_pc_addr_to_buf[48:2],by_pass_inc_pc_to_buf[4:2]}),
 .dout( {by_pass_pc_addr_bf[48:2],by_pass_inc_pc_bf[4:2]}));

ifu_ftu_agd_dp_msff_macro__stack_50c__width_47 by_pass_pc_f_reg  (
 .scan_in(by_pass_pc_f_reg_scanin),
 .scan_out(by_pass_pc_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din (by_pass_pc_addr_bf[48:2]),
 .dout(by_pass_pc_addr_f[48:2]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


ifu_ftu_agd_dp_msff_macro__stack_50c__width_47 by_pass_pc_c_reg  (
 .scan_in(by_pass_pc_c_reg_scanin),
 .scan_out(by_pass_pc_c_reg_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din (by_pass_pc_addr_f[48:2]),
 .dout(by_pass_pc_addr_c[48:2]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


///////////////////////////////////////////////////////////////////
// Stage the physical address to be written to the IC tags.      //
///////////////////////////////////////////////////////////////////
ifu_ftu_agd_dp_msff_macro__stack_50c__width_35 phys_addr_bf_reg  (
 .scan_in(phys_addr_bf_reg_scanin),
 .scan_out(phys_addr_bf_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1    ),  
 .din (cmu_fill_paddr[39:5]),
 .dout(phys_addr_bf[39:5]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_agd_dp_prty_macro__width_8 tag_parity_0_gen  (
        .din    (phys_addr_bf[18:11]),
        .dout   (tag_parity[0])
);

ifu_ftu_agd_dp_prty_macro__width_8 tag_parity_1_gen  (
        .din    (phys_addr_bf[26:19]),
        .dout   (tag_parity[1])
);

ifu_ftu_agd_dp_prty_macro__width_8 tag_parity_2_gen  (
        .din    (phys_addr_bf[34:27]),
        .dout   (tag_parity[2])
);

ifu_ftu_agd_dp_prty_macro__width_8 tag_parity_3_gen  (
        .din    ({3'b000,phys_addr_bf[39:35]}),
        .dout   (tag_parity[3])
);

ifu_ftu_agd_dp_prty_macro__width_4 tag_parity_gen  (
        .din    (tag_parity[3:0]),
        .dout   (ic_tag_parity)
);

ifu_ftu_agd_dp_msff_macro__stack_12c__width_6 inv_addr_bf_reg  (
 .scan_in(inv_addr_bf_reg_scanin),
 .scan_out(inv_addr_bf_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1    ),  
 .din ({cmu_icache_invalidate_index[10:6],agd_ic_index_bf[5]}),
 .dout({inv_addr_bf[10:6],agd_ic_index_f[5]}     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_8r__width_8 icv_valid_f_mux  (
 .din0( icv_valid_f[15:8]),      // 
 .din1( icv_valid_f[7:0]),      // 
 .sel0( agd_ic_index_f[5]),
 .dout( agd_itlb_valid_f[7:0]                               ));
assign agd_itlb_valid_dupl_f[7:0]  = itlb_valid_dupl_f[7:0] ;

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_8r__width_8 icv_valid_f_below_icv_mux  (
 .din0( icv_valid_f[15:8]),      // 
 .din1( icv_valid_f[7:0]),      // 
 .sel0( agd_ic_index_f[5]),
 .dout( agd_itlb_valid_fast_f[7:0]                               ));

ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_8r__width_8 icv_valid_f_2_mux  (
 .din0( icv_valid_f[31:24]),      // 
 .din1( icv_valid_f[23:16]),      // 
 .sel0( agd_ic_index_f[5]),
 .dout( itlb_valid_dupl_f[7:0]                               ));

// cmp_macro valid_err_detect (dcmp=8x,width=8) (
//     .dout( agd_ic_valid_err_l_to_buf),
//     .din0( itlb_valid_dupl_f[7:0]),
//     .din1( agd_itlb_valid_f[7:0])
// );

// buff_macro valid_err_detect_buf (width=1,stack=2r) (
//  .din ( agd_ic_valid_err_l_to_buf    ),
//  .dout( agd_ic_valid_err_l    ));

ifu_ftu_agd_dp_buff_macro__dbuff_32x__width_1 tst_mux_rep3  (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep3     ));


ifu_ftu_agd_dp_nand_macro__width_1 tag_data_mux_29_nand0  (
    .dout( tag_data_29_nand_0),
    .din0( ic_tag_parity), 
    .din1( ftp_ict_data_sel_bf[0]));

ifu_ftu_agd_dp_nand_macro__width_1 tag_data_mux_29_nand1  (
    .dout( tag_data_29_nand_1),
    .din0( asi_wr_data[29]), 
    .din1( ftp_ict_data_sel_bf[1]));

ifu_ftu_agd_dp_nand_macro__width_1 tag_data_mux_29_nand2  (
    .dout( tag_data_29_nand_2),
    .din0( agd_mbist_wdata_bf[5]), 
    .din1( ftp_ict_data_sel_bf[2]));

ifu_ftu_agd_dp_nand_macro__ports_3__width_1 tag_data_mux_29_nand3  (
    .dout( tag_data_29),
    .din0( tag_data_29_nand_0), 
    .din1( tag_data_29_nand_1), 
    .din2( tag_data_29_nand_2));


ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_3__stack_50c__width_33 tag_data_mux  (
 // .din0( {3'b000,ic_tag_parity,phys_addr_bf[39:11]}),      // 
 .din0( {4'b000,phys_addr_bf[39:11]}),      // 
 .din1( asi_wr_data[32:0]),      // 
 .din2( {agd_mbist_wdata_bf[0],agd_mbist_wdata_bf[7:0],agd_mbist_wdata_bf[7:0], agd_mbist_wdata_bf[7:0], agd_mbist_wdata_bf[7:0]}),      // 
 .muxtst (tcu_muxtest_rep3),
 .sel0( ftp_ict_data_sel_bf[0]),
 .sel1( ftp_ict_data_sel_bf[1]),
 .sel2( ftp_ict_data_sel_bf[2]),
 .dout( agd_asi_bist_wrdata[32:0]                               ));

assign agd_ict_wrtag_bf[29:0] ={tag_data_29,agd_asi_bist_wrdata[28:0]} ;


ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_16c__width_16 valid_c_reg_a  (
 .scan_in(valid_c_reg_a_scanin),
 .scan_out(valid_c_reg_a_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din (icv_valid_f[31:16]),
 .dout(icv_valid_c[31:16]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_16c__width_16 valid_c_reg_b  (
 .scan_in(valid_c_reg_b_scanin),
 .scan_out(valid_c_reg_b_scanout),
 .clk ( l2clk                ),
 .en  ( ftp_any_thr_clken    ),  
 .din (icv_valid_f[15:0]),
 .dout(icv_valid_c[15:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_agd_dp_cmp_macro__dcmp_8x__width_32 mbi_icv_fail_cmp  (
    .dout( agd_icv_fail_l),
    .din0( icv_valid_c[31:0]),
    .din1( {agd_mbist_wdata_c[7:0],agd_mbist_wdata_c[7:0],agd_mbist_wdata_c[7:0],agd_mbist_wdata_c[7:0]})
);

 ifu_ftu_agd_dp_inv_macro__width_1 icv_fail_inv_macro  (
    .dout( agd_icv_fail), 
    .din(  agd_icv_fail_l)
);

ifu_ftu_agd_dp_and_macro__width_1 icv_fail_and_qual  (
    .dout( ftu_mbi_icv_fail),
    .din0( agd_icv_fail), 
    .din1( mbi_icv_read_en_c));


// assign agd_ict_wrtag_bf[29:0] = {ic_tag_parity,phys_addr_bf[39:11]} ;

// assign se = tcu_scan_en ;
// fixscan start:
assign br_address0_m_reg0_scanin = scan_in                  ;
assign br_address0_m_reg1_scanin = br_address0_m_reg0_scanout;
assign br_address1_m_reg0_scanin = br_address0_m_reg1_scanout;
assign br_address1_m_reg1_scanin = br_address1_m_reg0_scanout;
assign thr0_pc_f_reg_scanin      = br_address1_m_reg1_scanout;
assign thr1_pc_f_reg_scanin      = thr0_pc_f_reg_scanout    ;
assign thr2_pc_f_reg_scanin      = thr1_pc_f_reg_scanout    ;
assign thr3_pc_f_reg_scanin      = thr2_pc_f_reg_scanout    ;
assign thr4_pc_f_reg_scanin      = thr3_pc_f_reg_scanout    ;
assign thr5_pc_f_reg_scanin      = thr4_pc_f_reg_scanout    ;
assign thr6_pc_f_reg_scanin      = thr5_pc_f_reg_scanout    ;
assign thr7_pc_f_reg_scanin      = thr6_pc_f_reg_scanout    ;
assign pc_f_reg_scanin           = thr7_pc_f_reg_scanout    ;
assign mbist_in_reg_scanin       = pc_f_reg_scanout         ;
assign pc_wo_by_pass_c_reg_scanin = mbist_in_reg_scanout     ;
assign by_pass_sel_reg_scanin    = pc_wo_by_pass_c_reg_scanout;
assign by_pass_pc_f_reg_scanin   = by_pass_sel_reg_scanout  ;
assign by_pass_pc_c_reg_scanin   = by_pass_pc_f_reg_scanout ;
assign phys_addr_bf_reg_scanin   = by_pass_pc_c_reg_scanout ;
assign inv_addr_bf_reg_scanin    = phys_addr_bf_reg_scanout ;
assign valid_c_reg_a_scanin      = inv_addr_bf_reg_scanout  ;
assign valid_c_reg_b_scanin      = valid_c_reg_a_scanout    ;
assign scan_out                  = valid_c_reg_b_scanout    ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__dbuff_32x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__stack_24l__width_24 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [22:0] so;

  input [23:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [23:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__dbuff_48x__rep_1__stack_50c__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_50c__width_49 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [48:0] din0;
  input sel0;
  input [48:0] din1;
  input sel1;
  input [48:0] din2;
  input sel2;
  output [48:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(49)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[48:0]),
  .in1(din1[48:0]),
  .in2(din2[48:0]),
.dout(dout[48:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_49 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [48:0] din0;
  input sel0;
  input [48:0] din1;
  input sel1;
  input [48:0] din2;
  input sel2;
  input [48:0] din3;
  input sel3;
  output [48:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(49)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[48:0]),
  .in1(din1[48:0]),
  .in2(din2[48:0]),
  .in3(din3[48:0]),
.dout(dout[48:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_49 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [48:0] din0;
  input sel0;
  input [48:0] din1;
  input sel1;
  output [48:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(49)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[48:0]),
  .in1(din1[48:0]),
.dout(dout[48:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__stack_50c__width_49 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [47:0] so;

  input [48:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [48:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(49)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[48:0]),
.si({scan_in,so[47:0]}),
.so({so[47:0],scan_out}),
.q(dout[48:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_49 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [48:0] din0;
  input [48:0] din1;
  input sel0;
  output [48:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(49)  d0_0 (
  .sel(psel1),
  .in0(din0[48:0]),
  .in1(din1[48:0]),
.dout(dout[48:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__stack_50c__width_49 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [48:0] din0;
  input sel0;
  input [48:0] din1;
  input sel1;
  input [48:0] din2;
  input sel2;
  input [48:0] din3;
  input sel3;
  input [48:0] din4;
  input sel4;
  input [48:0] din5;
  input sel5;
  input [48:0] din6;
  input sel6;
  input [48:0] din7;
  input sel7;
  output [48:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(49)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[48:0]),
  .in1(din1[48:0]),
  .in2(din2[48:0]),
  .in3(din3[48:0]),
  .in4(din4[48:0]),
  .in5(din5[48:0]),
  .in6(din6[48:0]),
  .in7(din7[48:0]),
.dout(dout[48:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__dbuff_48x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_6__stack_50c__width_49 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  muxtst, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;

  input [48:0] din0;
  input sel0;
  input [48:0] din1;
  input sel1;
  input [48:0] din2;
  input sel2;
  input [48:0] din3;
  input sel3;
  input [48:0] din4;
  input sel4;
  input [48:0] din5;
  input sel5;
  input muxtst;
  output [48:0] dout;


cl_dp1_muxbuff6_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5)
);
mux6 #(49)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .in0(din0[48:0]),
  .in1(din1[48:0]),
  .in2(din2[48:0]),
  .in3(din3[48:0]),
  .in4(din4[48:0]),
  .in5(din5[48:0]),
.dout(dout[48:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_3__stack_20r__width_19 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [18:0] din0;
  input sel0;
  input [18:0] din1;
  input sel1;
  input [18:0] din2;
  input sel2;
  output [18:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(19)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[18:0]),
  .in1(din1[18:0]),
  .in2(din2[18:0]),
.dout(dout[18:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_20c__width_16 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [15:0] din0;
  input sel0;
  input [15:0] din1;
  input sel1;
  input [15:0] din2;
  input sel2;
  input [15:0] din3;
  input sel3;
  output [15:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(16)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
  .in2(din2[15:0]),
  .in3(din3[15:0]),
.dout(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_20c__width_19 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [18:0] din0;
  input sel0;
  input [18:0] din1;
  input sel1;
  output [18:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(19)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[18:0]),
  .in1(din1[18:0]),
.dout(dout[18:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_2__stack_16c__width_16 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [15:0] din0;
  input sel0;
  input [15:0] din1;
  input sel1;
  output [15:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(16)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
.dout(dout[15:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__dbuff_40x__rep_1__width_35 (
  din, 
  dout);
  input [34:0] din;
  output [34:0] dout;


buff #(35)  d0_0 (
.in(din[34:0]),
.out(dout[34:0])
);


endmodule


//
//   invert macro
//
//


module ifu_ftu_agd_dp_inv_macro__stack_2c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ftu_agd_dp_and_macro__ports_2__stack_2c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   increment macro 
//
//


module ifu_ftu_agd_dp_increment_macro__dincr_8x__width_32 (
  din, 
  cin, 
  dout, 
  cout);
  input [31:0] din;
  input cin;
  output [31:0] dout;
  output cout;


incr #(32)  m0_0 (
.cin(cin),
.in(din[31:0]),
.out(dout[31:0]),
.cout(cout)
);


endmodule


//
//   increment macro 
//
//


module ifu_ftu_agd_dp_increment_macro__dincr_8x__width_8 (
  din, 
  cin, 
  dout, 
  cout);
  input [7:0] din;
  input cin;
  output [7:0] dout;
  output cout;


incr #(8)  m0_0 (
.cin(cin),
.in(din[7:0]),
.out(dout[7:0]),
.cout(cout)
);


endmodule


//
//   increment macro 
//
//


module ifu_ftu_agd_dp_increment_macro__dincr_8x__width_16 (
  din, 
  cin, 
  dout, 
  cout);
  input [15:0] din;
  input cin;
  output [15:0] dout;
  output cout;


incr #(16)  m0_0 (
.cin(cin),
.in(din[15:0]),
.out(dout[15:0]),
.cout(cout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_16c__width_16 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [15:0] din0;
  input [15:0] din1;
  input sel0;
  output [15:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(16)  d0_0 (
  .sel(psel1),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
.dout(dout[15:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__dbuff_32x__rep_1__stack_50c__width_49 (
  din, 
  dout);
  input [48:0] din;
  output [48:0] dout;


buff #(49)  d0_0 (
.in(din[48:0]),
.out(dout[48:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_12c__width_11 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [10:0] din0;
  input [10:0] din1;
  input sel0;
  output [10:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(11)  d0_0 (
  .sel(psel1),
  .in0(din0[10:0]),
  .in1(din1[10:0]),
.dout(dout[10:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__dbuff_24x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__minbuff_1__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_5__stack_12c__width_11 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  muxtst, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [10:0] din0;
  input sel0;
  input [10:0] din1;
  input sel1;
  input [10:0] din2;
  input sel2;
  input [10:0] din3;
  input sel3;
  input [10:0] din4;
  input sel4;
  input muxtst;
  output [10:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5 #(11)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[10:0]),
  .in1(din1[10:0]),
  .in2(din2[10:0]),
  .in3(din3[10:0]),
  .in4(din4[10:0]),
.dout(dout[10:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_5__stack_6l__width_6 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  muxtst, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [5:0] din0;
  input sel0;
  input [5:0] din1;
  input sel1;
  input [5:0] din2;
  input sel2;
  input [5:0] din3;
  input sel3;
  input [5:0] din4;
  input sel4;
  input muxtst;
  output [5:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5 #(6)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[5:0]),
  .in1(din1[5:0]),
  .in2(din2[5:0]),
  .in3(din3[5:0]),
  .in4(din4[5:0]),
.dout(dout[5:0]),
  .muxtst(muxtst)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__stack_50c__width_36 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [34:0] so;

  input [35:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [35:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(36)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[35:0]),
.si({scan_in,so[34:0]}),
.so({so[34:0],scan_out}),
.q(dout[35:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_12c__width_5 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [4:0] din0;
  input sel0;
  input [4:0] din1;
  input sel1;
  input [4:0] din2;
  input sel2;
  input [4:0] din3;
  input sel3;
  output [4:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(5)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[4:0]),
  .in1(din1[4:0]),
  .in2(din2[4:0]),
  .in3(din3[4:0]),
.dout(dout[4:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_aonpe__ports_4__stack_50c__width_47 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [46:0] din0;
  input sel0;
  input [46:0] din1;
  input sel1;
  input [46:0] din2;
  input sel2;
  input [46:0] din3;
  input sel3;
  output [46:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(47)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[46:0]),
  .in1(din1[46:0]),
  .in2(din2[46:0]),
  .in3(din3[46:0]),
.dout(dout[46:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__stack_50c__width_47 (
  din, 
  dout);
  input [46:0] din;
  output [46:0] dout;


buff #(47)  d0_0 (
.in(din[46:0]),
.out(dout[46:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_50c__width_49 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [47:0] so;

  input [48:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [48:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(49)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[48:0]),
.si({scan_in,so[47:0]}),
.so({so[47:0],scan_out}),
.q(dout[48:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__stack_8c__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__stack_52c__width_51 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [50:0] din0;
  input sel0;
  input [50:0] din1;
  input sel1;
  input [50:0] din2;
  input sel2;
  input [50:0] din3;
  input sel3;
  input [50:0] din4;
  input sel4;
  input [50:0] din5;
  input sel5;
  input [50:0] din6;
  input sel6;
  input [50:0] din7;
  input sel7;
  output [50:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(51)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[50:0]),
  .in1(din1[50:0]),
  .in2(din2[50:0]),
  .in3(din3[50:0]),
  .in4(din4[50:0]),
  .in5(din5[50:0]),
  .in6(din6[50:0]),
  .in7(din7[50:0]),
.dout(dout[50:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__stack_52c__width_50 (
  din, 
  dout);
  input [49:0] din;
  output [49:0] dout;


buff #(50)  d0_0 (
.in(din[49:0]),
.out(dout[49:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__stack_50c__width_47 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [45:0] so;

  input [46:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [46:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(47)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[46:0]),
.si({scan_in,so[45:0]}),
.so({so[45:0],scan_out}),
.q(dout[46:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__stack_50c__width_35 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [33:0] so;

  input [34:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [34:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(35)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[34:0]),
.si({scan_in,so[33:0]}),
.so({so[33:0],scan_out}),
.q(dout[34:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module ifu_ftu_agd_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module ifu_ftu_agd_dp_prty_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output dout;


prty #(4)  m0_0 (
.in(din[3:0]),
.out(dout)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__stack_12c__width_6 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [4:0] so;

  input [5:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [5:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_pgpe__ports_2__stack_8r__width_8 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [7:0] din0;
  input [7:0] din1;
  input sel0;
  output [7:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(8)  d0_0 (
  .sel(psel1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_agd_dp_buff_macro__dbuff_32x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ifu_ftu_agd_dp_nand_macro__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ifu_ftu_agd_dp_nand_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nand3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_mux_macro__mux_pgnpe__ports_3__stack_50c__width_33 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  muxtst, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [32:0] din0;
  input sel0;
  input [32:0] din1;
  input sel1;
  input [32:0] din2;
  input sel2;
  input muxtst;
  output [32:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3 #(33)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
  .in2(din2[32:0]),
.dout(dout[32:0]),
  .muxtst(muxtst)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_agd_dp_msff_macro__minbuff_1__stack_16c__width_16 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [14:0] so;

  input [15:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [15:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module ifu_ftu_agd_dp_cmp_macro__dcmp_8x__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module ifu_ftu_agd_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ftu_agd_dp_and_macro__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_asi_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`define BUS_CTL 64
`define BUS_VLD 63
`define BUS_ACK 62
`define BUS_RD  59
`define BUS_TID_END 58
`define BUS_TID_ST 56

`define IC_ASI  8'h66
`define TG_ASI  8'h67
`define ITD_ASI 8'h55
`define ITT_ASI 8'h56
`define ITH_ASI 8'h53
`define ASI 2'b00
`define IT_VA 48'h000000000FF8

module  ifu_ftu_asi_ctl (
  tcu_scan_en, 
  l2clk, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  scan_in, 
  rng_in_cdbus, 
  ic_rd_data, 
  tg_rd_data, 
  it_rd_data, 
  agc_vl_data_c, 
  ftp_asi_ic_rd_done, 
  ftp_asi_ic_wr_done, 
  ftp_asi_tg_rd_done, 
  ftp_asi_tg_wr_done, 
  ftp_asi_it_rd_done, 
  asi_wr_data, 
  asi_ic_rd_req, 
  asi_ic_wr_req, 
  asi_tg_rd_req, 
  asi_tg_wr_req, 
  asi_itd_rd_req, 
  asi_itt_rd_req, 
  asi_ith_det_req, 
  asi_wr_request, 
  asi_rd_request, 
  scan_out, 
  asi_addr_bf, 
  asi_way_bf, 
  asi_tid, 
  ifu_rngl_cdbus);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire asi_rd_data_rdy;
wire asi_it_rd_done_p;
wire [63:0] asi_data_out;
wire asi_wr_done_in;
wire l1clk;
wire asi_it_rd_done_reg_scanin;
wire asi_it_rd_done_reg_scanout;
wire rng_stg1_data_scanin;
wire rng_stg1_data_scanout;
wire [63:0] data_1f;
wire ic_data_parity;
wire ic_par_err_inj;
wire tg_data_parity;
wire tg_par_err_inj;
wire [63:0] data_2f;
wire [1:0] vl_bits;
wire [32:0] asi_wr_data_mux;
wire asi_ic_wr_req_2f;
wire [32:0] asi_wr_data_in;
wire asi_wr_request_2f;
wire [32:0] asi_wr_data_hold;
wire wr_data_hold_scanin;
wire wr_data_hold_scanout;
wire rng_stg1_ctl_scanin;
wire rng_stg1_ctl_scanout;
wire ctl_1f;
wire asi_ic_wr_req_in;
wire asi_tg_wr_req_in;
wire wr_req_ff_scanin;
wire wr_req_ff_scanout;
wire hole_det_1;
wire indet_acc_1;
wire rng_stg2_data_scanin;
wire rng_stg2_data_scanout;
wire rng_stg2_ctl_scanin;
wire rng_stg2_ctl_scanout;
wire ctl_2f;
wire rng_stg2_decctl_scanin;
wire rng_stg2_decctl_scanout;
wire hole_det_2f;
wire indet_acc_2f;
wire next_indet_return_rd_first;
wire indet_rd_rdy_f;
wire indet_return_rd_first;
wire indet_rd_done_2;
wire indet_wr_rdy_f;
wire indet_wr_done_2;
wire rng_stg3_decctl_scanin;
wire rng_stg3_decctl_scanout;
wire indet_rd_done_3f;
wire bypass_data_3;
wire [63:0] data_2;
wire [63:0] indet_data_f;
wire valid_2;
wire [2:0] tid_2;
wire [2:0] indet_wr_tid_f;
wire [2:0] indet_rd_tid_f;
wire rdwr_2;
wire ack_2;
wire [7:0] asi_err_2;
wire [63:0] ctl_2;
wire [63:0] rng_data_out_mux;
wire rng_stg3_scanin;
wire rng_stg3_scanout;
wire rng_stg3_ctl_scanin;
wire rng_stg3_ctl_scanout;
wire indet_rd_data_scanin;
wire indet_rd_data_scanout;
wire [2:0] next_indet_wr_tid;
wire pr_tid_wr_ret_scanin;
wire pr_tid_wr_ret_scanout;
wire [2:0] next_indet_rd_tid;
wire pr_tid_rd_ret_scanin;
wire pr_tid_rd_ret_scanout;
wire [39:3] next_rd_addr_bf;
wire [39:3] asi_rd_addr_bf;
wire address_rd_reg_scanin;
wire address_rd_reg_scanout;
wire [39:3] next_wr_addr_bf;
wire [39:3] asi_wr_addr_bf;
wire address_wr_reg_scanin;
wire address_wr_reg_scanout;
wire [2:0] next_rd_way_bf;
wire [2:0] asi_rd_way_bf;
wire rd_way_bf_reg_scanin;
wire rd_way_bf_reg_scanout;
wire [2:0] next_wr_way_bf;
wire [2:0] asi_wr_way_bf;
wire wr_way_bf_reg_scanin;
wire wr_way_bf_reg_scanout;
wire next_rd_is_first;
wire true_old_wr_req_pending;
wire rd_request_pending;
wire asi_rd_is_first;
wire rd_is_first_reg_scanin;
wire rd_is_first_reg_scanout;
wire wr_request_pending;
wire next_wr_request_pending;
wire next_rd_request_pending;
wire wr_request_pending_reg_scanin;
wire wr_request_pending_reg_scanout;
wire [39:3] next_asi_addr_bf;
wire address_reg_bf_scanin;
wire address_reg_bf_scanout;
wire [2:0] indet_tid_f;
wire [2:0] indet_tid_unused;
wire indet_rd_rdy_c;
wire indet_wr_rdy_c;
wire indet_comp_state_scanin;
wire indet_comp_state_scanout;
wire se;
wire spares_scanin;
wire spares_scanout;


// globals
input tcu_scan_en ;
input         l2clk ;
input  tcu_pce_ov;
input  spc_aclk;
input  spc_bclk;


input        scan_in;


input [64:0]  rng_in_cdbus; // 65 bit control/data bus to the  ring from lsu
input [32:0]  ic_rd_data  ;
input [29:0]  tg_rd_data  ;
input [63:0]  it_rd_data  ;
input [1:0]   agc_vl_data_c  ;


input         ftp_asi_ic_rd_done;    // indicates indeterminate ld data from ic is valid
input         ftp_asi_ic_wr_done;    // indicates indeterminate store to IC is done.
input         ftp_asi_tg_rd_done;    // indicates indeterminate ld data from tag is valid
input         ftp_asi_tg_wr_done;    // indicates indeterminate store to tag is done.
input         ftp_asi_it_rd_done;    // indicates indeterminate ld data from itlb is valid


output [32:0] asi_wr_data;       // Indeterminate store data to Cache or tag and Valid bits.  
output        asi_ic_rd_req;     // send indeterminate load  request to Icache data, sent in stage 1
output        asi_ic_wr_req;     // send indeterminate store request to Icache data, sent in stage 1
output        asi_tg_rd_req;     // send indeterminate load  request to Icache Tag, sent in stage 1
output        asi_tg_wr_req;     // send indeterminate store request to Icache Tag, sent in stage 1
output        asi_itd_rd_req;    // send indeterminate load  request to ITLB data , sent in stage 1
output        asi_itt_rd_req;    // send indeterminate load  request to ITLB tag  , sent in stage 1
output        asi_ith_det_req;   // send indeterminate load  request to ITLB to get translation  , sent in stage 1
output        asi_wr_request;    // indeterminate sent in stage 1
output        asi_rd_request;    // indeterminate sent in stage 1
output        scan_out ;
output [39:3] asi_addr_bf ;      // Read/write address
output [2:0]  asi_way_bf ;       // Read/write way
output [2:0]  asi_tid ;          // Thread id


output [64:0] ifu_rngl_cdbus; // 65 bit control/data bus output from the ring
                              // 64    - ctl/data
                              // 63    - valid/hole
                              // 62    - ack
                              // 61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR   
                              // 59    - rd/wrx
                              // 58:56 - Thread ID
                              // 55:48 - ASI field
                              // 47:0  - Virtual Address


assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;


assign asi_rd_data_rdy =  ftp_asi_ic_rd_done | ftp_asi_tg_rd_done | asi_it_rd_done_p;
assign asi_data_out[63:0] = ({64{ftp_asi_ic_rd_done}} &  {31'b0, ic_rd_data[32:0]}) |
                            ({64{ftp_asi_tg_rd_done}} &  {32'b0, tg_rd_data[29:0],agc_vl_data_c[1:0]}) |
                            ({64{asi_it_rd_done_p}} &  it_rd_data[63:0]) ; 

assign asi_wr_done_in = ftp_asi_ic_wr_done | ftp_asi_tg_wr_done;


////////////////////////////////////////////////////////
ifu_ftu_asi_ctl_l1clkhdr_ctl_macro clkgen 
  (
   .l2clk(l2clk),
   .l1en (1'b1 ),
   .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));
////////////////////////////////////////////////////////

ifu_ftu_asi_ctl_msff_ctl_macro__width_1 asi_it_rd_done_reg  (
	.scan_in(asi_it_rd_done_reg_scanin),
	.scan_out(asi_it_rd_done_reg_scanout),
	.l1clk	(l1clk),
	.din	(ftp_asi_it_rd_done),
	.dout	(asi_it_rd_done_p),
  .siclk(siclk),
  .soclk(soclk)
);


/////////////////////////////////////////////////////////////////////
//STAGE 1
/////////////////////////////////////////////////////////////////////
// Stage the packet coming on the ring
// First cycle of the packet holds control and address information
// Second cycle holds the store/load data

ifu_ftu_asi_ctl_msff_ctl_macro__width_64 rng_stg1_data  (
	.scan_in(rng_stg1_data_scanin),
	.scan_out(rng_stg1_data_scanout),
	.l1clk	(l1clk),
        .din( rng_in_cdbus[63:0]), 
        .dout( data_1f[63:0]),
  .siclk(siclk),
  .soclk(soclk));

assign ic_data_parity = ^data_1f[31:0] ;
assign ic_par_err_inj = ic_data_parity ^ data_1f[32] ;

assign tg_data_parity  = ^data_1f[30:2] ; 
assign tg_par_err_inj = tg_data_parity ^ data_2f[16] ;

assign vl_bits[1] = data_1f[1] ; 
assign vl_bits[0] = data_1f[1] ^ data_2f[15] ; 

assign asi_wr_data_mux[32:0] = asi_ic_wr_req_2f   ? {ic_par_err_inj,data_1f[31:0]} : {1'b0,vl_bits[1:0],tg_par_err_inj,data_1f[30:2]} ; 
assign asi_wr_data_in[32:0]  = asi_wr_request_2f  ? asi_wr_data_mux[32:0] : asi_wr_data_hold[32:0] ;

ifu_ftu_asi_ctl_msff_ctl_macro__width_33 wr_data_hold  (
	.scan_in(wr_data_hold_scanin),
	.scan_out(wr_data_hold_scanout),
	.l1clk	(l1clk),
        .din( asi_wr_data_in[32:0]), 
        .dout( asi_wr_data_hold[32:0]),
  .siclk(siclk),
  .soclk(soclk));

assign asi_wr_data[32:0] = asi_wr_data_hold[32:0] ;

// register control bit, bit 64 indicates whether ctl packet or data packet
ifu_ftu_asi_ctl_msff_ctl_macro__width_1 rng_stg1_ctl  (
	.scan_in(rng_stg1_ctl_scanin),
	.scan_out(rng_stg1_ctl_scanout),
	.l1clk	(l1clk),
	.din	(rng_in_cdbus[`BUS_CTL]),
	.dout	(ctl_1f),
  .siclk(siclk),
  .soclk(soclk)
);

// decode the packet, ack bit must not be set


assign asi_ic_rd_req  = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & 
                       (data_1f[61:60] == `ASI) &  data_1f[`BUS_RD] & (data_1f[55:48]==`IC_ASI) ; // & (data_1f[47:0] == `PR_VA);
assign asi_ic_wr_req_in  = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & 
                       (data_1f[61:60] == `ASI) & ~data_1f[`BUS_RD] & (data_1f[55:48]==`IC_ASI);//  & (data_1f[47:0] == `PR_VA);

assign asi_tg_rd_req  = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & 
                       (data_1f[61:60] == `ASI) &  data_1f[`BUS_RD] & (data_1f[55:48]==`TG_ASI) ; // & (data_1f[47:0] == `PR_VA);

assign asi_tg_wr_req_in  = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & 
                       (data_1f[61:60] == `ASI) & ~data_1f[`BUS_RD] & (data_1f[55:48]==`TG_ASI);//  & (data_1f[47:0] == `PR_VA);

ifu_ftu_asi_ctl_msff_ctl_macro__width_2 wr_req_ff  (
	.scan_in(wr_req_ff_scanin),
	.scan_out(wr_req_ff_scanout),
	.l1clk	(l1clk),
	.din	({asi_ic_wr_req_in, asi_tg_wr_req_in}),
	.dout	({asi_ic_wr_req, asi_tg_wr_req}),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_itd_rd_req  = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & 
                       (data_1f[61:60] == `ASI) &  data_1f[`BUS_RD] & (data_1f[55:48]==`ITD_ASI) ; // & (data_1f[47:0] == `IT_VA);

assign asi_itt_rd_req  = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & 
                       (data_1f[61:60] == `ASI) &  data_1f[`BUS_RD] & (data_1f[55:48]==`ITT_ASI) ;

assign asi_ith_det_req = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & 
                       (data_1f[61:60] == `ASI) & data_1f[`BUS_RD] & (data_1f[55:48]==`ITH_ASI);//  & (data_1f[47:0] == `PR_VA);


// assign pr_rd_1 = 1'b0 ;
// assign pr_wr_1 = 1'b0 ;

//detect a hole, this is used by indeterminate accesses.
assign hole_det_1 = ctl_1f & ~data_1f[`BUS_VLD];

// indeterminate accesses will clear the valid bit on the packet
// In this example stub, PR addresses are indeterminate. 
assign indet_acc_1 = asi_ic_rd_req | asi_ic_wr_req_in | asi_tg_rd_req | asi_tg_wr_req_in | asi_itd_rd_req | asi_itt_rd_req | asi_ith_det_req;

// decode determinate accesses


// Send load request and thread information from stage 1.
// In this example stub, data will be returned 2 cycles later,
// when ctl is in stage 3 and data is in stage 2.

/////////////////////////////////////////////////////////////////////
//STAGE 2
/////////////////////////////////////////////////////////////////////
// pipe the packets and decoded control information
ifu_ftu_asi_ctl_msff_ctl_macro__width_64 rng_stg2_data  (
	.scan_in(rng_stg2_data_scanin),
	.scan_out(rng_stg2_data_scanout),
	.l1clk	(l1clk),
        .din( data_1f[63:0]), 
        .dout( data_2f[63:0]),
  .siclk(siclk),
  .soclk(soclk));

// register control bit
ifu_ftu_asi_ctl_msff_ctl_macro__width_3 rng_stg2_ctl  (
	.scan_in(rng_stg2_ctl_scanin),
	.scan_out(rng_stg2_ctl_scanout),
	.l1clk	(l1clk),
	.din	({ctl_1f,asi_ic_wr_req_in, asi_wr_request}),
	.dout	({ctl_2f,asi_ic_wr_req_2f, asi_wr_request_2f}),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_asi_ctl_msff_ctl_macro__width_2 rng_stg2_decctl  (
	.scan_in(rng_stg2_decctl_scanin),
	.scan_out(rng_stg2_decctl_scanout),
	.l1clk	(l1clk),
	.din	({hole_det_1, indet_acc_1}),
	.dout	({hole_det_2f, indet_acc_2f}),
  .siclk(siclk),
  .soclk(soclk)
);

// send the store data out to the unit. Store data is in stage1 when control is in stage 2
// The data is accompanied by write control signal.


// also send the Thread ID with store data. It is in stage 2 (control packet).
// assign rng_wr_tid[2:0] = data_2f[`BUS_TID_END:`BUS_TID_ST];

assign next_indet_return_rd_first = (hole_det_2f & (indet_rd_rdy_f | indet_rd_rdy_f)) & ~indet_return_rd_first ; 
// If a hole is detected, and an indeterminate access is waiting to be sent, then insert it.
assign indet_rd_done_2 = hole_det_2f & indet_rd_rdy_f  & (~indet_wr_rdy_f |  indet_return_rd_first) ;
assign indet_wr_done_2 = hole_det_2f & indet_wr_rdy_f  & (~indet_rd_rdy_f | ~indet_return_rd_first);

// pipe the control bits 1 more cycle to line it up with data
ifu_ftu_asi_ctl_msff_ctl_macro__width_2 rng_stg3_decctl  (
	.scan_in(rng_stg3_decctl_scanin),
	.scan_out(rng_stg3_decctl_scanout),
	.l1clk	(l1clk),
	.din	({indet_rd_done_2,next_indet_return_rd_first}),
	.dout	({indet_rd_done_3f,indet_return_rd_first}),
  .siclk(siclk),
  .soclk(soclk)
);

// bypass incoming data if the packet is not a read request to the unit.
assign bypass_data_3 = ~indet_rd_done_3f;

// Mux the output data
// mux_macro mux_data_stg2 (width=64,ports=2,mux=aonpe) 
// (
//  .din0(data_2f[63:0]),
//  .din1(indet_data_f[63:0]),
//  .sel0(bypass_data_3),
//  .sel1(indet_rd_done_3f),
//  .dout(data_2[63:0]));

assign data_2[63:0] = bypass_data_3 ? data_2f[63:0] : indet_data_f[63:0] ;

// valid bit is cleared if current packet is indeterminate rd/wr
// valid bit is set if indeterminate data is being returned on current packet, indicated by indet_done
// indet_done and indet_acc are mutually exclusive by design.
assign valid_2 = (indet_wr_done_2 | indet_rd_done_2 | data_2f[`BUS_VLD]) & !indet_acc_2f;
// assign tid_2[2:0] = (indet_wr_done_2 | indet_rd_done_2)? indet_tid_f[2:0]: data_2f[`BUS_TID_END:`BUS_TID_ST];

assign tid_2[2:0] = (({3{( indet_wr_done_2 & ~indet_rd_done_2)}}) & indet_wr_tid_f[2:0]) |  
                    (({3{(~indet_wr_done_2 & indet_rd_done_2)}})  & indet_rd_tid_f[2:0]) |
                    (({3{(~indet_wr_done_2 & ~indet_rd_done_2)}}) & data_2f[`BUS_TID_END:`BUS_TID_ST]);

assign rdwr_2 = (indet_rd_done_2 & !indet_wr_done_2) | (!indet_rd_done_2 & !indet_wr_done_2 & data_2f[`BUS_RD]);

// ack bit is set if current packet was a determinate rd/wr destined for the unit.
// ack bit is also set if indeterminate data is being returned on current packet.
// ack bit is cleared if current packet is indeterminate rd/wr destined for the unit
// Else, ack bit is passed unchanged

assign ack_2 = (indet_wr_done_2 | indet_rd_done_2 |  data_2f[`BUS_ACK]) & !indet_acc_2f;

// report exceptions
assign asi_err_2[7:0] = (ack_2 & ~data_2f[`BUS_ACK]) ? 8'b0 : data_2f[55:48];

assign ctl_2[63:0] = {valid_2, ack_2, data_2f[61:60], rdwr_2, tid_2[2:0], asi_err_2[7:0],  data_2f[47:0]};

/////////////////////////////////////////////////////////////////////
//STAGE 3
/////////////////////////////////////////////////////////////////////
// This is the output register
// Mux ctl and data
// 

assign rng_data_out_mux[63:0] = ctl_2f ? ctl_2[63:0] : data_2[63:0] ; 

ifu_ftu_asi_ctl_msff_ctl_macro__width_64 rng_stg3  (
	.scan_in(rng_stg3_scanin),
	.scan_out(rng_stg3_scanout),
	.l1clk	(l1clk),
	.din	(rng_data_out_mux[63:0]),
	.dout	(ifu_rngl_cdbus[63:0]),
  .siclk(siclk),
  .soclk(soclk)
);


ifu_ftu_asi_ctl_msff_ctl_macro__width_1 rng_stg3_ctl  (
	.scan_in(rng_stg3_ctl_scanin),
	.scan_out(rng_stg3_ctl_scanout),
	.l1clk	(l1clk),
	.din	(ctl_2f),
	.dout	(ifu_rngl_cdbus[`BUS_CTL]),
  .siclk(siclk),
  .soclk(soclk)
);


// latch the indeterminate load data and set up state to hold it until
// a hole is detected and data is returned. Same applies to indeterminate
// store, except there is no data to return. Only a valid packet is returned
// with the right tid and rd/wr bit.


ifu_ftu_asi_ctl_msff_ctl_macro__en_1__width_64 indet_rd_data  (
 .scan_in(indet_rd_data_scanin),
 .scan_out(indet_rd_data_scanout),
 .l1clk	(l1clk),
 .en  ( asi_rd_data_rdy),
 .din( asi_data_out[63:0]), 
 .dout( indet_data_f[63:0]),
  .siclk(siclk),
  .soclk(soclk));

assign next_indet_wr_tid[2:0] = asi_wr_request ? data_1f[`BUS_TID_END:`BUS_TID_ST] : indet_wr_tid_f; 

ifu_ftu_asi_ctl_msff_ctl_macro__width_3 pr_tid_wr_ret  (
	.scan_in(pr_tid_wr_ret_scanin),
	.scan_out(pr_tid_wr_ret_scanout),
	.l1clk	(l1clk),
	.din	(next_indet_wr_tid[2:0]),
	.dout	(indet_wr_tid_f[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign next_indet_rd_tid[2:0] = asi_rd_request ? data_1f[`BUS_TID_END:`BUS_TID_ST] : indet_rd_tid_f; 

ifu_ftu_asi_ctl_msff_ctl_macro__width_3 pr_tid_rd_ret  (
	.scan_in(pr_tid_rd_ret_scanin),
	.scan_out(pr_tid_rd_ret_scanout),
	.l1clk	(l1clk),
	.din	(next_indet_rd_tid[2:0]),
	.dout	(indet_rd_tid_f[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign next_rd_addr_bf[39:3] = asi_rd_request ? data_1f[39:3] : asi_rd_addr_bf[39:3]; 
ifu_ftu_asi_ctl_msff_ctl_macro__width_37 address_rd_reg  (
	.scan_in(address_rd_reg_scanin),
	.scan_out(address_rd_reg_scanout),
	.l1clk	(l1clk),
	.din	(next_rd_addr_bf[39:3]),
	.dout	(asi_rd_addr_bf[39:3]),
  .siclk(siclk),
  .soclk(soclk)
);

assign next_wr_addr_bf[39:3] = asi_wr_request ? data_1f[39:3] : asi_wr_addr_bf[39:3]; 
ifu_ftu_asi_ctl_msff_ctl_macro__width_37 address_wr_reg  (
	.scan_in(address_wr_reg_scanin),
	.scan_out(address_wr_reg_scanout),
	.l1clk	(l1clk),
	.din	(next_wr_addr_bf[39:3]),
	.dout	(asi_wr_addr_bf[39:3]),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_rd_way_bf[2:0] = asi_rd_request ? data_1f[14:12] : asi_rd_way_bf[2:0]; 
ifu_ftu_asi_ctl_msff_ctl_macro__width_3 rd_way_bf_reg  (
	.scan_in(rd_way_bf_reg_scanin),
	.scan_out(rd_way_bf_reg_scanout),
	.l1clk	(l1clk),
	.din	(next_rd_way_bf[2:0]),
	.dout	(asi_rd_way_bf[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign next_wr_way_bf[2:0] = asi_wr_request ? data_1f[14:12] : asi_wr_way_bf[2:0]; 
ifu_ftu_asi_ctl_msff_ctl_macro__width_3 wr_way_bf_reg  (
	.scan_in(wr_way_bf_reg_scanin),
	.scan_out(wr_way_bf_reg_scanout),
	.l1clk	(l1clk),
	.din	(next_wr_way_bf[2:0]),
	.dout	(asi_wr_way_bf[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign next_rd_is_first = (asi_rd_request     & ~true_old_wr_req_pending)  | 
                          (rd_request_pending & ~true_old_wr_req_pending & ~asi_rd_data_rdy)  | 
                          (asi_rd_is_first    & ~asi_rd_data_rdy);

ifu_ftu_asi_ctl_msff_ctl_macro__width_1 rd_is_first_reg  (
	.scan_in(rd_is_first_reg_scanin),
	.scan_out(rd_is_first_reg_scanout),
	.l1clk	(l1clk),
	.din	(next_rd_is_first),
	.dout	(asi_rd_is_first),
  .siclk(siclk),
  .soclk(soclk)
);


assign true_old_wr_req_pending = (wr_request_pending	   & ~asi_wr_done_in) ;
assign next_wr_request_pending = asi_wr_request   | (wr_request_pending    & ~asi_wr_done_in);
assign next_rd_request_pending = asi_rd_request   | (rd_request_pending    & ~asi_rd_data_rdy);

ifu_ftu_asi_ctl_msff_ctl_macro__width_2 wr_request_pending_reg  (
	.scan_in(wr_request_pending_reg_scanin),
	.scan_out(wr_request_pending_reg_scanout),
	.l1clk	(l1clk),
	.din	({next_wr_request_pending, next_rd_request_pending}),
	.dout	({wr_request_pending,rd_request_pending}),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_asi_addr_bf[39:3]  = next_rd_is_first ? next_rd_addr_bf[39:3] : next_wr_addr_bf[39:3] ;

ifu_ftu_asi_ctl_msff_ctl_macro__width_37 address_reg_bf  (
	.scan_in(address_reg_bf_scanin),
	.scan_out(address_reg_bf_scanout),
	.l1clk	(l1clk),
	.din	(next_asi_addr_bf[39:3]),
	.dout	(asi_addr_bf[39:3]),
  .siclk(siclk),
  .soclk(soclk)
);


assign asi_way_bf[2:0]    = asi_rd_is_first ? asi_rd_way_bf[2:0]   : asi_wr_way_bf[2:0]   ;
assign indet_tid_f[2:0]   = asi_rd_is_first ? indet_rd_tid_f[2:0]  : indet_wr_tid_f[2:0]   ; 
assign indet_tid_unused[2:0]    = indet_tid_f[2:0] ;

// assign next_tid_bf[2:0] = asi_request ? data_1f[14:12] : asi_tid[2:0]; 
// msff_ctl_macro tid_bf_reg (width=3) (
// 	.scan_in(tid_bf_reg_scanin),
// 	.scan_out(tid_bf_reg_scanout),
// 	.l1clk	(l1clk),
// 	.din	(next_tid_bf[2:0]),
// 	.dout	(asi_tid[2:0])
// );

assign asi_tid[2:0] = data_1f[58:56] ;

// set up state to inidicate completed indeterminate operation
assign indet_rd_rdy_c = (asi_rd_data_rdy | indet_rd_rdy_f) & !indet_rd_done_2;
assign indet_wr_rdy_c = (asi_wr_done_in  | indet_wr_rdy_f) & !indet_wr_done_2;

ifu_ftu_asi_ctl_msff_ctl_macro__width_2 indet_comp_state  (
	.scan_in(indet_comp_state_scanin),
	.scan_out(indet_comp_state_scanout),
	.l1clk	(l1clk),
	.din	({indet_rd_rdy_c, indet_wr_rdy_c}),
	.dout	({indet_rd_rdy_f, indet_wr_rdy_f}),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_wr_request = asi_ic_wr_req_in | asi_tg_wr_req_in ;
assign asi_rd_request = asi_ic_rd_req | asi_tg_rd_req |  asi_itd_rd_req | asi_itt_rd_req | asi_ith_det_req;

assign se = tcu_scan_en ;
///////////////////////////////////////////////////////////////////////
// Spare circuits                                                    //
///////////////////////////////////////////////////////////////////////
ifu_ftu_asi_ctl_spare_ctl_macro__num_4 spares  (
        .scan_in(spares_scanin),
        .scan_out(spares_scanout),
        .l1clk  (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// fixscan start:
assign asi_it_rd_done_reg_scanin = scan_in                  ;
assign rng_stg1_data_scanin      = asi_it_rd_done_reg_scanout;
assign wr_data_hold_scanin       = rng_stg1_data_scanout    ;
assign rng_stg1_ctl_scanin       = wr_data_hold_scanout     ;
assign wr_req_ff_scanin          = rng_stg1_ctl_scanout     ;
assign rng_stg2_data_scanin      = wr_req_ff_scanout        ;
assign rng_stg2_ctl_scanin       = rng_stg2_data_scanout    ;
assign rng_stg2_decctl_scanin    = rng_stg2_ctl_scanout     ;
assign rng_stg3_decctl_scanin    = rng_stg2_decctl_scanout  ;
assign rng_stg3_scanin           = rng_stg3_decctl_scanout  ;
assign rng_stg3_ctl_scanin       = rng_stg3_scanout         ;
assign indet_rd_data_scanin      = rng_stg3_ctl_scanout     ;
assign pr_tid_wr_ret_scanin      = indet_rd_data_scanout    ;
assign pr_tid_rd_ret_scanin      = pr_tid_wr_ret_scanout    ;
assign address_rd_reg_scanin     = pr_tid_rd_ret_scanout    ;
assign address_wr_reg_scanin     = address_rd_reg_scanout   ;
assign rd_way_bf_reg_scanin      = address_wr_reg_scanout   ;
assign wr_way_bf_reg_scanin      = rd_way_bf_reg_scanout    ;
assign rd_is_first_reg_scanin    = wr_way_bf_reg_scanout    ;
assign wr_request_pending_reg_scanin = rd_is_first_reg_scanout  ;
assign address_reg_bf_scanin     = wr_request_pending_reg_scanout;
assign indet_comp_state_scanin   = address_reg_bf_scanout   ;
assign spares_scanin             = indet_comp_state_scanout ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_asi_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_asi_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_asi_ctl_msff_ctl_macro__width_64 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [63:0] fdin;
wire [62:0] so;

  input [63:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [63:0] dout;
  output scan_out;
assign fdin[63:0] = din[63:0];


dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_asi_ctl_msff_ctl_macro__width_33 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [32:0] fdin;
wire [31:0] so;

  input [32:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [32:0] dout;
  output scan_out;
assign fdin[32:0] = din[32:0];


dff #(33)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[32:0]),
.si({scan_in,so[31:0]}),
.so({so[31:0],scan_out}),
.q(dout[32:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_asi_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_asi_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_asi_ctl_msff_ctl_macro__en_1__width_64 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [63:0] fdin;
wire [62:0] so;

  input [63:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [63:0] dout;
  output scan_out;
assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}});


dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_asi_ctl_msff_ctl_macro__width_37 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [36:0] fdin;
wire [35:0] so;

  input [36:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [36:0] dout;
  output scan_out;
assign fdin[36:0] = din[36:0];


dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ftu_asi_ctl_spare_ctl_macro__num_4 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));
assign scan_out = so_3;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_byp_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_byp_dp (
  tcu_scan_en, 
  tcu_se_scancollar_out, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_muxtest, 
  tcu_dectest, 
  mbi_cambist_run, 
  mbi_addr, 
  agd_mbist_wdata_bf, 
  ftp_mbi_icd_read_en_bf, 
  ftp_mbi_ict_read_en_bf, 
  itc_mbi_itb_read_en, 
  cmu_fill_inst0, 
  cmu_fill_inst1, 
  cmu_fill_inst2, 
  cmu_fill_inst3, 
  icd_bus_0_instr_c, 
  icd_bus_1_instr_c, 
  icd_bus_2_instr_c, 
  icd_bus_3_instr_c, 
  agc_instr_bp_sel_c, 
  agc_asi_sel_word_c, 
  agc_sel_tg_data_f, 
  ict_itlb_way_0_tag_f, 
  ict_itlb_way_1_tag_f, 
  ict_itlb_way_2_tag_f, 
  ict_itlb_way_3_tag_f, 
  ict_itlb_way_4_tag_f, 
  ict_itlb_way_5_tag_f, 
  ict_itlb_way_6_tag_f, 
  ict_itlb_way_7_tag_f, 
  itb_tte_data, 
  itb_tte_tag, 
  itb_tte_u_bit, 
  ftu_paddr, 
  itb_cam_hit_c, 
  itb_itb_mhit_c, 
  itb_tte_data_parity, 
  agc_itb_tag_perr_c, 
  itc_itb_data_sz_1, 
  ftp_sel_mbist_itb_cycle0, 
  ftp_sel_mbist_itb_cycle1, 
  ftp_sel_mbist_itb_cycle2, 
  ftp_sel_mbist_itb_cycle3, 
  ftp_sel_itlb_tag_cntx0_c, 
  ftp_sel_itlb_tag_cntx1_c, 
  ftp_sel_itlb_data_c, 
  ftp_sel_itlb_pa_c, 
  ftu_instr_0_c, 
  ftu_instr_1_c, 
  ftu_instr_2_c, 
  ftu_instr_3_c, 
  ic_rd_data, 
  ic_dmo_rd_data, 
  tg_rd_data, 
  it_rd_data, 
  ftu_mbi_ict_fail, 
  ftu_mbi_icd_fail, 
  ftu_mbi_itb_fail, 
  ftu_mbi_tlb_data_cmp, 
  ftu_mbi_tlb_used, 
  ftu_mbi_tlb_valid, 
  ict_itlb_way_0_tag_f_rep0, 
  ict_itlb_way_1_tag_f_rep0, 
  ict_itlb_way_2_tag_f_rep0, 
  ict_itlb_way_3_tag_f_rep0, 
  ict_itlb_way_4_tag_f_rep0, 
  ict_itlb_way_5_tag_f_rep0, 
  ict_itlb_way_6_tag_f_rep0, 
  ict_itlb_way_7_tag_f_rep0, 
  scan_out) ;
wire stop;
wire test;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire by_pass_i0i1_f_reg_scanin;
wire by_pass_i0i1_f_reg_scanout;
wire [32:0] by_pass_instr_1_f;
wire [32:0] by_pass_instr_0_f;
wire by_pass_i2i3_f_reg_scanin;
wire by_pass_i2i3_f_reg_scanout;
wire [32:0] by_pass_instr_3_f;
wire [32:0] by_pass_instr_2_f;
wire by_pass_i0i1_c_reg_scanin;
wire by_pass_i0i1_c_reg_scanout;
wire [32:0] by_pass_instr_1_c;
wire [32:0] by_pass_instr_0_c;
wire by_pass_i2i3_c_reg_scanin;
wire by_pass_i2i3_c_reg_scanout;
wire [32:0] by_pass_instr_3_c;
wire [32:0] by_pass_instr_2_c;
wire tcu_muxtest_rep0;
wire tcu_muxtest_rep1;
wire [32:0] icd_bus_2_instr_reordered_c;
wire [32:0] icd_bus_3_instr_reordered_c;
wire asi_word_muxx_scanin;
wire asi_word_muxx_scanout;
wire asi_tag_mux_scanin;
wire asi_tag_mux_scanout;
wire asi_itlb_mux_scanin;
wire asi_itlb_mux_scanout;
wire itlb_bist_mux_scanin;
wire itlb_bist_mux_scanout;
wire [7:0] mbist_wdata_3_ff;
wire [31:0] itt_itd_cmp_data;
wire [65:0] tag_mbist_wdata;
wire [37:0] data_mbist_wdata;
wire itlb_w_bist_data_mux_scanin;
wire itlb_w_bist_data_mux_scanout;
wire [31:0] mbist_cmp_data_4_ff;
wire bist_data_stage_a_scanin;
wire bist_data_stage_a_scanout;
wire [7:0] mbist_wdata_2_ff;
wire cambist_run_ff;
wire [5:0] mbist_addr_1;
wire bist_data_stage_b_scanin;
wire bist_data_stage_b_scanout;
wire [7:0] mbist_wdata_4_ff;
wire bist_data_stage_dup_b_scanin;
wire bist_data_stage_dup_b_scanout;
wire [7:0] mbist_wdata_4_dup_ff;
wire [5:0] mbist_addr_2;
wire bist_data_stage_c_scanin;
wire bist_data_stage_c_scanout;
wire mbist_itb_read_en_2_ff;
wire mbist_itb_read_en_3_ff;
wire it_mbist_fail_q;
wire mbist_icd_read_en_2_ff;
wire mbist_icd_read_en_3_ff;
wire ict_mbist_fail_q;
wire icd_mbist_fail_q;
wire mbist_ict_read_en_2_ff;
wire [5:0] mbist_addr_3;
wire mbist_itb_read_en_4_ff;
wire mbist_icd_read_en_4_ff;
wire mbist_ict_read_en_3_ff;
wire [5:0] mbist_addr_4;
wire ict_mbist_fail_unq_l;
wire icd_mbist_fail_31_0_l;
wire icd_mbist_fail_32;
wire mbist_it_fail_unq_l;
wire ict_mbist_fail_unq;
wire icd_mbist_fail_31_0;
wire mbist_it_fail_unq;
wire cambist_run_ff_l;
wire sel_mbist_itb_cycle1_l;
wire icd_mbist_fail_unq;
wire mbist_it_read_en;
wire rbit_modify_unused;
wire sel_mbist_itb_cycle1_l_ff;
wire itb_data_for_cam_scanin;
wire itb_data_for_cam_scanout;
wire [5:0] itb_tte_data_1;

        
input tcu_scan_en ;
input tcu_se_scancollar_out ;
input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;
input tcu_muxtest;
input tcu_dectest;

input       mbi_cambist_run;
input [5:0] mbi_addr;

input [7:0] agd_mbist_wdata_bf;
input       ftp_mbi_icd_read_en_bf;
input       ftp_mbi_ict_read_en_bf;
input       itc_mbi_itb_read_en;
input [32:0] cmu_fill_inst0;
input [32:0] cmu_fill_inst1;
input [32:0] cmu_fill_inst2;
input [32:0] cmu_fill_inst3;
input [32:0] icd_bus_0_instr_c    ;
input [32:0] icd_bus_1_instr_c    ;
input [32:0] icd_bus_2_instr_c    ;
input [32:0] icd_bus_3_instr_c    ;
input [2:0]  agc_instr_bp_sel_c ;
input [3:0]  agc_asi_sel_word_c ;
input [7:0]  agc_sel_tg_data_f;
input [29:0] ict_itlb_way_0_tag_f;
input [29:0] ict_itlb_way_1_tag_f;
input [29:0] ict_itlb_way_2_tag_f;
input [29:0] ict_itlb_way_3_tag_f;
input [29:0] ict_itlb_way_4_tag_f;
input [29:0] ict_itlb_way_5_tag_f;
input [29:0] ict_itlb_way_6_tag_f;
input [29:0] ict_itlb_way_7_tag_f;
input [37:0] itb_tte_data;
input [65:0] itb_tte_tag;
input        itb_tte_u_bit;
input [39:13] ftu_paddr;
input        itb_cam_hit_c;
input        itb_itb_mhit_c;
input        itb_tte_data_parity;
input        agc_itb_tag_perr_c; 
input        itc_itb_data_sz_1;

input       ftp_sel_mbist_itb_cycle0;
input       ftp_sel_mbist_itb_cycle1;
input       ftp_sel_mbist_itb_cycle2;
input       ftp_sel_mbist_itb_cycle3;

input        ftp_sel_itlb_tag_cntx0_c;
input        ftp_sel_itlb_tag_cntx1_c;
input        ftp_sel_itlb_data_c;
input        ftp_sel_itlb_pa_c;


output [32:0] ftu_instr_0_c ;
output [32:0] ftu_instr_1_c ;
output [32:0] ftu_instr_2_c ;
output [32:0] ftu_instr_3_c ;
output [32:0] ic_rd_data    ;
output [32:0] ic_dmo_rd_data;
output [29:0] tg_rd_data    ;
output [63:0] it_rd_data    ;

output 	      ftu_mbi_ict_fail;
output        ftu_mbi_icd_fail ;
output        ftu_mbi_itb_fail ;
output        ftu_mbi_tlb_data_cmp ;
output        ftu_mbi_tlb_used; 
output        ftu_mbi_tlb_valid;

output [28:0] ict_itlb_way_0_tag_f_rep0;
output [28:0] ict_itlb_way_1_tag_f_rep0;
output [28:0] ict_itlb_way_2_tag_f_rep0;
output [28:0] ict_itlb_way_3_tag_f_rep0;
output [28:0] ict_itlb_way_4_tag_f_rep0;
output [28:0] ict_itlb_way_5_tag_f_rep0;
output [28:0] ict_itlb_way_6_tag_f_rep0;
output [28:0] ict_itlb_way_7_tag_f_rep0;

output 	      scan_out;

// TLB TTE defines
`define TAG_CNTX1_HI    65
`define TAG_CNTX1_LO    53
`define TAG_PID_HI      52
`define TAG_PID_LO      50
`define TAG_REAL        49
`define TAG_VA_47_28_HI 48
`define TAG_VA_47_28_LO 29
`define TAG_VA_27_22_HI 28
`define TAG_VA_27_22_LO 23
`define TAG_V           22
`define TAG_VA_21_16_HI 21
`define TAG_VA_21_16_LO 16
`define TAG_VA_15_13_HI 15
`define TAG_VA_15_13_LO 13
`define TAG_CNTX0_HI    12
`define TAG_CNTX0_LO     0

`define TAG_PARITY          37
`define DATA_PARITY         36
`define DATA_PA_39_28_HI    35
`define DATA_PA_39_28_LO    24
`define DATA_PA_27_22_HI    23
`define DATA_PA_27_22_LO    18
`define DATA_VA_27_22_V     17
`define DATA_PA_21_16_HI    16
`define DATA_PA_21_16_LO    11
`define DATA_VA_21_16_V     10
`define DATA_PA_15_13_HI     9
`define DATA_PA_15_13_LO     7
`define DATA_VA_15_13_V      6
`define DATA_NFO             5
`define DATA_IE              4
`define DATA_CP              3
`define DATA_E               2
`define DATA_P               1
`define DATA_W               0

// scan renames
// assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
// assign siclk = spc_aclk;
// assign soclk = spc_bclk;
assign test   = tcu_dectest ;
// end scan

ifu_ftu_byp_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0  (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);

///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////
// Flop the by_pass instructions from CMU
///////////////////////////////////////////////////////////////////////
ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 by_pass_i0i1_f_reg  (
 .scan_in(by_pass_i0i1_f_reg_scanin),
 .scan_out(by_pass_i0i1_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( {cmu_fill_inst1[32:0],    cmu_fill_inst0[32:0]}),
 .dout( {by_pass_instr_1_f[32:0], by_pass_instr_0_f[32:0]}     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

//msff_macro by_pass_i1_f_reg (width=33,stack=34c) (
// .scan_in(by_pass_i1_f_reg_scanin),
// .scan_out(by_pass_i1_f_reg_scanout),
// .clk ( l2clk                ),
// .en  ( 1'b1                 ),  
// .din ( cmu_fill_inst1[32:0]),
// .dout( by_pass_instr_1_f[32:0]     ));

ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 by_pass_i2i3_f_reg  (
 .scan_in(by_pass_i2i3_f_reg_scanin),
 .scan_out(by_pass_i2i3_f_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( {cmu_fill_inst3[32:0],   cmu_fill_inst2[32:0]}),
 .dout( {by_pass_instr_3_f[32:0], by_pass_instr_2_f[32:0]}     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

//msff_macro by_pass_i3_f_reg (width=33,stack=34c) (
// .scan_in(by_pass_i3_f_reg_scanin),
// .scan_out(by_pass_i3_f_reg_scanout),
// .clk ( l2clk                ),
// .en  ( 1'b1                 ),  
// .din ( cmu_fill_inst3[32:0]),
// .dout( by_pass_instr_3_f[32:0]     ));

///////////////////////////////////////////////////////////////////////
// The following flops and muxes can be folded into the IC array.    //
///////////////////////////////////////////////////////////////////////

 ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 by_pass_i0i1_c_reg  (
  .scan_in(by_pass_i0i1_c_reg_scanin),
  .scan_out(by_pass_i0i1_c_reg_scanout),
  .clk ( l2clk                ),
  .en  ( 1'b1                 ),  
  .din ( {by_pass_instr_1_f[32:0],by_pass_instr_0_f[32:0]}),
  .dout( {by_pass_instr_1_c[32:0],by_pass_instr_0_c[32:0]}     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// msff_macro by_pass_i1_c_reg (width=33,stack=34c) (
// .scan_in(by_pass_i1_c_reg_scanin),
// .scan_out(by_pass_i1_c_reg_scanout),
// .clk ( l2clk                ),
// .en  ( 1'b1                 ),  
// .din ( by_pass_instr_1_f[32:0]),
// .dout( by_pass_instr_1_c[32:0]     ));

 ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 by_pass_i2i3_c_reg  (
 .scan_in(by_pass_i2i3_c_reg_scanin),
 .scan_out(by_pass_i2i3_c_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( {by_pass_instr_3_f[32:0],by_pass_instr_2_f[32:0]}),
 .dout( {by_pass_instr_3_c[32:0],by_pass_instr_2_c[32:0]}     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// msff_macro by_pass_i3_c_reg (width=33,stack=34c) (
// .scan_in(by_pass_i3_c_reg_scanin),
// .scan_out(by_pass_i3_c_reg_scanout),
// .clk ( l2clk                ),
//.en  ( 1'b1                 ),  
// .din ( by_pass_instr_3_f[32:0]),
// .dout( by_pass_instr_3_c[32:0]     ));

ifu_ftu_byp_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep0  (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep0     ));


ifu_ftu_byp_dp_mux_macro__mux_pgpe__ports_4__stack_66c__width_66 inst_01_bp_mux  (
 .din0( {icd_bus_1_instr_c[32:0],icd_bus_0_instr_c[32:0]}), 
 .din1( {by_pass_instr_1_f[32:0],by_pass_instr_0_f[32:0]}),              
 .din2( {by_pass_instr_1_c[32:0],by_pass_instr_0_c[32:0]}),              
 .din3( {cmu_fill_inst1[32:0],cmu_fill_inst0[32:0]}),              
 .muxtst(tcu_muxtest_rep0),
 .sel0( agc_instr_bp_sel_c[0]),
 .sel1( agc_instr_bp_sel_c[1]),
 .sel2( agc_instr_bp_sel_c[2]),
 .dout( {ftu_instr_1_c[32:0],ftu_instr_0_c[32:0]} ),
  .test(test));

//mux_macro inst_1_bp_mux (width=33,ports=5,mux=aonpe,stack=34c) (
// .din0( icd_bus_1_instr_c[32:0]), 
// .din1( 33'h001000000),              
// .din2( cmu_fill_inst1[32:0]),              
// .din3( by_pass_instr_1_f[32:0]),              
// .din4( by_pass_instr_1_c[32:0]),              
// .sel0( agc_instr_bp_sel_c[0]),
// .sel1( agc_instr_bp_sel_c[1]),
// .sel2( agc_instr_bp_sel_c[2]),
// .sel3( agc_instr_bp_sel_c[3]),
// .sel4( agc_instr_bp_sel_c[4]),
// .dout( ftu_instr_1_c[32:0] ));

ifu_ftu_byp_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep1  (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep1     ));

ifu_ftu_byp_dp_mux_macro__dmux_8x__mux_pgpe__ports_4__stack_66c__width_66 inst_23_bp_mux  (
 .din0( {icd_bus_3_instr_c[32:0],icd_bus_2_instr_c[32:0]}), 
 .din1( {by_pass_instr_3_f[32:0],by_pass_instr_2_f[32:0]}),              
 .din2( {by_pass_instr_3_c[32:0],by_pass_instr_2_c[32:0]}),              
 .din3( {cmu_fill_inst3[32:0],cmu_fill_inst2[32:0]}),              
 .muxtst(tcu_muxtest_rep1),
 .sel0( agc_instr_bp_sel_c[0]),
 .sel1( agc_instr_bp_sel_c[1]),
 .sel2( agc_instr_bp_sel_c[2]),
 .dout( {ftu_instr_3_c[32:0],ftu_instr_2_c[32:0]} ),
  .test(test));


// buff_macro icd_bus_01_instr_rep0 (width=66,stack=66c,dbuff=48x) (
//   .din ({icd_bus_1_instr_c[32:0],icd_bus_0_instr_c[32:0]}     ),
//   .dout({icd_bus_1_instr_c_rep0[32:0], icd_bus_0_instr_c_rep0[32:0]})
//   );


// buff_macro icd_bus_23_instr_rep0 (width=66,stack=66c,dbuff=48x) (
//   .din ({icd_bus_3_instr_c[32:0], icd_bus_2_instr_c[32:0] }    ),
//   .dout({icd_bus_3_instr_c_rep0[32:0], icd_bus_2_instr_c_rep0[32:0]})
//   );


//mux_macro inst_3_bp_mux (width=33,ports=5,mux=aonpe,stack=34c) (
// .din0( icd_bus_3_instr_c[32:0]), 
// .din1( 33'h001000000),              
// .din2( cmu_fill_inst3[32:0]),              
// .din3( by_pass_instr_3_f[32:0]),              
// .din4( by_pass_instr_3_c[32:0]),              
// .sel0( agc_instr_bp_sel_c[0]),
// .sel1( agc_instr_bp_sel_c[1]),
// .sel2( agc_instr_bp_sel_c[2]),
// .sel3( agc_instr_bp_sel_c[3]),
// .sel4( agc_instr_bp_sel_c[4]),
// .dout( ftu_instr_3_c[32:0] ));

assign icd_bus_2_instr_reordered_c[32:0] = {icd_bus_2_instr_c[0],  icd_bus_2_instr_c[1] ,icd_bus_2_instr_c[2] ,icd_bus_2_instr_c[3],
                                            icd_bus_2_instr_c[4],  icd_bus_2_instr_c[5] ,icd_bus_2_instr_c[6] ,icd_bus_2_instr_c[7],
                                            icd_bus_2_instr_c[8],  icd_bus_2_instr_c[9] ,icd_bus_2_instr_c[10],icd_bus_2_instr_c[11],
                                            icd_bus_2_instr_c[12], icd_bus_2_instr_c[13],icd_bus_2_instr_c[14],icd_bus_2_instr_c[15],
                                            icd_bus_2_instr_c[16], icd_bus_2_instr_c[17],icd_bus_2_instr_c[18],icd_bus_2_instr_c[19],
                                            icd_bus_2_instr_c[20], icd_bus_2_instr_c[21],icd_bus_2_instr_c[22],icd_bus_2_instr_c[23],
                                            icd_bus_2_instr_c[24], icd_bus_2_instr_c[25],icd_bus_2_instr_c[26],icd_bus_2_instr_c[27],
                                            icd_bus_2_instr_c[28], icd_bus_2_instr_c[29],icd_bus_2_instr_c[30],icd_bus_2_instr_c[31],
                                            icd_bus_2_instr_c[32]};

assign icd_bus_3_instr_reordered_c[32:0] = {icd_bus_3_instr_c[0],  icd_bus_3_instr_c[1] ,icd_bus_3_instr_c[2] ,icd_bus_3_instr_c[3],
                                            icd_bus_3_instr_c[4],  icd_bus_3_instr_c[5] ,icd_bus_3_instr_c[6] ,icd_bus_3_instr_c[7],
                                            icd_bus_3_instr_c[8],  icd_bus_3_instr_c[9] ,icd_bus_3_instr_c[10],icd_bus_3_instr_c[11],
                                            icd_bus_3_instr_c[12], icd_bus_3_instr_c[13],icd_bus_3_instr_c[14],icd_bus_3_instr_c[15],
                                            icd_bus_3_instr_c[16], icd_bus_3_instr_c[17],icd_bus_3_instr_c[18],icd_bus_3_instr_c[19],
                                            icd_bus_3_instr_c[20], icd_bus_3_instr_c[21],icd_bus_3_instr_c[22],icd_bus_3_instr_c[23],
                                            icd_bus_3_instr_c[24], icd_bus_3_instr_c[25],icd_bus_3_instr_c[26],icd_bus_3_instr_c[27],
                                            icd_bus_3_instr_c[28], icd_bus_3_instr_c[29],icd_bus_3_instr_c[30],icd_bus_3_instr_c[31],
                                            icd_bus_3_instr_c[32]};

ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_4__stack_34c__width_33 asi_word_muxx  (
 .scan_in(asi_word_muxx_scanin),
 .scan_out(asi_word_muxx_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .se  ( tcu_se_scancollar_out ) ,
 .din0( icd_bus_0_instr_c[32:0]), 
 .din1( icd_bus_1_instr_c[32:0]), 
 .din2( icd_bus_2_instr_reordered_c[32:0]), 
 .din3( icd_bus_3_instr_reordered_c[32:0]), 
 .sel0( agc_asi_sel_word_c[0]),
 .sel1( agc_asi_sel_word_c[1]),
 .sel2( agc_asi_sel_word_c[2]),
 .sel3( agc_asi_sel_word_c[3]),
 .dout( ic_rd_data[32:0] ),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_byp_dp_buff_macro__dbuff_16x__rep_1__stack_34c__width_33 ic_dmo_rd_data_buf  (
     .din (ic_rd_data[32:0]     ),
     .dout(ic_dmo_rd_data[32:0])
   );


ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_0_tag_buff_rep0  (
     .din (ict_itlb_way_0_tag_f[28:0]     ),
     .dout(ict_itlb_way_0_tag_f_rep0[28:0])
   );

ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_1_tag_buff_rep0  (
     .din (ict_itlb_way_1_tag_f[28:0]     ),
     .dout(ict_itlb_way_1_tag_f_rep0[28:0])
   );

ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_2_tag_buff_rep0  (
     .din (ict_itlb_way_2_tag_f[28:0]     ),
     .dout(ict_itlb_way_2_tag_f_rep0[28:0])
   );

ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_3_tag_buff_rep0  (
     .din (ict_itlb_way_3_tag_f[28:0]     ),
     .dout(ict_itlb_way_3_tag_f_rep0[28:0])
   );

ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_4_tag_buff_rep0  (
     .din (ict_itlb_way_4_tag_f[28:0]     ),
     .dout(ict_itlb_way_4_tag_f_rep0[28:0])
   );

ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_5_tag_buff_rep0  (
     .din (ict_itlb_way_5_tag_f[28:0]     ),
     .dout(ict_itlb_way_5_tag_f_rep0[28:0])
   );

ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_6_tag_buff_rep0  (
     .din (ict_itlb_way_6_tag_f[28:0]     ),
     .dout(ict_itlb_way_6_tag_f_rep0[28:0])
   );

ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_7_tag_buff_rep0  (
     .din (ict_itlb_way_7_tag_f[28:0]     ),
     .dout(ict_itlb_way_7_tag_f_rep0[28:0])
   );

ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_8__stack_32c__width_30 asi_tag_mux  (
 .scan_in(asi_tag_mux_scanin),
 .scan_out(asi_tag_mux_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .se  ( tcu_se_scancollar_out ) ,
 .din0( ict_itlb_way_0_tag_f[29:0]), 
 .din1( ict_itlb_way_1_tag_f[29:0]), 
 .din2( ict_itlb_way_2_tag_f[29:0]), 
 .din3( ict_itlb_way_3_tag_f[29:0]), 
 .din4( ict_itlb_way_4_tag_f[29:0]), 
 .din5( ict_itlb_way_5_tag_f[29:0]), 
 .din6( ict_itlb_way_6_tag_f[29:0]), 
 .din7( ict_itlb_way_7_tag_f[29:0]), 
 .sel0( agc_sel_tg_data_f[0]),
 .sel1( agc_sel_tg_data_f[1]),
 .sel2( agc_sel_tg_data_f[2]),
 .sel3( agc_sel_tg_data_f[3]),
 .sel4( agc_sel_tg_data_f[4]),
 .sel5( agc_sel_tg_data_f[5]),
 .sel6( agc_sel_tg_data_f[6]),
 .sel7( agc_sel_tg_data_f[7]),
 .dout( tg_rd_data[29:0] ),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


// msff_macro itb_cam_hit_reg (width=4) (
//         .scan_in(itb_cam_hit_reg_scanin),
//         .scan_out(itb_cam_hit_reg_scanout),
//         .clk  (l2clk),
//         .en  ( 1'b1                 ),  
//         .din({itb_cam_hit_c,
//               itb_itb_mhit_c,
//               itb_tte_data_parity,
//               agc_itb_tag_perr_c}) ,
//         .dout({cam_hit_p,
//               itb_mhit_p,
//               tte_data_parity_p,
//               itb_tag_perr_p}));


ifu_ftu_byp_dp_msff_macro__minbuff_1__mux_aonpe__ports_4__stack_64c__width_64 asi_itlb_mux  (
.scan_in(asi_itlb_mux_scanin),
.scan_out(asi_itlb_mux_scanout),
.clk ( l2clk                ),
.en  ( 1'b1                 ),  
.se  ( tcu_se_scancollar_out ) ,
.din0   ({itb_tte_tag[`TAG_PID_HI:`TAG_PID_LO],                 // PID
          itb_tte_tag[`TAG_REAL],                               // REAL
          itb_tte_data[`TAG_PARITY],                            // PARITY
          itb_tte_u_bit,                                        // USED
          10'b0,
          itb_tte_tag[`TAG_VA_47_28_HI:`TAG_VA_27_22_LO],
          itb_tte_tag[`TAG_VA_21_16_HI:`TAG_VA_21_16_LO],
          itb_tte_tag[`TAG_VA_15_13_HI:`TAG_VA_15_13_LO],
          itb_tte_tag[`TAG_CNTX0_HI:`TAG_CNTX0_LO]              // context
          }),
.din1   ({itb_tte_tag[`TAG_PID_HI:`TAG_PID_LO],                 // PID
          itb_tte_tag[`TAG_REAL],                               // REAL
          itb_tte_data[`TAG_PARITY],                            // PARITY
          itb_tte_u_bit,                                        // USED
          10'b0,
          itb_tte_tag[`TAG_VA_47_28_HI:`TAG_VA_27_22_LO],
          itb_tte_tag[`TAG_VA_21_16_HI:`TAG_VA_21_16_LO],
          itb_tte_tag[`TAG_VA_15_13_HI:`TAG_VA_15_13_LO],
          itb_tte_tag[`TAG_CNTX1_HI:`TAG_CNTX1_LO]              // context
          }),
.din2   ({itb_tte_tag[`TAG_V],                                  // V
          itb_tte_data[`DATA_NFO],                              // NFO
          itb_tte_data[`DATA_PARITY],                           // PARITY
          5'b0,                                                 // SOFT
          16'b0,
          itb_tte_data[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO],    // PA
          itb_tte_data[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO],
          itb_tte_data[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO],
          itb_tte_data[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO],
          itb_tte_data[`DATA_IE],                               // IE
          itb_tte_data[`DATA_E],                                // E
          itb_tte_data[`DATA_CP],                               // CP
          1'b0,                                                 // CV
          itb_tte_data[`DATA_P],                                // P
          1'b0,                                                 // EP
          itb_tte_data[`DATA_W],                                // W
          3'b0,
          itb_tte_data[`DATA_VA_27_22_V],                       // SZ
          itc_itb_data_sz_1,itb_tte_data[`DATA_VA_15_13_V]      // SZ
           }),
.din3( {itb_cam_hit_c, itb_itb_mhit_c, agc_itb_tag_perr_c, itb_tte_data_parity, 20'b0,ftu_paddr[39:13],13'b0}), 
.sel0( ftp_sel_itlb_tag_cntx0_c),
.sel1( ftp_sel_itlb_tag_cntx1_c),
.sel2( ftp_sel_itlb_data_c),
.sel3( ftp_sel_itlb_pa_c), 
.dout( it_rd_data[63:0] ),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


//     mbist_wdata[68:0] = {    mbist_wdata_bf[1:0], mbist_wdata_bf[7:0],mbist_wdata_bf[7:6],          // [68:56]
//                              mbist_wdata_bf[4:2],                                                   // [55:53]
//                              1'b0,                                                                  // [52]
//                              mbist_wdata_bf[0],{3{mbist_wdata_bf[7:0]}},mbist_wdata_bf[7],          // [51:26]
//                              1'b0,                                                                  // [25]
//                              mbist_wdata_bf[6:0],                                                   // [24:18]
//                              1'b0,                                                                  // [17]
//                              mbist_wdata_bf[7:5],                                                   // [16:14]
//                              1'b0,                                                                  // [13]
//                              mbist_wdata_bf[4:0],mbist_wdata_bf[7:0]};                              // [12:0]
//
//     data_mbist_wdata[37:0] = { mbist_wdata_bf[4:0],mbist_wdata_bf[7:1],                             // [37:26]
//                              1'b0,                                                                  // [25]
//                              mbist_wdata_bf[0],mbist_wdata_bf[7:2],                                 // [24:18]
//                              1'b0,                                                                  // [17]
//                              mbist_wdata_bf[0], mbist_wdata_bf[7:6],                                // [16:14]
//                              1'b0,                                                                  // [13]
//                              mbist_wdata_bf[4:0],mbist_wdata_bf[7:0]};                              // [12:0]
//    
//
//
//   ifu_agd_pc_bf[47:13] = ({itd_tag[51:32],
//                            itd_tag[31:26],
//                            itd_tag[23:18],
//                            itd_tag[16:14]})
//
//  tte_tag[65:0] =       ({itd_tag[68:52],                   // [65:49]  ---> itd_tag[68:52]--> mbist_wdata_bf[2:0], 
//                                                                                               mbist_wdata_bf[7:0],mbist_data[7:6],mbist_data[4:2],1'b0 
//                          ifu_agd_pc_bf[47:22],             // [48:23]  ---> itd_tag[51:26]--> mbist_data[0],{3{mbist_wdata_bf[7:0]}},mbist_wdata_bf[7]
//                          itd_tag[24],                      // [22]     ---> itd_tag[24]-----> mbist_data[6]
//                          ifu_agd_pc_bf[21:16],             // [21:16]  ---> itd_tag[23:18]--> mbist_data[5:0]
//                          ifu_agd_pc_bf[15:13],             // [15:13]  ---> itd_tag[16:14]--> mbist_data[7:5]
//                          itd_tag[12:0]}),                  // [12:0]   ---> itd_tag[12:0]---> mbist_data[4:0],mbist_data[7:0]
//

// TAG_CNTX1_HI    65
// TAG_CNTX1_LO    53
// TAG_PID_HI      52
// TAG_PID_LO      50
// TAG_REAL        49
// TAG_VA_47_28_HI 48
// TAG_VA_47_28_LO 29
// TAG_VA_27_22_HI 28
// TAG_VA_27_22_LO 23
// TAG_V           22
// TAG_VA_21_16_HI 21
// TAG_VA_21_16_LO 16
// TAG_VA_15_13_HI 15
// TAG_VA_15_13_LO 13
// TAG_CNTX0_HI    12
// TAG_CNTX0_LO     0


ifu_ftu_byp_dp_msff_macro__minbuff_1__mux_aonpe__ports_4__stack_32c__width_32 itlb_bist_mux  (
.scan_in(itlb_bist_mux_scanin),
.scan_out(itlb_bist_mux_scanout),
.clk ( l2clk                ),
.en  ( 1'b1                 ),  
.se  ( tcu_se_scancollar_out ) ,
.din0   ( itb_tte_tag[31:0]),
.din1   ( itb_tte_tag[63:32]),
.din2   ( itb_tte_data[31:0] ),
.din3   ( {mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:1],itb_tte_u_bit,
           itb_tte_tag[65:64],itb_tte_data[37:32]} ),
.sel0   ( ftp_sel_mbist_itb_cycle0),
.sel1   ( ftp_sel_mbist_itb_cycle1),
.sel2   ( ftp_sel_mbist_itb_cycle2),
.sel3   ( ftp_sel_mbist_itb_cycle3),
.dout( itt_itd_cmp_data[31:0] ),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign  tag_mbist_wdata[65:0] = ({mbist_wdata_3_ff[1:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:5],mbist_wdata_3_ff[4:2],1'b0,  // [65:49]  
                                  mbist_wdata_3_ff[0],{3{mbist_wdata_3_ff[7:0]}},mbist_wdata_3_ff[7],                            // [48:23]
                                  mbist_wdata_3_ff[6],                                                                           // [22]
                                  mbist_wdata_3_ff[5:0],                                                                         // [21:16]
                                  mbist_wdata_3_ff[7:5],                                                                         // [15:13]
                                  mbist_wdata_3_ff[4:0],mbist_wdata_3_ff[7:0] }) ;                                               // [12:0]

assign data_mbist_wdata[37:0] = { mbist_wdata_3_ff[5:0],mbist_wdata_3_ff[7:2],                             // [37:26]
                                mbist_wdata_3_ff[1],                                                       // [25]
                                mbist_wdata_3_ff[0],mbist_wdata_3_ff[7:2],                                 // [24:18]
                                mbist_wdata_3_ff[1],                                                       // [17]
                                mbist_wdata_3_ff[0], mbist_wdata_3_ff[7:6],                                // [16:14]
                                mbist_wdata_3_ff[5],                                                       // [13]
                                mbist_wdata_3_ff[4:0],mbist_wdata_3_ff[7:0]};                              // [12:0]

  
ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_4__stack_32c__width_32 itlb_w_bist_data_mux  (
.scan_in(itlb_w_bist_data_mux_scanin),
.scan_out(itlb_w_bist_data_mux_scanout),
.clk ( l2clk                ),
.en  ( 1'b1                 ),  
.se  ( tcu_se_scancollar_out ) ,
.din0  ( tag_mbist_wdata[31:0]),
.din1  ( tag_mbist_wdata[63:32]),
.din2  ( data_mbist_wdata[31:0] ),
.din3  ( {mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],
          tag_mbist_wdata[65:64],data_mbist_wdata[37:32]} ),
.sel0  ( ftp_sel_mbist_itb_cycle0),
.sel1  ( ftp_sel_mbist_itb_cycle1),
.sel2  ( ftp_sel_mbist_itb_cycle2),
.sel3  ( ftp_sel_mbist_itb_cycle3),
.dout( mbist_cmp_data_4_ff[31:0] ),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_byp_dp_msff_macro__stack_16c__width_16 bist_data_stage_a  (
 .scan_in(bist_data_stage_a_scanin),
 .scan_out(bist_data_stage_a_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din  ({agd_mbist_wdata_bf[7:0],mbist_wdata_2_ff[7:3],mbi_cambist_run,mbi_addr[5:4]}), 
 .dout ({mbist_wdata_2_ff[7:0],  mbist_wdata_3_ff[7:3],cambist_run_ff,mbist_addr_1[5:4]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_byp_dp_msff_macro__stack_16c__width_15 bist_data_stage_b  (
 .scan_in(bist_data_stage_b_scanin),
 .scan_out(bist_data_stage_b_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din  ({mbist_wdata_2_ff[2:0],mbist_wdata_3_ff[7:0],mbi_addr[3:0] }), 
 .dout ({mbist_wdata_3_ff[2:0],mbist_wdata_4_ff[7:0],mbist_addr_1[3:0] } ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_byp_dp_msff_macro__stack_16c__width_14 bist_data_stage_dup_b  (
 .scan_in(bist_data_stage_dup_b_scanin),
 .scan_out(bist_data_stage_dup_b_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din  ({mbist_wdata_3_ff[7:0], mbist_addr_1[5:0] }), 
 .dout ({mbist_wdata_4_dup_ff[7:0], mbist_addr_2[5:0] } ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_byp_dp_msff_macro__stack_16c__width_16 bist_data_stage_c  (
 .scan_in(bist_data_stage_c_scanin),
 .scan_out(bist_data_stage_c_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din  ({ mbist_itb_read_en_2_ff,mbist_itb_read_en_3_ff,
         it_mbist_fail_q ,ftp_mbi_icd_read_en_bf, mbist_icd_read_en_2_ff,
         mbist_icd_read_en_3_ff, ict_mbist_fail_q,icd_mbist_fail_q,
         itc_mbi_itb_read_en,ftp_mbi_ict_read_en_bf,mbist_ict_read_en_2_ff,mbist_addr_3[4:0] }),
 .dout ({ mbist_itb_read_en_3_ff, mbist_itb_read_en_4_ff,
         ftu_mbi_itb_fail, mbist_icd_read_en_2_ff , mbist_icd_read_en_3_ff, 
         mbist_icd_read_en_4_ff, ftu_mbi_ict_fail,ftu_mbi_icd_fail,
         mbist_itb_read_en_2_ff,mbist_ict_read_en_2_ff,mbist_ict_read_en_3_ff,mbist_addr_4[4:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// mux_macro cmp_data_mux (width=33,ports=2,mux=aonpe,stack=34c) (
//  .din0( {mbist_wdata_3_ff[0],mbist_wdata_3_ff[7:6],tg_rd_data[29:0]}),
//  .din1( ic_rd_data[32:0]),              
//  .sel0( mbist_ict_read_en_3_ff),
//  .sel1( mbist_icd_read_en_4_ff),
//  .dout( ict_icd_cmp_data[32:0] ));

ifu_ftu_byp_dp_cmp_macro__dcmp_8x__width_32 ict_fail_detect  (
    .dout( ict_mbist_fail_unq_l),
    .din0( {mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0]}),
    .din1( {mbist_wdata_3_ff[7:6],tg_rd_data[29:0]})
);

// mux_macro itb_cmp_data_mux_1 (width=16,ports=2,mux=aope,stack=16c) (
//  .din0( {mbist_wdata_4_ff[7:2],it_rd_data[57:48]}),
//  .din1( it_rd_data[31:16]),              
//  .sel0( cmpsel_4_ff[0]),
//  .dout( itt_itd_cmp_data[31:16] ));

// mux_macro itb_cmp_data_mux_0 (width=16,ports=2,mux=aope,stack=16c) (
//  .din0( it_rd_data[47:32]),
//  .din1( it_rd_data[15:0]),              
//  .sel0( cmpsel_4_ff[0]),
//  .dout( itt_itd_cmp_data[15:0] ));


ifu_ftu_byp_dp_cmp_macro__dcmp_8x__width_32 icd_fail_detect  (
    .dout( icd_mbist_fail_31_0_l),
    .din0( {mbist_wdata_4_dup_ff[7:0],mbist_wdata_4_dup_ff[7:0],mbist_wdata_4_dup_ff[7:0],mbist_wdata_4_dup_ff[7:0]}),
    .din1( ic_rd_data[31:0])
);
ifu_ftu_byp_dp_xor_macro__ports_2__width_1 icd_fail_detect_xnor  (
    .din0( mbist_wdata_4_ff[0]) ,
    .din1( ic_rd_data[32]) ,
    .dout( icd_mbist_fail_32)) ;


ifu_ftu_byp_dp_cmp_macro__dcmp_8x__width_32 it_fail_detect  (
    .dout( mbist_it_fail_unq_l),
    .din0( mbist_cmp_data_4_ff[31:0]),
    .din1( itt_itd_cmp_data[31:0])
);

 ifu_ftu_byp_dp_inv_macro__width_5 ict_fail_macro  (
    .dout( {ict_mbist_fail_unq,icd_mbist_fail_31_0, mbist_it_fail_unq,cambist_run_ff_l,sel_mbist_itb_cycle1_l}), 
    .din(  {ict_mbist_fail_unq_l,icd_mbist_fail_31_0_l, mbist_it_fail_unq_l,cambist_run_ff,ftp_sel_mbist_itb_cycle1})
);

 ifu_ftu_byp_dp_or_macro__ports_2__width_1 icd_final_fail  (
    .din0 (icd_mbist_fail_32),
    .din1 (icd_mbist_fail_31_0) ,
    .dout (icd_mbist_fail_unq)) ;

//  or_macro read_or_macro (width=2,ports=2) (
//     .dout( {mbist_read_en,mbist_it_read_en}), 
//     .din0( {mbist_ict_read_en_3_ff,1'b0}),
//     .din1( {mbist_icd_read_en_4_ff,mbist_itb_read_en_3_ff})
// );

// assign mbist_it_read_en = mbist_itb_read_en_4_ff ;

 ifu_ftu_byp_dp_and_macro__width_5 fail_qual  (
    .dout( {ict_mbist_fail_q,icd_mbist_fail_q,it_mbist_fail_q,mbist_it_read_en,rbit_modify_unused}),
    .din0( {ict_mbist_fail_unq,icd_mbist_fail_unq,mbist_it_fail_unq,cambist_run_ff_l,sel_mbist_itb_cycle1_l_ff}), 
    .din1( {mbist_ict_read_en_3_ff,mbist_icd_read_en_4_ff,mbist_it_read_en,mbist_itb_read_en_4_ff,mbist_wdata_4_ff[1]})) ;


// assign ftu_mbi_icd_fail = ftu_mbi_ict_fail ;

ifu_ftu_byp_dp_msff_macro__minbuff_1__stack_16c__width_16 itb_data_for_cam  (
 .scan_in(itb_data_for_cam_scanin),
 .scan_out(itb_data_for_cam_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din  ({itb_tte_data[5:0] , itb_tte_u_bit , itb_tte_tag[`TAG_V],mbist_addr_2[5:0],sel_mbist_itb_cycle1_l,mbist_addr_3[5]}), 
 .dout ({itb_tte_data_1[5:0], ftu_mbi_tlb_used,   ftu_mbi_tlb_valid,mbist_addr_3[5:0] , sel_mbist_itb_cycle1_l_ff,mbist_addr_4[5]}  ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_byp_dp_cmp_macro__width_8 cambist_cmp  (
        .din0   ({2'b0,mbist_addr_4[5:0]}),
        .din1   ({2'b0,itb_tte_data_1[5:0]}),
        .dout   (ftu_mbi_tlb_data_cmp)
);


// assign se = tcu_scan_en ;
// fixscan start:
assign by_pass_i0i1_f_reg_scanin = scan_in                  ;
assign by_pass_i2i3_f_reg_scanin = by_pass_i0i1_f_reg_scanout;
assign by_pass_i0i1_c_reg_scanin = by_pass_i2i3_f_reg_scanout;
assign by_pass_i2i3_c_reg_scanin = by_pass_i0i1_c_reg_scanout;
assign asi_word_muxx_scanin      = by_pass_i2i3_c_reg_scanout;
assign asi_tag_mux_scanin        = asi_word_muxx_scanout    ;
assign asi_itlb_mux_scanin       = asi_tag_mux_scanout      ;
assign itlb_bist_mux_scanin      = asi_itlb_mux_scanout     ;
assign itlb_w_bist_data_mux_scanin = itlb_bist_mux_scanout    ;
assign bist_data_stage_a_scanin  = itlb_w_bist_data_mux_scanout;
assign bist_data_stage_b_scanin  = bist_data_stage_a_scanout;
assign bist_data_stage_dup_b_scanin = bist_data_stage_b_scanout;
assign bist_data_stage_c_scanin  = bist_data_stage_dup_b_scanout;
assign itb_data_for_cam_scanin   = bist_data_stage_c_scanout;
assign scan_out                  = itb_data_for_cam_scanout ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module ifu_ftu_byp_dp_buff_macro__dbuff_32x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [64:0] so;

  input [65:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [65:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_byp_dp_buff_macro__dbuff_48x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_mux_macro__mux_pgpe__ports_4__stack_66c__width_66 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [65:0] din0;
  input [65:0] din1;
  input [65:0] din2;
  input [65:0] din3;
  input sel0;
  input sel1;
  input sel2;
  input muxtst;
  input test;
  output [65:0] dout;


cl_dp1_penc4_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
  .test(test)
);

mux4 #(66)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
  .in2(din2[65:0]),
  .in3(din3[65:0]),
.dout(dout[65:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_mux_macro__dmux_8x__mux_pgpe__ports_4__stack_66c__width_66 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [65:0] din0;
  input [65:0] din1;
  input [65:0] din2;
  input [65:0] din3;
  input sel0;
  input sel1;
  input sel2;
  input muxtst;
  input test;
  output [65:0] dout;


cl_dp1_penc4_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
  .test(test)
);

mux4 #(66)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
  .in2(din2[65:0]),
  .in3(din3[65:0]),
.dout(dout[65:0]),
  .muxtst(muxtst)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_4__stack_34c__width_33 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire [32:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [31:0] so;

  input [32:0] din0;
  input sel0;
  input [32:0] din1;
  input sel1;
  input [32:0] din2;
  input sel2;
  input [32:0] din3;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [32:0] dout;


  output scan_out;


cl_dp1_muxbuff4_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(33)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
  .in2(din2[32:0]),
  .in3(din3[32:0]),
.dout(muxout[32:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(33)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[32:0]),
.si({scan_in,so[31:0]}),
.so({so[31:0],scan_out}),
.q(dout[32:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_byp_dp_buff_macro__dbuff_16x__rep_1__stack_34c__width_33 (
  din, 
  dout);
  input [32:0] din;
  output [32:0] dout;


buff #(33)  d0_0 (
.in(din[32:0]),
.out(dout[32:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 (
  din, 
  dout);
  input [28:0] din;
  output [28:0] dout;


buff #(29)  d0_0 (
.in(din[28:0]),
.out(dout[28:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_8__stack_32c__width_30 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;
wire [29:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [28:0] so;

  input [29:0] din0;
  input sel0;
  input [29:0] din1;
  input sel1;
  input [29:0] din2;
  input sel2;
  input [29:0] din3;
  input sel3;
  input [29:0] din4;
  input sel4;
  input [29:0] din5;
  input sel5;
  input [29:0] din6;
  input sel6;
  input [29:0] din7;
  input sel7;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [29:0] dout;


  output scan_out;


cl_dp1_muxbuff8_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(30)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[29:0]),
  .in1(din1[29:0]),
  .in2(din2[29:0]),
  .in3(din3[29:0]),
  .in4(din4[29:0]),
  .in5(din5[29:0]),
  .in6(din6[29:0]),
  .in7(din7[29:0]),
.dout(muxout[29:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(30)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[29:0]),
.si({scan_in,so[28:0]}),
.so({so[28:0],scan_out}),
.q(dout[29:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__minbuff_1__mux_aonpe__ports_4__stack_64c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_muxbuff4_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__minbuff_1__mux_aonpe__ports_4__stack_32c__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire [31:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  input [31:0] din2;
  input sel2;
  input [31:0] din3;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_muxbuff4_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(32)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
.dout(muxout[31:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_4__stack_32c__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire [31:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  input [31:0] din2;
  input sel2;
  input [31:0] din3;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_muxbuff4_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(32)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
.dout(muxout[31:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__stack_16c__width_16 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [14:0] so;

  input [15:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [15:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__stack_16c__width_15 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [13:0] so;

  input [14:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [14:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[14:0]),
.si({scan_in,so[13:0]}),
.so({so[13:0],scan_out}),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__stack_16c__width_14 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [12:0] so;

  input [13:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [13:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module ifu_ftu_byp_dp_cmp_macro__dcmp_8x__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module ifu_ftu_byp_dp_xor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module ifu_ftu_byp_dp_inv_macro__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


inv #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module ifu_ftu_byp_dp_or_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ftu_byp_dp_and_macro__width_5 (
  din0, 
  din1, 
  dout);
  input [4:0] din0;
  input [4:0] din1;
  output [4:0] dout;


and2 #(5)  d0_0 (
.in0(din0[4:0]),
.in1(din1[4:0]),
.out(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_byp_dp_msff_macro__minbuff_1__stack_16c__width_16 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [14:0] so;

  input [15:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [15:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module ifu_ftu_byp_dp_cmp_macro__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output dout;


cmp #(8)  m0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout)
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_cms_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_cms_ctl (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  lsu_ic_enable, 
  lsu_ifu_direct_map, 
  agd_direct_map_rep_way, 
  ftp_curr_fetch_thr_f, 
  ftu_agc_thr0_cmiss_c, 
  ftu_agc_thr1_cmiss_c, 
  ftu_agc_thr2_cmiss_c, 
  ftu_agc_thr3_cmiss_c, 
  ftu_agc_thr4_cmiss_c, 
  ftu_agc_thr5_cmiss_c, 
  ftu_agc_thr6_cmiss_c, 
  ftu_agc_thr7_cmiss_c, 
  cmu_ic_data_parity, 
  ftu_paddr_unq, 
  agc_any_invalidation_req_f, 
  itb_tte_cp_c, 
  itc_bypass_bf, 
  cmu_l2_err, 
  tlu_cerer_icl2u, 
  tlu_cerer_icl2nd, 
  ftu_thrx_un_cacheable, 
  ftu_rep_way, 
  cms_ic_modified_parity, 
  ftu_paddr, 
  scan_out) ;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire itb_tte_cp_c_q;
wire itb_bypass_c;
wire ic_disabled_c;
wire any_invalidation_req_c_l;
wire flip_parity_ff;
wire any_miss;
wire [2:0] rep_way_inc;
wire sel_miss;
wire ifu_direct_map_ff;
wire sel_direct_map;
wire sel_hold;
wire [2:0] rep_way_in;
wire flip_parity;
wire cerer_icl2u_ff;
wire cerer_icl2nd_ff;
wire any_invalidation_req_f_l;
wire rep_way_reg_scanin;
wire rep_way_reg_scanout;
wire itb_bypass_f;
wire ic_enable_reg_scanin;
wire ic_enable_reg_scanout;
wire [7:0] cms_icache_enable;
wire ic_disabled_f;
wire ic_disabled_reg_scanin;
wire ic_disabled_reg_scanout;
wire se;
wire spares_scanin;
wire spares_scanout;
 

input tcu_scan_en ;
input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;

input [7:0] lsu_ic_enable    ; 
input       lsu_ifu_direct_map;
input [2:0] agd_direct_map_rep_way; 

input [7:0] ftp_curr_fetch_thr_f    ; 
// input [7:0] agd_itlb_valid_f    ; 
   
// input       agc_qualify_cmiss    ;


 input        ftu_agc_thr0_cmiss_c;
 input        ftu_agc_thr1_cmiss_c;
 input        ftu_agc_thr2_cmiss_c;
 input        ftu_agc_thr3_cmiss_c;
 input        ftu_agc_thr4_cmiss_c;
 input        ftu_agc_thr5_cmiss_c;
 input        ftu_agc_thr6_cmiss_c;
 input        ftu_agc_thr7_cmiss_c;
 input [7:0]  cmu_ic_data_parity;
 input [39:37]  ftu_paddr_unq;
 input        agc_any_invalidation_req_f;
 input        itb_tte_cp_c ;
 input        itc_bypass_bf ;
 input [1:0]  cmu_l2_err     ;
 input        tlu_cerer_icl2u     ;
 input        tlu_cerer_icl2nd    ;


output       ftu_thrx_un_cacheable;

output [2:0] ftu_rep_way;
output [7:0] cms_ic_modified_parity;
output [39:37]  ftu_paddr;


output   scan_out;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan


ifu_ftu_cms_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


///////////////////////////////////////////////////////////
// Generate duplicate miss reset signal from WOB bits.   //
///////////////////////////////////////////////////////////
assign  itb_tte_cp_c_q = itb_tte_cp_c | itb_bypass_c ; 

assign ftu_thrx_un_cacheable = (ftu_paddr[39] | ic_disabled_c | ~itb_tte_cp_c_q) & any_invalidation_req_c_l ;
assign cms_ic_modified_parity[7:0] = (cmu_ic_data_parity[7:0] ^ {8{flip_parity_ff}}) ;


//////////////////////////////////////////////////////////////////
// Replace_way generation. The replace way is just a shifter which
// is shifted whenever a miss is sent to the cmu
//////////////////////////////////////////////////////////////////

assign any_miss = ftu_agc_thr7_cmiss_c | ftu_agc_thr6_cmiss_c | ftu_agc_thr5_cmiss_c |
                  ftu_agc_thr4_cmiss_c | ftu_agc_thr3_cmiss_c | ftu_agc_thr2_cmiss_c |
                  ftu_agc_thr1_cmiss_c | ftu_agc_thr0_cmiss_c ;  

assign rep_way_inc[2] = (!ftu_rep_way[2] &  ftu_rep_way[1]  &  ftu_rep_way[0]) | 
                        ( ftu_rep_way[2] & !ftu_rep_way[0]) | 
                        ( ftu_rep_way[2] & !ftu_rep_way[1]) ;
assign rep_way_inc[1] = (ftu_rep_way[1]  & !ftu_rep_way[0]) | 
                        (!ftu_rep_way[1]  &  ftu_rep_way[0]) ;
assign rep_way_inc[0] = (!ftu_rep_way[0]);

assign sel_miss        = (any_miss & ~ifu_direct_map_ff);
assign sel_direct_map  =  ifu_direct_map_ff;
assign sel_hold        = ~any_miss & ~ifu_direct_map_ff ;

assign rep_way_in[2:0]  = ({3{sel_miss}}       &  rep_way_inc[2:0] ) | 
                          ({3{sel_direct_map}} &  agd_direct_map_rep_way[2:0]      ) | 
                          ({3{sel_hold}}       &  ftu_rep_way[2:0]      ) ; 

assign flip_parity =   (cmu_l2_err[1] & ~cmu_l2_err[0] & cerer_icl2u_ff) |
                       (cmu_l2_err[1] &  cmu_l2_err[0] & cerer_icl2nd_ff) ; 
 
assign any_invalidation_req_f_l = ~agc_any_invalidation_req_f ;
ifu_ftu_cms_ctl_msff_ctl_macro__width_10 rep_way_reg  (
 .scan_in(rep_way_reg_scanin),
 .scan_out(rep_way_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({rep_way_in[2:0],flip_parity,lsu_ifu_direct_map,itc_bypass_bf,itb_bypass_f, 
         any_invalidation_req_f_l,tlu_cerer_icl2u,tlu_cerer_icl2nd}),
 .dout ({ftu_rep_way[2:0],flip_parity_ff,ifu_direct_map_ff,itb_bypass_f,itb_bypass_c,
         any_invalidation_req_c_l,cerer_icl2u_ff,cerer_icl2nd_ff}),
  .siclk(siclk),
  .soclk(soclk));

assign ftu_paddr[39:37] = ftu_paddr_unq[39:37] & {3{any_invalidation_req_c_l}} ;


ifu_ftu_cms_ctl_msff_ctl_macro__width_8 ic_enable_reg  (
 .scan_in(ic_enable_reg_scanin),
 .scan_out(ic_enable_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (lsu_ic_enable[7:0]),
 .dout (cms_icache_enable[7:0]),
  .siclk(siclk),
  .soclk(soclk)) ;


assign ic_disabled_f = (ftp_curr_fetch_thr_f[0] & ~cms_icache_enable[0] ) |
                     (ftp_curr_fetch_thr_f[1] & ~cms_icache_enable[1] ) |
                     (ftp_curr_fetch_thr_f[2] & ~cms_icache_enable[2] ) |
                     (ftp_curr_fetch_thr_f[3] & ~cms_icache_enable[3] ) |
                     (ftp_curr_fetch_thr_f[4] & ~cms_icache_enable[4] ) |
                     (ftp_curr_fetch_thr_f[5] & ~cms_icache_enable[5] ) |
                     (ftp_curr_fetch_thr_f[6] & ~cms_icache_enable[6] ) |
                     (ftp_curr_fetch_thr_f[7] & ~cms_icache_enable[7] ) ;

ifu_ftu_cms_ctl_msff_ctl_macro__width_1 ic_disabled_reg  (
 .scan_in(ic_disabled_reg_scanin),
 .scan_out(ic_disabled_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (ic_disabled_f),
 .dout (ic_disabled_c),
  .siclk(siclk),
  .soclk(soclk)) ;


assign se = tcu_scan_en ;
///////////////////////////////////////////////////////////////////////
// Spare circuits                                                    //
///////////////////////////////////////////////////////////////////////
ifu_ftu_cms_ctl_spare_ctl_macro__num_1 spares  (
        .scan_in(spares_scanin),
        .scan_out(spares_scanout),
        .l1clk  (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// fixscan start:
assign rep_way_reg_scanin        = scan_in                  ;
assign ic_enable_reg_scanin      = rep_way_reg_scanout      ;
assign ic_disabled_reg_scanin    = ic_enable_reg_scanout    ;
assign spares_scanin             = ic_disabled_reg_scanout  ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_cms_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_cms_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_cms_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_cms_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ftu_cms_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_ctx_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_ctx_dp (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  wmr_scan_out, 
  lsu_ifu_ctxt_data, 
  agc_thr0_cntx_0_sel_ff, 
  agc_thr0_cntx_1_sel_ff, 
  agc_thr1_cntx_0_sel_ff, 
  agc_thr1_cntx_1_sel_ff, 
  agc_thr2_cntx_0_sel_ff, 
  agc_thr2_cntx_1_sel_ff, 
  agc_thr3_cntx_0_sel_ff, 
  agc_thr3_cntx_1_sel_ff, 
  agc_thr4_cntx_0_sel_ff, 
  agc_thr4_cntx_1_sel_ff, 
  agc_thr5_cntx_0_sel_ff, 
  agc_thr5_cntx_1_sel_ff, 
  agc_thr6_cntx_0_sel_ff, 
  agc_thr6_cntx_1_sel_ff, 
  agc_thr7_cntx_0_sel_ff, 
  agc_thr7_cntx_1_sel_ff, 
  agc_thr0_cntx_0_sel, 
  agc_thr0_cntx_1_sel, 
  agc_thr1_cntx_0_sel, 
  agc_thr1_cntx_1_sel, 
  agc_thr2_cntx_0_sel, 
  agc_thr2_cntx_1_sel, 
  agc_thr3_cntx_0_sel, 
  agc_thr3_cntx_1_sel, 
  agc_thr4_cntx_0_sel, 
  agc_thr4_cntx_1_sel, 
  agc_thr5_cntx_0_sel, 
  agc_thr5_cntx_1_sel, 
  agc_thr6_cntx_0_sel, 
  agc_thr6_cntx_1_sel, 
  agc_thr7_cntx_0_sel, 
  agc_thr7_cntx_1_sel, 
  ftp_itb_fetch_thr_bf, 
  itc_thr_to_write, 
  tlu_tl_gt_0, 
  ftp_itlb_probe_req_l, 
  ctx_curr_cntx_0_bf, 
  ctx_curr_cntx_1_bf, 
  ctx_cntx_0_to_write_bf, 
  ctx_cntx_1_to_write_bf, 
  scan_out) ;
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire tlu_tl_gt_0_reg_scanin;
wire tlu_tl_gt_0_reg_scanout;
wire [7:0] gt_t_zero_to_buf;
wire [7:0] gt_t_zero;
wire lsu_ifu_data_reg_scanin;
wire lsu_ifu_data_reg_scanout;
wire [12:0] ifu_ctx_data_ff;
wire prty_ctxt;
wire [13:0] thr0_cntx_0;
wire thr0_prty_ctx_0;
wire [13:0] thr0_cntx_1;
wire thr0_prty_ctx_1;
wire [13:0] thr1_cntx_0;
wire thr1_prty_ctx_0;
wire [13:0] thr1_cntx_1;
wire thr1_prty_ctx_1;
wire [13:0] thr2_cntx_0;
wire thr2_prty_ctx_0;
wire [13:0] thr2_cntx_1;
wire thr2_prty_ctx_1;
wire [13:0] thr3_cntx_0;
wire thr3_prty_ctx_0;
wire [13:0] thr3_cntx_1;
wire thr3_prty_ctx_1;
wire [13:0] thr4_cntx_0;
wire thr4_prty_ctx_0;
wire [13:0] thr4_cntx_1;
wire thr4_prty_ctx_1;
wire [13:0] thr5_cntx_0;
wire thr5_prty_ctx_0;
wire [13:0] thr5_cntx_1;
wire thr5_prty_ctx_1;
wire [13:0] thr6_cntx_0;
wire thr6_prty_ctx_0;
wire [13:0] thr6_cntx_1;
wire thr6_prty_ctx_1;
wire [13:0] thr7_cntx_0;
wire thr7_prty_ctx_0;
wire [13:0] thr7_cntx_1;
wire thr7_prty_ctx_1;
wire [13:0] next_thr0_cnxt_0_data;
wire [13:0] next_thr0_cnxt_1_data;
wire [13:0] next_thr1_cnxt_0_data;
wire [13:0] next_thr1_cnxt_1_data;
wire [13:0] next_thr2_cnxt_0_data;
wire [13:0] next_thr2_cnxt_1_data;
wire [13:0] next_thr3_cnxt_0_data;
wire [13:0] next_thr3_cnxt_1_data;
wire [13:0] next_thr4_cnxt_0_data;
wire [13:0] next_thr4_cnxt_1_data;
wire [13:0] next_thr5_cnxt_0_data;
wire [13:0] next_thr5_cnxt_1_data;
wire [13:0] next_thr6_cnxt_0_data;
wire [13:0] next_thr6_cnxt_1_data;
wire [13:0] next_thr7_cnxt_0_data;
wire [13:0] next_thr7_cnxt_1_data;
wire thr0_cntx_0_reg_wmr_scanin;
wire thr0_cntx_0_reg_wmr_scanout;
wire [7:0] ctx_gt_zero_0_;
wire [12:0] thr0_cntx_0_q;
wire thr0_cntx_1_reg_wmr_scanin;
wire thr0_cntx_1_reg_wmr_scanout;
wire [12:0] thr0_cntx_1_q;
wire thr1_cntx_0_reg_wmr_scanin;
wire thr1_cntx_0_reg_wmr_scanout;
wire [12:0] thr1_cntx_0_q;
wire thr1_cntx_1_reg_wmr_scanin;
wire thr1_cntx_1_reg_wmr_scanout;
wire [12:0] thr1_cntx_1_q;
wire thr2_cntx_0_reg_wmr_scanin;
wire thr2_cntx_0_reg_wmr_scanout;
wire [12:0] thr2_cntx_0_q;
wire thr2_cntx_1_reg_wmr_scanin;
wire thr2_cntx_1_reg_wmr_scanout;
wire [12:0] thr2_cntx_1_q;
wire thr3_cntx_0_reg_wmr_scanin;
wire thr3_cntx_0_reg_wmr_scanout;
wire [12:0] thr3_cntx_0_q;
wire thr3_cntx_1_reg_wmr_scanin;
wire thr3_cntx_1_reg_wmr_scanout;
wire [12:0] thr3_cntx_1_q;
wire thr4_cntx_0_reg_wmr_scanin;
wire thr4_cntx_0_reg_wmr_scanout;
wire [12:0] thr4_cntx_0_q;
wire thr4_cntx_1_reg_wmr_scanin;
wire thr4_cntx_1_reg_wmr_scanout;
wire [12:0] thr4_cntx_1_q;
wire thr5_cntx_0_reg_wmr_scanin;
wire thr5_cntx_0_reg_wmr_scanout;
wire [12:0] thr5_cntx_0_q;
wire thr5_cntx_1_reg_wmr_scanin;
wire thr5_cntx_1_reg_wmr_scanout;
wire [12:0] thr5_cntx_1_q;
wire thr6_cntx_0_reg_wmr_scanin;
wire thr6_cntx_0_reg_wmr_scanout;
wire [12:0] thr6_cntx_0_q;
wire thr6_cntx_1_reg_wmr_scanin;
wire thr6_cntx_1_reg_wmr_scanout;
wire [12:0] thr6_cntx_1_q;
wire thr7_cntx_0_reg_wmr_scanin;
wire thr7_cntx_0_reg_wmr_scanout;
wire [12:0] thr7_cntx_0_q;
wire thr7_cntx_1_reg_wmr_scanin;
wire thr7_cntx_1_reg_wmr_scanout;
wire [12:0] thr7_cntx_1_q;
wire [12:0] ctx_curr_cntx_0_to_buf;
wire [12:0] ctx_curr_cntx_1_to_buf;
wire [13:0] ctx_cntx_0_to_write_to_buf;
wire [13:0] ctx_cntx_1_to_write_to_buf;

        
input tcu_scan_en ;
input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;
// input tcu_muxtest;
input           spc_aclk_wmr;
input           wmr_scan_in;
output          wmr_scan_out;


input   [12:0]  lsu_ifu_ctxt_data;
input           agc_thr0_cntx_0_sel_ff;
input           agc_thr0_cntx_1_sel_ff;
input           agc_thr1_cntx_0_sel_ff;
input           agc_thr1_cntx_1_sel_ff;
input           agc_thr2_cntx_0_sel_ff;
input           agc_thr2_cntx_1_sel_ff;
input           agc_thr3_cntx_0_sel_ff;
input           agc_thr3_cntx_1_sel_ff;
input           agc_thr4_cntx_0_sel_ff;
input           agc_thr4_cntx_1_sel_ff;
input           agc_thr5_cntx_0_sel_ff;
input           agc_thr5_cntx_1_sel_ff;
input           agc_thr6_cntx_0_sel_ff;
input           agc_thr6_cntx_1_sel_ff;
input           agc_thr7_cntx_0_sel_ff;
input           agc_thr7_cntx_1_sel_ff;
 
input  [1:0]    agc_thr0_cntx_0_sel;
input  [1:0]    agc_thr0_cntx_1_sel;
input  [1:0]    agc_thr1_cntx_0_sel;
input  [1:0]    agc_thr1_cntx_1_sel;
input  [1:0]    agc_thr2_cntx_0_sel;
input  [1:0]    agc_thr2_cntx_1_sel;
input  [1:0]    agc_thr3_cntx_0_sel;
input  [1:0]    agc_thr3_cntx_1_sel;
input  [1:0]    agc_thr4_cntx_0_sel;
input  [1:0]    agc_thr4_cntx_1_sel;
input  [1:0]    agc_thr5_cntx_0_sel;
input  [1:0]    agc_thr5_cntx_1_sel;
input  [1:0]    agc_thr6_cntx_0_sel;
input  [1:0]    agc_thr6_cntx_1_sel;
input  [1:0]    agc_thr7_cntx_0_sel;
input  [1:0]    agc_thr7_cntx_1_sel;
input  [7:0]    ftp_itb_fetch_thr_bf;
input  [7:0]    itc_thr_to_write;
input  [7:0]    tlu_tl_gt_0;

input           ftp_itlb_probe_req_l;

output [12:0]   ctx_curr_cntx_0_bf;
output [12:0]   ctx_curr_cntx_1_bf;

output [13:0]   ctx_cntx_0_to_write_bf;
output [13:0]   ctx_cntx_1_to_write_bf;
output scan_out;

// scan renames
// assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
// assign siclk = spc_aclk;
// assign soclk = spc_bclk;
// assign muxtst = tcu_muxtest;
// end scan

ifu_ftu_ctx_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0  (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_8 tlu_tl_gt_0_reg  (
 .scan_in(tlu_tl_gt_0_reg_scanin),
 .scan_out(tlu_tl_gt_0_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),
 .din ( tlu_tl_gt_0[7:0]),
 .dout( gt_t_zero_to_buf[7:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


ifu_ftu_ctx_dp_buff_macro__stack_14c__width_8 tlu_tl_gt_0_buf   (
  .din(gt_t_zero_to_buf[7:0]),
  .dout(gt_t_zero[7:0]));


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_13 lsu_ifu_data_reg  (
 .scan_in(lsu_ifu_data_reg_scanin),
 .scan_out(lsu_ifu_data_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),
 .din ( lsu_ifu_ctxt_data[12:0]),
 .dout( ifu_ctx_data_ff[12:0]     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_ctx_dp_prty_macro__width_16 pgen_lsu_ctxt  (
        .din    ({1'b0,ifu_ctx_data_ff[12:0],2'b00}),
        .dout   (prty_ctxt)
);

///////////////////////////////////////////////////////////////////////
// Parity muxing.                                                    //
///////////////////////////////////////////////////////////////////////
// Thr0                                                              //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr0_cntx_0_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr0_cntx_0[13]),           // Hold the old value 
 .sel0( agc_thr0_cntx_0_sel_ff),
 .dout( thr0_prty_ctx_0                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr0_cntx_1_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr0_cntx_1[13]),            // Hold the old value 
 .sel0( agc_thr0_cntx_1_sel_ff),
 .dout( thr0_prty_ctx_1                               ));
///////////////////////////////////////////////////////////////////////
// Thr1                                                              //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr1_cntx_0_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr1_cntx_0[13]),           // Hold the old value 
 .sel0( agc_thr1_cntx_0_sel_ff),
 .dout( thr1_prty_ctx_0                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr1_cntx_1_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr1_cntx_1[13]),            // Hold the old value 
 .sel0( agc_thr1_cntx_1_sel_ff),
 .dout( thr1_prty_ctx_1                               ));

///////////////////////////////////////////////////////////////////////
// Thr2                                                              //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr2_cntx_0_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr2_cntx_0[13]),           // Hold the old value 
 .sel0( agc_thr2_cntx_0_sel_ff),
 .dout( thr2_prty_ctx_0                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr2_cntx_1_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr2_cntx_1[13]),            // Hold the old value 
 .sel0( agc_thr2_cntx_1_sel_ff),
 .dout( thr2_prty_ctx_1                               ));
///////////////////////////////////////////////////////////////////////
// Thr3                                                              //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr3_cntx_0_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr3_cntx_0[13]),           // Hold the old value 
 .sel0( agc_thr3_cntx_0_sel_ff),
 .dout( thr3_prty_ctx_0                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr3_cntx_1_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr3_cntx_1[13]),            // Hold the old value 
 .sel0( agc_thr3_cntx_1_sel_ff),
 .dout( thr3_prty_ctx_1                               ));

///////////////////////////////////////////////////////////////////////
// Thr4                                                              //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr4_cntx_0_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr4_cntx_0[13]),           // Hold the old value 
 .sel0( agc_thr4_cntx_0_sel_ff),
 .dout( thr4_prty_ctx_0                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr4_cntx_1_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr4_cntx_1[13]),            // Hold the old value 
 .sel0( agc_thr4_cntx_1_sel_ff),
 .dout( thr4_prty_ctx_1                               ));
///////////////////////////////////////////////////////////////////////
// Thr5                                                              //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr5_cntx_0_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr5_cntx_0[13]),           // Hold the old value 
 .sel0( agc_thr5_cntx_0_sel_ff),
 .dout( thr5_prty_ctx_0                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr5_cntx_1_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr5_cntx_1[13]),            // Hold the old value 
 .sel0( agc_thr5_cntx_1_sel_ff),
 .dout( thr5_prty_ctx_1                               ));

///////////////////////////////////////////////////////////////////////
// Thr6                                                              //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr6_cntx_0_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr6_cntx_0[13]),           // Hold the old value 
 .sel0( agc_thr6_cntx_0_sel_ff),
 .dout( thr6_prty_ctx_0                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr6_cntx_1_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr6_cntx_1[13]),            // Hold the old value 
 .sel0( agc_thr6_cntx_1_sel_ff),
 .dout( thr6_prty_ctx_1                               ));
///////////////////////////////////////////////////////////////////////
// Thr7                                                              //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr7_cntx_0_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr7_cntx_0[13]),           // Hold the old value 
 .sel0( agc_thr7_cntx_0_sel_ff),
 .dout( thr7_prty_ctx_0                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 thr7_cntx_1_parity_mux  (
 .din0( prty_ctxt),                   // new parity 
 .din1( thr7_cntx_1[13]),            // Hold the old value 
 .sel0( agc_thr7_cntx_1_sel_ff),
 .dout( thr7_prty_ctx_1                               ));

////////////////////////////////////////////////
// Thread 0 context muxing                    //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr0_cntx_0_mux  (
 .din0( {1'b0 ,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr0_prty_ctx_0, thr0_cntx_0[12:0]}),           // Hold the old context 
 .sel0( agc_thr0_cntx_0_sel[0]),
 .sel1( agc_thr0_cntx_0_sel[1]),
 .dout( next_thr0_cnxt_0_data[13:0]                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr0_cntx_1_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr0_prty_ctx_1, thr0_cntx_1[12:0]}),           // Hold the old context 
 .sel0( agc_thr0_cntx_1_sel[0]),
 .sel1( agc_thr0_cntx_1_sel[1]),
 .dout( next_thr0_cnxt_1_data[13:0]                               ));

////////////////////////////////////////////////
// Thread 1 context muxing                    //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr1_cntx_0_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr1_prty_ctx_0, thr1_cntx_0[12:0]}),           // Hold the old context 
 .sel0( agc_thr1_cntx_0_sel[0]),
 .sel1( agc_thr1_cntx_0_sel[1]),
 .dout( next_thr1_cnxt_0_data[13:0]                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr1_cntx_1_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr1_prty_ctx_1, thr1_cntx_1[12:0]}),           // Hold the old context 
 .sel0( agc_thr1_cntx_1_sel[0]),
 .sel1( agc_thr1_cntx_1_sel[1]),
 .dout( next_thr1_cnxt_1_data[13:0]                               ));


////////////////////////////////////////////////
// Thread 2 context muxing                    //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr2_cntx_0_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr2_prty_ctx_0, thr2_cntx_0[12:0]}),           // Hold the old context 
 .sel0( agc_thr2_cntx_0_sel[0]),
 .sel1( agc_thr2_cntx_0_sel[1]),
 .dout( next_thr2_cnxt_0_data[13:0]                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr2_cntx_1_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr2_prty_ctx_1, thr2_cntx_1[12:0]}),           // Hold the old context 
 .sel0( agc_thr2_cntx_1_sel[0]),
 .sel1( agc_thr2_cntx_1_sel[1]),
 .dout( next_thr2_cnxt_1_data[13:0]                               ));

////////////////////////////////////////////////
// Thread 3 context muxing                    //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr3_cntx_0_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr3_prty_ctx_0, thr3_cntx_0[12:0]}),           // Hold the old context 
 .sel0( agc_thr3_cntx_0_sel[0]),
 .sel1( agc_thr3_cntx_0_sel[1]),
 .dout( next_thr3_cnxt_0_data[13:0]                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr3_cntx_1_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr3_prty_ctx_1, thr3_cntx_1[12:0]}),           // Hold the old context 
 .sel0( agc_thr3_cntx_1_sel[0]),
 .sel1( agc_thr3_cntx_1_sel[1]),
 .dout( next_thr3_cnxt_1_data[13:0]                               ));

////////////////////////////////////////////////
// Thread 4 context muxing                    //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr4_cntx_0_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr4_prty_ctx_0, thr4_cntx_0[12:0]}),           // Hold the old context 
 .sel0( agc_thr4_cntx_0_sel[0]),
 .sel1( agc_thr4_cntx_0_sel[1]),
 .dout( next_thr4_cnxt_0_data[13:0]                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr4_cntx_1_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr4_prty_ctx_1, thr4_cntx_1[12:0]}),           // Hold the old context 
 .sel0( agc_thr4_cntx_1_sel[0]),
 .sel1( agc_thr4_cntx_1_sel[1]),
 .dout( next_thr4_cnxt_1_data[13:0]                               ));

////////////////////////////////////////////////
// Thread 5 context muxing                    //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr5_cntx_0_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr5_prty_ctx_0, thr5_cntx_0[12:0]}),           // Hold the old context 
 .sel0( agc_thr5_cntx_0_sel[0]),
 .sel1( agc_thr5_cntx_0_sel[1]),
 .dout( next_thr5_cnxt_0_data[13:0]                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr5_cntx_1_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr5_prty_ctx_1, thr5_cntx_1[12:0]}),           // Hold the old context 
 .sel0( agc_thr5_cntx_1_sel[0]),
 .sel1( agc_thr5_cntx_1_sel[1]),
 .dout( next_thr5_cnxt_1_data[13:0]                               ));


////////////////////////////////////////////////
// Thread 6 context muxing                    //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr6_cntx_0_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr6_prty_ctx_0, thr6_cntx_0[12:0]}),           // Hold the old context 
 .sel0( agc_thr6_cntx_0_sel[0]),
 .sel1( agc_thr6_cntx_0_sel[1]),
 .dout( next_thr6_cnxt_0_data[13:0]                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr6_cntx_1_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr6_prty_ctx_1, thr6_cntx_1[12:0]}),           // Hold the old context 
 .sel0( agc_thr6_cntx_1_sel[0]),
 .sel1( agc_thr6_cntx_1_sel[1]),
 .dout( next_thr6_cnxt_1_data[13:0]                               ));

////////////////////////////////////////////////
// Thread 7 context muxing                    //
////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr7_cntx_0_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr7_prty_ctx_0, thr7_cntx_0[12:0]}),           // Hold the old context 
 .sel0( agc_thr7_cntx_0_sel[0]),
 .sel1( agc_thr7_cntx_0_sel[1]),
 .dout( next_thr7_cnxt_0_data[13:0]                               ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 thr7_cntx_1_mux  (
 .din0( {1'b0,lsu_ifu_ctxt_data[12:0]}),      // new context from lsu
 .din1( {thr7_prty_ctx_1, thr7_cntx_1[12:0]}),           // Hold the old context 
 .sel0( agc_thr7_cntx_1_sel[0]),
 .sel1( agc_thr7_cntx_1_sel[1]),
 .dout( next_thr7_cnxt_1_data[13:0]                               ));

///////////////////////////////////////////////////////////////////////
// Context registers                                                 //
///////////////////////////////////////////////////////////////////////
////////////////////////////////////
// Thread 0 context registers     //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr0_cntx_0_reg  ( // FS:wmr_protect
 .scan_in(thr0_cntx_0_reg_wmr_scanin),
 .scan_out(thr0_cntx_0_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr0_cnxt_0_data[13:0]),
 .dout( thr0_cntx_0[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr0_cntx_0_q[13:0] = thr0_cntx_0[13:0] & {13{~gt_t_zero[0]}} ;

ifu_ftu_ctx_dp_nand_macro__ports_2__stack_14c__width_8 gt_z_nand    (
 .din0(gt_t_zero[7:0]),
 .din1({8{ftp_itlb_probe_req_l}}),
 .dout(ctx_gt_zero_0_[7:0])
);

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr0_cntx_0_and    (
 .din0({13{ctx_gt_zero_0_[0]}}),
 .din1(thr0_cntx_0[12:0]),
 .dout(thr0_cntx_0_q[12:0])
);


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr0_cntx_1_reg  (   // FS:wmr_protect
 .scan_in(thr0_cntx_1_reg_wmr_scanin),
 .scan_out(thr0_cntx_1_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr0_cnxt_1_data[13:0]),
 .dout( thr0_cntx_1[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));


ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr0_cntx_1_and    (
 .din0({13{ctx_gt_zero_0_[0]}}),
 .din1(thr0_cntx_1[12:0]),
 .dout(thr0_cntx_1_q[12:0])
);


// assign thr0_cntx_1_q[13:0] = thr0_cntx_1[13:0] & {13{~gt_t_zero[0]}} ;

////////////////////////////////////
// Thread 1 context registers     //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr1_cntx_0_reg  (   // FS:wmr_protect
 .scan_in(thr1_cntx_0_reg_wmr_scanin),
 .scan_out(thr1_cntx_0_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr1_cnxt_0_data[13:0]),
 .dout( thr1_cntx_0[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr1_cntx_0_q[13:0] = thr1_cntx_0[13:0] & {13{~gt_t_zero[1]}} ;


ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr1_cntx_0_and    (
 .din0({13{ctx_gt_zero_0_[1]}}),
 .din1(thr1_cntx_0[12:0]),
 .dout(thr1_cntx_0_q[12:0])
);


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr1_cntx_1_reg  (   // FS:wmr_protect
 .scan_in(thr1_cntx_1_reg_wmr_scanin),
 .scan_out(thr1_cntx_1_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr1_cnxt_1_data[13:0]),
 .dout( thr1_cntx_1[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr1_cntx_1_q[13:0] = thr1_cntx_1[13:0] & {13{~gt_t_zero[1]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr1_cntx_1_and    (
 .din0({13{ctx_gt_zero_0_[1]}}),
 .din1(thr1_cntx_1[12:0]),
 .dout(thr1_cntx_1_q[12:0])
);


////////////////////////////////////
// Thread 2 context registers     //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr2_cntx_0_reg  (   // FS:wmr_protect
 .scan_in(thr2_cntx_0_reg_wmr_scanin),
 .scan_out(thr2_cntx_0_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr2_cnxt_0_data[13:0]),
 .dout( thr2_cntx_0[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr2_cntx_0_q[13:0] = thr2_cntx_0[13:0] & {13{~gt_t_zero[2]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr2_cntx_0_and    (
 .din0({13{ctx_gt_zero_0_[2]}}),
 .din1(thr2_cntx_0[12:0]),
 .dout(thr2_cntx_0_q[12:0])
);

ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr2_cntx_1_reg  (   // FS:wmr_protect
 .scan_in(thr2_cntx_1_reg_wmr_scanin),
 .scan_out(thr2_cntx_1_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr2_cnxt_1_data[13:0]),
 .dout( thr2_cntx_1[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr2_cntx_1_q[13:0] = thr2_cntx_1[13:0] & {13{~gt_t_zero[2]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr2_cntx_1_and    (
 .din0({13{ctx_gt_zero_0_[2]}}),
 .din1(thr2_cntx_1[12:0]),
 .dout(thr2_cntx_1_q[12:0])
);


////////////////////////////////////
// Thread 3 context registers     //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr3_cntx_0_reg  (   // FS:wmr_protect
 .scan_in(thr3_cntx_0_reg_wmr_scanin),
 .scan_out(thr3_cntx_0_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr3_cnxt_0_data[13:0]),
 .dout( thr3_cntx_0[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr3_cntx_0_q[13:0] = thr3_cntx_0[13:0] & {13{~gt_t_zero[3]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr3_cntx_0_and    (
 .din0({13{ctx_gt_zero_0_[3]}}),
 .din1(thr3_cntx_0[12:0]),
 .dout(thr3_cntx_0_q[12:0])
);


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr3_cntx_1_reg  (   // FS:wmr_protect
 .scan_in(thr3_cntx_1_reg_wmr_scanin),
 .scan_out(thr3_cntx_1_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr3_cnxt_1_data[13:0]),
 .dout( thr3_cntx_1[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr3_cntx_1_q[13:0] = thr3_cntx_1[13:0] & {13{~gt_t_zero[3]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr3_cntx_1_and    (
 .din0({13{ctx_gt_zero_0_[3]}}),
 .din1(thr3_cntx_1[12:0]),
 .dout(thr3_cntx_1_q[12:0])
);


////////////////////////////////////
// Thread 4 context registers     //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr4_cntx_0_reg  (   // FS:wmr_protect
 .scan_in(thr4_cntx_0_reg_wmr_scanin),
 .scan_out(thr4_cntx_0_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr4_cnxt_0_data[13:0]),
 .dout( thr4_cntx_0[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr4_cntx_0_q[13:0] = thr4_cntx_0[13:0] & {13{~gt_t_zero[4]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr4_cntx_0_and    (
 .din0({13{ctx_gt_zero_0_[4]}}),
 .din1(thr4_cntx_0[12:0]),
 .dout(thr4_cntx_0_q[12:0])
);


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr4_cntx_1_reg  (   // FS:wmr_protect
 .scan_in(thr4_cntx_1_reg_wmr_scanin),
 .scan_out(thr4_cntx_1_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr4_cnxt_1_data[13:0]),
 .dout( thr4_cntx_1[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr4_cntx_1_q[13:0] = thr4_cntx_1[13:0] & {13{~gt_t_zero[4]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr4_cntx_1_and    (
 .din0({13{ctx_gt_zero_0_[4]}}),
 .din1(thr4_cntx_1[12:0]),
 .dout(thr4_cntx_1_q[12:0])
);


////////////////////////////////////
// Thread 5 context registers     //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr5_cntx_0_reg  (   // FS:wmr_protect
 .scan_in(thr5_cntx_0_reg_wmr_scanin),
 .scan_out(thr5_cntx_0_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr5_cnxt_0_data[13:0]),
 .dout( thr5_cntx_0[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr5_cntx_0_q[13:0] = thr5_cntx_0[13:0] & {13{~gt_t_zero[5]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr5_cntx_0_and    (
 .din0({13{ctx_gt_zero_0_[5]}}),
 .din1(thr5_cntx_0[12:0]),
 .dout(thr5_cntx_0_q[12:0])
);


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr5_cntx_1_reg  (   // FS:wmr_protect
 .scan_in(thr5_cntx_1_reg_wmr_scanin),
 .scan_out(thr5_cntx_1_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr5_cnxt_1_data[13:0]),
 .dout( thr5_cntx_1[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr5_cntx_1_q[13:0] = thr5_cntx_1[13:0] & {13{~gt_t_zero[5]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr5_cntx_1_and    (
 .din0({13{ctx_gt_zero_0_[5]}}),
 .din1(thr5_cntx_1[12:0]),
 .dout(thr5_cntx_1_q[12:0])
);


////////////////////////////////////
// Thread 6 context registers     //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr6_cntx_0_reg  (   // FS:wmr_protect
 .scan_in(thr6_cntx_0_reg_wmr_scanin),
 .scan_out(thr6_cntx_0_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr6_cnxt_0_data[13:0]),
 .dout( thr6_cntx_0[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr6_cntx_0_q[13:0] = thr6_cntx_0[13:0] & {13{~gt_t_zero[6]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr6_cntx_0_and    (
 .din0({13{ctx_gt_zero_0_[6]}}),
 .din1(thr6_cntx_0[12:0]),
 .dout(thr6_cntx_0_q[12:0])
);


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr6_cntx_1_reg  (   // FS:wmr_protect
 .scan_in(thr6_cntx_1_reg_wmr_scanin),
 .scan_out(thr6_cntx_1_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr6_cnxt_1_data[13:0]),
 .dout( thr6_cntx_1[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr6_cntx_1_q[13:0] = thr6_cntx_1[13:0] & {13{~gt_t_zero[6]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr6_cntx_1_and    (
 .din0({13{ctx_gt_zero_0_[6]}}),
 .din1(thr6_cntx_1[12:0]),
 .dout(thr6_cntx_1_q[12:0])
);


////////////////////////////////////
// Thread 7 context registers     //
////////////////////////////////////
ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr7_cntx_0_reg  (   // FS:wmr_protect
 .scan_in(thr7_cntx_0_reg_wmr_scanin),
 .scan_out(thr7_cntx_0_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr7_cnxt_0_data[13:0]),
 .dout( thr7_cntx_0[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr7_cntx_0_q[13:0] = thr7_cntx_0[13:0] & {13{~gt_t_zero[7]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr7_cntx_0_and    (
 .din0({13{ctx_gt_zero_0_[7]}}),
 .din1(thr7_cntx_0[12:0]),
 .dout(thr7_cntx_0_q[12:0])
);


ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 thr7_cntx_1_reg  (   // FS:wmr_protect
 .scan_in(thr7_cntx_1_reg_wmr_scanin),
 .scan_out(thr7_cntx_1_reg_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .clk ( l2clk                ),
 .en  ( 1'b1                 ),  
 .din ( next_thr7_cnxt_1_data[13:0]),
 .dout( thr7_cntx_1[13:0]     ),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// assign thr7_cntx_1_q[13:0] = thr7_cntx_1[13:0] & {13{~gt_t_zero[7]}} ;

ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 thr7_cntx_1_and    (
 .din0({13{ctx_gt_zero_0_[7]}}),
 .din1(thr7_cntx_1[12:0]),
 .dout(thr7_cntx_1_q[12:0])
);


/////////////////////////////////////////////////////////////////////
// Mux out the current context for the thread currently in bf      //
/////////////////////////////////////////////////////////////////////


//buff_macro tst_mux_rep0 (width=1,dbuff=24x) (
// .din ( tcu_muxtest     ),
//.dout( tcu_muxtest_rep0     ));


ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 curr_cntx_0_mux  (
 .din0( thr0_cntx_0_q[12:0]),           // 
 .din1( thr1_cntx_0_q[12:0]),           // 
 .din2( thr2_cntx_0_q[12:0]),           // 
 .din3( thr3_cntx_0_q[12:0]),           // 
 .din4( thr4_cntx_0_q[12:0]),           // 
 .din5( thr5_cntx_0_q[12:0]),           // 
 .din6( thr6_cntx_0_q[12:0]),           // 
 .din7( thr7_cntx_0_q[12:0]),           // 
// .muxtst (tcu_muxtest_rep0),
 .sel0( ftp_itb_fetch_thr_bf[0]),
 .sel1( ftp_itb_fetch_thr_bf[1]),
 .sel2( ftp_itb_fetch_thr_bf[2]),
 .sel3( ftp_itb_fetch_thr_bf[3]),
 .sel4( ftp_itb_fetch_thr_bf[4]),
 .sel5( ftp_itb_fetch_thr_bf[5]),
 .sel6( ftp_itb_fetch_thr_bf[6]),
 .sel7( ftp_itb_fetch_thr_bf[7]),
 .dout( ctx_curr_cntx_0_to_buf[12:0]                               ));

 ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 curr_cntx_0_buff   (
   .din(ctx_curr_cntx_0_to_buf[12:0]),
   .dout(ctx_curr_cntx_0_bf[12:0]));
//assign ctx_curr_cntx_0_bf[13:0] = ctx_curr_cntx_0_to_buf[13:0]  ;

// buff_macro tst_mux_rep1 (width=1,dbuff=24x) (
//  .din ( tcu_muxtest     ),
//  .dout( tcu_muxtest_rep1     ));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 curr_cntx_1_mux  (
 .din0( thr0_cntx_1_q[12:0]),           // 
 .din1( thr1_cntx_1_q[12:0]),           // 
 .din2( thr2_cntx_1_q[12:0]),           // 
 .din3( thr3_cntx_1_q[12:0]),           // 
 .din4( thr4_cntx_1_q[12:0]),           // 
 .din5( thr5_cntx_1_q[12:0]),           // 
 .din6( thr6_cntx_1_q[12:0]),           // 
 .din7( thr7_cntx_1_q[12:0]),           // 
// .muxtst (tcu_muxtest_rep1),
 .sel0( ftp_itb_fetch_thr_bf[0]),
 .sel1( ftp_itb_fetch_thr_bf[1]),
 .sel2( ftp_itb_fetch_thr_bf[2]),
 .sel3( ftp_itb_fetch_thr_bf[3]),
 .sel4( ftp_itb_fetch_thr_bf[4]),
 .sel5( ftp_itb_fetch_thr_bf[5]),
 .sel6( ftp_itb_fetch_thr_bf[6]),
 .sel7( ftp_itb_fetch_thr_bf[7]),
 .dout( ctx_curr_cntx_1_to_buf[12:0]                               ));

ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 curr_cntx_1_buff   (
   .din(ctx_curr_cntx_1_to_buf[12:0]),
   .dout(ctx_curr_cntx_1_bf[12:0]));

// assign ctx_curr_cntx_1_bf[12:0] = ctx_curr_cntx_1_to_buf[12:0]  ;

/////////////////////////////////////////////////////////////////////
// Mux out the context to_write                                    //
/////////////////////////////////////////////////////////////////////
ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 cntx_0_to_write_mux  (
 .din0( thr0_cntx_0[13:0]),           // 
 .din1( thr1_cntx_0[13:0]),           // 
 .din2( thr2_cntx_0[13:0]),           // 
 .din3( thr3_cntx_0[13:0]),           // 
 .din4( thr4_cntx_0[13:0]),           // 
 .din5( thr5_cntx_0[13:0]),           // 
 .din6( thr6_cntx_0[13:0]),           // 
 .din7( thr7_cntx_0[13:0]),           // 
 .sel0( itc_thr_to_write[0]),
 .sel1( itc_thr_to_write[1]),
 .sel2( itc_thr_to_write[2]),
 .sel3( itc_thr_to_write[3]),
 .sel4( itc_thr_to_write[4]),
 .sel5( itc_thr_to_write[5]),
 .sel6( itc_thr_to_write[6]),
 .sel7( itc_thr_to_write[7]),
 .dout( ctx_cntx_0_to_write_to_buf[13:0]                               ));

ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 cntx_0_to_write_buf   (
  .din(ctx_cntx_0_to_write_to_buf[13:0]),
  .dout(ctx_cntx_0_to_write_bf[13:0]));

ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 cntx_1_to_write_mux  (
 .din0( thr0_cntx_1[13:0]),           // 
 .din1( thr1_cntx_1[13:0]),           // 
 .din2( thr2_cntx_1[13:0]),           // 
 .din3( thr3_cntx_1[13:0]),           // 
 .din4( thr4_cntx_1[13:0]),           // 
 .din5( thr5_cntx_1[13:0]),           // 
 .din6( thr6_cntx_1[13:0]),           // 
 .din7( thr7_cntx_1[13:0]),           // 
 .sel0( itc_thr_to_write[0]),
 .sel1( itc_thr_to_write[1]),
 .sel2( itc_thr_to_write[2]),
 .sel3( itc_thr_to_write[3]),
 .sel4( itc_thr_to_write[4]),
 .sel5( itc_thr_to_write[5]),
 .sel6( itc_thr_to_write[6]),
 .sel7( itc_thr_to_write[7]),
 .dout( ctx_cntx_1_to_write_to_buf[13:0]                               ));

ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 cntx_1_to_write_buf   (
  .din(ctx_cntx_1_to_write_to_buf[13:0]),
  .dout(ctx_cntx_1_to_write_bf[13:0]));


// assign se = tcu_scan_en ;
// fixscan start:
assign tlu_tl_gt_0_reg_scanin    = scan_in                  ;
assign lsu_ifu_data_reg_scanin   = tlu_tl_gt_0_reg_scanout  ;
assign scan_out                  = lsu_ifu_data_reg_scanout ;

assign thr0_cntx_0_reg_wmr_scanin = wmr_scan_in              ;
assign thr0_cntx_1_reg_wmr_scanin = thr0_cntx_0_reg_wmr_scanout;
assign thr1_cntx_0_reg_wmr_scanin = thr0_cntx_1_reg_wmr_scanout;
assign thr1_cntx_1_reg_wmr_scanin = thr1_cntx_0_reg_wmr_scanout;
assign thr2_cntx_0_reg_wmr_scanin = thr1_cntx_1_reg_wmr_scanout;
assign thr2_cntx_1_reg_wmr_scanin = thr2_cntx_0_reg_wmr_scanout;
assign thr3_cntx_0_reg_wmr_scanin = thr2_cntx_1_reg_wmr_scanout;
assign thr3_cntx_1_reg_wmr_scanin = thr3_cntx_0_reg_wmr_scanout;
assign thr4_cntx_0_reg_wmr_scanin = thr3_cntx_1_reg_wmr_scanout;
assign thr4_cntx_1_reg_wmr_scanin = thr4_cntx_0_reg_wmr_scanout;
assign thr5_cntx_0_reg_wmr_scanin = thr4_cntx_1_reg_wmr_scanout;
assign thr5_cntx_1_reg_wmr_scanin = thr5_cntx_0_reg_wmr_scanout;
assign thr6_cntx_0_reg_wmr_scanin = thr5_cntx_1_reg_wmr_scanout;
assign thr6_cntx_1_reg_wmr_scanin = thr6_cntx_0_reg_wmr_scanout;
assign thr7_cntx_0_reg_wmr_scanin = thr6_cntx_1_reg_wmr_scanout;
assign thr7_cntx_1_reg_wmr_scanin = thr7_cntx_0_reg_wmr_scanout;
assign wmr_scan_out              = thr7_cntx_1_reg_wmr_scanout;
// fixscan end:
endmodule


//
//   buff macro
//
//


module ifu_ftu_ctx_dp_buff_macro__dbuff_32x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_13 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [11:0] so;

  input [12:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [12:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(13)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[12:0]),
.si({scan_in,so[11:0]}),
.so({so[11:0],scan_out}),
.q(dout[12:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module ifu_ftu_ctx_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_ctx_dp_mux_macro__mux_aope__ports_2__stack_2c__width_1 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [0:0] din0;
  input [0:0] din1;
  input sel0;
  output [0:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(1)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
.dout(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_2__stack_14c__width_14 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [13:0] din0;
  input sel0;
  input [13:0] din1;
  input sel1;
  output [13:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(14)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[13:0]),
  .in1(din1[13:0]),
.dout(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ctx_dp_msff_macro__stack_14c__width_14 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [12:0] so;

  input [13:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [13:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ifu_ftu_ctx_dp_nand_macro__ports_2__stack_14c__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


nand2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ftu_ctx_dp_and_macro__ports_2__stack_14c__width_13 (
  din0, 
  din1, 
  dout);
  input [12:0] din0;
  input [12:0] din1;
  output [12:0] dout;


and2 #(13)  d0_0 (
.in0(din0[12:0]),
.in1(din1[12:0]),
.out(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_13 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [12:0] din0;
  input sel0;
  input [12:0] din1;
  input sel1;
  input [12:0] din2;
  input sel2;
  input [12:0] din3;
  input sel3;
  input [12:0] din4;
  input sel4;
  input [12:0] din5;
  input sel5;
  input [12:0] din6;
  input sel6;
  input [12:0] din7;
  input sel7;
  output [12:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(13)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
  .in2(din2[12:0]),
  .in3(din3[12:0]),
  .in4(din4[12:0]),
  .in5(din5[12:0]),
  .in6(din6[12:0]),
  .in7(din7[12:0]),
.dout(dout[12:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_13 (
  din, 
  dout);
  input [12:0] din;
  output [12:0] dout;


buff #(13)  d0_0 (
.in(din[12:0]),
.out(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_ctx_dp_mux_macro__mux_aonpe__ports_8__stack_14c__width_14 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [13:0] din0;
  input sel0;
  input [13:0] din1;
  input sel1;
  input [13:0] din2;
  input sel2;
  input [13:0] din3;
  input sel3;
  input [13:0] din4;
  input sel4;
  input [13:0] din5;
  input sel5;
  input [13:0] din6;
  input sel6;
  input [13:0] din7;
  input sel7;
  output [13:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(14)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[13:0]),
  .in1(din1[13:0]),
  .in2(din2[13:0]),
  .in3(din3[13:0]),
  .in4(din4[13:0]),
  .in5(din5[13:0]),
  .in6(din6[13:0]),
  .in7(din7[13:0]),
.dout(dout[13:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_ctx_dp_buff_macro__stack_14c__width_14 (
  din, 
  dout);
  input [13:0] din;
  output [13:0] dout;


buff #(14)  d0_0 (
.in(din[13:0]),
.out(dout[13:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_err_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_err_dp (
  ict_itlb_way_0_tag_f, 
  ict_itlb_way_1_tag_f, 
  ict_itlb_way_2_tag_f, 
  ict_itlb_way_3_tag_f, 
  ict_itlb_way_4_tag_f, 
  ict_itlb_way_5_tag_f, 
  ict_itlb_way_6_tag_f, 
  ict_itlb_way_7_tag_f, 
  err_w0_8b_parity_f, 
  err_w1_8b_parity_f, 
  err_w2_8b_parity_f, 
  err_w3_8b_parity_f, 
  err_w4_8b_parity_f, 
  err_w5_8b_parity_f, 
  err_w6_8b_parity_f, 
  err_w7_8b_parity_f) ;
wire err_w0_8b_parity_f_3_xor0;
wire err_w0_8b_parity_f_3_xor1;
wire [3:0] err_w0_8b_parity_f_in;
wire err_w0_8b_parity_f_2_xor0;
wire err_w0_8b_parity_f_2_xor1;
wire err_w0_8b_parity_f_2_xor2;
wire err_w0_8b_parity_f_1_xor0;
wire err_w0_8b_parity_f_1_xor1;
wire err_w0_8b_parity_f_1_xor2;
wire err_w0_8b_parity_f_0_xor0;
wire err_w0_8b_parity_f_0_xor1;
wire err_w0_8b_parity_f_0_xor2;
wire err_w1_8b_parity_f_3_xor0;
wire err_w1_8b_parity_f_3_xor1;
wire [3:0] err_w1_8b_parity_f_in;
wire err_w1_8b_parity_f_2_xor0;
wire err_w1_8b_parity_f_2_xor1;
wire err_w1_8b_parity_f_2_xor2;
wire err_w1_8b_parity_f_1_xor0;
wire err_w1_8b_parity_f_1_xor1;
wire err_w1_8b_parity_f_1_xor2;
wire err_w1_8b_parity_f_0_xor0;
wire err_w1_8b_parity_f_0_xor1;
wire err_w1_8b_parity_f_0_xor2;
wire err_w2_8b_parity_f_3_xor0;
wire err_w2_8b_parity_f_3_xor1;
wire [3:0] err_w2_8b_parity_f_in;
wire err_w2_8b_parity_f_2_xor0;
wire err_w2_8b_parity_f_2_xor1;
wire err_w2_8b_parity_f_2_xor2;
wire err_w2_8b_parity_f_1_xor0;
wire err_w2_8b_parity_f_1_xor1;
wire err_w2_8b_parity_f_1_xor2;
wire err_w2_8b_parity_f_0_xor0;
wire err_w2_8b_parity_f_0_xor1;
wire err_w2_8b_parity_f_0_xor2;
wire err_w3_8b_parity_f_3_xor0;
wire err_w3_8b_parity_f_3_xor1;
wire [3:0] err_w3_8b_parity_f_in;
wire err_w3_8b_parity_f_2_xor0;
wire err_w3_8b_parity_f_2_xor1;
wire err_w3_8b_parity_f_2_xor2;
wire err_w3_8b_parity_f_1_xor0;
wire err_w3_8b_parity_f_1_xor1;
wire err_w3_8b_parity_f_1_xor2;
wire err_w3_8b_parity_f_0_xor0;
wire err_w3_8b_parity_f_0_xor1;
wire err_w3_8b_parity_f_0_xor2;
wire err_w4_8b_parity_f_3_xor0;
wire err_w4_8b_parity_f_3_xor1;
wire [3:0] err_w4_8b_parity_f_in;
wire err_w4_8b_parity_f_2_xor0;
wire err_w4_8b_parity_f_2_xor1;
wire err_w4_8b_parity_f_2_xor2;
wire err_w4_8b_parity_f_1_xor0;
wire err_w4_8b_parity_f_1_xor1;
wire err_w4_8b_parity_f_1_xor2;
wire err_w4_8b_parity_f_0_xor0;
wire err_w4_8b_parity_f_0_xor1;
wire err_w4_8b_parity_f_0_xor2;
wire err_w5_8b_parity_f_3_xor0;
wire err_w5_8b_parity_f_3_xor1;
wire [3:0] err_w5_8b_parity_f_in;
wire err_w5_8b_parity_f_2_xor0;
wire err_w5_8b_parity_f_2_xor1;
wire err_w5_8b_parity_f_2_xor2;
wire err_w5_8b_parity_f_1_xor0;
wire err_w5_8b_parity_f_1_xor1;
wire err_w5_8b_parity_f_1_xor2;
wire err_w5_8b_parity_f_0_xor0;
wire err_w5_8b_parity_f_0_xor1;
wire err_w5_8b_parity_f_0_xor2;
wire err_w6_8b_parity_f_3_xor0;
wire err_w6_8b_parity_f_3_xor1;
wire [3:0] err_w6_8b_parity_f_in;
wire err_w6_8b_parity_f_2_xor0;
wire err_w6_8b_parity_f_2_xor1;
wire err_w6_8b_parity_f_2_xor2;
wire err_w6_8b_parity_f_1_xor0;
wire err_w6_8b_parity_f_1_xor1;
wire err_w6_8b_parity_f_1_xor2;
wire err_w6_8b_parity_f_0_xor0;
wire err_w6_8b_parity_f_0_xor1;
wire err_w6_8b_parity_f_0_xor2;
wire err_w7_8b_parity_f_3_xor0;
wire err_w7_8b_parity_f_3_xor1;
wire [3:0] err_w7_8b_parity_f_in;
wire err_w7_8b_parity_f_2_xor0;
wire err_w7_8b_parity_f_2_xor1;
wire err_w7_8b_parity_f_2_xor2;
wire err_w7_8b_parity_f_1_xor0;
wire err_w7_8b_parity_f_1_xor1;
wire err_w7_8b_parity_f_1_xor2;
wire err_w7_8b_parity_f_0_xor0;
wire err_w7_8b_parity_f_0_xor1;
wire err_w7_8b_parity_f_0_xor2;


input  [29:0] ict_itlb_way_0_tag_f; // 
input  [29:0] ict_itlb_way_1_tag_f; // 
input  [29:0] ict_itlb_way_2_tag_f; // 
input  [29:0] ict_itlb_way_3_tag_f; // 
input  [29:0] ict_itlb_way_4_tag_f; // 
input  [29:0] ict_itlb_way_5_tag_f; // 
input  [29:0] ict_itlb_way_6_tag_f; // 
input  [29:0] ict_itlb_way_7_tag_f; // 


output [3:0] err_w0_8b_parity_f;
output [3:0] err_w1_8b_parity_f;
output [3:0] err_w2_8b_parity_f;
output [3:0] err_w3_8b_parity_f;
output [3:0] err_w4_8b_parity_f;
output [3:0] err_w5_8b_parity_f;
output [3:0] err_w6_8b_parity_f;
output [3:0] err_w7_8b_parity_f;


///////////////////////////////////////////////////////////
// Generate parity in two stages. First stage is done in //
// F cycle when the tags are read.    The second stage   //
// is done in C.                                         //
///////////////////////////////////////////////////////////
///////////////////////////////
// Way 0                     //
///////////////////////////////
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p3_xor0  (
	.din0	(ict_itlb_way_0_tag_f[29]),
	.din1	(ict_itlb_way_0_tag_f[28]),
	.din2	(ict_itlb_way_0_tag_f[27]),
	.dout	(err_w0_8b_parity_f_3_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p3_xor1   (
	.din0	(ict_itlb_way_0_tag_f[26]),
	.din1	(ict_itlb_way_0_tag_f[25]),
	.din2	(ict_itlb_way_0_tag_f[24]),
	.dout	(err_w0_8b_parity_f_3_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w0_8b_p3_xor2   (
	.din0	(err_w0_8b_parity_f_3_xor1),
        .din1   (err_w0_8b_parity_f_3_xor0),
	.dout	(err_w0_8b_parity_f_in[3])
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p2_xor0   (
	.din0	(ict_itlb_way_0_tag_f[23]),
	.din1	(ict_itlb_way_0_tag_f[22]),
	.din2	(ict_itlb_way_0_tag_f[21]),
	.dout	(err_w0_8b_parity_f_2_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p2_xor1   (
	.din0	(ict_itlb_way_0_tag_f[20]),
	.din1	(ict_itlb_way_0_tag_f[19]),
	.din2	(ict_itlb_way_0_tag_f[18]),
	.dout	(err_w0_8b_parity_f_2_xor1)
);

ifu_ftu_err_dp_xor_macro__ports_2__width_1 w0_8b_p2_xor2   (
	.din0	(ict_itlb_way_0_tag_f[17]),
	.din1	(ict_itlb_way_0_tag_f[16]),
	.dout	(err_w0_8b_parity_f_2_xor2)
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p2_xor3   (
	.din0	(err_w0_8b_parity_f_2_xor2),
	.din1	(err_w0_8b_parity_f_2_xor1),
	.din2	(err_w0_8b_parity_f_2_xor0),
	.dout	(err_w0_8b_parity_f_in[2])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p1_xor0   (
	.din0	(ict_itlb_way_0_tag_f[15]),
	.din1	(ict_itlb_way_0_tag_f[14]),
	.din2	(ict_itlb_way_0_tag_f[13]),
	.dout	(err_w0_8b_parity_f_1_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p1_xor1   (
	.din0	(ict_itlb_way_0_tag_f[12]),
	.din1	(ict_itlb_way_0_tag_f[11]),
	.din2	(ict_itlb_way_0_tag_f[10]),
	.dout	(err_w0_8b_parity_f_1_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w0_8b_p1_xor2   (
	.din0	(ict_itlb_way_0_tag_f[9]),
	.din1	(ict_itlb_way_0_tag_f[8]),
	.dout	(err_w0_8b_parity_f_1_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p1_xor3   (
	.din0	(err_w0_8b_parity_f_1_xor2),
	.din1	(err_w0_8b_parity_f_1_xor1),
	.din2	(err_w0_8b_parity_f_1_xor0),
	.dout	(err_w0_8b_parity_f_in[1])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p0_xor0   (
	.din0	(ict_itlb_way_0_tag_f[7]),
	.din1	(ict_itlb_way_0_tag_f[6]),
	.din2	(ict_itlb_way_0_tag_f[5]),
	.dout	(err_w0_8b_parity_f_0_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p0_xor1   (
	.din0	(ict_itlb_way_0_tag_f[4]),
	.din1	(ict_itlb_way_0_tag_f[3]),
	.din2	(ict_itlb_way_0_tag_f[2]),
	.dout	(err_w0_8b_parity_f_0_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w0_8b_p0_xor2   (
	.din0	(ict_itlb_way_0_tag_f[1]),
	.din1	(ict_itlb_way_0_tag_f[0]),
	.dout	(err_w0_8b_parity_f_0_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w0_8b_p0_xor3   (
	.din0	(err_w0_8b_parity_f_0_xor2),
	.din1	(err_w0_8b_parity_f_0_xor1),
	.din2	(err_w0_8b_parity_f_0_xor0),
	.dout	(err_w0_8b_parity_f_in[0])
);

ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 w0_buff   (
        .din   (err_w0_8b_parity_f_in[3:0]),
        .dout  (err_w0_8b_parity_f[3:0])) ;
///////////////////////////////
// Way 1                     //
///////////////////////////////
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p3_xor0  (
	.din0	(ict_itlb_way_1_tag_f[29]),
	.din1	(ict_itlb_way_1_tag_f[28]),
	.din2	(ict_itlb_way_1_tag_f[27]),
	.dout	(err_w1_8b_parity_f_3_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p3_xor1   (
	.din0	(ict_itlb_way_1_tag_f[26]),
	.din1	(ict_itlb_way_1_tag_f[25]),
	.din2	(ict_itlb_way_1_tag_f[24]),
	.dout	(err_w1_8b_parity_f_3_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w1_8b_p3_xor2   (
	.din0	(err_w1_8b_parity_f_3_xor1),
        .din1   (err_w1_8b_parity_f_3_xor0),
	.dout	(err_w1_8b_parity_f_in[3])
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p2_xor0   (
	.din0	(ict_itlb_way_1_tag_f[23]),
	.din1	(ict_itlb_way_1_tag_f[22]),
	.din2	(ict_itlb_way_1_tag_f[21]),
	.dout	(err_w1_8b_parity_f_2_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p2_xor1   (
	.din0	(ict_itlb_way_1_tag_f[20]),
	.din1	(ict_itlb_way_1_tag_f[19]),
	.din2	(ict_itlb_way_1_tag_f[18]),
	.dout	(err_w1_8b_parity_f_2_xor1)
);

ifu_ftu_err_dp_xor_macro__ports_2__width_1 w1_8b_p2_xor2   (
	.din0	(ict_itlb_way_1_tag_f[17]),
	.din1	(ict_itlb_way_1_tag_f[16]),
	.dout	(err_w1_8b_parity_f_2_xor2)
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p2_xor3   (
	.din0	(err_w1_8b_parity_f_2_xor2),
	.din1	(err_w1_8b_parity_f_2_xor1),
	.din2	(err_w1_8b_parity_f_2_xor0),
	.dout	(err_w1_8b_parity_f_in[2])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p1_xor0   (
	.din0	(ict_itlb_way_1_tag_f[15]),
	.din1	(ict_itlb_way_1_tag_f[14]),
	.din2	(ict_itlb_way_1_tag_f[13]),
	.dout	(err_w1_8b_parity_f_1_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p1_xor1   (
	.din0	(ict_itlb_way_1_tag_f[12]),
	.din1	(ict_itlb_way_1_tag_f[11]),
	.din2	(ict_itlb_way_1_tag_f[10]),
	.dout	(err_w1_8b_parity_f_1_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w1_8b_p1_xor2   (
	.din0	(ict_itlb_way_1_tag_f[9]),
	.din1	(ict_itlb_way_1_tag_f[8]),
	.dout	(err_w1_8b_parity_f_1_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p1_xor3   (
	.din0	(err_w1_8b_parity_f_1_xor2),
	.din1	(err_w1_8b_parity_f_1_xor1),
	.din2	(err_w1_8b_parity_f_1_xor0),
	.dout	(err_w1_8b_parity_f_in[1])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p0_xor0   (
	.din0	(ict_itlb_way_1_tag_f[7]),
	.din1	(ict_itlb_way_1_tag_f[6]),
	.din2	(ict_itlb_way_1_tag_f[5]),
	.dout	(err_w1_8b_parity_f_0_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p0_xor1   (
	.din0	(ict_itlb_way_1_tag_f[4]),
	.din1	(ict_itlb_way_1_tag_f[3]),
	.din2	(ict_itlb_way_1_tag_f[2]),
	.dout	(err_w1_8b_parity_f_0_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w1_8b_p0_xor2   (
	.din0	(ict_itlb_way_1_tag_f[1]),
	.din1	(ict_itlb_way_1_tag_f[0]),
	.dout	(err_w1_8b_parity_f_0_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w1_8b_p0_xor3   (
	.din0	(err_w1_8b_parity_f_0_xor2),
	.din1	(err_w1_8b_parity_f_0_xor1),
	.din2	(err_w1_8b_parity_f_0_xor0),
	.dout	(err_w1_8b_parity_f_in[0])
);


ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 w1_buff   (
        .din   (err_w1_8b_parity_f_in[3:0]),
        .dout  (err_w1_8b_parity_f[3:0])) ;
///////////////////////////////
// Way 2                     //
///////////////////////////////
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p3_xor0  (
	.din0	(ict_itlb_way_2_tag_f[29]),
	.din1	(ict_itlb_way_2_tag_f[28]),
	.din2	(ict_itlb_way_2_tag_f[27]),
	.dout	(err_w2_8b_parity_f_3_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p3_xor1   (
	.din0	(ict_itlb_way_2_tag_f[26]),
	.din1	(ict_itlb_way_2_tag_f[25]),
	.din2	(ict_itlb_way_2_tag_f[24]),
	.dout	(err_w2_8b_parity_f_3_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w2_8b_p3_xor2   (
	.din0	(err_w2_8b_parity_f_3_xor1),
        .din1   (err_w2_8b_parity_f_3_xor0),
	.dout	(err_w2_8b_parity_f_in[3])
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p2_xor0   (
	.din0	(ict_itlb_way_2_tag_f[23]),
	.din1	(ict_itlb_way_2_tag_f[22]),
	.din2	(ict_itlb_way_2_tag_f[21]),
	.dout	(err_w2_8b_parity_f_2_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p2_xor1   (
	.din0	(ict_itlb_way_2_tag_f[20]),
	.din1	(ict_itlb_way_2_tag_f[19]),
	.din2	(ict_itlb_way_2_tag_f[18]),
	.dout	(err_w2_8b_parity_f_2_xor1)
);

ifu_ftu_err_dp_xor_macro__ports_2__width_1 w2_8b_p2_xor2   (
	.din0	(ict_itlb_way_2_tag_f[17]),
	.din1	(ict_itlb_way_2_tag_f[16]),
	.dout	(err_w2_8b_parity_f_2_xor2)
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p2_xor3   (
	.din0	(err_w2_8b_parity_f_2_xor2),
	.din1	(err_w2_8b_parity_f_2_xor1),
	.din2	(err_w2_8b_parity_f_2_xor0),
	.dout	(err_w2_8b_parity_f_in[2])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p1_xor0   (
	.din0	(ict_itlb_way_2_tag_f[15]),
	.din1	(ict_itlb_way_2_tag_f[14]),
	.din2	(ict_itlb_way_2_tag_f[13]),
	.dout	(err_w2_8b_parity_f_1_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p1_xor1   (
	.din0	(ict_itlb_way_2_tag_f[12]),
	.din1	(ict_itlb_way_2_tag_f[11]),
	.din2	(ict_itlb_way_2_tag_f[10]),
	.dout	(err_w2_8b_parity_f_1_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w2_8b_p1_xor2   (
	.din0	(ict_itlb_way_2_tag_f[9]),
	.din1	(ict_itlb_way_2_tag_f[8]),
	.dout	(err_w2_8b_parity_f_1_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p1_xor3   (
	.din0	(err_w2_8b_parity_f_1_xor2),
	.din1	(err_w2_8b_parity_f_1_xor1),
	.din2	(err_w2_8b_parity_f_1_xor0),
	.dout	(err_w2_8b_parity_f_in[1])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p0_xor0   (
	.din0	(ict_itlb_way_2_tag_f[7]),
	.din1	(ict_itlb_way_2_tag_f[6]),
	.din2	(ict_itlb_way_2_tag_f[5]),
	.dout	(err_w2_8b_parity_f_0_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p0_xor1   (
	.din0	(ict_itlb_way_2_tag_f[4]),
	.din1	(ict_itlb_way_2_tag_f[3]),
	.din2	(ict_itlb_way_2_tag_f[2]),
	.dout	(err_w2_8b_parity_f_0_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w2_8b_p0_xor2   (
	.din0	(ict_itlb_way_2_tag_f[1]),
	.din1	(ict_itlb_way_2_tag_f[0]),
	.dout	(err_w2_8b_parity_f_0_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w2_8b_p0_xor3   (
	.din0	(err_w2_8b_parity_f_0_xor2),
	.din1	(err_w2_8b_parity_f_0_xor1),
	.din2	(err_w2_8b_parity_f_0_xor0),
	.dout	(err_w2_8b_parity_f_in[0])
);


ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 w2_buff   (
        .din   (err_w2_8b_parity_f_in[3:0]),
        .dout  (err_w2_8b_parity_f[3:0])) ;

///////////////////////////////
// Way 3                     //
///////////////////////////////
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p3_xor0  (
	.din0	(ict_itlb_way_3_tag_f[29]),
	.din1	(ict_itlb_way_3_tag_f[28]),
	.din2	(ict_itlb_way_3_tag_f[27]),
	.dout	(err_w3_8b_parity_f_3_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p3_xor1   (
	.din0	(ict_itlb_way_3_tag_f[26]),
	.din1	(ict_itlb_way_3_tag_f[25]),
	.din2	(ict_itlb_way_3_tag_f[24]),
	.dout	(err_w3_8b_parity_f_3_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w3_8b_p3_xor2   (
	.din0	(err_w3_8b_parity_f_3_xor1),
        .din1   (err_w3_8b_parity_f_3_xor0),
	.dout	(err_w3_8b_parity_f_in[3])
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p2_xor0   (
	.din0	(ict_itlb_way_3_tag_f[23]),
	.din1	(ict_itlb_way_3_tag_f[22]),
	.din2	(ict_itlb_way_3_tag_f[21]),
	.dout	(err_w3_8b_parity_f_2_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p2_xor1   (
	.din0	(ict_itlb_way_3_tag_f[20]),
	.din1	(ict_itlb_way_3_tag_f[19]),
	.din2	(ict_itlb_way_3_tag_f[18]),
	.dout	(err_w3_8b_parity_f_2_xor1)
);

ifu_ftu_err_dp_xor_macro__ports_2__width_1 w3_8b_p2_xor2   (
	.din0	(ict_itlb_way_3_tag_f[17]),
	.din1	(ict_itlb_way_3_tag_f[16]),
	.dout	(err_w3_8b_parity_f_2_xor2)
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p2_xor3   (
	.din0	(err_w3_8b_parity_f_2_xor2),
	.din1	(err_w3_8b_parity_f_2_xor1),
	.din2	(err_w3_8b_parity_f_2_xor0),
	.dout	(err_w3_8b_parity_f_in[2])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p1_xor0   (
	.din0	(ict_itlb_way_3_tag_f[15]),
	.din1	(ict_itlb_way_3_tag_f[14]),
	.din2	(ict_itlb_way_3_tag_f[13]),
	.dout	(err_w3_8b_parity_f_1_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p1_xor1   (
	.din0	(ict_itlb_way_3_tag_f[12]),
	.din1	(ict_itlb_way_3_tag_f[11]),
	.din2	(ict_itlb_way_3_tag_f[10]),
	.dout	(err_w3_8b_parity_f_1_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w3_8b_p1_xor2   (
	.din0	(ict_itlb_way_3_tag_f[9]),
	.din1	(ict_itlb_way_3_tag_f[8]),
	.dout	(err_w3_8b_parity_f_1_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p1_xor3   (
	.din0	(err_w3_8b_parity_f_1_xor2),
	.din1	(err_w3_8b_parity_f_1_xor1),
	.din2	(err_w3_8b_parity_f_1_xor0),
	.dout	(err_w3_8b_parity_f_in[1])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p0_xor0   (
	.din0	(ict_itlb_way_3_tag_f[7]),
	.din1	(ict_itlb_way_3_tag_f[6]),
	.din2	(ict_itlb_way_3_tag_f[5]),
	.dout	(err_w3_8b_parity_f_0_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p0_xor1   (
	.din0	(ict_itlb_way_3_tag_f[4]),
	.din1	(ict_itlb_way_3_tag_f[3]),
	.din2	(ict_itlb_way_3_tag_f[2]),
	.dout	(err_w3_8b_parity_f_0_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w3_8b_p0_xor2   (
	.din0	(ict_itlb_way_3_tag_f[1]),
	.din1	(ict_itlb_way_3_tag_f[0]),
	.dout	(err_w3_8b_parity_f_0_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w3_8b_p0_xor3   (
	.din0	(err_w3_8b_parity_f_0_xor2),
	.din1	(err_w3_8b_parity_f_0_xor1),
	.din2	(err_w3_8b_parity_f_0_xor0),
	.dout	(err_w3_8b_parity_f_in[0])
);


ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 w3_buff   (
        .din   (err_w3_8b_parity_f_in[3:0]),
        .dout  (err_w3_8b_parity_f[3:0])) ;

///////////////////////////////
// Way 4                     //
///////////////////////////////
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p3_xor0  (
	.din0	(ict_itlb_way_4_tag_f[29]),
	.din1	(ict_itlb_way_4_tag_f[28]),
	.din2	(ict_itlb_way_4_tag_f[27]),
	.dout	(err_w4_8b_parity_f_3_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p3_xor1   (
	.din0	(ict_itlb_way_4_tag_f[26]),
	.din1	(ict_itlb_way_4_tag_f[25]),
	.din2	(ict_itlb_way_4_tag_f[24]),
	.dout	(err_w4_8b_parity_f_3_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w4_8b_p3_xor2   (
	.din0	(err_w4_8b_parity_f_3_xor1),
        .din1   (err_w4_8b_parity_f_3_xor0),
	.dout	(err_w4_8b_parity_f_in[3])
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p2_xor0   (
	.din0	(ict_itlb_way_4_tag_f[23]),
	.din1	(ict_itlb_way_4_tag_f[22]),
	.din2	(ict_itlb_way_4_tag_f[21]),
	.dout	(err_w4_8b_parity_f_2_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p2_xor1   (
	.din0	(ict_itlb_way_4_tag_f[20]),
	.din1	(ict_itlb_way_4_tag_f[19]),
	.din2	(ict_itlb_way_4_tag_f[18]),
	.dout	(err_w4_8b_parity_f_2_xor1)
);

ifu_ftu_err_dp_xor_macro__ports_2__width_1 w4_8b_p2_xor2   (
	.din0	(ict_itlb_way_4_tag_f[17]),
	.din1	(ict_itlb_way_4_tag_f[16]),
	.dout	(err_w4_8b_parity_f_2_xor2)
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p2_xor3   (
	.din0	(err_w4_8b_parity_f_2_xor2),
	.din1	(err_w4_8b_parity_f_2_xor1),
	.din2	(err_w4_8b_parity_f_2_xor0),
	.dout	(err_w4_8b_parity_f_in[2])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p1_xor0   (
	.din0	(ict_itlb_way_4_tag_f[15]),
	.din1	(ict_itlb_way_4_tag_f[14]),
	.din2	(ict_itlb_way_4_tag_f[13]),
	.dout	(err_w4_8b_parity_f_1_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p1_xor1   (
	.din0	(ict_itlb_way_4_tag_f[12]),
	.din1	(ict_itlb_way_4_tag_f[11]),
	.din2	(ict_itlb_way_4_tag_f[10]),
	.dout	(err_w4_8b_parity_f_1_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w4_8b_p1_xor2   (
	.din0	(ict_itlb_way_4_tag_f[9]),
	.din1	(ict_itlb_way_4_tag_f[8]),
	.dout	(err_w4_8b_parity_f_1_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p1_xor3   (
	.din0	(err_w4_8b_parity_f_1_xor2),
	.din1	(err_w4_8b_parity_f_1_xor1),
	.din2	(err_w4_8b_parity_f_1_xor0),
	.dout	(err_w4_8b_parity_f_in[1])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p0_xor0   (
	.din0	(ict_itlb_way_4_tag_f[7]),
	.din1	(ict_itlb_way_4_tag_f[6]),
	.din2	(ict_itlb_way_4_tag_f[5]),
	.dout	(err_w4_8b_parity_f_0_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p0_xor1   (
	.din0	(ict_itlb_way_4_tag_f[4]),
	.din1	(ict_itlb_way_4_tag_f[3]),
	.din2	(ict_itlb_way_4_tag_f[2]),
	.dout	(err_w4_8b_parity_f_0_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w4_8b_p0_xor2   (
	.din0	(ict_itlb_way_4_tag_f[1]),
	.din1	(ict_itlb_way_4_tag_f[0]),
	.dout	(err_w4_8b_parity_f_0_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w4_8b_p0_xor3   (
	.din0	(err_w4_8b_parity_f_0_xor2),
	.din1	(err_w4_8b_parity_f_0_xor1),
	.din2	(err_w4_8b_parity_f_0_xor0),
	.dout	(err_w4_8b_parity_f_in[0])
);

ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 w4_buff   (
        .din   (err_w4_8b_parity_f_in[3:0]),
        .dout  (err_w4_8b_parity_f[3:0])) ;


///////////////////////////////
// Way 5                     //
///////////////////////////////
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p3_xor0  (
	.din0	(ict_itlb_way_5_tag_f[29]),
	.din1	(ict_itlb_way_5_tag_f[28]),
	.din2	(ict_itlb_way_5_tag_f[27]),
	.dout	(err_w5_8b_parity_f_3_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p3_xor1   (
	.din0	(ict_itlb_way_5_tag_f[26]),
	.din1	(ict_itlb_way_5_tag_f[25]),
	.din2	(ict_itlb_way_5_tag_f[24]),
	.dout	(err_w5_8b_parity_f_3_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w5_8b_p3_xor2   (
	.din0	(err_w5_8b_parity_f_3_xor1),
        .din1   (err_w5_8b_parity_f_3_xor0),
	.dout	(err_w5_8b_parity_f_in[3])
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p2_xor0   (
	.din0	(ict_itlb_way_5_tag_f[23]),
	.din1	(ict_itlb_way_5_tag_f[22]),
	.din2	(ict_itlb_way_5_tag_f[21]),
	.dout	(err_w5_8b_parity_f_2_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p2_xor1   (
	.din0	(ict_itlb_way_5_tag_f[20]),
	.din1	(ict_itlb_way_5_tag_f[19]),
	.din2	(ict_itlb_way_5_tag_f[18]),
	.dout	(err_w5_8b_parity_f_2_xor1)
);

ifu_ftu_err_dp_xor_macro__ports_2__width_1 w5_8b_p2_xor2   (
	.din0	(ict_itlb_way_5_tag_f[17]),
	.din1	(ict_itlb_way_5_tag_f[16]),
	.dout	(err_w5_8b_parity_f_2_xor2)
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p2_xor3   (
	.din0	(err_w5_8b_parity_f_2_xor2),
	.din1	(err_w5_8b_parity_f_2_xor1),
	.din2	(err_w5_8b_parity_f_2_xor0),
	.dout	(err_w5_8b_parity_f_in[2])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p1_xor0   (
	.din0	(ict_itlb_way_5_tag_f[15]),
	.din1	(ict_itlb_way_5_tag_f[14]),
	.din2	(ict_itlb_way_5_tag_f[13]),
	.dout	(err_w5_8b_parity_f_1_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p1_xor1   (
	.din0	(ict_itlb_way_5_tag_f[12]),
	.din1	(ict_itlb_way_5_tag_f[11]),
	.din2	(ict_itlb_way_5_tag_f[10]),
	.dout	(err_w5_8b_parity_f_1_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w5_8b_p1_xor2   (
	.din0	(ict_itlb_way_5_tag_f[9]),
	.din1	(ict_itlb_way_5_tag_f[8]),
	.dout	(err_w5_8b_parity_f_1_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p1_xor3   (
	.din0	(err_w5_8b_parity_f_1_xor2),
	.din1	(err_w5_8b_parity_f_1_xor1),
	.din2	(err_w5_8b_parity_f_1_xor0),
	.dout	(err_w5_8b_parity_f_in[1])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p0_xor0   (
	.din0	(ict_itlb_way_5_tag_f[7]),
	.din1	(ict_itlb_way_5_tag_f[6]),
	.din2	(ict_itlb_way_5_tag_f[5]),
	.dout	(err_w5_8b_parity_f_0_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p0_xor1   (
	.din0	(ict_itlb_way_5_tag_f[4]),
	.din1	(ict_itlb_way_5_tag_f[3]),
	.din2	(ict_itlb_way_5_tag_f[2]),
	.dout	(err_w5_8b_parity_f_0_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w5_8b_p0_xor2   (
	.din0	(ict_itlb_way_5_tag_f[1]),
	.din1	(ict_itlb_way_5_tag_f[0]),
	.dout	(err_w5_8b_parity_f_0_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w5_8b_p0_xor3   (
	.din0	(err_w5_8b_parity_f_0_xor2),
	.din1	(err_w5_8b_parity_f_0_xor1),
	.din2	(err_w5_8b_parity_f_0_xor0),
	.dout	(err_w5_8b_parity_f_in[0])
);

ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 w5_buff   (
        .din   (err_w5_8b_parity_f_in[3:0]),
        .dout  (err_w5_8b_parity_f[3:0])) ;


///////////////////////////////
// Way 6                     //
///////////////////////////////
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p3_xor0  (
	.din0	(ict_itlb_way_6_tag_f[29]),
	.din1	(ict_itlb_way_6_tag_f[28]),
	.din2	(ict_itlb_way_6_tag_f[27]),
	.dout	(err_w6_8b_parity_f_3_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p3_xor1   (
	.din0	(ict_itlb_way_6_tag_f[26]),
	.din1	(ict_itlb_way_6_tag_f[25]),
	.din2	(ict_itlb_way_6_tag_f[24]),
	.dout	(err_w6_8b_parity_f_3_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w6_8b_p3_xor2   (
	.din0	(err_w6_8b_parity_f_3_xor1),
        .din1   (err_w6_8b_parity_f_3_xor0),
	.dout	(err_w6_8b_parity_f_in[3])
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p2_xor0   (
	.din0	(ict_itlb_way_6_tag_f[23]),
	.din1	(ict_itlb_way_6_tag_f[22]),
	.din2	(ict_itlb_way_6_tag_f[21]),
	.dout	(err_w6_8b_parity_f_2_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p2_xor1   (
	.din0	(ict_itlb_way_6_tag_f[20]),
	.din1	(ict_itlb_way_6_tag_f[19]),
	.din2	(ict_itlb_way_6_tag_f[18]),
	.dout	(err_w6_8b_parity_f_2_xor1)
);

ifu_ftu_err_dp_xor_macro__ports_2__width_1 w6_8b_p2_xor2   (
	.din0	(ict_itlb_way_6_tag_f[17]),
	.din1	(ict_itlb_way_6_tag_f[16]),
	.dout	(err_w6_8b_parity_f_2_xor2)
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p2_xor3   (
	.din0	(err_w6_8b_parity_f_2_xor2),
	.din1	(err_w6_8b_parity_f_2_xor1),
	.din2	(err_w6_8b_parity_f_2_xor0),
	.dout	(err_w6_8b_parity_f_in[2])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p1_xor0   (
	.din0	(ict_itlb_way_6_tag_f[15]),
	.din1	(ict_itlb_way_6_tag_f[14]),
	.din2	(ict_itlb_way_6_tag_f[13]),
	.dout	(err_w6_8b_parity_f_1_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p1_xor1   (
	.din0	(ict_itlb_way_6_tag_f[12]),
	.din1	(ict_itlb_way_6_tag_f[11]),
	.din2	(ict_itlb_way_6_tag_f[10]),
	.dout	(err_w6_8b_parity_f_1_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w6_8b_p1_xor2   (
	.din0	(ict_itlb_way_6_tag_f[9]),
	.din1	(ict_itlb_way_6_tag_f[8]),
	.dout	(err_w6_8b_parity_f_1_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p1_xor3   (
	.din0	(err_w6_8b_parity_f_1_xor2),
	.din1	(err_w6_8b_parity_f_1_xor1),
	.din2	(err_w6_8b_parity_f_1_xor0),
	.dout	(err_w6_8b_parity_f_in[1])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p0_xor0   (
	.din0	(ict_itlb_way_6_tag_f[7]),
	.din1	(ict_itlb_way_6_tag_f[6]),
	.din2	(ict_itlb_way_6_tag_f[5]),
	.dout	(err_w6_8b_parity_f_0_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p0_xor1   (
	.din0	(ict_itlb_way_6_tag_f[4]),
	.din1	(ict_itlb_way_6_tag_f[3]),
	.din2	(ict_itlb_way_6_tag_f[2]),
	.dout	(err_w6_8b_parity_f_0_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w6_8b_p0_xor2   (
	.din0	(ict_itlb_way_6_tag_f[1]),
	.din1	(ict_itlb_way_6_tag_f[0]),
	.dout	(err_w6_8b_parity_f_0_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w6_8b_p0_xor3   (
	.din0	(err_w6_8b_parity_f_0_xor2),
	.din1	(err_w6_8b_parity_f_0_xor1),
	.din2	(err_w6_8b_parity_f_0_xor0),
	.dout	(err_w6_8b_parity_f_in[0])
);

ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 w6_buff   (
        .din   (err_w6_8b_parity_f_in[3:0]),
        .dout  (err_w6_8b_parity_f[3:0])) ;

///////////////////////////////
// Way 7                     //
///////////////////////////////
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p3_xor0  (
	.din0	(ict_itlb_way_7_tag_f[29]),
	.din1	(ict_itlb_way_7_tag_f[28]),
	.din2	(ict_itlb_way_7_tag_f[27]),
	.dout	(err_w7_8b_parity_f_3_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p3_xor1   (
	.din0	(ict_itlb_way_7_tag_f[26]),
	.din1	(ict_itlb_way_7_tag_f[25]),
	.din2	(ict_itlb_way_7_tag_f[24]),
	.dout	(err_w7_8b_parity_f_3_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w7_8b_p3_xor2   (
	.din0	(err_w7_8b_parity_f_3_xor1),
        .din1   (err_w7_8b_parity_f_3_xor0),
	.dout	(err_w7_8b_parity_f_in[3])
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p2_xor0   (
	.din0	(ict_itlb_way_7_tag_f[23]),
	.din1	(ict_itlb_way_7_tag_f[22]),
	.din2	(ict_itlb_way_7_tag_f[21]),
	.dout	(err_w7_8b_parity_f_2_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p2_xor1   (
	.din0	(ict_itlb_way_7_tag_f[20]),
	.din1	(ict_itlb_way_7_tag_f[19]),
	.din2	(ict_itlb_way_7_tag_f[18]),
	.dout	(err_w7_8b_parity_f_2_xor1)
);

ifu_ftu_err_dp_xor_macro__ports_2__width_1 w7_8b_p2_xor2   (
	.din0	(ict_itlb_way_7_tag_f[17]),
	.din1	(ict_itlb_way_7_tag_f[16]),
	.dout	(err_w7_8b_parity_f_2_xor2)
);

ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p2_xor3   (
	.din0	(err_w7_8b_parity_f_2_xor2),
	.din1	(err_w7_8b_parity_f_2_xor1),
	.din2	(err_w7_8b_parity_f_2_xor0),
	.dout	(err_w7_8b_parity_f_in[2])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p1_xor0   (
	.din0	(ict_itlb_way_7_tag_f[15]),
	.din1	(ict_itlb_way_7_tag_f[14]),
	.din2	(ict_itlb_way_7_tag_f[13]),
	.dout	(err_w7_8b_parity_f_1_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p1_xor1   (
	.din0	(ict_itlb_way_7_tag_f[12]),
	.din1	(ict_itlb_way_7_tag_f[11]),
	.din2	(ict_itlb_way_7_tag_f[10]),
	.dout	(err_w7_8b_parity_f_1_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w7_8b_p1_xor2   (
	.din0	(ict_itlb_way_7_tag_f[9]),
	.din1	(ict_itlb_way_7_tag_f[8]),
	.dout	(err_w7_8b_parity_f_1_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p1_xor3   (
	.din0	(err_w7_8b_parity_f_1_xor2),
	.din1	(err_w7_8b_parity_f_1_xor1),
	.din2	(err_w7_8b_parity_f_1_xor0),
	.dout	(err_w7_8b_parity_f_in[1])
);


ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p0_xor0   (
	.din0	(ict_itlb_way_7_tag_f[7]),
	.din1	(ict_itlb_way_7_tag_f[6]),
	.din2	(ict_itlb_way_7_tag_f[5]),
	.dout	(err_w7_8b_parity_f_0_xor0)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p0_xor1   (
	.din0	(ict_itlb_way_7_tag_f[4]),
	.din1	(ict_itlb_way_7_tag_f[3]),
	.din2	(ict_itlb_way_7_tag_f[2]),
	.dout	(err_w7_8b_parity_f_0_xor1)
);
ifu_ftu_err_dp_xor_macro__ports_2__width_1 w7_8b_p0_xor2   (
	.din0	(ict_itlb_way_7_tag_f[1]),
	.din1	(ict_itlb_way_7_tag_f[0]),
	.dout	(err_w7_8b_parity_f_0_xor2)
);
ifu_ftu_err_dp_xor_macro__ports_3__width_1 w7_8b_p0_xor3   (
	.din0	(err_w7_8b_parity_f_0_xor2),
	.din1	(err_w7_8b_parity_f_0_xor1),
	.din2	(err_w7_8b_parity_f_0_xor0),
	.dout	(err_w7_8b_parity_f_in[0])
);

ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 w7_buff   (
        .din   (err_w7_8b_parity_f_in[3:0]),
        .dout  (err_w7_8b_parity_f[3:0])) ;


endmodule


//
//   xor macro for ports = 2,3
//
//


module ifu_ftu_err_dp_xor_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


xor3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module ifu_ftu_err_dp_xor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_err_dp_buff_macro__dbuff_56x__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_ftp_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_ftp_ctl (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  spc_core_running_status, 
  tlu_pstate_am, 
  tlu_flush_ifu, 
  tlu_itlb_bypass, 
  tlu_trap_0_tid, 
  tlu_trap_1_tid, 
  tlu_trap_pc_0_valid, 
  tlu_trap_pc_1_valid, 
  dec_br_taken_e, 
  dec_valid_e, 
  dec_tid0_d, 
  dec_tid1_d, 
  itc_demap_next, 
  mbi_run, 
  mbi_itb_cam_en_pre, 
  mbi_cmpsel, 
  mbi_ict_read_en, 
  mbi_ict_write_en, 
  mbi_icd_read_en, 
  mbi_icd_write_en, 
  mbi_icv_read_en, 
  mbi_icv_write_en, 
  cmu_thr0_data_ready, 
  cmu_thr1_data_ready, 
  cmu_thr2_data_ready, 
  cmu_thr3_data_ready, 
  cmu_thr4_data_ready, 
  cmu_thr5_data_ready, 
  cmu_thr6_data_ready, 
  cmu_thr7_data_ready, 
  tsm_thr0_ignore_by_pass, 
  tsm_thr1_ignore_by_pass, 
  tsm_thr2_ignore_by_pass, 
  tsm_thr3_ignore_by_pass, 
  tsm_thr4_ignore_by_pass, 
  tsm_thr5_ignore_by_pass, 
  tsm_thr6_ignore_by_pass, 
  tsm_thr7_ignore_by_pass, 
  dec_load_flush_w, 
  tsm_thr0_ready_hp_bf_in, 
  tsm_thr1_ready_hp_bf_in, 
  tsm_thr2_ready_hp_bf_in, 
  tsm_thr3_ready_hp_bf_in, 
  tsm_thr4_ready_hp_bf_in, 
  tsm_thr5_ready_hp_bf_in, 
  tsm_thr6_ready_hp_bf_in, 
  tsm_thr7_ready_hp_bf_in, 
  tsm_thr0_fill_rdy0, 
  tsm_thr1_fill_rdy0, 
  tsm_thr2_fill_rdy0, 
  tsm_thr3_fill_rdy0, 
  tsm_thr4_fill_rdy0, 
  tsm_thr5_fill_rdy0, 
  tsm_thr6_fill_rdy0, 
  tsm_thr7_fill_rdy0, 
  cmu_icache_invalidate, 
  cmu_any_un_cacheable, 
  cmu_any_data_ready, 
  ibu_empty, 
  ibu_room_4ormore, 
  agc_by_pass_update_lru_bf, 
  agc_invalidation_req_ff, 
  agc_kill_fetch_cv_c, 
  agc_thr0_micro_flush_unq_c, 
  agc_thr1_micro_flush_unq_c, 
  agc_thr2_micro_flush_unq_c, 
  agc_thr3_micro_flush_unq_c, 
  agc_thr4_micro_flush_unq_c, 
  agc_thr5_micro_flush_unq_c, 
  agc_thr6_micro_flush_unq_c, 
  agc_thr7_micro_flush_unq_c, 
  agc_thr0_sf_valid_f, 
  agc_thr1_sf_valid_f, 
  agc_thr2_sf_valid_f, 
  agc_thr3_sf_valid_f, 
  agc_thr4_sf_valid_f, 
  agc_thr5_sf_valid_f, 
  agc_thr6_sf_valid_f, 
  agc_thr7_sf_valid_f, 
  asi_sel_cntx_0, 
  asi_ic_wr_req, 
  asi_ic_rd_req, 
  asi_tg_wr_req, 
  asi_tg_rd_req, 
  asi_itd_rd_req, 
  asi_itt_rd_req, 
  asi_ith_det_req, 
  asi_tid, 
  agd_address0_m, 
  agd_address1_m, 
  agd_thr0_pc_4_2_f, 
  agd_thr1_pc_4_2_f, 
  agd_thr2_pc_4_2_f, 
  agd_thr3_pc_4_2_f, 
  agd_thr4_pc_4_2_f, 
  agd_thr5_pc_4_2_f, 
  agd_thr6_pc_4_2_f, 
  agd_thr7_pc_4_2_f, 
  ifu_agd_pc_f, 
  asi_addr_bf, 
  lsu_ifu_ftu_pmen, 
  lsu_ic_pmen, 
  lsu_ifu_wr_pid, 
  lsu_ifu_tid_w, 
  lsu_ifu_pid_data, 
  ftp_asi_rd_done, 
  ftp_asi_wr_done, 
  ftp_reset_fill_wait, 
  ftp_ic_rd_req_bf, 
  ftp_ic_wr_ps_en_bf, 
  ftp_ic_wr_req_bf, 
  ftp_tg_rd_req_bf, 
  ftp_tg_wr_req_bf, 
  ftp_iv_rd_req_bf, 
  ftp_itt_rd_req_bf, 
  ftp_itd_rd_req_bf, 
  ftp_itlb_cam_vld_bf, 
  ftp_itlb_cam_vld_f, 
  ftp_ith_det_req_bf, 
  ftp_itlb_probe_req_l, 
  ftp_sel_icv_mbist_addr, 
  ftp_sel_mbist_itb_cycle0, 
  ftp_sel_mbist_itb_cycle1, 
  ftp_sel_mbist_itb_cycle2, 
  ftp_sel_mbist_itb_cycle3, 
  ftp_sel_itlb_tag_cntx0_c, 
  ftp_sel_itlb_tag_cntx1_c, 
  ftp_sel_itlb_data_c, 
  ftp_sel_itlb_pa_c, 
  ftp_asi_mbist_access_bf, 
  ftp_asi_it_rd_done, 
  ftp_asi_ic_rd_done, 
  ftp_asi_ic_wr_done, 
  ftp_asi_tg_rd_done, 
  ftp_asi_tg_wr_done, 
  ftp_asi_tg_wr_req_hold, 
  ftp_thr0_room_is_less_t_3, 
  ftp_thr1_room_is_less_t_3, 
  ftp_thr2_room_is_less_t_3, 
  ftp_thr3_room_is_less_t_3, 
  ftp_thr4_room_is_less_t_3, 
  ftp_thr5_room_is_less_t_3, 
  ftp_thr6_room_is_less_t_3, 
  ftp_thr7_room_is_less_t_3, 
  ftp_thr0_go_to_sf_wait, 
  ftp_thr1_go_to_sf_wait, 
  ftp_thr2_go_to_sf_wait, 
  ftp_thr3_go_to_sf_wait, 
  ftp_thr4_go_to_sf_wait, 
  ftp_thr5_go_to_sf_wait, 
  ftp_thr6_go_to_sf_wait, 
  ftp_thr7_go_to_sf_wait, 
  ftp_thr0_trprdpc_sel_bf, 
  ftp_thr1_trprdpc_sel_bf, 
  ftp_thr2_trprdpc_sel_bf, 
  ftp_thr3_trprdpc_sel_bf, 
  ftp_thr4_trprdpc_sel_bf, 
  ftp_thr5_trprdpc_sel_bf, 
  ftp_thr6_trprdpc_sel_bf, 
  ftp_thr7_trprdpc_sel_bf, 
  ftp_thr0_sel_br_bf, 
  ftp_thr1_sel_br_bf, 
  ftp_thr2_sel_br_bf, 
  ftp_thr3_sel_br_bf, 
  ftp_thr4_sel_br_bf, 
  ftp_thr5_sel_br_bf, 
  ftp_thr6_sel_br_bf, 
  ftp_thr7_sel_br_bf, 
  ftp_icd_quad_0_en_bf, 
  ftp_icd_quad_1_en_bf, 
  ftp_icd_quad_2_en_bf, 
  ftp_icd_quad_3_en_bf, 
  ftp_tg_clk_en, 
  ftp_pc_sel_am, 
  ftp_pc_sel_tag_part1, 
  ftp_pc_sel_tag_part2, 
  ftp_pc_sel_tag_pc_bot, 
  ftp_pc_sel_tag_pc_top, 
  ftp_icaddr_sel_first_mux, 
  ftp_itb_fetch_thr_bf, 
  ftp_new_thr_sel_bf, 
  ftu_curr_fetch_thr_f, 
  ftp_curr_fetch_thr_f, 
  ftp_fetch_thr_q_f, 
  ftp_tid0_e, 
  ftp_tid1_e, 
  ftp_fetch_v_f, 
  ftp_fill_req_q_bf, 
  ftp_mbi_icd_read_en_bf, 
  ftp_mbi_ict_read_en_bf, 
  ftp_ict_data_sel_bf, 
  ftp_any_thr_clken, 
  scan_out, 
  ftp_curr_pid_bf, 
  ftp_thr7_pid_data, 
  ftp_thr6_pid_data, 
  ftp_thr5_pid_data, 
  ftp_thr4_pid_data, 
  ftp_thr3_pid_data, 
  ftp_thr2_pid_data, 
  ftp_thr1_pid_data, 
  ftp_thr0_pid_data);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire l1clk_pm1;
wire br_reg_scanin;
wire br_reg_scanout;
wire br0_matches_curr;
wire br1_matches_curr;
wire [1:0] dec_br_taken_m;
wire [1:0] dec_valid_m;
wire br0_matches_curr_f;
wire br1_matches_curr_f;
wire [1:0] br_taken_ff;
wire tlu_flush_ifu_req_scanin;
wire tlu_flush_ifu_req_scanout;
wire [7:0] ftp_tlu_flush_f;
wire br_tid_reg_scanin;
wire br_tid_reg_scanout;
wire [1:0] tid1_m;
wire [1:0] tid0_m;
wire [1:0] tid1_b;
wire [1:0] tid0_b;
wire [7:0] next_tid_dec_b;
wire tid_dec_w_reg_scanin;
wire tid_dec_w_reg_scanout;
wire [7:0] tid_dec_w;
wire ftp_any_thread_ready;
wire [7:0] ready_hp_bf;
wire [7:0] fpick;
wire [7:0] hp_pick;
wire [7:0] ftp_curr_fetch_thr_bf;
wire [7:0] next_ith_det_thr_id;
wire [7:0] ith_det_thr_id;
wire it_rd_req_done_f;
wire tid_bf_reg_scanin;
wire tid_bf_reg_scanout;
wire [7:0] ftp_itb_fetch_thr_dup_bf;
wire [3:0] top_hp_ready;
wire [7:0] enabled_threads;
wire [3:0] bot_hp_ready;
wire top_hp_pickready;
wire bot_hp_pickready;
wire hp_pickready;
wire [3:0] bot_hp_pick;
wire [7:0] bot_lru;
wire [3:0] top_hp_pick;
wire [7:0] top_lru;
wire sel_top_hp;
wire favor_top;
wire [3:0] top_fpick;
wire [3:0] bot_fpick;
wire [7:0] ntop_lru;
wire [7:0] ntop_lru_in;
wire top_lruf_scanin;
wire top_lruf_scanout;
wire [7:0] top_lru_out;
wire [7:0] nbot_lru;
wire [7:0] nbot_lru_in;
wire bot_lruf_scanin;
wire bot_lruf_scanout;
wire [7:0] bot_lru_out;
wire set_favor_top;
wire reset_favor_top;
wire next_favor_top;
wire favor_top_reg_scanin;
wire favor_top_reg_scanout;
wire [7:0] next_curr_fetch_f_bf;
wire curr_fetch_thr_f_reg_scanin;
wire curr_fetch_thr_f_reg_scanout;
wire curr_fetch_thr_c_reg_scanin;
wire curr_fetch_thr_c_reg_scanout;
wire [7:0] ftp_curr_fetch_thr_c;
wire ftp_fetch_v_dup_f;
wire next_ftp_fill_req_q;
wire inv_line_reg_scanin;
wire inv_line_reg_scanout;
wire inv_line_bf;
wire next_fill_req;
wire fill_req_bf_reg_scanin;
wire fill_req_bf_reg_scanout;
wire ftp_fill_req_bf;
wire asi_rd_request;
wire next_rd_is_first;
wire wr_request_pending;
wire rd_request_pending;
wire asi_rd_is_first;
wire rd_is_first_reg_scanin;
wire rd_is_first_reg_scanout;
wire asi_wr_request;
wire next_wr_request_pending;
wire asi_wr_done_in;
wire next_rd_request_pending;
wire wr_request_pending_reg_scanin;
wire wr_request_pending_reg_scanout;
wire asi_rd_ok;
wire asi_wr_ok;
wire next_ic_wr_req;
wire ic_wr_req_ff;
wire ic_wr_req_ff_reg_scanin;
wire ic_wr_req_ff_reg_scanout;
wire next_ic_rd_req;
wire ic_rd_req_ff;
wire ic_rd_req_ff_reg_scanin;
wire ic_rd_req_ff_reg_scanout;
wire next_tg_wr_req;
wire tg_wr_req_ff;
wire tg_wr_req_ff_reg_scanin;
wire tg_wr_req_ff_reg_scanout;
wire next_tg_rd_req;
wire tg_rd_req_ff;
wire tg_rd_req_ff_reg_scanin;
wire tg_rd_req_ff_reg_scanout;
wire next_itt_rd_req;
wire itt_rd_req_ff;
wire reload;
wire reload_last;
wire itt_rd_req_ff_reg_scanin;
wire itt_rd_req_ff_reg_scanout;
wire next_itd_rd_req;
wire itd_rd_req_ff;
wire itd_rd_req_ff_reg_scanin;
wire itd_rd_req_ff_reg_scanout;
wire next_ith_det_req;
wire ith_det_req_ff;
wire ith_det_req_ff_reg_scanin;
wire ith_det_req_ff_reg_scanout;
wire next_itlb_probe_req_l;
wire itlb_probe_l_reg_scanin;
wire itlb_probe_l_reg_scanout;
wire fill_req_bf_q_reg_scanin;
wire fill_req_bf_q_reg_scanout;
wire mbist_in_reg_scanin;
wire mbist_in_reg_scanout;
wire ftp_itb_cam_en_1;
wire mbi_run_bf;
wire mbi_icd_write_en_bf;
wire mbi_ict_write_en_bf;
wire [1:0] mbi_cmpsel_bf;
wire ftp_mbi_icv_read_en_bf;
wire ftp_mbi_icv_write_en_bf;
wire ftp_itb_cam_en_2;
wire ftp_fetch_v_bf;
wire ifu_ic_pmen;
wire ftp_bypass_bf;
wire itlb_cam_vld_reg_scanin;
wire itlb_cam_vld_reg_scanout;
wire itlb_bypass_lat_scanin;
wire itlb_bypass_lat_scanout;
wire [7:0] itlb_bypass;
wire [7:0] pre_bypass_bf;
wire ic_rd_req_done_in;
wire ic_rd_done_f_reg_scanin;
wire ic_rd_done_f_reg_scanout;
wire ic_rd_req_done_f;
wire ic_rd_done_c_reg_scanin;
wire ic_rd_done_c_reg_scanout;
wire ic_rd_req_done_c;
wire ic_rd_done_p_reg_scanin;
wire ic_rd_done_p_reg_scanout;
wire ic_rd_req_done_p;
wire ic_wr_req_done_in;
wire ic_wr_done_f_reg_scanin;
wire ic_wr_done_f_reg_scanout;
wire ic_wr_req_done_f;
wire tg_rd_req_done_in;
wire tg_rd_done_f_reg_scanin;
wire tg_rd_done_f_reg_scanout;
wire tg_rd_req_done_f;
wire tg_rd_done_c_reg_scanin;
wire tg_rd_done_c_reg_scanout;
wire tg_rd_req_done_c;
wire tg_wr_req_done_in;
wire tg_wr_done_f_reg_scanin;
wire tg_wr_done_f_reg_scanout;
wire tg_wr_req_done_f;
wire it_rd_req_done_in;
wire it_rd_done_f_reg_scanin;
wire it_rd_done_f_reg_scanout;
wire it_rd_done_c_reg_scanin;
wire it_rd_done_c_reg_scanout;
wire it_rd_req_done_c;
wire asi_rd_done_in;
wire ftp_asi_it_rd_done_p;
wire asi_rd_done_reg_scanin;
wire asi_rd_done_reg_scanout;
wire asi_wr_done_reg_scanin;
wire asi_wr_done_reg_scanout;
wire asi_it_rd_done_reg_scanin;
wire asi_it_rd_done_reg_scanout;
wire next_sel_mbist_itb_cycle0;
wire next_sel_mbist_itb_cycle1;
wire next_sel_mbist_itb_cycle2;
wire next_sel_mbist_itb_cycle3;
wire next_sel_itlb_tag;
wire itlb_sel_tag_f_reg_scanin;
wire itlb_sel_tag_f_reg_scanout;
wire ftp_sel_itlb_tag_f;
wire next_sel_itlb_data;
wire itlb_sel_data_f_reg_scanin;
wire itlb_sel_data_f_reg_scanout;
wire ftp_sel_itlb_data_f;
wire next_sel_itlb_pa;
wire itlb_sel_pa_f_reg_scanin;
wire itlb_sel_pa_f_reg_scanout;
wire ftp_sel_itlb_pa_f;
wire sel_itlb_tag_cntx0_f;
wire sel_itlb_tag_cntx1_f;
wire itlb_sel_c_reg_scanin;
wire itlb_sel_c_reg_scanout;
wire [3:0] trap_thread_g0;
wire [3:0] trap_thread_g1;
wire thr0_trap_pcaddr_is_valid_bf;
wire thr1_trap_pcaddr_is_valid_bf;
wire thr2_trap_pcaddr_is_valid_bf;
wire thr3_trap_pcaddr_is_valid_bf;
wire thr4_trap_pcaddr_is_valid_bf;
wire thr5_trap_pcaddr_is_valid_bf;
wire thr6_trap_pcaddr_is_valid_bf;
wire thr7_trap_pcaddr_is_valid_bf;
wire [7:0] load_flush_w;
wire thr0_red_no_br_bf;
wire thr1_red_no_br_bf;
wire thr2_red_no_br_bf;
wire thr3_red_no_br_bf;
wire thr4_red_no_br_bf;
wire thr5_red_no_br_bf;
wire thr6_red_no_br_bf;
wire thr7_red_no_br_bf;
wire thrx_redirect_reg_scanin;
wire thrx_redirect_reg_scanout;
wire thr7_redirect_part_bf;
wire thr6_redirect_part_bf;
wire thr5_redirect_part_bf;
wire thr4_redirect_part_bf;
wire thr3_redirect_part_bf;
wire thr2_redirect_part_bf;
wire thr1_redirect_part_bf;
wire thr0_redirect_part_bf;
wire thr0_redirect_bf;
wire thr0_br_taken_ff;
wire thr1_redirect_bf;
wire thr1_br_taken_ff;
wire thr2_redirect_bf;
wire thr2_br_taken_ff;
wire thr3_redirect_bf;
wire thr3_br_taken_ff;
wire thr4_redirect_bf;
wire thr4_br_taken_ff;
wire thr5_redirect_bf;
wire thr5_br_taken_ff;
wire thr6_redirect_bf;
wire thr6_br_taken_ff;
wire thr7_redirect_bf;
wire thr7_br_taken_ff;
wire kill_fetch_fv_bf;
wire next_fetch_fv_unq_bf;
wire fetch_v_f_reg_scanin;
wire fetch_v_f_reg_scanout;
wire ftp_fetch_v_unq_f;
wire fetch_v_f_dup_reg_scanin;
wire fetch_v_f_dup_reg_scanout;
wire ftp_fetch_v_unq_dup_f;
wire br_redirect_disqual;
wire br_redirect_dup_disqual;
wire next_fetch_v_c_f;
wire fetch_v_c_reg_scanin;
wire fetch_v_c_reg_scanout;
wire ftp_fetch_v_c_unq;
wire ftp_fetch_v_c;
wire [7:0] next_enabled_thread;
wire enabled_thr_reg_scanin;
wire enabled_thr_reg_scanout;
wire ifu_ftu_pmen;
wire [7:0] br_room_reset;
wire ftp_thr0_fetch_v_wo_br_bf;
wire thr0_by_pass_2_cycles_at_c;
wire ftp_thr1_fetch_v_wo_br_bf;
wire thr1_by_pass_2_cycles_at_c;
wire ftp_thr2_fetch_v_wo_br_bf;
wire thr2_by_pass_2_cycles_at_c;
wire ftp_thr3_fetch_v_wo_br_bf;
wire thr3_by_pass_2_cycles_at_c;
wire ftp_thr4_fetch_v_wo_br_bf;
wire thr4_by_pass_2_cycles_at_c;
wire ftp_thr5_fetch_v_wo_br_bf;
wire thr5_by_pass_2_cycles_at_c;
wire ftp_thr6_fetch_v_wo_br_bf;
wire thr6_by_pass_2_cycles_at_c;
wire ftp_thr7_fetch_v_wo_br_bf;
wire thr7_by_pass_2_cycles_at_c;
wire ftp_thr0_fetch_v_f;
wire thr0_by_pass_next_cycle_at_c;
wire ftp_thr1_fetch_v_f;
wire thr1_by_pass_next_cycle_at_c;
wire ftp_thr2_fetch_v_f;
wire thr2_by_pass_next_cycle_at_c;
wire ftp_thr3_fetch_v_f;
wire thr3_by_pass_next_cycle_at_c;
wire ftp_thr4_fetch_v_f;
wire thr4_by_pass_next_cycle_at_c;
wire ftp_thr5_fetch_v_f;
wire thr5_by_pass_next_cycle_at_c;
wire ftp_thr6_fetch_v_f;
wire thr6_by_pass_next_cycle_at_c;
wire ftp_thr7_fetch_v_f;
wire thr7_by_pass_next_cycle_at_c;
wire ftp_thr0_fetch_v_c;
wire thr0_by_pass_is_at_c;
wire ftp_thr1_fetch_v_c;
wire thr1_by_pass_is_at_c;
wire ftp_thr2_fetch_v_c;
wire thr2_by_pass_is_at_c;
wire ftp_thr3_fetch_v_c;
wire thr3_by_pass_is_at_c;
wire ftp_thr4_fetch_v_c;
wire thr4_by_pass_is_at_c;
wire ftp_thr5_fetch_v_c;
wire thr5_by_pass_is_at_c;
wire ftp_thr6_fetch_v_c;
wire thr6_by_pass_is_at_c;
wire ftp_thr7_fetch_v_c;
wire thr7_by_pass_is_at_c;
wire thr0_is_empty_c;
wire thr1_is_empty_c;
wire thr2_is_empty_c;
wire thr3_is_empty_c;
wire thr4_is_empty_c;
wire thr5_is_empty_c;
wire thr6_is_empty_c;
wire thr7_is_empty_c;
wire thr0_room_4ormore;
wire thr1_room_4ormore;
wire thr2_room_4ormore;
wire thr3_room_4ormore;
wire thr4_room_4ormore;
wire thr5_room_4ormore;
wire thr6_room_4ormore;
wire thr7_room_4ormore;
wire [7:0] ready_hp_in;
wire tsm_thr0_ready_hp_bf;
wire tsm_thr1_ready_hp_bf;
wire tsm_thr2_ready_hp_bf;
wire tsm_thr3_ready_hp_bf;
wire tsm_thr4_ready_hp_bf;
wire tsm_thr5_ready_hp_bf;
wire tsm_thr6_ready_hp_bf;
wire tsm_thr7_ready_hp_bf;
wire [7:0] ftp_unused;
wire ready_fp_reg_scanin;
wire ready_fp_reg_scanout;
wire [7:0] next_by_pass_sel_bbf;
wire cmu_fill_byp_thread_reg_scanin;
wire cmu_fill_byp_thread_reg_scanout;
wire [7:0] by_pass_sel_bf;
wire by_pass_sel_f_reg_scanin;
wire by_pass_sel_f_reg_scanout;
wire [7:0] by_pass_sel_f;
wire by_pass_sel_c_reg_scanin;
wire by_pass_sel_c_reg_scanout;
wire [7:0] by_pass_sel_c;
wire thr0_kill_by_pass_bbf;
wire thr1_kill_by_pass_bbf;
wire thr2_kill_by_pass_bbf;
wire thr3_kill_by_pass_bbf;
wire thr4_kill_by_pass_bbf;
wire thr5_kill_by_pass_bbf;
wire thr6_kill_by_pass_bbf;
wire thr7_kill_by_pass_bbf;
wire byp_valid_in;
wire byp_valid_reg_scanin;
wire byp_valid_reg_scanout;
wire ftp_byp_valid;
wire thrx_kill_by_pass_reg_scanin;
wire thrx_kill_by_pass_reg_scanout;
wire thr7_kill_by_pass_bf;
wire thr6_kill_by_pass_bf;
wire thr5_kill_by_pass_bf;
wire thr4_kill_by_pass_bf;
wire thr3_kill_by_pass_bf;
wire thr2_kill_by_pass_bf;
wire thr1_kill_by_pass_bf;
wire thr0_kill_by_pass_bf;
wire kill2_by_pass_bf;
wire bypass_thread_killed;
wire by_pass_valid_bf;
wire prev_by_pass_at_cycle_1;
wire cycle_2_by_pass_ok_f;
wire cycle_3_by_pass_ok_c;
wire prev_by_pass_at_cycle_2;
wire cycle_3_by_pass_ok_f;
wire cycle_2_by_pass_ok_bf;
wire cycle_3_by_pass_ok_bf;
wire cycle_2_by_pass_f_reg_scanin;
wire cycle_2_by_pass_f_reg_scanout;
wire cycle_3_by_pass_f_reg_scanin;
wire cycle_3_by_pass_f_reg_scanout;
wire cycle_3_by_pass_c_reg_scanin;
wire cycle_3_by_pass_c_reg_scanout;
wire by_pass_v_f_reg_scanin;
wire by_pass_v_f_reg_scanout;
wire by_pass_valid_unq_f;
wire by_pass_valid_f;
wire bypass_thread_redirected_p_f;
wire bypass_thread_redirected_f;
wire next_by_pass_c_valid;
wire by_pass_v_c_reg_scanin;
wire by_pass_v_c_reg_scanout;
wire by_pass_valid_c;
wire sel_by_pass_cycle_2_int_f;
wire sel_by_pass_cycle_3_int_c;
wire thr0_by_pass_valid_bf;
wire thr1_by_pass_valid_bf;
wire thr2_by_pass_valid_bf;
wire thr3_by_pass_valid_bf;
wire thr4_by_pass_valid_bf;
wire thr5_by_pass_valid_bf;
wire thr6_by_pass_valid_bf;
wire thr7_by_pass_valid_bf;
wire thr0_by_pass_valid_f;
wire thr1_by_pass_valid_f;
wire thr2_by_pass_valid_f;
wire thr3_by_pass_valid_f;
wire thr4_by_pass_valid_f;
wire thr5_by_pass_valid_f;
wire thr6_by_pass_valid_f;
wire thr7_by_pass_valid_f;
wire thr0_by_pass_valid_c;
wire thr1_by_pass_valid_c;
wire thr2_by_pass_valid_c;
wire thr3_by_pass_valid_c;
wire thr4_by_pass_valid_c;
wire thr5_by_pass_valid_c;
wire thr6_by_pass_valid_c;
wire thr7_by_pass_valid_c;
wire thr0_by_pass_cycle_2_bf;
wire thr0_by_pass_cycle_3_f;
wire thr1_by_pass_cycle_2_bf;
wire thr1_by_pass_cycle_3_f;
wire thr2_by_pass_cycle_2_bf;
wire thr2_by_pass_cycle_3_f;
wire thr3_by_pass_cycle_2_bf;
wire thr3_by_pass_cycle_3_f;
wire thr4_by_pass_cycle_2_bf;
wire thr4_by_pass_cycle_3_f;
wire thr5_by_pass_cycle_2_bf;
wire thr5_by_pass_cycle_3_f;
wire thr6_by_pass_cycle_2_bf;
wire thr6_by_pass_cycle_3_f;
wire thr7_by_pass_cycle_2_bf;
wire thr7_by_pass_cycle_3_f;
wire fetch_same_thr_again_bf;
wire ftp_curr_pstate_am_bf_;
wire select_itc_va;
wire sel_am_5;
wire [7:0] next_pstate_am_;
wire pstate_am_reg_scanin;
wire pstate_am_reg_scanout;
wire [7:0] ftp_pstate_am_bf_;
wire reload_in;
wire reload_latch_scanin;
wire reload_latch_scanout;
wire next_ftp_ith_det_req_bf;
wire next_select_itc_va;
wire next_sel_am_5;
wire pre_sel_am_reg_scanin;
wire pre_sel_am_reg_scanout;
wire [2:0] next_thr0_pid_data;
wire [2:0] thr0_pid_data;
wire [2:0] next_thr1_pid_data;
wire [2:0] thr1_pid_data;
wire [2:0] next_thr2_pid_data;
wire [2:0] thr2_pid_data;
wire [2:0] next_thr3_pid_data;
wire [2:0] thr3_pid_data;
wire [2:0] next_thr4_pid_data;
wire [2:0] thr4_pid_data;
wire [2:0] next_thr5_pid_data;
wire [2:0] thr5_pid_data;
wire [2:0] next_thr6_pid_data;
wire [2:0] thr6_pid_data;
wire [2:0] next_thr7_pid_data;
wire [2:0] thr7_pid_data;
wire thr0_pid_reg_scanin;
wire thr0_pid_reg_scanout;
wire thr1_pid_reg_scanin;
wire thr1_pid_reg_scanout;
wire thr2_pid_reg_scanin;
wire thr2_pid_reg_scanout;
wire thr3_pid_reg_scanin;
wire thr3_pid_reg_scanout;
wire thr4_pid_reg_scanin;
wire thr4_pid_reg_scanout;
wire thr5_pid_reg_scanin;
wire thr5_pid_reg_scanout;
wire thr6_pid_reg_scanin;
wire thr6_pid_reg_scanout;
wire thr7_pid_reg_scanin;
wire thr7_pid_reg_scanout;
wire invalidation_req_f;
wire spares_scanin;
wire spares_scanout;
wire [4:2] curr_thr_pc_bf;
wire [2:0] ic_pwr_sel_index;
wire [4:2] thr0_pc_muxed_f;
wire [4:2] thr1_pc_muxed_f;
wire [4:2] thr2_pc_muxed_f;
wire [4:2] thr3_pc_muxed_f;
wire [4:2] thr4_pc_muxed_f;
wire [4:2] thr5_pc_muxed_f;
wire [4:2] thr6_pc_muxed_f;
wire [4:2] thr7_pc_muxed_f;
wire [4:2] new_thr_pc_bf;
wire [4:2] ic_index_bf;
wire se;

input tcu_scan_en ;
input   l2clk;
input  	scan_in;
input  	tcu_pce_ov;		// scan signals
input  	spc_aclk;
input  	spc_bclk;

input [7:0] spc_core_running_status;
input [7:0] tlu_pstate_am;
input [7:0] tlu_flush_ifu;
input [7:0] tlu_itlb_bypass;

input [1:0] tlu_trap_0_tid;
input [1:0] tlu_trap_1_tid;
input       tlu_trap_pc_0_valid;
input       tlu_trap_pc_1_valid;

input [1:0]  dec_br_taken_e;
input [1:0]  dec_valid_e;
// input [1:0]  dec_br_reg_taken_e;
// input [1:0]  dec_br_noreg_taken_e;
input [1:0]  dec_tid0_d;
input [1:0]  dec_tid1_d;

input 	     itc_demap_next;
input        mbi_run;
input        mbi_itb_cam_en_pre	;
input  [1:0] mbi_cmpsel;
input        mbi_ict_read_en;
input        mbi_ict_write_en;
input        mbi_icd_read_en;
input        mbi_icd_write_en;
input        mbi_icv_read_en;
input        mbi_icv_write_en;


input		cmu_thr0_data_ready  ; 
input		cmu_thr1_data_ready  ;
input		cmu_thr2_data_ready  ;
input		cmu_thr3_data_ready  ;
input		cmu_thr4_data_ready  ;
input		cmu_thr5_data_ready  ;
input		cmu_thr6_data_ready  ;
input		cmu_thr7_data_ready  ;


input		tsm_thr0_ignore_by_pass  ;  
input		tsm_thr1_ignore_by_pass  ;
input		tsm_thr2_ignore_by_pass  ;
input		tsm_thr3_ignore_by_pass  ;
input		tsm_thr4_ignore_by_pass  ;
input		tsm_thr5_ignore_by_pass  ;
input		tsm_thr6_ignore_by_pass  ;
input		tsm_thr7_ignore_by_pass  ;


// input        agc_ld_flush_hi_pr_bf ;
// input  [2:0] agc_ld_flush_tid_bf ;
input  [1:0] dec_load_flush_w;


input   tsm_thr0_ready_hp_bf_in;
input   tsm_thr1_ready_hp_bf_in;
input   tsm_thr2_ready_hp_bf_in;
input   tsm_thr3_ready_hp_bf_in;
input   tsm_thr4_ready_hp_bf_in;
input   tsm_thr5_ready_hp_bf_in;
input   tsm_thr6_ready_hp_bf_in;
input   tsm_thr7_ready_hp_bf_in;


input   tsm_thr0_fill_rdy0;
input   tsm_thr1_fill_rdy0;
input   tsm_thr2_fill_rdy0;
input   tsm_thr3_fill_rdy0;
input   tsm_thr4_fill_rdy0;
input   tsm_thr5_fill_rdy0;
input   tsm_thr6_fill_rdy0;
input   tsm_thr7_fill_rdy0;


input       cmu_icache_invalidate   ;
input       cmu_any_un_cacheable    ;

input       cmu_any_data_ready      ;

input [7:0]   ibu_empty;
input [7:0]   ibu_room_4ormore;


input [7:0] agc_by_pass_update_lru_bf;
input [7:0] agc_invalidation_req_ff;
// input [2:0] itd_tid;

input   agc_kill_fetch_cv_c;

input   agc_thr0_micro_flush_unq_c ; 
input   agc_thr1_micro_flush_unq_c ; 
input   agc_thr2_micro_flush_unq_c ; 
input   agc_thr3_micro_flush_unq_c ; 
input   agc_thr4_micro_flush_unq_c ; 
input   agc_thr5_micro_flush_unq_c ; 
input   agc_thr6_micro_flush_unq_c ; 
input   agc_thr7_micro_flush_unq_c ; 

input   agc_thr0_sf_valid_f;
input   agc_thr1_sf_valid_f;
input   agc_thr2_sf_valid_f;
input   agc_thr3_sf_valid_f;
input   agc_thr4_sf_valid_f;
input   agc_thr5_sf_valid_f;
input   agc_thr6_sf_valid_f;
input   agc_thr7_sf_valid_f;

input   asi_sel_cntx_0;
input   asi_ic_wr_req;
input   asi_ic_rd_req;
input   asi_tg_wr_req;
input   asi_tg_rd_req;
input   asi_itd_rd_req;
input   asi_itt_rd_req;
input   asi_ith_det_req;

input [2:0] asi_tid ;

input [4:2]  agd_address0_m ;
input [4:2]  agd_address1_m ;
input [4:2]  agd_thr0_pc_4_2_f ;
input [4:2]  agd_thr1_pc_4_2_f ;
input [4:2]  agd_thr2_pc_4_2_f ;
input [4:2]  agd_thr3_pc_4_2_f ;
input [4:2]  agd_thr4_pc_4_2_f ;
input [4:2]  agd_thr5_pc_4_2_f ;
input [4:2]  agd_thr6_pc_4_2_f ;
input [4:2]  agd_thr7_pc_4_2_f ;
input [4:2]  ifu_agd_pc_f ;
input [5:3]  asi_addr_bf ;


// input        agc_sel_by_pass_cycle_2_int_f  ;
// input        agc_sel_by_pass_cycle_3_int_c  ;
input        lsu_ifu_ftu_pmen;              // enable power management.
input        lsu_ic_pmen;                   // enable power management for the ICD and ICT.
input        lsu_ifu_wr_pid  ; 
input [2:0]  lsu_ifu_tid_w ;   
input [2:0]  lsu_ifu_pid_data ;


// output        ftp_sel_flush_ld_flush;
output        ftp_asi_rd_done;
output        ftp_asi_wr_done;

output        ftp_reset_fill_wait;
output        ftp_ic_rd_req_bf;
output        ftp_ic_wr_ps_en_bf;
output        ftp_ic_wr_req_bf;
output        ftp_tg_rd_req_bf;
output        ftp_tg_wr_req_bf;
output        ftp_iv_rd_req_bf;
output        ftp_itt_rd_req_bf;
output        ftp_itd_rd_req_bf;
output        ftp_itlb_cam_vld_bf ;
output        ftp_itlb_cam_vld_f ;
output        ftp_ith_det_req_bf ;

output        ftp_itlb_probe_req_l ;

output        ftp_sel_icv_mbist_addr ;

output        ftp_sel_mbist_itb_cycle0 ;
output        ftp_sel_mbist_itb_cycle1 ;
output        ftp_sel_mbist_itb_cycle2 ;
output        ftp_sel_mbist_itb_cycle3 ;

output        ftp_sel_itlb_tag_cntx0_c;
output        ftp_sel_itlb_tag_cntx1_c;
output        ftp_sel_itlb_data_c;
output        ftp_sel_itlb_pa_c;
output        ftp_asi_mbist_access_bf;

output        ftp_asi_it_rd_done;
output        ftp_asi_ic_rd_done;
output        ftp_asi_ic_wr_done;
output        ftp_asi_tg_rd_done;
output        ftp_asi_tg_wr_done;
output        ftp_asi_tg_wr_req_hold;

output        ftp_thr0_room_is_less_t_3; 
output        ftp_thr1_room_is_less_t_3; 
output        ftp_thr2_room_is_less_t_3; 
output        ftp_thr3_room_is_less_t_3; 
output        ftp_thr4_room_is_less_t_3; 
output        ftp_thr5_room_is_less_t_3; 
output        ftp_thr6_room_is_less_t_3; 
output        ftp_thr7_room_is_less_t_3; 

output        ftp_thr0_go_to_sf_wait;
output        ftp_thr1_go_to_sf_wait;
output        ftp_thr2_go_to_sf_wait;
output        ftp_thr3_go_to_sf_wait;
output        ftp_thr4_go_to_sf_wait;
output        ftp_thr5_go_to_sf_wait;
output        ftp_thr6_go_to_sf_wait;
output        ftp_thr7_go_to_sf_wait;

output [2:0]  ftp_thr0_trprdpc_sel_bf;
output [2:0]  ftp_thr1_trprdpc_sel_bf;
output [2:0]  ftp_thr2_trprdpc_sel_bf;
output [2:0]  ftp_thr3_trprdpc_sel_bf;
output [2:0]  ftp_thr4_trprdpc_sel_bf;
output [2:0]  ftp_thr5_trprdpc_sel_bf;
output [2:0]  ftp_thr6_trprdpc_sel_bf;
output [2:0]  ftp_thr7_trprdpc_sel_bf;

output        ftp_thr0_sel_br_bf;
output        ftp_thr1_sel_br_bf;
output        ftp_thr2_sel_br_bf;
output        ftp_thr3_sel_br_bf;
output        ftp_thr4_sel_br_bf;
output        ftp_thr5_sel_br_bf;
output        ftp_thr6_sel_br_bf;
output        ftp_thr7_sel_br_bf;

output        ftp_icd_quad_0_en_bf;
output        ftp_icd_quad_1_en_bf;
output        ftp_icd_quad_2_en_bf;
output        ftp_icd_quad_3_en_bf;

output        ftp_tg_clk_en;

// output  [1:0] ftp_pc_sel_nb0_nb1;
// output  [2:0] ftp_pc_sel_b0_nb1;
// output  [2:0] ftp_pc_sel_nb0_b1;
// output  [1:0] ftp_pc_sel_b0_b1;

output  [5:0] ftp_pc_sel_am;
output  [2:0] ftp_pc_sel_tag_part1;
output  [3:0] ftp_pc_sel_tag_part2;
output  [1:0] ftp_pc_sel_tag_pc_bot;
output  [1:0] ftp_pc_sel_tag_pc_top;


output  [4:0] ftp_icaddr_sel_first_mux;

// output  [4:0] ftp_icaddr_sel_nb0_nb1;
// output  [4:0] ftp_icaddr_sel_b0_nb1;
// output  [4:0] ftp_icaddr_sel_nb0_b1;
// output  [4:0] ftp_icaddr_sel_b0_b1;

output  [7:0] ftp_itb_fetch_thr_bf;
// output  [7:0] ftp_ctx_fetch_thr_bf;
output  [7:0] ftp_new_thr_sel_bf;
output  [7:0] ftu_curr_fetch_thr_f;
output  [7:0] ftp_curr_fetch_thr_f;
output  [7:0] ftp_fetch_thr_q_f;
output  [1:0] ftp_tid0_e;
output  [1:0] ftp_tid1_e;
// output        ftp_go_to_fill_wait;

// output        ftp_thr0_go_to_fill_wait;
// output        ftp_thr1_go_to_fill_wait;
// output        ftp_thr2_go_to_fill_wait;
// output        ftp_thr3_go_to_fill_wait;
// output        ftp_thr4_go_to_fill_wait;
// output        ftp_thr5_go_to_fill_wait;
// output        ftp_thr6_go_to_fill_wait;
// output        ftp_thr7_go_to_fill_wait;

output        ftp_fetch_v_f;

// output        ftp_fill_req_bf;
output        ftp_fill_req_q_bf;
output        ftp_mbi_icd_read_en_bf;
output        ftp_mbi_ict_read_en_bf;
output [2:0]  ftp_ict_data_sel_bf;
output        ftp_any_thr_clken;				
output        scan_out;

output [2:0]  ftp_curr_pid_bf;
output [2:0]  ftp_thr7_pid_data;
output [2:0]  ftp_thr6_pid_data;
output [2:0]  ftp_thr5_pid_data;
output [2:0]  ftp_thr4_pid_data;
output [2:0]  ftp_thr3_pid_data;
output [2:0]  ftp_thr2_pid_data;
output [2:0]  ftp_thr1_pid_data;
output [2:0]  ftp_thr0_pid_data;


// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan


// assign br_reg_taken_e[1:0]   = dec_br_reg_taken_e[1:0]   & dec_valid_e[1:0];
// assign br_noreg_taken_e[1:0] = dec_br_noreg_taken_e[1:0] & dec_valid_e[1:0];


ifu_ftu_ftp_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

ifu_ftu_ftp_ctl_l1clkhdr_ctl_macro clkgen_pm (
 .l2clk(l2clk),
 .l1en (ftp_any_thr_clken),
 .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


////////////////////////////////////////////////////////////////


ifu_ftu_ftp_ctl_msff_ctl_macro__width_6 br_reg  (
 .scan_in(br_reg_scanin),
 .scan_out(br_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  ({dec_br_taken_e[1:0],   dec_valid_e[1:0] , br0_matches_curr  , br1_matches_curr}),
 .dout ({dec_br_taken_m[1:0],   dec_valid_m[1:0] , br0_matches_curr_f, br1_matches_curr_f}),
  .siclk(siclk),
  .soclk(soclk)
);

assign br_taken_ff[0] = dec_br_taken_m[0] & dec_valid_m[0] ;
assign br_taken_ff[1] = dec_br_taken_m[1] & dec_valid_m[1] ;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 tlu_flush_ifu_req  (
 .scan_in(tlu_flush_ifu_req_scanin),
 .scan_out(tlu_flush_ifu_req_scanout),
 .l1clk(l1clk),
 .din  (tlu_flush_ifu[7:0]),
 .dout (ftp_tlu_flush_f[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_12 br_tid_reg  (
 .scan_in(br_tid_reg_scanin),
 .scan_out(br_tid_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  ({dec_tid1_d[1:0],dec_tid0_d[1:0], ftp_tid1_e[1:0], ftp_tid0_e[1:0], tid1_m[1:0], tid0_m[1:0]}),
 .dout ({ftp_tid1_e[1:0],ftp_tid0_e[1:0], tid1_m[1:0], tid0_m[1:0], tid1_b[1:0], tid0_b[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign next_tid_dec_b[0] = ~tid0_b[1] & ~tid0_b[0] ;
assign next_tid_dec_b[1] = ~tid0_b[1] &  tid0_b[0] ;
assign next_tid_dec_b[2] =  tid0_b[1] & ~tid0_b[0] ;
assign next_tid_dec_b[3] =  tid0_b[1] &  tid0_b[0] ;
assign next_tid_dec_b[4] = ~tid1_b[1] & ~tid1_b[0] ;
assign next_tid_dec_b[5] = ~tid1_b[1] &  tid1_b[0] ;
assign next_tid_dec_b[6] =  tid1_b[1] & ~tid1_b[0] ;
assign next_tid_dec_b[7] =  tid1_b[1] &  tid1_b[0] ;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 tid_dec_w_reg  (
 .scan_in(tid_dec_w_reg_scanin),
 .scan_out(tid_dec_w_reg_scanout),
 .l1clk(l1clk),
 .din  (next_tid_dec_b[7:0]),
 .dout (tid_dec_w[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);


assign ftp_any_thread_ready       = |ready_hp_bf[7:0] ;
assign fpick[7:0]                 =  hp_pick[7:0] | agc_by_pass_update_lru_bf[7:0] ; 
assign ftp_curr_fetch_thr_bf[7:0] =  hp_pick[7:0] ;
assign ftp_new_thr_sel_bf[7:1] = hp_pick[7:1] ;
assign ftp_new_thr_sel_bf[0]   = hp_pick[0] | ~ftp_any_thread_ready ;

assign next_ith_det_thr_id[0]          =  asi_ith_det_req ? (~asi_tid[2] & ~asi_tid[1] & ~asi_tid[0]) : (ith_det_thr_id[0] & ~it_rd_req_done_f);
assign next_ith_det_thr_id[1]          =  asi_ith_det_req ? (~asi_tid[2] & ~asi_tid[1] &  asi_tid[0]) : (ith_det_thr_id[1] & ~it_rd_req_done_f);
assign next_ith_det_thr_id[2]          =  asi_ith_det_req ? (~asi_tid[2] &  asi_tid[1] & ~asi_tid[0]) : (ith_det_thr_id[2] & ~it_rd_req_done_f);
assign next_ith_det_thr_id[3]          =  asi_ith_det_req ? (~asi_tid[2] &  asi_tid[1] &  asi_tid[0]) : (ith_det_thr_id[3] & ~it_rd_req_done_f);
assign next_ith_det_thr_id[4]          =  asi_ith_det_req ? ( asi_tid[2] & ~asi_tid[1] & ~asi_tid[0]) : (ith_det_thr_id[4] & ~it_rd_req_done_f);
assign next_ith_det_thr_id[5]          =  asi_ith_det_req ? ( asi_tid[2] & ~asi_tid[1] &  asi_tid[0]) : (ith_det_thr_id[5] & ~it_rd_req_done_f);
assign next_ith_det_thr_id[6]          =  asi_ith_det_req ? ( asi_tid[2] &  asi_tid[1] & ~asi_tid[0]) : (ith_det_thr_id[6] & ~it_rd_req_done_f);
assign next_ith_det_thr_id[7]          =  asi_ith_det_req ? ( asi_tid[2] &  asi_tid[1] &  asi_tid[0]) : (ith_det_thr_id[7] & ~it_rd_req_done_f);


 ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 tid_bf_reg  (
      .scan_in(tid_bf_reg_scanin),
      .scan_out(tid_bf_reg_scanout),
      .l1clk  (l1clk),
      .din    (next_ith_det_thr_id[7:0]),
      .dout   (ith_det_thr_id[7:0]),
  .siclk(siclk),
  .soclk(soclk)
 );


   assign ftp_itb_fetch_thr_bf[7:0]     = ftp_ith_det_req_bf ? ith_det_thr_id[7:0] :  hp_pick[7:0] ;
   assign ftp_itb_fetch_thr_dup_bf[7:0] = ftp_ith_det_req_bf ? ith_det_thr_id[7:0] :  hp_pick[7:0] ;
// assign ftp_itb_fetch_thr_bf[7:0] = ith_det_thr_id[7:0]     |  hp_pick[7:0] ;
// assign ftp_itb_fetch_thr_dup_bf[7:0] = ith_det_thr_id[7:0] |  hp_pick[7:0] ;
// assign ftp_ctx_fetch_thr_bf[7:0] = ftp_select_itc_ctx ? tlb_wr_thr_id[7:0]  :   ftp_itb_fetch_thr_bf[7:0] ; 

assign top_hp_ready[3:0] = ready_hp_bf[7:4]  & enabled_threads[7:4];
assign bot_hp_ready[3:0] = ready_hp_bf[3:0]  & enabled_threads[3:0];

assign top_hp_pickready  = (|top_hp_ready[3:0]) ;
assign bot_hp_pickready  = (|bot_hp_ready[3:0]) ;
assign hp_pickready = top_hp_pickready | bot_hp_pickready  ;

assign bot_hp_pick[3] = (bot_hp_ready[3]&!bot_hp_ready[1]&!bot_hp_ready[0]&bot_lru[1]&!bot_lru[0]) | 
                        (bot_hp_ready[3]&!bot_hp_ready[2]&!bot_hp_ready[0]&!bot_lru[1]&bot_lru[0]) | 
                        (bot_hp_ready[3]&!bot_hp_ready[1]&!bot_lru[2]&!bot_lru[0]) | 
                        (bot_hp_ready[3]&!bot_hp_ready[2]&!bot_lru[3]&!bot_lru[1]) | 
                        (bot_hp_ready[3]&!bot_hp_ready[2]&!bot_hp_ready[1]&!bot_lru[1]&!bot_lru[0]) | 
                        (bot_hp_ready[3]&!bot_hp_ready[0]&!bot_lru[7]&!bot_lru[6]&bot_lru[5]&bot_lru[4]) | 
                        (bot_hp_ready[3]&bot_lru[7]&bot_lru[6]) | 
                        (bot_hp_ready[3]&!bot_hp_ready[2]&!bot_hp_ready[1]&!bot_hp_ready[0]);

assign bot_hp_pick[2] = (!bot_hp_ready[3]&bot_hp_ready[2]&!bot_hp_ready[1]&!bot_lru[1]&!bot_lru[0]) | 
                        (bot_hp_ready[2]&!bot_hp_ready[1]&!bot_hp_ready[0]&bot_lru[1]&bot_lru[0]) | 
                        (bot_hp_ready[2]&!bot_hp_ready[0]&bot_lru[2]&bot_lru[0]) | 
                        (!bot_hp_ready[3]&bot_hp_ready[2]&!bot_lru[3]&!bot_lru[1]) | 
                        (!bot_hp_ready[3]&bot_hp_ready[2]&!bot_hp_ready[0]&!bot_lru[1]&bot_lru[0]) | 
                        (bot_hp_ready[2]&!bot_hp_ready[1]&!bot_lru[7]&bot_lru[6]&bot_lru[5]&!bot_lru[4]) | 
                        (bot_hp_ready[2]&bot_lru[7]&!bot_lru[6]) | 
                        (!bot_hp_ready[3]&bot_hp_ready[2]&!bot_hp_ready[1]&!bot_hp_ready[0]);

assign bot_hp_pick[1] = (!bot_hp_ready[3]&!bot_hp_ready[2]&bot_hp_ready[1]&!bot_lru[1]&!bot_lru[0]) | 
                        (!bot_hp_ready[2]&bot_hp_ready[1]&!bot_hp_ready[0]&bot_lru[1]&bot_lru[0]) | 
                        (!bot_hp_ready[3]&bot_hp_ready[1]&!bot_lru[2]&!bot_lru[0]) | 
                        (bot_hp_ready[1]&!bot_hp_ready[0]&bot_lru[3]&bot_lru[1]) | 
                        (!bot_hp_ready[3]&bot_hp_ready[1]&!bot_hp_ready[0]&bot_lru[1]&!bot_lru[0]) | 
                        (!bot_hp_ready[2]&bot_hp_ready[1]&bot_lru[7]&!bot_lru[6]&!bot_lru[5]&bot_lru[4]) | 
                        (bot_hp_ready[1]&!bot_lru[7]&bot_lru[6]) | 
                        (!bot_hp_ready[3]&!bot_hp_ready[2]&bot_hp_ready[1]&!bot_hp_ready[0]);

assign bot_hp_pick[0] = (!bot_hp_ready[3]&!bot_hp_ready[1]&bot_hp_ready[0]&bot_lru[1]&!bot_lru[0]) | 
                        (!bot_hp_ready[3]&!bot_hp_ready[2]&bot_hp_ready[0]&!bot_lru[1]&bot_lru[0]) | 
                        (!bot_hp_ready[2]&bot_hp_ready[0]&bot_lru[2]&bot_lru[0]) | 
                        (!bot_hp_ready[1]&bot_hp_ready[0]&bot_lru[3]&bot_lru[1]) | 
                        (!bot_hp_ready[2]&!bot_hp_ready[1]&bot_hp_ready[0]&bot_lru[1]&bot_lru[0]) | 
                        (!bot_hp_ready[3]&bot_hp_ready[0]&bot_lru[7]&bot_lru[6]&!bot_lru[5]&!bot_lru[4]) | 
                        (bot_hp_ready[0]&!bot_lru[7]&!bot_lru[6]) | 
                        (!bot_hp_ready[3]&!bot_hp_ready[2]&!bot_hp_ready[1]&bot_hp_ready[0]);

assign top_hp_pick[3] = (top_hp_ready[3]&!top_hp_ready[1]&!top_hp_ready[0]&top_lru[1]&!top_lru[0]) | 
                        (top_hp_ready[3]
    &!top_hp_ready[2]&!top_hp_ready[0]&!top_lru[1]&top_lru[0]) | 
                        (top_hp_ready[3]&!top_hp_ready[1]&!top_lru[2]
    &!top_lru[0]) | 
                        (top_hp_ready[3]&!top_hp_ready[2]&!top_lru[3]&!top_lru[1]) | 
                        (top_hp_ready[3]&!top_hp_ready[2]
    &!top_hp_ready[1]&!top_lru[1]&!top_lru[0]) | 
                        (top_hp_ready[3]&!top_hp_ready[0]&!top_lru[7]&!top_lru[6]
    &top_lru[5]&top_lru[4]) | 
                        (top_hp_ready[3]&top_lru[7]&top_lru[6]) | 
                        (top_hp_ready[3]&!top_hp_ready[2]
    &!top_hp_ready[1]&!top_hp_ready[0]);

assign top_hp_pick[2] = (!top_hp_ready[3]&top_hp_ready[2]&!top_hp_ready[1]&!top_lru[1]&!top_lru[0]) | 
                        (top_hp_ready[2]&!top_hp_ready[1]&!top_hp_ready[0]&top_lru[1]&top_lru[0]) |
                       (top_hp_ready[2]&!top_hp_ready[0]&top_lru[2]&top_lru[0]) |
                       (!top_hp_ready[3]&top_hp_ready[2]&!top_lru[3]&!top_lru[1]) | 
                       (!top_hp_ready[3]&top_hp_ready[2]&!top_hp_ready[0]&!top_lru[1]&top_lru[0]) |
                       (top_hp_ready[2]&!top_hp_ready[1]&!top_lru[7]&top_lru[6]&top_lru[5]&!top_lru[4]) |
                       (top_hp_ready[2]&top_lru[7]&!top_lru[6]) | 
                       (!top_hp_ready[3]&top_hp_ready[2]&!top_hp_ready[1]&!top_hp_ready[0]);

assign top_hp_pick[1] = (!top_hp_ready[3]&!top_hp_ready[2]&top_hp_ready[1]&!top_lru[1]&!top_lru[0]) |
                       (!top_hp_ready[2]&top_hp_ready[1]&!top_hp_ready[0]&top_lru[1]&top_lru[0]) |
                       (!top_hp_ready[3]&top_hp_ready[1]&!top_lru[2]&!top_lru[0]) |
                       (top_hp_ready[1]&!top_hp_ready[0]&top_lru[3]&top_lru[1]) | 
                       (!top_hp_ready[3]&top_hp_ready[1]&!top_hp_ready[0]&top_lru[1]&!top_lru[0]) |
                       (!top_hp_ready[2]&top_hp_ready[1]&top_lru[7]&!top_lru[6]&!top_lru[5]&top_lru[4]) |
                       (top_hp_ready[1]&!top_lru[7]&top_lru[6]) | 
                       (!top_hp_ready[3]&!top_hp_ready[2]&top_hp_ready[1]&!top_hp_ready[0]);

assign top_hp_pick[0] = (!top_hp_ready[3]&!top_hp_ready[1]&top_hp_ready[0]&top_lru[1]&!top_lru[0]) |
                       (!top_hp_ready[3]&!top_hp_ready[2]&top_hp_ready[0]&!top_lru[1]&top_lru[0]) |
                       (!top_hp_ready[2]&top_hp_ready[0]&top_lru[2]&top_lru[0]) |
                       (!top_hp_ready[1]&top_hp_ready[0]&top_lru[3]&top_lru[1]) | 
                       (!top_hp_ready[2]&!top_hp_ready[1]&top_hp_ready[0]&top_lru[1]&top_lru[0]) |
                       (!top_hp_ready[3]&top_hp_ready[0]&top_lru[7]&top_lru[6]&!top_lru[5]&!top_lru[4]) |
                       (top_hp_ready[0]&!top_lru[7]&!top_lru[6]) | 
                       (!top_hp_ready[3]&!top_hp_ready[2]&!top_hp_ready[1]&top_hp_ready[0]);
assign sel_top_hp   = (~favor_top  &  top_hp_pickready & ~bot_hp_pickready) |
                      ( favor_top  & ~top_hp_pickready & ~bot_hp_pickready) | 
                      ( favor_top  &  top_hp_pickready) ;

assign hp_pick[7:0] = ({8{sel_top_hp}}  & {top_hp_pick[3:0],4'b0000}) |
                      ({8{~sel_top_hp}} & {4'b0000,bot_hp_pick[3:0]}) ;


assign top_fpick[3:0] = fpick[7:4] ;
assign bot_fpick[3:0] = fpick[3:0] ;

// lru is msb pair of the lru vector
assign ntop_lru[7] = (top_fpick[0]&!top_lru[6]&top_lru[5]) |
                        (top_fpick[1]&top_lru[6]&top_lru[5]) |
                        (!top_lru[3]&!top_lru[1]) |
                        (!top_fpick[2]&top_lru[7]&!top_lru[6]) |
                        (!top_fpick[3]&top_lru[7]&top_lru[6]);

assign ntop_lru[6] = (top_fpick[0]&!top_lru[7]&top_lru[4]) |
                        (top_fpick[2]&top_lru[7]&top_lru[4]) |
                        (!top_lru[2]&!top_lru[0]) |
                        (!top_fpick[1]&!top_lru[7]&top_lru[6]) |
                        (!top_fpick[3]&top_lru[7]&top_lru[6]);

assign ntop_lru[5] = (!top_fpick[3]&!top_fpick[0]&top_lru[5]&top_lru[4]&top_lru[2]&top_lru[1]) |
                        (top_fpick[0]&!top_lru[1]&top_lru[0]) |
                        (top_fpick[1]&top_lru[3]&top_lru[1]) |
                        (top_fpick[3]&top_lru[3]&!top_lru[2]&!top_lru[1]) |
                        (top_fpick[0]&!top_lru[7]&top_lru[3]) |
                        (top_fpick[2]&top_lru[3]&top_lru[2]&!top_lru[1]) |
                        (top_fpick[1]&top_lru[3]&!top_lru[0]) |
                        (!top_fpick[2]&!top_fpick[0]&!top_lru[7]&top_lru[5]&!top_lru[4]&top_lru[2]) |
                        (!top_fpick[3]&!top_fpick[1]&!top_lru[7]&top_lru[5]&top_lru[4]&!top_lru[2]) |
                        (!top_fpick[2]&!top_fpick[1]&!top_lru[7]&top_lru[5]&!top_lru[2]&top_lru[0]) |
                        (!top_fpick[3]&!top_fpick[2]&top_lru[5]&!top_lru[1]);

assign ntop_lru[4] = (top_fpick[0]&top_lru[1]&!top_lru[0]) |
                        (top_fpick[2]&top_lru[2]&top_lru[0]) |
                        (!top_fpick[3]&!top_fpick[2]&top_lru[4]&!top_lru[3]&!top_lru[1]) |
                        (top_fpick[3]&!top_lru[3]&top_lru[2]&!top_lru[0]) |
                        (top_fpick[0]&!top_lru[6]&top_lru[2]) |
                        (top_fpick[1]&top_lru[3]&top_lru[2]&!top_lru[0]) |
                        (top_fpick[2]&top_lru[2]&!top_lru[1]) |
                        (!top_fpick[3]&!top_fpick[0]&!top_lru[7]&!top_lru[6]&top_lru[5]&top_lru[4]) |
                        (!top_fpick[1]&!top_fpick[0]&!top_lru[6]&!top_lru[5]&top_lru[4]&top_lru[3]) |
                        (!top_fpick[2]&!top_fpick[1]&!top_lru[6]&top_lru[4]&!top_lru[3]&top_lru[1]) |
                        (!top_fpick[3]&!top_fpick[1]&top_lru[4]&!top_lru[0]);

assign ntop_lru[3] = (top_fpick[3]&top_lru[1]&!top_lru[0]) |
                        (top_fpick[2]&top_lru[1]&top_lru[0]) |
                        (!top_fpick[3]&!top_fpick[2]&!top_fpick[1]&top_lru[3]&!top_lru[0]) |
                        (!top_fpick[3]&!top_fpick[2]&!top_fpick[0]&top_lru[3]&top_lru[0]) |
                        (top_fpick[1]&top_lru[1]) |
                        (top_fpick[0]&top_lru[1]) |
                        (top_lru[3]&top_lru[1]);

assign ntop_lru[2] = (top_fpick[3]&!top_lru[1]&top_lru[0]) |
                        (top_fpick[1]&top_lru[1]&top_lru[0]) |
                        (top_lru[2]&top_lru[0]) |
                        (!top_fpick[3]&!top_fpick[2]&!top_fpick[1]&top_lru[2]&!top_lru[1]) |
                        (!top_fpick[3]&!top_fpick[1]&!top_fpick[0]&top_lru[2]&top_lru[1]) |
                        (top_fpick[2]&top_lru[0]) |
                        (top_fpick[0]&top_lru[0]);

assign ntop_lru[1] = (!top_fpick[1]&!top_fpick[0]&top_lru[1]) |
                        (top_fpick[3]) |
                        (top_fpick[2]);

assign ntop_lru[0] = (!top_fpick[2]&!top_fpick[0]&top_lru[0]) |
                        (top_fpick[3]) |
                        (top_fpick[1]);
assign ntop_lru_in[7:0] = {ntop_lru[7],ntop_lru[6], ntop_lru[5],~ntop_lru[4],
                          ~ntop_lru[3],ntop_lru[2],~ntop_lru[1],~ntop_lru[0]};

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 top_lruf  (
 .scan_in(top_lruf_scanin),
 .scan_out(top_lruf_scanout),
 .l1clk(l1clk_pm1),
 .din  (ntop_lru_in[7:0]),
 .dout (top_lru_out[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign top_lru[7:0] =  {top_lru_out[7],top_lru_out[6], top_lru_out[5],~top_lru_out[4],
                       ~top_lru_out[3],top_lru_out[2],~top_lru_out[1],~top_lru_out[0]};

assign nbot_lru[7] = (bot_fpick[0]&!bot_lru[6]&bot_lru[5]) |
                        (bot_fpick[1]&bot_lru[6]&bot_lru[5]) |
                        (!bot_lru[3]&!bot_lru[1]) |
                        (!bot_fpick[2]&bot_lru[7]&!bot_lru[6]) |
                        (!bot_fpick[3]&bot_lru[7]&bot_lru[6]);

assign nbot_lru[6] = (bot_fpick[0]&!bot_lru[7]&bot_lru[4]) |
                        (bot_fpick[2]&bot_lru[7]&bot_lru[4]) |
                        (!bot_lru[2]&!bot_lru[0]) |
                        (!bot_fpick[1]&!bot_lru[7]&bot_lru[6]) |
                        (!bot_fpick[3]&bot_lru[7]&bot_lru[6]);

assign nbot_lru[5] = (!bot_fpick[3]&!bot_fpick[0]&bot_lru[5]&bot_lru[4]&bot_lru[2]&bot_lru[1]) |
                        (bot_fpick[0]&!bot_lru[1]&bot_lru[0]) |
                        (bot_fpick[1]&bot_lru[3]&bot_lru[1]) |
                        (bot_fpick[3]&bot_lru[3]&!bot_lru[2]&!bot_lru[1]) |
                        (bot_fpick[0]&!bot_lru[7]&bot_lru[3]) |
                        (bot_fpick[2]&bot_lru[3]&bot_lru[2]&!bot_lru[1]) |
                        (bot_fpick[1]&bot_lru[3]&!bot_lru[0]) |
                        (!bot_fpick[2]&!bot_fpick[0]&!bot_lru[7]&bot_lru[5]&!bot_lru[4]&bot_lru[2]) |
                        (!bot_fpick[3]&!bot_fpick[1]&!bot_lru[7]&bot_lru[5]&bot_lru[4]&!bot_lru[2]) |
                        (!bot_fpick[2]&!bot_fpick[1]&!bot_lru[7]&bot_lru[5]&!bot_lru[2]&bot_lru[0]) |
                        (!bot_fpick[3]&!bot_fpick[2]&bot_lru[5]&!bot_lru[1]);

assign nbot_lru[4] = (bot_fpick[0]&bot_lru[1]&!bot_lru[0]) |
                        (bot_fpick[2]&bot_lru[2]&bot_lru[0]) |
                        (!bot_fpick[3]&!bot_fpick[2]&bot_lru[4]&!bot_lru[3]&!bot_lru[1]) |
                        (bot_fpick[3]&!bot_lru[3]&bot_lru[2]&!bot_lru[0]) |
                        (bot_fpick[0]&!bot_lru[6]&bot_lru[2]) |
                        (bot_fpick[1]&bot_lru[3]&bot_lru[2]&!bot_lru[0]) |
                        (bot_fpick[2]&bot_lru[2]&!bot_lru[1]) |
                        (!bot_fpick[3]&!bot_fpick[0]&!bot_lru[7]&!bot_lru[6]&bot_lru[5]&bot_lru[4]) |
                        (!bot_fpick[1]&!bot_fpick[0]&!bot_lru[6]&!bot_lru[5]&bot_lru[4]&bot_lru[3]) |
                        (!bot_fpick[2]&!bot_fpick[1]&!bot_lru[6]&bot_lru[4]&!bot_lru[3]&bot_lru[1]) |
                        (!bot_fpick[3]&!bot_fpick[1]&bot_lru[4]&!bot_lru[0]);

assign nbot_lru[3] = (bot_fpick[3]&bot_lru[1]&!bot_lru[0]) |
                        (bot_fpick[2]&bot_lru[1]&bot_lru[0]) |
                        (!bot_fpick[3]&!bot_fpick[2]&!bot_fpick[1]&bot_lru[3]&!bot_lru[0]) |
                        (!bot_fpick[3]&!bot_fpick[2]&!bot_fpick[0]&bot_lru[3]&bot_lru[0]) |
                        (bot_fpick[1]&bot_lru[1]) |
                        (bot_fpick[0]&bot_lru[1]) |
                        (bot_lru[3]&bot_lru[1]);

assign nbot_lru[2] = (bot_fpick[3]&!bot_lru[1]&bot_lru[0]) |
                        (bot_fpick[1]&bot_lru[1]&bot_lru[0]) |
                        (bot_lru[2]&bot_lru[0]) |
                        (!bot_fpick[3]&!bot_fpick[2]&!bot_fpick[1]&bot_lru[2]&!bot_lru[1]) |
                        (!bot_fpick[3]&!bot_fpick[1]&!bot_fpick[0]&bot_lru[2]&bot_lru[1]) |
                        (bot_fpick[2]&bot_lru[0]) |
                        (bot_fpick[0]&bot_lru[0]);

assign nbot_lru[1] = (!bot_fpick[1]&!bot_fpick[0]&bot_lru[1]) | (bot_fpick[3]) | (bot_fpick[2]);

assign nbot_lru[0] = (!bot_fpick[2]&!bot_fpick[0]&bot_lru[0]) | (bot_fpick[3]) | (bot_fpick[1]);

assign nbot_lru_in[7:0] = {nbot_lru[7],nbot_lru[6], nbot_lru[5],~nbot_lru[4],
                          ~nbot_lru[3],nbot_lru[2],~nbot_lru[1],~nbot_lru[0]}; 
ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 bot_lruf  (
 .scan_in(bot_lruf_scanin),
 .scan_out(bot_lruf_scanout),
 .l1clk(l1clk_pm1),
 .din  (nbot_lru_in[7:0]),
 .dout (bot_lru_out[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign bot_lru[7:0] = {bot_lru_out[7],bot_lru_out[6], bot_lru_out[5],~bot_lru_out[4],
                      ~bot_lru_out[3],bot_lru_out[2],~bot_lru_out[1],~bot_lru_out[0]};
////////////////////////////////////////////////////////////
// Manage the favor bit.                                  //
////////////////////////////////////////////////////////////
assign set_favor_top = |bot_fpick[3:0] | favor_top ; 
assign reset_favor_top = |top_fpick[3:0] ;
assign next_favor_top = set_favor_top & ~reset_favor_top ;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 favor_top_reg  (
 .scan_in(favor_top_reg_scanin),
 .scan_out(favor_top_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_favor_top),
 .dout (favor_top),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_curr_fetch_f_bf[7:0]  =  hp_pick[7:0]  ;


ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 curr_fetch_thr_f_reg  (
 .scan_in(curr_fetch_thr_f_reg_scanin),
 .scan_out(curr_fetch_thr_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_curr_fetch_f_bf[7:0]),
 .dout (ftp_curr_fetch_thr_f[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
 
assign ftu_curr_fetch_thr_f[7:0] = ftp_curr_fetch_thr_f[7:0] ;


ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 curr_fetch_thr_c_reg  (
 .scan_in(curr_fetch_thr_c_reg_scanin),
 .scan_out(curr_fetch_thr_c_reg_scanout),
 .l1clk(l1clk),
 .din  (ftp_curr_fetch_thr_f[7:0]),
 .dout (ftp_curr_fetch_thr_c[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);


assign ftp_fetch_thr_q_f[0] = ftp_curr_fetch_thr_f[0] & ftp_fetch_v_dup_f; 
assign ftp_fetch_thr_q_f[1] = ftp_curr_fetch_thr_f[1] & ftp_fetch_v_dup_f; 
assign ftp_fetch_thr_q_f[2] = ftp_curr_fetch_thr_f[2] & ftp_fetch_v_dup_f; 
assign ftp_fetch_thr_q_f[3] = ftp_curr_fetch_thr_f[3] & ftp_fetch_v_dup_f; 
assign ftp_fetch_thr_q_f[4] = ftp_curr_fetch_thr_f[4] & ftp_fetch_v_dup_f; 
assign ftp_fetch_thr_q_f[5] = ftp_curr_fetch_thr_f[5] & ftp_fetch_v_dup_f; 
assign ftp_fetch_thr_q_f[6] = ftp_curr_fetch_thr_f[6] & ftp_fetch_v_dup_f; 
assign ftp_fetch_thr_q_f[7] = ftp_curr_fetch_thr_f[7] & ftp_fetch_v_dup_f; 

////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////

assign next_ftp_fill_req_q = (cmu_any_data_ready & ~cmu_any_un_cacheable ) ;

////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 inv_line_reg  (
 .scan_in(inv_line_reg_scanin),
 .scan_out(inv_line_reg_scanout),
 .l1clk( l1clk                                                            ),
 .din  (cmu_icache_invalidate),
 .dout (inv_line_bf),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Generate valid fetch signals.                                      //
////////////////////////////////////////////////////////////////////////
assign next_fill_req =  cmu_any_data_ready ; 
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 fill_req_bf_reg  (
 .scan_in(fill_req_bf_reg_scanin),
 .scan_out(fill_req_bf_reg_scanout),
 .l1clk(l1clk),
 .din  (next_fill_req),
 .dout (ftp_fill_req_bf),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
assign asi_rd_request = asi_ic_rd_req |    asi_tg_rd_req  | asi_itd_rd_req |   
                       asi_itt_rd_req |    asi_ith_det_req;

assign next_rd_is_first = (asi_rd_request     & ~wr_request_pending)  |
                          (rd_request_pending & ~wr_request_pending & ~ftp_asi_rd_done)	 |
                          (asi_rd_is_first    & ~ftp_asi_rd_done);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 rd_is_first_reg  (
        .scan_in(rd_is_first_reg_scanin),
        .scan_out(rd_is_first_reg_scanout),
        .l1clk  (l1clk),
        .din    (next_rd_is_first),
        .dout   (asi_rd_is_first),
  .siclk(siclk),
  .soclk(soclk)
);


assign asi_wr_request = asi_ic_wr_req | asi_tg_wr_req ;
assign next_wr_request_pending = asi_wr_request   | (wr_request_pending    & ~asi_wr_done_in);
assign next_rd_request_pending = asi_rd_request	  | (rd_request_pending	   & ~ftp_asi_rd_done);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_2 wr_request_pending_reg  (
        .scan_in(wr_request_pending_reg_scanin),
        .scan_out(wr_request_pending_reg_scanout),
        .l1clk  (l1clk),
        .din    ({next_wr_request_pending,next_rd_request_pending}),
        .dout   ({wr_request_pending,rd_request_pending}),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_rd_ok =  !wr_request_pending |  asi_rd_is_first;
assign asi_wr_ok =   wr_request_pending & !asi_rd_is_first;


assign next_ic_wr_req = asi_ic_wr_req | (ic_wr_req_ff  & (ftp_fill_req_q_bf | !asi_wr_ok) ) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 ic_wr_req_ff_reg  (
 .scan_in(ic_wr_req_ff_reg_scanin),
 .scan_out(ic_wr_req_ff_reg_scanout),
 .l1clk(l1clk),
 .din  (next_ic_wr_req),
 .dout (ic_wr_req_ff),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_ic_rd_req = asi_ic_rd_req | (ic_rd_req_ff  & (ftp_fill_req_q_bf | !asi_rd_ok)) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 ic_rd_req_ff_reg  (
 .scan_in(ic_rd_req_ff_reg_scanin),
 .scan_out(ic_rd_req_ff_reg_scanout),
 .l1clk(l1clk),
 .din  (next_ic_rd_req),
 .dout (ic_rd_req_ff),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_tg_wr_req = asi_tg_wr_req | (tg_wr_req_ff  & (ftp_fill_req_q_bf | inv_line_bf | !asi_wr_ok)) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 tg_wr_req_ff_reg  (
 .scan_in(tg_wr_req_ff_reg_scanin),
 .scan_out(tg_wr_req_ff_reg_scanout),
 .l1clk(l1clk),
 .din  (next_tg_wr_req),
 .dout (tg_wr_req_ff),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_tg_rd_req = asi_tg_rd_req | (tg_rd_req_ff  & (ftp_fill_req_q_bf | !asi_rd_ok)) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 tg_rd_req_ff_reg  (
 .scan_in(tg_rd_req_ff_reg_scanin),
 .scan_out(tg_rd_req_ff_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_tg_rd_req),
 .dout (tg_rd_req_ff),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_itt_rd_req = asi_itt_rd_req | (itt_rd_req_ff  & (reload | reload_last | !asi_rd_ok)) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 itt_rd_req_ff_reg  (
 .scan_in(itt_rd_req_ff_reg_scanin),
 .scan_out(itt_rd_req_ff_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_itt_rd_req),
 .dout (itt_rd_req_ff),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_itd_rd_req = asi_itd_rd_req | (itd_rd_req_ff  & (reload | reload_last | !asi_rd_ok)) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 itd_rd_req_ff_reg  (
 .scan_in(itd_rd_req_ff_reg_scanin),
 .scan_out(itd_rd_req_ff_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_itd_rd_req),
 .dout (itd_rd_req_ff),
  .siclk(siclk),
  .soclk(soclk)
);

assign next_ith_det_req = asi_ith_det_req | (ith_det_req_ff  & (reload | reload_last | !asi_rd_ok)) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 ith_det_req_ff_reg  (
 .scan_in(ith_det_req_ff_reg_scanin),
 .scan_out(ith_det_req_ff_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_ith_det_req),
 .dout (ith_det_req_ff),
  .siclk(siclk),
  .soclk(soclk)
);


assign next_itlb_probe_req_l = ~(asi_ith_det_req | (ith_det_req_ff  & (reload | reload_last | !asi_rd_ok))) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 itlb_probe_l_reg  (
 .scan_in(itlb_probe_l_reg_scanin),
 .scan_out(itlb_probe_l_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_itlb_probe_req_l),
 .dout (ftp_itlb_probe_req_l),
  .siclk(siclk),
  .soclk(soclk)
);


ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 fill_req_bf_q_reg  (
 .scan_in(fill_req_bf_q_reg_scanin),
 .scan_out(fill_req_bf_q_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_ftp_fill_req_q),
 .dout (ftp_fill_req_q_bf),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_11 mbist_in_reg  (
 .scan_in(mbist_in_reg_scanin),
 .scan_out(mbist_in_reg_scanout),
 .l1clk(l1clk),
 .din  ({mbi_run, mbi_icd_read_en, mbi_ict_read_en, 
         mbi_icd_write_en ,  mbi_ict_write_en,
         mbi_cmpsel[1:0] ,
         mbi_icv_read_en, mbi_icv_write_en, mbi_itb_cam_en_pre,ftp_itb_cam_en_1}),
 .dout ({mbi_run_bf, ftp_mbi_icd_read_en_bf,ftp_mbi_ict_read_en_bf,
         mbi_icd_write_en_bf,mbi_ict_write_en_bf,
         mbi_cmpsel_bf[1:0],
         ftp_mbi_icv_read_en_bf, ftp_mbi_icv_write_en_bf, ftp_itb_cam_en_1,ftp_itb_cam_en_2}),
  .siclk(siclk),
  .soclk(soclk));

assign ftp_sel_icv_mbist_addr = ftp_mbi_icv_read_en_bf | ftp_mbi_icv_write_en_bf ;
assign ftp_ict_data_sel_bf[0] =  ftp_fill_req_q_bf & ~mbi_run_bf; 
assign ftp_ict_data_sel_bf[1] = ~ftp_fill_req_q_bf & ~mbi_run_bf; 
assign ftp_ict_data_sel_bf[2] =  mbi_run_bf ; 

assign ftp_ic_rd_req_bf = mbi_run_bf ? ftp_mbi_icd_read_en_bf  : (ftp_fetch_v_bf | (ic_rd_req_ff & ~ftp_fill_req_q_bf & asi_rd_ok)) ; 
assign ftp_ic_wr_req_bf = mbi_run_bf ? mbi_icd_write_en_bf     : (ftp_fill_req_q_bf | (ic_wr_req_ff & asi_wr_ok)) ; 
assign ftp_ic_wr_ps_en_bf = (mbi_run_bf & mbi_icd_write_en_bf) | (~mbi_run_bf & (ftp_fill_req_q_bf | ic_wr_req_ff)) | ~ifu_ic_pmen; 

assign ftp_tg_rd_req_bf = mbi_run_bf ? ftp_mbi_ict_read_en_bf  : (ftp_fetch_v_bf | (tg_rd_req_ff & ~ftp_fill_req_q_bf & asi_rd_ok)) ;
assign ftp_tg_wr_req_bf = mbi_run_bf ? mbi_ict_write_en_bf     : (ftp_fill_req_q_bf | (tg_wr_req_ff  & asi_wr_ok & ~inv_line_bf)) ; 
assign ftp_iv_rd_req_bf = mbi_run_bf ? ftp_mbi_icv_read_en_bf  : (ftp_fetch_v_bf | (tg_rd_req_ff & asi_rd_ok & ~ftp_fill_req_q_bf)) ;

assign ftp_tg_clk_en   = mbi_run_bf | tg_rd_req_ff | tg_wr_req_ff | ftp_fill_req_q_bf | ftp_fetch_v_bf | ~ifu_ic_pmen;
 
assign ftp_itt_rd_req_bf  = itt_rd_req_ff  & ~(reload | reload_last) & asi_rd_ok;
assign ftp_itd_rd_req_bf  = itd_rd_req_ff  & ~(reload | reload_last) & asi_rd_ok;
assign ftp_ith_det_req_bf = ith_det_req_ff & ~(reload | reload_last) & asi_rd_ok;
// assign ftp_itlb_probe_req_l = ~ith_det_req_ff ;
assign ftp_itlb_cam_vld_bf = (ftp_fetch_v_bf     & ~ftp_bypass_bf & ~mbi_run_bf) | 
                             (ftp_ith_det_req_bf                  & ~mbi_run_bf) | 
                             (ftp_itb_cam_en_2                    &  mbi_run_bf) ;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 itlb_cam_vld_reg  (
        .scan_in(itlb_cam_vld_reg_scanin),
        .scan_out(itlb_cam_vld_reg_scanout),
        .din    (ftp_itlb_cam_vld_bf ),
        .dout   (ftp_itlb_cam_vld_f ),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//////////////////////////////////////////////////////////////////////
// ITLB bypass control

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 itlb_bypass_lat  (
        .scan_in(itlb_bypass_lat_scanin),
        .scan_out(itlb_bypass_lat_scanout),
        .din    (tlu_itlb_bypass        [7:0] ),
        .dout   (itlb_bypass            [7:0] ),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign pre_bypass_bf[7:0] = ftp_ith_det_req_bf ? 8'h00 :
       itlb_bypass[7:0];


assign ftp_bypass_bf = (| (ftp_itb_fetch_thr_bf[7:0] & pre_bypass_bf[7:0]));
/////////////////////////////////////////////////////////////////////


assign ic_rd_req_done_in = (ic_rd_req_ff & ~ftp_fill_req_q_bf & asi_rd_ok);
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 ic_rd_done_f_reg  (
 .scan_in(ic_rd_done_f_reg_scanin),
 .scan_out(ic_rd_done_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (ic_rd_req_done_in),
 .dout (ic_rd_req_done_f),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 ic_rd_done_c_reg  (
 .scan_in(ic_rd_done_c_reg_scanin),
 .scan_out(ic_rd_done_c_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (ic_rd_req_done_f),
 .dout (ic_rd_req_done_c),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 ic_rd_done_p_reg  (
 .scan_in(ic_rd_done_p_reg_scanin),
 .scan_out(ic_rd_done_p_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (ic_rd_req_done_c),
 .dout (ic_rd_req_done_p),
  .siclk(siclk),
  .soclk(soclk)
);

assign ic_wr_req_done_in = (ic_wr_req_ff & ~ftp_fill_req_q_bf & asi_wr_ok);
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 ic_wr_done_f_reg  (
 .scan_in(ic_wr_done_f_reg_scanin),
 .scan_out(ic_wr_done_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (ic_wr_req_done_in),
 .dout (ic_wr_req_done_f),
  .siclk(siclk),
  .soclk(soclk)
);

assign ftp_asi_ic_rd_done     = ic_rd_req_done_p ;
assign ftp_asi_ic_wr_done     = ic_wr_req_done_f ;  

assign tg_rd_req_done_in = (tg_rd_req_ff & ~ftp_fill_req_q_bf & asi_rd_ok);
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 tg_rd_done_f_reg  (
 .scan_in(tg_rd_done_f_reg_scanin),
 .scan_out(tg_rd_done_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (tg_rd_req_done_in),
 .dout (tg_rd_req_done_f),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 tg_rd_done_c_reg  (
 .scan_in(tg_rd_done_c_reg_scanin),
 .scan_out(tg_rd_done_c_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (tg_rd_req_done_f),
 .dout (tg_rd_req_done_c),
  .siclk(siclk),
  .soclk(soclk)
);


assign tg_wr_req_done_in = (tg_wr_req_ff & ~(ftp_fill_req_q_bf | inv_line_bf) & asi_wr_ok);
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 tg_wr_done_f_reg  (
 .scan_in(tg_wr_done_f_reg_scanin),
 .scan_out(tg_wr_done_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (tg_wr_req_done_in),
 .dout (tg_wr_req_done_f),
  .siclk(siclk),
  .soclk(soclk)
);

assign ftp_asi_tg_rd_done     = tg_rd_req_done_c ;
assign ftp_asi_tg_wr_done     = tg_wr_req_done_f ;  
assign ftp_asi_tg_wr_req_hold = tg_wr_req_ff ;  

assign it_rd_req_done_in = ((itt_rd_req_ff | itd_rd_req_ff | ith_det_req_ff) & ~(reload | reload_last) & asi_rd_ok);
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 it_rd_done_f_reg  (
 .scan_in(it_rd_done_f_reg_scanin),
 .scan_out(it_rd_done_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (it_rd_req_done_in),
 .dout (it_rd_req_done_f),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 it_rd_done_c_reg  (
 .scan_in(it_rd_done_c_reg_scanin),
 .scan_out(it_rd_done_c_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (it_rd_req_done_f),
 .dout (it_rd_req_done_c),
  .siclk(siclk),
  .soclk(soclk)
);
                           
assign asi_rd_done_in = ftp_asi_ic_rd_done | ftp_asi_tg_rd_done | ftp_asi_it_rd_done_p ;
assign asi_wr_done_in = ftp_asi_ic_wr_done | ftp_asi_tg_wr_done;


ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 asi_rd_done_reg  (
        .scan_in(asi_rd_done_reg_scanin),
        .scan_out(asi_rd_done_reg_scanout),
        .l1clk  (l1clk),
        .din( asi_rd_done_in),
        .dout( ftp_asi_rd_done),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 asi_wr_done_reg  (
        .scan_in(asi_wr_done_reg_scanin),
        .scan_out(asi_wr_done_reg_scanout),
        .l1clk  (l1clk),
        .din( asi_wr_done_in),
        .dout( ftp_asi_wr_done),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 asi_it_rd_done_reg  (
        .scan_in(asi_it_rd_done_reg_scanin),
        .scan_out(asi_it_rd_done_reg_scanout),
        .l1clk  (l1clk),
        .din    (ftp_asi_it_rd_done),
        .dout   (ftp_asi_it_rd_done_p),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////////
assign next_sel_mbist_itb_cycle0 = mbi_run_bf & ~mbi_cmpsel_bf[1] & ~mbi_cmpsel_bf[0];
assign next_sel_mbist_itb_cycle1 = mbi_run_bf & ~mbi_cmpsel_bf[1] &  mbi_cmpsel_bf[0];
assign next_sel_mbist_itb_cycle2 = mbi_run_bf &  mbi_cmpsel_bf[1] & ~mbi_cmpsel_bf[0];
assign next_sel_mbist_itb_cycle3 = mbi_run_bf &  mbi_cmpsel_bf[1] &  mbi_cmpsel_bf[0];

assign next_sel_itlb_tag = (itt_rd_req_ff  & ~(reload | reload_last) & asi_rd_ok) ; 
ifu_ftu_ftp_ctl_msff_ctl_macro__width_5 itlb_sel_tag_f_reg  (
 .scan_in(itlb_sel_tag_f_reg_scanin),
 .scan_out(itlb_sel_tag_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  ({next_sel_itlb_tag,next_sel_mbist_itb_cycle0,next_sel_mbist_itb_cycle1,
         next_sel_mbist_itb_cycle2, next_sel_mbist_itb_cycle3}),
 .dout ({ftp_sel_itlb_tag_f,ftp_sel_mbist_itb_cycle0,ftp_sel_mbist_itb_cycle1,
         ftp_sel_mbist_itb_cycle2,ftp_sel_mbist_itb_cycle3}),
  .siclk(siclk),
  .soclk(soclk)
);
assign next_sel_itlb_data = (itd_rd_req_ff  & ~(reload | reload_last) & asi_rd_ok) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 itlb_sel_data_f_reg  (
 .scan_in(itlb_sel_data_f_reg_scanin),
 .scan_out(itlb_sel_data_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_sel_itlb_data),
 .dout (ftp_sel_itlb_data_f),
  .siclk(siclk),
  .soclk(soclk)
);
assign next_sel_itlb_pa = (ith_det_req_ff  & ~(reload | reload_last)  & asi_rd_ok) ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 itlb_sel_pa_f_reg  (
 .scan_in(itlb_sel_pa_f_reg_scanin),
 .scan_out(itlb_sel_pa_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_sel_itlb_pa),
 .dout (ftp_sel_itlb_pa_f),
  .siclk(siclk),
  .soclk(soclk)
);

assign sel_itlb_tag_cntx0_f = ftp_sel_itlb_tag_f &  asi_sel_cntx_0 ;
assign sel_itlb_tag_cntx1_f = ftp_sel_itlb_tag_f & ~asi_sel_cntx_0 ;
ifu_ftu_ftp_ctl_msff_ctl_macro__width_4 itlb_sel_c_reg  (
 .scan_in(itlb_sel_c_reg_scanin),
 .scan_out(itlb_sel_c_reg_scanout),
 .l1clk(l1clk_pm1 ),
 .din  ({sel_itlb_tag_cntx0_f,sel_itlb_tag_cntx1_f,ftp_sel_itlb_data_f,ftp_sel_itlb_pa_f}),
 .dout ({ftp_sel_itlb_tag_cntx0_c,ftp_sel_itlb_tag_cntx1_c, ftp_sel_itlb_data_c,ftp_sel_itlb_pa_c}),
  .siclk(siclk),
  .soclk(soclk)
);

assign ftp_asi_it_rd_done     = it_rd_req_done_c ;

assign ftp_asi_mbist_access_bf = ic_wr_req_done_in | ic_rd_req_done_in | mbi_run_bf;

////////////////////////////////////////////////////////////////////////////////////
/// Killing the instructions can be moved to F and C stage for timing reasons later
////////////////////////////////////////////////////////////////////////////////////

assign trap_thread_g0[0] = ~tlu_trap_0_tid[1] & ~tlu_trap_0_tid[0] ;
assign trap_thread_g0[1] = ~tlu_trap_0_tid[1] &  tlu_trap_0_tid[0] ;
assign trap_thread_g0[2] =  tlu_trap_0_tid[1] & ~tlu_trap_0_tid[0] ;
assign trap_thread_g0[3] =  tlu_trap_0_tid[1] &  tlu_trap_0_tid[0] ;

assign trap_thread_g1[0] = ~tlu_trap_1_tid[1] & ~tlu_trap_1_tid[0] ;
assign trap_thread_g1[1] = ~tlu_trap_1_tid[1] &  tlu_trap_1_tid[0] ;
assign trap_thread_g1[2] =  tlu_trap_1_tid[1] & ~tlu_trap_1_tid[0] ;
assign trap_thread_g1[3] =  tlu_trap_1_tid[1] &  tlu_trap_1_tid[0] ;

assign thr0_trap_pcaddr_is_valid_bf  = tlu_trap_pc_0_valid  & trap_thread_g0[0] ;
assign thr1_trap_pcaddr_is_valid_bf  = tlu_trap_pc_0_valid  & trap_thread_g0[1] ;
assign thr2_trap_pcaddr_is_valid_bf  = tlu_trap_pc_0_valid  & trap_thread_g0[2] ;
assign thr3_trap_pcaddr_is_valid_bf  = tlu_trap_pc_0_valid  & trap_thread_g0[3] ;

assign thr4_trap_pcaddr_is_valid_bf  = tlu_trap_pc_1_valid  & trap_thread_g1[0] ;
assign thr5_trap_pcaddr_is_valid_bf  = tlu_trap_pc_1_valid  & trap_thread_g1[1] ;
assign thr6_trap_pcaddr_is_valid_bf  = tlu_trap_pc_1_valid  & trap_thread_g1[2] ;
assign thr7_trap_pcaddr_is_valid_bf  = tlu_trap_pc_1_valid  & trap_thread_g1[3] ;

assign load_flush_w[0] = dec_load_flush_w[0] & tid_dec_w[0] ;
assign load_flush_w[1] = dec_load_flush_w[0] & tid_dec_w[1] ;
assign load_flush_w[2] = dec_load_flush_w[0] & tid_dec_w[2] ;
assign load_flush_w[3] = dec_load_flush_w[0] & tid_dec_w[3] ;
assign load_flush_w[4] = dec_load_flush_w[1] & tid_dec_w[4] ;
assign load_flush_w[5] = dec_load_flush_w[1] & tid_dec_w[5] ;
assign load_flush_w[6] = dec_load_flush_w[1] & tid_dec_w[6] ;
assign load_flush_w[7] = dec_load_flush_w[1] & tid_dec_w[7] ;

assign ftp_thr0_trprdpc_sel_bf[0] =  thr0_trap_pcaddr_is_valid_bf ;
assign ftp_thr0_trprdpc_sel_bf[1] =  load_flush_w[0] & ~thr0_trap_pcaddr_is_valid_bf;
assign ftp_thr0_trprdpc_sel_bf[2] = ~load_flush_w[0] & ~thr0_trap_pcaddr_is_valid_bf ;

assign ftp_thr1_trprdpc_sel_bf[0] =  thr1_trap_pcaddr_is_valid_bf ;
assign ftp_thr1_trprdpc_sel_bf[1] =  load_flush_w[1] & ~thr1_trap_pcaddr_is_valid_bf;
assign ftp_thr1_trprdpc_sel_bf[2] = ~load_flush_w[1] & ~thr1_trap_pcaddr_is_valid_bf ;

assign ftp_thr2_trprdpc_sel_bf[0] =  thr2_trap_pcaddr_is_valid_bf ;
assign ftp_thr2_trprdpc_sel_bf[1] =  load_flush_w[2] & ~thr2_trap_pcaddr_is_valid_bf;
assign ftp_thr2_trprdpc_sel_bf[2] = ~load_flush_w[2] & ~thr2_trap_pcaddr_is_valid_bf ;

assign ftp_thr3_trprdpc_sel_bf[0] =  thr3_trap_pcaddr_is_valid_bf ;
assign ftp_thr3_trprdpc_sel_bf[1] =  load_flush_w[3] & ~thr3_trap_pcaddr_is_valid_bf;
assign ftp_thr3_trprdpc_sel_bf[2] = ~load_flush_w[3] & ~thr3_trap_pcaddr_is_valid_bf ;


assign ftp_thr4_trprdpc_sel_bf[0] =  thr4_trap_pcaddr_is_valid_bf ;
assign ftp_thr4_trprdpc_sel_bf[1] =  load_flush_w[4] & ~thr4_trap_pcaddr_is_valid_bf;
assign ftp_thr4_trprdpc_sel_bf[2] = ~load_flush_w[4] & ~thr4_trap_pcaddr_is_valid_bf ;

assign ftp_thr5_trprdpc_sel_bf[0] =  thr5_trap_pcaddr_is_valid_bf ;
assign ftp_thr5_trprdpc_sel_bf[1] =  load_flush_w[5] & ~thr5_trap_pcaddr_is_valid_bf;
assign ftp_thr5_trprdpc_sel_bf[2] = ~load_flush_w[5] & ~thr5_trap_pcaddr_is_valid_bf ;

assign ftp_thr6_trprdpc_sel_bf[0] =  thr6_trap_pcaddr_is_valid_bf ;
assign ftp_thr6_trprdpc_sel_bf[1] =  load_flush_w[6] & ~thr6_trap_pcaddr_is_valid_bf;
assign ftp_thr6_trprdpc_sel_bf[2] = ~load_flush_w[6] & ~thr6_trap_pcaddr_is_valid_bf ;

assign ftp_thr7_trprdpc_sel_bf[0] =  thr7_trap_pcaddr_is_valid_bf ;
assign ftp_thr7_trprdpc_sel_bf[1] =  load_flush_w[7] & ~thr7_trap_pcaddr_is_valid_bf;
assign ftp_thr7_trprdpc_sel_bf[2] = ~load_flush_w[7] & ~thr7_trap_pcaddr_is_valid_bf ;


assign thr0_red_no_br_bf = thr0_trap_pcaddr_is_valid_bf | load_flush_w[0]  ;
assign thr1_red_no_br_bf = thr1_trap_pcaddr_is_valid_bf | load_flush_w[1]  ;
assign thr2_red_no_br_bf = thr2_trap_pcaddr_is_valid_bf | load_flush_w[2]  ;
assign thr3_red_no_br_bf = thr3_trap_pcaddr_is_valid_bf | load_flush_w[3]  ;
assign thr4_red_no_br_bf = thr4_trap_pcaddr_is_valid_bf | load_flush_w[4]  ;
assign thr5_red_no_br_bf = thr5_trap_pcaddr_is_valid_bf | load_flush_w[5]  ;
assign thr6_red_no_br_bf = thr6_trap_pcaddr_is_valid_bf | load_flush_w[6]  ;
assign thr7_red_no_br_bf = thr7_trap_pcaddr_is_valid_bf | load_flush_w[7]  ;


ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 thrx_redirect_reg  (
 .scan_in(thrx_redirect_reg_scanin),
 .scan_out(thrx_redirect_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  ({thr7_red_no_br_bf,thr6_red_no_br_bf,thr5_red_no_br_bf,thr4_red_no_br_bf,
         thr3_red_no_br_bf,thr2_red_no_br_bf,thr1_red_no_br_bf,thr0_red_no_br_bf}),
 .dout ({thr7_redirect_part_bf,thr6_redirect_part_bf,thr5_redirect_part_bf,thr4_redirect_part_bf,
         thr3_redirect_part_bf,thr2_redirect_part_bf,thr1_redirect_part_bf,thr0_redirect_part_bf}),
  .siclk(siclk),
  .soclk(soclk));

assign thr0_redirect_bf = thr0_redirect_part_bf | ftp_tlu_flush_f[0] | thr0_br_taken_ff ;
assign thr1_redirect_bf = thr1_redirect_part_bf | ftp_tlu_flush_f[1] | thr1_br_taken_ff ;
assign thr2_redirect_bf = thr2_redirect_part_bf | ftp_tlu_flush_f[2] | thr2_br_taken_ff ;
assign thr3_redirect_bf = thr3_redirect_part_bf | ftp_tlu_flush_f[3] | thr3_br_taken_ff ;
assign thr4_redirect_bf = thr4_redirect_part_bf | ftp_tlu_flush_f[4] | thr4_br_taken_ff ;
assign thr5_redirect_bf = thr5_redirect_part_bf | ftp_tlu_flush_f[5] | thr5_br_taken_ff ;
assign thr6_redirect_bf = thr6_redirect_part_bf | ftp_tlu_flush_f[6] | thr6_br_taken_ff ;
assign thr7_redirect_bf = thr7_redirect_part_bf | ftp_tlu_flush_f[7] | thr7_br_taken_ff ;


assign kill_fetch_fv_bf     =  (((thr0_red_no_br_bf | agc_thr0_micro_flush_unq_c  )
                                                    & ftp_curr_fetch_thr_bf[0])|
                                ((thr1_red_no_br_bf | agc_thr1_micro_flush_unq_c  )
                                                    & ftp_curr_fetch_thr_bf[1])|
                                ((thr2_red_no_br_bf | agc_thr2_micro_flush_unq_c  )
                                                    & ftp_curr_fetch_thr_bf[2])|
                                ((thr3_red_no_br_bf | agc_thr3_micro_flush_unq_c  )
                                                    & ftp_curr_fetch_thr_bf[3])|
                                ((thr4_red_no_br_bf | agc_thr4_micro_flush_unq_c  )
                                                    & ftp_curr_fetch_thr_bf[4])|
                                ((thr5_red_no_br_bf | agc_thr5_micro_flush_unq_c  )
                                                    & ftp_curr_fetch_thr_bf[5])|
                                ((thr6_red_no_br_bf | agc_thr6_micro_flush_unq_c  )
                                                    & ftp_curr_fetch_thr_bf[6])|
                                ((thr7_red_no_br_bf | agc_thr7_micro_flush_unq_c  )
                                                    & ftp_curr_fetch_thr_bf[7])) ;

assign ftp_fetch_v_bf         = (hp_pickready  )  ; 


assign next_fetch_fv_unq_bf = ((hp_pickready  & ~kill_fetch_fv_bf)  );


ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 fetch_v_f_reg  (
 .scan_in(fetch_v_f_reg_scanin),
 .scan_out(fetch_v_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_fetch_fv_unq_bf),
 .dout (ftp_fetch_v_unq_f),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 fetch_v_f_dup_reg  (
 .scan_in(fetch_v_f_dup_reg_scanin),
 .scan_out(fetch_v_f_dup_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_fetch_fv_unq_bf),
 .dout (ftp_fetch_v_unq_dup_f),
  .siclk(siclk),
  .soclk(soclk)
);


assign br_redirect_disqual = (br_taken_ff[0]  & br0_matches_curr_f)     | 
                             (br_taken_ff[1]  & br1_matches_curr_f)     ; 

assign br_redirect_dup_disqual = (br_taken_ff[0]  & br0_matches_curr_f)     | 
                             (br_taken_ff[1]  & br1_matches_curr_f)     ; 

assign ftp_fetch_v_dup_f = ftp_fetch_v_unq_dup_f & ~br_redirect_dup_disqual; 
assign ftp_fetch_v_f     = ftp_fetch_v_unq_f & ~br_redirect_disqual; 

assign next_fetch_v_c_f = ftp_fetch_v_dup_f ; // 
ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 fetch_v_c_reg  (
 .scan_in(fetch_v_c_reg_scanin),
 .scan_out(fetch_v_c_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (next_fetch_v_c_f),
 .dout (ftp_fetch_v_c_unq),
  .siclk(siclk),
  .soclk(soclk)
);

assign ftp_fetch_v_c = ftp_fetch_v_c_unq & ~agc_kill_fetch_cv_c ;
assign next_enabled_thread[7:0] =  spc_core_running_status[7:0] ;  
ifu_ftu_ftp_ctl_msff_ctl_macro__width_10 enabled_thr_reg  (
 .scan_in(enabled_thr_reg_scanin),
 .scan_out(enabled_thr_reg_scanout),
 .l1clk(l1clk),
 .din  ({next_enabled_thread[7:0],lsu_ifu_ftu_pmen,lsu_ic_pmen}),
 .dout ({enabled_threads[7:0],ifu_ftu_pmen,ifu_ic_pmen}),
  .siclk(siclk),
  .soclk(soclk)
);


assign ftp_any_thr_clken = |enabled_threads[7:0] | (~ifu_ftu_pmen) | mbi_run_bf;

 
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
assign thr0_br_taken_ff = br_taken_ff[0] & ~tid0_m[1] & ~tid0_m[0] ; 
assign thr1_br_taken_ff = br_taken_ff[0] & ~tid0_m[1] &  tid0_m[0] ; 
assign thr2_br_taken_ff = br_taken_ff[0] &  tid0_m[1] & ~tid0_m[0] ; 
assign thr3_br_taken_ff = br_taken_ff[0] &  tid0_m[1] &  tid0_m[0] ; 
assign thr4_br_taken_ff = br_taken_ff[1] & ~tid1_m[1] & ~tid1_m[0] ; 
assign thr5_br_taken_ff = br_taken_ff[1] & ~tid1_m[1] &  tid1_m[0] ; 
assign thr6_br_taken_ff = br_taken_ff[1] &  tid1_m[1] & ~tid1_m[0] ; 
assign thr7_br_taken_ff = br_taken_ff[1] &  tid1_m[1] &  tid1_m[0] ; 


assign ftp_thr0_sel_br_bf = br_taken_ff[0] & ~tid0_m[1] & ~tid0_m[0] ; 
assign ftp_thr1_sel_br_bf = br_taken_ff[0] & ~tid0_m[1] &  tid0_m[0] ; 
assign ftp_thr2_sel_br_bf = br_taken_ff[0] &  tid0_m[1] & ~tid0_m[0] ; 
assign ftp_thr3_sel_br_bf = br_taken_ff[0] &  tid0_m[1] &  tid0_m[0] ; 

assign ftp_thr4_sel_br_bf = br_taken_ff[1] & ~tid1_m[1] & ~tid1_m[0] ; 
assign ftp_thr5_sel_br_bf = br_taken_ff[1] & ~tid1_m[1] &  tid1_m[0] ; 
assign ftp_thr6_sel_br_bf = br_taken_ff[1] &  tid1_m[1] & ~tid1_m[0] ; 
assign ftp_thr7_sel_br_bf = br_taken_ff[1] &  tid1_m[1] &  tid1_m[0] ; 


assign br_room_reset[0] = thr0_br_taken_ff & ~ftp_curr_fetch_thr_bf[0]; 
assign br_room_reset[1] = thr1_br_taken_ff & ~ftp_curr_fetch_thr_bf[1]; 
assign br_room_reset[2] = thr2_br_taken_ff & ~ftp_curr_fetch_thr_bf[2]; 
assign br_room_reset[3] = thr3_br_taken_ff & ~ftp_curr_fetch_thr_bf[3]; 
assign br_room_reset[4] = thr4_br_taken_ff & ~ftp_curr_fetch_thr_bf[4]; 
assign br_room_reset[5] = thr5_br_taken_ff & ~ftp_curr_fetch_thr_bf[5]; 
assign br_room_reset[6] = thr6_br_taken_ff & ~ftp_curr_fetch_thr_bf[6]; 
assign br_room_reset[7] = thr7_br_taken_ff & ~ftp_curr_fetch_thr_bf[7]; 
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Generate buffer space available, taking into consideration any     //
// fetches in progress.                                               //
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////
// Room should refelect the actual data in flight including by_pass  that will be at C//
// two cycles from now.                                                               //
////////////////////////////////////////////////////////////////////////////////////////
assign ftp_thr0_fetch_v_wo_br_bf =  ftp_curr_fetch_thr_bf[0] | thr0_by_pass_2_cycles_at_c;
assign ftp_thr1_fetch_v_wo_br_bf =  ftp_curr_fetch_thr_bf[1] | thr1_by_pass_2_cycles_at_c;
assign ftp_thr2_fetch_v_wo_br_bf =  ftp_curr_fetch_thr_bf[2] | thr2_by_pass_2_cycles_at_c;
assign ftp_thr3_fetch_v_wo_br_bf =  ftp_curr_fetch_thr_bf[3] | thr3_by_pass_2_cycles_at_c;
assign ftp_thr4_fetch_v_wo_br_bf =  ftp_curr_fetch_thr_bf[4] | thr4_by_pass_2_cycles_at_c;
assign ftp_thr5_fetch_v_wo_br_bf =  ftp_curr_fetch_thr_bf[5] | thr5_by_pass_2_cycles_at_c;
assign ftp_thr6_fetch_v_wo_br_bf =  ftp_curr_fetch_thr_bf[6] | thr6_by_pass_2_cycles_at_c;
assign ftp_thr7_fetch_v_wo_br_bf =  ftp_curr_fetch_thr_bf[7] | thr7_by_pass_2_cycles_at_c;


////////////////////////////////////////////////////////////////////////////////////////
// Room should refelect the actual data in flight including by_pass  that will be at C//
// next cycle.                                                                        //
////////////////////////////////////////////////////////////////////////////////////////
assign ftp_thr0_fetch_v_f = (ftp_curr_fetch_thr_f[0] & ftp_fetch_v_dup_f ) | (thr0_by_pass_next_cycle_at_c); 
assign ftp_thr1_fetch_v_f = (ftp_curr_fetch_thr_f[1] & ftp_fetch_v_dup_f ) | (thr1_by_pass_next_cycle_at_c); 
assign ftp_thr2_fetch_v_f = (ftp_curr_fetch_thr_f[2] & ftp_fetch_v_dup_f ) | (thr2_by_pass_next_cycle_at_c);
assign ftp_thr3_fetch_v_f = (ftp_curr_fetch_thr_f[3] & ftp_fetch_v_dup_f ) | (thr3_by_pass_next_cycle_at_c);
assign ftp_thr4_fetch_v_f = (ftp_curr_fetch_thr_f[4] & ftp_fetch_v_dup_f ) | (thr4_by_pass_next_cycle_at_c);
assign ftp_thr5_fetch_v_f = (ftp_curr_fetch_thr_f[5] & ftp_fetch_v_dup_f ) | (thr5_by_pass_next_cycle_at_c);
assign ftp_thr6_fetch_v_f = (ftp_curr_fetch_thr_f[6] & ftp_fetch_v_dup_f ) | (thr6_by_pass_next_cycle_at_c);
assign ftp_thr7_fetch_v_f = (ftp_curr_fetch_thr_f[7] & ftp_fetch_v_dup_f ) | (thr7_by_pass_next_cycle_at_c);
////////////////////////////////////////////////////////////////////////////////////////
// Room should refelect the actual data in flight including by_pass at C              //
////////////////////////////////////////////////////////////////////////////////////////
assign ftp_thr0_fetch_v_c = (ftp_curr_fetch_thr_c[0] & ftp_fetch_v_c & ~ftp_tlu_flush_f[0]) | thr0_by_pass_is_at_c ; 
assign ftp_thr1_fetch_v_c = (ftp_curr_fetch_thr_c[1] & ftp_fetch_v_c & ~ftp_tlu_flush_f[1]) | thr1_by_pass_is_at_c ;
assign ftp_thr2_fetch_v_c = (ftp_curr_fetch_thr_c[2] & ftp_fetch_v_c & ~ftp_tlu_flush_f[2]) | thr2_by_pass_is_at_c ;
assign ftp_thr3_fetch_v_c = (ftp_curr_fetch_thr_c[3] & ftp_fetch_v_c & ~ftp_tlu_flush_f[3]) | thr3_by_pass_is_at_c ;
assign ftp_thr4_fetch_v_c = (ftp_curr_fetch_thr_c[4] & ftp_fetch_v_c & ~ftp_tlu_flush_f[4]) | thr4_by_pass_is_at_c ;
assign ftp_thr5_fetch_v_c = (ftp_curr_fetch_thr_c[5] & ftp_fetch_v_c & ~ftp_tlu_flush_f[5]) | thr5_by_pass_is_at_c ;
assign ftp_thr6_fetch_v_c = (ftp_curr_fetch_thr_c[6] & ftp_fetch_v_c & ~ftp_tlu_flush_f[6]) | thr6_by_pass_is_at_c ;
assign ftp_thr7_fetch_v_c = (ftp_curr_fetch_thr_c[7] & ftp_fetch_v_c & ~ftp_tlu_flush_f[7]) | thr7_by_pass_is_at_c ;


assign thr0_is_empty_c = ibu_empty[0] ;
assign thr1_is_empty_c = ibu_empty[1] ;
assign thr2_is_empty_c = ibu_empty[2] ;
assign thr3_is_empty_c = ibu_empty[3] ;
assign thr4_is_empty_c = ibu_empty[4] ;
assign thr5_is_empty_c = ibu_empty[5] ;
assign thr6_is_empty_c = ibu_empty[6] ;
assign thr7_is_empty_c = ibu_empty[7] ;


assign thr0_room_4ormore    = ibu_room_4ormore[0] ;
assign thr1_room_4ormore    = ibu_room_4ormore[1] ;
assign thr2_room_4ormore    = ibu_room_4ormore[2] ;
assign thr3_room_4ormore    = ibu_room_4ormore[3] ;
assign thr4_room_4ormore    = ibu_room_4ormore[4] ;
assign thr5_room_4ormore    = ibu_room_4ormore[5] ;
assign thr6_room_4ormore    = ibu_room_4ormore[6] ;
assign thr7_room_4ormore    = ibu_room_4ormore[7] ;


assign ftp_thr0_room_is_less_t_3 = ((!thr0_is_empty_c     & !thr0_room_4ormore)  | 
                                    ( ftp_thr0_fetch_v_wo_br_bf     &  ftp_thr0_fetch_v_f & ftp_thr0_fetch_v_c) |
                                    ( ftp_thr0_fetch_v_wo_br_bf     &  ftp_thr0_fetch_v_f & thr0_is_empty_c ) | 
                                    ( ftp_thr0_fetch_v_wo_br_bf     &  ftp_thr0_fetch_v_c & thr0_is_empty_c ) | 
                                    ( ftp_thr0_fetch_v_f  &  ftp_thr0_fetch_v_c & thr0_is_empty_c ) | 
                                    (!thr0_is_empty_c     &  thr0_room_4ormore   &  (ftp_thr0_fetch_v_wo_br_bf ))| 
                                    (!thr0_is_empty_c     &  thr0_room_4ormore   &  ftp_thr0_fetch_v_f) | 
                                    (!thr0_is_empty_c     &  thr0_room_4ormore   &  ftp_thr0_fetch_v_c)) & ~load_flush_w[0] & ~br_room_reset[0];


assign ftp_thr1_room_is_less_t_3 = ((!thr1_is_empty_c     & !thr1_room_4ormore)  | 
                                    ( ftp_thr1_fetch_v_wo_br_bf          &  ftp_thr1_fetch_v_f  & ftp_thr1_fetch_v_c) |
                                    ( ftp_thr1_fetch_v_wo_br_bf          &  ftp_thr1_fetch_v_f  & thr1_is_empty_c ) | 
                                    ( ftp_thr1_fetch_v_wo_br_bf          &  ftp_thr1_fetch_v_c  & thr1_is_empty_c ) | 
                                    ( ftp_thr1_fetch_v_f  &  ftp_thr1_fetch_v_c  & thr1_is_empty_c ) | 
                                    (!thr1_is_empty_c     &  thr1_room_4ormore   & (ftp_thr1_fetch_v_wo_br_bf ))| 
                                    (!thr1_is_empty_c     &  thr1_room_4ormore   & ftp_thr1_fetch_v_f) | 
                                    (!thr1_is_empty_c     &  thr1_room_4ormore   & ftp_thr1_fetch_v_c)) & ~load_flush_w[1] & ~br_room_reset[1];


assign ftp_thr2_room_is_less_t_3 = ((!thr2_is_empty_c    & !thr2_room_4ormore)  | 
                                   ( ftp_thr2_fetch_v_wo_br_bf          &  ftp_thr2_fetch_v_f & ftp_thr2_fetch_v_c) |
                                   ( ftp_thr2_fetch_v_wo_br_bf          &  ftp_thr2_fetch_v_f & thr2_is_empty_c ) | 
                                   ( ftp_thr2_fetch_v_wo_br_bf          &  ftp_thr2_fetch_v_c & thr2_is_empty_c ) | 
                                   ( ftp_thr2_fetch_v_f  &  ftp_thr2_fetch_v_c & thr2_is_empty_c ) | 
                                   ( !thr2_is_empty_c    & thr2_room_4ormore  &  (ftp_thr2_fetch_v_wo_br_bf ))| 
                                   ( !thr2_is_empty_c    & thr2_room_4ormore  &  ftp_thr2_fetch_v_f) | 
                                   ( !thr2_is_empty_c    & thr2_room_4ormore  &  ftp_thr2_fetch_v_c)) & ~load_flush_w[2] & ~br_room_reset[2];


assign ftp_thr3_room_is_less_t_3 = ((!thr3_is_empty_c    & !thr3_room_4ormore)  | 
                                   ( ftp_thr3_fetch_v_wo_br_bf          &  ftp_thr3_fetch_v_f & ftp_thr3_fetch_v_c) |
                                   ( ftp_thr3_fetch_v_wo_br_bf          &  ftp_thr3_fetch_v_f & thr3_is_empty_c ) | 
                                   ( ftp_thr3_fetch_v_wo_br_bf          &  ftp_thr3_fetch_v_c & thr3_is_empty_c ) | 
                                   ( ftp_thr3_fetch_v_f  &  ftp_thr3_fetch_v_c & thr3_is_empty_c ) | 
                                   ( !thr3_is_empty_c    & thr3_room_4ormore  &  (ftp_thr3_fetch_v_wo_br_bf ))| 
                                   ( !thr3_is_empty_c    & thr3_room_4ormore  &  ftp_thr3_fetch_v_f) | 
                                   ( !thr3_is_empty_c    & thr3_room_4ormore  &  ftp_thr3_fetch_v_c)) & ~load_flush_w[3] & ~br_room_reset[3];


assign ftp_thr4_room_is_less_t_3 = ((!thr4_is_empty_c    & !thr4_room_4ormore)  | 
                                   ( ftp_thr4_fetch_v_wo_br_bf          &  ftp_thr4_fetch_v_f & ftp_thr4_fetch_v_c) |
                                   ( ftp_thr4_fetch_v_wo_br_bf          &  ftp_thr4_fetch_v_f & thr4_is_empty_c ) | 
                                   ( ftp_thr4_fetch_v_wo_br_bf          &  ftp_thr4_fetch_v_c & thr4_is_empty_c ) | 
                                   ( ftp_thr4_fetch_v_f  &  ftp_thr4_fetch_v_c & thr4_is_empty_c ) | 
                                   ( !thr4_is_empty_c    & thr4_room_4ormore  &  (ftp_thr4_fetch_v_wo_br_bf ))| 
                                   ( !thr4_is_empty_c    & thr4_room_4ormore  &  ftp_thr4_fetch_v_f) | 
                                   ( !thr4_is_empty_c    & thr4_room_4ormore  &  ftp_thr4_fetch_v_c)) & ~load_flush_w[4] & ~br_room_reset[4];


assign ftp_thr5_room_is_less_t_3 = ((!thr5_is_empty_c    & !thr5_room_4ormore)  | 
                                   ( ftp_thr5_fetch_v_wo_br_bf          &  ftp_thr5_fetch_v_f & ftp_thr5_fetch_v_c) |
                                   ( ftp_thr5_fetch_v_wo_br_bf          &  ftp_thr5_fetch_v_f & thr5_is_empty_c ) | 
                                   ( ftp_thr5_fetch_v_wo_br_bf          &  ftp_thr5_fetch_v_c & thr5_is_empty_c ) | 
                                   ( ftp_thr5_fetch_v_f  &  ftp_thr5_fetch_v_c & thr5_is_empty_c ) | 
                                   ( !thr5_is_empty_c    & thr5_room_4ormore  &  (ftp_thr5_fetch_v_wo_br_bf ))| 
                                   ( !thr5_is_empty_c    & thr5_room_4ormore  &  ftp_thr5_fetch_v_f) | 
                                   ( !thr5_is_empty_c    & thr5_room_4ormore  &  ftp_thr5_fetch_v_c)) & ~load_flush_w[5] & ~br_room_reset[5];


assign ftp_thr6_room_is_less_t_3 = ((!thr6_is_empty_c    & !thr6_room_4ormore)  | 
                                   ( ftp_thr6_fetch_v_wo_br_bf          &  ftp_thr6_fetch_v_f & ftp_thr6_fetch_v_c) |
                                   ( ftp_thr6_fetch_v_wo_br_bf          &  ftp_thr6_fetch_v_f & thr6_is_empty_c ) | 
                                   ( ftp_thr6_fetch_v_wo_br_bf          &  ftp_thr6_fetch_v_c & thr6_is_empty_c ) | 
                                   ( ftp_thr6_fetch_v_f  &  ftp_thr6_fetch_v_c & thr6_is_empty_c ) | 
                                   ( !thr6_is_empty_c    & thr6_room_4ormore  &  (ftp_thr6_fetch_v_wo_br_bf ))| 
                                   ( !thr6_is_empty_c    & thr6_room_4ormore  &  ftp_thr6_fetch_v_f) | 
                                   ( !thr6_is_empty_c    & thr6_room_4ormore  &  ftp_thr6_fetch_v_c)) & ~load_flush_w[6] & ~br_room_reset[6];


assign ftp_thr7_room_is_less_t_3 = ((!thr7_is_empty_c    & !thr7_room_4ormore)  | 
                                   ( ftp_thr7_fetch_v_wo_br_bf          &  ftp_thr7_fetch_v_f & ftp_thr7_fetch_v_c) |
                                   ( ftp_thr7_fetch_v_wo_br_bf          &  ftp_thr7_fetch_v_f & thr7_is_empty_c ) | 
                                   ( ftp_thr7_fetch_v_wo_br_bf          &  ftp_thr7_fetch_v_c & thr7_is_empty_c ) | 
                                   ( ftp_thr7_fetch_v_f  &  ftp_thr7_fetch_v_c & thr7_is_empty_c ) | 
                                   ( !thr7_is_empty_c    & thr7_room_4ormore  & (ftp_thr7_fetch_v_wo_br_bf ))| 
                                   ( !thr7_is_empty_c    & thr7_room_4ormore  & ftp_thr7_fetch_v_f) | 
                                   ( !thr7_is_empty_c    & thr7_room_4ormore  & ftp_thr7_fetch_v_c)) & ~load_flush_w[7] & ~br_room_reset[7];


assign ready_hp_in[0] = tsm_thr0_ready_hp_bf_in & ~ftp_thr0_room_is_less_t_3 ; 
assign ready_hp_in[1] = tsm_thr1_ready_hp_bf_in & ~ftp_thr1_room_is_less_t_3 ; 
assign ready_hp_in[2] = tsm_thr2_ready_hp_bf_in & ~ftp_thr2_room_is_less_t_3 ; 
assign ready_hp_in[3] = tsm_thr3_ready_hp_bf_in & ~ftp_thr3_room_is_less_t_3 ; 
assign ready_hp_in[4] = tsm_thr4_ready_hp_bf_in & ~ftp_thr4_room_is_less_t_3 ; 
assign ready_hp_in[5] = tsm_thr5_ready_hp_bf_in & ~ftp_thr5_room_is_less_t_3 ; 
assign ready_hp_in[6] = tsm_thr6_ready_hp_bf_in & ~ftp_thr6_room_is_less_t_3 ; 
assign ready_hp_in[7] = tsm_thr7_ready_hp_bf_in & ~ftp_thr7_room_is_less_t_3 ; 

/// To keep old zero_in files happy
assign tsm_thr0_ready_hp_bf = ready_hp_bf[0];
assign tsm_thr1_ready_hp_bf = ready_hp_bf[1];
assign tsm_thr2_ready_hp_bf = ready_hp_bf[2];
assign tsm_thr3_ready_hp_bf = ready_hp_bf[3];
assign tsm_thr4_ready_hp_bf = ready_hp_bf[4];
assign tsm_thr5_ready_hp_bf = ready_hp_bf[5];
assign tsm_thr6_ready_hp_bf = ready_hp_bf[6];
assign tsm_thr7_ready_hp_bf = ready_hp_bf[7];

assign ftp_unused[7:0] = {tsm_thr7_ready_hp_bf, tsm_thr6_ready_hp_bf,
                          tsm_thr5_ready_hp_bf, tsm_thr4_ready_hp_bf,
                          tsm_thr3_ready_hp_bf, tsm_thr2_ready_hp_bf,
                          tsm_thr1_ready_hp_bf, tsm_thr0_ready_hp_bf} ;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 ready_fp_reg  (
 .scan_in(ready_fp_reg_scanin),
 .scan_out(ready_fp_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (ready_hp_in[7:0]),
 .dout (ready_hp_bf[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);


assign ftp_reset_fill_wait = tsm_thr0_fill_rdy0 |
                       tsm_thr1_fill_rdy0 | 
                       tsm_thr2_fill_rdy0 | 
                       tsm_thr3_fill_rdy0 | 
                       tsm_thr4_fill_rdy0 | 
                       tsm_thr5_fill_rdy0 | 
                       tsm_thr6_fill_rdy0 | 
                       tsm_thr7_fill_rdy0 ; 


///////////////////////////////////////////////////////////
// By_pass for each thread should be included in the room 
// calculations.
///////////////////////////////////////////////////////////
assign next_by_pass_sel_bbf[0] = cmu_thr0_data_ready;
assign next_by_pass_sel_bbf[1] = cmu_thr1_data_ready;
assign next_by_pass_sel_bbf[2] = cmu_thr2_data_ready;
assign next_by_pass_sel_bbf[3] = cmu_thr3_data_ready;
assign next_by_pass_sel_bbf[4] = cmu_thr4_data_ready;
assign next_by_pass_sel_bbf[5] = cmu_thr5_data_ready;
assign next_by_pass_sel_bbf[6] = cmu_thr6_data_ready;
assign next_by_pass_sel_bbf[7] = cmu_thr7_data_ready;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 cmu_fill_byp_thread_reg  (
 .scan_in(cmu_fill_byp_thread_reg_scanin),
 .scan_out(cmu_fill_byp_thread_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_by_pass_sel_bbf[7:0]),
 .dout (by_pass_sel_bf[7:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 by_pass_sel_f_reg  (
 .scan_in(by_pass_sel_f_reg_scanin),
 .scan_out(by_pass_sel_f_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (by_pass_sel_bf[7:0]),
 .dout (by_pass_sel_f[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 by_pass_sel_c_reg  (
 .scan_in(by_pass_sel_c_reg_scanin),
 .scan_out(by_pass_sel_c_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  (by_pass_sel_f[7:0]),
 .dout (by_pass_sel_c[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////////////////////////////////////////////////
// Generate by_pass signals                                                                  //
///////////////////////////////////////////////////////////////////////////////////////////////
assign thr0_kill_by_pass_bbf = cmu_thr0_data_ready & (tsm_thr0_ignore_by_pass | thr0_redirect_bf) ;
assign thr1_kill_by_pass_bbf = cmu_thr1_data_ready & (tsm_thr1_ignore_by_pass | thr1_redirect_bf) ;
assign thr2_kill_by_pass_bbf = cmu_thr2_data_ready & (tsm_thr2_ignore_by_pass | thr2_redirect_bf) ;
assign thr3_kill_by_pass_bbf = cmu_thr3_data_ready & (tsm_thr3_ignore_by_pass | thr3_redirect_bf) ;
assign thr4_kill_by_pass_bbf = cmu_thr4_data_ready & (tsm_thr4_ignore_by_pass | thr4_redirect_bf) ;
assign thr5_kill_by_pass_bbf = cmu_thr5_data_ready & (tsm_thr5_ignore_by_pass | thr5_redirect_bf) ;
assign thr6_kill_by_pass_bbf = cmu_thr6_data_ready & (tsm_thr6_ignore_by_pass | thr6_redirect_bf) ;
assign thr7_kill_by_pass_bbf = cmu_thr7_data_ready & (tsm_thr7_ignore_by_pass | thr7_redirect_bf) ;

assign byp_valid_in = cmu_any_data_ready & ~( thr0_kill_by_pass_bbf |
                                              thr1_kill_by_pass_bbf |
                                              thr2_kill_by_pass_bbf |
                                              thr3_kill_by_pass_bbf |
                                              thr4_kill_by_pass_bbf |
                                              thr5_kill_by_pass_bbf |
                                              thr6_kill_by_pass_bbf |
                                              thr7_kill_by_pass_bbf ) ;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 byp_valid_reg  (
  .scan_in(byp_valid_reg_scanin),
  .scan_out(byp_valid_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (byp_valid_in),
  .dout (ftp_byp_valid),
  .siclk(siclk),
  .soclk(soclk));


 ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 thrx_kill_by_pass_reg  (
  .scan_in(thrx_kill_by_pass_reg_scanin),
  .scan_out(thrx_kill_by_pass_reg_scanout),
  .l1clk( l1clk  ),
  .din  ({thr7_kill_by_pass_bbf,thr6_kill_by_pass_bbf,thr5_kill_by_pass_bbf,thr4_kill_by_pass_bbf,
          thr3_kill_by_pass_bbf,thr2_kill_by_pass_bbf,thr1_kill_by_pass_bbf,thr0_kill_by_pass_bbf}),
  .dout ({thr7_kill_by_pass_bf,thr6_kill_by_pass_bf,thr5_kill_by_pass_bf,thr4_kill_by_pass_bf,
          thr3_kill_by_pass_bf,thr2_kill_by_pass_bf,thr1_kill_by_pass_bf,thr0_kill_by_pass_bf}),
  .siclk(siclk),
  .soclk(soclk));

assign kill2_by_pass_bf  = (by_pass_sel_bf[0] & thr0_redirect_bf) |
                           (by_pass_sel_bf[1] & thr1_redirect_bf) |
                           (by_pass_sel_bf[2] & thr2_redirect_bf) |
                           (by_pass_sel_bf[3] & thr3_redirect_bf) |
                           (by_pass_sel_bf[4] & thr4_redirect_bf) |
                           (by_pass_sel_bf[5] & thr5_redirect_bf) |
                           (by_pass_sel_bf[6] & thr6_redirect_bf) |
                           (by_pass_sel_bf[7] & thr7_redirect_bf) ;

assign bypass_thread_killed = thr7_kill_by_pass_bf | thr6_kill_by_pass_bf | thr5_kill_by_pass_bf |
                              thr4_kill_by_pass_bf | thr3_kill_by_pass_bf | thr2_kill_by_pass_bf |
                              thr1_kill_by_pass_bf | thr0_kill_by_pass_bf | kill2_by_pass_bf     ;

assign by_pass_valid_bf = ftp_byp_valid & ~bypass_thread_killed ;

assign prev_by_pass_at_cycle_1 = cycle_2_by_pass_ok_f | cycle_3_by_pass_ok_c ;
assign prev_by_pass_at_cycle_2 = cycle_3_by_pass_ok_f ;

assign cycle_2_by_pass_ok_bf=  ((ftp_fetch_v_c_unq | prev_by_pass_at_cycle_1)  & ~(ftp_fetch_v_dup_f | prev_by_pass_at_cycle_2) & by_pass_valid_bf);
assign cycle_3_by_pass_ok_bf=  ((ftp_fetch_v_c_unq | prev_by_pass_at_cycle_1)  &  (ftp_fetch_v_dup_f | prev_by_pass_at_cycle_2) & by_pass_valid_bf) ;

// Cycle_2
 ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 cycle_2_by_pass_f_reg  (
  .scan_in(cycle_2_by_pass_f_reg_scanin),
  .scan_out(cycle_2_by_pass_f_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (cycle_2_by_pass_ok_bf),
  .dout (cycle_2_by_pass_ok_f),
  .siclk(siclk),
  .soclk(soclk));

// Cycle_3
 ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 cycle_3_by_pass_f_reg  (
  .scan_in(cycle_3_by_pass_f_reg_scanin),
  .scan_out(cycle_3_by_pass_f_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (cycle_3_by_pass_ok_bf),
  .dout (cycle_3_by_pass_ok_f),
  .siclk(siclk),
  .soclk(soclk));

 ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 cycle_3_by_pass_c_reg  (
  .scan_in(cycle_3_by_pass_c_reg_scanin),
  .scan_out(cycle_3_by_pass_c_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (cycle_3_by_pass_ok_f),
  .dout (cycle_3_by_pass_ok_c),
  .siclk(siclk),
  .soclk(soclk));

///////////////////////////////////////////////////////////////////////////////////////////////

ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 by_pass_v_f_reg  (
 .scan_in(by_pass_v_f_reg_scanin),
 .scan_out(by_pass_v_f_reg_scanout),
 .l1clk( l1clk_pm1  ),
 .din  (by_pass_valid_bf),
 .dout (by_pass_valid_unq_f),
  .siclk(siclk),
  .soclk(soclk));


assign by_pass_valid_f = by_pass_valid_unq_f & ~bypass_thread_redirected_p_f ;
assign bypass_thread_redirected_p_f = ((thr0_redirect_bf) & by_pass_sel_f[0]) |
                                      ((thr1_redirect_bf) & by_pass_sel_f[1]) |
                                      ((thr2_redirect_bf) & by_pass_sel_f[2]) |
                                      ((thr3_redirect_bf) & by_pass_sel_f[3]) |
                                      ((thr4_redirect_bf) & by_pass_sel_f[4]) |
                                      ((thr5_redirect_bf) & by_pass_sel_f[5]) |
                                      ((thr6_redirect_bf) & by_pass_sel_f[6]) |
                                      ((thr7_redirect_bf) & by_pass_sel_f[7]) ;


assign bypass_thread_redirected_f = ((thr0_red_no_br_bf | thr0_redirect_bf) & by_pass_sel_f[0]) |
                                    ((thr1_red_no_br_bf | thr1_redirect_bf) & by_pass_sel_f[1]) |
                                    ((thr2_red_no_br_bf | thr2_redirect_bf) & by_pass_sel_f[2]) |
                                    ((thr3_red_no_br_bf | thr3_redirect_bf) & by_pass_sel_f[3]) |
                                    ((thr4_red_no_br_bf | thr4_redirect_bf) & by_pass_sel_f[4]) |
                                    ((thr5_red_no_br_bf | thr5_redirect_bf) & by_pass_sel_f[5]) |
                                    ((thr6_red_no_br_bf | thr6_redirect_bf) & by_pass_sel_f[6]) |
                                    ((thr7_red_no_br_bf | thr7_redirect_bf) & by_pass_sel_f[7]) ;


 assign next_by_pass_c_valid = by_pass_valid_f & ~bypass_thread_redirected_f ;
 ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 by_pass_v_c_reg  (
  .scan_in(by_pass_v_c_reg_scanin),
  .scan_out(by_pass_v_c_reg_scanout),
  .l1clk( l1clk_pm1  ),
  .din  (next_by_pass_c_valid),
  .dout (by_pass_valid_c),
  .siclk(siclk),
  .soclk(soclk));


// assign sel_by_pass_cycle_1_int_bf = (cycle_1_by_pass_ok_bf & by_pass_valid_bf)    ;
assign sel_by_pass_cycle_2_int_f  = (cycle_2_by_pass_ok_f  & by_pass_valid_f) ;
assign sel_by_pass_cycle_3_int_c  = (cycle_3_by_pass_ok_c  & by_pass_valid_c) ;


///////////////////////////////////////////////////////////////////////////////////////////////
// Generate signals that show which thread is by_passing at C this cycle. (equivalent to C   //
// stage in normal fetching.                                                                 //
///////////////////////////////////////////////////////////////////////////////////////////////
// thr0 is by_passing the cycle after cmu_by_pass_valid                                      //
// DO NOT OVER QUALIFY with actual bypass when calculating room.                             // 
// It does not matter for performance and it is a timing path.                               //
///////////////////////////////////////////////////////////////////////////////////////////////
assign thr0_by_pass_valid_bf = by_pass_sel_bf[0] ; // &  agc_sel_by_pass_cycle_1_int_bf ;
assign thr1_by_pass_valid_bf = by_pass_sel_bf[1] ; // &  agc_sel_by_pass_cycle_1_int_bf ;
assign thr2_by_pass_valid_bf = by_pass_sel_bf[2] ; // &  agc_sel_by_pass_cycle_1_int_bf ;
assign thr3_by_pass_valid_bf = by_pass_sel_bf[3] ; // &  agc_sel_by_pass_cycle_1_int_bf ;
assign thr4_by_pass_valid_bf = by_pass_sel_bf[4] ; // &  agc_sel_by_pass_cycle_1_int_bf ;
assign thr5_by_pass_valid_bf = by_pass_sel_bf[5] ; // &  agc_sel_by_pass_cycle_1_int_bf ;
assign thr6_by_pass_valid_bf = by_pass_sel_bf[6] ; // &  agc_sel_by_pass_cycle_1_int_bf ;
assign thr7_by_pass_valid_bf = by_pass_sel_bf[7] ; // &  agc_sel_by_pass_cycle_1_int_bf ;

///////////////////////////////////////////////////////////////////////////////////////////////
// thr0 is by_passing the 2 cycles after cmu_by_pass_valid                                   //
///////////////////////////////////////////////////////////////////////////////////////////////
assign thr0_by_pass_valid_f = by_pass_sel_f[0] &  sel_by_pass_cycle_2_int_f ;
assign thr1_by_pass_valid_f = by_pass_sel_f[1] &  sel_by_pass_cycle_2_int_f ;
assign thr2_by_pass_valid_f = by_pass_sel_f[2] &  sel_by_pass_cycle_2_int_f ;
assign thr3_by_pass_valid_f = by_pass_sel_f[3] &  sel_by_pass_cycle_2_int_f ;
assign thr4_by_pass_valid_f = by_pass_sel_f[4] &  sel_by_pass_cycle_2_int_f ;
assign thr5_by_pass_valid_f = by_pass_sel_f[5] &  sel_by_pass_cycle_2_int_f ;
assign thr6_by_pass_valid_f = by_pass_sel_f[6] &  sel_by_pass_cycle_2_int_f ;
assign thr7_by_pass_valid_f = by_pass_sel_f[7] &  sel_by_pass_cycle_2_int_f ;

///////////////////////////////////////////////////////////////////////////////////////////////
// thr0 is by_passing the 3 cycles after cmu_by_pass_valid                                   //
///////////////////////////////////////////////////////////////////////////////////////////////
assign thr0_by_pass_valid_c = by_pass_sel_c[0] &  sel_by_pass_cycle_3_int_c ;
assign thr1_by_pass_valid_c = by_pass_sel_c[1] &  sel_by_pass_cycle_3_int_c ;
assign thr2_by_pass_valid_c = by_pass_sel_c[2] &  sel_by_pass_cycle_3_int_c ;
assign thr3_by_pass_valid_c = by_pass_sel_c[3] &  sel_by_pass_cycle_3_int_c ;
assign thr4_by_pass_valid_c = by_pass_sel_c[4] &  sel_by_pass_cycle_3_int_c ;
assign thr5_by_pass_valid_c = by_pass_sel_c[5] &  sel_by_pass_cycle_3_int_c ;
assign thr6_by_pass_valid_c = by_pass_sel_c[6] &  sel_by_pass_cycle_3_int_c ;
assign thr7_by_pass_valid_c = by_pass_sel_c[7] &  sel_by_pass_cycle_3_int_c ;

assign thr0_by_pass_is_at_c = thr0_by_pass_valid_bf | thr0_by_pass_valid_f | thr0_by_pass_valid_c ;
assign thr1_by_pass_is_at_c = thr1_by_pass_valid_bf | thr1_by_pass_valid_f | thr1_by_pass_valid_c ;
assign thr2_by_pass_is_at_c = thr2_by_pass_valid_bf | thr2_by_pass_valid_f | thr2_by_pass_valid_c ;
assign thr3_by_pass_is_at_c = thr3_by_pass_valid_bf | thr3_by_pass_valid_f | thr3_by_pass_valid_c ;
assign thr4_by_pass_is_at_c = thr4_by_pass_valid_bf | thr4_by_pass_valid_f | thr4_by_pass_valid_c ;
assign thr5_by_pass_is_at_c = thr5_by_pass_valid_bf | thr5_by_pass_valid_f | thr5_by_pass_valid_c ;
assign thr6_by_pass_is_at_c = thr6_by_pass_valid_bf | thr6_by_pass_valid_f | thr6_by_pass_valid_c ;
assign thr7_by_pass_is_at_c = thr7_by_pass_valid_bf | thr7_by_pass_valid_f | thr7_by_pass_valid_c ;
 
///////////////////////////////////////////////////////////////////////////////////////////////
// Generate signals that show which thread is by_passing at C next cycle. (equivalent to F   //
// stage in normal fetching.                                                                 //
///////////////////////////////////////////////////////////////////////////////////////////////
assign thr0_by_pass_cycle_2_bf = by_pass_sel_bf[0] & cycle_2_by_pass_ok_bf ;  
assign thr0_by_pass_cycle_3_f  = by_pass_sel_f[0]  & cycle_3_by_pass_ok_f ;  

assign thr1_by_pass_cycle_2_bf = by_pass_sel_bf[1] & cycle_2_by_pass_ok_bf ;  
assign thr1_by_pass_cycle_3_f  = by_pass_sel_f[1]  & cycle_3_by_pass_ok_f ;  

assign thr2_by_pass_cycle_2_bf = by_pass_sel_bf[2] & cycle_2_by_pass_ok_bf ;  
assign thr2_by_pass_cycle_3_f  = by_pass_sel_f[2]  & cycle_3_by_pass_ok_f ;  

assign thr3_by_pass_cycle_2_bf = by_pass_sel_bf[3] & cycle_2_by_pass_ok_bf ;  
assign thr3_by_pass_cycle_3_f  = by_pass_sel_f[3]  & cycle_3_by_pass_ok_f ;  

assign thr4_by_pass_cycle_2_bf = by_pass_sel_bf[4] & cycle_2_by_pass_ok_bf ;  
assign thr4_by_pass_cycle_3_f  = by_pass_sel_f[4]  & cycle_3_by_pass_ok_f ;  

assign thr5_by_pass_cycle_2_bf = by_pass_sel_bf[5] & cycle_2_by_pass_ok_bf ;  
assign thr5_by_pass_cycle_3_f = by_pass_sel_f[5]  & cycle_3_by_pass_ok_f ;  

assign thr6_by_pass_cycle_2_bf = by_pass_sel_bf[6] & cycle_2_by_pass_ok_bf ;  
assign thr6_by_pass_cycle_3_f  = by_pass_sel_f[6]  & cycle_3_by_pass_ok_f ;  

assign thr7_by_pass_cycle_2_bf = by_pass_sel_bf[7] & cycle_2_by_pass_ok_bf ;  
assign thr7_by_pass_cycle_3_f  = by_pass_sel_f[7]  & cycle_3_by_pass_ok_f ;  


assign thr0_by_pass_next_cycle_at_c = thr0_by_pass_cycle_2_bf | thr0_by_pass_cycle_3_f ;
assign thr1_by_pass_next_cycle_at_c = thr1_by_pass_cycle_2_bf | thr1_by_pass_cycle_3_f ;
assign thr2_by_pass_next_cycle_at_c = thr2_by_pass_cycle_2_bf | thr2_by_pass_cycle_3_f ;
assign thr3_by_pass_next_cycle_at_c = thr3_by_pass_cycle_2_bf | thr3_by_pass_cycle_3_f ;
assign thr4_by_pass_next_cycle_at_c = thr4_by_pass_cycle_2_bf | thr4_by_pass_cycle_3_f ;
assign thr5_by_pass_next_cycle_at_c = thr5_by_pass_cycle_2_bf | thr5_by_pass_cycle_3_f ;
assign thr6_by_pass_next_cycle_at_c = thr6_by_pass_cycle_2_bf | thr6_by_pass_cycle_3_f ;
assign thr7_by_pass_next_cycle_at_c = thr7_by_pass_cycle_2_bf | thr7_by_pass_cycle_3_f ;

assign thr0_by_pass_2_cycles_at_c   = by_pass_sel_bf[0]   & cycle_3_by_pass_ok_bf ;
assign thr1_by_pass_2_cycles_at_c   = by_pass_sel_bf[1]   & cycle_3_by_pass_ok_bf ;
assign thr2_by_pass_2_cycles_at_c   = by_pass_sel_bf[2]   & cycle_3_by_pass_ok_bf ;
assign thr3_by_pass_2_cycles_at_c   = by_pass_sel_bf[3]   & cycle_3_by_pass_ok_bf ;
assign thr4_by_pass_2_cycles_at_c   = by_pass_sel_bf[4]   & cycle_3_by_pass_ok_bf ;
assign thr5_by_pass_2_cycles_at_c   = by_pass_sel_bf[5]   & cycle_3_by_pass_ok_bf ;
assign thr6_by_pass_2_cycles_at_c   = by_pass_sel_bf[6]   & cycle_3_by_pass_ok_bf ;
assign thr7_by_pass_2_cycles_at_c   = by_pass_sel_bf[7]   & cycle_3_by_pass_ok_bf ;

////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////
// Generate a signal to show if fetching the thread again or not     //
///////////////////////////////////////////////////////////////////////
assign fetch_same_thr_again_bf = ((ftp_curr_fetch_thr_bf[0] & ftp_curr_fetch_thr_f[0]) |
                                  (ftp_curr_fetch_thr_bf[1] & ftp_curr_fetch_thr_f[1]) |
                                  (ftp_curr_fetch_thr_bf[2] & ftp_curr_fetch_thr_f[2]) |
                                  (ftp_curr_fetch_thr_bf[3] & ftp_curr_fetch_thr_f[3]) |
                                  (ftp_curr_fetch_thr_bf[4] & ftp_curr_fetch_thr_f[4]) |
                                  (ftp_curr_fetch_thr_bf[5] & ftp_curr_fetch_thr_f[5]) |
                                  (ftp_curr_fetch_thr_bf[6] & ftp_curr_fetch_thr_f[6]) |
                                  (ftp_curr_fetch_thr_bf[7] & ftp_curr_fetch_thr_f[7])) &
                                  ftp_fetch_v_dup_f;


////////////////////////////////////////////////////////////////////////
// current fetch thread matches the branch redirection thread
////////////////////////////////////////////////////////////////////////

assign br0_matches_curr = ((~ftp_tid0_e[1] & ~ftp_tid0_e[0] &
                                   ftp_curr_fetch_thr_bf[0]   ) |
                                  (~ftp_tid0_e[1] & ftp_tid0_e[0] &
                                   ftp_curr_fetch_thr_bf[1]   ) |
                                  (ftp_tid0_e[1] & ~ftp_tid0_e[0] &
                                   ftp_curr_fetch_thr_bf[2]   ) |
                                  (ftp_tid0_e[1] & ftp_tid0_e[0] &
                                   ftp_curr_fetch_thr_bf[3]   )) ;

assign br1_matches_curr  = ((~ftp_tid1_e[1] & ~ftp_tid1_e[0] &
                                   ftp_curr_fetch_thr_bf[4]   ) |
                                  (~ftp_tid1_e[1] & ftp_tid1_e[0] &
                                   ftp_curr_fetch_thr_bf[5]   ) |
                                  (ftp_tid1_e[1] & ~ftp_tid1_e[0] &
                                   ftp_curr_fetch_thr_bf[6]   ) |
                                  (ftp_tid1_e[1] & ftp_tid1_e[0] &
                                   ftp_curr_fetch_thr_bf[7]   )) ;

 // assign br_tid_matches_curr = br0_matches_curr | br1_matches_curr ;
///////////////////////////////////////////////////////////////////////
// Final mux for the PC_F                                            //
///////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////
// assuming dec_br_taken_e[0] = 0 and dec_br_taken_e[0] = 0 
/////////////////////////////////////////////////////////
// assign ftp_pc_sel_nb0_nb1[0] = ~fetch_same_thr_again_bf ;
// assign ftp_pc_sel_nb0_nb1[1] =  fetch_same_thr_again_bf ;
                          
/////////////////////////////////////////////////////////
// assuming dec_br_taken_e[0] = 1 and dec_br_taken_e[0] = 0 
/////////////////////////////////////////////////////////
// assign ftp_pc_sel_b0_nb1[0] =  ftp_any_thread_ready & ~fetch_same_thr_again_bf & ~single_thread_active;
// assign ftp_pc_sel_b0_nb1[1] =  ftp_any_thread_ready &  fetch_same_thr_again_bf & ~single_thread_active;
// assign ftp_pc_sel_b0_nb1[2] =  single_thread_active ; // 

/////////////////////////////////////////////////////////
// assuming dec_br_taken_e[0] = 0 and dec_br_taken_e[0] = 1 
/////////////////////////////////////////////////////////
// assign ftp_pc_sel_nb0_b1[0] =  ftp_any_thread_ready & ~fetch_same_thr_again_bf & ~single_thread_active;
// assign ftp_pc_sel_nb0_b1[1] =  ftp_any_thread_ready &  fetch_same_thr_again_bf & ~single_thread_active;
// assign ftp_pc_sel_nb0_b1[2] =  single_thread_active ; 

/////////////////////////////////////////////////////////
// assuming dec_br_taken_e[0] = 1 and dec_br_taken_e[0] = 1 
/////////////////////////////////////////////////////////
// assign ftp_pc_sel_b0_b1[0] =  ftp_any_thread_ready & ~fetch_same_thr_again_bf & ~br1_matches_curr & ~br0_matches_curr;
// assign ftp_pc_sel_b0_b1[1] =  ftp_any_thread_ready &  fetch_same_thr_again_bf & ~br1_matches_curr & ~br0_matches_curr;
// assign ftp_pc_sel_b0_b1[2] =  ( ~(ftp_any_thread_ready | br1_matches_curr) | br0_matches_curr)  ;
// assign ftp_pc_sel_b0_b1[3] =  br1_matches_curr ;
// Note: In single thread mode this case is NOT possible. In MT mode, we do NOT care what is selected this
//       this cycle because we DO not force the branch address in BF stage.
///////////////////////////////////////////////////////////////////////////////////////////////
// assign ftp_pc_sel_b0_b1[0] = ~fetch_same_thr_again_bf ;
// assign ftp_pc_sel_b0_b1[1] =  fetch_same_thr_again_bf ;
                          
/////////////////////////////////////////////////////////
// assuming dec_br_taken_e[0] = 0 and dec_br_taken_e[0] = 0 
/////////////////////////////////////////////////////////
//assign ftp_pc_sel_am_nb0_nb1[0] = ~fetch_same_thr_again_bf &  ftp_curr_pstate_am_bf_ & ~select_itc_va;
//assign ftp_pc_sel_am_nb0_nb1[1] =  fetch_same_thr_again_bf &  ftp_curr_pstate_am_bf_ & ~select_itc_va;
//assign ftp_pc_sel_am_nb0_nb1[2] = ~fetch_same_thr_again_bf & ~ftp_curr_pstate_am_bf_ & ~select_itc_va;
//assign ftp_pc_sel_am_nb0_nb1[3] =  fetch_same_thr_again_bf & ~ftp_curr_pstate_am_bf_ & ~select_itc_va;
//assign ftp_pc_sel_am_nb0_nb1[4] =  select_itc_va ;
//                          
/////////////////////////////////////////////////////////
// assuming dec_br_taken_e[0] = 1 and dec_br_taken_e[0] = 0 
/////////////////////////////////////////////////////////
 assign ftp_pc_sel_am[0] =  ftp_any_thread_ready & ~fetch_same_thr_again_bf &  ftp_curr_pstate_am_bf_ & ~select_itc_va &
                           ~sel_am_5; 

 assign ftp_pc_sel_am[1] =  ftp_any_thread_ready &  fetch_same_thr_again_bf &  ftp_curr_pstate_am_bf_ & ~select_itc_va &
                           ~sel_am_5; 

 assign ftp_pc_sel_am[2] =  ftp_any_thread_ready & ~fetch_same_thr_again_bf & ~ftp_curr_pstate_am_bf_ & ~select_itc_va &
                           ~sel_am_5;

 assign ftp_pc_sel_am[3] =  ftp_any_thread_ready &  fetch_same_thr_again_bf & ~ftp_curr_pstate_am_bf_ & ~select_itc_va & 
                           ~sel_am_5; 

 assign ftp_pc_sel_am[4] =  select_itc_va & ~sel_am_5;
 assign ftp_pc_sel_am[5] =  sel_am_5 | (~ftp_any_thread_ready & ~select_itc_va)     ;


assign  ftp_pc_sel_tag_part1[0] =  ftp_any_thread_ready & ~select_itc_va & ~sel_am_5;
assign  ftp_pc_sel_tag_part1[1] =  select_itc_va & ~sel_am_5 ;
assign  ftp_pc_sel_tag_part1[2] =  ~ftp_pc_sel_tag_part1[1] & ~ftp_pc_sel_tag_part1[0];

assign  ftp_pc_sel_tag_part2[0] =  ftp_any_thread_ready & ~select_itc_va & ftp_curr_pstate_am_bf_ & ~sel_am_5;
assign  ftp_pc_sel_tag_part2[1] =  select_itc_va & ~sel_am_5;
assign  ftp_pc_sel_tag_part2[2] =  ~ftp_pc_sel_tag_part2[0] & ~ftp_pc_sel_tag_part2[1] & ~ ftp_pc_sel_tag_part2[3] ; 
assign  ftp_pc_sel_tag_part2[3] =  ftp_any_thread_ready & ~select_itc_va & ~ftp_curr_pstate_am_bf_ & ~sel_am_5 ;

assign  ftp_pc_sel_tag_pc_bot[0]  =  ftp_any_thread_ready & ~fetch_same_thr_again_bf & ~select_itc_va;
assign  ftp_pc_sel_tag_pc_bot[1]  = ~( ftp_any_thread_ready & ~fetch_same_thr_again_bf & ~select_itc_va);

assign  ftp_pc_sel_tag_pc_top[0]  =  ftp_any_thread_ready & ~fetch_same_thr_again_bf & ftp_curr_pstate_am_bf_ & ~select_itc_va;
assign  ftp_pc_sel_tag_pc_top[1]  = ~( ftp_any_thread_ready & ~fetch_same_thr_again_bf & ftp_curr_pstate_am_bf_ & ~select_itc_va);

///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// Final mux for the ICADDR                                          //
///////////////////////////////////////////////////////////////////////

assign ftp_icaddr_sel_first_mux[0] = ~fetch_same_thr_again_bf & ~ftp_fill_req_q_bf & ~ic_rd_req_ff & ~ic_wr_req_ff & ~mbi_run_bf & 
                                      ~tg_rd_req_ff & ~tg_wr_req_ff;
assign ftp_icaddr_sel_first_mux[1] =  fetch_same_thr_again_bf & ~ftp_fill_req_q_bf & ~ic_rd_req_ff & ~ic_wr_req_ff & ~mbi_run_bf &
                                      ~tg_rd_req_ff & ~tg_wr_req_ff; 
assign ftp_icaddr_sel_first_mux[2] =  ftp_fill_req_q_bf & ~mbi_run_bf;
assign ftp_icaddr_sel_first_mux[3] =  (ic_rd_req_ff | ic_wr_req_ff | tg_rd_req_ff | tg_wr_req_ff) & ~ftp_fill_req_q_bf & ~mbi_run_bf;
assign ftp_icaddr_sel_first_mux[4] =  mbi_run_bf ;


assign next_pstate_am_[7:0]  = ~tlu_pstate_am[7:0] ;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 pstate_am_reg  (
 .scan_in(pstate_am_reg_scanin),
 .scan_out(pstate_am_reg_scanout),
 .l1clk( l1clk_pm1),
 .din  (next_pstate_am_[7:0]),
 .dout (ftp_pstate_am_bf_[7:0]),
  .siclk(siclk),
  .soclk(soclk));


assign ftp_curr_pstate_am_bf_ =  (ftp_curr_fetch_thr_bf[0] & ftp_pstate_am_bf_[0]) | 
                                (ftp_curr_fetch_thr_bf[1] & ftp_pstate_am_bf_[1]) |
                                (ftp_curr_fetch_thr_bf[2] & ftp_pstate_am_bf_[2]) |
                                (ftp_curr_fetch_thr_bf[3] & ftp_pstate_am_bf_[3]) |
                                (ftp_curr_fetch_thr_bf[4] & ftp_pstate_am_bf_[4]) |
                                (ftp_curr_fetch_thr_bf[5] & ftp_pstate_am_bf_[5]) |
                                (ftp_curr_fetch_thr_bf[6] & ftp_pstate_am_bf_[6]) |
                                (ftp_curr_fetch_thr_bf[7] & ftp_pstate_am_bf_[7]) ;


assign reload_in = itc_demap_next;


//flop reload

ifu_ftu_ftp_ctl_msff_ctl_macro__width_2 reload_latch  (
	.scan_in(reload_latch_scanin),
	.scan_out(reload_latch_scanout),
	.din	({reload_in,
		  reload}),
	.dout	({reload,
		  reload_last}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// assign select_itc_va      =  (reload | reload_last) | mbi_run_bf ;

assign next_ftp_ith_det_req_bf =   next_ith_det_req & ~(reload_in | reload) ;
assign next_select_itc_va      =   reload_in        |      reload | mbi_run_bf ; 
assign next_sel_am_5           =   next_ftp_ith_det_req_bf & ~next_select_itc_va ; 

ifu_ftu_ftp_ctl_msff_ctl_macro__width_2 pre_sel_am_reg  (
	.scan_in(pre_sel_am_reg_scanin),
	.scan_out(pre_sel_am_reg_scanout),
	.din	({next_select_itc_va,
		  next_sel_am_5}),
	.dout	({select_itc_va,
		  sel_am_5}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// assign ftp_select_itc_ctx =  (reload | reload_last);


assign next_thr0_pid_data[2:0] =  (lsu_ifu_wr_pid  & (lsu_ifu_tid_w[2:0] == 3'b000)) ?   lsu_ifu_pid_data:
                                   thr0_pid_data[2:0] ;
assign next_thr1_pid_data[2:0] =  (lsu_ifu_wr_pid  & (lsu_ifu_tid_w[2:0] == 3'b001)) ?   lsu_ifu_pid_data:
                                   thr1_pid_data[2:0] ;
assign next_thr2_pid_data[2:0] =  (lsu_ifu_wr_pid  & (lsu_ifu_tid_w[2:0] == 3'b010)) ?   lsu_ifu_pid_data:
                                   thr2_pid_data[2:0] ;
assign next_thr3_pid_data[2:0] =  (lsu_ifu_wr_pid  & (lsu_ifu_tid_w[2:0] == 3'b011)) ?   lsu_ifu_pid_data:
                                   thr3_pid_data[2:0] ;
assign next_thr4_pid_data[2:0] =  (lsu_ifu_wr_pid  & (lsu_ifu_tid_w[2:0] == 3'b100)) ?   lsu_ifu_pid_data:
                                   thr4_pid_data[2:0] ;
assign next_thr5_pid_data[2:0] =  (lsu_ifu_wr_pid  & (lsu_ifu_tid_w[2:0] == 3'b101)) ?   lsu_ifu_pid_data:
                                   thr5_pid_data[2:0] ;
assign next_thr6_pid_data[2:0] =  (lsu_ifu_wr_pid  & (lsu_ifu_tid_w[2:0] == 3'b110)) ?   lsu_ifu_pid_data:
                                   thr6_pid_data[2:0] ;
assign next_thr7_pid_data[2:0] =  (lsu_ifu_wr_pid  & (lsu_ifu_tid_w[2:0] == 3'b111)) ?   lsu_ifu_pid_data:
                                   thr7_pid_data[2:0] ;

ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 thr0_pid_reg  (
 .scan_in(thr0_pid_reg_scanin),
 .scan_out(thr0_pid_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_thr0_pid_data[2:0]),
 .dout (thr0_pid_data[2:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 thr1_pid_reg  (
 .scan_in(thr1_pid_reg_scanin),
 .scan_out(thr1_pid_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_thr1_pid_data[2:0]),
 .dout (thr1_pid_data[2:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 thr2_pid_reg  (
 .scan_in(thr2_pid_reg_scanin),
 .scan_out(thr2_pid_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_thr2_pid_data[2:0]),
 .dout (thr2_pid_data[2:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 thr3_pid_reg  (
 .scan_in(thr3_pid_reg_scanin),
 .scan_out(thr3_pid_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_thr3_pid_data[2:0]),
 .dout (thr3_pid_data[2:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 thr4_pid_reg  (
 .scan_in(thr4_pid_reg_scanin),
 .scan_out(thr4_pid_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_thr4_pid_data[2:0]),
 .dout (thr4_pid_data[2:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 thr5_pid_reg  (
 .scan_in(thr5_pid_reg_scanin),
 .scan_out(thr5_pid_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_thr5_pid_data[2:0]),
 .dout (thr5_pid_data[2:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 thr6_pid_reg  (
 .scan_in(thr6_pid_reg_scanin),
 .scan_out(thr6_pid_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_thr6_pid_data[2:0]),
 .dout (thr6_pid_data[2:0]),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 thr7_pid_reg  (
 .scan_in(thr7_pid_reg_scanin),
 .scan_out(thr7_pid_reg_scanout),
 .l1clk( l1clk_pm1                                                             ),
 .din  (next_thr7_pid_data[2:0]),
 .dout (thr7_pid_data[2:0]),
  .siclk(siclk),
  .soclk(soclk));

assign ftp_curr_pid_bf[2:0] = ({3{ftp_itb_fetch_thr_dup_bf[7]}} & thr7_pid_data[2:0]) | 
                              ({3{ftp_itb_fetch_thr_dup_bf[6]}} & thr6_pid_data[2:0]) |
                              ({3{ftp_itb_fetch_thr_dup_bf[5]}} & thr5_pid_data[2:0]) |
                              ({3{ftp_itb_fetch_thr_dup_bf[4]}} & thr4_pid_data[2:0]) |
                              ({3{ftp_itb_fetch_thr_dup_bf[3]}} & thr3_pid_data[2:0]) |
                              ({3{ftp_itb_fetch_thr_dup_bf[2]}} & thr2_pid_data[2:0]) |
                              ({3{ftp_itb_fetch_thr_dup_bf[1]}} & thr1_pid_data[2:0]) |
                              ({3{ftp_itb_fetch_thr_dup_bf[0]}} & thr0_pid_data[2:0]) ;

assign ftp_thr7_pid_data[2:0] = thr7_pid_data[2:0] ;
assign ftp_thr6_pid_data[2:0] = thr6_pid_data[2:0] ;
assign ftp_thr5_pid_data[2:0] = thr5_pid_data[2:0] ;
assign ftp_thr4_pid_data[2:0] = thr4_pid_data[2:0] ;
assign ftp_thr3_pid_data[2:0] = thr3_pid_data[2:0] ;
assign ftp_thr2_pid_data[2:0] = thr2_pid_data[2:0] ;
assign ftp_thr1_pid_data[2:0] = thr1_pid_data[2:0] ;
assign ftp_thr0_pid_data[2:0] = thr0_pid_data[2:0] ;

assign ftp_thr0_go_to_sf_wait = (((ftp_fetch_thr_q_f[0] & ~invalidation_req_f) | (by_pass_valid_bf & by_pass_sel_bf[0])) & agc_thr0_sf_valid_f) ;
assign ftp_thr1_go_to_sf_wait = (((ftp_fetch_thr_q_f[1] & ~invalidation_req_f) | (by_pass_valid_bf & by_pass_sel_bf[1])) & agc_thr1_sf_valid_f) ;
assign ftp_thr2_go_to_sf_wait = (((ftp_fetch_thr_q_f[2] & ~invalidation_req_f) | (by_pass_valid_bf & by_pass_sel_bf[2])) & agc_thr2_sf_valid_f) ;
assign ftp_thr3_go_to_sf_wait = (((ftp_fetch_thr_q_f[3] & ~invalidation_req_f) | (by_pass_valid_bf & by_pass_sel_bf[3])) & agc_thr3_sf_valid_f) ;
assign ftp_thr4_go_to_sf_wait = (((ftp_fetch_thr_q_f[4] & ~invalidation_req_f) | (by_pass_valid_bf & by_pass_sel_bf[4])) & agc_thr4_sf_valid_f) ;
assign ftp_thr5_go_to_sf_wait = (((ftp_fetch_thr_q_f[5] & ~invalidation_req_f) | (by_pass_valid_bf & by_pass_sel_bf[5])) & agc_thr5_sf_valid_f) ;
assign ftp_thr6_go_to_sf_wait = (((ftp_fetch_thr_q_f[6] & ~invalidation_req_f) | (by_pass_valid_bf & by_pass_sel_bf[6])) & agc_thr6_sf_valid_f) ;
assign ftp_thr7_go_to_sf_wait = (((ftp_fetch_thr_q_f[7] & ~invalidation_req_f) | (by_pass_valid_bf & by_pass_sel_bf[7])) & agc_thr7_sf_valid_f) ;

assign invalidation_req_f =  (ftp_fetch_thr_q_f[0] & agc_invalidation_req_ff[0]) |
                             (ftp_fetch_thr_q_f[1] & agc_invalidation_req_ff[1]) |
                             (ftp_fetch_thr_q_f[2] & agc_invalidation_req_ff[2]) |
                             (ftp_fetch_thr_q_f[3] & agc_invalidation_req_ff[3]) |
                             (ftp_fetch_thr_q_f[4] & agc_invalidation_req_ff[4]) |
                             (ftp_fetch_thr_q_f[5] & agc_invalidation_req_ff[5]) |
                             (ftp_fetch_thr_q_f[6] & agc_invalidation_req_ff[6]) |
                             (ftp_fetch_thr_q_f[7] & agc_invalidation_req_ff[7]) ;
 

///////////////////////////////////////////////////////////////////////
// Spare circuits                                                    //
///////////////////////////////////////////////////////////////////////
ifu_ftu_ftp_ctl_spare_ctl_macro__num_5 spares  (
        .scan_in(spares_scanin),
        .scan_out(spares_scanout),
        .l1clk  (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////////////////////
// Power management for ICD                                                                   //
////////////////////////////////////////////////////////////////////////////////////////////////

assign curr_thr_pc_bf[4] = ~ifu_agd_pc_f[4] ;
assign curr_thr_pc_bf[3] = ~ifu_agd_pc_f[4] & ifu_agd_pc_f[3] ;
assign curr_thr_pc_bf[2] = ~ifu_agd_pc_f[4] & ifu_agd_pc_f[2] ;

assign ic_pwr_sel_index[0] = ~fetch_same_thr_again_bf & ~ic_rd_req_ff & ~ic_wr_req_ff & ~tg_rd_req_ff & ~tg_wr_req_ff;
assign ic_pwr_sel_index[1] =  fetch_same_thr_again_bf & ~ic_rd_req_ff & ~ic_wr_req_ff & ~tg_rd_req_ff & ~tg_wr_req_ff; 
assign ic_pwr_sel_index[2] =  (ic_rd_req_ff | ic_wr_req_ff | tg_rd_req_ff | tg_wr_req_ff) ;

assign thr0_pc_muxed_f[4:2] = ftp_thr0_sel_br_bf ? agd_address0_m[4:2] : agd_thr0_pc_4_2_f[4:2] ;
assign thr1_pc_muxed_f[4:2] = ftp_thr1_sel_br_bf ? agd_address0_m[4:2] : agd_thr1_pc_4_2_f[4:2] ;
assign thr2_pc_muxed_f[4:2] = ftp_thr2_sel_br_bf ? agd_address0_m[4:2] : agd_thr2_pc_4_2_f[4:2] ;
assign thr3_pc_muxed_f[4:2] = ftp_thr3_sel_br_bf ? agd_address0_m[4:2] : agd_thr3_pc_4_2_f[4:2] ;
assign thr4_pc_muxed_f[4:2] = ftp_thr4_sel_br_bf ? agd_address1_m[4:2] : agd_thr4_pc_4_2_f[4:2] ;
assign thr5_pc_muxed_f[4:2] = ftp_thr5_sel_br_bf ? agd_address1_m[4:2] : agd_thr5_pc_4_2_f[4:2] ;
assign thr6_pc_muxed_f[4:2] = ftp_thr6_sel_br_bf ? agd_address1_m[4:2] : agd_thr6_pc_4_2_f[4:2] ;
assign thr7_pc_muxed_f[4:2] = ftp_thr7_sel_br_bf ? agd_address1_m[4:2] : agd_thr7_pc_4_2_f[4:2] ;

assign new_thr_pc_bf[4:2]   = ({3{ftp_curr_fetch_thr_bf[0]}} & thr0_pc_muxed_f[4:2]) |
                              ({3{ftp_curr_fetch_thr_bf[1]}} & thr1_pc_muxed_f[4:2]) |
                              ({3{ftp_curr_fetch_thr_bf[2]}} & thr2_pc_muxed_f[4:2]) |
                              ({3{ftp_curr_fetch_thr_bf[3]}} & thr3_pc_muxed_f[4:2]) |
                              ({3{ftp_curr_fetch_thr_bf[4]}} & thr4_pc_muxed_f[4:2]) |
                              ({3{ftp_curr_fetch_thr_bf[5]}} & thr5_pc_muxed_f[4:2]) |
                              ({3{ftp_curr_fetch_thr_bf[6]}} & thr6_pc_muxed_f[4:2]) |
                              ({3{ftp_curr_fetch_thr_bf[7]}} & thr7_pc_muxed_f[4:2]) ;

assign ic_index_bf[4:2]    = ({3{ic_pwr_sel_index[0]}} & new_thr_pc_bf[4:2])  | 
                             ({3{ic_pwr_sel_index[1]}} & curr_thr_pc_bf[4:2]) | 
                             ({3{ic_pwr_sel_index[2]}} & asi_addr_bf[5:3])    ; 

assign ftp_icd_quad_3_en_bf =   (hp_pickready        |
                                ic_pwr_sel_index[2] |
                                ftp_fill_req_q_bf) | ~ifu_ic_pmen  | mbi_run_bf;

assign ftp_icd_quad_2_en_bf = (~(ic_index_bf[4:2] == 3'b111) & (hp_pickready | ic_pwr_sel_index[2])) |
                                ftp_fill_req_q_bf  | ~ifu_ic_pmen  | mbi_run_bf;
          
assign ftp_icd_quad_1_en_bf = (~(ic_index_bf[4:3] == 2'b11) & (hp_pickready | ic_pwr_sel_index[2])) |
                                ftp_fill_req_q_bf  | ~ifu_ic_pmen  | mbi_run_bf;

assign ftp_icd_quad_0_en_bf = (~(ic_index_bf[4:3] == 2'b11)                 & (hp_pickready | ic_pwr_sel_index[2])) |
                              (~({ic_index_bf[4],ic_index_bf[2]} == 2'b11) & (hp_pickready | ic_pwr_sel_index[2])) |
                                ftp_fill_req_q_bf  | ~ifu_ic_pmen  | mbi_run_bf;
          
          
supply0 vss;
supply1 vdd;
assign se = tcu_scan_en ;
// fixscan start:
assign br_reg_scanin             = scan_in                  ;
assign tlu_flush_ifu_req_scanin  = br_reg_scanout           ;
assign br_tid_reg_scanin         = tlu_flush_ifu_req_scanout;
assign tid_dec_w_reg_scanin      = br_tid_reg_scanout       ;
assign tid_bf_reg_scanin         = tid_dec_w_reg_scanout    ;
assign top_lruf_scanin           = tid_bf_reg_scanout       ;
assign bot_lruf_scanin           = top_lruf_scanout         ;
assign favor_top_reg_scanin      = bot_lruf_scanout         ;
assign curr_fetch_thr_f_reg_scanin = favor_top_reg_scanout    ;
assign curr_fetch_thr_c_reg_scanin = curr_fetch_thr_f_reg_scanout;
assign inv_line_reg_scanin       = curr_fetch_thr_c_reg_scanout;
assign fill_req_bf_reg_scanin    = inv_line_reg_scanout     ;
assign rd_is_first_reg_scanin    = fill_req_bf_reg_scanout  ;
assign wr_request_pending_reg_scanin = rd_is_first_reg_scanout  ;
assign ic_wr_req_ff_reg_scanin   = wr_request_pending_reg_scanout;
assign ic_rd_req_ff_reg_scanin   = ic_wr_req_ff_reg_scanout ;
assign tg_wr_req_ff_reg_scanin   = ic_rd_req_ff_reg_scanout ;
assign tg_rd_req_ff_reg_scanin   = tg_wr_req_ff_reg_scanout ;
assign itt_rd_req_ff_reg_scanin  = tg_rd_req_ff_reg_scanout ;
assign itd_rd_req_ff_reg_scanin  = itt_rd_req_ff_reg_scanout;
assign ith_det_req_ff_reg_scanin = itd_rd_req_ff_reg_scanout;
assign itlb_probe_l_reg_scanin   = ith_det_req_ff_reg_scanout;
assign fill_req_bf_q_reg_scanin  = itlb_probe_l_reg_scanout ;
assign mbist_in_reg_scanin       = fill_req_bf_q_reg_scanout;
assign itlb_cam_vld_reg_scanin   = mbist_in_reg_scanout     ;
assign itlb_bypass_lat_scanin    = itlb_cam_vld_reg_scanout ;
assign ic_rd_done_f_reg_scanin   = itlb_bypass_lat_scanout  ;
assign ic_rd_done_c_reg_scanin   = ic_rd_done_f_reg_scanout ;
assign ic_rd_done_p_reg_scanin   = ic_rd_done_c_reg_scanout ;
assign ic_wr_done_f_reg_scanin   = ic_rd_done_p_reg_scanout ;
assign tg_rd_done_f_reg_scanin   = ic_wr_done_f_reg_scanout ;
assign tg_rd_done_c_reg_scanin   = tg_rd_done_f_reg_scanout ;
assign tg_wr_done_f_reg_scanin   = tg_rd_done_c_reg_scanout ;
assign it_rd_done_f_reg_scanin   = tg_wr_done_f_reg_scanout ;
assign it_rd_done_c_reg_scanin   = it_rd_done_f_reg_scanout ;
assign asi_rd_done_reg_scanin    = it_rd_done_c_reg_scanout ;
assign asi_wr_done_reg_scanin    = asi_rd_done_reg_scanout  ;
assign asi_it_rd_done_reg_scanin = asi_wr_done_reg_scanout  ;
assign itlb_sel_tag_f_reg_scanin = asi_it_rd_done_reg_scanout;
assign itlb_sel_data_f_reg_scanin = itlb_sel_tag_f_reg_scanout;
assign itlb_sel_pa_f_reg_scanin  = itlb_sel_data_f_reg_scanout;
assign itlb_sel_c_reg_scanin     = itlb_sel_pa_f_reg_scanout;
assign thrx_redirect_reg_scanin  = itlb_sel_c_reg_scanout   ;
assign fetch_v_f_reg_scanin      = thrx_redirect_reg_scanout;
assign fetch_v_f_dup_reg_scanin  = fetch_v_f_reg_scanout    ;
assign fetch_v_c_reg_scanin      = fetch_v_f_dup_reg_scanout;
assign enabled_thr_reg_scanin    = fetch_v_c_reg_scanout    ;
assign ready_fp_reg_scanin       = enabled_thr_reg_scanout  ;
assign cmu_fill_byp_thread_reg_scanin = ready_fp_reg_scanout     ;
assign by_pass_sel_f_reg_scanin  = cmu_fill_byp_thread_reg_scanout;
assign by_pass_sel_c_reg_scanin  = by_pass_sel_f_reg_scanout;
assign byp_valid_reg_scanin      = by_pass_sel_c_reg_scanout;
assign thrx_kill_by_pass_reg_scanin = byp_valid_reg_scanout    ;
assign cycle_2_by_pass_f_reg_scanin = thrx_kill_by_pass_reg_scanout;
assign cycle_3_by_pass_f_reg_scanin = cycle_2_by_pass_f_reg_scanout;
assign cycle_3_by_pass_c_reg_scanin = cycle_3_by_pass_f_reg_scanout;
assign by_pass_v_f_reg_scanin    = cycle_3_by_pass_c_reg_scanout;
assign by_pass_v_c_reg_scanin    = by_pass_v_f_reg_scanout  ;
assign pstate_am_reg_scanin      = by_pass_v_c_reg_scanout  ;
assign reload_latch_scanin       = pstate_am_reg_scanout    ;
assign pre_sel_am_reg_scanin     = reload_latch_scanout     ;
assign thr0_pid_reg_scanin       = pre_sel_am_reg_scanout   ;
assign thr1_pid_reg_scanin       = thr0_pid_reg_scanout     ;
assign thr2_pid_reg_scanin       = thr1_pid_reg_scanout     ;
assign thr3_pid_reg_scanin       = thr2_pid_reg_scanout     ;
assign thr4_pid_reg_scanin       = thr3_pid_reg_scanout     ;
assign thr5_pid_reg_scanin       = thr4_pid_reg_scanout     ;
assign thr6_pid_reg_scanin       = thr5_pid_reg_scanout     ;
assign thr7_pid_reg_scanin       = thr6_pid_reg_scanout     ;
assign spares_scanin             = thr7_pid_reg_scanout     ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_11 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [10:0] fdin;
wire [9:0] so;

  input [10:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [10:0] dout;
  output scan_out;
assign fdin[10:0] = din[10:0];


dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_ftp_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ftu_ftp_ctl_spare_ctl_macro__num_5 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));
assign scan_out = so_4;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_itc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_itc_ctl (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tlu_itlb_reload, 
  tlu_trap_pc_0, 
  tlu_trap_pc_1, 
  itd_index_valid_in, 
  ftp_itt_rd_req_bf, 
  ftp_itd_rd_req_bf, 
  mbi_wdata_6, 
  mbi_wdata_0, 
  tlu_trap_pc_0_45_43, 
  tlu_trap_pc_1_45_43, 
  lsu_asi_error_inject_b31, 
  lsu_asi_error_inject_b29, 
  lsu_asi_error_inject_b28, 
  tlu_itlb_bypass, 
  lsu_immu_enable, 
  ftp_itb_fetch_thr_bf, 
  asi_real_bf, 
  ftp_ith_det_req_bf, 
  mbi_run, 
  lbist_run, 
  mbi_cambist_run, 
  mbi_itb_demap_en, 
  mbi_demap_type, 
  mbi_dis_clr_ubit, 
  mbi_repl_write, 
  mbi_itb_cam_en_pre, 
  mbi_itb_write_en, 
  mbi_itb_read_en, 
  itb_tte_data_v_27_22, 
  itb_tte_data_v_21_16, 
  scan_out, 
  itc_wr_u_en, 
  itc_rw_index_vld, 
  itc_demap, 
  itc_demap_context, 
  itc_demap_all, 
  itc_demap_real, 
  itc_tte_ubit, 
  itc_sel_trap_pc_0, 
  itc_sel_trap_pc_1, 
  itc_sel_demap_tag_d, 
  itc_sel_demap_tag_c0, 
  itc_sel_demap_tag_c1, 
  itc_sel_write_tag, 
  itc_sel_write_tag_indexed, 
  itc_sel_default, 
  itc_itlb_rd_vld_bf, 
  itc_bypass_bf, 
  itc_ra_to_pa_bf, 
  itc_tag_error_inj, 
  itc_data_error_inj, 
  itc_dis_clr_ubit, 
  itc_write_next, 
  itc_demap_next, 
  itc_sel_mbist, 
  itc_mbi_itb_read_en, 
  itc_thr_to_write, 
  itc_itb_data_sz_1);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire lsu_err_inj_sig_reg_scanin;
wire lsu_err_inj_sig_reg_scanout;
wire asi_error_inject_b31_ff;
wire asi_error_inject_b29_ff;
wire asi_error_inject_b28_ff;
wire tag_error_inj;
wire wr_vld_in;
wire data_error_inj;
wire error_inj_latch_scanin;
wire error_inj_latch_scanout;
wire [1:0] reload;
wire demap_next_in;
wire reload0_latch_scanin;
wire reload0_latch_scanout;
wire reload0;
wire [37:35] tlu_tte;
wire [2:0] tlu_tte_45_43;
wire tte0_lat_scanin;
wire tte0_lat_scanout;
wire [37:35] tte0;
wire [7:0] tte0_tid_dec;
wire tte1_lat_scanin;
wire tte1_lat_scanout;
wire [7:0] tte1_tid_dec;
wire [7:0] thr_to_write_in;
wire demap_c0_reg_scanin;
wire demap_c0_reg_scanout;
wire [2:0] demap_c0;
wire demap_c1_reg_scanin;
wire demap_c1_reg_scanout;
wire [2:0] demap_c1;
wire reload1_latch_scanin;
wire reload1_latch_scanout;
wire reload1;
wire wr_vld_latch_scanin;
wire wr_vld_latch_scanout;
wire itc_cam_vld_1;
wire wr_vld;
wire mbist_dis_clr_ubit_ff;
wire itc_repl_wrire;
wire itc_cam_vld_2;
wire itc_cam_vld_2_unused;
wire bist_run_reg_scanin;
wire bist_run_reg_scanout;
wire itc_mbist_run;
wire itc_cambist_run;
wire itc_itb_demap_en;
wire [1:0] itc_demap_type;
wire itc_mbi_itb_write_en;
wire itc_mbi_wdata_6;
wire itc_mbi_wdata_0;
wire itc_tte_ubit_old;
wire demap_page;
wire demap_context;
wire demap_all;
wire demap_real;
wire itc_sel_demap_tag_d_in;
wire itc_sel_demap_tag_c0_in;
wire itc_sel_demap_tag_c1_in;
wire itc_sel_demap_reg_scanin;
wire itc_sel_demap_reg_scanout;
wire itc_sel_write_tag_in;
wire itc_sel_write_tag_indexed_in;
wire itc_sel_default_in;
wire index_valid;
wire itc_demap_page;
wire itc_demap_page_unused;
wire itlb_bypass_lat_scanin;
wire itlb_bypass_lat_scanout;
wire [7:0] itlb_bypass;
wire immu_enable_lat_scanin;
wire immu_enable_lat_scanout;
wire [7:0] immu_enable;
wire [7:0] pre_bypass_bf;
wire [7:0] pre_ra_to_pa;
wire spares_scanin;
wire spares_scanout;
wire se;


input		tcu_scan_en;
input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
                                        // The following signals indicate the
                                        // first cycle of TTE transfer as well
                                        // as the operation (write or demap)
input	[1:0]	tlu_itlb_reload;
input	[37:35]	tlu_trap_pc_0;	        // 
input	[37:35]	tlu_trap_pc_1;	        // 
input		itd_index_valid_in;	// Write with index

input		ftp_itt_rd_req_bf;
input		ftp_itd_rd_req_bf;
input		mbi_wdata_6;
input		mbi_wdata_0;
input [2:0] tlu_trap_pc_0_45_43;
input [2:0] tlu_trap_pc_1_45_43;

input  		lsu_asi_error_inject_b31;
input  		lsu_asi_error_inject_b29;
input  		lsu_asi_error_inject_b28;

input	[7:0]	tlu_itlb_bypass;
input	[7:0]	lsu_immu_enable;
input	[7:0]	ftp_itb_fetch_thr_bf;
input 		asi_real_bf;
input 	        ftp_ith_det_req_bf;

input           mbi_run;
input           lbist_run;
input           mbi_cambist_run ;
input           mbi_itb_demap_en ;
input  [1:0]    mbi_demap_type ;
input           mbi_dis_clr_ubit ;
input           mbi_repl_write ;
input           mbi_itb_cam_en_pre ;

input	        mbi_itb_write_en;
input	        mbi_itb_read_en;
input           itb_tte_data_v_27_22 ;
input           itb_tte_data_v_21_16 ;

output		scan_out;
output		itc_wr_u_en;		// Write enable
output		itc_rw_index_vld;	// Use index for read or write
output		itc_demap;		// Any demap
output		itc_demap_context;	// Demap context
output		itc_demap_all;		// Demap all
output		itc_demap_real;		// Demap real
output          itc_tte_ubit ;          // tte_ubit

output		itc_sel_trap_pc_0;	// Datapath controls
output		itc_sel_trap_pc_1;
output		itc_sel_demap_tag_d;
output		itc_sel_demap_tag_c0;
output		itc_sel_demap_tag_c1;
output		itc_sel_write_tag;
output		itc_sel_write_tag_indexed;
output		itc_sel_default;

output		itc_itlb_rd_vld_bf       ;
output 		itc_bypass_bf;

output		itc_ra_to_pa_bf;
output 	        itc_tag_error_inj;
output 	        itc_data_error_inj;

output          itc_dis_clr_ubit ;

output 	        itc_write_next;
output		itc_demap_next;
output 		itc_sel_mbist;
output 		itc_mbi_itb_read_en;
output [7:0]    itc_thr_to_write;
output 		itc_itb_data_sz_1;


//////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;

// Clock header
ifu_ftu_itc_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk 			),
        .l1en   (1'b1			),
        .l1clk  (l1clk			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


////////////////////////////////////////////////////////////////////////////////
//
//
//


ifu_ftu_itc_ctl_msff_ctl_macro__width_3 lsu_err_inj_sig_reg   (
	.scan_in(lsu_err_inj_sig_reg_scanin),
	.scan_out(lsu_err_inj_sig_reg_scanout),
	.din	({lsu_asi_error_inject_b31,
                  lsu_asi_error_inject_b29,
                  lsu_asi_error_inject_b28}	),
	.dout	({asi_error_inject_b31_ff,
                  asi_error_inject_b29_ff,
                  asi_error_inject_b28_ff}		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tag_error_inj  = asi_error_inject_b31_ff & asi_error_inject_b28_ff & wr_vld_in;
assign data_error_inj = asi_error_inject_b31_ff & asi_error_inject_b29_ff & wr_vld_in;

ifu_ftu_itc_ctl_msff_ctl_macro__width_2 error_inj_latch   (
        .scan_in(error_inj_latch_scanin),
        .scan_out(error_inj_latch_scanout),
        .din    ({    tag_error_inj,    data_error_inj  }),
        .dout   ({itc_tag_error_inj,itc_data_error_inj  }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//flop tlb_reload 

assign itc_sel_trap_pc_0 =
       tlu_itlb_reload[0] | reload[0];

assign itc_sel_trap_pc_1 =
       tlu_itlb_reload[1] | reload[1];

assign demap_next_in = (| tlu_itlb_reload[1:0] );
ifu_ftu_itc_ctl_msff_ctl_macro__width_3 reload0_latch   (
	.scan_in(reload0_latch_scanin),
	.scan_out(reload0_latch_scanout),
	.din	({tlu_itlb_reload[1:0], demap_next_in}	),
	.dout	({reload[1:0],itc_demap_next}		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign reload0 =
       (| reload[1:0]);


////////////////////////////////////////////////////
// TID logic                                      //
// Add logic here for timing reasons.             //
////////////////////////////////////////////////////

assign tlu_tte[37:35]     = itc_sel_trap_pc_0 ? tlu_trap_pc_0[37:35] : tlu_trap_pc_1[37:35] ;
assign tlu_tte_45_43[2:0] = itc_sel_trap_pc_0 ? tlu_trap_pc_0_45_43[2:0] : tlu_trap_pc_1_45_43[2:0] ;


ifu_ftu_itc_ctl_msff_ctl_macro__width_3 tte0_lat  (
        .scan_in(tte0_lat_scanin),
        .scan_out(tte0_lat_scanout),
        .din    (tlu_tte                [37:35] ),
        .dout   (tte0                   [37:35] ),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tte0_tid_dec[0] = ~tte0[37] & ~tte0[36]  & ~tte0[35] ;
assign tte0_tid_dec[1] = ~tte0[37] & ~tte0[36]  &  tte0[35] ;
assign tte0_tid_dec[2] = ~tte0[37] &  tte0[36]  & ~tte0[35] ;
assign tte0_tid_dec[3] = ~tte0[37] &  tte0[36]  &  tte0[35] ;
assign tte0_tid_dec[4] =  tte0[37] & ~tte0[36]  & ~tte0[35] ;
assign tte0_tid_dec[5] =  tte0[37] & ~tte0[36]  &  tte0[35] ;
assign tte0_tid_dec[6] =  tte0[37] &  tte0[36]  & ~tte0[35] ;
assign tte0_tid_dec[7] =  tte0[37] &  tte0[36]  &  tte0[35] ;

ifu_ftu_itc_ctl_msff_ctl_macro__width_8 tte1_lat  (
        .scan_in(tte1_lat_scanin),
        .scan_out(tte1_lat_scanout),
        .din    (tte0_tid_dec[7:0]),
        .dout   (tte1_tid_dec[7:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign itc_thr_to_write[7:0] = thr_to_write_in[7:0] ;


assign thr_to_write_in[7:0] = ({8{ reload0}} & tte0_tid_dec[7:0]) |
                               ({8{~reload0}} & tte1_tid_dec[7:0]) ;


////////////////////////////////////////////////////
////////////////////////////////////////////////////
////////////////////////////////////////////////////
////////////////////////////////////////////////////


ifu_ftu_itc_ctl_msff_ctl_macro__width_3 demap_c0_reg   (
	.scan_in(demap_c0_reg_scanin),
	.scan_out(demap_c0_reg_scanout),
	.din	(tlu_tte_45_43[2:0]		),
	.dout	(demap_c0[2:0]		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_itc_ctl_msff_ctl_macro__width_3 demap_c1_reg   (
	.scan_in(demap_c1_reg_scanin),
	.scan_out(demap_c1_reg_scanout),
	.din	(demap_c0[2:0]		),
	.dout	(demap_c1[2:0]		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_itc_ctl_msff_ctl_macro__width_1 reload1_latch   (
	.scan_in(reload1_latch_scanin),
	.scan_out(reload1_latch_scanout),
	.din	(reload0		),
	.dout	(reload1		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// demap_control[2]:  1 means demap, 0 means write
// demap_control[1:0] (if demap_control[2] is 1)
//      00     Demap page
//      01     Demap context
//      10     Demap all 
//      11     Demap real
// demap_control[1:0] (if demap_control[2] is 0)
//      00     Demap and write with supplied context
//      01     Demap and write with context_0
//      10     Demap and write with context_1
//      11     Illegal (but demap and write with context_0)

assign wr_vld_in =
       reload1 & ~demap_c1[2];
		  
ifu_ftu_itc_ctl_msff_ctl_macro__width_5 wr_vld_latch   (
	.scan_in(wr_vld_latch_scanin),
	.scan_out(wr_vld_latch_scanout),
	.din	({wr_vld_in, mbi_dis_clr_ubit , mbi_repl_write, mbi_itb_cam_en_pre, itc_cam_vld_1}		),
	.dout	({wr_vld   , mbist_dis_clr_ubit_ff, itc_repl_wrire ,itc_cam_vld_1, itc_cam_vld_2}		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk));

assign itc_cam_vld_2_unused = itc_cam_vld_2 ; 

ifu_ftu_itc_ctl_msff_ctl_macro__width_9 bist_run_reg   (
	.scan_in(bist_run_reg_scanin),
	.scan_out(bist_run_reg_scanout),
	.din	({mbi_run,mbi_cambist_run, mbi_itb_demap_en,mbi_demap_type[1:0], 
                  mbi_itb_read_en,mbi_itb_write_en,mbi_wdata_6,mbi_wdata_0}),
	.dout	({itc_mbist_run,itc_cambist_run,itc_itb_demap_en,itc_demap_type[1:0],
                  itc_mbi_itb_read_en,itc_mbi_itb_write_en,itc_mbi_wdata_6,itc_mbi_wdata_0}	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk));

assign itc_tte_ubit_old =  (itc_mbist_run & ~itc_cambist_run) ? itc_mbi_wdata_0 : itc_mbi_wdata_6 ; 
assign itc_tte_ubit     = itc_tte_ubit_old | (~itc_cambist_run & ~itc_mbist_run) ;

assign demap_page =
       (reload1 & demap_c1[2] & ~demap_c1[1] & ~demap_c1[0]) |
       (reload1 & ~demap_c1[2]);

assign demap_context =
       reload1 & demap_c1[2] & ~demap_c1[1] &  demap_c1[0];

assign demap_all  =
       reload1 & demap_c1[2] &  demap_c1[1] & ~demap_c1[0];

assign demap_real =
       reload1 & demap_c1[2] &  demap_c1[1] &  demap_c1[0];

assign itc_sel_demap_tag_d_in = (reload0 &  demap_c0[2] & ~mbi_run) | 
                                (reload0 & ~demap_c0[2] & ~demap_c0[1] & ~mbi_run) ;

assign itc_sel_demap_tag_c0_in =  (reload0 & ~demap_c0[2] &  demap_c0[0] & ~mbi_run) ;

assign itc_sel_demap_tag_c1_in = 
       (reload0 & ~demap_c0[2] &  demap_c0[1] & ~demap_c0[0] & ~mbi_run) ;

ifu_ftu_itc_ctl_msff_ctl_macro__width_7 itc_sel_demap_reg   (
	.scan_in(itc_sel_demap_reg_scanin),
	.scan_out(itc_sel_demap_reg_scanout),
	.din	({itc_sel_demap_tag_d_in,
              itc_sel_demap_tag_c0_in,
              itc_sel_demap_tag_c1_in,
              itc_sel_write_tag_in,
              itc_sel_write_tag_indexed_in,
              itc_sel_default_in,
              itd_index_valid_in}	),
	.dout	({itc_sel_demap_tag_d,
              itc_sel_demap_tag_c0,
              itc_sel_demap_tag_c1,
              itc_sel_write_tag,
              itc_sel_write_tag_indexed,
              itc_sel_default,
              index_valid}		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign itc_sel_write_tag_in = wr_vld_in & ~itd_index_valid_in & ~mbi_run;

assign itc_sel_write_tag_indexed_in = wr_vld_in & itd_index_valid_in & ~mbi_run;

assign itc_sel_mbist = itc_mbist_run ;
assign itc_sel_default_in = ~reload0 & ~wr_vld_in & ~mbi_run;

assign itc_write_next = wr_vld_in ;


///outputs

assign itc_demap                = (itc_mbist_run & itc_cambist_run) ? itc_itb_demap_en : (!itc_mbist_run & reload1);
assign itc_demap_page           = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en  & (itc_demap_type[1:0] == 2'b00)) : 
                                  (!itc_mbist_run & demap_page);
assign itc_demap_context        = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en  & (itc_demap_type[1:0] == 2'b10)) : 
                                  (!itc_mbist_run & demap_context);
assign itc_demap_all            = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en  & (itc_demap_type[1:0] == 2'b11)) : 
                                  (!itc_mbist_run & demap_all);
assign itc_demap_real           = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en  & (itc_demap_type[1:0] == 2'b01)) : 
                                  (!itc_mbist_run & demap_real);


assign itc_wr_u_en 		= (wr_vld & ~itc_mbist_run) | 
                                  (itc_mbi_itb_write_en & itc_mbist_run);

assign itc_rw_index_vld		= (wr_vld & index_valid & ~itc_mbist_run) | 
				  (ftp_itt_rd_req_bf  & ~itc_mbist_run) | 
                                  (ftp_itd_rd_req_bf  & ~itc_mbist_run) | 
                                  (itc_mbist_run & ~itc_repl_wrire) |
                                  lbist_run ;

assign itc_demap_page_unused = itc_demap_page ;


//////////////////////////////////////////////////////////////////////
// ITLB bypass control

ifu_ftu_itc_ctl_msff_ctl_macro__width_8 itlb_bypass_lat  (
	.scan_in(itlb_bypass_lat_scanin),
	.scan_out(itlb_bypass_lat_scanout),
	.din	(tlu_itlb_bypass	[7:0]	),
	.dout	(itlb_bypass		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

ifu_ftu_itc_ctl_msff_ctl_macro__width_8 immu_enable_lat  (
	.scan_in(immu_enable_lat_scanin),
	.scan_out(immu_enable_lat_scanout),
	.din	(lsu_immu_enable	[7:0]	),
	.dout	(immu_enable		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

       
   assign pre_bypass_bf[7:0] = ftp_ith_det_req_bf ? 8'h00 :
          itlb_bypass[7:0];

assign pre_ra_to_pa[7:0] = ftp_ith_det_req_bf ? {8{asi_real_bf}} :
       ~itlb_bypass[7:0] &~immu_enable[7:0];

assign itc_ra_to_pa_bf =
       (| (ftp_itb_fetch_thr_bf[7:0] & pre_ra_to_pa[7:0]));

assign itc_bypass_bf =
       (| (ftp_itb_fetch_thr_bf[7:0] & pre_bypass_bf[7:0])) & ~itc_mbist_run;


assign itc_itlb_rd_vld_bf          = (ftp_itt_rd_req_bf & ~itc_mbist_run) | 
                                     (ftp_itd_rd_req_bf & ~itc_mbist_run) | 
                                     (itc_mbi_itb_read_en & itc_mbist_run) ;

assign itc_itb_data_sz_1 = ~itb_tte_data_v_27_22 & itb_tte_data_v_21_16 ; 


///////////////////////////////////////////////////////////////////////
// Spare circuits                                                    //
///////////////////////////////////////////////////////////////////////
ifu_ftu_itc_ctl_spare_ctl_macro__num_1 spares  (
        .scan_in(spares_scanin),
        .scan_out(spares_scanout),
        .l1clk  (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign itc_dis_clr_ubit = itc_mbist_run & mbist_dis_clr_ubit_ff;

 
assign se = tcu_scan_en ;
// fixscan start:
assign lsu_err_inj_sig_reg_scanin = scan_in                  ;
assign error_inj_latch_scanin    = lsu_err_inj_sig_reg_scanout;
assign reload0_latch_scanin      = error_inj_latch_scanout  ;
assign tte0_lat_scanin           = reload0_latch_scanout    ;
assign tte1_lat_scanin           = tte0_lat_scanout         ;
assign demap_c0_reg_scanin       = tte1_lat_scanout         ;
assign demap_c1_reg_scanin       = demap_c0_reg_scanout     ;
assign reload1_latch_scanin      = demap_c1_reg_scanout     ;
assign wr_vld_latch_scanin       = reload1_latch_scanout    ;
assign bist_run_reg_scanin       = wr_vld_latch_scanout     ;
assign itc_sel_demap_reg_scanin  = bist_run_reg_scanout     ;
assign itlb_bypass_lat_scanin    = itc_sel_demap_reg_scanout;
assign immu_enable_lat_scanin    = itlb_bypass_lat_scanout  ;
assign spares_scanin             = immu_enable_lat_scanout  ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule	
	
	
// any PARAMS parms go into naming of macro

module ifu_ftu_itc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itc_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itc_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itc_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itc_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itc_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ftu_itc_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_itd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_itd_dp (
  tcu_scan_en, 
  tcu_muxtest, 
  tcu_dectest, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  default_pid, 
  default_r, 
  default_context_0, 
  default_context_1, 
  write_context_0, 
  write_context_1, 
  itc_sel_trap_pc_0, 
  itc_sel_trap_pc_1, 
  itc_sel_demap_tag_d, 
  itc_sel_demap_tag_c0, 
  itc_sel_demap_tag_c1, 
  itc_sel_write_tag, 
  itc_sel_default, 
  itc_sel_write_tag_indexed, 
  itc_tag_error_inj, 
  itc_data_error_inj, 
  ifu_agd_pc_bf, 
  tlu_trap_pc_0, 
  tlu_trap_pc_1, 
  mmu_index, 
  ftp_thr0_pid_data, 
  ftp_thr1_pid_data, 
  ftp_thr2_pid_data, 
  ftp_thr3_pid_data, 
  ftp_thr4_pid_data, 
  ftp_thr5_pid_data, 
  ftp_thr6_pid_data, 
  ftp_thr7_pid_data, 
  asi_addr_bf, 
  mbi_addr, 
  mbi_wdata, 
  mbi_run, 
  mbi_cambist_run, 
  mbi_cambist_shift, 
  mbi_init_to_zero, 
  itc_sel_mbist, 
  itc_write_next, 
  scan_out, 
  itd_tag, 
  itd_data, 
  itd_index_valid_in, 
  itd_rw_index, 
  itd_prty_256m, 
  itd_prty_4m, 
  itd_prty_64k, 
  itd_prty_8k, 
  itd_prty_ctxt0, 
  itd_prty_ctxt1);
wire stop;
wire en;
wire test;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [54:0] tlu_tte;
wire tte0_lat_scanin;
wire tte0_lat_scanout;
wire init_or_shift;
wire [54:0] tte0;
wire init_or_shift_bf;
wire tte1_lat_scanin;
wire tte1_lat_scanout;
wire [54:0] tte1;
wire not_init_and_run;
wire not_init_nor_run;
wire [54:0] tte2;
wire not_init_and_run_bf;
wire not_init_nor_run_bf;
wire [2:0] partition_id1_to_buf;
wire [2:0] partition_id1;
wire [68:0] tag_to_demap_d;
wire [68:0] tag_to_demap_c0;
wire [12:0] write_context_0_ff;
wire [68:0] tag_to_demap_c1;
wire [12:0] write_context_1_ff;
wire prty_tte0_ctxt_;
wire sel_write_tag_c0;
wire sel_write_tag_c1;
wire [13:0] context_to_write_in;
wire [68:0] tag_to_write;
wire [13:0] context_to_write;
wire [2:0] partition_id2;
wire context_to_write_prty;
wire mask_va_27_22_;
wire mask_va_21_16_;
wire mask_va_15_13_;
wire mask_context_;
wire [27:13] masked_va;
wire masked_ctxt_parity;
wire [68:0] access_tag_f;
wire wrdata_sel;
wire [51:13] tag_for_parity;
wire mux_masked_ctxt_parity;
wire tag_parity_unmasked;
wire tag_parity_masked;
wire tag_parity;
wire [7:0] mbist_wdata_bf;
wire mbist_run;
wire tag_parity_out;
wire prty_256m;
wire prty_8k_lower;
wire prty_va_27_22;
wire prty_4m;
wire prty_va_27_16;
wire prty_64k;
wire prty_8k;
wire prty_ctxt0;
wire prty_ctxt1;
wire [68:0] access_tag_in;
wire access_tag_reg_scanin;
wire access_tag_reg_scanout;
wire access_tag_reg0_scanin;
wire access_tag_reg0_scanout;
wire write_context_0_reg_scanin;
wire write_context_0_reg_scanout;
wire write_context_1_reg_scanin;
wire write_context_1_reg_scanout;
wire context_to_write_reg_scanin;
wire context_to_write_reg_scanout;
wire tte2_lat_scanin;
wire tte2_lat_scanout;
wire [52:0] tte2_out;
wire [3:0] atm_unused;
wire [6:0] tte2_unused;
wire tte1_unused;
wire [68:0] mbist_wdata;
wire [7:0] mbist_wdata_dup;
wire [37:0] data_mbist_wdata;
wire [68:0] mbist_camdata;
wire [68:0] mbist_camdata_shift;
wire [68:0] bist_wdata;
wire [68:0] itd_tag_to_buf;
wire [5:0] mbist_index;
wire [5:0] itd_rw_index_to_buf;
wire mbist_in_reg_scanin;
wire mbist_in_reg_scanout;
wire [5:0] mbist_index_to_buf;
wire [7:0] mbist_wdata_to_buf;
wire mbist_run_to_buf;
wire cambist_run_bf;
wire mbist_in_dup_reg_scanin;
wire mbist_in_dup_reg_scanout;
wire tcu_muxtest_rep0;
wire [37:0] data_to_write;
wire [36:0] itd_data_to_buf;
wire data_parity;
wire data_parity_0;
wire data_parity_1;
wire init_or_shift_nor;
wire [1:0] itd_demap_control1;
wire demap_control1_0_;


input tcu_scan_en ;
input tcu_muxtest;
input tcu_dectest;
input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;

input	[2:0] default_pid;
input		default_r;
input	[12:0] default_context_0;
input	[12:0] default_context_1;
input	[13:0] write_context_0;
input	[13:0] write_context_1;

input		itc_sel_trap_pc_0;
input		itc_sel_trap_pc_1;
input		itc_sel_demap_tag_d;
input		itc_sel_demap_tag_c0;
input		itc_sel_demap_tag_c1;
input		itc_sel_write_tag;
input           itc_sel_default;
input		itc_sel_write_tag_indexed;
input 	        itc_tag_error_inj;
input 	        itc_data_error_inj;

input	[47:13]	ifu_agd_pc_bf;

input	[47:0]	tlu_trap_pc_0;
input	[47:0]	tlu_trap_pc_1;
input	[6:0]	mmu_index;		// valid and index from data_access

input	[2:0]	ftp_thr0_pid_data;
input	[2:0]	ftp_thr1_pid_data;
input	[2:0]	ftp_thr2_pid_data;
input	[2:0]	ftp_thr3_pid_data;
input	[2:0]	ftp_thr4_pid_data;
input	[2:0]	ftp_thr5_pid_data;
input	[2:0]	ftp_thr6_pid_data;
input	[2:0]	ftp_thr7_pid_data;

input	[8:3]	asi_addr_bf;
input   [5:0] mbi_addr;
input   [7:0]	mbi_wdata;
input 	        mbi_run;
input           mbi_cambist_run;
input           mbi_cambist_shift;
input           mbi_init_to_zero;

input 		itc_sel_mbist;
input           itc_write_next;

output		scan_out;

output	[68:0]	itd_tag;
output	[37:0]	itd_data;
// output	[02:00]	itd_demap_control1;
output		itd_index_valid_in;
output	[5:0]	itd_rw_index;
output		itd_prty_256m;
output		itd_prty_4m;
output		itd_prty_64k;
output		itd_prty_8k;
output		itd_prty_ctxt0;
output		itd_prty_ctxt1;


// assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
// assign siclk	= spc_aclk;
// assign soclk	= spc_bclk;
assign en	= 1'b1;
// assign clk	= l2clk;
assign test  	= tcu_dectest;

ifu_ftu_itd_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0  (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);


///////////////////////////////////////////////////////////////////////////////
// Flop the TTE from TLU

// First cycle of transfer 
// (part of tag, data, controls)
// 	  45	  Demap valid
// 	  44:43	  Demap / context type
//	  42	  PS_GT_64K
//	  41:39   VA[15:13]
//	  38	  PS_GT_8K
//	  37:35   Thread ID
//	  34	  Real bit
//	  33:22   PA[39:28]
//	  21:16   PA[27:22]
//	  15:10   PA[21:16]
//	  09:07   PA[15:13]
//	  06	  Valid bit
//	  05	  NFO bit
//	  04	  IE bit
//	  03	  CP bit
//	  02	  X bit
//	  01	  P bit
//	  00	  W bit
// Second cycle of transfer 
// (rest of tag)
//	  47:28   VA[47:28]
//	  27:22   VA[27:22]
//	  21	  PS_EQ_256M
//	  20	  Valid
//	  19	  Lock
//	  18:13   VA[21:16]
//	  12:00   Context

ifu_ftu_itd_dp_mux_macro__mux_aonpe__ports_2__stack_60c__width_55 tte_mux     (
	.din0	({mmu_index		[6:0],
		  tlu_trap_pc_0		[47:0]}),
	.din1	({mmu_index		[6:0],
		  tlu_trap_pc_1		[47:0]}),
	.sel0	(itc_sel_trap_pc_0		),
	.sel1	(itc_sel_trap_pc_1		),
	.dout	(tlu_tte		[54:0]	)
 
);

ifu_ftu_itd_dp_msff_macro__stack_60c__width_56 tte0_lat   (
        .scan_in(tte0_lat_scanin),
        .scan_out(tte0_lat_scanout),
        .clk ( l2clk                ),
	.din	({tlu_tte		[54:0]	,init_or_shift }),
	.dout	({tte0			[54:0]	,init_or_shift_bf}),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

ifu_ftu_itd_dp_msff_macro__stack_60c__width_59 tte1_lat   (
        .scan_in(tte1_lat_scanin),
        .scan_out(tte1_lat_scanout),
        .clk ( l2clk                ),
	.din	({tte0[54:0],  tte1[37:36],not_init_and_run , not_init_nor_run}	),
	.dout	({tte1[54:0],  tte2[37:36],not_init_and_run_bf , not_init_nor_run_bf }	),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


///////////////////////////TTE tag///////////////////////////////////////////////

// First must capture partition ID for both cycles
ifu_ftu_itd_dp_mux_macro__mux_aodec__ports_8__stack_4r__width_3 mx_pid1     (
	.din0	(ftp_thr0_pid_data[2:0]),
	.din1	(ftp_thr1_pid_data[2:0]),
	.din2	(ftp_thr2_pid_data[2:0]),
	.din3	(ftp_thr3_pid_data[2:0]),
	.din4	(ftp_thr4_pid_data[2:0]),
	.din5	(ftp_thr5_pid_data[2:0]),
	.din6	(ftp_thr6_pid_data[2:0]),
	.din7	(ftp_thr7_pid_data[2:0]),
	.sel	(tte1[37:35]),
	.dout	(partition_id1_to_buf[2:0])
);

ifu_ftu_itd_dp_buff_macro__stack_4c__width_3 mx_pid1_buf   (
    .din(partition_id1_to_buf[2:0]),
    .dout(partition_id1[2:0]));

// Now build tag for the two cycles
// Demap with specified context
assign tag_to_demap_d[68:0] =
       {tte0		[12:0],	// Context	
	partition_id1	[2:0],	// PID
	tte1		[34   ],	// R
	tte0		[47:28],	// VA[47:28]
	tte0		[27:22],	// VA[27:22]
	tte0		[21   ],	// 27_22_V
	tte0		[20   ],	// V
	tte0		[18:13],	// VA[21:16]
	tte1		[42   ],	// 21_16_V
	tte1		[41:39],	// VA[15:13]
	tte1		[38   ],	// 15_13_V
	tte0		[12:0]};	// Context[12:00]

// Demap with context 0
assign tag_to_demap_c0[68:0] =
       {write_context_0_ff	[12:0],	// Context[12:00]
	partition_id1		[2:0],	// PID
	tte1			[34   ],	// R
	tte0			[47:28],	// VA[47:28]
	tte0			[27:22],	// VA[27:22]
	tte0			[21   ],	// 27_22_V
	tte0			[20   ],	// V
	tte0			[18:13],	// VA[21:16]
	tte1			[42   ],	// 21_16_V
	tte1			[41:39],	// VA[15:13]
	tte1			[38   ],	// 15_13_V
	write_context_0_ff	[12:0]};	// Context[12:00]
	
// Demap with context 1
assign tag_to_demap_c1[68:0] =
       {write_context_1_ff	[12:0],	// Context[12:00]
	partition_id1		[2:0],	// PID
	tte1			[34   ],	// R
	tte0			[47:28],	// VA[47:28]
	tte0			[27:22],	// VA[27:22]
	tte0			[21   ],	// 27_22_V
	tte0			[20   ],	// V
	tte0			[18:13],	// VA[21:16]
	tte1			[42   ],	// 21_16_V
	tte1			[41:39],	// VA[15:13]
	tte1			[38   ],	// 15_13_V
	write_context_1_ff	[12:0]};	// Context[12:00]

// Mux context for write tag
ifu_ftu_itd_dp_mux_macro__mux_aope__ports_3__stack_14r__width_14 context_to_write_mux     (
	.din0	(write_context_0	[13:0]	),
	.din1	(write_context_1	[13:0]	),
	.din2	({prty_tte0_ctxt_, tte0	[12:0]}),
	.sel0	(sel_write_tag_c0		),
	.sel1	(sel_write_tag_c1		),
	.dout	(context_to_write_in	[13:0]	)
);

// buff_macro context_to_write_buf (width=14, stack=14r) (
//     .din(context_to_write_to_buf[13:0]),
//     .dout(context_to_write[13:0]));

// Write with muxed context
assign tag_to_write[68:0] =
       {context_to_write[12:0],	// Context		68:56
	partition_id2	[2:0],	// PID			55:53
	tte2		[34   ],	// R			52
	tte1		[47:28],	// VA[47:28]		51:32
	tte1		[27:22],	// VA[27:22]		31:26
	tte1		[21   ],	// 27_22_V		25
	tte1		[20   ],	// V			24
	tte1		[18:13],	// VA[21:16]		23:18
	tte2		[42   ],	// 21_16_V		17
	tte2		[41:39],	// VA[15:13]		16:14
	tte2		[38   ],	// 15_13_V		13
	context_to_write[12:0]		// Context[12:00]	12:00
	};
	
assign context_to_write_prty = context_to_write[13] ;

///////////////////////////////////////////////
// Parity generation for tte_tag
///////////////////////////////////////////////

// Mask the appropriate address/context bits based on page size and RA or VA trans type.

ifu_ftu_itd_dp_inv_macro__width_3 pg_mask_va  (
	.din	({tag_to_write[25],tag_to_write[17],tag_to_write[13]}),
	.dout	({mask_va_27_22_,  mask_va_21_16_,  mask_va_15_13_})
);
ifu_ftu_itd_dp_inv_macro__width_1 pg_mask_ctxt  (
	.din	(tag_to_write[52]),
	.dout	(mask_context_)
);

ifu_ftu_itd_dp_and_macro__ports_2__stack_16l__width_16 mask_tag    (
	.din0	({tag_to_write[31:26],
		  tag_to_write[23:18],
		  tag_to_write[16:14],
		  context_to_write_prty}),
	.din1	({{6{mask_va_27_22_}},
		  {6{mask_va_21_16_}},
		  {3{mask_va_15_13_}},
		     mask_context_}),
	.dout	({masked_va[27:22],
		  masked_va[21:16],
		  masked_va[15:13],
		  masked_ctxt_parity})
);

ifu_ftu_itd_dp_mux_macro__left_2__mux_pgpe__ports_2__stack_60c__width_40 parity_mux      (
	.din0	({ tag_to_write[55:53],	
		  tag_to_write[52],	
		  tag_to_write[51:32],	
		  masked_va   [27:22],	
		  masked_va   [21:16],	
		  masked_va   [15:13],
                  masked_ctxt_parity}),	
	.din1	({ access_tag_f[55:53],	
		  access_tag_f[52],	
		  access_tag_f[51:26],	
		  access_tag_f[23:18],	
		  access_tag_f[16:14],
                  1'b0}),	
	.sel0	(wrdata_sel	),
	.dout	({ tag_for_parity[51:13], mux_masked_ctxt_parity})
);

ifu_ftu_itd_dp_prty_macro__width_32 tag_pgen0  (
	.din	({itc_tag_error_inj,1'b0,tag_for_parity[51:28],6'b0}),
	.dout	(tag_parity_unmasked)
);
ifu_ftu_itd_dp_prty_macro__width_16 tag_pgen1  (
	.din	({tag_for_parity[27:13],mux_masked_ctxt_parity}),
	.dout	(tag_parity_masked)
);
// inv_macro inv_tag_par (width=2) (
// 	.din	({tag_parity_unmasked ,tag_parity_masked}),
// 	.dout	({tag_parity_unmasked_,tag_parity_masked_}),
// );
ifu_ftu_itd_dp_xor_macro__ports_2__width_1 pgen_tag   (
	.din0	(tag_parity_unmasked),
	.din1	(tag_parity_masked),
	.dout	(tag_parity)
);
// inv_macro write_inv (width=1) (
// 	.din	(itc_write_next ),
// 	.dout	(write_next_))
// ;
ifu_ftu_itd_dp_mux_macro__mux_pgpe__ports_2__stack_2r__width_1 tag_pmux     (
	.din0	(mbist_wdata_bf[5]),
	.din1	(tag_parity),
	.sel0	(mbist_run),
	.dout	(tag_parity_out)
);
// buff_macro tag_pbuf (width=1) (
// 	.din	(tag_parity_out),
// 	.dout	(tld_data[37])
// );

// Additional logic needed to complete parity detection.  
// tag_parity_unmasked is valid for all page sizes (it's complete for 256m)
// tag_parity_masked represents the addtional parity for 8k pages


assign prty_256m     = tag_parity_unmasked ;
assign prty_8k_lower = tag_parity_masked ; 

ifu_ftu_itd_dp_prty_macro__width_8 pgen_va_27_22  (
	.din	({access_tag_f[31:26],2'b00}),
	.dout	(prty_va_27_22)
);
ifu_ftu_itd_dp_xor_macro__ports_2__width_1 pgen_4m   (
	.din0	(prty_256m),
	.din1	(prty_va_27_22),
	.dout	(prty_4m)
);

ifu_ftu_itd_dp_prty_macro__width_16 pgen_va_27_16  (
	.din	({access_tag_f[31:26],4'b0000,access_tag_f[23:18]}),
	.dout	(prty_va_27_16)
);
ifu_ftu_itd_dp_xor_macro__ports_2__width_1 pgen_64k   (
	.din0	(prty_256m),
	.din1	(prty_va_27_16),
	.dout	(prty_64k)
);

ifu_ftu_itd_dp_xor_macro__ports_2__width_1 pgen_8k   (
	.din0	(prty_256m),
	.din1	(prty_8k_lower),
	.dout	(prty_8k)
);

 ifu_ftu_itd_dp_prty_macro__width_16 pgen_ctxt0  (
 	.din	({access_tag_f[12:0],3'b000}),
 	.dout	(prty_ctxt0)
 );
 ifu_ftu_itd_dp_prty_macro__width_16 pgen_ctxt1  (
 	.din	({3'b000,access_tag_f[68:56]}),
 	.dout	(prty_ctxt1)
 );

ifu_ftu_itd_dp_buff_macro__width_6 prty_buf  (
	.din	({    prty_256m,    prty_4m,    prty_64k,    prty_8k,    prty_ctxt0,    prty_ctxt1}),
	.dout	({itd_prty_256m,itd_prty_4m,itd_prty_64k,itd_prty_8k,itd_prty_ctxt0,itd_prty_ctxt1})
);

/////////////////////////////////////////////////////////////////////////////////////////////////////////////


 ifu_ftu_itd_dp_prty_macro__width_16 pgen_tte0_ctxt  (
  	.din	({1'b0,tte0[12:0],2'b00}),
  	.dout	(prty_tte0_ctxt_)
  );


assign access_tag_in[68:0] = {itd_tag[68:52],ifu_agd_pc_bf[47:22],itd_tag[25:24],
                              ifu_agd_pc_bf[21:16],itd_tag[17],ifu_agd_pc_bf[15:13],itd_tag[13:0]};

ifu_ftu_itd_dp_msff_macro__stack_60c__width_56 access_tag_reg  (
 .scan_in(access_tag_reg_scanin),
 .scan_out(access_tag_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1 ),  
 .din ( access_tag_in[55:0]),
 .dout( access_tag_f[55:0]    ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_itd_dp_msff_macro__stack_14c__width_13 access_tag_reg0  (
 .scan_in(access_tag_reg0_scanin),
 .scan_out(access_tag_reg0_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1 ),  
 .din ( access_tag_in[68:56]),
 .dout( access_tag_f[68:56]    ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_itd_dp_msff_macro__stack_14c__width_13 write_context_0_reg  (
 .scan_in(write_context_0_reg_scanin),
 .scan_out(write_context_0_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1 ),  
 .din ( write_context_0[12:0]),
 .dout( write_context_0_ff[12:0]    ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_itd_dp_msff_macro__stack_14c__width_14 write_context_1_reg  (
 .scan_in(write_context_1_reg_scanin),
 .scan_out(write_context_1_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1 ),  
 .din ( {itc_write_next,write_context_1[12:0]}),
 .dout( {wrdata_sel,write_context_1_ff[12:0] }   ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_itd_dp_msff_macro__stack_14c__width_14 context_to_write_reg  (
 .scan_in(context_to_write_reg_scanin),
 .scan_out(context_to_write_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1 ),  
 .din ( context_to_write_in[13:0]),
 .dout( context_to_write[13:0]    ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// msff_macro tte2_lat (width=52, stack=70c, mux=aope, ports=4) (
//         .scan_in(tte2_lat_scanin),
//         .scan_out(tte2_lat_scanout),
//         .din0   ({51'b0,1'b1}),
//         .din1   ({tte2_lat_out[50:0],1'b0}),
//         .din2   ({tte1[54:47],partition_id1[2:0],tte1[42:38],1'b1,1'b0,tte1[34:7],tte1[5:0]}),
//         .din3   ({tld_tag[55:52],12'b0,1'b0,1'b1,7'b0,tgd_tag_c1[12:00],tgd_tag_c0[12:0],1'b0}),
//         .sel0   (mbi_init_to_zero),
//         .sel1   (mbi_cambist_shift),
//         .sel2   (tlc_write_next),
//         .dout   (tte2_lat_out[51:0]),
//         .en     (tlc_tte2_clken)
// );

ifu_ftu_itd_dp_msff_macro__mux_aope__ports_3__stack_60c__width_53 tte2_lat   (
        .scan_in(tte2_lat_scanin),
        .scan_out(tte2_lat_scanout),
        .clk(l2clk),
        .din0   ({52'b0,1'b1}),
        .din1   ({tte2_out[51:0],1'b0}),
	.din2 	({tte1[54:46],partition_id1[2:0],tte1[44:38],tte1[34:28],tte1[27:7],tte1[5:0]}),
        .sel0   (mbi_init_to_zero ),
        .sel1   (mbi_cambist_shift),
	.dout	({tte2[54:46],partition_id2[2:0],tte2[44:38],tte2[34:28],tte2[27:7],tte2[5:0]}),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


assign tte2_out[52:0]  = 	({tte2[54:46],partition_id2[2:0],tte2[44:38],tte2[34:28],tte2[27:7],tte2[5:0]});
assign itd_index_valid_in =          tte1[54];

assign atm_unused[3:0] = {access_tag_f[25:24],access_tag_f[17],access_tag_f[13]};
assign tte2_unused[6:0]            = {tte2[47:46],tte2[44:43],tte2[37:36], tte1[35]} ;
assign tte1_unused     = tte1[6] ;


///////////////////////////////////////////////
// Mux bist test data                        //
///////////////////////////////////////////////
//     mbist_wdata[68:0] = {    mbist_wdata_bf[2:0], mbist_wdata_bf[7:0],mbist_wdata_bf[7:6],          // [68:56]
//                              mbist_wdata_bf[4:2],                                                   // [55:53]
//                              1'b0,                                                                  // [52]
//                              mbist_wdata_bf[0],{3{mbist_wdata_bf[7:0]}},mbist_wdata_bf[7],          // [51:26]
//                              1'b0,                                                                  // [25]
//                              mbist_wdata_bf[6:0],                                                   // [24:18]
//                              1'b0,                                                                  // [17]
//                              mbist_wdata_bf[7:5],                                                   // [16:14]
//                              1'b0,                                                                  // [13]
//                              mbist_wdata_bf[4:0],mbist_wdata_bf[7:0]};                              // [12:0]
//
//
//

// Page mask and real bits must be zero for bist to avoid masking lower address and context bits.
assign mbist_wdata[68:0] = {    mbist_wdata_dup[1:0],mbist_wdata_dup[7:0], mbist_wdata_dup[7:5],          // [68:56]
                                mbist_wdata_dup[4:2],                                                   // [55:53]
                                1'b0,                                                                  // [52]
                                mbist_wdata_dup[0],{3{mbist_wdata_dup[7:0]}},mbist_wdata_dup[7],          // [51:26]
                                1'b0,                                                                  // [25]
                                mbist_wdata_dup[6:0],                                                   // [24:18]
                                1'b0,                                                                  // [17]
                                mbist_wdata_dup[7:5],                                                   // [16:14]
                                1'b0,                                                                  // [13]
                                mbist_wdata_dup[4:0],mbist_wdata_dup[7:0]};                              // [12:0]


assign data_mbist_wdata[37:0] = { mbist_wdata_bf[5:0],mbist_wdata_bf[7:2],                             // [37:26]
                                mbist_wdata_bf[1],                                                     // [25]
                                mbist_wdata_bf[0],mbist_wdata_bf[7:2],                                 // [24:18]
                                mbist_wdata_bf[1],                                                     // [17]
                                mbist_wdata_bf[0], mbist_wdata_bf[7:6],                                // [16:14]
                                mbist_wdata_bf[5],                                                     // [13]
                                mbist_wdata_bf[4:0],mbist_wdata_bf[7:0]};                              // [12:0]


// correct this
assign mbist_camdata[68:0]       =   ({{13{mbist_wdata_dup[2]}},{3{mbist_wdata_dup[1]}},mbist_wdata_dup[5],
                                       {26{mbist_wdata_dup[0]}},1'b0,mbist_wdata_dup[4],{6{mbist_wdata_dup[0]}}, 1'b0,
                                       {3{mbist_wdata_dup[0]}},1'b0,{13{mbist_wdata_dup[3]}}});          // CAMBIST match/write data

// correct this
assign mbist_camdata_shift[68:0] =   ({tte2_out[12:0],tte2_out[51:49],tte2_out[48],
                                       tte2_out[47:22],1'b0,1'b1,tte2_out[21:16], 1'b0,
                                       tte2_out[15:13],1'b0,tte2_out[12:0]});           // CAMBIST shift data


ifu_ftu_itd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_58c__width_56 test_data_mux0      (
        .din0   (mbist_camdata_shift[55:0]),           // CAMBIST shift data
        .din1   (mbist_camdata[55:0]),                 // CAMBIST match/write data
        .din2   (mbist_wdata[55:0]),                   // MEMBIST data
        .sel0   (init_or_shift_bf),
        .sel1   (not_init_and_run_bf),
        .sel2   (not_init_nor_run_bf),
        .dout   (bist_wdata[55:0])
);

ifu_ftu_itd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_14r__width_13 test_data_mux1      (
        .din0   (mbist_camdata_shift[68:56]),           // CAMBIST shift data
        .din1   (mbist_camdata[68:56]),                 // CAMBIST match/write data
        .din2   (mbist_wdata[68:56]),                   // MEMBIST data
        .sel0   (init_or_shift_bf),
        .sel1   (not_init_and_run_bf),
        .sel2   (not_init_nor_run_bf),
        .dout   (bist_wdata[68:56])
);

///////////////////////////////////////////////
// Parity generation for tte_tag
///////////////////////////////////////////////


// VA muxing done in ifu_ftu_agd_dp, and other "middle" parts of
// tag are not used in match
ifu_ftu_itd_dp_mux_macro__dmux_8x__mux_aonpe__ports_7__stack_58c__width_56 mx_tag0_d      (
	.din0	(tag_to_demap_d		[55:0]	),
	.din1	(tag_to_demap_c0	[55:0]	),
	.din2	(tag_to_demap_c1	[55:0]	),
	.din3	(tag_to_write		[55:0]	),
	.din4	(tag_to_write		[55:0]	),
	.din5	(bist_wdata     	[55:0]	),
	.din6	({default_pid		[2:0],
		  default_r		       ,
		  {39 {1'b0}}		       ,
		  default_context_0	[12:0]}),
	.sel0	(itc_sel_demap_tag_d		),
	.sel1	(itc_sel_demap_tag_c0		),
	.sel2	(itc_sel_demap_tag_c1		),
	.sel3	(itc_sel_write_tag		),
	.sel4	(itc_sel_write_tag_indexed	),
	.sel5	(itc_sel_mbist			),
	.sel6	(itc_sel_default			),
	.dout	(itd_tag_to_buf		[55:0]	)
);

assign itd_tag[55:0] = itd_tag_to_buf[55:0];

// buff_macro mx_tag0_d_buf (width=58, stack=60c) (
// 	.din 	(itd_tag_to_buf		[57:00]	),
// 	.dout	(itd_tag		[57:00]	));

ifu_ftu_itd_dp_mux_macro__dmux_6x__mux_aonpe__ports_7__stack_20r__width_19 mx_tag1_d      (
	.din0	({6'd0,tag_to_demap_d[68:56]}),
	.din1	({6'd0,tag_to_demap_c0[68:56]}),
	.din2	({6'd0,tag_to_demap_c1[68:56]}),
	.din3	({6'd0,tag_to_write[68:56]}),
	.din4	({tte2[53:48],tag_to_write[68:56]}),
	.din5   ({mbist_index[5:0],bist_wdata[68:56]}),
	.din6	({asi_addr_bf[8:3],default_context_1[12:0]}),
	.sel0	(itc_sel_demap_tag_d),
	.sel1	(itc_sel_demap_tag_c0),
	.sel2	(itc_sel_demap_tag_c1),
	.sel3	(itc_sel_write_tag),
	.sel4	(itc_sel_write_tag_indexed),
	.sel5	(itc_sel_mbist			),
	.sel6	(itc_sel_default			),
    	.dout	({itd_rw_index_to_buf[5:0],itd_tag_to_buf[68:56]})  
);

// buff_macro mx_tag1_d_buf (width=20, stack=20c) (
//     .din ( {prty_ctxt1_to_buf_,itd_rw_index_to_buf[5:0],itd_tag_to_buf[68:56]}), 
//     .dout({prty_ctxt1_,itd_rw_index[5:0],itd_tag[68:56]}) ) ;

// assign prty_ctxt1_       = prty_ctxt1_to_buf_; 
assign itd_rw_index[5:0] = itd_rw_index_to_buf[5:0] ;
assign itd_tag[68:56]    = itd_tag_to_buf[68:56] ;

ifu_ftu_itd_dp_msff_macro__stack_16r__width_16 mbist_in_reg  (
 .scan_in(mbist_in_reg_scanin),
 .scan_out(mbist_in_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1 ),  
 .din ( {mbi_addr[5:0],mbi_wdata[7:0],mbi_run,mbi_cambist_run}),
 .dout( {mbist_index_to_buf[5:0],mbist_wdata_to_buf[7:0],mbist_run_to_buf,cambist_run_bf}     ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_itd_dp_msff_macro__stack_8c__width_8 mbist_in_dup_reg  (
 .scan_in(mbist_in_dup_reg_scanin),
 .scan_out(mbist_in_dup_reg_scanout),
 .clk ( l2clk                ),
 .en  ( 1'b1 ),  
 .din ( mbi_wdata[7:0]),
 .dout( mbist_wdata_dup[7:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

ifu_ftu_itd_dp_buff_macro__stack_16r__width_15 mbist_in_buf  (
    .din( {mbist_index_to_buf[5:0],mbist_wdata_to_buf[7:0],mbist_run_to_buf}     ),
    .dout( {mbist_index[5:0],mbist_wdata_bf[7:0],mbist_run}     ));


///////////////////////////TTE data////////////////////////////////////////////
                                

ifu_ftu_itd_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep0  (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep0     ));


// Data is only needed for write, need a mux only for bist
ifu_ftu_itd_dp_mux_macro__mux_pgpe__ports_3__stack_38c__width_37 mx_itd_data     (
        .din0   ({31'b0,mbist_index[5:0]}),                  //CAM write data
	.din1	(data_mbist_wdata[36:0]),                    //MBIST write data
	.din2	(data_to_write[36:0]),                    //Functional write data
        .muxtst (tcu_muxtest_rep0),
	.sel0	(cambist_run_bf),
	.sel1	(mbist_run),
	.dout	(itd_data_to_buf[36:0]),
  .test(test)
);

assign itd_data[37:0] = {data_to_write[37], itd_data_to_buf[36:0]} ;

// buff_macro mx_itd_data_buf (width=39, stack=60c) (
// 	.din 	(itd_data_to_buf[38:0]),
// 	.dout	(itd_data[38:0]));

assign data_to_write[37:0] = 
       {tag_parity_out	       ,	// Parity for tag
	data_parity	       ,	// Parity
	tte2		[33:22],	// PA[39:28]
	tte2		[21:16],	// PA[27:22]
	tte1		[21   ],	// 27_22_V, PS_EQ_256M
	tte2		[15:10],	// PA[21:16]
	tte2		[42   ],	// 21_16_V, PS_GT_64K
	tte2		[9:7],	// VA[15:13]
	tte2		[38   ],	// 15_13_V, PS_GT_8K
	tte2		[5:0]		// NFO, IE, CP, E, P, W
	};	


 ifu_ftu_itd_dp_prty_macro__width_32 dprty0  (
	.din	(data_to_write[31:0]),
	.dout	(data_parity_0)
);
ifu_ftu_itd_dp_prty_macro__width_8 dprty1  (
	.din	({2'b00,data_to_write[35:32],itc_data_error_inj,1'b0}),
	.dout	(data_parity_1)
);

ifu_ftu_itd_dp_xor_macro__ports_2__width_1 pgen_data_xor   (
	.din0	(data_parity_0),
	.din1	(data_parity_1),
	.dout	(data_parity)
);

ifu_ftu_itd_dp_nor_macro__ports_2__width_1 shift_or_init   (
	.din0	(mbi_init_to_zero),
	.din1	(mbi_cambist_shift),
	.dout	(init_or_shift_nor)
);

ifu_ftu_itd_dp_inv_macro__width_1 shift_or_init_inv  (
         .din    (init_or_shift_nor),
         .dout   (init_or_shift)
 );

ifu_ftu_itd_dp_nor_macro__ports_2__width_1 not_init_nor_run_nor   (
	.din0	(init_or_shift),
	.din1	(mbi_cambist_run),
	.dout	(not_init_nor_run)
);

ifu_ftu_itd_dp_and_macro__ports_2__width_1 not_init_and_run_and   (
	.din0	(init_or_shift_nor),
	.din1	(mbi_cambist_run),
	.dout	(not_init_and_run)
);

// buff_macro dprty_buf (width=1) (
// 	.din	(data_parity),
// 	.dout	(data_parity_buf)
// );


assign itd_demap_control1[1:0] =
       tte1[44:43];

// Write context 0 if a write with use_context_0 on
// assign itc_sel_write_tag_c0 =
//        (wr_vld  &                  demap_c2[00]) ;
// 
// Write context 1 if a write with use_context_1 on
// assign itc_sel_write_tag_c1 =
//        (wr_vld  &                  demap_c2[01] & ~demap_c2[00]) ;


ifu_ftu_itd_dp_and_macro__ports_2__stack_2l__width_1 write_tag_c0_and    (
        .din0   (itc_write_next),
        .din1   (itd_demap_control1[0]),
        .dout   (sel_write_tag_c0)
);

ifu_ftu_itd_dp_and_macro__ports_3__stack_4l__width_1 write_tag_c1_and    (
        .din0   (itc_write_next),
        .din1   (demap_control1_0_),
        .din2   (itd_demap_control1[1]),
        .dout   (sel_write_tag_c1)
);

// assign sel_write_tag_t1 = write_next_ ;
// 
 ifu_ftu_itd_dp_inv_macro__width_1 sel_write_inv  (
         .din    (itd_demap_control1[0]),
         .dout   (demap_control1_0_)
 );


// assign se = tcu_scan_en ;
// fixscan start:
assign tte0_lat_scanin           = scan_in                  ;
assign tte1_lat_scanin           = tte0_lat_scanout         ;
assign access_tag_reg_scanin     = tte1_lat_scanout         ;
assign access_tag_reg0_scanin    = access_tag_reg_scanout   ;
assign write_context_0_reg_scanin = access_tag_reg0_scanout  ;
assign write_context_1_reg_scanin = write_context_0_reg_scanout;
assign context_to_write_reg_scanin = write_context_1_reg_scanout;
assign tte2_lat_scanin           = context_to_write_reg_scanout;
assign mbist_in_reg_scanin       = tte2_lat_scanout         ;
assign mbist_in_dup_reg_scanin   = mbist_in_reg_scanout     ;
assign scan_out                  = mbist_in_dup_reg_scanout ;
// fixscan end:
endmodule	
	
	
//
//   buff macro
//
//


module ifu_ftu_itd_dp_buff_macro__dbuff_32x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__mux_aonpe__ports_2__stack_60c__width_55 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [54:0] din0;
  input sel0;
  input [54:0] din1;
  input sel1;
  output [54:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(55)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[54:0]),
  .in1(din1[54:0]),
.dout(dout[54:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_msff_macro__stack_60c__width_56 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [54:0] so;

  input [55:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [55:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(56)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[55:0]),
.si({scan_in,so[54:0]}),
.so({so[54:0],scan_out}),
.q(dout[55:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_msff_macro__stack_60c__width_59 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [57:0] so;

  input [58:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [58:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(59)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[58:0]),
.si({scan_in,so[57:0]}),
.so({so[57:0],scan_out}),
.q(dout[58:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__mux_aodec__ports_8__stack_4r__width_3 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  input [2:0] din3;
  input [2:0] din4;
  input [2:0] din5;
  input [2:0] din6;
  input [2:0] din7;
  input [2:0] sel;
  output [2:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(3)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[2:0]),
  .in1(din1[2:0]),
  .in2(din2[2:0]),
  .in3(din3[2:0]),
  .in4(din4[2:0]),
  .in5(din5[2:0]),
  .in6(din6[2:0]),
  .in7(din7[2:0]),
.dout(dout[2:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_itd_dp_buff_macro__stack_4c__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


buff #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__mux_aope__ports_3__stack_14r__width_14 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [13:0] din0;
  input [13:0] din1;
  input [13:0] din2;
  input sel0;
  input sel1;
  output [13:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(14)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[13:0]),
  .in1(din1[13:0]),
  .in2(din2[13:0]),
.dout(dout[13:0])
);


endmodule


//
//   invert macro
//
//


module ifu_ftu_itd_dp_inv_macro__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


//
//   invert macro
//
//


module ifu_ftu_itd_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ftu_itd_dp_and_macro__ports_2__stack_16l__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output [15:0] dout;


and2 #(16)  d0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__left_2__mux_pgpe__ports_2__stack_60c__width_40 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [39:0] din0;
  input [39:0] din1;
  input sel0;
  output [39:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(40)  d0_0 (
  .sel(psel1),
  .in0(din0[39:0]),
  .in1(din1[39:0]),
.dout(dout[39:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module ifu_ftu_itd_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module ifu_ftu_itd_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module ifu_ftu_itd_dp_xor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__mux_pgpe__ports_2__stack_2r__width_1 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [0:0] din0;
  input [0:0] din1;
  input sel0;
  output [0:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(1)  d0_0 (
  .sel(psel1),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
.dout(dout[0:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module ifu_ftu_itd_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_itd_dp_buff_macro__width_6 (
  din, 
  dout);
  input [5:0] din;
  output [5:0] dout;


buff #(6)  d0_0 (
.in(din[5:0]),
.out(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_msff_macro__stack_14c__width_13 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [11:0] so;

  input [12:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [12:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(13)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[12:0]),
.si({scan_in,so[11:0]}),
.so({so[11:0],scan_out}),
.q(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_msff_macro__stack_14c__width_14 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [12:0] so;

  input [13:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [13:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_msff_macro__mux_aope__ports_3__stack_60c__width_53 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [52:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [51:0] so;

  input [52:0] din0;
  input [52:0] din1;
  input [52:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [52:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(53)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[52:0]),
  .in1(din1[52:0]),
  .in2(din2[52:0]),
.dout(muxout[52:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(53)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[52:0]),
.si({scan_in,so[51:0]}),
.so({so[51:0],scan_out}),
.q(dout[52:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_58c__width_56 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [55:0] din0;
  input sel0;
  input [55:0] din1;
  input sel1;
  input [55:0] din2;
  input sel2;
  output [55:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(56)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[55:0]),
  .in1(din1[55:0]),
  .in2(din2[55:0]),
.dout(dout[55:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_14r__width_13 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [12:0] din0;
  input sel0;
  input [12:0] din1;
  input sel1;
  input [12:0] din2;
  input sel2;
  output [12:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(13)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
  .in2(din2[12:0]),
.dout(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__dmux_8x__mux_aonpe__ports_7__stack_58c__width_56 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;

  input [55:0] din0;
  input sel0;
  input [55:0] din1;
  input sel1;
  input [55:0] din2;
  input sel2;
  input [55:0] din3;
  input sel3;
  input [55:0] din4;
  input sel4;
  input [55:0] din5;
  input sel5;
  input [55:0] din6;
  input sel6;
  output [55:0] dout;


cl_dp1_muxbuff7_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6)
);
mux7s #(56)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .in0(din0[55:0]),
  .in1(din1[55:0]),
  .in2(din2[55:0]),
  .in3(din3[55:0]),
  .in4(din4[55:0]),
  .in5(din5[55:0]),
  .in6(din6[55:0]),
.dout(dout[55:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__dmux_6x__mux_aonpe__ports_7__stack_20r__width_19 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;

  input [18:0] din0;
  input sel0;
  input [18:0] din1;
  input sel1;
  input [18:0] din2;
  input sel2;
  input [18:0] din3;
  input sel3;
  input [18:0] din4;
  input sel4;
  input [18:0] din5;
  input sel5;
  input [18:0] din6;
  input sel6;
  output [18:0] dout;


cl_dp1_muxbuff7_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6)
);
mux7s #(19)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .in0(din0[18:0]),
  .in1(din1[18:0]),
  .in2(din2[18:0]),
  .in3(din3[18:0]),
  .in4(din4[18:0]),
  .in5(din5[18:0]),
  .in6(din6[18:0]),
.dout(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_msff_macro__stack_16r__width_16 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [14:0] so;

  input [15:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [15:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_msff_macro__stack_8c__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_itd_dp_buff_macro__stack_16r__width_15 (
  din, 
  dout);
  input [14:0] din;
  output [14:0] dout;


buff #(15)  d0_0 (
.in(din[14:0]),
.out(dout[14:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ftu_itd_dp_buff_macro__dbuff_48x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ftu_itd_dp_mux_macro__mux_pgpe__ports_3__stack_38c__width_37 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [36:0] din0;
  input [36:0] din1;
  input [36:0] din2;
  input sel0;
  input sel1;
  input muxtst;
  input test;
  output [36:0] dout;


cl_dp1_penc3_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
  .test(test)
);

mux3 #(37)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[36:0]),
  .in1(din1[36:0]),
  .in2(din2[36:0]),
.dout(dout[36:0]),
  .muxtst(muxtst)
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module ifu_ftu_itd_dp_nor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ftu_itd_dp_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ftu_itd_dp_and_macro__ports_2__stack_2l__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ftu_itd_dp_and_macro__ports_3__stack_4l__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


and3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_red_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_red_ctl (
  efu_spc_fuse_data, 
  efu_spc_fuse_ixfer_en, 
  efu_spc_fuse_iclr, 
  io_cmp_sync_en, 
  cmp_io_sync_en, 
  spc_efu_fuse_idata, 
  spc_efu_fuse_ixfer_en, 
  hdr_sram_rvalue, 
  hdr_sram_rid, 
  hdr_sram_wr_en, 
  hdr_sram_red_clr, 
  sram_hdr_read_data, 
  l2clk, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_in, 
  scan_out);
wire [4:0] rval_unused;
wire [6:0] rid_unused;


// EFU to SRAM header
input           efu_spc_fuse_data;   // Efuse to dest data info
input           efu_spc_fuse_ixfer_en;// Efuse to dest data valid
input           efu_spc_fuse_iclr;    // EFuse to dest clear corresponding redudancy register
input           io_cmp_sync_en;
input           cmp_io_sync_en;

// SRAM header to EFU
output          spc_efu_fuse_idata;    // Dest to EFU read data return
output          spc_efu_fuse_ixfer_en; // Dest to EFU read data return valid

// SRAM header to SRAM
output  [5:0]   hdr_sram_rvalue;        // Redudancy Value to be written
				        // to SRAM red reg
output  [3:0]   hdr_sram_rid;           // Redudancy ID to address SRAM
					// red reg
output          hdr_sram_wr_en;         // Redudancy register write
					// enable to write to red reg
output          hdr_sram_red_clr;       // Redudancy register clear
					//

// SRAM to SRAM header
input	[5:0]	sram_hdr_read_data;     // Redudancy Read data from SRAM


// other common signals
input           l2clk;
input           tcu_pce_ov;
input           spc_aclk;
input           spc_bclk;
input           tcu_scan_en;
input           scan_in;
output          scan_out;

n2_efuhdr1_ctl sram_header_instance
        (
        // All the I/o ports to and from EFU <-> cluster
        .efu_hdr_write_data        (efu_spc_fuse_data),
        .efu_hdr_xfer_en           (efu_spc_fuse_ixfer_en),
        .efu_hdr_clr               (efu_spc_fuse_iclr),
        .hdr_efu_read_data         (spc_efu_fuse_idata),
        .io_cmp_sync_en		   (io_cmp_sync_en),
        .cmp_io_sync_en		   (cmp_io_sync_en),
        .hdr_efu_xfer_en           (spc_efu_fuse_ixfer_en),
        // All other general signals for DFT and clocks
        .scan_in                   (scan_in),
        .scan_out                  (scan_out),
        .l2clk                     (l2clk),
        .tcu_pce_ov                (tcu_pce_ov),
        .tcu_aclk                  (spc_aclk),
        .tcu_bclk                  (spc_bclk),
        .tcu_scan_en               (tcu_scan_en),
        .tcu_clk_stop              (1'b0),
        // All the I/o ports to and from SRAM
        .sram_hdr_read_data        ({5'b0,sram_hdr_read_data[5:0]}),
        .hdr_sram_rvalue           ({rval_unused[4:0],hdr_sram_rvalue[5:0]}),
        .hdr_sram_rid              ({rid_unused[6:0],hdr_sram_rid[3:0]}),
        .hdr_sram_wr_en            (hdr_sram_wr_en),
        .hdr_sram_red_clr          (hdr_sram_red_clr)
        );


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_red_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_red_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_red_ctl_msff_ctl_macro__en_1__width_4 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}});


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_red_ctl_msff_ctl_macro__en_1__width_22 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [21:0] fdin;
wire [20:0] so;

  input [21:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [21:0] dout;
  output scan_out;
assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}});


dff #(22)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[21:0]),
.si({scan_in,so[20:0]}),
.so({so[20:0],scan_out}),
.q(dout[21:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_red_ctl_msff_ctl_macro__en_1__width_1 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_red_ctl_msff_ctl_macro__en_1__width_5 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}});


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ftu_red_ctl_spare_ctl_macro__num_4 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));
assign scan_out = so_3;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_tfc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_tfc_ctl (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  spc_aclk, 
  spc_bclk, 
  tcu_pce_ov, 
  ftu_thr0_redirect_bf, 
  ftu_thr1_redirect_bf, 
  ftu_thr2_redirect_bf, 
  ftu_thr3_redirect_bf, 
  ftu_thr4_redirect_bf, 
  ftu_thr5_redirect_bf, 
  ftu_thr6_redirect_bf, 
  ftu_thr7_redirect_bf, 
  agc_thr0_err_detect_c, 
  agc_thr1_err_detect_c, 
  agc_thr2_err_detect_c, 
  agc_thr3_err_detect_c, 
  agc_thr4_err_detect_c, 
  agc_thr5_err_detect_c, 
  agc_thr6_err_detect_c, 
  agc_thr7_err_detect_c, 
  ftu_thr0_inv_req_c, 
  ftu_thr1_inv_req_c, 
  ftu_thr2_inv_req_c, 
  ftu_thr3_inv_req_c, 
  ftu_thr4_inv_req_c, 
  ftu_thr5_inv_req_c, 
  ftu_thr6_inv_req_c, 
  ftu_thr7_inv_req_c, 
  agc_thr0_lsu_no_ic_miss, 
  agc_thr1_lsu_no_ic_miss, 
  agc_thr2_lsu_no_ic_miss, 
  agc_thr3_lsu_no_ic_miss, 
  agc_thr4_lsu_no_ic_miss, 
  agc_thr5_lsu_no_ic_miss, 
  agc_thr6_lsu_no_ic_miss, 
  agc_thr7_lsu_no_ic_miss, 
  agc_thr0_tlu_redirect_bf, 
  agc_thr1_tlu_redirect_bf, 
  agc_thr2_tlu_redirect_bf, 
  agc_thr3_tlu_redirect_bf, 
  agc_thr4_tlu_redirect_bf, 
  agc_thr5_tlu_redirect_bf, 
  agc_thr6_tlu_redirect_bf, 
  agc_thr7_tlu_redirect_bf, 
  ftp_thr0_go_to_sf_wait, 
  ftp_thr1_go_to_sf_wait, 
  ftp_thr2_go_to_sf_wait, 
  ftp_thr3_go_to_sf_wait, 
  ftp_thr4_go_to_sf_wait, 
  ftp_thr5_go_to_sf_wait, 
  ftp_thr6_go_to_sf_wait, 
  ftp_thr7_go_to_sf_wait, 
  cmu_inval_ack, 
  cmu_rst_dupmiss, 
  cmu_null_st, 
  cmu_dupmiss_st, 
  cmu_thr0_data_ready, 
  cmu_thr1_data_ready, 
  cmu_thr2_data_ready, 
  cmu_thr3_data_ready, 
  cmu_thr4_data_ready, 
  cmu_thr5_data_ready, 
  cmu_thr6_data_ready, 
  cmu_thr7_data_ready, 
  agc_thr0_cmiss_stm_c, 
  agc_thr1_cmiss_stm_c, 
  agc_thr2_cmiss_stm_c, 
  agc_thr3_cmiss_stm_c, 
  agc_thr4_cmiss_stm_c, 
  agc_thr5_cmiss_stm_c, 
  agc_thr6_cmiss_stm_c, 
  agc_thr7_cmiss_stm_c, 
  agc_thr0_itb_miss_c, 
  agc_thr1_itb_miss_c, 
  agc_thr2_itb_miss_c, 
  agc_thr3_itb_miss_c, 
  agc_thr4_itb_miss_c, 
  agc_thr5_itb_miss_c, 
  agc_thr6_itb_miss_c, 
  agc_thr7_itb_miss_c, 
  cmu_any_data_ready, 
  ftp_reset_fill_wait, 
  ftp_thr0_room_is_less_t_3, 
  ftp_thr1_room_is_less_t_3, 
  ftp_thr2_room_is_less_t_3, 
  ftp_thr3_room_is_less_t_3, 
  ftp_thr4_room_is_less_t_3, 
  ftp_thr5_room_is_less_t_3, 
  ftp_thr6_room_is_less_t_3, 
  ftp_thr7_room_is_less_t_3, 
  itc_demap_next, 
  tlu_flush_ifu, 
  asi_wr_request, 
  asi_rd_request, 
  ftp_asi_rd_done, 
  ftp_asi_wr_done, 
  tsm_thr0_fill_rdy0, 
  tsm_thr1_fill_rdy0, 
  tsm_thr2_fill_rdy0, 
  tsm_thr3_fill_rdy0, 
  tsm_thr4_fill_rdy0, 
  tsm_thr5_fill_rdy0, 
  tsm_thr6_fill_rdy0, 
  tsm_thr7_fill_rdy0, 
  tsm_thr0_no_new_miss, 
  tsm_thr1_no_new_miss, 
  tsm_thr2_no_new_miss, 
  tsm_thr3_no_new_miss, 
  tsm_thr4_no_new_miss, 
  tsm_thr5_no_new_miss, 
  tsm_thr6_no_new_miss, 
  tsm_thr7_no_new_miss, 
  tsm_thr0_ignore_by_pass, 
  tsm_thr1_ignore_by_pass, 
  tsm_thr2_ignore_by_pass, 
  tsm_thr3_ignore_by_pass, 
  tsm_thr4_ignore_by_pass, 
  tsm_thr5_ignore_by_pass, 
  tsm_thr6_ignore_by_pass, 
  tsm_thr7_ignore_by_pass, 
  tsm_thr0_ready_hp_bf_in, 
  tsm_thr1_ready_hp_bf_in, 
  tsm_thr2_ready_hp_bf_in, 
  tsm_thr3_ready_hp_bf_in, 
  tsm_thr4_ready_hp_bf_in, 
  tsm_thr5_ready_hp_bf_in, 
  tsm_thr6_ready_hp_bf_in, 
  tsm_thr7_ready_hp_bf_in, 
  ftu_ifu_quiesce, 
  scan_out) ;
wire pce_ov;
wire stop;
wire l1clk;
wire tsm0_scanin;
wire tsm0_scanout;
wire tsm1_scanin;
wire tsm1_scanout;
wire tsm2_scanin;
wire tsm2_scanout;
wire tsm3_scanin;
wire tsm3_scanout;
wire tsm4_scanin;
wire tsm4_scanout;
wire tsm5_scanin;
wire tsm5_scanout;
wire tsm6_scanin;
wire tsm6_scanout;
wire tsm7_scanin;
wire tsm7_scanout;
wire se;


input tcu_scan_en ;
input   l2clk;
input  	scan_in;
input  	spc_aclk;
input  	spc_bclk;
input  	tcu_pce_ov;		// scan signals

input   ftu_thr0_redirect_bf;
input   ftu_thr1_redirect_bf;
input   ftu_thr2_redirect_bf;
input   ftu_thr3_redirect_bf;
input   ftu_thr4_redirect_bf;
input   ftu_thr5_redirect_bf;
input   ftu_thr6_redirect_bf;
input   ftu_thr7_redirect_bf;


input   agc_thr0_err_detect_c ;
input   agc_thr1_err_detect_c ;
input   agc_thr2_err_detect_c ;
input   agc_thr3_err_detect_c ;
input   agc_thr4_err_detect_c ;
input   agc_thr5_err_detect_c ;
input   agc_thr6_err_detect_c ;
input   agc_thr7_err_detect_c ;

input   ftu_thr0_inv_req_c ;
input   ftu_thr1_inv_req_c ;
input   ftu_thr2_inv_req_c ;
input   ftu_thr3_inv_req_c ;
input   ftu_thr4_inv_req_c ;
input   ftu_thr5_inv_req_c ;
input   ftu_thr6_inv_req_c ;
input   ftu_thr7_inv_req_c ;
        

input   agc_thr0_lsu_no_ic_miss ;
input   agc_thr1_lsu_no_ic_miss ;
input   agc_thr2_lsu_no_ic_miss ;
input   agc_thr3_lsu_no_ic_miss ;
input   agc_thr4_lsu_no_ic_miss ;
input   agc_thr5_lsu_no_ic_miss ;
input   agc_thr6_lsu_no_ic_miss ;
input   agc_thr7_lsu_no_ic_miss ;

input   agc_thr0_tlu_redirect_bf;
input   agc_thr1_tlu_redirect_bf;
input   agc_thr2_tlu_redirect_bf;
input   agc_thr3_tlu_redirect_bf;
input   agc_thr4_tlu_redirect_bf;
input   agc_thr5_tlu_redirect_bf;
input   agc_thr6_tlu_redirect_bf;
input   agc_thr7_tlu_redirect_bf;

input   ftp_thr0_go_to_sf_wait;
input   ftp_thr1_go_to_sf_wait;
input   ftp_thr2_go_to_sf_wait;
input   ftp_thr3_go_to_sf_wait;
input   ftp_thr4_go_to_sf_wait;
input   ftp_thr5_go_to_sf_wait;
input   ftp_thr6_go_to_sf_wait;
input   ftp_thr7_go_to_sf_wait;

input   [7:0] cmu_inval_ack;
input   [7:0] cmu_rst_dupmiss;
        

input  [7:0] cmu_null_st;
input  [7:0] cmu_dupmiss_st;
   
input   cmu_thr0_data_ready;
input   cmu_thr1_data_ready;
input   cmu_thr2_data_ready;
input   cmu_thr3_data_ready;
input   cmu_thr4_data_ready;
input   cmu_thr5_data_ready;
input   cmu_thr6_data_ready;
input   cmu_thr7_data_ready;
        
input   agc_thr0_cmiss_stm_c;
input   agc_thr1_cmiss_stm_c;
input   agc_thr2_cmiss_stm_c;
input   agc_thr3_cmiss_stm_c;
input   agc_thr4_cmiss_stm_c;
input   agc_thr5_cmiss_stm_c;
input   agc_thr6_cmiss_stm_c;
input   agc_thr7_cmiss_stm_c;
        
input   agc_thr0_itb_miss_c;
input   agc_thr1_itb_miss_c;
input   agc_thr2_itb_miss_c;
input   agc_thr3_itb_miss_c;
input   agc_thr4_itb_miss_c;
input   agc_thr5_itb_miss_c;
input   agc_thr6_itb_miss_c;
input   agc_thr7_itb_miss_c;


input   cmu_any_data_ready ;
input   ftp_reset_fill_wait;
// input   ftp_go_to_fill_wait;
// input   ftp_thr0_go_to_fill_wait;
// input   ftp_thr1_go_to_fill_wait;
// input   ftp_thr2_go_to_fill_wait;
// input   ftp_thr3_go_to_fill_wait;
// input   ftp_thr4_go_to_fill_wait;
// input   ftp_thr5_go_to_fill_wait;
// input   ftp_thr6_go_to_fill_wait;
// input   ftp_thr7_go_to_fill_wait;


input   ftp_thr0_room_is_less_t_3;
input   ftp_thr1_room_is_less_t_3;
input   ftp_thr2_room_is_less_t_3;
input   ftp_thr3_room_is_less_t_3;
input   ftp_thr4_room_is_less_t_3;
input   ftp_thr5_room_is_less_t_3;
input   ftp_thr6_room_is_less_t_3;
input   ftp_thr7_room_is_less_t_3;

// input   agc_thr0_rst_dmiss_bf;
// input   agc_thr1_rst_dmiss_bf;
// input   agc_thr2_rst_dmiss_bf;
// input   agc_thr3_rst_dmiss_bf;
// input   agc_thr4_rst_dmiss_bf;
// input   agc_thr5_rst_dmiss_bf;
// input   agc_thr6_rst_dmiss_bf;
// input   agc_thr7_rst_dmiss_bf;
//         
        
input   itc_demap_next;
input [7:0]  tlu_flush_ifu;

input        asi_wr_request ;
input        asi_rd_request ;
input        ftp_asi_rd_done ;
input        ftp_asi_wr_done ;


output  tsm_thr0_fill_rdy0  ;
output  tsm_thr1_fill_rdy0  ;
output  tsm_thr2_fill_rdy0  ;
output  tsm_thr3_fill_rdy0  ;
output  tsm_thr4_fill_rdy0  ;
output  tsm_thr5_fill_rdy0  ;
output  tsm_thr6_fill_rdy0  ;
output  tsm_thr7_fill_rdy0  ;
 
output  tsm_thr0_no_new_miss  ;
output  tsm_thr1_no_new_miss  ;
output  tsm_thr2_no_new_miss  ;
output  tsm_thr3_no_new_miss  ;
output  tsm_thr4_no_new_miss  ;
output  tsm_thr5_no_new_miss  ;
output  tsm_thr6_no_new_miss  ;
output  tsm_thr7_no_new_miss  ;

output  tsm_thr0_ignore_by_pass ;
output  tsm_thr1_ignore_by_pass ;
output  tsm_thr2_ignore_by_pass ;
output  tsm_thr3_ignore_by_pass ;
output  tsm_thr4_ignore_by_pass ;
output  tsm_thr5_ignore_by_pass ;
output  tsm_thr6_ignore_by_pass ;
output  tsm_thr7_ignore_by_pass ;
   
   
output  tsm_thr0_ready_hp_bf_in;
output  tsm_thr1_ready_hp_bf_in;
output  tsm_thr2_ready_hp_bf_in;
output  tsm_thr3_ready_hp_bf_in;
output  tsm_thr4_ready_hp_bf_in;
output  tsm_thr5_ready_hp_bf_in;
output  tsm_thr6_ready_hp_bf_in;
output  tsm_thr7_ready_hp_bf_in;
        
        
output  [7:0] ftu_ifu_quiesce; 

output  scan_out;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
// end scan

ifu_ftu_tfc_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


ifu_ftu_tsm_ctl tsm0 (
   .scan_in(tsm0_scanin),
   .scan_out(tsm0_scanout),
   .l1clk(l1clk), 
   .agc_redirect_bf(ftu_thr0_redirect_bf),
   .agc_tlu_redirect_bf(agc_thr0_tlu_redirect_bf),
   .thrx_go_to_sf_wait(ftp_thr0_go_to_sf_wait),
   .inv_req_c(ftu_thr0_inv_req_c),
   .err_detect_c(agc_thr0_err_detect_c),
   .cmu_inv_req_ack(cmu_inval_ack[0]),
   .thrx_is_null(cmu_null_st[0]),
   .thrx_is_dupmiss(cmu_dupmiss_st[0]),
   .ftu_agc_cmiss_c(agc_thr0_cmiss_stm_c),
   .data_ready(cmu_thr0_data_ready),
   .ftp_reset_fill_wait(ftp_reset_fill_wait),
   .reset_dmiss_bf(cmu_rst_dupmiss[0]),
   .ftp_room_is_less_t_3(ftp_thr0_room_is_less_t_3),
   .itb_miss_c(agc_thr0_itb_miss_c),
   .tlu_flush_thrx_ifu(tlu_flush_ifu[0]),
   .cmu_any_data_ready(cmu_any_data_ready),
   .agc_lsu_no_ic_miss(agc_thr0_lsu_no_ic_miss),
   .next_thrx_is_ready(tsm_thr0_ready_hp_bf_in),
   .tsm_fill_rdy0(tsm_thr0_fill_rdy0),
   .tsm_no_new_miss(tsm_thr0_no_new_miss),
   .tsm_thrx_ifu_quiesce(ftu_ifu_quiesce[0]),
   .tsm_ignore_by_pass(tsm_thr0_ignore_by_pass),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asi_rd_request(asi_rd_request),
  .asi_wr_request(asi_wr_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .itc_demap_next(itc_demap_next) 
);


ifu_ftu_tsm_ctl tsm1 (
   .scan_in(tsm1_scanin),
   .scan_out(tsm1_scanout),
   .l1clk(l1clk),
   .agc_redirect_bf(ftu_thr1_redirect_bf),
   .agc_tlu_redirect_bf(agc_thr1_tlu_redirect_bf),
   .thrx_go_to_sf_wait(ftp_thr1_go_to_sf_wait),
   .inv_req_c(ftu_thr1_inv_req_c),
   .err_detect_c(agc_thr1_err_detect_c),
   .cmu_inv_req_ack(cmu_inval_ack[1]),
   .ftu_agc_cmiss_c(agc_thr1_cmiss_stm_c),
   .thrx_is_null(cmu_null_st[1]),
   .thrx_is_dupmiss(cmu_dupmiss_st[1]),
   .data_ready(cmu_thr1_data_ready),
   .ftp_reset_fill_wait(ftp_reset_fill_wait),
   .reset_dmiss_bf(cmu_rst_dupmiss[1]),
   .ftp_room_is_less_t_3(ftp_thr1_room_is_less_t_3),
   .itb_miss_c(agc_thr1_itb_miss_c),
   .tlu_flush_thrx_ifu(tlu_flush_ifu[1]),
   .cmu_any_data_ready(cmu_any_data_ready),
   .agc_lsu_no_ic_miss(agc_thr1_lsu_no_ic_miss),
   .next_thrx_is_ready(tsm_thr1_ready_hp_bf_in),
   .tsm_fill_rdy0(tsm_thr1_fill_rdy0),
   .tsm_no_new_miss(tsm_thr1_no_new_miss),
   .tsm_thrx_ifu_quiesce(ftu_ifu_quiesce[1]),
   .tsm_ignore_by_pass(tsm_thr1_ignore_by_pass),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asi_rd_request(asi_rd_request),
  .asi_wr_request(asi_wr_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .itc_demap_next(itc_demap_next)
);

ifu_ftu_tsm_ctl tsm2 (
   .scan_in(tsm2_scanin),
   .scan_out(tsm2_scanout),
   .l1clk(l1clk),
   .agc_redirect_bf(ftu_thr2_redirect_bf),
   .agc_tlu_redirect_bf(agc_thr2_tlu_redirect_bf),
   .thrx_go_to_sf_wait(ftp_thr2_go_to_sf_wait),
   .inv_req_c(ftu_thr2_inv_req_c),
   .err_detect_c(agc_thr2_err_detect_c),
   .thrx_is_null(cmu_null_st[2]),
   .thrx_is_dupmiss(cmu_dupmiss_st[2]),
   .cmu_inv_req_ack(cmu_inval_ack[2]),
   .ftu_agc_cmiss_c(agc_thr2_cmiss_stm_c),
   .data_ready(cmu_thr2_data_ready),
   .ftp_reset_fill_wait(ftp_reset_fill_wait),
   .reset_dmiss_bf(cmu_rst_dupmiss[2]),
   .ftp_room_is_less_t_3(ftp_thr2_room_is_less_t_3),
   .itb_miss_c(agc_thr2_itb_miss_c),
   .tlu_flush_thrx_ifu(tlu_flush_ifu[2]),
   .cmu_any_data_ready(cmu_any_data_ready),
   .agc_lsu_no_ic_miss(agc_thr2_lsu_no_ic_miss),
   .next_thrx_is_ready(tsm_thr2_ready_hp_bf_in),
   .tsm_fill_rdy0(tsm_thr2_fill_rdy0),
   .tsm_no_new_miss(tsm_thr2_no_new_miss),
   .tsm_thrx_ifu_quiesce(ftu_ifu_quiesce[2]),
   .tsm_ignore_by_pass(tsm_thr2_ignore_by_pass),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asi_rd_request(asi_rd_request),
  .asi_wr_request(asi_wr_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .itc_demap_next(itc_demap_next) 
);


ifu_ftu_tsm_ctl tsm3 (
   .scan_in(tsm3_scanin),
   .scan_out(tsm3_scanout),
   .l1clk(l1clk),
   .agc_redirect_bf(ftu_thr3_redirect_bf),
   .agc_tlu_redirect_bf(agc_thr3_tlu_redirect_bf),
   .thrx_go_to_sf_wait(ftp_thr3_go_to_sf_wait),
   .inv_req_c(ftu_thr3_inv_req_c),
   .err_detect_c(agc_thr3_err_detect_c),
   .cmu_inv_req_ack(cmu_inval_ack[3]),
   .thrx_is_null(cmu_null_st[3]),
   .thrx_is_dupmiss(cmu_dupmiss_st[3]),
   .ftu_agc_cmiss_c(agc_thr3_cmiss_stm_c),
   .data_ready(cmu_thr3_data_ready),
   .ftp_reset_fill_wait(ftp_reset_fill_wait),
   .reset_dmiss_bf(cmu_rst_dupmiss[3]),
   .ftp_room_is_less_t_3(ftp_thr3_room_is_less_t_3),
   .itb_miss_c(agc_thr3_itb_miss_c),
   .tlu_flush_thrx_ifu(tlu_flush_ifu[3]),
   .cmu_any_data_ready(cmu_any_data_ready),
   .agc_lsu_no_ic_miss(agc_thr3_lsu_no_ic_miss),
   .next_thrx_is_ready(tsm_thr3_ready_hp_bf_in),
   .tsm_fill_rdy0(tsm_thr3_fill_rdy0),
   .tsm_no_new_miss(tsm_thr3_no_new_miss),
   .tsm_thrx_ifu_quiesce(ftu_ifu_quiesce[3]),
   .tsm_ignore_by_pass(tsm_thr3_ignore_by_pass),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asi_rd_request(asi_rd_request),
  .asi_wr_request(asi_wr_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .itc_demap_next(itc_demap_next) 
);


ifu_ftu_tsm_ctl tsm4 (
   .scan_in(tsm4_scanin),
   .scan_out(tsm4_scanout),
   .l1clk(l1clk),
   .agc_redirect_bf(ftu_thr4_redirect_bf),
   .agc_tlu_redirect_bf(agc_thr4_tlu_redirect_bf),
   .thrx_go_to_sf_wait(ftp_thr4_go_to_sf_wait),
   .inv_req_c(ftu_thr4_inv_req_c),
   .err_detect_c(agc_thr4_err_detect_c),
   .cmu_inv_req_ack(cmu_inval_ack[4]),
   .thrx_is_null(cmu_null_st[4]),
   .thrx_is_dupmiss(cmu_dupmiss_st[4]),
   .ftu_agc_cmiss_c(agc_thr4_cmiss_stm_c),
   .data_ready(cmu_thr4_data_ready),
   .ftp_reset_fill_wait(ftp_reset_fill_wait),
   .reset_dmiss_bf(cmu_rst_dupmiss[4]),
   .ftp_room_is_less_t_3(ftp_thr4_room_is_less_t_3),
   .itb_miss_c(agc_thr4_itb_miss_c),
   .tlu_flush_thrx_ifu(tlu_flush_ifu[4]),
   .cmu_any_data_ready(cmu_any_data_ready),
   .agc_lsu_no_ic_miss(agc_thr4_lsu_no_ic_miss),
   .next_thrx_is_ready(tsm_thr4_ready_hp_bf_in),
   .tsm_fill_rdy0(tsm_thr4_fill_rdy0),
   .tsm_ignore_by_pass(tsm_thr4_ignore_by_pass),
   .tsm_thrx_ifu_quiesce(ftu_ifu_quiesce[4]),
   .tsm_no_new_miss(tsm_thr4_no_new_miss),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asi_rd_request(asi_rd_request),
  .asi_wr_request(asi_wr_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .itc_demap_next(itc_demap_next)
);


ifu_ftu_tsm_ctl tsm5 (
   .scan_in(tsm5_scanin),
   .scan_out(tsm5_scanout),
   .l1clk(l1clk),
   .agc_redirect_bf(ftu_thr5_redirect_bf),
   .thrx_go_to_sf_wait(ftp_thr5_go_to_sf_wait),
   .agc_tlu_redirect_bf(agc_thr5_tlu_redirect_bf),
   .inv_req_c(ftu_thr5_inv_req_c),
   .err_detect_c(agc_thr5_err_detect_c),
   .cmu_inv_req_ack(cmu_inval_ack[5]),
   .thrx_is_null(cmu_null_st[5]),
   .thrx_is_dupmiss(cmu_dupmiss_st[5]),
   .ftu_agc_cmiss_c(agc_thr5_cmiss_stm_c),
   .data_ready(cmu_thr5_data_ready),
   .ftp_reset_fill_wait(ftp_reset_fill_wait),
   .reset_dmiss_bf(cmu_rst_dupmiss[5]),
   .ftp_room_is_less_t_3(ftp_thr5_room_is_less_t_3),
   .itb_miss_c(agc_thr5_itb_miss_c),
   .tlu_flush_thrx_ifu(tlu_flush_ifu[5]),
   .cmu_any_data_ready(cmu_any_data_ready),
   .agc_lsu_no_ic_miss(agc_thr5_lsu_no_ic_miss),
   .next_thrx_is_ready(tsm_thr5_ready_hp_bf_in),
   .tsm_fill_rdy0(tsm_thr5_fill_rdy0),
   .tsm_no_new_miss(tsm_thr5_no_new_miss),
   .tsm_thrx_ifu_quiesce(ftu_ifu_quiesce[5]),
   .tsm_ignore_by_pass(tsm_thr5_ignore_by_pass),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asi_rd_request(asi_rd_request),
  .asi_wr_request(asi_wr_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .itc_demap_next(itc_demap_next) 
);

ifu_ftu_tsm_ctl tsm6 (
   .scan_in(tsm6_scanin),
   .scan_out(tsm6_scanout),
   .l1clk(l1clk),
   .agc_redirect_bf(ftu_thr6_redirect_bf),
   .agc_tlu_redirect_bf(agc_thr6_tlu_redirect_bf),
   .thrx_go_to_sf_wait(ftp_thr6_go_to_sf_wait),
   .inv_req_c(ftu_thr6_inv_req_c),
   .err_detect_c(agc_thr6_err_detect_c),
   .cmu_inv_req_ack(cmu_inval_ack[6]),
   .thrx_is_null(cmu_null_st[6]),
   .thrx_is_dupmiss(cmu_dupmiss_st[6]),
   .ftu_agc_cmiss_c(agc_thr6_cmiss_stm_c),
   .data_ready(cmu_thr6_data_ready),
   .ftp_reset_fill_wait(ftp_reset_fill_wait),
   .reset_dmiss_bf(cmu_rst_dupmiss[6]),
   .ftp_room_is_less_t_3(ftp_thr6_room_is_less_t_3),
   .itb_miss_c(agc_thr6_itb_miss_c),
   .tlu_flush_thrx_ifu(tlu_flush_ifu[6]),
   .cmu_any_data_ready(cmu_any_data_ready),
   .agc_lsu_no_ic_miss(agc_thr6_lsu_no_ic_miss),
   .next_thrx_is_ready(tsm_thr6_ready_hp_bf_in),
   .tsm_fill_rdy0(tsm_thr6_fill_rdy0),
   .tsm_no_new_miss(tsm_thr6_no_new_miss),
   .tsm_thrx_ifu_quiesce(ftu_ifu_quiesce[6]),
   .tsm_ignore_by_pass(tsm_thr6_ignore_by_pass),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asi_rd_request(asi_rd_request),
  .asi_wr_request(asi_wr_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .itc_demap_next(itc_demap_next) 
);


ifu_ftu_tsm_ctl tsm7 (
   .scan_in(tsm7_scanin),
   .scan_out(tsm7_scanout),
   .l1clk(l1clk),
   .agc_redirect_bf(ftu_thr7_redirect_bf),
   .agc_tlu_redirect_bf(agc_thr7_tlu_redirect_bf),
   .thrx_go_to_sf_wait(ftp_thr7_go_to_sf_wait),
   .inv_req_c(ftu_thr7_inv_req_c),
   .err_detect_c(agc_thr7_err_detect_c),
   .cmu_inv_req_ack(cmu_inval_ack[7]),
   .thrx_is_null(cmu_null_st[7]),
   .thrx_is_dupmiss(cmu_dupmiss_st[7]),
   .ftu_agc_cmiss_c(agc_thr7_cmiss_stm_c),
   .data_ready(cmu_thr7_data_ready),
   .ftp_reset_fill_wait(ftp_reset_fill_wait),
   .reset_dmiss_bf(cmu_rst_dupmiss[7]),
   .ftp_room_is_less_t_3(ftp_thr7_room_is_less_t_3),
   .itb_miss_c(agc_thr7_itb_miss_c),
   .tlu_flush_thrx_ifu(tlu_flush_ifu[7]),
   .cmu_any_data_ready(cmu_any_data_ready),
   .agc_lsu_no_ic_miss(agc_thr7_lsu_no_ic_miss),
   .next_thrx_is_ready(tsm_thr7_ready_hp_bf_in),
   .tsm_fill_rdy0(tsm_thr7_fill_rdy0),
   .tsm_no_new_miss(tsm_thr7_no_new_miss),
   .tsm_thrx_ifu_quiesce(ftu_ifu_quiesce[7]),
   .tsm_ignore_by_pass(tsm_thr7_ignore_by_pass),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asi_rd_request(asi_rd_request),
  .asi_wr_request(asi_wr_request),
  .ftp_asi_rd_done(ftp_asi_rd_done),
  .ftp_asi_wr_done(ftp_asi_wr_done),
  .itc_demap_next(itc_demap_next) 
);


supply0 vss;
supply1 vdd;
// fixscan start:
assign tsm0_scanin               = scan_in                  ;
assign tsm1_scanin               = tsm0_scanout             ;
assign tsm2_scanin               = tsm1_scanout             ;
assign tsm3_scanin               = tsm2_scanout             ;
assign tsm4_scanin               = tsm3_scanout             ;
assign tsm5_scanin               = tsm4_scanout             ;
assign tsm6_scanin               = tsm5_scanout             ;
assign tsm7_scanin               = tsm6_scanout             ;
assign scan_out                  = tsm7_scanout             ;
// fixscan end:
assign se = tcu_scan_en ;
endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_tfc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_tfc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_tfc_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ftu_tfc_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ftu_tsm_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ftu_tsm_ctl (
  l1clk, 
  scan_in, 
  spc_aclk, 
  spc_bclk, 
  asi_rd_request, 
  asi_wr_request, 
  thrx_is_null, 
  thrx_is_dupmiss, 
  ftp_asi_rd_done, 
  ftp_asi_wr_done, 
  agc_redirect_bf, 
  agc_lsu_no_ic_miss, 
  agc_tlu_redirect_bf, 
  inv_req_c, 
  err_detect_c, 
  cmu_inv_req_ack, 
  ftu_agc_cmiss_c, 
  data_ready, 
  cmu_any_data_ready, 
  itb_miss_c, 
  ftp_room_is_less_t_3, 
  tlu_flush_thrx_ifu, 
  thrx_go_to_sf_wait, 
  itc_demap_next, 
  reset_dmiss_bf, 
  ftp_reset_fill_wait, 
  tsm_fill_rdy0, 
  next_thrx_is_ready, 
  tsm_no_new_miss, 
  tsm_ignore_by_pass, 
  tsm_thrx_ifu_quiesce, 
  scan_out) ;
wire siclk;
wire soclk;
wire next_reset_wait;
wire reset_wait_state;
wire next_reset_wait_;
wire reset_wait_reg_scanin;
wire reset_wait_reg_scanout;
wire reset_wait_state_;
wire go_to_rmiss_null;
wire rmiss_wait_state;
wire dmiss_wait_state;
wire no_new_miss_state;
wire can_miss_wait_state;
wire reset_dmiss_f;
wire inv_req_ack_ff;
wire rmiss_null_state;
wire tsm_ifill_done_bf;
wire leave_rmiss_null;
wire next_rmill_null_;
wire rmiss_null_reg_l_scanin;
wire rmiss_null_reg_l_scanout;
wire rmiss_null_state_;
wire go_to_rmiss_wait;
wire leave_rmiss_wait;
wire next_rmiss_wait;
wire rmiss_wait_reg_scanin;
wire rmiss_wait_reg_scanout;
wire go_to_no_new_miss;
wire leave_no_new_miss;
wire next_no_new_miss;
wire no_new_miss_reg_scanin;
wire no_new_miss_reg_scanout;
wire tsm_lsu_no_ic_miss_state;
wire go_to_lsu_ic_miss;
wire lsu_no_ic_miss_reg_scanin;
wire lsu_no_ic_miss_reg_scanout;
wire go_to_lsu_wait;
wire tsm_lsu_wait_state;
wire leave_lsu_wait;
wire next_lsu_wait;
wire lsu_stops_fetch_reg_scanin;
wire lsu_stops_fetch_reg_scanout;
wire go_to_inv_wait;
wire tsm_inv_wait_state;
wire leave_inv_wait;
wire next_inv_wait;
wire inv_stops_fetch_reg_scanin;
wire inv_stops_fetch_reg_scanout;
wire go_to_can_miss_refill;
wire can_miss_refill_state;
wire leave_can_miss_refill;
wire next_can_miss_refill;
wire can_miss_refill_reg_scanin;
wire can_miss_refill_reg_scanout;
wire go_to_can_miss_wait;
wire leave_can_miss_wait;
wire next_can_miss_wait;
wire can_miss_wait_reg_scanin;
wire can_miss_wait_reg_scanout;
wire go_to_fill_rdy0;
wire leave_fill_rdy0;
wire fill_rdy0_state;
wire next_fill_rdy0;
wire fill_rdy0_reg_scanin;
wire fill_rdy0_reg_scanout;
wire go_to_asi_rd_wait;
wire tsm_asi_rd_wait_state;
wire leave_asi_rd_wait;
wire next_asi_rd_wait;
wire asi_rd_stops_fetch_reg_scanin;
wire asi_rd_stops_fetch_reg_scanout;
wire go_to_asi_wr_wait;
wire tsm_asi_wr_wait_state;
wire leave_asi_wr_wait;
wire next_asi_wr_wait;
wire asi_wr_stops_fetch_reg_scanin;
wire asi_wr_stops_fetch_reg_scanout;
wire go_to_dmiss_wait;
wire leave_dmiss_wait;
wire next_dmiss_wait;
wire dmiss_wait_reg_scanin;
wire dmiss_wait_reg_scanout;
wire reset_dmiss_reg_scanin;
wire reset_dmiss_reg_scanout;
wire go_to_fill_wait;
wire fill_wait_state;
wire leave_fill_wait;
wire next_fill_wait;
wire fill_wait_reg_scanin;
wire fill_wait_reg_scanout;
wire go_to_itlb_miss_wait;
wire itlb_miss_wait_state;
wire leave_itlb_miss_wait;
wire next_itlb_miss_wait;
wire itlb_miss_wait_reg_scanin;
wire itlb_miss_wait_reg_scanout;
wire go_to_err_wait;
wire err_wait_state;
wire leave_err_wait;
wire next_err_wait;
wire err_wait_reg_scanin;
wire err_wait_reg_scanout;
wire go_to_no_room_wait;
wire no_room_wait_state;
wire leave_no_room_wait;
wire next_no_room_wait;
wire no_room_wait_reg_scanin;
wire no_room_wait_reg_scanout;
wire go_to_itlb_demap;
wire leave_itlb_demap;
wire itlb_demap_state;
wire next_itlb_demap;
wire itlb_demap_reg_scanin;
wire itlb_demap_reg_scanout;
wire go_to_itlb_write;
wire leave_itlb_write;
wire itlb_write_state;
wire next_itlb_write;
wire itlb_write_reg_scanin;
wire itlb_write_reg_scanout;
wire flush_ifu_reg_scanin;
wire flush_ifu_reg_scanout;
wire tlu_flush_thrx_ifu_d;
wire go_to_tlu_redr;
wire tsm_tlu_redr_wait_state;
wire leave_tlu_redr;
wire next_tlu_redr_wait;
wire tlu_red_reg_scanin;
wire tlu_red_reg_scanout;
wire next_sf_wait;
wire sf_wait_state;
wire tlu_sf_reg_scanin;
wire tlu_sf_reg_scanout;
wire next_ignore_by_pass;
wire ignore_by_pass_reg_scanin;
wire ignore_by_pass_reg_scanout;
wire next_ifu_quiesce;
wire no_icmiss_pending_reg_scanin;
wire no_icmiss_pending_reg_scanout;
wire ifill_done_reg_scanin;
wire ifill_done_reg_scanout;
wire spares_scanin;
wire spares_scanout;
 

input  l1clk;
input  scan_in;
input  spc_aclk;
input  spc_bclk;

input  asi_rd_request;
input  asi_wr_request;
input  thrx_is_null;
input  thrx_is_dupmiss;
input  ftp_asi_rd_done;
input  ftp_asi_wr_done;
input  agc_redirect_bf;
input  agc_lsu_no_ic_miss;
input  agc_tlu_redirect_bf;
input  inv_req_c;
input  err_detect_c;
input  cmu_inv_req_ack;
input  ftu_agc_cmiss_c;
input  data_ready;
input  cmu_any_data_ready;
input  itb_miss_c;
input  ftp_room_is_less_t_3;
input  tlu_flush_thrx_ifu ;
input  thrx_go_to_sf_wait ;
input  itc_demap_next;
input  reset_dmiss_bf;
input  ftp_reset_fill_wait;
// output tsm_ready_hp_bf;
output tsm_fill_rdy0; 
output next_thrx_is_ready ;
// output tsm_fill_rdy1; 
output tsm_no_new_miss;
output tsm_ignore_by_pass;
output tsm_thrx_ifu_quiesce;
output scan_out;

// scan renames
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan
    
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////


////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// First state machine controls the thread if it      //
// initiated  the cache miss.                         //
////////////////////////////////////////////////////////
// First wait state is to wait the initial trap       //
// redirection from the trap unit.                    //
////////////////////////////////////////////////////////
assign next_reset_wait  = reset_wait_state & ~agc_redirect_bf ;
assign next_reset_wait_ = ~next_reset_wait ; 
ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 reset_wait_reg  (
 .scan_in(reset_wait_reg_scanin),
 .scan_out(reset_wait_reg_scanout),
 .l1clk( l1clk                                                             ),
 .din  (next_reset_wait_),
 .dout (reset_wait_state_),
  .siclk(siclk),
  .soclk(soclk));

assign reset_wait_state = ~reset_wait_state_ ;
////////////////////////////////////////////////////////
// Real_Miss_Null state                               // 
// Note: Null state comes up as ONE after reset       //
// There is a case that we get reset_dmiss_bf the     //
// cycle that we trying to go dmiss_state.In that case//
// we should come to NULL state.                      //    
////////////////////////////////////////////////////////
assign go_to_rmiss_null =  ( rmiss_wait_state    & thrx_is_null   ) | 
                           // ( rmiss_wait_state    & agc_tg_or_v_err_p) |
                           ( dmiss_wait_state    & (thrx_is_null | agc_redirect_bf)) | 
                           ( thrx_is_dupmiss     & agc_redirect_bf) |
                           ( no_new_miss_state   & thrx_is_null)    | 
                           ( can_miss_wait_state & thrx_is_null)    |
                             reset_dmiss_f                         |
                             inv_req_ack_ff                         |
                             rmiss_null_state                       |                             
                             tsm_ifill_done_bf ;
assign leave_rmiss_null =  ((ftu_agc_cmiss_c | inv_req_c) & ~tsm_ifill_done_bf & ~tsm_no_new_miss) ;
assign next_rmill_null_ = ~(go_to_rmiss_null & ~leave_rmiss_null) ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 rmiss_null_reg_l  (
 .scan_in(rmiss_null_reg_l_scanin),
 .scan_out(rmiss_null_reg_l_scanout),
 .l1clk( l1clk ),
 .din  (next_rmill_null_),
 .dout (rmiss_null_state_),
  .siclk(siclk),
  .soclk(soclk));

assign rmiss_null_state = ~rmiss_null_state_ ;
////////////////////////////////////////////////////////
// Real_Miss_Wait state: rmiss_wait_state             //
////////////////////////////////////////////////////////
assign go_to_rmiss_wait = (ftu_agc_cmiss_c & rmiss_null_state & ~tsm_no_new_miss) | 
                           rmiss_wait_state;
// assign leave_rmiss_wait = (agc_redirect_bf | data_ready | (rmiss_wait_state & thrx_is_null) | thrx_is_dupmiss | agc_tg_or_v_err_p );
assign leave_rmiss_wait = (agc_redirect_bf | data_ready | (rmiss_wait_state & thrx_is_null) | thrx_is_dupmiss ) ; // | agc_tg_or_v_err_p );
assign next_rmiss_wait  =  go_to_rmiss_wait & ~leave_rmiss_wait ; 

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 rmiss_wait_reg  (
 .scan_in(rmiss_wait_reg_scanin),
 .scan_out(rmiss_wait_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_rmiss_wait),
 .dout (rmiss_wait_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
// No_New_Miss state: no_new_miss_state               //
// NOTE: we do not want to leave no_new_miss_state    //
// even when we go to can_miss_wait_state because it  //
// possible to get flush before the data comes for    //
// the original miss. In that case we simply reset    //
// can_miss_wait_state and we are ready to fetch again//
////////////////////////////////////////////////////////
assign go_to_no_new_miss = (rmiss_wait_state & agc_redirect_bf & ~thrx_is_null & ~thrx_is_dupmiss) | 
                            no_new_miss_state;
assign leave_no_new_miss =  tsm_ifill_done_bf | thrx_is_null  ; 
assign next_no_new_miss  = go_to_no_new_miss & ~leave_no_new_miss ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 no_new_miss_reg  (
 .scan_in(no_new_miss_reg_scanin),
 .scan_out(no_new_miss_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_no_new_miss),
 .dout (no_new_miss_state),
  .siclk(siclk),
  .soclk(soclk));

assign tsm_no_new_miss = no_new_miss_state |  tsm_lsu_no_ic_miss_state ;


//////////////////////////////////////////////////////////
// LSU no new_miss state. LSU needs to delay new misses //
//////////////////////////////////////////////////////////
assign go_to_lsu_ic_miss = agc_lsu_no_ic_miss ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 lsu_no_ic_miss_reg  (
 .scan_in(lsu_no_ic_miss_reg_scanin),
 .scan_out(lsu_no_ic_miss_reg_scanout),
 .l1clk( l1clk ),
 .din  (go_to_lsu_ic_miss),
 .dout (tsm_lsu_no_ic_miss_state),
  .siclk(siclk),
  .soclk(soclk));


/////////////////////////////////////////////////////////
// Stop fetch if lsu can not handle new miss and we    //
// detect new miss.                                    //
/////////////////////////////////////////////////////////
assign go_to_lsu_wait = (tsm_lsu_no_ic_miss_state & ftu_agc_cmiss_c) | 
                         tsm_lsu_wait_state ;
assign leave_lsu_wait = ~agc_lsu_no_ic_miss ; // | agc_tg_or_v_err_p;
assign next_lsu_wait  = go_to_lsu_wait & ~leave_lsu_wait ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_2 lsu_stops_fetch_reg  (
 .scan_in(lsu_stops_fetch_reg_scanin),
 .scan_out(lsu_stops_fetch_reg_scanout),
 .l1clk( l1clk ),
 .din  ({next_lsu_wait, cmu_inv_req_ack}),
 .dout ({tsm_lsu_wait_state,inv_req_ack_ff}),
  .siclk(siclk),
  .soclk(soclk));

/////////////////////////////////////////////////////////
// Stop fetch if parity eeror is dtetcted and INV is   // 
// requested from L2. Wait for inv ack.                //
/////////////////////////////////////////////////////////
assign go_to_inv_wait = (inv_req_c & rmiss_null_state & ~tsm_no_new_miss) | 
                         tsm_inv_wait_state ;
assign leave_inv_wait = inv_req_ack_ff  ;
assign next_inv_wait  = go_to_inv_wait & ~leave_inv_wait ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 inv_stops_fetch_reg  (
 .scan_in(inv_stops_fetch_reg_scanin),
 .scan_out(inv_stops_fetch_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_inv_wait),
 .dout (tsm_inv_wait_state),
  .siclk(siclk),
  .soclk(soclk));

//  Canceled_Miss_refill: can_miss_refill_state       //
////////////////////////////////////////////////////////
assign go_to_can_miss_refill = (no_new_miss_state & ftu_agc_cmiss_c & ~thrx_is_null) |
                              can_miss_refill_state ; 
assign leave_can_miss_refill = tsm_ifill_done_bf  | thrx_is_null ; // | agc_tg_or_v_err_p;
assign next_can_miss_refill  = go_to_can_miss_refill & ~leave_can_miss_refill ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 can_miss_refill_reg  (
 .scan_in(can_miss_refill_reg_scanin),
 .scan_out(can_miss_refill_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_can_miss_refill),
 .dout (can_miss_refill_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
//  Canceled_Miss_Wait: can_miss_wait_state           //
////////////////////////////////////////////////////////
assign go_to_can_miss_wait = (no_new_miss_state & ftu_agc_cmiss_c & ~thrx_is_null) |
                              can_miss_wait_state ; 
assign leave_can_miss_wait = tsm_ifill_done_bf | agc_redirect_bf  | thrx_is_null ; // | agc_tg_or_v_err_p;
assign next_can_miss_wait  = go_to_can_miss_wait & ~leave_can_miss_wait ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 can_miss_wait_reg  (
 .scan_in(can_miss_wait_reg_scanin),
 .scan_out(can_miss_wait_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_can_miss_wait),
 .dout (can_miss_wait_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
// Fill_rdy0 state :                                  //
////////////////////////////////////////////////////////
assign go_to_fill_rdy0 = (data_ready & (rmiss_wait_state |
                          no_new_miss_state  | can_miss_refill_state));
assign leave_fill_rdy0 = fill_rdy0_state ; 
assign next_fill_rdy0  = go_to_fill_rdy0 & ~leave_fill_rdy0 ;
 
ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 fill_rdy0_reg  (
 .scan_in(fill_rdy0_reg_scanin),
 .scan_out(fill_rdy0_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_fill_rdy0),
 .dout (fill_rdy0_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
// Fill_rdy1 state :                                  //
////////////////////////////////////////////////////////
// assign go_to_fill_rdy1 = fill_rdy0_state ;
// assign leave_fill_rdy1 = fill_rdy1_state ; 
// assign next_fill_rdy1  = go_to_fill_rdy1 & ~leave_fill_rdy1 ;
 
// msff_ctl_macro fill_rdy1_reg (width=1) (
//  .scan_in(fill_rdy1_reg_scanin),
//  .scan_out(fill_rdy1_reg_scanout),
//  .l1clk( l1clk ),
//  .din  (next_fill_rdy1),
//  .dout (fill_rdy1_state));

/////////////////////////////////////////////////////////
// asi read wait                                       //
//  when asi_request comes stop all threads to gain    //
//  access to the arrays. The only thing that may delay//
//  the access is writes to the Icache caused by fill  // 
/////////////////////////////////////////////////////////
assign go_to_asi_rd_wait = (asi_rd_request ) | 
                         tsm_asi_rd_wait_state ;
assign leave_asi_rd_wait = ftp_asi_rd_done  ; 
assign next_asi_rd_wait  = go_to_asi_rd_wait & ~leave_asi_rd_wait ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 asi_rd_stops_fetch_reg  (
 .scan_in(asi_rd_stops_fetch_reg_scanin),
 .scan_out(asi_rd_stops_fetch_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_asi_rd_wait),
 .dout (tsm_asi_rd_wait_state),
  .siclk(siclk),
  .soclk(soclk));

/////////////////////////////////////////////////////////
// asi write wait                                      //
//  when asi_request comes stop all threads to gain    //
//  access to the arrays. The only thing that may delay//
//  the access is writes to the Icache caused by fill  // 
/////////////////////////////////////////////////////////
assign go_to_asi_wr_wait = (asi_wr_request ) | 
                         tsm_asi_wr_wait_state ;
assign leave_asi_wr_wait = ftp_asi_wr_done  ; 
assign next_asi_wr_wait  = go_to_asi_wr_wait & ~leave_asi_wr_wait ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 asi_wr_stops_fetch_reg  (
 .scan_in(asi_wr_stops_fetch_reg_scanin),
 .scan_out(asi_wr_stops_fetch_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_asi_wr_wait),
 .dout (tsm_asi_wr_wait_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// second state machine is activated if the thread is // 
// waiting on a duplicate miss.                       // 
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Duplicate_Miss_Wait state: dmiss_wait_state        //
////////////////////////////////////////////////////////
assign go_to_dmiss_wait = (rmiss_wait_state & thrx_is_dupmiss ) | 
                           dmiss_wait_state;
assign leave_dmiss_wait = (agc_redirect_bf | reset_dmiss_f | thrx_is_null); 
assign next_dmiss_wait  =  go_to_dmiss_wait & ~leave_dmiss_wait ; 

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 dmiss_wait_reg  (
 .scan_in(dmiss_wait_reg_scanin),
 .scan_out(dmiss_wait_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_dmiss_wait),
 .dout (dmiss_wait_state),
  .siclk(siclk),
  .soclk(soclk));

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 reset_dmiss_reg  (
 .scan_in(reset_dmiss_reg_scanin),
 .scan_out(reset_dmiss_reg_scanout),
 .l1clk( l1clk ),
 .din  (reset_dmiss_bf),
 .dout (reset_dmiss_f),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Third state machine is activated if the thread is  // 
// waiting on a cache line being filled by an other   //
// thread.                                            // 
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Fill_Wait state: fill_wait_state                   //
////////////////////////////////////////////////////////
assign go_to_fill_wait =  cmu_any_data_ready | fill_wait_state;
assign leave_fill_wait =  ftp_reset_fill_wait & ~cmu_any_data_ready; 
assign next_fill_wait  =  go_to_fill_wait & ~leave_fill_wait ; 

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 fill_wait_reg  (
 .scan_in(fill_wait_reg_scanin),
 .scan_out(fill_wait_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_fill_wait),
 .dout (fill_wait_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Fourth state machine is activated if the thread is // 
// waiting on a ITLB miss.                            // 
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Fill_Wait state: itlb_miss_wait_state              //
////////////////////////////////////////////////////////
assign go_to_itlb_miss_wait =  itb_miss_c | itlb_miss_wait_state;
assign leave_itlb_miss_wait =  agc_redirect_bf ; 
assign next_itlb_miss_wait  =  go_to_itlb_miss_wait & ~leave_itlb_miss_wait ; 

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 itlb_miss_wait_reg  (
 .scan_in(itlb_miss_wait_reg_scanin),
 .scan_out(itlb_miss_wait_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_itlb_miss_wait),
 .dout (itlb_miss_wait_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// err_wait state: err_wait_state                     //
////////////////////////////////////////////////////////
assign go_to_err_wait       =  err_detect_c | err_wait_state;
assign leave_err_wait       =  agc_redirect_bf ; 
assign next_err_wait        =  go_to_err_wait & ~leave_err_wait ; 

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 err_wait_reg  (
 .scan_in(err_wait_reg_scanin),
 .scan_out(err_wait_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_err_wait),
 .dout (err_wait_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Fifth  state machine is activated if the thread    // 
// does not have room for 3 more instructions.        // 
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Fill_Wait state: no_room_wait_state                //
////////////////////////////////////////////////////////
assign go_to_no_room_wait =   ftp_room_is_less_t_3 | no_room_wait_state;
assign leave_no_room_wait =  ~ftp_room_is_less_t_3 ; 
assign next_no_room_wait  =  go_to_no_room_wait & ~leave_no_room_wait ; 

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 no_room_wait_reg  (
 .scan_in(no_room_wait_reg_scanin),
 .scan_out(no_room_wait_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_no_room_wait),
 .dout (no_room_wait_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// sixth  state machine is activated whenever a ITLB  //
// write is requested by TLU.                         //  
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// Itlb_Demap state: itlb_demap_state                 //
////////////////////////////////////////////////////////
assign go_to_itlb_demap =   itc_demap_next ;
assign leave_itlb_demap =   itlb_demap_state ; 
assign next_itlb_demap  =  go_to_itlb_demap & ~leave_itlb_demap ; 

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 itlb_demap_reg  (
 .scan_in(itlb_demap_reg_scanin),
 .scan_out(itlb_demap_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_itlb_demap),
 .dout (itlb_demap_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
// Itlb_write state: itlb_write_state                 //
////////////////////////////////////////////////////////
assign go_to_itlb_write =   itlb_demap_state ;
assign leave_itlb_write =   itlb_write_state ; 
assign next_itlb_write  =  go_to_itlb_write & ~leave_itlb_write ; 

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 itlb_write_reg  (
 .scan_in(itlb_write_reg_scanin),
 .scan_out(itlb_write_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_itlb_write),
 .dout (itlb_write_state),
  .siclk(siclk),
  .soclk(soclk));

// assign itlb_miss_write_done = itlb_write_state ;
//////////////////////////////////////////////////////////
// TLU flush causes the thread to wait until TLU redirection
/////////////////////////////////////////////////////////
ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 flush_ifu_reg  (
 .scan_in(flush_ifu_reg_scanin),
 .scan_out(flush_ifu_reg_scanout),
 .l1clk( l1clk ),
 .din  (tlu_flush_thrx_ifu),
 .dout (tlu_flush_thrx_ifu_d),
  .siclk(siclk),
  .soclk(soclk));

assign go_to_tlu_redr = tlu_flush_thrx_ifu_d | tsm_tlu_redr_wait_state  ; 
assign leave_tlu_redr = agc_tlu_redirect_bf   ; 
assign next_tlu_redr_wait  = go_to_tlu_redr & ~leave_tlu_redr ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 tlu_red_reg  (
 .scan_in(tlu_red_reg_scanin),
 .scan_out(tlu_red_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_tlu_redr_wait),
 .dout (tsm_tlu_redr_wait_state),
  .siclk(siclk),
  .soclk(soclk));

assign next_sf_wait = (thrx_go_to_sf_wait | sf_wait_state) & ~agc_tlu_redirect_bf & ~ftu_agc_cmiss_c ;
ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 tlu_sf_reg  (
 .scan_in(tlu_sf_reg_scanin),
 .scan_out(tlu_sf_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_sf_wait),
 .dout (sf_wait_state),
  .siclk(siclk),
  .soclk(soclk));

////////////////////////////////////////////////////////
// Now generate  a cumulative Ready for this thread   //
////////////////////////////////////////////////////////
assign next_thrx_is_ready = ( ~next_rmiss_wait & ~next_can_miss_wait & ~next_itlb_write & ~next_itlb_miss_wait & ~next_err_wait & 
                              ~next_dmiss_wait & ~next_fill_wait & ~next_reset_wait & ~next_itlb_demap & ~next_lsu_wait & ~next_sf_wait &
                              ~next_inv_wait   & ~next_asi_rd_wait  & ~next_asi_wr_wait & ~next_itlb_demap & ~next_tlu_redr_wait) ;
                               // | next_fill_rdy0   | next_fill_rdy1 ; 

// msff_ctl_macro thrx_is_ready_reg (width=1) (
//  .scan_in(thrx_is_ready_reg_scanin),
//  .scan_out(thrx_is_ready_reg_scanout),
//  .l1clk( l1clk ),
//  .din  (next_thrx_is_ready),
//  .dout (thrx_is_ready));


 // assign next_ignore_by_pass = (~next_dmiss_wait & ~next_rmiss_wait) | next_can_miss_refill | next_no_new_miss ;
 assign next_ignore_by_pass = (~next_dmiss_wait & ~rmiss_wait_state) | can_miss_refill_state | next_no_new_miss ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 ignore_by_pass_reg  (
 .scan_in(ignore_by_pass_reg_scanin),
 .scan_out(ignore_by_pass_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_ignore_by_pass),
 .dout (tsm_ignore_by_pass),
  .siclk(siclk),
  .soclk(soclk));
      
 
// assign tsm_ready_hp_bf = thrx_is_ready ; // &  ftp_buffer_is_empty;

assign next_ifu_quiesce = (~rmiss_wait_state & ~dmiss_wait_state & 
                                    ~can_miss_wait_state & ~no_new_miss_state) & (tsm_tlu_redr_wait_state |
                                     (next_sf_wait & sf_wait_state)) ;

ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 no_icmiss_pending_reg  (
 .scan_in(no_icmiss_pending_reg_scanin),
 .scan_out(no_icmiss_pending_reg_scanout),
 .l1clk( l1clk ),
 .din  (next_ifu_quiesce),
 .dout (tsm_thrx_ifu_quiesce),
  .siclk(siclk),
  .soclk(soclk));
      
/////////////////////////////////////////////////////////////////////////////////
// assign tsm_ifill_done_bf = leave_fill_rdy0 ; 
// Delay fill done for one cycle so that any fetches still in progress which
// match the current fill will have a chance to be flagged as duplicate in
// the CMU. Otherwise we have to compare the current fetch in C (about to 
// miss) to what is being written and if they match kill the miss.
/////////////////////////////////////////////////////////////////////////////////
ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 ifill_done_reg  (
 .scan_in(ifill_done_reg_scanin),
 .scan_out(ifill_done_reg_scanout),
 .l1clk( l1clk ),
 .din  (leave_fill_rdy0),
 .dout (tsm_ifill_done_bf),
  .siclk(siclk),
  .soclk(soclk));

assign tsm_fill_rdy0 = fill_rdy0_state ;

///////////////////////////////////////////////////////////////////////
// Spare circuits                                                    //
///////////////////////////////////////////////////////////////////////
ifu_ftu_tsm_ctl_spare_ctl_macro__num_1 spares  (
        .scan_in(spares_scanin),
        .scan_out(spares_scanout),
        .l1clk  (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// assign tsm_fill_rdy1 = fill_rdy1_state ; 
supply0 vss;
supply1 vdd;
// fixscan start:
assign reset_wait_reg_scanin     = scan_in                  ;
assign rmiss_null_reg_l_scanin   = reset_wait_reg_scanout   ;
assign rmiss_wait_reg_scanin     = rmiss_null_reg_l_scanout ;
assign no_new_miss_reg_scanin    = rmiss_wait_reg_scanout   ;
assign lsu_no_ic_miss_reg_scanin = no_new_miss_reg_scanout  ;
assign lsu_stops_fetch_reg_scanin = lsu_no_ic_miss_reg_scanout;
assign inv_stops_fetch_reg_scanin = lsu_stops_fetch_reg_scanout;
assign can_miss_refill_reg_scanin = inv_stops_fetch_reg_scanout;
assign can_miss_wait_reg_scanin  = can_miss_refill_reg_scanout;
assign fill_rdy0_reg_scanin      = can_miss_wait_reg_scanout;
assign asi_rd_stops_fetch_reg_scanin = fill_rdy0_reg_scanout    ;
assign asi_wr_stops_fetch_reg_scanin = asi_rd_stops_fetch_reg_scanout;
assign dmiss_wait_reg_scanin     = asi_wr_stops_fetch_reg_scanout;
assign reset_dmiss_reg_scanin    = dmiss_wait_reg_scanout   ;
assign fill_wait_reg_scanin      = reset_dmiss_reg_scanout  ;
assign itlb_miss_wait_reg_scanin = fill_wait_reg_scanout    ;
assign err_wait_reg_scanin       = itlb_miss_wait_reg_scanout;
assign no_room_wait_reg_scanin   = err_wait_reg_scanout     ;
assign itlb_demap_reg_scanin     = no_room_wait_reg_scanout ;
assign itlb_write_reg_scanin     = itlb_demap_reg_scanout   ;
assign flush_ifu_reg_scanin      = itlb_write_reg_scanout   ;
assign tlu_red_reg_scanin        = flush_ifu_reg_scanout    ;
assign tlu_sf_reg_scanin         = tlu_red_reg_scanout      ;
assign ignore_by_pass_reg_scanin = tlu_sf_reg_scanout       ;
assign no_icmiss_pending_reg_scanin = ignore_by_pass_reg_scanout;
assign ifill_done_reg_scanin     = no_icmiss_pending_reg_scanout;
assign spares_scanin             = ifill_done_reg_scanout   ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_tsm_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ftu_tsm_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ftu_tsm_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ibu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ibu (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  pku_flush_buffer0, 
  pku_flush_upper_buffer, 
  ftu_fetch_thr_c, 
  pku_pick_p, 
  ftu_exception_valid_c, 
  ftu_instr_sf_valid_c, 
  ftu_ibu_redirect_bf, 
  ftu_ic_no_err_c, 
  ftu_bus_0_is_first, 
  ftu_bus_1_is_first, 
  ftu_bus_2_is_first, 
  ftu_bus_3_is_first, 
  ftu_instr_valid_c, 
  ftu_instr_0_c_rep0, 
  ftu_instr_0_c_rep1, 
  ftu_instr_0_c_rep2, 
  ftu_instr_0_c_rep3, 
  ftu_instr_1_c_rep0, 
  ftu_instr_1_c_rep1, 
  ftu_instr_1_c_rep2, 
  ftu_instr_1_c_rep3, 
  ftu_instr_2_c_rep0, 
  ftu_instr_2_c_rep1, 
  ftu_instr_2_c_rep2, 
  ftu_instr_2_c_rep3, 
  ftu_instr_3_c_rep0, 
  ftu_instr_3_c_rep1, 
  ftu_instr_3_c_rep2, 
  ftu_instr_3_c_rep3, 
  ftu_instr_0_exceptions_c_rep0, 
  ftu_instr_0_exceptions_c_rep1, 
  ftu_instr_0_exceptions_c_rep2, 
  ftu_instr_0_exceptions_c_rep3, 
  ftu_instr_1_exceptions_c_rep0, 
  ftu_instr_1_exceptions_c_rep1, 
  ftu_instr_1_exceptions_c_rep2, 
  ftu_instr_1_exceptions_c_rep3, 
  ftu_instr_2_exceptions_c_rep0, 
  ftu_instr_2_exceptions_c_rep1, 
  ftu_instr_2_exceptions_c_rep2, 
  ftu_instr_2_exceptions_c_rep3, 
  ftu_instr_3_exceptions_c_rep0, 
  ftu_instr_3_exceptions_c_rep1, 
  ftu_instr_3_exceptions_c_rep2, 
  ftu_instr_3_exceptions_c_rep3, 
  lsu_ifu_ibu_pmen, 
  ftu_buffer_wr_en_f, 
  l15_ifu_valid, 
  ifu_buf0_valid_p, 
  ifu_upper_buffer_valid_p, 
  ibu_empty, 
  ibu_room_4ormore, 
  ifu_buf0_inst0, 
  ifu_buf0_inst1, 
  ifu_buf0_inst2, 
  ifu_buf0_inst3, 
  ifu_buf0_inst4, 
  ifu_buf0_inst5, 
  ifu_buf0_inst6, 
  ifu_buf0_inst7, 
  ifu_buf0_excp0, 
  ifu_buf0_excp1, 
  ifu_buf0_excp2, 
  ifu_buf0_excp3, 
  ifu_buf0_excp4, 
  ifu_buf0_excp5, 
  ifu_buf0_excp6, 
  ifu_buf0_excp7, 
  scan_out);
wire ibf0_scanin;
wire ibf0_scanout;
wire [7:0] ibq_buff_clken;
wire [7:0] ibq_ctl_clken;
wire [7:0] ibq_buf0_sel_inst0_pick;
wire [7:0] ibq_buf0_sel_inst1_pick;
wire [7:0] ibq_buf0_sel_inst2_pick;
wire [7:0] ibq_buf0_sel_inst3_pick;
wire [7:0] ibq_buf0_sel_inst0_pick_;
wire [7:0] ibq_buf0_sel_inst1_pick_;
wire [7:0] ibq_buf0_sel_inst2_pick_;
wire [7:0] ibq_buf0_sel_inst3_pick_;
wire [7:0] ibq_buf0_sel_buf1;
wire [7:0] ibq_buf0_sel_buf2;
wire [7:0] ibq_buf0_sel_buf3;
wire [7:0] ibq_buf0_sel_buf4;
wire [7:0] ibq_buf0_sel_buf5;
wire [7:0] ibq_buf0_sel_buf6;
wire [7:0] ibq_buf0_sel_buf7;
wire [7:0] ibq_buf0_sel_hold_pick;
wire [7:0] ibq_buf0_sel_hold_pick_;
wire [7:0] ibq_buf0_sel_buf1to7_pick;
wire [7:0] ibq_buf0_sel_buf1to7_pick_;
wire [7:0] ibq_buf1_sel_inst0;
wire [7:0] ibq_buf1_sel_inst1;
wire [7:0] ibq_buf1_sel_inst2;
wire [7:0] ibq_buf1_sel_inst3;
wire [7:0] ibq_buf1_sel_hold;
wire [7:0] ibq_buf2_sel_inst0;
wire [7:0] ibq_buf2_sel_inst1;
wire [7:0] ibq_buf2_sel_inst2;
wire [7:0] ibq_buf2_sel_inst3;
wire [7:0] ibq_buf2_sel_hold;
wire [7:0] ibq_buf3_sel_inst0;
wire [7:0] ibq_buf3_sel_inst1;
wire [7:0] ibq_buf3_sel_inst2;
wire [7:0] ibq_buf3_sel_inst3;
wire [7:0] ibq_buf3_sel_hold;
wire [7:0] ibq_buf4_sel_inst0;
wire [7:0] ibq_buf4_sel_inst1;
wire [7:0] ibq_buf4_sel_inst2;
wire [7:0] ibq_buf4_sel_inst3;
wire [7:0] ibq_buf4_sel_hold;
wire [7:0] ibq_buf5_sel_inst0;
wire [7:0] ibq_buf5_sel_inst1;
wire [7:0] ibq_buf5_sel_inst2;
wire [7:0] ibq_buf5_sel_inst3;
wire [7:0] ibq_buf5_sel_hold;
wire [7:0] ibq_buf6_sel_inst0;
wire [7:0] ibq_buf6_sel_inst1;
wire [7:0] ibq_buf6_sel_inst2;
wire [7:0] ibq_buf6_sel_inst3;
wire [7:0] ibq_buf6_sel_hold;
wire [7:0] ibq_buf7_sel_inst0;
wire [7:0] ibq_buf7_sel_inst1;
wire [7:0] ibq_buf7_sel_inst2;
wire [7:0] ibq_buf7_sel_inst3;
wire [7:0] ibq_buf7_sel_hold;
wire ibf1_scanin;
wire ibf1_scanout;
wire ibf2_scanin;
wire ibf2_scanout;
wire ibf3_scanin;
wire ibf3_scanout;
wire ibf4_scanin;
wire ibf4_scanout;
wire ibf5_scanin;
wire ibf5_scanout;
wire ibf6_scanin;
wire ibf6_scanout;
wire ibf7_scanin;
wire ibf7_scanout;
wire ibq0_scanin;
wire ibq0_scanout;
wire ibq1_scanin;
wire ibq1_scanout;
wire ibq2_scanin;
wire ibq2_scanout;
wire ibq3_scanin;
wire ibq3_scanout;
wire ibq4_scanin;
wire ibq4_scanout;
wire ibq5_scanin;
wire ibq5_scanout;
wire ibq6_scanin;
wire ibq6_scanout;
wire ibq7_scanin;
wire ibq7_scanout;


   input   l2clk;
   input   scan_in;
   input   tcu_pce_ov;  	  // scan signals
   input   tcu_scan_en;  	  // scan signals
   input   spc_aclk;
   input   spc_bclk;
	   
   input   [7:0] pku_flush_buffer0    ; 	// flush buf0 only
   input   [7:0] pku_flush_upper_buffer   ;	// flush buf1-7 only

   input   [7:0] ftu_fetch_thr_c       ;	// enables fetch
   input   [7:0] pku_pick_p	   ;		// instruction issue/pick indicator
   input         ftu_exception_valid_c ;
   input         ftu_instr_sf_valid_c ;

   input   [7:0] ftu_ibu_redirect_bf;
   input         ftu_ic_no_err_c   ;                // Data being by_passed does not have an error
   input         ftu_bus_0_is_first ;           // bus 0 contains first instr
   input         ftu_bus_1_is_first ;           // bus 1 contains first instr
   input         ftu_bus_2_is_first ;           // bus 2 contains first instr
   input         ftu_bus_3_is_first ;           // bus 3 contains first instr

 
   input   [3:0] ftu_instr_valid_c  ;

   input  [32:0] ftu_instr_0_c_rep0; 		
   input  [32:0] ftu_instr_0_c_rep1; 		
   input  [32:0] ftu_instr_0_c_rep2; 		
   input  [32:0] ftu_instr_0_c_rep3; 		
   input  [32:0] ftu_instr_1_c_rep0; 		
   input  [32:0] ftu_instr_1_c_rep1; 		
   input  [32:0] ftu_instr_1_c_rep2; 		
   input  [32:0] ftu_instr_1_c_rep3; 		
   input  [32:0] ftu_instr_2_c_rep0;
   input  [32:0] ftu_instr_2_c_rep1;
   input  [32:0] ftu_instr_2_c_rep2;
   input  [32:0] ftu_instr_2_c_rep3;
   input  [32:0] ftu_instr_3_c_rep0; 		
   input  [32:0] ftu_instr_3_c_rep1; 		
   input  [32:0] ftu_instr_3_c_rep2; 		
   input  [32:0] ftu_instr_3_c_rep3; 		
   input   [4:0] ftu_instr_0_exceptions_c_rep0;
   input   [4:0] ftu_instr_0_exceptions_c_rep1;
   input   [4:0] ftu_instr_0_exceptions_c_rep2;
   input   [4:0] ftu_instr_0_exceptions_c_rep3;
   input   [4:0] ftu_instr_1_exceptions_c_rep0;	
   input   [4:0] ftu_instr_1_exceptions_c_rep1;	
   input   [4:0] ftu_instr_1_exceptions_c_rep2;	
   input   [4:0] ftu_instr_1_exceptions_c_rep3;	
   input   [4:0] ftu_instr_2_exceptions_c_rep0;	
   input   [4:0] ftu_instr_2_exceptions_c_rep1;	
   input   [4:0] ftu_instr_2_exceptions_c_rep2;	
   input   [4:0] ftu_instr_2_exceptions_c_rep3;	
   input   [4:0] ftu_instr_3_exceptions_c_rep0;
   input   [4:0] ftu_instr_3_exceptions_c_rep1;
   input   [4:0] ftu_instr_3_exceptions_c_rep2;
   input   [4:0] ftu_instr_3_exceptions_c_rep3;

   input         lsu_ifu_ibu_pmen;              // enable power management.
   input   [7:0] ftu_buffer_wr_en_f;            // Buffer clock enables (Normal fetch)
   input         l15_ifu_valid;                 
    

   output  [7:0] ifu_buf0_valid_p  ;		// buf0 valid
   output  [7:0] ifu_upper_buffer_valid_p  ;	// at least one of buf1-7 valid


   output  [7:0] ibu_empty	  ;		// buf0-7 empty
   output  [7:0] ibu_room_4ormore  ;		// at least 4 empty buffers
      
   output [32:0] ifu_buf0_inst0; 
   output [32:0] ifu_buf0_inst1; 
   output [32:0] ifu_buf0_inst2; 
   output [32:0] ifu_buf0_inst3; 
   output [32:0] ifu_buf0_inst4; 
   output [32:0] ifu_buf0_inst5; 
   output [32:0] ifu_buf0_inst6; 
   output [32:0] ifu_buf0_inst7; 

   output  [4:0] ifu_buf0_excp0;
   output  [4:0] ifu_buf0_excp1;
   output  [4:0] ifu_buf0_excp2;
   output  [4:0] ifu_buf0_excp3;
   output  [4:0] ifu_buf0_excp4;
   output  [4:0] ifu_buf0_excp5;
   output  [4:0] ifu_buf0_excp6;
   output  [4:0] ifu_buf0_excp7;

   output  scan_out;
        
ifu_ibu_ibf_dp ibf0 (
   .scan_in(ibf0_scanin),
   .scan_out(ibf0_scanout),
   .l2clk(l2clk),

   .pku_pick_p         (pku_pick_p[0]  ),
   .ibq_buff_clken     (ibq_buff_clken[0] ),
   .ibq_ctl_clken      (ibq_ctl_clken[0] ),

   .ftu_ic_no_err_c (ftu_ic_no_err_c),
   

   .ftu_instr_0_c(ftu_instr_0_c_rep0[32:0]),
   .ftu_instr_1_c(ftu_instr_1_c_rep0[32:0]),
   .ftu_instr_2_c(ftu_instr_2_c_rep0[32:0]),
   .ftu_instr_3_c(ftu_instr_3_c_rep0[32:0]),
   .ftu_instr_0_exceptions_c(ftu_instr_0_exceptions_c_rep0[4:0]),
   .ftu_instr_1_exceptions_c(ftu_instr_1_exceptions_c_rep0[4:0]),
   .ftu_instr_2_exceptions_c(ftu_instr_2_exceptions_c_rep0[4:0]),
   .ftu_instr_3_exceptions_c(ftu_instr_3_exceptions_c_rep0[4:0]),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[0] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[0] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[0] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[0] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[0] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[0] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[0] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[0] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[0]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[0]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[0]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[0]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[0]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[0]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[0]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[0]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[0]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[0]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[0]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[0] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[0] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[0] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[0] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[0]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[0] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[0] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[0] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[0] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[0]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[0] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[0] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[0] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[0] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[0]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[0] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[0] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[0] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[0] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[0]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[0] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[0] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[0] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[0] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[0]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[0] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[0] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[0] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[0] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[0]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[0] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[0] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[0] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[0] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[0]  ),


   .ifu_buf0_excp    (ifu_buf0_excp0) ,
   .ifu_buf0_inst  (ifu_buf0_inst0[32:0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)) ;

ifu_ibu_ibf_dp ibf1 (
   .scan_in(ibf1_scanin),
   .scan_out(ibf1_scanout),
   .l2clk(l2clk),

   .ibq_buff_clken     (ibq_buff_clken[1] ),
   .ibq_ctl_clken      (ibq_ctl_clken[1] ),
   .pku_pick_p         (pku_pick_p[1]  ),

   .ftu_ic_no_err_c (ftu_ic_no_err_c),

   .ftu_instr_0_c(ftu_instr_0_c_rep0[32:0]),
   .ftu_instr_1_c(ftu_instr_1_c_rep0[32:0]),
   .ftu_instr_2_c(ftu_instr_2_c_rep0[32:0]),
   .ftu_instr_3_c(ftu_instr_3_c_rep0[32:0]),
   .ftu_instr_0_exceptions_c(ftu_instr_0_exceptions_c_rep0[4:0]),
   .ftu_instr_1_exceptions_c(ftu_instr_1_exceptions_c_rep0[4:0]),
   .ftu_instr_2_exceptions_c(ftu_instr_2_exceptions_c_rep0[4:0]),
   .ftu_instr_3_exceptions_c(ftu_instr_3_exceptions_c_rep0[4:0]),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[1] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[1] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[1] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[1] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[1] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[1] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[1] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[1] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[1]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[1]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[1]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[1]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[1]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[1]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[1]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[1]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[1]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[1]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[1]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[1] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[1] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[1] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[1] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[1]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[1] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[1] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[1] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[1] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[1]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[1] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[1] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[1] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[1] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[1]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[1] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[1] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[1] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[1] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[1]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[1] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[1] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[1] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[1] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[1]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[1] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[1] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[1] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[1] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[1]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[1] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[1] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[1] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[1] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[1]  ),


   .ifu_buf0_excp    (ifu_buf0_excp1) ,
   .ifu_buf0_inst  (ifu_buf0_inst1[32:0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)) ;

ifu_ibu_ibf_dp ibf2 (
   .scan_in(ibf2_scanin),
   .scan_out(ibf2_scanout),
   .l2clk(l2clk),

   .ibq_buff_clken     (ibq_buff_clken[2] ),
   .ibq_ctl_clken      (ibq_ctl_clken[2] ),
   .pku_pick_p         (pku_pick_p[2]  ),

   .ftu_ic_no_err_c (ftu_ic_no_err_c),

   .ftu_instr_0_c(ftu_instr_0_c_rep1[32:0]),
   .ftu_instr_1_c(ftu_instr_1_c_rep1[32:0]),
   .ftu_instr_2_c(ftu_instr_2_c_rep1[32:0]),
   .ftu_instr_3_c(ftu_instr_3_c_rep1[32:0]),
   .ftu_instr_0_exceptions_c(ftu_instr_0_exceptions_c_rep1[4:0]),
   .ftu_instr_1_exceptions_c(ftu_instr_1_exceptions_c_rep1[4:0]),
   .ftu_instr_2_exceptions_c(ftu_instr_2_exceptions_c_rep1[4:0]),
   .ftu_instr_3_exceptions_c(ftu_instr_3_exceptions_c_rep1[4:0]),


   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[2] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[2] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[2] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[2] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[2] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[2] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[2] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[2] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[2]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[2]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[2]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[2]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[2]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[2]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[2]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[2]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[2]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[2]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[2]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[2] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[2] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[2] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[2] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[2]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[2] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[2] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[2] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[2] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[2]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[2] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[2] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[2] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[2] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[2]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[2] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[2] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[2] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[2] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[2]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[2] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[2] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[2] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[2] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[2]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[2] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[2] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[2] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[2] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[2]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[2] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[2] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[2] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[2] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[2]  ),


   .ifu_buf0_excp    (ifu_buf0_excp2) ,
   .ifu_buf0_inst  (ifu_buf0_inst2[32:0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)) ;

ifu_ibu_ibf_dp ibf3 (
   .scan_in(ibf3_scanin),
   .scan_out(ibf3_scanout),
   .l2clk(l2clk),

   .ibq_buff_clken     (ibq_buff_clken[3] ),
   .ibq_ctl_clken      (ibq_ctl_clken[3] ),
   .pku_pick_p         (pku_pick_p[3]  ),

   .ftu_ic_no_err_c (ftu_ic_no_err_c),

   .ftu_instr_0_c(ftu_instr_0_c_rep1[32:0]),
   .ftu_instr_1_c(ftu_instr_1_c_rep1[32:0]),
   .ftu_instr_2_c(ftu_instr_2_c_rep1[32:0]),
   .ftu_instr_3_c(ftu_instr_3_c_rep1[32:0]),
   .ftu_instr_0_exceptions_c(ftu_instr_0_exceptions_c_rep1[4:0]),
   .ftu_instr_1_exceptions_c(ftu_instr_1_exceptions_c_rep1[4:0]),
   .ftu_instr_2_exceptions_c(ftu_instr_2_exceptions_c_rep1[4:0]),
   .ftu_instr_3_exceptions_c(ftu_instr_3_exceptions_c_rep1[4:0]),


   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[3] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[3] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[3] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[3] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[3] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[3] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[3] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[3] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[3]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[3]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[3]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[3]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[3]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[3]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[3]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[3]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[3]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[3]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[3]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[3] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[3] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[3] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[3] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[3]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[3] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[3] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[3] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[3] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[3]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[3] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[3] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[3] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[3] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[3]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[3] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[3] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[3] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[3] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[3]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[3] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[3] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[3] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[3] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[3]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[3] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[3] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[3] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[3] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[3]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[3] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[3] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[3] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[3] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[3]  ),


   .ifu_buf0_excp    (ifu_buf0_excp3) ,
   .ifu_buf0_inst  (ifu_buf0_inst3[32:0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)) ;

ifu_ibu_ibf_dp ibf4 (
   .scan_in(ibf4_scanin),
   .scan_out(ibf4_scanout),
   .l2clk(l2clk),

   .ibq_buff_clken     (ibq_buff_clken[4] ),
   .ibq_ctl_clken      (ibq_ctl_clken[4] ),
   .pku_pick_p         (pku_pick_p[4]  ),

   .ftu_ic_no_err_c (ftu_ic_no_err_c),

   .ftu_instr_0_c(ftu_instr_0_c_rep2[32:0]),
   .ftu_instr_1_c(ftu_instr_1_c_rep2[32:0]),
   .ftu_instr_2_c(ftu_instr_2_c_rep2[32:0]),
   .ftu_instr_3_c(ftu_instr_3_c_rep2[32:0]),
   .ftu_instr_0_exceptions_c(ftu_instr_0_exceptions_c_rep2[4:0]),
   .ftu_instr_1_exceptions_c(ftu_instr_1_exceptions_c_rep2[4:0]),
   .ftu_instr_2_exceptions_c(ftu_instr_2_exceptions_c_rep2[4:0]),
   .ftu_instr_3_exceptions_c(ftu_instr_3_exceptions_c_rep2[4:0]),


   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[4] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[4] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[4] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[4] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[4] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[4] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[4] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[4] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[4]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[4]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[4]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[4]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[4]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[4]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[4]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[4]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[4]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[4]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[4]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[4] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[4] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[4] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[4] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[4]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[4] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[4] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[4] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[4] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[4]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[4] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[4] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[4] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[4] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[4]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[4] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[4] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[4] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[4] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[4]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[4] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[4] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[4] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[4] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[4]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[4] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[4] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[4] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[4] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[4]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[4] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[4] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[4] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[4] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[4]  ),


   .ifu_buf0_excp    (ifu_buf0_excp4) ,
   .ifu_buf0_inst  (ifu_buf0_inst4[32:0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)) ;


ifu_ibu_ibf_dp ibf5 (
   .scan_in(ibf5_scanin),
   .scan_out(ibf5_scanout),
   .l2clk(l2clk),

   .ibq_buff_clken     (ibq_buff_clken[5] ),
   .ibq_ctl_clken      (ibq_ctl_clken[5] ),
   .pku_pick_p         (pku_pick_p[5]  ),

   .ftu_ic_no_err_c (ftu_ic_no_err_c),

   .ftu_instr_0_c(ftu_instr_0_c_rep2[32:0]),
   .ftu_instr_1_c(ftu_instr_1_c_rep2[32:0]),
   .ftu_instr_2_c(ftu_instr_2_c_rep2[32:0]),
   .ftu_instr_3_c(ftu_instr_3_c_rep2[32:0]),
   .ftu_instr_0_exceptions_c(ftu_instr_0_exceptions_c_rep2[4:0]),
   .ftu_instr_1_exceptions_c(ftu_instr_1_exceptions_c_rep2[4:0]),
   .ftu_instr_2_exceptions_c(ftu_instr_2_exceptions_c_rep2[4:0]),
   .ftu_instr_3_exceptions_c(ftu_instr_3_exceptions_c_rep2[4:0]),

   .ibq_buf0_sel_inst0_pick  (ibq_buf0_sel_inst0_pick[5] ),
   .ibq_buf0_sel_inst1_pick  (ibq_buf0_sel_inst1_pick[5] ),
   .ibq_buf0_sel_inst2_pick  (ibq_buf0_sel_inst2_pick[5] ),
   .ibq_buf0_sel_inst3_pick  (ibq_buf0_sel_inst3_pick[5] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[5] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[5] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[5] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[5] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[5]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[5]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[5]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[5]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[5]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[5]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[5]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[5]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[5]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[5]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[5]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[5] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[5] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[5] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[5] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[5]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[5] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[5] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[5] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[5] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[5]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[5] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[5] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[5] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[5] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[5]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[5] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[5] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[5] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[5] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[5]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[5] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[5] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[5] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[5] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[5]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[5] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[5] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[5] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[5] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[5]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[5] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[5] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[5] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[5] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[5]  ),


   .ifu_buf0_excp    (ifu_buf0_excp5) ,
   .ifu_buf0_inst  (ifu_buf0_inst5[32:0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)) ;

ifu_ibu_ibf_dp ibf6 (
   .scan_in(ibf6_scanin),
   .scan_out(ibf6_scanout),
   .l2clk(l2clk),

   .ibq_buff_clken     (ibq_buff_clken[6] ),
   .ibq_ctl_clken      (ibq_ctl_clken[6] ),
   .pku_pick_p         (pku_pick_p[6]  ),

   .ftu_ic_no_err_c (ftu_ic_no_err_c),

   .ftu_instr_0_c(ftu_instr_0_c_rep3[32:0]),
   .ftu_instr_1_c(ftu_instr_1_c_rep3[32:0]),
   .ftu_instr_2_c(ftu_instr_2_c_rep3[32:0]),
   .ftu_instr_3_c(ftu_instr_3_c_rep3[32:0]),
   .ftu_instr_0_exceptions_c(ftu_instr_0_exceptions_c_rep3[4:0]),
   .ftu_instr_1_exceptions_c(ftu_instr_1_exceptions_c_rep3[4:0]),
   .ftu_instr_2_exceptions_c(ftu_instr_2_exceptions_c_rep3[4:0]),
   .ftu_instr_3_exceptions_c(ftu_instr_3_exceptions_c_rep3[4:0]),


   .ibq_buf0_sel_inst0_pick  (ibq_buf0_sel_inst0_pick[6] ),
   .ibq_buf0_sel_inst1_pick  (ibq_buf0_sel_inst1_pick[6] ),
   .ibq_buf0_sel_inst2_pick  (ibq_buf0_sel_inst2_pick[6] ),
   .ibq_buf0_sel_inst3_pick  (ibq_buf0_sel_inst3_pick[6] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[6] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[6] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[6] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[6] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[6]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[6]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[6]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[6]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[6]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[6]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[6]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[6]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[6]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[6]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[6]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[6] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[6] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[6] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[6] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[6]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[6] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[6] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[6] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[6] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[6]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[6] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[6] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[6] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[6] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[6]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[6] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[6] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[6] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[6] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[6]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[6] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[6] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[6] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[6] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[6]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[6] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[6] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[6] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[6] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[6]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[6] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[6] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[6] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[6] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[6]  ),


   .ifu_buf0_excp    (ifu_buf0_excp6) ,
   .ifu_buf0_inst  (ifu_buf0_inst6[32:0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)) ;

ifu_ibu_ibf_dp ibf7 (
   .scan_in(ibf7_scanin),
   .scan_out(ibf7_scanout),
   .l2clk(l2clk),

   
   .ibq_buff_clken     (ibq_buff_clken[7] ),
   .ibq_ctl_clken      (ibq_ctl_clken[7] ),
   .pku_pick_p         (pku_pick_p[7]  ),

   .ftu_ic_no_err_c (ftu_ic_no_err_c),

   .ftu_instr_0_c(ftu_instr_0_c_rep3[32:0]),
   .ftu_instr_1_c(ftu_instr_1_c_rep3[32:0]),
   .ftu_instr_2_c(ftu_instr_2_c_rep3[32:0]),
   .ftu_instr_3_c(ftu_instr_3_c_rep3[32:0]),
   .ftu_instr_0_exceptions_c(ftu_instr_0_exceptions_c_rep3[4:0]),
   .ftu_instr_1_exceptions_c(ftu_instr_1_exceptions_c_rep3[4:0]),
   .ftu_instr_2_exceptions_c(ftu_instr_2_exceptions_c_rep3[4:0]),
   .ftu_instr_3_exceptions_c(ftu_instr_3_exceptions_c_rep3[4:0]),


   .ibq_buf0_sel_inst0_pick  (ibq_buf0_sel_inst0_pick[7] ),
   .ibq_buf0_sel_inst1_pick  (ibq_buf0_sel_inst1_pick[7] ),
   .ibq_buf0_sel_inst2_pick  (ibq_buf0_sel_inst2_pick[7] ),
   .ibq_buf0_sel_inst3_pick  (ibq_buf0_sel_inst3_pick[7] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[7] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[7] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[7] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[7] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[7]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[7]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[7]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[7]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[7]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[7]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[7]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[7]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[7]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[7]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[7]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[7] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[7] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[7] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[7] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[7]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[7] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[7] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[7] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[7] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[7]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[7] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[7] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[7] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[7] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[7]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[7] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[7] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[7] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[7] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[7]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[7] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[7] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[7] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[7] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[7]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[7] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[7] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[7] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[7] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[7]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[7] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[7] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[7] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[7] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[7]  ),


   .ifu_buf0_excp    (ifu_buf0_excp7) ,
   .ifu_buf0_inst  (ifu_buf0_inst7[32:0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)) ;

        
ifu_ibu_ibq_ctl  ibq0(
   .scan_in(ibq0_scanin),
   .scan_out(ibq0_scanout),
   .l2clk(l2clk),
   
   .pku_flush_buffer0  (pku_flush_buffer0[0]     ),
   .pku_flush_upper_buffer (pku_flush_upper_buffer[0]    ),
   
   .ftu_fetch_thr_c    (ftu_fetch_thr_c[0]   ),
   .ftu_buffer_wr_en_f (ftu_buffer_wr_en_f[0] ),
   .pku_pick_p         (pku_pick_p[0]  ),
 
   .ftu_instr_valid_c   (ftu_instr_valid_c      ),
   .ftu_redirect_bf     (ftu_ibu_redirect_bf[0]  ),

   .ifu_buf0_valid_p   (ifu_buf0_valid_p[0]   ),
   .ifu_upper_buffer_valid_p   (ifu_upper_buffer_valid_p[0]   ),


   .ibu_empty          (ibu_empty[0]          ),
   .ibu_room_4ormore   (ibu_room_4ormore[0]   ),

   .ibq_buff_clken (ibq_buff_clken[0] ),
   .ibq_ctl_clken      (ibq_ctl_clken[0] ),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[0] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[0] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[0] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[0] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[0] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[0] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[0] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[0] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[0]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[0]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[0]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[0]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[0]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[0]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[0]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[0]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[0]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[0]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[0]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[0] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[0] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[0] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[0] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[0]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[0] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[0] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[0] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[0] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[0]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[0] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[0] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[0] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[0] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[0]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[0] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[0] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[0] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[0] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[0]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[0] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[0] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[0] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[0] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[0]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[0] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[0] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[0] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[0] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[0]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[0] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[0] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[0] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[0] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[0]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .l15_ifu_valid(l15_ifu_valid),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first)) ;


ifu_ibu_ibq_ctl  ibq1(
   .scan_in(ibq1_scanin),
   .scan_out(ibq1_scanout),
   .l2clk(l2clk),
   
   .pku_flush_buffer0  (pku_flush_buffer0[1]     ),
   .pku_flush_upper_buffer (pku_flush_upper_buffer[1]    ),
   
   .ftu_fetch_thr_c        (ftu_fetch_thr_c[1]   ),
   .ftu_buffer_wr_en_f     (ftu_buffer_wr_en_f[1] ),
   .pku_pick_p             (pku_pick_p[1]  ),

   .ftu_instr_valid_c   (ftu_instr_valid_c      ),
   .ftu_redirect_bf     (ftu_ibu_redirect_bf[1]  ),

   .ifu_buf0_valid_p   (ifu_buf0_valid_p[1]   ),
   .ifu_upper_buffer_valid_p   (ifu_upper_buffer_valid_p[1]   ),


   .ibu_empty          (ibu_empty[1]          ),
   .ibu_room_4ormore   (ibu_room_4ormore[1]   ),
   .ibq_buff_clken (ibq_buff_clken[1] ),
   .ibq_ctl_clken      (ibq_ctl_clken[1] ),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[1] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[1] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[1] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[1] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[1] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[1] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[1] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[1] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[1]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[1]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[1]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[1]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[1]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[1]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[1]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[1]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[1]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[1]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[1]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[1] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[1] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[1] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[1] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[1]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[1] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[1] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[1] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[1] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[1]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[1] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[1] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[1] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[1] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[1]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[1] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[1] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[1] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[1] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[1]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[1] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[1] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[1] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[1] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[1]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[1] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[1] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[1] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[1] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[1]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[1] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[1] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[1] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[1] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[1]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .l15_ifu_valid(l15_ifu_valid),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first)) ;


ifu_ibu_ibq_ctl  ibq2(
   .scan_in(ibq2_scanin),
   .scan_out(ibq2_scanout),
   .l2clk(l2clk),
   
   .pku_flush_buffer0  (pku_flush_buffer0[2]     ),
   .pku_flush_upper_buffer (pku_flush_upper_buffer[2]    ),
   
   .ftu_fetch_thr_c        (ftu_fetch_thr_c[2]   ),
   .ftu_buffer_wr_en_f     (ftu_buffer_wr_en_f[2] ),   
   .pku_pick_p             (pku_pick_p[2]  ),

   .ftu_instr_valid_c   (ftu_instr_valid_c      ),
   .ftu_redirect_bf     (ftu_ibu_redirect_bf[2]  ),

   .ifu_buf0_valid_p   (ifu_buf0_valid_p[2]   ),
   .ifu_upper_buffer_valid_p   (ifu_upper_buffer_valid_p[2]   ),


   .ibu_empty          (ibu_empty[2]          ),
   .ibu_room_4ormore   (ibu_room_4ormore[2]   ),
   .ibq_buff_clken (ibq_buff_clken[2] ),
   .ibq_ctl_clken      (ibq_ctl_clken[2] ),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[2] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[2] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[2] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[2] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[2] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[2] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[2] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[2] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[2]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[2]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[2]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[2]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[2]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[2]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[2]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[2]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[2]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[2]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[2]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[2] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[2] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[2] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[2] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[2]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[2] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[2] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[2] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[2] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[2]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[2] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[2] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[2] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[2] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[2]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[2] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[2] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[2] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[2] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[2]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[2] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[2] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[2] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[2] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[2]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[2] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[2] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[2] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[2] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[2]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[2] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[2] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[2] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[2] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[2]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .l15_ifu_valid(l15_ifu_valid),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first)) ;


ifu_ibu_ibq_ctl  ibq3(
   .scan_in(ibq3_scanin),
   .scan_out(ibq3_scanout),
   .l2clk(l2clk),
   
   .pku_flush_buffer0  (pku_flush_buffer0[3]     ),
   .pku_flush_upper_buffer (pku_flush_upper_buffer[3]    ),
   
   .ftu_fetch_thr_c    (ftu_fetch_thr_c[3]   ),
   .ftu_buffer_wr_en_f (ftu_buffer_wr_en_f[3] ),
   .pku_pick_p         (pku_pick_p[3]  ),

   .ftu_instr_valid_c   (ftu_instr_valid_c      ),
   .ftu_redirect_bf     (ftu_ibu_redirect_bf[3]  ),

   .ifu_buf0_valid_p   (ifu_buf0_valid_p[3]   ),
   .ifu_upper_buffer_valid_p   (ifu_upper_buffer_valid_p[3]   ),


   .ibu_empty          (ibu_empty[3]          ),
   .ibu_room_4ormore   (ibu_room_4ormore[3]   ),
   .ibq_buff_clken (ibq_buff_clken[3] ),
   .ibq_ctl_clken      (ibq_ctl_clken[3] ),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[3] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[3] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[3] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[3] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[3] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[3] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[3] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[3] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[3]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[3]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[3]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[3]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[3]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[3]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[3]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[3]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[3]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[3]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[3]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[3] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[3] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[3] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[3] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[3]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[3] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[3] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[3] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[3] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[3]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[3] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[3] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[3] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[3] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[3]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[3] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[3] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[3] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[3] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[3]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[3] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[3] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[3] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[3] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[3]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[3] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[3] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[3] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[3] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[3]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[3] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[3] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[3] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[3] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[3]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .l15_ifu_valid(l15_ifu_valid),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first)) ;


ifu_ibu_ibq_ctl  ibq4(
   .scan_in(ibq4_scanin),
   .scan_out(ibq4_scanout),
   .l2clk(l2clk),
   
   .pku_flush_buffer0  (pku_flush_buffer0[4]     ),
   .pku_flush_upper_buffer (pku_flush_upper_buffer[4]    ),
   
   .ftu_fetch_thr_c    (ftu_fetch_thr_c[4]   ),
   .ftu_buffer_wr_en_f (ftu_buffer_wr_en_f[4] ),
   .pku_pick_p         (pku_pick_p[4]  ),

   .ftu_instr_valid_c   (ftu_instr_valid_c      ),
   .ftu_redirect_bf     (ftu_ibu_redirect_bf[4]  ),

   .ifu_buf0_valid_p   (ifu_buf0_valid_p[4]   ),
   .ifu_upper_buffer_valid_p   (ifu_upper_buffer_valid_p[4]   ),


   .ibu_empty          (ibu_empty[4]          ),
   .ibu_room_4ormore   (ibu_room_4ormore[4]   ),
   .ibq_buff_clken (ibq_buff_clken[4] ),
   .ibq_ctl_clken      (ibq_ctl_clken[4] ),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[4] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[4] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[4] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[4] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[4] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[4] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[4] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[4] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[4]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[4]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[4]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[4]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[4]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[4]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[4]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[4]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[4]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[4]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[4]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[4] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[4] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[4] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[4] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[4]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[4] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[4] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[4] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[4] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[4]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[4] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[4] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[4] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[4] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[4]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[4] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[4] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[4] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[4] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[4]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[4] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[4] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[4] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[4] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[4]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[4] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[4] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[4] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[4] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[4]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[4] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[4] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[4] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[4] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[4]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .l15_ifu_valid(l15_ifu_valid),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first)) ;


ifu_ibu_ibq_ctl  ibq5(
   .scan_in(ibq5_scanin),
   .scan_out(ibq5_scanout),
   .l2clk(l2clk),
   
   .pku_flush_buffer0  (pku_flush_buffer0[5]     ),
   .pku_flush_upper_buffer (pku_flush_upper_buffer[5]    ),
   
   .ftu_fetch_thr_c    (ftu_fetch_thr_c[5]   ),
   .ftu_buffer_wr_en_f (ftu_buffer_wr_en_f[5] ),
   .pku_pick_p         (pku_pick_p[5]  ),

   .ftu_instr_valid_c   (ftu_instr_valid_c      ),
   .ftu_redirect_bf     (ftu_ibu_redirect_bf[5]  ),

   .ifu_buf0_valid_p   (ifu_buf0_valid_p[5]   ),
   .ifu_upper_buffer_valid_p   (ifu_upper_buffer_valid_p[5]   ),


   .ibu_empty          (ibu_empty[5]          ),
   .ibu_room_4ormore   (ibu_room_4ormore[5]   ),
   .ibq_buff_clken (ibq_buff_clken[5] ),
   .ibq_ctl_clken      (ibq_ctl_clken[5] ),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[5] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[5] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[5] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[5] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[5] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[5] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[5] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[5] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[5]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[5]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[5]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[5]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[5]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[5]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[5]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[5]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[5]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[5]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[5]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[5] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[5] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[5] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[5] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[5]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[5] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[5] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[5] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[5] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[5]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[5] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[5] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[5] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[5] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[5]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[5] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[5] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[5] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[5] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[5]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[5] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[5] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[5] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[5] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[5]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[5] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[5] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[5] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[5] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[5]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[5] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[5] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[5] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[5] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[5]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .l15_ifu_valid(l15_ifu_valid),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first)) ;


ifu_ibu_ibq_ctl  ibq6(
   .scan_in(ibq6_scanin),
   .scan_out(ibq6_scanout),
   .l2clk(l2clk),
   
   .pku_flush_buffer0  (pku_flush_buffer0[6]     ),
   .pku_flush_upper_buffer (pku_flush_upper_buffer[6]    ),
   
   .ftu_fetch_thr_c        (ftu_fetch_thr_c[6]   ),
   .ftu_buffer_wr_en_f (ftu_buffer_wr_en_f[6] ),
   .pku_pick_p         (pku_pick_p[6]  ),

   .ftu_instr_valid_c   (ftu_instr_valid_c      ),
   .ftu_redirect_bf     (ftu_ibu_redirect_bf[6]  ),

   .ifu_buf0_valid_p   (ifu_buf0_valid_p[6]   ),
   .ifu_upper_buffer_valid_p   (ifu_upper_buffer_valid_p[6]   ),


   .ibu_empty          (ibu_empty[6]          ),
   .ibu_room_4ormore   (ibu_room_4ormore[6]   ),
   .ibq_buff_clken     (ibq_buff_clken[6] ),
   .ibq_ctl_clken      (ibq_ctl_clken[6] ),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[6] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[6] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[6] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[6] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[6] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[6] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[6] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[6] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[6]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[6]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[6]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[6]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[6]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[6]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[6]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[6]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[6]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[6]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[6]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[6] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[6] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[6] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[6] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[6]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[6] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[6] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[6] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[6] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[6]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[6] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[6] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[6] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[6] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[6]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[6] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[6] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[6] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[6] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[6]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[6] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[6] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[6] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[6] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[6]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[6] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[6] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[6] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[6] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[6]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[6] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[6] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[6] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[6] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[6]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .l15_ifu_valid(l15_ifu_valid),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first)) ;


ifu_ibu_ibq_ctl  ibq7(
   .scan_in(ibq7_scanin),
   .scan_out(ibq7_scanout),
   .l2clk(l2clk),
   
   .pku_flush_buffer0  (pku_flush_buffer0[7]     ),
   .pku_flush_upper_buffer (pku_flush_upper_buffer[7]    ),
   
   .ftu_fetch_thr_c    (ftu_fetch_thr_c[7]   ),
   .ftu_buffer_wr_en_f (ftu_buffer_wr_en_f[7] ),
   .pku_pick_p         (pku_pick_p[7]  ),

   .ftu_instr_valid_c   (ftu_instr_valid_c      ),
   .ftu_redirect_bf     (ftu_ibu_redirect_bf[7]  ),

   .ifu_buf0_valid_p   (ifu_buf0_valid_p[7]   ),
   .ifu_upper_buffer_valid_p   (ifu_upper_buffer_valid_p[7]   ),


   .ibu_empty          (ibu_empty[7]          ),
   .ibu_room_4ormore   (ibu_room_4ormore[7]   ),
   .ibq_buff_clken     (ibq_buff_clken[7] ),
   .ibq_ctl_clken      (ibq_ctl_clken[7] ),

   .ibq_buf0_sel_inst0_pick (ibq_buf0_sel_inst0_pick[7] ),
   .ibq_buf0_sel_inst1_pick (ibq_buf0_sel_inst1_pick[7] ),
   .ibq_buf0_sel_inst2_pick (ibq_buf0_sel_inst2_pick[7] ),
   .ibq_buf0_sel_inst3_pick (ibq_buf0_sel_inst3_pick[7] ),
   .ibq_buf0_sel_inst0_pick_ (ibq_buf0_sel_inst0_pick_[7] ),
   .ibq_buf0_sel_inst1_pick_ (ibq_buf0_sel_inst1_pick_[7] ),
   .ibq_buf0_sel_inst2_pick_ (ibq_buf0_sel_inst2_pick_[7] ),
   .ibq_buf0_sel_inst3_pick_ (ibq_buf0_sel_inst3_pick_[7] ),
   .ibq_buf0_sel_buf1  (ibq_buf0_sel_buf1[7]  ),
   .ibq_buf0_sel_buf2  (ibq_buf0_sel_buf2[7]  ),
   .ibq_buf0_sel_buf3  (ibq_buf0_sel_buf3[7]  ),
   .ibq_buf0_sel_buf4  (ibq_buf0_sel_buf4[7]  ),
   .ibq_buf0_sel_buf5  (ibq_buf0_sel_buf5[7]  ),
   .ibq_buf0_sel_buf6  (ibq_buf0_sel_buf6[7]  ),
   .ibq_buf0_sel_buf7  (ibq_buf0_sel_buf7[7]  ),
   .ibq_buf0_sel_hold_pick  (ibq_buf0_sel_hold_pick[7]  ),
   .ibq_buf0_sel_hold_pick_  (ibq_buf0_sel_hold_pick_[7]  ),

   .ibq_buf0_sel_buf1to7_pick (ibq_buf0_sel_buf1to7_pick[7]),
   .ibq_buf0_sel_buf1to7_pick_ (ibq_buf0_sel_buf1to7_pick_[7]),

   .ibq_buf1_sel_inst0 (ibq_buf1_sel_inst0[7] ),
   .ibq_buf1_sel_inst1 (ibq_buf1_sel_inst1[7] ),
   .ibq_buf1_sel_inst2 (ibq_buf1_sel_inst2[7] ),
   .ibq_buf1_sel_inst3 (ibq_buf1_sel_inst3[7] ),
   .ibq_buf1_sel_hold  (ibq_buf1_sel_hold[7]  ),

   .ibq_buf2_sel_inst0 (ibq_buf2_sel_inst0[7] ),
   .ibq_buf2_sel_inst1 (ibq_buf2_sel_inst1[7] ),
   .ibq_buf2_sel_inst2 (ibq_buf2_sel_inst2[7] ),
   .ibq_buf2_sel_inst3 (ibq_buf2_sel_inst3[7] ),
   .ibq_buf2_sel_hold  (ibq_buf2_sel_hold[7]  ),

   .ibq_buf3_sel_inst0 (ibq_buf3_sel_inst0[7] ),
   .ibq_buf3_sel_inst1 (ibq_buf3_sel_inst1[7] ),
   .ibq_buf3_sel_inst2 (ibq_buf3_sel_inst2[7] ),
   .ibq_buf3_sel_inst3 (ibq_buf3_sel_inst3[7] ),
   .ibq_buf3_sel_hold  (ibq_buf3_sel_hold[7]  ),

   .ibq_buf4_sel_inst0 (ibq_buf4_sel_inst0[7] ),
   .ibq_buf4_sel_inst1 (ibq_buf4_sel_inst1[7] ),
   .ibq_buf4_sel_inst2 (ibq_buf4_sel_inst2[7] ),
   .ibq_buf4_sel_inst3 (ibq_buf4_sel_inst3[7] ),
   .ibq_buf4_sel_hold  (ibq_buf4_sel_hold[7]  ),

   .ibq_buf5_sel_inst0 (ibq_buf5_sel_inst0[7] ),
   .ibq_buf5_sel_inst1 (ibq_buf5_sel_inst1[7] ),
   .ibq_buf5_sel_inst2 (ibq_buf5_sel_inst2[7] ),
   .ibq_buf5_sel_inst3 (ibq_buf5_sel_inst3[7] ),
   .ibq_buf5_sel_hold  (ibq_buf5_sel_hold[7]  ),

   .ibq_buf6_sel_inst0 (ibq_buf6_sel_inst0[7] ),
   .ibq_buf6_sel_inst1 (ibq_buf6_sel_inst1[7] ),
   .ibq_buf6_sel_inst2 (ibq_buf6_sel_inst2[7] ),
   .ibq_buf6_sel_inst3 (ibq_buf6_sel_inst3[7] ),
   .ibq_buf6_sel_hold  (ibq_buf6_sel_hold[7]  ),

   .ibq_buf7_sel_inst0 (ibq_buf7_sel_inst0[7] ),
   .ibq_buf7_sel_inst1 (ibq_buf7_sel_inst1[7] ),
   .ibq_buf7_sel_inst2 (ibq_buf7_sel_inst2[7] ),
   .ibq_buf7_sel_inst3 (ibq_buf7_sel_inst3[7] ),
   .ibq_buf7_sel_hold  (ibq_buf7_sel_hold[7]  ),
  .tcu_scan_en(tcu_scan_en),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .l15_ifu_valid(l15_ifu_valid),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first)) ;


// fixscan start:
assign ibf0_scanin               = scan_in                  ;
assign ibf1_scanin               = ibf0_scanout             ;
assign ibf2_scanin               = ibf1_scanout             ;
assign ibf3_scanin               = ibf2_scanout             ;
assign ibf4_scanin               = ibf3_scanout             ;
assign ibf5_scanin               = ibf4_scanout             ;
assign ibf6_scanin               = ibf5_scanout             ;
assign ibf7_scanin               = ibf6_scanout             ;
assign ibq0_scanin               = ibf7_scanout             ;
assign ibq1_scanin               = ibq0_scanout             ;
assign ibq2_scanin               = ibq1_scanout             ;
assign ibq3_scanin               = ibq2_scanout             ;
assign ibq4_scanin               = ibq3_scanout             ;
assign ibq5_scanin               = ibq4_scanout             ;
assign ibq6_scanin               = ibq5_scanout             ;
assign ibq7_scanin               = ibq6_scanout             ;
assign scan_out                  = ibq7_scanout             ;
// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ibu_ibf_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  ifu_ibu_ibf_dp (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  pku_pick_p, 
  ftu_instr_0_c, 
  ftu_instr_1_c, 
  ftu_instr_2_c, 
  ftu_instr_3_c, 
  ftu_instr_0_exceptions_c, 
  ftu_instr_1_exceptions_c, 
  ftu_instr_2_exceptions_c, 
  ftu_instr_3_exceptions_c, 
  ftu_ic_no_err_c, 
  ibq_buff_clken, 
  ibq_ctl_clken, 
  ibq_buf0_sel_inst0_pick, 
  ibq_buf0_sel_inst1_pick, 
  ibq_buf0_sel_inst2_pick, 
  ibq_buf0_sel_inst3_pick, 
  ibq_buf0_sel_inst0_pick_, 
  ibq_buf0_sel_inst1_pick_, 
  ibq_buf0_sel_inst2_pick_, 
  ibq_buf0_sel_inst3_pick_, 
  ibq_buf0_sel_buf1, 
  ibq_buf0_sel_buf2, 
  ibq_buf0_sel_buf3, 
  ibq_buf0_sel_buf4, 
  ibq_buf0_sel_buf5, 
  ibq_buf0_sel_buf6, 
  ibq_buf0_sel_buf7, 
  ibq_buf0_sel_hold_pick, 
  ibq_buf0_sel_hold_pick_, 
  ibq_buf0_sel_buf1to7_pick, 
  ibq_buf0_sel_buf1to7_pick_, 
  ibq_buf1_sel_inst0, 
  ibq_buf1_sel_inst1, 
  ibq_buf1_sel_inst2, 
  ibq_buf1_sel_inst3, 
  ibq_buf1_sel_hold, 
  ibq_buf2_sel_inst0, 
  ibq_buf2_sel_inst1, 
  ibq_buf2_sel_inst2, 
  ibq_buf2_sel_inst3, 
  ibq_buf2_sel_hold, 
  ibq_buf3_sel_inst0, 
  ibq_buf3_sel_inst1, 
  ibq_buf3_sel_inst2, 
  ibq_buf3_sel_inst3, 
  ibq_buf3_sel_hold, 
  ibq_buf4_sel_inst0, 
  ibq_buf4_sel_inst1, 
  ibq_buf4_sel_inst2, 
  ibq_buf4_sel_inst3, 
  ibq_buf4_sel_hold, 
  ibq_buf5_sel_inst0, 
  ibq_buf5_sel_inst1, 
  ibq_buf5_sel_inst2, 
  ibq_buf5_sel_inst3, 
  ibq_buf5_sel_hold, 
  ibq_buf6_sel_inst0, 
  ibq_buf6_sel_inst1, 
  ibq_buf6_sel_inst2, 
  ibq_buf6_sel_inst3, 
  ibq_buf6_sel_hold, 
  ibq_buf7_sel_inst0, 
  ibq_buf7_sel_inst1, 
  ibq_buf7_sel_inst2, 
  ibq_buf7_sel_inst3, 
  ibq_buf7_sel_hold, 
  ifu_buf0_inst, 
  ifu_buf0_excp, 
  scan_out);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [37:0] buf1_inst;
wire [37:0] buf2_inst;
wire [37:0] buf3_inst;
wire [37:0] buf4_inst;
wire [37:0] buf5_inst;
wire [37:0] buf6_inst;
wire [37:0] buf7_inst;
wire [37:0] buf0_in7to1;
wire pick0_;
wire pick1_;
wire pick2_;
wire buf0_sel_inst0_int0;
wire buf0_sel_inst1_int0;
wire buf0_sel_inst2_int0;
wire buf0_sel_inst3_int0;
wire buf0_sel_buf1to7_int0;
wire buf0_sel_hold_int0;
wire buf0_sel_inst0_int1;
wire buf0_sel_inst1_int1;
wire buf0_sel_inst2_int1;
wire buf0_sel_inst3_int1;
wire buf0_sel_buf1to7_int1;
wire buf0_sel_hold_int1;
wire buf0_sel_inst0;
wire buf0_sel_inst1;
wire buf0_sel_inst2;
wire buf0_sel_inst3;
wire buf0_sel_buf1to7;
wire buf0_sel_hold;
wire ic_no_err_c_buf;
wire [4:0] instr_1_exceptions_c_mod;
wire [4:0] instr_2_exceptions_c_mod;
wire [4:0] instr_3_exceptions_c_mod;
wire [37:0] buf0_in;
wire [37:0] buf1_in;
wire [37:0] buf2_in;
wire [37:0] buf3_in;
wire [37:0] buf4_in;
wire [37:0] buf5_in;
wire [37:0] buf6_in;
wire [37:0] buf7_in;
wire buf0_ff_scanin;
wire buf0_ff_scanout;
wire buf1_ff_scanin;
wire buf1_ff_scanout;
wire buf2_ff_scanin;
wire buf2_ff_scanout;
wire buf3_ff_scanin;
wire buf3_ff_scanout;
wire buf4_ff_scanin;
wire buf4_ff_scanout;
wire buf5_ff_scanin;
wire buf5_ff_scanout;
wire buf6_ff_scanin;
wire buf6_ff_scanout;
wire buf7_ff_scanin;
wire buf7_ff_scanout;


input tcu_scan_en ;
   input        l2clk ;
   input 	scan_in;
   input 	tcu_pce_ov;		// scan signals
   input 	spc_aclk;
   input 	spc_bclk;

   input        pku_pick_p;

   input [32:0] ftu_instr_0_c;
   input [32:0] ftu_instr_1_c;
   input [32:0] ftu_instr_2_c;
   input [32:0] ftu_instr_3_c;
   input  [4:0] ftu_instr_0_exceptions_c;
   input  [4:0] ftu_instr_1_exceptions_c;
   input  [4:0] ftu_instr_2_exceptions_c;
   input  [4:0] ftu_instr_3_exceptions_c;

   input        ftu_ic_no_err_c;

   input        ibq_buff_clken;
   input        ibq_ctl_clken     ;

   input        ibq_buf0_sel_inst0_pick ;
   input        ibq_buf0_sel_inst1_pick ;
   input        ibq_buf0_sel_inst2_pick ;
   input        ibq_buf0_sel_inst3_pick ;
   input        ibq_buf0_sel_inst0_pick_;
   input        ibq_buf0_sel_inst1_pick_;
   input        ibq_buf0_sel_inst2_pick_;
   input        ibq_buf0_sel_inst3_pick_;
   input        ibq_buf0_sel_buf1  ;
   input        ibq_buf0_sel_buf2  ;
   input        ibq_buf0_sel_buf3  ;
   input        ibq_buf0_sel_buf4  ;
   input        ibq_buf0_sel_buf5  ;
   input        ibq_buf0_sel_buf6  ;
   input        ibq_buf0_sel_buf7  ;
   input        ibq_buf0_sel_hold_pick  ;
   input        ibq_buf0_sel_hold_pick_ ;
         
   input        ibq_buf0_sel_buf1to7_pick;
   input        ibq_buf0_sel_buf1to7_pick_;
   
   input        ibq_buf1_sel_inst0 ;
   input        ibq_buf1_sel_inst1 ;
   input        ibq_buf1_sel_inst2 ;
   input        ibq_buf1_sel_inst3 ;
   input        ibq_buf1_sel_hold  ;
        
   input        ibq_buf2_sel_inst0 ;
   input        ibq_buf2_sel_inst1 ;
   input        ibq_buf2_sel_inst2 ;
   input        ibq_buf2_sel_inst3 ;
   input        ibq_buf2_sel_hold  ;
        
   input        ibq_buf3_sel_inst0 ;
   input        ibq_buf3_sel_inst1 ;
   input        ibq_buf3_sel_inst2 ;
   input        ibq_buf3_sel_inst3 ;
   input        ibq_buf3_sel_hold  ;
        
   input        ibq_buf4_sel_inst0 ;
   input        ibq_buf4_sel_inst1 ;
   input        ibq_buf4_sel_inst2 ;
   input        ibq_buf4_sel_inst3 ;
   input        ibq_buf4_sel_hold  ;
        
   input        ibq_buf5_sel_inst0 ;
   input        ibq_buf5_sel_inst1 ;
   input        ibq_buf5_sel_inst2 ;
   input        ibq_buf5_sel_inst3 ;
   input        ibq_buf5_sel_hold  ;
   
   input        ibq_buf6_sel_inst0 ;
   input        ibq_buf6_sel_inst1 ;
   input        ibq_buf6_sel_inst2 ;
   input        ibq_buf6_sel_inst3 ;
   input        ibq_buf6_sel_hold  ;
   
   input        ibq_buf7_sel_inst0 ;
   input        ibq_buf7_sel_inst1 ;
   input        ibq_buf7_sel_inst2 ;
   input        ibq_buf7_sel_inst3 ;
   input        ibq_buf7_sel_hold  ;
        
   output[32:0] ifu_buf0_inst      ;
   output[4:0]  ifu_buf0_excp      ;
   output 	scan_out;

// scan renames
// assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
// assign siclk = spc_aclk;
// assign soclk = spc_bclk;
// end scan

 ifu_ibu_ibf_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0  (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);


   ///////////////////////////////////////////////////////////
   // Muxing for each buffer                                //
   ///////////////////////////////////////////////////////////

   // mux types can be decided later based on area/timing.  Can also use other types of logic (i.e. and/or)
   ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_7__stack_38c__width_38 buf0_muxa  (
     .din0(buf1_inst[37:0]), 
     .din1(buf2_inst[37:0]),  
     .din2(buf3_inst[37:0]),  
     .din3(buf4_inst[37:0]), 
     .din4(buf5_inst[37:0]),  
     .din5(buf6_inst[37:0]),  
     .din6(buf7_inst[37:0]),  
     .sel0(ibq_buf0_sel_buf1),
     .sel1(ibq_buf0_sel_buf2),
     .sel2(ibq_buf0_sel_buf3),
     .sel3(ibq_buf0_sel_buf4),
     .sel4(ibq_buf0_sel_buf5),
     .sel5(ibq_buf0_sel_buf6),
     .sel6(ibq_buf0_sel_buf7),
     .dout(buf0_in7to1[37:0])
   );

   ///////////////////////////////////////////////////////////////////
   // Selects for buf0.                                             //
   ///////////////////////////////////////////////////////////////////
   ifu_ibu_ibf_dp_inv_macro__dinv_12x__width_3  pick_inv   (
      .din ({3{pku_pick_p}}),
      .dout({pick0_,pick1_,pick2_}));

   ifu_ibu_ibf_dp_nand_macro__dnand_20x__width_6 ibuf0_sel0_n0   (
     .din0 ({6{pku_pick_p}}),
     .din1 ({ibq_buf0_sel_inst0_pick,ibq_buf0_sel_inst1_pick,ibq_buf0_sel_inst2_pick,
             ibq_buf0_sel_inst3_pick,ibq_buf0_sel_buf1to7_pick,ibq_buf0_sel_hold_pick}),
     .dout ({buf0_sel_inst0_int0,buf0_sel_inst1_int0,buf0_sel_inst2_int0,
             buf0_sel_inst3_int0,buf0_sel_buf1to7_int0,buf0_sel_hold_int0})) ;

   ifu_ibu_ibf_dp_nand_macro__dnand_20x__width_6 ibuf0_sel0_n1   (
     .din0 ({2{pick0_,pick1_,pick2_}}),
     .din1 ({ibq_buf0_sel_inst0_pick_,ibq_buf0_sel_inst1_pick_,ibq_buf0_sel_inst2_pick_,
             ibq_buf0_sel_inst3_pick_,ibq_buf0_sel_buf1to7_pick_,ibq_buf0_sel_hold_pick_}),
     .dout ({buf0_sel_inst0_int1,buf0_sel_inst1_int1,buf0_sel_inst2_int1,
             buf0_sel_inst3_int1,buf0_sel_buf1to7_int1,buf0_sel_hold_int1})) ;

   ifu_ibu_ibf_dp_nand_macro__dnand_32x__width_6 ibuf0_sel0_n2   (
     .din0 ({buf0_sel_inst0_int1,buf0_sel_inst1_int1,buf0_sel_inst2_int1,
             buf0_sel_inst3_int1,buf0_sel_buf1to7_int1,buf0_sel_hold_int1}),
     .din1 ({buf0_sel_inst0_int0,buf0_sel_inst1_int0,buf0_sel_inst2_int0,
             buf0_sel_inst3_int0,buf0_sel_buf1to7_int0,buf0_sel_hold_int0}),
     .dout ({buf0_sel_inst0,buf0_sel_inst1,buf0_sel_inst2,
             buf0_sel_inst3,buf0_sel_buf1to7,buf0_sel_hold})) ;

   ////////////////////////////////////////////////////////////////////
   // Zero out the exception bits when in Ic by-pass mode and no_err //
   // This is done to avoid the PMU counting cache-misses and other  //
   // info more than once. I.e only one instruction should be marked //
   // NOTE: we can not do that when there are errors becuse we need  //  
   // to have at least two instruction marked just in case one of    //   
   // is annulled.                                                   //
   ////////////////////////////////////////////////////////////////////
   
   ifu_ibu_ibf_dp_buff_macro__dbuff_32x__stack_none__width_1 ic_no_err_buff  (
    .din (ftu_ic_no_err_c),
    .dout(ic_no_err_c_buf)
   );

   ifu_ibu_ibf_dp_and_macro__dnand_32x__width_5 except_1_and    (
     .din1 ({5{ic_no_err_c_buf}}),
     .din0 ( ftu_instr_1_exceptions_c[4:0]),
     .dout ( instr_1_exceptions_c_mod[4:0]));


   ifu_ibu_ibf_dp_and_macro__dnand_32x__width_5 except_2_and    (
     .din1 ({5{ic_no_err_c_buf}}),
     .din0 ( ftu_instr_2_exceptions_c[4:0]),
     .dout ( instr_2_exceptions_c_mod[4:0]));


   ifu_ibu_ibf_dp_and_macro__dnand_32x__width_5 except_3_and    (
     .din1 ({5{ic_no_err_c_buf}}),
     .din0 ( ftu_instr_3_exceptions_c[4:0]),
     .dout ( instr_3_exceptions_c_mod[4:0]));


   ///////////////////////////////////////////////////////////////////
   // Changed this mux to 7x1 because the instructions are no longer//
   // ordered and we do not know which one the first instruction is //
   //								    //
   ///////////////////////////////////////////////////////////////////
   
   ifu_ibu_ibf_dp_mux_macro__buffsel_none__mux_aonpe__ports_6__stack_38c__width_38 buf0_muxb  (
     .din0({ftu_instr_0_exceptions_c[4:0],ftu_instr_0_c[32:0]}),  
     .din1({instr_1_exceptions_c_mod[4:0],ftu_instr_1_c[32:0]}),  
     .din2({instr_2_exceptions_c_mod[4:0],ftu_instr_2_c[32:0]}),  
     .din3({instr_3_exceptions_c_mod[4:0],ftu_instr_3_c[32:0]}),  
     .din4(buf0_in7to1[37:0]),  
     .din5({ifu_buf0_excp[4:0], ifu_buf0_inst[32:0]}), 
     .sel0(buf0_sel_inst0),
     .sel1(buf0_sel_inst1),
     .sel2(buf0_sel_inst2),
     .sel3(buf0_sel_inst3),
     .sel4(buf0_sel_buf1to7),
     .sel5(buf0_sel_hold),
     .dout(buf0_in[37:0])
   );

//    mux_macro buf0_muxc (width=38,ports=2,mux=aope,stack=38c) (
//      .din0(buf0_flush0[37:0]),
//      .din1({ifu_buf0_excp[4:0], ifu_buf0_inst[32:0]}),
//      .sel0(ibq_buf0_sel_hold),
//      .dout(buf0_in[37:0])
//    );


   ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_5__stack_38c__width_38 buf1_mux  (
     .din0({ftu_instr_0_exceptions_c[4:0],ftu_instr_0_c[32:0]}),  
     .din1({instr_1_exceptions_c_mod[4:0],ftu_instr_1_c[32:0]}), 
     .din2({instr_2_exceptions_c_mod[4:0],ftu_instr_2_c[32:0]}), 
     .din3({instr_3_exceptions_c_mod[4:0],ftu_instr_3_c[32:0]}), 
     .din4(buf1_inst[37:0]), 
     .sel0(ibq_buf1_sel_inst0),
     .sel1(ibq_buf1_sel_inst1),
     .sel2(ibq_buf1_sel_inst2),
     .sel3(ibq_buf1_sel_inst3),
     .sel4(ibq_buf1_sel_hold),
     .dout(buf1_in[37:0])
   );

   ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_5__stack_38c__width_38 buf2_mux  (
     .din0({ftu_instr_0_exceptions_c[4:0],ftu_instr_0_c[32:0]}),  
     .din1({instr_1_exceptions_c_mod[4:0],ftu_instr_1_c[32:0]}), 
     .din2({instr_2_exceptions_c_mod[4:0],ftu_instr_2_c[32:0]}), 
     .din3({instr_3_exceptions_c_mod[4:0],ftu_instr_3_c[32:0]}), 
     .din4(buf2_inst[37:0]), 
     .sel0(ibq_buf2_sel_inst0),
     .sel1(ibq_buf2_sel_inst1),
     .sel2(ibq_buf2_sel_inst2),
     .sel3(ibq_buf2_sel_inst3),
     .sel4(ibq_buf2_sel_hold),
     .dout(buf2_in[37:0])
   );

   ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_5__stack_38c__width_38 buf3_mux  (
     .din0({ftu_instr_0_exceptions_c[4:0],ftu_instr_0_c[32:0]}),  
     .din1({instr_1_exceptions_c_mod[4:0],ftu_instr_1_c[32:0]}), 
     .din2({instr_2_exceptions_c_mod[4:0],ftu_instr_2_c[32:0]}), 
     .din3({instr_3_exceptions_c_mod[4:0],ftu_instr_3_c[32:0]}), 
     .din4(buf3_inst[37:0]), 
     .sel0(ibq_buf3_sel_inst0),
     .sel1(ibq_buf3_sel_inst1),
     .sel2(ibq_buf3_sel_inst2),
     .sel3(ibq_buf3_sel_inst3),
     .sel4(ibq_buf3_sel_hold),
     .dout(buf3_in[37:0])
   );

   ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_5__stack_38c__width_38 buf4_mux  (
     .din0({ftu_instr_0_exceptions_c[4:0],ftu_instr_0_c[32:0]}),  
     .din1({instr_1_exceptions_c_mod[4:0],ftu_instr_1_c[32:0]}), 
     .din2({instr_2_exceptions_c_mod[4:0],ftu_instr_2_c[32:0]}), 
     .din3({instr_3_exceptions_c_mod[4:0],ftu_instr_3_c[32:0]}), 
     .din4(buf4_inst[37:0]), 
     .sel0(ibq_buf4_sel_inst0),
     .sel1(ibq_buf4_sel_inst1),
     .sel2(ibq_buf4_sel_inst2),
     .sel3(ibq_buf4_sel_inst3),
     .sel4(ibq_buf4_sel_hold),
     .dout(buf4_in[37:0])
   );

   ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_5__stack_38c__width_38 buf5_mux  (
     .din0({ftu_instr_0_exceptions_c[4:0],ftu_instr_0_c[32:0]}),  
     .din1({instr_1_exceptions_c_mod[4:0],ftu_instr_1_c[32:0]}), 
     .din2({instr_2_exceptions_c_mod[4:0],ftu_instr_2_c[32:0]}), 
     .din3({instr_3_exceptions_c_mod[4:0],ftu_instr_3_c[32:0]}), 
     .din4(buf5_inst[37:0]), 
     .sel0(ibq_buf5_sel_inst0),
     .sel1(ibq_buf5_sel_inst1),
     .sel2(ibq_buf5_sel_inst2),
     .sel3(ibq_buf5_sel_inst3),
     .sel4(ibq_buf5_sel_hold),
     .dout(buf5_in[37:0])
   );

   ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_5__stack_38c__width_38 buf6_mux  (
     .din0({ftu_instr_0_exceptions_c[4:0],ftu_instr_0_c[32:0]}),  
     .din1({instr_1_exceptions_c_mod[4:0],ftu_instr_1_c[32:0]}), 
     .din2({instr_2_exceptions_c_mod[4:0],ftu_instr_2_c[32:0]}), 
     .din3({instr_3_exceptions_c_mod[4:0],ftu_instr_3_c[32:0]}), 
     .din4(buf6_inst[37:0]), 
     .sel0(ibq_buf6_sel_inst0),
     .sel1(ibq_buf6_sel_inst1),
     .sel2(ibq_buf6_sel_inst2),
     .sel3(ibq_buf6_sel_inst3),
     .sel4(ibq_buf6_sel_hold),
     .dout(buf6_in[37:0])
   );

   ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_5__stack_38c__width_38 buf7_mux  (
     .din0({ftu_instr_0_exceptions_c[4:0],ftu_instr_0_c[32:0]}),  
     .din1({instr_1_exceptions_c_mod[4:0],ftu_instr_1_c[32:0]}), 
     .din2({instr_2_exceptions_c_mod[4:0],ftu_instr_2_c[32:0]}), 
     .din3({instr_3_exceptions_c_mod[4:0],ftu_instr_3_c[32:0]}), 
     .din4(buf7_inst[37:0]), 
     .sel0(ibq_buf7_sel_inst0),
     .sel1(ibq_buf7_sel_inst1),
     .sel2(ibq_buf7_sel_inst2),
     .sel3(ibq_buf7_sel_inst3),
     .sel4(ibq_buf7_sel_hold),
     .dout(buf7_in[37:0])
   );


   ///////////////////////////////////////////////////////////
   // Flops for the buffers                                 //
   ///////////////////////////////////////////////////////////

   ifu_ibu_ibf_dp_msff_macro__dmsff_32x__stack_38c__width_38 buf0_ff   (
    .scan_in(buf0_ff_scanin),
    .scan_out(buf0_ff_scanout),
    .clk(l2clk),
    .din  (buf0_in[37:0]),
    .en   (ibq_ctl_clken),
    .dout ({ifu_buf0_excp[4:0],ifu_buf0_inst[32:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
   );

   ifu_ibu_ibf_dp_msff_macro__stack_38c__width_38 buf1_ff   (
    .scan_in(buf1_ff_scanin),
    .scan_out(buf1_ff_scanout),
    .clk(l2clk),
    .din  (buf1_in[37:0]),
    .en   (ibq_buff_clken),
    .dout (buf1_inst[37:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
   );

   ifu_ibu_ibf_dp_msff_macro__stack_38c__width_38 buf2_ff   (
    .scan_in(buf2_ff_scanin),
    .scan_out(buf2_ff_scanout),
    .clk(l2clk),
    .din  (buf2_in[37:0]),
    .en   (ibq_buff_clken),
    .dout (buf2_inst[37:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
   );
   ifu_ibu_ibf_dp_msff_macro__stack_38c__width_38 buf3_ff   (
    .scan_in(buf3_ff_scanin),
    .scan_out(buf3_ff_scanout),
    .clk(l2clk),
    .din  (buf3_in[37:0]),
    .en   (ibq_buff_clken),
    .dout (buf3_inst[37:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
   );
   ifu_ibu_ibf_dp_msff_macro__stack_38c__width_38 buf4_ff   (
    .scan_in(buf4_ff_scanin),
    .scan_out(buf4_ff_scanout),
    .clk(l2clk),
    .din  (buf4_in[37:0]),
    .en   (ibq_buff_clken),
    .dout (buf4_inst[37:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
   );
   ifu_ibu_ibf_dp_msff_macro__stack_38c__width_38 buf5_ff   (
    .scan_in(buf5_ff_scanin),
    .scan_out(buf5_ff_scanout),
    .clk(l2clk),
    .din  (buf5_in[37:0]),
    .en   (ibq_buff_clken),
    .dout (buf5_inst[37:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
   );
   ifu_ibu_ibf_dp_msff_macro__stack_38c__width_38 buf6_ff   (
    .scan_in(buf6_ff_scanin),
    .scan_out(buf6_ff_scanout),
    .clk(l2clk),
    .din  (buf6_in[37:0]),
    .en   (ibq_buff_clken),
    .dout (buf6_inst[37:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
   );
   ifu_ibu_ibf_dp_msff_macro__stack_38c__width_38 buf7_ff   (
    .scan_in(buf7_ff_scanin),
    .scan_out(buf7_ff_scanout),
    .clk(l2clk),
    .din  (buf7_in[37:0]),
    .en   (ibq_buff_clken),
    .dout (buf7_inst[37:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
   );

// fixscan start:
assign buf0_ff_scanin            = scan_in                  ;
assign buf1_ff_scanin            = buf0_ff_scanout          ;
assign buf2_ff_scanin            = buf1_ff_scanout          ;
assign buf3_ff_scanin            = buf2_ff_scanout          ;
assign buf4_ff_scanin            = buf3_ff_scanout          ;
assign buf5_ff_scanin            = buf4_ff_scanout          ;
assign buf6_ff_scanin            = buf5_ff_scanout          ;
assign buf7_ff_scanin            = buf6_ff_scanout          ;
assign scan_out                  = buf7_ff_scanout          ;
// fixscan end:
// assign se = tcu_scan_en ;
endmodule


//
//   buff macro
//
//


module ifu_ibu_ibf_dp_buff_macro__dbuff_32x__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_7__stack_38c__width_38 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;

  input [37:0] din0;
  input sel0;
  input [37:0] din1;
  input sel1;
  input [37:0] din2;
  input sel2;
  input [37:0] din3;
  input sel3;
  input [37:0] din4;
  input sel4;
  input [37:0] din5;
  input sel5;
  input [37:0] din6;
  input sel6;
  output [37:0] dout;


cl_dp1_muxbuff7_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6)
);
mux7s #(38)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .in0(din0[37:0]),
  .in1(din1[37:0]),
  .in2(din2[37:0]),
  .in3(din3[37:0]),
  .in4(din4[37:0]),
  .in5(din5[37:0]),
  .in6(din6[37:0]),
.dout(dout[37:0])
);


endmodule


//
//   invert macro
//
//


module ifu_ibu_ibf_dp_inv_macro__dinv_12x__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ifu_ibu_ibf_dp_nand_macro__dnand_20x__width_6 (
  din0, 
  din1, 
  dout);
  input [5:0] din0;
  input [5:0] din1;
  output [5:0] dout;


nand2 #(6)  d0_0 (
.in0(din0[5:0]),
.in1(din1[5:0]),
.out(dout[5:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module ifu_ibu_ibf_dp_nand_macro__dnand_32x__width_6 (
  din0, 
  din1, 
  dout);
  input [5:0] din0;
  input [5:0] din1;
  output [5:0] dout;


nand2 #(6)  d0_0 (
.in0(din0[5:0]),
.in1(din1[5:0]),
.out(dout[5:0])
);


endmodule


//
//   buff macro
//
//


module ifu_ibu_ibf_dp_buff_macro__dbuff_32x__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module ifu_ibu_ibf_dp_and_macro__dnand_32x__width_5 (
  din0, 
  din1, 
  dout);
  input [4:0] din0;
  input [4:0] din1;
  output [4:0] dout;


and2 #(5)  d0_0 (
.in0(din0[4:0]),
.in1(din1[4:0]),
.out(dout[4:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ibu_ibf_dp_mux_macro__buffsel_none__mux_aonpe__ports_6__stack_38c__width_38 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  dout);
  input [37:0] din0;
  input sel0;
  input [37:0] din1;
  input sel1;
  input [37:0] din2;
  input sel2;
  input [37:0] din3;
  input sel3;
  input [37:0] din4;
  input sel4;
  input [37:0] din5;
  input sel5;
  output [37:0] dout;


mux6s #(38)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .sel3(sel3),
  .sel4(sel4),
  .sel5(sel5),
  .in0(din0[37:0]),
  .in1(din1[37:0]),
  .in2(din2[37:0]),
  .in3(din3[37:0]),
  .in4(din4[37:0]),
  .in5(din5[37:0]),
.dout(dout[37:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module ifu_ibu_ibf_dp_mux_macro__mux_aonpe__ports_5__stack_38c__width_38 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [37:0] din0;
  input sel0;
  input [37:0] din1;
  input sel1;
  input [37:0] din2;
  input sel2;
  input [37:0] din3;
  input sel3;
  input [37:0] din4;
  input sel4;
  output [37:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(38)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[37:0]),
  .in1(din1[37:0]),
  .in2(din2[37:0]),
  .in3(din3[37:0]),
  .in4(din4[37:0]),
.dout(dout[37:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ibu_ibf_dp_msff_macro__dmsff_32x__stack_38c__width_38 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [36:0] so;

  input [37:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [37:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(38)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[37:0]),
.si({scan_in,so[36:0]}),
.so({so[36:0],scan_out}),
.q(dout[37:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ibu_ibf_dp_msff_macro__stack_38c__width_38 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [36:0] so;

  input [37:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [37:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(38)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[37:0]),
.si({scan_in,so[36:0]}),
.so({so[36:0],scan_out}),
.q(dout[37:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ifu_ibu_ibq_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module ifu_ibu_ibq_ctl (
  tcu_scan_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  pku_flush_buffer0, 
  pku_flush_upper_buffer, 
  ftu_fetch_thr_c, 
  ftu_instr_sf_valid_c, 
  pku_pick_p, 
  lsu_ifu_ibu_pmen, 
  ftu_buffer_wr_en_f, 
  l15_ifu_valid, 
  ftu_redirect_bf, 
  ftu_exception_valid_c, 
  ftu_instr_valid_c, 
  ftu_bus_0_is_first, 
  ftu_bus_1_is_first, 
  ftu_bus_2_is_first, 
  ftu_bus_3_is_first, 
  ifu_buf0_valid_p, 
  ifu_upper_buffer_valid_p, 
  ibu_empty, 
  ibu_room_4ormore, 
  ibq_buff_clken, 
  ibq_ctl_clken, 
  ibq_buf0_sel_inst0_pick, 
  ibq_buf0_sel_inst0_pick_, 
  ibq_buf0_sel_inst1_pick, 
  ibq_buf0_sel_inst1_pick_, 
  ibq_buf0_sel_inst2_pick, 
  ibq_buf0_sel_inst2_pick_, 
  ibq_buf0_sel_inst3_pick, 
  ibq_buf0_sel_inst3_pick_, 
  ibq_buf0_sel_buf1, 
  ibq_buf0_sel_buf2, 
  ibq_buf0_sel_buf3, 
  ibq_buf0_sel_buf4, 
  ibq_buf0_sel_buf5, 
  ibq_buf0_sel_buf6, 
  ibq_buf0_sel_buf7, 
  ibq_buf0_sel_hold_pick, 
  ibq_buf0_sel_hold_pick_, 
  ibq_buf0_sel_buf1to7_pick, 
  ibq_buf0_sel_buf1to7_pick_, 
  ibq_buf1_sel_inst0, 
  ibq_buf1_sel_inst1, 
  ibq_buf1_sel_inst2, 
  ibq_buf1_sel_inst3, 
  ibq_buf1_sel_hold, 
  ibq_buf2_sel_inst0, 
  ibq_buf2_sel_inst1, 
  ibq_buf2_sel_inst2, 
  ibq_buf2_sel_inst3, 
  ibq_buf2_sel_hold, 
  ibq_buf3_sel_inst0, 
  ibq_buf3_sel_inst1, 
  ibq_buf3_sel_inst2, 
  ibq_buf3_sel_inst3, 
  ibq_buf3_sel_hold, 
  ibq_buf4_sel_inst0, 
  ibq_buf4_sel_inst1, 
  ibq_buf4_sel_inst2, 
  ibq_buf4_sel_inst3, 
  ibq_buf4_sel_hold, 
  ibq_buf5_sel_inst0, 
  ibq_buf5_sel_inst1, 
  ibq_buf5_sel_inst2, 
  ibq_buf5_sel_inst3, 
  ibq_buf5_sel_hold, 
  ibq_buf6_sel_inst0, 
  ibq_buf6_sel_inst1, 
  ibq_buf6_sel_inst2, 
  ibq_buf6_sel_inst3, 
  ibq_buf6_sel_hold, 
  ibq_buf7_sel_inst0, 
  ibq_buf7_sel_inst1, 
  ibq_buf7_sel_inst2, 
  ibq_buf7_sel_inst3, 
  ibq_buf7_sel_hold, 
  scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire l1clk_pm1;
wire ibq_buff_clken_in;
wire ifu_ibu_pmen_d;
wire buff_clken_reg_scanin;
wire buff_clken_reg_scanout;
wire pmen_reg_scanin;
wire pmen_reg_scanout;
wire buf7to1_empty;
wire [7:1] curr_ip;
wire [7:1] buf_valid_p;
wire buf0_sel_hold_;
wire [7:1] nxt_fp;
wire ibq_buf1_sel_lsb;
wire ibq_buf2_sel_lsb;
wire ibq_buf3_sel_lsb;
wire ibq_buf4_sel_lsb;
wire ibq_buf5_sel_lsb;
wire ibq_buf6_sel_lsb;
wire ibq_buf7_sel_lsb;
wire buf1_val_inst0;
wire buf2_val_inst0;
wire buf3_val_inst0;
wire buf4_val_inst0;
wire buf5_val_inst0;
wire buf6_val_inst0;
wire buf7_val_inst0;
wire buf1_val_inst1;
wire buf2_val_inst1;
wire buf3_val_inst1;
wire buf4_val_inst1;
wire buf5_val_inst1;
wire buf6_val_inst1;
wire buf7_val_inst1;
wire buf1_val_inst2;
wire buf2_val_inst2;
wire buf3_val_inst2;
wire buf4_val_inst2;
wire buf5_val_inst2;
wire buf6_val_inst2;
wire buf7_val_inst2;
wire buf1_val_inst3;
wire buf2_val_inst3;
wire buf3_val_inst3;
wire buf4_val_inst3;
wire buf5_val_inst3;
wire buf6_val_inst3;
wire buf7_val_inst3;
wire buf1_val_hold;
wire buf2_val_hold;
wire buf3_val_hold;
wire buf4_val_hold;
wire buf5_val_hold;
wire buf6_val_hold;
wire buf7_val_hold;
wire ibq_buf1_sel_n_lsb;
wire ibq_buf2_sel_n_lsb;
wire ibq_buf3_sel_n_lsb;
wire ibq_buf4_sel_n_lsb;
wire ibq_buf5_sel_n_lsb;
wire ibq_buf6_sel_n_lsb;
wire ibq_buf7_sel_n_lsb;
wire instr_sf_valid_except_c;
wire fetch_sig_reg_scanin;
wire fetch_sig_reg_scanout;
wire any_instr_valid;
wire instr_sf_valid_except_p;
wire fetch_thr_p;
wire any_instr_valid_p;
wire bus_0_is_first_p;
wire bus_1_is_first_p;
wire instr_sf_valid_except_p_ff;
wire bus_2_is_first_p;
wire bus_3_is_first_p;
wire flush_upper_buffer_ff;
wire redirect_p;
wire [3:0] instr_valid_p;
wire sel_no_shift;
wire reset_fp_to_one;
wire sel_shift_left_by_one;
wire sel_shift_left_by_two;
wire sel_shift_left_by_three;
wire sel_shift_left_by_four;
wire [7:1] cur_fp;
wire cur_fp_7to2_scanin;
wire cur_fp_7to2_scanout;
wire [7:1] cur_fpq;
wire [1:1] nxt_fpd;
wire cur_fp_1_scanin;
wire cur_fp_1_scanout;
wire no_shift_ip;
wire shift_left_one_ip;
wire fp_plus_1_to_ip;
wire fp_to_ip;
wire [7:1] next_ip;
wire next_ip_7to2_scanin;
wire next_ip_7to2_scanout;
wire [7:1] curr_ipq;
wire [2:2] next_ipd;
wire next_ip_1_scanin;
wire next_ip_1_scanout;
wire [7:0] buf_valid_in;
wire [7:0] buf_valid_din;
wire valid_outpk_7to1_scanin;
wire valid_outpk_7to1_scanout;
wire true_buf0_valid_p;
wire valid_outpk_buf0_scanin;
wire valid_outpk_buf0_scanout;
wire spares_scanin;
wire spares_scanout;
wire se;


input tcu_scan_en ;
   input         l2clk;

   input 	 scan_in;
   input 	 tcu_pce_ov;			// scan signals
   input 	 spc_aclk;
   input 	 spc_bclk;

   input         pku_flush_buffer0; 		// flush buf0 only
   input         pku_flush_upper_buffer;	// flush buf1-7 only

   input         ftu_fetch_thr_c;		// enables fetch
   input         ftu_instr_sf_valid_c;          // Single instr fetch. Valid only during fetch not by_pass.
   input         pku_pick_p;			// instruction issue/pick indicator

   input         lsu_ifu_ibu_pmen;              // enable power management.
   input         ftu_buffer_wr_en_f;            // Buffer clock enables (Normal fetch)
   input         l15_ifu_valid;                 // 
   input         ftu_redirect_bf;               // The thread is redirected.
   input         ftu_exception_valid_c ;  

   input [3:0]   ftu_instr_valid_c;
   input         ftu_bus_0_is_first ;           // bus 0 contains first instr
   input         ftu_bus_1_is_first ;           // bus 1 contains first instr
   input         ftu_bus_2_is_first ;           // bus 2 contains first instr
   input         ftu_bus_3_is_first ;           // bus 3 contains first instr

   output        ifu_buf0_valid_p   ;		// buf0 valid
   output        ifu_upper_buffer_valid_p;	// at least one of buf1-7 valid


   output        ibu_empty          ;		// buf0-7 empty
   output        ibu_room_4ormore   ;		// at least 4 empty buffers

   output        ibq_buff_clken     ;
   output        ibq_ctl_clken      ;

   output        ibq_buf0_sel_inst0_pick ;
   output        ibq_buf0_sel_inst0_pick_ ;
   output        ibq_buf0_sel_inst1_pick ;
   output        ibq_buf0_sel_inst1_pick_ ;
   output        ibq_buf0_sel_inst2_pick ;
   output        ibq_buf0_sel_inst2_pick_ ;
   output        ibq_buf0_sel_inst3_pick ;
   output        ibq_buf0_sel_inst3_pick_ ;
   output        ibq_buf0_sel_buf1  ;
   output        ibq_buf0_sel_buf2  ;
   output        ibq_buf0_sel_buf3  ;
   output        ibq_buf0_sel_buf4  ;
   output        ibq_buf0_sel_buf5  ;
   output        ibq_buf0_sel_buf6  ;
   output        ibq_buf0_sel_buf7  ;
   output        ibq_buf0_sel_hold_pick  ;
   output        ibq_buf0_sel_hold_pick_  ;

   output        ibq_buf0_sel_buf1to7_pick;
   output        ibq_buf0_sel_buf1to7_pick_;
   
   output        ibq_buf1_sel_inst0 ;
   output        ibq_buf1_sel_inst1 ;
   output        ibq_buf1_sel_inst2 ;
   output        ibq_buf1_sel_inst3 ;
   output        ibq_buf1_sel_hold  ;
        
   output        ibq_buf2_sel_inst0 ;
   output        ibq_buf2_sel_inst1 ;
   output        ibq_buf2_sel_inst2 ;
   output        ibq_buf2_sel_inst3 ;
   output        ibq_buf2_sel_hold  ;
        
   output        ibq_buf3_sel_inst0 ;
   output        ibq_buf3_sel_inst1 ;
   output        ibq_buf3_sel_inst2 ;
   output        ibq_buf3_sel_inst3 ;
   output        ibq_buf3_sel_hold  ;
        
   output        ibq_buf4_sel_inst0 ;
   output        ibq_buf4_sel_inst1 ;
   output        ibq_buf4_sel_inst2 ;
   output        ibq_buf4_sel_inst3 ;
   output        ibq_buf4_sel_hold  ;
        
   output        ibq_buf5_sel_inst0 ;
   output        ibq_buf5_sel_inst1 ;
   output        ibq_buf5_sel_inst2 ;
   output        ibq_buf5_sel_inst3 ;
   output        ibq_buf5_sel_hold  ;
   
   output        ibq_buf6_sel_inst0 ;
   output        ibq_buf6_sel_inst1 ;
   output        ibq_buf6_sel_inst2 ;
   output        ibq_buf6_sel_inst3 ;
   output        ibq_buf6_sel_hold  ;
   
   output        ibq_buf7_sel_inst0 ;
   output        ibq_buf7_sel_inst1 ;
   output        ibq_buf7_sel_inst2 ;
   output        ibq_buf7_sel_inst3 ;
   output        ibq_buf7_sel_hold  ;

   output 	 scan_out;

// renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;

////////////////////////////////////////////////////////////
// cur_fp[7:1] is one hot vector showing where the
// first instruction should be written.            
// cur_fp[7:1] = 8'b00000010 means the current location  
// to write to is buf2. 
// 
// Assumptions:
// if pku_pick_p, it implies:
//   There is at least one valid inst in buf0-7.
//
// At start up:
//   curr_ip = 7'b0000010
//   cur_fp  = 7'b0000001
//   ibu_empty = 1;
//   buf7to1_empty = 1;            <--local signal
//   buf_valid_p[7:0] = 8'b0; <--local except bit 0
////////////////////////////////////////////////////////////
  
ifu_ibu_ibq_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

ifu_ibu_ibq_ctl_l1clkhdr_ctl_macro clkgen_pm (
 .l2clk(l2clk),
 .l1en (ibq_ctl_clken ),
 .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

assign ibq_buff_clken_in =    ( ftu_buffer_wr_en_f  |  l15_ifu_valid | ~ifu_ibu_pmen_d);           
assign ibq_ctl_clken     =    1'b1 ; 


ifu_ibu_ibq_ctl_msff_ctl_macro__width_1 buff_clken_reg (
    .scan_in(buff_clken_reg_scanin),
    .scan_out(buff_clken_reg_scanout),
    .l1clk(l1clk),
    .din  (ibq_buff_clken_in),
    .dout (ibq_buff_clken),
  .siclk(siclk),
  .soclk(soclk));

ifu_ibu_ibq_ctl_msff_ctl_macro__width_1 pmen_reg (
    .scan_in(pmen_reg_scanin),
    .scan_out(pmen_reg_scanout),
    .l1clk(l1clk),
    .din  (lsu_ifu_ibu_pmen),
    .dout (ifu_ibu_pmen_d),
  .siclk(siclk),
  .soclk(soclk));


// choose which instr to put in a particular buffer.
/////////////////////////////////////////////////////
// Thread 0 , buffer 0 selects                     //
/////////////////////////////////////////////////////

///////////////////////////////////////////////////////// 
// cases where buf0 gets inst0 directly:
// if inst0 is valid and all buffers are empty.
/////////////////////////////////////////////////////////
// treat (flush_buffer0 & ~flush_upper_buffer) as a pick when upper buffers are not empty 
// IB may think it is empty when fetch and pick are done at the same time.


// for the 1st level buf0 mux in dp: buf0_sel_inst0 if not taking from buf1-7.
// each ibq_buf0_sel_bufx = curr_ip[x] & buf_valid_p[x];
//

assign ibq_buf0_sel_inst0_pick_ = ((ibu_empty | pku_flush_buffer0) & buf7to1_empty) &  ftu_bus_0_is_first;
assign ibq_buf0_sel_inst0_pick  =   buf7to1_empty &  ftu_bus_0_is_first;
assign ibq_buf0_sel_inst1_pick_ = ((ibu_empty | pku_flush_buffer0) & buf7to1_empty) &  ftu_bus_1_is_first;
assign ibq_buf0_sel_inst1_pick  =   buf7to1_empty &  ftu_bus_1_is_first;
assign ibq_buf0_sel_inst2_pick_ = ((ibu_empty | pku_flush_buffer0) & buf7to1_empty) &  ftu_bus_2_is_first;
assign ibq_buf0_sel_inst2_pick  =   buf7to1_empty &  ftu_bus_2_is_first;
assign ibq_buf0_sel_inst3_pick_ = ((ibu_empty | pku_flush_buffer0) & buf7to1_empty) &  ftu_bus_3_is_first;
assign ibq_buf0_sel_inst3_pick  =   buf7to1_empty &  ftu_bus_3_is_first;

assign ibq_buf0_sel_buf1to7_pick_ = (ibq_buf0_sel_buf1 | ibq_buf0_sel_buf2 | ibq_buf0_sel_buf3 | ibq_buf0_sel_buf4 | ibq_buf0_sel_buf5 |
                              ibq_buf0_sel_buf6 | ibq_buf0_sel_buf7) &  pku_flush_buffer0 ;
                            
assign ibq_buf0_sel_buf1to7_pick  = (ibq_buf0_sel_buf1 | ibq_buf0_sel_buf2 | ibq_buf0_sel_buf3 | ibq_buf0_sel_buf4 | ibq_buf0_sel_buf5 |
                              ibq_buf0_sel_buf6 | ibq_buf0_sel_buf7)  ;
                            
                            
///////////////////////////////////////////////////////// 
// cases where buf0 gets inst from buf1-7:
// a) curr_ip points at buf1-7 and that inst is valid
///////////////////////////////////////////////////////// 

//can do concurrent pick and flush (but no refill of buf0)

assign ibq_buf0_sel_buf1 = curr_ip[1] & buf_valid_p[1];
assign ibq_buf0_sel_buf2 = curr_ip[2] & buf_valid_p[2];
assign ibq_buf0_sel_buf3 = curr_ip[3] & buf_valid_p[3];
assign ibq_buf0_sel_buf4 = curr_ip[4] & buf_valid_p[4];
assign ibq_buf0_sel_buf5 = curr_ip[5] & buf_valid_p[5]; 
assign ibq_buf0_sel_buf6 = curr_ip[6] & buf_valid_p[6]; 
assign ibq_buf0_sel_buf7 = curr_ip[7] & buf_valid_p[7];

///////////////////////////////////////////////////////// 
// the output from the 1st level buf0 mux in dp can make it to the end if:
// a). pku_pick_p = 1 and flush_upper_buffer = 0 OR          (issue)
// b). pku_flush_buffer0 = 1 and flush_upper_buffer = 0 OR   (issue equivalent)
// c). ibu_empty = 1 and ftu_fetch_thr_c = 1 and ftu_instr_valid_c[0] = 1 
//     (and buf7to1_empty = 1)                                (fetch)
//
// the output should be held if:
// a). pku_pick_p = 0 and pku_flush_buffer0 = 0 AND  (no issue)
// b). ftu_instr_valid_c[0] = 0                      (no fetch)
///////////////////////////////////////////////////////// 

// assign buf0_sel_hold_ = pku_flush_buffer0 | (ftu_fetch_thr_c & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | 
//                                ftu_instr_valid_c[2] | ftu_instr_valid_c[3]) &  ibu_empty & buf7to1_empty);

assign buf0_sel_hold_     = pku_flush_buffer0 | (ibu_empty & buf7to1_empty);
assign ibq_buf0_sel_hold_pick_  = ~(buf0_sel_hold_ );
assign ibq_buf0_sel_hold_pick   = 1'b0 ;
/////////////////////////////////////////////////////
// Thread 0 , buffer 1-7 selects                     
// Buf1-7 will fetch as usual while flush_upper_buffer is on, but the valid bits will be off.
/////////////////////////////////////////////////////
 
///////////////////////////////////////////////////////// 
// Example using buf1:
// buf1 gets inst0: 
// - cur_fp[1], fetch & inst0 valid (inst_vld_0 & addr_x00)
// - cur_fp[7], fetch & inst0 valid (inst_vld_3 & addr_011)
// - cur_fp[6], fetch & inst0 valid (inst_vld_2 & addr_010)
// - cur_fp[5], fetch & inst0 valid (inst_vld_1 & addr_001)
//   
// buf1 gets inst1: 
// - cur_fp[7], fetch & inst0 valid (inst_vld_0 & addr_x00)
// - cur_fp[6], fetch & inst0 valid (inst_vld_3 & addr_011)
// - cur_fp[5], fetch & inst0 valid (inst_vld_2 & addr_010)
// - cur_fp[1], fetch & inst0 valid (inst_vld_1 & addr_001)
//
// buf1 gets inst2:
// - cur_fp[6], fetch & inst0 valid (inst_vld_0 & addr_x00)
// - cur_fp[7], fetch & inst0 valid (inst_vld_3 & addr_011)
// - cur_fp[1], fetch & inst0 valid (inst_vld_2 & addr_010)
// - cur_fp[5], fetch & inst0 valid (inst_vld_1 & addr_001)
//
// buf1 gets inst3:
// - cur_fp[5], fetch & inst0 valid (inst_vld_0 & addr_x00)
// - cur_fp[6], fetch & inst0 valid (inst_vld_3 & addr_011)
// - cur_fp[7], fetch & inst0 valid (inst_vld_2 & addr_010)
// - cur_fp[1], fetch & inst0 valid (inst_vld_1 & addr_001)
//
///////////////////////////////////////////////////////// 


//////////////////////////////////////////////////////////////
// Bus 0 selects
//////////////////////////////////////////////////////////////
assign ibq_buf1_sel_inst0 = ((nxt_fp[1] & ftu_bus_0_is_first)|
                             (nxt_fp[5] & ftu_bus_1_is_first)|
                             (nxt_fp[6] & ftu_bus_2_is_first)|
                             (nxt_fp[7] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf2_sel_inst0 = ((nxt_fp[2] & ftu_bus_0_is_first)|
                             (nxt_fp[6] & ftu_bus_1_is_first)|
                             (nxt_fp[7] & ftu_bus_2_is_first)|
                             (nxt_fp[1] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf3_sel_inst0 = ((nxt_fp[3] & ftu_bus_0_is_first)|
                             (nxt_fp[7] & ftu_bus_1_is_first)|
                             (nxt_fp[1] & ftu_bus_2_is_first)|
                             (nxt_fp[2] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf4_sel_inst0 = ((nxt_fp[4] & ftu_bus_0_is_first)|
                             (nxt_fp[1] & ftu_bus_1_is_first)|
                             (nxt_fp[2] & ftu_bus_2_is_first)|
                             (nxt_fp[3] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf5_sel_inst0 = ((nxt_fp[5] & ftu_bus_0_is_first)|
                             (nxt_fp[2] & ftu_bus_1_is_first)|
                             (nxt_fp[3] & ftu_bus_2_is_first)|
                             (nxt_fp[4] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf6_sel_inst0 = ((nxt_fp[6] & ftu_bus_0_is_first)|
                             (nxt_fp[3] & ftu_bus_1_is_first)|
                             (nxt_fp[4] & ftu_bus_2_is_first)|
                             (nxt_fp[5] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf7_sel_inst0 = ((nxt_fp[7] & ftu_bus_0_is_first)|
                             (nxt_fp[4] & ftu_bus_1_is_first)|
                             (nxt_fp[5] & ftu_bus_2_is_first)|
                             (nxt_fp[6] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

//////////////////////////////////////////////////////////////
// Bus 1 selects
//////////////////////////////////////////////////////////////
assign ibq_buf1_sel_inst1 = ((nxt_fp[7] & ftu_bus_0_is_first)|
                             (nxt_fp[1] & ftu_bus_1_is_first)|
                             (nxt_fp[5] & ftu_bus_2_is_first)|
                             (nxt_fp[6] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf2_sel_inst1 = ((nxt_fp[1] & ftu_bus_0_is_first)|
                             (nxt_fp[2] & ftu_bus_1_is_first)|
                             (nxt_fp[6] & ftu_bus_2_is_first)|
                             (nxt_fp[7] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf3_sel_inst1 = ((nxt_fp[2] & ftu_bus_0_is_first)|
                             (nxt_fp[3] & ftu_bus_1_is_first)|
                             (nxt_fp[7] & ftu_bus_2_is_first)|
                             (nxt_fp[1] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf4_sel_inst1 = ((nxt_fp[3] & ftu_bus_0_is_first)|
                             (nxt_fp[4] & ftu_bus_1_is_first)|
                             (nxt_fp[1] & ftu_bus_2_is_first)|
                             (nxt_fp[2] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf5_sel_inst1 = ((nxt_fp[4] & ftu_bus_0_is_first)|
                             (nxt_fp[5] & ftu_bus_1_is_first)|
                             (nxt_fp[2] & ftu_bus_2_is_first)|
                             (nxt_fp[3] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf6_sel_inst1 = ((nxt_fp[5] & ftu_bus_0_is_first)|
                             (nxt_fp[6] & ftu_bus_1_is_first)|
                             (nxt_fp[3] & ftu_bus_2_is_first)|
                             (nxt_fp[4] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf7_sel_inst1 = ((nxt_fp[6] & ftu_bus_0_is_first)|
                             (nxt_fp[7] & ftu_bus_1_is_first)|
                             (nxt_fp[4] & ftu_bus_2_is_first)|
                             (nxt_fp[5] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

//////////////////////////////////////////////////////////////
// Bus 2 selects
//////////////////////////////////////////////////////////////
assign ibq_buf1_sel_inst2 = ((nxt_fp[6] & ftu_bus_0_is_first)|
                             (nxt_fp[7] & ftu_bus_1_is_first)|
                             (nxt_fp[1] & ftu_bus_2_is_first)|
                             (nxt_fp[5] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf2_sel_inst2 = ((nxt_fp[7] & ftu_bus_0_is_first)|
                             (nxt_fp[1] & ftu_bus_1_is_first)|
                             (nxt_fp[2] & ftu_bus_2_is_first)|
                             (nxt_fp[6] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf3_sel_inst2 = ((nxt_fp[1] & ftu_bus_0_is_first)|
                             (nxt_fp[2] & ftu_bus_1_is_first)|
                             (nxt_fp[3] & ftu_bus_2_is_first)|
                             (nxt_fp[7] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf4_sel_inst2 = ((nxt_fp[2] & ftu_bus_0_is_first)|
                             (nxt_fp[3] & ftu_bus_1_is_first)|
                             (nxt_fp[4] & ftu_bus_2_is_first)|
                             (nxt_fp[1] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf5_sel_inst2 = ((nxt_fp[3] & ftu_bus_0_is_first)|
                             (nxt_fp[4] & ftu_bus_1_is_first)|
                             (nxt_fp[5] & ftu_bus_2_is_first)|
                             (nxt_fp[2] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf6_sel_inst2 = ((nxt_fp[4] & ftu_bus_0_is_first)|
                             (nxt_fp[5] & ftu_bus_1_is_first)|
                             (nxt_fp[6] & ftu_bus_2_is_first)|
                             (nxt_fp[3] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf7_sel_inst2 = ((nxt_fp[5] & ftu_bus_0_is_first)|
                             (nxt_fp[6] & ftu_bus_1_is_first)|
                             (nxt_fp[7] & ftu_bus_2_is_first)|
                             (nxt_fp[4] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

//////////////////////////////////////////////////////////////
// Bus 3 selects
//////////////////////////////////////////////////////////////
assign ibq_buf1_sel_inst3 = ((nxt_fp[5] & ftu_bus_0_is_first)|
                             (nxt_fp[6] & ftu_bus_1_is_first)|
                             (nxt_fp[7] & ftu_bus_2_is_first)|
                             (nxt_fp[1] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf2_sel_inst3 = ((nxt_fp[6] & ftu_bus_0_is_first)|
                             (nxt_fp[7] & ftu_bus_1_is_first)|
                             (nxt_fp[1] & ftu_bus_2_is_first)|
                             (nxt_fp[2] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf3_sel_inst3 = ((nxt_fp[7] & ftu_bus_0_is_first)|
                             (nxt_fp[1] & ftu_bus_1_is_first)|
                             (nxt_fp[2] & ftu_bus_2_is_first)|
                             (nxt_fp[3] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf4_sel_inst3 = ((nxt_fp[1] & ftu_bus_0_is_first)|
                             (nxt_fp[2] & ftu_bus_1_is_first)|
                             (nxt_fp[3] & ftu_bus_2_is_first)|
                             (nxt_fp[4] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf5_sel_inst3 = ((nxt_fp[2] & ftu_bus_0_is_first)|
                             (nxt_fp[3] & ftu_bus_1_is_first)|
                             (nxt_fp[4] & ftu_bus_2_is_first)|
                             (nxt_fp[5] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf6_sel_inst3 = ((nxt_fp[3] & ftu_bus_0_is_first)|
                             (nxt_fp[4] & ftu_bus_1_is_first)|
                             (nxt_fp[5] & ftu_bus_2_is_first)|
                             (nxt_fp[6] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf7_sel_inst3 = ((nxt_fp[4] & ftu_bus_0_is_first)|
                             (nxt_fp[5] & ftu_bus_1_is_first)|
                             (nxt_fp[6] & ftu_bus_2_is_first)|
                             (nxt_fp[7] & ftu_bus_3_is_first)) &  ftu_fetch_thr_c & ibu_room_4ormore;

assign ibq_buf1_sel_hold = ~(ibq_buf1_sel_inst0 | ibq_buf1_sel_inst1 | ibq_buf1_sel_inst2 | ibq_buf1_sel_inst3);
assign ibq_buf2_sel_hold = ~(ibq_buf2_sel_inst0 | ibq_buf2_sel_inst1 | ibq_buf2_sel_inst2 | ibq_buf2_sel_inst3);
assign ibq_buf3_sel_hold = ~(ibq_buf3_sel_inst0 | ibq_buf3_sel_inst1 | ibq_buf3_sel_inst2 | ibq_buf3_sel_inst3);
assign ibq_buf4_sel_hold = ~(ibq_buf4_sel_inst0 | ibq_buf4_sel_inst1 | ibq_buf4_sel_inst2 | ibq_buf4_sel_inst3);
assign ibq_buf5_sel_hold = ~(ibq_buf5_sel_inst0 | ibq_buf5_sel_inst1 | ibq_buf5_sel_inst2 | ibq_buf5_sel_inst3);
assign ibq_buf6_sel_hold = ~(ibq_buf6_sel_inst0 | ibq_buf6_sel_inst1 | ibq_buf6_sel_inst2 | ibq_buf6_sel_inst3);
assign ibq_buf7_sel_hold = ~(ibq_buf7_sel_inst0 | ibq_buf7_sel_inst1 | ibq_buf7_sel_inst2 | ibq_buf7_sel_inst3);


// prepare for the pointer shifting

assign ibq_buf1_sel_lsb   = ftu_fetch_thr_c &   ~ftu_redirect_bf & ((nxt_fp[1]    &  ftu_bus_0_is_first  & ftu_instr_valid_c[0])  | 
                                                 (nxt_fp[1] & ftu_bus_1_is_first  & ftu_instr_valid_c[1])  | 		      
				 	         (nxt_fp[1] & ftu_bus_2_is_first  & ftu_instr_valid_c[2])  |      
                                                 (nxt_fp[1] & ftu_bus_3_is_first  & ftu_instr_valid_c[3]));

assign ibq_buf2_sel_lsb   = ftu_fetch_thr_c &   ~ftu_redirect_bf & ((nxt_fp[2] & ftu_bus_0_is_first & ftu_instr_valid_c[0]) | 
                                                 (nxt_fp[2] & ftu_bus_1_is_first & ftu_instr_valid_c[1]) | 		      
				 	         (nxt_fp[2] & ftu_bus_2_is_first & ftu_instr_valid_c[2]) |      
                                                 (nxt_fp[2] & ftu_bus_3_is_first & ftu_instr_valid_c[3]));

assign ibq_buf3_sel_lsb   = ftu_fetch_thr_c &   ~ftu_redirect_bf & ((nxt_fp[3] & ftu_bus_0_is_first & ftu_instr_valid_c[0]) | 
                                                 (nxt_fp[3] & ftu_bus_1_is_first & ftu_instr_valid_c[1]) | 		      
				 	         (nxt_fp[3] & ftu_bus_2_is_first & ftu_instr_valid_c[2]) |      
                                                 (nxt_fp[3] & ftu_bus_3_is_first & ftu_instr_valid_c[3]));

assign ibq_buf4_sel_lsb   = ftu_fetch_thr_c &   ~ftu_redirect_bf & ((nxt_fp[4] & ftu_bus_0_is_first & ftu_instr_valid_c[0]) | 
                                                 (nxt_fp[4] & ftu_bus_1_is_first & ftu_instr_valid_c[1]) | 		      
				 	         (nxt_fp[4] & ftu_bus_2_is_first & ftu_instr_valid_c[2]) |      
                                                 (nxt_fp[4] & ftu_bus_3_is_first & ftu_instr_valid_c[3]));

assign ibq_buf5_sel_lsb   = ftu_fetch_thr_c &   ~ftu_redirect_bf & ((nxt_fp[5] & ftu_bus_0_is_first & ftu_instr_valid_c[0]) | 
                                                 (nxt_fp[5] & ftu_bus_1_is_first & ftu_instr_valid_c[1]) | 		      
				 	         (nxt_fp[5] & ftu_bus_2_is_first & ftu_instr_valid_c[2]) |      
                                                 (nxt_fp[5] & ftu_bus_3_is_first & ftu_instr_valid_c[3]));

assign ibq_buf6_sel_lsb   = ftu_fetch_thr_c &   ~ftu_redirect_bf & ((nxt_fp[6] & ftu_bus_0_is_first & ftu_instr_valid_c[0]) | 
                                                 (nxt_fp[6] & ftu_bus_1_is_first & ftu_instr_valid_c[1]) | 		      
				 	         (nxt_fp[6] & ftu_bus_2_is_first & ftu_instr_valid_c[2]) |      
                                                 (nxt_fp[6] & ftu_bus_3_is_first & ftu_instr_valid_c[3]));

assign ibq_buf7_sel_lsb   = ftu_fetch_thr_c &   ~ftu_redirect_bf & ((nxt_fp[7] & ftu_bus_0_is_first & ftu_instr_valid_c[0]) | 
                                                 (nxt_fp[7] & ftu_bus_1_is_first & ftu_instr_valid_c[1]) | 		      
				 	         (nxt_fp[7] & ftu_bus_2_is_first & ftu_instr_valid_c[2]) |      
                                                 (nxt_fp[7] & ftu_bus_3_is_first & ftu_instr_valid_c[3]));

//////////////////////////////////////////////////////////////
// Bus 0 selects
//////////////////////////////////////////////////////////////
assign buf1_val_inst0 =    ((nxt_fp[1] & ftu_bus_0_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[5] & ftu_bus_1_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[6] & ftu_bus_2_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[7] & ftu_bus_3_is_first & ftu_instr_valid_c[0])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf2_val_inst0 =    ((nxt_fp[2] & ftu_bus_0_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[6] & ftu_bus_1_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[7] & ftu_bus_2_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[1] & ftu_bus_3_is_first & ftu_instr_valid_c[0])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf3_val_inst0 =    ((nxt_fp[3] & ftu_bus_0_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[7] & ftu_bus_1_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[1] & ftu_bus_2_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[2] & ftu_bus_3_is_first & ftu_instr_valid_c[0])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf4_val_inst0 =    ((nxt_fp[4] & ftu_bus_0_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[1] & ftu_bus_1_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[2] & ftu_bus_2_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[3] & ftu_bus_3_is_first & ftu_instr_valid_c[0])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf5_val_inst0 =    ((nxt_fp[5] & ftu_bus_0_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[2] & ftu_bus_1_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[3] & ftu_bus_2_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[4] & ftu_bus_3_is_first & ftu_instr_valid_c[0])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf6_val_inst0 =    ((nxt_fp[6] & ftu_bus_0_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[3] & ftu_bus_1_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[4] & ftu_bus_2_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[5] & ftu_bus_3_is_first & ftu_instr_valid_c[0])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf7_val_inst0 =    ((nxt_fp[7] & ftu_bus_0_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[4] & ftu_bus_1_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[5] & ftu_bus_2_is_first & ftu_instr_valid_c[0])|
                            (nxt_fp[6] & ftu_bus_3_is_first & ftu_instr_valid_c[0])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

//////////////////////////////////////////////////////////////
// Bus 1 selects
//////////////////////////////////////////////////////////////
assign buf1_val_inst1 =    ((nxt_fp[7] & ftu_bus_0_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[1] & ftu_bus_1_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[5] & ftu_bus_2_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[6] & ftu_bus_3_is_first & ftu_instr_valid_c[1])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf2_val_inst1 =    ((nxt_fp[1] & ftu_bus_0_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[2] & ftu_bus_1_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[6] & ftu_bus_2_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[7] & ftu_bus_3_is_first & ftu_instr_valid_c[1])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf3_val_inst1 =    ((nxt_fp[2] & ftu_bus_0_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[3] & ftu_bus_1_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[7] & ftu_bus_2_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[1] & ftu_bus_3_is_first & ftu_instr_valid_c[1])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf4_val_inst1 =    ((nxt_fp[3] & ftu_bus_0_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[4] & ftu_bus_1_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[1] & ftu_bus_2_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[2] & ftu_bus_3_is_first & ftu_instr_valid_c[1])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf5_val_inst1 =    ((nxt_fp[4] & ftu_bus_0_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[5] & ftu_bus_1_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[2] & ftu_bus_2_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[3] & ftu_bus_3_is_first & ftu_instr_valid_c[1])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf6_val_inst1 =    ((nxt_fp[5] & ftu_bus_0_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[6] & ftu_bus_1_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[3] & ftu_bus_2_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[4] & ftu_bus_3_is_first & ftu_instr_valid_c[1])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf7_val_inst1 =    ((nxt_fp[6] & ftu_bus_0_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[7] & ftu_bus_1_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[4] & ftu_bus_2_is_first & ftu_instr_valid_c[1])|
                            (nxt_fp[5] & ftu_bus_3_is_first & ftu_instr_valid_c[1])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

//////////////////////////////////////////////////////////////
// Bus 2 selects
//////////////////////////////////////////////////////////////
assign buf1_val_inst2 =    ((nxt_fp[6] & ftu_bus_0_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[7] & ftu_bus_1_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[1] & ftu_bus_2_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[5] & ftu_bus_3_is_first & ftu_instr_valid_c[2])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf2_val_inst2 =    ((nxt_fp[7] & ftu_bus_0_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[1] & ftu_bus_1_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[2] & ftu_bus_2_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[6] & ftu_bus_3_is_first & ftu_instr_valid_c[2])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf3_val_inst2 =    ((nxt_fp[1] & ftu_bus_0_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[2] & ftu_bus_1_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[3] & ftu_bus_2_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[7] & ftu_bus_3_is_first & ftu_instr_valid_c[2])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf4_val_inst2 =    ((nxt_fp[2] & ftu_bus_0_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[3] & ftu_bus_1_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[4] & ftu_bus_2_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[1] & ftu_bus_3_is_first & ftu_instr_valid_c[2])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf5_val_inst2 =    ((nxt_fp[3] & ftu_bus_0_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[4] & ftu_bus_1_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[5] & ftu_bus_2_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[2] & ftu_bus_3_is_first & ftu_instr_valid_c[2])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf6_val_inst2 =    ((nxt_fp[4] & ftu_bus_0_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[5] & ftu_bus_1_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[6] & ftu_bus_2_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[3] & ftu_bus_3_is_first & ftu_instr_valid_c[2])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf7_val_inst2 =    ((nxt_fp[5] & ftu_bus_0_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[6] & ftu_bus_1_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[7] & ftu_bus_2_is_first & ftu_instr_valid_c[2])|
                            (nxt_fp[4] & ftu_bus_3_is_first & ftu_instr_valid_c[2])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

//////////////////////////////////////////////////////////////
// Bus 3 selects
//////////////////////////////////////////////////////////////
assign buf1_val_inst3 =    ((nxt_fp[5] & ftu_bus_0_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[6] & ftu_bus_1_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[7] & ftu_bus_2_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[1] & ftu_bus_3_is_first & ftu_instr_valid_c[3])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf2_val_inst3 =    ((nxt_fp[6] & ftu_bus_0_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[7] & ftu_bus_1_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[1] & ftu_bus_2_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[2] & ftu_bus_3_is_first & ftu_instr_valid_c[3])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf3_val_inst3 =    ((nxt_fp[7] & ftu_bus_0_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[1] & ftu_bus_1_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[2] & ftu_bus_2_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[3] & ftu_bus_3_is_first & ftu_instr_valid_c[3])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf4_val_inst3 =    ((nxt_fp[1] & ftu_bus_0_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[2] & ftu_bus_1_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[3] & ftu_bus_2_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[4] & ftu_bus_3_is_first & ftu_instr_valid_c[3])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf5_val_inst3 =    ((nxt_fp[2] & ftu_bus_0_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[3] & ftu_bus_1_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[4] & ftu_bus_2_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[5] & ftu_bus_3_is_first & ftu_instr_valid_c[3])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf6_val_inst3 =    ((nxt_fp[3] & ftu_bus_0_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[4] & ftu_bus_1_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[5] & ftu_bus_2_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[6] & ftu_bus_3_is_first & ftu_instr_valid_c[3])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf7_val_inst3 =    ((nxt_fp[4] & ftu_bus_0_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[5] & ftu_bus_1_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[6] & ftu_bus_2_is_first & ftu_instr_valid_c[3])|
                            (nxt_fp[7] & ftu_bus_3_is_first & ftu_instr_valid_c[3])) &  ftu_fetch_thr_c & ~ftu_redirect_bf;

assign buf1_val_hold = (buf1_val_inst0 | buf1_val_inst1 | buf1_val_inst2 | buf1_val_inst3);
assign buf2_val_hold = (buf2_val_inst0 | buf2_val_inst1 | buf2_val_inst2 | buf2_val_inst3);
assign buf3_val_hold = (buf3_val_inst0 | buf3_val_inst1 | buf3_val_inst2 | buf3_val_inst3);
assign buf4_val_hold = (buf4_val_inst0 | buf4_val_inst1 | buf4_val_inst2 | buf4_val_inst3);
assign buf5_val_hold = (buf5_val_inst0 | buf5_val_inst1 | buf5_val_inst2 | buf5_val_inst3);
assign buf6_val_hold = (buf6_val_inst0 | buf6_val_inst1 | buf6_val_inst2 | buf6_val_inst3);
assign buf7_val_hold = (buf7_val_inst0 | buf7_val_inst1 | buf7_val_inst2 | buf7_val_inst3);


assign ibq_buf1_sel_n_lsb =  buf1_val_hold & ~ibq_buf1_sel_lsb ;
assign ibq_buf2_sel_n_lsb =  buf2_val_hold & ~ibq_buf2_sel_lsb ;
assign ibq_buf3_sel_n_lsb =  buf3_val_hold & ~ibq_buf3_sel_lsb ;
assign ibq_buf4_sel_n_lsb =  buf4_val_hold & ~ibq_buf4_sel_lsb ;
assign ibq_buf5_sel_n_lsb =  buf5_val_hold & ~ibq_buf5_sel_lsb ;
assign ibq_buf6_sel_n_lsb =  buf6_val_hold & ~ibq_buf6_sel_lsb ;
assign ibq_buf7_sel_n_lsb =  buf7_val_hold & ~ibq_buf7_sel_lsb ;


///////////////////////////////////////////////////////// 
// Generate the cur_fp[7:1]                            //
///////////////////////////////////////////////////////// 
// The new fp depends on the numbers of new instrs     //
// whether the buffer is empty, and the original       //
// pointer. Here are all the different cases.          //
//                                                     //
// 1) cur_fp is the same if :                          //
//    a) no fetch -- don't care about emptiness or pick//
//       fetch = ftu_fetch_thr_c & ftu_instr_valid_c[0]//
// 2) nxt_fp is cur_fp shift left by one.              //
//    a) 1 new inst fetched                            //
// 3) nxt_fp is cur_fp shift left by two.              //
//    a) 2 new inst fetched                            // 
// 4) nxt_fp is cur_fp shift left by three.            //
//    a) 3 new inst fetched                            //
// 5) nxt_fp is cur_fp shift left by four              //
//    a) 4 new inst fetched                            //
///////////////////////////////////////////////////////// 
assign instr_sf_valid_except_c = ftu_instr_sf_valid_c & ftu_exception_valid_c & ftu_fetch_thr_c; 
ifu_ibu_ibq_ctl_msff_ctl_macro__width_14 fetch_sig_reg (
    .scan_in(fetch_sig_reg_scanin),
    .scan_out(fetch_sig_reg_scanout),
    .l1clk(l1clk),
    .din  ({ftu_fetch_thr_c,any_instr_valid,ftu_bus_0_is_first, ftu_bus_1_is_first, instr_sf_valid_except_c,instr_sf_valid_except_p, 
            ftu_bus_2_is_first, ftu_bus_3_is_first ,pku_flush_upper_buffer,ftu_redirect_bf,ftu_instr_valid_c[3:0] }),
    .dout ({fetch_thr_p,any_instr_valid_p,bus_0_is_first_p, bus_1_is_first_p, instr_sf_valid_except_p,instr_sf_valid_except_p_ff,
            bus_2_is_first_p, bus_3_is_first_p,flush_upper_buffer_ff,redirect_p,instr_valid_p[3:0]}),
  .siclk(siclk),
  .soclk(soclk));

// all the shifts must be re-evaluated.

assign sel_no_shift            = ~reset_fp_to_one & ~(fetch_thr_p & any_instr_valid_p) ;

assign sel_shift_left_by_one   = ~reset_fp_to_one & fetch_thr_p & ~redirect_p & 
                                                   ((bus_0_is_first_p & instr_valid_p[0] & ~instr_valid_p[1]) |
                                                    (bus_1_is_first_p & instr_valid_p[1] & ~instr_valid_p[2]) |
                                                    (bus_2_is_first_p & instr_valid_p[2] & ~instr_valid_p[3]) |
                                                    (bus_3_is_first_p & instr_valid_p[3] & ~instr_valid_p[0]));
						    
assign sel_shift_left_by_two   = ~reset_fp_to_one & fetch_thr_p & ~redirect_p & 
                                                   ((bus_0_is_first_p & instr_valid_p[1] & ~instr_valid_p[2]) |
                                                    (bus_1_is_first_p & instr_valid_p[2] & ~instr_valid_p[3]) |
                                                    (bus_2_is_first_p & instr_valid_p[3] & ~instr_valid_p[0]) |
                                                    (bus_3_is_first_p & instr_valid_p[0] & ~instr_valid_p[1]));

assign sel_shift_left_by_three = ~reset_fp_to_one & fetch_thr_p & ~redirect_p & 
                                                   ((bus_0_is_first_p & instr_valid_p[2] & ~instr_valid_p[3]) |
                                                    (bus_1_is_first_p & instr_valid_p[3] & ~instr_valid_p[0]) |
                                                    (bus_2_is_first_p & instr_valid_p[0] & ~instr_valid_p[1]) |
                                                    (bus_3_is_first_p & instr_valid_p[1] & ~instr_valid_p[2]));

assign sel_shift_left_by_four  = ~reset_fp_to_one & fetch_thr_p & ~redirect_p & 
                                                   ((bus_0_is_first_p & instr_valid_p[3] ) |
                                                    (bus_1_is_first_p & instr_valid_p[0] ) |
                                                    (bus_2_is_first_p & instr_valid_p[1] ) |
                                                    (bus_3_is_first_p & instr_valid_p[2] ));

assign reset_fp_to_one = flush_upper_buffer_ff  | instr_sf_valid_except_p_ff; 

assign nxt_fp[7:1] = ({7{sel_no_shift}} & cur_fp[7:1]) |
                     ({7{reset_fp_to_one}} & 7'b0000001) | 
 		     ({7{sel_shift_left_by_one}} & {cur_fp[6:1], cur_fp[7]}) |
                     ({7{sel_shift_left_by_two}} & {cur_fp[5:1], cur_fp[7:6]}) | 
		     ({7{sel_shift_left_by_three}} & {cur_fp[4:1], cur_fp[7:5]})|
		     ({7{sel_shift_left_by_four}} & {cur_fp[3:1], cur_fp[7:4]});

ifu_ibu_ibq_ctl_msff_ctl_macro__width_6 cur_fp_7to2 (
    .scan_in(cur_fp_7to2_scanin),
    .scan_out(cur_fp_7to2_scanout),
    .l1clk(l1clk_pm1),
    .din  (nxt_fp[7:2]),
    .dout (cur_fpq[7:2]),
  .siclk(siclk),
  .soclk(soclk)
   );
   
assign nxt_fpd[1] = ~nxt_fp[1];

ifu_ibu_ibq_ctl_msff_ctl_macro__width_1 cur_fp_1 (
    .scan_in(cur_fp_1_scanin),
    .scan_out(cur_fp_1_scanout),
    .l1clk(l1clk_pm1),
    .din  (nxt_fpd[1]),
    .dout (cur_fpq[1]),
  .siclk(siclk),
  .soclk(soclk)
   );

assign cur_fp[7:1] = {cur_fpq[7:2], ~cur_fpq[1]}  ;

// redirecting the pointer(s)
// update curr_ip, up to one instruction issued per cycle:
// if the pointer is at 7'b10000000, then restart from 7'b00000001;
// special when buf1-7 are empty. aka. issueing an instruction from buf0.

///////////////////////////////////////////////////////// 
// Generate the next_ip[7:1]                           
///////////////////////////////////////////////////////// 
//                                                     
// must note whether an instr goes into buf0           
// must note the fetch&issue case                      
// 1) next_ip shifts by one if ~pku_flush_upper_buffer:
//    - pick or flush0 occurs while ~buf7to1_empty     
//    - fetch occurs (at buf0) while buf0_sel_inst0*   
// 2) next_ip stays if ~pku_flush_upper_buffer:        
//    - ~pick and ~flush0 & nofetch at buf0                             
// 3) next_ip = nxt_fp if pku_flush_upper_buffer       
///////////////////////////////////////////////////////// 


   assign no_shift_ip       = ~(shift_left_one_ip |  fp_plus_1_to_ip | fp_to_ip) ;
   assign shift_left_one_ip =  ((pku_pick_p | (pku_flush_buffer0 & ~ibu_empty)))  & ~pku_flush_upper_buffer & ~instr_sf_valid_except_p;
   assign fp_to_ip          =  (pku_flush_upper_buffer | instr_sf_valid_except_p) & ~(ibu_empty | pku_pick_p | pku_flush_buffer0) ;
   assign fp_plus_1_to_ip   =  (pku_flush_upper_buffer | instr_sf_valid_except_p) &  (ibu_empty | pku_pick_p | pku_flush_buffer0); 


assign next_ip[7:1] = ({7{shift_left_one_ip}} & {curr_ip[6:1], curr_ip[7]}) |
                      ({7{no_shift_ip}} & curr_ip[7:1]) |
                      ({7{fp_to_ip}}    & 7'b0000001)  |
                      ({7{fp_plus_1_to_ip}} & 7'b0000010);

ifu_ibu_ibq_ctl_msff_ctl_macro__width_6 next_ip_7to2 (
    .scan_in(next_ip_7to2_scanin),
    .scan_out(next_ip_7to2_scanout),
    .l1clk(l1clk),
    .din  ({next_ip[7:3],next_ip[1]}),
    .dout ({curr_ipq[7:3],curr_ipq[1]}),
  .siclk(siclk),
  .soclk(soclk)
   );

assign next_ipd[2] = ~next_ip[2];
ifu_ibu_ibq_ctl_msff_ctl_macro__width_1 next_ip_1 (
    .scan_in(next_ip_1_scanin),
    .scan_out(next_ip_1_scanout),
    .l1clk(l1clk),
    .din  (next_ipd[2]),
    .dout (curr_ipq[2]),
  .siclk(siclk),
  .soclk(soclk)
   );

assign curr_ip[7:1] = { curr_ipq[7:3], ~curr_ipq[2], curr_ipq[1]}  ;

////////////////////////////////////////////////////////
// generate the valids for buf1-7:                      
// curr    next                                         
// 0       0     a) no fetch, no issue OR 
//               b) fetched inst0 & ibu_empty                   
// 0       1     a) fetch inst0 but cannot have below 
//                  i)  buf0_sel_inst0 = 1
//                  ii) flush_upper_buffer = 1
//               b) fetch inst1 or 2 & ~flush_upper                  
// 1       0     a) issue or flush_upper and no fetch     
// 1       1     a) no issue (stay valid)
//                  i)  ~pku_pick_p & ~flush_upper
//                  ii) ~flush_upper             
// buf0_sel_inst0 means ftu_fetch_thr_c & ftu_instr_valid_c[0] & (ibu_empty | (pku_pick_p | pku_flush_buffer0) & buf7to1_empty).
// (ibq_buf1_sel_inst0 & ~ibq_buf0_sel_inst0) | ibq_buf1_sel_inst1 | ibq_buf1_sel_inst2 | (~ibq_buf0_sel_buf1 & buf_valid_p[1])
// if an instruction is issued from any buffer, invalidate that entry.
//////////////////////////////////////////////////////// 

assign buf_valid_in[1] = (((ibq_buf1_sel_lsb & ~(ftu_fetch_thr_c &  
                          (ibu_empty | (pku_pick_p | pku_flush_buffer0) & buf7to1_empty))) | 
                           ibq_buf1_sel_n_lsb) & ~buf_valid_p[1]) | 		  
                          (~(curr_ip[1] & (pku_pick_p | pku_flush_buffer0)) & buf_valid_p[1]) |
                          (ftu_exception_valid_c  & ftu_fetch_thr_c & ~ftu_redirect_bf);		       

assign buf_valid_in[2] = (((ibq_buf2_sel_lsb & ~(ftu_fetch_thr_c &  
                          (ibu_empty | (pku_pick_p | pku_flush_buffer0) & buf7to1_empty))) | 
                           ibq_buf2_sel_n_lsb) & ~buf_valid_p[2]) | 		  
                          (~(curr_ip[2] & (pku_pick_p | pku_flush_buffer0)) & buf_valid_p[2])|		       
                          (ftu_exception_valid_c  & ftu_fetch_thr_c & ~ftu_redirect_bf);		       

assign buf_valid_in[3] = (((ibq_buf3_sel_lsb & ~(ftu_fetch_thr_c &  
                          (ibu_empty | (pku_pick_p | pku_flush_buffer0) & buf7to1_empty))) | 
                           ibq_buf3_sel_n_lsb) & ~buf_valid_p[3]) | 		  
                          (~(curr_ip[3] & (pku_pick_p | pku_flush_buffer0)) & buf_valid_p[3])|		       
                          (ftu_exception_valid_c  & ftu_fetch_thr_c & ~ftu_redirect_bf);		       

assign buf_valid_in[4] = (((ibq_buf4_sel_lsb & ~(ftu_fetch_thr_c &  
                          (ibu_empty | (pku_pick_p | pku_flush_buffer0) & buf7to1_empty))) | 
                           ibq_buf4_sel_n_lsb) & ~buf_valid_p[4]) | 		  
                          (~(curr_ip[4] & (pku_pick_p | pku_flush_buffer0)) & buf_valid_p[4])|		       
                          (ftu_exception_valid_c  & ftu_fetch_thr_c & ~ftu_redirect_bf);		       

assign buf_valid_in[5] = (((ibq_buf5_sel_lsb & ~(ftu_fetch_thr_c &  
                          (ibu_empty | (pku_pick_p | pku_flush_buffer0) & buf7to1_empty))) | 
                           ibq_buf5_sel_n_lsb) & ~buf_valid_p[5]) | 		  
                          (~(curr_ip[5] & (pku_pick_p | pku_flush_buffer0)) & buf_valid_p[5])|		       
                          (ftu_exception_valid_c  & ftu_fetch_thr_c & ~ftu_redirect_bf);		       

assign buf_valid_in[6] = (((ibq_buf6_sel_lsb & ~(ftu_fetch_thr_c &  
                          (ibu_empty | (pku_pick_p | pku_flush_buffer0) & buf7to1_empty))) | 
                           ibq_buf6_sel_n_lsb) & ~buf_valid_p[6]) | 		  
                          (~(curr_ip[6] & (pku_pick_p | pku_flush_buffer0)) & buf_valid_p[6])|		       
                          (ftu_exception_valid_c  & ftu_fetch_thr_c & ~ftu_redirect_bf);		       

assign buf_valid_in[7] = (((ibq_buf7_sel_lsb & ~(ftu_fetch_thr_c &  
                          (ibu_empty | (pku_pick_p | pku_flush_buffer0) & buf7to1_empty))) | 
                           ibq_buf7_sel_n_lsb) & ~buf_valid_p[7]) | 		  
                          (~(curr_ip[7] & (pku_pick_p | pku_flush_buffer0)) & buf_valid_p[7])|		       
                          (ftu_exception_valid_c  & ftu_fetch_thr_c & ~ftu_redirect_bf);		       

assign buf_valid_din[7:1] = ({7{~pku_flush_upper_buffer & ~instr_sf_valid_except_p}} & buf_valid_in[7:1]);

ifu_ibu_ibq_ctl_msff_ctl_macro__width_7 valid_outpk_7to1 (
    .scan_in(valid_outpk_7to1_scanin),
    .scan_out(valid_outpk_7to1_scanout),
    .l1clk(l1clk_pm1),
    .din(buf_valid_din[7:1]),
    .dout (buf_valid_p[7:1]),
  .siclk(siclk),
  .soclk(soclk)
   );

/////////////////////////////////////////////////////// 
// generate the valids for buf0:                       
// curr    next                                        
// 0       0     no fetch, no issue OR fetch one & (issue one | flush0) ?                    
// 0       1     fetch 1 or more instr (issue cannot be on):                    
//               - ftu_fetch_thr_c & ftu_instr_valid_c[0]
//               - ifu_buf0_valid_p = 0 (same as ibu_empty = 1)
//               - flush0 = 0
//               - flush_upper = 0
//
// 1       0     issue & buf7to1_empty or flush0       
// 1       1     a) issue or flush0 & ~buf7to1_empty
//                  - pku_pick_p | pku_flush_buffer0 = 1
//                  - flush_upper = 0
//                  - buf7to1_empty = 0
//                  - flush0 = 0
//               b)  issue or flush0 & buf7to1_empty & fetch
//                  - pku_pick_p | pku_flush_buffer0 = 1
//                  - flush_upper = 0  
//                  - buf7to1_empty = 1
//                  - ftu_fetch_thr_c & ftu_instr_valid_c[0]
//                  - flush0 = 0
//               c) no issue 
//                  - pku_pick_p = 0
//                  - flush_upper = x  
//                  - flush0 = 0
//
//               ~flush_upper OR ~issue & ~flush0      
////////////////////////////////////////////////////////

// validate if buf0 picks any entry in buf1-7, stay validated if no pick, or any fetching is done
assign any_instr_valid =  ~ftu_redirect_bf & (ftu_instr_valid_c[0] | ftu_instr_valid_c[1] | ftu_instr_valid_c[2] | ftu_instr_valid_c[3]) ;

assign buf_valid_in[0] = ( ftu_fetch_thr_c   &  any_instr_valid & ~true_buf0_valid_p & ~pku_flush_upper_buffer ) | 
			 ( ftu_fetch_thr_c   &  any_instr_valid &  true_buf0_valid_p &  pku_pick_p & ~pku_flush_upper_buffer) | 
			 (~true_buf0_valid_p & ~buf7to1_empty   & ~pku_flush_upper_buffer) | 
			 ( pku_pick_p        & ~buf7to1_empty   & ~pku_flush_upper_buffer) |
			 (~pku_pick_p        &  true_buf0_valid_p);
			

assign buf_valid_din[0] = buf_valid_in[0] |
                          (ftu_exception_valid_c  & ftu_fetch_thr_c & ~ftu_redirect_bf & ~pku_flush_upper_buffer );

ifu_ibu_ibq_ctl_msff_ctl_macro__width_1 valid_outpk_buf0 (
    .scan_in(valid_outpk_buf0_scanin),
    .scan_out(valid_outpk_buf0_scanout),
    .l1clk(l1clk_pm1),
    .din(buf_valid_din[0]),
    .dout (ifu_buf0_valid_p),
  .siclk(siclk),
  .soclk(soclk)
   );

assign true_buf0_valid_p = ifu_buf0_valid_p & ~pku_flush_buffer0;

assign ifu_upper_buffer_valid_p = (buf_valid_p[1] | buf_valid_p[2] | buf_valid_p[3] | 
                                   buf_valid_p[4] | buf_valid_p[5] | buf_valid_p[6] |
				   buf_valid_p[7] ) & ~instr_sf_valid_except_p;


assign buf7to1_empty = ~ifu_upper_buffer_valid_p;
assign ibu_empty = ~ifu_buf0_valid_p;


// room for >4: check buffers 1-7 ;
assign ibu_room_4ormore =  (~buf_valid_p[1] & ~buf_valid_p[2] & ~buf_valid_p[3] & ~buf_valid_p[4]) |
                           (~buf_valid_p[2] & ~buf_valid_p[3] & ~buf_valid_p[4] & ~buf_valid_p[5]) |
                           (~buf_valid_p[3] & ~buf_valid_p[4] & ~buf_valid_p[5] & ~buf_valid_p[6]) |
                           (~buf_valid_p[4] & ~buf_valid_p[5] & ~buf_valid_p[6] & ~buf_valid_p[7]) |
                           (~buf_valid_p[5] & ~buf_valid_p[6] & ~buf_valid_p[7] & ~buf_valid_p[1]) |
                           (~buf_valid_p[6] & ~buf_valid_p[7] & ~buf_valid_p[1] & ~buf_valid_p[2]) |
                           (~buf_valid_p[7] & ~buf_valid_p[1] & ~buf_valid_p[2] & ~buf_valid_p[3]);

///////////////////////////////////////////////////////////////////////
// Spare circuits                                                    //
///////////////////////////////////////////////////////////////////////
ifu_ibu_ibq_ctl_spare_ctl_macro__num_2 spares  (
    .scan_in(spares_scanin),
    .scan_out(spares_scanout),
    .l1clk  (l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss;
supply1 vdd;
assign se = tcu_scan_en ;
// fixscan start:
assign buff_clken_reg_scanin     = scan_in                  ;
assign pmen_reg_scanin           = buff_clken_reg_scanout   ;
assign fetch_sig_reg_scanin      = pmen_reg_scanout         ;
assign cur_fp_7to2_scanin        = fetch_sig_reg_scanout    ;
assign cur_fp_1_scanin           = cur_fp_7to2_scanout      ;
assign next_ip_7to2_scanin       = cur_fp_1_scanout         ;
assign next_ip_1_scanin          = next_ip_7to2_scanout     ;
assign valid_outpk_7to1_scanin   = next_ip_1_scanout        ;
assign valid_outpk_buf0_scanin   = valid_outpk_7to1_scanout ;
assign spares_scanin             = valid_outpk_buf0_scanout ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module ifu_ibu_ibq_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ibu_ibq_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ibu_ibq_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ibu_ibq_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ifu_ibu_ibq_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module ifu_ibu_ibq_ctl_spare_ctl_macro__num_2 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));
assign scan_out = so_1;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu (
  l2clk, 
  scan_in, 
  wmr_scan_in, 
  tcu_pce_ov, 
  spc_aclk_wmr, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  lb_scan_en_wmr, 
  scan_out, 
  wmr_scan_out, 
  const_cpuid, 
  ifu_lsu_if_vld, 
  ifu_lsu_if_tid, 
  ifu_lsu_if_addr, 
  lsu_ifu_ctxt_data, 
  lsu_ifu_tid_w, 
  lsu_ifu_wr_p0ctxt, 
  lsu_ifu_wr_p1ctxt, 
  lsu_ifu_wr_pid, 
  lsu_immu_enable, 
  lsu_ic_enable, 
  lsu_ifu_ld_index, 
  lsu_ifu_direct_map, 
  lsu_ifu_no_miss, 
  lsu_cpx_data, 
  lsu_cpx_cpkt, 
  lsu_cpx_valid, 
  dec_lsu_tg_d, 
  dec_ld_inst_d, 
  dec_ld_inst_e, 
  dec_st_inst_e, 
  dec_fpldst_inst_e, 
  dec_fsr_ldst_e, 
  dec_ldst_dbl_e, 
  dec_pref_inst_e, 
  dec_flush_inst_e, 
  dec_memstbar_inst_e, 
  dec_sr_inst_e, 
  dec_pr_inst_e, 
  dec_hpr_inst_e, 
  dec_casa_inst_e, 
  dec_ldstub_inst_e, 
  dec_swap_inst_e, 
  dec_altspace_d, 
  dec_sign_ext_e, 
  dec_ldst_sz_e, 
  dec_lsu_rd_e, 
  dec_sraddr_e, 
  dec_imm_asi_vld_d, 
  dec_imm_asi_d, 
  dec_frf_r2_addr_e, 
  dec_flush_lm, 
  dec_flush_lb, 
  dec_lsu_tid0_d, 
  dec_lsu_tid1_d, 
  lsu_block_store_stall, 
  lsu_block_store_rd, 
  lsu_block_store_tid, 
  lsu_cpq_stall, 
  lsu_sync, 
  lsu_complete, 
  lsu_stb_alloc, 
  lsu_stb_dealloc, 
  lsu_block_store_kill, 
  tlu_flush_lsu_b, 
  tlu_pstate_cle, 
  tlu_asi_0, 
  tlu_asi_1, 
  tlu_asi_0_tid, 
  tlu_asi_1_tid, 
  tlu_asi_0_valid, 
  tlu_asi_1_valid, 
  tlu_lsu_hpstate_hpriv, 
  tlu_lsu_pstate_priv, 
  tlu_tl_gt_0, 
  tlu_lsu_clear_ctl_reg_, 
  tlu_tte, 
  tlu_cerer_dttp, 
  tlu_cerer_dttm, 
  tlu_cerer_dtdp, 
  tlu_cerer_dcvp, 
  tlu_cerer_dctp, 
  tlu_cerer_dctm, 
  tlu_cerer_dcdp, 
  tlu_cerer_dcl2c, 
  tlu_cerer_dcl2u, 
  tlu_cerer_dcl2nd, 
  tlu_cerer_sbdlc, 
  tlu_cerer_sbdlu, 
  tlu_cerer_sbapp, 
  tlu_cerer_sbdiou, 
  tlu_cerer_sbdpc, 
  tlu_cerer_sbdpu, 
  tlu_cerer_l2c_socc, 
  tlu_cerer_l2u_socu, 
  lsu_stb_empty, 
  lsu_trap_flush, 
  lsu_tlb_bypass_b, 
  lsu_tlb_real_b, 
  lsu_align_b, 
  lsu_lddf_align_b, 
  lsu_stdf_align_b, 
  lsu_dae_invalid_asi_b, 
  lsu_dae_nc_page_b, 
  lsu_dae_nfo_page_b, 
  lsu_dae_priv_viol_b, 
  lsu_dae_so_page, 
  lsu_priv_action_b, 
  lsu_va_watchpoint_b, 
  lsu_pa_watchpoint_b, 
  lsu_tlb_miss_b_, 
  lsu_illegal_inst_b, 
  lsu_daccess_prot_b, 
  lsu_perfmon_trap_b, 
  lsu_perfmon_trap_g, 
  lsu_priv_action_g, 
  lsu_tid_g, 
  lsu_tlu_dsfsr_ct_b, 
  lsu_sync_inst_b, 
  lsu_tlu_twocycle_m, 
  lsu_asi_error_inject, 
  lsu_dcmh_err_g, 
  lsu_dcvp_err_g, 
  lsu_dctp_err_g, 
  lsu_dcdp_err_g, 
  lsu_dcl2c_err_g, 
  lsu_dcl2u_err_g, 
  lsu_dcl2nd_err_g, 
  lsu_dcsoc_err_g, 
  lsu_dcerr_tid_g, 
  lsu_dcerr_sfar_g, 
  lsu_sbdlc_err_g, 
  lsu_sbdlu_err_g, 
  lsu_sbdpc_err_g, 
  lsu_sbdpu_err_g, 
  lsu_sbapp_err_g, 
  lsu_sbdiou_err_g, 
  lsu_stberr_tid_g, 
  lsu_stberr_index_g, 
  lsu_stberr_priv_g, 
  lsu_stb_flush_g, 
  lsu_dttp_err_b, 
  lsu_dtdp_err_b, 
  lsu_dtmh_err_b, 
  lsu_ext_interrupt, 
  lsu_ext_int_type, 
  lsu_ext_int_vec, 
  lsu_ext_int_tid, 
  mmu_dtlb_reload, 
  lsu_mmu_va_b, 
  lsu_context_b, 
  exu_lsu_rs2_e, 
  exu_lsu_address_e, 
  exu_lsu_store_data_e, 
  exu_lsu_va_error_m, 
  exu_ecc_m, 
  lsu_exu_ld_data_b, 
  lsu_exu_ld_vld_w, 
  lsu_exu_ld_b, 
  lsu_exu_rd_m, 
  lsu_exu_tid_m, 
  lsu_exu_address_e, 
  lsu_sel_lsu_addr_e, 
  fgu_lsu_fst_data_fx1, 
  fgu_fst_ecc_error_fx2, 
  fgu_fdiv_stall, 
  lsu_fgu_fld_data_b, 
  lsu_fgu_fld_vld_w, 
  lsu_fgu_fld_b, 
  lsu_fgu_fld_addr_b, 
  lsu_fgu_fld_tid_b, 
  lsu_fgu_fld_32b_b, 
  lsu_fgu_fld_odd32b_b, 
  lsu_fgu_fsr_load_b, 
  lsu_fgu_exception_w, 
  lsu_block_store_m, 
  lsu_frf_read_pending, 
  pmu_lsu_dcmiss_trap_m, 
  pmu_lsu_dtmiss_trap_m, 
  pmu_lsu_l2dmiss_trap_m, 
  lsu_pmu_mem_type_b, 
  l15_lsu_grant, 
  lsu_l15_lock, 
  lsu_l15_valid, 
  lsu_l15_addr, 
  lsu_l15_cpkt, 
  lsu_l15_data, 
  cpx_spc_data_cx, 
  tlu_rngf_cdbus, 
  tlu_rngf_cdbus_error, 
  rngl_lsu_cdbus, 
  lsu_rngf_cdbus, 
  lsu_rngl_cdbus, 
  lbist_run, 
  mbi_addr, 
  mbi_run, 
  mbi_wdata, 
  mbi_ptag_data, 
  mbi_cmpsel, 
  mbi_dca_read_en, 
  mbi_dca_write_en, 
  lsu_mbi_dca_fail, 
  mbi_dta_read_en, 
  mbi_dta_write_en, 
  lsu_mbi_dta_fail, 
  mbi_dva_read_en, 
  mbi_dva_write_en, 
  lsu_mbi_dva_fail, 
  mbi_lru_read_en, 
  mbi_lru_write_en, 
  lsu_mbi_lru_fail, 
  mbi_dtb_read_en, 
  mbi_dtb_write_en, 
  lsu_mbi_dtb_fail, 
  mbi_stb_cam_read_en, 
  mbi_stb_cam_write_en, 
  lsu_mbi_stb_cam_fail, 
  mbi_stb_ram_read_en, 
  mbi_stb_ram_write_en, 
  lsu_mbi_stb_ram_fail, 
  mbi_cpq_read_en, 
  mbi_cpq_write_en, 
  lsu_mbi_cpq_fail, 
  mbi_cambist_run, 
  mbi_cambist_shift, 
  mbi_dis_clr_ubit, 
  mbi_init_to_zero, 
  mbi_dtb_cam_en_pre, 
  mbi_repl_write, 
  mbi_dtb_demap_en, 
  mbi_demap_type, 
  lsu_mbi_tlb_data_cmp, 
  lsu_mbi_tlb_cam_hit, 
  lsu_mbi_tlb_cam_mhit, 
  lsu_mbi_tlb_ctxt0_hit, 
  lsu_mbi_tlb_valid, 
  lsu_mbi_tlb_used, 
  mbi_scm_cam_en_pre, 
  lsu_mbi_scm_hit, 
  lsu_mbi_scm_mhit, 
  lsu_mbi_scm_hit_ptr, 
  lsu_mbi_scm_praw, 
  dmo_coresel, 
  dmo_dcmuxctl, 
  dcc_dmo_parity, 
  lsu_ic_pmen, 
  lsu_ifu_cmu_pmen, 
  lsu_ifu_ftu_pmen, 
  lsu_ifu_ibu_pmen, 
  lsu_dec_pmen, 
  lsu_pku_pmen, 
  lsu_exu_pmen, 
  lsu_fgu_pmen, 
  lsu_tlu_pmen, 
  lsu_gkt_pmen, 
  lsu_spu_pmen, 
  lsu_mmu_pmen, 
  lsu_pmu_pmen, 
  lsu_misc_pmen, 
  lsu_asi_clken, 
  efu_spc_fuse_data, 
  efu_spc_fuse_dxfer_en, 
  efu_spc_fuse_dclr, 
  slow_cmp_sync_en, 
  cmp_slow_sync_en, 
  spc_efu_fuse_ddata, 
  spc_efu_fuse_dxfer_en, 
  vnw_ary);
wire tcu_aclk;
wire tcu_bclk;
wire pce;
wire rd_pce;
wire wr_pce;
wire bist_clk_mux_sel;
wire [129:0] spc_pcx_data_pa;
wire lsu_dc_pmen;
wire [15:0] lsu_asi_pwr_mgmt;
wire lsu_lsu_pmen;
wire arc_scanin;
wire arc_scanout;
wire ard_scanin;
wire ard_scanout;
wire dcd_scanin;
wire dcd_scanout;
wire [7:0] dac_bist_cmp_data;
wire dac_scanin;
wire dac_scanout;
wire [3:0] cache_way_hit_top_b;
wire dcache_bypass_e_;
wire dcc_dca_bypass_e_;
wire dcache_clk_en_e;
wire dcc_dca_clk_en_e;
wire dcache_rclk_en_m;
wire dcc_dca_rclk_en_m;
wire dcache_wclk_en_e;
wire dcc_dca_wclk_en_e;
wire [10:4] exu_lsu_address_e_rep0;
wire [10:3] dcc_dca_fill_addr_e;
wire dcc_alt_addr_sel_e;
wire dcc_dca_rvld_e;
wire dcc_dca_wvld_e;
wire [15:0] dcp_parity;
wire [127:0] dcp_fill_data_e;
wire [1:0] dcc_dca_fill_way_e;
wire [15:0] dcc_dca_byte_wr_en_e;
wire [3:0] dcc_alt_rsel_way_m;
wire dcc_alt_way_sel_m;
wire [3:0] tlb_cache_way_hit_b;
wire dca_scanin;
wire dca_scanout;
wire [63:0] dca_ld_data_b;
wire [7:0] dca_rparity_b;
wire dca_perr_w0_b;
wire dca_perr_w1_b;
wire dca_perr_w2_b;
wire dca_perr_w3_b;
wire [63:0] lmd_fill_or_byp_data_m_rep1;
wire [7:0] dca_msb_w0_b;
wire [7:0] dca_msb_w1_b;
wire [7:0] dca_msb_w2_b;
wire [7:0] dca_msb_w3_b;
wire [6:0] hdr_sram_rvalue;
wire [1:0] hdr_sram_rid;
wire hdr_sram_wr_en;
wire hdr_sram_red_clr;
wire [5:0] dca_fuse_repair_value;
wire [1:1] dca_fuse_repair_en_unused;
wire dca_fuse_repair_en;
wire dcc_mbi_run;
wire [3:0] lru_unused;
wire [3:0] lru_parity_unused;
wire [23:0] lru_rdata_m;
wire lru_scanin;
wire lru_scanout;
wire [10:6] tgc_dva_rd_addr_e;
wire dcc_lru_rvld_e;
wire [10:6] dcc_lru_wr_addr_w;
wire dcc_lru_wvld_w;
wire [3:0] dcc_lru_wen_w;
wire [5:0] dcc_lru_wdata_w;
wire [39:13] tlb_pgnum;
wire [47:0] sbd_st_predata_b_rep0;
wire tlb_tte_ie_b_rep01;
wire [3:0] tgc_cache_way_vld2_m;
wire [3:0] cache_way_hit_bot_b;
wire dcc_scanin;
wire dcc_scanout;
wire dcs_wmr_scanin;
wire dcs_wmr_scanout;
wire dcs_scanin;
wire dcs_scanout;
wire [63:0] sbd_st_data2_b_rep0;
wire [63:0] stb_ram_data_rep0;
wire lmd_scanin;
wire lmd_scanout;
wire [1:0] lmd_fill_way_m;
wire [10:4] lmd_fill_addr_m;
wire lmc_scanin;
wire lmc_scanout;
wire [60:40] dcc_ld_miss_ctl;
wire stb_cam_hit_rep0;
wire [39:3] lmd_fill_addr_e;
wire [2:0] cid_tid_unbuf;
wire sbc_pic_kill_store_p4_;
wire pic_scanin;
wire pic_scanout;
wire [4:0] cic_cpq_wptr;
wire cic_cpq_wr_en;
wire [4:0] cic_cpq_rptr;
wire cic_cpq_rd_en;
wire [151:0] cpq_din;
wire cpq_scanin;
wire cpq_scanout;
wire [151:0] cpq_dout;
wire [145:0] cid_cpq_wdata;
wire [145:0] cpq_rdata;
wire [5:0] cpq_unused;
wire cid_scanin;
wire cid_scanout;
wire cic_mbi_run;
wire red_scanin;
wire red_scanout;
wire cic_scanin;
wire cic_scanout;
wire cid_atomic_unbuf;
wire asc_scanin;
wire asc_scanout;
wire asd_scanin;
wire asd_scanout;
wire pid_scanin;
wire pid_scanout;
wire [63:0] stb_ram_data_corr;
wire [44:0] stb_cam_data_rep0;
wire sbs0_scanin;
wire sbs0_scanout;
wire tlb_tte_ie_b_rep00;
wire [7:0] sbc_cam_wvld_m;
wire [7:0] sbc_st_sel_p3;
wire [7:0] lsu_block_store_b;
wire [7:0] cic_st_ack;
wire [7:0] cic_st_dequeue;
wire [7:0] cic_rmo_dequeue;
wire [7:0] dcc_sync_inst_w;
wire [7:0] dcc_asi_rtn_vld;
wire [2:0] sbs0_stb_wptr_m;
wire [2:0] sbs0_stb_rptr;
wire [7:0] sbs0_state_vld;
wire [7:0] sbs0_state_ced;
wire [7:0] sbs_state_asi_rngf;
wire [7:0] sbs_pcx_pst_ie_p4;
wire [7:0] sbs_all_commited;
wire [7:0] sbs_stb_empty;
wire [7:0] sbs_stb_full;
wire [7:0] sbs_bst_req;
wire [7:0] sbc_bst_sel;
wire [7:0] sbc_st_addr_new;
wire [7:0] sbs_asi_indet_req;
wire [7:0] sbs_asi_indet_retire;
wire [7:0] sbs_rmo_st_p4;
wire [7:0] sbs_blk_st_p4;
wire [1:0] sbs0_st_type;
wire [7:0] sbs_asi_rq_vld;
wire [7:0] sbs_atm_rq_vld;
wire [7:0] sbs_pcx_rq_vld;
wire sbs1_scanin;
wire sbs1_scanout;
wire [2:0] sbs1_stb_wptr_m;
wire [2:0] sbs1_stb_rptr;
wire [7:0] sbs1_state_vld;
wire [7:0] sbs1_state_ced;
wire [1:0] sbs1_st_type;
wire sbs2_scanin;
wire sbs2_scanout;
wire [2:0] sbs2_stb_wptr_m;
wire [2:0] sbs2_stb_rptr;
wire [7:0] sbs2_state_vld;
wire [7:0] sbs2_state_ced;
wire [1:0] sbs2_st_type;
wire sbs3_scanin;
wire sbs3_scanout;
wire [2:0] sbs3_stb_wptr_m;
wire [2:0] sbs3_stb_rptr;
wire [7:0] sbs3_state_vld;
wire [7:0] sbs3_state_ced;
wire [1:0] sbs3_st_type;
wire sbs4_scanin;
wire sbs4_scanout;
wire [2:0] sbs4_stb_wptr_m;
wire [2:0] sbs4_stb_rptr;
wire [7:0] sbs4_state_vld;
wire [7:0] sbs4_state_ced;
wire [1:0] sbs4_st_type;
wire sbs5_scanin;
wire sbs5_scanout;
wire [2:0] sbs5_stb_wptr_m;
wire [2:0] sbs5_stb_rptr;
wire [7:0] sbs5_state_vld;
wire [7:0] sbs5_state_ced;
wire [1:0] sbs5_st_type;
wire sbs6_scanin;
wire sbs6_scanout;
wire [2:0] sbs6_stb_wptr_m;
wire [2:0] sbs6_stb_rptr;
wire [7:0] sbs6_state_vld;
wire [7:0] sbs6_state_ced;
wire [1:0] sbs6_st_type;
wire sbs7_scanin;
wire sbs7_scanout;
wire [2:0] sbs7_stb_wptr_m;
wire [2:0] sbs7_stb_rptr;
wire [7:0] sbs7_state_vld;
wire [7:0] sbs7_state_ced;
wire [1:0] sbs7_st_type;
wire sbc_scanin;
wire sbc_scanout;
wire spd_scanin;
wire spd_scanout;
wire sec_scanin;
wire sec_scanout;
wire [63:0] sec_corr_bit;
wire stb_cecc_err;
wire stb_uecc_err;
wire sed_scanin;
wire sed_scanout;
wire [7:0] bist_cmp_data_rep0;
wire sbc_mbi_run;
wire sbd_scanin;
wire sbd_scanout;
wire [63:0] exu_lsu_store_data_e_rep0;
wire [39:3] stb_st_addr_m;
wire [7:0] dcc_ldst_bmask;
wire dcc_stb_cam_vld_m;
wire [2:0] sbc_cam_tid;
wire [7:0] stb_cam_line_en_b;
wire [5:0] sbc_cam_rwptr;
wire sbc_cam_wptr_vld_m;
wire sbc_cam_rptr_vld;
wire dcc_stb_quad_ld_cam;
wire stb_cam_scanin;
wire stb_cam_scanout;
wire [44:0] stb_cam_data;
wire stb_ld_part_raw;
wire [2:0] stb_cam_hit_ptr;
wire stb_cam_hit;
wire stb_cam_mhit;
wire [5:0] sbc_ram_rptr;
wire sbc_ram_rptr_vld;
wire sbc_ram_wptr_vld_b;
wire [5:0] sbc_ram_wptr;
wire [83:0] stb_ram_din;
wire stb_ram_scanin;
wire stb_ram_scanout;
wire [83:0] stb_ram_dout;
wire [63:0] sbd_st_datab_b;
wire [13:0] sed_ecc_b;
wire [2:0] sbc_stb_ctl_data;
wire stb_cparity;
wire [63:0] stb_ram_rd_data;
wire [1:0] stb_ram_unused;
wire [13:0] stb_ram_rd_ecc;
wire [2:0] stb_ram_rd_ctl;
wire stb_ram_rd_cparity;
wire dta_clken;
wire dcc_dta_clken;
wire [29:0] dta_rdata_w0_m;
wire [29:0] dta_rdata_w1_m;
wire [29:0] dta_rdata_w2_m;
wire [29:0] dta_rdata_w3_m;
wire dta_scanin;
wire dta_scanout;
wire [10:4] dcc_dta_fill_addr_e;
wire dcc_dta_index1_sel_e;
wire [1:0] dcc_dta_fill_way_e;
wire dcc_dta_rvld_e;
wire dcc_dta_wvld_e;
wire dcc_dta_parity;
wire [15:0] dva_valid2_m;
wire [15:0] dva_valid_m;
wire dva_scanin;
wire dva_scanout;
wire dcc_dva_rvld_e;
wire [10:6] dcc_dva_wr_addr_e;
wire dcc_dva_wvld_e;
wire [15:0] dcc_dva_bit_wen_e;
wire [31:0] tgc_dva_din;
wire tgc_scanin;
wire tgc_scanout;
wire [47:0] lsu_va_m;
wire tgd_scanin;
wire tgd_scanout;
wire tte_ubit;
wire tld_ubit;
wire dcc_tlb_bypass;
wire tlc_wr_u_en;
wire dcc_tlb_rd_e;
wire [6:0] tld_rw_index;
wire tlc_rw_index_vld;
wire dcc_tlb_lookup;
wire tlc_demap;
wire tlc_demap_context;
wire tlc_demap_all;
wire tlc_demap_real;
wire [12:0] tgd_tag_c1;
wire [2:0] tld_tag_pid;
wire tld_tag_real;
wire tld_tag_valid;
wire [12:0] tgd_tag_c0;
wire [2:0] tld_tag_mask;
wire [37:0] tld_data;
wire tlc_dis_clr_ubit;
wire [28:0] dta_rdata_w0_rep;
wire [28:0] dta_rdata_w1_rep;
wire [28:0] dta_rdata_w2_rep;
wire [28:0] dta_rdata_w3_rep;
wire [3:0] tgc_cache_way_vld_m;
wire tlb_cache_hit_b;
wire tlb_scanin;
wire tlb_scanout;
wire tld_scanin;
wire tld_scanout;
wire [2:0] dcs_pid_e;
wire dcc_tlb_real;
wire tlc_scanin;
wire tlc_scanout;
wire tld_mbi_dtb_write_en;
wire tld_mbi_repl_write;
wire tld_mbi_dis_clr_ubit;
wire tld_mbi_dtb_demap_en;
wire [1:0] tld_mbi_demap_type;
wire ard_retl_ctl_1f;
wire ard_retl_vld_1f;
wire ard_retl_rd_1f;
wire [2:0] ard_retl_tid_1f;
wire ard_retl_ack_1f;
wire [1:0] ard_retl_exc_1f;
wire ard_retf_ctl_1f;
wire ard_retf_vld_1f;
wire ard_retf_rd_1f;
wire [2:0] ard_retf_tid_1f;
wire ard_retf_ack_1f;
wire [1:0] ard_retf_exc_1f;
wire arc_retl_vld_2f;
wire arc_retf_vld_2f;
wire arc_sel_fast;
wire [6:0] arc_pid_ctl_2f;
wire [63:0] ard_pid_data;
wire [7:1] dac_byte_one_extend;
wire [7:1] dac_byte_sel_data;
wire dac_swap7_byte0_l;
wire dac_swap7_byte3_l;
wire dac_swap7_byte4_l;
wire dac_swap7_byte7_l;
wire dac_swap6_byte1_l;
wire dac_swap6_byte2_l;
wire dac_swap6_byte5_l;
wire dac_swap6_byte6_l;
wire dac_swap5_byte1_l;
wire dac_swap5_byte2_l;
wire dac_swap5_byte5_l;
wire dac_swap5_byte6_l;
wire dac_swap4_byte0_l;
wire dac_swap4_byte3_l;
wire dac_swap4_byte4_l;
wire dac_swap4_byte7_l;
wire dac_swap3_byte0_r;
wire dac_swap3_byte3_r;
wire dac_swap3_byte4_r;
wire dac_swap3_byte7_r;
wire dac_swap2_byte1_r;
wire dac_swap2_byte2_r;
wire dac_swap2_byte5_r;
wire dac_swap2_byte6_r;
wire dac_swap1_byte0_r;
wire dac_swap1_byte1_r;
wire dac_swap1_byte2_r;
wire dac_swap1_byte3_r;
wire dac_swap1_byte4_r;
wire dac_swap1_byte5_r;
wire dac_swap1_byte6_r;
wire dac_swap1_byte7_r;
wire dac_swap0_byte0_r;
wire dac_swap0_byte1_r;
wire dac_swap0_byte2_r;
wire dac_swap0_byte3_r;
wire dac_swap0_byte4_r;
wire dac_swap0_byte5_r;
wire dac_swap0_byte6_r;
wire dac_swap0_byte7_r;
wire [1:0] dcd_dca_data_compare;
wire dcs_memref_m;
wire [47:0] lsu_mmu_va_m;
wire dcc_ld_inst_vld_m;
wire dcc_l2fill_vld_m;
wire dcc_lendian_pre_m;
wire dcc_bendian_byp_m;
wire [2:0] dcc_baddr_m;
wire [1:0] dcc_ld_sz_m;
wire dcc_signed_m;
wire lmc_asi_bypass_m;
wire lmc_byp_vld_m;
wire [7:0] lmd_misc_msb_m;
wire [7:0] bist_wdata_1;
wire lsu_lsu_pmen_;
wire [127:0] lmd_fill_data_e;
wire [7:0] dcc_parity_invert;
wire tlc_use_primary_context_c0;
wire tlc_use_secondary_context_c0;
wire [2:0] tld_tid;
wire tlc_wr_or_demap;
wire tld_va_m_eq_zero;
wire [1:0] lmd_sz_m;
wire lmd_fpld_m;
wire lmd_sxt_fsr_m;
wire [4:0] lmd_rd_m;
wire lmd_fpodd32b_m;
wire lmd_fp32b_m;
wire lmd_bendian_m;
wire [2:0] lmd_ld_addr_m;
wire [1:0] lmd_fill_way_e;
wire lmd_wrtag_parity_e;
wire [2:0] lmc_cpq_tid_m;
wire [7:0] lmc_thrd_byp_sel_e;
wire [2:0] lmc_byp_tid_m;
wire [7:0] lmc_pref_issued;
wire lmc_bld_annul;
wire lmc_bld_last_e;
wire lmc_bld_miss_e;
wire lmc_full_raw_w;
wire lmc_ld_stall;
wire lmc_l2_err_noup;
wire lmc_l2_uerr;
wire tlb_tte_cp_b;
wire tlb_tte_wbit_b;
wire tlb_tte_ebit_b;
wire tlb_tte_pbit_b;
wire tlb_tte_nfo_b;
wire tlb_cam_hit;
wire tlb_cam_mhit;
wire [2:0] tlb_pgsize;
wire tlb_context0_hit;
wire tlb_tag_parity;
wire tlb_tte_data_parity;
wire [7:0] dcs_asi_d;
wire [7:0] dcs_wpt_mask_m;
wire [1:0] dcs_wpt_enable_m;
wire [1:0] dcs_wpt_mode_m;
wire [7:0] dcs_dc_enable;
wire dcs_dmmu_enable_d;
wire [20:0] lsu_va_b;
wire cic_l2fill_vld_e;
wire cic_cpq_ld_sel;
wire cic_invalidate_e;
wire cic_xinval_e;
wire cic_st_update_e;
wire cic_rtn_cmplt;
wire cic_oddrd_e;
wire [15:0] cic_inv_wen_e;
wire cic_cpq_stall;
wire [2:0] cid_tid;
wire [1:0] cid_xway;
wire [10:3] cid_st_addr;
wire [1:0] cid_st_way;
wire [7:0] cid_st_bmask;
wire [10:6] cid_inv_index;
wire cid_ncache;
wire cid_atomic;
wire cid_l2miss;
wire sbc_bst_in_prog_m;
wire [2:0] sbc_tid_m;
wire [7:0] lsu_block_store_alloc;
wire tgd_w0_parity_b;
wire tgd_w1_parity_b;
wire tgd_w2_parity_b;
wire tgd_w3_parity_b;
wire tgd_va_wp_47_16;
wire tgd_va_wp_15_3;
wire tgd_pa_wp_39_16;
wire tgd_pa_wp_15_3;
wire tgd_prty_256m_b;
wire tgd_prty_4m_b;
wire tgd_prty_64k_b;
wire tgd_prty_8k_b;
wire tgd_prty_ctxt0_b;
wire tgd_prty_ctxt1_b;
wire [3:0] tgc_verr_b;
wire [7:0] bist_cmp_data;
wire [1:0] bist_cmpsel_1;
wire [8:5] bist_addr_1;
wire bist_srm_rd_1;
wire bist_scm_rd_1;
wire dcc_exception_flush_b;
wire dcc_asi_load_m;
wire dcc_asi_load_b;
wire dcc_asi_store_b;
wire dcc_asi_iomap_m;
wire dcc_asi_iomap_b;
wire dcc_asi_rngf_b;
wire dcc_asi_indet_b;
wire dcc_binit_st_b;
wire dcc_dva_din_e;
wire dcc_dva_din2_e;
wire dcc_cache_diag_wr_m;
wire dcc_cache_diag_wr_b;
wire dcc_bmask_parity_b;
wire dcc_ld_miss_b;
wire dcc_early_ld_b;
wire [1:0] dcc_ctxt_tid0_d;
wire [1:0] dcc_ctxt_tid1_d;
wire dcc_ctxt_tg_d;
wire [2:0] dcc_tid_e;
wire [2:0] dcc_tid_m;
wire [2:0] dcc_tid_b;
wire [7:0] dcc_asi_m;
wire dcc_ld_inst_unqual_e;
wire dcc_pref_inst_m;
wire dcc_std_inst_m;
wire dcc_ldstub_inst_m;
wire dcc_atomic_b;
wire dcc_casa_inst_b;
wire dcc_pst_asi_b;
wire dcc_tte_vld_m;
wire [1:0] dcc_ldst_sz_m;
wire dcc_fp32b_sel_m;
wire dcc_blk_inst_m;
wire dcc_blk_inst_b;
wire dcc_ldbl_b;
wire dcc_ncache_b;
wire [1:0] dcc_st_rq_type_w;
wire dcc_sync_pipe_w;
wire dcc_priv_b;
wire dcc_hpriv_b;
wire dcc_pctxt_sel_e;
wire dcc_sctxt_sel_e;
wire dcc_ld_miss_ldd;
wire [7:0] dcc_asi_reload_sel;
wire [7:0] dcc_wr_wtchpt;
wire [7:0] dcc_wr_lsu_ctl_reg;
wire dcc_wr_pwr_mgmt;
wire dcc_ceter_wr_w;
wire dcc_p0ctxt_rd_m;
wire dcc_p1ctxt_rd_m;
wire dcc_s0ctxt_rd_m;
wire dcc_s1ctxt_rd_m;
wire dcc_pid_rd_m;
wire dcc_wtchpt_sel_m;
wire dcc_demap_asi_m;
wire dcc_wtchpt_rd_b;
wire dcc_rd_lsu_ctl_reg_b;
wire dcc_rd_diag_reg_b;
wire dcc_rd_diag_dca_b;
wire dcc_rd_core_id_b;
wire dcc_rd_intr_id_b;
wire dcc_rd_dt_diag_m;
wire dcc_rd_dt_diag_b;
wire dcc_stb_diag_rd_m;
wire dcc_rd_error_inj_b;
wire dcc_rd_pwr_mgmt_b;
wire dcc_wr_error_inj_m;
wire dcc_wr_error_inj_w;
wire dcc_tlb_data_read_b;
wire dcc_tlb_tag0_read_b;
wire dcc_tlb_tag1_read_b;
wire dcc_tlb_rw_index_e;
wire dcc_rd_rhs_asi_b;
wire dcc_lsu_asi_rd_b;
wire dcc_lsu_asi_sel_w;
wire dcc_stb_diag_sel_w3;
wire dcc_stb_data_rd_w3;
wire dcc_stb_ecc_rd_w3;
wire dcc_stb_ctl_rd_w3;
wire dcc_stb_addr_sel_w3;
wire dcc_stb_ptr_rd_w3;
wire dcc_direct_map;
wire dcc_dcs_memref_e;
wire dcc_perror_b;
wire [1:0] dcc_perr_enc_b;
wire [12:3] lsu_va_w;
wire dcc_sbd_e_clken;
wire dcc_sbd_m_clken;
wire dcc_ldst_m_clken;
wire dcc_asi_rtn_excp;
wire dcc_asi_rtn_rd;
wire [7:0] asc_wr_p0ctxt;
wire [7:0] asc_wr_p1ctxt;
wire [7:0] asc_wr_s0ctxt;
wire [7:0] asc_wr_s1ctxt;
wire [7:0] asc_wr_pid;
wire [7:0] asc_wrasi;
wire [63:0] tgd_ldxa_asi_data_b;
wire [12:0] dcs_context0_e;
wire [12:0] dcs_context1_e;
wire [63:0] dcs_ldxa_asi_data_w;
wire [47:3] dcs_watchpoint_m;
wire [7:0] lmc_lmq_enable_b;
wire [7:0] lmc_lmq_bypass_en;
wire [7:0] lmc_pcx_sel_p4;
wire [7:0] lmc_byp_sel_e;
wire [7:0] lmc_thrd_byp_sel_m;
wire [4:0] lmc_lmq0_byp_sel;
wire [4:0] lmc_lmq1_byp_sel;
wire [4:0] lmc_lmq2_byp_sel;
wire [4:0] lmc_lmq3_byp_sel;
wire [4:0] lmc_lmq4_byp_sel;
wire [4:0] lmc_lmq5_byp_sel;
wire [4:0] lmc_lmq6_byp_sel;
wire [4:0] lmc_lmq7_byp_sel;
wire [1:0] lmc_bld_addr54;
wire lmc_bld_req;
wire lmc_bld_req_;
wire lmc_lmd_ncache_b;
wire [7:0] lmc_rd_update;
wire [7:0] lmc_ld_unfilled;
wire lmc_bist_or_diag_e;
wire lmc_byp_data_hi;
wire lmc_byp_data_enable;
wire [39:13] stb_st_addr_b;
wire [39:3] sbd_st_addr_b;
wire [63:0] stb_ldxa_asi_data_w;
wire [127:0] cid_fill_data_e;
wire cid_st_data_sel;
wire cic_diag_data_sel_e;
wire lmc_mbi_run;
wire lmd_addrb2;
wire [7:0] lmd_asi_ld;
wire [7:0] lmd_asi_indet;
wire [7:0] lmd_sec_cmp_b;
wire lmd_fill_sz_b0_e;
wire [2:1] lmd_rd_e;
wire [63:0] lmd_bypass_data_m;
wire [63:0] lmd_fill_or_byp_data_m;
wire [2:0] lmd_pcx_rqtyp;
wire lmd_pcx_nc;
wire lmd_pcx_pref;
wire [1:0] lmd_pcx_rway;
wire [39:0] lmd_pcx_addr;
wire lmd_asi_rngf;
wire [1:0] lmd_asi_type;
wire [7:0] lmd_asi_asi;
wire lmd_sz_b1;
wire lmd_sz_b0;
wire lmd_ldbl;
wire [1:0] lmd_dc_err_e;
wire pic_casa_squash_req;
wire pic_early_ld_b_sel_p3;
wire pic_no_load_p3;
wire pic_asi_busy;
wire cic_cpq_ld_rdy;
wire cic_cpq_ld_rdy_;
wire cic_div_stall_d;
wire [7:0] cic_xinval;
wire cic_set_inval;
wire cic_ext_interrupt;
wire [1:0] cid_err;
wire cid_dcsoc_err_e;
wire [7:0] sbc_st_atom_p3;
wire [7:0] sbc_rawp_rst;
wire [2:0] sbc_st_sel_tid_p4;
wire sbc_force_inv;
wire lmc_pcx_rq_vld;
wire lmc_asi_rq_vld;
wire lmc_ld_rq_p3;
wire lmc_ld_vld_p4;
wire lmc_ld_no_req_p4;
wire lmc_ld_inv_p4;
wire [2:0] lmc_ld_tid;
wire [7:0] lmc_ldd_vld;
wire [4:0] lmc_ld_sz;
wire lmc_ld_inst_w;
wire lmc_asi_indet_retire;
wire sbc_asi_rq_p3;
wire sbc_pcx_rq_p3;
wire sbc_st_atomic_p2;
wire sbc_st_rq_p2;
wire sbc_indet_block_p3;
wire asc_pid_ack;
wire lsu_ring_ctl;
wire pic_ld_pcx_sel_p4;
wire pic_st_pcx_sel_p3;
wire pic_st_pcx_sel_p4;
wire pic_st_asi_sel_p3;
wire pic_st_asi_p4;
wire pic_ld_asi_p4;
wire pic_st_sel_p3;
wire pic_asi_sel_p4;
wire pic_asi_req;
wire cic_byp_sel;
wire cic_d1_sel;
wire cic_cpq_sel;
wire cic_fifo_sel;
wire cic_fifo_clken;
wire [4:0] cid_pkt_type;
wire [2:0] cid_cpuid;
wire cid_xinval;
wire cid_pref;
wire [15:0] cid_st_vector;
wire [17:0] cid_inv_vec;
wire cid_rmo_ack;
wire cid_set_inval;
wire cid_set_icinval;
wire [4:0] cid_d1_rtntyp;
wire [2:0] cid_d1_tid;
wire [2:0] cid_d1_cpuid;
wire cid_d1_wv;
wire cid_d1_rmo;
wire cid_d1_pref;
wire [1:0] cid_d1_inval;
wire cid_cpq_cmp_1;
wire cid_cpq_cmp_2;
wire cid_cpq_cmp_3;
wire bist_cmpsel_2;
wire asd_p2a_vld;
wire asd_p2a_fast;
wire [63:56] asd_ring_ctl;
wire [7:0] asd_ring_asi;
wire [8:3] asd_ring_addr;
wire sbc_pid_kill_store_p4_;
wire asc_ring_ctl;
wire asc_ring_data;
wire asc_ring_local;
wire asc_ring_fast;
wire [127:0] pid_asi_pkt;
wire sbc_st_pcx_nc;
wire sbc_st_asi_fs;
wire [7:0] sbc_pcx_bmask;
wire [2:0] sbc_pcx_addr;
wire sbc_pcx_rmo_st;
wire sbc_pcx_blk_st;
wire [2:0] sbc_st_type_p4;
wire sbc_rmo_st_b;
wire sbc_bst_in_prog_b;
wire sbc_fgu_ecc_b;
wire sbc_bst_rd_err;
wire sbc_sbs_kill_store_p4_;
wire sbc_tte_vld_b;
wire sbc_blk_inst_b;
wire spd_st_line_match;
wire [2:0] stb_ram_ctl;
wire stb_cam_perr;
wire sed_bist_cmp_0;
wire sed_bist_cmp_1;
wire sed_bist_cmp_2;
wire sed_bist_cmp_3;
wire [7:0] sbc_thread_b;
wire sbc_st_int_sel_m;
wire sbc_std_le_m;
wire sbc_st_le_if_ie_m;
wire sbc_st_le_not_ie_m;
wire [1:0] sbc_st_sz_m;
wire sbc_inv_addr_prty;
wire [6:0] sbc_inv_ecc;
wire sbc_twocycle_inst_w;
wire [7:0] sbc_cam_line_en_m;
wire [2:0] sbc_diag_wptr_w3;
wire sbc_spd_clken;
wire sbc_ramout_clken;
wire sbc_tidb_eq_tidw;
wire sbc_load_bst_addr;
wire [2:0] sbc_bst_offset;
wire stb_ram_cparity;
wire stb_cparity_calc;
wire [1:0] sed_c1_lo;
wire [1:0] sed_c1_hi;
wire [1:0] sed_c2_lo;
wire [1:0] sed_c2_hi;
wire [1:0] sed_c4_lo;
wire [1:0] sed_c4_hi;
wire [1:0] sed_c8_lo;
wire [1:0] sed_c8_hi;
wire [1:0] sed_c16_lo;
wire [1:0] sed_c16_hi;
wire [2:0] sed_cf_lo;
wire [2:0] sed_cf_hi;
wire sed_c32_hi;
wire sed_c32_lo;
wire sec_st_sz_dw_std_le_b;
wire sec_st_sz_dw_le_not_ie_b;
wire sec_st_sz_dw_be_not_ie_b;
wire sec_st_sz_word_le_not_ie_b;
wire sec_st_sz_word_be_not_ie_b;
wire sec_st_sz_hw_le_not_ie_b;
wire sec_st_sz_hw_be_not_ie_b;
wire sec_st_sz_dw_le_if_ie_b;
wire sec_st_sz_dw_be_if_ie_b;
wire sec_st_sz_word_le_if_ie_b;
wire sec_st_sz_word_be_if_ie_b;
wire sec_st_sz_hw_le_if_ie_b;
wire sec_st_sz_hw_be_if_ie_b;
wire sec_st_sz_byte_b;
wire [63:0] sbd_st_data_b;
wire [63:0] stb_ram_data;
wire [39:13] tlb_pgnum_crit;
wire tlb_tte_ie_b;
wire [63:0] sbd_st_data2_b;
wire [47:0] sbd_st_predata_b;
wire tgd_bist_compare;
wire [1:0] tgc_way_sel_m;
wire bist_dta_cmp_en;
wire [37:0] tlb_tte_data;
wire [65:0] tlb_tte_tag;
wire tlb_tte_u_bit;
wire tld_prty_256m;
wire tld_prty_4m;
wire tld_prty_64k;
wire tld_prty_8k;
wire tld_prty_ctxt0;
wire tld_prty_ctxt1;
wire [12:0] tld_tag_c0;
wire [12:0] tld_tag_c1;
wire tlc_sel_tte_tag;
wire tlc_sel_demap_tag_c0;
wire tlc_sel_demap_tag_c1;
wire tlc_sel_write_tag;
wire tlc_sel_dm_tag;
wire tlc_sel_wr_dm_bist;
wire tlc_write_next;
wire tlc_tte0_clken;
wire tlc_tte1_clken;
wire tlc_tag_error_inj;
wire tlc_data_error_inj;
wire tlc_mbi_run;
wire [2:0] tld_demap_control0;
wire [3:0] tld_demap_control1;
wire tld_use_secondary_context0;
wire tld_index_valid;


input		l2clk;
input 		scan_in;
input 		wmr_scan_in;
input 		tcu_pce_ov;		// scan signals
input 		spc_aclk_wmr;
input 		spc_aclk;
input 		spc_bclk;
input		tcu_scan_en;
input		tcu_array_wr_inhibit;
input		tcu_se_scancollar_in;
input		tcu_se_scancollar_out;
input		lb_scan_en_wmr;
output		scan_out;
output		wmr_scan_out;

input	[2:0]	const_cpuid;		// hardwired CPU ID

////////////////////
// IFU interface

input		ifu_lsu_if_vld;		// indicates ifetch to L2 (used for xinval)
input	[2:0]	ifu_lsu_if_tid;		// indicates ifetch tid (used for xinval)
input	[10:5]	ifu_lsu_if_addr;	// index of ifetch request

output	[12:0]	lsu_ifu_ctxt_data;	// Value to write into context register
output	[2:0]	lsu_ifu_tid_w;		// TID for context write
output		lsu_ifu_wr_p0ctxt;	// Update primary context0
output		lsu_ifu_wr_p1ctxt;	// Update primary context1
output		lsu_ifu_wr_pid;		// Update partition ID
output	[7:0]	lsu_immu_enable;	// ASI_LSU_CTL_REG.IM
output	[7:0]	lsu_ic_enable;		// ASI_LSU_CTL_REG.IC
output	[10:5]	lsu_ifu_ld_index;	// Index of load being returned (for xinval)
output		lsu_ifu_direct_map;	// ASI_LSU_DIAG_REG.IASSOCDIS
output	[7:0]	lsu_ifu_no_miss;	// IFU must wait to handle a miss until xinval is done

// Flopped versions to IFU
output  [127:0] lsu_cpx_data;
output  [17:0]  lsu_cpx_cpkt;
output          lsu_cpx_valid;

////////////////////
// DEC interface

// 0in assert_leader -leader dec_ld_inst_d -follower dec_ld_inst_e -min 1 -max 1

input		dec_lsu_tg_d;		// Thread group of instruction in D
input		dec_ld_inst_d;		// Load instruction in D
input		dec_ld_inst_e;		// Load instruction in E
input		dec_st_inst_e;		// Store instruction in E
input		dec_fpldst_inst_e;	// Float ldst instruction in E
input		dec_fsr_ldst_e;		// LDFSR/STFSR instruction in E
input		dec_ldst_dbl_e;		// LDD/STD instruction in E
input		dec_pref_inst_e;	// Prefetch instruction in E
input		dec_flush_inst_e;	// Flush instruction in E
input		dec_memstbar_inst_e;	// Membar/stbar instruction in E
input		dec_sr_inst_e;		// Rd/wr State register instruction in E
input		dec_pr_inst_e;		// Rd/wr priv. register instruction in E
input		dec_hpr_inst_e;		// Rd/wr hyper priv. register instruction in E
input		dec_casa_inst_e;	// CASA instruction in E
input		dec_ldstub_inst_e;	// LDSTUB instruction in E
input		dec_swap_inst_e;	// SWAP instruction in E
input		dec_altspace_d;		// Memory access to alternate space
input		dec_sign_ext_e;		// Instruction requiring sign extension of data (op3[3:2]==10)
input	[1:0]	dec_ldst_sz_e;		// Size bits for the instruction in E
input	[4:0]	dec_lsu_rd_e;		// Dest. register for load data
input	[4:0]	dec_sraddr_e;		// State register address for instruction in E
input		dec_imm_asi_vld_d;	// Instruction in D uses immediate ASI 
input	[7:0]	dec_imm_asi_d;		// Value of the immediate ASI
input	[4:3]	dec_frf_r2_addr_e;	// Register offset for block store burst
input		dec_flush_lm;		// Flush the instruction in M
input		dec_flush_lb;		// Flush the instruction in B
input	[1:0]	dec_lsu_tid0_d;		// TID for TG0
input	[1:0]	dec_lsu_tid1_d;		// TID for TG1

output		lsu_block_store_stall;	// Initiate block store burst sequence
output	[4:3]	lsu_block_store_rd;	// Value of Rd for block store burst
output	[2:0]	lsu_block_store_tid;	// Thread ID of block store burst
output		lsu_cpq_stall;		// Halt decode of load instructions so cpq can drain


////////////////////
// PKU interface

output	[7:0]	lsu_sync;		// Switch out thread
output	[7:0]	lsu_complete;		// Resume thread
output	[7:0]	lsu_stb_alloc;		// Entry committed in STB
output	[7:0]	lsu_stb_dealloc;	// Entry dequeued from STB
output	[7:0]	lsu_block_store_kill;	// Reset spec and committed counters to zero

////////////////////
// TLU interface

input		tlu_flush_lsu_b;	// Flush the instruction in B
input	[7:0]	tlu_pstate_cle;		// PSTATE.CLE bit for the 8 threads
input	[7:0]	tlu_asi_0;		// Value for ASI reload
input	[7:0]	tlu_asi_1;		// Value for ASI reload
input	[1:0]	tlu_asi_0_tid;		// Thread for ASI reload
input	[1:0]	tlu_asi_1_tid;		// Thread for ASI reload
input		tlu_asi_0_valid;	// Enable ASI reload
input		tlu_asi_1_valid;	// Enable ASI reload
input	[7:0]	tlu_lsu_hpstate_hpriv;	// HPSTATE.HPRIV setting
input	[7:0]	tlu_lsu_pstate_priv;	// PSTATE.PRIV setting
input	[7:0]	tlu_tl_gt_0;		// Indicates TL>0
input	[7:0]	tlu_lsu_clear_ctl_reg_;	// Clear ASI_LSU_CONTROL_REG
input	[54:0]	tlu_tte;		// (Really just a copy of the fast ring)

input		tlu_cerer_dttp;
input		tlu_cerer_dttm;
input		tlu_cerer_dtdp;
input		tlu_cerer_dcvp;
input		tlu_cerer_dctp;
input		tlu_cerer_dctm;
input		tlu_cerer_dcdp;
input		tlu_cerer_dcl2c;
input		tlu_cerer_dcl2u;
input		tlu_cerer_dcl2nd;
input		tlu_cerer_sbdlc;
input		tlu_cerer_sbdlu;
input		tlu_cerer_sbapp;
input		tlu_cerer_sbdiou;
input		tlu_cerer_sbdpc;
input		tlu_cerer_sbdpu;
input		tlu_cerer_l2c_socc;
input		tlu_cerer_l2u_socu;


output	[7:0]	lsu_stb_empty;		// STB is empty
output	[7:0]	lsu_trap_flush;		// Initiate Trap flush 
output		lsu_tlb_bypass_b;	// Inst in B bypassed TLB
output		lsu_tlb_real_b;		// Inst in B did RA->PA translation
output		lsu_align_b;		// mem_address_not_aligned exception
output		lsu_lddf_align_b;	// LDDF_mem_address_not_aligned
output		lsu_stdf_align_b;	// STDF_mem_address_not_aligned
output		lsu_dae_invalid_asi_b;
output		lsu_dae_nc_page_b;
output		lsu_dae_nfo_page_b;
output		lsu_dae_priv_viol_b;
output		lsu_dae_so_page;
output		lsu_priv_action_b;	// privileged_action
output		lsu_va_watchpoint_b;	// VA_watchpoint
output		lsu_pa_watchpoint_b;	// PA_watchpoint
output 		lsu_tlb_miss_b_;	// TLB access missed (TLU figures trap type)
output 		lsu_illegal_inst_b;	// illegal_instruction
output		lsu_daccess_prot_b;	// data_access_protection
output		lsu_perfmon_trap_b;	// performance monitor trap
output		lsu_perfmon_trap_g;	// performance monitor trap
output		lsu_priv_action_g;	// privileged_opcode for long latency op
output	[2:0]	lsu_tid_g;		// TID for late priv_action exception
output	[1:0]	lsu_tlu_dsfsr_ct_b;

output		lsu_sync_inst_b;	// Inst in B is synchronizing
output		lsu_tlu_twocycle_m;
output	[31:0]	lsu_asi_error_inject;

// D$ parity error reporting
output		lsu_dcmh_err_g;		// D$ valid parity error
output		lsu_dcvp_err_g;		// D$ valid parity error
output		lsu_dctp_err_g;		// D$ tag parity error
output		lsu_dcdp_err_g;		// D$ data parity error

// Reporting L2 ecc errors for loads
output		lsu_dcl2c_err_g;	// L2 correctable error
output		lsu_dcl2u_err_g;	// L2 uncorrectable error
output		lsu_dcl2nd_err_g;	// L2 NotData error
output		lsu_dcsoc_err_g;	// Indicates error was from SOC (vs. L2)

// 0in bits_on -var {lsu_dcmh_err_g,lsu_dcvp_err_g,lsu_dctp_err_g,lsu_dcdp_err_g,lsu_dcl2c_err_g,lsu_dcl2u_err_g,lsu_dcl2nd_err_g} -max 1 -message "multiple DC errors reported"

// This tid is for D$ and L2 errors - only one can occur at a time.
output	[2:0]	lsu_dcerr_tid_g;	// TID of D$ error
output	[8:0]	lsu_dcerr_sfar_g;	// Contains the way and index of the error

// STB errors
output		lsu_sbdlc_err_g;	// STB RAW error (CE)
output		lsu_sbdlu_err_g;	// STB RAW error (UE)
output		lsu_sbdpc_err_g;	// STB read for issue data ECC error (CE)
output		lsu_sbdpu_err_g;	// STB read for issue data ECC error (UE)
output		lsu_sbapp_err_g;	// STB read for issue address parity error
output		lsu_sbdiou_err_g;	// STB read for issue UE error on IO or ASI
output	[2:0]	lsu_stberr_tid_g;	// TID of STB error
output	[2:0]	lsu_stberr_index_g;	// Index of STB error
output	[1:0]	lsu_stberr_priv_g;	// Encoded priv level of store (00=user, 01=priv, 10=hpriv, 11=error)
output		lsu_stb_flush_g;	// A store is being flushed from the STB

// TLB errors
output		lsu_dttp_err_b;		// DTLB tag parity error
output		lsu_dtdp_err_b;		// DTLB data parity error
output		lsu_dtmh_err_b;		// DTLB data parity error

// 0in assert_leader -leader lsu_complete[0] -follower (lsu_perfmon_trap_g & (lsu_dcerr_tid_g[2:0] == 3'd0)) -max 1 -min 1
// 0in assert_leader -leader lsu_complete[1] -follower (lsu_perfmon_trap_g & (lsu_dcerr_tid_g[2:0] == 3'd1)) -max 1 -min 1
// 0in assert_leader -leader lsu_complete[2] -follower (lsu_perfmon_trap_g & (lsu_dcerr_tid_g[2:0] == 3'd2)) -max 1 -min 1
// 0in assert_leader -leader lsu_complete[3] -follower (lsu_perfmon_trap_g & (lsu_dcerr_tid_g[2:0] == 3'd3)) -max 1 -min 1
// 0in assert_leader -leader lsu_complete[4] -follower (lsu_perfmon_trap_g & (lsu_dcerr_tid_g[2:0] == 3'd4)) -max 1 -min 1
// 0in assert_leader -leader lsu_complete[5] -follower (lsu_perfmon_trap_g & (lsu_dcerr_tid_g[2:0] == 3'd5)) -max 1 -min 1
// 0in assert_leader -leader lsu_complete[6] -follower (lsu_perfmon_trap_g & (lsu_dcerr_tid_g[2:0] == 3'd6)) -max 1 -min 1
// 0in assert_leader -leader lsu_complete[7] -follower (lsu_perfmon_trap_g & (lsu_dcerr_tid_g[2:0] == 3'd7)) -max 1 -min 1

output		lsu_ext_interrupt;
output	[1:0]	lsu_ext_int_type;
output	[5:0]	lsu_ext_int_vec;
output	[2:0]	lsu_ext_int_tid;

////////////////////
// MMU interface
input 		mmu_dtlb_reload;	// DTLB reload operation
output	[47:0]	lsu_mmu_va_b;		// virtual address in B
output	[12:0]	lsu_context_b;		// context of access in B

////////////////////
// EXU interface

input	[7:0]	exu_lsu_rs2_e;		// RS2 data for partial stores
input	[47:0]	exu_lsu_address_e;	// Calculated EA
input	[63:0]	exu_lsu_store_data_e;	// Store data from IRF
input	[1:0]	exu_lsu_va_error_m;	// VA error requiring a flush
input	[1:0]	exu_ecc_m;		// ECC error requiring a flush

output	[63:0]	lsu_exu_ld_data_b;	// IRF load return data
output		lsu_exu_ld_vld_w;	// IRF load return is valid
output		lsu_exu_ld_b;		// IRF load return is coming (but may be flushed)
output	[4:0]	lsu_exu_rd_m;		// Address of destination register
output	[2:0]	lsu_exu_tid_m;		// Thread ID of load return

output	[47:13]	lsu_exu_address_e;
output		lsu_sel_lsu_addr_e;

////////////////////
// FGU interface

input	[63:0]	fgu_lsu_fst_data_fx1;	// Store data from FRF
input		fgu_fst_ecc_error_fx2;	// FRF read encountered ECC error
input		fgu_fdiv_stall;		// Divide completing soon (see lsu_cic_ctl for timing)

output	[63:0]	lsu_fgu_fld_data_b;	// FRF load return data
output		lsu_fgu_fld_vld_w;	// FRF load return is valid
output		lsu_fgu_fld_b;		// FRF load return is coming (but may be flushed)
output	[4:0]	lsu_fgu_fld_addr_b;	// Register address for load data
output	[2:0]	lsu_fgu_fld_tid_b;	// FRF load data thread ID
output		lsu_fgu_fld_32b_b;	// FRF load return is 32 bits
output		lsu_fgu_fld_odd32b_b;	// FRF load return to odd 32b dest
output		lsu_fgu_fsr_load_b;	// FP load dest is %fsr, not FRF
output		lsu_fgu_exception_w;	// Signal exceptions to FGU (for STFSR)
output		lsu_block_store_m;	// Block store data transfer in "M" stage
output		lsu_frf_read_pending;

////////////////////
// PMU interface
input		pmu_lsu_dcmiss_trap_m;	// Enable D$ miss perfmon trap
input		pmu_lsu_dtmiss_trap_m;	// Enable DTLB miss perfmon trap
input	[7:0]	pmu_lsu_l2dmiss_trap_m;	// Enable L2 load miss permon trap
output	[2:0]	lsu_pmu_mem_type_b;	// Perfmon event {5:3 - tid ; 2:0 - {l2 d-miss, dt_miss, d-cache miss}}

///////////////////////////////////
// External gasket interface
input		l15_lsu_grant;		// One packet released to PCX

output		lsu_l15_lock;		// Request is atomic
output		lsu_l15_valid;		// LSU requests PCX access
output	[39:0]	lsu_l15_addr;		// PCX request address
output	[25:0]	lsu_l15_cpkt;		// PCX request control
output	[63:0]	lsu_l15_data;		// PCX request data

input	[145:0]	cpx_spc_data_cx;

///////////////////////////////////
// External ASI interfaces
input	[64:0]	tlu_rngf_cdbus; 	// 65 bit control/data bus from the fast ring
input		tlu_rngf_cdbus_error; 	// error signaled on same cycle as data 
input	[64:0]	rngl_lsu_cdbus; 	// 65 bit control/data bus from the local ring

//output	[62:0]	lsu_ring_cdbus; 	// 65 bit control/data bus to the local ring
//output		lsu_rngf_cdbus_b63; 	// 65 bit control/data bus to the fast ring
//output		lsu_rngl_cdbus_b63; 	// 65 bit control/data bus to the fast ring
//output		lsu_ring_ctl;
output	[64:0]	lsu_rngf_cdbus; 	// 65 bit control/data bus to the local ring
output	[64:0]	lsu_rngl_cdbus; 	// 65 bit control/data bus to the local ring

///////////////////////////////////
// BIST interface
input		lbist_run;
input	[8:0]	mbi_addr;
input		mbi_run;
input	[7:0]	mbi_wdata;
input		mbi_ptag_data;
input	[1:0]	mbi_cmpsel;

input		mbi_dca_read_en;
input		mbi_dca_write_en;
output		lsu_mbi_dca_fail;

input		mbi_dta_read_en;
input		mbi_dta_write_en;
output		lsu_mbi_dta_fail;

input		mbi_dva_read_en;
input		mbi_dva_write_en;
output		lsu_mbi_dva_fail;

input		mbi_lru_read_en;
input		mbi_lru_write_en;
output		lsu_mbi_lru_fail;

input		mbi_dtb_read_en;
input		mbi_dtb_write_en;
output		lsu_mbi_dtb_fail;

input		mbi_stb_cam_read_en;
input		mbi_stb_cam_write_en;
output		lsu_mbi_stb_cam_fail;

input		mbi_stb_ram_read_en;
input		mbi_stb_ram_write_en;
output		lsu_mbi_stb_ram_fail;

input		mbi_cpq_read_en;
input		mbi_cpq_write_en;
output		lsu_mbi_cpq_fail;

input		mbi_cambist_run;
input		mbi_cambist_shift;
input		mbi_dis_clr_ubit;
input		mbi_init_to_zero;
input		mbi_dtb_cam_en_pre;
input		mbi_repl_write;
input		mbi_dtb_demap_en;
input	[1:0]	mbi_demap_type;

output		lsu_mbi_tlb_data_cmp;
output		lsu_mbi_tlb_cam_hit;
output		lsu_mbi_tlb_cam_mhit;
output		lsu_mbi_tlb_ctxt0_hit;
output		lsu_mbi_tlb_valid;
output		lsu_mbi_tlb_used;

input		mbi_scm_cam_en_pre;

output		lsu_mbi_scm_hit;
output		lsu_mbi_scm_mhit;
output	[2:0]	lsu_mbi_scm_hit_ptr;
output		lsu_mbi_scm_praw;

input		dmo_coresel;
input		dmo_dcmuxctl;

output	[3:0]	dcc_dmo_parity;

///////////////////////////////////
// Power management signals
output		lsu_ic_pmen;
output		lsu_ifu_cmu_pmen;
output		lsu_ifu_ftu_pmen;
output		lsu_ifu_ibu_pmen;
output		lsu_dec_pmen    ;
output		lsu_pku_pmen    ;
output		lsu_exu_pmen    ;
output		lsu_fgu_pmen    ;
output		lsu_tlu_pmen    ;
output		lsu_gkt_pmen    ;
output		lsu_spu_pmen    ;
output		lsu_mmu_pmen    ;
output		lsu_pmu_pmen    ;
output		lsu_misc_pmen   ;
output		lsu_asi_clken;

/////////////////////////////////////
// EFU interface

input		efu_spc_fuse_data;
input		efu_spc_fuse_dxfer_en;
input		efu_spc_fuse_dclr;
input		slow_cmp_sync_en;
input		cmp_slow_sync_en;
output		spc_efu_fuse_ddata;
output		spc_efu_fuse_dxfer_en;

input		vnw_ary;


assign tcu_aclk = spc_aclk;
assign tcu_bclk = spc_bclk;
assign pce = 1'b1;
assign rd_pce = 1'b1;
assign wr_pce = 1'b1;
assign bist_clk_mux_sel = 1'b0;

// Reassign gasket interface to match existing ccx interfaces
//assign cpx_spc_data_cx[145:0] = {l15_spc_valid,l15_spc_cpkt[17:13],l15_spc_cpkt[11:0],l15_spc_data1[127:0]};
assign lsu_l15_cpkt[25:0] = spc_pcx_data_pa[129:104];
assign lsu_l15_addr[39:0] = spc_pcx_data_pa[103:64];
assign lsu_l15_data[63:0] = spc_pcx_data_pa[63:0];

assign lsu_dc_pmen      = lsu_asi_pwr_mgmt[15];
assign lsu_ic_pmen      = lsu_asi_pwr_mgmt[14];
assign lsu_ifu_cmu_pmen = lsu_asi_pwr_mgmt[13];
assign lsu_ifu_ftu_pmen = lsu_asi_pwr_mgmt[12];
assign lsu_ifu_ibu_pmen = lsu_asi_pwr_mgmt[11];
assign lsu_dec_pmen     = lsu_asi_pwr_mgmt[10];
assign lsu_pku_pmen     = lsu_asi_pwr_mgmt[9];
assign lsu_lsu_pmen     = lsu_asi_pwr_mgmt[8];
assign lsu_exu_pmen     = lsu_asi_pwr_mgmt[7];
assign lsu_fgu_pmen     = lsu_asi_pwr_mgmt[6];
assign lsu_tlu_pmen     = lsu_asi_pwr_mgmt[5];
assign lsu_gkt_pmen     = lsu_asi_pwr_mgmt[4];
assign lsu_spu_pmen     = lsu_asi_pwr_mgmt[3];
assign lsu_mmu_pmen     = lsu_asi_pwr_mgmt[2];
assign lsu_pmu_pmen     = lsu_asi_pwr_mgmt[1];
assign lsu_misc_pmen    = lsu_asi_pwr_mgmt[0];

lsu_arc_ctl arc (
	.scan_in(arc_scanin),
	.scan_out(arc_scanout),
	.l2clk		(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ard_retl_ctl_1f(ard_retl_ctl_1f),
  .ard_retl_vld_1f(ard_retl_vld_1f),
  .ard_retl_rd_1f(ard_retl_rd_1f),
  .ard_retl_tid_1f(ard_retl_tid_1f[2:0]),
  .ard_retl_ack_1f(ard_retl_ack_1f),
  .ard_retl_exc_1f(ard_retl_exc_1f[1:0]),
  .ard_retf_ctl_1f(ard_retf_ctl_1f),
  .ard_retf_vld_1f(ard_retf_vld_1f),
  .ard_retf_rd_1f(ard_retf_rd_1f),
  .ard_retf_tid_1f(ard_retf_tid_1f[2:0]),
  .ard_retf_ack_1f(ard_retf_ack_1f),
  .ard_retf_exc_1f(ard_retf_exc_1f[1:0]),
  .lsu_asi_clken(lsu_asi_clken),
  .tlu_rngf_cdbus_error(tlu_rngf_cdbus_error),
  .arc_retl_vld_2f(arc_retl_vld_2f),
  .arc_retf_vld_2f(arc_retf_vld_2f),
  .arc_sel_fast(arc_sel_fast),
  .arc_pid_ctl_2f(arc_pid_ctl_2f[6:0]),
  .lsu_priv_action_g(lsu_priv_action_g),
  .lsu_tid_g(lsu_tid_g[2:0])
);

lsu_ard_dp ard (
	.scan_in(ard_scanin),
	.scan_out(ard_scanout),
	.l2clk		(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .rngl_lsu_cdbus(rngl_lsu_cdbus[64:0]),
  .tlu_rngf_cdbus(tlu_rngf_cdbus[64:0]),
  .arc_retl_vld_2f(arc_retl_vld_2f),
  .arc_retf_vld_2f(arc_retf_vld_2f),
  .arc_sel_fast(arc_sel_fast),
  .lsu_asi_clken(lsu_asi_clken),
  .ard_retl_ctl_1f(ard_retl_ctl_1f),
  .ard_retl_vld_1f(ard_retl_vld_1f),
  .ard_retl_rd_1f(ard_retl_rd_1f),
  .ard_retl_tid_1f(ard_retl_tid_1f[2:0]),
  .ard_retl_ack_1f(ard_retl_ack_1f),
  .ard_retl_exc_1f(ard_retl_exc_1f[1:0]),
  .ard_retf_ctl_1f(ard_retf_ctl_1f),
  .ard_retf_vld_1f(ard_retf_vld_1f),
  .ard_retf_rd_1f(ard_retf_rd_1f),
  .ard_retf_tid_1f(ard_retf_tid_1f[2:0]),
  .ard_retf_ack_1f(ard_retf_ack_1f),
  .ard_retf_exc_1f(ard_retf_exc_1f[1:0]),
  .ard_pid_data(ard_pid_data[63:0])
);

lsu_dcd_dp dcd (
	.scan_in(dcd_scanin),
	.scan_out(dcd_scanout),
	.l2clk		(l2clk),
	.bist_cmp_data		(dac_bist_cmp_data[7:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .dca_ld_data_b(dca_ld_data_b[63:0]),
  .dac_byte_one_extend(dac_byte_one_extend[7:1]),
  .dac_byte_sel_data(dac_byte_sel_data[7:1]),
  .dac_swap7_byte0_l(dac_swap7_byte0_l),
  .dac_swap7_byte3_l(dac_swap7_byte3_l),
  .dac_swap7_byte4_l(dac_swap7_byte4_l),
  .dac_swap7_byte7_l(dac_swap7_byte7_l),
  .dac_swap6_byte1_l(dac_swap6_byte1_l),
  .dac_swap6_byte2_l(dac_swap6_byte2_l),
  .dac_swap6_byte5_l(dac_swap6_byte5_l),
  .dac_swap6_byte6_l(dac_swap6_byte6_l),
  .dac_swap5_byte1_l(dac_swap5_byte1_l),
  .dac_swap5_byte2_l(dac_swap5_byte2_l),
  .dac_swap5_byte5_l(dac_swap5_byte5_l),
  .dac_swap5_byte6_l(dac_swap5_byte6_l),
  .dac_swap4_byte0_l(dac_swap4_byte0_l),
  .dac_swap4_byte3_l(dac_swap4_byte3_l),
  .dac_swap4_byte4_l(dac_swap4_byte4_l),
  .dac_swap4_byte7_l(dac_swap4_byte7_l),
  .dac_swap3_byte0_r(dac_swap3_byte0_r),
  .dac_swap3_byte3_r(dac_swap3_byte3_r),
  .dac_swap3_byte4_r(dac_swap3_byte4_r),
  .dac_swap3_byte7_r(dac_swap3_byte7_r),
  .dac_swap2_byte1_r(dac_swap2_byte1_r),
  .dac_swap2_byte2_r(dac_swap2_byte2_r),
  .dac_swap2_byte5_r(dac_swap2_byte5_r),
  .dac_swap2_byte6_r(dac_swap2_byte6_r),
  .dac_swap1_byte0_r(dac_swap1_byte0_r),
  .dac_swap1_byte1_r(dac_swap1_byte1_r),
  .dac_swap1_byte2_r(dac_swap1_byte2_r),
  .dac_swap1_byte3_r(dac_swap1_byte3_r),
  .dac_swap1_byte4_r(dac_swap1_byte4_r),
  .dac_swap1_byte5_r(dac_swap1_byte5_r),
  .dac_swap1_byte6_r(dac_swap1_byte6_r),
  .dac_swap1_byte7_r(dac_swap1_byte7_r),
  .dac_swap0_byte0_r(dac_swap0_byte0_r),
  .dac_swap0_byte1_r(dac_swap0_byte1_r),
  .dac_swap0_byte2_r(dac_swap0_byte2_r),
  .dac_swap0_byte3_r(dac_swap0_byte3_r),
  .dac_swap0_byte4_r(dac_swap0_byte4_r),
  .dac_swap0_byte5_r(dac_swap0_byte5_r),
  .dac_swap0_byte6_r(dac_swap0_byte6_r),
  .dac_swap0_byte7_r(dac_swap0_byte7_r),
  .lsu_exu_ld_data_b(lsu_exu_ld_data_b[63:0]),
  .lsu_fgu_fld_data_b(lsu_fgu_fld_data_b[63:0]),
  .dcd_dca_data_compare(dcd_dca_data_compare[1:0]),
  .dcs_memref_m(dcs_memref_m),
  .lsu_mmu_va_m(lsu_mmu_va_m[47:0]),
  .lsu_mmu_va_b(lsu_mmu_va_b[47:0])
);

lsu_dac_ctl dac (
	.scan_in(dac_scanin),
	.scan_out(dac_scanout),
	.l2clk			(l2clk),
	.tlb_cache_way_hit_b	(cache_way_hit_top_b[3:0]),
  .dcc_ld_inst_vld_m(dcc_ld_inst_vld_m),
  .dcc_l2fill_vld_m(dcc_l2fill_vld_m),
  .dcc_lendian_pre_m(dcc_lendian_pre_m),
  .dcc_bendian_byp_m(dcc_bendian_byp_m),
  .dcc_baddr_m(dcc_baddr_m[2:0]),
  .dcc_ld_sz_m(dcc_ld_sz_m[1:0]),
  .dcc_signed_m(dcc_signed_m),
  .lmc_asi_bypass_m(lmc_asi_bypass_m),
  .lmc_byp_vld_m(lmc_byp_vld_m),
  .lmd_misc_msb_m(lmd_misc_msb_m[7:0]),
  .dca_msb_w0_b(dca_msb_w0_b[7:0]),
  .dca_msb_w1_b(dca_msb_w1_b[7:0]),
  .dca_msb_w2_b(dca_msb_w2_b[7:0]),
  .dca_msb_w3_b(dca_msb_w3_b[7:0]),
  .dac_swap7_byte0_l(dac_swap7_byte0_l),
  .dac_swap7_byte3_l(dac_swap7_byte3_l),
  .dac_swap7_byte4_l(dac_swap7_byte4_l),
  .dac_swap7_byte7_l(dac_swap7_byte7_l),
  .dac_swap6_byte1_l(dac_swap6_byte1_l),
  .dac_swap6_byte2_l(dac_swap6_byte2_l),
  .dac_swap6_byte5_l(dac_swap6_byte5_l),
  .dac_swap6_byte6_l(dac_swap6_byte6_l),
  .dac_swap5_byte1_l(dac_swap5_byte1_l),
  .dac_swap5_byte2_l(dac_swap5_byte2_l),
  .dac_swap5_byte5_l(dac_swap5_byte5_l),
  .dac_swap5_byte6_l(dac_swap5_byte6_l),
  .dac_swap4_byte0_l(dac_swap4_byte0_l),
  .dac_swap4_byte3_l(dac_swap4_byte3_l),
  .dac_swap4_byte4_l(dac_swap4_byte4_l),
  .dac_swap4_byte7_l(dac_swap4_byte7_l),
  .dac_swap3_byte0_r(dac_swap3_byte0_r),
  .dac_swap3_byte3_r(dac_swap3_byte3_r),
  .dac_swap3_byte4_r(dac_swap3_byte4_r),
  .dac_swap3_byte7_r(dac_swap3_byte7_r),
  .dac_swap2_byte1_r(dac_swap2_byte1_r),
  .dac_swap2_byte2_r(dac_swap2_byte2_r),
  .dac_swap2_byte5_r(dac_swap2_byte5_r),
  .dac_swap2_byte6_r(dac_swap2_byte6_r),
  .dac_swap1_byte0_r(dac_swap1_byte0_r),
  .dac_swap1_byte1_r(dac_swap1_byte1_r),
  .dac_swap1_byte2_r(dac_swap1_byte2_r),
  .dac_swap1_byte3_r(dac_swap1_byte3_r),
  .dac_swap1_byte4_r(dac_swap1_byte4_r),
  .dac_swap1_byte5_r(dac_swap1_byte5_r),
  .dac_swap1_byte6_r(dac_swap1_byte6_r),
  .dac_swap1_byte7_r(dac_swap1_byte7_r),
  .dac_swap0_byte0_r(dac_swap0_byte0_r),
  .dac_swap0_byte1_r(dac_swap0_byte1_r),
  .dac_swap0_byte2_r(dac_swap0_byte2_r),
  .dac_swap0_byte3_r(dac_swap0_byte3_r),
  .dac_swap0_byte4_r(dac_swap0_byte4_r),
  .dac_swap0_byte5_r(dac_swap0_byte5_r),
  .dac_swap0_byte6_r(dac_swap0_byte6_r),
  .dac_swap0_byte7_r(dac_swap0_byte7_r),
  .dac_byte_one_extend(dac_byte_one_extend[7:1]),
  .dac_byte_sel_data(dac_byte_sel_data[7:1]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .lbist_run(lbist_run),
  .mbi_run(mbi_run),
  .bist_wdata_1(bist_wdata_1[7:0]),
  .dac_bist_cmp_data(dac_bist_cmp_data[7:0]),
  .lsu_lsu_pmen_(lsu_lsu_pmen_),
  .dmo_coresel(dmo_coresel),
  .dmo_dcmuxctl(dmo_dcmuxctl)
);

assign dcache_bypass_e_ = dcc_dca_bypass_e_;
assign dcache_clk_en_e = dcc_dca_clk_en_e;
assign dcache_rclk_en_m = dcc_dca_rclk_en_m;
assign dcache_wclk_en_e = dcc_dca_wclk_en_e;

n2_dca_sp_9kb_cust dca (
	.dcache_rd_addr_e	({exu_lsu_address_e_rep0[10:4],exu_lsu_address_e[3]}),
	.dcache_alt_addr_e	(dcc_dca_fill_addr_e[10:3]),
	.dcache_alt_addr_sel_e	(dcc_alt_addr_sel_e),
	.dcache_rvld_e		(dcc_dca_rvld_e),
	.dcache_wvld_e		(dcc_dca_wvld_e),
	.dcache_wdata_e		({dcp_parity[15],dcp_fill_data_e[127:120],
                                  dcp_parity[14],dcp_fill_data_e[119:112],
                                  dcp_parity[13],dcp_fill_data_e[111:104],
                                  dcp_parity[12],dcp_fill_data_e[103:96],
                                  dcp_parity[11],dcp_fill_data_e[95:88],
                                  dcp_parity[10],dcp_fill_data_e[87:80],
                                  dcp_parity[9],dcp_fill_data_e[79:72],
                                  dcp_parity[8],dcp_fill_data_e[71:64],
                                  dcp_parity[7],dcp_fill_data_e[63:56],
                                  dcp_parity[6],dcp_fill_data_e[55:48],
                                  dcp_parity[5],dcp_fill_data_e[47:40],
                                  dcp_parity[4],dcp_fill_data_e[39:32],
                                  dcp_parity[3],dcp_fill_data_e[31:24],
                                  dcp_parity[2],dcp_fill_data_e[23:16],
                                  dcp_parity[1],dcp_fill_data_e[15:8],
                                  dcp_parity[0],dcp_fill_data_e[7:0] }),
	.dcache_wr_way_e	(dcc_dca_fill_way_e[1:0]),
	.dcache_byte_wr_en_e	(dcc_dca_byte_wr_en_e[15:0]),
	.dcache_alt_rsel_way_m	(dcc_alt_rsel_way_m[3:0]),
	.dcache_alt_way_sel_m	(dcc_alt_way_sel_m),
	.dcache_rsel_way_b	(tlb_cache_way_hit_b[3:0]),
	.scan_in(dca_scanin),
	.scan_out(dca_scanout),
	.l2clk			(l2clk),
	.dcache_rdata_b		(dca_ld_data_b[63:0]),
	.dcache_rparity_b	(dca_rparity_b[7:0]),
	.dcache_perr_w0_b	(dca_perr_w0_b),
	.dcache_perr_w1_b	(dca_perr_w1_b),
	.dcache_perr_w2_b	(dca_perr_w2_b),
	.dcache_perr_w3_b	(dca_perr_w3_b),
	.lsu_l2fill_or_byp_data_m (lmd_fill_or_byp_data_m_rep1[63:0]),
	.dcache_rdata_msb_w0_b	(dca_msb_w0_b[7:0]),
	.dcache_rdata_msb_w1_b	(dca_msb_w1_b[7:0]),
	.dcache_rdata_msb_w2_b	(dca_msb_w2_b[7:0]),
	.dcache_rdata_msb_w3_b	(dca_msb_w3_b[7:0]),
	.fuse_dca_repair_value	(hdr_sram_rvalue[6:1]),
	.fuse_dca_repair_en	({2{hdr_sram_rvalue[0]}}),
	.fuse_dca_rid		(hdr_sram_rid[1:0]),
	.fuse_dca_wen		(hdr_sram_wr_en),
	.fuse_red_reset		(hdr_sram_red_clr),
	.dca_fuse_repair_value	(dca_fuse_repair_value[5:0]),
	.dca_fuse_repair_en	({dca_fuse_repair_en_unused[1],dca_fuse_repair_en}),
  .dcache_clk_en_e(dcache_clk_en_e),
  .dcache_wclk_en_e(dcache_wclk_en_e),
  .dcache_rclk_en_m(dcache_rclk_en_m),
  .dcache_bypass_e_(dcache_bypass_e_),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .vnw_ary(vnw_ary)

);

lsu_dcp_dp dcp (
	.mbi_run		(dcc_mbi_run),
  .lmd_fill_data_e(lmd_fill_data_e[127:0]),
  .dcc_parity_invert(dcc_parity_invert[7:0]),
  .mbi_wdata(mbi_wdata[7:0]),
  .dcp_fill_data_e(dcp_fill_data_e[127:0]),
  .dcp_parity(dcp_parity[15:0])
);

n2_dva_dp_32x32_cust lru (
	.dout		({lru_unused[3],lru_parity_unused[3],lru_rdata_m[23:18],
			  lru_unused[2],lru_parity_unused[2],lru_rdata_m[17:12],
			  lru_unused[1],lru_parity_unused[1],lru_rdata_m[11:6],
			  lru_unused[0],lru_parity_unused[0],lru_rdata_m[5:0]}),
	.scan_in(lru_scanin),
	.scan_out(lru_scanout),
	.l2clk	(l2clk),
	.rd_addr	(tgc_dva_rd_addr_e[10:6]),
	.rd_en		(dcc_lru_rvld_e),
	.wr_addr	(dcc_lru_wr_addr_w[10:6]),
	.wr_en		(dcc_lru_wvld_w),
	.bit_wen	({{8{dcc_lru_wen_w[3]}},{8{dcc_lru_wen_w[2]}},{8{dcc_lru_wen_w[1]}},{8{dcc_lru_wen_w[0]}}}),
	.din		({4{2'b00,dcc_lru_wdata_w[5:0]}}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_scan_en(tcu_scan_en),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .pce(pce)
);

lsu_dcc_ctl dcc (		
	.tlb_pgnum_b39		(tlb_pgnum[39]),
	.sbd_st_data_b		(sbd_st_predata_b_rep0[1:0]),
	.mbi_cmpsel		(mbi_cmpsel[0]),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep01),
	.tgc_cache_way_vld_m	(tgc_cache_way_vld2_m[3:0]),
	.tlb_cache_way_hit_b	(cache_way_hit_bot_b[3:0]),
	.scan_in(dcc_scanin),
	.scan_out(dcc_scanout),
	.l2clk(l2clk),
  .dec_lsu_tg_d(dec_lsu_tg_d),
  .dec_ld_inst_d(dec_ld_inst_d),
  .dec_ld_inst_e(dec_ld_inst_e),
  .dec_st_inst_e(dec_st_inst_e),
  .dec_fpldst_inst_e(dec_fpldst_inst_e),
  .dec_fsr_ldst_e(dec_fsr_ldst_e),
  .dec_ldst_dbl_e(dec_ldst_dbl_e),
  .dec_pref_inst_e(dec_pref_inst_e),
  .dec_flush_inst_e(dec_flush_inst_e),
  .dec_memstbar_inst_e(dec_memstbar_inst_e),
  .dec_sr_inst_e(dec_sr_inst_e),
  .dec_pr_inst_e(dec_pr_inst_e),
  .dec_hpr_inst_e(dec_hpr_inst_e),
  .dec_casa_inst_e(dec_casa_inst_e),
  .dec_ldstub_inst_e(dec_ldstub_inst_e),
  .dec_swap_inst_e(dec_swap_inst_e),
  .dec_altspace_d(dec_altspace_d),
  .dec_sign_ext_e(dec_sign_ext_e),
  .dec_ldst_sz_e(dec_ldst_sz_e[1:0]),
  .dec_lsu_rd_e(dec_lsu_rd_e[4:0]),
  .dec_sraddr_e(dec_sraddr_e[4:0]),
  .dec_imm_asi_vld_d(dec_imm_asi_vld_d),
  .dec_imm_asi_d(dec_imm_asi_d[7:0]),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .dec_lsu_tid0_d(dec_lsu_tid0_d[1:0]),
  .dec_lsu_tid1_d(dec_lsu_tid1_d[1:0]),
  .tlu_pstate_cle(tlu_pstate_cle[7:0]),
  .tlu_asi_0_tid(tlu_asi_0_tid[1:0]),
  .tlu_asi_1_tid(tlu_asi_1_tid[1:0]),
  .tlu_asi_0_valid(tlu_asi_0_valid),
  .tlu_asi_1_valid(tlu_asi_1_valid),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .tlu_lsu_hpstate_hpriv(tlu_lsu_hpstate_hpriv[7:0]),
  .tlu_lsu_pstate_priv(tlu_lsu_pstate_priv[7:0]),
  .tlu_tl_gt_0(tlu_tl_gt_0[7:0]),
  .tlu_lsu_clear_ctl_reg_(tlu_lsu_clear_ctl_reg_[7:0]),
  .tlu_cerer_dttp(tlu_cerer_dttp),
  .tlu_cerer_dttm(tlu_cerer_dttm),
  .tlu_cerer_dtdp(tlu_cerer_dtdp),
  .tlu_cerer_dcvp(tlu_cerer_dcvp),
  .tlu_cerer_dctp(tlu_cerer_dctp),
  .tlu_cerer_dctm(tlu_cerer_dctm),
  .tlu_cerer_dcdp(tlu_cerer_dcdp),
  .tlc_use_primary_context_c0(tlc_use_primary_context_c0),
  .tlc_use_secondary_context_c0(tlc_use_secondary_context_c0),
  .tld_tid(tld_tid[2:0]),
  .tlc_wr_or_demap(tlc_wr_or_demap),
  .tld_va_m_eq_zero(tld_va_m_eq_zero),
  .exu_lsu_va_error_m(exu_lsu_va_error_m[1:0]),
  .exu_ecc_m(exu_ecc_m[1:0]),
  .exu_lsu_rs2_e(exu_lsu_rs2_e[7:0]),
  .fgu_fst_ecc_error_fx2(fgu_fst_ecc_error_fx2),
  .lmd_sz_m(lmd_sz_m[1:0]),
  .lmd_fpld_m(lmd_fpld_m),
  .lmd_sxt_fsr_m(lmd_sxt_fsr_m),
  .lmd_rd_m(lmd_rd_m[4:0]),
  .lmd_fpodd32b_m(lmd_fpodd32b_m),
  .lmd_fp32b_m(lmd_fp32b_m),
  .lmd_bendian_m(lmd_bendian_m),
  .lmd_fill_addr_e(lmd_fill_addr_e[10:3]),
  .lmd_ld_addr_m(lmd_ld_addr_m[2:0]),
  .lmd_fill_way_e(lmd_fill_way_e[1:0]),
  .lmd_wrtag_parity_e(lmd_wrtag_parity_e),
  .lmc_cpq_tid_m(lmc_cpq_tid_m[2:0]),
  .lmc_thrd_byp_sel_e(lmc_thrd_byp_sel_e[7:0]),
  .lmc_byp_tid_m(lmc_byp_tid_m[2:0]),
  .lmc_byp_vld_m(lmc_byp_vld_m),
  .lmc_asi_bypass_m(lmc_asi_bypass_m),
  .lmc_pref_issued(lmc_pref_issued[7:0]),
  .lmc_bld_annul(lmc_bld_annul),
  .lmc_bld_last_e(lmc_bld_last_e),
  .lmc_bld_miss_e(lmc_bld_miss_e),
  .lmc_full_raw_w(lmc_full_raw_w),
  .lmc_ld_stall(lmc_ld_stall),
  .lmc_l2_err_noup(lmc_l2_err_noup),
  .lmc_l2_uerr(lmc_l2_uerr),
  .tlb_tte_cp_b(tlb_tte_cp_b),
  .tlb_tte_wbit_b(tlb_tte_wbit_b),
  .tlb_tte_ebit_b(tlb_tte_ebit_b),
  .tlb_tte_pbit_b(tlb_tte_pbit_b),
  .tlb_tte_nfo_b(tlb_tte_nfo_b),
  .tlb_cache_hit_b(tlb_cache_hit_b),
  .tlb_cam_hit(tlb_cam_hit),
  .tlb_cam_mhit(tlb_cam_mhit),
  .tlb_pgsize(tlb_pgsize[2:0]),
  .tlb_context0_hit(tlb_context0_hit),
  .tlb_tag_parity(tlb_tag_parity),
  .tlb_tte_data_parity(tlb_tte_data_parity),
  .dcs_asi_d(dcs_asi_d[7:0]),
  .dcs_wpt_mask_m(dcs_wpt_mask_m[7:0]),
  .dcs_wpt_enable_m(dcs_wpt_enable_m[1:0]),
  .dcs_wpt_mode_m(dcs_wpt_mode_m[1:0]),
  .dcs_dc_enable(dcs_dc_enable[7:0]),
  .dcs_dmmu_enable_d(dcs_dmmu_enable_d),
  .lsu_va_m(lsu_va_m[15:0]),
  .lsu_va_b(lsu_va_b[20:3]),
  .cic_l2fill_vld_e(cic_l2fill_vld_e),
  .cic_cpq_ld_sel(cic_cpq_ld_sel),
  .cic_invalidate_e(cic_invalidate_e),
  .cic_xinval_e(cic_xinval_e),
  .cic_st_update_e(cic_st_update_e),
  .cic_rtn_cmplt(cic_rtn_cmplt),
  .cic_oddrd_e(cic_oddrd_e),
  .cic_inv_wen_e(cic_inv_wen_e[15:0]),
  .cic_cpq_stall(cic_cpq_stall),
  .cid_tid(cid_tid[2:0]),
  .cid_xway(cid_xway[1:0]),
  .cid_st_addr(cid_st_addr[10:3]),
  .cid_st_way(cid_st_way[1:0]),
  .cid_st_bmask(cid_st_bmask[7:0]),
  .cid_inv_index(cid_inv_index[10:6]),
  .cid_ncache(cid_ncache),
  .cid_atomic(cid_atomic),
  .cid_l2miss(cid_l2miss),
  .stb_cam_hit(stb_cam_hit),
  .sbc_bst_in_prog_m(sbc_bst_in_prog_m),
  .sbc_tid_m(sbc_tid_m[2:0]),
  .lsu_block_store_alloc(lsu_block_store_alloc[7:0]),
  .lsu_block_store_kill(lsu_block_store_kill[7:0]),
  .tgd_w0_parity_b(tgd_w0_parity_b),
  .tgd_w1_parity_b(tgd_w1_parity_b),
  .tgd_w2_parity_b(tgd_w2_parity_b),
  .tgd_w3_parity_b(tgd_w3_parity_b),
  .tgd_va_wp_47_16(tgd_va_wp_47_16),
  .tgd_va_wp_15_3(tgd_va_wp_15_3),
  .tgd_pa_wp_39_16(tgd_pa_wp_39_16),
  .tgd_pa_wp_15_3(tgd_pa_wp_15_3),
  .tgd_prty_256m_b(tgd_prty_256m_b),
  .tgd_prty_4m_b(tgd_prty_4m_b),
  .tgd_prty_64k_b(tgd_prty_64k_b),
  .tgd_prty_8k_b(tgd_prty_8k_b),
  .tgd_prty_ctxt0_b(tgd_prty_ctxt0_b),
  .tgd_prty_ctxt1_b(tgd_prty_ctxt1_b),
  .tgc_verr_b(tgc_verr_b[3:0]),
  .dca_perr_w0_b(dca_perr_w0_b),
  .dca_perr_w1_b(dca_perr_w1_b),
  .dca_perr_w2_b(dca_perr_w2_b),
  .dca_perr_w3_b(dca_perr_w3_b),
  .dca_rparity_b(dca_rparity_b[7:0]),
  .lru_rdata_m(lru_rdata_m[23:0]),
  .ifu_lsu_if_vld(ifu_lsu_if_vld),
  .ifu_lsu_if_tid(ifu_lsu_if_tid[2:0]),
  .ifu_lsu_if_addr(ifu_lsu_if_addr[10:5]),
  .arc_pid_ctl_2f(arc_pid_ctl_2f[6:0]),
  .dcd_dca_data_compare(dcd_dca_data_compare[1:0]),
  .lbist_run(lbist_run),
  .mbi_addr(mbi_addr[8:0]),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_run(mbi_run),
  .mbi_dca_read_en(mbi_dca_read_en),
  .mbi_dca_write_en(mbi_dca_write_en),
  .mbi_dta_read_en(mbi_dta_read_en),
  .mbi_dta_write_en(mbi_dta_write_en),
  .mbi_dva_read_en(mbi_dva_read_en),
  .mbi_dva_write_en(mbi_dva_write_en),
  .mbi_lru_read_en(mbi_lru_read_en),
  .mbi_lru_write_en(mbi_lru_write_en),
  .mbi_dtb_read_en(mbi_dtb_read_en),
  .mbi_dtb_cam_en_pre(mbi_dtb_cam_en_pre),
  .mbi_scm_cam_en_pre(mbi_scm_cam_en_pre),
  .dmo_dcmuxctl(dmo_dcmuxctl),
  .bist_cmp_data(bist_cmp_data[7:0]),
  .bist_cmpsel_1(bist_cmpsel_1[1:0]),
  .bist_addr_1(bist_addr_1[8:5]),
  .bist_srm_rd_1(bist_srm_rd_1),
  .bist_scm_rd_1(bist_scm_rd_1),
  .lsu_trap_flush(lsu_trap_flush[7:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .dcc_asi_load_m(dcc_asi_load_m),
  .dcc_asi_load_b(dcc_asi_load_b),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_m(dcc_asi_iomap_m),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_binit_st_b(dcc_binit_st_b),
  .dcc_dca_rvld_e(dcc_dca_rvld_e),
  .dcc_dca_wvld_e(dcc_dca_wvld_e),
  .dcc_dca_clk_en_e(dcc_dca_clk_en_e),
  .dcc_dca_wclk_en_e(dcc_dca_wclk_en_e),
  .dcc_dca_rclk_en_m(dcc_dca_rclk_en_m),
  .dcc_dca_bypass_e_(dcc_dca_bypass_e_),
  .dcc_dca_fill_way_e(dcc_dca_fill_way_e[1:0]),
  .dcc_dca_fill_addr_e(dcc_dca_fill_addr_e[10:3]),
  .dcc_dca_byte_wr_en_e(dcc_dca_byte_wr_en_e[15:0]),
  .dcc_parity_invert(dcc_parity_invert[7:0]),
  .dcc_dta_parity(dcc_dta_parity),
  .dcc_alt_addr_sel_e(dcc_alt_addr_sel_e),
  .dcc_alt_way_sel_m(dcc_alt_way_sel_m),
  .dcc_alt_rsel_way_m(dcc_alt_rsel_way_m[3:0]),
  .dcc_dta_fill_addr_e(dcc_dta_fill_addr_e[10:4]),
  .dcc_dta_fill_way_e(dcc_dta_fill_way_e[1:0]),
  .dcc_dta_wvld_e(dcc_dta_wvld_e),
  .dcc_dta_rvld_e(dcc_dta_rvld_e),
  .dcc_dta_index1_sel_e(dcc_dta_index1_sel_e),
  .dcc_dta_clken(dcc_dta_clken),
  .dcc_dva_wvld_e(dcc_dva_wvld_e),
  .dcc_dva_rvld_e(dcc_dva_rvld_e),
  .dcc_dva_din_e(dcc_dva_din_e),
  .dcc_dva_din2_e(dcc_dva_din2_e),
  .dcc_dva_wr_addr_e(dcc_dva_wr_addr_e[10:6]),
  .dcc_dva_bit_wen_e(dcc_dva_bit_wen_e[15:0]),
  .dcc_cache_diag_wr_m(dcc_cache_diag_wr_m),
  .dcc_cache_diag_wr_b(dcc_cache_diag_wr_b),
  .dcc_lru_rvld_e(dcc_lru_rvld_e),
  .dcc_lru_wvld_w(dcc_lru_wvld_w),
  .dcc_lru_wdata_w(dcc_lru_wdata_w[5:0]),
  .dcc_lru_wen_w(dcc_lru_wen_w[3:0]),
  .dcc_lru_wr_addr_w(dcc_lru_wr_addr_w[10:6]),
  .dcc_ldst_bmask(dcc_ldst_bmask[7:0]),
  .dcc_bmask_parity_b(dcc_bmask_parity_b),
  .dcc_ld_miss_b(dcc_ld_miss_b),
  .dcc_early_ld_b(dcc_early_ld_b),
  .dcc_stb_quad_ld_cam(dcc_stb_quad_ld_cam),
  .dcc_l2fill_vld_m(dcc_l2fill_vld_m),
  .dcc_ctxt_tid0_d(dcc_ctxt_tid0_d[1:0]),
  .dcc_ctxt_tid1_d(dcc_ctxt_tid1_d[1:0]),
  .dcc_ctxt_tg_d(dcc_ctxt_tg_d),
  .dcc_tid_e(dcc_tid_e[2:0]),
  .dcc_tid_m(dcc_tid_m[2:0]),
  .dcc_tid_b(dcc_tid_b[2:0]),
  .dcc_asi_m(dcc_asi_m[7:0]),
  .dcc_ld_inst_unqual_e(dcc_ld_inst_unqual_e),
  .dcc_ld_inst_vld_m(dcc_ld_inst_vld_m),
  .dcc_stb_cam_vld_m(dcc_stb_cam_vld_m),
  .dcc_baddr_m(dcc_baddr_m[2:0]),
  .dcc_signed_m(dcc_signed_m),
  .dcc_pref_inst_m(dcc_pref_inst_m),
  .dcc_std_inst_m(dcc_std_inst_m),
  .dcc_ldstub_inst_m(dcc_ldstub_inst_m),
  .dcc_atomic_b(dcc_atomic_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_lendian_pre_m(dcc_lendian_pre_m),
  .dcc_bendian_byp_m(dcc_bendian_byp_m),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_tte_vld_m(dcc_tte_vld_m),
  .dcc_ldst_sz_m(dcc_ldst_sz_m[1:0]),
  .dcc_ld_sz_m(dcc_ld_sz_m[1:0]),
  .dcc_fp32b_sel_m(dcc_fp32b_sel_m),
  .dcc_blk_inst_m(dcc_blk_inst_m),
  .dcc_blk_inst_b(dcc_blk_inst_b),
  .dcc_ldbl_b(dcc_ldbl_b),
  .dcc_ncache_b(dcc_ncache_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_sync_pipe_w(dcc_sync_pipe_w),
  .dcc_priv_b(dcc_priv_b),
  .dcc_hpriv_b(dcc_hpriv_b),
  .dcc_pctxt_sel_e(dcc_pctxt_sel_e),
  .dcc_sctxt_sel_e(dcc_sctxt_sel_e),
  .dcc_ld_miss_ldd(dcc_ld_miss_ldd),
  .dcc_ld_miss_ctl(dcc_ld_miss_ctl[60:40]),
  .dcc_sync_inst_w(dcc_sync_inst_w[7:0]),
  .dcc_asi_reload_sel(dcc_asi_reload_sel[7:0]),
  .dcc_wr_wtchpt(dcc_wr_wtchpt[7:0]),
  .dcc_wr_lsu_ctl_reg(dcc_wr_lsu_ctl_reg[7:0]),
  .dcc_wr_pwr_mgmt(dcc_wr_pwr_mgmt),
  .dcc_ceter_wr_w(dcc_ceter_wr_w),
  .dcc_p0ctxt_rd_m(dcc_p0ctxt_rd_m),
  .dcc_p1ctxt_rd_m(dcc_p1ctxt_rd_m),
  .dcc_s0ctxt_rd_m(dcc_s0ctxt_rd_m),
  .dcc_s1ctxt_rd_m(dcc_s1ctxt_rd_m),
  .dcc_pid_rd_m(dcc_pid_rd_m),
  .dcc_wtchpt_sel_m(dcc_wtchpt_sel_m),
  .dcc_demap_asi_m(dcc_demap_asi_m),
  .dcc_wtchpt_rd_b(dcc_wtchpt_rd_b),
  .dcc_rd_lsu_ctl_reg_b(dcc_rd_lsu_ctl_reg_b),
  .dcc_rd_diag_reg_b(dcc_rd_diag_reg_b),
  .dcc_rd_diag_dca_b(dcc_rd_diag_dca_b),
  .dcc_rd_core_id_b(dcc_rd_core_id_b),
  .dcc_rd_intr_id_b(dcc_rd_intr_id_b),
  .dcc_rd_dt_diag_m(dcc_rd_dt_diag_m),
  .dcc_rd_dt_diag_b(dcc_rd_dt_diag_b),
  .dcc_stb_diag_rd_m(dcc_stb_diag_rd_m),
  .dcc_rd_error_inj_b(dcc_rd_error_inj_b),
  .dcc_rd_pwr_mgmt_b(dcc_rd_pwr_mgmt_b),
  .dcc_wr_error_inj_m(dcc_wr_error_inj_m),
  .dcc_wr_error_inj_w(dcc_wr_error_inj_w),
  .dcc_tlb_data_read_b(dcc_tlb_data_read_b),
  .dcc_tlb_tag0_read_b(dcc_tlb_tag0_read_b),
  .dcc_tlb_tag1_read_b(dcc_tlb_tag1_read_b),
  .dcc_tlb_rw_index_e(dcc_tlb_rw_index_e),
  .dcc_rd_rhs_asi_b(dcc_rd_rhs_asi_b),
  .dcc_lsu_asi_rd_b(dcc_lsu_asi_rd_b),
  .dcc_lsu_asi_sel_w(dcc_lsu_asi_sel_w),
  .dcc_stb_diag_sel_w3(dcc_stb_diag_sel_w3),
  .dcc_stb_data_rd_w3(dcc_stb_data_rd_w3),
  .dcc_stb_ecc_rd_w3(dcc_stb_ecc_rd_w3),
  .dcc_stb_ctl_rd_w3(dcc_stb_ctl_rd_w3),
  .dcc_stb_addr_sel_w3(dcc_stb_addr_sel_w3),
  .dcc_stb_ptr_rd_w3(dcc_stb_ptr_rd_w3),
  .dcc_direct_map(dcc_direct_map),
  .dcc_dcs_memref_e(dcc_dcs_memref_e),
  .dcc_tlb_lookup(dcc_tlb_lookup),
  .dcc_tlb_bypass(dcc_tlb_bypass),
  .dcc_tlb_real(dcc_tlb_real),
  .dcc_tlb_rd_e(dcc_tlb_rd_e),
  .dcc_perror_b(dcc_perror_b),
  .dcc_perr_enc_b(dcc_perr_enc_b[1:0]),
  .dcc_dmo_parity(dcc_dmo_parity[3:0]),
  .lsu_va_w(lsu_va_w[12:3]),
  .dcc_sbd_e_clken(dcc_sbd_e_clken),
  .dcc_sbd_m_clken(dcc_sbd_m_clken),
  .dcc_ldst_m_clken(dcc_ldst_m_clken),
  .dcc_asi_rtn_vld(dcc_asi_rtn_vld[7:0]),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_exu_ld_vld_w(lsu_exu_ld_vld_w),
  .lsu_exu_ld_b(lsu_exu_ld_b),
  .lsu_exu_tid_m(lsu_exu_tid_m[2:0]),
  .lsu_exu_rd_m(lsu_exu_rd_m[4:0]),
  .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w),
  .lsu_fgu_fld_b(lsu_fgu_fld_b),
  .lsu_fgu_fld_32b_b(lsu_fgu_fld_32b_b),
  .lsu_fgu_fld_odd32b_b(lsu_fgu_fld_odd32b_b),
  .lsu_fgu_fsr_load_b(lsu_fgu_fsr_load_b),
  .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]),
  .lsu_fgu_fld_addr_b(lsu_fgu_fld_addr_b[4:0]),
  .lsu_fgu_exception_w(lsu_fgu_exception_w),
  .lsu_sync(lsu_sync[7:0]),
  .lsu_complete(lsu_complete[7:0]),
  .lsu_cpq_stall(lsu_cpq_stall),
  .lsu_tlu_twocycle_m(lsu_tlu_twocycle_m),
  .lsu_tlb_bypass_b(lsu_tlb_bypass_b),
  .lsu_tlb_real_b(lsu_tlb_real_b),
  .lsu_align_b(lsu_align_b),
  .lsu_lddf_align_b(lsu_lddf_align_b),
  .lsu_stdf_align_b(lsu_stdf_align_b),
  .lsu_dae_invalid_asi_b(lsu_dae_invalid_asi_b),
  .lsu_dae_nc_page_b(lsu_dae_nc_page_b),
  .lsu_dae_nfo_page_b(lsu_dae_nfo_page_b),
  .lsu_dae_priv_viol_b(lsu_dae_priv_viol_b),
  .lsu_dae_so_page(lsu_dae_so_page),
  .lsu_priv_action_b(lsu_priv_action_b),
  .lsu_va_watchpoint_b(lsu_va_watchpoint_b),
  .lsu_pa_watchpoint_b(lsu_pa_watchpoint_b),
  .lsu_illegal_inst_b(lsu_illegal_inst_b),
  .lsu_daccess_prot_b(lsu_daccess_prot_b),
  .lsu_tlb_miss_b_(lsu_tlb_miss_b_),
  .lsu_perfmon_trap_b(lsu_perfmon_trap_b),
  .lsu_perfmon_trap_g(lsu_perfmon_trap_g),
  .lsu_tlu_dsfsr_ct_b(lsu_tlu_dsfsr_ct_b[1:0]),
  .lsu_sync_inst_b(lsu_sync_inst_b),
  .lsu_dttp_err_b(lsu_dttp_err_b),
  .lsu_dtdp_err_b(lsu_dtdp_err_b),
  .lsu_dtmh_err_b(lsu_dtmh_err_b),
  .lsu_ifu_direct_map(lsu_ifu_direct_map),
  .dcc_mbi_run(dcc_mbi_run),
  .lsu_mbi_dca_fail(lsu_mbi_dca_fail),
  .lsu_mbi_lru_fail(lsu_mbi_lru_fail),
  .pmu_lsu_dcmiss_trap_m(pmu_lsu_dcmiss_trap_m),
  .pmu_lsu_dtmiss_trap_m(pmu_lsu_dtmiss_trap_m),
  .pmu_lsu_l2dmiss_trap_m(pmu_lsu_l2dmiss_trap_m[7:0]),
  .lsu_pmu_mem_type_b(lsu_pmu_mem_type_b[2:0]),
  .lsu_dc_pmen(lsu_dc_pmen),
  .lsu_lsu_pmen(lsu_lsu_pmen),
  .lsu_lsu_pmen_(lsu_lsu_pmen_),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

lsu_dcs_dp dcs (	// FS:wmr_prot
	.sbd_st_data_b		(sbd_st_predata_b_rep0[47:0]),
	.asd_asi_data		(lsu_rngf_cdbus[12:0]),
	.wmr_scan_in(dcs_wmr_scanin),
	.wmr_scan_out(dcs_wmr_scanout),
	.scan_in(dcs_scanin),
	.scan_out(dcs_scanout),
	.l2clk			(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk_wmr(spc_aclk_wmr),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .lb_scan_en_wmr(lb_scan_en_wmr),
  .const_cpuid(const_cpuid[2:0]),
  .dec_lsu_tid0_d(dec_lsu_tid0_d[1:0]),
  .dec_lsu_tid1_d(dec_lsu_tid1_d[1:0]),
  .dec_lsu_tg_d(dec_lsu_tg_d),
  .dcc_ld_inst_unqual_e(dcc_ld_inst_unqual_e),
  .dcc_ctxt_tid0_d(dcc_ctxt_tid0_d[1:0]),
  .dcc_ctxt_tid1_d(dcc_ctxt_tid1_d[1:0]),
  .dcc_ctxt_tg_d(dcc_ctxt_tg_d),
  .dcc_tid_m(dcc_tid_m[2:0]),
  .dcc_tid_b(dcc_tid_b[2:0]),
  .dcc_asi_reload_sel(dcc_asi_reload_sel[7:0]),
  .dcc_wr_wtchpt(dcc_wr_wtchpt[7:0]),
  .dcc_wr_lsu_ctl_reg(dcc_wr_lsu_ctl_reg[7:0]),
  .dcc_wr_pwr_mgmt(dcc_wr_pwr_mgmt),
  .dcc_rd_lsu_ctl_reg_b(dcc_rd_lsu_ctl_reg_b),
  .dcc_rd_diag_reg_b(dcc_rd_diag_reg_b),
  .dcc_rd_core_id_b(dcc_rd_core_id_b),
  .dcc_rd_intr_id_b(dcc_rd_intr_id_b),
  .dcc_rd_rhs_asi_b(dcc_rd_rhs_asi_b),
  .dcc_rd_diag_dca_b(dcc_rd_diag_dca_b),
  .dcc_rd_error_inj_b(dcc_rd_error_inj_b),
  .dcc_rd_pwr_mgmt_b(dcc_rd_pwr_mgmt_b),
  .dcc_wr_error_inj_w(dcc_wr_error_inj_w),
  .dcc_p0ctxt_rd_m(dcc_p0ctxt_rd_m),
  .dcc_p1ctxt_rd_m(dcc_p1ctxt_rd_m),
  .dcc_s0ctxt_rd_m(dcc_s0ctxt_rd_m),
  .dcc_s1ctxt_rd_m(dcc_s1ctxt_rd_m),
  .dcc_pid_rd_m(dcc_pid_rd_m),
  .dcc_wtchpt_sel_m(dcc_wtchpt_sel_m),
  .dcc_wtchpt_rd_b(dcc_wtchpt_rd_b),
  .dcc_pctxt_sel_e(dcc_pctxt_sel_e),
  .dcc_sctxt_sel_e(dcc_sctxt_sel_e),
  .dcc_dcs_memref_e(dcc_dcs_memref_e),
  .dcc_direct_map(dcc_direct_map),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_load_m(dcc_asi_load_m),
  .dcc_asi_load_b(dcc_asi_load_b),
  .lsu_ifu_direct_map(lsu_ifu_direct_map),
  .asc_wr_p0ctxt(asc_wr_p0ctxt[7:0]),
  .asc_wr_p1ctxt(asc_wr_p1ctxt[7:0]),
  .asc_wr_s0ctxt(asc_wr_s0ctxt[7:0]),
  .asc_wr_s1ctxt(asc_wr_s1ctxt[7:0]),
  .asc_wr_pid(asc_wr_pid[7:0]),
  .asc_wrasi(asc_wrasi[7:0]),
  .tlu_asi_0(tlu_asi_0[7:0]),
  .tlu_asi_1(tlu_asi_1[7:0]),
  .tlu_lsu_clear_ctl_reg_(tlu_lsu_clear_ctl_reg_[7:0]),
  .dca_rparity_b(dca_rparity_b[7:0]),
  .tgd_ldxa_asi_data_b(tgd_ldxa_asi_data_b[63:0]),
  .lsu_va_m(lsu_va_m[20:0]),
  .lsu_va_b(lsu_va_b[20:0]),
  .dcs_asi_d(dcs_asi_d[7:0]),
  .dcs_context0_e(dcs_context0_e[12:0]),
  .dcs_context1_e(dcs_context1_e[12:0]),
  .dcs_pid_e(dcs_pid_e[2:0]),
  .dcs_ldxa_asi_data_w(dcs_ldxa_asi_data_w[63:0]),
  .dcs_watchpoint_m(dcs_watchpoint_m[47:3]),
  .dcs_dc_enable(dcs_dc_enable[7:0]),
  .dcs_wpt_mask_m(dcs_wpt_mask_m[7:0]),
  .dcs_wpt_enable_m(dcs_wpt_enable_m[1:0]),
  .dcs_wpt_mode_m(dcs_wpt_mode_m[1:0]),
  .dcs_dmmu_enable_d(dcs_dmmu_enable_d),
  .lsu_immu_enable(lsu_immu_enable[7:0]),
  .lsu_ic_enable(lsu_ic_enable[7:0]),
  .lsu_context_b(lsu_context_b[12:0]),
  .lsu_asi_error_inject(lsu_asi_error_inject[31:0]),
  .lsu_asi_pwr_mgmt(lsu_asi_pwr_mgmt[15:0]),
  .dcs_memref_m(dcs_memref_m)
);

lsu_lmd_dp lmd (
	.sbd_st_data_b		(sbd_st_data2_b_rep0[63:0]),
	.stb_ram_data		(stb_ram_data_rep0[63:0]),
	.scan_in(lmd_scanin),
	.scan_out(lmd_scanout),
	.l2clk			(l2clk),
  .lmc_lmq_enable_b(lmc_lmq_enable_b[7:0]),
  .lmc_lmq_bypass_en(lmc_lmq_bypass_en[7:0]),
  .lmc_pcx_sel_p4(lmc_pcx_sel_p4[7:0]),
  .lmc_byp_sel_e(lmc_byp_sel_e[7:0]),
  .lmc_thrd_byp_sel_m(lmc_thrd_byp_sel_m[7:0]),
  .lmc_lmq0_byp_sel(lmc_lmq0_byp_sel[4:0]),
  .lmc_lmq1_byp_sel(lmc_lmq1_byp_sel[4:0]),
  .lmc_lmq2_byp_sel(lmc_lmq2_byp_sel[4:0]),
  .lmc_lmq3_byp_sel(lmc_lmq3_byp_sel[4:0]),
  .lmc_lmq4_byp_sel(lmc_lmq4_byp_sel[4:0]),
  .lmc_lmq5_byp_sel(lmc_lmq5_byp_sel[4:0]),
  .lmc_lmq6_byp_sel(lmc_lmq6_byp_sel[4:0]),
  .lmc_lmq7_byp_sel(lmc_lmq7_byp_sel[4:0]),
  .lmc_bld_addr54(lmc_bld_addr54[1:0]),
  .lmc_bld_req(lmc_bld_req),
  .lmc_bld_req_(lmc_bld_req_),
  .lmc_lmd_ncache_b(lmc_lmd_ncache_b),
  .lmc_rd_update(lmc_rd_update[7:0]),
  .lmc_ld_unfilled(lmc_ld_unfilled[7:0]),
  .lmc_bist_or_diag_e(lmc_bist_or_diag_e),
  .lmc_byp_data_hi(lmc_byp_data_hi),
  .lmc_byp_data_enable(lmc_byp_data_enable),
  .dcc_ld_miss_ctl(dcc_ld_miss_ctl[60:40]),
  .dcc_perr_enc_b(dcc_perr_enc_b[1:0]),
  .dcc_l2fill_vld_m(dcc_l2fill_vld_m),
  .dcc_cache_diag_wr_b(dcc_cache_diag_wr_b),
  .ard_pid_data(ard_pid_data[63:0]),
  .stb_st_addr_b(stb_st_addr_b[39:13]),
  .sbd_st_addr_b(sbd_st_addr_b[12:11]),
  .stb_ldxa_asi_data_w(stb_ldxa_asi_data_w[63:0]),
  .lsu_va_b(lsu_va_b[12:0]),
  .lsu_va_w(lsu_va_w[12:3]),
  .cid_fill_data_e(cid_fill_data_e[127:0]),
  .cid_st_data_sel(cid_st_data_sel),
  .cid_tid(cid_tid[2:0]),
  .lsu_cpx_cpkt(lsu_cpx_cpkt[8:6]),
  .dcs_ldxa_asi_data_w(dcs_ldxa_asi_data_w[63:0]),
  .cic_diag_data_sel_e(cic_diag_data_sel_e),
  .mbi_wdata(mbi_wdata[7:0]),
  .lmc_mbi_run(lmc_mbi_run),
  .lmd_addrb2(lmd_addrb2),
  .lmd_asi_ld(lmd_asi_ld[7:0]),
  .lmd_asi_indet(lmd_asi_indet[7:0]),
  .lmd_sec_cmp_b(lmd_sec_cmp_b[7:0]),
  .lmd_ld_addr_m(lmd_ld_addr_m[2:0]),
  .lmd_fill_sz_b0_e(lmd_fill_sz_b0_e),
  .lmd_bendian_m(lmd_bendian_m),
  .lmd_sxt_fsr_m(lmd_sxt_fsr_m),
  .lmd_fill_way_e(lmd_fill_way_e[1:0]),
  .lmd_fill_way_m(lmd_fill_way_m[1:0]),
  .lmd_sz_m(lmd_sz_m[1:0]),
  .lmd_fpld_m(lmd_fpld_m),
  .lmd_rd_e(lmd_rd_e[2:1]),
  .lmd_rd_m(lmd_rd_m[4:0]),
  .lmd_fpodd32b_m(lmd_fpodd32b_m),
  .lmd_fp32b_m(lmd_fp32b_m),
  .lmd_bypass_data_m(lmd_bypass_data_m[63:0]),
  .lmd_fill_data_e(lmd_fill_data_e[127:0]),
  .lmd_fill_or_byp_data_m(lmd_fill_or_byp_data_m[63:0]),
  .lmd_misc_msb_m(lmd_misc_msb_m[7:0]),
  .lmd_fill_addr_e(lmd_fill_addr_e[39:3]),
  .lmd_fill_addr_m(lmd_fill_addr_m[10:4]),
  .lmd_wrtag_parity_e(lmd_wrtag_parity_e),
  .lmd_pcx_rqtyp(lmd_pcx_rqtyp[2:0]),
  .lmd_pcx_nc(lmd_pcx_nc),
  .lmd_pcx_pref(lmd_pcx_pref),
  .lmd_pcx_rway(lmd_pcx_rway[1:0]),
  .lmd_pcx_addr(lmd_pcx_addr[39:0]),
  .lmd_asi_rngf(lmd_asi_rngf),
  .lmd_asi_type(lmd_asi_type[1:0]),
  .lmd_asi_asi(lmd_asi_asi[7:0]),
  .lmd_sz_b1(lmd_sz_b1),
  .lmd_sz_b0(lmd_sz_b0),
  .lmd_ldbl(lmd_ldbl),
  .lmd_dc_err_e(lmd_dc_err_e[1:0]),
  .lsu_ifu_ld_index(lsu_ifu_ld_index[10:5]),
  .lsu_ext_int_type(lsu_ext_int_type[1:0]),
  .lsu_ext_int_vec(lsu_ext_int_vec[5:0]),
  .lsu_ext_int_tid(lsu_ext_int_tid[2:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

assign lsu_dcerr_sfar_g[8:0] = {lmd_fill_way_m[1:0],lmd_fill_addr_m[10:4]};

lsu_lmc_ctl lmc (
	.scan_in(lmc_scanin),
	.scan_out(lmc_scanout),
	.l2clk(l2clk),
	.tlb_pgnum_b39		(tlb_pgnum[39]),
	.dcc_ld_miss_ctl_b43	(dcc_ld_miss_ctl[43]),
	.stb_cam_hit		(stb_cam_hit_rep0),
	.lmd_fill_addr_b3_e	(lmd_fill_addr_e[3]),
	.cid_tid		(cid_tid_unbuf[2:0]),
	.sbd_st_data_b_62	(sbd_st_data2_b_rep0[62]),
	.sbc_kill_store_p4_	(sbc_pic_kill_store_p4_),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .dcc_tid_m(dcc_tid_m[2:0]),
  .dcc_ld_inst_vld_m(dcc_ld_inst_vld_m),
  .dcc_pref_inst_m(dcc_pref_inst_m),
  .dcc_ld_miss_b(dcc_ld_miss_b),
  .dcc_ld_miss_ldd(dcc_ld_miss_ldd),
  .dcc_asi_load_b(dcc_asi_load_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_blk_inst_b(dcc_blk_inst_b),
  .dcc_ldbl_b(dcc_ldbl_b),
  .dcc_ncache_b(dcc_ncache_b),
  .dcc_atomic_b(dcc_atomic_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_lsu_asi_rd_b(dcc_lsu_asi_rd_b),
  .dcc_lsu_asi_sel_w(dcc_lsu_asi_sel_w),
  .dcc_ceter_wr_w(dcc_ceter_wr_w),
  .dcc_stb_diag_sel_w3(dcc_stb_diag_sel_w3),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .dcc_perror_b(dcc_perror_b),
  .dcc_sync_pipe_w(dcc_sync_pipe_w),
  .dcc_cache_diag_wr_b(dcc_cache_diag_wr_b),
  .dcc_asi_rtn_vld(dcc_asi_rtn_vld[7:0]),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .pic_casa_squash_req(pic_casa_squash_req),
  .pic_early_ld_b_sel_p3(pic_early_ld_b_sel_p3),
  .pic_no_load_p3(pic_no_load_p3),
  .pic_asi_busy(pic_asi_busy),
  .lmd_pcx_pref(lmd_pcx_pref),
  .lmd_asi_ld(lmd_asi_ld[7:0]),
  .lmd_asi_indet(lmd_asi_indet[7:0]),
  .lmd_sec_cmp_b(lmd_sec_cmp_b[7:0]),
  .lmd_addrb2(lmd_addrb2),
  .lmd_sz_b1(lmd_sz_b1),
  .lmd_sz_b0(lmd_sz_b0),
  .lmd_ldbl(lmd_ldbl),
  .lmd_rd_e(lmd_rd_e[2:1]),
  .lmd_dc_err_e(lmd_dc_err_e[1:0]),
  .lmd_fill_sz_b0_e(lmd_fill_sz_b0_e),
  .tlb_cam_mhit(tlb_cam_mhit),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .tlu_cerer_sbdlc(tlu_cerer_sbdlc),
  .tlu_cerer_sbdlu(tlu_cerer_sbdlu),
  .tlu_cerer_dcl2c(tlu_cerer_dcl2c),
  .tlu_cerer_dcl2u(tlu_cerer_dcl2u),
  .tlu_cerer_dcl2nd(tlu_cerer_dcl2nd),
  .tlu_cerer_l2c_socc(tlu_cerer_l2c_socc),
  .tlu_cerer_l2u_socu(tlu_cerer_l2u_socu),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .dec_ld_inst_d(dec_ld_inst_d),
  .cic_l2fill_vld_e(cic_l2fill_vld_e),
  .cic_cpq_ld_rdy(cic_cpq_ld_rdy),
  .cic_cpq_ld_rdy_(cic_cpq_ld_rdy_),
  .cic_div_stall_d(cic_div_stall_d),
  .cic_oddrd_e(cic_oddrd_e),
  .cic_xinval_e(cic_xinval_e),
  .cic_xinval(cic_xinval[7:0]),
  .cic_set_inval(cic_set_inval),
  .cic_rtn_cmplt(cic_rtn_cmplt),
  .cic_cpq_stall(cic_cpq_stall),
  .cic_ext_interrupt(cic_ext_interrupt),
  .cid_err(cid_err[1:0]),
  .cid_dcsoc_err_e(cid_dcsoc_err_e),
  .cid_l2miss(cid_l2miss),
  .stb_cam_mhit(stb_cam_mhit),
  .stb_ld_part_raw(stb_ld_part_raw),
  .stb_cecc_err(stb_cecc_err),
  .stb_uecc_err(stb_uecc_err),
  .sbs_all_commited(sbs_all_commited[7:0]),
  .sbc_st_atom_p3(sbc_st_atom_p3[7:0]),
  .sbc_rawp_rst(sbc_rawp_rst[7:0]),
  .sbc_st_sel_tid_p4(sbc_st_sel_tid_p4[2:0]),
  .sbc_force_inv(sbc_force_inv),
  .lsu_lsu_pmen(lsu_lsu_pmen),
  .lmc_lmq_enable_b(lmc_lmq_enable_b[7:0]),
  .lmc_pcx_sel_p4(lmc_pcx_sel_p4[7:0]),
  .lmc_pcx_rq_vld(lmc_pcx_rq_vld),
  .lmc_asi_rq_vld(lmc_asi_rq_vld),
  .lmc_ld_rq_p3(lmc_ld_rq_p3),
  .lmc_ld_vld_p4(lmc_ld_vld_p4),
  .lmc_ld_no_req_p4(lmc_ld_no_req_p4),
  .lmc_ld_inv_p4(lmc_ld_inv_p4),
  .lmc_ld_tid(lmc_ld_tid[2:0]),
  .lmc_byp_sel_e(lmc_byp_sel_e[7:0]),
  .lmc_cpq_tid_m(lmc_cpq_tid_m[2:0]),
  .lmc_lmq_bypass_en(lmc_lmq_bypass_en[7:0]),
  .lmc_asi_bypass_m(lmc_asi_bypass_m),
  .lmc_bld_addr54(lmc_bld_addr54[1:0]),
  .lmc_bld_req(lmc_bld_req),
  .lmc_bld_req_(lmc_bld_req_),
  .lmc_bld_annul(lmc_bld_annul),
  .lmc_bld_miss_e(lmc_bld_miss_e),
  .lmc_bld_last_e(lmc_bld_last_e),
  .lmc_rd_update(lmc_rd_update[7:0]),
  .lmc_pref_issued(lmc_pref_issued[7:0]),
  .lmc_ldd_vld(lmc_ldd_vld[7:0]),
  .lmc_ld_unfilled(lmc_ld_unfilled[7:0]),
  .lmc_lmd_ncache_b(lmc_lmd_ncache_b),
  .lmc_ld_sz(lmc_ld_sz[4:0]),
  .lmc_ld_inst_w(lmc_ld_inst_w),
  .lmc_full_raw_w(lmc_full_raw_w),
  .lmc_ld_stall(lmc_ld_stall),
  .lmc_l2_err_noup(lmc_l2_err_noup),
  .lmc_l2_uerr(lmc_l2_uerr),
  .lmc_byp_data_hi(lmc_byp_data_hi),
  .lmc_byp_data_enable(lmc_byp_data_enable),
  .lmc_thrd_byp_sel_e(lmc_thrd_byp_sel_e[7:0]),
  .lmc_thrd_byp_sel_m(lmc_thrd_byp_sel_m[7:0]),
  .lmc_byp_tid_m(lmc_byp_tid_m[2:0]),
  .lmc_byp_vld_m(lmc_byp_vld_m),
  .lmc_lmq0_byp_sel(lmc_lmq0_byp_sel[4:0]),
  .lmc_lmq1_byp_sel(lmc_lmq1_byp_sel[4:0]),
  .lmc_lmq2_byp_sel(lmc_lmq2_byp_sel[4:0]),
  .lmc_lmq3_byp_sel(lmc_lmq3_byp_sel[4:0]),
  .lmc_lmq4_byp_sel(lmc_lmq4_byp_sel[4:0]),
  .lmc_lmq5_byp_sel(lmc_lmq5_byp_sel[4:0]),
  .lmc_lmq6_byp_sel(lmc_lmq6_byp_sel[4:0]),
  .lmc_lmq7_byp_sel(lmc_lmq7_byp_sel[4:0]),
  .lmc_asi_indet_retire(lmc_asi_indet_retire),
  .lsu_ifu_no_miss(lsu_ifu_no_miss[7:0]),
  .lsu_dcmh_err_g(lsu_dcmh_err_g),
  .lsu_dcvp_err_g(lsu_dcvp_err_g),
  .lsu_dctp_err_g(lsu_dctp_err_g),
  .lsu_dcdp_err_g(lsu_dcdp_err_g),
  .lsu_dcerr_tid_g(lsu_dcerr_tid_g[2:0]),
  .lsu_dcl2c_err_g(lsu_dcl2c_err_g),
  .lsu_dcl2u_err_g(lsu_dcl2u_err_g),
  .lsu_dcl2nd_err_g(lsu_dcl2nd_err_g),
  .lsu_sbdlc_err_g(lsu_sbdlc_err_g),
  .lsu_sbdlu_err_g(lsu_sbdlu_err_g),
  .lsu_stberr_tid_g(lsu_stberr_tid_g[2:0]),
  .lbist_run(lbist_run),
  .mbi_run(mbi_run),
  .lmc_mbi_run(lmc_mbi_run),
  .lmc_bist_or_diag_e(lmc_bist_or_diag_e)
);

lsu_pic_ctl pic (
	.scan_in(pic_scanin),
	.scan_out(pic_scanout),
	.l2clk		(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .lmc_pcx_rq_vld(lmc_pcx_rq_vld),
  .lmc_asi_rq_vld(lmc_asi_rq_vld),
  .lmc_ld_rq_p3(lmc_ld_rq_p3),
  .lmc_ld_no_req_p4(lmc_ld_no_req_p4),
  .tlb_cache_hit_b(tlb_cache_hit_b),
  .dcc_early_ld_b(dcc_early_ld_b),
  .sbc_asi_rq_p3(sbc_asi_rq_p3),
  .sbc_pcx_rq_p3(sbc_pcx_rq_p3),
  .sbc_st_atomic_p2(sbc_st_atomic_p2),
  .sbc_st_rq_p2(sbc_st_rq_p2),
  .sbc_pic_kill_store_p4_(sbc_pic_kill_store_p4_),
  .sbc_indet_block_p3(sbc_indet_block_p3),
  .sbs_stb_full(sbs_stb_full[7:0]),
  .asc_pid_ack(asc_pid_ack),
  .dcc_asi_rtn_vld(dcc_asi_rtn_vld[7:0]),
  .lsu_ring_ctl(lsu_ring_ctl),
  .lsu_misc_pmen(lsu_misc_pmen),
  .pic_ld_pcx_sel_p4(pic_ld_pcx_sel_p4),
  .pic_st_pcx_sel_p3(pic_st_pcx_sel_p3),
  .pic_st_pcx_sel_p4(pic_st_pcx_sel_p4),
  .pic_st_asi_sel_p3(pic_st_asi_sel_p3),
  .pic_st_asi_p4(pic_st_asi_p4),
  .pic_ld_asi_p4(pic_ld_asi_p4),
  .pic_st_sel_p3(pic_st_sel_p3),
  .pic_asi_sel_p4(pic_asi_sel_p4),
  .pic_asi_req(pic_asi_req),
  .pic_casa_squash_req(pic_casa_squash_req),
  .pic_early_ld_b_sel_p3(pic_early_ld_b_sel_p3),
  .pic_no_load_p3(pic_no_load_p3),
  .pic_asi_busy(pic_asi_busy),
  .l15_lsu_grant(l15_lsu_grant),
  .lsu_l15_valid(lsu_l15_valid),
  .lsu_l15_lock(lsu_l15_lock),
  .lsu_asi_clken(lsu_asi_clken)
);

n2_com_dp_32x152_cust cpq (
	.wr_adr	(cic_cpq_wptr[4:0]),
	.wr_en	(cic_cpq_wr_en),
	.rd_adr	(cic_cpq_rptr[4:0]),
	.rd_en	(cic_cpq_rd_en),
	.din	(cpq_din[151:0]),
	.scan_in(cpq_scanin),
	.scan_out(cpq_scanout),
	.rdclk	(l2clk),
	.wrclk	(l2clk),
	.dout	(cpq_dout[151:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);

assign cpq_din[151:0] = {
 cid_cpq_wdata[127], cid_cpq_wdata[63], cid_cpq_wdata[126], cid_cpq_wdata[62],
 cid_cpq_wdata[125], cid_cpq_wdata[61], cid_cpq_wdata[124], cid_cpq_wdata[60],
 cid_cpq_wdata[123], cid_cpq_wdata[59], cid_cpq_wdata[122], cid_cpq_wdata[58],
 cid_cpq_wdata[121], cid_cpq_wdata[57], cid_cpq_wdata[120], cid_cpq_wdata[56],
 cid_cpq_wdata[119], cid_cpq_wdata[55], cid_cpq_wdata[118], cid_cpq_wdata[54],
 cid_cpq_wdata[117], cid_cpq_wdata[53], cid_cpq_wdata[116], cid_cpq_wdata[52],
 cid_cpq_wdata[115], cid_cpq_wdata[51], cid_cpq_wdata[114], cid_cpq_wdata[50],
 cid_cpq_wdata[113], cid_cpq_wdata[49], cid_cpq_wdata[112], cid_cpq_wdata[48],
 cid_cpq_wdata[111], cid_cpq_wdata[47], cid_cpq_wdata[110], cid_cpq_wdata[46],
 cid_cpq_wdata[109], cid_cpq_wdata[45], cid_cpq_wdata[108], cid_cpq_wdata[44],
 cid_cpq_wdata[107], cid_cpq_wdata[43], cid_cpq_wdata[106], cid_cpq_wdata[42],
 cid_cpq_wdata[105], cid_cpq_wdata[41], cid_cpq_wdata[104], cid_cpq_wdata[40],
 cid_cpq_wdata[103], cid_cpq_wdata[39], cid_cpq_wdata[102], cid_cpq_wdata[38],
 cid_cpq_wdata[101], cid_cpq_wdata[37], cid_cpq_wdata[100], cid_cpq_wdata[36],
 cid_cpq_wdata[99],  cid_cpq_wdata[35], cid_cpq_wdata[98],  cid_cpq_wdata[34],
 cid_cpq_wdata[97],  cid_cpq_wdata[33], cid_cpq_wdata[96],  cid_cpq_wdata[32],
 cid_cpq_wdata[95],  cid_cpq_wdata[31], cid_cpq_wdata[94],  cid_cpq_wdata[30],
 cid_cpq_wdata[93],  cid_cpq_wdata[29], cid_cpq_wdata[92],  cid_cpq_wdata[28],
 cid_cpq_wdata[91],  cid_cpq_wdata[27], cid_cpq_wdata[90],  cid_cpq_wdata[26],
 cid_cpq_wdata[89],  cid_cpq_wdata[25], cid_cpq_wdata[88],  cid_cpq_wdata[24],
 cid_cpq_wdata[87],  cid_cpq_wdata[23], cid_cpq_wdata[86],  cid_cpq_wdata[22],
 cid_cpq_wdata[85],  cid_cpq_wdata[21], cid_cpq_wdata[84],  cid_cpq_wdata[20],
 cid_cpq_wdata[83],  cid_cpq_wdata[19], cid_cpq_wdata[82],  cid_cpq_wdata[18],
 cid_cpq_wdata[81],  cid_cpq_wdata[17], cid_cpq_wdata[80],  cid_cpq_wdata[16],
 cid_cpq_wdata[79],  cid_cpq_wdata[15], cid_cpq_wdata[78],  cid_cpq_wdata[14],
 cid_cpq_wdata[77],  cid_cpq_wdata[13], cid_cpq_wdata[76],  cid_cpq_wdata[12],
 cid_cpq_wdata[75],  cid_cpq_wdata[11], cid_cpq_wdata[74],  cid_cpq_wdata[10],
 cid_cpq_wdata[73],  cid_cpq_wdata[9], cid_cpq_wdata[72],  cid_cpq_wdata[8],
 cid_cpq_wdata[71],  cid_cpq_wdata[7], cid_cpq_wdata[70],  cid_cpq_wdata[6],
 cid_cpq_wdata[69],  cid_cpq_wdata[5], cid_cpq_wdata[68],  cid_cpq_wdata[4],
 cid_cpq_wdata[67],  cid_cpq_wdata[3], cid_cpq_wdata[66],  cid_cpq_wdata[2],
 cid_cpq_wdata[65],  cid_cpq_wdata[1], cid_cpq_wdata[64],  cid_cpq_wdata[0],
 2'b00,
 cid_cpq_wdata[128], cid_cpq_wdata[129], cid_cpq_wdata[130], cid_cpq_wdata[131], 
 cid_cpq_wdata[132], cid_cpq_wdata[133], cid_cpq_wdata[134], cid_cpq_wdata[135], 
 cid_cpq_wdata[136], cid_cpq_wdata[137], cid_cpq_wdata[138], cid_cpq_wdata[139], 
 cid_cpq_wdata[140], cid_cpq_wdata[141], cid_cpq_wdata[142], cid_cpq_wdata[143], 
 cid_cpq_wdata[144], cid_cpq_wdata[145], 4'b0
 };

assign {
 cpq_rdata[127], cpq_rdata[63], cpq_rdata[126], cpq_rdata[62],
 cpq_rdata[125], cpq_rdata[61], cpq_rdata[124], cpq_rdata[60],
 cpq_rdata[123], cpq_rdata[59], cpq_rdata[122], cpq_rdata[58],
 cpq_rdata[121], cpq_rdata[57], cpq_rdata[120], cpq_rdata[56],
 cpq_rdata[119], cpq_rdata[55], cpq_rdata[118], cpq_rdata[54],
 cpq_rdata[117], cpq_rdata[53], cpq_rdata[116], cpq_rdata[52],
 cpq_rdata[115], cpq_rdata[51], cpq_rdata[114], cpq_rdata[50],
 cpq_rdata[113], cpq_rdata[49], cpq_rdata[112], cpq_rdata[48],
 cpq_rdata[111], cpq_rdata[47], cpq_rdata[110], cpq_rdata[46],
 cpq_rdata[109], cpq_rdata[45], cpq_rdata[108], cpq_rdata[44],
 cpq_rdata[107], cpq_rdata[43], cpq_rdata[106], cpq_rdata[42],
 cpq_rdata[105], cpq_rdata[41], cpq_rdata[104], cpq_rdata[40],
 cpq_rdata[103], cpq_rdata[39], cpq_rdata[102], cpq_rdata[38],
 cpq_rdata[101], cpq_rdata[37], cpq_rdata[100], cpq_rdata[36],
 cpq_rdata[99],  cpq_rdata[35], cpq_rdata[98],  cpq_rdata[34],
 cpq_rdata[97],  cpq_rdata[33], cpq_rdata[96],  cpq_rdata[32],
 cpq_rdata[95],  cpq_rdata[31], cpq_rdata[94],  cpq_rdata[30],
 cpq_rdata[93],  cpq_rdata[29], cpq_rdata[92],  cpq_rdata[28],
 cpq_rdata[91],  cpq_rdata[27], cpq_rdata[90],  cpq_rdata[26],
 cpq_rdata[89],  cpq_rdata[25], cpq_rdata[88],  cpq_rdata[24],
 cpq_rdata[87],  cpq_rdata[23], cpq_rdata[86],  cpq_rdata[22],
 cpq_rdata[85],  cpq_rdata[21], cpq_rdata[84],  cpq_rdata[20],
 cpq_rdata[83],  cpq_rdata[19], cpq_rdata[82],  cpq_rdata[18],
 cpq_rdata[81],  cpq_rdata[17], cpq_rdata[80],  cpq_rdata[16],
 cpq_rdata[79],  cpq_rdata[15], cpq_rdata[78],  cpq_rdata[14],
 cpq_rdata[77],  cpq_rdata[13], cpq_rdata[76],  cpq_rdata[12],
 cpq_rdata[75],  cpq_rdata[11], cpq_rdata[74],  cpq_rdata[10],
 cpq_rdata[73],  cpq_rdata[9], cpq_rdata[72],  cpq_rdata[8],
 cpq_rdata[71],  cpq_rdata[7], cpq_rdata[70],  cpq_rdata[6],
 cpq_rdata[69],  cpq_rdata[5], cpq_rdata[68],  cpq_rdata[4],
 cpq_rdata[67],  cpq_rdata[3], cpq_rdata[66],  cpq_rdata[2],
 cpq_rdata[65],  cpq_rdata[1], cpq_rdata[64],  cpq_rdata[0],
 cpq_unused[1:0],
 cpq_rdata[128], cpq_rdata[129], cpq_rdata[130], cpq_rdata[131], 
 cpq_rdata[132], cpq_rdata[133], cpq_rdata[134], cpq_rdata[135], 
 cpq_rdata[136], cpq_rdata[137], cpq_rdata[138], cpq_rdata[139], 
 cpq_rdata[140], cpq_rdata[141], cpq_rdata[142], cpq_rdata[143], 
 cpq_rdata[144], cpq_rdata[145], cpq_unused[5:2]
} = cpq_dout[151:0];

lsu_cid_dp cid (
	.scan_in(cid_scanin),
	.scan_out(cid_scanout),
	.l2clk			(l2clk),
	.mbi_run		(cic_mbi_run),
  .cpq_rdata(cpq_rdata[145:0]),
  .cpx_spc_data_cx(cpx_spc_data_cx[145:0]),
  .cic_byp_sel(cic_byp_sel),
  .cic_d1_sel(cic_d1_sel),
  .cic_cpq_sel(cic_cpq_sel),
  .cic_fifo_sel(cic_fifo_sel),
  .cic_fifo_clken(cic_fifo_clken),
  .cid_fill_data_e(cid_fill_data_e[127:0]),
  .cid_l2miss(cid_l2miss),
  .cid_pkt_type(cid_pkt_type[4:0]),
  .cid_tid(cid_tid[2:0]),
  .cid_tid_unbuf(cid_tid_unbuf[2:0]),
  .cid_cpuid(cid_cpuid[2:0]),
  .cid_st_data_sel(cid_st_data_sel),
  .cid_xinval(cid_xinval),
  .cid_pref(cid_pref),
  .cid_err(cid_err[1:0]),
  .cid_xway(cid_xway[1:0]),
  .cid_st_addr(cid_st_addr[10:3]),
  .cid_st_vector(cid_st_vector[15:0]),
  .cid_st_bmask(cid_st_bmask[7:0]),
  .cid_st_way(cid_st_way[1:0]),
  .cid_inv_vec(cid_inv_vec[17:0]),
  .cid_inv_index(cid_inv_index[10:6]),
  .cid_ncache(cid_ncache),
  .cid_atomic(cid_atomic),
  .cid_atomic_unbuf(cid_atomic_unbuf),
  .cid_rmo_ack(cid_rmo_ack),
  .cid_set_inval(cid_set_inval),
  .cid_set_icinval(cid_set_icinval),
  .cid_cpq_wdata(cid_cpq_wdata[145:0]),
  .cid_dcsoc_err_e(cid_dcsoc_err_e),
  .cid_d1_rtntyp(cid_d1_rtntyp[4:0]),
  .cid_d1_tid(cid_d1_tid[2:0]),
  .cid_d1_cpuid(cid_d1_cpuid[2:0]),
  .cid_d1_wv(cid_d1_wv),
  .cid_d1_rmo(cid_d1_rmo),
  .cid_d1_pref(cid_d1_pref),
  .cid_d1_inval(cid_d1_inval[1:0]),
  .cid_cpq_cmp_1(cid_cpq_cmp_1),
  .cid_cpq_cmp_2(cid_cpq_cmp_2),
  .cid_cpq_cmp_3(cid_cpq_cmp_3),
  .lsu_cpx_data(lsu_cpx_data[127:0]),
  .lsu_cpx_cpkt(lsu_cpx_cpkt[17:0]),
  .lsu_cpx_valid(lsu_cpx_valid),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .const_cpuid(const_cpuid[2:0]),
  .mbi_wdata(mbi_wdata[7:0]),
  .bist_wdata_1(bist_wdata_1[7:0]),
  .bist_cmpsel_2(bist_cmpsel_2)
);

lsu_red_ctl red (
	.scan_in(red_scanin),
	.scan_out(red_scanout),
        .io_cmp_sync_en(slow_cmp_sync_en),
        .cmp_io_sync_en(cmp_slow_sync_en),
	.l2clk			(l2clk),
	.sram_hdr_read_data	({dca_fuse_repair_value[5:0],dca_fuse_repair_en}),
  .efu_spc_fuse_data(efu_spc_fuse_data),
  .efu_spc_fuse_dxfer_en(efu_spc_fuse_dxfer_en),
  .efu_spc_fuse_dclr(efu_spc_fuse_dclr),
  .spc_efu_fuse_ddata(spc_efu_fuse_ddata),
  .spc_efu_fuse_dxfer_en(spc_efu_fuse_dxfer_en),
  .hdr_sram_rvalue(hdr_sram_rvalue[6:0]),
  .hdr_sram_rid(hdr_sram_rid[1:0]),
  .hdr_sram_wr_en(hdr_sram_wr_en),
  .hdr_sram_red_clr(hdr_sram_red_clr),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

// Atomic ack should never have set inval bits on
// 0in custom -fire ((cpx_spc_data_cx[145:141] == 5'b10100) & cpx_spc_data_cx[129] & |(cpx_spc_data_cx[124:123])) -message "ATOMIC load rtn packet expects NC=1"

lsu_cic_ctl cic (
	.scan_in(cic_scanin),
	.scan_out(cic_scanout),
	.l2clk			(l2clk),
	.cpx_pkt_vld		(cpx_spc_data_cx[145]),
	.cid_tid		(cid_tid_unbuf[2:0]),
	.cid_atomic		(cid_atomic_unbuf),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .const_cpuid(const_cpuid[2:0]),
  .cid_d1_rtntyp(cid_d1_rtntyp[4:0]),
  .cid_d1_wv(cid_d1_wv),
  .cid_d1_tid(cid_d1_tid[2:0]),
  .cid_d1_rmo(cid_d1_rmo),
  .cid_d1_pref(cid_d1_pref),
  .cid_d1_cpuid(cid_d1_cpuid[2:0]),
  .cid_d1_inval(cid_d1_inval[1:0]),
  .cid_cpuid(cid_cpuid[2:0]),
  .cid_pkt_type(cid_pkt_type[4:0]),
  .cid_xinval(cid_xinval),
  .cid_pref(cid_pref),
  .cid_inv_vec(cid_inv_vec[17:0]),
  .cid_rmo_ack(cid_rmo_ack),
  .cid_set_inval(cid_set_inval),
  .cid_set_icinval(cid_set_icinval),
  .cid_st_addr(cid_st_addr[5:4]),
  .cid_st_vector(cid_st_vector[15:0]),
  .cid_cpq_cmp_1(cid_cpq_cmp_1),
  .cid_cpq_cmp_2(cid_cpq_cmp_2),
  .cid_cpq_cmp_3(cid_cpq_cmp_3),
  .dcc_cache_diag_wr_b(dcc_cache_diag_wr_b),
  .dec_ld_inst_d(dec_ld_inst_d),
  .fgu_fdiv_stall(fgu_fdiv_stall),
  .lmc_ldd_vld(lmc_ldd_vld[7:0]),
  .sbc_bst_sel(sbc_bst_sel[7:0]),
  .mbi_run(mbi_run),
  .mbi_cpq_read_en(mbi_cpq_read_en),
  .mbi_cpq_write_en(mbi_cpq_write_en),
  .mbi_addr(mbi_addr[4:0]),
  .lbist_run(lbist_run),
  .cic_cpq_wptr(cic_cpq_wptr[4:0]),
  .cic_cpq_rptr(cic_cpq_rptr[4:0]),
  .cic_cpq_rd_en(cic_cpq_rd_en),
  .cic_cpq_wr_en(cic_cpq_wr_en),
  .cic_d1_sel(cic_d1_sel),
  .cic_cpq_sel(cic_cpq_sel),
  .cic_fifo_sel(cic_fifo_sel),
  .cic_byp_sel(cic_byp_sel),
  .cic_fifo_clken(cic_fifo_clken),
  .cic_l2fill_vld_e(cic_l2fill_vld_e),
  .cic_cpq_ld_rdy(cic_cpq_ld_rdy),
  .cic_cpq_ld_rdy_(cic_cpq_ld_rdy_),
  .cic_cpq_ld_sel(cic_cpq_ld_sel),
  .cic_div_stall_d(cic_div_stall_d),
  .cic_st_update_e(cic_st_update_e),
  .cic_rtn_cmplt(cic_rtn_cmplt),
  .cic_invalidate_e(cic_invalidate_e),
  .cic_xinval_e(cic_xinval_e),
  .cic_set_inval(cic_set_inval),
  .cic_xinval(cic_xinval[7:0]),
  .cic_oddrd_e(cic_oddrd_e),
  .cic_st_dequeue(cic_st_dequeue[7:0]),
  .cic_rmo_dequeue(cic_rmo_dequeue[7:0]),
  .cic_st_ack(cic_st_ack[7:0]),
  .cic_inv_wen_e(cic_inv_wen_e[15:0]),
  .cic_cpq_stall(cic_cpq_stall),
  .cic_diag_data_sel_e(cic_diag_data_sel_e),
  .cic_ext_interrupt(cic_ext_interrupt),
  .lsu_dcsoc_err_g(lsu_dcsoc_err_g),
  .lsu_ext_interrupt(lsu_ext_interrupt),
  .cic_mbi_run(cic_mbi_run),
  .lsu_mbi_cpq_fail(lsu_mbi_cpq_fail)
);

lsu_asc_ctl asc (
	.scan_in(asc_scanin),
	.scan_out(asc_scanout),
	.l2clk		(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .asd_p2a_vld(asd_p2a_vld),
  .asd_p2a_fast(asd_p2a_fast),
  .asd_ring_ctl(asd_ring_ctl[63:56]),
  .asd_ring_asi(asd_ring_asi[7:0]),
  .asd_ring_addr(asd_ring_addr[8:3]),
  .lsu_asi_clken(lsu_asi_clken),
  .sbc_pid_kill_store_p4_(sbc_pid_kill_store_p4_),
  .pic_st_asi_p4(pic_st_asi_p4),
  .asc_ring_ctl(asc_ring_ctl),
  .asc_ring_data(asc_ring_data),
  .asc_ring_local(asc_ring_local),
  .asc_ring_fast(asc_ring_fast),
  .asc_wr_p0ctxt(asc_wr_p0ctxt[7:0]),
  .asc_wr_p1ctxt(asc_wr_p1ctxt[7:0]),
  .asc_wr_s0ctxt(asc_wr_s0ctxt[7:0]),
  .asc_wr_s1ctxt(asc_wr_s1ctxt[7:0]),
  .asc_wr_pid(asc_wr_pid[7:0]),
  .asc_wrasi(asc_wrasi[7:0]),
  .asc_pid_ack(asc_pid_ack),
  .lsu_ring_ctl(lsu_ring_ctl),
  .lsu_ifu_tid_w(lsu_ifu_tid_w[2:0]),
  .lsu_ifu_wr_p0ctxt(lsu_ifu_wr_p0ctxt),
  .lsu_ifu_wr_p1ctxt(lsu_ifu_wr_p1ctxt),
  .lsu_ifu_wr_pid(lsu_ifu_wr_pid)
);

lsu_asd_dp asd (
.scan_in(asd_scanin),
.scan_out(asd_scanout),
.l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .pid_asi_pkt(pid_asi_pkt[127:0]),
  .asc_ring_ctl(asc_ring_ctl),
  .asc_ring_data(asc_ring_data),
  .asc_ring_local(asc_ring_local),
  .asc_ring_fast(asc_ring_fast),
  .lsu_asi_clken(lsu_asi_clken),
  .lsu_ring_ctl(lsu_ring_ctl),
  .asd_p2a_vld(asd_p2a_vld),
  .asd_p2a_fast(asd_p2a_fast),
  .lsu_rngf_cdbus(lsu_rngf_cdbus[64:0]),
  .lsu_rngl_cdbus(lsu_rngl_cdbus[64:0]),
  .lsu_ifu_ctxt_data(lsu_ifu_ctxt_data[12:0]),
  .asd_ring_ctl(asd_ring_ctl[63:56]),
  .asd_ring_asi(asd_ring_asi[7:0]),
  .asd_ring_addr(asd_ring_addr[8:3])
);

lsu_pid_dp pid (
	.scan_in(pid_scanin),
	.scan_out(pid_scanout),
	.l2clk		(l2clk),
	.stb_ram_data	(stb_ram_data_corr[63:0]),
	.stb_cam_data	(stb_cam_data_rep0[44:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .const_cpuid(const_cpuid[2:0]),
  .lmd_bypass_data_m(lmd_bypass_data_m[63:0]),
  .lmc_ld_tid(lmc_ld_tid[2:0]),
  .lmc_ld_sz(lmc_ld_sz[4:0]),
  .lmd_pcx_rqtyp(lmd_pcx_rqtyp[2:0]),
  .lmd_pcx_nc(lmd_pcx_nc),
  .lmd_pcx_pref(lmd_pcx_pref),
  .lmd_pcx_rway(lmd_pcx_rway[1:0]),
  .lmd_pcx_addr(lmd_pcx_addr[39:0]),
  .lmd_asi_rngf(lmd_asi_rngf),
  .lmd_asi_type(lmd_asi_type[1:0]),
  .lmd_asi_asi(lmd_asi_asi[7:0]),
  .lmc_ld_vld_p4(lmc_ld_vld_p4),
  .lmc_ld_inv_p4(lmc_ld_inv_p4),
  .sbc_st_sel_tid_p4(sbc_st_sel_tid_p4[2:0]),
  .sbc_st_pcx_nc(sbc_st_pcx_nc),
  .sbc_st_asi_fs(sbc_st_asi_fs),
  .sbc_pcx_bmask(sbc_pcx_bmask[7:0]),
  .sbc_pcx_addr(sbc_pcx_addr[2:0]),
  .sbc_pcx_rmo_st(sbc_pcx_rmo_st),
  .sbc_pcx_blk_st(sbc_pcx_blk_st),
  .sbc_pid_kill_store_p4_(sbc_pid_kill_store_p4_),
  .sbc_force_inv(sbc_force_inv),
  .sbc_st_type_p4(sbc_st_type_p4[2:0]),
  .pic_ld_pcx_sel_p4(pic_ld_pcx_sel_p4),
  .pic_st_pcx_sel_p4(pic_st_pcx_sel_p4),
  .pic_st_asi_p4(pic_st_asi_p4),
  .pic_ld_asi_p4(pic_ld_asi_p4),
  .pic_asi_sel_p4(pic_asi_sel_p4),
  .pic_asi_req(pic_asi_req),
  .spc_pcx_data_pa(spc_pcx_data_pa[129:0]),
  .pid_asi_pkt(pid_asi_pkt[127:0])
);

lsu_sbs_ctl sbs0 (
	.scan_in(sbs0_scanin),
	.scan_out(sbs0_scanout),
	.l2clk(l2clk),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep00),
	.sbc_cam_wvld_m		(sbc_cam_wvld_m[0]),
	.sbc_st_sel_p3		(sbc_st_sel_p3[0]),
	.sbc_bst_b		(lsu_block_store_b[0]),
	.cic_st_ack		(cic_st_ack[0]),
	.cic_st_dequeue		(cic_st_dequeue[0]),
	.cic_rmo_dequeue	(cic_rmo_dequeue[0]),
	.dcc_sync_inst_w	(dcc_sync_inst_w[0]),
	.dcc_asi_rtn_vld	(dcc_asi_rtn_vld[0]),
	.sbs_stb_wptr_m		(sbs0_stb_wptr_m[2:0]),
	.sbs_stb_rptr		(sbs0_stb_rptr[2:0]),
	.sbs_state_vld		(sbs0_state_vld[7:0]),
	.sbs_state_ced		(sbs0_state_ced[7:0]),
	.sbs_state_asi_rngf	(sbs_state_asi_rngf[0]),
	.sbs_pcx_pst_ie_p4	(sbs_pcx_pst_ie_p4[0]),
	.sbs_all_commited	(sbs_all_commited[0]),
	.sbs_stb_empty		(sbs_stb_empty[0]),
	.lsu_stb_empty		(lsu_stb_empty[0]),
	.sbs_stb_full		(sbs_stb_full[0]),
	.sbs_bst_req		(sbs_bst_req[0]),
	.sbc_bst_sel		(sbc_bst_sel[0]),
	.sbc_st_addr_new	(sbc_st_addr_new[0]),
	.sbs_asi_indet_req	(sbs_asi_indet_req[0]),
	.sbs_asi_indet_retire	(sbs_asi_indet_retire[0]),
	.sbs_sync		(lsu_trap_flush[0]),
	.sbs_rmo_st_p4		(sbs_rmo_st_p4[0]),
	.sbs_blk_st_p4		(sbs_blk_st_p4[0]),
	.sbs_st_type		(sbs0_st_type[1:0]),
	.lsu_stb_alloc		(lsu_stb_alloc[0]),
	.lsu_stb_dealloc	(lsu_stb_dealloc[0]),
	.lsu_block_store_kill	(lsu_block_store_kill[0]),
	.sbs_asi_rq_vld		(sbs_asi_rq_vld[0]),
	.sbs_atm_rq_vld		(sbs_atm_rq_vld[0]),
	.sbs_pcx_rq_vld		(sbs_pcx_rq_vld[0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .spd_st_line_match(spd_st_line_match),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .pic_st_sel_p3(pic_st_sel_p3),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_lsu_pmen_(lsu_lsu_pmen_)
);

lsu_sbs_ctl sbs1 (
	.scan_in(sbs1_scanin),
	.scan_out(sbs1_scanout),
	.l2clk(l2clk),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep00),
	.sbc_cam_wvld_m		(sbc_cam_wvld_m[1]),
	.sbc_st_sel_p3		(sbc_st_sel_p3[1]),
	.sbc_bst_b		(lsu_block_store_b[1]),
	.cic_st_ack		(cic_st_ack[1]),
	.cic_st_dequeue		(cic_st_dequeue[1]),
	.cic_rmo_dequeue	(cic_rmo_dequeue[1]),
	.dcc_sync_inst_w	(dcc_sync_inst_w[1]),
	.dcc_asi_rtn_vld	(dcc_asi_rtn_vld[1]),
	.sbs_stb_wptr_m		(sbs1_stb_wptr_m[2:0]),
	.sbs_stb_rptr		(sbs1_stb_rptr[2:0]),
	.sbs_state_vld		(sbs1_state_vld[7:0]),
	.sbs_state_ced		(sbs1_state_ced[7:0]),
	.sbs_state_asi_rngf	(sbs_state_asi_rngf[1]),
	.sbs_pcx_pst_ie_p4	(sbs_pcx_pst_ie_p4[1]),
	.sbs_all_commited	(sbs_all_commited[1]),
	.sbs_stb_empty		(sbs_stb_empty[1]),
	.lsu_stb_empty		(lsu_stb_empty[1]),
	.sbs_stb_full		(sbs_stb_full[1]),
	.sbs_bst_req		(sbs_bst_req[1]),
	.sbc_bst_sel		(sbc_bst_sel[1]),
	.sbc_st_addr_new	(sbc_st_addr_new[1]),
	.sbs_asi_indet_req	(sbs_asi_indet_req[1]),
	.sbs_asi_indet_retire	(sbs_asi_indet_retire[1]),
	.sbs_sync		(lsu_trap_flush[1]),
	.sbs_rmo_st_p4		(sbs_rmo_st_p4[1]),
	.sbs_blk_st_p4		(sbs_blk_st_p4[1]),
	.sbs_st_type		(sbs1_st_type[1:0]),
	.lsu_stb_alloc		(lsu_stb_alloc[1]),
	.lsu_stb_dealloc	(lsu_stb_dealloc[1]),
	.lsu_block_store_kill	(lsu_block_store_kill[1]),
	.sbs_asi_rq_vld		(sbs_asi_rq_vld[1]),
	.sbs_atm_rq_vld		(sbs_atm_rq_vld[1]),
	.sbs_pcx_rq_vld		(sbs_pcx_rq_vld[1]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .spd_st_line_match(spd_st_line_match),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .pic_st_sel_p3(pic_st_sel_p3),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_lsu_pmen_(lsu_lsu_pmen_)
);

lsu_sbs_ctl sbs2 (
	.scan_in(sbs2_scanin),
	.scan_out(sbs2_scanout),
	.l2clk(l2clk),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep00),
	.sbc_cam_wvld_m		(sbc_cam_wvld_m[2]),
	.sbc_st_sel_p3		(sbc_st_sel_p3[2]),
	.sbc_bst_b		(lsu_block_store_b[2]),
	.cic_st_ack		(cic_st_ack[2]),
	.cic_st_dequeue		(cic_st_dequeue[2]),
	.cic_rmo_dequeue	(cic_rmo_dequeue[2]),
	.dcc_sync_inst_w	(dcc_sync_inst_w[2]),
	.dcc_asi_rtn_vld	(dcc_asi_rtn_vld[2]),
	.sbs_stb_wptr_m		(sbs2_stb_wptr_m[2:0]),
	.sbs_stb_rptr		(sbs2_stb_rptr[2:0]),
	.sbs_state_vld		(sbs2_state_vld[7:0]),
	.sbs_state_ced		(sbs2_state_ced[7:0]),
	.sbs_state_asi_rngf	(sbs_state_asi_rngf[2]),
	.sbs_pcx_pst_ie_p4	(sbs_pcx_pst_ie_p4[2]),
	.sbs_all_commited	(sbs_all_commited[2]),
	.sbs_stb_empty		(sbs_stb_empty[2]),
	.lsu_stb_empty		(lsu_stb_empty[2]),
	.sbs_stb_full		(sbs_stb_full[2]),
	.sbs_bst_req		(sbs_bst_req[2]),
	.sbc_bst_sel		(sbc_bst_sel[2]),
	.sbc_st_addr_new	(sbc_st_addr_new[2]),
	.sbs_asi_indet_req	(sbs_asi_indet_req[2]),
	.sbs_asi_indet_retire	(sbs_asi_indet_retire[2]),
	.sbs_sync		(lsu_trap_flush[2]),
	.sbs_rmo_st_p4		(sbs_rmo_st_p4[2]),
	.sbs_blk_st_p4		(sbs_blk_st_p4[2]),
	.sbs_st_type		(sbs2_st_type[1:0]),
	.lsu_stb_alloc		(lsu_stb_alloc[2]),
	.lsu_stb_dealloc	(lsu_stb_dealloc[2]),
	.lsu_block_store_kill	(lsu_block_store_kill[2]),
	.sbs_asi_rq_vld		(sbs_asi_rq_vld[2]),
	.sbs_atm_rq_vld		(sbs_atm_rq_vld[2]),
	.sbs_pcx_rq_vld		(sbs_pcx_rq_vld[2]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .spd_st_line_match(spd_st_line_match),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .pic_st_sel_p3(pic_st_sel_p3),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_lsu_pmen_(lsu_lsu_pmen_)
);

lsu_sbs_ctl sbs3 (
	.scan_in(sbs3_scanin),
	.scan_out(sbs3_scanout),
	.l2clk(l2clk),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep00),
	.sbc_cam_wvld_m		(sbc_cam_wvld_m[3]),
	.sbc_st_sel_p3		(sbc_st_sel_p3[3]),
	.sbc_bst_b		(lsu_block_store_b[3]),
	.cic_st_ack		(cic_st_ack[3]),
	.cic_st_dequeue		(cic_st_dequeue[3]),
	.cic_rmo_dequeue	(cic_rmo_dequeue[3]),
	.dcc_sync_inst_w	(dcc_sync_inst_w[3]),
	.dcc_asi_rtn_vld	(dcc_asi_rtn_vld[3]),
	.sbs_stb_wptr_m		(sbs3_stb_wptr_m[2:0]),
	.sbs_stb_rptr		(sbs3_stb_rptr[2:0]),
	.sbs_state_vld		(sbs3_state_vld[7:0]),
	.sbs_state_ced		(sbs3_state_ced[7:0]),
	.sbs_state_asi_rngf	(sbs_state_asi_rngf[3]),
	.sbs_pcx_pst_ie_p4	(sbs_pcx_pst_ie_p4[3]),
	.sbs_all_commited	(sbs_all_commited[3]),
	.sbs_stb_empty		(sbs_stb_empty[3]),
	.lsu_stb_empty		(lsu_stb_empty[3]),
	.sbs_stb_full		(sbs_stb_full[3]),
	.sbs_bst_req		(sbs_bst_req[3]),
	.sbc_bst_sel		(sbc_bst_sel[3]),
	.sbc_st_addr_new	(sbc_st_addr_new[3]),
	.sbs_asi_indet_req	(sbs_asi_indet_req[3]),
	.sbs_asi_indet_retire	(sbs_asi_indet_retire[3]),
	.sbs_sync		(lsu_trap_flush[3]),
	.sbs_rmo_st_p4		(sbs_rmo_st_p4[3]),
	.sbs_blk_st_p4		(sbs_blk_st_p4[3]),
	.sbs_st_type		(sbs3_st_type[1:0]),
	.lsu_stb_alloc		(lsu_stb_alloc[3]),
	.lsu_stb_dealloc	(lsu_stb_dealloc[3]),
	.lsu_block_store_kill	(lsu_block_store_kill[3]),
	.sbs_asi_rq_vld		(sbs_asi_rq_vld[3]),
	.sbs_atm_rq_vld		(sbs_atm_rq_vld[3]),
	.sbs_pcx_rq_vld		(sbs_pcx_rq_vld[3]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .spd_st_line_match(spd_st_line_match),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .pic_st_sel_p3(pic_st_sel_p3),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_lsu_pmen_(lsu_lsu_pmen_)
);

lsu_sbs_ctl sbs4 (
	.scan_in(sbs4_scanin),
	.scan_out(sbs4_scanout),
	.l2clk(l2clk),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep00),
	.sbc_cam_wvld_m		(sbc_cam_wvld_m[4]),
	.sbc_st_sel_p3		(sbc_st_sel_p3[4]),
	.sbc_bst_b		(lsu_block_store_b[4]),
	.cic_st_ack		(cic_st_ack[4]),
	.cic_st_dequeue		(cic_st_dequeue[4]),
	.cic_rmo_dequeue	(cic_rmo_dequeue[4]),
	.dcc_sync_inst_w	(dcc_sync_inst_w[4]),
	.dcc_asi_rtn_vld	(dcc_asi_rtn_vld[4]),
	.sbs_stb_wptr_m		(sbs4_stb_wptr_m[2:0]),
	.sbs_stb_rptr		(sbs4_stb_rptr[2:0]),
	.sbs_state_vld		(sbs4_state_vld[7:0]),
	.sbs_state_ced		(sbs4_state_ced[7:0]),
	.sbs_state_asi_rngf	(sbs_state_asi_rngf[4]),
	.sbs_pcx_pst_ie_p4	(sbs_pcx_pst_ie_p4[4]),
	.sbs_all_commited	(sbs_all_commited[4]),
	.sbs_stb_empty		(sbs_stb_empty[4]),
	.lsu_stb_empty		(lsu_stb_empty[4]),
	.sbs_stb_full		(sbs_stb_full[4]),
	.sbs_bst_req		(sbs_bst_req[4]),
	.sbc_bst_sel		(sbc_bst_sel[4]),
	.sbc_st_addr_new	(sbc_st_addr_new[4]),
	.sbs_asi_indet_req	(sbs_asi_indet_req[4]),
	.sbs_asi_indet_retire	(sbs_asi_indet_retire[4]),
	.sbs_sync		(lsu_trap_flush[4]),
	.sbs_rmo_st_p4		(sbs_rmo_st_p4[4]),
	.sbs_blk_st_p4		(sbs_blk_st_p4[4]),
	.sbs_st_type		(sbs4_st_type[1:0]),
	.lsu_stb_alloc		(lsu_stb_alloc[4]),
	.lsu_stb_dealloc	(lsu_stb_dealloc[4]),
	.lsu_block_store_kill	(lsu_block_store_kill[4]),
	.sbs_asi_rq_vld		(sbs_asi_rq_vld[4]),
	.sbs_atm_rq_vld		(sbs_atm_rq_vld[4]),
	.sbs_pcx_rq_vld		(sbs_pcx_rq_vld[4]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .spd_st_line_match(spd_st_line_match),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .pic_st_sel_p3(pic_st_sel_p3),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_lsu_pmen_(lsu_lsu_pmen_)
);

lsu_sbs_ctl sbs5 (
	.scan_in(sbs5_scanin),
	.scan_out(sbs5_scanout),
	.l2clk(l2clk),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep00),
	.sbc_cam_wvld_m		(sbc_cam_wvld_m[5]),
	.sbc_st_sel_p3		(sbc_st_sel_p3[5]),
	.sbc_bst_b		(lsu_block_store_b[5]),
	.cic_st_ack		(cic_st_ack[5]),
	.cic_st_dequeue		(cic_st_dequeue[5]),
	.cic_rmo_dequeue	(cic_rmo_dequeue[5]),
	.dcc_sync_inst_w	(dcc_sync_inst_w[5]),
	.dcc_asi_rtn_vld	(dcc_asi_rtn_vld[5]),
	.sbs_stb_wptr_m		(sbs5_stb_wptr_m[2:0]),
	.sbs_stb_rptr		(sbs5_stb_rptr[2:0]),
	.sbs_state_vld		(sbs5_state_vld[7:0]),
	.sbs_state_ced		(sbs5_state_ced[7:0]),
	.sbs_state_asi_rngf	(sbs_state_asi_rngf[5]),
	.sbs_pcx_pst_ie_p4	(sbs_pcx_pst_ie_p4[5]),
	.sbs_all_commited	(sbs_all_commited[5]),
	.sbs_stb_empty		(sbs_stb_empty[5]),
	.lsu_stb_empty		(lsu_stb_empty[5]),
	.sbs_stb_full		(sbs_stb_full[5]),
	.sbs_bst_req		(sbs_bst_req[5]),
	.sbc_bst_sel		(sbc_bst_sel[5]),
	.sbc_st_addr_new	(sbc_st_addr_new[5]),
	.sbs_asi_indet_req	(sbs_asi_indet_req[5]),
	.sbs_asi_indet_retire	(sbs_asi_indet_retire[5]),
	.sbs_sync		(lsu_trap_flush[5]),
	.sbs_rmo_st_p4		(sbs_rmo_st_p4[5]),
	.sbs_blk_st_p4		(sbs_blk_st_p4[5]),
	.sbs_st_type		(sbs5_st_type[1:0]),
	.lsu_stb_alloc		(lsu_stb_alloc[5]),
	.lsu_stb_dealloc	(lsu_stb_dealloc[5]),
	.lsu_block_store_kill	(lsu_block_store_kill[5]),
	.sbs_asi_rq_vld		(sbs_asi_rq_vld[5]),
	.sbs_atm_rq_vld		(sbs_atm_rq_vld[5]),
	.sbs_pcx_rq_vld		(sbs_pcx_rq_vld[5]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .spd_st_line_match(spd_st_line_match),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .pic_st_sel_p3(pic_st_sel_p3),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_lsu_pmen_(lsu_lsu_pmen_)
);

lsu_sbs_ctl sbs6 (
	.scan_in(sbs6_scanin),
	.scan_out(sbs6_scanout),
	.l2clk(l2clk),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep00),
	.sbc_cam_wvld_m		(sbc_cam_wvld_m[6]),
	.sbc_st_sel_p3		(sbc_st_sel_p3[6]),
	.sbc_bst_b		(lsu_block_store_b[6]),
	.cic_st_ack		(cic_st_ack[6]),
	.cic_st_dequeue		(cic_st_dequeue[6]),
	.cic_rmo_dequeue	(cic_rmo_dequeue[6]),
	.dcc_sync_inst_w	(dcc_sync_inst_w[6]),
	.dcc_asi_rtn_vld	(dcc_asi_rtn_vld[6]),
	.sbs_stb_wptr_m		(sbs6_stb_wptr_m[2:0]),
	.sbs_stb_rptr		(sbs6_stb_rptr[2:0]),
	.sbs_state_vld		(sbs6_state_vld[7:0]),
	.sbs_state_ced		(sbs6_state_ced[7:0]),
	.sbs_state_asi_rngf	(sbs_state_asi_rngf[6]),
	.sbs_pcx_pst_ie_p4	(sbs_pcx_pst_ie_p4[6]),
	.sbs_all_commited	(sbs_all_commited[6]),
	.sbs_stb_empty		(sbs_stb_empty[6]),
	.lsu_stb_empty		(lsu_stb_empty[6]),
	.sbs_stb_full		(sbs_stb_full[6]),
	.sbs_bst_req		(sbs_bst_req[6]),
	.sbc_bst_sel		(sbc_bst_sel[6]),
	.sbc_st_addr_new	(sbc_st_addr_new[6]),
	.sbs_asi_indet_req	(sbs_asi_indet_req[6]),
	.sbs_asi_indet_retire	(sbs_asi_indet_retire[6]),
	.sbs_sync		(lsu_trap_flush[6]),
	.sbs_rmo_st_p4		(sbs_rmo_st_p4[6]),
	.sbs_blk_st_p4		(sbs_blk_st_p4[6]),
	.sbs_st_type		(sbs6_st_type[1:0]),
	.lsu_stb_alloc		(lsu_stb_alloc[6]),
	.lsu_stb_dealloc	(lsu_stb_dealloc[6]),
	.lsu_block_store_kill	(lsu_block_store_kill[6]),
	.sbs_asi_rq_vld		(sbs_asi_rq_vld[6]),
	.sbs_atm_rq_vld		(sbs_atm_rq_vld[6]),
	.sbs_pcx_rq_vld		(sbs_pcx_rq_vld[6]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .spd_st_line_match(spd_st_line_match),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .pic_st_sel_p3(pic_st_sel_p3),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_lsu_pmen_(lsu_lsu_pmen_)
);

lsu_sbs_ctl sbs7 (
	.scan_in(sbs7_scanin),
	.scan_out(sbs7_scanout),
	.l2clk(l2clk),
	.tlb_tte_ie_b		(tlb_tte_ie_b_rep00),
	.sbc_cam_wvld_m		(sbc_cam_wvld_m[7]),
	.sbc_st_sel_p3		(sbc_st_sel_p3[7]),
	.sbc_bst_b		(lsu_block_store_b[7]),
	.cic_st_ack		(cic_st_ack[7]),
	.cic_st_dequeue		(cic_st_dequeue[7]),
	.cic_rmo_dequeue	(cic_rmo_dequeue[7]),
	.dcc_sync_inst_w	(dcc_sync_inst_w[7]),
	.dcc_asi_rtn_vld	(dcc_asi_rtn_vld[7]),
	.sbs_stb_wptr_m		(sbs7_stb_wptr_m[2:0]),
	.sbs_stb_rptr		(sbs7_stb_rptr[2:0]),
	.sbs_state_vld		(sbs7_state_vld[7:0]),
	.sbs_state_ced		(sbs7_state_ced[7:0]),
	.sbs_state_asi_rngf	(sbs_state_asi_rngf[7]),
	.sbs_pcx_pst_ie_p4	(sbs_pcx_pst_ie_p4[7]),
	.sbs_all_commited	(sbs_all_commited[7]),
	.sbs_stb_empty		(sbs_stb_empty[7]),
	.lsu_stb_empty		(lsu_stb_empty[7]),
	.sbs_stb_full		(sbs_stb_full[7]),
	.sbs_bst_req		(sbs_bst_req[7]),
	.sbc_bst_sel		(sbc_bst_sel[7]),
	.sbc_st_addr_new	(sbc_st_addr_new[7]),
	.sbs_asi_indet_req	(sbs_asi_indet_req[7]),
	.sbs_asi_indet_retire	(sbs_asi_indet_retire[7]),
	.sbs_sync		(lsu_trap_flush[7]),
	.sbs_rmo_st_p4		(sbs_rmo_st_p4[7]),
	.sbs_blk_st_p4		(sbs_blk_st_p4[7]),
	.sbs_st_type		(sbs7_st_type[1:0]),
	.lsu_stb_alloc		(lsu_stb_alloc[7]),
	.lsu_stb_dealloc	(lsu_stb_dealloc[7]),
	.lsu_block_store_kill	(lsu_block_store_kill[7]),
	.sbs_asi_rq_vld		(sbs_asi_rq_vld[7]),
	.sbs_atm_rq_vld		(sbs_atm_rq_vld[7]),
	.sbs_pcx_rq_vld		(sbs_pcx_rq_vld[7]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .spd_st_line_match(spd_st_line_match),
  .dcc_asi_store_b(dcc_asi_store_b),
  .dcc_asi_iomap_b(dcc_asi_iomap_b),
  .dcc_asi_rngf_b(dcc_asi_rngf_b),
  .dcc_asi_indet_b(dcc_asi_indet_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_pst_asi_b(dcc_pst_asi_b),
  .dcc_st_rq_type_w(dcc_st_rq_type_w[1:0]),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .pic_st_sel_p3(pic_st_sel_p3),
  .dcc_asi_rtn_excp(dcc_asi_rtn_excp),
  .dcc_asi_rtn_rd(dcc_asi_rtn_rd),
  .lsu_lsu_pmen_(lsu_lsu_pmen_)
);

lsu_sbc_ctl sbc (
	.scan_in(sbc_scanin),
	.scan_out(sbc_scanout),
	.l2clk		(l2clk),
	.tlb_pgnum_b39			(tlb_pgnum[39]),
	.tlb_tte_ie_b			(tlb_tte_ie_b_rep00),
	.stb_cam_hit			(stb_cam_hit_rep0),
	.lsu_asi_error_inject_b17	(lsu_asi_error_inject[17]),
	.lsu_asi_error_inject_b19	(lsu_asi_error_inject[19]),
	.lsu_asi_error_inject_b31	(lsu_asi_error_inject[31]),
	.stb_cam_addr_b39		(stb_cam_data_rep0[44]),
	.stb_cam_data			(stb_cam_data_rep0[7:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .dec_st_inst_e(dec_st_inst_e),
  .dec_fpldst_inst_e(dec_fpldst_inst_e),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .dec_frf_r2_addr_e(dec_frf_r2_addr_e[4:3]),
  .dcc_lendian_pre_m(dcc_lendian_pre_m),
  .dcc_tte_vld_m(dcc_tte_vld_m),
  .dcc_ldst_sz_m(dcc_ldst_sz_m[1:0]),
  .dcc_tid_e(dcc_tid_e[2:0]),
  .dcc_blk_inst_m(dcc_blk_inst_m),
  .dcc_std_inst_m(dcc_std_inst_m),
  .dcc_asi_load_m(dcc_asi_load_m),
  .dcc_binit_st_b(dcc_binit_st_b),
  .dcc_casa_inst_b(dcc_casa_inst_b),
  .dcc_exception_flush_b(dcc_exception_flush_b),
  .dcc_priv_b(dcc_priv_b),
  .dcc_hpriv_b(dcc_hpriv_b),
  .dcc_stb_diag_rd_m(dcc_stb_diag_rd_m),
  .dcc_wr_error_inj_m(dcc_wr_error_inj_m),
  .dcc_sync_pipe_w(dcc_sync_pipe_w),
  .lsu_va_b(lsu_va_b[5:3]),
  .lsu_asi_error_inject(lsu_asi_error_inject[6:0]),
  .lsu_lsu_pmen(lsu_lsu_pmen),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .tlu_cerer_sbdpc(tlu_cerer_sbdpc),
  .tlu_cerer_sbdpu(tlu_cerer_sbdpu),
  .tlu_cerer_sbapp(tlu_cerer_sbapp),
  .tlu_cerer_sbdiou(tlu_cerer_sbdiou),
  .sbs0_stb_wptr_m(sbs0_stb_wptr_m[2:0]),
  .sbs1_stb_wptr_m(sbs1_stb_wptr_m[2:0]),
  .sbs2_stb_wptr_m(sbs2_stb_wptr_m[2:0]),
  .sbs3_stb_wptr_m(sbs3_stb_wptr_m[2:0]),
  .sbs4_stb_wptr_m(sbs4_stb_wptr_m[2:0]),
  .sbs5_stb_wptr_m(sbs5_stb_wptr_m[2:0]),
  .sbs6_stb_wptr_m(sbs6_stb_wptr_m[2:0]),
  .sbs7_stb_wptr_m(sbs7_stb_wptr_m[2:0]),
  .sbs0_stb_rptr(sbs0_stb_rptr[2:0]),
  .sbs1_stb_rptr(sbs1_stb_rptr[2:0]),
  .sbs2_stb_rptr(sbs2_stb_rptr[2:0]),
  .sbs3_stb_rptr(sbs3_stb_rptr[2:0]),
  .sbs4_stb_rptr(sbs4_stb_rptr[2:0]),
  .sbs5_stb_rptr(sbs5_stb_rptr[2:0]),
  .sbs6_stb_rptr(sbs6_stb_rptr[2:0]),
  .sbs7_stb_rptr(sbs7_stb_rptr[2:0]),
  .sbs_pcx_rq_vld(sbs_pcx_rq_vld[7:0]),
  .sbs_atm_rq_vld(sbs_atm_rq_vld[7:0]),
  .sbs_asi_rq_vld(sbs_asi_rq_vld[7:0]),
  .sbs0_state_vld(sbs0_state_vld[7:0]),
  .sbs1_state_vld(sbs1_state_vld[7:0]),
  .sbs2_state_vld(sbs2_state_vld[7:0]),
  .sbs3_state_vld(sbs3_state_vld[7:0]),
  .sbs4_state_vld(sbs4_state_vld[7:0]),
  .sbs5_state_vld(sbs5_state_vld[7:0]),
  .sbs6_state_vld(sbs6_state_vld[7:0]),
  .sbs7_state_vld(sbs7_state_vld[7:0]),
  .sbs0_state_ced(sbs0_state_ced[7:0]),
  .sbs1_state_ced(sbs1_state_ced[7:0]),
  .sbs2_state_ced(sbs2_state_ced[7:0]),
  .sbs3_state_ced(sbs3_state_ced[7:0]),
  .sbs4_state_ced(sbs4_state_ced[7:0]),
  .sbs5_state_ced(sbs5_state_ced[7:0]),
  .sbs6_state_ced(sbs6_state_ced[7:0]),
  .sbs7_state_ced(sbs7_state_ced[7:0]),
  .sbs0_st_type(sbs0_st_type[1:0]),
  .sbs1_st_type(sbs1_st_type[1:0]),
  .sbs2_st_type(sbs2_st_type[1:0]),
  .sbs3_st_type(sbs3_st_type[1:0]),
  .sbs4_st_type(sbs4_st_type[1:0]),
  .sbs5_st_type(sbs5_st_type[1:0]),
  .sbs6_st_type(sbs6_st_type[1:0]),
  .sbs7_st_type(sbs7_st_type[1:0]),
  .sbs_state_asi_rngf(sbs_state_asi_rngf[7:0]),
  .sbs_pcx_pst_ie_p4(sbs_pcx_pst_ie_p4[7:0]),
  .sbs_bst_req(sbs_bst_req[7:0]),
  .sbs_asi_indet_req(sbs_asi_indet_req[7:0]),
  .sbs_asi_indet_retire(sbs_asi_indet_retire[7:0]),
  .sbs_rmo_st_p4(sbs_rmo_st_p4[7:0]),
  .sbs_blk_st_p4(sbs_blk_st_p4[7:0]),
  .sbs_stb_empty(sbs_stb_empty[7:0]),
  .stb_cam_mhit(stb_cam_mhit),
  .stb_ld_part_raw(stb_ld_part_raw),
  .stb_cam_hit_ptr(stb_cam_hit_ptr[2:0]),
  .stb_cecc_err(stb_cecc_err),
  .stb_uecc_err(stb_uecc_err),
  .stb_ram_ctl(stb_ram_ctl[2:0]),
  .stb_cam_perr(stb_cam_perr),
  .lmd_asi_asi(lmd_asi_asi[7:0]),
  .lmd_asi_type(lmd_asi_type[1:0]),
  .lmc_ld_inst_w(lmc_ld_inst_w),
  .lmc_asi_indet_retire(lmc_asi_indet_retire),
  .pic_st_pcx_sel_p3(pic_st_pcx_sel_p3),
  .pic_st_asi_sel_p3(pic_st_asi_sel_p3),
  .pic_asi_sel_p4(pic_asi_sel_p4),
  .tlb_cam_mhit(tlb_cam_mhit),
  .fgu_fst_ecc_error_fx2(fgu_fst_ecc_error_fx2),
  .sed_bist_cmp_0(sed_bist_cmp_0),
  .sed_bist_cmp_1(sed_bist_cmp_1),
  .sed_bist_cmp_2(sed_bist_cmp_2),
  .sed_bist_cmp_3(sed_bist_cmp_3),
  .lbist_run(lbist_run),
  .mbi_run(mbi_run),
  .mbi_addr(mbi_addr[5:0]),
  .mbi_wdata(mbi_wdata[2:0]),
  .mbi_stb_cam_read_en(mbi_stb_cam_read_en),
  .mbi_stb_cam_write_en(mbi_stb_cam_write_en),
  .mbi_stb_ram_read_en(mbi_stb_ram_read_en),
  .mbi_stb_ram_write_en(mbi_stb_ram_write_en),
  .bist_srm_rd_1(bist_srm_rd_1),
  .bist_scm_rd_1(bist_scm_rd_1),
  .sbc_thread_b(sbc_thread_b[7:0]),
  .sbc_st_int_sel_m(sbc_st_int_sel_m),
  .sbc_std_le_m(sbc_std_le_m),
  .sbc_st_le_if_ie_m(sbc_st_le_if_ie_m),
  .sbc_st_le_not_ie_m(sbc_st_le_not_ie_m),
  .sbc_st_sz_m(sbc_st_sz_m[1:0]),
  .sbc_inv_addr_prty(sbc_inv_addr_prty),
  .sbc_inv_ecc(sbc_inv_ecc[6:0]),
  .sbc_stb_ctl_data(sbc_stb_ctl_data[2:0]),
  .sbc_twocycle_inst_w(sbc_twocycle_inst_w),
  .sbc_tte_vld_b(sbc_tte_vld_b),
  .sbc_cam_wvld_m(sbc_cam_wvld_m[7:0]),
  .sbc_cam_wptr_vld_m(sbc_cam_wptr_vld_m),
  .sbc_cam_rptr_vld(sbc_cam_rptr_vld),
  .sbc_cam_rwptr(sbc_cam_rwptr[5:0]),
  .sbc_cam_line_en_m(sbc_cam_line_en_m[7:0]),
  .sbc_ram_wptr_vld_b(sbc_ram_wptr_vld_b),
  .sbc_ram_rptr_vld(sbc_ram_rptr_vld),
  .sbc_ram_wptr(sbc_ram_wptr[5:0]),
  .sbc_ram_rptr(sbc_ram_rptr[5:0]),
  .sbc_cam_tid(sbc_cam_tid[2:0]),
  .sbc_diag_wptr_w3(sbc_diag_wptr_w3[2:0]),
  .sbc_st_rq_p2(sbc_st_rq_p2),
  .sbc_st_atomic_p2(sbc_st_atomic_p2),
  .sbc_pcx_rq_p3(sbc_pcx_rq_p3),
  .sbc_asi_rq_p3(sbc_asi_rq_p3),
  .sbc_st_sel_p3(sbc_st_sel_p3[7:0]),
  .sbc_bst_sel(sbc_bst_sel[7:0]),
  .sbc_st_sel_tid_p4(sbc_st_sel_tid_p4[2:0]),
  .sbc_st_pcx_nc(sbc_st_pcx_nc),
  .sbc_pcx_bmask(sbc_pcx_bmask[7:0]),
  .sbc_pcx_addr(sbc_pcx_addr[2:0]),
  .sbc_pcx_rmo_st(sbc_pcx_rmo_st),
  .sbc_pcx_blk_st(sbc_pcx_blk_st),
  .sbc_st_asi_fs(sbc_st_asi_fs),
  .sbc_st_addr_new(sbc_st_addr_new[7:0]),
  .sbc_spd_clken(sbc_spd_clken),
  .sbc_ramout_clken(sbc_ramout_clken),
  .sbc_tidb_eq_tidw(sbc_tidb_eq_tidw),
  .sbc_tid_m(sbc_tid_m[2:0]),
  .sbc_st_atom_p3(sbc_st_atom_p3[7:0]),
  .sbc_load_bst_addr(sbc_load_bst_addr),
  .sbc_bst_in_prog_m(sbc_bst_in_prog_m),
  .sbc_bst_in_prog_b(sbc_bst_in_prog_b),
  .sbc_bst_offset(sbc_bst_offset[2:0]),
  .sbc_rmo_st_b(sbc_rmo_st_b),
  .sbc_rawp_rst(sbc_rawp_rst[7:0]),
  .sbc_fgu_ecc_b(sbc_fgu_ecc_b),
  .sbc_bst_rd_err(sbc_bst_rd_err),
  .sbc_pid_kill_store_p4_(sbc_pid_kill_store_p4_),
  .sbc_pic_kill_store_p4_(sbc_pic_kill_store_p4_),
  .sbc_sbs_kill_store_p4_(sbc_sbs_kill_store_p4_),
  .sbc_force_inv(sbc_force_inv),
  .sbc_st_type_p4(sbc_st_type_p4[2:0]),
  .sbc_blk_inst_b(sbc_blk_inst_b),
  .sbc_indet_block_p3(sbc_indet_block_p3),
  .lsu_block_store_stall(lsu_block_store_stall),
  .lsu_block_store_rd(lsu_block_store_rd[4:3]),
  .lsu_block_store_tid(lsu_block_store_tid[2:0]),
  .lsu_block_store_alloc(lsu_block_store_alloc[7:0]),
  .lsu_block_store_b(lsu_block_store_b[7:0]),
  .lsu_block_store_m(lsu_block_store_m),
  .lsu_sbdpc_err_g(lsu_sbdpc_err_g),
  .lsu_sbdpu_err_g(lsu_sbdpu_err_g),
  .lsu_sbapp_err_g(lsu_sbapp_err_g),
  .lsu_sbdiou_err_g(lsu_sbdiou_err_g),
  .lsu_stberr_index_g(lsu_stberr_index_g[2:0]),
  .lsu_stberr_priv_g(lsu_stberr_priv_g[1:0]),
  .lsu_stb_flush_g(lsu_stb_flush_g),
  .lsu_frf_read_pending(lsu_frf_read_pending),
  .sbc_mbi_run(sbc_mbi_run),
  .lsu_mbi_stb_cam_fail(lsu_mbi_stb_cam_fail),
  .lsu_mbi_stb_ram_fail(lsu_mbi_stb_ram_fail),
  .lsu_mbi_scm_hit(lsu_mbi_scm_hit),
  .lsu_mbi_scm_mhit(lsu_mbi_scm_mhit),
  .lsu_mbi_scm_hit_ptr(lsu_mbi_scm_hit_ptr[2:0]),
  .lsu_mbi_scm_praw(lsu_mbi_scm_praw)
);

lsu_spd_dp spd (
.scan_in(spd_scanin),
.scan_out(spd_scanout),
.l2clk(l2clk),
  .sbd_st_addr_b(sbd_st_addr_b[39:3]),
  .sbc_st_addr_new(sbc_st_addr_new[7:0]),
  .sbc_thread_b(sbc_thread_b[7:0]),
  .sbc_spd_clken(sbc_spd_clken),
  .sbc_tidb_eq_tidw(sbc_tidb_eq_tidw),
  .sbc_inv_addr_prty(sbc_inv_addr_prty),
  .sbc_cam_line_en_m(sbc_cam_line_en_m[7:0]),
  .stb_cam_data(stb_cam_data[44:0]),
  .stb_ram_cparity(stb_ram_cparity),
  .dcc_bmask_parity_b(dcc_bmask_parity_b),
  .spd_st_line_match(spd_st_line_match),
  .stb_cam_perr(stb_cam_perr),
  .stb_cparity_calc(stb_cparity_calc),
  .stb_cam_line_en_b(stb_cam_line_en_b[7:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

lsu_sec_ctl sec (
	.scan_in(sec_scanin),
	.scan_out(sec_scanout),
	.l2clk		(l2clk),
	.corr_bit	(sec_corr_bit[63:0]),
	.cecc_err	(stb_cecc_err),
	.uecc_err	(stb_uecc_err),
	.mbi_wdata_b3	(mbi_wdata[3]),
  .sed_c1_lo(sed_c1_lo[1:0]),
  .sed_c1_hi(sed_c1_hi[1:0]),
  .sed_c2_lo(sed_c2_lo[1:0]),
  .sed_c2_hi(sed_c2_hi[1:0]),
  .sed_c4_lo(sed_c4_lo[1:0]),
  .sed_c4_hi(sed_c4_hi[1:0]),
  .sed_c8_lo(sed_c8_lo[1:0]),
  .sed_c8_hi(sed_c8_hi[1:0]),
  .sed_c16_lo(sed_c16_lo[1:0]),
  .sed_c16_hi(sed_c16_hi[1:0]),
  .sed_cf_lo(sed_cf_lo[2:0]),
  .sed_cf_hi(sed_cf_hi[2:0]),
  .sed_c32_hi(sed_c32_hi),
  .sed_c32_lo(sed_c32_lo),
  .sbc_twocycle_inst_w(sbc_twocycle_inst_w),
  .stb_cparity_calc(stb_cparity_calc),
  .sbc_st_sz_m(sbc_st_sz_m[1:0]),
  .sbc_std_le_m(sbc_std_le_m),
  .sbc_st_le_if_ie_m(sbc_st_le_if_ie_m),
  .sbc_st_le_not_ie_m(sbc_st_le_not_ie_m),
  .sbc_spd_clken(sbc_spd_clken),
  .mbi_run(mbi_run),
  .stb_cparity(stb_cparity),
  .sec_st_sz_dw_std_le_b(sec_st_sz_dw_std_le_b),
  .sec_st_sz_dw_le_not_ie_b(sec_st_sz_dw_le_not_ie_b),
  .sec_st_sz_dw_be_not_ie_b(sec_st_sz_dw_be_not_ie_b),
  .sec_st_sz_word_le_not_ie_b(sec_st_sz_word_le_not_ie_b),
  .sec_st_sz_word_be_not_ie_b(sec_st_sz_word_be_not_ie_b),
  .sec_st_sz_hw_le_not_ie_b(sec_st_sz_hw_le_not_ie_b),
  .sec_st_sz_hw_be_not_ie_b(sec_st_sz_hw_be_not_ie_b),
  .sec_st_sz_dw_le_if_ie_b(sec_st_sz_dw_le_if_ie_b),
  .sec_st_sz_dw_be_if_ie_b(sec_st_sz_dw_be_if_ie_b),
  .sec_st_sz_word_le_if_ie_b(sec_st_sz_word_le_if_ie_b),
  .sec_st_sz_word_be_if_ie_b(sec_st_sz_word_be_if_ie_b),
  .sec_st_sz_hw_le_if_ie_b(sec_st_sz_hw_le_if_ie_b),
  .sec_st_sz_hw_be_if_ie_b(sec_st_sz_hw_be_if_ie_b),
  .sec_st_sz_byte_b(sec_st_sz_byte_b),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

lsu_sed_dp sed (
	.scan_in(sed_scanin),
	.scan_out(sed_scanout),
	.l2clk			(l2clk),
	.bist_cmp_data		(bist_cmp_data_rep0[7:0]),
	.stb_cam_data		(stb_cam_data_rep0[44:0]),
	.mbi_run		(sbc_mbi_run),
  .sbc_ramout_clken(sbc_ramout_clken),
  .sbc_diag_wptr_w3(sbc_diag_wptr_w3[2:0]),
  .sbc_inv_ecc(sbc_inv_ecc[6:0]),
  .stb_ram_rd_data(stb_ram_rd_data[63:0]),
  .sec_corr_bit(sec_corr_bit[63:0]),
  .stb_ram_rd_ecc(stb_ram_rd_ecc[13:0]),
  .stb_ram_rd_cparity(stb_ram_rd_cparity),
  .stb_ram_rd_ctl(stb_ram_rd_ctl[2:0]),
  .sbd_st_data_b(sbd_st_data_b[63:0]),
  .dcc_stb_data_rd_w3(dcc_stb_data_rd_w3),
  .dcc_stb_ecc_rd_w3(dcc_stb_ecc_rd_w3),
  .dcc_stb_ctl_rd_w3(dcc_stb_ctl_rd_w3),
  .dcc_stb_addr_sel_w3(dcc_stb_addr_sel_w3),
  .dcc_stb_ptr_rd_w3(dcc_stb_ptr_rd_w3),
  .mbi_wdata(mbi_wdata[7:0]),
  .stb_ram_data(stb_ram_data[63:0]),
  .stb_ram_data_corr(stb_ram_data_corr[63:0]),
  .stb_ram_ctl(stb_ram_ctl[2:0]),
  .stb_ram_cparity(stb_ram_cparity),
  .sed_ecc_b(sed_ecc_b[13:0]),
  .sed_c1_lo(sed_c1_lo[1:0]),
  .sed_c1_hi(sed_c1_hi[1:0]),
  .sed_c2_lo(sed_c2_lo[1:0]),
  .sed_c2_hi(sed_c2_hi[1:0]),
  .sed_c4_lo(sed_c4_lo[1:0]),
  .sed_c4_hi(sed_c4_hi[1:0]),
  .sed_c8_lo(sed_c8_lo[1:0]),
  .sed_c8_hi(sed_c8_hi[1:0]),
  .sed_c16_lo(sed_c16_lo[1:0]),
  .sed_c16_hi(sed_c16_hi[1:0]),
  .sed_cf_lo(sed_cf_lo[2:0]),
  .sed_cf_hi(sed_cf_hi[2:0]),
  .sed_c32_hi(sed_c32_hi),
  .sed_c32_lo(sed_c32_lo),
  .stb_ldxa_asi_data_w(stb_ldxa_asi_data_w[63:0]),
  .sed_bist_cmp_0(sed_bist_cmp_0),
  .sed_bist_cmp_1(sed_bist_cmp_1),
  .sed_bist_cmp_2(sed_bist_cmp_2),
  .sed_bist_cmp_3(sed_bist_cmp_3),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

lsu_sbd_dp sbd (
	.scan_in(sbd_scanin),
	.scan_out(sbd_scanout),
	.l2clk			(l2clk),
	.exu_lsu_store_data_e	(exu_lsu_store_data_e_rep0[63:0]),
	.mbi_run		(sbc_mbi_run),
  .const_cpuid(const_cpuid[2:0]),
  .lsu_va_m(lsu_va_m[47:3]),
  .fgu_lsu_fst_data_fx1(fgu_lsu_fst_data_fx1[63:0]),
  .tlb_pgnum_crit(tlb_pgnum_crit[39:13]),
  .tlb_tte_ie_b(tlb_tte_ie_b),
  .sbc_st_int_sel_m(sbc_st_int_sel_m),
  .sbc_bst_offset(sbc_bst_offset[2:0]),
  .sbc_bst_in_prog_m(sbc_bst_in_prog_m),
  .sbc_load_bst_addr(sbc_load_bst_addr),
  .sec_st_sz_dw_std_le_b(sec_st_sz_dw_std_le_b),
  .sec_st_sz_dw_le_not_ie_b(sec_st_sz_dw_le_not_ie_b),
  .sec_st_sz_dw_be_not_ie_b(sec_st_sz_dw_be_not_ie_b),
  .sec_st_sz_word_le_not_ie_b(sec_st_sz_word_le_not_ie_b),
  .sec_st_sz_word_be_not_ie_b(sec_st_sz_word_be_not_ie_b),
  .sec_st_sz_hw_le_not_ie_b(sec_st_sz_hw_le_not_ie_b),
  .sec_st_sz_hw_be_not_ie_b(sec_st_sz_hw_be_not_ie_b),
  .sec_st_sz_dw_le_if_ie_b(sec_st_sz_dw_le_if_ie_b),
  .sec_st_sz_dw_be_if_ie_b(sec_st_sz_dw_be_if_ie_b),
  .sec_st_sz_word_le_if_ie_b(sec_st_sz_word_le_if_ie_b),
  .sec_st_sz_word_be_if_ie_b(sec_st_sz_word_be_if_ie_b),
  .sec_st_sz_hw_le_if_ie_b(sec_st_sz_hw_le_if_ie_b),
  .sec_st_sz_hw_be_if_ie_b(sec_st_sz_hw_be_if_ie_b),
  .sec_st_sz_byte_b(sec_st_sz_byte_b),
  .dcc_tid_m(dcc_tid_m[2:0]),
  .dcc_asi_m(dcc_asi_m[7:0]),
  .dcc_sbd_e_clken(dcc_sbd_e_clken),
  .dcc_sbd_m_clken(dcc_sbd_m_clken),
  .dcc_std_inst_m(dcc_std_inst_m),
  .dcc_fp32b_sel_m(dcc_fp32b_sel_m),
  .dcc_asi_iomap_m(dcc_asi_iomap_m),
  .dcc_cache_diag_wr_m(dcc_cache_diag_wr_m),
  .dcc_demap_asi_m(dcc_demap_asi_m),
  .dcc_ldstub_inst_m(dcc_ldstub_inst_m),
  .stb_cam_data(stb_cam_data[44:11]),
  .dcs_memref_m(dcs_memref_m),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_ptag_data(mbi_ptag_data),
  .mbi_init_to_zero(mbi_init_to_zero),
  .mbi_cambist_shift(mbi_cambist_shift),
  .sbd_st_data_b(sbd_st_data_b[63:0]),
  .sbd_st_data2_b(sbd_st_data2_b[63:0]),
  .sbd_st_datab_b(sbd_st_datab_b[63:0]),
  .sbd_st_predata_b(sbd_st_predata_b[47:0]),
  .sbd_st_addr_b(sbd_st_addr_b[39:3]),
  .stb_st_addr_m(stb_st_addr_m[39:3]),
  .stb_st_addr_b(stb_st_addr_b[39:13]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

n2_stb_cm_64x45_cust stb_cam (
	.stb_camwr_data		({stb_st_addr_m[39:3],dcc_ldst_bmask[7:0]}),
	.stb_cam_vld		(dcc_stb_cam_vld_m),
	.stb_cam_cm_tid		(sbc_cam_tid[2:0]),
	.stb_cam_line_en	(stb_cam_line_en_b[7:0]),
	.stb_cam_rw_ptr		(sbc_cam_rwptr[2:0]),
	.stb_cam_wptr_vld	(sbc_cam_wptr_vld_m),
	.stb_cam_rptr_vld	(sbc_cam_rptr_vld),
	.stb_cam_rw_tid		(sbc_cam_rwptr[5:3]),
	.stb_quad_ld_cam	(dcc_stb_quad_ld_cam),
	.scan_in(stb_cam_scanin),
	.scan_out(stb_cam_scanout),
	.l2clk			(l2clk),
	.stb_rdata_ramc		(stb_cam_data[44:0]),
	.stb_ld_partial_raw	(stb_ld_part_raw),
	.stb_cam_hit_ptr	(stb_cam_hit_ptr[2:0]),
	.stb_cam_hit		(stb_cam_hit),
	.stb_cam_mhit		(stb_cam_mhit),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .pce(pce)
);

n2_com_dp_64x84_cust stb_ram (
	.rd_adr	(sbc_ram_rptr[5:0]),
	.rd_en	(sbc_ram_rptr_vld),
	.wr_en	(sbc_ram_wptr_vld_b),
	.wr_adr	(sbc_ram_wptr[5:0]),
	.din	(stb_ram_din[83:0]),
	.scan_in(stb_ram_scanin),
	.scan_out(stb_ram_scanout),
	.rdclk	(l2clk),
	.wrclk	(l2clk),
	.dout	(stb_ram_dout[83:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);

// Reorder nets for physical layout (array pins go from LSB to MSB left to right)
assign stb_ram_din[83:0] = {
 sbd_st_datab_b[0], sbd_st_datab_b[32], sbd_st_datab_b[1], sbd_st_datab_b[33],
 sbd_st_datab_b[2], sbd_st_datab_b[34], sbd_st_datab_b[3], sbd_st_datab_b[35],
 sbd_st_datab_b[4], sbd_st_datab_b[36], sbd_st_datab_b[5], sbd_st_datab_b[37],
 sbd_st_datab_b[6], sbd_st_datab_b[38], sbd_st_datab_b[7], sbd_st_datab_b[39],
 sbd_st_datab_b[8], sbd_st_datab_b[40], sbd_st_datab_b[9], sbd_st_datab_b[41],
 sbd_st_datab_b[10], sbd_st_datab_b[42], sbd_st_datab_b[11], sbd_st_datab_b[43],
 sbd_st_datab_b[12], sbd_st_datab_b[44], sbd_st_datab_b[13], sbd_st_datab_b[45],
 sbd_st_datab_b[14], sbd_st_datab_b[46], sbd_st_datab_b[15], sbd_st_datab_b[47],
 2'b00,
 sed_ecc_b[0], sed_ecc_b[7], sed_ecc_b[1], sed_ecc_b[8], sed_ecc_b[2], sed_ecc_b[9],
 sed_ecc_b[3], sed_ecc_b[10], sed_ecc_b[4], sed_ecc_b[11], sed_ecc_b[5], sed_ecc_b[12],
 sed_ecc_b[6], sed_ecc_b[13],
 sbd_st_datab_b[16], sbd_st_datab_b[48], sbd_st_datab_b[17], sbd_st_datab_b[49],
 sbd_st_datab_b[18], sbd_st_datab_b[50], sbd_st_datab_b[19], sbd_st_datab_b[51],
 sbd_st_datab_b[20], sbd_st_datab_b[52], sbd_st_datab_b[21], sbd_st_datab_b[53],
 sbd_st_datab_b[22], sbd_st_datab_b[54], sbd_st_datab_b[23], sbd_st_datab_b[55],
 sbd_st_datab_b[24], sbd_st_datab_b[56], sbd_st_datab_b[25], sbd_st_datab_b[57],
 sbd_st_datab_b[26], sbd_st_datab_b[58], sbd_st_datab_b[27], sbd_st_datab_b[59],
 sbd_st_datab_b[28], sbd_st_datab_b[60], sbd_st_datab_b[29], sbd_st_datab_b[61],
 sbd_st_datab_b[30], sbd_st_datab_b[62], sbd_st_datab_b[31], sbd_st_datab_b[63],
 sbc_stb_ctl_data[0], sbc_stb_ctl_data[2], sbc_stb_ctl_data[1], stb_cparity
};

assign {
 stb_ram_rd_data[0], stb_ram_rd_data[32], stb_ram_rd_data[1], stb_ram_rd_data[33],
 stb_ram_rd_data[2], stb_ram_rd_data[34], stb_ram_rd_data[3], stb_ram_rd_data[35],
 stb_ram_rd_data[4], stb_ram_rd_data[36], stb_ram_rd_data[5], stb_ram_rd_data[37],
 stb_ram_rd_data[6], stb_ram_rd_data[38], stb_ram_rd_data[7], stb_ram_rd_data[39],
 stb_ram_rd_data[8], stb_ram_rd_data[40], stb_ram_rd_data[9], stb_ram_rd_data[41],
 stb_ram_rd_data[10], stb_ram_rd_data[42], stb_ram_rd_data[11], stb_ram_rd_data[43],
 stb_ram_rd_data[12], stb_ram_rd_data[44], stb_ram_rd_data[13], stb_ram_rd_data[45],
 stb_ram_rd_data[14], stb_ram_rd_data[46], stb_ram_rd_data[15], stb_ram_rd_data[47],
 stb_ram_unused[1:0],
 stb_ram_rd_ecc[0], stb_ram_rd_ecc[7], stb_ram_rd_ecc[1], stb_ram_rd_ecc[8],
 stb_ram_rd_ecc[2], stb_ram_rd_ecc[9], stb_ram_rd_ecc[3], stb_ram_rd_ecc[10],
 stb_ram_rd_ecc[4], stb_ram_rd_ecc[11], stb_ram_rd_ecc[5], stb_ram_rd_ecc[12],
 stb_ram_rd_ecc[6], stb_ram_rd_ecc[13],
 stb_ram_rd_data[16], stb_ram_rd_data[48], stb_ram_rd_data[17], stb_ram_rd_data[49],
 stb_ram_rd_data[18], stb_ram_rd_data[50], stb_ram_rd_data[19], stb_ram_rd_data[51],
 stb_ram_rd_data[20], stb_ram_rd_data[52], stb_ram_rd_data[21], stb_ram_rd_data[53],
 stb_ram_rd_data[22], stb_ram_rd_data[54], stb_ram_rd_data[23], stb_ram_rd_data[55],
 stb_ram_rd_data[24], stb_ram_rd_data[56], stb_ram_rd_data[25], stb_ram_rd_data[57],
 stb_ram_rd_data[26], stb_ram_rd_data[58], stb_ram_rd_data[27], stb_ram_rd_data[59],
 stb_ram_rd_data[28], stb_ram_rd_data[60], stb_ram_rd_data[29], stb_ram_rd_data[61],
 stb_ram_rd_data[30], stb_ram_rd_data[62], stb_ram_rd_data[31], stb_ram_rd_data[63],
 stb_ram_rd_ctl[0], stb_ram_rd_ctl[2], stb_ram_rd_ctl[1], stb_ram_rd_cparity
} = stb_ram_dout[83:0];

assign dta_clken = dcc_dta_clken;

n2_dta_sp_1920b_cust dta (
	.rdtag_w0_y	(dta_rdata_w0_m[29:0]),
	.rdtag_w1_y	(dta_rdata_w1_m[29:0]),
	.rdtag_w2_y	(dta_rdata_w2_m[29:0]),
	.rdtag_w3_y	(dta_rdata_w3_m[29:0]),
	.scan_in(dta_scanin),
	.scan_out(dta_scanout),
	.l2clk		(l2clk),
	.index0_x	(exu_lsu_address_e_rep0[10:4]),
	.index1_x	(dcc_dta_fill_addr_e[10:4]),
	.index_sel_x	(dcc_dta_index1_sel_e),
	.wrway_x	(dcc_dta_fill_way_e[1:0]),
	.rdreq_x	(dcc_dta_rvld_e),
	.wrreq_x	(dcc_dta_wvld_e),
	.wrtag_x	({dcc_dta_parity,lmd_fill_addr_e[39:11]}),
  .dta_clken(dta_clken),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_scan_en(tcu_scan_en),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit)
);

n2_dva_dp_32x32_cust dva (
	.dout		({dva_valid2_m[15:0],dva_valid_m[15:0]}),
	.scan_in(dva_scanin),
	.scan_out(dva_scanout),
	.l2clk	(l2clk),
	.rd_addr	(tgc_dva_rd_addr_e[10:6]),
	.rd_en		(dcc_dva_rvld_e),
	.wr_addr	(dcc_dva_wr_addr_e[10:6]),
	.wr_en		(dcc_dva_wvld_e),
	.bit_wen	({2{dcc_dva_bit_wen_e[15:0]}}),
	.din		(tgc_dva_din[31:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_scan_en(tcu_scan_en),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .pce(pce)
);

lsu_tgc_ctl tgc (
	.scan_in(tgc_scanin),
	.scan_out(tgc_scanout),
	.l2clk		(l2clk),
	.lsu_va_b12to11_m	(lsu_va_m[12:11]),
	.exu_lsu_address_e	(exu_lsu_address_e_rep0[10:6]),
  .dva_valid_m(dva_valid_m[15:0]),
  .dva_valid2_m(dva_valid2_m[15:0]),
  .lsu_va_m(lsu_va_m[5:4]),
  .dcc_ld_inst_vld_m(dcc_ld_inst_vld_m),
  .dcc_dva_din_e(dcc_dva_din_e),
  .dcc_dva_din2_e(dcc_dva_din2_e),
  .tgd_bist_compare(tgd_bist_compare),
  .tgc_cache_way_vld_m(tgc_cache_way_vld_m[3:0]),
  .tgc_cache_way_vld2_m(tgc_cache_way_vld2_m[3:0]),
  .tgc_verr_b(tgc_verr_b[3:0]),
  .tgc_way_sel_m(tgc_way_sel_m[1:0]),
  .tgc_dva_rd_addr_e(tgc_dva_rd_addr_e[10:6]),
  .tgc_dva_din(tgc_dva_din[31:0]),
  .lsu_mbi_dva_fail(lsu_mbi_dva_fail),
  .lsu_mbi_dta_fail(lsu_mbi_dta_fail),
  .lsu_mbi_dtb_fail(lsu_mbi_dtb_fail),
  .mbi_run(mbi_run),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_cmpsel(mbi_cmpsel[1:0]),
  .mbi_addr(mbi_addr[8:0]),
  .mbi_dta_read_en(mbi_dta_read_en),
  .mbi_dva_read_en(mbi_dva_read_en),
  .mbi_dtb_read_en(mbi_dtb_read_en),
  .bist_wdata_1(bist_wdata_1[7:0]),
  .bist_cmp_data(bist_cmp_data[7:0]),
  .bist_cmpsel_1(bist_cmpsel_1[1:0]),
  .bist_cmpsel_2(bist_cmpsel_2),
  .bist_addr_1(bist_addr_1[8:5]),
  .bist_dta_cmp_en(bist_dta_cmp_en),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .lsu_lsu_pmen(lsu_lsu_pmen)
);

lsu_tgd_dp tgd (
	.scan_in(tgd_scanin),
	.scan_out(tgd_scanout),
	.l2clk		(l2clk),
  .dta_rdata_w0_m(dta_rdata_w0_m[29:0]),
  .dta_rdata_w1_m(dta_rdata_w1_m[29:0]),
  .dta_rdata_w2_m(dta_rdata_w2_m[29:0]),
  .dta_rdata_w3_m(dta_rdata_w3_m[29:0]),
  .tgc_cache_way_vld_m(tgc_cache_way_vld_m[3:0]),
  .tgc_cache_way_vld2_m(tgc_cache_way_vld2_m[3:0]),
  .tgc_way_sel_m(tgc_way_sel_m[1:0]),
  .dcs_watchpoint_m(dcs_watchpoint_m[47:3]),
  .dcs_context0_e(dcs_context0_e[12:0]),
  .dcs_context1_e(dcs_context1_e[12:0]),
  .dcc_rd_dt_diag_m(dcc_rd_dt_diag_m),
  .dcc_rd_dt_diag_b(dcc_rd_dt_diag_b),
  .dcc_tlb_tag0_read_b(dcc_tlb_tag0_read_b),
  .dcc_tlb_tag1_read_b(dcc_tlb_tag1_read_b),
  .dcc_tlb_data_read_b(dcc_tlb_data_read_b),
  .dcc_ld_inst_vld_m(dcc_ld_inst_vld_m),
  .dcc_ldst_m_clken(dcc_ldst_m_clken),
  .tlb_pgnum(tlb_pgnum[39:13]),
  .tlb_tte_data(tlb_tte_data[37:0]),
  .tlb_tte_tag(tlb_tte_tag[65:0]),
  .tlb_tte_u_bit(tlb_tte_u_bit),
  .tlb_cam_hit(tlb_cam_hit),
  .tlb_context0_hit(tlb_context0_hit),
  .tlb_cam_mhit(tlb_cam_mhit),
  .tld_prty_256m(tld_prty_256m),
  .tld_prty_4m(tld_prty_4m),
  .tld_prty_64k(tld_prty_64k),
  .tld_prty_8k(tld_prty_8k),
  .tld_prty_ctxt0(tld_prty_ctxt0),
  .tld_prty_ctxt1(tld_prty_ctxt1),
  .tld_tag_c0(tld_tag_c0[12:0]),
  .tld_tag_c1(tld_tag_c1[12:0]),
  .tlc_sel_tte_tag(tlc_sel_tte_tag),
  .tlc_sel_demap_tag_c0(tlc_sel_demap_tag_c0),
  .tlc_sel_demap_tag_c1(tlc_sel_demap_tag_c1),
  .bist_cmp_data(bist_cmp_data[7:0]),
  .bist_dta_cmp_en(bist_dta_cmp_en),
  .bist_cmpsel_2(bist_cmpsel_2),
  .lsu_va_m(lsu_va_m[47:3]),
  .tgd_w0_parity_b(tgd_w0_parity_b),
  .tgd_w1_parity_b(tgd_w1_parity_b),
  .tgd_w2_parity_b(tgd_w2_parity_b),
  .tgd_w3_parity_b(tgd_w3_parity_b),
  .dta_rdata_w0_rep(dta_rdata_w0_rep[28:0]),
  .dta_rdata_w1_rep(dta_rdata_w1_rep[28:0]),
  .dta_rdata_w2_rep(dta_rdata_w2_rep[28:0]),
  .dta_rdata_w3_rep(dta_rdata_w3_rep[28:0]),
  .tgd_prty_256m_b(tgd_prty_256m_b),
  .tgd_prty_4m_b(tgd_prty_4m_b),
  .tgd_prty_64k_b(tgd_prty_64k_b),
  .tgd_prty_8k_b(tgd_prty_8k_b),
  .tgd_prty_ctxt0_b(tgd_prty_ctxt0_b),
  .tgd_prty_ctxt1_b(tgd_prty_ctxt1_b),
  .tgd_va_wp_47_16(tgd_va_wp_47_16),
  .tgd_va_wp_15_3(tgd_va_wp_15_3),
  .tgd_pa_wp_39_16(tgd_pa_wp_39_16),
  .tgd_pa_wp_15_3(tgd_pa_wp_15_3),
  .tgd_tag_c0(tgd_tag_c0[12:0]),
  .tgd_tag_c1(tgd_tag_c1[12:0]),
  .tlb_tag_parity(tlb_tag_parity),
  .tlb_pgsize(tlb_pgsize[2:0]),
  .tlb_tte_nfo_b(tlb_tte_nfo_b),
  .tlb_tte_ie_b(tlb_tte_ie_b),
  .tlb_tte_cp_b(tlb_tte_cp_b),
  .tlb_tte_ebit_b(tlb_tte_ebit_b),
  .tlb_tte_pbit_b(tlb_tte_pbit_b),
  .tlb_tte_wbit_b(tlb_tte_wbit_b),
  .tgd_ldxa_asi_data_b(tgd_ldxa_asi_data_b[63:0]),
  .tgd_bist_compare(tgd_bist_compare),
  .lsu_mbi_tlb_data_cmp(lsu_mbi_tlb_data_cmp),
  .lsu_mbi_tlb_cam_hit(lsu_mbi_tlb_cam_hit),
  .lsu_mbi_tlb_cam_mhit(lsu_mbi_tlb_cam_mhit),
  .lsu_mbi_tlb_ctxt0_hit(lsu_mbi_tlb_ctxt0_hit),
  .lsu_mbi_tlb_valid(lsu_mbi_tlb_valid),
  .lsu_mbi_tlb_used(lsu_mbi_tlb_used),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

assign tte_ubit = tld_ubit;

n2_tlb_tl_128x59_cust tlb (
	.tlb_bypass	(dcc_tlb_bypass),
	.tlb_wr_vld	(tlc_wr_u_en),
	.tlb_rd_vld	(dcc_tlb_rd_e),
	.tlb_rw_index	(tld_rw_index[6:0]),
	.tlb_rw_index_vld(tlc_rw_index_vld),
	.tlb_cam_vld	(dcc_tlb_lookup),
	.tlb_demap	(tlc_demap),
	.tlb_demap_context(tlc_demap_context),
	.tlb_demap_all	(tlc_demap_all),
	.tlb_demap_real	(tlc_demap_real),
	// Separate page size mask from tag proper
	.tte_tag	({tgd_tag_c1[12:0],		// C1
			  tld_tag_pid[2:0],		// PID
			  tld_tag_real,			// REAL
			  exu_lsu_address_e[47:22],	// VA[47:22]
			  tld_tag_valid,			// VALID
			  exu_lsu_address_e[21:13],	// VA[21:13]
			  tgd_tag_c0[12:0]}),		// C0
	.tte_page_size_mask(tld_tag_mask[2:0]),
	.tte_data	(tld_data[37:0]),
	.tlb_va		(exu_lsu_address_e[12:11]),
	.disable_clear_ubit(tlc_dis_clr_ubit),
	.cache_ptag_w0	(dta_rdata_w0_rep[28:0]),
	.cache_ptag_w1	(dta_rdata_w1_rep[28:0]),
	.cache_ptag_w2	(dta_rdata_w2_rep[28:0]),
	.cache_ptag_w3	(dta_rdata_w3_rep[28:0]),
	.cache_set_vld	(tgc_cache_way_vld_m[3:0]),
	.cache_way_hit	(tlb_cache_way_hit_b[3:0]),
	.cache_hit	(tlb_cache_hit_b),
	.scan_in(tlb_scanin),
	.scan_out(tlb_scanout),
	.l2clk		(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .pce(pce),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_scan_en(tcu_scan_en),
  .tte_ubit(tte_ubit),
  .tlb_cam_hit(tlb_cam_hit),
  .tlb_cam_mhit(tlb_cam_mhit),
  .tlb_context0_hit(tlb_context0_hit),
  .tlb_pgnum_crit(tlb_pgnum_crit[39:13]),
  .tlb_pgnum(tlb_pgnum[39:13]),
  .tlb_tte_data(tlb_tte_data[37:0]),
  .tlb_tte_tag(tlb_tte_tag[65:0]),
  .tlb_tte_u_bit(tlb_tte_u_bit),
  .tlb_tte_data_parity(tlb_tte_data_parity)
);

lsu_tld_dp tld (
	.scan_in(tld_scanin),
	.scan_out(tld_scanout),
	.l2clk		(l2clk),
	.default_tag	({dcs_pid_e[2:0],
			  dcc_tlb_real,
			  exu_lsu_address_e[47:22],
			  1'b1,
			  1'b1,			// tag valid
			  exu_lsu_address_e[21:16],
			  1'b1,
			  exu_lsu_address_e[15:13],
			  1'b1
			}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .exu_lsu_address_e(exu_lsu_address_e[47:0]),
  .tlc_sel_write_tag(tlc_sel_write_tag),
  .tlc_sel_dm_tag(tlc_sel_dm_tag),
  .tlc_sel_wr_dm_bist(tlc_sel_wr_dm_bist),
  .tlc_write_next(tlc_write_next),
  .tlc_tte0_clken(tlc_tte0_clken),
  .tlc_tte1_clken(tlc_tte1_clken),
  .tlc_tag_error_inj(tlc_tag_error_inj),
  .tlc_data_error_inj(tlc_data_error_inj),
  .tlu_tte(tlu_tte[54:0]),
  .tlc_mbi_run(tlc_mbi_run),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_addr(mbi_addr[6:0]),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_cambist_shift(mbi_cambist_shift),
  .mbi_init_to_zero(mbi_init_to_zero),
  .mbi_dtb_write_en(mbi_dtb_write_en),
  .mbi_repl_write(mbi_repl_write),
  .mbi_dis_clr_ubit(mbi_dis_clr_ubit),
  .mbi_dtb_demap_en(mbi_dtb_demap_en),
  .mbi_demap_type(mbi_demap_type[1:0]),
  .tld_mbi_dtb_write_en(tld_mbi_dtb_write_en),
  .tld_mbi_repl_write(tld_mbi_repl_write),
  .tld_mbi_dis_clr_ubit(tld_mbi_dis_clr_ubit),
  .tld_mbi_dtb_demap_en(tld_mbi_dtb_demap_en),
  .tld_mbi_demap_type(tld_mbi_demap_type[1:0]),
  .tgd_tag_c0(tgd_tag_c0[12:0]),
  .tgd_tag_c1(tgd_tag_c1[12:0]),
  .tld_ubit(tld_ubit),
  .tld_tag_pid(tld_tag_pid[2:0]),
  .tld_tag_c0(tld_tag_c0[12:0]),
  .tld_tag_c1(tld_tag_c1[12:0]),
  .tld_tag_real(tld_tag_real),
  .tld_tag_valid(tld_tag_valid),
  .tld_tag_mask(tld_tag_mask[2:0]),
  .tld_data(tld_data[37:0]),
  .tld_demap_control0(tld_demap_control0[2:0]),
  .tld_demap_control1(tld_demap_control1[3:0]),
  .tld_use_secondary_context0(tld_use_secondary_context0),
  .tld_tid(tld_tid[2:0]),
  .tld_index_valid(tld_index_valid),
  .tld_rw_index(tld_rw_index[6:0]),
  .tld_prty_256m(tld_prty_256m),
  .tld_prty_4m(tld_prty_4m),
  .tld_prty_64k(tld_prty_64k),
  .tld_prty_8k(tld_prty_8k),
  .tld_prty_ctxt0(tld_prty_ctxt0),
  .tld_prty_ctxt1(tld_prty_ctxt1),
  .tld_va_m_eq_zero(tld_va_m_eq_zero),
  .lsu_va_m(lsu_va_m[47:0]),
  .lsu_mmu_va_m(lsu_mmu_va_m[47:0]),
  .lsu_exu_address_e(lsu_exu_address_e[47:13])
);

lsu_tlc_ctl tlc (
	.scan_in(tlc_scanin),
	.scan_out(tlc_scanout),
	.l2clk		(l2clk),
	.lsu_asi_error_inject_b31(lsu_asi_error_inject[31]),
	.lsu_asi_error_inject_b27(lsu_asi_error_inject[27]),
	.lsu_asi_error_inject_b26(lsu_asi_error_inject[26]),
	.mbi_dtb_write_en	(tld_mbi_dtb_write_en),
	.mbi_repl_write		(tld_mbi_repl_write),
	.mbi_dis_clr_ubit	(tld_mbi_dis_clr_ubit),
	.mbi_dtb_demap_en	(tld_mbi_dtb_demap_en),
	.mbi_demap_type		(tld_mbi_demap_type[1:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .mmu_dtlb_reload(mmu_dtlb_reload),
  .tld_demap_control0(tld_demap_control0[2:0]),
  .tld_demap_control1(tld_demap_control1[3:0]),
  .tld_use_secondary_context0(tld_use_secondary_context0),
  .tld_index_valid(tld_index_valid),
  .lsu_lsu_pmen_(lsu_lsu_pmen_),
  .dcc_tlb_rw_index_e(dcc_tlb_rw_index_e),
  .lbist_run(lbist_run),
  .mbi_run(mbi_run),
  .mbi_cambist_run(mbi_cambist_run),
  .tlc_wr_u_en(tlc_wr_u_en),
  .tlc_rw_index_vld(tlc_rw_index_vld),
  .tlc_demap(tlc_demap),
  .tlc_demap_context(tlc_demap_context),
  .tlc_demap_all(tlc_demap_all),
  .tlc_demap_real(tlc_demap_real),
  .tlc_sel_demap_tag_c0(tlc_sel_demap_tag_c0),
  .tlc_sel_demap_tag_c1(tlc_sel_demap_tag_c1),
  .tlc_sel_write_tag(tlc_sel_write_tag),
  .tlc_sel_dm_tag(tlc_sel_dm_tag),
  .tlc_sel_wr_dm_bist(tlc_sel_wr_dm_bist),
  .tlc_sel_tte_tag(tlc_sel_tte_tag),
  .tlc_use_primary_context_c0(tlc_use_primary_context_c0),
  .tlc_use_secondary_context_c0(tlc_use_secondary_context_c0),
  .tlc_wr_or_demap(tlc_wr_or_demap),
  .tlc_write_next(tlc_write_next),
  .tlc_tte0_clken(tlc_tte0_clken),
  .tlc_tte1_clken(tlc_tte1_clken),
  .tlc_tag_error_inj(tlc_tag_error_inj),
  .tlc_data_error_inj(tlc_data_error_inj),
  .tlc_mbi_run(tlc_mbi_run),
  .tlc_dis_clr_ubit(tlc_dis_clr_ubit),
  .lsu_sel_lsu_addr_e(lsu_sel_lsu_addr_e)
);


lsu_rep_dp rep (.lmd_fill_or_byp_data_m(lmd_fill_or_byp_data_m[63:0]),
  .lmd_fill_or_byp_data_m_rep1(lmd_fill_or_byp_data_m_rep1[63:0]),
  .stb_ram_data(stb_ram_data[63:0]),
  .stb_ram_data_rep0(stb_ram_data_rep0[63:0]),
  .stb_cam_data(stb_cam_data[44:0]),
  .stb_cam_data_rep0(stb_cam_data_rep0[44:0]),
  .sbd_st_data2_b(sbd_st_data2_b[63:0]),
  .sbd_st_data2_b_rep0(sbd_st_data2_b_rep0[63:0]),
  .sbd_st_predata_b(sbd_st_predata_b[47:0]),
  .sbd_st_predata_b_rep0(sbd_st_predata_b_rep0[47:0]),
  .bist_cmp_data(bist_cmp_data[7:0]),
  .bist_cmp_data_rep0(bist_cmp_data_rep0[7:0]),
  .tlb_tte_ie_b(tlb_tte_ie_b),
  .tlb_tte_ie_b_rep00(tlb_tte_ie_b_rep00),
  .tlb_tte_ie_b_rep01(tlb_tte_ie_b_rep01),
  .stb_cam_hit(stb_cam_hit),
  .stb_cam_hit_rep0(stb_cam_hit_rep0),
  .tlb_cache_way_hit_b(tlb_cache_way_hit_b[3:0]),
  .cache_way_hit_top_b(cache_way_hit_top_b[3:0]),
  .cache_way_hit_bot_b(cache_way_hit_bot_b[3:0]),
  .exu_lsu_store_data_e(exu_lsu_store_data_e[63:0]),
  .exu_lsu_store_data_e_rep0(exu_lsu_store_data_e_rep0[63:0]),
  .exu_lsu_address_e(exu_lsu_address_e[10:4]),
  .exu_lsu_address_e_rep0(exu_lsu_address_e_rep0[10:4])
);

// fixscan start:
assign arc_scanin                = scan_in                  ;
assign ard_scanin                = arc_scanout              ;
assign dcd_scanin                = ard_scanout              ;
assign dac_scanin                = dcd_scanout              ;
assign dca_scanin                = dac_scanout              ;
assign lru_scanin                = dca_scanout              ;
assign dcc_scanin                = lru_scanout              ;
assign dcs_scanin                = dcc_scanout              ;
assign lmd_scanin                = dcs_scanout              ;
assign lmc_scanin                = lmd_scanout              ;
assign pic_scanin                = lmc_scanout              ;
assign cpq_scanin                = pic_scanout              ;
assign cid_scanin                = cpq_scanout              ;
assign red_scanin                = cid_scanout              ;
assign cic_scanin                = red_scanout              ;
assign asc_scanin                = cic_scanout              ;
assign asd_scanin                = asc_scanout              ;
assign pid_scanin                = asd_scanout              ;
assign sbs0_scanin               = pid_scanout              ;
assign sbs1_scanin               = sbs0_scanout             ;
assign sbs2_scanin               = sbs1_scanout             ;
assign sbs3_scanin               = sbs2_scanout             ;
assign sbs4_scanin               = sbs3_scanout             ;
assign sbs5_scanin               = sbs4_scanout             ;
assign sbs6_scanin               = sbs5_scanout             ;
assign sbs7_scanin               = sbs6_scanout             ;
assign sbc_scanin                = sbs7_scanout             ;
assign spd_scanin                = sbc_scanout              ;
assign sec_scanin                = spd_scanout              ;
assign sed_scanin                = sec_scanout              ;
assign sbd_scanin                = sed_scanout              ;
assign stb_cam_scanin            = sbd_scanout              ;
assign stb_ram_scanin            = stb_cam_scanout          ;
assign dta_scanin                = stb_ram_scanout          ;
assign dva_scanin                = dta_scanout              ;
assign tgc_scanin                = dva_scanout              ;
assign tgd_scanin                = tgc_scanout              ;
assign tlb_scanin                = tgd_scanout              ;
assign tld_scanin                = tlb_scanout              ;
assign tlc_scanin                = tld_scanout              ;
assign scan_out                  = tlc_scanout              ;

assign dcs_wmr_scanin            = wmr_scan_in              ;
assign wmr_scan_out              = dcs_wmr_scanout          ;
// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_adc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_adc_ctl (
  asi_e, 
  asi_m, 
  lsu_va_m, 
  sr_inst_e, 
  pr_inst_e, 
  hpr_inst_e, 
  sr_inst_m, 
  pr_inst_m, 
  hpr_inst_m, 
  altspace_ldst_e, 
  altspace_ldst_m, 
  ld_inst_vld_m, 
  legal_asi_va_m, 
  asi_legal_e, 
  asr_legal_m, 
  asi_sync_m, 
  asi_internal_e, 
  asi_rngf_m, 
  asi_indet_m, 
  lendian_asi_m, 
  asi_sz_byte_m, 
  asi_sz_hw_m, 
  pst_asi_m, 
  asi_pst8_m, 
  asi_pst16_m, 
  asi_pst32_m, 
  asi_read_only_m, 
  asi_write_only_m, 
  quad_asi_m, 
  binit_quad_asi_m, 
  primary_asi_e, 
  secondary_asi_e, 
  real_asi_e, 
  as_if_user_asi_e, 
  as_if_priv_asi_e, 
  atomic_asi_m, 
  blk_asi_e, 
  nofault_asi_m, 
  asi_iomap_m, 
  asi_no_va_check_m);
wire indet_m;


input	[7:0]	asi_e;
input	[7:0]	asi_m;			// This version has SR/PR/HPR muxed in
input	[11:3]	lsu_va_m;
input		sr_inst_e;
input		pr_inst_e;
input		hpr_inst_e;
input		sr_inst_m;
input		pr_inst_m;
input		hpr_inst_m;
input		altspace_ldst_e;
input		altspace_ldst_m;
input		ld_inst_vld_m;

output		legal_asi_va_m;
output		asi_legal_e;
output		asr_legal_m;
output		asi_sync_m;
output		asi_internal_e ;
output		asi_rngf_m;
output		asi_indet_m;
output		lendian_asi_m;
output		asi_sz_byte_m;
output		asi_sz_hw_m;
output		pst_asi_m;
output		asi_pst8_m;
output		asi_pst16_m;
output		asi_pst32_m;
output		asi_read_only_m;
output		asi_write_only_m;
output		quad_asi_m ;
output		binit_quad_asi_m ;
output		primary_asi_e ;
output		secondary_asi_e ;
output		real_asi_e;
output		as_if_user_asi_e ;
output		as_if_priv_asi_e ;
output		atomic_asi_m ;
output		blk_asi_e ;
output		nofault_asi_m ;
output		asi_iomap_m ;
output		asi_no_va_check_m ;

// CMP registers that reside off-chip and require IO mapping
assign asi_iomap_m = altspace_ldst_m & (
			(asi_m[7:0] == 8'h41) | 		// CMP registers
			(asi_m[7:0] == 8'h73) |			// ASI_SWVR_UDB_INTR_W
			(asi_m[7:0] == 8'h45 & lsu_va_m[4])	// SOC debug registers
			);

// Quad (These are duplicated - they can be shared)
assign	binit_quad_asi_m = altspace_ldst_m & (
        (asi_m[7:0] == 8'h27) | // asi_nucleus_blk_init_st_quad_ldd
        (asi_m[7:0] == 8'h2F) | // asi_nucleus_blk_init_st_quad_ldd_little
	(asi_m[7:0] == 8'h22) |	// asi_as_if_user_primary_quad_ldd (blk-init)
	(asi_m[7:0] == 8'h2A) |	// asi_as_if_user_primary_quad_ldd_little (blk-init)
	(asi_m[7:0] == 8'h23) |	// asi_as_if_user_secondary_quad_ldd (blk-init)
	(asi_m[7:0] == 8'h2B) |	// asi_as_if_user_secondary_quad_ldd_little (blk-init)
	(asi_m[7:0] == 8'hE2) |	// asi_primary_quad_ldd (blk-init)
	(asi_m[7:0] == 8'hEA) |	// asi_primary_quad_ldd_little (blk-init)
	(asi_m[7:0] == 8'hE3) |	// asi_secondary_quad_ldd (blk-init)
	(asi_m[7:0] == 8'hEB) 	// asi_secondary_quad_ldd_little (blk-init)
       );

assign	quad_asi_m = altspace_ldst_m & (
	binit_quad_asi_m      | // blk-init quad asi
	(asi_m[7:0] == 8'h26) | // asi_quad_ldd_real
	(asi_m[7:0] == 8'h2E) | // asi_quad_ldd_real_little
	(asi_m[7:0] == 8'h24) | // asi_nucleus_quad_ldd 
	(asi_m[7:0] == 8'h2C)   // asi_nucleus_quad_ldd_little 
       );
	
// Legal ASI's
assign asi_legal_e = (!asi_e[7]&!asi_e[6]&asi_e[4]&asi_e[2]&asi_e[1]&!asi_e[0]) | (
    asi_e[7]&asi_e[6]&!asi_e[3]&!asi_e[2]&!asi_e[1]) | (!asi_e[7]
    &asi_e[6]&!asi_e[5]&!asi_e[3]&asi_e[0]) | (!asi_e[7]&asi_e[6]
    &!asi_e[5]&asi_e[3]&!asi_e[0]) | (!asi_e[7]&asi_e[5]&!asi_e[4]
    &!asi_e[3]&asi_e[2]&asi_e[1]) | (!asi_e[7]&asi_e[6]&!asi_e[3]
    &!asi_e[2]&asi_e[1]&asi_e[0]) | (!asi_e[7]&!asi_e[6]&!asi_e[4]
    &asi_e[2]&!asi_e[1]&!asi_e[0]) | (asi_e[6]&!asi_e[5]&!asi_e[2]
    &asi_e[1]&!asi_e[0]) | (asi_e[6]&!asi_e[5]&!asi_e[2]&!asi_e[1]
    &asi_e[0]) | (asi_e[6]&!asi_e[5]&asi_e[4]&!asi_e[2]) | (!asi_e[7]
    &!asi_e[6]&asi_e[5]&!asi_e[4]&asi_e[1]) | (!asi_e[7]&!asi_e[6]
    &asi_e[5]&!asi_e[4]&!asi_e[3]) | (asi_e[7]&asi_e[6]&asi_e[4]&!asi_e[2]
    &!asi_e[1]) | (asi_e[7]&asi_e[6]&!asi_e[4]&!asi_e[2]&asi_e[1]) | (
    !asi_e[7]&!asi_e[6]&asi_e[4]&!asi_e[2]&!asi_e[1]) | (!asi_e[7]
    &!asi_e[5]&asi_e[4]&asi_e[2]) | (asi_e[7]&!asi_e[5]&!asi_e[4]
    &!asi_e[2]) | (asi_e[7]&asi_e[6]&!asi_e[5]&!asi_e[4]&!asi_e[1]) | (
    !asi_e[7]&asi_e[6]&asi_e[4]&!asi_e[3]&asi_e[2]&!asi_e[1]&!asi_e[0]) | (
    !asi_e[7]&asi_e[6]&asi_e[4]&!asi_e[3]&!asi_e[2]&asi_e[1]) | (
    !asi_e[7]&asi_e[6]&!asi_e[5]&asi_e[2]&asi_e[1]) | (!altspace_ldst_e);


assign asr_legal_m = (hpr_inst_m&asi_m[4]&asi_m[3]&asi_m[2]&asi_m[1]) | (
    !asi_m[4]&!asi_m[3]&!asi_m[2]&!asi_m[1]&!asi_m[0]) | (sr_inst_m
    &asi_m[4]&asi_m[3]&!asi_m[2]&!asi_m[0]) | (!sr_inst_m&!hpr_inst_m
    &!asi_m[4]&!asi_m[2]) | (!sr_inst_m&!hpr_inst_m&!asi_m[4]&!asi_m[3]) | (
    sr_inst_m&!asi_m[4]&asi_m[3]&asi_m[2]&asi_m[1]&asi_m[0]) | (
    !hpr_inst_m&!asi_m[4]&!asi_m[3]&!asi_m[2]&asi_m[1]) | (!sr_inst_m
    &!hpr_inst_m&!asi_m[4]&!asi_m[1]) | (sr_inst_m&!asi_m[3]&asi_m[2]
    &!asi_m[1]) | (!pr_inst_m&!hpr_inst_m&!asi_m[3]&!asi_m[2]&asi_m[1]
    &asi_m[0]) | (sr_inst_m&asi_m[4]&!asi_m[2]&!asi_m[1]) | (sr_inst_m
    &asi_m[4]&!asi_m[3]&asi_m[2]) | (!asi_m[4]&!asi_m[3]&!asi_m[2]
    &asi_m[1]&asi_m[0]) | (pr_inst_m&!asi_m[4]&!asi_m[0]) | (!hpr_inst_m
    &!asi_m[3]&!asi_m[2]&!asi_m[1]&!asi_m[0]) | (!sr_inst_m&!asi_m[4]
    &!asi_m[3]&!asi_m[1]&asi_m[0]) | (!asi_m[4]&!asi_m[3]&asi_m[2]
    &asi_m[1]&!asi_m[0]) | (!sr_inst_m&!pr_inst_m&!hpr_inst_m);

// ASI Internal Registers 
assign asi_internal_e = (altspace_ldst_e&asi_e[5]&asi_e[4]&!asi_e[2]&asi_e[1]) | (
    altspace_ldst_e&asi_e[6]&asi_e[5]&asi_e[2]) | (altspace_ldst_e
    &!asi_e[7]&!asi_e[4]&!asi_e[1]&asi_e[0]) | (altspace_ldst_e&asi_e[6]
    &asi_e[4]&asi_e[2]) | (altspace_ldst_e&asi_e[6]&asi_e[5]&!asi_e[4]
    &asi_e[3]&!asi_e[1]) | (altspace_ldst_e&!asi_e[6]&asi_e[4]&!asi_e[2]
    &asi_e[1]) | (altspace_ldst_e&!asi_e[7]&!asi_e[5]&!asi_e[4]&asi_e[1]) | (
    altspace_ldst_e&!asi_e[7]&!asi_e[4]&!asi_e[2]&!asi_e[1]) | (
    altspace_ldst_e&asi_e[5]&asi_e[4]&asi_e[1]&asi_e[0]) | (
    altspace_ldst_e&asi_e[6]&asi_e[2]&asi_e[1]) | (hpr_inst_e) | (
    sr_inst_e) | (pr_inst_e) | (altspace_ldst_e&asi_e[7]&!asi_e[6]
    &asi_e[5]) | (altspace_ldst_e&!asi_e[7]&asi_e[6]) | (altspace_ldst_e
    &asi_e[7]&!asi_e[6]&asi_e[4]) | (altspace_ldst_e&asi_e[7]&!asi_e[6]
    &asi_e[2]) | (altspace_ldst_e&asi_e[5]&asi_e[4]&asi_e[2]&!asi_e[1]);


// Diferentiate between fast and slow ring.
assign asi_rngf_m = (sr_inst_m&asi_m[4]&asi_m[2]) | (altspace_ldst_m&asi_m[3]
    &asi_m[1]&asi_m[0]) | (altspace_ldst_m&!asi_m[3]&!asi_m[2]&!asi_m[1]
    &asi_m[0]) | (altspace_ldst_m&asi_m[5]&!asi_m[1]) | (altspace_ldst_m
    &!asi_m[4]&!asi_m[2]&asi_m[1]&asi_m[0]) | (altspace_ldst_m&asi_m[2]
    &!asi_m[1]&!asi_m[0]) | (altspace_ldst_m&!asi_m[4]&asi_m[2]&!asi_m[1]) | (
    hpr_inst_m) | (altspace_ldst_m&asi_m[4]&!asi_m[2]&!asi_m[0]) | (
    sr_inst_m&asi_m[3]&!asi_m[1]) | (pr_inst_m&!asi_m[2]&!asi_m[1]
    &!asi_m[0]) | (altspace_ldst_m&asi_m[4]&asi_m[3]) | (pr_inst_m
    &!asi_m[3]) | (altspace_ldst_m&asi_m[3]&!asi_m[2]&asi_m[1]) | (
    sr_inst_m&!asi_m[4]&asi_m[0]) | (sr_inst_m&asi_m[2]&!asi_m[1]) | (
    altspace_ldst_m&asi_m[4]&asi_m[2]&asi_m[1]&asi_m[0]);


assign indet_m = (altspace_ldst_m&!asi_m[7]&asi_m[4]&asi_m[3]&!asi_m[2]
    &asi_m[1]) | (altspace_ldst_m&asi_m[6]&asi_m[4]&!asi_m[3]&asi_m[2]
    &!asi_m[1]&asi_m[0]) | (altspace_ldst_m&asi_m[6]&!asi_m[4]&!asi_m[3]
    &asi_m[2]&asi_m[1]) | (altspace_ldst_m&!asi_m[7]&!asi_m[5]&!asi_m[4]
    &asi_m[3]&!asi_m[2]) | (altspace_ldst_m&!asi_m[7]&asi_m[6]&!asi_m[5]
    &asi_m[4]&!asi_m[2]&asi_m[0]) | (pr_inst_m&~ld_inst_vld_m&asi_m[3]&!asi_m[2]
    &!asi_m[1]&asi_m[0]) | (altspace_ldst_m&asi_m[6]&!asi_m[3]&asi_m[2]
    &asi_m[1]&!asi_m[0]);

// ASI=0x40 / VA=0x30 and 0xA0 needs to be indeterminate as well
assign asi_indet_m = indet_m | (altspace_ldst_m & (asi_m[7:0] == 8'h40) &
                               ((lsu_va_m[7:5] == 3'b101) | (lsu_va_m[5:4] == 2'b11)));

// ASIs which sync on writes
assign asi_sync_m = (altspace_ldst_m&!asi_m[7]&asi_m[6]&asi_m[3]&!asi_m[0]) | (
    altspace_ldst_m&!asi_m[7]&asi_m[6]&!asi_m[3]&asi_m[1]) | (
    altspace_ldst_m&!asi_m[7]&!asi_m[4]&!asi_m[1]&asi_m[0]) | (
    hpr_inst_m) | (sr_inst_m) | (pr_inst_m) | (altspace_ldst_m&!asi_m[7]
    &asi_m[6]&asi_m[4]);

// Little Endian
assign lendian_asi_m = (altspace_ldst_m&!asi_m[6]&asi_m[3]) | (altspace_ldst_m
    &asi_m[7]&asi_m[3]);

// Size overrides for partial and short store ASIs
assign asi_sz_byte_m = (altspace_ldst_m&asi_m[7]&!asi_m[5]&asi_m[4]&!asi_m[1]);

assign asi_sz_hw_m = (altspace_ldst_m&asi_m[7]&asi_m[4]&asi_m[1]);

// Partial Store ASIs
assign pst_asi_m = altspace_ldst_m & (asi_m[7:4] == 4'hc);

assign asi_pst8_m = (altspace_ldst_m&asi_m[7]&asi_m[6]&!asi_m[5]&!asi_m[4]
    &!asi_m[2]&!asi_m[1]);
assign asi_pst16_m = (altspace_ldst_m&asi_m[7]&asi_m[6]&!asi_m[5]&!asi_m[4]
    &asi_m[1]);
assign asi_pst32_m = (altspace_ldst_m&asi_m[7]&asi_m[2]);

// Block ASI's
assign blk_asi_e = (altspace_ldst_e&!asi_e[6]&!asi_e[5]&asi_e[2]&asi_e[1]) | (
    altspace_ldst_e&asi_e[7]&asi_e[5]&!asi_e[1]);

// Atomic asi
assign atomic_asi_m = (!asi_m[6]&!asi_m[5]&!asi_m[2]&!asi_m[1]) | (!asi_m[6]
    &asi_m[5]&asi_m[4]) | (!asi_m[6]&!asi_m[5]&!asi_m[1]&!asi_m[0]) | (
    !altspace_ldst_m);

// Context selection
assign primary_asi_e = (asi_e[6]&!asi_e[0]) | (!asi_e[5]&asi_e[1]&!asi_e[0]) | (
    !asi_e[2]&!asi_e[0]) | (!altspace_ldst_e);

assign secondary_asi_e = (altspace_ldst_e&!asi_e[5]&asi_e[0]) | (
    altspace_ldst_e&!asi_e[2]&asi_e[0]);

assign real_asi_e = (altspace_ldst_e&!asi_e[6]&!asi_e[4]&asi_e[2]&asi_e[1]
    &!asi_e[0]) | (altspace_ldst_e&!asi_e[6]&asi_e[4]&asi_e[2]&!asi_e[1]);

assign as_if_user_asi_e = (altspace_ldst_e&!asi_e[6]&asi_e[5]&!asi_e[2]&asi_e[1]) | (
    altspace_ldst_e&!asi_e[6]&!asi_e[5]&asi_e[4]&!asi_e[2]) | (
    altspace_ldst_e&!asi_e[6]&!asi_e[5]&asi_e[2]&asi_e[1]);

assign as_if_priv_asi_e = (altspace_ldst_e&!asi_e[6]&asi_e[5]&asi_e[4]);

// No Fault
assign	nofault_asi_m = (altspace_ldst_m&asi_m[7]&!asi_m[6]&asi_m[1]);

// Read and write only ASI's
assign asi_read_only_m = (altspace_ldst_m&asi_m[5]&asi_m[4]&asi_m[2]&!asi_m[1]) | (
    altspace_ldst_m&asi_m[7]&!asi_m[6]&asi_m[1]) | (altspace_ldst_m
    &!asi_m[7]&asi_m[4]&asi_m[3]&!asi_m[2]&asi_m[1]) | (altspace_ldst_m
    &!asi_m[7]&asi_m[6]&!asi_m[5]&asi_m[4]&!asi_m[2]&asi_m[0]) | (
    altspace_ldst_m&!asi_m[7]&!asi_m[5]&!asi_m[4]&asi_m[3]&!asi_m[2]) | (
    altspace_ldst_m&!asi_m[7]&asi_m[6]&asi_m[5]&!asi_m[4]&!asi_m[2]) | (
    altspace_ldst_m&asi_m[6]&asi_m[4]&asi_m[2]&asi_m[1]&!asi_m[0]);

assign asi_write_only_m = (altspace_ldst_m&asi_m[5]&asi_m[4]&asi_m[1]&asi_m[0]) | (
    altspace_ldst_m&asi_m[6]&asi_m[5]&!asi_m[4]&!asi_m[1]) | (
    altspace_ldst_m&asi_m[6]&asi_m[4]&asi_m[2]&asi_m[1]&asi_m[0]) | (
    altspace_ldst_m&asi_m[6]&asi_m[4]&asi_m[3]&asi_m[2]&!asi_m[1]
    &!asi_m[0]) | (altspace_ldst_m&asi_m[7]&asi_m[6]&!asi_m[5]&!asi_m[4]);


// ASI's which do not require VA checking
assign asi_no_va_check_m = (altspace_ldst_m&asi_m[6]&asi_m[4]&asi_m[2]&asi_m[1]
    &asi_m[0]) | (altspace_ldst_m&asi_m[6]&!asi_m[4]&!asi_m[3]&asi_m[2]
    &asi_m[1]) | (altspace_ldst_m&!asi_m[7]&!asi_m[5]&!asi_m[4]&asi_m[3]
    &!asi_m[2]) | (altspace_ldst_m&!asi_m[7]&asi_m[6]&!asi_m[5]&asi_m[4]
    &!asi_m[2]&asi_m[0]);

// Valid ASI/VA combinations
assign legal_asi_va_m = (!asi_m[6]&asi_m[2]&!lsu_va_m[11]&!lsu_va_m[10]
    &lsu_va_m[9]&lsu_va_m[8]&lsu_va_m[7]&lsu_va_m[6]) | (!asi_m[6]
    &!asi_m[2]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]&lsu_va_m[3]) | (
    asi_m[5]&!asi_m[2]&!asi_m[1]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]
    &!lsu_va_m[9]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4]
    &!lsu_va_m[3]) | (asi_m[5]&!asi_m[4]&asi_m[1]&!lsu_va_m[11]
    &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]
    &!lsu_va_m[5]&!lsu_va_m[3]) | (asi_m[2]&!asi_m[0]&!lsu_va_m[11]
    &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]
    &!lsu_va_m[5]&!lsu_va_m[4]&!lsu_va_m[3]) | (asi_m[5]&!asi_m[4]
    &!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]
    &!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[4]) | (asi_m[5]&!asi_m[0]
    &!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]
    &!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]&!lsu_va_m[3]) | (!asi_m[5]
    &!asi_m[4]&!asi_m[2]&!asi_m[1]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]
    &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[6]&!lsu_va_m[4]&!lsu_va_m[3]) | (
    !asi_m[5]&!asi_m[2]&!asi_m[1]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]
    &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[5]
    &lsu_va_m[4]) | (!asi_m[5]&asi_m[4]&asi_m[2]&!lsu_va_m[11]
    &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]
    &!lsu_va_m[4]&!lsu_va_m[3]) | (!asi_m[4]&!asi_m[2]&!asi_m[0]
    &!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]
    &!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]&lsu_va_m[3]) | (asi_m[4]
    &asi_m[3]&asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[4]) | (!asi_m[4]
    &!asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4]
    &!lsu_va_m[3]) | (asi_m[4]&asi_m[3]&asi_m[1]&!lsu_va_m[11]
    &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]
    &!lsu_va_m[3]) | (!asi_m[5]&!asi_m[2]&!asi_m[1]&asi_m[0]&!lsu_va_m[11]
    &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&lsu_va_m[6]
    &lsu_va_m[5]&!lsu_va_m[4]) | (!asi_m[5]&!asi_m[2]&!asi_m[1]&asi_m[0]
    &!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]
    &lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4]) | (!asi_m[5]&!asi_m[3]
    &asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&lsu_va_m[6]) | (!asi_m[5]&!asi_m[3]
    &asi_m[2]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[3]) | (
    asi_m[4]&!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[4]&lsu_va_m[3]) | (
    asi_m[3]&!asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[4]&!lsu_va_m[3]) | (
    !asi_m[5]&!asi_m[3]&asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]
    &!lsu_va_m[9]&!lsu_va_m[8]&lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]) | (
    !asi_m[5]&!asi_m[3]&asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]
    &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&lsu_va_m[5]) | (asi_m[4]
    &!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[5]&lsu_va_m[4]) | (
    !asi_m[5]&!asi_m[4]&!asi_m[2]&!asi_m[1]&!asi_m[0]&!lsu_va_m[11]
    &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[6]&!lsu_va_m[5]) | (
    !asi_m[1]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]
    &!lsu_va_m[3]) | (!asi_m[5]&!asi_m[3]&asi_m[2]&!asi_m[0]&!lsu_va_m[11]
    &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&lsu_va_m[4]) | (
    !asi_m[5]&!asi_m[4]&!asi_m[1]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]
    &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[4]) | (
    !asi_m[5]&!asi_m[4]&!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]
    &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[3]) | (
    asi_m[6]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]
    &!lsu_va_m[3]) | (!asi_m[3]&asi_m[2]&asi_m[1]&!lsu_va_m[11]
    &!lsu_va_m[9]) | (asi_m[4]&!asi_m[1]&asi_m[0]&!lsu_va_m[11]
    &!lsu_va_m[9]) | (asi_m[4]&!asi_m[2]&!asi_m[1]&asi_m[0]) | (asi_m[3]
    &!asi_m[2]&!asi_m[1]&asi_m[0]) | (!asi_m[4]&!asi_m[3]&asi_m[2]
    &asi_m[1]) | (!asi_m[5]&asi_m[4]&asi_m[1]&asi_m[0]) | (asi_m[2]
    &asi_m[1]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]) | (!asi_m[4]&!asi_m[1]
    &!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]
    &!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]) | (!asi_m[5]&asi_m[4]
    &!asi_m[3]&!asi_m[2]&asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[5]&!lsu_va_m[4]
    &!lsu_va_m[3]) | (!asi_m[5]&asi_m[4]&!asi_m[3]&!asi_m[2]&asi_m[1]
    &!lsu_va_m[11]&!lsu_va_m[10]&lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]
    &!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[3]) | (!asi_m[5]&asi_m[4]
    &!asi_m[3]&asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[5]&!lsu_va_m[4]
    &!lsu_va_m[3]) | (!asi_m[5]&asi_m[4]&!asi_m[3]&asi_m[1]&!lsu_va_m[11]
    &!lsu_va_m[10]&!lsu_va_m[9]&lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]
    &!lsu_va_m[5]&lsu_va_m[3]) | (!asi_m[5]&asi_m[4]&!asi_m[3]&!asi_m[2]
    &asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&lsu_va_m[9]&!lsu_va_m[8]
    &!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4]) | (!asi_m[5]
    &asi_m[4]&!asi_m[3]&asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4]) | (
    asi_m[3]&!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]&!lsu_va_m[3]) | (
    asi_m[3]&!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]
    &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[5]&!lsu_va_m[4]&!lsu_va_m[3]) | (
    asi_m[4]&asi_m[3]&asi_m[2]&asi_m[1]&!lsu_va_m[11]) | (asi_m[4]
    &asi_m[3]&asi_m[0]&!lsu_va_m[11]) | (!asi_m[4]&asi_m[3]&!asi_m[2]
    &!asi_m[0]);


supply0 vss;
supply1 vdd;
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_arc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  lsu_arc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  ard_retl_ctl_1f, 
  ard_retl_vld_1f, 
  ard_retl_rd_1f, 
  ard_retl_tid_1f, 
  ard_retl_ack_1f, 
  ard_retl_exc_1f, 
  ard_retf_ctl_1f, 
  ard_retf_vld_1f, 
  ard_retf_rd_1f, 
  ard_retf_tid_1f, 
  ard_retf_ack_1f, 
  ard_retf_exc_1f, 
  lsu_asi_clken, 
  tlu_rngf_cdbus_error, 
  arc_retl_vld_2f, 
  arc_retf_vld_2f, 
  arc_sel_fast, 
  arc_pid_ctl_2f, 
  lsu_priv_action_g, 
  lsu_tid_g);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk_pm1;
wire arcl_retl_vld_1;
wire [1:0] arcl_retl_exc_1;
wire rngl_stg2_reg_scanin;
wire rngl_stg2_reg_scanout;
wire [1:0] arcl_retl_exc_2f;
wire arcl_retl_rd_2f;
wire [2:0] arcl_retl_tid_2f;
wire [6:0] arcl_pidl_ctl_2;
wire clr_local;
wire [6:0] arcl_pidl_ctl_3f;
wire rngl_stg3_reg_scanin;
wire rngl_stg3_reg_scanout;
wire arcl_retf_vld_1;
wire [1:0] arcl_retf_exc_1;
wire rngf_stg2_reg_scanin;
wire rngf_stg2_reg_scanout;
wire [1:0] arcl_retf_exc_2f;
wire arcl_retf_rd_2f;
wire [2:0] arcl_retf_tid_2f;
wire rngf_error_2f;
wire [6:0] arcl_pidf_ctl_2;
wire clr_fast;
wire [6:0] arcl_pidf_ctl_3f;
wire rngf_stg3_reg_scanin;
wire rngf_stg3_reg_scanout;
wire arc_sel_fast_2f;
wire spares_scanin;
wire spares_scanout;


// globals
input		l2clk;
input		scan_in;
input		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input		spc_aclk;
input		spc_bclk;
output		scan_out;

input		ard_retl_ctl_1f; // Control/Data bit from returning ring
input		ard_retl_vld_1f; // Valid/hold bit on returning ring
input		ard_retl_rd_1f;  // rd/wrx bit on returning ring
input	[2:0]	ard_retl_tid_1f; // Thread id on returning ring
input		ard_retl_ack_1f; // Ack bit returning on ring
input	[1:0]	ard_retl_exc_1f; // Exception status returning on ring

input		ard_retf_ctl_1f; // Control/Data bit from returning ring
input		ard_retf_vld_1f; // Valid/hold bit on returning ring
input		ard_retf_rd_1f;  // rd/wrx bit on returning ring
input	[2:0]   ard_retf_tid_1f; // Thread id on returning ring
input		ard_retf_ack_1f; // Ack bit returning on ring
input	[1:0]   ard_retf_exc_1f; // Exception status returning on ring

input		lsu_asi_clken;

input		tlu_rngf_cdbus_error;

output		arc_retl_vld_2f; // Valid data returned on the ring
output		arc_retf_vld_2f; // Valid data returned on the ring
output		arc_sel_fast;    // select fast ring data

output	[6:0]	arc_pid_ctl_2f;

output		lsu_priv_action_g;
output	[2:0]	lsu_tid_g;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

////////////////////////////////////////////////////////
lsu_arc_ctl_l1clkhdr_ctl_macro clkgen 
  (
   .l2clk(l2clk),
   .l1en (lsu_asi_clken ),
   .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));
////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////
// Return data coming from the ring. 
// This comes over two cycles. Combine
// into a single packet before returning.

// local ring

assign arcl_retl_vld_1 = ard_retl_ctl_1f & ard_retl_vld_1f;

// clear exceptions if no ack bit
assign arcl_retl_exc_1[1:0] = {ard_retl_ack_1f & ard_retl_exc_1f[1],
                               ard_retl_ack_1f & ard_retl_exc_1f[0]};


// Another staging register for the control bits.
lsu_arc_ctl_msff_ctl_macro__width_7 rngl_stg2_reg 
(
 .scan_in(rngl_stg2_reg_scanin),
 .scan_out(rngl_stg2_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  ({arcl_retl_vld_1,arcl_retl_exc_1[1:0],ard_retl_rd_1f,ard_retl_tid_1f[2:0]}),
 .dout ({arc_retl_vld_2f,arcl_retl_exc_2f[1:0],arcl_retl_rd_2f,arcl_retl_tid_2f[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

// stage the control bits for 1 more cycle to align it with output register 
// which holds data being returned to pid
// This is the output register and is loaded only when valid
// control is set in stage2. This can happen at the most every
// other cycle.
assign arcl_pidl_ctl_2[6:0] = ({7 { arc_retl_vld_2f}} & {arc_retl_vld_2f,arcl_retl_exc_2f[1:0],arcl_retl_rd_2f,arcl_retl_tid_2f[2:0]}) |
                              ({7 {~arc_retl_vld_2f & ~clr_local}} & arcl_pidl_ctl_3f[6:0]);

lsu_arc_ctl_msff_ctl_macro__width_7 rngl_stg3_reg 
(
 .scan_in(rngl_stg3_reg_scanin),
 .scan_out(rngl_stg3_reg_scanout),
 .l1clk(l1clk_pm1),
 .din (arcl_pidl_ctl_2[6:0]),
 .dout(arcl_pidl_ctl_3f[6:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

// Fast ring
assign arcl_retf_vld_1 = ard_retf_ctl_1f & ard_retf_vld_1f;
// clear exceptions if no ack bit
assign arcl_retf_exc_1[1:0] = {ard_retf_ack_1f & ard_retf_exc_1f[1],
                               ard_retf_ack_1f & ard_retf_exc_1f[0]};


// Another staging register for the control bits.
lsu_arc_ctl_msff_ctl_macro__width_8 rngf_stg2_reg 
(
 .scan_in(rngf_stg2_reg_scanin),
 .scan_out(rngf_stg2_reg_scanout),
 .l1clk(l1clk_pm1),
 .din  ({arcl_retf_vld_1,arcl_retf_exc_1[1:0],ard_retf_rd_1f,ard_retf_tid_1f[2:0],tlu_rngf_cdbus_error}),
 .dout ({arc_retf_vld_2f,arcl_retf_exc_2f[1:0],arcl_retf_rd_2f,arcl_retf_tid_2f[2:0],rngf_error_2f}),
  .siclk(siclk),
  .soclk(soclk)
 );

// stage the control bits for 1 more cycle to align it with
// data being returned to pid.
// This is the output register and is loaded only when valid
// control is set in stage2. This can happen at the most every
// other cycle.
// Set Fast bit (bit 4)

assign arcl_pidf_ctl_2[6:0] =
   ({7 { arc_retf_vld_2f}}              & {arc_retf_vld_2f,arcl_retf_exc_2f[1],(arcl_retf_exc_2f[0] | rngf_error_2f),
                                           arcl_retf_rd_2f,arcl_retf_tid_2f[2:0]}) |
   ({7 {~arc_retf_vld_2f & !clr_fast}}  & arcl_pidf_ctl_3f[6:0]);

lsu_arc_ctl_msff_ctl_macro__width_7 rngf_stg3_reg 
(
 .scan_in(rngf_stg3_reg_scanin),
 .scan_out(rngf_stg3_reg_scanout),
 .l1clk(l1clk_pm1),
 .din (arcl_pidf_ctl_2[6:0]),
 .dout(arcl_pidf_ctl_3f[6:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

// mux between the two output registers (fast and local). Give priority to the fast register.
// Once valid pkt is sent to pid, clear the corresponding output register.
// sel_fast if fast packet is valid (bit 7)

assign arc_sel_fast_2f = arcl_pidf_ctl_2[6];
assign arc_pid_ctl_2f[6:0] = arc_sel_fast_2f ? arcl_pidf_ctl_2[6:0]: arcl_pidl_ctl_2[6:0];

assign arc_sel_fast = arcl_pidf_ctl_3f[6];
assign clr_fast = arc_sel_fast;
assign clr_local = !arc_sel_fast & arcl_pidl_ctl_3f[6];

assign lsu_priv_action_g = arc_pid_ctl_2f[6] & arc_pid_ctl_2f[5] & ~arc_pid_ctl_2f[4];
assign lsu_tid_g[2:0] = arc_pid_ctl_2f[2:0];

lsu_arc_ctl_spare_ctl_macro spares (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);

supply0 vss;
supply1 vdd;
// fixscan start:
assign rngl_stg2_reg_scanin      = scan_in                  ;
assign rngl_stg3_reg_scanin      = rngl_stg2_reg_scanout    ;
assign rngf_stg2_reg_scanin      = rngl_stg3_reg_scanout    ;
assign rngf_stg3_reg_scanin      = rngf_stg2_reg_scanout    ;
assign spares_scanin             = rngf_stg3_reg_scanout    ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_arc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_arc_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_arc_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_arc_ctl_spare_ctl_macro (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_ard_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  lsu_ard_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  rngl_lsu_cdbus, 
  tlu_rngf_cdbus, 
  arc_retl_vld_2f, 
  arc_retf_vld_2f, 
  arc_sel_fast, 
  lsu_asi_clken, 
  ard_retl_ctl_1f, 
  ard_retl_vld_1f, 
  ard_retl_rd_1f, 
  ard_retl_tid_1f, 
  ard_retl_ack_1f, 
  ard_retl_exc_1f, 
  ard_retf_ctl_1f, 
  ard_retf_vld_1f, 
  ard_retf_rd_1f, 
  ard_retf_tid_1f, 
  ard_retf_ack_1f, 
  ard_retf_exc_1f, 
  ard_pid_data);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire i_rngl_stg1_reg_scanin;
wire i_rngl_stg1_reg_scanout;
wire [64:0] ardl_retl_pkt_1f;
wire i_rngl_stg2_reg_scanin;
wire i_rngl_stg2_reg_scanout;
wire [63:0] ardl_retl_pkt_2f;
wire i_rngf_stg1_reg_scanin;
wire i_rngf_stg1_reg_scanout;
wire [64:0] ardl_retf_pkt_1f;
wire i_rngf_stg2_reg_scanin;
wire i_rngf_stg2_reg_scanout;
wire [63:0] ardl_retf_pkt_2f;
wire [63:0] ardl_pid_data;


// globals
input 		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input 		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;


input	[64:0]	rngl_lsu_cdbus; // 64:0, 65 bit control/data bus coming from the ring
                              // 64    - ctl/data            
                              // 63    - valid/hole          
                              // 62    - ack            
                              // 61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR          
                              // 59    - rd/wrx              
                              // 58:56 - Thread ID           
                              // 55:48 - ASI field           
                              // 47:0  - Virtual Address     

input	[64:0]	tlu_rngf_cdbus; // 65 bit control/data bus from mmu (fast ring)


input		arc_retl_vld_2f; // valid data returned on the ring
input		arc_retf_vld_2f; // valid data returned on the ring

input		arc_sel_fast;    // select fast ring data to be returned to pid

input		lsu_asi_clken;

output		ard_retl_ctl_1f; // Control/Data bit from returning ring
output		ard_retl_vld_1f; // Valid/hold bit on returning ring
output		ard_retl_rd_1f;  // rd/wrx bit on returning ring
output	[2:0]	ard_retl_tid_1f; // Thread id on returning ring
output		ard_retl_ack_1f; // Ack bit returning on ring
output	[1:0]	ard_retl_exc_1f; // Exception status returning on ring

output		ard_retf_ctl_1f; // Control/Data bit from returning ring
output		ard_retf_vld_1f; // Valid/hold bit on returning ring
output		ard_retf_rd_1f;  // rd/wrx bit on returning ring
output	[2:0]	ard_retf_tid_1f; // Thread id on returning ring
output		ard_retf_ack_1f; // Ack bit returning on ring
output	[1:0]	ard_retf_exc_1f; // Exception status returning on ring
    
output	[63:0]	ard_pid_data;   // 63:0  - data being returned to pid

// scan renames
assign stop = 1'b0;
// end scan

lsu_ard_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_4 test_rep0   (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);


////////////////////////////////////////////////////////////////
//Return data coming over FAST and LOCAL RING
////////////////////////////////////////////////////////////////
//
//Latch Return packet coming from the ring
// This comes over two cycles. Combine
// into a single packet before returning to pid.
// Data comes simultaneously over the local ring and fast ring, but
// since it comes over 2 cycles and the data is returned to pid in
// 1 cycle, we can sustain simultaneous pipelined transfers on local
// and fast rings.
//

// Local  ring
lsu_ard_dp_msff_macro__stack_66c__width_65 i_rngl_stg1_reg  
(
 .scan_in(i_rngl_stg1_reg_scanin),
 .scan_out(i_rngl_stg1_reg_scanout),
 .clk (l2clk),
 .en  (lsu_asi_clken),
 .din (rngl_lsu_cdbus[64:0]),
 .dout(ardl_retl_pkt_1f[64:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// control bits are sent to arc where they are staged for
// two more cycles.
assign ard_retl_ctl_1f = ardl_retl_pkt_1f[64];
assign ard_retl_vld_1f = ardl_retl_pkt_1f[63];
assign ard_retl_rd_1f =  ardl_retl_pkt_1f[59];
assign ard_retl_tid_1f[2:0] = ardl_retl_pkt_1f[58:56];
assign ard_retl_ack_1f = ardl_retl_pkt_1f[62];
assign ard_retl_exc_1f[1:0] = ardl_retl_pkt_1f[49:48];

// Stage the data being sent to PID in the output register
// This register is loaded only when valid control is
// set in stage2. It implies that valid control came
// in the previous cycle. This can happen at the most
// every other cycle.
lsu_ard_dp_msff_macro__stack_66c__width_64 i_rngl_stg2_reg  
(
 .scan_in(i_rngl_stg2_reg_scanin),
 .scan_out(i_rngl_stg2_reg_scanout),
 .clk (l2clk),
 .en  (arc_retl_vld_2f),
 .din(ardl_retl_pkt_1f[63:0]),
 .dout(ardl_retl_pkt_2f[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Fast  ring
lsu_ard_dp_msff_macro__stack_66c__width_65 i_rngf_stg1_reg  
(
 .scan_in(i_rngf_stg1_reg_scanin),
 .scan_out(i_rngf_stg1_reg_scanout),
 .clk (l2clk),
 .en  (lsu_asi_clken),
 .din (tlu_rngf_cdbus[64:0]),
 .dout(ardl_retf_pkt_1f[64:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// control bits are sent to arc where they are staged for
// two more cycles.
assign ard_retf_ctl_1f = ardl_retf_pkt_1f[64];
assign ard_retf_vld_1f = ardl_retf_pkt_1f[63];
assign ard_retf_rd_1f =  ardl_retf_pkt_1f[59];
assign ard_retf_tid_1f[2:0] = ardl_retf_pkt_1f[58:56];
assign ard_retf_ack_1f = ardl_retf_pkt_1f[62];
assign ard_retf_exc_1f[1:0] = ardl_retf_pkt_1f[49:48];

// Stage the data being sent to PID in the output register
// This register is loaded only when valid control is
// set in stage2. It implies that valid control came
// in the previous cycle. This can happen at the most
// every other cycle.
lsu_ard_dp_msff_macro__stack_66c__width_64 i_rngf_stg2_reg  
(
 .scan_in(i_rngf_stg2_reg_scanin),
 .scan_out(i_rngf_stg2_reg_scanout),
 .clk (l2clk),
 .en  (arc_retf_vld_2f),
 .din(ardl_retf_pkt_1f[63:0]),
 .dout(ardl_retf_pkt_2f[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// Data being sent to PID aligns with the control being sent
// over arc_pid_ctl[6:0] from arc. Mux between the Fast Output
// register and the Local Output register.
lsu_ard_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 i_ret_pkt_mux  
(
 .din0( ardl_retf_pkt_2f[63:0]),
 .din1( ardl_retl_pkt_2f[63:0]),
 .sel0( arc_sel_fast),
 .dout( ardl_pid_data[63:0])
);

lsu_ard_dp_buff_macro__dbuff_32x__stack_66c__width_64 pid_data_buf  (
	.din (ardl_pid_data[63:0]),
	.dout(ard_pid_data[63:0])
);

// fixscan start:
assign i_rngl_stg1_reg_scanin    = scan_in                  ;
assign i_rngl_stg2_reg_scanin    = i_rngl_stg1_reg_scanout  ;
assign i_rngf_stg1_reg_scanin    = i_rngl_stg2_reg_scanout  ;
assign i_rngf_stg2_reg_scanin    = i_rngf_stg1_reg_scanout  ;
assign scan_out                  = i_rngf_stg2_reg_scanout  ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_ard_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_ard_dp_msff_macro__stack_66c__width_65 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_ard_dp_msff_macro__stack_66c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_ard_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_ard_dp_buff_macro__dbuff_32x__stack_66c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_asc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  lsu_asc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  asd_p2a_vld, 
  asd_p2a_fast, 
  asd_ring_ctl, 
  asd_ring_asi, 
  asd_ring_addr, 
  lsu_asi_clken, 
  sbc_pid_kill_store_p4_, 
  pic_st_asi_p4, 
  asc_ring_ctl, 
  asc_ring_data, 
  asc_ring_local, 
  asc_ring_fast, 
  asc_wr_p0ctxt, 
  asc_wr_p1ctxt, 
  asc_wr_s0ctxt, 
  asc_wr_s1ctxt, 
  asc_wr_pid, 
  asc_wrasi, 
  asc_pid_ack, 
  lsu_ring_ctl, 
  lsu_ifu_tid_w, 
  lsu_ifu_wr_p0ctxt, 
  lsu_ifu_wr_p1ctxt, 
  lsu_ifu_wr_pid);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk_pm1;
wire pid_ackl_c;
wire ascl_vld_1f;
wire hole_pend_f;
wire pid_ackf_c;
wire hole_vld_c;
wire ascl_vld_c;
wire ascl_vld_1_scanin;
wire ascl_vld_1_scanout;
wire asc_rngl_ctl_c;
wire asc_rngf_ctl_c;
wire asc_ring_ctl_c;
wire pid_ack_scanin;
wire pid_ack_scanout;
wire rngf_ctl;
wire rngl_ctl;
wire [3:0] count_c;
wire [3:0] count_f;
wire hole_count_scanin;
wire hole_count_scanout;
wire hole_pend_c;
wire create_tlb_hole;
wire hole_pend_state_scanin;
wire hole_pend_state_scanout;
wire rngf_unused;
wire asi_write;
wire asr_write;
wire asi_p0ctxt_wr;
wire asi_p1ctxt_wr;
wire asi_s0ctxt_wr;
wire asi_s1ctxt_wr;
wire asi_pid_wr;
wire wrasi;
wire dff_asr_wr_scanin;
wire dff_asr_wr_scanout;
wire [2:0] asr_wr_tid_2;
wire asi_p0ctxt_wr_2;
wire asi_p1ctxt_wr_2;
wire asi_s0ctxt_wr_2;
wire asi_s1ctxt_wr_2;
wire asi_pid_wr_2;
wire wrasi_2;
wire spares_scanin;
wire spares_scanout;


// globals
input		l2clk;
input		scan_in;
input		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input		spc_aclk;
input		spc_bclk;
output		scan_out;

input		asd_p2a_vld;    // valid packet from pid
input		asd_p2a_fast;   // packet from pid is destined for fast bus

input	[63:56]	asd_ring_ctl;   // Must look for DTLB writes to create hole
input	[7:0]	asd_ring_asi;
input	[8:3]	asd_ring_addr;
input		lsu_asi_clken;

input		sbc_pid_kill_store_p4_;
input		pic_st_asi_p4;

output		asc_ring_ctl;    // ring control to asd
output		asc_ring_data;   // ring data to asd
output		asc_ring_local;  // local ring to asd
output		asc_ring_fast;   // fast ring to asd

output	[7:0]	asc_wr_p0ctxt;
output	[7:0]	asc_wr_p1ctxt;
output	[7:0]	asc_wr_s0ctxt;
output	[7:0]	asc_wr_s1ctxt;
output	[7:0]	asc_wr_pid;
output	[7:0]	asc_wrasi;


output		asc_pid_ack;    // packet acknowledge to pid

output          lsu_ring_ctl;

output	[2:0]	lsu_ifu_tid_w;
output		lsu_ifu_wr_p0ctxt;
output		lsu_ifu_wr_p1ctxt;
output		lsu_ifu_wr_pid;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

////////////////////////////////////////////////////////
lsu_asc_ctl_l1clkhdr_ctl_macro clkgen 
  (
   .l2clk(l2clk),
   .l1en (lsu_asi_clken ),
   .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));
////////////////////////////////////////////////////////

////////////////////////////////////////////////////////
// generate an ack if a valid pid packet received and
// not launching the first cycle of a packet on the ring,
// and not in middle of a pending hole.

// generate a hole packet if a pending hole and
// not launching the first cycle of a packet on the ring.

assign pid_ackl_c = (asd_p2a_vld & !asd_p2a_fast & !ascl_vld_1f & !hole_pend_f);
assign pid_ackf_c = (asd_p2a_vld &  asd_p2a_fast & !ascl_vld_1f & !hole_pend_f);

// generate a hole every other cycle unless a pid_ack is being sent
assign hole_vld_c = ~(pid_ackl_c | pid_ackf_c) & !ascl_vld_1f;

// vld_c indicates a ctl pkt. Every other pkt is a control pkt (either a hole or an ack)
assign ascl_vld_c = ~ascl_vld_1f;

// register the first cycle valid signal
lsu_asc_ctl_msff_ctl_macro__width_1 ascl_vld_1 
(
 .scan_in(ascl_vld_1_scanin),
 .scan_out(ascl_vld_1_scanout),
 .l1clk(l1clk_pm1),
 .din  (ascl_vld_c),
 .dout (ascl_vld_1f),
  .siclk(siclk),
  .soclk(soclk)
 );

assign lsu_ring_ctl = ascl_vld_1f;


assign asc_pid_ack = pid_ackl_c | pid_ackf_c;

assign asc_rngl_ctl_c = ascl_vld_c & pid_ackl_c;
assign asc_rngf_ctl_c = ascl_vld_c & pid_ackf_c;
assign asc_ring_ctl_c = ascl_vld_c & (pid_ackf_c | pid_ackl_c);

assign asc_ring_ctl = asc_ring_ctl_c;

lsu_asc_ctl_msff_ctl_macro__width_3 pid_ack 
(
 .scan_in(pid_ack_scanin),
 .scan_out(pid_ack_scanout),
 .l1clk(l1clk_pm1),
 .din  ({asc_ring_ctl_c,asc_rngf_ctl_c,asc_rngl_ctl_c}),
 .dout ({asc_ring_data ,rngf_ctl,      rngl_ctl      }),
  .siclk(siclk),
  .soclk(soclk)
 );

assign asc_ring_local = (asc_rngl_ctl_c | rngl_ctl) & (sbc_pid_kill_store_p4_ | ~pic_st_asi_p4);
assign asc_ring_fast  = (asc_rngf_ctl_c | rngf_ctl) & (sbc_pid_kill_store_p4_ | ~pic_st_asi_p4);

/////////////////////////////////////////////////////////////
// HOLE INSERTION
/////////////////////////////////////////////////////////////
// Logic to insert hole every 16 cycles.
// Duplicated for fast and local rings
// 4 bit counter to insert a hole every 16 cycles
// This logic exists for local and fast rings
assign count_c[3:0] = count_f[3:0] + 4'b1;

lsu_asc_ctl_msff_ctl_macro__width_4 hole_count 
(
 .scan_in(hole_count_scanin),
 .scan_out(hole_count_scanout),
 .l1clk(l1clk_pm1),
 .din  (count_c[3:0]),
 .dout (count_f[3:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

// set state to indicate pending hole, clear when hole inserted

assign hole_pend_c = ((count_f[3:0] == 4'b0) | hole_pend_f | create_tlb_hole) & !hole_vld_c;

lsu_asc_ctl_msff_ctl_macro__width_1 hole_pend_state 
(
 .scan_in(hole_pend_state_scanin),
 .scan_out(hole_pend_state_scanout),
 .l1clk(l1clk_pm1),
 .din  (hole_pend_c),
 .dout (hole_pend_f),
  .siclk(siclk),
  .soclk(soclk)
 );

////////////////////////////////////////////////////////////
// There is a special case in which a hole must be created on the
// fast ring.  When a write to the DTLB_DATA_IN_REG goes out on the
// ring, a hold needs to be created afterwards to ensure that the
// bus is free to accomodate the tlb write.  (The MMU sends tlb
// reload information over the ASI bus.)

assign create_tlb_hole = rngf_ctl &	 				// ctl pkt
                         asd_ring_ctl[63] &				// valid
                         ~asd_ring_ctl[61] & ~asd_ring_ctl[60] &	// type=ASI
                         ~asd_ring_ctl[59] &				// write
                         ((asd_ring_asi[7:0] == 8'h5c) |		// ASI=DTLB_DATA_IN_REG
                          (asd_ring_asi[7:0] == 8'h5d) |		// ASI=DTLB_DATA_ACCESS_REG
                          (asd_ring_asi[7:0] == 8'h5f));		// ASI=DMMU_DEMAP

assign rngf_unused = asd_ring_ctl[62];


////////////////////////////////////////////////////////////
// Interface for ASI registers located in the LSU

assign asi_write = rngf_ctl & asd_ring_ctl[63] & ~asd_ring_ctl[61] & ~asd_ring_ctl[60] & ~asd_ring_ctl[59];
assign asr_write = rngf_ctl & asd_ring_ctl[63] & ~asd_ring_ctl[61] & asd_ring_ctl[60] & ~asd_ring_ctl[59];
assign asi_p0ctxt_wr = asi_write & (asd_ring_asi[7:0] == 8'h21) & (asd_ring_addr[8:3] == 6'b000001);
assign asi_p1ctxt_wr = asi_write & (asd_ring_asi[7:0] == 8'h21) & (asd_ring_addr[7:3] == 5'b00001);
assign asi_s0ctxt_wr = asi_write & (asd_ring_asi[7:0] == 8'h21) & (asd_ring_addr[8:3] == 6'b000010);
assign asi_s1ctxt_wr = asi_write & (asd_ring_asi[7:0] == 8'h21) & (asd_ring_addr[7:3] == 5'b00010);
assign asi_pid_wr    = asi_write & (asd_ring_asi[7:0] == 8'h58) &  asd_ring_addr[7];
assign wrasi         = asr_write & (asd_ring_asi[4:0] == 5'b00011);

lsu_asc_ctl_msff_ctl_macro__width_9 dff_asr_wr  (
  .scan_in(dff_asr_wr_scanin),
  .scan_out(dff_asr_wr_scanout),
  .l1clk(l1clk_pm1),
  .din	({asd_ring_ctl[58:56], asi_p0ctxt_wr,  asi_p1ctxt_wr,  asi_s0ctxt_wr,  asi_s1ctxt_wr,  asi_pid_wr,  wrasi}),
  .dout	({asr_wr_tid_2[2:0],    asi_p0ctxt_wr_2,asi_p1ctxt_wr_2,asi_s0ctxt_wr_2,asi_s1ctxt_wr_2,asi_pid_wr_2,wrasi_2}),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_ifu_tid_w[2:0] = asr_wr_tid_2[2:0]; 
assign lsu_ifu_wr_p0ctxt  = asi_p0ctxt_wr_2;
assign lsu_ifu_wr_p1ctxt  = asi_p1ctxt_wr_2;
assign lsu_ifu_wr_pid     = asi_pid_wr_2;

assign asc_wr_p0ctxt[0] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd0);
assign asc_wr_p0ctxt[1] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd1);
assign asc_wr_p0ctxt[2] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd2);
assign asc_wr_p0ctxt[3] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd3);
assign asc_wr_p0ctxt[4] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd4);
assign asc_wr_p0ctxt[5] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd5);
assign asc_wr_p0ctxt[6] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd6);
assign asc_wr_p0ctxt[7] = asi_p0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd7);

assign asc_wr_p1ctxt[0] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd0);
assign asc_wr_p1ctxt[1] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd1);
assign asc_wr_p1ctxt[2] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd2);
assign asc_wr_p1ctxt[3] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd3);
assign asc_wr_p1ctxt[4] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd4);
assign asc_wr_p1ctxt[5] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd5);
assign asc_wr_p1ctxt[6] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd6);
assign asc_wr_p1ctxt[7] = asi_p1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd7);

assign asc_wr_s0ctxt[0] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd0);
assign asc_wr_s0ctxt[1] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd1);
assign asc_wr_s0ctxt[2] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd2);
assign asc_wr_s0ctxt[3] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd3);
assign asc_wr_s0ctxt[4] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd4);
assign asc_wr_s0ctxt[5] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd5);
assign asc_wr_s0ctxt[6] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd6);
assign asc_wr_s0ctxt[7] = asi_s0ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd7);

assign asc_wr_s1ctxt[0] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd0);
assign asc_wr_s1ctxt[1] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd1);
assign asc_wr_s1ctxt[2] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd2);
assign asc_wr_s1ctxt[3] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd3);
assign asc_wr_s1ctxt[4] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd4);
assign asc_wr_s1ctxt[5] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd5);
assign asc_wr_s1ctxt[6] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd6);
assign asc_wr_s1ctxt[7] = asi_s1ctxt_wr_2 & (asr_wr_tid_2[2:0] == 3'd7);

assign asc_wr_pid[0] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd0);
assign asc_wr_pid[1] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd1);
assign asc_wr_pid[2] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd2);
assign asc_wr_pid[3] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd3);
assign asc_wr_pid[4] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd4);
assign asc_wr_pid[5] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd5);
assign asc_wr_pid[6] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd6);
assign asc_wr_pid[7] = asi_pid_wr_2 & (asr_wr_tid_2[2:0] == 3'd7);

assign asc_wrasi[0] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd0);
assign asc_wrasi[1] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd1);
assign asc_wrasi[2] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd2);
assign asc_wrasi[3] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd3);
assign asc_wrasi[4] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd4);
assign asc_wrasi[5] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd5);
assign asc_wrasi[6] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd6);
assign asc_wrasi[7] = wrasi_2 & (asr_wr_tid_2[2:0] == 3'd7);

lsu_asc_ctl_spare_ctl_macro spares (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);

supply0 vss;
supply1 vdd;
// fixscan start:
assign ascl_vld_1_scanin         = scan_in                  ;
assign pid_ack_scanin            = ascl_vld_1_scanout       ;
assign hole_count_scanin         = pid_ack_scanout          ;
assign hole_pend_state_scanin    = hole_count_scanout       ;
assign dff_asr_wr_scanin         = hole_pend_state_scanout  ;
assign spares_scanin             = dff_asr_wr_scanout       ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_asc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_asc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_asc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_asc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_asc_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_asc_ctl_spare_ctl_macro (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_asd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  lsu_asd_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  pid_asi_pkt, 
  asc_ring_ctl, 
  asc_ring_data, 
  asc_ring_local, 
  asc_ring_fast, 
  lsu_asi_clken, 
  lsu_ring_ctl, 
  asd_p2a_vld, 
  asd_p2a_fast, 
  lsu_rngf_cdbus, 
  lsu_rngl_cdbus, 
  lsu_ifu_ctxt_data, 
  asd_ring_ctl, 
  asd_ring_asi, 
  asd_ring_addr);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire i_pid_pkt_d2_reg_scanin;
wire i_pid_pkt_d2_reg_scanout;
wire [63:0] asdl_data_2f;
wire asdl_rngl_b63;
wire asdl_rngf_b63;
wire [62:0] asdl_ring_pkt;
wire i_rng_pkt_reg_scanin;
wire i_rng_pkt_reg_scanout;
wire asd_rngl_b63;
wire asd_rngf_b63;
wire [62:0] asd_ring_pkt;
wire lsu_rngl_cdbus_b63;
wire lsu_rngf_cdbus_b63;
wire [62:0] lsu_ring_cdbus;


// globals
input 		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input 		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;


input	[127:0]	pid_asi_pkt;    // 127:0, 128 bit packet coming from pid to ASI block
				// 127     - Valid           
				// 126     - Fast/Slow       
				// 125:124 - 00-ASI, 01-ASR, 10-PR, 11-HPR          
				// 123     - rd/wrx          
				// 122:120 - Thread ID       
				// 119:112 - ASI Field       
				// 111:64  - Virtual address 
				// 63:0    - Data            

input		asc_ring_ctl;	// ring control bit from asc
input		asc_ring_data;	// ring data bit from asc
input		asc_ring_local;	// local ring sending
input		asc_ring_fast;	// fast ring sending

input		lsu_asi_clken;
input		lsu_ring_ctl;

output		asd_p2a_vld;    // valid packet from pid
output		asd_p2a_fast;   // packet from pid is destined for fast bus


output	[64:0]	lsu_rngf_cdbus;
output	[64:0]	lsu_rngl_cdbus; 

output	[12:0]	lsu_ifu_ctxt_data;

output	[63:56]	asd_ring_ctl;
output	[7:0]	asd_ring_asi;
output	[8:3]	asd_ring_addr;

// scan renames
assign stop = 1'b0;
// end scan

lsu_asd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);

///////////////////////////////////////////////////////////////////
// PROCESS DATA FROM PID AND SEND IT OVER APPROPRIATE RING
///////////////////////////////////////////////////////////////////
//
//
// rename valid and Fast signal coming from the pid and send it to asc
assign asd_p2a_vld = pid_asi_pkt[127];
assign asd_p2a_fast = pid_asi_pkt[126];

// pipe data packet for one more cycle
// ctl and data packets are sent on the ring over two cycles
lsu_asd_dp_msff_macro__stack_66c__width_64 i_pid_pkt_d2_reg  
(
 .scan_in(i_pid_pkt_d2_reg_scanin),
 .scan_out(i_pid_pkt_d2_reg_scanout),
 .clk (l2clk),
 .en  (lsu_asi_clken),
 .din (pid_asi_pkt[63:0]),
 .dout(asdl_data_2f[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Mux between the data and control packet

lsu_asd_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_65 i_rng_pkt_mux  
(
 .din0( {asc_ring_local,  asc_ring_fast,   1'b0,pid_asi_pkt[125:64]}),          
 .din1( {asdl_data_2f[63],asdl_data_2f[63],asdl_data_2f[62:0]}),                     
 .sel0( asc_ring_ctl),
 .sel1( asc_ring_data),
 .dout( {asdl_rngl_b63,asdl_rngf_b63,asdl_ring_pkt[62:0]})
);

lsu_asd_dp_msff_macro__stack_66c__width_65 i_rng_pkt_reg  
(
 .scan_in(i_rng_pkt_reg_scanin),
 .scan_out(i_rng_pkt_reg_scanout),
 .clk (l2clk),
 .en  (lsu_asi_clken),
 .din ({asdl_rngl_b63,asdl_rngf_b63,asdl_ring_pkt[62:0]}),
 .dout({asd_rngl_b63, asd_rngf_b63, asd_ring_pkt[62:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign asd_ring_ctl[63:56] = {asd_rngf_b63,asd_ring_pkt[62:56]};
assign asd_ring_asi[7:0]   = asd_ring_pkt[55:48];
assign asd_ring_addr[8:3]  = asd_ring_pkt[8:3];

lsu_asd_dp_buff_macro__dbuff_16x__rep_1__stack_66c__width_13 ifu_rngf_buf     (
	.din	(asd_ring_pkt[12:0]),
	.dout	(lsu_ifu_ctxt_data[12:0])
);

// send packet over the ring
lsu_asd_dp_buff_macro__dbuff_16x__rep_1__stack_66c__width_65 ring_buf      (
	.din	({asd_rngl_b63,  asd_rngf_b63,  asd_ring_pkt[62:0]}),
	.dout	({lsu_rngl_cdbus_b63,lsu_rngf_cdbus_b63,lsu_ring_cdbus[62:0]})
);

lsu_asd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_65 rngf_buf     (
	.din	({lsu_ring_ctl,  lsu_rngf_cdbus_b63,  lsu_ring_cdbus[62:0]}),
	.dout	(lsu_rngf_cdbus[64:0])
);
lsu_asd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_65 rngl_buf     (
	.din	({lsu_ring_ctl,  lsu_rngl_cdbus_b63,  lsu_ring_cdbus[62:0]}),
	.dout	(lsu_rngl_cdbus[64:0])
);


// fixscan start:
assign i_pid_pkt_d2_reg_scanin   = scan_in                  ;
assign i_rng_pkt_reg_scanin      = i_pid_pkt_d2_reg_scanout ;
assign scan_out                  = i_rng_pkt_reg_scanout    ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_asd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_asd_dp_msff_macro__stack_66c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_asd_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_65 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [64:0] din0;
  input sel0;
  input [64:0] din1;
  input sel1;
  output [64:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(65)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
.dout(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_asd_dp_msff_macro__stack_66c__width_65 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


//
//   buff macro
//
//


module lsu_asd_dp_buff_macro__dbuff_16x__rep_1__stack_66c__width_13 (
  din, 
  dout);
  input [12:0] din;
  output [12:0] dout;


buff #(13)  d0_0 (
.in(din[12:0]),
.out(dout[12:0])
);


endmodule


//
//   buff macro
//
//


module lsu_asd_dp_buff_macro__dbuff_16x__rep_1__stack_66c__width_65 (
  din, 
  dout);
  input [64:0] din;
  output [64:0] dout;


buff #(65)  d0_0 (
.in(din[64:0]),
.out(dout[64:0])
);


endmodule


//
//   buff macro
//
//


module lsu_asd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_65 (
  din, 
  dout);
  input [64:0] din;
  output [64:0] dout;


buff #(65)  d0_0 (
.in(din[64:0]),
.out(dout[64:0])
);


endmodule


//
//   buff macro
//
//


module lsu_asd_dp_buff_macro__dbuff_16x__rep_1__stack_none__width_65 (
  din, 
  dout);
  input [64:0] din;
  output [64:0] dout;


buff #(65)  d0_0 (
.in(din[64:0]),
.out(dout[64:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_cic_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_cic_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  const_cpuid, 
  cpx_pkt_vld, 
  cid_d1_rtntyp, 
  cid_d1_wv, 
  cid_d1_tid, 
  cid_d1_rmo, 
  cid_d1_pref, 
  cid_d1_cpuid, 
  cid_d1_inval, 
  cid_tid, 
  cid_cpuid, 
  cid_pkt_type, 
  cid_xinval, 
  cid_pref, 
  cid_inv_vec, 
  cid_atomic, 
  cid_rmo_ack, 
  cid_set_inval, 
  cid_set_icinval, 
  cid_st_addr, 
  cid_st_vector, 
  cid_cpq_cmp_1, 
  cid_cpq_cmp_2, 
  cid_cpq_cmp_3, 
  dcc_cache_diag_wr_b, 
  dec_ld_inst_d, 
  fgu_fdiv_stall, 
  lmc_ldd_vld, 
  sbc_bst_sel, 
  mbi_run, 
  mbi_cpq_read_en, 
  mbi_cpq_write_en, 
  mbi_addr, 
  lbist_run, 
  cic_cpq_wptr, 
  cic_cpq_rptr, 
  cic_cpq_rd_en, 
  cic_cpq_wr_en, 
  cic_d1_sel, 
  cic_cpq_sel, 
  cic_fifo_sel, 
  cic_byp_sel, 
  cic_fifo_clken, 
  cic_l2fill_vld_e, 
  cic_cpq_ld_rdy, 
  cic_cpq_ld_rdy_, 
  cic_cpq_ld_sel, 
  cic_div_stall_d, 
  cic_st_update_e, 
  cic_rtn_cmplt, 
  cic_invalidate_e, 
  cic_xinval_e, 
  cic_set_inval, 
  cic_xinval, 
  cic_oddrd_e, 
  cic_st_dequeue, 
  cic_rmo_dequeue, 
  cic_st_ack, 
  cic_inv_wen_e, 
  cic_cpq_stall, 
  cic_diag_data_sel_e, 
  cic_ext_interrupt, 
  lsu_dcsoc_err_g, 
  lsu_ext_interrupt, 
  cic_mbi_run, 
  lsu_mbi_cpq_fail);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire [7:0] dec_cpuid;
wire [7:0] cpq_tid;
wire cpq_atomic;
wire cpq_rmo_ack;
wire dff_cpq_state_scanin;
wire dff_cpq_state_scanout;
wire state_fifo;
wire fifo_dff_enable;
wire last_state_fifo;
wire fifo_clken_last;
wire state_d1;
wire lsu_type_d1;
wire sel_byp_last;
wire cpq_pkt_done;
wire state_cpq;
wire [5:0] cpq_rptr;
wire [5:0] cpq_wptr;
wire sel_d1_last;
wire mbi_run_local;
wire block_cpq_d;
wire dff_cpq_sel_scanin;
wire dff_cpq_sel_scanout;
wire cpq_wr_en;
wire [5:0] cpq_wptr_inc;
wire [5:0] cpq_wptr_new;
wire dff_cpq_wptr_scanin;
wire dff_cpq_wptr_scanout;
wire cpq_rd_adv;
wire dff_cpq_rptr_scanin;
wire dff_cpq_rptr_scanout;
wire [5:0] cpq_rptr_new;
wire [5:0] cpq_rptr_inc;
wire fifo_empty;
wire [5:0] cpq_count;
wire cpq_gte_15;
wire reset_ll_cnt;
wire [2:0] ll_cnt_in;
wire [2:0] ll_cnt;
wire dff_ll_cnt_scanin;
wire dff_ll_cnt_scanout;
wire cpq_set_inval;
wire cpq_xinval;
wire cpq_local_pkt;
wire cpq_ld_type;
wire cpq_inv_type;
wire cpq_st_update;
wire cpq_evict_type;
wire cpq_st_type;
wire cpq_su_type;
wire cpq_ldd_type;
wire cpq_nonlsu_type;
wire cpq_ld_vld;
wire block_cpq_e;
wire cpq_st_vld;
wire cpq_su_vld;
wire cpq_inv_vld;
wire cpq_evict;
wire cpq_ldd_vld;
wire dff_ld_inst_e_scanin;
wire dff_ld_inst_e_scanout;
wire ld_inst_e;
wire [1:0] div_stall_in;
wire div_stall_d;
wire dff_div_stall_scanin;
wire dff_div_stall_scanout;
wire div_stall_e;
wire dcfill_active_e;
wire cic_ignore_fill_e;
wire ldd_2nd_pass;
wire cic_st_atm_cmplt;
wire st_dequeue;
wire ldd_1st_pass;
wire [15:0] evict_inv_wen;
wire [15:0] store_inv_wen;
wire next_ldd_2nd_pass;
wire dff_ldd_2nd_pass_scanin;
wire dff_ldd_2nd_pass_scanout;
wire lsu_dcsoc_err_e;
wire dff_dcl2_err_scanin;
wire dff_dcl2_err_scanout;
wire dff_diag_block_scanin;
wire dff_diag_block_scanout;
wire cpq_fail;
wire bist_cpq_cmp_en;
wire dff_bist_scanin;
wire dff_bist_scanout;
wire bist_cpq_rd_1;
wire spares_scanin;
wire spares_scanout;


// Globals
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input	[2:0]	const_cpuid;		// 0in const -message "const_cpuid changed!"

input		cpx_pkt_vld;

input	[4:0]	cid_d1_rtntyp;
input		cid_d1_wv;
input	[2:0]	cid_d1_tid;
input		cid_d1_rmo;
input		cid_d1_pref;
input	[2:0]	cid_d1_cpuid;
input	[1:0]	cid_d1_inval;

input	[2:0]	cid_tid;
input	[2:0]	cid_cpuid;
input	[4:0]	cid_pkt_type;
input		cid_xinval;
input		cid_pref;
input	[17:0]	cid_inv_vec;		// Invalidation vector
input		cid_atomic;
input		cid_rmo_ack;
input		cid_set_inval;
input		cid_set_icinval;
input	[5:4]	cid_st_addr;
input	[15:0]	cid_st_vector;
input		cid_cpq_cmp_1;
input		cid_cpq_cmp_2;
input		cid_cpq_cmp_3;

input		dcc_cache_diag_wr_b;	// must block returns for diag write
input		dec_ld_inst_d;

input		fgu_fdiv_stall;		// divide write to FRF W2 port pending

input	[7:0]	lmc_ldd_vld;		// LDD flags for each thread

input	[7:0]	sbc_bst_sel;

input		mbi_run;
input		mbi_cpq_read_en;
input		mbi_cpq_write_en;
input	[4:0]	mbi_addr;
input		lbist_run;

// CPQ control
output	[4:0]	cic_cpq_wptr;
output	[4:0]	cic_cpq_rptr;
output		cic_cpq_rd_en;
output		cic_cpq_wr_en;
output		cic_d1_sel;
output		cic_cpq_sel;
output		cic_fifo_sel;
output		cic_byp_sel;
output		cic_fifo_clken;

output		cic_l2fill_vld_e;	// Fill/bypass from L2 is proceeding
output		cic_cpq_ld_rdy;		// Fill/bypass is ready (but not necessarily happening)
output		cic_cpq_ld_rdy_;	// Fill/bypass is ready (but not necessarily happening)
output		cic_cpq_ld_sel;		// Load return is at head of queue
output		cic_div_stall_d;	// Divide is blocking the path to the regfiles
output		cic_st_update_e;	// Store update to D$ is happening
output		cic_rtn_cmplt;		// Load or atomic is complete
output		cic_invalidate_e;	// Invalidation is occuring
output		cic_xinval_e;		// Cross invalidate
output		cic_set_inval;
output	[7:0]	cic_xinval;		// xinval arrived on cpx
output		cic_oddrd_e;		// Second pass of a 2 pass load
output	[7:0]	cic_st_dequeue;		// Dequeue the store from the stb
output	[7:0]	cic_rmo_dequeue;
output	[7:0]	cic_st_ack;		// Store acks to each thread's stb
output	[15:0]	cic_inv_wen_e;		// Invalidation information
output		cic_cpq_stall;
output		cic_diag_data_sel_e;
output		cic_ext_interrupt;

output		lsu_dcsoc_err_g;
output		lsu_ext_interrupt;

output		cic_mbi_run;
output		lsu_mbi_cpq_fail;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

//////////////////////////////
// Clock header
//////////////////////////////

lsu_cic_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk                          ),
        .l1en   (1'b1                           ),
        .l1clk  (l1clk                          ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

assign dec_cpuid[0] = ~const_cpuid[2] & ~const_cpuid[1] & ~const_cpuid[0];
assign dec_cpuid[1] = ~const_cpuid[2] & ~const_cpuid[1] &  const_cpuid[0];
assign dec_cpuid[2] = ~const_cpuid[2] &  const_cpuid[1] & ~const_cpuid[0];
assign dec_cpuid[3] = ~const_cpuid[2] &  const_cpuid[1] &  const_cpuid[0];
assign dec_cpuid[4] =  const_cpuid[2] & ~const_cpuid[1] & ~const_cpuid[0];
assign dec_cpuid[5] =  const_cpuid[2] & ~const_cpuid[1] &  const_cpuid[0];
assign dec_cpuid[6] =  const_cpuid[2] &  const_cpuid[1] & ~const_cpuid[0];
assign dec_cpuid[7] =  const_cpuid[2] &  const_cpuid[1] &  const_cpuid[0];

assign cpq_tid[0] = ~cid_tid[2] & ~cid_tid[1] & ~cid_tid[0];
assign cpq_tid[1] = ~cid_tid[2] & ~cid_tid[1] &  cid_tid[0];
assign cpq_tid[2] = ~cid_tid[2] &  cid_tid[1] & ~cid_tid[0];
assign cpq_tid[3] = ~cid_tid[2] &  cid_tid[1] &  cid_tid[0];
assign cpq_tid[4] =  cid_tid[2] & ~cid_tid[1] & ~cid_tid[0];
assign cpq_tid[5] =  cid_tid[2] & ~cid_tid[1] &  cid_tid[0];
assign cpq_tid[6] =  cid_tid[2] &  cid_tid[1] & ~cid_tid[0];
assign cpq_tid[7] =  cid_tid[2] &  cid_tid[1] &  cid_tid[0];

assign cpq_atomic  = cid_atomic;
assign cpq_rmo_ack = cid_rmo_ack;

////////////////////////////////////////////////////////////////////////////////
// The CPX interface is built around a 32 entry FIFO (the CPQ).  Incoming
// packets queue in the FIFO (or bypass if the FIFO is empty).  Only the packet
// at the head of the FIFO can be dequeued. Packets which
// cause the dcache to update (cacheable loads from L2 and stores which update)
// must wait until there is no load instruction in the pipeline because the
// cache arrays are single ported.  Only packets processed by the LSU are 
// handled by this interface.  Ifill, SPU load, and MMU packets are ignored.
////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////
// FIFO and bypass management
// A packet can come from one of four sources:
// cpx  - direct bypass if fifo and bypass stages are empty
// d1   - 1st bypass stage (fifo written during this stage)
// cpq  - read data from fifo RAM
// fifo - data from fifo flop
////////////////////////////////////////////////////////////////////////////////

// FIFO/bypass state.  An asserted state bit indicates a valid, unprocessed
// packet exists in the respective stage.  If all are deasserted, packets bypass
// directly from the cpx.
lsu_cic_ctl_msff_ctl_macro__width_2 dff_cpq_state  (
	.scan_in(dff_cpq_state_scanin),
	.scan_out(dff_cpq_state_scanout),
	.din	({state_fifo, fifo_dff_enable}),
	.dout	({last_state_fifo,fifo_clken_last}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign state_d1 = lsu_type_d1 & ~(sel_byp_last & cpq_pkt_done);
assign state_cpq = (cpq_rptr[5:0] != cpq_wptr[5:0]) & ~(sel_d1_last & cpq_pkt_done);
assign state_fifo = (fifo_clken_last | last_state_fifo) & ~cpq_pkt_done;

assign fifo_dff_enable = state_cpq & ~state_fifo;
assign cic_fifo_clken = mbi_run_local | fifo_dff_enable;

// These are priority encoded versions used to mux return packets
// The aomux must output zeros for blocked packets and when in BIST mode.
assign cic_fifo_sel = state_fifo & ~block_cpq_d & ~mbi_run_local;
assign cic_cpq_sel  = state_cpq & ~state_fifo & ~block_cpq_d & ~mbi_run_local;
assign cic_d1_sel   = state_d1 & ~state_cpq & ~state_fifo & ~block_cpq_d & ~mbi_run_local;
assign cic_byp_sel  = ~state_d1 & ~state_cpq & ~state_fifo & ~block_cpq_d & ~mbi_run_local;

// 0in bits_on -var {cic_fifo_sel,cic_cpq_sel,cic_d1_sel,cic_byp_sel} -max 1 

lsu_cic_ctl_msff_ctl_macro__width_2 dff_cpq_sel  (
	.scan_in(dff_cpq_sel_scanin),
	.scan_out(dff_cpq_sel_scanout),
	.din	({cic_byp_sel, cic_d1_sel}),
	.dout	({sel_byp_last,sel_d1_last}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// CPQ write pointer and write enable
// All valid packets write into the fifo array.  (If timing allows for a predecode,
// I could supress the write of non-LSU packets.) In cycle d1, the packet will be decoded.
// If it wasn't an LSU type, the write pointer will not advance and the entry will be
// overwritten.

assign cpq_wr_en = cpx_pkt_vld;
assign cic_cpq_wr_en = (mbi_run_local | lbist_run) ? mbi_cpq_write_en : cpq_wr_en;

assign lsu_type_d1  = (cid_d1_rtntyp[4] & (cid_d1_rtntyp[2:0] == 3'b000) & ~cid_d1_pref)|	// loads
                      (cid_d1_rtntyp[4:0] == 5'b10100)					|	// store ack
                      ((cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv)			|	// ifill with inval
                      (cid_d1_rtntyp[4:0] == 5'b10011)					|	// eviction
                      (cid_d1_rtntyp[4:0] == 5'b10110)					|	// stream store ack
                      (cid_d1_rtntyp[4:0] == 5'b10111)					;	// interrupt return

assign cpq_wptr_inc[5:0] = cpq_wptr[5:0] + {6'b000001};
assign cpq_wptr_new[5:0] = lsu_type_d1 ? cpq_wptr_inc[5:0] : cpq_wptr[5:0];
assign cic_cpq_wptr[4:0] = mbi_run_local ? mbi_addr[4:0] : cpq_wptr_new[4:0];

lsu_cic_ctl_msff_ctl_macro__width_6 dff_cpq_wptr  (
	.scan_in(dff_cpq_wptr_scanin),
	.scan_out(dff_cpq_wptr_scanout),
	.din	(cpq_wptr_new[5:0]),
	.dout	(cpq_wptr[5:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//////////////////////////////////////////////////////////////////////////////////
// CPQ read pointer generation
// The read pointer increments if the a packet from a bypass stage is used or
// when the fifo_dff pops an entry.

assign cpq_rd_adv = (cpq_pkt_done & (sel_byp_last | sel_d1_last)) | fifo_dff_enable;

lsu_cic_ctl_msff_ctl_macro__width_6 dff_cpq_rptr  (
	.scan_in(dff_cpq_rptr_scanin),
	.scan_out(dff_cpq_rptr_scanout),
	.din	(cpq_rptr_new[5:0]),
	.dout	(cpq_rptr[5:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign cpq_rptr_inc[5:0] = cpq_rptr[5:0] + {6'b000001};
assign cpq_rptr_new[5:0] = cpq_rd_adv ? cpq_rptr_inc[5:0] : cpq_rptr[5:0];
assign cic_cpq_rptr[4:0] = mbi_run_local ? mbi_addr[4:0] : cpq_rptr_new[4:0];

/// CPQ will be read whenever there is a valid entry.
assign fifo_empty = (cpq_wptr_new[5:0] == cpq_rptr_new[5:0]);

assign cic_cpq_rd_en = mbi_run_local ? mbi_cpq_read_en : ~fifo_empty;

// Block the decode of any LSU op so the CPQ can drain.
// The CPQ cannot be allowed to rise above 16 entries used so that seven outstanding
// block loads can be accomodated.
 
assign cpq_count[5:0] = (cpq_wptr[5:0] - cpq_rptr[5:0]);

assign cpq_gte_15 = (cpq_count[5:0] >= 6'd15);

// To prevent livelock, request a stall if a packet is held at the head
// of the queue for 8 cycles.

assign reset_ll_cnt = cpq_pkt_done | ~(cic_d1_sel | cic_cpq_sel | cic_fifo_sel);

assign ll_cnt_in[2:0] = {3{~reset_ll_cnt}} & {ll_cnt[2:0] + 3'b001};
lsu_cic_ctl_msff_ctl_macro__width_3 dff_ll_cnt  (
	.scan_in(dff_ll_cnt_scanin),
	.scan_out(dff_ll_cnt_scanout),
	.din	(ll_cnt_in[2:0]),
	.dout	(ll_cnt[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign cic_cpq_stall = cpq_gte_15 | (&ll_cnt[2:0]);

// Assertion to check for cpq overflow
// 0in fifo -enq lsu_type_d1 -deq cpq_rd_adv -depth 32 -pass -registered 

////////////////////////////////////////////////////////////////////////////////
// Process the ready packet 
////////////////////////////////////////////////////////////////////////////////

assign cpq_set_inval = (cid_pkt_type[4:0] == 5'b10100) & cid_set_inval;
assign cpq_xinval    = (cid_pkt_type[4:0] == 5'b10001) & cid_xinval;			// ifill xinval
assign cpq_local_pkt = (cid_cpuid[2:0] == const_cpuid[2:0]);
assign cpq_ld_type   = cid_pkt_type[4] & (cid_pkt_type[2:0] == 3'b000) & ~cid_pref;	// load; no prefetch
assign cpq_inv_type  = (cid_pkt_type[4:0] == 5'b10011) | 				// eviction
                       ((cid_pkt_type[4:0] == 5'b10110) & cpq_st_update) |		// stream store ack
                       cpq_set_inval |							// set invalidate
                       ((cid_pkt_type[4:0] == 5'b10100) &
                         (~cpq_local_pkt | 						// non-local store ack
                           (cid_atomic & cpq_st_update) |				// atomic
                           (cid_rmo_ack & cpq_st_update)));				// BIS
assign cpq_evict_type= (cid_pkt_type[4:0] == 5'b10011);
assign cpq_st_type   = (cid_pkt_type[4:0] == 5'b10100 & cpq_local_pkt) &		// store ack
                       ~(cid_set_inval | cid_set_icinval);
assign cpq_su_type   = (cid_pkt_type[4:0] == 5'b10100) & cpq_local_pkt & 
                       cpq_st_update & ~(cid_set_icinval | cid_set_inval) &
                        ~cid_atomic & ~cid_rmo_ack;

assign cpq_st_update = (dec_cpuid[7] & cid_st_vector[15] & ~cid_st_vector[14]) |
                       (dec_cpuid[6] & cid_st_vector[13] & ~cid_st_vector[12]) |
                       (dec_cpuid[5] & cid_st_vector[11] & ~cid_st_vector[10]) |
                       (dec_cpuid[4] & cid_st_vector[9] & ~cid_st_vector[8]) |
                       (dec_cpuid[3] & cid_st_vector[7] & ~cid_st_vector[6]) |
                       (dec_cpuid[2] & cid_st_vector[5] & ~cid_st_vector[4]) |
                       (dec_cpuid[1] & cid_st_vector[3] & ~cid_st_vector[2]) |
                       (dec_cpuid[0] & cid_st_vector[1] & ~cid_st_vector[0]);

assign cpq_ldd_type = (cid_tid[2:0] == 3'b000) & cpq_ld_type & lmc_ldd_vld[0] |
                      (cid_tid[2:0] == 3'b001) & cpq_ld_type & lmc_ldd_vld[1] |
                      (cid_tid[2:0] == 3'b010) & cpq_ld_type & lmc_ldd_vld[2] |
                      (cid_tid[2:0] == 3'b011) & cpq_ld_type & lmc_ldd_vld[3] |
                      (cid_tid[2:0] == 3'b100) & cpq_ld_type & lmc_ldd_vld[4] |
                      (cid_tid[2:0] == 3'b101) & cpq_ld_type & lmc_ldd_vld[5] |
                      (cid_tid[2:0] == 3'b110) & cpq_ld_type & lmc_ldd_vld[6] |
                      (cid_tid[2:0] == 3'b111) & cpq_ld_type & lmc_ldd_vld[7] ;

assign cic_ext_interrupt = (cid_pkt_type[4:0] == 5'b10111);

// Because some packets may have been put into the queue that aren't interesting to the LSU,
// they need to be thrown away.
assign cpq_nonlsu_type = cid_pkt_type[4] & ~(cpq_ld_type | cpq_st_type | cpq_inv_type | cpq_evict_type | cpq_xinval);

// Operations must be qualifed with cpq blocks

assign cpq_ld_vld  = cpq_ld_type & ~block_cpq_e;
assign cpq_st_vld  = cpq_st_type & ~block_cpq_e;
assign cpq_su_vld  = cpq_su_type & ~block_cpq_e;
assign cpq_inv_vld = cpq_inv_type & ~block_cpq_e;
assign cpq_evict   = cpq_evict_type & ~block_cpq_e;
assign cpq_ldd_vld = cpq_ldd_type;

// This just blocks lmq load bypass and enables the data flop (for PM)
assign cic_cpq_ld_rdy = cpq_ld_vld;
assign cic_cpq_ld_rdy_ = ~cpq_ld_vld;

assign cic_set_inval = cpq_set_inval;

// This differentiates between load type and store/inv type.  It can
// only be used for mux selects because there is no guarantee that
// the operation will actually happen.
// NOTE: Further qualification with mbi_run and diag writes may be
//       required by the block(s) using this signal.
assign cic_cpq_ld_sel = ~cid_pkt_type[2] & ~cid_pkt_type[0];

// Invalidates can always be processed.  Invalidates come from evict and
// stream store packets and from non-local store acks.
assign cic_invalidate_e = cpq_inv_vld;
assign cic_xinval_e = cpq_xinval & ~block_cpq_e;

// The load instruction in D might get flushed in E, but because ldst_complete
// needs to go to pick in E, I don't have time to qualify it.  Therefore, a
// dcfill will only occur when there is no load instruction - flushed or not -
// coming down the pipe.

lsu_cic_ctl_msff_ctl_macro__width_1 dff_ld_inst_e  (
	.scan_in(dff_ld_inst_e_scanin),
	.scan_out(dff_ld_inst_e_scanout),
	.din	(dec_ld_inst_d),
	.dout	(ld_inst_e),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Divide results have highest priority to the W2 ports of the FRF.
// FGU will signal a stall to indicate that a result will be written in the
// future.  Fills cannot proceed when the result is being written.
// The timing is as below.  Use a shift register to track the stall.
//
//      |  D  |  E  |  M  
//  fdiv|     |     |  
// stall|     |     |  
//      |     |     |  

assign div_stall_in[1:0] = {fgu_fdiv_stall,div_stall_d}; 
lsu_cic_ctl_msff_ctl_macro__width_2 dff_div_stall  (
	.scan_in(dff_div_stall_scanin),
	.scan_out(dff_div_stall_scanout),
	.din	(div_stall_in[1:0]),
	.dout	({div_stall_d,div_stall_e}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign cic_div_stall_d = div_stall_d;		// send to lmc to block bypass

// The dcache can fill when the pipe is not blocked by a load or divide
assign dcfill_active_e = cpq_ld_vld & ~ld_inst_e & ~div_stall_e & ~block_cpq_e;
assign cic_l2fill_vld_e = dcfill_active_e;

// Don't restart the thread on the 1st pass of ldd or an atomic load
assign cic_ignore_fill_e = (cpq_ldd_vld & ~ldd_2nd_pass) | cpq_atomic;

assign cic_rtn_cmplt = (dcfill_active_e & ~cic_ignore_fill_e) | cic_st_atm_cmplt;

// Store updates follow the same rules to write to the cache as load fills;
// i.e. can't write if a load is coming down the pipe
assign cic_st_update_e = cpq_su_vld & ~ld_inst_e;

// Dequeue stores
assign st_dequeue = (cpq_su_vld & ~ld_inst_e) | (cpq_st_vld & ~cpq_su_vld);

assign cic_st_atm_cmplt = (cid_pkt_type[4:0] == 5'b10100 & cpq_local_pkt) & cid_atomic & ~block_cpq_e;

// Store deqeueing
// 0in bits_on -var {(cpq_tid[0] & st_dequeue & ~cpq_rmo_ack),sbc_bst_sel[0]} -max 1 -message "multiple dequeue in STB0"
// 0in bits_on -var {(cpq_tid[1] & st_dequeue & ~cpq_rmo_ack),sbc_bst_sel[1]} -max 1 -message "multiple dequeue in STB1"
// 0in bits_on -var {(cpq_tid[2] & st_dequeue & ~cpq_rmo_ack),sbc_bst_sel[2]} -max 1 -message "multiple dequeue in STB2"
// 0in bits_on -var {(cpq_tid[3] & st_dequeue & ~cpq_rmo_ack),sbc_bst_sel[3]} -max 1 -message "multiple dequeue in STB3"
// 0in bits_on -var {(cpq_tid[4] & st_dequeue & ~cpq_rmo_ack),sbc_bst_sel[4]} -max 1 -message "multiple dequeue in STB4"
// 0in bits_on -var {(cpq_tid[5] & st_dequeue & ~cpq_rmo_ack),sbc_bst_sel[5]} -max 1 -message "multiple dequeue in STB5"
// 0in bits_on -var {(cpq_tid[6] & st_dequeue & ~cpq_rmo_ack),sbc_bst_sel[6]} -max 1 -message "multiple dequeue in STB6"
// 0in bits_on -var {(cpq_tid[7] & st_dequeue & ~cpq_rmo_ack),sbc_bst_sel[7]} -max 1 -message "multiple dequeue in STB7"

assign cic_st_dequeue[7:0] = (cpq_tid[7:0] & {8{(st_dequeue & ~cpq_rmo_ack)}}) | sbc_bst_sel[7:0];
assign cic_rmo_dequeue[7:0] = cpq_tid[7:0] & {8{(cpq_st_vld & cpq_rmo_ack)}};

// store acks to respective store buffers - this is done when the packet is received
assign cic_st_ack[0] = ((cid_d1_rtntyp[4:0] == 5'b10100) & (cid_d1_cpuid[2:0] == const_cpuid[2:0]) &
                        ~cid_d1_rmo & (cid_d1_tid[2:0] == 3'd0) & ~(|cid_d1_inval[1:0]));
assign cic_st_ack[1] = ((cid_d1_rtntyp[4:0] == 5'b10100) & (cid_d1_cpuid[2:0] == const_cpuid[2:0]) &
                        ~cid_d1_rmo & (cid_d1_tid[2:0] == 3'd1) & ~(|cid_d1_inval[1:0]));
assign cic_st_ack[2] = ((cid_d1_rtntyp[4:0] == 5'b10100) & (cid_d1_cpuid[2:0] == const_cpuid[2:0]) &
                        ~cid_d1_rmo & (cid_d1_tid[2:0] == 3'd2) & ~(|cid_d1_inval[1:0]));
assign cic_st_ack[3] = ((cid_d1_rtntyp[4:0] == 5'b10100) & (cid_d1_cpuid[2:0] == const_cpuid[2:0]) &
                        ~cid_d1_rmo & (cid_d1_tid[2:0] == 3'd3) & ~(|cid_d1_inval[1:0]));
assign cic_st_ack[4] = ((cid_d1_rtntyp[4:0] == 5'b10100) & (cid_d1_cpuid[2:0] == const_cpuid[2:0]) &
                        ~cid_d1_rmo & (cid_d1_tid[2:0] == 3'd4) & ~(|cid_d1_inval[1:0]));
assign cic_st_ack[5] = ((cid_d1_rtntyp[4:0] == 5'b10100) & (cid_d1_cpuid[2:0] == const_cpuid[2:0]) &
                        ~cid_d1_rmo & (cid_d1_tid[2:0] == 3'd5) & ~(|cid_d1_inval[1:0]));
assign cic_st_ack[6] = ((cid_d1_rtntyp[4:0] == 5'b10100) & (cid_d1_cpuid[2:0] == const_cpuid[2:0]) &
                        ~cid_d1_rmo & (cid_d1_tid[2:0] == 3'd6) & ~(|cid_d1_inval[1:0]));
assign cic_st_ack[7] = ((cid_d1_rtntyp[4:0] == 5'b10100) & (cid_d1_cpuid[2:0] == const_cpuid[2:0]) &
                        ~cid_d1_rmo & (cid_d1_tid[2:0] == 3'd7) & ~(|cid_d1_inval[1:0]));

// The packet is done when it gets accepted into the pipeline.
assign cpq_pkt_done = ((dcfill_active_e & ~ldd_1st_pass) | cic_st_update_e) | (st_dequeue & ~cic_st_update_e) | 
                      cpq_inv_vld | cic_xinval_e | (cpq_nonlsu_type & (~sel_byp_last | lsu_type_d1));

//////////////////////////////////////////////////////////////////////////////
// Invalidation vector decoding
//////////////////////////////////////////////////////////////////////////////
// For evict inval. [13:0] = {A11[2:0],A10[3:0],A01[2:0],A00[3:0]}
// For store inval. [17:14] = {A[3:0]};

assign evict_inv_wen[15] = cid_inv_vec[11] & (cid_inv_vec[13:12] == 2'b11);
assign evict_inv_wen[14] = cid_inv_vec[11] & (cid_inv_vec[13:12] == 2'b10);
assign evict_inv_wen[13] = cid_inv_vec[11] & (cid_inv_vec[13:12] == 2'b01);
assign evict_inv_wen[12] = cid_inv_vec[11] & (cid_inv_vec[13:12] == 2'b00);

assign evict_inv_wen[11] = cid_inv_vec[8] & ~cid_inv_vec[7] & (cid_inv_vec[10:9] == 2'b11);
assign evict_inv_wen[10] = cid_inv_vec[8] & ~cid_inv_vec[7] & (cid_inv_vec[10:9] == 2'b10);
assign evict_inv_wen[9]  = cid_inv_vec[8] & ~cid_inv_vec[7] & (cid_inv_vec[10:9] == 2'b01);
assign evict_inv_wen[8]  = cid_inv_vec[8] & ~cid_inv_vec[7] & (cid_inv_vec[10:9] == 2'b00);

assign evict_inv_wen[7]  = cid_inv_vec[4] & (cid_inv_vec[6:5] == 2'b11);
assign evict_inv_wen[6]  = cid_inv_vec[4] & (cid_inv_vec[6:5] == 2'b10);
assign evict_inv_wen[5]  = cid_inv_vec[4] & (cid_inv_vec[6:5] == 2'b01);
assign evict_inv_wen[4]  = cid_inv_vec[4] & (cid_inv_vec[6:5] == 2'b00);

assign evict_inv_wen[3]  = cid_inv_vec[1] & ~cid_inv_vec[0] & (cid_inv_vec[3:2] == 2'b11);
assign evict_inv_wen[2]  = cid_inv_vec[1] & ~cid_inv_vec[0] & (cid_inv_vec[3:2] == 2'b10);
assign evict_inv_wen[1]  = cid_inv_vec[1] & ~cid_inv_vec[0] & (cid_inv_vec[3:2] == 2'b01);
assign evict_inv_wen[0]  = cid_inv_vec[1] & ~cid_inv_vec[0] & (cid_inv_vec[3:2] == 2'b00);

assign store_inv_wen[15] = ((cid_inv_vec[17:14] == 4'b1110) | cid_set_inval) & (cid_st_addr[5:4] == 2'b11);
assign store_inv_wen[14] = ((cid_inv_vec[17:14] == 4'b1010) | cid_set_inval) & (cid_st_addr[5:4] == 2'b11);
assign store_inv_wen[13] = ((cid_inv_vec[17:14] == 4'b0110) | cid_set_inval) & (cid_st_addr[5:4] == 2'b11);
assign store_inv_wen[12] = ((cid_inv_vec[17:14] == 4'b0010) | cid_set_inval) & (cid_st_addr[5:4] == 2'b11);

assign store_inv_wen[11] = ((cid_inv_vec[17:14] == 4'b1110) | cid_set_inval) & (cid_st_addr[5:4] == 2'b10);
assign store_inv_wen[10] = ((cid_inv_vec[17:14] == 4'b1010) | cid_set_inval) & (cid_st_addr[5:4] == 2'b10);
assign store_inv_wen[9]  = ((cid_inv_vec[17:14] == 4'b0110) | cid_set_inval) & (cid_st_addr[5:4] == 2'b10);
assign store_inv_wen[8]  = ((cid_inv_vec[17:14] == 4'b0010) | cid_set_inval) & (cid_st_addr[5:4] == 2'b10);

assign store_inv_wen[7]  = ((cid_inv_vec[17:14] == 4'b1110) | cid_set_inval) & (cid_st_addr[5:4] == 2'b01);
assign store_inv_wen[6]  = ((cid_inv_vec[17:14] == 4'b1010) | cid_set_inval) & (cid_st_addr[5:4] == 2'b01);
assign store_inv_wen[5]  = ((cid_inv_vec[17:14] == 4'b0110) | cid_set_inval) & (cid_st_addr[5:4] == 2'b01);
assign store_inv_wen[4]  = ((cid_inv_vec[17:14] == 4'b0010) | cid_set_inval) & (cid_st_addr[5:4] == 2'b01);

assign store_inv_wen[3]  = ((cid_inv_vec[17:14] == 4'b1110) | cid_set_inval) & (cid_st_addr[5:4] == 2'b00);
assign store_inv_wen[2]  = ((cid_inv_vec[17:14] == 4'b1010) | cid_set_inval) & (cid_st_addr[5:4] == 2'b00);
assign store_inv_wen[1]  = ((cid_inv_vec[17:14] == 4'b0110) | cid_set_inval) & (cid_st_addr[5:4] == 2'b00);
assign store_inv_wen[0]  = ((cid_inv_vec[17:14] == 4'b0010) | cid_set_inval) & (cid_st_addr[5:4] == 2'b00);

assign cic_inv_wen_e[15:0] = cpq_evict ? evict_inv_wen[15:0] : store_inv_wen[15:0];

//////////////////////////////////////////////////////////////////////////////
// LDD/QUAD/BLD control
//////////////////////////////////////////////////////////////////////////////

// 1st pass of ldd type instructions should not retire the packet or signal
// lsu_complete.  The load return of atomics should not signal complete either.
assign ldd_1st_pass = dcfill_active_e & cpq_ldd_vld & ~ldd_2nd_pass;

assign next_ldd_2nd_pass= (cpq_ldd_vld & (dcfill_active_e ^ ldd_2nd_pass)) | (ldd_2nd_pass & block_cpq_e);

lsu_cic_ctl_msff_ctl_macro__width_1 dff_ldd_2nd_pass  (
	.scan_in(dff_ldd_2nd_pass_scanin),
	.scan_out(dff_ldd_2nd_pass_scanout),
	.din	(next_ldd_2nd_pass),
	.dout	(ldd_2nd_pass),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign cic_oddrd_e = ldd_2nd_pass & dcfill_active_e;

//////////////////////////////////////////////////////////////////////////////
// xinval control
// Because the IFU does not queue incoming packets, there is the possibility
// that they process an ifill which requires D$ invalidation much earlier than
// the LSU.  This causes a problem because the fill will occur and the thread
// could miss again before the D$ inval occurs.  I will signal when an inval
// is pending.  During this time, the I$ will not service a miss from that thread.
//////////////////////////////////////////////////////////////////////////////

assign cic_xinval[0] = (cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv & (cid_d1_tid[2:0] == 3'b000);
assign cic_xinval[1] = (cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv & (cid_d1_tid[2:0] == 3'b001);
assign cic_xinval[2] = (cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv & (cid_d1_tid[2:0] == 3'b010);
assign cic_xinval[3] = (cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv & (cid_d1_tid[2:0] == 3'b011);
assign cic_xinval[4] = (cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv & (cid_d1_tid[2:0] == 3'b100);
assign cic_xinval[5] = (cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv & (cid_d1_tid[2:0] == 3'b101);
assign cic_xinval[6] = (cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv & (cid_d1_tid[2:0] == 3'b110);
assign cic_xinval[7] = (cid_d1_rtntyp[4:0] == 5'b10001) & cid_d1_wv & (cid_d1_tid[2:0] == 3'b111);


//////////////////////////////////////////////////////////////////////////////
// Must indicate to TLU whether a load error was L2 or SOC
//////////////////////////////////////////////////////////////////////////////

assign lsu_dcsoc_err_e = cid_pkt_type[3];

lsu_cic_ctl_msff_ctl_macro__width_2 dff_dcl2_err  (
	.scan_in(dff_dcl2_err_scanin),
	.scan_out(dff_dcl2_err_scanout),
	.din	({lsu_dcsoc_err_e,cic_ext_interrupt}),
	.dout	({lsu_dcsoc_err_g,lsu_ext_interrupt}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//////////////////////////////////////////////////////////////////////////////
// cpq must be blocked to accomodate diagnostic cache writes

assign block_cpq_d = dcc_cache_diag_wr_b;

lsu_cic_ctl_msff_ctl_macro__width_2 dff_diag_block  (
	.scan_in(dff_diag_block_scanin),
	.scan_out(dff_diag_block_scanout),
	.din	({block_cpq_d,block_cpq_d}),
	.dout	({block_cpq_e,cic_diag_data_sel_e}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// BIST
assign cpq_fail = bist_cpq_cmp_en & 
                          (~cid_cpq_cmp_1 | ~cid_cpq_cmp_2 | ~cid_cpq_cmp_3);

lsu_cic_ctl_msff_ctl_macro__width_4 dff_bist  (
	.scan_in(dff_bist_scanin),
	.scan_out(dff_bist_scanout),
	.din	({mbi_run,      mbi_cpq_read_en,bist_cpq_rd_1,  cpq_fail}),
	.dout	({mbi_run_local,bist_cpq_rd_1,  bist_cpq_cmp_en,lsu_mbi_cpq_fail}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// This drives to the cpq write mux.  BIST data must be selected during lbist mode to block
// the path from the cpx input pins.
assign cic_mbi_run = mbi_run_local | lbist_run;

//// Store ack packet should never have bits 125(BIS) and 129(atomic) asserted - move these to LSU
//// 0in custom -fire ((cpx_spc_data_cx[145:141] == 5'b10100) & cpx_spc_data_cx[125] & cpx_spc_data_cx[129]) -message "BIS and ATOMIC both set for store_ack packet"
//// Load rtn packet should never have bits 128(pf) and 129(atomic) asserted
//// 0in custom -fire ((cpx_spc_data_cx[145:141] == 5'b10000) & cpx_spc_data_cx[128] & cpx_spc_data_cx[129]) -message "PF and ATOMIC both set for load rtn packet"
//// Load rtn packet should have bit 137(nc) asserted if 129(atomic) asserted
//// 0in custom -fire ((cpx_spc_data_cx[145:141] == 5'b10000) & cpx_spc_data_cx[129] & ~cpx_spc_data_cx[137]) -message "ATOMIC load rtn packet expects NC=1"
//

lsu_cic_ctl_spare_ctl_macro__num_2 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_cpq_state_scanin      = scan_in                  ;
assign dff_cpq_sel_scanin        = dff_cpq_state_scanout    ;
assign dff_cpq_wptr_scanin       = dff_cpq_sel_scanout      ;
assign dff_cpq_rptr_scanin       = dff_cpq_wptr_scanout     ;
assign dff_ll_cnt_scanin         = dff_cpq_rptr_scanout     ;
assign dff_ld_inst_e_scanin      = dff_ll_cnt_scanout       ;
assign dff_div_stall_scanin      = dff_ld_inst_e_scanout    ;
assign dff_ldd_2nd_pass_scanin   = dff_div_stall_scanout    ;
assign dff_dcl2_err_scanin       = dff_ldd_2nd_pass_scanout ;
assign dff_diag_block_scanin     = dff_dcl2_err_scanout     ;
assign dff_bist_scanin           = dff_diag_block_scanout   ;
assign spares_scanin             = dff_bist_scanout         ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_cic_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cic_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cic_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cic_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cic_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cic_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_cic_ctl_spare_ctl_macro__num_2 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));
assign scan_out = so_1;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_cid_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_cid_dp (
  cpq_rdata, 
  cpx_spc_data_cx, 
  cic_byp_sel, 
  cic_d1_sel, 
  cic_cpq_sel, 
  cic_fifo_sel, 
  cic_fifo_clken, 
  cid_fill_data_e, 
  cid_l2miss, 
  cid_pkt_type, 
  cid_tid, 
  cid_tid_unbuf, 
  cid_cpuid, 
  cid_st_data_sel, 
  cid_xinval, 
  cid_pref, 
  cid_err, 
  cid_xway, 
  cid_st_addr, 
  cid_st_vector, 
  cid_st_bmask, 
  cid_st_way, 
  cid_inv_vec, 
  cid_inv_index, 
  cid_ncache, 
  cid_atomic, 
  cid_atomic_unbuf, 
  cid_rmo_ack, 
  cid_set_inval, 
  cid_set_icinval, 
  cid_cpq_wdata, 
  cid_dcsoc_err_e, 
  cid_d1_rtntyp, 
  cid_d1_tid, 
  cid_d1_cpuid, 
  cid_d1_wv, 
  cid_d1_rmo, 
  cid_d1_pref, 
  cid_d1_inval, 
  cid_cpq_cmp_1, 
  cid_cpq_cmp_2, 
  cid_cpq_cmp_3, 
  lsu_cpx_data, 
  lsu_cpx_cpkt, 
  lsu_cpx_valid, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  tcu_se_scancollar_out, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  const_cpuid, 
  mbi_run, 
  mbi_wdata, 
  bist_wdata_1, 
  bist_cmpsel_2);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [145:0] in_data;
wire dff_d1_0_scanin;
wire dff_d1_0_scanout;
wire [145:0] data_d1;
wire dff_d1_1_scanin;
wire dff_d1_1_scanout;
wire dff_d1_2_scanin;
wire dff_d1_2_scanout;
wire dff_d1_3_scanin;
wire dff_d1_3_scanout;
wire [145:0] cpq_read_data;
wire dff_fifo_0_scanin;
wire dff_fifo_0_scanout;
wire [145:0] fifo_data;
wire dff_fifo_1_scanin;
wire dff_fifo_1_scanout;
wire dff_fifo_2_scanin;
wire dff_fifo_2_scanout;
wire dff_fifo_3_scanin;
wire dff_fifo_3_scanout;
wire [145:0] cpq_mx_data;
wire dff_out_0_scanin;
wire dff_out_0_scanout;
wire [145:0] cpq_data_out;
wire dff_out_1_scanin;
wire dff_out_1_scanout;
wire dff_out_2_scanin;
wire dff_out_2_scanout;
wire dff_out_3_scanin;
wire dff_out_3_scanout;
wire [3:0] buf_unused;
wire [144:129] cid_pkt_data_e;
wire cid_pkt_unused;
wire [1:1] cid_unused;
wire [17:0] inv_vec;
wire dff_cmp_data_scanin;
wire dff_cmp_data_scanout;
wire [7:0] bist_cmp_data;
wire [72:0] fifo_cmp_data;


input	[145:0]	cpq_rdata;		// Read data from CPQ
input	[145:0]	cpx_spc_data_cx;	// CPX packet

input		cic_byp_sel;
input		cic_d1_sel;
input		cic_cpq_sel;
input		cic_fifo_sel;
input		cic_fifo_clken;

output	[127:0]	cid_fill_data_e;	// Fill data for dcache
output		cid_l2miss;
output	[4:0]	cid_pkt_type;
output	[2:0]	cid_tid;
output	[2:0]	cid_tid_unbuf;
output	[2:0]	cid_cpuid;
output		cid_st_data_sel;
output		cid_xinval;
output		cid_pref;
output	[1:0]	cid_err;
output	[1:0]	cid_xway;
output	[10:3]	cid_st_addr;		// Store update address
output	[15:0]	cid_st_vector;		// Store invalidate vector
output	[7:0]	cid_st_bmask;		// Store byte mask
output	[1:0]	cid_st_way;		// Dcache way to which store data gets written
output	[17:0]	cid_inv_vec;		// Invalidation data
output	[10:6]	cid_inv_index;		// Cache index for invalidation
output		cid_ncache;
output		cid_atomic;
output		cid_atomic_unbuf;
output		cid_rmo_ack;
output		cid_set_inval;
output		cid_set_icinval;
output	[145:0]	cid_cpq_wdata;
output		cid_dcsoc_err_e;

output	[4:0]	cid_d1_rtntyp;
output	[2:0]	cid_d1_tid;
output	[2:0]	cid_d1_cpuid;
output		cid_d1_wv;
output		cid_d1_rmo;
output		cid_d1_pref;
output	[1:0]	cid_d1_inval;

output		cid_cpq_cmp_1;
output		cid_cpq_cmp_2;
output		cid_cpq_cmp_3;

// Flopped versions to IFU
output	[127:0]	lsu_cpx_data;
output	[17:0]	lsu_cpx_cpkt;
output		lsu_cpx_valid;

// Globals 
input 		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input		tcu_se_scancollar_out;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input	[2:0]	const_cpuid;


// BIST
input		mbi_run;
input	[7:0]	mbi_wdata;
input	[7:0]	bist_wdata_1;
input		bist_cmpsel_2;

// scan renames
assign stop = 1'b0;
// end scan

lsu_cid_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);

assign in_data[145:0] = cpx_spc_data_cx[145:0];

lsu_cid_dp_msff_macro__stack_64c__width_64 dff_d1_0    (
	.scan_in(dff_d1_0_scanin),
	.scan_out(dff_d1_0_scanout),
	.clk	(l2clk),
	.en	(1'b1),
	.se	(tcu_se_scancollar_out),
        .din    (in_data[63:0]),
        .dout   (data_d1[63:0]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_d1_1    (
	.scan_in(dff_d1_1_scanin),
	.scan_out(dff_d1_1_scanout),
	.clk	(l2clk),
	.en	(1'b1),
	.se	(tcu_se_scancollar_out),
        .din    (in_data[127:64]),
        .dout   (data_d1[127:64]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_d1_2    (
	.scan_in(dff_d1_2_scanin),
	.scan_out(dff_d1_2_scanout),
	.clk	(l2clk),
	.en	(1'b1),
	.se	(tcu_se_scancollar_out),
        .din    ({in_data[128],in_data[130],in_data[132],in_data[134],in_data[136],in_data[138],
		  in_data[140],in_data[142],in_data[144]}),
        .dout   ({data_d1[128],data_d1[130],data_d1[132],data_d1[134],data_d1[136],data_d1[138],
		  data_d1[140],data_d1[142],data_d1[144]}),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_d1_3    (
	.scan_in(dff_d1_3_scanin),
	.scan_out(dff_d1_3_scanout),
	.clk	(l2clk),
	.en	(1'b1),
	.se	(tcu_se_scancollar_out),
        .din    ({in_data[129],in_data[131],in_data[133],in_data[135],in_data[137],in_data[139],
		  in_data[141],in_data[143],in_data[145]}),
        .dout   ({data_d1[129],data_d1[131],data_d1[133],data_d1[135],data_d1[137],data_d1[139],
		  data_d1[141],data_d1[143],data_d1[145]}),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign cid_d1_rtntyp[4:0] = data_d1[145:141];
assign cid_d1_tid[2:0]    = data_d1[136:134];
assign cid_d1_wv          = data_d1[133];
assign cid_d1_pref        = data_d1[128];
assign cid_d1_rmo         = lsu_cpx_data[125];
assign cid_d1_cpuid[2:0]  = lsu_cpx_data[120:118];
assign cid_d1_inval[1:0]  = lsu_cpx_data[124:123];

lsu_cid_dp_buff_macro__stack_64c__width_64 d1_data_buf_0    (
        .din    (data_d1[63:0]),
        .dout   (lsu_cpx_data[63:0])
);
lsu_cid_dp_buff_macro__stack_64c__width_64 d1_data_buf_1    (
        .din    (data_d1[127:64]),
        .dout   (lsu_cpx_data[127:64])
);
lsu_cid_dp_buff_macro__stack_10l__width_9 d1_data_buf_2    (
        .din    ({data_d1[128],    data_d1[130],    data_d1[132],    data_d1[134],    data_d1[136],
		  data_d1[138],    data_d1[140],    data_d1[142],    data_d1[144]}),
        .dout   ({lsu_cpx_cpkt[0],lsu_cpx_cpkt[2],lsu_cpx_cpkt[4],lsu_cpx_cpkt[6],lsu_cpx_cpkt[8],
		  lsu_cpx_cpkt[10],lsu_cpx_cpkt[12],lsu_cpx_cpkt[15],lsu_cpx_cpkt[17]})
);
lsu_cid_dp_buff_macro__stack_10l__width_9 d1_data_buf_3    (
        .din    ({data_d1[129],    data_d1[131],    data_d1[133],    data_d1[135],
		  data_d1[137],    data_d1[139],    data_d1[141],    data_d1[143],    data_d1[145]}),
        .dout   ({lsu_cpx_cpkt[1],lsu_cpx_cpkt[3],lsu_cpx_cpkt[5],lsu_cpx_cpkt[7],
		  lsu_cpx_cpkt[9],lsu_cpx_cpkt[11],lsu_cpx_cpkt[14],lsu_cpx_cpkt[16],lsu_cpx_valid})
);
assign lsu_cpx_cpkt[13] = 1'b0;

lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_64c__width_64 cpq_data_buf_0     (
	.din	(cpq_rdata[63:0]),
	.dout	(cpq_read_data[63:0])
);
lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_64c__width_64 cpq_data_buf_1     (
	.din	(cpq_rdata[127:64]),
	.dout	(cpq_read_data[127:64])
);
lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_10l__width_9 cpq_data_buf_2     (
        .din    ({cpq_rdata[128],cpq_rdata[130],cpq_rdata[132],cpq_rdata[134],cpq_rdata[136],cpq_rdata[138],
		  cpq_rdata[140],cpq_rdata[142],cpq_rdata[144]}),
        .dout    ({cpq_read_data[128],cpq_read_data[130],cpq_read_data[132],cpq_read_data[134],cpq_read_data[136],cpq_read_data[138],
		  cpq_read_data[140],cpq_read_data[142],cpq_read_data[144]})
);
lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_10l__width_9 cpq_data_buf_3     (
        .din    ({cpq_rdata[129],cpq_rdata[131],cpq_rdata[133],cpq_rdata[135],cpq_rdata[137],cpq_rdata[139],
		  cpq_rdata[141],cpq_rdata[143],cpq_rdata[145]}),
        .dout    ({cpq_read_data[129],cpq_read_data[131],cpq_read_data[133],cpq_read_data[135],cpq_read_data[137],cpq_read_data[139],
		  cpq_read_data[141],cpq_read_data[143],cpq_read_data[145]})
);

lsu_cid_dp_msff_macro__stack_64c__width_64 dff_fifo_0    (
	.scan_in(dff_fifo_0_scanin),
	.scan_out(dff_fifo_0_scanout),
	.se	(tcu_se_scancollar_out),
	.clk	(l2clk),
	.en	(cic_fifo_clken),
        .din    (cpq_read_data[63:0]),
        .dout   (fifo_data[63:0]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_fifo_1    (
	.scan_in(dff_fifo_1_scanin),
	.scan_out(dff_fifo_1_scanout),
	.se	(tcu_se_scancollar_out),
	.clk	(l2clk),
	.en	(cic_fifo_clken),
        .din    (cpq_read_data[127:64]),
        .dout   (fifo_data[127:64]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_fifo_2    (
	.scan_in(dff_fifo_2_scanin),
	.scan_out(dff_fifo_2_scanout),
	.se	(tcu_se_scancollar_out),
	.clk	(l2clk),
	.en	(cic_fifo_clken),
        .din    ({cpq_read_data[128],cpq_read_data[130],cpq_read_data[132],cpq_read_data[134],cpq_read_data[136],cpq_read_data[138],
		  cpq_read_data[140],cpq_read_data[142],cpq_read_data[144]}),
        .dout   ({fifo_data[128],fifo_data[130],fifo_data[132],fifo_data[134],fifo_data[136],fifo_data[138],
		  fifo_data[140],fifo_data[142],fifo_data[144]}),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_fifo_3    (
	.scan_in(dff_fifo_3_scanin),
	.scan_out(dff_fifo_3_scanout),
	.se	(tcu_se_scancollar_out),
	.clk	(l2clk),
	.en	(cic_fifo_clken),
        .din    ({cpq_read_data[129],cpq_read_data[131],cpq_read_data[133],cpq_read_data[135],cpq_read_data[137],cpq_read_data[139],
		  cpq_read_data[141],cpq_read_data[143],cpq_read_data[145]}),
        .dout   ({fifo_data[129],fifo_data[131],fifo_data[133],fifo_data[135],fifo_data[137],fifo_data[139],
		  fifo_data[141],fifo_data[143],fifo_data[145]}),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 cpq_mx_0      (
        .din0   (fifo_data[63:0]),
        .din1   (cpq_read_data[63:0]),
        .din2   (data_d1[63:0]),
        .din3   (in_data[63:0]),
	.sel0	(cic_fifo_sel),
	.sel1	(cic_cpq_sel),
	.sel2	(cic_d1_sel),
	.sel3	(cic_byp_sel),
        .dout   (cpq_mx_data[63:0])
);
lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 cpq_mx_1      (
        .din0   (fifo_data[127:64]),
        .din1   (cpq_read_data[127:64]),
        .din2   (data_d1[127:64]),
        .din3   (in_data[127:64]),
	.sel0	(cic_fifo_sel),
	.sel1	(cic_cpq_sel),
	.sel2	(cic_d1_sel),
	.sel3	(cic_byp_sel),
        .dout   (cpq_mx_data[127:64])
);
lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_10l__width_9 cpq_mx_2      (
        .din0   ({fifo_data[128],fifo_data[130],fifo_data[132],fifo_data[134],fifo_data[136],fifo_data[138],
		  fifo_data[140],fifo_data[142],fifo_data[144]}),
        .din1   ({cpq_read_data[128],cpq_read_data[130],cpq_read_data[132],cpq_read_data[134],cpq_read_data[136],cpq_read_data[138],
		  cpq_read_data[140],cpq_read_data[142],cpq_read_data[144]}),
        .din2   ({data_d1[128],data_d1[130],data_d1[132],data_d1[134],data_d1[136],data_d1[138],
		  data_d1[140],data_d1[142],data_d1[144]}),
        .din3   ({in_data[128],in_data[130],in_data[132],in_data[134],in_data[136],in_data[138],
		  in_data[140],in_data[142],in_data[144]}),
	.sel0	(cic_fifo_sel),
	.sel1	(cic_cpq_sel),
	.sel2	(cic_d1_sel),
	.sel3	(cic_byp_sel),
        .dout   ({cpq_mx_data[128],cpq_mx_data[130],cpq_mx_data[132],cpq_mx_data[134],cpq_mx_data[136],cpq_mx_data[138],
		  cpq_mx_data[140],cpq_mx_data[142],cpq_mx_data[144]})
);
lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_10l__width_9 cpq_mx_3      (
        .din0   ({fifo_data[129],fifo_data[131],fifo_data[133],fifo_data[135],fifo_data[137],fifo_data[139],
		  fifo_data[141],fifo_data[143],fifo_data[145]}),
        .din1   ({cpq_read_data[129],cpq_read_data[131],cpq_read_data[133],cpq_read_data[135],cpq_read_data[137],cpq_read_data[139],
		  cpq_read_data[141],cpq_read_data[143],cpq_read_data[145]}),
        .din2   ({data_d1[129],data_d1[131],data_d1[133],data_d1[135],data_d1[137],data_d1[139],
		  data_d1[141],data_d1[143],data_d1[145]}),
        .din3   ({in_data[129],in_data[131],in_data[133],in_data[135],in_data[137],in_data[139],
		  in_data[141],in_data[143],in_data[145]}),
	.sel0	(cic_fifo_sel),
	.sel1	(cic_cpq_sel),
	.sel2	(cic_d1_sel),
	.sel3	(cic_byp_sel),
        .dout   ({cpq_mx_data[129],cpq_mx_data[131],cpq_mx_data[133],cpq_mx_data[135],cpq_mx_data[137],cpq_mx_data[139],
		  cpq_mx_data[141],cpq_mx_data[143],cpq_mx_data[145]})
);

lsu_cid_dp_msff_macro__stack_64c__width_64 dff_out_0    (
	.scan_in(dff_out_0_scanin),
	.scan_out(dff_out_0_scanout),
	.se	(tcu_se_scancollar_out),
	.clk	(l2clk),
	.en	(1'b1),		// should have PM here, but need enough time to see incoming packet
        .din    (cpq_mx_data[63:0]),
        .dout   (cpq_data_out[63:0]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_out_1    (
	.scan_in(dff_out_1_scanin),
	.scan_out(dff_out_1_scanout),
	.se	(tcu_se_scancollar_out),
	.clk	(l2clk),
	.en	(1'b1),
        .din    (cpq_mx_data[127:64]),
        .dout   (cpq_data_out[127:64]),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_out_2    (
	.scan_in(dff_out_2_scanin),
	.scan_out(dff_out_2_scanout),
	.se	(tcu_se_scancollar_out),
	.clk	(l2clk),
	.en	(1'b1),
        .din    ({cpq_mx_data[128],cpq_mx_data[130],cpq_mx_data[132],cpq_mx_data[134],cpq_mx_data[136],cpq_mx_data[138],
		  cpq_mx_data[140],cpq_mx_data[142],cpq_mx_data[144]}),
        .dout   ({cpq_data_out[128],cpq_data_out[130],cpq_data_out[132],cpq_data_out[134],cpq_data_out[136],cpq_data_out[138],
		  cpq_data_out[140],cpq_data_out[142],cpq_data_out[144]}),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_cid_dp_msff_macro__stack_10l__width_10 dff_out_3    (
	.scan_in(dff_out_3_scanin),
	.scan_out(dff_out_3_scanout),
	.se	(tcu_se_scancollar_out),
	.clk	(l2clk),
	.en	(1'b1),
        .din    ({cpq_mx_data[143],cpq_mx_data[129],cpq_mx_data[131],cpq_mx_data[133],cpq_mx_data[135],cpq_mx_data[137],
		  cpq_mx_data[139],cpq_mx_data[141],cpq_mx_data[143],cpq_mx_data[145]}),
        .dout   ({cid_st_data_sel,  cpq_data_out[129],cpq_data_out[131],cpq_data_out[133],cpq_data_out[135],cpq_data_out[137],
		  cpq_data_out[139],cpq_data_out[141],cpq_data_out[143],cpq_data_out[145]}),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign cid_tid_unbuf[2:0] = cpq_data_out[136:134];
assign cid_pref           = cpq_data_out[128];
assign cid_pkt_type[4:0]  = cpq_data_out[145:141];
assign cid_atomic_unbuf   = cpq_data_out[129];

lsu_cid_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_64 fill_data_buf_0    (
        .din    (cpq_data_out[63:0]),
        .dout   (cid_fill_data_e[63:0])
);
lsu_cid_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_64 fill_data_buf_1    (
        .din    (cpq_data_out[127:64]),
        .dout   (cid_fill_data_e[127:64])
);
lsu_cid_dp_buff_macro__rep_1__stack_10l__width_9 fill_data_buf_2    (
        .din    ({1'b0,         cpq_data_out[130],  cpq_data_out[132],  cpq_data_out[134],  cpq_data_out[136],
		  cpq_data_out[138],  cpq_data_out[140],  1'b0,         cpq_data_out[144]}),
        .dout   ({buf_unused[0],cid_pkt_data_e[130],cid_pkt_data_e[132],cid_pkt_data_e[134],cid_pkt_data_e[136],
		  cid_pkt_data_e[138],cid_pkt_data_e[140],buf_unused[1],cid_pkt_data_e[144]})
);
lsu_cid_dp_buff_macro__rep_1__stack_10l__width_9 fill_data_buf_3    (
        .din    ({cpq_data_out[129],  cpq_data_out[131],  cpq_data_out[133],  cpq_data_out[135],
		  cpq_data_out[137],  cpq_data_out[139],  1'b0,         cpq_data_out[143],  1'b0}),
        .dout   ({cid_pkt_data_e[129],cid_pkt_data_e[131],cid_pkt_data_e[133],cid_pkt_data_e[135],
		  cid_pkt_data_e[137],cid_pkt_data_e[139],buf_unused[2],cid_pkt_data_e[143],buf_unused[3]})
);

lsu_cid_dp_buff_macro__width_3 misc_data_buf  (
	.din	(cpq_data_out[120:118]),
	.dout	(cid_cpuid[2:0])
); 

assign cid_rmo_ack       = cid_fill_data_e[125];
assign cid_set_icinval   = cid_fill_data_e[124];
assign cid_set_inval     = cid_fill_data_e[123];
assign cid_st_addr[5:4]  = cid_fill_data_e[122:121];
assign cid_st_addr[10:6] = cid_fill_data_e[116:112];
assign cid_st_addr[3]    = cid_fill_data_e[104];
assign cid_st_bmask[7:0] = cid_fill_data_e[103:96];
assign cid_st_vector[15:0]= {cid_fill_data_e[93:92],cid_fill_data_e[89:88],cid_fill_data_e[85:84],cid_fill_data_e[81:80],
                             cid_fill_data_e[77:76],cid_fill_data_e[73:72],cid_fill_data_e[69:68],cid_fill_data_e[65:64]};

assign cid_inv_index[10:6] = cid_st_addr[10:6];

assign cid_dcsoc_err_e     = cid_pkt_data_e[144];
assign cid_pkt_unused      = cid_pkt_data_e[143];
assign cid_l2miss          = cid_pkt_data_e[140];
assign cid_err[1:0]        = cid_pkt_data_e[139:138];
assign cid_ncache          = cid_pkt_data_e[137];
assign cid_tid[2:0]        = cid_pkt_data_e[136:134];
assign cid_xinval          = cid_pkt_data_e[133];
assign cid_xway[1:0]       = cid_pkt_data_e[132:131];
assign cid_unused[1]       = cid_pkt_data_e[130];
assign cid_atomic          = cid_pkt_data_e[129];

////////////////////////////////////////////////////////////////////////////////
// Invalidate processing
// Invalidation vectors have the following format.
// Vectors for store ack packets contain the first 32 bits only.
// [31:0]   = {cpu7[3:0],cpu6[3:0],...,cpu1[3:0],cpu0[3:0]} for addr[5:4]=00
// [55:32]  = {cpu7[2:0],cpu6[2:0],...,cpu1[2:0],cpu0[2:0]} for addr[5:4]=01
// [87:56]  = {cpu7[3:0],cpu6[3:0],...,cpu1[3:0],cpu0[3:0]} for addr[5:4]=10
// [111:88] = {cpu7[2:0],cpu6[2:0],...,cpu1[2:0],cpu0[2:0]} for addr[5:4]=11

//Select the invalidation info specific to this cpu
lsu_cid_dp_mux_macro__mux_aodec__ports_8__stack_18l__width_18 inv_vec_mx     (
	.din0	({cid_fill_data_e[67:64],cid_fill_data_e[90:88],cid_fill_data_e[59:56],cid_fill_data_e[34:32],cid_fill_data_e[3:0]}),
	.din1	({cid_fill_data_e[71:68],cid_fill_data_e[93:91],cid_fill_data_e[63:60],cid_fill_data_e[37:35],cid_fill_data_e[7:4]}),
	.din2	({cid_fill_data_e[75:72],cid_fill_data_e[96:94],cid_fill_data_e[67:64],cid_fill_data_e[40:38],cid_fill_data_e[11:8]}),
	.din3	({cid_fill_data_e[79:76],cid_fill_data_e[99:97],cid_fill_data_e[71:68],cid_fill_data_e[43:41],cid_fill_data_e[15:12]}),
	.din4	({cid_fill_data_e[83:80],cid_fill_data_e[102:100],cid_fill_data_e[75:72],cid_fill_data_e[46:44],cid_fill_data_e[19:16]}),
	.din5	({cid_fill_data_e[87:84],cid_fill_data_e[105:103],cid_fill_data_e[79:76],cid_fill_data_e[49:47],cid_fill_data_e[23:20]}),
	.din6	({cid_fill_data_e[91:88],cid_fill_data_e[108:106],cid_fill_data_e[83:80],cid_fill_data_e[52:50],cid_fill_data_e[27:24]}),
	.din7	({cid_fill_data_e[95:92],cid_fill_data_e[111:109],cid_fill_data_e[87:84],cid_fill_data_e[55:53],cid_fill_data_e[31:28]}),
	.sel	(const_cpuid[2:0]),
	.dout	(inv_vec[17:0])
);

lsu_cid_dp_buff_macro__stack_18l__width_18 inv_vec_buf   ( 
	.din	(inv_vec[17:0]),
	.dout	(cid_inv_vec[17:0])
);

assign cid_st_way[1:0] = cid_inv_vec[17:16];

////////////////////////////////////////////////////////////////////////////////
// BIST

// Flop compare data
lsu_cid_dp_msff_macro__stack_8l__width_8 dff_cmp_data   (
	.scan_in(dff_cmp_data_scanin),
	.scan_out(dff_cmp_data_scanout),
	.din	(bist_wdata_1[7:0]),
	.dout	(bist_cmp_data[7:0]),
	.clk	(l2clk),
	.en	(mbi_run),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Write data mux
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 bist_wdata_mx_0      (
        .din0   ({8{mbi_wdata[7:0]}}),
        .din1   (in_data[63:0]),
	.sel0	(mbi_run),
        .dout   (cid_cpq_wdata[63:0])
);
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 bist_wdata_mx_1      (
        .din0   ({8{mbi_wdata[7:0]}}),
        .din1   (in_data[127:64]),
	.sel0	(mbi_run),
        .dout   (cid_cpq_wdata[127:64])
);
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_10l__width_9 bist_wdata_mx_2      (
        .din0   ({mbi_wdata[0],mbi_wdata[7:0]}),
        .din1   ({in_data[128],in_data[130],in_data[132],in_data[134],in_data[136],in_data[138],
		  in_data[140],in_data[142],in_data[144]}),
	.sel0	(mbi_run),
        .dout   ({cid_cpq_wdata[128],cid_cpq_wdata[130],cid_cpq_wdata[132],cid_cpq_wdata[134],cid_cpq_wdata[136],
		  cid_cpq_wdata[138],cid_cpq_wdata[140],cid_cpq_wdata[142],cid_cpq_wdata[144]})
);
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_10l__width_9 bist_wdata_mx_3      (
        .din0   ({mbi_wdata[0],mbi_wdata[7:0]}),
        .din1   ({in_data[129],in_data[131],in_data[133],in_data[135],in_data[137],in_data[139],
		  in_data[141],in_data[143],in_data[145]}),
	.sel0	(mbi_run),
        .dout   ({cid_cpq_wdata[129],cid_cpq_wdata[131],cid_cpq_wdata[133],cid_cpq_wdata[135],cid_cpq_wdata[137],
		  cid_cpq_wdata[139],cid_cpq_wdata[141],cid_cpq_wdata[143],cid_cpq_wdata[145]})
);

// Read data mux

lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 cpq_bist_mx_0      (
        .din0   (fifo_data[127:64]),
        .din1   (fifo_data[63:0]),
	.sel0	(bist_cmpsel_2),
        .dout   (fifo_cmp_data[63:0])
);
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_10l__width_9 cpq_bist_mx_2      (
        .din0   ({fifo_data[129],fifo_data[131],fifo_data[133],fifo_data[135],fifo_data[137],fifo_data[139],
		  fifo_data[141],fifo_data[143],fifo_data[145]}),
        .din1   ({fifo_data[128],fifo_data[130],fifo_data[132],fifo_data[134],fifo_data[136],fifo_data[138],
		  fifo_data[140],fifo_data[142],fifo_data[144]}),
	.sel0	(bist_cmpsel_2),
        .dout   (fifo_cmp_data[72:64])
);

// Comparators

lsu_cid_dp_cmp_macro__width_64 bist_cmp1  (
	.din0	({8{bist_cmp_data[7:0]}}),
	.din1	({fifo_cmp_data[63:0]}),
	.dout	(cid_cpq_cmp_1)
);
lsu_cid_dp_cmp_macro__width_16 bist_cmp2  (
	.din0	({2{bist_cmp_data[7:0]}}),
	.din1	({bist_cmp_data[7:1],fifo_cmp_data[72:64]}),
	.dout	(cid_cpq_cmp_2)
);
assign cid_cpq_cmp_3 = 1'b1;


// fixscan start:
assign dff_d1_0_scanin           = scan_in                  ;
assign dff_d1_1_scanin           = dff_d1_0_scanout         ;
assign dff_d1_2_scanin           = dff_d1_1_scanout         ;
assign dff_d1_3_scanin           = dff_d1_2_scanout         ;
assign dff_fifo_0_scanin         = dff_d1_3_scanout         ;
assign dff_fifo_1_scanin         = dff_fifo_0_scanout       ;
assign dff_fifo_2_scanin         = dff_fifo_1_scanout       ;
assign dff_fifo_3_scanin         = dff_fifo_2_scanout       ;
assign dff_out_0_scanin          = dff_fifo_3_scanout       ;
assign dff_out_1_scanin          = dff_out_0_scanout        ;
assign dff_out_2_scanin          = dff_out_1_scanout        ;
assign dff_out_3_scanin          = dff_out_2_scanout        ;
assign dff_cmp_data_scanin       = dff_out_3_scanout        ;
assign scan_out                  = dff_cmp_data_scanout     ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cid_dp_msff_macro__stack_64c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cid_dp_msff_macro__stack_10l__width_9 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [7:0] so;

  input [8:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [8:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__stack_10l__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_10l__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  output [63:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_10l__width_9 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [8:0] din0;
  input sel0;
  input [8:0] din1;
  input sel1;
  input [8:0] din2;
  input sel2;
  input [8:0] din3;
  input sel3;
  output [8:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(9)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[8:0]),
  .in1(din1[8:0]),
  .in2(din2[8:0]),
  .in3(din3[8:0]),
.dout(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cid_dp_msff_macro__stack_10l__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__rep_1__stack_10l__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


buff #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


buff #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_cid_dp_mux_macro__mux_aodec__ports_8__stack_18l__width_18 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [17:0] din0;
  input [17:0] din1;
  input [17:0] din2;
  input [17:0] din3;
  input [17:0] din4;
  input [17:0] din5;
  input [17:0] din6;
  input [17:0] din7;
  input [2:0] sel;
  output [17:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(18)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[17:0]),
  .in1(din1[17:0]),
  .in2(din2[17:0]),
  .in3(din3[17:0]),
  .in4(din4[17:0]),
  .in5(din5[17:0]),
  .in6(din6[17:0]),
  .in7(din7[17:0]),
.dout(dout[17:0])
);


endmodule


//
//   buff macro
//
//


module lsu_cid_dp_buff_macro__stack_18l__width_18 (
  din, 
  dout);
  input [17:0] din;
  output [17:0] dout;


buff #(18)  d0_0 (
.in(din[17:0]),
.out(dout[17:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_cid_dp_msff_macro__stack_8l__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_10l__width_9 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [8:0] din0;
  input [8:0] din1;
  input sel0;
  output [8:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(9)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[8:0]),
  .in1(din1[8:0]),
.dout(dout[8:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_cid_dp_cmp_macro__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output dout;


cmp #(64)  m0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_cid_dp_cmp_macro__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output dout;


cmp #(16)  m0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout)
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_dac_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_dac_ctl (
  dcc_ld_inst_vld_m, 
  dcc_l2fill_vld_m, 
  dcc_lendian_pre_m, 
  dcc_bendian_byp_m, 
  dcc_baddr_m, 
  dcc_ld_sz_m, 
  dcc_signed_m, 
  lmc_asi_bypass_m, 
  lmc_byp_vld_m, 
  tlb_cache_way_hit_b, 
  lmd_misc_msb_m, 
  dca_msb_w0_b, 
  dca_msb_w1_b, 
  dca_msb_w2_b, 
  dca_msb_w3_b, 
  dac_swap7_byte0_l, 
  dac_swap7_byte3_l, 
  dac_swap7_byte4_l, 
  dac_swap7_byte7_l, 
  dac_swap6_byte1_l, 
  dac_swap6_byte2_l, 
  dac_swap6_byte5_l, 
  dac_swap6_byte6_l, 
  dac_swap5_byte1_l, 
  dac_swap5_byte2_l, 
  dac_swap5_byte5_l, 
  dac_swap5_byte6_l, 
  dac_swap4_byte0_l, 
  dac_swap4_byte3_l, 
  dac_swap4_byte4_l, 
  dac_swap4_byte7_l, 
  dac_swap3_byte0_r, 
  dac_swap3_byte3_r, 
  dac_swap3_byte4_r, 
  dac_swap3_byte7_r, 
  dac_swap2_byte1_r, 
  dac_swap2_byte2_r, 
  dac_swap2_byte5_r, 
  dac_swap2_byte6_r, 
  dac_swap1_byte0_r, 
  dac_swap1_byte1_r, 
  dac_swap1_byte2_r, 
  dac_swap1_byte3_r, 
  dac_swap1_byte4_r, 
  dac_swap1_byte5_r, 
  dac_swap1_byte6_r, 
  dac_swap1_byte7_r, 
  dac_swap0_byte0_r, 
  dac_swap0_byte1_r, 
  dac_swap0_byte2_r, 
  dac_swap0_byte3_r, 
  dac_swap0_byte4_r, 
  dac_swap0_byte5_r, 
  dac_swap0_byte6_r, 
  dac_swap0_byte7_r, 
  dac_byte_one_extend, 
  dac_byte_sel_data, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  lbist_run, 
  mbi_run, 
  bist_wdata_1, 
  dac_bist_cmp_data, 
  lsu_lsu_pmen_, 
  dmo_coresel, 
  dmo_dcmuxctl);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk_en;
wire mbi_run_local;
wire l1clk_pm1;
wire dmo_coresel_qual;
wire dmo_dcmuxctl_qual;
wire dff_dac_b_scanin;
wire dff_dac_b_scanout;
wire ld_inst_vld_b;
wire bendian_m;
wire dff_endian_b_scanin;
wire dff_endian_b_scanout;
wire bendian_b;
wire lendian_b;
wire [7:0] offset_m;
wire [7:0] offset_bist_data_in;
wire dff_baddr_b_scanin;
wire dff_baddr_b_scanout;
wire [7:0] offset_bist_data_out;
wire offset_b4_data_out;
wire offset_b0_data_out;
wire [7:0] offset;
wire [1:0] ld_sz_m;
wire byte_sz_m;
wire hw_sz_m;
wire word_sz_m;
wire dw_sz_m;
wire dff_ld_sz_b_scanin;
wire dff_ld_sz_b_scanout;
wire byte_sz;
wire hw_sz;
wire word_sz;
wire dw_sz;
wire dff_sext_b_scanin;
wire dff_sext_b_scanout;
wire signed_b;
wire dff_misc_msb_b_scanin;
wire dff_misc_msb_b_scanout;
wire [7:0] misc_msb_b;
wire sign_bit_w0;
wire sel_msb0;
wire sel_msb1;
wire sel_msb2;
wire sel_msb3;
wire sel_msb4;
wire sel_msb5;
wire sel_msb6;
wire sel_msb7;
wire sign_bit_w1;
wire sign_bit_w2;
wire sign_bit_w3;
wire sign_bit_xx;
wire sign_bit;
wire bendian;
wire lendian;
wire sign_ext;
wire swap7_byte0;
wire swap7_byte3;
wire swap7_byte4;
wire swap7_byte7;
wire swap6_byte1;
wire swap6_byte2;
wire swap6_byte5;
wire swap6_byte6;
wire swap5_byte1;
wire swap5_byte2;
wire swap5_byte5;
wire swap5_byte6;
wire swap4_byte0;
wire swap4_byte3;
wire swap4_byte4;
wire swap4_byte7;
wire swap3_byte0;
wire swap3_byte3;
wire swap3_byte4;
wire swap3_byte7;
wire swap2_byte1;
wire swap2_byte2;
wire swap2_byte5;
wire swap2_byte6;
wire swap1_byte0;
wire swap1_byte1;
wire swap1_byte2;
wire swap1_byte3;
wire swap1_byte4;
wire swap1_byte5;
wire swap1_byte6;
wire swap1_byte7;
wire swap0_byte0;
wire swap0_byte1;
wire swap0_byte2;
wire swap0_byte3;
wire swap0_byte4;
wire swap0_byte5;
wire swap0_byte6;
wire swap0_byte7;
wire spares_scanin;
wire spares_scanout;


input		dcc_ld_inst_vld_m;
input		dcc_l2fill_vld_m;
input		dcc_lendian_pre_m;
input		dcc_bendian_byp_m;
input	[2:0]	dcc_baddr_m;
input	[1:0]	dcc_ld_sz_m;
input		dcc_signed_m;

input		lmc_asi_bypass_m;
input		lmc_byp_vld_m;

input	[3:0]	tlb_cache_way_hit_b;

input	[7:0]	lmd_misc_msb_m;
input	[7:0]	dca_msb_w0_b;
input	[7:0]	dca_msb_w1_b;
input	[7:0]	dca_msb_w2_b;
input	[7:0]	dca_msb_w3_b;

output		dac_swap7_byte0_l;
output		dac_swap7_byte3_l;
output		dac_swap7_byte4_l;
output		dac_swap7_byte7_l;
output		dac_swap6_byte1_l;
output		dac_swap6_byte2_l;
output		dac_swap6_byte5_l;
output		dac_swap6_byte6_l;
output		dac_swap5_byte1_l;
output		dac_swap5_byte2_l;
output		dac_swap5_byte5_l;
output		dac_swap5_byte6_l;
output		dac_swap4_byte0_l;
output		dac_swap4_byte3_l;
output		dac_swap4_byte4_l;
output		dac_swap4_byte7_l;
output		dac_swap3_byte0_r;
output		dac_swap3_byte3_r;
output		dac_swap3_byte4_r;
output		dac_swap3_byte7_r;
output		dac_swap2_byte1_r;
output		dac_swap2_byte2_r;
output		dac_swap2_byte5_r;
output		dac_swap2_byte6_r;
output		dac_swap1_byte0_r;
output		dac_swap1_byte1_r;
output		dac_swap1_byte2_r;
output		dac_swap1_byte3_r;
output		dac_swap1_byte4_r;
output		dac_swap1_byte5_r;
output		dac_swap1_byte6_r;
output		dac_swap1_byte7_r;
output		dac_swap0_byte0_r;
output		dac_swap0_byte1_r;
output		dac_swap0_byte2_r;
output		dac_swap0_byte3_r;
output		dac_swap0_byte4_r;
output		dac_swap0_byte5_r;
output		dac_swap0_byte6_r;
output		dac_swap0_byte7_r;

output	[7:1]	dac_byte_one_extend;
output	[7:1]	dac_byte_sel_data;

input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input		lbist_run;
input		mbi_run;
input	[7:0]	bist_wdata_1;
output	[7:0]	dac_bist_cmp_data;

input		lsu_lsu_pmen_;

input		dmo_coresel;		// THIS IS ACTIVE LOW!!!!!
input		dmo_dcmuxctl;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

//////////////////////////////
// Clock header
//////////////////////////////

assign l1clk_en = lsu_lsu_pmen_ | dcc_ld_inst_vld_m | dcc_l2fill_vld_m | lmc_byp_vld_m |
                  mbi_run | mbi_run_local | lbist_run | ~dmo_coresel;

lsu_dac_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk                          ),
        .l1en   (l1clk_en                       ),
        .l1clk  (l1clk_pm1                      ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


// Qual core inputs with lbist run to prevent X propagation
assign dmo_coresel_qual = ~dmo_coresel & mbi_run_local & ~lbist_run;
assign dmo_dcmuxctl_qual = dmo_dcmuxctl & ~lbist_run;

// Data alignment and sign extension is part of the critical path with
// load data returning to the register files.  When possible, all inputs
// to this block should come from the M stage so that work can begin
// at the start of B.

lsu_dac_ctl_msff_ctl_macro__width_2 dff_dac_b  (
        .scan_in(dff_dac_b_scanin),
        .scan_out(dff_dac_b_scanout),
        .l1clk  (l1clk_pm1),
	.din	({dcc_ld_inst_vld_m, mbi_run}),
	.dout	({ld_inst_vld_b,     mbi_run_local}),
  .siclk(siclk),
  .soclk(soclk)
);

/////////////////////////////////////////////////////////////
// NOTE: DMO operation requires data alignment such that
// bits 63:32 are either 63:32 (no swapping) or 31:0 (bendian
// word at offset 4.
/////////////////////////////////////////////////////////////

// Endianess
// Endianess is controlled by the following rules
// 1. Internal ASI's are all big endian.
// 2. Accesses with implicit ASI's are controlled by (PSTATE.CLE ^ TTE.IE)
// 3. Accesses with explicit ASI's are controlled by (ASI value ^ TTE.IE)
// Most of the work is done ahead of time in dcc.
// Accesses with TTE.IE=1 always miss the D$, so it doesn't factor in the hit path

assign bendian_m = (dcc_ld_inst_vld_m & ~dcc_lendian_pre_m) | 	// ld hit
                   dcc_bendian_byp_m |				// fill or bypass
                   dmo_coresel_qual;				// DMO

lsu_dac_ctl_msff_ctl_macro__width_2 dff_endian_b  (
        .scan_in(dff_endian_b_scanin),
        .scan_out(dff_endian_b_scanout),
        .l1clk  (l1clk_pm1),
	.din	({(bendian_m | dmo_coresel_qual),~(bendian_m | dmo_coresel_qual)}),
	.dout	({bendian_b,                      lendian_b}),
  .siclk(siclk),
  .soclk(soclk)
);


// Byte offset

assign offset_m[0] = ~dcc_baddr_m[2] & ~dcc_baddr_m[1] & ~dcc_baddr_m[0];
assign offset_m[1] = ~dcc_baddr_m[2] & ~dcc_baddr_m[1] &  dcc_baddr_m[0];
assign offset_m[2] = ~dcc_baddr_m[2] &  dcc_baddr_m[1] & ~dcc_baddr_m[0];
assign offset_m[3] = ~dcc_baddr_m[2] &  dcc_baddr_m[1] &  dcc_baddr_m[0];
assign offset_m[4] =  dcc_baddr_m[2] & ~dcc_baddr_m[1] & ~dcc_baddr_m[0];
assign offset_m[5] =  dcc_baddr_m[2] & ~dcc_baddr_m[1] &  dcc_baddr_m[0];
assign offset_m[6] =  dcc_baddr_m[2] &  dcc_baddr_m[1] & ~dcc_baddr_m[0];
assign offset_m[7] =  dcc_baddr_m[2] &  dcc_baddr_m[1] &  dcc_baddr_m[0];

// Reuse this mux for bist data when in BIST mode
assign offset_bist_data_in[7:0] = mbi_run_local ? bist_wdata_1[7:0] : offset_m[7:0];

// offset[4,0] needs to factor the dmo_dcmuxctl so I can't share the flop between bist & functional

lsu_dac_ctl_msff_ctl_macro__width_10 dff_baddr_b  (
        .scan_in(dff_baddr_b_scanin),
        .scan_out(dff_baddr_b_scanout),
        .l1clk  (l1clk_pm1),
	.din	({offset_bist_data_in[7:0],(offset_m[4] | (dmo_coresel_qual & ~dmo_dcmuxctl_qual)),
                  (offset_m[0] & ~(dmo_coresel_qual & ~dmo_dcmuxctl_qual))}),
	.dout	({offset_bist_data_out[7:0],offset_b4_data_out,offset_b0_data_out}),
  .siclk(siclk),
  .soclk(soclk)
);

assign offset[7:0] = {offset_bist_data_out[7:5],offset_b4_data_out,offset_bist_data_out[3:1],offset_b0_data_out};
assign dac_bist_cmp_data[7:0] = offset_bist_data_out[7:0];

// Data Size
// Size for internal ASI accesses is always 64 bits (sz==11)
assign ld_sz_m[1:0] = dcc_ld_sz_m[1:0] | {2{lmc_asi_bypass_m}};

assign byte_sz_m = ~ld_sz_m[1] & ~ld_sz_m[0] & ~dmo_coresel_qual;
assign hw_sz_m   = ~ld_sz_m[1] &  ld_sz_m[0] & ~dmo_coresel_qual;
assign word_sz_m =  (ld_sz_m[1] & ~ld_sz_m[0] & ~dmo_coresel_qual) | (dmo_coresel_qual & ~dmo_dcmuxctl_qual);
assign dw_sz_m   =  (ld_sz_m[1] &  ld_sz_m[0] & ~dmo_coresel_qual) | (dmo_coresel_qual & dmo_dcmuxctl_qual);

lsu_dac_ctl_msff_ctl_macro__width_4 dff_ld_sz_b  (
        .scan_in(dff_ld_sz_b_scanin),
        .scan_out(dff_ld_sz_b_scanout),
        .l1clk  (l1clk_pm1),
	.din	({byte_sz_m,hw_sz_m,word_sz_m,dw_sz_m}),
	.dout	({byte_sz  ,hw_sz  ,word_sz  ,dw_sz  }),
  .siclk(siclk),
  .soclk(soclk)
);


// Sign extend
lsu_dac_ctl_msff_ctl_macro__width_1 dff_sext_b  (
        .scan_in(dff_sext_b_scanin),
        .scan_out(dff_sext_b_scanout),
        .l1clk  (l1clk_pm1),
	.din	(dcc_signed_m & ~mbi_run_local),
	.dout	(signed_b),
  .siclk(siclk),
  .soclk(soclk)
);

// Sign bit derivation
// Figure the correct sign bit for each way and the bypass path
// separately.  Then, once the hit way is known, mux the result.

lsu_dac_ctl_msff_ctl_macro__width_8 dff_misc_msb_b  (
        .scan_in(dff_misc_msb_b_scanin),
        .scan_out(dff_misc_msb_b_scanout),
        .l1clk  (l1clk_pm1),
	.din	(lmd_misc_msb_m[7:0]),
	.dout	(misc_msb_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign sign_bit_w0 = sel_msb0 & dca_msb_w0_b[0] |
                     sel_msb1 & dca_msb_w0_b[1] |
                     sel_msb2 & dca_msb_w0_b[2] |
                     sel_msb3 & dca_msb_w0_b[3] |
                     sel_msb4 & dca_msb_w0_b[4] |
                     sel_msb5 & dca_msb_w0_b[5] |
                     sel_msb6 & dca_msb_w0_b[6] |
                     sel_msb7 & dca_msb_w0_b[7] ;

assign sign_bit_w1 = sel_msb0 & dca_msb_w1_b[0] |
                     sel_msb1 & dca_msb_w1_b[1] |
                     sel_msb2 & dca_msb_w1_b[2] |
                     sel_msb3 & dca_msb_w1_b[3] |
                     sel_msb4 & dca_msb_w1_b[4] |
                     sel_msb5 & dca_msb_w1_b[5] |
                     sel_msb6 & dca_msb_w1_b[6] |
                     sel_msb7 & dca_msb_w1_b[7] ;

assign sign_bit_w2 = sel_msb0 & dca_msb_w2_b[0] |
                     sel_msb1 & dca_msb_w2_b[1] |
                     sel_msb2 & dca_msb_w2_b[2] |
                     sel_msb3 & dca_msb_w2_b[3] |
                     sel_msb4 & dca_msb_w2_b[4] |
                     sel_msb5 & dca_msb_w2_b[5] |
                     sel_msb6 & dca_msb_w2_b[6] |
                     sel_msb7 & dca_msb_w2_b[7] ;

assign sign_bit_w3 = sel_msb0 & dca_msb_w3_b[0] |
                     sel_msb1 & dca_msb_w3_b[1] |
                     sel_msb2 & dca_msb_w3_b[2] |
                     sel_msb3 & dca_msb_w3_b[3] |
                     sel_msb4 & dca_msb_w3_b[4] |
                     sel_msb5 & dca_msb_w3_b[5] |
                     sel_msb6 & dca_msb_w3_b[6] |
                     sel_msb7 & dca_msb_w3_b[7] ;

assign sign_bit_xx = sel_msb0 & misc_msb_b[0] |
                     sel_msb1 & misc_msb_b[1] |
                     sel_msb2 & misc_msb_b[2] |
                     sel_msb3 & misc_msb_b[3] |
                     sel_msb4 & misc_msb_b[4] |
                     sel_msb5 & misc_msb_b[5] |
                     sel_msb6 & misc_msb_b[6] |
                     sel_msb7 & misc_msb_b[7] ;

assign sign_bit = ld_inst_vld_b & tlb_cache_way_hit_b[0] & sign_bit_w0 |
                  ld_inst_vld_b & tlb_cache_way_hit_b[1] & sign_bit_w1 |
                  ld_inst_vld_b & tlb_cache_way_hit_b[2] & sign_bit_w2 |
                  ld_inst_vld_b & tlb_cache_way_hit_b[3] & sign_bit_w3 |
                  ~ld_inst_vld_b & sign_bit_xx;


assign bendian = bendian_b;
assign lendian = lendian_b;
assign sign_ext = signed_b;

// Byte Alignment
// dcc_swapX_byteY indicates that the aligned data will have byteY as
// returned from the dcache muxed into the byteX position.  This data
// may be overridden by sign extesion in the next step.
//
// See the espresso input file align_byte.pla for the truth table.
// espresso -Dso -o eqntott align_byte.pla

assign swap7_byte0 = (lendian&word_sz&offset[4]) | (lendian&dw_sz);

assign swap7_byte3 = (bendian&word_sz&offset[4]);			// DMOl

assign swap7_byte4 = (lendian&word_sz&offset[0]);

assign swap7_byte7 = (bendian&word_sz&offset[0]) | (bendian&dw_sz);	// DMOh

assign swap6_byte1 = (lendian&word_sz&offset[4]) | (lendian&dw_sz);

assign swap6_byte2 = (bendian&word_sz&offset[4]);			// DMOl

assign swap6_byte5 = (lendian&word_sz&offset[0]);

assign swap6_byte6 = (bendian&word_sz&offset[0]) | (bendian&dw_sz);	// DMOh

assign swap5_byte1 = (bendian&word_sz&offset[4]);			// DMOl

assign swap5_byte2 = (lendian&word_sz&offset[4]) | (lendian&dw_sz);

assign swap5_byte5 = (bendian&word_sz&offset[0]) | (bendian&dw_sz);	// DMOh

assign swap5_byte6 = (lendian&word_sz&offset[0]);

assign swap4_byte0 = (bendian&word_sz&offset[4]);			// DMOl

assign swap4_byte3 = (lendian&word_sz&offset[4]) | (lendian&dw_sz);

assign swap4_byte4 = (bendian&word_sz&offset[0]) | (bendian&dw_sz);	// DMOh

assign swap4_byte7 = (lendian&word_sz&offset[0]);

assign swap3_byte0 = (lendian&word_sz&offset[4]);

assign swap3_byte3 = (bendian&word_sz&offset[4]) | (bendian&dw_sz);

assign swap3_byte4 = (lendian&word_sz&offset[0]) | (lendian&dw_sz);

assign swap3_byte7 = (bendian&word_sz&offset[0]);

assign swap2_byte1 = (lendian&word_sz&offset[4]);

assign swap2_byte2 = (bendian&word_sz&offset[4]) | (bendian&dw_sz);

assign swap2_byte5 = (lendian&word_sz&offset[0]) | (lendian&dw_sz);

assign swap2_byte6 = (bendian&word_sz&offset[0]);

assign swap1_byte0 = (lendian&hw_sz&offset[6]);

assign swap1_byte1 = (bendian&hw_sz&offset[6]) | (bendian&word_sz&offset[4]) | (
    bendian&dw_sz);

assign swap1_byte2 = (lendian&word_sz&offset[4]) | (lendian&hw_sz&offset[4]);

assign swap1_byte3 = (bendian&hw_sz&offset[4]);

assign swap1_byte4 = (lendian&hw_sz&offset[2]);

assign swap1_byte5 = (bendian&hw_sz&offset[2]) | (bendian&word_sz&offset[0]);

assign swap1_byte6 = (lendian&word_sz&offset[0]) | (lendian&hw_sz&offset[0]) | (
    lendian&dw_sz);

assign swap1_byte7 = (bendian&hw_sz&offset[0]);

assign swap0_byte0 = (bendian&hw_sz&offset[6]) | (bendian&word_sz&offset[4]) | (
    byte_sz&offset[7]) | (bendian&dw_sz);

assign swap0_byte1 = (lendian&hw_sz&offset[6]) | (byte_sz&offset[6]);

assign swap0_byte2 = (bendian&hw_sz&offset[4]) | (byte_sz&offset[5]);

assign swap0_byte3 = (lendian&word_sz&offset[4]) | (lendian&hw_sz&offset[4]) | (
    byte_sz&offset[4]);

assign swap0_byte4 = (bendian&hw_sz&offset[2]) | (bendian&word_sz&offset[0]) | (
    byte_sz&offset[3]);

assign swap0_byte5 = (lendian&hw_sz&offset[2]) | (byte_sz&offset[2]);

assign swap0_byte6 = (bendian&hw_sz&offset[0]) | (byte_sz&offset[1]);

assign swap0_byte7 = (lendian&word_sz&offset[0]) | (lendian&hw_sz&offset[0]) | (
    byte_sz&offset[0]) | (lendian&dw_sz);

// Left and right side outputs
assign dac_swap7_byte0_l = swap7_byte0;
assign dac_swap7_byte3_l = swap7_byte3;
assign dac_swap7_byte4_l = swap7_byte4;
assign dac_swap7_byte7_l = swap7_byte7;
assign dac_swap6_byte1_l = swap6_byte1;
assign dac_swap6_byte2_l = swap6_byte2;
assign dac_swap6_byte5_l = swap6_byte5;
assign dac_swap6_byte6_l = swap6_byte6;
assign dac_swap5_byte1_l = swap5_byte1;
assign dac_swap5_byte2_l = swap5_byte2;
assign dac_swap5_byte5_l = swap5_byte5;
assign dac_swap5_byte6_l = swap5_byte6;
assign dac_swap4_byte0_l = swap4_byte0;
assign dac_swap4_byte3_l = swap4_byte3;
assign dac_swap4_byte4_l = swap4_byte4;
assign dac_swap4_byte7_l = swap4_byte7;
assign dac_swap3_byte0_r = swap3_byte0;
assign dac_swap3_byte3_r = swap3_byte3;
assign dac_swap3_byte4_r = swap3_byte4;
assign dac_swap3_byte7_r = swap3_byte7;
assign dac_swap2_byte1_r = swap2_byte1;
assign dac_swap2_byte2_r = swap2_byte2;
assign dac_swap2_byte5_r = swap2_byte5;
assign dac_swap2_byte6_r = swap2_byte6;
assign dac_swap1_byte0_r = swap1_byte0;
assign dac_swap1_byte1_r = swap1_byte1;
assign dac_swap1_byte2_r = swap1_byte2;
assign dac_swap1_byte3_r = swap1_byte3;
assign dac_swap1_byte4_r = swap1_byte4;
assign dac_swap1_byte5_r = swap1_byte5;
assign dac_swap1_byte6_r = swap1_byte6;
assign dac_swap1_byte7_r = swap1_byte7;
assign dac_swap0_byte0_r = swap0_byte0;
assign dac_swap0_byte1_r = swap0_byte1;
assign dac_swap0_byte2_r = swap0_byte2;
assign dac_swap0_byte3_r = swap0_byte3;
assign dac_swap0_byte4_r = swap0_byte4;
assign dac_swap0_byte5_r = swap0_byte5;
assign dac_swap0_byte6_r = swap0_byte6;
assign dac_swap0_byte7_r = swap0_byte7;

// Sign extension
// dac_byte_one_extend indicates a byte is to be filled with ones.
// dac_byte_sel_data indicates that the aligned data is to be passed.
// An aomux is used for this step, so the absence of one_extend or sel_data
// means that the byte will be zero filled.
// Byte 0 is never zero/one filled, so no control exists for it.
//
// See the espresso input file sext_byte.pla for the truth table.
// espresso -Dso -o eqntott sext_byte.pla

assign dac_byte_one_extend[7] = (sign_ext&sign_bit&!dw_sz);

assign dac_byte_sel_data[7] = dw_sz | dmo_coresel_qual;

assign dac_byte_one_extend[6] = (sign_ext&sign_bit&!dw_sz);

assign dac_byte_sel_data[6] = dw_sz | dmo_coresel_qual;

assign dac_byte_one_extend[5] = (sign_ext&sign_bit&!dw_sz);

assign dac_byte_sel_data[5] = dw_sz | dmo_coresel_qual;

assign dac_byte_one_extend[4] = (sign_ext&sign_bit&!dw_sz);

assign dac_byte_sel_data[4] = dw_sz | dmo_coresel_qual;

assign dac_byte_one_extend[3] = (sign_ext&sign_bit&!word_sz&!dw_sz);

assign dac_byte_sel_data[3] = (!byte_sz&!hw_sz);

assign dac_byte_one_extend[2] = (sign_ext&sign_bit&!word_sz&!dw_sz);

assign dac_byte_sel_data[2] = (!byte_sz&!hw_sz);

assign dac_byte_one_extend[1] = (sign_ext&sign_bit&byte_sz);

assign dac_byte_sel_data[1] = (!byte_sz);

// The sign bit is determined by first figuring out which byte will be
// the most significant based on access size, byte offset address, and
// endianess.  The msb of that byte is the sign bit.

assign sel_msb0 = (lendian & word_sz & offset[4]) | 				// LE word @4
                  (lendian & hw_sz & offset[6]) |				// LE hw @6
                  (offset[7]);							// byte @7

assign sel_msb1 = (bendian & offset[6]) |					// BE hw @6
                  (byte_sz & offset[6]);					// byte @6

assign sel_msb2 = (lendian & hw_sz & offset[4]) |				// LE hw @4
                  (offset[5]);							// byte @5

assign sel_msb3 = (bendian & offset[4]) |					// BE hw or word @4
                  (byte_sz & offset[4]);					// byte @4

assign sel_msb4 = (lendian & word_sz & offset[0]) |				// LE word @0
                  (lendian & hw_sz & offset[2]) |				// LE hw @2
                  (offset[3]);							// byte @3

assign sel_msb5 = (bendian & offset[2]) |					// BE hw@2
                  (byte_sz & offset[2]);					// byte @2

assign sel_msb6 = (lendian & hw_sz & offset[0]) |				// LE hw @0
                  (offset[1]);							// byte @1

assign sel_msb7 = (bendian & offset[0]) |					// BE hw or word @0
                  (byte_sz & offset[0]);					// byte @0


lsu_dac_ctl_spare_ctl_macro__num_1 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);

supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_dac_b_scanin          = scan_in                  ;
assign dff_endian_b_scanin       = dff_dac_b_scanout        ;
assign dff_baddr_b_scanin        = dff_endian_b_scanout     ;
assign dff_ld_sz_b_scanin        = dff_baddr_b_scanout      ;
assign dff_sext_b_scanin         = dff_ld_sz_b_scanout      ;
assign dff_misc_msb_b_scanin     = dff_sext_b_scanout       ;
assign spares_scanin             = dff_misc_msb_b_scanout   ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_dac_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dac_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dac_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dac_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dac_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dac_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_dac_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_dcc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_dcc_ctl (
  dec_lsu_tg_d, 
  dec_ld_inst_d, 
  dec_ld_inst_e, 
  dec_st_inst_e, 
  dec_fpldst_inst_e, 
  dec_fsr_ldst_e, 
  dec_ldst_dbl_e, 
  dec_pref_inst_e, 
  dec_flush_inst_e, 
  dec_memstbar_inst_e, 
  dec_sr_inst_e, 
  dec_pr_inst_e, 
  dec_hpr_inst_e, 
  dec_casa_inst_e, 
  dec_ldstub_inst_e, 
  dec_swap_inst_e, 
  dec_altspace_d, 
  dec_sign_ext_e, 
  dec_ldst_sz_e, 
  dec_lsu_rd_e, 
  dec_sraddr_e, 
  dec_imm_asi_vld_d, 
  dec_imm_asi_d, 
  dec_flush_lm, 
  dec_flush_lb, 
  dec_lsu_tid0_d, 
  dec_lsu_tid1_d, 
  tlu_pstate_cle, 
  tlu_asi_0_tid, 
  tlu_asi_1_tid, 
  tlu_asi_0_valid, 
  tlu_asi_1_valid, 
  tlu_flush_lsu_b, 
  tlu_lsu_hpstate_hpriv, 
  tlu_lsu_pstate_priv, 
  tlu_tl_gt_0, 
  tlu_lsu_clear_ctl_reg_, 
  tlu_cerer_dttp, 
  tlu_cerer_dttm, 
  tlu_cerer_dtdp, 
  tlu_cerer_dcvp, 
  tlu_cerer_dctp, 
  tlu_cerer_dctm, 
  tlu_cerer_dcdp, 
  tlc_use_primary_context_c0, 
  tlc_use_secondary_context_c0, 
  tld_tid, 
  tlc_wr_or_demap, 
  tld_va_m_eq_zero, 
  exu_lsu_va_error_m, 
  exu_ecc_m, 
  exu_lsu_rs2_e, 
  fgu_fst_ecc_error_fx2, 
  lmd_sz_m, 
  lmd_fpld_m, 
  lmd_sxt_fsr_m, 
  lmd_rd_m, 
  lmd_fpodd32b_m, 
  lmd_fp32b_m, 
  lmd_bendian_m, 
  lmd_fill_addr_e, 
  lmd_ld_addr_m, 
  lmd_fill_way_e, 
  lmd_wrtag_parity_e, 
  lmc_cpq_tid_m, 
  lmc_thrd_byp_sel_e, 
  lmc_byp_tid_m, 
  lmc_byp_vld_m, 
  lmc_asi_bypass_m, 
  lmc_pref_issued, 
  lmc_bld_annul, 
  lmc_bld_last_e, 
  lmc_bld_miss_e, 
  lmc_full_raw_w, 
  lmc_ld_stall, 
  lmc_l2_err_noup, 
  lmc_l2_uerr, 
  tlb_tte_ie_b, 
  tlb_tte_cp_b, 
  tlb_tte_wbit_b, 
  tlb_tte_ebit_b, 
  tlb_tte_pbit_b, 
  tlb_tte_nfo_b, 
  tlb_cache_way_hit_b, 
  tlb_cache_hit_b, 
  tlb_pgnum_b39, 
  tlb_cam_hit, 
  tlb_cam_mhit, 
  tlb_pgsize, 
  tlb_context0_hit, 
  tlb_tag_parity, 
  tlb_tte_data_parity, 
  dcs_asi_d, 
  dcs_wpt_mask_m, 
  dcs_wpt_enable_m, 
  dcs_wpt_mode_m, 
  dcs_dc_enable, 
  dcs_dmmu_enable_d, 
  lsu_va_m, 
  lsu_va_b, 
  cic_l2fill_vld_e, 
  cic_cpq_ld_sel, 
  cic_invalidate_e, 
  cic_xinval_e, 
  cic_st_update_e, 
  cic_rtn_cmplt, 
  cic_oddrd_e, 
  cic_inv_wen_e, 
  cic_cpq_stall, 
  cid_tid, 
  cid_xway, 
  cid_st_addr, 
  cid_st_way, 
  cid_st_bmask, 
  cid_inv_index, 
  cid_ncache, 
  cid_atomic, 
  cid_l2miss, 
  stb_cam_hit, 
  sbc_bst_in_prog_m, 
  sbc_tid_m, 
  lsu_block_store_alloc, 
  lsu_block_store_kill, 
  sbd_st_data_b, 
  tgd_w0_parity_b, 
  tgd_w1_parity_b, 
  tgd_w2_parity_b, 
  tgd_w3_parity_b, 
  tgd_va_wp_47_16, 
  tgd_va_wp_15_3, 
  tgd_pa_wp_39_16, 
  tgd_pa_wp_15_3, 
  tgd_prty_256m_b, 
  tgd_prty_4m_b, 
  tgd_prty_64k_b, 
  tgd_prty_8k_b, 
  tgd_prty_ctxt0_b, 
  tgd_prty_ctxt1_b, 
  tgc_cache_way_vld_m, 
  tgc_verr_b, 
  dca_perr_w0_b, 
  dca_perr_w1_b, 
  dca_perr_w2_b, 
  dca_perr_w3_b, 
  dca_rparity_b, 
  lru_rdata_m, 
  ifu_lsu_if_vld, 
  ifu_lsu_if_tid, 
  ifu_lsu_if_addr, 
  arc_pid_ctl_2f, 
  dcd_dca_data_compare, 
  lbist_run, 
  mbi_addr, 
  mbi_wdata, 
  mbi_run, 
  mbi_dca_read_en, 
  mbi_dca_write_en, 
  mbi_cmpsel, 
  mbi_dta_read_en, 
  mbi_dta_write_en, 
  mbi_dva_read_en, 
  mbi_dva_write_en, 
  mbi_lru_read_en, 
  mbi_lru_write_en, 
  mbi_dtb_read_en, 
  mbi_dtb_cam_en_pre, 
  mbi_scm_cam_en_pre, 
  dmo_dcmuxctl, 
  bist_cmp_data, 
  bist_cmpsel_1, 
  bist_addr_1, 
  bist_srm_rd_1, 
  bist_scm_rd_1, 
  lsu_trap_flush, 
  dcc_exception_flush_b, 
  dcc_asi_load_m, 
  dcc_asi_load_b, 
  dcc_asi_store_b, 
  dcc_asi_iomap_m, 
  dcc_asi_iomap_b, 
  dcc_asi_rngf_b, 
  dcc_asi_indet_b, 
  dcc_binit_st_b, 
  dcc_dca_rvld_e, 
  dcc_dca_wvld_e, 
  dcc_dca_clk_en_e, 
  dcc_dca_wclk_en_e, 
  dcc_dca_rclk_en_m, 
  dcc_dca_bypass_e_, 
  dcc_dca_fill_way_e, 
  dcc_dca_fill_addr_e, 
  dcc_dca_byte_wr_en_e, 
  dcc_parity_invert, 
  dcc_dta_parity, 
  dcc_alt_addr_sel_e, 
  dcc_alt_way_sel_m, 
  dcc_alt_rsel_way_m, 
  dcc_dta_fill_addr_e, 
  dcc_dta_fill_way_e, 
  dcc_dta_wvld_e, 
  dcc_dta_rvld_e, 
  dcc_dta_index1_sel_e, 
  dcc_dta_clken, 
  dcc_dva_wvld_e, 
  dcc_dva_rvld_e, 
  dcc_dva_din_e, 
  dcc_dva_din2_e, 
  dcc_dva_wr_addr_e, 
  dcc_dva_bit_wen_e, 
  dcc_cache_diag_wr_m, 
  dcc_cache_diag_wr_b, 
  dcc_lru_rvld_e, 
  dcc_lru_wvld_w, 
  dcc_lru_wdata_w, 
  dcc_lru_wen_w, 
  dcc_lru_wr_addr_w, 
  dcc_ldst_bmask, 
  dcc_bmask_parity_b, 
  dcc_ld_miss_b, 
  dcc_early_ld_b, 
  dcc_stb_quad_ld_cam, 
  dcc_l2fill_vld_m, 
  dcc_ctxt_tid0_d, 
  dcc_ctxt_tid1_d, 
  dcc_ctxt_tg_d, 
  dcc_tid_e, 
  dcc_tid_m, 
  dcc_tid_b, 
  dcc_asi_m, 
  dcc_ld_inst_unqual_e, 
  dcc_ld_inst_vld_m, 
  dcc_stb_cam_vld_m, 
  dcc_baddr_m, 
  dcc_signed_m, 
  dcc_pref_inst_m, 
  dcc_std_inst_m, 
  dcc_ldstub_inst_m, 
  dcc_atomic_b, 
  dcc_casa_inst_b, 
  dcc_lendian_pre_m, 
  dcc_bendian_byp_m, 
  dcc_pst_asi_b, 
  dcc_tte_vld_m, 
  dcc_ldst_sz_m, 
  dcc_ld_sz_m, 
  dcc_fp32b_sel_m, 
  dcc_blk_inst_m, 
  dcc_blk_inst_b, 
  dcc_ldbl_b, 
  dcc_ncache_b, 
  dcc_st_rq_type_w, 
  dcc_sync_pipe_w, 
  dcc_priv_b, 
  dcc_hpriv_b, 
  dcc_pctxt_sel_e, 
  dcc_sctxt_sel_e, 
  dcc_ld_miss_ldd, 
  dcc_ld_miss_ctl, 
  dcc_sync_inst_w, 
  dcc_asi_reload_sel, 
  dcc_wr_wtchpt, 
  dcc_wr_lsu_ctl_reg, 
  dcc_wr_pwr_mgmt, 
  dcc_ceter_wr_w, 
  dcc_p0ctxt_rd_m, 
  dcc_p1ctxt_rd_m, 
  dcc_s0ctxt_rd_m, 
  dcc_s1ctxt_rd_m, 
  dcc_pid_rd_m, 
  dcc_wtchpt_sel_m, 
  dcc_demap_asi_m, 
  dcc_wtchpt_rd_b, 
  dcc_rd_lsu_ctl_reg_b, 
  dcc_rd_diag_reg_b, 
  dcc_rd_diag_dca_b, 
  dcc_rd_core_id_b, 
  dcc_rd_intr_id_b, 
  dcc_rd_dt_diag_m, 
  dcc_rd_dt_diag_b, 
  dcc_stb_diag_rd_m, 
  dcc_rd_error_inj_b, 
  dcc_rd_pwr_mgmt_b, 
  dcc_wr_error_inj_m, 
  dcc_wr_error_inj_w, 
  dcc_tlb_data_read_b, 
  dcc_tlb_tag0_read_b, 
  dcc_tlb_tag1_read_b, 
  dcc_tlb_rw_index_e, 
  dcc_rd_rhs_asi_b, 
  dcc_lsu_asi_rd_b, 
  dcc_lsu_asi_sel_w, 
  dcc_stb_diag_sel_w3, 
  dcc_stb_data_rd_w3, 
  dcc_stb_ecc_rd_w3, 
  dcc_stb_ctl_rd_w3, 
  dcc_stb_addr_sel_w3, 
  dcc_stb_ptr_rd_w3, 
  dcc_direct_map, 
  dcc_dcs_memref_e, 
  dcc_tlb_lookup, 
  dcc_tlb_bypass, 
  dcc_tlb_real, 
  dcc_tlb_rd_e, 
  dcc_perror_b, 
  dcc_perr_enc_b, 
  dcc_dmo_parity, 
  lsu_va_w, 
  dcc_sbd_e_clken, 
  dcc_sbd_m_clken, 
  dcc_ldst_m_clken, 
  dcc_asi_rtn_vld, 
  dcc_asi_rtn_excp, 
  dcc_asi_rtn_rd, 
  lsu_exu_ld_vld_w, 
  lsu_exu_ld_b, 
  lsu_exu_tid_m, 
  lsu_exu_rd_m, 
  lsu_fgu_fld_vld_w, 
  lsu_fgu_fld_b, 
  lsu_fgu_fld_32b_b, 
  lsu_fgu_fld_odd32b_b, 
  lsu_fgu_fsr_load_b, 
  lsu_fgu_fld_tid_b, 
  lsu_fgu_fld_addr_b, 
  lsu_fgu_exception_w, 
  lsu_sync, 
  lsu_complete, 
  lsu_cpq_stall, 
  lsu_tlu_twocycle_m, 
  lsu_tlb_bypass_b, 
  lsu_tlb_real_b, 
  lsu_align_b, 
  lsu_lddf_align_b, 
  lsu_stdf_align_b, 
  lsu_dae_invalid_asi_b, 
  lsu_dae_nc_page_b, 
  lsu_dae_nfo_page_b, 
  lsu_dae_priv_viol_b, 
  lsu_dae_so_page, 
  lsu_priv_action_b, 
  lsu_va_watchpoint_b, 
  lsu_pa_watchpoint_b, 
  lsu_illegal_inst_b, 
  lsu_daccess_prot_b, 
  lsu_tlb_miss_b_, 
  lsu_perfmon_trap_b, 
  lsu_perfmon_trap_g, 
  lsu_tlu_dsfsr_ct_b, 
  lsu_sync_inst_b, 
  lsu_dttp_err_b, 
  lsu_dtdp_err_b, 
  lsu_dtmh_err_b, 
  lsu_ifu_direct_map, 
  dcc_mbi_run, 
  lsu_mbi_dca_fail, 
  lsu_mbi_lru_fail, 
  pmu_lsu_dcmiss_trap_m, 
  pmu_lsu_dtmiss_trap_m, 
  pmu_lsu_l2dmiss_trap_m, 
  lsu_pmu_mem_type_b, 
  lsu_dc_pmen, 
  lsu_lsu_pmen, 
  lsu_lsu_pmen_, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire dcc_pm_clken;
wire l1clk_pm1;
wire ifu_indx_clken;
wire l1clk_pm2;
wire l1clk;
wire dff_cerer_scanin;
wire dff_cerer_scanout;
wire cerer_dttp;
wire cerer_dttm;
wire cerer_dtdp;
wire cerer_dcvp;
wire cerer_dctp;
wire cerer_dctm;
wire cerer_dcdp;
wire exu_error_m;
wire [2:0] tid_m;
wire tlb_bypass_m;
wire exu_error_qual_m;
wire ld_inst_vld_m;
wire st_inst_vld_m;
wire flush_inst_m;
wire mb_inst_m;
wire exu_va_oor_m;
wire dff_flush_b_scanin;
wire dff_flush_b_scanout;
wire pipe_flush_b;
wire exu_error_pre_b;
wire exu_va_oor_b;
wire exu_error_b;
wire [2:0] tid_b;
wire twocycle_b;
wire fgu_error_b;
wire st_inst_vld_b;
wire fpldst_inst_vld_b;
wire dcc_any_exception_b;
wire flush_b;
wire flush_all_b;
wire dff_flush_w_scanin;
wire dff_flush_w_scanout;
wire flush_w;
wire dff_asi_d_scanin;
wire dff_asi_d_scanout;
wire [7:0] asi_d;
wire dcc_imm_asi_vld_e;
wire [7:0] dcc_asi_e;
wire altspace_e;
wire dmmu_enable_e;
wire ld_inst_unqual_e;
wire [7:0] asx_e;
wire asi_use_rd_e;
wire asi_use_sr_e;
wire mbi_run_local;
wire bist_cam_en;
wire asi_internal_e;
wire pref_inst_qual_e;
wire dff_dec_inst1_m_scanin;
wire dff_dec_inst1_m_scanout;
wire fpldst_inst_vld_m;
wire pref_inst_m;
wire casa_inst_pre_m;
wire ldstub_inst_pre_m;
wire swap_inst_pre_m;
wire ldst_dbl_m;
wire sr_inst_m;
wire pr_inst_m;
wire hpr_inst_m;
wire fsr_ldst_m;
wire imm_asi_vld_m;
wire casa_inst_m;
wire swap_inst_m;
wire ldstub_inst_m;
wire dff_sync_inst_scanin;
wire dff_sync_inst_scanout;
wire sync_inst_m;
wire sync_inst_pre_b;
wire mbi_scm_cam_en;
wire atomic_m;
wire asi_internal_m;
wire blk_inst_m;
wire [1:0] ldst_sz_mod_m;
wire asi_iomap_m;
wire asi_sync_m;
wire dff_dec_ctl_m_scanin;
wire dff_dec_ctl_m_scanout;
wire [1:0] ldst_sz_m;
wire [4:0] ld_rd_inst_m;
wire sign_ext_m;
wire asi_sz_byte_m;
wire asi_sz_hw_m;
wire asi_legal_m;
wire sxt_fsr_m;
wire [4:0] ld_rd_m;
wire [1:0] asi_type_m;
wire dff_dec_inst_b_scanin;
wire dff_dec_inst_b_scanout;
wire ld_inst_vld_b;
wire pref_inst_b;
wire casa_inst_b;
wire ldst_dbl_b;
wire atomic_b;
wire [1:0] asi_type_b;
wire sync_inst_b;
wire pst_asi_b;
wire tlb_tte_vld_b;
wire dff_dec_ctl_b_scanin;
wire dff_dec_ctl_b_scanout;
wire [1:0] ldst_sz_b;
wire [4:0] ld_rd_b;
wire ldst_sz_b0_b;
wire quad_asi_b;
wire [2:0] tid_d;
wire thread0_d;
wire thread1_d;
wire thread2_d;
wire thread3_d;
wire thread4_d;
wire thread5_d;
wire thread6_d;
wire thread7_d;
wire dff_tid_e_scanin;
wire dff_tid_e_scanout;
wire [2:0] tid_e;
wire thread0_e;
wire thread1_e;
wire thread2_e;
wire thread3_e;
wire thread4_e;
wire thread5_e;
wire thread6_e;
wire thread7_e;
wire dff_tid_m_scanin;
wire dff_tid_m_scanout;
wire dff_tid_b_scanin;
wire dff_tid_b_scanout;
wire thread0_b;
wire thread1_b;
wire thread2_b;
wire thread3_b;
wire thread4_b;
wire thread5_b;
wire thread6_b;
wire thread7_b;
wire dff_tid_w_scanin;
wire dff_tid_w_scanout;
wire [2:0] tid_w;
wire [7:0] thread_w;
wire fpld_32b_m;
wire fpld_odd32b_m;
wire altspace_ldst_e;
wire dff_altspace_m_scanin;
wire dff_altspace_m_scanout;
wire altspace_ldst_m;
wire dff_altspace_b_scanin;
wire dff_altspace_b_scanout;
wire altspace_ldst_b;
wire fpld_inst_m;
wire dff_fpld_b_scanin;
wire dff_fpld_b_scanout;
wire fpld_inst_b;
wire blk_asi_m;
wire blk_asi_b;
wire dff_oddrd_scanin;
wire dff_oddrd_scanout;
wire oddrd_m;
wire dff_rs2_m_scanin;
wire dff_rs2_m_scanout;
wire [7:0] rs2_m;
wire ldst_byte;
wire bad_fp_asi;
wire ldst_hword;
wire ldst_word;
wire ldst_dword;
wire [7:0] ldst_bmask;
wire [7:0] pst_bmask;
wire asi_pst32_m;
wire asi_pst16_m;
wire asi_pst8_m;
wire [7:0] lend_pst_bmask;
wire [7:0] ldst_bmask_mod;
wire asi_store_m;
wire pst_asi_m;
wire lendian_asi_m;
wire st_bmask_parity_m;
wire dff_sba_par_scanin;
wire dff_sba_par_scanout;
wire l1_ld_miss_b;
wire dcache_enable_b;
wire ncache_rq_b;
wire early_ld_m;
wire dcache_enable_m;
wire dff_early_ld_scanin;
wire dff_early_ld_scanout;
wire sync_pipe;
wire asi_dcd_diag_rd_b;
wire asi_sync_b;
wire dff_sync_pipe_scanin;
wire dff_sync_pipe_scanout;
wire [7:0] sync_st_in;
wire st_inst_vld_w;
wire [7:0] sync_st;
wire dff_sync_st_scanin;
wire dff_sync_st_scanout;
wire stb_diag_rd_e;
wire asi_cache_diag_wr_m;
wire dcache_enable_e;
wire dcache_read_e;
wire asi_dca_diag_rd_e;
wire asi_dta_diag_rd_e;
wire dcache_nodiag_read_e;
wire dc_enable_scanin;
wire dc_enable_scanout;
wire dcache_read_m;
wire dcache_nodiag_read_m;
wire dcache_read_b;
wire dcc_dca_rvld_m;
wire ld_fill_e;
wire dca_diag_wr_e;
wire l2fill_vld_m;
wire asi_dca_diag_rd_m;
wire dta_diag_wr_e;
wire diag_write_e;
wire [20:3] va_w;
wire [10:4] xinv_index;
wire [1:0] st_data_w;
wire [15:0] fill_bit_wen_e;
wire [15:0] xinval_bit_wen_e;
wire l2fill_vld_e;
wire dff_l2fill_m_scanin;
wire dff_l2fill_m_scanout;
wire int_fill_or_byp_m;
wire l2_perfmon_wb_cancel_m;
wire fp_fill_or_byp_m;
wire exu_ld_m;
wire fgu_fld_m;
wire dff_l2fill_b_scanin;
wire dff_l2fill_b_scanout;
wire int_fill_or_byp_b;
wire fp_fill_or_byp_b;
wire fld_32b_m;
wire fld_odd32b_m;
wire fld_sxt_fsr_m;
wire [4:0] return_rd_m;
wire [2:0] ld_tid_m;
wire dff_ld_tid_b_scanin;
wire dff_ld_tid_b_scanout;
wire [2:0] ld_tid_b;
wire dff_fp32_b_scanin;
wire dff_fp32_b_scanout;
wire fld_32b_b;
wire fld_odd32b_b;
wire fld_sxt_fsr_b;
wire [4:0] return_rd_b;
wire fsr_load_unqual_b;
wire ld_inst_qual_b;
wire exu_ld_vld_b;
wire fgu_fld_vld_b;
wire dff_ld_vld_w_scanin;
wire dff_ld_vld_w_scanout;
wire exu_ld_vld_w;
wire fgu_fld_vld_w;
wire ld_inst_vld_w;
wire pstate_cle_d;
wire pstate_cle_m;
wire dff_le_bits_scanin;
wire dff_le_bits_scanout;
wire pstate_cle_e;
wire pstate_cle_b;
wire l1hit_lendian_b;
wire asi_internal_b;
wire lendian_asi_b;
wire [2:0] byp_baddr_m;
wire asi_legal_e_unqual;
wire tl_gt_0_d;
wire [7:0] tl_gt_0;
wire dff_tl_gt_0_scanin;
wire dff_tl_gt_0_scanout;
wire tl_gt_0_e;
wire tl_gt_0_m;
wire dff_tlc_scanin;
wire dff_tlc_scanout;
wire tlc_use_primary_context_c1;
wire tlc_use_secondary_context_c1;
wire wr_or_demap;
wire tlc_use_primary_context_c2;
wire tlc_use_secondary_context_c2;
wire tlc_use_secondary_context;
wire tlc_use_primary_context;
wire primary_asi_e;
wire secondary_asi_e;
wire [1:0] context_enc_e;
wire dff_ct_scanin;
wire dff_ct_scanout;
wire [1:0] context_enc_m;
wire [1:0] context_enc_b;
wire hpstate_hpriv_e;
wire real_asi_e;
wire as_if_user_asi_e;
wire as_if_priv_asi_e;
wire dff_asi_m_scanin;
wire dff_asi_m_scanout;
wire blk_asi_e;
wire as_if_user_asi_m;
wire asi_legal_m_unqual;
wire dff_asi_b_scanin;
wire dff_asi_b_scanout;
wire asi_rngf_m;
wire quad_asi_m;
wire atomic_asi_m;
wire asi_indet_m;
wire binit_quad_asi_m;
wire nofault_asi_m;
wire quad_ld_m;
wire asi_rngf_b;
wire atomic_asi_b;
wire asi_store_b;
wire asi_indet_b;
wire binit_quad_asi_b;
wire nofault_asi_b;
wire quad_ldd_b;
wire [7:0] dcc_asi_b;
wire asi_legal_b;
wire bist_dtb_read_en;
wire asi_dca_diag_e;
wire asi_dta_diag_e;
wire dff_int_asi_m_scanin;
wire dff_int_asi_m_scanout;
wire asi_dca_diag_m;
wire asi_dta_diag_m;
wire asi_dta_diag_rd_m;
wire dcc_wtchpt_rd_m;
wire tlb_tag_read_m;
wire tlb_data_read_m;
wire asi_dcd_diag_rd_m;
wire lsu_asi_rd_m;
wire dff_int_asi_b_scanin;
wire dff_int_asi_b_scanout;
wire wr_error_inj_m;
wire lsu_asi_rd_b;
wire asi_dca_diag_rd_b;
wire stb_diag_rd_b;
wire wr_error_inj_b;
wire asi_cache_diag_wr_b;
wire dcc_tlb_tag_read_b;
wire dff_int_asi_w_scanin;
wire dff_int_asi_w_scanout;
wire lsu_asi_sel_b;
wire lsu_asi_sel_w;
wire stb_diag_rd_w;
wire asi_cache_diag_wr_w;
wire asi_dta_not_dca_diag_w;
wire asi_wtchpt_wr_b;
wire asi_ctl_reg_wr_b;
wire asi_diag_reg_wr_b;
wire asi_wr_pwr_mgmt_b;
wire asi_ceter_wr_b;
wire dff_wr_state_w_scanin;
wire dff_wr_state_w_scanout;
wire asi_wtchpt_wr_w;
wire asi_ctl_reg_wr_w;
wire asi_diag_reg_wr_w;
wire asi_wr_pwr_mgmt_w;
wire wr_error_inj_w;
wire asi_ceter_wr_w;
wire dff_tlu_asi_scanin;
wire dff_tlu_asi_scanout;
wire reload_asi_0_valid;
wire reload_asi_1_valid;
wire [1:0] reload_asi_0_tid;
wire [1:0] reload_asi_1_tid;
wire stb_diag_rd_w_qual;
wire stb_ptr_rd_w2;
wire stb_diag_rd_w2;
wire [10:4] va_w2;
wire stb_data_rd_w2;
wire stb_ecc_rd_w2;
wire stb_ctl_rd_w2;
wire stb_addr_rd_w2;
wire dff_stb_w3_scanin;
wire dff_stb_w3_scanout;
wire stb_data_rd_w3;
wire stb_ecc_rd_w3;
wire stb_ctl_rd_w3;
wire stb_ptr_rd_w3;
wire stb_addr_rd_w3;
wire [1:0] diag_reg_in;
wire [1:0] diag_reg;
wire dff_diag_reg_scanin;
wire dff_diag_reg_scanout;
wire [1:0] way_hit_enc;
wire [1:0] ld_way_b;
wire [1:0] way_err_enc;
wire [1:0] rway;
wire [3:0] lru_line_sel;
wire [5:0] lru_rd_data_m;
wire bypass_from_w2;
wire ld_inst_vld_w2;
wire bypass_from_w;
wire bypass_from_b;
wire [5:0] lru_state_in_m;
wire [5:0] new_lru_state_b;
wire [5:0] lru_state_w;
wire [5:0] lru_state_w2;
wire dff_lru_data_b_scanin;
wire dff_lru_data_b_scanout;
wire [5:0] lru_state_in_b;
wire [5:0] lru_state_b;
wire [3:0] lru_way;
wire ldhit_b;
wire [3:0] used_way;
wire dff_new_lru_w_scanin;
wire dff_new_lru_w_scanout;
wire [5:0] new_lru_state_w;
wire [5:0] old_lru_state_w;
wire dff_new_lru_w2_scanin;
wire dff_new_lru_w2_scanout;
wire update_lru_noraw_b;
wire update_lru_raw_b;
wire dff_update_lru_scanin;
wire dff_update_lru_scanout;
wire update_lru_noraw_w;
wire update_lru_raw_w;
wire lru_new_state;
wire [2:0] ld_rq_type;
wire pgnum_b39_qual;
wire [1:0] ld_pkt_way_b;
wire [60:40] mem_ld_miss_ctl;
wire pref_ice_b;
wire [60:40] asi_ld_miss_ctl;
wire dff_sync_inst_w_scanin;
wire dff_sync_inst_w_scanout;
wire sync_inst_w;
wire [1:0] st_rq_type_b;
wire dff_st_type_w_scanin;
wire dff_st_type_w_scanout;
wire pstate_priv_d;
wire hpstate_hpriv_d;
wire dff_priv_state_e_scanin;
wire dff_priv_state_e_scanout;
wire pstate_priv_e;
wire dff_priv_state_m_scanin;
wire dff_priv_state_m_scanout;
wire pstate_priv_m;
wire hpstate_hpriv_m;
wire bst_priv_m;
wire bst_hpriv_m;
wire pstate_priv_m_in;
wire pstate_priv_b;
wire hpstate_hpriv_m_in;
wire hpstate_hpriv_b;
wire dff_priv_state_b_scanin;
wire dff_priv_state_b_scanout;
wire tlb_bypass_b;
wire blk_rd_align_err_m;
wire rd_odd_align_err_m;
wire illegal_spr_m;
wire asr_legal_m;
wire pst_with_imm_m;
wire asi_wo_viol;
wire priv_wrpr_tick_m;
wire wrhpr_ver_m;
wire tl_eq_0_m;
wire illegal_inst_m;
wire hw_aligned;
wire wd_aligned;
wire dw_aligned;
wire qw_aligned;
wire bl_aligned;
wire hw_size;
wire wd_size;
wire dw_size;
wire bl_size;
wire qw_size;
wire mem_addr_not_aligned;
wire lddf_not_aligned;
wire stdf_not_aligned;
wire hpriv_asi;
wire hpriv_asi_excp;
wire priv_action_m;
wire illegal_asi_m;
wire non_atomic_asi_m;
wire atomic_uncache_b;
wire nfo_pg_nonnfo_asi_b;
wire nfo_asi_ebit_b;
wire user_page_access_m;
wire dff_usr_pg_access_b_scanin;
wire dff_usr_pg_access_b_scanout;
wire user_page_access_b;
wire priv_page_viol_b;
wire ldxa_asi_exception;
wire quad_ldda_exception;
wire block_inst_exception;
wire bld_to_io_b;
wire nofault_st_exception;
wire bis_with_fp;
wire asi_ro_viol;
wire asi_read_only_m;
wire asi_write_only_m;
wire bad_asi_va_exception_m;
wire asi_no_va_check_m;
wire legal_asi_va_m;
wire wrpriv_intq_reg_m;
wire dae_invalid_asi_m;
wire dff_excp_b_scanin;
wire dff_excp_b_scanout;
wire tlb_real_m;
wire dae_invalid_asi_b;
wire tlb_real_b;
wire access_exception_b;
wire va_wpt_en_m;
wire pa_wpt_en_m;
wire va_wpt_rd_en_m;
wire va_wpt_wr_en_m;
wire pa_wpt_rd_en_m;
wire pa_wpt_wr_en_m;
wire [7:0] wpt_bmask;
wire mask_match_m;
wire va_wpt_check_m;
wire pa_wpt_check_m;
wire dff_wpt_scanin;
wire dff_wpt_scanout;
wire va_wpt_check_b;
wire pa_wpt_check_b;
wire asi_rtn_vld_2f;
wire asi_rtn_excp_2f;
wire asi_rtn_rd_2f;
wire [2:0] asi_rtn_tid_2f;
wire dff_asi_g_scanin;
wire dff_asi_g_scanout;
wire asi_rtn_vld_3f;
wire asi_rtn_excp_3f;
wire asi_rtn_rd_3f;
wire [2:0] asi_rtn_tid_3f;
wire dff_except_scanin;
wire dff_except_scanout;
wire priv_action_b;
wire nop_pref_func;
wire pref_nop_b;
wire dff_fgu_excp_w_scanin;
wire dff_fgu_excp_w_scanout;
wire [10:5] if_indx_0_in;
wire [10:5] if_indx_0;
wire [10:5] if_indx_1_in;
wire [10:5] if_indx_1;
wire [10:5] if_indx_2_in;
wire [10:5] if_indx_2;
wire [10:5] if_indx_3_in;
wire [10:5] if_indx_3;
wire [10:5] if_indx_4_in;
wire [10:5] if_indx_4;
wire [10:5] if_indx_5_in;
wire [10:5] if_indx_5;
wire [10:5] if_indx_6_in;
wire [10:5] if_indx_6;
wire [10:5] if_indx_7_in;
wire [10:5] if_indx_7;
wire dff_if_indx_0_scanin;
wire dff_if_indx_0_scanout;
wire dff_if_indx_1_scanin;
wire dff_if_indx_1_scanout;
wire dff_if_indx_2_scanin;
wire dff_if_indx_2_scanout;
wire dff_if_indx_3_scanin;
wire dff_if_indx_3_scanout;
wire dff_if_indx_4_scanin;
wire dff_if_indx_4_scanout;
wire dff_if_indx_5_scanin;
wire dff_if_indx_5_scanout;
wire dff_if_indx_6_scanin;
wire dff_if_indx_6_scanout;
wire dff_if_indx_7_scanin;
wire dff_if_indx_7_scanout;
wire dff_way_vld_b_scanin;
wire dff_way_vld_b_scanout;
wire [3:0] cache_way_vld_b;
wire [3:0] dval_perr_b;
wire dval_perror_b;
wire [3:0] dtag_perr_b;
wire dtag_perror_b;
wire mhit_err_b;
wire mhit_error_b;
wire [3:0] data_perr_b;
wire data_perror_b;
wire [2:0] way_err;
wire prty_ctxt;
wire tag_parity;
wire dcmiss_trap_m;
wire dtmiss_trap_m;
wire dcmiss_trap_b;
wire dtmiss_trap_b;
wire l2miss_no_atomic_e;
wire dff_l2miss_scanin;
wire dff_l2miss_scanout;
wire l2miss_no_atomic_m;
wire l2lmiss_trap_e;
wire dff_pmu_trap_scanin;
wire dff_pmu_trap_scanout;
wire load_complete_e;
wire l2lmiss_trap_m;
wire load_complete_m;
wire sbd_m_clken;
wire dff_pwr_mgmt_scanin;
wire dff_pwr_mgmt_scanout;
wire dff_bist_run_scanin;
wire dff_bist_run_scanout;
wire dff_bist_in_scanin;
wire dff_bist_in_scanout;
wire bist_dca_rd_1;
wire bist_lru_rd_1;
wire tlb_cam_en_pre;
wire bist_dca_cmp_en;
wire bist_lru_cmp_en;
wire dca_parity_compare;
wire dca_fail;
wire lru_fail;
wire dff_bist_fail_scanin;
wire dff_bist_fail_scanout;
wire spares_scanin;
wire spares_scanout;


// Inputs from decode unit.
input		dec_lsu_tg_d;		// Thread group of instruction in D
input		dec_ld_inst_d;		// Load instruction in D
input		dec_ld_inst_e;		// Load instruction in E
input		dec_st_inst_e;		// Store instruction in E
input		dec_fpldst_inst_e;	// Float ldst instruction in E
input		dec_fsr_ldst_e;		// LDFSR/STFSR instruction in E
input		dec_ldst_dbl_e;		// LDD or STB instruction in E
input		dec_pref_inst_e;	// Prefetch instruction in E
input		dec_flush_inst_e;	// Flush instruction in E
input		dec_memstbar_inst_e;	// Membar/stbar instruction in E
input		dec_sr_inst_e;		// Rd/rw state register instruction in E
input		dec_pr_inst_e;		// Rd/rw priv. register instruction in E
input		dec_hpr_inst_e;		// Rd/rw hyper-priv. register instruction in E
input		dec_casa_inst_e;	// CASA instruction in E
input		dec_ldstub_inst_e;	// LDSTUB instruction in E
input		dec_swap_inst_e;	// SWAP instruction in E
input		dec_altspace_d;		// Memory access to alternate space
input		dec_sign_ext_e;		// Instruction requiring sign extension of data (op3[3:2]==10)
input	[1:0]	dec_ldst_sz_e;		// Size bits for the instruction in E
input	[4:0]	dec_lsu_rd_e;		// Dest. register for load data
input	[4:0]	dec_sraddr_e;		// Source register for store data
input		dec_imm_asi_vld_d;	// Instruction in D uses immediate ASI 
input	[7:0]	dec_imm_asi_d;
input		dec_flush_lm;
input		dec_flush_lb;
input	[1:0]	dec_lsu_tid0_d;
input	[1:0]	dec_lsu_tid1_d;

input	[7:0]	tlu_pstate_cle;		// PSTATE.CLE bit for the 8 threads
input	[1:0]	tlu_asi_0_tid;		// Thread for TLU reload
input	[1:0]	tlu_asi_1_tid;		// Thread for TLU reload
input		tlu_asi_0_valid;
input		tlu_asi_1_valid;
input		tlu_flush_lsu_b;
input	[7:0]	tlu_lsu_hpstate_hpriv;
input	[7:0]	tlu_lsu_pstate_priv;
input	[7:0]	tlu_tl_gt_0;
input	[7:0]	tlu_lsu_clear_ctl_reg_;
input		tlu_cerer_dttp;
input		tlu_cerer_dttm;
input		tlu_cerer_dtdp;
input		tlu_cerer_dcvp;
input		tlu_cerer_dctp;
input		tlu_cerer_dctm;
input		tlu_cerer_dcdp;

input		tlc_use_primary_context_c0;
input		tlc_use_secondary_context_c0;
input	[2:0]	tld_tid;
input		tlc_wr_or_demap;
input		tld_va_m_eq_zero;	// Zero compare result of VA[47:16]

input	[1:0]	exu_lsu_va_error_m;
input	[1:0]	exu_ecc_m;
input	[7:0]	exu_lsu_rs2_e;

input		fgu_fst_ecc_error_fx2;	// ECC error on FRF read (B)

input	[1:0]	lmd_sz_m;		// Size bits from LMQ
input		lmd_fpld_m;		// Load float
input		lmd_sxt_fsr_m;		// Sign extend / LDFSR for load misses
input	[4:0]	lmd_rd_m;
input		lmd_fpodd32b_m;
input		lmd_fp32b_m;
input		lmd_bendian_m;
input	[10:3]	lmd_fill_addr_e;
input	[2:0]	lmd_ld_addr_m;		// Byte offset address of LMQ entry
input	[1:0]	lmd_fill_way_e;		// Replacement way for fill data write
input		lmd_wrtag_parity_e;

input	[2:0]	lmc_cpq_tid_m;		// Thread ID of fill packet
input	[7:0]	lmc_thrd_byp_sel_e;	// Thread is bypassing data
input	[2:0]	lmc_byp_tid_m;		// Thread is bypassing data
input		lmc_byp_vld_m;		// Thread is bypassing data
input		lmc_asi_bypass_m;	// ASI data is byapssing now
input	[7:0]	lmc_pref_issued;
input		lmc_bld_annul;
input		lmc_bld_last_e;
input		lmc_bld_miss_e;
input		lmc_full_raw_w;
input		lmc_ld_stall;
input		lmc_l2_err_noup;
input		lmc_l2_uerr;

input		tlb_tte_ie_b;		// Invert endianess bit
input		tlb_tte_cp_b;		// Cacheable physical bit
input		tlb_tte_wbit_b;		// Writeable page bit
input		tlb_tte_ebit_b;		// Side effect bit
input		tlb_tte_pbit_b;		// Privileged page bit
input		tlb_tte_nfo_b;		// Non faulting page bit
input	[3:0]	tlb_cache_way_hit_b;	// tag compare result		
input		tlb_cache_hit_b;	// OR of the four way tag compares
input		tlb_pgnum_b39;		// For indetifying IO accesses
input 		tlb_cam_hit;
input		tlb_cam_mhit;
input	[2:0]	tlb_pgsize;
input		tlb_context0_hit;
input		tlb_tag_parity;
input		tlb_tte_data_parity;

input	[7:0]	dcs_asi_d;		// ASI value of instruction in E stage
input	[7:0]	dcs_wpt_mask_m;
input	[1:0]	dcs_wpt_enable_m;
input	[1:0]	dcs_wpt_mode_m;
input	[7:0]	dcs_dc_enable;
input		dcs_dmmu_enable_d;

input	[15:0]	lsu_va_m;		// VA of instruction in M
input	[20:3]	lsu_va_b;		// VA of instruction in B

input		cic_l2fill_vld_e;	// Fill data is coming from the cpx
//input		cic_cpq_ld_rdy;		// Load at cpq head and cpq is not blocked
input		cic_cpq_ld_sel;		// Load at cpq head (blocking unknown)
input		cic_invalidate_e;	// Invalidations are coming from the cpx
input		cic_xinval_e;		// Cross invalidation
input		cic_st_update_e;	// Store data writes to cache
input		cic_rtn_cmplt;		// Load/Atomic complete
input		cic_oddrd_e;		// 2nd pass of a 2 pass load
input	[15:0]	cic_inv_wen_e;		// Invalidation data
input		cic_cpq_stall;

input	[2:0]	cid_tid;		// Thread ID of packet at head of CPQ
input	[1:0]	cid_xway;		// Way for cross invalidation
input	[10:3]	cid_st_addr;		// Index for store update
input	[1:0]	cid_st_way;		// Way for store update
input	[7:0]	cid_st_bmask;		// Byte mask for store update
input	[10:6]  cid_inv_index;		// Cache index for invalidation
input		cid_ncache;		// NC bit of the CPX packet
input		cid_atomic;		// Also indicates 2nd ifill packet
input		cid_l2miss;

input		stb_cam_hit;		// RAW hit in the stb

input		sbc_bst_in_prog_m;
input	[2:0]	sbc_tid_m;

input	[7:0]	lsu_block_store_alloc;
input	[7:0]	lsu_block_store_kill;

input	[1:0]	sbd_st_data_b;		// store data
input		tgd_w0_parity_b;
input		tgd_w1_parity_b;
input		tgd_w2_parity_b;
input		tgd_w3_parity_b;
input		tgd_va_wp_47_16;
input		tgd_va_wp_15_3;
input		tgd_pa_wp_39_16;
input		tgd_pa_wp_15_3;
input		tgd_prty_256m_b;
input		tgd_prty_4m_b;
input		tgd_prty_64k_b;
input		tgd_prty_8k_b;
input		tgd_prty_ctxt0_b;
input		tgd_prty_ctxt1_b;
input	[3:0]	tgc_cache_way_vld_m;
input	[3:0]	tgc_verr_b;

input		dca_perr_w0_b;
input		dca_perr_w1_b;
input		dca_perr_w2_b;
input		dca_perr_w3_b;
input	[7:0]	dca_rparity_b;

input	[23:0]	lru_rdata_m;

input		ifu_lsu_if_vld;		// ifetch request (for cross invalidation)
input	[2:0]	ifu_lsu_if_tid;
input	[10:5]	ifu_lsu_if_addr;

input	[6:0]	arc_pid_ctl_2f;

input	[1:0]	dcd_dca_data_compare;

input		lbist_run;
input	[8:0]	mbi_addr;
input	[7:0]	mbi_wdata;
input		mbi_run;
input		mbi_dca_read_en;
input		mbi_dca_write_en;
input		mbi_cmpsel;
input		mbi_dta_read_en;
input		mbi_dta_write_en;
input		mbi_dva_read_en;
input		mbi_dva_write_en;
input		mbi_lru_read_en;
input		mbi_lru_write_en;
input		mbi_dtb_read_en;
input		mbi_dtb_cam_en_pre;
input		mbi_scm_cam_en_pre;

input		dmo_dcmuxctl;

input	[7:0]	bist_cmp_data;
input	[1:0]	bist_cmpsel_1;
input	[8:5]	bist_addr_1;
input		bist_srm_rd_1;
input		bist_scm_rd_1;

input	[7:0]	lsu_trap_flush;		// must send lsu_complete on a trap_flush

output		dcc_exception_flush_b;
output		dcc_asi_load_m;		// Access is to internal ASI
output		dcc_asi_load_b;		// Access is to internal ASI
output		dcc_asi_store_b;	// Access is to internal ASI
output		dcc_asi_iomap_m;
output		dcc_asi_iomap_b;
output		dcc_asi_rngf_b;		// ASI access targeted to fast ring
output		dcc_asi_indet_b;	// ASI access is indeterminate
output		dcc_binit_st_b;

output		dcc_dca_rvld_e;		// Dcache read enable
output		dcc_dca_wvld_e;		// Dcache write enable
output		dcc_dca_clk_en_e;	// Dcache array clock enable
output		dcc_dca_wclk_en_e;	// Dcache output flop clock enable
output		dcc_dca_rclk_en_m;	// Dcache output flop clock enable
output		dcc_dca_bypass_e_;	// Dcache bypass enable
output	[1:0]	dcc_dca_fill_way_e;	// Dcache replacement way
output	[10:3]	dcc_dca_fill_addr_e;	// Dcache write index
output	[15:0]	dcc_dca_byte_wr_en_e;	// Dcache byte enables
output	[7:0]	dcc_parity_invert;
output		dcc_dta_parity;
output		dcc_alt_addr_sel_e;	// read/write addr select for dca
output		dcc_alt_way_sel_m;	// way source select for dca
output	[3:0]	dcc_alt_rsel_way_m;	// Way select for bist/diag
output	[10:4]	dcc_dta_fill_addr_e;	// Dtag write index
output	[1:0]	dcc_dta_fill_way_e;	// Dcache replacement way
output		dcc_dta_wvld_e;		// dtag write enable
output		dcc_dta_rvld_e;		// dtag read enable
output		dcc_dta_index1_sel_e;	// dtag address select
output		dcc_dta_clken;		// dtag clock enable
output		dcc_dva_wvld_e;		// dva write enable
output		dcc_dva_rvld_e;		// dva write enable
output		dcc_dva_din_e;		// dva write data
output		dcc_dva_din2_e;		// dva write data (redundant copy)
output	[10:6]	dcc_dva_wr_addr_e;	// dva update address
output	[15:0]	dcc_dva_bit_wen_e;	// Valid bit mapping
output		dcc_cache_diag_wr_m;
output		dcc_cache_diag_wr_b;
output		dcc_lru_rvld_e;
output		dcc_lru_wvld_w;
output	[5:0]	dcc_lru_wdata_w;
output	[3:0]	dcc_lru_wen_w;
output	[10:6]	dcc_lru_wr_addr_w;
output	[7:0]	dcc_ldst_bmask;
output		dcc_bmask_parity_b;

output		dcc_ld_miss_b;		// Load needs to go to L2
output		dcc_early_ld_b;		// Load with D$ enabled to pcx
output		dcc_stb_quad_ld_cam;

output		dcc_l2fill_vld_m;

output	[1:0]	dcc_ctxt_tid0_d;
output	[1:0]	dcc_ctxt_tid1_d;
output		dcc_ctxt_tg_d;
output	[2:0]	dcc_tid_e;		// Used by other blocks in the LSU
output	[2:0]	dcc_tid_m;		// Used by other blocks in the LSU
output	[2:0]	dcc_tid_b;		// Used by other blocks in the LSU
output	[7:0]	dcc_asi_m;
output		dcc_ld_inst_unqual_e;
output		dcc_ld_inst_vld_m;
output		dcc_stb_cam_vld_m;
output	[2:0]	dcc_baddr_m;
output		dcc_signed_m;
output		dcc_pref_inst_m;
output		dcc_std_inst_m;
output		dcc_ldstub_inst_m;
output		dcc_atomic_b;
output		dcc_casa_inst_b;
output		dcc_lendian_pre_m;
output		dcc_bendian_byp_m;
output		dcc_pst_asi_b;
output		dcc_tte_vld_m;
output	[1:0]	dcc_ldst_sz_m;		// Size for loads and stores
output	[1:0]	dcc_ld_sz_m;		// Size for loads
output		dcc_fp32b_sel_m;	// Selects 32b fp store data
output		dcc_blk_inst_m;		// Block load/store instruction in pipe
output		dcc_blk_inst_b;		// Block load/store instruction in pipe
output		dcc_ldbl_b;		// Double return instruction (LDD/QUAD/BLD)
output		dcc_ncache_b;
output	[1:0]	dcc_st_rq_type_w;
output		dcc_sync_pipe_w;	// so other blocks know when an instruction was sync'ed
output		dcc_priv_b;
output		dcc_hpriv_b;
output		dcc_pctxt_sel_e;
output		dcc_sctxt_sel_e;
output		dcc_ld_miss_ldd;
output	[60:40]	dcc_ld_miss_ctl;	// Load miss info for the LMQ

output	[7:0]	dcc_sync_inst_w;	// Sync instruction to store buffers

output	[7:0]	dcc_asi_reload_sel;
output	[7:0]	dcc_wr_wtchpt;
output	[7:0]	dcc_wr_lsu_ctl_reg;
output		dcc_wr_pwr_mgmt;
output		dcc_ceter_wr_w;
output		dcc_p0ctxt_rd_m;
output		dcc_p1ctxt_rd_m;
output		dcc_s0ctxt_rd_m;
output		dcc_s1ctxt_rd_m;
output		dcc_pid_rd_m;
output		dcc_wtchpt_sel_m;
output		dcc_demap_asi_m;
output		dcc_wtchpt_rd_b;
output		dcc_rd_lsu_ctl_reg_b;
output		dcc_rd_diag_reg_b;
output		dcc_rd_diag_dca_b;
output		dcc_rd_core_id_b;
output		dcc_rd_intr_id_b;
output		dcc_rd_dt_diag_m;
output		dcc_rd_dt_diag_b;
output		dcc_stb_diag_rd_m;
output		dcc_rd_error_inj_b;
output		dcc_rd_pwr_mgmt_b;
output		dcc_wr_error_inj_m;
output		dcc_wr_error_inj_w;	// flush qualified
output		dcc_tlb_data_read_b;
output		dcc_tlb_tag0_read_b;
output		dcc_tlb_tag1_read_b;
output		dcc_tlb_rw_index_e;
output		dcc_rd_rhs_asi_b;	// reading an ASI on the right hand side
output		dcc_lsu_asi_rd_b;
output		dcc_lsu_asi_sel_w;
output		dcc_stb_diag_sel_w3;
output		dcc_stb_data_rd_w3;
output		dcc_stb_ecc_rd_w3;
output		dcc_stb_ctl_rd_w3;
output		dcc_stb_addr_sel_w3;
output		dcc_stb_ptr_rd_w3;
output		dcc_direct_map;		// output for diag reads only
output		dcc_dcs_memref_e;	// Used for power management
output		dcc_tlb_lookup;
output		dcc_tlb_bypass;
output		dcc_tlb_real;
output		dcc_tlb_rd_e;
output		dcc_perror_b;
output	[1:0]	dcc_perr_enc_b;		// error encoding
output	[3:0]	dcc_dmo_parity;

output	[12:3]	lsu_va_w;

output		dcc_sbd_e_clken;
output		dcc_sbd_m_clken;
output		dcc_ldst_m_clken;	// ld/st instruction in M

output	[7:0]	dcc_asi_rtn_vld;
output		dcc_asi_rtn_excp;
output		dcc_asi_rtn_rd;

output		lsu_exu_ld_vld_w;	// Valid data is being sent to the IRF
output		lsu_exu_ld_b;
output	[2:0]	lsu_exu_tid_m;		// Thread ID of return data
output	[4:0]	lsu_exu_rd_m;		
output		lsu_fgu_fld_vld_w;	// Valid data is being sent to the FRF
output		lsu_fgu_fld_b;
output		lsu_fgu_fld_32b_b;
output		lsu_fgu_fld_odd32b_b;
output		lsu_fgu_fsr_load_b;
output	[2:0]	lsu_fgu_fld_tid_b;	// Thread ID of return data
output	[4:0]	lsu_fgu_fld_addr_b;		
output		lsu_fgu_exception_w;
output	[7:0]	lsu_sync;		// Flush thread
output	[7:0]	lsu_complete;		// Restart the thread
output		lsu_cpq_stall;		// Stall pipe at decode

output		lsu_tlu_twocycle_m;		// A two-cycle op is in M
output		lsu_tlb_bypass_b;
output		lsu_tlb_real_b;
output		lsu_align_b;
output		lsu_lddf_align_b;
output		lsu_stdf_align_b;
output		lsu_dae_invalid_asi_b;
output		lsu_dae_nc_page_b;
output		lsu_dae_nfo_page_b;
output		lsu_dae_priv_viol_b;
output		lsu_dae_so_page;
output		lsu_priv_action_b;
output		lsu_va_watchpoint_b;
output		lsu_pa_watchpoint_b;
output		lsu_illegal_inst_b;
output		lsu_daccess_prot_b;
output 		lsu_tlb_miss_b_;
output		lsu_perfmon_trap_b;
output		lsu_perfmon_trap_g;
output	[1:0]	lsu_tlu_dsfsr_ct_b;

output		lsu_sync_inst_b;
output		lsu_dttp_err_b;
output		lsu_dtdp_err_b;
output		lsu_dtmh_err_b;

output		lsu_ifu_direct_map;

output		dcc_mbi_run;
output		lsu_mbi_dca_fail;
output		lsu_mbi_lru_fail;

input		pmu_lsu_dcmiss_trap_m;
input		pmu_lsu_dtmiss_trap_m;
input	[7:0]	pmu_lsu_l2dmiss_trap_m;

output	[2:0]	lsu_pmu_mem_type_b;	// 2:0 - {l2 d-miss, dt_miss, d-cache miss}

input		lsu_dc_pmen;
input		lsu_lsu_pmen;		// Dynamic power management enable
output		lsu_lsu_pmen_;

// Globals
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

//////////////////////////////
// Clock header
//////////////////////////////
lsu_dcc_ctl_l1clkhdr_ctl_macro clkgen_pm (
        .l2clk  (l2clk                          ),
        .l1en   (dcc_pm_clken                   ),
        .l1clk  (l1clk_pm1                      ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

lsu_dcc_ctl_l1clkhdr_ctl_macro clkgen_ifu_indx (
        .l2clk  (l2clk                          ),
        .l1en   (ifu_indx_clken                 ),
        .l1clk  (l1clk_pm2                      ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

lsu_dcc_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk                          ),
        .l1en   (1'b1                           ),
        .l1clk  (l1clk                          ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

lsu_dcc_ctl_msff_ctl_macro__width_7 dff_cerer  (
	.scan_in(dff_cerer_scanin),
	.scan_out(dff_cerer_scanout),
	.l1clk	(l1clk_pm1),
	.din	({tlu_cerer_dttp,tlu_cerer_dttm, tlu_cerer_dtdp,tlu_cerer_dcvp,tlu_cerer_dctp,
		  tlu_cerer_dctm,tlu_cerer_dcdp}),
	.dout	({cerer_dttp,    cerer_dttm,     cerer_dtdp,    cerer_dcvp,    cerer_dctp,    
		  cerer_dctm,    cerer_dcdp}),
  .siclk(siclk),
  .soclk(soclk)
);

//////////////////////////////
// Flush logic
//////////////////////////////

// Factor upstream exceptions into flush.  VA error is ignored if tlb_bypass.
assign exu_error_m = tid_m[2] ? (exu_ecc_m[1] | (exu_lsu_va_error_m[1] & ~tlb_bypass_m)) :
                                (exu_ecc_m[0] | (exu_lsu_va_error_m[0] & ~tlb_bypass_m)) ;
assign exu_error_qual_m = exu_error_m & (ld_inst_vld_m | st_inst_vld_m | flush_inst_m | mb_inst_m);

assign exu_va_oor_m = tid_m[2] ? exu_lsu_va_error_m[1] : exu_lsu_va_error_m[0];

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_flush_b  (
	.scan_in(dff_flush_b_scanin),
	.scan_out(dff_flush_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dec_flush_lm,exu_error_qual_m,exu_va_oor_m}),
	.dout	({pipe_flush_b,exu_error_pre_b, exu_va_oor_b}),
  .siclk(siclk),
  .soclk(soclk)
);

// Need to take into account ECC errors on the second read of a STD instruction
assign exu_error_b = exu_error_pre_b | 
                     ((tid_b[2] ? exu_ecc_m[1] : exu_ecc_m[0]) & twocycle_b);

// Internally generated flush conditions
assign fgu_error_b = fgu_fst_ecc_error_fx2 & st_inst_vld_b & fpldst_inst_vld_b;

assign dcc_exception_flush_b = dcc_any_exception_b | exu_error_b | fgu_error_b;

assign flush_b = dec_flush_lb | pipe_flush_b | dcc_any_exception_b | exu_error_b | fgu_error_b;

assign flush_all_b = flush_b | tlu_flush_lsu_b;

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_flush_w  (
	.scan_in(dff_flush_w_scanin),
	.scan_out(dff_flush_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	(flush_all_b),
	.dout	(flush_w),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Stage the main lsu controls coming from the decode and trap units.
////////////////////////////////////////////////////////////////////////////////

// 0in bits_on -var {(dec_ld_inst_e | dec_st_inst_e) & altspace_e,(dec_ld_inst_e | dec_st_inst_e) & dec_sr_inst_e,(dec_ld_inst_e | dec_st_inst_e) & dec_pr_inst_e,(dec_ld_inst_e | dec_st_inst_e) & dec_hpr_inst_e} -max 1

lsu_dcc_ctl_msff_ctl_macro__width_12 dff_asi_d  (
	.scan_in(dff_asi_d_scanin),
	.scan_out(dff_asi_d_scanout),
	.din	({dec_imm_asi_vld_d, asi_d[7:0],     dec_altspace_d,dcs_dmmu_enable_d,dec_ld_inst_d}),
	.dout	({dcc_imm_asi_vld_e, dcc_asi_e[7:0], altspace_e,    dmmu_enable_e,    ld_inst_unqual_e}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_ld_inst_unqual_e = ld_inst_unqual_e;

assign asi_d[7:0] = dec_imm_asi_vld_d ? dec_imm_asi_d[7:0] : dcs_asi_d[7:0];

assign asx_e[7:0] = ({8{asi_use_rd_e}} & {3'b000,dec_lsu_rd_e[4:0]}) |
                    ({8{asi_use_sr_e}} & {3'b000,dec_sraddr_e[4:0]}) |
                    ({8{~(asi_use_rd_e | asi_use_sr_e)}} & dcc_asi_e[7:0]);

assign dcc_tlb_lookup = mbi_run_local ? bist_cam_en :
                       ((dec_ld_inst_e | dec_st_inst_e) & ~asi_internal_e & ~dcc_tlb_bypass) ;

assign dcc_tlb_rw_index_e = ld_inst_unqual_e;

// dcc_memref_e is used to gate registers for power management
assign dcc_dcs_memref_e = dec_ld_inst_e | dec_st_inst_e | mbi_run_local | lsu_lsu_pmen_ ;

assign pref_inst_qual_e = dec_ld_inst_e & dec_pref_inst_e;

lsu_dcc_ctl_msff_ctl_macro__width_13 dff_dec_inst1_m  (
	.scan_in(dff_dec_inst1_m_scanin),
	.scan_out(dff_dec_inst1_m_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dec_ld_inst_e, dec_st_inst_e, dec_fpldst_inst_e, 
		 pref_inst_qual_e, 
		 dec_casa_inst_e, dec_ldstub_inst_e, dec_swap_inst_e,
		 dec_ldst_dbl_e, dec_sr_inst_e, dec_pr_inst_e, dec_hpr_inst_e,
	         dec_fsr_ldst_e, dcc_imm_asi_vld_e}),
	.dout	({ld_inst_vld_m, st_inst_vld_m, fpldst_inst_vld_m,
		 pref_inst_m,    
		 casa_inst_pre_m, ldstub_inst_pre_m, swap_inst_pre_m,
		 ldst_dbl_m,     sr_inst_m,     pr_inst_m,     hpr_inst_m,
	         fsr_ldst_m,     imm_asi_vld_m}),
  .siclk(siclk),
  .soclk(soclk)
);

assign casa_inst_m = casa_inst_pre_m & st_inst_vld_m;
assign swap_inst_m = swap_inst_pre_m & st_inst_vld_m;
assign ldstub_inst_m = ldstub_inst_pre_m & st_inst_vld_m;
assign dcc_ldstub_inst_m = ldstub_inst_m;

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_sync_inst  (
	.scan_in(dff_sync_inst_scanin),
	.scan_out(dff_sync_inst_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dec_memstbar_inst_e, dec_flush_inst_e,sync_inst_m}),
	.dout	({mb_inst_m,           flush_inst_m,    sync_inst_pre_b}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_ld_inst_vld_m = ld_inst_vld_m; 	// Used in other blocks

assign dcc_stb_cam_vld_m = mbi_run_local ? mbi_scm_cam_en :
       (ld_inst_vld_m & ~pref_inst_m & ~atomic_m & ~asi_internal_m & ~dec_flush_lm & ~blk_inst_m);

assign dcc_pref_inst_m = pref_inst_m;	 	// Used in other blocks
assign dcc_std_inst_m = ldst_dbl_m & st_inst_vld_m & ~fpldst_inst_vld_m;
assign dcc_fp32b_sel_m = fpldst_inst_vld_m & ldst_sz_mod_m[1] & ~ldst_sz_mod_m[0];

assign atomic_m = casa_inst_m | ldstub_inst_m | swap_inst_m;

// Use lbist_run here to force the store address mux.
assign dcc_asi_iomap_m = asi_iomap_m;

assign sync_inst_m = flush_inst_m | mb_inst_m | (asi_sync_m & st_inst_vld_m);

lsu_dcc_ctl_msff_ctl_macro__width_8 dff_dec_ctl_m  (
	.scan_in(dff_dec_ctl_m_scanin),
	.scan_out(dff_dec_ctl_m_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dec_ldst_sz_e[1:0], dec_lsu_rd_e[4:0], dec_sign_ext_e}),
	.dout	({ldst_sz_m[1:0],     ld_rd_inst_m[4:0], sign_ext_m}),
  .siclk(siclk),
  .soclk(soclk)
);

// Modify the size bits for short and paritial ASIs
assign ldst_sz_mod_m[1] = (ldst_sz_m[1] & ~asi_sz_byte_m & ~asi_sz_hw_m) | (ldst_sz_m[1] & ~asi_legal_m);
assign ldst_sz_mod_m[0] = (ldst_sz_m[0] & (~asi_sz_byte_m | ~asi_legal_m)) | (asi_sz_hw_m & asi_legal_m);

// The sign_ext and ldst_fsr bits share the same status bit since sign_ext
// only has meaning in the integer context and ldst_fsr in the fp context.
// NOTE: Add an assertion to check that sign_ext is never valid for fpldst instructions.
assign sxt_fsr_m = fsr_ldst_m | sign_ext_m;

assign dcc_ldst_sz_m[1:0] = ldst_sz_mod_m[1:0];	// For use elsewhere in the LSU

// Rd must be swizzled for fp loads
assign ld_rd_m[4:0] = ({5{~fpldst_inst_vld_m}} & ld_rd_inst_m[4:0]) |			// Int
                      ({5{fpldst_inst_vld_m & ldst_sz_m[0]}} &
                           {ld_rd_inst_m[0],ld_rd_inst_m[4:1]})	    |			// Fp64
                      ({5{fpldst_inst_vld_m & ~ldst_sz_m[0]}} &
                           {1'b0,ld_rd_inst_m[4:1]});		    			// Fp32

assign asi_type_m[1] = (pr_inst_m | hpr_inst_m) & (ld_inst_vld_m | st_inst_vld_m);
assign asi_type_m[0] = (sr_inst_m | hpr_inst_m) & (ld_inst_vld_m | st_inst_vld_m);

lsu_dcc_ctl_msff_ctl_macro__width_9 dff_dec_inst_b  (
	.scan_in(dff_dec_inst_b_scanin),
	.scan_out(dff_dec_inst_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ld_inst_vld_m, st_inst_vld_m, fpldst_inst_vld_m,
		 pref_inst_m, casa_inst_m,
		 ldst_dbl_m, atomic_m, asi_type_m[1:0]}),
	.dout	({ld_inst_vld_b,  st_inst_vld_b, fpldst_inst_vld_b,
		 pref_inst_b, casa_inst_b, 
		 ldst_dbl_b, atomic_b, asi_type_b[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Partial stores with TTE.IE=1 sync the thread so that later loads don't have
// to deal with an inverted byte mask in the CAM
assign sync_inst_b = sync_inst_pre_b | (pst_asi_b & tlb_tte_ie_b & tlb_tte_vld_b & st_inst_vld_b);

assign lsu_sync_inst_b = sync_inst_b;
assign dcc_atomic_b = atomic_b;
assign dcc_casa_inst_b = casa_inst_b;

lsu_dcc_ctl_msff_ctl_macro__width_7 dff_dec_ctl_b  (
	.scan_in(dff_dec_ctl_b_scanin),
	.scan_out(dff_dec_ctl_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ldst_sz_mod_m[1:0], ld_rd_m[4:0]}),
	.dout	({ldst_sz_b[1:0],     ld_rd_b[4:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// TLU has to know about two cycle ops in case the second cycle IRF read results 
// in an ECC error
assign lsu_tlu_twocycle_m = casa_inst_m | (ldst_dbl_m & st_inst_vld_m & ~fpldst_inst_vld_m);
assign twocycle_b = casa_inst_b | (ldst_dbl_b & st_inst_vld_b & ~fpldst_inst_vld_b);

// Manipulate size to that non-quad ldd's are words and quad ldd's are dword
assign ldst_sz_b0_b = (ldst_sz_b[0] & (~ldst_dbl_b | fpldst_inst_vld_b)) |
                      (ldst_dbl_b & ~fpldst_inst_vld_b & quad_asi_b);

// Thread ID staging and decode.

assign tid_d[2:0] = dec_lsu_tg_d ? {1'b1,dec_lsu_tid1_d[1:0]} : {1'b0,dec_lsu_tid0_d[1:0]};
assign thread0_d = ~tid_d[2] & ~tid_d[1] & ~tid_d[0];
assign thread1_d = ~tid_d[2] & ~tid_d[1] &  tid_d[0];
assign thread2_d = ~tid_d[2] &  tid_d[1] & ~tid_d[0];
assign thread3_d = ~tid_d[2] &  tid_d[1] &  tid_d[0];
assign thread4_d =  tid_d[2] & ~tid_d[1] & ~tid_d[0];
assign thread5_d =  tid_d[2] & ~tid_d[1] &  tid_d[0];
assign thread6_d =  tid_d[2] &  tid_d[1] & ~tid_d[0];
assign thread7_d =  tid_d[2] &  tid_d[1] &  tid_d[0];

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_tid_e  (
	.scan_in(dff_tid_e_scanin),
	.scan_out(dff_tid_e_scanout),
	.din	(tid_d[2:0]),
	.dout	(tid_e[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign thread0_e = ~tid_e[2] & ~tid_e[1] & ~tid_e[0];
assign thread1_e = ~tid_e[2] & ~tid_e[1] &  tid_e[0];
assign thread2_e = ~tid_e[2] &  tid_e[1] & ~tid_e[0];
assign thread3_e = ~tid_e[2] &  tid_e[1] &  tid_e[0];
assign thread4_e =  tid_e[2] & ~tid_e[1] & ~tid_e[0];
assign thread5_e =  tid_e[2] & ~tid_e[1] &  tid_e[0];
assign thread6_e =  tid_e[2] &  tid_e[1] & ~tid_e[0];
assign thread7_e =  tid_e[2] &  tid_e[1] &  tid_e[0];

assign dcc_tid_e[2:0] = tid_e[2:0];	// for distribution to other blocks

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_tid_m  (
	.scan_in(dff_tid_m_scanin),
	.scan_out(dff_tid_m_scanout),
	.l1clk	(l1clk_pm1),
	.din	(tid_e[2:0]),
	.dout	(tid_m[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_tid_m[2:0] = tid_m[2:0];	// for distribution to other blocks

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_tid_b  (
	.scan_in(dff_tid_b_scanin),
	.scan_out(dff_tid_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(tid_m[2:0]),
	.dout	(tid_b[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_tid_b[2:0] = tid_b[2:0];	// for distribution to other blocks

assign thread0_b = ~tid_b[2] & ~tid_b[1] & ~tid_b[0];
assign thread1_b = ~tid_b[2] & ~tid_b[1] &  tid_b[0];
assign thread2_b = ~tid_b[2] &  tid_b[1] & ~tid_b[0];
assign thread3_b = ~tid_b[2] &  tid_b[1] &  tid_b[0];
assign thread4_b =  tid_b[2] & ~tid_b[1] & ~tid_b[0];
assign thread5_b =  tid_b[2] & ~tid_b[1] &  tid_b[0];
assign thread6_b =  tid_b[2] &  tid_b[1] & ~tid_b[0];
assign thread7_b =  tid_b[2] &  tid_b[1] &  tid_b[0];

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_tid_w  (
	.scan_in(dff_tid_w_scanin),
	.scan_out(dff_tid_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	(tid_b[2:0]),
	.dout	(tid_w[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign thread_w[0] = ~tid_w[2] & ~tid_w[1] & ~tid_w[0];
assign thread_w[1] = ~tid_w[2] & ~tid_w[1] &  tid_w[0];
assign thread_w[2] = ~tid_w[2] &  tid_w[1] & ~tid_w[0];
assign thread_w[3] = ~tid_w[2] &  tid_w[1] &  tid_w[0];
assign thread_w[4] =  tid_w[2] & ~tid_w[1] & ~tid_w[0];
assign thread_w[5] =  tid_w[2] & ~tid_w[1] &  tid_w[0];
assign thread_w[6] =  tid_w[2] &  tid_w[1] & ~tid_w[0];
assign thread_w[7] =  tid_w[2] &  tid_w[1] &  tid_w[0];

assign fpld_32b_m = ~ldst_sz_m[0];
assign fpld_odd32b_m = ~ldst_sz_m[0] & ld_rd_inst_m[0];


// Stage and qualify controls

assign altspace_ldst_e = altspace_e & (dec_ld_inst_e | dec_st_inst_e);

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_altspace_m  (
	.scan_in(dff_altspace_m_scanin),
	.scan_out(dff_altspace_m_scanout),
	.l1clk	(l1clk_pm1),
	.din	(altspace_ldst_e),
	.dout	(altspace_ldst_m),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_altspace_b  (
	.scan_in(dff_altspace_b_scanin),
	.scan_out(dff_altspace_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(altspace_ldst_m),
	.dout	(altspace_ldst_b),
  .siclk(siclk),
  .soclk(soclk)
);

assign fpld_inst_m = ld_inst_vld_m & (fpldst_inst_vld_m | fsr_ldst_m);
lsu_dcc_ctl_msff_ctl_macro__width_1 dff_fpld_b  (
	.scan_in(dff_fpld_b_scanin),
	.scan_out(dff_fpld_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(fpld_inst_m),
	.dout	(fpld_inst_b),
  .siclk(siclk),
  .soclk(soclk)
);


assign blk_inst_m = blk_asi_m & asi_legal_m & ldst_dbl_m & fpldst_inst_vld_m;
assign dcc_blk_inst_m = blk_inst_m;
assign dcc_blk_inst_b = blk_asi_b & altspace_ldst_b & ldst_dbl_b;

assign dcc_ldbl_b = ld_inst_vld_b & ldst_dbl_b & ~fpld_inst_b;

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_oddrd  (
	.scan_in(dff_oddrd_scanin),
	.scan_out(dff_oddrd_scanout),
	.din	(cic_oddrd_e),
	.dout	(oddrd_m),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// LD/ST byte mask generation
////////////////////////////////////////////////////////////////////////////////
// For a normal ldst, the mask is based on the size and address.  For partial stores,
// the mask will come from rs2.

lsu_dcc_ctl_msff_ctl_macro__width_8 dff_rs2_m  (
	.scan_in(dff_rs2_m_scanin),
	.scan_out(dff_rs2_m_scanout),
	.l1clk	(l1clk_pm1),
	.din	(exu_lsu_rs2_e[7:0]),
	.dout	(rs2_m[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

//assign ldst_byte  = ~ldst_sz_mod_m[1] & ~ldst_sz_mod_m[0];
//assign ldst_hword = ~ldst_sz_mod_m[1] &  ldst_sz_mod_m[0];
//assign ldst_word  =  ldst_sz_mod_m[1] & ~ldst_sz_mod_m[0];
//assign ldst_dword =  ldst_sz_mod_m[1] &  ldst_sz_mod_m[0];

assign ldst_byte  = bad_fp_asi ? (ldst_sz_m[1:0] == 2'b00) : (ldst_sz_mod_m[1:0] == 2'b00);
assign ldst_hword = bad_fp_asi ? (ldst_sz_m[1:0] == 2'b01) : (ldst_sz_mod_m[1:0] == 2'b01);
assign ldst_word  = bad_fp_asi ? (ldst_sz_m[1:0] == 2'b10) : (ldst_sz_mod_m[1:0] == 2'b10);
assign ldst_dword = bad_fp_asi ? (ldst_sz_m[1:0] == 2'b11) : (ldst_sz_mod_m[1:0] == 2'b11);

assign ldst_bmask[7] = (~lsu_va_m[2] & ~lsu_va_m[1] & ~lsu_va_m[0]);

assign ldst_bmask[6] = (~lsu_va_m[2] & ~lsu_va_m[1] & ~ldst_byte) | 
                       (~lsu_va_m[2] & ~lsu_va_m[1] & lsu_va_m[0]);

assign ldst_bmask[5] = (~lsu_va_m[2] & ~ldst_byte & ~ldst_hword) |
                       (~lsu_va_m[2] & lsu_va_m[1] & ~lsu_va_m[0]);

assign ldst_bmask[4] = (~lsu_va_m[2] & lsu_va_m[1] & ldst_hword) |
                       (~lsu_va_m[2] & ~ldst_byte & ~ldst_hword) |
                       (~lsu_va_m[2] & lsu_va_m[1] & lsu_va_m[0]);

assign ldst_bmask[3] = (ldst_dword) |
                       (lsu_va_m[2] & ~lsu_va_m[1] & ~lsu_va_m[0]);

assign ldst_bmask[2] = (ldst_dword) |
                       (lsu_va_m[2] & ~lsu_va_m[1] & ~ldst_byte) |
                       (lsu_va_m[2] & ~lsu_va_m[1] & lsu_va_m[0]);

assign ldst_bmask[1] = (ldst_dword) |
                       (lsu_va_m[2] & ldst_word) |
                       (lsu_va_m[2] & lsu_va_m[1] & ~lsu_va_m[0]);

assign ldst_bmask[0] = (ldst_dword) |
                       (lsu_va_m[2] & lsu_va_m[1] & ldst_hword) |
                       (lsu_va_m[2] & ldst_word) |
                       (lsu_va_m[2] & lsu_va_m[1] & lsu_va_m[0]);

assign pst_bmask[7:0] = ({8{asi_pst32_m}} & {{4{rs2_m[1]}},{4{rs2_m[0]}}}) |
                        ({8{asi_pst16_m}} & {{2{rs2_m[3]}},{2{rs2_m[2]}},{2{rs2_m[1]}},{2{rs2_m[0]}}}) |
                        ({8{asi_pst8_m}} & rs2_m[7:0]);

assign lend_pst_bmask[7:0] = {pst_bmask[0],pst_bmask[1],pst_bmask[2],pst_bmask[3],
                              pst_bmask[4],pst_bmask[5],pst_bmask[6],pst_bmask[7]};


// 0in bits_on -var {(asi_legal_m & asi_store_m),(asi_legal_m & pst_asi_m)} -max 1
assign ldst_bmask_mod[7:0] = ({8{asi_store_m}} & (dcc_asi_m[7:0] | {8{asi_iomap_m}})) | 
                              ({8{pst_asi_m & lendian_asi_m}}  & lend_pst_bmask[7:0]) |
                              ({8{pst_asi_m & ~lendian_asi_m}} & pst_bmask[7:0]) |
                              ({8{~asi_store_m & ~pst_asi_m}}  & (ldst_bmask[7:0] | {8{sbc_bst_in_prog_m}}));

assign dcc_ldst_bmask[7:0] = mbi_run_local ? mbi_wdata[7:0] : ldst_bmask_mod[7:0];

assign st_bmask_parity_m = ^(ldst_bmask_mod[7:0]);

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_sba_par  (
	.scan_in(dff_sba_par_scanin),
	.scan_out(dff_sba_par_scanout),
	.din	(st_bmask_parity_m),
	.dout	(dcc_bmask_parity_b),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Hit/miss signaling
////////////////////////////////////////////////////////////////////////////////

// Need to track flushes through the pipe so lsu_sync isn't fired repeatedly.
// PKU will ignore an lsu_sync that asserts in the same cycle as dec_flush_lb
// since doing so here would create a bad timing path.  I'm responsible for
// tracking the flush_m.

// TLU flush can be ignored because the primary purpose of flush_b is to prevent
// the LMQ from loading on a flushed load.  If the flushed load is due to a
// previous load miss, that's handled by the dec_flush_lb.  If the load is flushed
// due to a trap, the LMQ will be loaded but the valid bit won't be set.

// This is a true load miss indicator used for advancing the rr replacement counter.
//assign l1_ld_miss_b = ld_inst_vld_b & ~tlb_cache_hit_b & ~flush_b;
assign l1_ld_miss_b = ld_inst_vld_b & ~(tlb_cache_hit_b & dcache_enable_b);

// In addition to true load misses, this signal asserts on any load type instruction
// that needs to go to L2.  (Ex. atomics, LDD, blk-ld, etc.)  This will cause the
// LMQ to load the miss information and begin requesting pcx access. 
assign dcc_ld_miss_b = (l1_ld_miss_b | ncache_rq_b | dcc_perror_b) & ld_inst_vld_b;

// True load misses are eligible to request pcx access in B.  The arbitration
// will be done in lsu_pic_ctl.  The cache hit result is sent there to be AND'ed
// with this signal.  If the D$ is disabled, loads cannot request early.
assign early_ld_m = ld_inst_vld_m & ~asi_internal_m & ~(blk_asi_m & altspace_ldst_m & ldst_dbl_m) &
                    ~atomic_m & ~(ldst_dbl_m & ~fpld_inst_m) & ~pref_inst_m & dcache_enable_m & ~dec_flush_lm;

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_early_ld  (
	.scan_in(dff_early_ld_scanin),
	.scan_out(dff_early_ld_scanout),
	.l1clk	(l1clk_pm1),
	.din	(early_ld_m),
	.dout	(dcc_early_ld_b),
  .siclk(siclk),
  .soclk(soclk)
);

//assign dcc_early_ld_b = ld_inst_vld_b & ~asi_internal_b & ~dcc_blk_inst_b & ~atomic_b & ~dcc_ldbl_b & ~pref_inst_b & dcache_enable_b;

// lsu_sync tells the IFU that the instruction in B cannot complete in the normal
// pipeline.  IFU will flush the thread and refetch from the next instruction.
// The thread must be restarted by either a lsu_complete signal or a trap flush.
// Cannot use flush_b as a factor here because that would create a roundtrip
// between lsu and dec.
assign sync_pipe = ((((l1_ld_miss_b | ncache_rq_b | dcc_perror_b) & ~asi_dcd_diag_rd_b & ld_inst_vld_b) | 
                     (((altspace_ldst_b & blk_asi_b) | asi_sync_b | (pst_asi_b & tlb_tte_ie_b & tlb_tte_vld_b)) & st_inst_vld_b) |
                     lsu_dtmh_err_b
                    ) & ~pipe_flush_b
                   ) | stb_cam_hit | lbist_run ;

assign lsu_sync[0] = sync_pipe & thread0_b;
assign lsu_sync[1] = sync_pipe & thread1_b;
assign lsu_sync[2] = sync_pipe & thread2_b;
assign lsu_sync[3] = sync_pipe & thread3_b;
assign lsu_sync[4] = sync_pipe & thread4_b;
assign lsu_sync[5] = sync_pipe & thread5_b;
assign lsu_sync[6] = sync_pipe & thread6_b;
assign lsu_sync[7] = sync_pipe & thread7_b;

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_sync_pipe  (
	.scan_in(dff_sync_pipe_scanin),
	.scan_out(dff_sync_pipe_scanout),
	.l1clk	(l1clk_pm1),
	.din	(sync_pipe),
	.dout	(dcc_sync_pipe_w),
  .siclk(siclk),
  .soclk(soclk)
);

// Must track cases where thread was stopped due to a store event.  If a
// disrupting store buffer error occurs while the thread is stopped due
// to a store event, lsu_complete must be sent to restart the thread.

assign sync_st_in[7:0] = ((thread_w[7:0] & {8{dcc_sync_pipe_w & st_inst_vld_w & ~flush_w}}) | sync_st[7:0]) &
                         ~lsu_complete[7:0];

lsu_dcc_ctl_msff_ctl_macro__width_8 dff_sync_st  (
	.scan_in(dff_sync_st_scanin),
	.scan_out(dff_sync_st_scanout),
	.din	(sync_st_in[7:0]),
	.dout	(sync_st[7:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Complete signaling
////////////////////////////////////////////////////////////////////////////////

// lsu_complete can only be signalled following an lsu_sync or postsync.

assign lsu_complete[0] = (cic_rtn_cmplt & (cid_tid[2:0] == 3'd0) & ~lmc_bld_annul) |
                         lmc_thrd_byp_sel_e[0] | lsu_block_store_alloc[0] |
                         lmc_pref_issued[0] | lsu_trap_flush[0] | 
                         (sync_st[0] & lsu_block_store_kill[0]);
assign lsu_complete[1] = (cic_rtn_cmplt & (cid_tid[2:0] == 3'd1) & ~lmc_bld_annul) |
                         lmc_thrd_byp_sel_e[1] | lsu_block_store_alloc[1] |
                         lmc_pref_issued[1] | lsu_trap_flush[1] | 
                         (sync_st[1] & lsu_block_store_kill[1]);
assign lsu_complete[2] = (cic_rtn_cmplt & (cid_tid[2:0] == 3'd2) & ~lmc_bld_annul) |
                         lmc_thrd_byp_sel_e[2] | lsu_block_store_alloc[2] |
                         lmc_pref_issued[2] | lsu_trap_flush[2] | 
                         (sync_st[2] & lsu_block_store_kill[2]);
assign lsu_complete[3] = (cic_rtn_cmplt & (cid_tid[2:0] == 3'd3) & ~lmc_bld_annul) |
                         lmc_thrd_byp_sel_e[3] | lsu_block_store_alloc[3] |
                         lmc_pref_issued[3] | lsu_trap_flush[3] | 
                         (sync_st[3] & lsu_block_store_kill[3]);
assign lsu_complete[4] = (cic_rtn_cmplt & (cid_tid[2:0] == 3'd4) & ~lmc_bld_annul) |
                         lmc_thrd_byp_sel_e[4] | lsu_block_store_alloc[4] |
                         lmc_pref_issued[4] | lsu_trap_flush[4] | 
                         (sync_st[4] & lsu_block_store_kill[4]);
assign lsu_complete[5] = (cic_rtn_cmplt & (cid_tid[2:0] == 3'd5) & ~lmc_bld_annul) |
                         lmc_thrd_byp_sel_e[5] | lsu_block_store_alloc[5] |
                         lmc_pref_issued[5] | lsu_trap_flush[5] | 
                         (sync_st[5] & lsu_block_store_kill[5]);
assign lsu_complete[6] = (cic_rtn_cmplt & (cid_tid[2:0] == 3'd6) & ~lmc_bld_annul) |
                         lmc_thrd_byp_sel_e[6] | lsu_block_store_alloc[6] |
                         lmc_pref_issued[6] | lsu_trap_flush[6] | 
                         (sync_st[6] & lsu_block_store_kill[6]);
assign lsu_complete[7] = (cic_rtn_cmplt & (cid_tid[2:0] == 3'd7) & ~lmc_bld_annul) |
                         lmc_thrd_byp_sel_e[7] | lsu_block_store_alloc[7] |
                         lmc_pref_issued[7] | lsu_trap_flush[7] | 
                         (sync_st[7] & lsu_block_store_kill[7]);

////////////////////////////////////////////////////////////////////////////////
// Decode stall
// Stalls are requested at decode to allow cpq or bypass regs to drain.
// Also to clear holes for diagnostic accesses
////////////////////////////////////////////////////////////////////////////////

assign lsu_cpq_stall = cic_cpq_stall | lmc_ld_stall | stb_diag_rd_e | asi_cache_diag_wr_m;

////////////////////////////////////////////////////////////////////////////////
// Dcache Array Control
////////////////////////////////////////////////////////////////////////////////

assign dcache_enable_e = (thread0_e & dcs_dc_enable[0]) |
                         (thread1_e & dcs_dc_enable[1]) |
                         (thread2_e & dcs_dc_enable[2]) |
                         (thread3_e & dcs_dc_enable[3]) |
                         (thread4_e & dcs_dc_enable[4]) |
                         (thread5_e & dcs_dc_enable[5]) |
                         (thread6_e & dcs_dc_enable[6]) |
                         (thread7_e & dcs_dc_enable[7]) ;

assign dcache_read_e = dec_ld_inst_e &
                       (~(asi_internal_e | dec_pref_inst_e | dec_casa_inst_e | 
                         dec_ldstub_inst_e | dec_swap_inst_e) & dcache_enable_e) |
                       (asi_internal_e & (asi_dca_diag_rd_e | asi_dta_diag_rd_e));

assign dcache_nodiag_read_e = ld_inst_unqual_e &
                       (~(asi_internal_e | dec_pref_inst_e | dec_casa_inst_e |
                         dec_ldstub_inst_e | dec_swap_inst_e) & dcache_enable_e);

lsu_dcc_ctl_msff_ctl_macro__width_5 dc_enable  (
	.scan_in(dc_enable_scanin),
	.scan_out(dc_enable_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dcache_enable_e,dcache_enable_m,dcache_nodiag_read_e,dcache_read_m,dcc_dca_rvld_e}),
	.dout	({dcache_enable_m,dcache_enable_b,dcache_nodiag_read_m,dcache_read_b,dcc_dca_rvld_m}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcache_read_m = dcache_nodiag_read_m & ld_inst_vld_m;

assign ld_fill_e = cic_l2fill_vld_e & ~cid_ncache;

assign dcc_dca_wvld_e = mbi_run_local ? mbi_dca_write_en :
                       (ld_fill_e | 			// l2 fills
                        cic_st_update_e |		// store updates
                        dca_diag_wr_e );		// diagnostic write


// Data read enable
assign dcc_dca_rvld_e = mbi_run_local ? mbi_dca_read_en : dcache_read_e;

assign dcc_dca_clk_en_e = ld_inst_unqual_e | dcc_dca_wvld_e | mbi_run_local | ~lsu_dc_pmen;			// E stage
assign dcc_dca_wclk_en_e = dcc_dca_wvld_e | mbi_run_local | ~lsu_dc_pmen;					// E stage
assign dcc_dca_rclk_en_m = dcc_dca_rvld_m | l2fill_vld_m | lmc_byp_vld_m | mbi_run_local | ~lsu_dc_pmen;	// M stage

// Force bypass mode off during BIST and during macrotest if possible.
assign dcc_dca_bypass_e_ = ld_inst_unqual_e | mbi_run_local;
assign dcc_alt_addr_sel_e = ~ld_inst_unqual_e | mbi_run_local;

// Use alternate way for diag data reads and bist reads.  If not performing a diag or bist read,
// way zero must be selected to allow for cache bypassing.
assign dcc_alt_way_sel_m = asi_dca_diag_rd_m | ~ld_inst_vld_m | mbi_run_local;
assign dcc_alt_rsel_way_m[0] = (asi_dca_diag_rd_m & ~mbi_run_local & ~lsu_va_m[12] & ~lsu_va_m[11]) |
                               (mbi_run_local & ~bist_addr_1[8] & ~bist_addr_1[7]) |
                               ~(asi_dca_diag_rd_m | mbi_run_local);
assign dcc_alt_rsel_way_m[1] = mbi_run_local ? (~bist_addr_1[8] &  bist_addr_1[7]) :
                                (asi_dca_diag_rd_m & ~lsu_va_m[12] &  lsu_va_m[11]) ;
assign dcc_alt_rsel_way_m[2] = mbi_run_local ? ( bist_addr_1[8] & ~bist_addr_1[7]) :
                                (asi_dca_diag_rd_m &  lsu_va_m[12] & ~lsu_va_m[11]) ;
assign dcc_alt_rsel_way_m[3] = mbi_run_local ? ( bist_addr_1[8] &  bist_addr_1[7]) :
                                (asi_dca_diag_rd_m &  lsu_va_m[12] &  lsu_va_m[11]) ;

// Tag read/write enable
assign dcc_dta_rvld_e = mbi_run_local ? mbi_dta_read_en : dcache_read_e;
assign dcc_dta_wvld_e = mbi_run_local ? mbi_dta_write_en : (ld_fill_e | dta_diag_wr_e);
assign dcc_dta_clken = ld_inst_unqual_e | cic_cpq_ld_sel | dta_diag_wr_e | mbi_run_local | ~lsu_dc_pmen;
assign dcc_dta_index1_sel_e = ~ld_inst_unqual_e | mbi_run_local;

// Fill/bypass control
assign dcc_dca_fill_way_e[1:0] =
                  ({2{mbi_run_local}}                                     & mbi_addr[8:7]) |
                  ({2{(cic_cpq_ld_sel | diag_write_e) & ~mbi_run_local}}  & lmd_fill_way_e[1:0]) |
                  ({2{~(mbi_run_local | cic_cpq_ld_sel | dca_diag_wr_e)}} & cid_st_way[1:0]);

assign dcc_dta_fill_way_e[1:0] = mbi_run_local ? mbi_addr[8:7] : lmd_fill_way_e[1:0];

assign dcc_dca_fill_addr_e[10:3] =
                  ({8{mbi_run_local}}                                    & {mbi_addr[6:0],mbi_cmpsel}) |
                  ({8{(cic_cpq_ld_sel | diag_write_e) & ~mbi_run_local}} & lmd_fill_addr_e[10:3]) |
                  ({8{~(mbi_run_local | cic_cpq_ld_sel | diag_write_e)}} & cid_st_addr[10:3]);

assign dcc_dta_fill_addr_e[10:4] = mbi_run_local ? mbi_addr[6:0] : lmd_fill_addr_e[10:4];

// 0in bits_on -var {ld_fill_e,diag_write_e} -max 1

// Fills from L2 update all bytes.  Stores are selective.
assign dcc_dca_byte_wr_en_e[15:0] = 
  ({16{dca_diag_wr_e}} & {{8{~va_w[3]}},{8{va_w[3]}}}) |
  ({16{(cic_cpq_ld_sel & ~dca_diag_wr_e) | mbi_run_local}}) |
  ({16{~(dca_diag_wr_e | cic_cpq_ld_sel | mbi_run_local)}} &
     {({8{~cid_st_addr[3]}} & cid_st_bmask[7:0]),({8{cid_st_addr[3]}} & cid_st_bmask[7:0])});
                                    
                                    
////////////////////////////////////////////////////////////////////////////////
// Valid Array Control
// The array is organized as 32x16.  Each line corresponds to one L2 cache line.
// (4 ways x 4 16B D$ lines per L2 line = 16)
// The valid array is read on every load instruction.
// The valid array is written on:
//  1 - a load fill sets one valid bit
//  2 - a diag write sets or clears one valid bit
//  3 - an invalidate caused by an L2 evicition clears up to four bits
//  4 - other invalidates clear one bit

assign dcc_dva_rvld_e = mbi_run_local ? mbi_dva_read_en : (dcache_read_e | asi_dta_diag_rd_e);
assign dcc_dva_wvld_e = mbi_run_local ? mbi_dva_write_en : (ld_fill_e | dta_diag_wr_e | cic_invalidate_e | cic_xinval_e);
// 0in bits_on -var {ld_fill_e,dta_diag_wr_e,cic_invalidate_e,cic_xinval_e} -max 1

// 0in bits_on -var {mbi_run_local,cic_l2fill_vld_e,cic_invalidate_e,cic_xinval_e} -max 1
assign dcc_dva_wr_addr_e[10:6] = mbi_run_local ? mbi_addr[4:0] :
                    (({5{cic_invalidate_e}} 			& cid_inv_index[10:6]) |
                     ({5{cic_xinval_e}} 			& xinv_index[10:6]) |
                     ({5{(cic_l2fill_vld_e | dta_diag_wr_e)}}	& dcc_dta_fill_addr_e[10:6]));
		
assign dcc_dva_din_e  = mbi_run_local ? mbi_wdata[1] : ((cic_cpq_ld_sel & ~dta_diag_wr_e) | (dta_diag_wr_e & st_data_w[1]));
assign dcc_dva_din2_e = mbi_run_local ? mbi_wdata[0] : ((cic_cpq_ld_sel & ~dta_diag_wr_e) | (dta_diag_wr_e & (st_data_w[1] ^ va_w[14])));

assign fill_bit_wen_e[0]  = ~lmd_fill_addr_e[5] & ~lmd_fill_addr_e[4] & ~lmd_fill_way_e[1] & ~lmd_fill_way_e[0];
assign fill_bit_wen_e[1]  = ~lmd_fill_addr_e[5] & ~lmd_fill_addr_e[4] & ~lmd_fill_way_e[1] &  lmd_fill_way_e[0];
assign fill_bit_wen_e[2]  = ~lmd_fill_addr_e[5] & ~lmd_fill_addr_e[4] &  lmd_fill_way_e[1] & ~lmd_fill_way_e[0];
assign fill_bit_wen_e[3]  = ~lmd_fill_addr_e[5] & ~lmd_fill_addr_e[4] &  lmd_fill_way_e[1] &  lmd_fill_way_e[0];
assign fill_bit_wen_e[4]  = ~lmd_fill_addr_e[5] &  lmd_fill_addr_e[4] & ~lmd_fill_way_e[1] & ~lmd_fill_way_e[0];
assign fill_bit_wen_e[5]  = ~lmd_fill_addr_e[5] &  lmd_fill_addr_e[4] & ~lmd_fill_way_e[1] &  lmd_fill_way_e[0];
assign fill_bit_wen_e[6]  = ~lmd_fill_addr_e[5] &  lmd_fill_addr_e[4] &  lmd_fill_way_e[1] & ~lmd_fill_way_e[0];
assign fill_bit_wen_e[7]  = ~lmd_fill_addr_e[5] &  lmd_fill_addr_e[4] &  lmd_fill_way_e[1] &  lmd_fill_way_e[0];
assign fill_bit_wen_e[8]  =  lmd_fill_addr_e[5] & ~lmd_fill_addr_e[4] & ~lmd_fill_way_e[1] & ~lmd_fill_way_e[0];
assign fill_bit_wen_e[9]  =  lmd_fill_addr_e[5] & ~lmd_fill_addr_e[4] & ~lmd_fill_way_e[1] &  lmd_fill_way_e[0];
assign fill_bit_wen_e[10] =  lmd_fill_addr_e[5] & ~lmd_fill_addr_e[4] &  lmd_fill_way_e[1] & ~lmd_fill_way_e[0];
assign fill_bit_wen_e[11] =  lmd_fill_addr_e[5] & ~lmd_fill_addr_e[4] &  lmd_fill_way_e[1] &  lmd_fill_way_e[0];
assign fill_bit_wen_e[12] =  lmd_fill_addr_e[5] &  lmd_fill_addr_e[4] & ~lmd_fill_way_e[1] & ~lmd_fill_way_e[0];
assign fill_bit_wen_e[13] =  lmd_fill_addr_e[5] &  lmd_fill_addr_e[4] & ~lmd_fill_way_e[1] &  lmd_fill_way_e[0];
assign fill_bit_wen_e[14] =  lmd_fill_addr_e[5] &  lmd_fill_addr_e[4] &  lmd_fill_way_e[1] & ~lmd_fill_way_e[0];
assign fill_bit_wen_e[15] =  lmd_fill_addr_e[5] &  lmd_fill_addr_e[4] &  lmd_fill_way_e[1] &  lmd_fill_way_e[0];

assign dcc_dva_bit_wen_e[15:0] =
		({16{mbi_run_local}}) | 
		({16{cic_invalidate_e}} 			& cic_inv_wen_e[15:0]) |
		({16{cic_xinval_e}} 				& xinval_bit_wen_e[15:0]) |
		({16{(cic_l2fill_vld_e | dta_diag_wr_e)}}	& fill_bit_wen_e[15:0]);

////////////////////////////////////////////////////////////////////////////////
// Regfile Data Control
////////////////////////////////////////////////////////////////////////////////

// Select the source of data to be passed to the register files.
// The same set of data always goes to both register files.
// [0] = load hit data from the dcache
// [1] = fill data from the CPX
// else bypass store buffer data

assign l2fill_vld_e = cic_l2fill_vld_e & ~lmc_l2_err_noup;

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_l2fill_m  (
	.scan_in(dff_l2fill_m_scanin),
	.scan_out(dff_l2fill_m_scanout),
	.din	(l2fill_vld_e),
	.dout	(l2fill_vld_m),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_l2fill_vld_m = l2fill_vld_m;

assign int_fill_or_byp_m = ((l2fill_vld_m & ~l2_perfmon_wb_cancel_m) | lmc_byp_vld_m) & ~lmd_fpld_m;
assign fp_fill_or_byp_m  = ((l2fill_vld_m & ~l2_perfmon_wb_cancel_m) | lmc_byp_vld_m) & lmd_fpld_m;

assign exu_ld_m = (ld_inst_vld_m & ~fpld_inst_m) | int_fill_or_byp_m;
assign fgu_fld_m = (ld_inst_vld_m & fpld_inst_m) | fp_fill_or_byp_m;

lsu_dcc_ctl_msff_ctl_macro__width_4 dff_l2fill_b  (
	.scan_in(dff_l2fill_b_scanin),
	.scan_out(dff_l2fill_b_scanout),
	.din	({int_fill_or_byp_m,fp_fill_or_byp_m,    exu_ld_m,    fgu_fld_m}),
	.dout	({int_fill_or_byp_b,fp_fill_or_byp_b,lsu_exu_ld_b,lsu_fgu_fld_b}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign fld_32b_m = ld_inst_vld_m ? fpld_32b_m : lmd_fp32b_m;
assign fld_odd32b_m = ld_inst_vld_m ? fpld_odd32b_m : lmd_fpodd32b_m;
assign fld_sxt_fsr_m = ld_inst_vld_m ? sxt_fsr_m : lmd_sxt_fsr_m;

assign return_rd_m[4:0] =  ld_inst_vld_m ? ld_rd_m[4:0] : lmd_rd_m[4:0];

assign lsu_exu_rd_m[4:0] =  ld_inst_vld_m ? ld_rd_inst_m[4:0] : lmd_rd_m[4:0];

assign ld_tid_m[2:0] = ({3{ld_inst_vld_m}} & tid_m[2:0]) |				// pipe
                       ({3{l2fill_vld_m}}  & lmc_cpq_tid_m[2:0]) |			// ld miss
                       ({3{lmc_byp_vld_m}} & lmc_byp_tid_m[2:0]);			// bypass

assign lsu_exu_tid_m[2:0] = ld_tid_m[2:0];

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_ld_tid_b  (
	.scan_in(dff_ld_tid_b_scanin),
	.scan_out(dff_ld_tid_b_scanout),
	.din	(ld_tid_m[2:0]),
	.dout	(ld_tid_b[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_dcc_ctl_msff_ctl_macro__width_8 dff_fp32_b  (
	.scan_in(dff_fp32_b_scanin),
	.scan_out(dff_fp32_b_scanout),
	.din	({fld_32b_m,fld_odd32b_m,fld_sxt_fsr_m,return_rd_m[4:0]}),
	.dout	({fld_32b_b,fld_odd32b_b,fld_sxt_fsr_b,return_rd_b[4:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_fgu_fld_32b_b = fld_32b_b;
assign lsu_fgu_fld_odd32b_b = fld_odd32b_b;
assign fsr_load_unqual_b = fld_sxt_fsr_b;

// Data is valid for the IRF/FRF when
// 1 - A load in the pipe hit the dcache.
// 2 - Data is returned from the CPX
// 3 - Data is bypassed from the LMQ bypass register (STB RAW, ASI, etc.)
assign ld_inst_qual_b = ld_inst_vld_b & ~sync_pipe & ~pipe_flush_b & ~dcc_any_exception_b;

assign exu_ld_vld_b = (ld_inst_qual_b & ~fpld_inst_b) |				// pipe
                      int_fill_or_byp_b;

assign fgu_fld_vld_b = (ld_inst_qual_b & fpld_inst_b) |				// pipe
                       fp_fill_or_byp_b;

lsu_dcc_ctl_msff_ctl_macro__width_2 dff_ld_vld_w  (
      .scan_in(dff_ld_vld_w_scanin),
      .scan_out(dff_ld_vld_w_scanout),
      .din    ({exu_ld_vld_b,fgu_fld_vld_b}),
      .dout   ({exu_ld_vld_w,fgu_fld_vld_w}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign lsu_exu_ld_vld_w = exu_ld_vld_w & ~(ld_inst_vld_w & flush_w);
assign lsu_fgu_fld_vld_w = fgu_fld_vld_w & ~(ld_inst_vld_w & flush_w);


assign lsu_fgu_fld_tid_b[2:0] = ld_tid_b[2:0];

assign lsu_fgu_fld_addr_b[4:0] = return_rd_b[4:0];

assign lsu_fgu_fsr_load_b = fsr_load_unqual_b & lsu_fgu_fld_b;

////////////////////////////////////////////////////////////////////////////////
// Big/little Endian
// Endianess is controlled by the following rules
// 1. Internal ASI's are all big endian.
// 2. Accesses with implicit ASI's are controlled by (PSTATE.CLE ^ TTE.IE)
// 3. Accesses with explicit ASI's are controlled by (ASI value ^ TTE.IE)

assign pstate_cle_d = tlu_pstate_cle[0] & thread0_d |
                      tlu_pstate_cle[1] & thread1_d |
                      tlu_pstate_cle[2] & thread2_d |
                      tlu_pstate_cle[3] & thread3_d |
                      tlu_pstate_cle[4] & thread4_d |
                      tlu_pstate_cle[5] & thread5_d |
                      tlu_pstate_cle[6] & thread6_d |
                      tlu_pstate_cle[7] & thread7_d;

assign dcc_lendian_pre_m = altspace_ldst_m ? lendian_asi_m : (pstate_cle_m & ~asi_internal_m);
assign dcc_bendian_byp_m = (~ld_inst_vld_m & lmd_bendian_m) | lmc_asi_bypass_m | dcc_asi_load_m;

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_le_bits  (
	.scan_in(dff_le_bits_scanin),
	.scan_out(dff_le_bits_scanout),
	.din	({pstate_cle_d,pstate_cle_e,pstate_cle_m}),
	.dout	({pstate_cle_e,pstate_cle_m,pstate_cle_b}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign l1hit_lendian_b = (ld_inst_vld_b | st_inst_vld_b) & ~asi_internal_b & 
                         ((~altspace_ldst_b & (pstate_cle_b ^  (tlb_tte_ie_b & tlb_tte_vld_b))) |
                          (altspace_ldst_b &  (lendian_asi_b ^ (tlb_tte_ie_b & tlb_tte_vld_b))));

// Insure that TTE.IE is never high for internal ASI's
// 0in custom -fire (st_inst_vld_b & asi_internal_b & tlb_tte_ie_b & ~flush_all_b) -message "TTE.IE high for internal ASI store"

////////////////////////////////////////////////////////////////////////////////
// Byte offset address

assign byp_baddr_m[2:0] = {lmd_ld_addr_m[2] ^ (oddrd_m & ~lmd_sz_m[0]), lmd_ld_addr_m[1:0]};

assign dcc_baddr_m[2:0] = ld_inst_vld_m ? lsu_va_m[2:0] : byp_baddr_m[2:0];

////////////////////////////////////////////////////////////////////////////////
// Alignment and sign extension for load return data.
// Integer data is aligned and sign-extended as defined in the Sparc V9
// architecture.  Floating point data is either 64bit (endian swapping may
// occur, but no other alignment is applicable) or 32bit (endian swapping may
// occur and the 32b data is replicated on the upper and lower halves of the
// 64b return bus).
//

// Return data (and it's size information) can come from
// 1. Load Hit (ldst_sz_m)
// 2. Load Miss
// 3. ASI bypass

assign dcc_ld_sz_m[1:0] = ld_inst_vld_m ? ldst_sz_mod_m[1:0] : lmd_sz_m[1:0];

assign dcc_signed_m = ld_inst_vld_m ? sxt_fsr_m : (lmd_sxt_fsr_m & ~lmc_asi_bypass_m);

////////////////////////////////////////////////////////////////////////////////
// ASI Decode

lsu_adc_ctl adc (
	.asi_e		(dcc_asi_e[7:0]),
	.asi_m		(dcc_asi_m[7:0]),
	.sr_inst_e	(dec_sr_inst_e),
	.pr_inst_e	(dec_pr_inst_e),
	.hpr_inst_e	(dec_hpr_inst_e),
	.altspace_ldst_e(altspace_e),
	.asi_legal_e	(asi_legal_e_unqual),
  .lsu_va_m(lsu_va_m[11:3]),
  .sr_inst_m(sr_inst_m),
  .pr_inst_m(pr_inst_m),
  .hpr_inst_m(hpr_inst_m),
  .altspace_ldst_m(altspace_ldst_m),
  .ld_inst_vld_m(ld_inst_vld_m),
  .legal_asi_va_m(legal_asi_va_m),
  .asr_legal_m(asr_legal_m),
  .asi_sync_m(asi_sync_m),
  .asi_internal_e(asi_internal_e),
  .asi_rngf_m(asi_rngf_m),
  .asi_indet_m(asi_indet_m),
  .lendian_asi_m(lendian_asi_m),
  .asi_sz_byte_m(asi_sz_byte_m),
  .asi_sz_hw_m(asi_sz_hw_m),
  .pst_asi_m(pst_asi_m),
  .asi_pst8_m(asi_pst8_m),
  .asi_pst16_m(asi_pst16_m),
  .asi_pst32_m(asi_pst32_m),
  .asi_read_only_m(asi_read_only_m),
  .asi_write_only_m(asi_write_only_m),
  .quad_asi_m(quad_asi_m),
  .binit_quad_asi_m(binit_quad_asi_m),
  .primary_asi_e(primary_asi_e),
  .secondary_asi_e(secondary_asi_e),
  .real_asi_e(real_asi_e),
  .as_if_user_asi_e(as_if_user_asi_e),
  .as_if_priv_asi_e(as_if_priv_asi_e),
  .atomic_asi_m(atomic_asi_m),
  .blk_asi_e(blk_asi_e),
  .nofault_asi_m(nofault_asi_m),
  .asi_iomap_m(asi_iomap_m),
  .asi_no_va_check_m(asi_no_va_check_m)
);

// Context selection.  Alternate instructions get their context from the ASI value.
// Non-alternates default to primary, unless TL>0, then it's nulceus.
assign tl_gt_0_d = (thread0_d & tl_gt_0[0]) |
                   (thread1_d & tl_gt_0[1]) |
                   (thread2_d & tl_gt_0[2]) |
                   (thread3_d & tl_gt_0[3]) |
                   (thread4_d & tl_gt_0[4]) |
                   (thread5_d & tl_gt_0[5]) |
                   (thread6_d & tl_gt_0[6]) |
                   (thread7_d & tl_gt_0[7]) ;

lsu_dcc_ctl_msff_ctl_macro__width_10 dff_tl_gt_0  (
	.scan_in(dff_tl_gt_0_scanin),
	.scan_out(dff_tl_gt_0_scanout),
	.din	({tlu_tl_gt_0[7:0],tl_gt_0_d,tl_gt_0_e}),
	.dout	({tl_gt_0[7:0],    tl_gt_0_e,tl_gt_0_m}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_dcc_ctl_msff_ctl_macro__width_5 dff_tlc  (
	.scan_in(dff_tlc_scanin),
	.scan_out(dff_tlc_scanout),
	.din	({tlc_wr_or_demap,
		  tlc_use_primary_context_c0,tlc_use_secondary_context_c0,
		  tlc_use_primary_context_c1,tlc_use_secondary_context_c1}),
	.dout	({wr_or_demap,
		  tlc_use_primary_context_c1,tlc_use_secondary_context_c1,
		  tlc_use_primary_context_c2,tlc_use_secondary_context_c2}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlc_use_secondary_context = tlc_use_secondary_context_c1 | tlc_use_secondary_context_c2;
assign tlc_use_primary_context   = tlc_use_primary_context_c1   | tlc_use_primary_context_c2;

assign dcc_ctxt_tid0_d[1:0] = tlc_wr_or_demap ? tld_tid[1:0] : dec_lsu_tid0_d[1:0];
assign dcc_ctxt_tid1_d[1:0] = tlc_wr_or_demap ? tld_tid[1:0] : dec_lsu_tid1_d[1:0];
assign dcc_ctxt_tg_d        = tlc_wr_or_demap ? tld_tid[2] : dec_lsu_tg_d;

assign dcc_pctxt_sel_e = wr_or_demap ? tlc_use_primary_context : (altspace_e ? primary_asi_e : ~tl_gt_0_e);
assign dcc_sctxt_sel_e = wr_or_demap ? tlc_use_secondary_context : (altspace_e & secondary_asi_e);

assign context_enc_e[1:0] = {(asi_internal_e | ~(dcc_pctxt_sel_e | dcc_sctxt_sel_e)),
                             (asi_internal_e | dcc_sctxt_sel_e)};

lsu_dcc_ctl_msff_ctl_macro__width_4 dff_ct  (
	.scan_in(dff_ct_scanin),
	.scan_out(dff_ct_scanout),
	.l1clk	(l1clk_pm1),
	.din	({context_enc_e[1:0],context_enc_m[1:0]}),
	.dout	({context_enc_m[1:0],context_enc_b[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// TLB translation controls
// 1. All except aiu/aip/real bypass in HPRIV ENB mode
// 2. All internal ASIs are non-translating
assign dcc_tlb_bypass = mbi_run_local ? ~bist_cam_en :
            ((hpstate_hpriv_e & ~(real_asi_e | as_if_user_asi_e | as_if_priv_asi_e)) |	// #1
            asi_internal_e);								// #2

// this is dont_care when bypassing
assign dcc_tlb_real = (~dmmu_enable_e & ~hpstate_hpriv_e) | real_asi_e;

lsu_dcc_ctl_msff_ctl_macro__width_12 dff_asi_m  (
	.scan_in(dff_asi_m_scanin),
	.scan_out(dff_asi_m_scanout),
	.l1clk	(l1clk_pm1),
	.din	({blk_asi_e,asi_internal_e,as_if_user_asi_e,asi_legal_e_unqual,asx_e[7:0]}),
	.dout	({blk_asi_m,asi_internal_m,as_if_user_asi_m,asi_legal_m_unqual,dcc_asi_m[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_legal_m = asi_legal_m_unqual & (ld_inst_vld_m | st_inst_vld_m);

// Don't make dcache diagnostics look like an internal ASI because they never go to
// the ASI ring and they don't sync the thread.
assign dcc_asi_load_m = asi_internal_m & ld_inst_vld_m;

assign asi_store_m = asi_internal_m & st_inst_vld_m;

lsu_dcc_ctl_msff_ctl_macro__width_24 dff_asi_b  (
	.scan_in(dff_asi_b_scanin),
	.scan_out(dff_asi_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({asi_internal_m, lendian_asi_m, asi_rngf_m, asi_sync_m, blk_asi_m, quad_asi_m, atomic_asi_m,
                  dcc_asi_load_m, asi_store_m, asi_iomap_m,     asi_indet_m,     binit_quad_asi_m, pst_asi_m,
                  nofault_asi_m, quad_ld_m,     dcc_asi_m[7:0], asi_legal_m}),
	.dout	({asi_internal_b, lendian_asi_b, asi_rngf_b, asi_sync_b, blk_asi_b, quad_asi_b, atomic_asi_b,
                  dcc_asi_load_b, asi_store_b, dcc_asi_iomap_b, asi_indet_b,     binit_quad_asi_b, pst_asi_b,
                  nofault_asi_b, quad_ldd_b,    dcc_asi_b[7:0], asi_legal_b}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_asi_store_b = asi_store_b;
assign dcc_binit_st_b = binit_quad_asi_b & st_inst_vld_b;
assign dcc_pst_asi_b = pst_asi_b;
assign dcc_asi_indet_b = asi_indet_b;

// Used in store buffer.  For ASI_ITLB_DATA_ACCESS (ASI=0x55), writes need to go to the
// fast ring but reads to the local ring.  Take care of that special case here.
assign dcc_asi_rngf_b = asi_rngf_b | (st_inst_vld_b & asi_internal_b & (dcc_asi_b[7:0] == 8'h55));

// ASI comes from Rd for wsr, wpr, and whpr.
assign asi_use_rd_e = (dec_sr_inst_e | dec_pr_inst_e | dec_hpr_inst_e) & dec_st_inst_e;
// ASI comes from sraddr for rsr, rpr, and rhpr.
assign asi_use_sr_e = (dec_sr_inst_e | dec_pr_inst_e | dec_hpr_inst_e) & ld_inst_unqual_e;

assign quad_ld_m = ld_inst_vld_m & ldst_dbl_m & quad_asi_m & ~fpldst_inst_vld_m;

assign dcc_stb_quad_ld_cam = quad_ld_m & ~mbi_run_local;

////////////////////////////////////////////////////////////////////////////////
// ASI and state register control

assign dcc_tlb_rd_e      = mbi_run_local ? bist_dtb_read_en :
            (ld_inst_unqual_e & altspace_e & ((dcc_asi_e[7:0] == 8'h5D) | (dcc_asi_e[7:0] == 8'h5E)));
assign stb_diag_rd_e     = dec_ld_inst_e & ~dec_pref_inst_e & ~dec_st_inst_e & altspace_e & (dcc_asi_e[7:0] == 8'h4A);

assign asi_dca_diag_e    = altspace_e & (dcc_asi_e[7:0] == 8'h46);
assign asi_dta_diag_e    = altspace_e & (dcc_asi_e[7:0] == 8'h47);

assign asi_dca_diag_rd_e = dec_ld_inst_e & ~dec_pref_inst_e & asi_dca_diag_e;
assign asi_dta_diag_rd_e = dec_ld_inst_e & ~dec_pref_inst_e & asi_dta_diag_e;

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_int_asi_m  (
	.scan_in(dff_int_asi_m_scanin),
	.scan_out(dff_int_asi_m_scanout),
	.l1clk	(l1clk_pm1),
	.din	({stb_diag_rd_e,    asi_dca_diag_e,asi_dta_diag_e}),
	.dout	({dcc_stb_diag_rd_m,asi_dca_diag_m,asi_dta_diag_m}),
  .siclk(siclk),
  .soclk(soclk)
);
assign asi_dca_diag_rd_m = ld_inst_vld_m & ~pref_inst_m & asi_dca_diag_m;
assign asi_dta_diag_rd_m = ld_inst_vld_m & ~pref_inst_m & asi_dta_diag_m;

assign asi_cache_diag_wr_m = st_inst_vld_m & ~atomic_m & (asi_dca_diag_m | asi_dta_diag_m);
assign dcc_cache_diag_wr_m = asi_cache_diag_wr_m | lbist_run;

assign dcc_p0ctxt_rd_m      = ld_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h21) & ~lsu_va_m[8] & lsu_va_m[3];
assign dcc_p1ctxt_rd_m      = ld_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h21) &  lsu_va_m[8] & lsu_va_m[3];
assign dcc_s0ctxt_rd_m      = ld_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h21) & ~lsu_va_m[8] & lsu_va_m[4];
assign dcc_s1ctxt_rd_m      = ld_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h21) &  lsu_va_m[8] & lsu_va_m[4];
assign dcc_pid_rd_m         = ld_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h58) &  lsu_va_m[7];
assign dcc_wtchpt_rd_m      = ld_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h58) & (lsu_va_m[5] & lsu_va_m[4] & lsu_va_m[3]);
assign     tlb_tag_read_m   = ld_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h5E);
assign     tlb_data_read_m  = ld_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h5D);
assign asi_dcd_diag_rd_m    = asi_dca_diag_rd_m & lsu_va_m[13];

// This signal gates the flop for tag/valid read data.  It must be active during BIST also.
assign dcc_rd_dt_diag_m = asi_dta_diag_rd_m | mbi_run_local;

// These are ASI's for which no ring transaction should be generated.
assign lsu_asi_rd_m = dcc_p0ctxt_rd_m | dcc_p1ctxt_rd_m   | dcc_s0ctxt_rd_m | dcc_s1ctxt_rd_m | dcc_pid_rd_m | 
                      dcc_wtchpt_rd_m | dcc_stb_diag_rd_m | asi_dca_diag_rd_m;

assign dcc_wtchpt_sel_m = dcc_wtchpt_rd_m;

lsu_dcc_ctl_msff_ctl_macro__width_10 dff_int_asi_b  (
	.scan_in(dff_int_asi_b_scanin),
	.scan_out(dff_int_asi_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({lsu_asi_rd_m,        dcc_wtchpt_rd_m,    asi_dca_diag_rd_m, 
		  dcc_stb_diag_rd_m,   asi_dcd_diag_rd_m,  asi_dta_diag_rd_m, wr_error_inj_m,
		  asi_cache_diag_wr_m, tlb_tag_read_m,     tlb_data_read_m }),
	.dout	({lsu_asi_rd_b,        dcc_wtchpt_rd_b,    asi_dca_diag_rd_b, 
		  stb_diag_rd_b,       asi_dcd_diag_rd_b,  dcc_rd_dt_diag_b,  wr_error_inj_b,
		  asi_cache_diag_wr_b, dcc_tlb_tag_read_b, dcc_tlb_data_read_b }),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_cache_diag_wr_b = asi_cache_diag_wr_b;

lsu_dcc_ctl_msff_ctl_macro__width_4 dff_int_asi_w  (
	.scan_in(dff_int_asi_w_scanin),
	.scan_out(dff_int_asi_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({lsu_asi_sel_b,stb_diag_rd_b,asi_cache_diag_wr_b,dcc_asi_b[0]}),
	.dout	({lsu_asi_sel_w,stb_diag_rd_w,asi_cache_diag_wr_w,asi_dta_not_dca_diag_w}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dca_diag_wr_e = asi_cache_diag_wr_w & ~asi_dta_not_dca_diag_w & ~flush_w & ~mbi_run_local;
assign dta_diag_wr_e = asi_cache_diag_wr_w & asi_dta_not_dca_diag_w & ~flush_w & ~mbi_run_local;
assign diag_write_e  = asi_cache_diag_wr_w & ~mbi_run_local;

// dcc_lsu_asi_sel_w is used to enable the loading of the bypass mux
assign lsu_asi_sel_b = dcc_lsu_asi_rd_b & ~(stb_diag_rd_b | asi_dcd_diag_rd_b);
assign dcc_lsu_asi_sel_w = lsu_asi_sel_w;

assign dcc_rd_diag_dca_b = asi_dca_diag_rd_b;

assign dcc_rd_lsu_ctl_reg_b = ld_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h45) & ~|(lsu_va_b[4:3]);
assign dcc_rd_intr_id_b     = ld_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h63) & ~lsu_va_b[4];
assign dcc_rd_core_id_b     = ld_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h63) &  lsu_va_b[4];
assign dcc_rd_diag_reg_b    = ld_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h42) &  lsu_va_b[4];
assign dcc_rd_error_inj_b   = ld_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h43);
assign dcc_rd_pwr_mgmt_b    = ld_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h4E);

assign dcc_tlb_tag0_read_b = dcc_tlb_tag_read_b & ~lsu_va_b[10];
assign dcc_tlb_tag1_read_b = dcc_tlb_tag_read_b &  lsu_va_b[10];

// ASI reads are muxed in two levels.  This controls the mux that selects among the sources
// on the right hand side of the LSU.  (DTAG, DTLB_DATA, DTLB_TAG, etc.)
assign dcc_rd_rhs_asi_b = dcc_rd_dt_diag_b | dcc_tlb_tag_read_b | dcc_tlb_data_read_b;

// dcc_lsu_asi_rd_b is used to block the load from going out on the ASI ring
assign dcc_lsu_asi_rd_b = lsu_asi_rd_b | dcc_rd_lsu_ctl_reg_b | dcc_rd_intr_id_b | 
                          dcc_rd_core_id_b | dcc_rd_diag_reg_b | dcc_rd_dt_diag_b |
                          dcc_rd_diag_dca_b | dcc_tlb_tag_read_b | dcc_tlb_data_read_b |
                          dcc_rd_error_inj_b | dcc_rd_pwr_mgmt_b;

assign wr_error_inj_m    = st_inst_vld_m & altspace_ldst_m & (dcc_asi_m[7:0] == 8'h43);

assign dcc_wr_error_inj_m = wr_error_inj_m;

// Need this to copy the address to the store data
assign dcc_demap_asi_m   = st_inst_vld_m & altspace_ldst_m & ((dcc_asi_m[7:0] == 8'h57) | (dcc_asi_m[7:0] == 8'h5f));

assign asi_wtchpt_wr_b   = st_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h58) & (lsu_va_b[5] & lsu_va_b[4] & lsu_va_b[3]);
assign asi_ctl_reg_wr_b  = st_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h45) & ~|(lsu_va_b[4:3]);
assign asi_diag_reg_wr_b = st_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h42) & lsu_va_b[4];
assign asi_wr_pwr_mgmt_b = st_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h4E);
assign asi_ceter_wr_b    = st_inst_vld_b & altspace_ldst_b & (dcc_asi_b[7:0] == 8'h4C) & (~lsu_va_b[5] & lsu_va_b[4] & lsu_va_b[3]);

lsu_dcc_ctl_msff_ctl_macro__width_8 dff_wr_state_w  (
	.scan_in(dff_wr_state_w_scanin),
	.scan_out(dff_wr_state_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({asi_wtchpt_wr_b,asi_ctl_reg_wr_b,asi_diag_reg_wr_b,sbd_st_data_b[1:0],
		  asi_wr_pwr_mgmt_b,wr_error_inj_b,asi_ceter_wr_b}),
	.dout	({asi_wtchpt_wr_w,asi_ctl_reg_wr_w,asi_diag_reg_wr_w,st_data_w[1:0],    
		  asi_wr_pwr_mgmt_w,wr_error_inj_w,asi_ceter_wr_w}),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_dcc_ctl_msff_ctl_macro__width_6 dff_tlu_asi  (
	.scan_in(dff_tlu_asi_scanin),
	.scan_out(dff_tlu_asi_scanout),
	.din	({tlu_asi_0_valid,   tlu_asi_1_valid,   tlu_asi_0_tid[1:0],   tlu_asi_1_tid[1:0]}),
	.dout	({reload_asi_0_valid,reload_asi_1_valid,reload_asi_0_tid[1:0],reload_asi_1_tid[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_asi_reload_sel[0] = ~reload_asi_0_tid[1] & ~reload_asi_0_tid[0] & reload_asi_0_valid;
assign dcc_asi_reload_sel[1] = ~reload_asi_0_tid[1] &  reload_asi_0_tid[0] & reload_asi_0_valid;
assign dcc_asi_reload_sel[2] =  reload_asi_0_tid[1] & ~reload_asi_0_tid[0] & reload_asi_0_valid;
assign dcc_asi_reload_sel[3] =  reload_asi_0_tid[1] &  reload_asi_0_tid[0] & reload_asi_0_valid;
assign dcc_asi_reload_sel[4] = ~reload_asi_1_tid[1] & ~reload_asi_1_tid[0] & reload_asi_1_valid;
assign dcc_asi_reload_sel[5] = ~reload_asi_1_tid[1] &  reload_asi_1_tid[0] & reload_asi_1_valid;
assign dcc_asi_reload_sel[6] =  reload_asi_1_tid[1] & ~reload_asi_1_tid[0] & reload_asi_1_valid;
assign dcc_asi_reload_sel[7] =  reload_asi_1_tid[1] &  reload_asi_1_tid[0] & reload_asi_1_valid;

assign dcc_wr_wtchpt[0] = asi_wtchpt_wr_w & thread_w[0] & ~flush_w;
assign dcc_wr_wtchpt[1] = asi_wtchpt_wr_w & thread_w[1] & ~flush_w;
assign dcc_wr_wtchpt[2] = asi_wtchpt_wr_w & thread_w[2] & ~flush_w;
assign dcc_wr_wtchpt[3] = asi_wtchpt_wr_w & thread_w[3] & ~flush_w;
assign dcc_wr_wtchpt[4] = asi_wtchpt_wr_w & thread_w[4] & ~flush_w;
assign dcc_wr_wtchpt[5] = asi_wtchpt_wr_w & thread_w[5] & ~flush_w;
assign dcc_wr_wtchpt[6] = asi_wtchpt_wr_w & thread_w[6] & ~flush_w;
assign dcc_wr_wtchpt[7] = asi_wtchpt_wr_w & thread_w[7] & ~flush_w;

assign dcc_wr_lsu_ctl_reg[0] = (asi_ctl_reg_wr_w & thread_w[0] & ~flush_w) | ~tlu_lsu_clear_ctl_reg_[0];
assign dcc_wr_lsu_ctl_reg[1] = (asi_ctl_reg_wr_w & thread_w[1] & ~flush_w) | ~tlu_lsu_clear_ctl_reg_[1];
assign dcc_wr_lsu_ctl_reg[2] = (asi_ctl_reg_wr_w & thread_w[2] & ~flush_w) | ~tlu_lsu_clear_ctl_reg_[2];
assign dcc_wr_lsu_ctl_reg[3] = (asi_ctl_reg_wr_w & thread_w[3] & ~flush_w) | ~tlu_lsu_clear_ctl_reg_[3];
assign dcc_wr_lsu_ctl_reg[4] = (asi_ctl_reg_wr_w & thread_w[4] & ~flush_w) | ~tlu_lsu_clear_ctl_reg_[4];
assign dcc_wr_lsu_ctl_reg[5] = (asi_ctl_reg_wr_w & thread_w[5] & ~flush_w) | ~tlu_lsu_clear_ctl_reg_[5];
assign dcc_wr_lsu_ctl_reg[6] = (asi_ctl_reg_wr_w & thread_w[6] & ~flush_w) | ~tlu_lsu_clear_ctl_reg_[6];
assign dcc_wr_lsu_ctl_reg[7] = (asi_ctl_reg_wr_w & thread_w[7] & ~flush_w) | ~tlu_lsu_clear_ctl_reg_[7];

assign dcc_wr_pwr_mgmt    = asi_wr_pwr_mgmt_w & ~flush_w;
assign dcc_wr_error_inj_w = wr_error_inj_w & ~flush_w;
assign dcc_ceter_wr_w     = asi_ceter_wr_w & ~flush_w;

assign stb_diag_rd_w_qual = stb_diag_rd_w & ~flush_w & ~mbi_run_local;

assign stb_ptr_rd_w2  = (stb_diag_rd_w2 &  va_w2[8]) & ~mbi_run_local;
assign stb_data_rd_w2 = (stb_diag_rd_w2 & ~va_w2[8] & ~va_w2[7] & ~va_w2[6]) |
                        (mbi_run_local & bist_srm_rd_1 & ~bist_cmpsel_1[1] & ~bist_cmpsel_1[0]);
assign stb_ecc_rd_w2  = (stb_diag_rd_w2 & ~va_w2[8] & ~va_w2[7] &  va_w2[6]) |
                        (mbi_run_local & bist_srm_rd_1 & ~bist_cmpsel_1[1] &  bist_cmpsel_1[0]);
assign stb_ctl_rd_w2  = (stb_diag_rd_w2 & ~va_w2[8] &  va_w2[7] & ~va_w2[6]) |
                        (mbi_run_local & bist_srm_rd_1 &  bist_cmpsel_1[1] & ~bist_cmpsel_1[0]);
assign stb_addr_rd_w2 = (stb_diag_rd_w2 & ~va_w2[8] &  va_w2[7] &  va_w2[6]) | 
                        (mbi_run_local & bist_scm_rd_1);

lsu_dcc_ctl_msff_ctl_macro__width_13 dff_stb_w3  (
	.scan_in(dff_stb_w3_scanin),
	.scan_out(dff_stb_w3_scanout),
	.din	({stb_diag_rd_w_qual,va_w[10:4], stb_data_rd_w2,stb_ecc_rd_w2,stb_ctl_rd_w2,stb_ptr_rd_w2,stb_addr_rd_w2}),
	.dout	({stb_diag_rd_w2,    va_w2[10:4],stb_data_rd_w3,stb_ecc_rd_w3,stb_ctl_rd_w3,stb_ptr_rd_w3,stb_addr_rd_w3}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_stb_ptr_rd_w3   = stb_ptr_rd_w3;
assign dcc_stb_data_rd_w3  = stb_data_rd_w3;
assign dcc_stb_ecc_rd_w3   = stb_ecc_rd_w3;
assign dcc_stb_ctl_rd_w3   = stb_ctl_rd_w3;
assign dcc_stb_addr_sel_w3 = stb_addr_rd_w3;

// dcc_stb_diag_sel_w3 loads the bypass mux
assign dcc_stb_diag_sel_w3 = stb_ptr_rd_w3 | stb_data_rd_w3 | stb_ecc_rd_w3 | stb_ctl_rd_w3 | stb_addr_rd_w3;

// ASI_LSU_DIAG_REG is just two bits and not threaded, so keep it here.
assign diag_reg_in[1:0] = (asi_diag_reg_wr_w & ~flush_w) ? st_data_w[1:0] : diag_reg[1:0] ;

lsu_dcc_ctl_msff_ctl_macro__width_2 dff_diag_reg  (
	.scan_in(dff_diag_reg_scanin),
	.scan_out(dff_diag_reg_scanout),
	.l1clk	(l1clk_pm1),
	.din	(diag_reg_in[1:0]),
	.dout	(diag_reg[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_ifu_direct_map = diag_reg[0];
assign dcc_direct_map = diag_reg[1] | asi_cache_diag_wr_b;

////////////////////////////////////////////////////////////////////////////////
// Replacement way for load miss.
////////////////////////////////////////////////////////////////////////////////

assign way_hit_enc[0] = tlb_cache_way_hit_b[1] | tlb_cache_way_hit_b[3];
assign way_hit_enc[1] = tlb_cache_way_hit_b[2] | tlb_cache_way_hit_b[3];

// Replacement way is from one of the following sources
// (1) The way with the error in case of D$ error
// (2) The way hit in the dcache in the case of a partial raw.
// (3) Bits 12:11 of the VA in direct mapped mode.
// (4) LRU replacement in all other cases
 
assign ld_way_b[1:0] =             dcc_perror_b ? way_err_enc[1:0] :	// (1)
              (tlb_cache_hit_b & ld_inst_vld_b) ? way_hit_enc[1:0] :  	// (2)
		                 dcc_direct_map ? lsu_va_b[12:11] :  	// (3)
		                                  rway[1:0];	     	// (4)
                        
//////////////////////////////////////////////////////////////
// LRU replacement.  Use the matrix method for LRU calculation.
//
//   3|               When line is used, set row to all 1's and
//   2|         [5]   set column to all 0's
//   1|     [3] [4]
//   0| [0] [1] [2]   LRU way is the one with all 0's in   
//    -------------   its row and all 1's in it's column
//   0   1   2   3 

// State data from LRU array
assign lru_line_sel[0] = mbi_run_local ? (~bist_addr_1[6] & ~bist_addr_1[5]) : (~lsu_va_m[5] & ~lsu_va_m[4]);
assign lru_line_sel[1] = mbi_run_local ? (~bist_addr_1[6] &  bist_addr_1[5]) : (~lsu_va_m[5] &  lsu_va_m[4]);
assign lru_line_sel[2] = mbi_run_local ? ( bist_addr_1[6] & ~bist_addr_1[5]) : ( lsu_va_m[5] & ~lsu_va_m[4]);
assign lru_line_sel[3] = mbi_run_local ? ( bist_addr_1[6] &  bist_addr_1[5]) : ( lsu_va_m[5] &  lsu_va_m[4]);

assign lru_rd_data_m[5:0] = ({6{lru_line_sel[3]}} & lru_rdata_m[23:18]) |
                            ({6{lru_line_sel[2]}} & lru_rdata_m[17:12]) |
                            ({6{lru_line_sel[1]}} & lru_rdata_m[11:6]) |
                            ({6{lru_line_sel[0]}} & lru_rdata_m[5:0]) ;

assign bypass_from_w2 = (lsu_va_m[10:4] ==     va_w2[10:4]) & ld_inst_vld_w2 & ~mbi_run_local;
assign bypass_from_w  = (lsu_va_m[10:4] ==     va_w[10:4])  & ld_inst_vld_w  & ~mbi_run_local;
assign bypass_from_b  = (lsu_va_m[10:4] == lsu_va_b[10:4])  & ld_inst_vld_b  & ~mbi_run_local;

assign lru_state_in_m[5:0] =
 bypass_from_b ? new_lru_state_b[5:0] : 
                 (bypass_from_w ? lru_state_w[5:0] :
                                  (bypass_from_w2 ? lru_state_w2[5:0] : lru_rd_data_m[5:0])
                 );

lsu_dcc_ctl_msff_ctl_macro__width_6 dff_lru_data_b  (
	.scan_in(dff_lru_data_b_scanin),
	.scan_out(dff_lru_data_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(lru_state_in_m[5:0]),
	.dout	(lru_state_in_b[5:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// If this was bypassed from W and that load missed the cache and was a full RAW, we
// don't want to use the modified state since the cache is unchanged.

assign lru_state_b[5:0] = lru_state_in_b[5:0];

// This is the logic that takes the lru state and "hit" way and generates the LRU way
// and the new lru state
assign lru_way[0] = ~(lru_state_b[0] | lru_state_b[1] | lru_state_b[2]);
assign lru_way[1] = ~(lru_state_b[3] | lru_state_b[4]) & lru_state_b[0];
assign lru_way[2] = ~lru_state_b[5] & lru_state_b[1] & lru_state_b[3];
assign lru_way[3] = lru_state_b[2] & lru_state_b[4] & lru_state_b[5];

assign rway[0] = lru_way[1] | lru_way[3];
assign rway[1] = lru_way[2] | lru_way[3];

assign ldhit_b = ld_inst_vld_b & (tlb_cache_hit_b & dcache_enable_b);
assign used_way[3:0] = ldhit_b ? tlb_cache_way_hit_b[3:0] : lru_way[3:0];

assign new_lru_state_b[0] = (lru_state_b[0] & ~used_way[1]) | used_way[0];
assign new_lru_state_b[1] = (lru_state_b[1] & ~used_way[2]) | used_way[0];
assign new_lru_state_b[2] = (lru_state_b[2] & ~used_way[3]) | used_way[0];
assign new_lru_state_b[3] = (lru_state_b[3] & ~used_way[2]) | used_way[1];
assign new_lru_state_b[4] = (lru_state_b[4] & ~used_way[3]) | used_way[1];
assign new_lru_state_b[5] = (lru_state_b[5] & ~used_way[3]) | used_way[2];


lsu_dcc_ctl_msff_ctl_macro__width_13 dff_new_lru_w  (
	.scan_in(dff_new_lru_w_scanin),
	.scan_out(dff_new_lru_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({new_lru_state_b[5:0],lru_state_b[5:0],    ld_inst_vld_b}),
	.dout	({new_lru_state_w[5:0],old_lru_state_w[5:0],ld_inst_vld_w}),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_dcc_ctl_msff_ctl_macro__width_7 dff_new_lru_w2  (
	.scan_in(dff_new_lru_w2_scanin),
	.scan_out(dff_new_lru_w2_scanout),
	.din	({lru_state_w[5:0], ld_inst_vld_w}),
	.dout	({lru_state_w2[5:0],ld_inst_vld_w2}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// LRU state should not be updated on full RAWs which miss the cache or non-cacheable loads
// The full RAW timing is too critical to use in B, so it gets factored in in W.

assign update_lru_noraw_b = ld_inst_vld_b & ~ncache_rq_b;
assign update_lru_raw_b = ld_inst_vld_b & ~ncache_rq_b & tlb_cache_hit_b;

lsu_dcc_ctl_msff_ctl_macro__width_20 dff_update_lru  (
	.scan_in(dff_update_lru_scanin),
	.scan_out(dff_update_lru_scanout),
	.l1clk	(l1clk_pm1),
	.din	({update_lru_noraw_b,update_lru_raw_b,lsu_va_b[20:3]}),
	.dout	({update_lru_noraw_w,update_lru_raw_w,va_w[20:3]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_va_w[12:3] = va_w[12:3];

assign dcc_lru_wr_addr_w[10:6] = mbi_run_local ? mbi_addr[4:0] : va_w[10:6];

assign dcc_lru_rvld_e = mbi_run_local ? mbi_lru_read_en : dcache_read_e; 
assign lru_new_state = (lmc_full_raw_w ? update_lru_raw_w : update_lru_noraw_w) & ~flush_w;
assign dcc_lru_wvld_w = mbi_run_local ? mbi_lru_write_en : lru_new_state;

assign lru_state_w[5:0] = lru_new_state ? new_lru_state_w[5:0] : old_lru_state_w[5:0];

assign dcc_lru_wdata_w[5:0] = mbi_run_local ? mbi_wdata[5:0] : new_lru_state_w[5:0];

assign dcc_lru_wen_w[0] = mbi_run_local ? (~mbi_addr[6] & ~mbi_addr[5]) : (~va_w[5] & ~va_w[4]);
assign dcc_lru_wen_w[1] = mbi_run_local ? (~mbi_addr[6] &  mbi_addr[5]) : (~va_w[5] &  va_w[4]);
assign dcc_lru_wen_w[2] = mbi_run_local ? ( mbi_addr[6] & ~mbi_addr[5]) : ( va_w[5] & ~va_w[4]);
assign dcc_lru_wen_w[3] = mbi_run_local ? ( mbi_addr[6] &  mbi_addr[5]) : ( va_w[5] &  va_w[4]);


////////////////////////////////////////////////////////////////////////////////
// LMQ packet formating
////////////////////////////////////////////////////////////////////////////////

// Second packet of CAS uses load packet port.  Otherwise it's a normal load.
assign ld_rq_type[2:0] = atomic_b ? 3'b011 : 3'b000;

// Non-cacheable requests (all will sync the thread and initiate a pcx request)
assign ncache_rq_b =
  (tlb_tte_vld_b & ~tlb_tte_cp_b) |	// page has CP=0
  (tlb_tte_vld_b & tlb_tte_ie_b) |	// page has IE=1
  atomic_b |				// cas,ldstub,swap
  pgnum_b39_qual |			// IO access
  ldst_dbl_b & (~fpld_inst_b | (altspace_ldst_b & blk_asi_b)) |	// LDD and blk-ld
  dcc_asi_load_b |			// internal ASI loads do not allocate
  pref_inst_b |				// Prefetch does not allocate in the L1 caches
  ~dcache_enable_b;			// all loads are NC when D$ disabled

assign dcc_ncache_b = ncache_rq_b;
			
// The way should not matter for CAS since it's non-cacheable
//assign ld_pkt_way_b[1:0] = casa_inst_b ? 2'b00 : ld_way_b[1:0];
assign ld_pkt_way_b[1:0] = ld_way_b[1:0];

assign mem_ld_miss_ctl[60:40] = {
  1'b0,
  fld_odd32b_b,
  fld_32b_b,
  fpld_inst_b,
  fld_sxt_fsr_b,
  ~l1hit_lendian_b,
  ld_rd_b[4:0],
  (ldst_dbl_b & (~fpld_inst_b | (altspace_ldst_b & blk_asi_b))) | pref_ice_b,
  ldst_sz_b[1],ldst_sz_b0_b,
  ld_rq_type[2:0],
  ncache_rq_b,
  pref_inst_b,
  ld_pkt_way_b[1:0]
};
assign dcc_ld_miss_ldd = mem_ld_miss_ctl[49] & ~pref_ice_b;

assign asi_ld_miss_ctl[60:40] = {
  1'b1,
  3'b000,
  asi_indet_b,
  asi_rngf_b,
  ld_rd_b[4:0],
  asi_type_b[1:0],
  dcc_asi_b[7:0]
};

assign dcc_ld_miss_ctl[60:40] = (dcc_asi_load_b & ~dcc_asi_iomap_b) ? asi_ld_miss_ctl[60:40] : mem_ld_miss_ctl[60:40];

////////////////////////////////////////////////////////////////////////////////
// Signal sync instructions (flush/membar/stbar) to the store buffers
////////////////////////////////////////////////////////////////////////////////

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_sync_inst_w  (
	.scan_in(dff_sync_inst_w_scanin),
	.scan_out(dff_sync_inst_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	(sync_inst_b),
	.dout	(sync_inst_w),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_sync_inst_w[0] = sync_inst_w & thread_w[0] & ~flush_w;
assign dcc_sync_inst_w[1] = sync_inst_w & thread_w[1] & ~flush_w;
assign dcc_sync_inst_w[2] = sync_inst_w & thread_w[2] & ~flush_w;
assign dcc_sync_inst_w[3] = sync_inst_w & thread_w[3] & ~flush_w;
assign dcc_sync_inst_w[4] = sync_inst_w & thread_w[4] & ~flush_w;
assign dcc_sync_inst_w[5] = sync_inst_w & thread_w[5] & ~flush_w;
assign dcc_sync_inst_w[6] = sync_inst_w & thread_w[6] & ~flush_w;
assign dcc_sync_inst_w[7] = sync_inst_w & thread_w[7] & ~flush_w;

////////////////////////////////////////////////////////////////////////////////

// Encode store request types
assign st_rq_type_b[1] = (atomic_b & ~casa_inst_b) | asi_type_b[1];
assign st_rq_type_b[0] = atomic_b | asi_type_b[0];

lsu_dcc_ctl_msff_ctl_macro__width_3 dff_st_type_w  (
	.scan_in(dff_st_type_w_scanin),
	.scan_out(dff_st_type_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({st_rq_type_b[1:0],    st_inst_vld_b}),
	.dout	({dcc_st_rq_type_w[1:0],st_inst_vld_w}),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Parity generation
////////////////////////////////////////////////////////////////////////////////

// Parity invert.  Parity can be inverted by diagnostic accesses.
// UE/ND errors from L2 also cause an error to be injected
// NOTE : lmc_l2_uerr will not assert when dca_diag_wr_e is high
// 0in bits_on -var {lmc_l2_uerr,dca_diag_wr_e} -max 1 

assign dcc_parity_invert[7:0] = (va_w[20:13] & {8{dca_diag_wr_e}}) | {8{(cic_cpq_ld_sel & lmc_l2_uerr)}};

assign dcc_dta_parity = mbi_run_local ? mbi_wdata[5] : ((dta_diag_wr_e & va_w[13]) ^ lmd_wrtag_parity_e);

////////////////////////////////////////////////////////////////////////////////
// Exceptions (listed in order of priority)
////////////////////////////////////////////////////////////////////////////////

// mux in the privilege status
assign pstate_priv_d = (thread0_d & tlu_lsu_pstate_priv[0]) |
                       (thread1_d & tlu_lsu_pstate_priv[1]) |
                       (thread2_d & tlu_lsu_pstate_priv[2]) |
                       (thread3_d & tlu_lsu_pstate_priv[3]) |
                       (thread4_d & tlu_lsu_pstate_priv[4]) |
                       (thread5_d & tlu_lsu_pstate_priv[5]) |
                       (thread6_d & tlu_lsu_pstate_priv[6]) |
                       (thread7_d & tlu_lsu_pstate_priv[7]) ;

assign hpstate_hpriv_d = (thread0_d & tlu_lsu_hpstate_hpriv[0]) |
                         (thread1_d & tlu_lsu_hpstate_hpriv[1]) |
                         (thread2_d & tlu_lsu_hpstate_hpriv[2]) |
                         (thread3_d & tlu_lsu_hpstate_hpriv[3]) |
                         (thread4_d & tlu_lsu_hpstate_hpriv[4]) |
                         (thread5_d & tlu_lsu_hpstate_hpriv[5]) |
                         (thread6_d & tlu_lsu_hpstate_hpriv[6]) |
                         (thread7_d & tlu_lsu_hpstate_hpriv[7]) ;

lsu_dcc_ctl_msff_ctl_macro__width_2 dff_priv_state_e  (
	.scan_in(dff_priv_state_e_scanin),
	.scan_out(dff_priv_state_e_scanout),
	.l1clk	(l1clk),
	.din	({pstate_priv_d,hpstate_hpriv_d}),
	.dout	({pstate_priv_e,hpstate_hpriv_e}),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_dcc_ctl_msff_ctl_macro__width_2 dff_priv_state_m  (
	.scan_in(dff_priv_state_m_scanin),
	.scan_out(dff_priv_state_m_scanout),
	.l1clk	(l1clk_pm1),
	.din	({pstate_priv_e,hpstate_hpriv_e}),
	.dout	({pstate_priv_m,hpstate_hpriv_m}),
  .siclk(siclk),
  .soclk(soclk)
);

assign bst_priv_m = ((sbc_tid_m[2:0] == 3'd0) & tlu_lsu_pstate_priv[0]) |
                    ((sbc_tid_m[2:0] == 3'd1) & tlu_lsu_pstate_priv[1]) |
                    ((sbc_tid_m[2:0] == 3'd2) & tlu_lsu_pstate_priv[2]) |
                    ((sbc_tid_m[2:0] == 3'd3) & tlu_lsu_pstate_priv[3]) |
                    ((sbc_tid_m[2:0] == 3'd4) & tlu_lsu_pstate_priv[4]) |
                    ((sbc_tid_m[2:0] == 3'd5) & tlu_lsu_pstate_priv[5]) |
                    ((sbc_tid_m[2:0] == 3'd6) & tlu_lsu_pstate_priv[6]) |
                    ((sbc_tid_m[2:0] == 3'd7) & tlu_lsu_pstate_priv[7]) ;

assign bst_hpriv_m = ((sbc_tid_m[2:0] == 3'd0) & tlu_lsu_hpstate_hpriv[0]) |
                     ((sbc_tid_m[2:0] == 3'd1) & tlu_lsu_hpstate_hpriv[1]) |
                     ((sbc_tid_m[2:0] == 3'd2) & tlu_lsu_hpstate_hpriv[2]) |
                     ((sbc_tid_m[2:0] == 3'd3) & tlu_lsu_hpstate_hpriv[3]) |
                     ((sbc_tid_m[2:0] == 3'd4) & tlu_lsu_hpstate_hpriv[4]) |
                     ((sbc_tid_m[2:0] == 3'd5) & tlu_lsu_hpstate_hpriv[5]) |
                     ((sbc_tid_m[2:0] == 3'd6) & tlu_lsu_hpstate_hpriv[6]) |
                     ((sbc_tid_m[2:0] == 3'd7) & tlu_lsu_hpstate_hpriv[7]) ;

assign pstate_priv_m_in = (sbc_bst_in_prog_m                 & bst_priv_m) |
                          (twocycle_b                        & pstate_priv_b) |
                          (~(sbc_bst_in_prog_m | twocycle_b) & pstate_priv_m);
assign hpstate_hpriv_m_in = (sbc_bst_in_prog_m                 & bst_hpriv_m) |
                            (twocycle_b                        & hpstate_hpriv_b) |
                            (~(sbc_bst_in_prog_m | twocycle_b) & hpstate_hpriv_m);

lsu_dcc_ctl_msff_ctl_macro__width_2 dff_priv_state_b  (
	.scan_in(dff_priv_state_b_scanin),
	.scan_out(dff_priv_state_b_scanout),
	.din	({pstate_priv_m_in,hpstate_hpriv_m_in}),
	.dout	({pstate_priv_b,   hpstate_hpriv_b}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_priv_b = pstate_priv_b;
assign dcc_hpriv_b = hpstate_hpriv_b;

// TTE's are not valid for internal ASIs and cases where the VA was out-of-range
assign tlb_tte_vld_b = (ld_inst_vld_b | st_inst_vld_b) & ~tlb_bypass_b & tlb_cam_hit & ~tlb_cam_mhit & ~asi_internal_b & ~exu_va_oor_b;

// Qualify tlb_pgnum_b39 with cam_mhit to prevent propagation of bad data
assign pgnum_b39_qual = tlb_pgnum_b39 & ~tlb_cam_mhit;

// Make an M stage version.  This won't reflect the result of tlb_miss, so that has to be factored in elsewhere.
// This is only used for endian determination, so exu_va_oor doesn't have to be factored.
assign dcc_tte_vld_m = (ld_inst_vld_m | st_inst_vld_m) & ~tlb_bypass_m & ~asi_internal_m;


////////////////////////////////////////
// illegal_instruction
// - illegal register alignment
// - illegal rs/rd values for RDPR/RDASR/WRPR/WRASR
// - partial store ASI with i=1
// - wrpr %tick in mode other than hpriv or wrasr to %tick (%asr4)
// - wrhpr to %hver (Rd=6)
// - access to pr<=3 or hpr==1 when tl=0 and not in user mode

assign blk_rd_align_err_m = blk_inst_m & asi_legal_m & ~bad_fp_asi & |(ld_rd_m[2:0]);
assign rd_odd_align_err_m = (ld_inst_vld_m | st_inst_vld_m) & (ldst_dbl_m & ~fpldst_inst_vld_m) & ld_rd_m[0];

assign illegal_spr_m = ~asr_legal_m & ~altspace_ldst_m;

assign pst_with_imm_m = pst_asi_m & asi_legal_m & ~imm_asi_vld_m & ~bad_fp_asi & ~asi_wo_viol;

assign priv_wrpr_tick_m = st_inst_vld_m & (ld_rd_inst_m[4:0] == 5'b00100) &
                          ((pr_inst_m & ~hpstate_hpriv_m & pstate_priv_m) | sr_inst_m);

assign wrhpr_ver_m = hpr_inst_m & st_inst_vld_m & (ld_rd_inst_m[3:0] == 4'b0110);

assign tl_eq_0_m = (ld_inst_vld_m | st_inst_vld_m) & ~tl_gt_0_m & (pstate_priv_m | hpstate_hpriv_m) &
                   ((pr_inst_m & dcc_asi_m[4:2]==3'b000) | (hpr_inst_m & dcc_asi_m[4:0]==5'b00001));

assign illegal_inst_m = (blk_rd_align_err_m | rd_odd_align_err_m | pst_with_imm_m |
                         illegal_spr_m      | priv_wrpr_tick_m   | wrhpr_ver_m    |
                         tl_eq_0_m) &
                        (ld_inst_vld_m | st_inst_vld_m);

////////////////////////////////////////
// mem_address_not_aligned
// Alignment is checked against the VA, unless the instruction
// alignment is modified by an ASI.  ASI modifiers are only used
// if a proper instruction/ASI combination is present.

assign  hw_aligned = ~lsu_va_m[0];
assign  wd_aligned = ~|(lsu_va_m[1:0]);
assign  dw_aligned = ~|(lsu_va_m[2:0]);
assign  qw_aligned = ~|(lsu_va_m[3:0]);
assign  bl_aligned = ~|(lsu_va_m[5:0]);

assign hw_size = bad_fp_asi ? (ldst_sz_m[1:0] == 2'b01) : (ldst_sz_mod_m[1:0] == 2'b01);
assign wd_size = bad_fp_asi ? (ldst_sz_m[1:0] == 2'b10) : (ldst_sz_mod_m[1:0] == 2'b10);
assign dw_size = (bad_fp_asi ? (ldst_sz_m[1:0] == 2'b11) : (ldst_sz_mod_m[1:0] == 2'b11)) & ~bl_size;
assign qw_size = quad_ld_m;
assign bl_size = blk_inst_m; 

assign mem_addr_not_aligned =
	(st_inst_vld_m | (ld_inst_vld_m & ~pref_inst_m)) &
	~(sr_inst_m | pr_inst_m | hpr_inst_m) &
	((hw_size & ~hw_aligned) |
	 (wd_size & ~wd_aligned) |
	 (dw_size & ~dw_aligned) |
	 (qw_size & ~qw_aligned) |
	 (bl_size & ~bl_aligned)) &
        ~(lddf_not_aligned | stdf_not_aligned);

assign lddf_not_aligned = fpldst_inst_vld_m & ldst_dbl_m & ld_inst_vld_m & dw_size & wd_aligned & ~dw_aligned; 
assign stdf_not_aligned = fpldst_inst_vld_m & ldst_dbl_m & st_inst_vld_m & dw_size & wd_aligned & ~dw_aligned; 

////////////////////////////////////////
// privileged_action
// - ASI privilege violations
// ASI's 0x00-0x2F are privileged
// ASI's 0x30-0x7F are hyperprivileged
// NOTE: If TL>0, the implicit ASI=0x04, so user access should cause the trap

// priv access to hpriv ASI's
assign hpriv_asi = ~dcc_asi_m[7] & (dcc_asi_m[6] | (dcc_asi_m[5] & dcc_asi_m[4]));

assign hpriv_asi_excp = altspace_ldst_m & (hpriv_asi & ~hpstate_hpriv_m & pstate_priv_m);

assign priv_action_m = (ld_inst_vld_m | st_inst_vld_m) & 		// valid ld/st inst. AND
                       ~(sr_inst_m | pr_inst_m | hpr_inst_m) &		//  NOT WRSR/WRPR/WRHPR AND
                       ((((altspace_ldst_m & ~dcc_asi_m[7]) |		//   explicit ASI<0x80 OR
                        (~altspace_ldst_m & tl_gt_0_m)) &		//   implicit ASI=0x04   AND
                       ~(hpstate_hpriv_m | pstate_priv_m)) |		//  in user mode  OR
                        hpriv_asi_excp);				//  priv access to hpriv ASIs

////////////////////////////////////////
// data_access_exception
// - attempts to access privileged pages when PSTATE.PRIV=0
// - atomic accesses to ASIs other than those specifically allowed
// - atomic accesses to non-cacheable pages (TTE.CP=0)
// - access to NFO page with an ASI other than non-fault
// - access to NFO page with TTE.E=1
// - non-priv access to pages with TTE.P set
// - invalid ASIs
//   - undefined/unimplemented ASI values
//   - disallowed ASI/instruction combination
//   - write to read-only or read to write-only
//   - internal ASIs with bad VA

assign illegal_asi_m = ~asi_legal_m & altspace_ldst_m;

assign non_atomic_asi_m = atomic_m & ~atomic_asi_m;

assign atomic_uncache_b = (atomic_b | quad_ldd_b) & ((tlb_tte_vld_b & ~tlb_tte_cp_b) | (pgnum_b39_qual & tlb_cam_hit));

assign nfo_pg_nonnfo_asi_b = (ld_inst_vld_b | st_inst_vld_b) & tlb_tte_nfo_b & ~nofault_asi_b & tlb_tte_vld_b;

assign nfo_asi_ebit_b = ld_inst_vld_b & nofault_asi_b & ((tlb_tte_ebit_b & tlb_tte_vld_b) | (tlb_bypass_b & pgnum_b39_qual));

assign user_page_access_m = (ld_inst_vld_m | st_inst_vld_m) & (as_if_user_asi_m | ~(hpstate_hpriv_m | pstate_priv_m));

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_usr_pg_access_b  (
	.scan_in(dff_usr_pg_access_b_scanin),
	.scan_out(dff_usr_pg_access_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(user_page_access_m),
	.dout	(user_page_access_b),
  .siclk(siclk),
  .soclk(soclk)
);
assign priv_page_viol_b = user_page_access_b & tlb_tte_pbit_b & tlb_tte_vld_b;
                           
// Internal ASI's can only be accessed with LDXA/STXA
assign ldxa_asi_exception = (ld_inst_vld_m | st_inst_vld_m) & asi_internal_m & (~(ldst_sz_mod_m[1:0] == 2'b11) | ldst_dbl_m);

// Quad ASI's can only be accessed via LDDA
assign quad_ldda_exception = (ld_inst_vld_m & quad_asi_m & (fpldst_inst_vld_m | ~ldst_dbl_m)) |
                             (st_inst_vld_m & quad_asi_m & ~binit_quad_asi_m);

// Block load/store ASI's can only be accessed via LDDFA/STDFA
assign block_inst_exception = blk_asi_m & ~(ldst_dbl_m & fpldst_inst_vld_m) & (ld_inst_vld_m | st_inst_vld_m);

// Block loads to IO are not allowed
assign bld_to_io_b = ld_inst_vld_b & blk_asi_b & altspace_ldst_b & fpldst_inst_vld_b & ldst_dbl_b & pgnum_b39_qual & tlb_cam_hit;

// Stores to nofault asi's are not allowed
assign nofault_st_exception = st_inst_vld_m & nofault_asi_m;

// ASI_FL* and ASI_PST* only with LDDFA/STDFA
assign bad_fp_asi = (asi_sz_byte_m | asi_sz_hw_m | pst_asi_m) & ~(ldst_dbl_m & fpldst_inst_vld_m) & (ld_inst_vld_m | st_inst_vld_m);

// BLK_INIT_ST only allowed with integer stores
assign bis_with_fp = st_inst_vld_m & binit_quad_asi_m & fpldst_inst_vld_m;

// read-only/write-only violations (the ones from asi decode only indicate if the entire ASI is RO/WO) 
assign asi_ro_viol = (altspace_ldst_m & st_inst_vld_m) & 
	(asi_read_only_m |
	 ((dcc_asi_m[7:0] == 8'h40) & ((lsu_va_m[7:5] == 3'b101) |		// 0x40/0xA0
                                       (lsu_va_m[5:4] == 2'b11)	)		// 0x40/0x30
	 ) |
	 ((dcc_asi_m[7:0] == 8'h41) & ((lsu_va_m[7:5] == 3'b000) |		// 0x41/0x0+0x10
	                               (lsu_va_m[7:3] == 5'b01011))		// 0x41/0x58
	 ) |
	 ((dcc_asi_m[7:0] == 8'h50) & (lsu_va_m[7:4] == 4'b0000) 		// 0x50/0x0
	 ) |
	 ((dcc_asi_m[7:0] == 8'h58) & ((lsu_va_m[7:4] == 4'b0000) |		// 0x58/0x0
	                               (lsu_va_m[7:4] == 4'b0010))		// 0x58/0x20
	 ) |
	 ((dcc_asi_m[7:0] == 8'h54) & ((lsu_va_m[7]&!lsu_va_m[4]) |		// 0x54/0x50-0x88
	                               (lsu_va_m[7]&lsu_va_m[3]) | 
	                               (lsu_va_m[6]&lsu_va_m[5]) | 
                                       (lsu_va_m[6]&lsu_va_m[4]))
	 ) |
	 ((dcc_asi_m[7:0] == 8'h4c) & ((lsu_va_m[5]) |				// 0x4c/0x20-0x28
                                       (lsu_va_m[5:4] == 2'b00))		// 0x4c/0x0-0x8
         )
	);

assign asi_wo_viol = (altspace_ldst_m & ld_inst_vld_m) &
	(asi_write_only_m |
	 ((dcc_asi_m[7:0] == 8'h40) & (lsu_va_m[5:3] == 3'b101)			// 0x40/0x28
	 ) |
	 ((dcc_asi_m[7:0] == 8'h41) & (lsu_va_m[7:4] == 4'b0110)		// 0x41/0x60+0x68
	 ) |
	 ((dcc_asi_m[7:0] == 8'h54) & (lsu_va_m[7:4] == 4'b0000)		// 0x54/0x0+0x400+0x800+0xC00
	 )
	);

// Check for valid ASI/VA accesses.  ASI's which provide diagnostic access to
// arrays have wide allowable ranges, so they are not checked.  All other internal
// ASI's are strictly checked.  Excluding array diag and demap ASI's, all others
// only use the bottom 12 bits of the VA, so [47:12] must be zeros.
assign bad_asi_va_exception_m = altspace_ldst_m & asi_internal_m & ~asi_no_va_check_m &
                                (~legal_asi_va_m | (|(lsu_va_m[15:12])) | ~tld_va_m_eq_zero) ;

// Writes to the interrupt queue registers (ASI=0x25) by supervisor is not allowed.
assign wrpriv_intq_reg_m = (altspace_ldst_m & st_inst_vld_m) & (dcc_asi_m[7:0] == 8'h25) &
                           lsu_va_m[3] & ~hpstate_hpriv_m & pstate_priv_m;
//assign wrpriv_intq_reg_m = 1'b0;

assign dae_invalid_asi_m = illegal_asi_m 	| ldxa_asi_exception 	| quad_ldda_exception	| 
                           asi_ro_viol 		| asi_wo_viol		|
                           non_atomic_asi_m	| bad_asi_va_exception_m|
                           block_inst_exception	| nofault_st_exception	| bad_fp_asi		|
                           bis_with_fp		| wrpriv_intq_reg_m;

lsu_dcc_ctl_msff_ctl_macro__width_5 dff_excp_b  (
	.scan_in(dff_excp_b_scanin),
	.scan_out(dff_excp_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dae_invalid_asi_m,dcc_tlb_bypass,tlb_bypass_m,dcc_tlb_real,tlb_real_m}),
	.dout	({dae_invalid_asi_b,tlb_bypass_m,  tlb_bypass_b,tlb_real_m,  tlb_real_b}),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_tlb_bypass_b = tlb_bypass_b;
assign lsu_tlb_real_b = tlb_real_b;

assign access_exception_b = ~pref_inst_b &
                (dae_invalid_asi_b | nfo_pg_nonnfo_asi_b | priv_page_viol_b | atomic_uncache_b |
                 nfo_asi_ebit_b | bld_to_io_b);
assign lsu_dae_invalid_asi_b = ~pref_inst_b & dae_invalid_asi_b;
assign lsu_dae_nc_page_b     = ~pref_inst_b & (atomic_uncache_b | bld_to_io_b);
assign lsu_dae_nfo_page_b    = ~pref_inst_b & nfo_pg_nonnfo_asi_b;
assign lsu_dae_priv_viol_b   = ~pref_inst_b & priv_page_viol_b;
assign lsu_dae_so_page       = ~pref_inst_b & nfo_asi_ebit_b;

////////////////////////////////////////
// watchpoint exceptions
// Only one exception (VA or PA) can be enabled per thread.
// If both are enabled in ASI_LSU_CONTROL_REG, only VA will be checked.
// Nontranslating(internal) or illegal ASI's should not cause wpt traps.
// RA->PA and bypass translations should not cause VA wpt traps.
assign va_wpt_en_m = dcs_wpt_mode_m[1] & dcs_wpt_mode_m[0] & 
                      ~asi_internal_m & ~illegal_asi_m & ~tlb_bypass_m & ~tlb_real_m & ~hpstate_hpriv_m;
assign pa_wpt_en_m = dcs_wpt_mode_m[1] & ~dcs_wpt_mode_m[0] &
                      ~asi_internal_m & ~illegal_asi_m;

assign va_wpt_rd_en_m = dcs_wpt_enable_m[1] & va_wpt_en_m;
assign va_wpt_wr_en_m = dcs_wpt_enable_m[0] & va_wpt_en_m;
assign pa_wpt_rd_en_m = dcs_wpt_enable_m[1] & pa_wpt_en_m;
assign pa_wpt_wr_en_m = dcs_wpt_enable_m[0] & pa_wpt_en_m;

// ldst_bmask is positional and corresponds to the byte within the 64B dword
// Each bit of dcs_wpt_mask corresponds to the big endian byte address within
// the 64B dword
// ldst_bmask		 [7]   [6]   [5]   [4]   [3]   [2]   [1]   [0]
// 64B dword		byte0 byte1 byte2 byte3 byte4 byte5 byte6 byte7 
// dcs_wpt_mask		 [0]   [1]   [2]   [3]   [4]   [5]   [6]   [7]

assign wpt_bmask[7:0] = ldst_bmask[7:0] | {8{pst_asi_m & ~bad_fp_asi}};

assign mask_match_m = (wpt_bmask[7] & dcs_wpt_mask_m[0]) |
                      (wpt_bmask[6] & dcs_wpt_mask_m[1]) |
                      (wpt_bmask[5] & dcs_wpt_mask_m[2]) |
                      (wpt_bmask[4] & dcs_wpt_mask_m[3]) |
                      (wpt_bmask[3] & dcs_wpt_mask_m[4]) |
                      (wpt_bmask[2] & dcs_wpt_mask_m[5]) |
                      (wpt_bmask[1] & dcs_wpt_mask_m[6]) |
                      (wpt_bmask[0] & dcs_wpt_mask_m[7]) ;

assign va_wpt_check_m = mask_match_m & ((va_wpt_rd_en_m & ld_inst_vld_m & ~pref_inst_m) | (va_wpt_wr_en_m & st_inst_vld_m));
assign pa_wpt_check_m = mask_match_m & ((pa_wpt_rd_en_m & ld_inst_vld_m & ~pref_inst_m) | (pa_wpt_wr_en_m & st_inst_vld_m));

lsu_dcc_ctl_msff_ctl_macro__width_2 dff_wpt  (
	.scan_in(dff_wpt_scanin),
	.scan_out(dff_wpt_scanout),
	.l1clk	(l1clk_pm1),
	.din	({va_wpt_check_m,pa_wpt_check_m}),
	.dout	({va_wpt_check_b,pa_wpt_check_b}),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_va_watchpoint_b = tgd_va_wp_47_16 & tgd_va_wp_15_3 & va_wpt_check_b;
assign lsu_pa_watchpoint_b = tgd_pa_wp_39_16 & tgd_pa_wp_15_3 & pa_wpt_check_b & ~tlb_cam_mhit;

// 0in bits_on -var {lsu_va_watchpoint_b,lsu_pa_watchpoint_b} -max 1 -message "Both watchpoints fired!"

//////////////////////////////////////////
// Feedback from the ASI ring

assign asi_rtn_vld_2f = arc_pid_ctl_2f[6];
assign asi_rtn_excp_2f = arc_pid_ctl_2f[5] | arc_pid_ctl_2f[4];
assign asi_rtn_rd_2f = arc_pid_ctl_2f[3];
assign asi_rtn_tid_2f[2:0] = arc_pid_ctl_2f[2:0];

lsu_dcc_ctl_msff_ctl_macro__width_6 dff_asi_g  (
	.scan_in(dff_asi_g_scanin),
	.scan_out(dff_asi_g_scanout),
	.din	({asi_rtn_vld_2f,asi_rtn_excp_2f,asi_rtn_rd_2f,asi_rtn_tid_2f[2:0]}),
	.dout	({asi_rtn_vld_3f,asi_rtn_excp_3f,asi_rtn_rd_3f,asi_rtn_tid_3f[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_asi_rtn_vld[0] = asi_rtn_vld_3f & (asi_rtn_tid_3f[2:0] == 3'd0);
assign dcc_asi_rtn_vld[1] = asi_rtn_vld_3f & (asi_rtn_tid_3f[2:0] == 3'd1);
assign dcc_asi_rtn_vld[2] = asi_rtn_vld_3f & (asi_rtn_tid_3f[2:0] == 3'd2);
assign dcc_asi_rtn_vld[3] = asi_rtn_vld_3f & (asi_rtn_tid_3f[2:0] == 3'd3);
assign dcc_asi_rtn_vld[4] = asi_rtn_vld_3f & (asi_rtn_tid_3f[2:0] == 3'd4);
assign dcc_asi_rtn_vld[5] = asi_rtn_vld_3f & (asi_rtn_tid_3f[2:0] == 3'd5);
assign dcc_asi_rtn_vld[6] = asi_rtn_vld_3f & (asi_rtn_tid_3f[2:0] == 3'd6);
assign dcc_asi_rtn_vld[7] = asi_rtn_vld_3f & (asi_rtn_tid_3f[2:0] == 3'd7);
assign dcc_asi_rtn_excp = asi_rtn_excp_3f;
assign dcc_asi_rtn_rd = asi_rtn_rd_3f;


//////////////////////////////////////////
// Outputs to TLU

lsu_dcc_ctl_msff_ctl_macro__width_5 dff_except  (
	.scan_in(dff_except_scanin),
	.scan_out(dff_except_scanout),
	.l1clk	(l1clk_pm1),
	.din	({mem_addr_not_aligned,lddf_not_aligned,stdf_not_aligned,priv_action_m,illegal_inst_m}),
	.dout	({lsu_align_b,         lsu_lddf_align_b,lsu_stdf_align_b,priv_action_b,lsu_illegal_inst_b}),
  .siclk(siclk),
  .soclk(soclk)
);

// Prefetch should not cause priv_action or tlb_miss exception
assign lsu_priv_action_b = priv_action_b & ~pref_inst_b;
assign lsu_tlb_miss_b_ = tlb_cam_hit | pref_inst_b | dae_invalid_asi_b;

assign lsu_daccess_prot_b = (st_inst_vld_b & ~tlb_tte_wbit_b & tlb_tte_vld_b) & ~access_exception_b; 

// Some conditions cause prefetch instructions to be treated as NOP.  These include
// prefetch to IO space
// prefetch with fcn=0x4,0x19-0x1f
// prefetcha with "bad" asi
// prefetch with fcn=0x18 and not hypervisor
// prefetcha with fcn=0x18
assign nop_pref_func = (~ld_rd_b[4]&ld_rd_b[2]) | (ld_rd_b[3] & |(ld_rd_b[2:0]));// DEC detects illegal for 0x5-0xf
assign pref_ice_b = pref_inst_b & (ld_rd_b[3:0] == 4'b1000);

assign pref_nop_b = pref_inst_b & 
                    (pgnum_b39_qual |
                     nop_pref_func |
                     (altspace_ldst_b & (~asi_legal_b | (~nofault_asi_b & ~atomic_asi_b))) |
                     ((ld_rd_b[3:0] == 4'b1000) & (altspace_ldst_b | ~hpstate_hpriv_b))
                    );

assign dcc_any_exception_b = lsu_align_b             | lsu_lddf_align_b    | lsu_stdf_align_b |
                             lsu_va_watchpoint_b     | lsu_pa_watchpoint_b | lsu_dtmh_err_b   | 
                             priv_action_b           | ~tlb_cam_hit        | lsu_dttp_err_b   |
                             lsu_illegal_inst_b      | lsu_daccess_prot_b  | lsu_dtdp_err_b   |
                             access_exception_b      | pref_nop_b          | lsu_perfmon_trap_b;


assign lsu_tlu_dsfsr_ct_b[1:0] = context_enc_b[1:0];

// FGU needs exceptions for setting FSR.ftt
lsu_dcc_ctl_msff_ctl_macro__width_1 dff_fgu_excp_w  (
	.scan_in(dff_fgu_excp_w_scanin),
	.scan_out(dff_fgu_excp_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	((dcc_any_exception_b | exu_error_b)),
	.dout	(lsu_fgu_exception_w),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////
// Logic for maintaining I$/D$ exlusivity
// I must store the index for each outgoing ifetch request so that
// if an invalidation is required, I know what line it applies to
////////////////////////////////////////////////////////////////////////

assign if_indx_0_in[10:5] = (ifu_lsu_if_vld & (ifu_lsu_if_tid[2:0]==3'd0)) ? ifu_lsu_if_addr[10:5] : if_indx_0[10:5];
assign if_indx_1_in[10:5] = (ifu_lsu_if_vld & (ifu_lsu_if_tid[2:0]==3'd1)) ? ifu_lsu_if_addr[10:5] : if_indx_1[10:5];
assign if_indx_2_in[10:5] = (ifu_lsu_if_vld & (ifu_lsu_if_tid[2:0]==3'd2)) ? ifu_lsu_if_addr[10:5] : if_indx_2[10:5];
assign if_indx_3_in[10:5] = (ifu_lsu_if_vld & (ifu_lsu_if_tid[2:0]==3'd3)) ? ifu_lsu_if_addr[10:5] : if_indx_3[10:5];
assign if_indx_4_in[10:5] = (ifu_lsu_if_vld & (ifu_lsu_if_tid[2:0]==3'd4)) ? ifu_lsu_if_addr[10:5] : if_indx_4[10:5];
assign if_indx_5_in[10:5] = (ifu_lsu_if_vld & (ifu_lsu_if_tid[2:0]==3'd5)) ? ifu_lsu_if_addr[10:5] : if_indx_5[10:5];
assign if_indx_6_in[10:5] = (ifu_lsu_if_vld & (ifu_lsu_if_tid[2:0]==3'd6)) ? ifu_lsu_if_addr[10:5] : if_indx_6[10:5];
assign if_indx_7_in[10:5] = (ifu_lsu_if_vld & (ifu_lsu_if_tid[2:0]==3'd7)) ? ifu_lsu_if_addr[10:5] : if_indx_7[10:5];

lsu_dcc_ctl_msff_ctl_macro__width_6 dff_if_indx_0  (
	.scan_in(dff_if_indx_0_scanin),
	.scan_out(dff_if_indx_0_scanout),
	.l1clk	(l1clk_pm2),
	.din	(if_indx_0_in[10:5]),
	.dout	(if_indx_0[10:5]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_dcc_ctl_msff_ctl_macro__width_6 dff_if_indx_1  (
	.scan_in(dff_if_indx_1_scanin),
	.scan_out(dff_if_indx_1_scanout),
	.l1clk	(l1clk_pm2),
	.din	(if_indx_1_in[10:5]),
	.dout	(if_indx_1[10:5]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_dcc_ctl_msff_ctl_macro__width_6 dff_if_indx_2  (
	.scan_in(dff_if_indx_2_scanin),
	.scan_out(dff_if_indx_2_scanout),
	.l1clk	(l1clk_pm2),
	.din	(if_indx_2_in[10:5]),
	.dout	(if_indx_2[10:5]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_dcc_ctl_msff_ctl_macro__width_6 dff_if_indx_3  (
	.scan_in(dff_if_indx_3_scanin),
	.scan_out(dff_if_indx_3_scanout),
	.l1clk	(l1clk_pm2),
	.din	(if_indx_3_in[10:5]),
	.dout	(if_indx_3[10:5]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_dcc_ctl_msff_ctl_macro__width_6 dff_if_indx_4  (
	.scan_in(dff_if_indx_4_scanin),
	.scan_out(dff_if_indx_4_scanout),
	.l1clk	(l1clk_pm2),
	.din	(if_indx_4_in[10:5]),
	.dout	(if_indx_4[10:5]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_dcc_ctl_msff_ctl_macro__width_6 dff_if_indx_5  (
	.scan_in(dff_if_indx_5_scanin),
	.scan_out(dff_if_indx_5_scanout),
	.l1clk	(l1clk_pm2),
	.din	(if_indx_5_in[10:5]),
	.dout	(if_indx_5[10:5]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_dcc_ctl_msff_ctl_macro__width_6 dff_if_indx_6  (
	.scan_in(dff_if_indx_6_scanin),
	.scan_out(dff_if_indx_6_scanout),
	.l1clk	(l1clk_pm2),
	.din	(if_indx_6_in[10:5]),
	.dout	(if_indx_6[10:5]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_dcc_ctl_msff_ctl_macro__width_6 dff_if_indx_7  (
	.scan_in(dff_if_indx_7_scanin),
	.scan_out(dff_if_indx_7_scanout),
	.l1clk	(l1clk_pm2),
	.din	(if_indx_7_in[10:5]),
	.dout	(if_indx_7[10:5]),
  .siclk(siclk),
  .soclk(soclk)
);

assign xinv_index[10:5] = ({6{(cid_tid[2:0] == 3'd0)}} & if_indx_0[10:5]) |
                          ({6{(cid_tid[2:0] == 3'd1)}} & if_indx_1[10:5]) |
                          ({6{(cid_tid[2:0] == 3'd2)}} & if_indx_2[10:5]) |
                          ({6{(cid_tid[2:0] == 3'd3)}} & if_indx_3[10:5]) |
                          ({6{(cid_tid[2:0] == 3'd4)}} & if_indx_4[10:5]) |
                          ({6{(cid_tid[2:0] == 3'd5)}} & if_indx_5[10:5]) |
                          ({6{(cid_tid[2:0] == 3'd6)}} & if_indx_6[10:5]) |
                          ({6{(cid_tid[2:0] == 3'd7)}} & if_indx_7[10:5]) ;
assign xinv_index[4] = cid_atomic;

assign xinval_bit_wen_e[0]  = ~xinv_index[5] & ~xinv_index[4] & ~cid_xway[1] & ~cid_xway[0];
assign xinval_bit_wen_e[1]  = ~xinv_index[5] & ~xinv_index[4] & ~cid_xway[1] &  cid_xway[0];
assign xinval_bit_wen_e[2]  = ~xinv_index[5] & ~xinv_index[4] &  cid_xway[1] & ~cid_xway[0];
assign xinval_bit_wen_e[3]  = ~xinv_index[5] & ~xinv_index[4] &  cid_xway[1] &  cid_xway[0];
assign xinval_bit_wen_e[4]  = ~xinv_index[5] &  xinv_index[4] & ~cid_xway[1] & ~cid_xway[0];
assign xinval_bit_wen_e[5]  = ~xinv_index[5] &  xinv_index[4] & ~cid_xway[1] &  cid_xway[0];
assign xinval_bit_wen_e[6]  = ~xinv_index[5] &  xinv_index[4] &  cid_xway[1] & ~cid_xway[0];
assign xinval_bit_wen_e[7]  = ~xinv_index[5] &  xinv_index[4] &  cid_xway[1] &  cid_xway[0];
assign xinval_bit_wen_e[8]  =  xinv_index[5] & ~xinv_index[4] & ~cid_xway[1] & ~cid_xway[0];
assign xinval_bit_wen_e[9]  =  xinv_index[5] & ~xinv_index[4] & ~cid_xway[1] &  cid_xway[0];
assign xinval_bit_wen_e[10] =  xinv_index[5] & ~xinv_index[4] &  cid_xway[1] & ~cid_xway[0];
assign xinval_bit_wen_e[11] =  xinv_index[5] & ~xinv_index[4] &  cid_xway[1] &  cid_xway[0];
assign xinval_bit_wen_e[12] =  xinv_index[5] &  xinv_index[4] & ~cid_xway[1] & ~cid_xway[0];
assign xinval_bit_wen_e[13] =  xinv_index[5] &  xinv_index[4] & ~cid_xway[1] &  cid_xway[0];
assign xinval_bit_wen_e[14] =  xinv_index[5] &  xinv_index[4] &  cid_xway[1] & ~cid_xway[0];
assign xinval_bit_wen_e[15] =  xinv_index[5] &  xinv_index[4] &  cid_xway[1] &  cid_xway[0];

////////////////////////////////////////////////////////////////////////
// Parity error detection
////////////////////////////////////////////////////////////////////////

lsu_dcc_ctl_msff_ctl_macro__width_4 dff_way_vld_b  (
	.scan_in(dff_way_vld_b_scanin),
	.scan_out(dff_way_vld_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(tgc_cache_way_vld_m[3:0]),
	.dout	(cache_way_vld_b[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Valid bit errors have top priority
assign dval_perr_b[0] = dcache_read_b & tgc_verr_b[0] & cerer_dcvp & ~pgnum_b39_qual;
assign dval_perr_b[1] = dcache_read_b & tgc_verr_b[1] & cerer_dcvp & ~pgnum_b39_qual;
assign dval_perr_b[2] = dcache_read_b & tgc_verr_b[2] & cerer_dcvp & ~pgnum_b39_qual;
assign dval_perr_b[3] = dcache_read_b & tgc_verr_b[3] & cerer_dcvp & ~pgnum_b39_qual;
assign dval_perror_b = |(dval_perr_b[3:0]);

// Tag errors have next priority
assign dtag_perr_b[0] = dcache_read_b & (tgd_w0_parity_b & cache_way_vld_b[0]) & cerer_dctp & ~pgnum_b39_qual;
assign dtag_perr_b[1] = dcache_read_b & (tgd_w1_parity_b & cache_way_vld_b[1]) & cerer_dctp & ~pgnum_b39_qual;
assign dtag_perr_b[2] = dcache_read_b & (tgd_w2_parity_b & cache_way_vld_b[2]) & cerer_dctp & ~pgnum_b39_qual;
assign dtag_perr_b[3] = dcache_read_b & (tgd_w3_parity_b & cache_way_vld_b[3]) & cerer_dctp & ~pgnum_b39_qual;
assign dtag_perror_b = ~dval_perror_b & |(dtag_perr_b[3:0]);

// Multiple tag hit errors have next priority
assign mhit_err_b = ((tlb_cache_way_hit_b[0] & tlb_cache_way_hit_b[1]) |
                     (tlb_cache_way_hit_b[0] & tlb_cache_way_hit_b[2]) |
                     (tlb_cache_way_hit_b[0] & tlb_cache_way_hit_b[3]) |
                     (tlb_cache_way_hit_b[1] & tlb_cache_way_hit_b[2]) |
                     (tlb_cache_way_hit_b[1] & tlb_cache_way_hit_b[3]) |
                     (tlb_cache_way_hit_b[2] & tlb_cache_way_hit_b[3])) &
                       dcache_read_b & cerer_dctm & ~pgnum_b39_qual;
assign mhit_error_b = mhit_err_b & ~(dval_perror_b | dtag_perror_b);

// Data parity errors are lowest priority
assign data_perr_b[0] = dcache_read_b & dca_perr_w0_b & cache_way_vld_b[0] & cerer_dcdp & ~pgnum_b39_qual;
assign data_perr_b[1] = dcache_read_b & dca_perr_w1_b & cache_way_vld_b[1] & cerer_dcdp & ~pgnum_b39_qual;
assign data_perr_b[2] = dcache_read_b & dca_perr_w2_b & cache_way_vld_b[2] & cerer_dcdp & ~pgnum_b39_qual;
assign data_perr_b[3] = dcache_read_b & dca_perr_w3_b & cache_way_vld_b[3] & cerer_dcdp & ~pgnum_b39_qual;
assign data_perror_b = ~(dval_perror_b | dtag_perror_b | mhit_error_b) & |(data_perr_b[3:0]);

assign dcc_perror_b = dval_perror_b | (|(dtag_perr_b[3:0])) | mhit_err_b | (|(data_perr_b[3:0]));

// Error encodings - 00=valid, 01=tag, 10=mhit, 11=data - prioritized in that order
assign dcc_perr_enc_b[1] = mhit_error_b | data_perror_b;
assign dcc_perr_enc_b[0] = dtag_perror_b | data_perror_b;

// Way encodings
assign way_err[0] = (dval_perror_b & dval_perr_b[0]) |
                    (dtag_perror_b & dtag_perr_b[0]) |
                    (data_perror_b & data_perr_b[0])  |
                    (mhit_error_b  & tlb_cache_way_hit_b[0]);
assign way_err[1] = (dval_perror_b & dval_perr_b[1]) |
                    (dtag_perror_b & dtag_perr_b[1]) |
                    (data_perror_b & data_perr_b[1])  |
                    (mhit_error_b  & tlb_cache_way_hit_b[1]);
assign way_err[2] = (dval_perror_b & dval_perr_b[2]) |
                    (dtag_perror_b & dtag_perr_b[2]) |
                    (data_perror_b & data_perr_b[2])  |
                    (mhit_error_b  & tlb_cache_way_hit_b[2]);

assign way_err_enc[1] = ~way_err[0] & ~way_err[1];
assign way_err_enc[0] = ~way_err[0] & (way_err[1] | ~way_err[2]);

// Check that errors are never signaled during normal testing


///////////////////////
// TLB errors

// Resolve TLB tag parity error here.  Select the proper parity bit based
// on the page size and compare it to the stored parity.

assign prty_ctxt = (tlb_context0_hit ? tgd_prty_ctxt0_b : tgd_prty_ctxt1_b) & ~tlb_real_b;

assign tag_parity = (( tlb_pgsize[2] &                                   tgd_prty_256m_b) |
                     (~tlb_pgsize[2] &  tlb_pgsize[1] &                  tgd_prty_4m_b) |
                     (~tlb_pgsize[2] & ~tlb_pgsize[1] &  tlb_pgsize[0] & tgd_prty_64k_b) |
                     (~tlb_pgsize[2] & ~tlb_pgsize[1] & ~tlb_pgsize[0] & tgd_prty_8k_b)) ^
                     prty_ctxt;
     

assign lsu_dttp_err_b = cerer_dttp & tlb_tte_vld_b & (tag_parity ^ tlb_tag_parity);
assign lsu_dtdp_err_b = cerer_dtdp & tlb_tte_vld_b & tlb_tte_data_parity;
assign lsu_dtmh_err_b = cerer_dttm & tlb_cam_mhit;

////////////////////////////////////////////////////////////////////////
// Perfmon support
// TID always indicates the l2_miss since pmu knows what's in B of the pipe
////////////////////////////////////////////////////////////////////////


// D$ miss
assign lsu_pmu_mem_type_b[0] = ld_inst_vld_b & ~(tlb_cache_hit_b & dcache_enable_b) & ~asi_internal_b &
                                ~ncache_rq_b & ~pipe_flush_b & tlb_cam_hit;

// DTLB miss
assign lsu_pmu_mem_type_b[1] = ~lsu_tlb_miss_b_ & ~pipe_flush_b;

// Generate traps if pmu requests
assign dcmiss_trap_m = pmu_lsu_dcmiss_trap_m;
assign dtmiss_trap_m = pmu_lsu_dtmiss_trap_m;

assign lsu_perfmon_trap_b = (dcmiss_trap_b & lsu_pmu_mem_type_b[0]) |
                            (dtmiss_trap_b & lsu_pmu_mem_type_b[1]) ;

// L2 miss (Don't count atomics)

assign l2miss_no_atomic_e = ((lmc_bld_annul | lmc_bld_last_e) ? lmc_bld_miss_e : cid_l2miss) & ~cid_atomic;

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_l2miss  (
	.scan_in(dff_l2miss_scanin),
	.scan_out(dff_l2miss_scanout),
	.din	(l2miss_no_atomic_e),
	.dout	(l2miss_no_atomic_m),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// The l2dmiss isn't really aligned to the M cycle.
assign l2lmiss_trap_e =((cid_tid[2:0] == 3'b000) & pmu_lsu_l2dmiss_trap_m[0]) |
                       ((cid_tid[2:0] == 3'b001) & pmu_lsu_l2dmiss_trap_m[1]) |
                       ((cid_tid[2:0] == 3'b010) & pmu_lsu_l2dmiss_trap_m[2]) |
                       ((cid_tid[2:0] == 3'b011) & pmu_lsu_l2dmiss_trap_m[3]) |
                       ((cid_tid[2:0] == 3'b100) & pmu_lsu_l2dmiss_trap_m[4]) |
                       ((cid_tid[2:0] == 3'b101) & pmu_lsu_l2dmiss_trap_m[5]) |
                       ((cid_tid[2:0] == 3'b110) & pmu_lsu_l2dmiss_trap_m[6]) |
                       ((cid_tid[2:0] == 3'b111) & pmu_lsu_l2dmiss_trap_m[7]) ;

lsu_dcc_ctl_msff_ctl_macro__width_4 dff_pmu_trap  (
	.scan_in(dff_pmu_trap_scanin),
	.scan_out(dff_pmu_trap_scanout),
	.din	({dcmiss_trap_m,dtmiss_trap_m,l2lmiss_trap_e,load_complete_e}),
	.dout	({dcmiss_trap_b,dtmiss_trap_b,l2lmiss_trap_m,load_complete_m}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign load_complete_e = cic_rtn_cmplt & ~lmc_bld_annul;

assign l2_perfmon_wb_cancel_m = l2fill_vld_m & l2miss_no_atomic_m & l2lmiss_trap_m;

// These really assert in M.  (The tid can be shared with TLU this way.)
assign lsu_pmu_mem_type_b[2] = l2miss_no_atomic_m & load_complete_m;

assign lsu_perfmon_trap_g = l2lmiss_trap_m & l2miss_no_atomic_m & load_complete_m;

////////////////////////////////////////////////////////////////////////
// Power management controls
////////////////////////////////////////////////////////////////////////

assign lsu_lsu_pmen_ = ~lsu_lsu_pmen;

assign dcc_sbd_e_clken = dec_st_inst_e | casa_inst_m | dcc_std_inst_m | lsu_lsu_pmen_; 
assign dcc_sbd_m_clken = sbd_m_clken | sbc_bst_in_prog_m | lsu_lsu_pmen_;

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_pwr_mgmt  (
	.scan_in(dff_pwr_mgmt_scanin),
	.scan_out(dff_pwr_mgmt_scanout),
	.din	(dcc_sbd_e_clken),
	.dout	(sbd_m_clken),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_ldst_m_clken = ld_inst_vld_m | st_inst_vld_m | lsu_lsu_pmen_;

assign dcc_pm_clken = lsu_lsu_pmen_    | mbi_run_local | 
                      ld_inst_unqual_e | dec_st_inst_e | dec_flush_inst_e | dec_memstbar_inst_e |
                      ld_inst_vld_m    | st_inst_vld_m | sync_inst_m |
                      ld_inst_vld_b    | st_inst_vld_b | sync_inst_b |
                      ld_inst_vld_w    | st_inst_vld_w | sync_inst_w ;

assign ifu_indx_clken = lsu_lsu_pmen_ | ifu_lsu_if_vld;

////////////////////////////////////////////////////////////////////////
// BIST / DIAGNOSTICS
////////////////////////////////////////////////////////////////////////

lsu_dcc_ctl_msff_ctl_macro__width_1 dff_bist_run  (
	.scan_in(dff_bist_run_scanin),
	.scan_out(dff_bist_run_scanout),
	.din	(mbi_run),
	.dout	(mbi_run_local),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_dcc_ctl_msff_ctl_macro__width_8 dff_bist_in  (
	.scan_in(dff_bist_in_scanin),
	.scan_out(dff_bist_in_scanout),
	.l1clk	(l1clk_pm1),
	.din	({mbi_dca_read_en,bist_dca_rd_1,  mbi_lru_read_en,bist_lru_rd_1,
		  mbi_dtb_cam_en_pre, tlb_cam_en_pre, mbi_scm_cam_en_pre,mbi_dtb_read_en}),
	.dout	({bist_dca_rd_1,  bist_dca_cmp_en,bist_lru_rd_1,  bist_lru_cmp_en,
		  tlb_cam_en_pre,     bist_cam_en, mbi_scm_cam_en,    bist_dtb_read_en}),
  .siclk(siclk),
  .soclk(soclk)
);

assign dcc_mbi_run = mbi_run_local;

assign dca_parity_compare = (dca_rparity_b[7:0] == bist_cmp_data[7:0]);
assign dca_fail = bist_dca_cmp_en & (~dcd_dca_data_compare[1] | ~dcd_dca_data_compare[0] | ~dca_parity_compare);

assign lru_fail = bist_lru_cmp_en & (lru_state_in_b[5:0] != bist_cmp_data[5:0]);

lsu_dcc_ctl_msff_ctl_macro__width_2 dff_bist_fail  (
	.scan_in(dff_bist_fail_scanin),
	.scan_out(dff_bist_fail_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dca_fail,        lru_fail}),
	.dout	({lsu_mbi_dca_fail,lsu_mbi_lru_fail}),
  .siclk(siclk),
  .soclk(soclk)
);

// DMO reads parity.  Need to mux between hi/lo here.
assign dcc_dmo_parity[3:0] = dmo_dcmuxctl ? dca_rparity_b[7:4] : dca_rparity_b[3:0];

lsu_dcc_ctl_spare_ctl_macro__num_9 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_cerer_scanin          = scan_in                  ;
assign dff_flush_b_scanin        = dff_cerer_scanout        ;
assign dff_flush_w_scanin        = dff_flush_b_scanout      ;
assign dff_asi_d_scanin          = dff_flush_w_scanout      ;
assign dff_dec_inst1_m_scanin    = dff_asi_d_scanout        ;
assign dff_sync_inst_scanin      = dff_dec_inst1_m_scanout  ;
assign dff_dec_ctl_m_scanin      = dff_sync_inst_scanout    ;
assign dff_dec_inst_b_scanin     = dff_dec_ctl_m_scanout    ;
assign dff_dec_ctl_b_scanin      = dff_dec_inst_b_scanout   ;
assign dff_tid_e_scanin          = dff_dec_ctl_b_scanout    ;
assign dff_tid_m_scanin          = dff_tid_e_scanout        ;
assign dff_tid_b_scanin          = dff_tid_m_scanout        ;
assign dff_tid_w_scanin          = dff_tid_b_scanout        ;
assign dff_altspace_m_scanin     = dff_tid_w_scanout        ;
assign dff_altspace_b_scanin     = dff_altspace_m_scanout   ;
assign dff_fpld_b_scanin         = dff_altspace_b_scanout   ;
assign dff_oddrd_scanin          = dff_fpld_b_scanout       ;
assign dff_rs2_m_scanin          = dff_oddrd_scanout        ;
assign dff_sba_par_scanin        = dff_rs2_m_scanout        ;
assign dff_early_ld_scanin       = dff_sba_par_scanout      ;
assign dff_sync_pipe_scanin      = dff_early_ld_scanout     ;
assign dff_sync_st_scanin        = dff_sync_pipe_scanout    ;
assign dc_enable_scanin          = dff_sync_st_scanout      ;
assign dff_l2fill_m_scanin       = dc_enable_scanout        ;
assign dff_l2fill_b_scanin       = dff_l2fill_m_scanout     ;
assign dff_ld_tid_b_scanin       = dff_l2fill_b_scanout     ;
assign dff_fp32_b_scanin         = dff_ld_tid_b_scanout     ;
assign dff_ld_vld_w_scanin       = dff_fp32_b_scanout       ;
assign dff_le_bits_scanin        = dff_ld_vld_w_scanout     ;
assign dff_tl_gt_0_scanin        = dff_le_bits_scanout      ;
assign dff_tlc_scanin            = dff_tl_gt_0_scanout      ;
assign dff_ct_scanin             = dff_tlc_scanout          ;
assign dff_asi_m_scanin          = dff_ct_scanout           ;
assign dff_asi_b_scanin          = dff_asi_m_scanout        ;
assign dff_int_asi_m_scanin      = dff_asi_b_scanout        ;
assign dff_int_asi_b_scanin      = dff_int_asi_m_scanout    ;
assign dff_int_asi_w_scanin      = dff_int_asi_b_scanout    ;
assign dff_wr_state_w_scanin     = dff_int_asi_w_scanout    ;
assign dff_tlu_asi_scanin        = dff_wr_state_w_scanout   ;
assign dff_stb_w3_scanin         = dff_tlu_asi_scanout      ;
assign dff_diag_reg_scanin       = dff_stb_w3_scanout       ;
assign dff_lru_data_b_scanin     = dff_diag_reg_scanout     ;
assign dff_new_lru_w_scanin      = dff_lru_data_b_scanout   ;
assign dff_new_lru_w2_scanin     = dff_new_lru_w_scanout    ;
assign dff_update_lru_scanin     = dff_new_lru_w2_scanout   ;
assign dff_sync_inst_w_scanin    = dff_update_lru_scanout   ;
assign dff_st_type_w_scanin      = dff_sync_inst_w_scanout  ;
assign dff_priv_state_e_scanin   = dff_st_type_w_scanout    ;
assign dff_priv_state_m_scanin   = dff_priv_state_e_scanout ;
assign dff_priv_state_b_scanin   = dff_priv_state_m_scanout ;
assign dff_usr_pg_access_b_scanin = dff_priv_state_b_scanout ;
assign dff_excp_b_scanin         = dff_usr_pg_access_b_scanout;
assign dff_wpt_scanin            = dff_excp_b_scanout       ;
assign dff_asi_g_scanin          = dff_wpt_scanout          ;
assign dff_except_scanin         = dff_asi_g_scanout        ;
assign dff_fgu_excp_w_scanin     = dff_except_scanout       ;
assign dff_if_indx_0_scanin      = dff_fgu_excp_w_scanout   ;
assign dff_if_indx_1_scanin      = dff_if_indx_0_scanout    ;
assign dff_if_indx_2_scanin      = dff_if_indx_1_scanout    ;
assign dff_if_indx_3_scanin      = dff_if_indx_2_scanout    ;
assign dff_if_indx_4_scanin      = dff_if_indx_3_scanout    ;
assign dff_if_indx_5_scanin      = dff_if_indx_4_scanout    ;
assign dff_if_indx_6_scanin      = dff_if_indx_5_scanout    ;
assign dff_if_indx_7_scanin      = dff_if_indx_6_scanout    ;
assign dff_way_vld_b_scanin      = dff_if_indx_7_scanout    ;
assign dff_l2miss_scanin         = dff_way_vld_b_scanout    ;
assign dff_pmu_trap_scanin       = dff_l2miss_scanout       ;
assign dff_pwr_mgmt_scanin       = dff_pmu_trap_scanout     ;
assign dff_bist_run_scanin       = dff_pwr_mgmt_scanout     ;
assign dff_bist_in_scanin        = dff_bist_run_scanout     ;
assign dff_bist_fail_scanin      = dff_bist_in_scanout      ;
assign spares_scanin             = dff_bist_fail_scanout    ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_13 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [12:0] fdin;
wire [11:0] so;

  input [12:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [12:0] dout;
  output scan_out;
assign fdin[12:0] = din[12:0];


dff #(13)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[12:0]),
.si({scan_in,so[11:0]}),
.so({so[11:0],scan_out}),
.q(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcc_ctl_msff_ctl_macro__width_20 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [19:0] fdin;
wire [18:0] so;

  input [19:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [19:0] dout;
  output scan_out;
assign fdin[19:0] = din[19:0];


dff #(20)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[19:0]),
.si({scan_in,so[18:0]}),
.so({so[18:0],scan_out}),
.q(dout[19:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_dcc_ctl_spare_ctl_macro__num_9 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire si_8;
wire so_8;
wire spare8_flop_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));

cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_8),
                               .so(so_8),
                               .d(1'b0),
                               .q(spare8_flop_unused));
assign si_8 = so_7;

cl_u1_buf_32x   spare8_buf_32x (.in(1'b1),
                                   .out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare8_nand3_8x_unused));
cl_u1_inv_8x    spare8_inv_8x (.in(1'b1),
                                  .out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_aoi22_4x_unused));
cl_u1_buf_8x    spare8_buf_8x (.in(1'b1),
                                  .out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_oai22_4x_unused));
cl_u1_inv_16x   spare8_inv_16x (.in(1'b1),
                                   .out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare8_nand2_8x_unused));
cl_u1_buf_16x   spare8_buf_16x (.in(1'b1),
                                   .out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare8_nor2_16x_unused));
cl_u1_inv_32x   spare8_inv_32x (.in(1'b1),
                                   .out(spare8_inv_32x_unused));
assign scan_out = so_8;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_dcd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_dcd_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  dca_ld_data_b, 
  dac_byte_one_extend, 
  dac_byte_sel_data, 
  dac_swap7_byte0_l, 
  dac_swap7_byte3_l, 
  dac_swap7_byte4_l, 
  dac_swap7_byte7_l, 
  dac_swap6_byte1_l, 
  dac_swap6_byte2_l, 
  dac_swap6_byte5_l, 
  dac_swap6_byte6_l, 
  dac_swap5_byte1_l, 
  dac_swap5_byte2_l, 
  dac_swap5_byte5_l, 
  dac_swap5_byte6_l, 
  dac_swap4_byte0_l, 
  dac_swap4_byte3_l, 
  dac_swap4_byte4_l, 
  dac_swap4_byte7_l, 
  dac_swap3_byte0_r, 
  dac_swap3_byte3_r, 
  dac_swap3_byte4_r, 
  dac_swap3_byte7_r, 
  dac_swap2_byte1_r, 
  dac_swap2_byte2_r, 
  dac_swap2_byte5_r, 
  dac_swap2_byte6_r, 
  dac_swap1_byte0_r, 
  dac_swap1_byte1_r, 
  dac_swap1_byte2_r, 
  dac_swap1_byte3_r, 
  dac_swap1_byte4_r, 
  dac_swap1_byte5_r, 
  dac_swap1_byte6_r, 
  dac_swap1_byte7_r, 
  dac_swap0_byte0_r, 
  dac_swap0_byte1_r, 
  dac_swap0_byte2_r, 
  dac_swap0_byte3_r, 
  dac_swap0_byte4_r, 
  dac_swap0_byte5_r, 
  dac_swap0_byte6_r, 
  dac_swap0_byte7_r, 
  lsu_exu_ld_data_b, 
  lsu_fgu_fld_data_b, 
  bist_cmp_data, 
  dcd_dca_data_compare, 
  dcs_memref_m, 
  lsu_mmu_va_m, 
  lsu_mmu_va_b);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire clk;
wire [63:0] prealign_load_data;
wire [7:0] byte7;
wire [7:0] byte6;
wire [7:0] byte5;
wire [7:0] byte4;
wire [7:0] byte3;
wire [7:0] byte2;
wire [7:0] byte1;
wire [7:0] byte0;
wire [7:0] align_byte0;
wire [63:0] final_data;
wire [7:0] align_byte1;
wire [7:0] align_byte2;
wire [7:0] align_byte3;
wire [7:0] align_byte4;
wire [7:0] align_byte5;
wire [7:0] align_byte6;
wire [7:0] align_byte7;
wire [1:0] data_compare;
wire [7:0] bist_cmp_data_local;
wire mmu_va_b_lat_scanin;
wire mmu_va_b_lat_scanout;
wire [47:0] va_b;


// globals
input 		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input 		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

// Data sources
input	[63:0]	dca_ld_data_b;		// data from dcache array

// Sign/zero extend controls
input	[7:1]	dac_byte_one_extend;
input	[7:1]	dac_byte_sel_data;

// Byte alignment controls
input		dac_swap7_byte0_l;
input		dac_swap7_byte3_l;
input		dac_swap7_byte4_l;
input		dac_swap7_byte7_l;
input		dac_swap6_byte1_l;
input		dac_swap6_byte2_l;
input		dac_swap6_byte5_l;
input		dac_swap6_byte6_l;
input		dac_swap5_byte1_l;   
input		dac_swap5_byte2_l;   
input		dac_swap5_byte5_l;   
input		dac_swap5_byte6_l;
input		dac_swap4_byte0_l;
input		dac_swap4_byte3_l;
input		dac_swap4_byte4_l;
input		dac_swap4_byte7_l;

input		dac_swap3_byte0_r;
input		dac_swap3_byte3_r;
input		dac_swap3_byte4_r;
input		dac_swap3_byte7_r;
input		dac_swap2_byte1_r;
input		dac_swap2_byte2_r;
input		dac_swap2_byte5_r;
input		dac_swap2_byte6_r;
input		dac_swap1_byte0_r;
input		dac_swap1_byte1_r;
input		dac_swap1_byte2_r;
input		dac_swap1_byte3_r;
input		dac_swap1_byte4_r;
input		dac_swap1_byte5_r;
input		dac_swap1_byte6_r;
input		dac_swap1_byte7_r; 
input		dac_swap0_byte0_r;
input		dac_swap0_byte1_r;
input		dac_swap0_byte2_r;
input		dac_swap0_byte3_r;
input		dac_swap0_byte4_r;
input		dac_swap0_byte5_r;
input		dac_swap0_byte6_r;
input		dac_swap0_byte7_r;

// Outputs to exu and fgu
output	[63:0]	lsu_exu_ld_data_b;
output	[63:0]	lsu_fgu_fld_data_b;

input	[7:0]	bist_cmp_data;
output	[1:0]	dcd_dca_data_compare;

input		dcs_memref_m;
input	[47:0]	lsu_mmu_va_m;
output	[47:0]	lsu_mmu_va_b;

assign se 	= tcu_scan_en;
assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign clk	= l2clk;


assign prealign_load_data[63:0] = dca_ld_data_b[63:0];

//=========================================================================================
//	Alignment of Load Return Data
//=========================================================================================

// All data returning to the register files must be aligned
// and sign extended here.  Formatting occurs in two steps.
// 1st: Swizzle the bytes based on endianess, size, and address.
// 2nd: Pass the data or replace with zero/one extention.
// In the layout, bits should be interleaved to (1) minmize wire
// usage and (2) keep msb's close to the dac block.

// Because the fgu is flipped in the spc floorplan, it's alignment muxes are separate
// so that the mux ordering matches the fgu bit ordering.

assign	byte7[7:0] = prealign_load_data[63:56];
assign	byte6[7:0] = prealign_load_data[55:48];
assign	byte5[7:0] = prealign_load_data[47:40];
assign	byte4[7:0] = prealign_load_data[39:32];
assign	byte3[7:0] = prealign_load_data[31:24];
assign	byte2[7:0] = prealign_load_data[23:16];
assign	byte1[7:0] = prealign_load_data[15:8];
assign	byte0[7:0] = prealign_load_data[7:0];

// INT muxes

// Byte 0.
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 i_swap_byte0       (
	.din0	(byte0[7:0]),
	.din1	(byte1[7:0]),
	.din2	(byte2[7:0]),
	.din3	(byte3[7:0]),
	.din4	(byte4[7:0]),
	.din5	(byte5[7:0]),
	.din6	(byte6[7:0]),
	.din7	(byte7[7:0]),
	.sel0	(dac_swap0_byte0_r),
	.sel1	(dac_swap0_byte1_r),
	.sel2	(dac_swap0_byte2_r),
	.sel3	(dac_swap0_byte3_r),
	.sel4	(dac_swap0_byte4_r),
	.sel5	(dac_swap0_byte5_r),
	.sel6	(dac_swap0_byte6_r),
	.sel7	(dac_swap0_byte7_r),
	.dout	(align_byte0[7:0])
);

// No sign-extension for byte0.  It always has "real" data.
assign final_data[7:0] = align_byte0[7:0];


// Byte 1.
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 i_swap_byte1       (
	.din0	(byte0[7:0]),
	.din1	(byte1[7:0]),
	.din2	(byte2[7:0]),
	.din3	(byte3[7:0]),
	.din4	(byte4[7:0]),
	.din5	(byte5[7:0]),
	.din6	(byte6[7:0]),
	.din7	(byte7[7:0]),
	.sel0	(dac_swap1_byte0_r),
	.sel1	(dac_swap1_byte1_r),
	.sel2	(dac_swap1_byte2_r),
	.sel3	(dac_swap1_byte3_r),
	.sel4	(dac_swap1_byte4_r),
	.sel5	(dac_swap1_byte5_r),
	.sel6	(dac_swap1_byte6_r),
	.sel7	(dac_swap1_byte7_r),
	.dout	(align_byte1[7:0])
);

lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte1       (
	.din0	(align_byte1[7:0]),
	.din1	(8'hff),
	.sel0	(dac_byte_sel_data[1]),
	.sel1	(dac_byte_one_extend[1]),
	.dout	(final_data[15:8])
);


// Byte 2.
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte2       (
	.din0	(byte1[7:0]),
	.din1	(byte2[7:0]),
	.din2	(byte5[7:0]),
	.din3	(byte6[7:0]),
	.sel0	(dac_swap2_byte1_r),
	.sel1	(dac_swap2_byte2_r),
	.sel2	(dac_swap2_byte5_r),
	.sel3	(dac_swap2_byte6_r),
	.dout	(align_byte2[7:0])
);

lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte2       (
	.din0	(align_byte2[7:0]),
	.din1	(8'hff),
	.sel0	(dac_byte_sel_data[2]),
	.sel1	(dac_byte_one_extend[2]),
	.dout	(final_data[23:16])
);


// Byte 3.
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte3       (
	.din0	(byte0[7:0]),
	.din1	(byte3[7:0]),
	.din2	(byte4[7:0]),
	.din3	(byte7[7:0]),
	.sel0	(dac_swap3_byte0_r),
	.sel1	(dac_swap3_byte3_r),
	.sel2	(dac_swap3_byte4_r),
	.sel3	(dac_swap3_byte7_r),
	.dout	(align_byte3[7:0])
);

lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte3       (
	.din0	(align_byte3[7:0]),
	.din1	(8'hff),
	.sel0	(dac_byte_sel_data[3]),
	.sel1	(dac_byte_one_extend[3]),
	.dout	(final_data[31:24])
);


// Byte 4.
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte4       (
	.din0	(byte0[7:0]),
	.din1	(byte3[7:0]),
	.din2	(byte4[7:0]),
	.din3	(byte7[7:0]),
	.sel0	(dac_swap4_byte0_l),
	.sel1	(dac_swap4_byte3_l),
	.sel2	(dac_swap4_byte4_l),
	.sel3	(dac_swap4_byte7_l),
	.dout	(align_byte4[7:0])
);

lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte4       (
	.din0	(align_byte4[7:0]),
	.din1	(8'hff),
	.sel0	(dac_byte_sel_data[4]),
	.sel1	(dac_byte_one_extend[4]),
	.dout	(final_data[39:32])
);


// Byte 5.
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte5       (
	.din0	(byte1[7:0]),
	.din1	(byte2[7:0]),
	.din2	(byte5[7:0]),
	.din3	(byte6[7:0]),
	.sel0	(dac_swap5_byte1_l),
	.sel1	(dac_swap5_byte2_l),
	.sel2	(dac_swap5_byte5_l),
	.sel3	(dac_swap5_byte6_l),
	.dout	(align_byte5[7:0])
);

lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte5       (
	.din0	(align_byte5[7:0]),
	.din1	(8'hff),
	.sel0	(dac_byte_sel_data[5]),
	.sel1	(dac_byte_one_extend[5]),
	.dout	(final_data[47:40])
);


// Byte 6.
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte6       (
	.din0	(byte1[7:0]),
	.din1	(byte2[7:0]),
	.din2	(byte5[7:0]),
	.din3	(byte6[7:0]),
	.sel0	(dac_swap6_byte1_l),
	.sel1	(dac_swap6_byte2_l),
	.sel2	(dac_swap6_byte5_l),
	.sel3	(dac_swap6_byte6_l),
	.dout	(align_byte6[7:0])
);

lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte6       (
	.din0	(align_byte6[7:0]),
	.din1	(8'hff),
	.sel0	(dac_byte_sel_data[6]),
	.sel1	(dac_byte_one_extend[6]),
	.dout	(final_data[55:48])
);


// Byte 7.
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte7       (
	.din0	(byte0[7:0]),
	.din1	(byte3[7:0]),
	.din2	(byte4[7:0]),
	.din3	(byte7[7:0]),
	.sel0	(dac_swap7_byte0_l),
	.sel1	(dac_swap7_byte3_l),
	.sel2	(dac_swap7_byte4_l),
	.sel3	(dac_swap7_byte7_l),
	.dout	(align_byte7[7:0])
);

lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte7       (
	.din0	(align_byte7[7:0]),
	.din1	(8'hff),
	.sel0	(dac_byte_sel_data[7]),
	.sel1	(dac_byte_one_extend[7]),
	.dout	(final_data[63:56])
);


lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 exu_data   (
	.din	(final_data[63:0]),
	.dout	(lsu_exu_ld_data_b[63:0])
);

lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 fgu_data   (
	.din	({align_byte7[7:0],align_byte6[7:0],align_byte5[7:0],align_byte4[7:0],
		  align_byte3[7:0],align_byte2[7:0],align_byte1[7:0],align_byte0[7:0]}),
	.dout	(lsu_fgu_fld_data_b[63:0])
);

///////////
// BIST

lsu_dcd_dp_buff_macro__width_10 cmp_buff  (
	.din	({        data_compare[1:0],bist_cmp_data[7:0]}),
	.dout	({dcd_dca_data_compare[1:0],bist_cmp_data_local[7:0]})
);

lsu_dcd_dp_cmp_macro__width_32 bist_cmp0  (
	.din0	({4{bist_cmp_data_local[7:0]}}),
	.din1	(dca_ld_data_b[63:32]),
	.dout	(data_compare[0])
);

lsu_dcd_dp_cmp_macro__width_32 bist_cmp1  (
	.din0	({4{bist_cmp_data_local[7:0]}}),
	.din1	(dca_ld_data_b[31:0]),
	.dout	(data_compare[1])
);

//////////////////////////////
// Flop for VA to send to MMU
lsu_dcd_dp_msff_macro__minbuff_1__stack_48c__width_48 mmu_va_b_lat   (
	.scan_in(mmu_va_b_lat_scanin),
	.scan_out(mmu_va_b_lat_scanout),
	.en	(dcs_memref_m),
	.din	(lsu_mmu_va_m[47:0]),
	.dout	(va_b[47:0]),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcd_dp_buff_macro__dbuff_32x__stack_48c__width_48 mmu_va_b_buf    (
	.din	(va_b[47:0]),
	.dout	(lsu_mmu_va_b[47:0])
);


// fixscan start:
assign mmu_va_b_lat_scanin       = scan_in                  ;
assign scan_out                  = mmu_va_b_lat_scanout     ;
// fixscan end:
endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
  input [7:0] din0;
  input sel0;
  input [7:0] din1;
  input sel1;
  input [7:0] din2;
  input sel2;
  input [7:0] din3;
  input sel3;
  input [7:0] din4;
  input sel4;
  input [7:0] din5;
  input sel5;
  input [7:0] din6;
  input sel6;
  input [7:0] din7;
  input sel7;
  output [7:0] dout;


mux8s #(8)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .sel3(sel3),
  .sel4(sel4),
  .sel5(sel5),
  .sel6(sel6),
  .sel7(sel7),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
  .in4(din4[7:0]),
  .in5(din5[7:0]),
  .in6(din6[7:0]),
  .in7(din7[7:0]),
.dout(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [7:0] din0;
  input sel0;
  input [7:0] din1;
  input sel1;
  output [7:0] dout;


mux2s #(8)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
  input [7:0] din0;
  input sel0;
  input [7:0] din1;
  input sel1;
  input [7:0] din2;
  input sel2;
  input [7:0] din3;
  input sel3;
  output [7:0] dout;


mux4s #(8)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .sel2(sel2),
  .sel3(sel3),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
.dout(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcd_dp_buff_macro__width_10 (
  din, 
  dout);
  input [9:0] din;
  output [9:0] dout;


buff #(10)  d0_0 (
.in(din[9:0]),
.out(dout[9:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_dcd_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcd_dp_msff_macro__minbuff_1__stack_48c__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcd_dp_buff_macro__dbuff_32x__stack_48c__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_dcp_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_dcp_dp (
  lmd_fill_data_e, 
  dcc_parity_invert, 
  mbi_run, 
  mbi_wdata, 
  dcp_fill_data_e, 
  dcp_parity);
wire [15:0] parity;
wire [15:0] parity_e;


input	[127:0]	lmd_fill_data_e;
input	[7:0]	dcc_parity_invert;

input		mbi_run;
input	[7:0]	mbi_wdata;

output	[127:0]	dcp_fill_data_e;
output	[15:0]	dcp_parity;

// Mux in BIST data

lsu_dcp_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__width_64 bist_dmux0     (
	.din0	({8{mbi_wdata[7:0]}}),
	.din1	(lmd_fill_data_e[127:64]),
	.sel0	(mbi_run),
	.dout	(dcp_fill_data_e[127:64])
);

lsu_dcp_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__width_64 bist_dmux1     (
	.din0	({8{mbi_wdata[7:0]}}),
	.din1	(lmd_fill_data_e[63:0]),
	.sel0	(mbi_run),
	.dout	(dcp_fill_data_e[63:0])
);

////////////////////////////////////////////////////////////////////////////////
// Parity generation
////////////////////////////////////////////////////////////////////////////////

lsu_dcp_dp_prty_macro__width_8 prty_b00  (
	.din	(lmd_fill_data_e[7:0]),
	.dout	(parity[0])
);
lsu_dcp_dp_prty_macro__width_8 prty_b01  (
	.din	(lmd_fill_data_e[15:8]),
	.dout	(parity[1])
);
lsu_dcp_dp_prty_macro__width_8 prty_b02  (
	.din	(lmd_fill_data_e[23:16]),
	.dout	(parity[2])
);
lsu_dcp_dp_prty_macro__width_8 prty_b03  (
	.din	(lmd_fill_data_e[31:24]),
	.dout	(parity[3])
);
lsu_dcp_dp_prty_macro__width_8 prty_b04  (
	.din	(lmd_fill_data_e[39:32]),
	.dout	(parity[4])
);
lsu_dcp_dp_prty_macro__width_8 prty_b05  (
	.din	(lmd_fill_data_e[47:40]),
	.dout	(parity[5])
);
lsu_dcp_dp_prty_macro__width_8 prty_b06  (
	.din	(lmd_fill_data_e[55:48]),
	.dout	(parity[6])
);
lsu_dcp_dp_prty_macro__width_8 prty_b07  (
	.din	(lmd_fill_data_e[63:56]),
	.dout	(parity[7])
);
lsu_dcp_dp_prty_macro__width_8 prty_b08  (
	.din	(lmd_fill_data_e[71:64]),
	.dout	(parity[8])
);
lsu_dcp_dp_prty_macro__width_8 prty_b09  (
	.din	(lmd_fill_data_e[79:72]),
	.dout	(parity[9])
);
lsu_dcp_dp_prty_macro__width_8 prty_b10  (
	.din	(lmd_fill_data_e[87:80]),
	.dout	(parity[10])
);
lsu_dcp_dp_prty_macro__width_8 prty_b11  (
	.din	(lmd_fill_data_e[95:88]),
	.dout	(parity[11])
);
lsu_dcp_dp_prty_macro__width_8 prty_b12  (
	.din	(lmd_fill_data_e[103:96]),
	.dout	(parity[12])
);
lsu_dcp_dp_prty_macro__width_8 prty_b13  (
	.din	(lmd_fill_data_e[111:104]),
	.dout	(parity[13])
);
lsu_dcp_dp_prty_macro__width_8 prty_b14  (
	.din	(lmd_fill_data_e[119:112]),
	.dout	(parity[14])
);
lsu_dcp_dp_prty_macro__width_8 prty_b15  (
	.din	(lmd_fill_data_e[127:120]),
	.dout	(parity[15])
);

////////////////////////////////////////////////////////////////////////////////
// Error injection
////////////////////////////////////////////////////////////////////////////////

lsu_dcp_dp_xor_macro__stack_16l__width_16 error_inj   (
	.din0	(parity[15:0]),
	.din1	({dcc_parity_invert[7:0],dcc_parity_invert[7:0]}),
	.dout	(parity_e[15:0])
);

////////////////////////////////////////////////////////////////////////////////
// Mux in BIST data
// NOTE: If timing is too tight, this mux could be removed.  It would mean that
// the bist engine doesn't have direct control over the parity bits.
////////////////////////////////////////////////////////////////////////////////

lsu_dcp_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_16l__width_16 bist_pmux      (
	.din0	({2{mbi_wdata[7:0]}}),
	.din1	(parity_e[15:0]),
	.sel0	(mbi_run),
	.dout	(dcp_parity[15:0])
);

endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcp_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(64)  d0_0 (
  .sel(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_dcp_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module lsu_dcp_dp_xor_macro__stack_16l__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output [15:0] dout;


xor2 #(16)  d0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcp_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_16l__width_16 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [15:0] din0;
  input [15:0] din1;
  input sel0;
  output [15:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(16)  d0_0 (
  .sel(psel1),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
.dout(dout[15:0])
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_dcs_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_dcs_dp (
  l2clk, 
  scan_in, 
  wmr_scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk_wmr, 
  spc_aclk, 
  spc_bclk, 
  lb_scan_en_wmr, 
  scan_out, 
  wmr_scan_out, 
  const_cpuid, 
  dec_lsu_tid0_d, 
  dec_lsu_tid1_d, 
  dec_lsu_tg_d, 
  dcc_ld_inst_unqual_e, 
  dcc_ctxt_tid0_d, 
  dcc_ctxt_tid1_d, 
  dcc_ctxt_tg_d, 
  dcc_tid_m, 
  dcc_tid_b, 
  dcc_asi_reload_sel, 
  dcc_wr_wtchpt, 
  dcc_wr_lsu_ctl_reg, 
  dcc_wr_pwr_mgmt, 
  dcc_rd_lsu_ctl_reg_b, 
  dcc_rd_diag_reg_b, 
  dcc_rd_core_id_b, 
  dcc_rd_intr_id_b, 
  dcc_rd_rhs_asi_b, 
  dcc_rd_diag_dca_b, 
  dcc_rd_error_inj_b, 
  dcc_rd_pwr_mgmt_b, 
  dcc_wr_error_inj_w, 
  dcc_p0ctxt_rd_m, 
  dcc_p1ctxt_rd_m, 
  dcc_s0ctxt_rd_m, 
  dcc_s1ctxt_rd_m, 
  dcc_pid_rd_m, 
  dcc_wtchpt_sel_m, 
  dcc_wtchpt_rd_b, 
  dcc_pctxt_sel_e, 
  dcc_sctxt_sel_e, 
  dcc_dcs_memref_e, 
  dcc_direct_map, 
  dcc_asi_store_b, 
  dcc_asi_load_m, 
  dcc_asi_load_b, 
  lsu_ifu_direct_map, 
  asc_wr_p0ctxt, 
  asc_wr_p1ctxt, 
  asc_wr_s0ctxt, 
  asc_wr_s1ctxt, 
  asc_wr_pid, 
  asc_wrasi, 
  tlu_asi_0, 
  tlu_asi_1, 
  tlu_lsu_clear_ctl_reg_, 
  dca_rparity_b, 
  sbd_st_data_b, 
  tgd_ldxa_asi_data_b, 
  asd_asi_data, 
  lsu_va_m, 
  lsu_va_b, 
  dcs_asi_d, 
  dcs_context0_e, 
  dcs_context1_e, 
  dcs_pid_e, 
  dcs_ldxa_asi_data_w, 
  dcs_watchpoint_m, 
  dcs_dc_enable, 
  dcs_wpt_mask_m, 
  dcs_wpt_enable_m, 
  dcs_wpt_mode_m, 
  dcs_dmmu_enable_d, 
  lsu_immu_enable, 
  lsu_ic_enable, 
  lsu_context_b, 
  lsu_asi_error_inject, 
  lsu_asi_pwr_mgmt, 
  dcs_memref_m);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire siclk_wmr;
wire scan_en_wmr;
wire dff_in_data_scanin;
wire dff_in_data_scanout;
wire [47:0] wsr_data_w;
wire [12:0] asi_data_in;
wire [7:0] reload_asi_0;
wire [7:0] asi_state0;
wire [7:0] asi_state0_in;
wire [7:0] asi_state1;
wire [7:0] asi_state1_in;
wire [7:0] asi_state2;
wire [7:0] asi_state2_in;
wire [7:0] asi_state3;
wire [7:0] asi_state3_in;
wire [7:0] reload_asi_1;
wire [7:0] asi_state4;
wire [7:0] asi_state4_in;
wire [7:0] asi_state5;
wire [7:0] asi_state5_in;
wire [7:0] asi_state6;
wire [7:0] asi_state6_in;
wire [7:0] asi_state7;
wire [7:0] asi_state7_in;
wire [7:0] wr_p1ctxt_;
wire [7:0] wr_s1ctxt_;
wire [7:0] wr_p0ctxt_;
wire [7:0] wr_s0ctxt_;
wire [7:0] wr_pid_;
wire [7:0] wr_p1ctxt;
wire [7:0] wr_s1ctxt;
wire [7:0] wr_p0ctxt;
wire [7:0] wr_s0ctxt;
wire [7:0] wr_pid;
wire [12:0] p0ctxt_0;
wire [12:0] p0ctxt_0_in;
wire [12:0] p0ctxt_1;
wire [12:0] p0ctxt_1_in;
wire [12:0] p0ctxt_2;
wire [12:0] p0ctxt_2_in;
wire [12:0] p0ctxt_3;
wire [12:0] p0ctxt_3_in;
wire [12:0] p0ctxt_4;
wire [12:0] p0ctxt_4_in;
wire [12:0] p0ctxt_5;
wire [12:0] p0ctxt_5_in;
wire [12:0] p0ctxt_6;
wire [12:0] p0ctxt_6_in;
wire [12:0] p0ctxt_7;
wire [12:0] p0ctxt_7_in;
wire [12:0] p1ctxt_0;
wire [12:0] p1ctxt_0_in;
wire [12:0] p1ctxt_1;
wire [12:0] p1ctxt_1_in;
wire [12:0] p1ctxt_2;
wire [12:0] p1ctxt_2_in;
wire [12:0] p1ctxt_3;
wire [12:0] p1ctxt_3_in;
wire [12:0] p1ctxt_4;
wire [12:0] p1ctxt_4_in;
wire [12:0] p1ctxt_5;
wire [12:0] p1ctxt_5_in;
wire [12:0] p1ctxt_6;
wire [12:0] p1ctxt_6_in;
wire [12:0] p1ctxt_7;
wire [12:0] p1ctxt_7_in;
wire [12:0] s0ctxt_0;
wire [12:0] s0ctxt_0_in;
wire [12:0] s0ctxt_1;
wire [12:0] s0ctxt_1_in;
wire [12:0] s0ctxt_2;
wire [12:0] s0ctxt_2_in;
wire [12:0] s0ctxt_3;
wire [12:0] s0ctxt_3_in;
wire [12:0] s0ctxt_4;
wire [12:0] s0ctxt_4_in;
wire [12:0] s0ctxt_5;
wire [12:0] s0ctxt_5_in;
wire [12:0] s0ctxt_6;
wire [12:0] s0ctxt_6_in;
wire [12:0] s0ctxt_7;
wire [12:0] s0ctxt_7_in;
wire [12:0] s1ctxt_0;
wire [12:0] s1ctxt_0_in;
wire [12:0] s1ctxt_1;
wire [12:0] s1ctxt_1_in;
wire [12:0] s1ctxt_2;
wire [12:0] s1ctxt_2_in;
wire [12:0] s1ctxt_3;
wire [12:0] s1ctxt_3_in;
wire [12:0] s1ctxt_4;
wire [12:0] s1ctxt_4_in;
wire [12:0] s1ctxt_5;
wire [12:0] s1ctxt_5_in;
wire [12:0] s1ctxt_6;
wire [12:0] s1ctxt_6_in;
wire [12:0] s1ctxt_7;
wire [12:0] s1ctxt_7_in;
wire [2:0] pid0;
wire [2:0] pid0_in;
wire [2:0] pid1;
wire [2:0] pid1_in;
wire [2:0] pid2;
wire [2:0] pid2_in;
wire [2:0] pid3;
wire [2:0] pid3_in;
wire [2:0] pid4;
wire [2:0] pid4_in;
wire [2:0] pid5;
wire [2:0] pid5_in;
wire [2:0] pid6;
wire [2:0] pid6_in;
wire [2:0] pid7;
wire [2:0] pid7_in;
wire dff_state0_wmr_scanin;
wire dff_state0_wmr_scanout;
wire [62:0] state0;
wire dff_state1_wmr_scanin;
wire dff_state1_wmr_scanout;
wire [62:0] state1;
wire dff_state2_wmr_scanin;
wire dff_state2_wmr_scanout;
wire [62:0] state2;
wire dff_state3_wmr_scanin;
wire dff_state3_wmr_scanout;
wire [62:0] state3;
wire dff_state4_wmr_scanin;
wire dff_state4_wmr_scanout;
wire [62:0] state4;
wire dff_state5_wmr_scanin;
wire dff_state5_wmr_scanout;
wire [62:0] state5;
wire dff_state6_wmr_scanin;
wire dff_state6_wmr_scanout;
wire [62:0] state6;
wire dff_state7_wmr_scanin;
wire dff_state7_wmr_scanout;
wire [62:0] state7;
wire [62:0] state_tg0;
wire [62:0] state_tg1;
wire [7:0] dmmu_enable;
wire dmmu_enable_tg0;
wire dmmu_enable_tg1;
wire dff_mx_ctxt_scanin;
wire dff_mx_ctxt_scanout;
wire [12:0] dcs_p1ctxt_e;
wire [12:0] dcs_s1ctxt_e;
wire [12:0] dcs_p0ctxt_e;
wire [12:0] dcs_s0ctxt_e;
wire [12:0] context0_e;
wire [12:0] context1_e;
wire dff_context_m_scanin;
wire dff_context_m_scanout;
wire memref_m;
wire [12:0] dcs_context0_m;
wire dff_context_b_scanin;
wire dff_context_b_scanout;
wire [4:0] lsu_ctl_reg_m;
wire [12:0] dcs_context0_b;
wire [1:0] dcs_wpt_mode_b;
wire [7:0] dcs_wpt_mask_b;
wire [1:0] dcs_wpt_enable_b;
wire [4:0] lsu_ctl_reg_b;
wire dff_state_m_scanin;
wire dff_state_m_scanout;
wire [2:0] dcs_pid_m;
wire [12:0] dcs_p1ctxt_m;
wire [12:0] dcs_s1ctxt_m;
wire [12:0] dcs_p0ctxt_m;
wire [12:0] dcs_s0ctxt_m;
wire [12:0] ldxa_asi_data_m;
wire dff_stg_b_scanin;
wire dff_stg_b_scanout;
wire [47:3] watchpoint_m;
wire [46:0] stg_b;
wire [12:0] ldxa_asi_data_b;
wire [47:3] watchpoint_b;
wire [5:0] core_id;
wire [5:0] max_core_id;
wire [5:0] max_strand_id;
wire [63:0] ldxa_asi_data_b_2;
wire dff_asi_w_scanin;
wire dff_asi_w_scanout;
wire dff_watchpoint_0_wmr_scanin;
wire dff_watchpoint_0_wmr_scanout;
wire [47:3] watchpoint0;
wire dff_watchpoint_1_wmr_scanin;
wire dff_watchpoint_1_wmr_scanout;
wire [47:3] watchpoint1;
wire dff_watchpoint_2_wmr_scanin;
wire dff_watchpoint_2_wmr_scanout;
wire [47:3] watchpoint2;
wire dff_watchpoint_3_wmr_scanin;
wire dff_watchpoint_3_wmr_scanout;
wire [47:3] watchpoint3;
wire dff_watchpoint_4_wmr_scanin;
wire dff_watchpoint_4_wmr_scanout;
wire [47:3] watchpoint4;
wire dff_watchpoint_5_wmr_scanin;
wire dff_watchpoint_5_wmr_scanout;
wire [47:3] watchpoint5;
wire dff_watchpoint_6_wmr_scanin;
wire dff_watchpoint_6_wmr_scanout;
wire [47:3] watchpoint6;
wire dff_watchpoint_7_wmr_scanin;
wire dff_watchpoint_7_wmr_scanout;
wire [47:3] watchpoint7;
wire [47:3] watchpoint_mx_m;
wire [16:0] ctl_reg0_in;
wire [16:0] ctl_reg1_in;
wire [16:0] ctl_reg2_in;
wire [16:0] ctl_reg3_in;
wire [16:0] ctl_reg4_in;
wire [16:0] ctl_reg5_in;
wire [16:0] ctl_reg6_in;
wire [16:0] ctl_reg7_in;
wire dff_lsu_ctl_0_scanin;
wire dff_lsu_ctl_0_scanout;
wire [1:0] wpt_mode_0;
wire [7:0] wpt_mask_0;
wire [1:0] wpt_enable_0;
wire [7:0] spec_enable;
wire [7:0] immu_enable;
wire [7:0] dc_enable;
wire [7:0] ic_enable;
wire dff_lsu_ctl_1_scanin;
wire dff_lsu_ctl_1_scanout;
wire [1:0] wpt_mode_1;
wire [7:0] wpt_mask_1;
wire [1:0] wpt_enable_1;
wire dff_lsu_ctl_2_scanin;
wire dff_lsu_ctl_2_scanout;
wire [1:0] wpt_mode_2;
wire [7:0] wpt_mask_2;
wire [1:0] wpt_enable_2;
wire dff_lsu_ctl_3_scanin;
wire dff_lsu_ctl_3_scanout;
wire [1:0] wpt_mode_3;
wire [7:0] wpt_mask_3;
wire [1:0] wpt_enable_3;
wire dff_lsu_ctl_4_scanin;
wire dff_lsu_ctl_4_scanout;
wire [1:0] wpt_mode_4;
wire [7:0] wpt_mask_4;
wire [1:0] wpt_enable_4;
wire dff_lsu_ctl_5_scanin;
wire dff_lsu_ctl_5_scanout;
wire [1:0] wpt_mode_5;
wire [7:0] wpt_mask_5;
wire [1:0] wpt_enable_5;
wire dff_lsu_ctl_6_scanin;
wire dff_lsu_ctl_6_scanout;
wire [1:0] wpt_mode_6;
wire [7:0] wpt_mask_6;
wire [1:0] wpt_enable_6;
wire dff_lsu_ctl_7_scanin;
wire dff_lsu_ctl_7_scanout;
wire [1:0] wpt_mode_7;
wire [7:0] wpt_mask_7;
wire [1:0] wpt_enable_7;
wire [16:0] lsu_ctl_mx;
wire dff_error_inject_scanin;
wire dff_error_inject_scanout;
wire [31:0] asi_error_inject;
wire dff_pwr_mgmt_scanin;
wire dff_pwr_mgmt_scanout;
wire [15:0] asi_pwr_mgmt;
wire dff_va_b_scanin;
wire dff_va_b_scanout;
wire [20:0] va_b;


input		l2clk;
input 		scan_in;
input 		wmr_scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk_wmr;
input 		spc_aclk;
input 		spc_bclk;
input		lb_scan_en_wmr;
output		scan_out;
output		wmr_scan_out;

input	[2:0]	const_cpuid;

input	[1:0]	dec_lsu_tid0_d;
input	[1:0]	dec_lsu_tid1_d;
input		dec_lsu_tg_d;

input		dcc_ld_inst_unqual_e;
input	[1:0]	dcc_ctxt_tid0_d;
input	[1:0]	dcc_ctxt_tid1_d;
input		dcc_ctxt_tg_d;
input	[2:0]	dcc_tid_m;
input	[2:0]	dcc_tid_b;
input	[7:0]	dcc_asi_reload_sel;
input	[7:0]	dcc_wr_wtchpt;
input	[7:0]	dcc_wr_lsu_ctl_reg;
input		dcc_wr_pwr_mgmt;
input		dcc_rd_lsu_ctl_reg_b;
input		dcc_rd_diag_reg_b;
input		dcc_rd_core_id_b;
input		dcc_rd_intr_id_b;
input		dcc_rd_rhs_asi_b;
input		dcc_rd_diag_dca_b;
input		dcc_rd_error_inj_b;
input		dcc_rd_pwr_mgmt_b;
input		dcc_wr_error_inj_w;
input		dcc_p0ctxt_rd_m;
input		dcc_p1ctxt_rd_m;
input		dcc_s0ctxt_rd_m;
input		dcc_s1ctxt_rd_m;
input		dcc_pid_rd_m;
input		dcc_wtchpt_sel_m;
input		dcc_wtchpt_rd_b;
input		dcc_pctxt_sel_e;
input		dcc_sctxt_sel_e;
input		dcc_dcs_memref_e;
input		dcc_direct_map;		// diag read only
input		dcc_asi_store_b;
input		dcc_asi_load_m;
input		dcc_asi_load_b;
input		lsu_ifu_direct_map;	// diag read only

input	[7:0]	asc_wr_p0ctxt;
input	[7:0]	asc_wr_p1ctxt;
input	[7:0]	asc_wr_s0ctxt;
input	[7:0]	asc_wr_s1ctxt;
input	[7:0]	asc_wr_pid;
input	[7:0]	asc_wrasi;

input	[7:0]	tlu_asi_0;	// ASI reload data
input	[7:0]	tlu_asi_1;
input	[7:0]	tlu_lsu_clear_ctl_reg_;

input	[7:0]	dca_rparity_b;

input	[47:0]	sbd_st_data_b;

input	[63:0]	tgd_ldxa_asi_data_b;

input	[12:0]	asd_asi_data;

input	[20:0]	lsu_va_m;
output	[20:0]	lsu_va_b;

output	[7:0]	dcs_asi_d;

output	[12:0]	dcs_context0_e;
output	[12:0]	dcs_context1_e;
output	[2:0]	dcs_pid_e;
output	[63:0]	dcs_ldxa_asi_data_w;
output	[47:3]	dcs_watchpoint_m;
output	[7:0]	dcs_dc_enable;
output	[7:0]	dcs_wpt_mask_m;
output	[1:0]	dcs_wpt_enable_m;
output	[1:0]	dcs_wpt_mode_m;
output		dcs_dmmu_enable_d;

output	[7:0]	lsu_immu_enable;
output	[7:0]	lsu_ic_enable;
output	[12:0]	lsu_context_b;
output	[31:0]	lsu_asi_error_inject;
output	[15:0]	lsu_asi_pwr_mgmt;
output		dcs_memref_m;

// scan renames
assign stop = 1'b0;
// end scan

lsu_dcs_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_6 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk,spc_aclk_wmr,lb_scan_en_wmr}),
	.dout({se,pce_ov,siclk,soclk,siclk_wmr,scan_en_wmr})
);

lsu_dcs_dp_msff_macro__left_16__stack_64c__width_48 dff_in_data   (
	.scan_in(dff_in_data_scanin),
	.scan_out(dff_in_data_scanout),
	.din	(sbd_st_data_b[47:0]),
	.dout	(wsr_data_w[47:0]),
	.clk	(l2clk),
	.en	(dcc_asi_store_b),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// These nets have a high internal load so buffer them off.
lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__width_13 asi_data_buf  (
	.din	(asd_asi_data[12:0]),
	.dout	(asi_data_in[12:0])
);

////////////////////////////////////////////////////////////////////////////////
// ASI muxes

lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state0      (
	.din0	(reload_asi_0[7:0]),
	.din1	(asi_data_in[7:0]),
	.din2	(asi_state0[7:0]),
	.sel0	(dcc_asi_reload_sel[0]),
	.sel1	(asc_wrasi[0]),
	.dout	(asi_state0_in[7:0])
);
lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state1      (
	.din0	(reload_asi_0[7:0]),
	.din1	(asi_data_in[7:0]),
	.din2	(asi_state1[7:0]),
	.sel0	(dcc_asi_reload_sel[1]),
	.sel1	(asc_wrasi[1]),
	.dout	(asi_state1_in[7:0])
);
lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state2      (
	.din0	(reload_asi_0[7:0]),
	.din1	(asi_data_in[7:0]),
	.din2	(asi_state2[7:0]),
	.sel0	(dcc_asi_reload_sel[2]),
	.sel1	(asc_wrasi[2]),
	.dout	(asi_state2_in[7:0])
);
lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state3      (
	.din0	(reload_asi_0[7:0]),
	.din1	(asi_data_in[7:0]),
	.din2	(asi_state3[7:0]),
	.sel0	(dcc_asi_reload_sel[3]),
	.sel1	(asc_wrasi[3]),
	.dout	(asi_state3_in[7:0])
);
lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state4      (
	.din0	(reload_asi_1[7:0]),
	.din1	(asi_data_in[7:0]),
	.din2	(asi_state4[7:0]),
	.sel0	(dcc_asi_reload_sel[4]),
	.sel1	(asc_wrasi[4]),
	.dout	(asi_state4_in[7:0])
);
lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state5      (
	.din0	(reload_asi_1[7:0]),
	.din1	(asi_data_in[7:0]),
	.din2	(asi_state5[7:0]),
	.sel0	(dcc_asi_reload_sel[5]),
	.sel1	(asc_wrasi[5]),
	.dout	(asi_state5_in[7:0])
);
lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state6      (
	.din0	(reload_asi_1[7:0]),
	.din1	(asi_data_in[7:0]),
	.din2	(asi_state6[7:0]),
	.sel0	(dcc_asi_reload_sel[6]),
	.sel1	(asc_wrasi[6]),
	.dout	(asi_state6_in[7:0])
);
lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state7      (
	.din0	(reload_asi_1[7:0]),
	.din1	(asi_data_in[7:0]),
	.din2	(asi_state7[7:0]),
	.sel0	(dcc_asi_reload_sel[7]),
	.sel1	(asc_wrasi[7]),
	.dout	(asi_state7_in[7:0])
);

// Invert/buffer select lines for aomuxes
lsu_dcs_dp_inv_macro__width_10 inv_sel0  (
	.din	({asc_wr_p1ctxt [0],asc_wr_s1ctxt [0],asc_wr_p0ctxt [0],asc_wr_s0ctxt [0],asc_wr_pid [0],
		      wr_p1ctxt_[0],    wr_s1ctxt_[0],    wr_p0ctxt_[0],    wr_s0ctxt_[0],    wr_pid_[0]}),
	.dout	({    wr_p1ctxt_[0],    wr_s1ctxt_[0],    wr_p0ctxt_[0],    wr_s0ctxt_[0],    wr_pid_[0],
		      wr_p1ctxt [0],    wr_s1ctxt [0],    wr_p0ctxt [0],    wr_s0ctxt [0],     wr_pid[0]})
);
lsu_dcs_dp_inv_macro__width_10 inv_sel1  (
	.din	({asc_wr_p1ctxt [1],asc_wr_s1ctxt [1],asc_wr_p0ctxt [1],asc_wr_s0ctxt [1],asc_wr_pid [1],
		      wr_p1ctxt_[1],    wr_s1ctxt_[1],    wr_p0ctxt_[1],    wr_s0ctxt_[1],    wr_pid_[1]}),
	.dout	({    wr_p1ctxt_[1],    wr_s1ctxt_[1],    wr_p0ctxt_[1],    wr_s0ctxt_[1],    wr_pid_[1],
		      wr_p1ctxt [1],    wr_s1ctxt [1],    wr_p0ctxt [1],    wr_s0ctxt [1],     wr_pid[1]})
);
lsu_dcs_dp_inv_macro__width_10 inv_sel2  (
	.din	({asc_wr_p1ctxt [2],asc_wr_s1ctxt [2],asc_wr_p0ctxt [2],asc_wr_s0ctxt [2],asc_wr_pid [2],
		      wr_p1ctxt_[2],    wr_s1ctxt_[2],    wr_p0ctxt_[2],    wr_s0ctxt_[2],    wr_pid_[2]}),
	.dout	({    wr_p1ctxt_[2],    wr_s1ctxt_[2],    wr_p0ctxt_[2],    wr_s0ctxt_[2],    wr_pid_[2],
		      wr_p1ctxt [2],    wr_s1ctxt [2],    wr_p0ctxt [2],    wr_s0ctxt [2],     wr_pid[2]})
);
lsu_dcs_dp_inv_macro__width_10 inv_sel3  (
	.din	({asc_wr_p1ctxt [3],asc_wr_s1ctxt [3],asc_wr_p0ctxt [3],asc_wr_s0ctxt [3],asc_wr_pid [3],
		      wr_p1ctxt_[3],    wr_s1ctxt_[3],    wr_p0ctxt_[3],    wr_s0ctxt_[3],    wr_pid_[3]}),
	.dout	({    wr_p1ctxt_[3],    wr_s1ctxt_[3],    wr_p0ctxt_[3],    wr_s0ctxt_[3],    wr_pid_[3],
		      wr_p1ctxt [3],    wr_s1ctxt [3],    wr_p0ctxt [3],    wr_s0ctxt [3],     wr_pid[3]})
);
lsu_dcs_dp_inv_macro__width_10 inv_sel4  (
	.din	({asc_wr_p1ctxt [4],asc_wr_s1ctxt [4],asc_wr_p0ctxt [4],asc_wr_s0ctxt [4],asc_wr_pid [4],
		      wr_p1ctxt_[4],    wr_s1ctxt_[4],    wr_p0ctxt_[4],    wr_s0ctxt_[4],    wr_pid_[4]}),
	.dout	({    wr_p1ctxt_[4],    wr_s1ctxt_[4],    wr_p0ctxt_[4],    wr_s0ctxt_[4],    wr_pid_[4],
		      wr_p1ctxt [4],    wr_s1ctxt [4],    wr_p0ctxt [4],    wr_s0ctxt [4],     wr_pid[4]})
);
lsu_dcs_dp_inv_macro__width_10 inv_sel5  (
	.din	({asc_wr_p1ctxt [5],asc_wr_s1ctxt [5],asc_wr_p0ctxt [5],asc_wr_s0ctxt [5],asc_wr_pid [5],
		      wr_p1ctxt_[5],    wr_s1ctxt_[5],    wr_p0ctxt_[5],    wr_s0ctxt_[5],    wr_pid_[5]}),
	.dout	({    wr_p1ctxt_[5],    wr_s1ctxt_[5],    wr_p0ctxt_[5],    wr_s0ctxt_[5],    wr_pid_[5],
		      wr_p1ctxt [5],    wr_s1ctxt [5],    wr_p0ctxt [5],    wr_s0ctxt [5],     wr_pid[5]})
);
lsu_dcs_dp_inv_macro__width_10 inv_sel6  (
	.din	({asc_wr_p1ctxt [6],asc_wr_s1ctxt [6],asc_wr_p0ctxt [6],asc_wr_s0ctxt [6],asc_wr_pid [6],
		      wr_p1ctxt_[6],    wr_s1ctxt_[6],    wr_p0ctxt_[6],    wr_s0ctxt_[6],    wr_pid_[6]}),
	.dout	({    wr_p1ctxt_[6],    wr_s1ctxt_[6],    wr_p0ctxt_[6],    wr_s0ctxt_[6],    wr_pid_[6],
		      wr_p1ctxt [6],    wr_s1ctxt [6],    wr_p0ctxt [6],    wr_s0ctxt [6],     wr_pid[6]})
);
lsu_dcs_dp_inv_macro__width_10 inv_sel7  (
	.din	({asc_wr_p1ctxt [7],asc_wr_s1ctxt [7],asc_wr_p0ctxt [7],asc_wr_s0ctxt [7],asc_wr_pid [7],
		      wr_p1ctxt_[7],    wr_s1ctxt_[7],    wr_p0ctxt_[7],    wr_s0ctxt_[7],    wr_pid_[7]}),
	.dout	({    wr_p1ctxt_[7],    wr_s1ctxt_[7],    wr_p0ctxt_[7],    wr_s0ctxt_[7],    wr_pid_[7],
		      wr_p1ctxt [7],    wr_s1ctxt [7],    wr_p0ctxt [7],    wr_s0ctxt [7],     wr_pid[7]})
);

// Primary context 0 muxes
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_0      (
	.din0	(asi_data_in[12:0]),
	.din1	(p0ctxt_0[12:0]),
	.sel0	(wr_p0ctxt[0]),
	.sel1	(wr_p0ctxt_[0]),
	.dout	(p0ctxt_0_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_1      (
	.din0	(asi_data_in[12:0]),
	.din1	(p0ctxt_1[12:0]),
	.sel0	(wr_p0ctxt[1]),
	.sel1	(wr_p0ctxt_[1]),
	.dout	(p0ctxt_1_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_2      (
	.din0	(asi_data_in[12:0]),
	.din1	(p0ctxt_2[12:0]),
	.sel0	(wr_p0ctxt[2]),
	.sel1	(wr_p0ctxt_[2]),
	.dout	(p0ctxt_2_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_3      (
	.din0	(asi_data_in[12:0]),
	.din1	(p0ctxt_3[12:0]),
	.sel0	(wr_p0ctxt[3]),
	.sel1	(wr_p0ctxt_[3]),
	.dout	(p0ctxt_3_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_4      (
	.din0	(asi_data_in[12:0]),
	.din1	(p0ctxt_4[12:0]),
	.sel0	(wr_p0ctxt[4]),
	.sel1	(wr_p0ctxt_[4]),
	.dout	(p0ctxt_4_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_5      (
	.din0	(asi_data_in[12:0]),
	.din1	(p0ctxt_5[12:0]),
	.sel0	(wr_p0ctxt[5]),
	.sel1	(wr_p0ctxt_[5]),
	.dout	(p0ctxt_5_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_6      (
	.din0	(asi_data_in[12:0]),
	.din1	(p0ctxt_6[12:0]),
	.sel0	(wr_p0ctxt[6]),
	.sel1	(wr_p0ctxt_[6]),
	.dout	(p0ctxt_6_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_7      (
	.din0	(asi_data_in[12:0]),
	.din1	(p0ctxt_7[12:0]),
	.sel0	(wr_p0ctxt[7]),
	.sel1	(wr_p0ctxt_[7]),
	.dout	(p0ctxt_7_in[12:0])
);

// Primary context 1 muxes
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_0      (
	.din0	(asi_data_in[12:0]),
	.din1	(p1ctxt_0[12:0]),
	.sel0	(wr_p1ctxt[0]),
	.sel1	(wr_p1ctxt_[0]),
	.dout	(p1ctxt_0_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_1      (
	.din0	(asi_data_in[12:0]),
	.din1	(p1ctxt_1[12:0]),
	.sel0	(wr_p1ctxt[1]),
	.sel1	(wr_p1ctxt_[1]),
	.dout	(p1ctxt_1_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_2      (
	.din0	(asi_data_in[12:0]),
	.din1	(p1ctxt_2[12:0]),
	.sel0	(wr_p1ctxt[2]),
	.sel1	(wr_p1ctxt_[2]),
	.dout	(p1ctxt_2_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_3      (
	.din0	(asi_data_in[12:0]),
	.din1	(p1ctxt_3[12:0]),
	.sel0	(wr_p1ctxt[3]),
	.sel1	(wr_p1ctxt_[3]),
	.dout	(p1ctxt_3_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_4      (
	.din0	(asi_data_in[12:0]),
	.din1	(p1ctxt_4[12:0]),
	.sel0	(wr_p1ctxt[4]),
	.sel1	(wr_p1ctxt_[4]),
	.dout	(p1ctxt_4_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_5      (
	.din0	(asi_data_in[12:0]),
	.din1	(p1ctxt_5[12:0]),
	.sel0	(wr_p1ctxt[5]),
	.sel1	(wr_p1ctxt_[5]),
	.dout	(p1ctxt_5_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_6      (
	.din0	(asi_data_in[12:0]),
	.din1	(p1ctxt_6[12:0]),
	.sel0	(wr_p1ctxt[6]),
	.sel1	(wr_p1ctxt_[6]),
	.dout	(p1ctxt_6_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_7      (
	.din0	(asi_data_in[12:0]),
	.din1	(p1ctxt_7[12:0]),
	.sel0	(wr_p1ctxt[7]),
	.sel1	(wr_p1ctxt_[7]),
	.dout	(p1ctxt_7_in[12:0])
);

// Secondary context 0 muxes
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_0      (
	.din0	(asi_data_in[12:0]),
	.din1	(s0ctxt_0[12:0]),
	.sel0	(wr_s0ctxt[0]),
	.sel1	(wr_s0ctxt_[0]),
	.dout	(s0ctxt_0_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_1      (
	.din0	(asi_data_in[12:0]),
	.din1	(s0ctxt_1[12:0]),
	.sel0	(wr_s0ctxt[1]),
	.sel1	(wr_s0ctxt_[1]),
	.dout	(s0ctxt_1_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_2      (
	.din0	(asi_data_in[12:0]),
	.din1	(s0ctxt_2[12:0]),
	.sel0	(wr_s0ctxt[2]),
	.sel1	(wr_s0ctxt_[2]),
	.dout	(s0ctxt_2_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_3      (
	.din0	(asi_data_in[12:0]),
	.din1	(s0ctxt_3[12:0]),
	.sel0	(wr_s0ctxt[3]),
	.sel1	(wr_s0ctxt_[3]),
	.dout	(s0ctxt_3_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_4      (
	.din0	(asi_data_in[12:0]),
	.din1	(s0ctxt_4[12:0]),
	.sel0	(wr_s0ctxt[4]),
	.sel1	(wr_s0ctxt_[4]),
	.dout	(s0ctxt_4_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_5      (
	.din0	(asi_data_in[12:0]),
	.din1	(s0ctxt_5[12:0]),
	.sel0	(wr_s0ctxt[5]),
	.sel1	(wr_s0ctxt_[5]),
	.dout	(s0ctxt_5_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_6      (
	.din0	(asi_data_in[12:0]),
	.din1	(s0ctxt_6[12:0]),
	.sel0	(wr_s0ctxt[6]),
	.sel1	(wr_s0ctxt_[6]),
	.dout	(s0ctxt_6_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_7      (
	.din0	(asi_data_in[12:0]),
	.din1	(s0ctxt_7[12:0]),
	.sel0	(wr_s0ctxt[7]),
	.sel1	(wr_s0ctxt_[7]),
	.dout	(s0ctxt_7_in[12:0])
);

// Secondary context 1 muxes
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_0      (
	.din0	(asi_data_in[12:0]),
	.din1	(s1ctxt_0[12:0]),
	.sel0	(wr_s1ctxt[0]),
	.sel1	(wr_s1ctxt_[0]),
	.dout	(s1ctxt_0_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_1      (
	.din0	(asi_data_in[12:0]),
	.din1	(s1ctxt_1[12:0]),
	.sel0	(wr_s1ctxt[1]),
	.sel1	(wr_s1ctxt_[1]),
	.dout	(s1ctxt_1_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_2      (
	.din0	(asi_data_in[12:0]),
	.din1	(s1ctxt_2[12:0]),
	.sel0	(wr_s1ctxt[2]),
	.sel1	(wr_s1ctxt_[2]),
	.dout	(s1ctxt_2_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_3      (
	.din0	(asi_data_in[12:0]),
	.din1	(s1ctxt_3[12:0]),
	.sel0	(wr_s1ctxt[3]),
	.sel1	(wr_s1ctxt_[3]),
	.dout	(s1ctxt_3_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_4      (
	.din0	(asi_data_in[12:0]),
	.din1	(s1ctxt_4[12:0]),
	.sel0	(wr_s1ctxt[4]),
	.sel1	(wr_s1ctxt_[4]),
	.dout	(s1ctxt_4_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_5      (
	.din0	(asi_data_in[12:0]),
	.din1	(s1ctxt_5[12:0]),
	.sel0	(wr_s1ctxt[5]),
	.sel1	(wr_s1ctxt_[5]),
	.dout	(s1ctxt_5_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_6      (
	.din0	(asi_data_in[12:0]),
	.din1	(s1ctxt_6[12:0]),
	.sel0	(wr_s1ctxt[6]),
	.sel1	(wr_s1ctxt_[6]),
	.dout	(s1ctxt_6_in[12:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_7      (
	.din0	(asi_data_in[12:0]),
	.din1	(s1ctxt_7[12:0]),
	.sel0	(wr_s1ctxt[7]),
	.sel1	(wr_s1ctxt_[7]),
	.dout	(s1ctxt_7_in[12:0])
);

// Partition ID muxes
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid0      (
	.din0	(asi_data_in[2:0]),
	.din1	(pid0[2:0]),
	.sel0	(wr_pid[0]),
	.sel1	(wr_pid_[0]),
	.dout	(pid0_in[2:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid1      (
	.din0	(asi_data_in[2:0]),
	.din1	(pid1[2:0]),
	.sel0	(wr_pid[1]),
	.sel1	(wr_pid_[1]),
	.dout	(pid1_in[2:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid2      (
	.din0	(asi_data_in[2:0]),
	.din1	(pid2[2:0]),
	.sel0	(wr_pid[2]),
	.sel1	(wr_pid_[2]),
	.dout	(pid2_in[2:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid3      (
	.din0	(asi_data_in[2:0]),
	.din1	(pid3[2:0]),
	.sel0	(wr_pid[3]),
	.sel1	(wr_pid_[3]),
	.dout	(pid3_in[2:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid4      (
	.din0	(asi_data_in[2:0]),
	.din1	(pid4[2:0]),
	.sel0	(wr_pid[4]),
	.sel1	(wr_pid_[4]),
	.dout	(pid4_in[2:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid5      (
	.din0	(asi_data_in[2:0]),
	.din1	(pid5[2:0]),
	.sel0	(wr_pid[5]),
	.sel1	(wr_pid_[5]),
	.dout	(pid5_in[2:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid6      (
	.din0	(asi_data_in[2:0]),
	.din1	(pid6[2:0]),
	.sel0	(wr_pid[6]),
	.sel1	(wr_pid_[6]),
	.dout	(pid6_in[2:0])
);
lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid7      (
	.din0	(asi_data_in[2:0]),
	.din1	(pid7[2:0]),
	.sel0	(wr_pid[7]),
	.sel1	(wr_pid_[7]),
	.dout	(pid7_in[2:0])
);

lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state0     (	// FS:wmr_protect
	.scan_in(dff_state0_wmr_scanin),
	.scan_out(dff_state0_wmr_scanout),
	.siclk(siclk_wmr),
	.din	({pid0_in[2:0],p1ctxt_0_in[12:0],s1ctxt_0_in[12:0],p0ctxt_0_in[12:0],s0ctxt_0_in[12:0],asi_state0_in[7:0]}),
	.dout	(state0[62:0]),                                                                                          
	.clk	(l2clk),                                                                                                 
	.en	(1'b1),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)                                                                                         
);                                                                                                                       
lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state1     ( 	// FS:wmr_protect
	.scan_in(dff_state1_wmr_scanin),
	.scan_out(dff_state1_wmr_scanout),
	.siclk(siclk_wmr),
	.din	({pid1_in[2:0],p1ctxt_1_in[12:0],s1ctxt_1_in[12:0],p0ctxt_1_in[12:0],s0ctxt_1_in[12:0],asi_state1_in[7:0]}),
	.dout	(state1[62:0]),                                                                                          
	.clk	(l2clk),                                                                                                 
	.en	(1'b1),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)                                                                                         
);                                                                                                                       
lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state2     (	// FS:wmr_protect
	.scan_in(dff_state2_wmr_scanin),
	.scan_out(dff_state2_wmr_scanout),
	.siclk(siclk_wmr),
	.din	({pid2_in[2:0],p1ctxt_2_in[12:0],s1ctxt_2_in[12:0],p0ctxt_2_in[12:0],s0ctxt_2_in[12:0],asi_state2_in[7:0]}),
	.dout	(state2[62:0]),                                                                                          
	.clk	(l2clk),                                                                                                 
	.en	(1'b1),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)                                                                                         
);                                                                                                                       
lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state3     (	// FS:wmr_protect
	.scan_in(dff_state3_wmr_scanin),
	.scan_out(dff_state3_wmr_scanout),
	.siclk(siclk_wmr),
	.din	({pid3_in[2:0],p1ctxt_3_in[12:0],s1ctxt_3_in[12:0],p0ctxt_3_in[12:0],s0ctxt_3_in[12:0],asi_state3_in[7:0]}),
	.dout	(state3[62:0]),                                                                                          
	.clk	(l2clk),                                                                                                 
	.en	(1'b1),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)                                                                                         
);                                                                                                                       
lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state4     (	// FS:wmr_protect
	.scan_in(dff_state4_wmr_scanin),
	.scan_out(dff_state4_wmr_scanout),
	.siclk(siclk_wmr),
	.din	({pid4_in[2:0],p1ctxt_4_in[12:0],s1ctxt_4_in[12:0],p0ctxt_4_in[12:0],s0ctxt_4_in[12:0],asi_state4_in[7:0]}),
	.dout	(state4[62:0]),                                                                                          
	.clk	(l2clk),                                                                                                 
	.en	(1'b1),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)                                                                                         
);                                                                                                                       
lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state5     (	// FS:wmr_protect
	.scan_in(dff_state5_wmr_scanin),
	.scan_out(dff_state5_wmr_scanout),
	.siclk(siclk_wmr),
	.din	({pid5_in[2:0],p1ctxt_5_in[12:0],s1ctxt_5_in[12:0],p0ctxt_5_in[12:0],s0ctxt_5_in[12:0],asi_state5_in[7:0]}),
	.dout	(state5[62:0]),                                                                                          
	.clk	(l2clk),                                                                                                 
	.en	(1'b1),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)                                                                                         
);                                                                                                                       
lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state6     (	// FS:wmr_protect
	.scan_in(dff_state6_wmr_scanin),
	.scan_out(dff_state6_wmr_scanout),
	.siclk(siclk_wmr),
	.din	({pid6_in[2:0],p1ctxt_6_in[12:0],s1ctxt_6_in[12:0],p0ctxt_6_in[12:0],s0ctxt_6_in[12:0],asi_state6_in[7:0]}),
	.dout	(state6[62:0]),                                                                                          
	.clk	(l2clk),                                                                                                 
	.en	(1'b1),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)                                                                                         
);                                                                                                                       
lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state7     (	// FS:wmr_protect
	.scan_in(dff_state7_wmr_scanin),
	.scan_out(dff_state7_wmr_scanout),
	.siclk(siclk_wmr),
	.din	({pid7_in[2:0],p1ctxt_7_in[12:0],s1ctxt_7_in[12:0],p0ctxt_7_in[12:0],s0ctxt_7_in[12:0],asi_state7_in[7:0]}),
	.dout	(state7[62:0]),
	.clk	(l2clk),
	.en	(1'b1),
  .se(se),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// DO NOT CHANGE THE NAMES OF THE asi_stateN SIGNALS.  THE VERIFICATION BENCH EXPECTS THIS NAME.
assign {pid0[2:0],p1ctxt_0[12:0],s1ctxt_0[12:0],p0ctxt_0[12:0],s0ctxt_0[12:0],asi_state0[7:0]} = state0[62:0];
assign {pid1[2:0],p1ctxt_1[12:0],s1ctxt_1[12:0],p0ctxt_1[12:0],s0ctxt_1[12:0],asi_state1[7:0]} = state1[62:0];
assign {pid2[2:0],p1ctxt_2[12:0],s1ctxt_2[12:0],p0ctxt_2[12:0],s0ctxt_2[12:0],asi_state2[7:0]} = state2[62:0];
assign {pid3[2:0],p1ctxt_3[12:0],s1ctxt_3[12:0],p0ctxt_3[12:0],s0ctxt_3[12:0],asi_state3[7:0]} = state3[62:0];
assign {pid4[2:0],p1ctxt_4[12:0],s1ctxt_4[12:0],p0ctxt_4[12:0],s0ctxt_4[12:0],asi_state4[7:0]} = state4[62:0];
assign {pid5[2:0],p1ctxt_5[12:0],s1ctxt_5[12:0],p0ctxt_5[12:0],s0ctxt_5[12:0],asi_state5[7:0]} = state5[62:0];
assign {pid6[2:0],p1ctxt_6[12:0],s1ctxt_6[12:0],p0ctxt_6[12:0],s0ctxt_6[12:0],asi_state6[7:0]} = state6[62:0];
assign {pid7[2:0],p1ctxt_7[12:0],s1ctxt_7[12:0],p0ctxt_7[12:0],s0ctxt_7[12:0],asi_state7[7:0]} = state7[62:0];

lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_64c__width_55 mx_ctxt0     (
	.din0	(state0[62:8]),
	.din1	(state1[62:8]),
	.din2	(state2[62:8]),
	.din3	(state3[62:8]),
	.sel	(dcc_ctxt_tid0_d[1:0]),
	.dout	(state_tg0[62:8])
);

lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_64c__width_55 mx_ctxt1     (
	.din0	(state4[62:8]),
	.din1	(state5[62:8]),
	.din2	(state6[62:8]),
	.din3	(state7[62:8]),
	.sel	(dcc_ctxt_tid1_d[1:0]),
	.dout	(state_tg1[62:8])
);
lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_10r__width_9 mx_asi0     (
	.din0	({asi_state0[7:0],dmmu_enable[0]}),
	.din1	({asi_state1[7:0],dmmu_enable[1]}),
	.din2	({asi_state2[7:0],dmmu_enable[2]}),
	.din3	({asi_state3[7:0],dmmu_enable[3]}),
	.sel	(dec_lsu_tid0_d[1:0]),
	.dout	({state_tg0[7:0],dmmu_enable_tg0})
);

lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_10r__width_9 mx_asi1     (
	.din0	({asi_state4[7:0],dmmu_enable[4]}),
	.din1	({asi_state5[7:0],dmmu_enable[5]}),
	.din2	({asi_state6[7:0],dmmu_enable[6]}),
	.din3	({asi_state7[7:0],dmmu_enable[7]}),
	.sel	(dec_lsu_tid1_d[1:0]),
	.dout	({state_tg1[7:0],dmmu_enable_tg1})
);

lsu_dcs_dp_msff_macro__mux_aope__ports_2__stack_64c__width_55 dff_mx_ctxt     (
	.scan_in(dff_mx_ctxt_scanin),
	.scan_out(dff_mx_ctxt_scanout),
	.din0	(state_tg1[62:8]),
	.din1	(state_tg0[62:8]),
	.sel0	(dcc_ctxt_tg_d),
	.clk	(l2clk),
	.en	(1'b1),
	.dout	({dcs_pid_e[2:0],dcs_p1ctxt_e[12:0],dcs_s1ctxt_e[12:0],dcs_p0ctxt_e[12:0],dcs_s0ctxt_e[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_dcs_dp_mux_macro__mux_pgpe__ports_2__stack_10r__width_9 mx_asi     (
	.din0	({state_tg1[7:0],dmmu_enable_tg1}),
	.din1	({state_tg0[7:0],dmmu_enable_tg0}),
	.sel0	(dec_lsu_tg_d),
	.dout	({dcs_asi_d[7:0],dcs_dmmu_enable_d})
);

// Context selection
lsu_dcs_dp_mux_macro__mux_aonpe__ports_2__stack_14l__width_13 mx_context0     (
	.din0	(dcs_p0ctxt_e[12:0]),
	.din1	(dcs_s0ctxt_e[12:0]),
	.sel0	(dcc_pctxt_sel_e),
	.sel1	(dcc_sctxt_sel_e),
	.dout	(context0_e[12:0])
);
lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_14r__width_13 buf_context0   (
	.din	(context0_e[12:0]),
	.dout	(dcs_context0_e[12:0])
);

// 0in bits_on -var {dcc_pctxt_sel_e,dcc_sctxt_sel_e} -max 1 -message "multiple context selects"
lsu_dcs_dp_mux_macro__mux_aonpe__ports_2__stack_14r__width_13 mx_context1     (
	.din0	(dcs_p1ctxt_e[12:0]),
	.din1	(dcs_s1ctxt_e[12:0]),
	.sel0	(dcc_pctxt_sel_e),
	.sel1	(dcc_sctxt_sel_e),
	.dout	(context1_e[12:0])
);
lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_14r__width_13 buf_context1   (
	.din	(context1_e[12:0]),
	.dout	(dcs_context1_e[12:0])
);

// MMU needs the context in B for miss processing
lsu_dcs_dp_msff_macro__stack_14r__width_14 dff_context_m    (
	.scan_in(dff_context_m_scanin),
	.scan_out(dff_context_m_scanout),
	.din	({dcc_dcs_memref_e,context0_e[12:0]}),
	.dout	({memref_m        ,dcs_context0_m[12:0]}),
	.clk	(l2clk),
	.en	(dcc_dcs_memref_e),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)		// gated for power
);

// Used elsewhere for power management
assign dcs_memref_m = memref_m;

lsu_dcs_dp_msff_macro__stack_30r__width_30 dff_context_b    (
	.scan_in(dff_context_b_scanin),
	.scan_out(dff_context_b_scanout),
	.din	({dcs_context0_m[12:0],
		  dcs_wpt_mode_m[1:0],dcs_wpt_mask_m[7:0],dcs_wpt_enable_m[1:0],lsu_ctl_reg_m[4:0]}),
	.dout	({dcs_context0_b[12:0],
		  dcs_wpt_mode_b[1:0],dcs_wpt_mask_b[7:0],dcs_wpt_enable_b[1:0],lsu_ctl_reg_b[4:0]}),
	.clk	(l2clk),
	.en	(memref_m),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)		// gated for power
);

lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__width_13 context_buf  (
	.din	(dcs_context0_b[12:0]),
	.dout	(lsu_context_b[12:0])
);

lsu_dcs_dp_msff_macro__stack_64c__width_55 dff_state_m    (
	.scan_in(dff_state_m_scanin),
	.scan_out(dff_state_m_scanout),
	.din	({dcs_pid_e[2:0],dcs_p1ctxt_e[12:0],dcs_s1ctxt_e[12:0],dcs_p0ctxt_e[12:0],dcs_s0ctxt_e[12:0]}),
	.dout	({dcs_pid_m[2:0],dcs_p1ctxt_m[12:0],dcs_s1ctxt_m[12:0],dcs_p0ctxt_m[12:0],dcs_s0ctxt_m[12:0]}),
	.clk	(l2clk),
	.en	(dcc_ld_inst_unqual_e),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	// gated for power
);

// Mux out values for asi read.  (ASI register is read in TLU, so it's not used here)
lsu_dcs_dp_mux_macro__mux_aonpe__ports_5__stack_14l__width_13 mx_state_rd     (
	.din0	(dcs_p0ctxt_m[12:0]),
	.din1	(dcs_p1ctxt_m[12:0]),
	.din2	(dcs_s0ctxt_m[12:0]),
	.din3	(dcs_s1ctxt_m[12:0]),
	.din4	({10'd0,dcs_pid_m[2:0]}),
	.sel0	(dcc_p0ctxt_rd_m),
	.sel1	(dcc_p1ctxt_rd_m),
	.sel2	(dcc_s0ctxt_rd_m),
	.sel3	(dcc_s1ctxt_rd_m),
	.sel4	(dcc_pid_rd_m),
	.dout	(ldxa_asi_data_m[12:0])
);

lsu_dcs_dp_msff_macro__left_17__mux_aope__ports_2__stack_64c__width_47 dff_stg_b       (
	.scan_in(dff_stg_b_scanin),
	.scan_out(dff_stg_b_scanout),
	.din0	({watchpoint_m[47:3],2'b0}),
	.din1	({34'd0,ldxa_asi_data_m[12:0]}),
	.sel0	(dcc_wtchpt_sel_m),
	.dout	(stg_b[46:0]),
	.clk	(l2clk),
	.en	(dcc_asi_load_m),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign ldxa_asi_data_b[12:0] = stg_b[12:0];
assign watchpoint_b[47:3] = {stg_b[46:2]};

assign core_id[5:0] = {const_cpuid[2:0],dcc_tid_b[2:0]};
assign max_core_id[5:0] = 6'b111111;
assign max_strand_id[5:0] = 6'b000111;

lsu_dcs_dp_mux_macro__mux_aope__ports_8__stack_64c__width_64 mx_asi_b      (
	.din0	({{16{watchpoint_b[47]}},watchpoint_b[47:3],3'b00}),
	.din1	({29'd0,dcs_wpt_mode_b[1:0],dcs_wpt_mask_b[7:0],dcs_wpt_enable_b[1:0],18'd0,lsu_ctl_reg_b[4:0]}),
	.din2	({56'd0,dca_rparity_b[7:0]}),
	.din3	({26'b0,max_strand_id[5:0],10'b0,max_core_id[5:0],10'b0,core_id[5:0]}),
	.din4	({58'b0,core_id[5:0]}),
	.din5	({32'b0,lsu_asi_error_inject[31:0]}),
	.din6	({48'b0,lsu_asi_pwr_mgmt[15:0]}),
	.din7	({51'd0,ldxa_asi_data_b[12:0]}),
	.sel0	(dcc_wtchpt_rd_b),
	.sel1	(dcc_rd_lsu_ctl_reg_b),
	.sel2	(dcc_rd_diag_dca_b),
	.sel3	(dcc_rd_core_id_b),
	.sel4	(dcc_rd_intr_id_b),
	.sel5	(dcc_rd_error_inj_b),
	.sel6	(dcc_rd_pwr_mgmt_b),
	.dout	(ldxa_asi_data_b_2[63:0])
);
lsu_dcs_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 dff_asi_w      (
	.scan_in(dff_asi_w_scanin),
	.scan_out(dff_asi_w_scanout),
	.din0	({62'd0,dcc_direct_map,lsu_ifu_direct_map}),
	.din1	(tgd_ldxa_asi_data_b[63:0]),
	.din2	(ldxa_asi_data_b_2[63:0]),
	.sel0	(dcc_rd_diag_reg_b),
	.sel1	(dcc_rd_rhs_asi_b),
	.dout	(dcs_ldxa_asi_data_w[63:0]),
	.clk	(l2clk),
	.en	(dcc_asi_load_b),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

////////////////////////////////////////////////////////////////////////////////
// Watchpoint registers and comparator

lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_0    (	// FS:wmr_protect
	.scan_in(dff_watchpoint_0_wmr_scanin),
	.scan_out(dff_watchpoint_0_wmr_scanout),
	.siclk(siclk_wmr),
	.se	(scan_en_wmr),
	.din	(wsr_data_w[47:3]),
	.dout	(watchpoint0[47:3]),
	.clk	(l2clk),
	.en	(dcc_wr_wtchpt[0]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_1    (	// FS:wmr_protect
	.scan_in(dff_watchpoint_1_wmr_scanin),
	.scan_out(dff_watchpoint_1_wmr_scanout),
	.siclk(siclk_wmr),
	.se	(scan_en_wmr),
	.din	(wsr_data_w[47:3]),
	.dout	(watchpoint1[47:3]),
	.clk	(l2clk),
	.en	(dcc_wr_wtchpt[1]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_2    (	// FS:wmr_protect
	.scan_in(dff_watchpoint_2_wmr_scanin),
	.scan_out(dff_watchpoint_2_wmr_scanout),
	.siclk(siclk_wmr),
	.se	(scan_en_wmr),
	.din	(wsr_data_w[47:3]),
	.dout	(watchpoint2[47:3]),
	.clk	(l2clk),
	.en	(dcc_wr_wtchpt[2]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_3    (	// FS:wmr_protect
	.scan_in(dff_watchpoint_3_wmr_scanin),
	.scan_out(dff_watchpoint_3_wmr_scanout),
	.siclk(siclk_wmr),
	.se	(scan_en_wmr),
	.din	(wsr_data_w[47:3]),
	.dout	(watchpoint3[47:3]),
	.clk	(l2clk),
	.en	(dcc_wr_wtchpt[3]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_4    (	// FS:wmr_protect
	.scan_in(dff_watchpoint_4_wmr_scanin),
	.scan_out(dff_watchpoint_4_wmr_scanout),
	.siclk(siclk_wmr),
	.se	(scan_en_wmr),
	.din	(wsr_data_w[47:3]),
	.dout	(watchpoint4[47:3]),
	.clk	(l2clk),
	.en	(dcc_wr_wtchpt[4]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_5    (	// FS:wmr_protect
	.scan_in(dff_watchpoint_5_wmr_scanin),
	.scan_out(dff_watchpoint_5_wmr_scanout),
	.siclk(siclk_wmr),
	.se	(scan_en_wmr),
	.din	(wsr_data_w[47:3]),
	.dout	(watchpoint5[47:3]),
	.clk	(l2clk),
	.en	(dcc_wr_wtchpt[5]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_6    (	// FS:wmr_protect
	.scan_in(dff_watchpoint_6_wmr_scanin),
	.scan_out(dff_watchpoint_6_wmr_scanout),
	.siclk(siclk_wmr),
	.se	(scan_en_wmr),
	.din	(wsr_data_w[47:3]),
	.dout	(watchpoint6[47:3]),
	.clk	(l2clk),
	.en	(dcc_wr_wtchpt[6]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_7    (	// FS:wmr_protect
	.scan_in(dff_watchpoint_7_wmr_scanin),
	.scan_out(dff_watchpoint_7_wmr_scanout),
	.siclk(siclk_wmr),
	.se	(scan_en_wmr),
	.din	(wsr_data_w[47:3]),
	.dout	(watchpoint7[47:3]),
	.clk	(l2clk),
	.en	(dcc_wr_wtchpt[7]),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_dcs_dp_mux_macro__left_18__mux_aodec__ports_8__stack_64c__width_45 mx_watchpoint       (
	.din0	(watchpoint0[47:3]),
	.din1	(watchpoint1[47:3]),
	.din2	(watchpoint2[47:3]),
	.din3	(watchpoint3[47:3]),
	.din4	(watchpoint4[47:3]),
	.din5	(watchpoint5[47:3]),
	.din6	(watchpoint6[47:3]),
	.din7	(watchpoint7[47:3]),
	.sel	(dcc_tid_m[2:0]),
	.dout	(watchpoint_mx_m[47:3])
);

lsu_dcs_dp_buff_macro__left_18__stack_64c__width_45 buf_watchpoint    (
	.din	(watchpoint_mx_m[47:3]),
	.dout	(watchpoint_m[47:3])
);
assign dcs_watchpoint_m[47:3] = watchpoint_m[47:3];

////////////////////////////////////////////////////////////////////////////////
// ASI_LSU_CTL_REG

lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_0    (
	.din0	({wsr_data_w[34:23],wsr_data_w[4:0]}),
	.din1	({17{tlu_lsu_clear_ctl_reg_[0]}}),
	.dout	(ctl_reg0_in[16:0])
);
lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_1    (
	.din0	({wsr_data_w[34:23],wsr_data_w[4:0]}),
	.din1	({17{tlu_lsu_clear_ctl_reg_[1]}}),
	.dout	(ctl_reg1_in[16:0])
);
lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_2    (
	.din0	({wsr_data_w[34:23],wsr_data_w[4:0]}),
	.din1	({17{tlu_lsu_clear_ctl_reg_[2]}}),
	.dout	(ctl_reg2_in[16:0])
);
lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_3    (
	.din0	({wsr_data_w[34:23],wsr_data_w[4:0]}),
	.din1	({17{tlu_lsu_clear_ctl_reg_[3]}}),
	.dout	(ctl_reg3_in[16:0])
);
lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_4    (
	.din0	({wsr_data_w[34:23],wsr_data_w[4:0]}),
	.din1	({17{tlu_lsu_clear_ctl_reg_[4]}}),
	.dout	(ctl_reg4_in[16:0])
);
lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_5    (
	.din0	({wsr_data_w[34:23],wsr_data_w[4:0]}),
	.din1	({17{tlu_lsu_clear_ctl_reg_[5]}}),
	.dout	(ctl_reg5_in[16:0])
);
lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_6    (
	.din0	({wsr_data_w[34:23],wsr_data_w[4:0]}),
	.din1	({17{tlu_lsu_clear_ctl_reg_[6]}}),
	.dout	(ctl_reg6_in[16:0])
);
lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_7    (
	.din0	({wsr_data_w[34:23],wsr_data_w[4:0]}),
	.din1	({17{tlu_lsu_clear_ctl_reg_[7]}}),
	.dout	(ctl_reg7_in[16:0])
);

lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_0   (
	.scan_in(dff_lsu_ctl_0_scanin),
	.scan_out(dff_lsu_ctl_0_scanout),
	.din	(ctl_reg0_in[16:0]),
	.dout	({wpt_mode_0[1:0],wpt_mask_0[7:0],wpt_enable_0[1:0],spec_enable[0],
		  dmmu_enable[0],immu_enable[0],dc_enable[0],ic_enable[0]}),
	.clk	(l2clk),
	.en	(dcc_wr_lsu_ctl_reg[0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_1   (
	.scan_in(dff_lsu_ctl_1_scanin),
	.scan_out(dff_lsu_ctl_1_scanout),
	.din	(ctl_reg1_in[16:0]),
	.dout	({wpt_mode_1[1:0],wpt_mask_1[7:0],wpt_enable_1[1:0],spec_enable[1],
		  dmmu_enable[1],immu_enable[1],dc_enable[1],ic_enable[1]}),
	.clk	(l2clk),
	.en	(dcc_wr_lsu_ctl_reg[1]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_2   (
	.scan_in(dff_lsu_ctl_2_scanin),
	.scan_out(dff_lsu_ctl_2_scanout),
	.din	(ctl_reg2_in[16:0]),
	.dout	({wpt_mode_2[1:0],wpt_mask_2[7:0],wpt_enable_2[1:0],spec_enable[2],
		  dmmu_enable[2],immu_enable[2],dc_enable[2],ic_enable[2]}),
	.clk	(l2clk),
	.en	(dcc_wr_lsu_ctl_reg[2]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_3   (
	.scan_in(dff_lsu_ctl_3_scanin),
	.scan_out(dff_lsu_ctl_3_scanout),
	.din	(ctl_reg3_in[16:0]),
	.dout	({wpt_mode_3[1:0],wpt_mask_3[7:0],wpt_enable_3[1:0],spec_enable[3],
		  dmmu_enable[3],immu_enable[3],dc_enable[3],ic_enable[3]}),
	.clk	(l2clk),
	.en	(dcc_wr_lsu_ctl_reg[3]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_4   (
	.scan_in(dff_lsu_ctl_4_scanin),
	.scan_out(dff_lsu_ctl_4_scanout),
	.din	(ctl_reg4_in[16:0]),
	.dout	({wpt_mode_4[1:0],wpt_mask_4[7:0],wpt_enable_4[1:0],spec_enable[4],
		  dmmu_enable[4],immu_enable[4],dc_enable[4],ic_enable[4]}),
	.clk	(l2clk),
	.en	(dcc_wr_lsu_ctl_reg[4]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_5   (
	.scan_in(dff_lsu_ctl_5_scanin),
	.scan_out(dff_lsu_ctl_5_scanout),
	.din	(ctl_reg5_in[16:0]),
	.dout	({wpt_mode_5[1:0],wpt_mask_5[7:0],wpt_enable_5[1:0],spec_enable[5],
		  dmmu_enable[5],immu_enable[5],dc_enable[5],ic_enable[5]}),
	.clk	(l2clk),
	.en	(dcc_wr_lsu_ctl_reg[5]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_6   (
	.scan_in(dff_lsu_ctl_6_scanin),
	.scan_out(dff_lsu_ctl_6_scanout),
	.din	(ctl_reg6_in[16:0]),
	.dout	({wpt_mode_6[1:0],wpt_mask_6[7:0],wpt_enable_6[1:0],spec_enable[6],
		  dmmu_enable[6],immu_enable[6],dc_enable[6],ic_enable[6]}),
	.clk	(l2clk),
	.en	(dcc_wr_lsu_ctl_reg[6]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_7   (
	.scan_in(dff_lsu_ctl_7_scanin),
	.scan_out(dff_lsu_ctl_7_scanout),
	.din	(ctl_reg7_in[16:0]),
	.dout	({wpt_mode_7[1:0],wpt_mask_7[7:0],wpt_enable_7[1:0],spec_enable[7],
		  dmmu_enable[7],immu_enable[7],dc_enable[7],ic_enable[7]}),
	.clk	(l2clk),
	.en	(dcc_wr_lsu_ctl_reg[7]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_0   (
	.din	({immu_enable[0], dc_enable[0],    ic_enable[0]}),
	.dout	({lsu_immu_enable[0], dcs_dc_enable[0],lsu_ic_enable[0]})
);
lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_1   (
	.din	({immu_enable[1], dc_enable[1],    ic_enable[1]}),
	.dout	({lsu_immu_enable[1], dcs_dc_enable[1],lsu_ic_enable[1]})
);
lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_2   (
	.din	({immu_enable[2], dc_enable[2],    ic_enable[2]}),
	.dout	({lsu_immu_enable[2], dcs_dc_enable[2],lsu_ic_enable[2]})
);
lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_3   (
	.din	({immu_enable[3], dc_enable[3],    ic_enable[3]}),
	.dout	({lsu_immu_enable[3], dcs_dc_enable[3],lsu_ic_enable[3]})
);
lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_4   (
	.din	({immu_enable[4], dc_enable[4],    ic_enable[4]}),
	.dout	({lsu_immu_enable[4], dcs_dc_enable[4],lsu_ic_enable[4]})
);
lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_5   (
	.din	({immu_enable[5], dc_enable[5],    ic_enable[5]}),
	.dout	({lsu_immu_enable[5], dcs_dc_enable[5],lsu_ic_enable[5]})
);
lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_6   (
	.din	({immu_enable[6], dc_enable[6],    ic_enable[6]}),
	.dout	({lsu_immu_enable[6], dcs_dc_enable[6],lsu_ic_enable[6]})
);
lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_7   (
	.din	({immu_enable[7], dc_enable[7],    ic_enable[7]}),
	.dout	({lsu_immu_enable[7], dcs_dc_enable[7],lsu_ic_enable[7]})
);

lsu_dcs_dp_mux_macro__mux_aodec__ports_8__stack_18r__width_17 mx_lsu_ctl      (
	.din0	({wpt_mode_0[1:0],wpt_mask_0[7:0],wpt_enable_0[1:0],spec_enable[0],
		  dmmu_enable[0],immu_enable[0],dc_enable[0],ic_enable[0]}),
	.din1	({wpt_mode_1[1:0],wpt_mask_1[7:0],wpt_enable_1[1:0],spec_enable[1],
		  dmmu_enable[1],immu_enable[1],dc_enable[1],ic_enable[1]}),
	.din2	({wpt_mode_2[1:0],wpt_mask_2[7:0],wpt_enable_2[1:0],spec_enable[2],
		  dmmu_enable[2],immu_enable[2],dc_enable[2],ic_enable[2]}),
	.din3	({wpt_mode_3[1:0],wpt_mask_3[7:0],wpt_enable_3[1:0],spec_enable[3],
		  dmmu_enable[3],immu_enable[3],dc_enable[3],ic_enable[3]}),
	.din4	({wpt_mode_4[1:0],wpt_mask_4[7:0],wpt_enable_4[1:0],spec_enable[4],
		  dmmu_enable[4],immu_enable[4],dc_enable[4],ic_enable[4]}),
	.din5	({wpt_mode_5[1:0],wpt_mask_5[7:0],wpt_enable_5[1:0],spec_enable[5],
		  dmmu_enable[5],immu_enable[5],dc_enable[5],ic_enable[5]}),
	.din6	({wpt_mode_6[1:0],wpt_mask_6[7:0],wpt_enable_6[1:0],spec_enable[6],
		  dmmu_enable[6],immu_enable[6],dc_enable[6],ic_enable[6]}),
	.din7	({wpt_mode_7[1:0],wpt_mask_7[7:0],wpt_enable_7[1:0],spec_enable[7],
		  dmmu_enable[7],immu_enable[7],dc_enable[7],ic_enable[7]}),
	.sel	(dcc_tid_m[2:0]),
	.dout	(lsu_ctl_mx[16:0])
);
lsu_dcs_dp_buff_macro__stack_18r__width_17 buf_lsu_ctl   (
	.din	(lsu_ctl_mx[16:0]),
	.dout	({dcs_wpt_mode_m[1:0],dcs_wpt_mask_m[7:0],dcs_wpt_enable_m[1:0],lsu_ctl_reg_m[4:0]})
);

////////////////////////////////////////////////////////////////////////////////
// ASI_ERROR_INJECT

lsu_dcs_dp_msff_macro__stack_64c__width_32 dff_error_inject   (
	.scan_in(dff_error_inject_scanin),
	.scan_out(dff_error_inject_scanout),
	.din	({wsr_data_w[31],1'b0,wsr_data_w[29:19],1'b0,wsr_data_w[17],9'b0,wsr_data_w[7:0]}),
	.dout	(asi_error_inject[31:0]),
	.clk	(l2clk),
	.en	(dcc_wr_error_inj_w),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_32 buf_error_inject   (
	.din	(asi_error_inject[31:0]),
	.dout	(lsu_asi_error_inject[31:0])
);

////////////////////////////////////////////////////////////////////////////////
// ASI_SPARC_PWR_MGMT

lsu_dcs_dp_msff_macro__stack_16r__width_16 dff_pwr_mgmt   (
	.scan_in(dff_pwr_mgmt_scanin),
	.scan_out(dff_pwr_mgmt_scanout),
	.din	(wsr_data_w[15:0]),
	.dout	(asi_pwr_mgmt[15:0]),
	.clk	(l2clk),
	.en	(dcc_wr_pwr_mgmt),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_16r__width_16 buf_pwr_mgmt   (
	.din	(asi_pwr_mgmt[15:0]),
	.dout	(lsu_asi_pwr_mgmt[15:0])
);

////////////////////////////////////////////////////////////////////////////////
// Flop VA from M->B
lsu_dcs_dp_msff_macro__stack_48c__width_37 dff_va_b   (
	.scan_in(dff_va_b_scanin),
	.scan_out(dff_va_b_scanout),
	.din	({tlu_asi_0[7:0],tlu_asi_1[7:0],lsu_va_m[20:0]}),
	.dout	({reload_asi_0[7:0],reload_asi_1[7:0],va_b[20:0]}),
	.clk	(l2clk),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_dcs_dp_buff_macro__stack_48c__width_21 buf_va_b   (
	.din	(va_b[20:0]),
	.dout	(lsu_va_b[20:0])
);

// fixscan start:
assign dff_in_data_scanin        = scan_in                  ;
assign dff_mx_ctxt_scanin        = dff_in_data_scanout      ;
assign dff_context_m_scanin      = dff_mx_ctxt_scanout      ;
assign dff_context_b_scanin      = dff_context_m_scanout    ;
assign dff_state_m_scanin        = dff_context_b_scanout    ;
assign dff_stg_b_scanin          = dff_state_m_scanout      ;
assign dff_asi_w_scanin          = dff_stg_b_scanout        ;
assign dff_lsu_ctl_0_scanin      = dff_asi_w_scanout        ;
assign dff_lsu_ctl_1_scanin      = dff_lsu_ctl_0_scanout    ;
assign dff_lsu_ctl_2_scanin      = dff_lsu_ctl_1_scanout    ;
assign dff_lsu_ctl_3_scanin      = dff_lsu_ctl_2_scanout    ;
assign dff_lsu_ctl_4_scanin      = dff_lsu_ctl_3_scanout    ;
assign dff_lsu_ctl_5_scanin      = dff_lsu_ctl_4_scanout    ;
assign dff_lsu_ctl_6_scanin      = dff_lsu_ctl_5_scanout    ;
assign dff_lsu_ctl_7_scanin      = dff_lsu_ctl_6_scanout    ;
assign dff_error_inject_scanin   = dff_lsu_ctl_7_scanout    ;
assign dff_pwr_mgmt_scanin       = dff_error_inject_scanout ;
assign dff_va_b_scanin           = dff_pwr_mgmt_scanout     ;
assign scan_out                  = dff_va_b_scanout         ;

assign dff_state0_wmr_scanin     = wmr_scan_in              ;
assign dff_state1_wmr_scanin     = dff_state0_wmr_scanout   ;
assign dff_state2_wmr_scanin     = dff_state1_wmr_scanout   ;
assign dff_state3_wmr_scanin     = dff_state2_wmr_scanout   ;
assign dff_state4_wmr_scanin     = dff_state3_wmr_scanout   ;
assign dff_state5_wmr_scanin     = dff_state4_wmr_scanout   ;
assign dff_state6_wmr_scanin     = dff_state5_wmr_scanout   ;
assign dff_state7_wmr_scanin     = dff_state6_wmr_scanout   ;
assign dff_watchpoint_0_wmr_scanin = dff_state7_wmr_scanout   ;
assign dff_watchpoint_1_wmr_scanin = dff_watchpoint_0_wmr_scanout;
assign dff_watchpoint_2_wmr_scanin = dff_watchpoint_1_wmr_scanout;
assign dff_watchpoint_3_wmr_scanin = dff_watchpoint_2_wmr_scanout;
assign dff_watchpoint_4_wmr_scanin = dff_watchpoint_3_wmr_scanout;
assign dff_watchpoint_5_wmr_scanin = dff_watchpoint_4_wmr_scanout;
assign dff_watchpoint_6_wmr_scanin = dff_watchpoint_5_wmr_scanout;
assign dff_watchpoint_7_wmr_scanin = dff_watchpoint_6_wmr_scanout;
assign wmr_scan_out              = dff_watchpoint_7_wmr_scanout;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_6 (
  din, 
  dout);
  input [5:0] din;
  output [5:0] dout;


buff #(6)  d0_0 (
.in(din[5:0]),
.out(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__left_16__stack_64c__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__width_13 (
  din, 
  dout);
  input [12:0] din;
  output [12:0] dout;


buff #(13)  d0_0 (
.in(din[12:0]),
.out(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  input sel0;
  input sel1;
  output [7:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
.dout(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module lsu_dcs_dp_inv_macro__width_10 (
  din, 
  dout);
  input [9:0] din;
  output [9:0] dout;


inv #(10)  d0_0 (
.in(din[9:0]),
.out(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [12:0] din0;
  input sel0;
  input [12:0] din1;
  input sel1;
  output [12:0] dout;


mux2s #(13)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
.dout(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [2:0] din0;
  input sel0;
  input [2:0] din1;
  input sel1;
  output [2:0] dout;


mux2s #(3)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[2:0]),
  .in1(din1[2:0]),
.dout(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [61:0] so;

  input [62:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [62:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(63)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[62:0]),
.si({scan_in,so[61:0]}),
.so({so[61:0],scan_out}),
.q(dout[62:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_64c__width_55 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [54:0] din0;
  input [54:0] din1;
  input [54:0] din2;
  input [54:0] din3;
  input [1:0] sel;
  output [54:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(55)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[54:0]),
  .in1(din1[54:0]),
  .in2(din2[54:0]),
  .in3(din3[54:0]),
.dout(dout[54:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_10r__width_9 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [8:0] din0;
  input [8:0] din1;
  input [8:0] din2;
  input [8:0] din3;
  input [1:0] sel;
  output [8:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(9)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[8:0]),
  .in1(din1[8:0]),
  .in2(din2[8:0]),
  .in3(din3[8:0]),
.dout(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__mux_aope__ports_2__stack_64c__width_55 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [54:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [53:0] so;

  input [54:0] din0;
  input [54:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [54:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(55)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[54:0]),
  .in1(din1[54:0]),
.dout(muxout[54:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(55)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[54:0]),
.si({scan_in,so[53:0]}),
.so({so[53:0],scan_out}),
.q(dout[54:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_pgpe__ports_2__stack_10r__width_9 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [8:0] din0;
  input [8:0] din1;
  input sel0;
  output [8:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(9)  d0_0 (
  .sel(psel1),
  .in0(din0[8:0]),
  .in1(din1[8:0]),
.dout(dout[8:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_aonpe__ports_2__stack_14l__width_13 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [12:0] din0;
  input sel0;
  input [12:0] din1;
  input sel1;
  output [12:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(13)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
.dout(dout[12:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_14r__width_13 (
  din, 
  dout);
  input [12:0] din;
  output [12:0] dout;


buff #(13)  d0_0 (
.in(din[12:0]),
.out(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_aonpe__ports_2__stack_14r__width_13 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [12:0] din0;
  input sel0;
  input [12:0] din1;
  input sel1;
  output [12:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(13)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
.dout(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__stack_14r__width_14 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [12:0] so;

  input [13:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [13:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__stack_30r__width_30 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [28:0] so;

  input [29:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [29:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(30)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[29:0]),
.si({scan_in,so[28:0]}),
.so({so[28:0],scan_out}),
.q(dout[29:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__stack_64c__width_55 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [53:0] so;

  input [54:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [54:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(55)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[54:0]),
.si({scan_in,so[53:0]}),
.so({so[53:0],scan_out}),
.q(dout[54:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_aonpe__ports_5__stack_14l__width_13 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [12:0] din0;
  input sel0;
  input [12:0] din1;
  input sel1;
  input [12:0] din2;
  input sel2;
  input [12:0] din3;
  input sel3;
  input [12:0] din4;
  input sel4;
  output [12:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(13)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
  .in2(din2[12:0]),
  .in3(din3[12:0]),
  .in4(din4[12:0]),
.dout(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__left_17__mux_aope__ports_2__stack_64c__width_47 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [46:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [45:0] so;

  input [46:0] din0;
  input [46:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [46:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(47)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[46:0]),
  .in1(din1[46:0]),
.dout(muxout[46:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(47)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[46:0]),
.si({scan_in,so[45:0]}),
.so({so[45:0],scan_out}),
.q(dout[46:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_aope__ports_8__stack_64c__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;
  output [63:0] dout;


cl_dp1_penc8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [43:0] so;

  input [44:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [44:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(45)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[44:0]),
.si({scan_in,so[43:0]}),
.so({so[43:0],scan_out}),
.q(dout[44:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__left_18__mux_aodec__ports_8__stack_64c__width_45 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [44:0] din0;
  input [44:0] din1;
  input [44:0] din2;
  input [44:0] din3;
  input [44:0] din4;
  input [44:0] din5;
  input [44:0] din6;
  input [44:0] din7;
  input [2:0] sel;
  output [44:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(45)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[44:0]),
  .in1(din1[44:0]),
  .in2(din2[44:0]),
  .in3(din3[44:0]),
  .in4(din4[44:0]),
  .in5(din5[44:0]),
  .in6(din6[44:0]),
  .in7(din7[44:0]),
.dout(dout[44:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__left_18__stack_64c__width_45 (
  din, 
  dout);
  input [44:0] din;
  output [44:0] dout;


buff #(45)  d0_0 (
.in(din[44:0]),
.out(dout[44:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 (
  din0, 
  din1, 
  dout);
  input [16:0] din0;
  input [16:0] din1;
  output [16:0] dout;


and2 #(17)  d0_0 (
.in0(din0[16:0]),
.in1(din1[16:0]),
.out(dout[16:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__stack_18r__width_17 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [15:0] so;

  input [16:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [16:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(17)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[16:0]),
.si({scan_in,so[15:0]}),
.so({so[15:0],scan_out}),
.q(dout[16:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__stack_4l__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


buff #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_mux_macro__mux_aodec__ports_8__stack_18r__width_17 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [16:0] din0;
  input [16:0] din1;
  input [16:0] din2;
  input [16:0] din3;
  input [16:0] din4;
  input [16:0] din5;
  input [16:0] din6;
  input [16:0] din7;
  input [2:0] sel;
  output [16:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(17)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[16:0]),
  .in1(din1[16:0]),
  .in2(din2[16:0]),
  .in3(din3[16:0]),
  .in4(din4[16:0]),
  .in5(din5[16:0]),
  .in6(din6[16:0]),
  .in7(din7[16:0]),
.dout(dout[16:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__stack_18r__width_17 (
  din, 
  dout);
  input [16:0] din;
  output [16:0] dout;


buff #(17)  d0_0 (
.in(din[16:0]),
.out(dout[16:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__stack_64c__width_32 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__stack_16r__width_16 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [14:0] so;

  input [15:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [15:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_16r__width_16 (
  din, 
  dout);
  input [15:0] din;
  output [15:0] dout;


buff #(16)  d0_0 (
.in(din[15:0]),
.out(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_dcs_dp_msff_macro__stack_48c__width_37 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [35:0] so;

  input [36:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [36:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


//
//   buff macro
//
//


module lsu_dcs_dp_buff_macro__stack_48c__width_21 (
  din, 
  dout);
  input [20:0] din;
  output [20:0] dout;


buff #(21)  d0_0 (
.in(din[20:0]),
.out(dout[20:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_lmc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_lmc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  dcc_tid_m, 
  dcc_ld_inst_vld_m, 
  dcc_pref_inst_m, 
  dcc_ld_miss_b, 
  dcc_ld_miss_ldd, 
  dcc_asi_load_b, 
  dcc_asi_iomap_b, 
  dcc_blk_inst_b, 
  dcc_ldbl_b, 
  dcc_ncache_b, 
  dcc_ld_miss_ctl_b43, 
  dcc_atomic_b, 
  dcc_casa_inst_b, 
  dcc_lsu_asi_rd_b, 
  dcc_lsu_asi_sel_w, 
  dcc_ceter_wr_w, 
  dcc_stb_diag_sel_w3, 
  dcc_exception_flush_b, 
  dcc_perror_b, 
  dcc_sync_pipe_w, 
  dcc_cache_diag_wr_b, 
  dcc_asi_rtn_vld, 
  dcc_asi_rtn_excp, 
  dcc_asi_rtn_rd, 
  pic_casa_squash_req, 
  pic_early_ld_b_sel_p3, 
  pic_no_load_p3, 
  pic_asi_busy, 
  lmd_pcx_pref, 
  lmd_asi_ld, 
  lmd_asi_indet, 
  lmd_sec_cmp_b, 
  lmd_addrb2, 
  lmd_sz_b1, 
  lmd_sz_b0, 
  lmd_ldbl, 
  lmd_rd_e, 
  lmd_dc_err_e, 
  lmd_fill_addr_b3_e, 
  lmd_fill_sz_b0_e, 
  tlb_pgnum_b39, 
  tlb_cam_mhit, 
  tlu_flush_lsu_b, 
  tlu_cerer_sbdlc, 
  tlu_cerer_sbdlu, 
  tlu_cerer_dcl2c, 
  tlu_cerer_dcl2u, 
  tlu_cerer_dcl2nd, 
  tlu_cerer_l2c_socc, 
  tlu_cerer_l2u_socu, 
  dec_flush_lm, 
  dec_flush_lb, 
  dec_ld_inst_d, 
  cic_l2fill_vld_e, 
  cic_cpq_ld_rdy, 
  cic_cpq_ld_rdy_, 
  cic_div_stall_d, 
  cic_oddrd_e, 
  cic_xinval_e, 
  cic_xinval, 
  cic_set_inval, 
  cic_rtn_cmplt, 
  cic_cpq_stall, 
  cic_ext_interrupt, 
  cid_tid, 
  cid_err, 
  cid_dcsoc_err_e, 
  cid_l2miss, 
  stb_cam_hit, 
  stb_cam_mhit, 
  stb_ld_part_raw, 
  stb_cecc_err, 
  stb_uecc_err, 
  sbd_st_data_b_62, 
  sbs_all_commited, 
  sbc_st_atom_p3, 
  sbc_rawp_rst, 
  sbc_st_sel_tid_p4, 
  sbc_force_inv, 
  sbc_kill_store_p4_, 
  lsu_lsu_pmen, 
  lmc_lmq_enable_b, 
  lmc_pcx_sel_p4, 
  lmc_pcx_rq_vld, 
  lmc_asi_rq_vld, 
  lmc_ld_rq_p3, 
  lmc_ld_vld_p4, 
  lmc_ld_no_req_p4, 
  lmc_ld_inv_p4, 
  lmc_ld_tid, 
  lmc_byp_sel_e, 
  lmc_cpq_tid_m, 
  lmc_lmq_bypass_en, 
  lmc_asi_bypass_m, 
  lmc_bld_addr54, 
  lmc_bld_req, 
  lmc_bld_req_, 
  lmc_bld_annul, 
  lmc_bld_miss_e, 
  lmc_bld_last_e, 
  lmc_rd_update, 
  lmc_pref_issued, 
  lmc_ldd_vld, 
  lmc_ld_unfilled, 
  lmc_lmd_ncache_b, 
  lmc_ld_sz, 
  lmc_ld_inst_w, 
  lmc_full_raw_w, 
  lmc_ld_stall, 
  lmc_l2_err_noup, 
  lmc_l2_uerr, 
  lmc_byp_data_hi, 
  lmc_byp_data_enable, 
  lmc_thrd_byp_sel_e, 
  lmc_thrd_byp_sel_m, 
  lmc_byp_tid_m, 
  lmc_byp_vld_m, 
  lmc_lmq0_byp_sel, 
  lmc_lmq1_byp_sel, 
  lmc_lmq2_byp_sel, 
  lmc_lmq3_byp_sel, 
  lmc_lmq4_byp_sel, 
  lmc_lmq5_byp_sel, 
  lmc_lmq6_byp_sel, 
  lmc_lmq7_byp_sel, 
  lmc_asi_indet_retire, 
  lsu_ifu_no_miss, 
  lsu_dcmh_err_g, 
  lsu_dcvp_err_g, 
  lsu_dctp_err_g, 
  lsu_dcdp_err_g, 
  lsu_dcerr_tid_g, 
  lsu_dcl2c_err_g, 
  lsu_dcl2u_err_g, 
  lsu_dcl2nd_err_g, 
  lsu_sbdlc_err_g, 
  lsu_sbdlu_err_g, 
  lsu_stberr_tid_g, 
  lbist_run, 
  mbi_run, 
  lmc_mbi_run, 
  lmc_bist_or_diag_e);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire rqpend_clken;
wire l1clk_pm1;
wire [7:0] cpq_mx_thread;
wire [7:0] ceter_pscce_in;
wire [7:0] thread_w;
wire st_data_w_62;
wire [7:0] ceter_pscce_reg;
wire dff_ceter_scanin;
wire dff_ceter_scanout;
wire ceter_pscce_cpq;
wire ceter_pscce_w3;
wire [7:0] thread_w3;
wire dff_cerer_scanin;
wire dff_cerer_scanout;
wire cerer_sbdlc;
wire cerer_sbdlu;
wire cerer_dcl2c;
wire cerer_dcl2u;
wire cerer_dcl2nd;
wire cerer_socc;
wire cerer_socu;
wire [7:0] thread_b;
wire [2:0] tid_b;
wire dff_thread_w_scanin;
wire dff_thread_w_scanout;
wire dff_flush_b_scanin;
wire dff_flush_b_scanout;
wire local_flush_b;
wire flush_b;
wire excep_only_flush_b;
wire dff_flush_w_scanin;
wire dff_flush_w_scanout;
wire flush_w;
wire perror_w;
wire dff_inst_b_scanin;
wire dff_inst_b_scanout;
wire ld_inst_vld_b;
wire pref_inst_b;
wire blk_inst_w;
wire dff_inst_w_scanin;
wire dff_inst_w_scanout;
wire pref_inst_w;
wire excep_only_flush_w;
wire [7:0] load_lmq_entry;
wire dff_l2fill_scanin;
wire dff_l2fill_scanout;
wire l2fill_vld_m;
wire [7:0] ld_fill;
wire [7:0] ld_unfilled_in;
wire [7:0] ld_unfilled;
wire dff_unfilled_scanin;
wire dff_unfilled_scanout;
wire [7:0] ld_unfilled_out;
wire [7:0] ld_pcx_vld_set;
wire ncache_w;
wire ld_sec_hit_b;
wire tlb_pgnum_b39_b;
wire stb_cam_hit_b;
wire stb_cam_mhit_b;
wire stb_ld_part_raw_b;
wire dff_stb_raw_scanin;
wire dff_stb_raw_scanout;
wire stb_cam_hit_w;
wire stb_cam_mhit_w;
wire stb_ld_part_raw_w;
wire tlb_pgnum_b39_w;
wire ldbl_w;
wire ld_full_raw_w;
wire ld_part_raw_w;
wire ld_rawp_disabled_asi_b;
wire [7:0] ld_rawp_disabled_in;
wire [7:0] ld_rawp_disabled;
wire dff_rawp_disable_scanin;
wire dff_rawp_disable_scanout;
wire ld_rawp_disabled_asi_w;
wire [7:0] ld_rawp_disabled_out;
wire [7:0] ld_rawp_disabled_set;
wire [7:0] ldd_vld_in;
wire dff_ldd_vld_scanin;
wire dff_ldd_vld_scanout;
wire lmq_vld_enable_b;
wire lmq_vld_cancel_b;
wire dff_ld_lmq_en_b_scanin;
wire dff_ld_lmq_en_b_scanout;
wire lmq_vld_enable_w_pre;
wire lmq_vld_cancel_w_pre;
wire lmq_vld_cancel_w;
wire lmq_vld_enable_w;
wire [7:0] ld_pcx_vld_rst;
wire [7:0] ld_pcx_commit;
wire [7:0] kill_pcx_ld_req;
wire [7:0] bld_hold;
wire [7:0] perr_inv;
wire [7:0] ld_pcx_vld_in;
wire [7:0] ld_pcx_vld;
wire dff_ld_pcx_vld_scanin;
wire dff_ld_pcx_vld_scanout;
wire [7:0] ld_pcx_vld_out;
wire ld_asi_vld_set_b;
wire [7:0] ld_asi_vld_set;
wire ld_asi_vld_set_w;
wire [7:0] ld_asi_vld_in;
wire [7:0] ld_asi_vld_rst;
wire [7:0] ld_asi_vld;
wire dff_ld_asi_vld_scanin;
wire dff_ld_asi_vld_scanout;
wire [7:0] ld_asi_vld_out;
wire early_ld_cancel_w;
wire [7:0] ld_pcx_rq_vld;
wire early_ld_b_sel_p4;
wire block_ldd_req;
wire [7:0] ld_asi_rq_vld;
wire asi_indet_block;
wire [7:0] ld_rq_vld;
wire [7:0] load_miss_w;
wire ld_inst_unflushed_w;
wire ld_inst_vld_w;
wire lru8_scanin;
wire lru8_scanout;
wire [7:0] ld_rq_sel;
wire [7:0] ld_pcx_rq_sel;
wire [7:0] ld_asi_rq_sel;
wire ld_pcx_sel_p3;
wire ld_asi_sel_p3;
wire [7:0] ld_early_rq_sel;
wire [7:0] ld_all_rq_sel;
wire [7:0] st_atom_p4_dec;
wire dff_ld_sel_scanin;
wire dff_ld_sel_scanout;
wire [7:0] ld_all_sel_p4;
wire ld_pcx_sel_p4;
wire [3:0] ldd_count_p1;
wire [3:0] ldd_count;
wire [3:0] ldd_count_m1;
wire inc_ldd_count_pre;
wire dec_ldd_count;
wire [3:0] ldd_count_in;
wire inc_ldd_count;
wire dff_ldd_out_scanin;
wire dff_ldd_out_scanout;
wire cpq_stall;
wire casa_ld_to_pcx;
wire [3:0] st_atom_p3;
wire casa_bypass_d;
wire dff_st_atom_p4_scanin;
wire dff_st_atom_p4_scanout;
wire [3:0] st_atom_p4;
wire casa_bypass_e;
wire [3:0] st_atom_p4_in;
wire dff_st_atom_p5_scanin;
wire dff_st_atom_p5_scanout;
wire asi_indet_sel;
wire asi_indet_retire;
wire asi_indet_in;
wire dff_asi_indet_scanin;
wire dff_asi_indet_scanout;
wire dff_cpq_tid_scanin;
wire dff_cpq_tid_scanout;
wire ld_inst_nopref_b;
wire dff_ld_raw_w_scanin;
wire dff_ld_raw_w_scanout;
wire ld_inst_nopref_w;
wire [2:0] tid_w;
wire ld_raw_bypass_w;
wire dff_ld_raw_w2_scanin;
wire dff_ld_raw_w2_scanout;
wire ld_raw_bypass_w2;
wire [2:0] tid_w2;
wire dff_ld_raw_w3_scanin;
wire dff_ld_raw_w3_scanout;
wire ld_raw_bypass_w3;
wire [2:0] tid_w3;
wire sbdlc_err;
wire sbdlu_err;
wire [7:0] lmq_bypass_vld;
wire [7:0] ldbyp_vld_en;
wire [7:0] ldbyp_rst;
wire [7:0] ldbyp_vld;
wire dff_ldbyp_vld_scanin;
wire dff_ldbyp_vld_scanout;
wire ld_bypass_ok_d;
wire dff_ld_inst_e_scanin;
wire dff_ld_inst_e_scanout;
wire ld_bypass_ok_e;
wire byp_cnt_rst;
wire [2:0] byp_cnt_in;
wire [2:0] byp_cnt;
wire dff_byp_cnt_scanin;
wire dff_byp_cnt_scanout;
wire ld_bypass_e;
wire byp_vld_e;
wire [7:0] thrd_byp_sel_e;
wire dff_thrd_byp_sel_m_scanin;
wire dff_thrd_byp_sel_m_scanout;
wire [7:0] thrd_byp_sel_m;
wire [7:0] bld_inst_w;
wire [7:0] bld_pending;
wire [7:0] bld_pend_hold;
wire [7:0] bld_pending_in;
wire [7:0] bld_reset;
wire dff_bld_pending_scanin;
wire dff_bld_pending_scanout;
wire [1:0] bld_addr54_p3;
wire [1:0] bld_cnt0;
wire [1:0] bld_cnt1;
wire [1:0] bld_cnt2;
wire [1:0] bld_cnt3;
wire [1:0] bld_cnt4;
wire [1:0] bld_cnt5;
wire [1:0] bld_cnt6;
wire [1:0] bld_cnt7;
wire bld_req_p3;
wire dff_bld_addr_scanin;
wire dff_bld_addr_scanout;
wire [1:0] bld_cnt0_in;
wire inc_bld0_cnt;
wire dff_bld_cnt0_scanin;
wire dff_bld_cnt0_scanout;
wire [1:0] bld_cnt1_in;
wire inc_bld1_cnt;
wire dff_bld_cnt1_scanin;
wire dff_bld_cnt1_scanout;
wire [1:0] bld_cnt2_in;
wire inc_bld2_cnt;
wire dff_bld_cnt2_scanin;
wire dff_bld_cnt2_scanout;
wire [1:0] bld_cnt3_in;
wire inc_bld3_cnt;
wire dff_bld_cnt3_scanin;
wire dff_bld_cnt3_scanout;
wire [1:0] bld_cnt4_in;
wire inc_bld4_cnt;
wire dff_bld_cnt4_scanin;
wire dff_bld_cnt4_scanout;
wire [1:0] bld_cnt5_in;
wire inc_bld5_cnt;
wire dff_bld_cnt5_scanin;
wire dff_bld_cnt5_scanout;
wire [1:0] bld_cnt6_in;
wire inc_bld6_cnt;
wire dff_bld_cnt6_scanin;
wire dff_bld_cnt6_scanout;
wire [1:0] bld_cnt7_in;
wire inc_bld7_cnt;
wire dff_bld_cnt7_scanin;
wire dff_bld_cnt7_scanout;
wire [7:0] bld_annul_rst;
wire [7:0] bld_annul_in;
wire [7:0] bld_annul;
wire dff_bld_bypass_scanin;
wire dff_bld_bypass_scanout;
wire block_load_annul;
wire [7:0] bld_miss_set;
wire [7:0] bld_miss_in;
wire [7:0] bld_miss;
wire report_and_clear_error;
wire [7:0] bld_miss_out;
wire bld_pass7;
wire dff_bld_miss_scanin;
wire dff_bld_miss_scanout;
wire bld_pass7_done;
wire [7:0] pref_issued;
wire dff_pref_issued_scanin;
wire dff_pref_issued_scanout;
wire [7:0] perr_set;
wire [7:0] perr_inv_in;
wire dff_perr_scanin;
wire dff_perr_scanout;
wire ld_inv_p3;
wire [7:0] perr_inv_out;
wire ld_inv_p4;
wire lsu_dcvp_err_e2;
wire lsu_dctp_err_e2;
wire lsu_dcmh_err_e2;
wire lsu_dcdp_err_e2;
wire dff_dcerr_scanin;
wire dff_dcerr_scanout;
wire [1:0] l2_err;
wire [1:0] l2_err0;
wire [1:0] l2_err1;
wire [1:0] l2_err2;
wire [1:0] l2_err3;
wire [1:0] l2_err4;
wire [1:0] l2_err5;
wire [1:0] l2_err6;
wire [1:0] l2_err7;
wire [1:0] l2_err_qual;
wire [1:0] l2_err_new;
wire [1:0] l2_err0_in;
wire [1:0] l2_err1_in;
wire [1:0] l2_err2_in;
wire [1:0] l2_err3_in;
wire [1:0] l2_err4_in;
wire [1:0] l2_err5_in;
wire [1:0] l2_err6_in;
wire [1:0] l2_err7_in;
wire dff_l2errcode_scanin;
wire dff_l2errcode_scanout;
wire dcl2c_err;
wire dcl2u_err;
wire dcl2nd_err;
wire dff_l2err_scanin;
wire dff_l2err_scanout;
wire [2:0] stberr_tid;
wire dff_stberr_scanin;
wire dff_stberr_scanout;
wire [7:0] xinval_pend_in;
wire [7:0] xinval_pend;
wire cpq_xinval_m;
wire dff_xinval_pend_scanin;
wire dff_xinval_pend_scanout;
wire dff_bist_diag_scanin;
wire dff_bist_diag_scanout;
wire bist_or_diag_d;
wire spares_scanin;
wire spares_scanout;
wire [4:0] unused;


// Globals
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input	[2:0]	dcc_tid_m;
input		dcc_ld_inst_vld_m;
input		dcc_pref_inst_m;
input		dcc_ld_miss_b;		// A load that needs to go to L2
input		dcc_ld_miss_ldd;
input		dcc_asi_load_b;
input		dcc_asi_iomap_b;
input		dcc_blk_inst_b;		// Block load instruction in B
input		dcc_ldbl_b;
input		dcc_ncache_b;		// Non-cacheable ldst in B
input		dcc_ld_miss_ctl_b43;	// Non-cacheable request to pcx
input		dcc_atomic_b;	
input		dcc_casa_inst_b;
input		dcc_lsu_asi_rd_b;
input		dcc_lsu_asi_sel_w;
input		dcc_ceter_wr_w;
input		dcc_stb_diag_sel_w3;
input		dcc_exception_flush_b;
input		dcc_perror_b;
input		dcc_sync_pipe_w;
input		dcc_cache_diag_wr_b;

input	[7:0]	dcc_asi_rtn_vld;
input		dcc_asi_rtn_excp;
input		dcc_asi_rtn_rd;

input		pic_casa_squash_req;	// No loads can request this cycle
input		pic_early_ld_b_sel_p3;	// The load in B is going to the pcx
input		pic_no_load_p3;		// Load cannot issue in P3
input		pic_asi_busy;		// ASI ring cannot accept a request

input		lmd_pcx_pref;
input	[7:0]	lmd_asi_ld;
input	[7:0]	lmd_asi_indet;
input	[7:0]	lmd_sec_cmp_b;		// secondary hit compare results
input		lmd_addrb2;
input		lmd_sz_b1;
input		lmd_sz_b0;
input		lmd_ldbl;
input	[2:1]	lmd_rd_e;
input	[1:0]	lmd_dc_err_e;
input		lmd_fill_addr_b3_e;
input		lmd_fill_sz_b0_e;

input		tlb_pgnum_b39;
input		tlb_cam_mhit;

input		tlu_flush_lsu_b;	// Flush the instruction in B
input		tlu_cerer_sbdlc;
input		tlu_cerer_sbdlu;
input		tlu_cerer_dcl2c;
input		tlu_cerer_dcl2u;
input		tlu_cerer_dcl2nd;
input		tlu_cerer_l2c_socc;
input		tlu_cerer_l2u_socu;

input		dec_flush_lm;		// Flush the instruction in M
input		dec_flush_lb;		// Flush the instruction in B
input		dec_ld_inst_d;

input		cic_l2fill_vld_e;
input		cic_cpq_ld_rdy;
input		cic_cpq_ld_rdy_;
input		cic_div_stall_d;
input		cic_oddrd_e;
input		cic_xinval_e;		// xinval is being processed
input	[7:0]	cic_xinval;		// xinval arrived for a thread
input		cic_set_inval;
input		cic_rtn_cmplt;
input		cic_cpq_stall;
input		cic_ext_interrupt;

input	[2:0]	cid_tid;
input	[1:0]	cid_err;
input		cid_dcsoc_err_e;
input		cid_l2miss;

input		stb_cam_hit;
input		stb_cam_mhit;
input		stb_ld_part_raw;
input		stb_cecc_err;
input		stb_uecc_err;

input		sbd_st_data_b_62;

input	[7:0]	sbs_all_commited;

input	[7:0]	sbc_st_atom_p3;
input	[7:0]	sbc_rawp_rst;
input	[2:0]	sbc_st_sel_tid_p4;
input		sbc_force_inv;
input		sbc_kill_store_p4_;

input		lsu_lsu_pmen;

output	[7:0]	lmc_lmq_enable_b;	// Load enables for LMQ flops (threaded)
output	[7:0]	lmc_pcx_sel_p4;		// Which thread to send to pcx/asi
output		lmc_pcx_rq_vld;		// At least one thread is ready to issue
output		lmc_asi_rq_vld;		// At least one thread is ready to issue
output		lmc_ld_rq_p3;
output		lmc_ld_vld_p4;
output		lmc_ld_no_req_p4;	// Cancel the pcx request of the load
output		lmc_ld_inv_p4;
output	[2:0]	lmc_ld_tid;		// Thread ID of load selected for issue
output	[7:0]	lmc_byp_sel_e;		// Thread select for fill/bypass data
output	[2:0]	lmc_cpq_tid_m;		// Thread ID of current cpq packet
output	[7:0]	lmc_lmq_bypass_en;	// Load enable for the LMQ bypass registers
output		lmc_asi_bypass_m;	// ASI data is bypassing now
output	[1:0]	lmc_bld_addr54;		// Block load address modifier
output		lmc_bld_req;		// Current pcx req is for block load
output		lmc_bld_req_;
output		lmc_bld_annul;		
output		lmc_bld_miss_e;
output		lmc_bld_last_e;
output	[7:0]	lmc_rd_update;
output	[7:0]	lmc_pref_issued;	// Prefetch issued to pcx
output	[7:0]	lmc_ldd_vld;
output	[7:0]	lmc_ld_unfilled;
output		lmc_lmd_ncache_b;
output	[4:0]	lmc_ld_sz;
output		lmc_ld_inst_w;
output		lmc_full_raw_w;
output		lmc_ld_stall;		// stall pipe so bypass can complete
output		lmc_l2_err_noup;
output		lmc_l2_uerr;
output		lmc_byp_data_hi;
output		lmc_byp_data_enable;

output	[7:0]	lmc_thrd_byp_sel_e;	// Thread is bypassing (or filling)
output	[7:0]	lmc_thrd_byp_sel_m;	// Which thread's bypass register is bypassing
output	[2:0]	lmc_byp_tid_m;		// Which thread's bypass register is bypassing
output		lmc_byp_vld_m;		// A bypass is occuring
output	[4:0]	lmc_lmq0_byp_sel;	// source selects for load bypass registers
output	[4:0]	lmc_lmq1_byp_sel;	// source selects for load bypass registers
output	[4:0]	lmc_lmq2_byp_sel;	// source selects for load bypass registers
output	[4:0]	lmc_lmq3_byp_sel;	// source selects for load bypass registers
output	[4:0]	lmc_lmq4_byp_sel;	// source selects for load bypass registers
output	[4:0]	lmc_lmq5_byp_sel;	// source selects for load bypass registers
output	[4:0]	lmc_lmq6_byp_sel;	// source selects for load bypass registers
output	[4:0]	lmc_lmq7_byp_sel;	// source selects for load bypass registers
output		lmc_asi_indet_retire;	// indeterminate ASI load back from ring

output	[7:0]	lsu_ifu_no_miss;	// xinval pending so do not allow I$ miss

output		lsu_dcmh_err_g;
output		lsu_dcvp_err_g;
output		lsu_dctp_err_g;
output		lsu_dcdp_err_g;
output	[2:0]	lsu_dcerr_tid_g;

output		lsu_dcl2c_err_g;
output		lsu_dcl2u_err_g;
output		lsu_dcl2nd_err_g;

output		lsu_sbdlc_err_g;
output		lsu_sbdlu_err_g;
output	[2:0]	lsu_stberr_tid_g;

input		lbist_run;
input		mbi_run;
output		lmc_mbi_run;
output		lmc_bist_or_diag_e;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

//////////////////////////////
// Clock header
//////////////////////////////
lsu_lmc_ctll1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk                          ),
        .l1en   (1'b1                           ),
        .l1clk  (l1clk                          ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

lsu_lmc_ctll1clkhdr_ctl_macro rqpend_clkgen (
        .l2clk  (l2clk                          ),
        .l1en   (rqpend_clken                   ),
        .l1clk  (l1clk_pm1                      ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

assign cpq_mx_thread[0] = (cid_tid[2:0] == 3'd0);
assign cpq_mx_thread[1] = (cid_tid[2:0] == 3'd1);
assign cpq_mx_thread[2] = (cid_tid[2:0] == 3'd2);
assign cpq_mx_thread[3] = (cid_tid[2:0] == 3'd3);
assign cpq_mx_thread[4] = (cid_tid[2:0] == 3'd4);
assign cpq_mx_thread[5] = (cid_tid[2:0] == 3'd5);
assign cpq_mx_thread[6] = (cid_tid[2:0] == 3'd6);
assign cpq_mx_thread[7] = (cid_tid[2:0] == 3'd7);

assign ceter_pscce_in[0] = (dcc_ceter_wr_w & thread_w[0]) ? st_data_w_62 : ceter_pscce_reg[0];
assign ceter_pscce_in[1] = (dcc_ceter_wr_w & thread_w[1]) ? st_data_w_62 : ceter_pscce_reg[1];
assign ceter_pscce_in[2] = (dcc_ceter_wr_w & thread_w[2]) ? st_data_w_62 : ceter_pscce_reg[2];
assign ceter_pscce_in[3] = (dcc_ceter_wr_w & thread_w[3]) ? st_data_w_62 : ceter_pscce_reg[3];
assign ceter_pscce_in[4] = (dcc_ceter_wr_w & thread_w[4]) ? st_data_w_62 : ceter_pscce_reg[4];
assign ceter_pscce_in[5] = (dcc_ceter_wr_w & thread_w[5]) ? st_data_w_62 : ceter_pscce_reg[5];
assign ceter_pscce_in[6] = (dcc_ceter_wr_w & thread_w[6]) ? st_data_w_62 : ceter_pscce_reg[6];
assign ceter_pscce_in[7] = (dcc_ceter_wr_w & thread_w[7]) ? st_data_w_62 : ceter_pscce_reg[7];

lsu_lmc_ctlmsff_ctl_macro__width_9 dff_ceter  (
	.scan_in(dff_ceter_scanin),
	.scan_out(dff_ceter_scanout),
	.din	({sbd_st_data_b_62,ceter_pscce_in[7:0]}),
	.dout	({st_data_w_62,    ceter_pscce_reg[7:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ceter_pscce_cpq = (cpq_mx_thread[0] & ceter_pscce_reg[0]) |
                         (cpq_mx_thread[1] & ceter_pscce_reg[1]) | 
                         (cpq_mx_thread[2] & ceter_pscce_reg[2]) | 
                         (cpq_mx_thread[3] & ceter_pscce_reg[3]) | 
                         (cpq_mx_thread[4] & ceter_pscce_reg[4]) | 
                         (cpq_mx_thread[5] & ceter_pscce_reg[5]) | 
                         (cpq_mx_thread[6] & ceter_pscce_reg[6]) | 
                         (cpq_mx_thread[7] & ceter_pscce_reg[7]) ;

assign ceter_pscce_w3 = (thread_w3[0] & ceter_pscce_reg[0]) |
                        (thread_w3[1] & ceter_pscce_reg[1]) | 
                        (thread_w3[2] & ceter_pscce_reg[2]) | 
                        (thread_w3[3] & ceter_pscce_reg[3]) | 
                        (thread_w3[4] & ceter_pscce_reg[4]) | 
                        (thread_w3[5] & ceter_pscce_reg[5]) | 
                        (thread_w3[6] & ceter_pscce_reg[6]) | 
                        (thread_w3[7] & ceter_pscce_reg[7]) ;

lsu_lmc_ctlmsff_ctl_macro__width_7 dff_cerer  (
	.scan_in(dff_cerer_scanin),
	.scan_out(dff_cerer_scanout),
	.din	({tlu_cerer_sbdlc,tlu_cerer_sbdlu,tlu_cerer_dcl2c,tlu_cerer_dcl2u,tlu_cerer_dcl2nd,
		  tlu_cerer_l2c_socc, tlu_cerer_l2u_socu}),
	.dout	({    cerer_sbdlc,    cerer_sbdlu,    cerer_dcl2c,    cerer_dcl2u,    cerer_dcl2nd,
		  cerer_socc,         cerer_socu}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//////////////////////////////
// Thread decoding
//////////////////////////////

assign thread_b[0] = ~tid_b[2] & ~tid_b[1] & ~tid_b[0];
assign thread_b[1] = ~tid_b[2] & ~tid_b[1] &  tid_b[0];
assign thread_b[2] = ~tid_b[2] &  tid_b[1] & ~tid_b[0];
assign thread_b[3] = ~tid_b[2] &  tid_b[1] &  tid_b[0];
assign thread_b[4] =  tid_b[2] & ~tid_b[1] & ~tid_b[0];
assign thread_b[5] =  tid_b[2] & ~tid_b[1] &  tid_b[0];
assign thread_b[6] =  tid_b[2] &  tid_b[1] & ~tid_b[0];
assign thread_b[7] =  tid_b[2] &  tid_b[1] &  tid_b[0];

lsu_lmc_ctlmsff_ctl_macro__width_8 dff_thread_w  (
	.scan_in(dff_thread_w_scanin),
	.scan_out(dff_thread_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	(thread_b[7:0]),
	.dout	(thread_w[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

//////////////////////////////
// Instruction flushing
//////////////////////////////

lsu_lmc_ctlmsff_ctl_macro__width_1 dff_flush_b  (
	.scan_in(dff_flush_b_scanin),
	.scan_out(dff_flush_b_scanout),
	.din	(dec_flush_lm),
	.dout	(local_flush_b),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign flush_b = tlu_flush_lsu_b | dec_flush_lb | local_flush_b | dcc_exception_flush_b;
assign excep_only_flush_b = dcc_exception_flush_b & ~(tlu_flush_lsu_b | dec_flush_lb | local_flush_b);

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_flush_w  (
	.scan_in(dff_flush_w_scanin),
	.scan_out(dff_flush_w_scanout),
	.din	({flush_b,dcc_perror_b}),
	.dout	({flush_w,perror_w}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Enables to load miss information into the LMQ buffers
// LMQ buffers are written in the W stage, so the enable must be valid in B.
// ld_miss_b will be the critical signal.  If it's too late, the LMQ can be loaded
// on every miss and a separate signal used to track whether the load needs to go
// to L2, but this will mess up the LRU mechanism below, so I'd like to avoid it
// if possible.
////////////////////////////////////////////////////////////////////////////////

lsu_lmc_ctlmsff_ctl_macro__width_6 dff_inst_b  (
	.scan_in(dff_inst_b_scanin),
	.scan_out(dff_inst_b_scanout),
	.din	({dcc_ld_inst_vld_m, dcc_pref_inst_m, dcc_blk_inst_b,dcc_tid_m[2:0]}),
	.dout	({    ld_inst_vld_b,     pref_inst_b, blk_inst_w,    tid_b[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_inst_w  (
	.scan_in(dff_inst_w_scanin),
	.scan_out(dff_inst_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({pref_inst_b, excep_only_flush_b}),
	.dout	({pref_inst_w, excep_only_flush_w}),
  .siclk(siclk),
  .soclk(soclk)
);

assign load_lmq_entry[7:0] = (({8{ld_inst_vld_b}} & thread_b[7:0]) &
                                ~(({8{dcc_sync_pipe_w}} & thread_w[7:0]) | {8{local_flush_b}}));
assign lmc_lmq_enable_b[7:0] = load_lmq_entry[7:0] | lmc_rd_update[7:0];

////////////////////////////////////////////////////////////////////////////////
// Fill state of each entry.  An unfilled flag is set when the miss occurs
// and cleared when the cache is filled (or when the data is bypassed in the
// case of non-cacheable loads).
////////////////////////////////////////////////////////////////////////////////

lsu_lmc_ctlmsff_ctl_macro__width_1 dff_l2fill  (
	.scan_in(dff_l2fill_scanin),
	.scan_out(dff_l2fill_scanout),
	.din	(cic_l2fill_vld_e),
	.dout	(l2fill_vld_m),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ld_fill[0] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b000);
assign ld_fill[1] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b001);
assign ld_fill[2] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b010);
assign ld_fill[3] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b011);
assign ld_fill[4] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b100);
assign ld_fill[5] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b101);
assign ld_fill[6] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b110);
assign ld_fill[7] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b111);

assign ld_unfilled_in[7:0] = ld_unfilled[7:0] & ~ld_fill[7:0];

lsu_lmc_ctlmsff_ctl_macro__width_8 dff_unfilled  (
	.scan_in(dff_unfilled_scanin),
	.scan_out(dff_unfilled_scanout),
	.din	(ld_unfilled_in[7:0]),
	.dout	(ld_unfilled_out[7:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign ld_unfilled[7:0] = (ld_pcx_vld_set[7:0] & {8{~ncache_w}}) | ld_unfilled_out[7:0];

////////////////////////////////////////////////////////////////////////////////
// Secondary miss processing
// A load miss is considered secondary if it matches a load from another thread
// that has a miss pending.  In this case, the secondary load will be marked
// as non-cacheable to avoid cache pollution. 
////////////////////////////////////////////////////////////////////////////////

assign lmc_ld_unfilled[7:0] = ld_unfilled[7:0];

assign ld_sec_hit_b = (|(lmd_sec_cmp_b[7:0]) & ~dcc_asi_load_b);

assign lmc_lmd_ncache_b = dcc_ld_miss_ctl_b43 | ld_sec_hit_b;

////////////////////////////////////////////////////////////////////////////////
// Partial RAW handling
// Partial RAWs and loads treated like partial raws (full raw to multiple stb
// entries) cannot issue to the pcx until dependent stores have been committed
// to the pcx.  The depedency tracking is done in lsu_sbc_ctl.
////////////////////////////////////////////////////////////////////////////////

assign tlb_pgnum_b39_b = ld_inst_vld_b & tlb_pgnum_b39 & ~tlb_cam_mhit;

assign stb_cam_hit_b     = stb_cam_hit     & ~(lbist_run | lmc_mbi_run);
assign stb_cam_mhit_b    = stb_cam_mhit    & ~(lbist_run | lmc_mbi_run);
assign stb_ld_part_raw_b = stb_ld_part_raw & ~(lbist_run | lmc_mbi_run);

lsu_lmc_ctlmsff_ctl_macro__width_5 dff_stb_raw  (
	.scan_in(dff_stb_raw_scanin),
	.scan_out(dff_stb_raw_scanout),
	.l1clk	(l1clk_pm1),
	.din	({stb_cam_hit_b,stb_cam_mhit_b,stb_ld_part_raw_b,tlb_pgnum_b39_b,dcc_ldbl_b}),
	.dout	({stb_cam_hit_w,stb_cam_mhit_w,stb_ld_part_raw_w,tlb_pgnum_b39_w,ldbl_w}),
  .siclk(siclk),
  .soclk(soclk)
);

assign ld_full_raw_w = stb_cam_hit_w & ~ld_part_raw_w;
assign ld_part_raw_w = stb_ld_part_raw_w |			// a partial hit
                       stb_cam_mhit_w |				// multiple hits
                       tlb_pgnum_b39_w |			// IO load
                       (ldbl_w & stb_cam_hit_w) ;		// BLD/QUAD/LDD

assign ld_rawp_disabled_asi_b = (dcc_asi_load_b & ~dcc_lsu_asi_rd_b) & ld_inst_vld_b;

assign ld_rawp_disabled_in[7:0] = (ld_rawp_disabled[7:0] & ~sbc_rawp_rst[7:0]) & ~sbs_all_commited[7:0];

lsu_lmc_ctlmsff_ctl_macro__width_9 dff_rawp_disable  (
	.scan_in(dff_rawp_disable_scanin),
	.scan_out(dff_rawp_disable_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ld_rawp_disabled_asi_b,ld_rawp_disabled_in[7:0]}),
	.dout	({ld_rawp_disabled_asi_w,ld_rawp_disabled_out[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Don't change or remove this signal name.  It's used by the bench.
assign ld_rawp_disabled_set[7:0] = {8{ (ld_rawp_disabled_asi_w | ld_part_raw_w) & ~flush_w }} & thread_w[7:0];	

assign ld_rawp_disabled[7:0] = ld_rawp_disabled_set[7:0] | ld_rawp_disabled_out[7:0];

////////////////////////////////////////////////////////////////////////////////
// Track ldd flags here.  They used to be part of lmq entry in lsu_lmd_dp, but
// they need to be here for timing.
////////////////////////////////////////////////////////////////////////////////

assign ldd_vld_in[7:0] = ( load_lmq_entry[7:0] & {8{dcc_ld_miss_ldd}}) |
                         (~load_lmq_entry[7:0] & lmc_ldd_vld[7:0]);

lsu_lmc_ctlmsff_ctl_macro__width_8 dff_ldd_vld  (
	.scan_in(dff_ldd_vld_scanin),
	.scan_out(dff_ldd_vld_scanout),
	.l1clk	(l1clk_pm1),
	.din	(ldd_vld_in[7:0]),
	.dout	(lmc_ldd_vld[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// PCX and ASI Load Control
// An LMQ entry is ready to issue to the pcx when it is loaded.
// The request is cleared once the entry successfully issues to the pcx.
//
//	B	|	W/P3	|	P4	
//		|		|		
// miss detected| LMQ loaded	| packet to gasket	
//		| request set	|		
//		| arb for pcx	|		
//
// Arbitration among threads with pending load requests happens here.  Arbitration
// between the pcx sources (loads and stores) happens in the pic control block.
////////////////////////////////////////////////////////////////////////////////

// Load misses issue to the pcx with the following exceptions
// - internal ASI's which aren't IO mapped (they go to the ASI ring instead)
// - atomics (the STB arbitrates for these)
// - prefetches always issue, regardless
// - full raw

assign lmq_vld_enable_b = dcc_ld_miss_b & ld_inst_vld_b;
assign lmq_vld_cancel_b = (dcc_asi_load_b & ~dcc_asi_iomap_b) | dcc_atomic_b;

lsu_lmc_ctlmsff_ctl_macro__width_3 dff_ld_lmq_en_b  (
	.scan_in(dff_ld_lmq_en_b_scanin),
	.scan_out(dff_ld_lmq_en_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({lmq_vld_enable_b,    lmq_vld_cancel_b,    lmc_lmd_ncache_b}),
	.dout	({lmq_vld_enable_w_pre,lmq_vld_cancel_w_pre,ncache_w}),
  .siclk(siclk),
  .soclk(soclk)
);
assign lmq_vld_cancel_w = lmq_vld_cancel_w_pre | ld_full_raw_w;
assign lmq_vld_enable_w = (lmq_vld_enable_w_pre | ld_part_raw_w) & ~lmq_vld_cancel_w;

// PCX requests pending
assign ld_pcx_vld_set[0] = lmq_vld_enable_w & ~flush_w & thread_w[0];
assign ld_pcx_vld_set[1] = lmq_vld_enable_w & ~flush_w & thread_w[1];
assign ld_pcx_vld_set[2] = lmq_vld_enable_w & ~flush_w & thread_w[2];
assign ld_pcx_vld_set[3] = lmq_vld_enable_w & ~flush_w & thread_w[3];
assign ld_pcx_vld_set[4] = lmq_vld_enable_w & ~flush_w & thread_w[4];
assign ld_pcx_vld_set[5] = lmq_vld_enable_w & ~flush_w & thread_w[5];
assign ld_pcx_vld_set[6] = lmq_vld_enable_w & ~flush_w & thread_w[6];
assign ld_pcx_vld_set[7] = lmq_vld_enable_w & ~flush_w & thread_w[7];

assign ld_pcx_vld_rst[7:0] = (ld_pcx_commit[7:0] | kill_pcx_ld_req[7:0]) & ~(bld_hold[7:0] | perr_inv[7:0]);

assign ld_pcx_vld_in[7:0] = ~ld_pcx_vld_rst[7:0] & ld_pcx_vld[7:0];

lsu_lmc_ctlmsff_ctl_macro__width_8 dff_ld_pcx_vld  (
	.scan_in(dff_ld_pcx_vld_scanin),
	.scan_out(dff_ld_pcx_vld_scanout),
	.l1clk	(l1clk_pm1),
	.din	(ld_pcx_vld_in[7:0]),
	.dout	(ld_pcx_vld_out[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
assign ld_pcx_vld[7:0] = ld_pcx_vld_set[7:0] | ld_pcx_vld_out[7:0];

// ASI requests pending
assign ld_asi_vld_set_b = dcc_asi_load_b & ~dcc_asi_iomap_b & ~dcc_lsu_asi_rd_b;

assign ld_asi_vld_set[0] = ld_asi_vld_set_w & ~flush_w & thread_w[0];
assign ld_asi_vld_set[1] = ld_asi_vld_set_w & ~flush_w & thread_w[1];
assign ld_asi_vld_set[2] = ld_asi_vld_set_w & ~flush_w & thread_w[2];
assign ld_asi_vld_set[3] = ld_asi_vld_set_w & ~flush_w & thread_w[3];
assign ld_asi_vld_set[4] = ld_asi_vld_set_w & ~flush_w & thread_w[4];
assign ld_asi_vld_set[5] = ld_asi_vld_set_w & ~flush_w & thread_w[5];
assign ld_asi_vld_set[6] = ld_asi_vld_set_w & ~flush_w & thread_w[6];
assign ld_asi_vld_set[7] = ld_asi_vld_set_w & ~flush_w & thread_w[7];

assign ld_asi_vld_in[7:0] = ~ld_asi_vld_rst[7:0] & ld_asi_vld[7:0];

lsu_lmc_ctlmsff_ctl_macro__width_9 dff_ld_asi_vld  (
	.scan_in(dff_ld_asi_vld_scanin),
	.scan_out(dff_ld_asi_vld_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ld_asi_vld_set_b,ld_asi_vld_in[7:0]}),
	.dout	({ld_asi_vld_set_w,ld_asi_vld_out[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign ld_asi_vld[7:0] = ld_asi_vld_set[7:0] | ld_asi_vld_out[7:0];

// Is the load which made an early request still valid?
assign early_ld_cancel_w = ld_full_raw_w | ld_part_raw_w | flush_w | perror_w;

// A thread should never have pcx and asi requests valid simultaneously
// 0in bits_on -var {ld_pcx_vld[0],ld_asi_vld[0]} -max 1 -message "PCX and ASI load requests for thread 0" 
// 0in bits_on -var {ld_pcx_vld[1],ld_asi_vld[1]} -max 1 -message "PCX and ASI load requests for thread 1" 
// 0in bits_on -var {ld_pcx_vld[2],ld_asi_vld[2]} -max 1 -message "PCX and ASI load requests for thread 2" 
// 0in bits_on -var {ld_pcx_vld[3],ld_asi_vld[3]} -max 1 -message "PCX and ASI load requests for thread 3" 
// 0in bits_on -var {ld_pcx_vld[4],ld_asi_vld[4]} -max 1 -message "PCX and ASI load requests for thread 4" 
// 0in bits_on -var {ld_pcx_vld[5],ld_asi_vld[5]} -max 1 -message "PCX and ASI load requests for thread 5" 
// 0in bits_on -var {ld_pcx_vld[6],ld_asi_vld[6]} -max 1 -message "PCX and ASI load requests for thread 6" 
// 0in bits_on -var {ld_pcx_vld[7],ld_asi_vld[7]} -max 1 -message "PCX and ASI load requests for thread 7" 

//////////////////////
// P3 stage
//////////////////////

// Generate valid pcx and asi requests.
// PCX requests can be cancelled by rawp conditions
// ASI requests can be cancelled by rawp conditions and by another outstanding indeterminate.

assign ld_pcx_rq_vld[7:0] = ld_pcx_vld[7:0] & ~ld_rawp_disabled[7:0] & ~({8{early_ld_b_sel_p4}} & thread_w[7:0]) & ~({8{block_ldd_req}} & lmc_ldd_vld[7:0]);
assign ld_asi_rq_vld[7:0] = ld_asi_vld[7:0] & ~ld_rawp_disabled[7:0] & ~(lmd_asi_ld[7:0] & lmd_asi_indet[7:0] & {8{asi_indet_block}});

assign ld_rq_vld[7:0] = ld_pcx_rq_vld[7:0] | ld_asi_rq_vld[7:0];
assign lmc_ld_rq_p3 = |(ld_rq_vld[7:0]);

// Pseudo-LRU picker to choose the oldest thread for issuing to pcx.
// LRU state is updated after a load is put into the miss queue
assign load_miss_w[7:0] = {8{(ld_inst_unflushed_w | (ld_inst_vld_w & ~flush_w))}} & thread_w[7:0] & (ld_pcx_vld[7:0] | ld_asi_vld[7:0]);

lsu_lru8_ctl lru8 (
	.scan_in(lru8_scanin),
	.scan_out(lru8_scanout),
	.request	(ld_rq_vld[7:0]),
	.enable		(load_miss_w[7:0]),
	.select		(ld_rq_sel[7:0]),
  .l1clk(l1clk),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

// Tell pic if request was pcx or asi
assign lmc_pcx_rq_vld = |(ld_rq_sel[7:0] & ld_pcx_rq_vld[7:0]);
assign lmc_asi_rq_vld = |(ld_rq_sel[7:0] & ld_asi_rq_vld[7:0]);

// A request wins arbitration to the pcx if it's thread is selected AND
// the load port wins source arbitration.
// Loads will win over stores unless blocked by pic_no_load_p3
assign ld_pcx_rq_sel[7:0]   = ld_rq_sel[7:0] & ld_pcx_rq_vld[7:0] & {8{~pic_no_load_p3}};
assign ld_asi_rq_sel[7:0]   = ld_rq_sel[7:0] & ld_asi_rq_vld[7:0] & {8{~(pic_no_load_p3 | pic_asi_busy)}};
assign ld_pcx_sel_p3 = |(ld_pcx_rq_sel[7:0]);
assign ld_asi_sel_p3 = |(ld_asi_rq_sel[7:0]);

assign ld_early_rq_sel[7:0] = {8{~(ld_pcx_sel_p3 | ld_asi_sel_p3 | pic_casa_squash_req)}} & thread_b[7:0];
assign ld_all_rq_sel[7:0] = ld_pcx_rq_sel[7:0] | ld_asi_rq_sel[7:0] | ld_early_rq_sel[7:0] | st_atom_p4_dec[7:0];

assign ld_pcx_commit[7:0] = ld_pcx_rq_sel[7:0];
assign ld_asi_vld_rst[7:0] = ld_asi_rq_sel[7:0];

lsu_lmc_ctlmsff_ctl_macro__width_10 dff_ld_sel  (
	.scan_in(dff_ld_sel_scanin),
	.scan_out(dff_ld_sel_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ld_all_rq_sel[7:0],ld_pcx_sel_p3,pic_early_ld_b_sel_p3}),
	.dout	({ld_all_sel_p4[7:0],ld_pcx_sel_p4, early_ld_b_sel_p4}),
  .siclk(siclk),
  .soclk(soclk)
);

// Need to throttle the number of outstanding LDD requests to avoid CPQ overflow.  
// No more LDD requests can be sent if
// (i) Number of outstanding requests is 14   OR
// (ii)cic is issuing a stall due to CPQ above high water mark
// Counter is incremented one cycle late to ease timing.

assign ldd_count_p1[3:0] = ldd_count[3:0] + 4'b0001;
assign ldd_count_m1[3:0] = ldd_count[3:0] - 4'b0001;

assign inc_ldd_count_pre = |(ld_pcx_rq_sel[7:0] & lmc_ldd_vld[7:0] & ~perr_inv[7:0]);
assign dec_ldd_count = cic_oddrd_e;
assign ldd_count_in[3:0] = ({4{inc_ldd_count & ~dec_ldd_count}} & ldd_count_p1[3:0]) |
                           ({4{dec_ldd_count & ~inc_ldd_count}} & ldd_count_m1[3:0]) |
                           ({4{inc_ldd_count ~^ dec_ldd_count}} & ldd_count[3:0]) ;

lsu_lmc_ctlmsff_ctl_macro__width_6 dff_ldd_out  (
	.scan_in(dff_ldd_out_scanin),
	.scan_out(dff_ldd_out_scanout),
	.din	({cic_cpq_stall,inc_ldd_count_pre,ldd_count_in[3:0]}),
	.dout	({cpq_stall,    inc_ldd_count    ,ldd_count[3:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign block_ldd_req = (ldd_count[3:2]==2'b11 & (ldd_count[1] | ldd_count[0] & inc_ldd_count)) | cpq_stall;

//////////////////////
// P4 stage
//////////////////////

assign lmc_ld_no_req_p4 = early_ld_b_sel_p4 & early_ld_cancel_w;

assign kill_pcx_ld_req[7:0] = {8{(early_ld_b_sel_p4 & ~early_ld_cancel_w)}} & thread_w[7:0];

assign lmc_ld_vld_p4 = (casa_ld_to_pcx) | 			// CAS packet 2
                       (ld_pcx_sel_p4) |			// queued miss request
                       (early_ld_b_sel_p4 & ~early_ld_cancel_w);// early B/W request

assign lmc_pcx_sel_p4[7:0] = ld_all_sel_p4[7:0];

assign lmc_ld_tid[2] = lmc_pcx_sel_p4[7] | lmc_pcx_sel_p4[6] | lmc_pcx_sel_p4[5] | lmc_pcx_sel_p4[4];
assign lmc_ld_tid[1] = lmc_pcx_sel_p4[7] | lmc_pcx_sel_p4[6] | lmc_pcx_sel_p4[3] | lmc_pcx_sel_p4[2];
assign lmc_ld_tid[0] = lmc_pcx_sel_p4[7] | lmc_pcx_sel_p4[5] | lmc_pcx_sel_p4[3] | lmc_pcx_sel_p4[1];

// Encode this info to save some flops. [3]=valid,[2:0]=tid
assign st_atom_p3[3] = |(sbc_st_atom_p3[7:0]);
assign st_atom_p3[2] = sbc_st_atom_p3[7] | sbc_st_atom_p3[6] | sbc_st_atom_p3[5] | sbc_st_atom_p3[4];
assign st_atom_p3[1] = sbc_st_atom_p3[7] | sbc_st_atom_p3[6] | sbc_st_atom_p3[3] | sbc_st_atom_p3[2];
assign st_atom_p3[0] = sbc_st_atom_p3[7] | sbc_st_atom_p3[5] | sbc_st_atom_p3[3] | sbc_st_atom_p3[1];

assign casa_bypass_d = st_atom_p3[3];

lsu_lmc_ctlmsff_ctl_macro__width_4 dff_st_atom_p4  (
	.scan_in(dff_st_atom_p4_scanin),
	.scan_out(dff_st_atom_p4_scanout),
	.din	(st_atom_p3[3:0]),
	.dout	(st_atom_p4[3:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// If casa is using the bypass register, other bypasses must be blocked.
assign casa_bypass_e = st_atom_p4[3];

// If STB read of CAS1 had an error, kill the CAS2 and restart the thread
assign st_atom_p4_in[3] = st_atom_p4[3] & sbc_kill_store_p4_;
assign st_atom_p4_in[2:0] = st_atom_p4[2:0];

assign st_atom_p4_dec[0] = st_atom_p4[3] & ~st_atom_p4[2] & ~st_atom_p4[1] & ~st_atom_p4[0];
assign st_atom_p4_dec[1] = st_atom_p4[3] & ~st_atom_p4[2] & ~st_atom_p4[1] &  st_atom_p4[0];
assign st_atom_p4_dec[2] = st_atom_p4[3] & ~st_atom_p4[2] &  st_atom_p4[1] & ~st_atom_p4[0];
assign st_atom_p4_dec[3] = st_atom_p4[3] & ~st_atom_p4[2] &  st_atom_p4[1] &  st_atom_p4[0];
assign st_atom_p4_dec[4] = st_atom_p4[3] &  st_atom_p4[2] & ~st_atom_p4[1] & ~st_atom_p4[0];
assign st_atom_p4_dec[5] = st_atom_p4[3] &  st_atom_p4[2] & ~st_atom_p4[1] &  st_atom_p4[0];
assign st_atom_p4_dec[6] = st_atom_p4[3] &  st_atom_p4[2] &  st_atom_p4[1] & ~st_atom_p4[0];
assign st_atom_p4_dec[7] = st_atom_p4[3] &  st_atom_p4[2] &  st_atom_p4[1] &  st_atom_p4[0];

lsu_lmc_ctlmsff_ctl_macro__width_1 dff_st_atom_p5  (
	.scan_in(dff_st_atom_p5_scanin),
	.scan_out(dff_st_atom_p5_scanout),
	.din	(st_atom_p4_in[3]),
	.dout	(casa_ld_to_pcx),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Indeterminate ASI blocks

assign asi_indet_sel = |(ld_asi_vld_rst[7:0] & lmd_asi_indet[7:0]); 
assign asi_indet_retire = (lmc_lmq0_byp_sel[1] & lmd_asi_indet[0]) |
                          (lmc_lmq1_byp_sel[1] & lmd_asi_indet[1]) |
                          (lmc_lmq2_byp_sel[1] & lmd_asi_indet[2]) |
                          (lmc_lmq3_byp_sel[1] & lmd_asi_indet[3]) |
                          (lmc_lmq4_byp_sel[1] & lmd_asi_indet[4]) |
                          (lmc_lmq5_byp_sel[1] & lmd_asi_indet[5]) |
                          (lmc_lmq6_byp_sel[1] & lmd_asi_indet[6]) |
                          (lmc_lmq7_byp_sel[1] & lmd_asi_indet[7]) ;

assign lmc_asi_indet_retire = asi_indet_retire;

assign asi_indet_in = asi_indet_sel | (asi_indet_block & ~asi_indet_retire);

lsu_lmc_ctlmsff_ctl_macro__width_1 dff_asi_indet  (
	.scan_in(dff_asi_indet_scanin),
	.scan_out(dff_asi_indet_scanout),
	.din    (asi_indet_in),
	.dout   (asi_indet_block),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Data return
////////////////////////////////////////////////////////////////////////////////

// Select the correct thread's LMQ
assign lmc_byp_sel_e[0] = cpq_mx_thread[0] & cic_cpq_ld_rdy |
                           lmc_thrd_byp_sel_e[0];
assign lmc_byp_sel_e[1] = cpq_mx_thread[1] & cic_cpq_ld_rdy |
                           lmc_thrd_byp_sel_e[1];
assign lmc_byp_sel_e[2] = cpq_mx_thread[2] & cic_cpq_ld_rdy |
                           lmc_thrd_byp_sel_e[2];
assign lmc_byp_sel_e[3] = cpq_mx_thread[3] & cic_cpq_ld_rdy |
                           lmc_thrd_byp_sel_e[3];
assign lmc_byp_sel_e[4] = cpq_mx_thread[4] & cic_cpq_ld_rdy |
                           lmc_thrd_byp_sel_e[4];
assign lmc_byp_sel_e[5] = cpq_mx_thread[5] & cic_cpq_ld_rdy |
                           lmc_thrd_byp_sel_e[5];
assign lmc_byp_sel_e[6] = cpq_mx_thread[6] & cic_cpq_ld_rdy |
                           lmc_thrd_byp_sel_e[6];
assign lmc_byp_sel_e[7] = cpq_mx_thread[7] & cic_cpq_ld_rdy |
                           lmc_thrd_byp_sel_e[7];

lsu_lmc_ctlmsff_ctl_macro__width_3 dff_cpq_tid  (
	.scan_in(dff_cpq_tid_scanin),
	.scan_out(dff_cpq_tid_scanout),
	.din	(cid_tid[2:0]),
	.dout	(lmc_cpq_tid_m[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// LMQ bypassing
////////////////////////////////////////////////////////////////////////////////

assign ld_inst_nopref_b = ld_inst_vld_b & ~pref_inst_b;

lsu_lmc_ctlmsff_ctl_macro__width_4 dff_ld_raw_w  (
	.scan_in(dff_ld_raw_w_scanin),
	.scan_out(dff_ld_raw_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ld_inst_nopref_b,tid_b[2:0]}),
	.dout	({ld_inst_nopref_w,tid_w[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign ld_inst_unflushed_w = ld_inst_nopref_w & ~flush_w;
assign lmc_ld_inst_w = ld_inst_unflushed_w;

assign ld_raw_bypass_w = ld_inst_unflushed_w & ld_full_raw_w & ~stb_cam_mhit_w & ~ldbl_w;

assign lmc_full_raw_w = ld_raw_bypass_w;

lsu_lmc_ctlmsff_ctl_macro__width_4 dff_ld_raw_w2  (
	.scan_in(dff_ld_raw_w2_scanin),
	.scan_out(dff_ld_raw_w2_scanout),
	.din	({ld_raw_bypass_w, tid_w[2:0]}),
	.dout	({ld_raw_bypass_w2,tid_w2[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_lmc_ctlmsff_ctl_macro__width_4 dff_ld_raw_w3  (
	.scan_in(dff_ld_raw_w3_scanin),
	.scan_out(dff_ld_raw_w3_scanout),
	.din	({ld_raw_bypass_w2,tid_w2[2:0]}),
	.dout	({ld_raw_bypass_w3,tid_w3[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign thread_w3[0] = ~tid_w3[2] & ~tid_w3[1] & ~tid_w3[0];
assign thread_w3[1] = ~tid_w3[2] & ~tid_w3[1] &  tid_w3[0];
assign thread_w3[2] = ~tid_w3[2] &  tid_w3[1] & ~tid_w3[0];
assign thread_w3[3] = ~tid_w3[2] &  tid_w3[1] &  tid_w3[0];
assign thread_w3[4] =  tid_w3[2] & ~tid_w3[1] & ~tid_w3[0];
assign thread_w3[5] =  tid_w3[2] & ~tid_w3[1] &  tid_w3[0];
assign thread_w3[6] =  tid_w3[2] &  tid_w3[1] & ~tid_w3[0];
assign thread_w3[7] =  tid_w3[2] &  tid_w3[1] &  tid_w3[0];

// Select the source to load into the bypass register 
// [0] - swap data for CAS operation
// [1] - load return data from the ASI interface
// [2] - raw bypass from stb
// [3] - ldxa asi read data from registers internal to LSU (left side)
// [4] - ldxa asi read data from registers internal to LSU (right side)
// [5] - error code from L2
assign lmc_lmq0_byp_sel[0] = dcc_casa_inst_b & thread_b[0] & ~(dcc_sync_pipe_w & thread_w[0]) & ~local_flush_b;
assign lmc_lmq1_byp_sel[0] = dcc_casa_inst_b & thread_b[1] & ~(dcc_sync_pipe_w & thread_w[1]) & ~local_flush_b;
assign lmc_lmq2_byp_sel[0] = dcc_casa_inst_b & thread_b[2] & ~(dcc_sync_pipe_w & thread_w[2]) & ~local_flush_b;
assign lmc_lmq3_byp_sel[0] = dcc_casa_inst_b & thread_b[3] & ~(dcc_sync_pipe_w & thread_w[3]) & ~local_flush_b;
assign lmc_lmq4_byp_sel[0] = dcc_casa_inst_b & thread_b[4] & ~(dcc_sync_pipe_w & thread_w[4]) & ~local_flush_b;
assign lmc_lmq5_byp_sel[0] = dcc_casa_inst_b & thread_b[5] & ~(dcc_sync_pipe_w & thread_w[5]) & ~local_flush_b;
assign lmc_lmq6_byp_sel[0] = dcc_casa_inst_b & thread_b[6] & ~(dcc_sync_pipe_w & thread_w[6]) & ~local_flush_b;
assign lmc_lmq7_byp_sel[0] = dcc_casa_inst_b & thread_b[7] & ~(dcc_sync_pipe_w & thread_w[7]) & ~local_flush_b;

assign lmc_lmq0_byp_sel[1] = dcc_asi_rtn_vld[0] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp;
assign lmc_lmq1_byp_sel[1] = dcc_asi_rtn_vld[1] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp;
assign lmc_lmq2_byp_sel[1] = dcc_asi_rtn_vld[2] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp;
assign lmc_lmq3_byp_sel[1] = dcc_asi_rtn_vld[3] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp;
assign lmc_lmq4_byp_sel[1] = dcc_asi_rtn_vld[4] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp;
assign lmc_lmq5_byp_sel[1] = dcc_asi_rtn_vld[5] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp;
assign lmc_lmq6_byp_sel[1] = dcc_asi_rtn_vld[6] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp;
assign lmc_lmq7_byp_sel[1] = dcc_asi_rtn_vld[7] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp;

assign lmc_lmq0_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[0];
assign lmc_lmq1_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[1];
assign lmc_lmq2_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[2];
assign lmc_lmq3_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[3];
assign lmc_lmq4_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[4];
assign lmc_lmq5_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[5];
assign lmc_lmq6_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[6];
assign lmc_lmq7_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[7];

assign lmc_lmq0_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[0] & ~flush_w;
assign lmc_lmq1_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[1] & ~flush_w;
assign lmc_lmq2_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[2] & ~flush_w;
assign lmc_lmq3_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[3] & ~flush_w;
assign lmc_lmq4_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[4] & ~flush_w;
assign lmc_lmq5_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[5] & ~flush_w;
assign lmc_lmq6_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[6] & ~flush_w;
assign lmc_lmq7_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[7] & ~flush_w;

assign lmc_lmq0_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[0];
assign lmc_lmq1_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[1];
assign lmc_lmq2_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[2];
assign lmc_lmq3_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[3];
assign lmc_lmq4_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[4];
assign lmc_lmq5_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[5];
assign lmc_lmq6_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[6];
assign lmc_lmq7_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[7];

assign lmc_lmq_bypass_en[0] = |(lmc_lmq0_byp_sel[4:0]);
assign lmc_lmq_bypass_en[1] = |(lmc_lmq1_byp_sel[4:0]);
assign lmc_lmq_bypass_en[2] = |(lmc_lmq2_byp_sel[4:0]);
assign lmc_lmq_bypass_en[3] = |(lmc_lmq3_byp_sel[4:0]);
assign lmc_lmq_bypass_en[4] = |(lmc_lmq4_byp_sel[4:0]);
assign lmc_lmq_bypass_en[5] = |(lmc_lmq5_byp_sel[4:0]);
assign lmc_lmq_bypass_en[6] = |(lmc_lmq6_byp_sel[4:0]);
assign lmc_lmq_bypass_en[7] = |(lmc_lmq7_byp_sel[4:0]);

// This indicates bypass data ready to bypass back to the registers.
// It should not be valid for CAS/DIAG storage
assign lmq_bypass_vld[0] = |(lmc_lmq0_byp_sel[4:1]);
assign lmq_bypass_vld[1] = |(lmc_lmq1_byp_sel[4:1]);
assign lmq_bypass_vld[2] = |(lmc_lmq2_byp_sel[4:1]);
assign lmq_bypass_vld[3] = |(lmc_lmq3_byp_sel[4:1]);
assign lmq_bypass_vld[4] = |(lmc_lmq4_byp_sel[4:1]);
assign lmq_bypass_vld[5] = |(lmc_lmq5_byp_sel[4:1]);
assign lmq_bypass_vld[6] = |(lmc_lmq6_byp_sel[4:1]);
assign lmq_bypass_vld[7] = |(lmc_lmq7_byp_sel[4:1]);

// Valid tracking
assign ldbyp_vld_en[7:0] = ~ldbyp_rst[7:0] &				// Reset
                            (lmq_bypass_vld[7:0] | ldbyp_vld[7:0]);	// Set/hold

lsu_lmc_ctlmsff_ctl_macro__width_8 dff_ldbyp_vld  (
	.scan_in(dff_ldbyp_vld_scanin),
	.scan_out(dff_ldbyp_vld_scanout),
	.din	(ldbyp_vld_en[7:0]),
	.dout	(ldbyp_vld[7:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// A valid entry ready for bypass can only go when there are no loads
// in the pipe and no data coming from the CPQ.

assign ld_bypass_ok_d = ~dec_ld_inst_d & ~cic_div_stall_d & ~casa_bypass_d;

lsu_lmc_ctlmsff_ctl_macro__width_1 dff_ld_inst_e  (
	.scan_in(dff_ld_inst_e_scanin),
	.scan_out(dff_ld_inst_e_scanout),
	.din	(ld_bypass_ok_d),
	.dout	(ld_bypass_ok_e),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Because of the low priority of bypass, and because of the fixed thread priority,
// there is a livelock concern.  If a bypass has been ready for eight cycles without
// proceeding, a decode block will be issued to free up the pipe.  The block will
// be removed once the bypass queue clears.

assign byp_cnt_rst = &(~ldbyp_vld[7:0] | lmc_thrd_byp_sel_e[7:0]);
assign byp_cnt_in[2:0] = {3{~byp_cnt_rst}} & (lmc_ld_stall ? byp_cnt[2:0] : (byp_cnt[2:0] + 3'b001));

lsu_lmc_ctlmsff_ctl_macro__width_3 dff_byp_cnt  (
	.scan_in(dff_byp_cnt_scanin),
	.scan_out(dff_byp_cnt_scanout),
	.din	(byp_cnt_in[2:0]),
	.dout	(byp_cnt[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign lmc_ld_stall = &(byp_cnt[2:0]);

assign ld_bypass_e = ld_bypass_ok_e & cic_cpq_ld_rdy_;

assign lmc_thrd_byp_sel_e[0] = ldbyp_vld[0] &                      ld_bypass_e;
assign lmc_thrd_byp_sel_e[1] = ldbyp_vld[1] & ~ldbyp_vld[0] &      ld_bypass_e;
assign lmc_thrd_byp_sel_e[2] = ldbyp_vld[2] & ~(|ldbyp_vld[1:0]) & ld_bypass_e;
assign lmc_thrd_byp_sel_e[3] = ldbyp_vld[3] & ~(|ldbyp_vld[2:0]) & ld_bypass_e;
assign lmc_thrd_byp_sel_e[4] = ldbyp_vld[4] & ~(|ldbyp_vld[3:0]) & ld_bypass_e;
assign lmc_thrd_byp_sel_e[5] = ldbyp_vld[5] & ~(|ldbyp_vld[4:0]) & ld_bypass_e;
assign lmc_thrd_byp_sel_e[6] = ldbyp_vld[6] & ~(|ldbyp_vld[5:0]) & ld_bypass_e;
assign lmc_thrd_byp_sel_e[7] = ldbyp_vld[7] & ~(|ldbyp_vld[6:0]) & ld_bypass_e;

assign byp_vld_e = |(lmc_thrd_byp_sel_e[7:0]);

assign ldbyp_rst[7:0] = lmc_thrd_byp_sel_e[7:0];

// Combine true bypass and a casa issue
assign thrd_byp_sel_e[7:0] = lmc_thrd_byp_sel_e[7:0] | st_atom_p4_dec[7:0];

lsu_lmc_ctlmsff_ctl_macro__width_9 dff_thrd_byp_sel_m  (
	.scan_in(dff_thrd_byp_sel_m_scanin),
	.scan_out(dff_thrd_byp_sel_m_scanout),
	.din	({    byp_vld_e,thrd_byp_sel_e[7:0]}),
	.dout	({lmc_byp_vld_m,thrd_byp_sel_m[7:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign lmc_thrd_byp_sel_m[7:0] = thrd_byp_sel_m[7:0];

assign lmc_asi_bypass_m = |(thrd_byp_sel_m[7:0] & lmd_asi_ld[7:0]);

assign lmc_byp_tid_m[2] = thrd_byp_sel_m[7] | thrd_byp_sel_m[6] | thrd_byp_sel_m[5] | thrd_byp_sel_m[4];
assign lmc_byp_tid_m[1] = thrd_byp_sel_m[7] | thrd_byp_sel_m[6] | thrd_byp_sel_m[3] | thrd_byp_sel_m[2];
assign lmc_byp_tid_m[0] = thrd_byp_sel_m[7] | thrd_byp_sel_m[5] | thrd_byp_sel_m[3] | thrd_byp_sel_m[1];


////////////////////////////////////////////////////////////////////////////////
// Block load control
// Each incoming block (64B) load instruction must cause four requests to the
// L2 which return 16B each.
////////////////////////////////////////////////////////////////////////////////

assign bld_inst_w[7:0] = {8{blk_inst_w & ld_inst_unflushed_w}} & thread_w[7:0];

assign bld_pending[7:0] = bld_inst_w[7:0] | bld_pend_hold[7:0];

assign bld_pending_in[7:0] = bld_pending[7:0] & ~bld_reset[7:0];

lsu_lmc_ctlmsff_ctl_macro__width_8 dff_bld_pending  (
	.scan_in(dff_bld_pending_scanin),
	.scan_out(dff_bld_pending_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_pending_in[7:0]),
	.dout	(bld_pend_hold[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign bld_addr54_p3[1:0] = {2{ld_pcx_rq_sel[0]}} & bld_cnt0[1:0] |
                            {2{ld_pcx_rq_sel[1]}} & bld_cnt1[1:0] |
                            {2{ld_pcx_rq_sel[2]}} & bld_cnt2[1:0] |
                            {2{ld_pcx_rq_sel[3]}} & bld_cnt3[1:0] |
                            {2{ld_pcx_rq_sel[4]}} & bld_cnt4[1:0] |
                            {2{ld_pcx_rq_sel[5]}} & bld_cnt5[1:0] |
                            {2{ld_pcx_rq_sel[6]}} & bld_cnt6[1:0] |
                            {2{ld_pcx_rq_sel[7]}} & bld_cnt7[1:0] ;

assign bld_req_p3 = |(ld_pcx_rq_sel[7:0] & bld_pending[7:0]);

lsu_lmc_ctlmsff_ctl_macro__width_3 dff_bld_addr  (
	.scan_in(dff_bld_addr_scanin),
	.scan_out(dff_bld_addr_scanout),
	.l1clk	(l1clk_pm1),
	.din	({bld_addr54_p3[1:0], bld_req_p3}),
	.dout	({lmc_bld_addr54[1:0],lmc_bld_req}),
  .siclk(siclk),
  .soclk(soclk)
);
assign lmc_bld_req_ = ~lmc_bld_req;

// Thread 0

// Counter is incremented when the preceeding request was accepted.
assign bld_cnt0_in[1:0] = bld_cnt0[1:0] + {1'b0,inc_bld0_cnt};
assign inc_bld0_cnt = ld_pcx_rq_sel[0] & ~perr_inv[0] & bld_pending[0];

// Reset the bld pending state when the final request is accepted.
assign bld_reset[0] = ld_pcx_rq_sel[0] & (&(bld_cnt0[1:0]));

// Requests 1-3 must prevent the ld_pcx_vld state from being reset so that
// following requests still go to the pcx.
assign bld_hold[0] = ~(&(bld_cnt0[1:0])) & bld_pending[0];

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt0  (
	.scan_in(dff_bld_cnt0_scanin),
	.scan_out(dff_bld_cnt0_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_cnt0_in[1:0]),
	.dout	(bld_cnt0[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Thread 1

// Counter is incremented when the preceeding request was accepted.
assign bld_cnt1_in[1:0] = bld_cnt1[1:0] + {1'b0,inc_bld1_cnt};
assign inc_bld1_cnt = ld_pcx_rq_sel[1] & ~perr_inv[1] & bld_pending[1];

// Reset the bld pending state when the final request is accepted.
assign bld_reset[1] = ld_pcx_rq_sel[1] & (&(bld_cnt1[1:0]));

// Requests 1-3 must prevent the ld_pcx_vld state from being reset so that
// following requests still go to the pcx.
assign bld_hold[1] = ~(&(bld_cnt1[1:0])) & bld_pending[1];

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt1  (
	.scan_in(dff_bld_cnt1_scanin),
	.scan_out(dff_bld_cnt1_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_cnt1_in[1:0]),
	.dout	(bld_cnt1[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Thread 2

// Counter is incremented when the preceeding request was accepted.
assign bld_cnt2_in[1:0] = bld_cnt2[1:0] + {1'b0,inc_bld2_cnt};
assign inc_bld2_cnt = ld_pcx_rq_sel[2] & ~perr_inv[2] & bld_pending[2];

// Reset the bld pending state when the final request is accepted.
assign bld_reset[2] = ld_pcx_rq_sel[2] & (&(bld_cnt2[1:0]));

// Requests 1-3 must prevent the ld_pcx_vld state from being reset so that
// following requests still go to the pcx.
assign bld_hold[2] = ~(&(bld_cnt2[1:0])) & bld_pending[2];

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt2  (
	.scan_in(dff_bld_cnt2_scanin),
	.scan_out(dff_bld_cnt2_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_cnt2_in[1:0]),
	.dout	(bld_cnt2[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Thread 3

// Counter is incremented when the preceeding request was accepted.
assign bld_cnt3_in[1:0] = bld_cnt3[1:0] + {1'b0,inc_bld3_cnt};
assign inc_bld3_cnt = ld_pcx_rq_sel[3] & ~perr_inv[3] & bld_pending[3];

// Reset the bld pending state when the final request is accepted.
assign bld_reset[3] = ld_pcx_rq_sel[3] & (&(bld_cnt3[1:0]));

// Requests 1-3 must prevent the ld_pcx_vld state from being reset so that
// following requests still go to the pcx.
assign bld_hold[3] = ~(&(bld_cnt3[1:0])) & bld_pending[3];

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt3  (
	.scan_in(dff_bld_cnt3_scanin),
	.scan_out(dff_bld_cnt3_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_cnt3_in[1:0]),
	.dout	(bld_cnt3[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Thread 4

// Counter is incremented when the preceeding request was accepted.
assign bld_cnt4_in[1:0] = bld_cnt4[1:0] + {1'b0,inc_bld4_cnt};
assign inc_bld4_cnt = ld_pcx_rq_sel[4] & ~perr_inv[4] & bld_pending[4];

// Reset the bld pending state when the final request is accepted.
assign bld_reset[4] = ld_pcx_rq_sel[4] & (&(bld_cnt4[1:0]));

// Requests 1-3 must prevent the ld_pcx_vld state from being reset so that
// following requests still go to the pcx.
assign bld_hold[4] = ~(&(bld_cnt4[1:0])) & bld_pending[4];

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt4  (
	.scan_in(dff_bld_cnt4_scanin),
	.scan_out(dff_bld_cnt4_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_cnt4_in[1:0]),
	.dout	(bld_cnt4[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Thread 5

// Counter is incremented when the preceeding request was accepted.
assign bld_cnt5_in[1:0] = bld_cnt5[1:0] + {1'b0,inc_bld5_cnt};
assign inc_bld5_cnt = ld_pcx_rq_sel[5] & ~perr_inv[5] & bld_pending[5];

// Reset the bld pending state when the final request is accepted.
assign bld_reset[5] = ld_pcx_rq_sel[5] & (&(bld_cnt5[1:0]));

// Requests 1-3 must prevent the ld_pcx_vld state from being reset so that
// following requests still go to the pcx.
assign bld_hold[5] = ~(&(bld_cnt5[1:0])) & bld_pending[5];

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt5  (
	.scan_in(dff_bld_cnt5_scanin),
	.scan_out(dff_bld_cnt5_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_cnt5_in[1:0]),
	.dout	(bld_cnt5[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Thread 6

// Counter is incremented when the preceeding request was accepted.
assign bld_cnt6_in[1:0] = bld_cnt6[1:0] + {1'b0,inc_bld6_cnt};
assign inc_bld6_cnt = ld_pcx_rq_sel[6] & ~perr_inv[6] & bld_pending[6];

// Reset the bld pending state when the final request is accepted.
assign bld_reset[6] = ld_pcx_rq_sel[6] & (&(bld_cnt6[1:0]));

// Requests 1-3 must prevent the ld_pcx_vld state from being reset so that
// following requests still go to the pcx.
assign bld_hold[6] = ~(&(bld_cnt6[1:0])) & bld_pending[6];

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt6  (
	.scan_in(dff_bld_cnt6_scanin),
	.scan_out(dff_bld_cnt6_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_cnt6_in[1:0]),
	.dout	(bld_cnt6[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Thread 7

// Counter is incremented when the preceeding request was accepted.
assign bld_cnt7_in[1:0] = bld_cnt7[1:0] + {1'b0,inc_bld7_cnt};
assign inc_bld7_cnt = ld_pcx_rq_sel[7] & ~perr_inv[7] & bld_pending[7];

// Reset the bld pending state when the final request is accepted.
assign bld_reset[7] = ld_pcx_rq_sel[7] & (&(bld_cnt7[1:0]));

// Requests 1-3 must prevent the ld_pcx_vld state from being reset so that
// following requests still go to the pcx.
assign bld_hold[7] = ~(&(bld_cnt7[1:0])) & bld_pending[7];

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt7  (
	.scan_in(dff_bld_cnt7_scanin),
	.scan_out(dff_bld_cnt7_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bld_cnt7_in[1:0]),
	.dout	(bld_cnt7[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Increment Rd after a load returns (used for QUAD/LDD/BLD)
// This path is also used to update the entry during a set invalidate to
// clear the error code.

assign lmc_rd_update[7:0] = {8{cic_l2fill_vld_e}} & lmc_byp_sel_e[7:0];

assign bld_annul_rst[7:0] = {8{(&lmd_rd_e[2:1] & cic_l2fill_vld_e)}} & lmc_byp_sel_e[7:0];

assign bld_annul_in[7:0] = ~bld_annul_rst[7:0] & (bld_annul[7:0] | bld_inst_w[7:0]);

lsu_lmc_ctlmsff_ctl_macro__width_8 dff_bld_bypass  (
	.scan_in(dff_bld_bypass_scanin),
	.scan_out(dff_bld_bypass_scanout),
	.din	(bld_annul_in[7:0]),
	.dout	(bld_annul[7:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign block_load_annul = (cpq_mx_thread[0] & bld_annul[0]) |
                          (cpq_mx_thread[1] & bld_annul[1]) | 
                          (cpq_mx_thread[2] & bld_annul[2]) | 
                          (cpq_mx_thread[3] & bld_annul[3]) | 
                          (cpq_mx_thread[4] & bld_annul[4]) | 
                          (cpq_mx_thread[5] & bld_annul[5]) | 
                          (cpq_mx_thread[6] & bld_annul[6]) | 
                          (cpq_mx_thread[7] & bld_annul[7]) ;

assign lmc_bld_annul = block_load_annul;

// Must track the l2miss behavior for block loads to properly trap &
// write frf on perfmon events.  Block loads will act based on the first
// helper.  If it misses, the entire instruction is considered a miss.

assign bld_miss_set[7:0] = bld_annul[7:0] & cpq_mx_thread[7:0] & {8{lmd_rd_e[2:1] == 2'b00}} & {8{cid_l2miss}};

assign bld_miss_in[7:0] = (bld_miss_set[7:0] | bld_miss[7:0]) &
                          ~({8{report_and_clear_error}} & cpq_mx_thread[7:0]);

assign bld_miss[7:0] = bld_miss_set[7:0] | bld_miss_out[7:0];

assign bld_pass7 = |(bld_annul_rst[7:0]) & ~report_and_clear_error;

lsu_lmc_ctlmsff_ctl_macro__width_9 dff_bld_miss  (
	.scan_in(dff_bld_miss_scanin),
	.scan_out(dff_bld_miss_scanout),
	.din	({bld_miss_in[7:0], bld_pass7}),
	.dout	({bld_miss_out[7:0],bld_pass7_done}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign lmc_bld_last_e = bld_pass7_done & report_and_clear_error;

assign lmc_bld_miss_e = (cpq_mx_thread[0] & bld_miss[0]) |
                        (cpq_mx_thread[1] & bld_miss[1]) | 
                        (cpq_mx_thread[2] & bld_miss[2]) | 
                        (cpq_mx_thread[3] & bld_miss[3]) | 
                        (cpq_mx_thread[4] & bld_miss[4]) | 
                        (cpq_mx_thread[5] & bld_miss[5]) | 
                        (cpq_mx_thread[6] & bld_miss[6]) | 
                        (cpq_mx_thread[7] & bld_miss[7]) ;

////////////////////////////////////////////////////////////////////////////////
// Tracking issued prefetches
////////////////////////////////////////////////////////////////////////////////

assign pref_issued[7:0] = (ld_all_sel_p4[7:0] & {8{ld_pcx_sel_p4 & lmd_pcx_pref & ~(early_ld_b_sel_p4 & flush_w)}}) |
                          (thread_w[7:0] & {8{pref_inst_w & excep_only_flush_w}}) ;

lsu_lmc_ctlmsff_ctl_macro__width_8 dff_pref_issued  (
	.scan_in(dff_pref_issued_scanin),
	.scan_out(dff_pref_issued_scanout),
	.din	(pref_issued[7:0]),
	.dout	(lmc_pref_issued[7:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Figure size mask for loads
// CAS(X)A uses the store format (00001111, 11110000, or 11111111)
// Loads use 00=byte, 01=hw, 10=wd, 11=dw, 100=quad; 5 MSB's are zero
////////////////////////////////////////////////////////////////////////////////

assign lmc_ld_sz[4] = casa_ld_to_pcx & (~lmd_addrb2 | lmd_sz_b0);
assign lmc_ld_sz[3] = casa_ld_to_pcx & (lmd_addrb2 | lmd_sz_b0);
assign lmc_ld_sz[2] = lmc_ld_sz[3] | (lmd_ldbl & lmd_sz_b0);
assign lmc_ld_sz[1] = lmc_ld_sz[3] | (~casa_ld_to_pcx & lmd_sz_b1 & ~lmd_sz_b0) | (~lmd_ldbl & lmd_sz_b1 & lmd_sz_b0);
assign lmc_ld_sz[0] = (casa_ld_to_pcx & lmd_addrb2) | (lmd_ldbl ^ lmd_sz_b0);

////////////////////////////////////////////////////////////////////////////////
// Select hi or low 64b for load return
// For LDD (sz=10), addr[3] determines
// For QUAD (sz=11), first pass is hi, second is low
////////////////////////////////////////////////////////////////////////////////

assign lmc_byp_data_hi = cic_cpq_ld_rdy & ~lmd_fill_addr_b3_e & ~(cic_oddrd_e & lmd_fill_sz_b0_e);

////////////////////////////////////////////////////////////////////////////////
// Clock enable for the bypass/fill data register

assign lmc_byp_data_enable = cic_l2fill_vld_e | byp_vld_e | cic_ext_interrupt;

////////////////////////////////////////////////////////////////////////////////
// Parity errors require an inval request to be sent to L2.
////////////////////////////////////////////////////////////////////////////////

assign perr_set[7:0] = {8{perror_w & ~(ld_raw_bypass_w | flush_w)}} & thread_w[7:0];

assign perr_inv_in[7:0] = perr_inv[7:0] & ~ld_pcx_rq_sel[7:0];

lsu_lmc_ctlmsff_ctl_macro__width_9 dff_perr  (
	.scan_in(dff_perr_scanin),
	.scan_out(dff_perr_scanout),
	.l1clk	(l1clk_pm1),
	.din	({perr_inv_in[7:0], ld_inv_p3}),
	.dout	({perr_inv_out[7:0],ld_inv_p4}),
  .siclk(siclk),
  .soclk(soclk)
);

assign perr_inv[7:0] = perr_inv_out[7:0] | perr_set[7:0];

// INV bit in pcx is asserted for line invalidation requests and for CAS2 packets
// if the store buffer had a UE
assign ld_inv_p3 = |(ld_pcx_rq_sel[7:0] & perr_inv[7:0]) | (sbc_force_inv & casa_bypass_e);

// INV bit is also asserted for prefetch ICE
assign lmc_ld_inv_p4 = ld_inv_p4 | (lmd_pcx_pref & lmd_ldbl);

// Error is reported when the inval_all packet comes back
// encoded error type: 00=valid, 01=tag, 10=mhit, 11=data

assign lsu_dcvp_err_e2 = cic_set_inval & (~lmd_dc_err_e[1] & ~lmd_dc_err_e[0]);
assign lsu_dctp_err_e2 = cic_set_inval & (~lmd_dc_err_e[1] &  lmd_dc_err_e[0]);
assign lsu_dcmh_err_e2 = cic_set_inval & ( lmd_dc_err_e[1] & ~lmd_dc_err_e[0]);
assign lsu_dcdp_err_e2 = cic_set_inval & ( lmd_dc_err_e[1] &  lmd_dc_err_e[0]);

lsu_lmc_ctlmsff_ctl_macro__width_4 dff_dcerr  (
	.scan_in(dff_dcerr_scanin),
	.scan_out(dff_dcerr_scanout),
	.din	({lsu_dcvp_err_e2,lsu_dctp_err_e2,lsu_dcmh_err_e2,lsu_dcdp_err_e2}),
	.dout	({lsu_dcvp_err_g ,lsu_dctp_err_g ,lsu_dcmh_err_g ,lsu_dcdp_err_g }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_dcerr_tid_g[2:0] = lmc_cpq_tid_m[2:0];

// Check that errors are never signaled during normal testing


////////////////////////////////////////////////////////////////////////////////
// L2 errors
// Multi-cycle loads (LDD,BLD) must wait until the final update to report the
// error.  Block loads will stop updating registers once an unc. error is detected.
// If multiple errors of different types are detected on the block load helpers,
// the highest priority error will be reported.  (UE > ND > CE)
////////////////////////////////////////////////////////////////////////////////

assign l2_err[1:0] = ({2{cpq_mx_thread[0]}} & l2_err0[1:0]) |
                     ({2{cpq_mx_thread[1]}} & l2_err1[1:0]) | 
                     ({2{cpq_mx_thread[2]}} & l2_err2[1:0]) | 
                     ({2{cpq_mx_thread[3]}} & l2_err3[1:0]) | 
                     ({2{cpq_mx_thread[4]}} & l2_err4[1:0]) | 
                     ({2{cpq_mx_thread[5]}} & l2_err5[1:0]) | 
                     ({2{cpq_mx_thread[6]}} & l2_err6[1:0]) | 
                     ({2{cpq_mx_thread[7]}} & l2_err7[1:0]) ;

assign l2_err_qual[1] = cic_cpq_ld_rdy & ceter_pscce_cpq &
                        ((cid_err[1] & ~cid_err[0] & cid_dcsoc_err_e  & cerer_socu) |
                         (cid_err[1] & ~cid_err[0] & ~cid_dcsoc_err_e & cerer_dcl2u) |
                         (cid_err[1] &  cid_err[0] & cerer_dcl2nd));

assign l2_err_qual[0] = cic_cpq_ld_rdy &
                        ((~cid_err[1] & cid_err[0] & cid_dcsoc_err_e  & cerer_socc) |
                         (~cid_err[1] & cid_err[0] & ~cid_dcsoc_err_e & cerer_dcl2c) |
                         ( cid_err[1] & cid_err[0] & ceter_pscce_cpq & cerer_dcl2nd));

assign l2_err_new[1] = l2_err[1] | l2_err_qual[1];
assign l2_err_new[0] = (l2_err[0] & ~l2_err_qual[1]) | 
                       (l2_err_qual[1] & l2_err_qual[0]) |
                       (~l2_err[1] & l2_err_qual[0]) |
                       (l2_err[1] & l2_err[0]);

// Suppress register update on any uncorrectable error, including accumulated errors.
assign lmc_l2_err_noup = l2_err_new[1];

// For uncorrectable errors on fill data, inject a parity error into the D$
// Don't need to worry about the accumulated error since LDD & BLD don't fill
// Inject errors even if ceter.pscce is off (for timing reasons).
assign lmc_l2_uerr = (cerer_dcl2u & cid_err[1] & ~cid_err[0]) | (cerer_dcl2nd & cid_err[1] & cid_err[0]);

assign l2_err0_in[1:0] = cpq_mx_thread[0] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err0[1:0];
assign l2_err1_in[1:0] = cpq_mx_thread[1] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err1[1:0];
assign l2_err2_in[1:0] = cpq_mx_thread[2] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err2[1:0];
assign l2_err3_in[1:0] = cpq_mx_thread[3] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err3[1:0];
assign l2_err4_in[1:0] = cpq_mx_thread[4] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err4[1:0];
assign l2_err5_in[1:0] = cpq_mx_thread[5] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err5[1:0];
assign l2_err6_in[1:0] = cpq_mx_thread[6] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err6[1:0];
assign l2_err7_in[1:0] = cpq_mx_thread[7] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err7[1:0];

lsu_lmc_ctlmsff_ctl_macro__width_16 dff_l2errcode  (
	.scan_in(dff_l2errcode_scanin),
	.scan_out(dff_l2errcode_scanout),
	.din	({l2_err0_in[1:0],l2_err1_in[1:0],l2_err2_in[1:0],l2_err3_in[1:0],
		  l2_err4_in[1:0],l2_err5_in[1:0],l2_err6_in[1:0],l2_err7_in[1:0]}),
	.dout	({l2_err0[1:0],   l2_err1[1:0],   l2_err2[1:0],   l2_err3[1:0],
		  l2_err4[1:0],   l2_err5[1:0],   l2_err6[1:0],   l2_err7[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign report_and_clear_error = cic_rtn_cmplt & ~block_load_annul;

assign dcl2c_err  = report_and_clear_error & (~l2_err_new[1] &  l2_err_new[0]);
assign dcl2u_err  = report_and_clear_error & ( l2_err_new[1] & ~l2_err_new[0]);
assign dcl2nd_err = report_and_clear_error & ( l2_err_new[1] &  l2_err_new[0]);

lsu_lmc_ctlmsff_ctl_macro__width_3 dff_l2err  (
	.scan_in(dff_l2err_scanin),
	.scan_out(dff_l2err_scanout),
	.din	({dcl2c_err,      dcl2u_err,      dcl2nd_err}),
	.dout	({lsu_dcl2c_err_g,lsu_dcl2u_err_g,lsu_dcl2nd_err_g}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// STB RAW errors
////////////////////////////////////////////////////////////////////////////////
assign sbdlc_err = ld_raw_bypass_w3 & stb_cecc_err & ~stb_uecc_err & ceter_pscce_w3 & cerer_sbdlc;
assign sbdlu_err = ld_raw_bypass_w3 & stb_uecc_err & ceter_pscce_w3 & cerer_sbdlu;
assign stberr_tid[2:0] = ld_raw_bypass_w3 ? tid_w3[2:0] : sbc_st_sel_tid_p4[2:0];

lsu_lmc_ctlmsff_ctl_macro__width_5 dff_stberr  (
	.scan_in(dff_stberr_scanin),
	.scan_out(dff_stberr_scanout),
	.din	({sbdlc_err,      sbdlu_err,      stberr_tid[2:0]}),
	.dout	({lsu_sbdlc_err_g,lsu_sbdlu_err_g,lsu_stberr_tid_g[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// xinval control
// Because the IFU does not queue incoming packets, there is the possibility
// that they process an ifill which requires D$ invalidation much earlier than
// the LSU.  This causes a problem because the fill will occur and the thread
// could miss again before the D$ inval occurs.  I will signal when an inval
// is pending.  During this time, the I$ will not service a miss from that thread.
////////////////////////////////////////////////////////////////////////////////

assign xinval_pend_in[0] = cic_xinval[0] | (xinval_pend[0] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b000));
assign xinval_pend_in[1] = cic_xinval[1] | (xinval_pend[1] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b001));
assign xinval_pend_in[2] = cic_xinval[2] | (xinval_pend[2] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b010));
assign xinval_pend_in[3] = cic_xinval[3] | (xinval_pend[3] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b011));
assign xinval_pend_in[4] = cic_xinval[4] | (xinval_pend[4] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b100));
assign xinval_pend_in[5] = cic_xinval[5] | (xinval_pend[5] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b101));
assign xinval_pend_in[6] = cic_xinval[6] | (xinval_pend[6] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b110));
assign xinval_pend_in[7] = cic_xinval[7] | (xinval_pend[7] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b111));

lsu_lmc_ctlmsff_ctl_macro__width_9 dff_xinval_pend  (
	.scan_in(dff_xinval_pend_scanin),
	.scan_out(dff_xinval_pend_scanout),
	.din	({xinval_pend_in[7:0],cic_xinval_e}),
	.dout	({xinval_pend[7:0],   cpq_xinval_m}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_ifu_no_miss[7:0] = xinval_pend[7:0];

////////////////////////////////////////////////////////////////////////////////
// Power management.
// lmc has 2 clock domains.
// 1. Free running (l1clk)
// 2. Any load request pending (l1clk_pm1)
// A third possible domain which represends any load miss outstanding could
// gate ~50 flops but would require adding 8 flops and logic.  Not worth it.
////////////////////////////////////////////////////////////////////////////////

assign rqpend_clken = ~lsu_lsu_pmen | ld_inst_vld_b | ld_inst_nopref_w | pref_inst_w |
                      (|(ld_pcx_vld[7:0])) | (|(ld_asi_vld[7:0])) | (|(ld_all_sel_p4[7:0]));


////////////////////////////////////////////////////////////////////////////////
// BIST/DIAG
////////////////////////////////////////////////////////////////////////////////

lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bist_diag  (
	.scan_in(dff_bist_diag_scanin),
	.scan_out(dff_bist_diag_scanout),
	.din	({mbi_run,    bist_or_diag_d}),
	.dout	({lmc_mbi_run,lmc_bist_or_diag_e}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign bist_or_diag_d = lmc_mbi_run | dcc_cache_diag_wr_b;

lsu_lmc_ctlmsff_ctl_macro__scanreverse_1__width_6 dff_spares   (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.din	({ld_inst_vld_b,5'b0       }),
	.dout	({ld_inst_vld_w,unused[4:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//spare_ctl_macro spares (num=6) (
//	.scan_in(spares_scanin),
//	.scan_out(spares_scanout),
//	.l1clk	(l1clk)
//);

supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_ceter_scanin          = scan_in                  ;
assign dff_cerer_scanin          = dff_ceter_scanout        ;
assign dff_thread_w_scanin       = dff_cerer_scanout        ;
assign dff_flush_b_scanin        = dff_thread_w_scanout     ;
assign dff_flush_w_scanin        = dff_flush_b_scanout      ;
assign dff_inst_b_scanin         = dff_flush_w_scanout      ;
assign dff_inst_w_scanin         = dff_inst_b_scanout       ;
assign dff_l2fill_scanin         = dff_inst_w_scanout       ;
assign dff_unfilled_scanin       = dff_l2fill_scanout       ;
assign dff_stb_raw_scanin        = dff_unfilled_scanout     ;
assign dff_rawp_disable_scanin   = dff_stb_raw_scanout      ;
assign dff_ldd_vld_scanin        = dff_rawp_disable_scanout ;
assign dff_ld_lmq_en_b_scanin    = dff_ldd_vld_scanout      ;
assign dff_ld_pcx_vld_scanin     = dff_ld_lmq_en_b_scanout  ;
assign dff_ld_asi_vld_scanin     = dff_ld_pcx_vld_scanout   ;
assign lru8_scanin               = dff_ld_asi_vld_scanout   ;
assign dff_ld_sel_scanin         = lru8_scanout             ;
assign dff_ldd_out_scanin        = dff_ld_sel_scanout       ;
assign dff_st_atom_p4_scanin     = dff_ldd_out_scanout      ;
assign dff_st_atom_p5_scanin     = dff_st_atom_p4_scanout   ;
assign dff_asi_indet_scanin      = dff_st_atom_p5_scanout   ;
assign dff_cpq_tid_scanin        = dff_asi_indet_scanout    ;
assign dff_ld_raw_w_scanin       = dff_cpq_tid_scanout      ;
assign dff_ld_raw_w2_scanin      = dff_ld_raw_w_scanout     ;
assign dff_ld_raw_w3_scanin      = dff_ld_raw_w2_scanout    ;
assign dff_ldbyp_vld_scanin      = dff_ld_raw_w3_scanout    ;
assign dff_ld_inst_e_scanin      = dff_ldbyp_vld_scanout    ;
assign dff_byp_cnt_scanin        = dff_ld_inst_e_scanout    ;
assign dff_thrd_byp_sel_m_scanin = dff_byp_cnt_scanout      ;
assign dff_bld_pending_scanin    = dff_thrd_byp_sel_m_scanout;
assign dff_bld_addr_scanin       = dff_bld_pending_scanout  ;
assign dff_bld_cnt0_scanin       = dff_bld_addr_scanout     ;
assign dff_bld_cnt1_scanin       = dff_bld_cnt0_scanout     ;
assign dff_bld_cnt2_scanin       = dff_bld_cnt1_scanout     ;
assign dff_bld_cnt3_scanin       = dff_bld_cnt2_scanout     ;
assign dff_bld_cnt4_scanin       = dff_bld_cnt3_scanout     ;
assign dff_bld_cnt5_scanin       = dff_bld_cnt4_scanout     ;
assign dff_bld_cnt6_scanin       = dff_bld_cnt5_scanout     ;
assign dff_bld_cnt7_scanin       = dff_bld_cnt6_scanout     ;
assign dff_bld_bypass_scanin     = dff_bld_cnt7_scanout     ;
assign dff_bld_miss_scanin       = dff_bld_bypass_scanout   ;
assign dff_pref_issued_scanin    = dff_bld_miss_scanout     ;
assign dff_perr_scanin           = dff_pref_issued_scanout  ;
assign dff_dcerr_scanin          = dff_perr_scanout         ;
assign dff_l2errcode_scanin      = dff_dcerr_scanout        ;
assign dff_l2err_scanin          = dff_l2errcode_scanout    ;
assign dff_stberr_scanin         = dff_l2err_scanout        ;
assign dff_xinval_pend_scanin    = dff_stberr_scanout       ;
assign dff_bist_diag_scanin      = dff_xinval_pend_scanout  ;
assign spares_scanin             = dff_bist_diag_scanout    ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctll1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmc_ctlmsff_ctl_macro__scanreverse_1__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [0:4] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({so[0:4],scan_in}),
.so({scan_out,so[0:4]}),
.q(dout[5:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_lmd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_lmd_dp (
  lmc_lmq_enable_b, 
  lmc_lmq_bypass_en, 
  lmc_pcx_sel_p4, 
  lmc_byp_sel_e, 
  lmc_thrd_byp_sel_m, 
  lmc_lmq0_byp_sel, 
  lmc_lmq1_byp_sel, 
  lmc_lmq2_byp_sel, 
  lmc_lmq3_byp_sel, 
  lmc_lmq4_byp_sel, 
  lmc_lmq5_byp_sel, 
  lmc_lmq6_byp_sel, 
  lmc_lmq7_byp_sel, 
  lmc_bld_addr54, 
  lmc_bld_req, 
  lmc_bld_req_, 
  lmc_lmd_ncache_b, 
  lmc_rd_update, 
  lmc_ld_unfilled, 
  lmc_bist_or_diag_e, 
  lmc_byp_data_hi, 
  lmc_byp_data_enable, 
  dcc_ld_miss_ctl, 
  dcc_perr_enc_b, 
  dcc_l2fill_vld_m, 
  dcc_cache_diag_wr_b, 
  stb_ram_data, 
  ard_pid_data, 
  stb_st_addr_b, 
  sbd_st_addr_b, 
  sbd_st_data_b, 
  stb_ldxa_asi_data_w, 
  lsu_va_b, 
  lsu_va_w, 
  cid_fill_data_e, 
  cid_st_data_sel, 
  cid_tid, 
  lsu_cpx_cpkt, 
  dcs_ldxa_asi_data_w, 
  cic_diag_data_sel_e, 
  mbi_wdata, 
  lmc_mbi_run, 
  lmd_addrb2, 
  lmd_asi_ld, 
  lmd_asi_indet, 
  lmd_sec_cmp_b, 
  lmd_ld_addr_m, 
  lmd_fill_sz_b0_e, 
  lmd_bendian_m, 
  lmd_sxt_fsr_m, 
  lmd_fill_way_e, 
  lmd_fill_way_m, 
  lmd_sz_m, 
  lmd_fpld_m, 
  lmd_rd_e, 
  lmd_rd_m, 
  lmd_fpodd32b_m, 
  lmd_fp32b_m, 
  lmd_bypass_data_m, 
  lmd_fill_data_e, 
  lmd_fill_or_byp_data_m, 
  lmd_misc_msb_m, 
  lmd_fill_addr_e, 
  lmd_fill_addr_m, 
  lmd_wrtag_parity_e, 
  lmd_pcx_rqtyp, 
  lmd_pcx_nc, 
  lmd_pcx_pref, 
  lmd_pcx_rway, 
  lmd_pcx_addr, 
  lmd_asi_rngf, 
  lmd_asi_type, 
  lmd_asi_asi, 
  lmd_sz_b1, 
  lmd_sz_b0, 
  lmd_ldbl, 
  lmd_dc_err_e, 
  lsu_ifu_ld_index, 
  lsu_ext_int_type, 
  lsu_ext_int_vec, 
  lsu_ext_int_tid, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [39:0] ld_addr_b;
wire [12:11] lsu_va_b_unused;
wire wrtag_parity_b;
wire [63:0] ld_miss_pkt;
wire ctl_unused;
wire [63:0] lmq7_pkt;
wire [63:0] lmq6_pkt;
wire [63:0] lmq5_pkt;
wire [63:0] lmq4_pkt;
wire [63:0] lmq3_pkt;
wire [63:0] lmq2_pkt;
wire [63:0] lmq1_pkt;
wire [63:0] lmq0_pkt;
wire [2:0] rd7_plus1;
wire [2:0] rd6_plus1;
wire [2:0] rd5_plus1;
wire [2:0] rd4_plus1;
wire [2:0] rd3_plus1;
wire [2:0] rd2_plus1;
wire [2:0] rd1_plus1;
wire [2:0] rd0_plus1;
wire [63:0] rd_update_pkt0;
wire [63:0] rd_update_pkt1;
wire [63:0] rd_update_pkt2;
wire [63:0] rd_update_pkt3;
wire [63:0] rd_update_pkt4;
wire [63:0] rd_update_pkt5;
wire [63:0] rd_update_pkt6;
wire [63:0] rd_update_pkt7;
wire dff_lmq0_scanin;
wire dff_lmq0_scanout;
wire dff_lmq1_scanin;
wire dff_lmq1_scanout;
wire dff_lmq2_scanin;
wire dff_lmq2_scanout;
wire dff_lmq3_scanin;
wire dff_lmq3_scanout;
wire dff_lmq4_scanin;
wire dff_lmq4_scanout;
wire dff_lmq5_scanin;
wire dff_lmq5_scanout;
wire dff_lmq6_scanin;
wire dff_lmq6_scanout;
wire dff_lmq7_scanin;
wire dff_lmq7_scanout;
wire [10:5] ifu_ld_index;
wire [39:4] cmp_addr;
wire [7:0] sec_cmp_lo;
wire [7:0] sec_cmp_hi;
wire pcx_pkt_b55;
wire [49:0] pcx_pkt;
wire [5:4] pcx_addr;
wire [49:0] lmd_pcx_pkt;
wire lmd_fpodd32b_e;
wire lmd_fp32b_e;
wire lmd_fpld_e;
wire lmd_sxt_fsr_e;
wire lmd_bendian_e;
wire [4:0] rd_e;
wire [1:0] lmd_sz_e;
wire [2:0] ld_addr_e;
wire [44:0] lmq0_or_diag;
wire [44:0] lmd_muxdata_e;
wire [30:2] diag_data_w_buf;
wire [39:11] diag_addr_e;
wire wrtag_parity_w;
wire dff_lmq_data_m_scanin;
wire dff_lmq_data_m_scanout;
wire [63:0] st_data_b;
wire [63:0] stb_ram_data_buf;
wire [63:0] stb_ldxa_asi_data_w_buf;
wire [63:0] ard_pid_data_buf;
wire [63:0] dcs_ldxa_asi_data_w_buf;
wire dff_ldbyp0_scanin;
wire dff_ldbyp0_scanout;
wire [63:0] lmq0_bypass_data;
wire dff_ldbyp1_scanin;
wire dff_ldbyp1_scanout;
wire [63:0] lmq1_bypass_data;
wire dff_ldbyp2_scanin;
wire dff_ldbyp2_scanout;
wire [63:0] lmq2_bypass_data;
wire dff_ldbyp3_scanin;
wire dff_ldbyp3_scanout;
wire [63:0] lmq3_bypass_data;
wire dff_ldbyp4_scanin;
wire dff_ldbyp4_scanout;
wire [63:0] lmq4_bypass_data;
wire dff_ldbyp5_scanin;
wire dff_ldbyp5_scanout;
wire [63:0] lmq5_bypass_data;
wire dff_ldbyp6_scanin;
wire dff_ldbyp6_scanout;
wire [63:0] lmq6_bypass_data;
wire dff_ldbyp7_scanin;
wire dff_ldbyp7_scanout;
wire [63:0] lmq7_bypass_data;
wire [63:0] bypass_data_m;
wire dff_st_data_w_scanin;
wire dff_st_data_w_scanout;
wire [63:0] diag_data_w;
wire [127:0] fill_data_e;
wire byp_half_sel_scanin;
wire byp_half_sel_scanout;
wire [63:0] fill_data_m;


input	[7:0]	lmc_lmq_enable_b;	// Load enables for LMQ flops (threaded)
input	[7:0]	lmc_lmq_bypass_en;	// Load enables for LMQ bypass registers
input	[7:0]	lmc_pcx_sel_p4;		// Mux the selected thread 
input	[7:0]	lmc_byp_sel_e;		// Thread select for fill/bypass
input	[7:0]	lmc_thrd_byp_sel_m;	// Thread select for bypass register
input	[4:0]	lmc_lmq0_byp_sel;	// source selects for load bypass registers
input	[4:0]	lmc_lmq1_byp_sel;	// source selects for load bypass registers
input	[4:0]	lmc_lmq2_byp_sel;	// source selects for load bypass registers
input	[4:0]	lmc_lmq3_byp_sel;	// source selects for load bypass registers
input	[4:0]	lmc_lmq4_byp_sel;	// source selects for load bypass registers
input	[4:0]	lmc_lmq5_byp_sel;	// source selects for load bypass registers
input	[4:0]	lmc_lmq6_byp_sel;	// source selects for load bypass registers
input	[4:0]	lmc_lmq7_byp_sel;	// source selects for load bypass registers
input	[1:0]	lmc_bld_addr54;		// Block load address modifier
input		lmc_bld_req;		// Current request is for block load
input		lmc_bld_req_;
input		lmc_lmd_ncache_b;
input	[7:0]	lmc_rd_update;
input	[7:0]	lmc_ld_unfilled;
input		lmc_bist_or_diag_e;
input		lmc_byp_data_hi;
input		lmc_byp_data_enable;

input	[60:40]	dcc_ld_miss_ctl;	// Load miss packet info
input	[1:0]	dcc_perr_enc_b;		// D$ parity error encoding
input		dcc_l2fill_vld_m;
input		dcc_cache_diag_wr_b;

input	[63:0]	stb_ram_data;		// stb data for RAW bypass
input	[63:0]	ard_pid_data;		// asi load data
input	[39:13]	stb_st_addr_b;		// should be equal to tlb_pgnum for normal loads
input	[12:11]	sbd_st_addr_b;
input	[63:0]	sbd_st_data_b;		// for CAS
input	[63:0]	stb_ldxa_asi_data_w;
input	[12:0]	lsu_va_b;
input	[12:3]	lsu_va_w;

input	[127:0]	cid_fill_data_e;	// cpx fill data
input		cid_st_data_sel;
input	[2:0]	cid_tid;
input	[8:6]	lsu_cpx_cpkt;

input	[63:0]	dcs_ldxa_asi_data_w;

input		cic_diag_data_sel_e;

input	[7:0]	mbi_wdata;
input		lmc_mbi_run;

output		lmd_addrb2;
output	[7:0]	lmd_asi_ld;		// ASI type flag for each thread
output	[7:0]	lmd_asi_indet;		// ASI type flag for each thread
output	[7:0]	lmd_sec_cmp_b;		// Secondary load indicators

// Data for fills and bypass
output	[2:0]	lmd_ld_addr_m;
output		lmd_fill_sz_b0_e;
output		lmd_bendian_m;		// Endian bit for load misses
output		lmd_sxt_fsr_m;		// Sign extend / LDFSR for load misses
output	[1:0]	lmd_fill_way_e;		// Replacement way for fill data write
output	[1:0]	lmd_fill_way_m;		// Replacement way for fill data write
output	[1:0]	lmd_sz_m;		// Size bits from LMQ
output		lmd_fpld_m;		// Load was floating point
output	[2:1]	lmd_rd_e;		// Dest. register address
output	[4:0]	lmd_rd_m;		// Dest. register address
output		lmd_fpodd32b_m;
output		lmd_fp32b_m;
output	[63:0]	lmd_bypass_data_m;
output	[127:0]	lmd_fill_data_e;
output	[63:0]	lmd_fill_or_byp_data_m;
output	[7:0]	lmd_misc_msb_m;
output	[39:3]	lmd_fill_addr_e;
output	[10:4]	lmd_fill_addr_m;
output		lmd_wrtag_parity_e;

output	[2:0]	lmd_pcx_rqtyp;
output		lmd_pcx_nc;
output		lmd_pcx_pref;
output	[1:0]	lmd_pcx_rway;
output	[39:0]	lmd_pcx_addr;
output		lmd_asi_rngf;
output	[1:0]	lmd_asi_type;
output	[7:0]	lmd_asi_asi;
output		lmd_sz_b1;
output		lmd_sz_b0;
output		lmd_ldbl;
output	[1:0]	lmd_dc_err_e;

output	[10:5]	lsu_ifu_ld_index;
output	[1:0]	lsu_ext_int_type;
output	[5:0]	lsu_ext_int_vec;
output	[2:0]	lsu_ext_int_tid;

// Globals
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

// scan renames
assign stop = 1'b0;
// end scan

lsu_lmd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);

`define LMQ_TPAR        61
`define LMQ_ASI 	60
`define LMQ_FPODD32 	59
`define LMQ_FP32 	58
`define LMQ_FPLD 	57
`define LMQ_SIGNEXT 	56
`define LMQ_BIGEND 	55
`define LMQ_RD_HI       54
`define LMQ_RD_LO       50
`define LMQ_LDD         49
`define LMQ_SZ_HI       48
`define LMQ_SZ_LO       47
`define LMQ_RQ_HI       46
`define LMQ_RQ_LO       44
`define LMQ_NC  	43
`define LMQ_PREF 	42
`define LMQ_WY_HI       41
`define LMQ_WY_LO       40
`define LMQ_AD_HI       39
`define LMQ_AD_LO       0
`define LMQ_ASI_IND	56
`define LMQ_ASI_TYPE	48
`define LMQ_ASI_HI	47
`define LMQ_ASI_LO	40

////////////////////////////////////////////////////////////////////////////////
// Format of the load miss buffer
//
// MEM format
//
// 63:62 - parity error info
// 61    - wrtag_parity
// 60    - ASI			- (==0 for memory access)
// 59    - fpodd32		- 32 bit fp load to odd Rd
// 58    - fp32			- 32 bit fp load
// 57    - fp_ld		- load is floating point
// 56    - sign_ext/fsr		- data requires sign extension or is LDFSR
// 55    - bendian		- big endian access
// 54:50 - rd[4:0]		- destination register
// 49	 - ldst_dbl		- instruction is LDD (requires two returns)
// 48:47 - sz[1:0]		- size
// 46:44 - rqtyp[2:0]		- request type
// 43    - nc			- non-cacheable load
// 42    - prefetch		- prefetch instruction
// 41:40 - way[1:0]		- replacement way
// 39:13 - pgnum[39:13]		- translated addr.
// 12:0  - va[12:0]		-
//
// ASI format
//
// 63:62 - unused
// 61    - unused
// 60    - ASI			- (==1 for ASI access)
// 59:57 - unused
// 56    - indeterminate flag
// 55    - fast/local ring	- 1=fast
// 54:50 - rd[4:0]
// 49:48 - ASI type (00-ASI,01-ASR,10-PR,11-HPR)
// 47:40 - ASI
// 39:0  - address

lsu_lmd_dp_buff_macro__rep_1__stack_64c__width_40 ld_addr_buf   (
	.din	({stb_st_addr_b[39:13],sbd_st_addr_b[12:11],lsu_va_b[10:0]}),
	.dout	(ld_addr_b[39:0])
);

// Leave lsu_va_b[12:11] at this level because verfication bench needs it.
assign lsu_va_b_unused[12:11] = lsu_va_b[12:11];

////////////////////////////////////////////////////////////////////////////////
// LMQ flops.  One for each thread.
////////////////////////////////////////////////////////////////////////////////

// Miss packet construction

lsu_lmd_dp_buff_macro__dbuff_32x__rep_1__stack_24c__width_24 miss_pkt_buf    (
	.din	({dcc_perr_enc_b[1:0],wrtag_parity_b,dcc_ld_miss_ctl[60:44],lmc_lmd_ncache_b,dcc_ld_miss_ctl[42:40]}),
	.dout	(ld_miss_pkt[63:40])
);
assign ctl_unused=dcc_ld_miss_ctl[43];

assign ld_miss_pkt[39:0] = ld_addr_b[39:0];

lsu_lmd_dp_prty_macro__width_32 wrtag_prty  (
	.din	({ld_miss_pkt[39:32],3'b000,ld_miss_pkt[31:11]}),
	.dout	(wrtag_parity_b)
);

// Library incrementer is too big and is more than I need.  Build a simple one for each thread.

lsu_lmd_dp_inv_macro__width_8 rd_incr0  (
	.din	({lmq7_pkt[`LMQ_RD_LO],lmq6_pkt[`LMQ_RD_LO],lmq5_pkt[`LMQ_RD_LO],lmq4_pkt[`LMQ_RD_LO],
		  lmq3_pkt[`LMQ_RD_LO],lmq2_pkt[`LMQ_RD_LO],lmq1_pkt[`LMQ_RD_LO],lmq0_pkt[`LMQ_RD_LO]}),
	.dout	({rd7_plus1[0],rd6_plus1[0],rd5_plus1[0],rd4_plus1[0],rd3_plus1[0],rd2_plus1[0],rd1_plus1[0],rd0_plus1[0]})
);

lsu_lmd_dp_xor_macro__ports_2__width_8 rd_incr1   (
	.din0	({lmq7_pkt[`LMQ_RD_LO],lmq6_pkt[`LMQ_RD_LO],lmq5_pkt[`LMQ_RD_LO],lmq4_pkt[`LMQ_RD_LO],
		  lmq3_pkt[`LMQ_RD_LO],lmq2_pkt[`LMQ_RD_LO],lmq1_pkt[`LMQ_RD_LO],lmq0_pkt[`LMQ_RD_LO]}),
	.din1	({lmq7_pkt[`LMQ_RD_LO + 1],lmq6_pkt[`LMQ_RD_LO + 1],lmq5_pkt[`LMQ_RD_LO + 1],lmq4_pkt[`LMQ_RD_LO + 1],
		  lmq3_pkt[`LMQ_RD_LO + 1],lmq2_pkt[`LMQ_RD_LO + 1],lmq1_pkt[`LMQ_RD_LO + 1],lmq0_pkt[`LMQ_RD_LO + 1]}),
	.dout	({rd7_plus1[1],rd6_plus1[1],rd5_plus1[1],rd4_plus1[1],rd3_plus1[1],rd2_plus1[1],rd1_plus1[1],rd0_plus1[1]})
);


lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_0     (
	.din0	(lmq0_pkt[`LMQ_RD_LO]),
	.sel0	(lmq0_pkt[`LMQ_RD_LO + 1]),
	.din1	(lmq0_pkt[`LMQ_RD_LO + 2]),
	.sel1	(1'b1),
	.dout	(rd0_plus1[2])
);

lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_1     (
	.din0	(lmq1_pkt[`LMQ_RD_LO]),
	.sel0	(lmq1_pkt[`LMQ_RD_LO + 1]),
	.din1	(lmq1_pkt[`LMQ_RD_LO + 2]),
	.sel1	(1'b1),
	.dout	(rd1_plus1[2])
);

lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_2     (
	.din0	(lmq2_pkt[`LMQ_RD_LO]),
	.sel0	(lmq2_pkt[`LMQ_RD_LO + 1]),
	.din1	(lmq2_pkt[`LMQ_RD_LO + 2]),
	.sel1	(1'b1),
	.dout	(rd2_plus1[2])
);

lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_3     (
	.din0	(lmq3_pkt[`LMQ_RD_LO]),
	.sel0	(lmq3_pkt[`LMQ_RD_LO + 1]),
	.din1	(lmq3_pkt[`LMQ_RD_LO + 2]),
	.sel1	(1'b1),
	.dout	(rd3_plus1[2])
);

lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_4     (
	.din0	(lmq4_pkt[`LMQ_RD_LO]),
	.sel0	(lmq4_pkt[`LMQ_RD_LO + 1]),
	.din1	(lmq4_pkt[`LMQ_RD_LO + 2]),
	.sel1	(1'b1),
	.dout	(rd4_plus1[2])
);

lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_5     (
	.din0	(lmq5_pkt[`LMQ_RD_LO]),
	.sel0	(lmq5_pkt[`LMQ_RD_LO + 1]),
	.din1	(lmq5_pkt[`LMQ_RD_LO + 2]),
	.sel1	(1'b1),
	.dout	(rd5_plus1[2])
);

lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_6     (
	.din0	(lmq6_pkt[`LMQ_RD_LO]),
	.sel0	(lmq6_pkt[`LMQ_RD_LO + 1]),
	.din1	(lmq6_pkt[`LMQ_RD_LO + 2]),
	.sel1	(1'b1),
	.dout	(rd6_plus1[2])
);

lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_7     (
	.din0	(lmq7_pkt[`LMQ_RD_LO]),
	.sel0	(lmq7_pkt[`LMQ_RD_LO + 1]),
	.din1	(lmq7_pkt[`LMQ_RD_LO + 2]),
	.sel1	(1'b1),
	.dout	(rd7_plus1[2])
);


assign rd_update_pkt0[63:0] = {lmq0_pkt[63:53],rd0_plus1[2:0],lmq0_pkt[49:0]};
assign rd_update_pkt1[63:0] = {lmq1_pkt[63:53],rd1_plus1[2:0],lmq1_pkt[49:0]};
assign rd_update_pkt2[63:0] = {lmq2_pkt[63:53],rd2_plus1[2:0],lmq2_pkt[49:0]};
assign rd_update_pkt3[63:0] = {lmq3_pkt[63:53],rd3_plus1[2:0],lmq3_pkt[49:0]};
assign rd_update_pkt4[63:0] = {lmq4_pkt[63:53],rd4_plus1[2:0],lmq4_pkt[49:0]};
assign rd_update_pkt5[63:0] = {lmq5_pkt[63:53],rd5_plus1[2:0],lmq5_pkt[49:0]};
assign rd_update_pkt6[63:0] = {lmq6_pkt[63:53],rd6_plus1[2:0],lmq6_pkt[49:0]};
assign rd_update_pkt7[63:0] = {lmq7_pkt[63:53],rd7_plus1[2:0],lmq7_pkt[49:0]};

lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq0      (
	.scan_in(dff_lmq0_scanin),
	.scan_out(dff_lmq0_scanout),
	.din0	(rd_update_pkt0[63:0]),
	.din1   (ld_miss_pkt[63:0]),
	.sel0	(lmc_rd_update[0]),
	.dout	(lmq0_pkt[63:0]),
	.clk    (l2clk),
	.en	(lmc_lmq_enable_b[0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq1      (
	.scan_in(dff_lmq1_scanin),
	.scan_out(dff_lmq1_scanout),
	.din0	(rd_update_pkt1[63:0]),
	.din1   (ld_miss_pkt[63:0]),
	.sel0	(lmc_rd_update[1]),
	.dout	(lmq1_pkt[63:0]),
	.clk    (l2clk),
	.en	(lmc_lmq_enable_b[1]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq2      (
	.scan_in(dff_lmq2_scanin),
	.scan_out(dff_lmq2_scanout),
	.din0	(rd_update_pkt2[63:0]),
	.din1   (ld_miss_pkt[63:0]),
	.sel0	(lmc_rd_update[2]),
	.dout	(lmq2_pkt[63:0]),
	.clk    (l2clk),
	.en	(lmc_lmq_enable_b[2]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq3      (
	.scan_in(dff_lmq3_scanin),
	.scan_out(dff_lmq3_scanout),
	.din0	(rd_update_pkt3[63:0]),
	.din1   (ld_miss_pkt[63:0]),
	.sel0	(lmc_rd_update[3]),
	.dout	(lmq3_pkt[63:0]),
	.clk    (l2clk),
	.en	(lmc_lmq_enable_b[3]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq4      (
	.scan_in(dff_lmq4_scanin),
	.scan_out(dff_lmq4_scanout),
	.din0	(rd_update_pkt4[63:0]),
	.din1   (ld_miss_pkt[63:0]),
	.sel0	(lmc_rd_update[4]),
	.dout	(lmq4_pkt[63:0]),
	.clk    (l2clk),
	.en	(lmc_lmq_enable_b[4]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq5      (
	.scan_in(dff_lmq5_scanin),
	.scan_out(dff_lmq5_scanout),
	.din0	(rd_update_pkt5[63:0]),
	.din1   (ld_miss_pkt[63:0]),
	.sel0	(lmc_rd_update[5]),
	.dout	(lmq5_pkt[63:0]),
	.clk    (l2clk),
	.en	(lmc_lmq_enable_b[5]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq6      (
	.scan_in(dff_lmq6_scanin),
	.scan_out(dff_lmq6_scanout),
	.din0	(rd_update_pkt6[63:0]),
	.din1   (ld_miss_pkt[63:0]),
	.sel0	(lmc_rd_update[6]),
	.dout	(lmq6_pkt[63:0]),
	.clk    (l2clk),
	.en	(lmc_lmq_enable_b[6]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq7      (
	.scan_in(dff_lmq7_scanin),
	.scan_out(dff_lmq7_scanout),
	.din0	(rd_update_pkt7[63:0]),
	.din1   (ld_miss_pkt[63:0]),
	.sel0	(lmc_rd_update[7]),
	.dout	(lmq7_pkt[63:0]),
	.clk    (l2clk),
	.en	(lmc_lmq_enable_b[7]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Export ASI flags to LMQ control
lsu_lmd_dp_buff_macro__width_8 asi_ld_buf  (
	.din	({lmq7_pkt[`LMQ_ASI],lmq6_pkt[`LMQ_ASI],lmq5_pkt[`LMQ_ASI],lmq4_pkt[`LMQ_ASI],
		  lmq3_pkt[`LMQ_ASI],lmq2_pkt[`LMQ_ASI],lmq1_pkt[`LMQ_ASI],lmq0_pkt[`LMQ_ASI]}),
	.dout	(lmd_asi_ld[7:0])
);

// Export ASI indeterminate flags to LMQ control
lsu_lmd_dp_buff_macro__width_8 asi_indet_buf  (
	.din	({lmq7_pkt[`LMQ_ASI_IND],lmq6_pkt[`LMQ_ASI_IND],lmq5_pkt[`LMQ_ASI_IND],lmq4_pkt[`LMQ_ASI_IND],
		  lmq3_pkt[`LMQ_ASI_IND],lmq2_pkt[`LMQ_ASI_IND],lmq1_pkt[`LMQ_ASI_IND],lmq0_pkt[`LMQ_ASI_IND]}),
	.dout	(lmd_asi_indet[7:0])
);

// Mux out the index of the load miss address for I$ to use for xinval
lsu_lmd_dp_mux_macro__mux_aodec__ports_8__stack_6l__width_6 xinval_indx_mx     (
	.din0	(lmq0_pkt[10:5]),
	.din1	(lmq1_pkt[10:5]),
	.din2	(lmq2_pkt[10:5]),
	.din3	(lmq3_pkt[10:5]),
	.din4	(lmq4_pkt[10:5]),
	.din5	(lmq5_pkt[10:5]),
	.din6	(lmq6_pkt[10:5]),
	.din7	(lmq7_pkt[10:5]),
	.sel	(lsu_cpx_cpkt[8:6]),
	.dout	(ifu_ld_index[10:5])
);
lsu_lmd_dp_buff_macro__stack_6l__width_6 xinval_indx_buf   (
	.din	(ifu_ld_index[10:5]),
	.dout	(lsu_ifu_ld_index[10:5])
);

////////////////////////////////////////////////////////////////////////////////
// Secondary miss comparators
////////////////////////////////////////////////////////////////////////////////

assign cmp_addr[39:4] = ld_addr_b[39:4];

lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_0  (
	.din0	({4'b0000,cmp_addr[31:4]}),
	.din1	({4'b0000,lmq0_pkt[31:4]}),
	.dout	(sec_cmp_lo[0])
);
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_0  (
	.din0	(cmp_addr[39:32]),
	.din1	(lmq0_pkt[39:32]),
	.dout	(sec_cmp_hi[0])
);
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_0   (
	.din0	(sec_cmp_lo[0]),
	.din1	(sec_cmp_hi[0]),
	.din2	(lmc_ld_unfilled[0]),
	.dout	(lmd_sec_cmp_b[0])
);

lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_1  (
	.din0	({4'b0000,cmp_addr[31:4]}),
	.din1	({4'b0000,lmq1_pkt[31:4]}),
	.dout	(sec_cmp_lo[1])
);
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_1  (
	.din0	(cmp_addr[39:32]),
	.din1	(lmq1_pkt[39:32]),
	.dout	(sec_cmp_hi[1])
);
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_1   (
	.din0	(sec_cmp_lo[1]),
	.din1	(sec_cmp_hi[1]),
	.din2	(lmc_ld_unfilled[1]),
	.dout	(lmd_sec_cmp_b[1])
);

lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_2  (
	.din0	({4'b0000,cmp_addr[31:4]}),
	.din1	({4'b0000,lmq2_pkt[31:4]}),
	.dout	(sec_cmp_lo[2])
);
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_2  (
	.din0	(cmp_addr[39:32]),
	.din1	(lmq2_pkt[39:32]),
	.dout	(sec_cmp_hi[2])
);
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_2   (
	.din0	(sec_cmp_lo[2]),
	.din1	(sec_cmp_hi[2]),
	.din2	(lmc_ld_unfilled[2]),
	.dout	(lmd_sec_cmp_b[2])
);

lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_3  (
	.din0	({4'b0000,cmp_addr[31:4]}),
	.din1	({4'b0000,lmq3_pkt[31:4]}),
	.dout	(sec_cmp_lo[3])
);
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_3  (
	.din0	(cmp_addr[39:32]),
	.din1	(lmq3_pkt[39:32]),
	.dout	(sec_cmp_hi[3])
);
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_3   (
	.din0	(sec_cmp_lo[3]),
	.din1	(sec_cmp_hi[3]),
	.din2	(lmc_ld_unfilled[3]),
	.dout	(lmd_sec_cmp_b[3])
);

lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_4  (
	.din0	({4'b0000,cmp_addr[31:4]}),
	.din1	({4'b0000,lmq4_pkt[31:4]}),
	.dout	(sec_cmp_lo[4])
);
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_4  (
	.din0	(cmp_addr[39:32]),
	.din1	(lmq4_pkt[39:32]),
	.dout	(sec_cmp_hi[4])
);
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_4   (
	.din0	(sec_cmp_lo[4]),
	.din1	(sec_cmp_hi[4]),
	.din2	(lmc_ld_unfilled[4]),
	.dout	(lmd_sec_cmp_b[4])
);

lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_5  (
	.din0	({4'b0000,cmp_addr[31:4]}),
	.din1	({4'b0000,lmq5_pkt[31:4]}),
	.dout	(sec_cmp_lo[5])
);
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_5  (
	.din0	(cmp_addr[39:32]),
	.din1	(lmq5_pkt[39:32]),
	.dout	(sec_cmp_hi[5])
);
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_5   (
	.din0	(sec_cmp_lo[5]),
	.din1	(sec_cmp_hi[5]),
	.din2	(lmc_ld_unfilled[5]),
	.dout	(lmd_sec_cmp_b[5])
);

lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_6  (
	.din0	({4'b0000,cmp_addr[31:4]}),
	.din1	({4'b0000,lmq6_pkt[31:4]}),
	.dout	(sec_cmp_lo[6])
);
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_6  (
	.din0	(cmp_addr[39:32]),
	.din1	(lmq6_pkt[39:32]),
	.dout	(sec_cmp_hi[6])
);
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_6   (
	.din0	(sec_cmp_lo[6]),
	.din1	(sec_cmp_hi[6]),
	.din2	(lmc_ld_unfilled[6]),
	.dout	(lmd_sec_cmp_b[6])
);

lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_7  (
	.din0	({4'b0000,cmp_addr[31:4]}),
	.din1	({4'b0000,lmq7_pkt[31:4]}),
	.dout	(sec_cmp_lo[7])
);
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_7  (
	.din0	(cmp_addr[39:32]),
	.din1	(lmq7_pkt[39:32]),
	.dout	(sec_cmp_hi[7])
);
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_7   (
	.din0	(sec_cmp_lo[7]),
	.din1	(sec_cmp_hi[7]),
	.din2	(lmc_ld_unfilled[7]),
	.dout	(lmd_sec_cmp_b[7])
);

////////////////////////////////////////////////////////////////////////////////
// Select one thread to issue to the pcx or asi interface
////////////////////////////////////////////////////////////////////////////////

lsu_lmd_dp_mux_macro__mux_aonpe__ports_8__stack_64c__width_51 lmq_pcx_mux      (
	.din0	({lmq0_pkt[55],lmq0_pkt[49:0]}),
	.din1	({lmq1_pkt[55],lmq1_pkt[49:0]}),
	.din2	({lmq2_pkt[55],lmq2_pkt[49:0]}),
	.din3	({lmq3_pkt[55],lmq3_pkt[49:0]}),
	.din4	({lmq4_pkt[55],lmq4_pkt[49:0]}),
	.din5	({lmq5_pkt[55],lmq5_pkt[49:0]}),
	.din6	({lmq6_pkt[55],lmq6_pkt[49:0]}),
	.din7	({lmq7_pkt[55],lmq7_pkt[49:0]}),
	.sel0	(lmc_pcx_sel_p4[0]),
	.sel1	(lmc_pcx_sel_p4[1]),
	.sel2	(lmc_pcx_sel_p4[2]),
	.sel3	(lmc_pcx_sel_p4[3]),
	.sel4	(lmc_pcx_sel_p4[4]),
	.sel5	(lmc_pcx_sel_p4[5]),
	.sel6	(lmc_pcx_sel_p4[6]),
	.sel7	(lmc_pcx_sel_p4[7]),
	.dout	({pcx_pkt_b55,pcx_pkt[49:6],pcx_addr[5:4],pcx_pkt[3:0]})
);

lsu_lmd_dp_buff_macro__stack_64c__width_51 lmq_pcx_buf    (
	.din	({pcx_pkt_b55,pcx_pkt[49:0]}),
	.dout	({lmd_asi_rngf,lmd_pcx_pkt[49:0]})
);

assign lmd_pcx_rqtyp[2:0] = lmd_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO];		// 46:44
assign lmd_pcx_nc         = lmd_pcx_pkt[`LMQ_NC];			// 43
assign lmd_pcx_pref       = lmd_pcx_pkt[`LMQ_PREF];			// 42
assign lmd_pcx_rway[1:0]  = lmd_pcx_pkt[`LMQ_WY_HI:`LMQ_WY_LO];		// 41:40
assign lmd_pcx_addr[39:0] = lmd_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO];		// 39:0
assign lmd_asi_type[1:0]  = lmd_pcx_pkt[`LMQ_ASI_TYPE + 1:`LMQ_ASI_TYPE];	// 49:48
assign lmd_ldbl           = lmd_pcx_pkt[`LMQ_LDD];			// 49
assign lmd_asi_asi[7:0]   = lmd_pcx_pkt[`LMQ_ASI_HI:`LMQ_ASI_LO];	// 47:40
assign lmd_sz_b1	  = lmd_pcx_pkt[`LMQ_SZ_LO + 1];		// 48
assign lmd_sz_b0	  = lmd_pcx_pkt[`LMQ_SZ_LO];			// 47


assign lmd_addrb2 = lmd_pcx_pkt[2];

lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_64c__width_2 bld_addr_mux       (
	.din0	(lmc_bld_addr54[1:0]),
	.din1	(pcx_addr[5:4]),
	.sel0	(lmc_bld_req),
	.sel1	(lmc_bld_req_),
	.dout	(pcx_pkt[5:4])
);

////////////////////////////////////////////////////////////////////////////////
// Data for fills and bypass
////////////////////////////////////////////////////////////////////////////////

lsu_lmd_dp_mux_macro__dbuff_32x__dmux_4x__mux_aonpe__ports_8__stack_64c__width_15 lmq_data_mux_e       (
	.din0	({lmq0_pkt[59:50],lmq0_pkt[48:47],lmq0_pkt[2:0]}),
	.din1	({lmq1_pkt[59:50],lmq1_pkt[48:47],lmq1_pkt[2:0]}),
	.din2	({lmq2_pkt[59:50],lmq2_pkt[48:47],lmq2_pkt[2:0]}),
	.din3	({lmq3_pkt[59:50],lmq3_pkt[48:47],lmq3_pkt[2:0]}),
	.din4	({lmq4_pkt[59:50],lmq4_pkt[48:47],lmq4_pkt[2:0]}),
	.din5	({lmq5_pkt[59:50],lmq5_pkt[48:47],lmq5_pkt[2:0]}),
	.din6	({lmq6_pkt[59:50],lmq6_pkt[48:47],lmq6_pkt[2:0]}),
	.din7	({lmq7_pkt[59:50],lmq7_pkt[48:47],lmq7_pkt[2:0]}),
	.sel0	(lmc_byp_sel_e[0]),
	.sel1	(lmc_byp_sel_e[1]),
	.sel2	(lmc_byp_sel_e[2]),
	.sel3	(lmc_byp_sel_e[3]),
	.sel4	(lmc_byp_sel_e[4]),
	.sel5	(lmc_byp_sel_e[5]),
	.sel6	(lmc_byp_sel_e[6]),
	.sel7	(lmc_byp_sel_e[7]),
	.dout	({lmd_fpodd32b_e,lmd_fp32b_e,lmd_fpld_e,lmd_sxt_fsr_e,lmd_bendian_e,
		  rd_e[4:0],lmd_sz_e[1:0],ld_addr_e[2:0]})
);

lsu_lmd_dp_mux_macro__mux_aodec__ports_8__width_45 lmq_mux_e    (
	.din0	(lmq0_or_diag[44:0]),
	.din1	({lmq1_pkt[63:62],lmq1_pkt[`LMQ_TPAR],lmq1_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
		  lmq1_pkt[`LMQ_SZ_LO],lmq1_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq1_pkt[39:3]}),
	.din2	({lmq2_pkt[63:62],lmq2_pkt[`LMQ_TPAR],lmq2_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
		  lmq2_pkt[`LMQ_SZ_LO],lmq2_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq2_pkt[39:3]}),
	.din3	({lmq3_pkt[63:62],lmq3_pkt[`LMQ_TPAR],lmq3_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
		  lmq3_pkt[`LMQ_SZ_LO],lmq3_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq3_pkt[39:3]}),
	.din4	({lmq4_pkt[63:62],lmq4_pkt[`LMQ_TPAR],lmq4_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
		  lmq4_pkt[`LMQ_SZ_LO],lmq4_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq4_pkt[39:3]}),
	.din5	({lmq5_pkt[63:62],lmq5_pkt[`LMQ_TPAR],lmq5_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
		  lmq5_pkt[`LMQ_SZ_LO],lmq5_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq5_pkt[39:3]}),
	.din6	({lmq6_pkt[63:62],lmq6_pkt[`LMQ_TPAR],lmq6_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
		  lmq6_pkt[`LMQ_SZ_LO],lmq6_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq6_pkt[39:3]}),
	.din7	({lmq7_pkt[63:62],lmq7_pkt[`LMQ_TPAR],lmq7_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
		  lmq7_pkt[`LMQ_SZ_LO],lmq7_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq7_pkt[39:3]}),
	.sel	(cid_tid[2:0]),
	.dout	(lmd_muxdata_e[44:0])
);

// Must mux in bist and diag write data for tag portion
lsu_lmd_dp_mux_macro__left_11__mux_aope__ports_2__stack_64c__width_29 bist_mx      (
	.din0	({mbi_wdata[4:0],{3{mbi_wdata[7:0]}}}),
	.din1	(diag_data_w_buf[30:2]),
	.sel0	(lmc_mbi_run),
	.dout	(diag_addr_e[39:11])
);
assign lmq0_or_diag[44:43] = lmq0_pkt[63:62];
assign lmq0_or_diag[41:39] = {lmq0_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],lmq0_pkt[`LMQ_SZ_LO]};

lsu_lmd_dp_mux_macro__left_3__mux_aope__ports_2__stack_64c__width_40 diag_mx      (
	.din0	({wrtag_parity_w,lsu_va_w[12:11],diag_addr_e[39:11],lsu_va_w[10:3]}),
	.din1	({lmq0_pkt[`LMQ_TPAR],lmq0_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq0_pkt[39:3]}),
	.sel0	(lmc_bist_or_diag_e),
	.dout	({lmq0_or_diag[42],lmq0_or_diag[38:0]})
);

lsu_lmd_dp_buff_macro__width_45 lmq_buf_e  (
	.din	(lmd_muxdata_e[44:0]),
	.dout	({lmd_dc_err_e[1:0],lmd_wrtag_parity_e,lmd_rd_e[2:1],lmd_fill_sz_b0_e,
		  lmd_fill_way_e[1:0], lmd_fill_addr_e[39:3]})
);

lsu_lmd_dp_msff_macro__stack_64c__width_25 dff_lmq_data_m    (
	.scan_in(dff_lmq_data_m_scanin),
	.scan_out(dff_lmq_data_m_scanout),
	.din    ({wrtag_parity_b,
		  lmd_fpodd32b_e,lmd_fp32b_e,lmd_fpld_e,lmd_sxt_fsr_e,lmd_bendian_e,
                      rd_e[4:0],lmd_sz_e[1:0],lmd_fill_way_e[1:0],lmd_fill_addr_e[10:4],ld_addr_e[2:0]}),
	.dout	({wrtag_parity_w,
		  lmd_fpodd32b_m,lmd_fp32b_m,lmd_fpld_m,lmd_sxt_fsr_m,lmd_bendian_m,
                  lmd_rd_m[4:0],lmd_sz_m[1:0],lmd_fill_way_m[1:0],lmd_fill_addr_m[10:4],lmd_ld_addr_m[2:0]}),
	.clk    (l2clk),
	.en	(1'b1),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

////////////////////////////////////////////////////////////////////////////////
// Load data bypassing
// Bypass registers can hold the following data
// 0 - swap data for CAS instructions
// 1 - load data for ASI ring operations
// 2 - RAW bypass data from STB
// 3 - load data for LSU ASI registers (non-STB)
// 4 - load data for LSU ASI registers (STB)
// 5 - parity update for STB CAM read
////////////////////////////////////////////////////////////////////////////////

// These come from the other side of LSU so buffer off the load of the eight muxes
lsu_lmd_dp_buff_macro__rep_1__width_64 st_data_buf  (
	.din	(sbd_st_data_b[63:0]),
	.dout	(st_data_b[63:0])
);
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_stb_ram_data  (
	.din	(stb_ram_data[63:0]),
	.dout	(stb_ram_data_buf[63:0])
);
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_stb_asi_data  (
	.din	(stb_ldxa_asi_data_w[63:0]),
	.dout	(stb_ldxa_asi_data_w_buf[63:0])
);
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_ard_pid_data  (
	.din	(ard_pid_data[63:0]),
	.dout	(ard_pid_data_buf[63:0])
);

// Rebuffer for the load of the eight muxes
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_dcs_asi_data  (
	.din	(dcs_ldxa_asi_data_w[63:0]),
	.dout	(dcs_ldxa_asi_data_w_buf[63:0])
);

lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp0      (
	.scan_in(dff_ldbyp0_scanin),
	.scan_out(dff_ldbyp0_scanout),
	.din0	(st_data_b[63:0]),
	.din1	(ard_pid_data_buf[63:0]),
	.din2	(stb_ram_data_buf[63:0]),
	.din3	(dcs_ldxa_asi_data_w_buf[63:0]),
	.din4	(stb_ldxa_asi_data_w_buf[63:0]),
	.sel0	(lmc_lmq0_byp_sel[0]),
	.sel1	(lmc_lmq0_byp_sel[1]),
	.sel2	(lmc_lmq0_byp_sel[2]),
	.sel3	(lmc_lmq0_byp_sel[3]),
	.sel4	(lmc_lmq0_byp_sel[4]),
	.dout	(lmq0_bypass_data[63:0]),
	.clk	(l2clk),
	.en	(lmc_lmq_bypass_en[0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp1      (
	.scan_in(dff_ldbyp1_scanin),
	.scan_out(dff_ldbyp1_scanout),
	.din0	(st_data_b[63:0]),
	.din1	(ard_pid_data_buf[63:0]),
	.din2	(stb_ram_data_buf[63:0]),
	.din3	(dcs_ldxa_asi_data_w_buf[63:0]),
	.din4	(stb_ldxa_asi_data_w_buf[63:0]),
	.sel0	(lmc_lmq1_byp_sel[0]),
	.sel1	(lmc_lmq1_byp_sel[1]),
	.sel2	(lmc_lmq1_byp_sel[2]),
	.sel3	(lmc_lmq1_byp_sel[3]),
	.sel4	(lmc_lmq1_byp_sel[4]),
	.dout	(lmq1_bypass_data[63:0]),
	.clk	(l2clk),
	.en	(lmc_lmq_bypass_en[1]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp2      (
	.scan_in(dff_ldbyp2_scanin),
	.scan_out(dff_ldbyp2_scanout),
	.din0	(st_data_b[63:0]),
	.din1	(ard_pid_data_buf[63:0]),
	.din2	(stb_ram_data_buf[63:0]),
	.din3	(dcs_ldxa_asi_data_w_buf[63:0]),
	.din4	(stb_ldxa_asi_data_w_buf[63:0]),
	.sel0	(lmc_lmq2_byp_sel[0]),
	.sel1	(lmc_lmq2_byp_sel[1]),
	.sel2	(lmc_lmq2_byp_sel[2]),
	.sel3	(lmc_lmq2_byp_sel[3]),
	.sel4	(lmc_lmq2_byp_sel[4]),
	.dout	(lmq2_bypass_data[63:0]),
	.clk	(l2clk),
	.en	(lmc_lmq_bypass_en[2]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp3      (
	.scan_in(dff_ldbyp3_scanin),
	.scan_out(dff_ldbyp3_scanout),
	.din0	(st_data_b[63:0]),
	.din1	(ard_pid_data_buf[63:0]),
	.din2	(stb_ram_data_buf[63:0]),
	.din3	(dcs_ldxa_asi_data_w_buf[63:0]),
	.din4	(stb_ldxa_asi_data_w_buf[63:0]),
	.sel0	(lmc_lmq3_byp_sel[0]),
	.sel1	(lmc_lmq3_byp_sel[1]),
	.sel2	(lmc_lmq3_byp_sel[2]),
	.sel3	(lmc_lmq3_byp_sel[3]),
	.sel4	(lmc_lmq3_byp_sel[4]),
	.dout	(lmq3_bypass_data[63:0]),
	.clk	(l2clk),
	.en	(lmc_lmq_bypass_en[3]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp4      (
	.scan_in(dff_ldbyp4_scanin),
	.scan_out(dff_ldbyp4_scanout),
	.din0	(st_data_b[63:0]),
	.din1	(ard_pid_data_buf[63:0]),
	.din2	(stb_ram_data_buf[63:0]),
	.din3	(dcs_ldxa_asi_data_w_buf[63:0]),
	.din4	(stb_ldxa_asi_data_w_buf[63:0]),
	.sel0	(lmc_lmq4_byp_sel[0]),
	.sel1	(lmc_lmq4_byp_sel[1]),
	.sel2	(lmc_lmq4_byp_sel[2]),
	.sel3	(lmc_lmq4_byp_sel[3]),
	.sel4	(lmc_lmq4_byp_sel[4]),
	.dout	(lmq4_bypass_data[63:0]),
	.clk	(l2clk),
	.en	(lmc_lmq_bypass_en[4]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp5      (
	.scan_in(dff_ldbyp5_scanin),
	.scan_out(dff_ldbyp5_scanout),
	.din0	(st_data_b[63:0]),
	.din1	(ard_pid_data_buf[63:0]),
	.din2	(stb_ram_data_buf[63:0]),
	.din3	(dcs_ldxa_asi_data_w_buf[63:0]),
	.din4	(stb_ldxa_asi_data_w_buf[63:0]),
	.sel0	(lmc_lmq5_byp_sel[0]),
	.sel1	(lmc_lmq5_byp_sel[1]),
	.sel2	(lmc_lmq5_byp_sel[2]),
	.sel3	(lmc_lmq5_byp_sel[3]),
	.sel4	(lmc_lmq5_byp_sel[4]),
	.dout	(lmq5_bypass_data[63:0]),
	.clk	(l2clk),
	.en	(lmc_lmq_bypass_en[5]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp6      (
	.scan_in(dff_ldbyp6_scanin),
	.scan_out(dff_ldbyp6_scanout),
	.din0	(st_data_b[63:0]),
	.din1	(ard_pid_data_buf[63:0]),
	.din2	(stb_ram_data_buf[63:0]),
	.din3	(dcs_ldxa_asi_data_w_buf[63:0]),
	.din4	(stb_ldxa_asi_data_w_buf[63:0]),
	.sel0	(lmc_lmq6_byp_sel[0]),
	.sel1	(lmc_lmq6_byp_sel[1]),
	.sel2	(lmc_lmq6_byp_sel[2]),
	.sel3	(lmc_lmq6_byp_sel[3]),
	.sel4	(lmc_lmq6_byp_sel[4]),
	.dout	(lmq6_bypass_data[63:0]),
	.clk	(l2clk),
	.en	(lmc_lmq_bypass_en[6]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp7      (
	.scan_in(dff_ldbyp7_scanin),
	.scan_out(dff_ldbyp7_scanout),
	.din0	(st_data_b[63:0]),
	.din1	(ard_pid_data_buf[63:0]),
	.din2	(stb_ram_data_buf[63:0]),
	.din3	(dcs_ldxa_asi_data_w_buf[63:0]),
	.din4	(stb_ldxa_asi_data_w_buf[63:0]),
	.sel0	(lmc_lmq7_byp_sel[0]),
	.sel1	(lmc_lmq7_byp_sel[1]),
	.sel2	(lmc_lmq7_byp_sel[2]),
	.sel3	(lmc_lmq7_byp_sel[3]),
	.sel4	(lmc_lmq7_byp_sel[4]),
	.dout	(lmq7_bypass_data[63:0]),
	.clk	(l2clk),
	.en	(lmc_lmq_bypass_en[7]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// 0in bits_on -var lmc_thrd_byp_sel_m[7:0] -max 1

lsu_lmd_dp_mux_macro__dmux_4x__mux_aonpe__ports_8__stack_64c__width_64 ldbyp_data_mux      (
	.din0	(lmq0_bypass_data[63:0]),
	.din1	(lmq1_bypass_data[63:0]),
	.din2	(lmq2_bypass_data[63:0]),
	.din3	(lmq3_bypass_data[63:0]),
	.din4	(lmq4_bypass_data[63:0]),
	.din5	(lmq5_bypass_data[63:0]),
	.din6	(lmq6_bypass_data[63:0]),
	.din7	(lmq7_bypass_data[63:0]),
	.sel0	(lmc_thrd_byp_sel_m[0]),
	.sel1	(lmc_thrd_byp_sel_m[1]),
	.sel2	(lmc_thrd_byp_sel_m[2]),
	.sel3	(lmc_thrd_byp_sel_m[3]),
	.sel4	(lmc_thrd_byp_sel_m[4]),
	.sel5	(lmc_thrd_byp_sel_m[5]),
	.sel6	(lmc_thrd_byp_sel_m[6]),
	.sel7	(lmc_thrd_byp_sel_m[7]),
	.dout	(bypass_data_m[63:0])
);

lsu_lmd_dp_buff_macro__rep_1__stack_64c__width_64 ldbyp_data_buf   (
	.din	(bypass_data_m[63:0]),
	.dout	(lmd_bypass_data_m[63:0])
);

////////////////////////////////////////////////////////////////////////////////
// L2 Fill Data
// Normal fill data comes from cid.  Diagnostic store data will come from the
// ASI ring.
////////////////////////////////////////////////////////////////////////////////

lsu_lmd_dp_msff_macro__width_64 dff_st_data_w   (
	.scan_in(dff_st_data_w_scanin),
	.scan_out(dff_st_data_w_scanout),
	.din	(st_data_b[63:0]),
	.dout	(diag_data_w[63:0]),
	.clk    (l2clk),
	.en	(dcc_cache_diag_wr_b),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_buff_macro__left_11__rep_1__stack_64c__width_29 diag_data_buf    (
	.din	(diag_data_w[30:2]),
	.dout	(diag_data_w_buf[30:2])
);

lsu_lmd_dp_mux_macro__mux_aope__ports_3__width_64 mx_fill_data_hi     (
	.din0	(diag_data_w[63:0]),
	.din1	(cid_fill_data_e[63:0]),
	.din2	(cid_fill_data_e[127:64]),
	.sel0	(cic_diag_data_sel_e),
	.sel1	(cid_st_data_sel),
	.dout	(fill_data_e[127:64])
);
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_fill_data_hi  (
	.din	(fill_data_e[127:64]),
	.dout	(lmd_fill_data_e[127:64])
);

lsu_lmd_dp_mux_macro__mux_aope__ports_2__width_64 mx_fill_data_lo     (
	.din0	(diag_data_w[63:0]),
	.din1	(cid_fill_data_e[63:0]),
	.sel0	(cic_diag_data_sel_e),
	.dout	(fill_data_e[63:0])
);
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_fill_data_lo  (
	.din	(fill_data_e[63:0]),
	.dout	(lmd_fill_data_e[63:0])
);


////////////////////////////////////////////////////////////////////////////////
// Data bypassing
////////////////////////////////////////////////////////////////////////////////

// Select the correct dword for bypassing
lsu_lmd_dp_msff_macro__mux_aope__ports_2__width_64 byp_half_sel     (
	.scan_in(byp_half_sel_scanin),
	.scan_out(byp_half_sel_scanout),
	.din0	(cid_fill_data_e[127:64]),
	.din1	(cid_fill_data_e[63:0]),
	.sel0	(lmc_byp_data_hi),
	.dout	(fill_data_m[63:0]),
	.clk    (l2clk),
	.en	(lmc_byp_data_enable),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_lmd_dp_buff_macro__width_11 int_buf  (
	.din	({fill_data_m[15:14],fill_data_m[10:8],fill_data_m[5:0]}),
	.dout	({lsu_ext_int_type[1:0],lsu_ext_int_tid[2:0],lsu_ext_int_vec[5:0]})
);

lsu_lmd_dp_mux_macro__mux_pgpe__ports_2__width_64 stgb_l2fd     (
	.din0	(fill_data_m[63:0]),
	.din1	(lmd_bypass_data_m[63:0]),
	.dout	(lmd_fill_or_byp_data_m[63:0]),
	.sel0	(dcc_l2fill_vld_m)
);

lsu_lmd_dp_buff_macro__width_8 msb_buf  (
	.din	({lmd_fill_or_byp_data_m[63],lmd_fill_or_byp_data_m[55],
                  lmd_fill_or_byp_data_m[47],lmd_fill_or_byp_data_m[39],
                  lmd_fill_or_byp_data_m[31],lmd_fill_or_byp_data_m[23],
                  lmd_fill_or_byp_data_m[15],lmd_fill_or_byp_data_m[7]}),
	.dout	(lmd_misc_msb_m[7:0])
);

// fixscan start:
assign dff_lmq0_scanin           = scan_in                  ;
assign dff_lmq1_scanin           = dff_lmq0_scanout         ;
assign dff_lmq2_scanin           = dff_lmq1_scanout         ;
assign dff_lmq3_scanin           = dff_lmq2_scanout         ;
assign dff_lmq4_scanin           = dff_lmq3_scanout         ;
assign dff_lmq5_scanin           = dff_lmq4_scanout         ;
assign dff_lmq6_scanin           = dff_lmq5_scanout         ;
assign dff_lmq7_scanin           = dff_lmq6_scanout         ;
assign dff_lmq_data_m_scanin     = dff_lmq7_scanout         ;
assign dff_ldbyp0_scanin         = dff_lmq_data_m_scanout   ;
assign dff_ldbyp1_scanin         = dff_ldbyp0_scanout       ;
assign dff_ldbyp2_scanin         = dff_ldbyp1_scanout       ;
assign dff_ldbyp3_scanin         = dff_ldbyp2_scanout       ;
assign dff_ldbyp4_scanin         = dff_ldbyp3_scanout       ;
assign dff_ldbyp5_scanin         = dff_ldbyp4_scanout       ;
assign dff_ldbyp6_scanin         = dff_ldbyp5_scanout       ;
assign dff_ldbyp7_scanin         = dff_ldbyp6_scanout       ;
assign dff_st_data_w_scanin      = dff_ldbyp7_scanout       ;
assign byp_half_sel_scanin       = dff_st_data_w_scanout    ;
assign scan_out                  = byp_half_sel_scanout     ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__rep_1__stack_64c__width_40 (
  din, 
  dout);
  input [39:0] din;
  output [39:0] dout;


buff #(40)  d0_0 (
.in(din[39:0]),
.out(dout[39:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__dbuff_32x__rep_1__stack_24c__width_24 (
  din, 
  dout);
  input [23:0] din;
  output [23:0] dout;


buff #(24)  d0_0 (
.in(din[23:0]),
.out(dout[23:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_lmd_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module lsu_lmd_dp_inv_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module lsu_lmd_dp_xor_macro__ports_2__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


xor2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  output [0:0] dout;


mux2s #(1)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
.dout(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__mux_aodec__ports_8__stack_6l__width_6 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [5:0] din0;
  input [5:0] din1;
  input [5:0] din2;
  input [5:0] din3;
  input [5:0] din4;
  input [5:0] din5;
  input [5:0] din6;
  input [5:0] din7;
  input [2:0] sel;
  output [5:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(6)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[5:0]),
  .in1(din1[5:0]),
  .in2(din2[5:0]),
  .in3(din3[5:0]),
  .in4(din4[5:0]),
  .in5(din5[5:0]),
  .in6(din6[5:0]),
  .in7(din7[5:0]),
.dout(dout[5:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__stack_6l__width_6 (
  din, 
  dout);
  input [5:0] din;
  output [5:0] dout;


buff #(6)  d0_0 (
.in(din[5:0]),
.out(dout[5:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_lmd_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_lmd_dp_cmp_macro__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output dout;


cmp #(8)  m0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout)
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module lsu_lmd_dp_and_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


and3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__mux_aonpe__ports_8__stack_64c__width_51 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [50:0] din0;
  input sel0;
  input [50:0] din1;
  input sel1;
  input [50:0] din2;
  input sel2;
  input [50:0] din3;
  input sel3;
  input [50:0] din4;
  input sel4;
  input [50:0] din5;
  input sel5;
  input [50:0] din6;
  input sel6;
  input [50:0] din7;
  input sel7;
  output [50:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(51)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[50:0]),
  .in1(din1[50:0]),
  .in2(din2[50:0]),
  .in3(din3[50:0]),
  .in4(din4[50:0]),
  .in5(din5[50:0]),
  .in6(din6[50:0]),
  .in7(din7[50:0]),
.dout(dout[50:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__stack_64c__width_51 (
  din, 
  dout);
  input [50:0] din;
  output [50:0] dout;


buff #(51)  d0_0 (
.in(din[50:0]),
.out(dout[50:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_64c__width_2 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [1:0] din0;
  input sel0;
  input [1:0] din1;
  input sel1;
  output [1:0] dout;


mux2s #(2)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[1:0]),
  .in1(din1[1:0]),
.dout(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__dbuff_32x__dmux_4x__mux_aonpe__ports_8__stack_64c__width_15 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [14:0] din0;
  input sel0;
  input [14:0] din1;
  input sel1;
  input [14:0] din2;
  input sel2;
  input [14:0] din3;
  input sel3;
  input [14:0] din4;
  input sel4;
  input [14:0] din5;
  input sel5;
  input [14:0] din6;
  input sel6;
  input [14:0] din7;
  input sel7;
  output [14:0] dout;


cl_dp1_muxbuff8_32x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(15)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[14:0]),
  .in1(din1[14:0]),
  .in2(din2[14:0]),
  .in3(din3[14:0]),
  .in4(din4[14:0]),
  .in5(din5[14:0]),
  .in6(din6[14:0]),
  .in7(din7[14:0]),
.dout(dout[14:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__mux_aodec__ports_8__width_45 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [44:0] din0;
  input [44:0] din1;
  input [44:0] din2;
  input [44:0] din3;
  input [44:0] din4;
  input [44:0] din5;
  input [44:0] din6;
  input [44:0] din7;
  input [2:0] sel;
  output [44:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(45)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[44:0]),
  .in1(din1[44:0]),
  .in2(din2[44:0]),
  .in3(din3[44:0]),
  .in4(din4[44:0]),
  .in5(din5[44:0]),
  .in6(din6[44:0]),
  .in7(din7[44:0]),
.dout(dout[44:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__left_11__mux_aope__ports_2__stack_64c__width_29 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [28:0] din0;
  input [28:0] din1;
  input sel0;
  output [28:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(29)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[28:0]),
  .in1(din1[28:0]),
.dout(dout[28:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__left_3__mux_aope__ports_2__stack_64c__width_40 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [39:0] din0;
  input [39:0] din1;
  input sel0;
  output [39:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(40)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[39:0]),
  .in1(din1[39:0]),
.dout(dout[39:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__width_45 (
  din, 
  dout);
  input [44:0] din;
  output [44:0] dout;


buff #(45)  d0_0 (
.in(din[44:0]),
.out(dout[44:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_msff_macro__stack_64c__width_25 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [23:0] so;

  input [24:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [24:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(25)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[24:0]),
.si({scan_in,so[23:0]}),
.so({so[23:0],scan_out}),
.q(dout[24:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__rep_1__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_muxbuff5_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(64)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__dmux_4x__mux_aonpe__ports_8__stack_64c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;
  input [63:0] din5;
  input sel5;
  input [63:0] din6;
  input sel6;
  input [63:0] din7;
  input sel7;
  output [63:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__rep_1__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_msff_macro__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__left_11__rep_1__stack_64c__width_29 (
  din, 
  dout);
  input [28:0] din;
  output [28:0] dout;


buff #(29)  d0_0 (
.in(din[28:0]),
.out(dout[28:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__mux_aope__ports_3__width_64 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input sel0;
  input sel1;
  output [63:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__mux_aope__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_msff_macro__mux_aope__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_lmd_dp_buff_macro__width_11 (
  din, 
  dout);
  input [10:0] din;
  output [10:0] dout;


buff #(11)  d0_0 (
.in(din[10:0]),
.out(dout[10:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_lmd_dp_mux_macro__mux_pgpe__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(64)  d0_0 (
  .sel(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_lru8_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_lru8_ctl (
  l1clk, 
  scan_in, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  request, 
  enable, 
  select);
wire siclk;
wire soclk;
wire dff_lru_scanin;
wire dff_lru_scanout;
wire nlru0_7;
wire nlru0_3;
wire nlru4_7;
wire nlru0_1;
wire nlru2_3;
wire nlru4_5;
wire nlru6_7;
wire lru0_7;
wire lru0_3;
wire lru4_7;
wire lru0_1;
wire lru2_3;
wire lru4_5;
wire lru6_7;
wire pick_0123;
wire pick_4567;
wire pick_01;
wire pick_23;
wire pick_45;
wire pick_67;
wire pick_0;
wire pick_1;
wire pick_2;
wire pick_3;
wire pick_4;
wire pick_5;
wire pick_6;
wire pick_7;


input		l1clk;
input 		scan_in;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input	[7:0]	request;
input	[7:0]	enable;

output	[7:0]	select;

// scan renames
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

////////////////////////////////////////////////////////////////////////////////
// Pseudo-LRU picker to choose the oldest thread for issuing to pcx.
// The picker uses a binary tree to track age.
// lru0_1 -> 0=#0 is newer, 1=#1 is newer
// lru2_3 -> 0=#2 is newer, 1=#3 is newer
// lru0_3 -> 0={0,1} is newer, 1={2,3} is newer
// lru4_7 -> 0={4,5} is newer, 1={6,7} is newer
// lru0_7 -> 0={0,1,2,3} is newer, 1={4,5,6,7} is newer
// The state updates every time an entry is written.  The "least recently written"
// as determined by tracing the tree has priority.
////////////////////////////////////////////////////////////////////////////////

lsu_lru8_ctl_msff_ctl_macro__width_7 dff_lru  (
	.scan_in(dff_lru_scanin),
	.scan_out(dff_lru_scanout),
	.din	({nlru0_7,nlru0_3,nlru4_7,nlru0_1,nlru2_3,nlru4_5,nlru6_7}),
	.dout	({ lru0_7, lru0_3, lru4_7, lru0_1, lru2_3, lru4_5, lru6_7}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pick_0123 = (|request[3:0]) & ( lru0_7 | ~(|request[7:4]));
assign pick_4567 = (|request[7:4]) & (~lru0_7 | ~(|request[3:0]));
assign pick_01 = (|request[1:0]) & ( lru0_3 | ~(|request[3:2]));
assign pick_23 = (|request[3:2]) & (~lru0_3 | ~(|request[1:0]));
assign pick_45 = (|request[5:4]) & ( lru4_7 | ~(|request[7:6]));
assign pick_67 = (|request[7:6]) & (~lru4_7 | ~(|request[5:4]));
assign pick_0 = request[0] & ( lru0_1 | ~request[1]);
assign pick_1 = request[1] & (~lru0_1 | ~request[0]);
assign pick_2 = request[2] & ( lru2_3 | ~request[3]);
assign pick_3 = request[3] & (~lru2_3 | ~request[2]);
assign pick_4 = request[4] & ( lru4_5 | ~request[5]);
assign pick_5 = request[5] & (~lru4_5 | ~request[4]);
assign pick_6 = request[6] & ( lru6_7 | ~request[7]);
assign pick_7 = request[7] & (~lru6_7 | ~request[6]);

assign select[0] = pick_0123 & pick_01 & pick_0;
assign select[1] = pick_0123 & pick_01 & pick_1;
assign select[2] = pick_0123 & pick_23 & pick_2;
assign select[3] = pick_0123 & pick_23 & pick_3;
assign select[4] = pick_4567 & pick_45 & pick_4;
assign select[5] = pick_4567 & pick_45 & pick_5;
assign select[6] = pick_4567 & pick_67 & pick_6;
assign select[7] = pick_4567 & pick_67 & pick_7;

assign nlru0_1 = enable[1] | (~enable[0] & lru0_1);
assign nlru2_3 = enable[3] | (~enable[2] & lru2_3);
assign nlru4_5 = enable[5] | (~enable[4] & lru4_5);
assign nlru6_7 = enable[7] | (~enable[6] & lru6_7);
assign nlru0_3 = (enable[2] | enable[3]) | (~(enable[0] | enable[1]) & lru0_3);
assign nlru4_7 = (enable[6] | enable[7]) | (~(enable[4] | enable[5]) & lru4_7);
assign nlru0_7 = (enable[4] | enable[5] | enable[6] | enable[7]) |
                 (~(enable[0] | enable[1] | enable[2] | enable[3]) &
                   lru0_7);


supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_lru_scanin            = scan_in                  ;
assign scan_out                  = dff_lru_scanout          ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_lru8_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_pic_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_pic_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  lmc_pcx_rq_vld, 
  lmc_asi_rq_vld, 
  lmc_ld_rq_p3, 
  lmc_ld_no_req_p4, 
  tlb_cache_hit_b, 
  dcc_early_ld_b, 
  sbc_asi_rq_p3, 
  sbc_pcx_rq_p3, 
  sbc_st_atomic_p2, 
  sbc_st_rq_p2, 
  sbc_pic_kill_store_p4_, 
  sbc_indet_block_p3, 
  sbs_stb_full, 
  asc_pid_ack, 
  dcc_asi_rtn_vld, 
  lsu_ring_ctl, 
  lsu_misc_pmen, 
  pic_ld_pcx_sel_p4, 
  pic_st_pcx_sel_p3, 
  pic_st_pcx_sel_p4, 
  pic_st_asi_sel_p3, 
  pic_st_asi_p4, 
  pic_ld_asi_p4, 
  pic_st_sel_p3, 
  pic_asi_sel_p4, 
  pic_asi_req, 
  pic_casa_squash_req, 
  pic_early_ld_b_sel_p3, 
  pic_no_load_p3, 
  pic_asi_busy, 
  l15_lsu_grant, 
  lsu_l15_valid, 
  lsu_l15_lock, 
  lsu_asi_clken);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire stb_full_in;
wire dff_stb_full_scanin;
wire dff_stb_full_scanout;
wire stb_full;
wire [1:0] favor_count_inc;
wire [1:0] favor_count;
wire inc_count;
wire st_rq_p3;
wire no_ldst_p3;
wire asi_busy;
wire cancel_store_req_p3;
wire ld_pcx_sel_p3;
wire ld_asi_sel_p3;
wire clear_count;
wire [1:0] favor_count_in;
wire dff_st_favor_scanin;
wire dff_st_favor_scanout;
wire st_favor_p2;
wire st_block_ld_p2;
wire st_favor_p3;
wire st_block_ld_p3;
wire cancel_store_req_p2;
wire unqual_no_load_p2;
wire pcx_atm_p3;
wire block_casa_p3;
wire dff_pic_p2_scanin;
wire dff_pic_p2_scanout;
wire st_atomic_p3;
wire unqual_no_load_p3;
wire early_ld_miss_b;
wire pipe_load_req;
wire fifo_empty;
wire fifo_full;
wire pcx_atm_p4;
wire block_casa_p4;
wire ld_sel_p3;
wire st_sel_p3;
wire early_ld_b_sel_p3;
wire st_pcx_sel_p3;
wire st_asi_sel_p3;
wire any_pcx_sel_p3;
wire dff_pcx_p4_scanin;
wire dff_pcx_p4_scanout;
wire ld_pcx_sel_p4;
wire st_pcx_sel_p4;
wire early_ld_b_sel_pa;
wire cas2_select_p4;
wire cas2_select_p3;
wire dff_cas_select_scanin;
wire dff_cas_select_scanout;
wire last_early_inv;
wire [1:0] fifo_count_next;
wire [1:0] fifo_count;
wire dff_fifo_count_scanin;
wire dff_fifo_count_scanout;
wire dff_asi_ack_scanin;
wire dff_asi_ack_scanout;
wire asi_ack;
wire dff_asi_sel_pa_scanin;
wire dff_asi_sel_pa_scanout;
wire asi_req_ax;
wire kill_asi_st_p5;
wire asi_req_ax_next;
wire kill_asi_st_p4;
wire dff_asi_req_scanin;
wire dff_asi_req_scanout;
wire kill_store_p5_;
wire kill_store_p5__unused;
wire [1:0] asi_dec;
wire [4:0] asi_count_dec;
wire [4:0] asi_count;
wire [4:0] asi_count_in;
wire asi_clken_next;
wire dff_asi_pm_scanin;
wire dff_asi_pm_scanout;
wire spares_scanin;
wire spares_scanout;


input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input		lmc_pcx_rq_vld;		// LMQ needs access to PCX
input		lmc_asi_rq_vld;		// LMQ needs access to PCX
input		lmc_ld_rq_p3;
input		lmc_ld_no_req_p4;

input		tlb_cache_hit_b;
input		dcc_early_ld_b;

input		sbc_asi_rq_p3;		// STB needs access to PCX
input		sbc_pcx_rq_p3;		// STB needs access to PCX
input		sbc_st_atomic_p2;
input		sbc_st_rq_p2;
input		sbc_pic_kill_store_p4_;
input		sbc_indet_block_p3;

input	[7:0]	sbs_stb_full;

input		asc_pid_ack;
input	[7:0]	dcc_asi_rtn_vld;

input		lsu_ring_ctl;
input		lsu_misc_pmen;

output		pic_ld_pcx_sel_p4;	
output		pic_st_pcx_sel_p3;		// store port has access
output		pic_st_pcx_sel_p4;
output		pic_st_asi_sel_p3;
output		pic_st_asi_p4;
output		pic_ld_asi_p4;
output		pic_st_sel_p3;
output		pic_asi_sel_p4;
output		pic_asi_req;
output		pic_casa_squash_req;
output		pic_early_ld_b_sel_p3;
output		pic_no_load_p3;			// load cannot issue
output		pic_asi_busy;

input		l15_lsu_grant;
output		lsu_l15_valid;
output		lsu_l15_lock;
output		lsu_asi_clken;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

//////////////////////////////
// Clock header
//////////////////////////////
lsu_pic_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk                          ),
        .l1en   (1'b1                           ),
        .l1clk  (l1clk                          ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

assign stb_full_in = |(sbs_stb_full[7:0]);

lsu_pic_ctl_msff_ctl_macro__width_1 dff_stb_full  (
	.scan_in(dff_stb_full_scanin),
	.scan_out(dff_stb_full_scanout),
	.din	(stb_full_in),
	.dout	(stb_full),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Source arbitration
// Loads and stores must arbitrate against each other for pcx/asi access
// Loads are generally favored over stores unless
// (i)  stores get favor every 4 cycles if they've been waiting
// (ii) stores get favor every 2 cycles if they've been waiting and a store
//      buffer is full
//  * - CAS second packet (from LMQ) must always follow the first packet
//  * - when a CAS is pending, ALL requests must wait until the FIFO is empty
//      to avoid starving the CAS
//  * - to avoid various potential store livelock cases, if a store request
//      is rejected while the st_favor condition is true, loads requests will
//      be suppressed until the store can be issued
////////////////////////////////////////////////////////////////////////////////

assign favor_count_inc[1:0] = favor_count[1:0] + 2'b01;
assign inc_count = (st_rq_p3 & ~pic_st_sel_p3 & ~no_ldst_p3 & ~(sbc_asi_rq_p3 & asi_busy & (pic_st_asi_p4 | lmc_asi_rq_vld))) | 
                   (cancel_store_req_p3 & (ld_pcx_sel_p3 | ld_asi_sel_p3));
assign clear_count = st_rq_p3 & pic_st_sel_p3;
assign favor_count_in[1:0] = {2{~clear_count}} & (inc_count ? favor_count_inc[1:0] : favor_count[1:0]);

lsu_pic_ctl_msff_ctl_macro__width_4 dff_st_favor  (
	.scan_in(dff_st_favor_scanin),
	.scan_out(dff_st_favor_scanout),
	.din	({st_favor_p2,st_block_ld_p2,favor_count_in[1:0]}),
	.dout	({st_favor_p3,st_block_ld_p3,favor_count[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign st_favor_p2 = ((&favor_count[1:0] | (favor_count[0] & (stb_full | sbc_st_atomic_p2))) & inc_count) |
                     (st_favor_p3 & ~pic_st_sel_p3);

assign st_block_ld_p2 = (st_favor_p3 & st_rq_p3 & ~pic_st_sel_p3) | (st_block_ld_p3 & ~pic_st_sel_p3);

//////////
// P2 - early signals for ld/st arb
//////////

// Still must be qualified with fifo_full in P3
// Loads never win when
// Stores have favor and are requesting OR
// CASA was picked last cycle OR
// CASA was blocked last cycle

// If a store requests but doesn't win arbitration, then stores can't win in the next
// cycle either.  Otherwise, we create a livelock possibility where ST0 wins thread arb
// in p2, but loses ld/st arb in P3.  Meanwhile, ST1 wins thread arb in the next P2, and
// wins ld/st arb in it's P3.  This can continue indefinitely.

assign cancel_store_req_p2 = st_rq_p3 & ~pic_st_sel_p3 & ~cancel_store_req_p3;

assign unqual_no_load_p2 = (st_favor_p2 & sbc_st_rq_p2 & ~cancel_store_req_p2) |
                           st_block_ld_p2 | pcx_atm_p3 | block_casa_p3;

lsu_pic_ctl_msff_ctl_macro__width_4 dff_pic_p2  (
	.scan_in(dff_pic_p2_scanin),
	.scan_out(dff_pic_p2_scanout),
	.din	({sbc_st_atomic_p2,unqual_no_load_p2,sbc_st_rq_p2,cancel_store_req_p2}),
	.dout	({    st_atomic_p3,unqual_no_load_p3,    st_rq_p3,cancel_store_req_p3}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//////////
// P3 - ld/st arb
//////////

assign early_ld_miss_b = dcc_early_ld_b & ~tlb_cache_hit_b;

assign pipe_load_req = early_ld_miss_b & ~lmc_ld_rq_p3;
assign block_casa_p3 = st_atomic_p3 & ~cancel_store_req_p3 & ~fifo_empty;
assign pic_no_load_p3 = unqual_no_load_p3 | fifo_full | block_casa_p3 | sbc_indet_block_p3; 


// Don't select anything if CASA selected last cycle (CAS2 must go) or fifo is full
assign no_ldst_p3 = pcx_atm_p4 | fifo_full | block_casa_p4 | sbc_indet_block_p3;

assign ld_sel_p3 = (lmc_ld_rq_p3 | early_ld_miss_b) & ~pic_no_load_p3;
assign st_sel_p3 = st_rq_p3 & (st_favor_p3 | ~(lmc_ld_rq_p3 | early_ld_miss_b)) & ~block_casa_p3 &
                   ~no_ldst_p3 & ~cancel_store_req_p3;

// 0in bits_on -var {st_sel_p3,ld_sel_p3} -max 1 -message "load and store selected for pcx"

assign early_ld_b_sel_p3 = ld_sel_p3 & ~lmc_ld_rq_p3 & early_ld_miss_b;

// 0in bits_on -var {ld_pcx_sel_p3,ld_asi_sel_p3} -max 1 -message "asi and pcx loads selected"
// 0in bits_on -var {st_pcx_sel_p3,st_asi_sel_p3} -max 1 -message "asi and pcx stores selected"

assign ld_pcx_sel_p3 = ld_sel_p3 & (lmc_pcx_rq_vld | pipe_load_req);
assign st_pcx_sel_p3 = st_sel_p3 & sbc_pcx_rq_p3;

assign ld_asi_sel_p3 = ld_sel_p3 & lmc_asi_rq_vld & ~asi_busy;
assign st_asi_sel_p3 = st_sel_p3 & sbc_asi_rq_p3 & ~asi_busy;

assign pic_st_asi_sel_p3 = st_asi_sel_p3;

assign pic_st_sel_p3 = st_pcx_sel_p3 | st_asi_sel_p3;

assign pic_st_pcx_sel_p3 = st_pcx_sel_p3;
assign pic_early_ld_b_sel_p3 = early_ld_b_sel_p3;	// to lmc


assign any_pcx_sel_p3 = ld_pcx_sel_p3 | st_pcx_sel_p3 | pcx_atm_p4;

assign pcx_atm_p3 = st_pcx_sel_p3 & st_atomic_p3;


lsu_pic_ctl_msff_ctl_macro__width_5 dff_pcx_p4  (
	.scan_in(dff_pcx_p4_scanin),
	.scan_out(dff_pcx_p4_scanout),
	.din	({ld_pcx_sel_p3,st_pcx_sel_p3,early_ld_b_sel_p3,pcx_atm_p3,block_casa_p3}),
	.dout	({ld_pcx_sel_p4,st_pcx_sel_p4,early_ld_b_sel_pa,pcx_atm_p4,block_casa_p4}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//////////
// P4 - drive packets to l1g
//////////

assign pic_ld_pcx_sel_p4 = ld_pcx_sel_p4 | cas2_select_p4;
assign pic_st_pcx_sel_p4 = st_pcx_sel_p4;

assign lsu_l15_valid = (ld_pcx_sel_p4 & ~lmc_ld_no_req_p4) | cas2_select_p4 | pic_st_pcx_sel_p4;

assign pic_casa_squash_req = pcx_atm_p4;

assign lsu_l15_lock = pcx_atm_p4;	// lock for atomic packets

// CAS2 packet comes from LMQ.
assign cas2_select_p3 = pcx_atm_p4;

lsu_pic_ctl_msff_ctl_macro__width_1 dff_cas_select  (
	.scan_in(dff_cas_select_scanin),
	.scan_out(dff_cas_select_scanout),
	.din	(cas2_select_p3),
	.dout	(cas2_select_p4),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Gasket FIFO Queue Tracking
// The gasket contains a two-entry FIFO.  It's the LSU's responsibility to not
// overflow this fifo.  Keep track of requests and grants to maintain the count.
// This count needs to be maintained based on the P3 cycle so that arbitration
// is halted if the FIFO is full.
// Increment the count for each ld/st sent (any_pcx_sel_p3)
// Decrement the count for each grant received (l15_lsu_grant) 
// Decrement the count for a load sent, but invalidated in P4 (last_early_inv)
////////////////////////////////////////////////////////////////////////////////

//assign fifo_count_inc[1:0] = fifo_count[1:0] + 2'b01;
//assign fifo_count_dec[1:0] = fifo_count[1:0] - 2'b01;
//assign fifo_count_dec2[1:0] = fifo_count[1:0] - 2'b10;

assign last_early_inv = early_ld_b_sel_pa & ~lsu_l15_valid;

assign fifo_count_next[1] = (fifo_count[1] & ~last_early_inv & (any_pcx_sel_p3 | ~l15_lsu_grant)) |
                            (fifo_count[0] & any_pcx_sel_p3 & ~l15_lsu_grant & ~last_early_inv) ;

assign fifo_count_next[0] = (fifo_count[0] & ~last_early_inv & (any_pcx_sel_p3 ~^ l15_lsu_grant)) |	// 1->1
                            (~fifo_count[0] & any_pcx_sel_p3 & ~l15_lsu_grant) |			// 0->1
                            (~fifo_count[0] & last_early_inv & (~l15_lsu_grant | any_pcx_sel_p3)) | 	// 2->1
                            (~fifo_count[0] & ~any_pcx_sel_p3 & l15_lsu_grant & ~last_early_inv) | 	// 2->1
                            (any_pcx_sel_p3 & ~l15_lsu_grant & last_early_inv);				// 1->1

lsu_pic_ctl_msff_ctl_macro__width_2 dff_fifo_count  (
	.scan_in(dff_fifo_count_scanin),
	.scan_out(dff_fifo_count_scanout),
	.din	(fifo_count_next[1:0]),
	.dout	(fifo_count[1:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in underflow -var fifo_count[1:0] 
// 0in maximum 2 -var fifo_count[1:0]  

assign fifo_full = fifo_count[1] & ~l15_lsu_grant;
assign fifo_empty = ~fifo_count[1] & (~fifo_count[0] | l15_lsu_grant);

////////
// P4 - ASI
////////

// asc_pid_ack returns (best case) on the same cycle as the packet is sent
lsu_pic_ctl_msff_ctl_macro__width_1 dff_asi_ack  (
	.scan_in(dff_asi_ack_scanin),
	.scan_out(dff_asi_ack_scanout),
	.din	(asc_pid_ack),
	.dout	(asi_ack),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_pic_ctl_msff_ctl_macro__width_2 dff_asi_sel_pa  (
	.scan_in(dff_asi_sel_pa_scanin),
	.scan_out(dff_asi_sel_pa_scanout),
	.din	({ld_asi_sel_p3,st_asi_sel_p3}),
	.dout	({pic_ld_asi_p4,pic_st_asi_p4}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pic_asi_sel_p4 = pic_ld_asi_p4 | pic_st_asi_p4;

assign pic_asi_req = (pic_asi_sel_p4 | asi_req_ax) & ~kill_asi_st_p5;

assign asi_req_ax_next = (pic_asi_sel_p4 | (asi_req_ax & ~asi_ack)) & ~kill_asi_st_p5;

assign kill_asi_st_p4 = pic_st_asi_p4 & ~sbc_pic_kill_store_p4_;

lsu_pic_ctl_msff_ctl_macro__width_3 dff_asi_req  (
	.scan_in(dff_asi_req_scanin),
	.scan_out(dff_asi_req_scanout),
	.din	({asi_req_ax_next,sbc_pic_kill_store_p4_,kill_asi_st_p4}),
	.dout	({asi_req_ax,     kill_store_p5_,        kill_asi_st_p5}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign kill_store_p5__unused = kill_store_p5_;

// ASI interface will be busy in the cycle following a request until the request is acked
assign asi_busy = (pic_asi_sel_p4 | asi_req_ax) & ~asi_ack;
assign pic_asi_busy = asi_busy;

////////////////////////////////////////////////////////////////////////////////
// ASI ring power management
// Keep count of number of ring transactions outstanding.  If >0, enable the ring.
// Increment each time an ASI request is selected (watch for errors)
// Decrement each time it returns from the ring
// Shut down the ring so that bit[64] is held low.
////////////////////////////////////////////////////////////////////////////////

assign asi_dec[1:0] = {1'b0,|(dcc_asi_rtn_vld[7:0])} + {1'b0,kill_asi_st_p5};
assign asi_count_dec[4:0] = asi_count[4:0] - {3'b000,asi_dec[1:0]};

assign asi_count_in[4:0] = asi_count_dec[4:0] + {4'b0000,(ld_asi_sel_p3 | st_asi_sel_p3)};

assign asi_clken_next = ~lsu_misc_pmen | ld_asi_sel_p3 | st_asi_sel_p3 | (|(asi_count[4:0])) |
                        (lsu_asi_clken & ~lsu_ring_ctl);

lsu_pic_ctl_msff_ctl_macro__width_6 dff_asi_pm  (
	.scan_in(dff_asi_pm_scanin),
	.scan_out(dff_asi_pm_scanout),
	.din	({asi_clken_next,asi_count_in[4:0]}),
	.dout	({lsu_asi_clken, asi_count[4:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
// 0in underflow -var asi_count[4:0] 
// 0in overflow -var asi_count[4:0] 


lsu_pic_ctl_spare_ctl_macro__num_1 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_stb_full_scanin       = scan_in                  ;
assign dff_st_favor_scanin       = dff_stb_full_scanout     ;
assign dff_pic_p2_scanin         = dff_st_favor_scanout     ;
assign dff_pcx_p4_scanin         = dff_pic_p2_scanout       ;
assign dff_cas_select_scanin     = dff_pcx_p4_scanout       ;
assign dff_fifo_count_scanin     = dff_cas_select_scanout   ;
assign dff_asi_ack_scanin        = dff_fifo_count_scanout   ;
assign dff_asi_sel_pa_scanin     = dff_asi_ack_scanout      ;
assign dff_asi_req_scanin        = dff_asi_sel_pa_scanout   ;
assign dff_asi_pm_scanin         = dff_asi_req_scanout      ;
assign spares_scanin             = dff_asi_pm_scanout       ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_pic_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_pic_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_pic_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_pic_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_pic_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_pic_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_pic_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_pic_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_pid_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_pid_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  const_cpuid, 
  lmd_bypass_data_m, 
  lmc_ld_tid, 
  lmc_ld_sz, 
  lmd_pcx_rqtyp, 
  lmd_pcx_nc, 
  lmd_pcx_pref, 
  lmd_pcx_rway, 
  lmd_pcx_addr, 
  lmd_asi_rngf, 
  lmd_asi_type, 
  lmd_asi_asi, 
  lmc_ld_vld_p4, 
  lmc_ld_inv_p4, 
  sbc_st_sel_tid_p4, 
  sbc_st_pcx_nc, 
  sbc_st_asi_fs, 
  sbc_pcx_bmask, 
  sbc_pcx_addr, 
  sbc_pcx_rmo_st, 
  sbc_pcx_blk_st, 
  sbc_pid_kill_store_p4_, 
  sbc_force_inv, 
  sbc_st_type_p4, 
  stb_cam_data, 
  stb_ram_data, 
  pic_ld_pcx_sel_p4, 
  pic_st_pcx_sel_p4, 
  pic_st_asi_p4, 
  pic_ld_asi_p4, 
  pic_asi_sel_p4, 
  pic_asi_req, 
  spc_pcx_data_pa, 
  pid_asi_pkt);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [63:0] lmd_cas_pkt2_data;
wire [129:0] load_pcx_pkt;
wire [129:0] store_pcx_pkt;
wire [129:0] pcx_data_pa;
wire [126:0] store_asi_pkt;
wire [126:0] load_asi_pkt;
wire [126:0] asi_pkt_hold;
wire dff_asi_pkt_hi_scanin;
wire dff_asi_pkt_hi_scanout;
wire dff_asi_pkt_lo_scanin;
wire dff_asi_pkt_lo_scanout;


input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input	[2:0]	const_cpuid;		// hardwired CPU ID

input	[63:0]	lmd_bypass_data_m;
input	[2:0]	lmc_ld_tid;		// thread id of load packet
input	[4:0]	lmc_ld_sz;
input	[2:0]	lmd_pcx_rqtyp;     
input		lmd_pcx_nc;        
input		lmd_pcx_pref;      
input	[1:0]	lmd_pcx_rway;
input	[39:0]	lmd_pcx_addr;
input		lmd_asi_rngf;      
input	[1:0]	lmd_asi_type;
input	[7:0]	lmd_asi_asi;
input		lmc_ld_vld_p4;
input		lmc_ld_inv_p4;


input	[2:0]	sbc_st_sel_tid_p4;
input		sbc_st_pcx_nc;
input		sbc_st_asi_fs;
input	[7:0]	sbc_pcx_bmask;
input	[2:0]	sbc_pcx_addr;
input		sbc_pcx_rmo_st;
input		sbc_pcx_blk_st;
input		sbc_pid_kill_store_p4_;
input		sbc_force_inv;
input	[2:0]	sbc_st_type_p4;

input	[44:0]	stb_cam_data;
input	[63:0]	stb_ram_data;

input		pic_ld_pcx_sel_p4;	// load port has access
input		pic_st_pcx_sel_p4;	// store port has access
input		pic_st_asi_p4;
input		pic_ld_asi_p4;
input		pic_asi_sel_p4;
input		pic_asi_req;

output	[129:0]	spc_pcx_data_pa;	// PCX Packet
output	[127:0]	pid_asi_pkt;

// scan renames
assign stop = 1'b0;
// end scan

lsu_pid_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);

assign lmd_cas_pkt2_data[63:0] = lmd_bypass_data_m[63:0];

assign load_pcx_pkt[129:0] = {
  lmc_ld_vld_p4,
  2'b00, lmd_pcx_rqtyp[2:0],			// rqtyp
  lmd_pcx_nc,
  const_cpuid[2:0],
  lmc_ld_tid[2:0],
  lmc_ld_inv_p4, lmd_pcx_pref,			// inval and prefetch 
  1'b0, lmd_pcx_rway[1:0],			// replacement way
  {4{lmc_ld_sz[4]}}, lmc_ld_sz[3:0],		// size
  lmd_pcx_addr[39:0],
  lmd_cas_pkt2_data[63:0]
};

assign store_pcx_pkt[129:0] = {
  sbc_pid_kill_store_p4_,
  2'b00,sbc_st_type_p4[2:0],
  sbc_st_pcx_nc,
  const_cpuid[2:0],
  sbc_st_sel_tid_p4[2:0],
  sbc_force_inv,				// inv
  sbc_pcx_blk_st,				// BST
  sbc_pcx_rmo_st,				// BIS
  2'b00,					// way
  sbc_pcx_bmask[7:0],				// byte mask
  stb_cam_data[44:8], sbc_pcx_addr[2:0],	// address
  stb_ram_data[63:0]
};

// Select the pcx source
lsu_pid_dp_mux_macro__dmux_2x__mux_aonpe__ports_2__stack_66c__width_65 mx_pcx_data_hi       (
	.din0	(load_pcx_pkt[129:65]),
	.din1	(store_pcx_pkt[129:65]),
	.sel0	(pic_ld_pcx_sel_p4),
	.sel1	(pic_st_pcx_sel_p4),
	.dout	(pcx_data_pa[129:65])
);
lsu_pid_dp_mux_macro__dmux_2x__mux_aonpe__ports_2__stack_66c__width_65 mx_pcx_data_lo       (
	.din0	(load_pcx_pkt[64:0]),
	.din1	(store_pcx_pkt[64:0]),
	.sel0	(pic_ld_pcx_sel_p4),
	.sel1	(pic_st_pcx_sel_p4),
	.dout	(pcx_data_pa[64:0])
);

lsu_pid_dp_buff_macro__stack_66c__width_65 buf_pcx_data_hi   (
	.din	(pcx_data_pa[129:65]),
	.dout	(spc_pcx_data_pa[129:65])
);
lsu_pid_dp_buff_macro__stack_66c__width_65 buf_pcx_data_lo   (
	.din	(pcx_data_pa[64:0]),
	.dout	(spc_pcx_data_pa[64:0])
);
////////////////////////////////////////////////////////////////////////////////
// Interface to the ASI block
// Unlike the pcx interface, the asi interface includes the "request" as the
// packet valid bit.  Because the asi interface will reply with an ack on the
// next cycle best case, all packets will be driven for at least two cycles.
////////////////////////////////////////////////////////////////////////////////

assign store_asi_pkt[126:0] = {
  sbc_st_asi_fs,
  sbc_st_type_p4[1:0],
  1'b0,		// write
  sbc_st_sel_tid_p4[2:0],
  stb_cam_data[7:0],					// ASI ID
  8'h00,stb_cam_data[44:8], 3'b0,			// virt. addr
  stb_ram_data[63:0]					// data
};

assign load_asi_pkt[126:0] = {
  lmd_asi_rngf,
  lmd_asi_type[1:0],
  1'b1,
  lmc_ld_tid[2:0],
  lmd_asi_asi[7:0],
  8'h00,lmd_pcx_addr[39:0],
  64'd0
};

lsu_pid_dp_mux_macro__mux_aope__ports_3__stack_66c__width_62 mx_asi_pkt_hi      (
	.din0	(store_asi_pkt[126:65]),
	.din1	(load_asi_pkt[126:65]),
	.din2	(asi_pkt_hold[126:65]),
	.sel0	(pic_st_asi_p4),
	.sel1	(pic_ld_asi_p4),
	.dout	(pid_asi_pkt[126:65])
);
lsu_pid_dp_mux_macro__mux_aope__ports_3__stack_66c__width_65 mx_asi_pkt_lo      (
	.din0	(store_asi_pkt[64:0]),
	.din1	(load_asi_pkt[64:0]),
	.din2	(asi_pkt_hold[64:0]),
	.sel0	(pic_st_asi_p4),
	.sel1	(pic_ld_asi_p4),
	.dout	(pid_asi_pkt[64:0])
);

lsu_pid_dp_msff_macro__stack_66c__width_62 dff_asi_pkt_hi    (
	.scan_in(dff_asi_pkt_hi_scanin),
	.scan_out(dff_asi_pkt_hi_scanout),
	.din	(pid_asi_pkt[126:65]),
	.dout	(asi_pkt_hold[126:65]),
	.clk	(l2clk),
	.en	(pic_asi_sel_p4),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_pid_dp_msff_macro__stack_66c__width_65 dff_asi_pkt_lo    (
	.scan_in(dff_asi_pkt_lo_scanin),
	.scan_out(dff_asi_pkt_lo_scanout),
	.din	(pid_asi_pkt[64:0]),
	.dout	(asi_pkt_hold[64:0]),
	.clk	(l2clk),
	.en	(pic_asi_sel_p4),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign pid_asi_pkt[127] = pic_asi_req;

////////////////////////////////
// Assertions

// Check that CAS packets are always back to back
// 0in assert_sequence -var (spc_pcx_data_pa[129:124] == 6'b100010) (spc_pcx_data_pa[129:124] == 6'b100011) -max 1 -message "CAS packets not back-to-back"

// fixscan start:
assign dff_asi_pkt_hi_scanin     = scan_in                  ;
assign dff_asi_pkt_lo_scanin     = dff_asi_pkt_hi_scanout   ;
assign scan_out                  = dff_asi_pkt_lo_scanout   ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_pid_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_pid_dp_mux_macro__dmux_2x__mux_aonpe__ports_2__stack_66c__width_65 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [64:0] din0;
  input sel0;
  input [64:0] din1;
  input sel1;
  output [64:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(65)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
.dout(dout[64:0])
);


endmodule


//
//   buff macro
//
//


module lsu_pid_dp_buff_macro__stack_66c__width_65 (
  din, 
  dout);
  input [64:0] din;
  output [64:0] dout;


buff #(65)  d0_0 (
.in(din[64:0]),
.out(dout[64:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_pid_dp_mux_macro__mux_aope__ports_3__stack_66c__width_62 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [61:0] din0;
  input [61:0] din1;
  input [61:0] din2;
  input sel0;
  input sel1;
  output [61:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(62)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[61:0]),
  .in1(din1[61:0]),
  .in2(din2[61:0]),
.dout(dout[61:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_pid_dp_mux_macro__mux_aope__ports_3__stack_66c__width_65 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [64:0] din0;
  input [64:0] din1;
  input [64:0] din2;
  input sel0;
  input sel1;
  output [64:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(65)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[64:0]),
  .in1(din1[64:0]),
  .in2(din2[64:0]),
.dout(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_pid_dp_msff_macro__stack_66c__width_62 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [60:0] so;

  input [61:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [61:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(62)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[61:0]),
.si({scan_in,so[60:0]}),
.so({so[60:0],scan_out}),
.q(dout[61:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_pid_dp_msff_macro__stack_66c__width_65 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [63:0] so;

  input [64:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [64:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_red_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_red_ctl (
  efu_spc_fuse_data, 
  efu_spc_fuse_dxfer_en, 
  efu_spc_fuse_dclr, 
  io_cmp_sync_en, 
  cmp_io_sync_en, 
  spc_efu_fuse_ddata, 
  spc_efu_fuse_dxfer_en, 
  hdr_sram_rvalue, 
  hdr_sram_rid, 
  hdr_sram_wr_en, 
  hdr_sram_red_clr, 
  sram_hdr_read_data, 
  l2clk, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_in, 
  scan_out);
wire sram_header_instance_scanin;
wire sram_header_instance_scanout;
wire [3:0] rval_unused;
wire [8:0] rid_unused;


// EFU to SRAM header
input           efu_spc_fuse_data;   // Efuse to dest data info
input           efu_spc_fuse_dxfer_en;// Efuse to dest data valid
input           efu_spc_fuse_dclr;    // EFuse to dest clear corresponding redudancy register
input		io_cmp_sync_en;       // (ccu_slow_cmp_sync_en),
input		cmp_io_sync_en;       // (ccu_cmp_slow_sync_en),


// SRAM header to EFU
output          spc_efu_fuse_ddata;    // Dest to EFU read data return
output          spc_efu_fuse_dxfer_en; // Dest to EFU read data return valid

// SRAM header to SRAM
output  [6:0]   hdr_sram_rvalue;        // Redudancy Value to be written
				        // to SRAM red reg
output  [1:0]   hdr_sram_rid;           // Redudancy ID to address SRAM
					// red reg
output          hdr_sram_wr_en;         // Redudancy register write
					// enable to write to red reg
output          hdr_sram_red_clr;       // Redudancy register clear
					//

// SRAM to SRAM header
input	[6:0]	sram_hdr_read_data;     // Redudancy Read data from SRAM


// other common signals
input           l2clk;
input           tcu_pce_ov;
input           spc_aclk;
input           spc_bclk;
input           tcu_scan_en;
input           scan_in;
output          scan_out;

n2_efuhdr1_ctl sram_header_instance
        (
        // All the I/o ports to and from EFU <-> cluster
        .efu_hdr_write_data        (efu_spc_fuse_data),
        .efu_hdr_xfer_en           (efu_spc_fuse_dxfer_en),
        .io_cmp_sync_en            (io_cmp_sync_en),
        .cmp_io_sync_en            (cmp_io_sync_en),
        .efu_hdr_clr               (efu_spc_fuse_dclr),
        .hdr_efu_read_data         (spc_efu_fuse_ddata),
        .hdr_efu_xfer_en           (spc_efu_fuse_dxfer_en),
        // All other general signals for DFT and clocks
	.tcu_aclk		   (spc_aclk),
	.tcu_bclk		   (spc_bclk),
	.tcu_clk_stop		   (1'b0),
        .scan_in(sram_header_instance_scanin),
        .scan_out(sram_header_instance_scanout),
        .l2clk                     (l2clk),
        // All the I/o ports to and from SRAM
        .sram_hdr_read_data        ({4'b0,sram_hdr_read_data[6:0]}),
        .hdr_sram_rvalue           ({rval_unused[3:0],hdr_sram_rvalue[6:0]}),
        .hdr_sram_rid              ({rid_unused[8:0],hdr_sram_rid[1:0]}),
        .hdr_sram_wr_en            (hdr_sram_wr_en),
        .hdr_sram_red_clr          (hdr_sram_red_clr),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_scan_en(tcu_scan_en)
        );


lsu_red_ctl_spare_ctl_macro__flops_0__num_1 spares   ();


// fixscan start:
assign sram_header_instance_scanin = scan_in                  ;
assign scan_out                  = sram_header_instance_scanout;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_red_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_red_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_red_ctl_msff_ctl_macro__en_1__width_4 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}});


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_red_ctl_msff_ctl_macro__en_1__width_22 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [21:0] fdin;
wire [20:0] so;

  input [21:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [21:0] dout;
  output scan_out;
assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}});


dff #(22)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[21:0]),
.si({scan_in,so[20:0]}),
.so({so[20:0],scan_out}),
.q(dout[21:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_red_ctl_msff_ctl_macro__en_1__width_1 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_red_ctl_msff_ctl_macro__en_1__width_5 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}});


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_red_ctl_spare_ctl_macro__num_4 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));
assign scan_out = so_3;


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_red_ctl_spare_ctl_macro__flops_0__num_1;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_rep_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_rep_dp (
  lmd_fill_or_byp_data_m, 
  lmd_fill_or_byp_data_m_rep1, 
  stb_ram_data, 
  stb_ram_data_rep0, 
  stb_cam_data, 
  stb_cam_data_rep0, 
  sbd_st_data2_b, 
  sbd_st_data2_b_rep0, 
  sbd_st_predata_b, 
  sbd_st_predata_b_rep0, 
  bist_cmp_data, 
  bist_cmp_data_rep0, 
  tlb_tte_ie_b, 
  tlb_tte_ie_b_rep00, 
  tlb_tte_ie_b_rep01, 
  stb_cam_hit, 
  stb_cam_hit_rep0, 
  tlb_cache_way_hit_b, 
  cache_way_hit_top_b, 
  cache_way_hit_bot_b, 
  exu_lsu_store_data_e, 
  exu_lsu_store_data_e_rep0, 
  exu_lsu_address_e, 
  exu_lsu_address_e_rep0);
wire [63:0] lmd_fill_or_byp_data_m_rep0;


input	[63:0]	lmd_fill_or_byp_data_m;
output	[63:0]	lmd_fill_or_byp_data_m_rep1;

input	[63:0]	stb_ram_data;
output	[63:0]	stb_ram_data_rep0;

input	[44:0]	stb_cam_data;
output	[44:0]	stb_cam_data_rep0;

input	[63:0]	sbd_st_data2_b;
output	[63:0]	sbd_st_data2_b_rep0;

input	[47:0]	sbd_st_predata_b;
output	[47:0]	sbd_st_predata_b_rep0;

input	[7:0]	bist_cmp_data;
output	[7:0]	bist_cmp_data_rep0;

input		tlb_tte_ie_b;
output		tlb_tte_ie_b_rep00;
output		tlb_tte_ie_b_rep01;

input		stb_cam_hit;
output		stb_cam_hit_rep0;

input	[3:0]	tlb_cache_way_hit_b;
output	[3:0]	cache_way_hit_top_b;
output	[3:0]	cache_way_hit_bot_b;

input	[63:0]	exu_lsu_store_data_e;
output	[63:0]	exu_lsu_store_data_e_rep0;

input	[10:4]	exu_lsu_address_e;
output	[10:4]	exu_lsu_address_e_rep0;

// D$ bypass data
lsu_rep_dp_buff_macro__rep_1__width_64 fill_or_byp_data_rep0  (
	.din	(lmd_fill_or_byp_data_m[63:0]),
	.dout	(lmd_fill_or_byp_data_m_rep0[63:0])
);
lsu_rep_dp_buff_macro__rep_1__width_64 fill_or_byp_data_rep1  (
	.din	(lmd_fill_or_byp_data_m_rep0[63:0]),
	.dout	(lmd_fill_or_byp_data_m_rep1[63:0])
);

// STB RAM read data (flopped)
lsu_rep_dp_buff_macro__rep_1__stack_32c__width_32 i0_stb_ram_data_rep0   (
	.din	(stb_ram_data[63:32]),
	.dout	(stb_ram_data_rep0[63:32])
);
lsu_rep_dp_buff_macro__rep_1__stack_32c__width_32 i1_stb_ram_data_rep0   (
	.din	(stb_ram_data[31:0]),
	.dout	(stb_ram_data_rep0[31:0])
);

// STB CAM read data
lsu_rep_dp_buff_macro__rep_1__width_45 i_stb_cam_data_rep0  (
	.din	(stb_cam_data[44:0]),
	.dout	(stb_cam_data_rep0[44:0])
);

// Prealigned data from store buffer
lsu_rep_dp_buff_macro__rep_1__width_48 st_predata_b_rep0  (
	.din	(sbd_st_predata_b[47:0]),
	.dout	(sbd_st_predata_b_rep0[47:0])
);

// Aligned data from store buffer
lsu_rep_dp_buff_macro__rep_1__width_64 st_data2_b_rep0  (
	.din	(sbd_st_data2_b[63:0]),
	.dout	(sbd_st_data2_b_rep0[63:0])
);

// BIST compare data
lsu_rep_dp_buff_macro__rep_1__width_8 i_bist_cmp_data_rep0  (
	.din	(bist_cmp_data[7:0]),
	.dout	(bist_cmp_data_rep0[7:0])
);

// TTE.IE
lsu_rep_dp_buff_macro__rep_1__width_1 tte_ie_rep00  (	// to sbs
	.din	(tlb_tte_ie_b),
	.dout	(tlb_tte_ie_b_rep00)
);
lsu_rep_dp_buff_macro__rep_1__width_1 tte_ie_rep01  (	// to dcc
	.din	(tlb_tte_ie_b),
	.dout	(tlb_tte_ie_b_rep01)
);

// stb_cam_hit; very critical to dcc, buffer off load to lmc
lsu_rep_dp_buff_macro__rep_1__width_1 i_stb_cam_hit_rep0  (	// to dcc
	.din	(stb_cam_hit),
	.dout	(stb_cam_hit_rep0)
);

// one copy of cache_way_hit goes up, one goes down
lsu_rep_dp_buff_macro__rep_1__width_4 i_cache_way_hit_top  (	// to dac
	.din	(tlb_cache_way_hit_b[3:0]),
	.dout	(cache_way_hit_top_b[3:0])
);
lsu_rep_dp_buff_macro__rep_1__width_4 i_cache_way_hit_bot  (	// to dcc
	.din	(tlb_cache_way_hit_b[3:0]),
	.dout	(cache_way_hit_bot_b[3:0])
);

lsu_rep_dp_buff_macro__rep_1__width_64 store_data_rep0  (
	.din	(exu_lsu_store_data_e[63:0]),
	.dout	(exu_lsu_store_data_e_rep0[63:0])
);

lsu_rep_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_7 exu_address_rep0  (
	.din	(exu_lsu_address_e[10:4]),
	.dout	(exu_lsu_address_e_rep0[10:4])
);

endmodule


//
//   buff macro
//
//


module lsu_rep_dp_buff_macro__rep_1__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_rep_dp_buff_macro__rep_1__stack_32c__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module lsu_rep_dp_buff_macro__rep_1__width_45 (
  din, 
  dout);
  input [44:0] din;
  output [44:0] dout;


buff #(45)  d0_0 (
.in(din[44:0]),
.out(dout[44:0])
);


endmodule


//
//   buff macro
//
//


module lsu_rep_dp_buff_macro__rep_1__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


//
//   buff macro
//
//


module lsu_rep_dp_buff_macro__rep_1__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module lsu_rep_dp_buff_macro__rep_1__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module lsu_rep_dp_buff_macro__rep_1__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module lsu_rep_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_7 (
  din, 
  dout);
  input [6:0] din;
  output [6:0] dout;


buff #(7)  d0_0 (
.in(din[6:0]),
.out(dout[6:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_sbc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_sbc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  dec_st_inst_e, 
  dec_fpldst_inst_e, 
  dec_flush_lm, 
  dec_flush_lb, 
  dec_frf_r2_addr_e, 
  dcc_lendian_pre_m, 
  dcc_tte_vld_m, 
  dcc_ldst_sz_m, 
  dcc_tid_e, 
  dcc_blk_inst_m, 
  dcc_std_inst_m, 
  dcc_asi_load_m, 
  dcc_binit_st_b, 
  dcc_casa_inst_b, 
  dcc_exception_flush_b, 
  dcc_priv_b, 
  dcc_hpriv_b, 
  dcc_stb_diag_rd_m, 
  dcc_wr_error_inj_m, 
  dcc_sync_pipe_w, 
  lsu_va_b, 
  lsu_asi_error_inject_b31, 
  lsu_asi_error_inject_b17, 
  lsu_asi_error_inject_b19, 
  lsu_asi_error_inject, 
  lsu_lsu_pmen, 
  tlu_flush_lsu_b, 
  tlu_cerer_sbdpc, 
  tlu_cerer_sbdpu, 
  tlu_cerer_sbapp, 
  tlu_cerer_sbdiou, 
  sbs0_stb_wptr_m, 
  sbs1_stb_wptr_m, 
  sbs2_stb_wptr_m, 
  sbs3_stb_wptr_m, 
  sbs4_stb_wptr_m, 
  sbs5_stb_wptr_m, 
  sbs6_stb_wptr_m, 
  sbs7_stb_wptr_m, 
  sbs0_stb_rptr, 
  sbs1_stb_rptr, 
  sbs2_stb_rptr, 
  sbs3_stb_rptr, 
  sbs4_stb_rptr, 
  sbs5_stb_rptr, 
  sbs6_stb_rptr, 
  sbs7_stb_rptr, 
  sbs_pcx_rq_vld, 
  sbs_atm_rq_vld, 
  sbs_asi_rq_vld, 
  sbs0_state_vld, 
  sbs1_state_vld, 
  sbs2_state_vld, 
  sbs3_state_vld, 
  sbs4_state_vld, 
  sbs5_state_vld, 
  sbs6_state_vld, 
  sbs7_state_vld, 
  sbs0_state_ced, 
  sbs1_state_ced, 
  sbs2_state_ced, 
  sbs3_state_ced, 
  sbs4_state_ced, 
  sbs5_state_ced, 
  sbs6_state_ced, 
  sbs7_state_ced, 
  sbs0_st_type, 
  sbs1_st_type, 
  sbs2_st_type, 
  sbs3_st_type, 
  sbs4_st_type, 
  sbs5_st_type, 
  sbs6_st_type, 
  sbs7_st_type, 
  sbs_state_asi_rngf, 
  sbs_pcx_pst_ie_p4, 
  sbs_bst_req, 
  sbs_asi_indet_req, 
  sbs_asi_indet_retire, 
  sbs_rmo_st_p4, 
  sbs_blk_st_p4, 
  sbs_stb_empty, 
  stb_cam_hit, 
  stb_cam_mhit, 
  stb_ld_part_raw, 
  stb_cam_hit_ptr, 
  stb_cam_data, 
  stb_cam_addr_b39, 
  stb_cecc_err, 
  stb_uecc_err, 
  stb_ram_ctl, 
  stb_cam_perr, 
  lmd_asi_asi, 
  lmd_asi_type, 
  lmc_ld_inst_w, 
  lmc_asi_indet_retire, 
  pic_st_pcx_sel_p3, 
  pic_st_asi_sel_p3, 
  pic_asi_sel_p4, 
  tlb_pgnum_b39, 
  tlb_tte_ie_b, 
  tlb_cam_mhit, 
  fgu_fst_ecc_error_fx2, 
  sed_bist_cmp_0, 
  sed_bist_cmp_1, 
  sed_bist_cmp_2, 
  sed_bist_cmp_3, 
  lbist_run, 
  mbi_run, 
  mbi_addr, 
  mbi_wdata, 
  mbi_stb_cam_read_en, 
  mbi_stb_cam_write_en, 
  mbi_stb_ram_read_en, 
  mbi_stb_ram_write_en, 
  bist_srm_rd_1, 
  bist_scm_rd_1, 
  sbc_thread_b, 
  sbc_st_int_sel_m, 
  sbc_std_le_m, 
  sbc_st_le_if_ie_m, 
  sbc_st_le_not_ie_m, 
  sbc_st_sz_m, 
  sbc_inv_addr_prty, 
  sbc_inv_ecc, 
  sbc_stb_ctl_data, 
  sbc_twocycle_inst_w, 
  sbc_tte_vld_b, 
  sbc_cam_wvld_m, 
  sbc_cam_wptr_vld_m, 
  sbc_cam_rptr_vld, 
  sbc_cam_rwptr, 
  sbc_cam_line_en_m, 
  sbc_ram_wptr_vld_b, 
  sbc_ram_rptr_vld, 
  sbc_ram_wptr, 
  sbc_ram_rptr, 
  sbc_cam_tid, 
  sbc_diag_wptr_w3, 
  sbc_st_rq_p2, 
  sbc_st_atomic_p2, 
  sbc_pcx_rq_p3, 
  sbc_asi_rq_p3, 
  sbc_st_sel_p3, 
  sbc_bst_sel, 
  sbc_st_sel_tid_p4, 
  sbc_st_pcx_nc, 
  sbc_pcx_bmask, 
  sbc_pcx_addr, 
  sbc_pcx_rmo_st, 
  sbc_pcx_blk_st, 
  sbc_st_asi_fs, 
  sbc_st_addr_new, 
  sbc_spd_clken, 
  sbc_ramout_clken, 
  sbc_tidb_eq_tidw, 
  sbc_tid_m, 
  sbc_st_atom_p3, 
  sbc_load_bst_addr, 
  sbc_bst_in_prog_m, 
  sbc_bst_in_prog_b, 
  sbc_bst_offset, 
  sbc_rmo_st_b, 
  sbc_rawp_rst, 
  sbc_fgu_ecc_b, 
  sbc_bst_rd_err, 
  sbc_pid_kill_store_p4_, 
  sbc_pic_kill_store_p4_, 
  sbc_sbs_kill_store_p4_, 
  sbc_force_inv, 
  sbc_st_type_p4, 
  sbc_blk_inst_b, 
  sbc_indet_block_p3, 
  lsu_block_store_stall, 
  lsu_block_store_rd, 
  lsu_block_store_tid, 
  lsu_block_store_alloc, 
  lsu_block_store_b, 
  lsu_block_store_m, 
  lsu_sbdpc_err_g, 
  lsu_sbdpu_err_g, 
  lsu_sbapp_err_g, 
  lsu_sbdiou_err_g, 
  lsu_stberr_index_g, 
  lsu_stberr_priv_g, 
  lsu_stb_flush_g, 
  lsu_frf_read_pending, 
  sbc_mbi_run, 
  lsu_mbi_stb_cam_fail, 
  lsu_mbi_stb_ram_fail, 
  lsu_mbi_scm_hit, 
  lsu_mbi_scm_mhit, 
  lsu_mbi_scm_hit_ptr, 
  lsu_mbi_scm_praw);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire stb_clken;
wire stb_cam_wptr_vld_m;
wire stb_cam_wptr_vld_b;
wire stb_cam_wptr_vld_w;
wire st_rq_p1;
wire st_rq_p2;
wire st_rq_p3;
wire st_rq_p4;
wire l1clk_pm1;
wire l1clk;
wire dff_flush_b_scanin;
wire dff_flush_b_scanout;
wire local_flush_b;
wire flush_b;
wire pipe_flush_b;
wire dff_flush_w_scanin;
wire dff_flush_w_scanout;
wire flush_w;
wire dff_inst_m_scanin;
wire dff_inst_m_scanout;
wire [4:3] bst_addr_m;
wire st_inst_vld_m;
wire dff_ldst_fp_m_scanin;
wire dff_ldst_fp_m_scanout;
wire ldst_fp_m;
wire bst_in_prog_m;
wire [1:0] st_sz_m;
wire std_inst_b;
wire [1:0] st_sz_b;
wire dff_ldst_sz_b_scanin;
wire dff_ldst_sz_b_scanout;
wire tidm_eq_tidb;
wire [2:0] tid_m;
wire [2:0] tid_b;
wire dff_st_w_scanin;
wire dff_st_w_scanout;
wire casa_inst_w;
wire st_lendian_b;
wire lendian_pre_b;
wire st_pre_le_m;
wire block_store_lendian;
wire std_le_m;
wire st_le_if_ie_m;
wire st_le_not_ie_m;
wire dff_st_le_b_scanin;
wire dff_st_le_b_scanout;
wire stb_cam_hit_b;
wire stb_cam_mhit_b;
wire stb_ld_part_raw_b;
wire [2:0] stb_cam_hit_ptr_b;
wire dff_cam_hit_scanin;
wire dff_cam_hit_scanout;
wire [2:0] tid_w;
wire stb_cam_hit_w;
wire stb_cam_mhit_w;
wire stb_ld_part_raw_w;
wire [2:0] stb_cam_hit_ptr_w;
wire full_raw_w;
wire io_or_asi_load_w;
wire [7:0] thread_w;
wire [7:0] thread_m;
wire mbi_run_local;
wire dff_ram_wptr_vld_b_scanin;
wire dff_ram_wptr_vld_b_scanout;
wire stb_ram_wptr_vld_b;
wire std_inst_w;
wire dff_stb_wptr_vld_w_scanin;
wire dff_stb_wptr_vld_w_scanout;
wire unflushed_store_w;
wire [2:0] tid_e;
wire bst_in_prog_e;
wire [2:0] bst_tid;
wire dff_tid_m_scanin;
wire dff_tid_m_scanout;
wire dff_thread_b_scanin;
wire dff_thread_b_scanout;
wire [7:0] thread_b;
wire [2:0] stb_wptr;
wire [2:0] cam_wptr_m;
wire st_pcx_rq_p2;
wire st_asi_rq_p2;
wire any_bst_req;
wire stb_diag_rd_w;
wire [5:3] va_w;
wire [2:0] st_rd_tid;
wire [2:0] stb_rptr_pcx;
wire dff_cam_wptr_scanin;
wire dff_cam_wptr_scanout;
wire [2:0] cam_wptr_b;
wire [2:0] cam_wptr_w;
wire [2:0] cam_wptr_w2;
wire [2:0] cam_wptr_w3;
wire dff_ram_rptr_scanin;
wire dff_ram_rptr_scanout;
wire [2:0] ram_rptr_d1;
wire stb_diag_rd_b_in;
wire ram_rptr_vld_2;
wire [2:0] ram_rptr_d2;
wire stb_diag_rd_b;
wire [7:0] st_rd_thread;
wire [7:0] asi_rq_vld;
wire asi_indet_block;
wire asi_indet_sel_qual_p2;
wire asi_indet_sel_p3;
wire asi_rq_blocked_p1;
wire [7:0] pcx_rq_vld;
wire [7:0] st_rq_vld_p1;
wire [7:0] st_rq_sel_p2;
wire [7:0] st_sel_p3;
wire [7:0] st_rq_asi_p1;
wire dff_st_rq_p2_scanin;
wire dff_st_rq_p2_scanout;
wire [7:0] st_rq_vld_p2;
wire [7:0] st_rq_asi_p2;
wire asi_rq_blocked_p2;
wire stb_hazard_p2;
wire st_pcx_rq_p3;
wire st_asi_rq_p3;
wire st_lru8_scanin;
wire st_lru8_scanout;
wire [7:0] st_lru_update_p3;
wire [7:0] st_rq_sel_unqual_p2;
wire st_asi_unqual_p2;
wire [2:0] st_tid_p2;
wire asi_indet_sel_p2;
wire dff_indet_temp_scanin;
wire dff_indet_temp_scanout;
wire asi_rq_blocked_p3;
wire indet_block_req_p2;
wire indet_block_req_p3;
wire [7:0] bst_sel;
wire dff_st_sel_p3_scanin;
wire dff_st_sel_p3_scanout;
wire [7:0] st_rq_sel_p3;
wire [7:0] st_atom_p3;
wire st_asi_fs_p3;
wire asi_indet_in;
wire dff_asi_indet_scanin;
wire dff_asi_indet_scanout;
wire dff_st_sel_p4_scanin;
wire dff_st_sel_p4_scanout;
wire [7:0] st_sel_p4;
wire st_asi_sel_p4;
wire st_pcx_sel_p4;
wire [2:0] st_sel_tid_p4;
wire bst_p2;
wire pst_ie_p4;
wire [7:0] bmask_ie;
wire [1:0] st_type_enc;
wire dff_cerer_scanin;
wire dff_cerer_scanout;
wire cerer_sbdpc;
wire cerer_sbdpu;
wire cerer_sbapp;
wire cerer_sbdiou;
wire sbdpc_err;
wire st_err_flush;
wire sbdpu_err;
wire sbapp_err;
wire sbdiou_err;
wire kill_store_p4_;
wire [1:0] stb_priv;
wire dff_stb_err_scanin;
wire dff_stb_err_scanout;
wire [7:0] fatal_err_cond_in;
wire [7:0] fatal_err_cond;
wire dff_fatal_err_scanin;
wire dff_fatal_err_scanout;
wire dff_bst_addr_pipe_scanin;
wire dff_bst_addr_pipe_scanout;
wire [4:3] bst_addr_b;
wire [4:3] bst_addr0_in;
wire [4:3] bst_addr0;
wire [4:3] bst_addr1_in;
wire [4:3] bst_addr1;
wire [4:3] bst_addr2_in;
wire [4:3] bst_addr2;
wire [4:3] bst_addr3_in;
wire [4:3] bst_addr3;
wire [4:3] bst_addr4_in;
wire [4:3] bst_addr4;
wire [4:3] bst_addr5_in;
wire [4:3] bst_addr5;
wire [4:3] bst_addr6_in;
wire [4:3] bst_addr6;
wire [4:3] bst_addr7_in;
wire [4:3] bst_addr7;
wire dff_bst_addr_scanin;
wire dff_bst_addr_scanout;
wire [7:0] bst_lendian_in;
wire [7:0] bst_lendian;
wire dff_bst_lendian_scanin;
wire dff_bst_lendian_scanout;
wire bst_busy_rst;
wire [2:0] bst_count;
wire bst_busy_in;
wire bst_busy;
wire dff_bst_busy_scanin;
wire dff_bst_busy_scanout;
wire bst_busy_out;
wire bst_lru8_scanin;
wire bst_lru8_scanout;
wire [7:0] bst_sel_unqual_p;
wire dff_bst_req_scanin;
wire dff_bst_req_scanout;
wire [7:0] bst_sel_unqual;
wire frf_read_pending;
wire [7:0] block_store_thread;
wire [2:0] bst_tid_in;
wire dff_bst_tid_scanin;
wire dff_bst_tid_scanout;
wire bst_in_prog_b;
wire rmo_st_w;
wire dff_rmo_st_w_scanin;
wire dff_rmo_st_w_scanout;
wire dff_bst_seq_scanin;
wire dff_bst_seq_scanout;
wire bst_p1;
wire bst_p2_in;
wire bst_p3;
wire [2:0] bst_count_in;
wire dff_bst_count_scanin;
wire dff_bst_count_scanout;
wire bst_err_p3;
wire dff_bst_rd_err_scanin;
wire dff_bst_rd_err_scanout;
wire bst_err_p4;
wire dff_std_seq_scanin;
wire dff_std_seq_scanout;
wire dff_praw_ctl_w_scanin;
wire dff_praw_ctl_w_scanout;
wire io_or_asi_load_b;
wire asi_load_b;
wire [2:0] last_stb_wptr_w;
wire [2:0] rawp_id_w;
wire [2:0] rawp_id0;
wire [2:0] rawp_id0_hold;
wire dff_rawp_id0_scanin;
wire dff_rawp_id0_scanout;
wire [7:0] dec_rawp_id0;
wire [2:0] rawp_id1;
wire [2:0] rawp_id1_hold;
wire dff_rawp_id1_scanin;
wire dff_rawp_id1_scanout;
wire [7:0] dec_rawp_id1;
wire [2:0] rawp_id2;
wire [2:0] rawp_id2_hold;
wire dff_rawp_id2_scanin;
wire dff_rawp_id2_scanout;
wire [7:0] dec_rawp_id2;
wire [2:0] rawp_id3;
wire [2:0] rawp_id3_hold;
wire dff_rawp_id3_scanin;
wire dff_rawp_id3_scanout;
wire [7:0] dec_rawp_id3;
wire [2:0] rawp_id4;
wire [2:0] rawp_id4_hold;
wire dff_rawp_id4_scanin;
wire dff_rawp_id4_scanout;
wire [7:0] dec_rawp_id4;
wire [2:0] rawp_id5;
wire [2:0] rawp_id5_hold;
wire dff_rawp_id5_scanin;
wire dff_rawp_id5_scanout;
wire [7:0] dec_rawp_id5;
wire [2:0] rawp_id6;
wire [2:0] rawp_id6_hold;
wire dff_rawp_id6_scanin;
wire dff_rawp_id6_scanout;
wire [7:0] dec_rawp_id6;
wire [2:0] rawp_id7;
wire [2:0] rawp_id7_hold;
wire dff_rawp_id7_scanin;
wire dff_rawp_id7_scanout;
wire [7:0] dec_rawp_id7;
wire [2:0] priv_enc;
wire inv_addr_prty_m;
wire inv_ecc_m;
wire dff_error_inj_scanin;
wire dff_error_inj_scanout;
wire inv_addr_prty_b;
wire inv_ecc_b;
wire dff_bist_in_scanin;
wire dff_bist_in_scanout;
wire bist_scm_cmp_en;
wire bist_srm_cmp_en;
wire stb_cam_fail;
wire stb_ram_fail;
wire dff_bist_fail_scanin;
wire dff_bist_fail_scanout;
wire frf_read_out;
wire frf_read_pending_in;
wire dff_frf_read_scanin;
wire dff_frf_read_scanout;
wire spares_scanin;
wire spares_scanout;
wire [2:0] unused;
wire indet_block_req_p4;


input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input		dec_st_inst_e;
input		dec_fpldst_inst_e;
input		dec_flush_lm;
input		dec_flush_lb;
input	[4:3]	dec_frf_r2_addr_e;

input		dcc_lendian_pre_m;
input		dcc_tte_vld_m;
input	[1:0]	dcc_ldst_sz_m;
input	[2:0]	dcc_tid_e;
input		dcc_blk_inst_m;
input		dcc_std_inst_m;
input		dcc_asi_load_m;
input		dcc_binit_st_b;
input		dcc_casa_inst_b;
input		dcc_exception_flush_b;
input		dcc_priv_b;
input		dcc_hpriv_b;
input		dcc_stb_diag_rd_m;
input		dcc_wr_error_inj_m;
input		dcc_sync_pipe_w;

input	[5:3]	lsu_va_b;
input		lsu_asi_error_inject_b31; 
input		lsu_asi_error_inject_b17; 
input		lsu_asi_error_inject_b19; 
input	[6:0]	lsu_asi_error_inject; 
input		lsu_lsu_pmen;

input		tlu_flush_lsu_b;
input		tlu_cerer_sbdpc;
input		tlu_cerer_sbdpu;
input		tlu_cerer_sbapp;
input		tlu_cerer_sbdiou;

input	[2:0]	sbs0_stb_wptr_m;
input	[2:0]	sbs1_stb_wptr_m;
input	[2:0]	sbs2_stb_wptr_m;
input	[2:0]	sbs3_stb_wptr_m;
input	[2:0]	sbs4_stb_wptr_m;
input	[2:0]	sbs5_stb_wptr_m;
input	[2:0]	sbs6_stb_wptr_m;
input	[2:0]	sbs7_stb_wptr_m;
input	[2:0]	sbs0_stb_rptr;
input	[2:0]	sbs1_stb_rptr;
input	[2:0]	sbs2_stb_rptr;
input	[2:0]	sbs3_stb_rptr;
input	[2:0]	sbs4_stb_rptr;
input	[2:0]	sbs5_stb_rptr;
input	[2:0]	sbs6_stb_rptr;
input	[2:0]	sbs7_stb_rptr;
input	[7:0]	sbs_pcx_rq_vld;		// Request for pcx - one per thread
input	[7:0]	sbs_atm_rq_vld;		// Atomic request (CAS)
input	[7:0]	sbs_asi_rq_vld;		// Request for asi - one per thread
input	[7:0]	sbs0_state_vld;
input	[7:0]	sbs1_state_vld;
input	[7:0]	sbs2_state_vld;
input	[7:0]	sbs3_state_vld;
input	[7:0]	sbs4_state_vld;
input	[7:0]	sbs5_state_vld;
input	[7:0]	sbs6_state_vld;
input	[7:0]	sbs7_state_vld;
input	[7:0]	sbs0_state_ced;
input	[7:0]	sbs1_state_ced;
input	[7:0]	sbs2_state_ced;
input	[7:0]	sbs3_state_ced;
input	[7:0]	sbs4_state_ced;
input	[7:0]	sbs5_state_ced;
input	[7:0]	sbs6_state_ced;
input	[7:0]	sbs7_state_ced;
input	[1:0]	sbs0_st_type;
input	[1:0]	sbs1_st_type;
input	[1:0]	sbs2_st_type;
input	[1:0]	sbs3_st_type;
input	[1:0]	sbs4_st_type;
input	[1:0]	sbs5_st_type;
input	[1:0]	sbs6_st_type;
input	[1:0]	sbs7_st_type;
input	[7:0]	sbs_state_asi_rngf;
input	[7:0]	sbs_pcx_pst_ie_p4;
input	[7:0]	sbs_bst_req;
input	[7:0]	sbs_asi_indet_req;
input	[7:0]	sbs_asi_indet_retire;
input	[7:0]	sbs_rmo_st_p4;
input	[7:0]	sbs_blk_st_p4;
input	[7:0]	sbs_stb_empty;

input		stb_cam_hit;
input		stb_cam_mhit;
input		stb_ld_part_raw;
input	[2:0]	stb_cam_hit_ptr;
input	[7:0]	stb_cam_data;		// Byte mask (also has ASI value for internal ASI stores)
input		stb_cam_addr_b39;
input		stb_cecc_err;
input		stb_uecc_err;
input	[2:0]	stb_ram_ctl;

input		stb_cam_perr;		// parity error occured on CAM read

input	[7:0]	lmd_asi_asi;
input	[1:0]	lmd_asi_type;

input		lmc_ld_inst_w;		// Unflushed load in W
input		lmc_asi_indet_retire;

input		pic_st_pcx_sel_p3;	// STB gets access to pcx
input		pic_st_asi_sel_p3;		// STB gets access to asi
input		pic_asi_sel_p4;

input		tlb_pgnum_b39;
input		tlb_tte_ie_b;
input		tlb_cam_mhit;

input		fgu_fst_ecc_error_fx2;

input		sed_bist_cmp_0;
input		sed_bist_cmp_1;
input		sed_bist_cmp_2;
input		sed_bist_cmp_3;

input		lbist_run;
input		mbi_run;
input	[5:0]	mbi_addr;
input	[2:0]	mbi_wdata;
input		mbi_stb_cam_read_en;
input		mbi_stb_cam_write_en;
input		mbi_stb_ram_read_en;
input		mbi_stb_ram_write_en;
output		bist_srm_rd_1;
output		bist_scm_rd_1;

output	[7:0]	sbc_thread_b;
output		sbc_st_int_sel_m;
output		sbc_std_le_m;
output		sbc_st_le_if_ie_m;
output		sbc_st_le_not_ie_m;
output	[1:0]	sbc_st_sz_m;
output		sbc_inv_addr_prty;
output	[6:0]	sbc_inv_ecc;
output	[2:0]	sbc_stb_ctl_data;
output		sbc_twocycle_inst_w;
output		sbc_tte_vld_b;		// tlb_miss not accounted for

output	[7:0]	sbc_cam_wvld_m;
output		sbc_cam_wptr_vld_m;	// enable stb_cam write
output		sbc_cam_rptr_vld;
output	[5:0]	sbc_cam_rwptr;		// stb_cam write pointer
output	[7:0]	sbc_cam_line_en_m;
output		sbc_ram_wptr_vld_b;	// enable stb_ram write
output		sbc_ram_rptr_vld;
output	[5:0]	sbc_ram_wptr;		// stb_ram write pointer
output	[5:0]	sbc_ram_rptr;		// stb_ram read pointer
output	[2:0]	sbc_cam_tid;		// stb_cam lookup tid
output	[2:0]	sbc_diag_wptr_w3;

output		sbc_st_rq_p2;
output		sbc_st_atomic_p2;
output		sbc_pcx_rq_p3;		// STB wants access to the pcx
output		sbc_asi_rq_p3;		// STB wants access to the asi
output	[7:0]	sbc_st_sel_p3;		// Selected thread in P3 (not qual'ed with store select)
output	[7:0]	sbc_bst_sel;
output	[2:0]	sbc_st_sel_tid_p4;		
output		sbc_st_pcx_nc;		
output	[7:0]	sbc_pcx_bmask;		// Byte mask for pcx requests
output	[2:0]	sbc_pcx_addr;		// Byte mask for pcx requests
output		sbc_pcx_rmo_st;		// Store in P4 is RMO
output		sbc_pcx_blk_st;		// Store in P4 is block store
output		sbc_st_asi_fs;
output	[7:0]	sbc_st_addr_new;
output		sbc_spd_clken;
output		sbc_ramout_clken;
output		sbc_tidb_eq_tidw;
output	[2:0]	sbc_tid_m;
output	[7:0]	sbc_st_atom_p3;
output		sbc_load_bst_addr;	// Enables the bst addr register in sbd
output		sbc_bst_in_prog_m;
output		sbc_bst_in_prog_b;
output	[2:0]	sbc_bst_offset;
output		sbc_rmo_st_b;
output	[7:0]	sbc_rawp_rst;
output		sbc_fgu_ecc_b;
output		sbc_bst_rd_err;
output		sbc_pid_kill_store_p4_;
output		sbc_pic_kill_store_p4_;
output		sbc_sbs_kill_store_p4_;
output		sbc_force_inv;
output	[2:0]	sbc_st_type_p4;
output		sbc_blk_inst_b;
output		sbc_indet_block_p3;

output		lsu_block_store_stall;
output	[4:3]	lsu_block_store_rd;
output	[2:0]	lsu_block_store_tid;
output	[7:0]	lsu_block_store_alloc;
output	[7:0]	lsu_block_store_b;
output		lsu_block_store_m;

output		lsu_sbdpc_err_g;
output		lsu_sbdpu_err_g;
output		lsu_sbapp_err_g;
output		lsu_sbdiou_err_g;
output	[2:0]	lsu_stberr_index_g;
output	[1:0]	lsu_stberr_priv_g;
output		lsu_stb_flush_g;

output		lsu_frf_read_pending;

output		sbc_mbi_run;
output		lsu_mbi_stb_cam_fail;
output		lsu_mbi_stb_ram_fail;
output		lsu_mbi_scm_hit;
output		lsu_mbi_scm_mhit;
output	[2:0]	lsu_mbi_scm_hit_ptr;
output		lsu_mbi_scm_praw;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

//////////////////////////////
// Clock header
//////////////////////////////

assign stb_clken = stb_cam_wptr_vld_m | stb_cam_wptr_vld_b | stb_cam_wptr_vld_w | 
                   st_rq_p1 | st_rq_p2 | st_rq_p3 | st_rq_p4 | mbi_run | ~lsu_lsu_pmen;

lsu_sbc_ctll1clkhdr_ctl_macro clkgen_stb (
        .l2clk  (l2clk                          ),
        .l1en   (stb_clken                      ),
        .l1clk  (l1clk_pm1                      ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

lsu_sbc_ctll1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk                          ),
        .l1en   (1'b1                           ),
        .l1clk  (l1clk                          ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

//////////////////////////////
// Flush logic
//////////////////////////////

lsu_sbc_ctlmsff_ctl_macro__width_1 dff_flush_b  (
	.scan_in(dff_flush_b_scanin),
	.scan_out(dff_flush_b_scanout),
	.din	(dec_flush_lm),
	.dout	(local_flush_b),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign flush_b = tlu_flush_lsu_b | dec_flush_lb | local_flush_b | dcc_exception_flush_b;
assign pipe_flush_b = dec_flush_lb | local_flush_b;

lsu_sbc_ctlmsff_ctl_macro__width_1 dff_flush_w  (
	.scan_in(dff_flush_w_scanin),
	.scan_out(dff_flush_w_scanout),
	.din	(flush_b),
	.dout	(flush_w),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_inst_m  (
	.scan_in(dff_inst_m_scanin),
	.scan_out(dff_inst_m_scanout),
	.din	({dec_frf_r2_addr_e[4:3],dec_st_inst_e}),
	.dout	({bst_addr_m[4:3],       st_inst_vld_m}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Store data source selects
////////////////////////////////////////////////////////////////////////////////

// M stage
// Select between integer store and fp stores.  FP stores can be 32b or
// 64b. 
lsu_sbc_ctlmsff_ctl_macro__width_1 dff_ldst_fp_m  (
	.scan_in(dff_ldst_fp_m_scanin),
	.scan_out(dff_ldst_fp_m_scanout),
	.din	(dec_fpldst_inst_e),
	.dout	(ldst_fp_m),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbc_st_int_sel_m = ~(ldst_fp_m | bst_in_prog_m);

////////////////////////////////////////////////////////////////////////////////
// Store data formatting
//
// Data must be swapped if little endian and then replicated for stores less
// than 8 bytes.
////////////////////////////////////////////////////////////////////////////////

// Force block stores to size=11.  CAS formats data over two cycles.
assign st_sz_m[1:0] = ((dcc_casa_inst_b | std_inst_b) ? st_sz_b[1:0] : dcc_ldst_sz_m[1:0]) |
                       {2{bst_in_prog_m}} ;

assign sbc_st_sz_m[1:0] = st_sz_m[1:0];

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_ldst_sz_b  (
	.scan_in(dff_ldst_sz_b_scanin),
	.scan_out(dff_ldst_sz_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(st_sz_m[1:0]),
	.dout	(st_sz_b[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign tidm_eq_tidb = (tid_m[2:0] == tid_b[2:0]) & stb_cam_wptr_vld_b;

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_st_w  (
	.scan_in(dff_st_w_scanin),
	.scan_out(dff_st_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({tidm_eq_tidb,     dcc_casa_inst_b}),
	.dout	({sbc_tidb_eq_tidw, casa_inst_w}),
  .siclk(siclk),
  .soclk(soclk)
);

// Endian swapping in sbd.  PE mux defaults to big endian.  Final qualification with TTE.IE will be
// done in sbd for timing reasons.
assign st_lendian_b = lendian_pre_b ^ (sbc_tte_vld_b & tlb_tte_ie_b);

assign st_pre_le_m = (dcc_casa_inst_b & st_lendian_b) |
                     (bst_in_prog_m & block_store_lendian) |
                     (st_inst_vld_m & dcc_lendian_pre_m);

assign std_le_m = std_inst_b & st_lendian_b;
assign st_le_if_ie_m =  (dcc_tte_vld_m & ~st_pre_le_m) | (~dcc_tte_vld_m & st_pre_le_m);
assign st_le_not_ie_m = (dcc_tte_vld_m &  st_pre_le_m) | (~dcc_tte_vld_m & st_pre_le_m);

assign sbc_std_le_m = std_le_m;
assign sbc_st_le_if_ie_m = st_le_if_ie_m;
assign sbc_st_le_not_ie_m = st_le_not_ie_m;

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_st_le_b  (
	.scan_in(dff_st_le_b_scanin),
	.scan_out(dff_st_le_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dcc_tte_vld_m,dcc_lendian_pre_m}),
	.dout	({sbc_tte_vld_b,    lendian_pre_b}),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// STB array controls
////////////////////////////////////////////////////////////////////////////////

assign stb_cam_hit_b          = stb_cam_hit     & ~lbist_run;
assign stb_cam_mhit_b         = stb_cam_mhit    & ~lbist_run;
assign stb_ld_part_raw_b      = stb_ld_part_raw & ~lbist_run;
assign stb_cam_hit_ptr_b[2:0] = stb_cam_hit_ptr[2:0] & {3{~lbist_run}};

lsu_sbc_ctlmsff_ctl_macro__width_9 dff_cam_hit  (
	.scan_in(dff_cam_hit_scanin),
	.scan_out(dff_cam_hit_scanout),
	.din	({tid_b[2:0],stb_cam_hit_b,stb_cam_mhit_b,stb_ld_part_raw_b,stb_cam_hit_ptr_b[2:0]}),
	.dout	({tid_w[2:0],stb_cam_hit_w,stb_cam_mhit_w,stb_ld_part_raw_w,stb_cam_hit_ptr_w[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_mbi_scm_hit     = stb_cam_hit_w;
assign lsu_mbi_scm_mhit    = stb_cam_mhit_w;
assign lsu_mbi_scm_hit_ptr = stb_cam_hit_ptr_w[2:0];
assign lsu_mbi_scm_praw    = stb_ld_part_raw_w;

// stb ram is read on a full RAW 
// Note: There are cases (LDD/QUAD come to mind) where full_raw_w evaulates true but a bypass will
// not occur.  The full qualification is done in lsu_lmc_ctl.  In those cases, the stb will get read
// but the data will not be used.
assign full_raw_w = stb_cam_hit_w & ~(stb_cam_mhit_w | stb_ld_part_raw_w | io_or_asi_load_w | flush_w);

assign thread_w[0] = ~tid_w[2] & ~tid_w[1] & ~tid_w[0];
assign thread_w[1] = ~tid_w[2] & ~tid_w[1] &  tid_w[0];
assign thread_w[2] = ~tid_w[2] &  tid_w[1] & ~tid_w[0];
assign thread_w[3] = ~tid_w[2] &  tid_w[1] &  tid_w[0];
assign thread_w[4] =  tid_w[2] & ~tid_w[1] & ~tid_w[0];
assign thread_w[5] =  tid_w[2] & ~tid_w[1] &  tid_w[0];
assign thread_w[6] =  tid_w[2] &  tid_w[1] & ~tid_w[0];
assign thread_w[7] =  tid_w[2] &  tid_w[1] &  tid_w[0];

// Valid signals from each threads state determine which cam entries are valid.
assign sbc_cam_line_en_m[7:0] = ({8{thread_m[0]}} & sbs0_state_vld[7:0] |
                                 {8{thread_m[1]}} & sbs1_state_vld[7:0] |
                                 {8{thread_m[2]}} & sbs2_state_vld[7:0] |
                                 {8{thread_m[3]}} & sbs3_state_vld[7:0] |
                                 {8{thread_m[4]}} & sbs4_state_vld[7:0] |
                                 {8{thread_m[5]}} & sbs5_state_vld[7:0] |
                                 {8{thread_m[6]}} & sbs6_state_vld[7:0] |
                                 {8{thread_m[7]}} & sbs7_state_vld[7:0] ) |
                                 {8{mbi_run_local}} ;


// Write pointer generation

assign stb_cam_wptr_vld_m = (st_inst_vld_m | bst_in_prog_m) & ~mbi_run_local;	// does not include BIST
assign sbc_cam_wptr_vld_m = mbi_run_local ? mbi_stb_cam_write_en : 
                                            stb_cam_wptr_vld_m & ~(dcc_sync_pipe_w & (tid_m[2:0] == tid_w[2:0]));

lsu_sbc_ctlmsff_ctl_macro__width_1 dff_ram_wptr_vld_b  (
	.scan_in(dff_ram_wptr_vld_b_scanin),
	.scan_out(dff_ram_wptr_vld_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_cam_wptr_vld_m),
	.dout	(stb_cam_wptr_vld_b),
  .siclk(siclk),
  .soclk(soclk)
);

assign stb_ram_wptr_vld_b = stb_cam_wptr_vld_b & ~(dcc_sync_pipe_w & (tid_b[2:0] == tid_w[2:0]));

assign sbc_ram_wptr_vld_b = mbi_run_local ? mbi_stb_ram_write_en : (stb_ram_wptr_vld_b | std_inst_w | casa_inst_w);

lsu_sbc_ctlmsff_ctl_macro__width_1 dff_stb_wptr_vld_w  (
	.scan_in(dff_stb_wptr_vld_w_scanin),
	.scan_out(dff_stb_wptr_vld_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_cam_wptr_vld_b),
	.dout	(stb_cam_wptr_vld_w),
  .siclk(siclk),
  .soclk(soclk)
);

assign unflushed_store_w = stb_cam_wptr_vld_w & ~flush_w;

assign tid_e[2:0] = bst_in_prog_e ? bst_tid[2:0] : dcc_tid_e[2:0];

lsu_sbc_ctlmsff_ctl_macro__width_6 dff_tid_m  (
	.scan_in(dff_tid_m_scanin),
	.scan_out(dff_tid_m_scanout),
	.din	({tid_e[2:0],tid_m[2:0]}),
	.dout	({tid_m[2:0],tid_b[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbc_tid_m[2:0] = tid_m[2:0];

assign thread_m[0] = ~tid_m[2] & ~tid_m[1] & ~tid_m[0];
assign thread_m[1] = ~tid_m[2] & ~tid_m[1] &  tid_m[0];
assign thread_m[2] = ~tid_m[2] &  tid_m[1] & ~tid_m[0];
assign thread_m[3] = ~tid_m[2] &  tid_m[1] &  tid_m[0];
assign thread_m[4] =  tid_m[2] & ~tid_m[1] & ~tid_m[0];
assign thread_m[5] =  tid_m[2] & ~tid_m[1] &  tid_m[0];
assign thread_m[6] =  tid_m[2] &  tid_m[1] & ~tid_m[0];
assign thread_m[7] =  tid_m[2] &  tid_m[1] &  tid_m[0];

assign sbc_cam_wvld_m[0] = stb_cam_wptr_vld_m & thread_m[0];
assign sbc_cam_wvld_m[1] = stb_cam_wptr_vld_m & thread_m[1];
assign sbc_cam_wvld_m[2] = stb_cam_wptr_vld_m & thread_m[2];
assign sbc_cam_wvld_m[3] = stb_cam_wptr_vld_m & thread_m[3];
assign sbc_cam_wvld_m[4] = stb_cam_wptr_vld_m & thread_m[4];
assign sbc_cam_wvld_m[5] = stb_cam_wptr_vld_m & thread_m[5];
assign sbc_cam_wvld_m[6] = stb_cam_wptr_vld_m & thread_m[6];
assign sbc_cam_wvld_m[7] = stb_cam_wptr_vld_m & thread_m[7];

lsu_sbc_ctlmsff_ctl_macro__width_8 dff_thread_b  (
	.scan_in(dff_thread_b_scanin),
	.scan_out(dff_thread_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(thread_m[7:0]),
	.dout	(thread_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbc_thread_b[7:0] = thread_b[7:0];

assign stb_wptr[2:0] = {3{thread_m[0]}} & sbs0_stb_wptr_m[2:0] |
                       {3{thread_m[1]}} & sbs1_stb_wptr_m[2:0] |
                       {3{thread_m[2]}} & sbs2_stb_wptr_m[2:0] |
                       {3{thread_m[3]}} & sbs3_stb_wptr_m[2:0] |
                       {3{thread_m[4]}} & sbs4_stb_wptr_m[2:0] |
                       {3{thread_m[5]}} & sbs5_stb_wptr_m[2:0] |
                       {3{thread_m[6]}} & sbs6_stb_wptr_m[2:0] |
                       {3{thread_m[7]}} & sbs7_stb_wptr_m[2:0];

assign cam_wptr_m[2:0] = stb_wptr[2:0];

// CAM is 1rw.  Writes always have priority, so anything that generated a read must be deferred.
// 0in bits_on -var {sbc_cam_rptr_vld,sbc_cam_wptr_vld_m} -max 1 -message "stb_cam read/write contention"
// 0in bits_on -var {(st_pcx_rq_p2 | st_asi_rq_p2),any_bst_req,stb_diag_rd_w} -max 1

assign sbc_cam_rptr_vld =  mbi_run_local ? mbi_stb_cam_read_en : (st_pcx_rq_p2 | st_asi_rq_p2 | any_bst_req | stb_diag_rd_w);

// STB CAM is 1rw, so read and write pointers must be muxed.
// 0in bits_on -var {stb_cam_wptr_vld_m,stb_diag_rd_w,mbi_run_local} -max 1 -message "multiple stb_cam address selects"
assign sbc_cam_rwptr[5:0] = mbi_run_local ? mbi_addr[5:0] : 
       (({6{stb_cam_wptr_vld_m}}                    & {tid_m[2:0],cam_wptr_m[2:0]}) |		// write
        ({6{stb_diag_rd_w}}                         & {tid_w[2:0],va_w[5:3]}) |			// diag read
        ({6{~(stb_cam_wptr_vld_m | stb_diag_rd_w)}} & {st_rd_tid[2:0],stb_rptr_pcx[2:0]}));	// read for pcx/asi/bst
         
assign sbc_cam_tid[2:0] = mbi_run_local ? mbi_addr[5:3] : tid_m[2:0];

lsu_sbc_ctlmsff_ctl_macro__width_12 dff_cam_wptr  (
	.scan_in(dff_cam_wptr_scanin),
	.scan_out(dff_cam_wptr_scanout),
	.din	({cam_wptr_m[2:0],cam_wptr_b[2:0],cam_wptr_w[2:0], cam_wptr_w2[2:0]}),
	.dout	({cam_wptr_b[2:0],cam_wptr_w[2:0],cam_wptr_w2[2:0],cam_wptr_w3[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign sbc_diag_wptr_w3[2:0] = cam_wptr_w3[2:0];

assign sbc_ram_wptr[5:0] = mbi_run_local ? mbi_addr[5:0] :
                          ((std_inst_w | casa_inst_w) ? {tid_w[2:0],cam_wptr_w[2:0]} : {tid_b[2:0],cam_wptr_b[2:0]});

// Read pointer generation

// rptr_vld and rptr_pcx can be generated from an earlier pcx_rq signal.  The
// advantage of the later signal is that the array will only be read when
// absolutely necessary.
// 0in bits_on -var {(st_pcx_rq_p2 | st_asi_rq_p2),full_raw_w,stb_diag_rd_w} -max 1

assign sbc_ram_rptr_vld = mbi_run_local ? mbi_stb_ram_read_en :
                         ((st_pcx_rq_p2 | st_asi_rq_p2) |		// read for pcx/asi
                          full_raw_w |					// read for RAW bypass
                          any_bst_req |					// read for block store initiate
                          stb_diag_rd_w); 				// diag read

assign sbc_ram_rptr[5:0] = mbi_run_local ? mbi_addr[5:0] : 
                           (full_raw_w ? {tid_w[2:0],stb_cam_hit_ptr_w[2:0]} :			// read for RAW bypass
                            stb_diag_rd_w  ? {tid_w[2:0],va_w[5:3]} :				// diag read
                                                {st_rd_tid[2:0],stb_rptr_pcx[2:0]});		// read for pcx

lsu_sbc_ctlmsff_ctl_macro__width_12 dff_ram_rptr  (
	.scan_in(dff_ram_rptr_scanin),
	.scan_out(dff_ram_rptr_scanout),
	.din	({sbc_ram_rptr_vld,sbc_ram_rptr[2:0],ram_rptr_d1[2:0],lsu_va_b[5:3],
		  dcc_stb_diag_rd_m,stb_diag_rd_b_in}),
	.dout	({ram_rptr_vld_2,  ram_rptr_d1[2:0], ram_rptr_d2[2:0],va_w[5:3],
		  stb_diag_rd_b,    stb_diag_rd_w}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign stb_diag_rd_b_in = stb_diag_rd_b & ~mbi_run_local;

assign sbc_ramout_clken = ram_rptr_vld_2 | ~lsu_lsu_pmen;

assign stb_rptr_pcx[2:0] = {3{st_rd_thread[0]}} & sbs0_stb_rptr[2:0] |
                           {3{st_rd_thread[1]}} & sbs1_stb_rptr[2:0] |
                           {3{st_rd_thread[2]}} & sbs2_stb_rptr[2:0] |
                           {3{st_rd_thread[3]}} & sbs3_stb_rptr[2:0] |
                           {3{st_rd_thread[4]}} & sbs4_stb_rptr[2:0] |
                           {3{st_rd_thread[5]}} & sbs5_stb_rptr[2:0] |
                           {3{st_rd_thread[6]}} & sbs6_stb_rptr[2:0] |
                           {3{st_rd_thread[7]}} & sbs7_stb_rptr[2:0];

// Update last stored address for pipelining comparisons
assign sbc_st_addr_new[0] = unflushed_store_w & thread_w[0];
assign sbc_st_addr_new[1] = unflushed_store_w & thread_w[1];
assign sbc_st_addr_new[2] = unflushed_store_w & thread_w[2];
assign sbc_st_addr_new[3] = unflushed_store_w & thread_w[3];
assign sbc_st_addr_new[4] = unflushed_store_w & thread_w[4];
assign sbc_st_addr_new[5] = unflushed_store_w & thread_w[5];
assign sbc_st_addr_new[6] = unflushed_store_w & thread_w[6];
assign sbc_st_addr_new[7] = unflushed_store_w & thread_w[7];

// Clock enables for pipe address flops

assign sbc_spd_clken = stb_cam_wptr_vld_m | stb_cam_wptr_vld_b | mbi_run_local | ~lsu_lsu_pmen;

////////////////////////////////////////////////////////////////////////////////
// PCX/ASI Arbitration
////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////
// P1 - receive requests from sbs
/////////////////////////////////////////////////////

// Turn off indeterminate ASI requests if they're blocked
// If an asi was selected in P2, clear the request since ASI can only issue
// every other cycle.
assign asi_rq_vld[7:0] = sbs_asi_rq_vld[7:0] & 
     ~(sbs_asi_indet_req[7:0] & {8{asi_indet_block | asi_indet_sel_qual_p2 | (asi_indet_sel_p3 & pic_st_asi_sel_p3)}});

assign asi_rq_blocked_p1 = |(sbs_asi_rq_vld[7:0] & sbs_asi_indet_req[7:0]) &
                            (asi_indet_block | asi_indet_sel_qual_p2 | (asi_indet_sel_p3 & pic_st_asi_sel_p3));

// Combine all requests for power management
assign st_rq_p1 = (|(sbs_pcx_rq_vld[7:0])) | (|(sbs_asi_rq_vld[7:0]));

// Turn off pcx requests for a thread during it's block store transfer.  Need to hold
// off until the end in case an ECC error occurs in the FGU.
assign pcx_rq_vld[7:0] = sbs_pcx_rq_vld[7:0] & ~lsu_block_store_b[7:0];

assign st_rq_vld_p1[7:0] = (pcx_rq_vld[7:0] | asi_rq_vld[7:0]) & ~st_rq_sel_p2[7:0] & ~st_sel_p3[7:0];
assign st_rq_asi_p1[7:0] = asi_rq_vld[7:0] & ~st_rq_sel_p2[7:0] & ~st_sel_p3[7:0];

lsu_sbc_ctlmsff_ctl_macro__width_18 dff_st_rq_p2  (
	.scan_in(dff_st_rq_p2_scanin),
	.scan_out(dff_st_rq_p2_scanout),
	.l1clk	(l1clk_pm1),
	.din	({st_rq_p1,st_rq_vld_p1[7:0],st_rq_asi_p1[7:0],asi_rq_blocked_p1}),
	.dout	({st_rq_p2,st_rq_vld_p2[7:0],st_rq_asi_p2[7:0],asi_rq_blocked_p2}),
  .siclk(siclk),
  .soclk(soclk)
);

/////////////////////////////////////////////////////
// P2 - arbitrate among the threads
/////////////////////////////////////////////////////

// Stores cannot request under the following conditions
// 1 - when a load in W is reading the STB for RAW bypass
// 2 - when another thread is reading the STB to initiate a block store
// 3 - when a store in M will be writing the STB
// 4 - when a STD or CASA in W needs to write the STB 
// 5 - when a diagnostic STB read is in M or W
assign stb_hazard_p2 = full_raw_w | any_bst_req | stb_cam_wptr_vld_m | std_inst_w | 
                       casa_inst_w | stb_diag_rd_w | st_pcx_rq_p3 | st_asi_rq_p3;

// Pseudo-LRU picker to choose the oldest thread for issuing to pcx.
lsu_lru8_ctl st_lru8 (
	.scan_in(st_lru8_scanin),
	.scan_out(st_lru8_scanout),
	.l1clk	(l1clk_pm1),
	.request(st_rq_vld_p2[7:0]),
	.enable	(st_lru_update_p3[7:0]),
	.select	(st_rq_sel_unqual_p2[7:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

assign st_rq_sel_p2[7:0] = st_rq_sel_unqual_p2[7:0] & {8{~stb_hazard_p2}};

assign st_asi_unqual_p2 = |(st_rq_sel_unqual_p2[7:0] & st_rq_asi_p2[7:0]);
assign st_pcx_rq_p2 = ~st_asi_unqual_p2 & |(st_rq_vld_p2[7:0]) & ~stb_hazard_p2;
assign st_asi_rq_p2 =  st_asi_unqual_p2 & |(st_rq_vld_p2[7:0]) & ~stb_hazard_p2;

// 0in arbiter -req st_rq_vld_p2[7:0] -gnt st_rq_sel_unqual_p2[7:0] -known_grant 

// Encode tid for use in STB read pointer
assign st_tid_p2[2] = st_rq_sel_p2[4] | st_rq_sel_p2[5] | st_rq_sel_p2[6] | st_rq_sel_p2[7];
assign st_tid_p2[1] = st_rq_sel_p2[2] | st_rq_sel_p2[3] | st_rq_sel_p2[6] | st_rq_sel_p2[7];
assign st_tid_p2[0] = st_rq_sel_p2[1] | st_rq_sel_p2[3] | st_rq_sel_p2[5] | st_rq_sel_p2[7];

// CAS tracking
assign sbc_st_atomic_p2 = |(st_rq_sel_p2[7:0] & sbs_atm_rq_vld[7:0]);

// Indeterminate asi tracking
assign asi_indet_sel_p2 = |(sbs_asi_indet_req[7:0] & st_rq_sel_unqual_p2[7:0]);

assign asi_indet_sel_qual_p2 = asi_indet_sel_p2 & ~stb_hazard_p2;

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_indet_temp  (
	.scan_in(dff_indet_temp_scanin),
	.scan_out(dff_indet_temp_scanout),
	.l1clk	(l1clk_pm1),
	.din	({asi_indet_sel_qual_p2,asi_rq_blocked_p2}),
	.dout	({asi_indet_sel_p3,     asi_rq_blocked_p3}),
  .siclk(siclk),
  .soclk(soclk)
);

// To prevent indeterminates from getting locked out, block the next two cycles if an
// indeterminate gets picked, but not selected in p3.
assign indet_block_req_p2 = asi_indet_sel_p3 & ~pic_st_asi_sel_p3;
//assign sbc_indet_block_p3 = indet_block_req_p3 | indet_block_req_p4;
assign sbc_indet_block_p3 = indet_block_req_p3;
 
// Data for STB read pointers
assign st_rd_tid[2:0] = st_tid_p2[2:0] | ({3{any_bst_req}} & lsu_block_store_tid[2:0]);
assign st_rd_thread[7:0] = st_rq_sel_p2[7:0] | bst_sel[7:0];

assign sbc_st_rq_p2 = st_pcx_rq_p2 | st_asi_rq_p2;

lsu_sbc_ctlmsff_ctl_macro__width_11 dff_st_sel_p3  (
	.scan_in(dff_st_sel_p3_scanin),
	.scan_out(dff_st_sel_p3_scanout),
	.l1clk	(l1clk_pm1),
	.din	({st_rq_p2,st_rq_sel_p2[7:0],st_pcx_rq_p2,st_asi_rq_p2}),
	.dout	({st_rq_p3,st_rq_sel_p3[7:0],st_pcx_rq_p3,st_asi_rq_p3}),
  .siclk(siclk),
  .soclk(soclk)
);

assign st_atom_p3[7:0] = st_rq_sel_p3[7:0] & sbs_atm_rq_vld[7:0];

////////////////////////////////////
// P3 - pic selects load or store //
////////////////////////////////////

assign sbc_st_atom_p3[7:0] = st_atom_p3[7:0] & {8{pic_st_pcx_sel_p3}};

assign sbc_asi_rq_p3 = st_asi_rq_p3;
assign sbc_pcx_rq_p3 = st_pcx_rq_p3;

assign st_sel_p3[7:0] = st_rq_sel_p3[7:0] & {8{(pic_st_pcx_sel_p3 | pic_st_asi_sel_p3)}};
assign sbc_st_sel_p3[7:0] = st_rq_sel_p3[7:0];

assign st_lru_update_p3[7:0] = st_sel_p3[7:0] & {8{~asi_rq_blocked_p3}};

assign st_asi_fs_p3 = (st_sel_p3[0] & sbs_state_asi_rngf[0]) |
                      (st_sel_p3[1] & sbs_state_asi_rngf[1]) |
                      (st_sel_p3[2] & sbs_state_asi_rngf[2]) |
                      (st_sel_p3[3] & sbs_state_asi_rngf[3]) |
                      (st_sel_p3[4] & sbs_state_asi_rngf[4]) |
                      (st_sel_p3[5] & sbs_state_asi_rngf[5]) |
                      (st_sel_p3[6] & sbs_state_asi_rngf[6]) |
                      (st_sel_p3[7] & sbs_state_asi_rngf[7]);

// Must track indeterminate ASI stores.  Only one (across all threads) can
// be outstanding at any time.

assign asi_indet_in = (asi_indet_sel_p3 & pic_st_asi_sel_p3) | (asi_indet_block & ~|(sbs_asi_indet_retire[7:0]));

lsu_sbc_ctlmsff_ctl_macro__width_1 dff_asi_indet  (
	.scan_in(dff_asi_indet_scanin),
	.scan_out(dff_asi_indet_scanout),
	.din	(asi_indet_in),
	.dout	(asi_indet_block),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

/////////////////////////////////////
// P4 - data is valid from CAM/RAM //
/////////////////////////////////////

lsu_sbc_ctlmsff_ctl_macro__width_12 dff_st_sel_p4  (
	.scan_in(dff_st_sel_p4_scanin),
	.scan_out(dff_st_sel_p4_scanout),
	.l1clk	(l1clk_pm1),
	.din	({st_rq_p3,st_asi_fs_p3, st_sel_p3[7:0],pic_st_asi_sel_p3,pic_st_pcx_sel_p3}),
	.dout	({st_rq_p4,sbc_st_asi_fs,st_sel_p4[7:0],st_asi_sel_p4,    st_pcx_sel_p4}),
  .siclk(siclk),
  .soclk(soclk)
);

assign st_sel_tid_p4[2] = st_sel_p4[4] | st_sel_p4[5] | st_sel_p4[6] | st_sel_p4[7];
assign st_sel_tid_p4[1] = st_sel_p4[2] | st_sel_p4[3] | st_sel_p4[6] | st_sel_p4[7];
assign st_sel_tid_p4[0] = st_sel_p4[1] | st_sel_p4[3] | st_sel_p4[5] | st_sel_p4[7];

assign sbc_st_sel_tid_p4[2:0] = bst_p2 ? bst_tid[2:0] : st_sel_tid_p4[2:0];

// Partial store mask calculation
assign pst_ie_p4 = |(sbs_pcx_pst_ie_p4[7:0]);

assign bmask_ie[7:0] = {stb_cam_data[0],stb_cam_data[1],stb_cam_data[2],stb_cam_data[3],
                        stb_cam_data[4],stb_cam_data[5],stb_cam_data[6],stb_cam_data[7]};
assign sbc_pcx_bmask[7:0] = pst_ie_p4 ? bmask_ie[7:0] : stb_cam_data[7:0];

// Generate addr[2:0] based on byte mask.  It won't be correct for PST instructions, but
// the L2 shouldn't use the address bits for those anyway.
assign sbc_pcx_addr[2] = (!stb_cam_data[0]&stb_cam_data[2]) | (!stb_cam_data[1]&stb_cam_data[0]) |
                         (!stb_cam_data[2]&stb_cam_data[1]) | (!stb_cam_data[4]&stb_cam_data[3]);
assign sbc_pcx_addr[1] = (!stb_cam_data[5]&stb_cam_data[4]) | (!stb_cam_data[1]&stb_cam_data[0]) |
                         (!stb_cam_data[6]&stb_cam_data[5]) | (!stb_cam_data[2]&stb_cam_data[1]);
assign sbc_pcx_addr[0] = (!stb_cam_data[7]&stb_cam_data[6]) | (!stb_cam_data[5]&stb_cam_data[4]) |
                         (!stb_cam_data[3]&stb_cam_data[2]) | (!stb_cam_data[1]&stb_cam_data[0]);


assign sbc_pcx_rmo_st = |(sbs_rmo_st_p4[7:0]);
assign sbc_pcx_blk_st = |(sbs_blk_st_p4[7:0]);

// Store type muxing
assign st_type_enc[1:0] = ({2{st_sel_p4[0]}} & sbs0_st_type[1:0]) |
                          ({2{st_sel_p4[1]}} & sbs1_st_type[1:0]) |
                          ({2{st_sel_p4[2]}} & sbs2_st_type[1:0]) |
                          ({2{st_sel_p4[3]}} & sbs3_st_type[1:0]) |
                          ({2{st_sel_p4[4]}} & sbs4_st_type[1:0]) |
                          ({2{st_sel_p4[5]}} & sbs5_st_type[1:0]) |
                          ({2{st_sel_p4[6]}} & sbs6_st_type[1:0]) |
                          ({2{st_sel_p4[7]}} & sbs7_st_type[1:0]) ;

assign sbc_st_type_p4[2] = st_pcx_sel_p4 & st_type_enc[1];
assign sbc_st_type_p4[1] = st_pcx_sel_p4 ? st_type_enc[0] : st_type_enc[1];
assign sbc_st_type_p4[0] = st_pcx_sel_p4 ? (~st_type_enc[0] | st_type_enc[1]) : st_type_enc[0];

///////////////////////////////
// STB error detection
///////////////////////////////

lsu_sbc_ctlmsff_ctl_macro__width_4 dff_cerer  (
	.scan_in(dff_cerer_scanin),
	.scan_out(dff_cerer_scanout),
	.l1clk	(l1clk_pm1),
	.din	({tlu_cerer_sbdpc,tlu_cerer_sbdpu,tlu_cerer_sbapp,tlu_cerer_sbdiou}),
	.dout	({    cerer_sbdpc,    cerer_sbdpu,    cerer_sbapp,    cerer_sbdiou}),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbdpc_err  = cerer_sbdpc & stb_cecc_err & ~stb_uecc_err & (st_pcx_sel_p4 | st_asi_sel_p4) & ~st_err_flush;
assign sbdpu_err  = cerer_sbdpu & stb_uecc_err & st_pcx_sel_p4 & ~stb_cam_addr_b39 & ~st_err_flush;
assign sbapp_err  = cerer_sbapp & stb_cam_perr & (st_pcx_sel_p4 | st_asi_sel_p4 | bst_p2) & ~st_err_flush;
assign sbdiou_err = cerer_sbdiou & stb_uecc_err & ((st_pcx_sel_p4 & stb_cam_addr_b39) | st_asi_sel_p4) & ~st_err_flush;

// Check that errors are never signaled during normal testing


assign kill_store_p4_ = ~(sbapp_err | sbdiou_err | (st_asi_sel_p4 & sbdpu_err) | st_err_flush);
assign sbc_pid_kill_store_p4_ = kill_store_p4_;
assign sbc_pic_kill_store_p4_ = kill_store_p4_;
assign sbc_sbs_kill_store_p4_ = kill_store_p4_;

// On UE for store and CAS, assert the inv bit of the pcx packet so the L2 stores NotData
assign sbc_force_inv = sbdpu_err;

// Decode the priv encodings
assign stb_priv[1] = (stb_ram_ctl[1]&!stb_ram_ctl[0]) | (!stb_ram_ctl[1]&stb_ram_ctl[0]) | (stb_ram_ctl[2]);
assign stb_priv[0] = (stb_ram_ctl[2]&!stb_ram_ctl[0]) | (!stb_ram_ctl[2]&stb_ram_ctl[0]) | (stb_ram_ctl[1]);

lsu_sbc_ctlmsff_ctl_macro__width_10 dff_stb_err  (
	.scan_in(dff_stb_err_scanin),
	.scan_out(dff_stb_err_scanout),
	.din	({sbdpc_err,      sbdpu_err,      sbapp_err,      sbdiou_err      ,
		  ram_rptr_d2[2:0],       stb_priv[1:0], st_err_flush}),
	.dout	({lsu_sbdpc_err_g,lsu_sbdpu_err_g,lsu_sbapp_err_g,lsu_sbdiou_err_g,
		  lsu_stberr_index_g[2:0],lsu_stberr_priv_g[1:0],lsu_stb_flush_g}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// When a "fatal" error occurs (one which kills a store), all other stores in the buffer should
// also be killed.  Keep a flag that indicates the error condition and kill all stores as they
// try to issue.  Once the stb is empty, reset the flag.
assign fatal_err_cond_in[7:0] = (({8{~kill_store_p4_}} & st_sel_p4[7:0]) | fatal_err_cond[7:0]) & ~sbs_stb_empty[7:0];

lsu_sbc_ctlmsff_ctl_macro__width_8 dff_fatal_err  (
	.scan_in(dff_fatal_err_scanin),
	.scan_out(dff_fatal_err_scanout),
	.din	(fatal_err_cond_in[7:0]),
	.dout	(fatal_err_cond[7:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign st_err_flush = |(fatal_err_cond[7:0] & (st_sel_p4[7:0] | bst_sel[7:0]));

////////////////////////////////////////////////////////////////////////////////
// Block stores
////////////////////////////////////////////////////////////////////////////////

// Must hold onto Rd value for the bst to send back to decode.
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_bst_addr_pipe  (
	.scan_in(dff_bst_addr_pipe_scanin),
	.scan_out(dff_bst_addr_pipe_scanout),
	.l1clk	(l1clk_pm1),
	.din	({bst_addr_m[4:3],dcc_blk_inst_m}),
	.dout	({bst_addr_b[4:3],sbc_blk_inst_b}),
  .siclk(siclk),
  .soclk(soclk)
);

assign bst_addr0_in[4:3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[0] & ~pipe_flush_b) ? bst_addr_b[4:3] : bst_addr0[4:3];
assign bst_addr1_in[4:3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[1] & ~pipe_flush_b) ? bst_addr_b[4:3] : bst_addr1[4:3];
assign bst_addr2_in[4:3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[2] & ~pipe_flush_b) ? bst_addr_b[4:3] : bst_addr2[4:3];
assign bst_addr3_in[4:3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[3] & ~pipe_flush_b) ? bst_addr_b[4:3] : bst_addr3[4:3];
assign bst_addr4_in[4:3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[4] & ~pipe_flush_b) ? bst_addr_b[4:3] : bst_addr4[4:3];
assign bst_addr5_in[4:3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[5] & ~pipe_flush_b) ? bst_addr_b[4:3] : bst_addr5[4:3];
assign bst_addr6_in[4:3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[6] & ~pipe_flush_b) ? bst_addr_b[4:3] : bst_addr6[4:3];
assign bst_addr7_in[4:3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[7] & ~pipe_flush_b) ? bst_addr_b[4:3] : bst_addr7[4:3];

lsu_sbc_ctlmsff_ctl_macro__width_16 dff_bst_addr  (
	.scan_in(dff_bst_addr_scanin),
	.scan_out(dff_bst_addr_scanout),
	.l1clk	(l1clk_pm1),
	.din	({bst_addr7_in[4:3],bst_addr6_in[4:3],bst_addr5_in[4:3],bst_addr4_in[4:3],
		  bst_addr3_in[4:3],bst_addr2_in[4:3],bst_addr1_in[4:3],bst_addr0_in[4:3]}),
	.dout	({bst_addr7[4:3],bst_addr6[4:3],bst_addr5[4:3],bst_addr4[4:3],
		  bst_addr3[4:3],bst_addr2[4:3],bst_addr1[4:3],bst_addr0[4:3]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Have to store the endianess of the store
assign bst_lendian_in[0] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[0] & ~pipe_flush_b) ? st_lendian_b : bst_lendian[0];
assign bst_lendian_in[1] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[1] & ~pipe_flush_b) ? st_lendian_b : bst_lendian[1];
assign bst_lendian_in[2] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[2] & ~pipe_flush_b) ? st_lendian_b : bst_lendian[2];
assign bst_lendian_in[3] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[3] & ~pipe_flush_b) ? st_lendian_b : bst_lendian[3];
assign bst_lendian_in[4] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[4] & ~pipe_flush_b) ? st_lendian_b : bst_lendian[4];
assign bst_lendian_in[5] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[5] & ~pipe_flush_b) ? st_lendian_b : bst_lendian[5];
assign bst_lendian_in[6] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[6] & ~pipe_flush_b) ? st_lendian_b : bst_lendian[6];
assign bst_lendian_in[7] = (sbc_blk_inst_b & stb_cam_wptr_vld_b & thread_b[7] & ~pipe_flush_b) ? st_lendian_b : bst_lendian[7];

lsu_sbc_ctlmsff_ctl_macro__width_8 dff_bst_lendian  (
	.scan_in(dff_bst_lendian_scanin),
	.scan_out(dff_bst_lendian_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bst_lendian_in[7:0]),
	.dout	(bst_lendian[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
assign block_store_lendian = ((bst_tid[2:0] == 3'd0) & bst_lendian[0]) |
                             ((bst_tid[2:0] == 3'd1) & bst_lendian[1]) |
                             ((bst_tid[2:0] == 3'd2) & bst_lendian[2]) |
                             ((bst_tid[2:0] == 3'd3) & bst_lendian[3]) |
                             ((bst_tid[2:0] == 3'd4) & bst_lendian[4]) |
                             ((bst_tid[2:0] == 3'd5) & bst_lendian[5]) |
                             ((bst_tid[2:0] == 3'd6) & bst_lendian[6]) |
                             ((bst_tid[2:0] == 3'd7) & bst_lendian[7]) ;

assign bst_busy_rst = &(bst_count[2:0]);

assign bst_busy_in = (|(bst_sel[7:0])) | (bst_busy & ~bst_busy_rst);

lsu_sbc_ctlmsff_ctl_macro__width_1 dff_bst_busy  (
	.scan_in(dff_bst_busy_scanin),
	.scan_out(dff_bst_busy_scanout),
	.din	(bst_busy_in),
	.dout	(bst_busy_out),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// If a store buffer diag read is in M, there will be a read-write collision in the stb_cam.
// In this case, restart the block store sequence by reissuing the lsu_block_store_stall
// and reseting the internal state machine.
assign bst_busy = bst_busy_out & ~(bst_p2 & dcc_stb_diag_rd_m);

lsu_lru8_ctl bst_lru8 (
	.scan_in(bst_lru8_scanin),
	.scan_out(bst_lru8_scanout),
	.request	(sbs_bst_req[7:0]),
	.enable		(bst_sel[7:0]),
	.select		(bst_sel_unqual_p[7:0]),
  .l1clk(l1clk),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk)
);

lsu_sbc_ctlmsff_ctl_macro__width_8 dff_bst_req  (
	.scan_in(dff_bst_req_scanin),
	.scan_out(dff_bst_req_scanout),
	.din	(bst_sel_unqual_p[7:0]),
	.dout	(bst_sel_unqual[7:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign bst_sel[7:0] = bst_sel_unqual[7:0] & ~fatal_err_cond[7:0] &
                      {8{~(bst_busy | st_inst_vld_m | stb_diag_rd_w | full_raw_w | frf_read_pending)}};

assign sbc_bst_sel[7:0] = {8{bst_p2 & ~dcc_stb_diag_rd_m}} & block_store_thread[7:0];
assign any_bst_req = |(bst_sel[7:0]);

assign bst_tid_in[2:0] = lsu_block_store_stall ? lsu_block_store_tid[2:0] : bst_tid[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_bst_tid  (
	.scan_in(dff_bst_tid_scanin),
	.scan_out(dff_bst_tid_scanout),
	.din	(bst_tid_in[2:0]),
	.dout	(bst_tid[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign block_store_thread[0] = (bst_tid[2:0] == 3'd0);
assign block_store_thread[1] = (bst_tid[2:0] == 3'd1);
assign block_store_thread[2] = (bst_tid[2:0] == 3'd2);
assign block_store_thread[3] = (bst_tid[2:0] == 3'd3);
assign block_store_thread[4] = (bst_tid[2:0] == 3'd4);
assign block_store_thread[5] = (bst_tid[2:0] == 3'd5);
assign block_store_thread[6] = (bst_tid[2:0] == 3'd6);
assign block_store_thread[7] = (bst_tid[2:0] == 3'd7);

assign sbc_rmo_st_b = (dcc_binit_st_b & ~(tlb_pgnum_b39 & ~tlb_cam_mhit)) | bst_in_prog_b | (rmo_st_w & std_inst_w);

lsu_sbc_ctlmsff_ctl_macro__width_1 dff_rmo_st_w  (
	.scan_in(dff_rmo_st_w_scanin),
	.scan_out(dff_rmo_st_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	(sbc_rmo_st_b),
	.dout	(rmo_st_w),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_block_store_stall = |(bst_sel[7:0]);
assign lsu_block_store_tid[2] = bst_sel_unqual[4] | bst_sel_unqual[5] | bst_sel_unqual[6] | bst_sel_unqual[7];
assign lsu_block_store_tid[1] = bst_sel_unqual[2] | bst_sel_unqual[3] | bst_sel_unqual[6] | bst_sel_unqual[7];
assign lsu_block_store_tid[0] = bst_sel_unqual[1] | bst_sel_unqual[3] | bst_sel_unqual[5] | bst_sel_unqual[7];
assign lsu_block_store_rd[4:3] = {2{bst_sel_unqual[0]}} & bst_addr0[4:3] |
                                 {2{bst_sel_unqual[1]}} & bst_addr1[4:3] |
                                 {2{bst_sel_unqual[2]}} & bst_addr2[4:3] |
                                 {2{bst_sel_unqual[3]}} & bst_addr3[4:3] |
                                 {2{bst_sel_unqual[4]}} & bst_addr4[4:3] |
                                 {2{bst_sel_unqual[5]}} & bst_addr5[4:3] |
                                 {2{bst_sel_unqual[6]}} & bst_addr6[4:3] |
                                 {2{bst_sel_unqual[7]}} & bst_addr7[4:3] ;

// TLU must know which thread is receiving the data transfer in case of an FRF ECC error
assign lsu_block_store_b[0] = bst_in_prog_b & (bst_tid[2:0] == 3'd0);
assign lsu_block_store_b[1] = bst_in_prog_b & (bst_tid[2:0] == 3'd1);
assign lsu_block_store_b[2] = bst_in_prog_b & (bst_tid[2:0] == 3'd2);
assign lsu_block_store_b[3] = bst_in_prog_b & (bst_tid[2:0] == 3'd3);
assign lsu_block_store_b[4] = bst_in_prog_b & (bst_tid[2:0] == 3'd4);
assign lsu_block_store_b[5] = bst_in_prog_b & (bst_tid[2:0] == 3'd5);
assign lsu_block_store_b[6] = bst_in_prog_b & (bst_tid[2:0] == 3'd6);
assign lsu_block_store_b[7] = bst_in_prog_b & (bst_tid[2:0] == 3'd7);

// Sequencing logic

lsu_sbc_ctlmsff_ctl_macro__width_3 dff_bst_seq  (
	.scan_in(dff_bst_seq_scanin),
	.scan_out(dff_bst_seq_scanout),
	.din	({any_bst_req,bst_p1,bst_p2_in}),
	.dout	({bst_p1,     bst_p2,bst_p3}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign bst_p2_in = bst_p2 & ~dcc_stb_diag_rd_m;

assign sbc_load_bst_addr = bst_p2;

assign bst_count_in[2:0] = bst_count[2:0] + {2'b00,bst_in_prog_m};

assign bst_in_prog_e = bst_p3 | (|(bst_count_in[2:0]));

lsu_sbc_ctlmsff_ctl_macro__width_6 dff_bst_count  (
	.scan_in(dff_bst_count_scanin),
	.scan_out(dff_bst_count_scanout),
	.din	({bst_count_in[2:0],bst_in_prog_e,bst_in_prog_e    ,bst_in_prog_m}),
	.dout	({bst_count[2:0],   bst_in_prog_m,lsu_block_store_m,bst_in_prog_b}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbc_bst_in_prog_m = bst_in_prog_m;
assign sbc_bst_in_prog_b = bst_in_prog_b;

assign sbc_bst_offset[2:0] = bst_count[2:0];

assign lsu_block_store_alloc[0] = (bst_count[2:0] == 3'b001) & (bst_tid[2:0] == 3'd0);
assign lsu_block_store_alloc[1] = (bst_count[2:0] == 3'b001) & (bst_tid[2:0] == 3'd1);
assign lsu_block_store_alloc[2] = (bst_count[2:0] == 3'b001) & (bst_tid[2:0] == 3'd2);
assign lsu_block_store_alloc[3] = (bst_count[2:0] == 3'b001) & (bst_tid[2:0] == 3'd3);
assign lsu_block_store_alloc[4] = (bst_count[2:0] == 3'b001) & (bst_tid[2:0] == 3'd4);
assign lsu_block_store_alloc[5] = (bst_count[2:0] == 3'b001) & (bst_tid[2:0] == 3'd5);
assign lsu_block_store_alloc[6] = (bst_count[2:0] == 3'b001) & (bst_tid[2:0] == 3'd6);
assign lsu_block_store_alloc[7] = (bst_count[2:0] == 3'b001) & (bst_tid[2:0] == 3'd7);

// Must watch fgu ecc errors to know whether to kill block store
assign sbc_fgu_ecc_b = fgu_fst_ecc_error_fx2;

// If the read of the block store request gets a fatal error, kill the block store
assign bst_err_p3 = lsu_sbapp_err_g & bst_p3;

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_bst_rd_err  (
	.scan_in(dff_bst_rd_err_scanin),
	.scan_out(dff_bst_rd_err_scanout),
	.din	({bst_err_p3,bst_err_p4}),
	.dout	({bst_err_p4,sbc_bst_rd_err}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// STD
////////////////////////////////////////////////////////////////////////////////

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_std_seq  (
	.scan_in(dff_std_seq_scanin),
	.scan_out(dff_std_seq_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dcc_std_inst_m,std_inst_b}),
	.dout	({std_inst_b,    std_inst_w}),
  .siclk(siclk),
  .soclk(soclk)
);

// Need to know when a 2 cycle is writing in W in order to used the older address parity
assign sbc_twocycle_inst_w = std_inst_w | casa_inst_w;

////////////////////////////////////////////////////////////////////////////////
// Partial RAW handling
// Generate an ID for use by partial raw cases.
////////////////////////////////////////////////////////////////////////////////

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_praw_ctl_w  (
	.scan_in(dff_praw_ctl_w_scanin),
	.scan_out(dff_praw_ctl_w_scanout),
	.din	({dcc_asi_load_m,io_or_asi_load_b}),
	.dout	({asi_load_b,    io_or_asi_load_w}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign io_or_asi_load_b = asi_load_b | (tlb_pgnum_b39 & ~tlb_cam_mhit);

assign last_stb_wptr_w[2:0] = cam_wptr_w[2:0] - {3'b001};
assign rawp_id_w[2:0] = (stb_cam_mhit_w | io_or_asi_load_w | stb_diag_rd_w) ?
                         last_stb_wptr_w[2:0] : stb_cam_hit_ptr_w[2:0];

// Thread 0
assign rawp_id0[2:0] = (lmc_ld_inst_w & thread_w[0]) ? rawp_id_w[2:0] : rawp_id0_hold[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_rawp_id0  (
	.scan_in(dff_rawp_id0_scanin),
	.scan_out(dff_rawp_id0_scanout),
	.din	(rawp_id0[2:0]),
	.dout	(rawp_id0_hold[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_rawp_id0[0] = ~rawp_id0[2] & ~rawp_id0[1] & ~rawp_id0[0];
assign dec_rawp_id0[1] = ~rawp_id0[2] & ~rawp_id0[1] &  rawp_id0[0];
assign dec_rawp_id0[2] = ~rawp_id0[2] &  rawp_id0[1] & ~rawp_id0[0];
assign dec_rawp_id0[3] = ~rawp_id0[2] &  rawp_id0[1] &  rawp_id0[0];
assign dec_rawp_id0[4] =  rawp_id0[2] & ~rawp_id0[1] & ~rawp_id0[0];
assign dec_rawp_id0[5] =  rawp_id0[2] & ~rawp_id0[1] &  rawp_id0[0];
assign dec_rawp_id0[6] =  rawp_id0[2] &  rawp_id0[1] & ~rawp_id0[0];
assign dec_rawp_id0[7] =  rawp_id0[2] &  rawp_id0[1] &  rawp_id0[0];
assign sbc_rawp_rst[0] = |(dec_rawp_id0[7:0] & sbs0_state_ced[7:0]);

// Thread 1
assign rawp_id1[2:0] = (lmc_ld_inst_w & thread_w[1]) ? rawp_id_w[2:0] : rawp_id1_hold[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_rawp_id1  (
	.scan_in(dff_rawp_id1_scanin),
	.scan_out(dff_rawp_id1_scanout),
	.din	(rawp_id1[2:0]),
	.dout	(rawp_id1_hold[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_rawp_id1[0] = ~rawp_id1[2] & ~rawp_id1[1] & ~rawp_id1[0];
assign dec_rawp_id1[1] = ~rawp_id1[2] & ~rawp_id1[1] &  rawp_id1[0];
assign dec_rawp_id1[2] = ~rawp_id1[2] &  rawp_id1[1] & ~rawp_id1[0];
assign dec_rawp_id1[3] = ~rawp_id1[2] &  rawp_id1[1] &  rawp_id1[0];
assign dec_rawp_id1[4] =  rawp_id1[2] & ~rawp_id1[1] & ~rawp_id1[0];
assign dec_rawp_id1[5] =  rawp_id1[2] & ~rawp_id1[1] &  rawp_id1[0];
assign dec_rawp_id1[6] =  rawp_id1[2] &  rawp_id1[1] & ~rawp_id1[0];
assign dec_rawp_id1[7] =  rawp_id1[2] &  rawp_id1[1] &  rawp_id1[0];
assign sbc_rawp_rst[1] = |(dec_rawp_id1[7:0] & sbs1_state_ced[7:0]);

// Thread 2
assign rawp_id2[2:0] = (lmc_ld_inst_w & thread_w[2]) ? rawp_id_w[2:0] : rawp_id2_hold[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_rawp_id2  (
	.scan_in(dff_rawp_id2_scanin),
	.scan_out(dff_rawp_id2_scanout),
	.din	(rawp_id2[2:0]),
	.dout	(rawp_id2_hold[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_rawp_id2[0] = ~rawp_id2[2] & ~rawp_id2[1] & ~rawp_id2[0];
assign dec_rawp_id2[1] = ~rawp_id2[2] & ~rawp_id2[1] &  rawp_id2[0];
assign dec_rawp_id2[2] = ~rawp_id2[2] &  rawp_id2[1] & ~rawp_id2[0];
assign dec_rawp_id2[3] = ~rawp_id2[2] &  rawp_id2[1] &  rawp_id2[0];
assign dec_rawp_id2[4] =  rawp_id2[2] & ~rawp_id2[1] & ~rawp_id2[0];
assign dec_rawp_id2[5] =  rawp_id2[2] & ~rawp_id2[1] &  rawp_id2[0];
assign dec_rawp_id2[6] =  rawp_id2[2] &  rawp_id2[1] & ~rawp_id2[0];
assign dec_rawp_id2[7] =  rawp_id2[2] &  rawp_id2[1] &  rawp_id2[0];
assign sbc_rawp_rst[2] = |(dec_rawp_id2[7:0] & sbs2_state_ced[7:0]);

// Thread 3
assign rawp_id3[2:0] = (lmc_ld_inst_w & thread_w[3]) ? rawp_id_w[2:0] : rawp_id3_hold[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_rawp_id3  (
	.scan_in(dff_rawp_id3_scanin),
	.scan_out(dff_rawp_id3_scanout),
	.din	(rawp_id3[2:0]),
	.dout	(rawp_id3_hold[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_rawp_id3[0] = ~rawp_id3[2] & ~rawp_id3[1] & ~rawp_id3[0];
assign dec_rawp_id3[1] = ~rawp_id3[2] & ~rawp_id3[1] &  rawp_id3[0];
assign dec_rawp_id3[2] = ~rawp_id3[2] &  rawp_id3[1] & ~rawp_id3[0];
assign dec_rawp_id3[3] = ~rawp_id3[2] &  rawp_id3[1] &  rawp_id3[0];
assign dec_rawp_id3[4] =  rawp_id3[2] & ~rawp_id3[1] & ~rawp_id3[0];
assign dec_rawp_id3[5] =  rawp_id3[2] & ~rawp_id3[1] &  rawp_id3[0];
assign dec_rawp_id3[6] =  rawp_id3[2] &  rawp_id3[1] & ~rawp_id3[0];
assign dec_rawp_id3[7] =  rawp_id3[2] &  rawp_id3[1] &  rawp_id3[0];
assign sbc_rawp_rst[3] = |(dec_rawp_id3[7:0] & sbs3_state_ced[7:0]);

// Thread 4
assign rawp_id4[2:0] = (lmc_ld_inst_w & thread_w[4]) ? rawp_id_w[2:0] : rawp_id4_hold[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_rawp_id4  (
	.scan_in(dff_rawp_id4_scanin),
	.scan_out(dff_rawp_id4_scanout),
	.din	(rawp_id4[2:0]),
	.dout	(rawp_id4_hold[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_rawp_id4[0] = ~rawp_id4[2] & ~rawp_id4[1] & ~rawp_id4[0];
assign dec_rawp_id4[1] = ~rawp_id4[2] & ~rawp_id4[1] &  rawp_id4[0];
assign dec_rawp_id4[2] = ~rawp_id4[2] &  rawp_id4[1] & ~rawp_id4[0];
assign dec_rawp_id4[3] = ~rawp_id4[2] &  rawp_id4[1] &  rawp_id4[0];
assign dec_rawp_id4[4] =  rawp_id4[2] & ~rawp_id4[1] & ~rawp_id4[0];
assign dec_rawp_id4[5] =  rawp_id4[2] & ~rawp_id4[1] &  rawp_id4[0];
assign dec_rawp_id4[6] =  rawp_id4[2] &  rawp_id4[1] & ~rawp_id4[0];
assign dec_rawp_id4[7] =  rawp_id4[2] &  rawp_id4[1] &  rawp_id4[0];
assign sbc_rawp_rst[4] = |(dec_rawp_id4[7:0] & sbs4_state_ced[7:0]);

// Thread 5
assign rawp_id5[2:0] = (lmc_ld_inst_w & thread_w[5]) ? rawp_id_w[2:0] : rawp_id5_hold[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_rawp_id5  (
	.scan_in(dff_rawp_id5_scanin),
	.scan_out(dff_rawp_id5_scanout),
	.din	(rawp_id5[2:0]),
	.dout	(rawp_id5_hold[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_rawp_id5[0] = ~rawp_id5[2] & ~rawp_id5[1] & ~rawp_id5[0];
assign dec_rawp_id5[1] = ~rawp_id5[2] & ~rawp_id5[1] &  rawp_id5[0];
assign dec_rawp_id5[2] = ~rawp_id5[2] &  rawp_id5[1] & ~rawp_id5[0];
assign dec_rawp_id5[3] = ~rawp_id5[2] &  rawp_id5[1] &  rawp_id5[0];
assign dec_rawp_id5[4] =  rawp_id5[2] & ~rawp_id5[1] & ~rawp_id5[0];
assign dec_rawp_id5[5] =  rawp_id5[2] & ~rawp_id5[1] &  rawp_id5[0];
assign dec_rawp_id5[6] =  rawp_id5[2] &  rawp_id5[1] & ~rawp_id5[0];
assign dec_rawp_id5[7] =  rawp_id5[2] &  rawp_id5[1] &  rawp_id5[0];
assign sbc_rawp_rst[5] = |(dec_rawp_id5[7:0] & sbs5_state_ced[7:0]);

// Thread 6
assign rawp_id6[2:0] = (lmc_ld_inst_w & thread_w[6]) ? rawp_id_w[2:0] : rawp_id6_hold[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_rawp_id6  (
	.scan_in(dff_rawp_id6_scanin),
	.scan_out(dff_rawp_id6_scanout),
	.din	(rawp_id6[2:0]),
	.dout	(rawp_id6_hold[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_rawp_id6[0] = ~rawp_id6[2] & ~rawp_id6[1] & ~rawp_id6[0];
assign dec_rawp_id6[1] = ~rawp_id6[2] & ~rawp_id6[1] &  rawp_id6[0];
assign dec_rawp_id6[2] = ~rawp_id6[2] &  rawp_id6[1] & ~rawp_id6[0];
assign dec_rawp_id6[3] = ~rawp_id6[2] &  rawp_id6[1] &  rawp_id6[0];
assign dec_rawp_id6[4] =  rawp_id6[2] & ~rawp_id6[1] & ~rawp_id6[0];
assign dec_rawp_id6[5] =  rawp_id6[2] & ~rawp_id6[1] &  rawp_id6[0];
assign dec_rawp_id6[6] =  rawp_id6[2] &  rawp_id6[1] & ~rawp_id6[0];
assign dec_rawp_id6[7] =  rawp_id6[2] &  rawp_id6[1] &  rawp_id6[0];
assign sbc_rawp_rst[6] = |(dec_rawp_id6[7:0] & sbs6_state_ced[7:0]);

// Thread 7
assign rawp_id7[2:0] = (lmc_ld_inst_w & thread_w[7]) ? rawp_id_w[2:0] : rawp_id7_hold[2:0];
lsu_sbc_ctlmsff_ctl_macro__width_3 dff_rawp_id7  (
	.scan_in(dff_rawp_id7_scanin),
	.scan_out(dff_rawp_id7_scanout),
	.din	(rawp_id7[2:0]),
	.dout	(rawp_id7_hold[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_rawp_id7[0] = ~rawp_id7[2] & ~rawp_id7[1] & ~rawp_id7[0];
assign dec_rawp_id7[1] = ~rawp_id7[2] & ~rawp_id7[1] &  rawp_id7[0];
assign dec_rawp_id7[2] = ~rawp_id7[2] &  rawp_id7[1] & ~rawp_id7[0];
assign dec_rawp_id7[3] = ~rawp_id7[2] &  rawp_id7[1] &  rawp_id7[0];
assign dec_rawp_id7[4] =  rawp_id7[2] & ~rawp_id7[1] & ~rawp_id7[0];
assign dec_rawp_id7[5] =  rawp_id7[2] & ~rawp_id7[1] &  rawp_id7[0];
assign dec_rawp_id7[6] =  rawp_id7[2] &  rawp_id7[1] & ~rawp_id7[0];
assign dec_rawp_id7[7] =  rawp_id7[2] &  rawp_id7[1] &  rawp_id7[0];
assign sbc_rawp_rst[7] = |(dec_rawp_id7[7:0] & sbs7_state_ced[7:0]);

////////////////////////////////////////////////////////////////////////////////
// Misc
////////////////////////////////////////////////////////////////////////////////

// Atomics are uncacheable.
assign sbc_st_pcx_nc = sbc_st_type_p4[1];

////////////////////////////////////////////////////////////////////////////////
// Store buffer RAM diagnostics and error handling
////////////////////////////////////////////////////////////////////////////////

// To make the error resolution even more robust, I'm encoding the priv/hpriv bits
// into three bits.  Each priv level has a Hamming distance >1 from the others, so
// I know if the parity error affected the priv information.

assign priv_enc[2] = dcc_hpriv_b;
assign priv_enc[1] = dcc_priv_b & ~dcc_hpriv_b;
assign priv_enc[0] = dcc_hpriv_b | dcc_priv_b;

assign sbc_stb_ctl_data[2:0] = mbi_run_local ? mbi_wdata[2:0] : priv_enc[2:0];

assign inv_addr_prty_m = lsu_asi_error_inject_b31 & lsu_asi_error_inject_b19 & ~dcc_wr_error_inj_m;
assign inv_ecc_m = lsu_asi_error_inject_b31 & lsu_asi_error_inject_b17 & ~dcc_wr_error_inj_m;

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_error_inj  (
	.scan_in(dff_error_inj_scanin),
	.scan_out(dff_error_inj_scanout),
	.l1clk	(l1clk_pm1),
	.din	({inv_addr_prty_m,inv_ecc_m}),
	.dout	({inv_addr_prty_b,inv_ecc_b}),
  .siclk(siclk),
  .soclk(soclk)
);
assign sbc_inv_addr_prty = inv_addr_prty_b; 
assign sbc_inv_ecc[6:0] = {7{inv_ecc_b}} & lsu_asi_error_inject[6:0];

////////////////////////////////////////////////////////////////////////////////
// BIST
////////////////////////////////////////////////////////////////////////////////

lsu_sbc_ctlmsff_ctl_macro__width_5 dff_bist_in  (
	.scan_in(dff_bist_in_scanin),
	.scan_out(dff_bist_in_scanout),
	.l1clk	(l1clk_pm1),
	.din	({mbi_stb_cam_read_en,bist_scm_rd_1,  mbi_stb_ram_read_en,bist_srm_rd_1,  mbi_run}),
	.dout	({bist_scm_rd_1,      bist_scm_cmp_en,bist_srm_rd_1,      bist_srm_cmp_en,mbi_run_local}),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbc_mbi_run = mbi_run_local;

assign stb_cam_fail = bist_scm_cmp_en & (~sed_bist_cmp_0 | ~sed_bist_cmp_1 | ~sed_bist_cmp_2 | ~sed_bist_cmp_3);
assign stb_ram_fail = bist_srm_cmp_en & (~sed_bist_cmp_0 | ~sed_bist_cmp_1 | ~sed_bist_cmp_2 | ~sed_bist_cmp_3);

lsu_sbc_ctlmsff_ctl_macro__width_2 dff_bist_fail  (
	.scan_in(dff_bist_fail_scanin),
	.scan_out(dff_bist_fail_scanout),
	.l1clk	(l1clk_pm1),
	.din	({stb_cam_fail,        stb_ram_fail}),
	.dout	({lsu_mbi_stb_cam_fail,lsu_mbi_stb_ram_fail}),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Junk to prevent a collision at the FRF.  Without this, there is a possibility
// that a block store (which reads the FRF) could collide with an ASI read.
// When I detect an ASI read going out, supress block store requests until it
// comes back.
////////////////////////////////////////////////////////////////////////////////

assign frf_read_out = pic_asi_sel_p4 & ~st_asi_sel_p4 & (lmd_asi_type[1:0] == 2'b00) & (lmd_asi_asi[7:0] == 8'h49);
assign frf_read_pending_in = frf_read_out | (frf_read_pending & ~lmc_asi_indet_retire);

lsu_sbc_ctlmsff_ctl_macro__width_1 dff_frf_read  (
	.scan_in(dff_frf_read_scanin),
	.scan_out(dff_frf_read_scanout),
	.din	(frf_read_pending_in),
	.dout	(frf_read_pending),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_frf_read_pending = frf_read_pending;

lsu_sbc_ctlmsff_ctl_macro__scanreverse_1__width_5 dff_spares   (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.din	({3'b0,       indet_block_req_p2,indet_block_req_p3}),
	.dout	({unused[2:0],indet_block_req_p3,indet_block_req_p4}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

//spare_ctl_macro spares (num=5) (
//	.scan_in(spares_scanin),
//	.scan_out(spares_scanout),
//	.l1clk	(l1clk)
//);

supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_flush_b_scanin        = scan_in                  ;
assign dff_flush_w_scanin        = dff_flush_b_scanout      ;
assign dff_inst_m_scanin         = dff_flush_w_scanout      ;
assign dff_ldst_fp_m_scanin      = dff_inst_m_scanout       ;
assign dff_ldst_sz_b_scanin      = dff_ldst_fp_m_scanout    ;
assign dff_st_w_scanin           = dff_ldst_sz_b_scanout    ;
assign dff_st_le_b_scanin        = dff_st_w_scanout         ;
assign dff_cam_hit_scanin        = dff_st_le_b_scanout      ;
assign dff_ram_wptr_vld_b_scanin = dff_cam_hit_scanout      ;
assign dff_stb_wptr_vld_w_scanin = dff_ram_wptr_vld_b_scanout;
assign dff_tid_m_scanin          = dff_stb_wptr_vld_w_scanout;
assign dff_thread_b_scanin       = dff_tid_m_scanout        ;
assign dff_cam_wptr_scanin       = dff_thread_b_scanout     ;
assign dff_ram_rptr_scanin       = dff_cam_wptr_scanout     ;
assign dff_st_rq_p2_scanin       = dff_ram_rptr_scanout     ;
assign st_lru8_scanin            = dff_st_rq_p2_scanout     ;
assign dff_indet_temp_scanin     = st_lru8_scanout          ;
assign dff_st_sel_p3_scanin      = dff_indet_temp_scanout   ;
assign dff_asi_indet_scanin      = dff_st_sel_p3_scanout    ;
assign dff_st_sel_p4_scanin      = dff_asi_indet_scanout    ;
assign dff_cerer_scanin          = dff_st_sel_p4_scanout    ;
assign dff_stb_err_scanin        = dff_cerer_scanout        ;
assign dff_fatal_err_scanin      = dff_stb_err_scanout      ;
assign dff_bst_addr_pipe_scanin  = dff_fatal_err_scanout    ;
assign dff_bst_addr_scanin       = dff_bst_addr_pipe_scanout;
assign dff_bst_lendian_scanin    = dff_bst_addr_scanout     ;
assign dff_bst_busy_scanin       = dff_bst_lendian_scanout  ;
assign bst_lru8_scanin           = dff_bst_busy_scanout     ;
assign dff_bst_req_scanin        = bst_lru8_scanout         ;
assign dff_bst_tid_scanin        = dff_bst_req_scanout      ;
assign dff_rmo_st_w_scanin       = dff_bst_tid_scanout      ;
assign dff_bst_seq_scanin        = dff_rmo_st_w_scanout     ;
assign dff_bst_count_scanin      = dff_bst_seq_scanout      ;
assign dff_bst_rd_err_scanin     = dff_bst_count_scanout    ;
assign dff_std_seq_scanin        = dff_bst_rd_err_scanout   ;
assign dff_praw_ctl_w_scanin     = dff_std_seq_scanout      ;
assign dff_rawp_id0_scanin       = dff_praw_ctl_w_scanout   ;
assign dff_rawp_id1_scanin       = dff_rawp_id0_scanout     ;
assign dff_rawp_id2_scanin       = dff_rawp_id1_scanout     ;
assign dff_rawp_id3_scanin       = dff_rawp_id2_scanout     ;
assign dff_rawp_id4_scanin       = dff_rawp_id3_scanout     ;
assign dff_rawp_id5_scanin       = dff_rawp_id4_scanout     ;
assign dff_rawp_id6_scanin       = dff_rawp_id5_scanout     ;
assign dff_rawp_id7_scanin       = dff_rawp_id6_scanout     ;
assign dff_error_inj_scanin      = dff_rawp_id7_scanout     ;
assign dff_bist_in_scanin        = dff_error_inj_scanout    ;
assign dff_bist_fail_scanin      = dff_bist_in_scanout      ;
assign dff_frf_read_scanin       = dff_bist_fail_scanout    ;
assign spares_scanin             = dff_frf_read_scanout     ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctll1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_18 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [17:0] fdin;
wire [16:0] so;

  input [17:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [17:0] dout;
  output scan_out;
assign fdin[17:0] = din[17:0];


dff #(18)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[17:0]),
.si({scan_in,so[16:0]}),
.so({so[16:0],scan_out}),
.q(dout[17:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_11 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [10:0] fdin;
wire [9:0] so;

  input [10:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [10:0] dout;
  output scan_out;
assign fdin[10:0] = din[10:0];


dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbc_ctlmsff_ctl_macro__scanreverse_1__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [0:3] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({so[0:3],scan_in}),
.so({scan_out,so[0:3]}),
.q(dout[4:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_sbd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_sbd_dp (
  const_cpuid, 
  lsu_va_m, 
  exu_lsu_store_data_e, 
  fgu_lsu_fst_data_fx1, 
  tlb_pgnum_crit, 
  tlb_tte_ie_b, 
  sbc_st_int_sel_m, 
  sbc_bst_offset, 
  sbc_bst_in_prog_m, 
  sbc_load_bst_addr, 
  sec_st_sz_dw_std_le_b, 
  sec_st_sz_dw_le_not_ie_b, 
  sec_st_sz_dw_be_not_ie_b, 
  sec_st_sz_word_le_not_ie_b, 
  sec_st_sz_word_be_not_ie_b, 
  sec_st_sz_hw_le_not_ie_b, 
  sec_st_sz_hw_be_not_ie_b, 
  sec_st_sz_dw_le_if_ie_b, 
  sec_st_sz_dw_be_if_ie_b, 
  sec_st_sz_word_le_if_ie_b, 
  sec_st_sz_word_be_if_ie_b, 
  sec_st_sz_hw_le_if_ie_b, 
  sec_st_sz_hw_be_if_ie_b, 
  sec_st_sz_byte_b, 
  dcc_tid_m, 
  dcc_asi_m, 
  dcc_sbd_e_clken, 
  dcc_sbd_m_clken, 
  dcc_std_inst_m, 
  dcc_fp32b_sel_m, 
  dcc_asi_iomap_m, 
  dcc_cache_diag_wr_m, 
  dcc_demap_asi_m, 
  dcc_ldstub_inst_m, 
  stb_cam_data, 
  dcs_memref_m, 
  mbi_run, 
  mbi_cambist_run, 
  mbi_wdata, 
  mbi_ptag_data, 
  mbi_init_to_zero, 
  mbi_cambist_shift, 
  sbd_st_data_b, 
  sbd_st_data2_b, 
  sbd_st_datab_b, 
  sbd_st_predata_b, 
  sbd_st_addr_b, 
  stb_st_addr_m, 
  stb_st_addr_b, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire dff_st_data_m_0_scanin;
wire dff_st_data_m_0_scanout;
wire [63:0] pre_st_data_m;
wire dff_st_data_m_1_scanin;
wire dff_st_data_m_1_scanout;
wire ldstub_inst_m_0;
wire ldstub_inst_m_1;
wire [63:0] pre_st_data2_m;
wire [63:0] st_data_m;
wire dff_st_data_b_0_scanin;
wire dff_st_data_b_0_scanout;
wire [63:0] st_data_b;
wire dff_st_data_b_1_scanin;
wire dff_st_data_b_1_scanout;
wire [7:0] byte0;
wire [7:0] byte1;
wire [7:0] byte2;
wire [7:0] byte3;
wire [7:0] byte4;
wire [7:0] byte5;
wire [7:0] byte6;
wire [7:0] byte7;
wire [63:0] st_data_ie0_b;
wire [63:0] st_data_ie1_b;
wire [39:3] st_addr_b;
wire [39:3] bist_data;
wire [39:6] bst_addr;
wire [39:3] st_addr_m;
wire dff_st_addr_scanin;
wire dff_st_addr_scanout;
wire dff_bst_addr_scanin;
wire dff_bst_addr_scanout;


input	[2:0]	const_cpuid;

input	[47:3]	lsu_va_m;		

input	[63:0]	exu_lsu_store_data_e;

input	[63:0]	fgu_lsu_fst_data_fx1;

input	[39:13]	tlb_pgnum_crit;
input		tlb_tte_ie_b;

input		sbc_st_int_sel_m;
input	[2:0]	sbc_bst_offset;
input		sbc_bst_in_prog_m;
input		sbc_load_bst_addr;

input		sec_st_sz_dw_std_le_b;
input		sec_st_sz_dw_le_not_ie_b;
input		sec_st_sz_dw_be_not_ie_b;
input		sec_st_sz_word_le_not_ie_b;
input		sec_st_sz_word_be_not_ie_b;
input		sec_st_sz_hw_le_not_ie_b;
input		sec_st_sz_hw_be_not_ie_b;
input		sec_st_sz_dw_le_if_ie_b;
input		sec_st_sz_dw_be_if_ie_b;
input		sec_st_sz_word_le_if_ie_b;
input		sec_st_sz_word_be_if_ie_b;
input		sec_st_sz_hw_le_if_ie_b;
input		sec_st_sz_hw_be_if_ie_b;
input		sec_st_sz_byte_b;

input	[2:0]	dcc_tid_m;
input	[7:0]	dcc_asi_m;
input		dcc_sbd_e_clken;
input		dcc_sbd_m_clken;
input		dcc_std_inst_m;
input		dcc_fp32b_sel_m;
input		dcc_asi_iomap_m;
input		dcc_cache_diag_wr_m;
input		dcc_demap_asi_m;
input		dcc_ldstub_inst_m;

input	[44:11]	stb_cam_data;

input		dcs_memref_m;

input		mbi_run;
input		mbi_cambist_run;
input	[7:0]	mbi_wdata;
input		mbi_ptag_data;
input		mbi_init_to_zero;
input		mbi_cambist_shift;

output	[63:0]	sbd_st_data_b;		// Final formatted data
output	[63:0]	sbd_st_data2_b;		// Final formatted data
output	[63:0]	sbd_st_datab_b;		// Final formatted data with bist
output	[47:0]	sbd_st_predata_b;	// Unformatted store data (ok for ASI writes)
output	[39:3]	sbd_st_addr_b;
output	[39:3]	stb_st_addr_m;
output	[39:13]	stb_st_addr_b;

// Globals
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

// scan renames
assign stop = 1'b0;
// end scan

lsu_sbd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);

////////////////////////////////////////////////////////////////////////////////
// Mux different sources of store data.  FGU data gets muxed spearately in M
// because it comes in that cycle.

lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 dff_st_data_m_0      (
	.scan_in(dff_st_data_m_0_scanin),
	.scan_out(dff_st_data_m_0_scanout),
	.din0	(pre_st_data_m[31:0]),					// std
	.din1	(exu_lsu_store_data_e[63:32]),				// default
	.sel0	(dcc_std_inst_m),
	.dout	(pre_st_data_m[63:32]),
	.clk    (l2clk),
	.en	(dcc_sbd_e_clken),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	// enable on stores, second half of STD/CAS
);
lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 dff_st_data_m_1      (
	.scan_in(dff_st_data_m_1_scanin),
	.scan_out(dff_st_data_m_1_scanout),
	.din0	(exu_lsu_store_data_e[31:0]),				// std
	.din1	(exu_lsu_store_data_e[31:0]),				// default
	.sel0	(dcc_std_inst_m),
	.dout	(pre_st_data_m[31:0]),
	.clk    (l2clk),
	.en	(dcc_sbd_e_clken),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	// enable on stores, second half of STD/CAS
);

lsu_sbd_dp_buff_macro__rep_1__width_2 ldstub_buf  (
	.din	({2{dcc_ldstub_inst_m}}),
	.dout	({ldstub_inst_m_0,ldstub_inst_m_1})
);

lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 ldstub_or_0    (
	.din0	(pre_st_data_m[63:32]),
	.din1	({32{ldstub_inst_m_0}}),
	.dout	(pre_st_data2_m[63:32])
);

lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 ldstub_or_1    (
	.din0	(pre_st_data_m[31:0]),
	.din1	({32{ldstub_inst_m_1}}),
	.dout	(pre_st_data2_m[31:0])
);

lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 mx_data_m_0      (
	.din0	({16'b0,lsu_va_m[47:32]}),
	.din1	(pre_st_data2_m[63:32]),
	.din2	(fgu_lsu_fst_data_fx1[63:32]),
	.din3	(fgu_lsu_fst_data_fx1[63:32]),
	.sel0	(dcc_demap_asi_m),
	.sel1	(sbc_st_int_sel_m),
	.sel2	(dcc_fp32b_sel_m),
	.dout	(st_data_m[63:32])
);
lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 mx_data_m_1      (
	.din0	({lsu_va_m[31:3],3'b0}),
	.din1	(pre_st_data2_m[31:0]),
	.din2	(fgu_lsu_fst_data_fx1[63:32]),
	.din3	(fgu_lsu_fst_data_fx1[31:0]),
	.sel0	(dcc_demap_asi_m),
	.sel1	(sbc_st_int_sel_m),
	.sel2	(dcc_fp32b_sel_m),
	.dout	(st_data_m[31:0])
);

lsu_sbd_dp_msff_macro__stack_32c__width_32 dff_st_data_b_0    (
	.scan_in(dff_st_data_b_0_scanin),
	.scan_out(dff_st_data_b_0_scanout),
	.din    (st_data_m[63:32]),
	.dout	(st_data_b[63:32]),
	.clk    (l2clk),
	.en	(dcc_sbd_m_clken),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_sbd_dp_msff_macro__stack_32c__width_32 dff_st_data_b_1    (
	.scan_in(dff_st_data_b_1_scanin),
	.scan_out(dff_st_data_b_1_scanout),
	.din    (st_data_m[31:0]),
	.dout	(st_data_b[31:0]),
	.clk    (l2clk),
	.en	(dcc_sbd_m_clken),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_16 st_predata_buf_0   (
	.din	(st_data_b[47:32]),
	.dout	(sbd_st_predata_b[47:32])
);
lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_32 st_predata_buf_1   (
	.din	(st_data_b[31:0]),
	.dout	(sbd_st_predata_b[31:0])
);

////////////////////////////////////////////////////////////////////////////////
// Little endian swapping and data fill

assign byte0[7:0] = st_data_b[7:0];
assign byte1[7:0] = st_data_b[15:8];
assign byte2[7:0] = st_data_b[23:16];
assign byte3[7:0] = st_data_b[31:24];
assign byte4[7:0] = st_data_b[39:32];
assign byte5[7:0] = st_data_b[47:40];
assign byte6[7:0] = st_data_b[55:48];
assign byte7[7:0] = st_data_b[63:56];

// Replicate data of size <64b to fill the line.

lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie0_0      (
	.din0	({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}),
	.din1	({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
	.din2	({byte7[7:0],byte6[7:0],byte5[7:0],byte4[7:0]}),
	.din3	({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
	.din4	({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
	.din5	({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}),
	.din6	({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}),
	.din7	({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}),
	.sel0	(sec_st_sz_dw_std_le_b),
	.sel1	(sec_st_sz_dw_le_not_ie_b),
	.sel2	(sec_st_sz_dw_be_not_ie_b),
	.sel3	(sec_st_sz_word_le_not_ie_b),
	.sel4	(sec_st_sz_word_be_not_ie_b),
	.sel5	(sec_st_sz_hw_le_not_ie_b),
	.sel6	(sec_st_sz_hw_be_not_ie_b),
	.sel7	(sec_st_sz_byte_b),
	.dout	(st_data_ie0_b[63:32])
);

lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie0_1      (
	.din0	({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
	.din1	({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}),
	.din2	({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
	.din3	({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
	.din4	({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
	.din5	({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}),
	.din6	({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}),
	.din7	({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}),
	.sel0	(sec_st_sz_dw_std_le_b),
	.sel1	(sec_st_sz_dw_le_not_ie_b),
	.sel2	(sec_st_sz_dw_be_not_ie_b),
	.sel3	(sec_st_sz_word_le_not_ie_b),
	.sel4	(sec_st_sz_word_be_not_ie_b),
	.sel5	(sec_st_sz_hw_le_not_ie_b),
	.sel6	(sec_st_sz_hw_be_not_ie_b),
	.sel7	(sec_st_sz_byte_b),
	.dout	(st_data_ie0_b[31:0])
);

lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie1_0      (
	.din0	({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}),
	.din1	({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
	.din2	({byte7[7:0],byte6[7:0],byte5[7:0],byte4[7:0]}),
	.din3	({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
	.din4	({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
	.din5	({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}),
	.din6	({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}),
	.din7	({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}),
	.sel0	(sec_st_sz_dw_std_le_b),
	.sel1	(sec_st_sz_dw_le_if_ie_b),
	.sel2	(sec_st_sz_dw_be_if_ie_b),
	.sel3	(sec_st_sz_word_le_if_ie_b),
	.sel4	(sec_st_sz_word_be_if_ie_b),
	.sel5	(sec_st_sz_hw_le_if_ie_b),
	.sel6	(sec_st_sz_hw_be_if_ie_b),
	.sel7	(sec_st_sz_byte_b),
	.dout	(st_data_ie1_b[63:32])
);

lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 mx_ie1_1      (
	.din0	({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
	.din1	({byte4[7:0],byte5[7:0],byte6[7:0],byte7[7:0]}),
	.din2	({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
	.din3	({byte0[7:0],byte1[7:0],byte2[7:0],byte3[7:0]}),
	.din4	({byte3[7:0],byte2[7:0],byte1[7:0],byte0[7:0]}),
	.din5	({byte0[7:0],byte1[7:0],byte0[7:0],byte1[7:0]}),
	.din6	({byte1[7:0],byte0[7:0],byte1[7:0],byte0[7:0]}),
	.din7	({byte0[7:0],byte0[7:0],byte0[7:0],byte0[7:0]}),
	.sel0	(sec_st_sz_dw_std_le_b),
	.sel1	(sec_st_sz_dw_le_if_ie_b),
	.sel2	(sec_st_sz_dw_be_if_ie_b),
	.sel3	(sec_st_sz_word_le_if_ie_b),
	.sel4	(sec_st_sz_word_be_if_ie_b),
	.sel5	(sec_st_sz_hw_le_if_ie_b),
	.sel6	(sec_st_sz_hw_be_if_ie_b),
	.sel7	(sec_st_sz_byte_b),
	.dout	(st_data_ie1_b[31:0])
);

lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_endian_0      (
	.din0	(st_data_ie1_b[63:32]),
	.din1	(st_data_ie0_b[63:32]),
	.sel0	(tlb_tte_ie_b),
	.dout	(sbd_st_data_b[63:32])
);
lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_endian_1      (
	.din0	(st_data_ie1_b[31:0]),
	.din1	(st_data_ie0_b[31:0]),
	.sel0	(tlb_tte_ie_b),
	.dout	(sbd_st_data_b[31:0])
);

lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 st_data_buf_0    (
	.din	(sbd_st_data_b[63:32]),
	.dout	(sbd_st_data2_b[63:32])
);
lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 st_data_buf_1    (
	.din	(sbd_st_data_b[31:0]),
	.dout	(sbd_st_data2_b[31:0])
);

lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 mx_bist_0      (
	.din0	({4{mbi_wdata[7:0]}}),
	.din1	(sbd_st_data2_b[63:32]),
	.sel0	(mbi_run),
	.dout	(sbd_st_datab_b[63:32])
);
lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 mx_bist_1      (
	.din0	({4{mbi_wdata[7:0]}}),
	.din1	(sbd_st_data2_b[31:0]),
	.sel0	(mbi_run),
	.dout	(sbd_st_datab_b[31:0])
);

////////////////////////////////////////////////////////////////////////////////
// Block store address flop and address mux.
// When a block store initiates, load the address in the mux.  With each step of
// the store, increment the address.  Store addresses either come from the tlb
// or from the block store address flop.

lsu_sbd_dp_mux_macro__left_1__mux_aope__ports_4__stack_38l__width_37 sbd_bist_mux       (
	.din0	({{36{1'b0}},1'b1}),
	.din1	({st_addr_b[38:3],1'b0}),
	.din2	({37{mbi_ptag_data}}),
	.din3	({{4{mbi_wdata[7:0]}},mbi_wdata[7:3]}),
	.sel0	(mbi_init_to_zero),
	.sel1	(mbi_cambist_shift),
	.sel2	(mbi_cambist_run),
	.dout	({bist_data[39:3]})
);

// During Lbist, dcc_asi_iomap_m is forced high.  This prevents the tlb_pgnum_crit
// from propagating.
lsu_sbd_dp_mux_macro__dmux_8x__left_1__mux_aope__ports_5__stack_38l__width_37 st_addr_mux        (
	.din0	(bist_data[39:3]),
	.din1	({bst_addr[39:6],sbc_bst_offset[2:0]}),
	.din2	({8'h90,const_cpuid[2:0],dcc_tid_m[2:0],dcc_asi_m[7:0],lsu_va_m[17:3]}),
	.din3	({pre_st_data_m[30:2],lsu_va_m[10:3]}),
	.din4	({tlb_pgnum_crit[39:13],lsu_va_m[12:3]}),
	.sel0	(mbi_run),
	.sel1	(sbc_bst_in_prog_m),
	.sel2	(dcc_asi_iomap_m),
	.sel3	(dcc_cache_diag_wr_m),
	.dout	({st_addr_m[39:3]})
);

assign stb_st_addr_m[39:3] = st_addr_m[39:3];	// to stb_cam

lsu_sbd_dp_msff_macro__left_1__stack_38l__width_37 dff_st_addr    (
	.scan_in(dff_st_addr_scanin),
	.scan_out(dff_st_addr_scanout),
	.din	(st_addr_m[39:3]),
	.dout	(st_addr_b[39:3]),
	.clk	(l2clk),
	.en	(dcs_memref_m),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_sbd_dp_buff_macro__left_1__rep_1__stack_38l__width_37 st_addr_b_buf    (
	.din	(st_addr_b[39:3]),
	.dout	(sbd_st_addr_b[39:3])
);

lsu_sbd_dp_buff_macro__left_10__rep_1__stack_40c__width_27 stb_st_addr_b_buf    (
	.din	(st_addr_b[39:13]),
	.dout	(stb_st_addr_b[39:13])
);

lsu_sbd_dp_msff_macro__left_4__minbuff_1__stack_38l__width_34 dff_bst_addr      (
	.scan_in(dff_bst_addr_scanin),
	.scan_out(dff_bst_addr_scanout),
	.din	(stb_cam_data[44:11]),
	.dout	(bst_addr[39:6]),
	.clk	(l2clk),
	.en	(sbc_load_bst_addr),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// fixscan start:
assign dff_st_data_m_0_scanin    = scan_in                  ;
assign dff_st_data_m_1_scanin    = dff_st_data_m_0_scanout  ;
assign dff_st_data_b_0_scanin    = dff_st_data_m_1_scanout  ;
assign dff_st_data_b_1_scanin    = dff_st_data_b_0_scanout  ;
assign dff_st_addr_scanin        = dff_st_data_b_1_scanout  ;
assign dff_bst_addr_scanin       = dff_st_addr_scanout      ;
assign scan_out                  = dff_bst_addr_scanout     ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_sbd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_msff_macro__mux_aope__ports_2__stack_32c__width_32 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [31:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(32)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(muxout[31:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module lsu_sbd_dp_buff_macro__rep_1__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module lsu_sbd_dp_or_macro__ports_2__stack_32c__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output [31:0] dout;


or2 #(32)  d0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_mux_macro__mux_aope__ports_4__stack_32c__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [31:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
.dout(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_msff_macro__stack_32c__width_32 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_16 (
  din, 
  dout);
  input [15:0] din;
  output [15:0] dout;


buff #(16)  d0_0 (
.in(din[15:0]),
.out(dout[15:0])
);


endmodule


//
//   buff macro
//
//


module lsu_sbd_dp_buff_macro__rep_1__stack_32c__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_mux_macro__mux_aonpe__ports_8__stack_32c__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  input [31:0] din2;
  input sel2;
  input [31:0] din3;
  input sel3;
  input [31:0] din4;
  input sel4;
  input [31:0] din5;
  input sel5;
  input [31:0] din6;
  input sel6;
  input [31:0] din7;
  input sel7;
  output [31:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(32)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
  .in5(din5[31:0]),
  .in6(din6[31:0]),
  .in7(din7[31:0]),
.dout(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;
  output [31:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(32)  d0_0 (
  .sel(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module lsu_sbd_dp_buff_macro__dbuff_16x__rep_1__stack_32c__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_mux_macro__mux_aope__ports_2__stack_32c__width_32 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;
  output [31:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_mux_macro__left_1__mux_aope__ports_4__stack_38l__width_37 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [36:0] din0;
  input [36:0] din1;
  input [36:0] din2;
  input [36:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [36:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(37)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[36:0]),
  .in1(din1[36:0]),
  .in2(din2[36:0]),
  .in3(din3[36:0]),
.dout(dout[36:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_mux_macro__dmux_8x__left_1__mux_aope__ports_5__stack_38l__width_37 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;

  input [36:0] din0;
  input [36:0] din1;
  input [36:0] din2;
  input [36:0] din3;
  input [36:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  output [36:0] dout;


cl_dp1_penc5_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(37)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[36:0]),
  .in1(din1[36:0]),
  .in2(din2[36:0]),
  .in3(din3[36:0]),
  .in4(din4[36:0]),
.dout(dout[36:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_msff_macro__left_1__stack_38l__width_37 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [35:0] so;

  input [36:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [36:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


//
//   buff macro
//
//


module lsu_sbd_dp_buff_macro__left_1__rep_1__stack_38l__width_37 (
  din, 
  dout);
  input [36:0] din;
  output [36:0] dout;


buff #(37)  d0_0 (
.in(din[36:0]),
.out(dout[36:0])
);


endmodule


//
//   buff macro
//
//


module lsu_sbd_dp_buff_macro__left_10__rep_1__stack_40c__width_27 (
  din, 
  dout);
  input [26:0] din;
  output [26:0] dout;


buff #(27)  d0_0 (
.in(din[26:0]),
.out(dout[26:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbd_dp_msff_macro__left_4__minbuff_1__stack_38l__width_34 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [32:0] so;

  input [33:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [33:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(34)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[33:0]),
.si({scan_in,so[32:0]}),
.so({so[32:0],scan_out}),
.q(dout[33:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_sbs_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_sbs_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  sbc_cam_wvld_m, 
  sbc_st_sel_p3, 
  sbc_bst_sel, 
  sbc_rmo_st_b, 
  sbc_st_addr_new, 
  sbc_bst_b, 
  sbc_bst_in_prog_b, 
  sbc_fgu_ecc_b, 
  sbc_bst_rd_err, 
  sbc_sbs_kill_store_p4_, 
  sbc_tte_vld_b, 
  sbc_blk_inst_b, 
  dec_flush_lm, 
  dec_flush_lb, 
  tlu_flush_lsu_b, 
  spd_st_line_match, 
  dcc_asi_store_b, 
  dcc_asi_iomap_b, 
  dcc_asi_rngf_b, 
  dcc_asi_indet_b, 
  dcc_sync_inst_w, 
  dcc_casa_inst_b, 
  dcc_pst_asi_b, 
  dcc_st_rq_type_w, 
  dcc_exception_flush_b, 
  tlb_tte_ie_b, 
  cic_st_ack, 
  cic_st_dequeue, 
  cic_rmo_dequeue, 
  pic_st_sel_p3, 
  dcc_asi_rtn_vld, 
  dcc_asi_rtn_excp, 
  dcc_asi_rtn_rd, 
  lsu_lsu_pmen_, 
  sbs_stb_wptr_m, 
  sbs_stb_rptr, 
  sbs_pcx_rq_vld, 
  sbs_atm_rq_vld, 
  sbs_asi_rq_vld, 
  sbs_state_vld, 
  sbs_state_ced, 
  sbs_state_asi_rngf, 
  sbs_pcx_pst_ie_p4, 
  sbs_all_commited, 
  sbs_stb_empty, 
  sbs_stb_full, 
  sbs_bst_req, 
  sbs_sync, 
  sbs_asi_indet_req, 
  sbs_asi_indet_retire, 
  sbs_rmo_st_p4, 
  sbs_blk_st_p4, 
  sbs_st_type, 
  lsu_stb_alloc, 
  lsu_stb_dealloc, 
  lsu_block_store_kill, 
  lsu_stb_empty);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire sbs_clken;
wire stb_cam_wvld_b;
wire stb_alloc_w;
wire bst_pend;
wire l1clk;
wire l1clk_pm1;
wire dff_flush_b_scanin;
wire dff_flush_b_scanout;
wire pipe_flush_b;
wire flush_b;
wire dff_flush_w_scanin;
wire dff_flush_w_scanout;
wire flush_w;
wire dff_cam_wvld_b_scanin;
wire dff_cam_wvld_b_scanout;
wire kill_store_p4;
wire st_commit_p4;
wire dff_st_dq_scanin;
wire dff_st_dq_scanout;
wire block_store_kill;
wire st_dequeue_d1;
wire kill_store_p5;
wire [7:0] dec_rptr_pcx;
wire [7:0] dec_stb_rptr;
wire [7:0] stb_state_vld;
wire [7:0] stb_state_ced;
wire [7:0] stb_state_ack;
wire [7:0] stb_state_mem;
wire [7:0] stb_state_rmo;
wire [7:0] stb_state_asi;
wire [7:0] dec_dqptr;
wire [4:0] rmo_count;
wire sbs_rmo_st;
wire bst_err;
wire [7:0] stb_state_cas;
wire [3:0] stb_rptr_inc;
wire [3:0] stb_rptr;
wire [3:0] stb_rptr_in;
wire stb_commit_entry;
wire flush_bst_inst;
wire bst_kill;
wire dff_rptr_scanin;
wire dff_rptr_scanout;
wire [3:0] stb_wptr_incr;
wire [3:0] stb_wptr;
wire flush_st_w;
wire [3:0] stb_wptr_decr;
wire [3:0] stb_wptr_in;
wire dff_wptr_scanin;
wire dff_wptr_scanout;
wire dff_wptr_b_scanin;
wire dff_wptr_b_scanout;
wire [2:0] stb_wptr_b;
wire [7:0] dec_wptr_b;
wire dff_wptr_w_scanin;
wire dff_wptr_w_scanout;
wire [2:0] stb_wptr_w;
wire [7:0] dec_wptr_w;
wire stb_empty;
wire rmo_st_commit_p4;
wire sbs_last_entry;
wire stb_flush_state;
wire [2:0] dqptr_in;
wire stb_flush_done;
wire [2:0] dqptr;
wire dff_dqptr_scanin;
wire dff_dqptr_scanout;
wire [7:0] stb_state_rst;
wire rmo_st_commit_p3;
wire set_valid_b;
wire [7:0] stb_state_vld_set;
wire [7:0] stb_state_vld_din;
wire dff_stb_vld_scanin;
wire dff_stb_vld_scanout;
wire [7:0] stb_state_vld_out;
wire set_valid_w;
wire [7:0] misc_state_wr;
wire stb_alloc_b;
wire dff_stb_alloc_w_scanin;
wire dff_stb_alloc_w_scanout;
wire st_commit_p3;
wire dff_st_commit_p4_scanin;
wire dff_st_commit_p4_scanout;
wire [7:0] stb_state_ced_set;
wire [7:0] stb_state_ced_din;
wire dff_stb_ced_scanin;
wire dff_stb_ced_scanout;
wire [2:0] ackptr_in;
wire [2:0] ackptr;
wire dff_ackptr_scanin;
wire dff_ackptr_scanout;
wire [7:0] dec_ackptr;
wire [7:0] stb_state_ack_set;
wire pipe_store_w;
wire [7:0] stb_state_ack_rst;
wire [7:0] stb_state_ack_din;
wire dff_stb_ack_scanin;
wire dff_stb_ack_scanout;
wire dff_asi_w_scanin;
wire dff_asi_w_scanout;
wire asi_store_w;
wire asi_rngf_w;
wire rmo_st_w;
wire last_st_asi;
wire last_st_asi_d1;
wire last_asi_ring;
wire last_asi_ring_d1;
wire last_st_rmo;
wire last_st_rmo_d1;
wire dff_asi_pipe_scanin;
wire dff_asi_pipe_scanout;
wire pipe_store_b;
wire [2:0] sbs_state_in;
wire [2:0] stb_state_0_din;
wire [2:0] sbs_state_0;
wire [2:0] stb_state_1_din;
wire [2:0] sbs_state_1;
wire [2:0] stb_state_2_din;
wire [2:0] sbs_state_2;
wire [2:0] stb_state_3_din;
wire [2:0] sbs_state_3;
wire [2:0] stb_state_4_din;
wire [2:0] sbs_state_4;
wire [2:0] stb_state_5_din;
wire [2:0] sbs_state_5;
wire [2:0] stb_state_6_din;
wire [2:0] sbs_state_6;
wire [2:0] stb_state_7_din;
wire [2:0] sbs_state_7;
wire dff_state_0_scanin;
wire dff_state_0_scanout;
wire dff_state_1_scanin;
wire dff_state_1_scanout;
wire dff_state_2_scanin;
wire dff_state_2_scanout;
wire dff_state_3_scanin;
wire dff_state_3_scanout;
wire dff_state_4_scanin;
wire dff_state_4_scanout;
wire dff_state_5_scanin;
wire dff_state_5_scanout;
wire dff_state_6_scanin;
wire dff_state_6_scanout;
wire dff_state_7_scanin;
wire dff_state_7_scanout;
wire sbs_blk_st;
wire [7:0] stb_state_indet;
wire asi_error;
wire sync_state;
wire sync_state_out;
wire sync_state_rst;
wire sync_state_in;
wire dff_sync_state_scanin;
wire dff_sync_state_scanout;
wire trap_sync;
wire dff_sbs_sync_scanin;
wire dff_sbs_sync_scanout;
wire bst_pend_in;
wire bst_w;
wire dff_bst_pend_scanin;
wire dff_bst_pend_scanout;
wire bst_pend_out;
wire blk_inst_w;
wire dff_bst_err_scanin;
wire dff_bst_err_scanout;
wire bst_err_next;
wire [4:0] rmo_count_dec;
wire [4:0] rmo_count_in;
wire blk_st_commit_p3;
wire dff_rmo_count_scanin;
wire dff_rmo_count_scanout;
wire [4:0] rmo_count_out;
wire blk_st_commit_p4;
wire dff_rmo_commit_scanin;
wire dff_rmo_commit_scanout;
wire rmo_st_commit_p5;
wire rmo_commit_p5;
wire pst_ie_b;
wire dff_pst_ie_scanin;
wire dff_pst_ie_scanout;
wire pst_ie_in;
wire pst_ie_w;
wire pst_ie;
wire [1:0] st_type_in;
wire [1:0] st_type;
wire dff_st_type_scanin;
wire dff_st_type_scanout;
wire stb_flush_set;
wire stb_flush_clr;
wire stb_flush_in;
wire dff_stb_flush_scanin;
wire dff_stb_flush_scanout;
wire spares_scanin;
wire spares_scanout;


input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input		sbc_cam_wvld_m;		// CAM is writing for this thread
input		sbc_st_sel_p3;		// This thread was selected (not ld/st P3 qualified)
input		sbc_bst_sel;
input		sbc_rmo_st_b;
input		sbc_st_addr_new;
input		sbc_bst_b;		// signals block store for this thread
input		sbc_bst_in_prog_b;	// signals block store for any thread
input		sbc_fgu_ecc_b;		// FRF ECC error in B (only used for block store)
input		sbc_bst_rd_err;		// FRF ECC error in B (only used for block store)
input		sbc_sbs_kill_store_p4_;
input		sbc_tte_vld_b;		// tlb_miss not accounted for 
input		sbc_blk_inst_b;

input		dec_flush_lm;
input		dec_flush_lb;
input		tlu_flush_lsu_b;

input		spd_st_line_match;	// Store in B is to same line as previous

input		dcc_asi_store_b;
input		dcc_asi_iomap_b;
input		dcc_asi_rngf_b;
input		dcc_asi_indet_b;
input		dcc_sync_inst_w;
input		dcc_casa_inst_b;
input		dcc_pst_asi_b;
input	[1:0]	dcc_st_rq_type_w;
input		dcc_exception_flush_b;

input		tlb_tte_ie_b;

input		cic_st_ack;		// Store from this thread is acked
input		cic_st_dequeue;		// Dequeue the store from this thread.
input		cic_rmo_dequeue;	// RMO ack received

input		pic_st_sel_p3;		// Store wins ld/st arbitration in P3

input		dcc_asi_rtn_vld;
input		dcc_asi_rtn_excp;
input		dcc_asi_rtn_rd;

input		lsu_lsu_pmen_;

output	[2:0]	sbs_stb_wptr_m;	
output	[2:0]	sbs_stb_rptr;	
output		sbs_pcx_rq_vld;
output		sbs_atm_rq_vld;
output		sbs_asi_rq_vld;
output	[7:0]	sbs_state_vld;
output	[7:0]	sbs_state_ced;
output		sbs_state_asi_rngf;
output		sbs_pcx_pst_ie_p4;
output		sbs_all_commited;
output		sbs_stb_empty;
output		sbs_stb_full;
output		sbs_bst_req;
output		sbs_sync;
output		sbs_asi_indet_req;	// Indeterminate ASI store selected for issue
output		sbs_asi_indet_retire;	// Indeterminate ASI store retired
output		sbs_rmo_st_p4;
output		sbs_blk_st_p4;
output	[1:0]	sbs_st_type;

output		lsu_stb_alloc;
output		lsu_stb_dealloc;
output		lsu_block_store_kill;
output		lsu_stb_empty;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

//////////////////////////////////////////
// Clock header and power mangagement
//////////////////////////////////////////

// Clocks run when a store is in M/B/W of the pipe and anytime the store buffer is not empty
assign sbs_clken = sbc_cam_wvld_m | stb_cam_wvld_b | stb_alloc_w | bst_pend | ~sbs_stb_empty | lsu_lsu_pmen_;

lsu_sbs_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk),
        .l1en   (1'b1 ),
        .l1clk  (l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

lsu_sbs_ctl_l1clkhdr_ctl_macro clkgenpm (
        .l2clk  (l2clk    ),
        .l1en   (sbs_clken),
        .l1clk  (l1clk_pm1 ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

//////////////////////////////
// Flush logic
//////////////////////////////

lsu_sbs_ctl_msff_ctl_macro__width_1 dff_flush_b  (
	.scan_in(dff_flush_b_scanin),
	.scan_out(dff_flush_b_scanout),
	.din	(dec_flush_lm),
	.dout	(pipe_flush_b),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign flush_b = tlu_flush_lsu_b | dec_flush_lb | pipe_flush_b | dcc_exception_flush_b;

lsu_sbs_ctl_msff_ctl_macro__width_1 dff_flush_w  (
	.scan_in(dff_flush_w_scanin),
	.scan_out(dff_flush_w_scanout),
	.din	(flush_b),
	.dout	(flush_w),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////

lsu_sbs_ctl_msff_ctl_macro__width_1 dff_cam_wvld_b  (
	.scan_in(dff_cam_wvld_b_scanin),
	.scan_out(dff_cam_wvld_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(sbc_cam_wvld_m),
	.dout	(stb_cam_wvld_b),
  .siclk(siclk),
  .soclk(soclk)
);

assign kill_store_p4 = st_commit_p4 & ~sbc_sbs_kill_store_p4_;

lsu_sbs_ctl_msff_ctl_macro__width_3 dff_st_dq  (
	.scan_in(dff_st_dq_scanin),
	.scan_out(dff_st_dq_scanout),
	.din	({(cic_st_dequeue | dcc_asi_rtn_vld & ~dcc_asi_rtn_rd),kill_store_p4,block_store_kill}),
	.dout	({st_dequeue_d1,                                       kill_store_p5,lsu_block_store_kill}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Assertion to check for STB overflow
// 0in multi_enq_deq_fifo -enq stb_cam_wvld_b -deq flush_st_w lsu_stb_dealloc bst_kill bst_kill bst_kill bst_kill bst_kill bst_kill bst_kill bst_kill (kill_store_p4 & ~(rmo_st_commit_p4 & ~stb_flush_state) & ~sbc_bst_sel) flush_bst_inst -depth 8

////////////////////////////////////////////////////////////////////////////////
// STB Read Pointer
////////////////////////////////////////////////////////////////////////////////
// A store can be sent to the pcx if the previous entry has been acked, or if 
// the it is addressed to the same L2 cache line (addr[39:6]) as the previous
// store.  Stores to IO cannot be pipelined.  Conditions for release are
// (1) Entry is valid and not already sent to pcx. AND
// (2) Previous entry is invalid or
// (3) Previous entry is valid and 
//  (a) mem store - prev. entry is acked OR (non-rmo only)
//  (b) asi store - prev. entry is asi and acked
//     If a store can be pipelined, the ack for the previous store will be set.
// The dec_dqptr term at the end is to prevent a deadlock condition where
// all entries are valid but none have been committed.

// Timing : this is very critical.  Some improvement could be made by
// decoding dec_stb_rptr and/or dec_dqptr in the previous cycle.
assign dec_rptr_pcx[7:0] =
         dec_stb_rptr[7:0] & stb_state_vld[7:0] & ~stb_state_ced[7:0] &		// --> (1)
          (~{stb_state_vld[6:0],stb_state_vld[7]} |				// --> (2)
           ({stb_state_vld[6:0],stb_state_vld[7]} &				// --> (3)
            {stb_state_ack[6:0],stb_state_ack[7]} &
            (stb_state_mem[7:0] & ~stb_state_rmo[7:0]) |			// --> (3a)
            (stb_state_asi[7:0] & {stb_state_asi[6:0],stb_state_asi[7]}) 	// --> (3b)
           ) |		
            dec_dqptr[7:0]);

// Max number of RMO stores outstanding is 8.  When 8 are out, rmo stores are blocked.
assign sbs_pcx_rq_vld = |(dec_rptr_pcx[7:0] & stb_state_mem[7:0]) & ~(rmo_count[4] & sbs_rmo_st) & ~bst_err;
assign sbs_atm_rq_vld = |(dec_rptr_pcx[7:0] & stb_state_cas[7:0]);
assign sbs_asi_rq_vld = |(dec_rptr_pcx[7:0] & stb_state_asi[7:0]);

assign stb_rptr_inc[3:0] = stb_rptr[3:0] + 4'b0001;

// Bit 3 must "wrap" when the buffer is flushed on a bst_kill error
assign stb_rptr_in[3] = ((stb_commit_entry | flush_bst_inst) ? stb_rptr_inc[3] : stb_rptr[3]) ^ bst_kill;
assign stb_rptr_in[2:0] = (stb_commit_entry | flush_bst_inst) ? stb_rptr_inc[2:0] : stb_rptr[2:0];

lsu_sbs_ctl_msff_ctl_macro__width_4 dff_rptr  (
	.scan_in(dff_rptr_scanin),
	.scan_out(dff_rptr_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_rptr_in[3:0]),
	.dout	(stb_rptr[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbs_stb_rptr[2:0] = stb_rptr[2:0];

assign dec_stb_rptr[0] = ~stb_rptr[2] & ~stb_rptr[1] & ~stb_rptr[0];
assign dec_stb_rptr[1] = ~stb_rptr[2] & ~stb_rptr[1] &  stb_rptr[0];
assign dec_stb_rptr[2] = ~stb_rptr[2] &  stb_rptr[1] & ~stb_rptr[0];
assign dec_stb_rptr[3] = ~stb_rptr[2] &  stb_rptr[1] &  stb_rptr[0];
assign dec_stb_rptr[4] =  stb_rptr[2] & ~stb_rptr[1] & ~stb_rptr[0];
assign dec_stb_rptr[5] =  stb_rptr[2] & ~stb_rptr[1] &  stb_rptr[0];
assign dec_stb_rptr[6] =  stb_rptr[2] &  stb_rptr[1] & ~stb_rptr[0];
assign dec_stb_rptr[7] =  stb_rptr[2] &  stb_rptr[1] &  stb_rptr[0];

////////////////////////////////////////////////////////////////////////////////
// STB Write Pointer
////////////////////////////////////////////////////////////////////////////////

// A valid entry causes the pointer to increment.
// A flushed store instruction decrements the pointer.

assign stb_wptr_incr[3:0] = stb_wptr[3:0] + {3'b000,~flush_st_w};
assign stb_wptr_decr[3:0] = stb_wptr[3:0] - {3'b000,flush_st_w};

assign stb_wptr_in[3:0] = sbc_cam_wvld_m ? stb_wptr_incr[3:0] : stb_wptr_decr[3:0];

lsu_sbs_ctl_msff_ctl_macro__width_4 dff_wptr  (
	.scan_in(dff_wptr_scanin),
	.scan_out(dff_wptr_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_wptr_in[3:0]),
	.dout	(stb_wptr[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbs_stb_wptr_m[2:0] = stb_wptr[2:0];

lsu_sbs_ctl_msff_ctl_macro__width_3 dff_wptr_b  (
	.scan_in(dff_wptr_b_scanin),
	.scan_out(dff_wptr_b_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_wptr[2:0]),
	.dout	(stb_wptr_b[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_wptr_b[0] = ~stb_wptr_b[2] & ~stb_wptr_b[1] & ~stb_wptr_b[0];
assign dec_wptr_b[1] = ~stb_wptr_b[2] & ~stb_wptr_b[1] &  stb_wptr_b[0];
assign dec_wptr_b[2] = ~stb_wptr_b[2] &  stb_wptr_b[1] & ~stb_wptr_b[0];
assign dec_wptr_b[3] = ~stb_wptr_b[2] &  stb_wptr_b[1] &  stb_wptr_b[0];
assign dec_wptr_b[4] =  stb_wptr_b[2] & ~stb_wptr_b[1] & ~stb_wptr_b[0];
assign dec_wptr_b[5] =  stb_wptr_b[2] & ~stb_wptr_b[1] &  stb_wptr_b[0];
assign dec_wptr_b[6] =  stb_wptr_b[2] &  stb_wptr_b[1] & ~stb_wptr_b[0];
assign dec_wptr_b[7] =  stb_wptr_b[2] &  stb_wptr_b[1] &  stb_wptr_b[0];

lsu_sbs_ctl_msff_ctl_macro__width_3 dff_wptr_w  (
	.scan_in(dff_wptr_w_scanin),
	.scan_out(dff_wptr_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_wptr_b[2:0]),
	.dout	(stb_wptr_w[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_wptr_w[0] = ~stb_wptr_w[2] & ~stb_wptr_w[1] & ~stb_wptr_w[0];
assign dec_wptr_w[1] = ~stb_wptr_w[2] & ~stb_wptr_w[1] &  stb_wptr_w[0];
assign dec_wptr_w[2] = ~stb_wptr_w[2] &  stb_wptr_w[1] & ~stb_wptr_w[0];
assign dec_wptr_w[3] = ~stb_wptr_w[2] &  stb_wptr_w[1] &  stb_wptr_w[0];
assign dec_wptr_w[4] =  stb_wptr_w[2] & ~stb_wptr_w[1] & ~stb_wptr_w[0];
assign dec_wptr_w[5] =  stb_wptr_w[2] & ~stb_wptr_w[1] &  stb_wptr_w[0];
assign dec_wptr_w[6] =  stb_wptr_w[2] &  stb_wptr_w[1] & ~stb_wptr_w[0];
assign dec_wptr_w[7] =  stb_wptr_w[2] &  stb_wptr_w[1] &  stb_wptr_w[0];

assign stb_empty = ~|(stb_state_vld[7:0]) & (rmo_count[4:0] == 5'd0) & ~rmo_st_commit_p4;
assign sbs_stb_empty = stb_empty & ~bst_pend & ~(sbc_cam_wvld_m | stb_cam_wvld_b | stb_alloc_w);
assign lsu_stb_empty = stb_empty & ~bst_pend;

// Might be able to speed this up by comparing stb_wptr_decr == stb_rptr_inc
// in previous cycle and flopping down.  I'd still have to deal with the
// stb_flush_done part though.
assign sbs_last_entry = (stb_wptr[3:0] == stb_rptr[3:0]);

assign sbs_stb_full = &(stb_state_vld[7:0]);

////////////////////////////////////////////////////////////////////////////////
// Control state
////////////////////////////////////////////////////////////////////////////////

// State is reset when an entry is dequeued and when a store gets flushed.
// 0in bits_on -var {st_dequeue_d1,(rmo_st_commit_p4 & ~stb_flush_state)} -max 1 -message "multiple stores retiring simultaneously"
assign lsu_stb_dealloc = st_dequeue_d1 | (rmo_st_commit_p4 & ~stb_flush_state); 

assign dqptr_in[2:0] = stb_flush_done ? stb_wptr[2:0] : (dqptr[2:0] + {2'b00, lsu_stb_dealloc});

lsu_sbs_ctl_msff_ctl_macro__width_3 dff_dqptr  (
	.scan_in(dff_dqptr_scanin),
	.scan_out(dff_dqptr_scanout),
	.din	(dqptr_in[2:0]),
	.dout	(dqptr[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
assign dec_dqptr[0] = ~dqptr[2] & ~dqptr[1] & ~dqptr[0];
assign dec_dqptr[1] = ~dqptr[2] & ~dqptr[1] &  dqptr[0];
assign dec_dqptr[2] = ~dqptr[2] &  dqptr[1] & ~dqptr[0];
assign dec_dqptr[3] = ~dqptr[2] &  dqptr[1] &  dqptr[0];
assign dec_dqptr[4] =  dqptr[2] & ~dqptr[1] & ~dqptr[0];
assign dec_dqptr[5] =  dqptr[2] & ~dqptr[1] &  dqptr[0];
assign dec_dqptr[6] =  dqptr[2] &  dqptr[1] & ~dqptr[0];
assign dec_dqptr[7] =  dqptr[2] &  dqptr[1] &  dqptr[0];

assign stb_state_rst[7:0] = ({8{st_dequeue_d1}}                  & dec_dqptr[7:0]) | 
                            ({8{rmo_st_commit_p3}}               & dec_stb_rptr[7:0]) | 
                            ({dec_stb_rptr[0],dec_stb_rptr[7:1]} & {8{kill_store_p5}}) |
                            (dec_wptr_w[7:0]                     & {8{flush_st_w}}) |
                            {8{bst_kill}};

// Valid state. Set when a store is written to the STB.  Cleared when the store
//		updates the cache.  The valid state is set in W.  If the store
//              in W must be flushed, disqualify the valid bit and reset the state.

assign set_valid_b = stb_cam_wvld_b & ~sbc_blk_inst_b;

assign stb_state_vld_set[7:0] = dec_wptr_b[7:0] & {8{set_valid_b}};

assign stb_state_vld_din[7:0] = stb_state_vld_set[7:0] |
				 (~stb_state_rst[7:0] & stb_state_vld[7:0]);

lsu_sbs_ctl_msff_ctl_macro__width_9 dff_stb_vld  (
	.scan_in(dff_stb_vld_scanin),
	.scan_out(dff_stb_vld_scanout),
	.l1clk	(l1clk_pm1),
	.din	({stb_state_vld_din[7:0],set_valid_b}),
	.dout	({stb_state_vld_out[7:0],    set_valid_w}),
  .siclk(siclk),
  .soclk(soclk)
);
assign stb_state_vld[7:0] = stb_state_vld_out[7:0] & ~({8{flush_st_w}} & dec_wptr_w[7:0]);

// Used for enabling CAM lookup on the next cycle
assign sbs_state_vld[7:0] = stb_state_mem[7:0] | (misc_state_wr[7:0] & {8{~dcc_asi_store_b}});

assign stb_alloc_b = stb_cam_wvld_b;

lsu_sbs_ctl_msff_ctl_macro__width_1 dff_stb_alloc_w  (
	.scan_in(dff_stb_alloc_w_scanin),
	.scan_out(dff_stb_alloc_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_alloc_b),
	.dout	(stb_alloc_w),
  .siclk(siclk),
  .soclk(soclk)
);
assign lsu_stb_alloc = stb_alloc_w & ~flush_w;
assign flush_st_w = stb_alloc_w & flush_w;


// Commited State. Set when a store is issued to the pcx.

// 0in bits_on -var {(sbc_st_sel_p3 & pic_st_sel_p3),sbc_bst_sel,flush_bst_inst} -max 1 -message "multiple stores commiting"

assign flush_bst_inst = bst_pend & stb_flush_state & stb_empty & ~(sbc_cam_wvld_m | stb_cam_wvld_b | stb_alloc_w);

assign stb_commit_entry = (sbc_st_sel_p3 & pic_st_sel_p3) | sbc_bst_sel;

assign st_commit_p3 = sbc_st_sel_p3 & pic_st_sel_p3;
lsu_sbs_ctl_msff_ctl_macro__width_1 dff_st_commit_p4  (
	.scan_in(dff_st_commit_p4_scanin),
	.scan_out(dff_st_commit_p4_scanout),
	.l1clk	(l1clk_pm1),
	.din	(st_commit_p3),
	.dout	(st_commit_p4),
  .siclk(siclk),
  .soclk(soclk)
);


assign stb_state_ced_set[7:0] = dec_stb_rptr[7:0] & {8{stb_commit_entry}};

assign stb_state_ced_din[7:0] = ~stb_state_rst[7:0] &
                                  (stb_state_ced_set[7:0] | stb_state_ced[7:0]);

lsu_sbs_ctl_msff_ctl_macro__width_8 dff_stb_ced  (
	.scan_in(dff_stb_ced_scanin),
	.scan_out(dff_stb_ced_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_ced_din[7:0]),
	.dout	(stb_state_ced[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbs_state_ced[7:0] = stb_state_ced[7:0];
assign sbs_all_commited = &(~stb_state_vld[7:0] | stb_state_ced[7:0]);

// Acked State. Set when a store ack is received from the CPX.  We do not have
//              to wait for the ack to reach the head of the CPQ since the
//              arrival on the CPX means the L2 has the store and will enforce
//              ordering requirements.
//		Ack state is automatically set when the "next" store can
//		be pipelined.  Ack state is cleared when a store is first
//		written to prevent stray acks.

// 0in bits_on -var {cic_st_ack,sbc_bst_sel,(rmo_st_commit_p4 & ~stb_flush_state),(dcc_asi_rtn_vld & ~dcc_asi_rtn_rd)} -max 1 -message "multiple acks received"
assign ackptr_in[2:0] = stb_flush_done ? stb_wptr[2:0] : 
             (ackptr[2:0] + {2'b00, (cic_st_ack | (dcc_asi_rtn_vld & ~dcc_asi_rtn_rd) | sbc_bst_sel | rmo_st_commit_p4)});

lsu_sbs_ctl_msff_ctl_macro__width_3 dff_ackptr  (
	.scan_in(dff_ackptr_scanin),
	.scan_out(dff_ackptr_scanout),
	.din	(ackptr_in[2:0]),
	.dout	(ackptr[2:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_ackptr[0] = ~ackptr[2] & ~ackptr[1] & ~ackptr[0];
assign dec_ackptr[1] = ~ackptr[2] & ~ackptr[1] &  ackptr[0];
assign dec_ackptr[2] = ~ackptr[2] &  ackptr[1] & ~ackptr[0];
assign dec_ackptr[3] = ~ackptr[2] &  ackptr[1] &  ackptr[0];
assign dec_ackptr[4] =  ackptr[2] & ~ackptr[1] & ~ackptr[0];
assign dec_ackptr[5] =  ackptr[2] & ~ackptr[1] &  ackptr[0];
assign dec_ackptr[6] =  ackptr[2] &  ackptr[1] & ~ackptr[0];
assign dec_ackptr[7] =  ackptr[2] &  ackptr[1] &  ackptr[0];

assign stb_state_ack_set[7:0] = (dec_ackptr[7:0] & {8{cic_st_ack | (dcc_asi_rtn_vld & ~dcc_asi_rtn_rd)}}) |
                                ({dec_wptr_w[0],dec_wptr_w[7:1]} & {8{pipe_store_w & set_valid_w & ~flush_w}});

assign stb_state_ack_rst[7:0] = stb_state_rst[7:0] | (dec_wptr_b[7:0] & {8{stb_cam_wvld_b}});

assign stb_state_ack_din[7:0] = ~stb_state_ack_rst[7:0] & (stb_state_ack_set[7:0] | stb_state_ack[7:0]);

lsu_sbs_ctl_msff_ctl_macro__width_8 dff_stb_ack  (
	.scan_in(dff_stb_ack_scanin),
	.scan_out(dff_stb_ack_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_ack_din[7:0]),
	.dout	(stb_state_ack[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Stores are pipelinable if they are to the same L2 cache line,
// to the same ring for ASI stores, and they are not IO stores.

lsu_sbs_ctl_msff_ctl_macro__width_3 dff_asi_w  (
	.scan_in(dff_asi_w_scanin),
	.scan_out(dff_asi_w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dcc_asi_store_b,dcc_asi_rngf_b,sbc_rmo_st_b}),
	.dout	({asi_store_w,    asi_rngf_w,    rmo_st_w}),
  .siclk(siclk),
  .soclk(soclk)
);

assign last_st_asi   = sbc_st_addr_new ? asi_store_w : last_st_asi_d1  ;
assign last_asi_ring = sbc_st_addr_new ? asi_rngf_w  : last_asi_ring_d1;
assign last_st_rmo   = sbc_st_addr_new ? rmo_st_w    : last_st_rmo_d1  ;

lsu_sbs_ctl_msff_ctl_macro__width_4 dff_asi_pipe  (
	.scan_in(dff_asi_pipe_scanin),
	.scan_out(dff_asi_pipe_scanout),
	.l1clk	(l1clk_pm1),
	.din	({last_st_asi,last_asi_ring,      last_st_rmo,   pipe_store_b}),
	.dout	({last_st_asi_d1,last_asi_ring_d1,last_st_rmo_d1,pipe_store_w}),
  .siclk(siclk),
  .soclk(soclk)
);

assign pipe_store_b = (dcc_asi_store_b ~^ last_st_asi) &			// asi/non-asi must match
                      (sbc_rmo_st_b ~^ last_st_rmo) &				// rmo must match
                      ~dcc_asi_indet_b &					// indeterminate ASI's never pipeline
                      ~dcc_asi_iomap_b &					// iomapped ASI's never pipeline
                      ((~dcc_asi_store_b & spd_st_line_match) |			// non-asi must be same L2 line
                       (dcc_asi_store_b & (last_asi_ring ~^ dcc_asi_rngf_b)));	// asi must be same ring

////////////////////////////////////////////////////////////////////////////////
// Misc information. The information differs between asi and non-asi stores
//              2      1     0
// ASI     |   1'b0 | ind | fast |
//
//              2      1     0
// non-ASI |   1'b1 | CAS | rmo  |
//
// Use [2:0] = 111 to signal a block store type
////////////////////////////////////////////////////////////////////////////////

assign misc_state_wr[7:0] = dec_wptr_b[7:0] & {8{stb_cam_wvld_b & ~sbc_blk_inst_b}};

assign sbs_state_in[2:0] = (dcc_asi_store_b & ~dcc_asi_iomap_b) ? 
     {1'b0,dcc_asi_indet_b,dcc_asi_rngf_b} :
     {1'b1,(dcc_casa_inst_b | sbc_bst_b),sbc_rmo_st_b};

assign stb_state_0_din[2:0] = {3{~stb_state_rst[0]}} & (misc_state_wr[0] ? sbs_state_in[2:0] : sbs_state_0[2:0]);
assign stb_state_1_din[2:0] = {3{~stb_state_rst[1]}} & (misc_state_wr[1] ? sbs_state_in[2:0] : sbs_state_1[2:0]);
assign stb_state_2_din[2:0] = {3{~stb_state_rst[2]}} & (misc_state_wr[2] ? sbs_state_in[2:0] : sbs_state_2[2:0]);
assign stb_state_3_din[2:0] = {3{~stb_state_rst[3]}} & (misc_state_wr[3] ? sbs_state_in[2:0] : sbs_state_3[2:0]);
assign stb_state_4_din[2:0] = {3{~stb_state_rst[4]}} & (misc_state_wr[4] ? sbs_state_in[2:0] : sbs_state_4[2:0]);
assign stb_state_5_din[2:0] = {3{~stb_state_rst[5]}} & (misc_state_wr[5] ? sbs_state_in[2:0] : sbs_state_5[2:0]);
assign stb_state_6_din[2:0] = {3{~stb_state_rst[6]}} & (misc_state_wr[6] ? sbs_state_in[2:0] : sbs_state_6[2:0]);
assign stb_state_7_din[2:0] = {3{~stb_state_rst[7]}} & (misc_state_wr[7] ? sbs_state_in[2:0] : sbs_state_7[2:0]);

lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_0  (
	.scan_in(dff_state_0_scanin),
	.scan_out(dff_state_0_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_0_din[2:0]),
	.dout	(sbs_state_0[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_1  (
	.scan_in(dff_state_1_scanin),
	.scan_out(dff_state_1_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_1_din[2:0]),
	.dout	(sbs_state_1[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_2  (
	.scan_in(dff_state_2_scanin),
	.scan_out(dff_state_2_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_2_din[2:0]),
	.dout	(sbs_state_2[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_3  (
	.scan_in(dff_state_3_scanin),
	.scan_out(dff_state_3_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_3_din[2:0]),
	.dout	(sbs_state_3[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_4  (
	.scan_in(dff_state_4_scanin),
	.scan_out(dff_state_4_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_4_din[2:0]),
	.dout	(sbs_state_4[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_5  (
	.scan_in(dff_state_5_scanin),
	.scan_out(dff_state_5_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_5_din[2:0]),
	.dout	(sbs_state_5[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_6  (
	.scan_in(dff_state_6_scanin),
	.scan_out(dff_state_6_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_6_din[2:0]),
	.dout	(sbs_state_6[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);
lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_7  (
	.scan_in(dff_state_7_scanin),
	.scan_out(dff_state_7_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_state_7_din[2:0]),
	.dout	(sbs_state_7[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign stb_state_mem[7:0] = {sbs_state_7[2],sbs_state_6[2],sbs_state_5[2],sbs_state_4[2],
                             sbs_state_3[2],sbs_state_2[2],sbs_state_1[2],sbs_state_0[2]};
assign stb_state_asi[7:0] = ~stb_state_mem[7:0];

assign sbs_state_asi_rngf = (dec_stb_rptr[0] & sbs_state_0[0]) |
                            (dec_stb_rptr[1] & sbs_state_1[0]) |
                            (dec_stb_rptr[2] & sbs_state_2[0]) |
                            (dec_stb_rptr[3] & sbs_state_3[0]) |
                            (dec_stb_rptr[4] & sbs_state_4[0]) |
                            (dec_stb_rptr[5] & sbs_state_5[0]) |
                            (dec_stb_rptr[6] & sbs_state_6[0]) |
                            (dec_stb_rptr[7] & sbs_state_7[0]);

assign sbs_rmo_st = (dec_stb_rptr[0] & stb_state_mem[0] & sbs_state_0[0]) |
                    (dec_stb_rptr[1] & stb_state_mem[1] & sbs_state_1[0]) |
                    (dec_stb_rptr[2] & stb_state_mem[2] & sbs_state_2[0]) |
                    (dec_stb_rptr[3] & stb_state_mem[3] & sbs_state_3[0]) |
                    (dec_stb_rptr[4] & stb_state_mem[4] & sbs_state_4[0]) |
                    (dec_stb_rptr[5] & stb_state_mem[5] & sbs_state_5[0]) |
                    (dec_stb_rptr[6] & stb_state_mem[6] & sbs_state_6[0]) |
                    (dec_stb_rptr[7] & stb_state_mem[7] & sbs_state_7[0]) ;

assign stb_state_rmo[7:0] = {sbs_state_7[0],sbs_state_6[0],sbs_state_5[0],sbs_state_4[0],
                             sbs_state_3[0],sbs_state_2[0],sbs_state_1[0],sbs_state_0[0]};

assign sbs_blk_st = (dec_stb_rptr[0] & stb_state_mem[0] & sbs_state_0[1] & sbs_state_0[0]) |
                    (dec_stb_rptr[1] & stb_state_mem[1] & sbs_state_1[1] & sbs_state_1[0]) |
                    (dec_stb_rptr[2] & stb_state_mem[2] & sbs_state_2[1] & sbs_state_2[0]) |
                    (dec_stb_rptr[3] & stb_state_mem[3] & sbs_state_3[1] & sbs_state_3[0]) |
                    (dec_stb_rptr[4] & stb_state_mem[4] & sbs_state_4[1] & sbs_state_4[0]) |
                    (dec_stb_rptr[5] & stb_state_mem[5] & sbs_state_5[1] & sbs_state_5[0]) |
                    (dec_stb_rptr[6] & stb_state_mem[6] & sbs_state_6[1] & sbs_state_6[0]) |
                    (dec_stb_rptr[7] & stb_state_mem[7] & sbs_state_7[1] & sbs_state_7[0]) ;

assign stb_state_indet[7:0] = {sbs_state_7[1] & stb_state_asi[7],
                               sbs_state_6[1] & stb_state_asi[6],
                               sbs_state_5[1] & stb_state_asi[5],
                               sbs_state_4[1] & stb_state_asi[4],
                               sbs_state_3[1] & stb_state_asi[3],
                               sbs_state_2[1] & stb_state_asi[2],
                               sbs_state_1[1] & stb_state_asi[1],
                               sbs_state_0[1] & stb_state_asi[0]
};

assign sbs_asi_indet_req = |(stb_state_indet[7:0] & dec_stb_rptr[7:0]);
assign sbs_asi_indet_retire = |(stb_state_indet[7:0] & dec_dqptr[7:0]) & st_dequeue_d1;

assign stb_state_cas[7:0] = {sbs_state_7[1] & ~sbs_state_7[0],
                             sbs_state_6[1] & ~sbs_state_6[0],
                             sbs_state_5[1] & ~sbs_state_5[0],
                             sbs_state_4[1] & ~sbs_state_4[0],
                             sbs_state_3[1] & ~sbs_state_3[0],
                             sbs_state_2[1] & ~sbs_state_2[0],
                             sbs_state_1[1] & ~sbs_state_1[0],
                             sbs_state_0[1] & ~sbs_state_0[0]};

////////////////////////////////////////////////////////////////////////////////
// Synchronizing instruction (flush/membar/stbar) tracking
// The thread will postsync on one of these instructions.  Once the store
// buffer is empty, a trap flush will restart the thread.
////////////////////////////////////////////////////////////////////////////////

assign asi_error = dcc_asi_rtn_vld & dcc_asi_rtn_excp;

assign sync_state = dcc_sync_inst_w | sync_state_out;

assign sync_state_rst = (sync_state & sbs_stb_empty) | asi_error;

assign sync_state_in = (dcc_sync_inst_w | sync_state_out) & ~sync_state_rst;

lsu_sbs_ctl_msff_ctl_macro__width_1 dff_sync_state  (
	.scan_in(dff_sync_state_scanin),
	.scan_out(dff_sync_state_scanout),
	.din	(sync_state_in),
	.dout	(sync_state_out),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trap_sync = sync_state_rst & ~asi_error;

lsu_sbs_ctl_msff_ctl_macro__width_1 dff_sbs_sync  (
	.scan_in(dff_sbs_sync_scanin),
	.scan_out(dff_sbs_sync_scanout),
	.din	(trap_sync),
	.dout	(sbs_sync),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Block stores
////////////////////////////////////////////////////////////////////////////////

// Simultaneous set and reset could be a problem so check for it.
// 0in bits_on -var {(stb_alloc_w & blk_inst_w & ~flush_w),(bst_w & ~sbc_bst_b)} -max 1
assign bst_pend_in = (bst_pend & ~(bst_w & ~sbc_bst_b)) & ~flush_bst_inst;

lsu_sbs_ctl_msff_ctl_macro__width_3 dff_bst_pend  (
	.scan_in(dff_bst_pend_scanin),
	.scan_out(dff_bst_pend_scanout),
	.l1clk	(l1clk_pm1),
	.din	({bst_pend_in, sbc_bst_b,sbc_blk_inst_b}),
	.dout	({bst_pend_out,bst_w,        blk_inst_w}),
  .siclk(siclk),
  .soclk(soclk)
);

assign bst_pend = (stb_alloc_w & blk_inst_w & ~flush_w) | bst_pend_out;

assign sbs_bst_req = bst_pend & ~bst_w & ~|(stb_state_vld[7:0]);
//assign sbs_bst_req = |(dec_stb_rptr[7:0] & ~stb_state_vld[7:0] & ~{stb_state_vld[6:0],stb_state_vld[7]} & stb_state_mem[7:0] & stb_state_cas[7:0]); 

// If an error occurs on any one of the 8 FRF reads, kill the entire bst
lsu_sbs_ctl_msff_ctl_macro__width_1 dff_bst_err  (
	.scan_in(dff_bst_err_scanin),
	.scan_out(dff_bst_err_scanout),
	.l1clk	(l1clk_pm1),
	.din	(bst_err_next),
	.dout	(bst_err),
  .siclk(siclk),
  .soclk(soclk)
);

assign bst_err_next = sbc_bst_b & (bst_err | sbc_fgu_ecc_b | sbc_bst_rd_err);
assign bst_kill = bst_w & ~sbc_bst_in_prog_b & bst_err;

////////////////////////////////////////////////////////////////////////////////
// RMO store counting
// Count the number of RMO stores outstanding to the L2.  The store buffer is
// not considered empty until all entries are dequeued AND there are no outstanding
// RMO stores.
// The counter is incremented in P5 when an RMO store is selected for issue
// The counter is decremented when the ack comes back from L2
////////////////////////////////////////////////////////////////////////////////

assign rmo_count_dec[4:0] = rmo_count[4:0] - 5'b00001;

assign rmo_st_commit_p3 = sbs_rmo_st & (sbc_st_sel_p3 & pic_st_sel_p3);

assign rmo_count_in[4:0] = cic_rmo_dequeue ? rmo_count_dec[4:0] : rmo_count[4:0];

assign blk_st_commit_p3 = sbs_blk_st & (sbc_st_sel_p3 & pic_st_sel_p3);

lsu_sbs_ctl_msff_ctl_macro__width_7 dff_rmo_count  (
	.scan_in(dff_rmo_count_scanin),
	.scan_out(dff_rmo_count_scanout),
	.l1clk	(l1clk_pm1),
	.din	({rmo_count_in[4:0], rmo_st_commit_p3,blk_st_commit_p3}),
	.dout	({rmo_count_out[4:0],rmo_st_commit_p4,blk_st_commit_p4}),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_sbs_ctl_msff_ctl_macro__width_1 dff_rmo_commit  (
	.scan_in(dff_rmo_commit_scanin),
	.scan_out(dff_rmo_commit_scanout),
	.din	(rmo_st_commit_p4),
	.dout	(rmo_st_commit_p5),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign rmo_commit_p5 = rmo_st_commit_p5 & ~kill_store_p5;
assign rmo_count[4:0] = rmo_count_out[4:0] + {4'b0000,rmo_commit_p5};

// 0in overflow -var rmo_count[4:0] -message "rmo counter overflow"
// 0in underflow -var rmo_count[4:0] -message "rmo counter underflow"

assign sbs_rmo_st_p4 = rmo_st_commit_p4;
assign sbs_blk_st_p4 = blk_st_commit_p4;

////////////////////////////////////////////////////////////////////////////////
// Tracking of partial stores with TTE.IE=1
// Because the byte mask is written to the CAM in B, but the TTE is not read until
// B, a partial store instruction with TTE.IE=1 will have it's stored byte mask
// with the wrong endianess.  We need to indicate when this store is issuing so
// that the mask can be reversed.
////////////////////////////////////////////////////////////////////////////////

assign pst_ie_b = dcc_pst_asi_b & stb_cam_wvld_b & tlb_tte_ie_b & sbc_tte_vld_b;

lsu_sbs_ctl_msff_ctl_macro__width_2 dff_pst_ie  (
	.scan_in(dff_pst_ie_scanin),
	.scan_out(dff_pst_ie_scanout),
	.l1clk	(l1clk_pm1),
	.din	({pst_ie_b,pst_ie_in}),
	.dout	({pst_ie_w,pst_ie}),
  .siclk(siclk),
  .soclk(soclk)
);

assign pst_ie_in = (pst_ie_w & ~flush_w) | (pst_ie & ~sbs_pcx_pst_ie_p4);

assign sbs_pcx_pst_ie_p4 = pst_ie & sbs_last_entry & st_commit_p4;

////////////////////////////////////////////////////////////////////////////////
// Instruction type storage
// The type of store is held here.  All "non-standard" stores are synchronizing,
// so this value is only valid when reading the last entry in the stb
// ASI - 00=ASI, 01=SR, 10=PR, 11=HPR
// mem - 00=store, 01=CAS, 10=unused, 11=SWAP

assign st_type_in[1:0] = lsu_stb_alloc ? dcc_st_rq_type_w[1:0] : st_type[1:0];

lsu_sbs_ctl_msff_ctl_macro__width_2 dff_st_type  (
	.scan_in(dff_st_type_scanin),
	.scan_out(dff_st_type_scanout),
	.l1clk	(l1clk_pm1),
	.din	(st_type_in[1:0]),
	.dout	(st_type[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign sbs_st_type[1:0] = st_type[1:0] & {2{sbs_last_entry}};

////////////////////////////////////////////////////////////////////////////////
// Cleanup for store buffer flush
// Once all stores have been killed due to a fatal error, the pick counters
// must be cleared and the dqptr reset.

assign stb_flush_set = kill_store_p5;
assign stb_flush_clr = stb_empty & ~bst_pend & ~(sbc_cam_wvld_m | stb_cam_wvld_b | stb_alloc_w);
assign stb_flush_in = (stb_flush_set | stb_flush_state) & ~stb_flush_clr;

lsu_sbs_ctl_msff_ctl_macro__width_2 dff_stb_flush  (
	.scan_in(dff_stb_flush_scanin),
	.scan_out(dff_stb_flush_scanout),
	.din	({stb_flush_in   ,((stb_flush_state | stb_flush_set) & stb_flush_clr)}),
	.dout	({stb_flush_state,stb_flush_done}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign block_store_kill = bst_kill | stb_flush_done;


lsu_sbs_ctl_spare_ctl_macro__num_3 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_flush_b_scanin        = scan_in                  ;
assign dff_flush_w_scanin        = dff_flush_b_scanout      ;
assign dff_cam_wvld_b_scanin     = dff_flush_w_scanout      ;
assign dff_st_dq_scanin          = dff_cam_wvld_b_scanout   ;
assign dff_rptr_scanin           = dff_st_dq_scanout        ;
assign dff_wptr_scanin           = dff_rptr_scanout         ;
assign dff_wptr_b_scanin         = dff_wptr_scanout         ;
assign dff_wptr_w_scanin         = dff_wptr_b_scanout       ;
assign dff_dqptr_scanin          = dff_wptr_w_scanout       ;
assign dff_stb_vld_scanin        = dff_dqptr_scanout        ;
assign dff_stb_alloc_w_scanin    = dff_stb_vld_scanout      ;
assign dff_st_commit_p4_scanin   = dff_stb_alloc_w_scanout  ;
assign dff_stb_ced_scanin        = dff_st_commit_p4_scanout ;
assign dff_ackptr_scanin         = dff_stb_ced_scanout      ;
assign dff_stb_ack_scanin        = dff_ackptr_scanout       ;
assign dff_asi_w_scanin          = dff_stb_ack_scanout      ;
assign dff_asi_pipe_scanin       = dff_asi_w_scanout        ;
assign dff_state_0_scanin        = dff_asi_pipe_scanout     ;
assign dff_state_1_scanin        = dff_state_0_scanout      ;
assign dff_state_2_scanin        = dff_state_1_scanout      ;
assign dff_state_3_scanin        = dff_state_2_scanout      ;
assign dff_state_4_scanin        = dff_state_3_scanout      ;
assign dff_state_5_scanin        = dff_state_4_scanout      ;
assign dff_state_6_scanin        = dff_state_5_scanout      ;
assign dff_state_7_scanin        = dff_state_6_scanout      ;
assign dff_sync_state_scanin     = dff_state_7_scanout      ;
assign dff_sbs_sync_scanin       = dff_sync_state_scanout   ;
assign dff_bst_pend_scanin       = dff_sbs_sync_scanout     ;
assign dff_bst_err_scanin        = dff_bst_pend_scanout     ;
assign dff_rmo_count_scanin      = dff_bst_err_scanout      ;
assign dff_rmo_commit_scanin     = dff_rmo_count_scanout    ;
assign dff_pst_ie_scanin         = dff_rmo_commit_scanout   ;
assign dff_st_type_scanin        = dff_pst_ie_scanout       ;
assign dff_stb_flush_scanin      = dff_st_type_scanout      ;
assign spares_scanin             = dff_stb_flush_scanout    ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_sbs_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbs_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbs_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbs_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbs_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbs_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbs_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sbs_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_sbs_ctl_spare_ctl_macro__num_3 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));
assign scan_out = so_2;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_sec_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_sec_ctl (
  sed_c1_lo, 
  sed_c1_hi, 
  sed_c2_lo, 
  sed_c2_hi, 
  sed_c4_lo, 
  sed_c4_hi, 
  sed_c8_lo, 
  sed_c8_hi, 
  sed_c16_lo, 
  sed_c16_hi, 
  sed_cf_lo, 
  sed_cf_hi, 
  sed_c32_hi, 
  sed_c32_lo, 
  sbc_twocycle_inst_w, 
  stb_cparity_calc, 
  sbc_st_sz_m, 
  sbc_std_le_m, 
  sbc_st_le_if_ie_m, 
  sbc_st_le_not_ie_m, 
  sbc_spd_clken, 
  mbi_run, 
  mbi_wdata_b3, 
  cecc_err, 
  uecc_err, 
  corr_bit, 
  stb_cparity, 
  sec_st_sz_dw_std_le_b, 
  sec_st_sz_dw_le_not_ie_b, 
  sec_st_sz_dw_be_not_ie_b, 
  sec_st_sz_word_le_not_ie_b, 
  sec_st_sz_word_be_not_ie_b, 
  sec_st_sz_hw_le_not_ie_b, 
  sec_st_sz_hw_be_not_ie_b, 
  sec_st_sz_dw_le_if_ie_b, 
  sec_st_sz_dw_be_if_ie_b, 
  sec_st_sz_word_le_if_ie_b, 
  sec_st_sz_word_be_if_ie_b, 
  sec_st_sz_hw_le_if_ie_b, 
  sec_st_sz_hw_be_if_ie_b, 
  sec_st_sz_byte_b, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire [31:0] err_bith;
wire [31:0] err_bitl;
wire l1clk_pm1;
wire parityl;
wire c32l;
wire c16l;
wire c8l;
wire c4l;
wire c2l;
wire c1l;
wire cecc_errl;
wire uecc_errl;
wire parityh;
wire c32h;
wire c16h;
wire c8h;
wire c4h;
wire c2h;
wire c1h;
wire cecc_errh;
wire uecc_errh;
wire stb_cparity_w;
wire dff_cparity_scanin;
wire dff_cparity_scanout;
wire st_sz_dw_m;
wire st_sz_word_m;
wire st_sz_hw_m;
wire st_sz_byte_m;
wire st_sz_dw_std_le_m;
wire st_sz_dw_le_not_ie_m;
wire st_sz_dw_be_not_ie_m;
wire st_sz_word_le_not_ie_m;
wire st_sz_word_be_not_ie_m;
wire st_sz_hw_le_not_ie_m;
wire st_sz_hw_be_not_ie_m;
wire st_sz_dw_le_if_ie_m;
wire st_sz_dw_be_if_ie_m;
wire st_sz_word_le_if_ie_m;
wire st_sz_word_be_if_ie_m;
wire st_sz_hw_le_if_ie_m;
wire st_sz_hw_be_if_ie_m;
wire dff_st_sz_scanin;
wire dff_st_sz_scanout;
wire spares_scanin;
wire spares_scanout;


input	[1:0]	sed_c1_lo;
input	[1:0]	sed_c1_hi;
input	[1:0]	sed_c2_lo;
input	[1:0]	sed_c2_hi;
input	[1:0]	sed_c4_lo;
input	[1:0]	sed_c4_hi;
input	[1:0]	sed_c8_lo;
input	[1:0]	sed_c8_hi;
input	[1:0]	sed_c16_lo;
input	[1:0]	sed_c16_hi;
input	[2:0]	sed_cf_lo;
input	[2:0]	sed_cf_hi;
input		sed_c32_hi;
input		sed_c32_lo;

input		sbc_twocycle_inst_w;
input		stb_cparity_calc;
input	[1:0]	sbc_st_sz_m;
input		sbc_std_le_m;
input		sbc_st_le_if_ie_m;
input		sbc_st_le_not_ie_m;
input		sbc_spd_clken;

input		mbi_run;
input		mbi_wdata_b3;

output		cecc_err;
output		uecc_err;
output	[63:0]	corr_bit;
output		stb_cparity;

output		sec_st_sz_dw_std_le_b;
output		sec_st_sz_dw_le_not_ie_b;
output		sec_st_sz_dw_be_not_ie_b;
output		sec_st_sz_word_le_not_ie_b;
output		sec_st_sz_word_be_not_ie_b;
output		sec_st_sz_hw_le_not_ie_b;
output		sec_st_sz_hw_be_not_ie_b;
output		sec_st_sz_dw_le_if_ie_b;
output		sec_st_sz_dw_be_if_ie_b;
output		sec_st_sz_word_le_if_ie_b;
output		sec_st_sz_word_be_if_ie_b;
output		sec_st_sz_hw_le_if_ie_b;
output		sec_st_sz_hw_be_if_ie_b;
output		sec_st_sz_byte_b;

input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

assign corr_bit[63:0] = {err_bith[31:0],err_bitl[31:0]};

//////////////////////////////
// Clock header
//////////////////////////////
lsu_sec_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk              ),
        .l1en   (sbc_spd_clken      ),
        .l1clk  (l1clk_pm1          ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

///////////////////////////////////////////////////////////////////////
// Flop check bits, determine error, and generate correction vector

assign parityl = sed_cf_lo[2] ^ sed_cf_lo[1] ^ sed_cf_lo[0];
assign c32l    = sed_c32_lo;
assign c16l    = sed_c16_lo[1] ^ sed_c16_lo[0];
assign c8l     = sed_c8_lo[1] ^ sed_c8_lo[0];
assign c4l     = sed_c4_lo[1] ^ sed_c4_lo[0];
assign c2l     = sed_c2_lo[1] ^ sed_c2_lo[0];
assign c1l     = sed_c1_lo[1] ^ sed_c1_lo[0];

assign cecc_errl = |({c1l,c2l,c4l,c8l,c16l,c32l}) & parityl;
assign uecc_errl = |({c1l,c2l,c4l,c8l,c16l,c32l}) & ~parityl;

assign err_bitl[0]  = ~c32l & ~c16l & ~c8l & ~c4l &  c2l &  c1l;
assign err_bitl[1]  = ~c32l & ~c16l & ~c8l &  c4l & ~c2l &  c1l;
assign err_bitl[2]  = ~c32l & ~c16l & ~c8l &  c4l &  c2l & ~c1l;
assign err_bitl[3]  = ~c32l & ~c16l & ~c8l &  c4l &  c2l &  c1l;
assign err_bitl[4]  = ~c32l & ~c16l &  c8l & ~c4l & ~c2l &  c1l;
assign err_bitl[5]  = ~c32l & ~c16l &  c8l & ~c4l &  c2l & ~c1l;
assign err_bitl[6]  = ~c32l & ~c16l &  c8l & ~c4l &  c2l &  c1l;
assign err_bitl[7]  = ~c32l & ~c16l &  c8l &  c4l & ~c2l & ~c1l;
assign err_bitl[8]  = ~c32l & ~c16l &  c8l &  c4l & ~c2l &  c1l;
assign err_bitl[9]  = ~c32l & ~c16l &  c8l &  c4l &  c2l & ~c1l;
assign err_bitl[10] = ~c32l & ~c16l &  c8l &  c4l &  c2l &  c1l;
assign err_bitl[11] = ~c32l &  c16l & ~c8l & ~c4l & ~c2l &  c1l;
assign err_bitl[12] = ~c32l &  c16l & ~c8l & ~c4l &  c2l & ~c1l;
assign err_bitl[13] = ~c32l &  c16l & ~c8l & ~c4l &  c2l &  c1l;
assign err_bitl[14] = ~c32l &  c16l & ~c8l &  c4l & ~c2l & ~c1l;
assign err_bitl[15] = ~c32l &  c16l & ~c8l &  c4l & ~c2l &  c1l;
assign err_bitl[16] = ~c32l &  c16l & ~c8l &  c4l &  c2l & ~c1l;
assign err_bitl[17] = ~c32l &  c16l & ~c8l &  c4l &  c2l &  c1l;
assign err_bitl[18] = ~c32l &  c16l &  c8l & ~c4l & ~c2l & ~c1l;
assign err_bitl[19] = ~c32l &  c16l &  c8l & ~c4l & ~c2l &  c1l;
assign err_bitl[20] = ~c32l &  c16l &  c8l & ~c4l &  c2l & ~c1l;
assign err_bitl[21] = ~c32l &  c16l &  c8l & ~c4l &  c2l &  c1l;
assign err_bitl[22] = ~c32l &  c16l &  c8l &  c4l & ~c2l & ~c1l;
assign err_bitl[23] = ~c32l &  c16l &  c8l &  c4l & ~c2l &  c1l;
assign err_bitl[24] = ~c32l &  c16l &  c8l &  c4l &  c2l & ~c1l;
assign err_bitl[25] = ~c32l &  c16l &  c8l &  c4l &  c2l &  c1l;
assign err_bitl[26] =  c32l & ~c16l & ~c8l & ~c4l & ~c2l &  c1l;
assign err_bitl[27] =  c32l & ~c16l & ~c8l & ~c4l &  c2l & ~c1l;
assign err_bitl[28] =  c32l & ~c16l & ~c8l & ~c4l &  c2l &  c1l;
assign err_bitl[29] =  c32l & ~c16l & ~c8l &  c4l & ~c2l & ~c1l;
assign err_bitl[30] =  c32l & ~c16l & ~c8l &  c4l & ~c2l &  c1l;
assign err_bitl[31] =  c32l & ~c16l & ~c8l &  c4l &  c2l & ~c1l;

assign parityh = sed_cf_hi[2] ^ sed_cf_hi[1] ^ sed_cf_hi[0];
assign c32h    = sed_c32_hi;
assign c16h    = sed_c16_hi[1] ^ sed_c16_hi[0];
assign c8h     = sed_c8_hi[1] ^ sed_c8_hi[0];
assign c4h     = sed_c4_hi[1] ^ sed_c4_hi[0];
assign c2h     = sed_c2_hi[1] ^ sed_c2_hi[0];
assign c1h     = sed_c1_hi[1] ^ sed_c1_hi[0];

assign cecc_errh = |({c1h,c2h,c4h,c8h,c16h,c32h}) &  parityh;
assign uecc_errh = |({c1h,c2h,c4h,c8h,c16h,c32h}) & ~parityh;

assign err_bith[0]  = ~c32h & ~c16h & ~c8h & ~c4h &  c2h &  c1h;
assign err_bith[1]  = ~c32h & ~c16h & ~c8h &  c4h & ~c2h &  c1h;
assign err_bith[2]  = ~c32h & ~c16h & ~c8h &  c4h &  c2h & ~c1h;
assign err_bith[3]  = ~c32h & ~c16h & ~c8h &  c4h &  c2h &  c1h;
assign err_bith[4]  = ~c32h & ~c16h &  c8h & ~c4h & ~c2h &  c1h;
assign err_bith[5]  = ~c32h & ~c16h &  c8h & ~c4h &  c2h & ~c1h;
assign err_bith[6]  = ~c32h & ~c16h &  c8h & ~c4h &  c2h &  c1h;
assign err_bith[7]  = ~c32h & ~c16h &  c8h &  c4h & ~c2h & ~c1h;
assign err_bith[8]  = ~c32h & ~c16h &  c8h &  c4h & ~c2h &  c1h;
assign err_bith[9]  = ~c32h & ~c16h &  c8h &  c4h &  c2h & ~c1h;
assign err_bith[10] = ~c32h & ~c16h &  c8h &  c4h &  c2h &  c1h;
assign err_bith[11] = ~c32h &  c16h & ~c8h & ~c4h & ~c2h &  c1h;
assign err_bith[12] = ~c32h &  c16h & ~c8h & ~c4h &  c2h & ~c1h;
assign err_bith[13] = ~c32h &  c16h & ~c8h & ~c4h &  c2h &  c1h;
assign err_bith[14] = ~c32h &  c16h & ~c8h &  c4h & ~c2h & ~c1h;
assign err_bith[15] = ~c32h &  c16h & ~c8h &  c4h & ~c2h &  c1h;
assign err_bith[16] = ~c32h &  c16h & ~c8h &  c4h &  c2h & ~c1h;
assign err_bith[17] = ~c32h &  c16h & ~c8h &  c4h &  c2h &  c1h;
assign err_bith[18] = ~c32h &  c16h &  c8h & ~c4h & ~c2h & ~c1h;
assign err_bith[19] = ~c32h &  c16h &  c8h & ~c4h & ~c2h &  c1h;
assign err_bith[20] = ~c32h &  c16h &  c8h & ~c4h &  c2h & ~c1h;
assign err_bith[21] = ~c32h &  c16h &  c8h & ~c4h &  c2h &  c1h;
assign err_bith[22] = ~c32h &  c16h &  c8h &  c4h & ~c2h & ~c1h;
assign err_bith[23] = ~c32h &  c16h &  c8h &  c4h & ~c2h &  c1h;
assign err_bith[24] = ~c32h &  c16h &  c8h &  c4h &  c2h & ~c1h;
assign err_bith[25] = ~c32h &  c16h &  c8h &  c4h &  c2h &  c1h;
assign err_bith[26] =  c32h & ~c16h & ~c8h & ~c4h & ~c2h &  c1h;
assign err_bith[27] =  c32h & ~c16h & ~c8h & ~c4h &  c2h & ~c1h;
assign err_bith[28] =  c32h & ~c16h & ~c8h & ~c4h &  c2h &  c1h;
assign err_bith[29] =  c32h & ~c16h & ~c8h &  c4h & ~c2h & ~c1h;
assign err_bith[30] =  c32h & ~c16h & ~c8h &  c4h & ~c2h &  c1h;
assign err_bith[31] =  c32h & ~c16h & ~c8h &  c4h &  c2h & ~c1h;

assign cecc_err = cecc_errl | cecc_errh;
assign uecc_err = uecc_errl | uecc_errh;

assign stb_cparity   = mbi_run ? mbi_wdata_b3 : (sbc_twocycle_inst_w ? stb_cparity_w : stb_cparity_calc);

// Store cam parity for a cycle for the STD case
lsu_sec_ctl_msff_ctl_macro__width_1 dff_cparity  (
	.scan_in(dff_cparity_scanin),
	.scan_out(dff_cparity_scanout),
	.l1clk	(l1clk_pm1),
	.din	(stb_cparity_calc),
	.dout	(stb_cparity_w),
  .siclk(siclk),
  .soclk(soclk)
);

assign st_sz_dw_m   =  sbc_st_sz_m[1] &  sbc_st_sz_m[0];
assign st_sz_word_m =  sbc_st_sz_m[1] & ~sbc_st_sz_m[0];
assign st_sz_hw_m   = ~sbc_st_sz_m[1] &  sbc_st_sz_m[0];
assign st_sz_byte_m = ~sbc_st_sz_m[1] & ~sbc_st_sz_m[0];

assign st_sz_dw_std_le_m = st_sz_dw_m & sbc_std_le_m;
assign st_sz_dw_le_not_ie_m = st_sz_dw_m & ~sbc_std_le_m & sbc_st_le_not_ie_m;
assign st_sz_dw_be_not_ie_m = st_sz_dw_m & ~sbc_std_le_m & ~sbc_st_le_not_ie_m;
assign st_sz_word_le_not_ie_m = st_sz_word_m & sbc_st_le_not_ie_m;
assign st_sz_word_be_not_ie_m = st_sz_word_m & ~sbc_st_le_not_ie_m;
assign st_sz_hw_le_not_ie_m = st_sz_hw_m & sbc_st_le_not_ie_m;
assign st_sz_hw_be_not_ie_m = st_sz_hw_m & ~sbc_st_le_not_ie_m;
assign st_sz_dw_le_if_ie_m = st_sz_dw_m & ~sbc_std_le_m & sbc_st_le_if_ie_m;
assign st_sz_dw_be_if_ie_m = st_sz_dw_m & ~sbc_std_le_m & ~sbc_st_le_if_ie_m;
assign st_sz_word_le_if_ie_m = st_sz_word_m & sbc_st_le_if_ie_m;
assign st_sz_word_be_if_ie_m = st_sz_word_m & ~sbc_st_le_if_ie_m;
assign st_sz_hw_le_if_ie_m = st_sz_hw_m & sbc_st_le_if_ie_m;
assign st_sz_hw_be_if_ie_m = st_sz_hw_m & ~sbc_st_le_if_ie_m;

lsu_sec_ctl_msff_ctl_macro__width_14 dff_st_sz  (
	.scan_in(dff_st_sz_scanin),
	.scan_out(dff_st_sz_scanout),
	.l1clk	(l1clk_pm1),
	.din	({    st_sz_dw_std_le_m,         st_sz_dw_le_not_ie_m,      st_sz_dw_be_not_ie_m,
		      st_sz_word_le_not_ie_m,    st_sz_word_be_not_ie_m,    st_sz_hw_le_not_ie_m,
		      st_sz_hw_be_not_ie_m,      st_sz_dw_le_if_ie_m,       st_sz_dw_be_if_ie_m,
		      st_sz_word_le_if_ie_m,     st_sz_word_be_if_ie_m,     st_sz_hw_le_if_ie_m,
		      st_sz_hw_be_if_ie_m,       st_sz_byte_m}),
	.dout	({sec_st_sz_dw_std_le_b,     sec_st_sz_dw_le_not_ie_b,  sec_st_sz_dw_be_not_ie_b,
		  sec_st_sz_word_le_not_ie_b,sec_st_sz_word_be_not_ie_b,sec_st_sz_hw_le_not_ie_b,
		  sec_st_sz_hw_be_not_ie_b,  sec_st_sz_dw_le_if_ie_b,   sec_st_sz_dw_be_if_ie_b,
		  sec_st_sz_word_le_if_ie_b, sec_st_sz_word_be_if_ie_b, sec_st_sz_hw_le_if_ie_b,
		  sec_st_sz_hw_be_if_ie_b,   sec_st_sz_byte_b}),
  .siclk(siclk),
  .soclk(soclk)
);


lsu_sec_ctl_spare_ctl_macro__num_1 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);

// fixscan start:
assign dff_cparity_scanin        = scan_in                  ;
assign dff_st_sz_scanin          = dff_cparity_scanout      ;
assign spares_scanin             = dff_st_sz_scanout        ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_sec_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sec_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sec_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_sec_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_sed_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_sed_dp (
  sbc_ramout_clken, 
  sbc_diag_wptr_w3, 
  sbc_inv_ecc, 
  stb_ram_rd_data, 
  sec_corr_bit, 
  stb_ram_rd_ecc, 
  stb_ram_rd_cparity, 
  stb_ram_rd_ctl, 
  sbd_st_data_b, 
  stb_cam_data, 
  dcc_stb_data_rd_w3, 
  dcc_stb_ecc_rd_w3, 
  dcc_stb_ctl_rd_w3, 
  dcc_stb_addr_sel_w3, 
  dcc_stb_ptr_rd_w3, 
  mbi_run, 
  mbi_wdata, 
  bist_cmp_data, 
  stb_ram_data, 
  stb_ram_data_corr, 
  stb_ram_ctl, 
  stb_ram_cparity, 
  sed_ecc_b, 
  sed_c1_lo, 
  sed_c1_hi, 
  sed_c2_lo, 
  sed_c2_hi, 
  sed_c4_lo, 
  sed_c4_hi, 
  sed_c8_lo, 
  sed_c8_hi, 
  sed_c16_lo, 
  sed_c16_hi, 
  sed_cf_lo, 
  sed_cf_hi, 
  sed_c32_hi, 
  sed_c32_lo, 
  stb_ldxa_asi_data_w, 
  sed_bist_cmp_0, 
  sed_bist_cmp_1, 
  sed_bist_cmp_2, 
  sed_bist_cmp_3, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_se_scancollar_out, 
  spc_aclk, 
  spc_bclk, 
  scan_out);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [31:0] wdh;
wire [31:0] wdl;
wire [6:0] inv;
wire p1_hi_l;
wire p1_hi_r;
wire p1_hi;
wire p2_hi_l;
wire p2_hi_r;
wire p2_hi;
wire p4_hi_l;
wire p4_hi_r;
wire p4_hi;
wire p8_hi_l;
wire p8_hi_r;
wire p8_hi;
wire p16_hi_l;
wire p16_hi_r;
wire p16_hi;
wire p32_hi_l;
wire p32_hi;
wire pf_hi_l;
wire pf_hi_r;
wire pf_hi;
wire p1_lo_l;
wire p1_lo_r;
wire p1_lo;
wire p2_lo_l;
wire p2_lo_r;
wire p2_lo;
wire p4_lo_l;
wire p4_lo_r;
wire p4_lo;
wire p8_lo_l;
wire p8_lo_r;
wire p8_lo;
wire p16_lo_l;
wire p16_lo_r;
wire p16_lo;
wire p32_lo_l;
wire p32_lo;
wire pf_lo_l;
wire pf_lo_r;
wire pf_lo;
wire mbi_run_;
wire mbi_run_local;
wire [31:0] rdh;
wire [31:0] rdl;
wire [13:0] ecc;
wire c1_hi_l;
wire c1_hi_r;
wire c2_hi_l;
wire c2_hi_r;
wire c4_hi_l;
wire c4_hi_r;
wire c8_hi_l;
wire c8_hi_r;
wire c16_hi_r;
wire c32_hi_l;
wire cf_hi_l;
wire cf_hi_r;
wire cf_hi_c;
wire c1_lo_l;
wire c1_lo_r;
wire c2_lo_l;
wire c2_lo_r;
wire c4_lo_l;
wire c4_lo_r;
wire c8_lo_l;
wire c8_lo_r;
wire c16_lo_r;
wire c32_lo_l;
wire cf_lo_l;
wire cf_lo_r;
wire cf_lo_c;
wire dff_prty_bits_scanin;
wire dff_prty_bits_scanout;
wire dff_rd_data_0_scanin;
wire dff_rd_data_0_scanout;
wire [13:0] stb_ram_ecc;
wire [1:0] unused;
wire dff_rd_data_1_scanin;
wire dff_rd_data_1_scanout;
wire [63:0] stb_ram_data_corr_;
wire [31:0] def_value;
wire [63:0] stb_diag_rd_data;


input		sbc_ramout_clken;
input	[2:0]	sbc_diag_wptr_w3;
input	[6:0]	sbc_inv_ecc;

input	[63:0]	stb_ram_rd_data;
input	[63:0]	sec_corr_bit;
input	[13:0]	stb_ram_rd_ecc;
input		stb_ram_rd_cparity;
input	[2:0]	stb_ram_rd_ctl;

input	[63:0]	sbd_st_data_b;

input	[44:0]	stb_cam_data;

input		dcc_stb_data_rd_w3;
input		dcc_stb_ecc_rd_w3;
input		dcc_stb_ctl_rd_w3;
input		dcc_stb_addr_sel_w3;
input		dcc_stb_ptr_rd_w3;

input		mbi_run;
input	[7:0]	mbi_wdata;
input	[7:0]	bist_cmp_data;

output	[63:0]	stb_ram_data;		// Flopped data
output	[63:0]	stb_ram_data_corr;	// Final formatted data
output	[2:0]	stb_ram_ctl;
output		stb_ram_cparity;
output	[13:0]	sed_ecc_b;		// generated ECC bits

output	[1:0]	sed_c1_lo;
output	[1:0]	sed_c1_hi;
output	[1:0]	sed_c2_lo;
output	[1:0]	sed_c2_hi;
output	[1:0]	sed_c4_lo;
output	[1:0]	sed_c4_hi;
output	[1:0]	sed_c8_lo;
output	[1:0]	sed_c8_hi;
output	[1:0]	sed_c16_lo;
output	[1:0]	sed_c16_hi;
output	[2:0]	sed_cf_lo;
output	[2:0]	sed_cf_hi;
output		sed_c32_hi;
output		sed_c32_lo;

output	[63:0]	stb_ldxa_asi_data_w;
output		sed_bist_cmp_0;
output		sed_bist_cmp_1;
output		sed_bist_cmp_2;
output		sed_bist_cmp_3;

// Globals
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_se_scancollar_out;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

// scan renames
assign stop = 1'b0;
// end scan

lsu_sed_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_se_scancollar_out,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);

////////////////////////////////////////////////////////////////////////////////
// ECC generation logic

assign {wdh[31:0],wdl[31:0]} = sbd_st_data_b[63:0];
assign inv[6:0] = sbc_inv_ecc[6:0];

// P1 - hi
lsu_sed_dp_prty_macro__width_16 pgen1_hi_l  (
	.din	({inv[0],wdh[30],1'b0   ,wdh[28],1'b0   ,wdh[26],wdh[25],1'b0   ,
		  wdh[23],1'b0   ,wdh[21],1'b0   ,wdh[19],1'b0   ,wdh[17],1'b0   }),
	.dout	(p1_hi_l)
);
lsu_sed_dp_prty_macro__width_16 pgen1_hi_r  (
	.din	({wdh[15],1'b0   ,wdh[13],1'b0   ,wdh[11],wdh[10],1'b0   ,wdh[8],
		  1'b0   ,wdh[6],1'b0   ,wdh[4],wdh[3],1'b0   ,wdh[1],wdh[0]}),
	.dout	(p1_hi_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen1_hi   (
	.din0	(p1_hi_l),
	.din1	(p1_hi_r),
	.dout	(p1_hi)
);

// P2 - hi
lsu_sed_dp_prty_macro__width_16 pgen2_hi_l  (
	.din	({wdh[31],inv[1],1'b0   ,wdh[28],wdh[27],1'b0   ,wdh[25],wdh[24],
		  1'b0   ,1'b0   ,wdh[21],wdh[20],1'b0   ,1'b0   ,wdh[17],wdh[16]}),
	.dout	(p2_hi_l)
);
lsu_sed_dp_prty_macro__width_16 pgen2_hi_r  (
	.din	({1'b0   ,1'b0   ,wdh[13],wdh[12],1'b0   ,wdh[10],wdh[9],1'b0   ,
		  1'b0   ,wdh[6],wdh[5],1'b0   ,wdh[3],wdh[2],1'b0   ,wdh[0]}),
	.dout	(p2_hi_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen2_hi   (
	.din0	(p2_hi_l),
	.din1	(p2_hi_r),
	.dout	(p2_hi)
);

// P4 - hi
lsu_sed_dp_prty_macro__width_16 pgen4_hi_l  (
	.din	({wdh[31],wdh[30],wdh[29],inv[2],1'b0   ,1'b0   ,wdh[25],wdh[24],
		  wdh[23],wdh[22],1'b0   ,1'b0   ,1'b0   ,1'b0   ,wdh[17],wdh[16]}),
	.dout	(p4_hi_l)
);
lsu_sed_dp_prty_macro__width_16 pgen4_hi_r  (
	.din	({wdh[15],wdh[14],1'b0   ,1'b0   ,1'b0   ,wdh[10],wdh[9],wdh[8],
		  wdh[7],1'b0   ,1'b0   ,1'b0   ,wdh[3],wdh[2],wdh[1],1'b0   }),
	.dout	(p4_hi_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen4_hi   (
	.din0	(p4_hi_l),
	.din1	(p4_hi_r),
	.dout	(p4_hi)
);

// P8 - hi
lsu_sed_dp_prty_macro__width_8 pgen8_hi_l  (
	.din	({wdh[25],wdh[24],wdh[23],wdh[22],wdh[21],wdh[20],wdh[19],wdh[18]}),
	.dout	(p8_hi_l)
);
lsu_sed_dp_prty_macro__width_8 pgen8_hi_r  (
	.din	({inv[3],wdh[10],wdh[9],wdh[8],wdh[7],wdh[6],wdh[5],wdh[4]}),
	.dout	(p8_hi_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen8_hi   (
	.din0	(p8_hi_l),
	.din1	(p8_hi_r),
	.dout	(p8_hi)
);

// P16 - hi
assign p16_hi_l = p8_hi_l;	// this one can be shared

lsu_sed_dp_prty_macro__width_8 pgen16_hi_r  (
	.din	({wdh[17],wdh[16],wdh[15],wdh[14],wdh[13],wdh[12],wdh[11],inv[4]}),
	.dout	(p16_hi_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen16_hi   (
	.din0	(p16_hi_l),
	.din1	(p16_hi_r),
	.dout	(p16_hi)
);

// P32 - hi
lsu_sed_dp_prty_macro__width_8 pgen32_hi_l  (
	.din	({wdh[31],wdh[30],wdh[29],wdh[28],wdh[27],wdh[26],inv[5],1'b0   }),
	.dout	(p32_hi_l)
);
lsu_sed_dp_buff_macro__width_1 pgen32_hi  (
	.din	(p32_hi_l),
	.dout	(p32_hi)
);

// PF - hi
lsu_sed_dp_prty_macro__width_16 pgenf_hi_l  (
	.din	({inv[6],1'b0   ,wdh[29],1'b0   ,wdh[27],wdh[26],1'b0   ,wdh[24],
		  wdh[23],1'b0   ,wdh[21],1'b0   ,1'b0   ,wdh[18],wdh[17],1'b0   }),
	.dout	(pf_hi_l)
);
lsu_sed_dp_prty_macro__width_16 pgenf_hi_r  (
	.din	({1'b0   ,wdh[14],1'b0   ,wdh[12],wdh[11],wdh[10],1'b0   ,1'b0   ,
		  wdh[7],1'b0   ,wdh[5],wdh[4],1'b0   ,wdh[2],wdh[1],wdh[0]}),
	.dout	(pf_hi_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgenf_hi   (
	.din0	(pf_hi_l),
	.din1	(pf_hi_r),
	.dout	(pf_hi)
);

// P1 - lo
lsu_sed_dp_prty_macro__width_16 pgen1_lo_l  (
	.din	({1'b0   ,wdl[30],1'b0   ,wdl[28],1'b0   ,wdl[26],wdl[25],1'b0   ,
		  wdl[23],1'b0   ,wdl[21],1'b0   ,wdl[19],1'b0   ,wdl[17],1'b0   }),
	.dout	(p1_lo_l)
);
lsu_sed_dp_prty_macro__width_16 pgen1_lo_r  (
	.din	({wdl[15],1'b0   ,wdl[13],1'b0   ,wdl[11],wdl[10],1'b0   ,wdl[8],
		  1'b0   ,wdl[6],1'b0   ,wdl[4],wdl[3],1'b0   ,wdl[1],wdl[0]}),
	.dout	(p1_lo_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen1_lo   (
	.din0	(p1_lo_l),
	.din1	(p1_lo_r),
	.dout	(p1_lo)
);

// P2 - lo
lsu_sed_dp_prty_macro__width_16 pgen2_lo_l  (
	.din	({wdl[31],1'b0   ,1'b0   ,wdl[28],wdl[27],1'b0   ,wdl[25],wdl[24],
		  1'b0   ,1'b0   ,wdl[21],wdl[20],1'b0   ,1'b0   ,wdl[17],wdl[16]}),
	.dout	(p2_lo_l)
);
lsu_sed_dp_prty_macro__width_16 pgen2_lo_r  (
	.din	({1'b0   ,1'b0   ,wdl[13],wdl[12],1'b0   ,wdl[10],wdl[9],1'b0   ,
		  1'b0   ,wdl[6],wdl[5],1'b0   ,wdl[3],wdl[2],1'b0   ,wdl[0]}),
	.dout	(p2_lo_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen2_lo   (
	.din0	(p2_lo_l),
	.din1	(p2_lo_r),
	.dout	(p2_lo)
);

// P4 - lo
lsu_sed_dp_prty_macro__width_16 pgen4_lo_l  (
	.din	({wdl[31],wdl[30],wdl[29],1'b0   ,1'b0   ,1'b0   ,wdl[25],wdl[24],
		  wdl[23],wdl[22],1'b0   ,1'b0   ,1'b0   ,1'b0   ,wdl[17],wdl[16]}),
	.dout	(p4_lo_l)
);
lsu_sed_dp_prty_macro__width_16 pgen4_lo_r  (
	.din	({wdl[15],wdl[14],1'b0   ,1'b0   ,1'b0   ,wdl[10],wdl[9],wdl[8],
		  wdl[7],1'b0   ,1'b0   ,1'b0   ,wdl[3],wdl[2],wdl[1],1'b0   }),
	.dout	(p4_lo_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen4_lo   (
	.din0	(p4_lo_l),
	.din1	(p4_lo_r),
	.dout	(p4_lo)
);

// P8 - lo
lsu_sed_dp_prty_macro__width_8 pgen8_lo_l  (
	.din	({wdl[25],wdl[24],wdl[23],wdl[22],wdl[21],wdl[20],wdl[19],wdl[18]}),
	.dout	(p8_lo_l)
);
lsu_sed_dp_prty_macro__width_8 pgen8_lo_r  (
	.din	({1'b0   ,wdl[10],wdl[9],wdl[8],wdl[7],wdl[6],wdl[5],wdl[4]}),
	.dout	(p8_lo_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen8_lo   (
	.din0	(p8_lo_l),
	.din1	(p8_lo_r),
	.dout	(p8_lo)
);

// P16 - lo
assign p16_lo_l = p8_lo_l;	// this one can be shared

lsu_sed_dp_prty_macro__width_8 pgen16_lo_r  (
	.din	({wdl[17],wdl[16],wdl[15],wdl[14],wdl[13],wdl[12],wdl[11],1'b0   }),
	.dout	(p16_lo_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgen16_lo   (
	.din0	(p16_lo_l),
	.din1	(p16_lo_r),
	.dout	(p16_lo)
);

// P32 - lo
lsu_sed_dp_prty_macro__width_8 pgen32_lo_l  (
	.din	({wdl[31],wdl[30],wdl[29],wdl[28],wdl[27],wdl[26],1'b0   ,1'b0   }),
	.dout	(p32_lo_l)
);
lsu_sed_dp_buff_macro__width_1 pgen32_lo  (
	.din	(p32_lo_l),
	.dout	(p32_lo)
);

// PF - lo
lsu_sed_dp_prty_macro__width_16 pgenf_lo_l  (
	.din	({1'b0   ,1'b0   ,wdl[29],1'b0   ,wdl[27],wdl[26],1'b0   ,wdl[24],
		  wdl[23],1'b0   ,wdl[21],1'b0   ,1'b0   ,wdl[18],wdl[17],1'b0   }),
	.dout	(pf_lo_l)
);
lsu_sed_dp_prty_macro__width_16 pgenf_lo_r  (
	.din	({1'b0   ,wdl[14],1'b0   ,wdl[12],wdl[11],wdl[10],1'b0   ,1'b0   ,
		  wdl[7],1'b0   ,wdl[5],wdl[4],1'b0   ,wdl[2],wdl[1],wdl[0]}),
	.dout	(pf_lo_r)
);
lsu_sed_dp_xor_macro__ports_2__width_1 pgenf_lo   (
	.din0	(pf_lo_l),
	.din1	(pf_lo_r),
	.dout	(pf_lo)
);

lsu_sed_dp_inv_macro__width_2 mbi_run_buf  (
	.din	({mbi_run, mbi_run_}),
	.dout	({mbi_run_,mbi_run_local})
);

lsu_sed_dp_mux_macro__buffsel_none__dmux_4x__mux_aonpe__ports_2__width_14 bist_ecc_mx      (
	.din0	({mbi_wdata[5:0],mbi_wdata[7:0]}),
	.din1	({pf_hi,p32_hi,p16_hi,p8_hi,p4_hi,p2_hi,p1_hi,
		  pf_lo,p32_lo,p16_lo,p8_lo,p4_lo,p2_lo,p1_lo}),
	.sel0	(mbi_run_local),
	.sel1	(mbi_run_),
	.dout	(sed_ecc_b[13:0])
);

////////////////////////////////////////////////////////////////////////////////
// ECC check logic

assign {rdh[31:0],rdl[31:0]} = stb_ram_rd_data[63:0];
assign ecc[13:0] = stb_ram_rd_ecc[13:0];

// C1 - hi
lsu_sed_dp_prty_macro__width_16 pchk1_hi_l  (
	.din	({1'b0   ,rdh[30],1'b0   ,rdh[28],1'b0   ,rdh[26],rdh[25],1'b0   ,
		  rdh[23],1'b0   ,rdh[21],1'b0   ,rdh[19],1'b0   ,rdh[17],ecc[7]}),
	.dout	(c1_hi_l)
);
lsu_sed_dp_prty_macro__width_16 pchk1_hi_r  (
	.din	({rdh[15],1'b0   ,rdh[13],1'b0   ,rdh[11],rdh[10],1'b0   ,rdh[8],
		  1'b0   ,rdh[6],1'b0   ,rdh[4],rdh[3],1'b0   ,rdh[1],rdh[0]}),
	.dout	(c1_hi_r)
);

// C2 - hi
lsu_sed_dp_prty_macro__width_16 pchk2_hi_l  (
	.din	({rdh[31],1'b0   ,1'b0   ,rdh[28],rdh[27],1'b0   ,rdh[25],rdh[24],
		  1'b0   ,1'b0   ,rdh[21],rdh[20],1'b0   ,1'b0   ,rdh[17],rdh[16]}),
	.dout	(c2_hi_l)
);
lsu_sed_dp_prty_macro__width_16 pchk2_hi_r  (
	.din	({ecc[8],1'b0   ,rdh[13],rdh[12],1'b0   ,rdh[10],rdh[9],1'b0   ,
		  1'b0   ,rdh[6],rdh[5],1'b0   ,rdh[3],rdh[2],1'b0   ,rdh[0]}),
	.dout	(c2_hi_r)
);

// C4 - hi
lsu_sed_dp_prty_macro__width_16 pchk4_hi_l  (
	.din	({rdh[31],rdh[30],rdh[29],1'b0   ,1'b0   ,1'b0   ,rdh[25],rdh[24],
		  rdh[23],rdh[22],1'b0   ,1'b0   ,1'b0   ,1'b0   ,rdh[17],rdh[16]}),
	.dout	(c4_hi_l)
);
lsu_sed_dp_prty_macro__width_16 pchk4_hi_r  (
	.din	({rdh[15],rdh[14],ecc[9],1'b0   ,1'b0   ,rdh[10],rdh[9],rdh[8],
		  rdh[7],1'b0   ,1'b0   ,1'b0   ,rdh[3],rdh[2],rdh[1],1'b0   }),
	.dout	(c4_hi_r)
);

// C8 - hi
lsu_sed_dp_prty_macro__width_8 pchk8_hi_l  (
	.din	({rdh[25],rdh[24],rdh[23],rdh[22],rdh[21],rdh[20],rdh[19],rdh[18]}),
	.dout	(c8_hi_l)
);
lsu_sed_dp_prty_macro__width_8 pchk8_hi_r  (
	.din	({ecc[10],rdh[10],rdh[9],rdh[8],rdh[7],rdh[6],rdh[5],rdh[4]}),
	.dout	(c8_hi_r)
);

// C16 - hi
lsu_sed_dp_prty_macro__width_8 pchk16_hi_r  (
	.din	({rdh[17],rdh[16],rdh[15],rdh[14],rdh[13],rdh[12],rdh[11],ecc[11]}),
	.dout	(c16_hi_r)
);

// C32 - hi
lsu_sed_dp_prty_macro__width_8 pchk32_hi_l  (
	.din	({rdh[31],rdh[30],rdh[29],rdh[28],rdh[27],rdh[26],1'b0   ,ecc[12]}),
	.dout	(c32_hi_l)
);

// CF - hi
lsu_sed_dp_prty_macro__width_16 pchkf_hi_l  (
	.din	({rdh[31],rdh[30],rdh[29],rdh[28],rdh[27],rdh[26],rdh[25],rdh[24],
		  rdh[23],rdh[22],rdh[21],rdh[20],rdh[19],rdh[18],rdh[17],rdh[16]}),
	.dout	(cf_hi_l)
);
lsu_sed_dp_prty_macro__width_16 pchkf_hi_r  (
	.din	({rdh[15],rdh[14],rdh[13],rdh[12],rdh[11],rdh[10],rdh[9],rdh[8],
		  rdh[7],rdh[6],rdh[5],rdh[4],rdh[3],rdh[2],rdh[1],rdh[0]}),
	.dout	(cf_hi_r)
);
lsu_sed_dp_prty_macro__width_8 pchkf_hi_c  (
	.din	({ecc[13],ecc[12],ecc[11],ecc[10],ecc[9],ecc[8],ecc[7],1'b0}),
	.dout	(cf_hi_c)
);

// C1 - lo
lsu_sed_dp_prty_macro__width_16 pchk1_lo_l  (
	.din	({1'b0   ,rdl[30],1'b0   ,rdl[28],1'b0   ,rdl[26],rdl[25],1'b0   ,
		  rdl[23],1'b0   ,rdl[21],1'b0   ,rdl[19],1'b0   ,rdl[17],1'b0}),
	.dout	(c1_lo_l)
);
lsu_sed_dp_prty_macro__width_16 pchk1_lo_r  (
	.din	({rdl[15],ecc[0],rdl[13],1'b0   ,rdl[11],rdl[10],1'b0   ,rdl[8],
		  1'b0   ,rdl[6],1'b0   ,rdl[4],rdl[3],1'b0   ,rdl[1],rdl[0]}),
	.dout	(c1_lo_r)
);

// C2 - lo
lsu_sed_dp_prty_macro__width_16 pchk2_lo_l  (
	.din	({rdl[31],1'b0   ,1'b0   ,rdl[28],rdl[27],1'b0   ,rdl[25],rdl[24],
		  1'b0   ,1'b0   ,rdl[21],rdl[20],1'b0   ,1'b0,rdl[17],rdl[16]}),
	.dout	(c2_lo_l)
);
lsu_sed_dp_prty_macro__width_16 pchk2_lo_r  (
	.din	({ecc[1],1'b0   ,rdl[13],rdl[12],1'b0   ,rdl[10],rdl[9],1'b0   ,
		  1'b0   ,rdl[6],rdl[5],1'b0   ,rdl[3],rdl[2],1'b0   ,rdl[0]}),
	.dout	(c2_lo_r)
);

// C4 - lo
lsu_sed_dp_prty_macro__width_16 pchk4_lo_l  (
	.din	({rdl[31],rdl[30],rdl[29],1'b0   ,1'b0   ,1'b0   ,rdl[25],rdl[24],
		  rdl[23],rdl[22],1'b0   ,1'b0   ,1'b0   ,1'b0,rdl[17],rdl[16]}),
	.dout	(c4_lo_l)
);
lsu_sed_dp_prty_macro__width_16 pchk4_lo_r  (
	.din	({rdl[15],rdl[14],ecc[2],1'b0   ,1'b0   ,rdl[10],rdl[9],rdl[8],
		  rdl[7],1'b0   ,1'b0   ,1'b0   ,rdl[3],rdl[2],rdl[1],1'b0   }),
	.dout	(c4_lo_r)
);

// C8 - lo
lsu_sed_dp_prty_macro__width_8 pchk8_lo_l  (
	.din	({rdl[25],rdl[24],rdl[23],rdl[22],rdl[21],rdl[20],rdl[19],rdl[18]}),
	.dout	(c8_lo_l)
);
lsu_sed_dp_prty_macro__width_8 pchk8_lo_r  (
	.din	({ecc[3],rdl[10],rdl[9],rdl[8],rdl[7],rdl[6],rdl[5],rdl[4]}),
	.dout	(c8_lo_r)
);

// C16 - lo
lsu_sed_dp_prty_macro__width_8 pchk16_lo_r  (
	.din	({ecc[4],rdl[17],rdl[16],rdl[15],rdl[14],rdl[13],rdl[12],rdl[11]}),
	.dout	(c16_lo_r)
);

// C32 - lo
lsu_sed_dp_prty_macro__width_8 pchk32_lo_l  (
	.din	({rdl[31],rdl[30],rdl[29],rdl[28],rdl[27],rdl[26],1'b0   ,ecc[5]}),
	.dout	(c32_lo_l)
);

// CF - lo
lsu_sed_dp_prty_macro__width_16 pchkf_lo_l  (
	.din	({rdl[31],rdl[30],rdl[29],rdl[28],rdl[27],rdl[26],rdl[25],rdl[24],
		  rdl[23],rdl[22],rdl[21],rdl[20],rdl[19],rdl[18],rdl[17],rdl[16]}),
	.dout	(cf_lo_l)
);
lsu_sed_dp_prty_macro__width_16 pchkf_lo_r  (
	.din	({rdl[15],rdl[14],rdl[13],rdl[12],rdl[11],rdl[10],rdl[9],rdl[8],
		  rdl[7],rdl[6],rdl[5],rdl[4],rdl[3],rdl[2],rdl[1],rdl[0]}),
	.dout	(cf_lo_r)
);
lsu_sed_dp_prty_macro__width_8 pchkf_lo_c  (
	.din	({ecc[6],ecc[5],ecc[4],ecc[3],ecc[2],ecc[1],ecc[0],1'b0}),
	.dout	(cf_lo_c)
);

lsu_sed_dp_msff_macro__stack_42l__width_26 dff_prty_bits   (
	.scan_in(dff_prty_bits_scanin),
	.scan_out(dff_prty_bits_scanout),
	.din	({c32_hi_l,c32_lo_l,c1_hi_l,c1_lo_l,c2_hi_l,c2_lo_l,c4_hi_l,c4_lo_l,
		  cf_hi_l,cf_lo_l,c8_hi_l,c8_lo_l,
		  cf_hi_c,cf_lo_c,
		  c16_hi_r,c16_lo_r,c1_hi_r,c1_lo_r,c2_hi_r,c2_lo_r,c4_hi_r,c4_lo_r,
		  c8_hi_r,c8_lo_r,cf_hi_r,cf_lo_r
		}),
	.dout	({sed_c32_hi,sed_c32_lo,sed_c1_hi[1],sed_c1_lo[1],sed_c2_hi[1],sed_c2_lo[1],sed_c4_hi[1],sed_c4_lo[1],
		  sed_cf_hi[1],sed_cf_lo[1],sed_c8_hi[1],sed_c8_lo[1],
		  sed_cf_hi[2],sed_cf_lo[2],
		  sed_c16_hi[0],sed_c16_lo[0],sed_c1_hi[0],sed_c1_lo[0],sed_c2_hi[0],sed_c2_lo[0],sed_c4_hi[0],sed_c4_lo[0],
		  sed_c8_hi[0],sed_c8_lo[0],sed_cf_hi[0],sed_cf_lo[0]
		}),
	.clk    (l2clk),
	.en	(sbc_ramout_clken),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
assign sed_c16_hi[1] = sed_c8_hi[1];
assign sed_c16_lo[1] = sed_c8_lo[1];

////////////////////////////////////////////////////////////////////////////////
// stb_ram output flops and correction xors

lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 dff_rd_data_0     (
	.scan_in(dff_rd_data_0_scanin),
	.scan_out(dff_rd_data_0_scanout),
	.din	({stb_ram_rd_cparity,stb_ram_rd_ctl[2],stb_ram_rd_data[63:48],stb_ram_rd_ecc[13:7],1'b0,     stb_ram_rd_data[47:32]}),
	.dout	({stb_ram_cparity,   stb_ram_ctl[2],   stb_ram_data[63:48],   stb_ram_ecc[13:7],   unused[0],stb_ram_data[47:32]}),
	.clk    (l2clk),
	.en	(sbc_ramout_clken),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 dff_rd_data_1     (
	.scan_in(dff_rd_data_1_scanin),
	.scan_out(dff_rd_data_1_scanout),
	.din	({stb_ram_rd_ctl[1:0],stb_ram_rd_data[31:16],stb_ram_rd_ecc[6:0],1'b0,     stb_ram_rd_data[15:0]}),
	.dout	({stb_ram_ctl[1:0],   stb_ram_data[31:16],   stb_ram_ecc[6:0],   unused[1],stb_ram_data[15:0]}),
	.clk    (l2clk),
	.en	(sbc_ramout_clken),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_sed_dp_xnor_macro__stack_32c__width_32 ecc_xnor_0   (
	.din0	(stb_ram_data[63:32]),
	.din1	(sec_corr_bit[63:32]),
	.dout	(stb_ram_data_corr_[63:32])
);
lsu_sed_dp_inv_macro__stack_32c__width_32 ecc_inv_0   (
	.din	(stb_ram_data_corr_[63:32]),
	.dout	(stb_ram_data_corr[63:32])
);
lsu_sed_dp_xnor_macro__stack_32c__width_32 ecc_xnor_1   (
	.din0	(stb_ram_data[31:0]),
	.din1	(sec_corr_bit[31:0]),
	.dout	(stb_ram_data_corr_[31:0])
);
lsu_sed_dp_inv_macro__stack_32c__width_32 ecc_inv_1   (
	.din	(stb_ram_data_corr_[31:0]),
	.dout	(stb_ram_data_corr[31:0])
);

////////////////////////////////////////////////////////////////////////////////
// STB diagnostic read and bist muxing

lsu_sed_dp_and_macro__ports_2__stack_32c__width_32 def_value_mx    (
	.din0	({4{bist_cmp_data[7:0]}}),
	.din1	({32{mbi_run}}),	
	.dout	(def_value[31:0])
);

lsu_sed_dp_mux_macro__mux_aope__ports_3__stack_32c__width_32 stb_diag_mux1_0     (
	.din0	(stb_ram_data[63:32]),
	.din1	({def_value[31:16],stb_cam_data[7:0],stb_cam_data[44:37]}),	
	.din2	(def_value[31:0]),
	.sel0	(dcc_stb_data_rd_w3),
	.sel1	(dcc_stb_addr_sel_w3),
	.dout	(stb_diag_rd_data[63:32])
);
lsu_sed_dp_mux_macro__mux_aonpe__ports_5__stack_32c__width_32 stb_diag_mux1_1     (
	.din0	(stb_ram_data[31:0]),
	.din1	({def_value[31:14],stb_ram_ecc[13:0]}),	
	.din2	({def_value[31:4],stb_ram_cparity,stb_ram_ctl[2:0]}),	
	.din3	({stb_cam_data[36:8],def_value[2:0]}),	
	.din4	({def_value[31:3],sbc_diag_wptr_w3[2:0]}),
	.sel0	(dcc_stb_data_rd_w3),
	.sel1	(dcc_stb_ecc_rd_w3),
	.sel2	(dcc_stb_ctl_rd_w3),
	.sel3	(dcc_stb_addr_sel_w3),
	.sel4	(dcc_stb_ptr_rd_w3),
	.dout	(stb_diag_rd_data[31:0])
);

lsu_sed_dp_cmp_macro__width_16 bist_cmp_0  (
	.din0	({2{bist_cmp_data[7:0]}}),
	.din1	(stb_diag_rd_data[63:48]),
	.dout	(sed_bist_cmp_0)
);
lsu_sed_dp_cmp_macro__width_16 bist_cmp_1  (
	.din0	({2{bist_cmp_data[7:0]}}),
	.din1	(stb_diag_rd_data[47:32]),
	.dout	(sed_bist_cmp_1)
);
lsu_sed_dp_cmp_macro__width_16 bist_cmp_2  (
	.din0	({2{bist_cmp_data[7:0]}}),
	.din1	(stb_diag_rd_data[31:16]),
	.dout	(sed_bist_cmp_2)
);
lsu_sed_dp_cmp_macro__width_16 bist_cmp_3  (
	.din0	({2{bist_cmp_data[7:0]}}),
	.din1	(stb_diag_rd_data[15:0]),
	.dout	(sed_bist_cmp_3)
);

lsu_sed_dp_buff_macro__stack_32c__width_32 ldxa_asi_data_buf_0   (
	.din	(stb_diag_rd_data[63:32]),
	.dout	(stb_ldxa_asi_data_w[63:32])
);
lsu_sed_dp_buff_macro__stack_32c__width_32 ldxa_asi_data_buf_1   (
	.din	(stb_diag_rd_data[31:0]),
	.dout	(stb_ldxa_asi_data_w[31:0])
);

// fixscan start:
assign dff_prty_bits_scanin      = scan_in                  ;
assign dff_rd_data_0_scanin      = dff_prty_bits_scanout    ;
assign dff_rd_data_1_scanin      = dff_rd_data_0_scanout    ;
assign scan_out                  = dff_rd_data_1_scanout    ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_sed_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_sed_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module lsu_sed_dp_xor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_sed_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module lsu_sed_dp_buff_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module lsu_sed_dp_inv_macro__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


inv #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sed_dp_mux_macro__buffsel_none__dmux_4x__mux_aonpe__ports_2__width_14 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
  input [13:0] din0;
  input sel0;
  input [13:0] din1;
  input sel1;
  output [13:0] dout;


mux2s #(14)  d0_0 (
  .sel0(sel0),
  .sel1(sel1),
  .in0(din0[13:0]),
  .in1(din1[13:0]),
.dout(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sed_dp_msff_macro__stack_42l__width_26 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [24:0] so;

  input [25:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [25:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(26)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[25:0]),
.si({scan_in,so[24:0]}),
.so({so[24:0],scan_out}),
.q(dout[25:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [40:0] so;

  input [41:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [41:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(42)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[41:0]),
.si({scan_in,so[40:0]}),
.so({so[40:0],scan_out}),
.q(dout[41:0])
);


endmodule


//
//   xnor macro for ports = 2,3
//
//


module lsu_sed_dp_xnor_macro__stack_32c__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output [31:0] dout;


xnor2 #(32)  d0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout[31:0])
);


endmodule


//
//   invert macro
//
//


module lsu_sed_dp_inv_macro__stack_32c__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


inv #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module lsu_sed_dp_and_macro__ports_2__stack_32c__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output [31:0] dout;


and2 #(32)  d0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sed_dp_mux_macro__mux_aope__ports_3__stack_32c__width_32 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input sel0;
  input sel1;
  output [31:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
.dout(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_sed_dp_mux_macro__mux_aonpe__ports_5__stack_32c__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  input [31:0] din2;
  input sel2;
  input [31:0] din3;
  input sel3;
  input [31:0] din4;
  input sel4;
  output [31:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(32)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_sed_dp_cmp_macro__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output dout;


cmp #(16)  m0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module lsu_sed_dp_buff_macro__stack_32c__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_spd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_spd_dp (
  sbd_st_addr_b, 
  sbc_st_addr_new, 
  sbc_thread_b, 
  sbc_spd_clken, 
  sbc_tidb_eq_tidw, 
  sbc_inv_addr_prty, 
  sbc_cam_line_en_m, 
  stb_cam_data, 
  stb_ram_cparity, 
  dcc_bmask_parity_b, 
  spd_st_line_match, 
  stb_cam_perr, 
  stb_cparity_calc, 
  stb_cam_line_en_b, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  tcu_se_scancollar_in, 
  spc_aclk, 
  spc_bclk, 
  scan_out);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [39:3] st_addr_b;
wire dff_st_addr_w_scanin;
wire dff_st_addr_w_scanout;
wire [38:6] st_addr_w;
wire dff_last_line_0_scanin;
wire dff_last_line_0_scanout;
wire [38:6] last_line_0;
wire dff_last_line_1_scanin;
wire dff_last_line_1_scanout;
wire [38:6] last_line_1;
wire dff_last_line_2_scanin;
wire dff_last_line_2_scanout;
wire [38:6] last_line_2;
wire dff_last_line_3_scanin;
wire dff_last_line_3_scanout;
wire [38:6] last_line_3;
wire dff_last_line_4_scanin;
wire dff_last_line_4_scanout;
wire [38:6] last_line_4;
wire dff_last_line_5_scanin;
wire dff_last_line_5_scanout;
wire [38:6] last_line_5;
wire dff_last_line_6_scanin;
wire dff_last_line_6_scanout;
wire [38:6] last_line_6;
wire dff_last_line_7_scanin;
wire dff_last_line_7_scanout;
wire [38:6] last_line_7;
wire [38:6] last_line;
wire [38:6] cmp_addr;
wire line_match_38_23;
wire line_match_22_7;
wire line_match_6;
wire pa_b39_b_;
wire addr_parity_hi;
wire addr_parity_lo;
wire stb_cparity_calc_;
wire rd_p0;
wire rd_p1;
wire cam_perr_;
wire dff_cam_line_en_b_scanin;
wire dff_cam_line_en_b_scanout;


input	[39:3]	sbd_st_addr_b;

input	[7:0]	sbc_st_addr_new;
input	[7:0]	sbc_thread_b;
input		sbc_spd_clken;
input		sbc_tidb_eq_tidw;
input		sbc_inv_addr_prty;
input	[7:0]	sbc_cam_line_en_m;

input	[44:0]	stb_cam_data;
input		stb_ram_cparity;

input		dcc_bmask_parity_b;

output		spd_st_line_match;
output		stb_cam_perr;
output		stb_cparity_calc;
output	[7:0]	stb_cam_line_en_b;

// Globals
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input		tcu_se_scancollar_in;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

// scan renames
assign stop = 1'b0;
// end scan

lsu_spd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);


////////////////////////////////////////////////////////////////////////////////
// Address staging and compare for store pipelining.
// For a 64B line, addr[5:0] do not compare.  IO stores are not pipelined, so
// PA[39] does not need to factor into the compare.

lsu_spd_dp_buff_macro__rep_1__stack_40c__width_37 st_addr_b_buf   (
	.din	(sbd_st_addr_b[39:3]),
	.dout	(st_addr_b[39:3])
);

lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_st_addr_w     (
	.scan_in(dff_st_addr_w_scanin),
	.scan_out(dff_st_addr_w_scanout),
	.din	(st_addr_b[38:6]),
	.dout	(st_addr_w[38:6]),
	.clk    (l2clk),
	.en	(sbc_spd_clken),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_last_line_0     (
	.scan_in(dff_last_line_0_scanin),
	.scan_out(dff_last_line_0_scanout),
	.din    (st_addr_w[38:6]),
	.dout	(last_line_0[38:6]),
	.clk    (l2clk),
	.en	(sbc_st_addr_new[0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_last_line_1     (
	.scan_in(dff_last_line_1_scanin),
	.scan_out(dff_last_line_1_scanout),
	.din    (st_addr_w[38:6]),
	.dout	(last_line_1[38:6]),
	.clk    (l2clk),
	.en	(sbc_st_addr_new[1]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_last_line_2     (
	.scan_in(dff_last_line_2_scanin),
	.scan_out(dff_last_line_2_scanout),
	.din    (st_addr_w[38:6]),
	.dout	(last_line_2[38:6]),
	.clk    (l2clk),
	.en	(sbc_st_addr_new[2]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_last_line_3     (
	.scan_in(dff_last_line_3_scanin),
	.scan_out(dff_last_line_3_scanout),
	.din    (st_addr_w[38:6]),
	.dout	(last_line_3[38:6]),
	.clk    (l2clk),
	.en	(sbc_st_addr_new[3]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_last_line_4     (
	.scan_in(dff_last_line_4_scanin),
	.scan_out(dff_last_line_4_scanout),
	.din    (st_addr_w[38:6]),
	.dout	(last_line_4[38:6]),
	.clk    (l2clk),
	.en	(sbc_st_addr_new[4]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_last_line_5     (
	.scan_in(dff_last_line_5_scanin),
	.scan_out(dff_last_line_5_scanout),
	.din    (st_addr_w[38:6]),
	.dout	(last_line_5[38:6]),
	.clk    (l2clk),
	.en	(sbc_st_addr_new[5]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_last_line_6     (
	.scan_in(dff_last_line_6_scanin),
	.scan_out(dff_last_line_6_scanout),
	.din    (st_addr_w[38:6]),
	.dout	(last_line_6[38:6]),
	.clk    (l2clk),
	.en	(sbc_st_addr_new[6]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 dff_last_line_7     (
	.scan_in(dff_last_line_7_scanin),
	.scan_out(dff_last_line_7_scanout),
	.din    (st_addr_w[38:6]),
	.dout	(last_line_7[38:6]),
	.clk    (l2clk),
	.en	(sbc_st_addr_new[7]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// mux out the last line of the store in B
lsu_spd_dp_mux_macro__left_3__mux_aonpe__ports_8__stack_40c__width_33 mux_last_line       (
	.din0	(last_line_0[38:6]),
	.din1	(last_line_1[38:6]),
	.din2	(last_line_2[38:6]),
	.din3	(last_line_3[38:6]),
	.din4	(last_line_4[38:6]),
	.din5	(last_line_5[38:6]),
	.din6	(last_line_6[38:6]),
	.din7	(last_line_7[38:6]),
	.sel0	(sbc_thread_b[0]),
	.sel1	(sbc_thread_b[1]),
	.sel2	(sbc_thread_b[2]),
	.sel3	(sbc_thread_b[3]),
	.sel4	(sbc_thread_b[4]),
	.sel5	(sbc_thread_b[5]),
	.sel6	(sbc_thread_b[6]),
	.sel7	(sbc_thread_b[7]),
	.dout	(last_line[38:6])
);

lsu_spd_dp_mux_macro__left_3__mux_aope__ports_2__stack_40c__width_33 mux_cmp_addr      (
	.din0	(st_addr_w[38:6]),
	.din1	(last_line[38:6]),
	.sel0	(sbc_tidb_eq_tidw),
	.dout	(cmp_addr[38:6])
);

lsu_spd_dp_cmp_macro__width_16 st_addr_cmp0  (
	.din0	(st_addr_b[38:23]),
	.din1	(cmp_addr[38:23]),
	.dout	(line_match_38_23)
);
lsu_spd_dp_cmp_macro__width_16 st_addr_cmp1  (
	.din0	(st_addr_b[22:7]),
	.din1	(cmp_addr[22:7]),
	.dout	(line_match_22_7)
);
lsu_spd_dp_xnor_macro__width_1 st_addr_cmp2  (
	.din0	(st_addr_b[6]),
	.din1	(cmp_addr[6]),
	.dout	(line_match_6)
);
lsu_spd_dp_inv_macro__width_1 pa_b39_inv  (
	.din	(st_addr_b[39]),
	.dout	(pa_b39_b_)
);

lsu_spd_dp_and_macro__ports_4__width_1 st_addr_cmp   (
	.din0	(line_match_38_23),
	.din1	(line_match_22_7),
	.din2	(line_match_6),
	.din3	(pa_b39_b_),		// IO stores cannot pipeline
	.dout	(spd_st_line_match)
);

////////////////////////////////////////////////////////////////////////////////
// Parity generation for stb_cam.  Timing does not allow for parity
// to be written into the CAM.  The parity is generated in the next cycle and
// written to the RAM. 

// in this physical order : dcc_bmask_parity_b,st_addr_b[39:3]

lsu_spd_dp_prty_macro__width_8 cam_wr_p0  (
	.din	({dcc_bmask_parity_b,sbc_inv_addr_prty,1'b0,st_addr_b[39:35]}),
	.dout	(addr_parity_hi)
);
lsu_spd_dp_prty_macro__width_32 cam_wr_p1  (
	.din	(st_addr_b[34:3]),
	.dout	(addr_parity_lo)
);
lsu_spd_dp_xnor_macro__ports_2__width_1 camwr_parity_bar  (
	.din0	(addr_parity_hi),
	.din1	(addr_parity_lo),
	.dout	(stb_cparity_calc_)
);
lsu_spd_dp_inv_macro__width_1 camwr_parity  (
	.din	(stb_cparity_calc_),
	.dout	(stb_cparity_calc)
);

///////////////////////////////////////////
// Parity error detection for stb_cam
// bits in this phyiscal order: stb_cam_data[7:0],2'b00,stb_cam_data[44:8],stb_ram_cparity

lsu_spd_dp_prty_macro__width_32 cam_rd_p0  (
	.din	({stb_cam_data[7:0],stb_cam_data[44:23],2'b00}),
	.dout	(rd_p0)
);
lsu_spd_dp_prty_macro__width_16 cam_rd_p1  (
	.din	({stb_cam_data[22:8],stb_ram_cparity}),
	.dout	(rd_p1)
);
lsu_spd_dp_xnor_macro__ports_2__width_1 cam_rd_perr   (
	.din0	(rd_p0),
	.din1	(rd_p1),
	.dout	(cam_perr_)
);
lsu_spd_dp_inv_macro__width_1 buf_cam_perr  (
	.din	(cam_perr_),
	.dout	(stb_cam_perr)
);

///////////////////////////////////////////
// flops for stb_cam_line_en_b
lsu_spd_dp_msff_macro__stack_8l__width_8 dff_cam_line_en_b    (
	.scan_in(dff_cam_line_en_b_scanin),
	.scan_out(dff_cam_line_en_b_scanout),
	.din    (sbc_cam_line_en_m[7:0]),
	.dout	(stb_cam_line_en_b[7:0]),
	.clk    (l2clk),
	.en	(1'b1),
	.se	(tcu_se_scancollar_in),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// fixscan start:
assign dff_st_addr_w_scanin      = scan_in                  ;
assign dff_last_line_0_scanin    = dff_st_addr_w_scanout    ;
assign dff_last_line_1_scanin    = dff_last_line_0_scanout  ;
assign dff_last_line_2_scanin    = dff_last_line_1_scanout  ;
assign dff_last_line_3_scanin    = dff_last_line_2_scanout  ;
assign dff_last_line_4_scanin    = dff_last_line_3_scanout  ;
assign dff_last_line_5_scanin    = dff_last_line_4_scanout  ;
assign dff_last_line_6_scanin    = dff_last_line_5_scanout  ;
assign dff_last_line_7_scanin    = dff_last_line_6_scanout  ;
assign dff_cam_line_en_b_scanin  = dff_last_line_7_scanout  ;
assign scan_out                  = dff_cam_line_en_b_scanout;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_spd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module lsu_spd_dp_buff_macro__rep_1__stack_40c__width_37 (
  din, 
  dout);
  input [36:0] din;
  output [36:0] dout;


buff #(37)  d0_0 (
.in(din[36:0]),
.out(dout[36:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_spd_dp_msff_macro__left_3__stack_40c__width_33 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [31:0] so;

  input [32:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [32:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(33)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[32:0]),
.si({scan_in,so[31:0]}),
.so({so[31:0],scan_out}),
.q(dout[32:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_spd_dp_mux_macro__left_3__mux_aonpe__ports_8__stack_40c__width_33 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [32:0] din0;
  input sel0;
  input [32:0] din1;
  input sel1;
  input [32:0] din2;
  input sel2;
  input [32:0] din3;
  input sel3;
  input [32:0] din4;
  input sel4;
  input [32:0] din5;
  input sel5;
  input [32:0] din6;
  input sel6;
  input [32:0] din7;
  input sel7;
  output [32:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(33)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
  .in2(din2[32:0]),
  .in3(din3[32:0]),
  .in4(din4[32:0]),
  .in5(din5[32:0]),
  .in6(din6[32:0]),
  .in7(din7[32:0]),
.dout(dout[32:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_spd_dp_mux_macro__left_3__mux_aope__ports_2__stack_40c__width_33 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [32:0] din0;
  input [32:0] din1;
  input sel0;
  output [32:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(33)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
.dout(dout[32:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_spd_dp_cmp_macro__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output dout;


cmp #(16)  m0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout)
);


endmodule


//
//   xnor macro for ports = 2,3
//
//


module lsu_spd_dp_xnor_macro__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xnor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module lsu_spd_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module lsu_spd_dp_and_macro__ports_4__width_1 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  input [0:0] din3;
  output [0:0] dout;


and4 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.in3(din3[0:0]),
.out(dout[0:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_spd_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_spd_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   xnor macro for ports = 2,3
//
//


module lsu_spd_dp_xnor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xnor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_spd_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_spd_dp_msff_macro__stack_8l__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_tgc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_tgc_ctl (
  dva_valid_m, 
  dva_valid2_m, 
  lsu_va_m, 
  lsu_va_b12to11_m, 
  exu_lsu_address_e, 
  dcc_ld_inst_vld_m, 
  dcc_dva_din_e, 
  dcc_dva_din2_e, 
  tgd_bist_compare, 
  tgc_cache_way_vld_m, 
  tgc_cache_way_vld2_m, 
  tgc_verr_b, 
  tgc_way_sel_m, 
  tgc_dva_rd_addr_e, 
  tgc_dva_din, 
  lsu_mbi_dva_fail, 
  lsu_mbi_dta_fail, 
  lsu_mbi_dtb_fail, 
  mbi_run, 
  mbi_cambist_run, 
  mbi_wdata, 
  mbi_cmpsel, 
  mbi_addr, 
  mbi_dta_read_en, 
  mbi_dva_read_en, 
  mbi_dtb_read_en, 
  bist_wdata_1, 
  bist_cmp_data, 
  bist_cmpsel_1, 
  bist_cmpsel_2, 
  bist_addr_1, 
  bist_dta_cmp_en, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  scan_out, 
  lsu_lsu_pmen);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire ld_vld_m_clken;
wire tgc_mbi_run;
wire l1clk_pm1;
wire [3:0] verr_m;
wire dff_way_vld_scanin;
wire dff_way_vld_scanout;
wire [8:5] local_bist_addr_1;
wire dva_fail;
wire bist_dva_cmp_en;
wire dta_fail;
wire dtb_fail;
wire bist_dtb_cmp_en;
wire dff_bist_fail_scanin;
wire dff_bist_fail_scanout;
wire [7:0] wdata_or_addr;
wire dff_bist_scanin;
wire dff_bist_scanout;
wire bist_dta_rd_1;
wire dtb_read_en;
wire bist_dtb_rd_1;
wire [7:0] cmp_data_in;
wire bist_dta_rd_2;
wire bist_dtb_rd_2;
wire [7:0] bist_wdata_2;
wire spares_scanin;
wire spares_scanout;


input	[15:0]	dva_valid_m;
input	[15:0]	dva_valid2_m; 	// redundant copies

input	[5:4]	lsu_va_m;
input	[12:11]	lsu_va_b12to11_m;

input	[10:6]	exu_lsu_address_e;

input		dcc_ld_inst_vld_m;
input		dcc_dva_din_e;
input		dcc_dva_din2_e;

input		tgd_bist_compare;

output	[3:0]	tgc_cache_way_vld_m;
output	[3:0]	tgc_cache_way_vld2_m;
output	[3:0]	tgc_verr_b;
output	[1:0]	tgc_way_sel_m;
output	[10:6]	tgc_dva_rd_addr_e;
output	[31:0]	tgc_dva_din;

output		lsu_mbi_dva_fail;
output		lsu_mbi_dta_fail;
output		lsu_mbi_dtb_fail;

// BIST
input		mbi_run;
input		mbi_cambist_run;
input	[7:0]	mbi_wdata;
input	[1:0]	mbi_cmpsel;		// encoded
input	[8:0]	mbi_addr;
input		mbi_dta_read_en;
input		mbi_dva_read_en;
input		mbi_dtb_read_en;
output	[7:0]	bist_wdata_1;
output	[7:0]	bist_cmp_data;
output	[1:0]	bist_cmpsel_1;
output		bist_cmpsel_2;
output	[8:5]	bist_addr_1;
output		bist_dta_cmp_en;


input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

input		lsu_lsu_pmen;

// scan renames
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
// end scan

//////////////////////////////
// Clock headers
//////////////////////////////

// Enable flops only when load is in M or during bist
assign ld_vld_m_clken = dcc_ld_inst_vld_m | mbi_run | tgc_mbi_run | ~lsu_lsu_pmen;

lsu_tgc_ctl_l1clkhdr_ctl_macro clkgen0 (
        .l2clk  (l2clk                          ),
        .l1en   (ld_vld_m_clken                 ),
        .l1clk  (l1clk_pm1                      ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

//////////////////////////////

// Valid bit muxing

assign tgc_cache_way_vld_m[3:0] = ({4{(lsu_va_m[5:4] == 2'b00)}} & dva_valid_m[3:0])  |
                                  ({4{(lsu_va_m[5:4] == 2'b01)}} & dva_valid_m[7:4])  |
                                  ({4{(lsu_va_m[5:4] == 2'b10)}} & dva_valid_m[11:8]) |
                                  ({4{(lsu_va_m[5:4] == 2'b11)}} & dva_valid_m[15:12]); 

assign tgc_cache_way_vld2_m[3:0] = ({4{(lsu_va_m[5:4] == 2'b00)}} & dva_valid2_m[3:0])  |
                                   ({4{(lsu_va_m[5:4] == 2'b01)}} & dva_valid2_m[7:4])  |
                                   ({4{(lsu_va_m[5:4] == 2'b10)}} & dva_valid2_m[11:8]) |
                                   ({4{(lsu_va_m[5:4] == 2'b11)}} & dva_valid2_m[15:12]); 

// Valid bit error detection

assign verr_m[0] = tgc_cache_way_vld_m[0] ^ tgc_cache_way_vld2_m[0];
assign verr_m[1] = tgc_cache_way_vld_m[1] ^ tgc_cache_way_vld2_m[1];
assign verr_m[2] = tgc_cache_way_vld_m[2] ^ tgc_cache_way_vld2_m[2];
assign verr_m[3] = tgc_cache_way_vld_m[3] ^ tgc_cache_way_vld2_m[3];

lsu_tgc_ctl_msff_ctl_macro__width_4 dff_way_vld  (
	.scan_in(dff_way_vld_scanin),
	.scan_out(dff_way_vld_scanout),
	.din	(verr_m[3:0]),
	.dout	(tgc_verr_b[3:0]),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);

// Valid array data in

assign tgc_dva_din[31:0] = tgc_mbi_run ? {4{mbi_wdata[7:0]}} : {{16{dcc_dva_din2_e}},{16{dcc_dva_din_e}}};

// This is the tag way select used for diagnostic and bist reads
assign tgc_way_sel_m[1:0] = tgc_mbi_run ? local_bist_addr_1[8:7] : lsu_va_b12to11_m[12:11];

// BIST compare results
assign dva_fail = bist_dva_cmp_en & ({dva_valid_m[15:0],dva_valid2_m[15:0]} != {4{bist_wdata_1[7:0]}});
assign dta_fail = bist_dta_cmp_en & ~tgd_bist_compare;
assign dtb_fail = bist_dtb_cmp_en & ~tgd_bist_compare & ~mbi_cambist_run;

lsu_tgc_ctl_msff_ctl_macro__width_3 dff_bist_fail  (
	.scan_in(dff_bist_fail_scanin),
	.scan_out(dff_bist_fail_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dta_fail,        dtb_fail,        dva_fail}),
	.dout	({lsu_mbi_dta_fail,lsu_mbi_dtb_fail,lsu_mbi_dva_fail}),
  .siclk(siclk),
  .soclk(soclk)
);

//
// Address muxing for DVA array
//
assign tgc_dva_rd_addr_e[10:6] = tgc_mbi_run ? mbi_addr[4:0] : exu_lsu_address_e[10:6];

////////////////////////////////////////////////////////////////////////////////
// Flops for bist signals

assign wdata_or_addr[7:0] = mbi_cambist_run ?  mbi_addr[7:0] : mbi_wdata[7:0];

lsu_tgc_ctl_msff_ctl_macro__width_38 dff_bist  (
	.scan_in(dff_bist_scanin),
	.scan_out(dff_bist_scanout),
	.l1clk	(l1clk_pm1),
	.din	({mbi_run,
		  mbi_dta_read_en,    bist_dta_rd_1,
		  mbi_dtb_read_en,    dtb_read_en,
                  bist_dtb_rd_1,      mbi_dva_read_en,    
		  wdata_or_addr[7:0], bist_wdata_1[7:0],
                  mbi_cmpsel[1:0],    bist_cmpsel_1[0],
		  mbi_addr[8:5],      cmp_data_in[7:0]
		}),
	.dout	({tgc_mbi_run,
		  bist_dta_rd_1,      bist_dta_rd_2,
		  dtb_read_en,        bist_dtb_rd_1,
		  bist_dtb_rd_2,      bist_dva_cmp_en,
		  bist_wdata_1[7:0],  bist_wdata_2[7:0],
                  bist_cmpsel_1[1:0], bist_cmpsel_2,
		  local_bist_addr_1[8:5],bist_cmp_data[7:0]
		}),
  .siclk(siclk),
  .soclk(soclk)
);

assign cmp_data_in[7:0] = bist_dtb_rd_1 ? bist_wdata_2[7:0] : bist_wdata_1[7:0];

assign bist_addr_1[8:5] = local_bist_addr_1[8:5];
assign bist_dta_cmp_en = bist_dta_rd_2;
assign bist_dtb_cmp_en = bist_dtb_rd_2;


lsu_tgc_ctl_spare_ctl_macro__num_1 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);

// fixscan start:
assign dff_way_vld_scanin        = scan_in                  ;
assign dff_bist_fail_scanin      = dff_way_vld_scanout      ;
assign dff_bist_scanin           = dff_bist_fail_scanout    ;
assign spares_scanin             = dff_bist_scanout         ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module lsu_tgc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tgc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tgc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tgc_ctl_msff_ctl_macro__width_38 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [37:0] fdin;
wire [36:0] so;

  input [37:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [37:0] dout;
  output scan_out;
assign fdin[37:0] = din[37:0];


dff #(38)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[37:0]),
.si({scan_in,so[36:0]}),
.so({so[36:0],scan_out}),
.q(dout[37:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_tgc_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_tgd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_tgd_dp (
  dta_rdata_w0_m, 
  dta_rdata_w1_m, 
  dta_rdata_w2_m, 
  dta_rdata_w3_m, 
  tgc_cache_way_vld_m, 
  tgc_cache_way_vld2_m, 
  tgc_way_sel_m, 
  dcs_watchpoint_m, 
  dcs_context0_e, 
  dcs_context1_e, 
  dcc_rd_dt_diag_m, 
  dcc_rd_dt_diag_b, 
  dcc_tlb_tag0_read_b, 
  dcc_tlb_tag1_read_b, 
  dcc_tlb_data_read_b, 
  dcc_ld_inst_vld_m, 
  dcc_ldst_m_clken, 
  tlb_pgnum, 
  tlb_tte_data, 
  tlb_tte_tag, 
  tlb_tte_u_bit, 
  tlb_cam_hit, 
  tlb_context0_hit, 
  tlb_cam_mhit, 
  tld_prty_256m, 
  tld_prty_4m, 
  tld_prty_64k, 
  tld_prty_8k, 
  tld_prty_ctxt0, 
  tld_prty_ctxt1, 
  tld_tag_c0, 
  tld_tag_c1, 
  tlc_sel_tte_tag, 
  tlc_sel_demap_tag_c0, 
  tlc_sel_demap_tag_c1, 
  bist_cmp_data, 
  bist_dta_cmp_en, 
  bist_cmpsel_2, 
  lsu_va_m, 
  tgd_w0_parity_b, 
  tgd_w1_parity_b, 
  tgd_w2_parity_b, 
  tgd_w3_parity_b, 
  dta_rdata_w0_rep, 
  dta_rdata_w1_rep, 
  dta_rdata_w2_rep, 
  dta_rdata_w3_rep, 
  tgd_prty_256m_b, 
  tgd_prty_4m_b, 
  tgd_prty_64k_b, 
  tgd_prty_8k_b, 
  tgd_prty_ctxt0_b, 
  tgd_prty_ctxt1_b, 
  tgd_va_wp_47_16, 
  tgd_va_wp_15_3, 
  tgd_pa_wp_39_16, 
  tgd_pa_wp_15_3, 
  tgd_tag_c0, 
  tgd_tag_c1, 
  tlb_tag_parity, 
  tlb_pgsize, 
  tlb_tte_nfo_b, 
  tlb_tte_ie_b, 
  tlb_tte_cp_b, 
  tlb_tte_ebit_b, 
  tlb_tte_pbit_b, 
  tlb_tte_wbit_b, 
  tgd_ldxa_asi_data_b, 
  tgd_bist_compare, 
  lsu_mbi_tlb_data_cmp, 
  lsu_mbi_tlb_cam_hit, 
  lsu_mbi_tlb_cam_mhit, 
  lsu_mbi_tlb_ctxt0_hit, 
  lsu_mbi_tlb_valid, 
  lsu_mbi_tlb_used, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  tcu_se_scancollar_out, 
  spc_aclk, 
  spc_bclk, 
  scan_out);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire clk;
wire [1:0] w0_16b_parity_m;
wire [1:0] w1_16b_parity_m;
wire [1:0] w2_16b_parity_m;
wire [1:0] w3_16b_parity_m;
wire dff_16b_prty_w01_scanin;
wire dff_16b_prty_w01_scanout;
wire [1:0] w0_16b_parity_b;
wire [1:0] w1_16b_parity_b;
wire dff_16b_prty_w23_scanin;
wire dff_16b_prty_w23_scanout;
wire [1:0] w2_16b_parity_b;
wire [1:0] w3_16b_parity_b;
wire [3:0] tag_parity_b;
wire [31:0] tgd_diag_tag01_m;
wire [31:0] tgd_diag_tag23_m;
wire dff_diag_tag_scanin;
wire dff_diag_tag_scanout;
wire [31:0] tgd_diag_tag_b;
wire tte_data_va_27_22_v_;
wire tte_data_sz_1;
wire [12:0] tag_c0;
wire [12:0] tag_c1;
wire [63:0] ldxa_asi_data_b;
wire [47:3] va_m_buf;
wire dff_va_b_scanin;
wire dff_va_b_scanout;
wire [47:3] va_b;
wire dff_wpt_b_scanin;
wire dff_wpt_b_scanout;
wire [47:3] watchpoint_b;
wire va_wp_47_16;
wire va_wp_15_3;
wire pa_wp_39_16;
wire pa_wp_15_3;
wire [63:0] bist_mux_data;


input	[29:0]	dta_rdata_w0_m;
input	[29:0]	dta_rdata_w1_m;
input	[29:0]	dta_rdata_w2_m;
input	[29:0]	dta_rdata_w3_m;

input	[3:0]	tgc_cache_way_vld_m;
input	[3:0]	tgc_cache_way_vld2_m;
input	[1:0]	tgc_way_sel_m;

input	[47:3]	dcs_watchpoint_m;
input	[12:0]	dcs_context0_e;
input	[12:0]	dcs_context1_e;

input		dcc_rd_dt_diag_m;
input		dcc_rd_dt_diag_b;
input		dcc_tlb_tag0_read_b;
input		dcc_tlb_tag1_read_b;
input		dcc_tlb_data_read_b;
input		dcc_ld_inst_vld_m;
input		dcc_ldst_m_clken;

input	[39:13]	tlb_pgnum;
input	[37:0]	tlb_tte_data;		// for diag read muxing
input	[65:0]	tlb_tte_tag;		// for diag read muxing
input		tlb_tte_u_bit;		// for diag read muxing
input		tlb_cam_hit;
input		tlb_context0_hit;
input		tlb_cam_mhit;

input		tld_prty_256m;
input		tld_prty_4m;
input		tld_prty_64k;
input		tld_prty_8k;
input		tld_prty_ctxt0;
input		tld_prty_ctxt1;
input	[12:0]	tld_tag_c0;
input	[12:0]	tld_tag_c1;

input		tlc_sel_tte_tag;
input		tlc_sel_demap_tag_c0;
input		tlc_sel_demap_tag_c1;

input	[7:0]	bist_cmp_data;
input		bist_dta_cmp_en;
input		bist_cmpsel_2;

input	[47:3]	lsu_va_m;

output		tgd_w0_parity_b;
output		tgd_w1_parity_b;
output		tgd_w2_parity_b;
output		tgd_w3_parity_b;

output	[28:0]	dta_rdata_w0_rep;
output	[28:0]	dta_rdata_w1_rep;
output	[28:0]	dta_rdata_w2_rep;
output	[28:0]	dta_rdata_w3_rep;

//output		tgd_tte_tag_parity;
//output		tgd_tte_data_parity;
output		tgd_prty_256m_b;
output		tgd_prty_4m_b;
output		tgd_prty_64k_b;
output		tgd_prty_8k_b;
output		tgd_prty_ctxt0_b;
output		tgd_prty_ctxt1_b;


output		tgd_va_wp_47_16;
output		tgd_va_wp_15_3;
output		tgd_pa_wp_39_16;
output		tgd_pa_wp_15_3;

output	[12:0]	tgd_tag_c0;
output	[12:0]	tgd_tag_c1;

output		tlb_tag_parity;
output	[2:0]	tlb_pgsize;
output		tlb_tte_nfo_b;
output		tlb_tte_ie_b;
output		tlb_tte_cp_b;
output		tlb_tte_ebit_b;
output		tlb_tte_pbit_b;
output		tlb_tte_wbit_b;

output	[63:0]	tgd_ldxa_asi_data_b;

output		tgd_bist_compare;

output		lsu_mbi_tlb_data_cmp;
output		lsu_mbi_tlb_cam_hit;
output		lsu_mbi_tlb_cam_mhit;
output		lsu_mbi_tlb_ctxt0_hit;
output		lsu_mbi_tlb_valid;
output		lsu_mbi_tlb_used;


// Globals
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input		tcu_scan_en;
input		tcu_se_scancollar_out;
input 		spc_aclk;
input 		spc_bclk;
output		scan_out;

// scan renames
assign stop = 1'b0;
// end scan

lsu_tgd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);

assign clk = l2clk;

// TLB TTE defines
`define TAG_CNTX1_HI    65
`define TAG_CNTX1_LO    53
`define TAG_PID_HI      52
`define TAG_PID_LO      50
`define TAG_REAL        49
`define TAG_VA_47_28_HI 48
`define TAG_VA_47_28_LO 29
`define TAG_VA_27_22_HI 28
`define TAG_VA_27_22_LO 23
`define TAG_V           22 
`define TAG_VA_21_16_HI 21
`define TAG_VA_21_16_LO 16
`define TAG_VA_15_13_HI 15 
`define TAG_VA_15_13_LO 13
`define TAG_CNTX0_HI    12
`define TAG_CNTX0_LO     0

`define TAG_PARITY	    37
`define DATA_PARITY         36 
`define DATA_PA_39_28_HI    35
`define DATA_PA_39_28_LO    24
`define DATA_PA_27_22_HI    23
`define DATA_PA_27_22_LO    18
`define DATA_VA_27_22_V     17 
`define DATA_PA_21_16_HI    16
`define DATA_PA_21_16_LO    11
`define DATA_VA_21_16_V     10 
`define DATA_PA_15_13_HI     9
`define DATA_PA_15_13_LO     7
`define DATA_VA_15_13_V      6 
`define DATA_NFO             5 
`define DATA_IE              4 
`define DATA_CP              3 
`define DATA_E               2 
`define DATA_P               1 
`define DATA_W               0 

// Parity checking for tag.  Tag is available late in M.  Flopping all 4 tags into
// B would require 120 flops, but there is not enough time to check 30b parity in M.
// So, generate 16b parity in M and flop that result (2 flops/way).  Then finish the 
// check in B.

lsu_tgd_dp_prty_macro__width_16 w0_16b_p1  (
	.din	({2'b00,dta_rdata_w0_m[29:16]}),
	.dout	(w0_16b_parity_m[1])
);
lsu_tgd_dp_prty_macro__width_16 w0_16b_p0  (
	.din	(dta_rdata_w0_m[15:0]),
	.dout	(w0_16b_parity_m[0])
);

lsu_tgd_dp_prty_macro__width_16 w1_16b_p1  (
	.din	({2'b00,dta_rdata_w1_m[29:16]}),
	.dout	(w1_16b_parity_m[1])
);
lsu_tgd_dp_prty_macro__width_16 w1_16b_p0  (
	.din	(dta_rdata_w1_m[15:0]),
	.dout	(w1_16b_parity_m[0])
);

lsu_tgd_dp_prty_macro__width_16 w2_16b_p1  (
	.din	({2'b00,dta_rdata_w2_m[29:16]}),
	.dout	(w2_16b_parity_m[1])
);
lsu_tgd_dp_prty_macro__width_16 w2_16b_p0  (
	.din	(dta_rdata_w2_m[15:0]),
	.dout	(w2_16b_parity_m[0])
);

lsu_tgd_dp_prty_macro__width_16 w3_16b_p1  (
	.din	({2'b00,dta_rdata_w3_m[29:16]}),
	.dout	(w3_16b_parity_m[1])
);
lsu_tgd_dp_prty_macro__width_16 w3_16b_p0  (
	.din	(dta_rdata_w3_m[15:0]),
	.dout	(w3_16b_parity_m[0])
);

lsu_tgd_dp_msff_macro__width_4 dff_16b_prty_w01  (
	.scan_in(dff_16b_prty_w01_scanin),
	.scan_out(dff_16b_prty_w01_scanout),
	.se	(tcu_se_scancollar_out),
	.din	({w0_16b_parity_m[1:0],w1_16b_parity_m[1:0]}),
	.dout	({w0_16b_parity_b[1:0],w1_16b_parity_b[1:0]}),
	.en	(dcc_ld_inst_vld_m),
  .clk(clk),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_tgd_dp_msff_macro__width_4 dff_16b_prty_w23  (
	.scan_in(dff_16b_prty_w23_scanin),
	.scan_out(dff_16b_prty_w23_scanout),
	.se	(tcu_se_scancollar_out),
	.din	({w2_16b_parity_m[1:0],w3_16b_parity_m[1:0]}),
	.dout	({w2_16b_parity_b[1:0],w3_16b_parity_b[1:0]}),
	.en	(dcc_ld_inst_vld_m),
  .clk(clk),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_tgd_dp_xor_macro__width_4 prty_xor  (
	.din0	({w3_16b_parity_b[0],w2_16b_parity_b[0],w1_16b_parity_b[0],w0_16b_parity_b[0]}),
	.din1	({w3_16b_parity_b[1],w2_16b_parity_b[1],w1_16b_parity_b[1],w0_16b_parity_b[1]}),
	.dout	(tag_parity_b[3:0])
);
lsu_tgd_dp_buff_macro__width_4 prty_buf  (
	.din	(tag_parity_b[3:0]),
	.dout	({tgd_w3_parity_b,tgd_w2_parity_b,tgd_w1_parity_b,tgd_w0_parity_b})
);

// Mux for diagnostic read
lsu_tgd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_tag_way01      (
	.din0   ({dta_rdata_w1_m[29:0],tgc_cache_way_vld_m[1],tgc_cache_way_vld2_m[1]}),
	.din1   ({dta_rdata_w0_m[29:0],tgc_cache_way_vld_m[0],tgc_cache_way_vld2_m[0]}),
	.sel0	(tgc_way_sel_m[0]),
	.dout	(tgd_diag_tag01_m[31:0])
);
lsu_tgd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_tag_way23      (
	.din0   ({dta_rdata_w3_m[29:0],tgc_cache_way_vld_m[3],tgc_cache_way_vld2_m[3]}),
	.din1   ({dta_rdata_w2_m[29:0],tgc_cache_way_vld_m[2],tgc_cache_way_vld2_m[2]}),
	.sel0	(tgc_way_sel_m[0]),
	.dout	(tgd_diag_tag23_m[31:0])
);
lsu_tgd_dp_msff_macro__mux_pgpe__ports_2__stack_32l__width_32 dff_diag_tag     (
	.scan_in(dff_diag_tag_scanin),
	.scan_out(dff_diag_tag_scanout),
	.se	(tcu_se_scancollar_out),
	.din0	(tgd_diag_tag23_m[31:0]),
	.din1	(tgd_diag_tag01_m[31:0]),
	.sel0	(tgc_way_sel_m[1]),
	.dout	(tgd_diag_tag_b[31:0]),
	.en	(dcc_rd_dt_diag_m),
  .clk(clk),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Buffer tag to tlb
lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 buf_tag_w0    (
	.din	(dta_rdata_w0_m[28:0]),
	.dout	(dta_rdata_w0_rep[28:0])
);
lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 buf_tag_w1    (
	.din	(dta_rdata_w1_m[28:0]),
	.dout	(dta_rdata_w1_rep[28:0])
);
lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 buf_tag_w2    (
	.din	(dta_rdata_w2_m[28:0]),
	.dout	(dta_rdata_w2_rep[28:0])
);
lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 buf_tag_w3    (
	.din	(dta_rdata_w3_m[28:0]),
	.dout	(dta_rdata_w3_rep[28:0])
);

lsu_tgd_dp_inv_macro__width_1 inv_sz_mux  (
	.din	(tlb_tte_data[`DATA_VA_27_22_V]),
	.dout	(tte_data_va_27_22_v_)
);
lsu_tgd_dp_and_macro__ports_2__width_1 and_sz   (
	.din0	(tlb_tte_data[`DATA_VA_21_16_V]),
	.din1	(tte_data_va_27_22_v_),
	.dout	(tte_data_sz_1)
);

////////////////////////////////////////////////////////////////////////////
// tte_tag context muxing

// First level of muxing is done in lsu_tld_dp and comes in as tld_tag_c0 
// and tld_tag_c1.  

lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_14l__width_13 mx_tag_c0     (
	.din0	(tld_tag_c0[12:0]),
	.din1	(dcs_context1_e[12:0]),
	.din2	(dcs_context0_e[12:0]),
	.sel0	(tlc_sel_tte_tag),
	.sel1	(tlc_sel_demap_tag_c1),
	.dout	(tag_c0[12:0])
);
lsu_tgd_dp_buff_macro__stack_14l__width_13 buf_tag_c0  (
	.din	(tag_c0[12:0]),
	.dout	(tgd_tag_c0[12:0])
);

lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_14r__width_13 mx_tag_c1     (
	.din0	(tld_tag_c1[12:0]),
	.din1	(dcs_context0_e[12:0]),
	.din2	(dcs_context1_e[12:0]),
	.sel0	(tlc_sel_tte_tag),
	.sel1	(tlc_sel_demap_tag_c0),
	.dout	(tag_c1[12:0])
);
lsu_tgd_dp_buff_macro__stack_14r__width_13 buf_tag_c1  (
	.din	(tag_c1[12:0]),
	.dout	(tgd_tag_c1[12:0])
);

//////
// Data access read format (sun4v TTE) is
// V    NFO   PRTY     0       0       PA    IE    E   CP   0   P   0   W    0    SZ
// 63 |  62 |  61  | 60:56 | 55:40 | 39:13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5:3 | 2:0
//
// Tag read register format is
//  PID    R    P    U      0      VA    Context
// 63:61 | 60 | 59 | 58 | 57:48 | 47:13 | 12:0


// Mux the different ASI read sources that are on the right side of the LSU
lsu_tgd_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 mx_asi_b      (
	.din0	({32'd0,tgd_diag_tag_b[31:0]}),
	.din1	({tlb_tte_tag[`TAG_V],					// V
		  tlb_tte_data[`DATA_NFO],				// NFO
		  tlb_tte_data[`DATA_PARITY],				// PARITY
		  5'b0,							// SOFT
		  16'b0,
		  tlb_tte_data[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO],	// PA
		  tlb_tte_data[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO],
		  tlb_tte_data[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO],
		  tlb_tte_data[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO],
		  tlb_tte_data[`DATA_IE],				// IE
		  tlb_tte_data[`DATA_E],				// E
		  tlb_tte_data[`DATA_CP],				// CP
		  1'b0,							// CV
		  tlb_tte_data[`DATA_P],				// P
		  1'b0,							// EP
		  tlb_tte_data[`DATA_W],				// W
		  3'b0,
		  tlb_tte_data[`DATA_VA_27_22_V],			// SZ
		  tte_data_sz_1,tlb_tte_data[`DATA_VA_15_13_V]		// SZ
		}),
	.din2	({tlb_tte_tag[`TAG_PID_HI:`TAG_PID_LO],			// PID
		  tlb_tte_tag[`TAG_REAL],				// REAL
		  tlb_tte_data[`TAG_PARITY],				// PARITY
		  tlb_tte_u_bit,					// USED
		  10'b0,
		  tlb_tte_tag[`TAG_VA_47_28_HI:`TAG_VA_27_22_LO],
		  tlb_tte_tag[`TAG_VA_21_16_HI:`TAG_VA_21_16_LO],
		  tlb_tte_tag[`TAG_VA_15_13_HI:`TAG_VA_15_13_LO],
		  tlb_tte_tag[`TAG_CNTX0_HI:`TAG_CNTX0_LO]		// context
		}),
	.din3	({tlb_tte_tag[`TAG_PID_HI:`TAG_PID_LO],			// PID
		  tlb_tte_tag[`TAG_REAL],				// REAL
		  tlb_tte_data[`TAG_PARITY],				// PARITY
		  tlb_tte_u_bit,					// USED
		  10'b0,
		  tlb_tte_tag[`TAG_VA_47_28_HI:`TAG_VA_27_22_LO],
		  tlb_tte_tag[`TAG_VA_21_16_HI:`TAG_VA_21_16_LO],
		  tlb_tte_tag[`TAG_VA_15_13_HI:`TAG_VA_15_13_LO],
		  tlb_tte_tag[`TAG_CNTX1_HI:`TAG_CNTX1_LO]		// context
		}),
	.sel0	(dcc_rd_dt_diag_b),
	.sel1	(dcc_tlb_data_read_b),
	.sel2	(dcc_tlb_tag0_read_b),
	.sel3	(dcc_tlb_tag1_read_b),
	.dout	(ldxa_asi_data_b[63:0])
);

lsu_tgd_dp_buff_macro__rep_1__stack_64c__width_64 buf_asi_b    (
	.din	(ldxa_asi_data_b[63:0]),
	.dout	(tgd_ldxa_asi_data_b[63:0])
);

lsu_tgd_dp_buff_macro__left_19__minbuff_1__stack_64c__width_45 va_minbuf     (
	.din	(lsu_va_m[47:3]),
	.dout	(va_m_buf[47:3])
);

// VA staging
lsu_tgd_dp_msff_macro__left_13__stack_64c__width_51 dff_va_b    (
	.scan_in(dff_va_b_scanin),
	.scan_out(dff_va_b_scanout),
	.din	({va_m_buf[47:3],
		  tld_prty_256m  ,tld_prty_4m  ,tld_prty_64k  ,tld_prty_8k  ,tld_prty_ctxt0  ,tld_prty_ctxt1}),
	.dout	({va_b[47:3],
		  tgd_prty_256m_b,tgd_prty_4m_b,tgd_prty_64k_b,tgd_prty_8k_b,tgd_prty_ctxt0_b,tgd_prty_ctxt1_b}),
	.en	(dcc_ldst_m_clken),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

///////////////////////////////////////////////////////////////
// Watchpoint mux and compare is here so it's close to the TLB

lsu_tgd_dp_msff_macro__left_19__stack_64c__width_45 dff_wpt_b    (
	.scan_in(dff_wpt_b_scanin),
	.scan_out(dff_wpt_b_scanout),
	.din	(dcs_watchpoint_m[47:3]),
	.dout	(watchpoint_b[47:3]),
	.en	(dcc_ldst_m_clken),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

lsu_tgd_dp_cmp_macro__width_32 cmp_va_47_16  (
	.din0	(watchpoint_b[47:16]),
	.din1	(va_b[47:16]),
	.dout	(va_wp_47_16)
);
lsu_tgd_dp_cmp_macro__width_16 cmp_va_15_3  (
	.din0	({3'b0,watchpoint_b[15:3]}),
	.din1	({3'b0,va_b[15:3]}),
	.dout	(va_wp_15_3)
);

lsu_tgd_dp_cmp_macro__width_32 cmp_pa_39_16  (
	.din0	({8'b0,watchpoint_b[39:16]}),
	.din1	({8'b0,tlb_pgnum[39:16]}),
	.dout	(pa_wp_39_16)
);
lsu_tgd_dp_cmp_macro__width_16 cmp_pa_15_3  (
	.din0	({3'b0,watchpoint_b[15:3]}),
	.din1	({3'b0,tlb_pgnum[15:13],va_b[12:3]}),
	.dout	(pa_wp_15_3)
);

lsu_tgd_dp_buff_macro__width_4 wpt_buf  (
	.din	({    va_wp_47_16,    pa_wp_39_16,    va_wp_15_3,    pa_wp_15_3}),
	.dout	({tgd_va_wp_47_16,tgd_pa_wp_39_16,tgd_va_wp_15_3,tgd_pa_wp_15_3})
);

lsu_tgd_dp_buff_macro__rep_1__width_10 tte_buf  (
	.din	({tlb_tte_data[`TAG_PARITY],tlb_tte_data[`DATA_VA_27_22_V],
		  tlb_tte_data[`DATA_VA_21_16_V],tlb_tte_data[`DATA_VA_15_13_V],
		  tlb_tte_data[`DATA_NFO:`DATA_W]}),
	.dout	({tlb_tag_parity, tlb_pgsize[2:0],tlb_tte_nfo_b,tlb_tte_ie_b,
		  tlb_tte_cp_b,tlb_tte_ebit_b,tlb_tte_pbit_b,tlb_tte_wbit_b})
);

// BIST mux and tag comparator
lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_64c__width_64 bist_mx    (
	.din0	({{4{bist_cmp_data[7:0]}},bist_cmp_data[7:6],tgd_diag_tag_b[31:2]}),
	.din1	({bist_cmp_data[7:1],tlb_tte_u_bit,bist_cmp_data[7:5],tlb_tte_tag[52:50],
		  bist_cmp_data[1],tlb_tte_tag[48:0]}),
	.din2	({tlb_tte_tag[65:53],bist_cmp_data[2:0],bist_cmp_data[7:0],
		  bist_cmp_data[7:6],tlb_tte_data[37:0]}),	
	.sel0	(bist_dta_cmp_en),
	.sel1	(bist_cmpsel_2),
	.dout	(bist_mux_data[63:0])
);

lsu_tgd_dp_cmp_macro__width_64 bist_cmp  (
	.din0	({8{bist_cmp_data[7:0]}}),
	.din1	(bist_mux_data[63:0]),
	.dout	(tgd_bist_compare)
);

lsu_tgd_dp_cmp_macro__width_8 cambist_cmp  (
	.din0	({1'b0,bist_cmp_data[6:0]}),
	.din1	({1'b0,tlb_tte_data[6:0]}),
	.dout	(lsu_mbi_tlb_data_cmp)
);

lsu_tgd_dp_buff_macro__width_5 cambist_buf  (
	.din	({tlb_cam_hit,        tlb_context0_hit,     tlb_cam_mhit,
		  tlb_tte_u_bit,      tlb_tte_tag[`TAG_V]}),
	.dout	({lsu_mbi_tlb_cam_hit,lsu_mbi_tlb_ctxt0_hit,lsu_mbi_tlb_cam_mhit,
		  lsu_mbi_tlb_used,   lsu_mbi_tlb_valid})
);

// fixscan start:
assign dff_16b_prty_w01_scanin   = scan_in                  ;
assign dff_16b_prty_w23_scanin   = dff_16b_prty_w01_scanout ;
assign dff_diag_tag_scanin       = dff_16b_prty_w23_scanout ;
assign dff_va_b_scanin           = dff_diag_tag_scanout     ;
assign dff_wpt_b_scanin          = dff_va_b_scanout         ;
assign scan_out                  = dff_wpt_b_scanout        ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_tgd_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_msff_macro__width_4 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [2:0] so;

  input [3:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [3:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module lsu_tgd_dp_xor_macro__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


xor2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;
  output [31:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(32)  d0_0 (
  .sel(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_msff_macro__mux_pgpe__ports_2__stack_32l__width_32 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0_unused;
wire psel1;
wire [31:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(32)  d1_0 (
  .sel(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(muxout[31:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 (
  din, 
  dout);
  input [28:0] din;
  output [28:0] dout;


buff #(29)  d0_0 (
.in(din[28:0]),
.out(dout[28:0])
);


endmodule


//
//   invert macro
//
//


module lsu_tgd_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module lsu_tgd_dp_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_14l__width_13 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [12:0] din0;
  input [12:0] din1;
  input [12:0] din2;
  input sel0;
  input sel1;
  output [12:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(13)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
  .in2(din2[12:0]),
.dout(dout[12:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__stack_14l__width_13 (
  din, 
  dout);
  input [12:0] din;
  output [12:0] dout;


buff #(13)  d0_0 (
.in(din[12:0]),
.out(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_14r__width_13 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [12:0] din0;
  input [12:0] din1;
  input [12:0] din2;
  input sel0;
  input sel1;
  output [12:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(13)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
  .in2(din2[12:0]),
.dout(dout[12:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__stack_14r__width_13 (
  din, 
  dout);
  input [12:0] din;
  output [12:0] dout;


buff #(13)  d0_0 (
.in(din[12:0]),
.out(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  output [63:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__rep_1__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__left_19__minbuff_1__stack_64c__width_45 (
  din, 
  dout);
  input [44:0] din;
  output [44:0] dout;


buff #(45)  d0_0 (
.in(din[44:0]),
.out(dout[44:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_msff_macro__left_13__stack_64c__width_51 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [49:0] so;

  input [50:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [50:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(51)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[50:0]),
.si({scan_in,so[49:0]}),
.so({so[49:0],scan_out}),
.q(dout[50:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_msff_macro__left_19__stack_64c__width_45 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [43:0] so;

  input [44:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [44:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(45)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[44:0]),
.si({scan_in,so[43:0]}),
.so({so[43:0],scan_out}),
.q(dout[44:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_tgd_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_tgd_dp_cmp_macro__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output dout;


cmp #(16)  m0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__rep_1__width_10 (
  din, 
  dout);
  input [9:0] din;
  output [9:0] dout;


buff #(10)  d0_0 (
.in(din[9:0]),
.out(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_64c__width_64 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input sel0;
  input sel1;
  output [63:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_tgd_dp_cmp_macro__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output dout;


cmp #(64)  m0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_tgd_dp_cmp_macro__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output dout;


cmp #(8)  m0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module lsu_tgd_dp_buff_macro__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_tlc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_tlc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  spc_aclk, 
  spc_bclk, 
  mmu_dtlb_reload, 
  tld_demap_control0, 
  tld_demap_control1, 
  tld_use_secondary_context0, 
  tld_index_valid, 
  lsu_lsu_pmen_, 
  lsu_asi_error_inject_b31, 
  lsu_asi_error_inject_b27, 
  lsu_asi_error_inject_b26, 
  dcc_tlb_rw_index_e, 
  lbist_run, 
  mbi_run, 
  mbi_dtb_write_en, 
  mbi_repl_write, 
  mbi_dis_clr_ubit, 
  mbi_cambist_run, 
  mbi_dtb_demap_en, 
  mbi_demap_type, 
  scan_out, 
  tlc_wr_u_en, 
  tlc_rw_index_vld, 
  tlc_demap, 
  tlc_demap_context, 
  tlc_demap_all, 
  tlc_demap_real, 
  tlc_sel_demap_tag_c0, 
  tlc_sel_demap_tag_c1, 
  tlc_sel_write_tag, 
  tlc_sel_dm_tag, 
  tlc_sel_wr_dm_bist, 
  tlc_sel_tte_tag, 
  tlc_use_primary_context_c0, 
  tlc_use_secondary_context_c0, 
  tlc_wr_or_demap, 
  tlc_write_next, 
  tlc_tte0_clken, 
  tlc_tte1_clken, 
  tlc_tag_error_inj, 
  tlc_data_error_inj, 
  tlc_mbi_run, 
  tlc_dis_clr_ubit, 
  lsu_sel_lsu_addr_e);
wire se;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk;
wire reload0_latch_scanin;
wire reload0_latch_scanout;
wire reload0;
wire reload1_latch_scanin;
wire reload1_latch_scanout;
wire reload1;
wire [2:0] demap_c0;
wire [3:0] demap_c1;
wire wr_vld_in;
wire sel_wr_dm_bist_next;
wire dm_tag_in;
wire wr_vld_latch_scanin;
wire wr_vld_latch_scanout;
wire wr_vld;
wire demap_context;
wire demap_all;
wire demap_real;
wire sel_demap_tag_d;
wire override_context0;
wire tag_error_inj;
wire data_error_inj;
wire error_inj_latch_scanin;
wire error_inj_latch_scanout;
wire bist_latch_scanin;
wire bist_latch_scanout;
wire spares_scanin;
wire spares_scanout;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_scan_en;
input		spc_aclk;
input		spc_bclk;
                                        // The following signals indicate the
                                        // first cycle of TTE transfer as well
                                        // as the operation (write or demap)
input		mmu_dtlb_reload;

input	[2:0]	tld_demap_control0;	// Demap and context controls
input	[3:0]	tld_demap_control1;	// Demap and context controls
input		tld_use_secondary_context0;
input		tld_index_valid;	// Write with index

input		lsu_lsu_pmen_;		// Power management enable
input		lsu_asi_error_inject_b31;
input		lsu_asi_error_inject_b27;
input		lsu_asi_error_inject_b26;

input		dcc_tlb_rw_index_e;

input		lbist_run;
input		mbi_run;
input		mbi_dtb_write_en;
input		mbi_repl_write;
input		mbi_dis_clr_ubit;
input		mbi_cambist_run;
input		mbi_dtb_demap_en;
input	[1:0]	mbi_demap_type;

output		scan_out;
output		tlc_wr_u_en;		// Write enable for tlb
output		tlc_rw_index_vld;	// Use index for read or write
output		tlc_demap;		// Any demap
output		tlc_demap_context;	// Demap context
output		tlc_demap_all;		// Demap all
output		tlc_demap_real;		// Demap real

output		tlc_sel_demap_tag_c0;
output		tlc_sel_demap_tag_c1;
output		tlc_sel_write_tag;
output		tlc_sel_dm_tag;
output		tlc_sel_wr_dm_bist;
output		tlc_sel_tte_tag;

output		tlc_use_primary_context_c0;// Control context muxes	
output		tlc_use_secondary_context_c0;	
				
output		tlc_wr_or_demap;	// Tells LSU to use the demap/write tid for context selection
output		tlc_write_next;

output		tlc_tte0_clken;
output		tlc_tte1_clken;

output		tlc_tag_error_inj;
output		tlc_data_error_inj;
output		tlc_mbi_run;
output		tlc_dis_clr_ubit;

output		lsu_sel_lsu_addr_e;

//////////////////////////////////////////////////////////////////////////////

assign se 	= tcu_scan_en;
assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;

// Clock header
lsu_tlc_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk 			),
        .l1en   (1'b1			),
        .l1clk  (l1clk			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


////////////////////////////////////////////////////////////////////////////////
//
//
//


//flop mmu_dtlb_reload 

lsu_tlc_ctl_msff_ctl_macro__width_1 reload0_latch   (
	.scan_in(reload0_latch_scanin),
	.scan_out(reload0_latch_scanout),
	.din	(mmu_dtlb_reload	),
	.dout	(reload0		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

lsu_tlc_ctl_msff_ctl_macro__width_1 reload1_latch   (
	.scan_in(reload1_latch_scanin),
	.scan_out(reload1_latch_scanout),
	.din	(reload0		),
	.dout	(reload1		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// demap_control[3]: use secondary context for demap/write
// demap_control[2]:  1 means demap, 0 means write
// demap_control[1:0] (if demap_control[2] is 1)
//      00     Demap page
//      01     Demap context
//      10     Demap all (to be consistent with Niagara 1)
//      11     Demap real
// demap_control[1:0] (if demap_control[2] is 0)
//      00     Demap and write with supplied context
//      01     Demap and write with context_0
//      10     Demap and write with context_1
//      11     Illegal (but demap and write with context_0)

assign demap_c0[2:0] =
       tld_demap_control0[2:0];
assign demap_c1[3:0] =
       tld_demap_control1[3:0];

assign wr_vld_in =
       reload1 & ~demap_c1[2] & ~tlc_mbi_run;
		  
assign tlc_write_next = wr_vld_in;

assign sel_wr_dm_bist_next = wr_vld_in | reload0 | tlc_mbi_run;

assign dm_tag_in = ~(wr_vld_in | tlc_mbi_run);

lsu_tlc_ctl_msff_ctl_macro__width_3 wr_vld_latch   (
	.scan_in(wr_vld_latch_scanin),
	.scan_out(wr_vld_latch_scanout),
	.din	({wr_vld_in, dm_tag_in,     sel_wr_dm_bist_next}),
	.dout	({wr_vld,    tlc_sel_dm_tag,tlc_sel_wr_dm_bist}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_sel_lsu_addr_e = tlc_sel_wr_dm_bist;

assign demap_context =
       reload1 & demap_c1[2] & ~demap_c1[1] &  demap_c1[0];

assign demap_all  =
       reload1 & demap_c1[2] &  demap_c1[1] & ~demap_c1[0];

assign demap_real =
       reload1 & demap_c1[2] &  demap_c1[1] &  demap_c1[0];

// demap default context if:
// a write with the use_context_[0,1] bits off OR
// a demap with use_seconday off
assign sel_demap_tag_d = 
       (reload1 & demap_c1[2] & ~demap_c1[3]) | 
       (reload1 & ~demap_c1[2] & ~demap_c1[1] & ~demap_c1[0]) ;

// demap context 0 if:
// a demap with use_secondary OR
// a write with use_context_0 on
assign tlc_sel_demap_tag_c0 = 
       (reload1 &  demap_c1[2] &  demap_c1[3]) |
       (reload1 & ~demap_c1[2] &  demap_c1[0]) ;

// demap context 1 if a write with use_context_1 on
assign tlc_sel_demap_tag_c1 = 
       (reload1 & ~demap_c1[2] &  demap_c1[1] & ~demap_c1[0]) ;


assign tlc_sel_write_tag = wr_vld;
assign tlc_sel_tte_tag = wr_vld | sel_demap_tag_d | tlc_mbi_run;


// Context mux controls
assign override_context0 =
       reload0 & ~demap_c0[2] & (demap_c0[1] | demap_c0[0]);

assign tlc_use_primary_context_c0 =
       (override_context0 & ~tld_use_secondary_context0) | 
       (reload0 & demap_c0[2] & ~tld_use_secondary_context0) ;

assign tlc_use_secondary_context_c0 =
       (override_context0 & tld_use_secondary_context0) | 
       (reload0 & demap_c0[2] & tld_use_secondary_context0) ;

///outputs

assign tlc_demap		= tlc_mbi_run ? (mbi_cambist_run & mbi_dtb_demap_en) : reload1;
assign tlc_demap_context	= tlc_mbi_run ? (mbi_cambist_run & mbi_dtb_demap_en & (mbi_demap_type[1:0] == 2'b10)) : demap_context;
assign tlc_demap_all   		= tlc_mbi_run ? (mbi_cambist_run & mbi_dtb_demap_en & (mbi_demap_type[1:0] == 2'b11)) : demap_all;
assign tlc_demap_real  		= tlc_mbi_run ? (mbi_cambist_run & mbi_dtb_demap_en & (mbi_demap_type[1:0] == 2'b01)) : demap_real;

assign tlc_wr_u_en 		= tlc_mbi_run ? mbi_dtb_write_en : wr_vld;

assign tlc_rw_index_vld		= (tlc_mbi_run ? ~mbi_repl_write : (dcc_tlb_rw_index_e | (wr_vld & tld_index_valid))) | lbist_run;

// This needs to be a cycle earlier than the tlb controls for timing
assign tlc_wr_or_demap 		= reload0 | wr_vld_in;

//////////////////////////////////
// Power mgmt for the datapath
assign tlc_tte0_clken = mmu_dtlb_reload | reload0 | lsu_lsu_pmen_;
assign tlc_tte1_clken = reload0 | reload1 | lsu_lsu_pmen_;

///////////////////////////////////
// Error injection
assign tag_error_inj  = lsu_asi_error_inject_b31 & lsu_asi_error_inject_b26 & wr_vld_in;
assign data_error_inj = lsu_asi_error_inject_b31 & lsu_asi_error_inject_b27 & wr_vld_in;

lsu_tlc_ctl_msff_ctl_macro__width_2 error_inj_latch   (
	.scan_in(error_inj_latch_scanin),
	.scan_out(error_inj_latch_scanout),
	.din	({    tag_error_inj,    data_error_inj	}),
	.dout	({tlc_tag_error_inj,tlc_data_error_inj	}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////
// BIST

lsu_tlc_ctl_msff_ctl_macro__width_1 bist_latch   (
	.scan_in(bist_latch_scanin),
	.scan_out(bist_latch_scanout),
	.din	(mbi_run),
	.dout	(tlc_mbi_run),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlc_dis_clr_ubit = tlc_mbi_run & mbi_dis_clr_ubit;

lsu_tlc_ctl_spare_ctl_macro__num_1 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// fixscan start:
assign reload0_latch_scanin      = scan_in                  ;
assign reload1_latch_scanin      = reload0_latch_scanout    ;
assign wr_vld_latch_scanin       = reload1_latch_scanout    ;
assign error_inj_latch_scanin    = wr_vld_latch_scanout     ;
assign bist_latch_scanin         = error_inj_latch_scanout  ;
assign spares_scanin             = bist_latch_scanout       ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule	
	
	
// any PARAMS parms go into naming of macro

module lsu_tlc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tlc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tlc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tlc_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module lsu_tlc_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: lsu_tld_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module lsu_tld_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  tcu_se_scancollar_in, 
  spc_aclk, 
  spc_bclk, 
  exu_lsu_address_e, 
  default_tag, 
  tlc_sel_write_tag, 
  tlc_sel_dm_tag, 
  tlc_sel_wr_dm_bist, 
  tlc_write_next, 
  tlc_tte0_clken, 
  tlc_tte1_clken, 
  tlc_tag_error_inj, 
  tlc_data_error_inj, 
  tlu_tte, 
  tlc_mbi_run, 
  mbi_wdata, 
  mbi_addr, 
  mbi_cambist_run, 
  mbi_cambist_shift, 
  mbi_init_to_zero, 
  mbi_dtb_write_en, 
  mbi_repl_write, 
  mbi_dis_clr_ubit, 
  mbi_dtb_demap_en, 
  mbi_demap_type, 
  tld_mbi_dtb_write_en, 
  tld_mbi_repl_write, 
  tld_mbi_dis_clr_ubit, 
  tld_mbi_dtb_demap_en, 
  tld_mbi_demap_type, 
  tgd_tag_c0, 
  tgd_tag_c1, 
  scan_out, 
  tld_ubit, 
  tld_tag_pid, 
  tld_tag_c0, 
  tld_tag_c1, 
  tld_tag_real, 
  tld_tag_valid, 
  tld_tag_mask, 
  tld_data, 
  tld_demap_control0, 
  tld_demap_control1, 
  tld_use_secondary_context0, 
  tld_tid, 
  tld_index_valid, 
  tld_rw_index, 
  tld_prty_256m, 
  tld_prty_4m, 
  tld_prty_64k, 
  tld_prty_8k, 
  tld_prty_ctxt0, 
  tld_prty_ctxt1, 
  tld_va_m_eq_zero, 
  lsu_va_m, 
  lsu_mmu_va_m, 
  lsu_exu_address_e);
wire stop;
wire en;
wire clk;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire tte0_lat_scanin;
wire tte0_lat_scanout;
wire [54:0] tte0;
wire [12:0] context_to_write;
wire tte1_lat_scanin;
wire tte1_lat_scanout;
wire [54:0] tte1;
wire tte2_lat_scanin;
wire tte2_lat_scanout;
wire [2:0] partition_id1;
wire [51:0] tte2_lat_out;
wire [54:0] tte2;
wire [2:0] partition_id2;
wire wrdata_sel;
wire wrdata_sel_;
wire [68:0] access_tag_m;
wire [68:0] tag_to_demap_d;
wire [68:0] tag_to_write;
wire [7:0] bist_data_0;
wire [69:0] mbist_wdata;
wire test_data_mux_scanin;
wire test_data_mux_scanout;
wire [69:0] bist_wdata;
wire tld_mbi_cambist_run;
wire [27:0] tag0;
wire [55:13] tld_tag_0;
wire default_unused;
wire [6:0] tld_mbi_addr;
wire mask_va_27_22_;
wire mask_va_21_16_;
wire mask_va_15_13_;
wire mask_context_;
wire [27:13] masked_va;
wire [12:0] masked_ctxt;
wire [47:0] va_m;
wire [51:0] tag_for_parity;
wire tag_parity_unmasked;
wire tag_parity_masked;
wire tag_parity_unmasked_;
wire tag_parity_masked_;
wire tag_parity;
wire prty_256m;
wire prty_8k_lower;
wire prty_va_27_22;
wire prty_4m;
wire prty_va_27_16;
wire prty_64k;
wire prty_8k;
wire prty_ctxt0;
wire prty_ctxt1;
wire [36:0] wr_data;
wire data_parity;
wire [7:0] bist_data_1;
wire data_parity_0;
wire data_parity_1;
wire va_m_lat_scanin;
wire va_m_lat_scanout;
wire bist_lat_scanin;
wire bist_lat_scanout;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_scan_en;
input		tcu_se_scancollar_in;
input		spc_aclk;
input		spc_bclk;

input	[47:0]	exu_lsu_address_e;	// E->M flop is in this dp

input	[55:13] default_tag;

                                        // The following signals indicate the
                                        // first cycle of TTE transfer as well
                                        // as the operation (write or demap)
input		tlc_sel_write_tag;
input		tlc_sel_dm_tag;
input		tlc_sel_wr_dm_bist;
input		tlc_write_next;
input		tlc_tte0_clken;
input		tlc_tte1_clken;

input		tlc_tag_error_inj;
input		tlc_data_error_inj;

input	[54:0]	tlu_tte;		
                                        // First cycle of transfer 
				        // (part of tag, data, controls)
					// 	  54	  Index valid
					// 	  53:47	  Index to write
					// 	  46	  Demap / repl sec. cxt
					// 	  45	  Demap valid
					// 	  44:43	  Demap / context type
                                        //	  42	  PS_GT_64K
                                        //	  41:39   VA[15:13]
                                        //	  38	  PS_GT_8K
                                        //	  37:35   Thread ID
                                        //	  34	  Real bit
                                        //	  33:22   PA[39:28]
                                        //	  21:16   PA[27:22]
                                        //	  15:10   PA[21:16]
                                        //	  09:07   PA[15:13]
                                        //	  06	  Valid bit
                                        //	  05	  NFO bit
                                        //	  04	  IE bit
                                        //	  03	  CP bit
                                        //	  02	  X bit
                                        //	  01	  P bit
                                        //	  00	  W bit
                                        // Second cycle of transfer 
					// (rest of tag)
                                        //	  47:28   VA[47:28]
                                        //	  27:22   VA[27:22]
                                        //	  21	  PS_EQ_256M
                                        //	  20	  Valid
                                        //	  19	  Lock
                                        //	  18:13   VA[21:16]
                                        //	  12:00   Context


input		tlc_mbi_run;
input	[7:0]	mbi_wdata;
input	[6:0]	mbi_addr;
input		mbi_cambist_run;
input		mbi_cambist_shift;
input		mbi_init_to_zero;

input		mbi_dtb_write_en;
input		mbi_repl_write;
input		mbi_dis_clr_ubit;
input		mbi_dtb_demap_en;
input	[1:0]	mbi_demap_type;
output		tld_mbi_dtb_write_en;
output		tld_mbi_repl_write;
output		tld_mbi_dis_clr_ubit;
output		tld_mbi_dtb_demap_en;
output	[1:0]	tld_mbi_demap_type;

input	[12:0]	tgd_tag_c0;
input	[12:0]	tgd_tag_c1;

output		scan_out;
output		tld_ubit;
output	[2:0]	tld_tag_pid;
output	[12:0]	tld_tag_c0;
output	[12:0]	tld_tag_c1;
output		tld_tag_real;
output		tld_tag_valid;
output	[2:0]	tld_tag_mask;
output	[37:0]	tld_data;
output	[2:0]	tld_demap_control0;
output	[3:0]	tld_demap_control1;
output		tld_use_secondary_context0;
output	[2:0]	tld_tid;
output		tld_index_valid;
output	[6:0]	tld_rw_index;
output		tld_prty_256m;
output		tld_prty_4m;
output		tld_prty_64k;
output		tld_prty_8k;
output		tld_prty_ctxt0;
output		tld_prty_ctxt1;
output		tld_va_m_eq_zero;
output	[47:0]	lsu_va_m;
output	[47:0]	lsu_mmu_va_m;
					
output	[47:13]	lsu_exu_address_e;


assign stop	= 1'b0;
assign en	= 1'b1;
assign clk	= l2clk;

lsu_tld_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
	.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
	.dout({se,pce_ov,siclk,soclk})
);


///////////////////////////////////////////////////////////////////////////////
// Flop the TTE from TLU

lsu_tld_dp_msff_macro__stack_70c__width_55 tte0_lat   (
	.scan_in(tte0_lat_scanin),
	.scan_out(tte0_lat_scanout),
	.din	(tlu_tte		[54:0]	),
	.dout	(tte0			[54:0]	),
	.en	(tlc_tte0_clken),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign tld_tid[2:0] =
       tte0[37:35];

// Mux context for write tag
lsu_tld_dp_mux_macro__mux_aope__ports_2__stack_70c__width_13 context_to_write_mux     (
	.din0	(tgd_tag_c0		[12:0]	),
	.din1	(tte0			[12:0]	),
	.sel0	(tlc_write_next			),
	.dout	(context_to_write	[12:0]	)
);

assign tld_use_secondary_context0 =
       tte0[46];

lsu_tld_dp_msff_macro__stack_70c__width_55 tte1_lat   (
	.scan_in(tte1_lat_scanin),
	.scan_out(tte1_lat_scanout),
	.din	({tte0	[54:13], context_to_write[12:0]}),
	.dout	( tte1	[54:0]				),
	.en	(tlc_tte1_clken),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// If a write will happen next cycle, flop the tte tag for write.
// Otherwise, flop the tag that was just used for lookup.
lsu_tld_dp_msff_macro__mux_aope__ports_2__stack_70c__width_52 tte2_lat     (
	.scan_in(tte2_lat_scanin),
	.scan_out(tte2_lat_scanout),
	.din0	({tte1[54:47],partition_id1[2:0],tte1[42:38],1'b1,1'b0,tte1[34:7],tte1[5:0]}),
	.din1	({tld_tag_pid[2:0],tld_tag_real,12'b0,1'b0,1'b1,7'b0,tgd_tag_c1[12:0],tgd_tag_c0[12:0],1'b0}),
	.sel0	(tlc_write_next),
	.dout	(tte2_lat_out[51:0]),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign {tte2[54:47],partition_id2[2:0],tte2[42:38],wrdata_sel,wrdata_sel_,tte2[34:7],tte2[5:0]} = tte2_lat_out[51:0];
assign {access_tag_m[68:56], access_tag_m[12:0]} = tte2_lat_out[26:1];
assign access_tag_m[55:52] = tte2_lat_out[51:48];

assign tld_index_valid =
       tte2[54];

///////////////////////////TTE tag///////////////////////////////////////////////

assign partition_id1[2:0] = default_tag[55:53];

// Now build tag for the two cycles
// Demap with specified context
assign tag_to_demap_d[68:0] =
       {tte0		[12:0],	// Context
	partition_id1	[2:0],	// PID
	tte1		[34   ],	// R
	tte0		[47:28],	// VA[47:28]
	tte0		[27:22],	// VA[27:22]
	tte0		[21   ],	// 27_22_V
	tte0		[20   ],	// V
	tte0		[18:13],	// VA[21:16]
	tte1		[42   ],	// 21_16_V
	tte1		[41:39],	// VA[15:13]
	tte1		[38   ],	// 15_13_V
	tte0		[12:0]};	// Context[12:00]

// Write with muxed context
assign tag_to_write[68:0] =
       {tte1		[12:0],	// Context
	partition_id2	[2:0],	// PID
	tte2		[34   ],	// R
	tte1		[47:28],	// VA[47:28]
	tte1		[27:22],	// VA[27:22]
	tte1		[21   ],	// 27_22_V
	tte1		[20   ],	// V
	tte1		[18:13],	// VA[21:16]
	tte2		[42   ],	// 21_16_V
	tte2		[41:39],	// VA[15:13]
	tte2		[38   ],	// 15_13_V
	tte1		[12:0]		// Context[12:00]
	};
	

lsu_tld_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_8 buf_mbi_wdata  (
	.din	(mbi_wdata[7:0]),
	.dout	(bist_data_0[7:0])
);

// Page mask and real bits must be zero for bist to avoid masking lower address and context bits.
assign mbist_wdata[69:0] = {	bist_data_0[0],						// U
				bist_data_0[7:0],bist_data_0[7:3],			// [68:56]
				bist_data_0[4:2],					// [55:53]
				1'b0,							// [52]
				bist_data_0[0],{3{bist_data_0[7:0]}},bist_data_0[7],	// [51:26]
				1'b0,							// [25]
				bist_data_0[6:0],					// [24:18]
				1'b0,							// [17]
				bist_data_0[7:5],					// [16:14]
				1'b0,							// [13]
				bist_data_0[4:0],bist_data_0[7:0]};			// [12:0]

// Key to CAMBIST match/write data
// [0] = other		[4] = Valid
// [1] = PID		[5] = Real
// [2] = Context1	[6] = Used
// [3] = Context0

lsu_tld_dp_msff_macro__mux_aope__ports_4__stack_70c__width_70 test_data_mux     (
	.scan_in(test_data_mux_scanin),
	.scan_out(test_data_mux_scanout),
	.en	(tlc_mbi_run),
	.din0	({13'b0,1'b1,55'b0,1'b1}),
	.din1	({1'b1,
		  bist_wdata[67:56],1'b0,
		  bist_wdata[54:26],bist_wdata[23],
		  1'b0,1'b1,
		  bist_wdata[22:18],bist_wdata[16],
		  1'b0,
		  bist_wdata[15:14],bist_wdata[12],
		  1'b0,
		  bist_wdata[11:0],1'b0}),		// CAMBIST shift data
	.din2	({bist_data_0[6],{13{bist_data_0[2]}},{3{bist_data_0[1]}},bist_data_0[5],
		 {26{bist_data_0[0]}},1'b0,bist_data_0[4],{6{bist_data_0[0]}},
		  1'b0,{3{bist_data_0[0]}},1'b0,{13{bist_data_0[3]}}}
		),								// CAMBIST match/write data
	.din3	(mbist_wdata[69:0]),						// MEMBIST data
	.sel0	(mbi_init_to_zero),
	.sel1	(mbi_cambist_shift),
	.sel2	(tld_mbi_cambist_run),
	.dout	(bist_wdata[69:0]),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// tte_tag pin ordering is, from left of CAM to right of CAM
// Used Valid Context0[12:0] Context1[12:0] Real VA[27:13] VA[47:28] PID[2:0]

// Valid and context are muxed one way.  The context result of this mux will be muxed later
// with the stored context values.  This mux sits above the tlb, that mux sits below in
// lsu_tgd_dp.
lsu_tld_dp_mux_macro__mux_aonpe__ports_3__stack_28l__width_28 mx_tag0_d     (
	.din0	({bist_wdata[69], bist_wdata    [24],bist_wdata    [12:0],bist_wdata    [68:56]	}),
	.din1	({          1'b1, tag_to_write  [24],tag_to_write  [12:0],tag_to_write  [68:56]	}),
	.din2	({          1'b1, tag_to_demap_d[24],tag_to_demap_d[12:0],tag_to_demap_d[68:56]	}),
	.sel0	(tlc_mbi_run							),
	.sel1	(tlc_sel_write_tag						),
	.sel2	(tlc_sel_dm_tag						  	),
	.dout	(tag0[27:0])
);
lsu_tld_dp_buff_macro__width_28 tag0_buf  (
	.din	(tag0[27:0]),
	.dout	({tld_ubit, tld_tag_valid,tld_tag_c0    [12:0],tld_tag_c1     [12:0]	})
);

// VA/PID/Real bit are muxed differently.  I use two levels of muxing to keep
// the delay for the exu address path to a minimum.
lsu_tld_dp_mux_macro__mux_aonpe__ports_3__stack_42l__width_42 mx_tag1_d     (
	.din0	({bist_wdata    [52],bist_wdata    [31:25],bist_wdata    [23:13],bist_wdata    [51:32],bist_wdata    [55:53]	}),
	.din1	({tag_to_write  [52],tag_to_write  [31:25],tag_to_write  [23:13],tag_to_write  [51:32],tag_to_write  [55:53]	}),
	.din2	({tag_to_demap_d[52],tag_to_demap_d[31:25],tag_to_demap_d[23:13],tag_to_demap_d[51:32],tag_to_demap_d[55:53]	}),
	.sel0	(tlc_mbi_run	        		        					 			 ),
	.sel1	(tlc_sel_write_tag      		        					 			 ),
	.sel2	(tlc_sel_dm_tag						  	),
	.dout	({tld_tag_0     [52],tld_tag_0     [31:25],tld_tag_0     [23:13],tld_tag_0     [51:32],tld_tag_0     [55:53]	})
);

lsu_tld_dp_buff_macro__dbuff_32x__stack_none__width_35 exu_addr_buf   (
	.din	({tld_tag_0[51:26],tld_tag_0[23:18],tld_tag_0[16:14]}),
	.dout	(lsu_exu_address_e[47:13])
);

//                   R                   27_22_V       21_16_V           15_13_V           PID
lsu_tld_dp_mux_macro__mux_pgpe__ports_2__stack_42r__width_7 mx_tag2_d     (
	.din0	({tld_tag_0     [52],tld_tag_0  [25],tld_tag_0  [17],tld_tag_0  [13],tld_tag_0  [55:53]	}),
	.din1	({default_tag   [52],default_tag[25],default_tag[17],default_tag[13],default_tag[55:53]	}),
	.sel0	(tlc_sel_wr_dm_bist     		           		 		      ),
	.dout	({tld_tag_real      ,tld_tag_mask[2],tld_tag_mask[1],tld_tag_mask[0],tld_tag_pid[2:0]	})
);

assign default_unused=default_tag[24];

lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_8l__width_7 mx_index     (
	.din0	(tld_mbi_addr[6:0]				),
	.din1	(tte2[53:47]					),
	.din2	(exu_lsu_address_e[9:3]				),
	.sel0	(tlc_mbi_run					),
	.sel1	(tlc_sel_write_tag				),
	.dout	(tld_rw_index[6:0]				)
);

///////////////////////////////////////////////
// Parity generation for tte_tag
///////////////////////////////////////////////

// Mask the appropriate address/context bits based on page size and RA or VA trans type.

lsu_tld_dp_inv_macro__width_3 pg_mask_va  (
	.din	({tag_to_write[25],tag_to_write[17],tag_to_write[13]}),
	.dout	({mask_va_27_22_,  mask_va_21_16_,  mask_va_15_13_})
);
lsu_tld_dp_inv_macro__width_1 pg_mask_ctxt  (
	.din	(tag_to_write[52]),
	.dout	(mask_context_)
);

lsu_tld_dp_and_macro__ports_2__stack_28l__width_28 mask_tag    (
	.din0	({tag_to_write[31:26],
		  tag_to_write[23:18],
		  tag_to_write[16:14],
		  tag_to_write[12:0]}),
	.din1	({{6{mask_va_27_22_}},
		  {6{mask_va_21_16_}},
		  {3{mask_va_15_13_}},
		  {13{mask_context_}}}),
	.dout	({masked_va[27:22],
		  masked_va[21:16],
		  masked_va[15:13],
		  masked_ctxt[12:0]})
);

lsu_tld_dp_mux_macro__left_6__mux_aonpe__ports_2__stack_70c__width_52 parity_mux      (
	.din0	({tag_to_write[55:53],	
		  tag_to_write[52],	
		  tag_to_write[51:32],	
		  masked_va   [27:22],	
		  masked_va   [21:16],	
		  masked_va   [15:13],	
		  masked_ctxt [12:0]}),
	.din1	({access_tag_m[55:53],	
		  access_tag_m[52],	
		  va_m        [47:22],	
		  va_m        [21:16],	
		  va_m        [15:13],	
		  13'b0}),
	.sel0	(wrdata_sel	),
	.sel1	(wrdata_sel_	),
	.dout	({tag_for_parity[51:0]})
);

lsu_tld_dp_prty_macro__width_32 tag_pgen0  (
	.din	({tlc_tag_error_inj,1'b0,tag_for_parity[51:28],6'b0}),
	.dout	(tag_parity_unmasked)
);
lsu_tld_dp_prty_macro__width_32 tag_pgen1  (
	.din	({2'b0,tag_for_parity[27:0],2'b0}),
	.dout	(tag_parity_masked)
);
lsu_tld_dp_inv_macro__width_2 inv_tag_par  (
	.din	({tag_parity_unmasked ,tag_parity_masked}),
	.dout	({tag_parity_unmasked_,tag_parity_masked_})
);
lsu_tld_dp_xor_macro__ports_2__width_1 pgen_tag   (
	.din0	(tag_parity_unmasked_),
	.din1	(tag_parity_masked_),
	.dout	(tag_parity)
);

// Additional logic needed to complete parity detection.  
// tag_parity_unmasked is valid for all page sizes (it's complete for 256m)
// tag_parity_masked represents the addtional parity for 8k pages

lsu_tld_dp_inv_macro__width_2 pgen_256m  (
	.din	({tag_parity_unmasked_,tag_parity_masked_}),
	.dout	({prty_256m,           prty_8k_lower})
);

lsu_tld_dp_prty_macro__width_8 pgen_va_27_22  (
	.din	({va_m[27:22],2'b00}),
	.dout	(prty_va_27_22)
);
lsu_tld_dp_xor_macro__ports_2__width_1 pgen_4m   (
	.din0	(prty_256m),
	.din1	(prty_va_27_22),
	.dout	(prty_4m)
);

lsu_tld_dp_prty_macro__width_16 pgen_va_27_16  (
	.din	({va_m[27:22],4'b0000,va_m[21:16]}),
	.dout	(prty_va_27_16)
);
lsu_tld_dp_xor_macro__ports_2__width_1 pgen_64k   (
	.din0	(prty_256m),
	.din1	(prty_va_27_16),
	.dout	(prty_64k)
);

lsu_tld_dp_xor_macro__ports_2__width_1 pgen_8k   (
	.din0	(prty_256m),
	.din1	(prty_8k_lower),
	.dout	(prty_8k)
);

lsu_tld_dp_prty_macro__width_16 pgen_ctxt0  (
	.din	({access_tag_m[12:0],3'b000}),
	.dout	(prty_ctxt0)
);
lsu_tld_dp_prty_macro__width_16 pgen_ctxt1  (
	.din	({3'b000,access_tag_m[68:56]}),
	.dout	(prty_ctxt1)
);

lsu_tld_dp_buff_macro__width_6 prty_buf  (
	.din	({    prty_256m,    prty_4m,    prty_64k,    prty_8k,    prty_ctxt1,    prty_ctxt0}),
	.dout	({tld_prty_256m,tld_prty_4m,tld_prty_64k,tld_prty_8k,tld_prty_ctxt1,tld_prty_ctxt0})
);

///////////////////////////TTE data////////////////////////////////////////////
                                
// Data is only needed for write, so only need a mux for bist

assign wr_data[36:0] = 
       {data_parity	       ,	// Data Parity
	tte2		[33:22],	// PA[39:28]
	tte2		[21:16],	// PA[27:22]
	tte1		[21   ],	// 27_22_V, PS_EQ_256M
	tte2		[15:10],	// PA[21:16]
	tte2		[42   ],	// 21_16_V, PS_GT_64K
	tte2		[9:7],	// PA[15:13]
	tte2		[38   ],	// 15_13_V, PS_GT_8K
	tte2		[5:0]		// NFO, IE, CP, E, P, W
	};	

lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_20r__width_19 mx_data_odd     (
        .din0   ({16'b0,tld_mbi_addr[5],tld_mbi_addr[3],tld_mbi_addr[1]}),
        .din1   ({bist_data_1[5],bist_data_1[3],bist_data_1[1],{4{bist_data_1[7],bist_data_1[5],bist_data_1[3],bist_data_1[1]}}}),
        .din2   ({            tag_parity ,wr_data[35],wr_data[33],wr_data[31],
                  wr_data[29],wr_data[27],wr_data[25],wr_data[23],wr_data[21],
                  wr_data[19],wr_data[17],wr_data[15],wr_data[13],wr_data[11],
                  wr_data[9],wr_data[7],wr_data[5],wr_data[3],wr_data[1]}),
        .sel0   (tld_mbi_cambist_run),
        .sel1   (tlc_mbi_run),
        .dout   ({             tld_data[37],tld_data[35],tld_data[33],tld_data[31],
                  tld_data[29],tld_data[27],tld_data[25],tld_data[23],tld_data[21],
                  tld_data[19],tld_data[17],tld_data[15],tld_data[13],tld_data[11],
                  tld_data[9],tld_data[7],tld_data[5],tld_data[3],tld_data[1]})
);
lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_20r__width_19 mx_data_even     (
        .din0   ({15'b0,tld_mbi_addr[6],tld_mbi_addr[4],tld_mbi_addr[2],tld_mbi_addr[0]}),
        .din1   ({bist_data_1[4],bist_data_1[2],bist_data_1[0],{4{bist_data_1[6],bist_data_1[4],bist_data_1[2],bist_data_1[0]}}}),
        .din2   ({            wr_data[36],wr_data[34],wr_data[32],wr_data[30],
                  wr_data[28],wr_data[26],wr_data[24],wr_data[22],wr_data[20],
                  wr_data[18],wr_data[16],wr_data[14],wr_data[12],wr_data[10],
                  wr_data[8],wr_data[6],wr_data[4],wr_data[2],wr_data[0]}),
        .sel0   (tld_mbi_cambist_run),
        .sel1   (tlc_mbi_run),
        .dout   ({             tld_data[36],tld_data[34],tld_data[32],tld_data[30],
                  tld_data[28],tld_data[26],tld_data[24],tld_data[22],tld_data[20],
                  tld_data[18],tld_data[16],tld_data[14],tld_data[12],tld_data[10],
                  tld_data[8],tld_data[6],tld_data[4],tld_data[2],tld_data[0]})
);

lsu_tld_dp_prty_macro__width_16 dprty0  (
	.din	({tlc_data_error_inj,wr_data[10],wr_data[7:6],1'b0,wr_data[35:25]}),
	.dout	(data_parity_0)
);
lsu_tld_dp_prty_macro__width_16 dprty1  (
	.din	({wr_data[24],wr_data[17],wr_data[23:18],wr_data[16:11],wr_data[9:8]}),
	.dout	(data_parity_1)
);
lsu_tld_dp_prty_macro__width_8 dprty2  (
	.din	({wr_data[5:0],data_parity_0,data_parity_1}),
	.dout	(data_parity)
);

assign tld_demap_control0[2:0] =
       tte0[45:43];
assign tld_demap_control1[3:0] =
       tte1[46:43];


////////////////////////////////////////////////////////////////////
// VA staging from E to M - it's located here for floorplan reasons
lsu_tld_dp_msff_macro__stack_48c__width_48 va_m_lat    (
	.scan_in(va_m_lat_scanin),
	.scan_out(va_m_lat_scanout),
	.se	(tcu_se_scancollar_in),
	.din	(exu_lsu_address_e[47:0]),
	.dout	(va_m[47:0]),
  .clk(clk),
  .en(en),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);
lsu_tld_dp_zero_macro__width_32 va_m_zdt  (
	.din	(va_m[47:16]),
	.dout	(tld_va_m_eq_zero)
);

lsu_tld_dp_buff_macro__rep_1__stack_48c__width_48 lsu_va_m_buf   (
	.din	(va_m[47:0]),
	.dout	(lsu_va_m[47:0])
);
lsu_tld_dp_buff_macro__rep_1__stack_48c__width_48 lsu_mmu_va_m_buf   (
	.din	(va_m[47:0]),
	.dout	(lsu_mmu_va_m[47:0])
);

lsu_tld_dp_msff_macro__stack_22r__width_22 bist_lat    (
	.scan_in(bist_lat_scanin),
	.scan_out(bist_lat_scanout),
	.en	(tlc_mbi_run),
	.din	({bist_data_0[7:0],    mbi_addr[6:0],        mbi_dtb_write_en,     mbi_cambist_run,
		  mbi_repl_write,      mbi_dis_clr_ubit,
		  mbi_dtb_demap_en,    mbi_demap_type[1:0]}),
	.dout	({bist_data_1[7:0],    tld_mbi_addr[6:0],    tld_mbi_dtb_write_en, tld_mbi_cambist_run,
		  tld_mbi_repl_write,  tld_mbi_dis_clr_ubit,
		  tld_mbi_dtb_demap_en,tld_mbi_demap_type[1:0]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// fixscan start:
assign tte0_lat_scanin           = scan_in                  ;
assign tte1_lat_scanin           = tte0_lat_scanout         ;
assign tte2_lat_scanin           = tte1_lat_scanout         ;
assign test_data_mux_scanin      = tte2_lat_scanout         ;
assign va_m_lat_scanin           = test_data_mux_scanout    ;
assign bist_lat_scanin           = va_m_lat_scanout         ;
assign scan_out                  = bist_lat_scanout         ;
// fixscan end:
endmodule	


//
//   buff macro
//
//


module lsu_tld_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tld_dp_msff_macro__stack_70c__width_55 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [53:0] so;

  input [54:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [54:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(55)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[54:0]),
.si({scan_in,so[53:0]}),
.so({so[53:0],scan_out}),
.q(dout[54:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tld_dp_mux_macro__mux_aope__ports_2__stack_70c__width_13 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [12:0] din0;
  input [12:0] din1;
  input sel0;
  output [12:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(13)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
.dout(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tld_dp_msff_macro__mux_aope__ports_2__stack_70c__width_52 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [51:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [50:0] so;

  input [51:0] din0;
  input [51:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [51:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(52)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[51:0]),
  .in1(din1[51:0]),
.dout(muxout[51:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(52)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[51:0]),
.si({scan_in,so[50:0]}),
.so({so[50:0],scan_out}),
.q(dout[51:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tld_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tld_dp_msff_macro__mux_aope__ports_4__stack_70c__width_70 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire [69:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [68:0] so;

  input [69:0] din0;
  input [69:0] din1;
  input [69:0] din2;
  input [69:0] din3;
  input sel0;
  input sel1;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [69:0] dout;


  output scan_out;


cl_dp1_penc4_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(70)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[69:0]),
  .in1(din1[69:0]),
  .in2(din2[69:0]),
  .in3(din3[69:0]),
.dout(muxout[69:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(70)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[69:0]),
.si({scan_in,so[68:0]}),
.so({so[68:0],scan_out}),
.q(dout[69:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tld_dp_mux_macro__mux_aonpe__ports_3__stack_28l__width_28 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [27:0] din0;
  input sel0;
  input [27:0] din1;
  input sel1;
  input [27:0] din2;
  input sel2;
  output [27:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(28)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[27:0]),
  .in1(din1[27:0]),
  .in2(din2[27:0]),
.dout(dout[27:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tld_dp_buff_macro__width_28 (
  din, 
  dout);
  input [27:0] din;
  output [27:0] dout;


buff #(28)  d0_0 (
.in(din[27:0]),
.out(dout[27:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tld_dp_mux_macro__mux_aonpe__ports_3__stack_42l__width_42 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [41:0] din0;
  input sel0;
  input [41:0] din1;
  input sel1;
  input [41:0] din2;
  input sel2;
  output [41:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(42)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[41:0]),
  .in1(din1[41:0]),
  .in2(din2[41:0]),
.dout(dout[41:0])
);


endmodule


//
//   buff macro
//
//


module lsu_tld_dp_buff_macro__dbuff_32x__stack_none__width_35 (
  din, 
  dout);
  input [34:0] din;
  output [34:0] dout;


buff #(35)  d0_0 (
.in(din[34:0]),
.out(dout[34:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tld_dp_mux_macro__mux_pgpe__ports_2__stack_42r__width_7 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [6:0] din0;
  input [6:0] din1;
  input sel0;
  output [6:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(7)  d0_0 (
  .sel(psel1),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
.dout(dout[6:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_8l__width_7 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [6:0] din0;
  input [6:0] din1;
  input [6:0] din2;
  input sel0;
  input sel1;
  output [6:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(7)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
  .in2(din2[6:0]),
.dout(dout[6:0])
);


endmodule


//
//   invert macro
//
//


module lsu_tld_dp_inv_macro__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


//
//   invert macro
//
//


module lsu_tld_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module lsu_tld_dp_and_macro__ports_2__stack_28l__width_28 (
  din0, 
  din1, 
  dout);
  input [27:0] din0;
  input [27:0] din1;
  output [27:0] dout;


and2 #(28)  d0_0 (
.in0(din0[27:0]),
.in1(din1[27:0]),
.out(dout[27:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tld_dp_mux_macro__left_6__mux_aonpe__ports_2__stack_70c__width_52 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [51:0] din0;
  input sel0;
  input [51:0] din1;
  input sel1;
  output [51:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(52)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[51:0]),
  .in1(din1[51:0]),
.dout(dout[51:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_tld_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module lsu_tld_dp_inv_macro__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


inv #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module lsu_tld_dp_xor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


xor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_tld_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module lsu_tld_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module lsu_tld_dp_buff_macro__width_6 (
  din, 
  dout);
  input [5:0] din;
  output [5:0] dout;


buff #(6)  d0_0 (
.in(din[5:0]),
.out(dout[5:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module lsu_tld_dp_mux_macro__mux_aope__ports_3__stack_20r__width_19 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [18:0] din0;
  input [18:0] din1;
  input [18:0] din2;
  input sel0;
  input sel1;
  output [18:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(19)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[18:0]),
  .in1(din1[18:0]),
  .in2(din2[18:0]),
.dout(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tld_dp_msff_macro__stack_48c__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module lsu_tld_dp_zero_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


zero #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module lsu_tld_dp_buff_macro__rep_1__stack_48c__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module lsu_tld_dp_msff_macro__stack_22r__width_22 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [20:0] so;

  input [21:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [21:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(22)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[21:0]),
.si({scan_in,so[20:0]}),
.so({so[20:0],scan_out}),
.q(dout[21:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  lb_scan_en_wmr, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lsu_mmu_pmen, 
  lsu_asi_clken, 
  tlu_tag_access_tid_0_b, 
  tlu_i_tag_access_0_b, 
  tlu_d_tag_access_0_b, 
  tlu_tag_access_tid_1_b, 
  tlu_i_tag_access_1_b, 
  tlu_d_tag_access_1_b, 
  spc_core_running_status, 
  mbi_mra0_write_en, 
  mbi_mra1_write_en, 
  mbi_scp0_write_en, 
  mbi_scp1_write_en, 
  mbi_addr, 
  mbi_run, 
  mbi_wdata, 
  mbi_mra0_read_en, 
  mbi_mra1_read_en, 
  mbi_scp0_read_en, 
  mbi_scp1_read_en, 
  mbi_mmu_cmpsel, 
  lsu_rngf_cdbus, 
  lsu_va_b, 
  lsu_context_b, 
  lsu_tlu_dsfsr_ct_b, 
  lsu_asi_error_inject, 
  tlu_load_i_tag_access_p, 
  tlu_load_i_tag_access_n, 
  tlu_load_d_tag_access, 
  tlu_load_d_tag_access_r, 
  tlu_release_tte, 
  tlu_pc_0_w, 
  tlu_pc_1_w, 
  tlu_iht_request, 
  tlu_dht_request, 
  tlu_mmu_tl_gt_0, 
  tlu_ceter_pscce, 
  tlu_cerer_mrau, 
  tlu_cerer_scac, 
  tlu_cerer_scau, 
  tlu_cerer_hwtwmu, 
  tlu_cerer_hwtwl2, 
  l15_mmu_grant, 
  l15_spc_data1, 
  l15_mmu_cpkt, 
  l15_mmu_valid, 
  scan_out, 
  wmr_scan_out, 
  mmu_mbi_mra0_fail, 
  mmu_mbi_mra1_fail, 
  mmu_mbi_scp0_fail, 
  mmu_mbi_scp1_fail, 
  mmu_l15_cpkt, 
  mmu_l15_addr, 
  mmu_l15_valid, 
  mmu_write_itlb, 
  mmu_itte_tag_data, 
  mmu_asi_data, 
  mmu_asi_read, 
  mmu_dae_req, 
  mmu_dae_tid, 
  mmu_dtlb_reload_stall, 
  mmu_dtlb_reload, 
  mmu_hw_tw_enable, 
  mmu_reload_done, 
  mmu_i_unauth_access, 
  mmu_i_tsb_miss, 
  mmu_d_tsb_miss, 
  mmu_i_tte_outofrange, 
  mmu_d_tte_outofrange, 
  mmu_index, 
  mmu_asi_cecc, 
  mmu_asi_uecc, 
  mmu_asi_tid, 
  mmu_asi_index, 
  mmu_asi_mra_not_sca, 
  mmu_i_l2cerr, 
  mmu_d_l2cerr, 
  mmu_i_eccerr, 
  mmu_d_eccerr, 
  mmu_thr0_err_type, 
  mmu_thr1_err_type, 
  mmu_thr2_err_type, 
  mmu_thr3_err_type, 
  mmu_thr4_err_type, 
  mmu_thr5_err_type, 
  mmu_thr6_err_type, 
  mmu_thr7_err_type, 
  mmu_thr0_err_index, 
  mmu_thr1_err_index, 
  mmu_thr2_err_index, 
  mmu_thr3_err_index, 
  mmu_thr4_err_index, 
  mmu_thr5_err_index, 
  mmu_thr6_err_index, 
  mmu_thr7_err_index, 
  mmu_pmu_l2ret, 
  mmu_pmu_l2miss, 
  mmu_pmu_dtlb, 
  mmu_pmu_tid);
wire rd_pce;
wire wr_pce;
wire bist_clk_mux_sel;
wire tcu_scan_en_wmr;
wire [30:8] error_inject_unused;
wire asi_wmr_scanin;
wire asi_wmr_scanout;
wire asi_scanin;
wire asi_scanout;
wire [3:3] asi_rd_dtte_unused;
wire [6:0] asi_rd_dtte;
wire asd0_wmr_scanin;
wire asd0_wmr_scanout;
wire asd0_scanin;
wire asd0_scanout;
wire [47:13] asd_pc_0_w;
wire [1:0] asi_mra_rd_en_last;
wire [7:0] asi_rd_immu_tag_target;
wire [7:0] asi_rd_immu_tag_access;
wire [7:0] asi_rd_dmmu_tag_target;
wire [7:0] asi_rd_dmmu_tag_access;
wire [1:0] asi_rd_i_access_target;
wire [1:0] asi_rd_d_access_target;
wire [1:0] asi_rd_access_target;
wire [7:0] asi_rd_itte_tag;
wire [7:0] asi_rd_itte_data;
wire [7:0] asi_wr_immu_tag_access;
wire [7:0] asi_i_tag_access_en;
wire [7:0] asi_wr_itlb_data_in;
wire [7:0] asi_wr_itlb_data_access;
wire [7:0] asi_wr_immu_demap;
wire [7:0] asi_wr_immu_demap_p;
wire [7:0] asi_wr_immu_demap_n;
wire [7:0] asi_i_data_in_en;
wire [7:0] asi_wr_dmmu_tag_access;
wire [7:0] asi_d_tag_access_en;
wire [7:0] asi_wr_dtlb_data_in;
wire [7:0] asi_wr_dtlb_data_access;
wire [7:0] asi_wr_dmmu_demap;
wire [7:0] asi_wr_dmmu_demap_p;
wire [7:0] asi_wr_dmmu_demap_s_n;
wire [7:0] asi_d_data_in_en;
wire [7:0] asi_wr_p_context_0;
wire [1:0] asi_p_context_0_en;
wire [4:0] asi_mra_rd_addr_0;
wire [81:0] mra0_data;
wire [7:0] htc_wr_itlb_data_in;
wire [7:0] htc_wr_dtlb_data_in;
wire [81:0] asd0_rd_data;
wire [63:0] asd0_asi_rd_data;
wire [47:0] asd0_dtte_tag;
wire [54:0] asd0_dtte_data;
wire [47:0] asd0_itte_tag_data_;
wire [6:0] asd0_itte_index;
wire [12:0] asd_i_p_ctx_0_0;
wire [12:0] asd_i_p_ctx_0_1;
wire [12:0] asd_i_p_ctx_0_2;
wire [12:0] asd_i_p_ctx_0_3;
wire [47:0] asd0_tag_access;
wire asd0_zero_context;
wire asd0_asi_zero_context;
wire asd0_mra_rd_addr_bit_1;
wire asd1_wmr_scanin;
wire asd1_wmr_scanout;
wire asd1_scanin;
wire asd1_scanout;
wire [47:13] asd_pc_1_w;
wire [4:0] asi_mra_rd_addr_1;
wire [81:0] mra1_data;
wire [81:0] asd1_rd_data;
wire [63:0] asd1_asi_rd_data;
wire [47:0] asd1_dtte_tag;
wire [54:0] asd1_dtte_data;
wire [47:0] asd1_itte_tag_data_;
wire [6:0] asd1_itte_index;
wire [12:0] asd_i_p_ctx_0_4;
wire [12:0] asd_i_p_ctx_0_5;
wire [12:0] asd_i_p_ctx_0_6;
wire [12:0] asd_i_p_ctx_0_7;
wire [47:0] asd1_tag_access;
wire asd1_zero_context;
wire asd1_asi_zero_context;
wire asd1_mra_rd_addr_bit_1;
wire ase_scanin;
wire ase_scanout;
wire [81:0] ase_mra_wr_data;
wire [1:0] meg_parity;
wire meg1_parity_err_unused;
wire meg0_parity_err_unused;
wire asi_error_mrau;
wire [3:2] asi_mbist_ecc;
wire [1:0] mem_parity;
wire mel0_scanin;
wire mel0_scanout;
wire [1:0] mra0_parity;
wire med00_parity_err;
wire med01_parity_err;
wire [1:0] mel0_crit_parity;
wire [1:0] mel0_parity;
wire mel0_parity_err;
wire mel0_htc_parity_err;
wire med01_parity_out_unused;
wire med00_parity_out_unused;
wire mra0_scanin;
wire mra0_scanout;
wire [1:0] asi_mra_rd_en;
wire [4:0] asi_mra_wr_addr;
wire [1:0] asi_mra_wr_en;
wire [81:0] ase_mra_wr_data_minbuf;
wire mel1_scanin;
wire mel1_scanout;
wire [1:0] mra1_parity;
wire med10_parity_err;
wire med11_parity_err;
wire [1:0] mel1_crit_parity;
wire [1:0] mel1_parity;
wire mel1_parity_err;
wire mel1_htc_parity_err;
wire med11_parity_out_unused;
wire med10_parity_out_unused;
wire mra1_scanin;
wire mra1_scanout;
wire [63:0] asi_seg_wr_data;
wire [7:0] seg_ecc;
wire asi_error_scau;
wire [7:0] sem_ecc;
wire sel_scanin;
wire sel_scanout;
wire [63:0] asi_rd_data;
wire [7:0] sel_crit_ecc;
wire [7:0] sed_syndrome;
wire sed_cecc_err;
wire sed_uecc_err;
wire scp0_scanin;
wire scp0_scanout;
wire [4:0] asi_scp_addr;
wire [1:0] asi_scp_rd_en;
wire [1:0] asi_scp_wr_en;
wire [63:0] asi_wr_data;
wire [7:0] scp0_ecc;
wire [63:0] scp0_data;
wire scp1_scanin;
wire scp1_scanout;
wire [7:0] scp1_ecc;
wire [63:0] scp1_data;
wire htc_wmr_scanin;
wire htc_wmr_scanout;
wire htc_scanin;
wire htc_scanout;
wire [7:0] mmu_reload_done_unused;
wire htd_scanin;
wire htd_scanout;
wire tmc_scanin;
wire tmc_scanout;
wire trc_scanin;
wire trc_scanout;
wire [7:0] htc_itlb_clken;
wire [7:0] htc_dtlb_clken;
wire mbd_compare;
wire sel_scac;
wire sel_scau;
wire [63:0] ase_mra_rd_data;
wire [39:4] htd_tsbptr;
wire [4:0] htc_mra_addr_in;
wire [1:0] htc_mra_rd_en;
wire [7:0] asi_error_mask;
wire asi_rd_scp0;
wire asi_rd_tsb_cfg_0_2;
wire asi_rd_tsb_cfg_1_3;
wire asi_rd_tsb_ptr_;
wire asi_rd_real_range;
wire asi_rd_physical_offset;
wire asi_sel_mra_0_in;
wire asi_mra_wr_en_next;
wire [7:0] asi_wr_partition_id;
wire asi_dmmu_demap_s;
wire [2:0] asi_tag_access_sel;
wire asi_tsb_ptr_req_valid;
wire [2:0] asi_tsb_ptr_req;
wire [1:0] asi_tsb_ptr_number;
wire [1:0] asi_tsb_hwtw_enable_0;
wire [1:0] asi_tsb_hwtw_enable_1;
wire asi_data_in_real;
wire [63:0] asi_mra_wr_data;
wire asi_mra_req_grant;
wire asi_demap_r_bit;
wire [1:0] asi_hwtw_config_0;
wire [1:0] asi_hwtw_config_1;
wire [1:0] asi_hwtw_config_2;
wire [1:0] asi_hwtw_config_3;
wire [1:0] asi_hwtw_config_4;
wire [1:0] asi_hwtw_config_5;
wire [1:0] asi_hwtw_config_6;
wire [1:0] asi_hwtw_config_7;
wire asi_sel_en;
wire [7:0] asi_mbist_wdata;
wire [7:0] asi_ase_compare_data;
wire [7:0] asi_compare_data;
wire [31:0] asi_mbd_scp_data;
wire asi_mbd_sel_scp;
wire [7:0] asi_mbist_ecc_in;
wire asi_mbist_run;
wire asi_ecc_cmpsel_in;
wire [1:0] asi_ase_cmpsel_in;
wire [47:13] ase_lsu_va_w;
wire [12:0] ase_lsu_context_w;
wire [47:0] htd_tagaccess_din;
wire [38:0] htd_tlbdatain_din;
wire mmu_use_context_0;
wire mmu_use_context_1;
wire mmu_sec_context;
wire [31:0] ase_mbd_mbist_data;
wire htd_ra2pa_lower_hit_hw4;
wire htd_ra2pa_upper_hit_hw4;
wire htd_razero_hw4;
wire htd_range_en_hw4;
wire [7:0] htd_zeroctx_m0;
wire htd_zeroctx_hw1;
wire htd_usectx0_hw1;
wire htd_usectx1_hw1;
wire htd_ranotpa_hw1;
wire htd_ptr_hit0_hw1;
wire htd_ptr_hit1_hw1;
wire htd_ptr_hit2_hw1;
wire htd_ctx_hit_hw1;
wire htd_tte_ep_hw1;
wire htd_dmiss_hw1;
wire [5:0] htd_pred0_idx_m0;
wire [5:0] htd_pred1_idx_m0;
wire [15:0] htd_pred0_m0;
wire [15:0] htd_pred1_m0;
wire [7:0] htd_dmiss;
wire [7:0] htd_sec_ctx;
wire [7:0] tsm_rqv;
wire [7:0] tsm_tsb_miss_hw2;
wire [7:0] trs_rqv;
wire [7:0] trs_null_st;
wire [7:0] trs_waitrr3_st;
wire [7:0] trs_ecc_err;
wire [7:0] trs_ep_err;
wire [2:0] trs0_err_type;
wire [2:0] trs1_err_type;
wire [2:0] trs2_err_type;
wire [2:0] trs3_err_type;
wire [2:0] trs4_err_type;
wire [2:0] trs5_err_type;
wire [2:0] trs6_err_type;
wire [2:0] trs7_err_type;
wire [2:0] trs0_err_index;
wire [2:0] trs1_err_index;
wire [2:0] trs2_err_index;
wire [2:0] trs3_err_index;
wire [2:0] trs4_err_index;
wire [2:0] trs5_err_index;
wire [2:0] trs6_err_index;
wire [2:0] trs7_err_index;
wire [7:0] htc_core_running;
wire htc_m1_clken;
wire htc_hw3_clken;
wire htc_hw4_clken;
wire htc_zero_ctx_m2;
wire [5:3] htc_upd_pred_idx_hw2;
wire [7:0] htc_upd_grp;
wire [7:0] htc_upd_grp_x;
wire [1:0] htc_new_pred_bit;
wire htc_wrpred0_hw2;
wire htc_wrpred1_hw2;
wire htc_wrpred2_hw2;
wire htc_wrpred3_hw2;
wire [7:0] htc_tlb_miss_m;
wire htc_l15_en;
wire htc_wr_q0new_nogrant;
wire htc_wr_q0new_grant;
wire htc_wr_q1new;
wire htc_shift_q1_grant;
wire htc_wr_m3new;
wire htc_wr_m3q0;
wire htc_mra_sel_0;
wire htc_sel_mra_lo;
wire [1:0] htc_conf_index_m2;
wire [7:0] htc_vld_tsbptr_m2;
wire [7:0] htc_rd_tteq;
wire [7:0] htc_ra2pahit_hw5;
wire [7:0] htc_ranotpax_hw5;
wire [7:0] htc_cindex_bit0;
wire [7:0] htc_cindex_bit1;
wire [7:0] htc_rrindex_bit0;
wire [7:0] htc_rrindex_bit1;
wire [2:0] htc_pid0_m0;
wire [2:0] htc_pid1_m0;
wire [7:0] htc_tsbrd_valid_m0;
wire [7:0] htc_thr_valid_hw3;
wire [7:0] htc_thr_prevalid_hw3;
wire [7:0] htc_va_rd_m2_in;
wire htc_ranotpa_hw4;
wire [7:0] htc_data_rcvd_hw1;
wire [7:0] htc_tsb_hit_hw1;
wire [7:0] htc_tsb_done_hw2;
wire [7:0] htc_thr_valid_m1;
wire [7:0] htc_thr_valid_m0;
wire [7:0] htc_hwtw_burst;
wire [1:0] rr_ecc_err_type;
wire [1:0] cfg_ecc_err_type;
wire [1:0] l2_ecc_err_type;
wire [7:0] rr_ecc_err_hw5;
wire [7:0] cfg_ecc_err_m3;
wire [7:0] l2_ecc_err_hw1;
wire [7:0] htc_ep_miss_hw1;
wire [2:0] cfg_ecc_err_index;
wire [2:0] rr_ecc_err_index;
wire [7:0] trs_eperr_st;
wire [7:0] trs_eccerr_st;
wire [7:0] tsm_waitfortte;


input		l2clk;		
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		tcu_dectest;
input		tcu_muxtest;
input		tcu_array_wr_inhibit;
input		tcu_se_scancollar_in;

input		lb_scan_en_wmr;
input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

// Power management
input           lsu_mmu_pmen;
input		lsu_asi_clken;
input	[1:0]	tlu_tag_access_tid_0_b;	// Tag access power management
input		tlu_i_tag_access_0_b;	// Tag access power management
input		tlu_d_tag_access_0_b;	// Tag access power management
input	[1:0]	tlu_tag_access_tid_1_b;	// Tag access power management
input		tlu_i_tag_access_1_b;	// Tag access power management
input		tlu_d_tag_access_1_b;	// Tag access power management
input 	[7:0]	spc_core_running_status;

// MBIST
input		mbi_mra0_write_en;	// MBIST write control
input		mbi_mra1_write_en;	// MBIST write control
input		mbi_scp0_write_en;	// MBIST write control
input		mbi_scp1_write_en;	// MBIST write control
input	[4:0]	mbi_addr;		// 32 entry addressability for MBIST
input		mbi_run;		// Select MBIST controls
input	[7:0]	mbi_wdata;		// MBIST write data
input		mbi_mra0_read_en;	// MBIST read control
input		mbi_mra1_read_en;	// MBIST read control
input		mbi_scp0_read_en;	// MBIST read control
input		mbi_scp1_read_en;	// MBIST read control
input	[1:0]	mbi_mmu_cmpsel;		// Mux (DEC) between 32 bit chunks 

input	[64:0]	lsu_rngf_cdbus;
input 	[47:0]	lsu_va_b;
input 	[12:0]	lsu_context_b;
input	[1:0]	lsu_tlu_dsfsr_ct_b;	// Indicates pri/sec context to HWTW

input 	[31:0]	lsu_asi_error_inject; 	// 31:Enb 23:SCAU 20:MRAU 7:0 ECCMASK

input 	[7:0]	tlu_load_i_tag_access_p;
input 	[7:0]	tlu_load_i_tag_access_n;
input 	[7:0]	tlu_load_d_tag_access;
input 	[7:0]	tlu_load_d_tag_access_r;
input 	[7:0]	tlu_release_tte;
input 	[47:13]	tlu_pc_0_w;
input 	[47:13]	tlu_pc_1_w;
input 	[7:0]	tlu_iht_request;	// ITLB hardware tablewalk request
input 	[7:0]	tlu_dht_request;	// DTLB hardware tablewalk request
input	[7:0]	tlu_mmu_tl_gt_0;	// Load '0' as ITLB context
input	[7:0]	tlu_ceter_pscce;		
input		tlu_cerer_mrau;
input		tlu_cerer_scac;
input		tlu_cerer_scau;
input		tlu_cerer_hwtwmu;
input		tlu_cerer_hwtwl2;

input           l15_mmu_grant;
input   [127:0] l15_spc_data1;   // 16 bytes of return data from L2
input   [17:0] l15_mmu_cpkt;    // Control part of cpx packet
input           l15_mmu_valid;


output		scan_out;

output		wmr_scan_out;		// Warm reset (non)scan

// MBIST
output		mmu_mbi_mra0_fail;	// MBIST fail
output		mmu_mbi_mra1_fail;	// MBIST fail
output		mmu_mbi_scp0_fail;	// MBIST fail
output		mmu_mbi_scp1_fail;	// MBIST fail

output  [4:0] mmu_l15_cpkt;
output  [39:4] mmu_l15_addr;
output          mmu_l15_valid;

output 	[7:0]	mmu_write_itlb;
output 	[47:0]	mmu_itte_tag_data;

output	[64:0]	mmu_asi_data;		// ASI read data for fast bus
output		mmu_asi_read;		// Valid for MMU ASI read

output		mmu_dae_req;		// data_access_exception for bad pg size
output	[2:0]	mmu_dae_tid;		

output 		mmu_dtlb_reload_stall;
output 		mmu_dtlb_reload;

output 	[7:0]	mmu_hw_tw_enable;
output	[7:0]	mmu_reload_done;
output	[7:0]	mmu_i_unauth_access;
output	[7:0]	mmu_i_tsb_miss;
output	[7:0]	mmu_d_tsb_miss;

output	[7:0]	mmu_i_tte_outofrange;	// RA out of range
output	[7:0]	mmu_d_tte_outofrange;	// RA out of range

output	[6:0]	mmu_index;		// Index and valid from idata_access

output 		mmu_asi_cecc; 		// Correctable ECC error on ASI read
output 		mmu_asi_uecc; 		// Uncorrectable ECC error on ASI read
output	[2:0]	mmu_asi_tid;		// Thread for reported error
output	[10:0]	mmu_asi_index;		// Syndrome and index of the failure 
output		mmu_asi_mra_not_sca;	// 1: MRA error 0: Scratchpad error
output	[7:0]	mmu_i_l2cerr;		// HW TW had L2 correctable error on I rld
output	[7:0]	mmu_d_l2cerr;		// HW TW had L2 correctable error on D rld
output	[7:0]	mmu_i_eccerr;		// HW TW had MRA or L2 error on I rld
output	[7:0]	mmu_d_eccerr;		// HW TW had MRA or L2 error on D rld
output	[2:0]	mmu_thr0_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
output	[2:0]	mmu_thr1_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
output	[2:0]	mmu_thr2_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
output	[2:0]	mmu_thr3_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
output	[2:0]	mmu_thr4_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
output	[2:0]	mmu_thr5_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
output	[2:0]	mmu_thr6_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
output	[2:0]	mmu_thr7_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
output	[2:0]	mmu_thr0_err_index;	
output	[2:0]	mmu_thr1_err_index;	
output	[2:0]	mmu_thr2_err_index;	
output	[2:0]	mmu_thr3_err_index;	
output	[2:0]	mmu_thr4_err_index;	
output	[2:0]	mmu_thr5_err_index;	
output	[2:0]	mmu_thr6_err_index;	
output	[2:0]	mmu_thr7_err_index;	

output          mmu_pmu_l2ret;
output          mmu_pmu_l2miss;
output          mmu_pmu_dtlb;
output [2:0]    mmu_pmu_tid;


//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// assertions
// Cannot send out a request to gkt, if in null state
/* 0in assert -var (~(tmc.tsm0.null_state & mmu_l15_valid & (mmu_l15_cpkt[2:0] == 3'b000)))
 -message "mmu.mmu_tsm_ctl: Valid request sent to gkt in null state, thread 0" */

/* 0in assert -var (~(tmc.tsm1.null_state & mmu_l15_valid & (mmu_l15_cpkt[2:0] == 3'b001)))
 -message "mmu.mmu_tsm_ctl: Valid request sent to gkt in null state, thread 1" */

/* 0in assert -var (~(tmc.tsm2.null_state & mmu_l15_valid & (mmu_l15_cpkt[2:0] == 3'b010)))
 -message "mmu.mmu_tsm_ctl: Valid request sent to gkt in null state, thread 2" */

/* 0in assert -var (~(tmc.tsm3.null_state & mmu_l15_valid & (mmu_l15_cpkt[2:0] == 3'b011)))
 -message "mmu.mmu_tsm_ctl: Valid request sent to gkt in null state, thread 3" */

/* 0in assert -var (~(tmc.tsm4.null_state & mmu_l15_valid & (mmu_l15_cpkt[2:0] == 3'b100)))
 -message "mmu.mmu_tsm_ctl: Valid request sent to gkt in null state, thread 4" */

/* 0in assert -var (~(tmc.tsm5.null_state & mmu_l15_valid & (mmu_l15_cpkt[2:0] == 3'b101)))
 -message "mmu.mmu_tsm_ctl: Valid request sent to gkt in null state, thread 5" */

/* 0in assert -var (~(tmc.tsm6.null_state & mmu_l15_valid & (mmu_l15_cpkt[2:0] == 3'b110)))
 -message "mmu.mmu_tsm_ctl: Valid request sent to gkt in null state, thread 6" */

/* 0in assert -var (~(tmc.tsm7.null_state & mmu_l15_valid & (mmu_l15_cpkt[2:0] == 3'b111)))
 -message "mmu.mmu_tsm_ctl: Valid request sent to gkt in null state, thread 7" */

// Cannot receive pkt from gkt, if in null state
/* 0in assert -var (~(tmc.tsm0.null_state & htc.load_ret_hw0 & htc.ret_tid_hw0[0]))
 -message "mmu.mmu_htc_ctl: Pkt received from gkt in null state, thread 0" */

/* 0in assert -var (~(tmc.tsm1.null_state & htc.load_ret_hw0 & htc.ret_tid_hw0[1]))
 -message "mmu.mmu_htc_ctl: Pkt received from gkt in null state, thread 1" */

/* 0in assert -var (~(tmc.tsm2.null_state & htc.load_ret_hw0 & htc.ret_tid_hw0[2]))
 -message "mmu.mmu_htc_ctl: Pkt received from gkt in null state, thread 2" */

/* 0in assert -var (~(tmc.tsm3.null_state & htc.load_ret_hw0 & htc.ret_tid_hw0[3]))
 -message "mmu.mmu_htc_ctl: Pkt received from gkt in null state, thread 3" */

/* 0in assert -var (~(tmc.tsm4.null_state & htc.load_ret_hw0 & htc.ret_tid_hw0[4]))
 -message "mmu.mmu_htc_ctl: Pkt received from gkt in null state, thread 4" */

/* 0in assert -var (~(tmc.tsm5.null_state & htc.load_ret_hw0 & htc.ret_tid_hw0[5]))
 -message "mmu.mmu_htc_ctl: Pkt received from gkt in null state, thread 5" */

/* 0in assert -var (~(tmc.tsm6.null_state & htc.load_ret_hw0 & htc.ret_tid_hw0[6]))
 -message "mmu.mmu_htc_ctl: Pkt received from gkt in null state, thread 6" */

/* 0in assert -var (~(tmc.tsm7.null_state & htc.load_ret_hw0 & htc.ret_tid_hw0[7]))
 -message "mmu.mmu_htc_ctl: Pkt received from gkt in null state, thread 7" */

//////////////////////////////////////////////////////////////////////////////
assign rd_pce = 1'b1;
assign wr_pce = 1'b1;
assign bist_clk_mux_sel = 1'b0;
assign tcu_scan_en_wmr = lb_scan_en_wmr;


assign error_inject_unused[30:24] =
       lsu_asi_error_inject[30:24];
assign error_inject_unused[22:21] =
       lsu_asi_error_inject[22:21];
assign error_inject_unused[19:8] =
       lsu_asi_error_inject[19:8];


//////////////////////////////////////////////////////////////////////////////


mmu_asi_ctl asi ( // FS:wmr_protect
	.wmr_scan_in(asi_wmr_scanin),
	.wmr_scan_out(asi_wmr_scanout),
	.scan_in(asi_scanin),
	.scan_out(asi_scanout),
	.l2clk			(l2clk				),
	.error_inject_enable	(lsu_asi_error_inject	[31   ]	),
	.error_inject_scau	(lsu_asi_error_inject	[23   ]	),
	.error_inject_mrau	(lsu_asi_error_inject	[20   ]	),
	.error_inject_mask	(lsu_asi_error_inject	[7:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk_wmr(spc_aclk_wmr),
  .htc_itlb_clken(htc_itlb_clken[7:0]),
  .htc_dtlb_clken(htc_dtlb_clken[7:0]),
  .lsu_asi_clken(lsu_asi_clken),
  .lsu_mmu_pmen(lsu_mmu_pmen),
  .tlu_tag_access_tid_0_b(tlu_tag_access_tid_0_b[1:0]),
  .tlu_i_tag_access_0_b(tlu_i_tag_access_0_b),
  .tlu_d_tag_access_0_b(tlu_d_tag_access_0_b),
  .tlu_tag_access_tid_1_b(tlu_tag_access_tid_1_b[1:0]),
  .tlu_i_tag_access_1_b(tlu_i_tag_access_1_b),
  .tlu_d_tag_access_1_b(tlu_d_tag_access_1_b),
  .mbi_mra0_write_en(mbi_mra0_write_en),
  .mbi_mra1_write_en(mbi_mra1_write_en),
  .mbi_scp0_write_en(mbi_scp0_write_en),
  .mbi_scp1_write_en(mbi_scp1_write_en),
  .mbi_addr(mbi_addr[4:0]),
  .mbi_run(mbi_run),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_mra0_read_en(mbi_mra0_read_en),
  .mbi_mra1_read_en(mbi_mra1_read_en),
  .mbi_scp0_read_en(mbi_scp0_read_en),
  .mbi_scp1_read_en(mbi_scp1_read_en),
  .mbi_mmu_cmpsel(mbi_mmu_cmpsel[1:0]),
  .mbd_compare(mbd_compare),
  .lsu_rngf_cdbus(lsu_rngf_cdbus[64:0]),
  .tlu_iht_request(tlu_iht_request[7:0]),
  .tlu_dht_request(tlu_dht_request[7:0]),
  .tlu_release_tte(tlu_release_tte[7:0]),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .scp0_data(scp0_data[63:0]),
  .scp1_data(scp1_data[63:0]),
  .scp0_ecc(scp0_ecc[7:0]),
  .scp1_ecc(scp1_ecc[7:0]),
  .sel_scac(sel_scac),
  .sel_scau(sel_scau),
  .ase_mra_rd_data(ase_mra_rd_data[63:0]),
  .mel0_parity(mel0_parity[1:0]),
  .mel1_parity(mel1_parity[1:0]),
  .mel0_parity_err(mel0_parity_err),
  .mel1_parity_err(mel1_parity_err),
  .asd0_asi_rd_data(asd0_asi_rd_data[63:0]),
  .asd1_asi_rd_data(asd1_asi_rd_data[63:0]),
  .asd0_dtte_tag(asd0_dtte_tag[47:0]),
  .asd1_dtte_tag(asd1_dtte_tag[47:0]),
  .asd0_dtte_data(asd0_dtte_data[54:0]),
  .asd1_dtte_data(asd1_dtte_data[54:0]),
  .asd0_itte_index(asd0_itte_index[6:0]),
  .asd1_itte_index(asd1_itte_index[6:0]),
  .asd0_asi_zero_context(asd0_asi_zero_context),
  .asd1_asi_zero_context(asd1_asi_zero_context),
  .htd_tsbptr(htd_tsbptr[39:4]),
  .htc_mra_addr_in(htc_mra_addr_in[4:0]),
  .htc_mra_rd_en(htc_mra_rd_en[1:0]),
  .htc_wr_itlb_data_in(htc_wr_itlb_data_in[7:0]),
  .htc_wr_dtlb_data_in(htc_wr_dtlb_data_in[7:0]),
  .mmu_i_unauth_access(mmu_i_unauth_access[7:0]),
  .mmu_i_tsb_miss(mmu_i_tsb_miss[7:0]),
  .mmu_d_tsb_miss(mmu_d_tsb_miss[7:0]),
  .mmu_i_tte_outofrange(mmu_i_tte_outofrange[7:0]),
  .mmu_d_tte_outofrange(mmu_d_tte_outofrange[7:0]),
  .mmu_i_eccerr(mmu_i_eccerr[7:0]),
  .mmu_d_eccerr(mmu_d_eccerr[7:0]),
  .asi_error_scau(asi_error_scau),
  .asi_error_mrau(asi_error_mrau),
  .asi_error_mask(asi_error_mask[7:0]),
  .asi_scp_addr(asi_scp_addr[4:0]),
  .asi_scp_wr_en(asi_scp_wr_en[1:0]),
  .asi_scp_rd_en(asi_scp_rd_en[1:0]),
  .asi_rd_scp0(asi_rd_scp0),
  .asi_mra_rd_addr_0(asi_mra_rd_addr_0[4:0]),
  .asi_mra_rd_addr_1(asi_mra_rd_addr_1[4:0]),
  .asi_mra_rd_en(asi_mra_rd_en[1:0]),
  .asi_mra_wr_addr(asi_mra_wr_addr[4:0]),
  .asi_mra_wr_en(asi_mra_wr_en[1:0]),
  .asi_mra_rd_en_last(asi_mra_rd_en_last[1:0]),
  .asi_rd_tsb_cfg_0_2(asi_rd_tsb_cfg_0_2),
  .asi_rd_tsb_cfg_1_3(asi_rd_tsb_cfg_1_3),
  .asi_rd_tsb_ptr_(asi_rd_tsb_ptr_),
  .asi_rd_real_range(asi_rd_real_range),
  .asi_rd_physical_offset(asi_rd_physical_offset),
  .asi_sel_mra_0_in(asi_sel_mra_0_in),
  .asi_mra_wr_en_next(asi_mra_wr_en_next),
  .asi_rd_immu_tag_target(asi_rd_immu_tag_target[7:0]),
  .asi_rd_immu_tag_access(asi_rd_immu_tag_access[7:0]),
  .asi_rd_dmmu_tag_target(asi_rd_dmmu_tag_target[7:0]),
  .asi_rd_dmmu_tag_access(asi_rd_dmmu_tag_access[7:0]),
  .asi_rd_i_access_target(asi_rd_i_access_target[1:0]),
  .asi_rd_d_access_target(asi_rd_d_access_target[1:0]),
  .asi_rd_access_target(asi_rd_access_target[1:0]),
  .asi_rd_itte_tag(asi_rd_itte_tag[7:0]),
  .asi_rd_itte_data(asi_rd_itte_data[7:0]),
  .asi_rd_dtte(asi_rd_dtte[6:0]),
  .asi_wr_immu_tag_access(asi_wr_immu_tag_access[7:0]),
  .asi_wr_itlb_data_in(asi_wr_itlb_data_in[7:0]),
  .asi_wr_itlb_data_access(asi_wr_itlb_data_access[7:0]),
  .asi_wr_immu_demap(asi_wr_immu_demap[7:0]),
  .asi_wr_immu_demap_p(asi_wr_immu_demap_p[7:0]),
  .asi_wr_immu_demap_n(asi_wr_immu_demap_n[7:0]),
  .asi_wr_dmmu_tag_access(asi_wr_dmmu_tag_access[7:0]),
  .asi_wr_dtlb_data_in(asi_wr_dtlb_data_in[7:0]),
  .asi_wr_dtlb_data_access(asi_wr_dtlb_data_access[7:0]),
  .asi_wr_partition_id(asi_wr_partition_id[7:0]),
  .asi_wr_dmmu_demap(asi_wr_dmmu_demap[7:0]),
  .asi_wr_dmmu_demap_p(asi_wr_dmmu_demap_p[7:0]),
  .asi_wr_dmmu_demap_s_n(asi_wr_dmmu_demap_s_n[7:0]),
  .asi_dmmu_demap_s(asi_dmmu_demap_s),
  .asi_wr_p_context_0(asi_wr_p_context_0[7:0]),
  .asi_p_context_0_en(asi_p_context_0_en[1:0]),
  .asi_tag_access_sel(asi_tag_access_sel[2:0]),
  .asi_tsb_ptr_req_valid(asi_tsb_ptr_req_valid),
  .asi_tsb_ptr_req(asi_tsb_ptr_req[2:0]),
  .asi_tsb_ptr_number(asi_tsb_ptr_number[1:0]),
  .asi_tsb_hwtw_enable_0(asi_tsb_hwtw_enable_0[1:0]),
  .asi_tsb_hwtw_enable_1(asi_tsb_hwtw_enable_1[1:0]),
  .asi_data_in_real(asi_data_in_real),
  .asi_seg_wr_data(asi_seg_wr_data[63:0]),
  .asi_wr_data(asi_wr_data[63:0]),
  .asi_mra_wr_data(asi_mra_wr_data[63:0]),
  .asi_mra_req_grant(asi_mra_req_grant),
  .asi_demap_r_bit(asi_demap_r_bit),
  .asi_rd_data(asi_rd_data[63:0]),
  .asi_hwtw_config_0(asi_hwtw_config_0[1:0]),
  .asi_hwtw_config_1(asi_hwtw_config_1[1:0]),
  .asi_hwtw_config_2(asi_hwtw_config_2[1:0]),
  .asi_hwtw_config_3(asi_hwtw_config_3[1:0]),
  .asi_hwtw_config_4(asi_hwtw_config_4[1:0]),
  .asi_hwtw_config_5(asi_hwtw_config_5[1:0]),
  .asi_hwtw_config_6(asi_hwtw_config_6[1:0]),
  .asi_hwtw_config_7(asi_hwtw_config_7[1:0]),
  .asi_sel_en(asi_sel_en),
  .asi_i_tag_access_en(asi_i_tag_access_en[7:0]),
  .asi_d_tag_access_en(asi_d_tag_access_en[7:0]),
  .asi_i_data_in_en(asi_i_data_in_en[7:0]),
  .asi_d_data_in_en(asi_d_data_in_en[7:0]),
  .asi_mbist_wdata(asi_mbist_wdata[7:0]),
  .asi_ase_compare_data(asi_ase_compare_data[7:0]),
  .asi_compare_data(asi_compare_data[7:0]),
  .asi_mbd_scp_data(asi_mbd_scp_data[31:0]),
  .asi_mbd_sel_scp(asi_mbd_sel_scp),
  .asi_mbist_ecc_in(asi_mbist_ecc_in[7:0]),
  .asi_mbist_ecc(asi_mbist_ecc[3:2]),
  .asi_mbist_run(asi_mbist_run),
  .asi_ecc_cmpsel_in(asi_ecc_cmpsel_in),
  .asi_ase_cmpsel_in(asi_ase_cmpsel_in[1:0]),
  .mmu_asi_data(mmu_asi_data[64:0]),
  .mmu_asi_read(mmu_asi_read),
  .mmu_write_itlb(mmu_write_itlb[7:0]),
  .mmu_dtlb_reload_stall(mmu_dtlb_reload_stall),
  .mmu_dtlb_reload(mmu_dtlb_reload),
  .mmu_hw_tw_enable(mmu_hw_tw_enable[7:0]),
  .mmu_asi_cecc(mmu_asi_cecc),
  .mmu_asi_uecc(mmu_asi_uecc),
  .mmu_asi_tid(mmu_asi_tid[2:0]),
  .mmu_asi_index(mmu_asi_index[2:0]),
  .mmu_asi_mra_not_sca(mmu_asi_mra_not_sca),
  .mmu_dae_req(mmu_dae_req),
  .mmu_dae_tid(mmu_dae_tid[2:0]),
  .mmu_reload_done(mmu_reload_done[7:0]),
  .mmu_index(mmu_index[6:0]),
  .mmu_mbi_mra0_fail(mmu_mbi_mra0_fail),
  .mmu_mbi_mra1_fail(mmu_mbi_mra1_fail),
  .mmu_mbi_scp0_fail(mmu_mbi_scp0_fail),
  .mmu_mbi_scp1_fail(mmu_mbi_scp1_fail)
);

assign asi_rd_dtte_unused[3] =
       asi_rd_dtte[3];

mmu_asd_dp asd0 ( // FS:wmr_protect
	.wmr_scan_in(asd0_wmr_scanin),
	.wmr_scan_out(asd0_wmr_scanout),
	.scan_in(asd0_scanin),
	.scan_out(asd0_scanout),
	.l2clk			(l2clk				),
	.thread_group		(1'b0				),
	.asd_pc_w		(asd_pc_0_w		[47:13]	),
	.asi_mra_rd_en_last	(asi_mra_rd_en_last	[0   ] ),
        .asi_rd_immu_tag_target	(asi_rd_immu_tag_target	[3:0]	),
        .asi_rd_immu_tag_access	(asi_rd_immu_tag_access	[3:0]	),
        .asi_rd_dmmu_tag_target	(asi_rd_dmmu_tag_target	[3:0]	),
        .asi_rd_dmmu_tag_access	(asi_rd_dmmu_tag_access	[3:0]	),
        .asi_rd_i_access_target	(asi_rd_i_access_target	[0   ]	),
        .asi_rd_d_access_target	(asi_rd_d_access_target	[0   ]	),
        .asi_rd_access_target	(asi_rd_access_target	[0   ]	),
        .asi_rd_itte_tag	(asi_rd_itte_tag	[3:0]	),
        .asi_rd_itte_data	(asi_rd_itte_data	[3:0]	),
        .asi_rd_dtte		(asi_rd_dtte		[2:0]	),
        .asi_wr_immu_tag_access	(asi_wr_immu_tag_access	[3:0]	),
        .asi_i_tag_access_en	(asi_i_tag_access_en	[3:0]	),
        .asi_wr_itlb_data_in	(asi_wr_itlb_data_in	[3:0]	),
        .asi_wr_itlb_data_access(asi_wr_itlb_data_access[3:0]	),
        .asi_wr_immu_demap	(asi_wr_immu_demap	[3:0]	),
        .asi_wr_immu_demap_p	(asi_wr_immu_demap_p	[3:0]	),
        .asi_wr_immu_demap_n	(asi_wr_immu_demap_n	[3:0]	),
        .asi_i_data_in_en	(asi_i_data_in_en	[3:0]	),
        .asi_wr_dmmu_tag_access	(asi_wr_dmmu_tag_access	[3:0]	),
        .asi_d_tag_access_en	(asi_d_tag_access_en	[3:0]	),
        .asi_wr_dtlb_data_in	(asi_wr_dtlb_data_in	[3:0]	),
        .asi_wr_dtlb_data_access(asi_wr_dtlb_data_access[3:0]	),
        .asi_wr_dmmu_demap	(asi_wr_dmmu_demap	[3:0]	),
        .asi_wr_dmmu_demap_p	(asi_wr_dmmu_demap_p	[3:0]	),
        .asi_wr_dmmu_demap_s_n	(asi_wr_dmmu_demap_s_n	[3:0]	),
        .asi_d_data_in_en	(asi_d_data_in_en	[3:0]	),
        .asi_wr_p_context_0	(asi_wr_p_context_0	[3:0]	),
        .asi_p_context_0_en	(asi_p_context_0_en	[0   ]	),
        .tlu_load_i_tag_access_p(tlu_load_i_tag_access_p[3:0]	),
        .tlu_load_i_tag_access_n(tlu_load_i_tag_access_n[3:0]	),
        .asi_mra_rd_addr_bit_1	(asi_mra_rd_addr_0	[1   ]	),
        .mra_data		(mra0_data		[81:0]	),
        .tlu_pc_w		(tlu_pc_0_w		[47:13]	),
        .tlu_load_d_tag_access	(tlu_load_d_tag_access	[3:0]	),
        .tlu_load_d_tag_access_r(tlu_load_d_tag_access_r[3:0]	),
	.htc_wr_itlb_data_in	(htc_wr_itlb_data_in	[3:0]	),
	.htc_wr_dtlb_data_in	(htc_wr_dtlb_data_in	[3:0]	),
	.asd_rd_data		(asd0_rd_data		[81:0] ),
	.asd_asi_rd_data	(asd0_asi_rd_data	[63:0] ),
	.asd_dtte_tag		(asd0_dtte_tag		[47:0] ),
	.asd_dtte_data		(asd0_dtte_data		[54:0] ),
	.asd_itte_tag_data_	(asd0_itte_tag_data_	[47:0] ),
	.asd_itte_index		(asd0_itte_index	[6:0]	),
	.asd_iht_p_ctx_0_0	(asd_i_p_ctx_0_0	[12:0] ),
	.asd_iht_p_ctx_0_1	(asd_i_p_ctx_0_1	[12:0] ),
	.asd_iht_p_ctx_0_2	(asd_i_p_ctx_0_2	[12:0] ),
	.asd_iht_p_ctx_0_3	(asd_i_p_ctx_0_3	[12:0] ),
	.asd_tag_access		(asd0_tag_access	[47:0] ),
	.asd_zero_context	(asd0_zero_context		),
	.asd_asi_zero_context	(asd0_asi_zero_context		),
        .asd_mra_rd_addr_bit_1	(asd0_mra_rd_addr_bit_1		),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_scan_en_wmr(tcu_scan_en_wmr),
  .spc_aclk_wmr(spc_aclk_wmr),
  .ase_lsu_va_w(ase_lsu_va_w[47:13]),
  .ase_lsu_context_w(ase_lsu_context_w[12:0]),
  .asi_wr_data(asi_wr_data[63:0]),
  .asi_dmmu_demap_s(asi_dmmu_demap_s),
  .asi_data_in_real(asi_data_in_real),
  .asi_tag_access_sel(asi_tag_access_sel[2:0]),
  .asi_mra_wr_data(asi_mra_wr_data[39:0]),
  .asi_demap_r_bit(asi_demap_r_bit),
  .asi_rd_tsb_ptr_(asi_rd_tsb_ptr_),
  .htd_tagaccess_din(htd_tagaccess_din[47:0]),
  .htd_tlbdatain_din(htd_tlbdatain_din[38:0]),
  .mmu_use_context_0(mmu_use_context_0),
  .mmu_use_context_1(mmu_use_context_1),
  .mmu_sec_context(mmu_sec_context)

);	

mmu_asd_dp asd1 ( // FS:wmr_protect
	.wmr_scan_in(asd1_wmr_scanin),
	.wmr_scan_out(asd1_wmr_scanout),
	.scan_in(asd1_scanin),
	.scan_out(asd1_scanout),
	.l2clk			(l2clk				),
	.thread_group		(1'b1				),
        .asd_pc_w 		(asd_pc_1_w		[47:13]	),
	.asi_mra_rd_en_last	(asi_mra_rd_en_last	[1   ] ),
        .asi_rd_immu_tag_target	(asi_rd_immu_tag_target	[7:4]	),
        .asi_rd_immu_tag_access	(asi_rd_immu_tag_access	[7:4]	),
        .asi_rd_dmmu_tag_target	(asi_rd_dmmu_tag_target	[7:4]	),
        .asi_rd_dmmu_tag_access	(asi_rd_dmmu_tag_access	[7:4]	),
        .asi_rd_i_access_target	(asi_rd_i_access_target	[1   ]	),
        .asi_rd_d_access_target	(asi_rd_d_access_target	[1   ]	),
        .asi_rd_access_target	(asi_rd_access_target	[1   ]	),
        .asi_rd_itte_tag	(asi_rd_itte_tag	[7:4]	),
        .asi_rd_itte_data	(asi_rd_itte_data	[7:4]	),
        .asi_rd_dtte		(asi_rd_dtte		[6:4]	),
        .asi_wr_immu_tag_access	(asi_wr_immu_tag_access	[7:4]	),
        .asi_i_tag_access_en	(asi_i_tag_access_en	[7:4]	),
        .asi_wr_itlb_data_in	(asi_wr_itlb_data_in	[7:4]	),
        .asi_wr_itlb_data_access(asi_wr_itlb_data_access[7:4]	),
        .asi_wr_immu_demap	(asi_wr_immu_demap	[7:4]	),
        .asi_wr_immu_demap_p	(asi_wr_immu_demap_p	[7:4]	),
        .asi_wr_immu_demap_n	(asi_wr_immu_demap_n	[7:4]	),
        .asi_i_data_in_en	(asi_i_data_in_en	[7:4]	),
        .asi_wr_dmmu_tag_access	(asi_wr_dmmu_tag_access	[7:4]	),
        .asi_d_tag_access_en	(asi_d_tag_access_en	[7:4]	),
        .asi_wr_dtlb_data_in	(asi_wr_dtlb_data_in	[7:4]	),
        .asi_wr_dtlb_data_access(asi_wr_dtlb_data_access[7:4]	),
        .asi_wr_dmmu_demap	(asi_wr_dmmu_demap	[7:4]	),
        .asi_wr_dmmu_demap_p	(asi_wr_dmmu_demap_p	[7:4]	),
        .asi_wr_dmmu_demap_s_n	(asi_wr_dmmu_demap_s_n	[7:4]	),
        .asi_d_data_in_en	(asi_d_data_in_en	[7:4]	),
        .asi_wr_p_context_0	(asi_wr_p_context_0	[7:4]	),
        .asi_p_context_0_en	(asi_p_context_0_en	[1   ]	),
        .tlu_load_i_tag_access_p(tlu_load_i_tag_access_p[7:4]	),
        .tlu_load_i_tag_access_n(tlu_load_i_tag_access_n[7:4]	),
        .asi_mra_rd_addr_bit_1	(asi_mra_rd_addr_1	[1   ]	),
        .mra_data		(mra1_data		[81:0]	),
        .tlu_pc_w		(tlu_pc_1_w		[47:13]	),
        .tlu_load_d_tag_access	(tlu_load_d_tag_access	[7:4]	),
        .tlu_load_d_tag_access_r(tlu_load_d_tag_access_r[7:4]	),
	.htc_wr_itlb_data_in	(htc_wr_itlb_data_in	[7:4]	),
	.htc_wr_dtlb_data_in	(htc_wr_dtlb_data_in	[7:4]	),
	.asd_rd_data		(asd1_rd_data		[81:0]	),
	.asd_asi_rd_data	(asd1_asi_rd_data	[63:0] ),
	.asd_dtte_tag		(asd1_dtte_tag		[47:0] ),
	.asd_dtte_data		(asd1_dtte_data		[54:0] ),
	.asd_itte_tag_data_	(asd1_itte_tag_data_	[47:0] ),
	.asd_itte_index		(asd1_itte_index	[6:0]	),
	.asd_iht_p_ctx_0_0	(asd_i_p_ctx_0_4	[12:0] ),
	.asd_iht_p_ctx_0_1	(asd_i_p_ctx_0_5	[12:0] ),
	.asd_iht_p_ctx_0_2	(asd_i_p_ctx_0_6	[12:0] ),
	.asd_iht_p_ctx_0_3	(asd_i_p_ctx_0_7	[12:0] ),
	.asd_tag_access		(asd1_tag_access	[47:0] ),
	.asd_zero_context	(asd1_zero_context		),
	.asd_asi_zero_context	(asd1_asi_zero_context		),
        .asd_mra_rd_addr_bit_1	(asd1_mra_rd_addr_bit_1		),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_scan_en_wmr(tcu_scan_en_wmr),
  .spc_aclk_wmr(spc_aclk_wmr),
  .ase_lsu_va_w(ase_lsu_va_w[47:13]),
  .ase_lsu_context_w(ase_lsu_context_w[12:0]),
  .asi_wr_data(asi_wr_data[63:0]),
  .asi_dmmu_demap_s(asi_dmmu_demap_s),
  .asi_data_in_real(asi_data_in_real),
  .asi_tag_access_sel(asi_tag_access_sel[2:0]),
  .asi_mra_wr_data(asi_mra_wr_data[39:0]),
  .asi_demap_r_bit(asi_demap_r_bit),
  .asi_rd_tsb_ptr_(asi_rd_tsb_ptr_),
  .htd_tagaccess_din(htd_tagaccess_din[47:0]),
  .htd_tlbdatain_din(htd_tlbdatain_din[38:0]),
  .mmu_use_context_0(mmu_use_context_0),
  .mmu_use_context_1(mmu_use_context_1),
  .mmu_sec_context(mmu_sec_context)
);	

mmu_ase_dp ase (
        .scan_in(ase_scanin),
        .scan_out(ase_scanout),
        .l2clk			(l2clk				),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .lsu_va_b(lsu_va_b[47:0]),
  .lsu_context_b(lsu_context_b[12:0]),
  .asi_rd_tsb_cfg_0_2(asi_rd_tsb_cfg_0_2),
  .asi_rd_tsb_cfg_1_3(asi_rd_tsb_cfg_1_3),
  .asi_rd_real_range(asi_rd_real_range),
  .asi_rd_physical_offset(asi_rd_physical_offset),
  .asi_sel_mra_0_in(asi_sel_mra_0_in),
  .asi_mra_wr_en_next(asi_mra_wr_en_next),
  .asi_mra_wr_data(asi_mra_wr_data[63:0]),
  .asd0_rd_data(asd0_rd_data[81:0]),
  .asd1_rd_data(asd1_rd_data[81:0]),
  .asd0_itte_tag_data_(asd0_itte_tag_data_[47:0]),
  .asd1_itte_tag_data_(asd1_itte_tag_data_[47:0]),
  .asi_mbist_run(asi_mbist_run),
  .asi_ecc_cmpsel_in(asi_ecc_cmpsel_in),
  .asi_ase_cmpsel_in(asi_ase_cmpsel_in[1:0]),
  .asi_mbist_wdata(asi_mbist_wdata[7:0]),
  .asi_ase_compare_data(asi_ase_compare_data[7:0]),
  .mel0_parity(mel0_parity[1:0]),
  .mel1_parity(mel1_parity[1:0]),
  .ase_mra_wr_data(ase_mra_wr_data[81:0]),
  .ase_mra_wr_data_minbuf(ase_mra_wr_data_minbuf[81:0]),
  .ase_mra_rd_data(ase_mra_rd_data[63:0]),
  .ase_lsu_va_w(ase_lsu_va_w[47:13]),
  .ase_lsu_context_w(ase_lsu_context_w[12:0]),
  .ase_mbd_mbist_data(ase_mbd_mbist_data[31:0]),
  .mmu_itte_tag_data(mmu_itte_tag_data[47:0])
);


// Parity generation for both MRAs (only one write source:  ASI bus)
mmu_mec_dp meg1 (
	.data_in		(ase_mra_wr_data	[81:41]	),
	.parity_in		({1 {1'b0}}			),
	.parity_out		(meg_parity		[1   ]	),
	.parity_err		(meg1_parity_err_unused		)
);

mmu_mec_dp meg0 (
	.data_in		(ase_mra_wr_data	[40:0]	),
	.parity_in		({1 {1'b0}}			),
	.parity_out		(meg_parity		[0   ]	),
	.parity_err		(meg0_parity_err_unused		)
);

mmu_mem_dp mem1 (
	.asi_error_inject	(asi_error_mrau			),
	.asi_error_mask		(1'b1				),
	.asi_mbist_ecc		(asi_mbist_ecc		[3   ]	),
	.parity_in		(meg_parity		[1   ]	),
	.parity_out		(mem_parity		[1   ]	),
  .asi_mbist_run(asi_mbist_run)
);

mmu_mem_dp mem0 (
	.asi_error_inject	(asi_error_mrau			),
	.asi_error_mask		(1'b1				),
	.asi_mbist_ecc		(asi_mbist_ecc		[2   ]	),
	.parity_in		(meg_parity		[0   ]	),
	.parity_out		(mem_parity		[0   ]	),
  .asi_mbist_run(asi_mbist_run)
);

// Parity error detection for MRA
mmu_mel_dp mel0 (
	.scan_in(mel0_scanin),
	.scan_out(mel0_scanout),
	.l2clk			(l2clk				),
	.mra_parity		(mra0_parity		[1:0]	),
	.med0_parity_err	(med00_parity_err		),
	.med1_parity_err	(med01_parity_err		),
	.mel_crit_parity	(mel0_crit_parity	[1:0]	),
	.mel_parity		(mel0_parity		[1:0]	),
	.mel_parity_err		(mel0_parity_err		),
	.mel_htc_parity_err	(mel0_htc_parity_err		),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tlu_cerer_mrau(tlu_cerer_mrau),
  .tlu_cerer_hwtwmu(tlu_cerer_hwtwmu)
);

mmu_mec_dp med01 (
	.data_in		(asd0_rd_data		[81:41]	),
	.parity_in		(mel0_crit_parity	[1   ]	),
	.parity_out		(med01_parity_out_unused	),
	.parity_err		(med01_parity_err		)
);

mmu_mec_dp med00 (
	.data_in		(asd0_rd_data		[40:0]	),
	.parity_in		(mel0_crit_parity	[0   ]	),
	.parity_out		(med00_parity_out_unused	),
	.parity_err		(med00_parity_err		)
);

n2_com_dp_32x84_cust mra0 (
        .tcu_aclk		(spc_aclk			),
        .tcu_bclk		(spc_bclk			),
        .scan_in(mra0_scanin),
        .scan_out(mra0_scanout),
        .rdclk			(l2clk				),
        .wrclk			(l2clk				),
	.rd_adr			({asi_mra_rd_addr_0	[4:2],
				  asd0_mra_rd_addr_bit_1       ,
				  asi_mra_rd_addr_0	[0   ]}),
	.rd_en			(asi_mra_rd_en		[0   ]	),
	.wr_adr			(asi_mra_wr_addr	[4:0]	),
	.wr_en			(asi_mra_wr_en		[0   ] ),
	.din			({mem_parity		[1:0],
				  ase_mra_wr_data_minbuf	[81:0]}),
	.dout			({mra0_parity		[1:0],
				  mra0_data		[81:0]}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);

// ECC error detection for MRA
mmu_mel_dp mel1 (
	.scan_in(mel1_scanin),
	.scan_out(mel1_scanout),
	.l2clk			(l2clk				),
	.mra_parity		(mra1_parity		[1:0]	),
	.med0_parity_err	(med10_parity_err		),
	.med1_parity_err	(med11_parity_err		),
	.mel_crit_parity	(mel1_crit_parity	[1:0]	),
	.mel_parity		(mel1_parity		[1:0]	),
	.mel_parity_err		(mel1_parity_err		),
	.mel_htc_parity_err	(mel1_htc_parity_err		),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tlu_cerer_mrau(tlu_cerer_mrau),
  .tlu_cerer_hwtwmu(tlu_cerer_hwtwmu)
);

mmu_mec_dp med11 (
	.data_in		(asd1_rd_data		[81:41]	),
	.parity_in		(mel1_crit_parity	[1   ]	),
	.parity_out		(med11_parity_out_unused	),
	.parity_err		(med11_parity_err		)
);

mmu_mec_dp med10 (
	.data_in		(asd1_rd_data		[40:0]	),
	.parity_in		(mel1_crit_parity	[0   ]	),
	.parity_out		(med10_parity_out_unused	),
	.parity_err		(med10_parity_err		)
);

n2_com_dp_32x84_cust mra1 (
        .tcu_aclk		(spc_aclk			),
        .tcu_bclk		(spc_bclk			),
        .scan_in(mra1_scanin),
        .scan_out(mra1_scanout),
        .rdclk			(l2clk				),
        .wrclk			(l2clk				),
	.rd_adr			({asi_mra_rd_addr_1	[4:2],
				  asd1_mra_rd_addr_bit_1       ,
				  asi_mra_rd_addr_1	[0   ]}),
	.rd_en			(asi_mra_rd_en		[1   ]	),
	.wr_adr			(asi_mra_wr_addr	[4:0]	),
	.wr_en			(asi_mra_wr_en		[1   ] ),
	.din			({mem_parity		[1:0],
				  ase_mra_wr_data_minbuf	[81:0]}),
	.dout			({mra1_parity		[1:0],
				  mra1_data		[81:0]}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);


// ECC generation for scratchpad arrays
mmu_seg_dp seg (
	.data_in		({{3 {1'b0}}		       ,
				 asi_seg_wr_data	[63:0]}),
	.ecc_out		(seg_ecc		[7:0]	)
);

mmu_eem_dp sem (
	.asi_error_inject	(asi_error_scau			),
	.ecc_in			(seg_ecc		[7:0]	),
	.ecc_out		(sem_ecc		[7:0]	),
  .asi_error_mask(asi_error_mask[7:0]),
  .asi_mbist_ecc_in(asi_mbist_ecc_in[7:0]),
  .asi_mbist_run(asi_mbist_run)
);

// ECC error detection for scratchpad arrays
mmu_sel_dp sel (
	.scan_in(sel_scanin),
	.scan_out(sel_scanout),
	.l2clk			(l2clk				),
	.sel_syndrome		(mmu_asi_index		[10:3]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tlu_cerer_scac(tlu_cerer_scac),
  .tlu_cerer_scau(tlu_cerer_scau),
  .asi_sel_en(asi_sel_en),
  .asi_rd_scp0(asi_rd_scp0),
  .sed_syndrome(sed_syndrome[7:0]),
  .scp0_ecc(scp0_ecc[7:0]),
  .scp1_ecc(scp1_ecc[7:0]),
  .sed_cecc_err(sed_cecc_err),
  .sed_uecc_err(sed_uecc_err),
  .sel_crit_ecc(sel_crit_ecc[7:0]),
  .sel_scac(sel_scac),
  .sel_scau(sel_scau)
);

mmu_sed_dp sed (
	.data_in		({{3 {1'b0}}		       ,
				 asi_rd_data		[63:0]}),
	.ecc_in			(sel_crit_ecc		[7:0]	),
	.syndrome		(sed_syndrome		[7:0]	),
	.cecc_err		(sed_cecc_err			),
	.uecc_err		(sed_uecc_err			)
);

n2_com_dp_32x72_cust scp0 (
        .tcu_aclk		(spc_aclk			),
        .tcu_bclk		(spc_bclk			),
        .scan_in(scp0_scanin),
        .scan_out(scp0_scanout),
        .rdclk			(l2clk				),
        .wrclk			(l2clk				),
	.rd_adr			(asi_scp_addr		[4:0]	),
	.rd_en			(asi_scp_rd_en		[0   ]	),
	.wr_adr			(asi_scp_addr		[4:0]	),
	.wr_en			(asi_scp_wr_en		[0   ]	),
	.din			({sem_ecc		[7:0],
				  asi_wr_data		[63:0]}),
	.dout			({scp0_ecc		[7:0],
				  scp0_data		[63:0]}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);

n2_com_dp_32x72_cust scp1 (
        .tcu_aclk		(spc_aclk			),
        .tcu_bclk		(spc_bclk			),
        .scan_in(scp1_scanin),
        .scan_out(scp1_scanout),
        .rdclk			(l2clk				),
        .wrclk			(l2clk				),
	.rd_adr			(asi_scp_addr		[4:0]	),
	.rd_en			(asi_scp_rd_en		[1   ]	),
	.wr_adr			(asi_scp_addr		[4:0]	),
	.wr_en			(asi_scp_wr_en		[1   ]	),
	.din			({sem_ecc		[7:0],
				  asi_wr_data		[63:0]}),
	.dout			({scp1_ecc		[7:0],
				  scp1_data		[63:0]}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);

mmu_htc_ctl htc ( // FS:wmr_protect
    .wmr_scan_in(htc_wmr_scanin),
    .wmr_scan_out(htc_wmr_scanout),
    .scan_in(htc_scanin),
    .scan_out(htc_scanout),
    .l2clk(l2clk),
    .mel0_parity_err    (mel0_htc_parity_err),
    .mel1_parity_err    (mel1_htc_parity_err),
    .mmu_reload_done	(mmu_reload_done_unused		[7:0]	),
    .htc_thr0_err_type	(mmu_thr0_err_type		[2:0]	),
    .htc_thr1_err_type	(mmu_thr1_err_type		[2:0]	),
    .htc_thr2_err_type	(mmu_thr2_err_type		[2:0]	),
    .htc_thr3_err_type	(mmu_thr3_err_type		[2:0]	),
    .htc_thr4_err_type	(mmu_thr4_err_type		[2:0]	),
    .htc_thr5_err_type	(mmu_thr5_err_type		[2:0]	),
    .htc_thr6_err_type	(mmu_thr6_err_type		[2:0]	),
    .htc_thr7_err_type	(mmu_thr7_err_type		[2:0]	),
    .htc_thr0_err_index	(mmu_thr0_err_index		[2:0]	),
    .htc_thr1_err_index	(mmu_thr1_err_index		[2:0]	),
    .htc_thr2_err_index	(mmu_thr2_err_index		[2:0]	),
    .htc_thr3_err_index	(mmu_thr3_err_index		[2:0]	),
    .htc_thr4_err_index	(mmu_thr4_err_index		[2:0]	),
    .htc_thr5_err_index	(mmu_thr5_err_index		[2:0]	),
    .htc_thr6_err_index	(mmu_thr6_err_index		[2:0]	),
    .htc_thr7_err_index	(mmu_thr7_err_index		[2:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .lsu_mmu_pmen(lsu_mmu_pmen),
  .spc_core_running_status(spc_core_running_status[7:0]),
  .l15_mmu_cpkt(l15_mmu_cpkt[17:0]),
  .l15_mmu_valid(l15_mmu_valid),
  .asi_tsb_ptr_req_valid(asi_tsb_ptr_req_valid),
  .asi_tsb_ptr_req(asi_tsb_ptr_req[2:0]),
  .asi_tsb_ptr_number(asi_tsb_ptr_number[1:0]),
  .asd0_zero_context(asd0_zero_context),
  .asd1_zero_context(asd1_zero_context),
  .asi_wr_partition_id(asi_wr_partition_id[7:0]),
  .asi_wr_data(asi_wr_data[2:0]),
  .asi_hwtw_config_0(asi_hwtw_config_0[1:0]),
  .asi_hwtw_config_1(asi_hwtw_config_1[1:0]),
  .asi_hwtw_config_2(asi_hwtw_config_2[1:0]),
  .asi_hwtw_config_3(asi_hwtw_config_3[1:0]),
  .asi_hwtw_config_4(asi_hwtw_config_4[1:0]),
  .asi_hwtw_config_5(asi_hwtw_config_5[1:0]),
  .asi_hwtw_config_6(asi_hwtw_config_6[1:0]),
  .asi_hwtw_config_7(asi_hwtw_config_7[1:0]),
  .asi_tsb_hwtw_enable_0(asi_tsb_hwtw_enable_0[1:0]),
  .asi_tsb_hwtw_enable_1(asi_tsb_hwtw_enable_1[1:0]),
  .htd_ra2pa_lower_hit_hw4(htd_ra2pa_lower_hit_hw4),
  .htd_ra2pa_upper_hit_hw4(htd_ra2pa_upper_hit_hw4),
  .htd_razero_hw4(htd_razero_hw4),
  .htd_range_en_hw4(htd_range_en_hw4),
  .htd_zeroctx_m0(htd_zeroctx_m0[7:0]),
  .htd_zeroctx_hw1(htd_zeroctx_hw1),
  .htd_usectx0_hw1(htd_usectx0_hw1),
  .htd_usectx1_hw1(htd_usectx1_hw1),
  .htd_ranotpa_hw1(htd_ranotpa_hw1),
  .htd_ptr_hit0_hw1(htd_ptr_hit0_hw1),
  .htd_ptr_hit1_hw1(htd_ptr_hit1_hw1),
  .htd_ptr_hit2_hw1(htd_ptr_hit2_hw1),
  .htd_ctx_hit_hw1(htd_ctx_hit_hw1),
  .htd_tte_ep_hw1(htd_tte_ep_hw1),
  .htd_dmiss_hw1(htd_dmiss_hw1),
  .htd_pred0_idx_m0(htd_pred0_idx_m0[5:0]),
  .htd_pred1_idx_m0(htd_pred1_idx_m0[5:0]),
  .htd_pred0_m0(htd_pred0_m0[15:0]),
  .htd_pred1_m0(htd_pred1_m0[15:0]),
  .htd_dmiss(htd_dmiss[7:0]),
  .htd_sec_ctx(htd_sec_ctx[7:0]),
  .tlu_iht_request(tlu_iht_request[7:0]),
  .tlu_dht_request(tlu_dht_request[7:0]),
  .l15_mmu_grant(l15_mmu_grant),
  .asi_mra_req_grant(asi_mra_req_grant),
  .tsm_rqv(tsm_rqv[7:0]),
  .tsm_tsb_miss_hw2(tsm_tsb_miss_hw2[7:0]),
  .trs_rqv(trs_rqv[7:0]),
  .trs_null_st(trs_null_st[7:0]),
  .trs_waitrr3_st(trs_waitrr3_st[7:0]),
  .trs_ecc_err(trs_ecc_err[7:0]),
  .trs_ep_err(trs_ep_err[7:0]),
  .trs0_err_type(trs0_err_type[2:0]),
  .trs1_err_type(trs1_err_type[2:0]),
  .trs2_err_type(trs2_err_type[2:0]),
  .trs3_err_type(trs3_err_type[2:0]),
  .trs4_err_type(trs4_err_type[2:0]),
  .trs5_err_type(trs5_err_type[2:0]),
  .trs6_err_type(trs6_err_type[2:0]),
  .trs7_err_type(trs7_err_type[2:0]),
  .trs0_err_index(trs0_err_index[2:0]),
  .trs1_err_index(trs1_err_index[2:0]),
  .trs2_err_index(trs2_err_index[2:0]),
  .trs3_err_index(trs3_err_index[2:0]),
  .trs4_err_index(trs4_err_index[2:0]),
  .trs5_err_index(trs5_err_index[2:0]),
  .trs6_err_index(trs6_err_index[2:0]),
  .trs7_err_index(trs7_err_index[2:0]),
  .tlu_cerer_hwtwl2(tlu_cerer_hwtwl2),
  .tlu_cerer_hwtwmu(tlu_cerer_hwtwmu),
  .htc_core_running(htc_core_running[7:0]),
  .htc_m1_clken(htc_m1_clken),
  .htc_hw3_clken(htc_hw3_clken),
  .htc_hw4_clken(htc_hw4_clken),
  .mmu_i_unauth_access(mmu_i_unauth_access[7:0]),
  .mmu_i_tsb_miss(mmu_i_tsb_miss[7:0]),
  .mmu_d_tsb_miss(mmu_d_tsb_miss[7:0]),
  .mmu_use_context_0(mmu_use_context_0),
  .mmu_use_context_1(mmu_use_context_1),
  .mmu_sec_context(mmu_sec_context),
  .htc_mra_addr_in(htc_mra_addr_in[4:0]),
  .htc_mra_rd_en(htc_mra_rd_en[1:0]),
  .htc_wr_itlb_data_in(htc_wr_itlb_data_in[7:0]),
  .htc_wr_dtlb_data_in(htc_wr_dtlb_data_in[7:0]),
  .htc_dtlb_clken(htc_dtlb_clken[7:0]),
  .htc_itlb_clken(htc_itlb_clken[7:0]),
  .htc_zero_ctx_m2(htc_zero_ctx_m2),
  .htc_upd_pred_idx_hw2(htc_upd_pred_idx_hw2[5:3]),
  .htc_upd_grp(htc_upd_grp[7:0]),
  .htc_upd_grp_x(htc_upd_grp_x[7:0]),
  .htc_new_pred_bit(htc_new_pred_bit[1:0]),
  .htc_wrpred0_hw2(htc_wrpred0_hw2),
  .htc_wrpred1_hw2(htc_wrpred1_hw2),
  .htc_wrpred2_hw2(htc_wrpred2_hw2),
  .htc_wrpred3_hw2(htc_wrpred3_hw2),
  .htc_tlb_miss_m(htc_tlb_miss_m[7:0]),
  .mmu_l15_cpkt(mmu_l15_cpkt[4:0]),
  .htc_l15_en(htc_l15_en),
  .mmu_l15_valid(mmu_l15_valid),
  .htc_wr_q0new_nogrant(htc_wr_q0new_nogrant),
  .htc_wr_q0new_grant(htc_wr_q0new_grant),
  .htc_wr_q1new(htc_wr_q1new),
  .htc_shift_q1_grant(htc_shift_q1_grant),
  .htc_wr_m3new(htc_wr_m3new),
  .htc_wr_m3q0(htc_wr_m3q0),
  .htc_mra_sel_0(htc_mra_sel_0),
  .htc_sel_mra_lo(htc_sel_mra_lo),
  .htc_conf_index_m2(htc_conf_index_m2[1:0]),
  .htc_vld_tsbptr_m2(htc_vld_tsbptr_m2[7:0]),
  .htc_rd_tteq(htc_rd_tteq[7:0]),
  .htc_ra2pahit_hw5(htc_ra2pahit_hw5[7:0]),
  .htc_ranotpax_hw5(htc_ranotpax_hw5[7:0]),
  .htc_cindex_bit0(htc_cindex_bit0[7:0]),
  .htc_cindex_bit1(htc_cindex_bit1[7:0]),
  .htc_rrindex_bit0(htc_rrindex_bit0[7:0]),
  .htc_rrindex_bit1(htc_rrindex_bit1[7:0]),
  .htc_pid0_m0(htc_pid0_m0[2:0]),
  .htc_pid1_m0(htc_pid1_m0[2:0]),
  .htc_tsbrd_valid_m0(htc_tsbrd_valid_m0[7:0]),
  .htc_thr_valid_hw3(htc_thr_valid_hw3[7:0]),
  .htc_thr_prevalid_hw3(htc_thr_prevalid_hw3[7:0]),
  .htc_va_rd_m2_in(htc_va_rd_m2_in[7:0]),
  .htc_ranotpa_hw4(htc_ranotpa_hw4),
  .htc_data_rcvd_hw1(htc_data_rcvd_hw1[7:0]),
  .htc_tsb_hit_hw1(htc_tsb_hit_hw1[7:0]),
  .htc_tsb_done_hw2(htc_tsb_done_hw2[7:0]),
  .htc_thr_valid_m1(htc_thr_valid_m1[7:0]),
  .htc_thr_valid_m0(htc_thr_valid_m0[7:0]),
  .htc_hwtw_burst(htc_hwtw_burst[7:0]),
  .mmu_i_tte_outofrange(mmu_i_tte_outofrange[7:0]),
  .mmu_d_tte_outofrange(mmu_d_tte_outofrange[7:0]),
  .rr_ecc_err_type(rr_ecc_err_type[1:0]),
  .cfg_ecc_err_type(cfg_ecc_err_type[1:0]),
  .l2_ecc_err_type(l2_ecc_err_type[1:0]),
  .rr_ecc_err_hw5(rr_ecc_err_hw5[7:0]),
  .cfg_ecc_err_m3(cfg_ecc_err_m3[7:0]),
  .l2_ecc_err_hw1(l2_ecc_err_hw1[7:0]),
  .htc_ep_miss_hw1(htc_ep_miss_hw1[7:0]),
  .cfg_ecc_err_index(cfg_ecc_err_index[2:0]),
  .rr_ecc_err_index(rr_ecc_err_index[2:0]),
  .mmu_i_eccerr(mmu_i_eccerr[7:0]),
  .mmu_d_eccerr(mmu_d_eccerr[7:0]),
  .mmu_i_l2cerr(mmu_i_l2cerr[7:0]),
  .mmu_d_l2cerr(mmu_d_l2cerr[7:0]),
  .mmu_pmu_l2ret(mmu_pmu_l2ret),
  .mmu_pmu_l2miss(mmu_pmu_l2miss),
  .mmu_pmu_dtlb(mmu_pmu_dtlb),
  .mmu_pmu_tid(mmu_pmu_tid[2:0]),
  .spc_aclk_wmr(spc_aclk_wmr)
);

mmu_htd_dp htd (
    .scan_in(htd_scanin),
    .scan_out(htd_scanout),
    .l2clk(l2clk),
    .asi_data_in_real(1'b0),
    .tlu_pc_0_w(asd_pc_0_w[47:13]),
    .tlu_pc_1_w(asd_pc_1_w[47:13]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_muxtest(tcu_muxtest),
  .tcu_dectest(tcu_dectest),
  .htc_core_running(htc_core_running[7:0]),
  .htc_m1_clken(htc_m1_clken),
  .htc_hw3_clken(htc_hw3_clken),
  .htc_hw4_clken(htc_hw4_clken),
  .asd0_tag_access(asd0_tag_access[47:0]),
  .asd1_tag_access(asd1_tag_access[47:0]),
  .htc_tsbrd_valid_m0(htc_tsbrd_valid_m0[7:0]),
  .ase_lsu_va_w(ase_lsu_va_w[47:13]),
  .lsu_context_b(lsu_context_b[12:0]),
  .lsu_tlu_dsfsr_ct_b(lsu_tlu_dsfsr_ct_b[1:0]),
  .l15_spc_data1(l15_spc_data1[127:0]),
  .l15_mmu_cpkt(l15_mmu_cpkt[8:3]),
  .l15_mmu_grant(l15_mmu_grant),
  .htc_zero_ctx_m2(htc_zero_ctx_m2),
  .htc_ranotpa_hw4(htc_ranotpa_hw4),
  .htc_pid0_m0(htc_pid0_m0[2:0]),
  .htc_pid1_m0(htc_pid1_m0[2:0]),
  .htc_thr_prevalid_hw3(htc_thr_prevalid_hw3[7:0]),
  .htc_va_rd_m2_in(htc_va_rd_m2_in[7:0]),
  .htc_l15_en(htc_l15_en),
  .htc_vld_tsbptr_m2(htc_vld_tsbptr_m2[7:0]),
  .trs_null_st(trs_null_st[7:0]),
  .htc_mra_sel_0(htc_mra_sel_0),
  .htc_sel_mra_lo(htc_sel_mra_lo),
  .mra0_data(mra0_data[81:0]),
  .mra1_data(mra1_data[81:0]),
  .htc_conf_index_m2(htc_conf_index_m2[1:0]),
  .htc_upd_pred_idx_hw2(htc_upd_pred_idx_hw2[5:3]),
  .htc_upd_grp(htc_upd_grp[7:0]),
  .htc_upd_grp_x(htc_upd_grp_x[7:0]),
  .htc_new_pred_bit(htc_new_pred_bit[1:0]),
  .htc_wrpred0_hw2(htc_wrpred0_hw2),
  .htc_wrpred1_hw2(htc_wrpred1_hw2),
  .htc_wrpred2_hw2(htc_wrpred2_hw2),
  .htc_wrpred3_hw2(htc_wrpred3_hw2),
  .htc_wr_q0new_nogrant(htc_wr_q0new_nogrant),
  .htc_wr_q0new_grant(htc_wr_q0new_grant),
  .htc_wr_q1new(htc_wr_q1new),
  .htc_shift_q1_grant(htc_shift_q1_grant),
  .htc_wr_m3new(htc_wr_m3new),
  .htc_wr_m3q0(htc_wr_m3q0),
  .htc_rd_tteq(htc_rd_tteq[7:0]),
  .tlu_iht_request(tlu_iht_request[7:0]),
  .tlu_dht_request(tlu_dht_request[7:0]),
  .tlu_mmu_tl_gt_0(tlu_mmu_tl_gt_0[7:0]),
  .asd_i_p_ctx_0_0(asd_i_p_ctx_0_0[12:0]),
  .asd_i_p_ctx_0_1(asd_i_p_ctx_0_1[12:0]),
  .asd_i_p_ctx_0_2(asd_i_p_ctx_0_2[12:0]),
  .asd_i_p_ctx_0_3(asd_i_p_ctx_0_3[12:0]),
  .asd_i_p_ctx_0_4(asd_i_p_ctx_0_4[12:0]),
  .asd_i_p_ctx_0_5(asd_i_p_ctx_0_5[12:0]),
  .asd_i_p_ctx_0_6(asd_i_p_ctx_0_6[12:0]),
  .asd_i_p_ctx_0_7(asd_i_p_ctx_0_7[12:0]),
  .htd_range_en_hw4(htd_range_en_hw4),
  .htd_zeroctx_hw1(htd_zeroctx_hw1),
  .htd_usectx0_hw1(htd_usectx0_hw1),
  .htd_usectx1_hw1(htd_usectx1_hw1),
  .htd_ranotpa_hw1(htd_ranotpa_hw1),
  .htd_ptr_hit0_hw1(htd_ptr_hit0_hw1),
  .htd_ptr_hit1_hw1(htd_ptr_hit1_hw1),
  .htd_ptr_hit2_hw1(htd_ptr_hit2_hw1),
  .htd_ctx_hit_hw1(htd_ctx_hit_hw1),
  .htd_tte_ep_hw1(htd_tte_ep_hw1),
  .htd_dmiss_hw1(htd_dmiss_hw1),
  .htd_ra2pa_lower_hit_hw4(htd_ra2pa_lower_hit_hw4),
  .htd_ra2pa_upper_hit_hw4(htd_ra2pa_upper_hit_hw4),
  .htd_razero_hw4(htd_razero_hw4),
  .htd_tagaccess_din(htd_tagaccess_din[47:0]),
  .htd_tlbdatain_din(htd_tlbdatain_din[38:0]),
  .mmu_l15_addr(mmu_l15_addr[39:4]),
  .htd_dmiss(htd_dmiss[7:0]),
  .htd_sec_ctx(htd_sec_ctx[7:0]),
  .htd_pred0_idx_m0(htd_pred0_idx_m0[5:0]),
  .htd_pred1_idx_m0(htd_pred1_idx_m0[5:0]),
  .htd_pred0_m0(htd_pred0_m0[15:0]),
  .htd_pred1_m0(htd_pred1_m0[15:0]),
  .htd_tsbptr(htd_tsbptr[39:4]),
  .htd_zeroctx_m0(htd_zeroctx_m0[7:0])                
);

mmu_tmc_ctl tmc (
    .scan_in(tmc_scanin),
    .scan_out(tmc_scanout),
    .l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .htc_data_rcvd_hw1(htc_data_rcvd_hw1[7:0]),
  .htc_tlb_miss_m(htc_tlb_miss_m[7:0]),
  .htc_tsb_done_hw2(htc_tsb_done_hw2[7:0]),
  .htc_vld_tsbptr_m2(htc_vld_tsbptr_m2[7:0]),
  .htc_thr_valid_m1(htc_thr_valid_m1[7:0]),
  .htc_thr_valid_m0(htc_thr_valid_m0[7:0]),
  .htc_hwtw_burst(htc_hwtw_burst[7:0]),
  .htc_cindex_bit0(htc_cindex_bit0[7:0]),
  .htc_cindex_bit1(htc_cindex_bit1[7:0]),
  .trs_eperr_st(trs_eperr_st[7:0]),
  .trs_eccerr_st(trs_eccerr_st[7:0]),
  .tsm_tsb_miss_hw2(tsm_tsb_miss_hw2[7:0]),
  .tsm_rqv(tsm_rqv[7:0]),
  .tsm_waitfortte(tsm_waitfortte[7:0])
);

mmu_trc_ctl trc (
    .scan_in(trc_scanin),
    .scan_out(trc_scanout),
    .l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .htc_tsb_hit_hw1(htc_tsb_hit_hw1[7:0]),
  .htc_thr_valid_hw3(htc_thr_valid_hw3[7:0]),
  .htc_ra2pahit_hw5(htc_ra2pahit_hw5[7:0]),
  .htc_ranotpax_hw5(htc_ranotpax_hw5[7:0]),
  .tsm_waitfortte(tsm_waitfortte[7:0]),
  .htc_ep_miss_hw1(htc_ep_miss_hw1[7:0]),
  .htc_rrindex_bit0(htc_rrindex_bit0[7:0]),
  .htc_rrindex_bit1(htc_rrindex_bit1[7:0]),
  .l2_ecc_err_hw1(l2_ecc_err_hw1[7:0]),
  .cfg_ecc_err_m3(cfg_ecc_err_m3[7:0]),
  .rr_ecc_err_hw5(rr_ecc_err_hw5[7:0]),
  .l2_ecc_err_type(l2_ecc_err_type[1:0]),
  .cfg_ecc_err_type(cfg_ecc_err_type[1:0]),
  .rr_ecc_err_type(rr_ecc_err_type[1:0]),
  .cfg_ecc_err_index(cfg_ecc_err_index[2:0]),
  .rr_ecc_err_index(rr_ecc_err_index[2:0]),
  .trs_rqv(trs_rqv[7:0]),
  .trs_null_st(trs_null_st[7:0]),
  .trs_waitrr3_st(trs_waitrr3_st[7:0]),
  .trs_ep_err(trs_ep_err[7:0]),
  .trs_ecc_err(trs_ecc_err[7:0]),
  .trs0_err_type(trs0_err_type[2:0]),
  .trs1_err_type(trs1_err_type[2:0]),
  .trs2_err_type(trs2_err_type[2:0]),
  .trs3_err_type(trs3_err_type[2:0]),
  .trs4_err_type(trs4_err_type[2:0]),
  .trs5_err_type(trs5_err_type[2:0]),
  .trs6_err_type(trs6_err_type[2:0]),
  .trs7_err_type(trs7_err_type[2:0]),
  .trs0_err_index(trs0_err_index[2:0]),
  .trs1_err_index(trs1_err_index[2:0]),
  .trs2_err_index(trs2_err_index[2:0]),
  .trs3_err_index(trs3_err_index[2:0]),
  .trs4_err_index(trs4_err_index[2:0]),
  .trs5_err_index(trs5_err_index[2:0]),
  .trs6_err_index(trs6_err_index[2:0]),
  .trs7_err_index(trs7_err_index[2:0]),
  .trs_eccerr_st(trs_eccerr_st[7:0]),
  .trs_eperr_st(trs_eperr_st[7:0])
);


//////////////////////////////////////////////////////////////////////////////
// MBIST datapath
mmu_mbd_dp mbd(
  .asi_mbd_scp_data(asi_mbd_scp_data[31:0]),
  .asi_compare_data(asi_compare_data[7:0]),
  .asi_mbd_sel_scp(asi_mbd_sel_scp),
  .ase_mbd_mbist_data(ase_mbd_mbist_data[31:0]),
  .mbd_compare(mbd_compare));


////////////////////////////////////////////////////////////////////////////////
// Scan patch panel
// fixscan start:
assign asi_scanin                = scan_in                  ;
assign asd0_scanin               = asi_scanout              ;
assign asd1_scanin               = asd0_scanout             ;
assign ase_scanin                = asd1_scanout             ;
assign mel0_scanin               = ase_scanout              ;
assign mra0_scanin               = mel0_scanout             ;
assign mel1_scanin               = mra0_scanout             ;
assign mra1_scanin               = mel1_scanout             ;
assign sel_scanin                = mra1_scanout             ;
assign scp0_scanin               = sel_scanout              ;
assign scp1_scanin               = scp0_scanout             ;
assign htc_scanin                = scp1_scanout             ;
assign htd_scanin                = htc_scanout              ;
assign tmc_scanin                = htd_scanout              ;
assign trc_scanin                = tmc_scanout              ;
assign scan_out                  = trc_scanout              ;

assign asi_wmr_scanin            = wmr_scan_in              ;
assign asd0_wmr_scanin           = asi_wmr_scanout          ;
assign asd1_wmr_scanin           = asd0_wmr_scanout         ;
assign htc_wmr_scanin            = asd1_wmr_scanout         ;
assign wmr_scan_out              = htc_wmr_scanout          ;
// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_asd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_asd_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_scan_en_wmr, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  thread_group, 
  ase_lsu_va_w, 
  ase_lsu_context_w, 
  asi_mra_rd_en_last, 
  asi_rd_immu_tag_target, 
  asi_rd_immu_tag_access, 
  asi_rd_dmmu_tag_target, 
  asi_rd_dmmu_tag_access, 
  asi_rd_i_access_target, 
  asi_rd_d_access_target, 
  asi_rd_access_target, 
  asi_rd_itte_tag, 
  asi_rd_itte_data, 
  asi_rd_dtte, 
  asi_wr_data, 
  asi_wr_immu_tag_access, 
  asi_i_tag_access_en, 
  asi_wr_itlb_data_in, 
  asi_wr_itlb_data_access, 
  asi_wr_immu_demap, 
  asi_wr_immu_demap_p, 
  asi_wr_immu_demap_n, 
  asi_i_data_in_en, 
  asi_wr_dmmu_tag_access, 
  asi_d_tag_access_en, 
  asi_wr_dtlb_data_in, 
  asi_wr_dtlb_data_access, 
  asi_wr_dmmu_demap, 
  asi_wr_dmmu_demap_p, 
  asi_wr_dmmu_demap_s_n, 
  asi_d_data_in_en, 
  asi_dmmu_demap_s, 
  asi_wr_p_context_0, 
  asi_p_context_0_en, 
  asi_data_in_real, 
  asi_tag_access_sel, 
  asi_mra_wr_data, 
  asi_demap_r_bit, 
  asi_mra_rd_addr_bit_1, 
  asi_rd_tsb_ptr_, 
  mra_data, 
  tlu_pc_w, 
  tlu_load_i_tag_access_p, 
  tlu_load_i_tag_access_n, 
  tlu_load_d_tag_access, 
  tlu_load_d_tag_access_r, 
  htd_tagaccess_din, 
  htd_tlbdatain_din, 
  htc_wr_itlb_data_in, 
  htc_wr_dtlb_data_in, 
  mmu_use_context_0, 
  mmu_use_context_1, 
  mmu_sec_context, 
  scan_out, 
  wmr_scan_out, 
  asd_rd_data, 
  asd_asi_rd_data, 
  asd_dtte_tag, 
  asd_dtte_data, 
  asd_itte_tag_data_, 
  asd_itte_index, 
  asd_iht_p_ctx_0_0, 
  asd_iht_p_ctx_0_1, 
  asd_iht_p_ctx_0_2, 
  asd_iht_p_ctx_0_3, 
  asd_tag_access, 
  asd_zero_context, 
  asd_asi_zero_context, 
  asd_mra_rd_addr_bit_1, 
  asd_pc_w);
wire [3:0] htc_wr_itlb_tag_access;
wire [3:0] htc_wr_dtlb_tag_access;
wire [60:48] wr_data_unused;
wire [12:0] mra_wr_data_unused;
wire clk;
wire stop;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire mra_read_1_lat_scanin;
wire mra_read_1_lat_scanout;
wire [81:0] mra_rd_data;
wire mra_read_0_lat_scanin;
wire mra_read_0_lat_scanout;
wire p_context_lat_wmr_scanin;
wire p_context_lat_wmr_scanout;
wire [12:0] p_context_0_3;
wire [12:0] p_context_0_2;
wire [12:0] p_context_0_1;
wire [12:0] p_context_0_0;
wire immu_tag_access_3_lat_wmr_scanin;
wire immu_tag_access_3_lat_wmr_scanout;
wire [47:0] immu_tag_access_3;
wire immu_tag_access_2_lat_wmr_scanin;
wire immu_tag_access_2_lat_wmr_scanout;
wire [47:0] immu_tag_access_2;
wire immu_tag_access_1_lat_wmr_scanin;
wire immu_tag_access_1_lat_wmr_scanout;
wire [47:0] immu_tag_access_1;
wire immu_tag_access_0_lat_wmr_scanin;
wire immu_tag_access_0_lat_wmr_scanout;
wire [47:0] immu_tag_access_0;
wire [61:0] immu_access_target;
wire dmmu_tag_access_3_lat_wmr_scanin;
wire dmmu_tag_access_3_lat_wmr_scanout;
wire [47:0] dmmu_tag_access_3;
wire dmmu_tag_access_2_lat_wmr_scanin;
wire dmmu_tag_access_2_lat_wmr_scanout;
wire [47:0] dmmu_tag_access_2;
wire dmmu_tag_access_1_lat_wmr_scanin;
wire dmmu_tag_access_1_lat_wmr_scanout;
wire [47:0] dmmu_tag_access_1;
wire dmmu_tag_access_0_lat_wmr_scanin;
wire dmmu_tag_access_0_lat_wmr_scanout;
wire [47:0] dmmu_tag_access_0;
wire [61:0] dmmu_access_target;
wire [47:0] tag_access;
wire [2:0] tag_access_sel;
wire zero_context;
wire bit1;
wire asi_rd_mux_scanin;
wire asi_rd_mux_scanout;
wire [48:0] itlb_data_in_0;
wire [48:0] itlb_data_in_1;
wire [48:0] itlb_data_in_2;
wire [48:0] itlb_data_in_3;
wire [50:0] dtlb_data_in_0;
wire [50:0] dtlb_data_in_1;
wire [50:0] dtlb_data_in_2;
wire [50:0] dtlb_data_in_3;
wire itlb_ps_eq_256m_0;
wire itlb_ps_eq_256m_1;
wire itlb_ps_eq_256m_2;
wire itlb_ps_eq_256m_3;
wire dtlb_ps_eq_256m_0;
wire dtlb_ps_eq_256m_1;
wire dtlb_ps_eq_256m_2;
wire dtlb_ps_eq_256m_3;
wire itlb_ps_gt_64k_0;
wire itlb_ps_gt_64k_1;
wire itlb_ps_gt_64k_2;
wire itlb_ps_gt_64k_3;
wire dtlb_ps_gt_64k_0;
wire dtlb_ps_gt_64k_1;
wire dtlb_ps_gt_64k_2;
wire dtlb_ps_gt_64k_3;
wire itlb_ps_gt_8k_0;
wire itlb_ps_gt_8k_1;
wire itlb_ps_gt_8k_2;
wire itlb_ps_gt_8k_3;
wire dtlb_ps_gt_8k_0;
wire dtlb_ps_gt_8k_1;
wire dtlb_ps_gt_8k_2;
wire dtlb_ps_gt_8k_3;
wire [47:0] itte_tag;
wire [47:0] dtte_tag;
wire [38:0] data_in;
wire itlb_data_in_3_lat_scanin;
wire itlb_data_in_3_lat_scanout;
wire itlb_data_in_2_lat_scanin;
wire itlb_data_in_2_lat_scanout;
wire itlb_data_in_1_lat_scanin;
wire itlb_data_in_1_lat_scanout;
wire itlb_data_in_0_lat_scanin;
wire itlb_data_in_0_lat_scanout;
wire dtlb_data_in_3_lat_scanin;
wire dtlb_data_in_3_lat_scanout;
wire dtlb_data_in_2_lat_scanin;
wire dtlb_data_in_2_lat_scanout;
wire dtlb_data_in_1_lat_scanin;
wire dtlb_data_in_1_lat_scanout;
wire dtlb_data_in_0_lat_scanin;
wire dtlb_data_in_0_lat_scanout;
wire [45:0] itte_data;
wire [54:0] dtte_data;


input		l2clk;
input 		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input		tcu_scan_en_wmr;
input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

input 		thread_group;

input	[47:13]	ase_lsu_va_w;
input	[12:0]	ase_lsu_context_w;

input 		asi_mra_rd_en_last;

input	[3:0]	asi_rd_immu_tag_target;
input	[3:0]	asi_rd_immu_tag_access;
input	[3:0]	asi_rd_dmmu_tag_target;
input	[3:0]	asi_rd_dmmu_tag_access;
input		asi_rd_i_access_target;
input		asi_rd_d_access_target;
input		asi_rd_access_target;
input	[3:0]	asi_rd_itte_tag;
input	[3:0]	asi_rd_itte_data;
input	[2:0]	asi_rd_dtte;

input 	[63:0]	asi_wr_data;
input	[3:0]	asi_wr_immu_tag_access;
input	[3:0] asi_i_tag_access_en;
input	[3:0]	asi_wr_itlb_data_in;
input	[3:0]	asi_wr_itlb_data_access;
input	[3:0]	asi_wr_immu_demap;
input	[3:0]	asi_wr_immu_demap_p;
input	[3:0]	asi_wr_immu_demap_n;
input	[3:0] asi_i_data_in_en;
input	[3:0]	asi_wr_dmmu_tag_access;
input	[3:0] asi_d_tag_access_en;
input	[3:0]	asi_wr_dtlb_data_in;
input	[3:0]	asi_wr_dtlb_data_access;
input	[3:0]	asi_wr_dmmu_demap;
input	[3:0]	asi_wr_dmmu_demap_p;
input	[3:0]	asi_wr_dmmu_demap_s_n;
input	[3:0] asi_d_data_in_en;
input		asi_dmmu_demap_s;
input	[3:0]	asi_wr_p_context_0;
input		asi_p_context_0_en;
input 		asi_data_in_real;
input	[2:0]	asi_tag_access_sel;

input	[39:0]	asi_mra_wr_data;
input 		asi_demap_r_bit;

input 		asi_mra_rd_addr_bit_1;
input 		asi_rd_tsb_ptr_;

input 	[81:0]	mra_data;

input	[47:13]	tlu_pc_w;
input 	[3:0]	tlu_load_i_tag_access_p;
input 	[3:0]	tlu_load_i_tag_access_n;
input 	[3:0]	tlu_load_d_tag_access;
input 	[3:0]	tlu_load_d_tag_access_r;

input   [47:0] htd_tagaccess_din;
input   [38:0] htd_tlbdatain_din;
input   [3:0] htc_wr_itlb_data_in;
input   [3:0] htc_wr_dtlb_data_in;

input		mmu_use_context_0;	// HW TW:  Replace TTE ctxt with ctxt 0
input		mmu_use_context_1;	// HW TW:  Replace TTE ctxt with ctxt 1
input		mmu_sec_context;	// HW TW:  Replace TTE ctxt with secon. 

output 		scan_out;

output		wmr_scan_out;		// Warm reset (non)scan

output	[81:0]	asd_rd_data;

output	[63:0]	asd_asi_rd_data;

output	[47:0]	asd_dtte_tag;
output	[54:0]	asd_dtte_data;
output	[47:0]	asd_itte_tag_data_;
output	[6:0]	asd_itte_index;

output	[12:0]	asd_iht_p_ctx_0_0;
output	[12:0]	asd_iht_p_ctx_0_1;
output	[12:0]	asd_iht_p_ctx_0_2;
output	[12:0]	asd_iht_p_ctx_0_3;

output	[47:0]	asd_tag_access;
output		asd_zero_context;
output		asd_asi_zero_context;

output		asd_mra_rd_addr_bit_1;

output	[47:13]	asd_pc_w;	// Needs to feed mmu_htd_dp


//////////////////////////////////////////////////////////////////////////////
assign htc_wr_itlb_tag_access[3:0] =
       htc_wr_itlb_data_in[3:0];

assign htc_wr_dtlb_tag_access[3:0] =
       htc_wr_dtlb_data_in[3:0];

assign wr_data_unused[60:48] =
       asi_wr_data[60:48];

assign mra_wr_data_unused[12:10] =
       asi_mra_wr_data[12:10];

assign mra_wr_data_unused[2:0] =
       asi_mra_wr_data[2:0];


//////////////////////////////////////////////////////////////////////

assign clk	= l2clk;
assign stop	= 1'b0;

mmu_asd_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);


//////////////////////////////////////////////////////////////////////
//
// Capture read data from mra
//

mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_24 mra_read_1_lat    (
	.scan_in(mra_read_1_lat_scanin),
	.scan_out(mra_read_1_lat_scanout),
	.en	(asi_mra_rd_en_last		),
	.din	(mra_data		[81:58]),
	.dout	(mra_rd_data		[81:58]),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_58 mra_read_0_lat    (
	.scan_in(mra_read_0_lat_scanin),
	.scan_out(mra_read_0_lat_scanout),
	.en	(asi_mra_rd_en_last		),
	.din	(mra_data		[57:0]	),
	.dout	(mra_rd_data		[57:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign asd_rd_data[81:0] = 
       mra_rd_data[81:0];


//////////////////////////////////////////////////////////////////////
//
// Individual registers
//

// Shadow copy of p_context_0 for tag_access regs
mmu_asd_dp_msff_macro__mux_aonpe__ports_4__stack_58c__width_52 p_context_lat     (
	.scan_in(p_context_lat_wmr_scanin),
	.scan_out(p_context_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({p_context_0_3		[12:0],
		  p_context_0_2		[12:0],
		  p_context_0_1		[12:0],
		  asi_wr_data		[12:0]}),
	.din1	({p_context_0_3		[12:0],
		  p_context_0_2		[12:0],
		  asi_wr_data		[12:0],
		  p_context_0_0		[12:0]}),	
	.din2	({p_context_0_3		[12:0],
		  asi_wr_data		[12:0],
		  p_context_0_1		[12:0],
		  p_context_0_0		[12:0]}),
	.din3	({asi_wr_data		[12:0],
		  p_context_0_2		[12:0],
		  p_context_0_1		[12:0],
		  p_context_0_0		[12:0]}),
	.sel0	(asi_wr_p_context_0	[0   ]	),
	.sel1	(asi_wr_p_context_0	[1   ]	),
	.sel2	(asi_wr_p_context_0	[2   ]	),
	.sel3	(asi_wr_p_context_0	[3   ]	),
	.en	(asi_p_context_0_en		),
	.dout	({p_context_0_3		[12:0],
		  p_context_0_2		[12:0],
		  p_context_0_1		[12:0],
		  p_context_0_0		[12:0]}),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_buff_macro__left_13__stack_58c__width_35 pc_w_buf    (
	.din	(tlu_pc_w		[47:13]	),
	.dout	(asd_pc_w		[47:13]	)
);

mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_3_lat     (
	.scan_in(immu_tag_access_3_lat_wmr_scanin),
	.scan_out(immu_tag_access_3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({asd_pc_w		[47:13],
		  p_context_0_3		[12:0]}),
	.din1	({asd_pc_w		[47:13],
		  {13 {1'b0}}		       }),
	.din2	(asi_wr_data		[47:0]	),
	.din3	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],   
		  p_context_0_3		[12:0]}),
	.din4	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  {13 {1'b0}}		       }),
	.din5	(htd_tagaccess_din	[47:0]	),
	.din6	(immu_tag_access_3	[47:0]	),
	.sel0	(tlu_load_i_tag_access_p[3   ]	),
	.sel1	(tlu_load_i_tag_access_n[3   ]	),
	.sel2	(asi_wr_immu_tag_access	[3   ]	),
	.sel3	(asi_wr_immu_demap_p	[3   ]	),
	.sel4	(asi_wr_immu_demap_n	[3   ]	),
	.sel5	(htc_wr_itlb_tag_access	[3   ]	), // HWTW Write ITLB Tag Access
	.en	(asi_i_tag_access_en	[3   ]	),
	.dout	(immu_tag_access_3	[47:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_2_lat     (
	.scan_in(immu_tag_access_2_lat_wmr_scanin),
	.scan_out(immu_tag_access_2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({asd_pc_w		[47:13],
		  p_context_0_2		[12:0]}),
	.din1	({asd_pc_w		[47:13],
		  {13 {1'b0}}		       }),
	.din2	(asi_wr_data		[47:0]	),
	.din3	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  p_context_0_2		[12:0]}),
	.din4	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  {13 {1'b0}}		       }),
	.din5	(htd_tagaccess_din	[47:0]	),
	.din6	(immu_tag_access_2	[47:0]	),
	.sel0	(tlu_load_i_tag_access_p[2   ]	),
	.sel1	(tlu_load_i_tag_access_n[2   ]	),
	.sel2	(asi_wr_immu_tag_access	[2   ]	),
	.sel3	(asi_wr_immu_demap_p	[2   ]	),
	.sel4	(asi_wr_immu_demap_n	[2   ]	),
	.sel5	(htc_wr_itlb_tag_access	[2   ]	), // HWTW Write ITLB Tag Access
	.en	(asi_i_tag_access_en	[2   ]	),
	.dout	(immu_tag_access_2	[47:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_1_lat     (
	.scan_in(immu_tag_access_1_lat_wmr_scanin),
	.scan_out(immu_tag_access_1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({asd_pc_w		[47:13],
		  p_context_0_1		[12:0]}),
	.din1	({asd_pc_w		[47:13],
		  {13 {1'b0}}		       }),
	.din2	(asi_wr_data		[47:0]	),
	.din3	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  p_context_0_1		[12:0]}),
	.din4	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  {13 {1'b0}}		       }),
	.din5	(htd_tagaccess_din	[47:0]	),
	.din6	(immu_tag_access_1	[47:0]	),
	.sel0	(tlu_load_i_tag_access_p[1   ]	),
	.sel1	(tlu_load_i_tag_access_n[1   ]	),
	.sel2	(asi_wr_immu_tag_access	[1   ]	),
	.sel3	(asi_wr_immu_demap_p	[1   ]	),
	.sel4	(asi_wr_immu_demap_n	[1   ]	),
	.sel5	(htc_wr_itlb_tag_access	[1   ]	), // HWTW Write ITLB Tag Access
	.en	(asi_i_tag_access_en	[1   ]	),
	.dout	(immu_tag_access_1	[47:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 immu_tag_access_0_lat     ( 
	.scan_in(immu_tag_access_0_lat_wmr_scanin),
	.scan_out(immu_tag_access_0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({asd_pc_w		[47:13],
		  p_context_0_0		[12:0]}),
	.din1	({asd_pc_w		[47:13],
		  {13 {1'b0}}		       }),
	.din2	(asi_wr_data		[47:0]	),
	.din3	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  p_context_0_0		[12:0]}),
	.din4	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  {13 {1'b0}}		       }),
	.din5	(htd_tagaccess_din	[47:0]	),
	.din6	(immu_tag_access_0	[47:0]	),
	.sel0	(tlu_load_i_tag_access_p[0   ]	),
	.sel1	(tlu_load_i_tag_access_n[0   ]	),
	.sel2	(asi_wr_immu_tag_access	[0   ]	),
	.sel3	(asi_wr_immu_demap_p	[0   ]	),
	.sel4	(asi_wr_immu_demap_n	[0   ]	),
	.sel5	(htc_wr_itlb_tag_access	[0   ]	), // HWTW Write ITLB Tag Access
	.en	(asi_i_tag_access_en	[0   ]	),
	.dout	(immu_tag_access_0	[47:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 immu_access_target_mux    (
	.din0	({{14 {immu_tag_access_0[47 ]}},
		  immu_tag_access_0	[47:0]}),
	.din1	({{14 {immu_tag_access_1[47 ]}},
		  immu_tag_access_1	[47:0]}),
	.din2	({{14 {immu_tag_access_2[47 ]}},
		  immu_tag_access_2	[47:0]}),
	.din3	({{14 {immu_tag_access_3[47 ]}},
		  immu_tag_access_3	[47:0]}),
	.din4	({1'b0			       ,
		  immu_tag_access_0	[12:0],
		  {6 {1'b0}}		       ,
		  {16 {immu_tag_access_0[47 ]}},
		  immu_tag_access_0	[47:22]}),  // tag target
	.din5	({1'b0			       ,
		  immu_tag_access_1	[12:0],
		  {6 {1'b0}}		       ,
		  {16 {immu_tag_access_1[47 ]}},
		  immu_tag_access_1	[47:22]}),  // tag target
	.din6	({1'b0			       ,
		  immu_tag_access_2	[12:0],
		  {6 {1'b0}}		       ,
		  {16 {immu_tag_access_2[47 ]}},
		  immu_tag_access_2	[47:22]}),  // tag target
	.din7	({1'b0			       ,
		  immu_tag_access_3	[12:0],
		  {6 {1'b0}}		       ,
		  {16 {immu_tag_access_3[47 ]}},
		  immu_tag_access_3	[47:22]}),  // tag target
	.sel0	(asi_rd_immu_tag_access	[0   ]	),
	.sel1	(asi_rd_immu_tag_access	[1   ]	),
	.sel2	(asi_rd_immu_tag_access	[2   ]	),
	.sel3	(asi_rd_immu_tag_access	[3   ]	),
	.sel4	(asi_rd_immu_tag_target	[0   ]	),
	.sel5	(asi_rd_immu_tag_target	[1   ]	),
	.sel6	(asi_rd_immu_tag_target	[2   ]	),
	.sel7	(asi_rd_immu_tag_target	[3   ]	),
	.dout	(immu_access_target	[61:0]	)
);

mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_3_lat     ( 
	.scan_in(dmmu_tag_access_3_lat_wmr_scanin),
	.scan_out(dmmu_tag_access_3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ase_lsu_va_w		[47:13],
		  ase_lsu_context_w	[12:0]}),
	.din1	({ase_lsu_va_w		[47:13],
		  {13 {1'b0}}		       }),
	.din2	(asi_wr_data		[47:0]	),
	.din3	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  p_context_0_3		[12:0]}),
	.din4	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  {13 {1'b0}}		       }),
	.din5	(htd_tagaccess_din	[47:0]	),
	.din6	(dmmu_tag_access_3	[47:0]	),
	.sel0	(tlu_load_d_tag_access	[3   ]	),
	.sel1	(tlu_load_d_tag_access_r[3   ]	),
	.sel2	(asi_wr_dmmu_tag_access	[3   ]	),
	.sel3	(asi_wr_dmmu_demap_p	[3   ]	),
	.sel4	(asi_wr_dmmu_demap_s_n	[3   ]	),
	.sel5	(htc_wr_dtlb_tag_access	[3   ]	), //HWTW Write DTLB Tag Access
	.en	(asi_d_tag_access_en	[3   ]	),
	.dout	(dmmu_tag_access_3	[47:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_2_lat     ( 
	.scan_in(dmmu_tag_access_2_lat_wmr_scanin),
	.scan_out(dmmu_tag_access_2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ase_lsu_va_w		[47:13],
		  ase_lsu_context_w	[12:0]}),
	.din1	({ase_lsu_va_w		[47:13],
		  {13 {1'b0}}		       }),
	.din2	(asi_wr_data		[47:0]	),
	.din3	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  p_context_0_2		[12:0]}),
	.din4	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  {13 {1'b0}}		       }),
	.din5	(htd_tagaccess_din	[47:0]	),
	.din6	(dmmu_tag_access_2	[47:0]	),
	.sel0	(tlu_load_d_tag_access	[2   ]	),
	.sel1	(tlu_load_d_tag_access_r[2   ]	),
	.sel2	(asi_wr_dmmu_tag_access	[2   ]	),
	.sel3	(asi_wr_dmmu_demap_p	[2   ]	),
	.sel4	(asi_wr_dmmu_demap_s_n	[2   ]	),
	.sel5	(htc_wr_dtlb_tag_access	[2   ]	), //HWTW Write DTLB Tag Access
	.en	(asi_d_tag_access_en	[2   ]	),
	.dout	(dmmu_tag_access_2	[47:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_1_lat     ( 
	.scan_in(dmmu_tag_access_1_lat_wmr_scanin),
	.scan_out(dmmu_tag_access_1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ase_lsu_va_w		[47:13],
		  ase_lsu_context_w	[12:0]}),
	.din1	({ase_lsu_va_w		[47:13],
		  {13 {1'b0}}		       }),
	.din2	(asi_wr_data		[47:0]	),
	.din3	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  p_context_0_1		[12:0]}),
	.din4	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  {13 {1'b0}}		       }),
	.din5	(htd_tagaccess_din	[47:0]	),
	.din6	(dmmu_tag_access_1	[47:0]	),
	.sel0	(tlu_load_d_tag_access	[1   ]	),
	.sel1	(tlu_load_d_tag_access_r[1   ]	),
	.sel2	(asi_wr_dmmu_tag_access	[1   ]	),
	.sel3	(asi_wr_dmmu_demap_p	[1   ]	),
	.sel4	(asi_wr_dmmu_demap_s_n	[1   ]	),
	.sel5	(htc_wr_dtlb_tag_access	[1   ]	), //HWTW Write DTLB Tag Access
	.en	(asi_d_tag_access_en	[1   ]	),
	.dout	(dmmu_tag_access_1	[47:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 dmmu_tag_access_0_lat     ( 
	.scan_in(dmmu_tag_access_0_lat_wmr_scanin),
	.scan_out(dmmu_tag_access_0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ase_lsu_va_w		[47:13],
		  ase_lsu_context_w	[12:0]}),
	.din1	({ase_lsu_va_w		[47:13],
		  {13 {1'b0}}		       }),
	.din2	(asi_wr_data		[47:0]	),
	.din3	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  p_context_0_0		[12:0]}),
	.din4	({asi_wr_data		[47:40],   // Demap VA[47:40] in data
		  asi_mra_wr_data	[39:13],
		  {13 {1'b0}}		       }),
	.din5	(htd_tagaccess_din	[47:0]	),
	.din6	(dmmu_tag_access_0	[47:0]	),
	.sel0	(tlu_load_d_tag_access	[0   ]	),
	.sel1	(tlu_load_d_tag_access_r[0   ]	),
	.sel2	(asi_wr_dmmu_tag_access	[0   ]	),
	.sel3	(asi_wr_dmmu_demap_p	[0   ]	),
	.sel4	(asi_wr_dmmu_demap_s_n	[0   ]	),
	.sel5	(htc_wr_dtlb_tag_access	[0   ]	), //HWTW Write DTLB Tag Access
	.en	(asi_d_tag_access_en	[0   ]	),
	.dout	(dmmu_tag_access_0	[47:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 dmmu_access_target_mux    (
	.din0	({{14 {dmmu_tag_access_0[47 ]}},
		  dmmu_tag_access_0	[47:0]}),
	.din1	({{14 {dmmu_tag_access_1[47 ]}},
		  dmmu_tag_access_1	[47:0]}),
	.din2	({{14 {dmmu_tag_access_2[47 ]}},
		  dmmu_tag_access_2	[47:0]}),
	.din3	({{14 {dmmu_tag_access_3[47 ]}},
		  dmmu_tag_access_3	[47:0]}),
	.din4	({1'b0			       ,
		  dmmu_tag_access_0	[12:0],
		  {6 {1'b0}}		       ,
		  {16 {dmmu_tag_access_0[47 ]}},
		  dmmu_tag_access_0	[47:22]}),  // tag target
	.din5	({1'b0			       ,
		  dmmu_tag_access_1	[12:0],
		  {6 {1'b0}}		       ,
		  {16 {dmmu_tag_access_1[47 ]}},
		  dmmu_tag_access_1	[47:22]}),  // tag target
	.din6	({1'b0			       ,
		  dmmu_tag_access_2	[12:0],
		  {6 {1'b0}}		       ,
		  {16 {dmmu_tag_access_2[47 ]}},
		  dmmu_tag_access_2	[47:22]}),  // tag target
	.din7	({1'b0			       ,
		  dmmu_tag_access_3	[12:0],
		  {6 {1'b0}}		       ,
		  {16 {dmmu_tag_access_3[47 ]}},
		  dmmu_tag_access_3	[47:22]}),  // tag target
	.sel0	(asi_rd_dmmu_tag_access	[0   ]	),
	.sel1	(asi_rd_dmmu_tag_access	[1   ]	),
	.sel2	(asi_rd_dmmu_tag_access	[2   ]	),
	.sel3	(asi_rd_dmmu_tag_access	[3   ]	),
	.sel4	(asi_rd_dmmu_tag_target	[0   ]	),
	.sel5	(asi_rd_dmmu_tag_target	[1   ]	),
	.sel6	(asi_rd_dmmu_tag_target	[2   ]	),
	.sel7	(asi_rd_dmmu_tag_target	[3   ]	),
	.dout	(dmmu_access_target	[61:0]	)
);

mmu_asd_dp_mux_macro__mux_aodec__ports_8__stack_58c__width_13 tag_access_crit_mux     (
	.din0	(immu_tag_access_0	[12:0]	),
	.din1	(immu_tag_access_1	[12:0]	),
	.din2	(immu_tag_access_2	[12:0]	),
	.din3	(immu_tag_access_3	[12:0]	),
	.din4	(dmmu_tag_access_0	[12:0]	),
	.din5	(dmmu_tag_access_1	[12:0]	),
	.din6	(dmmu_tag_access_2	[12:0]	),
	.din7	(dmmu_tag_access_3	[12:0]	),
	.sel	(asi_tag_access_sel	[2:0]	),
	.dout	(tag_access		[12:0]	)
);

mmu_asd_dp_buff_macro__stack_58c__width_3 tag_access_sel_buf   (
	.din	(asi_tag_access_sel	[2:0]	),
	.dout	(tag_access_sel		[2:0]	)
);
mmu_asd_dp_mux_macro__left_13__mux_aodec__ports_8__stack_58c__width_35 tag_access_mux      (
	.din0	(immu_tag_access_0	[47:13]	),
	.din1	(immu_tag_access_1	[47:13]	),
	.din2	(immu_tag_access_2	[47:13]	),
	.din3	(immu_tag_access_3	[47:13]	),
	.din4	(dmmu_tag_access_0	[47:13]	),
	.din5	(dmmu_tag_access_1	[47:13]	),
	.din6	(dmmu_tag_access_2	[47:13]	),
	.din7	(dmmu_tag_access_3	[47:13]	),
	.sel	(tag_access_sel		[2:0]	),
	.dout	(tag_access		[47:13]	)
);

mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 tag_access_buf    (
	.din	(tag_access		[47:0]	),
	.dout	(asd_tag_access		[47:0]	)
);

mmu_asd_dp_zero_macro__width_16 zero_context_cmp  (
	.din	({{3 {1'b0}},
		  tag_access		[12:0]}),
	.dout	(zero_context			)
);

mmu_asd_dp_nor_macro__ports_2__width_1 bit1_nor   (
	.din0	(zero_context			),
	.din1	(asi_rd_tsb_ptr_		),
	.dout	(bit1				)
);

mmu_asd_dp_or_macro__ports_2__width_1 bit1_or   (
	.din0	(bit1				),
	.din1	(asi_mra_rd_addr_bit_1		),
	.dout	(asd_mra_rd_addr_bit_1		)
);

mmu_asd_dp_buff_macro__rep_1__width_2 zero_context_buf   (
	.din	({2 {zero_context	      }}),
	.dout	({asd_zero_context	       ,
		  asd_asi_zero_context	       })
);

mmu_asd_dp_msff_macro__mux_aonpe__ports_2__width_62 asi_rd_mux    (
	.scan_in(asi_rd_mux_scanin),
	.scan_out(asi_rd_mux_scanout),
	.din0	(immu_access_target	[61:0]	),
	.din1	(dmmu_access_target	[61:0]	),
	.sel0	(asi_rd_i_access_target		),
	.sel1	(asi_rd_d_access_target		),
	.en	(asi_rd_access_target		),
	.dout	(asd_asi_rd_data	[61:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign asd_asi_rd_data[63:62] =
       {2 {asd_asi_rd_data[61]}};

mmu_asd_dp_and_macro__ports_2__stack_58c__width_8 ps_eq_256m_and    (
	.din0	({itlb_data_in_0	[2   ],
		  itlb_data_in_1	[2   ],
		  itlb_data_in_2	[2   ],
		  itlb_data_in_3	[2   ],
		  dtlb_data_in_0	[2   ],
		  dtlb_data_in_1	[2   ],
		  dtlb_data_in_2	[2   ],
		  dtlb_data_in_3	[2   ]}),
	.din1	({itlb_data_in_0	[0   ],
		  itlb_data_in_1	[0   ],
		  itlb_data_in_2	[0   ],
		  itlb_data_in_3	[0   ],
		  dtlb_data_in_0	[0   ],
		  dtlb_data_in_1	[0   ],
		  dtlb_data_in_2	[0   ],
		  dtlb_data_in_3	[0   ]}),
	.dout	({itlb_ps_eq_256m_0	       ,
		  itlb_ps_eq_256m_1	       ,
		  itlb_ps_eq_256m_2	       ,
		  itlb_ps_eq_256m_3	       ,
		  dtlb_ps_eq_256m_0	       ,
		  dtlb_ps_eq_256m_1	       ,
		  dtlb_ps_eq_256m_2	       ,
		  dtlb_ps_eq_256m_3	       })
);

mmu_asd_dp_or_macro__ports_2__stack_58c__width_8 ps_gt_64k_or    (
	.din0	({itlb_data_in_0	[2   ],
		  itlb_data_in_1	[2   ],
		  itlb_data_in_2	[2   ],
		  itlb_data_in_3	[2   ],
		  dtlb_data_in_0	[2   ],
		  dtlb_data_in_1	[2   ],
		  dtlb_data_in_2	[2   ],
		  dtlb_data_in_3	[2   ]}),
	.din1	({itlb_data_in_0	[1   ],
		  itlb_data_in_1	[1   ],
		  itlb_data_in_2	[1   ],
		  itlb_data_in_3	[1   ],
		  dtlb_data_in_0	[1   ],
		  dtlb_data_in_1	[1   ],
		  dtlb_data_in_2	[1   ],
		  dtlb_data_in_3	[1   ]}),
	.dout	({itlb_ps_gt_64k_0	       ,
		  itlb_ps_gt_64k_1	       ,
		  itlb_ps_gt_64k_2	       ,
		  itlb_ps_gt_64k_3	       ,
		  dtlb_ps_gt_64k_0	       ,
		  dtlb_ps_gt_64k_1	       ,
		  dtlb_ps_gt_64k_2	       ,
		  dtlb_ps_gt_64k_3	       })
);

mmu_asd_dp_or_macro__ports_3__stack_58c__width_8 ps_gt_8k_or    (
	.din0	({itlb_data_in_0	[2   ],
		  itlb_data_in_1	[2   ],
		  itlb_data_in_2	[2   ],
		  itlb_data_in_3	[2   ],
		  dtlb_data_in_0	[2   ],
		  dtlb_data_in_1	[2   ],
		  dtlb_data_in_2	[2   ],
		  dtlb_data_in_3	[2   ]}),
	.din1	({itlb_data_in_0	[1   ],
		  itlb_data_in_1	[1   ],
		  itlb_data_in_2	[1   ],
		  itlb_data_in_3	[1   ],
		  dtlb_data_in_0	[1   ],
		  dtlb_data_in_1	[1   ],
		  dtlb_data_in_2	[1   ],
		  dtlb_data_in_3	[1   ]}),
	.din2	({itlb_data_in_0	[0   ],
		  itlb_data_in_1	[0   ],
		  itlb_data_in_2	[0   ],
		  itlb_data_in_3	[0   ],
		  dtlb_data_in_0	[0   ],
		  dtlb_data_in_1	[0   ],
		  dtlb_data_in_2	[0   ],
		  dtlb_data_in_3	[0   ]}),
	.dout	({itlb_ps_gt_8k_0	       ,
		  itlb_ps_gt_8k_1	       ,
		  itlb_ps_gt_8k_2	       ,
		  itlb_ps_gt_8k_3	       ,
		  dtlb_ps_gt_8k_0	       ,
		  dtlb_ps_gt_8k_1	       ,
		  dtlb_ps_gt_8k_2	       ,
		  dtlb_ps_gt_8k_3	       })
);


mmu_asd_dp_mux_macro__mux_aonpe__ports_4__stack_58c__width_48 itte_tag_mux     (
	.din0	({immu_tag_access_0	[47:28],	// VA[47:28]
		  immu_tag_access_0	[27:22],	// VA[27:22]
		  itlb_ps_eq_256m_0	       ,
		  itlb_data_in_0	[38   ],	// Valid
		  itlb_data_in_0	[35   ],	// Locked
		  immu_tag_access_0	[21:16],	// VA[21:16]
		  immu_tag_access_0	[12:0]}),	// Context
	.din1	({immu_tag_access_1	[47:28],	// VA[47:28]
		  immu_tag_access_1	[27:22],	// VA[27:22]
		  itlb_ps_eq_256m_1	       ,
		  itlb_data_in_1	[38   ],	// Valid
		  itlb_data_in_1	[35   ],	// Locked
		  immu_tag_access_1	[21:16],	// VA[21:16]
		  immu_tag_access_1	[12:0]}),	// Context
	.din2	({immu_tag_access_2	[47:28],	// VA[47:28]
		  immu_tag_access_2	[27:22],	// VA[27:22]
		  itlb_ps_eq_256m_2	       ,
		  itlb_data_in_2	[38   ],	// Valid
		  itlb_data_in_2	[35   ],	// Locked
		  immu_tag_access_2	[21:16],	// VA[21:16]
		  immu_tag_access_2	[12:0]}),	// Context
	.din3	({immu_tag_access_3	[47:28],	// VA[47:28]
		  immu_tag_access_3	[27:22],	// VA[27:22]
		  itlb_ps_eq_256m_3	       ,
		  itlb_data_in_3	[38   ],	// Valid
		  itlb_data_in_3	[35   ],	// Locked
		  immu_tag_access_3	[21:16],	// VA[21:16]
		  immu_tag_access_3	[12:0]}),	// Context
	.sel0	(asi_rd_itte_tag	[0   ]	),
	.sel1	(asi_rd_itte_tag	[1   ]	),
	.sel2	(asi_rd_itte_tag	[2   ]	),
	.sel3	(asi_rd_itte_tag	[3   ]	),
	.dout	(itte_tag		[47:0]	)
);

mmu_asd_dp_mux_macro__dmux_8x__mux_aope__ports_4__stack_58c__width_48 dtte_tag_mux      (
	.din0	({dmmu_tag_access_0	[47:28],	// VA[47:28]
		  dmmu_tag_access_0	[27:22],	// VA[27:22]
		  dtlb_ps_eq_256m_0	       ,
		  dtlb_data_in_0	[38   ],	// Valid
		  dtlb_data_in_0	[35   ],	// Locked
		  dmmu_tag_access_0	[21:16],	// VA[21:16]
		  dmmu_tag_access_0	[12:0]}),	// Context
	.din1	({dmmu_tag_access_1	[47:28],	// VA[47:28]
		  dmmu_tag_access_1	[27:22],	// VA[27:22]
		  dtlb_ps_eq_256m_1	       ,
		  dtlb_data_in_1	[38   ],	// Valid
		  dtlb_data_in_1	[35   ],	// Locked
		  dmmu_tag_access_1	[21:16],	// VA[21:16]
		  dmmu_tag_access_1	[12:0]}),	// Context
	.din2	({dmmu_tag_access_2	[47:28],	// VA[47:28]
		  dmmu_tag_access_2	[27:22],	// VA[27:22]
		  dtlb_ps_eq_256m_2	       ,
		  dtlb_data_in_2	[38   ],	// Valid
		  dtlb_data_in_2	[35   ],	// Locked
		  dmmu_tag_access_2	[21:16],	// VA[21:16]
		  dmmu_tag_access_2	[12:0]}),	// Context
	.din3	({dmmu_tag_access_3	[47:28],	// VA[47:28]
		  dmmu_tag_access_3	[27:22],	// VA[27:22]
		  dtlb_ps_eq_256m_3	       ,
		  dtlb_data_in_3	[38   ],	// Valid
		  dtlb_data_in_3	[35   ],	// Locked
		  dmmu_tag_access_3	[21:16],	// VA[21:16]
		  dmmu_tag_access_3	[12:0]}),	// Context
	.sel0	(asi_rd_dtte		[0   ]	),
	.sel1	(asi_rd_dtte		[1   ]	),
	.sel2	(asi_rd_dtte		[2   ]	),
	.dout	(dtte_tag		[47:0]	)
);

mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 dtte_tag_buf    (
	.din	(dtte_tag		[47:0]	),
	.dout	(asd_dtte_tag		[47:0]	)
);


assign data_in[38:0] = 
	{asi_wr_data		[63   ],	// V
	 asi_wr_data		[62   ],	// NFO
	 asi_data_in_real	       ,	// Real
	 asi_wr_data		[61   ],	// Locked
	 asi_wr_data		[39:13],	// PA[39:13]
	 asi_wr_data		[12   ],	// IE
	 asi_wr_data		[11   ],	// Side effect
	 asi_wr_data		[10   ],	// CP
	 asi_wr_data		[8   ],	// P
	 asi_wr_data		[6   ],	// W
	 asi_wr_data		[2:0]};	// Size

mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_3_lat     (
	.scan_in(itlb_data_in_3_lat_scanin),
	.scan_out(itlb_data_in_3_lat_scanout),
	.din0	({{7 {1'b0}}		       ,   // Index valid & index
		  {3 {1'b0}}		       ,   // Demap valid & type
		  data_in		[38:0]}),
	.din1	({1'b1			       ,   // Index valid
		  asi_mra_wr_data	[8:3],   // Index to write
		  {3 {1'b0}}		       ,   // Demap valid & type
		  data_in		[38:0]}),
	.din2	({{7 {1'b0}}		       ,   // Index valid & index
		  1'b1			       ,   // Demap
		  asi_mra_wr_data	[7:6],   // Demap type field
		  itlb_data_in_3	[38:37],
		  asi_demap_r_bit	       ,   // Demap R bit
		  itlb_data_in_3	[35:0]}),    
	.din3	({{7 {1'b0}}		       ,   // Index valid & index
		  1'b0			       ,   // Demap valid
		  mmu_use_context_1	       ,   // Context type
		  mmu_use_context_0	       ,   // Context type
		  htd_tlbdatain_din	[38:0]}),    
	.din4	(itlb_data_in_3		[48:0]	),     
	.sel0	(asi_wr_itlb_data_in	[3   ]	), // ASI Write
	.sel1	(asi_wr_itlb_data_access[3   ]	), // ASI Write
	.sel2	(asi_wr_immu_demap	[3   ]	), 
	.sel3	(htc_wr_itlb_data_in	[3   ]	), // HWTW Write ITLB Data-In
	.en	(asi_i_data_in_en	[3   ]	),
	.dout	(itlb_data_in_3		[48:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_2_lat     (
	.scan_in(itlb_data_in_2_lat_scanin),
	.scan_out(itlb_data_in_2_lat_scanout),
	.din0	({{7 {1'b0}}		       ,   // Index valid & index
		  {3 {1'b0}}		       ,   // Demap valid & type
		  data_in		[38:0]}),
	.din1	({1'b1			       ,   // Index valid
		  asi_mra_wr_data	[8:3],   // Index to write
		  {3 {1'b0}}		       ,   // Demap valid & type
		  data_in		[38:0]}),
	.din2	({{7 {1'b0}}		       ,   // Index valid & index
		  1'b1			       ,   // Demap
		  asi_mra_wr_data	[7:6],   // Demap type field
		  itlb_data_in_2	[38:37],
		  asi_demap_r_bit	       ,   // Demap R bit
		  itlb_data_in_2	[35:0]}),    
	.din3	({{7 {1'b0}}		       ,   // Index valid & index
		  1'b0			       ,   // Demap valid
		  mmu_use_context_1	       ,   // Context type
		  mmu_use_context_0	       ,   // Context type
		  htd_tlbdatain_din	[38:0]}),    
	.din4	(itlb_data_in_2		[48:0]	),     
	.sel0	(asi_wr_itlb_data_in	[2   ]	), // ASI Write
	.sel1	(asi_wr_itlb_data_access[2   ]	), // ASI Write
	.sel2	(asi_wr_immu_demap	[2   ]	), 
	.sel3	(htc_wr_itlb_data_in	[2   ]	), // HWTW Write ITLB Data-In
	.en	(asi_i_data_in_en	[2   ]	),
	.dout	(itlb_data_in_2		[48:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_1_lat     (
	.scan_in(itlb_data_in_1_lat_scanin),
	.scan_out(itlb_data_in_1_lat_scanout),
	.din0	({{7 {1'b0}}		       ,   // Index valid & index
		  {3 {1'b0}}		       ,   // Demap valid & type
		  data_in		[38:0]}),
	.din1	({1'b1			       ,   // Index valid
		  asi_mra_wr_data	[8:3],   // Index to write
		  {3 {1'b0}}		       ,   // Demap valid & type
		  data_in		[38:0]}),
	.din2	({{7 {1'b0}}		       ,   // Index valid & index
		  1'b1			       ,   // Demap
		  asi_mra_wr_data	[7:6],   // Demap type field
		  itlb_data_in_1	[38:37],
		  asi_demap_r_bit	       ,   // Demap R bit
		  itlb_data_in_1	[35:0]}),    
	.din3	({{7 {1'b0}}		       ,   // Index valid & index
		  1'b0			       ,   // Demap valid
		  mmu_use_context_1	       ,   // Context type
		  mmu_use_context_0	       ,   // Context type
		  htd_tlbdatain_din	[38:0]}),    
	.din4	(itlb_data_in_1		[48:0]	),     
	.sel0	(asi_wr_itlb_data_in	[1   ]	), // ASI Write
	.sel1	(asi_wr_itlb_data_access[1   ]	), // ASI Write
	.sel2	(asi_wr_immu_demap	[1   ]	), 
	.sel3	(htc_wr_itlb_data_in	[1   ]	), // HWTW Write ITLB Data-In
	.en	(asi_i_data_in_en	[1   ]	),
	.dout	(itlb_data_in_1		[48:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 itlb_data_in_0_lat     (
	.scan_in(itlb_data_in_0_lat_scanin),
	.scan_out(itlb_data_in_0_lat_scanout),
	.din0	({{7 {1'b0}}		       ,   // Index valid & index
		  {3 {1'b0}}		       ,   // Demap valid & type
		  data_in		[38:0]}),
	.din1	({1'b1			       ,   // Index valid
		  asi_mra_wr_data	[8:3],   // Index to write
		  {3 {1'b0}}		       ,   // Demap valid & type
		  data_in		[38:0]}),
	.din2	({{7 {1'b0}}		       ,   // Index valid & index
		  1'b1			       ,   // Demap
		  asi_mra_wr_data	[7:6],   // Demap type field
		  itlb_data_in_0	[38:37],
		  asi_demap_r_bit	       ,   // Demap R bit
		  itlb_data_in_0	[35:0]}),    
	.din3	({{7 {1'b0}}		       ,   // Index valid & index
		  1'b0			       ,   // Demap valid
		  mmu_use_context_1	       ,   // Context type
		  mmu_use_context_0	       ,   // Context type
		  htd_tlbdatain_din	[38:0]}),    
	.din4	(itlb_data_in_0		[48:0]	),     
	.sel0	(asi_wr_itlb_data_in	[0   ]	), // ASI Write
	.sel1	(asi_wr_itlb_data_access[0   ]	), // ASI Write
	.sel2	(asi_wr_immu_demap	[0   ]	), 
	.sel3	(htc_wr_itlb_data_in	[0   ]	), // HWTW Write ITLB Data-In
	.en	(asi_i_data_in_en	[0   ]	),
	.dout	(itlb_data_in_0		[48:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_3_lat     (
	.scan_in(dtlb_data_in_3_lat_scanin),
	.scan_out(dtlb_data_in_3_lat_scanout),
	.din0	({{8 {1'b0}}		       ,   // Index valid & index
		  {4 {1'b0}}		       ,   // Demap valids & type
		  data_in		[38:0]}),   
	.din1	({1'b1			       ,   // Index valid
		  asi_mra_wr_data	[9:3],   // Index to write
		  {4 {1'b0}}		       ,   // Demap valids & type
		  data_in		[38:0]}),   
	.din2	({{8 {1'b0}}		       ,   // Index valid & index
		  asi_dmmu_demap_s	       ,   // Demap secondary context
		  1'b1			       ,   // Demap
		  asi_mra_wr_data	[7:6],   // Demap type field
		  dtlb_data_in_3	[38:37],
		  asi_demap_r_bit	       ,   // Demap R bit
		  dtlb_data_in_3	[35:0]}),    
	.din3	({{8 {1'b0}}		       ,   // Index valid & index
		  mmu_sec_context	       ,   // Replace with secondary cxt
		  1'b0			       ,   // Demap valid
		  mmu_use_context_1	       ,   // Context type
		  mmu_use_context_0	       ,   // Context type
		  htd_tlbdatain_din	[38:0]}),    
	.din4	(dtlb_data_in_3		[50:0]	),     
	.sel0	(asi_wr_dtlb_data_in	[3   ]	), // ASI Write
	.sel1	(asi_wr_dtlb_data_access[3   ]	), // ASI Write
	.sel2	(asi_wr_dmmu_demap	[3   ]	), 
	.sel3	(htc_wr_dtlb_data_in	[3   ]	), // HWTW Write DTLB Data-In
	.en	(asi_d_data_in_en	[3   ]	),
	.dout	(dtlb_data_in_3		[50:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_2_lat     (
	.scan_in(dtlb_data_in_2_lat_scanin),
	.scan_out(dtlb_data_in_2_lat_scanout),
	.din0	({{8 {1'b0}}		       ,   // Index valid & index
		  {4 {1'b0}}		       ,   // Demap valids & type
		  data_in		[38:0]}),   
	.din1	({1'b1			       ,   // Index valid
		  asi_mra_wr_data	[9:3],   // Index to write
		  {4 {1'b0}}		       ,   // Demap valids & type
		  data_in		[38:0]}),   
	.din2	({{8 {1'b0}}		       ,   // Index valid & index
		  asi_dmmu_demap_s	       ,   // Demap secondary context
		  1'b1			       ,   // Demap
		  asi_mra_wr_data	[7:6],   // Demap type field
		  dtlb_data_in_2	[38:37],
		  asi_demap_r_bit	       ,   // Demap R bit
		  dtlb_data_in_2	[35:0]}),    
	.din3	({{8 {1'b0}}		       ,   // Index valid & index
		  mmu_sec_context	       ,   // Replace with secondary cxt
		  1'b0			       ,   // Demap valid
		  mmu_use_context_1	       ,   // Context type
		  mmu_use_context_0	       ,   // Context type
		  htd_tlbdatain_din	[38:0]}),    
	.din4	(dtlb_data_in_2		[50:0]	),     
	.sel0	(asi_wr_dtlb_data_in	[2   ]	), // ASI Write
	.sel1	(asi_wr_dtlb_data_access[2   ]	), // ASI Write
	.sel2	(asi_wr_dmmu_demap	[2   ]	), 
	.sel3	(htc_wr_dtlb_data_in	[2   ]	), // HWTW Write DTLB Data-In
	.en	(asi_d_data_in_en	[2   ]	),
	.dout	(dtlb_data_in_2		[50:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_1_lat     (
	.scan_in(dtlb_data_in_1_lat_scanin),
	.scan_out(dtlb_data_in_1_lat_scanout),
	.din0	({{8 {1'b0}}		       ,   // Index valid & index
		  {4 {1'b0}}		       ,   // Demap valids & type
		  data_in		[38:0]}),   
	.din1	({1'b1			       ,   // Index valid
		  asi_mra_wr_data	[9:3],   // Index to write
		  {4 {1'b0}}		       ,   // Demap valids & type
		  data_in		[38:0]}),   
	.din2	({{8 {1'b0}}		       ,   // Index valid & index
		  asi_dmmu_demap_s	       ,   // Demap secondary context
		  1'b1			       ,   // Demap
		  asi_mra_wr_data	[7:6],   // Demap type field
		  dtlb_data_in_1	[38:37],
		  asi_demap_r_bit	       ,   // Demap R bit
		  dtlb_data_in_1	[35:0]}),    
	.din3	({{8 {1'b0}}		       ,   // Index valid & index
		  mmu_sec_context	       ,   // Replace with secondary cxt
		  1'b0			       ,   // Demap valid
		  mmu_use_context_1	       ,   // Context type
		  mmu_use_context_0	       ,   // Context type
		  htd_tlbdatain_din	[38:0]}),    
	.din4	(dtlb_data_in_1		[50:0]	),     
	.sel0	(asi_wr_dtlb_data_in	[1   ]	), // ASI Write
	.sel1	(asi_wr_dtlb_data_access[1   ]	), // ASI Write
	.sel2	(asi_wr_dmmu_demap	[1   ]	), 
	.sel3	(htc_wr_dtlb_data_in	[1   ]	), // HWTW Write DTLB Data-In
	.en	(asi_d_data_in_en	[1   ]	),
	.dout	(dtlb_data_in_1		[50:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 dtlb_data_in_0_lat     (
	.scan_in(dtlb_data_in_0_lat_scanin),
	.scan_out(dtlb_data_in_0_lat_scanout),
	.din0	({{8 {1'b0}}		       ,   // Index valid & index
		  {4 {1'b0}}		       ,   // Demap valids & type
		  data_in		[38:0]}),   
	.din1	({1'b1			       ,   // Index valid
		  asi_mra_wr_data	[9:3],   // Index to write
		  {4 {1'b0}}		       ,   // Demap valids & type
		  data_in		[38:0]}),   
	.din2	({{8 {1'b0}}		       ,   // Index valid & index
		  asi_dmmu_demap_s	       ,   // Demap secondary context
		  1'b1			       ,   // Demap
		  asi_mra_wr_data	[7:6],   // Demap type field
		  dtlb_data_in_0	[38:37],
		  asi_demap_r_bit	       ,   // Demap R bit
		  dtlb_data_in_0	[35:0]}),    
	.din3	({{8 {1'b0}}		       ,   // Index valid & index
		  mmu_sec_context	       ,   // Replace with secondary cxt
		  1'b0			       ,   // Demap valid
		  mmu_use_context_1	       ,   // Context type
		  mmu_use_context_0	       ,   // Context type
		  htd_tlbdatain_din	[38:0]}),    
	.din4	(dtlb_data_in_0 	[50:0]	),     
	.sel0	(asi_wr_dtlb_data_in	[0   ]	), // ASI Write
	.sel1	(asi_wr_dtlb_data_access[0   ]	), 
	.sel2	(asi_wr_dmmu_demap	[0   ]	), 
	.sel3	(htc_wr_dtlb_data_in	[0   ]	), // HWTW Write DTLB Data-In
	.en	(asi_d_data_in_en	[0   ]	),
	.dout	(dtlb_data_in_0		[50:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


mmu_asd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_53 itte_data_mux      (
	.din0	({itlb_data_in_0	[48:39],	// Demap info, etc.
		  itlb_ps_gt_64k_0	       ,
		  immu_tag_access_0	[15:13],	// VA[15:13]
		  itlb_ps_gt_8k_0	       ,
		  thread_group		       ,	// TID[02]
		  2'b00			       ,	// TID[01:00]
		  itlb_data_in_0	[36   ],	// Real bit
		  itlb_data_in_0	[34:23],	// PA[39:28]
		  itlb_data_in_0	[22:17],	// PA[27:22]
		  itlb_data_in_0	[16:11],	// PA[21:16]
		  itlb_data_in_0	[10:8],	// PA[15:13]
		  itlb_data_in_0	[38   ],	// Valid
		  itlb_data_in_0	[37   ],	// NFO
		  itlb_data_in_0	[7   ],	// IE
		  itlb_data_in_0	[5   ],	// CP
		  itlb_data_in_0	[6   ],	// E
		  itlb_data_in_0	[4   ],	// P
		  itlb_data_in_0	[3   ]}),	// W
	.din1	({itlb_data_in_1	[48:39],	// Demap info, etc.
		  itlb_ps_gt_64k_1	       ,
		  immu_tag_access_1	[15:13],	// VA[15:13]
		  itlb_ps_gt_8k_1	       ,
		  thread_group		       ,	// TID[02]
		  2'b01			       ,	// TID[01:00]
		  itlb_data_in_1	[36   ],	// Real bit
		  itlb_data_in_1	[34:23],	// PA[39:28]
		  itlb_data_in_1	[22:17],	// PA[27:22]
		  itlb_data_in_1	[16:11],	// PA[21:16]
		  itlb_data_in_1	[10:8],	// PA[15:13]
		  itlb_data_in_1	[38   ],	// Valid
		  itlb_data_in_1	[37   ],	// NFO
		  itlb_data_in_1	[7   ],	// IE
		  itlb_data_in_1	[5   ],	// CP
		  itlb_data_in_1	[6   ],	// E
		  itlb_data_in_1	[4   ],	// P
		  itlb_data_in_1	[3   ]}),	// W
	.din2	({itlb_data_in_2	[48:39],	// Demap info, etc.
		  itlb_ps_gt_64k_2	       ,
		  immu_tag_access_2	[15:13],	// VA[15:13]
		  itlb_ps_gt_8k_2	       ,
		  thread_group		       ,	// TID[02]
		  2'b10			       ,	// TID[01:00]
		  itlb_data_in_2	[36   ],	// Real bit
		  itlb_data_in_2	[34:23],	// PA[39:28]
		  itlb_data_in_2	[22:17],	// PA[27:22]
		  itlb_data_in_2	[16:11],	// PA[21:16]
		  itlb_data_in_2	[10:8],	// PA[15:13]
		  itlb_data_in_2	[38   ],	// Valid
		  itlb_data_in_2	[37   ],	// NFO
		  itlb_data_in_2	[7   ],	// IE
		  itlb_data_in_2	[5   ],	// CP
		  itlb_data_in_2	[6   ],	// E
		  itlb_data_in_2	[4   ],	// P
		  itlb_data_in_2	[3   ]}),	// W
	.din3	({itlb_data_in_3	[48:39],	// Demap info, etc.
		  itlb_ps_gt_64k_3	       ,
		  immu_tag_access_3	[15:13],	// VA[15:13]
		  itlb_ps_gt_8k_3	       ,
		  thread_group		       ,	// TID[02]
		  2'b11			       ,	// TID[01:00]
		  itlb_data_in_3	[36   ],	// Real bit
		  itlb_data_in_3	[34:23],	// PA[39:28]
		  itlb_data_in_3	[22:17],	// PA[27:22]
		  itlb_data_in_3	[16:11],	// PA[21:16]
		  itlb_data_in_3	[10:8],	// PA[15:13]
		  itlb_data_in_3	[38   ],	// Valid
		  itlb_data_in_3	[37   ],	// NFO
		  itlb_data_in_3	[7   ],	// IE
		  itlb_data_in_3	[5   ],	// CP
		  itlb_data_in_3	[6   ],	// E
		  itlb_data_in_3	[4   ],	// P
		  itlb_data_in_3	[3   ]}),	// W
	.sel0	(asi_rd_itte_data	[0   ]	),
	.sel1	(asi_rd_itte_data	[1   ]	),
	.sel2	(asi_rd_itte_data	[2   ]	),
	.sel3	(asi_rd_itte_data	[3   ]	),
	.dout	({asd_itte_index	[6:0],
		  itte_data		[45:0]})
);

// Merge ITLB tag and data
mmu_asd_dp_nor_macro__ports_2__stack_58c__width_48 itte_tag_data_b_nor    (
	.din0	(itte_tag		[47:0]	),
	.din1	({2'b00			       , 
		  itte_data		[45:0]}),
	.dout	(asd_itte_tag_data_	[47:0]	)
);


mmu_asd_dp_mux_macro__mux_aope__ports_4__stack_58c__width_55 dtte_data_mux     (
	.din0	({dtlb_data_in_0	[50:39],	// Demap info, etc
		  dtlb_ps_gt_64k_0	       ,
		  dmmu_tag_access_0	[15:13],	// VA[15:13]
		  dtlb_ps_gt_8k_0	       ,
		  thread_group		       ,	// TID[02]
		  2'b00			       ,	// TID[01:00]
		  dtlb_data_in_0	[36   ],	// Real bit
		  dtlb_data_in_0	[34:23],	// PA[39:28]
		  dtlb_data_in_0	[22:17],	// PA[27:22]
		  dtlb_data_in_0	[16:11],	// PA[21:16]
		  dtlb_data_in_0	[10:8],	// PA[15:13]
		  dtlb_data_in_0	[38   ],	// Valid
		  dtlb_data_in_0	[37   ],	// NFO
		  dtlb_data_in_0	[7   ],	// IE
		  dtlb_data_in_0	[5   ],	// CP
		  dtlb_data_in_0	[6   ],	// E (Side effect)
		  dtlb_data_in_0	[4   ],	// P
		  dtlb_data_in_0	[3   ]}),	// W
	.din1	({dtlb_data_in_1	[50:39],	// Demap info, etc
		  dtlb_ps_gt_64k_1	       ,
		  dmmu_tag_access_1	[15:13],	// VA[15:13]
		  dtlb_ps_gt_8k_1	       ,
		  thread_group		       ,	// TID[02]
		  2'b01			       ,	// TID[01:00]
		  dtlb_data_in_1	[36   ],	// Real bit
		  dtlb_data_in_1	[34:23],	// PA[39:28]
		  dtlb_data_in_1	[22:17],	// PA[27:22]
		  dtlb_data_in_1	[16:11],	// PA[21:16]
		  dtlb_data_in_1	[10:8],	// PA[15:13]
		  dtlb_data_in_1	[38   ],	// Valid
		  dtlb_data_in_1	[37   ],	// NFO
		  dtlb_data_in_1	[7   ],	// IE
		  dtlb_data_in_1	[5   ],	// CP
		  dtlb_data_in_1	[6   ],	// E (Side effect)
		  dtlb_data_in_1	[4   ],	// P
		  dtlb_data_in_1	[3   ]}),	// W
	.din2	({dtlb_data_in_2	[50:39],	// Demap info, etc
		  dtlb_ps_gt_64k_2	       ,
		  dmmu_tag_access_2	[15:13],	// VA[15:13]
		  dtlb_ps_gt_8k_2	       ,
		  thread_group		       ,	// TID[02]
		  2'b10			       ,	// TID[01:00]
		  dtlb_data_in_2	[36   ],	// Real bit
		  dtlb_data_in_2	[34:23],	// PA[39:28]
		  dtlb_data_in_2	[22:17],	// PA[27:22]
		  dtlb_data_in_2	[16:11],	// PA[21:16]
		  dtlb_data_in_2	[10:8],	// PA[15:13]
		  dtlb_data_in_2	[38   ],	// Valid
		  dtlb_data_in_2	[37   ],	// NFO
		  dtlb_data_in_2	[7   ],	// IE
		  dtlb_data_in_2	[5   ],	// CP
		  dtlb_data_in_2	[6   ],	// E (Side effect)
		  dtlb_data_in_2	[4   ],	// P
		  dtlb_data_in_2	[3   ]}),	// W
	.din3	({dtlb_data_in_3	[50:39],	// Demap info, etc
		  dtlb_ps_gt_64k_3	       ,
		  dmmu_tag_access_3	[15:13],	// VA[15:13]
		  dtlb_ps_gt_8k_3	       ,
		  thread_group		       ,	// TID[02]
		  2'b11			       ,	// TID[01:00]
		  dtlb_data_in_3	[36   ],	// Real bit
		  dtlb_data_in_3	[34:23],	// PA[39:28]
		  dtlb_data_in_3	[22:17],	// PA[27:22]
		  dtlb_data_in_3	[16:11],	// PA[21:16]
		  dtlb_data_in_3	[10:8],	// PA[15:13]
		  dtlb_data_in_3	[38   ],	// Valid
		  dtlb_data_in_3	[37   ],	// NFO
		  dtlb_data_in_3	[7   ],	// IE
		  dtlb_data_in_3	[5   ],	// CP
		  dtlb_data_in_3	[6   ],	// E (Side effect)
		  dtlb_data_in_3	[4   ],	// P
		  dtlb_data_in_3	[3   ]}),	// W	
	.sel0	(asi_rd_dtte		[0   ]	),
	.sel1	(asi_rd_dtte		[1   ]	),
	.sel2	(asi_rd_dtte		[2   ]	),
	.dout	(dtte_data		[54:0]	)
);

mmu_asd_dp_buff_macro__rep_1__stack_58c__width_55 dtte_data_buf    (
	.din	(dtte_data		[54:0]	),
	.dout	(asd_dtte_data		[54:0]	)
);

assign asd_iht_p_ctx_0_0    [12:0] = p_context_0_0 [12:0];	
assign asd_iht_p_ctx_0_1    [12:0] = p_context_0_1 [12:0];
assign asd_iht_p_ctx_0_2    [12:0] = p_context_0_2 [12:0];
assign asd_iht_p_ctx_0_3    [12:0] = p_context_0_3 [12:0];

//////////////////////////////////////////////////////////////////////
//
// Scan patch panel
//
// fixscan start:
assign mra_read_1_lat_scanin     = scan_in                  ;
assign mra_read_0_lat_scanin     = mra_read_1_lat_scanout   ;
assign asi_rd_mux_scanin         = mra_read_0_lat_scanout   ;
assign itlb_data_in_3_lat_scanin = asi_rd_mux_scanout       ;
assign itlb_data_in_2_lat_scanin = itlb_data_in_3_lat_scanout;
assign itlb_data_in_1_lat_scanin = itlb_data_in_2_lat_scanout;
assign itlb_data_in_0_lat_scanin = itlb_data_in_1_lat_scanout;
assign dtlb_data_in_3_lat_scanin = itlb_data_in_0_lat_scanout;
assign dtlb_data_in_2_lat_scanin = dtlb_data_in_3_lat_scanout;
assign dtlb_data_in_1_lat_scanin = dtlb_data_in_2_lat_scanout;
assign dtlb_data_in_0_lat_scanin = dtlb_data_in_1_lat_scanout;
assign scan_out                  = dtlb_data_in_0_lat_scanout;

assign p_context_lat_wmr_scanin  = wmr_scan_in              ;
assign immu_tag_access_3_lat_wmr_scanin = p_context_lat_wmr_scanout;
assign immu_tag_access_2_lat_wmr_scanin = immu_tag_access_3_lat_wmr_scanout;
assign immu_tag_access_1_lat_wmr_scanin = immu_tag_access_2_lat_wmr_scanout;
assign immu_tag_access_0_lat_wmr_scanin = immu_tag_access_1_lat_wmr_scanout;
assign dmmu_tag_access_3_lat_wmr_scanin = immu_tag_access_0_lat_wmr_scanout;
assign dmmu_tag_access_2_lat_wmr_scanin = dmmu_tag_access_3_lat_wmr_scanout;
assign dmmu_tag_access_1_lat_wmr_scanin = dmmu_tag_access_2_lat_wmr_scanout;
assign dmmu_tag_access_0_lat_wmr_scanin = dmmu_tag_access_1_lat_wmr_scanout;
assign wmr_scan_out              = dmmu_tag_access_0_lat_wmr_scanout;
// fixscan end:
endmodule


//
//   buff macro
//
//


module mmu_asd_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_24 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [22:0] so;

  input [23:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [23:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asd_dp_msff_macro__minbuff_1__stack_58c__width_58 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [56:0] so;

  input [57:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [57:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(58)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[57:0]),
.si({scan_in,so[56:0]}),
.so({so[56:0],scan_out}),
.q(dout[57:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asd_dp_msff_macro__mux_aonpe__ports_4__stack_58c__width_52 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire [51:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [50:0] so;

  input [51:0] din0;
  input sel0;
  input [51:0] din1;
  input sel1;
  input [51:0] din2;
  input sel2;
  input [51:0] din3;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [51:0] dout;


  output scan_out;


cl_dp1_muxbuff4_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(52)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[51:0]),
  .in1(din1[51:0]),
  .in2(din2[51:0]),
  .in3(din3[51:0]),
.dout(muxout[51:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(52)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[51:0]),
.si({scan_in,so[50:0]}),
.so({so[50:0],scan_out}),
.q(dout[51:0])
);


endmodule


//
//   buff macro
//
//


module mmu_asd_dp_buff_macro__left_13__stack_58c__width_35 (
  din, 
  dout);
  input [34:0] din;
  output [34:0] dout;


buff #(35)  d0_0 (
.in(din[34:0]),
.out(dout[34:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asd_dp_msff_macro__mux_aope__ports_7__stack_58c__width_48 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire [47:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din0;
  input [47:0] din1;
  input [47:0] din2;
  input [47:0] din3;
  input [47:0] din4;
  input [47:0] din5;
  input [47:0] din6;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_penc7_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6)
);

mux7s #(48)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
  .in5(din5[47:0]),
  .in6(din6[47:0]),
.dout(muxout[47:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_asd_dp_mux_macro__mux_aonpe__ports_8__width_62 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [61:0] din0;
  input sel0;
  input [61:0] din1;
  input sel1;
  input [61:0] din2;
  input sel2;
  input [61:0] din3;
  input sel3;
  input [61:0] din4;
  input sel4;
  input [61:0] din5;
  input sel5;
  input [61:0] din6;
  input sel6;
  input [61:0] din7;
  input sel7;
  output [61:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(62)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[61:0]),
  .in1(din1[61:0]),
  .in2(din2[61:0]),
  .in3(din3[61:0]),
  .in4(din4[61:0]),
  .in5(din5[61:0]),
  .in6(din6[61:0]),
  .in7(din7[61:0]),
.dout(dout[61:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_asd_dp_mux_macro__mux_aodec__ports_8__stack_58c__width_13 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [12:0] din0;
  input [12:0] din1;
  input [12:0] din2;
  input [12:0] din3;
  input [12:0] din4;
  input [12:0] din5;
  input [12:0] din6;
  input [12:0] din7;
  input [2:0] sel;
  output [12:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(13)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
  .in2(din2[12:0]),
  .in3(din3[12:0]),
  .in4(din4[12:0]),
  .in5(din5[12:0]),
  .in6(din6[12:0]),
  .in7(din7[12:0]),
.dout(dout[12:0])
);


endmodule


//
//   buff macro
//
//


module mmu_asd_dp_buff_macro__stack_58c__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


buff #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_asd_dp_mux_macro__left_13__mux_aodec__ports_8__stack_58c__width_35 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [34:0] din0;
  input [34:0] din1;
  input [34:0] din2;
  input [34:0] din3;
  input [34:0] din4;
  input [34:0] din5;
  input [34:0] din6;
  input [34:0] din7;
  input [2:0] sel;
  output [34:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(35)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[34:0]),
  .in1(din1[34:0]),
  .in2(din2[34:0]),
  .in3(din3[34:0]),
  .in4(din4[34:0]),
  .in5(din5[34:0]),
  .in6(din6[34:0]),
  .in7(din7[34:0]),
.dout(dout[34:0])
);


endmodule


//
//   buff macro
//
//


module mmu_asd_dp_buff_macro__rep_1__stack_58c__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module mmu_asd_dp_zero_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


zero #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module mmu_asd_dp_nor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module mmu_asd_dp_or_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module mmu_asd_dp_buff_macro__rep_1__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asd_dp_msff_macro__mux_aonpe__ports_2__width_62 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire [61:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [60:0] so;

  input [61:0] din0;
  input sel0;
  input [61:0] din1;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [61:0] dout;


  output scan_out;


cl_dp1_muxbuff2_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(62)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[61:0]),
  .in1(din1[61:0]),
.dout(muxout[61:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(62)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[61:0]),
.si({scan_in,so[60:0]}),
.so({so[60:0],scan_out}),
.q(dout[61:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module mmu_asd_dp_and_macro__ports_2__stack_58c__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


and2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module mmu_asd_dp_or_macro__ports_2__stack_58c__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


or2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module mmu_asd_dp_or_macro__ports_3__stack_58c__width_8 (
  din0, 
  din1, 
  din2, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  output [7:0] dout;


or3 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.in2(din2[7:0]),
.out(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_asd_dp_mux_macro__mux_aonpe__ports_4__stack_58c__width_48 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [47:0] din0;
  input sel0;
  input [47:0] din1;
  input sel1;
  input [47:0] din2;
  input sel2;
  input [47:0] din3;
  input sel3;
  output [47:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(48)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
.dout(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_asd_dp_mux_macro__dmux_8x__mux_aope__ports_4__stack_58c__width_48 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [47:0] din0;
  input [47:0] din1;
  input [47:0] din2;
  input [47:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [47:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(48)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
.dout(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_49 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [48:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [47:0] so;

  input [48:0] din0;
  input [48:0] din1;
  input [48:0] din2;
  input [48:0] din3;
  input [48:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [48:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(49)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[48:0]),
  .in1(din1[48:0]),
  .in2(din2[48:0]),
  .in3(din3[48:0]),
  .in4(din4[48:0]),
.dout(muxout[48:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(49)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[48:0]),
.si({scan_in,so[47:0]}),
.so({so[47:0],scan_out}),
.q(dout[48:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asd_dp_msff_macro__mux_aope__ports_5__stack_58c__width_51 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [50:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [49:0] so;

  input [50:0] din0;
  input [50:0] din1;
  input [50:0] din2;
  input [50:0] din3;
  input [50:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [50:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(51)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[50:0]),
  .in1(din1[50:0]),
  .in2(din2[50:0]),
  .in3(din3[50:0]),
  .in4(din4[50:0]),
.dout(muxout[50:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(51)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[50:0]),
.si({scan_in,so[49:0]}),
.so({so[49:0],scan_out}),
.q(dout[50:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_asd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_53 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [52:0] din0;
  input sel0;
  input [52:0] din1;
  input sel1;
  input [52:0] din2;
  input sel2;
  input [52:0] din3;
  input sel3;
  output [52:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(53)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[52:0]),
  .in1(din1[52:0]),
  .in2(din2[52:0]),
  .in3(din3[52:0]),
.dout(dout[52:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module mmu_asd_dp_nor_macro__ports_2__stack_58c__width_48 (
  din0, 
  din1, 
  dout);
  input [47:0] din0;
  input [47:0] din1;
  output [47:0] dout;


nor2 #(48)  d0_0 (
.in0(din0[47:0]),
.in1(din1[47:0]),
.out(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_asd_dp_mux_macro__mux_aope__ports_4__stack_58c__width_55 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [54:0] din0;
  input [54:0] din1;
  input [54:0] din2;
  input [54:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [54:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(55)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[54:0]),
  .in1(din1[54:0]),
  .in2(din2[54:0]),
  .in3(din3[54:0]),
.dout(dout[54:0])
);


endmodule


//
//   buff macro
//
//


module mmu_asd_dp_buff_macro__rep_1__stack_58c__width_55 (
  din, 
  dout);
  input [54:0] din;
  output [54:0] dout;


buff #(55)  d0_0 (
.in(din[54:0]),
.out(dout[54:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_ase_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_ase_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  lsu_va_b, 
  lsu_context_b, 
  asi_rd_tsb_cfg_0_2, 
  asi_rd_tsb_cfg_1_3, 
  asi_rd_real_range, 
  asi_rd_physical_offset, 
  asi_sel_mra_0_in, 
  asi_mra_wr_en_next, 
  asi_mra_wr_data, 
  asd0_rd_data, 
  asd1_rd_data, 
  asd0_itte_tag_data_, 
  asd1_itte_tag_data_, 
  asi_mbist_run, 
  asi_ecc_cmpsel_in, 
  asi_ase_cmpsel_in, 
  asi_mbist_wdata, 
  asi_ase_compare_data, 
  mel0_parity, 
  mel1_parity, 
  scan_out, 
  ase_mra_wr_data, 
  ase_mra_wr_data_minbuf, 
  ase_mra_rd_data, 
  ase_lsu_va_w, 
  ase_lsu_context_w, 
  ase_mbd_mbist_data, 
  mmu_itte_tag_data);
wire en;
wire clk;
wire stop;
wire test;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire lsu_context_w_lat_scanin;
wire lsu_context_w_lat_scanout;
wire [7:0] compare_data;
wire [1:0] mbist_cmpsel;
wire ecc_cmpsel;
wire sel_mra_0;
wire lsu_va_w_lat_scanin;
wire lsu_va_w_lat_scanout;
wire [47:13] lsu_va_w;
wire [81:0] mra_rd_data;
wire [60:54] wr_data_unused;
wire wr_1_mux_scanin;
wire wr_1_mux_scanout;
wire wr_0_mux_scanin;
wire wr_0_mux_scanout;
wire [1:0] mra_parity;
wire tcu_muxtest_rep0;


input		l2clk;
input 		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		tcu_dectest;
input		tcu_muxtest;

input	[47:0]	lsu_va_b;
input	[12:0]	lsu_context_b;

input		asi_rd_tsb_cfg_0_2;
input		asi_rd_tsb_cfg_1_3;
input		asi_rd_real_range;
input		asi_rd_physical_offset;
input 		asi_sel_mra_0_in;
input		asi_mra_wr_en_next;

input	[63:0]	asi_mra_wr_data;

input	[81:0]	asd0_rd_data;
input	[81:0]	asd1_rd_data;

input	[47:0]	asd0_itte_tag_data_;
input	[47:0]	asd1_itte_tag_data_;

input		asi_mbist_run;		// MBIST
input		asi_ecc_cmpsel_in;	// MBIST
input	[1:0]	asi_ase_cmpsel_in;	// MBIST
input	[7:0]	asi_mbist_wdata;	// MBIST
input	[7:0]	asi_ase_compare_data;	// MBIST
input	[1:0]	mel0_parity;		// MBIST
input	[1:0]	mel1_parity;		// MBIST


output		scan_out;

output 	[81:0]	ase_mra_wr_data;
output 	[81:0]	ase_mra_wr_data_minbuf;

output	[63:0]	ase_mra_rd_data;

output	[47:13]	ase_lsu_va_w;
output	[12:0]	ase_lsu_context_w;

output	[31:0]	ase_mbd_mbist_data;	// MBIST

output	[47:0]	mmu_itte_tag_data;


//////////////////////////////////////////////////////////////////////

assign en	= 1'b1;
assign clk	= l2clk;
assign stop	= 1'b0;
assign test	= tcu_dectest;

mmu_ase_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);


mmu_ase_dp_msff_macro__stack_58c__width_25 lsu_context_w_lat   (
	.scan_in(lsu_context_w_lat_scanin),
	.scan_out(lsu_context_w_lat_scanout),
	.din	({asi_ase_compare_data	[7:0],
		  asi_ase_cmpsel_in	[1:0],
		  asi_ecc_cmpsel_in	       ,
		  asi_sel_mra_0_in	       ,
		  lsu_context_b		[12:0]}),
	.dout	({compare_data		[7:0],
		  mbist_cmpsel		[1:0],
		  ecc_cmpsel		       ,
		  sel_mra_0		       ,
		  ase_lsu_context_w	[12:0]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_ase_dp_msff_macro__left_13__stack_58c__width_35 lsu_va_w_lat    (
	.scan_in(lsu_va_w_lat_scanin),
	.scan_out(lsu_va_w_lat_scanout),
	.din	({lsu_va_b		[47:13]}),
	.dout	({lsu_va_w		[47:13]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign ase_lsu_va_w[47:13] =
	lsu_va_w[47:13];


//////////////////////////////////////////////////////////////////////
//
// Mux the two thread groups together
//
mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_24 mra_rd_data_1_mux     (
	.din0	(asd0_rd_data		[81:58]),
	.din1	(asd1_rd_data		[81:58]),
	.sel0	(sel_mra_0			),
	.dout	(mra_rd_data		[81:58])
);

mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_58 mra_rd_data_0_mux     (
	.din0	(asd0_rd_data		[57:0]	),
	.din1	(asd1_rd_data		[57:0]	),
	.sel0	(sel_mra_0			),
	.dout	(mra_rd_data		[57:0]	)
);


//////////////////////////////////////////////////////////////////////
//
// Extract and format read data
//

mmu_ase_dp_mux_macro__mux_aonpe__ports_4__width_64 mra_rd_mux    (
	.din0	({mra_rd_data		[77:75],   // TSB config	63:61
		  {21 {1'b0}}		       ,
		  mra_rd_data		[74:48],   // TSB config	39:13
		  { 4 {1'b0}}		       ,
		  mra_rd_data		[47:39]}), // TSB config	08:00
	.din1	({mra_rd_data		[38:36],   // TSB config	63:61
		  {21 {1'b0}}		       ,
		  mra_rd_data		[35:9],   // TSB config	39:13
		  { 4 {1'b0}}		       ,
		  mra_rd_data		[8:0]}), // TSB config	08:00
	.din2	({mra_rd_data		[81   ],   // Real range	63
		  { 9 {1'b0}}		       ,
		  mra_rd_data		[80:27]}), // Real range 	53:00
	.din3	({{24 {1'b0}}		       ,
		  mra_rd_data		[26:0],   // Physical offset	39:13
		  {13 {1'b0}}		       }),
	.sel0	(asi_rd_tsb_cfg_0_2		),
	.sel1	(asi_rd_tsb_cfg_1_3		),
	.sel2	(asi_rd_real_range		),
	.sel3	(asi_rd_physical_offset		),
	.dout	(ase_mra_rd_data	[63:0]	)
);


//////////////////////////////////////////////////////////////////////
//
// Modify data for write
//

assign wr_data_unused[60:54] =
	asi_mra_wr_data[60:54];

mmu_ase_dp_msff_macro__mux_aope__ports_4__stack_58c__width_24 wr_1_mux     (
	.scan_in(wr_1_mux_scanin),
	.scan_out(wr_1_mux_scanout),
	.din0	({asi_mbist_wdata	[1:0],   //			81:80
		  asi_mbist_wdata	[7:0],   //			79:72
		  asi_mbist_wdata	[7:0],   //			71:64
		  asi_mbist_wdata	[7:2]}), //			63:58
	.din1	({{4 {1'b0}}		       ,   //			81:78
		  asi_mra_wr_data	[63:61],   // TSB config 0,2	77:75
		  asi_mra_wr_data	[39:29],   // TSB config 0,2	74:64
		  asi_mra_wr_data	[28:23]}), // TSB config 0,2 	63:58
	.din2	({asi_mra_wr_data	[63   ],   // Real range 	81
		  asi_mra_wr_data	[53:31]}), // Real range	80:58
	.din3	(mra_rd_data		[81:58]	),
	.sel0	(asi_mbist_run			),
	.sel1	(asi_rd_tsb_cfg_0_2		),
	.sel2	(asi_rd_real_range		),
	.en	(asi_mra_wr_en_next		),
	.dout	(ase_mra_wr_data	[81:58]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_24 wr_1_minbuf    (
    .din (ase_mra_wr_data[81:58]),
    .dout (ase_mra_wr_data_minbuf[81:58])
);
                                                         

mmu_ase_dp_msff_macro__mux_aope__ports_5__stack_58c__width_58 wr_0_mux     (
	.scan_in(wr_0_mux_scanin),
	.scan_out(wr_0_mux_scanout),
	.din0	({asi_mbist_wdata	[1:0],
		  {7 {asi_mbist_wdata	[7:0]}}}),
	.din1	({asi_mra_wr_data	[22:13],   // TSB config 0,2 	57:48
		  asi_mra_wr_data	[8:0],   // TSB config 0,2	47:39
		  mra_rd_data		[38:0]}), // TSB config 1,3	
	.din2	({mra_rd_data		[57:39],   // TSB config 0,2
		  asi_mra_wr_data	[63:61],   // TSB config 1,3	38:36
		  asi_mra_wr_data	[39:13],   // TSB config 1,3	35:09
		  asi_mra_wr_data	[8:0]}), // TSB config 1,3	08:00
	.din3	({asi_mra_wr_data	[30:0],   // Real range 	57:27
		  mra_rd_data		[26:0]}), // Physical offset
	.din4	({mra_rd_data		[57:27],   // Real range
		  asi_mra_wr_data	[39:13]}), // Physical offset	26:00
	.sel0	(asi_mbist_run			),
	.sel1	(asi_rd_tsb_cfg_0_2		),
	.sel2	(asi_rd_tsb_cfg_1_3		),
	.sel3	(asi_rd_real_range		),
	.en	(asi_mra_wr_en_next		),
	.dout	(ase_mra_wr_data	[57:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_58 wr_0_minbuf    (
    .din (ase_mra_wr_data[57:0]),
    .dout (ase_mra_wr_data_minbuf[57:0])
);
                                                         

//////////////////////////////////////////////////////////////////////////////
//
// Merge ITLB reload buses together
//

mmu_ase_dp_nand_macro__ports_2__stack_58c__width_48 itte_tag_data_nand    (
	.din0	(asd0_itte_tag_data_	[47:0]	),
	.din1	(asd1_itte_tag_data_	[47:0]	),
	.dout	(mmu_itte_tag_data	[47:0]	)
);


//////////////////////////////////////////////////////////////////////////////
//
// MBIST muxing
//

mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_2 mbist_ecc_mux     (
	.din0	(mel0_parity		[1:0]	),
	.din1	(mel1_parity		[1:0]	),
	.sel0	(ecc_cmpsel			),
	.dout	(mra_parity		[1:0]	)
);

mmu_ase_dp_buff_macro__dbuff_32x__width_1 tst_mux_rep0   (
	.din	(tcu_muxtest			),
	.dout	(tcu_muxtest_rep0		)
);

mmu_ase_dp_mux_macro__mux_pgdec__ports_8__stack_58c__width_32 mbist_mux     (
	.din0	(asd1_rd_data		[31:0]	),
	.din1	(asd1_rd_data		[63:32]	),
	.din2	({compare_data		[7:0],
		  compare_data		[7:2],
		  asd1_rd_data		[81:64]}),
	.din3	({{3 {compare_data	[7:0]}},
		  compare_data		[7:4],
		  mra_parity		[1:0],
		  compare_data		[1:0]}),
	.din4	(asd0_rd_data		[31:0]	),
	.din5	(asd0_rd_data		[63:32]	),
	.din6	({compare_data		[7:0],
		  compare_data		[7:2],
		  asd0_rd_data		[81:64]}),
	.din7	({{3 {compare_data	[7:0]}},
		  compare_data		[7:4],
		  mra_parity		[1:0],
		  compare_data		[1:0]}),
	.sel	({sel_mra_0		       ,
		  mbist_cmpsel		[1:0]}),
	.muxtst	(tcu_muxtest_rep0		),
	.dout	(ase_mbd_mbist_data	[31:0]	),
  .test(test)
);


// fixscan start:
assign lsu_context_w_lat_scanin  = scan_in                  ;
assign lsu_va_w_lat_scanin       = lsu_context_w_lat_scanout;
assign wr_1_mux_scanin           = lsu_va_w_lat_scanout     ;
assign wr_0_mux_scanin           = wr_1_mux_scanout         ;
assign scan_out                  = wr_0_mux_scanout         ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module mmu_ase_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_ase_dp_msff_macro__stack_58c__width_25 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [23:0] so;

  input [24:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [24:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(25)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[24:0]),
.si({scan_in,so[23:0]}),
.so({so[23:0],scan_out}),
.q(dout[24:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_ase_dp_msff_macro__left_13__stack_58c__width_35 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [33:0] so;

  input [34:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [34:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(35)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[34:0]),
.si({scan_in,so[33:0]}),
.so({so[33:0],scan_out}),
.q(dout[34:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_24 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [23:0] din0;
  input [23:0] din1;
  input sel0;
  output [23:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(24)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[23:0]),
  .in1(din1[23:0]),
.dout(dout[23:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_58 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [57:0] din0;
  input [57:0] din1;
  input sel0;
  output [57:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(58)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[57:0]),
  .in1(din1[57:0]),
.dout(dout[57:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_ase_dp_mux_macro__mux_aonpe__ports_4__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  output [63:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_ase_dp_msff_macro__mux_aope__ports_4__stack_58c__width_24 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire [23:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [22:0] so;

  input [23:0] din0;
  input [23:0] din1;
  input [23:0] din2;
  input [23:0] din3;
  input sel0;
  input sel1;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [23:0] dout;


  output scan_out;


cl_dp1_penc4_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(24)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[23:0]),
  .in1(din1[23:0]),
  .in2(din2[23:0]),
  .in3(din3[23:0]),
.dout(muxout[23:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


//
//   buff macro
//
//


module mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_24 (
  din, 
  dout);
  input [23:0] din;
  output [23:0] dout;


buff #(24)  d0_0 (
.in(din[23:0]),
.out(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_ase_dp_msff_macro__mux_aope__ports_5__stack_58c__width_58 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [57:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [56:0] so;

  input [57:0] din0;
  input [57:0] din1;
  input [57:0] din2;
  input [57:0] din3;
  input [57:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [57:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(58)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[57:0]),
  .in1(din1[57:0]),
  .in2(din2[57:0]),
  .in3(din3[57:0]),
  .in4(din4[57:0]),
.dout(muxout[57:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(58)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[57:0]),
.si({scan_in,so[56:0]}),
.so({so[56:0],scan_out}),
.q(dout[57:0])
);


endmodule


//
//   buff macro
//
//


module mmu_ase_dp_buff_macro__minbuff_1__stack_58c__width_58 (
  din, 
  dout);
  input [57:0] din;
  output [57:0] dout;


buff #(58)  d0_0 (
.in(din[57:0]),
.out(dout[57:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_ase_dp_nand_macro__ports_2__stack_58c__width_48 (
  din0, 
  din1, 
  dout);
  input [47:0] din0;
  input [47:0] din1;
  output [47:0] dout;


nand2 #(48)  d0_0 (
.in0(din0[47:0]),
.in1(din1[47:0]),
.out(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_ase_dp_mux_macro__mux_aope__ports_2__stack_58c__width_2 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [1:0] din0;
  input [1:0] din1;
  input sel0;
  output [1:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(2)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[1:0]),
  .in1(din1[1:0]),
.dout(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module mmu_ase_dp_buff_macro__dbuff_32x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_ase_dp_mux_macro__mux_pgdec__ports_8__stack_58c__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input [31:0] din4;
  input [31:0] din5;
  input [31:0] din6;
  input [31:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [31:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
  .in5(din5[31:0]),
  .in6(din6[31:0]),
  .in7(din7[31:0]),
.dout(dout[31:0]),
  .muxtst(muxtst)
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_asi_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  mmu_asi_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  htc_itlb_clken, 
  htc_dtlb_clken, 
  lsu_asi_clken, 
  lsu_mmu_pmen, 
  tlu_tag_access_tid_0_b, 
  tlu_i_tag_access_0_b, 
  tlu_d_tag_access_0_b, 
  tlu_tag_access_tid_1_b, 
  tlu_i_tag_access_1_b, 
  tlu_d_tag_access_1_b, 
  mbi_mra0_write_en, 
  mbi_mra1_write_en, 
  mbi_scp0_write_en, 
  mbi_scp1_write_en, 
  mbi_addr, 
  mbi_run, 
  mbi_wdata, 
  mbi_mra0_read_en, 
  mbi_mra1_read_en, 
  mbi_scp0_read_en, 
  mbi_scp1_read_en, 
  mbi_mmu_cmpsel, 
  mbd_compare, 
  error_inject_enable, 
  error_inject_mrau, 
  error_inject_scau, 
  error_inject_mask, 
  lsu_rngf_cdbus, 
  tlu_iht_request, 
  tlu_dht_request, 
  tlu_release_tte, 
  tlu_ceter_pscce, 
  scp0_data, 
  scp1_data, 
  scp0_ecc, 
  scp1_ecc, 
  sel_scac, 
  sel_scau, 
  ase_mra_rd_data, 
  mel0_parity, 
  mel1_parity, 
  mel0_parity_err, 
  mel1_parity_err, 
  asd0_asi_rd_data, 
  asd1_asi_rd_data, 
  asd0_dtte_tag, 
  asd1_dtte_tag, 
  asd0_dtte_data, 
  asd1_dtte_data, 
  asd0_itte_index, 
  asd1_itte_index, 
  asd0_asi_zero_context, 
  asd1_asi_zero_context, 
  htd_tsbptr, 
  htc_mra_addr_in, 
  htc_mra_rd_en, 
  htc_wr_itlb_data_in, 
  htc_wr_dtlb_data_in, 
  mmu_i_unauth_access, 
  mmu_i_tsb_miss, 
  mmu_d_tsb_miss, 
  mmu_i_tte_outofrange, 
  mmu_d_tte_outofrange, 
  mmu_i_eccerr, 
  mmu_d_eccerr, 
  scan_out, 
  wmr_scan_out, 
  asi_error_scau, 
  asi_error_mrau, 
  asi_error_mask, 
  asi_scp_addr, 
  asi_scp_wr_en, 
  asi_scp_rd_en, 
  asi_rd_scp0, 
  asi_mra_rd_addr_0, 
  asi_mra_rd_addr_1, 
  asi_mra_rd_en, 
  asi_mra_wr_addr, 
  asi_mra_wr_en, 
  asi_mra_rd_en_last, 
  asi_rd_tsb_cfg_0_2, 
  asi_rd_tsb_cfg_1_3, 
  asi_rd_tsb_ptr_, 
  asi_rd_real_range, 
  asi_rd_physical_offset, 
  asi_sel_mra_0_in, 
  asi_mra_wr_en_next, 
  asi_rd_immu_tag_target, 
  asi_rd_immu_tag_access, 
  asi_rd_dmmu_tag_target, 
  asi_rd_dmmu_tag_access, 
  asi_rd_i_access_target, 
  asi_rd_d_access_target, 
  asi_rd_access_target, 
  asi_rd_itte_tag, 
  asi_rd_itte_data, 
  asi_rd_dtte, 
  asi_wr_immu_tag_access, 
  asi_wr_itlb_data_in, 
  asi_wr_itlb_data_access, 
  asi_wr_immu_demap, 
  asi_wr_immu_demap_p, 
  asi_wr_immu_demap_n, 
  asi_wr_dmmu_tag_access, 
  asi_wr_dtlb_data_in, 
  asi_wr_dtlb_data_access, 
  asi_wr_partition_id, 
  asi_wr_dmmu_demap, 
  asi_wr_dmmu_demap_p, 
  asi_wr_dmmu_demap_s_n, 
  asi_dmmu_demap_s, 
  asi_wr_p_context_0, 
  asi_p_context_0_en, 
  asi_tag_access_sel, 
  asi_tsb_ptr_req_valid, 
  asi_tsb_ptr_req, 
  asi_tsb_ptr_number, 
  asi_tsb_hwtw_enable_0, 
  asi_tsb_hwtw_enable_1, 
  asi_data_in_real, 
  asi_seg_wr_data, 
  asi_wr_data, 
  asi_mra_wr_data, 
  asi_mra_req_grant, 
  asi_demap_r_bit, 
  asi_rd_data, 
  asi_hwtw_config_0, 
  asi_hwtw_config_1, 
  asi_hwtw_config_2, 
  asi_hwtw_config_3, 
  asi_hwtw_config_4, 
  asi_hwtw_config_5, 
  asi_hwtw_config_6, 
  asi_hwtw_config_7, 
  asi_sel_en, 
  asi_i_tag_access_en, 
  asi_d_tag_access_en, 
  asi_i_data_in_en, 
  asi_d_data_in_en, 
  asi_mbist_wdata, 
  asi_ase_compare_data, 
  asi_compare_data, 
  asi_mbd_scp_data, 
  asi_mbd_sel_scp, 
  asi_mbist_ecc_in, 
  asi_mbist_ecc, 
  asi_mbist_run, 
  asi_ecc_cmpsel_in, 
  asi_ase_cmpsel_in, 
  mmu_asi_data, 
  mmu_asi_read, 
  mmu_write_itlb, 
  mmu_dtlb_reload_stall, 
  mmu_dtlb_reload, 
  mmu_hw_tw_enable, 
  mmu_asi_cecc, 
  mmu_asi_uecc, 
  mmu_asi_tid, 
  mmu_asi_index, 
  mmu_asi_mra_not_sca, 
  mmu_dae_req, 
  mmu_dae_tid, 
  mmu_reload_done, 
  mmu_index, 
  mmu_mbi_mra0_fail, 
  mmu_mbi_mra1_fail, 
  mmu_mbi_scp0_fail, 
  mmu_mbi_scp1_fail);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire stg1_en_in;
wire stg1_en_lat_scanin;
wire stg1_en_lat_scanout;
wire stg1_en;
wire stg2_en_in;
wire stg2_en;
wire mbist_run;
wire stg2_en_lat_scanin;
wire stg2_en_lat_scanout;
wire pstg2_en;
wire [7:0] prd_itte;
wire [7:0] prd_dtte;
wire [7:0] rd_dtte_hwtw;
wire stg3_en_lat_scanin;
wire stg3_en_lat_scanout;
wire stg3_en;
wire stg4_en_lat_scanin;
wire stg4_en_lat_scanout;
wire stg4_en;
wire stg1_4_en;
wire l1clk_pm1;
wire pm2_en;
wire l1clk_pm2;
wire mbist_run_lat_scanin;
wire mbist_run_lat_scanout;
wire mra0_wr_en_lat_scanin;
wire mra0_wr_en_lat_scanout;
wire mbist_mra0_wr_en;
wire mra1_wr_en_lat_scanin;
wire mra1_wr_en_lat_scanout;
wire mbist_mra1_wr_en;
wire scp0_wr_en_lat_scanin;
wire scp0_wr_en_lat_scanout;
wire mbist_scp0_wr_en;
wire scp1_wr_en_lat_scanin;
wire scp1_wr_en_lat_scanout;
wire mbist_scp1_wr_en;
wire mbist_addr_lat_scanin;
wire mbist_addr_lat_scanout;
wire [4:0] mbist_addr;
wire mbist_wdata_lat_scanin;
wire mbist_wdata_lat_scanout;
wire [7:0] mbist_wdata;
wire mra0_rd_en_lat_scanin;
wire mra0_rd_en_lat_scanout;
wire mbist_mra0_rd_en;
wire mra1_rd_en_lat_scanin;
wire mra1_rd_en_lat_scanout;
wire mbist_mra1_rd_en;
wire scp0_rd_en_lat_scanin;
wire scp0_rd_en_lat_scanout;
wire mbist_scp0_rd_en;
wire scp1_rd_en_lat_scanin;
wire scp1_rd_en_lat_scanout;
wire mbist_scp1_rd_en;
wire mbist_cmpsel_lat_scanin;
wire mbist_cmpsel_lat_scanout;
wire [1:0] mbist_cmpsel;
wire [63:0] mbist_wr_data;
wire [7:0] mbist_wdata_2;
wire mra0_wr_en_2_lat_scanin;
wire mra0_wr_en_2_lat_scanout;
wire mbist_mra0_wr_en_2;
wire mra1_wr_en_2_lat_scanin;
wire mra1_wr_en_2_lat_scanout;
wire mbist_mra1_wr_en_2;
wire mra0_rd_en_2_lat_scanin;
wire mra0_rd_en_2_lat_scanout;
wire mbist_mra0_rd_en_2;
wire mra1_rd_en_2_lat_scanin;
wire mra1_rd_en_2_lat_scanout;
wire mbist_mra1_rd_en_2;
wire scp0_rd_en_2_lat_scanin;
wire scp0_rd_en_2_lat_scanout;
wire mbist_scp0_rd_en_2;
wire scp1_rd_en_2_lat_scanin;
wire scp1_rd_en_2_lat_scanout;
wire mbist_scp1_rd_en_2;
wire mbist_addr_2_lat_scanin;
wire mbist_addr_2_lat_scanout;
wire [4:0] mbist_addr_2;
wire mbist_cmpsel_2_lat_scanin;
wire mbist_cmpsel_2_lat_scanout;
wire [1:0] mbist_cmpsel_2;
wire mbist_compare_data_lat_scanin;
wire mbist_compare_data_lat_scanout;
wire [7:0] compare_data_in;
wire [7:0] mbist_wdata_3;
wire [7:0] compare_data;
wire mbist_mra_rd_en_3;
wire mbist_mra0_rd_en_3;
wire mbist_mra1_rd_en_3;
wire mbist_scp0_0_rd_en;
wire mbist_scp0_1_rd_en;
wire mbist_scp0_2_rd_en;
wire mbist_scp1_0_rd_en;
wire mbist_scp1_1_rd_en;
wire mbist_scp1_2_rd_en;
wire mra0_rd_en_3_lat_scanin;
wire mra0_rd_en_3_lat_scanout;
wire mra1_rd_en_3_lat_scanin;
wire mra1_rd_en_3_lat_scanout;
wire scp0_rd_en_3_lat_scanin;
wire scp0_rd_en_3_lat_scanout;
wire mbist_scp0_rd_en_3;
wire scp1_rd_en_3_lat_scanin;
wire scp1_rd_en_3_lat_scanout;
wire mbist_scp1_rd_en_3;
wire mra0_rd_en_4_lat_scanin;
wire mra0_rd_en_4_lat_scanout;
wire mbist_mra0_rd_en_4;
wire mra1_rd_en_4_lat_scanin;
wire mra1_rd_en_4_lat_scanout;
wire mbist_mra1_rd_en_4;
wire mra0_fail_in;
wire mra1_fail_in;
wire scp0_fail_in;
wire scp1_fail_in;
wire mra0_fail_lat_scanin;
wire mra0_fail_lat_scanout;
wire mra0_fail;
wire mra1_fail_lat_scanin;
wire mra1_fail_lat_scanout;
wire mra1_fail;
wire scp0_fail_lat_scanin;
wire scp0_fail_lat_scanout;
wire scp0_fail;
wire scp1_fail_lat_scanin;
wire scp1_fail_lat_scanout;
wire scp1_fail;
wire [1:0] hwtw_config_0_in;
wire [7:0] wr_hwtw_config_dec;
wire [63:0] data_1;
wire [1:0] hwtw_config_0;
wire [1:0] hwtw_config_1_in;
wire [1:0] hwtw_config_1;
wire [1:0] hwtw_config_2_in;
wire [1:0] hwtw_config_2;
wire [1:0] hwtw_config_3_in;
wire [1:0] hwtw_config_3;
wire [1:0] hwtw_config_4_in;
wire [1:0] hwtw_config_4;
wire [1:0] hwtw_config_5_in;
wire [1:0] hwtw_config_5;
wire [1:0] hwtw_config_6_in;
wire [1:0] hwtw_config_6;
wire [1:0] hwtw_config_7_in;
wire [1:0] hwtw_config_7;
wire hwtw_config_0_lat_wmr_scanin;
wire hwtw_config_0_lat_wmr_scanout;
wire hwtw_config_1_lat_wmr_scanin;
wire hwtw_config_1_lat_wmr_scanout;
wire hwtw_config_2_lat_wmr_scanin;
wire hwtw_config_2_lat_wmr_scanout;
wire hwtw_config_3_lat_wmr_scanin;
wire hwtw_config_3_lat_wmr_scanout;
wire hwtw_config_4_lat_wmr_scanin;
wire hwtw_config_4_lat_wmr_scanout;
wire hwtw_config_5_lat_wmr_scanin;
wire hwtw_config_5_lat_wmr_scanout;
wire hwtw_config_6_lat_wmr_scanin;
wire hwtw_config_6_lat_wmr_scanout;
wire hwtw_config_7_lat_wmr_scanin;
wire hwtw_config_7_lat_wmr_scanout;
wire [63:0] hwtw_config_muxed;
wire [7:0] rd_hwtw_config_dec;
wire [63:0] data_1_in;
wire rng_stg1_data_scanin;
wire rng_stg1_data_scanout;
wire ctl_1_lat_scanin;
wire ctl_1_lat_scanout;
wire ctl_1;
wire asi;
wire scratchpad;
wire rd_scratchpad;
wire wr_scratchpad;
wire context;
wire p_context_0;
wire wr_p_context_0;
wire asi_50;
wire rd_asi_50;
wire immu_tag_target;
wire rd_immu_tag_target;
wire immu_tag_access;
wire rd_immu_tag_access;
wire wr_immu_tag_access;
wire range_offset;
wire rd_range_offset;
wire real_range_0;
wire real_range_1;
wire real_range_2;
wire real_range_3;
wire physical_offset_0;
wire physical_offset_1;
wire physical_offset_2;
wire physical_offset_3;
wire asi_54;
wire rd_asi_54;
wire itlb_data_in;
wire wr_itlb_data_in;
wire z_tsb_cfg_0;
wire z_tsb_cfg_1;
wire z_tsb_cfg_2;
wire z_tsb_cfg_3;
wire nz_tsb_cfg_0;
wire nz_tsb_cfg_1;
wire nz_tsb_cfg_2;
wire nz_tsb_cfg_3;
wire wr_z_tsb_cfg_0;
wire wr_z_tsb_cfg_1;
wire wr_z_tsb_cfg_2;
wire wr_z_tsb_cfg_3;
wire wr_nz_tsb_cfg_0;
wire wr_nz_tsb_cfg_1;
wire wr_nz_tsb_cfg_2;
wire wr_nz_tsb_cfg_3;
wire itsb_ptr_0;
wire itsb_ptr_1;
wire itsb_ptr_2;
wire itsb_ptr_3;
wire dtsb_ptr_0;
wire dtsb_ptr_1;
wire dtsb_ptr_2;
wire dtsb_ptr_3;
wire asi_2;
wire ctl_2;
wire [63:0] data_2;
wire asi_54_2;
wire t_p_c_2;
wire t_p_s_2;
wire rd_t_p_c_2;
wire wr_t_p_c_2;
wire rd_t_p_s_2;
wire legal_data_in_page_size;
wire wr_itlb_data_in_2;
wire wr_dtlb_data_in_2;
wire wr_itlb_data_access_2;
wire wr_dtlb_data_access_2;
wire [7:0] clear_data_in_write_;
wire [7:0] wr_tid_dec;
wire legal_tsb_cfg_page_size;
wire fast_dtsb_ptr;
wire itsb_ptr;
wire dtsb_ptr;
wire rd_tsb_ptr_1;
wire mra_diag;
wire rd_mra_parity;
wire itlb_data_access;
wire rd_itlb_data_access;
wire wr_itlb_data_access;
wire itlb_tag_read;
wire rd_itlb_tag_read;
wire immu_demap;
wire legal_i_demap;
wire wr_immu_demap;
wire dmmu_demap;
wire legal_d_demap;
wire wr_dmmu_demap;
wire asi_58;
wire rd_asi_58;
wire rd_asi_58_not_sfr;
wire dmmu_tag_target;
wire rd_dmmu_tag_target;
wire dmmu_tag_access;
wire rd_dmmu_tag_access;
wire wr_dmmu_tag_access;
wire hwtwconfig;
wire partition_id;
wire wr_partition_id;
wire sca_diag;
wire rd_sca_ecc;
wire rd_sca_data;
wire dtlb_data_in;
wire wr_dtlb_data_in;
wire dtlb_data_access;
wire rd_dtlb_data_access;
wire wr_dtlb_data_access;
wire dtlb_tag_read;
wire rd_dtlb_tag_read;
wire mmu_asi_rd_1;
wire [4:0] scp_addr;
wire wr_scratchpad_2;
wire [1:0] scp_rd_en_2;
wire rd_scratchpad_2;
wire [1:0] scp_wr_en;
wire [1:0] rd_sca_data_en_2;
wire rd_sca_data_2;
wire [1:0] rd_sca_ecc_en_2;
wire rd_sca_ecc_2;
wire scp_ctl_lat_scanin;
wire scp_ctl_lat_scanout;
wire rd_scratchpad_3;
wire rd_scratchpad_4_in;
wire check_ecc;
wire rd_scratchpad_4_lat_scanin;
wire rd_scratchpad_4_lat_scanout;
wire rd_scratchpad_4;
wire [1:0] scp_rden;
wire [1:0] mra_rd_en_1;
wire [4:0] mra_rd_addr;
wire [4:0] mra_rd_addr0;
wire [4:0] mra_rd_addr1;
wire [1:0] mra_addr_sel_rd;
wire [1:0] mra_avail;
wire [1:0] mra_addr_sel_hw_tw;
wire req_grant_in;
wire req_grant_lat_scanin;
wire req_grant_lat_scanout;
wire req_grant;
wire [4:0] mra_rd_addr_1;
wire [4:0] mra_rd_addr_0;
wire zero_context;
wire [1:1] tsb_ptr_addr;
wire [4:0] mra_addr_1;
wire mra_addr_lat_scanin;
wire mra_addr_lat_scanout;
wire [4:0] mra_addr_2;
wire [4:0] mra_addr_3;
wire [4:0] mra_addr_4;
wire [1:0] mra_rd_en;
wire [1:0] mra_to_r3_in_in;
wire [1:0] mra_to_r3_in;
wire [1:0] pmra_to_r3_in;
wire mra_rd_en_lat_scanin;
wire mra_rd_en_lat_scanout;
wire [1:0] mra_rd_en_last;
wire [1:0] pmra_to_r3;
wire [1:0] mra_wr_en_1;
wire [1:0] mra_wr_en_3_in;
wire [1:0] mra_wr_en_2;
wire mra_sel_tsb_cfg_2;
wire mra_sel_tsb_cfg_0_2_2;
wire mra_sel_tsb_cfg_1_3_2;
wire mra_wr_en_lat_scanin;
wire mra_wr_en_lat_scanout;
wire [1:0] mra_wr_en_3;
wire mra_wr_en_4_lat_scanin;
wire mra_wr_en_4_lat_scanout;
wire [1:0] mra_wr_en_4;
wire [1:0] mra_wr_en_out;
wire mra_uecc_4;
wire mra_sel_tsb_cfg_0_2_1;
wire mra_sel_tsb_cfg_1_3_1;
wire mra_sel_real_range_1;
wire mra_sel_physical_offset_1;
wire mra_sel_lat_scanin;
wire mra_sel_lat_scanout;
wire mra_sel_real_range_2;
wire mra_sel_physical_offset_2;
wire mra_sel_tsb_cfg_0_2_3;
wire mra_sel_tsb_cfg_1_3_3;
wire mra_sel_real_range_3;
wire mra_sel_physical_offset_3;
wire rd_tsb_cfg_3;
wire demap_context_2;
wire [7:0] rd_tid_dec;
wire [63:0] dtlb0_tte_tag;
wire [63:0] dtlb1_tte_tag;
wire [63:0] scp0_ecc_bus;
wire [63:0] scp1_ecc_bus;
wire [63:0] mbist_scp0_0;
wire [63:0] mbist_scp0_1;
wire [63:0] mbist_scp0_2;
wire [63:0] mbist_scp1_0;
wire [63:0] mbist_scp1_1;
wire [63:0] mbist_scp1_2;
wire sel_data_1;
wire [1:0] use_dtlb_window;
wire [1:0] asd_asi_sel;
wire rd_hwtw_config_2;
wire asd_asi_rd_2;
wire asd_asi_rd_1;
wire [63:0] data_2_in;
wire [63:0] rd_t_p_c_data;
wire [63:0] rd_t_p_s_data;
wire stg2_data_lat_scanin;
wire stg2_data_lat_scanout;
wire stg2_ctl_lat_scanin;
wire stg2_ctl_lat_scanout;
wire mmu_asi_rd_2;
wire rd_tsb_ptr_2;
wire rd_mra_parity_2;
wire wr_immu_tag_access_2;
wire wr_immu_demap_2;
wire wr_dmmu_tag_access_2;
wire wr_dmmu_demap_2;
wire wr_p_context_0_2;
wire wr_partition_id_2;
wire hwtwconfig_2;
wire [7:0] a_wr_immu_tag_access;
wire [7:0] a_wr_itlb_data_in;
wire [7:0] a_wr_itlb_data_access;
wire [7:0] a_wr_immu_demap;
wire [7:0] a_wr_dmmu_tag_access;
wire [7:0] a_wr_dtlb_data_in;
wire [7:0] a_wr_dtlb_data_access;
wire [7:0] a_wr_dmmu_demap;
wire suppress_write_2;
wire dae_req_lat_scanin;
wire dae_req_lat_scanout;
wire suppress_write_3;
wire [64:0] data_3;
wire check_ecc_in;
wire check_ecc_lat_scanin;
wire check_ecc_lat_scanout;
wire [1:0] pmra_to_r4_in;
wire pmra_to_r4_lat_scanin;
wire pmra_to_r4_lat_scanout;
wire [1:0] pmra_to_r4;
wire cecc_4;
wire uecc_4;
wire tid_4_lat_scanin;
wire tid_4_lat_scanout;
wire [2:0] tid_4;
wire sca_index_lat_scanin;
wire sca_index_lat_scanout;
wire [2:0] sca_index;
wire [64:0] rngf_cdbus_2;
wire [64:0] mra_data;
wire [64:0] mra_tsb_cfg;
wire tsb_hwtw_en_3;
wire [64:0] mra_parity;
wire [64:0] dtlb0_tte_data;
wire [64:0] dtlb1_tte_data;
wire [64:0] tsb_ptr_data;
wire mra_to_r3;
wire mra_not_tsb_cfg;
wire rd_mra_parity_3;
wire rd_tsb_ptr_3;
wire mra_sel_tsb_cfg;
wire sel_cdbus_2;
wire [64:0] data_3_in;
wire rng_stg3_scanin;
wire rng_stg3_scanout;
wire ctl_3;
wire stg3_ctl_lat_scanin;
wire stg3_ctl_lat_scanout;
wire mmu_asi_rd_3;
wire asi_read_lat_scanin;
wire asi_read_lat_scanout;
wire asi_read_in;
wire asi_read;
wire dtlb_window_used;
wire dtlb_window_used_last;
wire idata_in_data_access;
wire ddata_in_data_access;
wire [7:0] rd_itte_in;
wire [7:0] rd_itte;
wire [7:0] rd_dtte_in;
wire [7:0] wrote_dtlb_in;
wire sel_rd_dtte_hwtw_in;
wire [7:0] rd_dtte_hwtw_in;
wire rd_tte_lat_scanin;
wire rd_tte_lat_scanout;
wire sel_rd_dtte_hwtw;
wire idata_in_data_access_2_lat_scanin;
wire idata_in_data_access_2_lat_scanout;
wire idata_in_data_access_2;
wire [7:0] rd_dtte;
wire [1:0] dtlb_window;
wire [7:0] rd_itte_last_in;
wire [7:0] rd_itte_last_last_in;
wire [7:0] rd_itte_last;
wire [7:0] rd_itte_data_in;
wire [7:0] rd_itte_last_last;
wire [7:0] rd_itte_tag_in;
wire [7:0] rd_itte_data;
wire rd_itte_lat_scanin;
wire rd_itte_lat_scanout;
wire [7:0] prd_itte_last;
wire [7:0] rd_itte_tag;
wire dtlb_window_used_last_lat_scanin;
wire dtlb_window_used_last_lat_scanout;
wire wrote_dtlb_tg1_lat_scanin;
wire wrote_dtlb_tg1_lat_scanout;
wire [7:0] wrote_dtlb;
wire wrote_dtlb_tg0_lat_scanin;
wire wrote_dtlb_tg0_lat_scanout;
wire [7:0] reload_done_in;
wire reload_done_tg1_lat_scanin;
wire reload_done_tg1_lat_scanout;
wire [7:0] reload_done;
wire reload_done_tg0_lat_scanin;
wire reload_done_tg0_lat_scanout;
wire dtlb_reload_stall_in;
wire dtlb_reload;
wire dtlb_reload_stall_lat_scanin;
wire dtlb_reload_stall_lat_scanout;
wire dtlb_reload_stall;
wire dtlb_reload_in;
wire dtlb_reload_lat_scanin;
wire dtlb_reload_lat_scanout;
wire [3:0] wr_tsb_cfg_enc;
wire wr_tsb_cfg_lat_scanin;
wire wr_tsb_cfg_lat_scanout;
wire [3:0] wr_tsb_cfg_enc_2;
wire [3:0] wr_tsb_cfg_enc_3;
wire [3:0] wr_tsb_cfg_enc_4;
wire wr_z_tsb_cfg_3_4;
wire wr_z_tsb_cfg_2_4;
wire wr_z_tsb_cfg_1_4;
wire wr_z_tsb_cfg_0_4;
wire wr_nz_tsb_cfg_3_4;
wire wr_nz_tsb_cfg_2_4;
wire wr_nz_tsb_cfg_1_4;
wire wr_nz_tsb_cfg_0_4;
wire [7:0] tid_dec_4;
wire [3:0] t7_e_z_in;
wire [3:0] t7_e_z;
wire [3:0] t7_e_nz_in;
wire [3:0] t7_e_nz;
wire [3:0] t6_e_z_in;
wire [3:0] t6_e_z;
wire [3:0] t6_e_nz_in;
wire [3:0] t6_e_nz;
wire [3:0] t5_e_z_in;
wire [3:0] t5_e_z;
wire [3:0] t5_e_nz_in;
wire [3:0] t5_e_nz;
wire [3:0] t4_e_z_in;
wire [3:0] t4_e_z;
wire [3:0] t4_e_nz_in;
wire [3:0] t4_e_nz;
wire [3:0] t3_e_z_in;
wire [3:0] t3_e_z;
wire [3:0] t3_e_nz_in;
wire [3:0] t3_e_nz;
wire [3:0] t2_e_z_in;
wire [3:0] t2_e_z;
wire [3:0] t2_e_nz_in;
wire [3:0] t2_e_nz;
wire [3:0] t1_e_z_in;
wire [3:0] t1_e_z;
wire [3:0] t1_e_nz_in;
wire [3:0] t1_e_nz;
wire [3:0] t0_e_z_in;
wire [3:0] t0_e_z;
wire [3:0] t0_e_nz_in;
wire [3:0] t0_e_nz;
wire hw_tw_e_lat_wmr_scanin;
wire hw_tw_e_lat_wmr_scanout;
wire [7:0] hwtw_enables;
wire tsb_hwtw_en_1;
wire tsb_hwtw_en_lat_scanin;
wire tsb_hwtw_en_lat_scanout;
wire tsb_hwtw_en_2;
wire htc_mra_addr_lat_scanin;
wire htc_mra_addr_lat_scanout;
wire [4:0] htc_mra_addr;
wire [3:0] htc_tid_dec;
wire [7:0] htc_enables_1_2;
wire [7:0] htc_enables_0_2;
wire [3:0] htc_sel_tsb_cfg;
wire [1:0] htc_hwtw_en_1_2;
wire [1:0] htc_hwtw_en_0_2;
wire [6:0] index_in;
wire data_access_index_lat_scanin;
wire data_access_index_lat_scanout;
wire error_inject_lat_scanin;
wire error_inject_lat_scanout;
wire error_enable;
wire error_scau;
wire error_mrau;
wire [7:0] error_mask;
wire tag_access_tid_0_lat_scanin;
wire tag_access_tid_0_lat_scanout;
wire [1:0] tag_access_tid_0;
wire i_tag_access_0_lat_scanin;
wire i_tag_access_0_lat_scanout;
wire i_tag_access_0;
wire d_tag_access_0_lat_scanin;
wire d_tag_access_0_lat_scanout;
wire d_tag_access_0;
wire tag_access_tid_1_lat_scanin;
wire tag_access_tid_1_lat_scanout;
wire [1:0] tag_access_tid_1;
wire i_tag_access_1_lat_scanin;
wire i_tag_access_1_lat_scanout;
wire i_tag_access_1;
wire d_tag_access_1_lat_scanin;
wire d_tag_access_1_lat_scanout;
wire d_tag_access_1;
wire [7:0] i_tag_access_exc;
wire [7:0] d_tag_access_exc;
wire [7:0] write_stp;
wire [7:0] stp_in;
wire [7:0] stp;
wire stp_lat_scanin;
wire stp_lat_scanout;
wire [7:0] set_htp;
wire [7:0] clr_htp;
wire [7:0] htp_in;
wire [7:0] htp;
wire htp_lat_scanin;
wire htp_lat_scanout;
wire spares_scanin;
wire spares_scanout;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

// Power management
input	[7:0] htc_itlb_clken;
input	[7:0] htc_dtlb_clken;
input		lsu_asi_clken;
input		lsu_mmu_pmen;
input	[1:0]	tlu_tag_access_tid_0_b;	// Tag access power management
input		tlu_i_tag_access_0_b;	// Tag access power management
input		tlu_d_tag_access_0_b;	// Tag access power management
input	[1:0]	tlu_tag_access_tid_1_b;	// Tag access power management
input		tlu_i_tag_access_1_b;	// Tag access power management
input		tlu_d_tag_access_1_b;	// Tag access power management

// MBIST
input		mbi_mra0_write_en;	// MBIST write control
input		mbi_mra1_write_en;	// MBIST write control
input		mbi_scp0_write_en;	// MBIST write control
input		mbi_scp1_write_en;	// MBIST write control
input	[4:0]	mbi_addr;		// 32 entry addressability for MBIST
input		mbi_run;		// Select MBIST controls
input	[7:0]	mbi_wdata;		// MBIST write data
input		mbi_mra0_read_en;	// MBIST read control
input		mbi_mra1_read_en;	// MBIST read control
input		mbi_scp0_read_en;	// MBIST read control
input		mbi_scp1_read_en;	// MBIST read control
input	[1:0]	mbi_mmu_cmpsel;		// Mux (DEC) between 32 bit chunks
input		mbd_compare;		// MBIST compare result

input		error_inject_enable;
input		error_inject_mrau;
input		error_inject_scau;
input	[7:0]	error_inject_mask;

input 	[64:0]	lsu_rngf_cdbus; 	// control/data bus from lsu

input 	[7:0]	tlu_iht_request;	// ITLB hardware tablewalk request
input 	[7:0]	tlu_dht_request;	// DTLB hardware tablewalk request
input 	[7:0]	tlu_release_tte;	// TTE write has been transmitted
input	[7:0]	tlu_ceter_pscce;

input	[63:0]	scp0_data;
input	[63:0]	scp1_data;
input	[7:0]	scp0_ecc;
input	[7:0]	scp1_ecc;
input		sel_scac;		// Correctable error on scratchpad
input		sel_scau;		// Uncorrectable error on scratchpad

input	[63:0]	ase_mra_rd_data;
input	[1:0]	mel0_parity;
input	[1:0]	mel1_parity;
input 		mel0_parity_err;
input 		mel1_parity_err;

input	[63:0]	asd0_asi_rd_data;
input	[63:0]	asd1_asi_rd_data;
input 	[47:0]	asd0_dtte_tag;
input 	[47:0]	asd1_dtte_tag;
input 	[54:0]	asd0_dtte_data;
input 	[54:0]	asd1_dtte_data;
input 	[6:0]	asd0_itte_index;	// Flop and send to IFU
input 	[6:0]	asd1_itte_index;	// Flop and send to IFU

input 		asd0_asi_zero_context;
input 		asd1_asi_zero_context;

input	[39:4]	htd_tsbptr;

input	[4:0]	htc_mra_addr_in;
input 	[1:0]	htc_mra_rd_en;

input	[7:0]	htc_wr_itlb_data_in;
input	[7:0]	htc_wr_dtlb_data_in;
input	[7:0]	mmu_i_unauth_access;
input	[7:0]	mmu_i_tsb_miss;
input	[7:0]	mmu_d_tsb_miss;
input	[7:0]	mmu_i_tte_outofrange;
input	[7:0]	mmu_d_tte_outofrange;
input	[7:0]	mmu_i_eccerr;		// HW TW had MRA or L2 error on I rld
input	[7:0]	mmu_d_eccerr;		// HW TW had MRA or L2 error on D rld


output		scan_out;
output		wmr_scan_out;

output		asi_error_scau;
output		asi_error_mrau;
output	[7:0]	asi_error_mask;

output	[4:0]	asi_scp_addr;
output	[1:0]	asi_scp_wr_en;
output	[1:0]	asi_scp_rd_en;
output		asi_rd_scp0;

output	[4:0]	asi_mra_rd_addr_0;	// For reads (flops now in array)
output	[4:0]	asi_mra_rd_addr_1;	// For reads (flops now in array)
output	[1:0]	asi_mra_rd_en;		//           (flops now in array)
output	[4:0]	asi_mra_wr_addr;
output	[1:0]	asi_mra_wr_en;
output	[1:0]	asi_mra_rd_en_last;	// to capture read data for rd-modify-wr
output		asi_rd_tsb_cfg_0_2;
output		asi_rd_tsb_cfg_1_3;
output		asi_rd_tsb_ptr_;
output		asi_rd_real_range;
output		asi_rd_physical_offset;
output		asi_sel_mra_0_in;	// Active in cycle 2
output		asi_mra_wr_en_next;	// Power management for rd-mod-wr flops

output	[7:0]	asi_rd_immu_tag_target;
output	[7:0]	asi_rd_immu_tag_access;
output	[7:0]	asi_rd_dmmu_tag_target;
output	[7:0]	asi_rd_dmmu_tag_access;
output	[1:0]	asi_rd_i_access_target;
output	[1:0]	asi_rd_d_access_target;
output	[1:0]	asi_rd_access_target;
output 	[7:0]	asi_rd_itte_tag;
output 	[7:0]	asi_rd_itte_data;
output 	[6:0]	asi_rd_dtte;

output	[7:0]	asi_wr_immu_tag_access;
output	[7:0]	asi_wr_itlb_data_in;
output	[7:0]	asi_wr_itlb_data_access;
output	[7:0]	asi_wr_immu_demap;
output	[7:0]	asi_wr_immu_demap_p;
output	[7:0]	asi_wr_immu_demap_n;
output	[7:0]	asi_wr_dmmu_tag_access;
output	[7:0]	asi_wr_dtlb_data_in;
output	[7:0]	asi_wr_dtlb_data_access;
output	[7:0]	asi_wr_partition_id;
output	[7:0]	asi_wr_dmmu_demap;
output	[7:0]	asi_wr_dmmu_demap_p;
output	[7:0]	asi_wr_dmmu_demap_s_n;
output		asi_dmmu_demap_s;
output	[7:0]	asi_wr_p_context_0;
output	[1:0]	asi_p_context_0_en;

output	[2:0]	asi_tag_access_sel;
output		asi_tsb_ptr_req_valid;
output	[2:0] asi_tsb_ptr_req;	// HW TW: which thread gets tag access
output	[1:0] asi_tsb_ptr_number;	// HW TW: which config reg to use

output	[1:0]	asi_tsb_hwtw_enable_0;	// TSB_CFG[63]; same timing as MRA output
output	[1:0]	asi_tsb_hwtw_enable_1;	// TSB_CFG[63]; same timing as MRA output
output 		asi_data_in_real;

output	[63:0] asi_seg_wr_data;
output	[63:0] asi_wr_data;
output	[63:0] asi_mra_wr_data;
output		asi_mra_req_grant;	// Hardware tablewalk request granted

output 		asi_demap_r_bit;

output	[63:0]	asi_rd_data;

output	[1:0]	asi_hwtw_config_0;
output	[1:0]	asi_hwtw_config_1;
output	[1:0]	asi_hwtw_config_2;
output	[1:0]	asi_hwtw_config_3;
output	[1:0]	asi_hwtw_config_4;
output	[1:0]	asi_hwtw_config_5;
output	[1:0]	asi_hwtw_config_6;
output	[1:0]	asi_hwtw_config_7;

output		asi_sel_en;		// Clock enable for scratchpad ECC check
output	[7:0] asi_i_tag_access_en;
output	[7:0] asi_d_tag_access_en;
output	[7:0] asi_i_data_in_en;
output	[7:0] asi_d_data_in_en;

output	[7:0]	asi_mbist_wdata;	// MBIST
output	[7:0]	asi_ase_compare_data;	// MBIST
output	[7:0]	asi_compare_data;	// MBIST
output	[31:0]	asi_mbd_scp_data;	// MBIST
output		asi_mbd_sel_scp;	// MBIST
output	[7:0]	asi_mbist_ecc_in;	// MBIST
output	[3:2]	asi_mbist_ecc;		// MBIST
output		asi_mbist_run;		// MBIST
output		asi_ecc_cmpsel_in;	// MBIST
output	[1:0]	asi_ase_cmpsel_in;	// MBIST

output	[64:0]	mmu_asi_data;		// ASI read data for fast bus (to TLU)
output		mmu_asi_read;		// Valid for MMU ASI read

output 	[7:0]	mmu_write_itlb;

output 		mmu_dtlb_reload_stall;
output 		mmu_dtlb_reload;

output 	[7:0]	mmu_hw_tw_enable;

output 		mmu_asi_cecc; 		// Correctable ECC error on ASI read
output 		mmu_asi_uecc; 		// Uncorrectable ECC error on ASI read
output	[2:0]	mmu_asi_tid;		// Thread for reported error
output	[2:0]	mmu_asi_index;		// Index of the failure (rest is TID)
output		mmu_asi_mra_not_sca;	// 1: MRA error 0: Scratchpad error

output		mmu_dae_req;		// data_access_exception for bad pg size
output	[2:0]	mmu_dae_tid;		

output 	[7:0]	mmu_reload_done;

output	[6:0]	mmu_index;		// Index and valid from idata_access

output		mmu_mbi_mra0_fail;	// MBIST
output		mmu_mbi_mra1_fail;	// MBIST
output		mmu_mbi_scp0_fail;	// MBIST
output		mmu_mbi_scp1_fail;	// MBIST


//////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;


mmu_asi_ctl_l1clkhdr_ctl_macro free_clken (
	.l2clk(l2clk),
	.l1en (1'b1 ),
	.l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


//////////////////////////////////////////////////////////////////////////////
// Power management

assign stg1_en_in =
       lsu_asi_clken;

mmu_asi_ctl_msff_ctl_macro__width_1 stg1_en_lat  (
	.scan_in(stg1_en_lat_scanin),
	.scan_out(stg1_en_lat_scanout),
	.din	(stg1_en_in			),
	.dout	(stg1_en			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign stg2_en_in =
       (lsu_rngf_cdbus[64] & lsu_rngf_cdbus[63]) | 
       (~lsu_rngf_cdbus[64] & stg2_en) |
       mbist_run |
       ~lsu_mmu_pmen;

mmu_asi_ctl_msff_ctl_macro__width_1 stg2_en_lat  (
	.scan_in(stg2_en_lat_scanin),
	.scan_out(stg2_en_lat_scanout),
	.din	(stg2_en_in			),
	.dout	(pstg2_en			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign stg2_en =
       | {pstg2_en, prd_itte[7:0], prd_dtte[7:0], rd_dtte_hwtw[7:0]};

mmu_asi_ctl_msff_ctl_macro__width_1 stg3_en_lat  (
	.scan_in(stg3_en_lat_scanin),
	.scan_out(stg3_en_lat_scanout),
	.din	(stg2_en			),
	.dout	(stg3_en			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 stg4_en_lat  (
	.scan_in(stg4_en_lat_scanin),
	.scan_out(stg4_en_lat_scanout),
	.din	(stg3_en			),
	.dout	(stg4_en			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign stg1_4_en =
       stg1_en | stg2_en | stg3_en | stg4_en;

mmu_asi_ctl_l1clkhdr_ctl_macro stg1_4_clken (
	.l2clk	(l2clk				),
	.l1en	(stg1_4_en			),
	.l1clk	(l1clk_pm1			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


assign pm2_en =
       mbist_run | ~lsu_mmu_pmen;

mmu_asi_ctl_l1clkhdr_ctl_macro mbist_clken (
	.l2clk	(l2clk				),
	.l1en	(pm2_en				),
	.l1clk	(l1clk_pm2			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


//////////////////////////////////////////////////////////////////////////////
// MBIST

// Note:  mbist_run is used to control power management,
// so do not power manage this flop
mmu_asi_ctl_msff_ctl_macro__width_1 mbist_run_lat  (					
	.scan_in(mbist_run_lat_scanin),
	.scan_out(mbist_run_lat_scanout),
	.din	(mbi_run			),
	.dout	(mbist_run			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra0_wr_en_lat  (
	.scan_in(mra0_wr_en_lat_scanin),
	.scan_out(mra0_wr_en_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_mra0_write_en		),
	.dout	(mbist_mra0_wr_en		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra1_wr_en_lat  (
	.scan_in(mra1_wr_en_lat_scanin),
	.scan_out(mra1_wr_en_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_mra1_write_en		),
	.dout	(mbist_mra1_wr_en		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp0_wr_en_lat  (
	.scan_in(scp0_wr_en_lat_scanin),
	.scan_out(scp0_wr_en_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_scp0_write_en		),
	.dout	(mbist_scp0_wr_en		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp1_wr_en_lat  (
	.scan_in(scp1_wr_en_lat_scanin),
	.scan_out(scp1_wr_en_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_scp1_write_en		),
	.dout	(mbist_scp1_wr_en		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_5 mbist_addr_lat  (
	.scan_in(mbist_addr_lat_scanin),
	.scan_out(mbist_addr_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_addr		[4:0]	),
	.dout	(mbist_addr		[4:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_8 mbist_wdata_lat  (
	.scan_in(mbist_wdata_lat_scanin),
	.scan_out(mbist_wdata_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_wdata		[7:0]	),
	.dout	(mbist_wdata		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra0_rd_en_lat  (
	.scan_in(mra0_rd_en_lat_scanin),
	.scan_out(mra0_rd_en_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_mra0_read_en		),
	.dout	(mbist_mra0_rd_en		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra1_rd_en_lat  (
	.scan_in(mra1_rd_en_lat_scanin),
	.scan_out(mra1_rd_en_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_mra1_read_en		),
	.dout	(mbist_mra1_rd_en		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp0_rd_en_lat  (
	.scan_in(scp0_rd_en_lat_scanin),
	.scan_out(scp0_rd_en_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_scp0_read_en		),
	.dout	(mbist_scp0_rd_en		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp1_rd_en_lat  (
	.scan_in(scp1_rd_en_lat_scanin),
	.scan_out(scp1_rd_en_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_scp1_read_en		),
	.dout	(mbist_scp1_rd_en		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_2 mbist_cmpsel_lat  (
	.scan_in(mbist_cmpsel_lat_scanin),
	.scan_out(mbist_cmpsel_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_mmu_cmpsel		[1:0]	),
	.dout	(mbist_cmpsel		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign mbist_wr_data[63:0] =
       {8 {mbist_wdata[7:0]}};

assign asi_mbist_wdata[7:0] =
       mbist_wdata[7:0];

assign asi_mbist_ecc_in[7:0] =
       mbist_wdata[7:0] & {8 {mbist_run}};

assign asi_mbist_ecc[3:2] =
       mbist_wdata_2[3:2] & {2 {mbist_run}};

assign asi_mbist_run =
       mbist_run;


mmu_asi_ctl_msff_ctl_macro__width_1 mra0_wr_en_2_lat  (
	.scan_in(mra0_wr_en_2_lat_scanin),
	.scan_out(mra0_wr_en_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_mra0_wr_en		),
	.dout	(mbist_mra0_wr_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra1_wr_en_2_lat  (
	.scan_in(mra1_wr_en_2_lat_scanin),
	.scan_out(mra1_wr_en_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_mra1_wr_en		),
	.dout	(mbist_mra1_wr_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra0_rd_en_2_lat  (
	.scan_in(mra0_rd_en_2_lat_scanin),
	.scan_out(mra0_rd_en_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_mra0_rd_en		),
	.dout	(mbist_mra0_rd_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra1_rd_en_2_lat  (
	.scan_in(mra1_rd_en_2_lat_scanin),
	.scan_out(mra1_rd_en_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_mra1_rd_en		),
	.dout	(mbist_mra1_rd_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp0_rd_en_2_lat  (
	.scan_in(scp0_rd_en_2_lat_scanin),
	.scan_out(scp0_rd_en_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_scp0_rd_en		),
	.dout	(mbist_scp0_rd_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp1_rd_en_2_lat  (
	.scan_in(scp1_rd_en_2_lat_scanin),
	.scan_out(scp1_rd_en_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_scp1_rd_en		),
	.dout	(mbist_scp1_rd_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_5 mbist_addr_2_lat  (
	.scan_in(mbist_addr_2_lat_scanin),
	.scan_out(mbist_addr_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_addr		[4:0]	),
	.dout	(mbist_addr_2		[4:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_2 mbist_cmpsel_2_lat  (
	.scan_in(mbist_cmpsel_2_lat_scanin),
	.scan_out(mbist_cmpsel_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_cmpsel		[1:0]	),
	.dout	(mbist_cmpsel_2		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_24 mbist_compare_data_lat  (
	.scan_in(mbist_compare_data_lat_scanin),
	.scan_out(mbist_compare_data_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	({mbist_wdata		[7:0],
		  mbist_wdata_2		[7:0],
		  compare_data_in	[7:0]}),
	.dout	({mbist_wdata_2  	[7:0],
		  mbist_wdata_3		[7:0],
		  compare_data		[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign mbist_mra_rd_en_3 =
       mbist_mra0_rd_en_3 | mbist_mra1_rd_en_3;

assign compare_data_in[7:0] =
       (mbist_wdata_2[7:0] & {8 {~mbist_mra_rd_en_3}}) |
       (mbist_wdata_3[7:0] & {8 { mbist_mra_rd_en_3}}) ;

assign asi_ase_compare_data[7:0] =
       compare_data_in[7:0];

assign asi_compare_data[7:0] =
       compare_data[7:0];

assign mbist_scp0_0_rd_en =
       mbist_scp0_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b00);
assign mbist_scp0_1_rd_en =
       mbist_scp0_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b01);
assign mbist_scp0_2_rd_en =
       mbist_scp0_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b10);
assign mbist_scp1_0_rd_en =
       mbist_scp1_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b00);
assign mbist_scp1_1_rd_en =
       mbist_scp1_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b01);
assign mbist_scp1_2_rd_en =
       mbist_scp1_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b10);

assign asi_ase_cmpsel_in[1:0] =
       mbist_cmpsel_2[1:0];


mmu_asi_ctl_msff_ctl_macro__width_1 mra0_rd_en_3_lat  (
	.scan_in(mra0_rd_en_3_lat_scanin),
	.scan_out(mra0_rd_en_3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_mra0_rd_en_2		),
	.dout	(mbist_mra0_rd_en_3		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra1_rd_en_3_lat  (
	.scan_in(mra1_rd_en_3_lat_scanin),
	.scan_out(mra1_rd_en_3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_mra1_rd_en_2		),
	.dout	(mbist_mra1_rd_en_3		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp0_rd_en_3_lat  (
	.scan_in(scp0_rd_en_3_lat_scanin),
	.scan_out(scp0_rd_en_3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_scp0_rd_en_2		),
	.dout	(mbist_scp0_rd_en_3		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp1_rd_en_3_lat  (
	.scan_in(scp1_rd_en_3_lat_scanin),
	.scan_out(scp1_rd_en_3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_scp1_rd_en_2		),
	.dout	(mbist_scp1_rd_en_3		),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mbd_sel_scp =
       mbist_scp0_rd_en_3 | mbist_scp1_rd_en_3;

mmu_asi_ctl_msff_ctl_macro__width_1 mra0_rd_en_4_lat  (
	.scan_in(mra0_rd_en_4_lat_scanin),
	.scan_out(mra0_rd_en_4_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_mra0_rd_en_3		),
	.dout	(mbist_mra0_rd_en_4		),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra1_rd_en_4_lat  (
	.scan_in(mra1_rd_en_4_lat_scanin),
	.scan_out(mra1_rd_en_4_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_mra1_rd_en_3		),
	.dout	(mbist_mra1_rd_en_4		),
  .siclk(siclk),
  .soclk(soclk)
);

assign mra0_fail_in =
       ~mbd_compare & mbist_mra0_rd_en_4;
assign mra1_fail_in =
       ~mbd_compare & mbist_mra1_rd_en_4;
assign scp0_fail_in =
       ~mbd_compare & mbist_scp0_rd_en_3;
assign scp1_fail_in =
       ~mbd_compare & mbist_scp1_rd_en_3;
// Generate select for MRA ECC muxing for MBIST
assign asi_ecc_cmpsel_in =
       mbist_mra0_rd_en_3;

mmu_asi_ctl_msff_ctl_macro__width_1 mra0_fail_lat  (
	.scan_in(mra0_fail_lat_scanin),
	.scan_out(mra0_fail_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mra0_fail_in			),
	.dout	(mra0_fail			),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 mra1_fail_lat  (
	.scan_in(mra1_fail_lat_scanin),
	.scan_out(mra1_fail_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mra1_fail_in			),
	.dout	(mra1_fail			),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp0_fail_lat  (
	.scan_in(scp0_fail_lat_scanin),
	.scan_out(scp0_fail_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(scp0_fail_in			),
	.dout	(scp0_fail			),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 scp1_fail_lat  (
	.scan_in(scp1_fail_lat_scanin),
	.scan_out(scp1_fail_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(scp1_fail_in			),
	.dout	(scp1_fail			),
  .siclk(siclk),
  .soclk(soclk)
);


assign mmu_mbi_mra0_fail =
       mra0_fail;
assign mmu_mbi_mra1_fail =
       mra1_fail;
assign mmu_mbi_scp0_fail =
       scp0_fail;
assign mmu_mbi_scp1_fail =
       scp1_fail;


//////////////////////////////////////////////////////////////////////////////
// HW TW config

assign hwtw_config_0_in[1:0] =
       ({2 { wr_hwtw_config_dec[0]}} & data_1		[1:0]) |
       ({2 {~wr_hwtw_config_dec[0]}} & hwtw_config_0	[1:0]) ;
assign hwtw_config_1_in[1:0] =
       ({2 { wr_hwtw_config_dec[1]}} & data_1		[1:0]) |
       ({2 {~wr_hwtw_config_dec[1]}} & hwtw_config_1	[1:0]) ;
assign hwtw_config_2_in[1:0] =
       ({2 { wr_hwtw_config_dec[2]}} & data_1		[1:0]) |
       ({2 {~wr_hwtw_config_dec[2]}} & hwtw_config_2	[1:0]) ;
assign hwtw_config_3_in[1:0] =
       ({2 { wr_hwtw_config_dec[3]}} & data_1		[1:0]) |
       ({2 {~wr_hwtw_config_dec[3]}} & hwtw_config_3	[1:0]) ;
assign hwtw_config_4_in[1:0] =
       ({2 { wr_hwtw_config_dec[4]}} & data_1		[1:0]) |
       ({2 {~wr_hwtw_config_dec[4]}} & hwtw_config_4	[1:0]) ;
assign hwtw_config_5_in[1:0] =
       ({2 { wr_hwtw_config_dec[5]}} & data_1		[1:0]) |
       ({2 {~wr_hwtw_config_dec[5]}} & hwtw_config_5	[1:0]) ;
assign hwtw_config_6_in[1:0] =
       ({2 { wr_hwtw_config_dec[6]}} & data_1		[1:0]) |
       ({2 {~wr_hwtw_config_dec[6]}} & hwtw_config_6	[1:0]) ;
assign hwtw_config_7_in[1:0] =
       ({2 { wr_hwtw_config_dec[7]}} & data_1		[1:0]) |
       ({2 {~wr_hwtw_config_dec[7]}} & hwtw_config_7	[1:0]) ;

mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_0_lat  ( // FS:wmr_protect
	.scan_in(hwtw_config_0_lat_wmr_scanin),
	.scan_out(hwtw_config_0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(hwtw_config_0_in	[1:0]	),
	.dout	(hwtw_config_0		[1:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_1_lat  ( // FS:wmr_protect
	.scan_in(hwtw_config_1_lat_wmr_scanin),
	.scan_out(hwtw_config_1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(hwtw_config_1_in	[1:0]	),
	.dout	(hwtw_config_1		[1:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_2_lat  ( // FS:wmr_protect
	.scan_in(hwtw_config_2_lat_wmr_scanin),
	.scan_out(hwtw_config_2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(hwtw_config_2_in	[1:0]	),
	.dout	(hwtw_config_2		[1:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_3_lat  ( // FS:wmr_protect
	.scan_in(hwtw_config_3_lat_wmr_scanin),
	.scan_out(hwtw_config_3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(hwtw_config_3_in	[1:0]	),
	.dout	(hwtw_config_3		[1:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_4_lat  ( // FS:wmr_protect
	.scan_in(hwtw_config_4_lat_wmr_scanin),
	.scan_out(hwtw_config_4_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(hwtw_config_4_in	[1:0]	),
	.dout	(hwtw_config_4		[1:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_5_lat  ( // FS:wmr_protect
	.scan_in(hwtw_config_5_lat_wmr_scanin),
	.scan_out(hwtw_config_5_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(hwtw_config_5_in	[1:0]	),
	.dout	(hwtw_config_5		[1:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_6_lat  ( // FS:wmr_protect
	.scan_in(hwtw_config_6_lat_wmr_scanin),
	.scan_out(hwtw_config_6_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(hwtw_config_6_in	[1:0]	),
	.dout	(hwtw_config_6		[1:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_7_lat  ( // FS:wmr_protect
	.scan_in(hwtw_config_7_lat_wmr_scanin),
	.scan_out(hwtw_config_7_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(hwtw_config_7_in	[1:0]	),
	.dout	(hwtw_config_7		[1:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

assign asi_hwtw_config_0[1:0] =
       hwtw_config_0[1:0];
assign asi_hwtw_config_1[1:0] =
       hwtw_config_1[1:0];
assign asi_hwtw_config_2[1:0] =
       hwtw_config_2[1:0];
assign asi_hwtw_config_3[1:0] =
       hwtw_config_3[1:0];
assign asi_hwtw_config_4[1:0] =
       hwtw_config_4[1:0];
assign asi_hwtw_config_5[1:0] =
       hwtw_config_5[1:0];
assign asi_hwtw_config_6[1:0] =
       hwtw_config_6[1:0];
assign asi_hwtw_config_7[1:0] =
       hwtw_config_7[1:0];

assign hwtw_config_muxed[63:2] =
       {62 {1'b0}};
assign hwtw_config_muxed[1:0] =
       ({2 {rd_hwtw_config_dec[0]}} & hwtw_config_0[1:0]) |
       ({2 {rd_hwtw_config_dec[1]}} & hwtw_config_1[1:0]) |
       ({2 {rd_hwtw_config_dec[2]}} & hwtw_config_2[1:0]) |
       ({2 {rd_hwtw_config_dec[3]}} & hwtw_config_3[1:0]) |
       ({2 {rd_hwtw_config_dec[4]}} & hwtw_config_4[1:0]) |
       ({2 {rd_hwtw_config_dec[5]}} & hwtw_config_5[1:0]) |
       ({2 {rd_hwtw_config_dec[6]}} & hwtw_config_6[1:0]) |
       ({2 {rd_hwtw_config_dec[7]}} & hwtw_config_7[1:0]) ;

//////////////////////////////////////////////////////////////////////////////
//STAGE 0

assign data_1_in[63:0] =
       lsu_rngf_cdbus[63:0];


/////////////////////////////////////////////////////////////////////
//STAGE 1
/////////////////////////////////////////////////////////////////////
// Stage the packet coming on the ring

mmu_asi_ctl_msff_ctl_macro__width_64 rng_stg1_data  (
	.scan_in(rng_stg1_data_scanin),
	.scan_out(rng_stg1_data_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(data_1_in		[63:0]	), 
	.dout	(data_1			[63:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// register control bit, bit 64 indicates whether ctl packet or data packet
mmu_asi_ctl_msff_ctl_macro__width_1 ctl_1_lat  (
	.scan_in(ctl_1_lat_scanin),
	.scan_out(ctl_1_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(lsu_rngf_cdbus		[64   ]	),
	.dout	(ctl_1				),
  .siclk(siclk),
  .soclk(soclk)
);

// decode the packet

assign asi = 
	ctl_1 & data_1[63] & ~data_1[62] & (data_1[61:60] == 2'b00);


// Scratchpad address is data_1[05:03] for regs 0 to 7
assign scratchpad =
       asi & ((data_1[55:48] == 8'h20) | (data_1[55:48] == 8'h4F)) ;
assign rd_scratchpad = 
       scratchpad &  data_1[59];
assign wr_scratchpad = 	       
       scratchpad & ~data_1[59];

// Context registers at 0x08, 0x10, 0x108, 0x110
assign context =
       asi & (data_1[55:48] == 8'h21);
assign p_context_0 =
       context & ~data_1[8] & ~data_1[4] &  data_1[3];
assign wr_p_context_0 =
       p_context_0 & ~data_1[59];

// IMMU tag target at 0x00, IMMU SFSR at 0x18, IMMU tag access at 0x30
// Note that ISFSR is in TLU, not MMU
assign asi_50 =
       asi & (data_1[55:48] == 8'h50);
assign rd_asi_50 =
       asi_50 &  data_1[59] & ~data_1[3];
assign immu_tag_target =
       asi_50 & (data_1[7:3] == 5'b00000);
assign rd_immu_tag_target =
       immu_tag_target &  data_1[59];
assign immu_tag_access =
       asi_50 & (data_1[7:3] == 5'b00110);
assign rd_immu_tag_access =
       immu_tag_access &  data_1[59];
assign wr_immu_tag_access =
       immu_tag_access & ~data_1[59];

// Real range at 0x108, 110, 118, 120; physical offset at 0x208, 210, 218, 220
assign range_offset = 
       asi & (data_1[55:48] == 8'h52);
assign rd_range_offset =
       range_offset &  data_1[59];
assign real_range_0 =
       range_offset & (data_1[9:8] == 2'b01) & (data_1[5:3] == 3'b001);
assign real_range_1 =
       range_offset & (data_1[9:8] == 2'b01) & (data_1[5:3] == 3'b010);
assign real_range_2 =
       range_offset & (data_1[9:8] == 2'b01) & (data_1[5:3] == 3'b011);
assign real_range_3 =
       range_offset & (data_1[9:8] == 2'b01) & (data_1[5:3] == 3'b100);
assign physical_offset_0 =
       range_offset & (data_1[9:8] == 2'b10) & (data_1[5:3] == 3'b001);
assign physical_offset_1 =
       range_offset & (data_1[9:8] == 2'b10) & (data_1[5:3] == 3'b010);
assign physical_offset_2 =
       range_offset & (data_1[9:8] == 2'b10) & (data_1[5:3] == 3'b011);
assign physical_offset_3 =
       range_offset & (data_1[9:8] == 2'b10) & (data_1[5:3] == 3'b100);

// ITLB data in reg at 0x00, TSB configurations at 0x[1-4][0,8],
// TSB pointers at 0x[5-8][0,8],
// tablewalk in progress registers at 0x90, 0x98
assign asi_54 = 
       asi & (data_1[55:48] == 8'h54);
assign rd_asi_54 =
       asi_54 &  data_1[59];
assign itlb_data_in =
       asi_54 & (data_1[7:3] == 5'b00000);
assign wr_itlb_data_in =
       itlb_data_in & ~data_1[59];
assign z_tsb_cfg_0 =
       asi_54 & (data_1[7:3] == 5'b00010);
assign z_tsb_cfg_1 =
       asi_54 & (data_1[7:3] == 5'b00011);
assign z_tsb_cfg_2 =
       asi_54 & (data_1[7:3] == 5'b00100);
assign z_tsb_cfg_3 =
       asi_54 & (data_1[7:3] == 5'b00101);
assign nz_tsb_cfg_0 =
       asi_54 & (data_1[7:3] == 5'b00110);
assign nz_tsb_cfg_1 =
       asi_54 & (data_1[7:3] == 5'b00111);
assign nz_tsb_cfg_2 =
       asi_54 & (data_1[7:3] == 5'b01000);
assign nz_tsb_cfg_3 =
       asi_54 & (data_1[7:3] == 5'b01001);
assign wr_z_tsb_cfg_0 =
       z_tsb_cfg_0 & ~data_1[59];
assign wr_z_tsb_cfg_1 =
       z_tsb_cfg_1 & ~data_1[59];
assign wr_z_tsb_cfg_2 =
       z_tsb_cfg_2 & ~data_1[59];
assign wr_z_tsb_cfg_3 =
       z_tsb_cfg_3 & ~data_1[59];
assign wr_nz_tsb_cfg_0 =
       nz_tsb_cfg_0 & ~data_1[59];
assign wr_nz_tsb_cfg_1 =
       nz_tsb_cfg_1 & ~data_1[59];
assign wr_nz_tsb_cfg_2 =
       nz_tsb_cfg_2 & ~data_1[59];
assign wr_nz_tsb_cfg_3 =
       nz_tsb_cfg_3 & ~data_1[59];
assign itsb_ptr_0 =
       asi_54 & (data_1[7:3] == 5'b01010);
assign itsb_ptr_1 =
       asi_54 & (data_1[7:3] == 5'b01011);
assign itsb_ptr_2 =
       asi_54 & (data_1[7:3] == 5'b01100);
assign itsb_ptr_3 =
       asi_54 & (data_1[7:3] == 5'b01101);
assign dtsb_ptr_0 =
       asi_54 & (data_1[7:3] == 5'b01110);
assign dtsb_ptr_1 =
       asi_54 & (data_1[7:3] == 5'b01111);
assign dtsb_ptr_2 =
       asi_54 & (data_1[7:3] == 5'b10000);
assign dtsb_ptr_3 =
       asi_54 & (data_1[7:3] == 5'b10001);
assign asi_2 = 
       ctl_2 & data_2[63] & ~data_2[62] & (data_2[61:60] == 2'b00);
assign asi_54_2 = 
       asi_2 & (data_2[55:48] == 8'h54);
assign t_p_c_2 = // tablewalk_pending_control
       asi_54_2 & (data_2[7:3] == 5'b10010);
assign t_p_s_2 = // tablewalk_pending_status
       asi_54_2 & (data_2[7:3] == 5'b10011);
assign rd_t_p_c_2 = 
       t_p_c_2 &  data_2[59] & ~mbist_run;
assign wr_t_p_c_2 =
       t_p_c_2 & ~data_2[59];
assign rd_t_p_s_2 =
       t_p_s_2 &  data_2[59] & ~mbist_run;

assign legal_data_in_page_size = // 0000, 0001, 0011, 0101
        ((~data_1[3] & ~data_1[2] & ~data_1[1]) |   // 0000, 0001
         (~data_1[3] & ~data_1[2] &  data_1[0]) |   // 0001, 0011
         (~data_1[3] & ~data_1[1] &  data_1[0]) ) | // 0001, 0101
       (~(wr_itlb_data_in_2 | wr_dtlb_data_in_2 | 
	  wr_itlb_data_access_2 | wr_dtlb_data_access_2));

assign clear_data_in_write_[7:0] =
       ({8 {legal_data_in_page_size}} & wr_tid_dec[7:0]) | 
       ~wr_tid_dec[7:0];

assign legal_tsb_cfg_page_size = // 0000, 0001, 0011, 0101
       (~data_1[7] & ~data_1[6] & ~data_1[5]) | // 0000, 0001
       (~data_1[7] & ~data_1[6] &  data_1[4]) | // 0001, 0011
       (~data_1[7] & ~data_1[5] &  data_1[4]) | // 0001, 0101
       data_2[59]; // read -- don't check for legal size on read!

// fast_dtsb_ptr distinguishes dtsb_ptr from itsb_ptr
assign fast_dtsb_ptr =
       (data_1[5] & data_1[4]) | data_1[7];

assign asi_tag_access_sel[2:0] =
       {fast_dtsb_ptr, data_1[57:56]};

assign asi_tsb_ptr_req_valid =
       itsb_ptr_0 | itsb_ptr_1 | itsb_ptr_2 | itsb_ptr_3 |
       dtsb_ptr_0 | dtsb_ptr_1 | dtsb_ptr_2 | dtsb_ptr_3 ;

assign itsb_ptr =
       itsb_ptr_0 | itsb_ptr_1 | itsb_ptr_2 | itsb_ptr_3;

assign dtsb_ptr = 
       dtsb_ptr_0 | dtsb_ptr_1 | dtsb_ptr_2 | dtsb_ptr_3;

assign asi_tsb_ptr_req[2:0] =
       {data_1[58:56]};

assign asi_tsb_ptr_number[1:0] =
       {dtsb_ptr_3 | dtsb_ptr_2 | itsb_ptr_3 | itsb_ptr_2,
	dtsb_ptr_3 | dtsb_ptr_1 | itsb_ptr_3 | itsb_ptr_1};

assign rd_tsb_ptr_1 = 
       itsb_ptr | dtsb_ptr;

assign asi_rd_tsb_ptr_ =
       ~(rd_tsb_ptr_1 & ~mbist_run);

// MRA diagnostic access at ASI 0x51, addr 0x00 - 0x38
assign mra_diag =
       asi & (data_1[55:48] == 8'h51);
assign rd_mra_parity =
       mra_diag & data_1[59];

// ITLB data access reg at 0x000 - 0x1F8
assign itlb_data_access = 
       asi & (data_1[55:48] == 8'h55);
assign rd_itlb_data_access =
       itlb_data_access &  data_1[59];
assign wr_itlb_data_access =
       itlb_data_access & ~data_1[59];
       
// ITLB tag read reg at 0x000 - 0x1F8
assign itlb_tag_read = 
       asi & (data_1[55:48] == 8'h56);
assign rd_itlb_tag_read =
       itlb_tag_read &  data_1[59];
       
// IMMU demap at address 0x0 (data holds command)
assign immu_demap = 
       asi & (data_1[55:48] == 8'h57) & legal_i_demap;
assign wr_immu_demap =
       immu_demap & ~data_1[59];
assign legal_i_demap = 
       data_1[7] |  // all, real
       ~data_1[4];  // primary, nucleus
       
// DMMU demap at address 0x0 (data holds command)
assign dmmu_demap = 
       asi & (data_1[55:48] == 8'h5f) & legal_d_demap;
assign wr_dmmu_demap =
       dmmu_demap & ~data_1[59];
assign legal_d_demap = 
       data_1[7] |  // all, real
       ~data_1[5] | // primary, secondary
       ~data_1[4];  // primary, nucleus
       
// DMMU tag target at 0x00, DMMU SFSR at 0x18, DMMU SFAR at 0x20,
// DMMU tag access at 0x30, hwtw_config at 0x40, partition ID at 0x80, 
assign asi_58 = 
       asi & (data_1[55:48] == 8'h58);
assign rd_asi_58 =
       asi_58 &  data_1[59];
// MMU owns ASI 0x58 except sync fault registers (addr 0x18 & 0x20)
assign rd_asi_58_not_sfr =
       rd_asi_58 & ((data_1[5:4] == 2'b00) | (data_1[5:4] == 2'b11));
assign dmmu_tag_target =
       asi_58 & (data_1[7:3] == 5'b00000);
assign rd_dmmu_tag_target =
       dmmu_tag_target &  data_1[59];
assign dmmu_tag_access =
       asi_58 & (data_1[7:3] == 5'b00110);
assign rd_dmmu_tag_access =
       dmmu_tag_access &  data_1[59];
assign wr_dmmu_tag_access =
       dmmu_tag_access & ~data_1[59];
assign hwtwconfig =
       asi_58 & (data_1[7:3] == 5'b01000);
assign partition_id =
       asi_58 & (data_1[7:3] == 5'b10000);
assign wr_partition_id =
       partition_id & ~data_1[59];

// Scratchpad diagnostic access at ASI 0x59, addr 0x00 - 0x78
assign sca_diag =
       asi & (data_1[55:48] == 8'h59);
assign rd_sca_ecc =
       sca_diag & ~data_1[6] &  data_1[59];
assign rd_sca_data =
       sca_diag &  data_1[6] &  data_1[59];

// DTLB data in reg at 0x00
assign dtlb_data_in =
       asi & (data_1[55:48] == 8'h5c);
assign wr_dtlb_data_in =
       dtlb_data_in & ~data_1[59];

// DTLB data access reg at 0x000 - 0x1F8
assign dtlb_data_access =
       asi & (data_1[55:48] == 8'h5d);
assign rd_dtlb_data_access =
       dtlb_data_access &  data_1[59];
assign wr_dtlb_data_access =
       dtlb_data_access & ~data_1[59];
       
// DTLB tag read reg at 0x000 - 0x1F8
assign dtlb_tag_read =
       asi & (data_1[55:48] == 8'h5e);
assign rd_dtlb_tag_read =
       dtlb_tag_read &  data_1[59];
       

assign mmu_asi_rd_1 = 
       rd_scratchpad | rd_asi_50 | rd_range_offset | rd_asi_54 |
       rd_itlb_data_access | rd_itlb_tag_read | rd_asi_58_not_sfr | 
       rd_dtlb_data_access | rd_dtlb_tag_read | rd_sca_ecc | rd_sca_data;


// Three classes of register:
//	1.  Scratchpad registers
// 	2.  Registers stored in MMU register array (MRA)
//	3.  Individual registers present in MMU
//		or
//	    calculations performed within MMU
//


//
// Scratchpad registers
// These are stored in SCP
//
assign scp_addr[4:0] =
       ({5 {rd_scratchpad   & ~mbist_run}} & {data_1[57:56], data_1[5:3]}) |
       ({5 {wr_scratchpad_2 & ~mbist_run}} & {data_2[57:56], data_2[5:3]}) |
       ({5 {rd_sca_ecc      & ~mbist_run}} & {data_1[57:56], data_1[5:3]}) |
       ({5 {rd_sca_data     & ~mbist_run}} & {data_1[57:56], data_1[5:3]}) |
       ({5 {                   mbist_run}} & mbist_addr[4:0]             ) ;

assign scp_rd_en_2[1:0] =
       {2 {rd_scratchpad_2 & ~mbist_run}} & {data_2[58], ~data_2[58]};
assign scp_wr_en[1:0] =
       ({2 {wr_scratchpad_2 & ~mbist_run}} & {data_2[58], ~data_2[58]}) | 
       ({2 {mbist_run}} & {mbist_scp1_wr_en, mbist_scp0_wr_en}) ;

assign rd_sca_data_en_2[1:0] =
       {2 {rd_sca_data_2 & ~mbist_run}} & {data_2[58], ~data_2[58]};
assign rd_sca_ecc_en_2[1:0] =
       {2 {rd_sca_ecc_2  & ~mbist_run}} & {data_2[58], ~data_2[58]};

mmu_asi_ctl_msff_ctl_macro__width_5 scp_ctl_lat  (
	.scan_in(scp_ctl_lat_scanin),
	.scan_out(scp_ctl_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	({rd_sca_ecc	       ,
		  rd_sca_data	       ,
		  rd_scratchpad	       ,
		  rd_scratchpad_2      ,
		  wr_scratchpad        }),
	.dout	({rd_sca_ecc_2	       ,
		  rd_sca_data_2	       ,
		  rd_scratchpad_2      ,
		  rd_scratchpad_3      ,
		  wr_scratchpad_2      }),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_sel_en =
       rd_scratchpad_2 | rd_scratchpad_3;

assign rd_scratchpad_4_in =
       rd_scratchpad_3 & check_ecc;

mmu_asi_ctl_msff_ctl_macro__width_1 rd_scratchpad_4_lat  (
	.scan_in(rd_scratchpad_4_lat_scanin),
	.scan_out(rd_scratchpad_4_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(rd_scratchpad_4_in	),
	.dout	(rd_scratchpad_4	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_scp_addr[4:0] =
       scp_addr[4:0];

assign asi_scp_wr_en[1:0] =
       scp_wr_en[1:0];

assign scp_rden[1:0] =
       ({2 {(rd_scratchpad | rd_sca_ecc | rd_sca_data) & ~mbist_run}} & 
	{data_1[58], ~data_1[58]}) |
       ({2 {mbist_run}} & {mbist_scp1_rd_en, mbist_scp0_rd_en}) ;

assign asi_scp_rd_en[1:0] =
       scp_rden[1:0];


//
// MMU register array (MRA)
//		z TSB cfg 0,1				address 0
//		z TSB cfg 2,3				address 1
//		nz TSB cfg 0,1				address 2
//		nz TSB cfg 2,3				address 3
//		Real range, physical offset pair 0	address 4
//		Real range, physical offset pair 1	address 5
//		Real range, physical offset pair 2	address 6
//		Real range, physical offset pair 3	address 7
// Since registers must be reformatted, read takes two cycles 
// (read of array and then format of data)
//
// Note that reads of the TSB pointers are calculations that depend on
// the TSB configuration registers (and therefore read them)
//
// All registers are written by
//
// Prioritizes between
// ASI access (highest)
// HW TW access (lowest)

assign mra_rd_en_1[1:0] =
       {data_1[58], ~data_1[58]} &
       {2 {z_tsb_cfg_0 | z_tsb_cfg_1 | 
	   z_tsb_cfg_2 | z_tsb_cfg_3 |
	   nz_tsb_cfg_0 | nz_tsb_cfg_1 | 
	   nz_tsb_cfg_2 | nz_tsb_cfg_3 |
	   itsb_ptr_0 | itsb_ptr_1 | 
	   itsb_ptr_2 | itsb_ptr_3 |
	   dtsb_ptr_0 | dtsb_ptr_1 | 
	   dtsb_ptr_2 | dtsb_ptr_3 |
	   real_range_0 | real_range_1 | 
	   real_range_2 | real_range_3 |
	   physical_offset_0 | physical_offset_1 | 
	   physical_offset_2 | physical_offset_3 | 
           rd_mra_parity}};

assign mra_rd_addr[4:3] =
       data_1[57:56];

assign mra_rd_addr[2] = // 4, 5, 6, 7
       real_range_0 | real_range_1 | 
       real_range_2 | real_range_3 |
       physical_offset_0 | physical_offset_1 | 
       physical_offset_2 | physical_offset_3 |
       (rd_mra_parity & data_1[5]);

assign mra_rd_addr0[1] = // 2, 3, 6, 7
       nz_tsb_cfg_0 | nz_tsb_cfg_1 | 
       nz_tsb_cfg_2 | nz_tsb_cfg_3 | 
       real_range_2 | real_range_3 |
       physical_offset_2 | physical_offset_3 |
       (rd_mra_parity & data_1[4]);

assign mra_rd_addr1[1] = // 2, 3, 6, 7
       nz_tsb_cfg_0 | nz_tsb_cfg_1 | 
       nz_tsb_cfg_2 | nz_tsb_cfg_3 | 
       real_range_2 | real_range_3 |
       physical_offset_2 | physical_offset_3 |
       (rd_mra_parity & data_1[4]);

assign mra_rd_addr[0] = // 1, 3, 5, 7
       z_tsb_cfg_2 | z_tsb_cfg_3 |
       nz_tsb_cfg_2 | nz_tsb_cfg_3 |
       itsb_ptr_2 | itsb_ptr_3 | 
       dtsb_ptr_2 | dtsb_ptr_3 | 
       real_range_1 | real_range_3 |
       physical_offset_1 | physical_offset_3 |
       (rd_mra_parity & data_1[3]);

assign mra_rd_addr0[4:2] =
       mra_rd_addr[4:2];
assign mra_rd_addr1[4:2] =
       mra_rd_addr[4:2];
assign mra_rd_addr[1] =
       mra_rd_addr0[1] | mra_rd_addr1[1];
assign mra_rd_addr0[0] =
       mra_rd_addr[0];
assign mra_rd_addr1[0] =
       mra_rd_addr[0];


assign mra_addr_sel_rd[1:0] = 
       mra_rd_en_1[1:0] & {2 {~mbist_run}};
assign mra_avail[1:0] = 
       ~mra_rd_en_1[1:0] & {2 {~mbist_run}};
// Prevent any HW TW access to MRA when tsb ptr read occurs
assign mra_addr_sel_hw_tw[1:0] = 
       htc_mra_rd_en[1:0] & mra_avail[1:0] & {2 {~rd_tsb_ptr_1}};

assign req_grant_in =
       | mra_addr_sel_hw_tw[1:0];

mmu_asi_ctl_msff_ctl_macro__width_1 req_grant_lat  (
	.scan_in(req_grant_lat_scanin),
	.scan_out(req_grant_lat_scanout),
	.din	(req_grant_in			),
	.dout	(req_grant			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mra_req_grant = // To hardware tablewalk
       req_grant;

// 0in bits_on -var {mra_addr_sel_rd[01], mra_addr_sel_hw_tw[01], mbist_run} -max 1
// 0in bits_on -var {mra_addr_sel_rd[00], mra_addr_sel_hw_tw[00], mbist_run} -max 1
assign mra_rd_addr_1[4:0] =
        ({5 {mra_addr_sel_rd   [1]}} & mra_rd_addr1	[4:0]) | 
        ({5 {mra_addr_sel_hw_tw[1]}} & htc_mra_addr_in	[4:0]) | 
        ({5 {mbist_run		   }} & mbist_addr_2	[4:0]) ;

assign mra_rd_addr_0[4:0] =
        ({5 {mra_addr_sel_rd   [0]}} & mra_rd_addr0	[4:0]) | 
        ({5 {mra_addr_sel_hw_tw[0]}} & htc_mra_addr_in	[4:0]) | 
        ({5 {mbist_run		   }} & mbist_addr_2	[4:0]) ;

assign asi_mra_rd_addr_1[4:0] =
       mra_rd_addr_1[4:0];

assign asi_mra_rd_addr_0[4:0] =
       mra_rd_addr_0[4:0];

// Account for logic in mmu_asd_dp
assign zero_context =
       (asd1_asi_zero_context &  data_1[58]) |
       (asd0_asi_zero_context & ~data_1[58]) ;
assign tsb_ptr_addr[1] = 
       ~zero_context & rd_tsb_ptr_1;

assign mra_addr_1[4:2] = 
       mra_rd_addr[4:2];
assign mra_addr_1[1] = 
       mra_rd_addr[1] | tsb_ptr_addr[1];
assign mra_addr_1[0] = 
       mra_rd_addr[0];

mmu_asi_ctl_msff_ctl_macro__width_15 mra_addr_lat  (
	.scan_in(mra_addr_lat_scanin),
	.scan_out(mra_addr_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	({mra_addr_1		[4:0],
		  mra_addr_2		[4:0],
		  mra_addr_3		[4:0]}),
	.dout	({mra_addr_2		[4:0],
		  mra_addr_3		[4:0],
		  mra_addr_4		[4:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mra_wr_addr[4:0] =
       (mra_addr_4	[4:0] & {5 {~mbist_run}}) | 
       (mbist_addr_2	[4:0] & {5 { mbist_run}}) ;

assign mra_rd_en[1:0] = 
       (    mra_rd_en_1[1:0]                   & {2 {~mbist_run}}) | 
       (htc_mra_rd_en  [1:0]                   & {2 {~mbist_run}}) | 
       ({mbist_mra1_rd_en_2, mbist_mra0_rd_en_2} & {2 { mbist_run}}) ;

assign asi_mra_rd_en[1:0] =
       mra_rd_en[1:0];

assign mra_to_r3_in_in[1:0] = 
       mra_addr_sel_rd[1:0];

assign mra_to_r3_in[1:0] =
       {pmra_to_r3_in[1], 
	(pmra_to_r3_in[0] & ~mbist_run) | (mbist_mra0_rd_en_3 & mbist_run)};

mmu_asi_ctl_msff_ctl_macro__width_6 mra_rd_en_lat  (
	.scan_in(mra_rd_en_lat_scanin),
	.scan_out(mra_rd_en_lat_scanout),
	.din	({mra_rd_en		[1:0],
		  mra_to_r3_in_in	[1:0],
		  mra_to_r3_in		[1:0]}),
	.dout	({mra_rd_en_last	[1:0],
		  pmra_to_r3_in		[1:0],
		  pmra_to_r3		[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_sel_mra_0_in =
       mra_to_r3_in[0];

assign asi_mra_rd_en_last[1:0] =
       mra_rd_en_last[1:0];

assign mra_wr_en_1[1:0] =
       mra_addr_sel_rd[1:0] & {2 {~data_1[59]}};

assign mra_wr_en_3_in[1:0] =
       mra_wr_en_2[1:0] & 
       (~mra_to_r3_in[1:0] | 
	(mra_to_r3_in[1:0] & 
	 {2 {((mra_sel_tsb_cfg_2 & legal_tsb_cfg_page_size) | 
	      ~mra_sel_tsb_cfg_2)}}));

assign mra_sel_tsb_cfg_2 =
       mra_sel_tsb_cfg_0_2_2 | mra_sel_tsb_cfg_1_3_2;

mmu_asi_ctl_msff_ctl_macro__width_4 mra_wr_en_lat  (
	.scan_in(mra_wr_en_lat_scanin),
	.scan_out(mra_wr_en_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	({mra_wr_en_1		[1:0],
		  mra_wr_en_3_in   	[1:0]}),
	.dout	({mra_wr_en_2   	[1:0],
		  mra_wr_en_3  		[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_2 mra_wr_en_4_lat  (
	.scan_in(mra_wr_en_4_lat_scanin),
	.scan_out(mra_wr_en_4_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(mra_wr_en_3   		[1:0]	),
	.dout	(mra_wr_en_4   		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mra_wr_en_next =
       (| mra_wr_en_3[1:0]) | mbist_run;

assign mra_wr_en_out[1:0] =
       (mra_wr_en_4[1:0] & {2 {~mra_uecc_4 & ~mbist_run}}) |
       ({mbist_mra1_wr_en_2, mbist_mra0_wr_en_2} & {2 { mbist_run}}) ;

assign asi_mra_wr_en[1:0] =
       mra_wr_en_out[1:0];

// Generate controls for readmux and modify cycles
assign mra_sel_tsb_cfg_0_2_1 =
       z_tsb_cfg_0 | z_tsb_cfg_2 | 
       nz_tsb_cfg_0 | nz_tsb_cfg_2 ;
assign mra_sel_tsb_cfg_1_3_1 =
       z_tsb_cfg_1 | z_tsb_cfg_3 | 
       nz_tsb_cfg_1 | nz_tsb_cfg_3 ;
assign mra_sel_real_range_1 =
       real_range_0 | real_range_1 | real_range_2 | real_range_3;
assign mra_sel_physical_offset_1 =
       physical_offset_0 | physical_offset_1 | 
       physical_offset_2 | physical_offset_3;

mmu_asi_ctl_msff_ctl_macro__width_8 mra_sel_lat  (
	.scan_in(mra_sel_lat_scanin),
	.scan_out(mra_sel_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	({mra_sel_tsb_cfg_0_2_1,
		  mra_sel_tsb_cfg_1_3_1,
		  mra_sel_real_range_1,
		  mra_sel_physical_offset_1,
		  mra_sel_tsb_cfg_0_2_2,
		  mra_sel_tsb_cfg_1_3_2,
		  mra_sel_real_range_2,
		  mra_sel_physical_offset_2}),
	.dout	({mra_sel_tsb_cfg_0_2_2,
		  mra_sel_tsb_cfg_1_3_2,
		  mra_sel_real_range_2,
		  mra_sel_physical_offset_2,
		  mra_sel_tsb_cfg_0_2_3,
		  mra_sel_tsb_cfg_1_3_3,
		  mra_sel_real_range_3,
		  mra_sel_physical_offset_3}),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_rd_tsb_cfg_0_2 = 
       mra_sel_tsb_cfg_0_2_3;
assign asi_rd_tsb_cfg_1_3 = 
       mra_sel_tsb_cfg_1_3_3;
assign asi_rd_real_range = 
       mra_sel_real_range_3;
assign asi_rd_physical_offset = 
       mra_sel_physical_offset_3;

assign rd_tsb_cfg_3 =
       mra_sel_tsb_cfg_0_2_3 | mra_sel_tsb_cfg_1_3_3;

assign asi_mra_wr_data[63:0] =
       data_2[63:0];

assign asi_demap_r_bit =
       data_2[10] & ~demap_context_2;
assign demap_context_2 =
       ~data_2[7] & data_2[6];		     


//
// Individual register reads (write controls from cycle 2)
//
assign rd_tid_dec	[7:0] = 
       { data_1[58] &  data_1[57] &  data_1[56], 
         data_1[58] &  data_1[57] & ~data_1[56], 
         data_1[58] & ~data_1[57] &  data_1[56], 
         data_1[58] & ~data_1[57] & ~data_1[56], 
        ~data_1[58] &  data_1[57] &  data_1[56], 
        ~data_1[58] &  data_1[57] & ~data_1[56], 
        ~data_1[58] & ~data_1[57] &  data_1[56], 
        ~data_1[58] & ~data_1[57] & ~data_1[56]};

assign asi_rd_immu_tag_target[7:0] =
       {8 {rd_immu_tag_target}} & rd_tid_dec[7:0];
assign asi_rd_immu_tag_access[7:0] =
       {8 {rd_immu_tag_access}} & rd_tid_dec[7:0];
assign asi_rd_i_access_target[1:0] =
       {2 {rd_immu_tag_target | rd_immu_tag_access}} &
       {data_1[58], ~data_1[58]};
assign asi_rd_dmmu_tag_target[7:0] =
       {8 {rd_dmmu_tag_target}} & rd_tid_dec[7:0];
assign asi_rd_dmmu_tag_access[7:0] =
       {8 {rd_dmmu_tag_access}} & rd_tid_dec[7:0];
assign asi_rd_d_access_target[1:0] =
       {2 {rd_dmmu_tag_target | rd_dmmu_tag_access}} &
       {data_1[58], ~data_1[58]};
assign asi_rd_access_target[1:0] =
       {2 {rd_immu_tag_target | rd_immu_tag_access | 
	   rd_dmmu_tag_target | rd_dmmu_tag_access }} &
       {data_1[58], ~data_1[58]};


assign dtlb0_tte_tag[63:0] =
       {{16 {1'b0}}, asd0_dtte_tag[47:0]};
assign dtlb1_tte_tag[63:0] =
       {{16 {1'b0}}, asd1_dtte_tag[47:0]};
assign scp0_ecc_bus[63:0] =
       {{56 {1'b0}}, scp0_ecc[7:0]};
assign scp1_ecc_bus[63:0] =
       {{56 {1'b0}}, scp1_ecc[7:0]};
assign mbist_scp0_0[63:0] =
       {{32 {1'b0}}, scp0_data[31:0]};
assign mbist_scp0_1[63:0] =
       {{32 {1'b0}}, scp0_data[63:32]};
assign mbist_scp0_2[63:0] =
       {{32 {1'b0}}, {4 {scp0_ecc[7:0]}}};
assign mbist_scp1_0[63:0] =
       {{32 {1'b0}}, scp1_data[31:0]};
assign mbist_scp1_1[63:0] =
       {{32 {1'b0}}, scp1_data[63:32]};
assign mbist_scp1_2[63:0] =
       {{32 {1'b0}}, {4 {scp1_ecc[7:0]}}};

assign sel_data_1 =
       ~(| {use_dtlb_window[1:0], asd_asi_sel[1:0], scp_rd_en_2[1:0],
	 rd_sca_ecc_en_2[1:0], rd_sca_data_en_2[1:0], 
	 mbist_scp0_rd_en_2, mbist_scp1_rd_en_2, rd_hwtw_config_2,
         rd_t_p_c_2, rd_t_p_s_2});

assign asd_asi_sel[1:0] =
       {2 {asd_asi_rd_2 & ~mbist_run}} & {data_2[58], ~data_2[58]};
assign asd_asi_rd_1 = 
       rd_immu_tag_target | rd_immu_tag_access |
       rd_dmmu_tag_target | rd_dmmu_tag_access; 


// 0in bits_on -var {sel_data_1, use_dtlb_window[01:00], asd_asi_sel[01:00], scp_rd_en_2[01:00], rd_sca_ecc_en_2[01:00], rd_hwtw_config_2, rd_sca_data_en_2[01:00]} -max 1
assign data_2_in[63:0] =
       ({64 {sel_data_1       	 }} & data_1		[63:0]) |
       ({64 {use_dtlb_window[0] }} & dtlb0_tte_tag	[63:0]) |
       ({64 {use_dtlb_window[1] }} & dtlb1_tte_tag	[63:0]) |
       ({64 {asd_asi_sel[0]  	 }} & asd0_asi_rd_data	[63:0]) |
       ({64 {asd_asi_sel[1]  	 }} & asd1_asi_rd_data	[63:0]) |
       ({64 {scp_rd_en_2[0]  	 }} & scp0_data		[63:0]) |
       ({64 {scp_rd_en_2[1]  	 }} & scp1_data		[63:0]) |
       ({64 {rd_sca_data_en_2[0]}} & scp0_data		[63:0]) |
       ({64 {rd_sca_data_en_2[1]}} & scp1_data		[63:0]) |
       ({64 {rd_sca_ecc_en_2[0] }} & scp0_ecc_bus	[63:0]) |
       ({64 {rd_sca_ecc_en_2[1] }} & scp1_ecc_bus	[63:0]) |
       ({64 {rd_hwtw_config_2    }} & hwtw_config_muxed	[63:0]) |
       ({64 {mbist_scp0_0_rd_en  }} & mbist_scp0_0	[63:0]) |
       ({64 {mbist_scp0_1_rd_en  }} & mbist_scp0_1	[63:0]) |
       ({64 {mbist_scp0_2_rd_en  }} & mbist_scp0_2	[63:0]) |
       ({64 {mbist_scp1_0_rd_en  }} & mbist_scp1_0	[63:0]) |
       ({64 {mbist_scp1_1_rd_en  }} & mbist_scp1_1	[63:0]) |
       ({64 {mbist_scp1_2_rd_en  }} & mbist_scp1_2	[63:0]) |
       ({64 {rd_t_p_c_2          }} & rd_t_p_c_data	[63:0]) |
       ({64 {rd_t_p_s_2          }} & rd_t_p_s_data	[63:0]) ;

// For muxing of ECC bits in mmu_sel_dp
assign asi_rd_scp0 =
       scp_rd_en_2[0];


/////////////////////////////////////////////////////////////////////
//STAGE 2
/////////////////////////////////////////////////////////////////////
// pipe the packets and decoded control information
mmu_asi_ctl_msff_ctl_macro__width_64 stg2_data_lat  (
	.scan_in(stg2_data_lat_scanin),
	.scan_out(stg2_data_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(data_2_in	[63:0]	), 
	.dout	(data_2		[63:0]	),
  .siclk(siclk),
  .soclk(soclk)
);


assign asi_mbd_scp_data[31:0] =
       data_2[31:0];

// register control bit
mmu_asi_ctl_msff_ctl_macro__width_16 stg2_ctl_lat  (
	.scan_in(stg2_ctl_lat_scanin),
	.scan_out(stg2_ctl_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	({ctl_1,
		  mmu_asi_rd_1,
		  asd_asi_rd_1,
		  rd_tsb_ptr_1,
		  rd_mra_parity,
		  wr_immu_tag_access,
		  wr_itlb_data_in,
		  wr_itlb_data_access,
		  wr_immu_demap,
		  wr_dmmu_tag_access,
		  wr_dmmu_demap,
		  wr_dtlb_data_in,
		  wr_dtlb_data_access,
		  wr_p_context_0,
		  wr_partition_id,
		  hwtwconfig}),
	.dout	({ctl_2,
		  mmu_asi_rd_2,
		  asd_asi_rd_2,
		  rd_tsb_ptr_2,
		  rd_mra_parity_2,
		  wr_immu_tag_access_2,
		  wr_itlb_data_in_2,
		  wr_itlb_data_access_2,
		  wr_immu_demap_2, 
		  wr_dmmu_tag_access_2,
		  wr_dmmu_demap_2, 
		  wr_dtlb_data_in_2,
		  wr_dtlb_data_access_2,
		  wr_p_context_0_2,
		  wr_partition_id_2, 
		  hwtwconfig_2}),
  .siclk(siclk),
  .soclk(soclk)
);

// send the store data out to the unit. Store data is in stage1 when control 
// is in stage 2.
assign asi_seg_wr_data	[63:0] = 
       data_1		[63:0] ;
assign asi_wr_data	[63:0] = 
       (data_1		[63:0] & {64 {~mbist_run}}) | 
       (mbist_wr_data	[63:0] & {64 { mbist_run}}) ;

assign wr_tid_dec	[7:0] = 
       { data_2[58] &  data_2[57] &  data_2[56], 
         data_2[58] &  data_2[57] & ~data_2[56], 
         data_2[58] & ~data_2[57] &  data_2[56], 
         data_2[58] & ~data_2[57] & ~data_2[56], 
        ~data_2[58] &  data_2[57] &  data_2[56], 
        ~data_2[58] &  data_2[57] & ~data_2[56], 
        ~data_2[58] & ~data_2[57] &  data_2[56], 
        ~data_2[58] & ~data_2[57] & ~data_2[56]};

assign a_wr_immu_tag_access[7:0] =
       {8 { wr_immu_tag_access_2}} & wr_tid_dec[7:0] ;
assign asi_wr_immu_tag_access[7:0] =
       a_wr_immu_tag_access[7:0];
assign a_wr_itlb_data_in[7:0] =
       {8 { wr_itlb_data_in_2 & legal_data_in_page_size}} & wr_tid_dec[7:0] ;
assign asi_wr_itlb_data_in[7:0] =
       a_wr_itlb_data_in[7:0];
assign a_wr_itlb_data_access[7:0] =
       {8 { wr_itlb_data_access_2 & legal_data_in_page_size}} & 
       wr_tid_dec[7:0] ;
assign asi_wr_itlb_data_access[7:0] =
       a_wr_itlb_data_access[7:0];
assign a_wr_immu_demap[7:0] =
       {8 {wr_immu_demap_2}} & wr_tid_dec[7:0] ;
assign asi_wr_immu_demap[7:0] =
       a_wr_immu_demap[7:0];
// Demap uses address, not data, so use data_2 here
assign asi_wr_immu_demap_p[7:0] =
       {8 {wr_immu_demap_2 & ~data_2[5] & ~data_2[4] }} & wr_tid_dec[7:0] ;
assign asi_wr_immu_demap_n[7:0] =
       {8 {wr_immu_demap_2 & (data_2[5] |  data_2[4])}} & wr_tid_dec[7:0] ;
assign a_wr_dmmu_tag_access[7:0] =
       {8 { wr_dmmu_tag_access_2}} & wr_tid_dec[7:0] ;
assign asi_wr_dmmu_tag_access[7:0] =
       a_wr_dmmu_tag_access[7:0];
assign a_wr_dtlb_data_in[7:0] =
       {8 { wr_dtlb_data_in_2 & legal_data_in_page_size}} & wr_tid_dec[7:0] ;
assign asi_wr_dtlb_data_in[7:0] =
       a_wr_dtlb_data_in[7:0];
assign a_wr_dtlb_data_access[7:0] =
       {8 { wr_dtlb_data_access_2 & legal_data_in_page_size}} & 
       wr_tid_dec[7:0] ;
assign asi_wr_dtlb_data_access[7:0] =
       a_wr_dtlb_data_access[7:0];
assign asi_wr_partition_id[7:0] =
       {8 {wr_partition_id_2}} & wr_tid_dec[7:0] ;
assign a_wr_dmmu_demap[7:0] =
       {8 {wr_dmmu_demap_2}} & wr_tid_dec[7:0] ;
assign asi_wr_dmmu_demap[7:0] =
       a_wr_dmmu_demap[7:0];
// Demap uses address, not data, so use data_2 here
assign asi_wr_dmmu_demap_p[7:0] =
       {8 {wr_dmmu_demap_2 & ~data_2[5] & ~data_2[4] }} & wr_tid_dec[7:0] ;
assign asi_wr_dmmu_demap_s_n[7:0] =
       {8 {wr_dmmu_demap_2 & (data_2[5] |  data_2[4])}} & wr_tid_dec[7:0] ;
assign asi_dmmu_demap_s =
       ~data_2[5] & data_2[4];

// Write of p_context shadows for immu_tag_access reg
assign asi_wr_p_context_0[7:0] =
       {8 {wr_p_context_0_2}} & wr_tid_dec[7:0];

assign asi_p_context_0_en[1:0] =
       {2 {wr_p_context_0_2}} & {data_2[58], ~data_2[58]};

assign rd_hwtw_config_2 =
       hwtwconfig_2 &  data_2[59] & ~mbist_run;
assign rd_hwtw_config_dec =
       {8 {hwtwconfig_2 &  data_2[59]}} & wr_tid_dec[7:0];
assign wr_hwtw_config_dec =
       {8 {hwtwconfig_2 & ~data_2[59]}} & wr_tid_dec[7:0];

assign suppress_write_2 = 
       ((wr_itlb_data_in_2 | wr_dtlb_data_in_2 | 
	 wr_itlb_data_access_2 | wr_dtlb_data_access_2) & 
	~legal_data_in_page_size) |
       ((| mra_to_r3_in[1:0]) & mra_sel_tsb_cfg_2 & ~legal_tsb_cfg_page_size);

mmu_asi_ctl_msff_ctl_macro__width_1 dae_req_lat  (
	.scan_in(dae_req_lat_scanin),
	.scan_out(dae_req_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(suppress_write_2		),
	.dout	(suppress_write_3		),
  .siclk(siclk),
  .soclk(soclk)
		  
);

assign mmu_dae_req =
       suppress_write_3;
assign mmu_dae_tid[2:0] =
       data_3[58:56];

// Real bit for data_in and data_access is encoded in address bit 10
assign asi_data_in_real =
       data_2[10];


// Set error bit for ECC problems
assign check_ecc_in =
       | (tlu_ceter_pscce[7:0] &
	  { data_2[58] &  data_2[57] &  data_2[56],
            data_2[58] &  data_2[57] & ~data_2[56],
            data_2[58] & ~data_2[57] &  data_2[56],
            data_2[58] & ~data_2[57] & ~data_2[56],
           ~data_2[58] &  data_2[57] &  data_2[56],
           ~data_2[58] &  data_2[57] & ~data_2[56],
           ~data_2[58] & ~data_2[57] &  data_2[56],
           ~data_2[58] & ~data_2[57] & ~data_2[56]});

mmu_asi_ctl_msff_ctl_macro__width_1 check_ecc_lat  (
	.scan_in(check_ecc_lat_scanin),
	.scan_out(check_ecc_lat_scanout),
	.din	(check_ecc_in			),
	.dout	(check_ecc			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pmra_to_r4_in[1:0] =
	pmra_to_r3[1:0] & {2 {check_ecc}};

mmu_asi_ctl_msff_ctl_macro__width_2 pmra_to_r4_lat  (
	.scan_in(pmra_to_r4_lat_scanin),
	.scan_out(pmra_to_r4_lat_scanout),
	.din	(pmra_to_r4_in		[1:0]	),
	.dout	(pmra_to_r4		[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
		  

assign cecc_4 =
       (sel_scac  & rd_scratchpad_4) ;

assign uecc_4 =
       (sel_scau  & rd_scratchpad_4) |
       (mel0_parity_err	& pmra_to_r4[0] ) |
       (mel1_parity_err	& pmra_to_r4[1] ) ;

assign mra_uecc_4 = 
       (mel0_parity_err	& pmra_to_r4[0] ) |
       (mel1_parity_err	& pmra_to_r4[1] ) ;

mmu_asi_ctl_msff_ctl_macro__width_3 tid_4_lat  (
	.scan_in(tid_4_lat_scanin),
	.scan_out(tid_4_lat_scanout),
	.din	(data_3			[58:56]	),
	.dout	(tid_4			[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign mmu_asi_cecc =
       cecc_4;
assign mmu_asi_uecc =
       uecc_4;
assign mmu_asi_tid[2:0] =
       tid_4[2:0];

assign mmu_asi_mra_not_sca =
       ~rd_scratchpad_4;

mmu_asi_ctl_msff_ctl_macro__width_3 sca_index_lat  (
	.scan_in(sca_index_lat_scanin),
	.scan_out(sca_index_lat_scanout),
	.din	(data_3			[5:3]	),
	.dout	(sca_index		[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign mmu_asi_index[2:0] = 
       ({3 {~rd_scratchpad_4}} & mra_addr_4[2:0]) | 
       ({3 { rd_scratchpad_4}} & sca_index [2:0]) ;

// Mux ctl and data
assign rngf_cdbus_2[64:0] =
       {ctl_2,	data_2[63:0]};
assign mra_data[64:0] =
       {1'b0, ase_mra_rd_data[63:0]};
assign mra_tsb_cfg[64:0] =
       {1'b0, tsb_hwtw_en_3, ase_mra_rd_data[62:0]};
assign mra_parity[64:0] =
       {{63 {1'b0}}, 
        (mel0_parity[1:0] & {2 {~data_3[59]}}) |
        (mel1_parity[1:0] & {2 { data_3[59]}}) };
assign dtlb0_tte_data[64:0] =
       {1'b0, {8 {1'b0}}, 1'b0, asd0_dtte_data[54:0]};
assign dtlb1_tte_data[64:0] =
       {1'b0, {8 {1'b0}}, 1'b0, asd1_dtte_data[54:0]};
assign tsb_ptr_data[64:0] =
       {1'b0, {24 {1'b0}}, htd_tsbptr[39:4], {4 {1'b0}}};
assign mra_to_r3 =
       (| pmra_to_r3[1:0]) & data_3[59];
assign mra_not_tsb_cfg =
       mra_to_r3 & ~rd_tsb_cfg_3 & ~rd_mra_parity_3 & ~rd_tsb_ptr_3;
assign mra_sel_tsb_cfg = 
       mra_to_r3 &  rd_tsb_cfg_3 & ~rd_mra_parity_3 & ~rd_tsb_ptr_3;

assign sel_cdbus_2 = 
       ~(| ({use_dtlb_window[1:0], mra_not_tsb_cfg, mra_sel_tsb_cfg, 
             rd_mra_parity_3, rd_tsb_ptr_3}));

// 0in bits_on -var {use_dtlb_window[01:00], sel_cdbus_2, mra_not_tsb_cfg, mra_sel_tsb_cfg, rd_mra_parity_3, rd_tsb_ptr_3} -max 1
assign data_3_in[64:0] =
       ({65 {use_dtlb_window[0]}} & dtlb0_tte_data	[64:0]) |
       ({65 {use_dtlb_window[1]}} & dtlb1_tte_data	[64:0]) |
       ({65 {sel_cdbus_2        }} & rngf_cdbus_2	[64:0]) |
       ({65 {mra_not_tsb_cfg    }} & mra_data		[64:0]) |
       ({65 {mra_sel_tsb_cfg    }} & mra_tsb_cfg	[64:0]) |
       ({65 {rd_mra_parity_3    }} & mra_parity		[64:0]) |
       ({65 {rd_tsb_ptr_3       }} & tsb_ptr_data	[64:0]) ;

		      
/////////////////////////////////////////////////////////////////////
//STAGE 3
/////////////////////////////////////////////////////////////////////
// Mux previous results with TSA reads
// Transmit to TLU

mmu_asi_ctl_msff_ctl_macro__width_65 rng_stg3  (
	.scan_in(rng_stg3_scanin),
	.scan_out(rng_stg3_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(data_3_in	[64:0]	),
	.dout	(data_3		[64:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ctl_3 =
       data_3[64];

assign asi_rd_data[63:0] =
       data_2[63:0];

mmu_asi_ctl_msff_ctl_macro__width_3 stg3_ctl_lat  (
	.scan_in(stg3_ctl_lat_scanin),
	.scan_out(stg3_ctl_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	({mmu_asi_rd_2,
		  rd_tsb_ptr_2,
		  rd_mra_parity_2}),
	.dout	({mmu_asi_rd_3,
		  rd_tsb_ptr_3,
		  rd_mra_parity_3}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 asi_read_lat  (
	.scan_in(asi_read_lat_scanin),
	.scan_out(asi_read_lat_scanout),
	.din	(asi_read_in		),
	.dout	(asi_read		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign mmu_asi_data[64:0] =
       {data_3[64:63],
	data_3[62] | suppress_write_3,
	data_3[61:50],
	(data_3[49:48] & ~{2 {suppress_write_3}}) | {1'b0, suppress_write_3},
	data_3[47:0]};
assign asi_read_in = 
       mmu_asi_rd_3 | dtlb_window_used | dtlb_window_used_last | 
       suppress_write_2;
assign mmu_asi_read = 
       asi_read;


//////////////////////////////////////////////////////////////////////
//
// TTE Management
//
// Once a data_in or data_access register write occurs, the tag and data
// must be transmitted to the TLB and written.
//

assign idata_in_data_access =
       wr_itlb_data_in | wr_itlb_data_access | wr_immu_demap;
assign ddata_in_data_access =
       wr_dtlb_data_in | wr_dtlb_data_access | wr_dmmu_demap;

assign rd_itte_in[7:0] =
       (rd_tid_dec[7:0] & {8 {idata_in_data_access}}) |
       (htc_wr_itlb_data_in[7:0]) |
       (rd_itte   [7:0] & ~tlu_release_tte[7:0]);

assign rd_dtte_in[7:0] =
       (rd_tid_dec[7:0] & {8 {ddata_in_data_access}}) |
       (prd_dtte  [7:0] & clear_data_in_write_[7:0] & ~wrote_dtlb_in[7:0]);

assign sel_rd_dtte_hwtw_in =
       ~(| rd_dtte_in[7:0]);

assign rd_dtte_hwtw_in[7:0] =
	(htc_wr_dtlb_data_in[7:0]) |
	(rd_dtte_hwtw[7:0] & ~wrote_dtlb_in[7:0]) ;
       
mmu_asi_ctl_msff_ctl_macro__width_25 rd_tte_lat  (
	.scan_in(rd_tte_lat_scanin),
	.scan_out(rd_tte_lat_scanout),
	.din	({rd_itte_in		[7:0],
		  rd_dtte_in		[7:0],
		  sel_rd_dtte_hwtw_in	       ,
		  rd_dtte_hwtw_in	[7:0]}),
	.dout	({prd_itte		[7:0],
		  prd_dtte		[7:0],
		  sel_rd_dtte_hwtw	       ,
		  rd_dtte_hwtw		[7:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 idata_in_data_access_2_lat  (
	.scan_in(idata_in_data_access_2_lat_scanin),
	.scan_out(idata_in_data_access_2_lat_scanout),
	.din	(idata_in_data_access		),
	.dout	(idata_in_data_access_2		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign rd_itte[7:0] =
       prd_itte[7:0] & clear_data_in_write_[7:0];

assign rd_dtte[7:0] =
       ({8 {~sel_rd_dtte_hwtw}} & prd_dtte[7:0] & 
	clear_data_in_write_[7:0]) |
       ({8 { sel_rd_dtte_hwtw}} & rd_dtte_hwtw[7:0] & 
        {{4 {dtlb_window[1]}}, {4 {dtlb_window[0]}}});

assign rd_itte_last_in[7:0] = 
	(rd_itte[7:0] & ~tlu_release_tte[7:0]) | htc_wr_itlb_data_in[7:0];

// data must be read same cycle as tlu_release_tte, but no time to control
//	directly
// tag must be read the cycle after tlu_release_tte
assign rd_itte_last_last_in[7:0] = 
       {rd_itte_last[7] & ~(| rd_itte_last[6:0]),
        rd_itte_last[6] & ~(| rd_itte_last[5:0]),
        rd_itte_last[5] & ~(| rd_itte_last[4:0]),
        rd_itte_last[4] & ~(| rd_itte_last[3:0]),
        rd_itte_last[3] & ~(| rd_itte_last[2:0]),
        rd_itte_last[2] & ~(| rd_itte_last[1:0]),
        rd_itte_last[1] & ~(  rd_itte_last[0   ]),
        rd_itte_last[0]                           };

assign rd_itte_data_in[7:0] = 
       rd_itte_last_last[7:0] & {8 {~(| tlu_release_tte[7:0])}};

assign rd_itte_tag_in[7:0] = 
       rd_itte_data[7:0] & tlu_release_tte[7:0];

mmu_asi_ctl_msff_ctl_macro__width_32 rd_itte_lat  (
	.scan_in(rd_itte_lat_scanin),
	.scan_out(rd_itte_lat_scanout),
	.din	({rd_itte_last_in		[7:0],
		  rd_itte_last_last_in		[7:0],
		  rd_itte_data_in		[7:0],
		  rd_itte_tag_in		[7:0]}),
	.dout	({prd_itte_last			[7:0],
		  rd_itte_last_last		[7:0],
		  rd_itte_data			[7:0],
		  rd_itte_tag			[7:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign rd_itte_last[7:0] =
       prd_itte_last[7:0] & ~tlu_release_tte[7:0];

assign asi_rd_itte_tag[7:0] =
       rd_itte_tag[7:0];

assign asi_rd_itte_data[7:0] =
       rd_itte_data[7:0];

assign asi_rd_dtte[6:0] =
       ({7 {~sel_rd_dtte_hwtw}} & prd_dtte    [6:0]) | 
       ({7 { sel_rd_dtte_hwtw}} & rd_dtte_hwtw[6:0]) ;

// Send ITLB reload request to TLU; only assert for one cycle
// Sent in cycle 2 of access
assign mmu_write_itlb[7:0] =
       (wr_tid_dec[7:0] & 
	{8 {idata_in_data_access_2 & legal_data_in_page_size}}) |
       htc_wr_itlb_data_in[7:0];

// Detect hole sufficient for DTLB reload
// If three cycles occur without a control packet, then DTLB write can use the
// last two cycles; the last two cycles are the DTLB window
// The tag and data will be loaded into the stage 2 and 3 flops.
// Bus is idle on a given cycle if ctl and valid are not both 1
assign dtlb_window[1:0] =
       {2 {~(ctl_1 & data_1[63]) & ~(ctl_2 & data_2[63]) & 
	   ~(ctl_3 & data_3[63]) & ~dtlb_window_used_last}};
// 0in req_ack -req wr_dtlb_data_in -ack (| {use_dtlb_window[01:00], (wr_itlb_data_in_2 | wr_itlb_data_access_2 | wr_dtlb_data_in_2 | wr_dtlb_data_access_2) & ~legal_data_in_page_size}) -single_ack off -message "Multiple DTLB updates outstanding for ASI bus from MMU to LSU"

assign use_dtlb_window[1:0] = 
       dtlb_window[1:0] & 
       {(| rd_dtte[7:4]) & ~(| rd_dtte[3:0]),
	(| rd_dtte[3:0])} & {2 {~mbist_run}};

assign dtlb_window_used = 
       | use_dtlb_window[1:0];

mmu_asi_ctl_msff_ctl_macro__width_1 dtlb_window_used_last_lat  (
	.scan_in(dtlb_window_used_last_lat_scanin),
	.scan_out(dtlb_window_used_last_lat_scanout),
	.din	(dtlb_window_used	),
	.dout	(dtlb_window_used_last	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign wrote_dtlb_in[7] = 
       use_dtlb_window[1] & rd_dtte[7] & ~(| rd_dtte[6:4]);
assign wrote_dtlb_in[6] = 
       use_dtlb_window[1] & rd_dtte[6] & ~(| rd_dtte[5:4]);
assign wrote_dtlb_in[5] = 
       use_dtlb_window[1] & rd_dtte[5] & ~   rd_dtte[4   ] ;
assign wrote_dtlb_in[4] = 
       use_dtlb_window[1] & rd_dtte[4]                      ;

assign wrote_dtlb_in[3] = 
       use_dtlb_window[0] & rd_dtte[3] & ~(| rd_dtte[2:0]);
assign wrote_dtlb_in[2] = 
       use_dtlb_window[0] & rd_dtte[2] & ~(| rd_dtte[1:0]);
assign wrote_dtlb_in[1] = 
       use_dtlb_window[0] & rd_dtte[1] & ~   rd_dtte[0   ] ;
assign wrote_dtlb_in[0] = 
       use_dtlb_window[0] & rd_dtte[0]                      ;

// 0in assert_follower -leader ($0in_rising_edge(prd_dtte[07:00]&clear_data_in_write_[07:00])) -follower ($0in_rising_edge(wrote_dtlb_in[07:00])) -min 2 -max 2 -message "DTLB updates are being reordered!"

mmu_asi_ctl_msff_ctl_macro__width_4 wrote_dtlb_tg1_lat  (
	.scan_in(wrote_dtlb_tg1_lat_scanin),
	.scan_out(wrote_dtlb_tg1_lat_scanout),
	.din	(wrote_dtlb_in	[7:4]	),
	.dout	(wrote_dtlb	[7:4]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_4 wrote_dtlb_tg0_lat  (
	.scan_in(wrote_dtlb_tg0_lat_scanin),
	.scan_out(wrote_dtlb_tg0_lat_scanout),
	.din	(wrote_dtlb_in	[3:0]	),
	.dout	(wrote_dtlb	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign reload_done_in[7:0] = 
       htc_wr_itlb_data_in[7:0] | 
       (rd_dtte_hwtw[7:0] & wrote_dtlb_in[7:0]) ;

mmu_asi_ctl_msff_ctl_macro__width_4 reload_done_tg1_lat  (
	.scan_in(reload_done_tg1_lat_scanin),
	.scan_out(reload_done_tg1_lat_scanout),
	.din	(reload_done_in	[7:4]	),
	.dout	(reload_done	[7:4]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_4 reload_done_tg0_lat  (
	.scan_in(reload_done_tg0_lat_scanin),
	.scan_out(reload_done_tg0_lat_scanout),
	.din	(reload_done_in	[3:0]	),
	.dout	(reload_done	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign mmu_reload_done[7:0] =
       reload_done[7:0];


// Block dispatch for DTLB reload
//
// Cycle			0 1 2 3 4 5 6 
//--------------------------------------------------------------------
// dtlb_window          	X
// mmu_asi_data			  X
// tlu_rngf_cdbus       	    X X
// DTLB demap           	          X
// DTLB write           	            X
// hole_in_m            	          X X
// hole_in_e            	        X X
// hole_in_d            	      X X
// mmu_dtlb_reload_stall	    X X
// mmu_dtlb_reload                  X 

assign dtlb_reload_stall_in =
       (| {wrote_dtlb[7:0], dtlb_reload});

mmu_asi_ctl_msff_ctl_macro__width_1 dtlb_reload_stall_lat  (
	.scan_in(dtlb_reload_stall_lat_scanin),
	.scan_out(dtlb_reload_stall_lat_scanout),
	.din	(dtlb_reload_stall_in		),
	.dout	(dtlb_reload_stall		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign mmu_dtlb_reload_stall =
       dtlb_reload_stall;

assign dtlb_reload_in =
       (| wrote_dtlb[7:0]);

mmu_asi_ctl_msff_ctl_macro__width_1 dtlb_reload_lat  (
	.scan_in(dtlb_reload_lat_scanin),
	.scan_out(dtlb_reload_lat_scanout),
	.din	(dtlb_reload_in			),
	.dout	(dtlb_reload			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign mmu_dtlb_reload =
       dtlb_reload;


//////////////////////////////////////////////////////////////////////
//
// Maintain hardware tablewalk enables
//

// Pipe write signals to stage 4 to match write of MRA

assign wr_tsb_cfg_enc[3:0] =
       {wr_z_tsb_cfg_0  | wr_z_tsb_cfg_1  | wr_z_tsb_cfg_2  | wr_z_tsb_cfg_3  |
        wr_nz_tsb_cfg_0 | wr_nz_tsb_cfg_1 | wr_nz_tsb_cfg_2 | wr_nz_tsb_cfg_3 ,
        wr_nz_tsb_cfg_0 | wr_nz_tsb_cfg_1 | wr_nz_tsb_cfg_2 | wr_nz_tsb_cfg_3 ,
        wr_z_tsb_cfg_2  | wr_z_tsb_cfg_3  | wr_nz_tsb_cfg_2 | wr_nz_tsb_cfg_3 ,
        wr_z_tsb_cfg_1  | wr_z_tsb_cfg_3  | wr_nz_tsb_cfg_1 | wr_nz_tsb_cfg_3 
       };

mmu_asi_ctl_msff_ctl_macro__width_12 wr_tsb_cfg_lat  (
	.scan_in(wr_tsb_cfg_lat_scanin),
	.scan_out(wr_tsb_cfg_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	({wr_tsb_cfg_enc	[3:0],
		  wr_tsb_cfg_enc_2	[3:0],
		  wr_tsb_cfg_enc_3	[3:0]}),
	.dout	({wr_tsb_cfg_enc_2	[3:0],
		  wr_tsb_cfg_enc_3	[3:0],
		  wr_tsb_cfg_enc_4	[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign wr_z_tsb_cfg_3_4 =
        wr_tsb_cfg_enc_4[3] & ~wr_tsb_cfg_enc_4[2] & 
        wr_tsb_cfg_enc_4[1] &  wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);

assign wr_z_tsb_cfg_2_4 =
        wr_tsb_cfg_enc_4[3] & ~wr_tsb_cfg_enc_4[2] & 
        wr_tsb_cfg_enc_4[1] & ~wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);

assign wr_z_tsb_cfg_1_4 =
        wr_tsb_cfg_enc_4[3] & ~wr_tsb_cfg_enc_4[2] & 
       ~wr_tsb_cfg_enc_4[1] &  wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);

assign wr_z_tsb_cfg_0_4 =
        wr_tsb_cfg_enc_4[3] & ~wr_tsb_cfg_enc_4[2] & 
       ~wr_tsb_cfg_enc_4[1] & ~wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);

assign wr_nz_tsb_cfg_3_4 =
        wr_tsb_cfg_enc_4[3] &  wr_tsb_cfg_enc_4[2] & 
        wr_tsb_cfg_enc_4[1] &  wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);

assign wr_nz_tsb_cfg_2_4 =
        wr_tsb_cfg_enc_4[3] &  wr_tsb_cfg_enc_4[2] & 
        wr_tsb_cfg_enc_4[1] & ~wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);

assign wr_nz_tsb_cfg_1_4 =
        wr_tsb_cfg_enc_4[3] &  wr_tsb_cfg_enc_4[2] & 
       ~wr_tsb_cfg_enc_4[1] &  wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);

assign wr_nz_tsb_cfg_0_4 =
        wr_tsb_cfg_enc_4[3] &  wr_tsb_cfg_enc_4[2] & 
       ~wr_tsb_cfg_enc_4[1] & ~wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);

assign tid_dec_4[7:0] = 
       { tid_4[2] &  tid_4[1] &  tid_4[0], 
         tid_4[2] &  tid_4[1] & ~tid_4[0], 
         tid_4[2] & ~tid_4[1] &  tid_4[0], 
         tid_4[2] & ~tid_4[1] & ~tid_4[0], 
        ~tid_4[2] &  tid_4[1] &  tid_4[0], 
        ~tid_4[2] &  tid_4[1] & ~tid_4[0], 
        ~tid_4[2] & ~tid_4[1] &  tid_4[0], 
        ~tid_4[2] & ~tid_4[1] & ~tid_4[0]};

assign t7_e_z_in [3] =
        (t7_e_z  [3] & ~(wr_z_tsb_cfg_3_4  & tid_dec_4[7])) |
	(data_3  [63] &  (wr_z_tsb_cfg_3_4  & tid_dec_4[7])) ;
assign t7_e_z_in [2] =			    
        (t7_e_z  [2] & ~(wr_z_tsb_cfg_2_4  & tid_dec_4[7])) |
	(data_3  [63] &  (wr_z_tsb_cfg_2_4  & tid_dec_4[7])) ;
assign t7_e_z_in [1] =			    
        (t7_e_z  [1] & ~(wr_z_tsb_cfg_1_4  & tid_dec_4[7])) |
	(data_3  [63] &  (wr_z_tsb_cfg_1_4  & tid_dec_4[7])) ;
assign t7_e_z_in [0] =			    
        (t7_e_z  [0] & ~(wr_z_tsb_cfg_0_4  & tid_dec_4[7])) |
	(data_3  [63] &  (wr_z_tsb_cfg_0_4  & tid_dec_4[7])) ;
assign t7_e_nz_in[3] =
        (t7_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[7])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_3_4 & tid_dec_4[7])) ;
assign t7_e_nz_in[2] =
        (t7_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[7])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_2_4 & tid_dec_4[7])) ;
assign t7_e_nz_in[1] =
        (t7_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[7])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_1_4 & tid_dec_4[7])) ;
assign t7_e_nz_in[0] =
        (t7_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[7])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_0_4 & tid_dec_4[7])) ;

assign t6_e_z_in [3] =
        (t6_e_z  [3] & ~(wr_z_tsb_cfg_3_4  & tid_dec_4[6])) |
	(data_3  [63] &  (wr_z_tsb_cfg_3_4  & tid_dec_4[6])) ;
assign t6_e_z_in [2] =			    
        (t6_e_z  [2] & ~(wr_z_tsb_cfg_2_4  & tid_dec_4[6])) |
	(data_3  [63] &  (wr_z_tsb_cfg_2_4  & tid_dec_4[6])) ;
assign t6_e_z_in [1] =			    
        (t6_e_z  [1] & ~(wr_z_tsb_cfg_1_4  & tid_dec_4[6])) |
	(data_3  [63] &  (wr_z_tsb_cfg_1_4  & tid_dec_4[6])) ;
assign t6_e_z_in [0] =			    
        (t6_e_z  [0] & ~(wr_z_tsb_cfg_0_4  & tid_dec_4[6])) |
	(data_3  [63] &  (wr_z_tsb_cfg_0_4  & tid_dec_4[6])) ;
assign t6_e_nz_in[3] =
        (t6_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[6])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_3_4 & tid_dec_4[6])) ;
assign t6_e_nz_in[2] =
        (t6_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[6])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_2_4 & tid_dec_4[6])) ;
assign t6_e_nz_in[1] =
        (t6_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[6])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_1_4 & tid_dec_4[6])) ;
assign t6_e_nz_in[0] =
        (t6_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[6])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_0_4 & tid_dec_4[6])) ;

assign t5_e_z_in [3] =
        (t5_e_z  [3] & ~(wr_z_tsb_cfg_3_4  & tid_dec_4[5])) |
	(data_3  [63] &  (wr_z_tsb_cfg_3_4  & tid_dec_4[5])) ;
assign t5_e_z_in [2] =			    
        (t5_e_z  [2] & ~(wr_z_tsb_cfg_2_4  & tid_dec_4[5])) |
	(data_3  [63] &  (wr_z_tsb_cfg_2_4  & tid_dec_4[5])) ;
assign t5_e_z_in [1] =			    
        (t5_e_z  [1] & ~(wr_z_tsb_cfg_1_4  & tid_dec_4[5])) |
	(data_3  [63] &  (wr_z_tsb_cfg_1_4  & tid_dec_4[5])) ;
assign t5_e_z_in [0] =			    
        (t5_e_z  [0] & ~(wr_z_tsb_cfg_0_4  & tid_dec_4[5])) |
	(data_3  [63] &  (wr_z_tsb_cfg_0_4  & tid_dec_4[5])) ;
assign t5_e_nz_in[3] =
        (t5_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[5])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_3_4 & tid_dec_4[5])) ;
assign t5_e_nz_in[2] =
        (t5_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[5])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_2_4 & tid_dec_4[5])) ;
assign t5_e_nz_in[1] =
        (t5_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[5])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_1_4 & tid_dec_4[5])) ;
assign t5_e_nz_in[0] =
        (t5_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[5])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_0_4 & tid_dec_4[5])) ;
	
assign t4_e_z_in [3] =
        (t4_e_z  [3] & ~(wr_z_tsb_cfg_3_4  & tid_dec_4[4])) |
	(data_3  [63] &  (wr_z_tsb_cfg_3_4  & tid_dec_4[4])) ;
assign t4_e_z_in [2] =			    
        (t4_e_z  [2] & ~(wr_z_tsb_cfg_2_4  & tid_dec_4[4])) |
	(data_3  [63] &  (wr_z_tsb_cfg_2_4  & tid_dec_4[4])) ;
assign t4_e_z_in [1] =			    
        (t4_e_z  [1] & ~(wr_z_tsb_cfg_1_4  & tid_dec_4[4])) |
	(data_3  [63] &  (wr_z_tsb_cfg_1_4  & tid_dec_4[4])) ;
assign t4_e_z_in [0] =			    
        (t4_e_z  [0] & ~(wr_z_tsb_cfg_0_4  & tid_dec_4[4])) |
	(data_3  [63] &  (wr_z_tsb_cfg_0_4  & tid_dec_4[4])) ;
assign t4_e_nz_in[3] =
        (t4_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[4])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_3_4 & tid_dec_4[4])) ;
assign t4_e_nz_in[2] =
        (t4_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[4])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_2_4 & tid_dec_4[4])) ;
assign t4_e_nz_in[1] =
        (t4_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[4])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_1_4 & tid_dec_4[4])) ;
assign t4_e_nz_in[0] =
        (t4_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[4])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_0_4 & tid_dec_4[4])) ;

assign t3_e_z_in [3] =
        (t3_e_z  [3] & ~(wr_z_tsb_cfg_3_4  & tid_dec_4[3])) |
	(data_3  [63] &  (wr_z_tsb_cfg_3_4  & tid_dec_4[3])) ;
assign t3_e_z_in [2] =			    
        (t3_e_z  [2] & ~(wr_z_tsb_cfg_2_4  & tid_dec_4[3])) |
	(data_3  [63] &  (wr_z_tsb_cfg_2_4  & tid_dec_4[3])) ;
assign t3_e_z_in [1] =			    
        (t3_e_z  [1] & ~(wr_z_tsb_cfg_1_4  & tid_dec_4[3])) |
	(data_3  [63] &  (wr_z_tsb_cfg_1_4  & tid_dec_4[3])) ;
assign t3_e_z_in [0] =			    
        (t3_e_z  [0] & ~(wr_z_tsb_cfg_0_4  & tid_dec_4[3])) |
	(data_3  [63] &  (wr_z_tsb_cfg_0_4  & tid_dec_4[3])) ;
assign t3_e_nz_in[3] =
        (t3_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[3])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_3_4 & tid_dec_4[3])) ;
assign t3_e_nz_in[2] =
        (t3_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[3])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_2_4 & tid_dec_4[3])) ;
assign t3_e_nz_in[1] =
        (t3_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[3])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_1_4 & tid_dec_4[3])) ;
assign t3_e_nz_in[0] =
        (t3_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[3])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_0_4 & tid_dec_4[3])) ;

assign t2_e_z_in [3] =
        (t2_e_z  [3] & ~(wr_z_tsb_cfg_3_4  & tid_dec_4[2])) |
	(data_3  [63] &  (wr_z_tsb_cfg_3_4  & tid_dec_4[2])) ;
assign t2_e_z_in [2] =			    
        (t2_e_z  [2] & ~(wr_z_tsb_cfg_2_4  & tid_dec_4[2])) |
	(data_3  [63] &  (wr_z_tsb_cfg_2_4  & tid_dec_4[2])) ;
assign t2_e_z_in [1] =			    
        (t2_e_z  [1] & ~(wr_z_tsb_cfg_1_4  & tid_dec_4[2])) |
	(data_3  [63] &  (wr_z_tsb_cfg_1_4  & tid_dec_4[2])) ;
assign t2_e_z_in [0] =			    
        (t2_e_z  [0] & ~(wr_z_tsb_cfg_0_4  & tid_dec_4[2])) |
	(data_3  [63] &  (wr_z_tsb_cfg_0_4  & tid_dec_4[2])) ;
assign t2_e_nz_in[3] =
        (t2_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[2])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_3_4 & tid_dec_4[2])) ;
assign t2_e_nz_in[2] =
        (t2_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[2])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_2_4 & tid_dec_4[2])) ;
assign t2_e_nz_in[1] =
        (t2_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[2])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_1_4 & tid_dec_4[2])) ;
assign t2_e_nz_in[0] =
        (t2_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[2])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_0_4 & tid_dec_4[2])) ;

assign t1_e_z_in [3] =
        (t1_e_z  [3] & ~(wr_z_tsb_cfg_3_4  & tid_dec_4[1])) |
	(data_3  [63] &  (wr_z_tsb_cfg_3_4  & tid_dec_4[1])) ;
assign t1_e_z_in [2] =			    
        (t1_e_z  [2] & ~(wr_z_tsb_cfg_2_4  & tid_dec_4[1])) |
	(data_3  [63] &  (wr_z_tsb_cfg_2_4  & tid_dec_4[1])) ;
assign t1_e_z_in [1] =			    
        (t1_e_z  [1] & ~(wr_z_tsb_cfg_1_4  & tid_dec_4[1])) |
	(data_3  [63] &  (wr_z_tsb_cfg_1_4  & tid_dec_4[1])) ;
assign t1_e_z_in [0] =			    
        (t1_e_z  [0] & ~(wr_z_tsb_cfg_0_4  & tid_dec_4[1])) |
	(data_3  [63] &  (wr_z_tsb_cfg_0_4  & tid_dec_4[1])) ;
assign t1_e_nz_in[3] =
        (t1_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[1])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_3_4 & tid_dec_4[1])) ;
assign t1_e_nz_in[2] =
        (t1_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[1])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_2_4 & tid_dec_4[1])) ;
assign t1_e_nz_in[1] =
        (t1_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[1])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_1_4 & tid_dec_4[1])) ;
assign t1_e_nz_in[0] =
        (t1_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[1])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_0_4 & tid_dec_4[1])) ;

assign t0_e_z_in [3] =
        (t0_e_z  [3] & ~(wr_z_tsb_cfg_3_4  & tid_dec_4[0])) |
	(data_3  [63] &  (wr_z_tsb_cfg_3_4  & tid_dec_4[0])) ;
assign t0_e_z_in [2] =			    
        (t0_e_z  [2] & ~(wr_z_tsb_cfg_2_4  & tid_dec_4[0])) |
	(data_3  [63] &  (wr_z_tsb_cfg_2_4  & tid_dec_4[0])) ;
assign t0_e_z_in [1] =			    
        (t0_e_z  [1] & ~(wr_z_tsb_cfg_1_4  & tid_dec_4[0])) |
	(data_3  [63] &  (wr_z_tsb_cfg_1_4  & tid_dec_4[0])) ;
assign t0_e_z_in [0] =			    
        (t0_e_z  [0] & ~(wr_z_tsb_cfg_0_4  & tid_dec_4[0])) |
	(data_3  [63] &  (wr_z_tsb_cfg_0_4  & tid_dec_4[0])) ;
assign t0_e_nz_in[3] =
        (t0_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[0])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_3_4 & tid_dec_4[0])) ;
assign t0_e_nz_in[2] =
        (t0_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[0])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_2_4 & tid_dec_4[0])) ;
assign t0_e_nz_in[1] =
        (t0_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[0])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_1_4 & tid_dec_4[0])) ;
assign t0_e_nz_in[0] =
        (t0_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[0])) |
	(data_3  [63] &  (wr_nz_tsb_cfg_0_4 & tid_dec_4[0])) ;

mmu_asi_ctl_msff_ctl_macro__width_64 hw_tw_e_lat  ( // FS:wmr_protect
	.scan_in(hw_tw_e_lat_wmr_scanin),
	.scan_out(hw_tw_e_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	({t7_e_z_in	[3:0],
		  t7_e_nz_in	[3:0],
		  t6_e_z_in	[3:0],
		  t6_e_nz_in	[3:0],
		  t5_e_z_in	[3:0],
		  t5_e_nz_in	[3:0],
		  t4_e_z_in	[3:0],
		  t4_e_nz_in	[3:0],
		  t3_e_z_in	[3:0],
		  t3_e_nz_in	[3:0],
		  t2_e_z_in	[3:0],
		  t2_e_nz_in	[3:0],
		  t1_e_z_in	[3:0],
		  t1_e_nz_in	[3:0],
		  t0_e_z_in	[3:0],
		  t0_e_nz_in	[3:0]}),
	.dout	({t7_e_z   	[3:0],
		  t7_e_nz   	[3:0],
		  t6_e_z   	[3:0],
		  t6_e_nz   	[3:0],
		  t5_e_z   	[3:0],
		  t5_e_nz   	[3:0],
		  t4_e_z   	[3:0],
		  t4_e_nz   	[3:0],
		  t3_e_z   	[3:0],
		  t3_e_nz   	[3:0],
		  t2_e_z   	[3:0],
		  t2_e_nz   	[3:0],
		  t1_e_z   	[3:0],
		  t1_e_nz   	[3:0],
		  t0_e_z   	[3:0],
		  t0_e_nz   	[3:0]}),
  .l1clk(l1clk),
  .soclk(soclk)
);

assign mmu_hw_tw_enable[7] =
	(| {t7_e_z[3:0], t7_e_nz[3:0]});
assign mmu_hw_tw_enable[6] =
	(| {t6_e_z[3:0], t6_e_nz[3:0]});
assign mmu_hw_tw_enable[5] =
	(| {t5_e_z[3:0], t5_e_nz[3:0]});
assign mmu_hw_tw_enable[4] =
	(| {t4_e_z[3:0], t4_e_nz[3:0]});
assign mmu_hw_tw_enable[3] =
	(| {t3_e_z[3:0], t3_e_nz[3:0]});
assign mmu_hw_tw_enable[2] =
	(| {t2_e_z[3:0], t2_e_nz[3:0]});
assign mmu_hw_tw_enable[1] =
	(| {t1_e_z[3:0], t1_e_nz[3:0]});
assign mmu_hw_tw_enable[0] =
	(| {t0_e_z[3:0], t0_e_nz[3:0]});

// Mux the enables for ASI read
assign hwtw_enables[7:0] =
       ({t7_e_z[3:0], t7_e_nz[3:0]} & {8 {rd_tid_dec[7]}}) |
       ({t6_e_z[3:0], t6_e_nz[3:0]} & {8 {rd_tid_dec[6]}}) |
       ({t5_e_z[3:0], t5_e_nz[3:0]} & {8 {rd_tid_dec[5]}}) |
       ({t4_e_z[3:0], t4_e_nz[3:0]} & {8 {rd_tid_dec[4]}}) |
       ({t3_e_z[3:0], t3_e_nz[3:0]} & {8 {rd_tid_dec[3]}}) |
       ({t2_e_z[3:0], t2_e_nz[3:0]} & {8 {rd_tid_dec[2]}}) |
       ({t1_e_z[3:0], t1_e_nz[3:0]} & {8 {rd_tid_dec[1]}}) |
       ({t0_e_z[3:0], t0_e_nz[3:0]} & {8 {rd_tid_dec[0]}}) ;
       
assign tsb_hwtw_en_1 =
       (hwtw_enables[7] &  z_tsb_cfg_3) |
       (hwtw_enables[6] &  z_tsb_cfg_2) |
       (hwtw_enables[5] &  z_tsb_cfg_1) |
       (hwtw_enables[4] &  z_tsb_cfg_0) |
       (hwtw_enables[3] & nz_tsb_cfg_3) |
       (hwtw_enables[2] & nz_tsb_cfg_2) |
       (hwtw_enables[1] & nz_tsb_cfg_1) |
       (hwtw_enables[0] & nz_tsb_cfg_0) ;

mmu_asi_ctl_msff_ctl_macro__width_2 tsb_hwtw_en_lat  (
	.scan_in(tsb_hwtw_en_lat_scanin),
	.scan_out(tsb_hwtw_en_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	({tsb_hwtw_en_1	       ,
		  tsb_hwtw_en_2	       }),
	.dout	({tsb_hwtw_en_2	       ,
		  tsb_hwtw_en_3	       }),
  .siclk(siclk),
  .soclk(soclk)
);

// Mux the enables for HW TW read
mmu_asi_ctl_msff_ctl_macro__width_4 htc_mra_addr_lat  (
	.scan_in(htc_mra_addr_lat_scanin),
	.scan_out(htc_mra_addr_lat_scanout),
	.din	({htc_mra_addr_in	[4:3],
		  htc_mra_addr_in	[1:0]}),
	.dout	({htc_mra_addr		[4:3],
		  htc_mra_addr		[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign htc_tid_dec[3:0] =
       { htc_mra_addr[4] &  htc_mra_addr[3], 
         htc_mra_addr[4] & ~htc_mra_addr[3], 
        ~htc_mra_addr[4] &  htc_mra_addr[3], 
        ~htc_mra_addr[4] & ~htc_mra_addr[3]}; 

assign htc_enables_1_2[7:0] =
       ({t7_e_z[3:0], t7_e_nz[3:0]} & {8 {htc_tid_dec[3]}}) |
       ({t6_e_z[3:0], t6_e_nz[3:0]} & {8 {htc_tid_dec[2]}}) |
       ({t5_e_z[3:0], t5_e_nz[3:0]} & {8 {htc_tid_dec[1]}}) |
       ({t4_e_z[3:0], t4_e_nz[3:0]} & {8 {htc_tid_dec[0]}}) ;

assign htc_enables_0_2[7:0] =
       ({t3_e_z[3:0], t3_e_nz[3:0]} & {8 {htc_tid_dec[3]}}) |
       ({t2_e_z[3:0], t2_e_nz[3:0]} & {8 {htc_tid_dec[2]}}) |
       ({t1_e_z[3:0], t1_e_nz[3:0]} & {8 {htc_tid_dec[1]}}) |
       ({t0_e_z[3:0], t0_e_nz[3:0]} & {8 {htc_tid_dec[0]}}) ;

assign htc_sel_tsb_cfg[3:0] =
       {~htc_mra_addr[1] &  htc_mra_addr[0], 
        ~htc_mra_addr[1] & ~htc_mra_addr[0], 
         htc_mra_addr[1] &  htc_mra_addr[0], 
         htc_mra_addr[1] & ~htc_mra_addr[0]}; 

assign htc_hwtw_en_1_2[1:0] =
       (htc_enables_1_2[7:6] & {2 {htc_sel_tsb_cfg[3]}}) | 
       (htc_enables_1_2[5:4] & {2 {htc_sel_tsb_cfg[2]}}) | 
       (htc_enables_1_2[3:2] & {2 {htc_sel_tsb_cfg[1]}}) | 
       (htc_enables_1_2[1:0] & {2 {htc_sel_tsb_cfg[0]}}) ;

assign htc_hwtw_en_0_2[1:0] =
       (htc_enables_0_2[7:6] & {2 {htc_sel_tsb_cfg[3]}}) | 
       (htc_enables_0_2[5:4] & {2 {htc_sel_tsb_cfg[2]}}) | 
       (htc_enables_0_2[3:2] & {2 {htc_sel_tsb_cfg[1]}}) | 
       (htc_enables_0_2[1:0] & {2 {htc_sel_tsb_cfg[0]}}) ;

assign asi_tsb_hwtw_enable_1[1:0] =
       htc_hwtw_en_1_2[1:0];

assign asi_tsb_hwtw_enable_0[1:0] =
       htc_hwtw_en_0_2[1:0];


//////////////////////////////////////////////////////////////////////////////
//
// Flop data_access index & valid and send to IFU
//

assign index_in[6:0] =
       asd0_itte_index[6:0] | asd1_itte_index[6:0];

mmu_asi_ctl_msff_ctl_macro__width_7 data_access_index_lat  (
	.scan_in(data_access_index_lat_scanin),
	.scan_out(data_access_index_lat_scanout),
	.din	(index_in		[6:0]	),
	.dout	(mmu_index		[6:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


//////////////////////////////////////////////////////////////////////////////
//
// 
//

mmu_asi_ctl_msff_ctl_macro__width_11 error_inject_lat  (
	.scan_in(error_inject_lat_scanin),
	.scan_out(error_inject_lat_scanout),
	.din	({error_inject_enable,
		  error_inject_scau,
		  error_inject_mrau,
		  error_inject_mask	[7:0]}),
	.dout	({error_enable,
		  error_scau,
		  error_mrau,
		  error_mask		[7:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_error_scau =
       error_enable & error_scau;
assign asi_error_mrau =
       error_enable & error_mrau;
assign asi_error_mask[7:0] =
       error_mask[7:0];


//////////////////////////////////////////////////////////////////////////////
//
//  Tag access power management
//

mmu_asi_ctl_msff_ctl_macro__width_2 tag_access_tid_0_lat  (
	.scan_in(tag_access_tid_0_lat_scanin),
	.scan_out(tag_access_tid_0_lat_scanout),
	.din	(tlu_tag_access_tid_0_b	[1:0]	),
	.dout	(tag_access_tid_0	[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 i_tag_access_0_lat  (
	.scan_in(i_tag_access_0_lat_scanin),
	.scan_out(i_tag_access_0_lat_scanout),
	.din	(tlu_i_tag_access_0_b		),
	.dout	(i_tag_access_0			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 d_tag_access_0_lat  (
	.scan_in(d_tag_access_0_lat_scanin),
	.scan_out(d_tag_access_0_lat_scanout),
	.din	(tlu_d_tag_access_0_b		),
	.dout	(d_tag_access_0			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_2 tag_access_tid_1_lat  (
	.scan_in(tag_access_tid_1_lat_scanin),
	.scan_out(tag_access_tid_1_lat_scanout),
	.din	(tlu_tag_access_tid_1_b	[1:0]	),
	.dout	(tag_access_tid_1	[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 i_tag_access_1_lat  (
	.scan_in(i_tag_access_1_lat_scanin),
	.scan_out(i_tag_access_1_lat_scanout),
	.din	(tlu_i_tag_access_1_b		),
	.dout	(i_tag_access_1			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_asi_ctl_msff_ctl_macro__width_1 d_tag_access_1_lat  (
	.scan_in(d_tag_access_1_lat_scanin),
	.scan_out(d_tag_access_1_lat_scanout),
	.din	(tlu_d_tag_access_1_b		),
	.dout	(d_tag_access_1			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign i_tag_access_exc[7:0] =
       {(tag_access_tid_1[1:0] == 2'b11) & i_tag_access_1,
	(tag_access_tid_1[1:0] == 2'b10) & i_tag_access_1,
	(tag_access_tid_1[1:0] == 2'b01) & i_tag_access_1,
	(tag_access_tid_1[1:0] == 2'b00) & i_tag_access_1,
	(tag_access_tid_0[1:0] == 2'b11) & i_tag_access_0,
	(tag_access_tid_0[1:0] == 2'b10) & i_tag_access_0,
	(tag_access_tid_0[1:0] == 2'b01) & i_tag_access_0,
	(tag_access_tid_0[1:0] == 2'b00) & i_tag_access_0};

assign d_tag_access_exc[7:0] =
       {(tag_access_tid_1[1:0] == 2'b11) & d_tag_access_1,
	(tag_access_tid_1[1:0] == 2'b10) & d_tag_access_1,
	(tag_access_tid_1[1:0] == 2'b01) & d_tag_access_1,
	(tag_access_tid_1[1:0] == 2'b00) & d_tag_access_1,
	(tag_access_tid_0[1:0] == 2'b11) & d_tag_access_0,
	(tag_access_tid_0[1:0] == 2'b10) & d_tag_access_0,
	(tag_access_tid_0[1:0] == 2'b01) & d_tag_access_0,
	(tag_access_tid_0[1:0] == 2'b00) & d_tag_access_0};

assign asi_i_tag_access_en[7:0] =
       i_tag_access_exc[7:0] | 
       a_wr_immu_tag_access[7:0] |
       a_wr_immu_demap[7:0] |
       htc_itlb_clken[7:0];

assign asi_d_tag_access_en[7:0] =
       d_tag_access_exc[7:0] | 
       a_wr_dmmu_tag_access[7:0] |
       a_wr_dmmu_demap[7:0] |
       htc_dtlb_clken[7:0];


//////////////////////////////////////////////////////////////////////////////
//
//  Data in power management
//

assign asi_i_data_in_en[7:0] =
       a_wr_itlb_data_in[7:0] |
       a_wr_itlb_data_access[7:0] |
       a_wr_immu_demap[7:0] |
       htc_itlb_clken[7:0];

assign asi_d_data_in_en[7:0] =
       a_wr_dtlb_data_in[7:0] |
       a_wr_dtlb_data_access[7:0] |
       a_wr_dmmu_demap[7:0] |
       htc_dtlb_clken[7:0];


//////////////////////////////////////////////////////////////////////////////
//
// Tablewalk in progress registers
//

assign write_stp[7:0] =
       {8 {wr_t_p_c_2}} & wr_tid_dec[7:0];

assign stp_in[7:0] =
       ( write_stp[7:0] & {8 {data_1[0]}}) |
       (~write_stp[7:0] & stp[7:0]      ) ;

mmu_asi_ctl_msff_ctl_macro__width_8 stp_lat  (
	.scan_in(stp_lat_scanin),
	.scan_out(stp_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(stp_in		[7:0]	),
	.dout	(stp		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign set_htp[7:0] = 
       tlu_iht_request[7:0] | tlu_dht_request[7:0];

// Can clear htp when hardware tablewalk fails
// but on successful hardware tablewalk, must wait until the write to the
// TLB is in progress and no longer pending
assign clr_htp[7:0] =
       tlu_release_tte[7:0] | 
       (rd_dtte_hwtw[7:0] & wrote_dtlb_in[7:0]) |
       mmu_i_unauth_access[7:0] |  
       mmu_i_tsb_miss[7:0] | mmu_d_tsb_miss[7:0] |
       mmu_i_tte_outofrange[7:0] | mmu_d_tte_outofrange[7:0] |
       mmu_i_eccerr[7:0] | mmu_d_eccerr[7:0];

assign htp_in[7:0] =
       set_htp[7:0] | (htp[7:0] & ~clr_htp[7:0]);

mmu_asi_ctl_msff_ctl_macro__width_8 htp_lat  (
	.scan_in(htp_lat_scanin),
	.scan_out(htp_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(htp_in		[7:0]	),
	.dout	(htp		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign rd_t_p_c_data[63:0] =
       {{63 {1'b0}}, | (stp[7:0] & wr_tid_dec[7:0])};

assign rd_t_p_s_data[63:0] =
       {{24 {1'b0}}, htp[7:0], {24 {1'b0}}, stp[7:0]};


//////////////////////////////////////////////////////////////////////////////
//
// Spares
//

mmu_asi_ctl_spare_ctl_macro__num_12 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk				),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

// fixscan start:
assign stg1_en_lat_scanin        = scan_in                  ;
assign stg2_en_lat_scanin        = stg1_en_lat_scanout      ;
assign stg3_en_lat_scanin        = stg2_en_lat_scanout      ;
assign stg4_en_lat_scanin        = stg3_en_lat_scanout      ;
assign mbist_run_lat_scanin      = stg4_en_lat_scanout      ;
assign mra0_wr_en_lat_scanin     = mbist_run_lat_scanout    ;
assign mra1_wr_en_lat_scanin     = mra0_wr_en_lat_scanout   ;
assign scp0_wr_en_lat_scanin     = mra1_wr_en_lat_scanout   ;
assign scp1_wr_en_lat_scanin     = scp0_wr_en_lat_scanout   ;
assign mbist_addr_lat_scanin     = scp1_wr_en_lat_scanout   ;
assign mbist_wdata_lat_scanin    = mbist_addr_lat_scanout   ;
assign mra0_rd_en_lat_scanin     = mbist_wdata_lat_scanout  ;
assign mra1_rd_en_lat_scanin     = mra0_rd_en_lat_scanout   ;
assign scp0_rd_en_lat_scanin     = mra1_rd_en_lat_scanout   ;
assign scp1_rd_en_lat_scanin     = scp0_rd_en_lat_scanout   ;
assign mbist_cmpsel_lat_scanin   = scp1_rd_en_lat_scanout   ;
assign mra0_wr_en_2_lat_scanin   = mbist_cmpsel_lat_scanout ;
assign mra1_wr_en_2_lat_scanin   = mra0_wr_en_2_lat_scanout ;
assign mra0_rd_en_2_lat_scanin   = mra1_wr_en_2_lat_scanout ;
assign mra1_rd_en_2_lat_scanin   = mra0_rd_en_2_lat_scanout ;
assign scp0_rd_en_2_lat_scanin   = mra1_rd_en_2_lat_scanout ;
assign scp1_rd_en_2_lat_scanin   = scp0_rd_en_2_lat_scanout ;
assign mbist_addr_2_lat_scanin   = scp1_rd_en_2_lat_scanout ;
assign mbist_cmpsel_2_lat_scanin = mbist_addr_2_lat_scanout ;
assign mbist_compare_data_lat_scanin = mbist_cmpsel_2_lat_scanout;
assign mra0_rd_en_3_lat_scanin   = mbist_compare_data_lat_scanout;
assign mra1_rd_en_3_lat_scanin   = mra0_rd_en_3_lat_scanout ;
assign scp0_rd_en_3_lat_scanin   = mra1_rd_en_3_lat_scanout ;
assign scp1_rd_en_3_lat_scanin   = scp0_rd_en_3_lat_scanout ;
assign mra0_rd_en_4_lat_scanin   = scp1_rd_en_3_lat_scanout ;
assign mra1_rd_en_4_lat_scanin   = mra0_rd_en_4_lat_scanout ;
assign mra0_fail_lat_scanin      = mra1_rd_en_4_lat_scanout ;
assign mra1_fail_lat_scanin      = mra0_fail_lat_scanout    ;
assign scp0_fail_lat_scanin      = mra1_fail_lat_scanout    ;
assign scp1_fail_lat_scanin      = scp0_fail_lat_scanout    ;
assign rng_stg1_data_scanin      = scp1_fail_lat_scanout    ;
assign ctl_1_lat_scanin          = rng_stg1_data_scanout    ;
assign scp_ctl_lat_scanin        = ctl_1_lat_scanout        ;
assign rd_scratchpad_4_lat_scanin = scp_ctl_lat_scanout      ;
assign req_grant_lat_scanin      = rd_scratchpad_4_lat_scanout;
assign mra_addr_lat_scanin       = req_grant_lat_scanout    ;
assign mra_rd_en_lat_scanin      = mra_addr_lat_scanout     ;
assign mra_wr_en_lat_scanin      = mra_rd_en_lat_scanout    ;
assign mra_wr_en_4_lat_scanin    = mra_wr_en_lat_scanout    ;
assign mra_sel_lat_scanin        = mra_wr_en_4_lat_scanout  ;
assign stg2_data_lat_scanin      = mra_sel_lat_scanout      ;
assign stg2_ctl_lat_scanin       = stg2_data_lat_scanout    ;
assign dae_req_lat_scanin        = stg2_ctl_lat_scanout     ;
assign check_ecc_lat_scanin      = dae_req_lat_scanout      ;
assign pmra_to_r4_lat_scanin     = check_ecc_lat_scanout    ;
assign tid_4_lat_scanin          = pmra_to_r4_lat_scanout   ;
assign sca_index_lat_scanin      = tid_4_lat_scanout        ;
assign rng_stg3_scanin           = sca_index_lat_scanout    ;
assign stg3_ctl_lat_scanin       = rng_stg3_scanout         ;
assign asi_read_lat_scanin       = stg3_ctl_lat_scanout     ;
assign rd_tte_lat_scanin         = asi_read_lat_scanout     ;
assign idata_in_data_access_2_lat_scanin = rd_tte_lat_scanout       ;
assign rd_itte_lat_scanin        = idata_in_data_access_2_lat_scanout;
assign dtlb_window_used_last_lat_scanin = rd_itte_lat_scanout      ;
assign wrote_dtlb_tg1_lat_scanin = dtlb_window_used_last_lat_scanout;
assign wrote_dtlb_tg0_lat_scanin = wrote_dtlb_tg1_lat_scanout;
assign reload_done_tg1_lat_scanin = wrote_dtlb_tg0_lat_scanout;
assign reload_done_tg0_lat_scanin = reload_done_tg1_lat_scanout;
assign dtlb_reload_stall_lat_scanin = reload_done_tg0_lat_scanout;
assign dtlb_reload_lat_scanin    = dtlb_reload_stall_lat_scanout;
assign wr_tsb_cfg_lat_scanin     = dtlb_reload_lat_scanout  ;
assign tsb_hwtw_en_lat_scanin    = wr_tsb_cfg_lat_scanout   ;
assign htc_mra_addr_lat_scanin   = tsb_hwtw_en_lat_scanout  ;
assign data_access_index_lat_scanin = htc_mra_addr_lat_scanout ;
assign error_inject_lat_scanin   = data_access_index_lat_scanout;
assign tag_access_tid_0_lat_scanin = error_inject_lat_scanout ;
assign i_tag_access_0_lat_scanin = tag_access_tid_0_lat_scanout;
assign d_tag_access_0_lat_scanin = i_tag_access_0_lat_scanout;
assign tag_access_tid_1_lat_scanin = d_tag_access_0_lat_scanout;
assign i_tag_access_1_lat_scanin = tag_access_tid_1_lat_scanout;
assign d_tag_access_1_lat_scanin = i_tag_access_1_lat_scanout;
assign stp_lat_scanin            = d_tag_access_1_lat_scanout;
assign htp_lat_scanin            = stp_lat_scanout          ;
assign spares_scanin             = htp_lat_scanout          ;
assign scan_out                  = spares_scanout           ;

assign hwtw_config_0_lat_wmr_scanin = wmr_scan_in              ;
assign hwtw_config_1_lat_wmr_scanin = hwtw_config_0_lat_wmr_scanout;
assign hwtw_config_2_lat_wmr_scanin = hwtw_config_1_lat_wmr_scanout;
assign hwtw_config_3_lat_wmr_scanin = hwtw_config_2_lat_wmr_scanout;
assign hwtw_config_4_lat_wmr_scanin = hwtw_config_3_lat_wmr_scanout;
assign hwtw_config_5_lat_wmr_scanin = hwtw_config_4_lat_wmr_scanout;
assign hwtw_config_6_lat_wmr_scanin = hwtw_config_5_lat_wmr_scanout;
assign hwtw_config_7_lat_wmr_scanin = hwtw_config_6_lat_wmr_scanout;
assign hw_tw_e_lat_wmr_scanin    = hwtw_config_7_lat_wmr_scanout;
assign wmr_scan_out              = hw_tw_e_lat_wmr_scanout  ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_64 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [63:0] fdin;
wire [62:0] so;

  input [63:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [63:0] dout;
  output scan_out;
assign fdin[63:0] = din[63:0];


dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_15 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [14:0] fdin;
wire [13:0] so;

  input [14:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [14:0] dout;
  output scan_out;
assign fdin[14:0] = din[14:0];


dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[14:0]),
.si({scan_in,so[13:0]}),
.so({so[13:0],scan_out}),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_65 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [64:0] fdin;
wire [63:0] so;

  input [64:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [64:0] dout;
  output scan_out;
assign fdin[64:0] = din[64:0];


dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_25 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [24:0] fdin;
wire [23:0] so;

  input [24:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [24:0] dout;
  output scan_out;
assign fdin[24:0] = din[24:0];


dff #(25)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[24:0]),
.si({scan_in,so[23:0]}),
.so({so[23:0],scan_out}),
.q(dout[24:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_32 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [30:0] so;

  input [31:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = din[31:0];


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_asi_ctl_msff_ctl_macro__width_11 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [10:0] fdin;
wire [9:0] so;

  input [10:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [10:0] dout;
  output scan_out;
assign fdin[10:0] = din[10:0];


dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module mmu_asi_ctl_spare_ctl_macro__num_12 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire si_8;
wire so_8;
wire spare8_flop_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;
wire si_9;
wire so_9;
wire spare9_flop_unused;
wire spare9_buf_32x_unused;
wire spare9_nand3_8x_unused;
wire spare9_inv_8x_unused;
wire spare9_aoi22_4x_unused;
wire spare9_buf_8x_unused;
wire spare9_oai22_4x_unused;
wire spare9_inv_16x_unused;
wire spare9_nand2_16x_unused;
wire spare9_nor3_4x_unused;
wire spare9_nand2_8x_unused;
wire spare9_buf_16x_unused;
wire spare9_nor2_16x_unused;
wire spare9_inv_32x_unused;
wire si_10;
wire so_10;
wire spare10_flop_unused;
wire spare10_buf_32x_unused;
wire spare10_nand3_8x_unused;
wire spare10_inv_8x_unused;
wire spare10_aoi22_4x_unused;
wire spare10_buf_8x_unused;
wire spare10_oai22_4x_unused;
wire spare10_inv_16x_unused;
wire spare10_nand2_16x_unused;
wire spare10_nor3_4x_unused;
wire spare10_nand2_8x_unused;
wire spare10_buf_16x_unused;
wire spare10_nor2_16x_unused;
wire spare10_inv_32x_unused;
wire si_11;
wire so_11;
wire spare11_flop_unused;
wire spare11_buf_32x_unused;
wire spare11_nand3_8x_unused;
wire spare11_inv_8x_unused;
wire spare11_aoi22_4x_unused;
wire spare11_buf_8x_unused;
wire spare11_oai22_4x_unused;
wire spare11_inv_16x_unused;
wire spare11_nand2_16x_unused;
wire spare11_nor3_4x_unused;
wire spare11_nand2_8x_unused;
wire spare11_buf_16x_unused;
wire spare11_nor2_16x_unused;
wire spare11_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));

cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_8),
                               .so(so_8),
                               .d(1'b0),
                               .q(spare8_flop_unused));
assign si_8 = so_7;

cl_u1_buf_32x   spare8_buf_32x (.in(1'b1),
                                   .out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare8_nand3_8x_unused));
cl_u1_inv_8x    spare8_inv_8x (.in(1'b1),
                                  .out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_aoi22_4x_unused));
cl_u1_buf_8x    spare8_buf_8x (.in(1'b1),
                                  .out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_oai22_4x_unused));
cl_u1_inv_16x   spare8_inv_16x (.in(1'b1),
                                   .out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare8_nand2_8x_unused));
cl_u1_buf_16x   spare8_buf_16x (.in(1'b1),
                                   .out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare8_nor2_16x_unused));
cl_u1_inv_32x   spare8_inv_32x (.in(1'b1),
                                   .out(spare8_inv_32x_unused));

cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_9),
                               .so(so_9),
                               .d(1'b0),
                               .q(spare9_flop_unused));
assign si_9 = so_8;

cl_u1_buf_32x   spare9_buf_32x (.in(1'b1),
                                   .out(spare9_buf_32x_unused));
cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare9_nand3_8x_unused));
cl_u1_inv_8x    spare9_inv_8x (.in(1'b1),
                                  .out(spare9_inv_8x_unused));
cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_aoi22_4x_unused));
cl_u1_buf_8x    spare9_buf_8x (.in(1'b1),
                                  .out(spare9_buf_8x_unused));
cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_oai22_4x_unused));
cl_u1_inv_16x   spare9_inv_16x (.in(1'b1),
                                   .out(spare9_inv_16x_unused));
cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare9_nand2_16x_unused));
cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare9_nor3_4x_unused));
cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare9_nand2_8x_unused));
cl_u1_buf_16x   spare9_buf_16x (.in(1'b1),
                                   .out(spare9_buf_16x_unused));
cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare9_nor2_16x_unused));
cl_u1_inv_32x   spare9_inv_32x (.in(1'b1),
                                   .out(spare9_inv_32x_unused));

cl_sc1_msff_8x spare10_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_10),
                               .so(so_10),
                               .d(1'b0),
                               .q(spare10_flop_unused));
assign si_10 = so_9;

cl_u1_buf_32x   spare10_buf_32x (.in(1'b1),
                                   .out(spare10_buf_32x_unused));
cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare10_nand3_8x_unused));
cl_u1_inv_8x    spare10_inv_8x (.in(1'b1),
                                  .out(spare10_inv_8x_unused));
cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare10_aoi22_4x_unused));
cl_u1_buf_8x    spare10_buf_8x (.in(1'b1),
                                  .out(spare10_buf_8x_unused));
cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare10_oai22_4x_unused));
cl_u1_inv_16x   spare10_inv_16x (.in(1'b1),
                                   .out(spare10_inv_16x_unused));
cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare10_nand2_16x_unused));
cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare10_nor3_4x_unused));
cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare10_nand2_8x_unused));
cl_u1_buf_16x   spare10_buf_16x (.in(1'b1),
                                   .out(spare10_buf_16x_unused));
cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare10_nor2_16x_unused));
cl_u1_inv_32x   spare10_inv_32x (.in(1'b1),
                                   .out(spare10_inv_32x_unused));

cl_sc1_msff_8x spare11_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_11),
                               .so(so_11),
                               .d(1'b0),
                               .q(spare11_flop_unused));
assign si_11 = so_10;

cl_u1_buf_32x   spare11_buf_32x (.in(1'b1),
                                   .out(spare11_buf_32x_unused));
cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare11_nand3_8x_unused));
cl_u1_inv_8x    spare11_inv_8x (.in(1'b1),
                                  .out(spare11_inv_8x_unused));
cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare11_aoi22_4x_unused));
cl_u1_buf_8x    spare11_buf_8x (.in(1'b1),
                                  .out(spare11_buf_8x_unused));
cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare11_oai22_4x_unused));
cl_u1_inv_16x   spare11_inv_16x (.in(1'b1),
                                   .out(spare11_inv_16x_unused));
cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare11_nand2_16x_unused));
cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare11_nor3_4x_unused));
cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare11_nand2_8x_unused));
cl_u1_buf_16x   spare11_buf_16x (.in(1'b1),
                                   .out(spare11_buf_16x_unused));
cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare11_nor2_16x_unused));
cl_u1_inv_32x   spare11_inv_32x (.in(1'b1),
                                   .out(spare11_inv_32x_unused));
assign scan_out = so_11;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_eem_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_eem_dp (
  asi_error_inject, 
  asi_error_mask, 
  asi_mbist_ecc_in, 
  asi_mbist_run, 
  ecc_in, 
  ecc_out);
wire mbist_run_;
wire [7:0] pre_error_inject_;
wire [7:0] pre_error_inject;
wire [7:0] error_inject;
wire [7:0] error_inject_;
wire [7:0] ecc_in_;
wire [7:0] ecc_mux_0;
wire [7:0] ecc_mux_1;
wire [7:0] ecc_mux_2;


input		asi_error_inject;
input	[7:0]	asi_error_mask;

input	[7:0]	asi_mbist_ecc_in;
input		asi_mbist_run;

input 	[7:0]	ecc_in;

output	[7:0]	ecc_out;	


mmu_eem_dp_inv_macro__stack_8r__width_1 mbist_run_b_inv   (
	.din	(asi_mbist_run			),
	.dout	(mbist_run_			)
);

mmu_eem_dp_nand_macro__ports_2__stack_8r__width_8 pre_error_inject_b_and    (
	.din0	({8 {asi_error_inject}}		),
	.din1	(asi_error_mask		[7:0]	),
	.dout	(pre_error_inject_	[7:0]	)
);

mmu_eem_dp_inv_macro__stack_8r__width_8 pre_error_inject_inv   (
	.din	(pre_error_inject_	[7:0]	),
	.dout	(pre_error_inject	[7:0]	)
);

mmu_eem_dp_and_macro__stack_8r__width_8 error_inject_and   (
	.din0	(pre_error_inject	[7:0]	),
	.din1	({8 {mbist_run_}}		),
	.dout	(error_inject		[7:0]	)
);

mmu_eem_dp_and_macro__stack_8r__width_8 error_inject_b_and   (
	.din0	(pre_error_inject_	[7:0]	),
	.din1	({8 {mbist_run_}}		),
	.dout	(error_inject_		[7:0]	)
);

mmu_eem_dp_inv_macro__stack_8r__width_8 ecc_in_b_inv   (
	.din	(ecc_in			[7:0]	),
	.dout	(ecc_in_		[7:0]	)
);

mmu_eem_dp_nand_macro__ports_2__stack_8r__width_8 ecc_mux_0_nand    (
	.din0	(ecc_in			[7:0]	),
	.din1	(error_inject_		[7:0]	),
	.dout	(ecc_mux_0		[7:0]	)
);

mmu_eem_dp_nand_macro__ports_2__stack_8r__width_8 ecc_mux_1_nand    (
	.din0	(ecc_in_		[7:0]	),
	.din1	(error_inject		[7:0]	),
	.dout	(ecc_mux_1		[7:0]	)
);

mmu_eem_dp_nand_macro__ports_2__stack_8r__width_8 ecc_mux_2_nand    (
	.din0	(asi_mbist_ecc_in	[7:0]	),
	.din1	({8 {asi_mbist_run}}		),
	.dout	(ecc_mux_2		[7:0]	)
);

mmu_eem_dp_nand_macro__ports_3__stack_8r__width_8 ecc_mux_nand    (
	.din0	(ecc_mux_0		[7:0]	),
	.din1	(ecc_mux_1		[7:0]	),
	.din2	(ecc_mux_2		[7:0]	),
	.dout	(ecc_out		[7:0]	)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

endmodule


//
//   invert macro
//
//


module mmu_eem_dp_inv_macro__stack_8r__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_eem_dp_nand_macro__ports_2__stack_8r__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


nand2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module mmu_eem_dp_inv_macro__stack_8r__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module mmu_eem_dp_and_macro__stack_8r__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


and2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_eem_dp_nand_macro__ports_3__stack_8r__width_8 (
  din0, 
  din1, 
  din2, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  output [7:0] dout;


nand3 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.in2(din2[7:0]),
.out(dout[7:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_htc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_htc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_out, 
  lsu_mmu_pmen, 
  spc_core_running_status, 
  l15_mmu_cpkt, 
  l15_mmu_valid, 
  asi_tsb_ptr_req_valid, 
  asi_tsb_ptr_req, 
  asi_tsb_ptr_number, 
  asd0_zero_context, 
  asd1_zero_context, 
  asi_wr_partition_id, 
  asi_wr_data, 
  asi_hwtw_config_0, 
  asi_hwtw_config_1, 
  asi_hwtw_config_2, 
  asi_hwtw_config_3, 
  asi_hwtw_config_4, 
  asi_hwtw_config_5, 
  asi_hwtw_config_6, 
  asi_hwtw_config_7, 
  asi_tsb_hwtw_enable_0, 
  asi_tsb_hwtw_enable_1, 
  htd_ra2pa_lower_hit_hw4, 
  htd_ra2pa_upper_hit_hw4, 
  htd_razero_hw4, 
  htd_range_en_hw4, 
  htd_zeroctx_m0, 
  htd_zeroctx_hw1, 
  htd_usectx0_hw1, 
  htd_usectx1_hw1, 
  htd_ranotpa_hw1, 
  htd_ptr_hit0_hw1, 
  htd_ptr_hit1_hw1, 
  htd_ptr_hit2_hw1, 
  htd_ctx_hit_hw1, 
  htd_tte_ep_hw1, 
  htd_dmiss_hw1, 
  htd_pred0_idx_m0, 
  htd_pred1_idx_m0, 
  htd_pred0_m0, 
  htd_pred1_m0, 
  htd_dmiss, 
  htd_sec_ctx, 
  tlu_iht_request, 
  tlu_dht_request, 
  l15_mmu_grant, 
  asi_mra_req_grant, 
  tsm_rqv, 
  tsm_tsb_miss_hw2, 
  trs_rqv, 
  trs_null_st, 
  trs_waitrr3_st, 
  trs_ecc_err, 
  trs_ep_err, 
  mel0_parity_err, 
  mel1_parity_err, 
  trs0_err_type, 
  trs1_err_type, 
  trs2_err_type, 
  trs3_err_type, 
  trs4_err_type, 
  trs5_err_type, 
  trs6_err_type, 
  trs7_err_type, 
  trs0_err_index, 
  trs1_err_index, 
  trs2_err_index, 
  trs3_err_index, 
  trs4_err_index, 
  trs5_err_index, 
  trs6_err_index, 
  trs7_err_index, 
  tlu_cerer_hwtwl2, 
  tlu_cerer_hwtwmu, 
  htc_core_running, 
  htc_m1_clken, 
  htc_hw3_clken, 
  htc_hw4_clken, 
  mmu_i_unauth_access, 
  mmu_i_tsb_miss, 
  mmu_d_tsb_miss, 
  mmu_reload_done, 
  mmu_use_context_0, 
  mmu_use_context_1, 
  mmu_sec_context, 
  htc_mra_addr_in, 
  htc_mra_rd_en, 
  htc_wr_itlb_data_in, 
  htc_wr_dtlb_data_in, 
  htc_dtlb_clken, 
  htc_itlb_clken, 
  htc_zero_ctx_m2, 
  htc_upd_pred_idx_hw2, 
  htc_upd_grp, 
  htc_upd_grp_x, 
  htc_new_pred_bit, 
  htc_wrpred0_hw2, 
  htc_wrpred1_hw2, 
  htc_wrpred2_hw2, 
  htc_wrpred3_hw2, 
  htc_tlb_miss_m, 
  mmu_l15_cpkt, 
  htc_l15_en, 
  mmu_l15_valid, 
  htc_wr_q0new_nogrant, 
  htc_wr_q0new_grant, 
  htc_wr_q1new, 
  htc_shift_q1_grant, 
  htc_wr_m3new, 
  htc_wr_m3q0, 
  htc_mra_sel_0, 
  htc_sel_mra_lo, 
  htc_conf_index_m2, 
  htc_vld_tsbptr_m2, 
  htc_rd_tteq, 
  htc_ra2pahit_hw5, 
  htc_ranotpax_hw5, 
  htc_cindex_bit0, 
  htc_cindex_bit1, 
  htc_rrindex_bit0, 
  htc_rrindex_bit1, 
  htc_pid0_m0, 
  htc_pid1_m0, 
  htc_tsbrd_valid_m0, 
  htc_thr_valid_hw3, 
  htc_thr_prevalid_hw3, 
  htc_va_rd_m2_in, 
  htc_ranotpa_hw4, 
  htc_data_rcvd_hw1, 
  htc_tsb_hit_hw1, 
  htc_tsb_done_hw2, 
  htc_thr_valid_m1, 
  htc_thr_valid_m0, 
  htc_hwtw_burst, 
  mmu_i_tte_outofrange, 
  mmu_d_tte_outofrange, 
  rr_ecc_err_type, 
  cfg_ecc_err_type, 
  l2_ecc_err_type, 
  rr_ecc_err_hw5, 
  cfg_ecc_err_m3, 
  l2_ecc_err_hw1, 
  htc_ep_miss_hw1, 
  cfg_ecc_err_index, 
  rr_ecc_err_index, 
  mmu_i_eccerr, 
  mmu_d_eccerr, 
  mmu_i_l2cerr, 
  mmu_d_l2cerr, 
  htc_thr0_err_type, 
  htc_thr1_err_type, 
  htc_thr2_err_type, 
  htc_thr3_err_type, 
  htc_thr4_err_type, 
  htc_thr5_err_type, 
  htc_thr6_err_type, 
  htc_thr7_err_type, 
  htc_thr0_err_index, 
  htc_thr1_err_index, 
  htc_thr2_err_index, 
  htc_thr3_err_index, 
  htc_thr4_err_index, 
  htc_thr5_err_index, 
  htc_thr6_err_index, 
  htc_thr7_err_index, 
  mmu_pmu_l2ret, 
  mmu_pmu_l2miss, 
  mmu_pmu_dtlb, 
  mmu_pmu_tid, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  wmr_scan_out);
wire [7:0] htc_hwtw_mode_0;
wire [7:0] htc_hwtw_mode_1;
wire [7:0] htc_hwtw_pred;
wire l1clk;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire pmen_reg_scanin;
wire pmen_reg_scanout;
wire htc_mmu_pmen;
wire tlb_miss_lat_scanin;
wire tlb_miss_lat_scanout;
wire [7:0] htc_tlb_miss_m0;
wire [7:0] htd_dmiss_lat;
wire tlb_cerer_lat_scanin;
wire tlb_cerer_lat_scanout;
wire hwtwl2_en;
wire hwtwmu_en;
wire [2:0] pid0_in;
wire [2:0] pid0;
wire [2:0] pid1_in;
wire [2:0] pid1;
wire [2:0] pid2_in;
wire [2:0] pid2;
wire [2:0] pid3_in;
wire [2:0] pid3;
wire [2:0] pid4_in;
wire [2:0] pid4;
wire [2:0] pid5_in;
wire [2:0] pid5;
wire [2:0] pid6_in;
wire [2:0] pid6;
wire [2:0] pid7_in;
wire [2:0] pid7;
wire pid0_lat_wmr_scanin;
wire pid0_lat_wmr_scanout;
wire pid1_lat_wmr_scanin;
wire pid1_lat_wmr_scanout;
wire pid2_lat_wmr_scanin;
wire pid2_lat_wmr_scanout;
wire pid3_lat_wmr_scanin;
wire pid3_lat_wmr_scanout;
wire pid4_lat_wmr_scanin;
wire pid4_lat_wmr_scanout;
wire pid5_lat_wmr_scanin;
wire pid5_lat_wmr_scanout;
wire pid6_lat_wmr_scanin;
wire pid6_lat_wmr_scanout;
wire pid7_lat_wmr_scanin;
wire pid7_lat_wmr_scanout;
wire [7:0] tsm_sel;
wire [3:0] tsm_ptr0;
wire [7:4] tsm_ptr1;
wire tg0_valid;
wire tg1_valid;
wire sel_tg1;
wire favor_tg1;
wire [7:0] tsm_thrsel_m0;
wire [7:0] trs_thrsel_hw2;
wire tsm_thrsel_v;
wire trs_thrsel_v;
wire [7:0] tsm_valid_m0;
wire [7:0] trs_valid_hw2;
wire tsm_tg0_selected;
wire tsm_tg1_selected;
wire favor_tg1_in;
wire favour_bit_reg_scanin;
wire favour_bit_reg_scanout;
wire [3:0] tsm_ptr0_in;
wire [7:4] tsm_ptr1_in;
wire tsm_ptr0_in_0_;
wire tsm_ptr1_in_4_;
wire ptr0_reg_scanin;
wire ptr0_reg_scanout;
wire tsm_ptr0_0_;
wire ptr1_reg_scanin;
wire ptr1_reg_scanout;
wire tsm_ptr1_4_;
wire zero_ctx;
wire [7:0] incr_cindex_bit0;
wire [7:0] incr_cindex_bit1;
wire [7:0] next_cindex_bit0;
wire [7:0] next_cindex_bit1;
wire conf_idx_reg_scanin;
wire conf_idx_reg_scanout;
wire [7:0] incr_rrindex_bit0;
wire [7:0] incr_rrindex_bit1;
wire [7:0] next_rrindex_bit0;
wire [7:0] next_rrindex_bit1;
wire rr_idx_reg_scanin;
wire rr_idx_reg_scanout;
wire [1:0] conf_index;
wire [7:0] cfg_done_m1;
wire conf_rd_en;
wire [2:0] conf_rd_thr_id;
wire [4:0] conf_addr_in;
wire [1:0] conf_mra_rd_en;
wire [4:0] rr_addr_in;
wire rr_rd_en;
wire [1:0] rr_mra_rd_en;
wire thr_valid_miss_lo_m0;
wire thr_valid_miss_hi_m0;
wire tsbrd_valid_m0;
wire m1_stg_lat_scanin;
wire m1_stg_lat_scanout;
wire zero_ctx_m1;
wire [1:0] conf_index_m1;
wire [2:0] conf_addr_m1;
wire conf_prevalid_lat_scanin;
wire conf_prevalid_lat_scanout;
wire [7:0] thr_prevalid_m1;
wire tsbrd_z_m0;
wire tsbrd_nz_m0;
wire tsbptr_lat_scanin;
wire tsbptr_lat_scanout;
wire [0:0] tsbrd_tsbptr_m1;
wire tsbrd_z_m1;
wire tsbrd_nz_m1;
wire [7:0] htc_tsbrd_valid_m1;
wire asi_tsb_ptr_number_unused;
wire predrow0_lat_scanin;
wire predrow0_lat_scanout;
wire [5:0] htd_pred0_idx_m1;
wire [15:0] htd_pred0_m1;
wire predrow1_lat_scanin;
wire predrow1_lat_scanout;
wire [5:0] htd_pred1_idx_m1;
wire [15:0] htd_pred1_m1;
wire tlbmiss_lat_scanin;
wire tlbmiss_lat_scanout;
wire [7:0] htc_tlb_miss_m1;
wire tlbvalidmiss_lat_scanin;
wire tlbvalidmiss_lat_scanout;
wire thr_valid_miss_hi_m1;
wire thr_valid_miss_lo_m1;
wire [1:0] pred0_bit_m1;
wire [1:0] pred1_bit_m1;
wire [5:0] pred_idx0_in;
wire [5:0] pred_idx0;
wire [5:0] pred_idx1_in;
wire [5:0] pred_idx1;
wire [5:0] pred_idx2_in;
wire [5:0] pred_idx2;
wire [5:0] pred_idx3_in;
wire [5:0] pred_idx3;
wire [5:0] pred_idx4_in;
wire [5:0] pred_idx4;
wire [5:0] pred_idx5_in;
wire [5:0] pred_idx5;
wire [5:0] pred_idx6_in;
wire [5:0] pred_idx6;
wire [5:0] pred_idx7_in;
wire [5:0] pred_idx7;
wire [1:0] pred_bit0_in;
wire [1:0] pred_bit0;
wire [1:0] pred_bit1_in;
wire [1:0] pred_bit1;
wire [1:0] pred_bit2_in;
wire [1:0] pred_bit2;
wire [1:0] pred_bit3_in;
wire [1:0] pred_bit3;
wire [1:0] pred_bit4_in;
wire [1:0] pred_bit4;
wire [1:0] pred_bit5_in;
wire [1:0] pred_bit5;
wire [1:0] pred_bit6_in;
wire [1:0] pred_bit6;
wire [1:0] pred_bit7_in;
wire [1:0] pred_bit7;
wire pred0_lat_scanin;
wire pred0_lat_scanout;
wire pred1_lat_scanin;
wire pred1_lat_scanout;
wire pred2_lat_scanin;
wire pred2_lat_scanout;
wire pred3_lat_scanin;
wire pred3_lat_scanout;
wire pred4_lat_scanin;
wire pred4_lat_scanout;
wire pred5_lat_scanin;
wire pred5_lat_scanout;
wire pred6_lat_scanin;
wire pred6_lat_scanout;
wire pred7_lat_scanin;
wire pred7_lat_scanout;
wire room_avail_m1;
wire cfg_read_tg0_m1;
wire cfg_read_tg1_m1;
wire htc_valid_m1;
wire [7:0] thr_valid_m2_in;
wire tsbrd_valid_m1;
wire tsbrd_tg0_m1;
wire tsbrd_tg1_m1;
wire [1:0] htc_mra_sel;
wire rr_read_tg1_hw3;
wire rr_read_tg0_hw3;
wire pred_en;
wire [1:1] pred_bit_m1;
wire conf_sel_mra_lo;
wire conf_sel_mra_up;
wire tsbrd_sel_mra_lo;
wire tsbrd_sel_mra_up;
wire htc_sel_mra_up;
wire [1:0] conf_index_m2_in;
wire hwtw_en_tg0;
wire hwtw_en_tg1;
wire hwtw_en_m2_in;
wire m2_stg_lat2_scanin;
wire m2_stg_lat2_scanout;
wire hwtw_en_m2;
wire cfg_read_tg0_m2;
wire cfg_read_tg1_m2;
wire zero_ctx_m2;
wire [2:0] conf_addr_m2;
wire [7:0] htc_thr_valid_m2;
wire [2:0] vld_tsbptr_thr_id_m2;
wire vld_tsbptr_rdy_m2;
wire [7:0] htc_cfg_ecc_err_en_m2;
wire [2:0] cfg_ecc_err_index_m2;
wire m3_stg_lat1_scanin;
wire m3_stg_lat1_scanout;
wire cfg_read_tg0_m3;
wire cfg_read_tg1_m3;
wire [7:0] htc_cfg_ecc_err_en_m3;
wire mel0_parity_err_m3;
wire mel1_parity_err_m3;
wire mra0_ecc_err_lat;
wire mra1_ecc_err_lat;
wire [1:0] mra0_err_type_lat;
wire [1:0] mra1_err_type_lat;
wire req_m2;
wire [2:0] htc_l15_cpkt_15_13;
wire [1:0] htc_l15_cpkt_9_8;
wire [1:0] next_gkt_count;
wire gkt_grant;
wire mmu_l15_valid_int;
wire [1:0] gkt_count;
wire gkt_count_reg_scanin;
wire gkt_count_reg_scanout;
wire gkt_full;
wire v0_in;
wire v0;
wire v1;
wire v1_in;
wire qv_reg_scanin;
wire qv_reg_scanout;
wire q0_val;
wire q1_val;
wire htc_wr_q0new;
wire htc_shift_q1;
wire [4:0] q1_cpkt_in;
wire [4:0] q1_cpkt;
wire q1cpkt_reg_scanin;
wire q1cpkt_reg_scanout;
wire [4:0] q0_cpkt_in;
wire [4:0] q0_cpkt;
wire q0cpkt_reg_scanin;
wire q0cpkt_reg_scanout;
wire htc_l15_valid;
wire [2:0] mmu_l15_cpkt_in_15_13_in;
wire [1:0] mmu_l15_cpkt_in_9_8_in;
wire cpkt_reg_scanin;
wire cpkt_reg_scanout;
wire load_ret_hw0;
wire [7:0] ret_tid_hw0;
wire l2_err_hw0;
wire [1:0] l2_ecc_err_type_hw0;
wire [1:0] ret_tsbid_hw0;
wire l2miss_hw0;
wire l2_cerr_hw0;
wire gkt_hw0_lat0_scanin;
wire gkt_hw0_lat0_scanout;
wire l2_cerr_hw1;
wire l2_err_hw1;
wire load_ret_hw1;
wire [7:0] ret_tid_hw1;
wire [1:0] ret_tsbid_hw1;
wire l2miss_hw1;
wire [2:0] mmutid_hw1;
wire htd_ptr_hit_hw1;
wire ctx_hit;
wire ep_hit;
wire raw_tsb_hit_hw1;
wire raw_ep_miss_hw1;
wire [7:0] tsb_done_hw1;
wire [7:0] d_l2_cerr;
wire [7:0] i_l2_cerr;
wire final_l2_cerr_lat_scanin;
wire final_l2_cerr_lat_scanout;
wire tsb_hit_lat_scanin;
wire tsb_hit_lat_scanout;
wire [7:0] htc_tsb_hit_hw2;
wire ep_miss_lat_scanin;
wire ep_miss_lat_scanout;
wire [7:0] htc_ep_miss_hw2;
wire tsb_done_lat_scanin;
wire tsb_done_lat_scanout;
wire [7:0] tsb_done_nocfg_hw2;
wire cfg_ecc_lat_scanin;
wire cfg_ecc_lat_scanout;
wire [7:0] cfg_ecc_err_m4;
wire tsbid_lat_scanin;
wire tsbid_lat_scanout;
wire [1:0] ret_tsbid_hw2;
wire [7:0] htd_ranotpa_in;
wire [7:0] htd_ranotpa;
wire [7:0] htd_zeroctx_in;
wire [7:0] htd_zeroctx;
wire [7:0] htd_usectx0_in;
wire [7:0] htd_usectx0;
wire [7:0] htd_usectx1_in;
wire [7:0] htd_usectx1;
wire tsb0_lat_scanin;
wire tsb0_lat_scanout;
wire [1:0] rr_index;
wire [7:0] thr_valid_hw2;
wire [7:0] rr_done_hw3;
wire [2:0] rr_rd_thr_id;
wire [5:0] upd_pred_idx;
wire [1:0] upd_pred_bit;
wire [1:0] ret_tsbnum_hw2;
wire inc_pred;
wire dec_pred;
wire pred_upd_en;
wire rr_addr_hw2_lat_scanin;
wire rr_addr_hw2_lat_scanout;
wire [2:0] rr_addr_hw3;
wire rr_index_hw2_lat_scanin;
wire rr_index_hw2_lat_scanout;
wire [1:0] rr_index_hw3;
wire rr_prevalid_lat_scanin;
wire rr_prevalid_lat_scanout;
wire stg_hw3_lat_scanin;
wire stg_hw3_lat_scanout;
wire rr_read_tg0_hw4;
wire rr_read_tg1_hw4;
wire [2:0] rr_addr_hw4;
wire thr_valid_hw3_lat_scanin;
wire thr_valid_hw3_lat_scanout;
wire [7:0] htc_thr_valid_hw4;
wire ra2pahit_raw;
wire [7:0] htc_thr_ra_valid_hw4;
wire [7:0] ra2pahit_thr_hw4;
wire [7:0] disable_ra2pahit_st;
wire [7:0] htc_ranotpax_hw4;
wire [7:0] disable_ra2pahit_st_in;
wire htc_zeroctx_hw4;
wire htc_usectx0_hw4;
wire htc_usectx1_hw4;
wire htc_sec_ctx_hw4;
wire htc_new_use_ctx0_hw4;
wire htc_new_use_ctx1_hw4;
wire [2:0] rr_ecc_err_index_hw4;
wire [7:0] tlb_clken_hw4;
wire [7:0] htc_dtlb_clken_hw4;
wire [7:0] htc_itlb_clken_hw4;
wire rr_ranotpax_hw4_lat_scanin;
wire rr_ranotpax_hw4_lat_scanout;
wire [7:0] htc_thr_ra_valid_hw5;
wire ra2pahit_st_lat_scanin;
wire ra2pahit_st_lat_scanout;
wire ra2pahit_lat_scanin;
wire ra2pahit_lat_scanout;
wire [7:0] ra2pahit_hw5;
wire hw4_stg_lat1_scanin;
wire hw4_stg_lat1_scanout;
wire rr_read_tg0_hw5;
wire rr_read_tg1_hw5;
wire hw4_stg_lat2_scanin;
wire hw4_stg_lat2_scanout;
wire [7:0] tlb_wr_en;
wire [7:0] mmu_reload_done_din;
wire [7:0] i_tte_outofrange;
wire [7:0] d_tte_outofrange;
wire [7:0] final_ecc_err_hw5;
wire [7:0] i_ecc_err;
wire [7:0] d_ecc_err;
wire stg_hw5_lat_scanin;
wire stg_hw5_lat_scanout;
wire outofrangemiss_lat_scanin;
wire outofrangemiss_lat_scanout;
wire final_ecc_err_lat_scanin;
wire final_ecc_err_lat_scanout;
wire err_type_lat_scanin;
wire err_type_lat_scanout;
wire err_index_lat_scanin;
wire err_index_lat_scanout;
wire [7:0] i_unauth_access;
wire [7:0] i_tsb_miss;
wire [7:0] d_tsb_miss;
wire tsbmiss_lat_scanin;
wire tsbmiss_lat_scanout;
wire [5:0] l15_mmu_cpkt_unused;
wire spares_scanin;
wire spares_scanout;


input           l2clk;
input           scan_in;
input           tcu_pce_ov;               // scan signals
input		spc_aclk;
input		spc_bclk;
input           tcu_scan_en;
output          scan_out;


input           lsu_mmu_pmen;
input [7:0]     spc_core_running_status;


input [17:0]    l15_mmu_cpkt;
input           l15_mmu_valid;

// tsbptr requests
input           asi_tsb_ptr_req_valid;
input [2:0]     asi_tsb_ptr_req;
input [1:0]     asi_tsb_ptr_number;
input		asd0_zero_context;
input		asd1_zero_context;


// partition id
input [7:0]     asi_wr_partition_id;
input [2:0]     asi_wr_data;

// tsb prediction mode bits 00 - seq no pred, 01 - burst, 10 - seq with pred, 11 - burst
input [1:0]     asi_hwtw_config_0;
input [1:0]     asi_hwtw_config_1;
input [1:0]     asi_hwtw_config_2;
input [1:0]     asi_hwtw_config_3;
input [1:0]     asi_hwtw_config_4;
input [1:0]     asi_hwtw_config_5;
input [1:0]     asi_hwtw_config_6;
input [1:0]     asi_hwtw_config_7;

//input           mra0_data_38;
//input           mra1_data_38;
//input           mra0_data_77;
//input           mra1_data_77;

input [1:0]     asi_tsb_hwtw_enable_0;    // tg0 
input [1:0]     asi_tsb_hwtw_enable_1;    // tg1 


// *** HTC_DP Interface ***
input           htd_ra2pa_lower_hit_hw4;
input           htd_ra2pa_upper_hit_hw4;
input           htd_razero_hw4;
          

input           htd_range_en_hw4;

input [7:0]     htd_zeroctx_m0;            // zero context indicator


input           htd_zeroctx_hw1;           // ignore context on return data
input           htd_usectx0_hw1;           // ignore context on return data
input           htd_usectx1_hw1;           // ignore context on return data
input           htd_ranotpa_hw1;           
input           htd_ptr_hit0_hw1;             // partial VPN(37:22) of rcvd TTE matches with VPN of request recvd
input           htd_ptr_hit1_hw1;             // partial VPN(47:38) of rcvd TTE matches with VPN of request recvd
input           htd_ptr_hit2_hw1;             // VPN(47) of rcvd TTE matches with VPN[63:48]
input           htd_ctx_hit_hw1;              // CTX of  of rcvd TTE matches with CTX of request recvd
input           htd_tte_ep_hw1;               // EP bit from TTE
input           htd_dmiss_hw1;                // dmiss for the thread whose tte is being returned


input [5:0]     htd_pred0_idx_m0;
input [5:0]     htd_pred1_idx_m0;

input [15:0]    htd_pred0_m0;
input [15:0]    htd_pred1_m0;


input [7:0]      htd_dmiss;                  // Dmiss indicator from htd queue
input [7:0]      htd_sec_ctx;                // Secondary context indicator from htd queue


// *** TLU Interface for ITLB/DTLB Miss ***
input [7:0]   tlu_iht_request;
input [7:0]   tlu_dht_request;


// *** Gasket/L15 Interface ***
input           l15_mmu_grant;

input           asi_mra_req_grant;      

// TLB Miss State Machine & TLB Reg Control State Machine Interface
input [7:0]     tsm_rqv;
input [7:0]     tsm_tsb_miss_hw2;

input [7:0]     trs_rqv;
input [7:0]     trs_null_st;
input [7:0]     trs_waitrr3_st;
input [7:0]     trs_ecc_err;
input [7:0]     trs_ep_err;

// ECC interface
input           mel0_parity_err;
input           mel1_parity_err;


input [2:0]     trs0_err_type;
input [2:0]     trs1_err_type;
input [2:0]     trs2_err_type;
input [2:0]     trs3_err_type;
input [2:0]     trs4_err_type;
input [2:0]     trs5_err_type;
input [2:0]     trs6_err_type;
input [2:0]     trs7_err_type;

input [2:0]     trs0_err_index;
input [2:0]     trs1_err_index;
input [2:0]     trs2_err_index;
input [2:0]     trs3_err_index;
input [2:0]     trs4_err_index;
input [2:0]     trs5_err_index;
input [2:0]     trs6_err_index;
input [2:0]     trs7_err_index;


input           tlu_cerer_hwtwl2;    // record enable bit of L2 errors
input           tlu_cerer_hwtwmu;    // record enable bit for mra uncorrectable


output [7:0]    htc_core_running;
output          htc_m1_clken;
output          htc_hw3_clken;
output          htc_hw4_clken;


output [7:0]    mmu_i_unauth_access; // I-TSB has EP off, tsm goes to NULL
output [7:0]    mmu_i_tsb_miss;      // I-TSB Miss indication going to TLU, tsm goes to NULL
output [7:0]    mmu_d_tsb_miss;      // D-TSB Miss indication going to TLU, tsm goes to NULL
output [7:0]    mmu_reload_done;     //Successful write of TLB registers with correct TTE
                                     //Not asserted if TSB Miss occurs
output          mmu_use_context_0;   // new use_context_0 and 1 bits.
output          mmu_use_context_1;
output          mmu_sec_context;


// *** MMU Reg. Array Interface ***
output [4:0]    htc_mra_addr_in;       // Address for mra read
output [1:0]    htc_mra_rd_en;         // Read TSB Conf/RR,Offset Register

output [7:0]    htc_wr_itlb_data_in;   // Enable for writing to ITLB DATAIN register
output [7:0]    htc_wr_dtlb_data_in;   // Enable for writing to DTLB DATAIN register
output [7:0]    htc_dtlb_clken;
output [7:0]    htc_itlb_clken;


output          htc_zero_ctx_m2;             // ignore context of request recvd, saved in htd queue

output [5:3]    htc_upd_pred_idx_hw2;
output [7:0]    htc_upd_grp;
output [7:0]    htc_upd_grp_x;
output [1:0]    htc_new_pred_bit;


output          htc_wrpred0_hw2;
output          htc_wrpred1_hw2;
output          htc_wrpred2_hw2;
output          htc_wrpred3_hw2;


output [7:0]    htc_tlb_miss_m;


// pkt sent to gkt
output [4:0]    mmu_l15_cpkt;  
output          htc_l15_en;
output          mmu_l15_valid;


// buffer ctl signals
output          htc_wr_q0new_nogrant;           
output          htc_wr_q0new_grant;           
output          htc_wr_q1new;
output          htc_shift_q1_grant;
output          htc_wr_m3new;
output          htc_wr_m3q0;


output    htc_mra_sel_0;             
output    htc_sel_mra_lo;


output [1:0]    htc_conf_index_m2;      // conf_index used to latch tsb config data
output [7:0]    htc_vld_tsbptr_m2;      // valid tsbptr being sent to gkt
output [7:0]    htc_rd_tteq;        // used to mux out the data returned, which is saved in queue in htd


output [7:0]    htc_ra2pahit_hw5;
output [7:0]    htc_ranotpax_hw5;

// index signals to tsm/trs

output [7:0]    htc_cindex_bit0;
output [7:0]    htc_cindex_bit1;
output [7:0]    htc_rrindex_bit0;
output [7:0]    htc_rrindex_bit1;


// interface to htd


output [2:0]    htc_pid0_m0;
output [2:0]    htc_pid1_m0;

output [7:0]    htc_tsbrd_valid_m0;


output [7:0]    htc_thr_valid_hw3;
output [7:0]    htc_thr_prevalid_hw3;
output [7:0]    htc_va_rd_m2_in;
output          htc_ranotpa_hw4;

output [7:0]    htc_data_rcvd_hw1;

output [7:0]    htc_tsb_hit_hw1;
output [7:0]    htc_tsb_done_hw2;
output [7:0]    htc_thr_valid_m1;     // valid req in m1, which has asi_grant and gkt_room_avail
output [7:0]    htc_thr_valid_m0;     // valid req in m0

output [7:0]    htc_hwtw_burst;


output [7:0]    mmu_i_tte_outofrange;
output [7:0]    mmu_d_tte_outofrange;


output [1:0]    rr_ecc_err_type;
output [1:0]    cfg_ecc_err_type;
output [1:0]    l2_ecc_err_type;
output [7:0]    rr_ecc_err_hw5;
output [7:0]    cfg_ecc_err_m3;
output [7:0]    l2_ecc_err_hw1;

output [7:0]    htc_ep_miss_hw1;

output [2:0]    cfg_ecc_err_index;
output [2:0]    rr_ecc_err_index;


output [7:0]    mmu_i_eccerr;
output [7:0]    mmu_d_eccerr;

output [7:0]    mmu_i_l2cerr;
output [7:0]    mmu_d_l2cerr;

output [2:0]    htc_thr0_err_type;
output [2:0]    htc_thr1_err_type;
output [2:0]    htc_thr2_err_type;
output [2:0]    htc_thr3_err_type;
output [2:0]    htc_thr4_err_type;
output [2:0]    htc_thr5_err_type;
output [2:0]    htc_thr6_err_type;
output [2:0]    htc_thr7_err_type;

output [2:0]    htc_thr0_err_index;
output [2:0]    htc_thr1_err_index;
output [2:0]    htc_thr2_err_index;
output [2:0]    htc_thr3_err_index;
output [2:0]    htc_thr4_err_index;
output [2:0]    htc_thr5_err_index;
output [2:0]    htc_thr6_err_index;
output [2:0]    htc_thr7_err_index;

// output pmu signals

output          mmu_pmu_l2ret;
output          mmu_pmu_l2miss;
output          mmu_pmu_dtlb;
output [2:0]    mmu_pmu_tid;

input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

output		wmr_scan_out;		// Warm reset (non)scan


assign htc_hwtw_mode_0[7:0] = {asi_hwtw_config_7[0],asi_hwtw_config_6[0],asi_hwtw_config_5[0],asi_hwtw_config_4[0],
                               asi_hwtw_config_3[0],asi_hwtw_config_2[0],asi_hwtw_config_1[0],asi_hwtw_config_0[0]}; 
assign htc_hwtw_mode_1[7:0] = {asi_hwtw_config_7[1],asi_hwtw_config_6[1],asi_hwtw_config_5[1],asi_hwtw_config_4[1],
                               asi_hwtw_config_3[1],asi_hwtw_config_2[1],asi_hwtw_config_1[1],asi_hwtw_config_0[1]}; 

assign htc_hwtw_burst[7:0] =  htc_hwtw_mode_0[7:0];
assign htc_hwtw_pred[7:0] = ~htc_hwtw_mode_0[7:0] & htc_hwtw_mode_1[7:0];


///////////////////////////////////////////////////
// clock header
///////////////////////////////////////////////////
mmu_htc_ctl_l1clkhdr_ctl_macro clkgen 
  (
   .l2clk(l2clk),
   .l1en (1'b1 ),
   .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
   );

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se = tcu_scan_en;

// end scan

mmu_htc_ctl_msff_ctl_macro__width_9 pmen_reg  
(
 .scan_in(pmen_reg_scanin),
 .scan_out(pmen_reg_scanout),
 .l1clk	(l1clk),
 .din	({lsu_mmu_pmen,spc_core_running_status[7:0]}),
 .dout	({htc_mmu_pmen,htc_core_running[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );


// flop htd_dmiss
mmu_htc_ctl_msff_ctl_macro__width_16 tlb_miss_lat  
(
 .scan_in(tlb_miss_lat_scanin),
 .scan_out(tlb_miss_lat_scanout),
 .l1clk( l1clk ),
 .din  ({htc_tlb_miss_m[7:0], htd_dmiss[7:0]}),
 .dout ({htc_tlb_miss_m0[7:0], htd_dmiss_lat[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );


mmu_htc_ctl_msff_ctl_macro__width_2 tlb_cerer_lat  
(
 .scan_in(tlb_cerer_lat_scanin),
 .scan_out(tlb_cerer_lat_scanout),
 .l1clk( l1clk ),
 .din  ({tlu_cerer_hwtwl2,tlu_cerer_hwtwmu}),
 .dout ({hwtwl2_en, hwtwmu_en}),
  .siclk(siclk),
  .soclk(soclk)
 );


// latch the partition id for each thread.
assign pid0_in[2:0] = ({3{asi_wr_partition_id[0]}} & asi_wr_data[2:0]) |
                      ({3{~asi_wr_partition_id[0]}} & pid0[2:0]);

assign pid1_in[2:0] = ({3{asi_wr_partition_id[1]}} & asi_wr_data[2:0]) |
                      ({3{~asi_wr_partition_id[1]}} & pid1[2:0]);

assign pid2_in[2:0] = ({3{asi_wr_partition_id[2]}} & asi_wr_data[2:0]) |
                      ({3{~asi_wr_partition_id[2]}} & pid2[2:0]);

assign pid3_in[2:0] = ({3{asi_wr_partition_id[3]}} & asi_wr_data[2:0]) |
                      ({3{~asi_wr_partition_id[3]}} & pid3[2:0]);

assign pid4_in[2:0] = ({3{asi_wr_partition_id[4]}} & asi_wr_data[2:0]) |
                      ({3{~asi_wr_partition_id[4]}} & pid4[2:0]);

assign pid5_in[2:0] = ({3{asi_wr_partition_id[5]}} & asi_wr_data[2:0]) |
                      ({3{~asi_wr_partition_id[5]}} & pid5[2:0]);

assign pid6_in[2:0] = ({3{asi_wr_partition_id[6]}} & asi_wr_data[2:0]) |
                      ({3{~asi_wr_partition_id[6]}} & pid6[2:0]);

assign pid7_in[2:0] = ({3{asi_wr_partition_id[7]}} & asi_wr_data[2:0]) |
                      ({3{~asi_wr_partition_id[7]}} & pid7[2:0]);

mmu_htc_ctl_msff_ctl_macro__width_3 pid0_lat  (// FS:wmr_protect
 .scan_in(pid0_lat_wmr_scanin),
 .scan_out(pid0_lat_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk),
 .din  ({pid0_in[2:0]}),
 .dout ({pid0[2:0]}),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_3 pid1_lat  (// FS:wmr_protect
 .scan_in(pid1_lat_wmr_scanin),
 .scan_out(pid1_lat_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk),
 .din  ({pid1_in[2:0]}),
 .dout ({pid1[2:0]}),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_3 pid2_lat  (// FS:wmr_protect
 .scan_in(pid2_lat_wmr_scanin),
 .scan_out(pid2_lat_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk),
 .din  ({pid2_in[2:0]}),
 .dout ({pid2[2:0]}),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_3 pid3_lat  (// FS:wmr_protect
 .scan_in(pid3_lat_wmr_scanin),
 .scan_out(pid3_lat_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk),
 .din  ({pid3_in[2:0]}),
 .dout ({pid3[2:0]}),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_3 pid4_lat  (// FS:wmr_protect
 .scan_in(pid4_lat_wmr_scanin),
 .scan_out(pid4_lat_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk),
 .din  ({pid4_in[2:0]}),
 .dout ({pid4[2:0]}),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_3 pid5_lat  (// FS:wmr_protect
 .scan_in(pid5_lat_wmr_scanin),
 .scan_out(pid5_lat_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk),
 .din  ({pid5_in[2:0]}),
 .dout ({pid5[2:0]}),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_3 pid6_lat  (// FS:wmr_protect
 .scan_in(pid6_lat_wmr_scanin),
 .scan_out(pid6_lat_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk),
 .din  ({pid6_in[2:0]}),
 .dout ({pid6[2:0]}),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_3 pid7_lat  (// FS:wmr_protect
 .scan_in(pid7_lat_wmr_scanin),
 .scan_out(pid7_lat_wmr_scanout),
 .siclk(spc_aclk_wmr),
 .l1clk( l1clk),
 .din  ({pid7_in[2:0]}),
 .dout ({pid7[2:0]}),
  .soclk(soclk)
 );
                             

// mra ecc errors
///////////////////////////////////////////////////
// Set the ECC ERROR TYPE
// 110 MRA Correctable
// 101 MRA Uncorrectable
// 001 L2 correctable
// 010 L2 uncorrectable
// 011 L2 Not Data
// latch the first ecc error and hold it.
///////////////////////////////////////////////////
//assign mra0_ecc_err = (med0_cecc & hwtwmc_en) | (med0_uecc & hwtwmu_en);
//assign mra1_ecc_err = (med1_cecc & hwtwmc_en) | (med1_uecc & hwtwmu_en);
//assign mra0_err_type[1:0] = {(med0_cecc & hwtwmc_en),(med0_uecc & hwtwmu_en)};
//assign mra1_err_type[1:0] = {(med1_cecc & hwtwmc_en),(med1_uecc & hwtwmu_en)};


/////////////////////////////////////////////////////////////////////
//
// | Update TTE | Req. Arb. | MRA Access | TSB Ptr Gen. | TTE Req to LSU |
// | Request Q  | Cfg. Rd.  |   Cycle    |              |                |
// |            | to MRA    |            |              |                |
// |            |           |            |              |                |
// |    M       |    M0     |    M1      |      M2      |       M3       |
//
/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////
// TTE Request Queue Controls (M)
/////////////////////////////////////////////////////////////////////
assign htc_tlb_miss_m[7:0] = tlu_iht_request[7:0] | tlu_dht_request[7:0];

// mux out the pid for two thread groups in M0

assign htc_pid0_m0[2:0] = ({3{htc_tlb_miss_m0[0]}} & pid0[2:0]) |
                          ({3{htc_tlb_miss_m0[1]}} & pid1[2:0]) |
                          ({3{htc_tlb_miss_m0[2]}} & pid2[2:0]) |
                          ({3{htc_tlb_miss_m0[3]}} & pid3[2:0]);

assign htc_pid1_m0[2:0] = ({3{htc_tlb_miss_m0[4]}} & pid4[2:0]) |
                          ({3{htc_tlb_miss_m0[5]}} & pid5[2:0]) |
                          ({3{htc_tlb_miss_m0[6]}} & pid6[2:0]) |
                          ({3{htc_tlb_miss_m0[7]}} & pid7[2:0]);


/////////////////////////////////////////////////////////////////////
// Request Arbitration (M0)
// Confg. Reg. Read Req to MRA
/////////////////////////////////////////////////////////////////////
// ARBITRATION logic
// Every cycle, at most one thread is selected for accessing MRA.
// Threads could be accessing MRA for TSB config read on tlb miss, or
// Range register read when tte comes back.

// Threads requesting range register read are (trs_reqv) are given higher priority
// than threads requesting tsb config (tsm_rqv).

// Threads requesting range register read are prioritized statically with thread
// 0 having highest priority and thread 7 having least. There is no issue about
// live lock, because all threads requesting RR would have to be completed before
// a new thread can request a tsb. And a thread cannot request a RR until it has
// gone through the process of reading TSB and fetching TTE from L2.

// Threads requesting TSB config cannot be statically prioritized because it can
// lead to a potential live lock. If all threads are missing in TLB at all times,
// Thread 0 can read TSB, get TTE, read RR, and get another TLB miss, before THR 7
// has had a chance to go out and read its TSB config. So we cannot use static priority
// for TSB config reads.

// TSB config reads will be prioritized by dividing the threads into 2 groups.
// A single favor bit will select alternatingly between the 2 groups.
// Within a group, the threads will be prioritized based on a 4-bit rotating pointer.
// The pointer always points to the thread with highest priority, and it gets updated
// when a thread gets selected. The pointer updates such that the selected thread will
// have the least priority.

assign tsm_sel[0] = (tsm_ptr0[1] & ~tsm_rqv[1] & ~tsm_rqv[2] & ~tsm_rqv[3] & tsm_rqv[0]) |
                    (tsm_ptr0[2] &               ~tsm_rqv[2] & ~tsm_rqv[3] & tsm_rqv[0]) |
                    (tsm_ptr0[3] &                             ~tsm_rqv[3] & tsm_rqv[0]) |
                    (tsm_ptr0[0] &                                           tsm_rqv[0]);

                    
assign tsm_sel[1] = (tsm_ptr0[2] & ~tsm_rqv[2] & ~tsm_rqv[3] & ~tsm_rqv[0] & tsm_rqv[1]) |
                    (tsm_ptr0[3] &               ~tsm_rqv[3] & ~tsm_rqv[0] & tsm_rqv[1]) |
                    (tsm_ptr0[0] &                             ~tsm_rqv[0] & tsm_rqv[1]) |
                    (tsm_ptr0[1] &                                           tsm_rqv[1]);

                    
assign tsm_sel[2] = (tsm_ptr0[3] & ~tsm_rqv[3] & ~tsm_rqv[0] & ~tsm_rqv[1] & tsm_rqv[2]) |
                    (tsm_ptr0[0] &               ~tsm_rqv[0] & ~tsm_rqv[1] & tsm_rqv[2]) |
                    (tsm_ptr0[1] &                             ~tsm_rqv[1] & tsm_rqv[2]) |
                    (tsm_ptr0[2] &                                           tsm_rqv[2]);
                    
assign tsm_sel[3] = (tsm_ptr0[0] & ~tsm_rqv[0] & ~tsm_rqv[1] & ~tsm_rqv[2] & tsm_rqv[3]) |
                    (tsm_ptr0[1] &               ~tsm_rqv[1] & ~tsm_rqv[2] & tsm_rqv[3]) |
                    (tsm_ptr0[2] &                             ~tsm_rqv[2] & tsm_rqv[3]) |
                    (tsm_ptr0[3] &                                           tsm_rqv[3]);


assign tsm_sel[4] = (tsm_ptr1[5] & ~tsm_rqv[5] & ~tsm_rqv[6] & ~tsm_rqv[7] & tsm_rqv[4]) |
                    (tsm_ptr1[6] &               ~tsm_rqv[6] & ~tsm_rqv[7] & tsm_rqv[4]) |
                    (tsm_ptr1[7] &                             ~tsm_rqv[7] & tsm_rqv[4]) |
                    (tsm_ptr1[4] &                                           tsm_rqv[4]);

assign tsm_sel[5] = (tsm_ptr1[6] & ~tsm_rqv[6] & ~tsm_rqv[7] & ~tsm_rqv[4] & tsm_rqv[5]) |
                    (tsm_ptr1[7] &               ~tsm_rqv[7] & ~tsm_rqv[4] & tsm_rqv[5]) |
                    (tsm_ptr1[4] &                             ~tsm_rqv[4] & tsm_rqv[5]) |
                    (tsm_ptr1[5] &                                           tsm_rqv[5]);

assign tsm_sel[6] = (tsm_ptr1[7] & ~tsm_rqv[7] & ~tsm_rqv[4] & ~tsm_rqv[5] & tsm_rqv[6]) |
                    (tsm_ptr1[4] &               ~tsm_rqv[4] & ~tsm_rqv[5] & tsm_rqv[6]) |
                    (tsm_ptr1[5] &                             ~tsm_rqv[5] & tsm_rqv[6]) |
                    (tsm_ptr1[6] &                                           tsm_rqv[6]);
                    
assign tsm_sel[7] = (tsm_ptr1[4] & ~tsm_rqv[4] & ~tsm_rqv[5] & ~tsm_rqv[6] & tsm_rqv[7]) |
                    (tsm_ptr1[5] &               ~tsm_rqv[5] & ~tsm_rqv[6] & tsm_rqv[7]) |
                    (tsm_ptr1[6] &                             ~tsm_rqv[6] & tsm_rqv[7]) |
                    (tsm_ptr1[7] &                                           tsm_rqv[7]);

assign tg0_valid = |(tsm_rqv[3:0]);
assign tg1_valid = |(tsm_rqv[7:4]);

assign sel_tg1 = (favor_tg1 & tg1_valid) | ~tg0_valid;

assign tsm_thrsel_m0[7:0] = sel_tg1? ({tsm_sel[7:4],4'b0000}): ({4'b0000,tsm_sel[3:0]});


assign trs_thrsel_hw2[0] = trs_rqv[0];
assign trs_thrsel_hw2[1] = trs_rqv[1] & ~trs_rqv[0];
assign trs_thrsel_hw2[2] = trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0];
assign trs_thrsel_hw2[3] = trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0];
assign trs_thrsel_hw2[4] = trs_rqv[4] & ~trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0];
assign trs_thrsel_hw2[5] = trs_rqv[5] & ~trs_rqv[4] & ~trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0];
assign trs_thrsel_hw2[6] = trs_rqv[6] & ~trs_rqv[5] & ~trs_rqv[4] & ~trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0];
assign trs_thrsel_hw2[7] = trs_rqv[7] & ~trs_rqv[6] & ~trs_rqv[5] & ~trs_rqv[4] & ~trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0];

assign tsm_thrsel_v = |(tsm_rqv[7:0]) & ~|(trs_rqv[7:0]);
assign trs_thrsel_v = |(trs_rqv[7:0]);

assign tsm_valid_m0[7:0] = tsm_thrsel_m0[7:0] & ({8{tsm_thrsel_v}});
assign trs_valid_hw2[7:0] = trs_thrsel_hw2[7:0] & ({8{trs_thrsel_v}});


//0in bits_on -var {tsm_valid_m0[7:0],trs_valid_hw2[7:0]} -max 1
//0in bits_on -var {tsm_sel[3:0]} -max 1
//0in bits_on -var {tsm_sel[7:4]} -max 1

// update the favor bit based on the thread group selected
// it is possible that none of the thread groups got selected

assign tsm_tg0_selected = |(tsm_valid_m0[3:0]);
assign tsm_tg1_selected = |(tsm_valid_m0[7:4]);

assign favor_tg1_in = (favor_tg1 & ~tsm_tg1_selected) | tsm_tg0_selected;

mmu_htc_ctl_msff_ctl_macro__width_1 favour_bit_reg  (
 .scan_in(favour_bit_reg_scanin),
 .scan_out(favour_bit_reg_scanout),
 .l1clk( l1clk ),
 .din  (favor_tg1_in),
 .dout (favor_tg1),
  .siclk(siclk),
  .soclk(soclk)
);

// update the tg0/tg1 pointers
assign tsm_ptr0_in[3:0] = tsm_tg0_selected ? ({tsm_valid_m0[2:0],tsm_valid_m0[3]}): tsm_ptr0[3:0];
assign tsm_ptr1_in[7:4] = tsm_tg1_selected ? ({tsm_valid_m0[6:4],tsm_valid_m0[7]}): tsm_ptr1[7:4];

assign tsm_ptr0_in_0_ = ~tsm_ptr0_in[0];
assign tsm_ptr1_in_4_ = ~tsm_ptr1_in[4];

mmu_htc_ctl_msff_ctl_macro__width_4 ptr0_reg  (
 .scan_in(ptr0_reg_scanin),
 .scan_out(ptr0_reg_scanout),
 .l1clk( l1clk ),
 .din  ({tsm_ptr0_in[3:1],tsm_ptr0_in_0_}),
 .dout ({tsm_ptr0[3:1],tsm_ptr0_0_}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_4 ptr1_reg  (
 .scan_in(ptr1_reg_scanin),
 .scan_out(ptr1_reg_scanout),
 .l1clk( l1clk ),
 .din  ({tsm_ptr1_in[7:5],tsm_ptr1_in_4_}),
 .dout ({tsm_ptr1[7:5],tsm_ptr1_4_}),
  .siclk(siclk),
  .soclk(soclk)
);

assign tsm_ptr0[0] = ~tsm_ptr0_0_;
assign tsm_ptr1[4] = ~tsm_ptr1_4_;


// *************************************************************** //
// Context Value Decode 
// *************************************************************** //
//assign zero_ctx = ~|htd_ctx_sel_m0[12:00];

assign zero_ctx = |(tsm_thrsel_m0[7:0] & htd_zeroctx_m0[7:0]);

//********************************************************************************
// Configuration Register Index
// Increment the index on  every grant, else hold.
//********************************************************************************

//assign incr_cindex0[1:0] =({2{~cindex0[01] & ~cindex0[00]}} & 2'b01) |
//                          ({2{~cindex0[01] &  cindex0[00]}} & 2'b10) |
//                          ({2{ cindex0[01] & ~cindex0[00]}} & 2'b11) |
//                          ({2{ cindex0[01] &  cindex0[00]}} & 2'b00) ;
                                                                                          
//assign next_cindex0[1:0] = ({2{thr_valid_m1[0]}} & incr_cindex0[1:0]) |
//                           ({2{tlb_miss_m0[0]}} & 2'b00) |
//                           ({2{(~tlb_miss_m0[0] & ~thr_valid_m1[0])}} & cindex0[1:0]);

assign incr_cindex_bit0[7:0] = ~htc_cindex_bit0[7:0];
assign incr_cindex_bit1[7:0] = htc_cindex_bit1[7:0] ^ htc_cindex_bit0[7:0];

assign next_cindex_bit0[7:0] = (htc_thr_valid_m1[7:0] & incr_cindex_bit0[7:0]) |
                               (htc_tlb_miss_m0[7:0] & 8'b0) |
                               (~htc_thr_valid_m1[7:0] & ~htc_tlb_miss_m0[7:0] & htc_cindex_bit0[7:0]);

assign next_cindex_bit1[7:0] = (htc_thr_valid_m1[7:0] & incr_cindex_bit1[7:0]) |
                               (htc_tlb_miss_m0[7:0] & 8'b0) |
                               (~htc_thr_valid_m1[7:0] & ~htc_tlb_miss_m0[7:0] & htc_cindex_bit1[7:0]);


mmu_htc_ctl_msff_ctl_macro__width_16 conf_idx_reg  (
 .scan_in(conf_idx_reg_scanin),
 .scan_out(conf_idx_reg_scanout),
 .l1clk(l1clk),
 .din  ({next_cindex_bit0[7:0],next_cindex_bit1[7:0]}),
 .dout ({htc_cindex_bit0[7:0],htc_cindex_bit1[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


//********************************************************************************
// RealRange Register Index
//********************************************************************************
//assign incr_index[1:0] = ({2{~rrindex[01] & ~rrindex[00]}} & 2'b01) |
//                         ({2{~rrindex[01] &  rrindex[00]}} & 2'b10) |
//                         ({2{ rrindex[01] & ~rrindex[00]}} & 2'b11) |
//                         ({2{ rrindex[01] &  rrindex[00]}} & 2'b00) ;
//
//assign next_rrindex[1:0] = ({2{thr_valid_hw3}} & incr_index[1:0]) |
//                           ({2{null_state}} & 2'b00) |
//                           ({2{(~null_state & ~thr_valid_hw3)}} & rrindex[1:0]);


assign incr_rrindex_bit0[7:0] = ~htc_rrindex_bit0[7:0];
assign incr_rrindex_bit1[7:0] = htc_rrindex_bit1[7:0] ^ htc_rrindex_bit0[7:0];

assign next_rrindex_bit0[7:0] = (htc_thr_valid_hw3[7:0] & incr_rrindex_bit0[7:0]) |
                                (trs_null_st[7:0] & 8'b0) |
                                (~htc_thr_valid_hw3[7:0] & ~trs_null_st[7:0] & htc_rrindex_bit0[7:0]);

assign next_rrindex_bit1[7:0] = (htc_thr_valid_hw3[7:0] & incr_rrindex_bit1[7:0]) |
                                (trs_null_st[7:0] & 8'b0) |
                                (~htc_thr_valid_hw3[7:0] & ~trs_null_st[7:0] & htc_rrindex_bit1[7:0]);


mmu_htc_ctl_msff_ctl_macro__width_16 rr_idx_reg  (
 .scan_in(rr_idx_reg_scanin),
 .scan_out(rr_idx_reg_scanout),
 .l1clk(l1clk),
 .din  ({next_rrindex_bit0[7:0],next_rrindex_bit1[7:0]}),
 .dout ({htc_rrindex_bit0[7:0],htc_rrindex_bit1[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


//********************************************************************************
// Read Configuration Register (M0)
//********************************************************************************
// MRA Layout
// Bit 2 of tid[2:0] selects mra1/mra0
// Bit tid[1:0] form address[4:3] of MRA_ADDR
// MRA_ADDR[2:0]   Data
//                 
// 000             unused[3:0],z_tsb_conf_0[77:39],z_tsb_conf_1[38:0]
// 001             unused[3:0],z_tsb_conf_2[77:39],z_tsb_conf_3[38:0]
// 010             unused[3:0],nz_tsb_conf_0[77:39],nz_tsb_conf_1[38:0]
// 011             unused[3:0],nz_tsb_conf_2[77:39],nz_tsb_conf_3[38:0]
// 100             RR0[81:27],PhyOff0[25:0] 
// 101             RR1[81:27],PhyOff1[25:0]
// 110             RR2[81:27],PhyOff2[25:0]
// 111             RR3[81:27],PhyOff3[25:0]

assign conf_index[1:0] = ({next_cindex_bit1[0],next_cindex_bit0[0]} & {2{tsm_thrsel_m0[0]}}) |
                         ({next_cindex_bit1[1],next_cindex_bit0[1]} & {2{tsm_thrsel_m0[1]}}) |
                         ({next_cindex_bit1[2],next_cindex_bit0[2]} & {2{tsm_thrsel_m0[2]}}) |
                         ({next_cindex_bit1[3],next_cindex_bit0[3]} & {2{tsm_thrsel_m0[3]}}) |
                         ({next_cindex_bit1[4],next_cindex_bit0[4]} & {2{tsm_thrsel_m0[4]}}) |
                         ({next_cindex_bit1[5],next_cindex_bit0[5]} & {2{tsm_thrsel_m0[5]}}) |
                         ({next_cindex_bit1[6],next_cindex_bit0[6]} & {2{tsm_thrsel_m0[6]}}) |
                         ({next_cindex_bit1[7],next_cindex_bit0[7]} & {2{tsm_thrsel_m0[7]}}) ;


assign htc_thr_valid_m0[7:0] = (tsm_valid_m0[7:0] & ~htc_tsb_done_hw2[7:0] & ~cfg_done_m1[7:0]);
assign conf_rd_en = |(htc_thr_valid_m0[7:0]);

assign conf_rd_thr_id[0] = tsm_thrsel_m0[1] | tsm_thrsel_m0[3] | tsm_thrsel_m0[5] | tsm_thrsel_m0[7];
assign conf_rd_thr_id[1] = tsm_thrsel_m0[2] | tsm_thrsel_m0[3] | tsm_thrsel_m0[6] | tsm_thrsel_m0[7];
assign conf_rd_thr_id[2] = tsm_thrsel_m0[4] | tsm_thrsel_m0[5] | tsm_thrsel_m0[6] | tsm_thrsel_m0[7];

// conf_addr_in[4:0]
// 4:3 - tid in a TG
// 2:0 - tsb conf reg id
assign conf_addr_in[4:3] = conf_rd_thr_id[1:0];
assign conf_addr_in[2] = 1'b0;
assign conf_addr_in[1] = ~zero_ctx;
assign conf_addr_in[0] = conf_index[1];
// mra_rd_en = 01 for TG0, mra_rd_en=10 for TG1
assign conf_mra_rd_en[1:0] = {conf_rd_thr_id[2],~conf_rd_thr_id[2]};


//0in bits_on -var {conf_rd_en, rr_rd_en} -max 1
assign htc_mra_addr_in[4:0] = (conf_addr_in[4:0] & {5{conf_rd_en}}) |  
                              (rr_addr_in[4:0] & {5{rr_rd_en}});
assign htc_mra_rd_en[1:0] = (conf_mra_rd_en[1:0] & {2{conf_rd_en}}) |  
                            (rr_mra_rd_en[1:0] & {2{rr_rd_en}});

// detect the condition where the thread selected is the same as the one which has tlbmiss
assign thr_valid_miss_lo_m0 = (htc_thr_valid_m0[3:0] == htc_tlb_miss_m0[3:0]) & |(htc_thr_valid_m0[3:0]);
assign thr_valid_miss_hi_m0 = (htc_thr_valid_m0[7:4] == htc_tlb_miss_m0[7:4]) & |(htc_thr_valid_m0[7:4]);


//********************************************************************************
// PROCESS TSBPTR READ REQUEST (M0)
//********************************************************************************
assign tsbrd_valid_m0 = asi_tsb_ptr_req_valid;

// decode tsbptr request
assign htc_tsbrd_valid_m0[0] = ~asi_tsb_ptr_req[2] & ~asi_tsb_ptr_req[1] & ~asi_tsb_ptr_req[0] & tsbrd_valid_m0;
assign htc_tsbrd_valid_m0[1] = ~asi_tsb_ptr_req[2] & ~asi_tsb_ptr_req[1] &  asi_tsb_ptr_req[0] & tsbrd_valid_m0;
assign htc_tsbrd_valid_m0[2] = ~asi_tsb_ptr_req[2] &  asi_tsb_ptr_req[1] & ~asi_tsb_ptr_req[0] & tsbrd_valid_m0;
assign htc_tsbrd_valid_m0[3] = ~asi_tsb_ptr_req[2] &  asi_tsb_ptr_req[1] &  asi_tsb_ptr_req[0] & tsbrd_valid_m0;
assign htc_tsbrd_valid_m0[4] =  asi_tsb_ptr_req[2] & ~asi_tsb_ptr_req[1] & ~asi_tsb_ptr_req[0] & tsbrd_valid_m0;
assign htc_tsbrd_valid_m0[5] =  asi_tsb_ptr_req[2] & ~asi_tsb_ptr_req[1] &  asi_tsb_ptr_req[0] & tsbrd_valid_m0;
assign htc_tsbrd_valid_m0[6] =  asi_tsb_ptr_req[2] &  asi_tsb_ptr_req[1] & ~asi_tsb_ptr_req[0] & tsbrd_valid_m0;
assign htc_tsbrd_valid_m0[7] =  asi_tsb_ptr_req[2] &  asi_tsb_ptr_req[1] &  asi_tsb_ptr_req[0] & tsbrd_valid_m0;


mmu_htc_ctl_msff_ctl_macro__width_6 m1_stg_lat  
(
 .scan_in(m1_stg_lat_scanin),
 .scan_out(m1_stg_lat_scanout),
 .l1clk( l1clk ),
 .din  ({zero_ctx, conf_index[1:0], conf_addr_in[2:0]}),
 .dout ({zero_ctx_m1, conf_index_m1[1:0], conf_addr_m1[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_8 conf_prevalid_lat  
(
 .scan_in(conf_prevalid_lat_scanin),
 .scan_out(conf_prevalid_lat_scanout),
 .l1clk		( l1clk ),
 .din  		(htc_thr_valid_m0[7:0]),
 .dout 		(thr_prevalid_m1[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign tsbrd_z_m0 = 
       ( asd0_zero_context & ~asi_tsb_ptr_req[2] & tsbrd_valid_m0) | 
       ( asd1_zero_context &  asi_tsb_ptr_req[2] & tsbrd_valid_m0) ;

assign tsbrd_nz_m0 = 
       (~asd0_zero_context & ~asi_tsb_ptr_req[2] & tsbrd_valid_m0) | 
       (~asd1_zero_context &  asi_tsb_ptr_req[2] & tsbrd_valid_m0) ;

// latch tsbptr read requests
mmu_htc_ctl_msff_ctl_macro__width_11 tsbptr_lat  
(
 .scan_in(tsbptr_lat_scanin),
 .scan_out(tsbptr_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({asi_tsb_ptr_number[0], tsbrd_z_m0, tsbrd_nz_m0, htc_tsbrd_valid_m0[7:0]}),
 .dout 		({tsbrd_tsbptr_m1[0], tsbrd_z_m1, tsbrd_nz_m1, htc_tsbrd_valid_m1[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


assign asi_tsb_ptr_number_unused =asi_tsb_ptr_number[1];


//********************************************************************************
// LATCH THE PREDICTION ROW READ OUT in mmu_htd_dp (M0)
// ALSO LATCH THE INDEX
//********************************************************************************
mmu_htc_ctl_msff_ctl_macro__width_22 predrow0_lat  
(
 .scan_in(predrow0_lat_scanin),
 .scan_out(predrow0_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({htd_pred0_idx_m0[5:0],htd_pred0_m0[15:0]}),
 .dout 		({htd_pred0_idx_m1[5:0],htd_pred0_m1[15:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_22 predrow1_lat  
(
 .scan_in(predrow1_lat_scanin),
 .scan_out(predrow1_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({htd_pred1_idx_m0[5:0],htd_pred1_m0[15:0]}),
 .dout 		({htd_pred1_idx_m1[5:0],htd_pred1_m1[15:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


mmu_htc_ctl_msff_ctl_macro__width_8 tlbmiss_lat  
(
 .scan_in(tlbmiss_lat_scanin),
 .scan_out(tlbmiss_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({htc_tlb_miss_m0[7:0]}),
 .dout 		({htc_tlb_miss_m1[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_2 tlbvalidmiss_lat  
(
 .scan_in(tlbvalidmiss_lat_scanin),
 .scan_out(tlbvalidmiss_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({thr_valid_miss_hi_m0,thr_valid_miss_lo_m0}),
 .dout 		({thr_valid_miss_hi_m1,thr_valid_miss_lo_m1}),
  .siclk(siclk),
  .soclk(soclk)
);

//0in bits_on -var {thr_valid_miss_hi_m1, thr_valid_miss_lo_m1} -max 1


//********************************************************************************
// READ OUT PREDICTION TABLE AND STORE THE INDEX AND PREDICTION HISTORY IN
// A TABLE (M1)
//********************************************************************************
// Read out the TSB prediction table for the two tlb misses,
// and write them to a register

// Logically prediction table has 64 entries, each entry is 2 bits.
// If MSB=1, then predict TSB 1, else predict TSB 0.
// The table is arranged as 4 registers, each 32 bits wide, in htd
// Bits [5:4] of pred_idx select, 1 of 4 registers in htd (htd_pred_m1[31:0]), 
// and bits [3:0] select 2 bits out of the 32 bits.


// thread group 0
assign pred0_bit_m1[1:0] = ({2{~htd_pred0_idx_m1[2] & ~htd_pred0_idx_m1[1] & ~htd_pred0_idx_m1[0]}} & htd_pred0_m1[1:0])   |
                           ({2{~htd_pred0_idx_m1[2] & ~htd_pred0_idx_m1[1] &  htd_pred0_idx_m1[0]}} & htd_pred0_m1[3:2])   |
                           ({2{~htd_pred0_idx_m1[2] &  htd_pred0_idx_m1[1] & ~htd_pred0_idx_m1[0]}} & htd_pred0_m1[5:4])   |
                           ({2{~htd_pred0_idx_m1[2] &  htd_pred0_idx_m1[1] &  htd_pred0_idx_m1[0]}} & htd_pred0_m1[7:6])   |
                           ({2{ htd_pred0_idx_m1[2] & ~htd_pred0_idx_m1[1] & ~htd_pred0_idx_m1[0]}} & htd_pred0_m1[9:8])   |
                           ({2{ htd_pred0_idx_m1[2] & ~htd_pred0_idx_m1[1] &  htd_pred0_idx_m1[0]}} & htd_pred0_m1[11:10]) |
                           ({2{ htd_pred0_idx_m1[2] &  htd_pred0_idx_m1[1] & ~htd_pred0_idx_m1[0]}} & htd_pred0_m1[13:12]) |
                           ({2{ htd_pred0_idx_m1[2] &  htd_pred0_idx_m1[1] &  htd_pred0_idx_m1[0]}} & htd_pred0_m1[15:14]);

//thread group1
assign pred1_bit_m1[1:0] = ({2{~htd_pred1_idx_m1[2] & ~htd_pred1_idx_m1[1] & ~htd_pred1_idx_m1[0]}} & htd_pred1_m1[1:0])   |
                           ({2{~htd_pred1_idx_m1[2] & ~htd_pred1_idx_m1[1] &  htd_pred1_idx_m1[0]}} & htd_pred1_m1[3:2])   |
                           ({2{~htd_pred1_idx_m1[2] &  htd_pred1_idx_m1[1] & ~htd_pred1_idx_m1[0]}} & htd_pred1_m1[5:4])   |
                           ({2{~htd_pred1_idx_m1[2] &  htd_pred1_idx_m1[1] &  htd_pred1_idx_m1[0]}} & htd_pred1_m1[7:6])   |
                           ({2{ htd_pred1_idx_m1[2] & ~htd_pred1_idx_m1[1] & ~htd_pred1_idx_m1[0]}} & htd_pred1_m1[9:8])   |
                           ({2{ htd_pred1_idx_m1[2] & ~htd_pred1_idx_m1[1] &  htd_pred1_idx_m1[0]}} & htd_pred1_m1[11:10]) |
                           ({2{ htd_pred1_idx_m1[2] &  htd_pred1_idx_m1[1] & ~htd_pred1_idx_m1[0]}} & htd_pred1_m1[13:12]) |
                           ({2{ htd_pred1_idx_m1[2] &  htd_pred1_idx_m1[1] &  htd_pred1_idx_m1[0]}} & htd_pred1_m1[15:14]);


// use tlb_miss_m1 to latch the prediction address and prediction bits for the thread whose
// request is being sent out. This will be used to predict the TSB and will be used to update the prediction
// table on a tsb hit.
assign pred_idx0_in[5:0] = ({6{htc_tlb_miss_m1[0]}} & htd_pred0_idx_m1[5:0]) |
                           ({6{~htc_tlb_miss_m1[0]}} & pred_idx0[5:0]);
assign pred_idx1_in[5:0] = ({6{htc_tlb_miss_m1[1]}} & htd_pred0_idx_m1[5:0]) |
                           ({6{~htc_tlb_miss_m1[1]}} & pred_idx1[5:0]);
assign pred_idx2_in[5:0] = ({6{htc_tlb_miss_m1[2]}} & htd_pred0_idx_m1[5:0]) |
                           ({6{~htc_tlb_miss_m1[2]}} & pred_idx2[5:0]);
assign pred_idx3_in[5:0] = ({6{htc_tlb_miss_m1[3]}} & htd_pred0_idx_m1[5:0]) |
                           ({6{~htc_tlb_miss_m1[3]}} & pred_idx3[5:0]);
assign pred_idx4_in[5:0] = ({6{htc_tlb_miss_m1[4]}} & htd_pred1_idx_m1[5:0]) |
                           ({6{~htc_tlb_miss_m1[4]}} & pred_idx4[5:0]);
assign pred_idx5_in[5:0] = ({6{htc_tlb_miss_m1[5]}} & htd_pred1_idx_m1[5:0]) |
                           ({6{~htc_tlb_miss_m1[5]}} & pred_idx5[5:0]);
assign pred_idx6_in[5:0] = ({6{htc_tlb_miss_m1[6]}} & htd_pred1_idx_m1[5:0]) |
                           ({6{~htc_tlb_miss_m1[6]}} & pred_idx6[5:0]);
assign pred_idx7_in[5:0] = ({6{htc_tlb_miss_m1[7]}} & htd_pred1_idx_m1[5:0]) |
                           ({6{~htc_tlb_miss_m1[7]}} & pred_idx7[5:0]);

assign pred_bit0_in[1:0] = ({2{htc_tlb_miss_m1[0]}} & pred0_bit_m1[1:0]) |
                           ({2{~htc_tlb_miss_m1[0]}} & pred_bit0[1:0]);
assign pred_bit1_in[1:0] = ({2{htc_tlb_miss_m1[1]}} & pred0_bit_m1[1:0]) |
                           ({2{~htc_tlb_miss_m1[1]}} & pred_bit1[1:0]);
assign pred_bit2_in[1:0] = ({2{htc_tlb_miss_m1[2]}} & pred0_bit_m1[1:0]) |
                           ({2{~htc_tlb_miss_m1[2]}} & pred_bit2[1:0]);
assign pred_bit3_in[1:0] = ({2{htc_tlb_miss_m1[3]}} & pred0_bit_m1[1:0]) |
                           ({2{~htc_tlb_miss_m1[3]}} & pred_bit3[1:0]);
assign pred_bit4_in[1:0] = ({2{htc_tlb_miss_m1[4]}} & pred1_bit_m1[1:0]) |
                           ({2{~htc_tlb_miss_m1[4]}} & pred_bit4[1:0]);
assign pred_bit5_in[1:0] = ({2{htc_tlb_miss_m1[5]}} & pred1_bit_m1[1:0]) |
                           ({2{~htc_tlb_miss_m1[5]}} & pred_bit5[1:0]);
assign pred_bit6_in[1:0] = ({2{htc_tlb_miss_m1[6]}} & pred1_bit_m1[1:0]) |
                           ({2{~htc_tlb_miss_m1[6]}} & pred_bit6[1:0]);
assign pred_bit7_in[1:0] = ({2{htc_tlb_miss_m1[7]}} & pred1_bit_m1[1:0]) |
                           ({2{~htc_tlb_miss_m1[7]}} & pred_bit7[1:0]);

mmu_htc_ctl_msff_ctl_macro__width_8 pred0_lat 
(
 .scan_in(pred0_lat_scanin),
 .scan_out(pred0_lat_scanout),
 .l1clk( l1clk),
 .din  ({pred_idx0_in[5:0], pred_bit0_in[1:0]}),
 .dout ({pred_idx0[5:0], pred_bit0[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_8 pred1_lat 
(
 .scan_in(pred1_lat_scanin),
 .scan_out(pred1_lat_scanout),
 .l1clk( l1clk),
 .din  ({pred_idx1_in[5:0], pred_bit1_in[1:0]}),
 .dout ({pred_idx1[5:0], pred_bit1[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_8 pred2_lat 
(
 .scan_in(pred2_lat_scanin),
 .scan_out(pred2_lat_scanout),
 .l1clk( l1clk),
 .din  ({pred_idx2_in[5:0], pred_bit2_in[1:0]}),
 .dout ({pred_idx2[5:0], pred_bit2[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_8 pred3_lat 
(
 .scan_in(pred3_lat_scanin),
 .scan_out(pred3_lat_scanout),
 .l1clk( l1clk),
 .din  ({pred_idx3_in[5:0], pred_bit3_in[1:0]}),
 .dout ({pred_idx3[5:0], pred_bit3[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_8 pred4_lat 
(
 .scan_in(pred4_lat_scanin),
 .scan_out(pred4_lat_scanout),
 .l1clk( l1clk),
 .din  ({pred_idx4_in[5:0], pred_bit4_in[1:0]}),
 .dout ({pred_idx4[5:0], pred_bit4[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_8 pred5_lat 
(
 .scan_in(pred5_lat_scanin),
 .scan_out(pred5_lat_scanout),
 .l1clk( l1clk),
 .din  ({pred_idx5_in[5:0], pred_bit5_in[1:0]}),
 .dout ({pred_idx5[5:0], pred_bit5[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_8 pred6_lat 
(
 .scan_in(pred6_lat_scanin),
 .scan_out(pred6_lat_scanout),
 .l1clk( l1clk),
 .din  ({pred_idx6_in[5:0], pred_bit6_in[1:0]}),
 .dout ({pred_idx6[5:0], pred_bit6[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_8 pred7_lat 
(
 .scan_in(pred7_lat_scanin),
 .scan_out(pred7_lat_scanout),
 .l1clk( l1clk),
 .din  ({pred_idx7_in[5:0], pred_bit7_in[1:0]}),
 .dout ({pred_idx7[5:0], pred_bit7[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );
                             

/////////////////////////////////////////////////////////////////////
// MRA Access Cycle (M1)
/////////////////////////////////////////////////////////////////////
assign htc_thr_valid_m1[7:0] =  ({8{asi_mra_req_grant & room_avail_m1}} & thr_prevalid_m1[7:0]);
// cfg_done comes on for 1 cycle after the last cfg is read.
assign cfg_done_m1[7:0] = {8{conf_index_m1[1] & conf_index_m1[0]}} & htc_thr_valid_m1[7:0];

assign cfg_read_tg0_m1 = |(htc_thr_valid_m1[3:0]);
assign cfg_read_tg1_m1 = |(htc_thr_valid_m1[7:4]);
assign htc_valid_m1 = |(htc_thr_valid_m1[7:0]);


assign thr_valid_m2_in[7:0] = htc_thr_valid_m1[7:0] & ~htc_tsb_done_hw2[7:0];


assign tsbrd_valid_m1 = tsbrd_z_m1 | tsbrd_nz_m1;
assign tsbrd_tg0_m1 = ~(|(htc_tsbrd_valid_m1[7:4])) & tsbrd_valid_m1;
assign tsbrd_tg1_m1 =  (|(htc_tsbrd_valid_m1[7:4])) & tsbrd_valid_m1;

//assign htc_va_rd_m2_in[7:0] = thr_valid_m2_in[7:0] | htc_tsbrd_valid_m1[7:0];
assign htc_va_rd_m2_in[7:0] = htc_thr_valid_m1[7:0] | htc_tsbrd_valid_m1[7:0];

assign htc_m1_clken = (|(htc_va_rd_m2_in[7:0])) | ~htc_mmu_pmen;

//0in bits_on -var {cfg_read_tg0_m1, cfg_read_tg1_m1, rr_read_tg0_hw3, rr_read_tg1_hw3, tsbrd_tg0_m1, tsbrd_tg1_m1} -max 1
assign htc_mra_sel[1] = (cfg_read_tg1_m1 | rr_read_tg1_hw3 | tsbrd_tg1_m1 );
assign htc_mra_sel[0] = (cfg_read_tg0_m1 | rr_read_tg0_hw3 | tsbrd_tg0_m1 );


// If prediction is disabled, then
// if conf_index == 00                  then read tsb0 => sel_mra_up
// if conf_index == 01                  then read tsb1 => sel_mra_lo
// if conf_index == 10                  then read tsb2 => sel_mra_up
// if conf_index == 11                  then read tsb3 => sel_mra_lo

// If prediction is enabled, then
// if conf_index == 00 and ~pred_bit[1] then read tsb0 => sel_mra_up
// if conf_index == 00 and  pred_bit[1] then read tsb1 => sel_mra_lo
// if conf_index == 01 and ~pred_bit[1] then read tsb1 => sel_mra_lo
// if conf_index == 01 and  pred_bit[1] then read tsb0 => sel_mra_up
// if conf_index == 10                  then read tsb2 => sel_mra_up
// if conf_index == 11                  then read tsb3 => sel_mra_lo


//0in bits_on -var {conf_sel_mra_lo, conf_sel_mra_up} -max 1

assign pred_en = |(htc_hwtw_pred[7:0] & htc_thr_valid_m1[7:0]);

// read out prediction bits
// If thr_prevalid is same as the one which had a tlbmiss in m0 (thr_valid_miss_lo or thr_valid_miss_hi),
// then use pred0_bit_m1 or pred1_bit_m1, else get the prediction information from latched data (pred_bit7-0)
assign pred_bit_m1[1] = (thr_valid_miss_lo_m1 & pred0_bit_m1[1]) |
                        (thr_valid_miss_hi_m1 & pred1_bit_m1[1]) |
                        (thr_prevalid_m1[0] & ~thr_valid_miss_lo_m1 & pred_bit0[1]) |
                        (thr_prevalid_m1[1] & ~thr_valid_miss_lo_m1 & pred_bit1[1]) |
                        (thr_prevalid_m1[2] & ~thr_valid_miss_lo_m1 & pred_bit2[1]) |
                        (thr_prevalid_m1[3] & ~thr_valid_miss_lo_m1 & pred_bit3[1]) |
                        (thr_prevalid_m1[4] & ~thr_valid_miss_hi_m1 & pred_bit4[1]) |
                        (thr_prevalid_m1[5] & ~thr_valid_miss_hi_m1 & pred_bit5[1]) |
                        (thr_prevalid_m1[6] & ~thr_valid_miss_hi_m1 & pred_bit6[1]) |
                        (thr_prevalid_m1[7] & ~thr_valid_miss_hi_m1 & pred_bit7[1]);


assign conf_sel_mra_lo = ((~pred_en & conf_index_m1[0]) |                
                         (conf_index_m1[1] & conf_index_m1[0]) |
                         (pred_en & ~pred_bit_m1[1] & ~conf_index_m1[1] &  conf_index_m1[0]) |
                         (pred_en &  pred_bit_m1[1] & ~conf_index_m1[1] & ~conf_index_m1[0])) & htc_valid_m1;

assign conf_sel_mra_up = ((~pred_en & ~conf_index_m1[0]) |                
                         (conf_index_m1[1] & ~conf_index_m1[0]) |
                         (pred_en & ~pred_bit_m1[1] & ~conf_index_m1[1] & ~conf_index_m1[0]) |
                         (pred_en &  pred_bit_m1[1] & ~conf_index_m1[1] &  conf_index_m1[0])) & htc_valid_m1;


assign tsbrd_sel_mra_lo =  tsbrd_tsbptr_m1[0] & tsbrd_valid_m1;
assign tsbrd_sel_mra_up =  ~tsbrd_tsbptr_m1[0] & tsbrd_valid_m1;

assign htc_sel_mra_lo = conf_sel_mra_lo | tsbrd_sel_mra_lo;
assign htc_sel_mra_up = conf_sel_mra_up | tsbrd_sel_mra_up;

//0in bits_on -var {conf_sel_mra_lo, conf_sel_mra_up, tsbrd_sel_mra_lo, tsbrd_sel_mra_up} -max 1

// conf_index_m2 should reflect the real tsb ptr being read.
// It is used to  keep track of tsb ptrs being returned out of order.
// it is the function of tsb prediction and conf_index_m1.
assign conf_index_m2_in[1:0] = {2{htc_valid_m1}} & conf_index_m1[1:0];


//asi_tsb_hwtw_en_0[0] : hwtw_en for tg0, tsb0,tsb2
//asi_tsb_hwtw_en_0[1] : hwtw_en for tg0, tsb1,tsb3

assign hwtw_en_tg0 = (htc_sel_mra_lo & asi_tsb_hwtw_enable_0[1]) |
                     (htc_sel_mra_up & asi_tsb_hwtw_enable_0[0]);

assign hwtw_en_tg1 = (htc_sel_mra_lo & asi_tsb_hwtw_enable_1[1]) |
                     (htc_sel_mra_up & asi_tsb_hwtw_enable_1[0]);

//assign mra_data_38 = (htc_mra_sel[0] & mra0_data_38) |
//                     (htc_mra_sel[1] & mra1_data_38);

//assign mra_data_77 = (htc_mra_sel[0] & mra0_data_77) |
//                     (htc_mra_sel[1] & mra1_data_77);

                     
assign hwtw_en_m2_in = (htc_mra_sel[0] & hwtw_en_tg0) |
                       (htc_mra_sel[1] & hwtw_en_tg1);

assign htc_mra_sel_0 = htc_mra_sel[0];

//assign hwtw_en_m2_in = asi_tsb_hwtw_enable;


mmu_htc_ctl_msff_ctl_macro__width_17 m2_stg_lat2  (
 .scan_in(m2_stg_lat2_scanin),
 .scan_out(m2_stg_lat2_scanout),
 .l1clk( l1clk ),
 .din ({hwtw_en_m2_in, cfg_read_tg0_m1, cfg_read_tg1_m1, zero_ctx_m1, conf_index_m2_in[1:0], conf_addr_m1[2:0], thr_valid_m2_in[7:0]}),
 .dout({hwtw_en_m2,    cfg_read_tg0_m2, cfg_read_tg1_m2, zero_ctx_m2, htc_conf_index_m2[1:0], conf_addr_m2[2:0], htc_thr_valid_m2[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


/////////////////////////////////////////////////////////////////////
// TSB Pointer Generation (M2)
/////////////////////////////////////////////////////////////////////

assign htc_zero_ctx_m2 = zero_ctx_m2;

//assign htc_ignore_ctx_m2 = ~zero_ctx_m2 & (htd_cfg_usc0_m2 | htd_cfg_usc1_m2) ;

// Valid tsbptr exists if 
// => thr_valid_m2
// => no tsb_hit in m2 cycle
// => & hwtw is enable (else we don't need to send the request to gasket)

// cancel tsbptr if tsb_hit_hw2
assign htc_vld_tsbptr_m2[0] = htc_thr_valid_m2[0] & ~htc_tsb_done_hw2[0] & hwtw_en_m2;
assign htc_vld_tsbptr_m2[1] = htc_thr_valid_m2[1] & ~htc_tsb_done_hw2[1] & hwtw_en_m2;
assign htc_vld_tsbptr_m2[2] = htc_thr_valid_m2[2] & ~htc_tsb_done_hw2[2] & hwtw_en_m2;
assign htc_vld_tsbptr_m2[3] = htc_thr_valid_m2[3] & ~htc_tsb_done_hw2[3] & hwtw_en_m2;
assign htc_vld_tsbptr_m2[4] = htc_thr_valid_m2[4] & ~htc_tsb_done_hw2[4] & hwtw_en_m2;
assign htc_vld_tsbptr_m2[5] = htc_thr_valid_m2[5] & ~htc_tsb_done_hw2[5] & hwtw_en_m2;
assign htc_vld_tsbptr_m2[6] = htc_thr_valid_m2[6] & ~htc_tsb_done_hw2[6] & hwtw_en_m2;
assign htc_vld_tsbptr_m2[7] = htc_thr_valid_m2[7] & ~htc_tsb_done_hw2[7] & hwtw_en_m2;

assign vld_tsbptr_thr_id_m2[0] = htc_vld_tsbptr_m2[1] | htc_vld_tsbptr_m2[3] | htc_vld_tsbptr_m2[5] | htc_vld_tsbptr_m2[7] ; 
assign vld_tsbptr_thr_id_m2[1] = htc_vld_tsbptr_m2[2] | htc_vld_tsbptr_m2[3] | htc_vld_tsbptr_m2[6] | htc_vld_tsbptr_m2[7] ; 
assign vld_tsbptr_thr_id_m2[2] = htc_vld_tsbptr_m2[4] | htc_vld_tsbptr_m2[5] | htc_vld_tsbptr_m2[6] | htc_vld_tsbptr_m2[7] ; 

assign vld_tsbptr_rdy_m2 = |(htc_vld_tsbptr_m2[7:0]);


// for ecc_err on MRA read, we need to report the error even if hwtw is not enabled in the tsb.
// 
// Do not enable cfg_ecc_err if tsb_miss has already been signalled.
// This can happen if the last cfg read has hwtw disabled, and all prior cfg reads have completed and
// have resulted in tsb miss. In this case we signal a tsbmiss without waiting for the parity error
// check on the last cfg read.
assign htc_cfg_ecc_err_en_m2[7:0] = htc_thr_valid_m2[7:0] & ~htc_tsb_done_hw2[7:0] & ~tsm_tsb_miss_hw2[7:0];

assign cfg_ecc_err_index_m2[2:0] = conf_addr_m2[2:0];


mmu_htc_ctl_msff_ctl_macro__width_13 m3_stg_lat1  
(
 .scan_in(m3_stg_lat1_scanin),
 .scan_out(m3_stg_lat1_scanout),
 .l1clk( l1clk ),
 .din  ({cfg_read_tg0_m2, cfg_read_tg1_m2, htc_cfg_ecc_err_en_m2[7:0],
         cfg_ecc_err_index_m2[2:0]}),
 .dout ({cfg_read_tg0_m3, cfg_read_tg1_m3, htc_cfg_ecc_err_en_m3[7:0],
         cfg_ecc_err_index[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

assign mel0_parity_err_m3 = mel0_parity_err;
assign mel1_parity_err_m3 = mel1_parity_err;


assign mra0_ecc_err_lat = (mel0_parity_err_m3 & hwtwmu_en);
assign mra1_ecc_err_lat = (mel1_parity_err_m3 & hwtwmu_en);
assign mra0_err_type_lat[1:0] = {(mel0_parity_err_m3 & hwtwmu_en), 1'b0};
assign mra1_err_type_lat[1:0] = {(mel1_parity_err_m3 & hwtwmu_en), 1'b0};

assign cfg_ecc_err_m3[7:0] = {8{((cfg_read_tg0_m3 & mra0_ecc_err_lat) | (cfg_read_tg1_m3 & mra1_ecc_err_lat))}} &
                             htc_cfg_ecc_err_en_m3[7:0] & ~htc_tsb_done_hw2[7:0] & ~tsm_tsb_miss_hw2[7:0];

assign cfg_ecc_err_type[1:0] = ({2{cfg_read_tg0_m3}} & mra0_err_type_lat[1:0]) |
                               ({2{cfg_read_tg1_m3}} & mra1_err_type_lat[1:0]);

/////////////////////////////////////////////////////////////////////
// TTE Req to Gasket (M3)
// tte read request is sent to gasket in M3. This is when the tsbptr is
// available.
// When a request is M0 in cycle 0, a grant for it will not be available
// until late in cycle 4.
// MMU has a two entry FIFO, q0 and q1,  where requests are queued if they cannot be
// sent to gasket.
// Once two requests have been sent to gkt and q0 and q1 are full, no more
// requests can come down the pipe until gkt gives a grant. The cycle after grant,
// a new req can be valid in M1.
/////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------
//        | 0   | 1   | 2   | 3   | 4   | 5   | 6   | 7   |     |
//-------------------------------------------------------------------
// M0     |RQA  |RQB  |RQC  |RQD  |RQE  |RQE  |RQE  |RQE  | RQF | RQG | RQH |
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//------------------------------------------------------------------------------------
// M1     |IN   |RQA  |RQB  |RQC  |RQD  |     |     |     |RQE  | RQF | RQG | RQH |     
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//------------------------------------------------------------------------------------
// M2     |     |     |RQA  |RQB  |RQC  |RQD  |     |     |     |RQE  | RQF | RQG | RQH |
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//------------------------------------------------------------------------------------
// M3     |     |     |     |RQA  |RQB  |RQC  |RQD  |     |     |     | RQE | RQF | RQG | RQH |
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//-----------------------------------------------------------------------------------------------
// mmu_l15|     |     |     |RQA  |RQB  |     |     |     |RQC  |RQD  | RQE | RQF | RQG | RQH |
// _valid |     |     |     |     |     |     |     |     |     |     |     |     |
//-----------------------------------------------------------------------------------------------
// grant  |     |     |     |     |     |     |     | A   | B   | C   | D   | E   |        
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//-----------------------------------------------------------------------------------------------
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//FIFO    |     |     |     |ct =0|ct =1|ct =2|ct =2|ct =2|ct =2|ct =2|ct =2|ct =1|ct =0|
//        |     |     |     |q0=0 |q0=0 |q0=C |q0=C |q0=C |q0=D |q0=E |q0=0 |q0=0 |q0=0 |
//        |     |     |     |q1=0 |q1=0 |q1=0 |q1=D |q1=D |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |
//-----------------------------------------------------------------------------------------------
// room   |  1  | 1   | 1   | 1   | 1   | 0   | 0   | 0   | 1   | 1   | 1   | 1   | 1
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//-----------------------------------------------------------------------------------------------

//----------------------------------------------------------------------------------------------------
// M0     |RQA  |RQB  |RQC  |RQD  | RQE | RQF | RQG | RQH | RQI | RQI |
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//----------------------------------------------------------------------------------------------------------
// M1     |     |RQA  |RQB  |RQC  |RQD  |RQE  | RQF | RQG | RQH |     | RQI | RQJ |
//        |     |     |     |     |     |     |     |     |     |     |     |     |     |
//----------------------------------------------------------------------------------------------------------
// M2     |     |     |RQA  |RQB  |RQC  |RQD  |RQE  | RQF | RQG | RQH |     | RQI | RQJ |
//        |     |     |     |     |     |     |     |     |     |     |     |     |     |     |
//----------------------------------------------------------------------------------------------------------
// M3     |     |     |     |RQA  |RQB  |RQC  |RQD  |RQE  | RQF | RQG | RQH |     | RQI | RQJ |
//        |     |     |     |     |     |     |     |     |     |     |     |     |     |     |     |
//----------------------------------------------------------------------------------------------------------
// mmu_l15|     |     |     |RQA  |RQB  |RQC  |RQD  |RQE  | RQF | RQG | RQH |     | RQI | RQJ |
// _valid |     |     |     |     |     |     |     |     |     |     |     |     |     |     |     |
//----------------------------------------------------------------------------------------------------------
// grant  |     |     |     |     |A    | B   | C   | D   |     | E   | F   | G   | H   |     | I   | J
//        |     |     |     |     |     |     |     |     |     |     |     |     |     |     |     |
//----------------------------------------------------------------------------------------------------------
//FIFO    |     |     |     | ct=0| ct=1| ct=1| ct=1| ct=1| ct=1| ct=2| ct=2| ct=2| ct=1| ct=1| ct=2|
//        |     |     |     |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |
//        |     |     |     |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |
//----------------------------------------------------------------------------------------------------------
// room   |  1  | 1   | 1   | 1   | 1   | 1   | 1   | 1   | 1   | 0   | 1   | 1   | 1   | 1
//        |     |     |     |     |     |     |     |     |     |     |     |     |
//----------------------------------------------------------------------------------------------------------

assign req_m2 = vld_tsbptr_rdy_m2;
assign htc_l15_cpkt_15_13[2:0] = vld_tsbptr_thr_id_m2[2:0];   //tid
assign htc_l15_cpkt_9_8[1:0] = htc_conf_index_m2[1:0];        //tag

/////////////////////////////////////////////////////////////////////
// Tracking GKT buffers
// to be able to send a new request out in the cycle after grant, use
// next_gkt_count.
/////////////////////////////////////////////////////////////////////
assign next_gkt_count[1:0] = ({2{~gkt_grant & ~mmu_l15_valid_int}} & gkt_count[1:0]) |
                             ({2{ gkt_grant &  mmu_l15_valid_int}} & gkt_count[1:0]) |
                             ({2{~gkt_grant &  mmu_l15_valid_int}} & (gkt_count[1:0]+2'b01)) |
                             ({2{ gkt_grant & ~mmu_l15_valid_int}} & (gkt_count[1:0]-2'b01));

mmu_htc_ctl_msff_ctl_macro__width_2 gkt_count_reg  (
 .scan_in(gkt_count_reg_scanin),
 .scan_out(gkt_count_reg_scanout),
 .l1clk( l1clk ),
 .din (next_gkt_count[1:0]),
 .dout(gkt_count[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign gkt_full = next_gkt_count[1];

/////////////////////////////////////////////////////////////////////
// q0 and q1 valids
/////////////////////////////////////////////////////////////////////
assign v0_in = (gkt_full & req_m2 ) |                     //new
               (v0 & ~v1 & gkt_grant & req_m2) |  //new
               (v0 & ~gkt_grant) |                //hold
               (v1 & gkt_grant);                  //shft

assign v1_in = (v0 & req_m2 & ~gkt_grant) |       //new
               (v1 & req_m2) |                            //new
               (v1 & ~gkt_grant);                 //hold

mmu_htc_ctl_msff_ctl_macro__width_2 qv_reg  (
 .scan_in(qv_reg_scanin),
 .scan_out(qv_reg_scanout),
 .l1clk( l1clk ),
 .din ({v0_in, v1_in}),
 .dout({v0,v1}),
  .siclk(siclk),
  .soclk(soclk)
);

assign q0_val = v0;
assign q1_val = v1;

/////////////////////////////////////////////////////////////////////
// q0 and q1 buffer ctl
// optimize to make minimum use of grant
/////////////////////////////////////////////////////////////////////
assign htc_wr_q1new = req_m2;

assign htc_wr_q0new = (~v0 & req_m2) |                           
                      (v0 & ~v1 & gkt_grant & req_m2);
assign htc_wr_q0new_nogrant = (~v0 & req_m2);

assign htc_wr_q0new_grant = (~v0 & req_m2) |                           
                            (v0 & ~v1 & req_m2);

// shift from q1 to q0 if q1 is valid and we get grant.
assign htc_shift_q1 = v1 & gkt_grant;
//assign htc_shift_q1_nogrant = 1'b0;

assign htc_shift_q1_grant = v1;

//0in bits_on -var {htc_wr_q0new_grant, htc_shift_q1_grant} -max 1
//0in bits_on -var {htc_wr_q0new, htc_shift_q1} -max 1


// (htc_wr_q0new | htc_shift_q1) is very late to be used as an enable for q0
// Instead used htc_q0_en which is an early signal but does not get
// use grant
//assign htc_q0_clken = v0 | v1 | req_m2 | ~htc_mmu_pmen;


// implement q0 and q1 for cpkt
assign q1_cpkt_in[4:0] = ({5{htc_wr_q1new}} & {htc_l15_cpkt_15_13[2:0],htc_l15_cpkt_9_8[1:0]}) |
                          ({5{~htc_wr_q1new}} & q1_cpkt[4:0]);

mmu_htc_ctl_msff_ctl_macro__width_5 q1cpkt_reg  (
 .scan_in(q1cpkt_reg_scanin),
 .scan_out(q1cpkt_reg_scanout),
 .l1clk( l1clk ),
 .din (q1_cpkt_in[4:0]),
 .dout(q1_cpkt[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign q0_cpkt_in[4:0] = ({5{htc_wr_q0new}} & {htc_l15_cpkt_15_13[2:0],htc_l15_cpkt_9_8[1:0]}) |
                          ({5{htc_shift_q1}} & q1_cpkt[4:0]) |
                          ({5{~htc_wr_q0new & ~htc_shift_q1}} & q0_cpkt[4:0]) ;

mmu_htc_ctl_msff_ctl_macro__width_5 q0cpkt_reg  (
 .scan_in(q0cpkt_reg_scanin),
 .scan_out(q0cpkt_reg_scanout),
 .l1clk( l1clk ),
 .din (q0_cpkt_in[4:0]),
 .dout(q0_cpkt[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);
/////////////////////////////////////////////////////////////////////
// output valid control and output buffer control (m3reg)
/////////////////////////////////////////////////////////////////////
// htc_l15_valid is flopped and sent out as mmu_l15_valid
assign htc_l15_valid = ((req_m2 | q0_val) & ~gkt_full);

// htc_l15_valid is very late to be used as an enable to htd output flop.
// Instead used htc_l15_en which is an early signal but does not get
// turned off if gkt is full
assign htc_l15_en = req_m2 | q0_val;

assign htc_wr_m3new = ~q0_val & req_m2;
assign htc_wr_m3q0 = q0_val;

assign {mmu_l15_cpkt_in_15_13_in[2:0],mmu_l15_cpkt_in_9_8_in[1:0]} = ({5{htc_wr_m3new}} & {htc_l15_cpkt_15_13[2:0],htc_l15_cpkt_9_8[1:0]}) |
                                                                     ({5{htc_wr_m3q0}} & q0_cpkt[4:0]);
mmu_htc_ctl_msff_ctl_macro__width_7 cpkt_reg  (
 .scan_in(cpkt_reg_scanin),
 .scan_out(cpkt_reg_scanout),
 .l1clk( l1clk ),
 .din ({htc_l15_valid, htc_l15_valid, mmu_l15_cpkt_in_15_13_in[2:0],mmu_l15_cpkt_in_9_8_in[1:0]}),
 .dout({mmu_l15_valid, mmu_l15_valid_int, mmu_l15_cpkt[2:0],mmu_l15_cpkt[4:3]}),
  .siclk(siclk),
  .soclk(soclk)
);


// actual mmu pkt format:
//assign mmu_l15_cpkt[25] = mmu_l15_valid;
//assign mmu_l15_cpkt[24:20] = 5'b01000;                    //rqtyp
//assign mmu_l15_cpkt[19] = 1'b1;                           //nc
//assign mmu_l15_cpkt[18:16] = cpuid[2:0];                  //cpuid
//assign mmu_l15_cpkt[15:13] = tid 
//assign mmu_l15_cpkt[12:10] = 3'b000;                      //inv,pf,bis
//assign mmu_l15_cpkt[9:7] =  mmuid
//assign mmu_l15_cpkt[7:0] = 8'b0;                          //size

// since only tid and mmuid need to be sent to the gkt, they are compressed to form a 5 bit mmu pkt
// gkt will form the final mmu pkt


//msff_ctl_macro grant_lat (width=8) 
//(
// .scan_in(grant_lat_scanin),
// .scan_out(grant_lat_scanout),
// .l1clk( l1clk ),
// .din ({grant_del[6:0],l15_mmu_grant}),
// .dout({grant_del[7:0]})
//);

assign gkt_grant = l15_mmu_grant;
//assign gkt_grant = grant_del[5];


/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
// ROOM AVAILABLE SIGNAL
// If room is not available, then the request is killed in M1 stage.
// i.e thr_valid_m1 will not come on.
// Also, cindex will not be incremented.
// room is available for a request in m1 in following cases:
// 1. gkt is not full
// 2. gkt is full, q0 is empty, and there is no request either in m3 or m2
// 3. gkt is full, q1 is empty, and there is no request in m3 and m2
/////////////////////////////////////////////////////////////////////
assign room_avail_m1 = (~gkt_count[1]) | 
                       (~q0_val & (~mmu_l15_valid_int | ~req_m2)) |
                       (~q1_val & ~mmu_l15_valid_int & ~req_m2);

/////////////////////////////////////////////////////////////////////
                        

/////////////////////////////////////////////////////////////////////
// L15 to MMU Interface
/////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////
// TRS STATE:   |    NULL      |    VREQ  |    VREQ     |  WAITRR2  |   WAITRR3  |
// |    HW0     |    HW1       |    HW2   |    HW3      |  HW4      |   HW5      | HW6
// |            |              |          |             |           |            |
// | L15 Return | CAM VPN &    | arb      | MRA Access  | RangeCheck|  ra2pahit  | WriteTLB
// |    Data    | Context      | RR rd_en | asi_grant   |           |            |
// |            | TSB hit/Miss |          |             |           |  outofrange| mmu_outofrange
// |            |              |          |             |           |            | mmu_ecc_err
// |            |              | tsb_miss |mmu_tsb_miss |           |            |
// |            |              |          |             |           |            |
//
/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////
// HW0
/////////////////////////////////////////////////////////////////////

assign load_ret_hw0 = l15_mmu_valid & (l15_mmu_cpkt[17:14] == 4'b0101);
assign ret_tid_hw0[7:0] = {(l15_mmu_cpkt[8] &   l15_mmu_cpkt[7] &  l15_mmu_cpkt[6]),
                           (l15_mmu_cpkt[8] &   l15_mmu_cpkt[7] & ~l15_mmu_cpkt[6]),
                           (l15_mmu_cpkt[8] &  ~l15_mmu_cpkt[7] &  l15_mmu_cpkt[6]),
                           (l15_mmu_cpkt[8] &  ~l15_mmu_cpkt[7] & ~l15_mmu_cpkt[6]),
                           (~l15_mmu_cpkt[8] &  l15_mmu_cpkt[7] &  l15_mmu_cpkt[6]),
                           (~l15_mmu_cpkt[8] &  l15_mmu_cpkt[7] & ~l15_mmu_cpkt[6]),
                           (~l15_mmu_cpkt[8] & ~l15_mmu_cpkt[7] &  l15_mmu_cpkt[6]),
                           (~l15_mmu_cpkt[8] & ~l15_mmu_cpkt[7] & ~l15_mmu_cpkt[6])};

// only flag uncorrectable and not data errors. In case of correctable errors,
// just report them asynchronously to tlu.
assign l2_err_hw0 = l15_mmu_cpkt[11] & hwtwl2_en;
assign l2_ecc_err_type_hw0[1:0] = {l15_mmu_cpkt[11],l15_mmu_cpkt[10]};
assign ret_tsbid_hw0[1:0] = l15_mmu_cpkt[4:3];
assign l2miss_hw0 = l15_mmu_cpkt[13];

assign l2_cerr_hw0 = ~l15_mmu_cpkt[11] & l15_mmu_cpkt[10] & hwtwl2_en;


// latch data coming from gkt
mmu_htc_ctl_msff_ctl_macro__width_19 gkt_hw0_lat0  
(
 .scan_in(gkt_hw0_lat0_scanin),
 .scan_out(gkt_hw0_lat0_scanout),
 .l1clk		( l1clk ),
 .din  		({l2_cerr_hw0, l2_err_hw0,l2_ecc_err_type_hw0[1:0],load_ret_hw0,ret_tid_hw0[7:0],ret_tsbid_hw0[1:0],l2miss_hw0, l15_mmu_cpkt[8:6]}),
 .dout 		({l2_cerr_hw1, l2_err_hw1,l2_ecc_err_type[1:0],load_ret_hw1,ret_tid_hw1[7:0],ret_tsbid_hw1[1:0],l2miss_hw1, mmutid_hw1[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );


/////////////////////////////////////////////////////////////////////
// TSB Hit/Miss Logic (HW1)
/////////////////////////////////////////////////////////////////////
assign htd_ptr_hit_hw1 = htd_ptr_hit2_hw1 & htd_ptr_hit1_hw1 & htd_ptr_hit0_hw1;
//assign ctx_hit = htd_ignore_ctx_hw1 | htd_ctx_hit_hw1;
assign ctx_hit = (~htd_zeroctx_hw1 & (htd_usectx0_hw1 | htd_usectx1_hw1)) | htd_ctx_hit_hw1;

// an I side tablewalk can hit only if EP bit is set.
assign ep_hit = htd_dmiss_hw1 | htd_tte_ep_hw1;


assign raw_tsb_hit_hw1 = ctx_hit & htd_ptr_hit_hw1 & ep_hit;
assign raw_ep_miss_hw1 = ctx_hit & htd_ptr_hit_hw1 & ~ep_hit;

assign htc_data_rcvd_hw1[7:0] = ret_tid_hw1[7:0] & {8{load_ret_hw1}};

// qualify tsb_hit with no l2err
assign htc_tsb_hit_hw1[7:0] = (htc_data_rcvd_hw1[7:0]  & {8{raw_tsb_hit_hw1 & ~l2_err_hw1}});
assign htc_ep_miss_hw1[7:0] = (htc_data_rcvd_hw1[7:0]  & {8{raw_ep_miss_hw1 & ~l2_err_hw1}});
assign l2_ecc_err_hw1[7:0] = (htc_data_rcvd_hw1[7:0] & {8{l2_err_hw1}});


// tsb processing is done if tsb_hit, or ep_miss, or l2_err

assign tsb_done_hw1[7:0] = (htc_data_rcvd_hw1[7:0] & {8{raw_tsb_hit_hw1 | raw_ep_miss_hw1 | l2_err_hw1}});

assign d_l2_cerr[7:0] = htc_data_rcvd_hw1[7:0] & {8{l2_cerr_hw1}} & htd_dmiss_lat[7:0];
assign i_l2_cerr[7:0] = htc_data_rcvd_hw1[7:0] & {8{l2_cerr_hw1}} & ~htd_dmiss_lat[7:0];


// Form signals for pmu
assign mmu_pmu_l2ret = load_ret_hw1;
assign mmu_pmu_l2miss = l2miss_hw1;
assign mmu_pmu_dtlb = htd_dmiss_hw1;
assign mmu_pmu_tid[2:0] = mmutid_hw1[2:0];


mmu_htc_ctl_msff_ctl_macro__width_16 final_l2_cerr_lat  (
 .scan_in(final_l2_cerr_lat_scanin),
 .scan_out(final_l2_cerr_lat_scanout),
 .l1clk( l1clk ),
 .din ({i_l2_cerr[7:0], d_l2_cerr[7:0]}),
 .dout({mmu_i_l2cerr[7:0], mmu_d_l2cerr[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


mmu_htc_ctl_msff_ctl_macro__width_8 tsb_hit_lat  (
 .scan_in(tsb_hit_lat_scanin),
 .scan_out(tsb_hit_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({htc_tsb_hit_hw1[7:0]}),
 .dout 		({htc_tsb_hit_hw2[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_8 ep_miss_lat  (
 .scan_in(ep_miss_lat_scanin),
 .scan_out(ep_miss_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({htc_ep_miss_hw1[7:0]}),
 .dout 		({htc_ep_miss_hw2[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_8 tsb_done_lat  (
 .scan_in(tsb_done_lat_scanin),
 .scan_out(tsb_done_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({tsb_done_hw1[7:0]}),
 .dout 		({tsb_done_nocfg_hw2[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_8 cfg_ecc_lat  (
 .scan_in(cfg_ecc_lat_scanin),
 .scan_out(cfg_ecc_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({cfg_ecc_err_m3[7:0]}),
 .dout 		({cfg_ecc_err_m4[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign htc_tsb_done_hw2[7:0] = tsb_done_nocfg_hw2[7:0] | cfg_ecc_err_m4[7:0];


mmu_htc_ctl_msff_ctl_macro__width_2 tsbid_lat  
(
 .scan_in(tsbid_lat_scanin),
 .scan_out(tsbid_lat_scanout),
 .l1clk		( l1clk ),
 .din  		(ret_tsbid_hw1[1:0]),
 .dout 		(ret_tsbid_hw2[1:0]),
  .siclk(siclk),
  .soclk(soclk)
 );


// latch the tsb config values on a tsb hit

assign htd_ranotpa_in[0] = (trs_null_st[0] & htd_ranotpa_hw1) | (~trs_null_st[0] & htd_ranotpa[0]);
assign htd_ranotpa_in[1] = (trs_null_st[1] & htd_ranotpa_hw1) | (~trs_null_st[1] & htd_ranotpa[1]);
assign htd_ranotpa_in[2] = (trs_null_st[2] & htd_ranotpa_hw1) | (~trs_null_st[2] & htd_ranotpa[2]);
assign htd_ranotpa_in[3] = (trs_null_st[3] & htd_ranotpa_hw1) | (~trs_null_st[3] & htd_ranotpa[3]);
assign htd_ranotpa_in[4] = (trs_null_st[4] & htd_ranotpa_hw1) | (~trs_null_st[4] & htd_ranotpa[4]);
assign htd_ranotpa_in[5] = (trs_null_st[5] & htd_ranotpa_hw1) | (~trs_null_st[5] & htd_ranotpa[5]);
assign htd_ranotpa_in[6] = (trs_null_st[6] & htd_ranotpa_hw1) | (~trs_null_st[6] & htd_ranotpa[6]);
assign htd_ranotpa_in[7] = (trs_null_st[7] & htd_ranotpa_hw1) | (~trs_null_st[7] & htd_ranotpa[7]);

assign htd_zeroctx_in[0] = (trs_null_st[0] & htd_zeroctx_hw1) | (~trs_null_st[0] & htd_zeroctx[0]);
assign htd_zeroctx_in[1] = (trs_null_st[1] & htd_zeroctx_hw1) | (~trs_null_st[1] & htd_zeroctx[1]);
assign htd_zeroctx_in[2] = (trs_null_st[2] & htd_zeroctx_hw1) | (~trs_null_st[2] & htd_zeroctx[2]);
assign htd_zeroctx_in[3] = (trs_null_st[3] & htd_zeroctx_hw1) | (~trs_null_st[3] & htd_zeroctx[3]);
assign htd_zeroctx_in[4] = (trs_null_st[4] & htd_zeroctx_hw1) | (~trs_null_st[4] & htd_zeroctx[4]);
assign htd_zeroctx_in[5] = (trs_null_st[5] & htd_zeroctx_hw1) | (~trs_null_st[5] & htd_zeroctx[5]);
assign htd_zeroctx_in[6] = (trs_null_st[6] & htd_zeroctx_hw1) | (~trs_null_st[6] & htd_zeroctx[6]);
assign htd_zeroctx_in[7] = (trs_null_st[7] & htd_zeroctx_hw1) | (~trs_null_st[7] & htd_zeroctx[7]);

assign htd_usectx0_in[0] = (trs_null_st[0] & htd_usectx0_hw1) | (~trs_null_st[0] & htd_usectx0[0]);
assign htd_usectx0_in[1] = (trs_null_st[1] & htd_usectx0_hw1) | (~trs_null_st[1] & htd_usectx0[1]);
assign htd_usectx0_in[2] = (trs_null_st[2] & htd_usectx0_hw1) | (~trs_null_st[2] & htd_usectx0[2]);
assign htd_usectx0_in[3] = (trs_null_st[3] & htd_usectx0_hw1) | (~trs_null_st[3] & htd_usectx0[3]);
assign htd_usectx0_in[4] = (trs_null_st[4] & htd_usectx0_hw1) | (~trs_null_st[4] & htd_usectx0[4]);
assign htd_usectx0_in[5] = (trs_null_st[5] & htd_usectx0_hw1) | (~trs_null_st[5] & htd_usectx0[5]);
assign htd_usectx0_in[6] = (trs_null_st[6] & htd_usectx0_hw1) | (~trs_null_st[6] & htd_usectx0[6]);
assign htd_usectx0_in[7] = (trs_null_st[7] & htd_usectx0_hw1) | (~trs_null_st[7] & htd_usectx0[7]);

assign htd_usectx1_in[0] = (trs_null_st[0] & htd_usectx1_hw1) | (~trs_null_st[0] & htd_usectx1[0]);
assign htd_usectx1_in[1] = (trs_null_st[1] & htd_usectx1_hw1) | (~trs_null_st[1] & htd_usectx1[1]);
assign htd_usectx1_in[2] = (trs_null_st[2] & htd_usectx1_hw1) | (~trs_null_st[2] & htd_usectx1[2]);
assign htd_usectx1_in[3] = (trs_null_st[3] & htd_usectx1_hw1) | (~trs_null_st[3] & htd_usectx1[3]);
assign htd_usectx1_in[4] = (trs_null_st[4] & htd_usectx1_hw1) | (~trs_null_st[4] & htd_usectx1[4]);
assign htd_usectx1_in[5] = (trs_null_st[5] & htd_usectx1_hw1) | (~trs_null_st[5] & htd_usectx1[5]);
assign htd_usectx1_in[6] = (trs_null_st[6] & htd_usectx1_hw1) | (~trs_null_st[6] & htd_usectx1[6]);
assign htd_usectx1_in[7] = (trs_null_st[7] & htd_usectx1_hw1) | (~trs_null_st[7] & htd_usectx1[7]);


mmu_htc_ctl_msff_ctl_macro__width_32 tsb0_lat 
(
 .scan_in(tsb0_lat_scanin),
 .scan_out(tsb0_lat_scanout),
 .l1clk( l1clk),
 .din  ({htd_ranotpa_in[7:0], htd_zeroctx_in[7:0], htd_usectx0_in[7:0], htd_usectx1_in[7:0]}),
 .dout ({htd_ranotpa[7:0],  htd_zeroctx[7:0],  htd_usectx0[7:0],  htd_usectx1[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );


//********************************************************************************
// Real Range Register & Physical Offset Register Read (HW2)
//********************************************************************************

assign rr_index[1:0] = ({next_rrindex_bit1[0],next_rrindex_bit0[0]} & {2{trs_thrsel_hw2[0]}}) |
                         ({next_rrindex_bit1[1],next_rrindex_bit0[1]} & {2{trs_thrsel_hw2[1]}}) |
                         ({next_rrindex_bit1[2],next_rrindex_bit0[2]} & {2{trs_thrsel_hw2[2]}}) |
                         ({next_rrindex_bit1[3],next_rrindex_bit0[3]} & {2{trs_thrsel_hw2[3]}}) |
                         ({next_rrindex_bit1[4],next_rrindex_bit0[4]} & {2{trs_thrsel_hw2[4]}}) |
                         ({next_rrindex_bit1[5],next_rrindex_bit0[5]} & {2{trs_thrsel_hw2[5]}}) |
                         ({next_rrindex_bit1[6],next_rrindex_bit0[6]} & {2{trs_thrsel_hw2[6]}}) |
                         ({next_rrindex_bit1[7],next_rrindex_bit0[7]} & {2{trs_thrsel_hw2[7]}}) ;

assign thr_valid_hw2[7:0] = (trs_valid_hw2[7:0] & ~rr_done_hw3[7:0]);
assign rr_rd_en = |(thr_valid_hw2[7:0]);

assign rr_rd_thr_id[0] = trs_thrsel_hw2[1] | trs_thrsel_hw2[3] | trs_thrsel_hw2[5] | trs_thrsel_hw2[7];
assign rr_rd_thr_id[1] = trs_thrsel_hw2[2] | trs_thrsel_hw2[3] | trs_thrsel_hw2[6] | trs_thrsel_hw2[7];
assign rr_rd_thr_id[2] = trs_thrsel_hw2[4] | trs_thrsel_hw2[5] | trs_thrsel_hw2[6] | trs_thrsel_hw2[7];
assign rr_addr_in[4:0] = {rr_rd_thr_id[1:0], 1'b1, rr_index[1:0]};
// mra_rd_en = 01 for TG0, mra_rd_en=10 for TG1
assign rr_mra_rd_en[1:0] = {rr_rd_thr_id[2],~rr_rd_thr_id[2]};


//********************************************************************************
// Update TSB Predciton bits based on tsbhit_hw2 (HW2)
//********************************************************************************

// mux out the index and prediction bits saved for each thread on tsb hit
assign upd_pred_idx[5:0] = ({6{htc_tsb_hit_hw2[0]}} & pred_idx0[5:0]) |
                           ({6{htc_tsb_hit_hw2[1]}} & pred_idx1[5:0]) |
                           ({6{htc_tsb_hit_hw2[2]}} & pred_idx2[5:0]) |
                           ({6{htc_tsb_hit_hw2[3]}} & pred_idx3[5:0]) |
                           ({6{htc_tsb_hit_hw2[4]}} & pred_idx4[5:0]) |
                           ({6{htc_tsb_hit_hw2[5]}} & pred_idx5[5:0]) |
                           ({6{htc_tsb_hit_hw2[6]}} & pred_idx6[5:0]) |
                           ({6{htc_tsb_hit_hw2[7]}} & pred_idx7[5:0]);

assign htc_upd_pred_idx_hw2[5:3] = upd_pred_idx[5:3];


assign upd_pred_bit[1:0] = ({2{htc_tsb_hit_hw2[0]}} & pred_bit0[1:0]) |
                           ({2{htc_tsb_hit_hw2[1]}} & pred_bit1[1:0]) |
                           ({2{htc_tsb_hit_hw2[2]}} & pred_bit2[1:0]) |
                           ({2{htc_tsb_hit_hw2[3]}} & pred_bit3[1:0]) |
                           ({2{htc_tsb_hit_hw2[4]}} & pred_bit4[1:0]) |
                           ({2{htc_tsb_hit_hw2[5]}} & pred_bit5[1:0]) |
                           ({2{htc_tsb_hit_hw2[6]}} & pred_bit6[1:0]) |
                           ({2{htc_tsb_hit_hw2[7]}} & pred_bit7[1:0]);


// determine the config reg corresponding to tsb_hit. The return id is not
// sufficient because in case of prediction, the ID does not identify the
// tsb config reg.

// if (tsbnum[1]) {tsbnum[1:0] = tsbid[1:0]}
// else if (pred_bit[1] == 0) { tsbnum[1:0]  = tsbid[1:0] }
// else if ((pred_bit[1] == 1) && (tsbid[1:0] == 2'b00) {tsbnum[1:0] = 2'b01}
// else if ((pred_bit[1] == 1) && (tsbid[1:0] == 2'b01) {tsbnum[1:0] = 2'b00}

assign ret_tsbnum_hw2[1:0] = ({2{~upd_pred_bit[1] | ret_tsbid_hw2[1]}} & ret_tsbid_hw2[1:0]) |
                             ({2{upd_pred_bit[1] & ~ret_tsbid_hw2[1] & ~ret_tsbid_hw2[0]}} & 2'b01) |
                             ({2{upd_pred_bit[1] & ~ret_tsbid_hw2[1] &  ret_tsbid_hw2[0]}} & 2'b00);


assign inc_pred = (ret_tsbnum_hw2[1:0] == 2'b01) & (upd_pred_bit[1:0] != 2'b11);        // inc pred count if tsb hit on tsbptr1, saturate at 3
assign dec_pred = (ret_tsbnum_hw2[1:0] == 2'b00) & (upd_pred_bit[1:0] != 2'b00);        // dec pred count if tsb hit on tsbptr0, saturate at 0

assign htc_new_pred_bit[1:0] = ({2{inc_pred}} & (upd_pred_bit[1:0] + 2'b01)) |
                           ({2{dec_pred}} & (upd_pred_bit[1:0] - 2'b01)) |
                           ({2{~inc_pred & ~dec_pred}} & (upd_pred_bit[1:0]));

// create the new prediction row
assign htc_upd_grp[0] = ~upd_pred_idx[2] & ~upd_pred_idx[1] & ~upd_pred_idx[0];
assign htc_upd_grp[1] = ~upd_pred_idx[2] & ~upd_pred_idx[1] &  upd_pred_idx[0];
assign htc_upd_grp[2] = ~upd_pred_idx[2] &  upd_pred_idx[1] & ~upd_pred_idx[0];
assign htc_upd_grp[3] = ~upd_pred_idx[2] &  upd_pred_idx[1] &  upd_pred_idx[0];
assign htc_upd_grp[4] =  upd_pred_idx[2] & ~upd_pred_idx[1] & ~upd_pred_idx[0];
assign htc_upd_grp[5] =  upd_pred_idx[2] & ~upd_pred_idx[1] &  upd_pred_idx[0];
assign htc_upd_grp[6] =  upd_pred_idx[2] &  upd_pred_idx[1] & ~upd_pred_idx[0];
assign htc_upd_grp[7] =  upd_pred_idx[2] &  upd_pred_idx[1] &  upd_pred_idx[0];

assign htc_upd_grp_x[7:0] = ~htc_upd_grp[7:0];


assign pred_upd_en = |(htc_tsb_hit_hw2[7:0] & htc_hwtw_pred[7:0]);

assign htc_wrpred0_hw2 = ~upd_pred_idx[5] & ~upd_pred_idx[4] & pred_upd_en;
assign htc_wrpred1_hw2 = ~upd_pred_idx[5] &  upd_pred_idx[4] & pred_upd_en;
assign htc_wrpred2_hw2 =  upd_pred_idx[5] & ~upd_pred_idx[4] & pred_upd_en;
assign htc_wrpred3_hw2 =  upd_pred_idx[5] &  upd_pred_idx[4] & pred_upd_en;


mmu_htc_ctl_msff_ctl_macro__width_3 rr_addr_hw2_lat  
(
 .scan_in(rr_addr_hw2_lat_scanin),
 .scan_out(rr_addr_hw2_lat_scanout),
 .l1clk		( l1clk ),
 .din  		(rr_addr_in[2:0]),
 .dout 		(rr_addr_hw3[2:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_2 rr_index_hw2_lat  
(
 .scan_in(rr_index_hw2_lat_scanin),
 .scan_out(rr_index_hw2_lat_scanout),
 .l1clk		( l1clk ),
 .din  		(rr_index[1:0]),
 .dout 		(rr_index_hw3[1:0]),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_8 rr_prevalid_lat  
(
 .scan_in(rr_prevalid_lat_scanin),
 .scan_out(rr_prevalid_lat_scanout),
 .l1clk		( l1clk ),
 .din  		(thr_valid_hw2[7:0]),
 .dout 		(htc_thr_prevalid_hw3[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

/////////////////////////////////////////////////////////////////////
// MRA Access Cycle - For RR and Physical Offset(HW3)
/////////////////////////////////////////////////////////////////////
// real range valid
assign htc_thr_valid_hw3[7:0] = ({8{asi_mra_req_grant}} & htc_thr_prevalid_hw3[7:0]);
assign rr_done_hw3[7:0] = {8{rr_index_hw3[1] & rr_index_hw3[0]}} & htc_thr_valid_hw3[7:0];

assign rr_read_tg0_hw3 = |(htc_thr_valid_hw3[3:0]);
assign rr_read_tg1_hw3 = |(htc_thr_valid_hw3[7:4]);
assign htc_hw3_clken = (|(htc_thr_valid_hw3[7:0])) | ~htc_mmu_pmen;


mmu_htc_ctl_msff_ctl_macro__width_5 stg_hw3_lat  (
 .scan_in(stg_hw3_lat_scanin),
 .scan_out(stg_hw3_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({rr_read_tg0_hw3, rr_read_tg1_hw3, rr_addr_hw3[2:0]}),
 .dout 		({rr_read_tg0_hw4, rr_read_tg1_hw4, rr_addr_hw4[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// should be free running
mmu_htc_ctl_msff_ctl_macro__width_8 thr_valid_hw3_lat  (
 .scan_in(thr_valid_hw3_lat_scanin),
 .scan_out(thr_valid_hw3_lat_scanout),
 .l1clk		( l1clk ),
 .din  		({htc_thr_valid_hw3[7:0]}),
 .dout 		({htc_thr_valid_hw4[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

/////////////////////////////////////////////////////////////////////
//  Range Checking & RA --> PA (HW4)
//  Perform RA --> PA for Sun4u format
//  Check if RA is within Real Range for give thread
/////////////////////////////////////////////////////////////////////
// do not generate a ra2pahit if ep_mask=0 for I side twalk
assign ra2pahit_raw = htd_ra2pa_lower_hit_hw4 & htd_ra2pa_upper_hit_hw4 & htd_razero_hw4 & htd_range_en_hw4;

// signal ra2pahit if
// ranotpa is set
// no ecc err on mra read
// allow only one ra2pahit per thread

//0in bits_on -var {ra2pahit_thr_hw4[7:0]} -max 1

assign htc_thr_ra_valid_hw4[7:0] = htc_thr_valid_hw4[7:0] & htd_ranotpa[7:0];


assign ra2pahit_thr_hw4[7:0] = htc_thr_valid_hw4[7:0] & htd_ranotpa[7:0] & {8{ra2pahit_raw}} & 
                               ~rr_ecc_err_hw5[7:0] & ~disable_ra2pahit_st[7:0];

assign htc_ranotpax_hw4[7:0] = (~htd_ranotpa[7:0] & htc_thr_valid_hw4[7:0] & ~disable_ra2pahit_st[7:0] & ~rr_ecc_err_hw5[7:0]);

// disable ra2pahit after the first hit, or eccerr, or ~ranotpa
assign disable_ra2pahit_st_in[7:0] = (ra2pahit_thr_hw4[7:0] | htc_ranotpax_hw4[7:0] | disable_ra2pahit_st[7:0] | rr_ecc_err_hw5[7:0]) & ~trs_null_st[7:0];


assign htc_ranotpa_hw4 = |(htd_ranotpa[7:0] & htc_thr_valid_hw4[7:0]);
assign htc_zeroctx_hw4 = |(htd_zeroctx[7:0] & htc_thr_valid_hw4[7:0]);
assign htc_usectx0_hw4 = |(htd_usectx0[7:0] & htc_thr_valid_hw4[7:0]);
assign htc_usectx1_hw4 = |(htd_usectx1[7:0] & htc_thr_valid_hw4[7:0]);
assign htc_sec_ctx_hw4 = |(htd_sec_ctx[7:0] & htc_thr_valid_hw4[7:0]);
// from prm
// hwtalk ignores use_ctx0 and use_ctx1 if it is a zero context.
// If it is a non-zero context, and use_ctx_0 is 1, hw twalk writes the value of context reg 0 to tlb.
// If it is a non-zero context, and use_ctx_0 is 0, and use_ctx_1 is 1, hw twalk writes the
// value of context reg 1 to tlb.

assign htc_new_use_ctx0_hw4 = ~htc_zeroctx_hw4 & htc_usectx0_hw4;
assign htc_new_use_ctx1_hw4 = ~htc_zeroctx_hw4 & ~htc_usectx0_hw4 & htc_usectx1_hw4;


//assign rr_ecc_err = (rr_read_tg0_hw4 & mra0_ecc_err) |
//                    (rr_read_tg1_hw4 & mra1_ecc_err);

//assign rr_ecc_err_hw4[7:0] = ({8{rr_ecc_err}} & htc_thr_valid_hw4[7:0] & htd_ranotpa[7:0]);
//assign rr_ecc_err_type_hw4[1:0] = ({2{rr_read_tg0_hw4}} & mra0_err_type[1:0]) |
//                              ({2{rr_read_tg1_hw4}} & mra1_err_type[1:0]);

assign rr_ecc_err_index_hw4[2:0] = rr_addr_hw4[2:0];

assign htc_hw4_clken = (|(htc_thr_valid_hw4[7:0])) | ~htc_mmu_pmen;

// create a speculative tlb write signal for power management
// use flopped version of htd_dmiss. 
assign tlb_clken_hw4[7:0]  = ra2pahit_thr_hw4[7:0] | htc_ranotpax_hw4[7:0];
assign htc_dtlb_clken_hw4[7:0] = (tlb_clken_hw4[7:0] & htd_dmiss_lat[7:0]) | {8{~htc_mmu_pmen}};
assign htc_itlb_clken_hw4[7:0] = (tlb_clken_hw4[7:0] & ~htd_dmiss_lat[7:0]) | {8{~htc_mmu_pmen}};

mmu_htc_ctl_msff_ctl_macro__width_16 rr_ranotpax_hw4_lat  (
 .scan_in(rr_ranotpax_hw4_lat_scanin),
 .scan_out(rr_ranotpax_hw4_lat_scanout),
 .l1clk( l1clk ),
 .din  ({htc_ranotpax_hw4[7:0], htc_thr_ra_valid_hw4[7:0]}),
 .dout ({htc_ranotpax_hw5[7:0], htc_thr_ra_valid_hw5[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_8 ra2pahit_st_lat  (
 .scan_in(ra2pahit_st_lat_scanin),
 .scan_out(ra2pahit_st_lat_scanout),
 .l1clk( l1clk ),
 .din  ({disable_ra2pahit_st_in[7:0]}),
 .dout ({disable_ra2pahit_st[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_8 ra2pahit_lat  (
 .scan_in(ra2pahit_lat_scanin),
 .scan_out(ra2pahit_lat_scanout),
 .l1clk( l1clk ),
 .din  ({ra2pahit_thr_hw4[7:0]}),
 .dout ({ra2pahit_hw5[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_8 hw4_stg_lat1  
(
 .scan_in(hw4_stg_lat1_scanin),
 .scan_out(hw4_stg_lat1_scanout),
 .l1clk( l1clk ),
 .din  ({rr_read_tg0_hw4, rr_read_tg1_hw4, rr_ecc_err_index_hw4[2:0], htc_new_use_ctx0_hw4, htc_new_use_ctx1_hw4, htc_sec_ctx_hw4}),
 .dout ({rr_read_tg0_hw5, rr_read_tg1_hw5, rr_ecc_err_index[2:0], mmu_use_context_0, mmu_use_context_1, mmu_sec_context}),
  .siclk(siclk),
  .soclk(soclk)
 );

mmu_htc_ctl_msff_ctl_macro__width_16 hw4_stg_lat2  
(
 .scan_in(hw4_stg_lat2_scanin),
 .scan_out(hw4_stg_lat2_scanout),
 .l1clk( l1clk ),
 .din  ({htc_dtlb_clken_hw4[7:0],htc_itlb_clken_hw4[7:0]}),
 .dout ({htc_dtlb_clken[7:0],htc_itlb_clken[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
 );

//assign rr_ecc_err = (rr_read_tg0_hw4 & mra0_ecc_err) |
//                    (rr_read_tg1_hw4 & mra1_ecc_err);

assign rr_ecc_err_hw5[7:0] = ({8{((rr_read_tg0_hw5 & mra0_ecc_err_lat) | (rr_read_tg1_hw5 & mra1_ecc_err_lat))}} & 
                              htc_thr_ra_valid_hw5[7:0]);
assign rr_ecc_err_type[1:0] = ({2{rr_read_tg0_hw5}} & mra0_err_type_lat[1:0]) |
                              ({2{rr_read_tg1_hw5}} & mra1_err_type_lat[1:0]);

/////////////////////////////////////////////////////////////////////
// => generate tlb write enable (HW5)
// => write into I/D TLB DataIn and Tag Access Register
// => generate out of range signals, ecc err signals
/////////////////////////////////////////////////////////////////////

//0in bits_on -var {tlb_wr_en[7:0]} -max 1

assign htc_ra2pahit_hw5[7:0] = ra2pahit_hw5[7:0] & ~rr_ecc_err_hw5[7:0];

assign tlb_wr_en[7:0] = (htc_ra2pahit_hw5[7:0]) | 
                        (htc_ranotpax_hw5[7:0]);

assign htc_rd_tteq[7:0] = tlb_wr_en[7:0];


assign htc_wr_itlb_data_in[7:0] = ~htd_dmiss_lat[7:0]  & tlb_wr_en[7:0];
assign htc_wr_dtlb_data_in[7:0] =  htd_dmiss_lat[7:0]  & tlb_wr_en[7:0];

assign mmu_reload_done_din[7:0] = tlb_wr_en[7:0];


// Out of range is qualified with ranotpa  and ~ecc_err in trs.

assign i_tte_outofrange[7:0] = trs_waitrr3_st[7:0] & ~ra2pahit_hw5[7:0] & ~rr_ecc_err_hw5[7:0] & ~htd_dmiss_lat[7:0];
assign d_tte_outofrange[7:0] = trs_waitrr3_st[7:0] & ~ra2pahit_hw5[7:0] & ~rr_ecc_err_hw5[7:0] & htd_dmiss_lat[7:0];


assign final_ecc_err_hw5[7:0] = trs_ecc_err[7:0];


assign i_ecc_err[7:0] = final_ecc_err_hw5[7:0] & ~htd_dmiss_lat[7:0];
assign d_ecc_err[7:0] = final_ecc_err_hw5[7:0] &  htd_dmiss_lat[7:0];


// should be free running latch
mmu_htc_ctl_msff_ctl_macro__width_8 stg_hw5_lat  (
 .scan_in(stg_hw5_lat_scanin),
 .scan_out(stg_hw5_lat_scanout),
 .l1clk( l1clk ),
 .din  ({mmu_reload_done_din[7:0]}),
 .dout ({mmu_reload_done[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// should be free running latch
mmu_htc_ctl_msff_ctl_macro__width_16 outofrangemiss_lat  (
 .scan_in(outofrangemiss_lat_scanin),
 .scan_out(outofrangemiss_lat_scanout),
 .l1clk( l1clk ),
 .din ({i_tte_outofrange[7:0], d_tte_outofrange[7:0]}),
 .dout({mmu_i_tte_outofrange[7:0], mmu_d_tte_outofrange[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// should be free running latch
mmu_htc_ctl_msff_ctl_macro__width_16 final_ecc_err_lat  (
 .scan_in(final_ecc_err_lat_scanin),
 .scan_out(final_ecc_err_lat_scanout),
 .l1clk( l1clk ),
 .din ({i_ecc_err[7:0], d_ecc_err[7:0]}),
 .dout({mmu_i_eccerr[7:0], mmu_d_eccerr[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_24 err_type_lat  (
 .scan_in(err_type_lat_scanin),
 .scan_out(err_type_lat_scanout),
 .l1clk( l1clk),
 .din ({trs0_err_type[2:0],
        trs1_err_type[2:0],
        trs2_err_type[2:0],
        trs3_err_type[2:0],
        trs4_err_type[2:0],
        trs5_err_type[2:0],
        trs6_err_type[2:0],
        trs7_err_type[2:0]}),
 .dout({htc_thr0_err_type[2:0],
        htc_thr1_err_type[2:0],
        htc_thr2_err_type[2:0],
        htc_thr3_err_type[2:0],
        htc_thr4_err_type[2:0],
        htc_thr5_err_type[2:0],
        htc_thr6_err_type[2:0],
        htc_thr7_err_type[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_htc_ctl_msff_ctl_macro__width_24 err_index_lat  (
 .scan_in(err_index_lat_scanin),
 .scan_out(err_index_lat_scanout),
 .l1clk( l1clk),
 .din ({trs0_err_index[2:0],
        trs1_err_index[2:0],
        trs2_err_index[2:0],
        trs3_err_index[2:0],
        trs4_err_index[2:0],
        trs5_err_index[2:0],
        trs6_err_index[2:0],
        trs7_err_index[2:0]}),
 .dout({htc_thr0_err_index[2:0],
        htc_thr1_err_index[2:0],
        htc_thr2_err_index[2:0],
        htc_thr3_err_index[2:0],
        htc_thr4_err_index[2:0],
        htc_thr5_err_index[2:0],
        htc_thr6_err_index[2:0],
        htc_thr7_err_index[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// report exception due to ep miss
assign i_unauth_access[7:0] = trs_ep_err[7:0];


///////////////////////////////////////////////////////////////////////
// Signal tsb_miss in hw2
/////////////////////////////////////////////////////////////////////
assign i_tsb_miss[7:0] = tsm_tsb_miss_hw2[7:0] & ~htd_dmiss_lat[7:0] & ~htc_ep_miss_hw2[7:0];
assign d_tsb_miss[7:0] = tsm_tsb_miss_hw2[7:0] &  htd_dmiss_lat[7:0];


mmu_htc_ctl_msff_ctl_macro__width_24 tsbmiss_lat  (
 .scan_in(tsbmiss_lat_scanin),
 .scan_out(tsbmiss_lat_scanout),
 .l1clk( l1clk ),
 .din ({i_unauth_access[7:0], i_tsb_miss[7:0], d_tsb_miss[7:0]}),
 .dout({mmu_i_unauth_access[7:0], mmu_i_tsb_miss[7:0], mmu_d_tsb_miss[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


assign l15_mmu_cpkt_unused[5:0] = {l15_mmu_cpkt[2:0],l15_mmu_cpkt[5],l15_mmu_cpkt[9],l15_mmu_cpkt[12]};

////////////////////////////////////////////////////////
// SPARE CELLS
////////////////////////////////////////////////////////
mmu_htc_ctl_spare_ctl_macro__num_7 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
////////////////////////////////////////////////////////

supply0 vss;
supply1 vdd;

// fixscan start:
assign pmen_reg_scanin           = scan_in                  ;
assign tlb_miss_lat_scanin       = pmen_reg_scanout         ;
assign tlb_cerer_lat_scanin      = tlb_miss_lat_scanout     ;
assign favour_bit_reg_scanin     = tlb_cerer_lat_scanout    ;
assign ptr0_reg_scanin           = favour_bit_reg_scanout   ;
assign ptr1_reg_scanin           = ptr0_reg_scanout         ;
assign conf_idx_reg_scanin       = ptr1_reg_scanout         ;
assign rr_idx_reg_scanin         = conf_idx_reg_scanout     ;
assign m1_stg_lat_scanin         = rr_idx_reg_scanout       ;
assign conf_prevalid_lat_scanin  = m1_stg_lat_scanout       ;
assign tsbptr_lat_scanin         = conf_prevalid_lat_scanout;
assign predrow0_lat_scanin       = tsbptr_lat_scanout       ;
assign predrow1_lat_scanin       = predrow0_lat_scanout     ;
assign tlbmiss_lat_scanin        = predrow1_lat_scanout     ;
assign tlbvalidmiss_lat_scanin   = tlbmiss_lat_scanout      ;
assign pred0_lat_scanin          = tlbvalidmiss_lat_scanout ;
assign pred1_lat_scanin          = pred0_lat_scanout        ;
assign pred2_lat_scanin          = pred1_lat_scanout        ;
assign pred3_lat_scanin          = pred2_lat_scanout        ;
assign pred4_lat_scanin          = pred3_lat_scanout        ;
assign pred5_lat_scanin          = pred4_lat_scanout        ;
assign pred6_lat_scanin          = pred5_lat_scanout        ;
assign pred7_lat_scanin          = pred6_lat_scanout        ;
assign m2_stg_lat2_scanin        = pred7_lat_scanout        ;
assign m3_stg_lat1_scanin        = m2_stg_lat2_scanout      ;
assign gkt_count_reg_scanin      = m3_stg_lat1_scanout      ;
assign qv_reg_scanin             = gkt_count_reg_scanout    ;
assign q1cpkt_reg_scanin         = qv_reg_scanout           ;
assign q0cpkt_reg_scanin         = q1cpkt_reg_scanout       ;
assign cpkt_reg_scanin           = q0cpkt_reg_scanout       ;
assign gkt_hw0_lat0_scanin       = cpkt_reg_scanout         ;
assign final_l2_cerr_lat_scanin  = gkt_hw0_lat0_scanout     ;
assign tsb_hit_lat_scanin        = final_l2_cerr_lat_scanout;
assign ep_miss_lat_scanin        = tsb_hit_lat_scanout      ;
assign tsb_done_lat_scanin       = ep_miss_lat_scanout      ;
assign cfg_ecc_lat_scanin        = tsb_done_lat_scanout     ;
assign tsbid_lat_scanin          = cfg_ecc_lat_scanout      ;
assign tsb0_lat_scanin           = tsbid_lat_scanout        ;
assign rr_addr_hw2_lat_scanin    = tsb0_lat_scanout         ;
assign rr_index_hw2_lat_scanin   = rr_addr_hw2_lat_scanout  ;
assign rr_prevalid_lat_scanin    = rr_index_hw2_lat_scanout ;
assign stg_hw3_lat_scanin        = rr_prevalid_lat_scanout  ;
assign thr_valid_hw3_lat_scanin  = stg_hw3_lat_scanout      ;
assign rr_ranotpax_hw4_lat_scanin = thr_valid_hw3_lat_scanout;
assign ra2pahit_st_lat_scanin    = rr_ranotpax_hw4_lat_scanout;
assign ra2pahit_lat_scanin       = ra2pahit_st_lat_scanout  ;
assign hw4_stg_lat1_scanin       = ra2pahit_lat_scanout     ;
assign hw4_stg_lat2_scanin       = hw4_stg_lat1_scanout     ;
assign stg_hw5_lat_scanin        = hw4_stg_lat2_scanout     ;
assign outofrangemiss_lat_scanin = stg_hw5_lat_scanout      ;
assign final_ecc_err_lat_scanin  = outofrangemiss_lat_scanout;
assign err_type_lat_scanin       = final_ecc_err_lat_scanout;
assign err_index_lat_scanin      = err_type_lat_scanout     ;
assign tsbmiss_lat_scanin        = err_index_lat_scanout    ;
assign spares_scanin             = tsbmiss_lat_scanout      ;
assign scan_out                  = spares_scanout           ;

assign pid0_lat_wmr_scanin       = wmr_scan_in              ;
assign pid1_lat_wmr_scanin       = pid0_lat_wmr_scanout     ;
assign pid2_lat_wmr_scanin       = pid1_lat_wmr_scanout     ;
assign pid3_lat_wmr_scanin       = pid2_lat_wmr_scanout     ;
assign pid4_lat_wmr_scanin       = pid3_lat_wmr_scanout     ;
assign pid5_lat_wmr_scanin       = pid4_lat_wmr_scanout     ;
assign pid6_lat_wmr_scanin       = pid5_lat_wmr_scanout     ;
assign pid7_lat_wmr_scanin       = pid6_lat_wmr_scanout     ;
assign wmr_scan_out              = pid7_lat_wmr_scanout     ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_11 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [10:0] fdin;
wire [9:0] so;

  input [10:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [10:0] dout;
  output scan_out;
assign fdin[10:0] = din[10:0];


dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_22 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [21:0] fdin;
wire [20:0] so;

  input [21:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [21:0] dout;
  output scan_out;
assign fdin[21:0] = din[21:0];


dff #(22)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[21:0]),
.si({scan_in,so[20:0]}),
.so({so[20:0],scan_out}),
.q(dout[21:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_17 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [16:0] fdin;
wire [15:0] so;

  input [16:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [16:0] dout;
  output scan_out;
assign fdin[16:0] = din[16:0];


dff #(17)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[16:0]),
.si({scan_in,so[15:0]}),
.so({so[15:0],scan_out}),
.q(dout[16:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_13 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [12:0] fdin;
wire [11:0] so;

  input [12:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [12:0] dout;
  output scan_out;
assign fdin[12:0] = din[12:0];


dff #(13)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[12:0]),
.si({scan_in,so[11:0]}),
.so({so[11:0],scan_out}),
.q(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_19 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [18:0] fdin;
wire [17:0] so;

  input [18:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [18:0] dout;
  output scan_out;
assign fdin[18:0] = din[18:0];


dff #(19)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[18:0]),
.si({scan_in,so[17:0]}),
.so({so[17:0],scan_out}),
.q(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_32 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [30:0] so;

  input [31:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = din[31:0];


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htc_ctl_msff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module mmu_htc_ctl_spare_ctl_macro__num_7 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));
assign scan_out = so_6;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_htd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_htd_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_muxtest, 
  tcu_dectest, 
  scan_out, 
  htc_core_running, 
  htc_m1_clken, 
  htc_hw3_clken, 
  htc_hw4_clken, 
  asd0_tag_access, 
  asd1_tag_access, 
  htc_tsbrd_valid_m0, 
  asi_data_in_real, 
  ase_lsu_va_w, 
  lsu_context_b, 
  lsu_tlu_dsfsr_ct_b, 
  l15_spc_data1, 
  l15_mmu_cpkt, 
  l15_mmu_grant, 
  htc_zero_ctx_m2, 
  htc_ranotpa_hw4, 
  htc_pid0_m0, 
  htc_pid1_m0, 
  htc_thr_prevalid_hw3, 
  htc_va_rd_m2_in, 
  htc_l15_en, 
  htc_vld_tsbptr_m2, 
  trs_null_st, 
  htc_mra_sel_0, 
  htc_sel_mra_lo, 
  mra0_data, 
  mra1_data, 
  htc_conf_index_m2, 
  htc_upd_pred_idx_hw2, 
  htc_upd_grp, 
  htc_upd_grp_x, 
  htc_new_pred_bit, 
  htc_wrpred0_hw2, 
  htc_wrpred1_hw2, 
  htc_wrpred2_hw2, 
  htc_wrpred3_hw2, 
  htc_wr_q0new_nogrant, 
  htc_wr_q0new_grant, 
  htc_wr_q1new, 
  htc_shift_q1_grant, 
  htc_wr_m3new, 
  htc_wr_m3q0, 
  htc_rd_tteq, 
  tlu_iht_request, 
  tlu_dht_request, 
  tlu_mmu_tl_gt_0, 
  tlu_pc_0_w, 
  tlu_pc_1_w, 
  asd_i_p_ctx_0_0, 
  asd_i_p_ctx_0_1, 
  asd_i_p_ctx_0_2, 
  asd_i_p_ctx_0_3, 
  asd_i_p_ctx_0_4, 
  asd_i_p_ctx_0_5, 
  asd_i_p_ctx_0_6, 
  asd_i_p_ctx_0_7, 
  htd_range_en_hw4, 
  htd_zeroctx_hw1, 
  htd_usectx0_hw1, 
  htd_usectx1_hw1, 
  htd_ranotpa_hw1, 
  htd_ptr_hit0_hw1, 
  htd_ptr_hit1_hw1, 
  htd_ptr_hit2_hw1, 
  htd_ctx_hit_hw1, 
  htd_tte_ep_hw1, 
  htd_dmiss_hw1, 
  htd_ra2pa_lower_hit_hw4, 
  htd_ra2pa_upper_hit_hw4, 
  htd_razero_hw4, 
  htd_tagaccess_din, 
  htd_tlbdatain_din, 
  mmu_l15_addr, 
  htd_dmiss, 
  htd_sec_ctx, 
  htd_pred0_idx_m0, 
  htd_pred1_idx_m0, 
  htd_pred0_m0, 
  htd_pred1_m0, 
  htd_tsbptr, 
  htd_zeroctx_m0);
wire stop;
wire test;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire [7:0] tlu_mmu_tl_gt_0_;
wire [7:0] tlb_miss_m;
wire reg_tlbmiss_w30_scanin;
wire reg_tlbmiss_w30_scanout;
wire [7:0] va_rd_m2;
wire [7:0] tlb_miss_m0;
wire lsu_sec_ctx_w;
wire [12:0] lsu_context_w;
wire [12:0] i_context_0;
wire [12:0] i_context_1;
wire [12:0] i_context_2;
wire [12:0] i_context_3;
wire [12:0] i_context_4;
wire [12:0] i_context_5;
wire [12:0] i_context_6;
wire [12:0] i_context_7;
wire reg0_vactx_w50_scanin;
wire reg0_vactx_w50_scanout;
wire [47:13] thr0_va_ff;
wire [12:0] htd_thr0_ctx_ff;
wire reg1_vactx_w50_scanin;
wire reg1_vactx_w50_scanout;
wire [47:13] thr1_va_ff;
wire [12:0] htd_thr1_ctx_ff;
wire reg2_vactx_w50_scanin;
wire reg2_vactx_w50_scanout;
wire [47:13] thr2_va_ff;
wire [12:0] htd_thr2_ctx_ff;
wire reg3_vactx_w50_scanin;
wire reg3_vactx_w50_scanout;
wire [47:13] thr3_va_ff;
wire [12:0] htd_thr3_ctx_ff;
wire reg4_vactx_w50_scanin;
wire reg4_vactx_w50_scanout;
wire [47:13] thr4_va_ff;
wire [12:0] htd_thr4_ctx_ff;
wire reg5_vactx_w50_scanin;
wire reg5_vactx_w50_scanout;
wire [47:13] thr5_va_ff;
wire [12:0] htd_thr5_ctx_ff;
wire reg6_vactx_w50_scanin;
wire reg6_vactx_w50_scanout;
wire [47:13] thr6_va_ff;
wire [12:0] htd_thr6_ctx_ff;
wire reg7_vactx_w50_scanin;
wire reg7_vactx_w50_scanout;
wire [47:13] thr7_va_ff;
wire [12:0] htd_thr7_ctx_ff;
wire [7:0] htd_zeroctx_m0_prebuf;
wire [47:28] va0_m0;
wire [12:0] ctx0_m0;
wire [47:28] va1_m0;
wire [12:0] ctx1_m0;
wire [2:0] pid0_m0;
wire [2:0] pid1_m0;
wire prty0_5_1;
wire prty0_5_0;
wire prty0_4_1;
wire prty0_4_0;
wire prty0_3_1;
wire prty0_3_0;
wire prty0_2_1;
wire prty0_2_0;
wire prty0_1_1;
wire prty0_1_0;
wire prty0_0_1;
wire prty0_0_0;
wire prty1_5_1;
wire prty1_5_0;
wire prty1_4_1;
wire prty1_4_0;
wire prty1_3_1;
wire prty1_3_0;
wire prty1_2_1;
wire prty1_2_0;
wire prty1_1_1;
wire prty1_1_0;
wire prty1_0_1;
wire prty1_0_0;
wire [81:0] mra_data;
wire [63:0] tsb_conf;
wire reg_tsbconf_m2_w39_scanin;
wire reg_tsbconf_m2_w39_scanout;
wire [63:0] tsb_conf_m2;
wire sun4v_unused;
wire hwtwen_unused;
wire [6:0] cfg_ctlpkt_m2;
wire [6:0] thrx_cfg3_ctlpkt;
wire [6:0] thrx_cfg2_ctlpkt;
wire [6:0] thrx_cfg1_ctlpkt;
wire [6:0] thrx_cfg0_ctlpkt;
wire [6:0] thrx_cfg3_ctlpkt_in;
wire [6:0] thrx_cfg2_ctlpkt_in;
wire [6:0] thrx_cfg1_ctlpkt_in;
wire [6:0] thrx_cfg0_ctlpkt_in;
wire reg0_tsbcfg_w28_scanin;
wire reg0_tsbcfg_w28_scanout;
wire [6:0] thr0_cfg3_ctlpkt;
wire [6:0] thr0_cfg2_ctlpkt;
wire [6:0] thr0_cfg1_ctlpkt;
wire [6:0] thr0_cfg0_ctlpkt;
wire reg1_tsbcfg_w28_scanin;
wire reg1_tsbcfg_w28_scanout;
wire [6:0] thr1_cfg3_ctlpkt;
wire [6:0] thr1_cfg2_ctlpkt;
wire [6:0] thr1_cfg1_ctlpkt;
wire [6:0] thr1_cfg0_ctlpkt;
wire reg2_tsbcfg_w28_scanin;
wire reg2_tsbcfg_w28_scanout;
wire [6:0] thr2_cfg3_ctlpkt;
wire [6:0] thr2_cfg2_ctlpkt;
wire [6:0] thr2_cfg1_ctlpkt;
wire [6:0] thr2_cfg0_ctlpkt;
wire reg3_tsbcfg_w28_scanin;
wire reg3_tsbcfg_w28_scanout;
wire [6:0] thr3_cfg3_ctlpkt;
wire [6:0] thr3_cfg2_ctlpkt;
wire [6:0] thr3_cfg1_ctlpkt;
wire [6:0] thr3_cfg0_ctlpkt;
wire reg4_tsbcfg_w28_scanin;
wire reg4_tsbcfg_w28_scanout;
wire [6:0] thr4_cfg3_ctlpkt;
wire [6:0] thr4_cfg2_ctlpkt;
wire [6:0] thr4_cfg1_ctlpkt;
wire [6:0] thr4_cfg0_ctlpkt;
wire reg5_tsbcfg_w28_scanin;
wire reg5_tsbcfg_w28_scanout;
wire [6:0] thr5_cfg3_ctlpkt;
wire [6:0] thr5_cfg2_ctlpkt;
wire [6:0] thr5_cfg1_ctlpkt;
wire [6:0] thr5_cfg0_ctlpkt;
wire reg6_tsbcfg_w28_scanin;
wire reg6_tsbcfg_w28_scanout;
wire [6:0] thr6_cfg3_ctlpkt;
wire [6:0] thr6_cfg2_ctlpkt;
wire [6:0] thr6_cfg1_ctlpkt;
wire [6:0] thr6_cfg0_ctlpkt;
wire reg7_tsbcfg_w28_scanin;
wire reg7_tsbcfg_w28_scanout;
wire [6:0] thr7_cfg3_ctlpkt;
wire [6:0] thr7_cfg2_ctlpkt;
wire [6:0] thr7_cfg1_ctlpkt;
wire [6:0] thr7_cfg0_ctlpkt;
wire [47:13] htd_va_prebuf;
wire [47:13] htd_va;
wire [39:13] htd_cfg_tsbbase;
wire [6:4] htd_pgsz_m2;
wire [3:0] htd_tsbsz_m2;
wire [23:0] vpn_m2;
wire [35:0] tsbptr0;
wire [35:0] tsbptr1;
wire [35:0] htd_tsbptr_m2;
wire [39:4] l15_addr;
wire reg_q1addr_w36_scanin;
wire reg_q1addr_w36_scanout;
wire [39:4] q1_addr;
wire [39:4] q0_addr;
wire [39:4] q0_addr_in_nogrant;
wire reg_q0addr_ng_w36_scanin;
wire reg_q0addr_ng_w36_scanout;
wire [39:4] q0_addr_nogrant;
wire [39:4] q0_addr_in_grant;
wire reg_q0addr_g_w36_scanin;
wire reg_q0addr_g_w36_scanout;
wire l15_mmu_grant_lat;
wire [39:4] q0_addr_grant;
wire [39:4] mmu_l15_addr_in;
wire reg_l15addr_w36_scanin;
wire reg_l15addr_w36_scanout;
wire tcu_muxtest_rep0;
wire htd_dmiss_hw0;
wire [47:22] va_hw0;
wire [12:0] ctx_hw0;
wire reg_vpn_w40_scanin;
wire reg_vpn_w40_scanout;
wire [47:22] va_hw1;
wire [12:0] ctx_hw1;
wire tcu_muxtest_rep1;
wire [6:0] cfg3_ctlpkt_hw0;
wire [6:0] cfg2_ctlpkt_hw0;
wire [6:0] cfg1_ctlpkt_hw0;
wire [6:0] cfg0_ctlpkt_hw0;
wire reg_tsbcfg_hw1_w30_scanin;
wire reg_tsbcfg_hw1_w30_scanout;
wire [4:3] l15_mmu_cpkt_hw1;
wire [6:0] cfg3_ctlpkt_hw1;
wire [6:0] cfg2_ctlpkt_hw1;
wire [6:0] cfg1_ctlpkt_hw1;
wire [6:0] cfg0_ctlpkt_hw1;
wire tcu_muxtest_rep2;
wire [6:0] cfg_ctlpkt_hw1;
wire reg_l15vahw1_w36_scanin;
wire reg_l15vahw1_w36_scanout;
wire [63:0] htd_tte_data_hw1;
wire [63:22] htd_tte_tag_ptr_hw1;
wire reg_l15ctx_w34_scanin;
wire reg_l15ctx_w34_scanout;
wire [2:0] htd_tte_rsvd0_hw1;
wire [5:0] htd_tte_rsvd1_hw1;
wire [60:48] htd_tte_tag_ctx_hw1;
wire reg_l15data_w49_scanin;
wire reg_l15data_w49_scanout;
wire tte_data_valid;
wire [3:0] tte_pgsz_hw1;
wire [2:0] tsb_pgsz_hw1;
wire [38:0] tte_data_hw1;
wire [47:22] thrx_vpn_hw1;
wire [63:22] tte_tag_hw1;
wire [2:0] tte_rsvdx;
wire tte_rsvd;
wire [3:0] tte_pgsz_hw1_;
wire [2:2] pgsize_illegal_;
wire [2:0] pgsize_illegal;
wire pg_illegal_1_0;
wire pg_illegal_1_1;
wire pg_illegal_1_2;
wire pg_illegal_0_0;
wire pg_illegal_0_1;
wire htd_razero_hw1;
wire [38:0] minbuf_tte_data_hw1;
wire e0_tte_reg_w40_scanin;
wire e0_tte_reg_w40_scanout;
wire [39:0] thr0_tte_data_hw2;
wire e1_tte_reg_w40_scanin;
wire e1_tte_reg_w40_scanout;
wire [39:0] thr1_tte_data_hw2;
wire e2_tte_reg_w40_scanin;
wire e2_tte_reg_w40_scanout;
wire [39:0] thr2_tte_data_hw2;
wire e3_tte_reg_w40_scanin;
wire e3_tte_reg_w40_scanout;
wire [39:0] thr3_tte_data_hw2;
wire e4_tte_reg_w40_scanin;
wire e4_tte_reg_w40_scanout;
wire [39:0] thr4_tte_data_hw2;
wire e5_tte_reg_w40_scanin;
wire e5_tte_reg_w40_scanout;
wire [39:0] thr5_tte_data_hw2;
wire e6_tte_reg_w40_scanin;
wire e6_tte_reg_w40_scanout;
wire [39:0] thr6_tte_data_hw2;
wire e7_tte_reg_w40_scanin;
wire e7_tte_reg_w40_scanout;
wire [39:0] thr7_tte_data_hw2;
wire pred_row0_w32_scanin;
wire pred_row0_w32_scanout;
wire [31:0] htd_newpred_hw2;
wire [31:0] pred_row0;
wire pred_row1_w32_scanin;
wire pred_row1_w32_scanout;
wire [31:0] pred_row1;
wire pred_row2_w32_scanin;
wire pred_row2_w32_scanout;
wire [31:0] pred_row2;
wire pred_row3_w32_scanin;
wire pred_row3_w32_scanout;
wire [31:0] pred_row3;
wire [15:0] htd_pred0_m0_prebuf;
wire [15:0] htd_pred1_m0_prebuf;
wire [31:0] htd_pred_hw2;
wire [31:0] new_row;
wire [31:0] old_row;
wire [31:0] new_pred_row;
wire [39:0] tte_data_hw3;
wire [27:13] ra_mask_hw3;
wire reg_ramaskhw4_w15_scanin;
wire reg_ramaskhw4_w15_scanout;
wire [27:13] htc_ra_mask_hw4;
wire reg_ttedatahw4_w40_scanin;
wire reg_ttedatahw4_w40_scanout;
wire [39:0] tte_data_hw4;
wire reg_offsethw4_w27_scanin;
wire reg_offsethw4_w27_scanout;
wire [39:13] offset0_hw4;
wire reg_rangehw4_w55_scanin;
wire reg_rangehw4_w55_scanout;
wire [63:0] range0_hw4;
wire [39:13] ra_mask_hw4;
wire [39:13] ra_mask_hw4_;
wire [39:13] tte_lo;
wire [39:13] tte_hi;
wire ra_to_pa_upper_hit_;
wire [39:13] tte_lo_;
wire ra_to_pa_lower_hit_;
wire [39:13] rg0_hi_;
wire [39:13] rg0_lo;
wire [31:0] sum0_unused;
wire [31:0] sum1_unused;
wire cout0;
wire [39:13] pa_0_din;
wire carry0_unused;
wire sum_unused;
wire [34:8] htd_tlbdatain;
wire [38:0] htd_tlbdatain_hw4;
wire reg_tlbdatainhw5_w39_scanin;
wire reg_tlbdatainhw5_w39_scanout;
wire [38:0] htd_tlbdatain_hw5;
wire [47:0] htd_tagaccess_din_prebuf;
wire lsu_tlu_dsfsr_ct_b_1_unused;
wire [25:0] l15_spc_data1_unused;
wire l15_mmu_cpkt_unused;


input            l2clk;
input            scan_in;
input            tcu_pce_ov;               // scan signals
input		spc_aclk;
input		spc_bclk;
input		 tcu_scan_en;
input        tcu_muxtest;
input        tcu_dectest;

output           scan_out;

input [7:0]      htc_core_running;
input            htc_m1_clken;
input            htc_hw3_clken;
input            htc_hw4_clken;

// tsbptr rd interface
input [47:0]     asd0_tag_access;
input [47:0]     asd1_tag_access;
input [7:0]      htc_tsbrd_valid_m0;


input            asi_data_in_real;
input [47:13]    ase_lsu_va_w;
input [12:0]  lsu_context_b;
input [1:0]      lsu_tlu_dsfsr_ct_b;


input [127:0]  l15_spc_data1;   // 16 bytes of return data from L2
input [8:3]      l15_mmu_cpkt;    // Control part of cpx packet
input            l15_mmu_grant;

input            htc_zero_ctx_m2;
input            htc_ranotpa_hw4;

input [2:0]      htc_pid0_m0;
input [2:0]      htc_pid1_m0;


input [7:0]      htc_thr_prevalid_hw3;
input [7:0]      htc_va_rd_m2_in;


input            htc_l15_en;
input  [7:0] htc_vld_tsbptr_m2;
input  [7:0] trs_null_st;
input            htc_mra_sel_0;
input            htc_sel_mra_lo;
input [81:0]     mra0_data;
input [81:0]     mra1_data;
input [1:0]      htc_conf_index_m2;

input [5:3]      htc_upd_pred_idx_hw2;
input [7:0]      htc_upd_grp;
input [7:0]      htc_upd_grp_x;
input [1:0]      htc_new_pred_bit;


input            htc_wrpred0_hw2;
input            htc_wrpred1_hw2;
input            htc_wrpred2_hw2;
input            htc_wrpred3_hw2;


input            htc_wr_q0new_nogrant;
input            htc_wr_q0new_grant;
input            htc_wr_q1new;
input            htc_shift_q1_grant;
input            htc_wr_m3new;
input            htc_wr_m3q0;


input  [7:0] htc_rd_tteq;

input [7:0]      tlu_iht_request;
input [7:0]      tlu_dht_request;
input [7:0]      tlu_mmu_tl_gt_0;   // zero context, TL > 0
input [47:13]    tlu_pc_0_w;        // PC for instruction in TG0
input [47:13]    tlu_pc_1_w;        // PC for instruction in TG1

input [12:0]   asd_i_p_ctx_0_0;     //Context register value per thread for Imiss
input [12:0]   asd_i_p_ctx_0_1;
input [12:0]   asd_i_p_ctx_0_2;
input [12:0]   asd_i_p_ctx_0_3;
input [12:0]   asd_i_p_ctx_0_4;
input [12:0]   asd_i_p_ctx_0_5;
input [12:0]   asd_i_p_ctx_0_6;
input [12:0]   asd_i_p_ctx_0_7;


//input            htc_thr0_tte_hw1;
//input            htc_thr1_tte_hw1;
//input            htc_thr2_tte_hw1;
//input            htc_thr3_tte_hw1;
//input            htc_thr4_tte_hw1;
//input            htc_thr5_tte_hw1;
//input            htc_thr6_tte_hw1;


output           htd_range_en_hw4;
output           htd_zeroctx_hw1;
output           htd_usectx0_hw1;
output           htd_usectx1_hw1;
output           htd_ranotpa_hw1;
output           htd_ptr_hit0_hw1;
output           htd_ptr_hit1_hw1;
output           htd_ptr_hit2_hw1;
output           htd_ctx_hit_hw1;
output           htd_tte_ep_hw1;
output           htd_dmiss_hw1;


output           htd_ra2pa_lower_hit_hw4;
output           htd_ra2pa_upper_hit_hw4;
output           htd_razero_hw4;
output [47:0] htd_tagaccess_din;
output [38:0] htd_tlbdatain_din;
output [39:4] mmu_l15_addr;
output [7:0]     htd_dmiss;
output [7:0]     htd_sec_ctx;


output [5:0]     htd_pred0_idx_m0;
output [5:0]     htd_pred1_idx_m0;

output [15:0]    htd_pred0_m0;         // read to predict
output [15:0]    htd_pred1_m0;         // read to predict

 
output [39:4]    htd_tsbptr;
output [7:0]     htd_zeroctx_m0;


//output           htd_ra2pa_lower_hit_1;
//output           htd_ra2pa_upper_hit_1;
//output [039:013] htd_pa_1;
//Notes:
//1). For a particular TSB_Size, with page size =5, setting tsb_size > 11
//    needs VA greater than 48 bits and is a programming error.
//2). For page size 4, setting TSB_Size to 5 needs 49 bit VA which is an 
//    error. Check whether page-size 4 is used or reserved.
//    Niagara PRM has only four page sizes (page-size = 2 and 4 are reserved)

assign stop	= 1'b0;
// assign muxtst = tcu_muxtest;
assign test   = tcu_dectest ;

mmu_htd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0   (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);


/////////////////////////////////////////////////////////////////////
// TTE Request Queue (W)/M
// MUX the incoming TLB miss request and latch it in 8 entry queue
// For each thread
// i_context[12:0] = asd_i_p_ctx_0[12:0] & {13{~tlu_mmu_tl_gt_0}}
/////////////////////////////////////////////////////////////////////
mmu_htd_dp_inv_macro__width_8 inv_tgt_z_w8  
(
 .din (tlu_mmu_tl_gt_0[7:0]),
 .dout(tlu_mmu_tl_gt_0_[7:0])
 );

mmu_htd_dp_or_macro__ports_2__width_8 or1_w8   (
  .din0({tlu_iht_request[7:0]}),
  .din1({tlu_dht_request[7:0]}),
  .dout({tlb_miss_m[7:0]})
);

/////////////////////////////////////////////////////////////////////
// Flop inputs from LSU (B)
// => lsu VA and CTX are in B cycle, while I see tlu_dht_request in W cycle.
/////////////////////////////////////////////////////////////////////
mmu_htd_dp_msff_macro__stack_50c__width_30 reg_tlbmiss_w30   
(
 .scan_in(reg_tlbmiss_w30_scanin),
 .scan_out(reg_tlbmiss_w30_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din ({htc_va_rd_m2_in[7:0], tlb_miss_m[7:0],  lsu_tlu_dsfsr_ct_b[0], lsu_context_b[12:0]}),
 .dout ({va_rd_m2[7:0],       tlb_miss_m0[7:0], lsu_sec_ctx_w,        lsu_context_w[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
 );

                                                
mmu_htd_dp_and_macro__stack_50c__width_13 and_ictx0_w13 
(.din0(asd_i_p_ctx_0_0[12:0]),
 .din1({13{tlu_mmu_tl_gt_0_[0]}}),
 .dout(i_context_0[12:0])
 );

mmu_htd_dp_and_macro__stack_50c__width_13 and_ictx1_w13 
(.din0(asd_i_p_ctx_0_1[12:0]),
 .din1({13{tlu_mmu_tl_gt_0_[1]}}),
 .dout(i_context_1[12:0])
 );

mmu_htd_dp_and_macro__stack_50c__width_13 and_ictx2_w13 
(.din0(asd_i_p_ctx_0_2[12:0]),
 .din1({13{tlu_mmu_tl_gt_0_[2]}}),
 .dout(i_context_2[12:0])
 );

mmu_htd_dp_and_macro__stack_50c__width_13 and_ictx3_w13 
(.din0(asd_i_p_ctx_0_3[12:0]),
 .din1({13{tlu_mmu_tl_gt_0_[3]}}),
 .dout(i_context_3[12:0])
 );

mmu_htd_dp_and_macro__stack_50c__width_13 and_ictx4_w13 
(.din0(asd_i_p_ctx_0_4[12:0]),
 .din1({13{tlu_mmu_tl_gt_0_[4]}}),
 .dout(i_context_4[12:0])
 );

mmu_htd_dp_and_macro__stack_50c__width_13 and_ictx5_w13 
(.din0(asd_i_p_ctx_0_5[12:0]),
 .din1({13{tlu_mmu_tl_gt_0_[5]}}),
 .dout(i_context_5[12:0])
 );

mmu_htd_dp_and_macro__stack_50c__width_13 and_ictx6_w13 
(.din0(asd_i_p_ctx_0_6[12:0]),
 .din1({13{tlu_mmu_tl_gt_0_[6]}}),
 .dout(i_context_6[12:0])
 );

mmu_htd_dp_and_macro__stack_50c__width_13 and_ictx7_w13 
(.din0(asd_i_p_ctx_0_7[12:0]),
 .din1({13{tlu_mmu_tl_gt_0_[7]}}),
 .dout(i_context_7[12:0])
 );

// Mux ITLB/DTLB/TSBPTR read requests

mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 reg0_vactx_w50  (
    .scan_in(reg0_vactx_w50_scanin),
    .scan_out(reg0_vactx_w50_scanout),
    .clk (l2clk),
    .en  (htc_core_running[0]),
    .din0({1'b0,               1'b0,         tlu_pc_0_w[47:13],   i_context_0[12:0]}),
    .din1({lsu_sec_ctx_w,      1'b1,         ase_lsu_va_w[47:13], lsu_context_w[12:0]}),
    .din2({1'b0,               1'b0,         asd0_tag_access[47:0]}),
    .din3({htd_sec_ctx[0],     htd_dmiss[0], thr0_va_ff[47:13],   htd_thr0_ctx_ff[12:0]}), 
    .sel0({tlu_iht_request[0]}),
    .sel1({tlu_dht_request[0]}),
    .sel2({htc_tsbrd_valid_m0[0]}),
    .dout({htd_sec_ctx[0],     htd_dmiss[0], thr0_va_ff[47:13],   htd_thr0_ctx_ff[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 reg1_vactx_w50  (
    .scan_in(reg1_vactx_w50_scanin),
    .scan_out(reg1_vactx_w50_scanout),
    .clk (l2clk),
    .en  (htc_core_running[1]),
    .din0({1'b0,               1'b0,         tlu_pc_0_w[47:13],   i_context_1[12:0]}),
    .din1({lsu_sec_ctx_w,      1'b1,         ase_lsu_va_w[47:13], lsu_context_w[12:0]}),
    .din2({1'b0,               1'b0,         asd0_tag_access[47:0]}),
    .din3({htd_sec_ctx[1],     htd_dmiss[1], thr1_va_ff[47:13],   htd_thr1_ctx_ff[12:0]}), 
    .sel0({tlu_iht_request[1]}),
    .sel1({tlu_dht_request[1]}),
    .sel2({htc_tsbrd_valid_m0[1]}),
    .dout({htd_sec_ctx[1],     htd_dmiss[1], thr1_va_ff[47:13],   htd_thr1_ctx_ff[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 reg2_vactx_w50  (
    .scan_in(reg2_vactx_w50_scanin),
    .scan_out(reg2_vactx_w50_scanout),
    .clk (l2clk),
    .en  (htc_core_running[2]),
    .din0({1'b0,               1'b0,         tlu_pc_0_w[47:13],   i_context_2[12:0]}),
    .din1({lsu_sec_ctx_w,      1'b1,         ase_lsu_va_w[47:13], lsu_context_w[12:0]}),
    .din2({1'b0,               1'b0,         asd0_tag_access[47:0]}),
    .din3({htd_sec_ctx[2],     htd_dmiss[2], thr2_va_ff[47:13],   htd_thr2_ctx_ff[12:0]}), 
    .sel0({tlu_iht_request[2]}),
    .sel1({tlu_dht_request[2]}),
    .sel2({htc_tsbrd_valid_m0[2]}),
    .dout({htd_sec_ctx[2],     htd_dmiss[2], thr2_va_ff[47:13],   htd_thr2_ctx_ff[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 reg3_vactx_w50  (
    .scan_in(reg3_vactx_w50_scanin),
    .scan_out(reg3_vactx_w50_scanout),
    .clk (l2clk),
    .en  (htc_core_running[3]),
    .din0({1'b0,               1'b0,         tlu_pc_0_w[47:13],   i_context_3[12:0]}),
    .din1({lsu_sec_ctx_w,      1'b1,         ase_lsu_va_w[47:13], lsu_context_w[12:0]}),
    .din2({1'b0,               1'b0,         asd0_tag_access[47:0]}),
    .din3({htd_sec_ctx[3],     htd_dmiss[3], thr3_va_ff[47:13],   htd_thr3_ctx_ff[12:0]}), 
    .sel0({tlu_iht_request[3]}),
    .sel1({tlu_dht_request[3]}),
    .sel2({htc_tsbrd_valid_m0[3]}),
    .dout({htd_sec_ctx[3],    htd_dmiss[3],  thr3_va_ff[47:13],   htd_thr3_ctx_ff[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 reg4_vactx_w50  (
    .scan_in(reg4_vactx_w50_scanin),
    .scan_out(reg4_vactx_w50_scanout),
    .clk (l2clk),
    .en  (htc_core_running[4]),
    .din0({1'b0,               1'b0,         tlu_pc_1_w[47:13],   i_context_4[12:0]}),
    .din1({lsu_sec_ctx_w,      1'b1,         ase_lsu_va_w[47:13], lsu_context_w[12:0]}),
    .din2({1'b0,               1'b0,         asd1_tag_access[47:0]}),
    .din3({htd_sec_ctx[4],     htd_dmiss[4], thr4_va_ff[47:13],   htd_thr4_ctx_ff[12:0]}), 
    .sel0({tlu_iht_request[4]}),
    .sel1({tlu_dht_request[4]}),
    .sel2({htc_tsbrd_valid_m0[4]}),
    .dout({htd_sec_ctx[4],     htd_dmiss[4], thr4_va_ff[47:13],   htd_thr4_ctx_ff[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 reg5_vactx_w50  (
    .scan_in(reg5_vactx_w50_scanin),
    .scan_out(reg5_vactx_w50_scanout),
    .clk (l2clk),
    .en  (htc_core_running[5]),
    .din0({1'b0,               1'b0,         tlu_pc_1_w[47:13],   i_context_5[12:0]}),
    .din1({lsu_sec_ctx_w,      1'b1,         ase_lsu_va_w[47:13], lsu_context_w[12:0]}),
    .din2({1'b0,               1'b0,         asd1_tag_access[47:0]}),
    .din3({htd_sec_ctx[5],     htd_dmiss[5], thr5_va_ff[47:13],   htd_thr5_ctx_ff[12:0]}), 
    .sel0({tlu_iht_request[5]}),
    .sel1({tlu_dht_request[5]}),
    .sel2({htc_tsbrd_valid_m0[5]}),
    .dout({htd_sec_ctx[5],     htd_dmiss[5], thr5_va_ff[47:13],   htd_thr5_ctx_ff[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 reg6_vactx_w50  (
    .scan_in(reg6_vactx_w50_scanin),
    .scan_out(reg6_vactx_w50_scanout),
    .clk (l2clk),
    .en  (htc_core_running[6]),
    .din0({1'b0,               1'b0,         tlu_pc_1_w[47:13],   i_context_6[12:0]}),
    .din1({lsu_sec_ctx_w,      1'b1,         ase_lsu_va_w[47:13], lsu_context_w[12:0]}),
    .din2({1'b0,               1'b0,         asd1_tag_access[47:0]}),
    .din3({htd_sec_ctx[6],     htd_dmiss[6], thr6_va_ff[47:13],   htd_thr6_ctx_ff[12:0]}), 
    .sel0({tlu_iht_request[6]}),
    .sel1({tlu_dht_request[6]}),
    .sel2({htc_tsbrd_valid_m0[6]}),
    .dout({htd_sec_ctx[6],     htd_dmiss[6], thr6_va_ff[47:13], htd_thr6_ctx_ff[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 reg7_vactx_w50  (
    .scan_in(reg7_vactx_w50_scanin),
    .scan_out(reg7_vactx_w50_scanout),
    .clk (l2clk),
    .en  (htc_core_running[7]),
    .din0({1'b0,               1'b0,         tlu_pc_1_w[47:13],   i_context_7[12:0]}),
    .din1({lsu_sec_ctx_w,      1'b1,         ase_lsu_va_w[47:13], lsu_context_w[12:0]}),
    .din2({1'b0,               1'b0,         asd1_tag_access[47:0]}),
    .din3({htd_sec_ctx[7],     htd_dmiss[7], thr7_va_ff[47:13],   htd_thr7_ctx_ff[12:0]}), 
    .sel0({tlu_iht_request[7]}),
    .sel1({tlu_dht_request[7]}),
    .sel2({htc_tsbrd_valid_m0[7]}),
    .dout({htd_sec_ctx[7],     htd_dmiss[7], thr7_va_ff[47:13],   htd_thr7_ctx_ff[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

/////////////////////////////////////////////////////////////////////
// zero detect the contexts and send them to htc in M0
//

mmu_htd_dp_zero_macro__dcmp_12x__width_16 ctx0_zd_cmp  (
    .din({3'b0,htd_thr0_ctx_ff[12:0]}),
    .dout(htd_zeroctx_m0_prebuf[0])
); 

mmu_htd_dp_zero_macro__dcmp_12x__width_16 ctx1_zd_cmp  (
    .din({3'b0,htd_thr1_ctx_ff[12:0]}),
    .dout(htd_zeroctx_m0_prebuf[1])
); 

mmu_htd_dp_zero_macro__dcmp_12x__width_16 ctx2_zd_cmp  (
    .din({3'b0,htd_thr2_ctx_ff[12:0]}),
    .dout(htd_zeroctx_m0_prebuf[2])
); 

mmu_htd_dp_zero_macro__dcmp_12x__width_16 ctx3_zd_cmp  (
    .din({3'b0,htd_thr3_ctx_ff[12:0]}),
    .dout(htd_zeroctx_m0_prebuf[3])
); 

mmu_htd_dp_zero_macro__dcmp_12x__width_16 ctx4_zd_cmp  (
    .din({3'b0,htd_thr4_ctx_ff[12:0]}),
    .dout(htd_zeroctx_m0_prebuf[4])
); 

mmu_htd_dp_zero_macro__dcmp_12x__width_16 ctx5_zd_cmp  (
    .din({3'b0,htd_thr5_ctx_ff[12:0]}),
    .dout(htd_zeroctx_m0_prebuf[5])
); 

mmu_htd_dp_zero_macro__dcmp_12x__width_16 ctx6_zd_cmp  (
    .din({3'b0,htd_thr6_ctx_ff[12:0]}),
    .dout(htd_zeroctx_m0_prebuf[6])
); 

mmu_htd_dp_zero_macro__dcmp_12x__width_16 ctx7_zd_cmp  (
    .din({3'b0,htd_thr7_ctx_ff[12:0]}),
    .dout(htd_zeroctx_m0_prebuf[7])
); 

mmu_htd_dp_buff_macro__stack_50c__width_8 buf_ctx0_w8   (
.din({htd_zeroctx_m0_prebuf[7:0]}),
.dout({htd_zeroctx_m0[7:0]})
);

/////////////////////////////////////////////////////////////////////
// GET TSB CONFIG DATA (M0)
// FORM HASHED ADDRESS to look up HWTWK PREDICTION REGISTERS
// Addressing into the table is calculated through the following hash.  The
// column headers specify which bit of the address the column calculates.  XOR
// the contents of the columns to calculate the address bit.
// cxt[12:0] = context of the request
// pid[2:0]  = partition ID of the request
// va[47:28] = Virtual Address bits 47 to 28 of request
// addr[5]   addr[4]   addr[3]   addr[2]   addr[1]   addr[0]
// -------   -------   -------   -------   -------   -------
// cxt[5]    cxt[4]    cxt[3]    cxt[2]    cxt[1]    cxt[0]
// cxt[6]    cxt[7]    cxt[8]    cxt[9]    cxt[10]   cxt[11]
// va[29]    va[28]    pid[2]    pid[1]    pid[0]    cxt[12]
// va[30]    va[31]    va[32]    va[33]    va[34]    va[35]
// va[41]    va[40]    va[39]    va[38]    va[37]    va[36]
// va[42]    va[43]    va[44]    va[45]    va[46]    va[47]

/////////////////////////////////////////////////////////////////////
// MUX out the VA and context in M0, to form the hashed index into
// prediction array
// There could be two tlb misses coming at same time for two thread groups


mmu_htd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_33 mux_va_m00_w33      (
    .din0({thr0_va_ff[47:28],htd_thr0_ctx_ff[12:0]}), 
    .din1({thr1_va_ff[47:28],htd_thr1_ctx_ff[12:0]}), 
    .din2({thr2_va_ff[47:28],htd_thr2_ctx_ff[12:0]}), 
    .din3({thr3_va_ff[47:28],htd_thr3_ctx_ff[12:0]}), 
    .sel0(tlb_miss_m0[0]),
    .sel1(tlb_miss_m0[1]),
    .sel2(tlb_miss_m0[2]),
    .sel3(tlb_miss_m0[3]),
    .dout({va0_m0[47:28], ctx0_m0[12:0]})
);

mmu_htd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_33 mux_va_m01_w33      (
    .din0({thr4_va_ff[47:28],htd_thr4_ctx_ff[12:0]}), 
    .din1({thr5_va_ff[47:28],htd_thr5_ctx_ff[12:0]}), 
    .din2({thr6_va_ff[47:28],htd_thr6_ctx_ff[12:0]}), 
    .din3({thr7_va_ff[47:28],htd_thr7_ctx_ff[12:0]}), 
    .sel0(tlb_miss_m0[4]),
    .sel1(tlb_miss_m0[5]),
    .sel2(tlb_miss_m0[6]),
    .sel3(tlb_miss_m0[7]),
    .dout({va1_m0[47:28], ctx1_m0[12:0]})
);


assign pid0_m0[2:0] = htc_pid0_m0[2:0];
assign pid1_m0[2:0] = htc_pid1_m0[2:0];


//prty_macro  prty0_0 (width=8) (
//                                  .din    ({1'b0,va0_m0[47],va0_m0[36],va0_m0[35],1'b0,ctx0_m0[12],ctx0_m0[11],ctx0_m0[00]}),
//                                  .dout   (htd_pred0_idx_m0[0]));

//prty_macro  prty0_1 (width=8) (
//                                  .din    ({1'b0,va0_m0[46],va0_m0[37],va0_m0[34],1'b0,pid0_m0[00],ctx0_m0[10],ctx0_m0[01]}),
//                                  .dout   (htd_pred0_idx_m0[1]));

//prty_macro  prty0_2 (width=8) (
//                                  .din    ({1'b0,va0_m0[45],va0_m0[38],va0_m0[33],1'b0,pid0_m0[01],ctx0_m0[09],ctx0_m0[02]}),
//                                  .dout   (htd_pred0_idx_m0[2]));

//prty_macro  prty0_3 (width=8) (
//                                  .din    ({1'b0,va0_m0[44],va0_m0[39],va0_m0[32],1'b0,pid0_m0[02],ctx0_m0[08],ctx0_m0[03]}),
//                                  .dout   (htd_pred0_idx_m0[3]));

//prty_macro  prty0_4 (width=8) (
//                                  .din    ({1'b0,va0_m0[43],va0_m0[40],va0_m0[31],1'b0, va0_m0[28],ctx0_m0[07],ctx0_m0[04]}),
//                                  .dout   (htd_pred0_idx_m0[4]));

//prty_macro  prty0_5 (width=8) (
//                                  .din    ({1'b0,va0_m0[42],va0_m0[41],va0_m0[30],1'b0, va0_m0[29],ctx0_m0[06],ctx0_m0[05]}),
//                                  .dout   (htd_pred0_idx_m0[5]));

mmu_htd_dp_xor_macro__ports_3__stack_64c__width_12 xor0_0_w12    (
.din0 ({va0_m0[30],ctx0_m0[5],va0_m0[31],ctx0_m0[4],va0_m0[32],ctx0_m0[3],va0_m0[33],ctx0_m0[2],va0_m0[34],ctx0_m0[1],va0_m0[35],ctx0_m0[0]}),
.din1 ({va0_m0[41],ctx0_m0[6],va0_m0[40],ctx0_m0[7],va0_m0[39],ctx0_m0[8],va0_m0[38],ctx0_m0[9],va0_m0[37],ctx0_m0[10],va0_m0[36],ctx0_m0[11]}),
.din2 ({va0_m0[42],va0_m0[29], va0_m0[43],va0_m0[28] ,va0_m0[44],pid0_m0[2],va0_m0[45],pid0_m0[1],va0_m0[46],pid0_m0[0],va0_m0[47],ctx0_m0[12]}),
.dout ({prty0_5_1,prty0_5_0,prty0_4_1,prty0_4_0,prty0_3_1,prty0_3_0,prty0_2_1,prty0_2_0,prty0_1_1,prty0_1_0,prty0_0_1,prty0_0_0})
);

mmu_htd_dp_xor_macro__ports_2__stack_64c__width_6 xor0_1_w6    (
.din0 ({prty0_5_0,prty0_4_0,prty0_3_0,prty0_2_0,prty0_1_0,prty0_0_0}),
.din1 ({prty0_5_1,prty0_4_1,prty0_3_1,prty0_2_1,prty0_1_1,prty0_0_1}),
.dout ({htd_pred0_idx_m0[5:0]})
);

//prty_macro  prty1_0 (width=8) (
//                                  .din    ({1'b0,va1_m0[47],va1_m0[36],va1_m0[35],1'b0,ctx1_m0[12],ctx1_m0[11],ctx1_m0[00]}),
//                                  .dout   (htd_pred1_idx_m0[0]));

//prty_macro  prty1_1 (width=8) (
//                                  .din    ({1'b0,va1_m0[46],va1_m0[37],va1_m0[34],1'b0,pid1_m0[00],ctx1_m0[10],ctx1_m0[01]}),
//                                  .dout   (htd_pred1_idx_m0[1]));

//prty_macro  prty1_2 (width=8) (
//                                  .din    ({1'b0,va1_m0[45],va1_m0[38],va1_m0[33],1'b0,pid1_m0[01],ctx1_m0[09],ctx1_m0[02]}),
//                                  .dout   (htd_pred1_idx_m0[2]));

//prty_macro  prty1_3 (width=8) (
//                                  .din    ({1'b0,va1_m0[44],va1_m0[39],va1_m0[32],1'b0,pid1_m0[02],ctx1_m0[08],ctx1_m0[03]}),
//                                  .dout   (htd_pred1_idx_m0[3]));

//prty_macro  prty1_4 (width=8) (
//                                  .din    ({1'b0,va1_m0[43],va1_m0[40],va1_m0[31],1'b0, va1_m0[28],ctx1_m0[07],ctx1_m0[04]}),
//                                  .dout   (htd_pred1_idx_m0[4]));

//prty_macro  prty1_5 (width=8) (
//                                  .din    ({1'b0,va1_m0[42],va1_m0[41],va1_m0[30],1'b0, va1_m0[29],ctx1_m0[06],ctx1_m0[05]}),
//                                  .dout   (htd_pred1_idx_m0[5]));

mmu_htd_dp_xor_macro__ports_3__stack_64c__width_12 xor1_0_w12    (
.din0 ({va1_m0[30],ctx1_m0[5],va1_m0[31],ctx1_m0[4],va1_m0[32],ctx1_m0[3],va1_m0[33],ctx1_m0[2],va1_m0[34],ctx1_m0[1],va1_m0[35],ctx1_m0[0]}),
.din1 ({va1_m0[41],ctx1_m0[6],va1_m0[40],ctx1_m0[7],va1_m0[39],ctx1_m0[8],va1_m0[38],ctx1_m0[9],va1_m0[37],ctx1_m0[10],va1_m0[36],ctx1_m0[11]}),
.din2 ({va1_m0[42],va1_m0[29], va1_m0[43],va1_m0[28] ,va1_m0[44],pid1_m0[2],va1_m0[45],pid1_m0[1],va1_m0[46],pid1_m0[0],va1_m0[47],ctx1_m0[12]}),
.dout ({prty1_5_1,prty1_5_0,prty1_4_1,prty1_4_0,prty1_3_1,prty1_3_0,prty1_2_1,prty1_2_0,prty1_1_1,prty1_1_0,prty1_0_1,prty1_0_0})
);

mmu_htd_dp_xor_macro__ports_2__stack_64c__width_6 xor1_1_w6    (
.din0 ({prty1_5_0,prty1_4_0,prty1_3_0,prty1_2_0,prty1_1_0,prty1_0_0}),
.din1 ({prty1_5_1,prty1_4_1,prty1_3_1,prty1_2_1,prty1_1_1,prty1_0_1}),
.dout ({htd_pred1_idx_m0[5:0]})
);
                                                    

/////////////////////////////////////////////////////////////////////
// GET TSB CONFIG DATA (M1)
// MRA data is returned in M1 and HW2 
/////////////////////////////////////////////////////////////////////

// MUX out MRA data based on TG0/1, in M1/HW2
mmu_htd_dp_mux_macro__mux_pgpe__ports_2__stack_58c__width_40 mux0_mra_data_w40  (
    .din0({mra0_data[39:0]}),
    .din1({mra1_data[39:0]}),
    .sel0({htc_mra_sel_0}), //TG0
//    .sel1({htc_mra_sel[1]}), //TG1
    .dout({mra_data[39:0]})
);

// MUX out MRA data based on TG0/1 in M1/HW2
mmu_htd_dp_mux_macro__mux_pgpe__ports_2__stack_58c__width_42 mux1_mra_data_w42  (
    .din0({mra0_data[81:40]}), 
    .din1({mra1_data[81:40]}),
    .sel0({htc_mra_sel_0}), //TG0
//    .sel1({htc_mra_sel[1]}), //TG1
    .dout({mra_data[81:40]})
);


// MRA Layout

// Bit 2 of tid[2:0] selects mra1/mra0
// Bit tid[1:0] form address[4:3] of MRA_ADDR
// MRA_ADDR[2:0]   Data
//                 
// 000             unused[3:0],z_tsb_conf_0[77:39],z_tsb_conf_1[38:0]
// 001             unused[3:0],z_tsb_conf_2[77:39],z_tsb_conf_3[38:0]
// 010             unused[3:0],nz_tsb_conf_0[77:39],nz_tsb_conf_1[38:0]
// 011             unused[3:0],nz_tsb_conf_2[77:39],nz_tsb_conf_3[38:0]
// 100             RR0[81:27],PhyOff0[25:0] 
// 101             RR1[81:27],PhyOff1[25:0]
// 110             RR2[81:27],PhyOff2[25:0]
// 111             RR3[81:27],PhyOff3[25:0]

mmu_htd_dp_mux_macro__mux_pgpe__ports_2__stack_58c__width_39 mux3_mra_data_w39  (
    .din0({mra_data[38:0]}), 
    .din1({mra_data[77:39]}),
    .sel0({htc_sel_mra_lo}), 
//    .sel1({htc_sel_mra_up}),
    .dout({tsb_conf[63:61], tsb_conf[39:13], tsb_conf[8:0]})

);

// Latch data coming from MRA due to a TSB config read in M1
// latch the data on TSB ptr gen or hwtwk tsb cfg rd.

mmu_htd_dp_msff_macro__stack_58c__width_39 reg_tsbconf_m2_w39   (
    .scan_in(reg_tsbconf_m2_w39_scanin),
    .scan_out(reg_tsbconf_m2_w39_scanout),
    .clk (l2clk),
    .en  (htc_m1_clken),
    .din ({tsb_conf[63:61], tsb_conf[39:13], tsb_conf[8:0]}),
    .dout ({tsb_conf_m2[63:61], tsb_conf_m2[39:13], tsb_conf_m2[8:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign sun4v_unused = tsb_conf_m2[7];
assign hwtwen_unused = tsb_conf_m2[63];


/////////////////////////////////////////////////////////////////////
// TSB Pointer Generation (M2)
/////////////////////////////////////////////////////////////////////
//
// send these tsb config bits to htc

// control bits from tsb config registers need to be saved.
// They will be used when tte data comes back.
// Each request can have upto 4 TSB config reads, and control bits from each have to be saved.
// control bits to be saved:
// cfg_ctlpkt_m2[8]   = tsb_conf_m2[63] = hwtw_en
// cfg_ctlpkt_m2[7]   = tsb_conf_m2[62] = use_context_0
// cfg_ctlpkt_m2[6]   = tsb_conf_m2[61] = use_context_1
// cfg_ctlpkt_m2[5]   = tsb_conf_m2[8]  = ranotpa
// cfg_ctlpkt_m2[4]   = tsb_conf_m2[7]  = sun4v
// cfg_ctlpkt_m2[3:1] = tsb_conf_m2[6:4] = pgsize
// cfg_ctlpkt_m2[0]   = htc_zero_ctx_m2
// cfg_ctlpkt[8:0] = { hwtw_en, use_context_0, use_context_1, ranotpa, sun4v, pgsize[6:4],zero_ctx}
// assign cfg_ctlpkt_m2[8:0] = {tsb_conf_m2[63:61], tsb_conf_m2[8:4], htc_zero_ctx_m2};


// 03/01/05  Only 7 bits need to be saved in cfg ctl packet.
// cfg_ctlpkt_m2[3]   = tsb_conf_m2[62] = use_context_0
// cfg_ctlpkt_m2[2]   = tsb_conf_m2[61] = use_context_1
// cfg_ctlpkt_m2[1]   = tsb_conf_m2[8]  = ranotpa
// cfg_ctlpkt_m2[3:1] = tsb_conf_m2[6:4] = pgsize
// cfg_ctlpkt_m2[0]   = htc_zero_ctx_m2
// cfg_ctlpkt_m2[3:0] = { use_context_0, use_context_1, ranotpa, tsb_conf_m2[6:4], zero_ctx}
assign cfg_ctlpkt_m2[6:0] = {tsb_conf_m2[62:61], tsb_conf_m2[8], tsb_conf_m2[6:4], htc_zero_ctx_m2};


// Each thread can read upto 4 tsb pointers. The control information from these registers
// are saved in a single flop.
mmu_htd_dp_mux_macro__mux_aodec__ports_4__stack_50c__width_28 mux_tsb_ctlpkt_w28     (
    .din0({thrx_cfg3_ctlpkt[6:0], thrx_cfg2_ctlpkt[6:0], thrx_cfg1_ctlpkt[6:0], cfg_ctlpkt_m2[6:0]   }), //tsbptr = 0
    .din1({thrx_cfg3_ctlpkt[6:0], thrx_cfg2_ctlpkt[6:0], cfg_ctlpkt_m2[6:0],    thrx_cfg0_ctlpkt[6:0]}), //tsbptr = 1
    .din2({thrx_cfg3_ctlpkt[6:0], cfg_ctlpkt_m2[6:0],    thrx_cfg1_ctlpkt[6:0], thrx_cfg0_ctlpkt[6:0]}), //tsbptr = 2
    .din3({cfg_ctlpkt_m2[6:0],    thrx_cfg2_ctlpkt[6:0], thrx_cfg1_ctlpkt[6:0], thrx_cfg0_ctlpkt[6:0]}), //tsbptr = 3
    .sel(htc_conf_index_m2[1:0]),
    .dout({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]})
);

mmu_htd_dp_msff_macro__stack_50c__width_28 reg0_tsbcfg_w28   (
    .scan_in(reg0_tsbcfg_w28_scanin),
    .scan_out(reg0_tsbcfg_w28_scanout),
    .clk (l2clk),
    .en  (htc_vld_tsbptr_m2[0]),
    .din  ({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]}),
    .dout ({thr0_cfg3_ctlpkt[6:0],   thr0_cfg2_ctlpkt[6:0],   thr0_cfg1_ctlpkt[6:0],   thr0_cfg0_ctlpkt[6:0]   }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_28 reg1_tsbcfg_w28   (
    .scan_in(reg1_tsbcfg_w28_scanin),
    .scan_out(reg1_tsbcfg_w28_scanout),
    .clk (l2clk),
    .en  (htc_vld_tsbptr_m2[1]),
    .din  ({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]}),
    .dout ({thr1_cfg3_ctlpkt[6:0],   thr1_cfg2_ctlpkt[6:0],   thr1_cfg1_ctlpkt[6:0],   thr1_cfg0_ctlpkt[6:0]   }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_28 reg2_tsbcfg_w28   (
    .scan_in(reg2_tsbcfg_w28_scanin),
    .scan_out(reg2_tsbcfg_w28_scanout),
    .clk (l2clk),
    .en  (htc_vld_tsbptr_m2[2]),
    .din  ({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]}),
    .dout ({thr2_cfg3_ctlpkt[6:0],   thr2_cfg2_ctlpkt[6:0],   thr2_cfg1_ctlpkt[6:0],   thr2_cfg0_ctlpkt[6:0]   }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_28 reg3_tsbcfg_w28   (
    .scan_in(reg3_tsbcfg_w28_scanin),
    .scan_out(reg3_tsbcfg_w28_scanout),
    .clk (l2clk),
    .en  (htc_vld_tsbptr_m2[3]),
    .din  ({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]}),
    .dout ({thr3_cfg3_ctlpkt[6:0],   thr3_cfg2_ctlpkt[6:0],   thr3_cfg1_ctlpkt[6:0],   thr3_cfg0_ctlpkt[6:0]   }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_28 reg4_tsbcfg_w28   (
    .scan_in(reg4_tsbcfg_w28_scanin),
    .scan_out(reg4_tsbcfg_w28_scanout),
    .clk (l2clk),
    .en  (htc_vld_tsbptr_m2[4]),
    .din  ({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]}),
    .dout ({thr4_cfg3_ctlpkt[6:0],   thr4_cfg2_ctlpkt[6:0],   thr4_cfg1_ctlpkt[6:0],   thr4_cfg0_ctlpkt[6:0]   }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_28 reg5_tsbcfg_w28   (
    .scan_in(reg5_tsbcfg_w28_scanin),
    .scan_out(reg5_tsbcfg_w28_scanout),
    .clk (l2clk),
    .en  (htc_vld_tsbptr_m2[5]),
    .din  ({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]}),
    .dout ({thr5_cfg3_ctlpkt[6:0],   thr5_cfg2_ctlpkt[6:0],   thr5_cfg1_ctlpkt[6:0],   thr5_cfg0_ctlpkt[6:0]   }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_28 reg6_tsbcfg_w28   (
    .scan_in(reg6_tsbcfg_w28_scanin),
    .scan_out(reg6_tsbcfg_w28_scanout),
    .clk (l2clk),
    .en  (htc_vld_tsbptr_m2[6]),
    .din  ({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]}),
    .dout ({thr6_cfg3_ctlpkt[6:0],   thr6_cfg2_ctlpkt[6:0],   thr6_cfg1_ctlpkt[6:0],   thr6_cfg0_ctlpkt[6:0]   }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_28 reg7_tsbcfg_w28   (
    .scan_in(reg7_tsbcfg_w28_scanin),
    .scan_out(reg7_tsbcfg_w28_scanout),
    .clk (l2clk),
    .en  (htc_vld_tsbptr_m2[7]),
    .din  ({thrx_cfg3_ctlpkt_in[6:0],thrx_cfg2_ctlpkt_in[6:0],thrx_cfg1_ctlpkt_in[6:0],thrx_cfg0_ctlpkt_in[6:0]}),
    .dout ({thr7_cfg3_ctlpkt[6:0],   thr7_cfg2_ctlpkt[6:0],   thr7_cfg1_ctlpkt[6:0],   thr7_cfg0_ctlpkt[6:0]   }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_mux_macro__mux_aonpe__ports_8__stack_50c__width_28 mux_tsbcfg_m2_w28     (
    .din0({thr0_cfg3_ctlpkt[6:0],thr0_cfg2_ctlpkt[6:0],thr0_cfg1_ctlpkt[6:0],thr0_cfg0_ctlpkt[6:0]}), 
    .din1({thr1_cfg3_ctlpkt[6:0],thr1_cfg2_ctlpkt[6:0],thr1_cfg1_ctlpkt[6:0],thr1_cfg0_ctlpkt[6:0]}), 
    .din2({thr2_cfg3_ctlpkt[6:0],thr2_cfg2_ctlpkt[6:0],thr2_cfg1_ctlpkt[6:0],thr2_cfg0_ctlpkt[6:0]}), 
    .din3({thr3_cfg3_ctlpkt[6:0],thr3_cfg2_ctlpkt[6:0],thr3_cfg1_ctlpkt[6:0],thr3_cfg0_ctlpkt[6:0]}), 
    .din4({thr4_cfg3_ctlpkt[6:0],thr4_cfg2_ctlpkt[6:0],thr4_cfg1_ctlpkt[6:0],thr4_cfg0_ctlpkt[6:0]}), 
    .din5({thr5_cfg3_ctlpkt[6:0],thr5_cfg2_ctlpkt[6:0],thr5_cfg1_ctlpkt[6:0],thr5_cfg0_ctlpkt[6:0]}), 
    .din6({thr6_cfg3_ctlpkt[6:0],thr6_cfg2_ctlpkt[6:0],thr6_cfg1_ctlpkt[6:0],thr6_cfg0_ctlpkt[6:0]}), 
    .din7({thr7_cfg3_ctlpkt[6:0],thr7_cfg2_ctlpkt[6:0],thr7_cfg1_ctlpkt[6:0],thr7_cfg0_ctlpkt[6:0]}), 
    .sel0(htc_vld_tsbptr_m2[0]),
    .sel1(htc_vld_tsbptr_m2[1]),
    .sel2(htc_vld_tsbptr_m2[2]),
    .sel3(htc_vld_tsbptr_m2[3]),
    .sel4(htc_vld_tsbptr_m2[4]),
    .sel5(htc_vld_tsbptr_m2[5]),
    .sel6(htc_vld_tsbptr_m2[6]),
    .sel7(htc_vld_tsbptr_m2[7]),
    .dout({thrx_cfg3_ctlpkt[6:0],thrx_cfg2_ctlpkt[6:0],thrx_cfg1_ctlpkt[6:0],thrx_cfg0_ctlpkt[6:0]})
);


// MUX out the VA in M2
mmu_htd_dp_mux_macro__left_13__mux_aonpe__ports_8__stack_50c__width_35 mux_va_m2_w35      (
    .din0(thr0_va_ff[47:13]), 
    .din1(thr1_va_ff[47:13]), 
    .din2(thr2_va_ff[47:13]), 
    .din3(thr3_va_ff[47:13]), 
    .din4(thr4_va_ff[47:13]), 
    .din5(thr5_va_ff[47:13]), 
    .din6(thr6_va_ff[47:13]), 
    .din7(thr7_va_ff[47:13]), 
    .sel0(va_rd_m2[0]),
    .sel1(va_rd_m2[1]),
    .sel2(va_rd_m2[2]),
    .sel3(va_rd_m2[3]),
    .sel4(va_rd_m2[4]),
    .sel5(va_rd_m2[5]),
    .sel6(va_rd_m2[6]),
    .sel7(va_rd_m2[7]),
    .dout(htd_va_prebuf[47:13])
);

mmu_htd_dp_buff_macro__left_13__stack_50c__width_35 buf_va_m2_w35    (
.din(htd_va_prebuf[47:13]),
.dout(htd_va[47:13])
);


////////////////////////////////////////////////////////////////////////////
// TSB POINTER GENERATION IN M2
////////////////////////////////////////////////////////////////////////////
// Old scheme:
//
//                tsb0-7                                tsb8-15
//                  |                                      |
//                  |                                      |
//      ----------------------                   ----------------------
//      |      |      |      |                   |      |      |      |    
//      |      |      |      |                   |      |      |      |    
//      pg0mx  pg1mx  pg3mx  pg5mx               pg0mx  pg1mx  pg3mx  pg5mx
//      8:1    8:1    8:1    8:1                 8:1    8:1    8:1    8:1
//      |      |      |      |                   |      |      |      |    
//      |      |      |      |                   |      |      |      |    
//      ----------------------                   ----------------------
//                  |                                      |
//                  |                                      |
//                  ---------------------------------------
//                                      |
//                                     2:1
//                                      |
//                                      |
//                                    tsbptr
//
//
// New Scheme:
//                     va[36:13] va[39:16] va[45:22] va[47:28]
//                         |          |         |         |
//                         |          |         |         |
//                         -------------------------------
//                                      |
//                                     4:1
//                                     vpn[23:0]
//                                      |
//                                      |
//                                      |
//                  ---------------------------------------
//                  |                                      |
//                  |                                      |
//                  |                                      |
//                pgmx                                    pgmx
//                 8:1                                     8:1
//                  |                                      |
//                  |                                      |
//                  ---------------------------------------
//                                      |
//                                     2:1
//                                      |
//                                      |
//                                    tsbptr

// use these bits for tsb pointer generation
assign htd_cfg_tsbbase[39:13] = tsb_conf_m2[39:13];
assign htd_pgsz_m2[6:4] = tsb_conf_m2[6:4];
assign htd_tsbsz_m2[3:0] = tsb_conf_m2[3:0];


// form the virtual page number
mmu_htd_dp_mux_macro__mux_aope__ports_4__stack_50c__width_24 mux_vpn_w24     (
    .din0({4'b0000,htd_va[47:28]}), //pgsz5, 256M
    .din1({htd_va[45:22]}),         //pgsz3, 4M
    .din2({htd_va[39:16]}),         //pgsz1, 64kb
    .din3({htd_va[36:13]}),         //pgsz0, 8kb
    .sel0(htd_pgsz_m2[6]),
    .sel1(htd_pgsz_m2[5]),
    .sel2(htd_pgsz_m2[4]),
    .dout({vpn_m2[23:0]})
);

// Form TSB pointer for TSB size 0-7
mmu_htd_dp_mux_macro__mux_aodec__ports_8__stack_50c__width_36 mux_tsb0_7_w36     (
    .din0({htd_cfg_tsbbase[39:13], vpn_m2[8:0]}),   //tsb_size = 0
    .din1({htd_cfg_tsbbase[39:14], vpn_m2[9:0]}),   //tsb_size = 1
    .din2({htd_cfg_tsbbase[39:15], vpn_m2[10:0]}),   //tsb_size = 2
    .din3({htd_cfg_tsbbase[39:16], vpn_m2[11:0]}),   //tsb_size = 3
    .din4({htd_cfg_tsbbase[39:17], vpn_m2[12:0]}),   //tsb_size = 4
    .din5({htd_cfg_tsbbase[39:18], vpn_m2[13:0]}),   //tsb_size = 5
    .din6({htd_cfg_tsbbase[39:19], vpn_m2[14:0]}),   //tsb_size = 6
    .din7({htd_cfg_tsbbase[39:20], vpn_m2[15:0]}),   //tsb_size = 7
    .sel(htd_tsbsz_m2[2:0]),
    .dout({tsbptr0[35:0]})
);

// Form TSB pointer for TSB size 0-7
mmu_htd_dp_mux_macro__mux_aodec__ports_8__stack_50c__width_36 mux_tsb8_15_w36     (
    .din0({htd_cfg_tsbbase[39:21], vpn_m2[16:0]}),   //tsb_size = 8
    .din1({htd_cfg_tsbbase[39:22], vpn_m2[17:0]}),   //tsb_size = 9
    .din2({htd_cfg_tsbbase[39:23], vpn_m2[18:0]}),   //tsb_size = 10
    .din3({htd_cfg_tsbbase[39:24], vpn_m2[19:0]}),   //tsb_size = 11
    .din4({htd_cfg_tsbbase[39:25], vpn_m2[20:0]}),   //tsb_size = 12
    .din5({htd_cfg_tsbbase[39:26], vpn_m2[21:0]}),   //tsb_size = 13
    .din6({htd_cfg_tsbbase[39:27], vpn_m2[22:0]}),   //tsb_size = 14
    .din7({htd_cfg_tsbbase[39:28], vpn_m2[23:0]}),   //tsb_size = 15
    .sel(htd_tsbsz_m2[2:0]),
    .dout({tsbptr1[35:0]})
);

mmu_htd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_36 mux_tsb_w36     (
    .din0(tsbptr1[35:0]),  //tsbsz = 8 - 15
    .din1(tsbptr0[35:0]),  //tsbsz = 0 - 7
    .sel0(htd_tsbsz_m2[3]),
    .dout(htd_tsbptr_m2[35:0])
);

assign l15_addr[39:4] = htd_tsbptr_m2[35:0];
assign htd_tsbptr[39:4] = htd_tsbptr_m2[35:0];

// ********************************************************************************
// MMU-L15 Request Buffer (Size=2)
// ********************************************************************************
// ********************************************************************************
// q1
// ********************************************************************************

mmu_htd_dp_msff_macro__stack_50c__width_36 reg_q1addr_w36   (
    .scan_in(reg_q1addr_w36_scanin),
    .scan_out(reg_q1addr_w36_scanout),
    .clk (l2clk),
    .en  (htc_wr_q1new),
    .din (l15_addr[39:4]), 
    .dout ({q1_addr[39:4]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// ********************************************************************************
// q0
// to optimize use of grant, create two versions, q0_grant and q0_nogrant.
// mux between these the next cycle using flopped version of grant
// ********************************************************************************
//mux_macro mux_q0addr_w36 (width=36, ports=3, mux=aope, stack=50c) (
//    .din0(l15_addr[39:04]), 
//    .din1(q1_addr[39:04]), 
//    .din2(q0_addr[39:04]), 
//    .sel0(htc_wr_q0new),
//    .sel1(htc_shift_q1),
//    .dout(q0_addr_in[39:04])
//);
//
//msff_macro reg_q0addr_w36 (width=36, stack=50c) (
//    .scan_in(reg_q0addr_w36_scanin),
//    .scan_out(reg_q0addr_w36_scanout),
//    .clk (l2clk),
//    .en  (htc_q0_clken),
//    .din (q0_addr_in[39:04]), 
//    .dout ({q0_addr[39:04]}),
//);

mmu_htd_dp_mux_macro__mux_aope__ports_2__stack_50c__width_36 mux_q0addr_ng_w36     (
    .din0(l15_addr[39:4]), 
    .din1(q0_addr[39:4]), 
    .sel0(htc_wr_q0new_nogrant),
    .dout(q0_addr_in_nogrant[39:4])
);

mmu_htd_dp_msff_macro__stack_50c__width_36 reg_q0addr_ng_w36   (
    .scan_in(reg_q0addr_ng_w36_scanin),
    .scan_out(reg_q0addr_ng_w36_scanout),
    .clk (l2clk),
    .en  (1'b1),
    .din (q0_addr_in_nogrant[39:4]),
    .dout ({q0_addr_nogrant[39:4]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_mux_macro__mux_aope__ports_3__stack_50c__width_36 mux_q0addr_g_w36     (
    .din0(l15_addr[39:4]), 
    .din1(q1_addr[39:4]), 
    .din2(q0_addr[39:4]), 
    .sel0(htc_wr_q0new_grant),
    .sel1(htc_shift_q1_grant),
    .dout(q0_addr_in_grant[39:4])
);

mmu_htd_dp_msff_macro__stack_50c__width_37 reg_q0addr_g_w36   (
    .scan_in(reg_q0addr_g_w36_scanin),
    .scan_out(reg_q0addr_g_w36_scanout),
    .clk (l2clk),
    .en  (1'b1),
    .din ({l15_mmu_grant,q0_addr_in_grant[39:4]}), 
    .dout ({l15_mmu_grant_lat,q0_addr_grant[39:4]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_mux_macro__mux_aope__ports_2__stack_50c__width_36 mux_q0addr_w36     (
    .din0(q0_addr_grant[39:4]), 
    .din1(q0_addr_nogrant[39:4]), 
    .sel0(l15_mmu_grant_lat),
    .dout(q0_addr[39:4])
);

// ********************************************************************************
// output register M3
// ********************************************************************************

mmu_htd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_36 mux_l15addr_w36     (
    .din0(l15_addr[39:4]), 
    .din1(q0_addr[39:4]), 
    .sel0(htc_wr_m3new),
    .sel1(htc_wr_m3q0),
    .dout(mmu_l15_addr_in[39:4])
);


mmu_htd_dp_msff_macro__stack_50c__width_36 reg_l15addr_w36   (
    .scan_in(reg_l15addr_w36_scanin),
    .scan_out(reg_l15addr_w36_scanout),
    .clk (l2clk),
    .en  (htc_l15_en),
    .din ({mmu_l15_addr_in[39:4]}),
    .dout ({mmu_l15_addr[39:4]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
// PROCESS RETURN DATA
// MUX out TSB and TTE REQUEST data (HW0)
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////

mmu_htd_dp_buff_macro__dbuff_48x__rep_1__width_1 tst_mux_rep0   (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep0     ));


mmu_htd_dp_mux_macro__mux_pgdec__ports_8__stack_50c__width_40 mux_vpn_hw0_w40     (
    .din0({htd_dmiss[0], thr0_va_ff[47:22], htd_thr0_ctx_ff[12:0]}), 
    .din1({htd_dmiss[1], thr1_va_ff[47:22], htd_thr1_ctx_ff[12:0]}), 
    .din2({htd_dmiss[2], thr2_va_ff[47:22], htd_thr2_ctx_ff[12:0]}), 
    .din3({htd_dmiss[3], thr3_va_ff[47:22], htd_thr3_ctx_ff[12:0]}), 
    .din4({htd_dmiss[4], thr4_va_ff[47:22], htd_thr4_ctx_ff[12:0]}), 
    .din5({htd_dmiss[5], thr5_va_ff[47:22], htd_thr5_ctx_ff[12:0]}), 
    .din6({htd_dmiss[6], thr6_va_ff[47:22], htd_thr6_ctx_ff[12:0]}), 
    .din7({htd_dmiss[7], thr7_va_ff[47:22], htd_thr7_ctx_ff[12:0]}), 
    .muxtst (tcu_muxtest_rep0),
    .sel({l15_mmu_cpkt[8:6]}),
    .dout({htd_dmiss_hw0, va_hw0[47:22], ctx_hw0[12:0]}),
  .test(test)
);


mmu_htd_dp_msff_macro__stack_50c__width_40 reg_vpn_w40   
(
 .scan_in(reg_vpn_w40_scanin),
 .scan_out(reg_vpn_w40_scanout),
 .clk (l2clk),
 .en  (1'b1),
 .din ({htd_dmiss_hw0, va_hw0[47:22], ctx_hw0[12:0]}),
 .dout ({htd_dmiss_hw1,va_hw1[47:22], ctx_hw1[12:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
 );


mmu_htd_dp_buff_macro__dbuff_32x__rep_1__width_1 tst_mux_rep1   (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep1     ));

mmu_htd_dp_mux_macro__mux_pgdec__ports_8__stack_50c__width_28 mux_tsbcfg_hw0_w28     (
    .din0({thr0_cfg3_ctlpkt[6:0],thr0_cfg2_ctlpkt[6:0],thr0_cfg1_ctlpkt[6:0],thr0_cfg0_ctlpkt[6:0]}), 
    .din1({thr1_cfg3_ctlpkt[6:0],thr1_cfg2_ctlpkt[6:0],thr1_cfg1_ctlpkt[6:0],thr1_cfg0_ctlpkt[6:0]}), 
    .din2({thr2_cfg3_ctlpkt[6:0],thr2_cfg2_ctlpkt[6:0],thr2_cfg1_ctlpkt[6:0],thr2_cfg0_ctlpkt[6:0]}), 
    .din3({thr3_cfg3_ctlpkt[6:0],thr3_cfg2_ctlpkt[6:0],thr3_cfg1_ctlpkt[6:0],thr3_cfg0_ctlpkt[6:0]}), 
    .din4({thr4_cfg3_ctlpkt[6:0],thr4_cfg2_ctlpkt[6:0],thr4_cfg1_ctlpkt[6:0],thr4_cfg0_ctlpkt[6:0]}), 
    .din5({thr5_cfg3_ctlpkt[6:0],thr5_cfg2_ctlpkt[6:0],thr5_cfg1_ctlpkt[6:0],thr5_cfg0_ctlpkt[6:0]}), 
    .din6({thr6_cfg3_ctlpkt[6:0],thr6_cfg2_ctlpkt[6:0],thr6_cfg1_ctlpkt[6:0],thr6_cfg0_ctlpkt[6:0]}), 
    .din7({thr7_cfg3_ctlpkt[6:0],thr7_cfg2_ctlpkt[6:0],thr7_cfg1_ctlpkt[6:0],thr7_cfg0_ctlpkt[6:0]}), 
    .muxtst (tcu_muxtest_rep1),
    .sel({l15_mmu_cpkt[8:6]}),
    .dout({cfg3_ctlpkt_hw0[6:0],cfg2_ctlpkt_hw0[6:0],cfg1_ctlpkt_hw0[6:0],cfg0_ctlpkt_hw0[6:0]}),
  .test(test) 
);

mmu_htd_dp_msff_macro__stack_50c__width_30 reg_tsbcfg_hw1_w30   (
    .scan_in(reg_tsbcfg_hw1_w30_scanin),
    .scan_out(reg_tsbcfg_hw1_w30_scanout),
    .clk (l2clk),
    .en  (1'b1),
    .din  ({l15_mmu_cpkt[4:3],    cfg3_ctlpkt_hw0[6:0],cfg2_ctlpkt_hw0[6:0],cfg1_ctlpkt_hw0[6:0],cfg0_ctlpkt_hw0[6:0]}),
    .dout ({l15_mmu_cpkt_hw1[4:3],cfg3_ctlpkt_hw1[6:0],cfg2_ctlpkt_hw1[6:0],cfg1_ctlpkt_hw1[6:0],cfg0_ctlpkt_hw1[6:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


mmu_htd_dp_buff_macro__dbuff_32x__rep_1__width_1 tst_mux_rep2   (
 .din ( tcu_muxtest     ),
 .dout( tcu_muxtest_rep2     ));

// mux out the right tsb config data based on [4:3] of ret data. These bits serve as a tag.
mmu_htd_dp_mux_macro__mux_pgdec__ports_4__stack_50c__width_7 mux_tsbcfg_hw1_w7     (
    .din0({cfg0_ctlpkt_hw1[6:0]}),
    .din1({cfg1_ctlpkt_hw1[6:0]}),
    .din2({cfg2_ctlpkt_hw1[6:0]}),
    .din3({cfg3_ctlpkt_hw1[6:0]}),
    .muxtst (tcu_muxtest_rep2),
    .sel({l15_mmu_cpkt_hw1[4:3]}),
    .dout({cfg_ctlpkt_hw1[6:0]}),
  .test(test) 
);


// cfg_ctlpkt[6:0] = { use_context_0, use_context_1, ranotpa, pgsize[6:4],zero_ctx}

/////////////////////////////////////////////////////////////////////
// Staging Flops for data input from L15 (HW1) and for va
// L15 return data format
// l15_spc_data[63:0] = htd_tte_data_hw1[63:0]         
// l15_spc_data[89:64] = htd_tte_tag_ptr_hw1[47:22]    (VA[47:22])
// l15_spc_data[105:90] = htd_tte_tag_ptr_hw1[63:48]   (VA[63:48])
// l15_spc_data[111:106] = htd_tte_rsvd1_hw1[5:0]      (RSVD1[5:0])
// l15_spc_data[124:112] = htd_tte_tag_ctx_hw1[60:48]  (CONTEXT)
// l15_spc_data[127:125] = htd_tte_rsvd0_hw1[2:0]      (RSVD0[2:0])
/////////////////////////////////////////////////////////////////////
mmu_htd_dp_msff_macro__stack_50c__width_36 reg_l15vahw1_w36   (
    .scan_in(reg_l15vahw1_w36_scanin),
    .scan_out(reg_l15vahw1_w36_scanout),
    .clk (l2clk),
    .en  (1'b1),
    .din ({l15_spc_data1[3:0],    l15_spc_data1[105:90],       l15_spc_data1[79:64]}),  
    .dout({htd_tte_data_hw1[3:0], htd_tte_tag_ptr_hw1[63:48], htd_tte_tag_ptr_hw1[37:22]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)

);


mmu_htd_dp_msff_macro__stack_50c__width_34 reg_l15ctx_w34   (
    .scan_in(reg_l15ctx_w34_scanin),
    .scan_out(reg_l15ctx_w34_scanout),
    .clk (l2clk),
    .en  (1'b1),
    .din ( {l15_spc_data1[127:125], l15_spc_data1[111:106], l15_spc_data1[63:62]   , l15_spc_data1[124:112]    , l15_spc_data1[89:80]      }),  
    .dout ({htd_tte_rsvd0_hw1[2:0], htd_tte_rsvd1_hw1[5:0], htd_tte_data_hw1[63:62], htd_tte_tag_ctx_hw1[60:48], htd_tte_tag_ptr_hw1[47:38]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)

);

mmu_htd_dp_msff_macro__stack_50c__width_49 reg_l15data_w49   (
    .scan_in(reg_l15data_w49_scanin),
    .scan_out(reg_l15data_w49_scanout),
    .clk (l2clk),
    .en  (1'b1),
    .din  ({l15_spc_data1[12:10],    l15_spc_data1[55:13],    l15_spc_data1[8:6]    }),
    .dout ({htd_tte_data_hw1[12:10], htd_tte_data_hw1[55:13], htd_tte_data_hw1[8:6] }),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


assign tte_data_valid = htd_tte_data_hw1[63];
assign tte_pgsz_hw1[3:0] = htd_tte_data_hw1[3:0];
assign htd_tte_ep_hw1 = htd_tte_data_hw1[7];
//assign sun4v_format_hw1 = cfg_ctlpkt_hw1[4];
assign htd_zeroctx_hw1 = cfg_ctlpkt_hw1[0];
assign tsb_pgsz_hw1[2:0] = cfg_ctlpkt_hw1[3:1];
assign htd_ranotpa_hw1 = cfg_ctlpkt_hw1[4];
assign htd_usectx1_hw1 = cfg_ctlpkt_hw1[5];
assign htd_usectx0_hw1 = cfg_ctlpkt_hw1[6];


// assign htd_hwtwen_hw1 = cfg_ctlpkt_hw1[8];
//assign htd_hwtwen_hw1_unused[1:0] = {cfg_ctlpkt_hw1[8],cfg_ctlpkt_hw1[4]};

//****************************************************
// 101904:
// NIAGARA2 WILL NOT SUPPORT SUN4U FORMAT
// REMOVING THE TTE MUX
//****************************************************

// MUX tte data based on sun4u/sun4v formats
//mux_macro mux_tte_hw1_w39 (width=39,ports=2,mux=aope,stack=58c) (
//                                                                            //Sun4V Format
//    .din0   ({htd_tte_data_hw1       [63   ],    // V                           
//              htd_tte_data_hw1       [62   ],    // NFO
//              asi_data_in_real         ,         // Real
//              htd_tte_data_hw1       [61   ],    // Locked
//              htd_tte_data_hw1       [39:13],    // RA[39:13]
//              htd_tte_data_hw1       [12   ],    // IE
//              htd_tte_data_hw1       [11   ],    // Side effect
//              htd_tte_data_hw1       [10   ],    // CP
//              htd_tte_data_hw1       [08   ],    // P
//              htd_tte_data_hw1       [06   ],    // W
//              htd_tte_data_hw1       [03:00   ]}),  //Size[3:0]   
//                                                                            //Sun4u Format
//    .din1   ({htd_tte_data_hw1       [63   ],    // V
//              htd_tte_data_hw1       [60   ],    // NFO
//              asi_data_in_real         ,         // Real
//              htd_tte_data_hw1       [06   ],    // Locked
//              htd_tte_data_hw1       [39:13],    // PA[39:13]
//              htd_tte_data_hw1       [59   ],    // IE
//              htd_tte_data_hw1       [03   ],    // Side-effect
//              htd_tte_data_hw1       [05   ],    // CP
//              htd_tte_data_hw1       [02   ],    // P
//              htd_tte_data_hw1       [01   ],    // Writable
//              htd_tte_data_hw1       [48   ],    // Size[2]
//              htd_tte_data_hw1       [62:61   ]}),    // Size[1:0]
//    .sel0   ({sun4v_format_hw1}),
//    .dout   ({tte_data_hw1          [38   ],    // V
//              tte_data_hw1          [37   ],    // NFO
//              tte_data_hw1          [36   ],    // Real
//              tte_data_hw1          [35   ],    // Locked
//              tte_data_hw1          [34:08],    // RA/PA[39:13]
//              tte_data_hw1          [07   ],    // IE
//              tte_data_hw1          [06   ],    // Side Effect
//              tte_data_hw1          [05   ],    // CP
//              tte_data_hw1          [04   ],    // P
//              tte_data_hw1          [03   ],    // W
//              tte_data_hw1          [02:00]    // Size[2:0]
//            })
//);

assign tte_data_hw1[38:0] = (
                            {htd_tte_data_hw1       [63   ],    // [38]   V                           
                             htd_tte_data_hw1       [62   ],    // [37]   NFO
                             asi_data_in_real              ,    // [36]   Real
                             1'b0                          ,    // [35]   Locked
                             htd_tte_data_hw1       [39:13],    // [34:8] RA[39:13]
                             htd_tte_data_hw1       [12   ],    // [7]    IE
                             htd_tte_data_hw1       [11   ],    // [6]    Side effect
                             htd_tte_data_hw1       [10   ],    // [5]    CP
                             htd_tte_data_hw1       [8   ],    // [4]    P
                             htd_tte_data_hw1       [6   ],    // [3]    W
                             htd_tte_data_hw1       [2:0   ]} // [2:0]  Size[2:0] // pass only 3 bits of page size
                                                                //                  // bit 3 is always 0
                             );

                                                  
/////////////////////////////////////////////////////////////////////
// TSB hit/miss (HW1)
/////////////////////////////////////////////////////////////////////
// MUX out compare data from TTE Request and TTE Return queues

// TAG compare
// Minimum tsb page size is 8k, so bits 12:0 are offset into page.
// Minimum tsb size is 512 bytes, so next 9 bits of va need not be compared.
// So bits 21:0 of VA need not be used for tag compare.
// Any bits above bit 21 which are part of page offset should not be used for tag compare.

// For pgsz=8k, 12:0 page offset,  use 63:22 for tag compare
// For pgsz=64k, 15:0 page offset, use 63:22 for tag compare
// For pgsz=4M, 21:0 page offset,  use 63:22 for tag compare
// For pgsz=256M, 27:0 page offset, use 63:28 for tag compare 


mmu_htd_dp_mux_macro__mux_aope__ports_2__stack_50c__width_32 mux1_vpn_hw1_w32     (
    .din0({va_hw1[37:28], 6'b000000   , htd_tte_tag_ptr_hw1[37:28], 6'b000000	}),	     //pgsz5, 256Mb
    .din1({va_hw1[37:22]			  , htd_tte_tag_ptr_hw1[37:22]				}),      //pgsz0-8kb, pgsz1-64k, pgsz3-4M
    .sel0(tte_data_hw1[2]), 
    .dout({thrx_vpn_hw1[37:22], tte_tag_hw1[37:22]})
);


assign thrx_vpn_hw1[47:38] = va_hw1[47:38];
assign tte_tag_hw1[63:38] = htd_tte_tag_ptr_hw1[63:38];


mmu_htd_dp_cmp_macro__dcmp_8x__width_16 ptr_cmp0  (
    .din1({tte_tag_hw1[37:22]}),
    .din0({thrx_vpn_hw1[37:22]}),
    .dout(htd_ptr_hit0_hw1)
); 

// compare the context
mmu_htd_dp_cmp_macro__dcmp_8x__width_16 ctx_cmp  (
    .din1({3'b0, htd_tte_tag_ctx_hw1[60:48]}),
    .din0({3'b0, ctx_hw1[12:0]}),
    .dout(htd_ctx_hit_hw1)
);

// The reserved bits in tte tag should be all zero
// (|({htd_tte_rsvd0_hw1[2:0], htd_tte_rsvd1_hw1[5:0]})) = 0

mmu_htd_dp_nor_macro__ports_3__width_3 rsvd_nor1   (
    .din0 (htd_tte_rsvd0_hw1[2:0]),
    .din1 (htd_tte_rsvd1_hw1[2:0]),
    .din2 (htd_tte_rsvd1_hw1[5:3]),
    .dout (tte_rsvdx[2:0])
);

mmu_htd_dp_nand_macro__ports_3__width_1 rsvd_nand1   (
    .din0 (tte_rsvdx[0]),
    .din1 (tte_rsvdx[1]),
    .din2 (tte_rsvdx[2]),
    .dout (tte_rsvd)
);

// tte pagesize should be legal (0000, 0001, 0011 or 0101)
// Also tsbsize should be less than the tte size
// If these two conditions are not satisfied, then we consider it to be a illegal page size and
// treat it as a TSB MISS.
//

// Truth table for illegal page size
// # 
// # to run /home/rg131678/bin/espresso -Dso -oeqntott legalpage.pla
// #
// .i 7
// .o 1
// .ilb tsb2 tsb1 tsb0 tte3 tte2 tte1 tte0
// .olb illglpgsz
// .p 0
// .type fd
// 
// - - - 1 - - -  1
// 
// - - - 0 0 1 0  1
// - - - 0 1 0 0  1
// - - - 0 1 1 0  1
// - - - 0 1 1 1  1
// 0 0 1 0 0 0 0  1
// 
// 0 1 0 0 0 0 0  -
// 0 1 0 0 0 0 1  -
//        
// 0 1 1 0 0 0 0  1
// 0 1 1 0 0 0 1  1
// 
// 1 0 0 0 0 0 0  -
// 1 0 0 0 0 0 1  -
// 1 0 0 0 0 1 1  -
// 1 0 0 0 1 0 1  -
//        
// 1 0 1 0 0 0 0  1
// 1 0 1 0 0 0 1  1
// 1 0 1 0 0 1 1  1
//        
// 1 1 0 0 0 0 0  -
// 1 1 0 0 0 0 1  -
// 1 1 0 0 0 1 1  -
// 1 1 0 0 1 0 1  -
//        
// 1 1 1 0 0 0 0  - 
// 1 1 1 0 0 0 1  -
// 1 1 1 0 0 1 1  -
// 1 1 1 0 1 0 1  -
//
//
// .olb illglpgsz
// v7.0 = (tsb1&!tte2&!tte1) | (tsb2&!tte2) | (tsb0&!tte0) | (tte2&tte1) | (
//     tte2&!tte0) | (tte1&!tte0) | (tte3);
//
//
// reduce this to 3 OR terms
// pgsize_illegal[2] = tsb1&!tte2&!tte1
// pgsize_illegal[1] = (tsb2&!tte2) | (tsb0&!tte0) | (tte2&tte1)
// pgsize_illegal[0] = (tte2&!tte0) | (tte1&!tte0) | (tte3)

// illegal page size = pgsize_illegal[2] | pgsize_illegal[1] | pgsize_illegal[0]


mmu_htd_dp_inv_macro__width_4 pgsz_inv1  (
    .din ({tte_pgsz_hw1[3:0]}),
    .dout (tte_pgsz_hw1_[3:0])
);
                              
mmu_htd_dp_nand_macro__ports_3__width_1 pgsz_nand1   (
    .din0 (tte_pgsz_hw1_[2]),
    .din1 (tte_pgsz_hw1_[1]),
    .din2 (tsb_pgsz_hw1[1]),
    .dout (pgsize_illegal_[2])
);

mmu_htd_dp_inv_macro__width_1 pgsz_inv2  (
    .din ({pgsize_illegal_[2]}),
    .dout (pgsize_illegal[2])
);
mmu_htd_dp_nand_macro__ports_2__width_5 pgsz_nand2   (
    .din0 ({tte_pgsz_hw1_[2], tte_pgsz_hw1_[0], tte_pgsz_hw1[2], tte_pgsz_hw1_[0],  tte_pgsz_hw1_[0]}),
    .din1 ({tsb_pgsz_hw1[2],  tsb_pgsz_hw1[0],  tte_pgsz_hw1[1], tte_pgsz_hw1[2],   tte_pgsz_hw1[1]}),
    .dout ({pg_illegal_1_0, pg_illegal_1_1, pg_illegal_1_2, pg_illegal_0_0, pg_illegal_0_1})
);

mmu_htd_dp_nand_macro__ports_3__width_2 pgsz_nand3   (
    .din0 ({pg_illegal_1_0, pg_illegal_0_0}),
    .din1 ({pg_illegal_1_1, pg_illegal_0_1}),
    .din2 ({pg_illegal_1_2, tte_pgsz_hw1_[3]}),
    .dout ({pgsize_illegal[1], pgsize_illegal[0]})
);

                              
//compare tag 
// tte entry should be valid.
// pgsize should be legal
mmu_htd_dp_cmp_macro__dcmp_8x__width_16 ptr_cmp1  (
    .din1({pgsize_illegal[2:0], 1'b0, tte_rsvd, tte_data_valid, tte_tag_hw1[47:38]  }),
    .din0({3'b000,              1'b0, 1'b0,     1'b1,           thrx_vpn_hw1[47:38] }),
    .dout(htd_ptr_hit1_hw1)
); 

// On Niagara2, virtual address VA[63:0] is assumed to be sign extended VA[47:0]. So bit 47 of TTE tag needs to
// match 63:48 of VA.
mmu_htd_dp_cmp_macro__dcmp_8x__width_16 ptr_cmp2  (
    .din1({tte_tag_hw1[63:48] }),
    .din0({16{tte_tag_hw1[47]}}),
    .dout(htd_ptr_hit2_hw1)
); 


// On Niagara2, bits 55:40 of RA should be 0 (when the tte entry holds RA and not PA).
// If the bits are not 0, then a the OutOfRange error will be signalled (again only for RA and not PA)
mmu_htd_dp_zero_macro__dcmp_12x__width_16 ra_zero   (
    .din({htd_tte_data_hw1[55:40] }),
    .dout(htd_razero_hw1)
); 
                                         

/////////////////////////////////////////////////////////////////////
// TTE RETURN QUEUE (HW2)
// Queue it only if TSB hit
// Holding Registers for TTE Data per thread (HW2)
/////////////////////////////////////////////////////////////////////
// insert buffer for mintime fix on tte_data_hw1
mmu_htd_dp_buff_macro__minbuff_1__stack_50c__width_39 minbuf_tte_data_w39    (
.din (tte_data_hw1[38:0]),
.dout (minbuf_tte_data_hw1[38:0])                                                          
);

                                                          
mmu_htd_dp_msff_macro__stack_50c__width_40 e0_tte_reg_w40   (
    .scan_in(e0_tte_reg_w40_scanin),
    .scan_out(e0_tte_reg_w40_scanout),
    .clk (l2clk),
    .en  (trs_null_st[0]),
    .din  ({htd_razero_hw1,minbuf_tte_data_hw1[38:0]}),
    .dout ({thr0_tte_data_hw2[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_40 e1_tte_reg_w40   (
    .scan_in(e1_tte_reg_w40_scanin),
    .scan_out(e1_tte_reg_w40_scanout),
    .clk (l2clk),
    .en  (trs_null_st[1]),
    .din  ({htd_razero_hw1,minbuf_tte_data_hw1[38:0]}),
    .dout ({thr1_tte_data_hw2[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_40 e2_tte_reg_w40   (
    .scan_in(e2_tte_reg_w40_scanin),
    .scan_out(e2_tte_reg_w40_scanout),
    .clk (l2clk),
    .en  (trs_null_st[2]),
    .din  ({htd_razero_hw1,minbuf_tte_data_hw1[38:0]}),
    .dout ({thr2_tte_data_hw2[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_40 e3_tte_reg_w40   (
    .scan_in(e3_tte_reg_w40_scanin),
    .scan_out(e3_tte_reg_w40_scanout),
    .clk (l2clk),
    .en  (trs_null_st[3]),
    .din  ({htd_razero_hw1,minbuf_tte_data_hw1[38:0]}),
    .dout ({thr3_tte_data_hw2[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_40 e4_tte_reg_w40   (
    .scan_in(e4_tte_reg_w40_scanin),
    .scan_out(e4_tte_reg_w40_scanout),
    .clk (l2clk),
    .en  (trs_null_st[4]),
    .din  ({htd_razero_hw1,minbuf_tte_data_hw1[38:0]}),
    .dout ({thr4_tte_data_hw2[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_40 e5_tte_reg_w40   (
    .scan_in(e5_tte_reg_w40_scanin),
    .scan_out(e5_tte_reg_w40_scanout),
    .clk (l2clk),
    .en  (trs_null_st[5]),
    .din  ({htd_razero_hw1,minbuf_tte_data_hw1[38:0]}),
    .dout ({thr5_tte_data_hw2[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_40 e6_tte_reg_w40   (
    .scan_in(e6_tte_reg_w40_scanin),
    .scan_out(e6_tte_reg_w40_scanout),
    .clk (l2clk),
    .en  (trs_null_st[6]),
    .din  ({htd_razero_hw1,minbuf_tte_data_hw1[38:0]}),
    .dout ({thr6_tte_data_hw2[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_40 e7_tte_reg_w40   (
    .scan_in(e7_tte_reg_w40_scanin),
    .scan_out(e7_tte_reg_w40_scanout),
    .clk (l2clk),
    .en  (trs_null_st[7]),
    .din  ({htd_razero_hw1,minbuf_tte_data_hw1[38:0]}),
    .dout ({thr7_tte_data_hw2[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// cfg_ctlpkt[8:0] = { hwtw_en, use_context_0, use_context_1, ranotpa, sun4v, pgsize[6:4],zero_ctx}

//assign htd_ranotpa[7:0] = {thr7_cfg_pkt_hw2[5],thr6_cfg_pkt_hw2[5],thr5_cfg_pkt_hw2[5],thr4_cfg_pkt_hw2[5],
//                           thr3_cfg_pkt_hw2[5],thr2_cfg_pkt_hw2[5],thr1_cfg_pkt_hw2[5],thr0_cfg_pkt_hw2[5]};
//assign htd_zeroctx[7:0] = {thr7_cfg_pkt_hw2[0],thr6_cfg_pkt_hw2[0],thr5_cfg_pkt_hw2[0],thr4_cfg_pkt_hw2[0],
//                           thr3_cfg_pkt_hw2[0],thr2_cfg_pkt_hw2[0],thr1_cfg_pkt_hw2[0],thr0_cfg_pkt_hw2[0]};
//assign htd_usectx0[7:0] = {thr7_cfg_pkt_hw2[7],thr6_cfg_pkt_hw2[7],thr5_cfg_pkt_hw2[7],thr4_cfg_pkt_hw2[7],
//                           thr3_cfg_pkt_hw2[7],thr2_cfg_pkt_hw2[7],thr1_cfg_pkt_hw2[7],thr0_cfg_pkt_hw2[7]};
//assign htd_usectx1[7:0] = {thr7_cfg_pkt_hw2[6],thr6_cfg_pkt_hw2[6],thr5_cfg_pkt_hw2[6],thr4_cfg_pkt_hw2[6],
//                           thr3_cfg_pkt_hw2[6],thr2_cfg_pkt_hw2[6],thr1_cfg_pkt_hw2[6],thr0_cfg_pkt_hw2[6]};

/////////////////////////////////////////////////////////////////////
// Update TSB prediction array on a tsb hit in hw2
// Prediction array consists of 64 entries of 2 bits each, accessed
// by 6 bit prediction index pred_idx[5:0].
// This array is organized as 4 registers, each of 32 bits.
// pred_idx[5:4] select one of the 4 registers, and pred_idx[3:0] select
// 2 bits out of the selected 32 bit.
// Prediction array is read and written in hw2 for updates.
// Prediction array is read in M1 to predict tsb access.
/////////////////////////////////////////////////////////////////////
mmu_htd_dp_msff_macro__stack_50c__width_32 pred_row0_w32   
(
 .scan_in(pred_row0_w32_scanin),
 .scan_out(pred_row0_w32_scanout),
 .clk (l2clk),
 .en  (htc_wrpred0_hw2),
 .din (htd_newpred_hw2[31:0]),
 .dout (pred_row0[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_32 pred_row1_w32   
(
 .scan_in(pred_row1_w32_scanin),
 .scan_out(pred_row1_w32_scanout),
 .clk (l2clk),
 .en  (htc_wrpred1_hw2),
 .din (htd_newpred_hw2[31:0]),
 .dout (pred_row1[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_32 pred_row2_w32   
(
 .scan_in(pred_row2_w32_scanin),
 .scan_out(pred_row2_w32_scanout),
 .clk (l2clk),
 .en  (htc_wrpred2_hw2),
 .din (htd_newpred_hw2[31:0]),
 .dout (pred_row2[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_50c__width_32 pred_row3_w32   
(
 .scan_in(pred_row3_w32_scanin),
 .scan_out(pred_row3_w32_scanout),
 .clk (l2clk),
 .en  (htc_wrpred3_hw2),
 .din (htd_newpred_hw2[31:0]),
 .dout (pred_row3[31:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_mux_macro__mux_aodec__ports_8__stack_50c__width_16 mux_pred0_m0_w16     
(
 .din0(pred_row0[15:0]),
 .din1(pred_row0[31:16]),
 .din2(pred_row1[15:0]),
 .din3(pred_row1[31:16]),
 .din4(pred_row2[15:0]),
 .din5(pred_row2[31:16]),
 .din6(pred_row3[15:0]),
 .din7(pred_row3[31:16]),
 .sel(htd_pred0_idx_m0[5:3]),
 .dout(htd_pred0_m0_prebuf[15:0])
);

mmu_htd_dp_buff_macro__stack_50c__width_16 buf_pred0_m0_w16   
(
 .din(htd_pred0_m0_prebuf[15:0]),
 .dout(htd_pred0_m0[15:0])
 );


mmu_htd_dp_mux_macro__mux_aodec__ports_8__stack_50c__width_16 mux_pred1_m0_w16     
(
 .din0(pred_row0[15:0]),
 .din1(pred_row0[31:16]),
 .din2(pred_row1[15:0]),
 .din3(pred_row1[31:16]),
 .din4(pred_row2[15:0]),
 .din5(pred_row2[31:16]),
 .din6(pred_row3[15:0]),
 .din7(pred_row3[31:16]),
 .sel(htd_pred1_idx_m0[5:3]),
 .dout(htd_pred1_m0_prebuf[15:0])
);

mmu_htd_dp_buff_macro__stack_50c__width_16 buf_pred1_m0_w16   
(
 .din(htd_pred1_m0_prebuf[15:0]),
 .dout(htd_pred1_m0[15:0])
 );

mmu_htd_dp_mux_macro__mux_aodec__ports_4__stack_50c__width_32 mux_predhw2_w32     
(
 .din0(pred_row0[31:0]),
 .din1(pred_row1[31:0]),
 .din2(pred_row2[31:0]),
 .din3(pred_row3[31:0]),
 .sel(htc_upd_pred_idx_hw2[5:4]),
 .dout(htd_pred_hw2[31:0])
);

//assign new_pred_rowlo[15:0] = {
//                             (({2{htc_upd_grp[7]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[7]}} & htd_pred_hw2[15:14])),
//                             (({2{htc_upd_grp[6]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[6]}} & htd_pred_hw2[13:12])),
//                             (({2{htc_upd_grp[5]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[5]}} & htd_pred_hw2[11:10])),
//                             (({2{htc_upd_grp[4]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[4]}} & htd_pred_hw2[9:8])),
//                             (({2{htc_upd_grp[3]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[3]}} & htd_pred_hw2[7:6])),
//                             (({2{htc_upd_grp[2]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[2]}} & htd_pred_hw2[5:4])),
//                             (({2{htc_upd_grp[1]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[1]}} & htd_pred_hw2[3:2])),
//                             (({2{htc_upd_grp[0]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[0]}} & htd_pred_hw2[1:0]))
//                             };
//


//assign new_pred_rowhi[15:0] = {
//                             (({2{htc_upd_grp[7]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[7]}} & htd_pred_hw2[31:30])),
//                             (({2{htc_upd_grp[6]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[6]}} & htd_pred_hw2[29:28])),
//                             (({2{htc_upd_grp[5]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[5]}} & htd_pred_hw2[27:26])),
//                             (({2{htc_upd_grp[4]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[4]}} & htd_pred_hw2[25:24])),
//                             (({2{htc_upd_grp[3]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[3]}} & htd_pred_hw2[23:22])),
//                             (({2{htc_upd_grp[2]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[2]}} & htd_pred_hw2[21:20])),
//                             (({2{htc_upd_grp[1]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[1]}} & htd_pred_hw2[19:18])),
//                             (({2{htc_upd_grp[0]}} & new_pred_bit[1:0]) | ({2{~htc_upd_grp[0]}} & htd_pred_hw2[17:16]))
//                             };
//
//assign htc_newpred_hw2[31:0] = {
//                                (({16{upd_pred_idx[3]}} & new_pred_rowhi[15:0]) | 
//                                 ({16{~upd_pred_idx[3]}} & htd_pred_hw2[31:16])),
//                                (({16{~upd_pred_idx[3]}} & new_pred_rowlo[15:0]) | 
//                                 ({16{upd_pred_idx[3]}} & htd_pred_hw2[15:0]))
//                                };


mmu_htd_dp_nand_macro__ports_2__stack_50c__width_32 nand_newpredrow_w32    (
.din0 ({16{htc_new_pred_bit[1:0]}}),
.din1 ({{2{htc_upd_grp[7]}},{2{htc_upd_grp[6]}},{2{htc_upd_grp[5]}},{2{htc_upd_grp[4]}},
       {2{htc_upd_grp[3]}},{2{htc_upd_grp[2]}},{2{htc_upd_grp[1]}},{2{htc_upd_grp[0]}},
       {2{htc_upd_grp[7]}},{2{htc_upd_grp[6]}},{2{htc_upd_grp[5]}},{2{htc_upd_grp[4]}},
       {2{htc_upd_grp[3]}},{2{htc_upd_grp[2]}},{2{htc_upd_grp[1]}},{2{htc_upd_grp[0]}}}),
.dout (new_row[31:0])
);

mmu_htd_dp_nand_macro__ports_2__stack_50c__width_32 nand_oldpredrow_w32    (
.din0 ({htd_pred_hw2[31:0]}),
.din1 ({{2{htc_upd_grp_x[7]}},{2{htc_upd_grp_x[6]}},{2{htc_upd_grp_x[5]}},{2{htc_upd_grp_x[4]}},
       {2{htc_upd_grp_x[3]}},{2{htc_upd_grp_x[2]}},{2{htc_upd_grp_x[1]}},{2{htc_upd_grp_x[0]}},
       {2{htc_upd_grp_x[7]}},{2{htc_upd_grp_x[6]}},{2{htc_upd_grp_x[5]}},{2{htc_upd_grp_x[4]}},
       {2{htc_upd_grp_x[3]}},{2{htc_upd_grp_x[2]}},{2{htc_upd_grp_x[1]}},{2{htc_upd_grp_x[0]}}}),
.dout (old_row[31:0])
);

mmu_htd_dp_nand_macro__ports_2__stack_50c__width_32 nand_predrow_w32    (
.din0 (new_row[31:0]),
.din1 (old_row[31:0]),
.dout (new_pred_row[31:0])
);

mmu_htd_dp_mux_macro__mux_aope__ports_2__stack_50c__width_32 mux_predrow_w32  (
    .din0   ({new_pred_row[31:16],htd_pred_hw2[15:0]}),
    .din1   ({htd_pred_hw2[31:16],new_pred_row[15:0]}),
    .sel0   ({htc_upd_pred_idx_hw2[3]}),
    .dout   ({htd_newpred_hw2[31:0]})
);


/////////////////////////////////////////////////////////////////////
// MRA Access Cycle 
// => Conf. Register (M1)
// => Read Range/Offset (HW3)
// => Muxing TTE data for thread whose RR values are available
/////////////////////////////////////////////////////////////////////
// MUX out RA/PA of return tte queue, prepare for RR check and RA2PA
mmu_htd_dp_mux_macro__mux_aonpe__ports_8__stack_50c__width_40  mux_ttedata_hw3_w40     (
    .din0({thr0_tte_data_hw2[39:0]}), 
    .din1({thr1_tte_data_hw2[39:0]}), 
    .din2({thr2_tte_data_hw2[39:0]}), 
    .din3({thr3_tte_data_hw2[39:0]}), 
    .din4({thr4_tte_data_hw2[39:0]}), 
    .din5({thr5_tte_data_hw2[39:0]}), 
    .din6({thr6_tte_data_hw2[39:0]}), 
    .din7({thr7_tte_data_hw2[39:0]}), 
    .sel0(htc_thr_prevalid_hw3[0]),
    .sel1(htc_thr_prevalid_hw3[1]),
    .sel2(htc_thr_prevalid_hw3[2]),
    .sel3(htc_thr_prevalid_hw3[3]),
    .sel4(htc_thr_prevalid_hw3[4]),
    .sel5(htc_thr_prevalid_hw3[5]),
    .sel6(htc_thr_prevalid_hw3[6]),
    .sel7(htc_thr_prevalid_hw3[7]),
    .dout({tte_data_hw3[39:0]})
);

                                                      
//assign htd_pgsz_hw3[2:0] = tte_data_hw3[2:0];


//generate the ramask

//mux_macro  mux_ramask_w18 (width=18, ports=8, mux=aodec, stack=36r) (
//    .din0(18'b000000000000000), 
//    .din1(18'b000000000000111), 
//    .din2(18'b000000000111111), 
//    .din3(18'b000000111111111), 
//    .din4(18'b000111111111111), 
//    .din5(18'b111111111111111), 
//    .din6(18'b111111111111111), 
//    .din7(18'b111111111111111), 
//    .sel(tte_data_hw2[2:0]),
//    .dout(ra_mask_hw3[30:13])
//);


// Use aope mux, because the selects are not one-hot
mmu_htd_dp_mux_macro__mux_aope__ports_4__stack_16r__width_15 mux_ramask_w15     (
    .din0({15'b111111111111111}),         //pgsz5
    .din1({15'b000000111111111}),         //pgsz3
    .din2({15'b000000000000111}),         //pgsz1
    .din3({15'b000000000000000}),         //pgsz0
    .sel0(tte_data_hw3[2]),
    .sel1(tte_data_hw3[1]),
    .sel2(tte_data_hw3[0]),
    .dout({ra_mask_hw3[27:13]})
);


mmu_htd_dp_msff_macro__stack_16r__width_15 reg_ramaskhw4_w15   (
    .scan_in(reg_ramaskhw4_w15_scanin),
    .scan_out(reg_ramaskhw4_w15_scanout),
    .clk (l2clk),
    .en  (htc_hw3_clken),
    .din ({ra_mask_hw3[27:13]}),
    .dout ({htc_ra_mask_hw4[27:13]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


mmu_htd_dp_msff_macro__stack_50c__width_40 reg_ttedatahw4_w40   (
    .scan_in(reg_ttedatahw4_w40_scanin),
    .scan_out(reg_ttedatahw4_w40_scanout),
    .clk (l2clk),
    .en  (htc_hw3_clken),
    .din ({tte_data_hw3[39:0]}),
    .dout ({tte_data_hw4[39:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// Range and offset are returned from mra in HW3

mmu_htd_dp_msff_macro__stack_58c__width_27 reg_offsethw4_w27   
(
 .scan_in(reg_offsethw4_w27_scanin),
 .scan_out(reg_offsethw4_w27_scanout),
 .clk (l2clk),
 .en  (htc_hw3_clken),
 .din  ({mra_data[26:0]}),
 .dout ({offset0_hw4[39:13]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

mmu_htd_dp_msff_macro__stack_58c__width_55 reg_rangehw4_w55   
(
 .scan_in(reg_rangehw4_w55_scanin),
 .scan_out(reg_rangehw4_w55_scanout),
 .clk (l2clk),
 .en  (htc_hw3_clken),
 .din ({mra_data[81:27]}),
 .dout ({range0_hw4[63],range0_hw4[53:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

/////////////////////////////////////////////////////////////////////
// Real Address to Physical Address (HW4)
/////////////////////////////////////////////////////////////////////


assign ra_mask_hw4[39:13] = {12'b0,htc_ra_mask_hw4[27:13]};


/////////////////////////////////////////////////////////////////////
// Range Window Checking
// Check whether TTE is within real range
// Cout = A + (~B) + (cin=1'b1);
// If Cout == 1, then A >=B
// If Cout == 0, then A < B
// Here A = TTE_DATA
//  and B = Lower Range or Upper Range


// We need to check for A>B
// So modify the above check to not add cin=1
// In this case Cout is generated only if A>B
// Cout = A + (~B) + (cin=0)
// In other words, a cout from a subtractor can give us A>=B, but
// we need A>B information.  A>B, implies A-1>=B, This is detected by doing (A-1) -B,
// which in 2's comp is (A-1) + (~B) + (cin=1) = A + (~B).
//
// For upper range check, A = TTE OR'd with MASK (upper address on page), B = range_hi,
//                        A>B indicates out of range
// For lower range check, A = range_lo, B = TTE And'd with ~MASK (lower address on page)
//                        A>B indicates in range.
/////////////////////////////////////////////////////////////////////
// range_en bit is physically located in bit 54.
// It is bit 63 in software visible real range register
assign htd_range_en_hw4 = range0_hw4[63];


// Clear W bit in TTE if W_mask==1 in offset register

mmu_htd_dp_inv_macro__stack_36r__width_27 inv1_w27   (
  .din({ra_mask_hw4[39:13]}),
  .dout({ra_mask_hw4_[39:13]})
);

// generate the lower bound for the page pointed to by tte
mmu_htd_dp_and_macro__ports_2__stack_36r__width_27 and1_w27    (
  .din0({tte_data_hw4[34:8]}),                   //PA
  .din1({ra_mask_hw4_[39:13]}),
  .dout({tte_lo[39:13]})
);

// generate the upper bound for the page pointed to by tte
mmu_htd_dp_or_macro__ports_2__stack_36r__width_27 or1_w27    (
  .din0({tte_data_hw4[34:8]}),
  .din1({ra_mask_hw4[39:13]}),
  .dout({tte_hi[39:13]})
);

/////////////////////////////////////////////////////////////////////
//Real Range Checking (0)
// lower range : range0[26:0]
// upper range : range0[53:27]

/////////////////////////////////////////////////////////////////////
mmu_htd_dp_inv_macro__stack_36r__width_28 inv2_w28   (
  .din({ra_to_pa_upper_hit_, tte_lo[39:13]}),
  .dout({htd_ra2pa_upper_hit_hw4, tte_lo_[39:13]})
);

mmu_htd_dp_inv_macro__stack_36r__width_28 inv3_w28   (
  .din({ ra_to_pa_lower_hit_,      range0_hw4[53:27]}),
  .dout({htd_ra2pa_lower_hit_hw4, rg0_hi_[39:13]})
);

assign rg0_lo[39:13] = range0_hw4[26:0];

assign htd_razero_hw4 = tte_data_hw4[39];

// lower limit check,
// range_lo > tte_lo => ~ra2pa_lower_hit
mmu_htd_dp_cla_macro__width_32	gt_lb_cla_rg0	 (
  .din0({rg0_lo[39:13], 5'b00000}),
  .din1({tte_lo_[39:13], 5'b11111}),
  .cin (1'b0),
  .cout(ra_to_pa_lower_hit_),
  .dout(sum0_unused[31:0])
);

// uppe limit check
// tte_hi > range_hi => ~ra2pa_upper_hit
mmu_htd_dp_cla_macro__width_32	lt_ub_cla_rg0	 (
  .din0({tte_hi[39:13], 5'b00000}),     
  .din1({rg0_hi_[39:13], 5'b11111}),
  .cin (1'b0),
  .cout(ra_to_pa_upper_hit_),
  .dout(sum1_unused[31:0])
);

// conver ra to pa, by adding offset to ra
mmu_htd_dp_cla_macro__width_12	cla0_ratopa	 (
  .din0(offset0_hw4[24:13]),
  .din1(tte_data_hw4[19:8]),
  .cin (1'b0),
  .cout(cout0),
  .dout(pa_0_din[24:13])
);

mmu_htd_dp_cla_macro__width_16	cla1_ratopa	 (
  .din0({1'b0, offset0_hw4[39:25]}),
  .din1({1'b0, tte_data_hw4[34:20]}),
  .cin (cout0),
  .cout(carry0_unused),
  .dout({sum_unused, pa_0_din[39:25]})
);
//assign pa_0_din[39:30] = offset0[39:30];


// Prepare to write to I/D TLB registers
// 
mmu_htd_dp_mux_macro__mux_aope__ports_2__stack_36r__width_27 mux_tlbdatainhw4_w27  (
    .din0   ({pa_0_din[39:13]}),       // RA       
    .din1   (tte_data_hw4[34:8]),                                               //PA
    .sel0   ({htc_ranotpa_hw4}),
    .dout   ({htd_tlbdatain[34:8]})
);


assign htd_tlbdatain_hw4[38:0] = {tte_data_hw4[38:35], htd_tlbdatain[34:8], tte_data_hw4[7:0]};


mmu_htd_dp_msff_macro__stack_50c__width_39 reg_tlbdatainhw5_w39   (
    .scan_in(reg_tlbdatainhw5_w39_scanin),
    .scan_out(reg_tlbdatainhw5_w39_scanout),
    .clk (l2clk),
    .en  (htc_hw4_clken),
    .din ({htd_tlbdatain_hw4[38:0]}),
    .dout ({htd_tlbdatain_hw5[38:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign htd_tlbdatain_din[38:0] = htd_tlbdatain_hw5[38:0];

                                               
// tag access mux
mmu_htd_dp_mux_macro__mux_aonpe__ports_8__stack_50c__width_48  mux_vactx_w48     (
    .din0({thr0_va_ff[47:13], htd_thr0_ctx_ff[12:0]}),
    .din1({thr1_va_ff[47:13], htd_thr1_ctx_ff[12:0]}),
    .din2({thr2_va_ff[47:13], htd_thr2_ctx_ff[12:0]}),
    .din3({thr3_va_ff[47:13], htd_thr3_ctx_ff[12:0]}),
    .din4({thr4_va_ff[47:13], htd_thr4_ctx_ff[12:0]}),
    .din5({thr5_va_ff[47:13], htd_thr5_ctx_ff[12:0]}),
    .din6({thr6_va_ff[47:13], htd_thr6_ctx_ff[12:0]}),
    .din7({thr7_va_ff[47:13], htd_thr7_ctx_ff[12:0]}),
    .sel0(htc_rd_tteq[0]),
    .sel1(htc_rd_tteq[1]),
    .sel2(htc_rd_tteq[2]),
    .sel3(htc_rd_tteq[3]),
    .sel4(htc_rd_tteq[4]),
    .sel5(htc_rd_tteq[5]),
    .sel6(htc_rd_tteq[6]),
    .sel7(htc_rd_tteq[7]),
    .dout({htd_tagaccess_din_prebuf[47:0]})
);

mmu_htd_dp_buff_macro__stack_50c__width_48 buf_vactx_w48   (
.din({htd_tagaccess_din_prebuf[47:0]}),
.dout({htd_tagaccess_din[47:0]})
);

assign lsu_tlu_dsfsr_ct_b_1_unused = lsu_tlu_dsfsr_ct_b[1];
assign l15_spc_data1_unused[25:0] = {l15_spc_data1[105:90], 
                                   l15_spc_data1[61:56],l15_spc_data1[9],l15_spc_data1[5:3]};
assign l15_mmu_cpkt_unused = l15_mmu_cpkt[5];


// fixscan start:
assign reg_tlbmiss_w30_scanin    = scan_in                  ;
assign reg0_vactx_w50_scanin     = reg_tlbmiss_w30_scanout  ;
assign reg1_vactx_w50_scanin     = reg0_vactx_w50_scanout   ;
assign reg2_vactx_w50_scanin     = reg1_vactx_w50_scanout   ;
assign reg3_vactx_w50_scanin     = reg2_vactx_w50_scanout   ;
assign reg4_vactx_w50_scanin     = reg3_vactx_w50_scanout   ;
assign reg5_vactx_w50_scanin     = reg4_vactx_w50_scanout   ;
assign reg6_vactx_w50_scanin     = reg5_vactx_w50_scanout   ;
assign reg7_vactx_w50_scanin     = reg6_vactx_w50_scanout   ;
assign reg_tsbconf_m2_w39_scanin = reg7_vactx_w50_scanout   ;
assign reg0_tsbcfg_w28_scanin    = reg_tsbconf_m2_w39_scanout;
assign reg1_tsbcfg_w28_scanin    = reg0_tsbcfg_w28_scanout  ;
assign reg2_tsbcfg_w28_scanin    = reg1_tsbcfg_w28_scanout  ;
assign reg3_tsbcfg_w28_scanin    = reg2_tsbcfg_w28_scanout  ;
assign reg4_tsbcfg_w28_scanin    = reg3_tsbcfg_w28_scanout  ;
assign reg5_tsbcfg_w28_scanin    = reg4_tsbcfg_w28_scanout  ;
assign reg6_tsbcfg_w28_scanin    = reg5_tsbcfg_w28_scanout  ;
assign reg7_tsbcfg_w28_scanin    = reg6_tsbcfg_w28_scanout  ;
assign reg_q1addr_w36_scanin     = reg7_tsbcfg_w28_scanout  ;
assign reg_q0addr_ng_w36_scanin  = reg_q1addr_w36_scanout   ;
assign reg_q0addr_g_w36_scanin   = reg_q0addr_ng_w36_scanout;
assign reg_l15addr_w36_scanin    = reg_q0addr_g_w36_scanout ;
assign reg_vpn_w40_scanin        = reg_l15addr_w36_scanout  ;
assign reg_tsbcfg_hw1_w30_scanin = reg_vpn_w40_scanout      ;
assign reg_l15vahw1_w36_scanin   = reg_tsbcfg_hw1_w30_scanout;
assign reg_l15ctx_w34_scanin     = reg_l15vahw1_w36_scanout ;
assign reg_l15data_w49_scanin    = reg_l15ctx_w34_scanout   ;
assign e0_tte_reg_w40_scanin     = reg_l15data_w49_scanout  ;
assign e1_tte_reg_w40_scanin     = e0_tte_reg_w40_scanout   ;
assign e2_tte_reg_w40_scanin     = e1_tte_reg_w40_scanout   ;
assign e3_tte_reg_w40_scanin     = e2_tte_reg_w40_scanout   ;
assign e4_tte_reg_w40_scanin     = e3_tte_reg_w40_scanout   ;
assign e5_tte_reg_w40_scanin     = e4_tte_reg_w40_scanout   ;
assign e6_tte_reg_w40_scanin     = e5_tte_reg_w40_scanout   ;
assign e7_tte_reg_w40_scanin     = e6_tte_reg_w40_scanout   ;
assign pred_row0_w32_scanin      = e7_tte_reg_w40_scanout   ;
assign pred_row1_w32_scanin      = pred_row0_w32_scanout    ;
assign pred_row2_w32_scanin      = pred_row1_w32_scanout    ;
assign pred_row3_w32_scanin      = pred_row2_w32_scanout    ;
assign reg_ramaskhw4_w15_scanin  = pred_row3_w32_scanout    ;
assign reg_ttedatahw4_w40_scanin = reg_ramaskhw4_w15_scanout;
assign reg_offsethw4_w27_scanin  = reg_ttedatahw4_w40_scanout;
assign reg_rangehw4_w55_scanin   = reg_offsethw4_w27_scanout;
assign reg_tlbdatainhw5_w39_scanin = reg_rangehw4_w55_scanout ;
assign scan_out                  = reg_tlbdatainhw5_w39_scanout;
// fixscan end:
endmodule


//
//   buff macro
//
//


module mmu_htd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module mmu_htd_dp_inv_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module mmu_htd_dp_or_macro__ports_2__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


or2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_30 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [28:0] so;

  input [29:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [29:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(30)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[29:0]),
.si({scan_in,so[28:0]}),
.so({so[28:0],scan_out}),
.q(dout[29:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module mmu_htd_dp_and_macro__stack_50c__width_13 (
  din0, 
  din1, 
  dout);
  input [12:0] din0;
  input [12:0] din1;
  output [12:0] dout;


and2 #(13)  d0_0 (
.in0(din0[12:0]),
.in1(din1[12:0]),
.out(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__mux_aope__ports_4__stack_50c__width_50 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire [49:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [48:0] so;

  input [49:0] din0;
  input [49:0] din1;
  input [49:0] din2;
  input [49:0] din3;
  input sel0;
  input sel1;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [49:0] dout;


  output scan_out;


cl_dp1_penc4_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(50)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[49:0]),
  .in1(din1[49:0]),
  .in2(din2[49:0]),
  .in3(din3[49:0]),
.dout(muxout[49:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(50)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[49:0]),
.si({scan_in,so[48:0]}),
.so({so[48:0],scan_out}),
.q(dout[49:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module mmu_htd_dp_zero_macro__dcmp_12x__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


zero #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module mmu_htd_dp_buff_macro__stack_50c__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_58c__width_33 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [32:0] din0;
  input sel0;
  input [32:0] din1;
  input sel1;
  input [32:0] din2;
  input sel2;
  input [32:0] din3;
  input sel3;
  output [32:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(33)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
  .in2(din2[32:0]),
  .in3(din3[32:0]),
.dout(dout[32:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module mmu_htd_dp_xor_macro__ports_3__stack_64c__width_12 (
  din0, 
  din1, 
  din2, 
  dout);
  input [11:0] din0;
  input [11:0] din1;
  input [11:0] din2;
  output [11:0] dout;


xor3 #(12)  d0_0 (
.in0(din0[11:0]),
.in1(din1[11:0]),
.in2(din2[11:0]),
.out(dout[11:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module mmu_htd_dp_xor_macro__ports_2__stack_64c__width_6 (
  din0, 
  din1, 
  dout);
  input [5:0] din0;
  input [5:0] din1;
  output [5:0] dout;


xor2 #(6)  d0_0 (
.in0(din0[5:0]),
.in1(din1[5:0]),
.out(dout[5:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_pgpe__ports_2__stack_58c__width_40 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [39:0] din0;
  input [39:0] din1;
  input sel0;
  output [39:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(40)  d0_0 (
  .sel(psel1),
  .in0(din0[39:0]),
  .in1(din1[39:0]),
.dout(dout[39:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_pgpe__ports_2__stack_58c__width_42 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [41:0] din0;
  input [41:0] din1;
  input sel0;
  output [41:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(42)  d0_0 (
  .sel(psel1),
  .in0(din0[41:0]),
  .in1(din1[41:0]),
.dout(dout[41:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_pgpe__ports_2__stack_58c__width_39 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [38:0] din0;
  input [38:0] din1;
  input sel0;
  output [38:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(39)  d0_0 (
  .sel(psel1),
  .in0(din0[38:0]),
  .in1(din1[38:0]),
.dout(dout[38:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_58c__width_39 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [37:0] so;

  input [38:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [38:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(39)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[38:0]),
.si({scan_in,so[37:0]}),
.so({so[37:0],scan_out}),
.q(dout[38:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aodec__ports_4__stack_50c__width_28 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [27:0] din0;
  input [27:0] din1;
  input [27:0] din2;
  input [27:0] din3;
  input [1:0] sel;
  output [27:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(28)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[27:0]),
  .in1(din1[27:0]),
  .in2(din2[27:0]),
  .in3(din3[27:0]),
.dout(dout[27:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_28 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [26:0] so;

  input [27:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [27:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aonpe__ports_8__stack_50c__width_28 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [27:0] din0;
  input sel0;
  input [27:0] din1;
  input sel1;
  input [27:0] din2;
  input sel2;
  input [27:0] din3;
  input sel3;
  input [27:0] din4;
  input sel4;
  input [27:0] din5;
  input sel5;
  input [27:0] din6;
  input sel6;
  input [27:0] din7;
  input sel7;
  output [27:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(28)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[27:0]),
  .in1(din1[27:0]),
  .in2(din2[27:0]),
  .in3(din3[27:0]),
  .in4(din4[27:0]),
  .in5(din5[27:0]),
  .in6(din6[27:0]),
  .in7(din7[27:0]),
.dout(dout[27:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__left_13__mux_aonpe__ports_8__stack_50c__width_35 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [34:0] din0;
  input sel0;
  input [34:0] din1;
  input sel1;
  input [34:0] din2;
  input sel2;
  input [34:0] din3;
  input sel3;
  input [34:0] din4;
  input sel4;
  input [34:0] din5;
  input sel5;
  input [34:0] din6;
  input sel6;
  input [34:0] din7;
  input sel7;
  output [34:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(35)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[34:0]),
  .in1(din1[34:0]),
  .in2(din2[34:0]),
  .in3(din3[34:0]),
  .in4(din4[34:0]),
  .in5(din5[34:0]),
  .in6(din6[34:0]),
  .in7(din7[34:0]),
.dout(dout[34:0])
);


endmodule


//
//   buff macro
//
//


module mmu_htd_dp_buff_macro__left_13__stack_50c__width_35 (
  din, 
  dout);
  input [34:0] din;
  output [34:0] dout;


buff #(35)  d0_0 (
.in(din[34:0]),
.out(dout[34:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aope__ports_4__stack_50c__width_24 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [23:0] din0;
  input [23:0] din1;
  input [23:0] din2;
  input [23:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [23:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(24)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[23:0]),
  .in1(din1[23:0]),
  .in2(din2[23:0]),
  .in3(din3[23:0]),
.dout(dout[23:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aodec__ports_8__stack_50c__width_36 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [35:0] din0;
  input [35:0] din1;
  input [35:0] din2;
  input [35:0] din3;
  input [35:0] din4;
  input [35:0] din5;
  input [35:0] din6;
  input [35:0] din7;
  input [2:0] sel;
  output [35:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(36)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[35:0]),
  .in1(din1[35:0]),
  .in2(din2[35:0]),
  .in3(din3[35:0]),
  .in4(din4[35:0]),
  .in5(din5[35:0]),
  .in6(din6[35:0]),
  .in7(din7[35:0]),
.dout(dout[35:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_pgpe__ports_2__stack_50c__width_36 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [35:0] din0;
  input [35:0] din1;
  input sel0;
  output [35:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(36)  d0_0 (
  .sel(psel1),
  .in0(din0[35:0]),
  .in1(din1[35:0]),
.dout(dout[35:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_36 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [34:0] so;

  input [35:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [35:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(36)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[35:0]),
.si({scan_in,so[34:0]}),
.so({so[34:0],scan_out}),
.q(dout[35:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aope__ports_2__stack_50c__width_36 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [35:0] din0;
  input [35:0] din1;
  input sel0;
  output [35:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(36)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[35:0]),
  .in1(din1[35:0]),
.dout(dout[35:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aope__ports_3__stack_50c__width_36 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [35:0] din0;
  input [35:0] din1;
  input [35:0] din2;
  input sel0;
  input sel1;
  output [35:0] dout;


cl_dp1_penc3_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(36)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[35:0]),
  .in1(din1[35:0]),
  .in2(din2[35:0]),
.dout(dout[35:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_37 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [35:0] so;

  input [36:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [36:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aonpe__ports_2__stack_50c__width_36 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [35:0] din0;
  input sel0;
  input [35:0] din1;
  input sel1;
  output [35:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(36)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[35:0]),
  .in1(din1[35:0]),
.dout(dout[35:0])
);


endmodule


//
//   buff macro
//
//


module mmu_htd_dp_buff_macro__dbuff_48x__rep_1__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_pgdec__ports_8__stack_50c__width_40 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [39:0] din0;
  input [39:0] din1;
  input [39:0] din2;
  input [39:0] din3;
  input [39:0] din4;
  input [39:0] din5;
  input [39:0] din6;
  input [39:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [39:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(40)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[39:0]),
  .in1(din1[39:0]),
  .in2(din2[39:0]),
  .in3(din3[39:0]),
  .in4(din4[39:0]),
  .in5(din5[39:0]),
  .in6(din6[39:0]),
  .in7(din7[39:0]),
.dout(dout[39:0]),
  .muxtst(muxtst)
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_40 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [38:0] so;

  input [39:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [39:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(40)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[39:0]),
.si({scan_in,so[38:0]}),
.so({so[38:0],scan_out}),
.q(dout[39:0])
);


endmodule


//
//   buff macro
//
//


module mmu_htd_dp_buff_macro__dbuff_32x__rep_1__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_pgdec__ports_8__stack_50c__width_28 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [27:0] din0;
  input [27:0] din1;
  input [27:0] din2;
  input [27:0] din3;
  input [27:0] din4;
  input [27:0] din5;
  input [27:0] din6;
  input [27:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [27:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(28)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[27:0]),
  .in1(din1[27:0]),
  .in2(din2[27:0]),
  .in3(din3[27:0]),
  .in4(din4[27:0]),
  .in5(din5[27:0]),
  .in6(din6[27:0]),
  .in7(din7[27:0]),
.dout(dout[27:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_pgdec__ports_4__stack_50c__width_7 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [6:0] din0;
  input [6:0] din1;
  input [6:0] din2;
  input [6:0] din3;
  input [1:0] sel;
  input muxtst;
  input test;
  output [6:0] dout;


cl_dp1_pdec4_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
  .test(test)
);

mux4 #(7)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
  .in2(din2[6:0]),
  .in3(din3[6:0]),
.dout(dout[6:0]),
  .muxtst(muxtst)
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_34 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [32:0] so;

  input [33:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [33:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(34)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[33:0]),
.si({scan_in,so[32:0]}),
.so({so[32:0],scan_out}),
.q(dout[33:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_49 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [47:0] so;

  input [48:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [48:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(49)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[48:0]),
.si({scan_in,so[47:0]}),
.so({so[47:0],scan_out}),
.q(dout[48:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aope__ports_2__stack_50c__width_32 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;
  output [31:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module mmu_htd_dp_cmp_macro__dcmp_8x__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output dout;


cmp #(16)  m0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout)
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module mmu_htd_dp_nor_macro__ports_3__width_3 (
  din0, 
  din1, 
  din2, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  output [2:0] dout;


nor3 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.in2(din2[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_htd_dp_nand_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nand3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module mmu_htd_dp_inv_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module mmu_htd_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_htd_dp_nand_macro__ports_2__width_5 (
  din0, 
  din1, 
  dout);
  input [4:0] din0;
  input [4:0] din1;
  output [4:0] dout;


nand2 #(5)  d0_0 (
.in0(din0[4:0]),
.in1(din1[4:0]),
.out(dout[4:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_htd_dp_nand_macro__ports_3__width_2 (
  din0, 
  din1, 
  din2, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  input [1:0] din2;
  output [1:0] dout;


nand3 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.in2(din2[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module mmu_htd_dp_buff_macro__minbuff_1__stack_50c__width_39 (
  din, 
  dout);
  input [38:0] din;
  output [38:0] dout;


buff #(39)  d0_0 (
.in(din[38:0]),
.out(dout[38:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_32 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aodec__ports_8__stack_50c__width_16 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [15:0] din0;
  input [15:0] din1;
  input [15:0] din2;
  input [15:0] din3;
  input [15:0] din4;
  input [15:0] din5;
  input [15:0] din6;
  input [15:0] din7;
  input [2:0] sel;
  output [15:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(16)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
  .in2(din2[15:0]),
  .in3(din3[15:0]),
  .in4(din4[15:0]),
  .in5(din5[15:0]),
  .in6(din6[15:0]),
  .in7(din7[15:0]),
.dout(dout[15:0])
);


endmodule


//
//   buff macro
//
//


module mmu_htd_dp_buff_macro__stack_50c__width_16 (
  din, 
  dout);
  input [15:0] din;
  output [15:0] dout;


buff #(16)  d0_0 (
.in(din[15:0]),
.out(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aodec__ports_4__stack_50c__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input [1:0] sel;
  output [31:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_htd_dp_nand_macro__ports_2__stack_50c__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output [31:0] dout;


nand2 #(32)  d0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aonpe__ports_8__stack_50c__width_40 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [39:0] din0;
  input sel0;
  input [39:0] din1;
  input sel1;
  input [39:0] din2;
  input sel2;
  input [39:0] din3;
  input sel3;
  input [39:0] din4;
  input sel4;
  input [39:0] din5;
  input sel5;
  input [39:0] din6;
  input sel6;
  input [39:0] din7;
  input sel7;
  output [39:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(40)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[39:0]),
  .in1(din1[39:0]),
  .in2(din2[39:0]),
  .in3(din3[39:0]),
  .in4(din4[39:0]),
  .in5(din5[39:0]),
  .in6(din6[39:0]),
  .in7(din7[39:0]),
.dout(dout[39:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aope__ports_4__stack_16r__width_15 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [14:0] din0;
  input [14:0] din1;
  input [14:0] din2;
  input [14:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [14:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(15)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[14:0]),
  .in1(din1[14:0]),
  .in2(din2[14:0]),
  .in3(din3[14:0]),
.dout(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_16r__width_15 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [13:0] so;

  input [14:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [14:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[14:0]),
.si({scan_in,so[13:0]}),
.so({so[13:0],scan_out}),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_58c__width_27 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [25:0] so;

  input [26:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [26:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(27)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[26:0]),
.si({scan_in,so[25:0]}),
.so({so[25:0],scan_out}),
.q(dout[26:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_58c__width_55 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [53:0] so;

  input [54:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [54:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(55)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[54:0]),
.si({scan_in,so[53:0]}),
.so({so[53:0],scan_out}),
.q(dout[54:0])
);


endmodule


//
//   invert macro
//
//


module mmu_htd_dp_inv_macro__stack_36r__width_27 (
  din, 
  dout);
  input [26:0] din;
  output [26:0] dout;


inv #(27)  d0_0 (
.in(din[26:0]),
.out(dout[26:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module mmu_htd_dp_and_macro__ports_2__stack_36r__width_27 (
  din0, 
  din1, 
  dout);
  input [26:0] din0;
  input [26:0] din1;
  output [26:0] dout;


and2 #(27)  d0_0 (
.in0(din0[26:0]),
.in1(din1[26:0]),
.out(dout[26:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module mmu_htd_dp_or_macro__ports_2__stack_36r__width_27 (
  din0, 
  din1, 
  dout);
  input [26:0] din0;
  input [26:0] din1;
  output [26:0] dout;


or2 #(27)  d0_0 (
.in0(din0[26:0]),
.in1(din1[26:0]),
.out(dout[26:0])
);


endmodule


//
//   invert macro
//
//


module mmu_htd_dp_inv_macro__stack_36r__width_28 (
  din, 
  dout);
  input [27:0] din;
  output [27:0] dout;


inv #(28)  d0_0 (
.in(din[27:0]),
.out(dout[27:0])
);


endmodule


//
//   cla macro
//
//


module mmu_htd_dp_cla_macro__width_32 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [31:0] din0;
  input [31:0] din1;
  output [31:0] dout;
  output cout;


cla #(32)  m0_0 (
.cin(cin),
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout[31:0]),
.cout(cout)
);


endmodule


//
//   cla macro
//
//


module mmu_htd_dp_cla_macro__width_12 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [11:0] din0;
  input [11:0] din1;
  output [11:0] dout;
  output cout;


cla #(12)  m0_0 (
.cin(cin),
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout[11:0]),
.cout(cout)
);


endmodule


//
//   cla macro
//
//


module mmu_htd_dp_cla_macro__width_16 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [15:0] din0;
  input [15:0] din1;
  output [15:0] dout;
  output cout;


cla #(16)  m0_0 (
.cin(cin),
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout[15:0]),
.cout(cout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aope__ports_2__stack_36r__width_27 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [26:0] din0;
  input [26:0] din1;
  input sel0;
  output [26:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(27)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[26:0]),
  .in1(din1[26:0]),
.dout(dout[26:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_htd_dp_msff_macro__stack_50c__width_39 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [37:0] so;

  input [38:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [38:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(39)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[38:0]),
.si({scan_in,so[37:0]}),
.so({so[37:0],scan_out}),
.q(dout[38:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_htd_dp_mux_macro__mux_aonpe__ports_8__stack_50c__width_48 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [47:0] din0;
  input sel0;
  input [47:0] din1;
  input sel1;
  input [47:0] din2;
  input sel2;
  input [47:0] din3;
  input sel3;
  input [47:0] din4;
  input sel4;
  input [47:0] din5;
  input sel5;
  input [47:0] din6;
  input sel6;
  input [47:0] din7;
  input sel7;
  output [47:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(48)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
  .in5(din5[47:0]),
  .in6(din6[47:0]),
  .in7(din7[47:0]),
.dout(dout[47:0])
);


endmodule


//
//   buff macro
//
//


module mmu_htd_dp_buff_macro__stack_50c__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_mbd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_mbd_dp (
  asi_mbd_scp_data, 
  asi_compare_data, 
  asi_mbd_sel_scp, 
  ase_mbd_mbist_data, 
  mbd_compare);
wire [31:0] read_data;


input	[31:0]	asi_mbd_scp_data;
input	[7:0]	asi_compare_data;
input 		asi_mbd_sel_scp;

input	[31:0]	ase_mbd_mbist_data;	// MBIST

output		mbd_compare;


//////////////////////////////////////////////////////////////////////


mmu_mbd_dp_mux_macro__mux_aope__ports_2__stack_32r__width_32 read_data_mux     (
	.din0	(asi_mbd_scp_data	[31:0]	),
	.din1	(ase_mbd_mbist_data	[31:0]	),
	.sel0	(asi_mbd_sel_scp		),
	.dout	(read_data		[31:0]	)
);

mmu_mbd_dp_cmp_macro__width_32 mbist_cmp  (
	.din0	(read_data		[31:0]	),
	.din1	({4 {asi_compare_data	[7:0]}}),
	.dout	(mbd_compare			)

);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_mbd_dp_mux_macro__mux_aope__ports_2__stack_32r__width_32 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [31:0] din0;
  input [31:0] din1;
  input sel0;
  output [31:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module mmu_mbd_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_mec_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_mec_dp (
  data_in, 
  parity_in, 
  parity_out, 
  parity_err);
wire [40:0] d;
wire p;
wire [41:0] check_bus;
wire check_4;
wire check_3;
wire check_2;
wire check_1;
wire check_0;


input	[40:0]	data_in;	// Used for generation and checking
input		parity_in;	// Used for checking only; tie to '0' for gen

output		parity_out;	// Used for generation only; unused for check
output		parity_err;	// Used for checking only; unused for gen


//////////////////////////////////////////////////////////////////////////////


assign d[40:0] = 
       data_in[40:0];
assign p =
       parity_in;


assign check_bus[41:0] = 
	{p, d[40:0]};

mmu_mec_dp_prty_macro__width_8 check_4_pty  (
	.din	(check_bus	[39:32]	),
	.dout	(check_4		)
);

mmu_mec_dp_prty_macro__width_8 check_3_pty  (
	.din	(check_bus	[31:24]	),
	.dout	(check_3		)
);

mmu_mec_dp_prty_macro__width_8 check_2_pty  (
	.din	(check_bus	[23:16]	),
	.dout	(check_2		)
);

mmu_mec_dp_prty_macro__width_8 check_1_pty  (
	.din	(check_bus	[15:8]	),
	.dout	(check_1		)
);

mmu_mec_dp_prty_macro__width_8 check_0_pty  (
	.din	(check_bus	[7:0]	),
	.dout	(check_0		)
);

mmu_mec_dp_prty_macro__width_8 check_pty  (
	.din	({1'b0		       ,
		  check_bus	[41:40],
		  check_4	       ,
		  check_3	       ,
		  check_2	       ,
		  check_1	       ,
		  check_0	       }),
	.dout	(parity_out		)
);


assign parity_err = parity_out;


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

endmodule


//
//   parity macro (even parity)
//
//


module mmu_mec_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_mel_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_mel_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tlu_cerer_mrau, 
  tlu_cerer_hwtwmu, 
  mra_parity, 
  med0_parity_err, 
  med1_parity_err, 
  scan_out, 
  mel_crit_parity, 
  mel_parity, 
  mel_parity_err, 
  mel_htc_parity_err);
wire pce_ov;
wire clk;
wire stop;
wire siclk;
wire soclk;
wire se;
wire en;
wire ecc_lat_scanin;
wire ecc_lat_scanout;
wire parity_err_in;
wire parity_err_for_htc_in;
wire [1:0] rd_parity;
wire parity_err;
wire parity_err_for_htc;
wire cerer_mrau_;
wire cerer_hwtwmu_;
wire pparity_err_;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input		tlu_cerer_mrau;
input		tlu_cerer_hwtwmu;

input	[1:0]	mra_parity;

input		med0_parity_err;
input		med1_parity_err;


output		scan_out;

output	[1:0]	mel_crit_parity;
output	[1:0]	mel_parity;

output		mel_parity_err;
output		mel_htc_parity_err;


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign clk      = l2clk;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;
assign en       = 1'b1;


// Data is flopped, but parity is not...  so flop here

mmu_mel_dp_msff_macro__width_4 ecc_lat  (
	.scan_in(ecc_lat_scanin),
	.scan_out(ecc_lat_scanout),
	.din	({mra_parity		[1:0],
		  parity_err_in		       ,
		  parity_err_for_htc_in	       }),
	.dout	({rd_parity		[1:0],
		  parity_err		       ,
		  parity_err_for_htc	       }),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign mel_crit_parity[1:0] =
       rd_parity[1:0];

mmu_mel_dp_buff_macro__rep_1__width_2 parity_buf   (
	.din	(rd_parity		[1:0]	),
	.dout	(mel_parity		[1:0]	)
);

// Qualify error signals


mmu_mel_dp_inv_macro__width_1 cerer_mrau_inv  (
	.din	(tlu_cerer_mrau			),
	.dout	(cerer_mrau_			)
);

mmu_mel_dp_inv_macro__width_1 cerer_hwtwmu_inv  (
	.din	(tlu_cerer_hwtwmu		),
	.dout	(cerer_hwtwmu_			)
);

mmu_mel_dp_nor_macro__ports_2__width_1 parity_err_inv_nor   (
	.din0	(med0_parity_err		),
	.din1	(med1_parity_err		),
	.dout	(pparity_err_			)
);

mmu_mel_dp_nor_macro__ports_2__width_1 mrau_in_nor   (
	.din0	(pparity_err_			),
	.din1	(cerer_mrau_			),
	.dout	(parity_err_in			)
);

mmu_mel_dp_nor_macro__ports_2__width_1 parity_err_for_htc_in_nor   (
	.din0	(pparity_err_			),
	.din1	(cerer_hwtwmu_			),
	.dout	(parity_err_for_htc_in		)
);

assign mel_parity_err =
       parity_err;

assign mel_htc_parity_err =
       parity_err_for_htc;


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

// fixscan start:
assign ecc_lat_scanin            = scan_in                  ;
assign scan_out                  = ecc_lat_scanout          ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module mmu_mel_dp_msff_macro__width_4 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [2:0] so;

  input [3:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [3:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module mmu_mel_dp_buff_macro__rep_1__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   invert macro
//
//


module mmu_mel_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module mmu_mel_dp_nor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_mem_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_mem_dp (
  asi_error_inject, 
  asi_error_mask, 
  asi_mbist_ecc, 
  asi_mbist_run, 
  parity_in, 
  parity_out);
wire mbist_run_;
wire pre_error_inject_;
wire pre_error_inject;
wire error_inject;
wire error_inject_;
wire parity_in_;
wire parity_mux_0;
wire parity_mux_1;
wire parity_mux_2;


input		asi_error_inject;
input		asi_error_mask;

input		asi_mbist_ecc;
input		asi_mbist_run;

input 		parity_in;

output		parity_out;	


mmu_mem_dp_inv_macro__width_1 mbist_run_b_inv  (
	.din	(asi_mbist_run			),
	.dout	(mbist_run_			)
);

mmu_mem_dp_nand_macro__ports_2__width_1 pre_error_inject_b_nand   (
	.din0	({1 {asi_error_inject}}		),
	.din1	(asi_error_mask			),
	.dout	(pre_error_inject_		)
);

mmu_mem_dp_inv_macro__width_1 pre_error_inject_inv  (
	.din	(pre_error_inject_		),
	.dout	(pre_error_inject		)
);

mmu_mem_dp_and_macro__width_1 error_inject_and  (
	.din0	(pre_error_inject		),
	.din1	({1 {mbist_run_}}		),
	.dout	(error_inject			)
);

mmu_mem_dp_and_macro__width_1 error_inject_b_and  (
	.din0	(pre_error_inject_		),
	.din1	({1 {mbist_run_}}		),
	.dout	(error_inject_			)
);

mmu_mem_dp_inv_macro__width_1 parity_in_b_inv  (
	.din	(parity_in			),
	.dout	(parity_in_			)
);

mmu_mem_dp_nand_macro__ports_2__width_1 parity_mux_0_nand   (
	.din0	(asi_mbist_ecc			),
	.din1	(asi_mbist_run			),
	.dout	(parity_mux_0			)
);

mmu_mem_dp_nand_macro__ports_2__width_1 parity_mux_1_nand   (
	.din0	(parity_in			),
	.din1	(error_inject_			),
	.dout	(parity_mux_1			)
);

mmu_mem_dp_nand_macro__ports_2__width_1 parity_mux_2_nand   (
	.din0	(parity_in_			),
	.din1	(error_inject			),
	.dout	(parity_mux_2			)
);

mmu_mem_dp_nand_macro__ports_3__width_1 parity_mux_nand   (
	.din0	(parity_mux_0			),
	.din1	(parity_mux_1			),
	.din2	(parity_mux_2			),
	.dout	(parity_out			)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

endmodule


//
//   invert macro
//
//


module mmu_mem_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_mem_dp_nand_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module mmu_mem_dp_and_macro__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_mem_dp_nand_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nand3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_sed_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_sed_dp (
  data_in, 
  ecc_in, 
  syndrome, 
  cecc_err, 
  uecc_err);
wire [66:0] d;
wire [7:0] e;
wire [36:0] check0_bus;
wire check0_4;
wire check0_3;
wire check0_2;
wire check0_1;
wire check0_0;
wire c0;
wire [36:0] check1_bus;
wire check1_4;
wire check1_3;
wire check1_2;
wire check1_1;
wire check1_0;
wire c1;
wire [35:0] check2_bus;
wire check2_4;
wire check2_3;
wire check2_2;
wire check2_1;
wire check2_0;
wire c2;
wire [34:0] check3_bus;
wire check3_4;
wire check3_3;
wire check3_2;
wire check3_1;
wire check3_0;
wire c3;
wire [31:0] check4_bus;
wire c4;
wire [31:0] check5_bus;
wire c5;
wire [10:0] check6_bus;
wire c6;
wire [73:0] check7_bus;
wire check7_4;
wire check7_3;
wire check7_2;
wire check7_1;
wire check7_0;
wire c7;
wire [7:7] e_;
wire c7_;
wire parity_incorrect;
wire parity_correct;
wire ecc_err_0;
wire ecc_err_1;
wire ecc_err_2;
wire ecc_err;


input	[66:0]	data_in;	// Used for generation and checking
input	[7:0]	ecc_in;		// Used for checking only

output	[7:0]	syndrome;	// Used for generation and checking
output		cecc_err;	// Used for checking only; unused for gen
output		uecc_err;	// Used for checking only; unused for gen


//////////////////////////////////////////////////////////////////////////////

// Position	Binary	
//	 1	0000001	C0
//	 2	0000010	C1
//	 3	0000011	D0
//
//	 4	0000100	C2
//	 5	0000101	D1
//	 6	0000110	D2
//	 7	0000111	D3
//			
//	 8 	0001000	C3
//	 9	0001001	D4
//	10	0001010	D5
//	11	0001011 D6
//	12	0001100	D7
//	...		...
//	15	0001111	D10
//			
//	16	0010000	C4
//	17	0010001	D11
//	...		...
//	20	0010100 D14
//	...		...
//	24	0011000	D18
//	...		...
//	28	0011100	D22
//	...		...
//	31	0011111	D25
//			
//	32	0100000	C5
//	33	0100001	D26
//	...		...
//	36	0100100	D29
//	...		...
//	40	0101000	D33
//	...		...
//	44	0101100	D37
//	...		...
//	48	0110000	D41
//	...		...
//	52	0110100	D45
//	...		...
//	56	0111000	D49
//	...		...
//	60	0111100	D53
//	...		...
//	63	0111111	D56
//			
//	64	1000000	C6
//	65	1000001	D57
//	...		...
//	68	1000100	D60
//	...		...
//	72	1001000	D64
//	73	1001001	D65
//	74	1001010	D66
//			
//	75	1001011	C7

assign d[66:0] = 
       data_in[66:0];
assign e[7:0] =
       ecc_in[7:0];


// All odd positions (LSB of position set)
assign check0_bus[36:0] = 
	{d[65], d[63], d[61], d[59], d[57], 
	 d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42], 
	 d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26], 
	 d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], 
	 d[10], d[8], d[6], d[4], 
	 d[3], d[1],
	 d[0], 
	 e[0]};

mmu_sed_dp_prty_macro__width_8 check0_4_pty  (
	.din	(check0_bus	[36:29]	),
	.dout	(check0_4		)
);

mmu_sed_dp_prty_macro__width_8 check0_3_pty  (
	.din	(check0_bus	[28:21]	),
	.dout	(check0_3		)
);

mmu_sed_dp_prty_macro__width_8 check0_2_pty  (
	.din	(check0_bus	[20:13]	),
	.dout	(check0_2		)
);

mmu_sed_dp_prty_macro__width_8 check0_1_pty  (
	.din	(check0_bus	[12:5]	),
	.dout	(check0_1		)
);

mmu_sed_dp_prty_macro__width_8 check0_0_pty  (
	.din	({check0_bus	[4:0],
		  {3 {1'b0}}	       }),
	.dout	(check0_0		)
);

mmu_sed_dp_prty_macro__width_8 check0_pty  (
	.din	({check0_4	       ,
		  check0_3	       ,
		  check0_2	       ,
		  check0_1	       ,
		  check0_0	       ,
		  {3 {1'b0}}	       }),
	.dout	(c0			)
);


// All positions with secondmost LSB set
assign check1_bus[36:0] =
       {d[66   ], d[63:62], d[59:58], 
        d[56:55], d[52:51], d[48:47], d[44:43],
        d[40:39], d[36:35], d[32:31], d[28:27],
        d[25:24], d[21:20], d[17:16], d[13:12],
        d[10:9], d[6:5], 
        d[3:2],
        d[0],
        e[1]};

mmu_sed_dp_prty_macro__width_8 check1_4_pty  (
	.din	(check1_bus	[36:29]	),
	.dout	(check1_4		)
);

mmu_sed_dp_prty_macro__width_8 check1_3_pty  (
	.din	(check1_bus	[28:21]	),
	.dout	(check1_3		)
);

mmu_sed_dp_prty_macro__width_8 check1_2_pty  (
	.din	(check1_bus	[20:13]	),
	.dout	(check1_2		)
);

mmu_sed_dp_prty_macro__width_8 check1_1_pty  (
	.din	(check1_bus	[12:5]	),
	.dout	(check1_1		)
);

mmu_sed_dp_prty_macro__width_8 check1_0_pty  (
	.din	({check1_bus	[4:0],
		  {3 {1'b0}}	       }),
	.dout	(check1_0		)
);

mmu_sed_dp_prty_macro__width_8 check1_pty  (
	.din	({check1_0	       ,
		  check1_1	       ,
		  check1_2	       ,
		  check1_3	       ,
		  check1_4	       ,
		  {3 {1'b0}}	       }),
	.dout	(c1			)
);


// All positions with thirdmost LSB set
assign check2_bus[35:0] =
       {d[63:60],
        d[56:53], d[48:45], d[40:37], d[32:29], 
        d[25:22], d[17:14],
        d[10:7],
        d[3:1],
	e[2]};

mmu_sed_dp_prty_macro__width_8 check2_4_pty  (
	.din	({1'b0,
		  check2_bus	[35:29]}),
	.dout	(check2_4		)
);

mmu_sed_dp_prty_macro__width_8 check2_3_pty  (
	.din	(check2_bus	[28:21]	),
	.dout	(check2_3		)
);

mmu_sed_dp_prty_macro__width_8 check2_2_pty  (
	.din	(check2_bus	[20:13]	),
	.dout	(check2_2		)
);

mmu_sed_dp_prty_macro__width_8 check2_1_pty  (
	.din	(check2_bus	[12:5]	),
	.dout	(check2_1		)
);

mmu_sed_dp_prty_macro__width_8 check2_0_pty  (
	.din	({check2_bus	[4:0],
		  {3 {1'b0}}	       }),
	.dout	(check2_0		)
);

mmu_sed_dp_prty_macro__width_8 check2_pty  (
	.din	({check2_0	       ,
		  check2_1	       ,
		  check2_2	       ,
		  check2_3	       ,
		  check2_4	       ,
		  {3 {1'b0}}	       }),
	.dout	(c2			)
);


// All positions with fourthmost LSB set
assign check3_bus[34:0] =
       {d[66:64],
        d[56:49], d[40:33], 
        d[25:18],
        d[10:4],
	e[3]};

mmu_sed_dp_prty_macro__width_8 check3_4_pty  (
	.din	({{2 {1'b0}}	       ,
		  check3_bus	[34:29]}),
	.dout	(check3_4		)
);

mmu_sed_dp_prty_macro__width_8 check3_3_pty  (
	.din	(check3_bus	[28:21]	),
	.dout	(check3_3		)
);

mmu_sed_dp_prty_macro__width_8 check3_2_pty  (
	.din	(check3_bus	[20:13]	),
	.dout	(check3_2		)
);

mmu_sed_dp_prty_macro__width_8 check3_1_pty  (
	.din	(check3_bus	[12:5]	),
	.dout	(check3_1		)
);

mmu_sed_dp_prty_macro__width_8 check3_0_pty  (
	.din	({check3_bus	[4:0],
		  {3 {1'b0}}	       }),
	.dout	(check3_0		)
);

mmu_sed_dp_prty_macro__width_8 check3_pty  (
	.din	({check3_0	       ,
		  check3_1	       ,
		  check3_2	       ,
		  check3_3	       ,
		  check3_4	       ,
		  {3 {1'b0}}	       }),
	.dout	(c3			)
);


// All positions with fifthmost LSB set
assign check4_bus[31:0] =
       {d[56:41],
        d[25:11],
	e[4]};

mmu_sed_dp_prty_macro__width_32 check4_pty  (
	.din	(check4_bus	[31:0]	),
	.dout	(c4			)
);


// All positions with sixthmost LSB set
assign check5_bus[31:0] =
       {d[56:26], 
	e[5]};

mmu_sed_dp_prty_macro__width_32 check5_pty  (
	.din	(check5_bus	[31:0]	),
	.dout	(c5			)
);


// All positions with seventhmost LSB set
assign check6_bus[10:0] =
       {d[66:57],
	e[6]};

mmu_sed_dp_prty_macro__width_16 check6_pty  (
	.din	({{5 {1'b0}}	       ,
		  check6_bus	[10:0]}),
	.dout	(c6			)
);


// Parity of the whole word (including ECC bits)
// Then xnor with e[07] to check the parity
// (or in this case, xor with e[07] to get miscompare)
assign check7_bus[73:0] =
      {d[66:0], e[6:0]};

mmu_sed_dp_prty_macro__width_8 check7_4_pty  (
	.din	(check7_bus	[71:64]	),
	.dout	(check7_4		)
);

mmu_sed_dp_prty_macro__width_16 check7_3_pty  (
	.din	(check7_bus	[63:48]	),
	.dout	(check7_3		)
);

mmu_sed_dp_prty_macro__width_16 check7_2_pty  (
	.din	(check7_bus	[47:32]	),
	.dout	(check7_2		)
);

mmu_sed_dp_prty_macro__width_16 check7_1_pty  (
	.din	(check7_bus	[31:16]	),
	.dout	(check7_1		)
);

mmu_sed_dp_prty_macro__width_16 check7_0_pty  (
	.din	(check7_bus	[15:0]	),
	.dout	(check7_0		)
);

mmu_sed_dp_prty_macro__width_8 check7_inv_pty  (
	.din	({e		[7   ],
		  check7_bus	[73:72],
		  check7_0	       ,
		  check7_1	       ,
		  check7_2	       ,
		  check7_3	       ,
		  check7_4	       }),
	.dout	(c7			)
);

mmu_sed_dp_inv_macro__width_1 e7_inv  (
	.din	(e		[7   ]	),
	.dout	(e_		[7   ]	)
);

mmu_sed_dp_prty_macro__width_8 check7_pty  (
	.din	({e_		[7   ],
		  check7_bus	[73:72],
		  check7_0	       ,
		  check7_1	       ,
		  check7_2	       ,
		  check7_3	       ,
		  check7_4	       }),
	.dout	(c7_			)
);

assign parity_incorrect =
       c7;

assign parity_correct =
       c7_;


assign syndrome[7:0] = 
       {c7, c6, c5, c4, c3, c2, c1, c0};


// If the syndrome is zero and overall parity is correct, then no errors

// If overall parity is incorrect, then correctable
//assign cecc_err =
//       c7;
// If overall parity is correct and the syndrome is nonzero, then uncorrectable
//assign uecc_err =
//       (| ecc_out[06:00]) & ~c7;

mmu_sed_dp_nor_macro__ports_3__width_1 ecc_err_2_nor   (
	.din0	(syndrome	[6]	),
	.din1	(syndrome	[5]	),
	.din2	(syndrome	[4]	),
	.dout	(ecc_err_0		)
);

mmu_sed_dp_nor_macro__ports_2__width_1 ecc_err_1_nor   (
	.din0	(syndrome	[3]	),
	.din1	(syndrome	[2]	),
	.dout	(ecc_err_1		)
);

mmu_sed_dp_nor_macro__ports_2__width_1 ecc_err_0_nor   (
	.din0	(syndrome	[1]	),
	.din1	(syndrome	[0]	),
	.dout	(ecc_err_2		)
);

mmu_sed_dp_nand_macro__ports_3__width_1 ecc_err_nand   (
	.din0	(ecc_err_0		),
	.din1	(ecc_err_1		),
	.din2	(ecc_err_2		),
	.dout	(ecc_err		)
);

mmu_sed_dp_buff_macro__width_1 cecc_err_buf  (
 	.din	(parity_incorrect	),
	.dout	(cecc_err		)
);

mmu_sed_dp_and_macro__ports_2__width_1 uecc_err_and   (
	.din0	(ecc_err		),
 	.din1	(parity_correct		),
	.dout	(uecc_err		)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

endmodule


//
//   parity macro (even parity)
//
//


module mmu_sed_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module mmu_sed_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module mmu_sed_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module mmu_sed_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module mmu_sed_dp_nor_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nor3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module mmu_sed_dp_nor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module mmu_sed_dp_nand_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nand3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module mmu_sed_dp_buff_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module mmu_sed_dp_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_seg_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_seg_dp (
  data_in, 
  ecc_out);
wire [66:0] d;
wire [35:0] check0_bus;
wire check0_3;
wire check0_2;
wire check0_1;
wire check0_0;
wire c0;
wire [35:0] check1_bus;
wire check1_3;
wire check1_2;
wire check1_1;
wire check1_0;
wire c1;
wire [34:0] check2_bus;
wire check2_3;
wire check2_2;
wire check2_1;
wire check2_0;
wire c2;
wire [33:0] check3_bus;
wire check3_3;
wire check3_2;
wire check3_1;
wire check3_0;
wire c3;
wire [30:0] check4_bus;
wire c4;
wire [30:0] check5_bus;
wire c5;
wire [9:0] check6_bus;
wire c6;
wire [35:0] check7_bus;
wire check7_3;
wire check7_2;
wire check7_1;
wire check7_0;
wire c7;


input	[66:0]	data_in;	// Used for generation and checking

output	[7:0]	ecc_out;	// Used for generation and checking


//////////////////////////////////////////////////////////////////////////////

// Position	Binary	
//	 1	0000001	C0
//	 2	0000010	C1
//	 3	0000011	D0
//
//	 4	0000100	C2
//	 5	0000101	D1
//	 6	0000110	D2
//	 7	0000111	D3
//			
//	 8 	0001000	C3
//	 9	0001001	D4
//	10	0001010	D5
//	11	0001011 D6
//	12	0001100	D7
//	...		...
//	15	0001111	D10
//			
//	16	0010000	C4
//	17	0010001	D11
//	...		...
//	20	0010100 D14
//	...		...
//	24	0011000	D18
//	...		...
//	28	0011100	D22
//	...		...
//	31	0011111	D25
//			
//	32	0100000	C5
//	33	0100001	D26
//	...		...
//	36	0100100	D29
//	...		...
//	40	0101000	D33
//	...		...
//	44	0101100	D37
//	...		...
//	48	0110000	D41
//	...		...
//	52	0110100	D45
//	...		...
//	56	0111000	D49
//	...		...
//	60	0111100	D53
//	...		...
//	63	0111111	D56
//			
//	64	1000000	C6
//	65	1000001	D57
//	...		...
//	68	1000100	D60
//	...		...
//	72	1001000	D64
//	73	1001001	D65
//	74	1001010	D66
//			
//	75	1001011	C7

assign d[66:0] = 
       data_in[66:0];


// All odd positions (LSB of position set)
assign check0_bus[35:0] = 
	{d[65], d[63], d[61], d[59], d[57], 
	 d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42], 
	 d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26], 
	 d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], 
	 d[10], d[8], d[6], d[4], 
	 d[3], d[1],
	 d[0]};

mmu_seg_dp_prty_macro__width_8 check0_3_pty  (
	.din	(check0_bus	[31:24]	),
	.dout	(check0_3		)
);

mmu_seg_dp_prty_macro__width_8 check0_2_pty  (
	.din	(check0_bus	[23:16]	),
	.dout	(check0_2		)
);

mmu_seg_dp_prty_macro__width_8 check0_1_pty  (
	.din	(check0_bus	[15:8]	),
	.dout	(check0_1		)
);

mmu_seg_dp_prty_macro__width_8 check0_0_pty  (
	.din	(check0_bus	[7:0]	),
	.dout	(check0_0		)
);

mmu_seg_dp_prty_macro__width_8 check0_pty  (
	.din	({check0_bus	[35:32],
		  check0_3	       ,
		  check0_2	       ,
		  check0_1	       ,
		  check0_0	       }),
	.dout	(c0			)
);


// All positions with secondmost LSB set
assign check1_bus[35:0] =
       {d[66   ], d[63:62], d[59:58], 
        d[56:55], d[52:51], d[48:47], d[44:43],
        d[40:39], d[36:35], d[32:31], d[28:27],
        d[25:24], d[21:20], d[17:16], d[13:12],
        d[10:9], d[6:5], 
        d[3:2],
        d[0]};

mmu_seg_dp_prty_macro__width_8 check1_3_pty  (
	.din	(check1_bus	[31:24]	),
	.dout	(check1_3		)
);

mmu_seg_dp_prty_macro__width_8 check1_2_pty  (
	.din	(check1_bus	[23:16]	),
	.dout	(check1_2		)
);

mmu_seg_dp_prty_macro__width_8 check1_1_pty  (
	.din	(check1_bus	[15:8]	),
	.dout	(check1_1		)
);

mmu_seg_dp_prty_macro__width_8 check1_0_pty  (
	.din	(check1_bus	[7:0]	),
	.dout	(check1_0		)
);

mmu_seg_dp_prty_macro__width_8 check1_pty  (
	.din	({check1_bus	[35:32],
		  check1_3	       ,
		  check1_2	       ,
		  check1_1	       ,
		  check1_0	       }),
	.dout	(c1			)
);


// All positions with thirdmost LSB set
assign check2_bus[34:0] =
       {d[63:60],
        d[56:53], d[48:45], d[40:37], d[32:29], 
        d[25:22], d[17:14],
        d[10:7],
        d[3:1]};

mmu_seg_dp_prty_macro__width_8 check2_3_pty  (
	.din	(check2_bus	[31:24]	),
	.dout	(check2_3		)
);

mmu_seg_dp_prty_macro__width_8 check2_2_pty  (
	.din	(check2_bus	[23:16]	),
	.dout	(check2_2		)
);

mmu_seg_dp_prty_macro__width_8 check2_1_pty  (
	.din	(check2_bus	[15:8]	),
	.dout	(check2_1		)
);

mmu_seg_dp_prty_macro__width_8 check2_0_pty  (
	.din	(check2_bus	[7:0]	),
	.dout	(check2_0		)
);

mmu_seg_dp_prty_macro__width_8 check2_pty  (
	.din	({{1 {1'b0}}	       ,
		  check2_bus	[34:32],
		  check2_3	       ,
		  check2_2	       ,
		  check2_1	       ,
		  check2_0	       }),
	.dout	(c2			)
);


// All positions with fourthmost LSB set
assign check3_bus[33:0] =
       {d[66:64],
        d[56:49], d[40:33], 
        d[25:18],
        d[10:4]};

mmu_seg_dp_prty_macro__width_8 check3_3_pty  (
	.din	(check3_bus	[31:24]	),
	.dout	(check3_3		)
);

mmu_seg_dp_prty_macro__width_8 check3_2_pty  (
	.din	(check3_bus	[23:16]	),
	.dout	(check3_2		)
);

mmu_seg_dp_prty_macro__width_8 check3_1_pty  (
	.din	(check3_bus	[15:8]	),
	.dout	(check3_1		)
);

mmu_seg_dp_prty_macro__width_8 check3_0_pty  (
	.din	(check3_bus	[7:0]	),
	.dout	(check3_0		)
);

mmu_seg_dp_prty_macro__width_8 check3_pty  (
	.din	({{2 {1'b0}}	       ,
		  check3_bus	[33:32],
		  check3_3	       ,
		  check3_2	       ,
		  check3_1	       ,
		  check3_0	       }),
	.dout	(c3			)
);


// All positions with fifthmost LSB set
assign check4_bus[30:0] =
       {d[56:41],
        d[25:11]};

mmu_seg_dp_prty_macro__width_32 check4_pty  (
	.din	({{1 {1'b0}}	       ,
		  check4_bus	[30:0]}),
	.dout	(c4			)
);


// All positions with sixthmost LSB set
assign check5_bus[30:0] =
       {d[56:26]};

mmu_seg_dp_prty_macro__width_32 check5_pty  (
	.din	({{1 {1'b0}}	       ,
		  check5_bus	[30:0]}),
	.dout	(c5			)
);


// All positions with seventhmost LSB set
assign check6_bus[9:0] =
       {d[66:57]};

mmu_seg_dp_prty_macro__width_16 check6_pty  (
	.din	({{6 {1'b0}}	       ,
		  check6_bus	[9:0]}),
	.dout	(c6			)
);


// Parity of the whole word (including check bits)
//assign check7_bus[73:00] =
//      {d[66:00], c0, c1, c2, c3, c4, c5, c6};
// But in generation this simplifies to
//	(all d bits with even parity binary positions)

assign check7_bus[35:0] =
//	  72     71     68     66     65     63     60     58     57
       {d[64], d[63], d[60], d[58], d[57], d[56], d[53], d[51], d[50],
//        54     53     51     48     46     45     43     40     39     
	d[47], d[46], d[44], d[41], d[39], d[38], d[36], d[33], d[32],
//	  36     34     33     30     29     27     24     23     20
	d[29], d[27], d[26], d[24], d[23], d[21], d[18], d[17], d[14],
//        18     17     15     12     10      9      6      5      3
	d[12], d[11], d[10], d[7], d[5], d[4], d[2], d[1], d[0]};

mmu_seg_dp_prty_macro__width_8 check7_3_pty  (
	.din	(check7_bus	[31:24]	),
	.dout	(check7_3		)
);

mmu_seg_dp_prty_macro__width_8 check7_2_pty  (
	.din	(check7_bus	[23:16]	),
	.dout	(check7_2		)
);

mmu_seg_dp_prty_macro__width_8 check7_1_pty  (
	.din	(check7_bus	[15:8]	),
	.dout	(check7_1		)
);

mmu_seg_dp_prty_macro__width_8 check7_0_pty  (
	.din	(check7_bus	[7:0]	),
	.dout	(check7_0		)
);

mmu_seg_dp_prty_macro__width_8 check7_pty  (
	.din	({check7_bus	[35:32],
		  check7_3	       ,
		  check7_2	       ,
		  check7_1	       ,
		  check7_0	       }),
	.dout	(c7			)
);

assign ecc_out[7:0] = 
       {c7, c6, c5, c4, c3, c2, c1, c0};


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

endmodule


//
//   parity macro (even parity)
//
//


module mmu_seg_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module mmu_seg_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module mmu_seg_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_sel_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_sel_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tlu_cerer_scac, 
  tlu_cerer_scau, 
  asi_sel_en, 
  asi_rd_scp0, 
  sed_syndrome, 
  scp0_ecc, 
  scp1_ecc, 
  sed_cecc_err, 
  sed_uecc_err, 
  scan_out, 
  sel_syndrome, 
  sel_crit_ecc, 
  sel_scac, 
  sel_scau);
wire pce_ov;
wire clk;
wire stop;
wire siclk;
wire soclk;
wire se;
wire en;
wire [7:0] rd_ecc_in;
wire ecc_lat_scanin;
wire ecc_lat_scanout;
wire scac_in;
wire scau_in;
wire [7:0] rd_ecc;
wire scac;
wire scau;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input		tlu_cerer_scac;
input		tlu_cerer_scau;

input		asi_sel_en;
input		asi_rd_scp0;

input	[7:0]	sed_syndrome;

input	[7:0]	scp0_ecc;
input	[7:0]	scp1_ecc;

input		sed_cecc_err;
input		sed_uecc_err;


output		scan_out;

output	[7:0]	sel_syndrome;
output	[7:0]	sel_crit_ecc;

output		sel_scac;
output		sel_scau;


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign clk      = l2clk;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;
assign en       = asi_sel_en;


// Data is flopped, but ECC is not...  so mux and flop here

mmu_sel_dp_mux_macro__mux_aope__ports_2__width_8 rd_ecc_in_mux    (
	.din0	(scp0_ecc		[7:0]	),
	.din1	(scp1_ecc		[7:0]	),
	.sel0	(asi_rd_scp0			),
	.dout	(rd_ecc_in		[7:0]	)
);

mmu_sel_dp_msff_macro__width_18 ecc_lat  (
	.scan_in(ecc_lat_scanin),
	.scan_out(ecc_lat_scanout),
	.din	({rd_ecc_in		[7:0],
		  scac_in		       ,
		  scau_in		       ,
		  sed_syndrome		[7:0]}),
	.dout	({rd_ecc		[7:0],
		  scac			       ,
		  scau			       ,
		  sel_syndrome		[7:0]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign sel_crit_ecc[7:0] =
       rd_ecc[7:0];


// Qualify error signals

mmu_sel_dp_and_macro__ports_2__width_1 scac_in_and   (
	.din0	(sed_cecc_err			),
	.din1	(tlu_cerer_scac			),
	.dout	(scac_in			)
);

mmu_sel_dp_and_macro__ports_2__width_1 scau_in_and   (
	.din0	(sed_uecc_err			),
	.din1	(tlu_cerer_scau			),
	.dout	(scau_in			)
);

assign sel_scac =
       scac;

assign sel_scau =
       scau;


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

// fixscan start:
assign ecc_lat_scanin            = scan_in                  ;
assign scan_out                  = ecc_lat_scanout          ;
// fixscan end:
endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module mmu_sel_dp_mux_macro__mux_aope__ports_2__width_8 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [7:0] din0;
  input [7:0] din1;
  input sel0;
  output [7:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_sel_dp_msff_macro__width_18 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [16:0] so;

  input [17:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [17:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(18)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[17:0]),
.si({scan_in,so[16:0]}),
.so({so[16:0],scan_out}),
.q(dout[17:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module mmu_sel_dp_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_tmc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_tmc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  htc_data_rcvd_hw1, 
  htc_tlb_miss_m, 
  htc_tsb_done_hw2, 
  htc_vld_tsbptr_m2, 
  htc_thr_valid_m1, 
  htc_thr_valid_m0, 
  htc_hwtw_burst, 
  htc_cindex_bit0, 
  htc_cindex_bit1, 
  trs_eperr_st, 
  trs_eccerr_st, 
  tsm_tsb_miss_hw2, 
  tsm_rqv, 
  tsm_waitfortte, 
  scan_out);
wire pce_ov;
wire stop;
wire se;
wire siclk;
wire soclk;
wire l1clk;
wire tsm0_scanin;
wire tsm0_scanout;
wire tsm1_scanin;
wire tsm1_scanout;
wire tsm2_scanin;
wire tsm2_scanout;
wire tsm3_scanin;
wire tsm3_scanout;
wire tsm4_scanin;
wire tsm4_scanout;
wire tsm5_scanin;
wire tsm5_scanout;
wire tsm6_scanin;
wire tsm6_scanout;
wire tsm7_scanin;
wire tsm7_scanout;
wire spares_scanin;
wire spares_scanout;


input           l2clk;
input           scan_in;
input           tcu_pce_ov;               // scan signals
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input [7:0]     htc_data_rcvd_hw1;
input [7:0]     htc_tlb_miss_m;
input [7:0]     htc_tsb_done_hw2;
input [7:0]     htc_vld_tsbptr_m2;
input [7:0]     htc_thr_valid_m1;
input [7:0]     htc_thr_valid_m0;
input [7:0]     htc_hwtw_burst;

input [7:0]     htc_cindex_bit0;
input [7:0]     htc_cindex_bit1;


input [7:0]     trs_eperr_st;

input [7:0]     trs_eccerr_st;

output [7:0]    tsm_tsb_miss_hw2;
output [7:0]    tsm_rqv;

output [7:0]    tsm_waitfortte;

output          scan_out;

assign pce_ov   = tcu_pce_ov;
assign stop = 1'b0;
assign se       = tcu_scan_en;

assign siclk	= spc_aclk;
assign soclk	= spc_bclk;


///////////////////////////////////////////////////
// clock header
///////////////////////////////////////////////////
mmu_tmc_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


/* mmu_tsm_ctl  AUTO_TEMPLATE
 (
.tlb_miss_m(htc_tlb_miss_m[@]),
.cindex_bit0(htc_cindex_bit0[@]),
.cindex_bit1(htc_cindex_bit1[@]),

.data_rcvd_hw1(htc_data_rcvd_hw1[@]),
.thr_valid_m1(htc_thr_valid_m1[@]),
.thr_valid_m0(htc_thr_valid_m0[@]),
.hwtw_burst(htc_hwtw_burst[@]),
.tsb_done_hw2(htc_tsb_done_hw2[@]),
.tsb_vld_tsbptr_m2(htc_vld_tsbptr_m2[@]),

.tsm_tsb_miss_hw2(tsm_tsb_miss_hw2[@]),
.tsm_rqv(tsm_rqv[@]),
.tsm_waitfortte(tsm_waitfortte[@]),
.trs_eperr_st(trs_eperr_st[@]),
.trs_eccerr_st(trs_eccerr_st[@]));
 */

mmu_tsm_ctl tsm0 (/*AUTOINST*/
                  // Outputs
                  .tsm_tsb_miss_hw2     (tsm_tsb_miss_hw2[0]),   // Templated
                  .tsm_rqv              (tsm_rqv[0]),            // Templated
                  .tsm_waitfortte       (tsm_waitfortte[0]),     // Templated
                  // Inputs
                  .scan_in(tsm0_scanin),
                  .scan_out(tsm0_scanout),
                  .l1clk                (l1clk),
                  .data_rcvd_hw1        (htc_data_rcvd_hw1[0]),  // Templated
                  .thr_valid_m1         (htc_thr_valid_m1[0]),  // Templated
                  .thr_valid_m0         (htc_thr_valid_m0[0]),  // Templated
                  .hwtw_burst           (htc_hwtw_burst[0]),    // Templated
                  .tlb_miss_m           (htc_tlb_miss_m[0]),     // Templated
                  .cindex_bit0          (htc_cindex_bit0[0]),    // Templated
                  .cindex_bit1          (htc_cindex_bit1[0]),    // Templated
                  .tsb_done_hw2          (htc_tsb_done_hw2[0]),    // Templated
                  .vld_tsbptr_m2        (htc_vld_tsbptr_m2[0]),    // Templated
                  .trs_eperr_st         (trs_eperr_st[0]),     // Templated
                  .trs_eccerr_st        (trs_eccerr_st[0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

mmu_tsm_ctl tsm1 (/*AUTOINST*/
                  // Outputs
                  .tsm_tsb_miss_hw2     (tsm_tsb_miss_hw2[1]),   // Templated
                  .tsm_rqv              (tsm_rqv[1]),            // Templated
                  .tsm_waitfortte       (tsm_waitfortte[1]),     // Templated
                  // Inputs
                  .scan_in(tsm1_scanin),
                  .scan_out(tsm1_scanout),
                  .l1clk                (l1clk),
                  .data_rcvd_hw1        (htc_data_rcvd_hw1[1]),  // Templated
                  .thr_valid_m1         (htc_thr_valid_m1[1]),  // Templated
                  .thr_valid_m0         (htc_thr_valid_m0[1]),  // Templated
                  .hwtw_burst       (htc_hwtw_burst[1]),    // Templated
                  .tlb_miss_m           (htc_tlb_miss_m[1]),     // Templated
                  .cindex_bit0          (htc_cindex_bit0[1]),    // Templated
                  .cindex_bit1          (htc_cindex_bit1[1]),    // Templated
                  .tsb_done_hw2          (htc_tsb_done_hw2[1]),    // Templated
                  .vld_tsbptr_m2        (htc_vld_tsbptr_m2[1]),    // Templated
                  .trs_eperr_st         (trs_eperr_st[1]),     // Templated
                  .trs_eccerr_st        (trs_eccerr_st[1]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

mmu_tsm_ctl tsm2 (/*AUTOINST*/
                  // Outputs
                  .tsm_tsb_miss_hw2     (tsm_tsb_miss_hw2[2]),   // Templated
                  .tsm_rqv              (tsm_rqv[2]),            // Templated
                  .tsm_waitfortte       (tsm_waitfortte[2]),     // Templated
                  // Inputs
                  .scan_in(tsm2_scanin),
                  .scan_out(tsm2_scanout),
                  .l1clk                (l1clk),
                  .data_rcvd_hw1        (htc_data_rcvd_hw1[2]),  // Templated
                  .thr_valid_m1         (htc_thr_valid_m1[2]),  // Templated
                  .thr_valid_m0         (htc_thr_valid_m0[2]),  // Templated
                  .hwtw_burst       (htc_hwtw_burst[2]),    // Templated
                  .tlb_miss_m           (htc_tlb_miss_m[2]),     // Templated
                  .cindex_bit0          (htc_cindex_bit0[2]),    // Templated
                  .cindex_bit1          (htc_cindex_bit1[2]),    // Templated
                  .tsb_done_hw2          (htc_tsb_done_hw2[2]),    // Templated
                  .vld_tsbptr_m2        (htc_vld_tsbptr_m2[2]),    // Templated
                  .trs_eperr_st         (trs_eperr_st[2]),     // Templated
                  .trs_eccerr_st        (trs_eccerr_st[2]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

mmu_tsm_ctl tsm3 (/*AUTOINST*/
                  // Outputs
                  .tsm_tsb_miss_hw2     (tsm_tsb_miss_hw2[3]),   // Templated
                  .tsm_rqv              (tsm_rqv[3]),            // Templated
                  .tsm_waitfortte       (tsm_waitfortte[3]),     // Templated
                  // Inputs
                  .scan_in(tsm3_scanin),
                  .scan_out(tsm3_scanout),
                  .l1clk                (l1clk),
                  .data_rcvd_hw1        (htc_data_rcvd_hw1[3]),  // Templated
                  .thr_valid_m1         (htc_thr_valid_m1[3]),  // Templated
                  .thr_valid_m0         (htc_thr_valid_m0[3]),  // Templated
                  .hwtw_burst       (htc_hwtw_burst[3]),    // Templated
                  .tlb_miss_m           (htc_tlb_miss_m[3]),     // Templated
                  .cindex_bit0          (htc_cindex_bit0[3]),    // Templated
                  .cindex_bit1          (htc_cindex_bit1[3]),    // Templated
                  .tsb_done_hw2          (htc_tsb_done_hw2[3]),    // Templated
                  .vld_tsbptr_m2        (htc_vld_tsbptr_m2[3]),    // Templated
                  .trs_eperr_st         (trs_eperr_st[3]),     // Templated
                  .trs_eccerr_st        (trs_eccerr_st[3]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

mmu_tsm_ctl tsm4 (/*AUTOINST*/
                  // Outputs
                  .tsm_tsb_miss_hw2     (tsm_tsb_miss_hw2[4]),   // Templated
                  .tsm_rqv              (tsm_rqv[4]),            // Templated
                  .tsm_waitfortte       (tsm_waitfortte[4]),     // Templated
                  // Inputs
                  .scan_in(tsm4_scanin),
                  .scan_out(tsm4_scanout),
                  .l1clk                (l1clk),
                  .data_rcvd_hw1        (htc_data_rcvd_hw1[4]),  // Templated
                  .thr_valid_m1         (htc_thr_valid_m1[4]),  // Templated
                  .thr_valid_m0         (htc_thr_valid_m0[4]),  // Templated
                  .hwtw_burst       (htc_hwtw_burst[4]),    // Templated
                  .tlb_miss_m           (htc_tlb_miss_m[4]),     // Templated
                  .cindex_bit0          (htc_cindex_bit0[4]),    // Templated
                  .cindex_bit1          (htc_cindex_bit1[4]),    // Templated
                  .tsb_done_hw2          (htc_tsb_done_hw2[4]),    // Templated
                  .vld_tsbptr_m2        (htc_vld_tsbptr_m2[4]),    // Templated

                  .trs_eperr_st         (trs_eperr_st[4]),     // Templated
                  .trs_eccerr_st        (trs_eccerr_st[4]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

mmu_tsm_ctl tsm5 (/*AUTOINST*/
                  // Outputs
                  .tsm_tsb_miss_hw2     (tsm_tsb_miss_hw2[5]),   // Templated
                  .tsm_rqv              (tsm_rqv[5]),            // Templated
                  .tsm_waitfortte       (tsm_waitfortte[5]),     // Templated
                  // Inputs
                  .scan_in(tsm5_scanin),
                  .scan_out(tsm5_scanout),
                  .l1clk                (l1clk),
                  .data_rcvd_hw1        (htc_data_rcvd_hw1[5]),  // Templated
                  .thr_valid_m1         (htc_thr_valid_m1[5]),  // Templated
                  .thr_valid_m0         (htc_thr_valid_m0[5]),  // Templated
                  .hwtw_burst       (htc_hwtw_burst[5]),    // Templated
                  .tlb_miss_m           (htc_tlb_miss_m[5]),     // Templated
                  .cindex_bit0          (htc_cindex_bit0[5]),    // Templated
                  .cindex_bit1          (htc_cindex_bit1[5]),    // Templated
                  .tsb_done_hw2          (htc_tsb_done_hw2[5]),    // Templated
                  .vld_tsbptr_m2        (htc_vld_tsbptr_m2[5]),    // Templated

                  .trs_eperr_st         (trs_eperr_st[5]),     // Templated
                  .trs_eccerr_st        (trs_eccerr_st[5]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

mmu_tsm_ctl tsm6 (/*AUTOINST*/
                  // Outputs
                  .tsm_tsb_miss_hw2     (tsm_tsb_miss_hw2[6]),   // Templated
                  .tsm_rqv              (tsm_rqv[6]),            // Templated
                  .tsm_waitfortte       (tsm_waitfortte[6]),     // Templated
                  // Inputs
                  .scan_in(tsm6_scanin),
                  .scan_out(tsm6_scanout),
                  .l1clk                (l1clk),
                  .data_rcvd_hw1        (htc_data_rcvd_hw1[6]),  // Templated
                  .thr_valid_m1         (htc_thr_valid_m1[6]),  // Templated
                  .thr_valid_m0         (htc_thr_valid_m0[6]),  // Templated
                  .hwtw_burst       (htc_hwtw_burst[6]),    // Templated
                  .tlb_miss_m           (htc_tlb_miss_m[6]),     // Templated
                  .cindex_bit0          (htc_cindex_bit0[6]),    // Templated
                  .cindex_bit1          (htc_cindex_bit1[6]),    // Templated
                  .tsb_done_hw2          (htc_tsb_done_hw2[6]),    // Templated
                  .vld_tsbptr_m2        (htc_vld_tsbptr_m2[6]),    // Templated
                  .trs_eperr_st         (trs_eperr_st[6]),     // Templated
                  .trs_eccerr_st        (trs_eccerr_st[6]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

mmu_tsm_ctl tsm7 (/*AUTOINST*/
                  // Outputs
                  .tsm_tsb_miss_hw2     (tsm_tsb_miss_hw2[7]),   // Templated
                  .tsm_rqv              (tsm_rqv[7]),            // Templated
                  .tsm_waitfortte       (tsm_waitfortte[7]),     // Templated
                  // Inputs
                  .scan_in(tsm7_scanin),
                  .scan_out(tsm7_scanout),
                  .l1clk                (l1clk),
                  .data_rcvd_hw1        (htc_data_rcvd_hw1[7]),  // Templated
                  .thr_valid_m1         (htc_thr_valid_m1[7]),  // Templated
                  .thr_valid_m0         (htc_thr_valid_m0[7]),  // Templated
                  .hwtw_burst       (htc_hwtw_burst[7]),    // Templated
                  .tlb_miss_m           (htc_tlb_miss_m[7]),     // Templated
                  .cindex_bit0          (htc_cindex_bit0[7]),    // Templated
                  .cindex_bit1          (htc_cindex_bit1[7]),    // Templated
                  .tsb_done_hw2          (htc_tsb_done_hw2[7]),    // Templated
                  .vld_tsbptr_m2        (htc_vld_tsbptr_m2[7]),    // Templated
                  .trs_eperr_st         (trs_eperr_st[7]),     // Templated
                  .trs_eccerr_st        (trs_eccerr_st[7]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));      // Templated

////////////////////////////////////////////////////////
// SPARE CELLS
////////////////////////////////////////////////////////
mmu_tmc_ctl_spare_ctl_macro__num_3 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
////////////////////////////////////////////////////////

// fixscan start:
assign tsm0_scanin               = scan_in                  ;
assign tsm1_scanin               = tsm0_scanout             ;
assign tsm2_scanin               = tsm1_scanout             ;
assign tsm3_scanin               = tsm2_scanout             ;
assign tsm4_scanin               = tsm3_scanout             ;
assign tsm5_scanin               = tsm4_scanout             ;
assign tsm6_scanin               = tsm5_scanout             ;
assign tsm7_scanin               = tsm6_scanout             ;
assign spares_scanin             = tsm7_scanout             ;
assign scan_out                  = spares_scanout           ;

// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


// any PARAMS parms go into naming of macro

module mmu_tmc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_tmc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_tmc_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module mmu_tmc_ctl_spare_ctl_macro__num_3 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));
assign scan_out = so_2;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_trc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_trc_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  htc_tsb_hit_hw1, 
  htc_thr_valid_hw3, 
  htc_ra2pahit_hw5, 
  htc_ranotpax_hw5, 
  tsm_waitfortte, 
  htc_ep_miss_hw1, 
  htc_rrindex_bit0, 
  htc_rrindex_bit1, 
  l2_ecc_err_hw1, 
  cfg_ecc_err_m3, 
  rr_ecc_err_hw5, 
  l2_ecc_err_type, 
  cfg_ecc_err_type, 
  rr_ecc_err_type, 
  cfg_ecc_err_index, 
  rr_ecc_err_index, 
  trs_rqv, 
  trs_null_st, 
  trs_waitrr3_st, 
  trs_ep_err, 
  trs_ecc_err, 
  trs0_err_type, 
  trs1_err_type, 
  trs2_err_type, 
  trs3_err_type, 
  trs4_err_type, 
  trs5_err_type, 
  trs6_err_type, 
  trs7_err_type, 
  trs0_err_index, 
  trs1_err_index, 
  trs2_err_index, 
  trs3_err_index, 
  trs4_err_index, 
  trs5_err_index, 
  trs6_err_index, 
  trs7_err_index, 
  trs_eccerr_st, 
  trs_eperr_st, 
  scan_out);
wire pce_ov;
wire stop;
wire se;
wire siclk;
wire soclk;
wire l1clk;
wire trs0_scanin;
wire trs0_scanout;
wire trs1_scanin;
wire trs1_scanout;
wire trs2_scanin;
wire trs2_scanout;
wire trs3_scanin;
wire trs3_scanout;
wire trs4_scanin;
wire trs4_scanout;
wire trs5_scanin;
wire trs5_scanout;
wire trs6_scanin;
wire trs6_scanout;
wire trs7_scanin;
wire trs7_scanout;
wire spares_scanin;
wire spares_scanout;


input           l2clk;
input           scan_in;
input           tcu_pce_ov;               // scan signals
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;


input [7:0]     htc_tsb_hit_hw1;
input [7:0]     htc_thr_valid_hw3;
input [7:0]     htc_ra2pahit_hw5;
input [7:0]     htc_ranotpax_hw5;
input [7:0]     tsm_waitfortte;
input [7:0]     htc_ep_miss_hw1;
input [7:0]     htc_rrindex_bit0;
input [7:0]     htc_rrindex_bit1;


input [7:0]     l2_ecc_err_hw1;
input [7:0]     cfg_ecc_err_m3;
input [7:0]     rr_ecc_err_hw5;

input [1:0]     l2_ecc_err_type;
input [1:0]     cfg_ecc_err_type;
input [1:0]     rr_ecc_err_type;

input [2:0]     cfg_ecc_err_index;
input [2:0]     rr_ecc_err_index;


output [7:0]    trs_rqv;
output [7:0]    trs_null_st;
output [7:0]    trs_waitrr3_st;
output [7:0]    trs_ep_err;
output [7:0]    trs_ecc_err;
output [2:0]    trs0_err_type;
output [2:0]    trs1_err_type;
output [2:0]    trs2_err_type;
output [2:0]    trs3_err_type;
output [2:0]    trs4_err_type;
output [2:0]    trs5_err_type;
output [2:0]    trs6_err_type;
output [2:0]    trs7_err_type;
output [2:0]    trs0_err_index;
output [2:0]    trs1_err_index;
output [2:0]    trs2_err_index;
output [2:0]    trs3_err_index;
output [2:0]    trs4_err_index;
output [2:0]    trs5_err_index;
output [2:0]    trs6_err_index;
output [2:0]    trs7_err_index;

output [7:0]    trs_eccerr_st;
output [7:0]    trs_eperr_st;

output          scan_out;

assign pce_ov   = tcu_pce_ov;
assign stop = 1'b0;
assign se       = tcu_scan_en;

assign siclk	= spc_aclk;
assign soclk	= spc_bclk;


///////////////////////////////////////////////////
// clock header
///////////////////////////////////////////////////
mmu_trc_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (1'b1),
 .l1clk(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


/* 
// mmu_trs_ctl  AUTO_TEMPLATE
 (
 .ep_miss_hw1(htc_ep_miss_hw1[@]),
 .rrindex_bit0(htc_rrindex_bit0[@]),
 .rrindex_bit1(htc_rrindex_bit1[@]),
 .l2_ecc_err_hw1(l2_ecc_err_hw1[@]),
 .cfg_ecc_err_m3(cfg_ecc_err_m3[@]),
 .rr_ecc_err_hw5(rr_ecc_err_hw5[@]),
.tsb_hit_hw1(htc_tsb_hit_hw1[@]),
.thr_valid_hw3(htc_thr_valid_hw3[@]),
.tsm_waitfortte(tsm_waitfortte[@]),
.ra2pahit_hw5(htc_ra2pahit_hw5[@]),
.ranotpax_hw5(htc_ranotpax_hw5[@]),
.trs_null_st(trs_null_st[@]),
.trs_waitrr3_st(trs_waitrr3_st[@]),
.trs_rqv(trs_rqv[@]),
.trs_ecc_err(trs_ecc_err[@]),
.trs_ep_err(trs_ecc_err[@]),
.trs_err_type(trs@_err_type[2:0]),
.trs_err_index(trs@_err_index[2:0]),
.trs_eperr_st (trs_eperr_st[@]),
.trs_eccerr_st (trs_eccerr_st[@]),
);
 */

mmu_trs_ctl trs0 (
                  /*AUTOINST*/
                  // Outputs
                  .trs_rqv              (trs_rqv[0]),            // Templated
                  .trs_null_st          (trs_null_st[0]),        // Templated
                  .trs_waitrr3_st       (trs_waitrr3_st[0]),        // Templated
                  .trs_ecc_err          (trs_ecc_err[0]),        // Templated
                  .trs_err_type         (trs0_err_type[2:0]),    // Templated
                  .trs_err_index        (trs0_err_index[2:0]),   // Templated
                  .trs_ep_err           (trs_ep_err[0]),      // Templated
                  .trs_eperr_st         (trs_eperr_st[0]),      // Templated
                  .trs_eccerr_st        (trs_eccerr_st[0]),      // Templated
                  // Inputs
                  .scan_in(trs0_scanin),
                  .scan_out(trs0_scanout),
                  .l1clk                (l1clk),
                  .tsb_hit_hw1          (htc_tsb_hit_hw1[0]),    // Templated
                  .thr_valid_hw3         (htc_thr_valid_hw3[0]),   // Templated
                  .ra2pahit_hw5         (htc_ra2pahit_hw5[0]),   // Templated
                  .ranotpax_hw5         (htc_ranotpax_hw5[0]),   // Templated
                  .tsm_waitfortte       (tsm_waitfortte[0]),     // Templated
                  .ep_miss_hw1          (htc_ep_miss_hw1[0]),     // Templated
                  .rrindex_bit0         (htc_rrindex_bit0[0]),     // Templated
                  .rrindex_bit1         (htc_rrindex_bit1[0]),     // Templated
                  .l2_ecc_err_hw1       (l2_ecc_err_hw1[0]),     // Templated
                  .cfg_ecc_err_m3       (cfg_ecc_err_m3[0]),     // Templated
                  .rr_ecc_err_hw5       (rr_ecc_err_hw5[0]),     // Templated
                  .l2_ecc_err_type      (l2_ecc_err_type[1:0]),
                  .cfg_ecc_err_type     (cfg_ecc_err_type[1:0]),
                  .rr_ecc_err_type      (rr_ecc_err_type[1:0]),
                  .cfg_ecc_err_index    (cfg_ecc_err_index[2:0]),
                  .rr_ecc_err_index     (rr_ecc_err_index[2:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));

mmu_trs_ctl trs1 (/*AUTOINST*/
                  // Outputs
                  .trs_rqv              (trs_rqv[1]),            // Templated
                  .trs_null_st          (trs_null_st[1]),        // Templated
                  .trs_waitrr3_st       (trs_waitrr3_st[1]),        // Templated
                  .trs_ecc_err          (trs_ecc_err[1]),        // Templated
                  .trs_err_type         (trs1_err_type[2:0]),    // Templated
                  .trs_err_index        (trs1_err_index[2:0]),   // Templated
                  .trs_ep_err           (trs_ep_err[1]),      // Templated
                  .trs_eperr_st         (trs_eperr_st[1]),      // Templated
                  .trs_eccerr_st        (trs_eccerr_st[1]),      // Templated
                  // Inputs
                  .scan_in(trs1_scanin),
                  .scan_out(trs1_scanout),
                  .l1clk                (l1clk),
                  .tsb_hit_hw1          (htc_tsb_hit_hw1[1]),    // Templated
                  .thr_valid_hw3         (htc_thr_valid_hw3[1]),   // Templated
                  .ra2pahit_hw5         (htc_ra2pahit_hw5[1]),   // Templated
                  .ranotpax_hw5         (htc_ranotpax_hw5[1]),   // Templated
                  .tsm_waitfortte       (tsm_waitfortte[1]),     // Templated
                  .ep_miss_hw1          (htc_ep_miss_hw1[1]),     // Templated
                  .rrindex_bit0         (htc_rrindex_bit0[1]),     // Templated
                  .rrindex_bit1         (htc_rrindex_bit1[1]),     // Templated
                  .l2_ecc_err_hw1       (l2_ecc_err_hw1[1]),     // Templated
                  .cfg_ecc_err_m3       (cfg_ecc_err_m3[1]),     // Templated
                  .rr_ecc_err_hw5       (rr_ecc_err_hw5[1]),     // Templated
                  .l2_ecc_err_type      (l2_ecc_err_type[1:0]),
                  .cfg_ecc_err_type     (cfg_ecc_err_type[1:0]),
                  .rr_ecc_err_type      (rr_ecc_err_type[1:0]),
                  .cfg_ecc_err_index    (cfg_ecc_err_index[2:0]),
                  .rr_ecc_err_index     (rr_ecc_err_index[2:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));
mmu_trs_ctl trs2 (
                  /*AUTOINST*/
                  // Outputs
                  .trs_rqv              (trs_rqv[2]),            // Templated
                  .trs_null_st          (trs_null_st[2]),        // Templated
                  .trs_waitrr3_st       (trs_waitrr3_st[2]),        // Templated
                  .trs_ecc_err          (trs_ecc_err[2]),        // Templated
                  .trs_err_type         (trs2_err_type[2:0]),    // Templated
                  .trs_err_index        (trs2_err_index[2:0]),   // Templated
                  .trs_ep_err           (trs_ep_err[2]),      // Templated
                  .trs_eperr_st         (trs_eperr_st[2]),      // Templated
                  .trs_eccerr_st        (trs_eccerr_st[2]),      // Templated
                  // Inputs
                  .scan_in(trs2_scanin),
                  .scan_out(trs2_scanout),
                  .l1clk                (l1clk),
                  .tsb_hit_hw1          (htc_tsb_hit_hw1[2]),    // Templated
                  .thr_valid_hw3         (htc_thr_valid_hw3[2]),   // Templated
                  .ra2pahit_hw5         (htc_ra2pahit_hw5[2]),   // Templated
                  .ranotpax_hw5         (htc_ranotpax_hw5[2]),   // Templated
                  .tsm_waitfortte       (tsm_waitfortte[2]),     // Templated
                  .ep_miss_hw1          (htc_ep_miss_hw1[2]),     // Templated
                  .rrindex_bit0         (htc_rrindex_bit0[2]),     // Templated
                  .rrindex_bit1         (htc_rrindex_bit1[2]),     // Templated
                  .l2_ecc_err_hw1       (l2_ecc_err_hw1[2]),     // Templated
                  .cfg_ecc_err_m3       (cfg_ecc_err_m3[2]),     // Templated
                  .rr_ecc_err_hw5       (rr_ecc_err_hw5[2]),     // Templated
                  .l2_ecc_err_type      (l2_ecc_err_type[1:0]),
                  .cfg_ecc_err_type     (cfg_ecc_err_type[1:0]),
                  .rr_ecc_err_type      (rr_ecc_err_type[1:0]),
                  .cfg_ecc_err_index    (cfg_ecc_err_index[2:0]),
                  .rr_ecc_err_index     (rr_ecc_err_index[2:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));
mmu_trs_ctl trs3 (
                  /*AUTOINST*/
                  // Outputs
                  .trs_rqv              (trs_rqv[3]),            // Templated
                  .trs_null_st          (trs_null_st[3]),        // Templated
                  .trs_waitrr3_st       (trs_waitrr3_st[3]),        // Templated
                  .trs_ecc_err          (trs_ecc_err[3]),        // Templated
                  .trs_err_type         (trs3_err_type[2:0]),    // Templated
                  .trs_err_index        (trs3_err_index[2:0]),   // Templated
                  .trs_ep_err           (trs_ep_err[3]),      // Templated
                  .trs_eperr_st         (trs_eperr_st[3]),      // Templated
                  .trs_eccerr_st        (trs_eccerr_st[3]),      // Templated
                  // Inputs
                  .scan_in(trs3_scanin),
                  .scan_out(trs3_scanout),
                  .l1clk                (l1clk),
                  .tsb_hit_hw1          (htc_tsb_hit_hw1[3]),    // Templated
                  .thr_valid_hw3         (htc_thr_valid_hw3[3]),   // Templated
                  .ra2pahit_hw5         (htc_ra2pahit_hw5[3]),   // Templated
                  .ranotpax_hw5         (htc_ranotpax_hw5[3]),   // Templated
                  .tsm_waitfortte       (tsm_waitfortte[3]),     // Templated
                  .ep_miss_hw1          (htc_ep_miss_hw1[3]),     // Templated
                  .rrindex_bit0         (htc_rrindex_bit0[3]),     // Templated
                  .rrindex_bit1         (htc_rrindex_bit1[3]),     // Templated
                  .l2_ecc_err_hw1       (l2_ecc_err_hw1[3]),     // Templated
                  .cfg_ecc_err_m3       (cfg_ecc_err_m3[3]),     // Templated
                  .rr_ecc_err_hw5       (rr_ecc_err_hw5[3]),     // Templated
                  .l2_ecc_err_type      (l2_ecc_err_type[1:0]),
                  .cfg_ecc_err_type     (cfg_ecc_err_type[1:0]),
                  .rr_ecc_err_type      (rr_ecc_err_type[1:0]),
                  .cfg_ecc_err_index    (cfg_ecc_err_index[2:0]),
                  .rr_ecc_err_index     (rr_ecc_err_index[2:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));
mmu_trs_ctl trs4 (
                  /*AUTOINST*/
                  // Outputs
                  .trs_rqv              (trs_rqv[4]),            // Templated
                  .trs_null_st          (trs_null_st[4]),        // Templated
                  .trs_waitrr3_st       (trs_waitrr3_st[4]),        // Templated
                  .trs_ecc_err          (trs_ecc_err[4]),        // Templated
                  .trs_err_type         (trs4_err_type[2:0]),    // Templated
                  .trs_err_index        (trs4_err_index[2:0]),   // Templated
                  .trs_ep_err           (trs_ep_err[4]),      // Templated
                  .trs_eperr_st         (trs_eperr_st[4]),      // Templated
                  .trs_eccerr_st        (trs_eccerr_st[4]),      // Templated
                  // Inputs
                  .scan_in(trs4_scanin),
                  .scan_out(trs4_scanout),
                  .l1clk                (l1clk),
                  .tsb_hit_hw1          (htc_tsb_hit_hw1[4]),    // Templated
                  .thr_valid_hw3         (htc_thr_valid_hw3[4]),   // Templated
                  .ra2pahit_hw5         (htc_ra2pahit_hw5[4]),   // Templated
                  .ranotpax_hw5         (htc_ranotpax_hw5[4]),   // Templated
                  .tsm_waitfortte       (tsm_waitfortte[4]),     // Templated
                  .ep_miss_hw1          (htc_ep_miss_hw1[4]),     // Templated
                  .rrindex_bit0         (htc_rrindex_bit0[4]),     // Templated
                  .rrindex_bit1         (htc_rrindex_bit1[4]),     // Templated
                  .l2_ecc_err_hw1       (l2_ecc_err_hw1[4]),     // Templated
                  .cfg_ecc_err_m3       (cfg_ecc_err_m3[4]),     // Templated
                  .rr_ecc_err_hw5       (rr_ecc_err_hw5[4]),     // Templated
                  .l2_ecc_err_type      (l2_ecc_err_type[1:0]),
                  .cfg_ecc_err_type     (cfg_ecc_err_type[1:0]),
                  .rr_ecc_err_type      (rr_ecc_err_type[1:0]),
                  .cfg_ecc_err_index    (cfg_ecc_err_index[2:0]),
                  .rr_ecc_err_index     (rr_ecc_err_index[2:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));
mmu_trs_ctl trs5 (
                  /*AUTOINST*/
                  // Outputs
                  .trs_rqv              (trs_rqv[5]),            // Templated
                  .trs_null_st          (trs_null_st[5]),        // Templated
                  .trs_waitrr3_st       (trs_waitrr3_st[5]),        // Templated
                  .trs_ecc_err          (trs_ecc_err[5]),        // Templated
                  .trs_err_type         (trs5_err_type[2:0]),    // Templated
                  .trs_err_index        (trs5_err_index[2:0]),   // Templated
                  .trs_ep_err           (trs_ep_err[5]),      // Templated
                  .trs_eperr_st         (trs_eperr_st[5]),      // Templated
                  .trs_eccerr_st        (trs_eccerr_st[5]),      // Templated
                  // Inputs
                  .scan_in(trs5_scanin),
                  .scan_out(trs5_scanout),
                  .l1clk                (l1clk),
                  .tsb_hit_hw1          (htc_tsb_hit_hw1[5]),    // Templated
                  .thr_valid_hw3         (htc_thr_valid_hw3[5]),   // Templated
                  .ra2pahit_hw5         (htc_ra2pahit_hw5[5]),   // Templated
                  .ranotpax_hw5         (htc_ranotpax_hw5[5]),   // Templated
                  .tsm_waitfortte       (tsm_waitfortte[5]),     // Templated
                  .ep_miss_hw1          (htc_ep_miss_hw1[5]),     // Templated
                  .rrindex_bit0         (htc_rrindex_bit0[5]),     // Templated
                  .rrindex_bit1         (htc_rrindex_bit1[5]),     // Templated
                  .l2_ecc_err_hw1       (l2_ecc_err_hw1[5]),     // Templated
                  .cfg_ecc_err_m3       (cfg_ecc_err_m3[5]),     // Templated
                  .rr_ecc_err_hw5       (rr_ecc_err_hw5[5]),     // Templated
                  .l2_ecc_err_type      (l2_ecc_err_type[1:0]),
                  .cfg_ecc_err_type     (cfg_ecc_err_type[1:0]),
                  .rr_ecc_err_type      (rr_ecc_err_type[1:0]),
                  .cfg_ecc_err_index    (cfg_ecc_err_index[2:0]),
                  .rr_ecc_err_index     (rr_ecc_err_index[2:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));
mmu_trs_ctl trs6 (
                  /*AUTOINST*/
                  // Outputs
                  .trs_rqv              (trs_rqv[6]),            // Templated
                  .trs_null_st          (trs_null_st[6]),        // Templated
                  .trs_waitrr3_st       (trs_waitrr3_st[6]),        // Templated
                  .trs_ecc_err          (trs_ecc_err[6]),        // Templated
                  .trs_err_type         (trs6_err_type[2:0]),    // Templated
                  .trs_err_index        (trs6_err_index[2:0]),   // Templated
                  .trs_ep_err           (trs_ep_err[6]),      // Templated
                  .trs_eperr_st         (trs_eperr_st[6]),      // Templated
                  .trs_eccerr_st        (trs_eccerr_st[6]),      // Templated
                  // Inputs
                  .scan_in(trs6_scanin),
                  .scan_out(trs6_scanout),
                  .l1clk                (l1clk),
                  .tsb_hit_hw1          (htc_tsb_hit_hw1[6]),    // Templated
                  .thr_valid_hw3         (htc_thr_valid_hw3[6]),   // Templated
                  .ra2pahit_hw5         (htc_ra2pahit_hw5[6]),   // Templated
                  .ranotpax_hw5         (htc_ranotpax_hw5[6]),   // Templated
                  .tsm_waitfortte       (tsm_waitfortte[6]),     // Templated
                  .ep_miss_hw1          (htc_ep_miss_hw1[6]),     // Templated
                  .rrindex_bit0         (htc_rrindex_bit0[6]),     // Templated
                  .rrindex_bit1         (htc_rrindex_bit1[6]),     // Templated
                  .l2_ecc_err_hw1       (l2_ecc_err_hw1[6]),     // Templated
                  .cfg_ecc_err_m3       (cfg_ecc_err_m3[6]),     // Templated
                  .rr_ecc_err_hw5       (rr_ecc_err_hw5[6]),     // Templated
                  .l2_ecc_err_type      (l2_ecc_err_type[1:0]),
                  .cfg_ecc_err_type     (cfg_ecc_err_type[1:0]),
                  .rr_ecc_err_type      (rr_ecc_err_type[1:0]),
                  .cfg_ecc_err_index    (cfg_ecc_err_index[2:0]),
                  .rr_ecc_err_index     (rr_ecc_err_index[2:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));
mmu_trs_ctl trs7 (
                  /*AUTOINST*/
                  // Outputs
                  .trs_rqv              (trs_rqv[7]),            // Templated
                  .trs_null_st          (trs_null_st[7]),        // Templated
                  .trs_waitrr3_st       (trs_waitrr3_st[7]),        // Templated
                  .trs_ecc_err          (trs_ecc_err[7]),        // Templated
                  .trs_err_type         (trs7_err_type[2:0]),    // Templated
                  .trs_err_index        (trs7_err_index[2:0]),   // Templated
                  .trs_ep_err           (trs_ep_err[7]),      // Templated
                  .trs_eperr_st         (trs_eperr_st[7]),      // Templated
                  .trs_eccerr_st        (trs_eccerr_st[7]),      // Templated
                  // Inputs
                  .scan_in(trs7_scanin),
                  .scan_out(trs7_scanout),
                  .l1clk                (l1clk),
                  .tsb_hit_hw1          (htc_tsb_hit_hw1[7]),    // Templated
                  .thr_valid_hw3         (htc_thr_valid_hw3[7]),   // Templated
                  .ra2pahit_hw5         (htc_ra2pahit_hw5[7]),   // Templated
                  .ranotpax_hw5         (htc_ranotpax_hw5[7]),   // Templated
                  .tsm_waitfortte       (tsm_waitfortte[7]),     // Templated
                  .ep_miss_hw1          (htc_ep_miss_hw1[7]),     // Templated
                  .rrindex_bit0         (htc_rrindex_bit0[7]),     // Templated
                  .rrindex_bit1         (htc_rrindex_bit1[7]),     // Templated
                  .l2_ecc_err_hw1       (l2_ecc_err_hw1[7]),     // Templated
                  .cfg_ecc_err_m3       (cfg_ecc_err_m3[7]),     // Templated
                  .rr_ecc_err_hw5       (rr_ecc_err_hw5[7]),     // Templated
                  .l2_ecc_err_type      (l2_ecc_err_type[1:0]),
                  .cfg_ecc_err_type     (cfg_ecc_err_type[1:0]),
                  .rr_ecc_err_type      (rr_ecc_err_type[1:0]),
                  .cfg_ecc_err_index    (cfg_ecc_err_index[2:0]),
                  .rr_ecc_err_index     (rr_ecc_err_index[2:0]),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk));

////////////////////////////////////////////////////////
// SPARE CELLS
////////////////////////////////////////////////////////
mmu_trc_ctl_spare_ctl_macro__num_2 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
////////////////////////////////////////////////////////

// fixscan start:
assign trs0_scanin               = scan_in                  ;
assign trs1_scanin               = trs0_scanout             ;
assign trs2_scanin               = trs1_scanout             ;
assign trs3_scanin               = trs2_scanout             ;
assign trs4_scanin               = trs3_scanout             ;
assign trs5_scanin               = trs4_scanout             ;
assign trs6_scanin               = trs5_scanout             ;
assign trs7_scanin               = trs6_scanout             ;
assign spares_scanin             = trs7_scanout             ;
assign scan_out                  = spares_scanout           ;

// fixscan end:
endmodule

// Local Variables:
// verilog-library-directories:("." "v")
// End:


// any PARAMS parms go into naming of macro

module mmu_trc_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_trc_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_trc_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module mmu_trc_ctl_spare_ctl_macro__num_2 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));
assign scan_out = so_1;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_trs_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_trs_ctl (
  l1clk, 
  scan_in, 
  spc_aclk, 
  spc_bclk, 
  tsb_hit_hw1, 
  thr_valid_hw3, 
  ra2pahit_hw5, 
  ranotpax_hw5, 
  tsm_waitfortte, 
  ep_miss_hw1, 
  rrindex_bit0, 
  rrindex_bit1, 
  l2_ecc_err_hw1, 
  cfg_ecc_err_m3, 
  rr_ecc_err_hw5, 
  l2_ecc_err_type, 
  cfg_ecc_err_type, 
  rr_ecc_err_type, 
  cfg_ecc_err_index, 
  rr_ecc_err_index, 
  trs_rqv, 
  trs_null_st, 
  trs_waitrr3_st, 
  trs_ecc_err, 
  trs_ep_err, 
  trs_err_type, 
  trs_err_index, 
  trs_eccerr_st, 
  trs_eperr_st, 
  scan_out);
wire siclk;
wire soclk;
wire [1:0] rrindex;
wire goto_null_state;
wire null_state;
wire ignorette_state;
wire eperr_state;
wire eccerr_state;
wire next_null_state;
wire next_null_state_;
wire null_state_;
wire null_state_reg_scanin;
wire null_state_reg_scanout;
wire goto_validreq_state;
wire validreq_state;
wire next_validreq_state;
wire validreq_state_reg_scanin;
wire validreq_state_reg_scanout;
wire goto_waitrr2_state;
wire next_waitrr2_state;
wire waitrr2_state_reg_scanin;
wire waitrr2_state_reg_scanout;
wire waitrr2_state;
wire goto_waitrr3_state;
wire next_waitrr3_state;
wire waitrr3_state_reg_scanin;
wire waitrr3_state_reg_scanout;
wire waitrr3_state;
wire goto_ignorette_state;
wire next_ignorette_state;
wire ignorette_state_reg_scanin;
wire ignorette_state_reg_scanout;
wire goto_eperr_state;
wire next_eperr_state;
wire eperr_state_reg_scanin;
wire eperr_state_reg_scanout;
wire goto_eccerr_state;
wire next_eccerr_state;
wire eccerr_state_reg_scanin;
wire eccerr_state_reg_scanout;
wire take_l2_err;
wire take_cfg_err;
wire take_rr_err;
wire [2:0] err_type;
wire err_type_en;
wire [2:0] err_type_in;
wire [2:0] new_err_index;
wire [2:0] err_index_in;
wire err_type_reg_scanin;
wire err_type_reg_scanout;
wire err_index_reg_scanin;
wire err_index_reg_scanout;


input           l1clk;
input           scan_in;
input		spc_aclk;
input		spc_bclk;

input           tsb_hit_hw1;
input           thr_valid_hw3;
input           ra2pahit_hw5;
input           ranotpax_hw5;
input           tsm_waitfortte;

input           ep_miss_hw1;
input           rrindex_bit0;
input           rrindex_bit1;


input           l2_ecc_err_hw1;
input           cfg_ecc_err_m3;
input           rr_ecc_err_hw5;

input [1:0]     l2_ecc_err_type;
input [1:0]     cfg_ecc_err_type;
input [1:0]     rr_ecc_err_type;

input [2:0]     cfg_ecc_err_index;
input [2:0]     rr_ecc_err_index;


output          trs_rqv;
output          trs_null_st;       // indicates that the thread in NULL state.
output          trs_waitrr3_st;    // indicates that the thread in waitrr3 state.
output          trs_ecc_err;       // ecc error signal
output          trs_ep_err;        // ep miss detection
output [2:0]    trs_err_type;      // ecc error type (001=>mra c 010=>mra uc 101=>l2 c 110=>l2 uc 111=>l2 notdata)
                                          // thread could be in validreq, readrr, waitrr2, waitrr3 or ignorette states.

output [2:0]    trs_err_index;     // index for mra errors

output          trs_eccerr_st;
output          trs_eperr_st;

output          scan_out;


assign siclk	= spc_aclk;
assign soclk	= spc_bclk;


assign rrindex[1:0] = {rrindex_bit1, rrindex_bit0};


///////////////////////////////////////////////////
// CASE STATEMENT DESCRIPTION OF TRS MACHINE
///////////////////////////////////////////////////
//case(`TRS_STATE)
//  `NULL_ST:
//    begin
//
//    if (~tsb_hit_hw1 & ~l2_ecc_err_hw1 & ~cfg_ecc_err_m3 & ~ep_miss_hw1)
//      next_state = `NULL_ST;
//    if (tsb_hit_hw1 & ~l2_ecc_err_hw1 & ~cfg_ecc_err_m3 & ~ep_miss_hw1)
//      next_state = `VALIDREQ_ST;
//    if (ep_miss_hw1 & l2_ecc_err_hw1 & ~cfg_ecc_err_m3)
//      next_state = `EPERR_ST;
//    if (l2_ecc_err_hw1 | cfg_ecc_err_m3)
//      next_state = `ECCERR_ST;
//
//    end
//
//  `VALIDREQ_ST:
//    begin
//        if (~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err &
//           (~(rrindex[1:0] == 2'b11 & thr_valid_hw3)))
//          next_state = `VALIDREQ_ST;
//        if (~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err &
//           ((rrindex[1:0] == 2'b11 & thr_valid_hw3)))
//          next_state = `WAITRR2_ST;
//        if ((ra2pahit_hw5 | ranotpax_hw5) & ~rr_ecc_err)
//          next_state = `IGNORETTE_ST;
//        if (rr_ecc_err)
//          next_state = `ECCERR_ST;
//    end
//
//  `WAITRR2_ST:
//    begin
//        if (~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err)
//          next_state = `WAITRR3_ST;
//        if ((ra2pahit_hw5 | ranotpax_hw5) & ~rr_ecc_err)
//          next_state = `IGNORETTE_ST;
//        if (rr_ecc_err)
//          next_state = `ECCERR_ST;
//    end
//
//  `WAITRR3_ST:
//    begin
//        if (~rr_ecc_err)
//          next_state = `IGNORETTE_ST;
//        if (rr_ecc_err)
//          next_state = `ECCERR_ST;
//    end
//
//  `IGNORETTE_ST:
//    begin
//        if (~tsm_waitfortte) 
//          next_state = `NULL_ST;
//        else
//          next_state = `IGNORETTE_ST;
//    end
//
//  `ECCERR_ST:
//    begin
//        if (~tsm_waitfortte) 
//          next_state = `NULL_ST;
//        else
//          next_state = `ECCERR_ST;
//    end
//
//  `EPERR_ST:
//    begin
//        if (~tsm_waitfortte) 
//          next_state = `NULL_ST;
//        else
//          next_state = `EPERR_ST;
//    end
//
//endcase // case(`TRS_STATE)
  
// 0in one_hot -var {null_state,validreq_state,waitrr2_state,waitrr3_state,ignorette_state,eccerr_state,eperr_state}


///////////////////////////////////////////////////
// Null State (HW1)
///////////////////////////////////////////////////
assign goto_null_state = (null_state  & ~tsb_hit_hw1 & ~l2_ecc_err_hw1 & ~cfg_ecc_err_m3 & ~ep_miss_hw1) | //if thr_sel then go to specrr)
                         (ignorette_state & ~tsm_waitfortte) |
                         (eperr_state & ~tsm_waitfortte) |
                         (eccerr_state & ~tsm_waitfortte);
assign next_null_state = goto_null_state;

assign next_null_state_ = ~next_null_state;
assign null_state = ~null_state_;

mmu_trs_ctl_msff_ctl_macro__width_1 null_state_reg  (
 .scan_in(null_state_reg_scanin),
 .scan_out(null_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_null_state_),
 .dout (null_state_),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// Valid Req State (HW2)
///////////////////////////////////////////////////
assign goto_validreq_state = (null_state & tsb_hit_hw1 & ~cfg_ecc_err_m3) |                          //ra2pahit_hw5 cannot happen in null_state
                             (validreq_state & ~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err_hw5 &
                              ~(rrindex[1] & rrindex[0] & thr_valid_hw3)) ;

assign next_validreq_state = goto_validreq_state;


mmu_trs_ctl_msff_ctl_macro__width_1 validreq_state_reg  (
 .scan_in(validreq_state_reg_scanin),
 .scan_out(validreq_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_validreq_state),
 .dout (validreq_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// WaitRR2 State (HW4)
///////////////////////////////////////////////////
assign goto_waitrr2_state = (validreq_state & ~ra2pahit_hw5 & ~ranotpax_hw5 & rrindex[1] & rrindex[0] & thr_valid_hw3 & ~rr_ecc_err_hw5);
assign next_waitrr2_state = goto_waitrr2_state;


mmu_trs_ctl_msff_ctl_macro__width_1 waitrr2_state_reg  (
 .scan_in(waitrr2_state_reg_scanin),
 .scan_out(waitrr2_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_waitrr2_state),
 .dout (waitrr2_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// WaitRR3 State (HW5)
///////////////////////////////////////////////////
assign goto_waitrr3_state = (waitrr2_state & ~ra2pahit_hw5 & ~ranotpax_hw5 & ~rr_ecc_err_hw5);
assign next_waitrr3_state = goto_waitrr3_state;

mmu_trs_ctl_msff_ctl_macro__width_1 waitrr3_state_reg  (
 .scan_in(waitrr3_state_reg_scanin),
 .scan_out(waitrr3_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_waitrr3_state),
 .dout (waitrr3_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// IgnoreTTE State (HW6)
///////////////////////////////////////////////////
assign goto_ignorette_state = ((validreq_state | waitrr2_state ) & (ra2pahit_hw5 | ranotpax_hw5) & ~rr_ecc_err_hw5) |
                              (waitrr3_state & ~rr_ecc_err_hw5) |
                              (ignorette_state & tsm_waitfortte);
assign next_ignorette_state = goto_ignorette_state;


mmu_trs_ctl_msff_ctl_macro__width_1 ignorette_state_reg  (
 .scan_in(ignorette_state_reg_scanin),
 .scan_out(ignorette_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_ignorette_state),
 .dout (ignorette_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// EpErr State (HW6)
///////////////////////////////////////////////////
assign goto_eperr_state = (null_state & ep_miss_hw1 & ~cfg_ecc_err_m3) |
                           (eperr_state & tsm_waitfortte);
assign next_eperr_state = goto_eperr_state;


mmu_trs_ctl_msff_ctl_macro__width_1 eperr_state_reg  (
 .scan_in(eperr_state_reg_scanin),
 .scan_out(eperr_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_eperr_state),
 .dout (eperr_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// EccErr State (HW6)
///////////////////////////////////////////////////
assign goto_eccerr_state = (null_state & (l2_ecc_err_hw1 | cfg_ecc_err_m3)) |
                           ((validreq_state | waitrr2_state | waitrr3_state ) & rr_ecc_err_hw5) |
                           (eccerr_state & tsm_waitfortte);
assign next_eccerr_state = goto_eccerr_state;


mmu_trs_ctl_msff_ctl_macro__width_1 eccerr_state_reg  (
 .scan_in(eccerr_state_reg_scanin),
 .scan_out(eccerr_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_eccerr_state),
 .dout (eccerr_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// Set the ECC ERROR TYPE
// 000 No errors
// 110 MRA Correctable
// 101 MRA Uncorrectable
// 001 L2 correctable
// 010 L2 uncorrectable
// 011 L2 Not Data
// latch the first ecc error and hold it.
///////////////////////////////////////////////////
//0in bits_on -var {take_l2_err, take_cfg_err, take_rr_err} -max 1
assign take_l2_err = (null_state & l2_ecc_err_hw1);
assign take_cfg_err = (null_state  & ~l2_ecc_err_hw1 & cfg_ecc_err_m3);
assign take_rr_err = (validreq_state | waitrr2_state | waitrr3_state ) & rr_ecc_err_hw5;

assign err_type[1:0] = ({2{take_l2_err}} & l2_ecc_err_type[1:0]) |
                       ({2{take_cfg_err}} & cfg_ecc_err_type[1:0]) |
                       ({2{take_rr_err}} & rr_ecc_err_type[1:0]);

assign err_type[2] = (take_cfg_err | take_rr_err) & ~take_l2_err;
assign err_type_en = take_l2_err | take_cfg_err | take_rr_err;

assign err_type_in[2:0] = ({3{err_type_en}} & err_type[2:0]) |
                          ({3{~err_type_en}} & trs_err_type[2:0]);

assign new_err_index[2:0] =   ({3{take_cfg_err}} & cfg_ecc_err_index[2:0]) |
                          ({3{take_rr_err}} & rr_ecc_err_index[2:0]);


assign err_index_in[2:0] = ({3{err_type_en}} & new_err_index[2:0]) |
                          ({3{~err_type_en}} & trs_err_index[2:0]);


mmu_trs_ctl_msff_ctl_macro__width_3 err_type_reg  
(
 .scan_in(err_type_reg_scanin),
 .scan_out(err_type_reg_scanout),
 .l1clk(l1clk),
 .din  (err_type_in[2:0]),
 .dout (trs_err_type[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

mmu_trs_ctl_msff_ctl_macro__width_3 err_index_reg  
(
 .scan_in(err_index_reg_scanin),
 .scan_out(err_index_reg_scanout),
 .l1clk(l1clk),
 .din  (err_index_in[2:0]),
 .dout (trs_err_index[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);
///////////////////////////////////////////////////
// State Machine Outputs
///////////////////////////////////////////////////
assign trs_rqv = validreq_state;

assign trs_null_st = null_state;
assign trs_ecc_err = eccerr_state & ~tsm_waitfortte;
assign trs_eccerr_st = eccerr_state;
assign trs_waitrr3_st = waitrr3_state;


assign trs_ep_err = eperr_state & ~tsm_waitfortte;
assign trs_eperr_st = eperr_state;


supply0 vss;
supply1 vdd;

// fixscan start:
assign null_state_reg_scanin     = scan_in                  ;
assign validreq_state_reg_scanin = null_state_reg_scanout   ;
assign waitrr2_state_reg_scanin  = validreq_state_reg_scanout;
assign waitrr3_state_reg_scanin  = waitrr2_state_reg_scanout;
assign ignorette_state_reg_scanin = waitrr3_state_reg_scanout;
assign eperr_state_reg_scanin    = ignorette_state_reg_scanout;
assign eccerr_state_reg_scanin   = eperr_state_reg_scanout  ;
assign err_type_reg_scanin       = eccerr_state_reg_scanout ;
assign err_index_reg_scanin      = err_type_reg_scanout     ;
assign scan_out                  = err_index_reg_scanout    ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module mmu_trs_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_trs_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: mmu_tsm_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module mmu_tsm_ctl (
  l1clk, 
  scan_in, 
  spc_aclk, 
  spc_bclk, 
  data_rcvd_hw1, 
  tlb_miss_m, 
  tsb_done_hw2, 
  vld_tsbptr_m2, 
  thr_valid_m1, 
  thr_valid_m0, 
  cindex_bit0, 
  cindex_bit1, 
  hwtw_burst, 
  trs_eperr_st, 
  trs_eccerr_st, 
  tsm_tsb_miss_hw2, 
  tsm_rqv, 
  tsm_waitfortte, 
  scan_out);
wire siclk;
wire soclk;
wire [1:0] cindex;
wire goto_null_state;
wire null_state;
wire validreq_state;
wire seqm1_state;
wire seqm2_state;
wire cfgdone_state;
wire ttewait_state;
wire next_null_state;
wire next_null_state_;
wire null_state_;
wire null_state_reg_scanin;
wire null_state_reg_scanout;
wire goto_validreq_state;
wire outstanding_miss_state;
wire next_validreq_state;
wire validreq_state_reg_scanin;
wire validreq_state_reg_scanout;
wire goto_seqm1_state;
wire next_seqm1_state;
wire seqm1_state_reg_scanin;
wire seqm1_state_reg_scanout;
wire goto_seqm2_state;
wire next_seqm2_state;
wire seqm2_state_reg_scanin;
wire seqm2_state_reg_scanout;
wire goto_cfgdone_state;
wire next_cfgdone_state;
wire cfgdone_state_reg_scanin;
wire cfgdone_state_reg_scanout;
wire goto_ttewait_state;
wire next_ttewait_state;
wire ttewait_state_reg_scanin;
wire ttewait_state_reg_scanout;
wire goto_outstanding_miss_state;
wire next_outstanding_miss_state;
wire outstanding_miss_state_reg_scanin;
wire outstanding_miss_state_reg_scanout;
wire data_rcvd_lat_scanin;
wire data_rcvd_lat_scanout;
wire data_rcvd_hw1_ff;
wire req_enq;
wire req_deq;
wire [3:0] next_bal;
wire [3:0] bal;
wire bal_lat_scanin;
wire bal_lat_scanout;


input           l1clk;
input           scan_in;
input		spc_aclk;
input		spc_bclk;

input           data_rcvd_hw1;       // data back from gkt, from htc
input           tlb_miss_m;             // indicates tlb miss, from htc
input           tsb_done_hw2;              // indicates tsb hit, from htc
input           vld_tsbptr_m2;              // indicates valid tsbptr
input           thr_valid_m1;       // valid req in M1 which got asi grant and room avail
input           thr_valid_m0;       // valid req in M0

input           cindex_bit0;
input           cindex_bit1;


input           hwtw_burst;         // hwtw is in burst mode

                                      // mra read, and data available.  
input           trs_eperr_st;         // trs is in ep miss err state

input           trs_eccerr_st;         // trs is in eccerr state

output          tsm_tsb_miss_hw2;    // no tsb hit on any of the 4 tsb 
output          tsm_rqv;         // request is valid, in REQ or CFG_RD
output          tsm_waitfortte;       // all tte not received
output          scan_out;

assign siclk	= spc_aclk;
assign soclk	= spc_bclk;


assign cindex[1:0] = {cindex_bit1, cindex_bit0};

///////////////////////////////////////////////////
// CASE STATEMENT DESCRIPTION OF TSM MACHINE
///////////////////////////////////////////////////

// tsb_done_hw2 = tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4;
//case(`TSM_STATE)
//  `NULL_ST:
//    if (~tlb_miss_m) 
//      next_state = `NULL_ST;
//    else 
//      next_state = `VALIDREQ_ST;
//
//  `VALIDREQ_ST:
//    begin
//        if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~tsm_waitfortte)
//          next_state = `NULL_ST;
//        if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte)
//          next_state = `TTEWAIT_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & burst_mode & (~(cindex[1:0] ==2'b11 & thr_valid_m1)))
//          next_state = `VALIDREQ_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~burst_mode & ~thr_valid_m0)
//          next_state = `VALIDREQ_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~burst_mode & thr_valid_m0)
//          next_state = `SEQM1_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & (cindex[1:0] ==2'b11 & thr_valid_m1))
//          next_state = `CFGDONE_ST;
//    end
//  
//  `SEQM1_ST:
//    begin
//        if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~tsm_waitfortte)
//          next_state = `NULL_ST;
//        if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte)
//          next_state = `TTEWAIT_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~thr_valid_m1)
//          next_state = `VALIDREQ_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & thr_valid_m1 & (cindex[1:0] ==2'b11))
//          next_state = `CFGDONE_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & thr_valid_m1 & ~(cindex[1:0] ==2'b11))
//          next_state = `SEQM2_ST;
//    end
//
//  `SEQM2_ST:
//    begin
//        if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~tsm_waitfortte)
//          next_state = `NULL_ST;          
//        if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte)
//          next_state = `TTEWAIT_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~tsm_waitfortte)
//          next_state = `VALIDREQ_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte)
//          next_state = `SEQM2_ST;
//    end
//
//  `CFGDONE_ST:
//    begin
//        if (~tsm_waitfortte)
//          next_state = `NULL_ST;
//        if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte)
//          next_state = `TTEWAIT_ST;
//        if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte)
//          next_state = `CFGDONE_ST;
//    end
//
//  `TTEWAIT_ST:
//    begin
//        if (tlb_miss_m)
//          next_state = `OUTMISSWAIT_ST;
//        if (~tsm_waitfortte & ~tlb_miss_m)
//          next_state = `NULL_ST;
//        if (tsm_waitfortte & ~tlb_miss_m)
//          next_state = `TTEWAIT_ST;
//    end
//
//  `OUTMISSWAIT_ST:
//    begin
//        if (tsm_waitfortte)
//          next_state = `OUTMISSWAIT_ST;
//        else
//          next_state = `VALIDREQ_ST;
//    end
//endcase // case(`TSM_STATE)

        
// 0in one_hot -var {null_state,validreq_state,seqm1_state,seqm2_state,cfgdone_state,ttewait_state,outstanding_miss_state}
///////////////////////////////////////////////////
// Null State (NULL_ST)
///////////////////////////////////////////////////
// Goto null state if either of following is true
// => NULL_ST     and  no tlb miss 
// => VALIDREQ_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and no outstanding tte
// => SEQM1_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and all  no outstanding tte
// => SEQM2_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and all  no outstanding tte
// => CFGDONE_ST  and no outstanding tte
// => TTEWAIT_ST  and no tlb miss and no outstanding tte

// Leave null state if either of following is true
// => tlb miss occurs (goto validreq state)

assign goto_null_state = (null_state & ~tlb_miss_m) |
                         (validreq_state & tsb_done_hw2 & ~tsm_waitfortte) |
                         (seqm1_state & tsb_done_hw2 & ~tsm_waitfortte) |
                         (seqm2_state & tsb_done_hw2 & ~tsm_waitfortte) |
                         (cfgdone_state & ~tsm_waitfortte) | //irrespective of tsb_hit_hw2
                         (ttewait_state & ~tsm_waitfortte & ~tlb_miss_m);

assign next_null_state = goto_null_state;
assign next_null_state_ = ~next_null_state;
assign null_state = ~null_state_;

mmu_tsm_ctl_msff_ctl_macro__width_1 null_state_reg  (
 .scan_in(null_state_reg_scanin),
 .scan_out(null_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_null_state_),
 .dout (null_state_),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// Valid Req State (VALIDREQ_ST)
///////////////////////////////////////////////////
// Goto valid req. state if either of following is true
// => VALIDREQ_ST      and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and burst mode and all tsb cfg not read
// => VALIDREQ_ST      and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and ~burst mode and current thread not selected
// => SEQM1_ST         and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and ~thr_valid_m1 (req did not get a grant from asi).
// => SEQM2_ST         and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and no outstanding tte
// => NULL_ST          and tlb_miss_m
// => OUTMISSWAIT_ST   and no outstanding tte 

// Leave valid req. state if either of following is true
// => VALIDREQ_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) (go to NULL_ST or TTEWAIT_ST)  
// => VALIDREQ_ST and all req are read (go to CFGDONE_ST)
// => VALIDREQ_ST and not burst mode and current thread selected (thr_valid_m0) (go to SEQM1_ST)

assign goto_validreq_state = (validreq_state & ~tsb_done_hw2 & hwtw_burst & ~(cindex[1] & cindex[0] & thr_valid_m1)) |
                             (validreq_state & ~tsb_done_hw2 & ~hwtw_burst & ~thr_valid_m0) | 
                             (seqm1_state & ~tsb_done_hw2 & ~thr_valid_m1) |
                             (seqm2_state & ~tsb_done_hw2 & ~tsm_waitfortte) |
                             (null_state & tlb_miss_m) | 
                             (outstanding_miss_state & ~tsm_waitfortte);
assign next_validreq_state = goto_validreq_state;


mmu_tsm_ctl_msff_ctl_macro__width_1 validreq_state_reg  (
 .scan_in(validreq_state_reg_scanin),
 .scan_out(validreq_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_validreq_state),
 .dout (validreq_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// Sequential M1 State (SEQM1_ST)
///////////////////////////////////////////////////
// Goto sequential M1 state if either of following is true
// => VALIDREQ_ST      and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and not burst mode and current thread selected

// Leave sequential M1 state if either of following is true
// => SEQM1_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) (go to NULL_ST or TTEWAIT_ST)  
// => SEQM1_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and ~thr_valid_m1 (req was not granted), (go to VALIDREQ_ST)
// => SEQM1_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and thr_valid_m1 (go to SEQM2_ST or CFGDONE_ST)

assign goto_seqm1_state = (validreq_state & ~tsb_done_hw2 & ~hwtw_burst & thr_valid_m0);
assign next_seqm1_state = goto_seqm1_state;


mmu_tsm_ctl_msff_ctl_macro__width_1 seqm1_state_reg  (
 .scan_in(seqm1_state_reg_scanin),
 .scan_out(seqm1_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_seqm1_state),
 .dout (seqm1_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// Sequential M2 State (SEQM2_ST)
///////////////////////////////////////////////////
// Goto sequential M2 state if either of following is true
// => SEQM1_ST      and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and thr_valid_m1 & all cfg not read
// => SEQM2_ST      and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte

// Leave sequential M2 state if either of following is true
// => SEQM2_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) (go to NULL_ST or TTEWAIT_ST)  
// => SEQM2_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and no outstanding tte (go to VALIDREQ_ST)

assign goto_seqm2_state = (seqm1_state & ~tsb_done_hw2 & thr_valid_m1 & ~(cindex[1] & cindex[0])) |
                          (seqm2_state & ~tsb_done_hw2 & tsm_waitfortte);
assign next_seqm2_state = goto_seqm2_state;


mmu_tsm_ctl_msff_ctl_macro__width_1 seqm2_state_reg  (
 .scan_in(seqm2_state_reg_scanin),
 .scan_out(seqm2_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_seqm2_state),
 .dout (seqm2_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// AllConfigRead State (CFGDONE_ST)
///////////////////////////////////////////////////
// Goto all TSB read state if either of following is true
// => VALIDREQ_ST  and burst mode and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & all cfg read
// => SEQM1_ST     and  ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & all cfg read
// => CFGDONE_ST   and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte

// Leave all CFG read state if either of following is true
// => CFGDONE_ST and all  no outstanding TTE (go to NULL_ST)
// => CFGDONE_ST and TSB hit and outstanding TTE (go to TTEWAIT_ST)

assign goto_cfgdone_state =  (cfgdone_state & ~tsb_done_hw2 & tsm_waitfortte) |
                             (validreq_state & ~tsb_done_hw2 & hwtw_burst & cindex[1] & cindex[0] & thr_valid_m1) |
                             (seqm1_state & ~tsb_done_hw2  & cindex[1] & cindex[0] & thr_valid_m1);


assign next_cfgdone_state = goto_cfgdone_state;


mmu_tsm_ctl_msff_ctl_macro__width_1 cfgdone_state_reg  (
 .scan_in(cfgdone_state_reg_scanin),
 .scan_out(cfgdone_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_cfgdone_state),
 .dout (cfgdone_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// TTE Wait State (TTEWAIT_ST)
// go to this state on (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4).
///////////////////////////////////////////////////
// Goto TTEWAIT_ST state if either of following is true
// => TTEWAIT_ST     and no tlb miss and outstanding tte
// => VALIDREQ_ST    and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte
// => SEQM1_ST       and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte
// => SEQM2_ST       and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte
// => CFGDONE_ST     and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte

// Leave TTEWAIT_ST state if either of following is true
// => TTEWAIT_ST and tlb miss (go to OUTMISSWAIT_ST)
// => TTEWAIT_ST and no tlb miss and no outstanding tte (go to NULL_ST)

assign goto_ttewait_state =  (ttewait_state & ~tlb_miss_m & tsm_waitfortte) |
                             (validreq_state & tsb_done_hw2 & tsm_waitfortte) |
                             (seqm1_state & tsb_done_hw2 & tsm_waitfortte) |
                             (seqm2_state & tsb_done_hw2 & tsm_waitfortte) |
                             (cfgdone_state & tsb_done_hw2 & tsm_waitfortte);

assign next_ttewait_state = goto_ttewait_state;


mmu_tsm_ctl_msff_ctl_macro__width_1 ttewait_state_reg  (
 .scan_in(ttewait_state_reg_scanin),
 .scan_out(ttewait_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_ttewait_state),
 .dout (ttewait_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// Outstanding Miss State (OUTMISSWAIT_ST)
//  Indicates TTEWAIT_ST and a  tlb_miss_m (can happen when we
// have a tsb  hit, thread gets restarted, but all tte's are not done for
// the original miss)
///////////////////////////////////////////////////
// Goto all OUTMISSWAIT_ST if either of following is true
// => OUTMISSWAIT_ST   and not all  TTE received (tsm_waitfortte)
// => TTEWAIT_ST       and tlb_miss_m

assign goto_outstanding_miss_state = (outstanding_miss_state & tsm_waitfortte) |
                                     (ttewait_state & tlb_miss_m);

assign next_outstanding_miss_state = goto_outstanding_miss_state;


mmu_tsm_ctl_msff_ctl_macro__width_1 outstanding_miss_state_reg  (
 .scan_in(outstanding_miss_state_reg_scanin),
 .scan_out(outstanding_miss_state_reg_scanout),
 .l1clk(l1clk),
 .din  (next_outstanding_miss_state),
 .dout (outstanding_miss_state),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// End of State machine
///////////////////////////////////////////////////

///////////////////////////////////////////////////
// EnQ/DeQ TTEs
// Keeping track of outstanding TTE requests.
// Increment the counter on every request  sent out (vld_tsbptr_m2),
// Decrement the counter on every data recvd, (data_rcvd_hw1)
///////////////////////////////////////////////////
mmu_tsm_ctl_msff_ctl_macro__width_1 data_rcvd_lat  (
 .scan_in(data_rcvd_lat_scanin),
 .scan_out(data_rcvd_lat_scanout),
 .l1clk(l1clk),
 .din  (data_rcvd_hw1),
 .dout (data_rcvd_hw1_ff),
  .siclk(siclk),
  .soclk(soclk)
);
assign req_enq = vld_tsbptr_m2 & ~data_rcvd_hw1_ff;
assign req_deq = data_rcvd_hw1_ff & ~vld_tsbptr_m2;

//0in bits_on -var {req_enq, req_deq} -max 1;
assign next_bal[3:0] = ({4{req_enq & ~bal[3] & ~bal[2] & ~bal[1] & ~bal[0]}} & 4'b0001) |
                       ({4{req_enq & ~bal[3] & ~bal[2] & ~bal[1] &  bal[0]}} & 4'b0011) |
                       ({4{req_enq & ~bal[3] & ~bal[2] &  bal[1] &  bal[0]}} & 4'b0111) |
                       ({4{req_enq & ~bal[3] &  bal[2] &  bal[1] &  bal[0]}} & 4'b1111) |
                       ({4{req_deq &  bal[3] &  bal[2] &  bal[1] &  bal[0]}} & 4'b0111) |
                       ({4{req_deq & ~bal[3] &  bal[2] &  bal[1] &  bal[0]}} & 4'b0011) |
                       ({4{req_deq & ~bal[3] & ~bal[2] &  bal[1] &  bal[0]}} & 4'b0001) |
                       ({4{req_deq & ~bal[3] & ~bal[2] & ~bal[1] &  bal[0]}} & 4'b0000) |
                       ({4{~req_deq & ~req_enq}} & bal[3:0]);

mmu_tsm_ctl_msff_ctl_macro__width_4 bal_lat  (
 .scan_in(bal_lat_scanin),
 .scan_out(bal_lat_scanout),
 .l1clk(l1clk),
 .din  ({next_bal[3:0]}),
 .dout ({bal[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

///////////////////////////////////////////////////
// State Machine Outputs
///////////////////////////////////////////////////
assign tsm_tsb_miss_hw2 = ~tsm_waitfortte & cfgdone_state & ~tsb_done_hw2  & ~trs_eccerr_st & ~trs_eperr_st;
assign tsm_rqv = validreq_state;
assign tsm_waitfortte = |next_bal[3:0];


supply0 vss;
supply1 vdd;

// fixscan start:
assign null_state_reg_scanin     = scan_in                  ;
assign validreq_state_reg_scanin = null_state_reg_scanout   ;
assign seqm1_state_reg_scanin    = validreq_state_reg_scanout;
assign seqm2_state_reg_scanin    = seqm1_state_reg_scanout  ;
assign cfgdone_state_reg_scanin  = seqm2_state_reg_scanout  ;
assign ttewait_state_reg_scanin  = cfgdone_state_reg_scanout;
assign outstanding_miss_state_reg_scanin = ttewait_state_reg_scanout;
assign data_rcvd_lat_scanin      = outstanding_miss_state_reg_scanout;
assign bal_lat_scanin            = data_rcvd_lat_scanout    ;
assign scan_out                  = bal_lat_scanout          ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module mmu_tsm_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module mmu_tsm_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pku.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module pku (
  tlu_halted, 
  tcu_do_mode, 
  dec_block_store_stall, 
  dec_ierr_d, 
  lsu_spec_enable, 
  spc_core_running_status, 
  lsu_pku_pmen, 
  tlu_retry_state, 
  tlu_flush_ifu, 
  dec_true_valid_e, 
  dec_decode0_d, 
  dec_decode1_d, 
  dec_valid0_d, 
  dec_valid1_d, 
  lsu_sync, 
  lsu_complete, 
  dec_br_taken_e, 
  fgu_divide_completion, 
  ifu_ibuffer_write_c, 
  lsu_stb_alloc, 
  lsu_stb_dealloc, 
  lsu_block_store_kill, 
  ifu_buf0_inst0, 
  ifu_buf0_inst1, 
  ifu_buf0_inst2, 
  ifu_buf0_inst3, 
  ifu_buf0_inst4, 
  ifu_buf0_inst5, 
  ifu_buf0_inst6, 
  ifu_buf0_inst7, 
  ifu_buf0_valid_p, 
  ifu_upper_buffer_valid_p, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  pku_raw_pick0_p, 
  pku_raw_pick1_p, 
  pku_base_pick_p, 
  pku_pick_p, 
  pku_lsu_p, 
  pku_fgu_p, 
  pku_pdist_p, 
  pku_twocycle_p, 
  pku_idest_p, 
  pku_fdest_p, 
  pku_fsrc_rd_p, 
  pku_isrc_rs1_p, 
  pku_isrc_rs2_p, 
  pku_isrc_rd_p, 
  pku_valid_e, 
  pku_annul_ds_dcti_brtaken0_e, 
  pku_annul_ds_dcti_brtaken1_e, 
  pku_flush_f1, 
  pku_flush_f2, 
  pku_flush_lb, 
  pku_flush_lm, 
  pku_flush_m, 
  pku_flush_b, 
  pku_load_flush_w, 
  pku_ds_e, 
  pku_flush_upper_buffer, 
  pku_flush_buffer0, 
  pku_quiesce, 
  pku_inst_cnt_brtaken00, 
  pku_inst_cnt_brtaken01, 
  pku_inst_cnt_brtaken02, 
  pku_inst_cnt_brtaken03, 
  pku_inst_cnt_brtaken04, 
  pku_inst_cnt_brtaken05, 
  pku_inst_cnt_brtaken06, 
  pku_inst_cnt_brtaken07, 
  pku_inst_cnt_brtaken10, 
  pku_inst_cnt_brtaken11, 
  pku_inst_cnt_brtaken12, 
  pku_inst_cnt_brtaken13, 
  pku_inst_cnt_brtaken14, 
  pku_inst_cnt_brtaken15, 
  pku_inst_cnt_brtaken16, 
  pku_inst_cnt_brtaken17, 
  scan_out);
wire [7:0] swl_divide_wait;
wire swl0_scanin;
wire swl0_scanout;
wire [7:0] swl_ready_p;
wire [7:0] swl_spec_ready_p;
wire [7:0] swl_cancel_pick_p;
wire swl1_scanin;
wire swl1_scanout;
wire swl2_scanin;
wire swl2_scanout;
wire swl3_scanin;
wire swl3_scanout;
wire pck0_scanin;
wire pck0_scanout;
wire swl4_scanin;
wire swl4_scanout;
wire swl5_scanin;
wire swl5_scanout;
wire swl6_scanin;
wire swl6_scanout;
wire swl7_scanin;
wire swl7_scanout;
wire pck1_scanin;
wire pck1_scanout;


input [7:0] tlu_halted;			// thread is in halted state

input tcu_do_mode;

input [7:0] dec_block_store_stall;  	// prevent window ops from coming too early after a block store 
input [1:0] dec_ierr_d;  		// tell pku that an inst error has occurred: illegal, parity error or ifetch error

input [7:0] lsu_spec_enable;		// enable speculation; assume this is serializing (if not pipeline it)
input [7:0] spc_core_running_status;	// active bits for each of the threads

input lsu_pku_pmen;			// power management enable for pku

input [7:0] tlu_retry_state;		// IF the first part of a retry, must let it go even in dcti w/out DS (part of address optimization)
input [7:0] tlu_flush_ifu;		// flush this thread (traps)
input [1:0] dec_true_valid_e;		// instruction at e stage is valid taking exceptions into account
input dec_decode0_d;			// instruction at d stage is decoded this cycle (TG0)
input dec_decode1_d;			// instruction at d stage is decoded this cycle (TG1)
input dec_valid0_d;			// instruction at d stage is valid (TG0)
input dec_valid1_d;			// instruction at d stage is valid (TG1)
input [7:0] lsu_sync;			// lsu needs thread to resync due to dcache_miss, ASI register access, etc.
input [7:0] lsu_complete;		// completion of lsu sync event
input [1:0] dec_br_taken_e;		// br is taken for e stage (br mispredict)

input [7:0] fgu_divide_completion;	// divide completion for any thread
input [7:0] ifu_ibuffer_write_c;	// any write to the ibuffer (C stage)
input [7:0] lsu_stb_alloc;		// lsu has allocated store in stb; sent in b_stage; increment ccnt by 1
input [7:0] lsu_stb_dealloc;		// lsu is deallocating store in stb; decrement sscnt,ccnt by 1
input [7:0] lsu_block_store_kill;  	// error occured in block store sequence; use this to set scnt=ccnt=0

input [31:0] ifu_buf0_inst0;		// oldest instruction for each of the instruction buffers
input [31:0] ifu_buf0_inst1;
input [31:0] ifu_buf0_inst2;
input [31:0] ifu_buf0_inst3;
input [31:0] ifu_buf0_inst4;
input [31:0] ifu_buf0_inst5;
input [31:0] ifu_buf0_inst6;
input [31:0] ifu_buf0_inst7;

input [7:0] ifu_buf0_valid_p;		// instruction valid signals for each of the buffers (oldest instruction)
input [7:0] ifu_upper_buffer_valid_p;	// instruction after oldest instruction is valid for each buffer

input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;
input tcu_scan_en;

output [3:0] pku_raw_pick0_p;   // raw pick signals to ifu to mux pc addresses (no swl_cancel_pick or decode cancel)
output [7:4] pku_raw_pick1_p;   

output [7:0] pku_base_pick_p;   // base pick signals to dec (no decode cancel)

output [7:0] pku_pick_p;	// final pick signals (with everything)

output [7:0] pku_lsu_p;		// lsu op at pick
output [7:0] pku_fgu_p;		// fgu op at pick
output [7:0] pku_pdist_p;	// pdist inst at pick
output [7:0] pku_twocycle_p;	// twocycle op at pick (std or casa)
output [7:0] pku_idest_p;	// op has integer dest at pick
output [7:0] pku_fdest_p;	// op has fp dest at pick

output [7:0] pku_fsrc_rd_p;	// fgu sources rd
	
output [7:0] pku_isrc_rs1_p;    // int op has rs1 source
output [7:0] pku_isrc_rs2_p;	// int op has rs2 source
output [7:0] pku_isrc_rd_p;	// int op has rd dest

output [7:0] pku_valid_e;	// inst is valid at e stage
	
output [7:0] pku_annul_ds_dcti_brtaken0_e;    // DS of dcti at e stage is annulled
output [7:0] pku_annul_ds_dcti_brtaken1_e;    // DS of dcti at e stage is annulled

output [7:0] pku_flush_f1;	// flush inst at f1 pipe stage of the fgu
output [7:0] pku_flush_f2;	// flush inst at f2 pipe stage of the fgu

output [7:0] pku_flush_lb;	// flush inst at b pipe stage of the lsu
output [7:0] pku_flush_lm;	// flush inst at m pipe stage of the lsu

output [7:0] pku_flush_m;	// flush inst at m pipe stage of trap
output [7:0] pku_flush_b;	// flush inst at b pipe stage of trap

output [7:0] pku_load_flush_w;	// tell ifu to flush this thread and fetch the npc of inst at w stage (due to load mispredict)

output [7:0] pku_ds_e;		// inst at e stage is a DS
	
output [7:0] pku_flush_upper_buffer;	// flush upper instruction buffers
output [7:0] pku_flush_buffer0;		// flush buffer0 of instruction buffers (oldest)

output [7:0] pku_quiesce;	// quiesce signal for each thread to tlu

output [1:0] pku_inst_cnt_brtaken00;	// inst cnts at e,m,b pipe stages for each thread
output [1:0] pku_inst_cnt_brtaken01;
output [1:0] pku_inst_cnt_brtaken02;
output [1:0] pku_inst_cnt_brtaken03;
output [1:0] pku_inst_cnt_brtaken04;
output [1:0] pku_inst_cnt_brtaken05;
output [1:0] pku_inst_cnt_brtaken06;
output [1:0] pku_inst_cnt_brtaken07;
output [1:0] pku_inst_cnt_brtaken10;	// inst cnts at e,m,b pipe stages for each thread
output [1:0] pku_inst_cnt_brtaken11;
output [1:0] pku_inst_cnt_brtaken12;
output [1:0] pku_inst_cnt_brtaken13;
output [1:0] pku_inst_cnt_brtaken14;
output [1:0] pku_inst_cnt_brtaken15;
output [1:0] pku_inst_cnt_brtaken16;
output [1:0] pku_inst_cnt_brtaken17;

output scan_out;


pku_swl_ctl swl0 (
    .tlu_halted(tlu_halted[0]),
    .dec_block_store_stall(dec_block_store_stall[0]),
    .dec_ierr_d(dec_ierr_d[0]),
    .ifu_ibuffer_write_c(ifu_ibuffer_write_c[0]),
    .ifu_buf0_inst(ifu_buf0_inst0[31:0]),
    .swl_divide_wait_all(swl_divide_wait[7:0]),
    .fgu_divide_completion(fgu_divide_completion[0]),
    .lsu_spec_enable(lsu_spec_enable[0]),
    .spc_core_running_status(spc_core_running_status[0]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[0]),
    .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[0]),
    .pku_raw_pick_p(pku_raw_pick0_p[0]),
    .tlu_flush_ifu(tlu_flush_ifu[0]),
    .dec_true_valid_e(dec_true_valid_e[0]),
    .dec_decode_d(dec_decode0_d),
    .dec_valid_d(dec_valid0_d),
    .tlu_retry_state(tlu_retry_state[0]),
    .lsu_stb_dealloc(lsu_stb_dealloc[0]),
    .lsu_stb_alloc(lsu_stb_alloc[0]),
    .lsu_block_store_kill(lsu_block_store_kill[0]),
    .lsu_sync(lsu_sync[0]),
    .lsu_complete(lsu_complete[0]),
    .dec_br_taken_e(dec_br_taken_e[0]),
    .scan_in(swl0_scanin),
    .scan_out(swl0_scanout),
    .l2clk(l2clk),
    .pku_quiesce(pku_quiesce[0]),
    .pku_lsu_p(pku_lsu_p[0]),
    .pku_fgu_p(pku_fgu_p[0]),
    .pku_pdist_p(pku_pdist_p[0]),
    .pku_twocycle_p(pku_twocycle_p[0]),
    .pku_idest_p(pku_idest_p[0]),
    .pku_fdest_p(pku_fdest_p[0]),
    .pku_isrc_rs1_p(pku_isrc_rs1_p[0]),
    .pku_isrc_rs2_p(pku_isrc_rs2_p[0]),
    .pku_isrc_rd_p(pku_isrc_rd_p[0]),
    .pku_fsrc_rd_p(pku_fsrc_rd_p[0]),
    .swl_ready_p(swl_ready_p[0]),
    .swl_spec_ready_p(swl_spec_ready_p[0]),
    .pku_load_flush_w(pku_load_flush_w[0]),
    .pku_flush_upper_buffer(pku_flush_upper_buffer[0]),
    .pku_flush_buffer0(pku_flush_buffer0[0]),
    .pku_valid_e(pku_valid_e[0]),
    .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[0]),
    .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[0]),
    .pku_flush_m(pku_flush_m[0]),
    .pku_flush_b(pku_flush_b[0]),
    .pku_flush_lm(pku_flush_lm[0]),
    .pku_flush_lb(pku_flush_lb[0]),
    .pku_flush_f1(pku_flush_f1[0]),
    .pku_flush_f2(pku_flush_f2[0]),
    .pku_inst_cnt_brtaken0(pku_inst_cnt_brtaken00[1:0]),
    .pku_inst_cnt_brtaken1(pku_inst_cnt_brtaken10[1:0]),
    .pku_ds_e(pku_ds_e[0]),
    .swl_divide_wait(swl_divide_wait[0]),
    .swl_cancel_pick_p(swl_cancel_pick_p[0]),
  .tcu_do_mode(tcu_do_mode),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

pku_swl_ctl swl1 (
    .tlu_halted(tlu_halted[1]),
    .dec_block_store_stall(dec_block_store_stall[1]),
    .dec_ierr_d(dec_ierr_d[0]),
    .ifu_ibuffer_write_c(ifu_ibuffer_write_c[1]),
    .ifu_buf0_inst(ifu_buf0_inst1[31:0]),
    .swl_divide_wait_all(swl_divide_wait[7:0]),
    .fgu_divide_completion(fgu_divide_completion[1]),
    .lsu_spec_enable(lsu_spec_enable[1]),
    .spc_core_running_status(spc_core_running_status[1]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[1]),
    .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[1]),
    .pku_raw_pick_p(pku_raw_pick0_p[1]),
    .tlu_flush_ifu(tlu_flush_ifu[1]),
    .dec_true_valid_e(dec_true_valid_e[0]),
    .dec_decode_d(dec_decode0_d),
    .dec_valid_d(dec_valid0_d),
    .tlu_retry_state(tlu_retry_state[1]),
    .lsu_stb_dealloc(lsu_stb_dealloc[1]),
    .lsu_stb_alloc(lsu_stb_alloc[1]),
    .lsu_block_store_kill(lsu_block_store_kill[1]),
    .lsu_sync(lsu_sync[1]),
    .lsu_complete(lsu_complete[1]),
    .dec_br_taken_e(dec_br_taken_e[0]),
    .scan_in(swl1_scanin),
    .scan_out(swl1_scanout),
    .l2clk(l2clk),
    .pku_quiesce(pku_quiesce[1]),
    .pku_lsu_p(pku_lsu_p[1]),
    .pku_fgu_p(pku_fgu_p[1]),
    .pku_pdist_p(pku_pdist_p[1]),
    .pku_twocycle_p(pku_twocycle_p[1]),
    .pku_idest_p(pku_idest_p[1]),
    .pku_fdest_p(pku_fdest_p[1]),
    .pku_isrc_rs1_p(pku_isrc_rs1_p[1]),
    .pku_isrc_rs2_p(pku_isrc_rs2_p[1]),
    .pku_isrc_rd_p(pku_isrc_rd_p[1]),
    .pku_fsrc_rd_p(pku_fsrc_rd_p[1]),
    .swl_ready_p(swl_ready_p[1]),
    .swl_spec_ready_p(swl_spec_ready_p[1]),
    .pku_load_flush_w(pku_load_flush_w[1]),
    .pku_flush_upper_buffer(pku_flush_upper_buffer[1]),
    .pku_flush_buffer0(pku_flush_buffer0[1]),
    .pku_valid_e(pku_valid_e[1]),
    .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[1]),
    .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[1]),
    .pku_flush_m(pku_flush_m[1]),
    .pku_flush_b(pku_flush_b[1]),
    .pku_flush_lm(pku_flush_lm[1]),
    .pku_flush_lb(pku_flush_lb[1]),
    .pku_flush_f1(pku_flush_f1[1]),
    .pku_flush_f2(pku_flush_f2[1]),
    .pku_inst_cnt_brtaken0(pku_inst_cnt_brtaken01[1:0]),
    .pku_inst_cnt_brtaken1(pku_inst_cnt_brtaken11[1:0]),
    .pku_ds_e(pku_ds_e[1]),
    .swl_divide_wait(swl_divide_wait[1]),
    .swl_cancel_pick_p(swl_cancel_pick_p[1]),
  .tcu_do_mode(tcu_do_mode),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

pku_swl_ctl swl2 (
    .tlu_halted(tlu_halted[2]),
    .dec_block_store_stall(dec_block_store_stall[2]),
    .dec_ierr_d(dec_ierr_d[0]),
    .ifu_ibuffer_write_c(ifu_ibuffer_write_c[2]),
    .ifu_buf0_inst(ifu_buf0_inst2[31:0]),
    .swl_divide_wait_all(swl_divide_wait[7:0]),
    .fgu_divide_completion(fgu_divide_completion[2]),
    .lsu_spec_enable(lsu_spec_enable[2]),
    .spc_core_running_status(spc_core_running_status[2]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[2]),
    .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[2]),
    .pku_raw_pick_p(pku_raw_pick0_p[2]),
    .tlu_flush_ifu(tlu_flush_ifu[2]),
    .dec_true_valid_e(dec_true_valid_e[0]),
    .dec_decode_d(dec_decode0_d),
    .dec_valid_d(dec_valid0_d),
    .tlu_retry_state(tlu_retry_state[2]),
    .lsu_stb_dealloc(lsu_stb_dealloc[2]),
    .lsu_stb_alloc(lsu_stb_alloc[2]),
    .lsu_block_store_kill(lsu_block_store_kill[2]),
    .lsu_sync(lsu_sync[2]),
    .lsu_complete(lsu_complete[2]),
    .dec_br_taken_e(dec_br_taken_e[0]),
    .scan_in(swl2_scanin),
    .scan_out(swl2_scanout),
    .l2clk(l2clk),
    .pku_quiesce(pku_quiesce[2]),
    .pku_lsu_p(pku_lsu_p[2]),
    .pku_fgu_p(pku_fgu_p[2]),
    .pku_pdist_p(pku_pdist_p[2]),
    .pku_twocycle_p(pku_twocycle_p[2]),
    .pku_idest_p(pku_idest_p[2]),
    .pku_fdest_p(pku_fdest_p[2]),
    .pku_isrc_rs1_p(pku_isrc_rs1_p[2]),
    .pku_isrc_rs2_p(pku_isrc_rs2_p[2]),
    .pku_isrc_rd_p(pku_isrc_rd_p[2]),
    .pku_fsrc_rd_p(pku_fsrc_rd_p[2]),
    .swl_ready_p(swl_ready_p[2]),
    .swl_spec_ready_p(swl_spec_ready_p[2]),
    .pku_load_flush_w(pku_load_flush_w[2]),
    .pku_flush_upper_buffer(pku_flush_upper_buffer[2]),
    .pku_flush_buffer0(pku_flush_buffer0[2]),
    .pku_valid_e(pku_valid_e[2]),
    .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[2]),
    .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[2]),
    .pku_flush_m(pku_flush_m[2]),
    .pku_flush_b(pku_flush_b[2]),
    .pku_flush_lm(pku_flush_lm[2]),
    .pku_flush_lb(pku_flush_lb[2]),
    .pku_flush_f1(pku_flush_f1[2]),
    .pku_flush_f2(pku_flush_f2[2]),
    .pku_inst_cnt_brtaken0(pku_inst_cnt_brtaken02[1:0]),
    .pku_inst_cnt_brtaken1(pku_inst_cnt_brtaken12[1:0]),
    .pku_ds_e(pku_ds_e[2]),
    .swl_divide_wait(swl_divide_wait[2]),
    .swl_cancel_pick_p(swl_cancel_pick_p[2]),
  .tcu_do_mode(tcu_do_mode),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

pku_swl_ctl swl3 (
    .tlu_halted(tlu_halted[3]),
    .dec_block_store_stall(dec_block_store_stall[3]),
    .dec_ierr_d(dec_ierr_d[0]),
    .ifu_ibuffer_write_c(ifu_ibuffer_write_c[3]),
    .ifu_buf0_inst(ifu_buf0_inst3[31:0]),
    .swl_divide_wait_all(swl_divide_wait[7:0]),
    .fgu_divide_completion(fgu_divide_completion[3]),
    .lsu_spec_enable(lsu_spec_enable[3]),
    .spc_core_running_status(spc_core_running_status[3]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[3]),
    .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[3]),
    .pku_raw_pick_p(pku_raw_pick0_p[3]),
    .tlu_flush_ifu(tlu_flush_ifu[3]),
    .dec_true_valid_e(dec_true_valid_e[0]),
    .dec_decode_d(dec_decode0_d),
    .dec_valid_d(dec_valid0_d),
    .tlu_retry_state(tlu_retry_state[3]),
    .lsu_stb_dealloc(lsu_stb_dealloc[3]),
    .lsu_stb_alloc(lsu_stb_alloc[3]),
    .lsu_block_store_kill(lsu_block_store_kill[3]),
    .lsu_sync(lsu_sync[3]),
    .lsu_complete(lsu_complete[3]),
    .dec_br_taken_e(dec_br_taken_e[0]),
    .scan_in(swl3_scanin),
    .scan_out(swl3_scanout),
    .l2clk(l2clk),
    .pku_quiesce(pku_quiesce[3]),
    .pku_lsu_p(pku_lsu_p[3]),
    .pku_fgu_p(pku_fgu_p[3]),
    .pku_pdist_p(pku_pdist_p[3]),
    .pku_twocycle_p(pku_twocycle_p[3]),
    .pku_idest_p(pku_idest_p[3]),
    .pku_fdest_p(pku_fdest_p[3]),
    .pku_isrc_rs1_p(pku_isrc_rs1_p[3]),
    .pku_isrc_rs2_p(pku_isrc_rs2_p[3]),
    .pku_isrc_rd_p(pku_isrc_rd_p[3]),
    .pku_fsrc_rd_p(pku_fsrc_rd_p[3]),
    .swl_ready_p(swl_ready_p[3]),
    .swl_spec_ready_p(swl_spec_ready_p[3]),
    .pku_load_flush_w(pku_load_flush_w[3]),
    .pku_flush_upper_buffer(pku_flush_upper_buffer[3]),
    .pku_flush_buffer0(pku_flush_buffer0[3]),
    .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[3]),
    .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[3]),
    .pku_valid_e(pku_valid_e[3]),
    .pku_flush_m(pku_flush_m[3]),
    .pku_flush_b(pku_flush_b[3]),
    .pku_flush_lm(pku_flush_lm[3]),
    .pku_flush_lb(pku_flush_lb[3]),
    .pku_flush_f1(pku_flush_f1[3]),
    .pku_flush_f2(pku_flush_f2[3]),
    .pku_inst_cnt_brtaken0(pku_inst_cnt_brtaken03[1:0]),
    .pku_inst_cnt_brtaken1(pku_inst_cnt_brtaken13[1:0]),
    .pku_ds_e(pku_ds_e[3]),
    .swl_divide_wait(swl_divide_wait[3]),
    .swl_cancel_pick_p(swl_cancel_pick_p[3]),
  .tcu_do_mode(tcu_do_mode),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

pku_pkd_dp pkd0 (
    .pku_raw_pick_p(pku_raw_pick0_p[3:0]),
    .dec_decode_d(dec_decode0_d),
    .dec_valid_d(dec_valid0_d),
    .swl_cancel_pick_p(swl_cancel_pick_p[3:0]),
    .pku_flush_buffer0(pku_flush_buffer0[3:0]),
    .pku_pick_p(pku_pick_p[3:0]),
    .pku_base_pick_p(pku_base_pick_p[3:0])
);

pku_pck_ctl pck0 (
    .pku_pick_p(pku_pick_p[3:0]),
    .swl_ready_p(swl_ready_p[3:0]),
    .swl_spec_ready_p(swl_spec_ready_p[3:0]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[3:0]),
    .scan_in(pck0_scanin),
    .scan_out(pck0_scanout),
    .l2clk(l2clk),
    .pku_raw_pick_p(pku_raw_pick0_p[3:0]),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);


pku_swl_ctl swl4 (
    .tlu_halted(tlu_halted[4]),
    .dec_block_store_stall(dec_block_store_stall[4]),
    .dec_ierr_d(dec_ierr_d[1]),
    .ifu_ibuffer_write_c(ifu_ibuffer_write_c[4]),
    .ifu_buf0_inst(ifu_buf0_inst4[31:0]),
    .swl_divide_wait_all(swl_divide_wait[7:0]),
    .fgu_divide_completion(fgu_divide_completion[4]),
    .lsu_spec_enable(lsu_spec_enable[4]),
    .spc_core_running_status(spc_core_running_status[4]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[4]),
    .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[4]),
    .pku_raw_pick_p(pku_raw_pick1_p[4]),
    .tlu_flush_ifu(tlu_flush_ifu[4]),
    .dec_true_valid_e(dec_true_valid_e[1]),
    .dec_decode_d(dec_decode1_d),
    .dec_valid_d(dec_valid1_d),
    .tlu_retry_state(tlu_retry_state[4]),
    .lsu_stb_dealloc(lsu_stb_dealloc[4]),
    .lsu_stb_alloc(lsu_stb_alloc[4]),
    .lsu_block_store_kill(lsu_block_store_kill[4]),
    .lsu_sync(lsu_sync[4]),
    .lsu_complete(lsu_complete[4]),
    .dec_br_taken_e(dec_br_taken_e[1]),
    .scan_in(swl4_scanin),
    .scan_out(swl4_scanout),
    .l2clk(l2clk),
    .pku_quiesce(pku_quiesce[4]),
    .pku_lsu_p(pku_lsu_p[4]),
    .pku_fgu_p(pku_fgu_p[4]),
    .pku_pdist_p(pku_pdist_p[4]),
    .pku_twocycle_p(pku_twocycle_p[4]),
    .pku_idest_p(pku_idest_p[4]),
    .pku_fdest_p(pku_fdest_p[4]),
    .pku_isrc_rs1_p(pku_isrc_rs1_p[4]),
    .pku_isrc_rs2_p(pku_isrc_rs2_p[4]),
    .pku_isrc_rd_p(pku_isrc_rd_p[4]),
    .pku_fsrc_rd_p(pku_fsrc_rd_p[4]),
    .swl_ready_p(swl_ready_p[4]),
    .swl_spec_ready_p(swl_spec_ready_p[4]),
    .pku_load_flush_w(pku_load_flush_w[4]),
    .pku_flush_upper_buffer(pku_flush_upper_buffer[4]),
    .pku_flush_buffer0(pku_flush_buffer0[4]),
    .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[4]),
    .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[4]),
    .pku_valid_e(pku_valid_e[4]),
    .pku_flush_m(pku_flush_m[4]),
    .pku_flush_b(pku_flush_b[4]),
    .pku_flush_lm(pku_flush_lm[4]),
    .pku_flush_lb(pku_flush_lb[4]),
    .pku_flush_f1(pku_flush_f1[4]),
    .pku_flush_f2(pku_flush_f2[4]),
    .pku_inst_cnt_brtaken0(pku_inst_cnt_brtaken04[1:0]),
    .pku_inst_cnt_brtaken1(pku_inst_cnt_brtaken14[1:0]),
    .pku_ds_e(pku_ds_e[4]),
    .swl_divide_wait(swl_divide_wait[4]),
    .swl_cancel_pick_p(swl_cancel_pick_p[4]),
  .tcu_do_mode(tcu_do_mode),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

pku_swl_ctl swl5 (
    .tlu_halted(tlu_halted[5]),
    .dec_block_store_stall(dec_block_store_stall[5]),
    .dec_ierr_d(dec_ierr_d[1]),
    .ifu_ibuffer_write_c(ifu_ibuffer_write_c[5]),
    .ifu_buf0_inst(ifu_buf0_inst5[31:0]),
    .swl_divide_wait_all(swl_divide_wait[7:0]),
    .fgu_divide_completion(fgu_divide_completion[5]),
    .lsu_spec_enable(lsu_spec_enable[5]),
    .spc_core_running_status(spc_core_running_status[5]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[5]),
    .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[5]),
    .pku_raw_pick_p(pku_raw_pick1_p[5]),
    .tlu_flush_ifu(tlu_flush_ifu[5]),
    .dec_true_valid_e(dec_true_valid_e[1]),
    .dec_decode_d(dec_decode1_d),
    .dec_valid_d(dec_valid1_d),
    .tlu_retry_state(tlu_retry_state[5]),
    .lsu_stb_dealloc(lsu_stb_dealloc[5]),
    .lsu_stb_alloc(lsu_stb_alloc[5]),
    .lsu_block_store_kill(lsu_block_store_kill[5]),
    .lsu_sync(lsu_sync[5]),
    .lsu_complete(lsu_complete[5]),
    .dec_br_taken_e(dec_br_taken_e[1]),
    .scan_in(swl5_scanin),
    .scan_out(swl5_scanout),
    .l2clk(l2clk),
    .pku_quiesce(pku_quiesce[5]),
    .pku_lsu_p(pku_lsu_p[5]),
    .pku_fgu_p(pku_fgu_p[5]),
    .pku_pdist_p(pku_pdist_p[5]),
    .pku_twocycle_p(pku_twocycle_p[5]),
    .pku_idest_p(pku_idest_p[5]),
    .pku_fdest_p(pku_fdest_p[5]),
    .pku_isrc_rs1_p(pku_isrc_rs1_p[5]),
    .pku_isrc_rs2_p(pku_isrc_rs2_p[5]),
    .pku_isrc_rd_p(pku_isrc_rd_p[5]),
    .pku_fsrc_rd_p(pku_fsrc_rd_p[5]),
    .swl_ready_p(swl_ready_p[5]),
    .swl_spec_ready_p(swl_spec_ready_p[5]),
    .pku_load_flush_w(pku_load_flush_w[5]),
    .pku_flush_upper_buffer(pku_flush_upper_buffer[5]),
    .pku_flush_buffer0(pku_flush_buffer0[5]),
    .pku_valid_e(pku_valid_e[5]),
    .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[5]),
    .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[5]),
    .pku_flush_m(pku_flush_m[5]),
    .pku_flush_b(pku_flush_b[5]),
    .pku_flush_lm(pku_flush_lm[5]),
    .pku_flush_lb(pku_flush_lb[5]),
    .pku_flush_f1(pku_flush_f1[5]),
    .pku_flush_f2(pku_flush_f2[5]),
    .pku_inst_cnt_brtaken0(pku_inst_cnt_brtaken05[1:0]),
    .pku_inst_cnt_brtaken1(pku_inst_cnt_brtaken15[1:0]),
    .pku_ds_e(pku_ds_e[5]),
    .swl_divide_wait(swl_divide_wait[5]),
    .swl_cancel_pick_p(swl_cancel_pick_p[5]),
  .tcu_do_mode(tcu_do_mode),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

pku_swl_ctl swl6 (
    .tlu_halted(tlu_halted[6]),
    .dec_block_store_stall(dec_block_store_stall[6]),
    .dec_ierr_d(dec_ierr_d[1]),
    .ifu_ibuffer_write_c(ifu_ibuffer_write_c[6]),
    .ifu_buf0_inst(ifu_buf0_inst6[31:0]),
    .swl_divide_wait_all(swl_divide_wait[7:0]),
    .fgu_divide_completion(fgu_divide_completion[6]),
    .lsu_spec_enable(lsu_spec_enable[6]),
    .spc_core_running_status(spc_core_running_status[6]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[6]),
    .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[6]),
    .pku_raw_pick_p(pku_raw_pick1_p[6]),
    .tlu_flush_ifu(tlu_flush_ifu[6]),
    .dec_true_valid_e(dec_true_valid_e[1]),
    .dec_decode_d(dec_decode1_d),
    .dec_valid_d(dec_valid1_d),
    .tlu_retry_state(tlu_retry_state[6]),
    .lsu_stb_dealloc(lsu_stb_dealloc[6]),
    .lsu_stb_alloc(lsu_stb_alloc[6]),
    .lsu_block_store_kill(lsu_block_store_kill[6]),
    .lsu_sync(lsu_sync[6]),
    .lsu_complete(lsu_complete[6]),
    .dec_br_taken_e(dec_br_taken_e[1]),
    .scan_in(swl6_scanin),
    .scan_out(swl6_scanout),
    .l2clk(l2clk),
    .pku_quiesce(pku_quiesce[6]),
    .pku_lsu_p(pku_lsu_p[6]),
    .pku_fgu_p(pku_fgu_p[6]),
    .pku_pdist_p(pku_pdist_p[6]),
    .pku_twocycle_p(pku_twocycle_p[6]),
    .pku_idest_p(pku_idest_p[6]),
    .pku_fdest_p(pku_fdest_p[6]),
    .pku_isrc_rs1_p(pku_isrc_rs1_p[6]),
    .pku_isrc_rs2_p(pku_isrc_rs2_p[6]),
    .pku_isrc_rd_p(pku_isrc_rd_p[6]),
    .pku_fsrc_rd_p(pku_fsrc_rd_p[6]),
    .swl_ready_p(swl_ready_p[6]),
    .swl_spec_ready_p(swl_spec_ready_p[6]),
    .pku_load_flush_w(pku_load_flush_w[6]),
    .pku_flush_upper_buffer(pku_flush_upper_buffer[6]),
    .pku_flush_buffer0(pku_flush_buffer0[6]),
    .pku_valid_e(pku_valid_e[6]),
    .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[6]),
    .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[6]),
    .pku_flush_m(pku_flush_m[6]),
    .pku_flush_b(pku_flush_b[6]),
    .pku_flush_lm(pku_flush_lm[6]),
    .pku_flush_lb(pku_flush_lb[6]),
    .pku_flush_f1(pku_flush_f1[6]),
    .pku_flush_f2(pku_flush_f2[6]),
    .pku_inst_cnt_brtaken0(pku_inst_cnt_brtaken06[1:0]),
    .pku_inst_cnt_brtaken1(pku_inst_cnt_brtaken16[1:0]),
    .pku_ds_e(pku_ds_e[6]),
    .swl_divide_wait(swl_divide_wait[6]),
    .swl_cancel_pick_p(swl_cancel_pick_p[6]),
  .tcu_do_mode(tcu_do_mode),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

pku_swl_ctl swl7 (
    .tlu_halted(tlu_halted[7]),
    .dec_block_store_stall(dec_block_store_stall[7]),
    .dec_ierr_d(dec_ierr_d[1]),
    .ifu_ibuffer_write_c(ifu_ibuffer_write_c[7]),
    .ifu_buf0_inst(ifu_buf0_inst7[31:0]),
    .swl_divide_wait_all(swl_divide_wait[7:0]),
    .fgu_divide_completion(fgu_divide_completion[7]),
    .lsu_spec_enable(lsu_spec_enable[7]),
    .spc_core_running_status(spc_core_running_status[7]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[7]),
    .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[7]),
    .pku_raw_pick_p(pku_raw_pick1_p[7]),
    .tlu_flush_ifu(tlu_flush_ifu[7]),
    .dec_true_valid_e(dec_true_valid_e[1]),
    .dec_decode_d(dec_decode1_d),
    .dec_valid_d(dec_valid1_d),
    .tlu_retry_state(tlu_retry_state[7]),
    .lsu_stb_dealloc(lsu_stb_dealloc[7]),
    .lsu_stb_alloc(lsu_stb_alloc[7]),
    .lsu_block_store_kill(lsu_block_store_kill[7]),
    .lsu_sync(lsu_sync[7]),
    .lsu_complete(lsu_complete[7]),
    .dec_br_taken_e(dec_br_taken_e[1]),
    .scan_in(swl7_scanin),
    .scan_out(swl7_scanout),
    .l2clk(l2clk),
    .pku_quiesce(pku_quiesce[7]),
    .pku_lsu_p(pku_lsu_p[7]),
    .pku_fgu_p(pku_fgu_p[7]),
    .pku_pdist_p(pku_pdist_p[7]),
    .pku_twocycle_p(pku_twocycle_p[7]),
    .pku_idest_p(pku_idest_p[7]),
    .pku_fdest_p(pku_fdest_p[7]),
    .pku_isrc_rs1_p(pku_isrc_rs1_p[7]),
    .pku_isrc_rs2_p(pku_isrc_rs2_p[7]),
    .pku_isrc_rd_p(pku_isrc_rd_p[7]),
    .pku_fsrc_rd_p(pku_fsrc_rd_p[7]),
    .swl_ready_p(swl_ready_p[7]),
    .swl_spec_ready_p(swl_spec_ready_p[7]),
    .pku_load_flush_w(pku_load_flush_w[7]),
    .pku_flush_upper_buffer(pku_flush_upper_buffer[7]),
    .pku_flush_buffer0(pku_flush_buffer0[7]),
    .pku_valid_e(pku_valid_e[7]),
    .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[7]),
    .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[7]),
    .pku_flush_m(pku_flush_m[7]),
    .pku_flush_b(pku_flush_b[7]),
    .pku_flush_lm(pku_flush_lm[7]),
    .pku_flush_lb(pku_flush_lb[7]),
    .pku_flush_f1(pku_flush_f1[7]),
    .pku_flush_f2(pku_flush_f2[7]),
    .pku_inst_cnt_brtaken0(pku_inst_cnt_brtaken07[1:0]),
    .pku_inst_cnt_brtaken1(pku_inst_cnt_brtaken17[1:0]),
    .pku_ds_e(pku_ds_e[7]),
    .swl_divide_wait(swl_divide_wait[7]),
    .swl_cancel_pick_p(swl_cancel_pick_p[7]),
  .tcu_do_mode(tcu_do_mode),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);


pku_pkd_dp pkd1 (
    .pku_raw_pick_p(pku_raw_pick1_p[7:4]),
    .dec_decode_d(dec_decode1_d),
    .dec_valid_d(dec_valid1_d),
    .swl_cancel_pick_p(swl_cancel_pick_p[7:4]),
    .pku_flush_buffer0(pku_flush_buffer0[7:4]),
    .pku_pick_p(pku_pick_p[7:4]),
    .pku_base_pick_p(pku_base_pick_p[7:4])
);

pku_pck_ctl pck1 (
    .pku_pick_p(pku_pick_p[7:4]),
    .swl_ready_p(swl_ready_p[7:4]),
    .swl_spec_ready_p(swl_spec_ready_p[7:4]),
    .ifu_buf0_valid_p(ifu_buf0_valid_p[7:4]),
    .scan_in(pck1_scanin),
    .scan_out(pck1_scanout),
    .l2clk(l2clk),
    .pku_raw_pick_p(pku_raw_pick1_p[7:4]),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

// fixscan start:
assign swl0_scanin               = scan_in                  ;
assign swl1_scanin               = swl0_scanout             ;
assign swl2_scanin               = swl1_scanout             ;
assign swl3_scanin               = swl2_scanout             ;
assign pck0_scanin               = swl3_scanout             ;
assign swl4_scanin               = pck0_scanout             ;
assign swl5_scanin               = swl4_scanout             ;
assign swl6_scanin               = swl5_scanout             ;
assign swl7_scanin               = swl6_scanout             ;
assign pck1_scanin               = swl7_scanout             ;
assign scan_out                  = pck1_scanout             ;
// fixscan end:
endmodule
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pku_pck_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module pku_pck_ctl (
  lsu_pku_pmen, 
  pku_pick_p, 
  swl_ready_p, 
  swl_spec_ready_p, 
  ifu_buf0_valid_p, 
  scan_in, 
  l2clk, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  pku_raw_pick_p, 
  scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire pick_en;
wire [3:0] nsready;
wire [3:0] sready;
wire l1clk_pm1;
wire spares_scanin;
wire spares_scanout;
wire nspick_sel;
wire [3:0] nspick;
wire [7:0] lru;
wire [3:0] spick;
wire [3:0] ipick;
wire [7:0] nlru;
wire any_pick;
wire [7:0] real_nlru_in;
wire [7:0] lru_out;
wire lruf_scanin;
wire lruf_scanout;


input lsu_pku_pmen;		// power management enable for pku
input [3:0] pku_pick_p;	        // from datapath logic

input [3:0] swl_ready_p;        // thread is in ready state
input [3:0] swl_spec_ready_p;	// thread is in speculative ready state
input [3:0] ifu_buf0_valid_p;	// oldest instruction for thread i is valid
input scan_in;
input l2clk;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;
input tcu_scan_en;


output [3:0] pku_raw_pick_p;  // raw pick signals to mux the pc addresses in the ifu (no swl_cancel_pick or decode cancel)
output scan_out;

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
assign se = tcu_scan_en;
// end scan


assign pick_en = (|nsready[3:0]) | (|sready[3:0]) | ~lsu_pku_pmen;

pku_pck_ctl_l1clkhdr_ctl_macro clkgen (
 .l2clk(l2clk),
 .l1en (pick_en ),
 .l1clk(l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

pku_pck_ctl_spare_ctl_macro__num_1 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);

assign nsready[3:0] = (swl_ready_p[3:0] & ifu_buf0_valid_p[3:0]);

assign nspick_sel = |nsready[3:0];

// 0in value -var nspick[3:0]  -val 4'b0000 4'b0001 4'b0010 4'b0100 4'b1000
// 0in value -var spick[3:0]  -val 4'b0000 4'b0001 4'b0010 4'b0100 4'b1000
// 0in value -var ipick[3:0]  -val 4'b0000 4'b0001 4'b0010 4'b0100 4'b1000

assign nspick[3] = (nsready[3]&!nsready[1]&!nsready[0]&lru[1]&!lru[0]) | (nsready[3]
    &!nsready[2]&!nsready[0]&!lru[1]&lru[0]) | (nsready[3]&!nsready[1]&!lru[2]
    &!lru[0]) | (nsready[3]&!nsready[2]&!lru[3]&!lru[1]) | (nsready[3]&!nsready[2]
    &!nsready[1]&!lru[1]&!lru[0]) | (nsready[3]&!nsready[0]&!lru[7]&!lru[6]
    &lru[5]&lru[4]) | (nsready[3]&lru[7]&lru[6]) | (nsready[3]&!nsready[2]
    &!nsready[1]&!nsready[0]);

assign nspick[2] = (!nsready[3]&nsready[2]&!nsready[1]&!lru[1]&!lru[0]) | (nsready[2]
    &!nsready[1]&!nsready[0]&lru[1]&lru[0]) | (nsready[2]&!nsready[0]&lru[2]
    &lru[0]) | (!nsready[3]&nsready[2]&!lru[3]&!lru[1]) | (!nsready[3]&nsready[2]
    &!nsready[0]&!lru[1]&lru[0]) | (nsready[2]&!nsready[1]&!lru[7]&lru[6]
    &lru[5]&!lru[4]) | (nsready[2]&lru[7]&!lru[6]) | (!nsready[3]&nsready[2]
    &!nsready[1]&!nsready[0]);

assign nspick[1] = (!nsready[3]&!nsready[2]&nsready[1]&!lru[1]&!lru[0]) | (!nsready[2]
    &nsready[1]&!nsready[0]&lru[1]&lru[0]) | (!nsready[3]&nsready[1]&!lru[2]
    &!lru[0]) | (nsready[1]&!nsready[0]&lru[3]&lru[1]) | (!nsready[3]&nsready[1]
    &!nsready[0]&lru[1]&!lru[0]) | (!nsready[2]&nsready[1]&lru[7]&!lru[6]
    &!lru[5]&lru[4]) | (nsready[1]&!lru[7]&lru[6]) | (!nsready[3]&!nsready[2]
    &nsready[1]&!nsready[0]);

assign nspick[0] = (!nsready[3]&!nsready[1]&nsready[0]&lru[1]&!lru[0]) | (!nsready[3]
    &!nsready[2]&nsready[0]&!lru[1]&lru[0]) | (!nsready[2]&nsready[0]&lru[2]
    &lru[0]) | (!nsready[1]&nsready[0]&lru[3]&lru[1]) | (!nsready[2]&!nsready[1]
    &nsready[0]&lru[1]&lru[0]) | (!nsready[3]&nsready[0]&lru[7]&lru[6]&!lru[5]
    &!lru[4]) | (nsready[0]&!lru[7]&!lru[6]) | (!nsready[3]&!nsready[2]
    &!nsready[1]&nsready[0]);

assign sready[3:0] = (swl_spec_ready_p[3:0] & ifu_buf0_valid_p[3:0]);

assign spick[3] = (sready[3]&!sready[1]&!sready[0]&lru[1]&!lru[0]) | (sready[3]
    &!sready[2]&!sready[0]&!lru[1]&lru[0]) | (sready[3]&!sready[1]&!lru[2]
    &!lru[0]) | (sready[3]&!sready[2]&!lru[3]&!lru[1]) | (sready[3]&!sready[2]
    &!sready[1]&!lru[1]&!lru[0]) | (sready[3]&!sready[0]&!lru[7]&!lru[6]
    &lru[5]&lru[4]) | (sready[3]&lru[7]&lru[6]) | (sready[3]&!sready[2]
    &!sready[1]&!sready[0]);

assign spick[2] = (!sready[3]&sready[2]&!sready[1]&!lru[1]&!lru[0]) | (sready[2]
    &!sready[1]&!sready[0]&lru[1]&lru[0]) | (sready[2]&!sready[0]&lru[2]
    &lru[0]) | (!sready[3]&sready[2]&!lru[3]&!lru[1]) | (!sready[3]&sready[2]
    &!sready[0]&!lru[1]&lru[0]) | (sready[2]&!sready[1]&!lru[7]&lru[6]
    &lru[5]&!lru[4]) | (sready[2]&lru[7]&!lru[6]) | (!sready[3]&sready[2]
    &!sready[1]&!sready[0]);

assign spick[1] = (!sready[3]&!sready[2]&sready[1]&!lru[1]&!lru[0]) | (!sready[2]
    &sready[1]&!sready[0]&lru[1]&lru[0]) | (!sready[3]&sready[1]&!lru[2]
    &!lru[0]) | (sready[1]&!sready[0]&lru[3]&lru[1]) | (!sready[3]&sready[1]
    &!sready[0]&lru[1]&!lru[0]) | (!sready[2]&sready[1]&lru[7]&!lru[6]
    &!lru[5]&lru[4]) | (sready[1]&!lru[7]&lru[6]) | (!sready[3]&!sready[2]
    &sready[1]&!sready[0]);

assign spick[0] = (!sready[3]&!sready[1]&sready[0]&lru[1]&!lru[0]) | (!sready[3]
    &!sready[2]&sready[0]&!lru[1]&lru[0]) | (!sready[2]&sready[0]&lru[2]
    &lru[0]) | (!sready[1]&sready[0]&lru[3]&lru[1]) | (!sready[2]&!sready[1]
    &sready[0]&lru[1]&lru[0]) | (!sready[3]&sready[0]&lru[7]&lru[6]&!lru[5]
    &!lru[4]) | (sready[0]&!lru[7]&!lru[6]) | (!sready[3]&!sready[2]
    &!sready[1]&sready[0]);

assign ipick[3:0] = ({4{nspick_sel}} & nspick[3:0]) |
		   ({4{~nspick_sel}} & spick[3:0]);

assign pku_raw_pick_p[3:0] = ipick[3:0];

// lru is msb pair of the lru vector
assign nlru[7] = (ipick[0]&!lru[6]&lru[5]) | (ipick[1]&lru[6]&lru[5]) | (!lru[3]
    &!lru[1]) | (!ipick[2]&lru[7]&!lru[6]) | (!ipick[3]&lru[7]&lru[6]);

assign nlru[6] = (ipick[0]&!lru[7]&lru[4]) | (ipick[2]&lru[7]&lru[4]) | (!lru[2]
    &!lru[0]) | (!ipick[1]&!lru[7]&lru[6]) | (!ipick[3]&lru[7]&lru[6]);

assign nlru[5] = (!ipick[3]&!ipick[0]&lru[5]&lru[4]&lru[2]&lru[1]) | (ipick[0]
    &!lru[1]&lru[0]) | (ipick[1]&lru[3]&lru[1]) | (ipick[3]&lru[3]&!lru[2]
    &!lru[1]) | (ipick[0]&!lru[7]&lru[3]) | (ipick[2]&lru[3]&lru[2]&!lru[1]) | (
    ipick[1]&lru[3]&!lru[0]) | (!ipick[2]&!ipick[0]&!lru[7]&lru[5]&!lru[4]
    &lru[2]) | (!ipick[3]&!ipick[1]&!lru[7]&lru[5]&lru[4]&!lru[2]) | (
    !ipick[2]&!ipick[1]&!lru[7]&lru[5]&!lru[2]&lru[0]) | (!ipick[3]&!ipick[2]
    &lru[5]&!lru[1]);

assign nlru[4] = (ipick[0]&lru[1]&!lru[0]) | (ipick[2]&lru[2]&lru[0]) | (!ipick[3]
    &!ipick[2]&lru[4]&!lru[3]&!lru[1]) | (ipick[3]&!lru[3]&lru[2]&!lru[0]) | (
    ipick[0]&!lru[6]&lru[2]) | (ipick[1]&lru[3]&lru[2]&!lru[0]) | (ipick[2]
    &lru[2]&!lru[1]) | (!ipick[3]&!ipick[0]&!lru[7]&!lru[6]&lru[5]&lru[4]) | (
    !ipick[1]&!ipick[0]&!lru[6]&!lru[5]&lru[4]&lru[3]) | (!ipick[2]&!ipick[1]
    &!lru[6]&lru[4]&!lru[3]&lru[1]) | (!ipick[3]&!ipick[1]&lru[4]&!lru[0]);

assign nlru[3] = (ipick[3]&lru[1]&!lru[0]) | (ipick[2]&lru[1]&lru[0]) | (!ipick[3]
    &!ipick[2]&!ipick[1]&lru[3]&!lru[0]) | (!ipick[3]&!ipick[2]&!ipick[0]
    &lru[3]&lru[0]) | (ipick[1]&lru[1]) | (ipick[0]&lru[1]) | (lru[3]
    &lru[1]);

assign nlru[2] = (ipick[3]&!lru[1]&lru[0]) | (ipick[1]&lru[1]&lru[0]) | (lru[2]
    &lru[0]) | (!ipick[3]&!ipick[2]&!ipick[1]&lru[2]&!lru[1]) | (!ipick[3]
    &!ipick[1]&!ipick[0]&lru[2]&lru[1]) | (ipick[2]&lru[0]) | (ipick[0]
    &lru[0]);

assign nlru[1] = (!ipick[1]&!ipick[0]&lru[1]) | (ipick[3]) | (ipick[2]);

assign nlru[0] = (!ipick[2]&!ipick[0]&lru[0]) | (ipick[3]) | (ipick[1]);

// only update the lru with the actual pick signals
assign any_pick = |pku_pick_p[3:0];

assign real_nlru_in[7:0] = ({8{any_pick}} & {nlru[7],nlru[6],nlru[5],~nlru[4],~nlru[3],nlru[2],~nlru[1],~nlru[0]}) |
			   ({8{!any_pick}} & lru_out[7:0]);

pku_pck_ctl_msff_ctl_macro__width_8 lruf  (
 .scan_in(lruf_scanin),
 .scan_out(lruf_scanout),
 .l1clk(l1clk_pm1),
 .din  (real_nlru_in[7:0]),
 .dout (lru_out[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
assign lru[7:0] = {lru_out[7],lru_out[6],lru_out[5],~lru_out[4],~lru_out[3],lru_out[2],~lru_out[1],~lru_out[0]};


supply0 vss;
supply1 vdd;
// fixscan start:
assign spares_scanin             = scan_in                  ;
assign lruf_scanin               = spares_scanout           ;
assign scan_out                  = lruf_scanout             ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module pku_pck_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module pku_pck_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule


// any PARAMS parms go into naming of macro

module pku_pck_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pku_pkd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module pku_pkd_dp (
  dec_valid_d, 
  dec_decode_d, 
  swl_cancel_pick_p, 
  pku_flush_buffer0, 
  pku_raw_pick_p, 
  pku_base_pick_p, 
  pku_pick_p);
wire [3:0] cancel_pick_p_;
wire [3:0] flush_buffer0_;
wire valid_d_;
wire decode_cancel;
wire [3:0] qraw_pick_;
wire [3:0] qraw_pick;
wire [3:0] early0;
wire [3:0] base_pick_p_;
wire [3:0] final_pick_p_;


input dec_valid_d;		// inst is valid at decode for relevant TG
input dec_decode_d;	        // decoded inst at decode for relevant TG
input [3:0] swl_cancel_pick_p;	// cancel pick for thread i
input [3:0] pku_flush_buffer0;	// flush oldest instruction for thread i
input [3:0] pku_raw_pick_p;	// raw_pick

output [3:0] pku_base_pick_p;
output [3:0] pku_pick_p;


// assign pku_base_pick_p[3:0] = ~swl_cancel_pick_p[3:0] & pku_raw_pick_p[3:0] & ~pku_flush_buffer0[3:0];

// assign pku_pick_p[3:0] = ~swl_cancel_pick_p[3:0] & ~{4{dec_valid_d & ~dec_decode_d}} & pku_raw_pick_p[3:0] & ~pku_flush_buffer0[3:0];

pku_pkd_dp_inv_macro__dinv_12x__width_4 inv00  (
	.din(swl_cancel_pick_p[3:0]),
	.dout(cancel_pick_p_[3:0])
);

pku_pkd_dp_inv_macro__dinv_8x__width_4 inv01  (
	.din(pku_flush_buffer0[3:0]),
	.dout(flush_buffer0_[3:0])
);

pku_pkd_dp_inv_macro__dinv_6x__width_1 inv02  (
	.din(dec_valid_d),
	.dout(valid_d_)
);

pku_pkd_dp_nor_macro__dnor_8x__ports_2__width_1 nor02  (
	.din0(dec_decode_d),
	.din1(valid_d_),
	.dout(decode_cancel)
);

pku_pkd_dp_nand_macro__dnand_12x__ports_2__width_4 nand03  (
	.din0(pku_raw_pick_p[3:0]),	
	.din1(flush_buffer0_[3:0]),
	.dout(qraw_pick_[3:0])
);

pku_pkd_dp_inv_macro__dinv_8x__width_4 inv05  (
	.din(qraw_pick_[3:0]),
	.dout(qraw_pick[3:0])
);

pku_pkd_dp_nor_macro__dnor_12x__ports_2__width_4 nor01  (
	.din0({4{decode_cancel}}),
	.din1(qraw_pick_[3:0]),
	.dout(early0[3:0])
);


pku_pkd_dp_nand_macro__dnand_12x__ports_2__width_4 nand01  (
	.din0(cancel_pick_p_[3:0]),
	.din1(qraw_pick[3:0]),
	.dout(base_pick_p_[3:0])
);


pku_pkd_dp_inv_macro__dinv_28x__width_4 inv03  (
	.din(base_pick_p_[3:0]),
	.dout(pku_base_pick_p[3:0])
);


pku_pkd_dp_nand_macro__dnand_20x__ports_2__width_4 nand02  (
	.din0(cancel_pick_p_[3:0]),
	.din1(early0[3:0]),
	.dout(final_pick_p_[3:0])
);


pku_pkd_dp_inv_macro__dinv_56x__width_4 inv04  (
	.din(final_pick_p_[3:0]),
	.dout(pku_pick_p[3:0])
);

endmodule


//
//   invert macro
//
//


module pku_pkd_dp_inv_macro__dinv_12x__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module pku_pkd_dp_inv_macro__dinv_8x__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module pku_pkd_dp_inv_macro__dinv_6x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module pku_pkd_dp_nor_macro__dnor_8x__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module pku_pkd_dp_nand_macro__dnand_12x__ports_2__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


nand2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module pku_pkd_dp_nor_macro__dnor_12x__ports_2__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


nor2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module pku_pkd_dp_inv_macro__dinv_28x__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module pku_pkd_dp_nand_macro__dnand_20x__ports_2__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


nand2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module pku_pkd_dp_inv_macro__dinv_56x__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pku_swl_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module pku_swl_ctl (
  tlu_halted, 
  dec_block_store_stall, 
  dec_ierr_d, 
  tcu_do_mode, 
  lsu_pku_pmen, 
  spc_core_running_status, 
  lsu_spec_enable, 
  ifu_ibuffer_write_c, 
  ifu_buf0_inst, 
  lsu_stb_alloc, 
  lsu_stb_dealloc, 
  lsu_block_store_kill, 
  swl_divide_wait_all, 
  fgu_divide_completion, 
  ifu_buf0_valid_p, 
  ifu_upper_buffer_valid_p, 
  pku_raw_pick_p, 
  tlu_flush_ifu, 
  tlu_retry_state, 
  dec_valid_d, 
  dec_decode_d, 
  dec_true_valid_e, 
  lsu_sync, 
  lsu_complete, 
  dec_br_taken_e, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  swl_ready_p, 
  swl_spec_ready_p, 
  pku_inst_cnt_brtaken0, 
  pku_inst_cnt_brtaken1, 
  pku_annul_ds_dcti_brtaken0_e, 
  pku_annul_ds_dcti_brtaken1_e, 
  pku_load_flush_w, 
  pku_flush_upper_buffer, 
  pku_flush_buffer0, 
  pku_valid_e, 
  pku_flush_m, 
  pku_flush_b, 
  pku_flush_lm, 
  pku_flush_lb, 
  pku_flush_f1, 
  pku_flush_f2, 
  pku_ds_e, 
  swl_divide_wait, 
  swl_cancel_pick_p, 
  pku_quiesce, 
  scan_out, 
  pku_lsu_p, 
  pku_fgu_p, 
  pku_pdist_p, 
  pku_twocycle_p, 
  pku_idest_p, 
  pku_fdest_p, 
  pku_fsrc_rd_p, 
  pku_isrc_rs1_p, 
  pku_isrc_rs2_p, 
  pku_isrc_rd_p);
wire l1clk;
wire spares_scanin;
wire spares_scanout;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire illegal_p;
wire [31:0] i;
wire isrc_rs1_u;
wire isrc_rs2_u;
wire isrc_rd_u;
wire idest_u;
wire fsrc_rs1_u;
wire fsrc_rs2_u;
wire fsrc_rd_u;
wire fdest_u;
wire fgu_u;
wire dcti_u;
wire specbr_u;
wire specld_u;
wire specfp_u;
wire lsu_u;
wire postsync_u;
wire div_u;
wire pdist_u;
wire condbr_u;
wire callclass_u;
wire fccsrc_u;
wire fsrsync_u;
wire twocycle_u;
wire bkick_u;
wire fbkick_u;
wire fccdest_u;
wire fpdest_single_u;
wire fpdest_double_u;
wire fpsrc_single_u;
wire fpsrc_double_u;
wire store_u;
wire windowsync_u;
wire fsrc_rs1_p;
wire fsrc_rs2_p;
wire dcti_p;
wire specbr_p;
wire specld_p;
wire specfp_p;
wire postsync_p;
wire do_mode_f;
wire div_p;
wire condbr_p;
wire callclass_p;
wire fccsrc_p;
wire fsrsync_p;
wire bkick_p;
wire fbkick_p;
wire fccdest_p;
wire fpdest_single_p;
wire fpdest_double_p;
wire fpsrc_single_p;
wire fpsrc_double_p;
wire store_p;
wire windowsync_p;
wire do_modef_scanin;
wire do_modef_scanout;
wire l1clk_pm1;
wire [4:0] rs1;
wire [4:0] rs2;
wire [4:0] rd;
wire annul;
wire vld_p;
wire vld_1;
wire valid;
wire vld_d;
wire vld_e;
wire vld_m;
wire vld_b;
wire vld_w;
wire vld_f4;
wire vld_f5;
wire vld_fb;
wire lsu_sync_wait;
wire pick_clken;
wire vldraw_d;
wire vldraw_e;
wire vldraw_m;
wire ext_flush;
wire thread_active;
wire l1clk_pm2;
wire active_clken;
wire external_flushf_scanin;
wire external_flushf_scanout;
wire lsu_ext_flush_in;
wire lsu_ext_flushf_scanin;
wire lsu_ext_flushf_scanout;
wire lsu_ext_flush_w;
wire divide_wait_outstanding;
wire fpdouble_wait;
wire fpdest_single_d;
wire fpdest_single_e;
wire fpdest_single_m;
wire lsu_b;
wire fpdest_single_b;
wire lsu_w;
wire fpdest_single_w;
wire lsu_f4;
wire fpdest_single_f4;
wire fpdouble_cancel;
wire lsu_f5;
wire fpdest_single_f5;
wire fpsingle_wait;
wire fpdest_double_d;
wire fpdest_double_e;
wire fpdest_double_m;
wire fpdest_double_b;
wire fpdest_double_w;
wire fpdest_double_f4;
wire fpsingle_cancel;
wire fpdest_double_f5;
wire fccdep_wait;
wire fccdest_d;
wire fccdest_e;
wire fccdest_m;
wire fccdep_cancel;
wire fccdest_b;
wire fsrsync_wait;
wire fgu_d;
wire fgu_e;
wire fgu_m;
wire fgu_b;
wire fgu_w;
wire fsrsync_cancel;
wire check_rs1_d;
wire idest_d;
wire specld_d;
wire fdest_d;
wire check_rs2_d;
wire check_rd_d;
wire check_rs1_e;
wire idest_e;
wire specld_e;
wire fdest_e;
wire check_rs2_e;
wire check_rd_e;
wire check_rs1_m;
wire fdest_m;
wire check_rs2_m;
wire check_rd_m;
wire check_rs1_b;
wire fdest_b;
wire check_rs2_b;
wire check_rd_b;
wire check_rs1_w;
wire fdest_w;
wire check_rs2_w;
wire check_rd_w;
wire cmp_rs1_rd_d;
wire [4:0] rd_d;
wire cmp_rs2_rd_d;
wire cmp_rd_rd_d;
wire cmp_rs1_rd_e;
wire [4:0] rd_e;
wire cmp_rs2_rd_e;
wire cmp_rd_rd_e;
wire cmp_rs1_rd_m;
wire [4:0] rd_m;
wire cmp_rs2_rd_m;
wire cmp_rd_rd_m;
wire cmp_rs1_rd_b;
wire [4:0] rd_b;
wire cmp_rs2_rd_b;
wire cmp_rd_rd_b;
wire cmp_rs1_rd_w;
wire [4:0] rd_w;
wire cmp_rs2_rd_w;
wire cmp_rd_rd_w;
wire dependent_cancel;
wire wait_rs1_d;
wire wait_rs2_d;
wire wait_rd_d;
wire wait_rs1_e;
wire wait_rs2_e;
wire wait_rd_e;
wire wait_rd_m;
wire wait_rd_b;
wire dependent_wait;
wire tlu_retryf_scanin;
wire tlu_retryf_scanout;
wire retry_state;
wire block_store_stallf_scanin;
wire block_store_stallf_scanout;
wire [1:0] block_store_stall;
wire full_scnt;
wire lsu_sync_raw_w;
wire dcti_d;
wire dcti_e;
wire any_twocycle_m;
wire divide_wait1;
wire stb_cancel;
wire ldst_sync_single;
wire ldst_sync_ldfsr;
wire restore_scnt;
wire pick_raw_p;
wire pick_p;
wire actual_pick_p;
wire flush_p;
wire actual_raw_pick_p;
wire rawflush_p;
wire set_postsync;
wire clear_postsync;
wire postsync_d;
wire flush_d;
wire postsync_e;
wire flush_e;
wire bkick_w;
wire fbkick_fb;
wire br_mispredict_m;
wire callclass_m;
wire bkick_m;
wire postsync_in;
wire post_sync;
wire post_syncf_scanin;
wire post_syncf_scanout;
wire spec_enf_scanin;
wire spec_enf_scanout;
wire spec_en;
wire active_threadf_scanin;
wire active_threadf_scanout;
wire set_postsync_ns;
wire clear_postsync_ns;
wire specbr_m;
wire specld_b;
wire fpvld_w2;
wire lsu_sync_w;
wire postsync_ns_in;
wire postsync_ns;
wire postsync_nsf_scanin;
wire postsync_nsf_scanout;
wire set_dep_wait;
wire clear_dep_wait;
wire dep_wait_in;
wire set_dcti_wait;
wire clear_dcti_wait;
wire dcti_wait_in;
wire set_dcti_couple_wait;
wire clear_dcti_couple_wait;
wire dcti_couple_wait_in;
wire flush_div;
wire div_d;
wire div_e;
wire set_divide_wait_in;
wire clear_divide_wait_in;
wire divide_wait_in;
wire divide_waitf_scanin;
wire divide_waitf_scanout;
wire divide_wait1f_scanin;
wire divide_wait1f_scanout;
wire otherdivide_wait_in;
wire lsu_completef_scanin;
wire lsu_completef_scanout;
wire lsu_complete_d1;
wire lsu_complete_d2;
wire set_lsu_sync_wait;
wire clear_lsu_sync_wait;
wire lsu_sync_wait_in;
wire lsu_sync_waitf_scanin;
wire lsu_sync_waitf_scanout;
wire clear_lsu_sync_single;
wire ldst_sync_single_in;
wire ldst_sync_singlef_scanin;
wire ldst_sync_singlef_scanout;
wire clear_lsu_sync_ldfsr;
wire fsrsync_w;
wire specld_w;
wire idest_w;
wire ldst_sync_ldfsr_in;
wire ldst_sync_ldfsrf_scanin;
wire ldst_sync_ldfsrf_scanout;
wire br_flush1_in;
wire br_mispredict_e;
wire brflush1_f_scanin;
wire brflush1_f_scanout;
wire br_flush1;
wire br_flush2_in;
wire brflush2_f_scanin;
wire brflush2_f_scanout;
wire brflush2;
wire not_annul_ds1_in;
wire annul_ds_dcti_e;
wire not_annul_ds1_f_scanin;
wire not_annul_ds1_f_scanout;
wire not_annul_ds1;
wire not_annul_ds2_in;
wire not_annul_ds2_f_scanin;
wire not_annul_ds2_f_scanout;
wire not_annul_ds2;
wire store_ds1_in;
wire pick_store_d;
wire store_ds1_f_scanin;
wire store_ds1_f_scanout;
wire store_ds1;
wire store_ds2_in;
wire store_ds2_f_scanin;
wire store_ds2_f_scanout;
wire store_ds2;
wire store_ds;
wire pick_store_p;
wire late_flush_p;
wire pickstoref_scanin;
wire pickstoref_scanout;
wire alloc_scnt;
wire dealloc_scnt;
wire inc_scnt_raw;
wire dec_scnt_raw;
wire hold_scnt_raw;
wire annul_store_in;
wire annul_store_f_scanin;
wire annul_store_f_scanout;
wire annul_store_d;
wire inc_scnt;
wire dec1_scnt;
wire hold_scnt;
wire dec2_scnt;
wire inc2_ccnt;
wire inc_ccnt_raw;
wire inc1_ccnt;
wire hold_ccnt_raw;
wire hold_ccnt;
wire dec_ccnt_raw;
wire dec1_ccnt;
wire [3:0] ccnt_in;
wire [3:0] ccnt;
wire [3:0] scnt_in;
wire [3:0] scnt;
wire scnt_f_scanin;
wire scnt_f_scanout;
wire alloc_ccnt;
wire dealloc_ccnt;
wire [3:0] ccnt_raw_in;
wire ccnt_f_scanin;
wire ccnt_f_scanout;
wire stb_wait_in;
wire rdy_in;
wire spec_in;
wire vld_d_in;
wire specbr_d_in;
wire specld_d_in;
wire vld_e_in;
wire specbr_e_in;
wire specld_e_in;
wire vld_m_in;
wire specld_m_in;
wire vld_b_in;
wire specld_b_in;
wire vld_w_in;
wire specld_w_in;
wire ready_in;
wire readyf_scanin;
wire readyf_scanout;
wire spec_ready_in;
wire spec_readyf_scanin;
wire spec_readyf_scanout;
wire allds_actual_p;
wire allds_p;
wire allds_is_p;
wire allds_actual_d;
wire allds_d;
wire allds_is_d;
wire allds_p_in;
wire allds_p_f_scanin;
wire allds_p_f_scanout;
wire allds_d_in;
wire allds_d_f_scanin;
wire allds_d_f_scanout;
wire allds_e_in;
wire allds_e_f_scanin;
wire allds_e_f_scanout;
wire set_vld_d;
wire clear_vld_d;
wire vld_df_scanin;
wire vld_df_scanout;
wire vld_ef_scanin;
wire vld_ef_scanout;
wire valid_e;
wire valid_e_in;
wire valid_ef_scanin;
wire valid_ef_scanout;
wire vld_mf_scanin;
wire vld_mf_scanout;
wire flush_m;
wire vld_bf_scanin;
wire vld_bf_scanout;
wire flush_b;
wire vld_wf_scanin;
wire vld_wf_scanout;
wire fpvld_w1_in;
wire specfp_w;
wire fpvld_w1f_scanin;
wire fpvld_w1f_scanout;
wire fpvld_w1;
wire fpvld_w2_in;
wire fpvld_w2f_scanin;
wire fpvld_w2f_scanout;
wire set_vldraw_d;
wire clear_vldraw_d;
wire rawflush_d;
wire vldraw_d_in;
wire vldraw_df_scanin;
wire vldraw_df_scanout;
wire vldraw_e_in;
wire vldraw_ef_scanin;
wire vldraw_ef_scanout;
wire vldraw_m_in;
wire vldraw_mf_scanin;
wire vldraw_mf_scanout;
wire annul_ds_dcti_mf_scanin;
wire annul_ds_dcti_mf_scanout;
wire annul_ds_dcti_m;
wire vldcnt_e_brtaken0_in;
wire vldcnt_e_brtaken1_in;
wire vldcnt_m_in;
wire vld_f4_in;
wire flush_w;
wire vld_f4f_scanin;
wire vld_f4f_scanout;
wire vld_f5_in;
wire flush_f4;
wire vld_f5f_scanin;
wire vld_f5f_scanout;
wire vld_fb_in;
wire flush_f5;
wire vld_fbf_scanin;
wire vld_fbf_scanout;
wire any_twocycle_p;
wire [23:0] data_d_in;
wire [23:0] data_d;
wire data_df_scanin;
wire data_df_scanout;
wire any_twocycle_d;
wire bkick_d;
wire lsu_d;
wire fbkick_d;
wire specfp_d;
wire condbr_d;
wire callclass_d;
wire annul_d;
wire specbr_d;
wire specld_m;
wire rdf_scanin;
wire rdf_scanout;
wire anytwocyclef_scanin;
wire anytwocyclef_scanout;
wire any_twocycle_e;
wire specldf_scanin;
wire specldf_scanout;
wire postsyncf_scanin;
wire postsyncf_scanout;
wire divf_scanin;
wire divf_scanout;
wire dctif_scanin;
wire dctif_scanout;
wire specbref_scanin;
wire specbref_scanout;
wire specbr_e;
wire specbrmf_scanin;
wire specbrmf_scanout;
wire annulf_scanin;
wire annulf_scanout;
wire annul_e;
wire callclassf_scanin;
wire callclassf_scanout;
wire callclass_e;
wire condbrf_scanin;
wire condbrf_scanout;
wire condbr_e;
wire idestf_scanin;
wire idestf_scanout;
wire idest_m;
wire idest_b;
wire fdestf_scanin;
wire fdestf_scanout;
wire specfpf_scanin;
wire specfpf_scanout;
wire specfp_e;
wire specfp_m;
wire specfp_b;
wire fbkickf_scanin;
wire fbkickf_scanout;
wire fbkick_e;
wire fbkick_m;
wire fbkick_b;
wire fbkick_w;
wire fbkick_f4;
wire fbkick_f5;
wire fgu_d_in;
wire fguf_scanin;
wire fguf_scanout;
wire bkickf_scanin;
wire bkickf_scanout;
wire bkick_e;
wire bkick_b;
wire fpdest_doublef_scanin;
wire fpdest_doublef_scanout;
wire fpdest_singlef_scanin;
wire fpdest_singlef_scanout;
wire fccdestf_scanin;
wire fccdestf_scanout;
wire lsu_d_in;
wire lsuf_scanin;
wire lsuf_scanout;
wire lsu_e;
wire lsu_m;
wire lsu_sync_early;
wire lsu_sync_in;
wire lsu_syncf_scanin;
wire lsu_syncf_scanout;
wire lsu_sync_raw_in;
wire lsu_sync_rawf_scanin;
wire lsu_sync_rawf_scanout;
wire flush_f3;
wire br_mispredict_m_in;
wire br_mispredict_mf_scanin;
wire br_mispredict_mf_scanout;
wire flush_m_in;
wire flush_mf_scanin;
wire flush_mf_scanout;
wire [6:0] i_unused;


input tlu_halted;		// put thread in halt state by gating off ready signals

input dec_block_store_stall;	// there is a block store stall in effect at the d stage for this thread

input dec_ierr_d;		// an inst error has occured at d stage: illegal, parity or ifetch error

input tcu_do_mode;

input lsu_pku_pmen;		// power management enable for pku

input spc_core_running_status;	// thread is active
input lsu_spec_enable;    	// enable speculation; assume this is serializing (if not pipeline it)

input ifu_ibuffer_write_c;	// ifu is writing 1 or more instructions into the ibuffers
input [31:0] ifu_buf0_inst;	// oldest instruction at pick 

input lsu_stb_alloc;	  	// lsu has allocated store in stb; sent in b_stage; increment ccnt by 1
input lsu_stb_dealloc;    	// lsu is deallocating store in stb; decrement sscnt,ccnt by 1
input lsu_block_store_kill;  	// error occured during block store; use this to set scnt=ccnt=0

input [7:0] swl_divide_wait_all;  // divide block for all threads (cycle detected) 

input fgu_divide_completion;	  // divide completion for any thread


//input ibuffer_write;		// any write to the ibuffer (C stage)  - REMOVED because it didn't make timing

input ifu_buf0_valid_p;		// ifu_buf0_valid_p for instruction buffer
input ifu_upper_buffer_valid_p;	// ifu_upper_buffer_valid_p for instruction buffer


input pku_raw_pick_p;  		// unqualified pick for this thread
input tlu_flush_ifu;		// flush this thread (traps)

input tlu_retry_state;		// IF the first part of a retry, must let it go even in dcti w/out DS (part of address optimization)
input dec_valid_d;		// inst is valid at decode for relevant TG
input dec_decode_d;		// decoded inst at decode for relevant TG

input dec_true_valid_e;		// take illegals and other exceptions into account

input lsu_sync;			// lsu needs thread to resync due to dcache_miss, ASI register access, etc.
input lsu_complete;	        // completion of lsu sync event

input dec_br_taken_e;		// br is taken for e stage (br mispredict)

input l2clk;
input scan_in;
input tcu_pce_ov;		// scan signals
input spc_aclk;
input spc_bclk;
input tcu_scan_en;

output swl_ready_p;		// non-speculative ready state
output swl_spec_ready_p;	// speculative ready state, past a br or load


output [1:0] pku_inst_cnt_brtaken0; 	// count of inst at e,m,b pipe stages (to dec)
output [1:0] pku_inst_cnt_brtaken1; 	// count of inst at e,m,b pipe stages (to dec)

output pku_annul_ds_dcti_brtaken0_e;	// the DS of the dcti at e stage is annulled
output pku_annul_ds_dcti_brtaken1_e;	// the DS of the dcti at e stage is annulled

output pku_load_flush_w; 	// lsu flush to fetch (fetch the npc of the load)

output pku_flush_upper_buffer;	// flush signals directly off a flop to IB's
output pku_flush_buffer0;       // kill valid for buffer 0 ALSO force shift of IB's

output pku_valid_e;		// this thread has a valid instruction at the e stage (to dec)

output pku_flush_m;		// tell trap to flush m
output pku_flush_b;		// tell trap to flush b

output pku_flush_lm;		// flush signals unique to the lsu
output pku_flush_lb;

output pku_flush_f1;		// flush signals unique to the fgu
output pku_flush_f2;

output pku_ds_e;		// the instruction at e stage is a DS

output swl_divide_wait; 	// this thread is waiting on divide; send out to all other threads

output swl_cancel_pick_p; 	// cancel pick of this thread due to hazard

output pku_quiesce;		// quiesce signal for tlu

output scan_out;


output pku_lsu_p;		// predecodes for the decode unit (for timing)
output pku_fgu_p;
output pku_pdist_p;
output pku_twocycle_p;
output pku_idest_p;
output pku_fdest_p;
output pku_fsrc_rd_p;
output pku_isrc_rs1_p;
output pku_isrc_rs2_p;
output pku_isrc_rd_p;

// l1clk: no power management; clock always runs

pku_swl_ctl_l1clkhdr_ctl_macro clkgen (
 .l1en (1'b1 ),
 .l1clk(l1clk),
  .l2clk(l2clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

pku_swl_ctl_spare_ctl_macro__num_4 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// scan renames
assign pce_ov = tcu_pce_ov;
assign stop = 1'b0;
assign siclk = spc_aclk;
assign soclk = spc_bclk;
assign se = tcu_scan_en;
// end scan

// all illegals are mapped to this before they are written into the icache
assign illegal_p = ~i[31] & ~i[30] & ~i[24] & ~i[23] & ~i[22];

// --- autogenerated by n2decode view=pku Wed Aug 10 15:04:21 CDT 2005

assign isrc_rs1_u = (i[31]&!i[21]&i[20]&!i[19]) | (i[31]&!i[21]&!i[17]&i[16]) | (
    i[31]&!i[21]&!i[19]&!i[16]&!i[13]) | (i[31]&!i[22]&!i[20]&!i[19]
    &!i[13]&!i[12]&!i[6]&!i[5]) | (i[31]&!i[22]&i[20]&!i[12]&!i[11]&!i[10]) | (
    i[31]&!i[28]&!i[22]&!i[19]&i[13]) | (i[31]&!i[26]&!i[22]&!i[19]&i[13]) | (
    !i[30]&!i[24]&i[23]&i[22]) | (i[31]&i[21]&i[20]&i[19]) | (i[31]&i[22]
    &!i[20]&i[19]) | (i[31]&i[23]&!i[21]&i[20]) | (!i[30]&i[23]&i[22]
    &!i[20]) | (i[31]&!i[23]&!i[22]) | (i[31]&!i[24]) | (i[31]&i[30]) | (
    i[31]&i[19]&!i[9]&i[7]);

assign isrc_rs2_u = (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&!i[22]&!i[21]
    &!i[19]&!i[13]) | (i[31]&i[23]&i[22]&!i[21]&!i[13]) | (i[31]&i[23]
    &i[22]&!i[20]&!i[13]) | (i[31]&!i[22]&i[20]&!i[13]&!i[12]&!i[11]
    &!i[10]) | (i[31]&!i[23]&i[21]&!i[13]) | (i[31]&i[30]&!i[13]) | (
    i[31]&!i[24]&!i[13]) | (i[31]&!i[23]&!i[22]&!i[13]);

assign isrc_rd_u = (i[31]&i[30]&i[22]&i[21]&i[20]) | (i[31]&i[30]&i[22]&i[21]
    &!i[19]) | (i[31]&i[30]&!i[24]&!i[22]&i[21]);

assign idest_u = (i[31]&!i[30]&!i[23]&i[20]&!i[19]) | (i[31]&!i[30]&!i[23]&!i[19]
    &!i[17]) | (i[31]&!i[30]&!i[23]&!i[20]&i[19]) | (i[31]&!i[30]&!i[13]
    &!i[11]&!i[10]&i[9]) | (i[31]&!i[30]&!i[22]&i[21]&i[20]&!i[12]&!i[11]
    &!i[9]) | (i[31]&!i[30]&i[22]&i[21]&i[16]) | (i[30]&i[24]&i[22]&!i[19]) | (
    i[30]&!i[24]&i[22]&i[19]) | (i[31]&!i[30]&!i[23]&!i[19]&!i[16]) | (
    i[30]&!i[24]&!i[21]) | (i[24]&i[23]&i[22]&!i[20]&!i[19]) | (i[31]
    &!i[30]&i[22]&i[21]&i[19]) | (!i[30]&!i[23]&!i[22]) | (i[31]&!i[30]
    &!i[24]) | (!i[31]&i[30]);

assign fsrc_rs1_u = (i[31]&!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[7]&!i[6]) | (
    i[31]&!i[30]&!i[13]&!i[12]&i[9]&!i[8]&i[5]) | (i[31]&!i[30]&i[20]
    &!i[13]&i[10]&!i[9]&i[8]) | (i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[9]
    &i[8]&!i[5]) | (i[31]&!i[30]&!i[19]&!i[13]&i[11]&i[10]&i[7]&!i[6]) | (
    i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[7]&i[6]) | (i[31]&!i[30]&i[20]
    &!i[19]&!i[13]&!i[11]&i[10]&!i[5]) | (i[31]&!i[30]&!i[22]&!i[20]
    &!i[19]&!i[13]&!i[12]&i[11]) | (i[31]&!i[30]&!i[13]&!i[12]&i[11]&i[9]
    &!i[8]);

assign fsrc_rs2_u = (i[31]&!i[30]&!i[13]&i[11]&i[8]&!i[6]) | (i[31]&!i[30]&!i[13]
    &i[11]&!i[8]&i[6]) | (i[31]&!i[30]&!i[13]&i[11]&i[9]&!i[7]) | (i[31]
    &!i[30]&!i[13]&i[11]&!i[9]&i[7]) | (i[31]&!i[30]&!i[22]&!i[13]&i[11]
    &!i[10]) | (i[31]&!i[30]&!i[19]&!i[13]&!i[11]&i[10]) | (i[31]&!i[30]
    &i[24]&i[23]&!i[22]&i[21]&!i[20]);

assign fsrc_rd_u = (i[31]&i[30]&i[24]&!i[22]&i[21]&!i[19]) | (i[31]&i[30]&i[24]
    &i[21]&i[20]&i[19]);

assign fdest_u = (i[31]&!i[30]&!i[13]&i[10]&i[9]) | (i[31]&!i[30]&i[24]&i[23]
    &!i[22]&i[21]&!i[20]&!i[9]) | (i[31]&!i[30]&!i[22]&!i[19]&!i[13]
    &i[11]) | (i[31]&i[30]&i[24]&!i[21]&i[20]) | (i[31]&i[30]&i[24]&!i[21]
    &!i[19]);

assign fgu_u = (i[31]&!i[30]&!i[13]&i[12]&i[5]) | (i[31]&!i[30]&!i[13]&i[9]&i[8]) | (
    i[31]&i[24]&!i[23]&i[22]&i[21]&i[20]&!i[19]) | (i[31]&!i[30]&!i[22]
    &!i[13]&i[11]) | (i[31]&!i[30]&!i[22]&!i[13]&i[10]) | (i[31]&!i[30]
    &i[22]&i[21]&!i[20]&i[19]) | (i[31]&!i[30]&i[24]&i[23]&i[21]&!i[20]) | (
    i[31]&i[30]&i[24]&!i[22]&i[21]) | (i[31]&!i[30]&!i[24]&i[22]&i[19]) | (
    i[31]&!i[30]&!i[24]&i[22]&i[20]) | (i[31]&i[24]&!i[22]&i[21]&!i[20]
    &!i[19]);

assign dcti_u = (i[24]&i[23]&i[22]&!i[21]&!i[20]) | (!i[31]&i[23]) | (!i[31]
    &i[22]) | (!i[31]&i[30]);

assign specbr_u = (!i[31]&!i[30]&i[22]) | (!i[31]&!i[30]&i[23]);

assign specld_u = (i[31]&i[30]&!i[21]);

assign specfp_u = (i[31]&!i[30]&!i[13]&i[12]&i[5]) | (i[31]&!i[30]&!i[13]&i[10]
    &i[9]) | (i[31]&!i[30]&!i[22]&!i[13]&i[11]) | (i[31]&!i[30]&i[24]
    &i[23]&!i[22]&i[21]&!i[20]);

assign lsu_u = (i[31]&i[24]&!i[23]&i[22]&i[20]&!i[19]&i[16]) | (i[31]&i[24]
    &!i[23]&i[22]&!i[21]&!i[17]&i[16]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]
    &!i[20]&i[19]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[19]&!i[16]) | (
    i[31]&i[24]&i[23]&!i[22]&!i[21]&i[20]) | (i[31]&!i[28]&i[24]&i[23]
    &!i[22]&!i[21]&!i[19]) | (i[31]&i[24]&i[23]&i[20]&i[19]) | (i[31]
    &i[29]&i[24]&i[23]&!i[22]&!i[21]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]
    &i[1]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[5]) | (i[31]&i[24]&!i[23]
    &i[22]&!i[21]&i[6]) | (i[31]&i[30]);

assign postsync_u = (i[31]&i[24]&i[22]&!i[21]&!i[20]&i[6]) | (i[31]&i[24]&i[22]
    &!i[21]&!i[20]&i[5]) | (i[31]&i[24]&i[22]&!i[21]&!i[20]&i[1]) | (
    i[31]&i[24]&i[22]&!i[21]&!i[20]&!i[17]) | (i[31]&i[24]&i[22]&!i[21]
    &!i[20]&!i[15]) | (i[31]&i[24]&i[20]&!i[19]&!i[13]&!i[11]&i[10]&!i[9]) | (
    i[31]&!i[30]&!i[28]&i[24]&i[23]&!i[21]&!i[20]) | (i[24]&i[23]&i[22]
    &i[21]) | (i[31]&!i[30]&!i[26]&i[24]&i[23]&!i[21]&!i[20]) | (i[31]
    &!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]) | (i[31]&!i[30]
    &i[24]&i[23]&!i[22]&!i[21]&i[20]) | (i[31]&i[24]&!i[23]&i[22]&i[20]
    &!i[19]) | (i[24]&i[23]&i[22]&!i[20]) | (i[31]&!i[30]&i[22]&!i[21]
    &i[19]) | (i[30]&i[24]&!i[20]&i[19]) | (i[30]&i[22]&i[21]&i[19]) | (
    i[31]&!i[30]&!i[24]&i[22]&!i[21]&i[20]) | (!i[31]&i[30]);

assign div_u = (i[31]&!i[30]&!i[20]&!i[19]&!i[13]&!i[11]&i[10]) | (i[31]&!i[30]
    &!i[20]&!i[13]&i[8]&i[7]) | (i[31]&!i[30]&!i[23]&i[22]&i[21]&!i[20]
    &i[19]) | (i[31]&!i[30]&!i[24]&i[22]&i[21]&i[20]);

assign pdist_u = (i[31]&!i[30]&!i[13]&!i[11]&i[9]&i[8]&i[7]&!i[5]);

assign condbr_u = (!i[31]&!i[30]&i[27]&i[22]) | (!i[31]&!i[30]&i[25]&i[22]) | (
    !i[31]&!i[30]&i[26]&i[22]) | (!i[31]&!i[30]&i[27]&i[23]) | (!i[31]
    &!i[30]&i[25]&i[23]) | (!i[31]&!i[30]&i[26]&i[23]);

assign callclass_u = (i[24]&i[23]&i[22]&!i[21]&!i[20]) | (!i[31]&i[30]);

assign fccsrc_u = (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[19]&!i[13]&!i[9]&!i[7]) | (
    !i[30]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]&!i[18]) | (!i[31]&!i[30]
    &i[24]&i[23]) | (!i[31]&!i[30]&i[24]&i[22]);

assign fsrsync_u = (i[31]&!i[30]&!i[13]&!i[11]&i[9]&i[8]&i[7]&!i[5]) | (i[31]
    &i[30]&i[24]&!i[22]&!i[20]&i[19]);

assign twocycle_u = (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&i[30]&!i[24]&!i[22]
    &i[21]&i[20]&i[19]);

assign bkick_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[20]&i[19]) | (i[31]&i[24]
    &i[23]&!i[21]&!i[20]&i[19]) | (i[31]&i[30]&i[24]&!i[22]&!i[20]&i[19]);

assign fbkick_u = (i[31]&!i[30]&i[20]&!i[19]&!i[13]&!i[11]&i[10]&!i[9]) | (
    i[31]&i[24]&!i[23]&i[22]&i[21]&i[20]&!i[19]) | (i[31]&!i[30]&i[24]
    &!i[23]&!i[22]&i[21]&!i[20]&!i[19]) | (!i[30]&i[24]&i[23]&i[22]&i[21]
    &!i[20]) | (i[31]&!i[30]&!i[24]&i[22]&!i[21]&i[19]) | (i[31]&!i[30]
    &!i[24]&i[22]&!i[21]&i[20]);

assign fccdest_u = (i[31]&!i[30]&i[19]&!i[13]&i[9]);

assign fpdest_single_u = (i[31]&!i[30]&!i[19]&!i[13]&i[12]&i[7]) | (i[31]&!i[30]
    &!i[13]&i[9]&i[8]&i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[9]&i[8]&i[7]
    &i[5]) | (i[31]&!i[30]&!i[20]&!i[13]&!i[11]&i[10]&i[5]) | (i[31]
    &!i[30]&!i[22]&!i[19]&!i[13]&i[12]&i[11]&!i[8]) | (i[31]&!i[30]&!i[19]
    &!i[13]&i[11]&!i[8]&i[5]) | (i[31]&i[24]&i[23]&!i[22]&!i[20]&i[19]
    &!i[9]&i[5]) | (i[31]&!i[30]&!i[20]&!i[19]&!i[13]&!i[12]&!i[10]&i[5]) | (
    i[31]&!i[30]&i[20]&!i[13]&i[11]&i[10]&i[5]) | (i[31]&i[30]&i[24]
    &!i[22]&!i[19]);

assign fpdest_double_u = (i[31]&!i[30]&!i[22]&!i[20]&!i[19]&!i[13]&i[12]&!i[9]
    &!i[7]) | (i[31]&!i[30]&i[19]&!i[13]&i[9]) | (i[31]&!i[30]&!i[20]
    &!i[19]&!i[13]&i[11]&i[10]) | (i[31]&i[24]&!i[22]&i[19]&!i[13]&i[6]) | (
    i[31]&!i[30]&!i[13]&i[10]&i[9]&!i[5]) | (i[31]&!i[30]&!i[13]&!i[11]
    &i[10]&i[9]&!i[7]&!i[6]) | (i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[10]
    &i[8]) | (i[31]&!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[8]) | (i[31]&!i[30]
    &i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[11]&i[6]) | (i[31]&i[30]&i[24]
    &i[20]&i[19]) | (i[31]&!i[30]&!i[22]&!i[13]&!i[12]&i[11]&!i[5]);

assign fpsrc_single_u = (i[31]&!i[30]&!i[22]&!i[13]&i[12]&i[11]&!i[6]) | (i[31]
    &!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[6]&!i[5]) | (i[31]&!i[30]&!i[13]
    &i[10]&i[8]&!i[7]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[8]&i[6]
    &i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[7]&i[6]&i[5]) | (i[31]&!i[30]
    &!i[13]&i[10]&!i[8]&i[7]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[11]
    &i[7]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[9]&i[8]&i[5]) | (
    i[31]&!i[30]&!i[13]&i[9]&!i[8]&!i[7]&i[5]) | (i[31]&i[24]&i[23]&!i[22]
    &i[21]&!i[20]&i[5]) | (i[31]&i[30]&i[24]&!i[22]&!i[19]);

assign fpsrc_double_u = (i[31]&!i[30]&!i[13]&!i[11]&i[8]&i[7]) | (i[31]&!i[30]
    &!i[13]&!i[11]&i[10]&i[8]&i[6]) | (i[31]&!i[30]&!i[13]&i[10]&!i[9]
    &i[8]&!i[5]) | (i[31]&!i[30]&!i[22]&!i[13]&!i[11]&i[10]&!i[8]&!i[7]
    &!i[6]) | (i[31]&!i[30]&!i[13]&i[10]&i[7]&!i[6]&!i[5]) | (i[31]&!i[30]
    &i[20]&!i[13]&i[11]&i[8]&!i[6]&!i[5]) | (i[31]&!i[30]&!i[13]&!i[11]
    &i[10]&i[7]&i[6]) | (i[31]&!i[30]&!i[13]&i[10]&!i[7]&i[6]&!i[5]) | (
    i[31]&!i[30]&!i[13]&i[11]&i[9]&!i[8]&!i[5]) | (i[31]&!i[30]&!i[13]
    &i[11]&!i[9]&i[6]&!i[5]) | (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21]
    &!i[20]&!i[11]&!i[5]) | (i[31]&i[30]&i[24]&i[20]&i[19]);

assign store_u = (i[31]&!i[30]&!i[26]&i[24]&i[23]&!i[22]&!i[21]&!i[19]) | (
    i[31]&i[30]&i[21]&!i[19]) | (i[31]&!i[30]&!i[28]&i[24]&i[23]&!i[22]
    &!i[21]&!i[19]) | (i[31]&!i[30]&i[24]&i[23]&!i[22]&!i[21]&i[20]) | (
    i[31]&i[30]&!i[22]&i[21]) | (i[31]&i[30]&!i[24]&i[21]);

assign windowsync_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[20]&i[19]) | (!i[30]
    &i[24]&i[23]&i[22]&i[21]&!i[20]) | (!i[30]&i[24]&i[23]&i[22]&!i[20]
    &i[19]);

// end autogeneration


assign pku_isrc_rs1_p  = isrc_rs1_u      & ~illegal_p;	
assign pku_isrc_rs2_p  = isrc_rs2_u      & ~illegal_p;	
assign pku_isrc_rd_p   = isrc_rd_u       & ~illegal_p;	
assign pku_idest_p     = idest_u         & ~illegal_p;	
assign fsrc_rs1_p      = fsrc_rs1_u      & ~illegal_p;	
assign fsrc_rs2_p      = fsrc_rs2_u      & ~illegal_p;	
assign pku_fsrc_rd_p   = fsrc_rd_u       & ~illegal_p;	
assign pku_fdest_p     = fdest_u         & ~illegal_p;	
assign pku_fgu_p       = fgu_u           & ~illegal_p;	
assign dcti_p          = dcti_u          & ~illegal_p;	
assign specbr_p        = specbr_u        & ~illegal_p;	
assign specld_p        = specld_u        & ~illegal_p;	
assign specfp_p        = specfp_u        & ~illegal_p;	
assign pku_lsu_p       = lsu_u           & ~illegal_p;	
assign postsync_p      = postsync_u      & ~do_mode_f & ~illegal_p;	
assign div_p           = div_u           & ~illegal_p;	
assign pku_pdist_p     = pdist_u         & ~illegal_p;	
assign condbr_p        = condbr_u        & ~illegal_p;	
assign callclass_p     = callclass_u     & ~illegal_p;	
assign fccsrc_p        = fccsrc_u        & ~illegal_p;	
assign fsrsync_p       = fsrsync_u       & ~illegal_p;	
assign pku_twocycle_p  = twocycle_u      & ~illegal_p;	
assign bkick_p         = bkick_u         & ~illegal_p;	
assign fbkick_p        = fbkick_u        & ~illegal_p;	
assign fccdest_p       = fccdest_u       & ~illegal_p;	
assign fpdest_single_p = fpdest_single_u & ~fsrc_rd_u & ~illegal_p;	// store-floats don't have a fpdest
assign fpdest_double_p = fpdest_double_u & ~fsrc_rd_u & ~illegal_p;	
assign fpsrc_single_p  = fpsrc_single_u  & ~illegal_p;	
assign fpsrc_double_p  = fpsrc_double_u  & ~illegal_p;	
assign store_p         = store_u         & ~illegal_p;	
assign windowsync_p    = windowsync_u    & ~illegal_p;	

pku_swl_ctl_msff_ctl_macro__width_1 do_modef  (
 .scan_in(do_modef_scanin),
 .scan_out(do_modef_scanout),
 .l1clk(l1clk_pm1),
 .din  (tcu_do_mode),
 .dout (do_mode_f),
  .siclk(siclk),
  .soclk(soclk)
);


assign i[31:0] = ifu_buf0_inst[31:0];

assign rs1[4:0] = i[18:14];
assign rs2[4:0] = i[4:0];
assign rd[4:0] = i[29:25];

assign annul = i[29];

// instruction buffers will be flushing this cycle; qualify input valids for this flush cycle
assign vld_p = ifu_buf0_valid_p & ~pku_flush_buffer0;
assign vld_1 = ifu_upper_buffer_valid_p & ~pku_flush_upper_buffer;

// quiesce signal

assign valid = (ifu_buf0_valid_p | vld_d | vld_e | vld_m | vld_b | vld_w | 
		vld_f4 | vld_f5 | vld_fb |
		swl_divide_wait | lsu_sync_wait);

assign pku_quiesce = ~valid;

// l1clk_pm2: fine grain power management; shut down clocks whenver pick is idle

assign pick_clken = (((ifu_buf0_valid_p & (swl_ready_p | swl_spec_ready_p)) |  // valid inst and ready to pick
	             vldraw_d | vldraw_e | vldraw_m |		               // must get inst cnts right
		     vld_d | vld_e | vld_m | vld_b | vld_w | 
		     vld_f4 | vld_f5 | vld_fb |   		               // clock fgu ops down the pipe 
		     ext_flush) & thread_active) | ~lsu_pku_pmen;

pku_swl_ctl_l1clkhdr_ctl_macro clkgenpm (
 .l1en (pick_clken ),
 .l1clk(l1clk_pm2),
  .l2clk(l2clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

// l1clk_pm1: coarse grain power management; shut down clocks if thread is not active

assign active_clken = thread_active | ~lsu_pku_pmen;

pku_swl_ctl_l1clkhdr_ctl_macro clkgenactive (
 .l1en (active_clken ),
 .l1clk(l1clk_pm1),
  .l2clk(l2clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


pku_swl_ctl_msff_ctl_macro__width_1 external_flushf  (
 .scan_in(external_flushf_scanin),
 .scan_out(external_flushf_scanout),
 .l1clk(l1clk_pm1),
 .din  (tlu_flush_ifu),
 .dout (ext_flush),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_ext_flush_in = tlu_flush_ifu | lsu_sync;

pku_swl_ctl_msff_ctl_macro__width_1 lsu_ext_flushf  (
 .scan_in(lsu_ext_flushf_scanin),
 .scan_out(lsu_ext_flushf_scanout),
 .l1clk(l1clk_pm1),
 .din  (lsu_ext_flush_in),
 .dout (lsu_ext_flush_w),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in bits_on -var swl_divide_wait_all[7:0] -max 2
assign divide_wait_outstanding = |swl_divide_wait_all[7:0];


// dependency logic to prevent fpdest_single followed by fpsrc_double
// no way to bypass partial result

assign fpdouble_wait =  (fpsrc_double_p & vld_d & fpdest_single_d) |
			(fpsrc_double_p & vld_e & fpdest_single_e) |
			(fpsrc_double_p & vld_m & fpdest_single_m) |
			(fpsrc_double_p & vld_b & ~lsu_b & fpdest_single_b) |     // no lsu hazards past b
			(fpsrc_double_p & vld_w & ~lsu_w & fpdest_single_w) |
			(fpsrc_double_p & vld_f4 & ~lsu_f4 & fpdest_single_f4);

assign fpdouble_cancel =  fpdouble_wait |
			(fpsrc_double_p & vld_b & lsu_b & fpdest_single_b) |     // if fpdest is load at b, cancel
			(fpsrc_double_p & vld_f5 & ~lsu_f5 & fpdest_single_f5);
	
// dependency logic to prevent fpdest_double followed by fpsrc_single
// don't want to deal with unscrambling the FP sources and destinations

assign fpsingle_wait =  (fpsrc_single_p & vld_d & fpdest_double_d) |
			(fpsrc_single_p & vld_e & fpdest_double_e) |
			(fpsrc_single_p & vld_m & fpdest_double_m) |
			(fpsrc_single_p & vld_b & ~lsu_b & fpdest_double_b) |     // no lsu hazards past b
			(fpsrc_single_p & vld_w & ~lsu_w & fpdest_double_w) |
			(fpsrc_single_p & vld_f4 & ~lsu_f4 & fpdest_double_f4);

assign fpsingle_cancel =  fpsingle_wait |
			(fpsrc_single_p & vld_b & lsu_b & fpdest_double_b) |     // if fpdest is load at b, cancel
			(fpsrc_single_p & vld_f5 & ~lsu_f5 & fpdest_double_f5);

// dependency logic for fcc : fbfcc, movcc, fmovcc
// FGU sends fcc's during F3/W stage; decode has 2 flop stages before E stage
assign fccdep_wait =   (fccsrc_p & vld_d & fccdest_d) |
		       (fccsrc_p & vld_e & fccdest_e) |
		       (fccsrc_p & vld_m & fccdest_m);

assign fccdep_cancel = fccdep_wait |
		       (fccsrc_p & vld_b & fccdest_b);

// presync logic for ldfsr, stfsr (wait for all fgu op to advance past f5)
// ldfsr has same presync timing as stfsr
assign fsrsync_wait = (fsrsync_p & vld_d & fgu_d) |  // wait on all fgus (including loads, fgu ints)
		     (fsrsync_p & vld_e & fgu_e) |
		     (fsrsync_p & vld_m & fgu_m) |
		     (fsrsync_p & vld_b & fgu_b) |
		     (fsrsync_p & vld_w & fgu_w) |
		     (fsrsync_p & vld_f4);

assign fsrsync_cancel = fsrsync_wait |
		     (fsrsync_p & vld_f5);

// fgu_op with dest { fgu fdest }
// load-int { lsu specld }
// load-float or fgu_op { fdest }

// integer sources (rs1,rs2,rd) check against integer loads
// float sources (rs1,rs2,rd) check against float-loads and fgu_ops
// float loads have WAW hazard with prior fgu ops

// dependency checking for integer and floats
assign check_rs1_d =  (idest_d & specld_d & pku_isrc_rs1_p) |   // check int rs1 VS int_load_d
		      (fdest_d & fsrc_rs1_p);		        // check fp rs1 VS fgu_op_d OR fgu_load_d
assign check_rs2_d = (idest_d & specld_d & pku_isrc_rs2_p) |	// rs2 same as rs1
		     (fdest_d & fsrc_rs2_p);
assign check_rd_d = (idest_d & specld_d & pku_isrc_rd_p) |	 // check int store VS prior int load 
		    (fdest_d & pku_fsrc_rd_p) |			 // check fp store VS prior fgu_op OR fgu_load
		    (fdest_d & fgu_d & pku_fdest_p & pku_lsu_p); // check float-load VS prior fgu_op WAW

assign check_rs1_e = (idest_e & specld_e & pku_isrc_rs1_p) | 	// check int rs1 VS int_load_e
		     (fdest_e & fgu_e & fsrc_rs1_p );	        // check fp rs1 VS fgu_op_e
assign check_rs2_e = (idest_e & specld_e & pku_isrc_rs2_p) |
		     (fdest_e & fgu_e & fsrc_rs2_p );
assign check_rd_e = (idest_e & specld_e & pku_isrc_rd_p) |
		    (fdest_e & fgu_e & pku_fsrc_rd_p) |		// check fp store VS prior fgu_op
		    (fdest_e & fgu_e & pku_fdest_p & pku_lsu_p);  // WAW

assign check_rs1_m = (fdest_m & fgu_m & fsrc_rs1_p);	  // check fp rs1 VS fgu_op_m
assign check_rs2_m = (fdest_m & fgu_m & fsrc_rs2_p);
assign check_rd_m =  (fdest_m & fgu_m & pku_fsrc_rd_p) |
		     (fdest_m & fgu_m & pku_fdest_p & pku_lsu_p);  // WAW, load-float write delay one cycle so release after m stage

assign check_rs1_b = (fdest_b & fgu_b & fsrc_rs1_p);	  // check fp rs1 VS fgu_op_b
assign check_rs2_b = (fdest_b & fgu_b & fsrc_rs2_p);
assign check_rd_b =  (fdest_b & fgu_b & pku_fsrc_rd_p);          
 
assign check_rs1_w = (fdest_w & fgu_w & fsrc_rs1_p);	  // check fp rs1 VS fgu_op_w
assign check_rs2_w = (fdest_w & fgu_w & fsrc_rs2_p);
assign check_rd_w =  (fdest_w & fgu_w & pku_fsrc_rd_p);

assign cmp_rs1_rd_d = (rs1[4:0] == rd_d[4:0]);
assign cmp_rs2_rd_d = (rs2[4:0] == rd_d[4:0]);
assign cmp_rd_rd_d =  ( rd[4:0] == rd_d[4:0]);
assign cmp_rs1_rd_e = (rs1[4:0] == rd_e[4:0]);
assign cmp_rs2_rd_e = (rs2[4:0] == rd_e[4:0]);
assign cmp_rd_rd_e =  ( rd[4:0] == rd_e[4:0]);
assign cmp_rs1_rd_m = (rs1[4:0] == rd_m[4:0]);
assign cmp_rs2_rd_m = (rs2[4:0] == rd_m[4:0]);
assign cmp_rd_rd_m =  ( rd[4:0] == rd_m[4:0]);
assign cmp_rs1_rd_b = (rs1[4:0] == rd_b[4:0]);
assign cmp_rs2_rd_b = (rs2[4:0] == rd_b[4:0]);
assign cmp_rd_rd_b =  ( rd[4:0] == rd_b[4:0]);
assign cmp_rs1_rd_w = (rs1[4:0] == rd_w[4:0]);
assign cmp_rs2_rd_w = (rs2[4:0] == rd_w[4:0]);
assign cmp_rd_rd_w =  ( rd[4:0] == rd_w[4:0]);

// dependency checking is independent of enable/disable of speculation
assign dependent_cancel = ((cmp_rs1_rd_d & vld_d & check_rs1_d) |
		       (cmp_rs2_rd_d & vld_d & check_rs2_d) |
		       (cmp_rd_rd_d  & vld_d & check_rd_d) |
		       (cmp_rs1_rd_e & vld_e & check_rs1_e) |
		       (cmp_rs2_rd_e & vld_e & check_rs2_e) |
		       (cmp_rd_rd_e  & vld_e & check_rd_e) |
		       (cmp_rs1_rd_m & vld_m & check_rs1_m) |
		       (cmp_rs2_rd_m & vld_m & check_rs2_m) |
		       (cmp_rd_rd_m  & vld_m & check_rd_m) |
		       (cmp_rs1_rd_b & vld_b & check_rs1_b) |
		       (cmp_rs2_rd_b & vld_b & check_rs2_b) |
		       (cmp_rd_rd_b  & vld_b & check_rd_b) |
		       (cmp_rs1_rd_w & vld_w & check_rs1_w) |
		       (cmp_rs2_rd_w & vld_w & check_rs2_w) |
		       (cmp_rd_rd_w  & vld_w & check_rd_w));

// wait exits 1 pipe stage earlier than the dependency logic
// * is the differences
// 
// assign check_rs1_d =  (idest_d & specld_d & pku_isrc_rs1_p) |   
// 			 (fdest_d & *fgu_d & fsrc_rs1_p);	
// assign check_rs2_d = (idest_d & specld_d & pku_isrc_rs2_p) |	
// 			(fdest_d & *fgu_d & fsrc_rs2_p);	
// assign check_rd_d = (idest_d & specld_d & pku_isrc_rd_p) |	
//		       (fdest_d & *fgu_d & pku_fsrc_rd_p) |	
// 		       (fdest_d & fgu_d & pku_fdest_p & pku_lsu_p);
// 								   
// assign check_rs1_e = *						
// 			(fdest_e & fgu_e & fsrc_rs1_p );	
// assign check_rs2_e = *						
// 			(fdest_e & fgu_e & fsrc_rs2_p );	
// assign check_rd_e =  *						
// 		       (fdest_e & fgu_e & pku_fsrc_rd_p) |	
// 		       (fdest_e & fgu_e & pku_fdest_p & pku_lsu_p);
// 								   
// assign check_rs1_m = (fdest_m & fgu_m & fsrc_rs1_p);	
// assign check_rs2_m = (fdest_m & fgu_m & fsrc_rs2_p);	
// assign check_rd_m =  (fdest_m & fgu_m & pku_fsrc_rd_p) |
//			*
// 								   
// assign check_rs1_b = (fdest_b & fgu_b & fsrc_rs1_p);	
// assign check_rs2_b = (fdest_b & fgu_b & fsrc_rs2_p);
// assign check_rd_b = (fdest_b & fgu_b & pku_fsrc_rd_p);
//			
// 
// assign check_rs1_w = *
// assign check_rs2_w = *
// assign check_rd_w = *

// fgu loads don't goto wait
// integer loads don't look at E stage to stay in wait
// fgus dont look at W stage to stay in wait 
// fgu WAW dont look at B stage

assign wait_rs1_d = (idest_d & specld_d & pku_isrc_rs1_p) |
		    (fdest_d & fgu_d & fsrc_rs1_p);
assign wait_rs2_d = (idest_d & specld_d & pku_isrc_rs2_p) |
		    (fdest_d & fgu_d & fsrc_rs2_p);
assign wait_rd_d =  (idest_d & specld_d & pku_isrc_rd_p) |	
		    (fdest_d & fgu_d & pku_fsrc_rd_p) |	
 		    (fdest_d & fgu_d & pku_fdest_p & pku_lsu_p);

assign wait_rs1_e = (fdest_e & fgu_e & fsrc_rs1_p);
assign wait_rs2_e = (fdest_e & fgu_e & fsrc_rs2_p);
assign wait_rd_e =  (fdest_e & fgu_e & pku_fsrc_rd_p) |	
		    (fdest_e & fgu_e & pku_fdest_p & pku_lsu_p);

assign wait_rd_m =  (fdest_m & fgu_m & pku_fsrc_rd_p);

assign wait_rd_b = (fdest_b & fgu_b & pku_fsrc_rd_p);

assign dependent_wait = 
                       (cmp_rs1_rd_d & vld_d & wait_rs1_d) |
		       (cmp_rs2_rd_d & vld_d & wait_rs2_d) |
		       (cmp_rd_rd_d  & vld_d & wait_rd_d) |
		       (cmp_rs1_rd_e & vld_e & wait_rs1_e) |
		       (cmp_rs2_rd_e & vld_e & wait_rs2_e) |
		       (cmp_rd_rd_e  & vld_e & wait_rd_e) |
		       (cmp_rs1_rd_m & vld_m & check_rs1_m) |
		       (cmp_rs2_rd_m & vld_m & check_rs2_m) |
		       (cmp_rd_rd_m  & vld_m & wait_rd_m) |
		       (cmp_rs1_rd_b & vld_b & check_rs1_b) |
		       (cmp_rs2_rd_b & vld_b & check_rs2_b) |
		       (cmp_rd_rd_b  & vld_b & wait_rd_b);


pku_swl_ctl_msff_ctl_macro__width_1 tlu_retryf  (
 .scan_in(tlu_retryf_scanin),
 .scan_out(tlu_retryf_scanout),
 .l1clk(l1clk_pm1),
 .din  (tlu_retry_state),
 .dout (retry_state),
  .siclk(siclk),
  .soclk(soclk)
);


// block_store_stall

pku_swl_ctl_msff_ctl_macro__width_2 block_store_stallf  (
 .scan_in(block_store_stallf_scanin),
 .scan_out(block_store_stallf_scanout),
 .l1clk(l1clk_pm1),
 .din  ({dec_block_store_stall,block_store_stall[1]}),
 .dout (block_store_stall[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);
   
// on leading edge of block_store_stall set scnt to full state (4'b1000)

assign full_scnt = ~block_store_stall[0] & block_store_stall[1];

// vld_p is not needed since pick cannot occur unless vld_p	
// illegals are treated as normal instructions wrt cancel_pick

assign swl_cancel_pick_p =   (lsu_sync_raw_w) |			  // cycle lsu sync don't pick since lsu_sync_wait is not in effect yet 
			     (dcti_p & ~vld_1 & ~retry_state) |   // IF retry_state, let the DCTI go
			     (dcti_p & vld_d & dcti_d) |          // for a DCTI pair, make sure we know the real DS
			     (dcti_p & ~vld_d & vld_e & dcti_e) |
			     (pku_twocycle_p & vld_d & specld_d & idest_d) |  // can't let twocycle go if int load at decode stage
									      // we do NO dependency checking on second half of twocycle (e.g. STD)
			     (dependent_cancel) |		  // dependency checking

			    // window ops needs at least 2 holes in front of them
			    // if an ecc error can be generated in the hole, it doesn't count as a hole (no flush_b for window_ops)
			     (windowsync_p & (vld_d | vld_e | (vld_m & any_twocycle_m) | divide_wait1 | block_store_stall[0])) |  

			     (fpsingle_cancel) |
			     (fpdouble_cancel) |
			     (fccdep_cancel) |
			     (fsrsync_cancel) |
			     (stb_cancel) |
			     (div_p & divide_wait_outstanding) |
			     (ldst_sync_single & fpsrc_double_p) |  // can't let double go if single missed
			     (ldst_sync_ldfsr) |		    // wait one cycle on ldfsr that misses the cache
			     (restore_scnt & store_p);   // cancel pick in this case; assume pick is too late to put into logic updating scnt

// this is "early" version of the pick signal (pku_flush_buffer0 is cycle AFTER branch mispredict)
assign pick_raw_p = pku_raw_pick_p & ~swl_cancel_pick_p & ~(~dec_decode_d & dec_valid_d);

assign pick_p = pick_raw_p & ~pku_flush_buffer0;

// this is the final version of the pick signal taking DS into account (flush_p is SAME cycle as branch mispredict)
assign actual_pick_p = pick_p & ~flush_p;  
     
// this is for the address logic (dont include annuling)
assign actual_raw_pick_p = vld_p & pick_raw_p & ~rawflush_p;

   
// postsync wait conditions
assign set_postsync = actual_pick_p & postsync_p;  

assign clear_postsync = (postsync_d & flush_d) |       // if postsync is flushed then clear
			(postsync_e & flush_e) |
		        (vld_w & bkick_w) |                                   // ldfsr,stfsr,save,restore,saved,restored,return
	                (vld_fb & fbkick_fb) |                                // all integer ops in fgu exit here
		        (br_mispredict_m & callclass_m & ~bkick_m) |          // clear out JMPS,CALLS (but not RETURNS)
		        lsu_sync_raw_w | ext_flush;                           // done, retries will exit via ext_flush

assign postsync_in = (post_sync & ~clear_postsync) | set_postsync;  // priority set 
		 
pku_swl_ctl_msff_ctl_macro__width_1 post_syncf  (
 .scan_in(post_syncf_scanin),
 .scan_out(post_syncf_scanout),
 .l1clk(l1clk_pm2),
 .din  (postsync_in),
 .dout (post_sync),
  .siclk(siclk),
  .soclk(soclk)
);
   
// lsu_spec_enable is static

pku_swl_ctl_msff_ctl_macro__width_1 spec_enf  (
 .scan_in(spec_enf_scanin),
 .scan_out(spec_enf_scanout),
 .l1clk(l1clk_pm1),
 .din  (lsu_spec_enable),
 .dout (spec_en),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 active_threadf  (
 .scan_in(active_threadf_scanin),
 .scan_out(active_threadf_scanout),
 .l1clk(l1clk),
 .din  (spc_core_running_status),
 .dout (thread_active),
  .siclk(siclk),
  .soclk(soclk)
);

// fgu asked that in non-spec mode we wait 1 more cycle before sending next op down pipe

assign set_postsync_ns = actual_pick_p & ((specbr_p | specld_p | specfp_p) & ~spec_en); 

assign clear_postsync_ns = (vld_m & specbr_m) | 
		           (vld_b & specld_b) |
		            fpvld_w2 | 
			    ext_flush | br_mispredict_m | lsu_sync_w;

assign postsync_ns_in = (postsync_ns | set_postsync_ns) & ~clear_postsync_ns; 

pku_swl_ctl_msff_ctl_macro__width_1 postsync_nsf  (
 .scan_in(postsync_nsf_scanin),
 .scan_out(postsync_nsf_scanout),
 .l1clk(l1clk_pm2),
 .din  (postsync_ns_in),
 .dout (postsync_ns),
  .siclk(siclk),
  .soclk(soclk)
);


// any instruction that has dependency on prior instruction is not allowed into machine
// includes int and FP ops
// dep_wait is independent of spec_en
// fccdep_wait checks fcc dependencies
// fsrsync checks for fsr hazards
// fpdouble wait doesn't allow fpsrc_double to go if prior fpdest_single
assign set_dep_wait = vld_p & (dependent_wait | fccdep_wait | fsrsync_wait | fpdouble_wait | fpsingle_wait);

assign clear_dep_wait = flush_p;

assign dep_wait_in = set_dep_wait & ~clear_dep_wait;

// dcti wait conditions (has delay slot)

assign set_dcti_wait = dcti_p & vld_p & ~vld_1 & ~retry_state;

assign clear_dcti_wait = ifu_ibuffer_write_c | flush_p;

assign dcti_wait_in = set_dcti_wait & ~clear_dcti_wait;

// dcti couple conditions (two dctis with delay slots)
// for this case, will be in wait state for dcti_e

assign set_dcti_couple_wait = dcti_d & vld_d & dcti_p & vld_p;

assign clear_dcti_couple_wait = flush_p;

assign dcti_couple_wait_in = set_dcti_couple_wait & ~clear_dcti_couple_wait;

// divide wait (as soon as you pick a divide goto wait)
// keep track of whether the divide is flushed or not

assign flush_div = (((flush_d & div_d) | (flush_e & div_e)) & swl_divide_wait) | lsu_sync_w | ext_flush;

assign set_divide_wait_in = actual_pick_p & div_p;  

assign clear_divide_wait_in = fgu_divide_completion | flush_div;

assign divide_wait_in = (set_divide_wait_in | swl_divide_wait) & ~clear_divide_wait_in;

pku_swl_ctl_msff_ctl_macro__width_1 divide_waitf  (
 .scan_in(divide_waitf_scanin),
 .scan_out(divide_waitf_scanout),
 .l1clk(l1clk_pm1),
 .din  (divide_wait_in),
 .dout (swl_divide_wait),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 divide_wait1f  (
 .scan_in(divide_wait1f_scanin),
 .scan_out(divide_wait1f_scanout),
 .l1clk(l1clk_pm1),
 .din  (swl_divide_wait),
 .dout (divide_wait1),
  .siclk(siclk),
  .soclk(soclk)
);

// wait for other divide to finish before you try to pick this divide
assign otherdivide_wait_in = div_p & vld_p & divide_wait_outstanding & ~flush_p;

pku_swl_ctl_msff_ctl_macro__width_2 lsu_completef  (
 .scan_in(lsu_completef_scanin),
 .scan_out(lsu_completef_scanout),
 .l1clk(l1clk_pm1),
 .din  ({lsu_complete,lsu_complete_d1}),
 .dout ({lsu_complete_d1,lsu_complete_d2}),
  .siclk(siclk),
  .soclk(soclk)
);

// lsu_sync has happened; wait for lsu_complete or thread is flushed (can't commit out-of-order)
assign set_lsu_sync_wait = lsu_sync_raw_w;

assign clear_lsu_sync_wait = ext_flush | lsu_complete;

assign lsu_sync_wait_in = (set_lsu_sync_wait | lsu_sync_wait) & ~clear_lsu_sync_wait;

pku_swl_ctl_msff_ctl_macro__width_1 lsu_sync_waitf  (
 .scan_in(lsu_sync_waitf_scanin),
 .scan_out(lsu_sync_waitf_scanout),
 .l1clk(l1clk_pm1),
 .din  (lsu_sync_wait_in),
 .dout (lsu_sync_wait),
  .siclk(siclk),
  .soclk(soclk)
);

// FGU handles case where double is followed by single
// pick handles single followed by double
// wait a cycle to clear to make sure hazard free with subsequent fp double
assign clear_lsu_sync_single = ext_flush | lsu_complete_d2;

assign ldst_sync_single_in = (lsu_sync_raw_w & ~clear_lsu_sync_single & fpdest_single_w) |
		             (~lsu_sync_raw_w & ~clear_lsu_sync_single & ldst_sync_single);

pku_swl_ctl_msff_ctl_macro__width_1 ldst_sync_singlef  (
 .scan_in(ldst_sync_singlef_scanin),
 .scan_out(ldst_sync_singlef_scanout),
 .l1clk(l1clk_pm1),
 .din  (ldst_sync_single_in),
 .dout (ldst_sync_single),
  .siclk(siclk),
  .soclk(soclk)
);


// wait a cycle if a ldfsr misses to make sure ccr's are updated correctly
assign clear_lsu_sync_ldfsr = ext_flush | lsu_complete_d2;

// NOTE: load with no fdest and no idest MUST be ldfsr
assign fsrsync_w = specld_w & ~fdest_w & ~idest_w;

assign ldst_sync_ldfsr_in = (lsu_sync_raw_w & ~clear_lsu_sync_ldfsr & fsrsync_w) |
		           (~lsu_sync_raw_w & ~clear_lsu_sync_ldfsr & ldst_sync_ldfsr);

pku_swl_ctl_msff_ctl_macro__width_1 ldst_sync_ldfsrf  (
 .scan_in(ldst_sync_ldfsrf_scanin),
 .scan_out(ldst_sync_ldfsrf_scanout),
 .l1clk(l1clk_pm1),
 .din  (ldst_sync_ldfsr_in),
 .dout (ldst_sync_ldfsr),
  .siclk(siclk),
  .soclk(soclk)
);

// track stores down the pipe to the store buffer

assign br_flush1_in = br_mispredict_e & ~(lsu_sync_w | ext_flush);
pku_swl_ctl_msff_ctl_macro__width_1 brflush1_f  (
 .scan_in(brflush1_f_scanin),
 .scan_out(brflush1_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (br_flush1_in),
 .dout (br_flush1),
  .siclk(siclk),
  .soclk(soclk)
);

assign br_flush2_in = br_flush1 &  ~(lsu_sync_w | ext_flush);
pku_swl_ctl_msff_ctl_macro__width_1 brflush2_f  (
 .scan_in(brflush2_f_scanin),
 .scan_out(brflush2_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (br_flush2_in),
 .dout (brflush2),
  .siclk(siclk),
  .soclk(soclk)	
);

assign not_annul_ds1_in = ~annul_ds_dcti_e;
pku_swl_ctl_msff_ctl_macro__width_1 not_annul_ds1_f  (
 .scan_in(not_annul_ds1_f_scanin),
 .scan_out(not_annul_ds1_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (not_annul_ds1_in),
 .dout (not_annul_ds1),
  .siclk(siclk),
  .soclk(soclk)
);

assign not_annul_ds2_in = not_annul_ds1;
pku_swl_ctl_msff_ctl_macro__width_1 not_annul_ds2_f  (
 .scan_in(not_annul_ds2_f_scanin),
 .scan_out(not_annul_ds2_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (not_annul_ds2_in),
 .dout (not_annul_ds2),
  .siclk(siclk),
  .soclk(soclk)
);


//assign store_ds1_in = (br_mispredict_e & ~annul_ds_dcti_e & vld_d & pick_store_d) & ~(lsu_sync_w | ext_flush);

assign store_ds1_in = (~annul_ds_dcti_e & vld_d & pick_store_d) & ~(lsu_sync_w | ext_flush);

pku_swl_ctl_msff_ctl_macro__width_1 store_ds1_f  (
 .scan_in(store_ds1_f_scanin),
 .scan_out(store_ds1_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (store_ds1_in),
 .dout (store_ds1),
  .siclk(siclk),
  .soclk(soclk)
);

assign store_ds2_in = (store_ds1 | (not_annul_ds1 & vld_d & pick_store_d)) & ~(lsu_sync_w | ext_flush);

pku_swl_ctl_msff_ctl_macro__width_1 store_ds2_f  (
 .scan_in(store_ds2_f_scanin),
 .scan_out(store_ds2_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (store_ds2_in),
 .dout (store_ds2),
  .siclk(siclk),
  .soclk(soclk)
);

assign store_ds = (store_ds2 | (not_annul_ds2 & vld_d & pick_store_d)) & ~(lsu_sync_w | ext_flush);

assign restore_scnt = (brflush2 | lsu_sync_w | ext_flush);

// delay allocation of store into the scnt for timing
assign pick_store_p = (pick_p & ~late_flush_p & store_p);

pku_swl_ctl_msff_ctl_macro__width_1 pickstoref  (
 .scan_in(pickstoref_scanin),
 .scan_out(pickstoref_scanout),
 .l1clk(l1clk_pm2),
 .din  (pick_store_p),
 .dout (pick_store_d),
  .siclk(siclk),
  .soclk(soclk)
);

assign alloc_scnt = pick_store_d;

assign dealloc_scnt = lsu_stb_dealloc;

// take everything into account except for annuling stores   
assign inc_scnt_raw = alloc_scnt & ~dealloc_scnt;
assign dec_scnt_raw = ~alloc_scnt & dealloc_scnt;
assign hold_scnt_raw = ~inc_scnt_raw & ~dec_scnt_raw;

// take annuling into account
// if you annul a store then you need to decrement scnt by 1
assign annul_store_in = annul_ds_dcti_e & vld_d & pick_store_d & ~restore_scnt & ~full_scnt;

pku_swl_ctl_msff_ctl_macro__width_1 annul_store_f  (
 .scan_in(annul_store_f_scanin),
 .scan_out(annul_store_f_scanout),
 .l1clk(l1clk_pm1),
 .din  (annul_store_in),
 .dout (annul_store_d),
  .siclk(siclk),
  .soclk(soclk)
);

// take into account that the store may be annuled

assign inc_scnt =  (inc_scnt_raw & ~annul_store_d);
assign dec1_scnt = (dec_scnt_raw & ~annul_store_d) | (hold_scnt_raw & annul_store_d);
assign hold_scnt = (hold_scnt_raw & ~annul_store_d) | (inc_scnt_raw & annul_store_d);
assign dec2_scnt = (dec_scnt_raw & annul_store_d);
    
// on a restore_scnt, pick must keep track of the DS is a store and whether it is annuled or not
   
assign inc2_ccnt = (inc_ccnt_raw & store_ds);
assign inc1_ccnt = (inc_ccnt_raw & ~store_ds) | (hold_ccnt_raw & store_ds);
assign hold_ccnt = (hold_ccnt_raw & ~store_ds) | (dec_ccnt_raw & store_ds);
assign dec1_ccnt = (dec_ccnt_raw & ~store_ds);
   

assign ccnt_in[3:0] = ({4{hold_ccnt}} & ccnt[3:0]) |
	              ({4{inc2_ccnt}} & (ccnt[3:0]+4'b0010)) |
		      ({4{inc1_ccnt}} & (ccnt[3:0]+4'b0001)) |
		      ({4{dec1_ccnt}} & (ccnt[3:0]-4'b0001));

// 0in bits_on -var {hold_ccnt,inc2_ccnt,inc1_ccnt,dec1_ccnt} -max 1 -message "bad ccnt update"

// compute scnt
assign scnt_in[3:0] = (({4{~restore_scnt & hold_scnt & ~full_scnt}} & scnt[3:0]) |
	               ({4{~restore_scnt & inc_scnt & ~full_scnt}} & (scnt[3:0]+4'b0001)) |
		       ({4{~restore_scnt & dec1_scnt & ~full_scnt}} & (scnt[3:0]-4'b0001)) |
		       ({4{~restore_scnt & dec2_scnt & ~full_scnt}} & (scnt[3:0]-4'b0010)) |
		       ({4{restore_scnt & ~full_scnt}} & ccnt_in[3:0]) |
                       ({4{full_scnt}} & 4'b1000)) & {4{~lsu_block_store_kill}};

// 0in bits_on -var {hold_scnt,inc_scnt,dec1_scnt} -max 1 -message "scnt selects not mutually exclusive"

// 0in value -var scnt[3:0] -val 4'b0000 4'b0001 4'b0010 4'b0011 4'b0100 4'b0101 4'b0110 4'b0111 4'b1000 -message "scnt[3:0] illegal state"

pku_swl_ctl_msff_ctl_macro__width_4 scnt_f  (
 .scan_in(scnt_f_scanin),
 .scan_out(scnt_f_scanout),
 .l1clk(l1clk_pm1),
 .din  (scnt_in[3:0]),
 .dout (scnt[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign alloc_ccnt = lsu_stb_alloc;
assign dealloc_ccnt = lsu_stb_dealloc;

assign inc_ccnt_raw = alloc_ccnt & ~dealloc_ccnt;
assign dec_ccnt_raw = ~alloc_ccnt & dealloc_ccnt;
assign hold_ccnt_raw = ~inc_ccnt_raw & ~dec_ccnt_raw;

assign ccnt_raw_in[3:0] = (({4{hold_ccnt_raw}} & ccnt[3:0]) |
		           ({4{inc_ccnt_raw}} & (ccnt[3:0]+4'b0001)) |
		           ({4{dec_ccnt_raw}} & (ccnt[3:0]-4'b0001))) & {4{~lsu_block_store_kill}};


// 0in value -var ccnt[3:0] -val 4'b0000 4'b0001 4'b0010 4'b0011 4'b0100 4'b0101 4'b0110 4'b0111 4'b1000 -message "ccnt[3:0] illegal state"

// 0in assert -var (~(ccnt[3:0]>scnt[3:0])) -message "unexpected ccnt[3:0] > scnt[3:0]"

pku_swl_ctl_msff_ctl_macro__width_4 ccnt_f  (
 .scan_in(ccnt_f_scanin),
 .scan_out(ccnt_f_scanout),
 .l1clk(l1clk_pm1),
 .din  (ccnt_raw_in[3:0]),
 .dout (ccnt[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// stb is full; cancel pick
//assign stb_cancel = (scnt[3] & store_p) | (scnt[2] & scnt[1] & scnt[0] & pick_store_d);

assign stb_cancel = (scnt[3] | (scnt[2] & scnt[1] & scnt[0] & pick_store_d)) & store_p;

assign stb_wait_in = stb_cancel;

assign rdy_in = ~( 	lsu_sync_wait_in |
			otherdivide_wait_in  |
			divide_wait_in | 
			postsync_in |
			postsync_ns_in |
			dep_wait_in |			// wait due to dependency
			stb_wait_in |
		        dcti_wait_in |
			dcti_couple_wait_in );

// in multithread mode, added w stage to give load flush a chance before transitioning from spec to ready

assign spec_in = (spec_en & vld_d_in & (specbr_d_in | specld_d_in)) |
	         (spec_en & vld_e_in & (specbr_e_in | specld_e_in)) |
	         (spec_en & vld_m_in & specld_m_in) |
	         (spec_en & vld_b_in & specld_b_in) |
	         (spec_en & vld_w_in & specld_w_in);   


// 0in assert -var (~(tlu_halted & spec_in)) -message "spec_in must be 0 if tlu_halted is a 1"

assign ready_in = rdy_in & ~tlu_halted & ~spec_in;

pku_swl_ctl_msff_ctl_macro__width_1 readyf  (
 .scan_in(readyf_scanin),
 .scan_out(readyf_scanout),
 .l1clk(l1clk_pm1),
 .din  (ready_in),
 .dout (swl_ready_p),
  .siclk(siclk),
  .soclk(soclk)
);

// remove tlu_halted since spec_in must be 0 if tlu_halted is asserted
assign spec_ready_in = rdy_in & spec_in;

pku_swl_ctl_msff_ctl_macro__width_1 spec_readyf  (
 .scan_in(spec_readyf_scanin),
 .scan_out(spec_readyf_scanout),
 .l1clk(l1clk_pm1),
 .din  (spec_ready_in),
 .dout (swl_spec_ready_p),
  .siclk(siclk),
  .soclk(soclk)
);


// track all delay slots down the pipe for tlu

assign allds_actual_p = (allds_p | allds_is_p) & ~(lsu_sync_w | ext_flush);
assign allds_actual_d = (allds_d | allds_is_d) & ~(lsu_sync_w | ext_flush);

assign allds_p_in = ~actual_pick_p & allds_actual_p;

pku_swl_ctl_msff_ctl_macro__width_1 allds_p_f  (
 .scan_in(allds_p_f_scanin),
 .scan_out(allds_p_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (allds_p_in),
 .dout (allds_p),
  .siclk(siclk),
  .soclk(soclk)
);

assign allds_d_in = (actual_pick_p & allds_actual_p) |
   	  	    (~dec_decode_d & allds_actual_d);
		   
pku_swl_ctl_msff_ctl_macro__width_1 allds_d_f  (
 .scan_in(allds_d_f_scanin),
 .scan_out(allds_d_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (allds_d_in),
 .dout (allds_d),
  .siclk(siclk),
  .soclk(soclk)
);

assign allds_e_in = dec_decode_d & allds_actual_d;

pku_swl_ctl_msff_ctl_macro__width_1 allds_e_f  (
 .scan_in(allds_e_f_scanin),
 .scan_out(allds_e_f_scanout),
 .l1clk(l1clk_pm2),
 .din  (allds_e_in),
 .dout (pku_ds_e),
  .siclk(siclk),
  .soclk(soclk)
);

// pipeline tracking
// decode, execute, memory(dcache access), writeback (hit/miss determination)

// any flush will clear the proper valids the next cycle

assign set_vld_d = actual_pick_p;

assign clear_vld_d = dec_decode_d | flush_d;

assign vld_d_in = (vld_d & ~clear_vld_d) | set_vld_d;

pku_swl_ctl_msff_ctl_macro__width_1 vld_df  (
 .scan_in(vld_df_scanin),
 .scan_out(vld_df_scanout),
 .l1clk(l1clk_pm2),
 .din  (vld_d_in),
 .dout (vld_d),
  .siclk(siclk),
  .soclk(soclk)
);


assign vld_e_in = vld_d & dec_decode_d & ~flush_d;

pku_swl_ctl_msff_ctl_macro__width_1 vld_ef  (
 .scan_in(vld_ef_scanin),
 .scan_out(vld_ef_scanout),
 .l1clk(l1clk_pm2),
 .din  (vld_e_in),
 .dout (vld_e),
  .siclk(siclk),
  .soclk(soclk)
);

assign valid_e = vld_e & dec_true_valid_e;  // final valid e taking exceptions into account

assign valid_e_in = vld_e_in & ~lsu_sync & ~tlu_flush_ifu & ~annul_ds_dcti_e;

pku_swl_ctl_msff_ctl_macro__width_1 valid_ef  (
 .scan_in(valid_ef_scanin),
 .scan_out(valid_ef_scanout),
 .l1clk(l1clk_pm2),
 .din  (valid_e_in),
 .dout (pku_valid_e),
  .siclk(siclk),
  .soclk(soclk)
);

assign vld_m_in = vld_e & ~flush_e;

pku_swl_ctl_msff_ctl_macro__width_1 vld_mf  (
 .scan_in(vld_mf_scanin),
 .scan_out(vld_mf_scanout),
 .l1clk(l1clk_pm2),
 .din  (vld_m_in),
 .dout (vld_m),
  .siclk(siclk),
  .soclk(soclk)
);

assign vld_b_in = vld_m & ~flush_m;

pku_swl_ctl_msff_ctl_macro__width_1 vld_bf  (
 .scan_in(vld_bf_scanin),
 .scan_out(vld_bf_scanout),
 .l1clk(l1clk_pm2),
 .din  (vld_b_in),
 .dout (vld_b),
  .siclk(siclk),
  .soclk(soclk)
);

assign vld_w_in = vld_b & ~flush_b;

pku_swl_ctl_msff_ctl_macro__width_1 vld_wf  (
 .scan_in(vld_wf_scanin),
 .scan_out(vld_wf_scanout),
 .l1clk(l1clk_pm2),
 .din  (vld_w_in),
 .dout (vld_w),
  .siclk(siclk),
  .soclk(soclk)
);

assign fpvld_w1_in = vld_w & specfp_w & ~ext_flush;

pku_swl_ctl_msff_ctl_macro__width_1 fpvld_w1f  (
 .scan_in(fpvld_w1f_scanin),
 .scan_out(fpvld_w1f_scanout),
 .l1clk(l1clk_pm2),
 .din  (fpvld_w1_in),
 .dout (fpvld_w1),
  .siclk(siclk),
  .soclk(soclk)
);

assign fpvld_w2_in = fpvld_w1 & ~ext_flush;

pku_swl_ctl_msff_ctl_macro__width_1 fpvld_w2f  (
 .scan_in(fpvld_w2f_scanin),
 .scan_out(fpvld_w2f_scanout),
 .l1clk(l1clk_pm2),
 .din  (fpvld_w2_in),
 .dout (fpvld_w2),
  .siclk(siclk),
  .soclk(soclk)
);

// seperate pipeline for address tracking with no DS flushing

assign set_vldraw_d = actual_raw_pick_p; 

assign clear_vldraw_d = dec_decode_d | rawflush_d;

assign vldraw_d_in = (vldraw_d & ~clear_vldraw_d) | set_vldraw_d;

pku_swl_ctl_msff_ctl_macro__width_1 vldraw_df  (
 .scan_in(vldraw_df_scanin),
 .scan_out(vldraw_df_scanout),
 .l1clk(l1clk_pm2),
 .din  (vldraw_d_in),
 .dout (vldraw_d),
  .siclk(siclk),
  .soclk(soclk)
);

assign vldraw_e_in = dec_decode_d & vldraw_d;

pku_swl_ctl_msff_ctl_macro__width_1 vldraw_ef  (
 .scan_in(vldraw_ef_scanin),
 .scan_out(vldraw_ef_scanout),
 .l1clk(l1clk_pm2),
 .din  (vldraw_e_in),
 .dout (vldraw_e),
  .siclk(siclk),
  .soclk(soclk)
);

assign vldraw_m_in = vldraw_e;

pku_swl_ctl_msff_ctl_macro__width_1 vldraw_mf  (
 .scan_in(vldraw_mf_scanin),
 .scan_out(vldraw_mf_scanout),
 .l1clk(l1clk_pm2),
 .din  (vldraw_m_in),
 .dout (vldraw_m),
  .siclk(siclk),
  .soclk(soclk)
);

// Include annulled instructions until branch is in W
// Since cnt is calculated a cycle ahead, count annulled until branch exits M

pku_swl_ctl_msff_ctl_macro__width_1 annul_ds_dcti_mf  (
 .scan_in(annul_ds_dcti_mf_scanin),
 .scan_out(annul_ds_dcti_mf_scanout),
 .l1clk(l1clk_pm2),
 .din  (annul_ds_dcti_e),
 .dout (    annul_ds_dcti_m),
  .siclk(siclk),
  .soclk(soclk)
);

assign vldcnt_e_brtaken0_in = 
       ( pku_annul_ds_dcti_brtaken0_e & vldraw_e_in) | 
       ( annul_ds_dcti_m & vldraw_e_in) |
       (~pku_annul_ds_dcti_brtaken0_e & ~annul_ds_dcti_m & vld_d & dec_decode_d);  // dont need flush_d here

assign vldcnt_e_brtaken1_in = 
       ( pku_annul_ds_dcti_brtaken1_e & vldraw_e_in) | 
       ( annul_ds_dcti_m & vldraw_e_in) |
       (~pku_annul_ds_dcti_brtaken1_e & ~annul_ds_dcti_m & vld_d & dec_decode_d);  // dont need flush_d here
	     
assign vldcnt_m_in = 
       ( annul_ds_dcti_m & vldraw_m_in) |
       (~annul_ds_dcti_m & vld_m_in);
	     
assign pku_inst_cnt_brtaken0[1:0] = ({1'b0,vldcnt_e_brtaken0_in} + {1'b0,vldcnt_m_in} + {1'b0,vld_b_in});

assign pku_inst_cnt_brtaken1[1:0] = ({1'b0,vldcnt_e_brtaken1_in} + {1'b0,vldcnt_m_in} + {1'b0,vld_b_in});

// end address logic


// track down to fb to flush inst in the fgu on a trap

assign vld_f4_in = vld_w & fgu_w & ~flush_w;

pku_swl_ctl_msff_ctl_macro__width_1 vld_f4f  (
 .scan_in(vld_f4f_scanin),
 .scan_out(vld_f4f_scanout),
 .l1clk(l1clk_pm2),
 .din  (vld_f4_in),
 .dout (vld_f4),
  .siclk(siclk),
  .soclk(soclk)
);

assign vld_f5_in = vld_f4 & ~flush_f4;

pku_swl_ctl_msff_ctl_macro__width_1 vld_f5f  (
 .scan_in(vld_f5f_scanin),
 .scan_out(vld_f5f_scanout),
 .l1clk(l1clk_pm2),
 .din  (vld_f5_in),
 .dout (vld_f5),
  .siclk(siclk),
  .soclk(soclk)
);

assign vld_fb_in = vld_f5 & ~flush_f5;

pku_swl_ctl_msff_ctl_macro__width_1 vld_fbf  (
 .scan_in(vld_fbf_scanin),
 .scan_out(vld_fbf_scanout),
 .l1clk(l1clk_pm2),
 .din  (vld_fb_in),
 .dout (vld_fb),
  .siclk(siclk),
  .soclk(soclk)
);

// pipe raw data down the pipe
// speculate decode to avoid loading
// must qualify with vld's before using

// anytwocycle - inst is twocycle or pdist
// postsync - inst is a postsync
// div   - inst is a divide inst
// bkick - inst should be kicked out of wait a b stage
// fpdest_double - fp dest double precision
// fpdest_single - fp dest single precision
// fccdest - inst will modify fcc 
// lsu - inst executed by lsu
// fgu - inst executed by fgu
// fbkick - inst should be kicked out of wait at fb stage
// specfp - inst is fgu that is speculated on
// fdest - inst has FP dest
// idest - inst has integer dest
// div - any divide (int or fpu)
// condbr_p - conditional branch
// callclass_p - one of call, jmp or return 
// annul - annul bit
// specbr - branch that is speculated on if spec_en==1
// dcti - has delay slot
// specld - integer load that is speculated on if spec_en==1
// rd[4:0] - destination of load

assign any_twocycle_p = pku_twocycle_p | pku_pdist_p;

assign data_d_in[23:0] = ({24{pick_p}} & {any_twocycle_p,postsync_p,div_p,bkick_p,fpdest_double_p,fpdest_single_p,fccdest_p,pku_lsu_p,pku_fgu_p,fbkick_p,specfp_p,pku_fdest_p,pku_idest_p,condbr_p,callclass_p,annul,specbr_p,dcti_p,specld_p,rd[4:0]}) |
			 ({24{~pick_p}} & data_d[23:0]);

assign specld_d_in = data_d_in[5];
assign specbr_d_in = data_d_in[7];

pku_swl_ctl_msff_ctl_macro__width_24 data_df  (
 .scan_in(data_df_scanin),
 .scan_out(data_df_scanout),
 .l1clk(l1clk_pm2),
 .din  (data_d_in[23:0]),
 .dout (data_d[23:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign {any_twocycle_d,postsync_d,div_d,bkick_d,fpdest_double_d,fpdest_single_d,fccdest_d,lsu_d,
        fgu_d,fbkick_d,
        specfp_d,fdest_d,idest_d,condbr_d,callclass_d,annul_d, 
        specbr_d,dcti_d,specld_d,rd_d[4:0]} = data_d[23:0];

assign specbr_e_in = specbr_d;

assign specld_e_in = specld_d;
assign specld_m_in = specld_e;
assign specld_b_in = specld_m;
assign specld_w_in = specld_b;


pku_swl_ctl_msff_ctl_macro__width_20 rdf  (
 .scan_in(rdf_scanin),
 .scan_out(rdf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({rd_d[4:0],rd_e[4:0],rd_m[4:0],rd_b[4:0]}),
 .dout ({rd_e[4:0],rd_m[4:0],rd_b[4:0],rd_w[4:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_2 anytwocyclef  (
 .scan_in(anytwocyclef_scanin),
 .scan_out(anytwocyclef_scanout),
 .l1clk(l1clk_pm2),
 .din  ({any_twocycle_d,any_twocycle_e}),
 .dout ({any_twocycle_e,any_twocycle_m}),
  .siclk(siclk),
  .soclk(soclk)
);


pku_swl_ctl_msff_ctl_macro__width_4 specldf  (
 .scan_in(specldf_scanin),
 .scan_out(specldf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({specld_d,specld_e,specld_m,specld_b}),
 .dout ({specld_e,specld_m,specld_b,specld_w}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 postsyncf  (
 .scan_in(postsyncf_scanin),
 .scan_out(postsyncf_scanout),
 .l1clk(l1clk_pm2),
 .din  (postsync_d),
 .dout (postsync_e),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 divf  (
 .scan_in(divf_scanin),
 .scan_out(divf_scanout),
 .l1clk(l1clk_pm2),
 .din  (div_d),
 .dout (div_e),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 dctif  (
 .scan_in(dctif_scanin),
 .scan_out(dctif_scanout),
 .l1clk(l1clk_pm2),
 .din  (dcti_d),
 .dout (dcti_e),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 specbref  (
 .scan_in(specbref_scanin),
 .scan_out(specbref_scanout),
 .l1clk(l1clk_pm2),
 .din  (specbr_d),
 .dout (specbr_e),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 specbrmf  (
 .scan_in(specbrmf_scanin),
 .scan_out(specbrmf_scanout),
 .l1clk(l1clk_pm2),
 .din  (specbr_e),
 .dout (specbr_m),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 annulf  (
 .scan_in(annulf_scanin),
 .scan_out(annulf_scanout),
 .l1clk(l1clk_pm2),
 .din  (annul_d),
 .dout (annul_e),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_2 callclassf  (
 .scan_in(callclassf_scanin),
 .scan_out(callclassf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({callclass_d,callclass_e}),
 .dout ({callclass_e,callclass_m}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_1 condbrf  (
 .scan_in(condbrf_scanin),
 .scan_out(condbrf_scanout),
 .l1clk(l1clk_pm2),
 .din  (condbr_d),
 .dout (condbr_e),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_4 idestf  (
 .scan_in(idestf_scanin),
 .scan_out(idestf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({idest_d,idest_e,idest_m,idest_b}),
 .dout ({idest_e,idest_m,idest_b,idest_w}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_4 fdestf  (
 .scan_in(fdestf_scanin),
 .scan_out(fdestf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({fdest_d,fdest_e,fdest_m,fdest_b}),
 .dout ({fdest_e,fdest_m,fdest_b,fdest_w}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_4 specfpf  (
 .scan_in(specfpf_scanin),
 .scan_out(specfpf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({specfp_d,specfp_e,specfp_m,specfp_b}),
 .dout ({specfp_e,specfp_m,specfp_b,specfp_w}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_7 fbkickf  (
 .scan_in(fbkickf_scanin),
 .scan_out(fbkickf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({fbkick_d,fbkick_e,fbkick_m,fbkick_b,fbkick_w,fbkick_f4,fbkick_f5}),
 .dout ({fbkick_e,fbkick_m,fbkick_b,fbkick_w,fbkick_f4,fbkick_f5,fbkick_fb}),
  .siclk(siclk),
  .soclk(soclk)
);

// on an inst error dec forces all decodes to zero; make pku forget fgu if there is one

assign fgu_d_in = fgu_d & ~dec_ierr_d & vld_d;


pku_swl_ctl_msff_ctl_macro__width_4 fguf  (
 .scan_in(fguf_scanin),
 .scan_out(fguf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({fgu_d_in,fgu_e,fgu_m,fgu_b}),
 .dout ({fgu_e,fgu_m,fgu_b,fgu_w}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_4 bkickf  (
 .scan_in(bkickf_scanin),
 .scan_out(bkickf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({bkick_d,bkick_e,bkick_m,bkick_b}),
 .dout ({bkick_e,bkick_m,bkick_b,bkick_w}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_6 fpdest_doublef  (
 .scan_in(fpdest_doublef_scanin),
 .scan_out(fpdest_doublef_scanout),
 .l1clk(l1clk_pm2),
 .din  ({fpdest_double_d,fpdest_double_e,fpdest_double_m,fpdest_double_b,fpdest_double_w,fpdest_double_f4}),
 .dout ({fpdest_double_e,fpdest_double_m,fpdest_double_b,fpdest_double_w,fpdest_double_f4,fpdest_double_f5}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_6 fpdest_singlef  (
 .scan_in(fpdest_singlef_scanin),
 .scan_out(fpdest_singlef_scanout),
 .l1clk(l1clk_pm2),
 .din  ({fpdest_single_d,fpdest_single_e,fpdest_single_m,fpdest_single_b,fpdest_single_w,fpdest_single_f4}),
 .dout ({fpdest_single_e,fpdest_single_m,fpdest_single_b,fpdest_single_w,fpdest_single_f4,fpdest_single_f5}),
  .siclk(siclk),
  .soclk(soclk)
);

pku_swl_ctl_msff_ctl_macro__width_3 fccdestf  (
 .scan_in(fccdestf_scanin),
 .scan_out(fccdestf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({fccdest_d,fccdest_e,fccdest_m}),
 .dout ({fccdest_e,fccdest_m,fccdest_b}),
  .siclk(siclk),
  .soclk(soclk)
);

// on an inst error dec forces all decodes to zero; make pku forget a load if there is one

assign lsu_d_in = lsu_d & ~dec_ierr_d & vld_d;

pku_swl_ctl_msff_ctl_macro__width_6 lsuf  (
 .scan_in(lsuf_scanin),
 .scan_out(lsuf_scanout),
 .l1clk(l1clk_pm2),
 .din  ({lsu_d_in,lsu_e,lsu_m,lsu_b,lsu_w,lsu_f4}),
 .dout ({lsu_e,lsu_m,lsu_b,lsu_w,lsu_f4,lsu_f5}),
  .siclk(siclk),
  .soclk(soclk)
);

// logic to generate internal flushes
// on a flush, all vld latches and wait states clear out the same cycle
// externally, the flush happens 1 cycle later off flop

// this signal will be late, flop before using
// only sync if something actually went down the pipe after the load 

assign lsu_sync_early = ~pku_flush_lb & (vld_d_in | vld_e_in | vld_m_in | vld_b_in);

assign lsu_sync_in = lsu_sync & lsu_sync_early;

pku_swl_ctl_msff_ctl_macro__width_1 lsu_syncf  (
 .scan_in(lsu_syncf_scanin),
 .scan_out(lsu_syncf_scanout),
 .l1clk(l1clk_pm2),
 .din  (lsu_sync_in),
 .dout (lsu_sync_w),
  .siclk(siclk),
  .soclk(soclk)
);

assign lsu_sync_raw_in = lsu_sync & ~pku_flush_lb;

pku_swl_ctl_msff_ctl_macro__width_1 lsu_sync_rawf  (
 .scan_in(lsu_sync_rawf_scanin),
 .scan_out(lsu_sync_rawf_scanout),
 .l1clk(l1clk_pm2),
 .din  (lsu_sync_raw_in),
 .dout (lsu_sync_raw_w),
  .siclk(siclk),
  .soclk(soclk)
);

// all branches that are taken are cti's

assign br_mispredict_e = valid_e & dec_br_taken_e;

// callclass = { call, jmpl, return } for which delay slot is never annuled
// for condbr's only not-taken can be annuled
// all unconditional branches can be annuled

// rework for timing
// assign annul_ds_dcti_e = ((valid_e & annul_e & condbr_e & ~dec_br_taken_e) |            // condbr not taken with a==1
//	  		     (valid_e & dcti_e & annul_e & ~condbr_e & ~callclass_e));	// branch always with a==1		

assign pku_annul_ds_dcti_brtaken0_e = ((valid_e & annul_e & condbr_e) |
				       (valid_e & dcti_e & annul_e & ~condbr_e & ~callclass_e));

assign pku_annul_ds_dcti_brtaken1_e = (valid_e & dcti_e & annul_e & ~condbr_e & ~callclass_e);

assign annul_ds_dcti_e = (~dec_br_taken_e & pku_annul_ds_dcti_brtaken0_e) |
		         ( dec_br_taken_e & pku_annul_ds_dcti_brtaken1_e);


assign allds_is_p = valid_e & dec_br_taken_e & ~annul_ds_dcti_e & ~vld_d;
assign allds_is_d = valid_e & dec_br_taken_e & ~annul_ds_dcti_e & vld_d;

// generate flush signals

// flush internally and externally 1 cycle after event

// pick can occur in a flush_p situation
// ideally, squash it but dcache_miss or dec_br_taken_e is probably too late ... lru is updated in this case

// annul_ds_dcti_e flushes the delay slot as needed
// br_mispredict_e flushes everything but the delay slot
// lsu_sync_w flushes everything


// late flush using the late br_mispredict and br annul signals
assign late_flush_p =  (br_mispredict_e & vld_d) |
		       (annul_ds_dcti_e & ~vld_d) |
                       (lsu_sync_w) |
		       (ext_flush);


assign flush_p =  (br_mispredict_m & (vld_d | vld_e)) |
		  (annul_ds_dcti_m & ~vld_d & ~vld_e) |
                  (lsu_sync_w) |
		  (ext_flush);

// for the address logic; no annuling
assign rawflush_p =  (br_mispredict_m & (vld_d | vld_e)) |
                     (lsu_sync_w) |
	   	     (ext_flush);
			
// all br's that can mispredict are dcti's

// annul covers br_mispredict_e as well since all branches that mispredict are dctis & annul has precedence over br_mispredict_e

assign flush_d =  (br_mispredict_m & vld_d & vld_e) |
		  (annul_ds_dcti_m & vld_d & ~vld_e) |  
                  (lsu_sync_w) |	
		  (ext_flush);		

assign rawflush_d = (lsu_sync_w) |	
		    (ext_flush);

assign flush_e = lsu_ext_flush_w | (annul_ds_dcti_m & vld_e);
assign flush_m = lsu_ext_flush_w;
assign flush_b = lsu_ext_flush_w;

assign flush_w = ext_flush;

assign flush_f3 = ext_flush;  // internal flush signals
assign flush_f4 = flush_f3;
assign flush_f5 = flush_f3;


// external flush signals to IFU
// prioritize so only 1 can fire at a time
// IFU will get trap flush separately

assign pku_load_flush_w = lsu_sync_w;

// external flush signals to the instruction buffers


// change this logic to always flush the buffers the cycle after the flush event occurs

assign br_mispredict_m_in = br_mispredict_e;

pku_swl_ctl_msff_ctl_macro__width_1 br_mispredict_mf  (
 .scan_in(br_mispredict_mf_scanin),
 .scan_out(br_mispredict_mf_scanout),
 .l1clk(l1clk_pm2),
 .din  (br_mispredict_m_in),
 .dout (br_mispredict_m),
  .siclk(siclk),
  .soclk(soclk)
);

assign pku_flush_upper_buffer = br_mispredict_m | lsu_sync_w | ext_flush;

assign pku_flush_buffer0 = flush_p;

// on trap will clear out thread in trap unit 

assign flush_m_in = (vld_m_in & tlu_flush_ifu) |
	            (vld_m_in & lsu_sync);

// generate right off flop for timing
pku_swl_ctl_msff_ctl_macro__width_1 flush_mf  (
 .scan_in(flush_mf_scanin),
 .scan_out(flush_mf_scanout),
 .l1clk(l1clk_pm2),
 .din  (flush_m_in),
 .dout (pku_flush_m),
  .siclk(siclk),
  .soclk(soclk)
);

assign pku_flush_b = vld_b & lsu_ext_flush_w;

// trap handles w stage
assign pku_flush_lm = vld_m & lsu_m & lsu_ext_flush_w;
assign pku_flush_lb = vld_b & lsu_b & lsu_ext_flush_w;

// flush signals to the fgu; trap handles f3 which is w stage
assign pku_flush_f1 = vld_m & fgu_m & lsu_ext_flush_w;
assign pku_flush_f2 = vld_b & fgu_b & lsu_ext_flush_w;


// unused bits 
assign i_unused[6:0]        = {i[15],i[14],i[4:0]};

supply0 vss;
supply1 vdd;

// fixscan start:
assign spares_scanin             = scan_in                  ;
assign do_modef_scanin           = spares_scanout           ;
assign external_flushf_scanin    = do_modef_scanout         ;
assign lsu_ext_flushf_scanin     = external_flushf_scanout  ;
assign tlu_retryf_scanin         = lsu_ext_flushf_scanout   ;
assign block_store_stallf_scanin = tlu_retryf_scanout       ;
assign post_syncf_scanin         = block_store_stallf_scanout;
assign spec_enf_scanin           = post_syncf_scanout       ;
assign active_threadf_scanin     = spec_enf_scanout         ;
assign postsync_nsf_scanin       = active_threadf_scanout   ;
assign divide_waitf_scanin       = postsync_nsf_scanout     ;
assign divide_wait1f_scanin      = divide_waitf_scanout     ;
assign lsu_completef_scanin      = divide_wait1f_scanout    ;
assign lsu_sync_waitf_scanin     = lsu_completef_scanout    ;
assign ldst_sync_singlef_scanin  = lsu_sync_waitf_scanout   ;
assign ldst_sync_ldfsrf_scanin   = ldst_sync_singlef_scanout;
assign brflush1_f_scanin         = ldst_sync_ldfsrf_scanout ;
assign brflush2_f_scanin         = brflush1_f_scanout       ;
assign not_annul_ds1_f_scanin    = brflush2_f_scanout       ;
assign not_annul_ds2_f_scanin    = not_annul_ds1_f_scanout  ;
assign store_ds1_f_scanin        = not_annul_ds2_f_scanout  ;
assign store_ds2_f_scanin        = store_ds1_f_scanout      ;
assign pickstoref_scanin         = store_ds2_f_scanout      ;
assign annul_store_f_scanin      = pickstoref_scanout       ;
assign scnt_f_scanin             = annul_store_f_scanout    ;
assign ccnt_f_scanin             = scnt_f_scanout           ;
assign readyf_scanin             = ccnt_f_scanout           ;
assign spec_readyf_scanin        = readyf_scanout           ;
assign allds_p_f_scanin          = spec_readyf_scanout      ;
assign allds_d_f_scanin          = allds_p_f_scanout        ;
assign allds_e_f_scanin          = allds_d_f_scanout        ;
assign vld_df_scanin             = allds_e_f_scanout        ;
assign vld_ef_scanin             = vld_df_scanout           ;
assign valid_ef_scanin           = vld_ef_scanout           ;
assign vld_mf_scanin             = valid_ef_scanout         ;
assign vld_bf_scanin             = vld_mf_scanout           ;
assign vld_wf_scanin             = vld_bf_scanout           ;
assign fpvld_w1f_scanin          = vld_wf_scanout           ;
assign fpvld_w2f_scanin          = fpvld_w1f_scanout        ;
assign vldraw_df_scanin          = fpvld_w2f_scanout        ;
assign vldraw_ef_scanin          = vldraw_df_scanout        ;
assign vldraw_mf_scanin          = vldraw_ef_scanout        ;
assign annul_ds_dcti_mf_scanin   = vldraw_mf_scanout        ;
assign vld_f4f_scanin            = annul_ds_dcti_mf_scanout ;
assign vld_f5f_scanin            = vld_f4f_scanout          ;
assign vld_fbf_scanin            = vld_f5f_scanout          ;
assign data_df_scanin            = vld_fbf_scanout          ;
assign rdf_scanin                = data_df_scanout          ;
assign anytwocyclef_scanin       = rdf_scanout              ;
assign specldf_scanin            = anytwocyclef_scanout     ;
assign postsyncf_scanin          = specldf_scanout          ;
assign divf_scanin               = postsyncf_scanout        ;
assign dctif_scanin              = divf_scanout             ;
assign specbref_scanin           = dctif_scanout            ;
assign specbrmf_scanin           = specbref_scanout         ;
assign annulf_scanin             = specbrmf_scanout         ;
assign callclassf_scanin         = annulf_scanout           ;
assign condbrf_scanin            = callclassf_scanout       ;
assign idestf_scanin             = condbrf_scanout          ;
assign fdestf_scanin             = idestf_scanout           ;
assign specfpf_scanin            = fdestf_scanout           ;
assign fbkickf_scanin            = specfpf_scanout          ;
assign fguf_scanin               = fbkickf_scanout          ;
assign bkickf_scanin             = fguf_scanout             ;
assign fpdest_doublef_scanin     = bkickf_scanout           ;
assign fpdest_singlef_scanin     = fpdest_doublef_scanout   ;
assign fccdestf_scanin           = fpdest_singlef_scanout   ;
assign lsuf_scanin               = fccdestf_scanout         ;
assign lsu_syncf_scanin          = lsuf_scanout             ;
assign lsu_sync_rawf_scanin      = lsu_syncf_scanout        ;
assign br_mispredict_mf_scanin   = lsu_sync_rawf_scanout    ;
assign flush_mf_scanin           = br_mispredict_mf_scanout ;
assign scan_out                  = flush_mf_scanout         ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module pku_swl_ctl_spare_ctl_macro__num_4 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));
assign scan_out = so_3;


endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_msff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_msff_ctl_macro__width_20 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [19:0] fdin;
wire [18:0] so;

  input [19:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [19:0] dout;
  output scan_out;
assign fdin[19:0] = din[19:0];


dff #(20)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[19:0]),
.si({scan_in,so[18:0]}),
.so({so[18:0],scan_out}),
.q(dout[19:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pku_swl_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pmu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module pmu (
  in_rngl_cdbus, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_bclk, 
  spc_aclk, 
  tcu_scan_en, 
  lsu_pmu_pmen, 
  lsu_asi_clken, 
  scan_out, 
  pmu_rngl_cdbus, 
  dec_pmu_instr0_type_d, 
  dec_pmu_instr1_type_d, 
  lsu_pmu_mem_type_b, 
  dec_br_taken_e, 
  dec_lsu_sel0_d, 
  mmu_pmu_l2ret, 
  mmu_pmu_l2miss, 
  mmu_pmu_dtlb, 
  mmu_pmu_tid, 
  l15_pmu_xbar_optype, 
  spu_pmu_cwq_busy, 
  spu_pmu_cwq_tid, 
  spu_pmu_ma_busy, 
  tlu_pmu_pstate_priv, 
  tlu_pmu_hpstate_hpriv, 
  tlu_pmu_trap_taken, 
  tlu_pmu_trap_mask_e, 
  dec_valid_e, 
  dec_flush_m, 
  dec_flush_b, 
  tlu_flush_pmu_b, 
  tlu_flush_pmu_w, 
  pmu_tlu_trap_m, 
  pmu_tlu_debug_event, 
  pmu_lsu_dcmiss_trap_m, 
  pmu_lsu_dtmiss_trap_m, 
  pmu_lsu_l2dmiss_trap_m);
wire pmu_pdp_dp_scanin;
wire pmu_pdp_dp_scanout;
wire pmu_pct_ctl_scanin;
wire pmu_pct_ctl_scanout;
wire [7:0] pct_rd_pic;
wire pct_rd_a_pic;
wire pct_rd_pic_pcr;
wire pct_bypass_asi;
wire [31:0] pct_pcr_data;
wire pct_exception;
wire [7:0] pct_pic_clken;
wire pct_pic07_w2_clken;
wire [7:0] pct_wr_pic_w2;
wire [6:0] pct_incr_pic_w1;
wire pct_incr_asi_w1;
wire [3:0] pct_pich07_add_w2;
wire [3:0] pct_picl07_add_w2;
wire pmu_asi_clken;
wire [31:0] pdp_asi_din_to_pctl;
wire [7:0] pdp_asi_ctlin_to_pctl_15_8;
wire [4:0] pdp_asi_ctlin_to_pctl_4_0;
wire pdp_pich_cout07;
wire pdp_picl_cout07;
wire [7:0] pdp_pich_wrap;
wire [7:0] pdp_picl_wrap;


input	[64:0]	in_rngl_cdbus;		// ASI local ring data in

input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input 		spc_bclk;
input 		spc_aclk;
input		tcu_scan_en;

// Power management
input		lsu_pmu_pmen;
input		lsu_asi_clken;

output		scan_out;

output	[64:0]  pmu_rngl_cdbus;		// ASI local ring data out 

// Instruction decode events
input	[12:0]	dec_pmu_instr0_type_d;	// {12 - valid; 11:10 - tid; 9:0 - {atomic_d, l2imiss, itmiss, icmiss, other, %sethi, store, load, FGU, branch}}
input	[12:0]	dec_pmu_instr1_type_d;
input	[5:0]	lsu_pmu_mem_type_b;	// {5:3 - tid (use for l2miss only); 2:0 - {l2 d-miss, dt_miss, d-cache miss}}
input	[1:0]	dec_br_taken_e;		// branch taken indicator
input		dec_lsu_sel0_d;		// select tg0 for LSU tid

// MMU activity (excluding ITLB/DTLB misses)
input 	        mmu_pmu_l2ret;          // indicates l2 data to MMU
input           mmu_pmu_l2miss;         // indicates the return pkt had l2 miss
input           mmu_pmu_dtlb;           // indicates that return pkt is for D-side table walk
input   [2:0]   mmu_pmu_tid;   		// thread id

// Crossbar activity
input	[6:0]	l15_pmu_xbar_optype;	// {6 - valid; 5:3 - tid; 2:0 - {111 - mastore; 110 - maload; 101 - ifetch; 100 - mmuld; 011 - cwqstore; 010 - cwqload; 001 - cpustore; 000 - cpuld}}

// SPU activity
input	[4:0]	spu_pmu_cwq_busy;	// CWQ busy {rc4,hash,des,crc,aes}
input	[2:0]	spu_pmu_cwq_tid;
input	[3:0]	spu_pmu_ma_busy;	// {3 - busy/idle; 2:0 - tid}

// state bits to decide when counters should record
input	[7:0] 	tlu_pmu_pstate_priv;	// pstate.priv for each thread (bit 7 == thread 7)
input	[7:0]	tlu_pmu_hpstate_hpriv;	// hpstate.hpriv (ditto)

// PMU trap is taken, reset the counter if "-"ve.
input   [7:0]   tlu_pmu_trap_taken;
input	[1:0]	tlu_pmu_trap_mask_e;	// True if TLU enabled for PMU trap {1 - tg1; 0 - tg0}

// Flushes from IFU and TLU
input   [1:0]	dec_valid_e;		// bit 1 is for TG1, 0 for TG0; 
                                        //instr valid in the e-stage (taken flush_e into consideration?)

input	[1:0]	dec_flush_m;		// bit 1 is for TG1, 0 for TG0
input	[1:0]	dec_flush_b;		// bit 1 is for TG1, 0 for TG0
input	[1:0]	tlu_flush_pmu_b;	// bit 1 is for TG1, 0 for TG0
input	[1:0]	tlu_flush_pmu_w;	// bit 1 is for TG1, 0 for TG0

// Signals to tell TLU if we may/should trap due to counter overflow
output	[7:0]	pmu_tlu_trap_m;		// Sent at beginning of M to TLU
output	[7:0]	pmu_tlu_debug_event;	// Tell trap if a perf. monitor event occurred to soft/hard stop/trigger on

// Signals to LSU for trap on DCmiss, DTmiss, L2Dmiss
output		pmu_lsu_dcmiss_trap_m;
output		pmu_lsu_dtmiss_trap_m;
output	[7:0]	pmu_lsu_l2dmiss_trap_m;

pmu_pdp_dp pmu_pdp_dp( 	
	.scan_in(pmu_pdp_dp_scanin),
	.scan_out(pmu_pdp_dp_scanout),
	.l2clk(l2clk),
	.pmu_rngl_cdbus(pmu_rngl_cdbus[63:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .in_rngl_cdbus(in_rngl_cdbus[63:0]),
  .pct_rd_pic(pct_rd_pic[7:0]),
  .pct_rd_a_pic(pct_rd_a_pic),
  .pct_rd_pic_pcr(pct_rd_pic_pcr),
  .pct_bypass_asi(pct_bypass_asi),
  .pct_pcr_data(pct_pcr_data[31:0]),
  .pct_exception(pct_exception),
  .pct_pic_clken(pct_pic_clken[7:0]),
  .pct_pic07_w2_clken(pct_pic07_w2_clken),
  .pct_wr_pic_w2(pct_wr_pic_w2[7:0]),
  .pct_incr_pic_w1(pct_incr_pic_w1[6:0]),
  .pct_incr_asi_w1(pct_incr_asi_w1),
  .pct_pich07_add_w2(pct_pich07_add_w2[3:0]),
  .pct_picl07_add_w2(pct_picl07_add_w2[3:0]),
  .pmu_asi_clken(pmu_asi_clken),
  .pdp_asi_din_to_pctl(pdp_asi_din_to_pctl[31:0]),
  .pdp_asi_ctlin_to_pctl_15_8(pdp_asi_ctlin_to_pctl_15_8[7:0]),
  .pdp_asi_ctlin_to_pctl_4_0(pdp_asi_ctlin_to_pctl_4_0[4:0]),
  .pdp_pich_cout07(pdp_pich_cout07),
  .pdp_picl_cout07(pdp_picl_cout07),
  .pdp_pich_wrap(pdp_pich_wrap[7:0]),
  .pdp_picl_wrap(pdp_picl_wrap[7:0])
	);

pmu_pct_ctl pmu_pct_ctl( 
	.in_rngl_cdbus_ctl_ndata(in_rngl_cdbus[64]),
        .pct_rngl_cdbus_ctl_ndata(pmu_rngl_cdbus[64]),                        
        .scan_in(pmu_pct_ctl_scanin),
        .scan_out(pmu_pct_ctl_scanout),
        .l2clk(l2clk),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .lsu_asi_clken(lsu_asi_clken),
  .lsu_pmu_pmen(lsu_pmu_pmen),
  .dec_pmu_instr0_type_d(dec_pmu_instr0_type_d[12:0]),
  .dec_pmu_instr1_type_d(dec_pmu_instr1_type_d[12:0]),
  .dec_br_taken_e(dec_br_taken_e[1:0]),
  .lsu_pmu_mem_type_b(lsu_pmu_mem_type_b[5:0]),
  .dec_lsu_sel0_d(dec_lsu_sel0_d),
  .mmu_pmu_l2ret(mmu_pmu_l2ret),
  .mmu_pmu_l2miss(mmu_pmu_l2miss),
  .mmu_pmu_dtlb(mmu_pmu_dtlb),
  .mmu_pmu_tid(mmu_pmu_tid[2:0]),
  .l15_pmu_xbar_optype(l15_pmu_xbar_optype[6:0]),
  .spu_pmu_cwq_busy(spu_pmu_cwq_busy[4:0]),
  .spu_pmu_cwq_tid(spu_pmu_cwq_tid[2:0]),
  .spu_pmu_ma_busy(spu_pmu_ma_busy[3:0]),
  .tlu_pmu_pstate_priv(tlu_pmu_pstate_priv[7:0]),
  .tlu_pmu_hpstate_hpriv(tlu_pmu_hpstate_hpriv[7:0]),
  .tlu_pmu_trap_taken(tlu_pmu_trap_taken[7:0]),
  .tlu_pmu_trap_mask_e(tlu_pmu_trap_mask_e[1:0]),
  .tlu_flush_pmu_b(tlu_flush_pmu_b[1:0]),
  .tlu_flush_pmu_w(tlu_flush_pmu_w[1:0]),
  .dec_valid_e(dec_valid_e[1:0]),
  .dec_flush_m(dec_flush_m[1:0]),
  .dec_flush_b(dec_flush_b[1:0]),
  .pdp_pich_cout07(pdp_pich_cout07),
  .pdp_picl_cout07(pdp_picl_cout07),
  .pdp_pich_wrap(pdp_pich_wrap[7:0]),
  .pdp_picl_wrap(pdp_picl_wrap[7:0]),
  .pdp_asi_ctlin_to_pctl_15_8(pdp_asi_ctlin_to_pctl_15_8[7:0]),
  .pdp_asi_ctlin_to_pctl_4_0(pdp_asi_ctlin_to_pctl_4_0[4:0]),
  .pdp_asi_din_to_pctl(pdp_asi_din_to_pctl[31:0]),
  .pmu_tlu_trap_m(pmu_tlu_trap_m[7:0]),
  .pmu_tlu_debug_event(pmu_tlu_debug_event[7:0]),
  .pct_pich07_add_w2(pct_pich07_add_w2[3:0]),
  .pct_picl07_add_w2(pct_picl07_add_w2[3:0]),
  .pmu_lsu_dcmiss_trap_m(pmu_lsu_dcmiss_trap_m),
  .pmu_lsu_dtmiss_trap_m(pmu_lsu_dtmiss_trap_m),
  .pmu_lsu_l2dmiss_trap_m(pmu_lsu_l2dmiss_trap_m[7:0]),
  .pct_rd_pic(pct_rd_pic[7:0]),
  .pct_rd_a_pic(pct_rd_a_pic),
  .pct_rd_pic_pcr(pct_rd_pic_pcr),
  .pct_bypass_asi(pct_bypass_asi),
  .pct_pcr_data(pct_pcr_data[31:0]),
  .pct_exception(pct_exception),
  .pct_wr_pic_w2(pct_wr_pic_w2[7:0]),
  .pct_incr_pic_w1(pct_incr_pic_w1[6:0]),
  .pct_incr_asi_w1(pct_incr_asi_w1),
  .pct_pic_clken(pct_pic_clken[7:0]),
  .pct_pic07_w2_clken(pct_pic07_w2_clken),
  .pmu_asi_clken(pmu_asi_clken)
	);

// fixscan start:
assign pmu_pdp_dp_scanin         = scan_in                  ;
assign pmu_pct_ctl_scanin        = pmu_pdp_dp_scanout       ;
assign scan_out                  = pmu_pct_ctl_scanout      ;
// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pmu_pct_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module pmu_pct_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_out, 
  lsu_asi_clken, 
  lsu_pmu_pmen, 
  dec_pmu_instr0_type_d, 
  dec_pmu_instr1_type_d, 
  dec_br_taken_e, 
  lsu_pmu_mem_type_b, 
  dec_lsu_sel0_d, 
  mmu_pmu_l2ret, 
  mmu_pmu_l2miss, 
  mmu_pmu_dtlb, 
  mmu_pmu_tid, 
  l15_pmu_xbar_optype, 
  spu_pmu_cwq_busy, 
  spu_pmu_cwq_tid, 
  spu_pmu_ma_busy, 
  tlu_pmu_pstate_priv, 
  tlu_pmu_hpstate_hpriv, 
  tlu_pmu_trap_taken, 
  tlu_pmu_trap_mask_e, 
  tlu_flush_pmu_b, 
  tlu_flush_pmu_w, 
  dec_valid_e, 
  dec_flush_m, 
  dec_flush_b, 
  pdp_pich_cout07, 
  pdp_picl_cout07, 
  pdp_pich_wrap, 
  pdp_picl_wrap, 
  in_rngl_cdbus_ctl_ndata, 
  pdp_asi_ctlin_to_pctl_15_8, 
  pdp_asi_ctlin_to_pctl_4_0, 
  pdp_asi_din_to_pctl, 
  pmu_tlu_trap_m, 
  pmu_tlu_debug_event, 
  pct_pich07_add_w2, 
  pct_picl07_add_w2, 
  pmu_lsu_dcmiss_trap_m, 
  pmu_lsu_dtmiss_trap_m, 
  pmu_lsu_l2dmiss_trap_m, 
  pct_rd_pic, 
  pct_rd_a_pic, 
  pct_rd_pic_pcr, 
  pct_bypass_asi, 
  pct_pcr_data, 
  pct_rngl_cdbus_ctl_ndata, 
  pct_exception, 
  pct_wr_pic_w2, 
  pct_incr_pic_w1, 
  pct_incr_asi_w1, 
  pct_pic_clken, 
  pct_pic07_w2_clken, 
  pmu_asi_clken);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire pwrm_scanin;
wire pwrm_scanout;
wire pmu_pmen;
wire pmu_busy;
wire skip_wakeup_in;
wire pmu_pmen_del_1;
wire pmu_busy_del_1;
wire skip_wakeup;
wire [31:0] pcr7_dout;
wire [31:0] pcr6_dout;
wire [31:0] pcr5_dout;
wire [31:0] pcr4_dout;
wire [31:0] pcr3_dout;
wire [31:0] pcr2_dout;
wire [31:0] pcr1_dout;
wire [31:0] pcr0_dout;
wire wakeup;
wire p_wr;
wire [7:0] atid;
wire [7:0] pic_std_w2;
wire sleep;
wire sleep_cnt_scanin;
wire sleep_cnt_scanout;
wire [3:0] sleep_cntr_din;
wire [3:0] sleep_cntr;
wire wait_for_sleep;
wire l1b;
wire l1clk_pm1;
wire ov_busy;
wire [7:0] wr_pcr;
wire [7:0] rd_pcr;
wire l1clk_pm2;
wire hpstate_scanin;
wire hpstate_scanout;
wire [7:0] hpriv;
wire [7:0] priv;
wire [5:0] mmu_mtyp;
wire events_scanin;
wire events_scanout;
wire rc4;
wire hash;
wire des;
wire crc;
wire aes;
wire [3:0] ma;
wire [12:0] tg0_e;
wire [12:0] tg1_e;
wire [1:0] dec_br_taken_m;
wire [5:0] mm_mtyp;
wire [5:0] mem_typ_w;
wire [6:0] xbar;
wire [2:0] spu_tid;
wire rc4_d1;
wire hash_d1;
wire des_d1;
wire crc_d1;
wire aes_d1;
wire ma_3_d1;
wire dec_lsu_sel0_e;
wire [11:0] tg0_ityp_e;
wire [11:0] tg1_ityp_e;
wire [2:0] lsu_tid_e;
wire lsutid_scanin;
wire lsutid_scanout;
wire [2:0] lsu_tid_m;
wire [2:0] lsu_tid_b;
wire [2:0] lsu_tid_w;
wire all_idle_e;
wire [7:0] th;
wire [7:0] cwq_tid;
wire [7:0] desb;
wire [7:0] aesb;
wire [7:0] rc4b;
wire [7:0] hashb;
wire [7:0] crcb;
wire [7:0] ma_tid;
wire [7:0] mab;
wire [7:0] dcm;
wire [7:0] dtm;
wire [7:0] l2m;
wire [7:0] ov1;
wire [7:0] set_ovh_spec;
wire [7:0] ov0;
wire [7:0] set_ovl_spec;
wire [7:0] ht_in;
wire [29:0] pcr0_din;
wire [7:0] disable_h;
wire [7:0] disable_l;
wire l1clk_pm3;
wire pcr0_scanin;
wire pcr0_scanout;
wire bit63;
wire bit62;
wire [1:0] x0;
wire pcr0_ov_scanin;
wire pcr0_ov_scanout;
wire [29:0] pcr1_din;
wire pcr1_scanin;
wire pcr1_scanout;
wire [1:0] x1;
wire pcr1_ov_scanin;
wire pcr1_ov_scanout;
wire [29:0] pcr2_din;
wire pcr2_scanin;
wire pcr2_scanout;
wire [1:0] x2;
wire pcr2_ov_scanin;
wire pcr2_ov_scanout;
wire [29:0] pcr3_din;
wire pcr3_scanin;
wire pcr3_scanout;
wire [1:0] x3;
wire pcr3_ov_scanin;
wire pcr3_ov_scanout;
wire [29:0] pcr4_din;
wire pcr4_scanin;
wire pcr4_scanout;
wire [1:0] x4;
wire pcr4_ov_scanin;
wire pcr4_ov_scanout;
wire [29:0] pcr5_din;
wire pcr5_scanin;
wire pcr5_scanout;
wire [1:0] x5;
wire pcr5_ov_scanin;
wire pcr5_ov_scanout;
wire [29:0] pcr6_din;
wire pcr6_scanin;
wire pcr6_scanout;
wire [1:0] x6;
wire pcr6_ov_scanin;
wire pcr6_ov_scanout;
wire [29:0] pcr7_din;
wire pcr7_scanin;
wire pcr7_scanout;
wire [1:0] x7;
wire pcr7_ov_scanin;
wire pcr7_ov_scanout;
wire pcr_ov_del_scanin;
wire pcr_ov_del_scanout;
wire [1:0] x7_1;
wire [1:0] x6_1;
wire [1:0] x5_1;
wire [1:0] x4_1;
wire [1:0] x3_1;
wire [1:0] x2_1;
wire [1:0] x1_1;
wire [1:0] x0_1;
wire [7:0] p_cnt_en;
wire [7:0] ph_all_idle;
wire [7:0] ph_ig;
wire [7:0] ph_cg;
wire [7:0] ph_mm;
wire [7:0] ph_xb;
wire [7:0] ph_so;
wire [7:0] ph_sb;
wire [7:0] pl_all_idle;
wire [7:0] pl_ig;
wire [7:0] pl_cg;
wire [7:0] pl_mm;
wire [7:0] pl_xb;
wire [7:0] pl_so;
wire [7:0] pl_sb;
wire [7:0] dcm_h;
wire [7:0] dcm_l;
wire [7:0] pmu_lsu_dcmiss_trap_e;
wire [7:0] pich_wrap;
wire [7:0] picl_wrap;
wire [7:0] t;
wire pmu_lsu_dcm_trap_e;
wire [7:0] dtm_h;
wire [7:0] dtm_l;
wire [7:0] pmu_lsu_dtmiss_trap_e;
wire pmu_lsu_dtm_trap_e;
wire [7:0] l2dm_h;
wire [7:0] l2dm_l;
wire lsu_e2m_scanin;
wire lsu_e2m_scanout;
wire [7:0] l2dm_wrap_e;
wire [7:0] lsu_trap_mask_m_din;
wire [7:0] l2dm_wrap_m;
wire [7:0] lsu_trap_mask_m;
wire [7:0] th_m;
wire [1:0] tlu_pmu_trap_mask_m;
wire [7:0] lsu_tidm_update_m;
wire [1:0] dec_valid_m;
wire [7:0] ph_ai;
wire [7:0] pl_ai;
wire [7:0] ph_ige;
wire [7:0] pl_ige;
wire [7:0] ph_bre;
wire [7:0] pl_bre;
wire [7:0] dcm_he;
wire [7:0] dtm_he;
wire [7:0] l2m_he;
wire [7:0] dcm_le;
wire [7:0] dtm_le;
wire [7:0] l2m_le;
wire [7:0] ph_icge;
wire [7:0] pl_icge;
wire [7:0] mm_tid;
wire [3:0] mm_l2e;
wire [7:0] ph_mme;
wire [7:0] pl_mme;
wire [5:0] xb;
wire use_ma;
wire use_cwq;
wire [2:0] xbtid;
wire [7:0] ph_xbe;
wire [7:0] pl_xbe;
wire [7:0] spu_des;
wire [7:0] spu_aes;
wire [7:0] spu_rc4;
wire [7:0] spu_hash;
wire [7:0] spu_ma;
wire [7:0] spu_crc;
wire [7:0] ph_soe;
wire [7:0] pl_soe;
wire [7:0] ph_sbe;
wire [7:0] pl_sbe;
wire [7:0] ovh;
wire [7:0] ovl;
wire [7:0] pipeh_incr_e;
wire [7:0] pipel_incr_e;
wire [7:0] pipeh_incr_m;
wire [7:0] ph_brm;
wire [7:0] pipel_incr_m;
wire [7:0] pl_brm;
wire [7:0] pipeh_incr_w;
wire [7:0] pipel_incr_w;
wire [7:0] pipeh_async;
wire [7:0] pipel_async;
wire tp_scanin;
wire tp_scanout;
wire [7:0] trap_e;
wire [7:0] trap_b_in;
wire [7:0] trap_w_in;
wire [7:0] trap_w1_in;
wire [7:0] tpt;
wire [7:0] trap_m;
wire [7:0] trap_b;
wire [7:0] trap_w;
wire [7:0] trap_w1;
wire tp1_scanin;
wire tp1_scanout;
wire [7:0] trap_hold_in;
wire [7:0] trap_hold;
wire br_scanin;
wire br_scanout;
wire [7:0] ph_br_may_trap_m;
wire [1:0] ifu_fl_b;
wire [1:0] fl_w;
wire [7:0] trap_w1_final;
wire [1:0] tlu_fl_w1;
wire [7:0] async;
wire ti_e2m_scanin;
wire ti_e2m_scanout;
wire [7:0] ph_incr_m;
wire [7:0] pl_incr_m;
wire [7:0] ph_i_m;
wire [7:0] pl_i_m;
wire ti_m2b_scanin;
wire ti_m2b_scanout;
wire [7:0] ph_incr_b;
wire [7:0] pl_incr_b;
wire [7:0] ph_i_b;
wire [7:0] pl_i_b;
wire ti_b2w_scanin;
wire ti_b2w_scanout;
wire [7:0] ph_incr_w;
wire [7:0] pl_incr_w;
wire [7:0] ph_i_w;
wire [7:0] pl_i_w;
wire ti_w2w1_scanin;
wire ti_w2w1_scanout;
wire [7:0] ph_incr_w1;
wire [7:0] pl_incr_w1;
wire [7:0] flush_h;
wire [7:0] flush_l;
wire [7:0] ph_final_incr_w1;
wire [7:0] pl_final_incr_w1;
wire [7:0] pic_std_w1;
wire [7:0] pic_st_dout;
wire [7:0] pic_st_din;
wire pic_st_scanin;
wire pic_st_scanout;
wire [3:0] t0h_din;
wire [3:0] t0h_dout;
wire t0h_scanin;
wire t0h_scanout;
wire [3:0] t1h_din;
wire [3:0] t1h_dout;
wire t1h_scanin;
wire t1h_scanout;
wire [3:0] t2h_din;
wire [3:0] t2h_dout;
wire t2h_scanin;
wire t2h_scanout;
wire [3:0] t3h_din;
wire [3:0] t3h_dout;
wire t3h_scanin;
wire t3h_scanout;
wire [3:0] t4h_din;
wire [3:0] t4h_dout;
wire t4h_scanin;
wire t4h_scanout;
wire [3:0] t5h_din;
wire [3:0] t5h_dout;
wire t5h_scanin;
wire t5h_scanout;
wire [3:0] t6h_din;
wire [3:0] t6h_dout;
wire t6h_scanin;
wire t6h_scanout;
wire [3:0] t7h_din;
wire [3:0] t7h_dout;
wire t7h_scanin;
wire t7h_scanout;
wire [3:0] t0l_din;
wire [3:0] t0l_dout;
wire t0l_scanin;
wire t0l_scanout;
wire [3:0] t1l_din;
wire [3:0] t1l_dout;
wire t1l_scanin;
wire t1l_scanout;
wire [3:0] t2l_din;
wire [3:0] t2l_dout;
wire t2l_scanin;
wire t2l_scanout;
wire [3:0] t3l_din;
wire [3:0] t3l_dout;
wire t3l_scanin;
wire t3l_scanout;
wire [3:0] t4l_din;
wire [3:0] t4l_dout;
wire t4l_scanin;
wire t4l_scanout;
wire [3:0] t5l_din;
wire [3:0] t5l_dout;
wire t5l_scanin;
wire t5l_scanout;
wire [3:0] t6l_din;
wire [3:0] t6l_dout;
wire t6l_scanin;
wire t6l_scanout;
wire [3:0] t7l_din;
wire [3:0] t7l_dout;
wire t7l_scanin;
wire t7l_scanout;
wire [3:0] pich07_add_in_w1;
wire [7:0] incr_asi;
wire [3:0] picl07_add_in_w1;
wire accum_scanin;
wire accum_scanout;
wire [15:8] asi_cntrl_h;
wire [4:0] asi_cntrl;
wire asr;
wire asr_rd;
wire asi_ctl_ndata;
wire asr_wr;
wire pcr;
wire pic;
wire pic_rd;
wire pic_wr;
wire pcr_rd;
wire pcr_wr;
wire [7:0] tid;
wire [7:0] asr_priv;
wire priv_ex;
wire pmu_op;
wire l1clk_pm4;
wire asi_scanin;
wire asi_scanout;
wire p_rd;
wire pc_rd;
wire pc_wr;
wire [31:0] pcr0_read;
wire [31:0] pcr1_read;
wire [31:0] pcr2_read;
wire [31:0] pcr3_read;
wire [31:0] pcr4_read;
wire [31:0] pcr5_read;
wire [31:0] pcr6_read;
wire [31:0] pcr7_read;
wire spares_scanin;
wire spares_scanout;


// *** globals ***
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input 		spc_aclk;
input 		spc_bclk;
input		tcu_scan_en;
output		scan_out;

// Power management for ASI ring...
input		lsu_asi_clken;
input		lsu_pmu_pmen;

// Instruction decode events
// if idle, then there is no pick, or other activity... valid would be off.
//input   [2:0]   lsu_pmu_tid_b;          // tid used by real lsu; for DC and DT misses
input	[12:0]	dec_pmu_instr0_type_d;	// {12 - valid; 11:10 - tid; 9:0 - {atomic_d, l2imiss, itmiss, icmiss, other, %sethi, store, load, FGU, branch}}
input	[12:0]	dec_pmu_instr1_type_d;
input	[1:0]	dec_br_taken_e;		// branch taken indicator
input	[5:0]	lsu_pmu_mem_type_b;	// {5:3 - tid (use for l2miss only); 2:0 - {l2 d-miss, dt_miss, d-cache miss}}
input		dec_lsu_sel0_d;		// select tg0 for lsu tid

// MMU activity (excluding ITLB/DTLB misses)
input 	        mmu_pmu_l2ret;          // indicates l2 data to MMU
input           mmu_pmu_l2miss;         // indicates the return pkt had l2 miss
input           mmu_pmu_dtlb;           // indicates that return pkt is for D-side table walk
input   [2:0]   mmu_pmu_tid;   		// thread id
//input	[5:0]	mmu_mtyp;		// {5 - valid; 4:2 - tid; 1 - D/~I; 0 - L2 hit/miss}

// Crossbar activity
//input	[9:0]	lsu_pmu_xbar_optype;	// {9 - valid; 8:6 - tid; 5:0 - {mmuld, cpustore, ifetch, cpuld, ststore, stload}}
input	[6:0]	l15_pmu_xbar_optype;	// {6 - valid; 5:3 - tid; 2:0 - {111 - mastore; 110 - maload; 101 - ifetch; 100 - mmuld; 011 - cwqstore; 010 - cwqload; 001 - cpustore; 000 - cpuld}}

// SPU activity
input	[4:0]	spu_pmu_cwq_busy;	// CWQ busy {rc4,hash,des,crc,aes}
input	[2:0]	spu_pmu_cwq_tid;
input	[3:0]	spu_pmu_ma_busy;

// state bits to decide when counters should record
input	[7:0] 	tlu_pmu_pstate_priv;	// pstate.priv for each thread (bit 7 == thread 7)
input	[7:0]	tlu_pmu_hpstate_hpriv;	// hpstate.hpriv (ditto)

// PMU trap is taken, reset the counter if "-"ve.
input   [7:0]   tlu_pmu_trap_taken;
input	[1:0]	tlu_pmu_trap_mask_e;	// True if TLU enabled for PMU trap {1 - tg1; 0 - tg0}

// Flush requests from TLU and IFU - bit 1 is for TG1, bit 0 for TG0
input	[1:0]	tlu_flush_pmu_b;	// kill what is in B now
input	[1:0]	tlu_flush_pmu_w;	// kill what is in W now

input   [1:0]	dec_valid_e;		// bit 1 is for TG1, 0 for TG0; instr valids in the e-stage

input	[1:0]	dec_flush_m;	// kill what is in M now
input	[1:0]	dec_flush_b;	// kill what is in B now

// Carry-out bits of incrementors to set OV bits in PCRs, valid in cycle W+1
input		pdp_pich_cout07;	
input		pdp_picl_cout07;		

// Near-overflow values (-16..-1) for each counter
input	[7:0]	pdp_pich_wrap;
input	[7:0]	pdp_picl_wrap;

// ASI read/write inputs
input		in_rngl_cdbus_ctl_ndata;// Bit 64 of input bus, register here
input	[7:0]   pdp_asi_ctlin_to_pctl_15_8;  // Bits 63:56 of registered data from PDP (save 8 flop bits)
input	[4:0]   pdp_asi_ctlin_to_pctl_4_0;   // Bits 52:48 of registered data from PDP (save 5 flop bits)
input	[31:0]	pdp_asi_din_to_pctl;	// control block needs lower 32 bits too for PCR data...

// Signals to tell TLU if we may/should trap due to counter overflow
output	[7:0]	pmu_tlu_trap_m;		// Sent at (near) beginning of M to TLU
output	[7:0]	pmu_tlu_debug_event;	// Tell trap if a perf. monitor event occurred to soft/hard stop/trigger on

// Event outputs
output	[3:0]	pct_pich07_add_w2;	// Add value for pich
output	[3:0]	pct_picl07_add_w2;	// Add value for picl

// Signals to LSU for trap on DCmiss, DTmiss, L2Dmiss
//input	[2:0]	dec_lsu_tid_e;		// TID of LSU instruction in E stage
output		pmu_lsu_dcmiss_trap_m;
output		pmu_lsu_dtmiss_trap_m;
output	[7:0]	pmu_lsu_l2dmiss_trap_m;

// ASI read controls
output   [7:0]	pct_rd_pic;		// ASI read of PIC (bit 7 == read PIC for tid 7)
output		pct_rd_a_pic;		// ASI read of any PIC
output		pct_rd_pic_pcr;         // ASI read of PIC or PCR (select PIC or PCR)
output		pct_bypass_asi;		// Flow this node's ASI data to the output
output	[31:0]	pct_pcr_data;		// PCR data on ASI read
output 		pct_rngl_cdbus_ctl_ndata; // Piped value of uppermost ASI ring ctl/data bus output
output		pct_exception;		// True if a privileged exception on ASR read or write to PIC or PCR

// ASI write controls
output	[7:0]	pct_wr_pic_w2;		// Write corresponding PICH/L from ASI (bit 7 == write PIC7)
output	[6:0]	pct_incr_pic_w1;	// increment PIC (PICL is enabled for counting) W+1 cycle, prior to adding in W+2
output		pct_incr_asi_w1;	// Select new ASI value to increment to deal with simultaneous ASI write and increment

// Clock gates to PICs in DP
output	[7:0]	pct_pic_clken;		// Only enable when pic configured to count
output		pct_pic07_w2_clken;	// Enable for pic_07 flop for ASI/PIC's selected to be added
 
// Pwr management for ASI ring in DP
output		pmu_asi_clken;
////////////////////////////////////////////////////////////////////////////////

// scan renames
assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
assign stop = 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se	= tcu_scan_en;
// end scan

pmu_pct_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk          	),
        .l1en   (1'b1			),
        .l1clk  (l1clk			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

// Flop ASI clken
pmu_pct_ctl_msff_ctl_macro__width_5 pwrm  (
	.scan_in(pwrm_scanin),
	.scan_out(pwrm_scanout),
	.l1clk	(l1clk),
	.din	({lsu_pmu_pmen, pmu_pmen, lsu_asi_clken, pmu_busy, skip_wakeup_in}),
	.dout	({pmu_pmen, pmu_pmen_del_1, pmu_asi_clken, pmu_busy_del_1, skip_wakeup}),
  .siclk(siclk),
  .soclk(soclk)
);

// Generally busy if any PCR is enabled to count in at least one mode
assign pmu_busy = (|pcr7_dout[3:1]) | (|pcr6_dout[3:1]) | (|pcr5_dout[3:1]) | (|pcr4_dout[3:1]) | 
                  (|pcr3_dout[3:1]) | (|pcr2_dout[3:1]) | (|pcr1_dout[3:1]) | (|pcr0_dout[3:1]);

// exposed a bug. The PMU was being power-managed, and when the last clock fired, counter 0
// was scheduled to be updated (in W2). However, while the PMU was powered-down, PIC0 was written to. Then,
// PCR0 was written to, waking up the PMU. Since PIC0 was being updated in W2 (from the stale PIC value in 
// pic07_w2 flop), it proceeded to overwrite the newly-written PIC value. To fix this the following was done.

// We record the fact that the PIC which will be updated upon wakeup has been
// written to in the interim, so the value in the W+2 add stage is incorrect. We then prevent the update 
// in that case, using the skip_wakeup flop.

assign skip_wakeup_in = ~wakeup & (skip_wakeup | 
                                   (~pmu_busy & pmu_pmen & (|({8 {p_wr}} & atid[7:0] & pic_std_w2[7:0])))
                                  );

assign wakeup = pmu_busy & ~pmu_busy_del_1;

// Sleep when: a) are power managed and pmu goes not busy, or b) pmu is not busy and we become power managed
assign sleep = (~pmu_busy & pmu_busy_del_1 & pmu_pmen) | (pmu_pmen & ~pmu_pmen_del_1 & ~pmu_busy);

// If events flop was stopped due to power management, then there is junk in it...we let the pipe drain
// to prevent spurious events on startup
// When sleep starts, let pipe drain...run for 13 cycles (== time from E->W2 + 7 cycles to account for 
// last possible update of a PIC due to the rotating counter. But we can subtract 1 since the counter is
// loaded 1 cycle after sleep.
pmu_pct_ctl_msff_ctl_macro__width_4 sleep_cnt  (
	.scan_in(sleep_cnt_scanin),
	.scan_out(sleep_cnt_scanout),
	.l1clk	(l1clk),
	.din	(sleep_cntr_din[3:0]),
	.dout	(sleep_cntr[3:0]),
  .siclk(siclk),
  .soclk(soclk) 
);

assign wait_for_sleep = |sleep_cntr[3:0];

assign sleep_cntr_din[3:0] = ({4 {sleep}} & 4'b1100) |
                             ({4 {~sleep & wait_for_sleep}} & (sleep_cntr[3:0] - 4'b0001));

// l1clk_pm1 = pmu_busy_l1clk...

assign l1b = pmu_busy | sleep | wait_for_sleep | ~pmu_pmen;

pmu_pct_ctl_l1clkhdr_ctl_macro pmu_busy_clkgen (
        .l2clk  (l2clk          	),
        .l1en   (l1b	),
        .l1clk  (l1clk_pm1		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

// power manage OV bits; enable during ASI write to PCR, or when any flop is recording
assign ov_busy = |wr_pcr[7:0] | (|rd_pcr[7:0]) | pmu_busy | sleep | wait_for_sleep;

pmu_pct_ctl_l1clkhdr_ctl_macro ov_busy_clkgen (
        .l2clk  (l2clk          	),
        .l1en   (ov_busy | ~pmu_pmen	),
//        .l1clk  (ov_busy_l1clk		)
        .l1clk  (l1clk_pm2		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

// register state input bits
// these bits are used to 1) check for priv exceptions due to read/writes of pic or pcr, as well as qualifying counting events
// simplest thing is to keep running all the time (was l1clk_pm1 but 
// this broke priv exception check since asi ring busy not included (bug 86773))
// attempt to use pmu_busy | asi_clken (PMU is not first on ASI ring)
// Change to keep busy all the time...not ideal, but need this clock to save pwr for pcr's
//l1clkhdr_ctl_macro priv_busy_clkgen (
//        .l2clk  (l2clk          	),
//        .l1en   (pmu_busy | pmu_asi_clken | ~pmu_pmen	),
//        .l1clk  (priv_busy_l1clk		)
//        .l1clk  (l1clk_pm3		)
//);

pmu_pct_ctl_msff_ctl_macro__width_16 hpstate  (
//	.l1clk	(priv_busy_l1clk),
	.scan_in(hpstate_scanin),
	.scan_out(hpstate_scanout),
	.l1clk	(l1clk),
	.din	({tlu_pmu_hpstate_hpriv[7:0], tlu_pmu_pstate_priv[7:0]}),
	.dout	({hpriv[7:0], priv[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// register event inputs
// Make sure only one of the CWQ events is active at a time...
// 0in bits_on -var (spu_pmu_cwq_busy[4:0]) -message "spu_pmu_cwq_busy[4:0] not mutex"

assign mmu_mtyp[5:0] = {mmu_pmu_l2ret, mmu_pmu_tid[2:0], mmu_pmu_dtlb, mmu_pmu_l2miss};

// delay rc4, hash, des, crc, aes, ma_busy 1 clock to avoid timing problem  - edge-detect 
// from flopped version - costs 6 flops
pmu_pct_ctl_msff_ctl_macro__width_66 events  (
	.scan_in(events_scanin),
	.scan_out(events_scanout),
	.l1clk	(l1clk_pm1),
	.din	({dec_pmu_instr0_type_d[12:0], dec_pmu_instr1_type_d[12:0], 
                  dec_br_taken_e[1:0], mmu_mtyp[5:0],
                  lsu_pmu_mem_type_b[5:0], l15_pmu_xbar_optype[6:0], spu_pmu_cwq_busy[4:0],
                  spu_pmu_cwq_tid[2:0], spu_pmu_ma_busy[3:0], rc4, hash, des, crc, aes, ma[3], dec_lsu_sel0_d}),
	.dout	({tg0_e[12:0], tg1_e[12:0], 
                  dec_br_taken_m[1:0], mm_mtyp[5:0],
                  mem_typ_w[5:0], xbar[6:0], rc4, hash, des, crc, aes, 
                  spu_tid[2:0], ma[3:0], rc4_d1, hash_d1, des_d1, crc_d1, aes_d1, ma_3_d1, dec_lsu_sel0_e}),
  .siclk(siclk),
  .soclk(soclk)
);

assign tg0_ityp_e[11:0] = {12 {tg0_e[12]}} & tg0_e[11:0];
assign tg1_ityp_e[11:0] = {12 {tg1_e[12]}} & tg1_e[11:0];

// Use dec signal for below
assign lsu_tid_e[2:0] = {~dec_lsu_sel0_e, ({2 { dec_lsu_sel0_e}} & tg0_ityp_e[11:10]) |
                                          ({2 {~dec_lsu_sel0_e}} & tg1_ityp_e[11:10]) };

pmu_pct_ctl_msff_ctl_macro__width_9 lsutid  (
	.scan_in(lsutid_scanin),
	.scan_out(lsutid_scanout),
	.l1clk	(l1clk_pm1),
	.din	({lsu_tid_e[2:0], lsu_tid_m[2:0], lsu_tid_b[2:0]}),
	.dout	({lsu_tid_m[2:0], lsu_tid_b[2:0], lsu_tid_w[2:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Decode the events

assign all_idle_e = ~tg0_e[12] & ~tg1_e[12];

// What thread is instruction event for
//             11:10 - tid;            
assign th[0] = ~tg0_ityp_e[11] & ~tg0_ityp_e[10];
assign th[1] = ~tg0_ityp_e[11] &  tg0_ityp_e[10];
assign th[2] =  tg0_ityp_e[11] & ~tg0_ityp_e[10];
assign th[3] =  tg0_ityp_e[11] &  tg0_ityp_e[10];
assign th[4] = ~tg1_ityp_e[11] & ~tg1_ityp_e[10];
assign th[5] = ~tg1_ityp_e[11] &  tg1_ityp_e[10];
assign th[6] =  tg1_ityp_e[11] & ~tg1_ityp_e[10];
assign th[7] =  tg1_ityp_e[11] &  tg1_ityp_e[10];

// DES/3DES busy event
// 3 - busy/idle; 2:0 - tid;
assign cwq_tid[0] = ~spu_tid[2] & ~spu_tid[1] & ~spu_tid[0];
assign cwq_tid[1] = ~spu_tid[2] & ~spu_tid[1] &  spu_tid[0];
assign cwq_tid[2] = ~spu_tid[2] &  spu_tid[1] & ~spu_tid[0];
assign cwq_tid[3] = ~spu_tid[2] &  spu_tid[1] &  spu_tid[0];
assign cwq_tid[4] =  spu_tid[2] & ~spu_tid[1] & ~spu_tid[0];
assign cwq_tid[5] =  spu_tid[2] & ~spu_tid[1] &  spu_tid[0];
assign cwq_tid[6] =  spu_tid[2] &  spu_tid[1] & ~spu_tid[0];
assign cwq_tid[7] =  spu_tid[2] &  spu_tid[1] &  spu_tid[0];

assign desb[7:0] = {8 {des}} & cwq_tid[7:0];

// AES busy event
assign aesb[7:0] = {8 {aes}} & cwq_tid[7:0];

// RC4 busy event
assign rc4b[7:0] = {8 {rc4}} & cwq_tid[7:0];

// SHA-1/SHA-256/MD5 busy event
assign hashb[7:0] = {8 {hash}} & cwq_tid[7:0];

// CRC busy event
assign crcb[7:0] = {8 {crc}} & cwq_tid[7:0];

// MA busy event
assign ma_tid[0] = ~ma[2] & ~ma[1] & ~ma[0];
assign ma_tid[1] = ~ma[2] & ~ma[1] &  ma[0];
assign ma_tid[2] = ~ma[2] &  ma[1] & ~ma[0];
assign ma_tid[3] = ~ma[2] &  ma[1] &  ma[0];
assign ma_tid[4] =  ma[2] & ~ma[1] & ~ma[0];
assign ma_tid[5] =  ma[2] & ~ma[1] &  ma[0];
assign ma_tid[6] =  ma[2] &  ma[1] & ~ma[0];
assign ma_tid[7] =  ma[2] &  ma[1] &  ma[0];

assign mab[7:0] = {8 {ma[3]}} & ma_tid[7:0];

// register spu_ops to detect edges
// Fundamentally, only need to detect edges on ma[3], des, aes, rc4, crc, hash individually except
// iff the TID can change from one cycle to the next any busy bit stays high...
// CWQ can't do this - put in assertions to make sure
// MA can't do this by design
// 0in assert -var ~(|(spu_pmu_cwq_busy[4:0] & {rc4,hash,des,crc,aes}) & (spu_pmu_cwq_tid[2:0] != spu_tid[2:0]) & l1clk_pm1) -message "spu_pmu_cwq_busy[4:0] busy but spu_pmu_cwq_tid[2:0] changes"

// dcmiss, dtmiss, l2miss from lsu in previous cycle
assign dcm[0] = ~lsu_tid_w[2] & ~lsu_tid_w[1] & ~lsu_tid_w[0] & mem_typ_w[0];
assign dcm[1] = ~lsu_tid_w[2] & ~lsu_tid_w[1] &  lsu_tid_w[0] & mem_typ_w[0];
assign dcm[2] = ~lsu_tid_w[2] &  lsu_tid_w[1] & ~lsu_tid_w[0] & mem_typ_w[0];
assign dcm[3] = ~lsu_tid_w[2] &  lsu_tid_w[1] &  lsu_tid_w[0] & mem_typ_w[0];
assign dcm[4] =  lsu_tid_w[2] & ~lsu_tid_w[1] & ~lsu_tid_w[0] & mem_typ_w[0];
assign dcm[5] =  lsu_tid_w[2] & ~lsu_tid_w[1] &  lsu_tid_w[0] & mem_typ_w[0];
assign dcm[6] =  lsu_tid_w[2] &  lsu_tid_w[1] & ~lsu_tid_w[0] & mem_typ_w[0];
assign dcm[7] =  lsu_tid_w[2] &  lsu_tid_w[1] &  lsu_tid_w[0] & mem_typ_w[0];

assign dtm[0] = ~lsu_tid_w[2] & ~lsu_tid_w[1] & ~lsu_tid_w[0] & mem_typ_w[1];
assign dtm[1] = ~lsu_tid_w[2] & ~lsu_tid_w[1] &  lsu_tid_w[0] & mem_typ_w[1];
assign dtm[2] = ~lsu_tid_w[2] &  lsu_tid_w[1] & ~lsu_tid_w[0] & mem_typ_w[1];
assign dtm[3] = ~lsu_tid_w[2] &  lsu_tid_w[1] &  lsu_tid_w[0] & mem_typ_w[1];
assign dtm[4] =  lsu_tid_w[2] & ~lsu_tid_w[1] & ~lsu_tid_w[0] & mem_typ_w[1];
assign dtm[5] =  lsu_tid_w[2] & ~lsu_tid_w[1] &  lsu_tid_w[0] & mem_typ_w[1];
assign dtm[6] =  lsu_tid_w[2] &  lsu_tid_w[1] & ~lsu_tid_w[0] & mem_typ_w[1];
assign dtm[7] =  lsu_tid_w[2] &  lsu_tid_w[1] &  lsu_tid_w[0] & mem_typ_w[1];

//              5:3 - tid;	    2:0 - {l2 d-miss, dt_miss, d-cache miss}
assign l2m[0] = ~mem_typ_w[5] & ~mem_typ_w[4] & ~mem_typ_w[3] & mem_typ_w[2];
assign l2m[1] = ~mem_typ_w[5] & ~mem_typ_w[4] &  mem_typ_w[3] & mem_typ_w[2];
assign l2m[2] = ~mem_typ_w[5] &  mem_typ_w[4] & ~mem_typ_w[3] & mem_typ_w[2];
assign l2m[3] = ~mem_typ_w[5] &  mem_typ_w[4] &  mem_typ_w[3] & mem_typ_w[2];
assign l2m[4] =  mem_typ_w[5] & ~mem_typ_w[4] & ~mem_typ_w[3] & mem_typ_w[2];
assign l2m[5] =  mem_typ_w[5] & ~mem_typ_w[4] &  mem_typ_w[3] & mem_typ_w[2];
assign l2m[6] =  mem_typ_w[5] &  mem_typ_w[4] & ~mem_typ_w[3] & mem_typ_w[2];
assign l2m[7] =  mem_typ_w[5] &  mem_typ_w[4] &  mem_typ_w[3] & mem_typ_w[2];

// NEED to HANDLE the potential of a Dmiss and a L2Dmiss at the same time

// PCR's for each thread
// PCR format is:
// 31    - OV1
// 30:27 - SL1
// 26:19 - Mask1
// 18    - OV0
// 17:14 - SL0
// 13:6  - Mask0
// 5:4   - TOE
// 3     - HT
// 2     - UT
// 1     - ST
// 0     - Priv 

// where each SL field decoding is:
// 0 - all idle (async)
// 1 - unused
// 2 - instruction group (sync)
// 3 - cache/tlb group (sync)
// 4 - unused
// 5 - xbar group (async)
// 6 - spu ops (async) -- ops derived from spu busy
// 7 - spu busy (async)

// generate OV bits for all PCR's
assign ov1[7:0] = {8 {pdp_pich_cout07}} & {pic_std_w2[7:0]} | set_ovh_spec[7:0];
assign ov0[7:0] = {8 {pdp_picl_cout07}} & {pic_std_w2[7:0]} | set_ovl_spec[7:0];

// generate clk enables for all PICs; keep it simple for now (enable only when a PIC is configured to count)
assign pct_pic_clken[7:0] = pct_wr_pic_w2[7:0] | (pic_std_w2[7:0] & ~{8 {skip_wakeup}} &
                            {|pcr7_dout[3:1],|pcr6_dout[3:1],|pcr5_dout[3:1],|pcr4_dout[3:1],
                             |pcr3_dout[3:1],|pcr2_dout[3:1],|pcr1_dout[3:1],|pcr0_dout[3:1]});

// writing to a PCR kills any pending OV updates

// PCR0

// In case of not writing to a PCR, keep the OV state.
// qualify the pcr0_din with ov1[0]; 
// Except! reset OV bits when PCR read...bug!

// Don't write to HT unless in hyperpriv mode...
assign ht_in[7:0] = ( hpriv[7:0] & {8 {pdp_asi_din_to_pctl[3]}}) |
                    (~hpriv[7:0] & {pcr7_dout[3], pcr6_dout[3], pcr5_dout[3], pcr4_dout[3],
                                    pcr3_dout[3], pcr2_dout[3], pcr1_dout[3], pcr0_dout[3]});

assign pcr0_din[29:0] = ({30 { wr_pcr[0]}} & {pdp_asi_din_to_pctl[30:19],pdp_asi_din_to_pctl[17:4],ht_in[0],pdp_asi_din_to_pctl[2:0]}) |
                        ({30 {~wr_pcr[0]}} & {disable_h[0],pcr0_dout[29:19],disable_l[0],pcr0_dout[16:0]});

// Now use one header to control write clocks for all pcr's - still need mux for individual flops
pmu_pct_ctl_l1clkhdr_ctl_macro wr_pcr_clkgen (
        .l2clk  (l2clk          ),
        .l1en   (|wr_pcr[7:0] 	),
        .l1clk  (l1clk_pm3	),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

pmu_pct_ctl_msff_ctl_macro__width_30 pcr0  (
	.scan_in(pcr0_scanin),
	.scan_out(pcr0_scanout),
	.l1clk	(l1clk_pm3),
	.din	(pcr0_din[29:0]),
	.dout	({disable_h[0],pcr0_dout[29:19],disable_l[0],pcr0_dout[16:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
assign pcr0_dout[30] = 1'b0;
assign pcr0_dout[17] = 1'b0;

// For selective write to OV:
// Write OV0 iff bit 62 not set - use negative active to keep compatibility with pre-existing DV tests
// Write OV1 iff bit 63 not set - use negative active to keep compatibility with pre-existing DV tests

assign bit63 = pdp_asi_ctlin_to_pctl_15_8[7]; // bit 63 of ring data cycle
assign bit62 = pdp_asi_ctlin_to_pctl_15_8[6]; // bit 62 of ring data cycle

assign x0[1:0] = ( ({2 {wr_pcr[0]}} & {~bit63,~bit62}) & {pdp_asi_din_to_pctl[31], pdp_asi_din_to_pctl[18]}) |
                 (~({2 {wr_pcr[0]}} & {~bit63,~bit62}) & {(ov1[0] | pcr0_dout[31]), (ov0[0] | pcr0_dout[18])});

pmu_pct_ctl_msff_ctl_macro__width_2 pcr0_ov  (
	.scan_in(pcr0_ov_scanin),
	.scan_out(pcr0_ov_scanout),
	.l1clk	(l1clk_pm2),
	.din	(x0[1:0]),
	.dout	({pcr0_dout[31],pcr0_dout[18]}),
  .siclk(siclk),
  .soclk(soclk)
);

// PCR1
assign pcr1_din[29:0] = ({30 { wr_pcr[1]}} & {pdp_asi_din_to_pctl[30:19],pdp_asi_din_to_pctl[17:4],ht_in[1],pdp_asi_din_to_pctl[2:0]}) |
                        ({30 {~wr_pcr[1]}} & {disable_h[1],pcr1_dout[29:19],disable_l[1],pcr1_dout[16:0]});

pmu_pct_ctl_msff_ctl_macro__width_30 pcr1  (
	.scan_in(pcr1_scanin),
	.scan_out(pcr1_scanout),
	.l1clk	(l1clk_pm3),
	.din	(pcr1_din[29:0]),
	.dout	({disable_h[1],pcr1_dout[29:19],disable_l[1],pcr1_dout[16:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
assign pcr1_dout[30] = 1'b0;
assign pcr1_dout[17] = 1'b0;

assign x1[1:0] = ( ({2 {wr_pcr[1]}} & {~bit63,~bit62}) & {pdp_asi_din_to_pctl[31], pdp_asi_din_to_pctl[18]}) |
                 (~({2 {wr_pcr[1]}} & {~bit63,~bit62}) & {(ov1[1] | pcr1_dout[31]), (ov0[1] | pcr1_dout[18])});

pmu_pct_ctl_msff_ctl_macro__width_2 pcr1_ov  (
	.scan_in(pcr1_ov_scanin),
	.scan_out(pcr1_ov_scanout),
	.l1clk	(l1clk_pm2),
	.din	(x1[1:0]),
	.dout	({pcr1_dout[31],pcr1_dout[18]}),
  .siclk(siclk),
  .soclk(soclk)
);

// PCR2
assign pcr2_din[29:0] = ({30 { wr_pcr[2]}} & {pdp_asi_din_to_pctl[30:19],pdp_asi_din_to_pctl[17:4],ht_in[2],pdp_asi_din_to_pctl[2:0]}) |
                        ({30 {~wr_pcr[2]}} & {disable_h[2],pcr2_dout[29:19],disable_l[2],pcr2_dout[16:0]});

pmu_pct_ctl_msff_ctl_macro__width_30 pcr2  (
	.scan_in(pcr2_scanin),
	.scan_out(pcr2_scanout),
	.l1clk	(l1clk_pm3),
	.din	(pcr2_din[29:0]),
	.dout	({disable_h[2],pcr2_dout[29:19],disable_l[2],pcr2_dout[16:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
assign pcr2_dout[30] = 1'b0;
assign pcr2_dout[17] = 1'b0;

assign x2[1:0] = ( ({2 {wr_pcr[2]}} & {~bit63,~bit62}) & {pdp_asi_din_to_pctl[31], pdp_asi_din_to_pctl[18]}) |
                 (~({2 {wr_pcr[2]}} & {~bit63,~bit62}) & {(ov1[2] | pcr2_dout[31]), (ov0[2] | pcr2_dout[18])});

pmu_pct_ctl_msff_ctl_macro__width_2 pcr2_ov  (
	.scan_in(pcr2_ov_scanin),
	.scan_out(pcr2_ov_scanout),
	.l1clk	(l1clk_pm2),
	.din	(x2[1:0]),
	.dout	({pcr2_dout[31],pcr2_dout[18]}),
  .siclk(siclk),
  .soclk(soclk)
);

// PCR3
assign pcr3_din[29:0] = ({30 { wr_pcr[3]}} & {pdp_asi_din_to_pctl[30:19],pdp_asi_din_to_pctl[17:4],ht_in[3],pdp_asi_din_to_pctl[2:0]}) |
                        ({30 {~wr_pcr[3]}} & {disable_h[3],pcr3_dout[29:19],disable_l[3],pcr3_dout[16:0]});

pmu_pct_ctl_msff_ctl_macro__width_30 pcr3  (
	.scan_in(pcr3_scanin),
	.scan_out(pcr3_scanout),
	.l1clk	(l1clk_pm3),
	.din	(pcr3_din[29:0]),
	.dout	({disable_h[3],pcr3_dout[29:19],disable_l[3],pcr3_dout[16:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
assign pcr3_dout[30] = 1'b0;
assign pcr3_dout[17] = 1'b0;

assign x3[1:0] = ( ({2 {wr_pcr[3]}} & {~bit63,~bit62}) & {pdp_asi_din_to_pctl[31], pdp_asi_din_to_pctl[18]}) |
                 (~({2 {wr_pcr[3]}} & {~bit63,~bit62}) & {(ov1[3] | pcr3_dout[31]), (ov0[3] | pcr3_dout[18])});

pmu_pct_ctl_msff_ctl_macro__width_2 pcr3_ov  (
	.scan_in(pcr3_ov_scanin),
	.scan_out(pcr3_ov_scanout),
	.l1clk	(l1clk_pm2),
	.din	(x3[1:0]),
	.dout	({pcr3_dout[31],pcr3_dout[18]}),
  .siclk(siclk),
  .soclk(soclk)
);

// PCR4
assign pcr4_din[29:0] = ({30 { wr_pcr[4]}} & {pdp_asi_din_to_pctl[30:19],pdp_asi_din_to_pctl[17:4],ht_in[4],pdp_asi_din_to_pctl[2:0]}) |
                        ({30 {~wr_pcr[4]}} & {disable_h[4],pcr4_dout[29:19],disable_l[4],pcr4_dout[16:0]});

pmu_pct_ctl_msff_ctl_macro__width_30 pcr4  (
	.scan_in(pcr4_scanin),
	.scan_out(pcr4_scanout),
	.l1clk	(l1clk_pm3),
	.din	(pcr4_din[29:0]),
	.dout	({disable_h[4],pcr4_dout[29:19],disable_l[4],pcr4_dout[16:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
assign pcr4_dout[30] = 1'b0;
assign pcr4_dout[17] = 1'b0;

assign x4[1:0] = ( ({2 {wr_pcr[4]}} & {~bit63,~bit62}) & {pdp_asi_din_to_pctl[31], pdp_asi_din_to_pctl[18]}) |
                 (~({2 {wr_pcr[4]}} & {~bit63,~bit62}) & {(ov1[4] | pcr4_dout[31]), (ov0[4] | pcr4_dout[18])});

pmu_pct_ctl_msff_ctl_macro__width_2 pcr4_ov  (
	.scan_in(pcr4_ov_scanin),
	.scan_out(pcr4_ov_scanout),
	.l1clk	(l1clk_pm2),
	.din	(x4[1:0]),
	.dout	({pcr4_dout[31],pcr4_dout[18]}),
  .siclk(siclk),
  .soclk(soclk)
);

// PCR5
assign pcr5_din[29:0] = ({30 { wr_pcr[5]}} & {pdp_asi_din_to_pctl[30:19],pdp_asi_din_to_pctl[17:4],ht_in[5],pdp_asi_din_to_pctl[2:0]}) |
                        ({30 {~wr_pcr[5]}} & {disable_h[5],pcr5_dout[29:19],disable_l[5],pcr5_dout[16:0]});

pmu_pct_ctl_msff_ctl_macro__width_30 pcr5  (
	.scan_in(pcr5_scanin),
	.scan_out(pcr5_scanout),
	.l1clk	(l1clk_pm3),
	.din	(pcr5_din[29:0]),
	.dout	({disable_h[5],pcr5_dout[29:19],disable_l[5],pcr5_dout[16:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
assign pcr5_dout[30] = 1'b0;
assign pcr5_dout[17] = 1'b0;

assign x5[1:0] = ( ({2 {wr_pcr[5]}} & {~bit63,~bit62}) & {pdp_asi_din_to_pctl[31], pdp_asi_din_to_pctl[18]}) |
                 (~({2 {wr_pcr[5]}} & {~bit63,~bit62}) & {(ov1[5] | pcr5_dout[31]), (ov0[5] | pcr5_dout[18])});

pmu_pct_ctl_msff_ctl_macro__width_2 pcr5_ov  (
	.scan_in(pcr5_ov_scanin),
	.scan_out(pcr5_ov_scanout),
	.l1clk	(l1clk_pm2),
	.din	(x5[1:0]),
	.dout	({pcr5_dout[31],pcr5_dout[18]}),
  .siclk(siclk),
  .soclk(soclk)
);

// PCR6
assign pcr6_din[29:0] = ({30 { wr_pcr[6]}} & {pdp_asi_din_to_pctl[30:19],pdp_asi_din_to_pctl[17:4],ht_in[6],pdp_asi_din_to_pctl[2:0]}) |
                        ({30 {~wr_pcr[6]}} & {disable_h[6],pcr6_dout[29:19],disable_l[6],pcr6_dout[16:0]});

pmu_pct_ctl_msff_ctl_macro__width_30 pcr6  (
	.scan_in(pcr6_scanin),
	.scan_out(pcr6_scanout),
	.l1clk	(l1clk_pm3),
	.din	(pcr6_din[29:0]),
	.dout	({disable_h[6],pcr6_dout[29:19],disable_l[6],pcr6_dout[16:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
assign pcr6_dout[30] = 1'b0;
assign pcr6_dout[17] = 1'b0;

assign x6[1:0] = ( ({2 {wr_pcr[6]}} & {~bit63,~bit62}) & {pdp_asi_din_to_pctl[31], pdp_asi_din_to_pctl[18]}) |
                 (~({2 {wr_pcr[6]}} & {~bit63,~bit62}) & {(ov1[6] | pcr6_dout[31]), (ov0[6] | pcr6_dout[18])});

pmu_pct_ctl_msff_ctl_macro__width_2 pcr6_ov  (
	.scan_in(pcr6_ov_scanin),
	.scan_out(pcr6_ov_scanout),
	.l1clk	(l1clk_pm2),
	.din	(x6[1:0]),
	.dout	({pcr6_dout[31],pcr6_dout[18]}),
  .siclk(siclk),
  .soclk(soclk)
);

// PCR7
assign pcr7_din[29:0] = ({30 { wr_pcr[7]}} & {pdp_asi_din_to_pctl[30:19],pdp_asi_din_to_pctl[17:4],ht_in[7],pdp_asi_din_to_pctl[2:0]}) |
                        ({30 {~wr_pcr[7]}} & {disable_h[7],pcr7_dout[29:19],disable_l[7],pcr7_dout[16:0]});

pmu_pct_ctl_msff_ctl_macro__width_30 pcr7  (
	.scan_in(pcr7_scanin),
	.scan_out(pcr7_scanout),
	.l1clk	(l1clk_pm3),
	.din	(pcr7_din[29:0]),
	.dout	({disable_h[7],pcr7_dout[29:19],disable_l[7],pcr7_dout[16:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
assign pcr7_dout[30] = 1'b0;
assign pcr7_dout[17] = 1'b0;

assign x7[1:0] = ( ({2 {wr_pcr[7]}} & {~bit63,~bit62}) & {pdp_asi_din_to_pctl[31], pdp_asi_din_to_pctl[18]}) |
                 (~({2 {wr_pcr[7]}} & {~bit63,~bit62}) & {(ov1[7] | pcr7_dout[31]), (ov0[7] | pcr7_dout[18])});

pmu_pct_ctl_msff_ctl_macro__width_2 pcr7_ov  (
	.scan_in(pcr7_ov_scanin),
	.scan_out(pcr7_ov_scanout),
	.l1clk	(l1clk_pm2),
	.din	(x7[1:0]),
	.dout	({pcr7_dout[31],pcr7_dout[18]}),
  .siclk(siclk),
  .soclk(soclk)
);

// can't power manage x*_1 signals, otherwise can't do edge detect - need free running l1clk

pmu_pct_ctl_msff_ctl_macro__width_16 pcr_ov_del  (
	.scan_in(pcr_ov_del_scanin),
	.scan_out(pcr_ov_del_scanout),
	.l1clk	(l1clk),
	.din	({pcr7_dout[31],pcr7_dout[18],pcr6_dout[31],pcr6_dout[18],pcr5_dout[31],pcr5_dout[18],pcr4_dout[31],pcr4_dout[18],
                  pcr3_dout[31],pcr3_dout[18],pcr2_dout[31],pcr2_dout[18],pcr1_dout[31],pcr1_dout[18],pcr0_dout[31],pcr0_dout[18]}),
	.dout	({x7_1[1:0],x6_1[1:0],x5_1[1:0],x4_1[1:0],x3_1[1:0],x2_1[1:0],x1_1[1:0],x0_1[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Count only if in correct state (HT, UT, ST)
assign p_cnt_en[0] = (pcr0_dout[3] & hpriv[0]) | (pcr0_dout[1] & ~hpriv[0] & priv[0]) | (pcr0_dout[2] & ~hpriv[0] & ~priv[0]);
assign p_cnt_en[1] = (pcr1_dout[3] & hpriv[1]) | (pcr1_dout[1] & ~hpriv[1] & priv[1]) | (pcr1_dout[2] & ~hpriv[1] & ~priv[1]);
assign p_cnt_en[2] = (pcr2_dout[3] & hpriv[2]) | (pcr2_dout[1] & ~hpriv[2] & priv[2]) | (pcr2_dout[2] & ~hpriv[2] & ~priv[2]);
assign p_cnt_en[3] = (pcr3_dout[3] & hpriv[3]) | (pcr3_dout[1] & ~hpriv[3] & priv[3]) | (pcr3_dout[2] & ~hpriv[3] & ~priv[3]);
assign p_cnt_en[4] = (pcr4_dout[3] & hpriv[4]) | (pcr4_dout[1] & ~hpriv[4] & priv[4]) | (pcr4_dout[2] & ~hpriv[4] & ~priv[4]);
assign p_cnt_en[5] = (pcr5_dout[3] & hpriv[5]) | (pcr5_dout[1] & ~hpriv[5] & priv[5]) | (pcr5_dout[2] & ~hpriv[5] & ~priv[5]);
assign p_cnt_en[6] = (pcr6_dout[3] & hpriv[6]) | (pcr6_dout[1] & ~hpriv[6] & priv[6]) | (pcr6_dout[2] & ~hpriv[6] & ~priv[6]);
assign p_cnt_en[7] = (pcr7_dout[3] & hpriv[7]) | (pcr7_dout[1] & ~hpriv[7] & priv[7]) | (pcr7_dout[2] & ~hpriv[7] & ~priv[7]);

// Decode upper counter events

// SL[3:0] = 4'b0000
assign ph_all_idle[0]= ~|pcr0_dout[30:27] & p_cnt_en[0]; 
assign ph_all_idle[1]= ~|pcr1_dout[30:27] & p_cnt_en[1]; 
assign ph_all_idle[2]= ~|pcr2_dout[30:27] & p_cnt_en[2]; 
assign ph_all_idle[3]= ~|pcr3_dout[30:27] & p_cnt_en[3]; 
assign ph_all_idle[4]= ~|pcr4_dout[30:27] & p_cnt_en[4]; 
assign ph_all_idle[5]= ~|pcr5_dout[30:27] & p_cnt_en[5]; 
assign ph_all_idle[6]= ~|pcr6_dout[30:27] & p_cnt_en[6]; 
assign ph_all_idle[7]= ~|pcr7_dout[30:27] & p_cnt_en[7]; 

// SL[3:0] = 4'b0010 - instruction events
assign ph_ig[0] = ~pcr0_dout[30] & ~pcr0_dout[29] &  pcr0_dout[28] & ~pcr0_dout[27] & p_cnt_en[0];
assign ph_ig[1] = ~pcr1_dout[30] & ~pcr1_dout[29] &  pcr1_dout[28] & ~pcr1_dout[27] & p_cnt_en[1];
assign ph_ig[2] = ~pcr2_dout[30] & ~pcr2_dout[29] &  pcr2_dout[28] & ~pcr2_dout[27] & p_cnt_en[2];
assign ph_ig[3] = ~pcr3_dout[30] & ~pcr3_dout[29] &  pcr3_dout[28] & ~pcr3_dout[27] & p_cnt_en[3];
assign ph_ig[4] = ~pcr4_dout[30] & ~pcr4_dout[29] &  pcr4_dout[28] & ~pcr4_dout[27] & p_cnt_en[4];
assign ph_ig[5] = ~pcr5_dout[30] & ~pcr5_dout[29] &  pcr5_dout[28] & ~pcr5_dout[27] & p_cnt_en[5];
assign ph_ig[6] = ~pcr6_dout[30] & ~pcr6_dout[29] &  pcr6_dout[28] & ~pcr6_dout[27] & p_cnt_en[6];
assign ph_ig[7] = ~pcr7_dout[30] & ~pcr7_dout[29] &  pcr7_dout[28] & ~pcr7_dout[27] & p_cnt_en[7];

// SL[3:0] = 4'b0011 - cache events
assign ph_cg[0] = ~pcr0_dout[30] & ~pcr0_dout[29] &  pcr0_dout[28] &  pcr0_dout[27] & p_cnt_en[0];
assign ph_cg[1] = ~pcr1_dout[30] & ~pcr1_dout[29] &  pcr1_dout[28] &  pcr1_dout[27] & p_cnt_en[1];
assign ph_cg[2] = ~pcr2_dout[30] & ~pcr2_dout[29] &  pcr2_dout[28] &  pcr2_dout[27] & p_cnt_en[2];
assign ph_cg[3] = ~pcr3_dout[30] & ~pcr3_dout[29] &  pcr3_dout[28] &  pcr3_dout[27] & p_cnt_en[3];
assign ph_cg[4] = ~pcr4_dout[30] & ~pcr4_dout[29] &  pcr4_dout[28] &  pcr4_dout[27] & p_cnt_en[4];
assign ph_cg[5] = ~pcr5_dout[30] & ~pcr5_dout[29] &  pcr5_dout[28] &  pcr5_dout[27] & p_cnt_en[5];
assign ph_cg[6] = ~pcr6_dout[30] & ~pcr6_dout[29] &  pcr6_dout[28] &  pcr6_dout[27] & p_cnt_en[6];
assign ph_cg[7] = ~pcr7_dout[30] & ~pcr7_dout[29] &  pcr7_dout[28] &  pcr7_dout[27] & p_cnt_en[7];

// SL[3:0] = 4'b0100 - L2 mmu events
assign ph_mm[0] = ~pcr0_dout[30] &  pcr0_dout[29] & ~pcr0_dout[28] & ~pcr0_dout[27] & p_cnt_en[0];
assign ph_mm[1] = ~pcr1_dout[30] &  pcr1_dout[29] & ~pcr1_dout[28] & ~pcr1_dout[27] & p_cnt_en[1];
assign ph_mm[2] = ~pcr2_dout[30] &  pcr2_dout[29] & ~pcr2_dout[28] & ~pcr2_dout[27] & p_cnt_en[2];
assign ph_mm[3] = ~pcr3_dout[30] &  pcr3_dout[29] & ~pcr3_dout[28] & ~pcr3_dout[27] & p_cnt_en[3];
assign ph_mm[4] = ~pcr4_dout[30] &  pcr4_dout[29] & ~pcr4_dout[28] & ~pcr4_dout[27] & p_cnt_en[4];
assign ph_mm[5] = ~pcr5_dout[30] &  pcr5_dout[29] & ~pcr5_dout[28] & ~pcr5_dout[27] & p_cnt_en[5];
assign ph_mm[6] = ~pcr6_dout[30] &  pcr6_dout[29] & ~pcr6_dout[28] & ~pcr6_dout[27] & p_cnt_en[6];
assign ph_mm[7] = ~pcr7_dout[30] &  pcr7_dout[29] & ~pcr7_dout[28] & ~pcr7_dout[27] & p_cnt_en[7];

// SL[3:0] = 4'b0101 - crossbar events
assign ph_xb[0] = ~pcr0_dout[30] &  pcr0_dout[29] & ~pcr0_dout[28] &  pcr0_dout[27] & p_cnt_en[0];
assign ph_xb[1] = ~pcr1_dout[30] &  pcr1_dout[29] & ~pcr1_dout[28] &  pcr1_dout[27] & p_cnt_en[1];
assign ph_xb[2] = ~pcr2_dout[30] &  pcr2_dout[29] & ~pcr2_dout[28] &  pcr2_dout[27] & p_cnt_en[2];
assign ph_xb[3] = ~pcr3_dout[30] &  pcr3_dout[29] & ~pcr3_dout[28] &  pcr3_dout[27] & p_cnt_en[3];
assign ph_xb[4] = ~pcr4_dout[30] &  pcr4_dout[29] & ~pcr4_dout[28] &  pcr4_dout[27] & p_cnt_en[4];
assign ph_xb[5] = ~pcr5_dout[30] &  pcr5_dout[29] & ~pcr5_dout[28] &  pcr5_dout[27] & p_cnt_en[5];
assign ph_xb[6] = ~pcr6_dout[30] &  pcr6_dout[29] & ~pcr6_dout[28] &  pcr6_dout[27] & p_cnt_en[6];
assign ph_xb[7] = ~pcr7_dout[30] &  pcr7_dout[29] & ~pcr7_dout[28] &  pcr7_dout[27] & p_cnt_en[7];

// SL[3:0] = 4'b0110 - spu operation events
assign ph_so[0] = ~pcr0_dout[30] &  pcr0_dout[29] &  pcr0_dout[28] & ~pcr0_dout[27] & p_cnt_en[0];
assign ph_so[1] = ~pcr1_dout[30] &  pcr1_dout[29] &  pcr1_dout[28] & ~pcr1_dout[27] & p_cnt_en[1];
assign ph_so[2] = ~pcr2_dout[30] &  pcr2_dout[29] &  pcr2_dout[28] & ~pcr2_dout[27] & p_cnt_en[2];
assign ph_so[3] = ~pcr3_dout[30] &  pcr3_dout[29] &  pcr3_dout[28] & ~pcr3_dout[27] & p_cnt_en[3];
assign ph_so[4] = ~pcr4_dout[30] &  pcr4_dout[29] &  pcr4_dout[28] & ~pcr4_dout[27] & p_cnt_en[4];
assign ph_so[5] = ~pcr5_dout[30] &  pcr5_dout[29] &  pcr5_dout[28] & ~pcr5_dout[27] & p_cnt_en[5];
assign ph_so[6] = ~pcr6_dout[30] &  pcr6_dout[29] &  pcr6_dout[28] & ~pcr6_dout[27] & p_cnt_en[6];
assign ph_so[7] = ~pcr7_dout[30] &  pcr7_dout[29] &  pcr7_dout[28] & ~pcr7_dout[27] & p_cnt_en[7];

// SL[3:0] = 4'b0111 - spu busy cycles
assign ph_sb[0] = ~pcr0_dout[30] &  pcr0_dout[29] &  pcr0_dout[28] &  pcr0_dout[27] & p_cnt_en[0];
assign ph_sb[1] = ~pcr1_dout[30] &  pcr1_dout[29] &  pcr1_dout[28] &  pcr1_dout[27] & p_cnt_en[1];
assign ph_sb[2] = ~pcr2_dout[30] &  pcr2_dout[29] &  pcr2_dout[28] &  pcr2_dout[27] & p_cnt_en[2];
assign ph_sb[3] = ~pcr3_dout[30] &  pcr3_dout[29] &  pcr3_dout[28] &  pcr3_dout[27] & p_cnt_en[3];
assign ph_sb[4] = ~pcr4_dout[30] &  pcr4_dout[29] &  pcr4_dout[28] &  pcr4_dout[27] & p_cnt_en[4];
assign ph_sb[5] = ~pcr5_dout[30] &  pcr5_dout[29] &  pcr5_dout[28] &  pcr5_dout[27] & p_cnt_en[5];
assign ph_sb[6] = ~pcr6_dout[30] &  pcr6_dout[29] &  pcr6_dout[28] &  pcr6_dout[27] & p_cnt_en[6];
assign ph_sb[7] = ~pcr7_dout[30] &  pcr7_dout[29] &  pcr7_dout[28] &  pcr7_dout[27] & p_cnt_en[7];

// Decode lower counter events

// SL[3:0] = 4'b0000
assign pl_all_idle[0] = ~|pcr0_dout[17:14] & p_cnt_en[0]; 
assign pl_all_idle[1] = ~|pcr1_dout[17:14] & p_cnt_en[1]; 
assign pl_all_idle[2] = ~|pcr2_dout[17:14] & p_cnt_en[2]; 
assign pl_all_idle[3] = ~|pcr3_dout[17:14] & p_cnt_en[3]; 
assign pl_all_idle[4] = ~|pcr4_dout[17:14] & p_cnt_en[4]; 
assign pl_all_idle[5] = ~|pcr5_dout[17:14] & p_cnt_en[5]; 
assign pl_all_idle[6] = ~|pcr6_dout[17:14] & p_cnt_en[6]; 
assign pl_all_idle[7] = ~|pcr7_dout[17:14] & p_cnt_en[7]; 

// SL[3:0] = 4'b0010 - instruction events
assign pl_ig[0] = ~pcr0_dout[17] & ~pcr0_dout[16] &  pcr0_dout[15] & ~pcr0_dout[14] & p_cnt_en[0];
assign pl_ig[1] = ~pcr1_dout[17] & ~pcr1_dout[16] &  pcr1_dout[15] & ~pcr1_dout[14] & p_cnt_en[1];
assign pl_ig[2] = ~pcr2_dout[17] & ~pcr2_dout[16] &  pcr2_dout[15] & ~pcr2_dout[14] & p_cnt_en[2];
assign pl_ig[3] = ~pcr3_dout[17] & ~pcr3_dout[16] &  pcr3_dout[15] & ~pcr3_dout[14] & p_cnt_en[3];
assign pl_ig[4] = ~pcr4_dout[17] & ~pcr4_dout[16] &  pcr4_dout[15] & ~pcr4_dout[14] & p_cnt_en[4];
assign pl_ig[5] = ~pcr5_dout[17] & ~pcr5_dout[16] &  pcr5_dout[15] & ~pcr5_dout[14] & p_cnt_en[5];
assign pl_ig[6] = ~pcr6_dout[17] & ~pcr6_dout[16] &  pcr6_dout[15] & ~pcr6_dout[14] & p_cnt_en[6];
assign pl_ig[7] = ~pcr7_dout[17] & ~pcr7_dout[16] &  pcr7_dout[15] & ~pcr7_dout[14] & p_cnt_en[7];

// SL[3:0] = 4'b0011 - cache events
assign pl_cg[0] = ~pcr0_dout[17] & ~pcr0_dout[16] &  pcr0_dout[15] &  pcr0_dout[14] & p_cnt_en[0];
assign pl_cg[1] = ~pcr1_dout[17] & ~pcr1_dout[16] &  pcr1_dout[15] &  pcr1_dout[14] & p_cnt_en[1];
assign pl_cg[2] = ~pcr2_dout[17] & ~pcr2_dout[16] &  pcr2_dout[15] &  pcr2_dout[14] & p_cnt_en[2];
assign pl_cg[3] = ~pcr3_dout[17] & ~pcr3_dout[16] &  pcr3_dout[15] &  pcr3_dout[14] & p_cnt_en[3];
assign pl_cg[4] = ~pcr4_dout[17] & ~pcr4_dout[16] &  pcr4_dout[15] &  pcr4_dout[14] & p_cnt_en[4];
assign pl_cg[5] = ~pcr5_dout[17] & ~pcr5_dout[16] &  pcr5_dout[15] &  pcr5_dout[14] & p_cnt_en[5];
assign pl_cg[6] = ~pcr6_dout[17] & ~pcr6_dout[16] &  pcr6_dout[15] &  pcr6_dout[14] & p_cnt_en[6];
assign pl_cg[7] = ~pcr7_dout[17] & ~pcr7_dout[16] &  pcr7_dout[15] &  pcr7_dout[14] & p_cnt_en[7];

// SL[3:0] = 4'b0100 - L2 mmu events
assign pl_mm[0] = ~pcr0_dout[17] &  pcr0_dout[16] & ~pcr0_dout[15] & ~pcr0_dout[14] & p_cnt_en[0];
assign pl_mm[1] = ~pcr1_dout[17] &  pcr1_dout[16] & ~pcr1_dout[15] & ~pcr1_dout[14] & p_cnt_en[1];
assign pl_mm[2] = ~pcr2_dout[17] &  pcr2_dout[16] & ~pcr2_dout[15] & ~pcr2_dout[14] & p_cnt_en[2];
assign pl_mm[3] = ~pcr3_dout[17] &  pcr3_dout[16] & ~pcr3_dout[15] & ~pcr3_dout[14] & p_cnt_en[3];
assign pl_mm[4] = ~pcr4_dout[17] &  pcr4_dout[16] & ~pcr4_dout[15] & ~pcr4_dout[14] & p_cnt_en[4];
assign pl_mm[5] = ~pcr5_dout[17] &  pcr5_dout[16] & ~pcr5_dout[15] & ~pcr5_dout[14] & p_cnt_en[5];
assign pl_mm[6] = ~pcr6_dout[17] &  pcr6_dout[16] & ~pcr6_dout[15] & ~pcr6_dout[14] & p_cnt_en[6];
assign pl_mm[7] = ~pcr7_dout[17] &  pcr7_dout[16] & ~pcr7_dout[15] & ~pcr7_dout[14] & p_cnt_en[7];

// SL[3:0] = 4'b0101 - crossbar events
assign pl_xb[0] = ~pcr0_dout[17] &  pcr0_dout[16] & ~pcr0_dout[15] &  pcr0_dout[14] & p_cnt_en[0];
assign pl_xb[1] = ~pcr1_dout[17] &  pcr1_dout[16] & ~pcr1_dout[15] &  pcr1_dout[14] & p_cnt_en[1];
assign pl_xb[2] = ~pcr2_dout[17] &  pcr2_dout[16] & ~pcr2_dout[15] &  pcr2_dout[14] & p_cnt_en[2];
assign pl_xb[3] = ~pcr3_dout[17] &  pcr3_dout[16] & ~pcr3_dout[15] &  pcr3_dout[14] & p_cnt_en[3];
assign pl_xb[4] = ~pcr4_dout[17] &  pcr4_dout[16] & ~pcr4_dout[15] &  pcr4_dout[14] & p_cnt_en[4];
assign pl_xb[5] = ~pcr5_dout[17] &  pcr5_dout[16] & ~pcr5_dout[15] &  pcr5_dout[14] & p_cnt_en[5];
assign pl_xb[6] = ~pcr6_dout[17] &  pcr6_dout[16] & ~pcr6_dout[15] &  pcr6_dout[14] & p_cnt_en[6];
assign pl_xb[7] = ~pcr7_dout[17] &  pcr7_dout[16] & ~pcr7_dout[15] &  pcr7_dout[14] & p_cnt_en[7];

// SL[3:0] = 4'b0110 - spu operation events
assign pl_so[0] = ~pcr0_dout[17] &  pcr0_dout[16] &  pcr0_dout[15] & ~pcr0_dout[14] & p_cnt_en[0];
assign pl_so[1] = ~pcr1_dout[17] &  pcr1_dout[16] &  pcr1_dout[15] & ~pcr1_dout[14] & p_cnt_en[1];
assign pl_so[2] = ~pcr2_dout[17] &  pcr2_dout[16] &  pcr2_dout[15] & ~pcr2_dout[14] & p_cnt_en[2];
assign pl_so[3] = ~pcr3_dout[17] &  pcr3_dout[16] &  pcr3_dout[15] & ~pcr3_dout[14] & p_cnt_en[3];
assign pl_so[4] = ~pcr4_dout[17] &  pcr4_dout[16] &  pcr4_dout[15] & ~pcr4_dout[14] & p_cnt_en[4];
assign pl_so[5] = ~pcr5_dout[17] &  pcr5_dout[16] &  pcr5_dout[15] & ~pcr5_dout[14] & p_cnt_en[5];
assign pl_so[6] = ~pcr6_dout[17] &  pcr6_dout[16] &  pcr6_dout[15] & ~pcr6_dout[14] & p_cnt_en[6];
assign pl_so[7] = ~pcr7_dout[17] &  pcr7_dout[16] &  pcr7_dout[15] & ~pcr7_dout[14] & p_cnt_en[7];

// SL[3:0] = 4'b0111 - spu busy events
assign pl_sb[0] = ~pcr0_dout[17] &  pcr0_dout[16] &  pcr0_dout[15] &  pcr0_dout[14] & p_cnt_en[0];
assign pl_sb[1] = ~pcr1_dout[17] &  pcr1_dout[16] &  pcr1_dout[15] &  pcr1_dout[14] & p_cnt_en[1];
assign pl_sb[2] = ~pcr2_dout[17] &  pcr2_dout[16] &  pcr2_dout[15] &  pcr2_dout[14] & p_cnt_en[2];
assign pl_sb[3] = ~pcr3_dout[17] &  pcr3_dout[16] &  pcr3_dout[15] &  pcr3_dout[14] & p_cnt_en[3];
assign pl_sb[4] = ~pcr4_dout[17] &  pcr4_dout[16] &  pcr4_dout[15] &  pcr4_dout[14] & p_cnt_en[4];
assign pl_sb[5] = ~pcr5_dout[17] &  pcr5_dout[16] &  pcr5_dout[15] &  pcr5_dout[14] & p_cnt_en[5];
assign pl_sb[6] = ~pcr6_dout[17] &  pcr6_dout[16] &  pcr6_dout[15] &  pcr6_dout[14] & p_cnt_en[6];
assign pl_sb[7] = ~pcr7_dout[17] &  pcr7_dout[16] &  pcr7_dout[15] &  pcr7_dout[14] & p_cnt_en[7];

// Generate outputs to let LSU know if we are about to trap on a dcache/dt/l2d/store miss
// pdp_pich_wrap need to be qualified with pct_wr_pic_w2? (e.g. PIC gets overwritten with a near overflow value and cause trap?)
// Must use flopped wrap signals to avoid a timing path now that PMU is at the upper left and LSU at lower right...
// New design - take TID of what is in LSU in E from DEC; mux down PMU signals internally; send 1 bit to LSU for 
// each one of dcmiss & icmiss trap indicator; still send 8 bits for L2miss since there is no equivalent TID.

assign dcm_h[7:0] = ph_cg[7:0] & {pcr7_dout[20], pcr6_dout[20], pcr5_dout[20], pcr4_dout[20],
                                  pcr3_dout[20], pcr2_dout[20], pcr1_dout[20], pcr0_dout[20]};

assign dcm_l[7:0] = pl_cg[7:0] & {pcr7_dout[ 7], pcr6_dout[7], pcr5_dout[7], pcr4_dout[7],
                                  pcr3_dout[7], pcr2_dout[7], pcr1_dout[7], pcr0_dout[7]};

assign pmu_lsu_dcmiss_trap_e[7:0] = (dcm_h[7:0] & pich_wrap[7:0]) | (dcm_l & picl_wrap[7:0]);

// Decode TID from DEC
assign t[0] = ~lsu_tid_e[2] & ~lsu_tid_e[1] & ~lsu_tid_e[0];
assign t[1] = ~lsu_tid_e[2] & ~lsu_tid_e[1] &  lsu_tid_e[0];
assign t[2] = ~lsu_tid_e[2] &  lsu_tid_e[1] & ~lsu_tid_e[0];
assign t[3] = ~lsu_tid_e[2] &  lsu_tid_e[1] &  lsu_tid_e[0];
assign t[4] =  lsu_tid_e[2] & ~lsu_tid_e[1] & ~lsu_tid_e[0];
assign t[5] =  lsu_tid_e[2] & ~lsu_tid_e[1] &  lsu_tid_e[0];
assign t[6] =  lsu_tid_e[2] &  lsu_tid_e[1] & ~lsu_tid_e[0];
assign t[7] =  lsu_tid_e[2] &  lsu_tid_e[1] &  lsu_tid_e[0];

assign pmu_lsu_dcm_trap_e = |(t[7:0] & pmu_lsu_dcmiss_trap_e[7:0] & { {4 {tlu_pmu_trap_mask_e[1]}}, {4 {tlu_pmu_trap_mask_e[0]}} });

assign dtm_h[7:0] = ph_cg[7:0] & {pcr7_dout[22], pcr6_dout[22], pcr5_dout[22], pcr4_dout[22],
                                  pcr3_dout[22], pcr2_dout[22], pcr1_dout[22], pcr0_dout[22]};

assign dtm_l[7:0] = pl_cg[7:0] & {pcr7_dout[9], pcr6_dout[9], pcr5_dout[9], pcr4_dout[9],
                                  pcr3_dout[9], pcr2_dout[9], pcr1_dout[9], pcr0_dout[9]};

assign pmu_lsu_dtmiss_trap_e[7:0] = (dtm_h[7:0] & pich_wrap[7:0]) | (dtm_l & picl_wrap[7:0]);

assign pmu_lsu_dtm_trap_e = |(t[7:0] & pmu_lsu_dtmiss_trap_e[7:0] & { {4 {tlu_pmu_trap_mask_e[1]}}, {4 {tlu_pmu_trap_mask_e[0]}} });

assign l2dm_h[7:0] = ph_cg[7:0] & {pcr7_dout[24], pcr6_dout[24], pcr5_dout[24], pcr4_dout[24],
                                   pcr3_dout[24], pcr2_dout[24], pcr1_dout[24], pcr0_dout[24]};

assign l2dm_l[7:0] = pl_cg[7:0] & {pcr7_dout[11], pcr6_dout[11], pcr5_dout[11], pcr4_dout[11],
                                   pcr3_dout[11], pcr2_dout[11], pcr1_dout[11], pcr0_dout[11]};

// Need to do L2 misses on an individual TID basis, as out-of-pipe!
//assign pmu_lsu_l2dmiss_trap_e[7:0] = ((l2dm_h[7:0] & pich_wrap[7:0]) | (l2dm_l & picl_wrap[7:0])) & { {4 {tlu_pmu_trap_mask_e[1]}}, {4 {tlu_pmu_trap_mask_e[0]}} };

// Must accumulate current value of trap mask for all threads; update when valid tid in E
// TLU gives PMU a trap mask per TG; must update trap mask based upon TID of each TG's instruction.
// Each cycle a valid instruction comes down the pipe, update the current value of the the lsu trap mask for that thread
// Flop to M, then compute for timing reasons (dec_valid_e late)

// Flop from E to M
pmu_pct_ctl_msff_ctl_macro__width_28 lsu_e2m  (
	.scan_in(lsu_e2m_scanin),
	.scan_out(lsu_e2m_scanout),
	.l1clk	(l1clk_pm1),
	.din	({pmu_lsu_dcm_trap_e, pmu_lsu_dtm_trap_e, l2dm_wrap_e[7:0], lsu_trap_mask_m_din[7:0], th[7:0], tlu_pmu_trap_mask_e[1:0]}),
	.dout	({pmu_lsu_dcmiss_trap_m, pmu_lsu_dtmiss_trap_m, l2dm_wrap_m[7:0], lsu_trap_mask_m[7:0], th_m[7:0], tlu_pmu_trap_mask_m[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// At most 2 bits should be on in this mask
// 0in bits_on -var (lsu_tidm_update_m[7:0]) -max 2 -message "Too many bits on in lsu_tidm_update_m[7:0]"
assign lsu_tidm_update_m[7:0] = {{4 {dec_valid_m[1]}}, {4 {dec_valid_m[0]}}} & th_m[7:0];

assign lsu_trap_mask_m_din[7:0] = ( ~lsu_tidm_update_m[7:0] & lsu_trap_mask_m[7:0]) |
                                  (  lsu_tidm_update_m[7:0] & {{4 {tlu_pmu_trap_mask_m[1]}}, {4 {tlu_pmu_trap_mask_m[0]}}});

assign l2dm_wrap_e[7:0] = (l2dm_h[7:0] & pich_wrap[7:0]) | (l2dm_l[7:0] & picl_wrap[7:0]);

assign pmu_lsu_l2dmiss_trap_m[7:0] = l2dm_wrap_m[7:0] & lsu_trap_mask_m_din[7:0];

// Generate increment values
// All idle
assign ph_ai[7:0] = ph_all_idle[7:0] & {8 {all_idle_e}};
assign pl_ai[7:0] = pl_all_idle[7:0] & {8 {all_idle_e}};

// Generate actual increment events (counter is configured and event occurs)

// First do instruction group events

// For SL[3:0] = 4'b0010... tg0_ityp_e[9:0]: atomic, l2i, it, ic, other, %sethi, store, load, FGU, branch
// 0x01, 0x02, 0x04, 0x08, 0x10 and 0x20

// taken branch event for TLU is done in M stage... th & dec_br_taken_e[1:0]

// High counters
assign ph_ige[0] = |({7 {ph_ig[0] & th[0]}} & {tg0_ityp_e[9], tg0_ityp_e[5:0]} & {pcr0_dout[26:21], pcr0_dout[19]});
assign ph_ige[1] = |({7 {ph_ig[1] & th[1]}} & {tg0_ityp_e[9], tg0_ityp_e[5:0]} & {pcr1_dout[26:21], pcr1_dout[19]});
assign ph_ige[2] = |({7 {ph_ig[2] & th[2]}} & {tg0_ityp_e[9], tg0_ityp_e[5:0]} & {pcr2_dout[26:21], pcr2_dout[19]});
assign ph_ige[3] = |({7 {ph_ig[3] & th[3]}} & {tg0_ityp_e[9], tg0_ityp_e[5:0]} & {pcr3_dout[26:21], pcr3_dout[19]});
assign ph_ige[4] = |({7 {ph_ig[4] & th[4]}} & {tg1_ityp_e[9], tg1_ityp_e[5:0]} & {pcr4_dout[26:21], pcr4_dout[19]});
assign ph_ige[5] = |({7 {ph_ig[5] & th[5]}} & {tg1_ityp_e[9], tg1_ityp_e[5:0]} & {pcr5_dout[26:21], pcr5_dout[19]});
assign ph_ige[6] = |({7 {ph_ig[6] & th[6]}} & {tg1_ityp_e[9], tg1_ityp_e[5:0]} & {pcr6_dout[26:21], pcr6_dout[19]});
assign ph_ige[7] = |({7 {ph_ig[7] & th[7]}} & {tg1_ityp_e[9], tg1_ityp_e[5:0]} & {pcr7_dout[26:21], pcr7_dout[19]});

// Low counters
assign pl_ige[0] = |({7 {pl_ig[0] & th[0]}} & {tg0_ityp_e[9], tg0_ityp_e[5:0]} & {pcr0_dout[13:8], pcr0_dout[6]});
assign pl_ige[1] = |({7 {pl_ig[1] & th[1]}} & {tg0_ityp_e[9], tg0_ityp_e[5:0]} & {pcr1_dout[13:8], pcr1_dout[6]});
assign pl_ige[2] = |({7 {pl_ig[2] & th[2]}} & {tg0_ityp_e[9], tg0_ityp_e[5:0]} & {pcr2_dout[13:8], pcr2_dout[6]});
assign pl_ige[3] = |({7 {pl_ig[3] & th[3]}} & {tg0_ityp_e[9], tg0_ityp_e[5:0]} & {pcr3_dout[13:8], pcr3_dout[6]});
assign pl_ige[4] = |({7 {pl_ig[4] & th[4]}} & {tg1_ityp_e[9], tg1_ityp_e[5:0]} & {pcr4_dout[13:8], pcr4_dout[6]});
assign pl_ige[5] = |({7 {pl_ig[5] & th[5]}} & {tg1_ityp_e[9], tg1_ityp_e[5:0]} & {pcr5_dout[13:8], pcr5_dout[6]});
assign pl_ige[6] = |({7 {pl_ig[6] & th[6]}} & {tg1_ityp_e[9], tg1_ityp_e[5:0]} & {pcr6_dout[13:8], pcr6_dout[6]});
assign pl_ige[7] = |({7 {pl_ig[7] & th[7]}} & {tg1_ityp_e[9], tg1_ityp_e[5:0]} & {pcr7_dout[13:8], pcr7_dout[6]});

// qualifier for dec_br_taken
assign ph_bre[0] = ph_ig[0] & th[0] & pcr0_dout[20];
assign ph_bre[1] = ph_ig[1] & th[1] & pcr1_dout[20];
assign ph_bre[2] = ph_ig[2] & th[2] & pcr2_dout[20];
assign ph_bre[3] = ph_ig[3] & th[3] & pcr3_dout[20];
assign ph_bre[4] = ph_ig[4] & th[4] & pcr4_dout[20];
assign ph_bre[5] = ph_ig[5] & th[5] & pcr5_dout[20];
assign ph_bre[6] = ph_ig[6] & th[6] & pcr6_dout[20];
assign ph_bre[7] = ph_ig[7] & th[7] & pcr7_dout[20];

assign pl_bre[0] = pl_ig[0] & th[0] & pcr0_dout[7];
assign pl_bre[1] = pl_ig[1] & th[1] & pcr1_dout[7];
assign pl_bre[2] = pl_ig[2] & th[2] & pcr2_dout[7];
assign pl_bre[3] = pl_ig[3] & th[3] & pcr3_dout[7];
assign pl_bre[4] = pl_ig[4] & th[4] & pcr4_dout[7];
assign pl_bre[5] = pl_ig[5] & th[5] & pcr5_dout[7];
assign pl_bre[6] = pl_ig[6] & th[6] & pcr6_dout[7];
assign pl_bre[7] = pl_ig[7] & th[7] & pcr7_dout[7];

// High and low counters for cache group events
// For SL[3:0] = 4'b0011...
// 0x02 
assign dcm_he[0] = ph_cg[0] & pcr0_dout[20] & dcm[0];
assign dcm_he[1] = ph_cg[1] & pcr1_dout[20] & dcm[1];
assign dcm_he[2] = ph_cg[2] & pcr2_dout[20] & dcm[2];
assign dcm_he[3] = ph_cg[3] & pcr3_dout[20] & dcm[3];
assign dcm_he[4] = ph_cg[4] & pcr4_dout[20] & dcm[4];
assign dcm_he[5] = ph_cg[5] & pcr5_dout[20] & dcm[5];
assign dcm_he[6] = ph_cg[6] & pcr6_dout[20] & dcm[6];
assign dcm_he[7] = ph_cg[7] & pcr7_dout[20] & dcm[7];

// 0x08
assign dtm_he[0] = ph_cg[0] & pcr0_dout[22] & dtm[0];
assign dtm_he[1] = ph_cg[1] & pcr1_dout[22] & dtm[1];
assign dtm_he[2] = ph_cg[2] & pcr2_dout[22] & dtm[2];
assign dtm_he[3] = ph_cg[3] & pcr3_dout[22] & dtm[3];
assign dtm_he[4] = ph_cg[4] & pcr4_dout[22] & dtm[4];
assign dtm_he[5] = ph_cg[5] & pcr5_dout[22] & dtm[5];
assign dtm_he[6] = ph_cg[6] & pcr6_dout[22] & dtm[6];
assign dtm_he[7] = ph_cg[7] & pcr7_dout[22] & dtm[7];

// 0x20
assign l2m_he[0] = ph_cg[0] & pcr0_dout[24] & l2m[0];
assign l2m_he[1] = ph_cg[1] & pcr1_dout[24] & l2m[1];
assign l2m_he[2] = ph_cg[2] & pcr2_dout[24] & l2m[2];
assign l2m_he[3] = ph_cg[3] & pcr3_dout[24] & l2m[3];
assign l2m_he[4] = ph_cg[4] & pcr4_dout[24] & l2m[4];
assign l2m_he[5] = ph_cg[5] & pcr5_dout[24] & l2m[5];
assign l2m_he[6] = ph_cg[6] & pcr6_dout[24] & l2m[6];
assign l2m_he[7] = ph_cg[7] & pcr7_dout[24] & l2m[7];

// 0x02 
assign dcm_le[0] = pl_cg[0] & pcr0_dout[7] & dcm[0];
assign dcm_le[1] = pl_cg[1] & pcr1_dout[7] & dcm[1];
assign dcm_le[2] = pl_cg[2] & pcr2_dout[7] & dcm[2];
assign dcm_le[3] = pl_cg[3] & pcr3_dout[7] & dcm[3];
assign dcm_le[4] = pl_cg[4] & pcr4_dout[7] & dcm[4];
assign dcm_le[5] = pl_cg[5] & pcr5_dout[7] & dcm[5];
assign dcm_le[6] = pl_cg[6] & pcr6_dout[7] & dcm[6];
assign dcm_le[7] = pl_cg[7] & pcr7_dout[7] & dcm[7];

// 0x08
assign dtm_le[0] = pl_cg[0] & pcr0_dout[9] & dtm[0];
assign dtm_le[1] = pl_cg[1] & pcr1_dout[9] & dtm[1];
assign dtm_le[2] = pl_cg[2] & pcr2_dout[9] & dtm[2];
assign dtm_le[3] = pl_cg[3] & pcr3_dout[9] & dtm[3];
assign dtm_le[4] = pl_cg[4] & pcr4_dout[9] & dtm[4];
assign dtm_le[5] = pl_cg[5] & pcr5_dout[9] & dtm[5];
assign dtm_le[6] = pl_cg[6] & pcr6_dout[9] & dtm[6];
assign dtm_le[7] = pl_cg[7] & pcr7_dout[9] & dtm[7];

// 0x20
assign l2m_le[0] = pl_cg[0] & pcr0_dout[11] & l2m[0];
assign l2m_le[1] = pl_cg[1] & pcr1_dout[11] & l2m[1];
assign l2m_le[2] = pl_cg[2] & pcr2_dout[11] & l2m[2];
assign l2m_le[3] = pl_cg[3] & pcr3_dout[11] & l2m[3];
assign l2m_le[4] = pl_cg[4] & pcr4_dout[11] & l2m[4];
assign l2m_le[5] = pl_cg[5] & pcr5_dout[11] & l2m[5];
assign l2m_le[6] = pl_cg[6] & pcr6_dout[11] & l2m[6];
assign l2m_le[7] = pl_cg[7] & pcr7_dout[11] & l2m[7];

// Split cache group events into I & D side misses, since they need to get piped in
// at different stages...
assign ph_icge[0] = |({3 {ph_cg[0] & th[0]}} & tg0_ityp_e[8:6] & {pcr0_dout[23],pcr0_dout[21],pcr0_dout[19]});   // l2i, it, ic miss
assign ph_icge[1] = |({3 {ph_cg[1] & th[1]}} & tg0_ityp_e[8:6] & {pcr1_dout[23],pcr1_dout[21],pcr1_dout[19]});   // l2i, it, ic miss
assign ph_icge[2] = |({3 {ph_cg[2] & th[2]}} & tg0_ityp_e[8:6] & {pcr2_dout[23],pcr2_dout[21],pcr2_dout[19]});   // l2i, it, ic miss
assign ph_icge[3] = |({3 {ph_cg[3] & th[3]}} & tg0_ityp_e[8:6] & {pcr3_dout[23],pcr3_dout[21],pcr3_dout[19]});   // l2i, it, ic miss
assign ph_icge[4] = |({3 {ph_cg[4] & th[4]}} & tg1_ityp_e[8:6] & {pcr4_dout[23],pcr4_dout[21],pcr4_dout[19]});   // l2i, it, ic miss
assign ph_icge[5] = |({3 {ph_cg[5] & th[5]}} & tg1_ityp_e[8:6] & {pcr5_dout[23],pcr5_dout[21],pcr5_dout[19]});   // l2i, it, ic miss
assign ph_icge[6] = |({3 {ph_cg[6] & th[6]}} & tg1_ityp_e[8:6] & {pcr6_dout[23],pcr6_dout[21],pcr6_dout[19]});   // l2i, it, ic miss
assign ph_icge[7] = |({3 {ph_cg[7] & th[7]}} & tg1_ityp_e[8:6] & {pcr7_dout[23],pcr7_dout[21],pcr7_dout[19]});   // l2i, it, ic miss

//assign ph_dcge[7:0] = dcm_he[7:0] | dtm_he[7:0] | l2m_he[7:0];

assign pl_icge[0] = |({3 {pl_cg[0] & th[0]}} & tg0_ityp_e[8:6] & {pcr0_dout[10],pcr0_dout[8],pcr0_dout[6]});   // l2i, it, ic miss
assign pl_icge[1] = |({3 {pl_cg[1] & th[1]}} & tg0_ityp_e[8:6] & {pcr1_dout[10],pcr1_dout[8],pcr1_dout[6]});   // l2i, it, ic miss
assign pl_icge[2] = |({3 {pl_cg[2] & th[2]}} & tg0_ityp_e[8:6] & {pcr2_dout[10],pcr2_dout[8],pcr2_dout[6]});   // l2i, it, ic miss
assign pl_icge[3] = |({3 {pl_cg[3] & th[3]}} & tg0_ityp_e[8:6] & {pcr3_dout[10],pcr3_dout[8],pcr3_dout[6]});   // l2i, it, ic miss
assign pl_icge[4] = |({3 {pl_cg[4] & th[4]}} & tg1_ityp_e[8:6] & {pcr4_dout[10],pcr4_dout[8],pcr4_dout[6]});   // l2i, it, ic miss
assign pl_icge[5] = |({3 {pl_cg[5] & th[5]}} & tg1_ityp_e[8:6] & {pcr5_dout[10],pcr5_dout[8],pcr5_dout[6]});   // l2i, it, ic miss
assign pl_icge[6] = |({3 {pl_cg[6] & th[6]}} & tg1_ityp_e[8:6] & {pcr6_dout[10],pcr6_dout[8],pcr6_dout[6]});   // l2i, it, ic miss
assign pl_icge[7] = |({3 {pl_cg[7] & th[7]}} & tg1_ityp_e[8:6] & {pcr7_dout[10],pcr7_dout[8],pcr7_dout[6]});   // l2i, it, ic miss

//assign pl_dcge[7:0] = dcm_le[7:0] | dtm_le[7:0] | l2m_le[7:0];

// High and low MMU events
// first decode MMU tid...
assign mm_tid[0] = ~mm_mtyp[4] & ~mm_mtyp[3] & ~mm_mtyp[2];
assign mm_tid[1] = ~mm_mtyp[4] & ~mm_mtyp[3] &  mm_mtyp[2];
assign mm_tid[2] = ~mm_mtyp[4] &  mm_mtyp[3] & ~mm_mtyp[2];
assign mm_tid[3] = ~mm_mtyp[4] &  mm_mtyp[3] &  mm_mtyp[2];
assign mm_tid[4] =  mm_mtyp[4] & ~mm_mtyp[3] & ~mm_mtyp[2];
assign mm_tid[5] =  mm_mtyp[4] & ~mm_mtyp[3] &  mm_mtyp[2];
assign mm_tid[6] =  mm_mtyp[4] &  mm_mtyp[3] & ~mm_mtyp[2];
assign mm_tid[7] =  mm_mtyp[4] &  mm_mtyp[3] &  mm_mtyp[2];

// Now decode what actually happened {l2dtm, l2itm, l2dtr, l2itr}
assign mm_l2e[3:0] = {4 {mm_mtyp[5]}} & 
                     {mm_mtyp[1] & mm_mtyp[0], ~mm_mtyp[1] &  mm_mtyp[0],  mm_mtyp[1], ~mm_mtyp[1]};

assign ph_mme[0] = ph_mm[0] & mm_tid[0] & |(mm_l2e[3:0] & pcr0_dout[24:21]);
assign ph_mme[1] = ph_mm[1] & mm_tid[1] & |(mm_l2e[3:0] & pcr1_dout[24:21]);
assign ph_mme[2] = ph_mm[2] & mm_tid[2] & |(mm_l2e[3:0] & pcr2_dout[24:21]);
assign ph_mme[3] = ph_mm[3] & mm_tid[3] & |(mm_l2e[3:0] & pcr3_dout[24:21]);
assign ph_mme[4] = ph_mm[4] & mm_tid[4] & |(mm_l2e[3:0] & pcr4_dout[24:21]);
assign ph_mme[5] = ph_mm[5] & mm_tid[5] & |(mm_l2e[3:0] & pcr5_dout[24:21]);
assign ph_mme[6] = ph_mm[6] & mm_tid[6] & |(mm_l2e[3:0] & pcr6_dout[24:21]);
assign ph_mme[7] = ph_mm[7] & mm_tid[7] & |(mm_l2e[3:0] & pcr7_dout[24:21]);

assign pl_mme[0] = pl_mm[0] & mm_tid[0] & |(mm_l2e[3:0] & pcr0_dout[11:8]);
assign pl_mme[1] = pl_mm[1] & mm_tid[1] & |(mm_l2e[3:0] & pcr1_dout[11:8]);
assign pl_mme[2] = pl_mm[2] & mm_tid[2] & |(mm_l2e[3:0] & pcr2_dout[11:8]);
assign pl_mme[3] = pl_mm[3] & mm_tid[3] & |(mm_l2e[3:0] & pcr3_dout[11:8]);
assign pl_mme[4] = pl_mm[4] & mm_tid[4] & |(mm_l2e[3:0] & pcr4_dout[11:8]);
assign pl_mme[5] = pl_mm[5] & mm_tid[5] & |(mm_l2e[3:0] & pcr5_dout[11:8]);
assign pl_mme[6] = pl_mm[6] & mm_tid[6] & |(mm_l2e[3:0] & pcr6_dout[11:8]);
assign pl_mme[7] = pl_mm[7] & mm_tid[7] & |(mm_l2e[3:0] & pcr7_dout[11:8]);

// High and low xbar events
//assign xb[7] =  xbar[2] &  xbar[1] &  xbar[0]; // ma st
//assign xb[6] =  xbar[2] &  xbar[1] & ~xbar[0]; // ma ld
assign xb[5] =  xbar[2] & ~xbar[1] & ~xbar[0]; // mmuld
assign xb[4] = ~xbar[2] & ~xbar[1] &  xbar[0]; // cpust
assign xb[3] =  xbar[2] & ~xbar[1] &  xbar[0]; // ifetch
assign xb[2] = ~xbar[2] & ~xbar[1] & ~xbar[0]; // cpuld
assign xb[1] = (~xbar[2] &  xbar[1] &  xbar[0]) | (xbar[2] & xbar[1] & xbar[0]); // cwq st or ma st
assign xb[0] = (~xbar[2] &  xbar[1] & ~xbar[0]) | (xbar[2] & xbar[1] & ~xbar[0]); // cwq ld or ma ld

// For stream lds/stores, must munge tid, as xbar tid not accurate

assign use_ma =  xbar[2] & xbar[1];
assign use_cwq = ~xbar[2] & xbar[1];

assign xbtid[2:0] = ({3 { use_ma}} & ma[2:0]) |
                    ({3 { use_cwq}} & spu_tid[2:0]) |
                    ({3 { ~use_ma & ~use_cwq}} & xbar[5:3]);

// SL[3:0] = 4'b0101
assign ph_xbe[0] = ph_xb[0] & xbar[6] & ~xbtid[2] & ~xbtid[1] & ~xbtid[0] & |(xb[5:0] & pcr0_dout[24:19]);
assign ph_xbe[1] = ph_xb[1] & xbar[6] & ~xbtid[2] & ~xbtid[1] &  xbtid[0] & |(xb[5:0] & pcr1_dout[24:19]);
assign ph_xbe[2] = ph_xb[2] & xbar[6] & ~xbtid[2] &  xbtid[1] & ~xbtid[0] & |(xb[5:0] & pcr2_dout[24:19]);
assign ph_xbe[3] = ph_xb[3] & xbar[6] & ~xbtid[2] &  xbtid[1] &  xbtid[0] & |(xb[5:0] & pcr3_dout[24:19]);
assign ph_xbe[4] = ph_xb[4] & xbar[6] &  xbtid[2] & ~xbtid[1] & ~xbtid[0] & |(xb[5:0] & pcr4_dout[24:19]);
assign ph_xbe[5] = ph_xb[5] & xbar[6] &  xbtid[2] & ~xbtid[1] &  xbtid[0] & |(xb[5:0] & pcr5_dout[24:19]);
assign ph_xbe[6] = ph_xb[6] & xbar[6] &  xbtid[2] &  xbtid[1] & ~xbtid[0] & |(xb[5:0] & pcr6_dout[24:19]);
assign ph_xbe[7] = ph_xb[7] & xbar[6] &  xbtid[2] &  xbtid[1] &  xbtid[0] & |(xb[5:0] & pcr7_dout[24:19]);

assign pl_xbe[0] = pl_xb[0] & xbar[6] & ~xbtid[2] & ~xbtid[1] & ~xbtid[0] & |(xb[5:0] & pcr0_dout[11:6]);
assign pl_xbe[1] = pl_xb[1] & xbar[6] & ~xbtid[2] & ~xbtid[1] &  xbtid[0] & |(xb[5:0] & pcr1_dout[11:6]);
assign pl_xbe[2] = pl_xb[2] & xbar[6] & ~xbtid[2] &  xbtid[1] & ~xbtid[0] & |(xb[5:0] & pcr2_dout[11:6]);
assign pl_xbe[3] = pl_xb[3] & xbar[6] & ~xbtid[2] &  xbtid[1] &  xbtid[0] & |(xb[5:0] & pcr3_dout[11:6]);
assign pl_xbe[4] = pl_xb[4] & xbar[6] &  xbtid[2] & ~xbtid[1] & ~xbtid[0] & |(xb[5:0] & pcr4_dout[11:6]);
assign pl_xbe[5] = pl_xb[5] & xbar[6] &  xbtid[2] & ~xbtid[1] &  xbtid[0] & |(xb[5:0] & pcr5_dout[11:6]);
assign pl_xbe[6] = pl_xb[6] & xbar[6] &  xbtid[2] &  xbtid[1] & ~xbtid[0] & |(xb[5:0] & pcr6_dout[11:6]);
assign pl_xbe[7] = pl_xb[7] & xbar[6] &  xbtid[2] &  xbtid[1] &  xbtid[0] & |(xb[5:0] & pcr7_dout[11:6]);

// High and low SPU ops

// SL[3:0] = 4'b0110
// increment spu_op only when the current des/aes/rc4/hash/ma/crc is busy and was not the previous cycle.
assign spu_des[7:0] = {8 {des & ~des_d1}} & cwq_tid[7:0];
assign spu_aes[7:0] = {8 {aes & ~aes_d1}} & cwq_tid[7:0];
assign spu_rc4[7:0] = {8 {rc4 & ~rc4_d1}} & cwq_tid[7:0];
assign spu_hash[7:0] = {8 {hash & ~hash_d1}} & cwq_tid[7:0];
assign spu_ma[7:0] = {8 {ma[3] & ~ma_3_d1}} & ma_tid[7:0];
assign spu_crc[7:0] = {8 {crc & ~crc_d1}} & cwq_tid[7:0];

assign ph_soe[0] = ph_so[0] & |({spu_crc[0], spu_ma[0], spu_hash[0], spu_rc4[0], spu_aes[0], spu_des[0]} & pcr0_dout[24:19]);
assign ph_soe[1] = ph_so[1] & |({spu_crc[1], spu_ma[1], spu_hash[1], spu_rc4[1], spu_aes[1], spu_des[1]} & pcr1_dout[24:19]);
assign ph_soe[2] = ph_so[2] & |({spu_crc[2], spu_ma[2], spu_hash[2], spu_rc4[2], spu_aes[2], spu_des[2]} & pcr2_dout[24:19]);
assign ph_soe[3] = ph_so[3] & |({spu_crc[3], spu_ma[3], spu_hash[3], spu_rc4[3], spu_aes[3], spu_des[3]} & pcr3_dout[24:19]);
assign ph_soe[4] = ph_so[4] & |({spu_crc[4], spu_ma[4], spu_hash[4], spu_rc4[4], spu_aes[4], spu_des[4]} & pcr4_dout[24:19]);
assign ph_soe[5] = ph_so[5] & |({spu_crc[5], spu_ma[5], spu_hash[5], spu_rc4[5], spu_aes[5], spu_des[5]} & pcr5_dout[24:19]);
assign ph_soe[6] = ph_so[6] & |({spu_crc[6], spu_ma[6], spu_hash[6], spu_rc4[6], spu_aes[6], spu_des[6]} & pcr6_dout[24:19]);
assign ph_soe[7] = ph_so[7] & |({spu_crc[7], spu_ma[7], spu_hash[7], spu_rc4[7], spu_aes[7], spu_des[7]} & pcr7_dout[24:19]);

assign pl_soe[0] = pl_so[0] & |({spu_crc[0], spu_ma[0], spu_hash[0], spu_rc4[0], spu_aes[0], spu_des[0]} & pcr0_dout[11:6]);
assign pl_soe[1] = pl_so[1] & |({spu_crc[1], spu_ma[1], spu_hash[1], spu_rc4[1], spu_aes[1], spu_des[1]} & pcr1_dout[11:6]);
assign pl_soe[2] = pl_so[2] & |({spu_crc[2], spu_ma[2], spu_hash[2], spu_rc4[2], spu_aes[2], spu_des[2]} & pcr2_dout[11:6]);
assign pl_soe[3] = pl_so[3] & |({spu_crc[3], spu_ma[3], spu_hash[3], spu_rc4[3], spu_aes[3], spu_des[3]} & pcr3_dout[11:6]);
assign pl_soe[4] = pl_so[4] & |({spu_crc[4], spu_ma[4], spu_hash[4], spu_rc4[4], spu_aes[4], spu_des[4]} & pcr4_dout[11:6]);
assign pl_soe[5] = pl_so[5] & |({spu_crc[5], spu_ma[5], spu_hash[5], spu_rc4[5], spu_aes[5], spu_des[5]} & pcr5_dout[11:6]);
assign pl_soe[6] = pl_so[6] & |({spu_crc[6], spu_ma[6], spu_hash[6], spu_rc4[6], spu_aes[6], spu_des[6]} & pcr6_dout[11:6]);
assign pl_soe[7] = pl_so[7] & |({spu_crc[7], spu_ma[7], spu_hash[7], spu_rc4[7], spu_aes[7], spu_des[7]} & pcr7_dout[11:6]);

// High and low SPU busy cycles
// SL[3:0] = 4'b0111
assign ph_sbe[0] = ph_sb[0] & |({crcb[0], mab[0], hashb[0], rc4b[0], aesb[0], desb[0]} & pcr0_dout[24:19]);
assign ph_sbe[1] = ph_sb[1] & |({crcb[1], mab[1], hashb[1], rc4b[1], aesb[1], desb[1]} & pcr1_dout[24:19]);
assign ph_sbe[2] = ph_sb[2] & |({crcb[2], mab[2], hashb[2], rc4b[2], aesb[2], desb[2]} & pcr2_dout[24:19]);
assign ph_sbe[3] = ph_sb[3] & |({crcb[3], mab[3], hashb[3], rc4b[3], aesb[3], desb[3]} & pcr3_dout[24:19]);
assign ph_sbe[4] = ph_sb[4] & |({crcb[4], mab[4], hashb[4], rc4b[4], aesb[4], desb[4]} & pcr4_dout[24:19]);
assign ph_sbe[5] = ph_sb[5] & |({crcb[5], mab[5], hashb[5], rc4b[5], aesb[5], desb[5]} & pcr5_dout[24:19]);
assign ph_sbe[6] = ph_sb[6] & |({crcb[6], mab[6], hashb[6], rc4b[6], aesb[6], desb[6]} & pcr6_dout[24:19]);
assign ph_sbe[7] = ph_sb[7] & |({crcb[7], mab[7], hashb[7], rc4b[7], aesb[7], desb[7]} & pcr7_dout[24:19]);

assign pl_sbe[0] = pl_sb[0] & |({crcb[0], mab[0], hashb[0], rc4b[0], aesb[0], desb[0]} & pcr0_dout[11:6]);
assign pl_sbe[1] = pl_sb[1] & |({crcb[1], mab[1], hashb[1], rc4b[1], aesb[1], desb[1]} & pcr1_dout[11:6]);
assign pl_sbe[2] = pl_sb[2] & |({crcb[2], mab[2], hashb[2], rc4b[2], aesb[2], desb[2]} & pcr2_dout[11:6]);
assign pl_sbe[3] = pl_sb[3] & |({crcb[3], mab[3], hashb[3], rc4b[3], aesb[3], desb[3]} & pcr3_dout[11:6]);
assign pl_sbe[4] = pl_sb[4] & |({crcb[4], mab[4], hashb[4], rc4b[4], aesb[4], desb[4]} & pcr4_dout[11:6]);
assign pl_sbe[5] = pl_sb[5] & |({crcb[5], mab[5], hashb[5], rc4b[5], aesb[5], desb[5]} & pcr5_dout[11:6]);
assign pl_sbe[6] = pl_sb[6] & |({crcb[6], mab[6], hashb[6], rc4b[6], aesb[6], desb[6]} & pcr6_dout[11:6]);
assign pl_sbe[7] = pl_sb[7] & |({crcb[7], mab[7], hashb[7], rc4b[7], aesb[7], desb[7]} & pcr7_dout[11:6]);

// qualify wrap with whether we should trap 
assign pich_wrap[0] = pdp_pich_wrap[0] & pcr0_dout[5];
assign pich_wrap[1] = pdp_pich_wrap[1] & pcr1_dout[5];
assign pich_wrap[2] = pdp_pich_wrap[2] & pcr2_dout[5];
assign pich_wrap[3] = pdp_pich_wrap[3] & pcr3_dout[5];
assign pich_wrap[4] = pdp_pich_wrap[4] & pcr4_dout[5];
assign pich_wrap[5] = pdp_pich_wrap[5] & pcr5_dout[5];
assign pich_wrap[6] = pdp_pich_wrap[6] & pcr6_dout[5];
assign pich_wrap[7] = pdp_pich_wrap[7] & pcr7_dout[5];

assign picl_wrap[0] = pdp_picl_wrap[0] & pcr0_dout[4];
assign picl_wrap[1] = pdp_picl_wrap[1] & pcr1_dout[4];
assign picl_wrap[2] = pdp_picl_wrap[2] & pcr2_dout[4];
assign picl_wrap[3] = pdp_picl_wrap[3] & pcr3_dout[4];
assign picl_wrap[4] = pdp_picl_wrap[4] & pcr4_dout[4];
assign picl_wrap[5] = pdp_picl_wrap[5] & pcr5_dout[4];
assign picl_wrap[6] = pdp_picl_wrap[6] & pcr6_dout[4];
assign picl_wrap[7] = pdp_picl_wrap[7] & pcr7_dout[4];

// Generate traps if OV bit set (obviously don't increment the counters in this case!)
assign ovh[7:0] = {pcr7_dout[31] & pcr7_dout[5], 
                   pcr6_dout[31] & pcr6_dout[5], 
                   pcr5_dout[31] & pcr5_dout[5], 
                   pcr4_dout[31] & pcr4_dout[5],
                   pcr3_dout[31] & pcr3_dout[5], 
                   pcr2_dout[31] & pcr2_dout[5], 
                   pcr1_dout[31] & pcr1_dout[5], 
                   pcr0_dout[31] & pcr0_dout[5]};

assign ovl[7:0] = {pcr7_dout[18] & pcr7_dout[4], 
                   pcr6_dout[18] & pcr6_dout[4], 
                   pcr5_dout[18] & pcr5_dout[4], 
                   pcr4_dout[18] & pcr4_dout[4],
                   pcr3_dout[18] & pcr3_dout[4], 
                   pcr2_dout[18] & pcr2_dout[4], 
                   pcr1_dout[18] & pcr1_dout[4], 
                   pcr0_dout[18] & pcr0_dout[4]};

// According to dec_del_ctl.sv
// we don't need to clear the valid_d's for br_mispredict, trap flush or load flush
// we will never get a dec_valid_e for these cases
// flush means NOT valid... ifu_fl_e[1] = ~tg0_ityp_e[12]; qualified in th[7:0];

// There are 3 distinct types of signals.
// 1) ige/icge - can get killed by ifu at m/b or tlu at b/w. In either case the kill actually happens
//    one cycle later since the flush signals are flopped for timing reasons.
// 2) the dcge - can get killed by tlu at w (again, 1 cycle later).
// 3) the rest - which can't get killed.
// So, we have to do 2 things:
// A) for the trap signal to TLU, we have to generate a trap request and hold it until TLU acks it
//    via the tlu_pmu_trap_taken signal. This implies that we have a pipe from e2m, m2b, b2w, and w2w1
//    where we kill events appropriately, otherwise OR the flops together. All reqs are killed when
//    the trap_taken signal occurs.
// B) for incrementing the counters, a similar pipe holds. Except that group 1) is piped from e2m, m2b,
//    b2w, w2w1, group 2) is piped from w2w1, and the rest are jammed in during w1.

// Must clip off spurious events during wakeup cycle: during that cycle, events flop has junk in it; and 1 pcr is now valid and counting.
// So one thread can generate spurious events.
assign pipeh_incr_e[7:0] = (ph_ige[7:0] | ph_icge[7:0]) & ~{8 {wakeup}};
assign pipel_incr_e[7:0] = (pl_ige[7:0] | pl_icge[7:0]) & ~{8 {wakeup}};

// Since dec_br_taken[1:0] is late, flop in E, generate br_taken event in W...
assign pipeh_incr_m[7:0] = ph_brm[7:0] & {{4{dec_br_taken_m[1]&dec_valid_m[1]}}, {4 {dec_br_taken_m[0]&dec_valid_m[0]}}};
assign pipel_incr_m[7:0] = pl_brm[7:0] & {{4{dec_br_taken_m[1]&dec_valid_m[1]}}, {4 {dec_br_taken_m[0]&dec_valid_m[0]}}};

// 9/16/05
// Don't consider L2 dcache misses as "flushable" events. If they were supposed to be flushed, they wouldn't
// have made it to L2. So OR them in as "async" events.
assign pipeh_incr_w[7:0] = (dcm_he[7:0] | dtm_he[7:0]) & ~{8 {wakeup}};
assign pipel_incr_w[7:0] = (dcm_le[7:0] | dtm_le[7:0]) & ~{8 {wakeup}};

assign pipeh_async[7:0] = (ph_ai[7:0] | ph_xbe[7:0] | ph_soe[7:0] | ph_sbe[7:0] | ph_mme[7:0] | l2m_he[7:0]) & ~{8 {wait_for_sleep | wakeup}};
assign pipel_async[7:0] = (pl_ai[7:0] | pl_xbe[7:0] | pl_soe[7:0] | pl_sbe[7:0] | pl_mme[7:0] | l2m_le[7:0]) & ~{8 {wait_for_sleep | wakeup}};

// Setup trap pipeline...
// Sample ige/icge events during e using pich/picl_wrap, then pipe to w1, kill with appropriate flushes along the way
// Sample dcge during w using pich/picl_wrap, pipe to w1, kill in w1 with appropriate flushes
// Async sampled at w1 using pich/picl; ov also sampled at w1, but not using pich/picl_wrap
// 0in assert -var ~(((|trap_m[7:0]) | (|trap_b[7:0]) | (|trap_w[7:0]) | (|trap_w1[7:0])) & ~l1b) -message "trap_m or trap_b or trap_w or trap_w1 not 0 when clock stopped!"
pmu_pct_ctl_msff_ctl_macro__width_32 tp  (
	.scan_in(tp_scanin),
	.scan_out(tp_scanout),
	.l1clk	(l1clk_pm1),
	.din	({trap_e[7:0], trap_b_in[7:0], trap_w_in[7:0], trap_w1_in[7:0]} & ~{4 {tpt[7:0]}}),
	.dout	({trap_m[7:0], trap_b[7:0], trap_w[7:0], trap_w1[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Don't power-manage this flop - wait_for_sleep is long enough to get any trap to this flop, 
pmu_pct_ctl_msff_ctl_macro__width_8 tp1  (
	.scan_in(tp1_scanin),
	.scan_out(tp1_scanout),
	.l1clk	(l1clk),
	.din	(trap_hold_in[7:0]),
	.dout	(trap_hold[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in assert -var ~(((|ph_brm[7:0]) | (|pl_brm[7:0]) | (|ph_br_may_trap_m[7:0])) & ~l1b) -message "ph_brm or pl_brm or ph_br_may_trap_m not 0 when clock stopped!"
pmu_pct_ctl_msff_ctl_macro__width_24 br  (
	.scan_in(br_scanin),
	.scan_out(br_scanout),
	.l1clk	(l1clk_pm1),
	.din	(~{24 {wakeup}} & {ph_bre[7:0], pl_bre[7:0], (ph_bre[7:0] & pich_wrap[7:0]) | (pl_bre[7:0] & picl_wrap[7:0])}),
	.dout	({ph_brm[7:0], pl_brm[7:0], ph_br_may_trap_m[7:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// for safety, clear everything when tlu takes a pmu trap for a thread
assign tpt[7:0] = tlu_pmu_trap_taken[7:0];

assign trap_e[7:0] = (pipeh_incr_e[7:0] & pich_wrap[7:0]) |
                     (pipel_incr_e[7:0] & picl_wrap[7:0]);

// Since dec_br_taken[1:0] is late, flop in E, generate br_taken event in W...

//assign trap_b_in[7:0] = trap_m[7:0] & {{4 {dec_valid_m[1]}}, {4 {dec_valid_m[0]}}};
assign trap_b_in[7:0] = (trap_m[7:0] | 
                          (ph_br_may_trap_m[7:0] & {{4 {dec_br_taken_m[1]}}, {4 {dec_br_taken_m[0]}}}))
                        & {{4 {dec_valid_m[1]}}, {4 {dec_valid_m[0]}}};

assign trap_w_in[7:0] = trap_b[7:0] & ~{{4 {ifu_fl_b[1]}}, {4 {ifu_fl_b[0]}}};

assign trap_w1_in[7:0] = trap_w[7:0] & ~{{4 {fl_w[1]}}, {4 {fl_w[0]}}};

assign trap_w1_final[7:0] = (trap_w1 & ~{{4 {tlu_fl_w1[1]}}, {4 {tlu_fl_w1[0]}}});

assign async[7:0] = (pipeh_async[7:0] & pich_wrap[7:0]) |
                    (pipel_async[7:0] & picl_wrap[7:0]);

// Remove ovh & ovl since these will drive the interrupt request directly; also remove trap_hold since
// OV will be set. Use "trap_hold" only to pipeline async requests...
//assign trap_hold_in[7:0] = async[7:0] | ovh[7:0] | ovl[7:0] | trap_w1_final[7:0] | trap_hold[7:0];
assign trap_hold_in[7:0] = async[7:0];

// Deal with the trap signal now...
// Use trap_hold flop output to avoid timing problem w/async req's
// Need to OR in OV bits for the true "hold" function (actually OR the AND of OV & TOE)
assign pmu_tlu_trap_m[7:0] = trap_b_in[7:0] | trap_w_in[7:0] | trap_w1_in[7:0] | trap_w1_final[7:0] | trap_hold[7:0] | ovh[7:0] | ovl[7:0];

// Now for the increment pipeline

// Flop increment signals signals to M stage
// Also register kill signals from IFU and TLU, and gate off increment signals appropriately
// Don't pipe in precise DCmiss, DTmiss, L2Dmiss until W stage!
// Don't gate off "imprecise" events with trap signals, pipe in at "last minute"...
// Inject "0" when wait_for_sleep starts, pipe down...
// 0in assert -var ~(((|ph_incr_m[7:0]) | (|pl_incr_m[7:0])) & ~l1b) -message "ph_incr_m or pl_incr_m not 0 when clock stopped!"
pmu_pct_ctl_msff_ctl_macro__width_18 ti_e2m  (
	.scan_in(ti_e2m_scanin),
	.scan_out(ti_e2m_scanout),
	.l1clk	(l1clk_pm1),
	.din	({(~{16 {wait_for_sleep}} & {pipeh_incr_e[7:0], pipel_incr_e[7:0]}), dec_valid_e[1:0]}),
	.dout	({ph_incr_m[7:0], pl_incr_m[7:0], dec_valid_m[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Kill off if was a flush from ifu for E last cycle
// Also need to kill off increment signals as events flop and/or these ti_* flops stopped with junk in them...
// so need 1 clock to clear out to sync up to pipeline again after restart

// Equivalent to flush from D last cycle
assign ph_i_m[7:0] = (ph_incr_m[7:0] | pipeh_incr_m[7:0]) & {{4 {dec_valid_m[1]}}, {4 {dec_valid_m[0]}}};
assign pl_i_m[7:0] = (pl_incr_m[7:0] | pipel_incr_m[7:0]) & {{4 {dec_valid_m[1]}}, {4 {dec_valid_m[0]}}};

// Pipe increment signals to B stage to wait for possible trap
// 0in assert -var ~(((|ph_incr_b[7:0]) | (|pl_incr_b[7:0])) & ~l1b) -message "ph_incr_b or pl_incr_b not 0 when clock stopped!"
pmu_pct_ctl_msff_ctl_macro__width_18 ti_m2b  (
	.scan_in(ti_m2b_scanin),
	.scan_out(ti_m2b_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ph_i_m[7:0], pl_i_m[7:0], dec_flush_m[1:0]}),
	.dout	({ph_incr_b[7:0], pl_incr_b[7:0], ifu_fl_b[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Kill off if was a flush from ifu for M last cycle
assign ph_i_b[7:0] = ph_incr_b[7:0] & ~{{4 {ifu_fl_b[1]}}, {4 {ifu_fl_b[0]}}};
assign pl_i_b[7:0] = pl_incr_b[7:0] & ~{{4 {ifu_fl_b[1]}}, {4 {ifu_fl_b[0]}}};

// Pipe to W stage, grab trap flush request from IFU or TLU
// 0in assert -var ~(((|ph_incr_w[7:0]) | (|pl_incr_w[7:0])) & ~l1b) -message "ph_incr_w or pl_incr_w not 0 when clock stopped!"
pmu_pct_ctl_msff_ctl_macro__width_18 ti_b2w  (
	.scan_in(ti_b2w_scanin),
	.scan_out(ti_b2w_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ph_i_b[7:0], pl_i_b[7:0], tlu_flush_pmu_b[1:0] | dec_flush_b[1:0]}),
	.dout	({ph_incr_w[7:0], pl_incr_w[7:0], fl_w[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Add in DCmiss, DTmiss, L2Dmiss events from B
// Must be exlusive between thread groups, since each thread can only monitor one event group
// at a time. Within an event group, the only possibility is for the cache events to
// happen on the same instruction (e.g., ICmiss on a load which also DCmisses).
// But the event mask field forces them to be counted as one event.

assign ph_i_w[7:0] = (ph_incr_w[7:0] | pipeh_incr_w[7:0]) & ~{{4 {fl_w[1]}}, {4 {fl_w[0]}}};
assign pl_i_w[7:0] = (pl_incr_w[7:0] | pipel_incr_w[7:0]) & ~{{4 {fl_w[1]}}, {4 {fl_w[0]}}};

// Pipe to W+1 stage, grab trap flush request from TLU for W
// 0in assert -var ~(((|ph_incr_w1[7:0]) | (|pl_incr_w1[7:0])) & ~l1b) -message "ph_incr_w1 or pl_incr_w1 not 0 when clock stopped!"
pmu_pct_ctl_msff_ctl_macro__width_18 ti_w2w1  (
	.scan_in(ti_w2w1_scanin),
	.scan_out(ti_w2w1_scanout),
	.l1clk	(l1clk_pm1),
	.din	({ph_i_w[7:0], pl_i_w[7:0], tlu_flush_pmu_w[1:0]}),
	.dout	({ph_incr_w1[7:0], pl_incr_w1[7:0], tlu_fl_w1[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// The counter increment pipeline is as follows:
// (Needed to delay this by 1 cycle compared to original design since flush signal
// for trapping op, which should not increment counters, comes in W, not B)
// In the W+1 stage, generate the final increment signals by gating with trap signals
// Add these increment signals to the 4-bit accumulators for each PIC. Meanwhile mux the
// accumulators (8:1) and PICs for high, low, and each thread group, then flop. The ST (select thread)
// register determines which thread is selected for adding in cycle W+2.
// In the W+2 stage, add the flopped accumulator value to the proper PIC. 
// during W+2 to save another 64-bit register per TG. So critical dataflow path is flopped data ->
// -> adder -> incrementor -> incrementor -> PIC mux flop which should be about
// 500 pS total.

// Generate final increment sums during W1 stage; gate off if tlu flush
// check to make sure async events never intersect with non-async (better if the decoding
// is done correctly)
// 0in assert -var (~|(ph_incr_w1[7:0]&pipeh_async[7:0])) -message "high instruction event and async event not mutex"
// 0in assert -var (~|(pl_incr_w1[7:0]&pipel_async[7:0])) -message "low instruction event and async event not mutex"

// ECOxxx: For tlb misses must not allow tlu to flush the incr signals
//assign ph_final_incr_w1[7:0] = (ph_incr_w1[7:0] & ~{{4 {tlu_fl_w1[1]}}, {4 {tlu_fl_w1[0]}}}) | pipeh_async[7:0];
//assign pl_final_incr_w1[7:0] = (pl_incr_w1[7:0] & ~{{4 {tlu_fl_w1[1]}}, {4 {tlu_fl_w1[0]}}}) | pipel_async[7:0];

assign flush_h[7:0] = (~disable_h[7:0] & { {4{tlu_fl_w1[1]}}, {4{tlu_fl_w1[0]}} });
assign flush_l[7:0] = (~disable_l[7:0] & { {4{tlu_fl_w1[1]}}, {4{tlu_fl_w1[0]}} });

assign ph_final_incr_w1[7:0] = (ph_incr_w1[7:0] & ~flush_h[7:0]) | pipeh_async[7:0];
assign pl_final_incr_w1[7:0] = (pl_incr_w1[7:0] & ~flush_l[7:0]) | pipel_async[7:0];

// Send final increment signals to Trap for debug event (soft/hard stop/trigger)
// Fix below so that event only sent to PMU when a counter wraps (actually the OV bit is set)
// So we are going to do an edge detection (send a pulse whenever the OV bit transitions from 0 to 1)
// assign pmu_tlu_debug_event[7:0] = ph_final_incr_w1[7:0] | pl_final_incr_w1[7:0];
assign pmu_tlu_debug_event[7:0] = {|({pcr7_dout[31],pcr7_dout[18]} & ~x7_1[1:0]), |({pcr6_dout[31],pcr6_dout[18]} & ~x6_1[1:0]), 
                                   |({pcr5_dout[31],pcr5_dout[18]} & ~x5_1[1:0]), |({pcr4_dout[31],pcr4_dout[18]} & ~x4_1[1:0]),
                                   |({pcr3_dout[31],pcr3_dout[18]} & ~x3_1[1:0]), |({pcr2_dout[31],pcr2_dout[18]} & ~x2_1[1:0]),
                                   |({pcr1_dout[31],pcr1_dout[18]} & ~x1_1[1:0]), |({pcr0_dout[31],pcr0_dout[18]} & ~x0_1[1:0])};

// Fix oversight ( - set OV bits when we are within range and a trap occurs...
// Assume that if we are going to increment, and we are within range, and TOE is set,
// there must already be a trap request. Since the trap is disrupting, the trap may
// not occur for some time, but in the meantime we set the OV bit.
assign set_ovh_spec[7:0] = ph_final_incr_w1[7:0] & pich_wrap[7:0];
assign set_ovl_spec[7:0] = pl_final_incr_w1[7:0] & picl_wrap[7:0];

// Now for the increment controls...ST register
// ST runs "asynchronously" to the pipeline
// Cycle through each TG's PICs every 4th cycle
// Logically reset pic_std_w1 to 0x1
// Consider having 1 incrementor for all 8 threads...

// NEW scheme -- Cycle through each TG's PICs every 8th cycle
// Let pct_incr_pic_w1 = 8'h01 => 8'h02  => 8'h04 => 8'h08 => 8'h10 => 8'h20  => 8'h40 => 8'h80

// 0in one_hot -var pic_std_w1[7:0]
assign pic_std_w1[7:0] = {pic_st_dout[7:1], ~pic_st_dout[0]};
assign pic_st_din[7:0] = {pic_std_w1[6:0], ~pic_std_w1[7]};

assign pct_incr_pic_w1[6:0] = pic_std_w1[6:0];

pmu_pct_ctl_msff_ctl_macro__width_8 pic_st  (
      .scan_in(pic_st_scanin),
      .scan_out(pic_st_scanout),
      .l1clk  (l1clk_pm1),
      .din    (pic_st_din[7:0]),
      .dout   (pic_st_dout[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Have 16 4-bit accumulators, one per thread counter
// assert - need to make sure counters never get above 8 (e.g., should be <= 0x8 at all times)
// Increment, but reset to 0 when read (set to 1 if an instruction completes same cycle as accumulator being read)
// If write to PCR, reset accumulator values to 0, under the assumption that accumulated events are leftovers from
// previous event in PCR (this doesn't work if the event/mask are not changed...)

// This bug is especially apparent when idle is being counted...
// find out whether the SL has changed on wr_pcr = 1;
// pdp_asi_din_to_pctl[31:27] and pdp_asi_din_to_pctl[17:14]

// thread 0 high
assign t0h_din[3:0] = (({4 {~pic_std_w1[0]}} & t0h_dout[3:0]) + {3'b0, ph_final_incr_w1[0]}) & 
                       ~{4 {wr_pcr[0] & {pdp_asi_din_to_pctl[30:27] != pcr0_dout[30:27]}}};

pmu_pct_ctl_msff_ctl_macro__width_4 t0h  (
	.scan_in(t0h_scanin),
	.scan_out(t0h_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t0h_din[3:0]),
	.dout	(t0h_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t0h_dout[3:0] -val 8 -message "t0h accumulator overflow"
// 0in assert -var ~((|t0h_dout[3:0]) & ~l1b) -message "t0h accumulator non-zero when clocks off!"

// thread 1 high
assign t1h_din[3:0] = (({4 {~pic_std_w1[1]}} & t1h_dout[3:0]) + {3'b0, ph_final_incr_w1[1]}) & 
                       ~{4 {wr_pcr[1] & {pdp_asi_din_to_pctl[30:27] != pcr1_dout[30:27]}}};

pmu_pct_ctl_msff_ctl_macro__width_4 t1h  (
	.scan_in(t1h_scanin),
	.scan_out(t1h_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t1h_din[3:0]),
	.dout	(t1h_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t1h_dout[3:0] -val 8 -message "t1h accumulator overflow"
// 0in assert -var ~((|t1h_dout[3:0]) & ~l1b) -message "t1h accumulator non-zero when clocks off!"

// thread 2 high
assign t2h_din[3:0] = (({4 {~pic_std_w1[2]}} & t2h_dout[3:0]) + {3'b0, ph_final_incr_w1[2]}) & 
                       ~{4 {wr_pcr[2] & {pdp_asi_din_to_pctl[30:27] != pcr2_dout[30:27]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t2h  (
	.scan_in(t2h_scanin),
	.scan_out(t2h_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t2h_din[3:0]),
	.dout	(t2h_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t2h_dout[3:0] -val 8 -message "t2h accumulator overflow"
// 0in assert -var ~((|t2h_dout[3:0]) & ~l1b) -message "t2h accumulator non-zero when clocks off!"

// thread 3 high
assign t3h_din[3:0] = (({4 {~pic_std_w1[3]}} & t3h_dout[3:0]) + {3'b0, ph_final_incr_w1[3]}) & 
                       ~{4 {wr_pcr[3] & {pdp_asi_din_to_pctl[30:27] != pcr3_dout[30:27]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t3h  (
	.scan_in(t3h_scanin),
	.scan_out(t3h_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t3h_din[3:0]),
	.dout	(t3h_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t3h_dout[3:0] -val 8 -message "t3h accumulator overflow"
// 0in assert -var ~((|t3h_dout[3:0]) & ~l1b) -message "t3h accumulator non-zero when clocks off!"

// thread 4 high
assign t4h_din[3:0] = (({4 {~pic_std_w1[4]}} & t4h_dout[3:0]) + {3'b0, ph_final_incr_w1[4]}) &  
                       ~{4 {wr_pcr[4] & {pdp_asi_din_to_pctl[30:27] != pcr4_dout[30:27]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t4h  (
	.scan_in(t4h_scanin),
	.scan_out(t4h_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t4h_din[3:0]),
	.dout	(t4h_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t4h_dout[3:0] -val 8 -message "t4h accumulator overflow"
// 0in assert -var ~((|t4h_dout[3:0]) & ~l1b) -message "t4h accumulator non-zero when clocks off!"

// thread 5 high
assign t5h_din[3:0] = (({4 {~pic_std_w1[5]}} & t5h_dout[3:0]) + {3'b0, ph_final_incr_w1[5]}) & 
                       ~{4 {wr_pcr[5] & {pdp_asi_din_to_pctl[30:27] != pcr5_dout[30:27]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t5h  (
	.scan_in(t5h_scanin),
	.scan_out(t5h_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t5h_din[3:0]),
	.dout	(t5h_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t5h_dout[3:0] -val 8 -message "t5h accumulator overflow"
// 0in assert -var ~((|t5h_dout[3:0]) & ~l1b) -message "t5h accumulator non-zero when clocks off!"

// thread 6 high
assign t6h_din[3:0] = (({4 {~pic_std_w1[6]}} & t6h_dout[3:0]) + {3'b0, ph_final_incr_w1[6]}) & 
                       ~{4 {wr_pcr[6] & {pdp_asi_din_to_pctl[30:27] != pcr6_dout[30:27]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t6h  (
	.scan_in(t6h_scanin),
	.scan_out(t6h_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t6h_din[3:0]),
	.dout	(t6h_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t6h_dout[3:0] -val 8 -message "t6h accumulator overflow"
// 0in assert -var ~((|t6h_dout[3:0]) & ~l1b) -message "t6h accumulator non-zero when clocks off!"

// thread 7 high
assign t7h_din[3:0] = (({4 {~pic_std_w1[7]}} & t7h_dout[3:0]) + {3'b0, ph_final_incr_w1[7]}) & 
                       ~{4 {wr_pcr[7] & {pdp_asi_din_to_pctl[30:27] != pcr7_dout[30:27]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t7h  (
	.scan_in(t7h_scanin),
	.scan_out(t7h_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t7h_din[3:0]),
	.dout	(t7h_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t7h_dout[3:0] -val 8 -message "t7h accumulator overflow"
// 0in assert -var ~((|t7h_dout[3:0]) & ~l1b) -message "t7h accumulator non-zero when clocks off!"

// thread 0 low
assign t0l_din[3:0] = (({4 {~pic_std_w1[0]}} & t0l_dout[3:0]) + {3'b0, pl_final_incr_w1[0]}) & 
                       ~{4 {wr_pcr[0] & {pdp_asi_din_to_pctl[17:14] != pcr0_dout[17:14]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t0l  (
	.scan_in(t0l_scanin),
	.scan_out(t0l_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t0l_din[3:0]),
	.dout	(t0l_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t0l_dout[3:0] -val 8 -message "t0l accumulator overflow"
// 0in assert -var ~((|t0l_dout[3:0]) & ~l1b) -message "t0l accumulator non-zero when clocks off!"

// thread 1 low
assign t1l_din[3:0] = (({4 {~pic_std_w1[1]}} & t1l_dout[3:0]) + {3'b0, pl_final_incr_w1[1]}) & 
                       ~{4 {wr_pcr[1] & {pdp_asi_din_to_pctl[17:14] != pcr1_dout[17:14]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t1l  (
	.scan_in(t1l_scanin),
	.scan_out(t1l_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t1l_din[3:0]),
	.dout	(t1l_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t1l_dout[3:0] -val 8 -message "t1l accumulator overflow"
// 0in assert -var ~((|t1l_dout[3:0]) & ~l1b) -message "t1l accumulator non-zero when clocks off!"

// thread 2 low
assign t2l_din[3:0] = (({4 {~pic_std_w1[2]}} & t2l_dout[3:0]) + {3'b0, pl_final_incr_w1[2]}) & 
                       ~{4 {wr_pcr[2] & {pdp_asi_din_to_pctl[17:14] != pcr2_dout[17:14]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t2l  (
	.scan_in(t2l_scanin),
	.scan_out(t2l_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t2l_din[3:0]),
	.dout	(t2l_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t2l_dout[3:0] -val 8 -message "t2l accumulator overflow"
// 0in assert -var ~((|t2l_dout[3:0]) & ~l1b) -message "t2l accumulator non-zero when clocks off!"

// thread 3 low
assign t3l_din[3:0] = (({4 {~pic_std_w1[3]}} & t3l_dout[3:0]) + {3'b0, pl_final_incr_w1[3]}) & 
                       ~{4 {wr_pcr[3] & {pdp_asi_din_to_pctl[17:14] != pcr3_dout[17:14]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t3l  (
	.scan_in(t3l_scanin),
	.scan_out(t3l_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t3l_din[3:0]),
	.dout	(t3l_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t3l_dout[3:0] -val 8 -message "t3l accumulator overflow"
// 0in assert -var ~((|t3l_dout[3:0]) & ~l1b) -message "t3l accumulator non-zero when clocks off!"

// thread 4 low
assign t4l_din[3:0] = (({4 {~pic_std_w1[4]}} & t4l_dout[3:0]) + {3'b0, pl_final_incr_w1[4]}) & 
                       ~{4 {wr_pcr[4] & {pdp_asi_din_to_pctl[17:14] != pcr4_dout[17:14]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t4l  (
	.scan_in(t4l_scanin),
	.scan_out(t4l_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t4l_din[3:0]),
	.dout	(t4l_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t4l_dout[3:0] -val 8 -message "t4l accumulator overflow"
// 0in assert -var ~((|t4l_dout[3:0]) & ~l1b) -message "t4l accumulator non-zero when clocks off!"

// thread 5 low
assign t5l_din[3:0] = (({4 {~pic_std_w1[5]}} & t5l_dout[3:0]) + {3'b0, pl_final_incr_w1[5]}) & 
                       ~{4 {wr_pcr[5] & {pdp_asi_din_to_pctl[17:14] != pcr5_dout[17:14]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t5l  (
	.scan_in(t5l_scanin),
	.scan_out(t5l_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t5l_din[3:0]),
	.dout	(t5l_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t5l_dout[3:0] -val 8 -message "t5l accumulator overflow"
// 0in assert -var ~((|t5l_dout[3:0]) & ~l1b) -message "t0l accumulator non-zero when clocks off!"

// thread 6 low
assign t6l_din[3:0] = (({4 {~pic_std_w1[6]}} & t6l_dout[3:0]) + {3'b0, pl_final_incr_w1[6]}) & 
                       ~{4 {wr_pcr[6] & {pdp_asi_din_to_pctl[17:14] != pcr6_dout[17:14]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t6l  (
	.scan_in(t6l_scanin),
	.scan_out(t6l_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t6l_din[3:0]),
	.dout	(t6l_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t6l_dout[3:0] -val 8 -message "t6l accumulator overflow"
// 0in assert -var ~((|t6l_dout[3:0]) & ~l1b) -message "t6l accumulator non-zero when clocks off!"

// thread 7 low
assign t7l_din[3:0] = (({4 {~pic_std_w1[7]}} & t7l_dout[3:0]) + {3'b0, pl_final_incr_w1[7]}) & 
                       ~{4 {wr_pcr[7] & {pdp_asi_din_to_pctl[17:14] != pcr7_dout[17:14]}}};
pmu_pct_ctl_msff_ctl_macro__width_4 t7l  (
	.scan_in(t7l_scanin),
	.scan_out(t7l_scanout),
	.l1clk	(l1clk_pm1),
	.din	(t7l_din[3:0]),
	.dout	(t7l_dout[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in maximum -var t7l_dout[3:0] -val 8 -message "t7l accumulator overflow"
// 0in assert -var ~((|t7l_dout[3:0]) & ~l1b) -message "t7l accumulator non-zero when clocks off!"

// Mux during W1
// Force a zero value iff are writing to the PIC from the ASI this cycle,
// to prevent overwriting the PIC with the previous PIC + accum. value
// Instead we write the PIC in 2 successive cycles...to save 8 flop bits

assign pich07_add_in_w1[3:0] = ({4 {pic_std_w1[7] & ~incr_asi[7]}} & t7h_dout[3:0]) |
                               ({4 {pic_std_w1[6] & ~incr_asi[6]}} & t6h_dout[3:0]) | 
                               ({4 {pic_std_w1[5] & ~incr_asi[5]}} & t5h_dout[3:0]) | 
                               ({4 {pic_std_w1[4] & ~incr_asi[4]}} & t4h_dout[3:0]) |
			       ({4 {pic_std_w1[3] & ~incr_asi[3]}} & t3h_dout[3:0]) |
                               ({4 {pic_std_w1[2] & ~incr_asi[2]}} & t2h_dout[3:0]) | 
                               ({4 {pic_std_w1[1] & ~incr_asi[1]}} & t1h_dout[3:0]) | 
                               ({4 {pic_std_w1[0] & ~incr_asi[0]}} & t0h_dout[3:0]);

assign picl07_add_in_w1[3:0] = ({4 {pic_std_w1[7] & ~incr_asi[7]}} & t7l_dout[3:0]) |
                               ({4 {pic_std_w1[6] & ~incr_asi[6]}} & t6l_dout[3:0]) | 
                               ({4 {pic_std_w1[5] & ~incr_asi[5]}} & t5l_dout[3:0]) | 
                               ({4 {pic_std_w1[4] & ~incr_asi[4]}} & t4l_dout[3:0]) |
			       ({4 {pic_std_w1[3] & ~incr_asi[3]}} & t3l_dout[3:0]) |
                               ({4 {pic_std_w1[2] & ~incr_asi[2]}} & t2l_dout[3:0]) | 
                               ({4 {pic_std_w1[1] & ~incr_asi[1]}} & t1l_dout[3:0]) | 
                               ({4 {pic_std_w1[0] & ~incr_asi[0]}} & t0l_dout[3:0]);


// Now register and drive to datapath adder during W+1;
// also register the ST signals to drive the PIC muxes during W+1
pmu_pct_ctl_msff_ctl_macro__width_8 accum  (
	.scan_in(accum_scanin),
	.scan_out(accum_scanout),
	.l1clk	(l1clk_pm1),
	.din	({pich07_add_in_w1[3:0], picl07_add_in_w1[3:0]}),
	.dout	({pct_pich07_add_w2[3:0], pct_picl07_add_w2[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

// w2 is w1 from the previous cycle; e.g., rotate w1 right
assign pic_std_w2[7:0] = {pic_std_w1[0], pic_std_w1[7:1]};

// ASI write timing:
// 1st cycle: decode ASI data bus (contains address) & control field;
//            pipe ASI to output flop; flop if request for us & which op to do
// 2nd cycle: if ASI not for us, pipe ASI input flop to output flop; else
//            for ASI write, write ASI data into selected PIC or PCR; else for
//            ASI read, drive mux controls and select PIC/PCR at ASI output flop

// Format of ASI data in bus:
// 64    - ctl/data
// 63    - valid/hole
// 62    - ack/nack
// 61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR   
// 59    - rd/wr
// 58:56 - Thread ID
// 55:48 - ASI field/exception: if illegal opcode, set bit 48; if privileged operation, set bit 49
// 47:0  - Virtual Address

// PCR ASR = 16 (decimal), PIC = 17 decimal 
// PCR is privileged, PIC is privileged if PCR.PRIV is set...
  
// 1st cycle decode
// See if this op is for us
assign asi_cntrl_h[15:8] = pdp_asi_ctlin_to_pctl_15_8[7:0];
assign asi_cntrl[4:0] = pdp_asi_ctlin_to_pctl_4_0[4:0];

assign asr = ~asi_cntrl_h[13] & asi_cntrl_h[12];
assign asr_rd = asi_ctl_ndata & asi_cntrl_h[15] & ~asi_cntrl_h[14] & asr & asi_cntrl_h[11];
assign asr_wr = asi_ctl_ndata & asi_cntrl_h[15] & ~asi_cntrl_h[14] & asr & ~asi_cntrl_h[11];
assign pcr = asi_cntrl[4] & ~asi_cntrl[3] & ~asi_cntrl[2] & ~asi_cntrl[1] & ~asi_cntrl[0]; // 16
assign pic = asi_cntrl[4] & ~asi_cntrl[3] & ~asi_cntrl[2] & ~asi_cntrl[1] &  asi_cntrl[0]; // 17

assign pic_rd = asr_rd & pic;
assign pic_wr = asr_wr & pic;
assign pcr_rd = asr_rd & pcr;
assign pcr_wr = asr_wr & pcr;

// If this op is for us, make sure the ack bit is not set...otherwise there is a decode conflict on
// the local ring; this actually isn't a full check unless the pmu is the last link on the ring before 
// returning to the lsu
// 0in assert -var (~((pic | pcr) & asr & asi_ctl_ndata & asi_cntrl_h[15] & asi_cntrl_h[14])) -message "ack set for pic or pcr operation"

assign tid[7:0] = {
   asi_cntrl_h[10] &  asi_cntrl_h[9] &  asi_cntrl_h[8],  
   asi_cntrl_h[10] &  asi_cntrl_h[9] & ~asi_cntrl_h[8],  
   asi_cntrl_h[10] & ~asi_cntrl_h[9] &  asi_cntrl_h[8],  
   asi_cntrl_h[10] & ~asi_cntrl_h[9] & ~asi_cntrl_h[8],  
  ~asi_cntrl_h[10] &  asi_cntrl_h[9] &  asi_cntrl_h[8],  
  ~asi_cntrl_h[10] &  asi_cntrl_h[9] & ~asi_cntrl_h[8],  
  ~asi_cntrl_h[10] & ~asi_cntrl_h[9] &  asi_cntrl_h[8],  
  ~asi_cntrl_h[10] & ~asi_cntrl_h[9] & ~asi_cntrl_h[8]
                  };  

// Check for exceptions...if no exception set ack bit
assign asr_priv[7:0] = tid[7:0] & ~(hpriv[7:0] | priv[7:0]) & (
                                                               ({8 {pcr_rd | pcr_wr}}) |
                                                               ({8 {pic_rd | pic_wr}} & {pcr7_dout[0], pcr6_dout[0],
                                                                                         pcr5_dout[0], pcr4_dout[0], 
                                                                                         pcr3_dout[0], pcr2_dout[0], 
                                                                                         pcr1_dout[0], pcr0_dout[0]})
                                                              );

assign priv_ex = |asr_priv[7:0];
assign pmu_op = pic_rd | pic_wr | pcr_rd | pcr_wr;
assign pct_exception = priv_ex;

pmu_pct_ctl_l1clkhdr_ctl_macro asi_busy_clkgen (
        .l2clk  (l2clk          	),
        .l1en   (pmu_asi_clken 		),
//        .l1clk  (asi_busy_l1clk		)
        .l1clk  (l1clk_pm4		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

pmu_pct_ctl_msff_ctl_macro__width_14 asi  (
	.scan_in(asi_scanin),
	.scan_out(asi_scanout),
	.l1clk	(l1clk_pm4),
	.din	({pic_rd & ~priv_ex, pic_wr & ~priv_ex, pcr_rd & ~priv_ex, pcr_wr & ~priv_ex, tid[7:0], 
                  in_rngl_cdbus_ctl_ndata, asi_ctl_ndata}),
	.dout	({p_rd, p_wr, pc_rd, pc_wr, atid[7:0], 
                  asi_ctl_ndata, pct_rngl_cdbus_ctl_ndata}),
  .siclk(siclk),
  .soclk(soclk)
);

// Mux down PCR for read
// save power at expense of time if can by gating with pc_rd
// Restore read of bits 30 and 17
assign pcr0_read[31:0] = {pcr0_dout[31], disable_h[0], pcr0_dout[29:18], disable_l[0], pcr0_dout[16:0]};
assign pcr1_read[31:0] = {pcr1_dout[31], disable_h[1], pcr1_dout[29:18], disable_l[1], pcr1_dout[16:0]};
assign pcr2_read[31:0] = {pcr2_dout[31], disable_h[2], pcr2_dout[29:18], disable_l[2], pcr2_dout[16:0]};
assign pcr3_read[31:0] = {pcr3_dout[31], disable_h[3], pcr3_dout[29:18], disable_l[3], pcr3_dout[16:0]};
assign pcr4_read[31:0] = {pcr4_dout[31], disable_h[4], pcr4_dout[29:18], disable_l[4], pcr4_dout[16:0]};
assign pcr5_read[31:0] = {pcr5_dout[31], disable_h[5], pcr5_dout[29:18], disable_l[5], pcr5_dout[16:0]};
assign pcr6_read[31:0] = {pcr6_dout[31], disable_h[6], pcr6_dout[29:18], disable_l[6], pcr6_dout[16:0]};
assign pcr7_read[31:0] = {pcr7_dout[31], disable_h[7], pcr7_dout[29:18], disable_l[7], pcr7_dout[16:0]};

assign pct_pcr_data[31:0] = ({32 {pc_rd & atid[0]}} & pcr0_read[31:0]) | 
                            ({32 {pc_rd & atid[1]}} & pcr1_read[31:0]) |   
                            ({32 {pc_rd & atid[2]}} & pcr2_read[31:0]) |   
                            ({32 {pc_rd & atid[3]}} & pcr3_read[31:0]) |   
                            ({32 {pc_rd & atid[4]}} & pcr4_read[31:0]) |   
                            ({32 {pc_rd & atid[5]}} & pcr5_read[31:0]) |   
                            ({32 {pc_rd & atid[6]}} & pcr6_read[31:0]) |   
                            ({32 {pc_rd & atid[7]}} & pcr7_read[31:0]);   

assign pct_rd_pic_pcr = p_rd | pc_rd;

// Generate PIC mux selects for read
assign pct_rd_pic[7:0] = {8 {p_rd}} & atid[7:0];
assign pct_rd_a_pic = p_rd;

// Always bypass unless doing an ASR/PR read for this node
assign pct_bypass_asi = ~(p_rd | pc_rd | pmu_op);

// There is a 2 cycle pipeline for writing to a PIC
// In cycle 1 (which corresponds to W+1), pic_std_w1 selects a thread for adding the next cycle;
// the thread's PIC is muxed into a staging register in pdp. The accumulator has also been selected
// and is flopped in pct_pic*_add_w1 above.
// In cycle 2, the PIC and the accumulator value are added in the DP block.

// Simple enough but we have to consider the case of writing to a PIC from the ASI and doing an
// increment the same cycle...We consider this architecturally undefined, but we would like
// to have a predictable value for validation purposes. The cleanest solution is to always
// select the ASI value.

// Note: At the current time, wr %pic is post-syncing...and there is a 5-cycle delay between
// the pic update in W+2 and the ASI write to the PIC. The delay will increase when the FGU is
// added in the local ring ahead of the PMU. Due to the post-syncing, there isn't a way to
// keep the PIC counting events past a wr %pic...so we can't test a simultaneous write to
// an incrementing PIC using instructions. This has to be tested via async. events.

// Since there is a 2-cycle pipeline, there are 4 cases:
// 1. Write to ASI in W+2 and add PIC in W+2. Here we should overwrite the updated PIC with the new ASI value. Note:
//    we may lose counts due to this. The only way to fix this is to put a mux in front of the adder during W+2.
// 2. Write to ASI in W+1 and add PIC in W+2. Here we should select the ASI value, otherwise,
//    we will lose the ASI data by overwriting it with the previous PIC + accumulator value.
// 3. Write to ASI in W+3 and add PIC in W+2. This works fine.
// 4. Write to ASI in W and add PIC in W+2. This works fine.
// We could disable the write during case 2) above which would guarantee that the ASI value always wins 
// over a current update. We could handle this either by forcing an add of 0 to the ASI value, or disabling writing the
// PIC with the ASI+accumulator in W+2. For now we choose the former, to avoid having 8 flops to degate pct_incr_pic_w2
// (below) if incr_asi was set the previous cycle.

// Decode for PIC write; force ASI over increment value if both happen during W2
assign pct_wr_pic_w2[7:0] = {8 {p_wr}} & atid[7:0];
//assign pct_incr_pic_w2[7:0] = {pic_std_w2[7:0]} & ~pct_wr_pic_w2[7:0];

// Selects for pre-add flop port...select asi if incrementing and writing
assign incr_asi[7:0] = pic_std_w1[7:0] & {8 {p_wr}} & atid[7:0];
assign pct_incr_asi_w1 = {|incr_asi[7:0]};

// Clock enable for pic07_w2 flop (adder for PIC incrementors)
//assign pct_pic07_w2_clken = pct_incr_asi_w1 | (|pct_pic_clken[7:0]);
// add in wr_pcr below - if pcr is not active now, but will be next cycle, need to make sure we
// select the proper pic value this cycle; else may add in wrong pic value (e.g., leftover from a previous thread)
assign pct_pic07_w2_clken = ~pmu_pmen | pct_incr_asi_w1 | (|(pic_std_w1[7:0] & (wr_pcr[7:0] | (
                            {|pcr7_dout[3:1],|pcr6_dout[3:1],|pcr5_dout[3:1],|pcr4_dout[3:1],
                             |pcr3_dout[3:1],|pcr2_dout[3:1],|pcr1_dout[3:1],|pcr0_dout[3:1]}))));


// Update PCR on write
assign wr_pcr[7:0] = {8 {pc_wr}} & atid[7:0];

// Clear PCR OV bits on read...
assign rd_pcr[7:0] = {8 {pc_rd}} & atid[7:0];

supply0 vss;
supply1 vdd;

pmu_pct_ctl_spare_ctl_macro__num_12 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk),
  .siclk(siclk),
  .soclk(soclk));

// fixscan start:
assign pwrm_scanin               = scan_in                  ;
assign sleep_cnt_scanin          = pwrm_scanout             ;
assign hpstate_scanin            = sleep_cnt_scanout        ;
assign events_scanin             = hpstate_scanout          ;
assign lsutid_scanin             = events_scanout           ;
assign pcr0_scanin               = lsutid_scanout           ;
assign pcr0_ov_scanin            = pcr0_scanout             ;
assign pcr1_scanin               = pcr0_ov_scanout          ;
assign pcr1_ov_scanin            = pcr1_scanout             ;
assign pcr2_scanin               = pcr1_ov_scanout          ;
assign pcr2_ov_scanin            = pcr2_scanout             ;
assign pcr3_scanin               = pcr2_ov_scanout          ;
assign pcr3_ov_scanin            = pcr3_scanout             ;
assign pcr4_scanin               = pcr3_ov_scanout          ;
assign pcr4_ov_scanin            = pcr4_scanout             ;
assign pcr5_scanin               = pcr4_ov_scanout          ;
assign pcr5_ov_scanin            = pcr5_scanout             ;
assign pcr6_scanin               = pcr5_ov_scanout          ;
assign pcr6_ov_scanin            = pcr6_scanout             ;
assign pcr7_scanin               = pcr6_ov_scanout          ;
assign pcr7_ov_scanin            = pcr7_scanout             ;
assign pcr_ov_del_scanin         = pcr7_ov_scanout          ;
assign lsu_e2m_scanin            = pcr_ov_del_scanout       ;
assign tp_scanin                 = lsu_e2m_scanout          ;
assign tp1_scanin                = tp_scanout               ;
assign br_scanin                 = tp1_scanout              ;
assign ti_e2m_scanin             = br_scanout               ;
assign ti_m2b_scanin             = ti_e2m_scanout           ;
assign ti_b2w_scanin             = ti_m2b_scanout           ;
assign ti_w2w1_scanin            = ti_b2w_scanout           ;
assign pic_st_scanin             = ti_w2w1_scanout          ;
assign t0h_scanin                = pic_st_scanout           ;
assign t1h_scanin                = t0h_scanout              ;
assign t2h_scanin                = t1h_scanout              ;
assign t3h_scanin                = t2h_scanout              ;
assign t4h_scanin                = t3h_scanout              ;
assign t5h_scanin                = t4h_scanout              ;
assign t6h_scanin                = t5h_scanout              ;
assign t7h_scanin                = t6h_scanout              ;
assign t0l_scanin                = t7h_scanout              ;
assign t1l_scanin                = t0l_scanout              ;
assign t2l_scanin                = t1l_scanout              ;
assign t3l_scanin                = t2l_scanout              ;
assign t4l_scanin                = t3l_scanout              ;
assign t5l_scanin                = t4l_scanout              ;
assign t6l_scanin                = t5l_scanout              ;
assign t7l_scanin                = t6l_scanout              ;
assign accum_scanin              = t7l_scanout              ;
assign asi_scanin                = accum_scanout            ;
assign spares_scanin             = asi_scanout              ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_66 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [65:0] fdin;
wire [64:0] so;

  input [65:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [65:0] dout;
  output scan_out;
assign fdin[65:0] = din[65:0];


dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[65:0]),
.si({scan_in,so[64:0]}),
.so({so[64:0],scan_out}),
.q(dout[65:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_30 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [29:0] fdin;
wire [28:0] so;

  input [29:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [29:0] dout;
  output scan_out;
assign fdin[29:0] = din[29:0];


dff #(30)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[29:0]),
.si({scan_in,so[28:0]}),
.so({so[28:0],scan_out}),
.q(dout[29:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_28 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [27:0] fdin;
wire [26:0] so;

  input [27:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [27:0] dout;
  output scan_out;
assign fdin[27:0] = din[27:0];


dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_32 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [30:0] so;

  input [31:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = din[31:0];


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_18 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [17:0] fdin;
wire [16:0] so;

  input [17:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [17:0] dout;
  output scan_out;
assign fdin[17:0] = din[17:0];


dff #(18)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[17:0]),
.si({scan_in,so[16:0]}),
.so({so[16:0],scan_out}),
.q(dout[17:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pct_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module pmu_pct_ctl_spare_ctl_macro__num_12 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire si_8;
wire so_8;
wire spare8_flop_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;
wire si_9;
wire so_9;
wire spare9_flop_unused;
wire spare9_buf_32x_unused;
wire spare9_nand3_8x_unused;
wire spare9_inv_8x_unused;
wire spare9_aoi22_4x_unused;
wire spare9_buf_8x_unused;
wire spare9_oai22_4x_unused;
wire spare9_inv_16x_unused;
wire spare9_nand2_16x_unused;
wire spare9_nor3_4x_unused;
wire spare9_nand2_8x_unused;
wire spare9_buf_16x_unused;
wire spare9_nor2_16x_unused;
wire spare9_inv_32x_unused;
wire si_10;
wire so_10;
wire spare10_flop_unused;
wire spare10_buf_32x_unused;
wire spare10_nand3_8x_unused;
wire spare10_inv_8x_unused;
wire spare10_aoi22_4x_unused;
wire spare10_buf_8x_unused;
wire spare10_oai22_4x_unused;
wire spare10_inv_16x_unused;
wire spare10_nand2_16x_unused;
wire spare10_nor3_4x_unused;
wire spare10_nand2_8x_unused;
wire spare10_buf_16x_unused;
wire spare10_nor2_16x_unused;
wire spare10_inv_32x_unused;
wire si_11;
wire so_11;
wire spare11_flop_unused;
wire spare11_buf_32x_unused;
wire spare11_nand3_8x_unused;
wire spare11_inv_8x_unused;
wire spare11_aoi22_4x_unused;
wire spare11_buf_8x_unused;
wire spare11_oai22_4x_unused;
wire spare11_inv_16x_unused;
wire spare11_nand2_16x_unused;
wire spare11_nor3_4x_unused;
wire spare11_nand2_8x_unused;
wire spare11_buf_16x_unused;
wire spare11_nor2_16x_unused;
wire spare11_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));

cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_8),
                               .so(so_8),
                               .d(1'b0),
                               .q(spare8_flop_unused));
assign si_8 = so_7;

cl_u1_buf_32x   spare8_buf_32x (.in(1'b1),
                                   .out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare8_nand3_8x_unused));
cl_u1_inv_8x    spare8_inv_8x (.in(1'b1),
                                  .out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_aoi22_4x_unused));
cl_u1_buf_8x    spare8_buf_8x (.in(1'b1),
                                  .out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_oai22_4x_unused));
cl_u1_inv_16x   spare8_inv_16x (.in(1'b1),
                                   .out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare8_nand2_8x_unused));
cl_u1_buf_16x   spare8_buf_16x (.in(1'b1),
                                   .out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare8_nor2_16x_unused));
cl_u1_inv_32x   spare8_inv_32x (.in(1'b1),
                                   .out(spare8_inv_32x_unused));

cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_9),
                               .so(so_9),
                               .d(1'b0),
                               .q(spare9_flop_unused));
assign si_9 = so_8;

cl_u1_buf_32x   spare9_buf_32x (.in(1'b1),
                                   .out(spare9_buf_32x_unused));
cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare9_nand3_8x_unused));
cl_u1_inv_8x    spare9_inv_8x (.in(1'b1),
                                  .out(spare9_inv_8x_unused));
cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_aoi22_4x_unused));
cl_u1_buf_8x    spare9_buf_8x (.in(1'b1),
                                  .out(spare9_buf_8x_unused));
cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_oai22_4x_unused));
cl_u1_inv_16x   spare9_inv_16x (.in(1'b1),
                                   .out(spare9_inv_16x_unused));
cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare9_nand2_16x_unused));
cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare9_nor3_4x_unused));
cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare9_nand2_8x_unused));
cl_u1_buf_16x   spare9_buf_16x (.in(1'b1),
                                   .out(spare9_buf_16x_unused));
cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare9_nor2_16x_unused));
cl_u1_inv_32x   spare9_inv_32x (.in(1'b1),
                                   .out(spare9_inv_32x_unused));

cl_sc1_msff_8x spare10_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_10),
                               .so(so_10),
                               .d(1'b0),
                               .q(spare10_flop_unused));
assign si_10 = so_9;

cl_u1_buf_32x   spare10_buf_32x (.in(1'b1),
                                   .out(spare10_buf_32x_unused));
cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare10_nand3_8x_unused));
cl_u1_inv_8x    spare10_inv_8x (.in(1'b1),
                                  .out(spare10_inv_8x_unused));
cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare10_aoi22_4x_unused));
cl_u1_buf_8x    spare10_buf_8x (.in(1'b1),
                                  .out(spare10_buf_8x_unused));
cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare10_oai22_4x_unused));
cl_u1_inv_16x   spare10_inv_16x (.in(1'b1),
                                   .out(spare10_inv_16x_unused));
cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare10_nand2_16x_unused));
cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare10_nor3_4x_unused));
cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare10_nand2_8x_unused));
cl_u1_buf_16x   spare10_buf_16x (.in(1'b1),
                                   .out(spare10_buf_16x_unused));
cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare10_nor2_16x_unused));
cl_u1_inv_32x   spare10_inv_32x (.in(1'b1),
                                   .out(spare10_inv_32x_unused));

cl_sc1_msff_8x spare11_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_11),
                               .so(so_11),
                               .d(1'b0),
                               .q(spare11_flop_unused));
assign si_11 = so_10;

cl_u1_buf_32x   spare11_buf_32x (.in(1'b1),
                                   .out(spare11_buf_32x_unused));
cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare11_nand3_8x_unused));
cl_u1_inv_8x    spare11_inv_8x (.in(1'b1),
                                  .out(spare11_inv_8x_unused));
cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare11_aoi22_4x_unused));
cl_u1_buf_8x    spare11_buf_8x (.in(1'b1),
                                  .out(spare11_buf_8x_unused));
cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare11_oai22_4x_unused));
cl_u1_inv_16x   spare11_inv_16x (.in(1'b1),
                                   .out(spare11_inv_16x_unused));
cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare11_nand2_16x_unused));
cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare11_nor3_4x_unused));
cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare11_nand2_8x_unused));
cl_u1_buf_16x   spare11_buf_16x (.in(1'b1),
                                   .out(spare11_buf_16x_unused));
cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare11_nor2_16x_unused));
cl_u1_inv_32x   spare11_inv_32x (.in(1'b1),
                                   .out(spare11_inv_32x_unused));
assign scan_out = so_11;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: pmu_pdp_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module pmu_pdp_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_out, 
  in_rngl_cdbus, 
  pct_rd_pic, 
  pct_rd_a_pic, 
  pct_rd_pic_pcr, 
  pct_bypass_asi, 
  pct_pcr_data, 
  pct_exception, 
  pct_pic_clken, 
  pct_pic07_w2_clken, 
  pct_wr_pic_w2, 
  pct_incr_pic_w1, 
  pct_incr_asi_w1, 
  pct_pich07_add_w2, 
  pct_picl07_add_w2, 
  pmu_asi_clken, 
  pmu_rngl_cdbus, 
  pdp_asi_din_to_pctl, 
  pdp_asi_ctlin_to_pctl_15_8, 
  pdp_asi_ctlin_to_pctl_4_0, 
  pdp_pich_cout07, 
  pdp_picl_cout07, 
  pdp_pich_wrap, 
  pdp_picl_wrap);
wire stop;
wire se;
wire pce_ov;
wire siclk;
wire soclk;
wire asi_din_scanin;
wire asi_din_scanout;
wire [63:0] pdp_asi_din;
wire pic0_scanin;
wire pic0_scanout;
wire [31:0] pich07_incr;
wire [31:0] picl07_incr;
wire [31:0] pich0;
wire [31:0] picl0;
wire [7:0] pdp_pich_wrapa;
wire [7:0] pdp_picl_wrapa;
wire [7:0] pdp_pich_wrapb;
wire [7:0] pdp_picl_wrapb;
wire pic1_scanin;
wire pic1_scanout;
wire [31:0] pich1;
wire [31:0] picl1;
wire pic2_scanin;
wire pic2_scanout;
wire [31:0] pich2;
wire [31:0] picl2;
wire pic3_scanin;
wire pic3_scanout;
wire [31:0] pich3;
wire [31:0] picl3;
wire pic4_scanin;
wire pic4_scanout;
wire [31:0] pich4;
wire [31:0] picl4;
wire pic5_scanin;
wire pic5_scanout;
wire [31:0] pich5;
wire [31:0] picl5;
wire pic6_scanin;
wire pic6_scanout;
wire [31:0] pich6;
wire [31:0] picl6;
wire pic7_scanin;
wire pic7_scanout;
wire [31:0] pich7;
wire [31:0] picl7;
wire [31:0] pich07_w1;
wire [31:0] picl07_w1;
wire pic07_w2_scanin;
wire pic07_w2_scanout;
wire [31:0] pich07_w2;
wire [31:0] picl07_w2;
wire [63:0] pdp_pic_data;
wire [63:0] picpcr_data;
wire asi_dout_scanin;
wire asi_dout_scanout;
wire [63:0] pmu_rngl_cdbus_nobuf;


// *** globals ***
input		l2clk;
input 		scan_in;
input 		tcu_pce_ov;		// scan signals
input 		spc_aclk;    
input 		spc_bclk;    
input		tcu_scan_en;
output		scan_out;

// ASI write data bus
input	[63:0]	in_rngl_cdbus;		// ASI ring data input

// ASI read controls
input   [7:0]	pct_rd_pic;		// ASI read of PIC (bit 7 == read PIC for tid 7)
input		pct_rd_a_pic;		// ASI read of any PIC
input		pct_rd_pic_pcr;         // ASI read of PIC or PCR (select PIC or PCR)
input		pct_bypass_asi;		// Flow this node's ASI data to the output
input	[31:0]	pct_pcr_data;		// PCR data on ASI read
input		pct_exception;		// If a privileged exception on an ASR read or write to PIC or PCR
input	[7:0]	pct_pic_clken;		// Clock enables for PIC
input 		pct_pic07_w2_clken; 	// Clock enable for pic07_w2 flop 
// ASI write controls
input	[7:0]	pct_wr_pic_w2;		// Write corresponding PICH/L from ASI (bit 7 == write PIC7)
input	[6:0]	pct_incr_pic_w1;	// increment PIC (PICL is enabled for counting) W+1 cycle (mux prior to adding)
input		pct_incr_asi_w1;	// Select new ASI value to increment to deal with simultaneous ASI write and increment

// Event inputs
input	[3:0]	pct_pich07_add_w2;	// Add value for pich 
input	[3:0]	pct_picl07_add_w2;	// Add value for picl 

// ASI pwr mgmt
input		pmu_asi_clken;		// Gate ASI ring flops

// ASI outputs
output	[63:0]  pmu_rngl_cdbus;		// ASI ring data out 
output	[31:0]	pdp_asi_din_to_pctl;	// for PCR writes
output	[7:0]	pdp_asi_ctlin_to_pctl_15_8;  // Bits 63:56 of registered data from PDP (save 8 flop bits)
output	[4:0] 	pdp_asi_ctlin_to_pctl_4_0;  // Bits 63:48 of registered data from PDP (save 5 flop bits)

// Carry-out bits for PCR of each counter
output		pdp_pich_cout07;	// carry-outs of incrementors, to set OV bits in PCR's
output		pdp_picl_cout07;		

// Wrap indicators for trap generation
output	[7:0]	pdp_pich_wrap;		// If counter within -16..-1
output	[7:0]	pdp_picl_wrap;		// If counter within -16..-1

// scan renames
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
assign stop = 1'b0;
//assign siclk = spc_aclk;    
//assign soclk = spc_bclk;
//assign se = tcu_scan_en;
// end scan

pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0  (
  .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
  .dout({se,pce_ov,siclk,soclk})
);

// First put in the ASI staging reg, bit 64 is flopped in ctl
pmu_pdp_dp_msff_macro__stack_64c__width_64 asi_din  (
 .scan_in(asi_din_scanin),
 .scan_out(asi_din_scanout),
 .clk ( l2clk                    ),
 .en  ( pmu_asi_clken            ),  // powerdown pin
 .din( in_rngl_cdbus[63:0]), 
 .dout( pdp_asi_din[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

assign pdp_asi_din_to_pctl[31:0] = pdp_asi_din[31:0]; 	// bus to pctl for PCR writes
assign pdp_asi_ctlin_to_pctl_15_8[7:0] = pdp_asi_din[63:56];// Bits 63:56 of registered data from PDP (save 8 flop bits)
assign pdp_asi_ctlin_to_pctl_4_0[4:0] = pdp_asi_din[52:48];// Bits 52:48 of registered data from PDP (save 5 flop bits)

// PICs
// There are 8, 1 for each thread

// split the 64 bit 3-input mux to two 32 bit ones
// and use AND to zero out the counter values

// PIC0

pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic0     (
 .scan_in(pic0_scanin),
 .scan_out(pic0_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic_clken[0]         ),  // powerdown pin
 .din0( pdp_asi_din[63:0] ), 
 .din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
 .sel0( pct_wr_pic_w2[0] ),
 .dout( {pich0[31:0],picl0[31:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop) );

pmu_pdp_dp_cmp_macro__width_16 pic0hca  (
 .din0(pich0[31:16]),
 .din1(16'hffff),
 .dout(pdp_pich_wrapa[0]));
pmu_pdp_dp_cmp_macro__width_16 pic0lca  (
 .din0(picl0[31:16]),
 .din1(16'hffff),
 .dout(pdp_picl_wrapa[0]));

pmu_pdp_dp_cmp_macro__width_12 pic0hcb  (
 .din0(pich0[15:4]),
 .din1(12'hfff),
 .dout(pdp_pich_wrapb[0]));
pmu_pdp_dp_cmp_macro__width_12 pic0lcb  (
 .din0(picl0[15:4]),
 .din1(12'hfff),
 .dout(pdp_picl_wrapb[0]));

// the ANDing is done for all 8 threads after PIC7
//and_macro pich0wrap (width=2, ports=2) (
// .din0   ({pdp_pich_wrapa[0],pdp_picl_wrapa[0]}),
// .din1   ({pdp_pich_wrapb[0],pdp_picl_wrapb[0]}),
// .dout   ({pdp_pich_wrap[0], pdp_picl_wrap[0]});

// PIC1
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic1     (
 .scan_in(pic1_scanin),
 .scan_out(pic1_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic_clken[1]         ),  // powerdown pin
 .din0( pdp_asi_din[63:0] ), 
 .din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
 .sel0( pct_wr_pic_w2[1] ),
 .dout( {pich1[31:0],picl1[31:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop) );

pmu_pdp_dp_cmp_macro__width_16 pic1hca  (
 .din0(pich1[31:16]),
 .din1(16'hffff),
 .dout(pdp_pich_wrapa[1]));
pmu_pdp_dp_cmp_macro__width_16 pic1lca  (
 .din0(picl1[31:16]),
 .din1(16'hffff),
 .dout(pdp_picl_wrapa[1]));

pmu_pdp_dp_cmp_macro__width_12 pic1hcb  (
 .din0(pich1[15:4]),
 .din1(12'hfff),
 .dout(pdp_pich_wrapb[1]));
pmu_pdp_dp_cmp_macro__width_12 pic1lcb  (
 .din0(picl1[15:4]),
 .din1(12'hfff),
 .dout(pdp_picl_wrapb[1]));

// PIC2
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic2     (
 .scan_in(pic2_scanin),
 .scan_out(pic2_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic_clken[2]         ),  // powerdown pin
 .din0( pdp_asi_din[63:0] ), 
 .din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
 .sel0( pct_wr_pic_w2[2] ),
 .dout( {pich2[31:0],picl2[31:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop) );

pmu_pdp_dp_cmp_macro__width_16 pic2hca  (
 .din0(pich2[31:16]),
 .din1(16'hffff),
 .dout(pdp_pich_wrapa[2]));
pmu_pdp_dp_cmp_macro__width_16 pic2lca  (
 .din0(picl2[31:16]),
 .din1(16'hffff),
 .dout(pdp_picl_wrapa[2]));

pmu_pdp_dp_cmp_macro__width_12 pic2hcb  (
 .din0(pich2[15:4]),
 .din1(12'hfff),
 .dout(pdp_pich_wrapb[2]));
pmu_pdp_dp_cmp_macro__width_12 pic2lcb  (
 .din0(picl2[15:4]),
 .din1(12'hfff),
 .dout(pdp_picl_wrapb[2]));

// PIC3
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic3     (
 .scan_in(pic3_scanin),
 .scan_out(pic3_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic_clken[3]         ),  // powerdown pin
 .din0( pdp_asi_din[63:0] ), 
 .din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
 .sel0( pct_wr_pic_w2[3] ),
 .dout( {pich3[31:0],picl3[31:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop) );

pmu_pdp_dp_cmp_macro__width_16 pic3hca  (
 .din0(pich3[31:16]),
 .din1(16'hffff),
 .dout(pdp_pich_wrapa[3]));
pmu_pdp_dp_cmp_macro__width_16 pic3lca  (
 .din0(picl3[31:16]),
 .din1(16'hffff),
 .dout(pdp_picl_wrapa[3]));

pmu_pdp_dp_cmp_macro__width_12 pic3hcb  (
 .din0(pich3[15:4]),
 .din1(12'hfff),
 .dout(pdp_pich_wrapb[3]));
pmu_pdp_dp_cmp_macro__width_12 pic3lcb  (
 .din0(picl3[15:4]),
 .din1(12'hfff),
 .dout(pdp_picl_wrapb[3]));

// PIC4
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic4     (
 .scan_in(pic4_scanin),
 .scan_out(pic4_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic_clken[4]         ),  // powerdown pin
 .din0( pdp_asi_din[63:0] ), 
 .din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
 .sel0( pct_wr_pic_w2[4] ),
 .dout( {pich4[31:0],picl4[31:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop) );

pmu_pdp_dp_cmp_macro__width_16 pic4hca  (
 .din0(pich4[31:16]),
 .din1(16'hffff),
 .dout(pdp_pich_wrapa[4]));
pmu_pdp_dp_cmp_macro__width_16 pic4lca  (
 .din0(picl4[31:16]),
 .din1(16'hffff),
 .dout(pdp_picl_wrapa[4]));

pmu_pdp_dp_cmp_macro__width_12 pic4hcb  (
 .din0(pich4[15:4]),
 .din1(12'hfff),
 .dout(pdp_pich_wrapb[4]));
pmu_pdp_dp_cmp_macro__width_12 pic4lcb  (
 .din0(picl4[15:4]),
 .din1(12'hfff),
 .dout(pdp_picl_wrapb[4]));

// PIC5
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic5     (
 .scan_in(pic5_scanin),
 .scan_out(pic5_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic_clken[5]         ),  // powerdown pin
 .din0( pdp_asi_din[63:0] ), 
 .din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
 .sel0( pct_wr_pic_w2[5] ),
 .dout( {pich5[31:0],picl5[31:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop) );

pmu_pdp_dp_cmp_macro__width_16 pic5hca  (
 .din0(pich5[31:16]),
 .din1(16'hffff),
 .dout(pdp_pich_wrapa[5]));
pmu_pdp_dp_cmp_macro__width_16 pic5lca  (
 .din0(picl5[31:16]),
 .din1(16'hffff),
 .dout(pdp_picl_wrapa[5]));

pmu_pdp_dp_cmp_macro__width_12 pic5hcb  (
 .din0(pich5[15:4]),
 .din1(12'hfff),
 .dout(pdp_pich_wrapb[5]));
pmu_pdp_dp_cmp_macro__width_12 pic5lcb  (
 .din0(picl5[15:4]),
 .din1(12'hfff),
 .dout(pdp_picl_wrapb[5]));

// PIC6
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic6     (
 .scan_in(pic6_scanin),
 .scan_out(pic6_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic_clken[6]         ),  // powerdown pin
 .din0( pdp_asi_din[63:0] ), 
 .din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
 .sel0( pct_wr_pic_w2[6] ),
 .dout( {pich6[31:0],picl6[31:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop) );

pmu_pdp_dp_cmp_macro__width_16 pic6hca  (
 .din0(pich6[31:16]),
 .din1(16'hffff),
 .dout(pdp_pich_wrapa[6]));
pmu_pdp_dp_cmp_macro__width_16 pic6lca  (
 .din0(picl6[31:16]),
 .din1(16'hffff),
 .dout(pdp_picl_wrapa[6]));

pmu_pdp_dp_cmp_macro__width_12 pic6hcb  (
 .din0(pich6[15:4]),
 .din1(12'hfff),
 .dout(pdp_pich_wrapb[6]));
pmu_pdp_dp_cmp_macro__width_12 pic6lcb  (
 .din0(picl6[15:4]),
 .din1(12'hfff),
 .dout(pdp_picl_wrapb[6]));

// PIC7
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic7     (
 .scan_in(pic7_scanin),
 .scan_out(pic7_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic_clken[7]         ),  // powerdown pin
 .din0( pdp_asi_din[63:0] ), 
 .din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
 .sel0( pct_wr_pic_w2[7] ),
 .dout( {pich7[31:0],picl7[31:0]}),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop) );

pmu_pdp_dp_cmp_macro__width_16 pic7hca  (
 .din0(pich7[31:16]),
 .din1(16'hffff),
 .dout(pdp_pich_wrapa[7]));
pmu_pdp_dp_cmp_macro__width_16 pic7lca  (
 .din0(picl7[31:16]),
 .din1(16'hffff),
 .dout(pdp_picl_wrapa[7]));

pmu_pdp_dp_cmp_macro__width_12 pic7hcb  (
 .din0(pich7[15:4]),
 .din1(12'hfff),
 .dout(pdp_pich_wrapb[7]));
pmu_pdp_dp_cmp_macro__width_12 pic7lcb  (
 .din0(picl7[15:4]),
 .din1(12'hfff),
 .dout(pdp_picl_wrapb[7]));

pmu_pdp_dp_and_macro__ports_2__width_16 pich0wrap   (
 .din0   ({pdp_pich_wrapa[7:0],pdp_picl_wrapa[7:0]}),
 .din1   ({pdp_pich_wrapb[7:0],pdp_picl_wrapb[7:0]}),
 .dout   ({pdp_pich_wrap[7:0], pdp_picl_wrap[7:0]}));

// Mux PIC's 0-7 together to share one incrementor & adder
// Mux in W1 cycle, increment in W2
pmu_pdp_dp_mux_macro__mux_aope__ports_8__width_64 pic07_mux  (
 .din0({pich0[31:0], picl0[31:0]}),
 .din1({pich1[31:0], picl1[31:0]}),
 .din2({pich2[31:0], picl2[31:0]}),
 .din3({pich3[31:0], picl3[31:0]}),
 .din4({pich4[31:0], picl4[31:0]}),
 .din5({pich5[31:0], picl5[31:0]}),
 .din6({pich6[31:0], picl6[31:0]}),
 .din7({pich7[31:0], picl7[31:0]}),
 .sel0(pct_incr_pic_w1[0]),
 .sel1(pct_incr_pic_w1[1]),
 .sel2(pct_incr_pic_w1[2]),
 .sel3(pct_incr_pic_w1[3]),
 .sel4(pct_incr_pic_w1[4]),
 .sel5(pct_incr_pic_w1[5]),
 .sel6(pct_incr_pic_w1[6]),
// .sel7(pct_incr_pic_w1[7]), // pct_incr_pic_w1 is guaranteed to be one-hot
 .dout({pich07_w1[31:0], picl07_w1[31:0]}));

// all 8 threads sharing two comparators
// not practical, as wrap must be matched with tid in the ctl logic
//cmp_macro pic07hc (width=28) (
// .din0(pich07_w1[31:4]),
// .din1(28'hfffffff),
// .dout(pdp_pich_wrap));

//cmp_macro pic07lc (width=28) (
// .din0(pich07_w1[31:4]),
// .din1(28'hfffffff),
// .dout(pdp_picl_wrap));

// send these two wrap signals to the ctl logic and qualify with pct_incr_pic_w1

pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic07_w2  (
 .scan_in(pic07_w2_scanin),
 .scan_out(pic07_w2_scanout),
 .clk ( l2clk                    ),
 .en  ( pct_pic07_w2_clken       ),  // powerdown pin
 .din0( pdp_asi_din[63:0]), 
 .din1( {pich07_w1[31:0], picl07_w1[31:0]} ),
 .sel0( pct_incr_asi_w1 ),
 .dout( {pich07_w2[31:0], picl07_w2[31:0]} ),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// PICH incrementor for PIC's 0-7
pmu_pdp_dp_cla_macro__width_32 pich07_cla  (
  .din0({28'b0, pct_pich07_add_w2[3:0]}),
  .din1(pich07_w2[31:0]),
  .cin(1'b0),
  .dout(pich07_incr[31:0]),
  .cout(pdp_pich_cout07)
);
 
pmu_pdp_dp_cla_macro__width_32 picl07_cla  (
  .din0({28'b0, pct_picl07_add_w2[3:0]}),
  .din1(picl07_w2[31:0]),
  .cin(1'b0),
  .dout(picl07_incr[31:0]),
  .cout(pdp_picl_cout07)
);
 
// 8:1 mux for ASR reads to mux between PICs

pmu_pdp_dp_mux_macro__mux_aonpe__ports_8__width_64 pic_mux  (
 .din0({pich0[31:0],picl0[31:0]}),
 .din1({pich1[31:0],picl1[31:0]}),
 .din2({pich2[31:0],picl2[31:0]}),
 .din3({pich3[31:0],picl3[31:0]}),
 .din4({pich4[31:0],picl4[31:0]}),
 .din5({pich5[31:0],picl5[31:0]}),
 .din6({pich6[31:0],picl6[31:0]}),
 .din7({pich7[31:0],picl7[31:0]}),
 .sel0(pct_rd_pic[0]),
 .sel1(pct_rd_pic[1]),
 .sel2(pct_rd_pic[2]),
 .sel3(pct_rd_pic[3]),
 .sel4(pct_rd_pic[4]),
 .sel5(pct_rd_pic[5]),
 .sel6(pct_rd_pic[6]),
 .sel7(pct_rd_pic[7]),
 .dout(pdp_pic_data[63:0]));

pmu_pdp_dp_mux_macro__mux_aope__ports_2__width_64 picpcr_mux  (
 .din0(pdp_pic_data[63:0]),
 .din1({32'b0, pct_pcr_data[31:0]}),
 .sel0(pct_rd_a_pic),
 .dout(picpcr_data[63:0]));

// ASI output registers
pmu_pdp_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 asi_dout  (
 .scan_in(asi_dout_scanin),
 .scan_out(asi_dout_scanout),
 .clk ( l2clk),
 .en  ( pmu_asi_clken            ),  // powerdown pin
 .din0( pdp_asi_din[63:0]), 
 .din1( picpcr_data[63:0]), 
 .din2({pdp_asi_din[63],1'b1,pdp_asi_din[61:56],6'b0,pct_exception,1'b0,pdp_asi_din[47:0]}),
 .sel0( pct_bypass_asi),
 .sel1( pct_rd_pic_pcr),
 .dout( pmu_rngl_cdbus_nobuf[63:0]),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

// Add buffer to drive FGU since aope muxes can't drive big loads well...
pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 rngl_out_buf     (
 .din (pmu_rngl_cdbus_nobuf[63:0]),
 .dout(pmu_rngl_cdbus[63:0]));


// fixscan start:
assign asi_din_scanin            = scan_in                  ;
assign pic0_scanin               = asi_din_scanout          ;
assign pic1_scanin               = pic0_scanout             ;
assign pic2_scanin               = pic1_scanout             ;
assign pic3_scanin               = pic2_scanout             ;
assign pic4_scanin               = pic3_scanout             ;
assign pic5_scanin               = pic4_scanout             ;
assign pic6_scanin               = pic5_scanout             ;
assign pic7_scanin               = pic6_scanout             ;
assign pic07_w2_scanin           = pic7_scanout             ;
assign asi_dout_scanin           = pic07_w2_scanout         ;
assign scan_out                  = asi_dout_scanout         ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pdp_dp_msff_macro__stack_64c__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module pmu_pdp_dp_cmp_macro__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output dout;


cmp #(16)  m0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module pmu_pdp_dp_cmp_macro__width_12 (
  din0, 
  din1, 
  dout);
  input [11:0] din0;
  input [11:0] din1;
  output dout;


cmp #(12)  m0_0 (
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout)
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module pmu_pdp_dp_and_macro__ports_2__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output [15:0] dout;


and2 #(16)  d0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module pmu_pdp_dp_mux_macro__mux_aope__ports_8__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;
  output [63:0] dout;


cl_dp1_penc8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   cla macro
//
//


module pmu_pdp_dp_cla_macro__width_32 (
  cin, 
  din0, 
  din1, 
  dout, 
  cout);
  input cin;
  input [31:0] din0;
  input [31:0] din1;
  output [31:0] dout;
  output cout;


cla #(32)  m0_0 (
.cin(cin),
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout[31:0]),
.cout(cout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module pmu_pdp_dp_mux_macro__mux_aonpe__ports_8__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;
  input [63:0] din5;
  input sel5;
  input [63:0] din6;
  input sel6;
  input [63:0] din7;
  input sel7;
  output [63:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module pmu_pdp_dp_mux_macro__mux_aope__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module pmu_pdp_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmo_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmo_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  ic_dmo_rd_data, 
  lsu_dc_data, 
  dmo_din, 
  dmo_coresel, 
  dmo_icmuxctl, 
  tcu_se_scancollar_out, 
  dmo_dout, 
  scan_out, 
  dmo_coresel_buff);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire dmo_icmuxctl_buff;
wire [35:0] dmo_din_buff;
wire dmo_flop_scanin;
wire dmo_flop_scanout;
wire [35:0] dmo_flop_dout;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;

input 	[32:0] 	ic_dmo_rd_data;
input 	[35:0] 	lsu_dc_data;

input 	[35:0]	dmo_din;		
input		dmo_coresel;
input		dmo_icmuxctl;

input		tcu_se_scancollar_out;

output 	[35:0]	dmo_dout;
output		scan_out;
output		dmo_coresel_buff; // for LSU

// scan renames
assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
//assign se	= tcu_se_scancollar_out;
//assign muxtst	= tcu_muxtest;
//assign test	= tcu_dectest;
// end scan

dmo_dpbuff_macro__rep_1__width_38 dmo_din_buf  (
  .din ({dmo_coresel, dmo_icmuxctl, dmo_din[35:0]}),
  .dout({dmo_coresel_buff, dmo_icmuxctl_buff, dmo_din_buff[35:0]})
  );

// Flop data from other core and this core
dmo_dpmsff_macro__mux_aope__ports_3__stack_64c__width_36	dmo_flop  (
  .scan_in(dmo_flop_scanin),
  .scan_out(dmo_flop_scanout),
  .clk ( l2clk					),
  .en  ( 1'b1					),
  .se  (tcu_se_scancollar_out			),
  .din0 ( dmo_din_buff[35:0]			),	// other core data
//  .din0 ( dmo_din[35:0]				),	// other core data
  .din1 ( {3'b0, ic_dmo_rd_data[32:0]}		),	// I$ data
  .din2 ( lsu_dc_data[35:0]			),	// D$ data
  .sel0 ( dmo_coresel_buff                    	),
  .sel1 ( dmo_icmuxctl_buff			),
  .dout( dmo_flop_dout[35:0]	),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop));

dmo_dpbuff_macro__dbuff_48x__rep_1__stack_none__width_36 dmo_dout_buf  (
  .din (dmo_flop_dout[35:0]),
  .dout(dmo_dout[35:0])
  );


// fixscan start:
assign dmo_flop_scanin           = scan_in                  ;
assign scan_out                  = dmo_flop_scanout         ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module dmo_dpbuff_macro__rep_1__width_38 (
  din, 
  dout);
  input [37:0] din;
  output [37:0] dout;


buff #(38)  d0_0 (
.in(din[37:0]),
.out(dout[37:0])
);


endmodule


// any PARAMS parms go into naming of macro

module dmo_dpmsff_macro__mux_aope__ports_3__stack_64c__width_36 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [35:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [34:0] so;

  input [35:0] din0;
  input [35:0] din1;
  input [35:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [35:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(36)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[35:0]),
  .in1(din1[35:0]),
  .in2(din2[35:0]),
.dout(muxout[35:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(36)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[35:0]),
.si({scan_in,so[34:0]}),
.so({so[34:0],scan_out}),
.q(dout[35:0])
);


endmodule


//
//   buff macro
//
//


module dmo_dpbuff_macro__dbuff_48x__rep_1__stack_none__width_36 (
  din, 
  dout);
  input [35:0] din;
  output [35:0] dout;


buff #(36)  d0_0 (
.in(din[35:0]),
.out(dout[35:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spc.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module spc (
  gclk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_clk_stop, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_scan_en, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  tcu_atpg_mode, 
  rst_wmr_protect, 
  scan_out, 
  tcu_shscan_pce_ov, 
  tcu_shscan_clk_stop, 
  tcu_shscan_aclk, 
  tcu_shscan_bclk, 
  tcu_shscan_scan_in, 
  tcu_shscan_scan_en, 
  tcu_shscanid, 
  spc_shscan_scan_out, 
  cluster_arst_l, 
  tcu_spc_mbist_scan_in, 
  tcu_mbist_bisi_en, 
  tcu_spc_mbist_start, 
  tcu_mbist_user_mode, 
  spc_mbist_fail, 
  spc_mbist_done, 
  spc_tcu_mbist_scan_out, 
  const_cpuid, 
  tcu_ss_mode, 
  tcu_do_mode, 
  tcu_ss_request, 
  ncu_cmp_tick_enable, 
  spc_ss_complete, 
  ncu_wmr_vec_mask, 
  spc_hardstop_request, 
  spc_softstop_request, 
  spc_trigger_pulse, 
  ncu_spc_pm, 
  ncu_spc_ba01, 
  ncu_spc_ba23, 
  ncu_spc_ba45, 
  ncu_spc_ba67, 
  efu_spc_fuse_data, 
  efu_spc_fuse_ixfer_en, 
  efu_spc_fuse_dxfer_en, 
  efu_spc_fuse_iclr, 
  efu_spc_fuse_dclr, 
  spc_efu_fuse_ddata, 
  spc_efu_fuse_idata, 
  spc_efu_fuse_ixfer_en, 
  spc_efu_fuse_dxfer_en, 
  vnw_ary0, 
  vnw_ary1, 
  tcu_spc_lbist_start, 
  tcu_spc_lbist_scan_in, 
  tcu_spc_lbist_pgm, 
  tcu_spc_test_mode, 
  spc_tcu_lbist_done, 
  spc_tcu_lbist_scan_out, 
  dmo_din, 
  dmo_coresel, 
  dmo_icmuxctl, 
  dmo_dcmuxctl, 
  dmo_dout, 
  ncu_spc_l2_idx_hash_en, 
  cpx_spc_data_cx, 
  pcx_spc_grant_px, 
  spc_pcx_req_pq, 
  spc_pcx_atm_pq, 
  spc_pcx_data_pa, 
  tcu_core_running, 
  spc_core_running_status, 
  power_throttle, 
  spc_dbg_instr_cmt_grp0, 
  spc_dbg_instr_cmt_grp1, 
  hver_mask_minor_rev, 
  ccu_slow_cmp_sync_en, 
  ccu_cmp_slow_sync_en);
wire lsu_scanin;
wire msf0_scanout;
wire l2clk;
wire lb_se_sc_out;
wire pce_ov_br;
wire lb_scan_en_br;
wire spc_aclk_br;
wire spc_bclk_br;
wire gkt_scanin;
wire msf1_scanout;
wire tcu_spc_lbist_scan_in_buf;
wire spc_tcu_lbist_scan_out_buf;
wire pce_ov_tr;
wire tcu_aclk_buf;
wire tcu_bclk_buf;
wire tcu_scan_en_buf;
wire tcu_se_scancollar_in_buf;
wire tcu_se_scancollar_out_buf;
wire tcu_array_wr_inhibit_buf;
wire tcu_spc_test_mode_buf;
wire [1:0] scan_in_buf;
wire [1:0] scan_out_buf;
wire tcu_spc_lbist_start_buf;
wire tcu_spc_lbist_pgm_buf;
wire lb_lbist_done;
wire lb_lbist_running;
wire wmr_protect_scanin;
wire dmo_scanin;
wire clk_spc_scanin;
wire mmu_scanin;
wire ifu_ibu_scanin;
wire ifu_ftu_scanin;
wire ifu_cmu_scanin;
wire dec_scanin;
wire pku_scanin;
wire exu0_scanin;
wire exu1_scanin;
wire tlu_scanin;
wire spu_scanin;
wire fgu_scanin;
wire mmu_wmr_scanout;
wire dmo_scanout;
wire clk_spc_scanout;
wire pmu_scanout;
wire ifu_ibu_scanout;
wire ifu_ftu_scanout;
wire ifu_cmu_scanout;
wire dec_scanout;
wire pku_scanout;
wire exu0_scanout;
wire exu1_scanout;
wire tlu_scanout;
wire lsu_scanout;
wire spu_scanout;
wire fgu_scanout;
wire gkt_scanout;
wire lb_mb_channel_si;
wire mb2_scanout;
wire tcu_spc_mbist_scan_in_buf;
wire spc_tcu_mbist_scan_out_buf;
wire lb_aclk;
wire lb_bclk;
wire lb_scan_en;
wire lb_se_sc_in;
wire lb_clk_stop;
wire lb_array_wr_inhibit;
wire lb_scan_en_wmr;
wire spc_aclk;
wire spc_aclk_wmr;
wire clk_array_wr_inhibit;
wire spc_bclk;
wire cluster_arst_l_buf;
wire cmp_slow_sync_en;
wire pce_ov;
wire por_unused;
wire rst_wmr_protect_buf;
wire slow_cmp_sync_en;
wire tcu_pce_ov_buf;
wire msf0_atpg_mode_buf;
wire wmr_unused;
wire [3:0] dcc_dmo_parity;
wire [63:0] lsu_exu_ld_data_b;
wire [39:4] mmu_l15_addr;
wire [4:0] mmu_l15_cpkt;
wire [38:3] spu_l15_addr;
wire [12:0] spu_l15_cpkt;
wire [63:0] spu_l15_data;
wire exu1_wmr_scanout;
wire fgu_wmr_scanout;
wire spc_aclk_tr;
wire spc_aclk_wmr_tr;
wire spc_bclk_tr;
wire lb_scan_en_tr;
wire tcu_dectest_buf;
wire tcu_muxtest_buf;
wire exu_fgu_fmov_vld_m;
wire dec_spu_grant_fgu_d;
wire [7:0] tlu_core_running_status;
wire [64:0] pmu_rngl_cdbus;
wire [64:0] fgu_rngl_cdbus;
wire [63:0] lsu_fgu_fld_data_b;
wire [63:0] exu_fgu_rs1_e;
wire [63:0] exu_fgu_rs2_e;
wire [63:0] spu_fgu_rs1_e;
wire [63:0] spu_fgu_rs2_e;
wire [9:0] mb2_addr;
wire mb2_run;
wire [7:0] mb2_write_data;
wire mb2_frf_read_en;
wire mb2_frf_write_en;
wire pce_ov_bl;
wire lb_scan_en_bl;
wire spc_aclk_bl;
wire spc_bclk_bl;
wire lsu_cpx_valid;
wire lsu_wmr_scanout;
wire ifu_ftu_wmr_scanout;
wire spc_aclk_wmr_bl;
wire mb0_run;
wire mb0_ict_write_en;
wire mb0_ict_read_en;
wire mb0_icd_write_en;
wire mb0_icd_read_en;
wire mb0_icv_write_en;
wire mb0_icv_read_en;
wire mb0_itb_write_en;
wire mb0_itb_read_en;
wire [11:0] mb0_addr;
wire [7:0] mb0_write_data;
wire [2:0] mb0_cmpsel;
wire [47:0] exu_address0_e_rep01;
wire [47:0] exu_address1_e_rep01;
wire tlu_trap_pc_0_valid;
wire tlu_trap_pc_1_valid;
wire [47:0] tlu_trap_pc_0;
wire [47:0] tlu_trap_pc_1;
wire [47:2] tlu_npc_w;
wire [64:0] lsu_rngl_cdbus;
wire [64:0] ifu_rngl_cdbus;
wire cmu_inst3_v;
wire cmu_inst2_v;
wire cmu_inst1_v;
wire cmu_inst0_v;
wire efu_spc_fuse_data_buf;
wire efu_spc_fuse_ixfer_en_buf;
wire efu_spc_fuse_iclr_buf;
wire spc_efu_fuse_ixfer_en_buf;
wire spc_efu_fuse_idata_buf;
wire [17:0] lsu_cpx_cpkt;
wire [127:0] lsu_cpx_data;
wire mmu_dtlb_reload_stall;
wire [2:0] power_throttle_buf;
wire lsu_frf_read_pending;
wire msf0_do_mode;
wire [1:0] dec_br_taken_e1;
wire [7:0] tlu_spec_enable;
wire exu0_wmr_scanout;
wire [7:0] del_pick_d;
wire [1:0] dec_tid0_p;
wire dec_inst0_rs1_vld_p;
wire dec_inst0_rs2_vld_p;
wire dec_inst0_rs3_vld_p;
wire [4:0] dec_inst0_rs1_p;
wire [4:0] dec_inst0_rs2_p;
wire [4:0] dec_inst0_rs3_p;
wire [1:0] dec_exu_clken;
wire [32:0] dec_inst0_d;
wire [4:0] dec_inst0_rd_d;
wire dec_decode0_d;
wire [1:0] dec_valid_e;
wire [1:0] dec_flush_m;
wire [1:0] dec_flush_b;
wire [63:0] fgu_exu_result_fx5_rep1;
wire [1:0] fgu_exu_w_vld_fx5;
wire [47:2] tlu_pc_0_d;
wire [1:0] tlu_itlb_bypass_e;
wire [1:0] tlu_flush_exu_b;
wire [7:0] tlu_ccr_0;
wire [2:0] tlu_cwp_0;
wire tlu_ccr_cwp_0_valid;
wire [1:0] tlu_ccr_cwp_0_tid;
wire [7:0] tlu_pstate_am;
wire [1:0] tlu_gl0;
wire [1:0] tlu_gl1;
wire [1:0] tlu_gl2;
wire [1:0] tlu_gl3;
wire tlu_cerer_irf;
wire [7:0] tlu_ceter_pscce;
wire [7:0] mb2_write_data_p1;
wire mb2_irf_write_en;
wire mb2_irf_read_en;
wire mb2_irf_save_en;
wire mb2_irf_restore_en;
wire [31:0] lsu_asi_error_inject;
wire [63:0] lsu_exu_ld_data_b_rep00;
wire [64:0] exu0_rngl_cdbus;
wire [47:0] exu_address0_e;
wire [5:0] exu0_mdp_mux_sel_e;
wire exu_ms_icc0_e;
wire [63:0] exu_rs1_data0_e;
wire [63:0] exu_rs2_data0_e;
wire [63:0] exu_store_data0_e;
wire [3:0] exu0_oddwin_b;
wire [1:0] exu_cecc_m;
wire [1:0] exu_uecc_m;
wire [1:0] exu_misalign_m;
wire [1:0] exu_oor_va_m;
wire [1:0] exu_tcc_m;
wire [1:0] exu_tof_m;
wire [7:0] exu0_trap_number_b;
wire [1:0] exu_spill_b;
wire [1:0] exu_fill_m;
wire [1:0] exu_normal_b;
wire [1:0] exu_cleanwin_b;
wire [2:0] exu0_wstate_b;
wire [7:0] exu0_ccr0;
wire [7:0] exu0_ccr1;
wire [7:0] exu0_ccr2;
wire [7:0] exu0_ccr3;
wire [1:0] exu_ecc_m;
wire [7:0] exu0_ecc_check_m;
wire [4:0] exu0_ecc_addr_m;
wire [31:0] exu_gsr_data0_m;
wire [1:0] exu_gsr_vld0_m;
wire [1:0] exu_cmov_true_m;
wire [1:0] dec_br_taken_e;
wire [1:0] exu_ibp_m;
wire [1:0] exu_lsu_va_error_m;
wire [31:0] exu_y_data0_e;
wire [2:0] exu0_cwp0;
wire [2:0] exu0_cwp1;
wire [2:0] exu0_cwp2;
wire [2:0] exu0_cwp3;
wire exu0_window_block;
wire [1:0] exu_tlu_window_block;
wire [1:0] exu_ecc_winop_flush_m;
wire exu_test_valid0;
wire [1:0] exu_test_tid0;
wire [4:0] exu_test_addr0;
wire [1:0] exu0_mbi_irf_fail_;
wire [1:0] dec_tid1_p;
wire dec_inst1_rs1_vld_p;
wire dec_inst1_rs2_vld_p;
wire dec_inst1_rs3_vld_p;
wire [4:0] dec_inst1_rs1_p;
wire [4:0] dec_inst1_rs2_p;
wire [4:0] dec_inst1_rs3_p;
wire [32:0] dec_inst1_d;
wire [4:0] dec_inst1_rd_d;
wire dec_decode1_d;
wire [63:0] fgu_exu_result_fx5_rep0;
wire [47:2] tlu_pc_1_d;
wire [7:0] tlu_ccr_1;
wire [2:0] tlu_cwp_1;
wire tlu_ccr_cwp_1_valid;
wire [1:0] tlu_ccr_cwp_1_tid;
wire [1:0] tlu_gl4;
wire [1:0] tlu_gl5;
wire [1:0] tlu_gl6;
wire [1:0] tlu_gl7;
wire [63:0] lsu_exu_ld_data_b_rep01;
wire [64:0] exu1_rngl_cdbus;
wire [47:0] exu_address1_e;
wire [5:0] exu1_mdp_mux_sel_e;
wire exu_ms_icc1_e;
wire [63:0] exu_rs1_data1_e;
wire [63:0] exu_rs2_data1_e;
wire [63:0] exu_store_data1_e;
wire [3:0] exu1_oddwin_b;
wire [7:0] exu1_trap_number_b;
wire [2:0] exu1_wstate_b;
wire [7:0] exu1_ccr0;
wire [7:0] exu1_ccr1;
wire [7:0] exu1_ccr2;
wire [7:0] exu1_ccr3;
wire [7:0] exu1_ecc_check_m;
wire [4:0] exu1_ecc_addr_m;
wire [31:0] exu_gsr_data1_m;
wire [1:0] exu_gsr_vld1_m;
wire [31:0] exu_y_data1_e;
wire [2:0] exu1_cwp0;
wire [2:0] exu1_cwp1;
wire [2:0] exu1_cwp2;
wire [2:0] exu1_cwp3;
wire exu1_window_block;
wire exu_test_valid1;
wire [1:0] exu_test_tid1;
wire [4:0] exu_test_addr1;
wire [1:0] exu1_mbi_irf_fail_;
wire tlu_wmr_scanout;
wire pce_ov_tl;
wire lb_scan_en_tl;
wire spc_aclk_tl;
wire spc_aclk_wmr_tl;
wire spc_bclk_tl;
wire [3:0] hver_mask_minor_rev_buf;
wire msf0_cmp_tick_enable;
wire msf0_ss_mode;
wire msf0_ss_request;
wire msf0_wmr_vec_mask;
wire [47:0] exu_address0_e_rep0;
wire [47:0] exu_address1_e_rep0;
wire fgu_cecc_fx2_rep1;
wire fgu_uecc_fx2_rep1;
wire l15_mmu_valid;
wire [17:0] l15_spc_cpkt;
wire [127:0] l15_spc_data1;
wire mb1_tsa0_write_en;
wire mb1_tsa1_write_en;
wire mb1_tca_write_en;
wire [7:0] mb1_addr;
wire mb1_run;
wire [7:0] mb1_write_data;
wire mb1_tsa0_read_en;
wire mb1_tsa1_read_en;
wire mb1_tca_read_en;
wire [4:0] mb1_cmpsel;
wire [7:0] dec_block_store_b;
wire [64:0] lsu_rngf_cdbus;
wire [47:0] lsu_mmu_va_b;
wire [3:0] spu_pmu_ma_busy;
wire spc_shscan_scan_out_buf;
wire tcu_shscan_pce_ov_buf;
wire msf0_shscan_clk_stop;
wire tcu_shscan_aclk_buf;
wire tcu_shscan_bclk_buf;
wire tcu_shscan_scan_en_buf;
wire tcu_shscan_scan_in_buf;
wire [2:0] msf0_shscanid;
wire [7:0] msf0_core_running;
wire dmo_coresel_buff;
wire dmo_dcmuxctl_buf;
wire spc_aclk_wmr_br;
wire [63:0] fgu_lsu_fst_data_fx1;
wire [145:0] cpx_spc_data_cx_rep0;
wire [64:0] tlu_rngf_cdbus;
wire mb0_dca_read_en;
wire mb0_dca_write_en;
wire mb0_dta_read_en;
wire mb0_dta_write_en;
wire mb0_dva_read_en;
wire mb0_dva_write_en;
wire mb0_lru_read_en;
wire mb0_lru_write_en;
wire mb0_dtb_read_en;
wire mb0_dtb_write_en;
wire mb0_stb_cam_read_en;
wire mb0_stb_cam_write_en;
wire mb0_stb_ram_read_en;
wire mb0_stb_ram_write_en;
wire mb0_cpq_read_en;
wire mb0_cpq_write_en;
wire efu_spc_fuse_dxfer_en_buf;
wire efu_spc_fuse_dclr_buf;
wire spc_efu_fuse_ddata_buf;
wire spc_efu_fuse_dxfer_en_buf;
wire [63:0] fgu_mul_result_fx5;
wire dec_spu_grant_d_rep0;
wire [64:0] spu_rngl_cdbus;
wire l15_spu_valid;
wire [7:0] mb2_write_data_p2;
wire mb2_arf_read_en;
wire mb2_arf_write_en;
wire mb2_mam_read_en;
wire mb2_mam_write_en;
wire mb2_rrf_read_en;
wire mb2_rrf_write_en;
wire mmu_scanout;
wire mb1_mra0_write_en;
wire mb1_mra1_write_en;
wire mb1_scp0_write_en;
wire mb1_scp1_write_en;
wire mb1_mra0_read_en;
wire mb1_mra1_read_en;
wire mb1_scp0_read_en;
wire mb1_scp1_read_en;
wire dec_valid0_d;
wire [1:0] dec_tid0_d;
wire [9:0] dec_instr0_type_d;
wire dec_valid1_d;
wire [1:0] dec_tid1_d;
wire [9:0] dec_instr1_type_d;
wire [1:0] dec_pmu_valid_e;
wire [2:0] lsu_dcerr_tid_g;
wire [2:0] lsu_pmu_mem_type_b;
wire mb0_scanin;
wire mb0_scanout;
wire tcu_spc_mbist_start_buf0;
wire msf0_mbist_user_mode_ff;
wire msf0_mbist_bisi_en_ff;
wire mb2_mb0_fail;
wire mb1_mb0_fail;
wire mb2_mb0_done;
wire mb1_mb0_done;
wire spc_mbist_fail_buf;
wire spc_mbist_done_buf;
wire [15:12] mb0_addr_unused;
wire mb1_scanin;
wire mb1_scanout;
wire [15:8] mb1_addr_unused;
wire mb2_scanin;
wire [15:10] mb2_addr_unused;
wire [63:0] fgu_exu_result_fx5;
wire fgu_cecc_fx2;
wire fgu_uecc_fx2;
wire tcu_spc_mbist_start_ff;
wire spc_mbist_fail_ff;
wire spc_mbist_done_ff;
wire [32:0] ftu_instr_0_c;
wire [32:0] ftu_instr_1_c;
wire [32:0] ftu_instr_2_c;
wire [32:0] ftu_instr_3_c;
wire [4:0] ftu_instr_exceptions_c;
wire [32:0] ftu_instr_0_c_rep0;
wire [32:0] ftu_instr_0_c_rep1;
wire [32:0] ftu_instr_0_c_rep2;
wire [32:0] ftu_instr_0_c_rep3;
wire [32:0] ftu_instr_1_c_rep0;
wire [32:0] ftu_instr_1_c_rep1;
wire [32:0] ftu_instr_1_c_rep2;
wire [32:0] ftu_instr_1_c_rep3;
wire [32:0] ftu_instr_2_c_rep0;
wire [32:0] ftu_instr_2_c_rep1;
wire [32:0] ftu_instr_2_c_rep2;
wire [32:0] ftu_instr_2_c_rep3;
wire [32:0] ftu_instr_3_c_rep0;
wire [32:0] ftu_instr_3_c_rep1;
wire [32:0] ftu_instr_3_c_rep2;
wire [32:0] ftu_instr_3_c_rep3;
wire [4:0] ftu_instr_0_exceptions_c_rep0;
wire [4:0] ftu_instr_0_exceptions_c_rep1;
wire [4:0] ftu_instr_0_exceptions_c_rep2;
wire [4:0] ftu_instr_0_exceptions_c_rep3;
wire [4:0] ftu_instr_1_exceptions_c_rep0;
wire [4:0] ftu_instr_1_exceptions_c_rep1;
wire [4:0] ftu_instr_1_exceptions_c_rep2;
wire [4:0] ftu_instr_1_exceptions_c_rep3;
wire [4:0] ftu_instr_2_exceptions_c_rep0;
wire [4:0] ftu_instr_2_exceptions_c_rep1;
wire [4:0] ftu_instr_2_exceptions_c_rep2;
wire [4:0] ftu_instr_2_exceptions_c_rep3;
wire [4:0] ftu_instr_3_exceptions_c_rep0;
wire [4:0] ftu_instr_3_exceptions_c_rep1;
wire [4:0] ftu_instr_3_exceptions_c_rep2;
wire [4:0] ftu_instr_3_exceptions_c_rep3;
wire dec_spu_grant_d;
wire tlu_ss_complete;
wire tlu_hardstop_request;
wire tlu_softstop_request;
wire tlu_trigger_pulse;
wire [1:0] tlu_dbg_instr_cmt_grp0;
wire [1:0] tlu_dbg_instr_cmt_grp1;
wire wmr_protect;
wire core_isolate;
wire [32:0] ic_dmo_rd_data;
wire lsu_gkt_pmen;
wire ifu_l15_valid;
wire mmu_l15_valid;
wire lsu_l15_valid;
wire spu_l15_valid;
wire lsu_l15_lock;
wire [39:0] ifu_l15_addr;
wire [39:0] lsu_l15_addr;
wire [7:0] ifu_l15_cpkt;
wire [25:0] lsu_l15_cpkt;
wire [63:0] lsu_l15_data;
wire l15_ifu_grant;
wire l15_mmu_grant;
wire l15_lsu_grant;
wire l15_spu_grant;
wire [3:0] gkt_ifu_legal;
wire [3:0] gkt_ifu_flip_parity;
wire [6:0] l15_pmu_xbar_optype;
wire [4:0] dec_frf_r1_addr_d;
wire [4:0] dec_frf_r2_addr_d;
wire dec_frf_r1_vld_d;
wire dec_frf_r2_vld_d;
wire dec_frf_r1_32b_d;
wire dec_frf_r2_32b_d;
wire dec_frf_r1_odd32b_d;
wire dec_frf_r2_odd32b_d;
wire dec_frf_w_vld_d;
wire [4:0] dec_frf_w_addr_d;
wire dec_frf_w_32b_d;
wire dec_frf_w_odd32b_d;
wire dec_exu_src_vld_d;
wire [4:0] dec_irf_w_addr_d;
wire dec_frf_store_d;
wire dec_fsr_store_d;
wire [5:0] dec_fgu_op3_d;
wire [7:0] dec_fgu_opf_d;
wire dec_fgu_decode_d;
wire dec_fgu_valid_e;
wire [2:0] dec_fgu_tid_d;
wire dec_flush_f1;
wire dec_flush_f2;
wire [1:0] fgu_cmp_fcc_fx3;
wire [3:0] fgu_cmp_fcc_vld_fx3;
wire [2:0] fgu_cmp_fcc_tid_fx2;
wire [7:0] fgu_fld_fcc_fx3;
wire [1:0] fgu_fld_fcc_vld_fx3;
wire [7:0] fgu_fprs_fef;
wire fgu_fdiv_stall;
wire [1:0] fgu_idiv_stall;
wire [7:0] fgu_divide_completion;
wire tlu_flush_fgu_b;
wire tlu_cerer_frf;
wire fgu_predict_fx2;
wire fgu_pdist_beat2_fx1;
wire [5:0] fgu_ecc_addr_fx2;
wire [13:0] fgu_ecc_check_fx2;
wire fgu_fpx_ieee_trap_fw;
wire fgu_fpd_ieee_trap_fw;
wire fgu_fpx_unfin_fw;
wire fgu_fpd_unfin_fw;
wire fgu_fpd_idiv0_trap_fw;
wire [2:0] fgu_fpx_trap_tid_fw;
wire [2:0] fgu_fpd_trap_tid_fw;
wire [4:0] lsu_fgu_fld_addr_b;
wire lsu_fgu_fld_vld_w;
wire lsu_fgu_fld_b;
wire [2:0] lsu_fgu_fld_tid_b;
wire lsu_fgu_fld_32b_b;
wire lsu_fgu_fld_odd32b_b;
wire lsu_fgu_fsr_load_b;
wire lsu_fgu_exception_w;
wire lsu_block_store_m;
wire lsu_fgu_pmen;
wire lsu_asi_clken;
wire fgu_fst_ecc_error_fx2;
wire [31:0] exu_fgu_gsr_m;
wire [1:0] exu_fgu_gsr_vld_m;
wire exu_fgu_flush_m;
wire [3:0] fgu_exu_icc_fx5;
wire [1:0] fgu_exu_xcc_fx5;
wire fgu_exu_cc_vld_fx5;
wire [1:0] fgu_result_tid_fx5;
wire [4:0] fgu_irf_w_addr_fx5;
wire [6:0] spu_fgu_fpy_ctl_d;
wire fgu_accum_b0_fx5;
wire fgu_mbi_frf_fail;
wire [7:0] pku_flush_buffer0;
wire [7:0] pku_flush_upper_buffer;
wire [7:0] ftu_fetch_thr_c;
wire [7:0] pku_pick_p;
wire ftu_exception_valid_c;
wire ftu_instr_sf_valid_c;
wire [7:0] ftu_ibu_redirect_bf;
wire ftu_ic_no_err_c;
wire ftu_bus_0_is_first;
wire ftu_bus_1_is_first;
wire ftu_bus_2_is_first;
wire ftu_bus_3_is_first;
wire [3:0] ftu_instr_valid_c;
wire lsu_ifu_ibu_pmen;
wire [7:0] ftu_buffer_wr_en_f;
wire [7:0] ifu_buf0_valid_p;
wire [7:0] ifu_upper_buffer_valid_p;
wire [7:0] ibu_empty;
wire [7:0] ibu_room_4ormore;
wire [32:0] ifu_buf0_inst0;
wire [32:0] ifu_buf0_inst1;
wire [32:0] ifu_buf0_inst2;
wire [32:0] ifu_buf0_inst3;
wire [32:0] ifu_buf0_inst4;
wire [32:0] ifu_buf0_inst5;
wire [32:0] ifu_buf0_inst6;
wire [32:0] ifu_buf0_inst7;
wire [4:0] ifu_buf0_excp0;
wire [4:0] ifu_buf0_excp1;
wire [4:0] ifu_buf0_excp2;
wire [4:0] ifu_buf0_excp3;
wire [4:0] ifu_buf0_excp4;
wire [4:0] ifu_buf0_excp5;
wire [4:0] ifu_buf0_excp6;
wire [4:0] ifu_buf0_excp7;
wire mbi_cambist_run;
wire mbi_cambist_shift;
wire mbi_dis_clr_ubit;
wire mbi_init_to_zero;
wire mbi_itb_cam_en_pre;
wire mbi_repl_write;
wire mbi_itb_demap_en;
wire [1:0] mbi_demap_type;
wire ftu_mbi_tlb_data_cmp;
wire ftu_mbi_tlb_cam_hit;
wire ftu_mbi_tlb_cam_mhit;
wire ftu_mbi_tlb_ctxt0_hit;
wire ftu_mbi_tlb_valid;
wire ftu_mbi_tlb_used;
wire lsu_ifu_direct_map;
wire ftu_mbi_ict_fail;
wire ftu_mbi_icd_fail;
wire ftu_mbi_itb_fail;
wire ftu_mbi_icv_fail;
wire [1:0] tlu_retry;
wire [7:0] tlu_ifu_hpstate_hpriv;
wire [7:0] tlu_ifu_pstate_priv;
wire [1:0] tlu_ifu_invalidate;
wire [39:0] cmu_fill_paddr;
wire [7:0] cmu_inval_ack;
wire [1:0] cmu_l2_err;
wire cmu_l2miss;
wire tlu_cerer_ittp;
wire tlu_cerer_itdp;
wire tlu_cerer_ittm;
wire tlu_cerer_icl2c;
wire tlu_cerer_icl2u;
wire tlu_cerer_icl2nd;
wire tlu_cerer_icvp;
wire tlu_cerer_ictp;
wire tlu_cerer_ictm;
wire cmu_icache_invalidate;
wire cmu_evic_invalidate;
wire [2:0] cmu_icache_invalidate_way;
wire [2:0] cmu_icache_inv_way1;
wire [10:5] cmu_icache_invalidate_index;
wire [1:0] dec_load_flush_w;
wire [1:0] tlu_trap_0_tid;
wire [1:0] tlu_trap_1_tid;
wire [7:0] tlu_flush_ifu;
wire [1:0] tlu_itlb_reload;
wire [7:0] tlu_itlb_bypass;
wire [7:0] tlu_tl_gt_0;
wire [7:0] cmu_null_st;
wire [7:0] cmu_dupmiss_st;
wire [7:0] cmu_rst_dupmiss;
wire cmu_any_un_cacheable;
wire cmu_any_data_ready;
wire cmu_thr0_data_ready;
wire cmu_thr1_data_ready;
wire cmu_thr2_data_ready;
wire cmu_thr3_data_ready;
wire cmu_thr4_data_ready;
wire cmu_thr5_data_ready;
wire cmu_thr6_data_ready;
wire cmu_thr7_data_ready;
wire [32:0] cmu_fill_inst0;
wire [32:0] cmu_fill_inst1;
wire [32:0] cmu_fill_inst2;
wire [32:0] cmu_fill_inst3;
wire [7:0] lsu_ic_enable;
wire [7:0] lsu_ifu_no_miss;
wire [12:0] lsu_ifu_ctxt_data;
wire [2:0] lsu_ifu_tid_w;
wire lsu_ifu_wr_p0ctxt;
wire lsu_ifu_wr_p1ctxt;
wire lsu_ifu_wr_pid;
wire [7:0] lsu_immu_enable;
wire lsu_ifu_ftu_pmen;
wire lsu_ic_pmen;
wire [2:0] cmu_fill_wrway;
wire [263:0] cmu_ic_data;
wire [6:0] mmu_index;
wire [2:0] ftu_rep_way;
wire [39:0] ftu_paddr;
wire [7:0] ftu_curr_fetch_thr_f;
wire [7:0] ftu_ifu_quiesce;
wire [7:0] ifu_ibuffer_write_c;
wire [2:0] ftu_excp_way_d;
wire [2:0] ftu_excp_tid_d;
wire ftu_excp_way_valid_d;
wire ftu_thrx_un_cacheable;
wire ftu_agc_thr0_cmiss_c;
wire ftu_agc_thr1_cmiss_c;
wire ftu_agc_thr2_cmiss_c;
wire ftu_agc_thr3_cmiss_c;
wire ftu_agc_thr4_cmiss_c;
wire ftu_agc_thr5_cmiss_c;
wire ftu_agc_thr6_cmiss_c;
wire ftu_agc_thr7_cmiss_c;
wire ftu_thr0_inv_req_c;
wire ftu_thr1_inv_req_c;
wire ftu_thr2_inv_req_c;
wire ftu_thr3_inv_req_c;
wire ftu_thr4_inv_req_c;
wire ftu_thr5_inv_req_c;
wire ftu_thr6_inv_req_c;
wire ftu_thr7_inv_req_c;
wire ftu_thr0_redirect_bf;
wire ftu_thr1_redirect_bf;
wire ftu_thr2_redirect_bf;
wire ftu_thr3_redirect_bf;
wire ftu_thr4_redirect_bf;
wire ftu_thr5_redirect_bf;
wire ftu_thr6_redirect_bf;
wire ftu_thr7_redirect_bf;
wire lsu_ifu_cmu_pmen;
wire [10:5] lsu_ifu_ld_index;
wire ifu_lsu_if_vld;
wire [2:0] ifu_lsu_if_tid;
wire [10:5] ifu_lsu_if_addr;
wire lsu_dec_pmen;
wire lsu_exu_pmen;
wire tlu_cerer_icdp;
wire [7:0] tlu_dec_pstate_pef;
wire [7:0] tlu_dec_hpstate_hpriv;
wire [7:0] tlu_dec_pstate_priv;
wire [1:0] tlu_window_block;
wire lsu_cpq_stall;
wire [7:0] pku_load_flush_w;
wire [1:0] pku_inst_cnt_brtaken00;
wire [1:0] pku_inst_cnt_brtaken01;
wire [1:0] pku_inst_cnt_brtaken02;
wire [1:0] pku_inst_cnt_brtaken03;
wire [1:0] pku_inst_cnt_brtaken04;
wire [1:0] pku_inst_cnt_brtaken05;
wire [1:0] pku_inst_cnt_brtaken06;
wire [1:0] pku_inst_cnt_brtaken07;
wire [1:0] pku_inst_cnt_brtaken10;
wire [1:0] pku_inst_cnt_brtaken11;
wire [1:0] pku_inst_cnt_brtaken12;
wire [1:0] pku_inst_cnt_brtaken13;
wire [1:0] pku_inst_cnt_brtaken14;
wire [1:0] pku_inst_cnt_brtaken15;
wire [1:0] pku_inst_cnt_brtaken16;
wire [1:0] pku_inst_cnt_brtaken17;
wire [7:0] pku_base_pick_p;
wire [3:0] pku_raw_pick0_p;
wire [7:4] pku_raw_pick1_p;
wire [7:0] pku_annul_ds_dcti_brtaken0_e;
wire [7:0] pku_annul_ds_dcti_brtaken1_e;
wire [7:0] pku_valid_e;
wire [7:0] pku_ds_e;
wire [7:0] pku_lsu_p;
wire [7:0] pku_fgu_p;
wire [7:0] pku_pdist_p;
wire [7:0] pku_twocycle_p;
wire [7:0] pku_idest_p;
wire [7:0] pku_fdest_p;
wire [7:0] pku_fsrc_rd_p;
wire [7:0] pku_isrc_rs1_p;
wire [7:0] pku_isrc_rs2_p;
wire [7:0] pku_isrc_rd_p;
wire [7:0] pku_flush_f1;
wire [7:0] pku_flush_f2;
wire [7:0] pku_flush_lm;
wire [7:0] pku_flush_lb;
wire [7:0] pku_flush_m;
wire [7:0] pku_flush_b;
wire spu_mult_request;
wire lsu_block_store_stall;
wire [4:3] lsu_block_store_rd;
wire [2:0] lsu_block_store_tid;
wire dec_rs1_addr0_e;
wire dec_rs1_addr1_e;
wire [1:0] dec_true_valid_e;
wire [7:0] dec_raw_pick_p;
wire dec_flush_lm;
wire dec_flush_lb;
wire [4:0] dec_exc0_m;
wire [4:0] dec_exc1_m;
wire [1:0] dec_inst0_cnt;
wire [1:0] dec_inst1_cnt;
wire [1:0] dec_tid0_m;
wire [1:0] dec_tid1_m;
wire [1:0] dec_inst_valid_m;
wire [1:0] dec_lsu_inst_m;
wire [1:0] dec_fgu_inst_m;
wire [1:0] dec_cti_inst_m;
wire [1:0] dec_illegal_inst_m;
wire [1:0] dec_icache_perr_m;
wire [1:0] dec_priv_exc_m;
wire [1:0] dec_hpriv_exc_m;
wire [1:0] dec_fpdisable_exc_m;
wire [1:0] dec_br_taken_m;
wire [1:0] dec_done_inst_m;
wire [1:0] dec_retry_inst_m;
wire [1:0] dec_sir_inst_m;
wire [1:0] dec_annul_ds_m;
wire [1:0] dec_ds_m;
wire [1:0] dec_fgu_sel_e;
wire [1:0] dec_fgu_sel_m;
wire dec_lsu_sel0_e;
wire dec_lsu_sel1_e;
wire dec_lsu_sel0_lower_e;
wire dec_lsu_sel1_lower_e;
wire dec_lsu_sel0_upper_e;
wire dec_lsu_sel1_upper_e;
wire dec_rs1_addr0_upper_e;
wire dec_rs1_addr1_upper_e;
wire dec_ld_inst_e;
wire dec_st_inst_e;
wire dec_fsr_ldst_e;
wire dec_fpldst_inst_e;
wire dec_ldst_dbl_e;
wire dec_pref_inst_e;
wire dec_flush_inst_e;
wire dec_memstbar_inst_e;
wire [1:0] dec_ldst_sz_e;
wire [4:3] dec_frf_r2_addr_e;
wire dec_sr_inst_e;
wire dec_pr_inst_e;
wire dec_hpr_inst_e;
wire dec_casa_inst_e;
wire dec_ldstub_inst_e;
wire dec_swap_inst_e;
wire dec_altspace_d;
wire dec_sign_ext_e;
wire [4:0] dec_sraddr_e;
wire dec_imm_asi_vld_d;
wire [7:0] dec_imm_asi_d;
wire [1:0] dec_lsu_tid0_d;
wire [1:0] dec_lsu_tid1_d;
wire dec_lsu_tg_d;
wire [4:0] dec_lsu_rd_e;
wire dec_ld_inst_d;
wire dec_lsu_sel0_d;
wire [1:0] dec_ierr_d;
wire [7:0] dec_block_store_stall;
wire [7:0] tlu_halted;
wire lsu_pku_pmen;
wire [7:0] tlu_retry_state;
wire [7:0] lsu_sync;
wire [7:0] lsu_complete;
wire [7:0] lsu_stb_alloc;
wire [7:0] lsu_stb_dealloc;
wire [7:0] lsu_block_store_kill;
wire [7:0] pku_quiesce;
wire lsu_exu_ld_b;
wire [4:0] lsu_exu_rd_m;
wire [2:0] lsu_exu_tid_m;
wire lsu_exu_ld_vld_w;
wire [47:13] lsu_exu_address_e;
wire lsu_sel_lsu_addr_e;
wire [47:0] exu_lsu_address_e;
wire [63:0] exu_lsu_store_data_e;
wire [7:0] exu_lsu_rs2_e;
wire lsu_tlu_pmen;
wire lsu_lddf_align_b;
wire lsu_stdf_align_b;
wire lsu_illegal_inst_b;
wire lsu_daccess_prot_b;
wire lsu_priv_action_b;
wire lsu_va_watchpoint_b;
wire lsu_pa_watchpoint_b;
wire lsu_align_b;
wire lsu_tlb_miss_b_;
wire lsu_dae_invalid_asi_b;
wire lsu_dae_nc_page_b;
wire lsu_dae_nfo_page_b;
wire lsu_dae_priv_viol_b;
wire lsu_dae_so_page;
wire lsu_priv_action_g;
wire [2:0] lsu_tid_g;
wire [7:0] lsu_trap_flush;
wire lsu_tlb_bypass_b;
wire lsu_tlb_real_b;
wire lsu_sync_inst_b;
wire [7:0] lsu_stb_empty;
wire lsu_tlu_twocycle_m;
wire lsu_dcmh_err_g;
wire lsu_dcvp_err_g;
wire lsu_dctp_err_g;
wire lsu_dcdp_err_g;
wire lsu_dcl2c_err_g;
wire lsu_dcl2u_err_g;
wire lsu_dcl2nd_err_g;
wire lsu_dcsoc_err_g;
wire [8:0] lsu_dcerr_sfar_g;
wire lsu_sbdlc_err_g;
wire lsu_sbdlu_err_g;
wire lsu_sbdpc_err_g;
wire lsu_sbdpu_err_g;
wire lsu_sbapp_err_g;
wire lsu_sbdiou_err_g;
wire [2:0] lsu_stberr_tid_g;
wire [2:0] lsu_stberr_index_g;
wire [1:0] lsu_stberr_priv_g;
wire lsu_stb_flush_g;
wire lsu_dttp_err_b;
wire lsu_dtdp_err_b;
wire lsu_dtmh_err_b;
wire lsu_perfmon_trap_b;
wire lsu_perfmon_trap_g;
wire lsu_ext_interrupt;
wire [1:0] lsu_ext_int_type;
wire [5:0] lsu_ext_int_vec;
wire [2:0] lsu_ext_int_tid;
wire [7:0] mmu_hw_tw_enable;
wire [7:0] mmu_write_itlb;
wire [7:0] mmu_reload_done;
wire [7:0] mmu_i_unauth_access;
wire [7:0] mmu_i_tsb_miss;
wire [7:0] mmu_d_tsb_miss;
wire [7:0] mmu_i_tte_outofrange;
wire [7:0] mmu_d_tte_outofrange;
wire [47:0] mmu_itte_tag_data;
wire [64:0] mmu_asi_data;
wire mmu_asi_read;
wire mmu_dae_req;
wire [2:0] mmu_dae_tid;
wire mmu_asi_cecc;
wire mmu_asi_uecc;
wire [2:0] mmu_asi_tid;
wire [10:0] mmu_asi_index;
wire mmu_asi_mra_not_sca;
wire [7:0] mmu_i_l2cerr;
wire [7:0] mmu_d_l2cerr;
wire [7:0] mmu_i_eccerr;
wire [7:0] mmu_d_eccerr;
wire [2:0] mmu_thr0_err_type;
wire [2:0] mmu_thr1_err_type;
wire [2:0] mmu_thr2_err_type;
wire [2:0] mmu_thr3_err_type;
wire [2:0] mmu_thr4_err_type;
wire [2:0] mmu_thr5_err_type;
wire [2:0] mmu_thr6_err_type;
wire [2:0] mmu_thr7_err_type;
wire [2:0] mmu_thr0_err_index;
wire [2:0] mmu_thr1_err_index;
wire [2:0] mmu_thr2_err_index;
wire [2:0] mmu_thr3_err_index;
wire [2:0] mmu_thr4_err_index;
wire [2:0] mmu_thr5_err_index;
wire [2:0] mmu_thr6_err_index;
wire [2:0] mmu_thr7_err_index;
wire spu_tlu_cwq_busy;
wire [10:0] spu_tlu_mamu_err_req;
wire [4:0] spu_tlu_ma_int_req;
wire [3:0] spu_tlu_cwq_int_req;
wire [5:0] spu_tlu_l2_error;
wire [7:0] pmu_tlu_trap_m;
wire [7:0] pmu_tlu_debug_event;
wire tlu_flush_lsu_b;
wire [7:0] tlu_release_tte;
wire tlu_rngf_cdbus_error;
wire [7:0] tlu_asi_0;
wire [7:0] tlu_asi_1;
wire tlu_asi_0_valid;
wire tlu_asi_1_valid;
wire [1:0] tlu_asi_0_tid;
wire [1:0] tlu_asi_1_tid;
wire [7:0] tlu_lsu_clear_ctl_reg_;
wire [7:0] tlu_load_i_tag_access_p;
wire [7:0] tlu_load_i_tag_access_n;
wire [7:0] tlu_load_d_tag_access;
wire [7:0] tlu_load_d_tag_access_r;
wire [47:13] tlu_pc_0_w;
wire [47:13] tlu_pc_1_w;
wire [7:0] tlu_iht_request;
wire [7:0] tlu_dht_request;
wire [7:0] tlu_mmu_tl_gt_0;
wire [1:0] tlu_flush_pmu_b;
wire [1:0] tlu_flush_pmu_w;
wire [7:0] tlu_pmu_trap_taken;
wire [1:0] tlu_pmu_trap_mask_e;
wire [7:0] tlu_lsu_hpstate_hpriv;
wire [7:0] tlu_lsu_pstate_priv;
wire [7:0] tlu_pmu_hpstate_hpriv;
wire [7:0] tlu_pmu_pstate_priv;
wire [7:0] tlu_pstate_cle;
wire tlu_cerer_hwtwmu;
wire tlu_cerer_hwtwl2;
wire tlu_cerer_dttp;
wire tlu_cerer_dttm;
wire tlu_cerer_dtdp;
wire tlu_cerer_dcl2c;
wire tlu_cerer_dcl2u;
wire tlu_cerer_dcl2nd;
wire tlu_cerer_sbdlc;
wire tlu_cerer_sbdlu;
wire tlu_cerer_mrau;
wire tlu_cerer_scac;
wire tlu_cerer_scau;
wire tlu_cerer_sbapp;
wire tlu_cerer_l2c_socc;
wire tlu_cerer_l2u_socu;
wire tlu_cerer_dcvp;
wire tlu_cerer_dctp;
wire tlu_cerer_dctm;
wire tlu_cerer_dcdp;
wire tlu_cerer_sbdpc;
wire tlu_cerer_sbdpu;
wire tlu_cerer_mamu;
wire tlu_cerer_mal2c;
wire tlu_cerer_mal2u;
wire tlu_cerer_mal2nd;
wire tlu_cerer_cwql2c;
wire tlu_cerer_cwql2u;
wire tlu_cerer_cwql2nd;
wire tlu_cerer_sbdiou;
wire [1:0] tlu_tag_access_tid_0_b;
wire tlu_i_tag_access_0_b;
wire tlu_d_tag_access_0_b;
wire [1:0] tlu_tag_access_tid_1_b;
wire tlu_i_tag_access_1_b;
wire tlu_d_tag_access_1_b;
wire tlu_mbi_tsa0_fail;
wire tlu_mbi_tsa1_fail;
wire tlu_mbi_tca_fail;
wire [1:0] lsu_tlu_dsfsr_ct_b;
wire mmu_dtlb_reload;
wire [12:0] lsu_context_b;
wire pmu_lsu_dcmiss_trap_m;
wire pmu_lsu_dtmiss_trap_m;
wire [7:0] pmu_lsu_l2dmiss_trap_m;
wire mbi_ptag_data;
wire lsu_mbi_dca_fail;
wire lsu_mbi_dta_fail;
wire lsu_mbi_dva_fail;
wire lsu_mbi_lru_fail;
wire lsu_mbi_dtb_fail;
wire lsu_mbi_stb_cam_fail;
wire lsu_mbi_stb_ram_fail;
wire lsu_mbi_cpq_fail;
wire mbi_dtb_cam_en_pre;
wire mbi_dtb_demap_en;
wire lsu_mbi_tlb_data_cmp;
wire lsu_mbi_tlb_cam_hit;
wire lsu_mbi_tlb_cam_mhit;
wire lsu_mbi_tlb_ctxt0_hit;
wire lsu_mbi_tlb_valid;
wire lsu_mbi_tlb_used;
wire mbi_scm_cam_en_pre;
wire lsu_mbi_scm_hit;
wire lsu_mbi_scm_mhit;
wire [2:0] lsu_mbi_scm_hit_ptr;
wire lsu_mbi_scm_praw;
wire lsu_spu_pmen;
wire lsu_mmu_pmen;
wire lsu_pmu_pmen;
wire lsu_misc_pmen;
wire spu_mbi_mam_fail_;
wire spu_mbi_mam_fail2_;
wire spu_mbi_arf_fail_;
wire spu_mbi_rrf_fail_;
wire [4:0] spu_pmu_cwq_busy;
wire [2:0] spu_pmu_cwq_tid;
wire mmu_mbi_mra0_fail;
wire mmu_mbi_mra1_fail;
wire mmu_mbi_scp0_fail;
wire mmu_mbi_scp1_fail;
wire mmu_pmu_l2ret;
wire mmu_pmu_l2miss;
wire mmu_pmu_dtlb;
wire [2:0] mmu_pmu_tid;
wire mb2_misc_pmen;

input        gclk;         	// PINDEF:BOT

// scan signals
input  [1:0] scan_in;       	//               arc=l2clk:30 cap=20
input 	     tcu_pce_ov;	// PINDEF:BOT	 arc=l2clk:30 cap=20
input 	     tcu_clk_stop;	// PINDEF:BOT    arc=l2clk:30 cap=20
input 	     tcu_aclk;		// PINDEF:BOT    
input 	     tcu_bclk;		// PINDEF:BOT    
input 	     tcu_dectest;	// PINDEF:BOT    
input 	     tcu_muxtest;	// PINDEF:BOT    
input 	     tcu_scan_en;	// PINDEF:BOT    
input        tcu_array_wr_inhibit;	// PINDEF:BOT    
input        tcu_se_scancollar_in;	// PINDEF:BOT    
input        tcu_se_scancollar_out;	// PINDEF:BOT    
input	     tcu_atpg_mode;
input        rst_wmr_protect;		// PINDEF:BOT

output [1:0] scan_out;	    	// PINDEF:BOT    arc=l2clk:100 drv=32x

// shadow scan signals
input		tcu_shscan_pce_ov;	// PINDEF:BOT
input		tcu_shscan_clk_stop;	// PINDEF:BOT
input		tcu_shscan_aclk;	// PINDEF:BOT
input		tcu_shscan_bclk;	// PINDEF:BOT
input		tcu_shscan_scan_in;	// PINDEF:BOT
input		tcu_shscan_scan_en;	// PINDEF:BOT
input	[2:0]	tcu_shscanid;		// PINDEF:BOT
output		spc_shscan_scan_out;	// PINDEF:BOT

// From RST
input		cluster_arst_l;		// PINDEF:BOT

// MBIST signals
input           tcu_spc_mbist_scan_in;	// PINDEF:BOT 
input           tcu_mbist_bisi_en;	// PINDEF:BOT 
input           tcu_spc_mbist_start;	// PINDEF:BOT 
input           tcu_mbist_user_mode;	// PINDEF:BOT 
output		spc_mbist_fail;		// PINDEF:BOT    
output          spc_mbist_done;		// PINDEF:BOT 
output          spc_tcu_mbist_scan_out;	// PINDEF:BOT 

input	[2:0]	const_cpuid;	// PINDEF:BOT    arc=l2clk:30 cap=20

// Core enable signals from CMP
input		tcu_ss_mode;		// PINDEF:BOT
input		tcu_do_mode;		// PINDEF:BOT
input		tcu_ss_request;		// PINDEF:BOT
input		ncu_cmp_tick_enable;	// PINDEF:BOT
output		spc_ss_complete;	// PINDEF:BOT

// RSTVADDR (POR address) control
input 		ncu_wmr_vec_mask;	// PINDEF:BOT

// Debug signals
output		spc_hardstop_request;	// PINDEF:BOT
output		spc_softstop_request;	// PINDEF:BOT
output		spc_trigger_pulse;	// PINDEF:BOT

// partial core signals
input           ncu_spc_pm;      	// PINDEF:BOT arc=l2clk:50 cap=20
input           ncu_spc_ba01;   	// PINDEF:BOT arc=l2clk:50 cap=20
input           ncu_spc_ba23;   	// PINDEF:BOT arc=l2clk:50 cap=20
input           ncu_spc_ba45;   	// PINDEF:BOT arc=l2clk:50 cap=20
input           ncu_spc_ba67;   	// PINDEF:BOT arc=l2clk:50 cap=20

// EFUSE interface
input		efu_spc_fuse_data;	// PINDEF:BOT
input		efu_spc_fuse_ixfer_en;	// PINDEF:BOT
input		efu_spc_fuse_dxfer_en;	// PINDEF:BOT
input		efu_spc_fuse_iclr;	// PINDEF:BOT
input		efu_spc_fuse_dclr;	// PINDEF:BOT
output		spc_efu_fuse_ddata;	// PINDEF:BOT
output		spc_efu_fuse_idata;	// PINDEF:BOT
output		spc_efu_fuse_ixfer_en;	// PINDEF:BOT
output		spc_efu_fuse_dxfer_en;	// PINDEF:BOT

// VNW inputs
input		vnw_ary0;
input		vnw_ary1;

// Logic BIST signals
input           tcu_spc_lbist_start;    // PINDEF:BOT 
input           tcu_spc_lbist_scan_in;  // PINDEF:BOT 
input           tcu_spc_lbist_pgm;      // PINDEF:BOT 
input           tcu_spc_test_mode;      // PINDEF:BOT 

output          spc_tcu_lbist_done;     // PINDEF:BOT
output          spc_tcu_lbist_scan_out; // PINDEF:BOT

// DMO interface
input	[35:0]	dmo_din;		// PINDEF: RIGHT
input		dmo_coresel;
input		dmo_icmuxctl;
input		dmo_dcmuxctl;

output	[35:0]	dmo_dout;

// l2 index hashing

input           ncu_spc_l2_idx_hash_en; // PINDEF:BOT arc=l2clk:50 cap=20

// gasket <-> CPX interface
// ---------------------------       
// Incoming CPX packet
input   [145:0] cpx_spc_data_cx;	// PINDEF:BOT arc=l2clk:100 cap=20
// 0in known_driven -var cpx_spc_data_cx[144:0] -active cpx_spc_data_cx[145]

// gasket <-> PCX interface
input   [8:0]   pcx_spc_grant_px;	// PINDEF:BOT arc=l2clk:200 cap=20

// PCX request
output  [8:0]   spc_pcx_req_pq; 	// PINDEF:BOT arc=l2clk:200 drv=32x
output  [8:0]   spc_pcx_atm_pq;		// PINDEF:BOT arc=l2clk:200 drv=32x

// PCX packet data
output  [129:0] spc_pcx_data_pa;   	// PINDEF:BOT arc=l2clk:100 drv=32x    

input [7:0] tcu_core_running;   	// PINDEF:BOT arc=l2clk:30 cap=20
output [7:0] spc_core_running_status;   // PINDEF:BOT arc=l2clk:100 drv=32x

input [2:0] power_throttle; // power throttle, [2:0] is encoded number of stalls in 8 cycle window
			    // 000 - no stalls, 001 - 1 stall, ... 111 - 7 stalls

output [1:0] spc_dbg_instr_cmt_grp0;  // Pipe status for debug
output [1:0] spc_dbg_instr_cmt_grp1;  // Pipe status for debug


// Needs to be spc input so that it can be easily changed for metal ECs
input [3:0]  hver_mask_minor_rev;

input        ccu_slow_cmp_sync_en;
input        ccu_cmp_slow_sync_en;


//spc_rep0_dp rep0;	// global repeaters

spc_rep1_dp rep1(
  .exu_address0_e(exu_address0_e[47:0]),
  .exu_address1_e(exu_address1_e[47:0]),
  .exu_address0_e_rep0(exu_address0_e_rep0[47:0]),
  .exu_address1_e_rep0(exu_address1_e_rep0[47:0]),
  .exu_address0_e_rep01(exu_address0_e_rep01[47:0]),
  .exu_address1_e_rep01(exu_address1_e_rep01[47:0]),
  .fgu_exu_result_fx5(fgu_exu_result_fx5[63:0]),
  .fgu_exu_result_fx5_rep0(fgu_exu_result_fx5_rep0[63:0]),
  .fgu_exu_result_fx5_rep1(fgu_exu_result_fx5_rep1[63:0]),
  .lsu_exu_ld_data_b(lsu_exu_ld_data_b[63:0]),
  .lsu_exu_ld_data_b_rep00(lsu_exu_ld_data_b_rep00[63:0]),
  .lsu_exu_ld_data_b_rep01(lsu_exu_ld_data_b_rep01[63:0]),
  .fgu_cecc_fx2(fgu_cecc_fx2),
  .fgu_uecc_fx2(fgu_uecc_fx2),
  .fgu_cecc_fx2_rep1(fgu_cecc_fx2_rep1),
  .fgu_uecc_fx2_rep1(fgu_uecc_fx2_rep1),
  .pce_ov(pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lb_scan_en(lb_scan_en),
  .scan_in(scan_in[1:0]),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_aclk(tcu_aclk),
  .tcu_bclk(tcu_bclk),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en(tcu_scan_en),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .tcu_se_scancollar_out(tcu_se_scancollar_out),
  .rst_wmr_protect(rst_wmr_protect),
  .dmo_dcmuxctl(dmo_dcmuxctl),
  .hver_mask_minor_rev(hver_mask_minor_rev[3:0]),
  .scan_out(scan_out[1:0]),
  .tcu_shscan_pce_ov(tcu_shscan_pce_ov),
  .tcu_shscan_aclk(tcu_shscan_aclk),
  .tcu_shscan_bclk(tcu_shscan_bclk),
  .tcu_shscan_scan_in(tcu_shscan_scan_in),
  .tcu_shscan_scan_en(tcu_shscan_scan_en),
  .spc_shscan_scan_out(spc_shscan_scan_out),
  .cluster_arst_l(cluster_arst_l),
  .tcu_spc_mbist_scan_in(tcu_spc_mbist_scan_in),
  .tcu_spc_mbist_start_ff(tcu_spc_mbist_start_ff),
  .spc_mbist_fail(spc_mbist_fail),
  .spc_mbist_done(spc_mbist_done),
  .spc_tcu_mbist_scan_out(spc_tcu_mbist_scan_out),
  .tcu_spc_lbist_start(tcu_spc_lbist_start),
  .tcu_spc_lbist_scan_in(tcu_spc_lbist_scan_in),
  .tcu_spc_lbist_pgm(tcu_spc_lbist_pgm),
  .tcu_spc_test_mode(tcu_spc_test_mode),
  .spc_tcu_lbist_done(spc_tcu_lbist_done),
  .spc_tcu_lbist_scan_out(spc_tcu_lbist_scan_out),
  .scan_in_buf(scan_in_buf[1:0]),
  .tcu_pce_ov_buf(tcu_pce_ov_buf),
  .tcu_aclk_buf(tcu_aclk_buf),
  .tcu_bclk_buf(tcu_bclk_buf),
  .tcu_dectest_buf(tcu_dectest_buf),
  .tcu_muxtest_buf(tcu_muxtest_buf),
  .tcu_scan_en_buf(tcu_scan_en_buf),
  .tcu_array_wr_inhibit_buf(tcu_array_wr_inhibit_buf),
  .tcu_se_scancollar_in_buf(tcu_se_scancollar_in_buf),
  .tcu_se_scancollar_out_buf(tcu_se_scancollar_out_buf),
  .rst_wmr_protect_buf(rst_wmr_protect_buf),
  .dmo_dcmuxctl_buf(dmo_dcmuxctl_buf),
  .hver_mask_minor_rev_buf(hver_mask_minor_rev_buf[3:0]),
  .scan_out_buf(scan_out_buf[1:0]),
  .tcu_shscan_pce_ov_buf(tcu_shscan_pce_ov_buf),
  .tcu_shscan_aclk_buf(tcu_shscan_aclk_buf),
  .tcu_shscan_bclk_buf(tcu_shscan_bclk_buf),
  .tcu_shscan_scan_in_buf(tcu_shscan_scan_in_buf),
  .tcu_shscan_scan_en_buf(tcu_shscan_scan_en_buf),
  .spc_shscan_scan_out_buf(spc_shscan_scan_out_buf),
  .cluster_arst_l_buf(cluster_arst_l_buf),
  .tcu_spc_mbist_scan_in_buf(tcu_spc_mbist_scan_in_buf),
  .tcu_spc_mbist_start_buf0(tcu_spc_mbist_start_buf0),
  .spc_mbist_fail_ff(spc_mbist_fail_ff),
  .spc_mbist_done_ff(spc_mbist_done_ff),
  .spc_tcu_mbist_scan_out_buf(spc_tcu_mbist_scan_out_buf),
  .tcu_spc_lbist_start_buf(tcu_spc_lbist_start_buf),
  .tcu_spc_lbist_scan_in_buf(tcu_spc_lbist_scan_in_buf),
  .tcu_spc_lbist_pgm_buf(tcu_spc_lbist_pgm_buf),
  .tcu_spc_test_mode_buf(tcu_spc_test_mode_buf),
  .lb_lbist_done(lb_lbist_done),
  .spc_tcu_lbist_scan_out_buf(spc_tcu_lbist_scan_out_buf),
  .ftu_instr_0_c(ftu_instr_0_c[32:0]),
  .ftu_instr_1_c(ftu_instr_1_c[32:0]),
  .ftu_instr_2_c(ftu_instr_2_c[32:0]),
  .ftu_instr_3_c(ftu_instr_3_c[32:0]),
  .ftu_instr_exceptions_c(ftu_instr_exceptions_c[4:0]),
  .ftu_instr_0_c_rep0(ftu_instr_0_c_rep0[32:0]),
  .ftu_instr_0_c_rep1(ftu_instr_0_c_rep1[32:0]),
  .ftu_instr_0_c_rep2(ftu_instr_0_c_rep2[32:0]),
  .ftu_instr_0_c_rep3(ftu_instr_0_c_rep3[32:0]),
  .ftu_instr_1_c_rep0(ftu_instr_1_c_rep0[32:0]),
  .ftu_instr_1_c_rep1(ftu_instr_1_c_rep1[32:0]),
  .ftu_instr_1_c_rep2(ftu_instr_1_c_rep2[32:0]),
  .ftu_instr_1_c_rep3(ftu_instr_1_c_rep3[32:0]),
  .ftu_instr_2_c_rep0(ftu_instr_2_c_rep0[32:0]),
  .ftu_instr_2_c_rep1(ftu_instr_2_c_rep1[32:0]),
  .ftu_instr_2_c_rep2(ftu_instr_2_c_rep2[32:0]),
  .ftu_instr_2_c_rep3(ftu_instr_2_c_rep3[32:0]),
  .ftu_instr_3_c_rep0(ftu_instr_3_c_rep0[32:0]),
  .ftu_instr_3_c_rep1(ftu_instr_3_c_rep1[32:0]),
  .ftu_instr_3_c_rep2(ftu_instr_3_c_rep2[32:0]),
  .ftu_instr_3_c_rep3(ftu_instr_3_c_rep3[32:0]),
  .ftu_instr_0_exceptions_c_rep0(ftu_instr_0_exceptions_c_rep0[4:0]),
  .ftu_instr_0_exceptions_c_rep1(ftu_instr_0_exceptions_c_rep1[4:0]),
  .ftu_instr_0_exceptions_c_rep2(ftu_instr_0_exceptions_c_rep2[4:0]),
  .ftu_instr_0_exceptions_c_rep3(ftu_instr_0_exceptions_c_rep3[4:0]),
  .ftu_instr_1_exceptions_c_rep0(ftu_instr_1_exceptions_c_rep0[4:0]),
  .ftu_instr_1_exceptions_c_rep1(ftu_instr_1_exceptions_c_rep1[4:0]),
  .ftu_instr_1_exceptions_c_rep2(ftu_instr_1_exceptions_c_rep2[4:0]),
  .ftu_instr_1_exceptions_c_rep3(ftu_instr_1_exceptions_c_rep3[4:0]),
  .ftu_instr_2_exceptions_c_rep0(ftu_instr_2_exceptions_c_rep0[4:0]),
  .ftu_instr_2_exceptions_c_rep1(ftu_instr_2_exceptions_c_rep1[4:0]),
  .ftu_instr_2_exceptions_c_rep2(ftu_instr_2_exceptions_c_rep2[4:0]),
  .ftu_instr_2_exceptions_c_rep3(ftu_instr_2_exceptions_c_rep3[4:0]),
  .ftu_instr_3_exceptions_c_rep0(ftu_instr_3_exceptions_c_rep0[4:0]),
  .ftu_instr_3_exceptions_c_rep1(ftu_instr_3_exceptions_c_rep1[4:0]),
  .ftu_instr_3_exceptions_c_rep2(ftu_instr_3_exceptions_c_rep2[4:0]),
  .ftu_instr_3_exceptions_c_rep3(ftu_instr_3_exceptions_c_rep3[4:0]),
  .pce_ov_tl(pce_ov_tl),
  .spc_aclk_tl(spc_aclk_tl),
  .spc_bclk_tl(spc_bclk_tl),
  .spc_aclk_wmr_tl(spc_aclk_wmr_tl),
  .lb_scan_en_tl(lb_scan_en_tl),
  .pce_ov_tr(pce_ov_tr),
  .spc_aclk_tr(spc_aclk_tr),
  .spc_bclk_tr(spc_bclk_tr),
  .spc_aclk_wmr_tr(spc_aclk_wmr_tr),
  .lb_scan_en_tr(lb_scan_en_tr),
  .pce_ov_bl(pce_ov_bl),
  .spc_aclk_bl(spc_aclk_bl),
  .spc_bclk_bl(spc_bclk_bl),
  .spc_aclk_wmr_bl(spc_aclk_wmr_bl),
  .lb_scan_en_bl(lb_scan_en_bl),
  .pce_ov_br(pce_ov_br),
  .spc_aclk_br(spc_aclk_br),
  .spc_bclk_br(spc_bclk_br),
  .spc_aclk_wmr_br(spc_aclk_wmr_br),
  .lb_scan_en_br(lb_scan_en_br),
  .dec_spu_grant_d(dec_spu_grant_d),
  .dec_spu_grant_d_rep0(dec_spu_grant_d_rep0));	// global repeaters

spc_msf0_dp msf0 (	// I/O MSFFs for CMP clock domain signals
	// Put in front of lsu
	.scan_in(lsu_scanin),
	.scan_out(msf0_scanout),
	.l2clk(l2clk),
        .tcu_se_scancollar_out(lb_se_sc_out),
	.tcu_pce_ov(pce_ov_br),
        .tcu_scan_en(lb_scan_en_br),
	.spc_aclk(spc_aclk_br),
	.spc_bclk(spc_bclk_br),
  .tcu_atpg_mode(tcu_atpg_mode),
  .lb_lbist_running(lb_lbist_running),
  .slow_cmp_sync_en(slow_cmp_sync_en),
  .cmp_slow_sync_en(cmp_slow_sync_en),
  .ncu_cmp_tick_enable(ncu_cmp_tick_enable),
  .ncu_wmr_vec_mask(ncu_wmr_vec_mask),
  .tcu_ss_mode(tcu_ss_mode),
  .tcu_do_mode(tcu_do_mode),
  .tcu_mbist_user_mode(tcu_mbist_user_mode),
  .tcu_mbist_bisi_en(tcu_mbist_bisi_en),
  .tcu_ss_request(tcu_ss_request),
  .tcu_core_running(tcu_core_running[7:0]),
  .tcu_shscan_clk_stop(tcu_shscan_clk_stop),
  .tcu_shscanid(tcu_shscanid[2:0]),
  .efu_spc_fuse_data(efu_spc_fuse_data),
  .efu_spc_fuse_ixfer_en(efu_spc_fuse_ixfer_en),
  .efu_spc_fuse_dxfer_en(efu_spc_fuse_dxfer_en),
  .efu_spc_fuse_iclr(efu_spc_fuse_iclr),
  .efu_spc_fuse_dclr(efu_spc_fuse_dclr),
  .spc_efu_fuse_ddata(spc_efu_fuse_ddata),
  .spc_efu_fuse_idata(spc_efu_fuse_idata),
  .spc_efu_fuse_ixfer_en(spc_efu_fuse_ixfer_en),
  .spc_efu_fuse_dxfer_en(spc_efu_fuse_dxfer_en),
  .efu_spc_fuse_data_buf(efu_spc_fuse_data_buf),
  .efu_spc_fuse_ixfer_en_buf(efu_spc_fuse_ixfer_en_buf),
  .efu_spc_fuse_dxfer_en_buf(efu_spc_fuse_dxfer_en_buf),
  .efu_spc_fuse_iclr_buf(efu_spc_fuse_iclr_buf),
  .efu_spc_fuse_dclr_buf(efu_spc_fuse_dclr_buf),
  .spc_efu_fuse_ddata_buf(spc_efu_fuse_ddata_buf),
  .spc_efu_fuse_idata_buf(spc_efu_fuse_idata_buf),
  .spc_efu_fuse_ixfer_en_buf(spc_efu_fuse_ixfer_en_buf),
  .spc_efu_fuse_dxfer_en_buf(spc_efu_fuse_dxfer_en_buf),
  .tlu_core_running_status(tlu_core_running_status[7:0]),
  .tlu_ss_complete(tlu_ss_complete),
  .tlu_hardstop_request(tlu_hardstop_request),
  .tlu_softstop_request(tlu_softstop_request),
  .tlu_trigger_pulse(tlu_trigger_pulse),
  .tlu_dbg_instr_cmt_grp0(tlu_dbg_instr_cmt_grp0[1:0]),
  .tlu_dbg_instr_cmt_grp1(tlu_dbg_instr_cmt_grp1[1:0]),
  .msf0_cmp_tick_enable(msf0_cmp_tick_enable),
  .msf0_wmr_vec_mask(msf0_wmr_vec_mask),
  .msf0_ss_mode(msf0_ss_mode),
  .msf0_do_mode(msf0_do_mode),
  .msf0_ss_request(msf0_ss_request),
  .msf0_core_running(msf0_core_running[7:0]),
  .msf0_shscan_clk_stop(msf0_shscan_clk_stop),
  .msf0_shscanid(msf0_shscanid[2:0]),
  .msf0_mbist_user_mode_ff(msf0_mbist_user_mode_ff),
  .msf0_mbist_bisi_en_ff(msf0_mbist_bisi_en_ff),
  .msf0_atpg_mode_buf(msf0_atpg_mode_buf),
  .spc_core_running_status(spc_core_running_status[7:0]),
  .spc_ss_complete(spc_ss_complete),
  .spc_hardstop_request(spc_hardstop_request),
  .spc_softstop_request(spc_softstop_request),
  .spc_trigger_pulse(spc_trigger_pulse),
  .spc_dbg_instr_cmt_grp0(spc_dbg_instr_cmt_grp0[1:0]),
  .spc_dbg_instr_cmt_grp1(spc_dbg_instr_cmt_grp1[1:0]),
  .power_throttle(power_throttle[2:0]),
  .power_throttle_buf(power_throttle_buf[2:0])
);

spc_msf1_dp msf1 (	// I/O MSFFs for mbist start/done/fail and lbist start/done signals
	// Put in front of gkt
	.scan_in(gkt_scanin),
	.scan_out(msf1_scanout),
	.l2clk(l2clk),
        .tcu_se_scancollar_out(lb_se_sc_out),
	.tcu_pce_ov(pce_ov_br),
	.spc_aclk(spc_aclk_br),
	.spc_bclk(spc_bclk_br),
  .tcu_spc_mbist_start(tcu_spc_mbist_start),
  .spc_mbist_fail_buf(spc_mbist_fail_buf),
  .spc_mbist_done_buf(spc_mbist_done_buf),
  .tcu_spc_mbist_start_ff(tcu_spc_mbist_start_ff),
  .spc_mbist_fail_ff(spc_mbist_fail_ff),
  .spc_mbist_done_ff(spc_mbist_done_ff)
);

// LBIST controller
spc_lb_ctl lb (
        .scan_in(tcu_spc_lbist_scan_in_buf),
        .scan_out(spc_tcu_lbist_scan_out_buf),
        .l2clk(gclk),	// not stopped during LBIST...comes from cluster header
        .tcu_pce_ov(pce_ov_tr),
	.aclk(tcu_aclk_buf),
        .bclk(tcu_bclk_buf),
        .scan_en(tcu_scan_en_buf),
        .se_scancollar_in(tcu_se_scancollar_in_buf),
        .se_scancollar_out(tcu_se_scancollar_out_buf),
        .clk_stop(tcu_clk_stop),
        .array_wr_inhibit(tcu_array_wr_inhibit_buf),
        .test_mode(tcu_spc_test_mode_buf),
        .io_si(scan_in_buf[1:0]),							// From pins: Core scan chain for ATPG 
        .io_so(scan_out_buf[1:0]),							// To pins:   Core scan chain for ATPG
        .lbist_start(tcu_spc_lbist_start_buf),
        .lbist_pgm(tcu_spc_lbist_pgm_buf),
        .lbist_done(lb_lbist_done),							// Indicates Logic BIST is done
        .lbist_run(lb_lbist_running),						// Indicates Logic BIST is running
        .channel_si({wmr_protect_scanin, dmo_scanin     , clk_spc_scanin , mmu_scanin,
                     ifu_ibu_scanin    , ifu_ftu_scanin , ifu_cmu_scanin , dec_scanin,
                     pku_scanin        , exu0_scanin    , exu1_scanin    , tlu_scanin,
                     lsu_scanin        , spu_scanin     , fgu_scanin     , gkt_scanin}),
        .channel_so({mmu_wmr_scanout   , dmo_scanout    , clk_spc_scanout, pmu_scanout,
                     ifu_ibu_scanout   , ifu_ftu_scanout, ifu_cmu_scanout, dec_scanout,
                     pku_scanout       , exu0_scanout   , exu1_scanout   , tlu_scanout,
                     lsu_scanout       , spu_scanout    , fgu_scanout    , gkt_scanout}),
        .mb_channel_si(lb_mb_channel_si),
        .mb_channel_so(mb2_scanout),
        .mbist_si(tcu_spc_mbist_scan_in_buf),						// From TCU:  To core's mbist scan chain	
        .mbist_so(spc_tcu_mbist_scan_out_buf),						// To TCU:    From core's mbist scan chain
        .core_aclk(lb_aclk),
        .core_bclk(lb_bclk),
        .core_scan_en(lb_scan_en),
        .core_se_sc_in(lb_se_sc_in),
        .core_se_sc_out(lb_se_sc_out),
        .core_clk_stop(lb_clk_stop),
        .core_awi(lb_array_wr_inhibit),
        .core_scan_en_wmr(lb_scan_en_wmr),
  .wmr_protect(wmr_protect),
  .slow_cmp_sync_en(slow_cmp_sync_en),
  .core_isolate(core_isolate)
);

clkgen_spc_cmp clk_spc (
	.aclk(spc_aclk),
	.aclk_wmr(spc_aclk_wmr),
        .array_wr_inhibit(clk_array_wr_inhibit),
	.bclk(spc_bclk),
	.ccu_cmp_slow_sync_en(ccu_cmp_slow_sync_en),
	.ccu_div_ph(1'b1),
	.ccu_serdes_dtm(1'b0),
	.ccu_slow_cmp_sync_en(ccu_slow_cmp_sync_en),
	.clk_ext(1'b0),
	.cluster_arst_l(cluster_arst_l_buf),
	.cluster_div_en(1'b0),
	.cmp_slow_sync_en(cmp_slow_sync_en),
	.gclk(gclk),
	.l2clk(l2clk),
	.pce_ov(pce_ov),
	.por_(por_unused),
	.rst_por_(1'b1),
	.rst_wmr_(1'b1),
	.rst_wmr_protect(rst_wmr_protect_buf),
	.scan_en(lb_scan_en),
	.scan_in(clk_spc_scanin),
	.scan_out(clk_spc_scanout),
	.slow_cmp_sync_en(slow_cmp_sync_en),
	.tcu_aclk(lb_aclk),
	.tcu_bclk(lb_bclk),
	.tcu_clk_stop(lb_clk_stop),
	.tcu_div_bypass(1'b0),
	.tcu_pce_ov(tcu_pce_ov_buf),
        .tcu_atpg_mode(msf0_atpg_mode_buf),
        .tcu_wr_inhibit(lb_array_wr_inhibit),
	.wmr_(wmr_unused),
  .wmr_protect(wmr_protect) 		
);

dmo_dp dmo (
	.scan_in(dmo_scanin),
        .scan_out(dmo_scanout),
        .tcu_pce_ov(pce_ov),
        .tcu_se_scancollar_out(lb_se_sc_out),
        .lsu_dc_data({dcc_dmo_parity[3:0], lsu_exu_ld_data_b[63:32]}),
  .l2clk(l2clk),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .ic_dmo_rd_data(ic_dmo_rd_data[32:0]),
  .dmo_din(dmo_din[35:0]),
  .dmo_coresel(dmo_coresel),
  .dmo_icmuxctl(dmo_icmuxctl),
  .dmo_dout(dmo_dout[35:0]),
  .dmo_coresel_buff(dmo_coresel_buff)
);

gkt gkt (
        .scan_in(msf1_scanout),
        .scan_out(gkt_scanout),
        .l2clk(l2clk),
        .lbist_run(lb_lbist_running),
        .tcu_se_scancollar_out(lb_se_sc_out),
        .slow_cmp_sync_en(slow_cmp_sync_en),
        .tcu_scan_en(lb_scan_en_br),
        .tcu_pce_ov(pce_ov_br),
	.spc_aclk(spc_aclk_br),
	.spc_bclk(spc_bclk_br),
        .mmu_l15_addr(mmu_l15_addr[39:4]),
        .mmu_l15_cpkt(mmu_l15_cpkt[4:0]),
	.spu_l15_addr(spu_l15_addr[38:3]),
	.spu_l15_cpkt(spu_l15_cpkt[12:0]),
	.spu_l15_data(spu_l15_data[63:0]),
  .core_isolate(core_isolate),
  .const_cpuid(const_cpuid[2:0]),
  .lsu_gkt_pmen(lsu_gkt_pmen),
  .ifu_l15_valid(ifu_l15_valid),
  .mmu_l15_valid(mmu_l15_valid),
  .lsu_l15_valid(lsu_l15_valid),
  .spu_l15_valid(spu_l15_valid),
  .lsu_l15_lock(lsu_l15_lock),
  .ifu_l15_addr(ifu_l15_addr[39:0]),
  .lsu_l15_addr(lsu_l15_addr[39:0]),
  .ifu_l15_cpkt(ifu_l15_cpkt[7:0]),
  .lsu_l15_cpkt(lsu_l15_cpkt[25:0]),
  .lsu_l15_data(lsu_l15_data[63:0]),
  .ncu_spc_pm(ncu_spc_pm),
  .ncu_spc_ba01(ncu_spc_ba01),
  .ncu_spc_ba23(ncu_spc_ba23),
  .ncu_spc_ba45(ncu_spc_ba45),
  .ncu_spc_ba67(ncu_spc_ba67),
  .ncu_spc_l2_idx_hash_en(ncu_spc_l2_idx_hash_en),
  .cpx_spc_data_cx(cpx_spc_data_cx[145:0]),
  .pcx_spc_grant_px(pcx_spc_grant_px[8:0]),
  .l15_spc_cpkt(l15_spc_cpkt[17:0]),
  .l15_spc_data1(l15_spc_data1[127:0]),
  .cpx_spc_data_cx_rep0(cpx_spc_data_cx_rep0[145:0]),
  .l15_mmu_valid(l15_mmu_valid),
  .l15_spu_valid(l15_spu_valid),
  .l15_ifu_grant(l15_ifu_grant),
  .l15_mmu_grant(l15_mmu_grant),
  .l15_lsu_grant(l15_lsu_grant),
  .l15_spu_grant(l15_spu_grant),
  .gkt_ifu_legal(gkt_ifu_legal[3:0]),
  .gkt_ifu_flip_parity(gkt_ifu_flip_parity[3:0]),
  .l15_pmu_xbar_optype(l15_pmu_xbar_optype[6:0]),
  .spc_pcx_req_pq(spc_pcx_req_pq[8:0]),
  .spc_pcx_atm_pq(spc_pcx_atm_pq[8:0]),
  .spc_pcx_data_pa(spc_pcx_data_pa[129:0])
        );

// To prevent collisions between ASI reads and block stores at the FRF, the
// minimum local ring latency to the FGU must be >= 8 cycles.
// 0in assert_follower -leader ((lsu_rngl_cdbus[64:63] == 2'b11) & (lsu_rngl_cdbus[55:48] == 8'h4E)) -follower ((fgu.in_rngl_cdbus[64:63] == 2'b11) & (fgu.in_rngl_cdbus[55:48] == 8'h4E)) -max 30 -min 8


fgu fgu (
	.scan_in(fgu_scanin),
	.scan_out(fgu_scanout),
        .wmr_scan_in(exu1_wmr_scanout),
        .wmr_scan_out(fgu_wmr_scanout),
	.l2clk(l2clk),
	.spc_aclk(spc_aclk_tr),
	.spc_aclk_wmr(spc_aclk_wmr_tr),
	.spc_bclk(spc_bclk_tr),
        .tcu_pce_ov(pce_ov_tr),
        .tcu_scan_en(lb_scan_en_tr),
        .tcu_se_scancollar_in(lb_se_sc_in),
        .tcu_se_scancollar_out(lb_se_sc_out),
        .tcu_dectest		(tcu_dectest_buf		),
        .tcu_muxtest		(tcu_muxtest_buf		),
        .tcu_array_wr_inhibit	(clk_array_wr_inhibit	),
	.dec_fgu_fmov_vld_m	(exu_fgu_fmov_vld_m),
	.dec_spu_grant_d        (dec_spu_grant_fgu_d),
	.spc_core_running_status(tlu_core_running_status[7:0]),
	.in_rngl_cdbus		(pmu_rngl_cdbus[64:0]),
	.fgu_rngl_cdbus		(fgu_rngl_cdbus[64:0]),
	.lsu_fgu_fld_data_b	(lsu_fgu_fld_data_b[63:0]),
	.exu_fgu_rs1_e		(exu_fgu_rs1_e[63:0]),
	.exu_fgu_rs2_e		(exu_fgu_rs2_e[63:0]),
	.spu_fgu_rs1_e		(spu_fgu_rs1_e[63:0]),
	.spu_fgu_rs2_e		(spu_fgu_rs2_e[63:0]),
	.mbi_addr		(mb2_addr[7:0]),
	.mbi_run		(mb2_run),
	.mbi_wdata		(mb2_write_data[7:0]),
	.mbi_frf_read_en	(mb2_frf_read_en),
	.mbi_frf_write_en	(mb2_frf_write_en),
  .dec_frf_r1_addr_d(dec_frf_r1_addr_d[4:0]),
  .dec_frf_r2_addr_d(dec_frf_r2_addr_d[4:0]),
  .dec_frf_r1_vld_d(dec_frf_r1_vld_d),
  .dec_frf_r2_vld_d(dec_frf_r2_vld_d),
  .dec_frf_r1_32b_d(dec_frf_r1_32b_d),
  .dec_frf_r2_32b_d(dec_frf_r2_32b_d),
  .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d),
  .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d),
  .dec_frf_w_vld_d(dec_frf_w_vld_d),
  .dec_frf_w_addr_d(dec_frf_w_addr_d[4:0]),
  .dec_frf_w_32b_d(dec_frf_w_32b_d),
  .dec_frf_w_odd32b_d(dec_frf_w_odd32b_d),
  .dec_exu_src_vld_d(dec_exu_src_vld_d),
  .dec_irf_w_addr_d(dec_irf_w_addr_d[4:0]),
  .dec_frf_store_d(dec_frf_store_d),
  .dec_fsr_store_d(dec_fsr_store_d),
  .dec_valid_e(dec_valid_e[1:0]),
  .dec_fgu_op3_d(dec_fgu_op3_d[5:0]),
  .dec_fgu_opf_d(dec_fgu_opf_d[7:0]),
  .dec_fgu_decode_d(dec_fgu_decode_d),
  .dec_fgu_valid_e(dec_fgu_valid_e),
  .dec_fgu_tid_d(dec_fgu_tid_d[2:0]),
  .dec_flush_f1(dec_flush_f1),
  .dec_flush_f2(dec_flush_f2),
  .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]),
  .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0]),
  .fgu_cmp_fcc_tid_fx2(fgu_cmp_fcc_tid_fx2[2:0]),
  .fgu_fld_fcc_fx3(fgu_fld_fcc_fx3[7:0]),
  .fgu_fld_fcc_vld_fx3(fgu_fld_fcc_vld_fx3[1:0]),
  .fgu_fprs_fef(fgu_fprs_fef[7:0]),
  .fgu_fdiv_stall(fgu_fdiv_stall),
  .fgu_idiv_stall(fgu_idiv_stall[1:0]),
  .fgu_divide_completion(fgu_divide_completion[7:0]),
  .tlu_flush_fgu_b(tlu_flush_fgu_b),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .tlu_cerer_frf(tlu_cerer_frf),
  .fgu_predict_fx2(fgu_predict_fx2),
  .fgu_pdist_beat2_fx1(fgu_pdist_beat2_fx1),
  .fgu_cecc_fx2(fgu_cecc_fx2),
  .fgu_uecc_fx2(fgu_uecc_fx2),
  .fgu_ecc_addr_fx2(fgu_ecc_addr_fx2[5:0]),
  .fgu_ecc_check_fx2(fgu_ecc_check_fx2[13:0]),
  .fgu_fpx_ieee_trap_fw(fgu_fpx_ieee_trap_fw),
  .fgu_fpd_ieee_trap_fw(fgu_fpd_ieee_trap_fw),
  .fgu_fpx_unfin_fw(fgu_fpx_unfin_fw),
  .fgu_fpd_unfin_fw(fgu_fpd_unfin_fw),
  .fgu_fpd_idiv0_trap_fw(fgu_fpd_idiv0_trap_fw),
  .fgu_fpx_trap_tid_fw(fgu_fpx_trap_tid_fw[2:0]),
  .fgu_fpd_trap_tid_fw(fgu_fpd_trap_tid_fw[2:0]),
  .lsu_fgu_fld_addr_b(lsu_fgu_fld_addr_b[4:0]),
  .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w),
  .lsu_fgu_fld_b(lsu_fgu_fld_b),
  .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]),
  .lsu_fgu_fld_32b_b(lsu_fgu_fld_32b_b),
  .lsu_fgu_fld_odd32b_b(lsu_fgu_fld_odd32b_b),
  .lsu_fgu_fsr_load_b(lsu_fgu_fsr_load_b),
  .lsu_fgu_exception_w(lsu_fgu_exception_w),
  .lsu_block_store_m(lsu_block_store_m),
  .lsu_asi_error_inject(lsu_asi_error_inject[31:0]),
  .lsu_fgu_pmen(lsu_fgu_pmen),
  .lsu_asi_clken(lsu_asi_clken),
  .fgu_lsu_fst_data_fx1(fgu_lsu_fst_data_fx1[63:0]),
  .fgu_fst_ecc_error_fx2(fgu_fst_ecc_error_fx2),
  .exu_fgu_gsr_m(exu_fgu_gsr_m[31:0]),
  .exu_fgu_gsr_vld_m(exu_fgu_gsr_vld_m[1:0]),
  .exu_fgu_flush_m(exu_fgu_flush_m),
  .fgu_exu_icc_fx5(fgu_exu_icc_fx5[3:0]),
  .fgu_exu_xcc_fx5(fgu_exu_xcc_fx5[1:0]),
  .fgu_exu_cc_vld_fx5(fgu_exu_cc_vld_fx5),
  .fgu_exu_w_vld_fx5(fgu_exu_w_vld_fx5[1:0]),
  .fgu_result_tid_fx5(fgu_result_tid_fx5[1:0]),
  .fgu_irf_w_addr_fx5(fgu_irf_w_addr_fx5[4:0]),
  .fgu_exu_result_fx5(fgu_exu_result_fx5[63:0]),
  .spu_fgu_fpy_ctl_d(spu_fgu_fpy_ctl_d[6:0]),
  .fgu_accum_b0_fx5(fgu_accum_b0_fx5),
  .fgu_mul_result_fx5(fgu_mul_result_fx5[63:0]),
  .lb_scan_en_wmr(lb_scan_en_wmr),
  .fgu_mbi_frf_fail(fgu_mbi_frf_fail)
);


ifu_ibu ifu_ibu (
	.scan_in(ifu_ibu_scanin),
	.scan_out(ifu_ibu_scanout),
        .tcu_pce_ov(pce_ov_bl),
        .tcu_scan_en(lb_scan_en_bl),
	.spc_aclk(spc_aclk_bl),
	.spc_bclk(spc_bclk_bl),
	.l15_ifu_valid(lsu_cpx_valid),
	.l2clk(l2clk),
  .pku_flush_buffer0(pku_flush_buffer0[7:0]),
  .pku_flush_upper_buffer(pku_flush_upper_buffer[7:0]),
  .ftu_fetch_thr_c(ftu_fetch_thr_c[7:0]),
  .pku_pick_p(pku_pick_p[7:0]),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .ftu_ibu_redirect_bf(ftu_ibu_redirect_bf[7:0]),
  .ftu_ic_no_err_c(ftu_ic_no_err_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first),
  .ftu_instr_valid_c(ftu_instr_valid_c[3:0]),
  .ftu_instr_0_c_rep0(ftu_instr_0_c_rep0[32:0]),
  .ftu_instr_0_c_rep1(ftu_instr_0_c_rep1[32:0]),
  .ftu_instr_0_c_rep2(ftu_instr_0_c_rep2[32:0]),
  .ftu_instr_0_c_rep3(ftu_instr_0_c_rep3[32:0]),
  .ftu_instr_1_c_rep0(ftu_instr_1_c_rep0[32:0]),
  .ftu_instr_1_c_rep1(ftu_instr_1_c_rep1[32:0]),
  .ftu_instr_1_c_rep2(ftu_instr_1_c_rep2[32:0]),
  .ftu_instr_1_c_rep3(ftu_instr_1_c_rep3[32:0]),
  .ftu_instr_2_c_rep0(ftu_instr_2_c_rep0[32:0]),
  .ftu_instr_2_c_rep1(ftu_instr_2_c_rep1[32:0]),
  .ftu_instr_2_c_rep2(ftu_instr_2_c_rep2[32:0]),
  .ftu_instr_2_c_rep3(ftu_instr_2_c_rep3[32:0]),
  .ftu_instr_3_c_rep0(ftu_instr_3_c_rep0[32:0]),
  .ftu_instr_3_c_rep1(ftu_instr_3_c_rep1[32:0]),
  .ftu_instr_3_c_rep2(ftu_instr_3_c_rep2[32:0]),
  .ftu_instr_3_c_rep3(ftu_instr_3_c_rep3[32:0]),
  .ftu_instr_0_exceptions_c_rep0(ftu_instr_0_exceptions_c_rep0[4:0]),
  .ftu_instr_0_exceptions_c_rep1(ftu_instr_0_exceptions_c_rep1[4:0]),
  .ftu_instr_0_exceptions_c_rep2(ftu_instr_0_exceptions_c_rep2[4:0]),
  .ftu_instr_0_exceptions_c_rep3(ftu_instr_0_exceptions_c_rep3[4:0]),
  .ftu_instr_1_exceptions_c_rep0(ftu_instr_1_exceptions_c_rep0[4:0]),
  .ftu_instr_1_exceptions_c_rep1(ftu_instr_1_exceptions_c_rep1[4:0]),
  .ftu_instr_1_exceptions_c_rep2(ftu_instr_1_exceptions_c_rep2[4:0]),
  .ftu_instr_1_exceptions_c_rep3(ftu_instr_1_exceptions_c_rep3[4:0]),
  .ftu_instr_2_exceptions_c_rep0(ftu_instr_2_exceptions_c_rep0[4:0]),
  .ftu_instr_2_exceptions_c_rep1(ftu_instr_2_exceptions_c_rep1[4:0]),
  .ftu_instr_2_exceptions_c_rep2(ftu_instr_2_exceptions_c_rep2[4:0]),
  .ftu_instr_2_exceptions_c_rep3(ftu_instr_2_exceptions_c_rep3[4:0]),
  .ftu_instr_3_exceptions_c_rep0(ftu_instr_3_exceptions_c_rep0[4:0]),
  .ftu_instr_3_exceptions_c_rep1(ftu_instr_3_exceptions_c_rep1[4:0]),
  .ftu_instr_3_exceptions_c_rep2(ftu_instr_3_exceptions_c_rep2[4:0]),
  .ftu_instr_3_exceptions_c_rep3(ftu_instr_3_exceptions_c_rep3[4:0]),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .ftu_buffer_wr_en_f(ftu_buffer_wr_en_f[7:0]),
  .ifu_buf0_valid_p(ifu_buf0_valid_p[7:0]),
  .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[7:0]),
  .ibu_empty(ibu_empty[7:0]),
  .ibu_room_4ormore(ibu_room_4ormore[7:0]),
  .ifu_buf0_inst0(ifu_buf0_inst0[32:0]),
  .ifu_buf0_inst1(ifu_buf0_inst1[32:0]),
  .ifu_buf0_inst2(ifu_buf0_inst2[32:0]),
  .ifu_buf0_inst3(ifu_buf0_inst3[32:0]),
  .ifu_buf0_inst4(ifu_buf0_inst4[32:0]),
  .ifu_buf0_inst5(ifu_buf0_inst5[32:0]),
  .ifu_buf0_inst6(ifu_buf0_inst6[32:0]),
  .ifu_buf0_inst7(ifu_buf0_inst7[32:0]),
  .ifu_buf0_excp0(ifu_buf0_excp0[4:0]),
  .ifu_buf0_excp1(ifu_buf0_excp1[4:0]),
  .ifu_buf0_excp2(ifu_buf0_excp2[4:0]),
  .ifu_buf0_excp3(ifu_buf0_excp3[4:0]),
  .ifu_buf0_excp4(ifu_buf0_excp4[4:0]),
  .ifu_buf0_excp5(ifu_buf0_excp5[4:0]),
  .ifu_buf0_excp6(ifu_buf0_excp6[4:0]),
  .ifu_buf0_excp7(ifu_buf0_excp7[4:0])
);


ifu_ftu ifu_ftu (
	.scan_in(ifu_ftu_scanin),
	.scan_out(ifu_ftu_scanout),
        .wmr_scan_in(lsu_wmr_scanout),
        .wmr_scan_out(ifu_ftu_wmr_scanout),
	.l2clk(l2clk),
        .tcu_pce_ov(pce_ov_bl),
        .tcu_scan_en(lb_scan_en_bl),
	.spc_aclk(spc_aclk_bl),
	.spc_aclk_wmr(spc_aclk_wmr_bl),
	.spc_bclk(spc_bclk_bl),
        .lbist_run		(lb_lbist_running	),
        .tcu_dectest		(tcu_dectest_buf		),
        .tcu_muxtest		(tcu_muxtest_buf		),
        .tcu_array_wr_inhibit	(clk_array_wr_inhibit	),
        .tcu_se_scancollar_in(lb_se_sc_in),
        .tcu_se_scancollar_out(lb_se_sc_out),
	.vnw_ary(vnw_ary0),
	.mbi_run(mb0_run),
	.mbi_ict_write_en(mb0_ict_write_en),
	.mbi_ict_read_en(mb0_ict_read_en),
	.mbi_icd_write_en(mb0_icd_write_en),
	.mbi_icd_read_en(mb0_icd_read_en),
	.mbi_icv_write_en(mb0_icv_write_en),
	.mbi_icv_read_en(mb0_icv_read_en),
	.mbi_itb_write_en(mb0_itb_write_en),
	.mbi_itb_read_en(mb0_itb_read_en),
	.mbi_addr(mb0_addr[8:0]),
	.mbi_wdata(mb0_write_data[7:0]),
	.mbi_cmpsel(mb0_cmpsel[2:0]),
	.exu_address0_e(exu_address0_e_rep01[47:0]),
	.exu_address1_e(exu_address1_e_rep01[47:0]),
	.tlu_trap_pc_0_valid(tlu_trap_pc_0_valid),
	.tlu_trap_pc_1_valid(tlu_trap_pc_1_valid),
	.tlu_trap_pc_0(tlu_trap_pc_0[47:0]),
	.tlu_trap_pc_1(tlu_trap_pc_1[47:0]),
	.tlu_npc_w(tlu_npc_w[47:2]),
	.in_rngl_cdbus	( lsu_rngl_cdbus[64:0]),
	.ifu_rngl_cdbus ( ifu_rngl_cdbus[64:0]	),
	.cmu_instr_v({cmu_inst3_v, cmu_inst2_v, cmu_inst1_v, cmu_inst0_v}),
        .efu_spc_fuse_data(efu_spc_fuse_data_buf),
        .efu_spc_fuse_ixfer_en(efu_spc_fuse_ixfer_en_buf),
        .efu_spc_fuse_iclr(efu_spc_fuse_iclr_buf),
        .spc_efu_fuse_ixfer_en(spc_efu_fuse_ixfer_en_buf),
        .spc_efu_fuse_idata(spc_efu_fuse_idata_buf),
	.spc_core_running_status(tlu_core_running_status[7:0]),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_cambist_shift(mbi_cambist_shift),
  .mbi_dis_clr_ubit(mbi_dis_clr_ubit),
  .mbi_init_to_zero(mbi_init_to_zero),
  .mbi_itb_cam_en_pre(mbi_itb_cam_en_pre),
  .mbi_repl_write(mbi_repl_write),
  .mbi_itb_demap_en(mbi_itb_demap_en),
  .mbi_demap_type(mbi_demap_type[1:0]),
  .ftu_mbi_tlb_data_cmp(ftu_mbi_tlb_data_cmp),
  .ftu_mbi_tlb_cam_hit(ftu_mbi_tlb_cam_hit),
  .ftu_mbi_tlb_cam_mhit(ftu_mbi_tlb_cam_mhit),
  .ftu_mbi_tlb_ctxt0_hit(ftu_mbi_tlb_ctxt0_hit),
  .ftu_mbi_tlb_valid(ftu_mbi_tlb_valid),
  .ftu_mbi_tlb_used(ftu_mbi_tlb_used),
  .lsu_asi_error_inject(lsu_asi_error_inject[31:28]),
  .lsu_ifu_direct_map(lsu_ifu_direct_map),
  .ftu_mbi_ict_fail(ftu_mbi_ict_fail),
  .ftu_mbi_icd_fail(ftu_mbi_icd_fail),
  .ftu_mbi_itb_fail(ftu_mbi_itb_fail),
  .ftu_mbi_icv_fail(ftu_mbi_icv_fail),
  .tlu_retry(tlu_retry[1:0]),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .tlu_ifu_hpstate_hpriv(tlu_ifu_hpstate_hpriv[7:0]),
  .tlu_ifu_pstate_priv(tlu_ifu_pstate_priv[7:0]),
  .tlu_pstate_am(tlu_pstate_am[7:0]),
  .tlu_ifu_invalidate(tlu_ifu_invalidate[1:0]),
  .cmu_fill_paddr(cmu_fill_paddr[39:5]),
  .cmu_inval_ack(cmu_inval_ack[7:0]),
  .cmu_l2_err(cmu_l2_err[1:0]),
  .cmu_l2miss(cmu_l2miss),
  .tlu_cerer_ittp(tlu_cerer_ittp),
  .tlu_cerer_itdp(tlu_cerer_itdp),
  .tlu_cerer_ittm(tlu_cerer_ittm),
  .tlu_cerer_icl2c(tlu_cerer_icl2c),
  .tlu_cerer_icl2u(tlu_cerer_icl2u),
  .tlu_cerer_icl2nd(tlu_cerer_icl2nd),
  .tlu_cerer_icvp(tlu_cerer_icvp),
  .tlu_cerer_ictp(tlu_cerer_ictp),
  .tlu_cerer_ictm(tlu_cerer_ictm),
  .cmu_icache_invalidate(cmu_icache_invalidate),
  .cmu_evic_invalidate(cmu_evic_invalidate),
  .cmu_icache_invalidate_way(cmu_icache_invalidate_way[2:0]),
  .cmu_icache_inv_way1(cmu_icache_inv_way1[2:0]),
  .cmu_icache_invalidate_index(cmu_icache_invalidate_index[10:5]),
  .dec_load_flush_w(dec_load_flush_w[1:0]),
  .dec_tid0_d(dec_tid0_d[1:0]),
  .dec_tid1_d(dec_tid1_d[1:0]),
  .dec_br_taken_e(dec_br_taken_e[1:0]),
  .dec_valid_e(dec_valid_e[1:0]),
  .tlu_trap_0_tid(tlu_trap_0_tid[1:0]),
  .tlu_trap_1_tid(tlu_trap_1_tid[1:0]),
  .tlu_flush_ifu(tlu_flush_ifu[7:0]),
  .tlu_itlb_reload(tlu_itlb_reload[1:0]),
  .tlu_itlb_bypass(tlu_itlb_bypass[7:0]),
  .tlu_tl_gt_0(tlu_tl_gt_0[7:0]),
  .ibu_empty(ibu_empty[7:0]),
  .ibu_room_4ormore(ibu_room_4ormore[7:0]),
  .cmu_null_st(cmu_null_st[7:0]),
  .cmu_dupmiss_st(cmu_dupmiss_st[7:0]),
  .cmu_rst_dupmiss(cmu_rst_dupmiss[7:0]),
  .cmu_any_un_cacheable(cmu_any_un_cacheable),
  .cmu_any_data_ready(cmu_any_data_ready),
  .cmu_thr0_data_ready(cmu_thr0_data_ready),
  .cmu_thr1_data_ready(cmu_thr1_data_ready),
  .cmu_thr2_data_ready(cmu_thr2_data_ready),
  .cmu_thr3_data_ready(cmu_thr3_data_ready),
  .cmu_thr4_data_ready(cmu_thr4_data_ready),
  .cmu_thr5_data_ready(cmu_thr5_data_ready),
  .cmu_thr6_data_ready(cmu_thr6_data_ready),
  .cmu_thr7_data_ready(cmu_thr7_data_ready),
  .cmu_fill_inst0(cmu_fill_inst0[32:0]),
  .cmu_fill_inst1(cmu_fill_inst1[32:0]),
  .cmu_fill_inst2(cmu_fill_inst2[32:0]),
  .cmu_fill_inst3(cmu_fill_inst3[32:0]),
  .lsu_ic_enable(lsu_ic_enable[7:0]),
  .lsu_ifu_no_miss(lsu_ifu_no_miss[7:0]),
  .lsu_ifu_ctxt_data(lsu_ifu_ctxt_data[12:0]),
  .lsu_ifu_tid_w(lsu_ifu_tid_w[2:0]),
  .lsu_ifu_wr_p0ctxt(lsu_ifu_wr_p0ctxt),
  .lsu_ifu_wr_p1ctxt(lsu_ifu_wr_p1ctxt),
  .lsu_ifu_wr_pid(lsu_ifu_wr_pid),
  .lsu_immu_enable(lsu_immu_enable[7:0]),
  .lsu_ifu_ftu_pmen(lsu_ifu_ftu_pmen),
  .lsu_ic_pmen(lsu_ic_pmen),
  .cmu_fill_wrway(cmu_fill_wrway[2:0]),
  .cmu_ic_data(cmu_ic_data[263:0]),
  .mmu_index(mmu_index[6:0]),
  .ftu_buffer_wr_en_f(ftu_buffer_wr_en_f[7:0]),
  .ftu_rep_way(ftu_rep_way[2:0]),
  .ftu_paddr(ftu_paddr[39:0]),
  .ftu_instr_0_c(ftu_instr_0_c[32:0]),
  .ftu_instr_1_c(ftu_instr_1_c[32:0]),
  .ftu_instr_2_c(ftu_instr_2_c[32:0]),
  .ftu_instr_3_c(ftu_instr_3_c[32:0]),
  .ftu_exception_valid_c(ftu_exception_valid_c),
  .ftu_instr_exceptions_c(ftu_instr_exceptions_c[4:0]),
  .ftu_instr_valid_c(ftu_instr_valid_c[3:0]),
  .ftu_fetch_thr_c(ftu_fetch_thr_c[7:0]),
  .ftu_curr_fetch_thr_f(ftu_curr_fetch_thr_f[7:0]),
  .ftu_ifu_quiesce(ftu_ifu_quiesce[7:0]),
  .ifu_ibuffer_write_c(ifu_ibuffer_write_c[7:0]),
  .ftu_ic_no_err_c(ftu_ic_no_err_c),
  .ftu_bus_0_is_first(ftu_bus_0_is_first),
  .ftu_bus_1_is_first(ftu_bus_1_is_first),
  .ftu_bus_2_is_first(ftu_bus_2_is_first),
  .ftu_bus_3_is_first(ftu_bus_3_is_first),
  .ftu_instr_sf_valid_c(ftu_instr_sf_valid_c),
  .ftu_excp_way_d(ftu_excp_way_d[2:0]),
  .ftu_excp_tid_d(ftu_excp_tid_d[2:0]),
  .ftu_excp_way_valid_d(ftu_excp_way_valid_d),
  .ftu_thrx_un_cacheable(ftu_thrx_un_cacheable),
  .ftu_agc_thr0_cmiss_c(ftu_agc_thr0_cmiss_c),
  .ftu_agc_thr1_cmiss_c(ftu_agc_thr1_cmiss_c),
  .ftu_agc_thr2_cmiss_c(ftu_agc_thr2_cmiss_c),
  .ftu_agc_thr3_cmiss_c(ftu_agc_thr3_cmiss_c),
  .ftu_agc_thr4_cmiss_c(ftu_agc_thr4_cmiss_c),
  .ftu_agc_thr5_cmiss_c(ftu_agc_thr5_cmiss_c),
  .ftu_agc_thr6_cmiss_c(ftu_agc_thr6_cmiss_c),
  .ftu_agc_thr7_cmiss_c(ftu_agc_thr7_cmiss_c),
  .ftu_thr0_inv_req_c(ftu_thr0_inv_req_c),
  .ftu_thr1_inv_req_c(ftu_thr1_inv_req_c),
  .ftu_thr2_inv_req_c(ftu_thr2_inv_req_c),
  .ftu_thr3_inv_req_c(ftu_thr3_inv_req_c),
  .ftu_thr4_inv_req_c(ftu_thr4_inv_req_c),
  .ftu_thr5_inv_req_c(ftu_thr5_inv_req_c),
  .ftu_thr6_inv_req_c(ftu_thr6_inv_req_c),
  .ftu_thr7_inv_req_c(ftu_thr7_inv_req_c),
  .ftu_ibu_redirect_bf(ftu_ibu_redirect_bf[7:0]),
  .ftu_thr0_redirect_bf(ftu_thr0_redirect_bf),
  .ftu_thr1_redirect_bf(ftu_thr1_redirect_bf),
  .ftu_thr2_redirect_bf(ftu_thr2_redirect_bf),
  .ftu_thr3_redirect_bf(ftu_thr3_redirect_bf),
  .ftu_thr4_redirect_bf(ftu_thr4_redirect_bf),
  .ftu_thr5_redirect_bf(ftu_thr5_redirect_bf),
  .ftu_thr6_redirect_bf(ftu_thr6_redirect_bf),
  .ftu_thr7_redirect_bf(ftu_thr7_redirect_bf),
  .ic_dmo_rd_data(ic_dmo_rd_data[32:0]),
  .slow_cmp_sync_en(slow_cmp_sync_en),
  .cmp_slow_sync_en(cmp_slow_sync_en)
);


ifu_cmu ifu_cmu (
	.scan_in(ifu_cmu_scanin),
	.scan_out(ifu_cmu_scanout),
	.l15_spc_cpkt		(lsu_cpx_cpkt[17:0]),
	.l15_spc_data1		(lsu_cpx_data[127:0]),
	.l15_ifu_valid		(lsu_cpx_valid),
	.l2clk(l2clk),
        .tcu_pce_ov(pce_ov_bl),
        .tcu_scan_en(lb_scan_en_bl),
	.spc_aclk(spc_aclk_bl),
	.spc_bclk(spc_bclk_bl),
  .const_cpuid(const_cpuid[2:0]),
  .lsu_ifu_cmu_pmen(lsu_ifu_cmu_pmen),
  .ftu_paddr(ftu_paddr[39:0]),
  .ftu_rep_way(ftu_rep_way[2:0]),
  .ftu_thrx_un_cacheable(ftu_thrx_un_cacheable),
  .ftu_curr_fetch_thr_f(ftu_curr_fetch_thr_f[7:0]),
  .ftu_agc_thr0_cmiss_c(ftu_agc_thr0_cmiss_c),
  .ftu_agc_thr1_cmiss_c(ftu_agc_thr1_cmiss_c),
  .ftu_agc_thr2_cmiss_c(ftu_agc_thr2_cmiss_c),
  .ftu_agc_thr3_cmiss_c(ftu_agc_thr3_cmiss_c),
  .ftu_agc_thr4_cmiss_c(ftu_agc_thr4_cmiss_c),
  .ftu_agc_thr5_cmiss_c(ftu_agc_thr5_cmiss_c),
  .ftu_agc_thr6_cmiss_c(ftu_agc_thr6_cmiss_c),
  .ftu_agc_thr7_cmiss_c(ftu_agc_thr7_cmiss_c),
  .ftu_thr0_inv_req_c(ftu_thr0_inv_req_c),
  .ftu_thr1_inv_req_c(ftu_thr1_inv_req_c),
  .ftu_thr2_inv_req_c(ftu_thr2_inv_req_c),
  .ftu_thr3_inv_req_c(ftu_thr3_inv_req_c),
  .ftu_thr4_inv_req_c(ftu_thr4_inv_req_c),
  .ftu_thr5_inv_req_c(ftu_thr5_inv_req_c),
  .ftu_thr6_inv_req_c(ftu_thr6_inv_req_c),
  .ftu_thr7_inv_req_c(ftu_thr7_inv_req_c),
  .ftu_thr0_redirect_bf(ftu_thr0_redirect_bf),
  .ftu_thr1_redirect_bf(ftu_thr1_redirect_bf),
  .ftu_thr2_redirect_bf(ftu_thr2_redirect_bf),
  .ftu_thr3_redirect_bf(ftu_thr3_redirect_bf),
  .ftu_thr4_redirect_bf(ftu_thr4_redirect_bf),
  .ftu_thr5_redirect_bf(ftu_thr5_redirect_bf),
  .ftu_thr6_redirect_bf(ftu_thr6_redirect_bf),
  .ftu_thr7_redirect_bf(ftu_thr7_redirect_bf),
  .lsu_ifu_ld_index(lsu_ifu_ld_index[10:5]),
  .l15_ifu_grant(l15_ifu_grant),
  .gkt_ifu_legal(gkt_ifu_legal[3:0]),
  .gkt_ifu_flip_parity(gkt_ifu_flip_parity[3:0]),
  .cmu_l2miss(cmu_l2miss),
  .cmu_any_data_ready(cmu_any_data_ready),
  .cmu_thr0_data_ready(cmu_thr0_data_ready),
  .cmu_thr1_data_ready(cmu_thr1_data_ready),
  .cmu_thr2_data_ready(cmu_thr2_data_ready),
  .cmu_thr3_data_ready(cmu_thr3_data_ready),
  .cmu_thr4_data_ready(cmu_thr4_data_ready),
  .cmu_thr5_data_ready(cmu_thr5_data_ready),
  .cmu_thr6_data_ready(cmu_thr6_data_ready),
  .cmu_thr7_data_ready(cmu_thr7_data_ready),
  .cmu_any_un_cacheable(cmu_any_un_cacheable),
  .cmu_null_st(cmu_null_st[7:0]),
  .cmu_dupmiss_st(cmu_dupmiss_st[7:0]),
  .cmu_rst_dupmiss(cmu_rst_dupmiss[7:0]),
  .cmu_inst0_v(cmu_inst0_v),
  .cmu_inst1_v(cmu_inst1_v),
  .cmu_inst2_v(cmu_inst2_v),
  .cmu_inst3_v(cmu_inst3_v),
  .cmu_fill_wrway(cmu_fill_wrway[2:0]),
  .cmu_fill_paddr(cmu_fill_paddr[39:0]),
  .cmu_fill_inst0(cmu_fill_inst0[32:0]),
  .cmu_fill_inst1(cmu_fill_inst1[32:0]),
  .cmu_fill_inst2(cmu_fill_inst2[32:0]),
  .cmu_fill_inst3(cmu_fill_inst3[32:0]),
  .cmu_ic_data(cmu_ic_data[263:0]),
  .cmu_icache_invalidate(cmu_icache_invalidate),
  .cmu_icache_invalidate_way(cmu_icache_invalidate_way[2:0]),
  .cmu_icache_invalidate_index(cmu_icache_invalidate_index[10:5]),
  .cmu_icache_inv_way1(cmu_icache_inv_way1[2:0]),
  .cmu_evic_invalidate(cmu_evic_invalidate),
  .cmu_inval_ack(cmu_inval_ack[7:0]),
  .cmu_l2_err(cmu_l2_err[1:0]),
  .ifu_l15_valid(ifu_l15_valid),
  .ifu_l15_cpkt(ifu_l15_cpkt[7:0]),
  .ifu_l15_addr(ifu_l15_addr[39:0]),
  .ifu_lsu_if_vld(ifu_lsu_if_vld),
  .ifu_lsu_if_tid(ifu_lsu_if_tid[2:0]),
  .ifu_lsu_if_addr(ifu_lsu_if_addr[10:5])
);


dec dec (
	.scan_in(dec_scanin),
	.scan_out(dec_scanout),
	.l2clk(l2clk),
        .tcu_pce_ov(pce_ov_bl),
        .tcu_scan_en(lb_scan_en_bl),
	.spc_aclk(spc_aclk_bl),
	.spc_bclk(spc_bclk_bl),
	.tlu_dtlb_reload_stall	(mmu_dtlb_reload_stall),
        .power_throttle(power_throttle_buf[2:0]),
	.spc_core_running_status(tlu_core_running_status[7:0]),
	.fgu_ecc_asi_stall(lsu_frf_read_pending),
  .lb_lbist_running(lb_lbist_running),
  .lsu_dec_pmen(lsu_dec_pmen),
  .lsu_exu_pmen(lsu_exu_pmen),
  .exu_test_tid0(exu_test_tid0[1:0]),
  .exu_test_addr0(exu_test_addr0[4:0]),
  .exu_test_valid0(exu_test_valid0),
  .exu_test_tid1(exu_test_tid1[1:0]),
  .exu_test_addr1(exu_test_addr1[4:0]),
  .exu_test_valid1(exu_test_valid1),
  .tlu_cerer_icdp(tlu_cerer_icdp),
  .tlu_dec_pstate_pef(tlu_dec_pstate_pef[7:0]),
  .fgu_fprs_fef(fgu_fprs_fef[7:0]),
  .tlu_dec_hpstate_hpriv(tlu_dec_hpstate_hpriv[7:0]),
  .tlu_dec_pstate_priv(tlu_dec_pstate_priv[7:0]),
  .tlu_pstate_am(tlu_pstate_am[7:0]),
  .tlu_window_block(tlu_window_block[1:0]),
  .exu0_window_block(exu0_window_block),
  .exu1_window_block(exu1_window_block),
  .lsu_cpq_stall(lsu_cpq_stall),
  .ifu_buf0_inst0(ifu_buf0_inst0[32:0]),
  .ifu_buf0_inst1(ifu_buf0_inst1[32:0]),
  .ifu_buf0_inst2(ifu_buf0_inst2[32:0]),
  .ifu_buf0_inst3(ifu_buf0_inst3[32:0]),
  .ifu_buf0_inst4(ifu_buf0_inst4[32:0]),
  .ifu_buf0_inst5(ifu_buf0_inst5[32:0]),
  .ifu_buf0_inst6(ifu_buf0_inst6[32:0]),
  .ifu_buf0_inst7(ifu_buf0_inst7[32:0]),
  .ifu_buf0_excp0(ifu_buf0_excp0[4:0]),
  .ifu_buf0_excp1(ifu_buf0_excp1[4:0]),
  .ifu_buf0_excp2(ifu_buf0_excp2[4:0]),
  .ifu_buf0_excp3(ifu_buf0_excp3[4:0]),
  .ifu_buf0_excp4(ifu_buf0_excp4[4:0]),
  .ifu_buf0_excp5(ifu_buf0_excp5[4:0]),
  .ifu_buf0_excp6(ifu_buf0_excp6[4:0]),
  .ifu_buf0_excp7(ifu_buf0_excp7[4:0]),
  .tlu_flush_ifu(tlu_flush_ifu[7:0]),
  .pku_load_flush_w(pku_load_flush_w[7:0]),
  .pku_inst_cnt_brtaken00(pku_inst_cnt_brtaken00[1:0]),
  .pku_inst_cnt_brtaken01(pku_inst_cnt_brtaken01[1:0]),
  .pku_inst_cnt_brtaken02(pku_inst_cnt_brtaken02[1:0]),
  .pku_inst_cnt_brtaken03(pku_inst_cnt_brtaken03[1:0]),
  .pku_inst_cnt_brtaken04(pku_inst_cnt_brtaken04[1:0]),
  .pku_inst_cnt_brtaken05(pku_inst_cnt_brtaken05[1:0]),
  .pku_inst_cnt_brtaken06(pku_inst_cnt_brtaken06[1:0]),
  .pku_inst_cnt_brtaken07(pku_inst_cnt_brtaken07[1:0]),
  .pku_inst_cnt_brtaken10(pku_inst_cnt_brtaken10[1:0]),
  .pku_inst_cnt_brtaken11(pku_inst_cnt_brtaken11[1:0]),
  .pku_inst_cnt_brtaken12(pku_inst_cnt_brtaken12[1:0]),
  .pku_inst_cnt_brtaken13(pku_inst_cnt_brtaken13[1:0]),
  .pku_inst_cnt_brtaken14(pku_inst_cnt_brtaken14[1:0]),
  .pku_inst_cnt_brtaken15(pku_inst_cnt_brtaken15[1:0]),
  .pku_inst_cnt_brtaken16(pku_inst_cnt_brtaken16[1:0]),
  .pku_inst_cnt_brtaken17(pku_inst_cnt_brtaken17[1:0]),
  .pku_base_pick_p(pku_base_pick_p[7:0]),
  .pku_raw_pick0_p(pku_raw_pick0_p[3:0]),
  .pku_raw_pick1_p(pku_raw_pick1_p[7:4]),
  .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[7:0]),
  .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[7:0]),
  .pku_valid_e(pku_valid_e[7:0]),
  .pku_ds_e(pku_ds_e[7:0]),
  .pku_lsu_p(pku_lsu_p[7:0]),
  .pku_fgu_p(pku_fgu_p[7:0]),
  .pku_pdist_p(pku_pdist_p[7:0]),
  .pku_twocycle_p(pku_twocycle_p[7:0]),
  .pku_idest_p(pku_idest_p[7:0]),
  .pku_fdest_p(pku_fdest_p[7:0]),
  .pku_fsrc_rd_p(pku_fsrc_rd_p[7:0]),
  .pku_isrc_rs1_p(pku_isrc_rs1_p[7:0]),
  .pku_isrc_rs2_p(pku_isrc_rs2_p[7:0]),
  .pku_isrc_rd_p(pku_isrc_rd_p[7:0]),
  .pku_flush_f1(pku_flush_f1[7:0]),
  .pku_flush_f2(pku_flush_f2[7:0]),
  .pku_flush_lm(pku_flush_lm[7:0]),
  .pku_flush_lb(pku_flush_lb[7:0]),
  .pku_flush_m(pku_flush_m[7:0]),
  .pku_flush_b(pku_flush_b[7:0]),
  .spu_mult_request(spu_mult_request),
  .lsu_block_store_stall(lsu_block_store_stall),
  .lsu_block_store_rd(lsu_block_store_rd[4:3]),
  .lsu_block_store_tid(lsu_block_store_tid[2:0]),
  .exu0_oddwin_b(exu0_oddwin_b[3:0]),
  .exu1_oddwin_b(exu1_oddwin_b[3:0]),
  .fgu_idiv_stall(fgu_idiv_stall[1:0]),
  .fgu_fdiv_stall(fgu_fdiv_stall),
  .dec_br_taken_e1(dec_br_taken_e1[1:0]),
  .del_pick_d(del_pick_d[7:0]),
  .dec_inst0_rd_d(dec_inst0_rd_d[4:0]),
  .dec_inst1_rd_d(dec_inst1_rd_d[4:0]),
  .dec_rs1_addr0_e(dec_rs1_addr0_e),
  .dec_rs1_addr1_e(dec_rs1_addr1_e),
  .dec_inst0_d(dec_inst0_d[32:0]),
  .dec_inst1_d(dec_inst1_d[32:0]),
  .dec_decode0_d(dec_decode0_d),
  .dec_decode1_d(dec_decode1_d),
  .dec_valid0_d(dec_valid0_d),
  .dec_valid1_d(dec_valid1_d),
  .dec_true_valid_e(dec_true_valid_e[1:0]),
  .dec_tid0_d(dec_tid0_d[1:0]),
  .dec_tid1_d(dec_tid1_d[1:0]),
  .dec_tid0_p(dec_tid0_p[1:0]),
  .dec_tid1_p(dec_tid1_p[1:0]),
  .dec_raw_pick_p(dec_raw_pick_p[7:0]),
  .dec_inst0_rs1_p(dec_inst0_rs1_p[4:0]),
  .dec_inst0_rs2_p(dec_inst0_rs2_p[4:0]),
  .dec_inst0_rs3_p(dec_inst0_rs3_p[4:0]),
  .dec_inst0_rs1_vld_p(dec_inst0_rs1_vld_p),
  .dec_inst0_rs2_vld_p(dec_inst0_rs2_vld_p),
  .dec_inst0_rs3_vld_p(dec_inst0_rs3_vld_p),
  .dec_inst1_rs1_p(dec_inst1_rs1_p[4:0]),
  .dec_inst1_rs2_p(dec_inst1_rs2_p[4:0]),
  .dec_inst1_rs3_p(dec_inst1_rs3_p[4:0]),
  .dec_inst1_rs1_vld_p(dec_inst1_rs1_vld_p),
  .dec_inst1_rs2_vld_p(dec_inst1_rs2_vld_p),
  .dec_inst1_rs3_vld_p(dec_inst1_rs3_vld_p),
  .dec_frf_r1_addr_d(dec_frf_r1_addr_d[4:0]),
  .dec_frf_r2_addr_d(dec_frf_r2_addr_d[4:0]),
  .dec_frf_r1_vld_d(dec_frf_r1_vld_d),
  .dec_frf_r2_vld_d(dec_frf_r2_vld_d),
  .dec_frf_r1_32b_d(dec_frf_r1_32b_d),
  .dec_frf_r2_32b_d(dec_frf_r2_32b_d),
  .dec_frf_r1_odd32b_d(dec_frf_r1_odd32b_d),
  .dec_frf_r2_odd32b_d(dec_frf_r2_odd32b_d),
  .dec_frf_w_addr_d(dec_frf_w_addr_d[4:0]),
  .dec_frf_w_vld_d(dec_frf_w_vld_d),
  .dec_frf_w_32b_d(dec_frf_w_32b_d),
  .dec_frf_w_odd32b_d(dec_frf_w_odd32b_d),
  .dec_exu_src_vld_d(dec_exu_src_vld_d),
  .dec_irf_w_addr_d(dec_irf_w_addr_d[4:0]),
  .dec_frf_store_d(dec_frf_store_d),
  .dec_fsr_store_d(dec_fsr_store_d),
  .dec_fgu_op3_d(dec_fgu_op3_d[5:0]),
  .dec_fgu_opf_d(dec_fgu_opf_d[7:0]),
  .dec_fgu_decode_d(dec_fgu_decode_d),
  .dec_fgu_tid_d(dec_fgu_tid_d[2:0]),
  .dec_flush_f1(dec_flush_f1),
  .dec_flush_f2(dec_flush_f2),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .dec_flush_m(dec_flush_m[1:0]),
  .dec_flush_b(dec_flush_b[1:0]),
  .dec_spu_grant_d(dec_spu_grant_d),
  .dec_spu_grant_fgu_d(dec_spu_grant_fgu_d),
  .dec_block_store_b(dec_block_store_b[7:0]),
  .dec_load_flush_w(dec_load_flush_w[1:0]),
  .dec_exc0_m(dec_exc0_m[4:0]),
  .dec_exc1_m(dec_exc1_m[4:0]),
  .dec_inst0_cnt(dec_inst0_cnt[1:0]),
  .dec_inst1_cnt(dec_inst1_cnt[1:0]),
  .dec_tid0_m(dec_tid0_m[1:0]),
  .dec_tid1_m(dec_tid1_m[1:0]),
  .dec_inst_valid_m(dec_inst_valid_m[1:0]),
  .dec_lsu_inst_m(dec_lsu_inst_m[1:0]),
  .dec_fgu_inst_m(dec_fgu_inst_m[1:0]),
  .dec_cti_inst_m(dec_cti_inst_m[1:0]),
  .dec_illegal_inst_m(dec_illegal_inst_m[1:0]),
  .dec_icache_perr_m(dec_icache_perr_m[1:0]),
  .dec_priv_exc_m(dec_priv_exc_m[1:0]),
  .dec_hpriv_exc_m(dec_hpriv_exc_m[1:0]),
  .dec_fpdisable_exc_m(dec_fpdisable_exc_m[1:0]),
  .dec_br_taken_m(dec_br_taken_m[1:0]),
  .dec_done_inst_m(dec_done_inst_m[1:0]),
  .dec_retry_inst_m(dec_retry_inst_m[1:0]),
  .dec_sir_inst_m(dec_sir_inst_m[1:0]),
  .dec_annul_ds_m(dec_annul_ds_m[1:0]),
  .dec_ds_m(dec_ds_m[1:0]),
  .dec_fgu_sel_e(dec_fgu_sel_e[1:0]),
  .dec_fgu_sel_m(dec_fgu_sel_m[1:0]),
  .dec_lsu_sel0_e(dec_lsu_sel0_e),
  .dec_lsu_sel1_e(dec_lsu_sel1_e),
  .dec_lsu_sel0_lower_e(dec_lsu_sel0_lower_e),
  .dec_lsu_sel1_lower_e(dec_lsu_sel1_lower_e),
  .dec_lsu_sel0_upper_e(dec_lsu_sel0_upper_e),
  .dec_lsu_sel1_upper_e(dec_lsu_sel1_upper_e),
  .dec_rs1_addr0_upper_e(dec_rs1_addr0_upper_e),
  .dec_rs1_addr1_upper_e(dec_rs1_addr1_upper_e),
  .dec_ld_inst_e(dec_ld_inst_e),
  .dec_st_inst_e(dec_st_inst_e),
  .dec_fsr_ldst_e(dec_fsr_ldst_e),
  .dec_fpldst_inst_e(dec_fpldst_inst_e),
  .dec_ldst_dbl_e(dec_ldst_dbl_e),
  .dec_pref_inst_e(dec_pref_inst_e),
  .dec_flush_inst_e(dec_flush_inst_e),
  .dec_memstbar_inst_e(dec_memstbar_inst_e),
  .dec_ldst_sz_e(dec_ldst_sz_e[1:0]),
  .dec_frf_r2_addr_e(dec_frf_r2_addr_e[4:3]),
  .dec_sr_inst_e(dec_sr_inst_e),
  .dec_pr_inst_e(dec_pr_inst_e),
  .dec_hpr_inst_e(dec_hpr_inst_e),
  .dec_casa_inst_e(dec_casa_inst_e),
  .dec_ldstub_inst_e(dec_ldstub_inst_e),
  .dec_swap_inst_e(dec_swap_inst_e),
  .dec_altspace_d(dec_altspace_d),
  .dec_sign_ext_e(dec_sign_ext_e),
  .dec_sraddr_e(dec_sraddr_e[4:0]),
  .dec_imm_asi_vld_d(dec_imm_asi_vld_d),
  .dec_imm_asi_d(dec_imm_asi_d[7:0]),
  .dec_lsu_tid0_d(dec_lsu_tid0_d[1:0]),
  .dec_lsu_tid1_d(dec_lsu_tid1_d[1:0]),
  .dec_lsu_tg_d(dec_lsu_tg_d),
  .dec_lsu_rd_e(dec_lsu_rd_e[4:0]),
  .dec_ld_inst_d(dec_ld_inst_d),
  .dec_instr0_type_d(dec_instr0_type_d[9:0]),
  .dec_instr1_type_d(dec_instr1_type_d[9:0]),
  .dec_valid_e(dec_valid_e[1:0]),
  .dec_pmu_valid_e(dec_pmu_valid_e[1:0]),
  .dec_fgu_valid_e(dec_fgu_valid_e),
  .dec_exu_clken(dec_exu_clken[1:0]),
  .dec_lsu_sel0_d(dec_lsu_sel0_d),
  .dec_ierr_d(dec_ierr_d[1:0]),
  .dec_block_store_stall(dec_block_store_stall[7:0])
);


pku pku (
	.scan_in(pku_scanin),
	.scan_out(pku_scanout),
	.l2clk(l2clk),
        .tcu_pce_ov(pce_ov_bl),
        .tcu_scan_en(lb_scan_en_bl),
        .tcu_do_mode(msf0_do_mode),
	.spc_aclk(spc_aclk_bl),
	.spc_bclk(spc_bclk_bl),
	.dec_br_taken_e(dec_br_taken_e1[1:0]),
	.lsu_spec_enable(tlu_spec_enable[7:0]),
	.spc_core_running_status(tlu_core_running_status[7:0]),
  .tlu_halted(tlu_halted[7:0]),
  .dec_block_store_stall(dec_block_store_stall[7:0]),
  .dec_ierr_d(dec_ierr_d[1:0]),
  .lsu_pku_pmen(lsu_pku_pmen),
  .tlu_retry_state(tlu_retry_state[7:0]),
  .tlu_flush_ifu(tlu_flush_ifu[7:0]),
  .dec_true_valid_e(dec_true_valid_e[1:0]),
  .dec_decode0_d(dec_decode0_d),
  .dec_decode1_d(dec_decode1_d),
  .dec_valid0_d(dec_valid0_d),
  .dec_valid1_d(dec_valid1_d),
  .lsu_sync(lsu_sync[7:0]),
  .lsu_complete(lsu_complete[7:0]),
  .fgu_divide_completion(fgu_divide_completion[7:0]),
  .ifu_ibuffer_write_c(ifu_ibuffer_write_c[7:0]),
  .lsu_stb_alloc(lsu_stb_alloc[7:0]),
  .lsu_stb_dealloc(lsu_stb_dealloc[7:0]),
  .lsu_block_store_kill(lsu_block_store_kill[7:0]),
  .ifu_buf0_inst0(ifu_buf0_inst0[31:0]),
  .ifu_buf0_inst1(ifu_buf0_inst1[31:0]),
  .ifu_buf0_inst2(ifu_buf0_inst2[31:0]),
  .ifu_buf0_inst3(ifu_buf0_inst3[31:0]),
  .ifu_buf0_inst4(ifu_buf0_inst4[31:0]),
  .ifu_buf0_inst5(ifu_buf0_inst5[31:0]),
  .ifu_buf0_inst6(ifu_buf0_inst6[31:0]),
  .ifu_buf0_inst7(ifu_buf0_inst7[31:0]),
  .ifu_buf0_valid_p(ifu_buf0_valid_p[7:0]),
  .ifu_upper_buffer_valid_p(ifu_upper_buffer_valid_p[7:0]),
  .pku_raw_pick0_p(pku_raw_pick0_p[3:0]),
  .pku_raw_pick1_p(pku_raw_pick1_p[7:4]),
  .pku_base_pick_p(pku_base_pick_p[7:0]),
  .pku_pick_p(pku_pick_p[7:0]),
  .pku_lsu_p(pku_lsu_p[7:0]),
  .pku_fgu_p(pku_fgu_p[7:0]),
  .pku_pdist_p(pku_pdist_p[7:0]),
  .pku_twocycle_p(pku_twocycle_p[7:0]),
  .pku_idest_p(pku_idest_p[7:0]),
  .pku_fdest_p(pku_fdest_p[7:0]),
  .pku_fsrc_rd_p(pku_fsrc_rd_p[7:0]),
  .pku_isrc_rs1_p(pku_isrc_rs1_p[7:0]),
  .pku_isrc_rs2_p(pku_isrc_rs2_p[7:0]),
  .pku_isrc_rd_p(pku_isrc_rd_p[7:0]),
  .pku_valid_e(pku_valid_e[7:0]),
  .pku_annul_ds_dcti_brtaken0_e(pku_annul_ds_dcti_brtaken0_e[7:0]),
  .pku_annul_ds_dcti_brtaken1_e(pku_annul_ds_dcti_brtaken1_e[7:0]),
  .pku_flush_f1(pku_flush_f1[7:0]),
  .pku_flush_f2(pku_flush_f2[7:0]),
  .pku_flush_lb(pku_flush_lb[7:0]),
  .pku_flush_lm(pku_flush_lm[7:0]),
  .pku_flush_m(pku_flush_m[7:0]),
  .pku_flush_b(pku_flush_b[7:0]),
  .pku_load_flush_w(pku_load_flush_w[7:0]),
  .pku_ds_e(pku_ds_e[7:0]),
  .pku_flush_upper_buffer(pku_flush_upper_buffer[7:0]),
  .pku_flush_buffer0(pku_flush_buffer0[7:0]),
  .pku_quiesce(pku_quiesce[7:0]),
  .pku_inst_cnt_brtaken00(pku_inst_cnt_brtaken00[1:0]),
  .pku_inst_cnt_brtaken01(pku_inst_cnt_brtaken01[1:0]),
  .pku_inst_cnt_brtaken02(pku_inst_cnt_brtaken02[1:0]),
  .pku_inst_cnt_brtaken03(pku_inst_cnt_brtaken03[1:0]),
  .pku_inst_cnt_brtaken04(pku_inst_cnt_brtaken04[1:0]),
  .pku_inst_cnt_brtaken05(pku_inst_cnt_brtaken05[1:0]),
  .pku_inst_cnt_brtaken06(pku_inst_cnt_brtaken06[1:0]),
  .pku_inst_cnt_brtaken07(pku_inst_cnt_brtaken07[1:0]),
  .pku_inst_cnt_brtaken10(pku_inst_cnt_brtaken10[1:0]),
  .pku_inst_cnt_brtaken11(pku_inst_cnt_brtaken11[1:0]),
  .pku_inst_cnt_brtaken12(pku_inst_cnt_brtaken12[1:0]),
  .pku_inst_cnt_brtaken13(pku_inst_cnt_brtaken13[1:0]),
  .pku_inst_cnt_brtaken14(pku_inst_cnt_brtaken14[1:0]),
  .pku_inst_cnt_brtaken15(pku_inst_cnt_brtaken15[1:0]),
  .pku_inst_cnt_brtaken16(pku_inst_cnt_brtaken16[1:0]),
  .pku_inst_cnt_brtaken17(pku_inst_cnt_brtaken17[1:0])
);


exu exu0 (
	.scan_in(exu0_scanin),
	.scan_out(exu0_scanout),
	.wmr_scan_in(wmr_protect_scanin),
	.wmr_scan_out(exu0_wmr_scanout),
	.l2clk			(l2clk				),
        .tcu_dectest		(tcu_dectest_buf		),
        .tcu_muxtest		(tcu_muxtest_buf		),
        .tcu_array_wr_inhibit	(clk_array_wr_inhibit	),
        .tcu_pce_ov		(pce_ov_tr			),
        .tcu_scan_en		(lb_scan_en_tr			),
	.spc_aclk               (spc_aclk_tr                    ),
	.spc_aclk_wmr           (spc_aclk_wmr_tr                ),
	.spc_bclk               (spc_bclk_tr                    ),
        .tcu_se_scancollar_in	(lb_se_sc_in			),
	.in_rngl_cdbus		(ifu_rngl_cdbus[64:0]		),
	.dec_pick_d		(del_pick_d[3:0]		),
	.dec_tid_p		(dec_tid0_p[1:0]		),
	.dec_inst_rs1_vld_p	(dec_inst0_rs1_vld_p		),
	.dec_inst_rs2_vld_p	(dec_inst0_rs2_vld_p		),
	.dec_inst_rs3_vld_p	(dec_inst0_rs3_vld_p		),
	.dec_inst_rs1_p		(dec_inst0_rs1_p[4:0]		),
	.dec_inst_rs2_p		(dec_inst0_rs2_p[4:0]		),
	.dec_inst_rs3_p		(dec_inst0_rs3_p[4:0]		),
	.dec_exu_clken		(dec_exu_clken[0]		),
	.dec_inst_d		(dec_inst0_d[31:0]		),
	.dec_inst_rd_d		(dec_inst0_rd_d[4:0]		),
	.dec_decode_d		(dec_decode0_d			),	
	.dec_valid_e		(dec_valid_e[0]			),
	.dec_flush_m		(dec_flush_m[0]			),
	.dec_flush_b		(dec_flush_b[0]			),
	.dec_thread_group	(1'b0				),
	.fgu_exu_result_fx5	(fgu_exu_result_fx5_rep1[63:0]	),
	.fgu_exu_w_vld_fx5	(fgu_exu_w_vld_fx5[0]		),
	.tlu_pc_d		(tlu_pc_0_d[47:2]		),
	.tlu_itlb_bypass_e	(tlu_itlb_bypass_e[0]		),
	.tlu_flush_exu_b	(tlu_flush_exu_b[0]		),
	.tlu_ccr		(tlu_ccr_0[7:0]			),
	.tlu_cwp		(tlu_cwp_0[2:0]			),
	.tlu_ccr_cwp_valid	(tlu_ccr_cwp_0_valid		),
	.tlu_ccr_cwp_tid	(tlu_ccr_cwp_0_tid[1:0]		),
	.tlu_pstate_am		(tlu_pstate_am[3:0]		),
	.tlu_gl_thr0   		(tlu_gl0[1:0] 			),
	.tlu_gl_thr1   		(tlu_gl1[1:0] 			),
	.tlu_gl_thr2   		(tlu_gl2[1:0] 			),
	.tlu_gl_thr3   		(tlu_gl3[1:0] 			),
	.tlu_cerer_irf		(tlu_cerer_irf			),
	.tlu_ceter_pscce	(tlu_ceter_pscce[3:0]		),
	.mbi_run		(mb2_run			),
	.mbi_addr		(mb2_addr[9:0]			),
	.mbi_write_data_p1	(mb2_write_data_p1[7:0]		),
	.mbi_irf_write_en	(mb2_irf_write_en		),
	.mbi_irf_read_en	(mb2_irf_read_en		),
	.mbi_irf_save_en	(mb2_irf_save_en		),
	.mbi_irf_restore_en	(mb2_irf_restore_en		),
	.spc_core_running_status(tlu_core_running_status[3:0]	),
	.lsu_asi_error_inject_b31(lsu_asi_error_inject[31]	),
	.lsu_asi_error_inject_b25(lsu_asi_error_inject[25]	),
	.lsu_exu_ld_data_b	(lsu_exu_ld_data_b_rep00[63:0]	),
	.exu_rngl_cdbus			(exu0_rngl_cdbus[64:0]		),
	.exu_address_e			(exu_address0_e[47:0]		),
	.exu_mdp_mux_sel_e		(exu0_mdp_mux_sel_e[5:0]	),
	.exu_ms_icc_e			(exu_ms_icc0_e			),
	.exu_rs1_data_e			(exu_rs1_data0_e[63:0]		),
	.exu_rs2_data_e			(exu_rs2_data0_e[63:0]		),
	.exu_store_data_e		(exu_store_data0_e[63:0]	),
	.exu_oddwin_b			(exu0_oddwin_b[3:0]		),
	.exu_cecc_m			(exu_cecc_m[0]			),
	.exu_uecc_m			(exu_uecc_m[0]			),
	.exu_misalign_m			(exu_misalign_m[0]		),
	.exu_oor_va_m			(exu_oor_va_m[0]		),
	.exu_tcc_m			(exu_tcc_m[0]			),
	.exu_tof_m			(exu_tof_m[0]			),
	.exu_trap_number_b		(exu0_trap_number_b[7:0]	),
	.exu_spill_b			(exu_spill_b[0]			),
	.exu_fill_m			(exu_fill_m[0]			),
	.exu_normal_b			(exu_normal_b[0]		),
	.exu_cleanwin_b			(exu_cleanwin_b[0]		),
	.exu_wstate_b			(exu0_wstate_b[2:0]		),
	.exu_ccr0			(exu0_ccr0[7:0]			),
	.exu_ccr1			(exu0_ccr1[7:0]			),
	.exu_ccr2			(exu0_ccr2[7:0]			),
	.exu_ccr3			(exu0_ccr3[7:0]			),
	.exu_ecc_m			(exu_ecc_m[0]			),
	.exu_ecc_check_m		(exu0_ecc_check_m[7:0]		),
	.exu_ecc_addr_m			(exu0_ecc_addr_m[4:0]		),
	.exu_gsr_data_m			(exu_gsr_data0_m[31:0]		),
	.exu_gsr_vld_m			(exu_gsr_vld0_m[1:0]		),
	.exu_cmov_true_m		(exu_cmov_true_m[0]		),
	.exu_br_taken_e			(dec_br_taken_e[0]		),
	.exu_br_taken_e1		(dec_br_taken_e1[0]		),
	.exu_ibp_m			(exu_ibp_m[0]			),
	.exu_lsu_va_error_m		(exu_lsu_va_error_m[0]		),
	.exu_y_data_e			(exu_y_data0_e[31:0]		),
	.exu_cwp_thr0			(exu0_cwp0[2:0]			),
	.exu_cwp_thr1			(exu0_cwp1[2:0]			),
	.exu_cwp_thr2			(exu0_cwp2[2:0]			),
	.exu_cwp_thr3			(exu0_cwp3[2:0]			),
        .exu_window_block_m		(exu0_window_block              ),
	.exu_tlu_window_block		(exu_tlu_window_block[0]        ),
	.exu_ecc_winop_flush_m		(exu_ecc_winop_flush_m[0]	),
        .exu_test_valid			(exu_test_valid0		),
	.exu_test_tid			(exu_test_tid0[1:0]		),
	.exu_test_addr			(exu_test_addr0[4:0]		),
	.exu_mbi_irf_fail_		(exu0_mbi_irf_fail_[1:0]	),
  .fgu_exu_icc_fx5(fgu_exu_icc_fx5[3:0]),
  .fgu_exu_xcc_fx5(fgu_exu_xcc_fx5[1:0]),
  .fgu_exu_cc_vld_fx5(fgu_exu_cc_vld_fx5),
  .fgu_result_tid_fx5(fgu_result_tid_fx5[1:0]),
  .fgu_irf_w_addr_fx5(fgu_irf_w_addr_fx5[4:0]),
  .lsu_exu_ld_b(lsu_exu_ld_b),
  .lsu_exu_rd_m(lsu_exu_rd_m[4:0]),
  .lsu_exu_tid_m(lsu_exu_tid_m[2:0]),
  .lsu_exu_ld_vld_w(lsu_exu_ld_vld_w),
  .lsu_asi_error_inject(lsu_asi_error_inject[7:0]),
  .lsu_exu_pmen(lsu_exu_pmen),
  .lsu_asi_clken(lsu_asi_clken),
  .fgu_fld_fcc_fx3(fgu_fld_fcc_fx3[7:0]),
  .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]),
  .fgu_fld_fcc_vld_fx3(fgu_fld_fcc_vld_fx3[1:0]),
  .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w),
  .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]),
  .fgu_cmp_fcc_tid_fx2(fgu_cmp_fcc_tid_fx2[2:0]),
  .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0])
);


exu exu1 (
        .scan_in(exu1_scanin),
        .scan_out(exu1_scanout),
	.wmr_scan_in(exu0_wmr_scanout),
	.wmr_scan_out(exu1_wmr_scanout),
        .l2clk(l2clk),
        .tcu_dectest		(tcu_dectest_buf		),
        .tcu_muxtest		(tcu_muxtest_buf		),
        .tcu_array_wr_inhibit	(clk_array_wr_inhibit	),
        .tcu_pce_ov		(pce_ov_tr			),
        .tcu_scan_en		(lb_scan_en_tr			),
	.spc_aclk               (spc_aclk_tr                    ),
	.spc_aclk_wmr           (spc_aclk_wmr_tr                ),
	.spc_bclk               (spc_bclk_tr                    ),
        .tcu_se_scancollar_in   (lb_se_sc_in			),
	.in_rngl_cdbus		(fgu_rngl_cdbus[64:0]		),
	.dec_pick_d		(del_pick_d[7:4]		),
	.dec_tid_p		(dec_tid1_p[1:0]		),
	.dec_inst_rs1_vld_p	(dec_inst1_rs1_vld_p		),
	.dec_inst_rs2_vld_p	(dec_inst1_rs2_vld_p		),
	.dec_inst_rs3_vld_p	(dec_inst1_rs3_vld_p		),
	.dec_inst_rs1_p		(dec_inst1_rs1_p[4:0]		),
	.dec_inst_rs2_p		(dec_inst1_rs2_p[4:0]		),
	.dec_inst_rs3_p		(dec_inst1_rs3_p[4:0]		),
	.dec_exu_clken		(dec_exu_clken[1]		),
	.dec_inst_d		(dec_inst1_d[31:0]		),
	.dec_inst_rd_d		(dec_inst1_rd_d[4:0]		),
	.dec_decode_d		(dec_decode1_d			),	
	.dec_valid_e		(dec_valid_e[1]			),
	.dec_flush_m		(dec_flush_m[1]			),
	.dec_flush_b		(dec_flush_b[1]			),
	.dec_thread_group	(1'b1				),
	.fgu_exu_result_fx5	(fgu_exu_result_fx5_rep0[63:0]	),
	.fgu_exu_w_vld_fx5	(fgu_exu_w_vld_fx5[1]		),
	.tlu_pc_d		(tlu_pc_1_d[47:2]		),
	.tlu_itlb_bypass_e	(tlu_itlb_bypass_e[1]		),
	.tlu_flush_exu_b	(tlu_flush_exu_b[1]		),
	.tlu_ccr		(tlu_ccr_1[7:0]			),
	.tlu_cwp		(tlu_cwp_1[2:0]			),
	.tlu_ccr_cwp_valid	(tlu_ccr_cwp_1_valid		),
	.tlu_ccr_cwp_tid	(tlu_ccr_cwp_1_tid[1:0]		),
	.tlu_pstate_am		(tlu_pstate_am[7:4]		),
	.tlu_gl_thr0   		(tlu_gl4[1:0] 			),
	.tlu_gl_thr1   		(tlu_gl5[1:0] 			),
	.tlu_gl_thr2   		(tlu_gl6[1:0] 			),
	.tlu_gl_thr3   		(tlu_gl7[1:0] 			),
	.tlu_cerer_irf		(tlu_cerer_irf			),
	.tlu_ceter_pscce	(tlu_ceter_pscce[7:4]		),
	.mbi_run		(mb2_run			),
	.mbi_addr		(mb2_addr[9:0]			),
	.mbi_write_data_p1	(mb2_write_data_p1[7:0]		),
	.mbi_irf_write_en	(mb2_irf_write_en		),
	.mbi_irf_read_en	(mb2_irf_read_en		),
	.mbi_irf_save_en	(mb2_irf_save_en		),
	.mbi_irf_restore_en	(mb2_irf_restore_en		),
	.spc_core_running_status(tlu_core_running_status[7:4]	),
	.lsu_asi_error_inject_b31(lsu_asi_error_inject[31]	),
	.lsu_asi_error_inject_b25(lsu_asi_error_inject[25]	),
	.lsu_exu_ld_data_b	(lsu_exu_ld_data_b_rep01[63:0]	),
	.exu_rngl_cdbus			(exu1_rngl_cdbus[64:0]		),
	.exu_address_e			(exu_address1_e[47:0]		),
	.exu_mdp_mux_sel_e		(exu1_mdp_mux_sel_e[5:0]	),
	.exu_ms_icc_e			(exu_ms_icc1_e			),
	.exu_rs1_data_e			(exu_rs1_data1_e[63:0]		),
	.exu_rs2_data_e			(exu_rs2_data1_e[63:0]		),
	.exu_store_data_e		(exu_store_data1_e[63:0]	),
	.exu_oddwin_b			(exu1_oddwin_b[3:0]		),
	.exu_cecc_m			(exu_cecc_m[1]			),
	.exu_uecc_m			(exu_uecc_m[1]			),
	.exu_misalign_m			(exu_misalign_m[1]		),
	.exu_oor_va_m			(exu_oor_va_m[1]		),
	.exu_tcc_m			(exu_tcc_m[1]			),
	.exu_tof_m			(exu_tof_m[1]			),
	.exu_trap_number_b		(exu1_trap_number_b[7:0]	),
	.exu_spill_b			(exu_spill_b[1]			),
	.exu_fill_m			(exu_fill_m[1]			),
	.exu_normal_b			(exu_normal_b[1]		),
	.exu_cleanwin_b			(exu_cleanwin_b[1]		),
	.exu_wstate_b			(exu1_wstate_b[2:0]		),
	.exu_ccr0			(exu1_ccr0[7:0]			),
	.exu_ccr1			(exu1_ccr1[7:0]			),
	.exu_ccr2			(exu1_ccr2[7:0]			),
	.exu_ccr3			(exu1_ccr3[7:0]			),
	.exu_ecc_m			(exu_ecc_m[1]			),
	.exu_ecc_check_m		(exu1_ecc_check_m[7:0]		),
	.exu_ecc_addr_m			(exu1_ecc_addr_m[4:0]		),
	.exu_gsr_data_m			(exu_gsr_data1_m[31:0]		),
	.exu_gsr_vld_m			(exu_gsr_vld1_m[1:0]		),
	.exu_cmov_true_m		(exu_cmov_true_m[1]		),
	.exu_br_taken_e			(dec_br_taken_e[1]		),
	.exu_br_taken_e1		(dec_br_taken_e1[1]		),
	.exu_ibp_m			(exu_ibp_m[1]			),
	.exu_lsu_va_error_m		(exu_lsu_va_error_m[1]		),
	.exu_y_data_e			(exu_y_data1_e[31:0]		),
	.exu_cwp_thr0			(exu1_cwp0[2:0]			),
	.exu_cwp_thr1			(exu1_cwp1[2:0]			),
	.exu_cwp_thr2			(exu1_cwp2[2:0]			),
	.exu_cwp_thr3			(exu1_cwp3[2:0]			),
        .exu_window_block_m		(exu1_window_block              ),
	.exu_tlu_window_block		(exu_tlu_window_block[1]        ),
	.exu_ecc_winop_flush_m		(exu_ecc_winop_flush_m[1]	),
        .exu_test_valid			(exu_test_valid1		),
	.exu_test_tid			(exu_test_tid1[1:0]		),
	.exu_test_addr			(exu_test_addr1[4:0]		),
	.exu_mbi_irf_fail_		(exu1_mbi_irf_fail_[1:0]	),
  .fgu_exu_icc_fx5(fgu_exu_icc_fx5[3:0]),
  .fgu_exu_xcc_fx5(fgu_exu_xcc_fx5[1:0]),
  .fgu_exu_cc_vld_fx5(fgu_exu_cc_vld_fx5),
  .fgu_result_tid_fx5(fgu_result_tid_fx5[1:0]),
  .fgu_irf_w_addr_fx5(fgu_irf_w_addr_fx5[4:0]),
  .lsu_exu_ld_b(lsu_exu_ld_b),
  .lsu_exu_rd_m(lsu_exu_rd_m[4:0]),
  .lsu_exu_tid_m(lsu_exu_tid_m[2:0]),
  .lsu_exu_ld_vld_w(lsu_exu_ld_vld_w),
  .lsu_asi_error_inject(lsu_asi_error_inject[7:0]),
  .lsu_exu_pmen(lsu_exu_pmen),
  .lsu_asi_clken(lsu_asi_clken),
  .fgu_fld_fcc_fx3(fgu_fld_fcc_fx3[7:0]),
  .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]),
  .fgu_fld_fcc_vld_fx3(fgu_fld_fcc_vld_fx3[1:0]),
  .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w),
  .fgu_cmp_fcc_fx3(fgu_cmp_fcc_fx3[1:0]),
  .fgu_cmp_fcc_tid_fx2(fgu_cmp_fcc_tid_fx2[2:0]),
  .fgu_cmp_fcc_vld_fx3(fgu_cmp_fcc_vld_fx3[3:0])
);


// not sequential
exu_mdp_dp mdp (.tcu_dectest		(tcu_dectest_buf		),
                .tcu_muxtest		(tcu_muxtest_buf		),
  .dec_fgu_sel_e(dec_fgu_sel_e[1:0]),
  .dec_fgu_sel_m(dec_fgu_sel_m[1:0]),
  .dec_lsu_sel0_e(dec_lsu_sel0_e),
  .dec_lsu_sel1_e(dec_lsu_sel1_e),
  .dec_rs1_addr0_e(dec_rs1_addr0_e),
  .dec_rs1_addr1_e(dec_rs1_addr1_e),
  .dec_lsu_sel0_lower_e(dec_lsu_sel0_lower_e),
  .dec_lsu_sel1_lower_e(dec_lsu_sel1_lower_e),
  .dec_lsu_sel0_upper_e(dec_lsu_sel0_upper_e),
  .dec_lsu_sel1_upper_e(dec_lsu_sel1_upper_e),
  .dec_rs1_addr0_upper_e(dec_rs1_addr0_upper_e),
  .dec_rs1_addr1_upper_e(dec_rs1_addr1_upper_e),
  .exu0_mdp_mux_sel_e(exu0_mdp_mux_sel_e[5:0]),
  .exu1_mdp_mux_sel_e(exu1_mdp_mux_sel_e[5:0]),
  .exu_ms_icc0_e(exu_ms_icc0_e),
  .exu_ms_icc1_e(exu_ms_icc1_e),
  .exu_rs1_data0_e(exu_rs1_data0_e[63:0]),
  .exu_rs1_data1_e(exu_rs1_data1_e[63:0]),
  .exu_rs2_data0_e(exu_rs2_data0_e[63:0]),
  .exu_rs2_data1_e(exu_rs2_data1_e[63:0]),
  .exu_y_data0_e(exu_y_data0_e[31:0]),
  .exu_y_data1_e(exu_y_data1_e[31:0]),
  .exu_address0_e(exu_address0_e[47:0]),
  .exu_address1_e(exu_address1_e[47:0]),
  .exu_store_data0_e(exu_store_data0_e[63:0]),
  .exu_store_data1_e(exu_store_data1_e[63:0]),
  .exu_ecc_winop_flush_m(exu_ecc_winop_flush_m[1:0]),
  .exu_gsr_data0_m(exu_gsr_data0_m[31:0]),
  .exu_gsr_data1_m(exu_gsr_data1_m[31:0]),
  .exu_gsr_vld0_m(exu_gsr_vld0_m[1:0]),
  .exu_gsr_vld1_m(exu_gsr_vld1_m[1:0]),
  .exu_cmov_true_m(exu_cmov_true_m[1:0]),
  .lsu_exu_address_e(lsu_exu_address_e[47:13]),
  .lsu_sel_lsu_addr_e(lsu_sel_lsu_addr_e),
  .exu_fgu_rs1_e(exu_fgu_rs1_e[63:0]),
  .exu_fgu_rs2_e(exu_fgu_rs2_e[63:0]),
  .exu_fgu_gsr_m(exu_fgu_gsr_m[31:0]),
  .exu_fgu_gsr_vld_m(exu_fgu_gsr_vld_m[1:0]),
  .exu_fgu_flush_m(exu_fgu_flush_m),
  .exu_fgu_fmov_vld_m(exu_fgu_fmov_vld_m),
  .exu_lsu_address_e(exu_lsu_address_e[47:0]),
  .exu_lsu_store_data_e(exu_lsu_store_data_e[63:0]),
  .exu_lsu_rs2_e(exu_lsu_rs2_e[7:0])
);

tlu tlu (
	.scan_in(tlu_scanin),
	.scan_out(tlu_scanout),
	.wmr_scan_in(ifu_ftu_wmr_scanout),
	.wmr_scan_out(tlu_wmr_scanout),
	.l2clk			(l2clk				),
        .tcu_pce_ov		(pce_ov_tl			),
        .tcu_scan_en		(lb_scan_en_tl			),
	.spc_aclk               (spc_aclk_tl                    ),
	.spc_aclk_wmr           (spc_aclk_wmr_tl                ),
	.spc_bclk               (spc_bclk_tl                    ),
        .hver_mask_minor_rev	(hver_mask_minor_rev_buf[3:0] ),
        .cmp_tick_enable	(msf0_cmp_tick_enable		),
        .tcu_ss_mode		(msf0_ss_mode			),
        .tcu_do_mode		(msf0_do_mode			),
        .tcu_ss_request		(msf0_ss_request		),
        .tcu_wmr_vec_mask	(msf0_wmr_vec_mask		),
        .tcu_dectest		(tcu_dectest_buf		),
        .tcu_muxtest		(tcu_muxtest_buf		),
        .tcu_array_wr_inhibit	(clk_array_wr_inhibit	),
        .tcu_se_scancollar_in	(lb_se_sc_in			),
	.exu_address0_e		(exu_address0_e_rep0	[47:0]	),
	.exu_address1_e		(exu_address1_e_rep0	[47:0]	),
	.fgu_cecc_fx2		(fgu_cecc_fx2_rep1		),
	.fgu_uecc_fx2		(fgu_uecc_fx2_rep1		),
	.l15_spc_valid		(l15_mmu_valid			),
	.l15_spc_cpkt		(l15_spc_cpkt		[17:0]	),
	.l15_spc_data1		(l15_spc_data1		[15:0]	),
	.mbi_tsa0_write_en	(mb1_tsa0_write_en		),
	.mbi_tsa1_write_en	(mb1_tsa1_write_en		),
	.mbi_tca_write_en	(mb1_tca_write_en		),
	.mbi_addr		(mb1_addr		[4:0]	),
	.mbi_run		(mb1_run			),
	.mbi_wdata		(mb1_write_data		[7:0]	),
	.mbi_tsa0_read_en	(mb1_tsa0_read_en		),
	.mbi_tsa1_read_en	(mb1_tsa1_read_en		),
	.mbi_tca_read_en	(mb1_tca_read_en		),
	.mbi_tlu_cmpsel		(mb1_cmpsel		[3:0]	),
	.lsu_block_store_b      (dec_block_store_b	[7:0]	),
	.lsu_rngf_cdbus		(lsu_rngf_cdbus		[64:0]	),
	.lsu_va_b		(lsu_mmu_va_b		[47:0]	),
	.spu_pmu_ma_busy	(spu_pmu_ma_busy	[3]	),
        .spc_shscan_scan_out    (spc_shscan_scan_out_buf       ),
        .tcu_shscan_pce_ov      (tcu_shscan_pce_ov_buf         ),
        .tcu_shscan_clk_stop    (msf0_shscan_clk_stop		),
        .tcu_shscan_aclk        (tcu_shscan_aclk_buf           ),
        .tcu_shscan_bclk        (tcu_shscan_bclk_buf           ),
        .tcu_shscan_scan_en     (tcu_shscan_scan_en_buf        ),
        .tcu_shscan_scan_in     (tcu_shscan_scan_in_buf        ),
        .tcu_shscanid           (msf0_shscanid                  ),
        .tcu_core_running	(msf0_core_running	[7:0] ),
  .lb_scan_en_wmr(lb_scan_en_wmr),
  .lsu_asi_clken(lsu_asi_clken),
  .lsu_tlu_pmen(lsu_tlu_pmen),
  .ftu_ifu_quiesce(ftu_ifu_quiesce[7:0]),
  .pku_quiesce(pku_quiesce[7:0]),
  .ftu_excp_way_d(ftu_excp_way_d[2:0]),
  .ftu_excp_tid_d(ftu_excp_tid_d[2:0]),
  .ftu_excp_way_valid_d(ftu_excp_way_valid_d),
  .dec_inst0_cnt(dec_inst0_cnt[1:0]),
  .dec_inst1_cnt(dec_inst1_cnt[1:0]),
  .dec_raw_pick_p(dec_raw_pick_p[7:0]),
  .dec_tid0_m(dec_tid0_m[1:0]),
  .dec_tid1_m(dec_tid1_m[1:0]),
  .dec_inst_valid_m(dec_inst_valid_m[1:0]),
  .dec_lsu_inst_m(dec_lsu_inst_m[1:0]),
  .dec_fgu_inst_m(dec_fgu_inst_m[1:0]),
  .dec_illegal_inst_m(dec_illegal_inst_m[1:0]),
  .dec_exc0_m(dec_exc0_m[4:0]),
  .dec_exc1_m(dec_exc1_m[4:0]),
  .dec_done_inst_m(dec_done_inst_m[1:0]),
  .dec_retry_inst_m(dec_retry_inst_m[1:0]),
  .dec_sir_inst_m(dec_sir_inst_m[1:0]),
  .dec_hpriv_exc_m(dec_hpriv_exc_m[1:0]),
  .dec_priv_exc_m(dec_priv_exc_m[1:0]),
  .dec_fpdisable_exc_m(dec_fpdisable_exc_m[1:0]),
  .dec_br_taken_m(dec_br_taken_m[1:0]),
  .dec_annul_ds_m(dec_annul_ds_m[1:0]),
  .dec_ds_m(dec_ds_m[1:0]),
  .dec_icache_perr_m(dec_icache_perr_m[1:0]),
  .dec_cti_inst_m(dec_cti_inst_m[1:0]),
  .dec_flush_b(dec_flush_b[1:0]),
  .exu_ibp_m(exu_ibp_m[1:0]),
  .exu_tcc_m(exu_tcc_m[1:0]),
  .exu_tof_m(exu_tof_m[1:0]),
  .exu_cecc_m(exu_cecc_m[1:0]),
  .exu_uecc_m(exu_uecc_m[1:0]),
  .exu0_ecc_addr_m(exu0_ecc_addr_m[4:0]),
  .exu1_ecc_addr_m(exu1_ecc_addr_m[4:0]),
  .exu0_ecc_check_m(exu0_ecc_check_m[7:0]),
  .exu1_ecc_check_m(exu1_ecc_check_m[7:0]),
  .exu_oor_va_m(exu_oor_va_m[1:0]),
  .exu_misalign_m(exu_misalign_m[1:0]),
  .exu_spill_b(exu_spill_b[1:0]),
  .exu_fill_m(exu_fill_m[1:0]),
  .exu_normal_b(exu_normal_b[1:0]),
  .exu_cleanwin_b(exu_cleanwin_b[1:0]),
  .exu0_wstate_b(exu0_wstate_b[2:0]),
  .exu1_wstate_b(exu1_wstate_b[2:0]),
  .exu0_ccr0(exu0_ccr0[7:0]),
  .exu0_ccr1(exu0_ccr1[7:0]),
  .exu0_ccr2(exu0_ccr2[7:0]),
  .exu0_ccr3(exu0_ccr3[7:0]),
  .exu1_ccr0(exu1_ccr0[7:0]),
  .exu1_ccr1(exu1_ccr1[7:0]),
  .exu1_ccr2(exu1_ccr2[7:0]),
  .exu1_ccr3(exu1_ccr3[7:0]),
  .exu0_cwp0(exu0_cwp0[2:0]),
  .exu0_cwp1(exu0_cwp1[2:0]),
  .exu0_cwp2(exu0_cwp2[2:0]),
  .exu0_cwp3(exu0_cwp3[2:0]),
  .exu1_cwp0(exu1_cwp0[2:0]),
  .exu1_cwp1(exu1_cwp1[2:0]),
  .exu1_cwp2(exu1_cwp2[2:0]),
  .exu1_cwp3(exu1_cwp3[2:0]),
  .exu0_trap_number_b(exu0_trap_number_b[7:0]),
  .exu1_trap_number_b(exu1_trap_number_b[7:0]),
  .exu_tlu_window_block(exu_tlu_window_block[1:0]),
  .lsu_lddf_align_b(lsu_lddf_align_b),
  .lsu_stdf_align_b(lsu_stdf_align_b),
  .lsu_illegal_inst_b(lsu_illegal_inst_b),
  .lsu_daccess_prot_b(lsu_daccess_prot_b),
  .lsu_priv_action_b(lsu_priv_action_b),
  .lsu_va_watchpoint_b(lsu_va_watchpoint_b),
  .lsu_pa_watchpoint_b(lsu_pa_watchpoint_b),
  .lsu_align_b(lsu_align_b),
  .lsu_tlb_miss_b_(lsu_tlb_miss_b_),
  .lsu_dae_invalid_asi_b(lsu_dae_invalid_asi_b),
  .lsu_dae_nc_page_b(lsu_dae_nc_page_b),
  .lsu_dae_nfo_page_b(lsu_dae_nfo_page_b),
  .lsu_dae_priv_viol_b(lsu_dae_priv_viol_b),
  .lsu_dae_so_page(lsu_dae_so_page),
  .lsu_priv_action_g(lsu_priv_action_g),
  .lsu_tid_g(lsu_tid_g[2:0]),
  .lsu_trap_flush(lsu_trap_flush[7:0]),
  .lsu_tlb_bypass_b(lsu_tlb_bypass_b),
  .lsu_tlb_real_b(lsu_tlb_real_b),
  .lsu_sync_inst_b(lsu_sync_inst_b),
  .lsu_stb_empty(lsu_stb_empty[7:0]),
  .lsu_tlu_twocycle_m(lsu_tlu_twocycle_m),
  .lsu_dcmh_err_g(lsu_dcmh_err_g),
  .lsu_dcvp_err_g(lsu_dcvp_err_g),
  .lsu_dctp_err_g(lsu_dctp_err_g),
  .lsu_dcdp_err_g(lsu_dcdp_err_g),
  .lsu_dcl2c_err_g(lsu_dcl2c_err_g),
  .lsu_dcl2u_err_g(lsu_dcl2u_err_g),
  .lsu_dcl2nd_err_g(lsu_dcl2nd_err_g),
  .lsu_dcsoc_err_g(lsu_dcsoc_err_g),
  .lsu_dcerr_tid_g(lsu_dcerr_tid_g[2:0]),
  .lsu_dcerr_sfar_g(lsu_dcerr_sfar_g[8:0]),
  .lsu_sbdlc_err_g(lsu_sbdlc_err_g),
  .lsu_sbdlu_err_g(lsu_sbdlu_err_g),
  .lsu_sbdpc_err_g(lsu_sbdpc_err_g),
  .lsu_sbdpu_err_g(lsu_sbdpu_err_g),
  .lsu_sbapp_err_g(lsu_sbapp_err_g),
  .lsu_sbdiou_err_g(lsu_sbdiou_err_g),
  .lsu_stberr_tid_g(lsu_stberr_tid_g[2:0]),
  .lsu_stberr_index_g(lsu_stberr_index_g[2:0]),
  .lsu_stberr_priv_g(lsu_stberr_priv_g[1:0]),
  .lsu_stb_flush_g(lsu_stb_flush_g),
  .lsu_dttp_err_b(lsu_dttp_err_b),
  .lsu_dtdp_err_b(lsu_dtdp_err_b),
  .lsu_dtmh_err_b(lsu_dtmh_err_b),
  .lsu_perfmon_trap_b(lsu_perfmon_trap_b),
  .lsu_perfmon_trap_g(lsu_perfmon_trap_g),
  .lsu_ext_interrupt(lsu_ext_interrupt),
  .lsu_ext_int_type(lsu_ext_int_type[1:0]),
  .lsu_ext_int_vec(lsu_ext_int_vec[5:0]),
  .lsu_ext_int_tid(lsu_ext_int_tid[2:0]),
  .lsu_asi_error_inject(lsu_asi_error_inject[31:0]),
  .fgu_pdist_beat2_fx1(fgu_pdist_beat2_fx1),
  .fgu_predict_fx2(fgu_predict_fx2),
  .fgu_ecc_addr_fx2(fgu_ecc_addr_fx2[5:0]),
  .fgu_ecc_check_fx2(fgu_ecc_check_fx2[13:0]),
  .fgu_fpx_ieee_trap_fw(fgu_fpx_ieee_trap_fw),
  .fgu_fpd_ieee_trap_fw(fgu_fpd_ieee_trap_fw),
  .fgu_fpx_unfin_fw(fgu_fpx_unfin_fw),
  .fgu_fpx_trap_tid_fw(fgu_fpx_trap_tid_fw[2:0]),
  .fgu_fpd_unfin_fw(fgu_fpd_unfin_fw),
  .fgu_fpd_idiv0_trap_fw(fgu_fpd_idiv0_trap_fw),
  .fgu_fpd_trap_tid_fw(fgu_fpd_trap_tid_fw[2:0]),
  .mmu_hw_tw_enable(mmu_hw_tw_enable[7:0]),
  .mmu_write_itlb(mmu_write_itlb[7:0]),
  .mmu_reload_done(mmu_reload_done[7:0]),
  .mmu_i_unauth_access(mmu_i_unauth_access[7:0]),
  .mmu_i_tsb_miss(mmu_i_tsb_miss[7:0]),
  .mmu_d_tsb_miss(mmu_d_tsb_miss[7:0]),
  .mmu_i_tte_outofrange(mmu_i_tte_outofrange[7:0]),
  .mmu_d_tte_outofrange(mmu_d_tte_outofrange[7:0]),
  .mmu_itte_tag_data(mmu_itte_tag_data[47:0]),
  .mmu_asi_data(mmu_asi_data[64:0]),
  .mmu_asi_read(mmu_asi_read),
  .mmu_dae_req(mmu_dae_req),
  .mmu_dae_tid(mmu_dae_tid[2:0]),
  .mmu_asi_cecc(mmu_asi_cecc),
  .mmu_asi_uecc(mmu_asi_uecc),
  .mmu_asi_tid(mmu_asi_tid[2:0]),
  .mmu_asi_index(mmu_asi_index[10:0]),
  .mmu_asi_mra_not_sca(mmu_asi_mra_not_sca),
  .mmu_i_l2cerr(mmu_i_l2cerr[7:0]),
  .mmu_d_l2cerr(mmu_d_l2cerr[7:0]),
  .mmu_i_eccerr(mmu_i_eccerr[7:0]),
  .mmu_d_eccerr(mmu_d_eccerr[7:0]),
  .mmu_thr0_err_type(mmu_thr0_err_type[2:0]),
  .mmu_thr1_err_type(mmu_thr1_err_type[2:0]),
  .mmu_thr2_err_type(mmu_thr2_err_type[2:0]),
  .mmu_thr3_err_type(mmu_thr3_err_type[2:0]),
  .mmu_thr4_err_type(mmu_thr4_err_type[2:0]),
  .mmu_thr5_err_type(mmu_thr5_err_type[2:0]),
  .mmu_thr6_err_type(mmu_thr6_err_type[2:0]),
  .mmu_thr7_err_type(mmu_thr7_err_type[2:0]),
  .mmu_thr0_err_index(mmu_thr0_err_index[2:0]),
  .mmu_thr1_err_index(mmu_thr1_err_index[2:0]),
  .mmu_thr2_err_index(mmu_thr2_err_index[2:0]),
  .mmu_thr3_err_index(mmu_thr3_err_index[2:0]),
  .mmu_thr4_err_index(mmu_thr4_err_index[2:0]),
  .mmu_thr5_err_index(mmu_thr5_err_index[2:0]),
  .mmu_thr6_err_index(mmu_thr6_err_index[2:0]),
  .mmu_thr7_err_index(mmu_thr7_err_index[2:0]),
  .spu_tlu_cwq_busy(spu_tlu_cwq_busy),
  .spu_tlu_mamu_err_req(spu_tlu_mamu_err_req[10:0]),
  .spu_tlu_ma_int_req(spu_tlu_ma_int_req[4:0]),
  .spu_tlu_cwq_int_req(spu_tlu_cwq_int_req[3:0]),
  .spu_tlu_l2_error(spu_tlu_l2_error[5:0]),
  .pmu_tlu_trap_m(pmu_tlu_trap_m[7:0]),
  .pmu_tlu_debug_event(pmu_tlu_debug_event[7:0]),
  .tlu_core_running_status(tlu_core_running_status[7:0]),
  .tlu_ss_complete(tlu_ss_complete),
  .tlu_hardstop_request(tlu_hardstop_request),
  .tlu_softstop_request(tlu_softstop_request),
  .tlu_trigger_pulse(tlu_trigger_pulse),
  .tlu_dbg_instr_cmt_grp0(tlu_dbg_instr_cmt_grp0[1:0]),
  .tlu_dbg_instr_cmt_grp1(tlu_dbg_instr_cmt_grp1[1:0]),
  .tlu_flush_ifu(tlu_flush_ifu[7:0]),
  .tlu_window_block(tlu_window_block[1:0]),
  .tlu_retry_state(tlu_retry_state[7:0]),
  .tlu_halted(tlu_halted[7:0]),
  .tlu_pc_0_d(tlu_pc_0_d[47:2]),
  .tlu_pc_1_d(tlu_pc_1_d[47:2]),
  .tlu_flush_exu_b(tlu_flush_exu_b[1:0]),
  .tlu_ccr_0(tlu_ccr_0[7:0]),
  .tlu_ccr_1(tlu_ccr_1[7:0]),
  .tlu_cwp_0(tlu_cwp_0[2:0]),
  .tlu_cwp_1(tlu_cwp_1[2:0]),
  .tlu_ccr_cwp_0_valid(tlu_ccr_cwp_0_valid),
  .tlu_ccr_cwp_1_valid(tlu_ccr_cwp_1_valid),
  .tlu_ccr_cwp_0_tid(tlu_ccr_cwp_0_tid[1:0]),
  .tlu_ccr_cwp_1_tid(tlu_ccr_cwp_1_tid[1:0]),
  .tlu_gl0(tlu_gl0[1:0]),
  .tlu_gl1(tlu_gl1[1:0]),
  .tlu_gl2(tlu_gl2[1:0]),
  .tlu_gl3(tlu_gl3[1:0]),
  .tlu_gl4(tlu_gl4[1:0]),
  .tlu_gl5(tlu_gl5[1:0]),
  .tlu_gl6(tlu_gl6[1:0]),
  .tlu_gl7(tlu_gl7[1:0]),
  .tlu_itlb_bypass_e(tlu_itlb_bypass_e[1:0]),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .tlu_flush_fgu_b(tlu_flush_fgu_b),
  .tlu_trap_pc_0(tlu_trap_pc_0[47:0]),
  .tlu_trap_pc_0_valid(tlu_trap_pc_0_valid),
  .tlu_trap_0_tid(tlu_trap_0_tid[1:0]),
  .tlu_trap_pc_1(tlu_trap_pc_1[47:0]),
  .tlu_trap_pc_1_valid(tlu_trap_pc_1_valid),
  .tlu_trap_1_tid(tlu_trap_1_tid[1:0]),
  .tlu_retry(tlu_retry[1:0]),
  .tlu_ifu_invalidate(tlu_ifu_invalidate[1:0]),
  .tlu_itlb_reload(tlu_itlb_reload[1:0]),
  .tlu_itlb_bypass(tlu_itlb_bypass[7:0]),
  .tlu_release_tte(tlu_release_tte[7:0]),
  .tlu_rngf_cdbus(tlu_rngf_cdbus[64:0]),
  .tlu_rngf_cdbus_error(tlu_rngf_cdbus_error),
  .tlu_asi_0(tlu_asi_0[7:0]),
  .tlu_asi_1(tlu_asi_1[7:0]),
  .tlu_asi_0_valid(tlu_asi_0_valid),
  .tlu_asi_1_valid(tlu_asi_1_valid),
  .tlu_asi_0_tid(tlu_asi_0_tid[1:0]),
  .tlu_asi_1_tid(tlu_asi_1_tid[1:0]),
  .tlu_tl_gt_0(tlu_tl_gt_0[7:0]),
  .tlu_lsu_clear_ctl_reg_(tlu_lsu_clear_ctl_reg_[7:0]),
  .tlu_load_i_tag_access_p(tlu_load_i_tag_access_p[7:0]),
  .tlu_load_i_tag_access_n(tlu_load_i_tag_access_n[7:0]),
  .tlu_load_d_tag_access(tlu_load_d_tag_access[7:0]),
  .tlu_load_d_tag_access_r(tlu_load_d_tag_access_r[7:0]),
  .tlu_npc_w(tlu_npc_w[47:2]),
  .tlu_pc_0_w(tlu_pc_0_w[47:13]),
  .tlu_pc_1_w(tlu_pc_1_w[47:13]),
  .tlu_iht_request(tlu_iht_request[7:0]),
  .tlu_dht_request(tlu_dht_request[7:0]),
  .tlu_mmu_tl_gt_0(tlu_mmu_tl_gt_0[7:0]),
  .tlu_flush_pmu_b(tlu_flush_pmu_b[1:0]),
  .tlu_flush_pmu_w(tlu_flush_pmu_w[1:0]),
  .tlu_pmu_trap_taken(tlu_pmu_trap_taken[7:0]),
  .tlu_pmu_trap_mask_e(tlu_pmu_trap_mask_e[1:0]),
  .tlu_lsu_hpstate_hpriv(tlu_lsu_hpstate_hpriv[7:0]),
  .tlu_lsu_pstate_priv(tlu_lsu_pstate_priv[7:0]),
  .tlu_ifu_hpstate_hpriv(tlu_ifu_hpstate_hpriv[7:0]),
  .tlu_ifu_pstate_priv(tlu_ifu_pstate_priv[7:0]),
  .tlu_pmu_hpstate_hpriv(tlu_pmu_hpstate_hpriv[7:0]),
  .tlu_pmu_pstate_priv(tlu_pmu_pstate_priv[7:0]),
  .tlu_dec_hpstate_hpriv(tlu_dec_hpstate_hpriv[7:0]),
  .tlu_dec_pstate_priv(tlu_dec_pstate_priv[7:0]),
  .tlu_dec_pstate_pef(tlu_dec_pstate_pef[7:0]),
  .tlu_pstate_cle(tlu_pstate_cle[7:0]),
  .tlu_pstate_am(tlu_pstate_am[7:0]),
  .tlu_cerer_ittp(tlu_cerer_ittp),
  .tlu_cerer_itdp(tlu_cerer_itdp),
  .tlu_cerer_ittm(tlu_cerer_ittm),
  .tlu_cerer_hwtwmu(tlu_cerer_hwtwmu),
  .tlu_cerer_hwtwl2(tlu_cerer_hwtwl2),
  .tlu_cerer_icl2c(tlu_cerer_icl2c),
  .tlu_cerer_icl2u(tlu_cerer_icl2u),
  .tlu_cerer_icl2nd(tlu_cerer_icl2nd),
  .tlu_cerer_irf(tlu_cerer_irf),
  .tlu_cerer_frf(tlu_cerer_frf),
  .tlu_cerer_dttp(tlu_cerer_dttp),
  .tlu_cerer_dttm(tlu_cerer_dttm),
  .tlu_cerer_dtdp(tlu_cerer_dtdp),
  .tlu_cerer_dcl2c(tlu_cerer_dcl2c),
  .tlu_cerer_dcl2u(tlu_cerer_dcl2u),
  .tlu_cerer_dcl2nd(tlu_cerer_dcl2nd),
  .tlu_cerer_sbdlc(tlu_cerer_sbdlc),
  .tlu_cerer_sbdlu(tlu_cerer_sbdlu),
  .tlu_cerer_mrau(tlu_cerer_mrau),
  .tlu_cerer_scac(tlu_cerer_scac),
  .tlu_cerer_scau(tlu_cerer_scau),
  .tlu_cerer_sbapp(tlu_cerer_sbapp),
  .tlu_cerer_l2c_socc(tlu_cerer_l2c_socc),
  .tlu_cerer_l2u_socu(tlu_cerer_l2u_socu),
  .tlu_cerer_icvp(tlu_cerer_icvp),
  .tlu_cerer_ictp(tlu_cerer_ictp),
  .tlu_cerer_ictm(tlu_cerer_ictm),
  .tlu_cerer_icdp(tlu_cerer_icdp),
  .tlu_cerer_dcvp(tlu_cerer_dcvp),
  .tlu_cerer_dctp(tlu_cerer_dctp),
  .tlu_cerer_dctm(tlu_cerer_dctm),
  .tlu_cerer_dcdp(tlu_cerer_dcdp),
  .tlu_cerer_sbdpc(tlu_cerer_sbdpc),
  .tlu_cerer_sbdpu(tlu_cerer_sbdpu),
  .tlu_cerer_mamu(tlu_cerer_mamu),
  .tlu_cerer_mal2c(tlu_cerer_mal2c),
  .tlu_cerer_mal2u(tlu_cerer_mal2u),
  .tlu_cerer_mal2nd(tlu_cerer_mal2nd),
  .tlu_cerer_cwql2c(tlu_cerer_cwql2c),
  .tlu_cerer_cwql2u(tlu_cerer_cwql2u),
  .tlu_cerer_cwql2nd(tlu_cerer_cwql2nd),
  .tlu_cerer_sbdiou(tlu_cerer_sbdiou),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .tlu_tag_access_tid_0_b(tlu_tag_access_tid_0_b[1:0]),
  .tlu_i_tag_access_0_b(tlu_i_tag_access_0_b),
  .tlu_d_tag_access_0_b(tlu_d_tag_access_0_b),
  .tlu_tag_access_tid_1_b(tlu_tag_access_tid_1_b[1:0]),
  .tlu_i_tag_access_1_b(tlu_i_tag_access_1_b),
  .tlu_d_tag_access_1_b(tlu_d_tag_access_1_b),
  .tlu_mbi_tsa0_fail(tlu_mbi_tsa0_fail),
  .tlu_mbi_tsa1_fail(tlu_mbi_tsa1_fail),
  .tlu_mbi_tca_fail(tlu_mbi_tca_fail),
  .tlu_spec_enable(tlu_spec_enable[7:0])
);


lsu lsu (
	// I/O flops tacked onto front of LSU chain
	.scan_in(msf0_scanout),
	.scan_out(lsu_scanout),
	.wmr_scan_in(fgu_wmr_scanout),
	.wmr_scan_out(lsu_wmr_scanout),
        .dmo_coresel(dmo_coresel_buff),
	.vnw_ary(vnw_ary1),
	.l2clk(l2clk),
        .tcu_array_wr_inhibit   (clk_array_wr_inhibit),
        .dmo_dcmuxctl		(dmo_dcmuxctl_buf	),
        .tcu_pce_ov		(pce_ov_br		),
        .tcu_scan_en		(lb_scan_en_br		),
	.spc_aclk               (spc_aclk_br            ),
	.spc_aclk_wmr           (spc_aclk_wmr_br        ),
	.spc_bclk               (spc_bclk_br            ),
        .tcu_se_scancollar_in  	(lb_se_sc_in		),
        .tcu_se_scancollar_out	(lb_se_sc_out		),
	.fgu_lsu_fst_data_fx1	(fgu_lsu_fst_data_fx1[63:0]),
	.cpx_spc_data_cx	(cpx_spc_data_cx_rep0[145:0]	),
	.rngl_lsu_cdbus		(exu1_rngl_cdbus[64:0]	),
	.tlu_rngf_cdbus		(tlu_rngf_cdbus[64:0]	),
	.tlu_tte		(tlu_rngf_cdbus[54:0]	),
        .lbist_run		(lb_lbist_running	),
	.mbi_addr		(mb0_addr[8:0]		),
	.mbi_run		(mb0_run		),
	.mbi_wdata		(mb0_write_data[7:0]	),
	.mbi_cmpsel		(mb0_cmpsel[1:0]        ),
	.mbi_dca_read_en	(mb0_dca_read_en        ),
	.mbi_dca_write_en	(mb0_dca_write_en       ),
	.mbi_dta_read_en	(mb0_dta_read_en        ),
	.mbi_dta_write_en	(mb0_dta_write_en       ),
	.mbi_dva_read_en	(mb0_dva_read_en        ),
	.mbi_dva_write_en	(mb0_dva_write_en       ),
	.mbi_lru_read_en	(mb0_lru_read_en        ),
	.mbi_lru_write_en	(mb0_lru_write_en       ),
	.mbi_dtb_read_en	(mb0_dtb_read_en        ),
	.mbi_dtb_write_en	(mb0_dtb_write_en       ),
	.mbi_stb_cam_read_en	(mb0_stb_cam_read_en    ),
	.mbi_stb_cam_write_en	(mb0_stb_cam_write_en   ),
	.mbi_stb_ram_read_en	(mb0_stb_ram_read_en    ),
	.mbi_stb_ram_write_en	(mb0_stb_ram_write_en   ),
	.mbi_cpq_read_en	(mb0_cpq_read_en        ),
	.mbi_cpq_write_en	(mb0_cpq_write_en       ),
        .efu_spc_fuse_data	(efu_spc_fuse_data_buf  ),
        .efu_spc_fuse_dxfer_en	(efu_spc_fuse_dxfer_en_buf),
        .efu_spc_fuse_dclr	(efu_spc_fuse_dclr_buf	),
        .spc_efu_fuse_ddata	(spc_efu_fuse_ddata_buf	),
        .spc_efu_fuse_dxfer_en	(spc_efu_fuse_dxfer_en_buf),
  .lb_scan_en_wmr(lb_scan_en_wmr),
  .const_cpuid(const_cpuid[2:0]),
  .ifu_lsu_if_vld(ifu_lsu_if_vld),
  .ifu_lsu_if_tid(ifu_lsu_if_tid[2:0]),
  .ifu_lsu_if_addr(ifu_lsu_if_addr[10:5]),
  .lsu_ifu_ctxt_data(lsu_ifu_ctxt_data[12:0]),
  .lsu_ifu_tid_w(lsu_ifu_tid_w[2:0]),
  .lsu_ifu_wr_p0ctxt(lsu_ifu_wr_p0ctxt),
  .lsu_ifu_wr_p1ctxt(lsu_ifu_wr_p1ctxt),
  .lsu_ifu_wr_pid(lsu_ifu_wr_pid),
  .lsu_immu_enable(lsu_immu_enable[7:0]),
  .lsu_ic_enable(lsu_ic_enable[7:0]),
  .lsu_ifu_ld_index(lsu_ifu_ld_index[10:5]),
  .lsu_ifu_direct_map(lsu_ifu_direct_map),
  .lsu_ifu_no_miss(lsu_ifu_no_miss[7:0]),
  .lsu_cpx_data(lsu_cpx_data[127:0]),
  .lsu_cpx_cpkt(lsu_cpx_cpkt[17:0]),
  .lsu_cpx_valid(lsu_cpx_valid),
  .dec_lsu_tg_d(dec_lsu_tg_d),
  .dec_ld_inst_d(dec_ld_inst_d),
  .dec_ld_inst_e(dec_ld_inst_e),
  .dec_st_inst_e(dec_st_inst_e),
  .dec_fpldst_inst_e(dec_fpldst_inst_e),
  .dec_fsr_ldst_e(dec_fsr_ldst_e),
  .dec_ldst_dbl_e(dec_ldst_dbl_e),
  .dec_pref_inst_e(dec_pref_inst_e),
  .dec_flush_inst_e(dec_flush_inst_e),
  .dec_memstbar_inst_e(dec_memstbar_inst_e),
  .dec_sr_inst_e(dec_sr_inst_e),
  .dec_pr_inst_e(dec_pr_inst_e),
  .dec_hpr_inst_e(dec_hpr_inst_e),
  .dec_casa_inst_e(dec_casa_inst_e),
  .dec_ldstub_inst_e(dec_ldstub_inst_e),
  .dec_swap_inst_e(dec_swap_inst_e),
  .dec_altspace_d(dec_altspace_d),
  .dec_sign_ext_e(dec_sign_ext_e),
  .dec_ldst_sz_e(dec_ldst_sz_e[1:0]),
  .dec_lsu_rd_e(dec_lsu_rd_e[4:0]),
  .dec_sraddr_e(dec_sraddr_e[4:0]),
  .dec_imm_asi_vld_d(dec_imm_asi_vld_d),
  .dec_imm_asi_d(dec_imm_asi_d[7:0]),
  .dec_frf_r2_addr_e(dec_frf_r2_addr_e[4:3]),
  .dec_flush_lm(dec_flush_lm),
  .dec_flush_lb(dec_flush_lb),
  .dec_lsu_tid0_d(dec_lsu_tid0_d[1:0]),
  .dec_lsu_tid1_d(dec_lsu_tid1_d[1:0]),
  .lsu_block_store_stall(lsu_block_store_stall),
  .lsu_block_store_rd(lsu_block_store_rd[4:3]),
  .lsu_block_store_tid(lsu_block_store_tid[2:0]),
  .lsu_cpq_stall(lsu_cpq_stall),
  .lsu_sync(lsu_sync[7:0]),
  .lsu_complete(lsu_complete[7:0]),
  .lsu_stb_alloc(lsu_stb_alloc[7:0]),
  .lsu_stb_dealloc(lsu_stb_dealloc[7:0]),
  .lsu_block_store_kill(lsu_block_store_kill[7:0]),
  .tlu_flush_lsu_b(tlu_flush_lsu_b),
  .tlu_pstate_cle(tlu_pstate_cle[7:0]),
  .tlu_asi_0(tlu_asi_0[7:0]),
  .tlu_asi_1(tlu_asi_1[7:0]),
  .tlu_asi_0_tid(tlu_asi_0_tid[1:0]),
  .tlu_asi_1_tid(tlu_asi_1_tid[1:0]),
  .tlu_asi_0_valid(tlu_asi_0_valid),
  .tlu_asi_1_valid(tlu_asi_1_valid),
  .tlu_lsu_hpstate_hpriv(tlu_lsu_hpstate_hpriv[7:0]),
  .tlu_lsu_pstate_priv(tlu_lsu_pstate_priv[7:0]),
  .tlu_tl_gt_0(tlu_tl_gt_0[7:0]),
  .tlu_lsu_clear_ctl_reg_(tlu_lsu_clear_ctl_reg_[7:0]),
  .tlu_cerer_dttp(tlu_cerer_dttp),
  .tlu_cerer_dttm(tlu_cerer_dttm),
  .tlu_cerer_dtdp(tlu_cerer_dtdp),
  .tlu_cerer_dcvp(tlu_cerer_dcvp),
  .tlu_cerer_dctp(tlu_cerer_dctp),
  .tlu_cerer_dctm(tlu_cerer_dctm),
  .tlu_cerer_dcdp(tlu_cerer_dcdp),
  .tlu_cerer_dcl2c(tlu_cerer_dcl2c),
  .tlu_cerer_dcl2u(tlu_cerer_dcl2u),
  .tlu_cerer_dcl2nd(tlu_cerer_dcl2nd),
  .tlu_cerer_sbdlc(tlu_cerer_sbdlc),
  .tlu_cerer_sbdlu(tlu_cerer_sbdlu),
  .tlu_cerer_sbapp(tlu_cerer_sbapp),
  .tlu_cerer_sbdiou(tlu_cerer_sbdiou),
  .tlu_cerer_sbdpc(tlu_cerer_sbdpc),
  .tlu_cerer_sbdpu(tlu_cerer_sbdpu),
  .tlu_cerer_l2c_socc(tlu_cerer_l2c_socc),
  .tlu_cerer_l2u_socu(tlu_cerer_l2u_socu),
  .lsu_stb_empty(lsu_stb_empty[7:0]),
  .lsu_trap_flush(lsu_trap_flush[7:0]),
  .lsu_tlb_bypass_b(lsu_tlb_bypass_b),
  .lsu_tlb_real_b(lsu_tlb_real_b),
  .lsu_align_b(lsu_align_b),
  .lsu_lddf_align_b(lsu_lddf_align_b),
  .lsu_stdf_align_b(lsu_stdf_align_b),
  .lsu_dae_invalid_asi_b(lsu_dae_invalid_asi_b),
  .lsu_dae_nc_page_b(lsu_dae_nc_page_b),
  .lsu_dae_nfo_page_b(lsu_dae_nfo_page_b),
  .lsu_dae_priv_viol_b(lsu_dae_priv_viol_b),
  .lsu_dae_so_page(lsu_dae_so_page),
  .lsu_priv_action_b(lsu_priv_action_b),
  .lsu_va_watchpoint_b(lsu_va_watchpoint_b),
  .lsu_pa_watchpoint_b(lsu_pa_watchpoint_b),
  .lsu_tlb_miss_b_(lsu_tlb_miss_b_),
  .lsu_illegal_inst_b(lsu_illegal_inst_b),
  .lsu_daccess_prot_b(lsu_daccess_prot_b),
  .lsu_perfmon_trap_b(lsu_perfmon_trap_b),
  .lsu_perfmon_trap_g(lsu_perfmon_trap_g),
  .lsu_priv_action_g(lsu_priv_action_g),
  .lsu_tid_g(lsu_tid_g[2:0]),
  .lsu_tlu_dsfsr_ct_b(lsu_tlu_dsfsr_ct_b[1:0]),
  .lsu_sync_inst_b(lsu_sync_inst_b),
  .lsu_tlu_twocycle_m(lsu_tlu_twocycle_m),
  .lsu_asi_error_inject(lsu_asi_error_inject[31:0]),
  .lsu_dcmh_err_g(lsu_dcmh_err_g),
  .lsu_dcvp_err_g(lsu_dcvp_err_g),
  .lsu_dctp_err_g(lsu_dctp_err_g),
  .lsu_dcdp_err_g(lsu_dcdp_err_g),
  .lsu_dcl2c_err_g(lsu_dcl2c_err_g),
  .lsu_dcl2u_err_g(lsu_dcl2u_err_g),
  .lsu_dcl2nd_err_g(lsu_dcl2nd_err_g),
  .lsu_dcsoc_err_g(lsu_dcsoc_err_g),
  .lsu_dcerr_tid_g(lsu_dcerr_tid_g[2:0]),
  .lsu_dcerr_sfar_g(lsu_dcerr_sfar_g[8:0]),
  .lsu_sbdlc_err_g(lsu_sbdlc_err_g),
  .lsu_sbdlu_err_g(lsu_sbdlu_err_g),
  .lsu_sbdpc_err_g(lsu_sbdpc_err_g),
  .lsu_sbdpu_err_g(lsu_sbdpu_err_g),
  .lsu_sbapp_err_g(lsu_sbapp_err_g),
  .lsu_sbdiou_err_g(lsu_sbdiou_err_g),
  .lsu_stberr_tid_g(lsu_stberr_tid_g[2:0]),
  .lsu_stberr_index_g(lsu_stberr_index_g[2:0]),
  .lsu_stberr_priv_g(lsu_stberr_priv_g[1:0]),
  .lsu_stb_flush_g(lsu_stb_flush_g),
  .lsu_dttp_err_b(lsu_dttp_err_b),
  .lsu_dtdp_err_b(lsu_dtdp_err_b),
  .lsu_dtmh_err_b(lsu_dtmh_err_b),
  .lsu_ext_interrupt(lsu_ext_interrupt),
  .lsu_ext_int_type(lsu_ext_int_type[1:0]),
  .lsu_ext_int_vec(lsu_ext_int_vec[5:0]),
  .lsu_ext_int_tid(lsu_ext_int_tid[2:0]),
  .mmu_dtlb_reload(mmu_dtlb_reload),
  .lsu_mmu_va_b(lsu_mmu_va_b[47:0]),
  .lsu_context_b(lsu_context_b[12:0]),
  .exu_lsu_rs2_e(exu_lsu_rs2_e[7:0]),
  .exu_lsu_address_e(exu_lsu_address_e[47:0]),
  .exu_lsu_store_data_e(exu_lsu_store_data_e[63:0]),
  .exu_lsu_va_error_m(exu_lsu_va_error_m[1:0]),
  .exu_ecc_m(exu_ecc_m[1:0]),
  .lsu_exu_ld_data_b(lsu_exu_ld_data_b[63:0]),
  .lsu_exu_ld_vld_w(lsu_exu_ld_vld_w),
  .lsu_exu_ld_b(lsu_exu_ld_b),
  .lsu_exu_rd_m(lsu_exu_rd_m[4:0]),
  .lsu_exu_tid_m(lsu_exu_tid_m[2:0]),
  .lsu_exu_address_e(lsu_exu_address_e[47:13]),
  .lsu_sel_lsu_addr_e(lsu_sel_lsu_addr_e),
  .fgu_fst_ecc_error_fx2(fgu_fst_ecc_error_fx2),
  .fgu_fdiv_stall(fgu_fdiv_stall),
  .lsu_fgu_fld_data_b(lsu_fgu_fld_data_b[63:0]),
  .lsu_fgu_fld_vld_w(lsu_fgu_fld_vld_w),
  .lsu_fgu_fld_b(lsu_fgu_fld_b),
  .lsu_fgu_fld_addr_b(lsu_fgu_fld_addr_b[4:0]),
  .lsu_fgu_fld_tid_b(lsu_fgu_fld_tid_b[2:0]),
  .lsu_fgu_fld_32b_b(lsu_fgu_fld_32b_b),
  .lsu_fgu_fld_odd32b_b(lsu_fgu_fld_odd32b_b),
  .lsu_fgu_fsr_load_b(lsu_fgu_fsr_load_b),
  .lsu_fgu_exception_w(lsu_fgu_exception_w),
  .lsu_block_store_m(lsu_block_store_m),
  .lsu_frf_read_pending(lsu_frf_read_pending),
  .pmu_lsu_dcmiss_trap_m(pmu_lsu_dcmiss_trap_m),
  .pmu_lsu_dtmiss_trap_m(pmu_lsu_dtmiss_trap_m),
  .pmu_lsu_l2dmiss_trap_m(pmu_lsu_l2dmiss_trap_m[7:0]),
  .lsu_pmu_mem_type_b(lsu_pmu_mem_type_b[2:0]),
  .l15_lsu_grant(l15_lsu_grant),
  .lsu_l15_lock(lsu_l15_lock),
  .lsu_l15_valid(lsu_l15_valid),
  .lsu_l15_addr(lsu_l15_addr[39:0]),
  .lsu_l15_cpkt(lsu_l15_cpkt[25:0]),
  .lsu_l15_data(lsu_l15_data[63:0]),
  .tlu_rngf_cdbus_error(tlu_rngf_cdbus_error),
  .lsu_rngf_cdbus(lsu_rngf_cdbus[64:0]),
  .lsu_rngl_cdbus(lsu_rngl_cdbus[64:0]),
  .mbi_ptag_data(mbi_ptag_data),
  .lsu_mbi_dca_fail(lsu_mbi_dca_fail),
  .lsu_mbi_dta_fail(lsu_mbi_dta_fail),
  .lsu_mbi_dva_fail(lsu_mbi_dva_fail),
  .lsu_mbi_lru_fail(lsu_mbi_lru_fail),
  .lsu_mbi_dtb_fail(lsu_mbi_dtb_fail),
  .lsu_mbi_stb_cam_fail(lsu_mbi_stb_cam_fail),
  .lsu_mbi_stb_ram_fail(lsu_mbi_stb_ram_fail),
  .lsu_mbi_cpq_fail(lsu_mbi_cpq_fail),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_cambist_shift(mbi_cambist_shift),
  .mbi_dis_clr_ubit(mbi_dis_clr_ubit),
  .mbi_init_to_zero(mbi_init_to_zero),
  .mbi_dtb_cam_en_pre(mbi_dtb_cam_en_pre),
  .mbi_repl_write(mbi_repl_write),
  .mbi_dtb_demap_en(mbi_dtb_demap_en),
  .mbi_demap_type(mbi_demap_type[1:0]),
  .lsu_mbi_tlb_data_cmp(lsu_mbi_tlb_data_cmp),
  .lsu_mbi_tlb_cam_hit(lsu_mbi_tlb_cam_hit),
  .lsu_mbi_tlb_cam_mhit(lsu_mbi_tlb_cam_mhit),
  .lsu_mbi_tlb_ctxt0_hit(lsu_mbi_tlb_ctxt0_hit),
  .lsu_mbi_tlb_valid(lsu_mbi_tlb_valid),
  .lsu_mbi_tlb_used(lsu_mbi_tlb_used),
  .mbi_scm_cam_en_pre(mbi_scm_cam_en_pre),
  .lsu_mbi_scm_hit(lsu_mbi_scm_hit),
  .lsu_mbi_scm_mhit(lsu_mbi_scm_mhit),
  .lsu_mbi_scm_hit_ptr(lsu_mbi_scm_hit_ptr[2:0]),
  .lsu_mbi_scm_praw(lsu_mbi_scm_praw),
  .dcc_dmo_parity(dcc_dmo_parity[3:0]),
  .lsu_ic_pmen(lsu_ic_pmen),
  .lsu_ifu_cmu_pmen(lsu_ifu_cmu_pmen),
  .lsu_ifu_ftu_pmen(lsu_ifu_ftu_pmen),
  .lsu_ifu_ibu_pmen(lsu_ifu_ibu_pmen),
  .lsu_dec_pmen(lsu_dec_pmen),
  .lsu_pku_pmen(lsu_pku_pmen),
  .lsu_exu_pmen(lsu_exu_pmen),
  .lsu_fgu_pmen(lsu_fgu_pmen),
  .lsu_tlu_pmen(lsu_tlu_pmen),
  .lsu_gkt_pmen(lsu_gkt_pmen),
  .lsu_spu_pmen(lsu_spu_pmen),
  .lsu_mmu_pmen(lsu_mmu_pmen),
  .lsu_pmu_pmen(lsu_pmu_pmen),
  .lsu_misc_pmen(lsu_misc_pmen),
  .lsu_asi_clken(lsu_asi_clken),
  .slow_cmp_sync_en(slow_cmp_sync_en),
  .cmp_slow_sync_en(cmp_slow_sync_en)
);

//assign lsu_rngf_cdbus[64:0] = {lsu_ring_ctl,lsu_rngf_cdbus_b63,lsu_ring_cdbus[62:0]};
//assign lsu_rngl_cdbus[64:0] = {lsu_ring_ctl,lsu_rngl_cdbus_b63,lsu_ring_cdbus[62:0]};


spu spu (
	.scan_in(spu_scanin),
	.scan_out(spu_scanout),
	.l2clk(l2clk),
	.in_rngl_cdbus	( exu0_rngl_cdbus[64:0] ),

  .spu_mbi_mam_fail_(spu_mbi_mam_fail_),
  .spu_mbi_mam_fail2_(spu_mbi_mam_fail2_),
  .spu_mbi_arf_fail_(spu_mbi_arf_fail_),
  .spu_mbi_rrf_fail_(spu_mbi_rrf_fail_),
  .spu_rngl_cdbus	( spu_rngl_cdbus[64:0]		),
  .spu_l15_valid(spu_l15_valid),
  .spu_l15_addr(spu_l15_addr[38:3]),
  .spu_l15_cpkt(spu_l15_cpkt[12:0]),
  .spu_l15_data(spu_l15_data[63:0]),
  .spu_mult_request(spu_mult_request),
  .spu_fgu_rs1_e(spu_fgu_rs1_e[63:0]),
  .spu_fgu_rs2_e(spu_fgu_rs2_e[63:0]),
  .spu_fgu_fpy_ctl_d(spu_fgu_fpy_ctl_d[6:0]),
  .spu_pmu_cwq_busy(spu_pmu_cwq_busy[4:0]),
  .spu_pmu_cwq_tid(spu_pmu_cwq_tid[2:0]),
  .spu_pmu_ma_busy(spu_pmu_ma_busy[3:0]),
  .spu_tlu_cwq_busy(spu_tlu_cwq_busy),
  .spu_tlu_cwq_int_req(spu_tlu_cwq_int_req[3:0]),
  .spu_tlu_ma_int_req(spu_tlu_ma_int_req[4:0]),
  .spu_tlu_mamu_err_req(spu_tlu_mamu_err_req[10:0]),
  .spu_tlu_l2_error(spu_tlu_l2_error[5:0])

);


mmu mmu (
	.scan_in(mmu_scanin),
	.scan_out(mmu_scanout),
	.wmr_scan_in(tlu_wmr_scanout),
	.wmr_scan_out(mmu_wmr_scanout),
	.l2clk			(l2clk				),
        .tcu_dectest		(tcu_dectest_buf		),
        .tcu_muxtest		(tcu_muxtest_buf		),
        .tcu_array_wr_inhibit	(clk_array_wr_inhibit	),
        .tcu_pce_ov		(pce_ov_tl		),
        .tcu_scan_en		(lb_scan_en_tl		),
	.spc_aclk               (spc_aclk_tl            ),
	.spc_aclk_wmr           (spc_aclk_wmr_tl        ),
	.spc_bclk               (spc_bclk_tl            ),
        .tcu_se_scancollar_in	(lb_se_sc_in			),
	.l15_mmu_cpkt		(l15_spc_cpkt[17:0]	),
	.l15_spc_data1		(l15_spc_data1[127:0]	),
	.mbi_mra0_write_en	(mb1_mra0_write_en		),
	.mbi_mra1_write_en	(mb1_mra1_write_en		),
	.mbi_scp0_write_en	(mb1_scp0_write_en		),
	.mbi_scp1_write_en	(mb1_scp1_write_en		),
	.mbi_addr		(mb1_addr[4:0]			),
	.mbi_run		(mb1_run			),
	.mbi_wdata		(mb1_write_data[7:0]		),
	.mbi_mra0_read_en	(mb1_mra0_read_en		),
	.mbi_mra1_read_en	(mb1_mra1_read_en		),
	.mbi_scp0_read_en	(mb1_scp0_read_en		),
	.mbi_scp1_read_en	(mb1_scp1_read_en		),
	.mbi_mmu_cmpsel		(mb1_cmpsel[1:0]		),
	.lsu_va_b		(lsu_mmu_va_b[47:0]	),
	.lsu_rngf_cdbus		(lsu_rngf_cdbus[64:0]	),
	.spc_core_running_status(tlu_core_running_status[7:0]),
  .lb_scan_en_wmr(lb_scan_en_wmr),
  .lsu_mmu_pmen(lsu_mmu_pmen),
  .lsu_asi_clken(lsu_asi_clken),
  .tlu_tag_access_tid_0_b(tlu_tag_access_tid_0_b[1:0]),
  .tlu_i_tag_access_0_b(tlu_i_tag_access_0_b),
  .tlu_d_tag_access_0_b(tlu_d_tag_access_0_b),
  .tlu_tag_access_tid_1_b(tlu_tag_access_tid_1_b[1:0]),
  .tlu_i_tag_access_1_b(tlu_i_tag_access_1_b),
  .tlu_d_tag_access_1_b(tlu_d_tag_access_1_b),
  .lsu_context_b(lsu_context_b[12:0]),
  .lsu_tlu_dsfsr_ct_b(lsu_tlu_dsfsr_ct_b[1:0]),
  .lsu_asi_error_inject(lsu_asi_error_inject[31:0]),
  .tlu_load_i_tag_access_p(tlu_load_i_tag_access_p[7:0]),
  .tlu_load_i_tag_access_n(tlu_load_i_tag_access_n[7:0]),
  .tlu_load_d_tag_access(tlu_load_d_tag_access[7:0]),
  .tlu_load_d_tag_access_r(tlu_load_d_tag_access_r[7:0]),
  .tlu_release_tte(tlu_release_tte[7:0]),
  .tlu_pc_0_w(tlu_pc_0_w[47:13]),
  .tlu_pc_1_w(tlu_pc_1_w[47:13]),
  .tlu_iht_request(tlu_iht_request[7:0]),
  .tlu_dht_request(tlu_dht_request[7:0]),
  .tlu_mmu_tl_gt_0(tlu_mmu_tl_gt_0[7:0]),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .tlu_cerer_mrau(tlu_cerer_mrau),
  .tlu_cerer_scac(tlu_cerer_scac),
  .tlu_cerer_scau(tlu_cerer_scau),
  .tlu_cerer_hwtwmu(tlu_cerer_hwtwmu),
  .tlu_cerer_hwtwl2(tlu_cerer_hwtwl2),
  .l15_mmu_grant(l15_mmu_grant),
  .l15_mmu_valid(l15_mmu_valid),
  .mmu_mbi_mra0_fail(mmu_mbi_mra0_fail),
  .mmu_mbi_mra1_fail(mmu_mbi_mra1_fail),
  .mmu_mbi_scp0_fail(mmu_mbi_scp0_fail),
  .mmu_mbi_scp1_fail(mmu_mbi_scp1_fail),
  .mmu_l15_cpkt(mmu_l15_cpkt[4:0]),
  .mmu_l15_addr(mmu_l15_addr[39:4]),
  .mmu_l15_valid(mmu_l15_valid),
  .mmu_write_itlb(mmu_write_itlb[7:0]),
  .mmu_itte_tag_data(mmu_itte_tag_data[47:0]),
  .mmu_asi_data(mmu_asi_data[64:0]),
  .mmu_asi_read(mmu_asi_read),
  .mmu_dae_req(mmu_dae_req),
  .mmu_dae_tid(mmu_dae_tid[2:0]),
  .mmu_dtlb_reload_stall(mmu_dtlb_reload_stall),
  .mmu_dtlb_reload(mmu_dtlb_reload),
  .mmu_hw_tw_enable(mmu_hw_tw_enable[7:0]),
  .mmu_reload_done(mmu_reload_done[7:0]),
  .mmu_i_unauth_access(mmu_i_unauth_access[7:0]),
  .mmu_i_tsb_miss(mmu_i_tsb_miss[7:0]),
  .mmu_d_tsb_miss(mmu_d_tsb_miss[7:0]),
  .mmu_i_tte_outofrange(mmu_i_tte_outofrange[7:0]),
  .mmu_d_tte_outofrange(mmu_d_tte_outofrange[7:0]),
  .mmu_index(mmu_index[6:0]),
  .mmu_asi_cecc(mmu_asi_cecc),
  .mmu_asi_uecc(mmu_asi_uecc),
  .mmu_asi_tid(mmu_asi_tid[2:0]),
  .mmu_asi_index(mmu_asi_index[10:0]),
  .mmu_asi_mra_not_sca(mmu_asi_mra_not_sca),
  .mmu_i_l2cerr(mmu_i_l2cerr[7:0]),
  .mmu_d_l2cerr(mmu_d_l2cerr[7:0]),
  .mmu_i_eccerr(mmu_i_eccerr[7:0]),
  .mmu_d_eccerr(mmu_d_eccerr[7:0]),
  .mmu_thr0_err_type(mmu_thr0_err_type[2:0]),
  .mmu_thr1_err_type(mmu_thr1_err_type[2:0]),
  .mmu_thr2_err_type(mmu_thr2_err_type[2:0]),
  .mmu_thr3_err_type(mmu_thr3_err_type[2:0]),
  .mmu_thr4_err_type(mmu_thr4_err_type[2:0]),
  .mmu_thr5_err_type(mmu_thr5_err_type[2:0]),
  .mmu_thr6_err_type(mmu_thr6_err_type[2:0]),
  .mmu_thr7_err_type(mmu_thr7_err_type[2:0]),
  .mmu_thr0_err_index(mmu_thr0_err_index[2:0]),
  .mmu_thr1_err_index(mmu_thr1_err_index[2:0]),
  .mmu_thr2_err_index(mmu_thr2_err_index[2:0]),
  .mmu_thr3_err_index(mmu_thr3_err_index[2:0]),
  .mmu_thr4_err_index(mmu_thr4_err_index[2:0]),
  .mmu_thr5_err_index(mmu_thr5_err_index[2:0]),
  .mmu_thr6_err_index(mmu_thr6_err_index[2:0]),
  .mmu_thr7_err_index(mmu_thr7_err_index[2:0]),
  .mmu_pmu_l2ret(mmu_pmu_l2ret),
  .mmu_pmu_l2miss(mmu_pmu_l2miss),
  .mmu_pmu_dtlb(mmu_pmu_dtlb),
  .mmu_pmu_tid(mmu_pmu_tid[2:0])
);


pmu pmu (
	.scan_in(mmu_scanout),
	.scan_out(pmu_scanout),
	.l2clk(l2clk),
        .tcu_pce_ov			(pce_ov_tl),
        .tcu_scan_en			(lb_scan_en_tl),
	.spc_aclk               	(spc_aclk_tl),
	.spc_bclk               	(spc_bclk_tl),
        .in_rngl_cdbus			(spu_rngl_cdbus[64:0]),
        .pmu_rngl_cdbus			(pmu_rngl_cdbus[64:0]),
	.dec_pmu_instr0_type_d		({dec_valid0_d,dec_tid0_d[1:0],dec_instr0_type_d[9:0]}),
	.dec_pmu_instr1_type_d		({dec_valid1_d,dec_tid1_d[1:0],dec_instr1_type_d[9:0]}),
	.dec_valid_e			(dec_pmu_valid_e[1:0]),
	.lsu_pmu_mem_type_b		({lsu_dcerr_tid_g[2:0],lsu_pmu_mem_type_b[2:0]}),
  .lsu_pmu_pmen(lsu_pmu_pmen),
  .lsu_asi_clken(lsu_asi_clken),
  .dec_br_taken_e(dec_br_taken_e[1:0]),
  .dec_lsu_sel0_d(dec_lsu_sel0_d),
  .mmu_pmu_l2ret(mmu_pmu_l2ret),
  .mmu_pmu_l2miss(mmu_pmu_l2miss),
  .mmu_pmu_dtlb(mmu_pmu_dtlb),
  .mmu_pmu_tid(mmu_pmu_tid[2:0]),
  .l15_pmu_xbar_optype(l15_pmu_xbar_optype[6:0]),
  .spu_pmu_cwq_busy(spu_pmu_cwq_busy[4:0]),
  .spu_pmu_cwq_tid(spu_pmu_cwq_tid[2:0]),
  .spu_pmu_ma_busy(spu_pmu_ma_busy[3:0]),
  .tlu_pmu_pstate_priv(tlu_pmu_pstate_priv[7:0]),
  .tlu_pmu_hpstate_hpriv(tlu_pmu_hpstate_hpriv[7:0]),
  .tlu_pmu_trap_taken(tlu_pmu_trap_taken[7:0]),
  .tlu_pmu_trap_mask_e(tlu_pmu_trap_mask_e[1:0]),
  .dec_flush_m(dec_flush_m[1:0]),
  .dec_flush_b(dec_flush_b[1:0]),
  .tlu_flush_pmu_b(tlu_flush_pmu_b[1:0]),
  .tlu_flush_pmu_w(tlu_flush_pmu_w[1:0]),
  .pmu_tlu_trap_m(pmu_tlu_trap_m[7:0]),
  .pmu_tlu_debug_event(pmu_tlu_debug_event[7:0]),
  .pmu_lsu_dcmiss_trap_m(pmu_lsu_dcmiss_trap_m),
  .pmu_lsu_dtmiss_trap_m(pmu_lsu_dtmiss_trap_m),
  .pmu_lsu_l2dmiss_trap_m(pmu_lsu_l2dmiss_trap_m[7:0])
);


////////////////////
// MBIST controllers

spc_mb0_ctl mb0 (
	.scan_in(mb0_scanin),
	.scan_out(mb0_scanout),
        .tcu_pce_ov			(pce_ov_br),
        .tcu_scan_en			(lb_scan_en_br),
	.tcu_aclk               	(spc_aclk_br),
	.tcu_bclk               	(spc_bclk_br),
        .tcu_clk_stop(1'b0),
	.l2clk				(l2clk),
	.mbist_start			(tcu_spc_mbist_start_buf0),
	.mbist_user_mode		(msf0_mbist_user_mode_ff),
	.mbist_bisi_mode		(msf0_mbist_bisi_en_ff),
    .mb2_mb0_fail   (mb2_mb0_fail),
    .mb1_mb0_fail   (mb1_mb0_fail),
    .mb2_mb0_done   (mb2_mb0_done),
    .mb1_mb0_done   (mb1_mb0_done),
        .mb0_cmpsel                     (mb0_cmpsel[2:0]),
        .mb0_mbist_fail			(spc_mbist_fail_buf),
        .mb0_done                       (spc_mbist_done_buf),
        .mb0_addr                       ({mb0_addr_unused[15:12],mb0_addr[11:0]}),
  .mb0_run(mb0_run),
  .mb0_ict_read_en(mb0_ict_read_en),
  .mb0_ict_write_en(mb0_ict_write_en),
  .mb0_icd_read_en(mb0_icd_read_en),
  .mb0_icd_write_en(mb0_icd_write_en),
  .mb0_icv_read_en(mb0_icv_read_en),
  .mb0_icv_write_en(mb0_icv_write_en),
  .mb0_itb_read_en(mb0_itb_read_en),
  .mb0_itb_write_en(mb0_itb_write_en),
  .mb0_write_data(mb0_write_data[7:0]),
  .mb0_dca_read_en(mb0_dca_read_en),
  .mb0_dca_write_en(mb0_dca_write_en),
  .mb0_dta_read_en(mb0_dta_read_en),
  .mb0_dta_write_en(mb0_dta_write_en),
  .mb0_dva_read_en(mb0_dva_read_en),
  .mb0_dva_write_en(mb0_dva_write_en),
  .mb0_lru_read_en(mb0_lru_read_en),
  .mb0_lru_write_en(mb0_lru_write_en),
  .mb0_dtb_read_en(mb0_dtb_read_en),
  .mb0_dtb_write_en(mb0_dtb_write_en),
  .mb0_stb_cam_read_en(mb0_stb_cam_read_en),
  .mb0_stb_cam_write_en(mb0_stb_cam_write_en),
  .mb0_stb_ram_read_en(mb0_stb_ram_read_en),
  .mb0_stb_ram_write_en(mb0_stb_ram_write_en),
  .mb0_cpq_read_en(mb0_cpq_read_en),
  .mb0_cpq_write_en(mb0_cpq_write_en),
  .mbi_cambist_run(mbi_cambist_run),
  .mbi_cambist_shift(mbi_cambist_shift),
  .mbi_dis_clr_ubit(mbi_dis_clr_ubit),
  .mbi_init_to_zero(mbi_init_to_zero),
  .mbi_dtb_cam_en_pre(mbi_dtb_cam_en_pre),
  .mbi_dtb_demap_en(mbi_dtb_demap_en),
  .mbi_itb_cam_en_pre(mbi_itb_cam_en_pre),
  .mbi_itb_demap_en(mbi_itb_demap_en),
  .mbi_repl_write(mbi_repl_write),
  .mbi_demap_type(mbi_demap_type[1:0]),
  .mbi_ptag_data(mbi_ptag_data),
  .mbi_scm_cam_en_pre(mbi_scm_cam_en_pre),
  .lsu_misc_pmen(lsu_misc_pmen),
  .lsu_mbi_dca_fail(lsu_mbi_dca_fail),
  .lsu_mbi_dta_fail(lsu_mbi_dta_fail),
  .lsu_mbi_dva_fail(lsu_mbi_dva_fail),
  .lsu_mbi_lru_fail(lsu_mbi_lru_fail),
  .lsu_mbi_dtb_fail(lsu_mbi_dtb_fail),
  .lsu_mbi_stb_cam_fail(lsu_mbi_stb_cam_fail),
  .lsu_mbi_stb_ram_fail(lsu_mbi_stb_ram_fail),
  .lsu_mbi_cpq_fail(lsu_mbi_cpq_fail),
  .ftu_mbi_ict_fail(ftu_mbi_ict_fail),
  .ftu_mbi_icd_fail(ftu_mbi_icd_fail),
  .ftu_mbi_itb_fail(ftu_mbi_itb_fail),
  .ftu_mbi_icv_fail(ftu_mbi_icv_fail),
  .lsu_mbi_tlb_data_cmp(lsu_mbi_tlb_data_cmp),
  .lsu_mbi_tlb_cam_hit(lsu_mbi_tlb_cam_hit),
  .lsu_mbi_tlb_cam_mhit(lsu_mbi_tlb_cam_mhit),
  .lsu_mbi_tlb_ctxt0_hit(lsu_mbi_tlb_ctxt0_hit),
  .lsu_mbi_tlb_valid(lsu_mbi_tlb_valid),
  .lsu_mbi_tlb_used(lsu_mbi_tlb_used),
  .lsu_mbi_scm_hit(lsu_mbi_scm_hit),
  .lsu_mbi_scm_mhit(lsu_mbi_scm_mhit),
  .lsu_mbi_scm_hit_ptr(lsu_mbi_scm_hit_ptr[2:0]),
  .lsu_mbi_scm_praw(lsu_mbi_scm_praw),
  .ftu_mbi_tlb_data_cmp(ftu_mbi_tlb_data_cmp),
  .ftu_mbi_tlb_cam_hit(ftu_mbi_tlb_cam_hit),
  .ftu_mbi_tlb_cam_mhit(ftu_mbi_tlb_cam_mhit),
  .ftu_mbi_tlb_ctxt0_hit(ftu_mbi_tlb_ctxt0_hit),
  .ftu_mbi_tlb_valid(ftu_mbi_tlb_valid),
  .ftu_mbi_tlb_used(ftu_mbi_tlb_used)

);

spc_mb1_ctl mb1 (	
	.scan_in(mb1_scanin),
	.scan_out(mb1_scanout),
        .tcu_pce_ov			(pce_ov_tl),
        .tcu_scan_en			(lb_scan_en_tl),
	.tcu_aclk               	(spc_aclk_tl),
	.tcu_bclk               	(spc_bclk_tl),
        .tcu_clk_stop(1'b0),
	.l2clk				(l2clk),
	.mbist_start			(tcu_spc_mbist_start_buf0),
    .mb1_mbist_fail			(mb1_mb0_fail),
	.mbist_user_mode		(msf0_mbist_user_mode_ff),
	.mbist_bisi_mode		(msf0_mbist_bisi_en_ff),
    .mb1_done                       (mb1_mb0_done),
	.mb1_addr                       ({mb1_addr_unused[15:8],mb1_addr[7:0]}),
  .mb1_run(mb1_run),
  .mb1_cmpsel(mb1_cmpsel[4:0]),
  .mb1_write_data(mb1_write_data[7:0]),
  .mb1_tsa0_read_en(mb1_tsa0_read_en),
  .mb1_tsa0_write_en(mb1_tsa0_write_en),
  .mb1_tsa1_read_en(mb1_tsa1_read_en),
  .mb1_tsa1_write_en(mb1_tsa1_write_en),
  .mb1_tca_read_en(mb1_tca_read_en),
  .mb1_tca_write_en(mb1_tca_write_en),
  .mb1_scp0_read_en(mb1_scp0_read_en),
  .mb1_scp0_write_en(mb1_scp0_write_en),
  .mb1_scp1_read_en(mb1_scp1_read_en),
  .mb1_scp1_write_en(mb1_scp1_write_en),
  .mb1_mra0_read_en(mb1_mra0_read_en),
  .mb1_mra0_write_en(mb1_mra0_write_en),
  .mb1_mra1_read_en(mb1_mra1_read_en),
  .mb1_mra1_write_en(mb1_mra1_write_en),
  .mb2_misc_pmen(mb2_misc_pmen),
  .mmu_mbi_mra0_fail(mmu_mbi_mra0_fail),
  .mmu_mbi_mra1_fail(mmu_mbi_mra1_fail),
  .mmu_mbi_scp0_fail(mmu_mbi_scp0_fail),
  .mmu_mbi_scp1_fail(mmu_mbi_scp1_fail),
  .tlu_mbi_tsa0_fail(tlu_mbi_tsa0_fail),
  .tlu_mbi_tsa1_fail(tlu_mbi_tsa1_fail),
  .tlu_mbi_tca_fail(tlu_mbi_tca_fail)
			
);

spc_mb2_ctl mb2 (	
	.scan_in(mb2_scanin),
	.scan_out(mb2_scanout),
        .tcu_pce_ov			(pce_ov_tr),
        .tcu_scan_en			(lb_scan_en_tr),
	.tcu_aclk               	(spc_aclk_tr),
	.tcu_bclk               	(spc_bclk_tr),
        .tcu_clk_stop(1'b0),
	.l2clk				(l2clk),
	.mbist_start			(tcu_spc_mbist_start_buf0),
	.mbist_user_mode		(msf0_mbist_user_mode_ff),
	.mbist_bisi_mode		(msf0_mbist_bisi_en_ff),
    .mb2_mbist_fail			(mb2_mb0_fail),
    .mb2_done               (mb2_mb0_done),
	.mb2_addr               ({mb2_addr_unused[15:10],mb2_addr[9:0]}),
  .mb2_run(mb2_run),
  .mb2_frf_read_en(mb2_frf_read_en),
  .mb2_frf_write_en(mb2_frf_write_en),
  .mb2_arf_read_en(mb2_arf_read_en),
  .mb2_arf_write_en(mb2_arf_write_en),
  .mb2_irf_read_en(mb2_irf_read_en),
  .mb2_irf_write_en(mb2_irf_write_en),
  .mb2_irf_save_en(mb2_irf_save_en),
  .mb2_irf_restore_en(mb2_irf_restore_en),
  .mb2_mam_read_en(mb2_mam_read_en),
  .mb2_mam_write_en(mb2_mam_write_en),
  .mb2_rrf_read_en(mb2_rrf_read_en),
  .mb2_rrf_write_en(mb2_rrf_write_en),
  .mb2_write_data(mb2_write_data[7:0]),
  .mb2_write_data_p1(mb2_write_data_p1[7:0]),
  .mb2_write_data_p2(mb2_write_data_p2[7:0]),
  .mb2_misc_pmen(mb2_misc_pmen),
  .lsu_misc_pmen(lsu_misc_pmen),
  .spu_mbi_mam_fail_(spu_mbi_mam_fail_),
  .spu_mbi_mam_fail2_(spu_mbi_mam_fail2_),
  .spu_mbi_arf_fail_(spu_mbi_arf_fail_),
  .spu_mbi_rrf_fail_(spu_mbi_rrf_fail_),
  .exu0_mbi_irf_fail_(exu0_mbi_irf_fail_[1:0]),
  .exu1_mbi_irf_fail_(exu1_mbi_irf_fail_[1:0]),
  .fgu_mbi_frf_fail(fgu_mbi_frf_fail)
);


// Check that the asi values mirrored in the TLU are consistent with those in the LSU.
// Anytime an instruction decodes for a thread, that's thread's ASI's must be equal.
// 0in custom -fire ((dec_valid0_d & (dec_tid0_d[1:0] == 2'b00)) & ~(lsu.dcs.asi_state0[7:0] == tlu.tsd0.asi0[7:0])) -message "T0 ASI registers are inconsistent"
// 0in custom -fire ((dec_valid0_d & (dec_tid0_d[1:0] == 2'b01)) & ~(lsu.dcs.asi_state1[7:0] == tlu.tsd0.asi1[7:0])) -message "T1 ASI registers are inconsistent"
// 0in custom -fire ((dec_valid0_d & (dec_tid0_d[1:0] == 2'b10)) & ~(lsu.dcs.asi_state2[7:0] == tlu.tsd0.asi2[7:0])) -message "T2 ASI registers are inconsistent"
// 0in custom -fire ((dec_valid0_d & (dec_tid0_d[1:0] == 2'b11)) & ~(lsu.dcs.asi_state3[7:0] == tlu.tsd0.asi3[7:0])) -message "T3 ASI registers are inconsistent"
// 0in custom -fire ((dec_valid1_d & (dec_tid1_d[1:0] == 2'b00)) & ~(lsu.dcs.asi_state4[7:0] == tlu.tsd1.asi0[7:0])) -message "T4 ASI registers are inconsistent"
// 0in custom -fire ((dec_valid1_d & (dec_tid1_d[1:0] == 2'b01)) & ~(lsu.dcs.asi_state5[7:0] == tlu.tsd1.asi1[7:0])) -message "T5 ASI registers are inconsistent"
// 0in custom -fire ((dec_valid1_d & (dec_tid1_d[1:0] == 2'b10)) & ~(lsu.dcs.asi_state6[7:0] == tlu.tsd1.asi2[7:0])) -message "T6 ASI registers are inconsistent"
// 0in custom -fire ((dec_valid1_d & (dec_tid1_d[1:0] == 2'b11)) & ~(lsu.dcs.asi_state7[7:0] == tlu.tsd1.asi3[7:0])) -message "T7 ASI registers are inconsistent"


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
// fixscan start:
//assign gkt_scanin                = scan_in[0]               ;
//assign fgu_scanin                = gkt_scanout              ;
//assign ifu_ibu_scanin            = fgu_scanout              ;
//assign ifu_ftu_scanin            = ifu_ibu_scanout          ;
//assign ifu_cmu_scanin            = ifu_ftu_scanout          ;
//assign dec_scanin                = ifu_cmu_scanout          ;
//assign pku_scanin                = dec_scanout              ;
//assign exu0_scanin               = pku_scanout              ;
//assign exu1_scanin               = exu0_scanout             ;
//assign tlu_scanin                = exu1_scanout             ;
//assign lsu_scanin                = tlu_scanout              ;
//assign spu_scanin                = lsu_scanout              ;
//assign mmu_scanin                = spu_scanout              ;
//assign pmu_scanin                = mmu_scanout              ;

// MBIST Scan Chain
assign mb0_scanin                = lb_mb_channel_si;
assign mb1_scanin                = mb0_scanout;
assign mb2_scanin                = mb1_scanout;

// Main Scan Chain
//assign scan_out[0]               = pmu_scanout;

// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spc_lb_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`define    SHFT_LENGTH  15'b010_0000_0000_0000		// (Longest) Shift Length
`define    VECT_COUNT   16'b0000_0000_0000_0011		// Vector Count
`define    PRPG_SEED    24'h111111			// PRPG Seed (non-zero)
`define    CH_BYP       16'b0000_0000_0000_0000		// Bypass Channels (Outputs)

module spc_lb_ctl (
  l2clk, 
  tcu_pce_ov, 
  scan_in, 
  scan_out, 
  aclk, 
  bclk, 
  scan_en, 
  se_scancollar_in, 
  se_scancollar_out, 
  clk_stop, 
  test_mode, 
  wmr_protect, 
  array_wr_inhibit, 
  io_si, 
  mbist_si, 
  io_so, 
  mbist_so, 
  lbist_start, 
  lbist_pgm, 
  lbist_done, 
  lbist_run, 
  channel_so, 
  mb_channel_so, 
  channel_si, 
  mb_channel_si, 
  core_aclk, 
  core_bclk, 
  core_scan_en, 
  core_scan_en_wmr, 
  core_se_sc_in, 
  core_se_sc_out, 
  core_clk_stop, 
  core_awi, 
  slow_cmp_sync_en, 
  core_isolate);
wire pce_ov;
wire stop;
wire lb_int_clk_stop;
wire se;
wire siclk;
wire soclk;
wire clock_enable;
wire [4:0] lbcontrol_out;
wire lbl2clk;
wire l1clk_pm1;
wire frl1clk;
wire lb_clkstop_reg_scanin;
wire lb_clkstop_reg_scanout;
wire lb_iocmpsyncen_reg_scanin;
wire lb_iocmpsyncen_reg_scanout;
wire io_cmp_sync_en_local;
wire lb_control_reg_scanin;
wire lb_control_reg_scanout;
wire [4:0] lbcontrol_new;
wire reset;
wire lb_done;
wire load_default;
wire load_pgm;
wire capclk_done;
wire init_done;
wire init_cycle;
wire vect_count_equal;
wire capture_mode;
wire vect_unload_done;
wire lb_shftpgm_reg_scanin;
wire lb_shftpgm_reg_scanout;
wire [14:0] shft_pgm_new;
wire [14:0] shft_pgm_out;
wire lb_shftcnt_reg_scanin;
wire lb_shftcnt_reg_scanout;
wire [18:0] shft_cnt_new;
wire [18:0] shft_cnt_out;
wire shift_chains;
wire shft_count_equal;
wire capclk_cycle;
wire lb_capclkcnt_reg_scanin;
wire lb_capclkcnt_reg_scanout;
wire [4:0] capclk_cnt_new;
wire [4:0] capclk_cnt_out;
wire lb_vectpgm_reg_scanin;
wire lb_vectpgm_reg_scanout;
wire [15:0] vect_pgm_new;
wire [15:0] vect_pgm_out;
wire lb_vectorcnt_reg_scanin;
wire lb_vectorcnt_reg_scanout;
wire [15:0] vect_cnt_new;
wire [15:0] vect_cnt_out;
wire increase_vect_cnt;
wire lb_clk_stop;
wire lb_scan_en;
wire lb_aclk;
wire lb_bclk;
wire lb_prpg_reg_scanin;
wire lb_prpg_reg_scanout;
wire [23:0] prpg_new;
wire [23:0] prpg_out;
wire prpg_run;
wire [23:0] prpg_calc;
wire prpg_xor7_out;
wire prpg_xor2_out;
wire prpg_xor1_out;
wire lb_misr_reg_scanin;
wire lb_misr_reg_scanout;
wire [23:0] misr_new;
wire [23:0] misr_out;
wire misr_run;
wire [23:0] misr_calc;
wire misr_xor7_out;
wire [15:0] misr_ch;
wire misr_xor2_out;
wire misr_xor1_out;
wire [15:0] ch_byp;
wire lb_cb_reg_scanin;
wire lb_cb_reg_scanout;
wire [15:0] cb_new;
wire [15:0] cb_out;
wire lb_done_reg_scanin;
wire lb_done_reg_scanout;
wire spare_scanin;
wire spare_scanout;

   
   input         l2clk;
   input         tcu_pce_ov;

   // Scan input/output for this block 
   input 	 scan_in;
   output 	 scan_out;

   // Scan Controls for Core & this block (LBIST) are shared
   input 	 aclk;              // Core aclk from TCU
   input 	 bclk;              // Core bclk from TCU
   input 	 scan_en;           // Core scan_en from TCU
   input         se_scancollar_in;
   input         se_scancollar_out;
   input         clk_stop;          // Core clk_stop from TCU; must be low 
                                    //  to run Logic BIST
   input         test_mode;         // From TCU, indicates ATPG mode
   input         wmr_protect;       // From cluster header, protect warm scan outputs
   input         array_wr_inhibit;  // From TCU 

   input   [1:0] io_si;             // From pins: Core scan chain for ATPG 
   input         mbist_si;          // From TCU:  To core's mbist scan chain
   output  [1:0] io_so;             // To pins:   Core scan chain for ATPG
   output        mbist_so;          // To TCU:    From core's mbist scan chain
   
   // Logic BIST Control Signals
   input 	 lbist_start;       // Drive high and hold to run Logic BIST
   input 	 lbist_pgm;         // Use programmed values, not defaults
   // Logic BIST Status Signals
   output        lbist_done;        // Indicates Logic BIST is done
   output        lbist_run;         // Indicates Logic BIST is running

   input  [15:0] channel_so;        // Receives so from core scan chains
   input         mb_channel_so;     // Receives so from core mbist chain
   output [15:0] channel_si;        // Feeds si of Core scan chains
   output        mb_channel_si;     // Feeds si of core's mbist chain

   output        core_aclk;         // aclk to Core scan chains
   output        core_bclk;         // bclk to Core scan chains
   output        core_scan_en;      // scan_en to Core scan chains
   output        core_scan_en_wmr;  // scan_en to Core scan chains, wmr protect version
   output        core_se_sc_in;     // se_scancollar_in to Core scan chains
   output        core_se_sc_out;    // se_scancollar_out to Core scan chains
   output        core_clk_stop;     // clk_stop to Core scan chains
   output        core_awi;          // array write inhibit to cluster header

   // Sync Enable
   input         slow_cmp_sync_en;  // io_cmp_sync_en from cluster header

   // Signal to isolate SPC from CCX
   output        core_isolate;      // Blocks requests to CCX
  
   // ********************************************************************
   // Scan reassigns
   // ********************************************************************
   assign        pce_ov = tcu_pce_ov;
   assign        stop   = lb_int_clk_stop; // this must be free-running
   assign 	 se     = scan_en;
   assign        siclk  = aclk;
   assign        soclk  = bclk;


   assign     clock_enable        =  lbist_start | lbcontrol_out[1] | lbist_done;

 `ifndef FPGA
   // synopsys translate_off
   spc_lb_ctll1clkhdr_ctl_macro lbist_clkgen 
     (.l2clk    (lbl2clk),
      .l1en     (clock_enable),
      .l1clk    (l1clk_pm1),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se) );
     
   // ********************************************************************
   // Buffer Clock for LBIST to flop headers & Add Staging Flop for
   // LBIST internal clock stop with its own Flop Header
   // ********************************************************************
   cl_u1_buf_4x lbist_clkbuf // instantiated at back-end request to 
     (.in       (l2clk),     //  isolate clock
      .out      (lbl2clk) );

   spc_lb_ctll1clkhdr_ctl_macro lbist_frclkgen 
     (.l2clk    (lbl2clk),
      .l1en     (1'b1),
      .stop     (1'b0),
      .l1clk    (frl1clk),
  .pce_ov(pce_ov),
  .se(se) ); // free-run clock only to clk_stop staging flop

   // synopsys translate_on
`endif
   spc_lb_ctlmsff_ctl_macro__width_1 lb_clkstop_reg 
   (
    .scan_in(lb_clkstop_reg_scanin),
    .scan_out(lb_clkstop_reg_scanout),
    .l1clk    (frl1clk),
    .din      (clk_stop),
    .dout     (lb_int_clk_stop),
  .siclk(siclk),
  .soclk(soclk) // internal clock stop
    );
   
   // ********************************************************************
   // Flop io_cmp_sync_en
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__width_1 lb_iocmpsyncen_reg 
   (
    .scan_in(lb_iocmpsyncen_reg_scanin),
    .scan_out(lb_iocmpsyncen_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (slow_cmp_sync_en),
    .dout     (io_cmp_sync_en_local),
  .siclk(siclk),
  .soclk(soclk) 
    );

   // ********************************************************************
   // Control Register
   // Drive lbist_pgm to prevent reset updates to registers, allows
   //  programmed values to be used instead of defaults
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__width_5 lb_control_reg 
   (
    .scan_in(lb_control_reg_scanin),
    .scan_out(lb_control_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (lbcontrol_new[4:0]),
    .dout     (lbcontrol_out[4:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
  
   // Generate reset, run signals off of start
   assign     lbcontrol_new[0]    =  io_cmp_sync_en_local  ?  lbist_start :   lbcontrol_out[0];
   assign     lbcontrol_new[1]    =  lbcontrol_out[0];
   assign     reset               =  lbcontrol_out[0]	   & ~lbcontrol_out[1];
   
   // Allow clk_stop to core to override lbist control of core_clk_stop for scan dumps
   assign     lbist_run           =  lbcontrol_out[1]      & ~lb_done     &  ~test_mode;// & ~clk_stop;

   // User drives this bit to use programmed values
   assign     lbcontrol_new[2]    =  lbist_pgm;
   assign     load_default        =  reset                 & ~lbcontrol_out[2]; 
   assign     load_pgm            =  reset                 &  lbcontrol_out[2]; 

   // bits [3] & [4] used for control
   assign     lbcontrol_new[3]	  =  reset                 ?  1'b0           
                                  :  capclk_done           ?  1'b1
                                  :  lbcontrol_out[3];
   assign     init_done           =  lbcontrol_out[1]      &  lbcontrol_out[3];
   assign     init_cycle          =  lbist_run             & ~init_done;

   assign     lbcontrol_new[4]	  =  reset                 ?  1'b0
                                  :  vect_count_equal & capture_mode  ? 1'b1
                                  :  lbcontrol_out[4];
   assign     vect_unload_done    =  lbcontrol_out[4];

   // ********************************************************************
   // Shift Counter
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__width_15 lb_shftpgm_reg 
   (
    .scan_in(lb_shftpgm_reg_scanin),
    .scan_out(lb_shftpgm_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (shft_pgm_new[14:0]),
    .dout     (shft_pgm_out[14:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
   // Hard-coded default shift count equal to length of longest core scan chain during LBist 
   assign     shft_pgm_new[14:0]  =  load_default          ?  `SHFT_LENGTH
                                  :  shft_pgm_out[14:0];

   spc_lb_ctlmsff_ctl_macro__width_19 lb_shftcnt_reg 
   (
    .scan_in(lb_shftcnt_reg_scanin),
    .scan_out(lb_shftcnt_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (shft_cnt_new[18:0]),
    .dout     (shft_cnt_out[18:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
   assign     shft_cnt_new[18:0]  =  load_default          ?  {`SHFT_LENGTH,4'b0000}
                                  :  load_pgm              ?  {shft_pgm_out[14:0],4'b0000}
                                  :  shift_chains          ?  (shft_cnt_out[18:0] + 19'b1) 
                                  :  capclk_done           ?  19'b0
                                  :  shft_cnt_out[18:0];

   // 4 lsb's are used to generate and separate a, bclks during lbist 
   // to provide 7 cycles between aclk to bclk changes and bclk to aclk changes
   assign     shft_count_equal    =  (shft_cnt_out[18:4]  ==  shft_pgm_out[14:0]);
   assign     shift_chains        =  lbist_run             & ~shft_count_equal    & ~capclk_cycle;

   // ********************************************************************
   // Capture Clock Counter
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__width_5 lb_capclkcnt_reg 
   (
    .scan_in(lb_capclkcnt_reg_scanin),
    .scan_out(lb_capclkcnt_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (capclk_cnt_new[4:0]),
    .dout     (capclk_cnt_out[4:0]),
  .siclk(siclk),
  .soclk(soclk)
   );

   assign     capclk_cnt_new[4:0] =  reset                 ?  5'b10010 
                                  :  capclk_cycle          ?  (capclk_cnt_out[4:0] + 5'b1)
                                  :  capclk_cnt_out[4:0];

   assign     capclk_cycle        =  (shft_count_equal      |  (reset  & shft_count_equal)) & lbist_run;
   assign     capclk_done         =  (capclk_cnt_out[4:0] ==  5'b11111);

   // ********************************************************************
   // Vector Counter
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__width_16 lb_vectpgm_reg 
   (
    .scan_in(lb_vectpgm_reg_scanin),
    .scan_out(lb_vectpgm_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (vect_pgm_new[15:0]),
    .dout     (vect_pgm_out[15:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
   // Hard-coded default vector count equal to 2^^15
   // msb used to indicate done 
   assign     vect_pgm_new[15:0]  =  load_default          ?  `VECT_COUNT
                                  :  vect_pgm_out[15:0];

   spc_lb_ctlmsff_ctl_macro__width_16 lb_vectorcnt_reg 
   (
    .scan_in(lb_vectorcnt_reg_scanin),
    .scan_out(lb_vectorcnt_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (vect_cnt_new[15:0]),
    .dout     (vect_cnt_out[15:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
   
   // Set vector count equal to number of vector patterns desired; user can define also
   assign     vect_count_equal    =  (vect_cnt_out[15:0]  ==  vect_pgm_out[15:0]);

   assign     vect_cnt_new[15:0]  =  reset                 ?  16'b0 
                                  :  increase_vect_cnt     ?  (vect_cnt_out[15:0] + 16'b1) 
                                  :  vect_cnt_out[15:0];

   assign     lb_done             =  (vect_cnt_out[15]     |  vect_unload_done)   &  lbcontrol_out[1];

   assign     increase_vect_cnt   =  lbist_run             &  capclk_done         &  ~init_cycle; 

   // ********************************************************************
   // Generate Scan Controls for Core 
   //  Logic BIST Mode: LBist drives signals
   //  Else: Signals sourced externally to Core
   // LBIST can't drive scan controls when test_mode driven 'high'
   // When clk_stop is 'high', lbist loses control of scan 
   // Note:
   //    Bclk, Scan_En and Clk_Stop are separated to insure minimum multi-cycle paths
   //    are met; bclk to scan_en = 3 cycles; scan_en to bclk = 3 cycles;
   //    bclk to clk_stop = 3 cycles; clk_stop to bclk = 1 cycle (clk_stop timed) 
   // ********************************************************************

   assign     core_clk_stop       = (lbist_run             &  lb_clk_stop)        |  clk_stop;
   assign     core_scan_en        =  lbist_run             ?  lb_scan_en          :  scan_en; 
   assign     core_scan_en_wmr    =  wmr_protect           ?  1'b0                :  core_scan_en; 
   assign     core_se_sc_in       =  lbist_run             ?  lb_scan_en          :  se_scancollar_in;
   assign     core_se_sc_out      =  lbist_run             ?  1'b1                :  se_scancollar_out;
   assign     core_awi            = (lbist_run             &  capclk_cycle)       |  array_wr_inhibit;

   // Clock stop occurs out of cluster header with 4-cycle latency
   assign     lb_clk_stop         = ~(capclk_cnt_out[4:0] ==  5'b10001)  // ~h11 to effect h15
                                  & ~(capclk_cnt_out[4:0] ==  5'b10010); // ~h12 to effect h16

   assign     core_aclk           =  lbist_run             ?  lb_aclk             :  aclk;
   assign     core_bclk           =  lbist_run             ?  lb_bclk             :  bclk;

   assign     lb_aclk             =  (shft_cnt_out[3:0]   ==  4'b0111); //  h7
   assign     lb_bclk             = ~(shft_cnt_out[3:0]   ==  4'b1111)  //  hF
                                  & ~(capclk_cnt_out[4:0] ==  5'b01110) // ~h0E
                                  & ~(capclk_cnt_out[4:0] ==  5'b01111) // ~h0F
                                  & ~(capclk_cnt_out[4:0] ==  5'b10000) // ~h10
                                  & ~(capclk_cnt_out[4:0] ==  5'b10001) // ~h11
                                  & ~(capclk_cnt_out[4:0] ==  5'b10010) // ~h12
                                  & ~(capclk_cnt_out[4:0] ==  5'b10011) // ~h13
                                  & ~(capclk_cnt_out[4:0] ==  5'b10100) // ~h14
                                  & ~(capclk_cnt_out[4:0] ==  5'b10101) // ~h15
                                  & ~(capclk_cnt_out[4:0] ==  5'b10110) // ~h16
                                  & ~(capclk_cnt_out[4:0] ==  5'b10111);// ~h17

   // Note: exit scan shift mode, first turn off scan_en, then turn off bclk
   assign     lb_scan_en          = ~(capclk_cnt_out[4:0] ==  5'b00111) // ~h07
                                  & ~(capclk_cnt_out[4:0] ==  5'b01000) // ~h08
                                  & ~(capclk_cnt_out[4:0] ==  5'b01001) // ~h09
                                  & ~(capclk_cnt_out[4:0] ==  5'b01010) // ~h0A
                                  & ~(capclk_cnt_out[4:0] ==  5'b01011) // ~h0B
                                  & ~(capclk_cnt_out[4:0] ==  5'b01100) // ~h0C
                                  & ~(capclk_cnt_out[4:0] ==  5'b01101) // ~h0D
                                  & ~(capclk_cnt_out[4:0] ==  5'b01110) // ~h0E
                                  & ~(capclk_cnt_out[4:0] ==  5'b01111) // ~h0F
                                  & ~(capclk_cnt_out[4:0] ==  5'b10000) // ~h10
                                  & ~(capclk_cnt_out[4:0] ==  5'b10001) // ~h11
                                  & ~(capclk_cnt_out[4:0] ==  5'b10010) // ~h12
                                  & ~(capclk_cnt_out[4:0] ==  5'b10011) // ~h13
                                  & ~(capclk_cnt_out[4:0] ==  5'b10100) // ~h14
                                  & ~(capclk_cnt_out[4:0] ==  5'b10101) // ~h15
                                  & ~(capclk_cnt_out[4:0] ==  5'b10110) // ~h16
                                  & ~(capclk_cnt_out[4:0] ==  5'b10111) // ~h17
                                  & ~(capclk_cnt_out[4:0] ==  5'b11000) // ~h18
                                  & ~(capclk_cnt_out[4:0] ==  5'b11001) // ~h19
                                  & ~(capclk_cnt_out[4:0] ==  5'b11010) // ~h1A
                                  & ~(capclk_cnt_out[4:0] ==  5'b11011) // ~h1B
                                  & ~(capclk_cnt_out[4:0] ==  5'b11100) // ~h1C
                                  & ~(capclk_cnt_out[4:0] ==  5'b11101) // ~h1D
                                  & ~(capclk_cnt_out[4:0] ==  5'b11110) // ~h1E
                                  & ~(capclk_cnt_out[4:0] ==  5'b11111);// ~h1F

   assign     capture_mode        = ~lb_aclk   & ~lb_bclk  & ~lb_scan_en  & ~lb_clk_stop; 

   // ********************************************************************
   // Psuedo-Random Pattern Generator - updates on bclk
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__width_24 lb_prpg_reg 
   (
    .scan_in(lb_prpg_reg_scanin),
    .scan_out(lb_prpg_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (prpg_new[23:0]),
    .dout     (prpg_out[23:0]),
  .siclk(siclk),
  .soclk(soclk)
   );

   // Hard-coded default Seed can be overridden; Seed must not be zero
   assign     prpg_new[23:0]      =  load_default          ?  `PRPG_SEED
                                  :  load_pgm              ?  prpg_out[23:0]
                                  :  prpg_run              ?  prpg_calc[23:0]
                                  :  prpg_out[23:0];

   // f(x) = x^^24 + x^^7 + x^^2 + x^^1 + 1
   assign     prpg_calc[23]       =  prpg_xor7_out;
   assign     prpg_calc[22:0]     =  prpg_out[23:1];

   assign     prpg_xor7_out       =  prpg_out[7]           ^  prpg_xor2_out;
   assign     prpg_xor2_out       =  prpg_out[2]           ^  prpg_xor1_out;
   assign     prpg_xor1_out       =  prpg_out[1]           ^  prpg_out[0];

   assign     prpg_run            = ~core_bclk             &  lbist_run           
                                  &  init_done             & ~capclk_cycle;

   // ********************************************************************
   // Pattern Compactor - updates on aclk
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__width_24 lb_misr_reg 
   (
    .scan_in(lb_misr_reg_scanin),
    .scan_out(lb_misr_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (misr_new[23:0]),
    .dout     (misr_out[23:0]),
  .siclk(siclk),
  .soclk(soclk)
   );

   assign     misr_new[23:0]      =  reset                 ?  24'b0
                                  :  misr_run              ?  misr_calc[23:0]
                                  :  misr_out[23:0];

   assign     misr_run            =  core_aclk             &  lbist_run
                                  &  init_done             & ~capclk_cycle
                                  &  (|(vect_cnt_out[15:0]));

   // f(x) = x^^24 + x^^7 + x^^2 + x^^1 + 1
   assign     misr_calc[23]       =  misr_xor7_out;
   assign     misr_calc[22:16]    =  misr_out[23:17];
   assign     misr_calc[15]       =  misr_out[16]          ^  misr_ch[15];
   assign     misr_calc[14]       =  misr_out[15]          ^  misr_ch[14];
   assign     misr_calc[13]       =  misr_out[14]          ^  misr_ch[13];
   assign     misr_calc[12]       =  misr_out[13]          ^  misr_ch[12];
   assign     misr_calc[11]       =  misr_out[12]          ^  misr_ch[11];
   assign     misr_calc[10]       =  misr_out[11]          ^  misr_ch[10];
   assign     misr_calc[9]        =  misr_out[10]          ^  misr_ch[9];
   assign     misr_calc[8]        =  misr_out[9]           ^  misr_ch[8];
   assign     misr_calc[7]        =  misr_out[8]           ^  misr_ch[7];
   assign     misr_calc[6]        =  misr_out[7]           ^  misr_ch[6];
   assign     misr_calc[5]        =  misr_out[6]           ^  misr_ch[5];
   assign     misr_calc[4]        =  misr_out[5]           ^  misr_ch[4];
   assign     misr_calc[3]        =  misr_out[4]           ^  misr_ch[3];
   assign     misr_calc[2]        =  misr_out[3]           ^  misr_ch[2];
   assign     misr_calc[1]        =  misr_out[2]           ^  misr_ch[1];
   assign     misr_calc[0]        =  misr_out[1]           ^  misr_ch[0];

   assign     misr_xor7_out       =  misr_out[7]           ^  misr_xor2_out;
   assign     misr_xor2_out       =  misr_out[2]           ^  misr_xor1_out;
   assign     misr_xor1_out       =  misr_out[1]           ^  misr_out[0];

   // ********************************************************************
   // Drive Channels to Core
   // ********************************************************************
   // These feed the scan_in of the channels in the core
   // Outputs to Core Scan Chains (16 Channels + mbist)
   // Channel 15 is the warm reset protected scan-out from the SPC
// assign     channel_si[15]      =  lbist_run             ?  prpg_out[15]        :  1'b0;
// assign     channel_si[14]      =  lbist_run             ?  prpg_out[14]        :  io_si[1];
   assign     channel_si[15]      =  lbist_run             ?  prpg_out[15]        :  io_si[1];
   assign     channel_si[14]      =  lbist_run             ?  prpg_out[14]        :  wmr_protect ? 1'b0 : channel_so[15];
   assign     channel_si[13]      =  lbist_run             ?  prpg_out[13]        :  channel_so[14];
   assign     channel_si[12]      =  lbist_run             ?  prpg_out[12]        :  channel_so[13];
   assign     channel_si[11]      =  lbist_run             ?  prpg_out[11]        :  channel_so[12]; 
   assign     channel_si[10]      =  lbist_run             ?  prpg_out[10]        :  channel_so[11]; 
   assign     channel_si[9]       =  lbist_run             ?  prpg_out[9]         :  channel_so[10]; 
   assign     channel_si[8]       =  lbist_run             ?  prpg_out[8]         :  channel_so[9];
   assign     channel_si[7]       =  lbist_run             ?  prpg_out[7]         :  channel_so[8]; 
   assign     channel_si[6]       =  lbist_run             ?  prpg_out[6]         :  channel_so[7];
   assign     channel_si[5]       =  lbist_run             ?  prpg_out[5]         :  channel_so[6]; 
   assign     channel_si[4]       =  lbist_run             ?  prpg_out[4]         :  channel_so[5];
   assign     channel_si[3]       =  lbist_run             ?  prpg_out[3]         :  io_si[0]; 
   assign     channel_si[2]       =  lbist_run             ?  prpg_out[2]         :  channel_so[3];
   assign     channel_si[1]       =  lbist_run             ?  prpg_out[1]         :  channel_so[2];
   assign     channel_si[0]       =  lbist_run             ?  prpg_out[0]         :  channel_so[1];
   assign     mb_channel_si       =  lbist_run             ?  channel_so[0]       :  mbist_si;

   // ********************************************************************
   // Receive Channels from Core
   // ********************************************************************
   // Inputs from Core Scan Chains (16 Channels + mbist)

   // 0in known_driven -var (channel_so[15:0] & ~ch_byp[15:0]) -clock l2clk -active misr_run -group zin_core_lbist  -message "LBIST : X's detected on channel_so"

   assign     misr_ch[15]         =  channel_so[15]        & ~ch_byp[15];
   assign     misr_ch[14]         =  channel_so[14]        & ~ch_byp[14];
   assign     misr_ch[13]         =  channel_so[13]        & ~ch_byp[13];
   assign     misr_ch[12]         =  channel_so[12]        & ~ch_byp[12];
   assign     misr_ch[11]         =  channel_so[11]        & ~ch_byp[11];  
   assign     misr_ch[10]         =  channel_so[10]        & ~ch_byp[10];
   assign     misr_ch[9]          =  channel_so[9]         & ~ch_byp[9];
   assign     misr_ch[8]          =  channel_so[8]         & ~ch_byp[8];
   assign     misr_ch[7]          =  channel_so[7]         & ~ch_byp[7];
   assign     misr_ch[6]          =  channel_so[6]         & ~ch_byp[6];
   assign     misr_ch[5]          =  channel_so[5]         & ~ch_byp[5];
   assign     misr_ch[4]          =  channel_so[4]         & ~ch_byp[4];
   assign     misr_ch[3]          =  channel_so[3]         & ~ch_byp[3];
   assign     misr_ch[2]          =  channel_so[2]         & ~ch_byp[2];
   assign     misr_ch[1]          =  channel_so[1]         & ~ch_byp[1];
   assign     misr_ch[0]          =  mb_channel_so         & ~ch_byp[0];


   assign     io_so[1]            = channel_so[4]; 
   assign     io_so[0]            = channel_so[0];
   assign     mbist_so            = mb_channel_so;
   
   // ********************************************************************
   // Pattern Disable & Channel Bypass
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__width_16 lb_cb_reg 
   (
    .scan_in(lb_cb_reg_scanin),
    .scan_out(lb_cb_reg_scanout),
    .l1clk    (l1clk_pm1),
    .din      (cb_new[15:0]),
    .dout     (cb_out[15:0]),
  .siclk(siclk),
  .soclk(soclk)
   );
   // Default is no channel bypass (16'b0)
   assign     cb_new[15:0]        =  load_default          ?  `CH_BYP
                                  :  load_pgm              ?  cb_out[15:0]
                                  :  cb_out[15:0];
   assign     ch_byp[15:0]        =  cb_out[15:0];

   // ********************************************************************
   // Generate LBist Done on IO Clock Domain
   // ********************************************************************
   spc_lb_ctlmsff_ctl_macro__en_1__width_1 lb_done_reg 
   (
    .scan_in(lb_done_reg_scanin),
    .scan_out(lb_done_reg_scanout),
    .l1clk    (l1clk_pm1),
    .en       (io_cmp_sync_en_local),
    .din      (lb_done),
    .dout     (lbist_done),
  .siclk(siclk),
  .soclk(soclk)
   );

   // ********************************************************************
   // Signal to isolate SPC from CCX; Blocks requests to CCX
   //  during either ATPG or JTAG scan, or during LBIST
   // ********************************************************************
   assign     core_isolate       =   scan_en               |  lbist_run;

   spc_lb_ctlspare_ctl_macro__num_3 spare  
   (
    .l1clk    (l1clk_pm1     ),
    .scan_in  (spare_scanin  ),
    .scan_out (spare_scanout ),
  .siclk(siclk),
  .soclk(soclk)
   );

// fixscan start:lb_clkstop_reg_scanin
assign lb_clkstop_reg_scanin     = scan_in                  ;
assign lb_iocmpsyncen_reg_scanin = lb_clkstop_reg_scanout   ;
assign lb_control_reg_scanin     = lb_iocmpsyncen_reg_scanout ;
assign lb_shftpgm_reg_scanin     = lb_control_reg_scanout   ;
assign lb_shftcnt_reg_scanin     = lb_shftpgm_reg_scanout   ;
assign lb_capclkcnt_reg_scanin   = lb_shftcnt_reg_scanout   ;
assign lb_vectpgm_reg_scanin     = lb_capclkcnt_reg_scanout ;
assign lb_vectorcnt_reg_scanin   = lb_vectpgm_reg_scanout   ;
assign lb_prpg_reg_scanin        = lb_vectorcnt_reg_scanout ;
assign lb_misr_reg_scanin        = lb_prpg_reg_scanout      ;
assign lb_cb_reg_scanin          = lb_misr_reg_scanout      ;
assign lb_done_reg_scanin        = lb_cb_reg_scanout        ;
assign spare_scanin              = lb_done_reg_scanout      ;
assign scan_out                  = spare_scanout            ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module spc_lb_ctll1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module spc_lb_ctlmsff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_lb_ctlmsff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_lb_ctlmsff_ctl_macro__width_15 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [14:0] fdin;
wire [13:0] so;

  input [14:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [14:0] dout;
  output scan_out;
assign fdin[14:0] = din[14:0];


dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[14:0]),
.si({scan_in,so[13:0]}),
.so({so[13:0],scan_out}),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_lb_ctlmsff_ctl_macro__width_19 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [18:0] fdin;
wire [17:0] so;

  input [18:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [18:0] dout;
  output scan_out;
assign fdin[18:0] = din[18:0];


dff #(19)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[18:0]),
.si({scan_in,so[17:0]}),
.so({so[17:0],scan_out}),
.q(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_lb_ctlmsff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_lb_ctlmsff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_lb_ctlmsff_ctl_macro__en_1__width_1 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module spc_lb_ctlspare_ctl_macro__num_3 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));
assign scan_out = so_2;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spc_mb0_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module spc_mb0_ctl (
  scan_out, 
  mb0_done, 
  mb0_run, 
  mb0_addr, 
  mb0_cmpsel, 
  mb0_ict_read_en, 
  mb0_ict_write_en, 
  mb0_icd_read_en, 
  mb0_icd_write_en, 
  mb0_icv_read_en, 
  mb0_icv_write_en, 
  mb0_itb_read_en, 
  mb0_itb_write_en, 
  mb0_write_data, 
  mb0_dca_read_en, 
  mb0_dca_write_en, 
  mb0_dta_read_en, 
  mb0_dta_write_en, 
  mb0_dva_read_en, 
  mb0_dva_write_en, 
  mb0_lru_read_en, 
  mb0_lru_write_en, 
  mb0_dtb_read_en, 
  mb0_dtb_write_en, 
  mb0_stb_cam_read_en, 
  mb0_stb_cam_write_en, 
  mb0_stb_ram_read_en, 
  mb0_stb_ram_write_en, 
  mb0_cpq_read_en, 
  mb0_cpq_write_en, 
  mb0_mbist_fail, 
  mbi_cambist_run, 
  mbi_cambist_shift, 
  mbi_dis_clr_ubit, 
  mbi_init_to_zero, 
  mbi_dtb_cam_en_pre, 
  mbi_dtb_demap_en, 
  mbi_itb_cam_en_pre, 
  mbi_itb_demap_en, 
  mbi_repl_write, 
  mbi_demap_type, 
  mbi_ptag_data, 
  mbi_scm_cam_en_pre, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_clk_stop, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  lsu_misc_pmen, 
  mbist_start, 
  mbist_bisi_mode, 
  mbist_user_mode, 
  lsu_mbi_dca_fail, 
  lsu_mbi_dta_fail, 
  lsu_mbi_dva_fail, 
  lsu_mbi_lru_fail, 
  lsu_mbi_dtb_fail, 
  lsu_mbi_stb_cam_fail, 
  lsu_mbi_stb_ram_fail, 
  lsu_mbi_cpq_fail, 
  ftu_mbi_ict_fail, 
  ftu_mbi_icd_fail, 
  ftu_mbi_itb_fail, 
  ftu_mbi_icv_fail, 
  lsu_mbi_tlb_data_cmp, 
  lsu_mbi_tlb_cam_hit, 
  lsu_mbi_tlb_cam_mhit, 
  lsu_mbi_tlb_ctxt0_hit, 
  lsu_mbi_tlb_valid, 
  lsu_mbi_tlb_used, 
  lsu_mbi_scm_hit, 
  lsu_mbi_scm_mhit, 
  lsu_mbi_scm_hit_ptr, 
  lsu_mbi_scm_praw, 
  ftu_mbi_tlb_data_cmp, 
  ftu_mbi_tlb_cam_hit, 
  ftu_mbi_tlb_cam_mhit, 
  ftu_mbi_tlb_ctxt0_hit, 
  ftu_mbi_tlb_valid, 
  ftu_mbi_tlb_used, 
  mb1_mb0_fail, 
  mb2_mb0_fail, 
  mb1_mb0_done, 
  mb2_mb0_done);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire pmen_scanin;
wire pmen_scanout;
wire start_in;
wire misc_pmen_;
wire pmem_unused;
wire clock_enable;
wire l1clk_pm1;
wire array_usr_reg_scanin;
wire array_usr_reg_scanout;
wire [3:0] user_array_in;
wire [3:0] user_array;
wire user_addr_mode_reg_scanin;
wire user_addr_mode_reg_scanout;
wire user_addr_mode_in;
wire user_addr_mode;
wire user_start_addr_reg_scanin;
wire user_start_addr_reg_scanout;
wire [8:0] user_start_addr_in;
wire [8:0] user_start_addr;
wire user_stop_addr_reg_scanin;
wire user_stop_addr_reg_scanout;
wire [8:0] user_stop_addr_in;
wire [8:0] user_stop_addr;
wire user_incr_addr_reg_scanin;
wire user_incr_addr_reg_scanout;
wire [8:0] user_incr_addr_in;
wire [8:0] user_incr_addr;
wire user_data_mode_reg_scanin;
wire user_data_mode_reg_scanout;
wire user_data_mode_in;
wire user_data_mode;
wire user_data_reg_scanin;
wire user_data_reg_scanout;
wire [7:0] user_data_in;
wire [7:0] user_data;
wire user_cmpselinc_hold_reg_scanin;
wire user_cmpselinc_hold_reg_scanout;
wire user_cmpselinc_hold_in;
wire user_cmpselinc_hold;
wire user_cmpsel_reg_scanin;
wire user_cmpsel_reg_scanout;
wire [2:0] user_cmpsel_in;
wire [2:0] user_cmpsel;
wire user_loop_mode_reg_scanin;
wire user_loop_mode_reg_scanout;
wire user_loop_mode_in;
wire user_loop_mode;
wire ten_n_mode_reg_scanin;
wire ten_n_mode_reg_scanout;
wire ten_n_mode_in;
wire ten_n_mode;
wire user_cam_mode_reg_scanin;
wire user_cam_mode_reg_scanout;
wire user_cam_mode_in;
wire user_cam_mode;
wire user_cam_select_reg_scanin;
wire user_cam_select_reg_scanout;
wire [1:0] user_cam_sel_in;
wire [1:0] user_cam_sel;
wire user_cam_test_select_reg_scanin;
wire user_cam_test_select_reg_scanout;
wire [3:0] user_cam_test_sel_in;
wire [3:0] user_cam_test_sel;
wire user_bisi_wr_mode_reg_scanin;
wire user_bisi_wr_mode_reg_scanout;
wire user_bisi_wr_mode_in;
wire user_bisi_wr_mode;
wire user_bisi_rd_mode_reg_scanin;
wire user_bisi_rd_mode_reg_scanout;
wire user_bisi_rd_mode_in;
wire user_bisi_rd_mode;
wire mb_user_data_mode;
wire user_mode;
wire mb_user_addr_mode;
wire mb_user_cmpselinc_hold;
wire mb_ten_n_mode;
wire mb_user_loop_mode;
wire mb_user_cam_mode;
wire mb_user_ram_mode;
wire mb_user_bisi_wr_mode;
wire bisi_mode;
wire mb_user_bisi_rd_mode;
wire mb_user_bisi_rw_mode;
wire mb_default_bisi;
wire input_signals_reg_scanin;
wire input_signals_reg_scanout;
wire mb_enable_reg_scanin;
wire mb_enable_reg_scanout;
wire mb_enable;
wire mb_enable_out;
wire start;
wire config_reg_scanin;
wire config_reg_scanout;
wire [1:0] config_in;
wire [1:0] config_out;
wire start_transition;
wire end_transition;
wire reset_engine;
wire loop_again;
wire run;
wire loop_again_reg_scanin;
wire loop_again_reg_scanout;
wire stop_engine_l;
wire stop_engine_l_q;
wire cam_array_0;
wire [1:0] cam_sel;
wire cambist_d4;
wire run3;
wire cam_array_1;
wire cam_array_2;
wire cam_clear;
wire last_cam;
wire cambist;
wire cntl_msb;
wire cambist_delay_reg_scanin;
wire cambist_delay_reg_scanout;
wire cambist_d1;
wire cambist_d2;
wire cambist_d3;
wire cam_cntl_reg_scanin;
wire cam_cntl_reg_scanout;
wire [26:0] cam_in;
wire [26:0] cam_out;
wire cam_shift_reg_scanin;
wire cam_shift_reg_scanout;
wire cam_shift_val;
wire cam_shift;
wire cam_msb;
wire [1:0] cam_array_sel;
wire [3:0] cam_ctest;
wire sel_ctest_pass;
wire [2:0] cam_cseq;
wire sel_cseq_pass;
wire [14:0] cam_raw_addr;
wire ctest13;
wire cseq1;
wire ctest06;
wire cseq0;
wire ctest08;
wire ctest10;
wire [6:0] tlb_mhit_addr1;
wire [6:0] tlb_mhit_addr2;
wire tlb_same_addr;
wire mhit_begin;
wire [2:0] stb_mhit_addr1;
wire [2:0] stb_mhit_addr2;
wire stb_same_addr;
wire stb_cam_mhit_test;
wire [6:0] cam_addr;
wire crw0;
wire [1:0] cam_crw;
wire sel_crw_pass;
wire [2:0] cseq;
wire cseq2;
wire cseq3;
wire cseq4;
wire [1:0] crw;
wire crw1;
wire crw2;
wire crw3;
wire [6:0] tlb_addr;
wire [6:0] tlb_stb_addr;
wire stb_cam_pwk1_test;
wire cam_wr_en;
wire tlb_cam_gen_test;
wire tlb_cam_dmap_test;
wire tlb_cam_dmap2_test;
wire tlb_cam_walk1_test;
wire tlb_cam_rpwr_test;
wire tlb_cam_mhit_test;
wire stb_cam_gen_test;
wire ctest09;
wire stb_cam_bwk1_test;
wire stb_cam_bwk2_test;
wire cam_en_pre;
wire cam_zero;
wire end_shift;
wire dmap_en;
wire cam_rd_en;
wire tlb_rpwr_en;
wire tlb_dis_clr_bit;
wire mbist_dis_clr_ubit;
wire array_04;
wire array_08;
wire cam_en_reg_scanin;
wire cam_en_reg_scanout;
wire cam_en;
wire dmap_all;
wire dmap_real;
wire ctest07;
wire dmap_cntx;
wire dmap_page;
wire dmap_on;
wire [1:0] mbist_demap_type;
wire mbist_dtb_demap_en;
wire mbist_itb_demap_en;
wire mbist_stb_cam_en_pre;
wire mbist_dtb_cam_en_pre;
wire mbist_itb_cam_en_pre;
wire ctest00;
wire [3:0] ctest;
wire ctest01;
wire ctest02;
wire ctest03;
wire ctest04;
wire ctest05;
wire ctest11;
wire ctest12;
wire tlb;
wire stb;
wire cam_walk1;
wire mbist_ptag_data;
wire ptag_data;
wire [7:0] stb_data;
wire [7:0] walk1data;
wire [7:0] cam_data;
wire [7:0] tlb_data;
wire stb_cam_en;
wire stb_hit_cmp;
wire stb_hit_cmp_mhit_l;
wire exp_stb_cam_hit;
wire [2:0] exp_stb_hit_ptr;
wire exp_stb_mhit;
wire exp_stb_ld_partial_raw;
wire stb_hit_cmp_delay_scanin;
wire stb_hit_cmp_delay_scanout;
wire stb_hit_cmp_d1;
wire stb_hit_cmp_d2;
wire stb_hit_cmp_d3;
wire stb_hit_cmp_mhit_l_delay_scanin;
wire stb_hit_cmp_mhit_l_delay_scanout;
wire stb_hit_cmp_mhit_l_d1;
wire stb_hit_cmp_mhit_l_d2;
wire stb_hit_cmp_mhit_l_d3;
wire exp_stb_cam_hit_delay_scanin;
wire exp_stb_cam_hit_delay_scanout;
wire exp_stb_cam_hit_d1;
wire exp_stb_cam_hit_d2;
wire exp_stb_cam_hit_d3;
wire exp_stb_hit_ptr_delay_scanin;
wire exp_stb_hit_ptr_delay_scanout;
wire [2:0] exp_stb_hit_ptr_d1;
wire [2:0] exp_stb_hit_ptr_d2;
wire [2:0] exp_stb_hit_ptr_d3;
wire exp_stb_mhit_delay_scanin;
wire exp_stb_mhit_delay_scanout;
wire exp_stb_mhit_d1;
wire exp_stb_mhit_d2;
wire exp_stb_mhit_d3;
wire exp_stb_ld_partial_raw_delay_scanin;
wire exp_stb_ld_partial_raw_delay_scanout;
wire exp_stb_ld_partial_raw_d1;
wire exp_stb_ld_partial_raw_d2;
wire exp_stb_ld_partial_raw_d3;
wire stb_cam_hit_pass;
wire stb_hit_ptr_pass;
wire stb_mhit_pass;
wire stb_ld_partial_raw_pass;
wire cbist_stb_cam_fail;
wire cam_array_2_d3;
wire tlb_cam_en;
wire tlb_hit_cmp;
wire cam_valid_cmp;
wire cam_used_cmp;
wire tlb_cntx0_cmp;
wire exp_tlb_mhit;
wire tlb_data_cmp;
wire exp_cam_hit;
wire exp_valid;
wire exp_used;
wire exp_data_cmp;
wire exp_cntx0_hit;
wire cam_array_0_delay_scanin;
wire cam_array_0_delay_scanout;
wire cam_array_0_d1;
wire cam_array_0_d2;
wire cam_array_0_d3;
wire cam_array_0_d4;
wire cam_array_1_delay_scanin;
wire cam_array_1_delay_scanout;
wire cam_array_1_d1;
wire cam_array_1_d2;
wire cam_array_1_d3;
wire cam_array_1_d4;
wire cam_array_1_d5;
wire cam_array_2_delay_scanin;
wire cam_array_2_delay_scanout;
wire cam_array_2_d1;
wire cam_array_2_d2;
wire cam_hit_cmp_delay_scanin;
wire cam_hit_cmp_delay_scanout;
wire tlb_hit_cmp_d1;
wire tlb_hit_cmp_d2;
wire tlb_hit_cmp_d3;
wire tlb_hit_cmp_d4;
wire tlb_hit_cmp_d5;
wire tlb_hit_cmp_d6;
wire data_cmp_delay_scanin;
wire data_cmp_delay_scanout;
wire tlb_data_cmp_d1;
wire tlb_data_cmp_d2;
wire tlb_data_cmp_d3;
wire tlb_data_cmp_d4;
wire tlb_data_cmp_d5;
wire cam_valid_cmp_delay_scanin;
wire cam_valid_cmp_delay_scanout;
wire cam_valid_cmp_d1;
wire cam_valid_cmp_d2;
wire cam_valid_cmp_d3;
wire cam_valid_cmp_d4;
wire cam_valid_cmp_d5;
wire cam_used_cmp_delay_scanin;
wire cam_used_cmp_delay_scanout;
wire cam_used_cmp_d1;
wire cam_used_cmp_d2;
wire cam_used_cmp_d3;
wire cam_used_cmp_d4;
wire cam_used_cmp_d5;
wire exp_data_cmp_delay_scanin;
wire exp_data_cmp_delay_scanout;
wire exp_data_cmp_d1;
wire exp_data_cmp_d2;
wire exp_data_cmp_d3;
wire exp_data_cmp_d4;
wire exp_data_cmp_d5;
wire exp_valid_delay_scanin;
wire exp_valid_delay_scanout;
wire exp_valid_d1;
wire exp_valid_d2;
wire exp_valid_d3;
wire exp_valid_d4;
wire exp_valid_d5;
wire exp_used_delay_scanin;
wire exp_used_delay_scanout;
wire exp_used_d1;
wire exp_used_d2;
wire exp_used_d3;
wire exp_used_d4;
wire exp_used_d5;
wire tlb_cntx0_cmp_delay_scanin;
wire tlb_cntx0_cmp_delay_scanout;
wire tlb_cntx0_cmp_d1;
wire tlb_cntx0_cmp_d2;
wire tlb_cntx0_cmp_d3;
wire tlb_cntx0_cmp_d4;
wire tlb_cntx0_cmp_d5;
wire tlb_cntx0_cmp_d6;
wire exp_cam_hit_delay_scanin;
wire exp_cam_hit_delay_scanout;
wire exp_cam_hit_d1;
wire exp_cam_hit_d2;
wire exp_cam_hit_d3;
wire exp_cam_hit_d4;
wire exp_cam_hit_d5;
wire exp_cam_hit_d6;
wire exp_cntx0_hit_delay_scanin;
wire exp_cntx0_hit_delay_scanout;
wire exp_cntx0_hit_d1;
wire exp_cntx0_hit_d2;
wire exp_cntx0_hit_d3;
wire exp_cntx0_hit_d4;
wire exp_cntx0_hit_d5;
wire exp_cntx0_hit_d6;
wire exp_mhit_delay_scanin;
wire exp_mhit_delay_scanout;
wire exp_tlb_mhit_d1;
wire exp_tlb_mhit_d2;
wire exp_tlb_mhit_d3;
wire exp_tlb_mhit_d4;
wire exp_tlb_mhit_d5;
wire exp_tlb_mhit_d6;
wire dtlb_cam_hit_pass;
wire dtlb_cntx0_hit_pass;
wire dtlb_mhit_pass;
wire dtlb_valid_pass;
wire dtlb_used_pass;
wire dtlb_data_cmp_pass;
wire cbist_dtlb_cam_fail;
wire itlb_cam_hit_pass;
wire itlb_cntx0_hit_pass;
wire itlb_mhit_pass;
wire itlb_valid_pass;
wire itlb_used_pass;
wire itlb_data_cmp_pass;
wire cbist_itlb_cam_fail;
wire [26:0] qual_cam;
wire tlb_cam_intf_out_scanin;
wire tlb_cam_intf_out_scanout;
wire mbist_cambist_run;
wire mbist_cambist_shift;
wire mbist_init_to_zero;
wire mbist_repl_write;
wire cntl_reg_scanin;
wire cntl_reg_scanout;
wire [34:0] cntl_in;
wire [34:0] cntl_out;
wire [15:0] cntl_algr;
wire [15:0] next_algr;
wire sel_nextaddr_reset;
wire sel_nextaddr_restart;
wire overflow;
wire sel_nextaddr_incred;
wire cout_rw;
wire sel_nextaddr_same;
wire [8:0] start_addr;
wire [8:0] restart_addr;
wire [8:0] incred_addr;
wire [8:0] cntl_addr;
wire [2:0] cntl_rw;
wire [2:0] next_rw;
wire cntl_bisi;
wire [3:0] cntl_array_sel;
wire last_array;
wire [2:0] cntl_cmp_sel;
wire sel_cmp_pass;
wire [1:0] cntl_data_sel;
wire cntl_addr_mix;
wire addr_mix;
wire [3:0] cntl_march_element;
wire sel_march_1_pass;
wire cout_addr;
wire upaddr;
wire march_0;
wire march_1;
wire march_2;
wire march_6;
wire march_7;
wire [3:0] march_element_pre;
wire march_pre_0;
wire march_pre_1;
wire march_pre_2;
wire march_pre_6;
wire march_pre_7;
wire upaddr_pre;
wire [8:0] incr_addr;
wire [8:0] stop_addr;
wire sel_rw_pass;
wire one_cycle_march;
wire march_5;
wire five_cycle_march;
wire march_8;
wire two_cycle_march;
wire mem_wr_pbi;
wire march_3;
wire march_4;
wire rw_1;
wire rw_0;
wire rw_4;
wire mem_wr;
wire bisi_wr_mode;
wire bisi_rd_mode;
wire mem_rd_pbi;
wire mem_rd;
wire [8:0] adj_addr;
wire rw_3;
wire [8:0] mem_addr1;
wire true_data_l;
wire rw_2;
wire true_data;
wire [7:0] data_pat_sel;
wire [7:0] mem_data;
wire array_01;
wire array_02;
wire array_03;
wire array_05;
wire array_06;
wire array_07;
wire array_09;
wire array_10;
wire array_11;
wire array_12;
wire [8:0] mem_addr_mix0;
wire [8:0] mem_addr_mix1;
wire [8:0] mem_addr;
wire [3:0] array_sel;
wire cmp_0;
wire [2:0] cmp_sel;
wire cmp_1;
wire cmp_2;
wire cmp_3;
wire cmp_7;
wire [3:0] march_element;
wire [2:0] rw;
wire [1:0] cam_sel_cntl_out;
wire [3:0] ctest_cntl_out;
wire ctest_reg_scanin;
wire ctest_reg_scanout;
wire [3:0] ctest_out;
wire [2:0] cseq_cntl_out;
wire cseq_reg_scanin;
wire cseq_reg_scanout;
wire [2:0] cseq_out;
wire [3:0] array_sel_cntl_out;
wire array_sel_reg_scanin;
wire array_sel_reg_scanout;
wire [3:0] array_sel_out;
wire [2:0] cmp_sel_cntl_out;
wire cmp_sel_reg_scanin;
wire cmp_sel_reg_scanout;
wire [2:0] cmp_sel_out;
wire [3:0] march_element_cntl_out;
wire marche_element_reg_scanin;
wire marche_element_reg_scanout;
wire [3:0] march_element_out;
wire sel_rw_1_pass;
wire sel_rw_2_pass;
wire sel_rw_5_pass;
wire [2:0] mb_cmp_sel;
wire [8:0] mb_addr;
wire [7:0] mb_write_data;
wire mb_array_01_rd;
wire mb_array_02_rd;
wire mb_array_03_rd;
wire mb_array_04_rd;
wire mb_array_05_rd;
wire mb_array_06_rd;
wire mb_array_07_rd;
wire mb_array_08_rd;
wire mb_array_09_rd;
wire mb_array_10_rd;
wire mb_array_11_rd;
wire mb_array_12_rd;
wire mb_array_01_wr;
wire mb_array_02_wr;
wire mb_array_03_wr;
wire mb_array_04_wr;
wire mb_array_05_wr;
wire mb_array_06_wr;
wire mb_array_07_wr;
wire mb_array_08_wr;
wire mb_array_09_wr;
wire mb_array_10_wr;
wire mb_array_11_wr;
wire mb_array_12_wr;
wire mb_run;
wire msb_latch_scanin;
wire msb_latch_scanout;
wire msb_in;
wire msb_out;
wire mb_done;
wire [4:0] done_delay;
wire run3_transition_reg_scanin;
wire run3_transition_reg_scanout;
wire run3_out;
wire run3_transition;
wire done_delay_reg_scanin;
wire done_delay_reg_scanout;
wire [4:0] done_delay_in;
wire dca_fail;
wire lsu_mbi_dca_fail_sticky;
wire dta_fail;
wire lsu_mbi_dta_fail_sticky;
wire dva_fail;
wire lsu_mbi_dva_fail_sticky;
wire lru_fail;
wire lsu_mbi_lru_fail_sticky;
wire dtb_fail;
wire lsu_mbi_dtb_fail_sticky;
wire stb_cam_fail;
wire lsu_mbi_stb_cam_fail_sticky;
wire stb_ram_fail;
wire lsu_mbi_stb_ram_fail_sticky;
wire cpq_fail;
wire lsu_mbi_cpq_fail_sticky;
wire ict_fail;
wire ftu_mbi_ict_fail_sticky;
wire icd_fail;
wire ftu_mbi_icd_fail_sticky;
wire itb_fail;
wire ftu_mbi_itb_fail_sticky;
wire icv_fail;
wire ftu_mbi_icv_fail_sticky;
wire cbist_itlb_fail;
wire cbist_itlb_cam_fail_sticky;
wire cbist_dtlb_fail;
wire cbist_dtlb_cam_fail_sticky;
wire cbist_stb_fail;
wire cbist_stb_cam_fail_sticky;
wire fail_reg_scanin;
wire fail_reg_scanout;
wire mbist_fail_array;
wire mbist_fail_sticky;
wire valid_fail;
wire mb_fail;
wire out_mb_tcu_done_reg_scanin;
wire out_mb_tcu_done_reg_scanout;
wire mb_done_out;
wire out_mb_tcu_fail_reg_scanin;
wire out_mb_tcu_fail_reg_scanout;
wire mb_fail_out;
wire out_cmp_sel_reg_scanin;
wire out_cmp_sel_reg_scanout;
wire [2:0] mb_cmpsel_out;
wire out_run_mb_arrays_reg_scanin;
wire out_run_mb_arrays_reg_scanout;
wire mb_run_out;
wire out_data_mb_arrays_reg_scanin;
wire out_data_mb_arrays_reg_scanout;
wire [7:0] mb_write_data_out;
wire out_addr_mb_arrays_reg_scanin;
wire out_addr_mb_arrays_reg_scanout;
wire [8:0] mb_addr_out;
wire out_wr_mb_arrays_reg_scanin;
wire out_wr_mb_arrays_reg_scanout;
wire mb_array_01_wr_out;
wire mb_array_02_wr_out;
wire mb_array_03_wr_out;
wire mb_array_04_wr_out;
wire mb_array_05_wr_out;
wire mb_array_06_wr_out;
wire mb_array_07_wr_out;
wire mb_array_08_wr_out;
wire mb_array_09_wr_out;
wire mb_array_10_wr_out;
wire mb_array_11_wr_out;
wire mb_array_12_wr_out;
wire out_rd_mb_arrays_reg_scanin;
wire out_rd_mb_arrays_reg_scanout;
wire mb_array_01_rd_out;
wire mb_array_02_rd_out;
wire mb_array_03_rd_out;
wire mb_array_04_rd_out;
wire mb_array_05_rd_out;
wire mb_array_06_rd_out;
wire mb_array_07_rd_out;
wire mb_array_08_rd_out;
wire mb_array_09_rd_out;
wire mb_array_10_rd_out;
wire mb_array_11_rd_out;
wire mb_array_12_rd_out;
wire merged_fail_scanin;
wire merged_fail_scanout;
wire mb_fail_merged;
wire mb1_fail;
wire mb2_fail;
wire merged_done_scanin;
wire merged_done_scanout;
wire mb_done_merged;
wire mb1_done;
wire mb2_done;
wire mb0_fail;
wire spares_scanin;
wire spares_scanout;


// /////////////////////////////////////////////////////////////////////////////
// Outputs
// /////////////////////////////////////////////////////////////////////////////

   output		scan_out;

   output		mb0_done;
 

   output		mb0_run;
   output [15:0]	mb0_addr;
   output [2:0]		mb0_cmpsel;
   output		mb0_ict_read_en;
   output		mb0_ict_write_en;
   output		mb0_icd_read_en;
   output		mb0_icd_write_en;
   output		mb0_icv_read_en;
   output		mb0_icv_write_en;
   output		mb0_itb_read_en;
   output		mb0_itb_write_en;
   output [7:0]		mb0_write_data;

   output		mb0_dca_read_en;
   output		mb0_dca_write_en;
   output		mb0_dta_read_en;
   output		mb0_dta_write_en;
   output		mb0_dva_read_en;
   output		mb0_dva_write_en;
   output		mb0_lru_read_en;
   output		mb0_lru_write_en;
   output		mb0_dtb_read_en;
   output		mb0_dtb_write_en;
   output		mb0_stb_cam_read_en;
   output		mb0_stb_cam_write_en;
   output		mb0_stb_ram_read_en;
   output		mb0_stb_ram_write_en;
   output		mb0_cpq_read_en;
   output		mb0_cpq_write_en;

   output		mb0_mbist_fail;


   output		mbi_cambist_run;
   output		mbi_cambist_shift;
   output		mbi_dis_clr_ubit;
   output		mbi_init_to_zero;
   output		mbi_dtb_cam_en_pre;
   output		mbi_dtb_demap_en;
   output		mbi_itb_cam_en_pre;
   output		mbi_itb_demap_en;
   output		mbi_repl_write;

   output    [1:0]	mbi_demap_type;

// stb:   
   output		mbi_ptag_data;
   output		mbi_scm_cam_en_pre;

// /////////////////////////////////////////////////////////////////////////////
// Inputs
// /////////////////////////////////////////////////////////////////////////////

   input		l2clk;
   input		scan_in;
   input		tcu_pce_ov;             // scan signals
   input		tcu_clk_stop;
   input		tcu_aclk;
   input		tcu_bclk;
   input		tcu_scan_en;
   input		lsu_misc_pmen;		// Power management enable

   input		mbist_start;
   input		mbist_bisi_mode;
   input		mbist_user_mode;
 		

   input		lsu_mbi_dca_fail;
   input		lsu_mbi_dta_fail;
   input		lsu_mbi_dva_fail;
   input		lsu_mbi_lru_fail;
   input		lsu_mbi_dtb_fail;
   input		lsu_mbi_stb_cam_fail;
   input		lsu_mbi_stb_ram_fail;
   input		lsu_mbi_cpq_fail;
   input 		ftu_mbi_ict_fail;
   input 		ftu_mbi_icd_fail;
   input 		ftu_mbi_itb_fail;
   input 		ftu_mbi_icv_fail;
		

   input		lsu_mbi_tlb_data_cmp;
   input		lsu_mbi_tlb_cam_hit;
   input		lsu_mbi_tlb_cam_mhit;
   input		lsu_mbi_tlb_ctxt0_hit;
   input		lsu_mbi_tlb_valid;
   input		lsu_mbi_tlb_used;

   input		lsu_mbi_scm_hit;
   input		lsu_mbi_scm_mhit;
   input  [2:0]		lsu_mbi_scm_hit_ptr;
   input		lsu_mbi_scm_praw;


   input		ftu_mbi_tlb_data_cmp;
   input		ftu_mbi_tlb_cam_hit;
   input		ftu_mbi_tlb_cam_mhit;
   input		ftu_mbi_tlb_ctxt0_hit;
   input		ftu_mbi_tlb_valid;
   input		ftu_mbi_tlb_used;


   input		mb1_mb0_fail;
   input		mb2_mb0_fail;


   input		mb1_mb0_done;
   input		mb2_mb0_done;

   
// /////////////////////////////////////////////////////////////////////////////
// Scan Renames
// /////////////////////////////////////////////////////////////////////////////

assign pce_ov = tcu_pce_ov;
assign stop   = tcu_clk_stop;
assign siclk  = tcu_aclk;
assign soclk  = tcu_bclk;
assign se = tcu_scan_en;


////////////////////////////////////////////////////////////////////////////////
// Clock header
////////////////////////////////////////////////////////////////////////////////

spc_mb0_ctll1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk 		),
        .l1en   (1'b1		),
        .l1clk  (l1clk		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

spc_mb0_ctlmsff_ctl_macro__width_3 pmen  (
	.scan_in(pmen_scanin),
	.scan_out(pmen_scanout),
	.l1clk    ( l1clk					),	// Must be connected to a free running clock
	.din      ({mbist_start, ~lsu_misc_pmen , 1'b0}		),
	.dout     ({start_in   ,  misc_pmen_    , pmem_unused}	),
  .siclk(siclk),
  .soclk(soclk));


assign clock_enable	= start_in | mb0_done | mb0_run | mb0_mbist_fail | misc_pmen_;

spc_mb0_ctll1clkhdr_ctl_macro clkgen_pm1 (
        .l2clk  (l2clk 		),
        .l1en   (clock_enable	),
        .l1clk  (l1clk_pm1	),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


// /////////////////////////////////////////////////////////////////////////////
//
// user mode resgisters   
// MBIST PGM Control Register
//
// /////////////////////////////////////////////////////////////////////////////
// /////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////
// user control registers
//                         size
// -  user_array            4
// -  user_addr_mode        1
// -  user_start_addr      15
// -  user_stop_addr       15
// -  user_inc_addr        15
// -  user_data_mode        1
// -  user_data             8
// -  user_cmpselinc_mode   1
// -  user_cmpselinc        3
// -  user_loop_mode        1
// -  user_cam_select       2
// -  user_cam_test_sel     4
////////////////////////////////////////////////////////////////////////////////


   spc_mb0_ctlmsff_ctl_macro__width_4 array_usr_reg  (
                  .scan_in(array_usr_reg_scanin),
                  .scan_out(array_usr_reg_scanout),
                  .l1clk    ( l1clk_pm1	           ),
  	          .din      ( user_array_in[3:0]   ),
  		  .dout     ( user_array[3:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_array_in[3:0]=user_array[3:0];


   // user address mode

   spc_mb0_ctlmsff_ctl_macro__width_1 user_addr_mode_reg  (
                  .scan_in(user_addr_mode_reg_scanin),
                  .scan_out(user_addr_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	            ),
  	          .din      ( user_addr_mode_in     ),
  		  .dout     ( user_addr_mode        ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_addr_mode_in=user_addr_mode;
   

   //  user start address
   
  spc_mb0_ctlmsff_ctl_macro__width_9 user_start_addr_reg  (
                 .scan_in(user_start_addr_reg_scanin),
                 .scan_out(user_start_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1	               ),
                 .din      ( user_start_addr_in[8:0]   ),
                 .dout     ( user_start_addr[8:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_start_addr_in[8:0]=user_start_addr[8:0];

   //  user stop address
   
  spc_mb0_ctlmsff_ctl_macro__width_9 user_stop_addr_reg  (
                 .scan_in(user_stop_addr_reg_scanin),
                 .scan_out(user_stop_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1	              ),
                 .din      ( user_stop_addr_in[8:0]   ),
                 .dout     ( user_stop_addr[8:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_stop_addr_in[8:0]=user_stop_addr[8:0];
   

  //  user increment address
   
  spc_mb0_ctlmsff_ctl_macro__width_9 user_incr_addr_reg  (
                 .scan_in(user_incr_addr_reg_scanin),
                 .scan_out(user_incr_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1	              ),
                 .din      ( user_incr_addr_in[8:0]   ),
                 .dout     ( user_incr_addr[8:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_incr_addr_in[8:0]=user_incr_addr[8:0];

   // user data mode

   spc_mb0_ctlmsff_ctl_macro__width_1 user_data_mode_reg  (
                  .scan_in(user_data_mode_reg_scanin),
                  .scan_out(user_data_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	            ),
  	          .din      ( user_data_mode_in     ),
   		  .dout     ( user_data_mode        ),
  .siclk(siclk),
  .soclk(soclk));

							 
   assign user_data_mode_in=user_data_mode;

   //  user data select
   
   spc_mb0_ctlmsff_ctl_macro__width_8 user_data_reg  (
                 .scan_in(user_data_reg_scanin),
                 .scan_out(user_data_reg_scanout),
                 .l1clk    ( l1clk_pm1	         ),
                 .din      ( user_data_in[7:0]   ),
                 .dout     ( user_data[7:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_data_in[7:0]    =    user_data[7:0];

   // user cmp sel inc
   // if its one, user need to program the cmpselinc register
   // otherwise it will loop all cmpsel

   spc_mb0_ctlmsff_ctl_macro__width_1 user_cmpselinc_hold_reg  (
                  .scan_in(user_cmpselinc_hold_reg_scanin),
                  .scan_out(user_cmpselinc_hold_reg_scanout),
                  .l1clk    ( l1clk_pm1	               ),
  	          .din      ( user_cmpselinc_hold_in   ),
   		  .dout     ( user_cmpselinc_hold      ),
  .siclk(siclk),
  .soclk(soclk));

							 
   assign user_cmpselinc_hold_in=user_cmpselinc_hold;


   // user cmp sel reg
   
   spc_mb0_ctlmsff_ctl_macro__width_3 user_cmpsel_reg  (
                  .scan_in(user_cmpsel_reg_scanin),
                  .scan_out(user_cmpsel_reg_scanout),
                  .l1clk    ( l1clk_pm1	            ),
  	          .din      ( user_cmpsel_in[2:0]   ),
  		  .dout     ( user_cmpsel[2:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_cmpsel_in[2:0]=user_cmpsel[2:0];


   // user loop mode

   spc_mb0_ctlmsff_ctl_macro__width_1 user_loop_mode_reg  (
                  .scan_in(user_loop_mode_reg_scanin),
                  .scan_out(user_loop_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	            ),
  	          .din      ( user_loop_mode_in     ),
  		  .dout     ( user_loop_mode        ),
  .siclk(siclk),
  .soclk(soclk));

  
   assign user_loop_mode_in=user_loop_mode;

   
   // 10N Algorithm for bit mapping

   spc_mb0_ctlmsff_ctl_macro__width_1 ten_n_mode_reg  (
                  .scan_in(ten_n_mode_reg_scanin),
                  .scan_out(ten_n_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	        ),
  	          .din      ( ten_n_mode_in     ),
  		  .dout     ( ten_n_mode        ),
  .siclk(siclk),
  .soclk(soclk));

  
   assign ten_n_mode_in=ten_n_mode;


   // cambist: user array select

   spc_mb0_ctlmsff_ctl_macro__width_1 user_cam_mode_reg  (
                  .scan_in(user_cam_mode_reg_scanin),
                  .scan_out(user_cam_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	         ),
  	          .din      ( user_cam_mode_in   ),
  		  .dout     ( user_cam_mode      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_cam_mode_in=user_cam_mode;


   spc_mb0_ctlmsff_ctl_macro__width_2 user_cam_select_reg  (
                  .scan_in(user_cam_select_reg_scanin),
                  .scan_out(user_cam_select_reg_scanout),
                  .l1clk    ( l1clk_pm1	             ),
  	          .din      ( user_cam_sel_in[1:0]   ),
  		  .dout     ( user_cam_sel[1:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_cam_sel_in[1:0]=user_cam_sel[1:0];


   spc_mb0_ctlmsff_ctl_macro__width_4 user_cam_test_select_reg  (
                  .scan_in(user_cam_test_select_reg_scanin),
                  .scan_out(user_cam_test_select_reg_scanout),
                  .l1clk    ( l1clk_pm1	                  ),
  	          .din      ( user_cam_test_sel_in[3:0]   ),
  		  .dout     ( user_cam_test_sel[3:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_cam_test_sel_in[3:0]=user_cam_test_sel[3:0];


   spc_mb0_ctlmsff_ctl_macro__width_1 user_bisi_wr_mode_reg  (
                  .scan_in(user_bisi_wr_mode_reg_scanin),
                  .scan_out(user_bisi_wr_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                  ),
  	          .din      ( user_bisi_wr_mode_in   ),
  		  .dout     ( user_bisi_wr_mode      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_bisi_wr_mode_in=user_bisi_wr_mode;

   spc_mb0_ctlmsff_ctl_macro__width_1 user_bisi_rd_mode_reg  (
                  .scan_in(user_bisi_rd_mode_reg_scanin),
                  .scan_out(user_bisi_rd_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                  ),
  	          .din      ( user_bisi_rd_mode_in   ),
  		  .dout     ( user_bisi_rd_mode      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_bisi_rd_mode_in=user_bisi_rd_mode;


   assign mb_user_data_mode = user_mode & user_data_mode;
   assign mb_user_addr_mode = user_mode & user_addr_mode;
   assign mb_user_cmpselinc_hold = user_mode & user_cmpselinc_hold;
   assign mb_ten_n_mode     = user_mode & ten_n_mode;
   assign mb_user_loop_mode      = user_mode & user_loop_mode;
   assign mb_user_cam_mode      = user_mode & user_cam_mode;
   assign mb_user_ram_mode = user_mode & ~user_cam_mode;


   assign mb_user_bisi_wr_mode   = user_mode & user_bisi_wr_mode & bisi_mode;
   assign mb_user_bisi_rd_mode   = user_mode & user_bisi_rd_mode & bisi_mode;

   assign mb_user_bisi_rw_mode   = ((~user_bisi_wr_mode & ~user_bisi_rd_mode) | (user_bisi_wr_mode & user_bisi_rd_mode)) & bisi_mode;

   assign mb_default_bisi = bisi_mode & ~user_mode;


// /////////////////////////////////////////////////////////////////////////////
//
// MBIST Config Register
//
// /////////////////////////////////////////////////////////////////////////////
//
// A low to high transition on mbist_start will reset and start the engine.  
// mbist_start must remain active high for the duration of MBIST.  
// If mbist_start deasserts the engine will stop but not reset.
// Once MBIST has completed mb0_done will assert and the fail status
// signals will be valid.  
// To run MBIST again the mbist_start signal must transition low then high.
//
// Loop on Address will disable the address mix function.
//
// /////////////////////////////////////////////////////////////////////////////

  // flop incoming signals:

  spc_mb0_ctlmsff_ctl_macro__width_2 input_signals_reg  (
                .scan_in(input_signals_reg_scanin),
                .scan_out(input_signals_reg_scanout),
                .l1clk   ( l1clk	                                 ),
               .din      ( {mbist_bisi_mode,mbist_user_mode} ),
               .dout     ( {bisi_mode      ,user_mode}       ),
  .siclk(siclk),
  .soclk(soclk));
  

  // default   : mb_enable=0
  // bisi      : mb_enable=0
  // user_mode : mb_enable=depend on programmed value

  spc_mb0_ctlmsff_ctl_macro__width_1 mb_enable_reg  (
               .scan_in(mb_enable_reg_scanin),
               .scan_out(mb_enable_reg_scanout),
               .l1clk    ( l1clk_pm1	       ),
               .din      ( mb_enable           ),
               .dout     ( mb_enable_out       ),
  .siclk(siclk),
  .soclk(soclk));

//assign mb_enable = user_mode ? mb_enable_out : 1'b0;
  assign mb_enable = mb_enable_out;

 
  assign start = user_mode ? (mb_enable_out & start_in) :
                              start_in;


  spc_mb0_ctlmsff_ctl_macro__width_2 config_reg  (
               .scan_in(config_reg_scanin),
               .scan_out(config_reg_scanout),
               .l1clk    ( l1clk_pm1	        ),
               .din      ( config_in[1:0]       ),
               .dout     ( config_out[1:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   
  assign config_in[0]        =    start;
  assign config_in[1]        =    config_out[0];
  assign start_transition    =    config_out[0] & ~config_out[1];
  assign end_transition      =   ~config_out[0] &  config_out[1];
  assign reset_engine        =    start_transition | loop_again  | end_transition;
  assign run                 =    config_out[1] ;


  spc_mb0_ctlmsff_ctl_macro__width_1 loop_again_reg  (
               .scan_in(loop_again_reg_scanin),
               .scan_out(loop_again_reg_scanout),
               .l1clk    ( l1clk_pm1	    ),
               .din      ( stop_engine_l    ),
               .dout     ( stop_engine_l_q  ),
  .siclk(siclk),
  .soclk(soclk));


assign loop_again=mb_user_loop_mode ? stop_engine_l & ~stop_engine_l_q:  1'b0;


// config


   // cam selection

   assign cam_array_0   = (cam_sel[1:0]==2'b00) & (cambist_d4 & run3);
   assign cam_array_1   = (cam_sel[1:0]==2'b01) & (cambist_d4 & run3);
   assign cam_array_2   = (cam_sel[1:0]==2'b10) & (cambist_d4 & run3);
   assign cam_clear     = (cam_sel[1:0]==2'b11) & (cambist_d4 & run3);

   assign last_cam = cam_clear;

  //  default   mode   :  cambist = cntl_msb
  //  mb_user_cam_mode :  cambist = 1
  //  mbist_bisi_mode  :  cambist = 0


  assign cambist=((mb_user_cam_mode | (cntl_msb & ~bisi_mode)) & run3 );

   
   spc_mb0_ctlmsff_ctl_macro__width_4 cambist_delay_reg  (
                  .scan_in(cambist_delay_reg_scanin),
                  .scan_out(cambist_delay_reg_scanout),
                  .l1clk    ( l1clk_pm1	         ),
  	          .din      ( {cambist,cambist_d1,cambist_d2,cambist_d3}  ),
  		  .dout     ( {cambist_d1,cambist_d2,cambist_d3,cambist_d4}  ),
  .siclk(siclk),
  .soclk(soclk));


// /////////////////////////////////////////////////////////////////////////////
//
// CAM BIST:
//
// /////////////////////////////////////////////////////////////////////////////


   spc_mb0_ctlmsff_ctl_macro__width_27 cam_cntl_reg  (
                 .scan_in(cam_cntl_reg_scanin),
                 .scan_out(cam_cntl_reg_scanout),
                 .l1clk    ( l1clk_pm1	        ),
                 .din      ( cam_in[26:0]       ),
                 .dout     ( cam_out[26:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_1 cam_shift_reg  (
                 .scan_in(cam_shift_reg_scanin),
                 .scan_out(cam_shift_reg_scanout),
                 .l1clk    ( l1clk_pm1	        ),
                 .din      ( cam_shift_val      ),
                 .dout     ( cam_shift          ),
  .siclk(siclk),
  .soclk(soclk));


   // stbcam

   // 
  

   // tlb_op
   //              000   - tlb cam
   //              001   - demap page
   //              010   - demap real
   //              011   - demap context
   //              100   - demap all
   //              101   - replacement write
   //              110   - multiple hit
   //              111   - used bit 
   //              
   
   
   // clear 0       0    - clear
   // ^(W1CmRdW0)   1    - test
   // work


   // test0:
   //
   // ^(W0);
   // ^(W1C1RvW0);
   // seq0
   //   crw0
   // seq1
   //   crw0
   //   crw1
   //   crw2
   //   crw2

   assign cam_msb                 =     ~start_in ? 1'b0 : cam_out[26];    //

   assign cam_array_sel[1:0]        =   (user_mode | last_cam  ) ? 2'b11:
                                                                    cam_out[25:24];    // 2 bits

   assign cam_ctest[3:0]             =   sel_ctest_pass | user_mode? 4'b1111:
                                                     cam_out[23:20];    //   


   assign cam_cseq[2:0]                =   sel_cseq_pass  ? 3'b111 :  cam_out[19:17];   


//   assign stb_bwk2_cseq3 = cam_array_0 & stb_cam_bwk2_test & cseq3 ;
//   assign stb_pwk1_cseq3 = cam_array_0 & (~stb_cam_pwk1_test & cseq3);
//   assign stb_mhit_cseq3 = cam_array_0 & (stb_cam_mhit_test & cseq3);
//   assign dtb_mhit_cseq3 = cam_array_0 & (tlb_cam_mhit_test & cseq3);
//   assign itb_mhit_cseq3 = cam_array_2 & (tlb_cam_mhit_test & cseq3);

   assign cam_raw_addr[14:0] =  (cam_array_0 & ctest13 & cseq1) ? { 1'b1, cam_out[15:9],cam_out[8:2]}:
                                (cam_array_1 & ctest13 & cseq1) ? { 2'b11,cam_out[14:9],1'b1,cam_out[7:2]}:
//                                (cam_array_2 & ctest10 & cseq1) ? { 2'b11,cam_out[14:9],1'b1,cam_out[7:2]}:
                                 cam_array_0 | cam_clear          ? { 8'b1111_1111   ,cam_out[8:2]}:
                                (cam_array_2 & ctest06 & ~cseq0)  ? { 6'b1111_11,   cam_out[10:2]}:
                                (cam_array_2 & ctest08 & ~cseq0)  ? { 6'b1111_11,   cam_out[10:2]}:
                                (cam_array_2 & ctest10 & ~cseq0)  ? { 6'b1111_11,   cam_out[10:2]}:
                                (cam_array_1 | cam_array_2)       ? { 9'b1111_1111_1 ,cam_out[7:2]}:
                                                                   cam_out[16:2];

//   assign cam_raw_addr[14:0] =  stb_bwk2_cseq3    ?  { 9'b1111_1111_1 ,cam_out[7:5],3'b111}:  
//                                stb_mhit_cseq3    ?  { 5'b1111_1      ,cam_out[11:2]}:
//                                stb_pwk1_cseq3    ?  { 9'b1111_1111_1,cam_out[7:2]}:
// 	                            dtb_mhit_cseq3    ?                    cam_out[16:2]:
// 	                            itb_mhit_cseq3    ?  {1'b1,cam_out[15:9],1'b1,cam_out[7:2]}:
//                                  cam_array_1    ?  { 9'b1111_1111_1,cam_out[7:2]}:     
//                                  cam_array_0    ?  { 8'b1111_1111 ,cam_out[8:2]}:

// 	                                                                   cam_out[16:2];

   // tlb mhit addressing
   assign tlb_mhit_addr1[6:0]=cam_raw_addr[13:7];
   assign tlb_mhit_addr2[6:0]=cam_raw_addr[6:0];
   assign tlb_same_addr=tlb_mhit_addr1[6:0]==tlb_mhit_addr2[6:0];

   assign mhit_begin= (cseq1 & ctest13 & ((cam_array_0 & ~(|tlb_mhit_addr2[6:0]) | (cam_array_1 & ~(|tlb_mhit_addr2[5:0]))))) |
                      (cseq1 & ctest10 & (cam_array_2 & ~(|tlb_mhit_addr2[2:0]))) ;

   // stb mhit addressing

   assign stb_mhit_addr1[2:0]=cam_raw_addr[5:3];
   assign stb_mhit_addr2[2:0]=cam_raw_addr[2:0];
//   assign stb_mhit_clear=cam_raw_addr[3];
   assign stb_same_addr=(stb_mhit_addr1[2:0] == stb_mhit_addr2[2:0]) & stb_cam_mhit_test & cseq1;


   assign cam_addr[6:0] = (cam_array_2 & mhit_begin & crw0)               ? {cam_raw_addr[6:3],stb_mhit_addr1[2:0]} :
                          ((cam_array_1|cam_array_0) & mhit_begin & crw0) ? tlb_mhit_addr1[6:0] : 
                          (cam_array_2)                                   ? {1'b0,cam_raw_addr[5:0]} :
                                                                            cam_raw_addr[6:0];


   // read write control:


   assign cam_crw[1:0]               =  sel_crw_pass ?  2'b11 : cam_out[1:0];    // read write control


   // decoding of control signals

   assign cseq0 = cseq[2:0]==3'b000;
   assign cseq1 = cseq[2:0]==3'b001;
   assign cseq2 = cseq[2:0]==3'b010;
   assign cseq3 = cseq[2:0]==3'b011;
   assign cseq4 = cseq[2:0]==3'b100;


   assign crw0 = ~( crw[1] |  crw[0]);
   assign crw1 = ~( crw[1] | ~crw[0]);
   assign crw2 = ~(~crw[1] |  crw[0]);
   assign crw3 = ~(~crw[1] | ~crw[0]);
   

   assign tlb_addr[6:0]= stb_cam_mhit_test & cseq1 ? {1'b0,cam_raw_addr[8:6],cam_addr[2:0]} :
                                                     cam_addr[6:0];

   assign tlb_stb_addr[6:0]= (stb_cam_pwk1_test & cseq1) ? {1'b0,cam_raw_addr[8:6],3'b000} : tlb_addr[6:0];

   assign cam_wr_en  =  (tlb_cam_gen_test & cseq0 & crw0) |
                        (tlb_cam_gen_test & cseq1 & (crw0 | crw3)) |
                        (tlb_cam_dmap_test & cseq0 & crw0 ) |
                        (tlb_cam_dmap2_test & cseq0 & crw0 ) |
                        (tlb_cam_walk1_test & cseq0 & crw0 ) |
                        (tlb_cam_rpwr_test & cseq0 & crw0 ) |
                        (tlb_cam_rpwr_test & cseq1 & crw0 ) |
                        (tlb_cam_rpwr_test & cseq3 & crw0 ) |
                        (tlb_cam_rpwr_test & cseq4 & (crw0 | crw2) ) |
                        (tlb_cam_mhit_test & cseq0 & crw0 ) |
//                        (tlb_cam_mhit_test & cseq2 & crw0 ) |
                        (tlb_cam_mhit_test & cseq1 & ((crw1 | crw3) & ~tlb_same_addr)) |
                        (tlb_cam_mhit_test & cseq1 & (crw0 & mhit_begin)) |

                        (stb_cam_mhit_test & cseq0 & crw0 ) |
                        (stb_cam_mhit_test & cseq1 & ((crw1 | crw3) & ~stb_same_addr)) |
                        (stb_cam_mhit_test & cseq1 & (crw0 & mhit_begin)) |
                        (stb_cam_gen_test  & cseq0 & crw0) |
                        (stb_cam_gen_test  & ~ctest09 & cseq1 & (crw0 | crw2)) |
//                        (stb_cam_mhit_test  & cseq2 & crw0) |
                        (stb_cam_pwk1_test  & cseq0 & crw0) |
                        (stb_cam_bwk1_test  & cseq0 & crw0) |
                        (stb_cam_bwk2_test  & cseq0 & crw0) |
                        (stb_cam_bwk2_test  & cseq1 & (crw0 | crw2)) |
                        (cam_clear  & cseq1) ;

   assign cam_en_pre     =  (tlb_cam_gen_test & cseq1 & crw0) |
                            (cam_array_0 & tlb_cam_walk1_test & cseq1 & (cam_zero | (cam_shift & ~(end_shift) ) | (cam_addr[6:0]==7'd0))) |
                            (cam_array_1 & tlb_cam_walk1_test & cseq1 & (cam_zero | (cam_shift & ~(end_shift) ) | (cam_addr[5:0]==6'd0))) |
                            (tlb_cam_mhit_test & cseq1 & crw1 & ~tlb_same_addr) |
                            (stb_cam_mhit_test & cseq1 & crw1 & ~stb_same_addr) |
                            (stb_cam_gen_test  & cseq1 & crw0) |
                            (stb_cam_pwk1_test & cseq1 & crw0 &         (cam_zero | (cam_shift & ~(end_shift) ) | (cam_addr[5:0]==6'd0))) |
                            (stb_cam_bwk2_test & cseq1 & crw0) |
                            (stb_cam_bwk1_test & (((cam_addr[5:0]==6'd63) & cseq0) | (~(cam_addr[5:0]==6'd63) & cseq1))) ;

   // can't have dmap and cam_en on at same time

   assign dmap_en       =   (cam_array_0 & tlb_cam_dmap_test & cseq1 & crw0 & (~|cam_addr[6:0])) |
                            (cam_array_0 & tlb_cam_dmap2_test & cseq1 & (~|cam_addr[6:0])) |
                            (cam_array_1 & tlb_cam_dmap_test & cseq1 & (~|cam_addr[5:0])) |
                            (cam_array_1 & tlb_cam_dmap2_test & cseq1 & ~|cam_addr[5:0]);


   assign cam_rd_en  =  (tlb_cam_gen_test & cseq1 & crw2) |
                        (tlb_cam_dmap_test & cseq2 & crw0) |
                        (tlb_cam_dmap2_test & cseq2 & crw0) |
                        (tlb_cam_rpwr_test & cseq1 & crw1) |
                        (tlb_cam_rpwr_test & cseq3 & crw1) |
                        (tlb_cam_rpwr_test & cseq4 & crw3);

   assign tlb_rpwr_en =    (tlb_cam_rpwr_test  & cseq1 & crw0) |
                           (tlb_cam_rpwr_test  & cseq3 & crw0) |
                           (tlb_cam_rpwr_test  & cseq4 & crw2) ;

   assign tlb_dis_clr_bit = (tlb_cam_rpwr_test & (cseq0 | cseq3 | cseq4)) | 
                                                 tlb_cam_gen_test |
                                                 tlb_cam_dmap_test |
                                                 tlb_cam_dmap2_test |
                                                 tlb_cam_walk1_test |
                                                 tlb_cam_mhit_test ;

   assign mbist_dis_clr_ubit=(tlb_dis_clr_bit | array_04 | array_08);


   spc_mb0_ctlmsff_ctl_macro__width_1 cam_en_reg  (
                 .scan_in(cam_en_reg_scanin),
                 .scan_out(cam_en_reg_scanout),
                 .l1clk    ( l1clk_pm1	    ),
                 .din      ( cam_en_pre     ),
                 .dout     ( cam_en         ),
  .siclk(siclk),
  .soclk(soclk));


   assign dmap_all  = ((ctest09 | (ctest10 & crw0)) & dmap_en);
   assign dmap_real = ((ctest07 | (ctest10 & crw3)) & dmap_en);
   assign dmap_cntx = ((ctest08 | (ctest10 & crw1)) & dmap_en);
   assign dmap_page = ((ctest06 | (ctest10 & crw2)) & dmap_en);


   assign dmap_on  = dmap_page | dmap_real | dmap_cntx | dmap_all;


   assign mbist_demap_type[1:0] = ({2{dmap_page}} & 2'b00) |
                                  ({2{dmap_real}} & 2'b01) |
                                  ({2{dmap_cntx}} & 2'b10) |
                                  ({2{dmap_all}}   & 2'b11);


  assign mbist_dtb_demap_en = dmap_on & cam_array_0;  // active only when dtlb is on
  assign mbist_itb_demap_en = dmap_on & cam_array_1;  // active only when itlb is on

  assign mbist_stb_cam_en_pre  = cam_array_2 & cam_en_pre;
  assign mbist_dtb_cam_en_pre  = cam_array_0 & cam_en_pre;
  assign mbist_itb_cam_en_pre  = cam_array_1 & cam_en_pre;

   // tcam   
   assign ctest00  =  ctest[3:0]==4'h0 & cambist;
   assign ctest01  =  ctest[3:0]==4'h1;
   assign ctest02  =  ctest[3:0]==4'h2;
   assign ctest03  =  ctest[3:0]==4'h3;
   assign ctest04  =  ctest[3:0]==4'h4;
   assign ctest05  =  ctest[3:0]==4'h5;

   // demap
   assign ctest06  =  ctest[3:0]==4'h6;
   assign ctest07  =  ctest[3:0]==4'h7;
   assign ctest08  =  ctest[3:0]==4'h8;
   assign ctest09  =  ctest[3:0]==4'h9;
   assign ctest10  =  ctest[3:0]==4'hA;

 
   assign ctest11  =  ctest[3:0]==4'hB;
   assign ctest12  =  ctest[3:0]==4'hC;
   assign ctest13  =  ctest[3:0]==4'hD;
//   assign ctest14  =  ctest[3:0]==4'hE;
//   assign ctest15  =  ~(~ctest[3] | ~ctest[2] | ~ctest[1] |  ctest[0]);
//   assign ctest16  =  ~(~ctest[3] | ~ctest[2] | ~ctest[1] | ~ctest[0]);


   assign tlb = cam_array_0 | cam_array_1;
   assign stb = cam_array_2;


   // stb generic cam test
   //     ^(W);^(----);
   //     seq2;seq3
   // 
   assign stb_cam_gen_test = stb &
                              (ctest00 |
                              ctest01 |
                              ctest02 |
                              ctest03 |
                              ctest04 |
                              ctest05 |
                              ctest09 );
                              

   assign stb_cam_pwk1_test = stb & (ctest06);


   // stb walking 1 byte_match
   // 


   // stb walking 1 ptag

   assign stb_cam_bwk1_test = stb & ctest07;                                


   assign stb_cam_bwk2_test = stb & ctest08;

//   assign stb_cam_misc_test = stb & ctest09;                                

   assign stb_cam_mhit_test = stb & ctest10;

   ////// TLB  

   assign tlb_cam_gen_test =  tlb &
                              (ctest00 |
                               ctest01 |
                               ctest02 |
                               ctest03 |
                               ctest04 |
                               ctest05) ;


   assign tlb_cam_dmap_test = tlb & 
                              (ctest06 | 
                               ctest07 | 
                               ctest08 | 
                               ctest09 );

   assign tlb_cam_dmap2_test = tlb & (ctest10);


   assign tlb_cam_walk1_test = tlb & ctest11;

   assign tlb_cam_rpwr_test =  tlb & ctest12;

   assign tlb_cam_mhit_test =  tlb & ctest13;


   assign cam_walk1 = (tlb_cam_walk1_test & cseq1) | (stb_cam_pwk1_test | stb_cam_bwk1_test | stb_cam_bwk2_test) ;


//   assign end_shift_pre =  ((cam_array_0 | cam_array_1) & tlb_cam_walk1_test) ?  cam_walk1 & (tlb_addr[5:0]==6'd51) :
//                            cam_array_2 & stb_cam_pwk1_test ?  cam_walk1 & (tlb_addr[5:0]==6'd36) :
//                                                               cam_walk1 & (tlb_addr[2:0]==3'd7) ;


   assign end_shift = cam_array_0 ? cam_walk1 & (tlb_addr[6:0]==7'd52) :
                      cam_array_1 ? cam_walk1 & (tlb_addr[5:0]==6'd52) :
                      cam_array_2 & stb_cam_pwk1_test ?  cam_walk1 & (tlb_addr[5:0]==6'd37) :
                                                         cam_walk1 & (tlb_addr[2:0]==3'd7) ;


   assign cam_zero  = (cam_array_0 & tlb_cam_walk1_test & cseq1 & (cam_addr[6:0]==7'b0000001)) |
                      (cam_array_1 & tlb_cam_walk1_test & cseq1 & (cam_addr[5:0]==6'b000001)) |
                      (cam_array_2 & stb_cam_pwk1_test & cseq1 &  (cam_addr[5:0]==6'b000001)) |
                      (cam_array_2 & stb_cam_bwk1_test & cseq1 & ~|cam_addr[2:0]) ;
                     

  assign cam_shift_val =   ~cambist | end_shift  ? 1'b0 :
                           cam_zero & (cseq1 | cseq3)   ? 1'b1 :
                                                  cam_shift;
                                           

   // data assignments

  assign mbist_ptag_data = ptag_data;

   // cam data assignment

  assign ptag_data     = (ctest00 & cseq1 & (crw0 |crw1)) |
                         (ctest01 & cseq0)        |
                         (ctest01 & cseq1 & crw2) |
                         (ctest02 & cseq1 & (crw0 | crw1)) |
                         (ctest03 & cseq1 & (crw0 | crw1)) |
                         (ctest04 & cseq1 & (crw0 | crw1)) |
                         (ctest05 & cseq1 & (crw0 | crw1)) |
                         (ctest07 ) |
                         (ctest09 ) |
                         (ctest10 & cseq1 & (crw1 | crw2) ) |
                         (ctest10 & cseq1 & crw0 & mhit_begin ) ;


  assign stb_data[7:0] = ({8{(ctest00 & cseq0)        }} & 8'b00000000) |
                         ({8{(ctest00 & cseq1 & crw0 )}} & 8'b11111111) |
                         ({8{(ctest00 & cseq1 & crw1 )}} & 8'b11111111) |
                         ({8{(ctest00 & cseq1 & crw3 )}} & 8'b00000000) |
                         ({8{(ctest01 & cseq0)        }} & 8'b00000000) |
                         ({8{(ctest01 & cseq1 & crw0 )}} & 8'b11111111) |
                         ({8{(ctest01 & cseq1 & crw1 )}} & 8'b11111111) |
                         ({8{(ctest01 & cseq1 & crw3 )}} & 8'b00000000) |
                         ({8{(ctest02 & cseq0)        }} & 8'h00) |
                         ({8{(ctest02 & cseq1 & crw0 )}} & 8'hAA) |
                         ({8{(ctest02 & cseq1 & crw1 )}} & 8'hFF) |
                         ({8{(ctest02 & cseq1 & crw3 )}} & 8'h00) |
                         ({8{(ctest03 & cseq0)        }} & 8'h00) |
                         ({8{(ctest03 & cseq1 & crw0 )}} & 8'h55) |
                         ({8{(ctest03 & cseq1 & crw1 )}} & 8'hFF) |
                         ({8{(ctest03 & cseq1 & crw3 )}} & 8'h00) |
                         ({8{(ctest04 & cseq0)        }} & 8'h00) |
                         ({8{(ctest04 & cseq1 & crw0 )}} & 8'h55) |
                         ({8{(ctest04 & cseq1 & crw1 )}} & 8'h55) |
                         ({8{(ctest04 & cseq1 & crw3 )}} & 8'h00) |
                         ({8{(ctest05 & cseq0)        }} & 8'h00) |
                         ({8{(ctest05 & cseq1 & crw0 )}} & 8'hAA) |
                         ({8{(ctest05 & cseq1 & crw1 )}} & 8'hAA) |
                         ({8{(ctest05 & cseq1 & crw3 )}} & 8'h00) |
                         ({8{(ctest06 & cseq0)        }} & 8'hFF) |
                         ({8{(ctest06 & cseq1 & crw0 )}} & 8'hFF) |
                         ({8{(ctest07 & cseq0)        }} & 8'h00) |
                         ({8{(ctest07 & cam_zero     )}} & 8'h01) |
                         ({8{(ctest07 & cam_shift     )}} & {mb0_write_data[6:0],1'b0}) |
                         ({8{(ctest08 & cseq0         )}} & 8'h00) |
                         ({8{(ctest08 & cseq1 & crw0  )}} & 8'hFF) |
                         ({8{(ctest08 & cseq1 & crw1  )}} & walk1data[7:0]) |
                         ({8{(ctest08 & cseq1 & crw2  )}} & 8'h00) |
                         ({8{(ctest10 & cseq1 & crw1  )}} & 8'hFF) |
                         ({8{(ctest10 & cseq1 & crw2  )}} & 8'hFF) |
                         ({8{(ctest10 & cseq0 & crw0  )}} & 8'h00) |
                         ({8{(ctest10 & cseq1 & mhit_begin & crw0  )}} & 8'hFF) ;

  assign walk1data[7:0] = ({8{cam_raw_addr[8:6]==3'b000}} & 8'b0000_0001) |
                          ({8{cam_raw_addr[8:6]==3'b001}} & 8'b0000_0010) |
                          ({8{cam_raw_addr[8:6]==3'b010}} & 8'b0000_0100) |
                          ({8{cam_raw_addr[8:6]==3'b011}} & 8'b0000_1000) |
                          ({8{cam_raw_addr[8:6]==3'b100}} & 8'b0001_0000) |
                          ({8{cam_raw_addr[8:6]==3'b101}} & 8'b0010_0000) |
                          ({8{cam_raw_addr[8:6]==3'b110}} & 8'b0100_0000) |
                          ({8{cam_raw_addr[8:6]==3'b111}} & 8'b1000_0000) ;
                         
  assign cam_data[7:0] = cam_clear   ? 8'h00 :
                         cam_array_2 ? stb_data[7:0] : 
                                       tlb_data[7:0];


   // 7 ( nothing)
   // 6 used
   // 5 real
   // 4 valid
   // 3 context0
   // 2 context1
   // 1 PID
   // 0 oter (va)

                         
  assign tlb_data[7:0] = ({8{(ctest00 & cseq0)        }} & 8'b10101111) | // ^(W0)
                         ({8{(ctest00 & cseq1 & crw0 )}} & 8'b10111111) | // W1
                         ({8{(ctest00 & cseq1 & crw1 )}} & 8'b10110011) | // C1
                         ({8{(ctest00 & cseq1 & crw3 )}} & 8'b10101111) | // W0

                         ({8{(ctest01 & cseq0)        }} & 8'b00100000) |
                         ({8{(ctest01 & cseq1 & crw0 )}} & 8'b00110000) | // W1
                         ({8{(ctest01 & cseq1 & crw1 )}} & 8'b00101100) | // C1
                         ({8{(ctest01 & cseq1 & crw3 )}} & 8'b00100000) | // W0

                         ({8{(ctest02 & cseq0)        }} & 8'b10001111) |
                         ({8{(ctest02 & cseq1 & crw0 )}} & 8'b10011111) | // W1
                         ({8{(ctest02 & cseq1 & crw1 )}} & 8'b10010111) | // C1
                         ({8{(ctest02 & cseq1 & crw3 )}} & 8'b10001111) | // W0

                         ({8{(ctest03 & cseq0)        }} & 8'b10001111) |
                         ({8{(ctest03 & cseq1 & crw0 )}} & 8'b10011111) | // W1
                         ({8{(ctest03 & cseq1 & crw1 )}} & 8'b10011011) | // C1
                         ({8{(ctest03 & cseq1 & crw3 )}} & 8'b10001111) | // W0

                         ({8{(ctest04 & cseq0)        }} & 8'b00000000) |
                         ({8{(ctest04 & cseq1 & crw0 )}} & 8'b00010000) | // W1
                         ({8{(ctest04 & cseq1 & crw1 )}} & 8'b00001000) | // C1
                         ({8{(ctest04 & cseq1 & crw3 )}} & 8'b00000000) | // W0

                         ({8{(ctest05 & cseq0)        }} & 8'b00000000) |
                         ({8{(ctest05 & cseq1 & crw0 )}} & 8'b00010000) | // W1
                         ({8{(ctest05 & cseq1 & crw1 )}} & 8'b00000100) | // C1
                         ({8{(ctest05 & cseq1 & crw3 )}} & 8'b00000000) | // W0

                         ({8{(ctest06 & cseq0)        }} & 8'b00010000) |
                         ({8{(ctest06 & cseq1 )}}        & 8'b00001000) |

                         ({8{(ctest07 & cseq0)        }} & 8'b10111111) |
                         ({8{(ctest07 & cseq1 )}}        & 8'b00100010) |

                         ({8{(ctest08 & cseq0)        }} & 8'b00010000) |
                         ({8{(ctest08 & cseq1 )}}        & 8'b10010101) |

                         ({8{(ctest09 & cseq0)        }} & 8'b10111111) |
                         ({8{(ctest09 & cseq1 )}}        & 8'b00000010) |

                         ({8{(ctest10 & cseq0)        }} & 8'b00010000) |
                         ({8{(ctest10 & cseq1 & crw0 )}} & 8'b00000010) |
                         ({8{(ctest10 & cseq1 & crw1 )}} & 8'b00001100) |
                         ({8{(ctest10 & cseq1 & crw2 )}} & 8'b00001100) |
                         ({8{(ctest10 & cseq1 & crw3 )}} & 8'b00100000) |

                         ({8{(ctest11 & cseq0 & crw0 )}} & 8'b00010000) |

                         ({8{(ctest12 & cseq0 & crw0 )}} & 8'b00000000) |
                         ({8{(ctest12 & cseq1 & crw0 )}} & 8'b01010000) |
                         ({8{(ctest12 & cseq3 & crw0 )}} & 8'b01010000) |
                         ({8{(ctest12 & cseq4 & crw0 )}} & 8'b01000000) |
                         ({8{(ctest12 & cseq4 & crw2 )}} & 8'b01010000) |

                         ({8{(ctest13 & cseq0 & crw0 )}} & 8'b00000000) |
                         ({8{(ctest13 & cseq1 & crw0 )}} & 8'b10111111) |
                         ({8{(ctest13 & cseq1 & crw1 )}} & 8'b10111111) |
                         ({8{(ctest13 & cseq1 & crw2 )}} & 8'b10111111) |
                         ({8{(ctest13 & cseq1 & crw3 )}} & 8'b00000000) ;


//  assign tlb_sb_mhit      =(tlb_cam_gen_test   & cseq1 & crw1) |
//                           (tlb_cam_walk1_test & cseq1 & crw0) |
//                           (tlb_cam_mhit_test  & cseq1 & crw1) ;

//  assign tlb_sb_camhit    =(tlb_cam_gen_test   & cseq1 & crw1) |
//                           (tlb_cam_walk1_test & cseq1 & crw0) |
//                           (tlb_cam_mhit_test  & cseq1 & crw1) ;

//  assign tlb_sb_data_cmp  =(tlb_cam_gen_test   & cseq1 & crw1) |
//                           (tlb_cam_rpwr_test  & cseq1 & crw1) |
//                           (tlb_cam_rpwr_test  & cseq2 & crw1) |
//                           (tlb_cam_rpwr_test  & cseq3 & crw2);

//  assign tlb_sb_cntx0_hit =(ctest02  & cseq1 & crw1) |
//                           (ctest03  & cseq1 & crw1) |
//                           (ctest04  & cseq1 & crw1) |
//                           (ctest05  & cseq1 & crw1) ;


//  assign tlb_sb_valid     =(tlb_cam_gen_test   & cseq1 & crw2) |
//                           (tlb_cam_dmap_test  & cseq2 & crw0) |
//                           (tlb_cam_dmap2_test & cseq2 & crw0) ;

//  assign tlb_sb_ubit      =(tlb_cam_gen_test   & cseq1 & crw2) |
//                           (tlb_cam_walk1_test & cseq2 & crw0) ;

    // stb
    assign stb_cam_en             = cam_en & cam_array_2;
    assign stb_hit_cmp            = stb_cam_en;
    assign stb_hit_cmp_mhit_l     = stb_cam_en & ~ctest10;
    assign exp_stb_cam_hit        = ~(ctest06 | ctest07 | ctest09);
    assign exp_stb_hit_ptr[2:0]   = (ctest07 | ctest09) ? 3'b000: mb0_addr[2:0];
    assign exp_stb_mhit           = ctest10;
    assign exp_stb_ld_partial_raw = (ctest02 | ctest03);


   spc_mb0_ctlmsff_ctl_macro__width_3 stb_hit_cmp_delay  (
                 .scan_in(stb_hit_cmp_delay_scanin),
                 .scan_out(stb_hit_cmp_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                    ),
                 .din      ({stb_hit_cmp,   stb_hit_cmp_d1, stb_hit_cmp_d2} ),
                 .dout     ({stb_hit_cmp_d1,stb_hit_cmp_d2, stb_hit_cmp_d3}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_3 stb_hit_cmp_mhit_l_delay  (
                 .scan_in(stb_hit_cmp_mhit_l_delay_scanin),
                 .scan_out(stb_hit_cmp_mhit_l_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                    ),
                 .din      ({stb_hit_cmp_mhit_l,   stb_hit_cmp_mhit_l_d1, stb_hit_cmp_mhit_l_d2} ),
                 .dout     ({stb_hit_cmp_mhit_l_d1,stb_hit_cmp_mhit_l_d2, stb_hit_cmp_mhit_l_d3}),
  .siclk(siclk),
  .soclk(soclk));

   spc_mb0_ctlmsff_ctl_macro__width_3 exp_stb_cam_hit_delay  (
                 .scan_in(exp_stb_cam_hit_delay_scanin),
                 .scan_out(exp_stb_cam_hit_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                                ),
                 .din      ({exp_stb_cam_hit,   exp_stb_cam_hit_d1, exp_stb_cam_hit_d2} ),
                 .dout     ({exp_stb_cam_hit_d1,exp_stb_cam_hit_d2, exp_stb_cam_hit_d3}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_9 exp_stb_hit_ptr_delay  (
                 .scan_in(exp_stb_hit_ptr_delay_scanin),
                 .scan_out(exp_stb_hit_ptr_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                                               ),
                 .din      ({exp_stb_hit_ptr[2:0],   exp_stb_hit_ptr_d1[2:0], exp_stb_hit_ptr_d2[2:0]} ),
                 .dout     ({exp_stb_hit_ptr_d1[2:0],exp_stb_hit_ptr_d2[2:0], exp_stb_hit_ptr_d3[2:0]}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_3 exp_stb_mhit_delay  (
                 .scan_in(exp_stb_mhit_delay_scanin),
                 .scan_out(exp_stb_mhit_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                       ),
                 .din      ({exp_stb_mhit,   exp_stb_mhit_d1, exp_stb_mhit_d2} ),
                 .dout     ({exp_stb_mhit_d1,exp_stb_mhit_d2, exp_stb_mhit_d3}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_3 exp_stb_ld_partial_raw_delay  (
                 .scan_in(exp_stb_ld_partial_raw_delay_scanin),
                 .scan_out(exp_stb_ld_partial_raw_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                                                     ),
                 .din      ({exp_stb_ld_partial_raw,   exp_stb_ld_partial_raw_d1, exp_stb_ld_partial_raw_d2} ),
                 .dout     ({exp_stb_ld_partial_raw_d1,exp_stb_ld_partial_raw_d2, exp_stb_ld_partial_raw_d3}),
  .siclk(siclk),
  .soclk(soclk));


     assign stb_cam_hit_pass             = (~stb_hit_cmp_d3)        | (stb_hit_cmp_d3          & (exp_stb_cam_hit_d3 == lsu_mbi_scm_hit));
     assign stb_hit_ptr_pass             = (~stb_hit_cmp_mhit_l_d3) | (stb_hit_cmp_mhit_l_d3   & (exp_stb_hit_ptr_d3[2:0] == lsu_mbi_scm_hit_ptr[2:0]));
     assign stb_mhit_pass                = (~stb_hit_cmp_d3)        | (stb_hit_cmp_d3          & (exp_stb_mhit_d3 == lsu_mbi_scm_mhit));
     assign stb_ld_partial_raw_pass      = (~stb_hit_cmp_mhit_l_d3) | (stb_hit_cmp_mhit_l_d3   & (exp_stb_ld_partial_raw_d3 == lsu_mbi_scm_praw));

     assign cbist_stb_cam_fail = ~(stb_cam_hit_pass &
                             stb_hit_ptr_pass &
                             stb_mhit_pass &
                             stb_ld_partial_raw_pass ) & cam_array_2_d3;
                             
    // tlb
    assign tlb_cam_en    = (cam_en & (cam_array_0 | cam_array_1));
    assign tlb_hit_cmp   = tlb_cam_en;
//    assign cam_rd_cmp   = cam_rd_en;
    assign cam_valid_cmp   = cam_rd_en;
    assign cam_used_cmp    = cam_rd_en & (~cseq1 & tlb_cam_rpwr_test);
    assign tlb_cntx0_cmp = (ctest02 | ctest03 | ctest04 | ctest05 | ctest06 | ctest05) & (cam_array_0 | cam_array_1) & cam_en;
    assign exp_tlb_mhit = (tlb_cam_mhit_test);
    assign tlb_data_cmp = (~ctest13 | ~ctest12) ? 1'b0 : tlb_hit_cmp;

    assign exp_cam_hit  = (tlb_cam_gen_test | tlb_cam_mhit_test & cseq1);
    assign exp_valid    = (tlb_cam_gen_test | tlb_cam_dmap2_test | tlb_cam_rpwr_test) ;
    assign exp_used     = (tlb_cam_gen_test | tlb_cam_walk1_test | tlb_cam_rpwr_test);
    assign exp_data_cmp = (tlb_cam_gen_test);
    

    assign exp_cntx0_hit= (ctest03 | ctest05) & (cam_array_0 | cam_array_1);

   spc_mb0_ctlmsff_ctl_macro__width_4 cam_array_0_delay  (
                 .scan_in(cam_array_0_delay_scanin),
                 .scan_out(cam_array_0_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                    ),
                 .din      ({cam_array_0,   cam_array_0_d1, cam_array_0_d2,cam_array_0_d3} ),
                 .dout     ({cam_array_0_d1,cam_array_0_d2, cam_array_0_d3,cam_array_0_d4}),
  .siclk(siclk),
  .soclk(soclk));

   spc_mb0_ctlmsff_ctl_macro__width_5 cam_array_1_delay  (
                 .scan_in(cam_array_1_delay_scanin),
                 .scan_out(cam_array_1_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                    ),
                 .din      ({cam_array_1,   cam_array_1_d1, cam_array_1_d2, cam_array_1_d3,cam_array_1_d4} ),
                 .dout     ({cam_array_1_d1,cam_array_1_d2, cam_array_1_d3, cam_array_1_d4,cam_array_1_d5}),
  .siclk(siclk),
  .soclk(soclk));

   spc_mb0_ctlmsff_ctl_macro__width_3 cam_array_2_delay  (
                 .scan_in(cam_array_2_delay_scanin),
                 .scan_out(cam_array_2_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                    ),
                 .din      ({cam_array_2,   cam_array_2_d1, cam_array_2_d2} ),
                 .dout     ({cam_array_2_d1,cam_array_2_d2, cam_array_2_d3}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_6 cam_hit_cmp_delay  (
                 .scan_in(cam_hit_cmp_delay_scanin),
                 .scan_out(cam_hit_cmp_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                    ),
                 .din      ({tlb_hit_cmp,   tlb_hit_cmp_d1, tlb_hit_cmp_d2,tlb_hit_cmp_d3,tlb_hit_cmp_d4,tlb_hit_cmp_d5} ),
                 .dout     ({tlb_hit_cmp_d1,tlb_hit_cmp_d2, tlb_hit_cmp_d3,tlb_hit_cmp_d4,tlb_hit_cmp_d5,tlb_hit_cmp_d6}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_5 data_cmp_delay  (
                 .scan_in(data_cmp_delay_scanin),
                 .scan_out(data_cmp_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                    ),
                 .din      ({tlb_data_cmp,   tlb_data_cmp_d1, tlb_data_cmp_d2,tlb_data_cmp_d3,tlb_data_cmp_d4} ),
                 .dout     ({tlb_data_cmp_d1,tlb_data_cmp_d2, tlb_data_cmp_d3,tlb_data_cmp_d4,tlb_data_cmp_d5}),
  .siclk(siclk),
  .soclk(soclk));


//   msff_ctl_macro cam_rd_cmp_delay (width=3) (
//                 .scan_in(cam_rd_cmp_delay_scanin),
//                 .scan_out(cam_rd_cmp_delay_scanout),
//                 .l1clk    ( l1clk_pm1	                           ),
//                 .din      ({cam_rd_cmp,   cam_rd_cmp_d1, cam_rd_cmp_d2} ),
//                 .dout     ({cam_rd_cmp_d1,cam_rd_cmp_d2, cam_rd_cmp_d3}));


   spc_mb0_ctlmsff_ctl_macro__width_5 cam_valid_cmp_delay  (
                 .scan_in(cam_valid_cmp_delay_scanin),
                 .scan_out(cam_valid_cmp_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                                         ),
                 .din      ({cam_valid_cmp,   
                             cam_valid_cmp_d1, 
                             cam_valid_cmp_d2,
                             cam_valid_cmp_d3,
                             cam_valid_cmp_d4} ),
                 .dout     ({cam_valid_cmp_d1,
                             cam_valid_cmp_d2, 
                             cam_valid_cmp_d3,
                             cam_valid_cmp_d4,
                             cam_valid_cmp_d5}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_5 cam_used_cmp_delay  (
                 .scan_in(cam_used_cmp_delay_scanin),
                 .scan_out(cam_used_cmp_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                                         ),
                 .din      ({cam_used_cmp,   
                             cam_used_cmp_d1, 
                             cam_used_cmp_d2,
                             cam_used_cmp_d3,
                             cam_used_cmp_d4} ),
                 .dout     ({cam_used_cmp_d1,
                             cam_used_cmp_d2, 
                             cam_used_cmp_d3,
                             cam_used_cmp_d4,
                             cam_used_cmp_d5}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_5 exp_data_cmp_delay  (
                 .scan_in(exp_data_cmp_delay_scanin),
                 .scan_out(exp_data_cmp_delay_scanout),
                 .l1clk    ( l1clk_pm1	                              ),
                 .din      ({exp_data_cmp,   exp_data_cmp_d1, exp_data_cmp_d2,exp_data_cmp_d3, exp_data_cmp_d4} ),
                 .dout     ({exp_data_cmp_d1,exp_data_cmp_d2, exp_data_cmp_d3,exp_data_cmp_d4, exp_data_cmp_d5}),
  .siclk(siclk),
  .soclk(soclk));

   spc_mb0_ctlmsff_ctl_macro__width_5 exp_valid_delay  (
                 .scan_in(exp_valid_delay_scanin),
                 .scan_out(exp_valid_delay_scanout),
                 .l1clk    ( l1clk_pm1	                              ),
                 .din      ({exp_valid,   exp_valid_d1, exp_valid_d2,exp_valid_d3,exp_valid_d4} ),
                 .dout     ({exp_valid_d1,exp_valid_d2, exp_valid_d3,exp_valid_d4,exp_valid_d5}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_5 exp_used_delay  (
                 .scan_in(exp_used_delay_scanin),
                 .scan_out(exp_used_delay_scanout),
                 .l1clk    ( l1clk_pm1	                           ),
                 .din      ({exp_used,   exp_used_d1, exp_used_d2,exp_used_d3,exp_used_d4} ),
                 .dout     ({exp_used_d1,exp_used_d2, exp_used_d3,exp_used_d4,exp_used_d5}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_6 tlb_cntx0_cmp_delay  (
                 .scan_in(tlb_cntx0_cmp_delay_scanin),
                 .scan_out(tlb_cntx0_cmp_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                          ),
                 .din      ({tlb_cntx0_cmp,   tlb_cntx0_cmp_d1, tlb_cntx0_cmp_d2, tlb_cntx0_cmp_d3,tlb_cntx0_cmp_d4,tlb_cntx0_cmp_d5} ),
                 .dout     ({tlb_cntx0_cmp_d1,tlb_cntx0_cmp_d2, tlb_cntx0_cmp_d3, tlb_cntx0_cmp_d4,tlb_cntx0_cmp_d5,tlb_cntx0_cmp_d6}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_6 exp_cam_hit_delay  (
                 .scan_in(exp_cam_hit_delay_scanin),
                 .scan_out(exp_cam_hit_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                    ),
                 .din      ({exp_cam_hit,   exp_cam_hit_d1, exp_cam_hit_d2,exp_cam_hit_d3,exp_cam_hit_d4,exp_cam_hit_d5} ),
                 .dout     ({exp_cam_hit_d1,exp_cam_hit_d2, exp_cam_hit_d3,exp_cam_hit_d4,exp_cam_hit_d5,exp_cam_hit_d6}),
  .siclk(siclk),
  .soclk(soclk));

   spc_mb0_ctlmsff_ctl_macro__width_6 exp_cntx0_hit_delay  (
                 .scan_in(exp_cntx0_hit_delay_scanin),
                 .scan_out(exp_cntx0_hit_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                          ),
                 .din      ({exp_cntx0_hit,   exp_cntx0_hit_d1, exp_cntx0_hit_d2, exp_cntx0_hit_d3,exp_cntx0_hit_d4,exp_cntx0_hit_d5} ),
                 .dout     ({exp_cntx0_hit_d1,exp_cntx0_hit_d2, exp_cntx0_hit_d3, exp_cntx0_hit_d4,exp_cntx0_hit_d5,exp_cntx0_hit_d6}),
  .siclk(siclk),
  .soclk(soclk));


   spc_mb0_ctlmsff_ctl_macro__width_6 exp_mhit_delay  (
                 .scan_in(exp_mhit_delay_scanin),
                 .scan_out(exp_mhit_delay_scanout),
                 .l1clk    ( l1clk_pm1	                                       ),
                 .din      ({exp_tlb_mhit,   exp_tlb_mhit_d1, exp_tlb_mhit_d2, exp_tlb_mhit_d3,exp_tlb_mhit_d4,exp_tlb_mhit_d5} ),
                 .dout     ({exp_tlb_mhit_d1,exp_tlb_mhit_d2, exp_tlb_mhit_d3, exp_tlb_mhit_d4,exp_tlb_mhit_d5,exp_tlb_mhit_d6}),
  .siclk(siclk),
  .soclk(soclk));


   assign dtlb_cam_hit_pass   = (~tlb_hit_cmp_d4)        | (tlb_hit_cmp_d4   & (exp_cam_hit_d4 == lsu_mbi_tlb_cam_hit));
   assign dtlb_cntx0_hit_pass = (~tlb_cntx0_cmp_d4)      | (tlb_cntx0_cmp_d4 & (exp_cntx0_hit_d4 == lsu_mbi_tlb_ctxt0_hit));
   assign dtlb_mhit_pass      = (~tlb_hit_cmp_d4)        | (tlb_hit_cmp_d4   & (exp_tlb_mhit_d4 == lsu_mbi_tlb_cam_mhit));
   assign dtlb_valid_pass     = (~cam_valid_cmp_d4)      | (cam_valid_cmp_d4    & (exp_valid_d4 == lsu_mbi_tlb_valid));
   assign dtlb_used_pass      = (~cam_used_cmp_d4)       | (cam_used_cmp_d4    & (exp_used_d4 == lsu_mbi_tlb_used));
   assign dtlb_data_cmp_pass  = (~tlb_data_cmp_d4)       | (tlb_data_cmp_d4    & (exp_data_cmp_d4 == lsu_mbi_tlb_data_cmp));

   assign cbist_dtlb_cam_fail = ~(dtlb_cam_hit_pass & 
                            dtlb_cntx0_hit_pass & 
                            dtlb_mhit_pass & 
                            dtlb_valid_pass & 
                            dtlb_used_pass & 
                            dtlb_data_cmp_pass ) & cam_array_0_d4;


   assign itlb_cam_hit_pass   = (~tlb_hit_cmp_d6)        | (tlb_hit_cmp_d6   & (exp_cam_hit_d6 == ftu_mbi_tlb_cam_hit));
   assign itlb_cntx0_hit_pass = (~tlb_cntx0_cmp_d6)      | (tlb_cntx0_cmp_d6 & (exp_cntx0_hit_d6 == ftu_mbi_tlb_ctxt0_hit));
   assign itlb_mhit_pass      = (~tlb_hit_cmp_d6)        | (tlb_hit_cmp_d6   & (exp_tlb_mhit_d6 == ftu_mbi_tlb_cam_mhit));
   assign itlb_valid_pass     = (~cam_valid_cmp_d5)      | (cam_valid_cmp_d5 & (exp_valid_d5 == ftu_mbi_tlb_valid));
   assign itlb_used_pass      = (~cam_used_cmp_d5)       | (cam_used_cmp_d5  & (exp_used_d5 == ftu_mbi_tlb_used));
   assign itlb_data_cmp_pass  = (~tlb_data_cmp_d5)       | (tlb_data_cmp_d5  & (exp_data_cmp_d5 == ftu_mbi_tlb_data_cmp));


   assign cbist_itlb_cam_fail = ~(itlb_cam_hit_pass & 
                            itlb_cntx0_hit_pass & 
                            itlb_mhit_pass & 
                            itlb_valid_pass & 
                            itlb_used_pass & 
                            itlb_data_cmp_pass ) & cam_array_1_d5;


   assign qual_cam[26:0]={cam_msb,            //  1  27
              			  cam_array_sel[1:0], //  2	 26		  
              			  cam_ctest[3:0],     //  4  24
              			  cam_cseq[2:0],          //  2  19
                          cam_raw_addr[14:0], // 15  17
			              cam_crw[1:0]};          //  2  
   

   assign cam_in[26:0]=((~cambist | ~cambist_d4) & run3) | reset_engine ? 27'b0: 
                       (cambist_d4 & run3)     ?      qual_cam[26:0]+27'h1:
	                                           qual_cam[26:0];
	                                      
   
/////////////////////////////////////////////////////////////////////////////////
//
// Mbist fail signals
//
// /////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////   
// Interface signal for cambist
// 
//
//
//////////////////////////////////////////////////////////////////////////////


spc_mb0_ctlmsff_ctl_macro__width_13		tlb_cam_intf_out  (
                   .scan_in(tlb_cam_intf_out_scanin),
                   .scan_out(tlb_cam_intf_out_scanout),
                   .l1clk( l1clk_pm1				),
                   .din  ({ mbist_cambist_run			,
                            mbist_cambist_shift			,
                            mbist_dis_clr_ubit			,
                            mbist_demap_type[1:0]		,
                            mbist_init_to_zero			,
                            mbist_stb_cam_en_pre		,
                            mbist_ptag_data			,
                            mbist_dtb_cam_en_pre		,
                            mbist_dtb_demap_en			,
                            mbist_itb_demap_en			,
                            mbist_itb_cam_en_pre		,
                            mbist_repl_write}			),
                   .dout ({ mbi_cambist_run			,
                            mbi_cambist_shift			,
                            mbi_dis_clr_ubit			,
                            mbi_demap_type[1:0]			,
                            mbi_init_to_zero			,
                            mbi_scm_cam_en_pre			,
                            mbi_ptag_data			,
                            mbi_dtb_cam_en_pre			,
                            mbi_dtb_demap_en			,
                            mbi_itb_demap_en			,
                            mbi_itb_cam_en_pre			,
                            mbi_repl_write}			),
  .siclk(siclk),
  .soclk(soclk));


//////////////////////////////////////////////////////////////////////
///  cam comparator:
//////////////////////////////////////////////////////////////////////


//assign cam_fail=~cam_pass;

assign mbist_cambist_run=(cambist & ~cam_clear) | cam_msb;
assign mbist_cambist_shift=(stb_cam_bwk1_test | stb_cam_bwk2_test) ? 1'b0 : cam_shift;
assign mbist_init_to_zero=(stb_cam_bwk1_test | stb_cam_bwk2_test) ? 1'b0 : cam_zero;
assign mbist_repl_write=tlb_rpwr_en;


// /////////////////////////////////////////////////////////////////////////////
//
// MBIST Control Register
//
// /////////////////////////////////////////////////////////////////////////////
// standard membist
// /////////////////////////////////////////////////////////////////////////////
//   0       1       2       3      4      5          6         7        8
// ^(W0);^(R0W1);^(R1W0);v(R0W1);v(R1W0);v(R0);^(W1W0*R1R0W0);v(W1);^(W0W1*R0R1W1);
//   
// - there are 9 march elements in the engine
//   march_0 - march_8 indicate which march element it's in
//
// - for each march element, there are write and read sequences and for some
//   just write or just read
// 
// - for each march element, it can move upaddr (0-max) or downaddr (max-0)
//
//       march      rw       upaddr                    truedata
// --------------------------------------------------------------------------------
//    -  march_0    w          1    one_cycle_march       rw_0        ^(W0)
//    -  march_1    rw         1    two_cycle_march       rw_0        ^(R0W1)
//    -  march_2    rw         1    two_cycle_march       rw_1        ^(R1W0)
//    -  march_3    rw         0    two_cycle_march       rw_0        v(R0W1)
//    -  march_4    rw         0    two_cycle_march       rw_1        v(R1W0)
//    -  march_5    r          0    one_cycle_march       rw_0        v(R0)
//    -  march_6    wwrrw      1    five_cycle_march      rw_1,3,4    ^(W1W0*R1R0W0)
//    -  march_7    w          0    one_cycle_march       --          v(W1)
//    -  march_8    wwrrw      1    five_cycle_march      rw_0,2      ^(W0W1*R0R1W1)
// mbist address:
//    one_cycle_march  : march_0 | march_5 | march_7
//    five_cycle_march : march_6 | march_8
//    two_cycle_march  : ~(one_cycle_march | five_cycle_march)

   ////////////////////////////////////////////////////////////////////////////////
   //////  user mode signals

// the different between cntl_march and march is that march is before mux and
// and cntl_march is after mux

// /////////////////////////////////////////////////////////////////////////////
//
// MBIST Control Register
//
// /////////////////////////////////////////////////////////////////////////////
// standard membist
// /////////////////////////////////////////////////////////////////////////////
//   0       1       2       3      4      5          6         7        8
// ^(W0);^(R0W1);^(R1W0);v(R0W1);v(R1W0);v(R0);^(W1W0*R1R0W0);v(W1);^(W0W1*R0R1W1);
//   
// - there are 9 march elements in the engine
//   march_0 - march_8 indicate which march element it's in
//
// - for each march element, there are write and read sequences and for some
//   just write or just read
// 
// - for each march element, it can move upaddr (0-max) or downaddr (max-0)
//
//       march      rw       upaddr                    truedata
// --------------------------------------------------------------------------------
//    -  march_0    w          1    one_cycle_march       rw_0        ^(W0)
//    -  march_1    rw         1    two_cycle_march       rw_0        ^(R0W1)
//    -  march_2    rw         1    two_cycle_march       rw_1        ^(R1W0)
//    -  march_3    rw         0    two_cycle_march       rw_0        v(R0W1)
//    -  march_4    rw         0    two_cycle_march       rw_1        v(R1W0)
//    -  march_5    r          0    one_cycle_march       rw_0        v(R0)
//    -  march_6    wwrrw      1    five_cycle_march      rw_1,3,4    ^(W1W0*R1R0W0)
//    -  march_7    w          0    one_cycle_march       --          v(W1)
//    -  march_8    wwrrw      1    five_cycle_march      rw_0,2      ^(W0W1*R0R1W1)
// mbist address:
//    one_cycle_march  : march_0 | march_5 | march_7
//    five_cycle_march : march_6 | march_8
//    two_cycle_march  : ~(one_cycle_march | five_cycle_march)

   ////////////////////////////////////////////////////////////////////////////////
   //////  user mode signals

// the different between cntl_march and march is that march is before mux and
// and cntl_march is after mux

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////   ////////////////////////////////////
//  CONTROL REG:
////////////////////////////////////   ////////////////////////////////////


   spc_mb0_ctlmsff_ctl_macro__width_28 cntl_reg  (
                 .scan_in(cntl_reg_scanin),
                 .scan_out(cntl_reg_scanout),
                 .l1clk    ( l1clk_pm1	                      ),
                 .din      ({cntl_in[34:19] ,cntl_in[11:0]}   ),
                 .dout     ({cntl_out[34:19],cntl_out[11:0]}  ),
  .siclk(siclk),
  .soclk(soclk));


   assign cntl_in[34:19]   = reset_engine      ? {16'b00000_0000000000}:
     	                     ~run3 | cambist   ? cntl_algr[15:0]:	  
	                                          next_algr[15:0];

   
   // reset_engine   run3    overflow   cout_rw    output
   // ---------------------------------------------------------
   //    1             x        x          x       start_addr
   //    0             0        x          x       cntl_addr
   //    0             1        1          x       restart_addr
   //    0             1        0          1       incred_addr
   //    0             1        0          0       cntl_addr                                     


   assign sel_nextaddr_reset    = reset_engine;
   assign sel_nextaddr_restart  = ~reset_engine & run3 & overflow;
   assign sel_nextaddr_incred   = ~reset_engine & run3 & ~overflow & cout_rw & ~cambist;
   assign sel_nextaddr_same     = ~(sel_nextaddr_reset | sel_nextaddr_restart | sel_nextaddr_incred) | cambist;

   assign cntl_in[11:3] = ({9{sel_nextaddr_reset}} & start_addr[8:0]) |
                          ({9{sel_nextaddr_restart}} & restart_addr[8:0]) |
                          ({9{sel_nextaddr_incred}} & incred_addr[8:0]) |
                          ({9{sel_nextaddr_same}} & cntl_addr[8:0]);  
   

   assign cntl_in[2:0]     = reset_engine  ? 3'b000 : 
                             (~run3 | cambist)          ? cntl_rw[2:0]:
                                             next_rw[2:0];


////////////////////////////////////   ////////////////////////////////////
//  NEXT ALGR
////////////////////////////////////   ////////////////////////////////////

   // msb
   assign cntl_msb                    =       start_in & cntl_out[34];    // done selection


   assign cntl_bisi                    =       mb_default_bisi | mb_user_bisi_rw_mode ? cntl_out[33] :
                                                                                        1'b1;

   // array
   assign cntl_array_sel[3:0]        =       (last_array | user_mode) ? 4'b1111:
                                                        cntl_out[32:29];    // array selection 
   // cmp
   assign cntl_cmp_sel[2:0]  = sel_cmp_pass ? {3'b111} :
                                              cntl_out[28:26];

   // data
   assign cntl_data_sel[1:0]          =   (bisi_mode | mb_user_data_mode)  ? 2'b11 :    cntl_out[25:24];    // data selection

   // address mix
   assign cntl_addr_mix               =   (bisi_mode | mb_user_addr_mode) ? 1'b1  : cntl_out[23];    // address mix
   assign addr_mix                    =   (bisi_mode | mb_user_addr_mode) ? 1'b0  : cntl_out[23];

   assign cntl_march_element[3:0]     =   sel_march_1_pass  ? 4'b1111:
                                                              cntl_out[22:19];    // march element


   assign cntl_algr[15:0] =       {cntl_msb,
                                   cntl_bisi,
                                   cntl_array_sel[3:0],
			           cntl_cmp_sel[2:0],
			           cntl_data_sel[1:0],
			           cntl_addr_mix,
			           cntl_march_element[3:0]};

   assign next_algr[15:0] = cout_addr ? cntl_algr[15:0] + 16'h1 : cntl_algr[15:0];         // mbist control


////////////////////////////////////   ////////////////////////////////////
//  NEXT ADDR
////////////////////////////////////   ////////////////////////////////////


   /////////////////////////
   // address engine
   /////////////////////////


   assign upaddr           =    march_0 | march_1 | march_2 | march_6 | march_7 | bisi_mode ;
                                

   assign march_element_pre[3:0]=next_algr[3:0];

   assign march_pre_0   = march_element_pre[3:0]==4'h0;
   assign march_pre_1   = march_element_pre[3:0]==4'h1;
   assign march_pre_2   = march_element_pre[3:0]==4'h2;
   assign march_pre_6   = march_element_pre[3:0]==4'h6;
   assign march_pre_7   = march_element_pre[3:0]==4'h7;

   assign upaddr_pre =     march_pre_0 | march_pre_1 | march_pre_2 | march_pre_6 | march_pre_7;


   assign incr_addr[8:0]  = mb_user_addr_mode ? user_incr_addr[8:0] :  9'b000000001;

   assign start_addr[8:0] = mb_user_addr_mode ? user_start_addr[8:0] : 9'b000000000;
   
   
//   assign next_addr_out[8:0] = cout_rw ? cntl_addr[8:0] + incr_addr[8:0] : cntl_addr[8:0];    // next address


   assign incred_addr[8:0] = cntl_addr[8:0] + incr_addr[8:0];


   assign overflow   = upaddr   ? ( cntl_addr[8:0] == stop_addr[8:0])  & (cntl_rw[2:0]==3'b111):
                                  (~cntl_addr[8:0] == start_addr[8:0]) & (cntl_rw[2:0]==3'b111);


//   assign next_addr[8:0]= overflow ? restart_addr[8:0] : next_addr_out[8:0];
  
   assign restart_addr[8:0] = upaddr_pre ? start_addr[8:0] : ~stop_addr[8:0];
      
   assign cout_addr =  overflow;


////////////////////////////////////   ////////////////////////////////////
//  NEXT RW
////////////////////////////////////   ////////////////////////////////////


   assign cntl_rw[2:0]                =   sel_rw_pass      ? 3'b111: 
                                                               cntl_out[ 2: 0];    // read write control

   assign next_rw[2:0] = cntl_rw[2:0]+3'b001 ;              
   
   assign cout_rw = &cntl_rw[2:0];     // carry over for rw 


////////////////////////////////////   ////////////////////////////////////
//  MBIST CONTROL SIGNAL
//  - mem_wr
////////////////////////////////////   ////////////////////////////////////


   assign one_cycle_march  =  march_0 | march_5 | march_7;
   assign five_cycle_march =  march_6 | march_8;
   assign two_cycle_march  = ~(one_cycle_march | five_cycle_march);


   /////////////////////////
   // membist write enable
   /////////////////////////


    assign mem_wr_pbi     = run3 & (
                               march_0  |
                               ((march_1 | march_2 | march_3 | march_4 ) & rw_1) |
                               (march_6 & (rw_0 | rw_1 | rw_4)) |
                               march_7 |
                               (march_8 & (rw_0 | rw_1 | rw_4))
                               );  

   assign mem_wr = bisi_wr_mode ? 1'b1 :
                   bisi_rd_mode ? 1'b0 :
                                  mem_wr_pbi;
   /////////////////////////
   // membist read enable
   /////////////////////////

                                            
   assign mem_rd_pbi         =     run3   &      ~mem_wr;  

   assign mem_rd= bisi_rd_mode ? 1'b1 : mem_rd_pbi;
   /////////////////////
   // membist address:
   ////////////////////

   assign cntl_addr[8:0]   = cntl_out[11:3];

   assign adj_addr          = (five_cycle_march & (rw_1 | rw_3)) ? {cntl_addr[8:1],~cntl_addr[0]}:
                                                                      cntl_addr[8:0] ;

   assign mem_addr1[8:0]    = upaddr   ?  adj_addr[8:0]:  ~adj_addr[8:0];


   /////////////////////
   // true data
   ////////////////////

   assign true_data_l     =    bisi_mode |
                             march_0   |
                             (march_1 & rw_0)   |
                             (march_2 & rw_1)   |
                             (march_3 & rw_0)   |
                             (march_4 & rw_1)   |
                             (march_5)   |
                             (march_6 & (rw_1 | rw_3 | rw_4))   |
                             (march_8 & (rw_0 | rw_2));

   assign true_data=~true_data_l;

   /////////////////////
   // membist data:
   ////////////////////

   assign data_pat_sel[7:0]        =     (mb_user_data_mode & bisi_mode)     ?   ~user_data[7:0]:
                                         (mb_user_data_mode)                 ?    user_data[7:0]:
                                         bisi_mode                           ?    8'hFF:              
                                         (cntl_data_sel[1:0] == 2'h0)        ?    8'hAA:
                                         (cntl_data_sel[1:0] == 2'h1)        ?    8'h99:
                                         (cntl_data_sel[1:0] == 2'h2)        ?    8'hCC:
                                                                                  8'h00;
   assign mem_data[7:0]         = true_data ? data_pat_sel[7:0] : ~data_pat_sel[7:0];


////////////////////////////////////   ////////////////////////////////////
//  STOP ADDR
////////////////////////////////////   ////////////////////////////////////


   assign stop_addr[8:0]  = mb_user_addr_mode ? user_stop_addr[8:0]  : 
                                                   //               8_7654_3210
                                                   array_01   ?  9'b1_1111_1111:  // ict
                                                   array_02   ?  9'b1_1111_1111:  // icd
                                                   array_03   ?  9'b0_0001_1111:  // icv
                                                   array_04   ?  9'b0_0011_1111:  // itb
                                                   array_05   ?  9'b1_1111_1111:  // dca
                                                   array_06   ?  9'b1_1111_1111:  // dta
                                                   array_07   ?  9'b0_0001_1111:  // dva
                                                   array_08   ?  9'b0_0111_1111:  // dtlb
                                                   array_09   ?  9'b0_0001_1111:  // cpq
                                                   array_10   ?  9'b0_0011_1111:  // stbcam
                                                   array_11   ?  9'b0_0011_1111:  // stbram
                                                   array_12   ?  9'b0_0111_1111:  // lru
                                                                 9'b1_1111_1111;


////////////////////////////////////   ////////////////////////////////////
//  ADDR MIX
////////////////////////////////////   ////////////////////////////////////


   assign mem_addr_mix0[8:0]   =   (array_06) ? { mem_addr1[8:7],mem_addr1[5:0],mem_addr1[6]} :	// DTA fixed
                                                  mem_addr1[8:0];


   assign mem_addr_mix1[8:0]   =   (array_01) ? { mem_addr1[2:0],mem_addr1[8:3]}              :	// ICT fixed circuit
                                   (array_02) ? { mem_addr1[2:0],mem_addr1[8:3]}              :	// ICD fixed circuit
                                   (array_03) ? { mem_addr1[8:5],mem_addr1[3:0],mem_addr1[4]} :	// ICV
                                   (array_04) ? { mem_addr1[8:6],mem_addr1[4:0],mem_addr1[5]} :	// ITLB
                                   (array_05) ? { mem_addr1[1:0],mem_addr1[8:2]}              :	// DCA fixed circuit
                                   (array_06) ? { mem_addr1[2:1],mem_addr1[8:3],mem_addr1[0]} :	// DTA fixed circuit
                                   (array_07) ? { mem_addr1[8:5],mem_addr1[3:0],mem_addr1[4]} :	// DVA
                                   (array_08) ? { mem_addr1[8:7],mem_addr1[5:0],mem_addr1[6]} :	// DTLB
                                   (array_09) ? { mem_addr1[8:5],mem_addr1[0],mem_addr1[4:1]} :	// CPQ
                                   (array_10) ? { mem_addr1[8:6],mem_addr1[2:0],mem_addr1[5:3]} :	// STBCAM
                                   (array_11) ? { mem_addr1[8:6],mem_addr1[1:0],mem_addr1[5:2]} :	// STBRAM
                                   (array_12) ? { mem_addr1[8:5],mem_addr1[0],mem_addr1[4:1]} :	// LRU
                                                            mem_addr1[8:0];


    assign mem_addr[8:0] = addr_mix ? mem_addr_mix1[8:0] : mem_addr_mix0[8:0];

////////////////////////////////////   ////////////////////////////////////
//  SEQ selection
////////////////////////////////////   ////////////////////////////////////

    // array

    assign array_01     = array_sel[3:0]==4'h0 & (~cambist & run3);
    assign array_02     = array_sel[3:0]==4'h1 & (~cambist & run3);
    assign array_03     = array_sel[3:0]==4'h2 & (~cambist & run3);
    assign array_04     = array_sel[3:0]==4'h3 & (~cambist & run3);
    assign array_05     = array_sel[3:0]==4'h4 & (~cambist & run3);
    assign array_06     = array_sel[3:0]==4'h5 & (~cambist & run3);
    assign array_07     = array_sel[3:0]==4'h6 & (~cambist & run3);
    assign array_08     = array_sel[3:0]==4'h7 & (~cambist & run3);
    assign array_09     = array_sel[3:0]==4'h8 & (~cambist & run3);
    assign array_10     = array_sel[3:0]==4'h9 & (~cambist & run3);
    assign array_11     = array_sel[3:0]==4'hA & (~cambist & run3);
    assign array_12     = array_sel[3:0]==4'hB & (~cambist & run3);


   assign last_array= array_12;

   // cmp
   assign cmp_0      = cmp_sel[2:0]==3'b000;
   assign cmp_1      = cmp_sel[2:0]==3'b001;
   assign cmp_2      = cmp_sel[2:0]==3'b010;
   assign cmp_3      = cmp_sel[2:0]==3'b011;
//   assign cmp_4      = cmp_sel[2:0]==3'b100;
//   assign cmp_5      = cmp_sel[2:0]==3'b101;
//   assign cmp_6      = cmp_sel[2:0]==3'b110;
   assign cmp_7      = cmp_sel[2:0]==3'b111;

   // march

   assign march_0   = (march_element[3:0]==4'h0);
   assign march_1   = (march_element[3:0]==4'h1);
   assign march_2   = (march_element[3:0]==4'h2);
   assign march_3   = (march_element[3:0]==4'h3);
   assign march_4   = (march_element[3:0]==4'h4);
   assign march_5   = (march_element[3:0]==4'h5);
   assign march_6   = (march_element[3:0]==4'h6);
   assign march_7   = (march_element[3:0]==4'h7);
   assign march_8   = (march_element[3:0]==4'h8);

   // rw

   assign rw_0           =  (rw[2:0]==3'b000);
   assign rw_1           =  (rw[2:0]==3'b001);
   assign rw_2           =  (rw[2:0]==3'b010);
   assign rw_3           =  (rw[2:0]==3'b011);
   assign rw_4           =  (rw[2:0]==3'b100);
//   assign rw_5           =  (rw[2:0]==3'b101);
//   assign rw_6           =  (rw[2:0]==3'b110);
//   assign rw_7           =  (rw[2:0]==3'b111);


////////////////////////////////////   ////////////////////////////////////
//  SEQ logic
////////////////////////////////////   ////////////////////////////////////
   

   // cam sel logic

  assign cam_sel_cntl_out[1:0]=cam_out[25:24];


   assign cam_sel[1:0]=   mb_user_cam_mode   ?  user_cam_sel[1:0] :
                                                cam_sel_cntl_out[1:0];


  // ctest logic

  assign ctest_cntl_out[3:0]=cam_out[23:20];


  spc_mb0_ctlmsff_ctl_macro__width_4 ctest_reg  (
               .scan_in(ctest_reg_scanin),
               .scan_out(ctest_reg_scanout),
               .l1clk    ( l1clk_pm1	   ),
               .din      ( ctest[3:0]      ),
               .dout     ( ctest_out[3:0] ),
  .siclk(siclk),
  .soclk(soclk));

   assign ctest[3:0]=(&ctest_cntl_out[3:0]) ? ctest_out[3:0] :
                          mb_user_cam_mode      ? user_cam_test_sel[3:0] :
                                                  ctest_cntl_out[3:0];


  // cseq


  assign cseq_cntl_out[2:0]=cam_out[19:17];


  spc_mb0_ctlmsff_ctl_macro__width_3 cseq_reg  (
               .scan_in(cseq_reg_scanin),
               .scan_out(cseq_reg_scanout),
               .l1clk    ( l1clk_pm1	  ),
               .din      ( cseq[2:0]      ),
               .dout     ( cseq_out[2:0] ),
  .siclk(siclk),
  .soclk(soclk));

   assign cseq[2:0]=(&cseq_cntl_out[2:0]) ? cseq_out[2:0] :
                                            cseq_cntl_out[2:0];


   assign crw[1:0]=cam_out[1:0];


   // array logic

  assign array_sel_cntl_out[3:0]=cntl_out[32:29];


  spc_mb0_ctlmsff_ctl_macro__width_4 array_sel_reg  (
               .scan_in(array_sel_reg_scanin),
               .scan_out(array_sel_reg_scanout),
               .l1clk    ( l1clk_pm1	       ),
               .din      ( array_sel[3:0]      ),
               .dout     ( array_sel_out[3:0] ),
  .siclk(siclk),
  .soclk(soclk));

   assign array_sel[3:0]=(&array_sel_cntl_out[3:0]) ? array_sel_out[3:0] :
                          user_mode                 ? user_array[3:0] :
                                                      array_sel_cntl_out[3:0];


   // cmp logic

   assign cmp_sel_cntl_out[2:0] = cntl_out[28:26];

   spc_mb0_ctlmsff_ctl_macro__width_3 cmp_sel_reg  (
               .scan_in(cmp_sel_reg_scanin),
               .scan_out(cmp_sel_reg_scanout),
               .l1clk    ( l1clk_pm1	     ),
               .din      ( cmp_sel[2:0]      ),
               .dout     ( cmp_sel_out[2:0] ),
  .siclk(siclk),
  .soclk(soclk));

   assign cmp_sel[2:0]=  (&cmp_sel_cntl_out[2:0] & ~array_02) | bisi_wr_mode ? cmp_sel_out[2:0] :
                               mb_user_cmpselinc_hold         ? user_cmpsel[2:0] :
                                                                cmp_sel_cntl_out[2:0];
   

 // march logic                                          

  assign march_element_cntl_out[3:0]=cntl_out[22:19];


  spc_mb0_ctlmsff_ctl_macro__width_4 marche_element_reg  (
               .scan_in(marche_element_reg_scanin),
               .scan_out(marche_element_reg_scanout),
               .l1clk    ( l1clk_pm1	      ),
               .din      ( march_element[3:0] ),
               .dout     ( march_element_out ),
  .siclk(siclk),
  .soclk(soclk));

   assign march_element[3:0]=(&march_element_cntl_out[3:0]) ? march_element_out[3:0] :
                                                              march_element_cntl_out[3:0];


   // rw
   assign rw[2:0]=cntl_out[2:0];


//////////////////////////////////////////////////////////////////
// SEL_PASS LOGIC
//////////////////////////////////////////////////////////////////
   // sel_ctest_pass
   assign sel_ctest_pass=(cam_array_0 & ctest13) |
                         (cam_array_1 & ctest13) |
                         (cam_array_2 & ctest10) |
                         (cam_clear   & ctest00) ;


   // sel_cseq_pass 

   assign sel_cseq_pass=(tlb_cam_gen_test   & cseq1)  |  // cseq0, cseq1
                        (tlb_cam_dmap_test  & cseq2)  |  // cseq0, cseq1, cseq2
                        (tlb_cam_dmap2_test & cseq2) | // cseq0, cseq1, cseq2
                        (tlb_cam_walk1_test & cseq2) |  // cseq0, cseq1, cseq2
                        (tlb_cam_mhit_test  & cseq1) |  // cseq0, cseq1, cseq2
                        (tlb_cam_rpwr_test  & cseq4) |  // cseq0, cseq1, cseq2
                        (stb_cam_gen_test   & cseq1) |  // cseq0, cseq1, cseq2
                        (stb_cam_pwk1_test  & cseq1) |  // cseq0, cseq1, cseq2
                        (stb_cam_bwk1_test  & cseq1) |  // cseq0, cseq1, cseq2
                        (stb_cam_bwk2_test  & cseq1) |  // cseq0, cseq1, cseq2
                        (stb_cam_mhit_test  & cseq1) |  // cseq0, cseq1, cseq2
                        (cam_clear  & cseq1) ;  // cseq0, cseq1, cseq2


   // sel_crw_pass 

   assign sel_crw_pass= (tlb_cam_gen_test & cseq0 & crw0) |  
                        (tlb_cam_dmap_test  & (cseq0 | cseq1 | cseq2) & crw0) | 
                        (tlb_cam_dmap2_test & (cseq0 | cseq2 ) & crw0) |
                        (tlb_cam_dmap2_test & (cseq1 ) & crw3) |
                        (tlb_cam_walk1_test  & crw0) |
                        (tlb_cam_mhit_test  & cseq0 & crw0) |
                        (tlb_cam_mhit_test  & cseq1 & crw3) |
//                        (tlb_cam_mhit_test  & cseq2 & crw0) |
                        (tlb_cam_rpwr_test  & cseq0 & crw0) | 
                        (tlb_cam_rpwr_test  & cseq1 & crw1) | 
                        (tlb_cam_rpwr_test  & cseq2 & crw0) | 
                        (tlb_cam_rpwr_test  & cseq3 & crw1) | 
                        (tlb_cam_rpwr_test  & cseq4 & crw3) |
                        (stb_cam_gen_test   & cseq0 & crw0) | 
                        (stb_cam_gen_test   & ~ctest09  & cseq1 & crw2) |
                        (stb_cam_gen_test   & ctest09  & cseq1 & crw1) |
                        (stb_cam_pwk1_test   & cseq0 & crw0) |
                        (stb_cam_pwk1_test   & cseq1 & crw0) | 
                        (stb_cam_bwk1_test   & cseq0 & crw0) |
                        (stb_cam_bwk1_test   & cseq1 & crw0) | 
                        (stb_cam_bwk2_test   & cseq0 & crw0) |
                        (stb_cam_bwk2_test   & cseq1 & crw2) |
                        (stb_cam_mhit_test   & cseq0) | 
//                        (stb_cam_mhit_test   & cseq2 & crw0) | 
                        (stb_cam_mhit_test   & cseq1 & cseq3) |
                        (cam_clear   & (cseq0 | cseq1)) ; 


   // march
   assign sel_march_1_pass = bisi_mode | (mb_ten_n_mode & march_5) | march_8;
 
   // cmp

   assign bisi_wr_mode = mb_default_bisi | mb_user_bisi_rw_mode ?  ~cntl_bisi & run3 :
                                                                   mb_user_bisi_wr_mode & run3;
                         
   assign bisi_rd_mode  =mb_default_bisi | mb_user_bisi_rw_mode ?  cntl_bisi & run3 :
                                                                   mb_user_bisi_rd_mode & run3;
                          

   assign sel_cmp_pass= (mb_user_cmpselinc_hold | bisi_wr_mode) |
                             (array_01 & cmp_0) |  // 
  	                         (array_02 & cmp_7) |  // icd 8
                             (array_03 & cmp_0) |  // 
                             (array_04 & cmp_3) |  // itb 4
                             (array_05 & cmp_1) |  // dca 2
                             (array_06 & cmp_0) |  // 
                             (array_07 & cmp_0) |  // 
                             (array_08 & cmp_1) |  // dtb 2
  	                         (array_09 & cmp_1) |  // cpq 2
                             (array_10 & cmp_0) |  // 
                             (array_11 & cmp_2) |  // stbram 3
                             (array_12 & cmp_0) ;


   // rw
   assign sel_rw_1_pass = bisi_mode | one_cycle_march ;

   assign sel_rw_2_pass = two_cycle_march;
   assign sel_rw_5_pass = five_cycle_march;

   assign sel_rw_pass = (run3 & sel_rw_1_pass & rw_0) |
                        (run3 & sel_rw_2_pass & rw_1) |
                        (run3 & sel_rw_5_pass & rw_4) ;


////////////////////////////////////   ////////////////////////////////////
//  membist control assignment
////////////////////////////////////   ////////////////////////////////////

			       
   assign mb_cmp_sel[2:0] = cmp_sel[2:0];
 
   assign mb_addr[8:0]=cambist ? {2'b00,tlb_stb_addr[6:0]}: mem_addr[8:0];  // ??
   assign mb_write_data[7:0]= cambist ? cam_data[7:0] : mem_data[7:0];


   // only one array read signal should be active   

   assign  mb_array_01_rd = array_01  & mem_rd;
   assign  mb_array_02_rd = array_02  & mem_rd;
   assign  mb_array_03_rd = array_03  & mem_rd;
   assign  mb_array_04_rd = (array_04  & mem_rd) | (cam_array_1 & cam_rd_en);
   assign  mb_array_05_rd = array_05  & mem_rd;
   assign  mb_array_06_rd = array_06  & mem_rd;
   assign  mb_array_07_rd = array_07  & mem_rd;
   assign  mb_array_08_rd = (array_08  & mem_rd) | (cam_array_0 & cam_rd_en);
   assign  mb_array_09_rd = array_09  & mem_rd;
   assign  mb_array_10_rd= array_10  & mem_rd;
   assign  mb_array_11_rd= array_11  & mem_rd;
   assign  mb_array_12_rd= array_12  & mem_rd;

   // only one array write signal should be active

   assign  mb_array_01_wr  = array_01  & mem_wr;
   assign  mb_array_02_wr  = array_02  & mem_wr;
   assign  mb_array_03_wr  = array_03  & mem_wr;
   assign  mb_array_04_wr  =(array_04  & mem_wr) |  ((cam_array_1 | cam_clear) & cam_wr_en);
   assign  mb_array_05_wr  = array_05  & mem_wr;
   assign  mb_array_06_wr  = array_06  & mem_wr;
   assign  mb_array_07_wr  = array_07  & mem_wr;
   assign  mb_array_08_wr  =(array_08  & mem_wr) |  ((cam_array_0 | cam_clear) & cam_wr_en);
   assign  mb_array_09_wr  = array_09  & mem_wr;
   assign  mb_array_10_wr =(array_10 & mem_wr)   |  ((cam_array_2 | cam_clear) & cam_wr_en);
   assign  mb_array_11_wr = array_11 & mem_wr;
   assign  mb_array_12_wr = array_12 & mem_wr;


   assign mb_run = run;


   ////////////////////////////////////   ////////////////////////////////////
   //  DONE LOGIC
   ////////////////////////////////////   ////////////////////////////////////

   
  spc_mb0_ctlmsff_ctl_macro__width_1  msb_latch  (
               .scan_in(msb_latch_scanin),
               .scan_out(msb_latch_scanout),
               .l1clk    ( l1clk_pm1	    ),
               .din      ( msb_in    ),
               .dout     ( msb_out  ),
  .siclk(siclk),
  .soclk(soclk));
   
   assign msb_in= (~start_in ) | (mb_user_loop_mode & mb_done) ? 1'b0 :
                   (cntl_msb | cam_msb)                        ? 1'b1 :
                                                                 msb_out;

   assign stop_engine_l     =  ~start_in ? 1'b0 :
                               mb_user_cam_mode                 ? cam_msb :
                               mb_user_loop_mode                ? cntl_msb :
                               (mb_user_ram_mode | bisi_mode)   ? cntl_msb :
                                                                  cam_msb;

   assign mb_done=  ~start_in ? 1'b0 :
                     bisi_mode | mb_user_loop_mode | mb_user_ram_mode ? msb_out & (done_delay[4:0]==5'b11110): 
                                       cam_msb & (done_delay[4:0]==5'b11110) ;
 
  assign  run3   = &done_delay[4:1] & ~stop_engine_l & start_in;


   spc_mb0_ctlmsff_ctl_macro__width_1 run3_transition_reg  (
                  .scan_in(run3_transition_reg_scanin),
                  .scan_out(run3_transition_reg_scanout),
                  .l1clk    ( l1clk_pm1	          ),
                  .din      ( run3  ),
                  .dout     ( run3_out    ),
  .siclk(siclk),
  .soclk(soclk));

   assign run3_transition = run3 & ~run3_out;

   spc_mb0_ctlmsff_ctl_macro__width_5 done_delay_reg  (
                  .scan_in(done_delay_reg_scanin),
                  .scan_out(done_delay_reg_scanout),
                  .l1clk    ( l1clk_pm1	          ),
                  .din      ( done_delay_in[4:0]  ),
                  .dout     ( done_delay[4:0]    ),
  .siclk(siclk),
  .soclk(soclk));


   assign done_delay_in[4:0] = ~start_in    ?  5'b00000 :
                               run3         ?  5'b11111 :
                               mb_done      ?  5'b11110 :
                              (run & ~run3) ? done_delay[4:0] + 5'b00001 : 
                                                   5'b00000;


////////////////////////////////////   ////////////////////////////////////
//  FAIL LOGIC
////////////////////////////////////   ////////////////////////////////////


assign   dca_fail     = run3_transition ? 1'b0 : (lsu_mbi_dca_fail     | lsu_mbi_dca_fail_sticky);
assign	 dta_fail     = run3_transition ? 1'b0 : (lsu_mbi_dta_fail     | lsu_mbi_dta_fail_sticky);
assign	 dva_fail     = run3_transition ? 1'b0 : (lsu_mbi_dva_fail     | lsu_mbi_dva_fail_sticky);
assign	 lru_fail     = run3_transition ? 1'b0 : (lsu_mbi_lru_fail     | lsu_mbi_lru_fail_sticky);
assign	 dtb_fail     = run3_transition ? 1'b0 : (lsu_mbi_dtb_fail     | lsu_mbi_dtb_fail_sticky);
assign	 stb_cam_fail = run3_transition ? 1'b0 : (lsu_mbi_stb_cam_fail | lsu_mbi_stb_cam_fail_sticky);
assign	 stb_ram_fail = run3_transition ? 1'b0 : (lsu_mbi_stb_ram_fail | lsu_mbi_stb_ram_fail_sticky);
assign	 cpq_fail     = run3_transition ? 1'b0 : (lsu_mbi_cpq_fail     | lsu_mbi_cpq_fail_sticky);
assign	 ict_fail     = run3_transition ? 1'b0 : (ftu_mbi_ict_fail     | ftu_mbi_ict_fail_sticky);
assign	 icd_fail     = run3_transition ? 1'b0 : (ftu_mbi_icd_fail     | ftu_mbi_icd_fail_sticky);
assign	 itb_fail     = run3_transition ? 1'b0 : (ftu_mbi_itb_fail     | ftu_mbi_itb_fail_sticky);
assign	 icv_fail     = run3_transition ? 1'b0 : (ftu_mbi_icv_fail     | ftu_mbi_icv_fail_sticky);

assign	 cbist_itlb_fail     = run3_transition ? 1'b0 : (cbist_itlb_cam_fail     | cbist_itlb_cam_fail_sticky);
assign	 cbist_dtlb_fail     = run3_transition ? 1'b0 : (cbist_dtlb_cam_fail     | cbist_dtlb_cam_fail_sticky);
assign	 cbist_stb_fail      = run3_transition ? 1'b0 : (cbist_stb_cam_fail      | cbist_stb_cam_fail_sticky);


spc_mb0_ctlmsff_ctl_macro__width_15		fail_reg		 (
 .scan_in(fail_reg_scanin),
 .scan_out(fail_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ({dca_fail                       ,
	 dta_fail                       ,
	 dva_fail                       ,
	 lru_fail                       ,
	 dtb_fail                       ,
	 stb_cam_fail                   ,
	 stb_ram_fail                   ,
	 cpq_fail                       ,
	 ict_fail                       ,
	 icd_fail                       ,
	 itb_fail                       ,
	 icv_fail,
     cbist_itlb_fail,
     cbist_dtlb_fail,
     cbist_stb_fail}			),
 .dout ({lsu_mbi_dca_fail_sticky    	,
	 lsu_mbi_dta_fail_sticky        ,
	 lsu_mbi_dva_fail_sticky        ,
	 lsu_mbi_lru_fail_sticky        ,
	 lsu_mbi_dtb_fail_sticky        ,
	 lsu_mbi_stb_cam_fail_sticky    ,
	 lsu_mbi_stb_ram_fail_sticky    ,
	 lsu_mbi_cpq_fail_sticky        ,
	 ftu_mbi_ict_fail_sticky        ,
	 ftu_mbi_icd_fail_sticky        ,
	 ftu_mbi_itb_fail_sticky        ,
	 ftu_mbi_icv_fail_sticky,
     cbist_itlb_cam_fail_sticky,
     cbist_dtlb_cam_fail_sticky,
     cbist_stb_cam_fail_sticky}	),
  .siclk(siclk),
  .soclk(soclk));
   

assign mbist_fail_array =  lsu_mbi_dca_fail |
                           lsu_mbi_dta_fail |
                           lsu_mbi_dva_fail |
                           lsu_mbi_lru_fail |
                           lsu_mbi_dtb_fail |
                           lsu_mbi_stb_cam_fail |
                           lsu_mbi_stb_ram_fail |
                           lsu_mbi_cpq_fail |
                           ftu_mbi_ict_fail |
                           ftu_mbi_icd_fail |
                           ftu_mbi_itb_fail |
                           ftu_mbi_icv_fail |
                           cbist_itlb_cam_fail |
                           cbist_dtlb_cam_fail |
                           cbist_stb_cam_fail  ;


assign mbist_fail_sticky = lsu_mbi_dca_fail_sticky |
			   lsu_mbi_dta_fail_sticky |
			   lsu_mbi_dva_fail_sticky |
			   lsu_mbi_lru_fail_sticky |
			   lsu_mbi_dtb_fail_sticky |
			   lsu_mbi_stb_cam_fail_sticky |
			   lsu_mbi_stb_ram_fail_sticky |
			   lsu_mbi_cpq_fail_sticky |
			   ftu_mbi_ict_fail_sticky |
			   ftu_mbi_icd_fail_sticky |
			   ftu_mbi_itb_fail_sticky |
			   ftu_mbi_icv_fail_sticky |
               cbist_itlb_cam_fail_sticky |
               cbist_dtlb_cam_fail_sticky |
               cbist_stb_cam_fail_sticky  ;


assign valid_fail=run3 | (stop_engine_l & ~mb_done);
assign mb_fail = mb_done ? (mbist_fail_sticky) : (mbist_fail_array & valid_fail);


//////////////////////////////////////////////////////////////////
// OUTPUT FLOP:
//////////////////////////////////////////////////////////////////

// mb_done


spc_mb0_ctlmsff_ctl_macro__width_1  out_mb_tcu_done_reg  (
               .scan_in(out_mb_tcu_done_reg_scanin),
               .scan_out(out_mb_tcu_done_reg_scanout),
               .l1clk    ( l1clk_pm1     ),
               .din      ( mb_done       ),
               .dout     ( mb_done_out  ),
  .siclk(siclk),
  .soclk(soclk));


// mb_fail


spc_mb0_ctlmsff_ctl_macro__width_1 out_mb_tcu_fail_reg  (
               .scan_in(out_mb_tcu_fail_reg_scanin),
               .scan_out(out_mb_tcu_fail_reg_scanout),
               .l1clk    ( l1clk_pm1     ),
               .din      ( mb_fail       ),
               .dout     ( mb_fail_out  ),
  .siclk(siclk),
  .soclk(soclk));


// out cmpsel


spc_mb0_ctlmsff_ctl_macro__width_3		out_cmp_sel_reg		 (
 .scan_in(out_cmp_sel_reg_scanin),
 .scan_out(out_cmp_sel_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_cmp_sel[2:0]		),
 .dout ( mb_cmpsel_out[2:0]		),
  .siclk(siclk),
  .soclk(soclk));


// thes are all the output flops to arrays
// for the following signals:
//
// - run
// - data
// - address


spc_mb0_ctlmsff_ctl_macro__width_1		out_run_mb_arrays_reg		 (
 .scan_in(out_run_mb_arrays_reg_scanin),
 .scan_out(out_run_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_run				),
 .dout ( mb_run_out			),
  .siclk(siclk),
  .soclk(soclk));

// data 8 bits

spc_mb0_ctlmsff_ctl_macro__width_8		out_data_mb_arrays_reg		 (
 .scan_in(out_data_mb_arrays_reg_scanin),
 .scan_out(out_data_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_write_data[7:0]		),
 .dout ( mb_write_data_out[7:0]		),
  .siclk(siclk),
  .soclk(soclk));


// address 16 bits


spc_mb0_ctlmsff_ctl_macro__width_9		out_addr_mb_arrays_reg		 (
 .scan_in(out_addr_mb_arrays_reg_scanin),
 .scan_out(out_addr_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_addr[8:0]			),
 .dout ( mb_addr_out[8:0]		),
  .siclk(siclk),
  .soclk(soclk));


//
// write enable

spc_mb0_ctlmsff_ctl_macro__width_12		out_wr_mb_arrays_reg		 (
 .scan_in(out_wr_mb_arrays_reg_scanin),
 .scan_out(out_wr_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( {
          mb_array_01_wr,
          mb_array_02_wr,
          mb_array_03_wr,
          mb_array_04_wr,
          mb_array_05_wr,
          mb_array_06_wr,
          mb_array_07_wr,
          mb_array_08_wr,
          mb_array_09_wr,
          mb_array_10_wr,
          mb_array_11_wr,
          mb_array_12_wr
          }		),
 .dout ({ 
          mb_array_01_wr_out,
          mb_array_02_wr_out,
          mb_array_03_wr_out,
          mb_array_04_wr_out,
          mb_array_05_wr_out,
          mb_array_06_wr_out,
          mb_array_07_wr_out,
          mb_array_08_wr_out,
          mb_array_09_wr_out,
          mb_array_10_wr_out,
          mb_array_11_wr_out,
          mb_array_12_wr_out
        }		),
  .siclk(siclk),
  .soclk(soclk));


// read enable
 
spc_mb0_ctlmsff_ctl_macro__width_12		out_rd_mb_arrays_reg		 (
 .scan_in(out_rd_mb_arrays_reg_scanin),
 .scan_out(out_rd_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( {
          mb_array_01_rd,
          mb_array_02_rd,
          mb_array_03_rd,
          mb_array_04_rd,
          mb_array_05_rd,
          mb_array_06_rd,
          mb_array_07_rd,
          mb_array_08_rd,
          mb_array_09_rd,
          mb_array_10_rd,
          mb_array_11_rd,
          mb_array_12_rd
          }		),
 .dout ({ 
          mb_array_01_rd_out,
          mb_array_02_rd_out,
          mb_array_03_rd_out,
          mb_array_04_rd_out,
          mb_array_05_rd_out,
          mb_array_06_rd_out,
          mb_array_07_rd_out,
          mb_array_08_rd_out,
          mb_array_09_rd_out,
          mb_array_10_rd_out,
          mb_array_11_rd_out,
          mb_array_12_rd_out
        }		),
  .siclk(siclk),
  .soclk(soclk));

// merge fail and done signals:

   spc_mb0_ctlmsff_ctl_macro__width_3 merged_fail  (
                  .scan_in(merged_fail_scanin),
                  .scan_out(merged_fail_scanout),
                  .l1clk    ( l1clk_pm1                                  ),
  	          .din      ( {mb1_mb0_fail,mb2_mb0_fail,mb_fail_merged} ),
  		  .dout     ( {mb1_fail    ,mb2_fail    ,mb0_mbist_fail} ),
  .siclk(siclk),
  .soclk(soclk));

   spc_mb0_ctlmsff_ctl_macro__width_3 merged_done  (
                  .scan_in(merged_done_scanin),
                  .scan_out(merged_done_scanout),
                  .l1clk    ( l1clk_pm1                                  ),
  	          .din      ( {mb1_mb0_done,mb2_mb0_done,mb_done_merged} ),
  		  .dout     ( {mb1_done    ,mb2_done    ,mb0_done}       ),
  .siclk(siclk),
  .soclk(soclk));


   assign mb_fail_merged=mb1_fail | mb2_fail | mb0_fail;

   assign mb_done_merged= user_mode ? (mb1_done | mb2_done | mb_done_out) : (mb1_done & mb2_done & mb_done_out);


// port name re-assignment


   assign mb0_run             =mb_run_out;
   assign mb0_write_data[7:0] =mb_write_data_out[7:0];
   assign mb0_addr[15:0]      ={7'b0000000,mb_addr_out[8:0]};
   assign mb0_cmpsel[2:0]     =mb_cmpsel_out[2:0];
   assign mb0_fail           =mb_fail_out;
//   assign mb0_done         =mb_done_out;

   assign mb0_ict_write_en   =mb_array_01_wr_out;
   assign mb0_icd_write_en   =mb_array_02_wr_out;
   assign mb0_icv_write_en   =mb_array_03_wr_out;
   assign mb0_itb_write_en   =mb_array_04_wr_out;
   assign mb0_dca_write_en   =mb_array_05_wr_out;
   assign mb0_dta_write_en   =mb_array_06_wr_out;
   assign mb0_dva_write_en   =mb_array_07_wr_out;
   assign mb0_dtb_write_en  =mb_array_08_wr_out;
   assign mb0_cpq_write_en   =mb_array_09_wr_out;
   assign mb0_stb_cam_write_en=mb_array_10_wr_out;
   assign mb0_stb_ram_write_en=mb_array_11_wr_out;
   assign mb0_lru_write_en   =mb_array_12_wr_out;

   assign mb0_ict_read_en   =mb_array_01_rd_out;
   assign mb0_icd_read_en   =mb_array_02_rd_out;
   assign mb0_icv_read_en   =mb_array_03_rd_out;
   assign mb0_itb_read_en   =mb_array_04_rd_out;
   assign mb0_dca_read_en   =mb_array_05_rd_out;
   assign mb0_dta_read_en   =mb_array_06_rd_out;
   assign mb0_dva_read_en   =mb_array_07_rd_out;
   assign mb0_dtb_read_en  =mb_array_08_rd_out;
   assign mb0_cpq_read_en   =mb_array_09_rd_out;
   assign mb0_stb_cam_read_en=mb_array_10_rd_out;
   assign mb0_stb_ram_read_en=mb_array_11_rd_out;
   assign mb0_lru_read_en   =mb_array_12_rd_out;


// spare gates:


spc_mb0_ctlspare_ctl_macro__num_6 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 


// /////////////////////////////////////////////////////////////////////////////

// /////////////////////////////////////////////////////////////////////////////

// fixscan start:
assign pmen_scanin               = scan_in                  ;
assign array_usr_reg_scanin      = pmen_scanout             ;
assign user_addr_mode_reg_scanin = array_usr_reg_scanout    ;
assign user_start_addr_reg_scanin = user_addr_mode_reg_scanout;
assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout;
assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout;
assign user_data_mode_reg_scanin = user_incr_addr_reg_scanout;
assign user_data_reg_scanin      = user_data_mode_reg_scanout;
assign user_cmpselinc_hold_reg_scanin = user_data_reg_scanout    ;
assign user_cmpsel_reg_scanin    = user_cmpselinc_hold_reg_scanout;
assign user_loop_mode_reg_scanin = user_cmpsel_reg_scanout  ;
assign ten_n_mode_reg_scanin     = user_loop_mode_reg_scanout;
assign user_cam_mode_reg_scanin  = ten_n_mode_reg_scanout   ;
assign user_cam_select_reg_scanin = user_cam_mode_reg_scanout;
assign user_cam_test_select_reg_scanin = user_cam_select_reg_scanout;
assign user_bisi_wr_mode_reg_scanin = user_cam_test_select_reg_scanout;
assign user_bisi_rd_mode_reg_scanin = user_bisi_wr_mode_reg_scanout;
assign input_signals_reg_scanin  = user_bisi_rd_mode_reg_scanout;
assign mb_enable_reg_scanin      = input_signals_reg_scanout;
assign config_reg_scanin         = mb_enable_reg_scanout    ;
assign loop_again_reg_scanin     = config_reg_scanout       ;
assign cambist_delay_reg_scanin  = loop_again_reg_scanout   ;
assign cam_cntl_reg_scanin       = cambist_delay_reg_scanout;
assign cam_shift_reg_scanin      = cam_cntl_reg_scanout     ;
assign cam_en_reg_scanin         = cam_shift_reg_scanout    ;
assign stb_hit_cmp_delay_scanin  = cam_en_reg_scanout       ;
assign stb_hit_cmp_mhit_l_delay_scanin = stb_hit_cmp_delay_scanout;
assign exp_stb_cam_hit_delay_scanin = stb_hit_cmp_mhit_l_delay_scanout;
assign exp_stb_hit_ptr_delay_scanin = exp_stb_cam_hit_delay_scanout;
assign exp_stb_mhit_delay_scanin = exp_stb_hit_ptr_delay_scanout;
assign exp_stb_ld_partial_raw_delay_scanin = exp_stb_mhit_delay_scanout;
assign cam_array_0_delay_scanin  = exp_stb_ld_partial_raw_delay_scanout;
assign cam_array_1_delay_scanin  = cam_array_0_delay_scanout;
assign cam_array_2_delay_scanin  = cam_array_1_delay_scanout;
assign cam_hit_cmp_delay_scanin  = cam_array_2_delay_scanout;
assign data_cmp_delay_scanin     = cam_hit_cmp_delay_scanout;
assign cam_valid_cmp_delay_scanin = data_cmp_delay_scanout   ;
assign cam_used_cmp_delay_scanin = cam_valid_cmp_delay_scanout;
assign exp_data_cmp_delay_scanin = cam_used_cmp_delay_scanout;
assign exp_valid_delay_scanin    = exp_data_cmp_delay_scanout;
assign exp_used_delay_scanin     = exp_valid_delay_scanout  ;
assign tlb_cntx0_cmp_delay_scanin = exp_used_delay_scanout   ;
assign exp_cam_hit_delay_scanin  = tlb_cntx0_cmp_delay_scanout;
assign exp_cntx0_hit_delay_scanin = exp_cam_hit_delay_scanout;
assign exp_mhit_delay_scanin     = exp_cntx0_hit_delay_scanout;
assign tlb_cam_intf_out_scanin   = exp_mhit_delay_scanout   ;
assign cntl_reg_scanin           = tlb_cam_intf_out_scanout ;
assign ctest_reg_scanin          = cntl_reg_scanout         ;
assign cseq_reg_scanin           = ctest_reg_scanout        ;
assign array_sel_reg_scanin      = cseq_reg_scanout         ;
assign cmp_sel_reg_scanin        = array_sel_reg_scanout    ;
assign marche_element_reg_scanin = cmp_sel_reg_scanout      ;
assign msb_latch_scanin          = marche_element_reg_scanout;
assign run3_transition_reg_scanin = msb_latch_scanout        ;
assign done_delay_reg_scanin     = run3_transition_reg_scanout;
assign fail_reg_scanin           = done_delay_reg_scanout   ;
assign out_mb_tcu_done_reg_scanin = fail_reg_scanout         ;
assign out_mb_tcu_fail_reg_scanin = out_mb_tcu_done_reg_scanout;
assign out_cmp_sel_reg_scanin    = out_mb_tcu_fail_reg_scanout;
assign out_run_mb_arrays_reg_scanin = out_cmp_sel_reg_scanout  ;
assign out_data_mb_arrays_reg_scanin = out_run_mb_arrays_reg_scanout;
assign out_addr_mb_arrays_reg_scanin = out_data_mb_arrays_reg_scanout;
assign out_wr_mb_arrays_reg_scanin = out_addr_mb_arrays_reg_scanout;
assign out_rd_mb_arrays_reg_scanin = out_wr_mb_arrays_reg_scanout;
assign merged_fail_scanin        = out_rd_mb_arrays_reg_scanout;
assign merged_done_scanin        = merged_fail_scanout      ;
assign spares_scanin             = merged_done_scanout      ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctll1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_27 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [26:0] fdin;
wire [25:0] so;

  input [26:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [26:0] dout;
  output scan_out;
assign fdin[26:0] = din[26:0];


dff #(27)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[26:0]),
.si({scan_in,so[25:0]}),
.so({so[25:0],scan_out}),
.q(dout[26:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_13 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [12:0] fdin;
wire [11:0] so;

  input [12:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [12:0] dout;
  output scan_out;
assign fdin[12:0] = din[12:0];


dff #(13)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[12:0]),
.si({scan_in,so[11:0]}),
.so({so[11:0],scan_out}),
.q(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_28 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [27:0] fdin;
wire [26:0] so;

  input [27:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [27:0] dout;
  output scan_out;
assign fdin[27:0] = din[27:0];


dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_15 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [14:0] fdin;
wire [13:0] so;

  input [14:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [14:0] dout;
  output scan_out;
assign fdin[14:0] = din[14:0];


dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[14:0]),
.si({scan_in,so[13:0]}),
.so({so[13:0],scan_out}),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb0_ctlmsff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module spc_mb0_ctlspare_ctl_macro__num_6 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));
assign scan_out = so_5;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spc_mb1_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module spc_mb1_ctl (
  scan_out, 
  mb1_done, 
  mb1_run, 
  mb1_addr, 
  mb1_cmpsel, 
  mb1_write_data, 
  mb1_tsa0_read_en, 
  mb1_tsa0_write_en, 
  mb1_tsa1_read_en, 
  mb1_tsa1_write_en, 
  mb1_tca_read_en, 
  mb1_tca_write_en, 
  mb1_scp0_read_en, 
  mb1_scp0_write_en, 
  mb1_scp1_read_en, 
  mb1_scp1_write_en, 
  mb1_mra0_read_en, 
  mb1_mra0_write_en, 
  mb1_mra1_read_en, 
  mb1_mra1_write_en, 
  mb1_mbist_fail, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_clk_stop, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  mb2_misc_pmen, 
  mbist_start, 
  mbist_bisi_mode, 
  mbist_user_mode, 
  mmu_mbi_mra0_fail, 
  mmu_mbi_mra1_fail, 
  mmu_mbi_scp0_fail, 
  mmu_mbi_scp1_fail, 
  tlu_mbi_tsa0_fail, 
  tlu_mbi_tsa1_fail, 
  tlu_mbi_tca_fail);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire pmen_scanin;
wire pmen_scanout;
wire start_in;
wire misc_pmen_;
wire pmem_unused;
wire clock_enable;
wire l1clk_pm1;
wire input_signals_reg_scanin;
wire input_signals_reg_scanout;
wire bisi_mode;
wire user_mode;
wire mb_enable_reg_scanin;
wire mb_enable_reg_scanout;
wire mb_enable;
wire mb_enable_out;
wire start;
wire config_reg_scanin;
wire config_reg_scanout;
wire [1:0] config_in;
wire [1:0] config_out;
wire start_transition;
wire end_transition;
wire reset_engine;
wire loop_again;
wire run;
wire loop_again_reg_scanin;
wire loop_again_reg_scanout;
wire stop_engine_l;
wire stop_engine_l_q;
wire mb_user_loop_mode;
wire array_usr_reg_scanin;
wire array_usr_reg_scanout;
wire [3:0] user_array_in;
wire [3:0] user_array;
wire user_addr_mode_reg_scanin;
wire user_addr_mode_reg_scanout;
wire user_addr_mode_in;
wire user_addr_mode;
wire user_start_addr_reg_scanin;
wire user_start_addr_reg_scanout;
wire [4:0] user_start_addr_in;
wire [4:0] user_start_addr;
wire user_stop_addr_reg_scanin;
wire user_stop_addr_reg_scanout;
wire [4:0] user_stop_addr_in;
wire [4:0] user_stop_addr;
wire user_incr_addr_reg_scanin;
wire user_incr_addr_reg_scanout;
wire [4:0] user_incr_addr_in;
wire [4:0] user_incr_addr;
wire user_data_mode_reg_scanin;
wire user_data_mode_reg_scanout;
wire user_data_mode_in;
wire user_data_mode;
wire user_data_reg_scanin;
wire user_data_reg_scanout;
wire [7:0] user_data_in;
wire [7:0] user_data;
wire user_cmpselinc_hold_reg_scanin;
wire user_cmpselinc_hold_reg_scanout;
wire user_cmpselinc_hold_in;
wire user_cmpselinc_hold;
wire user_cmpsel_reg_scanin;
wire user_cmpsel_reg_scanout;
wire [2:0] user_cmpsel_in;
wire [2:0] user_cmpsel;
wire user_loop_mode_reg_scanin;
wire user_loop_mode_reg_scanout;
wire user_loop_mode_in;
wire user_loop_mode;
wire ten_n_mode_reg_scanin;
wire ten_n_mode_reg_scanout;
wire ten_n_mode_in;
wire ten_n_mode;
wire user_bisi_wr_mode_reg_scanin;
wire user_bisi_wr_mode_reg_scanout;
wire user_bisi_wr_mode_in;
wire user_bisi_wr_mode;
wire user_bisi_rd_mode_reg_scanin;
wire user_bisi_rd_mode_reg_scanout;
wire user_bisi_rd_mode_in;
wire user_bisi_rd_mode;
wire mb_user_data_mode;
wire mb_user_addr_mode;
wire mb_user_cmpselinc_hold;
wire mb_ten_n_mode;
wire mb_user_bisi_wr_mode;
wire mb_user_bisi_rd_mode;
wire mb_user_bisi_rw_mode;
wire mb_default_bisi;
wire cntl_reg_scanin;
wire cntl_reg_scanout;
wire [34:0] cntl_in;
wire [34:0] cntl_out;
wire run3;
wire [15:0] cntl_algr;
wire [15:0] next_algr;
wire sel_nextaddr_reset;
wire sel_nextaddr_restart;
wire overflow;
wire sel_nextaddr_incred;
wire cout_rw;
wire sel_nextaddr_same;
wire [4:0] start_addr;
wire [4:0] restart_addr;
wire [4:0] incred_addr;
wire [4:0] cntl_addr;
wire [2:0] cntl_rw;
wire [2:0] next_rw;
wire cntl_msb;
wire cntl_bisi;
wire [3:0] cntl_array_sel;
wire last_array;
wire [2:0] cntl_cmp_sel;
wire sel_cmp_pass;
wire [1:0] cntl_data_sel;
wire cntl_addr_mix;
wire addr_mix;
wire [3:0] cntl_march_element;
wire sel_march_1_pass;
wire cout_addr;
wire upaddr;
wire march_0;
wire march_1;
wire march_2;
wire march_6;
wire march_7;
wire [3:0] march_element_pre;
wire march_pre_0;
wire march_pre_1;
wire march_pre_2;
wire march_pre_6;
wire march_pre_7;
wire upaddr_pre;
wire [4:0] incr_addr;
wire [4:0] stop_addr;
wire sel_rw_pass;
wire one_cycle_march;
wire march_5;
wire five_cycle_march;
wire march_8;
wire two_cycle_march;
wire mem_wr_pbi;
wire march_3;
wire march_4;
wire rw_1;
wire rw_0;
wire rw_4;
wire mem_wr;
wire bisi_wr_mode;
wire bisi_rd_mode;
wire mem_rd_pbi;
wire mem_rd;
wire [4:0] adj_addr;
wire rw_3;
wire [4:0] mem_addr1;
wire true_data_l;
wire rw_2;
wire true_data;
wire [7:0] data_pat_sel;
wire [7:0] mem_data;
wire array_0;
wire array_1;
wire array_2;
wire array_3;
wire array_4;
wire array_5;
wire array_6;
wire [4:0] mem_addr;
wire [3:0] array_sel;
wire cmp_2;
wire [2:0] cmp_sel;
wire cmp_3;
wire cmp_4;
wire [3:0] march_element;
wire [2:0] rw;
wire [3:0] array_sel_cntl_out;
wire array_sel_reg_scanin;
wire array_sel_reg_scanout;
wire [3:0] array_sel_out;
wire [2:0] cmp_sel_cntl_out;
wire cmp_sel_reg_scanin;
wire cmp_sel_reg_scanout;
wire [2:0] cmp_sel_out;
wire [3:0] march_element_cntl_out;
wire marche_element_reg_scanin;
wire marche_element_reg_scanout;
wire [3:0] march_element_out;
wire sel_rw_1_pass;
wire sel_rw_2_pass;
wire sel_rw_5_pass;
wire cmp_decoded_arrays;
wire [4:0] mb_cmp_sel;
wire [4:0] mb_addr;
wire [7:0] mb_write_data;
wire mb_array_0_rd;
wire mb_array_1_rd;
wire mb_array_2_rd;
wire mb_array_3_rd;
wire mb_array_4_rd;
wire mb_array_5_rd;
wire mb_array_6_rd;
wire mb_array_0_wr;
wire mb_array_1_wr;
wire mb_array_2_wr;
wire mb_array_3_wr;
wire mb_array_4_wr;
wire mb_array_5_wr;
wire mb_array_6_wr;
wire mb_run;
wire msb_latch_scanin;
wire msb_latch_scanout;
wire msb_in;
wire msb_out;
wire mb_done;
wire [4:0] done_delay;
wire run3_transition_reg_scanin;
wire run3_transition_reg_scanout;
wire run3_out;
wire run3_transition;
wire done_delay_reg_scanin;
wire done_delay_reg_scanout;
wire [4:0] done_delay_in;
wire mra0_fail;
wire mra0_fail_sticky;
wire mra1_fail;
wire mra1_fail_sticky;
wire scp0_fail;
wire scp0_fail_sticky;
wire scp1_fail;
wire scp1_fail_sticky;
wire tsa0_fail;
wire tsa0_fail_sticky;
wire tsa1_fail;
wire tsa1_fail_sticky;
wire tca_fail;
wire tca_fail_sticky;
wire fail_reg_scanin;
wire fail_reg_scanout;
wire mbist_fail_sticky;
wire mbist_fail_array;
wire valid_fail;
wire mb_fail;
wire out_mb_tcu_done_reg_scanin;
wire out_mb_tcu_done_reg_scanout;
wire mb_done_out;
wire out_mb_tcu_fail_reg_scanin;
wire out_mb_tcu_fail_reg_scanout;
wire mb_fail_out;
wire out_cmp_sel_reg_scanin;
wire out_cmp_sel_reg_scanout;
wire [4:0] mb_cmpsel_out;
wire out_run_mb_arrays_reg_scanin;
wire out_run_mb_arrays_reg_scanout;
wire mb_run_out;
wire out_data_mb_arrays_reg_scanin;
wire out_data_mb_arrays_reg_scanout;
wire [7:0] mb_write_data_out;
wire out_addr_mb_arrays_reg_scanin;
wire out_addr_mb_arrays_reg_scanout;
wire [4:0] mb_addr_out;
wire out_wr_mb_arrays_reg_scanin;
wire out_wr_mb_arrays_reg_scanout;
wire mb_array_0_wr_out;
wire mb_array_1_wr_out;
wire mb_array_2_wr_out;
wire mb_array_3_wr_out;
wire mb_array_4_wr_out;
wire mb_array_5_wr_out;
wire mb_array_6_wr_out;
wire out_rd_mb_arrays_reg_scanin;
wire out_rd_mb_arrays_reg_scanout;
wire mb_array_0_rd_out;
wire mb_array_1_rd_out;
wire mb_array_2_rd_out;
wire mb_array_3_rd_out;
wire mb_array_4_rd_out;
wire mb_array_5_rd_out;
wire mb_array_6_rd_out;
wire spares_scanin;
wire spares_scanout;


// /////////////////////////////////////////////////////////////////////////////
// Outputs
// /////////////////////////////////////////////////////////////////////////////

   output		scan_out;
   output		mb1_done;
   output		mb1_run;
   output [15:0]	mb1_addr;
   output [4:0]		mb1_cmpsel;
   output [7:0]		mb1_write_data;

   output		mb1_tsa0_read_en;
   output		mb1_tsa0_write_en;
   output		mb1_tsa1_read_en;
   output		mb1_tsa1_write_en;
   output		mb1_tca_read_en;
   output		mb1_tca_write_en;
   output		mb1_scp0_read_en;
   output		mb1_scp0_write_en;
   output		mb1_scp1_read_en;
   output		mb1_scp1_write_en;
   output		mb1_mra0_read_en;
   output		mb1_mra0_write_en;
   output		mb1_mra1_read_en;
   output		mb1_mra1_write_en;
   
   output		mb1_mbist_fail;

// /////////////////////////////////////////////////////////////////////////////
// Inputs
// /////////////////////////////////////////////////////////////////////////////

   input		l2clk;
   input		scan_in;
   input		tcu_pce_ov;             // scan signals
   input		tcu_clk_stop;
   input		tcu_aclk;
   input		tcu_bclk;
   input		tcu_scan_en;
   input		mb2_misc_pmen;		// Power management enable

   input		mbist_start;
   input		mbist_bisi_mode;
   input		mbist_user_mode;   

// membist fail

   input		mmu_mbi_mra0_fail;
   input		mmu_mbi_mra1_fail;
   input		mmu_mbi_scp0_fail;
   input		mmu_mbi_scp1_fail;
   input		tlu_mbi_tsa0_fail;
   input		tlu_mbi_tsa1_fail;
   input		tlu_mbi_tca_fail;


// /////////////////////////////////////////////////////////////////////////////
// Scan Renames
// /////////////////////////////////////////////////////////////////////////////

assign pce_ov = tcu_pce_ov;
assign stop   = tcu_clk_stop;
assign siclk  = tcu_aclk;
assign soclk  = tcu_bclk;
assign se     = tcu_scan_en;


////////////////////////////////////////////////////////////////////////////////
// Clock header
////////////////////////////////////////////////////////////////////////////////

spc_mb1_ctll1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk 		),
        .l1en   (1'b1		),
        .l1clk  (l1clk		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

spc_mb1_ctlmsff_ctl_macro__width_3 pmen  (
	.scan_in(pmen_scanin),
	.scan_out(pmen_scanout),
	.l1clk    ( l1clk					),	// Must be connected to a free running clock
	.din      ({mbist_start, ~mb2_misc_pmen , 1'b0}		),
	.dout     ({start_in   ,  misc_pmen_    , pmem_unused}	),
  .siclk(siclk),
  .soclk(soclk));


assign clock_enable	= start_in | mb1_done | mb1_run | mb1_mbist_fail | misc_pmen_;

spc_mb1_ctll1clkhdr_ctl_macro clkgen_pm1 (
        .l2clk  (l2clk 		),
        .l1en   (clock_enable	),
        .l1clk  (l1clk_pm1	),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


////////////////////////////////////   ////////////////////////////////////
//  START LOGIC
////////////////////////////////////   ////////////////////////////////////


// /////////////////////////////////////////////////////////////////////////////
//
// MBIST Config Register
//
// /////////////////////////////////////////////////////////////////////////////
//
// A low to high transition on mbist_start will reset and start the engine.  
// mbist_start must remain active high for the duration of MBIST.  
// If mbist_start deasserts the engine will stop but not reset.
// Once MBIST has completed mb0_done will assert and the fail status
// signals will be valid.  
// To run MBIST again the mbist_start signal must transition low then high.
//
// Loop on Address will disable the address mix function.
//
// /////////////////////////////////////////////////////////////////////////////


  // flop incoming signals:

  spc_mb1_ctlmsff_ctl_macro__width_2 input_signals_reg  (
               .scan_in(input_signals_reg_scanin),
               .scan_out(input_signals_reg_scanout),
               .l1clk    ( l1clk	                                 ),
               .din      ( {mbist_bisi_mode,mbist_user_mode} ),
               .dout     ( {bisi_mode      ,user_mode}       ),
  .siclk(siclk),
  .soclk(soclk));
  
  // default   : mb_enable=0
  // bisi      : mb_enable=0
  // user_mode : mb_enable=depend on programmed value

  spc_mb1_ctlmsff_ctl_macro__width_1 mb_enable_reg  (
               .scan_in(mb_enable_reg_scanin),
               .scan_out(mb_enable_reg_scanout),
               .l1clk    ( l1clk_pm1	       ),
               .din      ( mb_enable           ),
               .dout     ( mb_enable_out       ),
  .siclk(siclk),
  .soclk(soclk));


//assign mb_enable = user_mode ? mb_enable_out : 1'b0;
  assign mb_enable = mb_enable_out;

 
  assign start = user_mode ? (mb_enable_out & start_in) :
                              start_in;


  spc_mb1_ctlmsff_ctl_macro__width_2 config_reg  (
               .scan_in(config_reg_scanin),
               .scan_out(config_reg_scanout),
               .l1clk    ( l1clk_pm1	        ),
               .din      ( config_in[1:0]       ),
               .dout     ( config_out[1:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   
  assign config_in[0]        =    start;
  assign config_in[1]        =    config_out[0];
  assign start_transition    =    config_out[0] & ~config_out[1];
  assign end_transition      =   ~config_out[0] &  config_out[1];
  assign reset_engine        =    start_transition | loop_again  | end_transition;
  assign run                 =    config_out[1] ;


  spc_mb1_ctlmsff_ctl_macro__width_1 loop_again_reg  (
               .scan_in(loop_again_reg_scanin),
               .scan_out(loop_again_reg_scanout),
               .l1clk    ( l1clk_pm1	     ),
               .din      ( stop_engine_l     ),
               .dout     ( stop_engine_l_q   ),
  .siclk(siclk),
  .soclk(soclk));


assign loop_again=mb_user_loop_mode ? (stop_engine_l & ~stop_engine_l_q): 1'b0;


////////////////////////////////////   ////////////////////////////////////
//  USER MODE REGISTER (CONFIG)
////////////////////////////////////   ////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////
// user control registers
//                         size
// -  user_array            4
// -  user_addr_mode        1
// -  user_start_addr      15
// -  user_stop_addr       15
// -  user_inc_addr        15
// -  user_data_mode        1
// -  user_data             8
// -  user_cmpselinc_mode   1
// -  user_cmpselinc        3
// -  user_loop_mode        1

   spc_mb1_ctlmsff_ctl_macro__width_4 array_usr_reg  (
                  .scan_in(array_usr_reg_scanin),
                  .scan_out(array_usr_reg_scanout),
                  .l1clk    ( l1clk_pm1	                ),
  	          .din      ( user_array_in[3:0]	),
  		  .dout     ( user_array[3:0]		),
  .siclk(siclk),
  .soclk(soclk));

   assign user_array_in[3:0]=user_array[3:0];


   // user address mode

   spc_mb1_ctlmsff_ctl_macro__width_1 user_addr_mode_reg  (
                  .scan_in(user_addr_mode_reg_scanin),
                  .scan_out(user_addr_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                ),
  	          .din      ( user_addr_mode_in		),
  		  .dout     ( user_addr_mode		),
  .siclk(siclk),
  .soclk(soclk));

   assign user_addr_mode_in=user_addr_mode;
   

   //  user start address
   
  spc_mb1_ctlmsff_ctl_macro__width_5 user_start_addr_reg  (
                 .scan_in(user_start_addr_reg_scanin),
                 .scan_out(user_start_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1	                ),
                 .din      ( user_start_addr_in[4:0]	),
                 .dout     ( user_start_addr[4:0]	),
  .siclk(siclk),
  .soclk(soclk));


   assign user_start_addr_in[4:0]=user_start_addr[4:0];

   //  user stop address
   
  spc_mb1_ctlmsff_ctl_macro__width_5 user_stop_addr_reg  (
                 .scan_in(user_stop_addr_reg_scanin),
                 .scan_out(user_stop_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1	                ),
                 .din      ( user_stop_addr_in[4:0]	),
                 .dout     ( user_stop_addr[4:0]	),
  .siclk(siclk),
  .soclk(soclk));


   assign user_stop_addr_in[4:0]=user_stop_addr[4:0];
   

  //  user increment address
   
  spc_mb1_ctlmsff_ctl_macro__width_5 user_incr_addr_reg  (
                 .scan_in(user_incr_addr_reg_scanin),
                 .scan_out(user_incr_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1	                ),
                 .din      ( user_incr_addr_in[4:0]	),
                 .dout     ( user_incr_addr[4:0]	),
  .siclk(siclk),
  .soclk(soclk));


   assign user_incr_addr_in[4:0]=user_incr_addr[4:0];

   // user data mode

   spc_mb1_ctlmsff_ctl_macro__width_1 user_data_mode_reg  (
                  .scan_in(user_data_mode_reg_scanin),
                  .scan_out(user_data_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                ),
  	          .din      ( user_data_mode_in		),
   		  .dout     ( user_data_mode		),
  .siclk(siclk),
  .soclk(soclk));

							 
   assign user_data_mode_in=user_data_mode;

   //  user data select
   
   spc_mb1_ctlmsff_ctl_macro__width_8 user_data_reg  (
                 .scan_in(user_data_reg_scanin),
                 .scan_out(user_data_reg_scanout),
                 .l1clk    ( l1clk_pm1	                ),
                 .din      ( user_data_in[7:0]		),
                 .dout     ( user_data[7:0]		),
  .siclk(siclk),
  .soclk(soclk));


   assign user_data_in[7:0]    =    user_data[7:0];

   // user cmp sel inc
   // if its one, user need to program the cmpselinc register
   // otherwise it will loop all cmpsel

   spc_mb1_ctlmsff_ctl_macro__width_1 user_cmpselinc_hold_reg  (
                  .scan_in(user_cmpselinc_hold_reg_scanin),
                  .scan_out(user_cmpselinc_hold_reg_scanout),
                  .l1clk    ( l1clk_pm1	                ),
  	          .din      ( user_cmpselinc_hold_in	),
   		  .dout     ( user_cmpselinc_hold	),
  .siclk(siclk),
  .soclk(soclk));

							 
   assign user_cmpselinc_hold_in=user_cmpselinc_hold;


   // user cmp sel reg
   
   spc_mb1_ctlmsff_ctl_macro__width_3 user_cmpsel_reg  (
                  .scan_in(user_cmpsel_reg_scanin),
                  .scan_out(user_cmpsel_reg_scanout),
                  .l1clk    ( l1clk_pm1	                ),
  	          .din      ( user_cmpsel_in[2:0]	),
  		  .dout     ( user_cmpsel[2:0]		),
  .siclk(siclk),
  .soclk(soclk));

   assign user_cmpsel_in[2:0]=user_cmpsel[2:0];


   // user loop mode

   spc_mb1_ctlmsff_ctl_macro__width_1 user_loop_mode_reg  (
                  .scan_in(user_loop_mode_reg_scanin),
                  .scan_out(user_loop_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                ),
  	          .din      ( user_loop_mode_in		),
  		  .dout     ( user_loop_mode		),
  .siclk(siclk),
  .soclk(soclk));

  
   assign user_loop_mode_in=user_loop_mode;


   // 10N Algorithm for bit mapping

   spc_mb1_ctlmsff_ctl_macro__width_1 ten_n_mode_reg  (
                  .scan_in(ten_n_mode_reg_scanin),
                  .scan_out(ten_n_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                ),
  	          .din      ( ten_n_mode_in		),
  		  .dout     ( ten_n_mode		),
  .siclk(siclk),
  .soclk(soclk));

  
   assign ten_n_mode_in=ten_n_mode;


   spc_mb1_ctlmsff_ctl_macro__width_1 user_bisi_wr_mode_reg  (
                  .scan_in(user_bisi_wr_mode_reg_scanin),
                  .scan_out(user_bisi_wr_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                  ),
  	          .din      ( user_bisi_wr_mode_in   ),
  		  .dout     ( user_bisi_wr_mode      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_bisi_wr_mode_in=user_bisi_wr_mode;

   spc_mb1_ctlmsff_ctl_macro__width_1 user_bisi_rd_mode_reg  (
                  .scan_in(user_bisi_rd_mode_reg_scanin),
                  .scan_out(user_bisi_rd_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                  ),
  	          .din      ( user_bisi_rd_mode_in   ),
  		  .dout     ( user_bisi_rd_mode      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_bisi_rd_mode_in=user_bisi_rd_mode;


   assign mb_user_data_mode      = user_mode & user_data_mode;
   assign mb_user_addr_mode      = user_mode & user_addr_mode;
   assign mb_user_cmpselinc_hold = user_mode & user_cmpselinc_hold;
   assign mb_ten_n_mode          = user_mode & ten_n_mode;
   assign mb_user_loop_mode      = user_mode & user_loop_mode;


   assign mb_user_bisi_wr_mode   = user_mode & user_bisi_wr_mode & bisi_mode;
   assign mb_user_bisi_rd_mode   = user_mode & user_bisi_rd_mode & bisi_mode;

   assign mb_user_bisi_rw_mode   = ((~user_bisi_wr_mode & ~user_bisi_rd_mode) | (user_bisi_wr_mode & user_bisi_rd_mode)) & bisi_mode;

   assign mb_default_bisi = bisi_mode & ~user_mode;


////////////////////////////////////   ////////////////////////////////////
//  CONTROL REG:
////////////////////////////////////   ////////////////////////////////////


   spc_mb1_ctlmsff_ctl_macro__width_24 cntl_reg  (
                 .scan_in(cntl_reg_scanin),
                 .scan_out(cntl_reg_scanout),
                 .l1clk    ( l1clk_pm1	                   ),
                 .din      ({cntl_in[34:19] ,cntl_in[7:0]} ),
                 .dout     ({cntl_out[34:19],cntl_out[7:0]}),
  .siclk(siclk),
  .soclk(soclk));


   assign cntl_in[34:19]   = reset_engine   ? {16'b0000_0000000000}:
     	                     ~run3          ? cntl_algr[15:0]:	  
	                                          next_algr[15:0];

   
   // reset_engine   run3    overflow   cout_rw    output
   // ---------------------------------------------------------
   //    1             x        x          x       start_addr
   //    0             0        x          x       cntl_addr
   //    0             1        1          x       restart_addr
   //    0             1        0          1       incred_addr
   //    0             1        0          0       cntl_addr                                     


   assign sel_nextaddr_reset    = reset_engine;
   assign sel_nextaddr_restart  = ~reset_engine & run3 & overflow;
   assign sel_nextaddr_incred   = ~reset_engine & run3 & ~overflow & cout_rw;
   assign sel_nextaddr_same     = ~(sel_nextaddr_reset | sel_nextaddr_restart | sel_nextaddr_incred);


   assign cntl_in[7:3]  = ({5{sel_nextaddr_reset  }} & start_addr[4:0]) |
                          ({5{sel_nextaddr_restart}} & restart_addr[4:0]) |
                          ({5{sel_nextaddr_incred }} & incred_addr[4:0]) |
                          ({5{sel_nextaddr_same   }} & cntl_addr[4:0]);  
   

   assign cntl_in[2:0]     = reset_engine  ? 3'b000 : 
                            ~run3          ? cntl_rw[2:0]:
                                             next_rw[2:0];

////////////////////////////////////   ////////////////////////////////////
//  NEXT ALGR
////////////////////////////////////   ////////////////////////////////////

   // msb
   assign cntl_msb                    =      start_in & cntl_out[34];    // done selection

   assign cntl_bisi                    =       mb_default_bisi | mb_user_bisi_rw_mode ? cntl_out[33] :
                                                                                        1'b1;
   // array
   assign cntl_array_sel[3:0]         =       (last_array | user_mode) ? 4'b1111:
                                                        cntl_out[32:29];    // array selection 
   // cmp
   assign cntl_cmp_sel[2:0]           =   sel_cmp_pass ? {3'b111} :
                                                        cntl_out[28:26];

   // data
   assign cntl_data_sel[1:0]          =   (bisi_mode | mb_user_data_mode)  ? 2'b11 :    cntl_out[25:24];    // data selection

   // address mix
   assign cntl_addr_mix               =   (mb_user_addr_mode | bisi_mode) ? 1'b1  :    cntl_out[23];    // address mix
   assign addr_mix                    =   (mb_user_addr_mode | bisi_mode) ? 1'b0  :    cntl_out[23];

   assign cntl_march_element[3:0]     =   sel_march_1_pass  ? 4'b1111:
                                                              cntl_out[22:19];    // march element


   assign cntl_algr[15:0] =       {cntl_msb,
                                   cntl_bisi,
                                   cntl_array_sel[3:0],
			                       cntl_cmp_sel[2:0],
			                       cntl_data_sel[1:0],
			                       cntl_addr_mix,
			                       cntl_march_element[3:0]};

   assign next_algr[15:0] = cout_addr ? cntl_algr[15:0] + 16'h1 : cntl_algr[15:0];         // mbist control


////////////////////////////////////   ////////////////////////////////////
//  NEXT ADDR
////////////////////////////////////   ////////////////////////////////////


   /////////////////////////
   // address engine
   /////////////////////////


   assign upaddr           =    march_0 | march_1 | march_2 | march_6 | march_7 | bisi_mode ;
                                

   assign march_element_pre[3:0]=next_algr[3:0];

   assign march_pre_0   = march_element_pre[3:0]==4'h0;
   assign march_pre_1   = march_element_pre[3:0]==4'h1;
   assign march_pre_2   = march_element_pre[3:0]==4'h2;
   assign march_pre_6   = march_element_pre[3:0]==4'h6;
   assign march_pre_7   = march_element_pre[3:0]==4'h7;

   assign upaddr_pre =     march_pre_0 | march_pre_1 | march_pre_2 | march_pre_6 | march_pre_7;


   assign incr_addr[4:0]  = mb_user_addr_mode ? user_incr_addr[4:0] : 5'b00001;

   assign start_addr[4:0] = mb_user_addr_mode ? user_start_addr[4:0] : 5'b00000;
   
   
//   assign next_addr_out[7:0] = cout_rw ? cntl_addr[7:0] + incr_addr[7:0] : cntl_addr[7:0];    // next address


   assign incred_addr[4:0] = cntl_addr[4:0] + incr_addr[4:0];


   assign overflow   = upaddr   ? ( cntl_addr[4:0] == stop_addr[4:0])  & (cntl_rw[2:0]==3'b111):
                                  (~cntl_addr[4:0] == start_addr[4:0]) & (cntl_rw[2:0]==3'b111);


//   assign next_addr[7:0]= overflow ? restart_addr[7:0] : next_addr_out[7:0];
  
   assign restart_addr[4:0] = upaddr_pre ? start_addr[4:0] : ~stop_addr[4:0];
      
   assign cout_addr =  overflow;


////////////////////////////////////   ////////////////////////////////////
//  NEXT RW
////////////////////////////////////   ////////////////////////////////////


   assign cntl_rw[2:0]                =   sel_rw_pass      ? 3'b111: 
                                                               cntl_out[ 2: 0];    // read write control

   assign next_rw[2:0] = cntl_rw[2:0]+3'b001 ;              
   
   assign cout_rw = &cntl_rw[2:0];     // carry over for rw 


////////////////////////////////////   ////////////////////////////////////
//  MBIST CONTROL SIGNAL
//  - mem_wr
////////////////////////////////////   ////////////////////////////////////


   assign one_cycle_march  =  march_0 | march_5 | march_7;
   assign five_cycle_march =  march_6 | march_8;
   assign two_cycle_march  = ~(one_cycle_march | five_cycle_march);


   /////////////////////////
   // membist write enable
   /////////////////////////


    assign mem_wr_pbi     = run3 & (
                               march_0 |
                               ((march_1 | march_2 | march_3 | march_4 ) & rw_1) |
                               (march_6 & (rw_0 | rw_1 | rw_4)) |
                               march_7 |
                               (march_8 & (rw_0 | rw_1 | rw_4))
                               );  

   assign mem_wr = bisi_wr_mode ? 1'b1 :
                   bisi_rd_mode ? 1'b0 :
                                  mem_wr_pbi;

   /////////////////////////
   // membist read enable
   /////////////////////////

                                            
   assign mem_rd_pbi         =     run3   &      ~mem_wr;  

   assign mem_rd= bisi_rd_mode ? 1'b1 : mem_rd_pbi;

   /////////////////////
   // membist address:
   ////////////////////

   assign cntl_addr[4:0]   = cntl_out[7:3];

   assign adj_addr[4:0]     = (five_cycle_march & (rw_1 | rw_3)) ? {cntl_addr[4:1],~cntl_addr[0]}:
                                                                      cntl_addr[4:0] ;

   assign mem_addr1[4:0]    = upaddr   ?  adj_addr[4:0]:  ~adj_addr[4:0];


   /////////////////////
   // true data
   ////////////////////

   assign true_data_l     =   bisi_mode |
                              march_0   |
                             (march_1 & rw_0)   |
                             (march_2 & rw_1)   |
                             (march_3 & rw_0)   |
                             (march_4 & rw_1)   |
                             (march_5)   |
                             (march_6 & (rw_1 | rw_3 | rw_4))   |
                             (march_8 & (rw_0 | rw_2));

   assign true_data=~true_data_l;

   /////////////////////
   // membist data:
   ////////////////////

   assign data_pat_sel[7:0]        =     (mb_user_data_mode)     ?    user_data[7:0]:
                                         bisi_mode               ?    8'hFF:              
                                         (cntl_data_sel[1:0] == 2'h0)            ?    8'hAA:
                                         (cntl_data_sel[1:0] == 2'h1)            ?    8'h99:
                                         (cntl_data_sel[1:0] == 2'h2)            ?    8'hCC:
                                                                                      8'h00;
   assign mem_data[7:0]         = true_data ? data_pat_sel[7:0] : ~data_pat_sel[7:0];

////////////////////////////////////   ////////////////////////////////////
//  STOP ADDR
////////////////////////////////////   ////////////////////////////////////

   assign stop_addr[4:0]  = mb_user_addr_mode ? user_stop_addr[4:0]  : 
                                                   array_0   ?  5'b1_1111:  // tsa0
                                                   array_1   ?  5'b1_1111:  // tsa1
                                                   array_2   ?  5'b1_1111:  // tca
                                                   array_3   ?  5'b1_1111:  // scp0
                                                   array_4   ?  5'b1_1111:  // scp1
                                                   array_5   ?  5'b1_1111:  // mra0
                                                   array_6   ?  5'b1_1111:  // mra1
                                                                5'b1_1111;


////////////////////////////////////   ////////////////////////////////////
//  ADDR MIX
////////////////////////////////////   ////////////////////////////////////

   assign mem_addr[4:0]   =  (addr_mix) ?  
                                   {mem_addr1[0],mem_addr1[4:1]} :
                                    mem_addr1[4:0];


////////////////////////////////////   ////////////////////////////////////
//  SEQ selection
////////////////////////////////////   ////////////////////////////////////

    // array
    assign array_0     = array_sel[3:0]==4'h0;
    assign array_1     = array_sel[3:0]==4'h1;
    assign array_2     = array_sel[3:0]==4'h2;
    assign array_3     = array_sel[3:0]==4'h3;
    assign array_4     = array_sel[3:0]==4'h4;
    assign array_5     = array_sel[3:0]==4'h5;
    assign array_6     = array_sel[3:0]==4'h6;


   assign last_array= array_6;

   // cmp
// assign cmp_0      = cmp_sel[2:0]==3'b000;
   assign cmp_2      = cmp_sel[2:0]==3'b010;
   assign cmp_3      = cmp_sel[2:0]==3'b011;
   assign cmp_4      = cmp_sel[2:0]==3'b100;

   // march

   assign march_0   = (march_element[3:0]==4'h0);
   assign march_1   = (march_element[3:0]==4'h1);
   assign march_2   = (march_element[3:0]==4'h2);
   assign march_3   = (march_element[3:0]==4'h3);
   assign march_4   = (march_element[3:0]==4'h4);
   assign march_5   = (march_element[3:0]==4'h5);
   assign march_6   = (march_element[3:0]==4'h6);
   assign march_7   = (march_element[3:0]==4'h7);
   assign march_8   = (march_element[3:0]==4'h8);

   // rw

   assign rw_0           =  (rw[2:0]==3'b000);
   assign rw_1           =  (rw[2:0]==3'b001);
   assign rw_2           =  (rw[2:0]==3'b010);
   assign rw_3           =  (rw[2:0]==3'b011);
   assign rw_4           =  (rw[2:0]==3'b100);
// assign rw_5           =  (rw[2:0]==3'b101);
// assign rw_6           =  (rw[2:0]==3'b110);
// assign rw_7           =  (rw[2:0]==3'b111);


////////////////////////////////////   ////////////////////////////////////
//  SEQ logic
////////////////////////////////////   ////////////////////////////////////
   

   // array logic

  assign array_sel_cntl_out[3:0]=cntl_out[32:29];


  spc_mb1_ctlmsff_ctl_macro__width_4 array_sel_reg  (
               .scan_in(array_sel_reg_scanin),
               .scan_out(array_sel_reg_scanout),
               .l1clk    ( l1clk_pm1          ),
               .din      ( array_sel[3:0]     ),
               .dout     ( array_sel_out[3:0] ),
  .siclk(siclk),
  .soclk(soclk));

   assign array_sel[3:0]=(&array_sel_cntl_out[3:0]) ? array_sel_out[3:0] :
                          user_mode                 ? user_array[3:0] :
                                                      array_sel_cntl_out[3:0];


   // cmp logic

   assign cmp_sel_cntl_out[2:0] = cntl_out[28:26];

   spc_mb1_ctlmsff_ctl_macro__width_3 cmp_sel_reg  (
               .scan_in(cmp_sel_reg_scanin),
               .scan_out(cmp_sel_reg_scanout),
               .l1clk    ( l1clk_pm1        ),
               .din      ( cmp_sel[2:0]     ),
               .dout     ( cmp_sel_out[2:0] ),
  .siclk(siclk),
  .soclk(soclk));

   assign cmp_sel[2:0]=(&cmp_sel_cntl_out[2:0]) ? cmp_sel_out[2:0] :
                        mb_user_cmpselinc_hold         ? user_cmpsel[2:0] :
                                                  cmp_sel_cntl_out[2:0];
   

 // march logic                                          

  assign march_element_cntl_out[3:0]=cntl_out[22:19];


  spc_mb1_ctlmsff_ctl_macro__width_4 marche_element_reg  (
               .scan_in(marche_element_reg_scanin),
               .scan_out(marche_element_reg_scanout),
               .l1clk    ( l1clk_pm1          ),
               .din      ( march_element[3:0] ),
               .dout     ( march_element_out ),
  .siclk(siclk),
  .soclk(soclk));

   assign march_element[3:0]=(&march_element_cntl_out[3:0]) ? march_element_out[3:0] :
                                                              march_element_cntl_out[3:0];


   // rw
   assign rw[2:0]=cntl_out[2:0];


//////////////////////////////////////////////////////////////////
// SEL_PASS LOGIC
//////////////////////////////////////////////////////////////////


   // pass logic:

   // march
   assign sel_march_1_pass = bisi_mode | (mb_ten_n_mode & march_5) | march_8;
 

   assign bisi_wr_mode = mb_default_bisi | mb_user_bisi_rw_mode ?  ~cntl_bisi & run3 :
                                                                   mb_user_bisi_wr_mode & run3;
                         
   assign bisi_rd_mode  =mb_default_bisi | mb_user_bisi_rw_mode ?  cntl_bisi & run3 :
                                                                   mb_user_bisi_rd_mode & run3;
                          

   // cmp

   assign sel_cmp_pass= (mb_user_cmpselinc_hold | bisi_wr_mode) |
                             (array_0 & cmp_4) |  // tsa0 5
                             (array_1 & cmp_4) |  // tsa1 5
  	                     (array_2 & cmp_2) |  // tca  3
                             (array_3 & cmp_2) |  // scp0 3
                             (array_4 & cmp_2) |  // scp1 3
                             (array_5 & cmp_3) |  // mra0 4
                             (array_6 & cmp_3) ;  // mra1 4


   // rw
   assign sel_rw_1_pass = bisi_mode | one_cycle_march ;

   assign sel_rw_2_pass = two_cycle_march;
   assign sel_rw_5_pass = five_cycle_march;

   assign sel_rw_pass = (run3 & sel_rw_1_pass & rw_0) |
                        (run3 & sel_rw_2_pass & rw_1) |
                        (run3 & sel_rw_5_pass & rw_4) ;


////////////////////////////////////   ////////////////////////////////////
//  membist control assignment
////////////////////////////////////   ////////////////////////////////////

			       
   // TSA0, TSA1, and TCA are fully decoded for cmp signals
   // extra logic for cmp
   assign cmp_decoded_arrays= array_0 | array_1 | array_2 ;

   assign mb_cmp_sel[4:0] = cmp_decoded_arrays & (cmp_sel[2:0] == 3'b000) ? 5'b00001 :
                            cmp_decoded_arrays & (cmp_sel[2:0] == 3'b001) ? 5'b00010 :
                            cmp_decoded_arrays & (cmp_sel[2:0] == 3'b010) ? 5'b00100 :
                            cmp_decoded_arrays & (cmp_sel[2:0] == 3'b011) ? 5'b01000 :
                            cmp_decoded_arrays & (cmp_sel[2:0] == 3'b100) ? 5'b10000 :
                                                                            {2'b00,cmp_sel[2:0]};

 
   assign mb_addr[4:0]=mem_addr[4:0];
   assign mb_write_data[7:0]=mem_data[7:0];


   // only one array read signal should be active   

   assign  mb_array_0_rd= array_0  && mem_rd;
   assign  mb_array_1_rd= array_1  && mem_rd;
   assign  mb_array_2_rd= array_2  && mem_rd;
   assign  mb_array_3_rd= array_3  && mem_rd;
   assign  mb_array_4_rd= array_4  && mem_rd;
   assign  mb_array_5_rd= array_5  && mem_rd;
   assign  mb_array_6_rd= array_6  && mem_rd;


   assign  mb_array_0_wr= array_0  && mem_wr;
   assign  mb_array_1_wr= array_1  && mem_wr;
   assign  mb_array_2_wr= array_2  && mem_wr;
   assign  mb_array_3_wr= array_3  && mem_wr;
   assign  mb_array_4_wr= array_4  && mem_wr;
   assign  mb_array_5_wr= array_5  && mem_wr;
   assign  mb_array_6_wr= array_6  && mem_wr;


   assign mb_run = run;


////////////////////////////////////   ////////////////////////////////////
//  DONE LOGIC
////////////////////////////////////   ////////////////////////////////////


  spc_mb1_ctlmsff_ctl_macro__width_1  msb_latch  (
               .scan_in(msb_latch_scanin),
               .scan_out(msb_latch_scanout),
               .l1clk    ( l1clk_pm1	    ),
               .din      ( msb_in    ),
               .dout     ( msb_out  ),
  .siclk(siclk),
  .soclk(soclk));
   
   assign msb_in= (~start_in ) | (mb_user_loop_mode & mb_done) ? 1'b0 :
                   (cntl_msb)                                  ? 1'b1 :
                                                                 msb_out;

   
   assign stop_engine_l     =  start_in  & cntl_msb;


   assign mb_done=msb_out & (done_delay[4:0]==5'b11110);

   assign  run3   = &done_delay[4:1] & ~stop_engine_l & start_in;


   spc_mb1_ctlmsff_ctl_macro__width_1 run3_transition_reg  (
                  .scan_in(run3_transition_reg_scanin),
                  .scan_out(run3_transition_reg_scanout),
                  .l1clk    ( l1clk_pm1	          ),
                  .din      ( run3  ),
                  .dout     ( run3_out    ),
  .siclk(siclk),
  .soclk(soclk));

   assign run3_transition = run3 & ~run3_out;
   
   spc_mb1_ctlmsff_ctl_macro__width_5 done_delay_reg  (
                  .scan_in(done_delay_reg_scanin),
                  .scan_out(done_delay_reg_scanout),
                  .l1clk    ( l1clk_pm1	          ),
                  .din      ( done_delay_in[4:0]  ),
                  .dout     ( done_delay[4:0]    ),
  .siclk(siclk),
  .soclk(soclk));


   assign done_delay_in[4:0] = run3          ?  5'b11111 :
                               mb_done       ?  5'b11110 :
                              (run & ~run3)  ? done_delay[4:0] + 5'b00001 : 
                                                   5'b00000;


////////////////////////////////////   ////////////////////////////////////
//  FAIL LOGIC
////////////////////////////////////   ////////////////////////////////////


assign mra0_fail=run3_transition ? 1'b0 : (mmu_mbi_mra0_fail | mra0_fail_sticky);
assign mra1_fail=run3_transition ? 1'b0 : (mmu_mbi_mra1_fail | mra1_fail_sticky);
assign scp0_fail=run3_transition ? 1'b0 : (mmu_mbi_scp0_fail | scp0_fail_sticky);
assign scp1_fail=run3_transition ? 1'b0 : (mmu_mbi_scp1_fail | scp1_fail_sticky);
assign tsa0_fail=run3_transition ? 1'b0 : (tlu_mbi_tsa0_fail | tsa0_fail_sticky);
assign tsa1_fail=run3_transition ? 1'b0 : (tlu_mbi_tsa1_fail | tsa1_fail_sticky);
assign tca_fail =run3_transition ? 1'b0 : (tlu_mbi_tca_fail  | tca_fail_sticky);


spc_mb1_ctlmsff_ctl_macro__width_7		fail_reg		 (
 .scan_in(fail_reg_scanin),
 .scan_out(fail_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ({mra0_fail			,
	     mra1_fail			,
	     scp0_fail			,
	     scp1_fail			,
	     tsa0_fail			,
	     tsa1_fail			,
	     tca_fail}			),
 .dout ({mra0_fail_sticky		,
	     mra1_fail_sticky		,
	     scp0_fail_sticky		,
	     scp1_fail_sticky		,
	     tsa0_fail_sticky		,
	     tsa1_fail_sticky		,
	     tca_fail_sticky}		),
  .siclk(siclk),
  .soclk(soclk));


assign mbist_fail_sticky = mra0_fail_sticky |
                           mra1_fail_sticky |
                           scp0_fail_sticky |
                           scp1_fail_sticky |
                           tsa0_fail_sticky |
                           tsa1_fail_sticky |
                           tca_fail_sticky; 


assign mbist_fail_array = mmu_mbi_mra0_fail |
                          mmu_mbi_mra1_fail |
                          mmu_mbi_scp0_fail |
                          mmu_mbi_scp1_fail | 
                          tlu_mbi_tsa0_fail |
                          tlu_mbi_tsa1_fail |
                          tlu_mbi_tca_fail  ;

assign valid_fail=run3 | (stop_engine_l & ~mb_done);


assign mb_fail = mb_done ? mbist_fail_sticky : mbist_fail_array & valid_fail;


//////////////////////////////////////////////////////////////////
// OUTPUT FLOP:
//////////////////////////////////////////////////////////////////

// mb_done


spc_mb1_ctlmsff_ctl_macro__width_1  out_mb_tcu_done_reg  (
               .scan_in(out_mb_tcu_done_reg_scanin),
               .scan_out(out_mb_tcu_done_reg_scanout),
               .l1clk    ( l1clk_pm1    ),
               .din      ( mb_done      ),
               .dout     ( mb_done_out  ),
  .siclk(siclk),
  .soclk(soclk));


// mb_fail


spc_mb1_ctlmsff_ctl_macro__width_1 out_mb_tcu_fail_reg  (
               .scan_in(out_mb_tcu_fail_reg_scanin),
               .scan_out(out_mb_tcu_fail_reg_scanout),
               .l1clk    ( l1clk_pm1    ),
               .din      ( mb_fail      ),
               .dout     ( mb_fail_out  ),
  .siclk(siclk),
  .soclk(soclk));


// out cmpsel


spc_mb1_ctlmsff_ctl_macro__width_5		out_cmp_sel_reg		 (
 .scan_in(out_cmp_sel_reg_scanin),
 .scan_out(out_cmp_sel_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_cmp_sel[4:0]		),
 .dout ( mb_cmpsel_out[4:0]		),
  .siclk(siclk),
  .soclk(soclk));


// thes are all the output flops to arrays
// for the following signals:
//
// - run
// - data
// - address


spc_mb1_ctlmsff_ctl_macro__width_1		out_run_mb_arrays_reg		 (
 .scan_in(out_run_mb_arrays_reg_scanin),
 .scan_out(out_run_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_run				),
 .dout ( mb_run_out			),
  .siclk(siclk),
  .soclk(soclk));

// data 8 bits

spc_mb1_ctlmsff_ctl_macro__width_8		out_data_mb_arrays_reg		 (
 .scan_in(out_data_mb_arrays_reg_scanin),
 .scan_out(out_data_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_write_data[7:0]		),
 .dout ( mb_write_data_out[7:0]		),
  .siclk(siclk),
  .soclk(soclk));


// address 16 bits


spc_mb1_ctlmsff_ctl_macro__width_5		out_addr_mb_arrays_reg		 (
 .scan_in(out_addr_mb_arrays_reg_scanin),
 .scan_out(out_addr_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_addr[4:0]			),
 .dout ( mb_addr_out[4:0]		),
  .siclk(siclk),
  .soclk(soclk));


//
// write enable

spc_mb1_ctlmsff_ctl_macro__width_7		out_wr_mb_arrays_reg		 (
 .scan_in(out_wr_mb_arrays_reg_scanin),
 .scan_out(out_wr_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( {mb_array_0_wr,
     	  mb_array_1_wr,
	  mb_array_2_wr,
	  mb_array_3_wr,
          mb_array_4_wr,
     	  mb_array_5_wr,
	  mb_array_6_wr}		),
 .dout ({ mb_array_0_wr_out,
       	  mb_array_1_wr_out,
   	  mb_array_2_wr_out,
   	  mb_array_3_wr_out,
          mb_array_4_wr_out,
       	  mb_array_5_wr_out,
   	  mb_array_6_wr_out}		),
  .siclk(siclk),
  .soclk(soclk));


// read enable
 
spc_mb1_ctlmsff_ctl_macro__width_7		out_rd_mb_arrays_reg		 (
 .scan_in(out_rd_mb_arrays_reg_scanin),
 .scan_out(out_rd_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( {mb_array_0_rd,
     	  mb_array_1_rd,
	  mb_array_2_rd,
	  mb_array_3_rd,
          mb_array_4_rd,
     	  mb_array_5_rd,
	  mb_array_6_rd}		),
 .dout ({ mb_array_0_rd_out,
          mb_array_1_rd_out,
          mb_array_2_rd_out,
          mb_array_3_rd_out,
          mb_array_4_rd_out,
          mb_array_5_rd_out,
          mb_array_6_rd_out}		),
  .siclk(siclk),
  .soclk(soclk));


// port name re-assignment


   assign mb1_run             =mb_run_out;
   assign mb1_write_data[7:0] =mb_write_data_out[7:0];
   assign mb1_addr[15:0]      ={11'b000_0000_0000,mb_addr_out[4:0]};
   assign mb1_cmpsel[4:0]     =mb_cmpsel_out[4:0];
   assign mb1_mbist_fail      = mb_fail_out;
   assign mb1_done            = mb_done_out;

   assign mb1_tsa0_write_en=mb_array_0_wr_out;
   assign mb1_tsa1_write_en=mb_array_1_wr_out;
   assign mb1_tca_write_en =mb_array_2_wr_out;
   assign mb1_scp0_write_en=mb_array_3_wr_out;
   assign mb1_scp1_write_en=mb_array_4_wr_out;
   assign mb1_mra0_write_en=mb_array_5_wr_out;
   assign mb1_mra1_write_en=mb_array_6_wr_out;


   assign mb1_tsa0_read_en=mb_array_0_rd_out;
   assign mb1_tsa1_read_en=mb_array_1_rd_out;
   assign mb1_tca_read_en =mb_array_2_rd_out;
   assign mb1_scp0_read_en=mb_array_3_rd_out;
   assign mb1_scp1_read_en=mb_array_4_rd_out;
   assign mb1_mra0_read_en=mb_array_5_rd_out;
   assign mb1_mra1_read_en=mb_array_6_rd_out;


// spare gate

spc_mb1_ctlspare_ctl_macro__num_2 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
// /////////////////////////////////////////////////////////////////////////////
// fixscan start:
assign pmen_scanin               = scan_in                  ;
assign input_signals_reg_scanin  = pmen_scanout             ;
assign mb_enable_reg_scanin      = input_signals_reg_scanout;
assign config_reg_scanin         = mb_enable_reg_scanout    ;
assign loop_again_reg_scanin     = config_reg_scanout       ;
assign array_usr_reg_scanin      = loop_again_reg_scanout   ;
assign user_addr_mode_reg_scanin = array_usr_reg_scanout    ;
assign user_start_addr_reg_scanin = user_addr_mode_reg_scanout;
assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout;
assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout;
assign user_data_mode_reg_scanin = user_incr_addr_reg_scanout;
assign user_data_reg_scanin      = user_data_mode_reg_scanout;
assign user_cmpselinc_hold_reg_scanin = user_data_reg_scanout    ;
assign user_cmpsel_reg_scanin    = user_cmpselinc_hold_reg_scanout;
assign user_loop_mode_reg_scanin = user_cmpsel_reg_scanout  ;
assign ten_n_mode_reg_scanin     = user_loop_mode_reg_scanout;
assign user_bisi_wr_mode_reg_scanin = ten_n_mode_reg_scanout   ;
assign user_bisi_rd_mode_reg_scanin = user_bisi_wr_mode_reg_scanout;
assign cntl_reg_scanin           = user_bisi_rd_mode_reg_scanout;
assign array_sel_reg_scanin      = cntl_reg_scanout         ;
assign cmp_sel_reg_scanin        = array_sel_reg_scanout    ;
assign marche_element_reg_scanin = cmp_sel_reg_scanout      ;
assign msb_latch_scanin          = marche_element_reg_scanout;
assign run3_transition_reg_scanin = msb_latch_scanout        ;
assign done_delay_reg_scanin     = run3_transition_reg_scanout;
assign fail_reg_scanin           = done_delay_reg_scanout   ;
assign out_mb_tcu_done_reg_scanin = fail_reg_scanout         ;
assign out_mb_tcu_fail_reg_scanin = out_mb_tcu_done_reg_scanout;
assign out_cmp_sel_reg_scanin    = out_mb_tcu_fail_reg_scanout;
assign out_run_mb_arrays_reg_scanin = out_cmp_sel_reg_scanout  ;
assign out_data_mb_arrays_reg_scanin = out_run_mb_arrays_reg_scanout;
assign out_addr_mb_arrays_reg_scanin = out_data_mb_arrays_reg_scanout;
assign out_wr_mb_arrays_reg_scanin = out_addr_mb_arrays_reg_scanout;
assign out_rd_mb_arrays_reg_scanin = out_wr_mb_arrays_reg_scanout;
assign spares_scanin             = out_rd_mb_arrays_reg_scanout;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule
// /////////////////////////////////////////////////////////////////////////////


// any PARAMS parms go into naming of macro

module spc_mb1_ctll1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb1_ctlmsff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb1_ctlmsff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb1_ctlmsff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb1_ctlmsff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb1_ctlmsff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb1_ctlmsff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb1_ctlmsff_ctl_macro__width_24 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [23:0] fdin;
wire [22:0] so;

  input [23:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [23:0] dout;
  output scan_out;
assign fdin[23:0] = din[23:0];


dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb1_ctlmsff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module spc_mb1_ctlspare_ctl_macro__num_2 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));
assign scan_out = so_1;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spc_mb2_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module spc_mb2_ctl (
  scan_out, 
  mb2_done, 
  mb2_run, 
  mb2_addr, 
  mb2_frf_read_en, 
  mb2_frf_write_en, 
  mb2_arf_read_en, 
  mb2_arf_write_en, 
  mb2_irf_read_en, 
  mb2_irf_write_en, 
  mb2_irf_save_en, 
  mb2_irf_restore_en, 
  mb2_mam_read_en, 
  mb2_mam_write_en, 
  mb2_rrf_read_en, 
  mb2_rrf_write_en, 
  mb2_write_data, 
  mb2_write_data_p1, 
  mb2_write_data_p2, 
  mb2_misc_pmen, 
  mb2_mbist_fail, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_clk_stop, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  lsu_misc_pmen, 
  mbist_start, 
  mbist_user_mode, 
  mbist_bisi_mode, 
  spu_mbi_mam_fail_, 
  spu_mbi_mam_fail2_, 
  spu_mbi_arf_fail_, 
  spu_mbi_rrf_fail_, 
  exu0_mbi_irf_fail_, 
  exu1_mbi_irf_fail_, 
  fgu_mbi_frf_fail);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire pmen_scanin;
wire pmen_scanout;
wire start_in;
wire misc_pmen_;
wire pmem_unused;
wire clock_enable;
wire l1clk_pm1;
wire input_signals_reg_scanin;
wire input_signals_reg_scanout;
wire bisi_mode;
wire user_mode;
wire mb_enable_reg_scanin;
wire mb_enable_reg_scanout;
wire mb_enable;
wire mb_enable_out;
wire start;
wire config_reg_scanin;
wire config_reg_scanout;
wire [1:0] config_in;
wire [1:0] config_out;
wire start_transition;
wire end_transition;
wire reset_engine;
wire loop_again;
wire run;
wire loop_again_reg_scanin;
wire loop_again_reg_scanout;
wire stop_engine_l;
wire stop_engine_l_q;
wire mb_user_loop_mode;
wire array_usr_reg_scanin;
wire array_usr_reg_scanout;
wire [3:0] user_array_in;
wire [3:0] user_array;
wire user_addr_mode_reg_scanin;
wire user_addr_mode_reg_scanout;
wire user_addr_mode_in;
wire user_addr_mode;
wire user_start_addr_reg_scanin;
wire user_start_addr_reg_scanout;
wire [9:0] user_start_addr_in;
wire [9:0] user_start_addr;
wire user_stop_addr_reg_scanin;
wire user_stop_addr_reg_scanout;
wire [9:0] user_stop_addr_in;
wire [9:0] user_stop_addr;
wire user_incr_addr_reg_scanin;
wire user_incr_addr_reg_scanout;
wire [9:0] user_incr_addr_in;
wire [9:0] user_incr_addr;
wire user_data_mode_reg_scanin;
wire user_data_mode_reg_scanout;
wire user_data_mode_in;
wire user_data_mode;
wire user_data_reg_scanin;
wire user_data_reg_scanout;
wire [7:0] user_data_in;
wire [7:0] user_data;
wire user_cmpselinc_hold_reg_scanin;
wire user_cmpselinc_hold_reg_scanout;
wire user_cmpselinc_hold_in;
wire user_cmpselinc_hold;
wire user_cmpsel_reg_scanin;
wire user_cmpsel_reg_scanout;
wire [2:0] user_cmpsel_in;
wire [2:0] user_cmpsel;
wire user_loop_mode_reg_scanin;
wire user_loop_mode_reg_scanout;
wire user_loop_mode_in;
wire user_loop_mode;
wire ten_n_mode_reg_scanin;
wire ten_n_mode_reg_scanout;
wire ten_n_mode_in;
wire ten_n_mode;
wire user_bisi_wr_mode_reg_scanin;
wire user_bisi_wr_mode_reg_scanout;
wire user_bisi_wr_mode_in;
wire user_bisi_wr_mode;
wire user_bisi_rd_mode_reg_scanin;
wire user_bisi_rd_mode_reg_scanout;
wire user_bisi_rd_mode_in;
wire user_bisi_rd_mode;
wire mb_user_data_mode;
wire mb_user_addr_mode;
wire mb_ten_n_mode;
wire mb_user_cmpselinc_hold;
wire mb_user_bisi_wr_mode;
wire mb_user_bisi_rd_mode;
wire mb_user_bisi_rw_mode;
wire mb_default_bisi;
wire [9:0] stop_addr;
wire array_0;
wire array_1;
wire array_2;
wire array_3;
wire array_4;
wire array_5;
wire rw_0;
wire [2:0] rw;
wire rw_1;
wire rw_2;
wire rw_3;
wire rw_4;
wire rw_5;
wire rw_6;
wire march_0;
wire [3:0] march_element;
wire march_1;
wire march_2;
wire march_3;
wire march_4;
wire march_5;
wire march_6;
wire march_7;
wire march_8;
wire [9:0] mem_addr;
wire addr_mix;
wire [9:0] up_addr;
wire cntl_msb;
wire [34:0] cntl_out;
wire cntl_bisi;
wire [3:0] cntl_array_sel;
wire last_array;
wire [2:0] cntl_cmp_sel;
wire sel_cmp_pass;
wire cmp_0;
wire cmp_7;
wire [2:0] cmp_sel_cntl_out;
wire cmp_sel_reg_scanin;
wire cmp_sel_reg_scanout;
wire [2:0] cmp_sel;
wire [2:0] cmp_sel_out;
wire [1:0] cntl_data_sel;
wire cntl_addr_mix;
wire [3:0] cntl_march_element;
wire sel_march_1_pass;
wire [15:0] cntl_algr;
wire [15:0] next_algr;
wire cout_addr;
wire [34:0] cntl_in;
wire run3;
wire sel_nextaddr_reset;
wire sel_nextaddr_restart;
wire overflow;
wire sel_nextaddr_incred;
wire cout_rw;
wire sel_nextaddr_same;
wire [9:0] start_addr;
wire [9:0] restart_addr;
wire [9:0] incred_addr;
wire [9:0] cntl_addr;
wire [9:0] incr_addr;
wire upaddr;
wire [2:0] cntl_rw;
wire upaddr_pre;
wire [3:0] march_element_pre;
wire march_pre_0;
wire march_pre_1;
wire march_pre_2;
wire march_pre_6;
wire march_pre_7;
wire sel_rw_pass;
wire [2:0] next_rw;
wire [3:0] array_sel;
wire cntl_reg_scanin;
wire cntl_reg_scanout;
wire one_cycle_march;
wire five_cycle_march;
wire two_cycle_march;
wire bisi_wr_mode;
wire bisi_rd_mode;
wire sel_rw_1_pass;
wire sel_rw_2_pass;
wire sel_rw_5_pass;
wire true_data_l;
wire true_data;
wire [7:0] data_pat_sel;
wire [7:0] mem_data1;
wire [7:0] mem_data;
wire [9:0] adj_addr;
wire mem_wr_pbi;
wire mem_wr;
wire mem_save;
wire mem_restore;
wire mem_rd_pbi;
wire mem_rd;
wire [3:0] array_sel_cntl_out;
wire array_sel_reg_scanin;
wire array_sel_reg_scanout;
wire [3:0] array_sel_out;
wire [3:0] march_element_cntl_out;
wire marche_element_reg_scanin;
wire marche_element_reg_scanout;
wire [3:0] march_element_out;
wire mb_run;
wire [15:0] mb_addr;
wire [7:0] mb_write_data;
wire mb_array_0_rd;
wire mb_array_1_rd;
wire mb_array_2_rd;
wire mb_array_3_rd;
wire mb_array_save;
wire mb_array_5_rd;
wire mb_array_0_wr;
wire mb_array_1_wr;
wire mb_array_2_wr;
wire mb_array_3_wr;
wire mb_array_restore;
wire mb_array_5_wr;
wire spu_arf_fail;
wire mb2_arf_read_en_p2;
wire spu_rrf_fail;
wire mb2_rrf_read_en_p2;
wire spu_mam_fail;
wire mb2_mam_read_en_p2;
wire exu0_irf_fail;
wire mb2_irf_read_en_p4;
wire exu1_irf_fail;
wire arf_fail;
wire run3_transition;
wire spu_arf_fail_sticky;
wire rrf_fail;
wire spu_rrf_fail_sticky;
wire mam_fail;
wire spu_mam_fail_sticky;
wire irf0_fail;
wire exu0_irf_fail_sticky;
wire irf1_fail;
wire exu1_irf_fail_sticky;
wire frf_fail;
wire fgu_frf_fail_sticky;
wire fail_reg_scanin;
wire fail_reg_scanout;
wire mbist_fail_sticky;
wire mbist_fail_array;
wire valid_fail;
wire mb_done;
wire mb_fail;
wire msb_latch_scanin;
wire msb_latch_scanout;
wire msb_in;
wire msb_out;
wire [4:0] done_delay;
wire run3_transition_reg_scanin;
wire run3_transition_reg_scanout;
wire run3_out;
wire done_delay_reg_scanin;
wire done_delay_reg_scanout;
wire [4:0] done_delay_in;
wire out_run_mb_arrays_reg_scanin;
wire out_run_mb_arrays_reg_scanout;
wire mb_run_out;
wire out_data_mb_arrays_reg_scanin;
wire out_data_mb_arrays_reg_scanout;
wire [7:0] mb_write_data_out;
wire out_addr_mb_arrays_reg_scanin;
wire out_addr_mb_arrays_reg_scanout;
wire [15:0] mb_addr_out;
wire out_wr_mb_arrays_reg_scanin;
wire out_wr_mb_arrays_reg_scanout;
wire mb_array_0_wr_out;
wire mb_array_1_wr_out;
wire mb_array_2_wr_out;
wire mb_array_3_wr_out;
wire mb_array_5_wr_out;
wire out_rd_mb_arrays_reg_scanin;
wire out_rd_mb_arrays_reg_scanout;
wire mb_array_0_rd_out;
wire mb_array_1_rd_out;
wire mb_array_2_rd_out;
wire mb_array_3_rd_out;
wire mb_array_5_rd_out;
wire out_mb_tcu_done_reg_scanin;
wire out_mb_tcu_done_reg_scanout;
wire mb_done_out;
wire out_mb_tcu_fail_reg_scanin;
wire out_mb_tcu_fail_reg_scanout;
wire mb_fail_out;
wire spares_scanin;
wire spares_scanout;
wire i_delay_4th_scanin;
wire i_delay_4th_scanout;
wire mb2_irf_read_en_p1;
wire mb2_irf_read_en_p2;
wire mb2_irf_read_en_p3;
wire delayed_cmp_rd_data_reg_scanin;
wire delayed_cmp_rd_data_reg_scanout;
wire mb2_arf_read_en_p1;
wire mb2_mam_read_en_p1;
wire mb2_rrf_read_en_p1;
wire out_save_restore_mb_arrays_reg_scanin;
wire out_save_restore_mb_arrays_reg_scanout;


// /////////////////////////////////////////////////////////////////////////////
// Outputs
// /////////////////////////////////////////////////////////////////////////////

   output		    scan_out;

   output		    mb2_done;

   output		    mb2_run;
   output [15:0]	    mb2_addr;
   output		    mb2_frf_read_en;
   output		    mb2_frf_write_en;
   output		    mb2_arf_read_en;
   output		    mb2_arf_write_en;
   output		    mb2_irf_read_en;
   output		    mb2_irf_write_en;
   output		    mb2_irf_save_en;
   output		    mb2_irf_restore_en;
   output		    mb2_mam_read_en;
   output		    mb2_mam_write_en;
   output		    mb2_rrf_read_en;
   output		    mb2_rrf_write_en;
   output [7:0]		    mb2_write_data;
   output [7:0]		    mb2_write_data_p1;
   output [7:0]		    mb2_write_data_p2;

   output                   mb2_misc_pmen;
   output		    mb2_mbist_fail;

// /////////////////////////////////////////////////////////////////////////////
// Inputs
// /////////////////////////////////////////////////////////////////////////////

   input		    l2clk;
   input		    scan_in;
   input		    tcu_pce_ov;			// scan signals
   input		    tcu_clk_stop;
   input		    tcu_aclk;
   input		    tcu_bclk;
   input            	    tcu_scan_en;
   input                    lsu_misc_pmen;		// Power management enable

   input		    mbist_start;
   input		    mbist_user_mode;
   input		    mbist_bisi_mode;


   input		    spu_mbi_mam_fail_; 		// MBIST comparator output bits 63:0
   input		    spu_mbi_mam_fail2_; 	// MBIST comparator output bits 71:64
   input		    spu_mbi_arf_fail_;		// MBIST comparator
   input		    spu_mbi_rrf_fail_;		// MBIST comparator

   input  [1:0]		    exu0_mbi_irf_fail_;		// MBIST [0] == data[63:0]; [1] == data[71:64]
   input  [1:0]		    exu1_mbi_irf_fail_;		// MBIST [0] == data[63:0]; [1] == data[71:64]
   input     		    fgu_mbi_frf_fail;


   supply0 vss; // <- port for ground
   supply1 vdd; // <- port for power 


// /////////////////////////////////////////////////////////////////////////////
// Scan Renames
// /////////////////////////////////////////////////////////////////////////////

assign pce_ov = tcu_pce_ov;
assign stop   = tcu_clk_stop;
assign siclk  = tcu_aclk;
assign soclk  = tcu_bclk;
assign se     = tcu_scan_en;


////////////////////////////////////////////////////////////////////////////////
// Clock header
////////////////////////////////////////////////////////////////////////////////

spc_mb2_ctll1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk 		),
        .l1en   (1'b1		),
        .l1clk  (l1clk		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));

spc_mb2_ctlmsff_ctl_macro__width_3 pmen  (
	.scan_in(pmen_scanin),
	.scan_out(pmen_scanout),
	.l1clk    ( l1clk					),	// Must be connected to a free running clock
	.din      ({mbist_start, ~lsu_misc_pmen , 1'b0}		),
	.dout     ({start_in   ,  misc_pmen_    , pmem_unused}	),
  .siclk(siclk),
  .soclk(soclk));

assign mb2_misc_pmen	= ~misc_pmen_;					// Sent to MB1 for timing reasons

assign clock_enable	= start_in | mb2_done | mb2_run | mb2_mbist_fail | misc_pmen_;

spc_mb2_ctll1clkhdr_ctl_macro clkgen_pm1 (
        .l2clk  (l2clk 		),
        .l1en   (clock_enable	),
        .l1clk  (l1clk_pm1	),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se));


// /////////////////////////////////////////////////////////////////////////////
//
// MBIST Config Register
//
// /////////////////////////////////////////////////////////////////////////////
//
// A low to high transition on mbist_start will reset and start the engine.  
// mbist_start must remain active high for the duration of MBIST.  
// If mbist_start deasserts the engine will stop but not reset.
// Once MBIST has completed mb0_done will assert and the fail status
// signals will be valid.  
// To run MBIST again the mbist_start signal must transition low then high.
//
// Loop on Address will disable the address mix function.
//
// /////////////////////////////////////////////////////////////////////////////

  // flop incoming signals:

  spc_mb2_ctlmsff_ctl_macro__width_2 input_signals_reg  (
               .scan_in(input_signals_reg_scanin),
               .scan_out(input_signals_reg_scanout),
               .l1clk    ( l1clk	                                 ),
               .din      ( {mbist_bisi_mode,mbist_user_mode} ),
               .dout     ( {bisi_mode      ,user_mode}       ),
  .siclk(siclk),
  .soclk(soclk));
  

  // default   : mb_enable=0
  // bisi      : mb_enable=0
  // user_mode : mb_enable=depend on programmed value

  spc_mb2_ctlmsff_ctl_macro__width_1 mb_enable_reg  (
               .scan_in(mb_enable_reg_scanin),
               .scan_out(mb_enable_reg_scanout),
               .l1clk    ( l1clk_pm1           ),
               .din      ( mb_enable           ),
               .dout     ( mb_enable_out       ),
  .siclk(siclk),
  .soclk(soclk));


//assign mb_enable = user_mode ? mb_enable_out : 1'b0;
  assign mb_enable = mb_enable_out;

 
  assign start = user_mode ? (mb_enable_out & start_in) :
                              start_in;


  spc_mb2_ctlmsff_ctl_macro__width_2 config_reg  (
               .scan_in(config_reg_scanin),
               .scan_out(config_reg_scanout),
               .l1clk    ( l1clk_pm1            ),
               .din      ( config_in[1:0]       ),
               .dout     ( config_out[1:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   
  assign config_in[0]        =    start;
  assign config_in[1]        =    config_out[0];
  assign start_transition    =    config_out[0] & ~config_out[1];
  assign end_transition      =   ~config_out[0] &  config_out[1];
  assign reset_engine        =    start_transition | loop_again  | end_transition;
  assign run                 =    config_out[1];


  spc_mb2_ctlmsff_ctl_macro__width_1 loop_again_reg  (
               .scan_in(loop_again_reg_scanin),
               .scan_out(loop_again_reg_scanout),
               .l1clk    ( l1clk_pm1        ),
               .din      ( stop_engine_l    ),
               .dout     ( stop_engine_l_q  ),
  .siclk(siclk),
  .soclk(soclk));

  assign loop_again=mb_user_loop_mode ? stop_engine_l & ~stop_engine_l_q:  1'b0;


////////////////////////////////////////////////////////////////////////////////
// user control registers
//                         size
// -  user_array           4
// -  user_addr_mode        1
// -  user_start_addr      10
// -  user_stop_addr       10
// -  user_inc_addr        10
// -  user_data_mode        1
// -  user_data             8
// -  user_cmpselinc_mode   1
// -  user_cmpselinc        3
// -  user_loop_mode        1
// -  user_cam_select       2
// -  user_cam_test_sel     4
////////////////////////////////////////////////////////////////////////////////


   spc_mb2_ctlmsff_ctl_macro__width_4 array_usr_reg  (
                  .scan_in(array_usr_reg_scanin),
                  .scan_out(array_usr_reg_scanout),
                  .l1clk    ( l1clk_pm1            ),
  	          .din      ( user_array_in[3:0]   ),
  		  .dout     ( user_array[3:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_array_in[3:0]=user_array[3:0];


   // user address mode

   spc_mb2_ctlmsff_ctl_macro__width_1 user_addr_mode_reg  (
                  .scan_in(user_addr_mode_reg_scanin),
                  .scan_out(user_addr_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1             ),
  	          .din      ( user_addr_mode_in     ),
  		  .dout     ( user_addr_mode        ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_addr_mode_in=user_addr_mode;
   

   //  user start address
   
  spc_mb2_ctlmsff_ctl_macro__width_10 user_start_addr_reg  (
                 .scan_in(user_start_addr_reg_scanin),
                 .scan_out(user_start_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1                 ),
                 .din      ( user_start_addr_in[9:0]   ),
                 .dout     ( user_start_addr[9:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_start_addr_in[9:0]=user_start_addr[9:0];

   //  user stop address
   
  spc_mb2_ctlmsff_ctl_macro__width_10 user_stop_addr_reg  (
                 .scan_in(user_stop_addr_reg_scanin),
                 .scan_out(user_stop_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1                ),
                 .din      ( user_stop_addr_in[9:0]   ),
                 .dout     ( user_stop_addr[9:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_stop_addr_in[9:0]=user_stop_addr[9:0];
   

  //  user increment address
   
  spc_mb2_ctlmsff_ctl_macro__width_10 user_incr_addr_reg  (
                 .scan_in(user_incr_addr_reg_scanin),
                 .scan_out(user_incr_addr_reg_scanout),
                 .l1clk    ( l1clk_pm1                ),
                 .din      ( user_incr_addr_in[9:0]   ),
                 .dout     ( user_incr_addr[9:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_incr_addr_in[9:0]=user_incr_addr[9:0];

   // user data mode

   spc_mb2_ctlmsff_ctl_macro__width_1 user_data_mode_reg  (
                  .scan_in(user_data_mode_reg_scanin),
                  .scan_out(user_data_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1             ),
  	          .din      ( user_data_mode_in     ),
   		  .dout     ( user_data_mode        ),
  .siclk(siclk),
  .soclk(soclk));

							 
   assign user_data_mode_in=user_data_mode;

   //  user data select
   
   spc_mb2_ctlmsff_ctl_macro__width_8 user_data_reg  (
                 .scan_in(user_data_reg_scanin),
                 .scan_out(user_data_reg_scanout),
                 .l1clk    ( l1clk_pm1           ),
                 .din      ( user_data_in[7:0]   ),
                 .dout     ( user_data[7:0]      ),
  .siclk(siclk),
  .soclk(soclk));


   assign user_data_in[7:0]    =    user_data[7:0];


   // user cmp sel inc
   // if its one, user need to program the cmpselinc register
   // otherwise it will loop all cmpsel

   spc_mb2_ctlmsff_ctl_macro__width_1 user_cmpselinc_hold_reg  (
                  .scan_in(user_cmpselinc_hold_reg_scanin),
                  .scan_out(user_cmpselinc_hold_reg_scanout),
                  .l1clk    ( l1clk_pm1                  ),
  	          .din      ( user_cmpselinc_hold_in     ),
   		  .dout     ( user_cmpselinc_hold        ),
  .siclk(siclk),
  .soclk(soclk));

							 
   assign user_cmpselinc_hold_in=user_cmpselinc_hold;


   // user cmp sel reg
   
   spc_mb2_ctlmsff_ctl_macro__width_3 user_cmpsel_reg  (
                  .scan_in(user_cmpsel_reg_scanin),
                  .scan_out(user_cmpsel_reg_scanout),
                  .l1clk    ( l1clk_pm1             ),
  	          .din      ( user_cmpsel_in[2:0]   ),
  		  .dout     ( user_cmpsel[2:0]      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_cmpsel_in[2:0]=user_cmpsel[2:0];

   // user loop mode

   spc_mb2_ctlmsff_ctl_macro__width_1 user_loop_mode_reg  (
                  .scan_in(user_loop_mode_reg_scanin),
                  .scan_out(user_loop_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1             ),
  	          .din      ( user_loop_mode_in     ),
  		  .dout     ( user_loop_mode        ),
  .siclk(siclk),
  .soclk(soclk));

  
   assign user_loop_mode_in=user_loop_mode;

   
   // 10N Algorithm for bit mapping

   spc_mb2_ctlmsff_ctl_macro__width_1 ten_n_mode_reg  (
                  .scan_in(ten_n_mode_reg_scanin),
                  .scan_out(ten_n_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1         ),
  	          .din      ( ten_n_mode_in     ),
  		  .dout     ( ten_n_mode        ),
  .siclk(siclk),
  .soclk(soclk));

  
   assign ten_n_mode_in=ten_n_mode;


   spc_mb2_ctlmsff_ctl_macro__width_1 user_bisi_wr_mode_reg  (
                  .scan_in(user_bisi_wr_mode_reg_scanin),
                  .scan_out(user_bisi_wr_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                  ),
  	          .din      ( user_bisi_wr_mode_in   ),
  		  .dout     ( user_bisi_wr_mode      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_bisi_wr_mode_in=user_bisi_wr_mode;

   spc_mb2_ctlmsff_ctl_macro__width_1 user_bisi_rd_mode_reg  (
                  .scan_in(user_bisi_rd_mode_reg_scanin),
                  .scan_out(user_bisi_rd_mode_reg_scanout),
                  .l1clk    ( l1clk_pm1	                  ),
  	          .din      ( user_bisi_rd_mode_in   ),
  		  .dout     ( user_bisi_rd_mode      ),
  .siclk(siclk),
  .soclk(soclk));

   assign user_bisi_rd_mode_in=user_bisi_rd_mode;


   assign mb_user_data_mode = user_mode & user_data_mode;
   assign mb_user_addr_mode = user_mode & user_addr_mode;
   assign mb_ten_n_mode     = user_mode & ten_n_mode;
   assign mb_user_loop_mode = user_mode & user_loop_mode;
   assign mb_user_cmpselinc_hold = user_mode & user_cmpselinc_hold;


   assign mb_user_bisi_wr_mode   = user_mode & user_bisi_wr_mode & bisi_mode;
   assign mb_user_bisi_rd_mode   = user_mode & user_bisi_rd_mode & bisi_mode;

   assign mb_user_bisi_rw_mode   = ((~user_bisi_wr_mode & ~user_bisi_rd_mode) | (user_bisi_wr_mode & user_bisi_rd_mode)) & bisi_mode;

   assign mb_default_bisi = bisi_mode & ~user_mode;


   assign stop_addr[9:0]  = ({10{ mb_user_addr_mode          }} & user_stop_addr[9:0]) |
                            ({10{~mb_user_addr_mode & array_0}} & 10'b00_0001_1111   ) |	// arf
                            ({10{~mb_user_addr_mode & array_1}} & 10'b00_0011_1111   ) |	// rrf
                            ({10{~mb_user_addr_mode & array_2}} & 10'b00_1001_1111   ) |	// mam
                            ({10{~mb_user_addr_mode & array_3}} & 10'b00_0111_1111   ) |	// irf active
                            ({10{~mb_user_addr_mode & array_4}} & 10'b00_0111_1111   ) |    // irf shadow
                            ({10{~mb_user_addr_mode & array_5}} & 10'b00_1111_1111   );		// frf


   assign rw_0           =  (rw[2:0]==3'b000);
   assign rw_1           =  (rw[2:0]==3'b001);
   assign rw_2           =  (rw[2:0]==3'b010);
   assign rw_3           =  (rw[2:0]==3'b011);
   assign rw_4           =  (rw[2:0]==3'b100);
   assign rw_5           =  (rw[2:0]==3'b101);
   assign rw_6           =  (rw[2:0]==3'b110);
// assign rw_7           =  (rw[2:0]==3'b111);


   assign march_0   = (march_element[3:0]==4'h0);
   assign march_1   = (march_element[3:0]==4'h1);
   assign march_2   = (march_element[3:0]==4'h2);
   assign march_3   = (march_element[3:0]==4'h3);
   assign march_4   = (march_element[3:0]==4'h4);
   assign march_5   = (march_element[3:0]==4'h5);
   assign march_6   = (march_element[3:0]==4'h6);
   assign march_7   = (march_element[3:0]==4'h7);
   assign march_8   = (march_element[3:0]==4'h8);


   ////////////////////////////////////////////////////////////////////////////////////////////////////////////
   /// address mix : fast_row and fast_column
   ////////////////////////////////////////////////////////////////////////////////////////////////////////////

   // arf: no column decorder or multiple bansk
   // maps one to one  - logical to physical

   // rrf:  no column decoder or banks addr[5:0]
   //       maps one to one


   // mam:  
   //        -  address 7:5 is for block select (0-5) blocks
   //        -  4:1  row select
   //        -  0 column select

   // irf:  
   //        -  addr[0] is for column select
   //        -  addr[6:0]
   //


   assign mem_addr[9:0]   =   (addr_mix & array_0) ? { up_addr[9:5],up_addr[3:0],up_addr[4] } : // arf fixed w/circuit
                              (addr_mix & array_1) ? { up_addr[9:6],up_addr[2:0],up_addr[5:3] } : // rrf fixed w/circuit
                              (addr_mix & array_2) ? { up_addr[9:5],up_addr[3:0],up_addr[4] } : // mam fixed w/circuit
                              (addr_mix & array_3) ? { up_addr[9:7],up_addr[5:0],up_addr[6] } : // irf active w/circuit
                              (addr_mix & array_4) ? { up_addr[9:0] } : // no addr mix for irf shadow
                              (addr_mix & array_5) ? { up_addr[9:8],up_addr[6:0],up_addr[7]} :  // frf w/circuit
                                             up_addr[9:0];


   assign cntl_msb                    =       start_in & cntl_out[34];    // done selection


   assign cntl_bisi                    =       mb_default_bisi | mb_user_bisi_rw_mode ? cntl_out[33] :
                                                                                        1'b1;


   assign cntl_array_sel[3:0]        =       (last_array | user_mode) ? 4'b1111:
                                                        cntl_out[32:29];    // array selection 

   assign cntl_cmp_sel[2:0]  = sel_cmp_pass ? {3'b111} :
                                              cntl_out[28:26];
   
   // cmp

   assign sel_cmp_pass= mb_user_cmpselinc_hold |
                             (array_0 & cmp_0) |  // arf
                             (array_1 & cmp_0) |  // rrf
  	                         (array_2 & cmp_0) |  // mam
                             (array_3 & cmp_0) |  // irf active
                             (array_4 & cmp_7) |  // irf shadow
                             (array_5 & cmp_0) ;  // frf


  // cmp logic

   assign cmp_sel_cntl_out[2:0] = cntl_out[28:26];

   spc_mb2_ctlmsff_ctl_macro__width_3 cmp_sel_reg  (
               .scan_in(cmp_sel_reg_scanin),
               .scan_out(cmp_sel_reg_scanout),
               .l1clk    ( l1clk_pm1        ),
               .din      ( cmp_sel[2:0]     ),
               .dout     ( cmp_sel_out[2:0] ),
  .siclk(siclk),
  .soclk(soclk));

   assign cmp_sel[2:0]=(&cmp_sel_cntl_out[2:0] & ~array_4) ? cmp_sel_out[2:0] :
                        mb_user_cmpselinc_hold         ? user_cmpsel[2:0] :
                                                  cmp_sel_cntl_out[2:0];
   

   assign cmp_0      = cmp_sel[2:0]==3'b000;
   assign cmp_7      = cmp_sel[2:0]==3'b111;


   assign cntl_data_sel[1:0]          =   bisi_mode |
                                          mb_user_data_mode  ? 2'b11 :    cntl_out[25:24];    // data selection

   assign cntl_addr_mix               =   (bisi_mode | mb_user_addr_mode) ? 1'b1  :    cntl_out[23];    // address mix
   assign addr_mix                    =   (bisi_mode | mb_user_addr_mode) ? 1'b0  :    cntl_out[23];


   assign cntl_march_element[3:0]     =   sel_march_1_pass  ? 4'b1111:
                                                              cntl_out[22:19];    // march element


   assign cntl_algr[15:0] =       {cntl_msb,
                                   cntl_bisi,
                                   cntl_array_sel[3:0],
			                       cntl_cmp_sel[2:0],
			                       cntl_data_sel[1:0],
			                       cntl_addr_mix,
			                       cntl_march_element[3:0]};


   assign next_algr[15:0] = cout_addr ? cntl_algr[15:0] + 16'h1 : cntl_algr[15:0];         // mbist control

   // next algr
   assign cntl_in[34:19]   = reset_engine              ? {16'b000000_0000000000}:
     	                     ~run3                     ? cntl_algr[15:0]:	  
	                                                    next_algr[15:0];


   // reset_engine   run3    overflow   cout_rw    output
   // ---------------------------------------------------------
   //    1             x        x          x       start_addr
   //    0             0        x          x       cntl_addr
   //    0             1        1          x       restart_addr
   //    0             1        0          1       incred_addr
   //    0             1        0          0       cntl_addr                                     


   assign sel_nextaddr_reset    = reset_engine;
   assign sel_nextaddr_restart  = ~reset_engine & run3 & overflow;
   assign sel_nextaddr_incred   = ~reset_engine & run3 & ~overflow & cout_rw;
   assign sel_nextaddr_same     = ~(sel_nextaddr_reset | sel_nextaddr_restart | sel_nextaddr_incred);

   assign cntl_in[12:3] = ({10{sel_nextaddr_reset}} & start_addr[9:0]) |
                          ({10{sel_nextaddr_restart}} & restart_addr[9:0]) |
                          ({10{sel_nextaddr_incred}} & incred_addr[9:0]) |
                          ({10{sel_nextaddr_same}} & cntl_addr[9:0]);  
   

   assign incr_addr[9:0]  = mb_user_addr_mode ? user_incr_addr[9:0] : 10'b00_00000001;


   assign start_addr[9:0] = mb_user_addr_mode ? user_start_addr[9:0] : 10'b00_00000000;
   
   
   // assign next_addr_out[9:0] = cout_rw ? cntl_addr[9:0] + incr_addr[9:0] : cntl_addr[9:0];    // next address

   assign incred_addr[9:0] = cntl_addr[9:0] + incr_addr[9:0];


   assign overflow   = upaddr   ? ( cntl_addr[9:0] == stop_addr[9:0]) &  (cntl_rw[2:0]==3'b111):
                                  (~cntl_addr[9:0] == start_addr[9:0]) & (cntl_rw[2:0]==3'b111);


   // assign next_addr[9:0]= overflow ? restart_addr[9:0] : next_addr_out[9:0];
  
   assign restart_addr[9:0] = upaddr_pre ? start_addr[9:0] : ~stop_addr[9:0];
      
   assign cout_addr =  overflow;


   assign march_element_pre[3:0]=next_algr[3:0];

   assign march_pre_0   = ~(march_element_pre[3] | march_element_pre[2] |  march_element_pre[1] |  march_element_pre[0]);
   assign march_pre_1   = ~(march_element_pre[3] | march_element_pre[2] |  march_element_pre[1] | ~march_element_pre[0]);
   assign march_pre_2   = ~(march_element_pre[3] | march_element_pre[2] | ~march_element_pre[1] |  march_element_pre[0]);
   assign march_pre_6   = ~(march_element_pre[3] |~march_element_pre[2] | ~march_element_pre[1] |  march_element_pre[0]);
   assign march_pre_7   = ~(march_element_pre[3] | march_element_pre[3] | ~march_element_pre[2] | ~march_element_pre[1] | ~march_element_pre[0]); 
   

   assign upaddr_pre =     march_pre_0 | march_pre_1 | march_pre_2 | march_pre_6 | march_pre_7;


   /////////////////////////
   // rw engine
   /////////////////////////

   assign cntl_rw[2:0]                =   sel_rw_pass      ? 3'b111: 
                                                               cntl_out[ 2: 0];    // read write control

   assign next_rw[2:0] = cntl_rw[2:0]+3'b001 ;              

   
   assign cout_rw = &cntl_rw[2:0];     // carry over for rw 


   // next rw
   assign cntl_in[2:0]     = reset_engine  ? 3'b000 : 
	                         ~run3            ? cntl_rw[2:0]:
	                                                    next_rw[2:0];
   

    ////////////////////////////////////////////////////////////////////////////////
    // array selection
    ////////////////////////////////////////////////////////////////////////////////


    assign array_0     = array_sel[3:0]==4'h0;
    assign array_1     = array_sel[3:0]==4'h1;
    assign array_2     = array_sel[3:0]==4'h2;
    assign array_3     = array_sel[3:0]==4'h3;
    assign array_4     = array_sel[3:0]==4'h4;
    assign array_5     = array_sel[3:0]==4'h5;
//    assign array_end   = array_sel[3:0]==4'h5;


   assign last_array = array_5;


// /////////////////////////////////////////////////////////////////////////////
//
// MBIST Control Register
//
// /////////////////////////////////////////////////////////////////////////////
// standard membist
// /////////////////////////////////////////////////////////////////////////////
//   0       1       2       3      4      5          6         7        8
// ^(W0);^(R0W1);^(R1W0);v(R0W1);v(R1W0);v(R0);^(W1W0*R1R0W0);v(W1);^(W0W1*R0R1W1);
//   
// - there are 9 march elements in the engine
//   march_0 - march_8 indicate which march element it's in
//
// - for each march element, there are write and read sequences and for some
//   just write or just read
// 
// - for each march element, it can move upaddr (0-max) or downaddr (max-0)
//
//       march      rw       upaddr                    truedata
// --------------------------------------------------------------------------------
//    -  march_0    w          1    one_cycle_march       rw_0        ^(W0)
//    -  march_1    rw         1    two_cycle_march       rw_0        ^(R0W1)
//    -  march_2    rw         1    two_cycle_march       rw_1        ^(R1W0)
//    -  march_3    rw         0    two_cycle_march       rw_0        v(R0W1)
//    -  march_4    rw         0    two_cycle_march       rw_1        v(R1W0)
//    -  march_5    r          0    one_cycle_march       rw_0        v(R0)
//    -  march_6    wwrrw      1    five_cycle_march      rw_1,3,4    ^(W1W0*R1R0W0)
//    -  march_7    w          0    one_cycle_march       --          v(W1)
//    -  march_8    wwrrw      1    five_cycle_march      rw_0,2      ^(W0W1*R0R1W1)
// mbist address:
//    one_cycle_march  : march_0 | march_5 | march_7
//    five_cycle_march : march_6 | march_8
//    two_cycle_march  : ~(one_cycle_march | five_cycle_march)

   ////////////////////////////////////////////////////////////////////////////////
   //////  user mode signals

// the different between cntl_march and march is that march is before mux and
// and cntl_march is after mux

// IRF-shadow
// write: W1,S1,X,W0,restore
// rw   : R1,W1,S1,X,W0,restore

   spc_mb2_ctlmsff_ctl_macro__width_29 cntl_reg  (
                 .scan_in(cntl_reg_scanin),
                 .scan_out(cntl_reg_scanout),
                 .l1clk    ( l1clk_pm1                            ),
                 .din      ({cntl_in[34:19] ,cntl_in[12:0]}       ),
                 .dout     ({cntl_out[34:19],cntl_out[12:0]}      ),
  .siclk(siclk),
  .soclk(soclk));


   assign one_cycle_march  =  march_0 | march_5 | march_7;
   assign five_cycle_march =  march_6 | march_8;
   assign two_cycle_march  = ~(one_cycle_march | five_cycle_march);


   // this will indicate last march turn
   assign sel_march_1_pass = bisi_mode | ((mb_ten_n_mode | array_4) & march_5) | march_8;


   assign bisi_wr_mode = mb_default_bisi | mb_user_bisi_rw_mode ?  ~cntl_bisi & run3 :
                                                                   mb_user_bisi_wr_mode & run3;
                         
   assign bisi_rd_mode  =mb_default_bisi | mb_user_bisi_rw_mode ?  cntl_bisi & run3 :
                                                                   mb_user_bisi_rd_mode & run3;


   //  control for rw
   assign sel_rw_1_pass = bisi_mode | one_cycle_march ;

   assign sel_rw_2_pass = two_cycle_march;
   assign sel_rw_5_pass = five_cycle_march;

   assign sel_rw_pass = (run3 & sel_rw_1_pass & rw_0 & ~array_4) |
                        (run3 & sel_rw_2_pass & rw_1 & ~array_4) |
                        (run3 & sel_rw_5_pass & rw_4 & ~array_4) |
                        (run3 & array_4 & march_5 & rw_0)  |
                        (run3 & array_4 & march_0 & rw_5)  |
                        (run3 & array_4 & ~(march_5 | march_0) & rw_6) ;

   /////////////////////
   // true data
   ////////////////////


   assign true_data_l     =    bisi_mode |
                             (~array_4 & march_0)   |
                             (array_4 & march_0 & ~rw_3)   |
                             (~array_4 & march_1 & rw_0)   |
                             (array_4 & march_1 & (rw_0 | rw_4))   |
                             (~array_4 & march_2 & rw_1)   |
                             (array_4 & march_2 & (rw_1 | rw_4))   |
                             (~array_4 & march_3 & rw_0)   |
                             (array_4 & march_3 & (rw_0 | rw_4))   |
                             (~array_4 & march_4 & rw_1)   |
                             (array_4 & march_4 & (rw_1 | rw_4))   |
                             (march_5)   |
                             (march_6 & (rw_1 | rw_3 | rw_4))   |
                             (march_8 & (rw_0 | rw_2));

   assign true_data=~true_data_l;


   /////////////////////
   // membist data:
   ////////////////////

   assign data_pat_sel[7:0]        =     mb_user_data_mode                 ?    user_data[7:0]:
                                         bisi_mode                         ?    8'hFF:              
                                         (cntl_data_sel[1:0] == 2'h0)      ?    8'hAA:
                                         (cntl_data_sel[1:0] == 2'h1)      ?    8'h99:
                                         (cntl_data_sel[1:0] == 2'h2)      ?    8'hCC:
                                                                                8'h00;

   assign mem_data1[7:0]         = (true_data) ? data_pat_sel[7:0] : ~data_pat_sel[7:0];
   assign mem_data[7:0]         = ~array_4     ?   mem_data1[7:0] : 
                                   array_4 & bisi_mode ? 8'h00  :
                                                   ~mem_data1[7:0];

   /////////////////////
   // membist address:
   ////////////////////

   assign cntl_addr[9:0]   = cntl_out[12:3];

   assign adj_addr          = (five_cycle_march & (rw_1 | rw_3)) ? {cntl_addr[9:3],~cntl_addr[2],cntl_addr[1:0]}:
                                                                      cntl_addr[9:0] ;


   assign up_addr[9:0]    = upaddr   ?  adj_addr[9:0]:  ~adj_addr[9:0];


   /////////////////////////
   // membist write enable
   /////////////////////////

   
   assign mem_wr_pbi     =    (run3 & ~array_4 & (
                               march_0 |
                               ((march_1 | march_2 | march_3 | march_4 ) & rw_1) |
                               (march_6 & (rw_0 | rw_1 | rw_4)) |
                               march_7 |
                               (march_8 & (rw_0 | rw_1 | rw_4))
                               )) |
                         (run3 & array_4 & (
                               (march_0 & (rw_0 | rw_3)) |
                               ((march_1 | march_2 | march_3 | march_4 ) & (rw_1 | rw_4)) 
                               )) ;


   assign mem_wr = bisi_wr_mode ? mem_wr_pbi :
                   bisi_rd_mode ? 1'b0 :
                                  mem_wr_pbi;
   
   assign mem_save    = (run3 & array_4 & ((march_0 & rw_1) | (~march_0 & rw_2)));
   assign mem_restore = (run3 & array_4 & ((march_0 & rw_4) | (~march_0 & rw_5)));
   /////////////////////////
   // membist read enable
   /////////////////////////

                                            
   assign mem_rd_pbi         =  (~array_4 & run3 & ~mem_wr) |
                            ( array_4 & run3 & ~march_0 & rw_0);  
                                        
   assign mem_rd= bisi_rd_mode ? 1'b1 : mem_rd_pbi;
   // loop detection


   assign upaddr           =    march_0 | march_1 | march_2 | march_6 | march_7 | bisi_mode ;
                                
   
   // next_rw[1:0]
   
   
  assign array_sel_cntl_out[3:0]=cntl_out[32:29];


  spc_mb2_ctlmsff_ctl_macro__width_4 array_sel_reg  (
               .scan_in(array_sel_reg_scanin),
               .scan_out(array_sel_reg_scanout),
               .l1clk    ( l1clk_pm1          ),
               .din      ( array_sel[3:0]     ),
               .dout     ( array_sel_out[3:0] ),
  .siclk(siclk),
  .soclk(soclk));

   assign array_sel[3:0]=(&array_sel_cntl_out[3:0]) ? array_sel_out[3:0] :
                          user_mode                 ? user_array[3:0] :
                                                      array_sel_cntl_out[3:0];

   
  assign march_element_cntl_out[3:0]=cntl_out[22:19];


  spc_mb2_ctlmsff_ctl_macro__width_4 marche_element_reg  (
               .scan_in(marche_element_reg_scanin),
               .scan_out(marche_element_reg_scanout),
               .l1clk    ( l1clk_pm1          ),
               .din      ( march_element[3:0] ),
               .dout     ( march_element_out  ),
  .siclk(siclk),
  .soclk(soclk));

   assign march_element[3:0]=(&march_element_cntl_out[3:0]) ? march_element_out[3:0] :
                                                              march_element_cntl_out[3:0];


  assign rw[2:0]=cntl_out[2:0];


   ////////////////////////////////////   ////////////////////////////////////
   // mbist signals
   ////////////////////////////////////   ////////////////////////////////////
   
   assign mb_run=run;
//   assign mbist_cmp_sel[2:0]=~cntl_cmp_sel[2:0];
   assign mb_addr[15:0]=array_4 ? {6'b000000,cmp_sel[2:0],mem_addr[6:0]} : {6'b000000,mem_addr[9:0]};
   assign mb_write_data[7:0]=mem_data[7:0];


   // only one array read signal should be active   


   assign  mb_array_0_rd= array_0  & mem_rd;
   assign  mb_array_1_rd= array_1  & mem_rd;
   assign  mb_array_2_rd= array_2  & mem_rd;
   assign  mb_array_3_rd= (array_3 & mem_rd & ((|mem_addr[4:0]) | ~(|mem_data[7:0])) & ~bisi_mode) |
                          (array_4 & mem_rd & ((|mem_addr[4:0]) | ~(|mem_data[7:0])) & ~bisi_mode);
   assign  mb_array_save= mem_save;
   assign  mb_array_5_rd= array_5  & mem_rd;

   // only one array write signal should be active
  
 
   assign  mb_array_0_wr= array_0  & mem_wr;
   assign  mb_array_1_wr= array_1  & mem_wr;
   assign  mb_array_2_wr= array_2  & mem_wr;
   assign  mb_array_3_wr= (array_3 & mem_wr) | (array_4  & mem_wr);
   assign  mb_array_restore = mem_restore;
   assign  mb_array_5_wr= array_5  & mem_wr;   


// fail sigals from arrays


assign spu_arf_fail	=  mb2_arf_read_en_p2 & ~spu_mbi_arf_fail_;
assign spu_rrf_fail	=  mb2_rrf_read_en_p2 & ~spu_mbi_rrf_fail_;
assign spu_mam_fail	= (mb2_mam_read_en_p2 & ~spu_mbi_mam_fail_ ) |
         		  (mb2_mam_read_en_p2 & ~spu_mbi_mam_fail2_);

assign exu0_irf_fail	= (mb2_irf_read_en_p4 & ~exu0_mbi_irf_fail_[0] ) |
            		  (mb2_irf_read_en_p4 & ~exu0_mbi_irf_fail_[1]);
assign exu1_irf_fail	= (mb2_irf_read_en_p4 & ~exu1_mbi_irf_fail_[0] ) |
             		  (mb2_irf_read_en_p4 & ~exu1_mbi_irf_fail_[1]);
  

assign   arf_fail  = run3_transition ? 1'b0 : (spu_arf_fail | spu_arf_fail_sticky);
assign	 rrf_fail  = run3_transition ? 1'b0 : (spu_rrf_fail | spu_rrf_fail_sticky);
assign	 mam_fail  = run3_transition ? 1'b0 : (spu_mam_fail | spu_mam_fail_sticky);
assign	 irf0_fail = run3_transition ? 1'b0 : (exu0_irf_fail | exu0_irf_fail_sticky);
assign	 irf1_fail = run3_transition ? 1'b0 : (exu1_irf_fail | exu1_irf_fail_sticky);
assign	 frf_fail =  run3_transition ? 1'b0 : (fgu_mbi_frf_fail | fgu_frf_fail_sticky);


spc_mb2_ctlmsff_ctl_macro__width_6		fail_reg		 (
 .scan_in(fail_reg_scanin),
 .scan_out(fail_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ({arf_fail			,
	 rrf_fail			,
	 mam_fail			,
	 irf0_fail			,
	 irf1_fail			,
	 frf_fail}			),
 .dout ({spu_arf_fail_sticky		,
	 spu_rrf_fail_sticky		,
	 spu_mam_fail_sticky		,
	 exu0_irf_fail_sticky		,
	 exu1_irf_fail_sticky		,
	 fgu_frf_fail_sticky}		),
  .siclk(siclk),
  .soclk(soclk));


assign mbist_fail_sticky =      spu_arf_fail_sticky    |
                               spu_rrf_fail_sticky    |
                               spu_mam_fail_sticky    |
                               exu0_irf_fail_sticky	  |
                               exu1_irf_fail_sticky   |
                               fgu_frf_fail_sticky   ;


assign mbist_fail_array =   spu_arf_fail |
                            spu_rrf_fail |
                			spu_mam_fail |
                			exu0_irf_fail |
			                exu1_irf_fail |
			                fgu_mbi_frf_fail;

assign valid_fail=run3 | (stop_engine_l & ~mb_done);

assign mb_fail = mb_done ? mbist_fail_sticky  : mbist_fail_array & valid_fail;


////////////////////////////////////   ////////////////////////////////////
//  DONE LOGIC
////////////////////////////////////   ////////////////////////////////////


  spc_mb2_ctlmsff_ctl_macro__width_1  msb_latch  (
               .scan_in(msb_latch_scanin),
               .scan_out(msb_latch_scanout),
               .l1clk    ( l1clk_pm1	    ),
               .din      ( msb_in    ),
               .dout     ( msb_out  ),
  .siclk(siclk),
  .soclk(soclk));
   
   assign msb_in= (~start_in ) | (mb_user_loop_mode & mb_done) ? 1'b0 :
                   (cntl_msb)                                  ? 1'b1 :
                                                                 msb_out;

   
   assign stop_engine_l     =  start_in  & cntl_msb;


   assign mb_done=msb_out & (done_delay[4:0]==5'b11110);

   assign  run3   = &done_delay[4:1] & ~stop_engine_l & start_in;


   spc_mb2_ctlmsff_ctl_macro__width_1 run3_transition_reg  (
                  .scan_in(run3_transition_reg_scanin),
                  .scan_out(run3_transition_reg_scanout),
                  .l1clk    ( l1clk_pm1	          ),
                  .din      ( run3  ),
                  .dout     ( run3_out    ),
  .siclk(siclk),
  .soclk(soclk));

   assign run3_transition = run3 & ~run3_out;
   
   spc_mb2_ctlmsff_ctl_macro__width_5 done_delay_reg  (
                  .scan_in(done_delay_reg_scanin),
                  .scan_out(done_delay_reg_scanout),
                  .l1clk    ( l1clk_pm1	          ),
                  .din      ( done_delay_in[4:0]  ),
                  .dout     ( done_delay[4:0]    ),
  .siclk(siclk),
  .soclk(soclk));


   assign done_delay_in[4:0] = run3      ?  5'b11111 :
                               mb_done   ?  5'b11110 :
                               (run & ~run3) ? done_delay[4:0] + 5'b00001 :
                                                   5'b00000;


////////////////////////////////////   ////////////////////////////////////
//  FAIL LOGIC
////////////////////////////////////   ////////////////////////////////////


spc_mb2_ctlmsff_ctl_macro__width_1		out_run_mb_arrays_reg		 (
 .scan_in(out_run_mb_arrays_reg_scanin),
 .scan_out(out_run_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_run				),
 .dout ( mb_run_out			),
  .siclk(siclk),
  .soclk(soclk));


spc_mb2_ctlmsff_ctl_macro__width_8		out_data_mb_arrays_reg		 (
 .scan_in(out_data_mb_arrays_reg_scanin),
 .scan_out(out_data_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_write_data[7:0]		),
 .dout ( mb_write_data_out[7:0]		),
  .siclk(siclk),
  .soclk(soclk));


spc_mb2_ctlmsff_ctl_macro__width_16		out_addr_mb_arrays_reg		 (
 .scan_in(out_addr_mb_arrays_reg_scanin),
 .scan_out(out_addr_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( mb_addr[15:0]			),
 .dout ( mb_addr_out[15:0]		),
  .siclk(siclk),
  .soclk(soclk));


spc_mb2_ctlmsff_ctl_macro__width_5		out_wr_mb_arrays_reg		 (
 .scan_in(out_wr_mb_arrays_reg_scanin),
 .scan_out(out_wr_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( {
          mb_array_0_wr		,
     	  mb_array_1_wr		,
	  mb_array_2_wr,
	  mb_array_3_wr,
	  mb_array_5_wr
         }		),
 .dout ({ 
          mb_array_0_wr_out		,
       	  mb_array_1_wr_out		,
   	  mb_array_2_wr_out,
   	  mb_array_3_wr_out,
   	  mb_array_5_wr_out
        }		),
  .siclk(siclk),
  .soclk(soclk));


spc_mb2_ctlmsff_ctl_macro__width_5		out_rd_mb_arrays_reg		 (
 .scan_in(out_rd_mb_arrays_reg_scanin),
 .scan_out(out_rd_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ( {
          mb_array_0_rd,
     	  mb_array_1_rd,
	  mb_array_2_rd,
	  mb_array_3_rd,
	  mb_array_5_rd
          }		),
 .dout ({ 
          mb_array_0_rd_out,
          mb_array_1_rd_out,
          mb_array_2_rd_out,
          mb_array_3_rd_out,
          mb_array_5_rd_out
        }		),
  .siclk(siclk),
  .soclk(soclk));


assign mb2_run=mb_run_out;
assign mb2_write_data[7:0]=mb_write_data_out[7:0];
assign mb2_addr[15:0]=mb_addr_out[15:0];


assign mb2_arf_write_en=mb_array_0_wr_out;
assign mb2_rrf_write_en=mb_array_1_wr_out;
assign mb2_mam_write_en=mb_array_2_wr_out;
assign mb2_irf_write_en=mb_array_3_wr_out;
assign mb2_frf_write_en=mb_array_5_wr_out;

assign mb2_arf_read_en=mb_array_0_rd_out;
assign mb2_rrf_read_en=mb_array_1_rd_out;
assign mb2_mam_read_en=mb_array_2_rd_out;
assign mb2_irf_read_en=mb_array_3_rd_out;
assign mb2_frf_read_en=mb_array_5_rd_out;


spc_mb2_ctlmsff_ctl_macro__width_1  out_mb_tcu_done_reg  (
               .scan_in(out_mb_tcu_done_reg_scanin),
               .scan_out(out_mb_tcu_done_reg_scanout),
               .l1clk    ( l1clk_pm1	),
               .din      ( mb_done      ),
               .dout     ( mb_done_out  ),
  .siclk(siclk),
  .soclk(soclk));


spc_mb2_ctlmsff_ctl_macro__width_1 out_mb_tcu_fail_reg  (
               .scan_in(out_mb_tcu_fail_reg_scanin),
               .scan_out(out_mb_tcu_fail_reg_scanout),
               .l1clk    ( l1clk_pm1	 ),
               .din      (  mb_fail      ),
               .dout     (  mb_fail_out  ),
  .siclk(siclk),
  .soclk(soclk));


assign mb2_done=mb_done_out;
assign mb2_mbist_fail=mb_fail_out;

    // spare gates:


    spc_mb2_ctlspare_ctl_macro__num_3 spares  (
      .scan_in(spares_scanin),
      .scan_out(spares_scanout),
      .l1clk	(l1clk_pm1),
  .siclk(siclk),
  .soclk(soclk)
      );


   ////////////////////////////////////////////////////////////////////////////////
   // UNIQUE TO ENGINE
   ////////////////////////////////////////////////////////////////////////////////

//   assign first_six_march =~(march_6 | march_7 | march_8);


   // END UNIQUE   


spc_mb2_ctlmsff_ctl_macro__width_4		i_delay_4th		 (
 .scan_in(i_delay_4th_scanin),
 .scan_out(i_delay_4th_scanout),
 .l1clk( l1clk_pm1			),
 .din  ({mb2_irf_read_en		,
	 mb2_irf_read_en_p1		,
	 mb2_irf_read_en_p2		,
	 mb2_irf_read_en_p3}		),
 .dout ({mb2_irf_read_en_p1		,
	 mb2_irf_read_en_p2		,
	 mb2_irf_read_en_p3		,
	 mb2_irf_read_en_p4}		),
  .siclk(siclk),
  .soclk(soclk));


// delayed compare read and data signals

spc_mb2_ctlmsff_ctl_macro__width_22		delayed_cmp_rd_data_reg		 (
 .scan_in(delayed_cmp_rd_data_reg_scanin),
 .scan_out(delayed_cmp_rd_data_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ({mb2_arf_read_en		,
	 mb2_mam_read_en		,
	 mb2_rrf_read_en		,
	 mb2_write_data[7:0]		,
	 mb2_arf_read_en_p1		,
	 mb2_mam_read_en_p1		,
	 mb2_rrf_read_en_p1		,
	 mb2_write_data_p1[7:0]}	),
 .dout ({mb2_arf_read_en_p1		,
	 mb2_mam_read_en_p1		,
	 mb2_rrf_read_en_p1		,
	 mb2_write_data_p1[7:0]		,
	 mb2_arf_read_en_p2		,
	 mb2_mam_read_en_p2		,
	 mb2_rrf_read_en_p2		,
	 mb2_write_data_p2[7:0]}	),
  .siclk(siclk),
  .soclk(soclk));


// save and restore signals to arrays


spc_mb2_ctlmsff_ctl_macro__width_2		out_save_restore_mb_arrays_reg		 (
 .scan_in(out_save_restore_mb_arrays_reg_scanin),
 .scan_out(out_save_restore_mb_arrays_reg_scanout),
 .l1clk( l1clk_pm1			),
 .din  ({mb_array_save			,
    	 mb_array_restore}		),
 .dout ({mb2_irf_save_en		,
	 mb2_irf_restore_en}		),
  .siclk(siclk),
  .soclk(soclk));


// fixscan start:
assign pmen_scanin               = scan_in                  ;
assign input_signals_reg_scanin  = pmen_scanout             ;
assign mb_enable_reg_scanin      = input_signals_reg_scanout;
assign config_reg_scanin         = mb_enable_reg_scanout    ;
assign loop_again_reg_scanin     = config_reg_scanout       ;
assign array_usr_reg_scanin      = loop_again_reg_scanout   ;
assign user_addr_mode_reg_scanin = array_usr_reg_scanout    ;
assign user_start_addr_reg_scanin = user_addr_mode_reg_scanout;
assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout;
assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout;
assign user_data_mode_reg_scanin = user_incr_addr_reg_scanout;
assign user_data_reg_scanin      = user_data_mode_reg_scanout;
assign user_cmpselinc_hold_reg_scanin = user_data_reg_scanout    ;
assign user_cmpsel_reg_scanin    = user_cmpselinc_hold_reg_scanout;
assign user_loop_mode_reg_scanin = user_cmpsel_reg_scanout  ;
assign ten_n_mode_reg_scanin     = user_loop_mode_reg_scanout;
assign user_bisi_wr_mode_reg_scanin = ten_n_mode_reg_scanout   ;
assign user_bisi_rd_mode_reg_scanin = user_bisi_wr_mode_reg_scanout;
assign cmp_sel_reg_scanin        = user_bisi_rd_mode_reg_scanout;
assign cntl_reg_scanin           = cmp_sel_reg_scanout      ;
assign array_sel_reg_scanin      = cntl_reg_scanout         ;
assign marche_element_reg_scanin = array_sel_reg_scanout    ;
assign fail_reg_scanin           = marche_element_reg_scanout;
assign msb_latch_scanin          = fail_reg_scanout         ;
assign run3_transition_reg_scanin = msb_latch_scanout        ;
assign done_delay_reg_scanin     = run3_transition_reg_scanout;
assign out_run_mb_arrays_reg_scanin = done_delay_reg_scanout   ;
assign out_data_mb_arrays_reg_scanin = out_run_mb_arrays_reg_scanout;
assign out_addr_mb_arrays_reg_scanin = out_data_mb_arrays_reg_scanout;
assign out_wr_mb_arrays_reg_scanin = out_addr_mb_arrays_reg_scanout;
assign out_rd_mb_arrays_reg_scanin = out_wr_mb_arrays_reg_scanout;
assign out_mb_tcu_done_reg_scanin = out_rd_mb_arrays_reg_scanout;
assign out_mb_tcu_fail_reg_scanin = out_mb_tcu_done_reg_scanout;
assign spares_scanin             = out_mb_tcu_fail_reg_scanout;
assign i_delay_4th_scanin        = spares_scanout           ;
assign delayed_cmp_rd_data_reg_scanin = i_delay_4th_scanout      ;
assign out_save_restore_mb_arrays_reg_scanin = delayed_cmp_rd_data_reg_scanout;
assign scan_out                  = out_save_restore_mb_arrays_reg_scanout;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctll1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_29 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [28:0] fdin;
wire [27:0] so;

  input [28:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [28:0] dout;
  output scan_out;
assign fdin[28:0] = din[28:0];


dff #(29)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[28:0]),
.si({scan_in,so[27:0]}),
.so({so[27:0],scan_out}),
.q(dout[28:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module spc_mb2_ctlspare_ctl_macro__num_3 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));
assign scan_out = so_2;


endmodule


// any PARAMS parms go into naming of macro

module spc_mb2_ctlmsff_ctl_macro__width_22 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [21:0] fdin;
wire [20:0] so;

  input [21:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [21:0] dout;
  output scan_out;
assign fdin[21:0] = din[21:0];


dff #(22)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[21:0]),
.si({scan_in,so[20:0]}),
.so({so[20:0],scan_out}),
.q(dout[21:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spc_msf0_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module spc_msf0_dp (
  l2clk, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_se_scancollar_out, 
  tcu_atpg_mode, 
  scan_in, 
  lb_lbist_running, 
  slow_cmp_sync_en, 
  cmp_slow_sync_en, 
  ncu_cmp_tick_enable, 
  ncu_wmr_vec_mask, 
  tcu_ss_mode, 
  tcu_do_mode, 
  tcu_mbist_user_mode, 
  tcu_mbist_bisi_en, 
  tcu_ss_request, 
  tcu_core_running, 
  tcu_shscan_clk_stop, 
  tcu_shscanid, 
  efu_spc_fuse_data, 
  efu_spc_fuse_ixfer_en, 
  efu_spc_fuse_dxfer_en, 
  efu_spc_fuse_iclr, 
  efu_spc_fuse_dclr, 
  spc_efu_fuse_ddata, 
  spc_efu_fuse_idata, 
  spc_efu_fuse_ixfer_en, 
  spc_efu_fuse_dxfer_en, 
  efu_spc_fuse_data_buf, 
  efu_spc_fuse_ixfer_en_buf, 
  efu_spc_fuse_dxfer_en_buf, 
  efu_spc_fuse_iclr_buf, 
  efu_spc_fuse_dclr_buf, 
  spc_efu_fuse_ddata_buf, 
  spc_efu_fuse_idata_buf, 
  spc_efu_fuse_ixfer_en_buf, 
  spc_efu_fuse_dxfer_en_buf, 
  tlu_core_running_status, 
  tlu_ss_complete, 
  tlu_hardstop_request, 
  tlu_softstop_request, 
  tlu_trigger_pulse, 
  tlu_dbg_instr_cmt_grp0, 
  tlu_dbg_instr_cmt_grp1, 
  scan_out, 
  msf0_cmp_tick_enable, 
  msf0_wmr_vec_mask, 
  msf0_ss_mode, 
  msf0_do_mode, 
  msf0_ss_request, 
  msf0_core_running, 
  msf0_shscan_clk_stop, 
  msf0_shscanid, 
  msf0_mbist_user_mode_ff, 
  msf0_mbist_bisi_en_ff, 
  msf0_atpg_mode_buf, 
  spc_core_running_status, 
  spc_ss_complete, 
  spc_hardstop_request, 
  spc_softstop_request, 
  spc_trigger_pulse, 
  spc_dbg_instr_cmt_grp0, 
  spc_dbg_instr_cmt_grp1, 
  power_throttle, 
  power_throttle_buf);
wire stop;
wire en;
wire clk;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire bank0_lat_scanin;
wire bank0_lat_scanout;
wire cmp_slow_sync_en_ff;
wire [7:0] tlu_core_running_status_rep0;
wire tlu_ss_complete_rep0;
wire tlu_hardstop_request_rep0;
wire tlu_softstop_request_rep0;
wire tlu_trigger_pulse_rep0;
wire [1:0] tlu_dbg_instr_cmt_grp0_rep0;
wire [1:0] tlu_dbg_instr_cmt_grp1_rep0;
wire bank1_lat_scanin;
wire bank1_lat_scanout;
wire tcu_ss_request_rep0;
wire bank2_lat_scanin;
wire bank2_lat_scanout;
wire slow_cmp_sync_en_ff;
wire efu_spc_fuse_data_bufin;
wire efu_spc_fuse_ixfer_en_bufin;
wire efu_spc_fuse_dxfer_en_bufin;
wire efu_spc_fuse_iclr_bufin;
wire efu_spc_fuse_dclr_bufin;
wire lb_lbist_running_n1;
wire lb_efu_spc_fuse_data;
wire lb_efu_spc_fuse_ixfer_en;
wire lb_efu_spc_fuse_dxfer_en;
wire lb_efu_spc_fuse_iclr;
wire lb_efu_spc_fuse_dclr;
wire ncu_cmp_tick_enable_rep0;
wire [7:0] tcu_core_running_rep0;
wire ncu_wmr_vec_mask_rep0;
wire bank3_lat_scanin;
wire bank3_lat_scanout;
wire tcu_ss_mode_rep0;
wire tcu_mbist_user_mode_rep0;
wire tcu_mbist_bisi_en_rep0;
wire tcu_do_mode_rep0;
wire bank4_lat_scanin;
wire bank4_lat_scanout;
wire [2:0] tcu_shscanid_rep0;
wire tcu_shscan_clk_stop_rep0;
wire bank5_lat_scanin;
wire bank5_lat_scanout;


input		l2clk;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		tcu_se_scancollar_out;
input		tcu_atpg_mode;
input 		scan_in;

input		lb_lbist_running;

input		slow_cmp_sync_en;
input		cmp_slow_sync_en;

// Core inputs before the MSFF
input		ncu_cmp_tick_enable;
input		ncu_wmr_vec_mask;
input		tcu_ss_mode;
input		tcu_do_mode;
input		tcu_mbist_user_mode;
input		tcu_mbist_bisi_en;
input		tcu_ss_request;
input	[7:0]	tcu_core_running;
input		tcu_shscan_clk_stop;	
input	[2:0]	tcu_shscanid;		

input		efu_spc_fuse_data;	
input		efu_spc_fuse_ixfer_en;	
input		efu_spc_fuse_dxfer_en;	
input		efu_spc_fuse_iclr;	
input		efu_spc_fuse_dclr;	

output		spc_efu_fuse_ddata;	
output		spc_efu_fuse_idata;	
output		spc_efu_fuse_ixfer_en;	
output		spc_efu_fuse_dxfer_en;	

output		efu_spc_fuse_data_buf;	
output		efu_spc_fuse_ixfer_en_buf;	
output		efu_spc_fuse_dxfer_en_buf;	
output		efu_spc_fuse_iclr_buf;	
output		efu_spc_fuse_dclr_buf;	

input		spc_efu_fuse_ddata_buf;	
input 		spc_efu_fuse_idata_buf;	
input		spc_efu_fuse_ixfer_en_buf;
input		spc_efu_fuse_dxfer_en_buf;

// Core outputs before the MSFF
input	[7:0]	tlu_core_running_status;
input		tlu_ss_complete;
input		tlu_hardstop_request;
input		tlu_softstop_request;
input 		tlu_trigger_pulse;
input 	[1:0]	tlu_dbg_instr_cmt_grp0;
input 	[1:0]	tlu_dbg_instr_cmt_grp1;

output		scan_out;

// Core inputs after the MSFF
output		msf0_cmp_tick_enable;
output		msf0_wmr_vec_mask;
output		msf0_ss_mode;
output		msf0_do_mode;
output		msf0_ss_request;
output	[7:0]	msf0_core_running;
output		msf0_shscan_clk_stop;	
output	[2:0]	msf0_shscanid;		
output          msf0_mbist_user_mode_ff;
output          msf0_mbist_bisi_en_ff;
output		msf0_atpg_mode_buf;

// Core outputs after the MSFF
output	[7:0]	spc_core_running_status;
output		spc_ss_complete;
output		spc_hardstop_request;
output		spc_softstop_request;
output 		spc_trigger_pulse;
output 	[1:0]	spc_dbg_instr_cmt_grp0;
output 	[1:0]	spc_dbg_instr_cmt_grp1;

input	[2:0]	power_throttle;
output	[2:0] power_throttle_buf;


//////////////////////////////////////////////////////////////////////

assign stop	= 1'b0;
assign en	= 1'b1;
assign clk	= l2clk;

assign pce_ov	= tcu_pce_ov;
assign se	= tcu_scan_en;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;

//////////////////////////////////////////////////////////////////////


spc_msf0_dpmsff_macro__stack_10r__width_8 bank0_lat   (
        .scan_in(bank0_lat_scanin),
        .scan_out(bank0_lat_scanout),
        .en     (cmp_slow_sync_en_ff),
	.din	(tlu_core_running_status	[7:0]	),
	.dout	(tlu_core_running_status_rep0	[7:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_8 bank0_rep   (
        .din(tlu_core_running_status_rep0[7:0]),
        .dout(spc_core_running_status[7:0])
);

//inv_macro bank1_inv (width=1) (
//        .din(lb_lbist_running),
//        .dout(lb_lbist_running_n)
//);

//buff_macro bank1_rep0 (width=3,stack=none,dbuff=16x,rep=1) (
//        .din    (power_throttle[2:0]),
//        .dout   (power_throttle_bufin[2:0])
//);

//and_macro bank1_and (width=3) (
//        .din0   (power_throttle_bufin[2:0]),
//        .din1   ({3 {lb_lbist_running_n}}),
//        .dout   (lb_power_throttle[2:0])
//);

spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_11 bank1_rep1  (
	.din	({tlu_ss_complete_rep0		       ,
		  tlu_hardstop_request_rep0	       ,
		  tlu_softstop_request_rep0	       ,
                  power_throttle[2:0]                  ,
		  tlu_trigger_pulse_rep0	       ,
		  tlu_dbg_instr_cmt_grp0_rep0	[1:0],
		  tlu_dbg_instr_cmt_grp1_rep0	[1:0]}),
	.dout	({spc_ss_complete		       ,
		  spc_hardstop_request 	               ,
		  spc_softstop_request	               ,
                  power_throttle_buf[2:0]              ,
		  spc_trigger_pulse		       ,
		  spc_dbg_instr_cmt_grp0	[1:0],
		  spc_dbg_instr_cmt_grp1	[1:0]})
);

spc_msf0_dpmsff_macro__stack_8r__width_8 bank1_lat   (
	.scan_in(bank1_lat_scanin),
	.scan_out(bank1_lat_scanout),
	.din	({tlu_ss_complete	        ,
		  tlu_hardstop_request	        ,
		  tlu_softstop_request	        ,
		  tlu_trigger_pulse		,
		  tlu_dbg_instr_cmt_grp0	[1:0],
		  tlu_dbg_instr_cmt_grp1	[1:0]}),
	.dout	({tlu_ss_complete_rep0		,
		  tlu_hardstop_request_rep0     ,
		  tlu_softstop_request_rep0     ,
		  tlu_trigger_pulse_rep0	,
		  tlu_dbg_instr_cmt_grp0_rep0	[1:0],
		  tlu_dbg_instr_cmt_grp1_rep0	[1:0]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1 bank2_rep1  (
       .din    (tcu_ss_request                       ),
       .dout   (tcu_ss_request_rep0                  )
);

spc_msf0_dpmsff_macro__stack_8r__width_3 bank2_lat   (
	.scan_in(bank2_lat_scanin),
	.scan_out(bank2_lat_scanout),
	.se	( tcu_se_scancollar_out			),
	.din    ({slow_cmp_sync_en                       ,
                  cmp_slow_sync_en                       ,
		  tcu_ss_request_rep0		       }),
        .dout   ({slow_cmp_sync_en_ff                  ,
                  cmp_slow_sync_en_ff                  ,
		  msf0_ss_request		       }),
  .clk(clk),
  .en(en),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

spc_msf0_dpbuff_macro__dbuff_16x__rep_1__stack_none__width_5 bank3_rep0  (
        .din    ({efu_spc_fuse_data, 
                  efu_spc_fuse_ixfer_en, 
		  efu_spc_fuse_dxfer_en,	
		  efu_spc_fuse_iclr,	
		  efu_spc_fuse_dclr}),	
        .dout   ({efu_spc_fuse_data_bufin, 
                  efu_spc_fuse_ixfer_en_bufin, 
		  efu_spc_fuse_dxfer_en_bufin,	
		  efu_spc_fuse_iclr_bufin,	
		  efu_spc_fuse_dclr_bufin})	
);

spc_msf0_dpinv_macro__width_1 bank3_inv  (
        .din(lb_lbist_running),
        .dout(lb_lbist_running_n1)
);

spc_msf0_dpand_macro__width_5 bank3_and  (
        .din0   ({efu_spc_fuse_data_bufin, 
                  efu_spc_fuse_ixfer_en_bufin, 
		  efu_spc_fuse_dxfer_en_bufin,	
		  efu_spc_fuse_iclr_bufin,	
		  efu_spc_fuse_dclr_bufin}),	
        .din1   ({5 {lb_lbist_running_n1}}),
        .dout   ({lb_efu_spc_fuse_data, 
                  lb_efu_spc_fuse_ixfer_en, 
		  lb_efu_spc_fuse_dxfer_en,	
		  lb_efu_spc_fuse_iclr,	
		  lb_efu_spc_fuse_dclr})	

);

spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_19 bank3_rep1  (
	.din	({ncu_cmp_tick_enable		       ,
                  tcu_core_running[7:0],
   		  lb_efu_spc_fuse_data,	
		  lb_efu_spc_fuse_ixfer_en,	
		  lb_efu_spc_fuse_dxfer_en,	
		  lb_efu_spc_fuse_iclr,	
		  lb_efu_spc_fuse_dclr,	
  		  spc_efu_fuse_ddata_buf,	
		  spc_efu_fuse_idata_buf,	
		  spc_efu_fuse_ixfer_en_buf,	
		  spc_efu_fuse_dxfer_en_buf,	
                  ncu_wmr_vec_mask		       }),
	.dout	({ncu_cmp_tick_enable_rep0	       ,
                  tcu_core_running_rep0[7:0],
   		  efu_spc_fuse_data_buf,	
		  efu_spc_fuse_ixfer_en_buf,	
		  efu_spc_fuse_dxfer_en_buf,	
		  efu_spc_fuse_iclr_buf,	
		  efu_spc_fuse_dclr_buf,	
  		  spc_efu_fuse_ddata,	
		  spc_efu_fuse_idata,	
		  spc_efu_fuse_ixfer_en,	
		  spc_efu_fuse_dxfer_en,	
                  ncu_wmr_vec_mask_rep0		       })
);

spc_msf0_dpmsff_macro__stack_10r__width_10 bank3_lat   (
	.scan_in(bank3_lat_scanin),
	.scan_out(bank3_lat_scanout),
	.se	( tcu_se_scancollar_out			),
        .en	( slow_cmp_sync_en_ff),
	.din	({ncu_cmp_tick_enable_rep0		       ,
                  tcu_core_running_rep0[7:0],
                  ncu_wmr_vec_mask_rep0		       }),
	.dout	({msf0_cmp_tick_enable		       ,
		  msf0_core_running[7:0]	       ,
                  msf0_wmr_vec_mask                    }),
  .clk(clk),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 bank4_rep1  (
	.din    ({tcu_atpg_mode,
                  tcu_ss_mode,
                  tcu_mbist_user_mode,
                  tcu_mbist_bisi_en,
		  tcu_do_mode			       }),
	.dout    ({msf0_atpg_mode_buf,
                  tcu_ss_mode_rep0,
                  tcu_mbist_user_mode_rep0,
                  tcu_mbist_bisi_en_rep0,
		  tcu_do_mode_rep0		 })
);

spc_msf0_dpmsff_macro__stack_8r__width_4 bank4_lat   (
	.scan_in(bank4_lat_scanin),
	.scan_out(bank4_lat_scanout),
	.se	( tcu_se_scancollar_out			),
        .en	( slow_cmp_sync_en_ff),
	.din    ({tcu_ss_mode_rep0,
                  tcu_mbist_user_mode_rep0,
                  tcu_mbist_bisi_en_rep0,
		  tcu_do_mode_rep0		       }),
        .dout   ({msf0_ss_mode,
                  msf0_mbist_user_mode_ff,
                  msf0_mbist_bisi_en_ff,
		  msf0_do_mode			       }),
  .clk(clk),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_4 bank5_rep1  (
	.din	({tcu_shscanid			[2:0],
                  tcu_shscan_clk_stop		}),
	.dout	({tcu_shscanid_rep0		[2:0],
                  tcu_shscan_clk_stop_rep0	})
);

spc_msf0_dpmsff_macro__stack_8r__width_4 bank5_lat   (
	.scan_in(bank5_lat_scanin),
	.scan_out(bank5_lat_scanout),
	.se	( tcu_se_scancollar_out			),
        .en	( slow_cmp_sync_en_ff),
	.din	({tcu_shscanid_rep0		[2:0],
                  tcu_shscan_clk_stop_rep0	       }),
	.dout	({msf0_shscanid			[2:0],
                  msf0_shscan_clk_stop		       }),
  .clk(clk),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// fixscan start:
assign bank0_lat_scanin          = scan_in                  ;
assign bank1_lat_scanin          = bank0_lat_scanout        ;
assign bank2_lat_scanin          = bank1_lat_scanout        ;
assign bank3_lat_scanin          = bank2_lat_scanout        ;
assign bank4_lat_scanin          = bank3_lat_scanout        ;
assign bank5_lat_scanin          = bank4_lat_scanout        ;
assign scan_out                  = bank5_lat_scanout        ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module spc_msf0_dpmsff_macro__stack_10r__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_11 (
  din, 
  dout);
  input [10:0] din;
  output [10:0] dout;


buff #(11)  d0_0 (
.in(din[10:0]),
.out(dout[10:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_msf0_dpmsff_macro__stack_8r__width_8 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [6:0] so;

  input [7:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [7:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_msf0_dpmsff_macro__stack_8r__width_3 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [1:0] so;

  input [2:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [2:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


//
//   buff macro
//
//


module spc_msf0_dpbuff_macro__dbuff_16x__rep_1__stack_none__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   invert macro
//
//


module spc_msf0_dpinv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module spc_msf0_dpand_macro__width_5 (
  din0, 
  din1, 
  dout);
  input [4:0] din0;
  input [4:0] din1;
  output [4:0] dout;


and2 #(5)  d0_0 (
.in0(din0[4:0]),
.in1(din1[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_19 (
  din, 
  dout);
  input [18:0] din;
  output [18:0] dout;


buff #(19)  d0_0 (
.in(din[18:0]),
.out(dout[18:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_msf0_dpmsff_macro__stack_10r__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


//
//   buff macro
//
//


module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_msf0_dpmsff_macro__stack_8r__width_4 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [2:0] so;

  input [3:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [3:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spc_msf1_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module spc_msf1_dp (
  l2clk, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_se_scancollar_out, 
  scan_in, 
  scan_out, 
  tcu_spc_mbist_start, 
  spc_mbist_fail_buf, 
  spc_mbist_done_buf, 
  tcu_spc_mbist_start_ff, 
  spc_mbist_fail_ff, 
  spc_mbist_done_ff);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire en;
wire clk;
wire tcu_spc_mbist_start_rep0;
wire bank0_lat_scanin;
wire bank0_lat_scanout;


input		l2clk;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_se_scancollar_out;
input 		scan_in;
output		scan_out;

// Core I/O before the MSFF
input		tcu_spc_mbist_start;
input		spc_mbist_fail_buf;
input		spc_mbist_done_buf;

// Core I/O after the MSFF
output		tcu_spc_mbist_start_ff;
output		spc_mbist_fail_ff;
output		spc_mbist_done_ff;

//////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign en	= 1'b1;
assign clk	= l2clk;


//////////////////////////////////////////////////////////////////////


spc_msf1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1 chip_io_rep0  (
        .din(tcu_spc_mbist_start),
        .dout(tcu_spc_mbist_start_rep0)
);

spc_msf1_dpmsff_macro__stack_8r__width_3 bank0_lat   (
	.scan_in(bank0_lat_scanin),
	.scan_out(bank0_lat_scanout),
	.se	( tcu_se_scancollar_out						),
	.din	({tcu_spc_mbist_start_rep0, spc_mbist_fail_buf, spc_mbist_done_buf}),
	.dout	({tcu_spc_mbist_start_ff, spc_mbist_fail_ff, spc_mbist_done_ff}	),
  .clk(clk),
  .en(en),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// fixscan start:
assign bank0_lat_scanin          = scan_in                  ;
assign scan_out                  = bank0_lat_scanout        ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module spc_msf1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module spc_msf1_dpmsff_macro__stack_8r__width_3 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [1:0] so;

  input [2:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [2:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spc_rep1_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module spc_rep1_dp (
  exu_address0_e, 
  exu_address1_e, 
  exu_address0_e_rep0, 
  exu_address1_e_rep0, 
  exu_address0_e_rep01, 
  exu_address1_e_rep01, 
  fgu_exu_result_fx5, 
  fgu_exu_result_fx5_rep0, 
  fgu_exu_result_fx5_rep1, 
  lsu_exu_ld_data_b, 
  lsu_exu_ld_data_b_rep00, 
  lsu_exu_ld_data_b_rep01, 
  fgu_cecc_fx2, 
  fgu_uecc_fx2, 
  fgu_cecc_fx2_rep1, 
  fgu_uecc_fx2_rep1, 
  pce_ov, 
  spc_aclk, 
  spc_bclk, 
  spc_aclk_wmr, 
  lb_scan_en, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_scan_en, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  rst_wmr_protect, 
  dmo_dcmuxctl, 
  hver_mask_minor_rev, 
  scan_out, 
  tcu_shscan_pce_ov, 
  tcu_shscan_aclk, 
  tcu_shscan_bclk, 
  tcu_shscan_scan_in, 
  tcu_shscan_scan_en, 
  spc_shscan_scan_out, 
  cluster_arst_l, 
  tcu_spc_mbist_scan_in, 
  tcu_spc_mbist_start_ff, 
  spc_mbist_fail, 
  spc_mbist_done, 
  spc_tcu_mbist_scan_out, 
  tcu_spc_lbist_start, 
  tcu_spc_lbist_scan_in, 
  tcu_spc_lbist_pgm, 
  tcu_spc_test_mode, 
  spc_tcu_lbist_done, 
  spc_tcu_lbist_scan_out, 
  scan_in_buf, 
  tcu_pce_ov_buf, 
  tcu_aclk_buf, 
  tcu_bclk_buf, 
  tcu_dectest_buf, 
  tcu_muxtest_buf, 
  tcu_scan_en_buf, 
  tcu_array_wr_inhibit_buf, 
  tcu_se_scancollar_in_buf, 
  tcu_se_scancollar_out_buf, 
  rst_wmr_protect_buf, 
  dmo_dcmuxctl_buf, 
  hver_mask_minor_rev_buf, 
  scan_out_buf, 
  tcu_shscan_pce_ov_buf, 
  tcu_shscan_aclk_buf, 
  tcu_shscan_bclk_buf, 
  tcu_shscan_scan_in_buf, 
  tcu_shscan_scan_en_buf, 
  spc_shscan_scan_out_buf, 
  cluster_arst_l_buf, 
  tcu_spc_mbist_scan_in_buf, 
  tcu_spc_mbist_start_buf0, 
  spc_mbist_fail_ff, 
  spc_mbist_done_ff, 
  spc_tcu_mbist_scan_out_buf, 
  tcu_spc_lbist_start_buf, 
  tcu_spc_lbist_scan_in_buf, 
  tcu_spc_lbist_pgm_buf, 
  tcu_spc_test_mode_buf, 
  lb_lbist_done, 
  spc_tcu_lbist_scan_out_buf, 
  ftu_instr_0_c, 
  ftu_instr_1_c, 
  ftu_instr_2_c, 
  ftu_instr_3_c, 
  ftu_instr_exceptions_c, 
  ftu_instr_0_c_rep0, 
  ftu_instr_0_c_rep1, 
  ftu_instr_0_c_rep2, 
  ftu_instr_0_c_rep3, 
  ftu_instr_1_c_rep0, 
  ftu_instr_1_c_rep1, 
  ftu_instr_1_c_rep2, 
  ftu_instr_1_c_rep3, 
  ftu_instr_2_c_rep0, 
  ftu_instr_2_c_rep1, 
  ftu_instr_2_c_rep2, 
  ftu_instr_2_c_rep3, 
  ftu_instr_3_c_rep0, 
  ftu_instr_3_c_rep1, 
  ftu_instr_3_c_rep2, 
  ftu_instr_3_c_rep3, 
  ftu_instr_0_exceptions_c_rep0, 
  ftu_instr_0_exceptions_c_rep1, 
  ftu_instr_0_exceptions_c_rep2, 
  ftu_instr_0_exceptions_c_rep3, 
  ftu_instr_1_exceptions_c_rep0, 
  ftu_instr_1_exceptions_c_rep1, 
  ftu_instr_1_exceptions_c_rep2, 
  ftu_instr_1_exceptions_c_rep3, 
  ftu_instr_2_exceptions_c_rep0, 
  ftu_instr_2_exceptions_c_rep1, 
  ftu_instr_2_exceptions_c_rep2, 
  ftu_instr_2_exceptions_c_rep3, 
  ftu_instr_3_exceptions_c_rep0, 
  ftu_instr_3_exceptions_c_rep1, 
  ftu_instr_3_exceptions_c_rep2, 
  ftu_instr_3_exceptions_c_rep3, 
  pce_ov_tl, 
  spc_aclk_tl, 
  spc_bclk_tl, 
  spc_aclk_wmr_tl, 
  lb_scan_en_tl, 
  pce_ov_tr, 
  spc_aclk_tr, 
  spc_bclk_tr, 
  spc_aclk_wmr_tr, 
  lb_scan_en_tr, 
  pce_ov_bl, 
  spc_aclk_bl, 
  spc_bclk_bl, 
  spc_aclk_wmr_bl, 
  lb_scan_en_bl, 
  pce_ov_br, 
  spc_aclk_br, 
  spc_bclk_br, 
  spc_aclk_wmr_br, 
  lb_scan_en_br, 
  dec_spu_grant_d, 
  dec_spu_grant_d_rep0);
wire fgu_cecc_fx2_rep0;
wire fgu_uecc_fx2_rep0;


input	[47:0]	exu_address0_e;
input	[47:0]	exu_address1_e;

output	[47:0]	exu_address0_e_rep0;
output	[47:0]	exu_address1_e_rep0;
output	[47:0]	exu_address0_e_rep01;
output	[47:0]	exu_address1_e_rep01;

input	[63:0]	fgu_exu_result_fx5;
output	[63:0]	fgu_exu_result_fx5_rep0;
output	[63:0]	fgu_exu_result_fx5_rep1;

input	[63:0]	lsu_exu_ld_data_b;
output	[63:0]	lsu_exu_ld_data_b_rep00;
output	[63:0]	lsu_exu_ld_data_b_rep01;

input		fgu_cecc_fx2;
input		fgu_uecc_fx2;
output		fgu_cecc_fx2_rep1;
output		fgu_uecc_fx2_rep1;

// high-fanout nets that need buffering
input 	     pce_ov;  		// from cluster header
input        spc_aclk;		// from cluster header
input 	     spc_bclk;		// from cluster header
input 	     spc_aclk_wmr;	// from cluster header
input	     lb_scan_en;	// from spc_lb_ctl


// Next few are primary I/O's needing buffers and/or flops
input  [1:0] scan_in;       	
input 	     tcu_pce_ov;	
input 	     tcu_aclk;		
input 	     tcu_bclk;		
input 	     tcu_dectest;	
input 	     tcu_muxtest;	
input 	     tcu_scan_en;	
input        tcu_array_wr_inhibit;	
input        tcu_se_scancollar_in;	
input        tcu_se_scancollar_out;	
input        rst_wmr_protect;		

input		dmo_dcmuxctl;
input	[3:0]	hver_mask_minor_rev;

output [1:0] scan_out;	    	

// shadow scan signals
input		tcu_shscan_pce_ov;	
input		tcu_shscan_aclk;	
input		tcu_shscan_bclk;	
input		tcu_shscan_scan_in;	
input		tcu_shscan_scan_en;	
output		spc_shscan_scan_out;	

// From RST
input		cluster_arst_l;		

// MBIST signals
input           tcu_spc_mbist_scan_in;	
input           tcu_spc_mbist_start_ff;	// input flop + buffer
output		spc_mbist_fail;		// flop + output buffer
output          spc_mbist_done;		// flop + output buffer
output          spc_tcu_mbist_scan_out;	

// Logic BIST signals
input           tcu_spc_lbist_start;    // buffer
input           tcu_spc_lbist_scan_in;  
input           tcu_spc_lbist_pgm;      
input           tcu_spc_test_mode;      

output          spc_tcu_lbist_done;     // output buffer
output          spc_tcu_lbist_scan_out; 

// and the I/O from the internals of SPC for these signals

output [1:0] 	scan_in_buf;       	
output 	     	tcu_pce_ov_buf;	
output 	     	tcu_aclk_buf;		
output 	     	tcu_bclk_buf;		
output 	     	tcu_dectest_buf;	
output 	     	tcu_muxtest_buf;	
output 	     	tcu_scan_en_buf;	
output       	tcu_array_wr_inhibit_buf;	
output       	tcu_se_scancollar_in_buf;	
output       	tcu_se_scancollar_out_buf;	
output       	rst_wmr_protect_buf;		

output		dmo_dcmuxctl_buf;
output	[3:0]	hver_mask_minor_rev_buf;

input  [1:0]  	scan_out_buf;	    	

// shadow scan signals
output		tcu_shscan_pce_ov_buf;	
output		tcu_shscan_aclk_buf;	
output		tcu_shscan_bclk_buf;	
output		tcu_shscan_scan_in_buf;	
output		tcu_shscan_scan_en_buf;	
input		spc_shscan_scan_out_buf;	

// From RST
output		cluster_arst_l_buf;		

// MBIST signals
output           tcu_spc_mbist_scan_in_buf;	
output           tcu_spc_mbist_start_buf0;	
input 		 spc_mbist_fail_ff;		
input            spc_mbist_done_ff;		
input            spc_tcu_mbist_scan_out_buf;	

// Logic BIST signals
output           tcu_spc_lbist_start_buf;    
output           tcu_spc_lbist_scan_in_buf;  
output           tcu_spc_lbist_pgm_buf;      
output           tcu_spc_test_mode_buf;      

input 		 lb_lbist_done;
input            spc_tcu_lbist_scan_out_buf; 

/////////////////////////////////////////////////////////
// Added the following for ifu_ftu                     //
/////////////////////////////////////////////////////////
input [32:0] ftu_instr_0_c ;
input [32:0] ftu_instr_1_c ;
input [32:0] ftu_instr_2_c ;
input [32:0] ftu_instr_3_c ;

input  [4:0]  ftu_instr_exceptions_c;

output [32:0] ftu_instr_0_c_rep0 ;
output [32:0] ftu_instr_0_c_rep1 ;
output [32:0] ftu_instr_0_c_rep2 ;
output [32:0] ftu_instr_0_c_rep3 ;
output [32:0] ftu_instr_1_c_rep0 ;
output [32:0] ftu_instr_1_c_rep1 ;
output [32:0] ftu_instr_1_c_rep2 ;
output [32:0] ftu_instr_1_c_rep3 ;
output [32:0] ftu_instr_2_c_rep0 ;
output [32:0] ftu_instr_2_c_rep1 ;
output [32:0] ftu_instr_2_c_rep2 ;
output [32:0] ftu_instr_2_c_rep3 ;
output [32:0] ftu_instr_3_c_rep0 ;
output [32:0] ftu_instr_3_c_rep1 ;
output [32:0] ftu_instr_3_c_rep2 ;
output [32:0] ftu_instr_3_c_rep3 ;

output  [4:0]  ftu_instr_0_exceptions_c_rep0;
output  [4:0]  ftu_instr_0_exceptions_c_rep1;
output  [4:0]  ftu_instr_0_exceptions_c_rep2;
output  [4:0]  ftu_instr_0_exceptions_c_rep3;

output  [4:0]  ftu_instr_1_exceptions_c_rep0;
output  [4:0]  ftu_instr_1_exceptions_c_rep1;
output  [4:0]  ftu_instr_1_exceptions_c_rep2;
output  [4:0]  ftu_instr_1_exceptions_c_rep3;

output  [4:0]  ftu_instr_2_exceptions_c_rep0;
output  [4:0]  ftu_instr_2_exceptions_c_rep1;
output  [4:0]  ftu_instr_2_exceptions_c_rep2;
output  [4:0]  ftu_instr_2_exceptions_c_rep3;

output  [4:0]  ftu_instr_3_exceptions_c_rep0;
output  [4:0]  ftu_instr_3_exceptions_c_rep1;
output  [4:0]  ftu_instr_3_exceptions_c_rep2;
output  [4:0]  ftu_instr_3_exceptions_c_rep3;


output pce_ov_tl;
output spc_aclk_tl;
output spc_bclk_tl;
output spc_aclk_wmr_tl;
output lb_scan_en_tl;

output pce_ov_tr;
output spc_aclk_tr;
output spc_bclk_tr;
output spc_aclk_wmr_tr;
output lb_scan_en_tr;

output pce_ov_bl;
output spc_aclk_bl;
output spc_bclk_bl;
output spc_aclk_wmr_bl;
output lb_scan_en_bl;

output pce_ov_br;
output spc_aclk_br;
output spc_bclk_br;
output spc_aclk_wmr_br;
output lb_scan_en_br;


////////////// END ifu_ftu /////////////////////////////////////

// dec -> spu_mct_ctl
input		dec_spu_grant_d;
output		dec_spu_grant_d_rep0;

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__vertical_1__width_37 chip_io_rep0  (
  .din ({scan_in[1:0], tcu_pce_ov, tcu_aclk, tcu_bclk, tcu_dectest, tcu_muxtest, tcu_scan_en, tcu_array_wr_inhibit,
         tcu_se_scancollar_in, tcu_se_scancollar_out, rst_wmr_protect, scan_out_buf[1:0], tcu_shscan_pce_ov, 
         tcu_shscan_aclk, tcu_shscan_bclk, tcu_shscan_scan_in, tcu_shscan_scan_en, spc_shscan_scan_out_buf,
         cluster_arst_l, tcu_spc_mbist_scan_in, tcu_spc_mbist_start_ff, spc_mbist_fail_ff,
         spc_mbist_done_ff, spc_tcu_mbist_scan_out_buf, tcu_spc_lbist_start, tcu_spc_lbist_scan_in, tcu_spc_lbist_pgm, 
         tcu_spc_test_mode, lb_lbist_done, spc_tcu_lbist_scan_out_buf, dmo_dcmuxctl, hver_mask_minor_rev[3:0]}),

  .dout ({scan_in_buf[1:0], tcu_pce_ov_buf, tcu_aclk_buf, tcu_bclk_buf, tcu_dectest_buf, tcu_muxtest_buf, tcu_scan_en_buf, tcu_array_wr_inhibit_buf,
         tcu_se_scancollar_in_buf, tcu_se_scancollar_out_buf, rst_wmr_protect_buf, scan_out[1:0], tcu_shscan_pce_ov_buf, 
         tcu_shscan_aclk_buf, tcu_shscan_bclk_buf, tcu_shscan_scan_in_buf, tcu_shscan_scan_en_buf, spc_shscan_scan_out,
         cluster_arst_l_buf, tcu_spc_mbist_scan_in_buf, tcu_spc_mbist_start_buf0, spc_mbist_fail,
         spc_mbist_done, spc_tcu_mbist_scan_out, tcu_spc_lbist_start_buf, tcu_spc_lbist_scan_in_buf, tcu_spc_lbist_pgm_buf, 
         tcu_spc_test_mode_buf, spc_tcu_lbist_done, spc_tcu_lbist_scan_out, dmo_dcmuxctl_buf, hver_mask_minor_rev_buf[3:0]})
  );

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1 spu_grant_rep0  (
  .din (dec_spu_grant_d),
  .dout(dec_spu_grant_d_rep0)
  );


// end dec -> spu_mct_ctl

// high-fanout buffering
spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 hf_tl_rep0  (
  .din ({pce_ov,spc_aclk,spc_bclk,spc_aclk_wmr,lb_scan_en}),
  .dout({pce_ov_tl,spc_aclk_tl,spc_bclk_tl,spc_aclk_wmr_tl,lb_scan_en_tl})
  );

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 hf_tr_rep0  (
  .din ({pce_ov,spc_aclk,spc_bclk,spc_aclk_wmr,lb_scan_en}),
  .dout({pce_ov_tr,spc_aclk_tr,spc_bclk_tr,spc_aclk_wmr_tr,lb_scan_en_tr})
  );

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 hf_br_rep0  (
  .din ({pce_ov,spc_aclk,spc_bclk,spc_aclk_wmr,lb_scan_en}),
  .dout({pce_ov_br,spc_aclk_br,spc_bclk_br,spc_aclk_wmr_br,lb_scan_en_br})
  );

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 hf_bl_rep0  (
  .din ({pce_ov,spc_aclk,spc_bclk,spc_aclk_wmr,lb_scan_en}),
  .dout({pce_ov_bl,spc_aclk_bl,spc_bclk_bl,spc_aclk_wmr_bl,lb_scan_en_bl})
  );

///////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////
// Added the following for ifu_ftu                     //
// All exception buses are the same and interchangeable//
// The exception buses are connected to the closest    //
// buffer.                                             //
/////////////////////////////////////////////////////////
spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_0_rep0  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_0_c[32:0]  }  ),
  .dout({ftu_instr_0_exceptions_c_rep0[4:0] , ftu_instr_0_c_rep0[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_0_rep1  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_0_c[32:0]  }  ),
  .dout({ftu_instr_0_exceptions_c_rep1[4:0] , ftu_instr_0_c_rep1[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_0_rep2  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_0_c[32:0]  }  ),
  .dout({ftu_instr_0_exceptions_c_rep2[4:0] , ftu_instr_0_c_rep2[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_0_rep3  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_0_c[32:0]  }  ),
  .dout({ftu_instr_0_exceptions_c_rep3[4:0] , ftu_instr_0_c_rep3[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_1_rep0  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_1_c[32:0]  }  ),
  .dout({ftu_instr_1_exceptions_c_rep0[4:0] , ftu_instr_1_c_rep0[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_1_rep1  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_1_c[32:0]  }  ),
  .dout({ftu_instr_1_exceptions_c_rep1[4:0] , ftu_instr_1_c_rep1[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_1_rep2  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_1_c[32:0]  }  ),
  .dout({ftu_instr_1_exceptions_c_rep2[4:0] , ftu_instr_1_c_rep2[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_1_rep3  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_1_c[32:0]  }  ),
  .dout({ftu_instr_1_exceptions_c_rep3[4:0] , ftu_instr_1_c_rep3[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_2_rep0  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_2_c[32:0]  }  ),
  .dout({ftu_instr_2_exceptions_c_rep0[4:0] , ftu_instr_2_c_rep0[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_2_rep1  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_2_c[32:0]  }  ),
  .dout({ftu_instr_2_exceptions_c_rep1[4:0] , ftu_instr_2_c_rep1[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_2_rep2  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_2_c[32:0]  }  ),
  .dout({ftu_instr_2_exceptions_c_rep2[4:0] , ftu_instr_2_c_rep2[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_2_rep3  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_2_c[32:0]  }  ),
  .dout({ftu_instr_2_exceptions_c_rep3[4:0] , ftu_instr_2_c_rep3[32:0]})
  );

spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_3_rep0  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_3_c[32:0]  }  ),
  .dout({ftu_instr_3_exceptions_c_rep0[4:0] , ftu_instr_3_c_rep0[32:0]})
  );
spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_3_rep1  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_3_c[32:0]  }  ),
  .dout({ftu_instr_3_exceptions_c_rep1[4:0] , ftu_instr_3_c_rep1[32:0]})
  );
spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_3_rep2  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_3_c[32:0]  }  ),
  .dout({ftu_instr_3_exceptions_c_rep2[4:0] , ftu_instr_3_c_rep2[32:0]})
  );
spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 ftu_instr_3_rep3  (
  .din ({ftu_instr_exceptions_c[4:0], ftu_instr_3_c[32:0]  }  ),
  .dout({ftu_instr_3_exceptions_c_rep3[4:0] , ftu_instr_3_c_rep3[32:0]})
  );

////////////// END ifu_ftu /////////////////////////////////////

// exu_address; buffer off the less critical ifu/tlu load to
// improve timing on the path to lsu

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_64c__width_48 i_exu_address0_e_rep0  (
  .din (exu_address0_e[47:0]),
  .dout(exu_address0_e_rep0[47:0])
);
spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_50c__width_48 i_exu_address0_e_rep01  (
  .din (exu_address0_e_rep0[47:0]),
  .dout(exu_address0_e_rep01[47:0])
);
spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_64c__width_48 i_exu_address1_e_rep0  (
  .din (exu_address1_e[47:0]),
  .dout(exu_address1_e_rep0[47:0])
);
spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_50c__width_48 i_exu_address1_e_rep01  (
  .din (exu_address1_e_rep0[47:0]),
  .dout(exu_address1_e_rep01[47:0])
);

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__top_lsb__vertical_1__width_32 i_fgu_exu_result_fx5_rep0a  (
	.din	(fgu_exu_result_fx5[31:0]),
	.dout	(fgu_exu_result_fx5_rep0[31:0])
);
spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__top_lsb__vertical_1__width_32 i_fgu_exu_result_fx5_rep0b  (
	.din	(fgu_exu_result_fx5[63:32]),
	.dout	(fgu_exu_result_fx5_rep0[63:32])
);

spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_none__top_lsb__vertical_1__width_32 i_fgu_exu_result_fx5_rep1a  (
	.din	(fgu_exu_result_fx5_rep0[31:0]),
	.dout	(fgu_exu_result_fx5_rep1[31:0])
);
spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_none__top_lsb__vertical_1__width_32 i_fgu_exu_result_fx5_rep1b  (
	.din	(fgu_exu_result_fx5_rep0[63:32]),
	.dout	(fgu_exu_result_fx5_rep1[63:32])
);

// lsu_exu_ld_data_b
spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_72c__width_64 i_lsu_exu_ld_data_rep00  (
  .din (lsu_exu_ld_data_b[63:0]),
  .dout(lsu_exu_ld_data_b_rep00[63:0])
);
spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_72c__width_64 i_lsu_exu_ld_data_rep01  (
  .din (lsu_exu_ld_data_b[63:0]),
  .dout(lsu_exu_ld_data_b_rep01[63:0])
);

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_2 i_fgu_ecc_fx2_rep0  (
  .din ({fgu_cecc_fx2,      fgu_uecc_fx2     }),
  .dout({fgu_cecc_fx2_rep0, fgu_uecc_fx2_rep0})
);

spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__vertical_1__width_2 i_fgu_ecc_fx2_rep1  (
  .din ({fgu_cecc_fx2_rep0, fgu_uecc_fx2_rep0}),
  .dout({fgu_cecc_fx2_rep1, fgu_uecc_fx2_rep1})
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__vertical_1__width_37 (
  din, 
  dout);
  input [36:0] din;
  output [36:0] dout;


buff #(37)  d0_0 (
.in(din[36:0]),
.out(dout[36:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


buff #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_48x__rep_1__stack_38c__width_38 (
  din, 
  dout);
  input [37:0] din;
  output [37:0] dout;


buff #(38)  d0_0 (
.in(din[37:0]),
.out(dout[37:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_64c__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_50c__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__top_lsb__vertical_1__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_none__top_lsb__vertical_1__width_32 (
  din, 
  dout);
  input [31:0] din;
  output [31:0] dout;


buff #(32)  d0_0 (
.in(din[31:0]),
.out(dout[31:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_16x__rep_1__stack_72c__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


buff #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module spc_rep1_dpbuff_macro__dbuff_32x__rep_1__stack_none__vertical_1__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: spu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module spu (
  scan_in, 
  scan_out, 
  l2clk,
  in_rngl_cdbus, 

  spu_mbi_mam_fail_, 
  spu_mbi_mam_fail2_, 
  spu_mbi_arf_fail_, 
  spu_mbi_rrf_fail_, 
  spu_rngl_cdbus, 
  spu_l15_valid, 
  spu_l15_addr, 
  spu_l15_cpkt, 
  spu_l15_data, 
  spu_mult_request, 
  spu_fgu_rs1_e, 
  spu_fgu_rs2_e, 
  spu_fgu_fpy_ctl_d, 
  spu_pmu_cwq_busy, 
  spu_pmu_cwq_tid, 
  spu_pmu_ma_busy, 
  spu_tlu_cwq_busy, 
  spu_tlu_cwq_int_req, 
  spu_tlu_ma_int_req, 
  spu_tlu_mamu_err_req, 
  spu_tlu_l2_error);

input 		scan_in;
output		scan_out;
input		l2clk;

input  [64:0]	in_rngl_cdbus;			// ASI Ring
						//   64:0, 65 bit control/data bus coming from the ring
						//   64    - ctl/data            
						//   63    - valid/hole          
						//   62    - ack            
						//   61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR          
						//   59    - rd/wrx              
						//   58:56 - Thread ID           
						//   55:48 - ASI field           
						//   47:0  - Virtual Address    

output		spu_mbi_mam_fail_; 		// MBIST MAM comparator output bits 63:0
output		spu_mbi_mam_fail2_; 		// MBIST MAM comparator output bits 71:64
output		spu_mbi_arf_fail_;		// MBIST ARF comparator
output		spu_mbi_rrf_fail_;		// MBIST RRF comparator

output [64:0]	spu_rngl_cdbus;			// ASI Ring

output		spu_l15_valid;			// To L1.5 : Valid Control/Data
output [38:3]	spu_l15_addr;			// To L1.5 : Address
output [12:0]	spu_l15_cpkt;			// To L1.5 : Control portion of PCX packet
output [63:0]	spu_l15_data;			// To L1.5 : Store data

output		spu_mult_request;		// To FGU  : Multiply Request
output [63:0]	spu_fgu_rs1_e;			// To FGU  : Multiply RS1
output [63:0]	spu_fgu_rs2_e;			// To FGU  : Multiply RS2
output [6:0]	spu_fgu_fpy_ctl_d;		// To FGU  : SPU control bus for crypto multiply ops

output [4:0]	spu_pmu_cwq_busy;		// To PMU  : CWQ busy {rc4,hash,des,crc,aes}
output [2:0]	spu_pmu_cwq_tid;		// To PMU  : CWQ tid
output [3:0]	spu_pmu_ma_busy;		// To PMU  : Ma  busy

output		spu_tlu_cwq_busy;		// To TLU  : Prevents core from parking
output [3:0]	spu_tlu_cwq_int_req;		// To TLU  : [3] == valid; [2:0] == TID;
output [4:0]	spu_tlu_ma_int_req;		// To TLU  : Int req when MA op completes {4 -  error; 3 - req valid; 2:0 - TID}
output [10:0]	spu_tlu_mamu_err_req;		// was: 14 - valid; 13:11 - TID; 10 - ma port; 9:8 - syndrome; 7:0 - MA index
						// now: share 14..11 with tlu_ma_int_req; bits 10:0 stay the same
output [5:0]	spu_tlu_l2_error;		// To TLU  : L2 Error reporting : {MAL2C,MAL2U,MAL2ND,CWQL2C,CWQL2U,CWQL2ND}


//----- this module is blackboxed.

   assign 	scan_out = scan_in;        // SCAN
   
   assign 	spu_mbi_arf_fail_=1'b1;    // MBIST
   assign 	spu_mbi_mam_fail2_=1'b1;   // MBIST
   assign 	spu_mbi_mam_fail_=1'b1;    // MBIST
   assign 	spu_mbi_rrf_fail_=1'b1;    // MBIST
   
   reg [64:0] 	in_rngl_cdbus_d1;          // ASI ring
   reg [64:0] 	in_rngl_cdbus_d2;          // ASI ring

//nasim
`ifdef OPENSPARC_CMP
   reg l2clk_nba;
   always @(l2clk) l2clk_nba <= l2clk;
   always @(l2clk_nba)
`else
   always @(l2clk)
`endif
     begin
	in_rngl_cdbus_d1=in_rngl_cdbus;
	in_rngl_cdbus_d2=in_rngl_cdbus_d1;
     end	

   assign spu_rngl_cdbus=in_rngl_cdbus_d2; // ASI ring

   assign spu_mult_request=1'b0;	// To FGU  : Multiply Request
   assign spu_fgu_rs1_e=64'b0;	 	// To FGU  : Multiply RS1
   assign spu_fgu_rs2_e=64'b0;	 	// To FGU  : Multiply RS2
   assign spu_fgu_fpy_ctl_d=7'b0;	// To FGU  : SPU control bus for crypto multiply ops

   assign spu_l15_valid=1'b0;		// To L1.5 : Valid Control/Data
   assign spu_l15_addr[38:3] =36'b0;		// To L1.5 : Address
   assign spu_l15_data=64'b0;		// To L1.5 : Store data
   assign spu_l15_cpkt=13'b0;		// To L1.5 : Control portion of PCX packet
   
   assign spu_pmu_cwq_tid=3'b0;		// To PMU  : CWQ tid
   assign spu_pmu_ma_busy=4'b0;		// To PMU  : Ma  busy
   assign spu_pmu_cwq_busy=5'b0;	// To PMU  : CWQ busy {rc4,hash,des,crc,aes}

   assign spu_tlu_cwq_busy=1'b0;	// To TLU  : Prevents core from parking
   assign spu_tlu_mamu_err_req=11'b0;	// was: 14 - valid; 13:11 - TID; 10 - ma port; 9:8 - syndrome; 7:0 - MA index
   assign spu_tlu_cwq_int_req=4'b0;	// To TLU  : [3] == valid; [2:0] == TID;
   assign spu_tlu_ma_int_req=5'b0;	// To TLU  : Int req when MA op completes {4 -  error; 3 - req valid; 2:0 - TID}
   assign spu_tlu_l2_error=6'b0;	// To TLU  : L2 Error reporting : {MAL2C,MAL2U,MAL2ND,CWQL2C,CWQL2U,CWQL2ND}
   
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  hver_mask_minor_rev, 
  spc_aclk_wmr, 
  lb_scan_en_wmr, 
  wmr_scan_in, 
  tcu_wmr_vec_mask, 
  cmp_tick_enable, 
  lsu_asi_clken, 
  lsu_tlu_pmen, 
  mbi_tsa0_write_en, 
  mbi_tsa1_write_en, 
  mbi_tca_write_en, 
  mbi_addr, 
  mbi_run, 
  mbi_wdata, 
  mbi_tsa0_read_en, 
  mbi_tsa1_read_en, 
  mbi_tca_read_en, 
  mbi_tlu_cmpsel, 
  tcu_shscan_pce_ov, 
  tcu_shscan_clk_stop, 
  tcu_shscan_aclk, 
  tcu_shscan_bclk, 
  tcu_shscan_scan_in, 
  tcu_shscan_scan_en, 
  tcu_shscanid, 
  tcu_core_running, 
  tcu_ss_mode, 
  tcu_do_mode, 
  tcu_ss_request, 
  ftu_ifu_quiesce, 
  pku_quiesce, 
  ftu_excp_way_d, 
  ftu_excp_tid_d, 
  ftu_excp_way_valid_d, 
  dec_inst0_cnt, 
  dec_inst1_cnt, 
  dec_raw_pick_p, 
  dec_tid0_m, 
  dec_tid1_m, 
  dec_inst_valid_m, 
  dec_lsu_inst_m, 
  dec_fgu_inst_m, 
  dec_illegal_inst_m, 
  dec_exc0_m, 
  dec_exc1_m, 
  dec_done_inst_m, 
  dec_retry_inst_m, 
  dec_sir_inst_m, 
  dec_hpriv_exc_m, 
  dec_priv_exc_m, 
  dec_fpdisable_exc_m, 
  dec_br_taken_m, 
  dec_annul_ds_m, 
  dec_ds_m, 
  dec_icache_perr_m, 
  dec_cti_inst_m, 
  dec_flush_b, 
  exu_ibp_m, 
  exu_tcc_m, 
  exu_tof_m, 
  exu_cecc_m, 
  exu_uecc_m, 
  exu0_ecc_addr_m, 
  exu1_ecc_addr_m, 
  exu0_ecc_check_m, 
  exu1_ecc_check_m, 
  exu_oor_va_m, 
  exu_misalign_m, 
  exu_spill_b, 
  exu_fill_m, 
  exu_normal_b, 
  exu_cleanwin_b, 
  exu0_wstate_b, 
  exu1_wstate_b, 
  exu0_ccr0, 
  exu0_ccr1, 
  exu0_ccr2, 
  exu0_ccr3, 
  exu1_ccr0, 
  exu1_ccr1, 
  exu1_ccr2, 
  exu1_ccr3, 
  exu0_cwp0, 
  exu0_cwp1, 
  exu0_cwp2, 
  exu0_cwp3, 
  exu1_cwp0, 
  exu1_cwp1, 
  exu1_cwp2, 
  exu1_cwp3, 
  exu0_trap_number_b, 
  exu1_trap_number_b, 
  exu_tlu_window_block, 
  exu_address0_e, 
  exu_address1_e, 
  lsu_lddf_align_b, 
  lsu_stdf_align_b, 
  lsu_illegal_inst_b, 
  lsu_daccess_prot_b, 
  lsu_priv_action_b, 
  lsu_va_watchpoint_b, 
  lsu_pa_watchpoint_b, 
  lsu_align_b, 
  lsu_tlb_miss_b_, 
  lsu_dae_invalid_asi_b, 
  lsu_dae_nc_page_b, 
  lsu_dae_nfo_page_b, 
  lsu_dae_priv_viol_b, 
  lsu_dae_so_page, 
  lsu_priv_action_g, 
  lsu_tid_g, 
  lsu_trap_flush, 
  lsu_tlb_bypass_b, 
  lsu_tlb_real_b, 
  lsu_sync_inst_b, 
  lsu_stb_empty, 
  lsu_tlu_twocycle_m, 
  lsu_block_store_b, 
  lsu_dcmh_err_g, 
  lsu_dcvp_err_g, 
  lsu_dctp_err_g, 
  lsu_dcdp_err_g, 
  lsu_dcl2c_err_g, 
  lsu_dcl2u_err_g, 
  lsu_dcl2nd_err_g, 
  lsu_dcsoc_err_g, 
  lsu_dcerr_tid_g, 
  lsu_dcerr_sfar_g, 
  lsu_sbdlc_err_g, 
  lsu_sbdlu_err_g, 
  lsu_sbdpc_err_g, 
  lsu_sbdpu_err_g, 
  lsu_sbapp_err_g, 
  lsu_sbdiou_err_g, 
  lsu_stberr_tid_g, 
  lsu_stberr_index_g, 
  lsu_stberr_priv_g, 
  lsu_stb_flush_g, 
  lsu_dttp_err_b, 
  lsu_dtdp_err_b, 
  lsu_dtmh_err_b, 
  lsu_perfmon_trap_b, 
  lsu_perfmon_trap_g, 
  lsu_va_b, 
  lsu_ext_interrupt, 
  lsu_ext_int_type, 
  lsu_ext_int_vec, 
  lsu_ext_int_tid, 
  l15_spc_data1, 
  l15_spc_cpkt, 
  l15_spc_valid, 
  lsu_asi_error_inject, 
  lsu_rngf_cdbus, 
  fgu_pdist_beat2_fx1, 
  fgu_predict_fx2, 
  fgu_cecc_fx2, 
  fgu_uecc_fx2, 
  fgu_ecc_addr_fx2, 
  fgu_ecc_check_fx2, 
  fgu_fpx_ieee_trap_fw, 
  fgu_fpd_ieee_trap_fw, 
  fgu_fpx_unfin_fw, 
  fgu_fpx_trap_tid_fw, 
  fgu_fpd_unfin_fw, 
  fgu_fpd_idiv0_trap_fw, 
  fgu_fpd_trap_tid_fw, 
  mmu_hw_tw_enable, 
  mmu_write_itlb, 
  mmu_reload_done, 
  mmu_i_unauth_access, 
  mmu_i_tsb_miss, 
  mmu_d_tsb_miss, 
  mmu_i_tte_outofrange, 
  mmu_d_tte_outofrange, 
  mmu_itte_tag_data, 
  mmu_asi_data, 
  mmu_asi_read, 
  mmu_dae_req, 
  mmu_dae_tid, 
  mmu_asi_cecc, 
  mmu_asi_uecc, 
  mmu_asi_tid, 
  mmu_asi_index, 
  mmu_asi_mra_not_sca, 
  mmu_i_l2cerr, 
  mmu_d_l2cerr, 
  mmu_i_eccerr, 
  mmu_d_eccerr, 
  mmu_thr0_err_type, 
  mmu_thr1_err_type, 
  mmu_thr2_err_type, 
  mmu_thr3_err_type, 
  mmu_thr4_err_type, 
  mmu_thr5_err_type, 
  mmu_thr6_err_type, 
  mmu_thr7_err_type, 
  mmu_thr0_err_index, 
  mmu_thr1_err_index, 
  mmu_thr2_err_index, 
  mmu_thr3_err_index, 
  mmu_thr4_err_index, 
  mmu_thr5_err_index, 
  mmu_thr6_err_index, 
  mmu_thr7_err_index, 
  spu_pmu_ma_busy, 
  spu_tlu_cwq_busy, 
  spu_tlu_mamu_err_req, 
  spu_tlu_ma_int_req, 
  spu_tlu_cwq_int_req, 
  spu_tlu_l2_error, 
  pmu_tlu_trap_m, 
  pmu_tlu_debug_event, 
  scan_out, 
  wmr_scan_out, 
  spc_shscan_scan_out, 
  tlu_core_running_status, 
  tlu_ss_complete, 
  tlu_hardstop_request, 
  tlu_softstop_request, 
  tlu_trigger_pulse, 
  tlu_dbg_instr_cmt_grp0, 
  tlu_dbg_instr_cmt_grp1, 
  tlu_flush_ifu, 
  tlu_window_block, 
  tlu_retry_state, 
  tlu_halted, 
  tlu_pc_0_d, 
  tlu_pc_1_d, 
  tlu_flush_exu_b, 
  tlu_ccr_0, 
  tlu_ccr_1, 
  tlu_cwp_0, 
  tlu_cwp_1, 
  tlu_ccr_cwp_0_valid, 
  tlu_ccr_cwp_1_valid, 
  tlu_ccr_cwp_0_tid, 
  tlu_ccr_cwp_1_tid, 
  tlu_gl0, 
  tlu_gl1, 
  tlu_gl2, 
  tlu_gl3, 
  tlu_gl4, 
  tlu_gl5, 
  tlu_gl6, 
  tlu_gl7, 
  tlu_itlb_bypass_e, 
  tlu_flush_lsu_b, 
  tlu_flush_fgu_b, 
  tlu_trap_pc_0, 
  tlu_trap_pc_0_valid, 
  tlu_trap_0_tid, 
  tlu_trap_pc_1, 
  tlu_trap_pc_1_valid, 
  tlu_trap_1_tid, 
  tlu_retry, 
  tlu_ifu_invalidate, 
  tlu_itlb_reload, 
  tlu_itlb_bypass, 
  tlu_release_tte, 
  tlu_rngf_cdbus, 
  tlu_rngf_cdbus_error, 
  tlu_asi_0, 
  tlu_asi_1, 
  tlu_asi_0_valid, 
  tlu_asi_1_valid, 
  tlu_asi_0_tid, 
  tlu_asi_1_tid, 
  tlu_tl_gt_0, 
  tlu_lsu_clear_ctl_reg_, 
  tlu_load_i_tag_access_p, 
  tlu_load_i_tag_access_n, 
  tlu_load_d_tag_access, 
  tlu_load_d_tag_access_r, 
  tlu_npc_w, 
  tlu_pc_0_w, 
  tlu_pc_1_w, 
  tlu_iht_request, 
  tlu_dht_request, 
  tlu_mmu_tl_gt_0, 
  tlu_flush_pmu_b, 
  tlu_flush_pmu_w, 
  tlu_pmu_trap_taken, 
  tlu_pmu_trap_mask_e, 
  tlu_lsu_hpstate_hpriv, 
  tlu_lsu_pstate_priv, 
  tlu_ifu_hpstate_hpriv, 
  tlu_ifu_pstate_priv, 
  tlu_pmu_hpstate_hpriv, 
  tlu_pmu_pstate_priv, 
  tlu_dec_hpstate_hpriv, 
  tlu_dec_pstate_priv, 
  tlu_dec_pstate_pef, 
  tlu_pstate_cle, 
  tlu_pstate_am, 
  tlu_cerer_ittp, 
  tlu_cerer_itdp, 
  tlu_cerer_ittm, 
  tlu_cerer_hwtwmu, 
  tlu_cerer_hwtwl2, 
  tlu_cerer_icl2c, 
  tlu_cerer_icl2u, 
  tlu_cerer_icl2nd, 
  tlu_cerer_irf, 
  tlu_cerer_frf, 
  tlu_cerer_dttp, 
  tlu_cerer_dttm, 
  tlu_cerer_dtdp, 
  tlu_cerer_dcl2c, 
  tlu_cerer_dcl2u, 
  tlu_cerer_dcl2nd, 
  tlu_cerer_sbdlc, 
  tlu_cerer_sbdlu, 
  tlu_cerer_mrau, 
  tlu_cerer_scac, 
  tlu_cerer_scau, 
  tlu_cerer_sbapp, 
  tlu_cerer_l2c_socc, 
  tlu_cerer_l2u_socu, 
  tlu_cerer_icvp, 
  tlu_cerer_ictp, 
  tlu_cerer_ictm, 
  tlu_cerer_icdp, 
  tlu_cerer_dcvp, 
  tlu_cerer_dctp, 
  tlu_cerer_dctm, 
  tlu_cerer_dcdp, 
  tlu_cerer_sbdpc, 
  tlu_cerer_sbdpu, 
  tlu_cerer_mamu, 
  tlu_cerer_mal2c, 
  tlu_cerer_mal2u, 
  tlu_cerer_mal2nd, 
  tlu_cerer_cwql2c, 
  tlu_cerer_cwql2u, 
  tlu_cerer_cwql2nd, 
  tlu_cerer_sbdiou, 
  tlu_ceter_pscce, 
  tlu_tag_access_tid_0_b, 
  tlu_i_tag_access_0_b, 
  tlu_d_tag_access_0_b, 
  tlu_tag_access_tid_1_b, 
  tlu_i_tag_access_1_b, 
  tlu_d_tag_access_1_b, 
  tlu_mbi_tsa0_fail, 
  tlu_mbi_tsa1_fail, 
  tlu_mbi_tca_fail, 
  tlu_spec_enable);
wire [30:8] error_inject_unused;
wire rd_pce;
wire wr_pce;
wire bist_clk_mux_sel;
wire tcu_scan_en_wmr;
wire fls0_wmr_scanin;
wire fls0_wmr_scanout;
wire fls0_scanin;
wire fls0_scanout;
wire trl0_shscanid_2;
wire [1:0] trl0_shscanid;
wire [7:0] cxi_xir;
wire [7:0] cxi_ivt;
wire [7:0] asi_spec_enable;
wire [7:0] asi_immu_enable;
wire [7:0] asi_irl_cleared;
wire [7:0] asi_halt;
wire [7:0] asi_clear_spu_trap_req;
wire [7:0] tel_tsacu_exc;
wire [1:0] pct0_iaw_exc_e;
wire [3:2] pct_npc_0_w;
wire [3:2] pct_npc_1_w;
wire [3:2] pct_npc_2_w;
wire [3:2] pct_npc_3_w;
wire [1:0] pct_pc_oor_va_e;
wire [7:0] trl_tl_eq_0;
wire [7:0] trl_pil_mask_15;
wire [7:0] trl_iln_exc;
wire [7:0] trl_hstick_match;
wire [7:0] trl_unhalt_;
wire [7:0] trl_tlz_exc;
wire [7:0] trl_nns_exc;
wire [7:0] trl_ssc_exc;
wire [7:0] trl_invalidate_pc;
wire [7:0] trl_invalidate_npc;
wire [7:0] trl_pc_sel_trap_pc;
wire [7:0] trl_fls_npc_en;
wire [7:0] trl_trap_taken;
wire trl0_take_sma;
wire trl0_take_cwq;
wire trl0_take_xir;
wire trl0_take_ftt;
wire [7:0] trl_core_running_status;
wire [4:0] trl0_tsa_wr_addr;
wire [7:0] tlu_ceter_de;
wire [7:0] tlu_ceter_dhcce;
wire [7:0] tsd_hpstate_ibe;
wire [7:0] tsd_hpstate_hpriv;
wire [7:0] tsd_hpstate_red;
wire [7:0] tsd_pstate_tct;
wire [7:0] tsd_pstate_priv;
wire [7:0] tsd_pstate_ie;
wire [7:0] tsd_pstate_am;
wire [7:0] tsd_itlb_bypass;
wire tsd0_mrqr_exc_;
wire tsd0_dqr_exc_;
wire [7:0] asi_check_qr_exc;
wire [7:0] dfd_fls_desr_f;
wire [7:0] dfd_fls_desr_s;
wire [7:0] ras_precise_error;
wire [7:0] ras_disrupting_error;
wire [7:0] ras_deferred_error;
wire fls0_spc_hardstop_request;
wire fls0_spc_softstop_request;
wire fls0_spc_trigger_pulse;
wire tlu_flush_lsu_b_unused;
wire tlu_flush_fgu_b_unused;
wire fls0_flush_lsu_b;
wire fls0_flush_fgu_b;
wire [1:0] fls0_tid_d;
wire [3:0] fls0_tid_dec_b;
wire [3:0] fls0_tid_dec_w;
wire [7:0] fls_pc_sel_npc;
wire [7:0] fls_pc_sel_npc_plus_4;
wire [7:0] fls_npc_sel_npc_plus_4;
wire [7:0] fls_npc_sel_npc_plus_8;
wire [7:0] fls_npc_sel_target;
wire fls0_npc_b_sel_npc;
wire fls0_pc_is_npc;
wire [1:0] fls_pstate_am_d_;
wire [1:0] fls_pstate_am_b_;
wire [1:0] fls_pstate_am_w_;
wire fls0_lsu_inst_w_unused;
wire fls0_dfd_lsu_inst_b;
wire [2:0] fls_wstate0;
wire [2:0] fls_wstate1;
wire [2:0] fls_wstate2;
wire [2:0] fls_wstate3;
wire [7:0] fls_tcc_number_0;
wire [7:0] fls_tcc_number_1;
wire [7:0] fls_tcc_number_2;
wire [7:0] fls_tcc_number_3;
wire [7:0] fls_tid_dec_w_in;
wire [7:0] fls_por_request;
wire [7:0] fls_xir_request;
wire [7:0] fls_ivt_request;
wire [7:0] fls_sir_request;
wire [7:0] fls_itm_request;
wire [7:0] fls_iln_request;
wire [7:0] fls_hst_request;
wire [7:0] fls_tlz_request;
wire [7:0] fls_sma_request;
wire [7:0] fls_cwq_request;
wire [7:0] fls_ade_request;
wire [7:0] fls_iae_request;
wire [7:0] fls_ipe_request;
wire [1:0] fls_ipv_request;
wire [1:0] fls_inp_request;
wire [1:0] fls_iar_request;
wire [1:0] fls_irr_request;
wire [1:0] fls_mar_request;
wire [1:0] fls_mrr_request;
wire [1:0] fls_pro_request;
wire [1:0] fls_ill_request;
wire [1:0] fls_don_request;
wire [1:0] fls_ret_request;
wire [1:0] fls_fpd_request;
wire [1:0] fls_snn_request;
wire [1:0] fls_sno_request;
wire [1:0] fls_fnn_request;
wire [1:0] fls_fno_request;
wire [1:0] fls_clw_request;
wire [7:0] fls_dtm_request;
wire [1:0] fls_ldf_request;
wire [1:0] fls_stf_request;
wire [1:0] fls_dap_request;
wire [1:0] fls_vaw_request;
wire [1:0] fls_iaw_request;
wire [1:0] fls_paw_request;
wire [1:0] fls_maa_request;
wire [1:0] fls_fpe_request;
wire [7:0] fls_fei_request;
wire [7:0] fls_fof_request;
wire [7:0] fls_pra_request;
wire [1:0] fls_dia_request;
wire [7:0] fls_ups_request;
wire [1:0] fls_dpv_request;
wire [1:0] fls_dnc_request;
wire [1:0] fls_dnf_request;
wire [1:0] fls_dso_request;
wire [1:0] fls_tof_request;
wire [7:0] fls_dbz_request;
wire [1:0] fls_tcc_request;
wire [7:0] fls_dae_request;
wire [7:0] fls_lsr_request;
wire [1:0] fls_irt_request;
wire [1:0] fls_drt_request;
wire [7:0] fls_pmu_request;
wire [7:0] fls_mqr_request;
wire [7:0] fls_dqr_request;
wire [7:0] fls_rqr_request;
wire [7:0] fls_idl_request;
wire [7:0] fls_res_request;
wire [7:0] fls_ssr_request;
wire [7:0] fls_ssc_request;
wire [7:0] fls_nns_request;
wire [7:0] fls_ime_request;
wire [7:0] fls_dme_request;
wire [7:0] fls_eer_request;
wire [1:0] fls_icp_request;
wire [7:0] fls_ftt_request;
wire [1:0] fls_ibp_request;
wire [1:0] fls_tct_request;
wire [1:0] fls_ref_request;
wire [1:0] fls_ipe_dme_request;
wire [7:0] fls_pc_valid;
wire [7:0] fls_load_dsfar;
wire [1:0] fls_irf_cecc_b;
wire [1:0] fls_irf_uecc_b;
wire [1:0] fls_kill_irf_ecc_w;
wire [2:0] fls0_cwp0;
wire [2:0] fls0_cwp1;
wire [2:0] fls0_cwp2;
wire [2:0] fls0_cwp3;
wire [7:0] fls_core_running;
wire fls_ss_request;
wire [7:0] fls_pct_pc_en;
wire [7:0] fls_pct_npc_en;
wire [7:0] fls_trl_l1en;
wire [4:2] fls0_npc_if_cnt_eq_1_d;
wire [4:2] fls0_npc_if_cnt_eq_2_d;
wire [4:2] fls0_npc_if_cnt_eq_3_d;
wire [7:0] fls_flush;
wire [1:0] fls_disrupting_flush_w;
wire fls_f_cecc_w;
wire fls_f_uecc_w;
wire [1:0] fls_ss_update_pc_w;
wire fls1_wmr_scanin;
wire fls1_wmr_scanout;
wire fls1_scanin;
wire fls1_scanout;
wire trl1_shscanid_2;
wire [1:0] trl1_shscanid;
wire [1:0] pct1_iaw_exc_e;
wire [3:2] pct_npc_4_w;
wire [3:2] pct_npc_5_w;
wire [3:2] pct_npc_6_w;
wire [3:2] pct_npc_7_w;
wire trl1_take_sma;
wire trl1_take_cwq;
wire trl1_take_xir;
wire trl1_take_ftt;
wire [4:0] trl1_tsa_wr_addr;
wire tsd1_mrqr_exc_;
wire tsd1_dqr_exc_;
wire fls1_spc_hardstop_request;
wire fls1_spc_softstop_request;
wire fls1_spc_trigger_pulse;
wire fls1_flush_lsu_b_unused;
wire fls1_flush_fgu_b_unused;
wire [1:0] fls1_tid_d;
wire [3:0] fls1_tid_dec_b;
wire [3:0] fls1_tid_dec_w;
wire fls1_npc_b_sel_npc;
wire fls1_pc_is_npc;
wire fls1_lsu_inst_w;
wire fls1_dfd_lsu_inst_b;
wire [2:0] fls_wstate4;
wire [2:0] fls_wstate5;
wire [2:0] fls_wstate6;
wire [2:0] fls_wstate7;
wire [7:0] fls_tcc_number_4;
wire [7:0] fls_tcc_number_5;
wire [7:0] fls_tcc_number_6;
wire [7:0] fls_tcc_number_7;
wire [2:0] fls1_cwp0;
wire [2:0] fls1_cwp1;
wire [2:0] fls1_cwp2;
wire [2:0] fls1_cwp3;
wire fls_ss_request_unused;
wire [4:2] fls1_npc_if_cnt_eq_1_d;
wire [4:2] fls1_npc_if_cnt_eq_2_d;
wire [4:2] fls1_npc_if_cnt_eq_3_d;
wire fls_f_cecc_w_unused;
wire fls_f_uecc_w_unused;
wire pct0_wmr_scanin;
wire pct0_wmr_scanout;
wire pct0_scanin;
wire pct0_scanout;
wire [47:2] tic_exu_address0_m;
wire [7:0] asi_rd_pc;
wire [1:0] asi_wr_iaw;
wire [63:0] asi_wr_data_0;
wire [7:0] trl_npc_sel_trap_npc;
wire [7:0] trl_npc_sel_tnpc;
wire [8:0] trl0_trap_type;
wire [3:0] trl0_pc_thread_sel;
wire [1:0] trl_pc_pstate_am_;
wire [1:0] trl_pc_sel_pc;
wire [1:0] trl_pc_sel_npc;
wire [1:0] trl_pc_sel_trap;
wire [1:0] trl_pc_sel_reset;
wire [1:0] trl_pc_done;
wire [1:0] trl_pc_retry;
wire [1:0] trl_pc_tte;
wire [1:0] trl_pct_trap_pc_en;
wire [1:0] trl_pct_tnpc_en;
wire [47:14] tsd0_tba;
wire [47:2] tsd0_tpc;
wire [1:0] tsd_tpc_oor_va;
wire [47:2] tsd0_tnpc;
wire [1:0] tsd_tnpc_oor_va;
wire [1:0] tsd_tnpc_nonseq;
wire [47:2] tsd0_asi_data_;
wire [48:2] pct0_asi_data;
wire [47:2] pct0_tsa_pc;
wire [1:0] pct_tsa_pc_oor_va;
wire [47:2] pct0_tsa_npc;
wire [1:0] pct_tsa_npc_oor_va;
wire [1:0] pct_tsa_npc_nonseq;
wire [7:0] pct_npc_is_nonseq;
wire [47:2] pct0_shadow_pc_d;
wire [47:2] pct0_npc_w;
wire [47:2] pct0_target_b;
wire [16:0] pct0_trl_wr_data;
wire [10:5] tsd_pc_0_w;
wire [47:2] tlu_pc_0_prebuf_d;
wire pct1_wmr_scanin;
wire pct1_wmr_scanout;
wire pct1_scanin;
wire pct1_scanout;
wire [47:2] tic_exu_address1_m;
wire [62:0] asi_wr_data_1;
wire [8:0] trl1_trap_type;
wire [3:0] trl1_pc_thread_sel;
wire [47:14] tsd1_tba;
wire [47:2] tsd1_tpc;
wire [47:2] tsd1_tnpc;
wire [47:2] tsd1_asi_data_;
wire [48:2] pct1_asi_data;
wire [47:2] pct1_tsa_pc;
wire [47:2] pct1_tsa_npc;
wire [47:2] pct1_shadow_pc_d;
wire [47:2] pct1_npc_w;
wire [47:2] pct1_target_b;
wire [16:0] pct1_trl_wr_data;
wire [10:5] tsd_pc_1_w;
wire cxi_scanin;
wire cxi_scanout;
wire [13:1] l15_spc_cpkt_unused;
wire [13:6] l15_spc_data1_unused;
wire cth_wmr_scanin;
wire cth_wmr_scanout;
wire cth_scanin;
wire cth_scanout;
wire trl0_wmr_scanin;
wire trl0_wmr_scanout;
wire trl0_scanin;
wire trl0_scanout;
wire trl1_itw_last;
wire [1:0] tsa0_gl;
wire [1:0] tsa_tnpc_nonseq;
wire [7:0] tsd_hpstate_tlz;
wire [1:0] tsd_htstate_hpriv;
wire [7:0] asi_rd_tl;
wire [7:0] asi_wr_tl;
wire [7:0] asi_rd_pil;
wire [7:0] asi_wr_pil;
wire [7:0] asi_rd_gl;
wire [7:0] asi_wr_gl;
wire [7:0] asi_wr_set_softint;
wire [7:0] asi_wr_clear_softint;
wire [7:0] asi_rd_softint;
wire [7:0] asi_wr_softint;
wire [7:0] asi_rd_hintp;
wire [7:0] asi_wr_hintp;
wire [1:0] asi_preempt_trap;
wire [1:0] asi_preempt_done_retry;
wire [1:0] asi_rmw_tsa;
wire [7:0] asi_wr_asireg;
wire [1:0] asi_trl_pstate_en;
wire [1:0] asi_mbist_tsa_rd_en;
wire [1:0] asi_mbist_tsa_wr_en;
wire [8:0] trl0_tsa_trap_type;
wire [4:0] trl0_asireg_sel;
wire trl0_asireg_en;
wire [3:0] trl0_thread_sel;
wire [2:0] trl0_tba_sel;
wire [4:0] trl0_pstate_thread_sel;
wire [3:0] trl0_don_ret_pstate_sel;
wire trl0_pstate_en;
wire [1:0] trl_reset_trap;
wire [1:0] trl_other_trap;
wire [1:0] trl_stay_in_priv;
wire [1:0] trl_tsa_wr_en_pre;
wire [1:0] trl_tsa_rd_en;
wire [4:0] trl0_tsa_rd_addr;
wire trl0_save_tsa;
wire trl0_tsd_tsa_en;
wire trl0_tsd_tsa_wd_en;
wire trl0_capture_ss;
wire trl0_rmw_tsa;
wire [1:0] trl_tl_gt_0;
wire [1:0] trl0_tsa_gl;
wire [16:0] trl0_asi_data;
wire [7:0] trl_ss_complete;
wire trl0_itw_wait;
wire trl0_itw_last;
wire [2:0] trl0_shadow_tl;
wire [2:0] trl0_tl_for_tt;
wire [1:0] trl_tel_en;
wire [1:0] trl_gl0;
wire [1:0] trl_gl1;
wire [1:0] trl_gl2;
wire [1:0] trl_gl3;
wire [7:0] trl_tsacu_en_in;
wire [2:0] tlu_tsa_index_0;
wire [7:0] tlu_tccd;
wire [7:0] tlu_tcud;
wire [1:0] tlu_tca_index_0;
wire trl1_wmr_scanin;
wire trl1_wmr_scanout;
wire trl1_scanin;
wire trl1_scanout;
wire [1:0] tsa1_gl;
wire [8:0] trl1_tsa_trap_type;
wire [4:0] trl1_asireg_sel;
wire trl1_asireg_en;
wire [3:0] trl1_thread_sel;
wire [2:0] trl1_tba_sel;
wire [4:0] trl1_pstate_thread_sel;
wire [3:0] trl1_don_ret_pstate_sel;
wire trl1_pstate_en;
wire [4:0] trl1_tsa_rd_addr;
wire trl1_save_tsa;
wire trl1_tsd_tsa_en;
wire trl1_tsd_tsa_wd_en;
wire trl1_capture_ss;
wire trl1_rmw_tsa;
wire [1:0] trl1_tsa_gl;
wire [16:0] trl1_asi_data;
wire trl1_itw_wait_unused;
wire [2:0] trl1_shadow_tl;
wire [2:0] trl1_tl_for_tt;
wire [1:0] trl_gl4;
wire [1:0] trl_gl5;
wire [1:0] trl_gl6;
wire [1:0] trl_gl7;
wire [2:0] tlu_tsa_index_1;
wire [1:0] tlu_tca_index_1;
wire [135:0] teg0_data_in;
wire [1:0] tsd_wr_tpc_oor_va;
wire [1:0] tsd_wr_tnpc_oor_va;
wire [1:0] tsd_wr_tnpc_nonseq;
wire [1:0] tsd0_wr_gl;
wire [29:0] tsd0_wr_data;
wire [8:0] tsd0_wr_trap_type;
wire [47:2] tsd0_wr_tpc;
wire [47:2] tsd0_wr_tnpc;
wire [15:0] teg0_ecc;
wire asi_error_tsau;
wire [7:0] asi_mbist_tsa_ecc_in;
wire [15:0] tem0_ecc;
wire tel0_scanin;
wire tel0_scanout;
wire [1:0] asi_mbist_tel_en;
wire [15:0] tsa0_ecc;
wire [15:0] ted0_syndrome;
wire ted00_cecc_err;
wire ted00_uecc_err;
wire ted00_uecc_err_;
wire ted01_cecc_err;
wire ted01_uecc_err;
wire ted01_uecc_err_;
wire [15:0] tel0_syndrome;
wire [15:0] tel0_ecc;
wire [15:0] tel0_crit_ecc;
wire tel0_tsac;
wire tel0_tsau;
wire [7:0] tlu_tsac;
wire [7:0] tlu_tsau;
wire [135:0] tsd0_ted_mra_rd_data;
wire tlu_cerer_tsac;
wire tlu_cerer_tsau;
wire [1:0] asi_tsacu;
wire [135:0] tsb0_data_out;
wire [1:0] trl_tsa_wr_en;
wire tsa0_scanin;
wire tsa0_scanout;
wire [1:0] tsa_tpc_oor_va;
wire [1:0] tsa_tnpc_oor_va;
wire [29:0] tsa0_rd_data;
wire [8:0] tsa0_trap_type;
wire [47:2] tsa0_tpc;
wire [47:2] tsa0_tnpc;
wire [135:0] teg1_data_in;
wire [1:0] tsd1_wr_gl;
wire [29:0] tsd1_wr_data;
wire [8:0] tsd1_wr_trap_type;
wire [47:2] tsd1_wr_tpc;
wire [47:2] tsd1_wr_tnpc;
wire [15:0] teg1_ecc;
wire [15:0] tem1_ecc;
wire tel1_scanin;
wire tel1_scanout;
wire [15:0] tsa1_ecc;
wire [15:0] ted1_syndrome;
wire ted10_cecc_err;
wire ted10_uecc_err;
wire ted10_uecc_err_;
wire ted11_cecc_err;
wire ted11_uecc_err;
wire ted11_uecc_err_;
wire [15:0] tel1_syndrome;
wire [15:0] tel1_ecc;
wire [15:0] tel1_crit_ecc;
wire tel1_tsac;
wire tel1_tsau;
wire [135:0] tsd1_ted_mra_rd_data;
wire [135:0] tsb1_data_out;
wire tsa1_scanin;
wire tsa1_scanout;
wire [29:0] tsa1_rd_data;
wire [8:0] tsa1_trap_type;
wire [47:2] tsa1_tpc;
wire [47:2] tsa1_tnpc;
wire tsd0_wmr_scanin;
wire tsd0_wmr_scanout;
wire tsd0_scanin;
wire tsd0_scanout;
wire [1:0] asi_wr_mondo_head;
wire [1:0] asi_wr_mondo_tail;
wire [1:0] asi_wr_device_head;
wire [1:0] asi_wr_device_tail;
wire [1:0] asi_wr_res_err_head;
wire [1:0] asi_wr_res_err_tail;
wire [1:0] asi_wr_nonres_err_head;
wire [1:0] asi_wr_nonres_err_tail;
wire [1:0] asi_rd_iqr_reg;
wire [1:0] asi_rd_tpc;
wire [1:0] asi_wr_tpc;
wire [1:0] asi_rd_tnpc;
wire [1:0] asi_wr_tnpc;
wire [1:0] asi_rd_tstate;
wire [1:0] asi_wr_tstate;
wire [1:0] asi_rd_tt;
wire [1:0] asi_wr_tt;
wire [1:0] asi_rd_htstate;
wire [1:0] asi_wr_htstate;
wire [7:0] asi_wr_tba;
wire [7:0] asi_wr_pstate;
wire [7:0] asi_wr_hpstate;
wire [7:0] asi_wr_htba;
wire [7:0] asi_rd_asireg;
wire [1:0] asi_rd_tba_htba;
wire [1:0] asi_rd_pstate_hpstate;
wire asi_tsd0_wr_data_12;
wire [10:8] asi_tsd0_wr_data_10_08;
wire [5:0] asi_tsd0_wr_data_05_00;
wire [1:0] tsd0_asi_data;
wire [10:0] tsd0_shadow_pstate;
wire [47:2] tsd0_shadow_tpc;
wire [8:0] tsd0_shadow_tt;
wire [31:0] tsd0_mbist_data;
wire tsd1_wmr_scanin;
wire tsd1_wmr_scanout;
wire tsd1_scanin;
wire tsd1_scanout;
wire asi_tsd1_wr_data_12;
wire [10:8] asi_tsd1_wr_data_10_08;
wire [5:0] asi_tsd1_wr_data_05_00;
wire [1:0] tsd1_asi_data;
wire [10:0] tsd1_shadow_pstate;
wire [47:2] tsd1_shadow_tpc;
wire [8:0] tsd1_shadow_tt;
wire [31:0] tsd1_mbist_data;
wire asi_wmr_scanin;
wire asi_wmr_scanout;
wire asi_scanin;
wire asi_scanout;
wire tic_scanin;
wire tic_scanout;
wire tca_scanin;
wire tca_scanout;
wire [4:0] tic_cmpr_addr;
wire tic_cmpr_rd_en;
wire tic_cmpr_wr_en;
wire [7:0] cem_ecc;
wire asi_tca_wr_data_63;
wire [7:0] tca_ecc;
wire [63:0] tca_cmpr_data_in;
wire cep_scanin;
wire cep_scanout;
wire [63:0] cep_wr_data;
wire [7:0] ceg_ecc;
wire asi_error_tccu;
wire cel_scanin;
wire cel_scanout;
wire [63:0] tic_cmpr_data;
wire [7:0] cel_crit_ecc;
wire [7:0] ced_syndrome;
wire ced_cecc_err;
wire ced_uecc_err;
wire ced_uecc_err__unused;
wire cer_scanin;
wire cer_scanout;
wire ras_wmr_scanin;
wire ras_wmr_scanout;
wire ras_scanin;
wire ras_scanout;
wire [61:0] cth_wr_data;
wire dfd_wmr_scanin;
wire dfd_wmr_scanout;
wire dfd_scanin;
wire dfd_scanout;
wire sse_scanin;
wire sse_scanout;
wire shscan_l2clk;
wire asi_ece_exc;
wire asi_eue_exc;
wire [2:0] asi_ecc_tid;
wire [63:46] asi_decr;
wire asi_rd_iaw;
wire [63:0] cth_irl_cleared;
wire tlu_cerer_l2nd;
wire [7:0] cxi_wr_int_dis;
wire [5:0] cxi_int_dis_vec;
wire cxi_l2_soc_sre;
wire [1:0] cxi_l2_soc_err_type;
wire [2:0] cxi_l2_soc_tid;
wire cxi_l2_err;
wire cxi_soc_err;
wire [7:0] asi_wr_int_rec;
wire [7:0] asi_rd_inc_vec_2;
wire [2:0] asi_int_rec_mux_sel_in;
wire asi_rd_int_rec;
wire asi_rd_inc_vec;
wire asi_wr_any_int_rec;
wire asi_rd_stage_1;
wire [47:0] dfd_asi_data;
wire [18:0] dfd_asi_desr;
wire [63:0] cth_asi_data;
wire [4:0] tic_addr;
wire tic_not_valid;
wire tic_match;
wire cel_tccd;
wire cel_tcud;
wire [4:0] asi_tsa_rd_addr;
wire asi_tsa_rd_iqr_ecc;
wire [1:0] asi_tsa_tid;
wire [4:0] asi_mbist_addr;
wire [7:0] asi_error_mask;
wire asi_mbist_run;
wire [2:0] asi_rd_iqr;
wire [2:0] asi_rd_h_pstate_tba;
wire [47:0] asi_tsa_wr_data;
wire asi_tsa_wr_data_npc_oor_va;
wire asi_tsa_wr_data_npc_nonseq;
wire [7:0] asi_mbist_ecc_in;
wire [3:0] asi_mbist_cmpsel;
wire mbd_compare;
wire [63:0] tic_asi_data;
wire [7:0] cel_ecc;
wire [63:0] cer_asi_data;
wire cel_tccp;
wire cel_tcup;
wire [7:0] dfd_desr_f;
wire [7:0] dfd_fesr_f;
wire asi_rd_tick;
wire asi_wr_tick;
wire [4:0] asi_tca_addr;
wire asi_tca_addr_valid;
wire asi_tca_wr;
wire asi_rd_cerer;
wire asi_rd_ceter;
wire asi_wr_cerer;
wire [2:0] asi_ceter_tid;
wire asi_wr_ceter;
wire [2:0] asi_rd_tid;
wire asi_rd_isfsr;
wire asi_rd_dsfsr;
wire asi_rd_dsfar;
wire asi_rd_desr;
wire asi_rd_fesr;
wire [7:0] asi_wr_isfsr;
wire [7:0] asi_wr_dsfsr;
wire [7:0] asi_wr_dsfar;
wire asi_tsac;
wire asi_tsau;
wire [2:0] asi_tsacu_tid;
wire asi_stg1_en;
wire [7:0] asi_mbd_compare_data;
wire asi_mbd_sel_tsd0;
wire asi_mbd_sel_tsd1;
wire asi_mbd_sel_tic;
wire asi_tccup_in;
wire asi_tccud_in;
wire [2:0] tlu_tca_tid;
wire [1:0] tlu_tca_index;
wire [31:0] tic_mbist_data;
wire [1:0] tic_exu_address0_b;
wire [1:0] tic_exu_address1_b;
wire tlu_cerer_tccp;
wire tlu_cerer_tcup;
wire tlu_cerer_tccd;
wire tlu_cerer_tcud;
wire [7:0] cel_syndrome;
wire [7:0] dfd_desr_s;
wire [1:0] dfd_fesr_priv_0;
wire [1:0] dfd_fesr_priv_1;
wire [1:0] dfd_fesr_priv_2;
wire [1:0] dfd_fesr_priv_3;
wire [1:0] dfd_fesr_priv_4;
wire [1:0] dfd_fesr_priv_5;
wire [1:0] dfd_fesr_priv_6;
wire [1:0] dfd_fesr_priv_7;
wire [3:0] ras_asi_data;
wire [19:0] ras_dsfar_0;
wire [19:0] ras_dsfar_1;
wire [19:0] ras_dsfar_2;
wire [19:0] ras_dsfar_3;
wire [19:0] ras_dsfar_4;
wire [19:0] ras_dsfar_5;
wire [19:0] ras_dsfar_6;
wire [19:0] ras_dsfar_7;
wire [7:0] ras_dsfar_sel_lsu_va;
wire [7:0] ras_dsfar_sel_ras;
wire [7:0] ras_dsfar_sel_tsa;
wire [7:0] ras_rd_dsfar;
wire [61:56] ras_desr_et_0;
wire [61:56] ras_desr_et_1;
wire [61:56] ras_desr_et_2;
wire [61:56] ras_desr_et_3;
wire [61:56] ras_desr_et_4;
wire [61:56] ras_desr_et_5;
wire [61:56] ras_desr_et_6;
wire [61:56] ras_desr_et_7;
wire [10:0] ras_desr_ea_0;
wire [10:0] ras_desr_ea_1;
wire [10:0] ras_desr_ea_2;
wire [10:0] ras_desr_ea_3;
wire [10:0] ras_desr_ea_4;
wire [10:0] ras_desr_ea_5;
wire [10:0] ras_desr_ea_6;
wire [10:0] ras_desr_ea_7;
wire ras_desr_me_0;
wire ras_desr_me_1;
wire ras_desr_me_2;
wire ras_desr_me_3;
wire ras_desr_me_4;
wire ras_desr_me_5;
wire ras_desr_me_6;
wire ras_desr_me_7;
wire [7:0] ras_desr_en;
wire [7:0] ras_write_desr_1st;
wire [7:0] ras_write_desr_2nd;
wire [7:0] ras_rd_desr;
wire [61:60] ras_fesr_et_0;
wire [61:60] ras_fesr_et_1;
wire [61:60] ras_fesr_et_2;
wire [61:60] ras_fesr_et_3;
wire [61:60] ras_fesr_et_4;
wire [61:60] ras_fesr_et_5;
wire [61:60] ras_fesr_et_6;
wire [61:60] ras_fesr_et_7;
wire [59:55] ras_fesr_ea_0;
wire [59:55] ras_fesr_ea_1;
wire [59:55] ras_fesr_ea_2;
wire [59:55] ras_fesr_ea_3;
wire [59:55] ras_fesr_ea_4;
wire [59:55] ras_fesr_ea_5;
wire [59:55] ras_fesr_ea_6;
wire [59:55] ras_fesr_ea_7;
wire [7:0] ras_fesr_en;
wire [7:0] ras_write_fesr;
wire [59:58] ras_fesr_priv;
wire [7:0] ras_update_priv;
wire [7:0] ras_rd_fesr;
wire sse_shscan_clk_stop;
wire [47:2] sse_shadow_pc;


input		l2clk;		
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		tcu_dectest;
input		tcu_muxtest;
input		tcu_array_wr_inhibit;
input		tcu_se_scancollar_in;

input	[3:0]	hver_mask_minor_rev;	// Input to spc for easy metal change

input 		spc_aclk_wmr;		// Warm reset (non)scan
input		lb_scan_en_wmr;
input		wmr_scan_in;

// RSTVADDR (POR address) control
input 		tcu_wmr_vec_mask;

// TICK register enable
input 		cmp_tick_enable;

input		lsu_asi_clken;		// Power management
input		lsu_tlu_pmen;		// Power management

// MBIST
input		mbi_tsa0_write_en;	// MBIST write control
input		mbi_tsa1_write_en;	// MBIST write control
input		mbi_tca_write_en;	// MBIST write control
input	[4:0]	mbi_addr;		// 32 entry addressability for MBIST
input		mbi_run;		// Select MBIST controls
input	[7:0]	mbi_wdata;		// MBIST write data
input		mbi_tsa0_read_en;	// MBIST read control
input		mbi_tsa1_read_en;	// MBIST read control
input		mbi_tca_read_en;	// MBIST read control
input	[3:0]	mbi_tlu_cmpsel;		// Mux (NPE) between 32 bit chunks 

input		tcu_shscan_pce_ov;	// Shadow scan controls
input		tcu_shscan_clk_stop;
input		tcu_shscan_aclk;
input		tcu_shscan_bclk;
input		tcu_shscan_scan_in;
input		tcu_shscan_scan_en;
input	[2:0]	tcu_shscanid;		// Select which thread to shadow

input	[7:0]	tcu_core_running;
input		tcu_ss_mode;		// Core is in single step mode
input		tcu_do_mode;		// Core is in disable overlap mode
input		tcu_ss_request;		// Enabled threads should single step

input	[7:0]	ftu_ifu_quiesce;
input	[7:0]	pku_quiesce;

input	[2:0]	ftu_excp_way_d;
input	[2:0]	ftu_excp_tid_d;
input		ftu_excp_way_valid_d;

input 	[1:0]	dec_inst0_cnt;		// Count of instructions in E, M, B
input 	[1:0]	dec_inst1_cnt;		// Count of instructions in E, M, B
input	[7:0]	dec_raw_pick_p;		// Decoded TID for instructions at P
input	[1:0]	dec_tid0_m;		// TID for instruction in TG0 at M
input	[1:0]	dec_tid1_m;		// TID for instruction in TG1 at M
input 	[1:0]	dec_inst_valid_m;	// Valid instruction
input 	[1:0]	dec_lsu_inst_m;		// LSU instruction
input 	[1:0]	dec_fgu_inst_m;		// FGU instruction
input	[1:0]	dec_illegal_inst_m;	// Illegal instruction
input	[4:0]	dec_exc0_m;		// Exceptions before the ibuffer
input	[4:0]	dec_exc1_m;		// Exceptions before the ibuffer
input	[1:0]	dec_done_inst_m;	// DONE
input	[1:0]	dec_retry_inst_m;	// RETRY
input	[1:0]	dec_sir_inst_m;		// Software initiated reset
input	[1:0]	dec_hpriv_exc_m;	// Instruction has hyperprivilege exc
input	[1:0]	dec_priv_exc_m;		// Instruction has privilege exc
input	[1:0]	dec_fpdisable_exc_m;	// Floating-point disabled exception
input	[1:0]	dec_br_taken_m;		// Branch in M is taken
input	[1:0]	dec_annul_ds_m;		// Branch in M annuls delay slot
input	[1:0]	dec_ds_m;		// Instruction is in a delay slot
input	[1:0]	dec_icache_perr_m;	// Icache data array had parity error
input	[1:0]	dec_cti_inst_m;
input	[1:0] dec_flush_b;		// Flush instruction in B

input	[1:0]	exu_ibp_m;		// Instruction breakpoint
input	[1:0]	exu_tcc_m;		// Trap on condition codes
input	[1:0]	exu_tof_m;		// Tag overflow (TADccTV, TSUBccTV)
input	[1:0]	exu_cecc_m;		// Correctable ECC error on source
input	[1:0]	exu_uecc_m;		// Uncorrectable ECC error on source
input	[4:0]	exu0_ecc_addr_m;	// Address for ECC error
input	[4:0]	exu1_ecc_addr_m;	// Address for ECC error
input	[7:0]	exu0_ecc_check_m;	// ECC bits
input	[7:0]	exu1_ecc_check_m;	// ECC bits
input	[1:0]	exu_oor_va_m;		// VA is out of range
input	[1:0]	exu_misalign_m;		// Misaligned address for JMPL, RETURN
input	[1:0]	exu_spill_b;
input	[1:0]	exu_fill_m; 
input	[1:0]	exu_normal_b; 
input	[1:0]	exu_cleanwin_b;
input	[2:0]	exu0_wstate_b;  
input	[2:0]	exu1_wstate_b;  
input	[7:0]	exu0_ccr0;
input	[7:0]	exu0_ccr1;
input	[7:0]	exu0_ccr2;
input	[7:0]	exu0_ccr3;
input	[7:0]	exu1_ccr0;
input	[7:0]	exu1_ccr1;
input	[7:0]	exu1_ccr2;
input	[7:0]	exu1_ccr3;
input	[2:0]	exu0_cwp0;
input	[2:0]	exu0_cwp1;
input	[2:0]	exu0_cwp2;
input	[2:0]	exu0_cwp3;
input	[2:0]	exu1_cwp0;
input	[2:0]	exu1_cwp1;
input	[2:0]	exu1_cwp2;
input	[2:0]	exu1_cwp3;
input	[7:0] exu0_trap_number_b;	// Bits 7:0 of the ALU result
input	[7:0] exu1_trap_number_b;
input	[1:0]	exu_tlu_window_block;	// EXU needs hole for CWP change
input	[47:0]	exu_address0_e;		// Target address for branch in TG0
input	[47:0]	exu_address1_e;		// Target address for branch in TG1

input		lsu_lddf_align_b;
input		lsu_stdf_align_b;
input		lsu_illegal_inst_b;
input		lsu_daccess_prot_b;
input		lsu_priv_action_b;
input		lsu_va_watchpoint_b;
input		lsu_pa_watchpoint_b;
input		lsu_align_b;		// Alignment exception
input		lsu_tlb_miss_b_;	// TLB miss
input		lsu_dae_invalid_asi_b;
input		lsu_dae_nc_page_b;
input		lsu_dae_nfo_page_b;
input		lsu_dae_priv_viol_b;
input		lsu_dae_so_page; 
input		lsu_priv_action_g;
input	[2:0]	lsu_tid_g;		// TID for exceptions from G
input	[7:0]	lsu_trap_flush;		// Flush thread and redirect to NPC
input 		lsu_tlb_bypass_b;	// TLB in bypass mode
input 		lsu_tlb_real_b;		// TLB doing RA->PA translation
input 		lsu_sync_inst_b;	// Instruction will get a trap flush
input	[7:0]	lsu_stb_empty;		// Store buffer empty (for entering RED)
input		lsu_tlu_twocycle_m;	// LSU takes extra cycle on this inst
input	[7:0]	lsu_block_store_b;	// LSU reads FRF for block store
input		lsu_dcmh_err_g;		// LSU data cache multiple hit
input		lsu_dcvp_err_g;		// LSU data cache valid parity error
input		lsu_dctp_err_g;		// LSU data cache tag parity error
input		lsu_dcdp_err_g;		// LSU data cache parity error
input		lsu_dcl2c_err_g;	// LSU data cache L2 correctable ECC
input		lsu_dcl2u_err_g;	// LSU data cache L2 uncorrectable ECC
input		lsu_dcl2nd_err_g;	// LSU data cache L2 NotData
input		lsu_dcsoc_err_g;	// LSU data cache SOC error
input	[2:0]	lsu_dcerr_tid_g;	// TID for G stage errors (above)
input	[8:0]	lsu_dcerr_sfar_g;	// DSFAR data for data cache errors
input		lsu_sbdlc_err_g;        // STB RAW error (CE)
input		lsu_sbdlu_err_g;        // STB RAW error (UE)
input		lsu_sbdpc_err_g;        // STB read for issue data (CE)
input		lsu_sbdpu_err_g;        // STB read for issue data (UE)
input		lsu_sbapp_err_g;        // STB read for issue addr parity error
input		lsu_sbdiou_err_g;       // STB read for issue IO/ext ASI parity
input	[2:0]	lsu_stberr_tid_g;       // TID of STB error
input	[2:0]	lsu_stberr_index_g;	// Index of STB error
input	[1:0]	lsu_stberr_priv_g;	// Privilege level for STB entry
input		lsu_stb_flush_g;	// STB entry flushed STB (capture priv)
input		lsu_dttp_err_b;         // DTLB tag parity error
input		lsu_dtdp_err_b;         // DTLB data parity error
input		lsu_dtmh_err_b;         // DTLB data parity error 
input		lsu_perfmon_trap_b;	// Take pic_overflow on this instruction
input		lsu_perfmon_trap_g;	// Take pic_overflow on this instruction
input	[47:0]	lsu_va_b;		// For DSFAR
input		lsu_ext_interrupt;	// Write to interrupt vector dispatch
input	[1:0]	lsu_ext_int_type;	// Type for CPX packet
input	[5:0]	lsu_ext_int_vec;	// Interrupt vector
input	[2:0]	lsu_ext_int_tid;

input	[15:0]	l15_spc_data1;		// Lowest 16 bits of return data from L2
input	[17:0]	l15_spc_cpkt;		// Control part of cpx packet
					// NOTE: 17:13 == 144:140
					//       12 is always 1'b0
					// 	 11:0  == 139:128
input		l15_spc_valid;

input 	[31:0]	lsu_asi_error_inject; 	// 31:Enb 22:TCCU 21:TSAU 7:0 ECCMASK
input 	[64:0]	lsu_rngf_cdbus; 	// control/data bus from lsu


input		fgu_pdist_beat2_fx1;	// Second part of PDIST in FX1
input		fgu_predict_fx2;	// Exception predicted
input		fgu_cecc_fx2;		// Correctable ECC Error on FRF
input		fgu_uecc_fx2;		// Uncorrectable ECC Error on FRF
input	[5:0]	fgu_ecc_addr_fx2;	// Address for ECC error
input	[13:0]	fgu_ecc_check_fx2;	// ECC bits
input		fgu_fpx_ieee_trap_fw;	// IEEE 754 trap exception
input		fgu_fpd_ieee_trap_fw;	// IEEE 754 trap exception
input		fgu_fpx_unfin_fw; 	// Other FGU exception
input	[2:0]	fgu_fpx_trap_tid_fw;	// TID for FGU exceptions other than div
input		fgu_fpd_unfin_fw; 	// Other divide exception
input		fgu_fpd_idiv0_trap_fw;
input	[2:0]	fgu_fpd_trap_tid_fw;	// TID for divide exception

input	[7:0]	mmu_hw_tw_enable;	// Hardware tablewalk enable 
input	[7:0]	mmu_write_itlb;		// Reload the ITLB
input	[7:0]	mmu_reload_done;	// Hardware tablewalk done
input	[7:0]	mmu_i_unauth_access;	// Hardware tablewalk ITSB with EP=0
input	[7:0]	mmu_i_tsb_miss;		// Hardware tablewalk missed
input	[7:0]	mmu_d_tsb_miss;		// Hardware tablewalk missed
input	[7:0]	mmu_i_tte_outofrange;	// RA out of range
input	[7:0]	mmu_d_tte_outofrange;	// RA out of range
input	[47:0]	mmu_itte_tag_data;
input	[64:0]	mmu_asi_data;		// ASI read data for fast bus
input		mmu_asi_read;		// Valid for MMU ASI read
input		mmu_dae_req;		// data_access_exception for bad pg size
input	[2:0]	mmu_dae_tid;		
input 		mmu_asi_cecc; 		// Correctable ECC error on ASI read
input 		mmu_asi_uecc; 		// Uncorrectable ECC error on ASI read
input	[2:0]	mmu_asi_tid;		// Thread for reported error
input	[10:0]	mmu_asi_index;		// Syndrome and index of the failure
input		mmu_asi_mra_not_sca;	// 1: MRA error 0: Scratchpad error
input	[7:0]	mmu_i_l2cerr;           // HW TW had L2 CE on I rld
input	[7:0]	mmu_d_l2cerr;           // HW TW had L2 CE on D rld
input	[7:0]	mmu_i_eccerr;		// HW TW had MRA or L2 error on I rld
input	[7:0]	mmu_d_eccerr;		// HW TW had MRA or L2 error on D rld
input	[2:0]	mmu_thr0_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
input	[2:0]	mmu_thr1_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
input	[2:0]	mmu_thr2_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
input	[2:0]	mmu_thr3_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
input	[2:0]	mmu_thr4_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
input	[2:0]	mmu_thr5_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
input	[2:0]	mmu_thr6_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
input	[2:0]	mmu_thr7_err_type;	// [2]: 1-MRA 0-L2 [1:0] ND U C - (3-0)
input	[2:0]	mmu_thr0_err_index;	
input	[2:0]	mmu_thr1_err_index;	
input	[2:0]	mmu_thr2_err_index;	
input	[2:0]	mmu_thr3_err_index;	
input	[2:0]	mmu_thr4_err_index;	
input	[2:0]	mmu_thr5_err_index;	
input	[2:0]	mmu_thr6_err_index;	
input	[2:0]	mmu_thr7_err_index;	

input		spu_pmu_ma_busy;	// Must idle before parking
input		spu_tlu_cwq_busy;	// Must idle before soft stop parking
input	[10:0]	spu_tlu_mamu_err_req;	// SPU MAMEM parity error
input	[4:0]	spu_tlu_ma_int_req;	// SPU MA  4 err  3 vld  2:0 thread ID
input	[3:0]	spu_tlu_cwq_int_req;	// SPU CWQ trap rq  3 vld  2:0 thread ID
input	[5:0]	spu_tlu_l2_error;	// MAL2[C,U,ND],CWQL2[C,U,ND]


input	[7:0]	pmu_tlu_trap_m;		// PMU trap; kill instruction in M 
input	[7:0]	pmu_tlu_debug_event;	// PMU event; soft/hard stop or pulse 


output		scan_out;

output		wmr_scan_out;		// Warm reset (non)scan

output		spc_shscan_scan_out;	// Shadow scan

output	[7:0]	tlu_core_running_status;
output		tlu_ss_complete;

output		tlu_hardstop_request;	
output		tlu_softstop_request;	
output		tlu_trigger_pulse;	
output	[1:0]	tlu_dbg_instr_cmt_grp0;	
output	[1:0]	tlu_dbg_instr_cmt_grp1;	

output	[7:0]	tlu_flush_ifu;		// Flush specified thread

output	[1:0]	tlu_window_block;	// Block decode of CWP altering ops

output	[7:0]	tlu_retry_state;	// DEC should not wait for delay slot

output	[7:0]	tlu_halted;		// Pick should stall;

output 	[47:2]	tlu_pc_0_d;
output 	[47:2]	tlu_pc_1_d;
output	[1:0]	tlu_flush_exu_b;	// EXU to flush instr in B stage
output	[7:0]	tlu_ccr_0;
output	[7:0]	tlu_ccr_1;
output	[2:0]	tlu_cwp_0;
output	[2:0]	tlu_cwp_1;
output		tlu_ccr_cwp_0_valid;
output		tlu_ccr_cwp_1_valid;
output	[1:0]	tlu_ccr_cwp_0_tid;
output	[1:0]	tlu_ccr_cwp_1_tid;
output	[1:0]	tlu_gl0;
output	[1:0]	tlu_gl1;
output	[1:0]	tlu_gl2;
output	[1:0]	tlu_gl3;
output	[1:0]	tlu_gl4;
output	[1:0]	tlu_gl5;
output	[1:0]	tlu_gl6;
output	[1:0]	tlu_gl7;
output	[1:0]	tlu_itlb_bypass_e;

output 		tlu_flush_lsu_b;	// LSU to flush instr in B stage

output		tlu_flush_fgu_b;	// FGU to flush instr in B stage

output	[47:0]	tlu_trap_pc_0;
output		tlu_trap_pc_0_valid;
output	[1:0]	tlu_trap_0_tid;

output	[47:0]	tlu_trap_pc_1;
output		tlu_trap_pc_1_valid;
output	[1:0]	tlu_trap_1_tid;

output	[1:0]	tlu_retry;
output	[1:0]	tlu_ifu_invalidate;	// Forces IFU to invalidate, refetch

output	[1:0]	tlu_itlb_reload;
output	[7:0]	tlu_itlb_bypass;

output 	[7:0]	tlu_release_tte;

output 	[64:0]	tlu_rngf_cdbus;
output 		tlu_rngf_cdbus_error;	// Same cycle as data on cdbus

output	[7:0]	tlu_asi_0;
output	[7:0]	tlu_asi_1;
output		tlu_asi_0_valid;
output		tlu_asi_1_valid;
output	[1:0]	tlu_asi_0_tid;
output	[1:0]	tlu_asi_1_tid;

output	[7:0]	tlu_tl_gt_0;
output	[7:0]	tlu_lsu_clear_ctl_reg_;

output 	[7:0]	tlu_load_i_tag_access_p;
output 	[7:0]	tlu_load_i_tag_access_n;
output 	[7:0]	tlu_load_d_tag_access;
output 	[7:0]	tlu_load_d_tag_access_r;
output 	[47:2]	tlu_npc_w;
output 	[47:13]	tlu_pc_0_w;
output 	[47:13]	tlu_pc_1_w;
output 	[7:0]	tlu_iht_request;	// ITLB hardware tablewalk request
output 	[7:0]	tlu_dht_request;	// DTLB hardware tablewalk request
output	[7:0]	tlu_mmu_tl_gt_0;


output 	[1:0]	tlu_flush_pmu_b;
output 	[1:0]	tlu_flush_pmu_w;
output 	[7:0]	tlu_pmu_trap_taken;
output 	[1:0]	tlu_pmu_trap_mask_e;

output	[7:0]	tlu_lsu_hpstate_hpriv;
output	[7:0]	tlu_lsu_pstate_priv;
output	[7:0]	tlu_ifu_hpstate_hpriv;
output	[7:0]	tlu_ifu_pstate_priv;
output	[7:0]	tlu_pmu_hpstate_hpriv;
output	[7:0]	tlu_pmu_pstate_priv;
output	[7:0]	tlu_dec_hpstate_hpriv;
output	[7:0]	tlu_dec_pstate_priv;
output	[7:0]	tlu_dec_pstate_pef;
output	[7:0]	tlu_pstate_cle;
output	[7:0]	tlu_pstate_am;

output		tlu_cerer_ittp 		;
output		tlu_cerer_itdp 		;
output		tlu_cerer_ittm 		;
output		tlu_cerer_hwtwmu 	;
output		tlu_cerer_hwtwl2	;
output		tlu_cerer_icl2c 	;
output		tlu_cerer_icl2u 	;
output		tlu_cerer_icl2nd 	;
output		tlu_cerer_irf 		;
output		tlu_cerer_frf 		;
output		tlu_cerer_dttp 		;
output		tlu_cerer_dttm 		;
output		tlu_cerer_dtdp 		;
output		tlu_cerer_dcl2c 	;
output		tlu_cerer_dcl2u 	;
output		tlu_cerer_dcl2nd 	;
output		tlu_cerer_sbdlc 	;
output		tlu_cerer_sbdlu 	;
output		tlu_cerer_mrau 		;
output		tlu_cerer_scac 		;
output		tlu_cerer_scau 		;
output		tlu_cerer_sbapp 	;
output		tlu_cerer_l2c_socc	;
output		tlu_cerer_l2u_socu	;
output		tlu_cerer_icvp 		;
output		tlu_cerer_ictp 		;
output		tlu_cerer_ictm 		;
output		tlu_cerer_icdp 		;
output		tlu_cerer_dcvp 		;
output		tlu_cerer_dctp 		;
output		tlu_cerer_dctm 		;
output		tlu_cerer_dcdp 		;
output		tlu_cerer_sbdpc 	;
output		tlu_cerer_sbdpu 	;
output		tlu_cerer_mamu 		;
output		tlu_cerer_mal2c 	;
output		tlu_cerer_mal2u 	;
output		tlu_cerer_mal2nd 	;
output		tlu_cerer_cwql2c 	;
output		tlu_cerer_cwql2u 	;
output		tlu_cerer_cwql2nd 	;
output		tlu_cerer_sbdiou 	;

output	[7:0]	tlu_ceter_pscce;

output	[1:0]	tlu_tag_access_tid_0_b;	// Tag access power management
output		tlu_i_tag_access_0_b;	// Tag access power management
output		tlu_d_tag_access_0_b;	// Tag access power management
output	[1:0]	tlu_tag_access_tid_1_b;	// Tag access power management
output		tlu_i_tag_access_1_b;	// Tag access power management
output		tlu_d_tag_access_1_b;	// Tag access power management

output		tlu_mbi_tsa0_fail;	// MBIST
output		tlu_mbi_tsa1_fail;	// MBIST
output		tlu_mbi_tca_fail;	// MBIST

output 	[7:0]	tlu_spec_enable;


//////////////////////////////////////////////////////////////////////////////

assign error_inject_unused[30:23] =
       lsu_asi_error_inject[30:23];
assign error_inject_unused[20:8] =
       lsu_asi_error_inject[20:8];

assign tlu_cerer_sbdiou =
	tlu_cerer_sbdpu;

assign rd_pce = 1'b1;
assign wr_pce = 1'b1;
assign bist_clk_mux_sel = 1'b0;
assign tcu_scan_en_wmr = lb_scan_en_wmr;


////////////////////////////////////////////////////////////////////////////////
// Flush Logic: one for each thread group and datapath to merge LSU, FGU flushes
tlu_fls_ctl fls0 ( 
	.wmr_scan_in(fls0_wmr_scanin),
	.wmr_scan_out(fls0_wmr_scanout),
	.scan_in(fls0_scanin),
	.scan_out(fls0_scanout),
	.l2clk			(l2clk				),
	.thread_group		(1'b0				),
	.trl_shscanid		({trl0_shscanid_2	       ,
				  trl0_shscanid		[1:0]}),
	.tcu_core_running	(tcu_core_running	[3:0]	),
	.cxi_xir		(cxi_xir		[3:0]	),
	.cxi_ivt		(cxi_ivt		[3:0]	),
	.dec_raw_pick_p		(dec_raw_pick_p		[3:1]	),
	.dec_tid_m		(dec_tid0_m		[1:0]	),
	.dec_inst_valid_m	(dec_inst_valid_m	[0   ]	),
	.dec_lsu_inst_m		(dec_lsu_inst_m		[0   ]	),
	.dec_fgu_inst_m		(dec_fgu_inst_m		[0   ]	),
	.dec_illegal_inst_m	(dec_illegal_inst_m	[0   ]	),
	.dec_exc_m		(dec_exc0_m		[4:0]	),
	.dec_done_inst_m	(dec_done_inst_m	[0   ]	),
	.dec_retry_inst_m	(dec_retry_inst_m	[0   ]	),
	.dec_sir_inst_m		(dec_sir_inst_m		[0   ]	),
	.dec_hpriv_exc_m	(dec_hpriv_exc_m	[0   ]	),
	.dec_priv_exc_m		(dec_priv_exc_m		[0   ]	),
	.dec_fpdisable_exc_m	(dec_fpdisable_exc_m	[0   ]	),
	.dec_br_taken_m		(dec_br_taken_m		[0   ]	),
	.dec_annul_ds_m		(dec_annul_ds_m		[0   ]	),
	.dec_ds_m		(dec_ds_m		[0   ]	),
	.dec_icache_perr_m	(dec_icache_perr_m	[0   ]	),
	.dec_cti_inst_m		(dec_cti_inst_m		[0   ]	),
	.dec_flush_b		(dec_flush_b		[0   ]	),
	.exu_ibp_m		(exu_ibp_m		[0   ]	),
	.exu_tcc_m		(exu_tcc_m		[0   ]	),
	.exu_tof_m		(exu_tof_m		[0   ]	),
	.exu_cecc_m		(exu_cecc_m		[0   ]	),
	.exu_uecc_m		(exu_uecc_m		[0   ]	),
	.exu_oor_va_m		(exu_oor_va_m		[0   ]	),
	.exu_misalign_m		(exu_misalign_m		[0   ]	),
	.exu_spill_b		(exu_spill_b		[0   ]	),
	.exu_fill_m		(exu_fill_m		[0   ]	),
	.exu_normal_b		(exu_normal_b		[0   ]	),
	.exu_cleanwin_b		(exu_cleanwin_b		[0   ]	),
	.exu_wstate_b		(exu0_wstate_b		[2:0]	),
	.exu_trap_number_b	(exu0_trap_number_b	[7:0]	),
	.exu_cwp0		(exu0_cwp0		[2:0]	),
	.exu_cwp1		(exu0_cwp1		[2:0]	),
	.exu_cwp2		(exu0_cwp2		[2:0]	),
	.exu_cwp3		(exu0_cwp3		[2:0]	),
	.lsu_trap_flush		(lsu_trap_flush		[3:0]	),
	.lsu_spec_enable	(asi_spec_enable	[3:0]	),
	.lsu_block_store_b	(lsu_block_store_b	[3:0]	),
	.lsu_immu_enable	(asi_immu_enable	[3:0]	),
	.asi_irl_cleared	(asi_irl_cleared	[3:0]	),
	.asi_halt		(asi_halt		[3:0]	),
	.asi_clear_spu_trap_req	(asi_clear_spu_trap_req	[3:0]	),
	.tel_tsacu_exc		(tel_tsacu_exc		[3:0]	),
	.mmu_hw_tw_enable	(mmu_hw_tw_enable	[3:0]	),
	.mmu_i_unauth_access	(mmu_i_unauth_access	[3:0]	),
	.mmu_i_tsb_miss		(mmu_i_tsb_miss		[3:0]	),
	.mmu_d_tsb_miss		(mmu_d_tsb_miss		[3:0]	),
	.mmu_i_tte_outofrange	(mmu_i_tte_outofrange	[3:0]	),
	.mmu_d_tte_outofrange	(mmu_d_tte_outofrange	[3:0]	),
	.mmu_i_eccerr		(mmu_i_eccerr		[3:0]	),
	.mmu_d_eccerr		(mmu_d_eccerr		[3:0]	),
	.mmu_thr0_err_type_b1   (mmu_thr0_err_type	[1   ]	),
	.mmu_thr1_err_type_b1   (mmu_thr1_err_type	[1   ]	),
	.mmu_thr2_err_type_b1   (mmu_thr2_err_type	[1   ]	),
	.mmu_thr3_err_type_b1   (mmu_thr3_err_type	[1   ]	),
	.pmu_tlu_trap_m		(pmu_tlu_trap_m		[3:0]	),
	.pmu_tlu_debug_event	(pmu_tlu_debug_event	[3:0]	),
	.flsx_flush_lsu_b	(1'b0				),
	.flsx_flush_fgu_b	(1'b0				),
	.pct_iaw_exc_e		(pct0_iaw_exc_e		[1:0]	),
	.pct_npc_0_w		(pct_npc_0_w		[3:2]	),
	.pct_npc_1_w		(pct_npc_1_w		[3:2]	),
	.pct_npc_2_w		(pct_npc_2_w		[3:2]	),
	.pct_npc_3_w		(pct_npc_3_w		[3:2]	),
	.pct_pc_oor_va_e	(pct_pc_oor_va_e	[0   ]	),
	.trl_tl_eq_0		(trl_tl_eq_0		[3:0]	),
	.trl_pil_mask_15	(trl_pil_mask_15	[3:0]	),
	.trl_iln_exc		(trl_iln_exc		[3:0]	),
	.trl_hstick_match	(trl_hstick_match	[3:0]	),
	.trl_unhalt_		(trl_unhalt_		[3:0]	),
	.trl_tlz_exc		(trl_tlz_exc		[3:0]	),
	.trl_nns_exc		(trl_nns_exc		[3:0]	),
	.trl_ssc_exc		(trl_ssc_exc		[3:0]	),
	.trl_invalidate_pc	(trl_invalidate_pc	[3:0]	),
	.trl_invalidate_npc	(trl_invalidate_npc	[3:0]	),
	.trl_pc_sel_trap_pc	(trl_pc_sel_trap_pc	[3:0]	),
	.trl_fls_npc_en		(trl_fls_npc_en		[3:0]	),
	.trl_trap_taken		(trl_trap_taken		[3:0]	),
	.trl_take_sma		(trl0_take_sma			),
	.trl_take_cwq		(trl0_take_cwq			),
	.trl_take_xir		(trl0_take_xir			),
	.trl_take_ftt		(trl0_take_ftt			),
	.trl_core_running_status(trl_core_running_status[3:0]	),
	.trl_check_rqr		(trl0_tsa_wr_addr	[0   ]	),
	.tlu_ceter_de		(tlu_ceter_de		[3:0]	),
	.tlu_ceter_dhcce	(tlu_ceter_dhcce	[3:0]	),
	.tsd_hpstate_ibe	(tsd_hpstate_ibe	[3:0]	),
	.tsd_hpstate_hpriv	(tsd_hpstate_hpriv	[3:0]	),
	.tsd_hpstate_red	(tsd_hpstate_red	[3:0]	),
	.tsd_pstate_tct		(tsd_pstate_tct		[3:0]	),
	.tsd_pstate_priv	(tsd_pstate_priv	[3:0]	),
	.tsd_pstate_ie		(tsd_pstate_ie		[3:0]	),
	.tsd_pstate_am		(tsd_pstate_am		[3:0]	),
	.tsd_itlb_bypass	(tsd_itlb_bypass	[3:0]	),
	.tsd_mrqr_exc_		(tsd0_mrqr_exc_			),
	.tsd_dqr_exc_		(tsd0_dqr_exc_			),
	.asi_check_qr_exc	(asi_check_qr_exc	[3:0]	),
	.dfd_fls_desr_f		(dfd_fls_desr_f		[3:0]	),
	.dfd_fls_desr_s		(dfd_fls_desr_s		[3:0]	),
	.ras_precise_error	(ras_precise_error	[3:0]	),
	.ras_disrupting_error	(ras_disrupting_error	[3:0]	),
	.ras_deferred_error	(ras_deferred_error	[3:0]	),
	.fls_spc_hardstop_request(fls0_spc_hardstop_request	),
	.fls_spc_softstop_request(fls0_spc_softstop_request	),
	.fls_spc_trigger_pulse  (fls0_spc_trigger_pulse 	),
	.tlu_dbg_instr_cmt_grp 	(tlu_dbg_instr_cmt_grp0 [1:0]	),
	.tlu_flush_ifu		(tlu_flush_ifu		[3:0]	),
	.tlu_flush_exu_b	(tlu_flush_exu_b	[0   ]	),
	.tlu_flush_lsu_b	(tlu_flush_lsu_b_unused		),
	.tlu_flush_fgu_b	(tlu_flush_fgu_b_unused		),
	.tlu_flush_pmu_b	(tlu_flush_pmu_b	[0   ]	),
	.tlu_flush_pmu_w	(tlu_flush_pmu_w	[0   ]	),
	.tlu_load_i_tag_access_p(tlu_load_i_tag_access_p[3:0]	),
	.tlu_load_i_tag_access_n(tlu_load_i_tag_access_n[3:0]	),
	.tlu_load_d_tag_access	(tlu_load_d_tag_access	[3:0]	),
	.tlu_load_d_tag_access_r(tlu_load_d_tag_access_r[3:0]	),
	.fls_flush_lsu_b	(fls0_flush_lsu_b		),
	.fls_flush_fgu_b	(fls0_flush_fgu_b		),
	.fls_tid_d		(fls0_tid_d		[1:0]	),
	.fls_tid_dec_b		(fls0_tid_dec_b		[3:0]	),
	.fls_tid_dec_w		(fls0_tid_dec_w		[3:0]	),
	.fls_pc_sel_npc		(fls_pc_sel_npc		[3:0]	),
	.fls_pc_sel_npc_plus_4	(fls_pc_sel_npc_plus_4	[3:0]	),
	.fls_npc_sel_npc_plus_4	(fls_npc_sel_npc_plus_4	[3:0]	),
	.fls_npc_sel_npc_plus_8	(fls_npc_sel_npc_plus_8	[3:0]	),
	.fls_npc_sel_target	(fls_npc_sel_target	[3:0]	),
	.fls_npc_b_sel_npc	(fls0_npc_b_sel_npc		),
	.fls_pc_is_npc		(fls0_pc_is_npc			),
	.fls_pstate_am_d_	(fls_pstate_am_d_	[0   ]	),
	.fls_pstate_am_b_	(fls_pstate_am_b_	[0   ]	),
	.fls_pstate_am_w_	(fls_pstate_am_w_	[0   ]	),
	.fls_lsu_inst_w		(fls0_lsu_inst_w_unused		),
	.fls_dfd_lsu_inst_b	(fls0_dfd_lsu_inst_b		),
	.fls_wstate0		(fls_wstate0		[2:0]	),
	.fls_wstate1		(fls_wstate1		[2:0]	),
	.fls_wstate2		(fls_wstate2		[2:0]	),
	.fls_wstate3		(fls_wstate3 		[2:0]	),
	.fls_tcc_number_0	(fls_tcc_number_0	[7:0]	),
	.fls_tcc_number_1	(fls_tcc_number_1	[7:0]	),
	.fls_tcc_number_2	(fls_tcc_number_2	[7:0]	),
	.fls_tcc_number_3	(fls_tcc_number_3	[7:0]	),
	.fls_tid_dec_w_in	(fls_tid_dec_w_in	[3:0]	),
	.fls_por_request	(fls_por_request	[3:0]	),
	.fls_xir_request	(fls_xir_request	[3:0]	),
	.fls_ivt_request	(fls_ivt_request	[3:0]	),
	.fls_sir_request	(fls_sir_request	[3:0]	),
	.fls_itm_request	(fls_itm_request	[3:0]	),
	.fls_iln_request	(fls_iln_request	[3:0]	),
	.fls_hst_request	(fls_hst_request	[3:0]	),
	.fls_tlz_request	(fls_tlz_request	[3:0]	),
	.fls_sma_request	(fls_sma_request	[3:0]	),
	.fls_cwq_request	(fls_cwq_request	[3:0]	),
	.fls_ade_request	(fls_ade_request	[3:0]	),
	.fls_iae_request	(fls_iae_request	[3:0]	),
	.fls_ipe_request	(fls_ipe_request	[3:0]	),
	.fls_ipv_request	(fls_ipv_request	[0   ]	),
	.fls_inp_request	(fls_inp_request	[0   ]	),
	.fls_iar_request	(fls_iar_request	[0   ]	),
	.fls_irr_request	(fls_irr_request	[0   ]	),
	.fls_mar_request	(fls_mar_request	[0   ]	),
	.fls_mrr_request	(fls_mrr_request	[0   ]	),
	.fls_pro_request	(fls_pro_request	[0   ]	),
	.fls_ill_request	(fls_ill_request	[0   ]	),
	.fls_don_request	(fls_don_request	[0   ]	),
	.fls_ret_request	(fls_ret_request	[0   ]	),
	.fls_fpd_request	(fls_fpd_request	[0   ]	),
	.fls_snn_request	(fls_snn_request	[0   ]	),
	.fls_sno_request	(fls_sno_request	[0   ]	),
	.fls_fnn_request	(fls_fnn_request	[0   ]	),
	.fls_fno_request	(fls_fno_request	[0   ]	),
	.fls_clw_request	(fls_clw_request	[0   ]	),
	.fls_dtm_request	(fls_dtm_request	[3:0]	),
	.fls_ldf_request	(fls_ldf_request	[0   ]	),
	.fls_stf_request	(fls_stf_request	[0   ]	),
	.fls_dap_request	(fls_dap_request	[0   ]	),
	.fls_vaw_request	(fls_vaw_request	[0   ]	),
	.fls_iaw_request	(fls_iaw_request	[0   ]	),
	.fls_paw_request	(fls_paw_request	[0   ]	),
	.fls_maa_request	(fls_maa_request	[0   ]	),
	.fls_fpe_request	(fls_fpe_request	[0   ]	),
	.fls_fei_request	(fls_fei_request	[3:0]	),
	.fls_fof_request	(fls_fof_request	[3:0]	),
	.fls_pra_request	(fls_pra_request	[3:0]	),
	.fls_dia_request	(fls_dia_request	[0   ]	),
	.fls_ups_request	(fls_ups_request	[3:0]	),
	.fls_dpv_request	(fls_dpv_request	[0   ]	),
	.fls_dnc_request	(fls_dnc_request	[0   ]	),
	.fls_dnf_request	(fls_dnf_request	[0   ]	),
	.fls_dso_request	(fls_dso_request	[0   ]	),
	.fls_tof_request	(fls_tof_request	[0   ]	),
	.fls_dbz_request	(fls_dbz_request	[3:0]	),
	.fls_tcc_request	(fls_tcc_request	[0   ]	),
	.fls_dae_request	(fls_dae_request	[3:0]	),
	.fls_lsr_request	(fls_lsr_request	[3:0]	),
	.fls_irt_request	(fls_irt_request	[0   ]	),
	.fls_drt_request	(fls_drt_request	[0   ]	),
	.fls_pmu_request	(fls_pmu_request	[3:0]	),
	.fls_mqr_request	(fls_mqr_request	[3:0]	),
	.fls_dqr_request	(fls_dqr_request	[3:0]	),
	.fls_rqr_request	(fls_rqr_request	[3:0]	),
	.fls_idl_request	(fls_idl_request	[3:0]	),
	.fls_res_request	(fls_res_request	[3:0]	),
	.fls_ssr_request	(fls_ssr_request	[3:0]	),
	.fls_ssc_request	(fls_ssc_request	[3:0]	),
	.fls_nns_request	(fls_nns_request	[3:0]	),
	.fls_ime_request	(fls_ime_request	[3:0]	),
	.fls_dme_request	(fls_dme_request	[3:0]	),
	.fls_eer_request	(fls_eer_request	[3:0]	),
	.fls_icp_request	(fls_icp_request	[0   ]	),
	.fls_ftt_request	(fls_ftt_request	[3:0]	),
	.fls_ibp_request	(fls_ibp_request	[0   ]	),
	.fls_tct_request	(fls_tct_request	[0   ]	),
	.fls_ref_request	(fls_ref_request	[0   ]	),
	.fls_ipe_dme_request	(fls_ipe_dme_request	[0   ]	),
	.fls_pc_valid		(fls_pc_valid		[3:0]	),
	.fls_load_dsfar		(fls_load_dsfar		[3:0]	),
	.fls_irf_cecc_b		(fls_irf_cecc_b		[0   ]	),
	.fls_irf_uecc_b		(fls_irf_uecc_b		[0   ]	),
	.fls_kill_irf_ecc_w	(fls_kill_irf_ecc_w	[0   ]	),
	.fls_cwp0		(fls0_cwp0		[2:0]	),
	.fls_cwp1		(fls0_cwp1		[2:0]	),
	.fls_cwp2		(fls0_cwp2		[2:0]	),
	.fls_cwp3		(fls0_cwp3		[2:0]	),
	.fls_core_running	(fls_core_running	[3:0]	),
	.fls_ss_request		(fls_ss_request			),
	.fls_pct_pc_en		(fls_pct_pc_en		[3:0]	),
	.fls_pct_npc_en		(fls_pct_npc_en		[3:0]	),
	.fls_trl_l1en		(fls_trl_l1en		[3:0]	),
	.fls_npc_if_cnt_eq_1_d	(fls0_npc_if_cnt_eq_1_d	[4:2]	),
	.fls_npc_if_cnt_eq_2_d	(fls0_npc_if_cnt_eq_2_d	[4:2]	),
	.fls_npc_if_cnt_eq_3_d	(fls0_npc_if_cnt_eq_3_d	[4:2]	),
	.fls_flush		(fls_flush		[3:0]	),
	.fls_disrupting_flush_w	(fls_disrupting_flush_w	[0   ]	),
	.fls_f_cecc_w		(fls_f_cecc_w			),
	.fls_f_uecc_w		(fls_f_uecc_w			),
	.fls_ss_update_pc_w	(fls_ss_update_pc_w	[0   ]	),
	.tlu_iht_request	(tlu_iht_request	[3:0]	),
	.tlu_dht_request	(tlu_dht_request	[3:0]	),
	.tlu_itlb_bypass_e	(tlu_itlb_bypass_e	[0   ]	),
	.tlu_tag_access_tid_b	(tlu_tag_access_tid_0_b	[1:0]	),
	.tlu_i_tag_access_b	(tlu_i_tag_access_0_b		),
	.tlu_d_tag_access_b	(tlu_d_tag_access_0_b		),
	.tlu_retry_state	(tlu_retry_state	[3:0]	),
	.tlu_halted		(tlu_halted		[3:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_tlu_pmen(lsu_tlu_pmen),
  .tcu_ss_mode(tcu_ss_mode),
  .tcu_do_mode(tcu_do_mode),
  .tcu_ss_request(tcu_ss_request),
  .lsu_lddf_align_b(lsu_lddf_align_b),
  .lsu_stdf_align_b(lsu_stdf_align_b),
  .lsu_illegal_inst_b(lsu_illegal_inst_b),
  .lsu_daccess_prot_b(lsu_daccess_prot_b),
  .lsu_priv_action_b(lsu_priv_action_b),
  .lsu_va_watchpoint_b(lsu_va_watchpoint_b),
  .lsu_pa_watchpoint_b(lsu_pa_watchpoint_b),
  .lsu_align_b(lsu_align_b),
  .lsu_tlb_miss_b_(lsu_tlb_miss_b_),
  .lsu_dae_invalid_asi_b(lsu_dae_invalid_asi_b),
  .lsu_dae_nc_page_b(lsu_dae_nc_page_b),
  .lsu_dae_nfo_page_b(lsu_dae_nfo_page_b),
  .lsu_dae_priv_viol_b(lsu_dae_priv_viol_b),
  .lsu_dae_so_page(lsu_dae_so_page),
  .lsu_priv_action_g(lsu_priv_action_g),
  .lsu_tid_g(lsu_tid_g[2:0]),
  .lsu_tlb_bypass_b(lsu_tlb_bypass_b),
  .lsu_tlb_real_b(lsu_tlb_real_b),
  .lsu_sync_inst_b(lsu_sync_inst_b),
  .lsu_tlu_twocycle_m(lsu_tlu_twocycle_m),
  .lsu_dcl2u_err_g(lsu_dcl2u_err_g),
  .lsu_dcl2nd_err_g(lsu_dcl2nd_err_g),
  .lsu_dcerr_tid_g(lsu_dcerr_tid_g[2:0]),
  .lsu_sbdlc_err_g(lsu_sbdlc_err_g),
  .lsu_sbdlu_err_g(lsu_sbdlu_err_g),
  .lsu_sbapp_err_g(lsu_sbapp_err_g),
  .lsu_sbdiou_err_g(lsu_sbdiou_err_g),
  .lsu_stberr_tid_g(lsu_stberr_tid_g[2:0]),
  .lsu_dttp_err_b(lsu_dttp_err_b),
  .lsu_dtdp_err_b(lsu_dtdp_err_b),
  .lsu_dtmh_err_b(lsu_dtmh_err_b),
  .lsu_perfmon_trap_b(lsu_perfmon_trap_b),
  .lsu_perfmon_trap_g(lsu_perfmon_trap_g),
  .fgu_predict_fx2(fgu_predict_fx2),
  .fgu_pdist_beat2_fx1(fgu_pdist_beat2_fx1),
  .fgu_cecc_fx2(fgu_cecc_fx2),
  .fgu_uecc_fx2(fgu_uecc_fx2),
  .fgu_fpx_ieee_trap_fw(fgu_fpx_ieee_trap_fw),
  .fgu_fpd_ieee_trap_fw(fgu_fpd_ieee_trap_fw),
  .fgu_fpx_unfin_fw(fgu_fpx_unfin_fw),
  .fgu_fpd_unfin_fw(fgu_fpd_unfin_fw),
  .fgu_fpd_idiv0_trap_fw(fgu_fpd_idiv0_trap_fw),
  .fgu_fpx_trap_tid_fw(fgu_fpx_trap_tid_fw[2:0]),
  .fgu_fpd_trap_tid_fw(fgu_fpd_trap_tid_fw[2:0]),
  .asi_ece_exc(asi_ece_exc),
  .asi_eue_exc(asi_eue_exc),
  .asi_ecc_tid(asi_ecc_tid[2:0]),
  .asi_decr(asi_decr[63:46]),
  .mmu_asi_cecc(mmu_asi_cecc),
  .mmu_asi_uecc(mmu_asi_uecc),
  .mmu_asi_tid(mmu_asi_tid[2:0]),
  .mmu_dae_req(mmu_dae_req),
  .mmu_dae_tid(mmu_dae_tid[2:0]),
  .spu_tlu_ma_int_req(spu_tlu_ma_int_req[4:0]),
  .spu_tlu_cwq_int_req(spu_tlu_cwq_int_req[3:0])
);

tlu_fls_ctl fls1 ( 
	.wmr_scan_in(fls1_wmr_scanin),
	.wmr_scan_out(fls1_wmr_scanout),
	.scan_in(fls1_scanin),
	.scan_out(fls1_scanout),
	.l2clk			(l2clk				),
	.thread_group		(1'b1				),
	.trl_shscanid		({trl1_shscanid_2	       ,
				  trl1_shscanid		[1:0]}),
	.tcu_core_running	(tcu_core_running	[7:4]	),
	.cxi_xir		(cxi_xir		[7:4]	),
	.cxi_ivt		(cxi_ivt		[7:4]	),
	.dec_raw_pick_p		(dec_raw_pick_p		[7:5]	),
	.dec_tid_m		(dec_tid1_m		[1:0]	),
	.dec_inst_valid_m	(dec_inst_valid_m	[1   ]	),
	.dec_lsu_inst_m		(dec_lsu_inst_m		[1   ]	),
	.dec_fgu_inst_m		(dec_fgu_inst_m		[1   ]	),
	.dec_illegal_inst_m	(dec_illegal_inst_m	[1   ]	),
	.dec_exc_m		(dec_exc1_m		[4:0]	),
	.dec_done_inst_m	(dec_done_inst_m	[1   ]	),
	.dec_retry_inst_m	(dec_retry_inst_m	[1   ]	),
	.dec_sir_inst_m		(dec_sir_inst_m		[1   ]	),
	.dec_hpriv_exc_m	(dec_hpriv_exc_m	[1   ]	),
	.dec_priv_exc_m		(dec_priv_exc_m		[1   ]	),
	.dec_fpdisable_exc_m	(dec_fpdisable_exc_m	[1   ]	),
	.dec_br_taken_m		(dec_br_taken_m		[1   ]	),
	.dec_annul_ds_m		(dec_annul_ds_m		[1   ]	),
	.dec_ds_m		(dec_ds_m		[1   ]	),
	.dec_icache_perr_m	(dec_icache_perr_m	[1   ]	),
	.dec_cti_inst_m		(dec_cti_inst_m		[1   ]	),
	.dec_flush_b		(dec_flush_b		[1   ]	),
	.exu_ibp_m		(exu_ibp_m		[1   ]	),
	.exu_tcc_m		(exu_tcc_m		[1   ]	),
	.exu_tof_m		(exu_tof_m		[1   ]	),
	.exu_cecc_m		(exu_cecc_m		[1   ]	),
	.exu_uecc_m		(exu_uecc_m		[1   ]	),
	.exu_oor_va_m		(exu_oor_va_m		[1   ]	),
	.exu_misalign_m		(exu_misalign_m		[1   ]	),
	.exu_spill_b		(exu_spill_b		[1   ]	),
	.exu_fill_m		(exu_fill_m		[1   ]	),
	.exu_normal_b		(exu_normal_b		[1   ]	),
	.exu_cleanwin_b		(exu_cleanwin_b		[1   ]	),
	.exu_wstate_b		(exu1_wstate_b		[2:0]	),
	.exu_trap_number_b	(exu1_trap_number_b	[7:0]	),
	.exu_cwp0		(exu1_cwp0		[2:0]	),
	.exu_cwp1		(exu1_cwp1		[2:0]	),
	.exu_cwp2		(exu1_cwp2		[2:0]	),
	.exu_cwp3		(exu1_cwp3		[2:0]	),
	.lsu_trap_flush		(lsu_trap_flush		[7:4]	),
	.lsu_spec_enable	(asi_spec_enable	[7:4]	),
	.lsu_block_store_b	(lsu_block_store_b	[7:4]	),
	.lsu_immu_enable	(asi_immu_enable	[7:4]	),
	.asi_irl_cleared	(asi_irl_cleared	[7:4]	),
	.asi_halt		(asi_halt		[7:4]	),
	.asi_clear_spu_trap_req	(asi_clear_spu_trap_req	[7:4]	),
	.tel_tsacu_exc		(tel_tsacu_exc		[7:4]	),
	.mmu_hw_tw_enable	(mmu_hw_tw_enable	[7:4]	),
	.mmu_i_unauth_access	(mmu_i_unauth_access	[7:4]	),
	.mmu_i_tsb_miss		(mmu_i_tsb_miss		[7:4]	),
	.mmu_d_tsb_miss		(mmu_d_tsb_miss		[7:4]	),
	.mmu_i_tte_outofrange	(mmu_i_tte_outofrange	[7:4]	),
	.mmu_d_tte_outofrange	(mmu_d_tte_outofrange	[7:4]	),
	.mmu_i_eccerr		(mmu_i_eccerr		[7:4]	),
	.mmu_d_eccerr		(mmu_d_eccerr		[7:4]	),
	.mmu_thr0_err_type_b1   (mmu_thr4_err_type	[1   ]	),
	.mmu_thr1_err_type_b1   (mmu_thr5_err_type	[1   ]	),
	.mmu_thr2_err_type_b1   (mmu_thr6_err_type	[1   ]	),
	.mmu_thr3_err_type_b1   (mmu_thr7_err_type	[1   ]	),
	.pmu_tlu_trap_m		(pmu_tlu_trap_m		[7:4]	),
	.pmu_tlu_debug_event	(pmu_tlu_debug_event	[7:4]	),
	.flsx_flush_lsu_b	(fls0_flush_lsu_b		),
	.flsx_flush_fgu_b	(fls0_flush_fgu_b		),
	.pct_iaw_exc_e		(pct1_iaw_exc_e		[1:0]	),
	.pct_npc_0_w		(pct_npc_4_w		[3:2]	),
	.pct_npc_1_w		(pct_npc_5_w		[3:2]	),
	.pct_npc_2_w		(pct_npc_6_w		[3:2]	),
	.pct_npc_3_w		(pct_npc_7_w		[3:2]	),
	.pct_pc_oor_va_e	(pct_pc_oor_va_e	[1   ]	),
	.trl_tl_eq_0		(trl_tl_eq_0		[7:4]	),
	.trl_pil_mask_15	(trl_pil_mask_15	[7:4]	),
	.trl_iln_exc		(trl_iln_exc		[7:4]	),
	.trl_hstick_match	(trl_hstick_match	[7:4]	),
	.trl_unhalt_		(trl_unhalt_		[7:4]	),
	.trl_tlz_exc		(trl_tlz_exc		[7:4]	),
	.trl_nns_exc		(trl_nns_exc		[7:4]	),
	.trl_ssc_exc		(trl_ssc_exc		[7:4]	),
	.trl_invalidate_pc	(trl_invalidate_pc	[7:4]	),
	.trl_invalidate_npc	(trl_invalidate_npc	[7:4]	),
	.trl_pc_sel_trap_pc	(trl_pc_sel_trap_pc	[7:4]	),
	.trl_fls_npc_en		(trl_fls_npc_en		[7:4]	),
	.trl_trap_taken		(trl_trap_taken		[7:4]	),
	.trl_take_sma		(trl1_take_sma			),
	.trl_take_cwq		(trl1_take_cwq			),
	.trl_take_xir		(trl1_take_xir			),
	.trl_take_ftt		(trl1_take_ftt			),
	.trl_core_running_status(trl_core_running_status[7:4]	),
	.trl_check_rqr		(trl1_tsa_wr_addr	[0   ]	),
	.tlu_ceter_de		(tlu_ceter_de		[7:4]	),
	.tlu_ceter_dhcce	(tlu_ceter_dhcce	[7:4]	),
	.tsd_hpstate_ibe	(tsd_hpstate_ibe	[7:4]	),
	.tsd_hpstate_hpriv	(tsd_hpstate_hpriv	[7:4]	),
	.tsd_hpstate_red	(tsd_hpstate_red	[7:4]	),
	.tsd_pstate_tct		(tsd_pstate_tct		[7:4]	),
	.tsd_pstate_priv	(tsd_pstate_priv	[7:4]	),
	.tsd_pstate_ie		(tsd_pstate_ie		[7:4]	),
	.tsd_pstate_am		(tsd_pstate_am		[7:4]	),
	.tsd_itlb_bypass	(tsd_itlb_bypass	[7:4]	),
	.tsd_mrqr_exc_		(tsd1_mrqr_exc_			),
	.tsd_dqr_exc_		(tsd1_dqr_exc_			),
	.asi_check_qr_exc	(asi_check_qr_exc	[7:4]	),
	.dfd_fls_desr_f		(dfd_fls_desr_f		[7:4]	),
	.dfd_fls_desr_s		(dfd_fls_desr_s		[7:4]	),
	.ras_precise_error	(ras_precise_error	[7:4]	),
	.ras_disrupting_error	(ras_disrupting_error	[7:4]	),
	.ras_deferred_error	(ras_deferred_error	[7:4]	),
	.fls_spc_hardstop_request(fls1_spc_hardstop_request	),
	.fls_spc_softstop_request(fls1_spc_softstop_request	),
	.fls_spc_trigger_pulse  (fls1_spc_trigger_pulse 	),
	.tlu_dbg_instr_cmt_grp 	(tlu_dbg_instr_cmt_grp1 [1:0]	),
	.tlu_flush_ifu		(tlu_flush_ifu		[7:4]	),
	.tlu_flush_exu_b	(tlu_flush_exu_b	[1   ]	),
	.tlu_flush_lsu_b	(tlu_flush_lsu_b		),
	.tlu_flush_fgu_b	(tlu_flush_fgu_b		),
	.tlu_flush_pmu_b	(tlu_flush_pmu_b	[1   ]	),
	.tlu_flush_pmu_w	(tlu_flush_pmu_w	[1   ]	),
	.tlu_load_i_tag_access_p(tlu_load_i_tag_access_p[7:4]	),
	.tlu_load_i_tag_access_n(tlu_load_i_tag_access_n[7:4]	),
	.tlu_load_d_tag_access	(tlu_load_d_tag_access	[7:4]	),
	.tlu_load_d_tag_access_r(tlu_load_d_tag_access_r[7:4]	),
	.fls_flush_lsu_b	(fls1_flush_lsu_b_unused	),
	.fls_flush_fgu_b	(fls1_flush_fgu_b_unused	),
	.fls_tid_d		(fls1_tid_d		[1:0]	),
	.fls_tid_dec_b		(fls1_tid_dec_b		[3:0]	),
	.fls_tid_dec_w		(fls1_tid_dec_w		[3:0]	),
	.fls_pc_sel_npc		(fls_pc_sel_npc		[7:4]	),
	.fls_pc_sel_npc_plus_4	(fls_pc_sel_npc_plus_4	[7:4]	),
	.fls_npc_sel_npc_plus_4	(fls_npc_sel_npc_plus_4	[7:4]	),
	.fls_npc_sel_npc_plus_8	(fls_npc_sel_npc_plus_8	[7:4]	),
	.fls_npc_sel_target	(fls_npc_sel_target	[7:4]	),
	.fls_npc_b_sel_npc	(fls1_npc_b_sel_npc		),
	.fls_pc_is_npc		(fls1_pc_is_npc			),
	.fls_pstate_am_d_	(fls_pstate_am_d_	[1   ]	),
	.fls_pstate_am_b_	(fls_pstate_am_b_	[1   ]	),
	.fls_pstate_am_w_	(fls_pstate_am_w_	[1   ]	),
	.fls_lsu_inst_w		(fls1_lsu_inst_w		),
	.fls_dfd_lsu_inst_b	(fls1_dfd_lsu_inst_b		),
	.fls_wstate0		(fls_wstate4		[2:0]	),
	.fls_wstate1		(fls_wstate5		[2:0]	),
	.fls_wstate2		(fls_wstate6		[2:0]	),
	.fls_wstate3		(fls_wstate7 		[2:0]	),
	.fls_tcc_number_0	(fls_tcc_number_4	[7:0]	),
	.fls_tcc_number_1	(fls_tcc_number_5	[7:0]	),
	.fls_tcc_number_2	(fls_tcc_number_6	[7:0]	),
	.fls_tcc_number_3	(fls_tcc_number_7	[7:0]	),
	.fls_tid_dec_w_in	(fls_tid_dec_w_in	[7:4]	),
	.fls_por_request	(fls_por_request	[7:4]	),
	.fls_xir_request	(fls_xir_request	[7:4]	),
	.fls_ivt_request	(fls_ivt_request	[7:4]	),
	.fls_sir_request	(fls_sir_request	[7:4]	),
	.fls_itm_request	(fls_itm_request	[7:4]	),
	.fls_iln_request	(fls_iln_request	[7:4]	),
	.fls_hst_request	(fls_hst_request	[7:4]	),
	.fls_tlz_request	(fls_tlz_request	[7:4]	),
	.fls_sma_request	(fls_sma_request	[7:4]	),
	.fls_cwq_request	(fls_cwq_request	[7:4]	),
	.fls_ade_request	(fls_ade_request	[7:4]	),
	.fls_iae_request	(fls_iae_request	[7:4]	),
	.fls_ipe_request	(fls_ipe_request	[7:4]	),
	.fls_ipv_request	(fls_ipv_request	[1   ]	),
	.fls_inp_request	(fls_inp_request	[1   ]	),
	.fls_iar_request	(fls_iar_request	[1   ]	),
	.fls_irr_request	(fls_irr_request	[1   ]	),
	.fls_mar_request	(fls_mar_request	[1   ]	),
	.fls_mrr_request	(fls_mrr_request	[1   ]	),
	.fls_pro_request	(fls_pro_request	[1   ]	),
	.fls_ill_request	(fls_ill_request	[1   ]	),
	.fls_don_request	(fls_don_request	[1   ]	),
	.fls_ret_request	(fls_ret_request	[1   ]	),
	.fls_fpd_request	(fls_fpd_request	[1   ]	),
	.fls_snn_request	(fls_snn_request	[1   ]	),
	.fls_sno_request	(fls_sno_request	[1   ]	),
	.fls_fnn_request	(fls_fnn_request	[1   ]	),
	.fls_fno_request	(fls_fno_request	[1   ]	),
	.fls_clw_request	(fls_clw_request	[1   ]	),
	.fls_dtm_request	(fls_dtm_request	[7:4]	),
	.fls_ldf_request	(fls_ldf_request	[1   ]	),
	.fls_stf_request	(fls_stf_request	[1   ]	),
	.fls_dap_request	(fls_dap_request	[1   ]	),
	.fls_vaw_request	(fls_vaw_request	[1   ]	),
	.fls_iaw_request	(fls_iaw_request	[1   ]	),
	.fls_paw_request	(fls_paw_request	[1   ]	),
	.fls_maa_request	(fls_maa_request	[1   ]	),
	.fls_fpe_request	(fls_fpe_request	[1   ]	),
	.fls_fei_request	(fls_fei_request	[7:4]	),
	.fls_fof_request	(fls_fof_request	[7:4]	),
	.fls_pra_request	(fls_pra_request	[7:4]	),
	.fls_dia_request	(fls_dia_request	[1   ]	),
	.fls_ups_request	(fls_ups_request	[7:4]	),
	.fls_dpv_request	(fls_dpv_request	[1   ]	),
	.fls_dnc_request	(fls_dnc_request	[1   ]	),
	.fls_dnf_request	(fls_dnf_request	[1   ]	),
	.fls_dso_request	(fls_dso_request	[1   ]	),
	.fls_tof_request	(fls_tof_request	[1   ]	),
	.fls_dbz_request	(fls_dbz_request	[7:4]	),
	.fls_tcc_request	(fls_tcc_request	[1   ]	),
	.fls_dae_request	(fls_dae_request	[7:4]	),
	.fls_lsr_request	(fls_lsr_request	[7:4]	),
	.fls_irt_request	(fls_irt_request	[1   ]	),
	.fls_drt_request	(fls_drt_request	[1   ]	),
	.fls_pmu_request	(fls_pmu_request	[7:4]	),
	.fls_mqr_request	(fls_mqr_request	[7:4]	),
	.fls_dqr_request	(fls_dqr_request	[7:4]	),
	.fls_rqr_request	(fls_rqr_request	[7:4]	),
	.fls_idl_request	(fls_idl_request	[7:4]	),
	.fls_res_request	(fls_res_request	[7:4]	),
	.fls_ssr_request	(fls_ssr_request	[7:4]	),
	.fls_ssc_request	(fls_ssc_request	[7:4]	),
	.fls_nns_request	(fls_nns_request	[7:4]	),
	.fls_ime_request	(fls_ime_request	[7:4]	),
	.fls_dme_request	(fls_dme_request	[7:4]	),
	.fls_eer_request	(fls_eer_request	[7:4]	),
	.fls_icp_request	(fls_icp_request	[1   ]	),
	.fls_ftt_request	(fls_ftt_request	[7:4]	),
	.fls_ibp_request	(fls_ibp_request	[1   ]	),
	.fls_tct_request	(fls_tct_request	[1   ]	),
	.fls_ref_request	(fls_ref_request	[1   ]	),
	.fls_ipe_dme_request	(fls_ipe_dme_request	[1   ]	),
	.fls_pc_valid		(fls_pc_valid		[7:4]	),
	.fls_load_dsfar		(fls_load_dsfar		[7:4]	),
	.fls_irf_cecc_b		(fls_irf_cecc_b		[1   ]	),
	.fls_irf_uecc_b		(fls_irf_uecc_b		[1   ]	),
	.fls_kill_irf_ecc_w	(fls_kill_irf_ecc_w	[1   ]	),
	.fls_cwp0		(fls1_cwp0		[2:0]	),
	.fls_cwp1		(fls1_cwp1		[2:0]	),
	.fls_cwp2		(fls1_cwp2		[2:0]	),
	.fls_cwp3		(fls1_cwp3		[2:0]	),
	.fls_core_running	(fls_core_running	[7:4]	),
	.fls_ss_request		(fls_ss_request_unused		),
	.fls_pct_pc_en		(fls_pct_pc_en		[7:4]	),
	.fls_pct_npc_en		(fls_pct_npc_en		[7:4]	),
	.fls_trl_l1en		(fls_trl_l1en		[7:4]	),
	.fls_npc_if_cnt_eq_1_d	(fls1_npc_if_cnt_eq_1_d	[4:2]	),
	.fls_npc_if_cnt_eq_2_d	(fls1_npc_if_cnt_eq_2_d	[4:2]	),
	.fls_npc_if_cnt_eq_3_d	(fls1_npc_if_cnt_eq_3_d	[4:2]	),
	.fls_flush		(fls_flush		[7:4]	),
	.fls_disrupting_flush_w	(fls_disrupting_flush_w	[1   ]	),
	.fls_f_cecc_w		(fls_f_cecc_w_unused		),
	.fls_f_uecc_w		(fls_f_uecc_w_unused		),
	.fls_ss_update_pc_w	(fls_ss_update_pc_w	[1   ]	),
	.tlu_iht_request	(tlu_iht_request	[7:4]	),
	.tlu_dht_request	(tlu_dht_request	[7:4]	),
	.tlu_itlb_bypass_e	(tlu_itlb_bypass_e	[1   ]	),
	.tlu_tag_access_tid_b	(tlu_tag_access_tid_1_b	[1:0]	),
	.tlu_i_tag_access_b	(tlu_i_tag_access_1_b		),
	.tlu_d_tag_access_b	(tlu_d_tag_access_1_b		),
	.tlu_retry_state	(tlu_retry_state	[7:4]	),
	.tlu_halted		(tlu_halted		[7:4]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_tlu_pmen(lsu_tlu_pmen),
  .tcu_ss_mode(tcu_ss_mode),
  .tcu_do_mode(tcu_do_mode),
  .tcu_ss_request(tcu_ss_request),
  .lsu_lddf_align_b(lsu_lddf_align_b),
  .lsu_stdf_align_b(lsu_stdf_align_b),
  .lsu_illegal_inst_b(lsu_illegal_inst_b),
  .lsu_daccess_prot_b(lsu_daccess_prot_b),
  .lsu_priv_action_b(lsu_priv_action_b),
  .lsu_va_watchpoint_b(lsu_va_watchpoint_b),
  .lsu_pa_watchpoint_b(lsu_pa_watchpoint_b),
  .lsu_align_b(lsu_align_b),
  .lsu_tlb_miss_b_(lsu_tlb_miss_b_),
  .lsu_dae_invalid_asi_b(lsu_dae_invalid_asi_b),
  .lsu_dae_nc_page_b(lsu_dae_nc_page_b),
  .lsu_dae_nfo_page_b(lsu_dae_nfo_page_b),
  .lsu_dae_priv_viol_b(lsu_dae_priv_viol_b),
  .lsu_dae_so_page(lsu_dae_so_page),
  .lsu_priv_action_g(lsu_priv_action_g),
  .lsu_tid_g(lsu_tid_g[2:0]),
  .lsu_tlb_bypass_b(lsu_tlb_bypass_b),
  .lsu_tlb_real_b(lsu_tlb_real_b),
  .lsu_sync_inst_b(lsu_sync_inst_b),
  .lsu_tlu_twocycle_m(lsu_tlu_twocycle_m),
  .lsu_dcl2u_err_g(lsu_dcl2u_err_g),
  .lsu_dcl2nd_err_g(lsu_dcl2nd_err_g),
  .lsu_dcerr_tid_g(lsu_dcerr_tid_g[2:0]),
  .lsu_sbdlc_err_g(lsu_sbdlc_err_g),
  .lsu_sbdlu_err_g(lsu_sbdlu_err_g),
  .lsu_sbapp_err_g(lsu_sbapp_err_g),
  .lsu_sbdiou_err_g(lsu_sbdiou_err_g),
  .lsu_stberr_tid_g(lsu_stberr_tid_g[2:0]),
  .lsu_dttp_err_b(lsu_dttp_err_b),
  .lsu_dtdp_err_b(lsu_dtdp_err_b),
  .lsu_dtmh_err_b(lsu_dtmh_err_b),
  .lsu_perfmon_trap_b(lsu_perfmon_trap_b),
  .lsu_perfmon_trap_g(lsu_perfmon_trap_g),
  .fgu_predict_fx2(fgu_predict_fx2),
  .fgu_pdist_beat2_fx1(fgu_pdist_beat2_fx1),
  .fgu_cecc_fx2(fgu_cecc_fx2),
  .fgu_uecc_fx2(fgu_uecc_fx2),
  .fgu_fpx_ieee_trap_fw(fgu_fpx_ieee_trap_fw),
  .fgu_fpd_ieee_trap_fw(fgu_fpd_ieee_trap_fw),
  .fgu_fpx_unfin_fw(fgu_fpx_unfin_fw),
  .fgu_fpd_unfin_fw(fgu_fpd_unfin_fw),
  .fgu_fpd_idiv0_trap_fw(fgu_fpd_idiv0_trap_fw),
  .fgu_fpx_trap_tid_fw(fgu_fpx_trap_tid_fw[2:0]),
  .fgu_fpd_trap_tid_fw(fgu_fpd_trap_tid_fw[2:0]),
  .asi_ece_exc(asi_ece_exc),
  .asi_eue_exc(asi_eue_exc),
  .asi_ecc_tid(asi_ecc_tid[2:0]),
  .asi_decr(asi_decr[63:46]),
  .mmu_asi_cecc(mmu_asi_cecc),
  .mmu_asi_uecc(mmu_asi_uecc),
  .mmu_asi_tid(mmu_asi_tid[2:0]),
  .mmu_dae_req(mmu_dae_req),
  .mmu_dae_tid(mmu_dae_tid[2:0]),
  .spu_tlu_ma_int_req(spu_tlu_ma_int_req[4:0]),
  .spu_tlu_cwq_int_req(spu_tlu_cwq_int_req[3:0])
);


////////////////////////////////////////////////////////////////////////////////
// PC and NPC tracking:  one for each thread group
tlu_pct_dp pct0 ( 
	.wmr_scan_in(pct0_wmr_scanin),
	.wmr_scan_out(pct0_wmr_scanout),
	.scan_in(pct0_scanin),
	.scan_out(pct0_scanout),
	.l2clk			(l2clk				),
	.dec_flush_b		(dec_flush_b		[0   ]	),
	.dec_inst_cnt		(dec_inst0_cnt		[1:0]	),
	.dec_raw_pick_p		(dec_raw_pick_p		[3:0]	),
	.exu_address_m		(tic_exu_address0_m	[47:2]	),
	.exu_oor_va_m		(exu_oor_va_m		[0   ]	),
	.asi_rd_pc		(asi_rd_pc		[3:0]	),
	.asi_wr_iaw		(asi_wr_iaw		[0   ]	),
	.asi_wr_data		(asi_wr_data_0		[47:0]	),
	.fls_tid_dec_b		(fls0_tid_dec_b		[3:0]	),
	.fls_tid_dec_w		(fls0_tid_dec_w		[3:0]	),
	.fls_pc_sel_npc		(fls_pc_sel_npc		[3:0]	),
	.fls_pc_sel_npc_plus_4	(fls_pc_sel_npc_plus_4	[3:0]	),
	.fls_npc_sel_npc_plus_4	(fls_npc_sel_npc_plus_4	[3:0]	),
	.fls_npc_sel_npc_plus_8	(fls_npc_sel_npc_plus_8	[3:0]	),
	.fls_npc_sel_target	(fls_npc_sel_target	[3:0]	),
	.fls_npc_b_sel_npc	(fls0_npc_b_sel_npc		),
	.fls_pc_is_npc		(fls0_pc_is_npc			),
	.fls_pstate_am_d_	(fls_pstate_am_d_	[0   ]	),
	.fls_pstate_am_b_	(fls_pstate_am_b_	[0   ]	),
	.fls_pstate_am_w_	(fls_pstate_am_w_	[0   ]	),
	.fls_npc_if_cnt_eq_1_d	(fls0_npc_if_cnt_eq_1_d	[4:2]	),
	.fls_npc_if_cnt_eq_2_d	(fls0_npc_if_cnt_eq_2_d	[4:2]	),
	.fls_npc_if_cnt_eq_3_d	(fls0_npc_if_cnt_eq_3_d	[4:2]	),
	.fls_pct_pc_en		(fls_pct_pc_en		[3:0]	),
	.fls_pct_npc_en		(fls_pct_npc_en		[3:0]	),
	.trl_pc_sel_trap_pc	(trl_pc_sel_trap_pc	[3:0]	),
	.trl_npc_sel_trap_npc	(trl_npc_sel_trap_npc	[3:0]	),
	.trl_npc_sel_tnpc	(trl_npc_sel_tnpc	[3:0]	),
	.trl_trap_type		(trl0_trap_type		[8:0]	),
	.trl_pc_thread_sel	(trl0_pc_thread_sel	[3:0]	),
	.trl_pc_pstate_am_	(trl_pc_pstate_am_	[0   ]	),
	.trl_pc_sel_pc		(trl_pc_sel_pc		[0   ]	),
	.trl_pc_sel_npc		(trl_pc_sel_npc		[0   ]	),
	.trl_pc_sel_trap	(trl_pc_sel_trap	[0   ]	),
	.trl_pc_sel_reset	(trl_pc_sel_reset	[0   ]	),
	.trl_pc_done		(trl_pc_done		[0   ]	),
	.trl_pc_retry		(trl_pc_retry		[0   ]	),
	.trl_pc_tte		(trl_pc_tte		[0   ]	),
	.trl_pct_trap_pc_en	(trl_pct_trap_pc_en	[0   ]	),
	.trl_pct_tnpc_en	(trl_pct_tnpc_en	[0   ]	),
	.tsd_tba		(tsd0_tba		[47:14]	),
	.tsd_tpc		(tsd0_tpc		[47:2]	),
	.tsd_tpc_oor_va		(tsd_tpc_oor_va		[0   ]	),
	.tsd_tnpc		(tsd0_tnpc		[47:2]	),
	.tsd_tnpc_oor_va	(tsd_tnpc_oor_va	[0   ]	),
	.tsd_tnpc_nonseq	(tsd_tnpc_nonseq	[0   ]	),
	.tsd_asi_data_		(tsd0_asi_data_		[47:2]	),
	.tsd_pstate_am		(tsd_pstate_am		[3:0]	),
	.pct_npc_0_w		(pct_npc_0_w		[3:2]	),
	.pct_npc_1_w		(pct_npc_1_w		[3:2]	),
	.pct_npc_2_w		(pct_npc_2_w		[3:2]	),
	.pct_npc_3_w		(pct_npc_3_w		[3:2]	),
	.pct_asi_data		(pct0_asi_data		[48:2]	),
	.pct_tsa_pc		(pct0_tsa_pc		[47:2]	),
	.pct_tsa_pc_oor_va	(pct_tsa_pc_oor_va	[0   ]	),
	.pct_tsa_npc		(pct0_tsa_npc		[47:2]	),
	.pct_tsa_npc_oor_va	(pct_tsa_npc_oor_va	[0   ]	),
	.pct_tsa_npc_nonseq	(pct_tsa_npc_nonseq	[0   ]	),
	.pct_npc_is_nonseq	(pct_npc_is_nonseq	[3:0]	),
	.pct_pc_oor_va_e	(pct_pc_oor_va_e	[0   ]	),
	.pct_iaw_exc_e		(pct0_iaw_exc_e		[1:0]	),
	.pct_shadow_pc_d	(pct0_shadow_pc_d	[47:2]	),
	.pct_npc_w 		(pct0_npc_w		[47:2]	),
	.pct_target_b 		(pct0_target_b		[47:2]	),
	.pct_trl_wr_data	(pct0_trl_wr_data	[16:0]	),
	.tsd_pc_w 		(tsd_pc_0_w		[10:5]	),
	.tlu_pc_d		(tlu_pc_0_prebuf_d	[47:2]	),
	.tlu_pc_w 		(tlu_pc_0_w		[47:13]	),
	.tlu_trap_pc		(tlu_trap_pc_0		[47:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en_wmr(tcu_scan_en_wmr),
  .spc_aclk_wmr(spc_aclk_wmr),
  .tcu_wmr_vec_mask(tcu_wmr_vec_mask),
  .mmu_itte_tag_data(mmu_itte_tag_data[47:0]),
  .asi_rd_iaw(asi_rd_iaw)
);

tlu_pct_dp pct1 ( 
	.wmr_scan_in(pct1_wmr_scanin),
	.wmr_scan_out(pct1_wmr_scanout),
	.scan_in(pct1_scanin),
	.scan_out(pct1_scanout),
	.l2clk			(l2clk				),
	.dec_flush_b		(dec_flush_b		[1   ]	),
	.dec_inst_cnt		(dec_inst1_cnt		[1:0]	),
	.dec_raw_pick_p		(dec_raw_pick_p		[7:4]	),
	.exu_address_m		(tic_exu_address1_m	[47:2]	),
	.exu_oor_va_m		(exu_oor_va_m		[1   ]	),
	.asi_rd_pc		(asi_rd_pc		[7:4]	),
	.asi_wr_iaw		(asi_wr_iaw		[1   ]	),
	.asi_wr_data		(asi_wr_data_1		[47:0]	),
	.fls_tid_dec_b		(fls1_tid_dec_b		[3:0]	),
	.fls_tid_dec_w		(fls1_tid_dec_w		[3:0]	),
	.fls_pc_sel_npc		(fls_pc_sel_npc		[7:4]	),
	.fls_pc_sel_npc_plus_4	(fls_pc_sel_npc_plus_4	[7:4]	),
	.fls_npc_sel_npc_plus_4	(fls_npc_sel_npc_plus_4	[7:4]	),
	.fls_npc_sel_npc_plus_8	(fls_npc_sel_npc_plus_8	[7:4]	),
	.fls_npc_sel_target	(fls_npc_sel_target	[7:4]	),
	.fls_npc_b_sel_npc	(fls1_npc_b_sel_npc		),
	.fls_pc_is_npc		(fls1_pc_is_npc			),
	.fls_pstate_am_d_	(fls_pstate_am_d_	[1   ]	),
	.fls_pstate_am_b_	(fls_pstate_am_b_	[1   ]	),
	.fls_pstate_am_w_	(fls_pstate_am_w_	[1   ]	),
	.fls_npc_if_cnt_eq_1_d	(fls1_npc_if_cnt_eq_1_d	[4:2]	),
	.fls_npc_if_cnt_eq_2_d	(fls1_npc_if_cnt_eq_2_d	[4:2]	),
	.fls_npc_if_cnt_eq_3_d	(fls1_npc_if_cnt_eq_3_d	[4:2]	),
	.fls_pct_pc_en		(fls_pct_pc_en		[7:4]	),
	.fls_pct_npc_en		(fls_pct_npc_en		[7:4]	),
	.trl_pc_sel_trap_pc	(trl_pc_sel_trap_pc	[7:4]	),
	.trl_npc_sel_trap_npc	(trl_npc_sel_trap_npc	[7:4]	),
	.trl_npc_sel_tnpc	(trl_npc_sel_tnpc	[7:4]	),
	.trl_trap_type		(trl1_trap_type		[8:0]	),
	.trl_pc_thread_sel	(trl1_pc_thread_sel	[3:0]	),
	.trl_pc_pstate_am_	(trl_pc_pstate_am_	[1   ]	),
	.trl_pc_sel_pc		(trl_pc_sel_pc		[1   ]	),
	.trl_pc_sel_npc		(trl_pc_sel_npc		[1   ]	),
	.trl_pc_sel_trap	(trl_pc_sel_trap	[1   ]	),
	.trl_pc_sel_reset	(trl_pc_sel_reset	[1   ]	),
	.trl_pc_done		(trl_pc_done		[1   ]	),
	.trl_pc_retry		(trl_pc_retry		[1   ]	),
	.trl_pc_tte		(trl_pc_tte		[1   ]	),
	.trl_pct_trap_pc_en	(trl_pct_trap_pc_en	[1   ]	),
	.trl_pct_tnpc_en	(trl_pct_tnpc_en	[1   ]	),
	.tsd_tba		(tsd1_tba		[47:14]	),
	.tsd_tpc		(tsd1_tpc		[47:2]	),
	.tsd_tpc_oor_va		(tsd_tpc_oor_va		[1   ]	),
	.tsd_tnpc		(tsd1_tnpc		[47:2]	),
	.tsd_tnpc_oor_va	(tsd_tnpc_oor_va	[1   ]	),
	.tsd_tnpc_nonseq	(tsd_tnpc_nonseq	[1   ]	),
	.tsd_asi_data_		(tsd1_asi_data_		[47:2]	),
	.tsd_pstate_am		(tsd_pstate_am		[7:4]	),
	.pct_npc_0_w		(pct_npc_4_w		[3:2]	),
	.pct_npc_1_w		(pct_npc_5_w		[3:2]	),
	.pct_npc_2_w		(pct_npc_6_w		[3:2]	),
	.pct_npc_3_w		(pct_npc_7_w		[3:2]	),
	.pct_asi_data		(pct1_asi_data		[48:2]	),
	.pct_tsa_pc		(pct1_tsa_pc		[47:2]	),
	.pct_tsa_pc_oor_va	(pct_tsa_pc_oor_va	[1   ]	),
	.pct_tsa_npc		(pct1_tsa_npc		[47:2]	),
	.pct_tsa_npc_oor_va	(pct_tsa_npc_oor_va	[1   ]	),
	.pct_tsa_npc_nonseq	(pct_tsa_npc_nonseq	[1   ]	),
	.pct_npc_is_nonseq	(pct_npc_is_nonseq	[7:4]	),
	.pct_pc_oor_va_e	(pct_pc_oor_va_e	[1   ]	),
	.pct_iaw_exc_e		(pct1_iaw_exc_e		[1:0]	),
	.pct_shadow_pc_d	(pct1_shadow_pc_d	[47:2]	),
	.pct_npc_w 		(pct1_npc_w		[47:2]	),
	.pct_target_b 		(pct1_target_b		[47:2]	),
	.pct_trl_wr_data	(pct1_trl_wr_data	[16:0]	),
	.tsd_pc_w 		(tsd_pc_1_w		[10:5]	),
	.tlu_pc_d		(tlu_pc_1_d		[47:2]	),
	.tlu_pc_w		(tlu_pc_1_w		[47:13]	),
	.tlu_trap_pc		(tlu_trap_pc_1		[47:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en_wmr(tcu_scan_en_wmr),
  .spc_aclk_wmr(spc_aclk_wmr),
  .tcu_wmr_vec_mask(tcu_wmr_vec_mask),
  .mmu_itte_tag_data(mmu_itte_tag_data[47:0]),
  .asi_rd_iaw(asi_rd_iaw)
);

tlu_npc_dp npc(
  .pct0_npc_w(pct0_npc_w[47:2]),
  .pct1_npc_w(pct1_npc_w[47:2]),
  .fls1_lsu_inst_w(fls1_lsu_inst_w),
  .tlu_npc_w(tlu_npc_w[47:2]));


////////////////////////////////////////////////////////////////////////////////
// Crossbar Interface
tlu_cxi_ctl cxi (
	.scan_in(cxi_scanin),
	.scan_out(cxi_scanout),
	.l2clk			(l2clk				),
	.lsu_cpx_req		(l15_spc_cpkt		[17:14]	),
	.lsu_cpx_err		(l15_spc_cpkt		[11:10]	),
	.lsu_cpx_sre		(l15_spc_cpkt		[9   ]	),
	.lsu_cpx_err_thread_id	(l15_spc_cpkt		[8:6]	),
	.lsu_cpx_thread_id	(l15_spc_data1		[10:8]	),
	.lsu_cpx_valid		(l15_spc_valid			),
	.lsu_cpx_type		(l15_spc_data1		[15:14]	),
	.lsu_cpx_vector		(l15_spc_data1		[5:0]	),
	.lsu_cpx_prefetch	(l15_spc_cpkt		[0   ]	),
	.spc_ss_complete	(tlu_ss_complete		),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .fls_core_running(fls_core_running[7:0]),
  .fls_ss_request(fls_ss_request),
  .lsu_ext_interrupt(lsu_ext_interrupt),
  .lsu_ext_int_type(lsu_ext_int_type[1:0]),
  .lsu_ext_int_vec(lsu_ext_int_vec[5:0]),
  .lsu_ext_int_tid(lsu_ext_int_tid[2:0]),
  .trl_ss_complete(trl_ss_complete[7:0]),
  .asi_irl_cleared(asi_irl_cleared[7:0]),
  .cth_irl_cleared(cth_irl_cleared[63:0]),
  .tlu_cerer_l2c_socc(tlu_cerer_l2c_socc),
  .tlu_cerer_l2u_socu(tlu_cerer_l2u_socu),
  .tlu_cerer_l2nd(tlu_cerer_l2nd),
  .cxi_xir(cxi_xir[7:0]),
  .cxi_ivt(cxi_ivt[7:0]),
  .cxi_wr_int_dis(cxi_wr_int_dis[7:0]),
  .cxi_int_dis_vec(cxi_int_dis_vec[5:0]),
  .cxi_l2_soc_sre(cxi_l2_soc_sre),
  .cxi_l2_soc_err_type(cxi_l2_soc_err_type[1:0]),
  .cxi_l2_soc_tid(cxi_l2_soc_tid[2:0]),
  .cxi_l2_err(cxi_l2_err),
  .cxi_soc_err(cxi_soc_err)
);

assign l15_spc_cpkt_unused[13:12] = l15_spc_cpkt[13:12];
assign l15_spc_cpkt_unused[5:1] = l15_spc_cpkt[5:1];
assign l15_spc_data1_unused[13:11] = l15_spc_data1[13:11];
assign l15_spc_data1_unused[7:6] = l15_spc_data1[7:6];


////////////////////////////////////////////////////////////////////////////////
// Cross Thread Interrupts
tlu_cth_dp cth ( 
	.wmr_scan_in(cth_wmr_scanin),
	.wmr_scan_out(cth_wmr_scanout),
	.scan_in(cth_scanin),
	.scan_out(cth_scanout),
	.l2clk			(l2clk				),
	.asi_wr_data		(asi_wr_data_0		[63:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en_wmr(tcu_scan_en_wmr),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_rngf_cdbus(lsu_rngf_cdbus[64:56]),
  .cxi_wr_int_dis(cxi_wr_int_dis[7:0]),
  .cxi_int_dis_vec(cxi_int_dis_vec[5:0]),
  .asi_wr_int_rec(asi_wr_int_rec[7:0]),
  .asi_rd_inc_vec_2(asi_rd_inc_vec_2[7:0]),
  .asi_int_rec_mux_sel_in(asi_int_rec_mux_sel_in[2:0]),
  .asi_rd_int_rec(asi_rd_int_rec),
  .asi_rd_inc_vec(asi_rd_inc_vec),
  .asi_wr_any_int_rec(asi_wr_any_int_rec),
  .asi_rd_stage_1(asi_rd_stage_1),
  .dfd_asi_data(dfd_asi_data[47:0]),
  .dfd_asi_desr(dfd_asi_desr[18:0]),
  .cth_wr_data(cth_wr_data[61:0]),
  .cth_asi_data(cth_asi_data[63:0]),
  .cth_irl_cleared(cth_irl_cleared[63:0])
);


////////////////////////////////////////////////////////////////////////////////
// Trap Redirect Logic:  one for each thread group
tlu_trl_ctl trl0 ( 
	.wmr_scan_in(trl0_wmr_scanin),
	.wmr_scan_out(trl0_wmr_scanout),
	.scan_in(trl0_scanin),
	.scan_out(trl0_scanout),
	.l2clk			(l2clk				),
	.thread_group		(1'b0				),
	.ftu_ifu_quiesce	(ftu_ifu_quiesce	[3:0]	),
	.pku_quiesce		(pku_quiesce		[3:0]	),
	.exu_tlu_window_block	(exu_tlu_window_block	[0   ]	),
	.lsu_stb_empty		(lsu_stb_empty		[3:0]	),
	.mmu_write_itlb		(mmu_write_itlb		[3:0]	),
	.mmu_reload_done	(mmu_reload_done	[3:0]	),
	.mmu_i_unauth_access	(mmu_i_unauth_access	[3:0]	),
	.mmu_i_tsb_miss		(mmu_i_tsb_miss		[3:0]	),
	.mmu_d_tsb_miss		(mmu_d_tsb_miss		[3:0]	),
	.mmu_i_tte_outofrange	(mmu_i_tte_outofrange	[3:0]	),
	.mmu_d_tte_outofrange	(mmu_d_tte_outofrange	[3:0]	),
	.fls_wstate0		(fls_wstate0		[2:0]	),
	.fls_wstate1		(fls_wstate1		[2:0]	),
	.fls_wstate2		(fls_wstate2		[2:0]	),
	.fls_wstate3		(fls_wstate3		[2:0]	),
	.fls_tcc_number_0	(fls_tcc_number_0	[7:0]	),
	.fls_tcc_number_1	(fls_tcc_number_1	[7:0]	),
	.fls_tcc_number_2	(fls_tcc_number_2	[7:0]	),
	.fls_tcc_number_3	(fls_tcc_number_3	[7:0]	),
	.fls_tid_d		(fls0_tid_d		[1:0]	),
	.fls_tid_dec_w_in	(fls_tid_dec_w_in	[3:0]	),
	.fls_por_request	(fls_por_request	[3:0]	),
	.fls_xir_request	(fls_xir_request	[3:0]	),
	.fls_ivt_request	(fls_ivt_request	[3:0]	),
	.fls_sir_request	(fls_sir_request	[3:0]	),
	.fls_itm_request	(fls_itm_request	[3:0]	),
	.fls_iln_request	(fls_iln_request	[3:0]	),
	.fls_hst_request	(fls_hst_request	[3:0]	),
	.fls_tlz_request	(fls_tlz_request	[3:0]	),
	.fls_sma_request	(fls_sma_request	[3:0]	),
	.fls_cwq_request	(fls_cwq_request	[3:0]	),
	.fls_ade_request	(fls_ade_request	[3:0]	),
	.fls_iae_request	(fls_iae_request	[3:0]	),
	.fls_ipe_request	(fls_ipe_request	[3:0]	),
	.fls_ipv_request	(fls_ipv_request	[0   ]	),
	.fls_inp_request	(fls_inp_request	[0   ]	),
	.fls_iar_request	(fls_iar_request	[0   ]	),
	.fls_irr_request	(fls_irr_request	[0   ]	),
	.fls_mar_request	(fls_mar_request	[0   ]	),
	.fls_mrr_request	(fls_mrr_request	[0   ]	),
	.fls_pro_request	(fls_pro_request	[0   ]	),
	.fls_ill_request	(fls_ill_request	[0   ]	),
	.fls_don_request	(fls_don_request	[0   ]	),
	.fls_ret_request	(fls_ret_request	[0   ]	),
	.fls_fpd_request	(fls_fpd_request	[0   ]	),
	.fls_snn_request	(fls_snn_request	[0   ]	),
	.fls_sno_request	(fls_sno_request	[0   ]	),
	.fls_fnn_request	(fls_fnn_request	[0   ]	),
	.fls_fno_request	(fls_fno_request	[0   ]	),
	.fls_clw_request	(fls_clw_request	[0   ]	),
	.fls_dtm_request	(fls_dtm_request	[3:0]	),
	.fls_ldf_request	(fls_ldf_request	[0   ]	),
	.fls_stf_request	(fls_stf_request	[0   ]	),
	.fls_dap_request	(fls_dap_request	[0   ]	),
	.fls_vaw_request	(fls_vaw_request	[0   ]	),
	.fls_iaw_request	(fls_iaw_request	[0   ]	),
	.fls_paw_request	(fls_paw_request	[0   ]	),
	.fls_maa_request	(fls_maa_request	[0   ]	),
	.fls_fpe_request	(fls_fpe_request	[0   ]	),
	.fls_fei_request	(fls_fei_request	[3:0]	),
	.fls_fof_request	(fls_fof_request	[3:0]	),
	.fls_pra_request	(fls_pra_request	[3:0]	),
	.fls_dia_request	(fls_dia_request	[0   ]	),
	.fls_ups_request	(fls_ups_request	[3:0]	),
	.fls_dpv_request	(fls_dpv_request	[0   ]	),
	.fls_dnc_request	(fls_dnc_request	[0   ]	),
	.fls_dnf_request	(fls_dnf_request	[0   ]	),
	.fls_dso_request	(fls_dso_request	[0   ]	),
	.fls_tof_request	(fls_tof_request	[0   ]	),
	.fls_dbz_request	(fls_dbz_request	[3:0]	),
	.fls_tcc_request	(fls_tcc_request	[0   ]	),
	.fls_dae_request	(fls_dae_request	[3:0]	),
	.fls_lsr_request	(fls_lsr_request	[3:0]	),
	.fls_irt_request	(fls_irt_request	[0   ]	),
	.fls_drt_request	(fls_drt_request	[0   ]	),
	.fls_pmu_request	(fls_pmu_request	[3:0]	),
	.fls_mqr_request	(fls_mqr_request	[3:0]	),
	.fls_dqr_request	(fls_dqr_request	[3:0]	),
	.fls_rqr_request	(fls_rqr_request	[3:0]	),
	.fls_idl_request	(fls_idl_request	[3:0]	),
	.fls_res_request	(fls_res_request	[3:0]	),
	.fls_ssr_request	(fls_ssr_request	[3:0]	),
	.fls_ssc_request	(fls_ssc_request	[3:0]	),
	.fls_nns_request	(fls_nns_request	[3:0]	),
	.fls_ime_request	(fls_ime_request	[3:0]	),
	.fls_dme_request	(fls_dme_request	[3:0]	),
	.fls_eer_request	(fls_eer_request	[3:0]	),
	.fls_icp_request	(fls_icp_request	[0   ]	),
	.fls_ftt_request	(fls_ftt_request	[3:0]	),
	.fls_ibp_request	(fls_ibp_request	[0   ]	),
	.fls_tct_request	(fls_tct_request	[0   ]	),
	.fls_ref_request	(fls_ref_request	[0   ]	),
	.fls_pc_valid		(fls_pc_valid		[3:0]	),
	.pmu_tlu_trap_m		(pmu_tlu_trap_m		[3:0]	),
	.fls_trl_l1en		(fls_trl_l1en		[3:0]	),
	.fls_core_running	(fls_core_running	[3:0]	),
	.tlu_flush_ifu		(tlu_flush_ifu		[3:0]	),
	.pct_npc_is_nonseq	(pct_npc_is_nonseq	[3:0]	),
	.trlx_itw_wait		(1'b0				),
	.trlx_itw_last		(trl1_itw_last			),
	.tsa_gl			(tsa0_gl		[1:0]	),
	.tsa_tnpc_nonseq	(tsa_tnpc_nonseq	[0   ]	),
	.tel_tsacu_exc		(tel_tsacu_exc		[3:0]	),
	.tlu_ceter_de		(tlu_ceter_de		[3:0]	),
	.tlu_ceter_pscce	(tlu_ceter_pscce	[3:0]	),
	.tsd_hpstate_red	(tsd_hpstate_red	[3:0]	),
	.tsd_hpstate_hpriv	(tsd_hpstate_hpriv	[3:0]	),
	.tsd_hpstate_tlz	(tsd_hpstate_tlz	[3:0]	),
	.tsd_pstate_ie		(tsd_pstate_ie		[3:0]	),
	.tsd_pstate_am		(tsd_pstate_am		[3:0]	),
	.tsd_htstate_hpriv	(tsd_htstate_hpriv	   [0]	),
	.asi_rd_tl		(asi_rd_tl		[3:0]	),
	.asi_wr_tl		(asi_wr_tl		[3:0]	),
	.asi_rd_pil		(asi_rd_pil		[3:0]	),
	.asi_wr_pil		(asi_wr_pil		[3:0]	),
	.asi_rd_gl		(asi_rd_gl		[3:0]	),
	.asi_wr_gl		(asi_wr_gl		[3:0]	),
	.asi_wr_set_softint	(asi_wr_set_softint	[3:0]	),
	.asi_wr_clear_softint	(asi_wr_clear_softint	[3:0]	),
	.asi_rd_softint		(asi_rd_softint		[3:0]	),
	.asi_wr_softint		(asi_wr_softint		[3:0]	),
	.asi_rd_hintp		(asi_rd_hintp		[3:0]	),
	.asi_wr_hintp		(asi_wr_hintp		[3:0]	),
	.asi_wr_data		(pct0_trl_wr_data	[16:0]	),
	.asi_preempt_trap	(asi_preempt_trap	[0   ]	),
	.asi_preempt_done_retry	(asi_preempt_done_retry	[0   ]	),
	.asi_rmw_tsa		(asi_rmw_tsa		[0   ]	),
	.asi_wr_asireg		(asi_wr_asireg		[3:0]	),
	.asi_trl_pstate_en	(asi_trl_pstate_en	[0   ]	),
	.asi_mbist_tsa_rd_en	(asi_mbist_tsa_rd_en	[0   ]	),
	.asi_mbist_tsa_wr_en	(asi_mbist_tsa_wr_en	[0   ]	),
	.spc_core_running_status(tlu_core_running_status[3:0]	),
	.trl_core_running_status(trl_core_running_status[3:0]	),
	.trl_pil_mask_15	(trl_pil_mask_15	[3:0]	),
	.trl_iln_exc		(trl_iln_exc		[3:0]	),
	.trl_hstick_match	(trl_hstick_match	[3:0]	),
	.trl_unhalt_		(trl_unhalt_		[3:0]	),
	.trl_tlz_exc		(trl_tlz_exc		[3:0]	),
	.trl_nns_exc		(trl_nns_exc		[3:0]	),
	.trl_ssc_exc		(trl_ssc_exc		[3:0]	),
	.trl_take_sma		(trl0_take_sma			),
	.trl_take_cwq		(trl0_take_cwq			),
	.trl_take_xir		(trl0_take_xir			),
	.trl_take_ftt		(trl0_take_ftt			),
	.trl_pc_sel_trap_pc	(trl_pc_sel_trap_pc	[3:0]	),
	.trl_npc_sel_trap_npc	(trl_npc_sel_trap_npc	[3:0]	),
	.trl_npc_sel_tnpc	(trl_npc_sel_tnpc	[3:0]	),
	.trl_invalidate_pc	(trl_invalidate_pc	[3:0]	),
	.trl_invalidate_npc	(trl_invalidate_npc	[3:0]	),
	.trl_trap_type		(trl0_trap_type		[8:0]	),
	.trl_tsa_trap_type	(trl0_tsa_trap_type	[8:0]	),
	.trl_asireg_sel		(trl0_asireg_sel	[4:0]	),
	.trl_asireg_en		(trl0_asireg_en			),
	.trl_thread_sel		(trl0_thread_sel	[3:0]	),
	.trl_tba_sel		(trl0_tba_sel		[2:0]	),
	.trl_pc_thread_sel	(trl0_pc_thread_sel	[3:0]	),
	.trl_pc_pstate_am_	(trl_pc_pstate_am_	[0   ]	),
	.trl_pstate_thread_sel	(trl0_pstate_thread_sel	[4:0]	),
	.trl_don_ret_pstate_sel	(trl0_don_ret_pstate_sel[3:0]	),
	.trl_pstate_en		(trl0_pstate_en			),
	.trl_pc_sel_pc		(trl_pc_sel_pc		[0   ]	),
	.trl_pc_sel_npc		(trl_pc_sel_npc		[0   ]	),
	.trl_pc_sel_trap	(trl_pc_sel_trap	[0   ]	),
	.trl_pc_sel_reset	(trl_pc_sel_reset	[0   ]	),
	.trl_pc_done		(trl_pc_done		[0   ]	),
	.trl_pc_retry		(trl_pc_retry		[0   ]	),
	.trl_pc_tte		(trl_pc_tte		[0   ]	),
	.trl_pct_trap_pc_en	(trl_pct_trap_pc_en	[0   ]	),
	.trl_pct_tnpc_en	(trl_pct_tnpc_en	[0   ]	),
	.trl_reset_trap		(trl_reset_trap		[0   ]	),
	.trl_other_trap		(trl_other_trap		[0   ]	),
	.trl_stay_in_priv	(trl_stay_in_priv	[0   ]	),
	.trl_tsa_wr_en		(trl_tsa_wr_en_pre	[0   ]	),
	.trl_tsa_wr_addr	(trl0_tsa_wr_addr	[4:0]	),
	.trl_tsa_rd_en		(trl_tsa_rd_en		[0   ]	),
	.trl_tsa_rd_addr	(trl0_tsa_rd_addr	[4:0]	),
	.trl_save_tsa		(trl0_save_tsa			),
	.trl_tsd_tsa_en		(trl0_tsd_tsa_en		),
	.trl_tsd_tsa_wd_en	(trl0_tsd_tsa_wd_en		),
	.trl_capture_ss		(trl0_capture_ss		),
	.trl_rmw_tsa		(trl0_rmw_tsa			),
	.trl_tl_gt_0		(trl_tl_gt_0		[0   ]	),
	.trl_tl_eq_0		(trl_tl_eq_0		[3:0]	),
	.trl_tsa_gl		(trl0_tsa_gl		[1:0]	),
	.trl_asi_data		(trl0_asi_data		[16:0]	),
	.trl_ss_complete	(trl_ss_complete	[3:0]	),
	.trl_itw_wait		(trl0_itw_wait			),
	.trl_itw_last		(trl0_itw_last			),
	.trl_shscanid		(trl0_shscanid		[1:0]	),
	.trl_shscanid_2		(trl0_shscanid_2		),
	.trl_shadow_tl		(trl0_shadow_tl		[2:0]	),
	.trl_tl_for_tt		(trl0_tl_for_tt		[2:0]	),
	.trl_fls_npc_en		(trl_fls_npc_en		[3:0]	),
	.trl_trap_taken		(trl_trap_taken		[3:0]	),
	.trl_tel_en		(trl_tel_en		[0   ]	),
	.trl_gl0		(trl_gl0		[1:0]	),
	.trl_gl1		(trl_gl1		[1:0]	),
	.trl_gl2		(trl_gl2		[1:0]	),
	.trl_gl3		(trl_gl3		[1:0]	),
	.trl_tsacu_en_in	(trl_tsacu_en_in	[3:0]	),
	.tlu_tsa_index		(tlu_tsa_index_0	[2:0]	),
	.tlu_tccd		(tlu_tccd		[3:0]	),
	.tlu_tcud		(tlu_tcud		[3:0]	),
	.tlu_tca_index		(tlu_tca_index_0	[1:0]	),
	.tlu_window_block	(tlu_window_block	[0   ]	),
	.tlu_trap_pc_valid	(tlu_trap_pc_0_valid		),
	.tlu_retry		(tlu_retry		[0   ]	),
	.tlu_ifu_invalidate	(tlu_ifu_invalidate	[0   ]	),
	.tlu_trap_tid		(tlu_trap_0_tid		[1:0]	),
	.tlu_itlb_reload	(tlu_itlb_reload	[0   ]	),
	.tlu_ccr_cwp_valid	(tlu_ccr_cwp_0_valid		),
	.tlu_ccr_cwp_tid	(tlu_ccr_cwp_0_tid	[1:0]	),
	.tlu_asi_valid		(tlu_asi_0_valid		),
	.tlu_asi_tid		(tlu_asi_0_tid		[1:0]	),
	.tlu_gl0		(tlu_gl0		[1:0]	),
	.tlu_gl1		(tlu_gl1		[1:0]	),
	.tlu_gl2		(tlu_gl2		[1:0]	),
	.tlu_gl3		(tlu_gl3		[1:0]	),
	.tlu_tl_gt_0		(tlu_tl_gt_0		[3:0]	),
	.tlu_mmu_tl_gt_0	(tlu_mmu_tl_gt_0	[3:0]	),
	.tlu_release_tte	(tlu_release_tte	[3:0]	),
	.tlu_lsu_clear_ctl_reg_	(tlu_lsu_clear_ctl_reg_	[3:0]	),
	.tlu_pmu_trap_taken	(tlu_pmu_trap_taken	[3:0]	),
	.tlu_pmu_trap_mask_e	(tlu_pmu_trap_mask_e	[0   ]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_tlu_pmen(lsu_tlu_pmen),
  .tcu_shscanid(tcu_shscanid[2:0]),
  .tcu_ss_mode(tcu_ss_mode),
  .tcu_do_mode(tcu_do_mode),
  .mbi_run(mbi_run),
  .fgu_fpx_ieee_trap_fw(fgu_fpx_ieee_trap_fw),
  .fgu_fpd_ieee_trap_fw(fgu_fpd_ieee_trap_fw),
  .fgu_fpx_unfin_fw(fgu_fpx_unfin_fw),
  .fgu_fpd_unfin_fw(fgu_fpd_unfin_fw),
  .fgu_fpd_idiv0_trap_fw(fgu_fpd_idiv0_trap_fw),
  .fgu_fpx_trap_tid_fw(fgu_fpx_trap_tid_fw[2:0]),
  .fgu_fpd_trap_tid_fw(fgu_fpd_trap_tid_fw[2:0]),
  .spu_pmu_ma_busy(spu_pmu_ma_busy),
  .spu_tlu_cwq_busy(spu_tlu_cwq_busy),
  .spu_tlu_ma_int_req(spu_tlu_ma_int_req[2:0]),
  .tic_addr(tic_addr[4:0]),
  .tic_not_valid(tic_not_valid),
  .tic_match(tic_match),
  .cel_tccd(cel_tccd),
  .cel_tcud(cel_tcud),
  .asi_tsa_rd_addr(asi_tsa_rd_addr[4:0]),
  .asi_tsa_rd_iqr_ecc(asi_tsa_rd_iqr_ecc),
  .asi_tsa_tid(asi_tsa_tid[1:0]),
  .asi_mbist_addr(asi_mbist_addr[4:0])
);

tlu_trl_ctl trl1 ( 
	.wmr_scan_in(trl1_wmr_scanin),
	.wmr_scan_out(trl1_wmr_scanout),
	.scan_in(trl1_scanin),
	.scan_out(trl1_scanout),
	.l2clk			(l2clk				),
	.thread_group		(1'b1				),
	.ftu_ifu_quiesce	(ftu_ifu_quiesce	[7:4]	),
	.pku_quiesce		(pku_quiesce		[7:4]	),
	.exu_tlu_window_block	(exu_tlu_window_block	[1   ]	),
	.lsu_stb_empty		(lsu_stb_empty		[7:4]	),
	.mmu_write_itlb		(mmu_write_itlb		[7:4]	),
	.mmu_reload_done	(mmu_reload_done	[7:4]	),
	.mmu_i_unauth_access	(mmu_i_unauth_access	[7:4]	),
	.mmu_i_tsb_miss		(mmu_i_tsb_miss		[7:4]	),
	.mmu_d_tsb_miss		(mmu_d_tsb_miss		[7:4]	),
	.mmu_i_tte_outofrange	(mmu_i_tte_outofrange	[7:4]	),
	.mmu_d_tte_outofrange	(mmu_d_tte_outofrange	[7:4]	),
	.fls_wstate0		(fls_wstate4		[2:0]	),
	.fls_wstate1		(fls_wstate5		[2:0]	),
	.fls_wstate2		(fls_wstate6		[2:0]	),
	.fls_wstate3		(fls_wstate7		[2:0]	),
	.fls_tcc_number_0	(fls_tcc_number_4	[7:0]	),
	.fls_tcc_number_1	(fls_tcc_number_5	[7:0]	),
	.fls_tcc_number_2	(fls_tcc_number_6	[7:0]	),
	.fls_tcc_number_3	(fls_tcc_number_7	[7:0]	),
	.fls_tid_d		(fls1_tid_d		[1:0]	),
	.fls_tid_dec_w_in	(fls_tid_dec_w_in	[7:4]	),
	.fls_por_request	(fls_por_request	[7:4]	),
	.fls_xir_request	(fls_xir_request	[7:4]	),
	.fls_ivt_request	(fls_ivt_request	[7:4]	),
	.fls_sir_request	(fls_sir_request	[7:4]	),
	.fls_itm_request	(fls_itm_request	[7:4]	),
	.fls_iln_request	(fls_iln_request	[7:4]	),
	.fls_hst_request	(fls_hst_request	[7:4]	),
	.fls_tlz_request	(fls_tlz_request	[7:4]	),
	.fls_sma_request	(fls_sma_request	[7:4]	),
	.fls_cwq_request	(fls_cwq_request	[7:4]	),
	.fls_ade_request	(fls_ade_request	[7:4]	),
	.fls_iae_request	(fls_iae_request	[7:4]	),
	.fls_ipe_request	(fls_ipe_request	[7:4]	),
	.fls_ipv_request	(fls_ipv_request	[1   ]	),
	.fls_inp_request	(fls_inp_request	[1   ]	),
	.fls_iar_request	(fls_iar_request	[1   ]	),
	.fls_irr_request	(fls_irr_request	[1   ]	),
	.fls_mar_request	(fls_mar_request	[1   ]	),
	.fls_mrr_request	(fls_mrr_request	[1   ]	),
	.fls_pro_request	(fls_pro_request	[1   ]	),
	.fls_ill_request	(fls_ill_request	[1   ]	),
	.fls_don_request	(fls_don_request	[1   ]	),
	.fls_ret_request	(fls_ret_request	[1   ]	),
	.fls_fpd_request	(fls_fpd_request	[1   ]	),
	.fls_snn_request	(fls_snn_request	[1   ]	),
	.fls_sno_request	(fls_sno_request	[1   ]	),
	.fls_fnn_request	(fls_fnn_request	[1   ]	),
	.fls_fno_request	(fls_fno_request	[1   ]	),
	.fls_clw_request	(fls_clw_request	[1   ]	),
	.fls_dtm_request	(fls_dtm_request	[7:4]	),
	.fls_ldf_request	(fls_ldf_request	[1   ]	),
	.fls_stf_request	(fls_stf_request	[1   ]	),
	.fls_dap_request	(fls_dap_request	[1   ]	),
	.fls_vaw_request	(fls_vaw_request	[1   ]	),
	.fls_iaw_request	(fls_iaw_request	[1   ]	),
	.fls_paw_request	(fls_paw_request	[1   ]	),
	.fls_maa_request	(fls_maa_request	[1   ]	),
	.fls_fpe_request	(fls_fpe_request	[1   ]	),
	.fls_fei_request	(fls_fei_request	[7:4]	),
	.fls_fof_request	(fls_fof_request	[7:4]	),
	.fls_pra_request	(fls_pra_request	[7:4]	),
	.fls_dia_request	(fls_dia_request	[1   ]	),
	.fls_ups_request	(fls_ups_request	[7:4]	),
	.fls_dpv_request	(fls_dpv_request	[1   ]	),
	.fls_dnc_request	(fls_dnc_request	[1   ]	),
	.fls_dnf_request	(fls_dnf_request	[1   ]	),
	.fls_dso_request	(fls_dso_request	[1   ]	),
	.fls_tof_request	(fls_tof_request	[1   ]	),
	.fls_dbz_request	(fls_dbz_request	[7:4]	),
	.fls_tcc_request	(fls_tcc_request	[1   ]	),
	.fls_dae_request	(fls_dae_request	[7:4]	),
	.fls_lsr_request	(fls_lsr_request	[7:4]	),
	.fls_irt_request	(fls_irt_request	[1   ]	),
	.fls_drt_request	(fls_drt_request	[1   ]	),
	.fls_pmu_request	(fls_pmu_request	[7:4]	),
	.fls_mqr_request	(fls_mqr_request	[7:4]	),
	.fls_dqr_request	(fls_dqr_request	[7:4]	),
	.fls_rqr_request	(fls_rqr_request	[7:4]	),
	.fls_idl_request	(fls_idl_request	[7:4]	),
	.fls_res_request	(fls_res_request	[7:4]	),
	.fls_ssr_request	(fls_ssr_request	[7:4]	),
	.fls_ssc_request	(fls_ssc_request	[7:4]	),
	.fls_nns_request	(fls_nns_request	[7:4]	),
	.fls_ime_request	(fls_ime_request	[7:4]	),
	.fls_dme_request	(fls_dme_request	[7:4]	),
	.fls_eer_request	(fls_eer_request	[7:4]	),
	.fls_icp_request	(fls_icp_request	[1   ]	),
	.fls_ftt_request	(fls_ftt_request	[7:4]	),
	.fls_ibp_request	(fls_ibp_request	[1   ]	),
	.fls_tct_request	(fls_tct_request	[1   ]	),
	.fls_ref_request	(fls_ref_request	[1   ]	),
	.fls_pc_valid		(fls_pc_valid		[7:4]	),
	.pmu_tlu_trap_m		(pmu_tlu_trap_m		[7:4]	),
	.fls_trl_l1en		(fls_trl_l1en		[7:4]	),
	.fls_core_running	(fls_core_running	[7:4]	),
	.tlu_flush_ifu		(tlu_flush_ifu		[7:4]	),
	.pct_npc_is_nonseq	(pct_npc_is_nonseq	[7:4]	),
	.trlx_itw_wait		(trl0_itw_wait			),
	.trlx_itw_last		(trl0_itw_last			),
	.tsa_gl			(tsa1_gl		[1:0]	),
	.tsa_tnpc_nonseq	(tsa_tnpc_nonseq	[1   ]	),
	.tel_tsacu_exc		(tel_tsacu_exc		[7:4]	),
	.tlu_ceter_de		(tlu_ceter_de		[7:4]	),
	.tlu_ceter_pscce	(tlu_ceter_pscce	[7:4]	),
	.tsd_hpstate_red	(tsd_hpstate_red	[7:4]	),
	.tsd_hpstate_hpriv	(tsd_hpstate_hpriv	[7:4]	),
	.tsd_hpstate_tlz	(tsd_hpstate_tlz	[7:4]	),
	.tsd_pstate_ie		(tsd_pstate_ie		[7:4]	),
	.tsd_pstate_am		(tsd_pstate_am		[7:4]	),
	.tsd_htstate_hpriv	(tsd_htstate_hpriv	   [1]	),
	.asi_rd_tl		(asi_rd_tl		[7:4]	),
	.asi_wr_tl		(asi_wr_tl		[7:4]	),
	.asi_rd_pil		(asi_rd_pil		[7:4]	),
	.asi_wr_pil		(asi_wr_pil		[7:4]	),
	.asi_rd_gl		(asi_rd_gl		[7:4]	),
	.asi_wr_gl		(asi_wr_gl		[7:4]	),
	.asi_wr_set_softint	(asi_wr_set_softint	[7:4]	),
	.asi_wr_clear_softint	(asi_wr_clear_softint	[7:4]	),
	.asi_rd_softint		(asi_rd_softint		[7:4]	),
	.asi_wr_softint		(asi_wr_softint		[7:4]	),
	.asi_rd_hintp		(asi_rd_hintp		[7:4]	),
	.asi_wr_hintp		(asi_wr_hintp		[7:4]	),
	.asi_wr_data		(pct1_trl_wr_data	[16:0]	),
	.asi_preempt_trap	(asi_preempt_trap	[1   ]	),
	.asi_preempt_done_retry	(asi_preempt_done_retry	[1   ]	),
	.asi_rmw_tsa		(asi_rmw_tsa		[1   ]	),
	.asi_wr_asireg		(asi_wr_asireg		[7:4]	),
	.asi_trl_pstate_en	(asi_trl_pstate_en	[1   ]	),
	.asi_mbist_tsa_rd_en	(asi_mbist_tsa_rd_en	[1   ]	),
	.asi_mbist_tsa_wr_en	(asi_mbist_tsa_wr_en	[1   ]	),
	.spc_core_running_status(tlu_core_running_status[7:4]	),
	.trl_core_running_status(trl_core_running_status[7:4]	),
	.trl_pil_mask_15	(trl_pil_mask_15	[7:4]	),
	.trl_iln_exc		(trl_iln_exc		[7:4]	),
	.trl_hstick_match	(trl_hstick_match	[7:4]	),
	.trl_unhalt_		(trl_unhalt_		[7:4]	),
	.trl_tlz_exc		(trl_tlz_exc		[7:4]	),
	.trl_nns_exc		(trl_nns_exc		[7:4]	),
	.trl_ssc_exc		(trl_ssc_exc		[7:4]	),
	.trl_take_sma		(trl1_take_sma			),
	.trl_take_cwq		(trl1_take_cwq			),
	.trl_take_xir		(trl1_take_xir			),
	.trl_take_ftt		(trl1_take_ftt			),
	.trl_pc_sel_trap_pc	(trl_pc_sel_trap_pc	[7:4]	),
	.trl_npc_sel_trap_npc	(trl_npc_sel_trap_npc	[7:4]	),
	.trl_npc_sel_tnpc	(trl_npc_sel_tnpc	[7:4]	),
	.trl_invalidate_pc	(trl_invalidate_pc	[7:4]	),
	.trl_invalidate_npc	(trl_invalidate_npc	[7:4]	),
	.trl_trap_type		(trl1_trap_type		[8:0]	),
	.trl_tsa_trap_type	(trl1_tsa_trap_type	[8:0]	),
	.trl_asireg_sel		(trl1_asireg_sel	[4:0]	),
	.trl_asireg_en		(trl1_asireg_en			),
	.trl_thread_sel		(trl1_thread_sel	[3:0]	),
	.trl_tba_sel		(trl1_tba_sel		[2:0]	),
	.trl_pstate_thread_sel	(trl1_pstate_thread_sel	[4:0]	),
	.trl_don_ret_pstate_sel	(trl1_don_ret_pstate_sel[3:0]	),
	.trl_pstate_en		(trl1_pstate_en			),
	.trl_pc_thread_sel	(trl1_pc_thread_sel	[3:0]	),
	.trl_pc_pstate_am_	(trl_pc_pstate_am_	[1   ]	),
	.trl_pc_sel_pc		(trl_pc_sel_pc		[1   ]	),
	.trl_pc_sel_npc		(trl_pc_sel_npc		[1   ]	),
	.trl_pc_sel_trap	(trl_pc_sel_trap	[1   ]	),
	.trl_pc_sel_reset	(trl_pc_sel_reset	[1   ]	),
	.trl_pc_done		(trl_pc_done		[1   ]	),
	.trl_pc_retry		(trl_pc_retry		[1   ]	),
	.trl_pc_tte		(trl_pc_tte		[1   ]	),
	.trl_pct_trap_pc_en	(trl_pct_trap_pc_en	[1   ]	),
	.trl_pct_tnpc_en	(trl_pct_tnpc_en	[1   ]	),
	.trl_reset_trap		(trl_reset_trap		[1   ]	),
	.trl_other_trap		(trl_other_trap		[1   ]	),
	.trl_stay_in_priv	(trl_stay_in_priv	[1   ]	),
	.trl_tsa_wr_en		(trl_tsa_wr_en_pre	[1   ]	),
	.trl_tsa_wr_addr	(trl1_tsa_wr_addr	[4:0]	),
	.trl_tsa_rd_en		(trl_tsa_rd_en		[1   ]	),
	.trl_tsa_rd_addr	(trl1_tsa_rd_addr	[4:0]	),
	.trl_save_tsa		(trl1_save_tsa			),
	.trl_tsd_tsa_en		(trl1_tsd_tsa_en		),
	.trl_tsd_tsa_wd_en	(trl1_tsd_tsa_wd_en		),
	.trl_capture_ss		(trl1_capture_ss		),
	.trl_rmw_tsa		(trl1_rmw_tsa			),
	.trl_tl_gt_0		(trl_tl_gt_0		[1   ]	),
	.trl_tl_eq_0		(trl_tl_eq_0		[7:4]	),
	.trl_tsa_gl		(trl1_tsa_gl		[1:0]	),
	.trl_asi_data		(trl1_asi_data		[16:0]	),
	.trl_ss_complete	(trl_ss_complete	[7:4]	),
	.trl_itw_wait		(trl1_itw_wait_unused		),
	.trl_itw_last		(trl1_itw_last			),
	.trl_shscanid		(trl1_shscanid		[1:0]	),
	.trl_shscanid_2		(trl1_shscanid_2		),
	.trl_shadow_tl		(trl1_shadow_tl		[2:0]	),
	.trl_tl_for_tt		(trl1_tl_for_tt		[2:0]	),
	.trl_fls_npc_en		(trl_fls_npc_en		[7:4]	),
	.trl_trap_taken		(trl_trap_taken		[7:4]	),
	.trl_tel_en		(trl_tel_en		[1   ]	),
	.trl_gl0		(trl_gl4		[1:0]	),
	.trl_gl1		(trl_gl5		[1:0]	),
	.trl_gl2		(trl_gl6		[1:0]	),
	.trl_gl3		(trl_gl7		[1:0]	),
	.trl_tsacu_en_in	(trl_tsacu_en_in	[7:4]	),
	.tlu_tsa_index		(tlu_tsa_index_1	[2:0]	),
	.tlu_tccd		(tlu_tccd		[7:4]	),
	.tlu_tcud		(tlu_tcud		[7:4]	),
	.tlu_tca_index		(tlu_tca_index_1	[1:0]	),
	.tlu_window_block	(tlu_window_block	[1]	),
	.tlu_trap_pc_valid	(tlu_trap_pc_1_valid		),
	.tlu_retry		(tlu_retry		[1   ]	),
	.tlu_ifu_invalidate	(tlu_ifu_invalidate	[1   ]	),
	.tlu_trap_tid		(tlu_trap_1_tid		[1:0]	),
	.tlu_itlb_reload	(tlu_itlb_reload	[1   ]	),
	.tlu_ccr_cwp_valid	(tlu_ccr_cwp_1_valid		),
	.tlu_ccr_cwp_tid	(tlu_ccr_cwp_1_tid	[1:0]	),
	.tlu_asi_valid		(tlu_asi_1_valid		),
	.tlu_asi_tid		(tlu_asi_1_tid		[1:0]	),
	.tlu_gl0		(tlu_gl4		[1:0]	),
	.tlu_gl1		(tlu_gl5		[1:0]	),
	.tlu_gl2		(tlu_gl6		[1:0]	),
	.tlu_gl3		(tlu_gl7		[1:0]	),
	.tlu_tl_gt_0		(tlu_tl_gt_0		[7:4]	),
	.tlu_mmu_tl_gt_0	(tlu_mmu_tl_gt_0	[7:4]	),
	.tlu_release_tte	(tlu_release_tte	[7:4]	),
	.tlu_lsu_clear_ctl_reg_	(tlu_lsu_clear_ctl_reg_	[7:4]	),
	.tlu_pmu_trap_taken	(tlu_pmu_trap_taken	[7:4]	),
	.tlu_pmu_trap_mask_e	(tlu_pmu_trap_mask_e	[1   ]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_tlu_pmen(lsu_tlu_pmen),
  .tcu_shscanid(tcu_shscanid[2:0]),
  .tcu_ss_mode(tcu_ss_mode),
  .tcu_do_mode(tcu_do_mode),
  .mbi_run(mbi_run),
  .fgu_fpx_ieee_trap_fw(fgu_fpx_ieee_trap_fw),
  .fgu_fpd_ieee_trap_fw(fgu_fpd_ieee_trap_fw),
  .fgu_fpx_unfin_fw(fgu_fpx_unfin_fw),
  .fgu_fpd_unfin_fw(fgu_fpd_unfin_fw),
  .fgu_fpd_idiv0_trap_fw(fgu_fpd_idiv0_trap_fw),
  .fgu_fpx_trap_tid_fw(fgu_fpx_trap_tid_fw[2:0]),
  .fgu_fpd_trap_tid_fw(fgu_fpd_trap_tid_fw[2:0]),
  .spu_pmu_ma_busy(spu_pmu_ma_busy),
  .spu_tlu_cwq_busy(spu_tlu_cwq_busy),
  .spu_tlu_ma_int_req(spu_tlu_ma_int_req[2:0]),
  .tic_addr(tic_addr[4:0]),
  .tic_not_valid(tic_not_valid),
  .tic_match(tic_match),
  .cel_tccd(cel_tccd),
  .cel_tcud(cel_tcud),
  .asi_tsa_rd_addr(asi_tsa_rd_addr[4:0]),
  .asi_tsa_rd_iqr_ecc(asi_tsa_rd_iqr_ecc),
  .asi_tsa_tid(asi_tsa_tid[1:0]),
  .asi_mbist_addr(asi_mbist_addr[4:0])
);


////////////////////////////////////////////////////////////////////////////////
// Trap Stack Array and associated datapath
//   GL      CCR    ASI   PSTATE  CWP
//  41 40   39 32  31 24  19   8  4 0

// ECC generation for 136 bits

assign teg0_data_in[135:0] =
	{tsd_wr_tpc_oor_va	[0   ],
	 tsd_wr_tnpc_oor_va	[0   ],
	 tsd_wr_tnpc_nonseq	[0   ],
	 tsd0_wr_gl		[1:0],
	 tsd0_wr_data		[29:0],
	 tsd0_wr_trap_type	[8:0],
	 tsd0_wr_tpc		[47:23],
	 tsd0_wr_tpc		[22:2],
	 tsd0_wr_tnpc		[47:2]};

tlu_ecg_dp teg01 (
	.data_in		(teg0_data_in		[135:68]),
	.ecc_out		(teg0_ecc		[15:8]	)
);

tlu_ecg_dp teg00 (
	.data_in		(teg0_data_in		[67:0]	),
	.ecc_out		(teg0_ecc		[7:0]	)
);

tlu_eem_dp tem01 (
	.asi_error_inject	(asi_error_tsau			),
	.asi_mbist_ecc_in	(asi_mbist_tsa_ecc_in	[7:0]	),
	.ecc_in			(teg0_ecc		[15:8]	),
	.ecc_out		(tem0_ecc		[15:8]	),
  .asi_error_mask(asi_error_mask[7:0]),
  .asi_mbist_run(asi_mbist_run)
);

tlu_eem_dp tem00 (
	.asi_error_inject	(asi_error_tsau			),
	.asi_mbist_ecc_in	(asi_mbist_tsa_ecc_in	[7:0]	),
	.ecc_in			(teg0_ecc		[7:0]	),
	.ecc_out		(tem0_ecc		[7:0]	),
  .asi_error_mask(asi_error_mask[7:0]),
  .asi_mbist_run(asi_mbist_run)
);

// ECC error detection for 136 bits
tlu_tel_dp tel0 (
	.scan_in(tel0_scanin),
	.scan_out(tel0_scanout),
	.l2clk			(l2clk				),
	.trl_tel_en		(trl_tel_en		[0   ]	),
	.asi_mbist_tel_en	(asi_mbist_tel_en	[0   ]	),
	.tsa_ecc		(tsa0_ecc		[15:0]	),
	.ted_syndrome		(ted0_syndrome		[15:0]	),
	.ted0_cecc_err		(ted00_cecc_err			),
	.ted0_uecc_err		(ted00_uecc_err			),
	.ted0_uecc_err_		(ted00_uecc_err_		),
	.ted1_cecc_err		(ted01_cecc_err			),
	.ted1_uecc_err		(ted01_uecc_err			),
	.ted1_uecc_err_		(ted01_uecc_err_		),
	.trl_tsacu_en_in	(trl_tsacu_en_in	[3:0]	),
	.tel_syndrome		(tel0_syndrome		[15:0]	),
	.tel_ecc		(tel0_ecc		[15:0]	),
	.tel_crit_ecc		(tel0_crit_ecc		[15:0]	),
	.tel_tsac		(tel0_tsac			),
	.tel_tsau		(tel0_tsau			),
	.tel_tsac_exc		(tlu_tsac		[3:0]	),
	.tel_tsau_exc		(tlu_tsau		[3:0]	),
	.tel_tsacu_exc		(tel_tsacu_exc		[3:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

tlu_ecd_dp ted01 (
	.data_in		(tsd0_ted_mra_rd_data	[135:68]),
	.ecc_in			(tel0_crit_ecc		[15:8]	),
	.cerer_ce		(tlu_cerer_tsac			),
	.cerer_ue		(tlu_cerer_tsau			),
	.syndrome		(ted0_syndrome		[15:8]	),
	.cecc_err		(ted01_cecc_err			),
	.uecc_err		(ted01_uecc_err			),
	.uecc_err_		(ted01_uecc_err_		)
);

tlu_ecd_dp ted00 (
	.data_in		(tsd0_ted_mra_rd_data	[67:0]	),
	.ecc_in			(tel0_crit_ecc		[7:0]	),
	.cerer_ce		(tlu_cerer_tsac			),
	.cerer_ue		(tlu_cerer_tsau			),
	.syndrome		(ted0_syndrome		[7:0]	),
	.cecc_err		(ted00_cecc_err			),
	.uecc_err		(ted00_uecc_err			),
	.uecc_err_		(ted00_uecc_err_		)
);

tlu_tsb_dp tsb0 (
	.tsb_in			(teg0_data_in		[135:0]	),
        .wr_en_in		(trl_tsa_wr_en_pre	[0   ] ),
        .ecc_error		(asi_tsacu		[0   ] ),
	.tsb_out		(tsb0_data_out		[135:0]	),
        .wr_en_out		(trl_tsa_wr_en		[0   ] )
);

n2_com_dp_32x152_cust tsa0 (
	.scan_in(tsa0_scanin),
	.scan_out(tsa0_scanout),
	.rdclk			(l2clk				),
	.wrclk			(l2clk				),
	.tcu_aclk		(spc_aclk			),
	.tcu_bclk		(spc_bclk			),
	.rd_adr			(trl0_tsa_rd_addr	[4:0]	),
	.rd_en			(trl_tsa_rd_en		[0   ]	),
	.wr_adr			(trl0_tsa_wr_addr	[4:0]	),
	.wr_en			(trl_tsa_wr_en		[0   ]	),
	.din			({tsb0_data_out		[135:134],
				  tem0_ecc		[15:0],
				  tsb0_data_out		[133:0]}),
	.dout			({tsa_tpc_oor_va	[0   ],
				  tsa_tnpc_oor_va	[0   ],
				  tsa0_ecc		[15:0],
				  tsa_tnpc_nonseq	[0   ],
				  tsa0_gl		[1:0],
				  tsa0_rd_data		[29:0],
				  tsa0_trap_type	[8:0],
				  tsa0_tpc		[47:2],
				  tsa0_tnpc		[47:2]}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);


// ECC generation for 136 bits
assign teg1_data_in[135:0] =
	{tsd_wr_tpc_oor_va	[1   ],
	 tsd_wr_tnpc_oor_va	[1   ],
	 tsd_wr_tnpc_nonseq	[1   ],
	 tsd1_wr_gl		[1:0],
	 tsd1_wr_data		[29:0],
	 tsd1_wr_trap_type	[8:0],
	 tsd1_wr_tpc		[47:23],
	 tsd1_wr_tpc		[22:2],
	 tsd1_wr_tnpc		[47:2]};

tlu_ecg_dp teg11 (
	.data_in		(teg1_data_in		[135:68]),
	.ecc_out		(teg1_ecc		[15:8]	)
);

tlu_ecg_dp teg10 (
	.data_in		(teg1_data_in		[67:0]	),
	.ecc_out		(teg1_ecc		[7:0]	)
);

tlu_eem_dp tem11 (
	.asi_error_inject	(asi_error_tsau			),
	.asi_mbist_ecc_in	(asi_mbist_tsa_ecc_in	[7:0]	),
	.ecc_in			(teg1_ecc		[15:8]	),
	.ecc_out		(tem1_ecc		[15:8]	),
  .asi_error_mask(asi_error_mask[7:0]),
  .asi_mbist_run(asi_mbist_run)
);

tlu_eem_dp tem10 (
	.asi_error_inject	(asi_error_tsau			),
	.asi_mbist_ecc_in	(asi_mbist_tsa_ecc_in	[7:0]	),
	.ecc_in			(teg1_ecc		[7:0]	),
	.ecc_out		(tem1_ecc		[7:0]	),
  .asi_error_mask(asi_error_mask[7:0]),
  .asi_mbist_run(asi_mbist_run)
);

// ECC error detection for 136 bits
tlu_tel_dp tel1 (
	.scan_in(tel1_scanin),
	.scan_out(tel1_scanout),
	.l2clk			(l2clk				),
	.trl_tel_en		(trl_tel_en		[1   ]	),
	.asi_mbist_tel_en	(asi_mbist_tel_en	[1   ]	),
	.tsa_ecc		(tsa1_ecc		[15:0]	),
	.ted_syndrome		(ted1_syndrome		[15:0]	),
	.ted0_cecc_err		(ted10_cecc_err			),
	.ted0_uecc_err		(ted10_uecc_err			),
	.ted0_uecc_err_		(ted10_uecc_err_		),
	.ted1_cecc_err		(ted11_cecc_err			),
	.ted1_uecc_err		(ted11_uecc_err			),
	.ted1_uecc_err_		(ted11_uecc_err_		),
	.trl_tsacu_en_in	(trl_tsacu_en_in	[7:4]	),
	.tel_syndrome		(tel1_syndrome		[15:0]	),
	.tel_ecc		(tel1_ecc		[15:0]	),
	.tel_crit_ecc		(tel1_crit_ecc		[15:0]	),
	.tel_tsac		(tel1_tsac			),
	.tel_tsau		(tel1_tsau			),
	.tel_tsac_exc		(tlu_tsac		[7:4]	),
	.tel_tsau_exc		(tlu_tsau		[7:4]	),
	.tel_tsacu_exc		(tel_tsacu_exc		[7:4]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en)
);

tlu_ecd_dp ted11 (
	.data_in		(tsd1_ted_mra_rd_data	[135:68]),
	.ecc_in			(tel1_crit_ecc		[15:8]	),
	.cerer_ce		(tlu_cerer_tsac			),
	.cerer_ue		(tlu_cerer_tsau			),
	.syndrome		(ted1_syndrome		[15:8]	),
	.cecc_err		(ted11_cecc_err			),
	.uecc_err		(ted11_uecc_err			),
	.uecc_err_		(ted11_uecc_err_		)
);

tlu_ecd_dp ted10 (
	.data_in		(tsd1_ted_mra_rd_data	[67:0]	),
	.ecc_in			(tel1_crit_ecc		[7:0]	),
	.cerer_ce		(tlu_cerer_tsac			),
	.cerer_ue		(tlu_cerer_tsau			),
	.syndrome		(ted1_syndrome		[7:0]	),
	.cecc_err		(ted10_cecc_err			),
	.uecc_err		(ted10_uecc_err			),
	.uecc_err_		(ted10_uecc_err_		)
);

tlu_tsb_dp tsb1 (
	.tsb_in			(teg1_data_in		[135:0]	),
        .wr_en_in		(trl_tsa_wr_en_pre	[1   ] ),
        .ecc_error		(asi_tsacu		[1   ] ),
	.tsb_out		(tsb1_data_out		[135:0]	),
        .wr_en_out		(trl_tsa_wr_en		[1   ] )
);

n2_com_dp_32x152_cust tsa1 (
	.scan_in(tsa1_scanin),
	.scan_out(tsa1_scanout),
	.rdclk			(l2clk				),
	.wrclk			(l2clk				),
	.tcu_aclk		(spc_aclk			),
	.tcu_bclk		(spc_bclk			),
	.rd_adr			(trl1_tsa_rd_addr	[4:0]	),
	.rd_en			(trl_tsa_rd_en		[1   ]	),
	.wr_adr			(trl1_tsa_wr_addr	[4:0]	),
	.wr_en			(trl_tsa_wr_en		[1   ]	),
	.din			({tsb1_data_out		[135:134],
				  tem1_ecc		[15:0],
				  tsb1_data_out		[133:0]}),
	.dout			({tsa_tpc_oor_va	[1   ],
				  tsa_tnpc_oor_va	[1   ],
				  tsa1_ecc		[15:0],
				  tsa_tnpc_nonseq	[1   ],
				  tsa1_gl		[1:0],
				  tsa1_rd_data		[29:0],
				  tsa1_trap_type	[8:0],
				  tsa1_tpc		[47:2],
				  tsa1_tnpc		[47:2]}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);


tlu_tsd_dp tsd0 ( 
	.wmr_scan_in(tsd0_wmr_scanin),
	.wmr_scan_out(tsd0_wmr_scanout),
	.scan_in(tsd0_scanin),
	.scan_out(tsd0_scanout),
	.l2clk			(l2clk				),
	.trl_shscanid		(trl0_shscanid		[1:0]	),
	.exu_ccr0		(exu0_ccr0		[7:0]	),
	.exu_ccr1		(exu0_ccr1		[7:0]	),
	.exu_ccr2		(exu0_ccr2		[7:0]	),
	.exu_ccr3		(exu0_ccr3		[7:0]	),
	.fls_cwp0		(fls0_cwp0		[2:0]	),
	.fls_cwp1		(fls0_cwp1		[2:0]	),
	.fls_cwp2		(fls0_cwp2		[2:0]	),
	.fls_cwp3		(fls0_cwp3		[2:0]	),
	.pct_tsa_pc		(pct0_tsa_pc		[47:2]	),
	.pct_tsa_pc_oor_va	(pct_tsa_pc_oor_va	[0   ]	),
	.pct_tsa_npc		(pct0_tsa_npc		[47:2]	),
	.pct_tsa_npc_oor_va	(pct_tsa_npc_oor_va	[0   ]	),
	.pct_tsa_npc_nonseq	(pct_tsa_npc_nonseq	[0   ]	),
	.trl_tsa_gl		(trl0_tsa_gl		[1:0]	),
	.trl_tsa_trap_type	(trl0_tsa_trap_type	[8:0]	),
	.trl_asireg_sel		(trl0_asireg_sel	[4:0]	),
	.trl_asireg_en		(trl0_asireg_en			),
	.trl_thread_sel		(trl0_thread_sel	[3:0]	),
	.trl_tba_sel		(trl0_tba_sel		[2:0]	),
	.trl_pstate_thread_sel	(trl0_pstate_thread_sel	[4:0]	),
	.trl_don_ret_pstate_sel	(trl0_don_ret_pstate_sel[3:0]	),
	.trl_pstate_en		(trl0_pstate_en			),
	.trl_reset_trap		(trl_reset_trap		[0   ]	),
	.trl_other_trap		(trl_other_trap		[0   ]	),
	.trl_stay_in_priv	(trl_stay_in_priv	[0   ]	),
	.trl_tl_gt_0		(trl_tl_gt_0		[0   ]	),
	.trl_save_tsa		(trl0_save_tsa			),
	.trl_tsd_tsa_en		(trl0_tsd_tsa_en		),
	.trl_tsd_tsa_wd_en	(trl0_tsd_tsa_wd_en		),
	.trl_capture_ss		(trl0_capture_ss		),
	.trl_rmw_tsa		(trl0_rmw_tsa			),
	.tsa_tpc		(tsa0_tpc		[47:2]	),
	.tsa_tpc_oor_va		(tsa_tpc_oor_va		[0   ]	),
	.tsa_tnpc		(tsa0_tnpc		[47:2]	),
	.tsa_tnpc_oor_va	(tsa_tnpc_oor_va	[0   ]	),
	.tsa_tnpc_nonseq	(tsa_tnpc_nonseq	[0   ]	),
	.tsa_gl			(tsa0_gl		[1:0]	),
	.tsa_rd_data		(tsa0_rd_data		[29:0]	),
	.tsa_trap_type		(tsa0_trap_type		[8:0]	),
	.asi_wr_mondo_head	(asi_wr_mondo_head	[0   ]	),
	.asi_wr_mondo_tail	(asi_wr_mondo_tail	[0   ]	),
	.asi_wr_device_head	(asi_wr_device_head	[0   ]	),
	.asi_wr_device_tail	(asi_wr_device_tail	[0   ]	),
	.asi_wr_res_err_head	(asi_wr_res_err_head	[0   ]	),
	.asi_wr_res_err_tail	(asi_wr_res_err_tail	[0   ]	),
	.asi_wr_nonres_err_head	(asi_wr_nonres_err_head	[0   ]	),
	.asi_wr_nonres_err_tail	(asi_wr_nonres_err_tail	[0   ]	),
	.asi_rd_iqr_reg		(asi_rd_iqr_reg		[0   ]	),
	.asi_rd_tpc		(asi_rd_tpc		[0   ]	),
	.asi_wr_tpc		(asi_wr_tpc		[0   ]	),
	.asi_rd_tnpc		(asi_rd_tnpc		[0   ]	),
	.asi_wr_tnpc		(asi_wr_tnpc		[0   ]	),
	.asi_rd_tstate		(asi_rd_tstate		[0   ]	),
	.asi_wr_tstate		(asi_wr_tstate		[0   ]	),
	.asi_rd_tt		(asi_rd_tt		[0   ]	),
	.asi_wr_tt		(asi_wr_tt		[0   ]	),
	.asi_rd_htstate		(asi_rd_htstate		[0   ]	),
	.asi_wr_htstate		(asi_wr_htstate		[0   ]	),
	.asi_wr_tba		(asi_wr_tba		[3:0]	),
	.asi_wr_pstate		(asi_wr_pstate		[3:0]	),
	.asi_wr_hpstate		(asi_wr_hpstate		[3:0]	),
	.asi_wr_htba		(asi_wr_htba		[3:0]	),
	.asi_rd_asireg		(asi_rd_asireg		[3:0]	),
	.asi_wr_asireg		(asi_wr_asireg		[3:0]	),
	.asi_rd_tba_htba	(asi_rd_tba_htba	[0   ]	),
	.asi_rd_pstate_hpstate	(asi_rd_pstate_hpstate	[0   ]	),
	.asi_wr_data_47_14	(asi_wr_data_0		[47:14]	),
	.asi_wr_data_07_00	(asi_wr_data_0		[7:0]	),
	.asi_tsd_wr_data_12	(asi_tsd0_wr_data_12		),
	.asi_tsd_wr_data_10_08	(asi_tsd0_wr_data_10_08	[10:8]	),
	.asi_tsd_wr_data_05_00	(asi_tsd0_wr_data_05_00	[5:0]	),
	.tel_ecc		(tel0_ecc		[15:0]	),
	.tsd_tba		(tsd0_tba		[47:14]	),
	.tsd_wr_tpc		(tsd0_wr_tpc		[47:2]	),
	.tsd_wr_tpc_oor_va	(tsd_wr_tpc_oor_va	[0   ]	),
	.tsd_wr_tnpc		(tsd0_wr_tnpc		[47:2]	),
	.tsd_wr_tnpc_oor_va	(tsd_wr_tnpc_oor_va	[0   ]	),
	.tsd_wr_tnpc_nonseq	(tsd_wr_tnpc_nonseq	[0   ]	),
	.tsd_wr_gl		(tsd0_wr_gl		[1:0]	),
	.tsd_wr_data		(tsd0_wr_data		[29:0]	),
	.tsd_wr_trap_type	(tsd0_wr_trap_type	[8:0]	),
	.tsd_tpc		(tsd0_tpc		[47:2]	),
	.tsd_tpc_oor_va		(tsd_tpc_oor_va		[0   ]	),
	.tsd_tnpc		(tsd0_tnpc		[47:2]	),
	.tsd_tnpc_oor_va	(tsd_tnpc_oor_va	[0   ]	),
	.tsd_tnpc_nonseq	(tsd_tnpc_nonseq	[0   ]	),
	.tsd_mrqr_exc_		(tsd0_mrqr_exc_			),
	.tsd_dqr_exc_		(tsd0_dqr_exc_			),
	.tsd_asi_data_		(tsd0_asi_data_		[47:2]	),
	.tsd_asi_data		(tsd0_asi_data		[1:0]	),
	.tsd_ted_mra_rd_data	(tsd0_ted_mra_rd_data	[135:0]	),
	.tsd_hpstate_ibe	(tsd_hpstate_ibe	[3:0]	),
	.tsd_hpstate_red	(tsd_hpstate_red	[3:0]	),
	.tsd_hpstate_hpriv	(tsd_hpstate_hpriv	[3:0]	),
	.tsd_hpstate_tlz	(tsd_hpstate_tlz	[3:0]	),
	.tsd_pstate_tct		(tsd_pstate_tct		[3:0]	),
	.tsd_pstate_priv	(tsd_pstate_priv	[3:0]	),
	.tsd_pstate_ie		(tsd_pstate_ie		[3:0]	),
	.tsd_pstate_am		(tsd_pstate_am		[3:0]	),
	.tsd_htstate_hpriv	(tsd_htstate_hpriv	   [0]	),
	.tsd_shadow_pstate 	(tsd0_shadow_pstate	[10:0]	),
	.tsd_shadow_tpc 	(tsd0_shadow_tpc	[47:2]	),
	.tsd_shadow_tt 		(tsd0_shadow_tt		[8:0]	),
	.tsd_mbist_data 	(tsd0_mbist_data	[31:0]	),
	.tsd_itlb_bypass	(tsd_itlb_bypass	[3:0]	),
	.tlu_itlb_bypass	(tlu_itlb_bypass	[3:0]	),
	.tlu_lsu_hpstate_hpriv	(tlu_lsu_hpstate_hpriv	[3:0]	),
	.tlu_lsu_pstate_priv	(tlu_lsu_pstate_priv	[3:0]	),
	.tlu_ifu_hpstate_hpriv	(tlu_ifu_hpstate_hpriv	[3:0]	),
	.tlu_ifu_pstate_priv	(tlu_ifu_pstate_priv	[3:0]	),
	.tlu_pmu_hpstate_hpriv	(tlu_pmu_hpstate_hpriv	[3:0]	),
	.tlu_pmu_pstate_priv	(tlu_pmu_pstate_priv	[3:0]	),
	.tlu_dec_hpstate_hpriv	(tlu_dec_hpstate_hpriv	[3:0]	),
	.tlu_dec_pstate_priv	(tlu_dec_pstate_priv	[3:0]	),
	.tlu_dec_pstate_pef	(tlu_dec_pstate_pef	[3:0]	),
	.tlu_pstate_cle		(tlu_pstate_cle		[3:0]	),
	.tlu_pstate_am		(tlu_pstate_am		[3:0]	),
	.tlu_ccr		(tlu_ccr_0		[7:0]	),
	.tlu_asi		(tlu_asi_0		[7:0]	),
	.tlu_cwp		(tlu_cwp_0		[2:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en_wmr(tcu_scan_en_wmr),
  .spc_aclk_wmr(spc_aclk_wmr),
  .asi_rd_iqr(asi_rd_iqr[2:0]),
  .asi_rd_h_pstate_tba(asi_rd_h_pstate_tba[2:0]),
  .asi_tsa_wr_data(asi_tsa_wr_data[47:0]),
  .asi_tsa_wr_data_npc_oor_va(asi_tsa_wr_data_npc_oor_va),
  .asi_tsa_wr_data_npc_nonseq(asi_tsa_wr_data_npc_nonseq),
  .asi_mbist_ecc_in(asi_mbist_ecc_in[7:0]),
  .asi_mbist_run(asi_mbist_run),
  .asi_mbist_cmpsel(asi_mbist_cmpsel[3:0])
);

tlu_tsd_dp tsd1 ( 
	.wmr_scan_in(tsd1_wmr_scanin),
	.wmr_scan_out(tsd1_wmr_scanout),
	.scan_in(tsd1_scanin),
	.scan_out(tsd1_scanout),
	.l2clk			(l2clk				),
	.trl_shscanid		(trl1_shscanid		[1:0]	),
	.exu_ccr0		(exu1_ccr0		[7:0]	),
	.exu_ccr1		(exu1_ccr1		[7:0]	),
	.exu_ccr2		(exu1_ccr2		[7:0]	),
	.exu_ccr3		(exu1_ccr3		[7:0]	),
	.fls_cwp0		(fls1_cwp0		[2:0]	),
	.fls_cwp1		(fls1_cwp1		[2:0]	),
	.fls_cwp2		(fls1_cwp2		[2:0]	),
	.fls_cwp3		(fls1_cwp3		[2:0]	),
	.pct_tsa_pc		(pct1_tsa_pc		[47:2]	),
	.pct_tsa_pc_oor_va	(pct_tsa_pc_oor_va	[1   ]	),
	.pct_tsa_npc		(pct1_tsa_npc		[47:2]	),
	.pct_tsa_npc_nonseq	(pct_tsa_npc_nonseq	[1   ]	),
	.pct_tsa_npc_oor_va	(pct_tsa_npc_oor_va	[1   ]	),
	.trl_tsa_gl		(trl1_tsa_gl		[1:0]	),
	.trl_tsa_trap_type	(trl1_tsa_trap_type	[8:0]	),
	.trl_asireg_sel		(trl1_asireg_sel	[4:0]	),
	.trl_asireg_en		(trl1_asireg_en			),
	.trl_thread_sel		(trl1_thread_sel	[3:0]	),
	.trl_tba_sel		(trl1_tba_sel		[2:0]	),
	.trl_pstate_thread_sel	(trl1_pstate_thread_sel	[4:0]	),
	.trl_don_ret_pstate_sel	(trl1_don_ret_pstate_sel[3:0]	),
	.trl_pstate_en		(trl1_pstate_en			),
	.trl_reset_trap		(trl_reset_trap		[1   ]	),
	.trl_other_trap		(trl_other_trap		[1   ]	),
	.trl_stay_in_priv	(trl_stay_in_priv	[1   ]	),
	.trl_tl_gt_0		(trl_tl_gt_0		[1   ]	),
	.trl_save_tsa		(trl1_save_tsa			),
	.trl_tsd_tsa_en		(trl1_tsd_tsa_en		),
	.trl_tsd_tsa_wd_en	(trl1_tsd_tsa_wd_en		),
	.trl_capture_ss		(trl1_capture_ss		),
	.trl_rmw_tsa		(trl1_rmw_tsa			),
	.tsa_tpc		(tsa1_tpc		[47:2]	),
	.tsa_tpc_oor_va		(tsa_tpc_oor_va		[1   ]	),
	.tsa_tnpc		(tsa1_tnpc		[47:2]	),
	.tsa_tnpc_oor_va	(tsa_tnpc_oor_va	[1   ]	),
	.tsa_tnpc_nonseq	(tsa_tnpc_nonseq	[1   ]	),
	.tsa_gl			(tsa1_gl		[1:0]	),
	.tsa_rd_data		(tsa1_rd_data		[29:0]	),
	.tsa_trap_type		(tsa1_trap_type		[8:0]	),
	.asi_wr_mondo_head	(asi_wr_mondo_head	[1   ]	),
	.asi_wr_mondo_tail	(asi_wr_mondo_tail	[1   ]	),
	.asi_wr_device_head	(asi_wr_device_head	[1   ]	),
	.asi_wr_device_tail	(asi_wr_device_tail	[1   ]	),
	.asi_wr_res_err_head	(asi_wr_res_err_head	[1   ]	),
	.asi_wr_res_err_tail	(asi_wr_res_err_tail	[1   ]	),
	.asi_wr_nonres_err_head	(asi_wr_nonres_err_head	[1   ]	),
	.asi_wr_nonres_err_tail	(asi_wr_nonres_err_tail	[1   ]	),
	.asi_rd_iqr_reg		(asi_rd_iqr_reg		[1   ]	),
	.asi_rd_tpc		(asi_rd_tpc		[1   ]	),
	.asi_wr_tpc		(asi_wr_tpc		[1   ]	),
	.asi_rd_tnpc		(asi_rd_tnpc		[1   ]	),
	.asi_wr_tnpc		(asi_wr_tnpc		[1   ]	),
	.asi_rd_tstate		(asi_rd_tstate		[1   ]	),
	.asi_wr_tstate		(asi_wr_tstate		[1   ]	),
	.asi_rd_tt		(asi_rd_tt		[1   ]	),
	.asi_wr_tt		(asi_wr_tt		[1   ]	),
	.asi_rd_htstate		(asi_rd_htstate		[1   ]	),
	.asi_wr_htstate		(asi_wr_htstate		[1   ]	),
	.asi_wr_tba		(asi_wr_tba		[7:4]	),
	.asi_wr_pstate		(asi_wr_pstate		[7:4]	),
	.asi_wr_hpstate		(asi_wr_hpstate		[7:4]	),
	.asi_wr_htba		(asi_wr_htba		[7:4]	),
	.asi_rd_asireg		(asi_rd_asireg		[7:4]	),
	.asi_wr_asireg		(asi_wr_asireg		[7:4]	),
	.asi_rd_tba_htba	(asi_rd_tba_htba	[1   ]	),
	.asi_rd_pstate_hpstate	(asi_rd_pstate_hpstate	[1   ]	),
	.asi_wr_data_47_14	(asi_wr_data_1		[47:14]	),
	.asi_wr_data_07_00	(asi_wr_data_1		[7:0]	),
	.asi_tsd_wr_data_12	(asi_tsd1_wr_data_12		),
	.asi_tsd_wr_data_10_08	(asi_tsd1_wr_data_10_08	[10:8]	),
	.asi_tsd_wr_data_05_00	(asi_tsd1_wr_data_05_00	[5:0]	),
	.tel_ecc		(tel1_ecc		[15:0]	),
	.tsd_tba		(tsd1_tba		[47:14]	),
	.tsd_wr_tpc		(tsd1_wr_tpc		[47:2]	),
	.tsd_wr_tpc_oor_va	(tsd_wr_tpc_oor_va	[1   ]	),
	.tsd_wr_tnpc		(tsd1_wr_tnpc		[47:2]	),
	.tsd_wr_tnpc_oor_va	(tsd_wr_tnpc_oor_va	[1   ]	),
	.tsd_wr_tnpc_nonseq	(tsd_wr_tnpc_nonseq	[1   ]	),
	.tsd_mrqr_exc_		(tsd1_mrqr_exc_			),
	.tsd_dqr_exc_		(tsd1_dqr_exc_			),
	.tsd_wr_gl		(tsd1_wr_gl		[1:0]	),
	.tsd_wr_data		(tsd1_wr_data		[29:0]	),
	.tsd_wr_trap_type	(tsd1_wr_trap_type	[8:0]	),
	.tsd_tpc		(tsd1_tpc		[47:2]	),
	.tsd_tpc_oor_va		(tsd_tpc_oor_va		[1   ]	),
	.tsd_tnpc		(tsd1_tnpc		[47:2]	),
	.tsd_tnpc_oor_va	(tsd_tnpc_oor_va	[1   ]	),
	.tsd_tnpc_nonseq	(tsd_tnpc_nonseq	[1   ]	),
	.tsd_asi_data_		(tsd1_asi_data_		[47:2]	),
	.tsd_asi_data		(tsd1_asi_data		[1:0]	),
	.tsd_ted_mra_rd_data	(tsd1_ted_mra_rd_data	[135:0]	),
	.tsd_hpstate_ibe	(tsd_hpstate_ibe	[7:4]	),
	.tsd_hpstate_red	(tsd_hpstate_red	[7:4]	),
	.tsd_hpstate_hpriv	(tsd_hpstate_hpriv	[7:4]	),
	.tsd_hpstate_tlz	(tsd_hpstate_tlz	[7:4]	),
	.tsd_pstate_tct		(tsd_pstate_tct		[7:4]	),
	.tsd_pstate_priv	(tsd_pstate_priv	[7:4]	),
	.tsd_pstate_ie		(tsd_pstate_ie		[7:4]	),
	.tsd_pstate_am		(tsd_pstate_am		[7:4]	),
	.tsd_htstate_hpriv	(tsd_htstate_hpriv	   [1]	),
	.tsd_shadow_pstate 	(tsd1_shadow_pstate	[10:0]	),
	.tsd_shadow_tpc 	(tsd1_shadow_tpc	[47:2]	),
	.tsd_shadow_tt 		(tsd1_shadow_tt		[8:0]	),
	.tsd_mbist_data 	(tsd1_mbist_data	[31:0]	),
	.tsd_itlb_bypass	(tsd_itlb_bypass	[7:4]	),
	.tlu_itlb_bypass	(tlu_itlb_bypass	[7:4]	),
	.tlu_lsu_hpstate_hpriv	(tlu_lsu_hpstate_hpriv	[7:4]	),
	.tlu_lsu_pstate_priv	(tlu_lsu_pstate_priv	[7:4]	),
	.tlu_ifu_hpstate_hpriv	(tlu_ifu_hpstate_hpriv	[7:4]	),
	.tlu_ifu_pstate_priv	(tlu_ifu_pstate_priv	[7:4]	),
	.tlu_pmu_hpstate_hpriv	(tlu_pmu_hpstate_hpriv	[7:4]	),
	.tlu_pmu_pstate_priv	(tlu_pmu_pstate_priv	[7:4]	),
	.tlu_dec_hpstate_hpriv	(tlu_dec_hpstate_hpriv	[7:4]	),
	.tlu_dec_pstate_priv	(tlu_dec_pstate_priv	[7:4]	),
	.tlu_dec_pstate_pef	(tlu_dec_pstate_pef	[7:4]	),
	.tlu_pstate_cle		(tlu_pstate_cle		[7:4]	),
	.tlu_pstate_am		(tlu_pstate_am		[7:4]	),
	.tlu_ccr		(tlu_ccr_1		[7:0]	),
	.tlu_asi		(tlu_asi_1		[7:0]	),
	.tlu_cwp		(tlu_cwp_1		[2:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .tcu_scan_en_wmr(tcu_scan_en_wmr),
  .spc_aclk_wmr(spc_aclk_wmr),
  .asi_rd_iqr(asi_rd_iqr[2:0]),
  .asi_rd_h_pstate_tba(asi_rd_h_pstate_tba[2:0]),
  .asi_tsa_wr_data(asi_tsa_wr_data[47:0]),
  .asi_tsa_wr_data_npc_oor_va(asi_tsa_wr_data_npc_oor_va),
  .asi_tsa_wr_data_npc_nonseq(asi_tsa_wr_data_npc_nonseq),
  .asi_mbist_ecc_in(asi_mbist_ecc_in[7:0]),
  .asi_mbist_run(asi_mbist_run),
  .asi_mbist_cmpsel(asi_mbist_cmpsel[3:0])
);


////////////////////////////////////////////////////////////////////////////////
// Fast ASI ring stub

tlu_asi_ctl asi ( 
	.wmr_scan_in(asi_wmr_scanin),
	.wmr_scan_out(asi_wmr_scanout),
	.scan_in(asi_scanin),
	.scan_out(asi_scanout),
	.l2clk			(l2clk				),
	.hver_mask_major_rev	(4'h2				),
	.error_inject_enable	(lsu_asi_error_inject	[31   ]	),
	.error_inject_tccu	(lsu_asi_error_inject	[22   ]	),
	.error_inject_tsau	(lsu_asi_error_inject	[21   ]	),
	.error_inject_mask	(lsu_asi_error_inject	[7:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_asi_clken(lsu_asi_clken),
  .lsu_tlu_pmen(lsu_tlu_pmen),
  .mbi_tsa0_write_en(mbi_tsa0_write_en),
  .mbi_tsa1_write_en(mbi_tsa1_write_en),
  .mbi_tca_write_en(mbi_tca_write_en),
  .mbi_addr(mbi_addr[4:0]),
  .mbi_run(mbi_run),
  .mbi_wdata(mbi_wdata[7:0]),
  .mbi_tsa0_read_en(mbi_tsa0_read_en),
  .mbi_tsa1_read_en(mbi_tsa1_read_en),
  .mbi_tca_read_en(mbi_tca_read_en),
  .mbi_tlu_cmpsel(mbi_tlu_cmpsel[3:0]),
  .mbd_compare(mbd_compare),
  .lsu_rngf_cdbus(lsu_rngf_cdbus[64:0]),
  .pct0_asi_data(pct0_asi_data[48:2]),
  .pct1_asi_data(pct1_asi_data[48:2]),
  .trl0_asi_data(trl0_asi_data[16:0]),
  .trl1_asi_data(trl1_asi_data[16:0]),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .tsd_hpstate_hpriv(tsd_hpstate_hpriv[7:0]),
  .tsd_pstate_priv(tsd_pstate_priv[7:0]),
  .tsd0_asi_data(tsd0_asi_data[1:0]),
  .tsd1_asi_data(tsd1_asi_data[1:0]),
  .tel0_ecc(tel0_ecc[15:0]),
  .tel0_tsac(tel0_tsac),
  .tel0_tsau(tel0_tsau),
  .tel1_ecc(tel1_ecc[15:0]),
  .tel1_tsac(tel1_tsac),
  .tel1_tsau(tel1_tsau),
  .tic_asi_data(tic_asi_data[63:0]),
  .cel_ecc(cel_ecc[7:0]),
  .cer_asi_data(cer_asi_data[63:0]),
  .cel_tccp(cel_tccp),
  .cel_tcup(cel_tcup),
  .mmu_asi_data(mmu_asi_data[64:0]),
  .mmu_asi_read(mmu_asi_read),
  .mmu_asi_cecc(mmu_asi_cecc),
  .mmu_asi_uecc(mmu_asi_uecc),
  .dfd_desr_f(dfd_desr_f[7:0]),
  .dfd_fesr_f(dfd_fesr_f[7:0]),
  .tlu_lsu_clear_ctl_reg_(tlu_lsu_clear_ctl_reg_[7:0]),
  .hver_mask_minor_rev(hver_mask_minor_rev[3:0]),
  .asi_error_tccu(asi_error_tccu),
  .asi_error_tsau(asi_error_tsau),
  .asi_error_mask(asi_error_mask[7:0]),
  .asi_tsa_rd_addr(asi_tsa_rd_addr[4:0]),
  .asi_tsa_rd_iqr_ecc(asi_tsa_rd_iqr_ecc),
  .asi_tsa_tid(asi_tsa_tid[1:0]),
  .asi_rd_asireg(asi_rd_asireg[7:0]),
  .asi_wr_asireg(asi_wr_asireg[7:0]),
  .asi_rd_tick(asi_rd_tick),
  .asi_wr_tick(asi_wr_tick),
  .asi_rd_pc(asi_rd_pc[7:0]),
  .asi_wr_set_softint(asi_wr_set_softint[7:0]),
  .asi_wr_clear_softint(asi_wr_clear_softint[7:0]),
  .asi_rd_softint(asi_rd_softint[7:0]),
  .asi_wr_softint(asi_wr_softint[7:0]),
  .asi_tca_addr(asi_tca_addr[4:0]),
  .asi_tca_addr_valid(asi_tca_addr_valid),
  .asi_tca_wr(asi_tca_wr),
  .asi_wr_mondo_head(asi_wr_mondo_head[1:0]),
  .asi_wr_mondo_tail(asi_wr_mondo_tail[1:0]),
  .asi_wr_device_head(asi_wr_device_head[1:0]),
  .asi_wr_device_tail(asi_wr_device_tail[1:0]),
  .asi_wr_res_err_head(asi_wr_res_err_head[1:0]),
  .asi_wr_res_err_tail(asi_wr_res_err_tail[1:0]),
  .asi_wr_nonres_err_head(asi_wr_nonres_err_head[1:0]),
  .asi_wr_nonres_err_tail(asi_wr_nonres_err_tail[1:0]),
  .asi_rd_iqr_reg(asi_rd_iqr_reg[1:0]),
  .asi_rd_iqr(asi_rd_iqr[2:0]),
  .asi_rd_tpc(asi_rd_tpc[1:0]),
  .asi_wr_tpc(asi_wr_tpc[1:0]),
  .asi_rd_tnpc(asi_rd_tnpc[1:0]),
  .asi_wr_tnpc(asi_wr_tnpc[1:0]),
  .asi_rd_tstate(asi_rd_tstate[1:0]),
  .asi_wr_tstate(asi_wr_tstate[1:0]),
  .asi_rd_tt(asi_rd_tt[1:0]),
  .asi_wr_tt(asi_wr_tt[1:0]),
  .asi_wr_tba(asi_wr_tba[7:0]),
  .asi_wr_pstate(asi_wr_pstate[7:0]),
  .asi_rd_tl(asi_rd_tl[7:0]),
  .asi_wr_tl(asi_wr_tl[7:0]),
  .asi_rd_pil(asi_rd_pil[7:0]),
  .asi_wr_pil(asi_wr_pil[7:0]),
  .asi_rd_gl(asi_rd_gl[7:0]),
  .asi_wr_gl(asi_wr_gl[7:0]),
  .asi_wr_hpstate(asi_wr_hpstate[7:0]),
  .asi_rd_htstate(asi_rd_htstate[1:0]),
  .asi_wr_htstate(asi_wr_htstate[1:0]),
  .asi_rd_hintp(asi_rd_hintp[7:0]),
  .asi_wr_hintp(asi_wr_hintp[7:0]),
  .asi_wr_htba(asi_wr_htba[7:0]),
  .asi_rd_h_pstate_tba(asi_rd_h_pstate_tba[2:0]),
  .asi_rd_tba_htba(asi_rd_tba_htba[1:0]),
  .asi_rd_pstate_hpstate(asi_rd_pstate_hpstate[1:0]),
  .asi_preempt_trap(asi_preempt_trap[1:0]),
  .asi_preempt_done_retry(asi_preempt_done_retry[1:0]),
  .asi_rmw_tsa(asi_rmw_tsa[1:0]),
  .asi_wr_int_rec(asi_wr_int_rec[7:0]),
  .asi_wr_any_int_rec(asi_wr_any_int_rec),
  .asi_rd_inc_vec_2(asi_rd_inc_vec_2[7:0]),
  .asi_int_rec_mux_sel_in(asi_int_rec_mux_sel_in[2:0]),
  .asi_rd_int_rec(asi_rd_int_rec),
  .asi_rd_inc_vec(asi_rd_inc_vec),
  .asi_check_qr_exc(asi_check_qr_exc[7:0]),
  .asi_tca_wr_data_63(asi_tca_wr_data_63),
  .asi_wr_data_0(asi_wr_data_0[63:0]),
  .asi_wr_data_1(asi_wr_data_1[62:0]),
  .asi_tsd0_wr_data_12(asi_tsd0_wr_data_12),
  .asi_tsd0_wr_data_10_08(asi_tsd0_wr_data_10_08[10:8]),
  .asi_tsd0_wr_data_05_00(asi_tsd0_wr_data_05_00[5:0]),
  .asi_tsd1_wr_data_12(asi_tsd1_wr_data_12),
  .asi_tsd1_wr_data_10_08(asi_tsd1_wr_data_10_08[10:8]),
  .asi_tsd1_wr_data_05_00(asi_tsd1_wr_data_05_00[5:0]),
  .asi_tsa_wr_data(asi_tsa_wr_data[47:0]),
  .asi_tsa_wr_data_npc_oor_va(asi_tsa_wr_data_npc_oor_va),
  .asi_tsa_wr_data_npc_nonseq(asi_tsa_wr_data_npc_nonseq),
  .asi_rd_cerer(asi_rd_cerer),
  .asi_rd_ceter(asi_rd_ceter),
  .asi_wr_cerer(asi_wr_cerer),
  .asi_ceter_tid(asi_ceter_tid[2:0]),
  .asi_wr_ceter(asi_wr_ceter),
  .asi_rd_tid(asi_rd_tid[2:0]),
  .asi_rd_isfsr(asi_rd_isfsr),
  .asi_rd_dsfsr(asi_rd_dsfsr),
  .asi_rd_dsfar(asi_rd_dsfar),
  .asi_rd_desr(asi_rd_desr),
  .asi_rd_fesr(asi_rd_fesr),
  .asi_wr_isfsr(asi_wr_isfsr[7:0]),
  .asi_wr_dsfsr(asi_wr_dsfsr[7:0]),
  .asi_wr_dsfar(asi_wr_dsfar[7:0]),
  .asi_rd_iaw(asi_rd_iaw),
  .asi_wr_iaw(asi_wr_iaw[1:0]),
  .asi_decr(asi_decr[63:46]),
  .asi_ece_exc(asi_ece_exc),
  .asi_eue_exc(asi_eue_exc),
  .asi_ecc_tid(asi_ecc_tid[2:0]),
  .asi_tsac(asi_tsac),
  .asi_tsau(asi_tsau),
  .asi_tsacu(asi_tsacu[1:0]),
  .asi_tsacu_tid(asi_tsacu_tid[2:0]),
  .asi_irl_cleared(asi_irl_cleared[7:0]),
  .asi_rd_stage_1(asi_rd_stage_1),
  .asi_trl_pstate_en(asi_trl_pstate_en[1:0]),
  .asi_stg1_en(asi_stg1_en),
  .asi_mbist_ecc_in(asi_mbist_ecc_in[7:0]),
  .asi_mbist_tsa_ecc_in(asi_mbist_tsa_ecc_in[7:0]),
  .asi_mbist_run(asi_mbist_run),
  .asi_mbist_cmpsel(asi_mbist_cmpsel[3:0]),
  .asi_mbd_compare_data(asi_mbd_compare_data[7:0]),
  .asi_mbd_sel_tsd0(asi_mbd_sel_tsd0),
  .asi_mbd_sel_tsd1(asi_mbd_sel_tsd1),
  .asi_mbd_sel_tic(asi_mbd_sel_tic),
  .asi_mbist_addr(asi_mbist_addr[4:0]),
  .asi_mbist_tsa_rd_en(asi_mbist_tsa_rd_en[1:0]),
  .asi_mbist_tsa_wr_en(asi_mbist_tsa_wr_en[1:0]),
  .asi_mbist_tel_en(asi_mbist_tel_en[1:0]),
  .asi_tccup_in(asi_tccup_in),
  .asi_tccud_in(asi_tccud_in),
  .asi_immu_enable(asi_immu_enable[7:0]),
  .asi_spec_enable(asi_spec_enable[7:0]),
  .asi_halt(asi_halt[7:0]),
  .asi_clear_spu_trap_req(asi_clear_spu_trap_req[7:0]),
  .tlu_spec_enable(tlu_spec_enable[7:0]),
  .tlu_tca_tid(tlu_tca_tid[2:0]),
  .tlu_tca_index(tlu_tca_index[1:0]),
  .tlu_mbi_tsa0_fail(tlu_mbi_tsa0_fail),
  .tlu_mbi_tsa1_fail(tlu_mbi_tsa1_fail),
  .tlu_mbi_tca_fail(tlu_mbi_tca_fail),
  .tlu_rngf_cdbus(tlu_rngf_cdbus[64:0]),
  .tlu_rngf_cdbus_error(tlu_rngf_cdbus_error)
);


////////////////////////////////////////////////////////////////////////////////
// TICK register support

tlu_tic_dp tic (
	.scan_in(tic_scanin),
	.scan_out(tic_scanout),
	.l2clk			(l2clk				),
	.asi_wr_data		(asi_wr_data_1		[62:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_dectest(tcu_dectest),
  .tcu_muxtest(tcu_muxtest),
  .cmp_tick_enable(cmp_tick_enable),
  .asi_rd_tick(asi_rd_tick),
  .asi_wr_tick(asi_wr_tick),
  .asi_tca_addr(asi_tca_addr[4:0]),
  .asi_tca_addr_valid(asi_tca_addr_valid),
  .asi_tca_wr(asi_tca_wr),
  .asi_mbist_run(asi_mbist_run),
  .asi_mbist_cmpsel(asi_mbist_cmpsel[1:0]),
  .tca_cmpr_data_in(tca_cmpr_data_in[63:0]),
  .cel_ecc(cel_ecc[7:0]),
  .exu_address0_e(exu_address0_e[47:0]),
  .exu_address1_e(exu_address1_e[47:0]),
  .tic_cmpr_addr(tic_cmpr_addr[4:0]),
  .tic_cmpr_wr_en(tic_cmpr_wr_en),
  .tic_cmpr_rd_en(tic_cmpr_rd_en),
  .tic_asi_data(tic_asi_data[63:0]),
  .tic_cmpr_data(tic_cmpr_data[63:0]),
  .tic_addr(tic_addr[4:0]),
  .tic_not_valid(tic_not_valid),
  .tic_match(tic_match),
  .tic_mbist_data(tic_mbist_data[31:0]),
  .tic_exu_address0_m(tic_exu_address0_m[47:2]),
  .tic_exu_address1_m(tic_exu_address1_m[47:2]),
  .tic_exu_address0_b(tic_exu_address0_b[1:0]),
  .tic_exu_address1_b(tic_exu_address1_b[1:0])
);

// Storage for TICK_CMPR, STICK_CMPR, HSTICK_CMPR
// Addressing:
//		4:3	10 HSTICK_CMPR
//			01 STICK_CMPR
//			00 TICK_CMPR
//		2:0	Thread ID
//
// Since (H)(S)TICK_CMPR.INTDIS (bit 63) has POR value of 1, store it
// negative active


n2_com_dp_32x72_cust tca (
        .scan_in(tca_scanin),
        .scan_out(tca_scanout),
        .rdclk			(l2clk				),
        .wrclk			(l2clk				),
	.tcu_aclk		(spc_aclk			),
	.tcu_bclk		(spc_bclk			),
	.rd_adr			(tic_cmpr_addr		[4:0]	),
	.rd_en			(tic_cmpr_rd_en			),
	.wr_adr			(tic_cmpr_addr		[4:0]	),
	.wr_en			(tic_cmpr_wr_en			),
	.din			({cem_ecc		[7:0],
				  asi_tca_wr_data_63	       ,
				  asi_wr_data_1		[62:0]}),
	.dout			({tca_ecc		[7:0],
				  tca_cmpr_data_in	[63:0]}),
  .tcu_pce_ov(tcu_pce_ov),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .tcu_se_scancollar_in(tcu_se_scancollar_in),
  .bist_clk_mux_sel(bist_clk_mux_sel),
  .rd_pce(rd_pce),
  .wr_pce(wr_pce)
);


// ECC generation for 64 bits
tlu_cep_dp cep (
	.scan_in(cep_scanin),
	.scan_out(cep_scanout),
	.l2clk			(l2clk				),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .lsu_rngf_cdbus(lsu_rngf_cdbus[63:0]),
  .asi_stg1_en(asi_stg1_en),
  .cep_wr_data(cep_wr_data[63:0])
);

tlu_ecg_dp ceg (
	.data_in		({{4 {1'b0}}		       ,
				  cep_wr_data		[63:0]}),
	.ecc_out		(ceg_ecc		[7:0]	)
);

tlu_eem_dp cem (
	.asi_error_inject	(asi_error_tccu			),
	.ecc_in			(ceg_ecc		[7:0]	),
	.ecc_out		(cem_ecc		[7:0]	),
  .asi_error_mask(asi_error_mask[7:0]),
  .asi_mbist_ecc_in(asi_mbist_ecc_in[7:0]),
  .asi_mbist_run(asi_mbist_run)
);

// ECC error detection for 64 bits
tlu_cel_dp cel (
	.scan_in(cel_scanin),
	.scan_out(cel_scanout),
	.l2clk			(l2clk				),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tlu_cerer_tccp(tlu_cerer_tccp),
  .tlu_cerer_tcup(tlu_cerer_tcup),
  .tlu_cerer_tccd(tlu_cerer_tccd),
  .tlu_cerer_tcud(tlu_cerer_tcud),
  .ced_syndrome(ced_syndrome[7:0]),
  .tca_ecc(tca_ecc[7:0]),
  .ced_cecc_err(ced_cecc_err),
  .ced_uecc_err(ced_uecc_err),
  .asi_tccup_in(asi_tccup_in),
  .asi_tccud_in(asi_tccud_in),
  .cel_syndrome(cel_syndrome[7:0]),
  .cel_ecc(cel_ecc[7:0]),
  .cel_crit_ecc(cel_crit_ecc[7:0]),
  .cel_tccp(cel_tccp),
  .cel_tcup(cel_tcup),
  .cel_tccd(cel_tccd),
  .cel_tcud(cel_tcud)
);

tlu_ecd_dp ced (
	.data_in		({{4 {1'b0}}		       ,
				 tic_cmpr_data		[63:0]}),
	.ecc_in			(cel_crit_ecc		[7:0]	),
	.cerer_ce		(1'b1				),
	.cerer_ue		(1'b1				),
	.syndrome		(ced_syndrome		[7:0]	),
	.cecc_err		(ced_cecc_err			),
	.uecc_err		(ced_uecc_err			),
	.uecc_err_		(ced_uecc_err__unused		)
);


////////////////////////////////////////////////////////////////////////////////
// RAS 

// control regs
tlu_cer_dp cer (
	.scan_in(cer_scanin),
	.scan_out(cer_scanout),
	.l2clk			(l2clk			       	),
	.asi_wr_data		(asi_wr_data_0		[63:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .asi_rd_cerer(asi_rd_cerer),
  .asi_rd_ceter(asi_rd_ceter),
  .asi_wr_cerer(asi_wr_cerer),
  .asi_ceter_tid(asi_ceter_tid[2:0]),
  .asi_wr_ceter(asi_wr_ceter),
  .cth_asi_data(cth_asi_data[63:0]),
  .cer_asi_data(cer_asi_data[63:0]),
  .tlu_cerer_ittp(tlu_cerer_ittp),
  .tlu_cerer_itdp(tlu_cerer_itdp),
  .tlu_cerer_ittm(tlu_cerer_ittm),
  .tlu_cerer_hwtwmu(tlu_cerer_hwtwmu),
  .tlu_cerer_hwtwl2(tlu_cerer_hwtwl2),
  .tlu_cerer_icl2c(tlu_cerer_icl2c),
  .tlu_cerer_icl2u(tlu_cerer_icl2u),
  .tlu_cerer_icl2nd(tlu_cerer_icl2nd),
  .tlu_cerer_irf(tlu_cerer_irf),
  .tlu_cerer_frf(tlu_cerer_frf),
  .tlu_cerer_dttp(tlu_cerer_dttp),
  .tlu_cerer_dttm(tlu_cerer_dttm),
  .tlu_cerer_dtdp(tlu_cerer_dtdp),
  .tlu_cerer_dcl2c(tlu_cerer_dcl2c),
  .tlu_cerer_dcl2u(tlu_cerer_dcl2u),
  .tlu_cerer_dcl2nd(tlu_cerer_dcl2nd),
  .tlu_cerer_sbdlc(tlu_cerer_sbdlc),
  .tlu_cerer_sbdlu(tlu_cerer_sbdlu),
  .tlu_cerer_mrau(tlu_cerer_mrau),
  .tlu_cerer_tsac(tlu_cerer_tsac),
  .tlu_cerer_tsau(tlu_cerer_tsau),
  .tlu_cerer_scac(tlu_cerer_scac),
  .tlu_cerer_scau(tlu_cerer_scau),
  .tlu_cerer_tccp(tlu_cerer_tccp),
  .tlu_cerer_tcup(tlu_cerer_tcup),
  .tlu_cerer_sbapp(tlu_cerer_sbapp),
  .tlu_cerer_l2c_socc(tlu_cerer_l2c_socc),
  .tlu_cerer_l2u_socu(tlu_cerer_l2u_socu),
  .tlu_cerer_l2nd(tlu_cerer_l2nd),
  .tlu_cerer_icvp(tlu_cerer_icvp),
  .tlu_cerer_ictp(tlu_cerer_ictp),
  .tlu_cerer_ictm(tlu_cerer_ictm),
  .tlu_cerer_icdp(tlu_cerer_icdp),
  .tlu_cerer_dcvp(tlu_cerer_dcvp),
  .tlu_cerer_dctp(tlu_cerer_dctp),
  .tlu_cerer_dctm(tlu_cerer_dctm),
  .tlu_cerer_dcdp(tlu_cerer_dcdp),
  .tlu_cerer_sbdpc(tlu_cerer_sbdpc),
  .tlu_cerer_sbdpu(tlu_cerer_sbdpu),
  .tlu_cerer_mamu(tlu_cerer_mamu),
  .tlu_cerer_tccd(tlu_cerer_tccd),
  .tlu_cerer_tcud(tlu_cerer_tcud),
  .tlu_cerer_mal2c(tlu_cerer_mal2c),
  .tlu_cerer_mal2u(tlu_cerer_mal2u),
  .tlu_cerer_mal2nd(tlu_cerer_mal2nd),
  .tlu_cerer_cwql2c(tlu_cerer_cwql2c),
  .tlu_cerer_cwql2u(tlu_cerer_cwql2u),
  .tlu_cerer_cwql2nd(tlu_cerer_cwql2nd),
  .tlu_ceter_pscce(tlu_ceter_pscce[7:0]),
  .tlu_ceter_de(tlu_ceter_de[7:0]),
  .tlu_ceter_dhcce(tlu_ceter_dhcce[7:0])
);

tlu_ras_ctl ras ( 
	.wmr_scan_in(ras_wmr_scanin),
	.wmr_scan_out(ras_wmr_scanout),
	.scan_in(ras_scanin),
	.scan_out(ras_scanout),
	.l2clk			(l2clk			       	),
	.asi_wr_data		(cth_wr_data		[3:0]	),
	.spu_tlu_mamu_err_req_v	(spu_tlu_ma_int_req	[4   ]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_tlu_pmen(lsu_tlu_pmen),
  .ftu_excp_way_d(ftu_excp_way_d[2:0]),
  .ftu_excp_tid_d(ftu_excp_tid_d[2:0]),
  .ftu_excp_way_valid_d(ftu_excp_way_valid_d),
  .dec_exc0_m(dec_exc0_m[4:0]),
  .dec_exc1_m(dec_exc1_m[4:0]),
  .dec_icache_perr_m(dec_icache_perr_m[1:0]),
  .dec_tid0_m(dec_tid0_m[1:0]),
  .dec_tid1_m(dec_tid1_m[1:0]),
  .dec_inst_valid_m(dec_inst_valid_m[1:0]),
  .dec_fgu_inst_m(dec_fgu_inst_m[1:0]),
  .dec_lsu_inst_m(dec_lsu_inst_m[1:0]),
  .dec_flush_b(dec_flush_b[1:0]),
  .fls_irf_cecc_b(fls_irf_cecc_b[1:0]),
  .fls_irf_uecc_b(fls_irf_uecc_b[1:0]),
  .fls_kill_irf_ecc_w(fls_kill_irf_ecc_w[1:0]),
  .exu0_ecc_addr_m(exu0_ecc_addr_m[4:0]),
  .exu1_ecc_addr_m(exu1_ecc_addr_m[4:0]),
  .exu0_ecc_check_m(exu0_ecc_check_m[7:0]),
  .exu1_ecc_check_m(exu1_ecc_check_m[7:0]),
  .fls_f_cecc_w(fls_f_cecc_w),
  .fls_f_uecc_w(fls_f_uecc_w),
  .fgu_ecc_addr_fx2(fgu_ecc_addr_fx2[5:0]),
  .fgu_ecc_check_fx2(fgu_ecc_check_fx2[13:0]),
  .fgu_pdist_beat2_fx1(fgu_pdist_beat2_fx1),
  .lsu_tlu_twocycle_m(lsu_tlu_twocycle_m),
  .lsu_block_store_b(lsu_block_store_b[7:0]),
  .fls_load_dsfar(fls_load_dsfar[7:0]),
  .fls_ipe_dme_request(fls_ipe_dme_request[1:0]),
  .lsu_dttp_err_b(lsu_dttp_err_b),
  .lsu_dtdp_err_b(lsu_dtdp_err_b),
  .lsu_dtmh_err_b(lsu_dtmh_err_b),
  .lsu_dcmh_err_g(lsu_dcmh_err_g),
  .lsu_dcvp_err_g(lsu_dcvp_err_g),
  .lsu_dctp_err_g(lsu_dctp_err_g),
  .lsu_dcdp_err_g(lsu_dcdp_err_g),
  .lsu_dcl2c_err_g(lsu_dcl2c_err_g),
  .lsu_dcl2u_err_g(lsu_dcl2u_err_g),
  .lsu_dcl2nd_err_g(lsu_dcl2nd_err_g),
  .lsu_dcsoc_err_g(lsu_dcsoc_err_g),
  .lsu_dcerr_tid_g(lsu_dcerr_tid_g[2:0]),
  .lsu_dcerr_sfar_g(lsu_dcerr_sfar_g[8:0]),
  .lsu_sbdlc_err_g(lsu_sbdlc_err_g),
  .lsu_sbdlu_err_g(lsu_sbdlu_err_g),
  .lsu_sbdpc_err_g(lsu_sbdpc_err_g),
  .lsu_sbdpu_err_g(lsu_sbdpu_err_g),
  .lsu_sbapp_err_g(lsu_sbapp_err_g),
  .lsu_sbdiou_err_g(lsu_sbdiou_err_g),
  .lsu_stberr_tid_g(lsu_stberr_tid_g[2:0]),
  .lsu_stberr_index_g(lsu_stberr_index_g[2:0]),
  .lsu_stberr_priv_g(lsu_stberr_priv_g[1:0]),
  .lsu_stb_flush_g(lsu_stb_flush_g),
  .cel_tccp(cel_tccp),
  .cel_tcup(cel_tcup),
  .cel_syndrome(cel_syndrome[7:0]),
  .tlu_tca_tid(tlu_tca_tid[2:0]),
  .tlu_tca_index(tlu_tca_index[1:0]),
  .tlu_tsac(tlu_tsac[7:0]),
  .tlu_tsau(tlu_tsau[7:0]),
  .asi_tsac(asi_tsac),
  .asi_tsau(asi_tsau),
  .asi_tsacu_tid(asi_tsacu_tid[2:0]),
  .tlu_tccd(tlu_tccd[7:0]),
  .tlu_tcud(tlu_tcud[7:0]),
  .tlu_tca_index_0(tlu_tca_index_0[1:0]),
  .tlu_tca_index_1(tlu_tca_index_1[1:0]),
  .tsd_pc_0_w(tsd_pc_0_w[10:5]),
  .tsd_pc_1_w(tsd_pc_1_w[10:5]),
  .fls_flush(fls_flush[7:0]),
  .fls_disrupting_flush_w(fls_disrupting_flush_w[1:0]),
  .trl_gl0(trl_gl0[1:0]),
  .trl_gl1(trl_gl1[1:0]),
  .trl_gl2(trl_gl2[1:0]),
  .trl_gl3(trl_gl3[1:0]),
  .trl_gl4(trl_gl4[1:0]),
  .trl_gl5(trl_gl5[1:0]),
  .trl_gl6(trl_gl6[1:0]),
  .trl_gl7(trl_gl7[1:0]),
  .mmu_asi_cecc(mmu_asi_cecc),
  .mmu_asi_uecc(mmu_asi_uecc),
  .mmu_asi_index(mmu_asi_index[10:0]),
  .mmu_asi_mra_not_sca(mmu_asi_mra_not_sca),
  .mmu_i_l2cerr(mmu_i_l2cerr[7:0]),
  .mmu_d_l2cerr(mmu_d_l2cerr[7:0]),
  .mmu_i_eccerr(mmu_i_eccerr[7:0]),
  .mmu_d_eccerr(mmu_d_eccerr[7:0]),
  .mmu_thr0_err_type(mmu_thr0_err_type[2:0]),
  .mmu_thr1_err_type(mmu_thr1_err_type[2:0]),
  .mmu_thr2_err_type(mmu_thr2_err_type[2:0]),
  .mmu_thr3_err_type(mmu_thr3_err_type[2:0]),
  .mmu_thr4_err_type(mmu_thr4_err_type[2:0]),
  .mmu_thr5_err_type(mmu_thr5_err_type[2:0]),
  .mmu_thr6_err_type(mmu_thr6_err_type[2:0]),
  .mmu_thr7_err_type(mmu_thr7_err_type[2:0]),
  .mmu_thr0_err_index(mmu_thr0_err_index[2:0]),
  .mmu_thr1_err_index(mmu_thr1_err_index[2:0]),
  .mmu_thr2_err_index(mmu_thr2_err_index[2:0]),
  .mmu_thr3_err_index(mmu_thr3_err_index[2:0]),
  .mmu_thr4_err_index(mmu_thr4_err_index[2:0]),
  .mmu_thr5_err_index(mmu_thr5_err_index[2:0]),
  .mmu_thr6_err_index(mmu_thr6_err_index[2:0]),
  .mmu_thr7_err_index(mmu_thr7_err_index[2:0]),
  .spu_tlu_mamu_err_req(spu_tlu_mamu_err_req[10:0]),
  .spu_tlu_ma_int_req(spu_tlu_ma_int_req[2:0]),
  .spu_tlu_cwq_int_req(spu_tlu_cwq_int_req[2:0]),
  .spu_tlu_l2_error(spu_tlu_l2_error[5:0]),
  .cxi_l2_soc_sre(cxi_l2_soc_sre),
  .cxi_l2_soc_err_type(cxi_l2_soc_err_type[1:0]),
  .cxi_l2_soc_tid(cxi_l2_soc_tid[2:0]),
  .cxi_l2_err(cxi_l2_err),
  .cxi_soc_err(cxi_soc_err),
  .asi_rd_isfsr(asi_rd_isfsr),
  .asi_rd_dsfsr(asi_rd_dsfsr),
  .asi_rd_dsfar(asi_rd_dsfar),
  .asi_rd_desr(asi_rd_desr),
  .asi_rd_fesr(asi_rd_fesr),
  .asi_rd_tid(asi_rd_tid[2:0]),
  .asi_wr_isfsr(asi_wr_isfsr[7:0]),
  .asi_wr_dsfsr(asi_wr_dsfsr[7:0]),
  .dfd_desr_f(dfd_desr_f[7:0]),
  .dfd_desr_s(dfd_desr_s[7:0]),
  .dfd_fesr_f(dfd_fesr_f[7:0]),
  .dfd_fesr_priv_0(dfd_fesr_priv_0[1:0]),
  .dfd_fesr_priv_1(dfd_fesr_priv_1[1:0]),
  .dfd_fesr_priv_2(dfd_fesr_priv_2[1:0]),
  .dfd_fesr_priv_3(dfd_fesr_priv_3[1:0]),
  .dfd_fesr_priv_4(dfd_fesr_priv_4[1:0]),
  .dfd_fesr_priv_5(dfd_fesr_priv_5[1:0]),
  .dfd_fesr_priv_6(dfd_fesr_priv_6[1:0]),
  .dfd_fesr_priv_7(dfd_fesr_priv_7[1:0]),
  .ras_asi_data(ras_asi_data[3:0]),
  .ras_dsfar_0(ras_dsfar_0[19:0]),
  .ras_dsfar_1(ras_dsfar_1[19:0]),
  .ras_dsfar_2(ras_dsfar_2[19:0]),
  .ras_dsfar_3(ras_dsfar_3[19:0]),
  .ras_dsfar_4(ras_dsfar_4[19:0]),
  .ras_dsfar_5(ras_dsfar_5[19:0]),
  .ras_dsfar_6(ras_dsfar_6[19:0]),
  .ras_dsfar_7(ras_dsfar_7[19:0]),
  .ras_dsfar_sel_lsu_va(ras_dsfar_sel_lsu_va[7:0]),
  .ras_dsfar_sel_ras(ras_dsfar_sel_ras[7:0]),
  .ras_dsfar_sel_tsa(ras_dsfar_sel_tsa[7:0]),
  .ras_rd_dsfar(ras_rd_dsfar[7:0]),
  .ras_desr_et_0(ras_desr_et_0[61:56]),
  .ras_desr_et_1(ras_desr_et_1[61:56]),
  .ras_desr_et_2(ras_desr_et_2[61:56]),
  .ras_desr_et_3(ras_desr_et_3[61:56]),
  .ras_desr_et_4(ras_desr_et_4[61:56]),
  .ras_desr_et_5(ras_desr_et_5[61:56]),
  .ras_desr_et_6(ras_desr_et_6[61:56]),
  .ras_desr_et_7(ras_desr_et_7[61:56]),
  .ras_desr_ea_0(ras_desr_ea_0[10:0]),
  .ras_desr_ea_1(ras_desr_ea_1[10:0]),
  .ras_desr_ea_2(ras_desr_ea_2[10:0]),
  .ras_desr_ea_3(ras_desr_ea_3[10:0]),
  .ras_desr_ea_4(ras_desr_ea_4[10:0]),
  .ras_desr_ea_5(ras_desr_ea_5[10:0]),
  .ras_desr_ea_6(ras_desr_ea_6[10:0]),
  .ras_desr_ea_7(ras_desr_ea_7[10:0]),
  .ras_desr_me_0(ras_desr_me_0),
  .ras_desr_me_1(ras_desr_me_1),
  .ras_desr_me_2(ras_desr_me_2),
  .ras_desr_me_3(ras_desr_me_3),
  .ras_desr_me_4(ras_desr_me_4),
  .ras_desr_me_5(ras_desr_me_5),
  .ras_desr_me_6(ras_desr_me_6),
  .ras_desr_me_7(ras_desr_me_7),
  .ras_desr_en(ras_desr_en[7:0]),
  .ras_write_desr_1st(ras_write_desr_1st[7:0]),
  .ras_write_desr_2nd(ras_write_desr_2nd[7:0]),
  .ras_rd_desr(ras_rd_desr[7:0]),
  .ras_fesr_et_0(ras_fesr_et_0[61:60]),
  .ras_fesr_et_1(ras_fesr_et_1[61:60]),
  .ras_fesr_et_2(ras_fesr_et_2[61:60]),
  .ras_fesr_et_3(ras_fesr_et_3[61:60]),
  .ras_fesr_et_4(ras_fesr_et_4[61:60]),
  .ras_fesr_et_5(ras_fesr_et_5[61:60]),
  .ras_fesr_et_6(ras_fesr_et_6[61:60]),
  .ras_fesr_et_7(ras_fesr_et_7[61:60]),
  .ras_fesr_ea_0(ras_fesr_ea_0[59:55]),
  .ras_fesr_ea_1(ras_fesr_ea_1[59:55]),
  .ras_fesr_ea_2(ras_fesr_ea_2[59:55]),
  .ras_fesr_ea_3(ras_fesr_ea_3[59:55]),
  .ras_fesr_ea_4(ras_fesr_ea_4[59:55]),
  .ras_fesr_ea_5(ras_fesr_ea_5[59:55]),
  .ras_fesr_ea_6(ras_fesr_ea_6[59:55]),
  .ras_fesr_ea_7(ras_fesr_ea_7[59:55]),
  .ras_fesr_en(ras_fesr_en[7:0]),
  .ras_write_fesr(ras_write_fesr[7:0]),
  .ras_fesr_priv(ras_fesr_priv[59:58]),
  .ras_update_priv(ras_update_priv[7:0]),
  .ras_rd_fesr(ras_rd_fesr[7:0]),
  .ras_precise_error(ras_precise_error[7:0]),
  .ras_disrupting_error(ras_disrupting_error[7:0]),
  .ras_deferred_error(ras_deferred_error[7:0])
);

tlu_dfd_dp dfd ( 
	.wmr_scan_in(dfd_wmr_scanin),
	.wmr_scan_out(dfd_wmr_scanout),
	.scan_in(dfd_scanin),
	.scan_out(dfd_scanout),
	.l2clk			(l2clk			       	),
	.asi_wr_data		(cth_wr_data		[61:0]	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_scan_en_wmr(tcu_scan_en_wmr),
  .spc_aclk_wmr(spc_aclk_wmr),
  .lsu_va_b(lsu_va_b[47:0]),
  .pct0_target_b(pct0_target_b[47:2]),
  .pct1_target_b(pct1_target_b[47:2]),
  .tic_exu_address0_b(tic_exu_address0_b[1:0]),
  .tic_exu_address1_b(tic_exu_address1_b[1:0]),
  .fls0_dfd_lsu_inst_b(fls0_dfd_lsu_inst_b),
  .fls1_dfd_lsu_inst_b(fls1_dfd_lsu_inst_b),
  .tel0_syndrome(tel0_syndrome[15:0]),
  .tel1_syndrome(tel1_syndrome[15:0]),
  .tlu_tsa_index_0(tlu_tsa_index_0[2:0]),
  .tlu_tsa_index_1(tlu_tsa_index_1[2:0]),
  .ras_dsfar_0(ras_dsfar_0[19:0]),
  .ras_dsfar_1(ras_dsfar_1[19:0]),
  .ras_dsfar_2(ras_dsfar_2[19:0]),
  .ras_dsfar_3(ras_dsfar_3[19:0]),
  .ras_dsfar_4(ras_dsfar_4[19:0]),
  .ras_dsfar_5(ras_dsfar_5[19:0]),
  .ras_dsfar_6(ras_dsfar_6[19:0]),
  .ras_dsfar_7(ras_dsfar_7[19:0]),
  .ras_dsfar_sel_lsu_va(ras_dsfar_sel_lsu_va[7:0]),
  .ras_dsfar_sel_ras(ras_dsfar_sel_ras[7:0]),
  .ras_dsfar_sel_tsa(ras_dsfar_sel_tsa[7:0]),
  .ras_desr_et_0(ras_desr_et_0[61:56]),
  .ras_desr_et_1(ras_desr_et_1[61:56]),
  .ras_desr_et_2(ras_desr_et_2[61:56]),
  .ras_desr_et_3(ras_desr_et_3[61:56]),
  .ras_desr_et_4(ras_desr_et_4[61:56]),
  .ras_desr_et_5(ras_desr_et_5[61:56]),
  .ras_desr_et_6(ras_desr_et_6[61:56]),
  .ras_desr_et_7(ras_desr_et_7[61:56]),
  .ras_desr_ea_0(ras_desr_ea_0[10:0]),
  .ras_desr_ea_1(ras_desr_ea_1[10:0]),
  .ras_desr_ea_2(ras_desr_ea_2[10:0]),
  .ras_desr_ea_3(ras_desr_ea_3[10:0]),
  .ras_desr_ea_4(ras_desr_ea_4[10:0]),
  .ras_desr_ea_5(ras_desr_ea_5[10:0]),
  .ras_desr_ea_6(ras_desr_ea_6[10:0]),
  .ras_desr_ea_7(ras_desr_ea_7[10:0]),
  .ras_desr_me_0(ras_desr_me_0),
  .ras_desr_me_1(ras_desr_me_1),
  .ras_desr_me_2(ras_desr_me_2),
  .ras_desr_me_3(ras_desr_me_3),
  .ras_desr_me_4(ras_desr_me_4),
  .ras_desr_me_5(ras_desr_me_5),
  .ras_desr_me_6(ras_desr_me_6),
  .ras_desr_me_7(ras_desr_me_7),
  .ras_desr_en(ras_desr_en[7:0]),
  .ras_write_desr_1st(ras_write_desr_1st[7:0]),
  .ras_write_desr_2nd(ras_write_desr_2nd[7:0]),
  .ras_fesr_et_0(ras_fesr_et_0[61:60]),
  .ras_fesr_et_1(ras_fesr_et_1[61:60]),
  .ras_fesr_et_2(ras_fesr_et_2[61:60]),
  .ras_fesr_et_3(ras_fesr_et_3[61:60]),
  .ras_fesr_et_4(ras_fesr_et_4[61:60]),
  .ras_fesr_et_5(ras_fesr_et_5[61:60]),
  .ras_fesr_et_6(ras_fesr_et_6[61:60]),
  .ras_fesr_et_7(ras_fesr_et_7[61:60]),
  .ras_fesr_ea_0(ras_fesr_ea_0[59:55]),
  .ras_fesr_ea_1(ras_fesr_ea_1[59:55]),
  .ras_fesr_ea_2(ras_fesr_ea_2[59:55]),
  .ras_fesr_ea_3(ras_fesr_ea_3[59:55]),
  .ras_fesr_ea_4(ras_fesr_ea_4[59:55]),
  .ras_fesr_ea_5(ras_fesr_ea_5[59:55]),
  .ras_fesr_ea_6(ras_fesr_ea_6[59:55]),
  .ras_fesr_ea_7(ras_fesr_ea_7[59:55]),
  .ras_fesr_en(ras_fesr_en[7:0]),
  .ras_write_fesr(ras_write_fesr[7:0]),
  .ras_fesr_priv(ras_fesr_priv[59:58]),
  .ras_update_priv(ras_update_priv[7:0]),
  .ras_asi_data(ras_asi_data[3:0]),
  .ras_rd_dsfar(ras_rd_dsfar[7:0]),
  .ras_rd_desr(ras_rd_desr[7:0]),
  .ras_rd_fesr(ras_rd_fesr[7:0]),
  .asi_wr_dsfar(asi_wr_dsfar[7:0]),
  .dfd_desr_f(dfd_desr_f[7:0]),
  .dfd_desr_s(dfd_desr_s[7:0]),
  .dfd_fls_desr_f(dfd_fls_desr_f[7:0]),
  .dfd_fls_desr_s(dfd_fls_desr_s[7:0]),
  .dfd_fesr_f(dfd_fesr_f[7:0]),
  .dfd_fesr_priv_0(dfd_fesr_priv_0[1:0]),
  .dfd_fesr_priv_1(dfd_fesr_priv_1[1:0]),
  .dfd_fesr_priv_2(dfd_fesr_priv_2[1:0]),
  .dfd_fesr_priv_3(dfd_fesr_priv_3[1:0]),
  .dfd_fesr_priv_4(dfd_fesr_priv_4[1:0]),
  .dfd_fesr_priv_5(dfd_fesr_priv_5[1:0]),
  .dfd_fesr_priv_6(dfd_fesr_priv_6[1:0]),
  .dfd_fesr_priv_7(dfd_fesr_priv_7[1:0]),
  .dfd_asi_data(dfd_asi_data[47:0]),
  .dfd_asi_desr(dfd_asi_desr[18:0])
);


////////////////////////////////////////////////////////////////////////////////
// Debug 

// Freerunning domain
tlu_sse_dp sse (
	.scan_in(sse_scanin),
	.scan_out(sse_scanout),
	.l2clk			(l2clk			       	),
  .tcu_pce_ov(tcu_pce_ov),
  .spc_aclk(spc_aclk),
  .spc_bclk(spc_bclk),
  .tcu_scan_en(tcu_scan_en),
  .tcu_shscan_clk_stop(tcu_shscan_clk_stop),
  .trl1_shscanid_2(trl1_shscanid_2),
  .fls_ss_update_pc_w(fls_ss_update_pc_w[1:0]),
  .pct0_shadow_pc_d(pct0_shadow_pc_d[47:2]),
  .pct1_shadow_pc_d(pct1_shadow_pc_d[47:2]),
  .fls0_spc_hardstop_request(fls0_spc_hardstop_request),
  .fls0_spc_softstop_request(fls0_spc_softstop_request),
  .fls0_spc_trigger_pulse(fls0_spc_trigger_pulse),
  .fls1_spc_hardstop_request(fls1_spc_hardstop_request),
  .fls1_spc_softstop_request(fls1_spc_softstop_request),
  .fls1_spc_trigger_pulse(fls1_spc_trigger_pulse),
  .sse_shscan_clk_stop(sse_shscan_clk_stop),
  .sse_shadow_pc(sse_shadow_pc[47:2]),
  .tlu_hardstop_request(tlu_hardstop_request),
  .tlu_softstop_request(tlu_softstop_request),
  .tlu_trigger_pulse(tlu_trigger_pulse)
);

// Shadow scan domain
assign shscan_l2clk = l2clk; 
tlu_ssd_dp ssd (.shscan_l2clk(shscan_l2clk),
  .tcu_shscan_scan_in(tcu_shscan_scan_in),
  .tcu_shscan_pce_ov(tcu_shscan_pce_ov),
  .tcu_shscan_aclk(tcu_shscan_aclk),
  .tcu_shscan_bclk(tcu_shscan_bclk),
  .tcu_shscan_scan_en(tcu_shscan_scan_en),
  .trl1_shscanid_2(trl1_shscanid_2),
  .sse_shscan_clk_stop(sse_shscan_clk_stop),
  .sse_shadow_pc(sse_shadow_pc[47:2]),
  .tsd0_shadow_pstate(tsd0_shadow_pstate[10:0]),
  .tsd1_shadow_pstate(tsd1_shadow_pstate[10:0]),
  .tsd0_shadow_tpc(tsd0_shadow_tpc[47:2]),
  .tsd1_shadow_tpc(tsd1_shadow_tpc[47:2]),
  .tsd0_shadow_tt(tsd0_shadow_tt[8:0]),
  .tsd1_shadow_tt(tsd1_shadow_tt[8:0]),
  .trl0_shadow_tl(trl0_shadow_tl[2:0]),
  .trl1_shadow_tl(trl1_shadow_tl[2:0]),
  .trl0_tl_for_tt(trl0_tl_for_tt[2:0]),
  .trl1_tl_for_tt(trl1_tl_for_tt[2:0]),
  .spc_shscan_scan_out(spc_shscan_scan_out)
);


////////////////////////////////////////////////////////////////////////////////
// MBIST

tlu_mbd_dp mbd(
  .asi_mbd_compare_data(asi_mbd_compare_data[7:0]),
  .asi_mbd_sel_tsd0(asi_mbd_sel_tsd0),
  .asi_mbd_sel_tsd1(asi_mbd_sel_tsd1),
  .asi_mbd_sel_tic(asi_mbd_sel_tic),
  .tic_mbist_data(tic_mbist_data[31:0]),
  .tsd0_mbist_data(tsd0_mbist_data[31:0]),
  .tsd1_mbist_data(tsd1_mbist_data[31:0]),
  .tlu_pc_0_prebuf_d(tlu_pc_0_prebuf_d[47:2]),
  .mbd_compare(mbd_compare),
  .tlu_pc_0_d(tlu_pc_0_d[47:2]));


////////////////////////////////////////////////////////////////////////////////
// Scan patch panel
// fixscan start:
assign fls0_scanin               = scan_in                  ;
assign fls1_scanin               = fls0_scanout             ;
assign pct0_scanin               = fls1_scanout             ;
assign pct1_scanin               = pct0_scanout             ;
assign cxi_scanin                = pct1_scanout             ;
assign cth_scanin                = cxi_scanout              ;
assign trl0_scanin               = cth_scanout              ;
assign trl1_scanin               = trl0_scanout             ;
assign tel0_scanin               = trl1_scanout             ;
assign tsa0_scanin               = tel0_scanout             ;
assign tel1_scanin               = tsa0_scanout             ;
assign tsa1_scanin               = tel1_scanout             ;
assign tsd0_scanin               = tsa1_scanout             ;
assign tsd1_scanin               = tsd0_scanout             ;
assign asi_scanin                = tsd1_scanout             ;
assign tic_scanin                = asi_scanout              ;
assign tca_scanin                = tic_scanout              ;
assign cep_scanin                = tca_scanout              ;
assign cel_scanin                = cep_scanout              ;
assign cer_scanin                = cel_scanout              ;
assign ras_scanin                = cer_scanout              ;
assign dfd_scanin                = ras_scanout              ;
assign sse_scanin                = dfd_scanout              ;
assign scan_out                  = sse_scanout              ;

assign fls0_wmr_scanin           = wmr_scan_in              ;
assign fls1_wmr_scanin           = fls0_wmr_scanout         ;
assign pct0_wmr_scanin           = fls1_wmr_scanout         ;
assign pct1_wmr_scanin           = pct0_wmr_scanout         ;
assign cth_wmr_scanin            = pct1_wmr_scanout         ;
assign trl0_wmr_scanin           = cth_wmr_scanout          ;
assign trl1_wmr_scanin           = trl0_wmr_scanout         ;
assign tsd0_wmr_scanin           = trl1_wmr_scanout         ;
assign tsd1_wmr_scanin           = tsd0_wmr_scanout         ;
assign asi_wmr_scanin            = tsd1_wmr_scanout         ;
assign ras_wmr_scanin            = asi_wmr_scanout          ;
assign dfd_wmr_scanin            = ras_wmr_scanout          ;
assign wmr_scan_out              = dfd_wmr_scanout          ;
// fixscan end:
endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_asi_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  tlu_asi_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lsu_asi_clken, 
  lsu_tlu_pmen, 
  mbi_tsa0_write_en, 
  mbi_tsa1_write_en, 
  mbi_tca_write_en, 
  mbi_addr, 
  mbi_run, 
  mbi_wdata, 
  mbi_tsa0_read_en, 
  mbi_tsa1_read_en, 
  mbi_tca_read_en, 
  mbi_tlu_cmpsel, 
  mbd_compare, 
  error_inject_enable, 
  error_inject_tccu, 
  error_inject_tsau, 
  error_inject_mask, 
  lsu_rngf_cdbus, 
  pct0_asi_data, 
  pct1_asi_data, 
  trl0_asi_data, 
  trl1_asi_data, 
  tlu_ceter_pscce, 
  tsd_hpstate_hpriv, 
  tsd_pstate_priv, 
  tsd0_asi_data, 
  tsd1_asi_data, 
  tel0_ecc, 
  tel0_tsac, 
  tel0_tsau, 
  tel1_ecc, 
  tel1_tsac, 
  tel1_tsau, 
  tic_asi_data, 
  cel_ecc, 
  cer_asi_data, 
  cel_tccp, 
  cel_tcup, 
  mmu_asi_data, 
  mmu_asi_read, 
  mmu_asi_cecc, 
  mmu_asi_uecc, 
  dfd_desr_f, 
  dfd_fesr_f, 
  tlu_lsu_clear_ctl_reg_, 
  hver_mask_major_rev, 
  hver_mask_minor_rev, 
  wmr_scan_out, 
  scan_out, 
  asi_error_tccu, 
  asi_error_tsau, 
  asi_error_mask, 
  asi_tsa_rd_addr, 
  asi_tsa_rd_iqr_ecc, 
  asi_tsa_tid, 
  asi_rd_asireg, 
  asi_wr_asireg, 
  asi_rd_tick, 
  asi_wr_tick, 
  asi_rd_pc, 
  asi_wr_set_softint, 
  asi_wr_clear_softint, 
  asi_rd_softint, 
  asi_wr_softint, 
  asi_tca_addr, 
  asi_tca_addr_valid, 
  asi_tca_wr, 
  asi_wr_mondo_head, 
  asi_wr_mondo_tail, 
  asi_wr_device_head, 
  asi_wr_device_tail, 
  asi_wr_res_err_head, 
  asi_wr_res_err_tail, 
  asi_wr_nonres_err_head, 
  asi_wr_nonres_err_tail, 
  asi_rd_iqr_reg, 
  asi_rd_iqr, 
  asi_rd_tpc, 
  asi_wr_tpc, 
  asi_rd_tnpc, 
  asi_wr_tnpc, 
  asi_rd_tstate, 
  asi_wr_tstate, 
  asi_rd_tt, 
  asi_wr_tt, 
  asi_wr_tba, 
  asi_wr_pstate, 
  asi_rd_tl, 
  asi_wr_tl, 
  asi_rd_pil, 
  asi_wr_pil, 
  asi_rd_gl, 
  asi_wr_gl, 
  asi_wr_hpstate, 
  asi_rd_htstate, 
  asi_wr_htstate, 
  asi_rd_hintp, 
  asi_wr_hintp, 
  asi_wr_htba, 
  asi_rd_h_pstate_tba, 
  asi_rd_tba_htba, 
  asi_rd_pstate_hpstate, 
  asi_preempt_trap, 
  asi_preempt_done_retry, 
  asi_rmw_tsa, 
  asi_wr_int_rec, 
  asi_wr_any_int_rec, 
  asi_rd_inc_vec_2, 
  asi_int_rec_mux_sel_in, 
  asi_rd_int_rec, 
  asi_rd_inc_vec, 
  asi_check_qr_exc, 
  asi_tca_wr_data_63, 
  asi_wr_data_0, 
  asi_wr_data_1, 
  asi_tsd0_wr_data_12, 
  asi_tsd0_wr_data_10_08, 
  asi_tsd0_wr_data_05_00, 
  asi_tsd1_wr_data_12, 
  asi_tsd1_wr_data_10_08, 
  asi_tsd1_wr_data_05_00, 
  asi_tsa_wr_data, 
  asi_tsa_wr_data_npc_oor_va, 
  asi_tsa_wr_data_npc_nonseq, 
  asi_rd_cerer, 
  asi_rd_ceter, 
  asi_wr_cerer, 
  asi_ceter_tid, 
  asi_wr_ceter, 
  asi_rd_tid, 
  asi_rd_isfsr, 
  asi_rd_dsfsr, 
  asi_rd_dsfar, 
  asi_rd_desr, 
  asi_rd_fesr, 
  asi_wr_isfsr, 
  asi_wr_dsfsr, 
  asi_wr_dsfar, 
  asi_rd_iaw, 
  asi_wr_iaw, 
  asi_decr, 
  asi_ece_exc, 
  asi_eue_exc, 
  asi_ecc_tid, 
  asi_tsac, 
  asi_tsau, 
  asi_tsacu, 
  asi_tsacu_tid, 
  asi_irl_cleared, 
  asi_rd_stage_1, 
  asi_trl_pstate_en, 
  asi_stg1_en, 
  asi_mbist_ecc_in, 
  asi_mbist_tsa_ecc_in, 
  asi_mbist_run, 
  asi_mbist_cmpsel, 
  asi_mbd_compare_data, 
  asi_mbd_sel_tsd0, 
  asi_mbd_sel_tsd1, 
  asi_mbd_sel_tic, 
  asi_mbist_addr, 
  asi_mbist_tsa_rd_en, 
  asi_mbist_tsa_wr_en, 
  asi_mbist_tel_en, 
  asi_tccup_in, 
  asi_tccud_in, 
  asi_immu_enable, 
  asi_spec_enable, 
  asi_halt, 
  asi_clear_spu_trap_req, 
  tlu_spec_enable, 
  tlu_tca_tid, 
  tlu_tca_index, 
  tlu_mbi_tsa0_fail, 
  tlu_mbi_tsa1_fail, 
  tlu_mbi_tca_fail, 
  tlu_rngf_cdbus, 
  tlu_rngf_cdbus_error);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire pmen_lat_scanin;
wire pmen_lat_scanout;
wire pmen;
wire stg1_en_in;
wire stg1_en_lat_scanin;
wire stg1_en_lat_scanout;
wire stg1_en;
wire stg2_en_in;
wire stg2_en;
wire stg2_en_lat_scanin;
wire stg2_en_lat_scanout;
wire stg3_en_lat_scanin;
wire stg3_en_lat_scanout;
wire stg3_en;
wire stg4_en_lat_scanin;
wire stg4_en_lat_scanout;
wire pstg4_en;
wire stg4_en;
wire [64:0] data_4;
wire pm1_en;
wire mbist_run;
wire l1clk_pm1;
wire pm2_en;
wire l1clk_pm2;
wire mbist_run_lat_scanin;
wire mbist_run_lat_scanout;
wire mbist_tsa0_write_lat_scanin;
wire mbist_tsa0_write_lat_scanout;
wire mbist_tsa0_wr_en;
wire mbist_tsa1_write_lat_scanin;
wire mbist_tsa1_write_lat_scanout;
wire mbist_tsa1_wr_en;
wire mbist_tca_write_lat_scanin;
wire mbist_tca_write_lat_scanout;
wire mbist_tca_wr_en;
wire mbist_addr_lat_scanin;
wire mbist_addr_lat_scanout;
wire [4:0] mbist_addr;
wire [7:0] mbist_wdata;
wire [63:0] data_1;
wire mbist_tsa0_read_lat_scanin;
wire mbist_tsa0_read_lat_scanout;
wire mbist_tsa0_rd_en;
wire mbist_tsa1_read_lat_scanin;
wire mbist_tsa1_read_lat_scanout;
wire mbist_tsa1_rd_en;
wire mbist_tca_read_lat_scanin;
wire mbist_tca_read_lat_scanout;
wire mbist_tca_rd_en;
wire mbist_cmpsel_lat_scanin;
wire mbist_cmpsel_lat_scanout;
wire [3:0] mbist_cmpsel;
wire [7:0] mbist_wdata_2;
wire mbist_tsa1_rd_en_2;
wire mbist_tsa0_rd_en_2;
wire mbist_addr_2_lat_scanin;
wire mbist_addr_2_lat_scanout;
wire [4:0] mbist_addr_2;
wire mbist_tsa0_read_2_lat_scanin;
wire mbist_tsa0_read_2_lat_scanout;
wire mbist_tsa1_read_2_lat_scanin;
wire mbist_tsa1_read_2_lat_scanout;
wire mbist_tca_read_2_lat_scanin;
wire mbist_tca_read_2_lat_scanout;
wire mbist_tca_rd_en_2;
wire mbist_cmpsel_2_lat_scanin;
wire mbist_cmpsel_2_lat_scanout;
wire [3:0] mbist_cmpsel_2;
wire mbist_wdata_2_lat_scanin;
wire mbist_wdata_2_lat_scanout;
wire mbist_tsa0_read_3_lat_scanin;
wire mbist_tsa0_read_3_lat_scanout;
wire mbist_tsa0_rd_en_3;
wire mbist_tsa1_read_3_lat_scanin;
wire mbist_tsa1_read_3_lat_scanout;
wire mbist_tsa1_rd_en_3;
wire mbist_tca_read_3_lat_scanin;
wire mbist_tca_read_3_lat_scanout;
wire mbist_tca_rd_en_3;
wire mbist_wdata_3_lat_scanin;
wire mbist_wdata_3_lat_scanout;
wire [7:0] mbist_wdata_3;
wire rd_tsa_pc_2;
wire rd_tsa_nopc_2;
wire rd_tsa_ecc_2;
wire rd_tsa_pc_3;
wire rd_tsa_nopc_3;
wire rd_tsa_ecc_3;
wire wr_tsa_2;
wire wr_tsa_3;
wire mbist_tsa0_read_4_lat_scanin;
wire mbist_tsa0_read_4_lat_scanout;
wire mbist_tsa0_rd_en_4;
wire mbist_tsa1_read_4_lat_scanin;
wire mbist_tsa1_read_4_lat_scanout;
wire mbist_tsa1_rd_en_4;
wire [7:0] compare_data_in;
wire mbist_tsa_3;
wire compare_data_lat_scanin;
wire compare_data_lat_scanout;
wire [7:0] compare_data;
wire tsa0_fail_in;
wire tsa1_fail_in;
wire tca_fail_in;
wire tsa0_fail_lat_scanin;
wire tsa0_fail_lat_scanout;
wire tsa0_fail;
wire tsa1_fail_lat_scanin;
wire tsa1_fail_lat_scanout;
wire tsa1_fail;
wire tca_fail_lat_scanin;
wire tca_fail_lat_scanout;
wire tca_fail;
wire compare_lat_scanin;
wire compare_lat_scanout;
wire compare;
wire ctl_0;
wire [63:48] data_0;
wire data_0_59_unused;
wire data_0_57_unused;
wire data_0_56_unused;
wire asi_0;
wire pr_0;
wire hpr_0;
wire pr_tstack_0;
wire wr_gl_0;
wire htstate_0;
wire asi_25_0;
wire tsa_diag_0;
wire [1:0] preempt_done_retry_in;
wire [1:0] preempt_trap_in;
wire wr_gl_2;
wire [63:0] data_2;
wire preempt_trap_lat_scanin;
wire preempt_trap_lat_scanout;
wire [1:0] preempt_trap;
wire [1:0] preempt_done_retry;
wire sel_lsu;
wire rd_clesr;
wire rd_clfesr;
wire [63:0] clesr_data;
wire [63:0] clfesr_in;
wire [63:48] clfesr_data;
wire clfesr_lat_wmr_scanin;
wire clfesr_lat_wmr_scanout;
wire [63:0] data_1_in;
wire rng_stg1_data_scanin;
wire rng_stg1_data_scanout;
wire ctl_1_lat_scanin;
wire ctl_1_lat_scanout;
wire ctl_1;
wire rd_stage_1;
wire hpstatehpriv_lat_scanin;
wire hpstatehpriv_lat_scanout;
wire [7:0] hpstatehpriv;
wire pstatepriv_lat_scanin;
wire pstatepriv_lat_scanout;
wire [7:0] pstatepriv;
wire hpstate_hpriv;
wire [7:0] rd_tid_dec;
wire pstate_priv;
wire asi;
wire asr;
wire pr;
wire hpr;
wire asi_2;
wire ctl_2;
wire asr_2;
wire pr_2;
wire hpr_2;
wire fast_asi;
wire superfast_hpr_2;
wire mondo_head;
wire rd_mondo_head;
wire wr_mondo_head;
wire mondo_tail;
wire rd_mondo_tail;
wire wr_mondo_tail;
wire device_head;
wire rd_device_head;
wire wr_device_head;
wire device_tail;
wire rd_device_tail;
wire wr_device_tail;
wire res_err_head;
wire rd_res_err_head;
wire wr_res_err_head;
wire res_err_tail;
wire rd_res_err_tail;
wire wr_res_err_tail;
wire nonres_err_head;
wire rd_nonres_err_head;
wire wr_nonres_err_head;
wire nonres_err_tail;
wire rd_nonres_err_tail;
wire wr_nonres_err_tail;
wire lsu_ctl;
wire wr_lsu_ctl;
wire decr;
wire rd_decr;
wire wr_decr;
wire esr;
wire desr;
wire rd_desr;
wire fesr;
wire rd_fesr;
wire clesr;
wire clfesr;
wire cerer;
wire rd_cerer;
wire wr_cerer;
wire ceter;
wire rd_ceter;
wire wr_ceter;
wire isfsr;
wire rd_isfsr;
wire wr_isfsr;
wire iaw_2;
wire rd_iaw_2;
wire wr_iaw_2;
wire dsfsr;
wire rd_dsfsr;
wire wr_dsfsr;
wire dsfar;
wire rd_dsfar;
wire wr_dsfar;
wire tca_diag;
wire rd_tca_ecc;
wire rd_tca_data;
wire tsa_diag;
wire rd_tsa_ecc;
wire int_rec;
wire rd_int_rec;
wire wr_int_rec;
wire inc_vec;
wire rd_inc_vec;
wire asireg_2;
wire rd_asireg_2;
wire wr_asireg_2;
wire tick;
wire rd_tick;
wire tick_npt_1_;
wire priv_action;
wire wr_tick;
wire [7:0] tick_npt_;
wire pc_2;
wire rd_pc_2;
wire set_softint;
wire wr_set_softint;
wire clear_softint;
wire wr_clear_softint;
wire softint;
wire rd_softint;
wire wr_softint;
wire tick_cmpr;
wire rd_tick_cmpr;
wire wr_tick_cmpr;
wire stick_cmpr;
wire rd_stick_cmpr;
wire wr_stick_cmpr;
wire tpc;
wire rd_tpc;
wire wr_tpc;
wire tnpc;
wire rd_tnpc;
wire wr_tnpc;
wire tstate;
wire rd_tstate;
wire wr_tstate;
wire tt;
wire rd_tt;
wire wr_tt;
wire tba_2;
wire rd_tba_2;
wire wr_tba_2;
wire pstate;
wire wr_pstate;
wire pstate_2;
wire rd_pstate_2;
wire tl;
wire rd_tl;
wire wr_tl;
wire pil;
wire rd_pil;
wire wr_pil;
wire gl;
wire rd_gl;
wire wr_gl;
wire hpstate;
wire wr_hpstate;
wire hpstate_2;
wire rd_hpstate_2;
wire htstate;
wire rd_htstate;
wire wr_htstate;
wire hintp;
wire rd_hintp;
wire wr_hintp;
wire htba_2;
wire rd_htba_2;
wire wr_htba_2;
wire hver;
wire rd_hver;
wire rd_halt;
wire wr_halt;
wire hstick_cmpr;
wire rd_hstick_cmpr;
wire wr_hstick_cmpr;
wire fast_tsa_rd_iqr;
wire fast_rd_tsa_ecc;
wire fast_tsa_rd_iqr_res_nonres;
wire rd_tca;
wire wr_tca;
wire [4:3] tca_rd_addr;
wire [4:0] tca_addr;
wire wr_hstick_cmpr_2;
wire wr_stick_cmpr_2;
wire wr_tca_2;
wire rd_tsa_nopc;
wire rd_tsa_pc;
wire wr_tstate_2;
wire wr_tt_2;
wire wr_htstate_2;
wire wr_mondo_head_2;
wire wr_mondo_tail_2;
wire wr_device_head_2;
wire wr_device_tail_2;
wire wr_res_err_head_2;
wire wr_res_err_tail_2;
wire wr_nonres_err_head_2;
wire wr_nonres_err_tail_2;
wire wr_tpc_2;
wire wr_tnpc_2;
wire wr_tstate_3;
wire wr_tt_3;
wire wr_htstate_3;
wire wr_mondo_head_3;
wire wr_mondo_tail_3;
wire wr_device_head_3;
wire wr_device_tail_3;
wire wr_res_err_head_3;
wire wr_res_err_tail_3;
wire wr_nonres_err_head_3;
wire wr_nonres_err_tail_3;
wire wr_tpc_3;
wire wr_tnpc_3;
wire [2:0] rd_iqr_2;
wire rd_device_head_2;
wire rd_nonres_err_head_2;
wire rd_mondo_tail_2;
wire rd_res_err_tail_2;
wire rd_device_tail_2;
wire rd_nonres_err_tail_2;
wire rd_iqr_reg_2;
wire rd_res_err_head_2;
wire rd_mondo_head_2;
wire rd_tpc_2;
wire rd_tnpc_2;
wire rd_tstate_2;
wire rd_tt_2;
wire rd_htstate_2;
wire rd_cerer_2;
wire rd_ceter_2;
wire rd_inc_vec_2;
wire [7:0] wr_tid_dec;
wire rd_tick_3;
wire rd_cth;
wire rd_trl;
wire rd_tic;
wire rd_tsd_2;
wire rd_tba_htba_2;
wire [1:0] rmw_tsa_in;
wire [63:0] hver_value;
wire [63:0] tic_ecc;
wire [63:0] data_err_1;
wire [63:0] decr_data;
wire [63:46] decr_reg;
wire [63:0] dsfar_data;
wire [63:0] fesr_data;
wire [63:0] desr_data;
wire [63:0] isfsr_data;
wire [63:0] dsfsr_data;
wire sel_data1;
wire rd_hver_2;
wire rd_cth_2;
wire rd_tca_ecc_2;
wire rd_tca_data_2;
wire rd_desr_2;
wire rd_fesr_2;
wire rd_dsfar_2;
wire rd_isfsr_2;
wire rd_dsfsr_2;
wire rd_decr_2;
wire [63:0] data_2_in;
wire [64:0] tic_data;
wire stg2_data_lat_scanin;
wire stg2_data_lat_scanout;
wire stg2_ctl_lat_scanin;
wire stg2_ctl_lat_scanout;
wire rd_tic_2;
wire rd_tick_2;
wire rd_softint_2;
wire rd_tl_2;
wire rd_gl_2;
wire rd_pil_2;
wire rd_hintp_2;
wire rd_trl_2;
wire wr_int_rec_2;
wire wr_tick_2;
wire wr_set_softint_2;
wire wr_clear_softint_2;
wire wr_softint_2;
wire wr_pstate_2;
wire wr_tl_2;
wire wr_pil_2;
wire wr_hpstate_2;
wire wr_hintp_2;
wire wr_cerer_2;
wire wr_ceter_2;
wire wr_isfsr_2;
wire wr_dsfsr_2;
wire wr_dsfar_2;
wire wr_decr_2;
wire wr_lsu_ctl_2;
wire wr_tid_dec_lat_scanin;
wire wr_tid_dec_lat_scanout;
wire [47:0] mbist_tsa_wdata;
wire irl_any_cleared_in;
wire irl_any_cleared_lat_scanin;
wire irl_any_cleared_lat_scanout;
wire irl_any_cleared;
wire [7:0] tid_dec_3;
wire [64:0] data_3;
wire [7:0] tick_npt_in_;
wire tick_npt_inv_lat_scanin;
wire tick_npt_inv_lat_scanout;
wire tick_npt_2_;
wire tick_npt_3_inv_lat_scanin;
wire tick_npt_3_inv_lat_scanout;
wire tick_npt_3_;
wire [63:46] decr_reg_in;
wire decr_lat_scanin;
wire decr_lat_scanout;
wire rd_pct_2;
wire [64:0] trl_data;
wire [64:0] tsd_data;
wire [64:0] tba_htba_data;
wire [64:0] tsa_nopc_data;
wire [64:0] tsa_pc_data;
wire [64:0] tsa_ecc_data;
wire [64:0] tic_data_for_3;
wire [64:0] tick_data;
wire [64:0] pct_data;
wire [64:0] rngf_cdbus_2;
wire no_rd_3;
wire rd_trl_3;
wire rd_tsd_3;
wire rd_tba_htba_3;
wire rd_tic_3;
wire rd_pct_3;
wire [64:0] data_3_in;
wire rd_tca_diag_2;
wire rng_stg3_scanin;
wire rng_stg3_scanout;
wire tsa_wr_lat_scanin;
wire tsa_wr_lat_scanout;
wire rd_tca_diag_3;
wire wr_iqr_3;
wire check_ecc;
wire tsacu_in;
wire kill_write_if_error_in;
wire ecc_lat_scanin;
wire ecc_lat_scanout;
wire ptsacu;
wire kill_write_if_error;
wire tsac;
wire tsau;
wire tca_rd_addr_2_lat_scanin;
wire tca_rd_addr_2_lat_scanout;
wire [4:3] tca_rd_addr_2;
wire tca_rd_addr_3_lat_scanin;
wire tca_rd_addr_3_lat_scanout;
wire [4:3] tca_rd_addr_3;
wire tca_rd_addr_4_lat_scanin;
wire tca_rd_addr_4_lat_scanout;
wire [4:3] tca_rd_addr_4;
wire [64:0] rngf_cdbus_3;
wire [64:0] data_4_in;
wire error_4_in;
wire rng_stg4_scanin;
wire rng_stg4_scanout;
wire error_4_lat_scanin;
wire error_4_lat_scanout;
wire error_4;
wire [3:0] check_qr_exc_in;
wire check_qr_exc_lat_scanin;
wire check_qr_exc_lat_scanout;
wire [3:0] check_qr_exc;
wire error_inject_lat_scanin;
wire error_inject_lat_scanout;
wire error_enable;
wire error_tccu;
wire error_tsau;
wire [7:0] error_mask;
wire [7:0] write_lsu_ctl;
wire [7:0] hold_lsu_ctl;
wire [7:0] spec_enable_in;
wire [7:0] spec_enable;
wire spec_enable_lat_scanin;
wire spec_enable_lat_scanout;
wire [7:0] immu_enable_in;
wire [7:0] immu_enable;
wire immu_enable_lat_scanin;
wire immu_enable_lat_scanout;
wire spares_scanin;
wire spares_scanout;
wire rd_halt_2;
wire wr_halt_2;
wire [6:0] unused;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

input		lsu_asi_clken;		// Power management
input		lsu_tlu_pmen;		// Power management

// MBIST
input		mbi_tsa0_write_en;	// MBIST write control
input		mbi_tsa1_write_en;	// MBIST write control
input		mbi_tca_write_en;	// MBIST write control
input	[4:0]	mbi_addr;		// 32 entry addressability for MBIST
input		mbi_run;		// Select MBIST controls
input	[7:0]	mbi_wdata;		// MBIST write data
input		mbi_tsa0_read_en;	// MBIST read control
input		mbi_tsa1_read_en;	// MBIST read control
input		mbi_tca_read_en;	// MBIST read control
input	[3:0]	mbi_tlu_cmpsel;		// Mux (NPE) between 32 bit chunks 
input		mbd_compare;

input		error_inject_enable;
input		error_inject_tccu;
input		error_inject_tsau;
input	[7:0]	error_inject_mask;

input 	[64:0]	lsu_rngf_cdbus; 	// control/data bus from lsu

input	[48:2]	pct0_asi_data;
input	[48:2]	pct1_asi_data;

input   [16:0]	trl0_asi_data;
input   [16:0]	trl1_asi_data;

input	[7:0]	tlu_ceter_pscce;

input	[7:0]	tsd_hpstate_hpriv;
input	[7:0]	tsd_pstate_priv;
input	[1:0]	tsd0_asi_data;
input	[1:0]	tsd1_asi_data;
input	[15:0]	tel0_ecc;
input		tel0_tsac;
input		tel0_tsau;
input	[15:0]	tel1_ecc;
input		tel1_tsac;
input		tel1_tsau;

input 	[63:0]	tic_asi_data;
input	[7:0] cel_ecc;

input	[63:0]	cer_asi_data;

input		cel_tccp;
input		cel_tcup;

input	[64:0]	mmu_asi_data;		// ASI read data for fast bus
input		mmu_asi_read;		// Valid for MMU ASI read
input		mmu_asi_cecc;		// Correctable ECC error (stg 4)
input		mmu_asi_uecc;		// Uncorrectable ECC error (stg 4)

input	[7:0]	dfd_desr_f;
input	[7:0]	dfd_fesr_f;

input 	[7:0]	tlu_lsu_clear_ctl_reg_;

input	[3:0]	hver_mask_major_rev;	// An input to asi
input	[3:0]	hver_mask_minor_rev;	// An input to spc


output		wmr_scan_out;

output		scan_out;

output		asi_error_tccu;
output		asi_error_tsau;
output	[7:0]	asi_error_mask;

output	[4:0]	asi_tsa_rd_addr;
output		asi_tsa_rd_iqr_ecc;
output	[1:0]	asi_tsa_tid;
output	[7:0]	asi_rd_asireg;		
output	[7:0]	asi_wr_asireg;		
output		asi_rd_tick;		
output		asi_wr_tick;		
output	[7:0]	asi_rd_pc;
output	[7:0]	asi_wr_set_softint;
output	[7:0]	asi_wr_clear_softint;
output	[7:0]	asi_rd_softint;
output	[7:0]	asi_wr_softint;
output	[4:0]	asi_tca_addr;		// Used for [H][S]TICK_CMPR
output		asi_tca_addr_valid;
output		asi_tca_wr;
output	[1:0]	asi_wr_mondo_head;
output	[1:0]	asi_wr_mondo_tail;
output	[1:0]	asi_wr_device_head;
output	[1:0]	asi_wr_device_tail;
output	[1:0]	asi_wr_res_err_head;
output	[1:0]	asi_wr_res_err_tail;
output	[1:0]	asi_wr_nonres_err_head;
output	[1:0]	asi_wr_nonres_err_tail;
output	[1:0]	asi_rd_iqr_reg;
output	[2:0]	asi_rd_iqr;		// Read any interrupt queue reg
output	[1:0]	asi_rd_tpc;		// encoded TID for IQR read
output	[1:0]	asi_wr_tpc;
output	[1:0]	asi_rd_tnpc;
output	[1:0]	asi_wr_tnpc;
output	[1:0]	asi_rd_tstate;
output	[1:0]	asi_wr_tstate;
output	[1:0]	asi_rd_tt;
output	[1:0]	asi_wr_tt;
output	[7:0]	asi_wr_tba;
output	[7:0]	asi_wr_pstate;
output	[7:0]	asi_rd_tl;
output	[7:0]	asi_wr_tl;
output	[7:0]	asi_rd_pil;
output	[7:0]	asi_wr_pil;
output	[7:0]	asi_rd_gl;
output	[7:0]	asi_wr_gl;
output	[7:0]	asi_wr_hpstate;
output	[1:0]	asi_rd_htstate;
output	[1:0]	asi_wr_htstate;
output	[7:0]	asi_rd_hintp;
output	[7:0]	asi_wr_hintp;
output	[7:0]	asi_wr_htba;
output	[2:0]	asi_rd_h_pstate_tba;
output	[1:0]	asi_rd_tba_htba;
output	[1:0]	asi_rd_pstate_hpstate;
output  [1:0]	asi_preempt_trap;
output  [1:0]	asi_preempt_done_retry;
output	[1:0]	asi_rmw_tsa;

output	[7:0]	asi_wr_int_rec;		// Write Interrupt Receive Register
output		asi_wr_any_int_rec;	// Write any Interrupt Receive Register
output 	[7:0]	asi_rd_inc_vec_2;	// Update Interrupt Vector  Register
output 	[2:0]	asi_int_rec_mux_sel_in;
output 		asi_rd_int_rec;		// Read for any thread
output 		asi_rd_inc_vec;		// Read for any thread

output 	[7:0]	asi_check_qr_exc;	// Check for Interrupt Queue Register
					// head vs. tail mismatch

output		asi_tca_wr_data_63;	// stored negative active
output	[63:0] asi_wr_data_0;		// data to write
output	[62:0] asi_wr_data_1;		// data to write
output 		asi_tsd0_wr_data_12;
output 	[10:8]	asi_tsd0_wr_data_10_08;
output 	[5:0]	asi_tsd0_wr_data_05_00;
output 		asi_tsd1_wr_data_12;
output 	[10:8]	asi_tsd1_wr_data_10_08;
output 	[5:0]	asi_tsd1_wr_data_05_00;
output	[47:0] asi_tsa_wr_data;
output		asi_tsa_wr_data_npc_oor_va;
output		asi_tsa_wr_data_npc_nonseq;

output		asi_rd_cerer;
output		asi_rd_ceter;
output		asi_wr_cerer;
output	[2:0]	asi_ceter_tid;
output		asi_wr_ceter;

output	[2:0]	asi_rd_tid;
output		asi_rd_isfsr;
output		asi_rd_dsfsr;
output		asi_rd_dsfar;
output		asi_rd_desr;
output		asi_rd_fesr;
output	[7:0]	asi_wr_isfsr;
output	[7:0]	asi_wr_dsfsr;
output	[7:0]	asi_wr_dsfar;

output		asi_rd_iaw;
output	[1:0]	asi_wr_iaw;

output	[63:46]	asi_decr;

output		asi_ece_exc;		// Correctable ECC error on ASI rd/wr
output		asi_eue_exc;		// Uncorrectable ECC error on ASI rd/wr
output	[2:0]	asi_ecc_tid;		// TID for ECC error

output		asi_tsac;		// For DSFSR
output		asi_tsau;		
output	[1:0]	asi_tsacu;		// For killing TSA writes
output	[2:0]	asi_tsacu_tid;		

output	[7:0] asi_irl_cleared;	// Int_Received Reg had bits cleared

output		asi_rd_stage_1;		// Power management:  read in stage 1
output	[1:0]	asi_trl_pstate_en;	// Power management:  h/pstate flop
output		asi_stg1_en;		// Power management:  TCA wr data flop

output	[7:0]	asi_mbist_ecc_in;	// MBIST
output	[7:0]	asi_mbist_tsa_ecc_in;	// MBIST
output		asi_mbist_run;		// MBIST
output	[3:0]	asi_mbist_cmpsel;	// MBIST
output	[7:0]	asi_mbd_compare_data;	// MBIST
output		asi_mbd_sel_tsd0;	// MBIST
output		asi_mbd_sel_tsd1;	// MBIST
output		asi_mbd_sel_tic;	// MBIST
output	[4:0]	asi_mbist_addr;		// MBIST
output	[1:0]	asi_mbist_tsa_rd_en;	// MBIST
output	[1:0]	asi_mbist_tsa_wr_en;	// MBIST
output	[1:0]	asi_mbist_tel_en;	// MBIST

output		asi_tccup_in;
output		asi_tccud_in;

output	[7:0]	asi_immu_enable;
output	[7:0]	asi_spec_enable;

output	[7:0]	asi_halt;		
output	[7:0]	asi_clear_spu_trap_req;	

output	[7:0]	tlu_spec_enable;

output	[2:0]	tlu_tca_tid;		
output	[1:0]	tlu_tca_index;		// Index for precise TCA errors

output		tlu_mbi_tsa0_fail;	// MBIST
output		tlu_mbi_tsa1_fail;	// MBIST
output		tlu_mbi_tca_fail;	// MBIST

output	[64:0]	tlu_rngf_cdbus;		// 65 bit control/data bus 
					// 64    - ctl/data
					// 63    - valid/hole
					// 62    - ack
					// 61:60 - 00-ASI, 01-ASR, 10-PR,11-HPR
					// 59    - rd/wrx
					// 58:56 - Thread ID
					// 55:48 - ASI field
					// 47:0  - Virtual Address
output 		tlu_rngf_cdbus_error;


//////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;


tlu_asi_ctl_l1clkhdr_ctl_macro free_clken (
	.l2clk	(l2clk),
	.l1en 	(1'b1 ),
	.l1clk	(l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


//////////////////////////////////////////////////////////////////////////////
//
//  Power management
//

tlu_asi_ctl_msff_ctl_macro__width_1 pmen_lat  (
	.scan_in(pmen_lat_scanin),
	.scan_out(pmen_lat_scanout),
	.din	(lsu_tlu_pmen			),
	.dout	(pmen				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign stg1_en_in =
       lsu_asi_clken;

tlu_asi_ctl_msff_ctl_macro__width_1 stg1_en_lat  (
	.scan_in(stg1_en_lat_scanin),
	.scan_out(stg1_en_lat_scanout),
	.din	(stg1_en_in			),
	.dout	(stg1_en			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_stg1_en =
       stg1_en;

assign stg2_en_in =
       (lsu_rngf_cdbus[64] & lsu_rngf_cdbus[63]) | 
       (~lsu_rngf_cdbus[64] & stg2_en) |
       ~pmen;

tlu_asi_ctl_msff_ctl_macro__width_1 stg2_en_lat  (
	.scan_in(stg2_en_lat_scanin),
	.scan_out(stg2_en_lat_scanout),
	.din	(stg2_en_in			),
	.dout	(stg2_en			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 stg3_en_lat  (
	.scan_in(stg3_en_lat_scanin),
	.scan_out(stg3_en_lat_scanout),
	.din	(stg2_en			),
	.dout	(stg3_en			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 stg4_en_lat  (
	.scan_in(stg4_en_lat_scanin),
	.scan_out(stg4_en_lat_scanout),
	.din	(stg3_en			),
	.dout	(pstg4_en			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// data_4[64] added to prevent stopping on control packet on MMU ITLB reload
assign stg4_en =
       pstg4_en | mmu_asi_read | data_4[64];

// Have to enable during mbist because the write data goes through
// the functional path
assign pm1_en =
       stg1_en | stg2_en | stg3_en | stg4_en | mbist_run;

tlu_asi_ctl_l1clkhdr_ctl_macro stg4_clken (
	.l2clk	(l2clk				),
	.l1en	(pm1_en				),
	.l1clk	(l1clk_pm1			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


assign pm2_en =
       mbist_run | ~pmen;

tlu_asi_ctl_l1clkhdr_ctl_macro mbist_clken (
	.l2clk	(l2clk				),
	.l1en	(pm2_en				),
	.l1clk	(l1clk_pm2			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


//////////////////////////////////////////////////////////////////////////////
//
//  MBIST
//

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_run_lat 	(
	.scan_in(mbist_run_lat_scanin),
	.scan_out(mbist_run_lat_scanout),
	.din	(mbi_run			),
	.dout	(mbist_run			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mbist_run =
       mbist_run;

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa0_write_lat  (
	.scan_in(mbist_tsa0_write_lat_scanin),
	.scan_out(mbist_tsa0_write_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_tsa0_write_en		),
	.dout	(mbist_tsa0_wr_en		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa1_write_lat  (
	.scan_in(mbist_tsa1_write_lat_scanin),
	.scan_out(mbist_tsa1_write_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_tsa1_write_en		),
	.dout	(mbist_tsa1_wr_en		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tca_write_lat  (
	.scan_in(mbist_tca_write_lat_scanin),
	.scan_out(mbist_tca_write_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_tca_write_en		),
	.dout	(mbist_tca_wr_en		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_5 mbist_addr_lat  (
	.scan_in(mbist_addr_lat_scanin),
	.scan_out(mbist_addr_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_addr		[4:0]	),
	.dout	(mbist_addr		[4:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign mbist_wdata[7:0] =
       data_1[7:0];

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa0_read_lat  (
	.scan_in(mbist_tsa0_read_lat_scanin),
	.scan_out(mbist_tsa0_read_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_tsa0_read_en		),
	.dout	(mbist_tsa0_rd_en		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa1_read_lat  (
	.scan_in(mbist_tsa1_read_lat_scanin),
	.scan_out(mbist_tsa1_read_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_tsa1_read_en		),
	.dout	(mbist_tsa1_rd_en		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tca_read_lat  (
	.scan_in(mbist_tca_read_lat_scanin),
	.scan_out(mbist_tca_read_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_tca_read_en		),
	.dout	(mbist_tca_rd_en		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_4 mbist_cmpsel_lat  (
	.scan_in(mbist_cmpsel_lat_scanin),
	.scan_out(mbist_cmpsel_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbi_tlu_cmpsel		[3:0]	),
	.dout	(mbist_cmpsel		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mbist_ecc_in[7:0] =
       mbist_wdata[7:0] & {8 {mbist_run}};

assign asi_mbist_tsa_ecc_in[7:0] =
       mbist_wdata_2[7:0] & {8 {mbist_run}};

assign asi_mbist_addr[4:0] =
       mbist_addr[4:0];

assign asi_mbist_tsa_rd_en[1:0] =
       {2 {mbist_run}} & {mbist_tsa1_rd_en_2, mbist_tsa0_rd_en_2};

assign asi_mbist_tsa_wr_en[1:0] =
       {2 {mbist_run}} & {mbist_tsa1_wr_en, mbist_tsa0_wr_en};


tlu_asi_ctl_msff_ctl_macro__width_5 mbist_addr_2_lat  (
	.scan_in(mbist_addr_2_lat_scanin),
	.scan_out(mbist_addr_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_addr		[4:0]	),
	.dout	(mbist_addr_2		[4:0]	),
  .siclk(siclk),
  .soclk(soclk)
);


tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa0_read_2_lat  (
	.scan_in(mbist_tsa0_read_2_lat_scanin),
	.scan_out(mbist_tsa0_read_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_tsa0_rd_en		),
	.dout	(mbist_tsa0_rd_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa1_read_2_lat  (
	.scan_in(mbist_tsa1_read_2_lat_scanin),
	.scan_out(mbist_tsa1_read_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_tsa1_rd_en		),
	.dout	(mbist_tsa1_rd_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tca_read_2_lat  (
	.scan_in(mbist_tca_read_2_lat_scanin),
	.scan_out(mbist_tca_read_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_tca_rd_en		),
	.dout	(mbist_tca_rd_en_2		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_4 mbist_cmpsel_2_lat  (
	.scan_in(mbist_cmpsel_2_lat_scanin),
	.scan_out(mbist_cmpsel_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_cmpsel		[3:0]	),
	.dout	(mbist_cmpsel_2		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_8 mbist_wdata_2_lat  (
	.scan_in(mbist_wdata_2_lat_scanin),
	.scan_out(mbist_wdata_2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_wdata		[7:0]	),
	.dout	(mbist_wdata_2		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mbist_cmpsel[3:0] =
       mbist_cmpsel_2[3:0];


tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa0_read_3_lat  (
	.scan_in(mbist_tsa0_read_3_lat_scanin),
	.scan_out(mbist_tsa0_read_3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_tsa0_rd_en_2		),
	.dout	(mbist_tsa0_rd_en_3		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa1_read_3_lat  (
	.scan_in(mbist_tsa1_read_3_lat_scanin),
	.scan_out(mbist_tsa1_read_3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_tsa1_rd_en_2		),
	.dout	(mbist_tsa1_rd_en_3		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tca_read_3_lat  (
	.scan_in(mbist_tca_read_3_lat_scanin),
	.scan_out(mbist_tca_read_3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_tca_rd_en_2		),
	.dout	(mbist_tca_rd_en_3		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_8 mbist_wdata_3_lat  (
	.scan_in(mbist_wdata_3_lat_scanin),
	.scan_out(mbist_wdata_3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_wdata_2		[7:0]	),
	.dout	(mbist_wdata_3		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mbist_tel_en[1:0] =
       {mbist_tsa1_rd_en_3, mbist_tsa0_rd_en_3} | 
       {2 {rd_tsa_pc_2 | rd_tsa_nopc_2 | rd_tsa_ecc_2 | 
	   rd_tsa_pc_3 | rd_tsa_nopc_3 | rd_tsa_ecc_3 ||
           wr_tsa_2    | wr_tsa_3 | ~pmen}};

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa0_read_4_lat  (
	.scan_in(mbist_tsa0_read_4_lat_scanin),
	.scan_out(mbist_tsa0_read_4_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_tsa0_rd_en_3		),
	.dout	(mbist_tsa0_rd_en_4		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 mbist_tsa1_read_4_lat  (
	.scan_in(mbist_tsa1_read_4_lat_scanin),
	.scan_out(mbist_tsa1_read_4_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbist_tsa1_rd_en_3		),
	.dout	(mbist_tsa1_rd_en_4		),
  .siclk(siclk),
  .soclk(soclk)
);

assign compare_data_in[7:0] =
       (mbist_wdata_2[7:0] & {8 {~mbist_tsa_3}}) | 
       (mbist_wdata_3[7:0] & {8 { mbist_tsa_3}}) ;

tlu_asi_ctl_msff_ctl_macro__width_8 compare_data_lat  (
	.scan_in(compare_data_lat_scanin),
	.scan_out(compare_data_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(compare_data_in	[7:0]	),
	.dout	(compare_data 		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_mbd_compare_data[7:0] =
       compare_data[7:0];

assign mbist_tsa_3 =
       mbist_tsa0_rd_en_3 | mbist_tsa1_rd_en_3;

assign asi_mbd_sel_tsd0 =
       mbist_tsa0_rd_en_4;

assign asi_mbd_sel_tsd1 =
       mbist_tsa1_rd_en_4;

assign asi_mbd_sel_tic =
       mbist_tca_rd_en_3;


assign tsa0_fail_in =
       mbist_tsa0_rd_en_4;

assign tsa1_fail_in =
       mbist_tsa1_rd_en_4;

assign tca_fail_in =
       mbist_tca_rd_en_3;

tlu_asi_ctl_msff_ctl_macro__width_1 tsa0_fail_lat  (
	.scan_in(tsa0_fail_lat_scanin),
	.scan_out(tsa0_fail_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(tsa0_fail_in			),
	.dout	(tsa0_fail			),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 tsa1_fail_lat  (
	.scan_in(tsa1_fail_lat_scanin),
	.scan_out(tsa1_fail_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(tsa1_fail_in			),
	.dout	(tsa1_fail			),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 tca_fail_lat  (
	.scan_in(tca_fail_lat_scanin),
	.scan_out(tca_fail_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(tca_fail_in			),
	.dout	(tca_fail			),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 compare_lat  (
	.scan_in(compare_lat_scanin),
	.scan_out(compare_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(mbd_compare			),
	.dout	(compare			),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_mbi_tsa0_fail =
       tsa0_fail & ~compare;

assign tlu_mbi_tsa1_fail =
       tsa1_fail & ~compare;

assign tlu_mbi_tca_fail =
       tca_fail & ~compare;


//////////////////////////////////////////////////////////////////////////////
//STAGE 0
//////////////////////////////////////////////////////////////////////////////
// Decode preempt_trap/_done_retry so that read controls can go to TSA in 
// cycle 1
// so read can occur in cycle 2
// so ECC error detect can occur in cycle 3
// so packet can transmit in cycle 4

assign ctl_0 =
       lsu_rngf_cdbus[64];

assign data_0[63:48] =
       lsu_rngf_cdbus[63:48];
assign data_0_59_unused =
       data_0[59];
assign data_0_57_unused =
       data_0[57];
assign data_0_56_unused =
       data_0[56];

assign asi_0 = 
	ctl_0 & data_0[63] & ~data_0[62] & (data_0[61:60] == 2'b00);
assign pr_0 = 
	ctl_0 & data_0[63] & ~data_0[62] &  data_0[61] & ~data_0[60];
assign hpr_0 = 
	ctl_0 & data_0[63] & ~data_0[62] & (data_0[61:60] == 2'b11);

// Any PR between 0 and 3 (field is 5 bits)
assign pr_tstack_0 = 
	pr_0 & (data_0[52:50] == 3'b000);

// Note that write to GL must preempt trap because EXU cannot handle 
// multiple GL updates
assign wr_gl_0 = 
	pr_0 & data_0[52] & ~data_0[59];

// HPR is 1, not 0, 3, 5, 6, or 1F
assign htstate_0 = 
	hpr_0 & ~data_0[50] & ~data_0[49] &  data_0[48];

// All queue registers are ASI 25
assign asi_25_0 =
       asi_0 & (data_0[55:48] == 8'h25);

// TSA diagnostic ECC read at ASI 0x5B
assign tsa_diag_0 =
       asi_0 & (data_0[55:48] == 8'h5b);

// The following require access to the trap stack array (TSA)
// Even writes require a read, so block done and retry for both
assign preempt_done_retry_in[1:0] =
       ({2 {pr_tstack_0 | wr_gl_0 | htstate_0 | asi_25_0 | tsa_diag_0}} &
        {data_0[58], ~data_0[58]}) | 
       {2 {mbist_run}};

// Need to preempt traps on writes to GL reg
// but these are held two cycles now so delay by two cycles
assign preempt_trap_in[1:0] =
       {2 {wr_gl_2}} & {data_2[58], ~data_2[58]};

tlu_asi_ctl_msff_ctl_macro__width_4 preempt_trap_lat  (
	.scan_in(preempt_trap_lat_scanin),
	.scan_out(preempt_trap_lat_scanout),
	.din	({preempt_trap_in	[1:0],
		  preempt_done_retry_in	[1:0]}),
	.dout	({preempt_trap		[1:0],
		  preempt_done_retry	[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_preempt_trap[1:0] = 
       preempt_trap[1:0];
assign asi_preempt_done_retry[1:0] = 
       preempt_done_retry[1:0];


//
// Handle fatal deferred and disrupting error registers
//

assign sel_lsu =
       ~rd_clesr & ~rd_clfesr;

assign clesr_data[63:0] =
       {dfd_desr_f[7], dfd_fesr_f[7],
	dfd_desr_f[6], dfd_fesr_f[6],
	dfd_desr_f[5], dfd_fesr_f[5],
	dfd_desr_f[4], dfd_fesr_f[4],
	dfd_desr_f[3], dfd_fesr_f[3],
	dfd_desr_f[2], dfd_fesr_f[2],
	dfd_desr_f[1], dfd_fesr_f[1],
	dfd_desr_f[0], dfd_fesr_f[0],
	{48 {1'b0}}};

assign clfesr_in[63:48] =
       ({16 {~(| clfesr_data[63:48])}} & clesr_data [63:48]) |
       ({16 { (| clesr_data [63:48])}} & clfesr_data[63:48]) ;
assign clfesr_in[47:0] =
       {48 {1'b0}};

tlu_asi_ctl_msff_ctl_macro__width_16 clfesr_lat  ( // FS:wmr_protect
	.scan_in(clfesr_lat_wmr_scanin),
	.scan_out(clfesr_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(clfesr_in		[63:48]	),
	.dout	(clfesr_data		[63:48]	),
  .l1clk(l1clk),
  .soclk(soclk)
);


assign data_1_in[63:0] =
       ({64 {mbist_run}} & {8 {mbi_wdata[7:0]}}) |
       ({64 {sel_lsu  & ~mbist_run}} & lsu_rngf_cdbus	[63:0]) |
       ({64 {rd_clesr & ~mbist_run}} & clesr_data	[63:0]) |
       ({64 {rd_clfesr& ~mbist_run}} & clfesr_in	[63:0]) ;


assign asi_int_rec_mux_sel_in[2:0] =
       data_1        [58:56];


/////////////////////////////////////////////////////////////////////
//STAGE 1
/////////////////////////////////////////////////////////////////////
// Stage the packet coming on the ring
// First cycle of the packet holds control and address information
// Second cycle holds the store/load data

tlu_asi_ctl_msff_ctl_macro__width_64 rng_stg1_data  (
	.scan_in(rng_stg1_data_scanin),
	.scan_out(rng_stg1_data_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(data_1_in		[63:0]	), 
	.dout	(data_1			[63:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// register control bit, bit 64 indicates whether ctl packet or data packet
tlu_asi_ctl_msff_ctl_macro__width_1 ctl_1_lat  (
	.scan_in(ctl_1_lat_scanin),
	.scan_out(ctl_1_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(lsu_rngf_cdbus		[64   ]	),
	.dout	(ctl_1				),
  .siclk(siclk),
  .soclk(soclk)
);

assign rd_stage_1 =
       ctl_1 & data_1[59];

assign asi_rd_stage_1 =
       rd_stage_1;


// decode the packet

tlu_asi_ctl_msff_ctl_macro__width_8 hpstatehpriv_lat  (
	.scan_in(hpstatehpriv_lat_scanin),
	.scan_out(hpstatehpriv_lat_scanout),
	.din	(tsd_hpstate_hpriv	[7:0]	),
	.dout	(hpstatehpriv		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_8 pstatepriv_lat  (
	.scan_in(pstatepriv_lat_scanin),
	.scan_out(pstatepriv_lat_scanout),
	.din	(tsd_pstate_priv	[7:0]	),
	.dout	(pstatepriv		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign hpstate_hpriv = 
       (| (hpstatehpriv[7:0] & rd_tid_dec[7:0]));

assign pstate_priv = 
       (| (pstatepriv[7:0] & rd_tid_dec[7:0])) | hpstate_hpriv;

assign asi = 
	ctl_1 & data_1[63] & ~data_1[62] & (data_1[61:60] == 2'b00);
assign asr = 
	ctl_1 & data_1[63] & ~data_1[62] & (data_1[61:60] == 2'b01);
assign pr = 
	ctl_1 & data_1[63] & ~data_1[62] & (data_1[61:60] == 2'b10);
assign hpr = 
	ctl_1 & data_1[63] & ~data_1[62] & (data_1[61:60] == 2'b11);

assign asi_2 = 
	ctl_2 & data_2[63] & ~data_2[62] & (data_2[61:60] == 2'b00);
assign asr_2 = 
	ctl_2 & data_2[63] & ~data_2[62] & (data_2[61:60] == 2'b01);
assign pr_2 = 
	  ctl_2 & data_2[63] & ~data_2[62] & (data_2[61:60] == 2'b10);
assign hpr_2 = 
	  ctl_2 & data_2[63] & ~data_2[62] & (data_2[61:60] == 2'b11);

assign fast_asi =
       ~data_1[61] & ~data_1[60];	

assign superfast_hpr_2 =
       data_2[60];		

assign mondo_head =
       asi & (data_1[55:48] == 8'h25) & (data_1[5:3] == 3'h0);
assign rd_mondo_head =
       mondo_head &  data_1[59];
assign wr_mondo_head =
       mondo_head & ~data_1[59];

assign mondo_tail =
       asi & (data_1[55:48] == 8'h25) & (data_1[5:3] == 3'h1);
assign rd_mondo_tail =
       mondo_tail &  data_1[59];
assign wr_mondo_tail =
       mondo_tail & ~data_1[59];

assign device_head =
       asi & (data_1[55:48] == 8'h25) & (data_1[5:3] == 3'h2);
assign rd_device_head =
       device_head &  data_1[59];
assign wr_device_head =
       device_head & ~data_1[59];

assign device_tail =
       asi & (data_1[55:48] == 8'h25) & (data_1[5:3] == 3'h3);
assign rd_device_tail =
       device_tail &  data_1[59];
assign wr_device_tail =
       device_tail & ~data_1[59];

assign res_err_head =
       asi & (data_1[55:48] == 8'h25) & (data_1[5:3] == 3'h4);
assign rd_res_err_head =
       res_err_head &  data_1[59];
assign wr_res_err_head =
       res_err_head & ~data_1[59];

assign res_err_tail =
       asi & (data_1[55:48] == 8'h25) & (data_1[5:3] == 3'h5);
assign rd_res_err_tail =
       res_err_tail &  data_1[59];
assign wr_res_err_tail =
       res_err_tail & ~data_1[59];

assign nonres_err_head =
       asi & (data_1[55:48] == 8'h25) & (data_1[5:3] == 3'h6);
assign rd_nonres_err_head =
       nonres_err_head &  data_1[59];
assign wr_nonres_err_head =
       nonres_err_head & ~data_1[59];

assign nonres_err_tail =
       asi & (data_1[55:48] == 8'h25) & (data_1[5:3] == 3'h7);
assign rd_nonres_err_tail =
       nonres_err_tail &  data_1[59];
assign wr_nonres_err_tail =
       nonres_err_tail & ~data_1[59];

// Shadow copy of spec enable and IMMU enable bits in LSU control reg
// Only support write; LSU handles read
assign lsu_ctl = 
       asi & (data_1[55:48] == 8'h45) & ~data_1[4] & ~data_1[3];
assign wr_lsu_ctl =
       lsu_ctl & ~data_1[59];

// DECR (only one per physical core)
assign decr = 
       asi & (data_1[55:48] == 8'h45) & ~data_1[4] & data_1[3];
assign rd_decr =
       decr &  data_1[59];
assign wr_decr =
       decr & ~data_1[59];

// DESR, FESR
assign esr =
       asi & (data_1[55:48] == 8'h4c);
assign desr =
       esr &  (data_1[5:3] == 3'b000);
assign rd_desr =
       desr &  data_1[59];
assign fesr =
       esr &  (data_1[5:3] == 3'b001);
assign rd_fesr =
       fesr &  data_1[59];
assign clesr =
       esr &  (data_1[5:3] == 3'b100);
assign rd_clesr =
       clesr &  data_1[59];
assign clfesr =
       esr &  (data_1[5:3] == 3'b101);
assign rd_clfesr =
       clfesr &  data_1[59];

assign cerer =
       esr & (data_1[5:3] == 3'b010);
assign rd_cerer =
       cerer &  data_1[59];
assign wr_cerer =
       cerer & ~data_1[59];

assign ceter =
       esr & (data_1[5:3] == 3'b011);
assign rd_ceter =
       ceter &  data_1[59];
assign wr_ceter =
       ceter & ~data_1[59];

// ISFSR at 0x50/0x18
// instruction_va_watchpoint at 0x50/0x38
assign isfsr =
       asi & (data_1[55:48] == 8'h50) & (data_1[5:3] == 3'b011);
assign rd_isfsr =
       isfsr &  data_1[59];
assign wr_isfsr =
       isfsr & ~data_1[59];

assign iaw_2 =
       asi_2 & (data_2[55:48] == 8'h50) & (data_2[5:3] == 3'b111);
assign rd_iaw_2 =
       iaw_2 &  data_2[59];
assign wr_iaw_2 =
       iaw_2 & ~data_2[59];

// DSFSR at 0x58/0x18, DSFAR at 0x20
assign dsfsr =
       asi & (data_1[55:48] == 8'h58) & (data_1[5:3] == 3'b011);
assign rd_dsfsr =
       dsfsr &  data_1[59];
assign wr_dsfsr =
       dsfsr & ~data_1[59];
assign dsfar =
       asi & (data_1[55:48] == 8'h58) & (data_1[5:3] == 3'b100);
assign rd_dsfar =
       dsfar &  data_1[59];
assign wr_dsfar =
       dsfar & ~data_1[59];

// Tick compare array ECC / data access at 0x5A/0x00-0x38
assign tca_diag =
       asi & (data_1[55:48] == 8'h5a);
assign rd_tca_ecc =
       tca_diag & ~data_1[5] &  data_1[59];
assign rd_tca_data =
       tca_diag &  data_1[5] &  data_1[59];

// TSA ECC access at 0x5B/0x00-0x18
assign tsa_diag =
       asi & (data_1[55:48] == 8'h5b);
assign rd_tsa_ecc =
       tsa_diag & ~data_1[6] &  data_1[59];

assign int_rec =
       asi & (data_1[55:48] == 8'h72);
assign rd_int_rec =
       int_rec &  data_1[59];
assign wr_int_rec =
       int_rec & ~data_1[59];

assign inc_vec =
       asi & (data_1[55:48] == 8'h74);
assign rd_inc_vec =
       inc_vec &  data_1[59];


assign asireg_2 = 
       asr_2 & (data_2[55:48] == 8'h03);
assign rd_asireg_2 = 
       asireg_2 &  data_2[59];
assign wr_asireg_2 = 
       asireg_2 & ~data_2[59];

// Covers ASR tick, PR tick, and ASR stick
assign tick = 
	((asr | pr) & (data_1[55:48] == 8'h04)) |
	(asr & (data_1[55:48] == 8'h18));
assign rd_tick = 
	tick &  data_1[59] &  (hpstate_hpriv | pstate_priv | tick_npt_1_);
assign priv_action = 
	tick &  data_1[59] & ~(hpstate_hpriv | pstate_priv | tick_npt_1_);
assign wr_tick = 
	tick & ~data_1[59] & hpstate_hpriv;
assign tick_npt_1_ =
       | (tick_npt_[7:0] & rd_tid_dec[7:0]);

assign pc_2 = 
	asr_2 & (data_2[55:48] == 8'h05);
assign rd_pc_2 = 
	pc_2 &  data_2[59];

assign set_softint = 
	asr & (data_1[55:48] == 8'h14);
assign wr_set_softint = 
	set_softint & ~data_1[59];

assign clear_softint = 
	asr & (data_1[55:48] == 8'h15);
assign wr_clear_softint = 
	clear_softint & ~data_1[59];

assign softint = 
	asr & (data_1[55:48] == 8'h16);
assign rd_softint = 
	softint &  data_1[59];
assign wr_softint = 
	softint & ~data_1[59];

assign tick_cmpr = 
	asr & (data_1[55:48] == 8'h17);
assign rd_tick_cmpr = 
	tick_cmpr &  data_1[59];
assign wr_tick_cmpr = 
	tick_cmpr & ~data_1[59];

// ASR stick covered by tick

assign stick_cmpr = 
	asr & (data_1[55:48] == 8'h19);
assign rd_stick_cmpr = 
	stick_cmpr &  data_1[59] & pstate_priv;
assign wr_stick_cmpr = 
	stick_cmpr & ~data_1[59] & pstate_priv;

assign tpc = 
	pr & (data_1[55:48] == 8'h00);
assign rd_tpc = 
	tpc	&  data_1[59];
assign wr_tpc = 
	tpc 	& ~data_1[59];

assign tnpc = 
	pr & (data_1[55:48] == 8'h01);
assign rd_tnpc = 
	tnpc	&  data_1[59];
assign wr_tnpc =
	tnpc 	& ~data_1[59];

assign tstate = 
	pr & (data_1[55:48] == 8'h02);
assign rd_tstate = 
	tstate	&  data_1[59];
assign wr_tstate =
	tstate 	& ~data_1[59];

assign tt = 
	pr & (data_1[55:48] == 8'h03);
assign rd_tt = 
	tt	&  data_1[59];
assign wr_tt =
	tt 	& ~data_1[59];

// tick as PR 0x04 is covered in ASR section

assign tba_2 = 
	pr_2 & (data_2[55:48] == 8'h05);
assign rd_tba_2 = 
	tba_2	&  data_2[59];
assign wr_tba_2 =
	tba_2 	& ~data_2[59];

assign pstate = 
	pr & (data_1[55:48] == 8'h06);
assign wr_pstate = 
	pstate & ~data_1[59];
assign pstate_2 = 
	pr_2 & (data_2[55:48] == 8'h06);
assign rd_pstate_2 = 
	pstate_2 &  data_2[59];

assign tl = 
	pr & (data_1[55:48] == 8'h07);
assign rd_tl = 
	tl	&  data_1[59];
assign wr_tl = 
	tl	& ~data_1[59];

assign pil = 
	pr & (data_1[55:48] == 8'h08);
assign rd_pil = 
	pil	&  data_1[59];
assign wr_pil = 
	pil	& ~data_1[59];

assign gl = 
	pr & (data_1[55:48] == 8'h10);
assign rd_gl = 
	gl	&  data_1[59];
assign wr_gl = 
	gl	& ~data_1[59];

assign hpstate = 
	hpr & (data_1[55:48] == 8'h00);
assign wr_hpstate = 
	hpstate & ~data_1[59];
assign hpstate_2 = 
	hpr_2 & (data_2[55:48] == 8'h00);
assign rd_hpstate_2 = 
	hpstate_2 &  data_2[59];

assign htstate = 
	hpr & (data_1[55:48] == 8'h01);
assign rd_htstate = 
	htstate &  data_1[59];
assign wr_htstate = 
	htstate & ~data_1[59];

assign hintp = 
	hpr & (data_1[55:48] == 8'h03);
assign rd_hintp = 
	hintp &  data_1[59];
assign wr_hintp = 
	hintp & ~data_1[59];

assign htba_2 = 
	hpr_2 & (data_2[55:48] == 8'h05);
assign rd_htba_2 = 
	htba_2 &  data_2[59];
assign wr_htba_2 = 
	htba_2 & ~data_2[59];

assign hver = 
	hpr & (data_1[55:48] == 8'h06);
assign rd_hver = 
	hver &  data_1[59];

assign rd_halt = 
	hpr & (data_1[55:48] == 8'h1e) &  data_1[59];
assign wr_halt = 
	hpr & (data_1[55:48] == 8'h1e) & ~data_1[59];

assign hstick_cmpr = 
	hpr & (data_1[55:48] == 8'h1f);
assign rd_hstick_cmpr = 
	hstick_cmpr &  data_1[59];
assign wr_hstick_cmpr = 
	hstick_cmpr & ~data_1[59];


// address to send to TSA
assign fast_tsa_rd_iqr =
       fast_asi &  data_1[48];
assign fast_rd_tsa_ecc =
       fast_asi & ~data_1[48];
 
assign fast_tsa_rd_iqr_res_nonres =
       fast_tsa_rd_iqr & data_1[5];

assign asi_tsa_rd_iqr_ecc =
       fast_asi | mbist_run;

assign asi_tsa_tid[1:0] =
       data_1[57:56];

assign asi_tsa_rd_addr[4:0] =
       ({5 {~mbist_run}} & 
	{data_1[57:56],
       	 ({3 {fast_tsa_rd_iqr & ~fast_rd_tsa_ecc}} & 3'b110) |
       	 ({3 {fast_tsa_rd_iqr_res_nonres & ~fast_rd_tsa_ecc}} & 3'b111) |
       	 ({3 {                   fast_rd_tsa_ecc}} & data_1[5:3])}) |
       ({5 {mbist_run}} & mbist_addr_2[4:0]) ;


assign rd_tca = 
       rd_tick_cmpr | rd_stick_cmpr | rd_hstick_cmpr | rd_tca_ecc | rd_tca_data;
assign wr_tca = 
       wr_tick_cmpr | wr_stick_cmpr | wr_hstick_cmpr;

// Hold TCA read address for RAS
assign tca_rd_addr[4] =
       rd_hstick_cmpr;
assign tca_rd_addr[3] =
       rd_stick_cmpr;

assign tca_addr[4] =
       tca_rd_addr[4] | wr_hstick_cmpr_2 | (tca_diag & data_1[4]);
assign tca_addr[3] =
       tca_rd_addr[3]  | wr_stick_cmpr_2 | (tca_diag & data_1[3]);
assign tca_addr[2:0] =
       (data_1[58:56] & {3 {rd_tca  }}) |
       (data_2[58:56] & {3 {wr_tca_2}}) ;

assign asi_tca_addr[4:0] =
       ({5 {~mbist_run}} &   tca_addr[4:0]) |
       ({5 { mbist_run}} & mbist_addr[4:0]) ;
	       
assign asi_tca_addr_valid =
       rd_tca | wr_tca_2 | mbist_run;
assign asi_tca_wr =
       (wr_tca_2 & ~mbist_run) | (mbist_tca_wr_en & mbist_run);


assign rd_tid_dec	[7:0] = 
       { data_1[58] &  data_1[57] &  data_1[56], 
         data_1[58] &  data_1[57] & ~data_1[56], 
         data_1[58] & ~data_1[57] &  data_1[56], 
         data_1[58] & ~data_1[57] & ~data_1[56], 
        ~data_1[58] &  data_1[57] &  data_1[56], 
        ~data_1[58] &  data_1[57] & ~data_1[56], 
        ~data_1[58] & ~data_1[57] &  data_1[56], 
        ~data_1[58] & ~data_1[57] & ~data_1[56]};

// For tlu_ras_ctl and tlu_dfd_dp
assign asi_rd_tid[2:0] = 
       data_1[58:56];

// These are stored in the TSA
assign rd_tsa_nopc =
       rd_tstate | rd_tt | rd_htstate | 
       rd_mondo_head | rd_mondo_tail | 
       rd_device_head | rd_device_tail |
       rd_res_err_head | rd_res_err_tail | 
       rd_nonres_err_head | rd_nonres_err_tail;
assign rd_tsa_pc =
       rd_tpc | rd_tnpc;

assign wr_tsa_2 =
       wr_tstate_2 | wr_tt_2 | wr_htstate_2 | 
       wr_mondo_head_2 | wr_mondo_tail_2 | 
       wr_device_head_2 | wr_device_tail_2 |
       wr_res_err_head_2 | wr_res_err_tail_2 | 
       wr_nonres_err_head_2 | wr_nonres_err_tail_2 |
       wr_tpc_2 | wr_tnpc_2;

assign wr_tsa_3 =
       wr_tstate_3 | wr_tt_3 | wr_htstate_3 | 
       wr_mondo_head_3 | wr_mondo_tail_3 | 
       wr_device_head_3 | wr_device_tail_3 |
       wr_res_err_head_3 | wr_res_err_tail_3 | 
       wr_nonres_err_head_3 | wr_nonres_err_tail_3 |
       wr_tpc_3 | wr_tnpc_3;
// 
// no rd_iqr[2:0] for mondo/res head
// rd_iqr[2] for device/nonres head
// rd_iqr[1] for mondo/res tail
// rd_iqr[0] for device/nonres tail
assign rd_iqr_2[2] =
       rd_device_head_2     | rd_nonres_err_head_2 ;
assign rd_iqr_2[1] =
       rd_mondo_tail_2      | rd_res_err_tail_2    ;
assign rd_iqr_2[0] =
       rd_device_tail_2     | rd_nonres_err_tail_2 ;

assign rd_iqr_reg_2 = 
       rd_nonres_err_tail_2 | rd_nonres_err_head_2 | 
       rd_res_err_tail_2    | rd_res_err_head_2    |
       rd_device_tail_2     | rd_device_head_2     |
       rd_mondo_tail_2      | rd_mondo_head_2      ;
// These are flopped in TSD before use
assign asi_rd_iqr		[2:0] =
       rd_iqr_2			[2:0];
assign asi_rd_tpc		[1:0] = 
       {2 {rd_tpc_2}}			& {data_2[58], ~data_2[58]};
assign asi_rd_tnpc		[1:0] = 
       {2 {rd_tnpc_2}}			& {data_2[58], ~data_2[58]};
assign asi_rd_tstate		[1:0] = 
       {2 {rd_tstate_2}}		& {data_2[58], ~data_2[58]};
assign asi_rd_tt		[1:0] = 
       {2 {rd_tt_2}}			& {data_2[58], ~data_2[58]};
assign asi_rd_htstate		[1:0] = 
       {2 {rd_htstate_2}}		& {data_2[58], ~data_2[58]};
assign asi_rd_iqr_reg		[1:0] = 
       {2 {rd_iqr_reg_2}}		& {data_2[58], ~data_2[58]};

assign asi_rd_cerer =
       rd_cerer_2;
assign asi_rd_ceter =
       rd_ceter_2;
assign asi_rd_int_rec =
       rd_int_rec;
assign asi_rd_inc_vec =
       rd_inc_vec;
assign asi_rd_inc_vec_2[7:0] =
	{8 {rd_inc_vec_2}}	&  wr_tid_dec[7:0];
assign asi_rd_asireg[7:0] = 
	{8 {rd_asireg_2}}	&  wr_tid_dec[7:0];
assign asi_rd_tick          = 
       rd_tick_3  		                    ;
assign asi_rd_pc[7:0] = 
       {8 {rd_pc_2}} & wr_tid_dec[7:0];
assign asi_rd_iaw = 
       rd_iaw_2;
assign asi_rd_isfsr	=
       rd_isfsr;
assign asi_rd_dsfsr	=
       rd_dsfsr;

assign asi_rd_h_pstate_tba	[2:0] =
	{superfast_hpr_2, data_2[57:56]};
assign asi_rd_tba_htba		[1:0]	=
       {2 {rd_tba_2 | rd_htba_2}} & {data_2[58], ~data_2[58]};
assign asi_rd_pstate_hpstate	[1:0]	=
       {2 {rd_pstate_2 | rd_hpstate_2}} & {data_2[58], ~data_2[58]};

assign rd_cth =
       rd_int_rec | rd_inc_vec;

assign rd_trl = 
       rd_tl | rd_pil | rd_gl | rd_softint | rd_hintp;

assign rd_tic = 
       rd_tick_cmpr | rd_stick_cmpr | rd_hstick_cmpr;

assign rd_tsd_2 = 
       rd_asireg_2 | rd_pstate_2 | rd_hpstate_2;

assign rd_tba_htba_2 =
       rd_tba_2 | rd_htba_2;

assign rmw_tsa_in[1:0] =
       {2 {wr_tpc | wr_tnpc | wr_tstate | wr_tt | wr_htstate |
	   wr_mondo_head | wr_mondo_tail | wr_device_head | wr_device_tail |
	   wr_res_err_head | wr_res_err_tail | 
	   wr_nonres_err_head | wr_nonres_err_tail}} & 
       {data_1[58], ~data_1[58]} & {2 {~data_1[59]}};

assign asi_rmw_tsa[1:0] =
       rmw_tsa_in[1:0];
				  

// HVER read
// Bits    Field   Contents
// 63:48   manuf   0x003E
// 47:32   impl    0x0024
// 31:24   mask    1
// 23:19   rsvd0   0
// 18:16   maxgl   0x3
// 15:8    maxtl   0x6
// 7:5     rsvd1   0
// 4:0     maxwin  0x7
assign hver_value[63:0] =
       {32'h003e0024, hver_mask_major_rev[3:0], hver_mask_minor_rev[3:0], 
	24'h030607};


// Bit 63 is stored negative active
assign tic_ecc[63:0] =
       { {56 {1'b0}}, cel_ecc[7:0]};
assign data_err_1[63:0] = 
	{data_1[63],
	 data_1[62] | priv_action,
	 data_1[61:56],
	 (data_1[55:48] & ~{8 {priv_action}}) | {{6 {1'b0}}, priv_action, 1'b0},
	 data_1[47:0]};
assign decr_data[63:0] =
	{decr_reg[63:46], {46 {1'b0}}};

// Map of how the various registers get merged into the ASI bus in DFD,CTH,CER
// cer_asi_data	63:48 47:41	40:37	36:19	18:0
// cth_asi_data	63:48 47:41	40:37	36:19	18:0
// dfd_asi_data	63:48 47:41	40:37	36:19	18:0
// dsfar	63:48 47:41	40:37	36:19	18:0
// fesr		       6:0
// desr					        18:0
// dsfsr/{0,isfsr}	         3:0
assign dsfar_data[63:0] =
       {{16 {1'b0}}, cer_asi_data[47:0]};
assign fesr_data[63:0] =
       {{2 {1'b0}}, cer_asi_data[47:41], {55 {1'b0}}};
assign desr_data[63:0] =
       {cer_asi_data[18:11], {45 {1'b0}}, cer_asi_data[10:0]};
assign isfsr_data[63:0] =
       { {61 {1'b0}}, cer_asi_data[39:37]};
assign dsfsr_data[63:0] =
       { {60 {1'b0}}, cer_asi_data[40:37]};
			

assign sel_data1 =
       ~priv_action   & ~rd_hver_2     & ~rd_cth_2   & 
       ~rd_cerer_2 &  
       ~rd_tca_ecc_2  & ~rd_tca_data_2 & ~rd_ceter_2 & 
       ~rd_desr_2 & ~rd_fesr_2 & ~rd_dsfar_2 & 
       ~rd_isfsr_2    & ~rd_dsfsr_2    & ~rd_decr_2  ;

assign data_2_in[63:0] =
       ({64 {sel_data1    }} & data_1		[63:0]) |
       ({64 {priv_action  }} & data_err_1	[63:0]) |
       ({64 {rd_hver_2    }} & hver_value	[63:0]) |
       ({64 {rd_cth_2     }} & cer_asi_data	[63:0]) |
       ({64 {rd_cerer_2   }} & cer_asi_data	[63:0]) |
       ({64 {rd_tca_ecc_2 }} & tic_ecc		[63:0]) |
       ({64 {rd_tca_data_2}} & tic_data		[63:0]) |
       ({64 {rd_ceter_2	  }} & cer_asi_data	[63:0]) |
       ({64 {rd_desr_2    }} & desr_data	[63:0]) |
       ({64 {rd_fesr_2    }} & fesr_data	[63:0]) |
       ({64 {rd_dsfar_2   }} & dsfar_data	[63:0]) |
       ({64 {rd_isfsr_2	  }} & isfsr_data	[63:0]) |
       ({64 {rd_dsfsr_2	  }} & dsfsr_data	[63:0]) |
       ({64 {rd_decr_2	  }} & decr_data	[63:0]) ;
        

/////////////////////////////////////////////////////////////////////
//STAGE 2
/////////////////////////////////////////////////////////////////////
// pipe the packets and decoded control information
tlu_asi_ctl_msff_ctl_macro__width_64 stg2_data_lat  (
	.scan_in(stg2_data_lat_scanin),
	.scan_out(stg2_data_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(data_2_in		[63:0]	), 
	.dout	(data_2			[63:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// register control bit
tlu_asi_ctl_msff_ctl_macro__width_72 stg2_ctl_lat  (
	.scan_in(stg2_ctl_lat_scanin),
	.scan_out(stg2_ctl_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	({ctl_1, 
		  rd_cth,
		  rd_tsa_pc,
		  rd_tsa_ecc,
		  rd_tsa_nopc,
		  rd_hver,
		  rd_tic,
		  rd_tca_ecc,
		  rd_tca_data,
		  rd_tick,
		  rd_mondo_head,
		  rd_mondo_tail,
		  rd_device_head,
		  rd_device_tail,
		  rd_res_err_head,
		  rd_res_err_tail,
		  rd_nonres_err_head,
		  rd_nonres_err_tail,
		  rd_tpc,
		  rd_tnpc,
		  rd_tstate,
		  rd_tt,
		  rd_htstate,
		  rd_ceter,
		  rd_inc_vec,
		  rd_decr,
		  rd_softint,
		  rd_tl,
		  rd_gl,
		  rd_pil,
		  rd_hintp,
		  rd_trl,
		  rd_cerer,
		  rd_isfsr,
		  rd_dsfsr,
		  rd_dsfar,
		  rd_desr,
		  rd_fesr,
		  wr_mondo_head,
		  wr_mondo_tail,
		  wr_device_head,
		  wr_device_tail,
		  wr_res_err_head,
		  wr_res_err_tail,
		  wr_nonres_err_head,
		  wr_nonres_err_tail,
		  wr_int_rec,
		  wr_tick,
		  wr_set_softint,
		  wr_clear_softint,
		  wr_softint,
		  wr_tpc,
		  wr_tnpc,
		  wr_tstate,
		  wr_tt,
		  wr_pstate,
		  wr_tl, 
		  wr_pil, 
		  wr_gl,
		  wr_hpstate,
		  wr_htstate,
		  wr_hintp,
		  wr_tca,
		  wr_hstick_cmpr,
		  wr_stick_cmpr,
		  wr_cerer,
		  wr_ceter,
		  wr_isfsr,
		  wr_dsfsr,
		  wr_dsfar,
		  wr_decr,
		  wr_lsu_ctl}),
	.dout	({ctl_2,
		  rd_cth_2,
		  rd_tsa_pc_2,
		  rd_tsa_ecc_2,
		  rd_tsa_nopc_2,
		  rd_hver_2,
		  rd_tic_2,
		  rd_tca_ecc_2,
		  rd_tca_data_2,
		  rd_tick_2,
		  rd_mondo_head_2,
		  rd_mondo_tail_2,
		  rd_device_head_2,
		  rd_device_tail_2,
		  rd_res_err_head_2,
		  rd_res_err_tail_2,
		  rd_nonres_err_head_2,
		  rd_nonres_err_tail_2,
		  rd_tpc_2,
		  rd_tnpc_2,
		  rd_tstate_2,
		  rd_tt_2,
		  rd_htstate_2,
		  rd_ceter_2,
		  rd_inc_vec_2,
		  rd_decr_2,
		  rd_softint_2,
		  rd_tl_2,
		  rd_gl_2,
		  rd_pil_2,
		  rd_hintp_2,
		  rd_trl_2,
		  rd_cerer_2,
		  rd_isfsr_2,
		  rd_dsfsr_2,
		  rd_dsfar_2,
		  rd_desr_2,
		  rd_fesr_2,
		  wr_mondo_head_2,
		  wr_mondo_tail_2,
		  wr_device_head_2,
		  wr_device_tail_2,
		  wr_res_err_head_2,
		  wr_res_err_tail_2,
		  wr_nonres_err_head_2,
		  wr_nonres_err_tail_2,
		  wr_int_rec_2,
		  wr_tick_2,
		  wr_set_softint_2,
		  wr_clear_softint_2,
		  wr_softint_2,
		  wr_tpc_2,
		  wr_tnpc_2,
		  wr_tstate_2,
		  wr_tt_2,
		  wr_pstate_2,
		  wr_tl_2, 
		  wr_pil_2, 
		  wr_gl_2,
		  wr_hpstate_2,
		  wr_htstate_2,
		  wr_hintp_2,
		  wr_tca_2,
		  wr_hstick_cmpr_2,
		  wr_stick_cmpr_2,
		  wr_cerer_2,
		  wr_ceter_2,
		  wr_isfsr_2,
		  wr_dsfsr_2,
		  wr_dsfar_2,
		  wr_decr_2,
		  wr_lsu_ctl_2}),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_8 wr_tid_dec_lat  (
	.scan_in(wr_tid_dec_lat_scanin),
	.scan_out(wr_tid_dec_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(rd_tid_dec		[7:0]	),
	.dout	(wr_tid_dec		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_rd_softint[7:0] = 
	{8 {rd_softint_2}}	&  wr_tid_dec[7:0];
assign asi_rd_tl	[7:0] = 
	{8 {rd_tl_2}}		&  wr_tid_dec[7:0];
assign asi_rd_pil	[7:0] = 
	{8 {rd_pil_2}}		&  wr_tid_dec[7:0];
assign asi_rd_gl	[7:0] = 
	{8 {rd_gl_2}}		&  wr_tid_dec[7:0];
assign asi_rd_hintp	[7:0] =
	{8 {rd_hintp_2}}	&  wr_tid_dec[7:0];


// send the store data out to the unit. Store data is in stage1 when control 
// is in stage 2.
//  The data is accompanied by write control signal.
assign asi_wr_data_0[63:0] =
       data_1[63:0];
assign asi_wr_data_1[62:0] =
       data_1[62:0];
assign asi_tsd0_wr_data_12 = 
       data_1[12];
assign asi_tsd0_wr_data_10_08[10:8] = 
       data_1[10:8];
assign asi_tsd0_wr_data_05_00[5:0] = 
       data_1[5:0];
assign asi_tsd1_wr_data_12 = 
       data_1[12];
assign asi_tsd1_wr_data_10_08[10:8] = 
       data_1[10:8];
assign asi_tsd1_wr_data_05_00[5:0] = 
       data_1[5:0];

assign asi_tca_wr_data_63 =
       (~data_1[63] & ~mbist_run) | (mbist_wdata[7] & mbist_run);
// TSA written one cycles later
assign asi_tsa_wr_data	[47:0] = 
       (data_2		[47:0] & {48 {~mbist_run}}) | 
       (mbist_tsa_wdata	[47:0] & {48 { mbist_run}}) ;
// MBIST data shifted because only store NPC down to bit 2
assign mbist_tsa_wdata[47:0] = 
       {mbist_wdata[5:0], {5 {mbist_wdata[7:0]}}, 2'b00};

// Functionally this should be 0; during MBIST it should be wdata[0]
assign asi_tsa_wr_data_npc_oor_va =
        mbist_run & mbist_wdata[0];
// Functionally this should be 1; during MBIST it should be mbist_wdata[5]
assign asi_tsa_wr_data_npc_nonseq =
       ~mbist_run | mbist_wdata[5];
assign asi_wr_cerer =
       wr_cerer_2;
assign asi_wr_ceter =
       wr_ceter_2;
assign asi_ceter_tid[2:0] =
       data_2[58:56];
assign asi_wr_int_rec	[7:0] =
       {8 {wr_int_rec_2}}	& wr_tid_dec[7:0];
assign asi_wr_any_int_rec	=
       wr_int_rec_2;
assign asi_wr_asireg	[7:0] = 
       {8 {wr_asireg_2}}	& wr_tid_dec[7:0];
assign asi_wr_tick	        = 
           wr_tick_2  		                   ;
assign asi_wr_set_softint[7:0] = 
       {8 {wr_set_softint_2}}	& wr_tid_dec[7:0];
assign asi_wr_clear_softint[7:0] = 
       {8 {wr_clear_softint_2}}	& wr_tid_dec[7:0];
assign asi_wr_softint	[7:0] = 
       {8 {wr_softint_2}}	& wr_tid_dec[7:0];
assign asi_wr_tba	[7:0] = 
       {8 {wr_tba_2}}		& wr_tid_dec[7:0];
// Sent a cycle early and flopped locally to sink
assign asi_wr_pstate	[7:0] = 
       {8 {wr_pstate}}		& rd_tid_dec[7:0];
assign asi_wr_tl	[7:0] = 
       {8 {wr_tl_2}}		& wr_tid_dec[7:0];
assign asi_wr_pil	[7:0] = 
       {8 {wr_pil_2}}		& wr_tid_dec[7:0];
assign asi_wr_gl	[7:0] = 
       {8 {wr_gl_2}}		& wr_tid_dec[7:0];
// Sent a cycle early and flopped locally to sink
assign asi_wr_hpstate	[7:0] = 
       {8 {wr_hpstate}}		& rd_tid_dec[7:0];
assign asi_wr_hintp	[7:0] = 
       {8 {wr_hintp_2}}		& wr_tid_dec[7:0];
assign asi_wr_htba	[7:0] = 
       {8 {wr_htba_2}}		& wr_tid_dec[7:0];
assign asi_rd_dsfar =
       rd_dsfar;
assign asi_rd_desr =
       rd_desr;
assign asi_rd_fesr =
       rd_fesr;
assign asi_wr_isfsr[7:0] =
       {8 {wr_isfsr_2}}		& wr_tid_dec[7:0] ;
assign asi_wr_iaw[1:0] =
       {2 {wr_iaw_2}}		& {data_2[58], ~data_2[58]};
assign asi_wr_dsfsr[7:0] =
       {8 {wr_dsfsr_2}}		& wr_tid_dec[7:0] ;
assign asi_wr_dsfar[7:0] =
       {8 {wr_dsfar_2}}		& wr_tid_dec[7:0] ;

assign asi_trl_pstate_en[1:0] =
       {2 {wr_hpstate_2 | wr_pstate_2}} & {data_2[58], ~data_2[58]};

// Pipe Interrupt Receive Register clear controls to check if the register
// is actually cleared out entirely
assign irl_any_cleared_in =
       rd_inc_vec_2 | wr_int_rec_2;

tlu_asi_ctl_msff_ctl_macro__width_1 irl_any_cleared_lat  (
	.scan_in(irl_any_cleared_lat_scanin),
	.scan_out(irl_any_cleared_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(irl_any_cleared_in		),
	.dout	(irl_any_cleared		),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid_dec_3[7:0] = 
       { data_3[58] &  data_3[57] &  data_3[56], 
         data_3[58] &  data_3[57] & ~data_3[56], 
         data_3[58] & ~data_3[57] &  data_3[56], 
         data_3[58] & ~data_3[57] & ~data_3[56], 
        ~data_3[58] &  data_3[57] &  data_3[56], 
        ~data_3[58] &  data_3[57] & ~data_3[56], 
        ~data_3[58] & ~data_3[57] &  data_3[56], 
        ~data_3[58] & ~data_3[57] & ~data_3[56]};

assign asi_irl_cleared[7:0] =
       {8 {irl_any_cleared}} & tid_dec_3[7:0];

// Maintain TICK.NPT per thread
// TICK.NPT PORs to a 1, so store negative active
assign tick_npt_in_[7:0] =
       ( (wr_tid_dec[7:0] & {8 {wr_tick_2}}) & {8 {~data_1[63]}}) | 
       (~(wr_tid_dec[7:0] & {8 {wr_tick_2}}) & tick_npt_[7:0]) ; 

tlu_asi_ctl_msff_ctl_macro__width_8 tick_npt_inv_lat  (
	.scan_in(tick_npt_inv_lat_scanin),
	.scan_out(tick_npt_inv_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tick_npt_in_		[7:0]	),
	.dout	(tick_npt_		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign tick_npt_2_ =
       | (tick_npt_[7:0] & wr_tid_dec[7:0]);

tlu_asi_ctl_msff_ctl_macro__width_1 tick_npt_3_inv_lat  (
	.scan_in(tick_npt_3_inv_lat_scanin),
	.scan_out(tick_npt_3_inv_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tick_npt_2_			),
	.dout	(tick_npt_3_			),
  .siclk(siclk),
  .soclk(soclk)
);

// Maintain decr
assign decr_reg_in[63:46] =
	({18 {~wr_decr_2}} & decr_reg	[63:46]) |
	({18 { wr_decr_2}} & data_1	[63:46]) ;

tlu_asi_ctl_msff_ctl_macro__width_18 decr_lat  (
	.scan_in(decr_lat_scanin),
	.scan_out(decr_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(decr_reg_in		[63:46]	),
	.dout	(decr_reg		[63:46]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_decr[63:46] =
	decr_reg[63:46];

// Mux ctl and data

assign rd_pct_2 =
       rd_pc_2 | rd_iaw_2;

assign trl_data[64:0] =
       { {48 {1'b0}}, 
	(trl1_asi_data[16:0] & {17 { data_3[58]}}) |
       	(trl0_asi_data[16:0] & {17 {~data_3[58]}})  };

assign tsd_data[64:48] =
       {17 {1'b0}};
assign tsd_data[47:2] = 
       (pct1_asi_data[47:2] & {46 { data_3[58]}}) |
       (pct0_asi_data[47:2] & {46 {~data_3[58]}}) ;
assign tsd_data[1:0] = 
       (tsd1_asi_data[1:0] & { 2 { data_3[58]}}) |
       (tsd0_asi_data[1:0] & { 2 {~data_3[58]}}) ;

assign tba_htba_data[64] =
       tsd_data[64];
assign tba_htba_data[63:48] = 
       {16 {(pct1_asi_data[47] &  data_3[58]) |
            (pct0_asi_data[47] & ~data_3[58])}} ;
assign tba_htba_data[47:0] =
       tsd_data[47:0];

assign tsa_nopc_data[64:0] =
       tsd_data[64:0];

assign tsa_pc_data[64] = 1'b0;
assign tsa_pc_data[63:48] = 
       ({16 { data_3[58]}} & {16 {pct1_asi_data[47   ]}}) |
       ({16 {~data_3[58]}} & {16 {pct0_asi_data[47   ]}}) ;
assign tsa_pc_data[47:0] =
       tsd_data[47:0];

assign tsa_ecc_data[64:0] =
       {{49 {1'b0}}, 
	({16 { data_3[58]}} & tel1_ecc[15:0]) |
	({16 {~data_3[58]}} & tel0_ecc[15:0])  };

assign tic_data[64:0] =
       {1'b0, ~tic_asi_data[63], tic_asi_data[62:0]};
// 
// Force bits 6:0 of %stick to 1s
// Synthesis combined the rd_tic_3 and rd_tick_3 paths for bits 6:0
// rd_tick_3 is required in the data bits
assign tic_data_for_3[64:0] =
       tic_data[64:0] |
       {{58 {1'b0}}, {7 {data_3[52] & rd_tick_3}}};
assign tick_data[64:0] =
       {1'b0, ~tick_npt_3_, tic_asi_data[62:0]} |
       {{58 {1'b0}}, {7 {data_3[52] & rd_tick_3}}};

assign pct_data[64] =
       {1 {1'b0}};
assign pct_data[63:2] =
       ({{16 {pct1_asi_data[47]}}, pct1_asi_data[47:2]} & {62 { data_3[58]}}) |
       ({{16 {pct0_asi_data[47]}}, pct0_asi_data[47:2]} & {62 {~data_3[58]}}) ;
assign pct_data[1] =
       {1 {1'b0}};
assign pct_data[0] =
       (pct1_asi_data[48] &  data_3[58]) |
       (pct0_asi_data[48] & ~data_3[58]) ;

assign rngf_cdbus_2[64:0] =
       {ctl_2, data_2[63:0]};

assign no_rd_3 = ~rd_trl_3 & ~rd_tsd_3 & ~rd_tba_htba_3 & 
       ~rd_tsa_pc_3 & ~rd_tsa_ecc_3 & ~rd_tsa_nopc_3 &
       ~rd_tic_3 & ~rd_tick_3 & ~rd_pct_3;

assign data_3_in[64:0] = 
       ({65 {no_rd_3      }} & rngf_cdbus_2	[64:0]) |
       ({65 {rd_trl_3     }} & trl_data 	[64:0]) |
       ({65 {rd_tsd_3     }} & tsd_data 	[64:0]) |
       ({65 {rd_tba_htba_3}} & tba_htba_data 	[64:0]) |
       ({65 {rd_tsa_pc_3  }} & tsa_pc_data	[64:0]) |
       ({65 {rd_tsa_ecc_3 }} & tsa_ecc_data	[64:0]) |
       ({65 {rd_tsa_nopc_3}} & tsa_nopc_data	[64:0]) |
       ({65 {rd_tic_3     }} & tic_data_for_3	[64:0]) |
       ({65 {rd_tick_3    }} & tick_data	[64:0]) |
       ({65 {rd_pct_3     }} & pct_data 	[64:0]) ;

assign rd_tca_diag_2 =
       rd_tca_ecc_2 | rd_tca_data_2;


/////////////////////////////////////////////////////////////////////
//STAGE 3
/////////////////////////////////////////////////////////////////////
// Mux previous results with TSA reads

tlu_asi_ctl_msff_ctl_macro__width_65 rng_stg3  (
	.scan_in(rng_stg3_scanin),
	.scan_out(rng_stg3_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(data_3_in		[64:0]	),
	.dout	(data_3			[64:0]	),
  .siclk(siclk),
  .soclk(soclk)
);


tlu_asi_ctl_msff_ctl_macro__width_23 tsa_wr_lat  (
	.scan_in(tsa_wr_lat_scanin),
	.scan_out(tsa_wr_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	({rd_tsa_nopc_2,
		  rd_tsa_pc_2,
		  rd_tsa_ecc_2,
		  rd_tic_2,
		  rd_tick_2,
		  rd_trl_2,
		  rd_pct_2,
		  rd_tsd_2,
		  rd_tba_htba_2,
		  rd_tca_diag_2,
		  wr_mondo_head_2,
		  wr_mondo_tail_2,
		  wr_device_head_2,
		  wr_device_tail_2,
		  wr_res_err_head_2,
		  wr_res_err_tail_2,
		  wr_nonres_err_head_2,
		  wr_nonres_err_tail_2,
		  wr_tpc_2,
		  wr_tnpc_2,
		  wr_tstate_2,
		  wr_tt_2,
		  wr_htstate_2		       }),
	.dout	({rd_tsa_nopc_3,
		  rd_tsa_pc_3,
		  rd_tsa_ecc_3,
		  rd_tic_3,
		  rd_tick_3,
		  rd_trl_3,
		  rd_pct_3,
		  rd_tsd_3,
		  rd_tba_htba_3,
		  rd_tca_diag_3,
		  wr_mondo_head_3,
		  wr_mondo_tail_3,
		  wr_device_head_3,
		  wr_device_tail_3,
		  wr_res_err_head_3,
		  wr_res_err_tail_3,
		  wr_nonres_err_head_3,
		  wr_nonres_err_tail_3,
		  wr_tpc_3,
		  wr_tnpc_3,
		  wr_tstate_3,
		  wr_tt_3,
		  wr_htstate_3		       }),
  .siclk(siclk),
  .soclk(soclk)
);
 

// Since these access the TSA, need to send control one cycles later than
// normal
assign asi_wr_mondo_head	[1:0] = 
       {2 {wr_mondo_head_3}}		& {data_3[58], ~data_3[58]};
assign asi_wr_mondo_tail	[1:0] = 
       {2 {wr_mondo_tail_3}}		& {data_3[58], ~data_3[58]};
assign asi_wr_device_head	[1:0] = 
       {2 {wr_device_head_3}}		& {data_3[58], ~data_3[58]};
assign asi_wr_device_tail	[1:0] = 
       {2 {wr_device_tail_3}}		& {data_3[58], ~data_3[58]};
assign asi_wr_res_err_head	[1:0] = 
       {2 {wr_res_err_head_3}}		& {data_3[58], ~data_3[58]};
assign asi_wr_res_err_tail	[1:0] = 
       {2 {wr_res_err_tail_3}}		& {data_3[58], ~data_3[58]};
assign asi_wr_nonres_err_head	[1:0] = 
       {2 {wr_nonres_err_head_3}}	& {data_3[58], ~data_3[58]};
assign asi_wr_nonres_err_tail	[1:0] = 
       {2 {wr_nonres_err_tail_3}}	& {data_3[58], ~data_3[58]};
assign asi_wr_tpc		[1:0] = 
       {2 {wr_tpc_3}}			& {data_3[58], ~data_3[58]};
assign asi_wr_tnpc		[1:0] = 
       ({2 {wr_tnpc_3}}			& {data_3[58], ~data_3[58]}) |
       {2 {mbist_run}};
assign asi_wr_tstate		[1:0] = 
       {2 {wr_tstate_3}}		& {data_3[58], ~data_3[58]};
assign asi_wr_tt		[1:0] = 
       {2 {wr_tt_3}}			& {data_3[58], ~data_3[58]};
assign asi_wr_htstate		[1:0] = 
       {2 {wr_htstate_3}}		& {data_3[58], ~data_3[58]};


// Do not need to check for interrupt if nonres_err registers are written
assign wr_iqr_3 =
       wr_mondo_head_3 | wr_mondo_tail_3 | wr_device_head_3 | wr_device_tail_3 |
       wr_res_err_head_3 | wr_res_err_tail_3;

// Check for ECC errors
assign check_ecc =
       | (tlu_ceter_pscce[7:0] &
	  { data_3[58] &  data_3[57] &  data_3[56],
            data_3[58] &  data_3[57] & ~data_3[56],
            data_3[58] & ~data_3[57] &  data_3[56],
            data_3[58] & ~data_3[57] & ~data_3[56],
           ~data_3[58] &  data_3[57] &  data_3[56],
           ~data_3[58] &  data_3[57] & ~data_3[56],
           ~data_3[58] & ~data_3[57] &  data_3[56],
           ~data_3[58] & ~data_3[57] & ~data_3[56]});

assign asi_tccup_in =
       rd_tic_3 & ~rd_tick_3 & check_ecc;
assign asi_tccud_in =
       ~(rd_tic_3 & ~rd_tick_3) & ~rd_tca_diag_3;
assign tsacu_in = 
       (rd_tsa_pc_3 | rd_tsa_nopc_3 | wr_tsa_3) & check_ecc;

assign kill_write_if_error_in = 
       wr_tsa_3 & check_ecc;

tlu_asi_ctl_msff_ctl_macro__width_2 ecc_lat  (
	.scan_in(ecc_lat_scanin),
	.scan_out(ecc_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	({tsacu_in		       ,
		  kill_write_if_error_in       }),
	.dout	({ptsacu		       ,
		  kill_write_if_error	       }),
  .siclk(siclk),
  .soclk(soclk)
);

assign tsac =
       ((tel0_tsac & ~data_4[58]) | 
        (tel1_tsac &  data_4[58]) ) & ptsacu;

assign tsau =
       ((tel0_tsau & ~data_4[58]) | 
        (tel1_tsau &  data_4[58]) ) & ptsacu;

// For killing trap stack write
assign asi_tsacu[1:0] =
       {(tel1_tsac | tel1_tsau) &  data_4[58] & kill_write_if_error,
        (tel0_tsac | tel0_tsau) & ~data_4[58] & kill_write_if_error};

tlu_asi_ctl_msff_ctl_macro__width_2 tca_rd_addr_2_lat  (
	.scan_in(tca_rd_addr_2_lat_scanin),
	.scan_out(tca_rd_addr_2_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tca_rd_addr		[4:3]	),
	.dout	(tca_rd_addr_2		[4:3]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_2 tca_rd_addr_3_lat  (
	.scan_in(tca_rd_addr_3_lat_scanin),
	.scan_out(tca_rd_addr_3_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tca_rd_addr_2		[4:3]	),
	.dout	(tca_rd_addr_3		[4:3]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_2 tca_rd_addr_4_lat  (
	.scan_in(tca_rd_addr_4_lat_scanin),
	.scan_out(tca_rd_addr_4_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tca_rd_addr_3		[4:3]	),
	.dout	(tca_rd_addr_4		[4:3]	),
  .siclk(siclk),
  .soclk(soclk)
);


assign asi_ece_exc =
       tsac | cel_tccp;
assign asi_eue_exc =
       tsau | cel_tcup;
assign asi_ecc_tid[2:0] =
       data_4[58:56];

// For DSFSR
assign asi_tsac =
       tsac;
assign asi_tsau =
       tsau;
assign asi_tsacu_tid[2:0] =
       data_4[58:56];

assign tlu_tca_tid[2:0] = 
       data_4[58:56];
assign tlu_tca_index[1:0] =
       tca_rd_addr_4[4:3];


assign rngf_cdbus_3[64:0] =
       data_3[64:0];

assign data_4_in[64:0] =
       ({65 {~mmu_asi_read}} & rngf_cdbus_3	[64:0]) |	
       ({65 { mmu_asi_read}} & mmu_asi_data	[64:0]) ;

assign error_4_in =
       mmu_asi_cecc | mmu_asi_uecc | cel_tccp | cel_tcup | tsac | tsau;


/////////////////////////////////////////////////////////////////////
//STAGE 4
/////////////////////////////////////////////////////////////////////
// Output latch

tlu_asi_ctl_msff_ctl_macro__width_65 rng_stg4  (
	.scan_in(rng_stg4_scanin),
	.scan_out(rng_stg4_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(data_4_in		[64:0]	),
	.dout	(data_4			[64:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_asi_ctl_msff_ctl_macro__width_1 error_4_lat  (
	.scan_in(error_4_lat_scanin),
	.scan_out(error_4_lat_scanout),
	.din	(error_4_in			),
	.dout	(error_4			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_rngf_cdbus[64:0] =
       data_4[64:0];

assign tlu_rngf_cdbus_error =
       error_4;

assign check_qr_exc_in[3:0] =
       {wr_iqr_3, data_3[58:56]};

tlu_asi_ctl_msff_ctl_macro__width_4 check_qr_exc_lat  (
	.scan_in(check_qr_exc_lat_scanin),
	.scan_out(check_qr_exc_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(check_qr_exc_in	[3:0]	),
	.dout	(check_qr_exc		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_check_qr_exc[7:0] =
       {8 {check_qr_exc[3]}} & 
       { check_qr_exc[2] &  check_qr_exc[1] &  check_qr_exc[0],
         check_qr_exc[2] &  check_qr_exc[1] & ~check_qr_exc[0],
         check_qr_exc[2] & ~check_qr_exc[1] &  check_qr_exc[0],
         check_qr_exc[2] & ~check_qr_exc[1] & ~check_qr_exc[0],
        ~check_qr_exc[2] &  check_qr_exc[1] &  check_qr_exc[0],
        ~check_qr_exc[2] &  check_qr_exc[1] & ~check_qr_exc[0],
        ~check_qr_exc[2] & ~check_qr_exc[1] &  check_qr_exc[0],
        ~check_qr_exc[2] & ~check_qr_exc[1] & ~check_qr_exc[0]};


//////////////////////////////////////////////////////////////////////////////
//
// Error inject staging
//

tlu_asi_ctl_msff_ctl_macro__width_11 error_inject_lat  (
	.scan_in(error_inject_lat_scanin),
	.scan_out(error_inject_lat_scanout),
	.din	({error_inject_enable,
		  error_inject_tccu,
		  error_inject_tsau,
		  error_inject_mask	[7:0]}),
	.dout	({error_enable,
		  error_tccu,
		  error_tsau,
		  error_mask		[7:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_error_tccu =
       error_enable & error_tccu;
assign asi_error_tsau =
       error_enable & error_tsau;
assign asi_error_mask[7:0] =
       error_mask[7:0];


//////////////////////////////////////////////////////////////////////////////
//
// LSU control reg shadow copies
//

assign write_lsu_ctl[7:0] = 
       ({8 { wr_lsu_ctl_2}} &  wr_tid_dec[7:0]) & 
       tlu_lsu_clear_ctl_reg_[7:0];

assign hold_lsu_ctl[7:0] = 
       ({8 {~wr_lsu_ctl_2}} | ~wr_tid_dec[7:0]) & 
       tlu_lsu_clear_ctl_reg_[7:0];

assign spec_enable_in[7:0] =
       (write_lsu_ctl[7:0] & {8 {data_1[4]}}) |
       ( hold_lsu_ctl[7:0] & spec_enable[7:0]) ;

tlu_asi_ctl_msff_ctl_macro__width_8 spec_enable_lat  (
	.scan_in(spec_enable_lat_scanin),
	.scan_out(spec_enable_lat_scanout),
	.din	(spec_enable_in		[7:0]	),
	.dout	(spec_enable		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_spec_enable[7:0] =
       spec_enable[7:0];

assign tlu_spec_enable[7:0] =
       spec_enable[7:0];

assign immu_enable_in[7:0] =
       (write_lsu_ctl[7:0] & {8 {data_1[2]}}) |
       ( hold_lsu_ctl[7:0] & immu_enable[7:0]) ;

tlu_asi_ctl_msff_ctl_macro__width_8 immu_enable_lat  (
	.scan_in(immu_enable_lat_scanin),
	.scan_out(immu_enable_lat_scanout),
	.din	(immu_enable_in		[7:0]	),
	.dout	(immu_enable		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_immu_enable[7:0] =
       immu_enable[7:0];


//////////////////////////////////////////////////////////////////////////////
//
// Spares
//

// Use spare flop 7
tlu_asi_ctl_msff_ctl_macro__scanreverse_1__width_9 spare_8_0_lat  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.din	({rd_halt		       , 
		  wr_halt		       ,
		  {7{1'b0}}		       }),
	.dout	({rd_halt_2		       ,
		  wr_halt_2		       ,
		  unused		[6:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign asi_halt[7:0] =
       {8 {wr_halt_2}} & wr_tid_dec[7:0];

assign asi_clear_spu_trap_req[7:0] =
       {8 {rd_halt_2}} & wr_tid_dec[7:0];


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
// fixscan start:
assign pmen_lat_scanin           = scan_in                  ;
assign stg1_en_lat_scanin        = pmen_lat_scanout         ;
assign stg2_en_lat_scanin        = stg1_en_lat_scanout      ;
assign stg3_en_lat_scanin        = stg2_en_lat_scanout      ;
assign stg4_en_lat_scanin        = stg3_en_lat_scanout      ;
assign mbist_run_lat_scanin      = stg4_en_lat_scanout      ;
assign mbist_tsa0_write_lat_scanin = mbist_run_lat_scanout    ;
assign mbist_tsa1_write_lat_scanin = mbist_tsa0_write_lat_scanout;
assign mbist_tca_write_lat_scanin = mbist_tsa1_write_lat_scanout;
assign mbist_addr_lat_scanin     = mbist_tca_write_lat_scanout;
assign mbist_tsa0_read_lat_scanin = mbist_addr_lat_scanout   ;
assign mbist_tsa1_read_lat_scanin = mbist_tsa0_read_lat_scanout;
assign mbist_tca_read_lat_scanin = mbist_tsa1_read_lat_scanout;
assign mbist_cmpsel_lat_scanin   = mbist_tca_read_lat_scanout;
assign mbist_addr_2_lat_scanin   = mbist_cmpsel_lat_scanout ;
assign mbist_tsa0_read_2_lat_scanin = mbist_addr_2_lat_scanout ;
assign mbist_tsa1_read_2_lat_scanin = mbist_tsa0_read_2_lat_scanout;
assign mbist_tca_read_2_lat_scanin = mbist_tsa1_read_2_lat_scanout;
assign mbist_cmpsel_2_lat_scanin = mbist_tca_read_2_lat_scanout;
assign mbist_wdata_2_lat_scanin  = mbist_cmpsel_2_lat_scanout;
assign mbist_tsa0_read_3_lat_scanin = mbist_wdata_2_lat_scanout;
assign mbist_tsa1_read_3_lat_scanin = mbist_tsa0_read_3_lat_scanout;
assign mbist_tca_read_3_lat_scanin = mbist_tsa1_read_3_lat_scanout;
assign mbist_wdata_3_lat_scanin  = mbist_tca_read_3_lat_scanout;
assign mbist_tsa0_read_4_lat_scanin = mbist_wdata_3_lat_scanout;
assign mbist_tsa1_read_4_lat_scanin = mbist_tsa0_read_4_lat_scanout;
assign compare_data_lat_scanin   = mbist_tsa1_read_4_lat_scanout;
assign tsa0_fail_lat_scanin      = compare_data_lat_scanout ;
assign tsa1_fail_lat_scanin      = tsa0_fail_lat_scanout    ;
assign tca_fail_lat_scanin       = tsa1_fail_lat_scanout    ;
assign compare_lat_scanin        = tca_fail_lat_scanout     ;
assign preempt_trap_lat_scanin   = compare_lat_scanout      ;
assign rng_stg1_data_scanin      = preempt_trap_lat_scanout ;
assign ctl_1_lat_scanin          = rng_stg1_data_scanout    ;
assign hpstatehpriv_lat_scanin   = ctl_1_lat_scanout        ;
assign pstatepriv_lat_scanin     = hpstatehpriv_lat_scanout ;
assign stg2_data_lat_scanin      = pstatepriv_lat_scanout   ;
assign stg2_ctl_lat_scanin       = stg2_data_lat_scanout    ;
assign wr_tid_dec_lat_scanin     = stg2_ctl_lat_scanout     ;
assign irl_any_cleared_lat_scanin = wr_tid_dec_lat_scanout   ;
assign tick_npt_inv_lat_scanin   = irl_any_cleared_lat_scanout;
assign tick_npt_3_inv_lat_scanin = tick_npt_inv_lat_scanout ;
assign decr_lat_scanin           = tick_npt_3_inv_lat_scanout;
assign rng_stg3_scanin           = decr_lat_scanout         ;
assign tsa_wr_lat_scanin         = rng_stg3_scanout         ;
assign ecc_lat_scanin            = tsa_wr_lat_scanout       ;
assign tca_rd_addr_2_lat_scanin  = ecc_lat_scanout          ;
assign tca_rd_addr_3_lat_scanin  = tca_rd_addr_2_lat_scanout;
assign tca_rd_addr_4_lat_scanin  = tca_rd_addr_3_lat_scanout;
assign rng_stg4_scanin           = tca_rd_addr_4_lat_scanout;
assign error_4_lat_scanin        = rng_stg4_scanout         ;
assign check_qr_exc_lat_scanin   = error_4_lat_scanout      ;
assign error_inject_lat_scanin   = check_qr_exc_lat_scanout ;
assign spec_enable_lat_scanin    = error_inject_lat_scanout ;
assign immu_enable_lat_scanin    = spec_enable_lat_scanout  ;
assign spares_scanin             = immu_enable_lat_scanout  ;
assign scan_out                  = spares_scanout           ;

assign clfesr_lat_wmr_scanin     = wmr_scan_in              ;
assign wmr_scan_out              = clfesr_lat_wmr_scanout   ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_64 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [63:0] fdin;
wire [62:0] so;

  input [63:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [63:0] dout;
  output scan_out;
assign fdin[63:0] = din[63:0];


dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_72 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [71:0] fdin;
wire [70:0] so;

  input [71:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [71:0] dout;
  output scan_out;
assign fdin[71:0] = din[71:0];


dff #(72)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[71:0]),
.si({scan_in,so[70:0]}),
.so({so[70:0],scan_out}),
.q(dout[71:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_18 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [17:0] fdin;
wire [16:0] so;

  input [17:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [17:0] dout;
  output scan_out;
assign fdin[17:0] = din[17:0];


dff #(18)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[17:0]),
.si({scan_in,so[16:0]}),
.so({so[16:0],scan_out}),
.q(dout[17:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_65 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [64:0] fdin;
wire [63:0] so;

  input [64:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [64:0] dout;
  output scan_out;
assign fdin[64:0] = din[64:0];


dff #(65)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[64:0]),
.si({scan_in,so[63:0]}),
.so({so[63:0],scan_out}),
.q(dout[64:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_23 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [22:0] fdin;
wire [21:0] so;

  input [22:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [22:0] dout;
  output scan_out;
assign fdin[22:0] = din[22:0];


dff #(23)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[22:0]),
.si({scan_in,so[21:0]}),
.so({so[21:0],scan_out}),
.q(dout[22:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__width_11 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [10:0] fdin;
wire [9:0] so;

  input [10:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [10:0] dout;
  output scan_out;
assign fdin[10:0] = din[10:0];


dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_asi_ctl_msff_ctl_macro__scanreverse_1__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [0:7] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({so[0:7],scan_in}),
.so({scan_out,so[0:7]}),
.q(dout[8:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_cel_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_cel_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tlu_cerer_tccp, 
  tlu_cerer_tcup, 
  tlu_cerer_tccd, 
  tlu_cerer_tcud, 
  ced_syndrome, 
  tca_ecc, 
  ced_cecc_err, 
  ced_uecc_err, 
  asi_tccup_in, 
  asi_tccud_in, 
  scan_out, 
  cel_syndrome, 
  cel_ecc, 
  cel_crit_ecc, 
  cel_tccp, 
  cel_tcup, 
  cel_tccd, 
  cel_tcud);
wire pce_ov;
wire clk;
wire stop;
wire siclk;
wire soclk;
wire se;
wire en;
wire ecc_lat_scanin;
wire ecc_lat_scanout;
wire tccp_in;
wire tcup_in;
wire tccd_in;
wire tcud_in;
wire [7:0] syndrome_in;
wire [7:0] rd_ecc;
wire tccp;
wire tcup;
wire tccd;
wire tcud;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input		tlu_cerer_tccp;		// Correctable precise enable    
input		tlu_cerer_tcup;		// Unorrectable precise enable   
input		tlu_cerer_tccd;		// Correctable disrupting enable 
input		tlu_cerer_tcud;		// Unorrectable disrupting enable

input	[7:0]	ced_syndrome;
input	[7:0]	tca_ecc;

input		ced_cecc_err;
input		ced_uecc_err;

input		asi_tccup_in;
input		asi_tccud_in;


output		scan_out;

output	[7:0]	cel_syndrome;
output	[7:0]	cel_ecc;
output	[7:0]	cel_crit_ecc;

output		cel_tccp;
output		cel_tcup;
output		cel_tccd;
output		cel_tcud;


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign clk      = l2clk;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;
assign en       = 1'b1;


// Data is flopped, but ECC is not...  so flop here

tlu_cel_dp_msff_macro__minbuff_1__width_28 ecc_lat  (
	.scan_in(ecc_lat_scanin),
	.scan_out(ecc_lat_scanout),
	.din	({tca_ecc		[7:0],
		  tccp_in		       ,
		  tcup_in		       ,
		  tccd_in		       ,
		  tcud_in		       ,
		  ced_syndrome		[7:0],
		  syndrome_in		[7:0]}),
	.dout	({rd_ecc		[7:0],
		  tccp			       ,
		  tcup			       ,
		  tccd			       ,
		  tcud			       ,
		  syndrome_in		[7:0],
		  cel_syndrome		[7:0]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign cel_crit_ecc[7:0] =
       rd_ecc[7:0];

tlu_cel_dp_buff_macro__rep_1__width_8 ecc_buf   (
	.din	(rd_ecc			[7:0]	),
	.dout	(cel_ecc		[7:0]	)
);


// Merge error signals
//assign tccp_in = 
//	 cecc_err & tlu_cerer_tccp;
//assign tcup_in = 
//	 uecc_err & tlu_cerer_tcup;
//assign tccd_in = 
//	 cecc_err & tlu_cerer_tccd;
//assign tcud_in = 
//	 uecc_err & tlu_cerer_tcud;
//assign tccp =
//	 cel_tccp & asi_tccup_in;
//assign tcup =
//	 cel_tcup & asi_tccup_in;


tlu_cel_dp_and_macro__ports_3__width_1 tccp_in_and   (
	.din0	(ced_cecc_err			),
	.din1	(tlu_cerer_tccp			),
	.din2	(asi_tccup_in			),
	.dout	(tccp_in			)
);

tlu_cel_dp_and_macro__ports_3__width_1 tcup_in_and   (
	.din0	(ced_uecc_err			),
	.din1	(tlu_cerer_tcup			),
	.din2	(asi_tccup_in			),
	.dout	(tcup_in			)
);

tlu_cel_dp_and_macro__ports_3__width_1 tccd_in_and   (
	.din0	(ced_cecc_err			),
	.din1	(tlu_cerer_tccd			),
	.din2	(asi_tccud_in			),
	.dout	(tccd_in			)
);

tlu_cel_dp_and_macro__ports_3__width_1 tcud_in_and   (
	.din0	(ced_uecc_err			),
	.din1	(tlu_cerer_tcud			),
	.din2	(asi_tccud_in			),
	.dout	(tcud_in			)
);


assign cel_tccp =
       tccp;

assign cel_tcup =
       tcup;

assign cel_tccd =
       tccd;

assign cel_tcud =
       tcud;


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

// fixscan start:
assign ecc_lat_scanin            = scan_in                  ;
assign scan_out                  = ecc_lat_scanout          ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module tlu_cel_dp_msff_macro__minbuff_1__width_28 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [26:0] so;

  input [27:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [27:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(28)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[27:0]),
.si({scan_in,so[26:0]}),
.so({so[26:0],scan_out}),
.q(dout[27:0])
);


endmodule


//
//   buff macro
//
//


module tlu_cel_dp_buff_macro__rep_1__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_cel_dp_and_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


and3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_cep_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_cep_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  lsu_rngf_cdbus, 
  asi_stg1_en, 
  scan_out, 
  cep_wr_data);
wire pce_ov;
wire clk;
wire stop;
wire siclk;
wire soclk;
wire se;
wire bit63_;
wire asi_lat_scanin;
wire asi_lat_scanout;


input 		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input	[63:0] lsu_rngf_cdbus;

input		asi_stg1_en;


output		scan_out;

output 	[63:0]	cep_wr_data;


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign clk	= l2clk;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;


tlu_cep_dp_inv_macro__left_63__width_1 bit63_inv   (
	.din	(lsu_rngf_cdbus		[63   ]	),
	.dout	(bit63_				)
);

tlu_cep_dp_msff_macro__width_64 asi_lat  (	
	.scan_in(asi_lat_scanin),
	.scan_out(asi_lat_scanout),
	.en	(asi_stg1_en			),
	.din	({bit63_		       ,
		  lsu_rngf_cdbus	[62:0]}),
	.dout	(cep_wr_data		[63:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// fixscan start:
assign asi_lat_scanin            = scan_in                  ;
assign scan_out                  = asi_lat_scanout          ;
// fixscan end:
endmodule


//
//   invert macro
//
//


module tlu_cep_dp_inv_macro__left_63__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cep_dp_msff_macro__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_cer_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_cer_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  asi_rd_cerer, 
  asi_rd_ceter, 
  asi_wr_cerer, 
  asi_ceter_tid, 
  asi_wr_ceter, 
  asi_wr_data, 
  cth_asi_data, 
  scan_out, 
  cer_asi_data, 
  tlu_cerer_ittp, 
  tlu_cerer_itdp, 
  tlu_cerer_ittm, 
  tlu_cerer_hwtwmu, 
  tlu_cerer_hwtwl2, 
  tlu_cerer_icl2c, 
  tlu_cerer_icl2u, 
  tlu_cerer_icl2nd, 
  tlu_cerer_irf, 
  tlu_cerer_frf, 
  tlu_cerer_dttp, 
  tlu_cerer_dttm, 
  tlu_cerer_dtdp, 
  tlu_cerer_dcl2c, 
  tlu_cerer_dcl2u, 
  tlu_cerer_dcl2nd, 
  tlu_cerer_sbdlc, 
  tlu_cerer_sbdlu, 
  tlu_cerer_mrau, 
  tlu_cerer_tsac, 
  tlu_cerer_tsau, 
  tlu_cerer_scac, 
  tlu_cerer_scau, 
  tlu_cerer_tccp, 
  tlu_cerer_tcup, 
  tlu_cerer_sbapp, 
  tlu_cerer_l2c_socc, 
  tlu_cerer_l2u_socu, 
  tlu_cerer_l2nd, 
  tlu_cerer_icvp, 
  tlu_cerer_ictp, 
  tlu_cerer_ictm, 
  tlu_cerer_icdp, 
  tlu_cerer_dcvp, 
  tlu_cerer_dctp, 
  tlu_cerer_dctm, 
  tlu_cerer_dcdp, 
  tlu_cerer_sbdpc, 
  tlu_cerer_sbdpu, 
  tlu_cerer_mamu, 
  tlu_cerer_tccd, 
  tlu_cerer_tcud, 
  tlu_cerer_mal2c, 
  tlu_cerer_mal2u, 
  tlu_cerer_mal2nd, 
  tlu_cerer_cwql2c, 
  tlu_cerer_cwql2u, 
  tlu_cerer_cwql2nd, 
  tlu_ceter_pscce, 
  tlu_ceter_de, 
  tlu_ceter_dhcce);
wire clk;
wire stop;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire [57:22] wr_data_unused;
wire cerer_lat_scanin;
wire cerer_lat_scanout;
wire [63:0] cerer;
wire [23:0] ceter;
wire [23:0] ceter_in;
wire ceter_lat_scanin;
wire ceter_lat_scanout;
wire [62:60] ceter_data;
wire [63:0] read_data;
wire [63:0] asi_data;


input 		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;


input		asi_rd_cerer;
input		asi_rd_ceter;
input		asi_wr_cerer;
input	[2:0]	asi_ceter_tid;
input		asi_wr_ceter;
input	[63:0]	asi_wr_data;

input	[63:0]	cth_asi_data;


output		scan_out;

output	[63:0]	cer_asi_data;

output		tlu_cerer_ittp 		;
output		tlu_cerer_itdp 		;
output		tlu_cerer_ittm 		;
output		tlu_cerer_hwtwmu	;
output		tlu_cerer_hwtwl2 	;
output		tlu_cerer_icl2c 	;
output		tlu_cerer_icl2u 	;
output		tlu_cerer_icl2nd 	;
output		tlu_cerer_irf 		;
output		tlu_cerer_frf 		;
output		tlu_cerer_dttp 		;
output		tlu_cerer_dttm 		;
output		tlu_cerer_dtdp 		;
output		tlu_cerer_dcl2c 	;
output		tlu_cerer_dcl2u 	;
output		tlu_cerer_dcl2nd 	;
output		tlu_cerer_sbdlc 	;
output		tlu_cerer_sbdlu 	;
output		tlu_cerer_mrau 		;
output		tlu_cerer_tsac 		;
output		tlu_cerer_tsau 		;
output		tlu_cerer_scac 		;
output		tlu_cerer_scau 		;
output		tlu_cerer_tccp 		;
output		tlu_cerer_tcup 		;
output		tlu_cerer_sbapp 	;
output		tlu_cerer_l2c_socc 	;
output		tlu_cerer_l2u_socu 	;
output		tlu_cerer_l2nd	 	;
output		tlu_cerer_icvp 		;
output		tlu_cerer_ictp 		;
output		tlu_cerer_ictm 		;
output		tlu_cerer_icdp 		;
output		tlu_cerer_dcvp 		;
output		tlu_cerer_dctp 		;
output		tlu_cerer_dctm 		;
output		tlu_cerer_dcdp 		;
output		tlu_cerer_sbdpc 	;
output		tlu_cerer_sbdpu 	;
output		tlu_cerer_mamu 		;
output		tlu_cerer_tccd 		;
output		tlu_cerer_tcud 		;
output		tlu_cerer_mal2c 	;
output		tlu_cerer_mal2u 	;
output		tlu_cerer_mal2nd 	;
output		tlu_cerer_cwql2c 	;
output		tlu_cerer_cwql2u 	;
output		tlu_cerer_cwql2nd 	;

output	[7:0]	tlu_ceter_pscce;
output	[7:0]	tlu_ceter_de;
output	[7:0]	tlu_ceter_dhcce;


////////////////////////////////////////////////////////////////////////////////

assign clk	= l2clk;
assign stop	= 1'b0;

tlu_cer_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);

assign wr_data_unused[57:56] =
	  asi_wr_data[57:56];
assign wr_data_unused[51   ] =
	  asi_wr_data[51   ];
assign wr_data_unused[49   ] =
	  asi_wr_data[49   ];
assign wr_data_unused[45:41] =
	  asi_wr_data[45:41];
assign wr_data_unused[35:34] =
	  asi_wr_data[35:34];
assign wr_data_unused[26:24] =
	  asi_wr_data[26:24];
assign wr_data_unused[22   ] =
	  asi_wr_data[22   ];


///////////////////////////////////////////////////////////////////////////////
// CERER
// One per core

tlu_cer_dp_msff_macro__minbuff_1__width_48 cerer_lat  (	
	.scan_in(cerer_lat_scanin),
	.scan_out(cerer_lat_scanout),
	.en	(asi_wr_cerer			),
	.din	({asi_wr_data		[63:61],
		  asi_wr_data		[59:58],
		  asi_wr_data		[55:52],
		  asi_wr_data		[50   ],
		  asi_wr_data		[48:46],
		  asi_wr_data		[40:36],
		  asi_wr_data		[33:27],
		  asi_wr_data		[23   ],
		  asi_wr_data		[21:0]}),
	.dout	({cerer			[63:61],
		  cerer			[59:58],
		  cerer			[55:52],
		  cerer			[50   ],
		  cerer			[48:46],
		  cerer			[40:36],
		  cerer			[33:27],
		  cerer			[23   ],
		  cerer			[21:0]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign tlu_cerer_ittp 		= cerer[63];
assign tlu_cerer_itdp 		= cerer[62];
assign tlu_cerer_ittm 		= cerer[61];
assign tlu_cerer_hwtwmu		= cerer[59];
assign tlu_cerer_hwtwl2		= cerer[58];
assign tlu_cerer_icl2c 		= cerer[55];
assign tlu_cerer_icl2u 		= cerer[54];
assign tlu_cerer_icl2nd 	= cerer[53];
assign tlu_cerer_irf 		= cerer[52];
assign tlu_cerer_frf 		= cerer[50];
assign tlu_cerer_dttp 		= cerer[48];
assign tlu_cerer_dttm 		= cerer[47];
assign tlu_cerer_dtdp 		= cerer[46];
assign tlu_cerer_dcl2c 		= cerer[40];
assign tlu_cerer_dcl2u 		= cerer[39];
assign tlu_cerer_dcl2nd 	= cerer[38];
assign tlu_cerer_sbdlc 		= cerer[37];
assign tlu_cerer_sbdlu 		= cerer[36];
assign tlu_cerer_mrau 		= cerer[33];
assign tlu_cerer_tsac 		= cerer[32];
assign tlu_cerer_tsau 		= cerer[31];
assign tlu_cerer_scac 		= cerer[30];
assign tlu_cerer_scau 		= cerer[29];
assign tlu_cerer_tccp 		= cerer[28];
assign tlu_cerer_tcup 		= cerer[27];
assign tlu_cerer_sbapp 		= cerer[23];
assign tlu_cerer_l2c_socc	= cerer[21];
assign tlu_cerer_l2u_socu	= cerer[20];
assign tlu_cerer_l2nd		= cerer[19];
assign tlu_cerer_icvp 		= cerer[18];
assign tlu_cerer_ictp 		= cerer[17];
assign tlu_cerer_ictm 		= cerer[16];
assign tlu_cerer_icdp 		= cerer[15];
assign tlu_cerer_dcvp 		= cerer[14];
assign tlu_cerer_dctp 		= cerer[13];
assign tlu_cerer_dctm 		= cerer[12];
assign tlu_cerer_dcdp 		= cerer[11];
assign tlu_cerer_sbdpc 		= cerer[10];
assign tlu_cerer_sbdpu 		= cerer[9];
assign tlu_cerer_mamu 		= cerer[8];
assign tlu_cerer_tccd 		= cerer[7];
assign tlu_cerer_tcud 		= cerer[6];
assign tlu_cerer_mal2c 		= cerer[5];
assign tlu_cerer_mal2u 		= cerer[4];
assign tlu_cerer_mal2nd 	= cerer[3];
assign tlu_cerer_cwql2c 	= cerer[2];
assign tlu_cerer_cwql2u 	= cerer[1];
assign tlu_cerer_cwql2nd 	= cerer[0];


//////////////////////////////////////////////////////////////////////////////
// CETER
// 4 bits per CETER, 1 per thread

tlu_cer_dp_mux_macro__mux_aodec__ports_8__width_24 ceter_mux    (	
	.din0	({ceter			[23:3],
		  asi_wr_data		[62:60]}),
	.din1	({ceter			[23:6],
		  asi_wr_data		[62:60],
		  ceter			[2:0]}),
	.din2	({ceter			[23:9],
		  asi_wr_data		[62:60],
		  ceter			[5:0]}),
	.din3	({ceter			[23:12],
		  asi_wr_data		[62:60],
		  ceter			[8:0]}),
	.din4	({ceter			[23:15],
		  asi_wr_data		[62:60],
		  ceter			[11:0]}),
	.din5	({ceter			[23:18],
		  asi_wr_data		[62:60],
		  ceter			[14:0]}),
	.din6	({ceter			[23:21],
		  asi_wr_data		[62:60],
		  ceter			[17:0]}),
	.din7	({asi_wr_data		[62:60],
		  ceter			[20:0]}),
	.sel	(asi_ceter_tid		[2:0]	),
	.dout	(ceter_in		[23:0]	)
);

tlu_cer_dp_msff_macro__width_24 ceter_lat  (	
	.scan_in(ceter_lat_scanin),
	.scan_out(ceter_lat_scanout),
	.en	(asi_wr_ceter			),
	.din	(ceter_in		[23:0]	),
	.dout	(ceter			[23:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


assign tlu_ceter_pscce[7:0] =
       {ceter[23], ceter[20], ceter[17], ceter[14],
	ceter[11], ceter[8], ceter[5], ceter[2]};

assign tlu_ceter_de[7:0] =
       {ceter[22], ceter[19], ceter[16], ceter[13],
	ceter[10], ceter[7], ceter[4], ceter[1]};

assign tlu_ceter_dhcce[7:0] =
       {ceter[21], ceter[18], ceter[15], ceter[12],
	ceter[9], ceter[6], ceter[3], ceter[0]};


//////////////////////////////////////////////////////////////////////////////
tlu_cer_dp_mux_macro__mux_aodec__ports_8__width_3 ceter_data_mux    (
	.din0	(ceter			[2:0]	),
	.din1	(ceter			[5:3]	),
	.din2	(ceter			[8:6]	),
	.din3	(ceter			[11:9]	),
	.din4	(ceter			[14:12]	),
	.din5	(ceter			[17:15]	),
	.din6	(ceter			[20:18]	),
	.din7	(ceter			[23:21]	),
	.sel	(asi_ceter_tid		[2:0]	),
	.dout	(ceter_data		[62:60]	)
);

tlu_cer_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_49 read_data_mux     (
	.din0	({cerer			[63:61],
		  1'b0			       ,
		  cerer			[59:58],
		  cerer			[55:52],
		  cerer			[50   ],
		  cerer			[48:46],
		  cerer			[40:36],
		  cerer			[33:27],
		  cerer			[23   ],
		  cerer			[21:0]}),
	.din1	({1'b0			       ,
		  ceter_data		[62:60],
		  {45 {1'b0}}		       }),
	.sel0	(asi_rd_cerer			),
	.sel1	(asi_rd_ceter			),
	.dout	({read_data		 [63:60],
		  read_data		 [59:58],
		  read_data		 [55:52],
		  read_data		 [50   ],
		  read_data		 [48:46],
		  read_data		 [40:36],
		  read_data		 [33:27],
		  read_data		 [23   ],
		  read_data		 [21:0]})
);

assign asi_data[63:0] =
       {read_data[63:60],
	read_data[59:58],
	{2 {1'b0}},
	read_data[55:52],
	{1 {1'b0}},
	read_data[50   ],
	{1 {1'b0}},
	read_data[48:46],
	{5 {1'b0}},
	read_data[40:36],
	{2 {1'b0}},
	read_data[33:27],
	{3 {1'b0}},
	read_data[23   ],
	{1 {1'b0}},
	read_data[21:0]};
       

tlu_cer_dp_or_macro__ports_2__width_64 asi_data_or   (
	.din0	(cth_asi_data		[63:0]	),
	.din1	(asi_data		[63:0]	),
	.dout	(cer_asi_data		[63:0]	)
);


// fixscan start:
assign cerer_lat_scanin          = scan_in                  ;
assign ceter_lat_scanin          = cerer_lat_scanout        ;
assign scan_out                  = ceter_lat_scanout        ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module tlu_cer_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cer_dp_msff_macro__minbuff_1__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cer_dp_mux_macro__mux_aodec__ports_8__width_24 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [23:0] din0;
  input [23:0] din1;
  input [23:0] din2;
  input [23:0] din3;
  input [23:0] din4;
  input [23:0] din5;
  input [23:0] din6;
  input [23:0] din7;
  input [2:0] sel;
  output [23:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(24)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[23:0]),
  .in1(din1[23:0]),
  .in2(din2[23:0]),
  .in3(din3[23:0]),
  .in4(din4[23:0]),
  .in5(din5[23:0]),
  .in6(din6[23:0]),
  .in7(din7[23:0]),
.dout(dout[23:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cer_dp_msff_macro__width_24 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [22:0] so;

  input [23:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [23:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(24)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[23:0]),
.si({scan_in,so[22:0]}),
.so({so[22:0],scan_out}),
.q(dout[23:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cer_dp_mux_macro__mux_aodec__ports_8__width_3 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  input [2:0] din3;
  input [2:0] din4;
  input [2:0] din5;
  input [2:0] din6;
  input [2:0] din7;
  input [2:0] sel;
  output [2:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(3)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[2:0]),
  .in1(din1[2:0]),
  .in2(din2[2:0]),
  .in3(din3[2:0]),
  .in4(din4[2:0]),
  .in5(din5[2:0]),
  .in6(din6[2:0]),
  .in7(din7[2:0]),
.dout(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cer_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_49 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [48:0] din0;
  input sel0;
  input [48:0] din1;
  input sel1;
  output [48:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(49)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[48:0]),
  .in1(din1[48:0]),
.dout(dout[48:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_cer_dp_or_macro__ports_2__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;


or2 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_cth_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_cth_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_scan_en_wmr, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lsu_rngf_cdbus, 
  cxi_wr_int_dis, 
  cxi_int_dis_vec, 
  asi_wr_int_rec, 
  asi_rd_inc_vec_2, 
  asi_int_rec_mux_sel_in, 
  asi_rd_int_rec, 
  asi_rd_inc_vec, 
  asi_wr_any_int_rec, 
  asi_wr_data, 
  asi_rd_stage_1, 
  dfd_asi_data, 
  dfd_asi_desr, 
  scan_out, 
  wmr_scan_out, 
  cth_wr_data, 
  cth_asi_data, 
  cth_irl_cleared);
wire clk;
wire en;
wire stop;
wire test;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire [7:0] irl_en;
wire any_irl_en_0_2;
wire any_irl_en_3_5;
wire any_irl_en_6_7;
wire any_irl_en;
wire interrupt_receive7_lat_wmr_scanin;
wire interrupt_receive7_lat_wmr_scanout;
wire [63:0] int_dis;
wire [63:0] int_rec;
wire [63:0] inc_vec;
wire [63:0] int_rec7;
wire interrupt_receive6_lat_wmr_scanin;
wire interrupt_receive6_lat_wmr_scanout;
wire [63:0] int_rec6;
wire interrupt_receive5_lat_wmr_scanin;
wire interrupt_receive5_lat_wmr_scanout;
wire [63:0] int_rec5;
wire interrupt_receive4_lat_wmr_scanin;
wire interrupt_receive4_lat_wmr_scanout;
wire [63:0] int_rec4;
wire interrupt_receive3_lat_wmr_scanin;
wire interrupt_receive3_lat_wmr_scanout;
wire [63:0] int_rec3;
wire interrupt_receive2_lat_wmr_scanin;
wire interrupt_receive2_lat_wmr_scanout;
wire [63:0] int_rec2;
wire interrupt_receive1_lat_wmr_scanin;
wire interrupt_receive1_lat_wmr_scanout;
wire [63:0] int_rec1;
wire interrupt_receive0_lat_wmr_scanin;
wire interrupt_receive0_lat_wmr_scanout;
wire [63:0] int_rec0;
wire int_rec_mux_sel_lat_scanin;
wire int_rec_mux_sel_lat_scanout;
wire [2:0] int_rec_mux_sel;
wire [63:59] rngf_cdbus_unused;
wire [63:0] int_rec_muxed;
wire [2:0] ivr_63_56;
wire [2:0] ivr_55_48;
wire [2:0] ivr_47_40;
wire [2:0] ivr_39_32;
wire [2:0] ivr_31_24;
wire [2:0] ivr_23_16;
wire [2:0] ivr_15_08;
wire [2:0] ivr_07_00;
wire [31:4] ivl_sel;
wire [7:1] incoming_vector_mux_sel;
wire [5:0] incoming_vector_in;
wire incoming_vector_lat_scanin;
wire incoming_vector_lat_scanout;
wire [5:0] incoming_vector;
wire [7:0] dec_inc_vec_first;
wire [63:0] dec_inc_vec;
wire [63:0] int_rec_muxed_;
wire [63:0] int_rec_dis_muxed;
wire wr_int_rec;
wire rd_inc_vec_2;
wire set_clear_same_thread;
wire s_c_idvw_irw_;
wire s_c_idvw_irw;
wire s_c_idvw_ivr_;
wire s_c_idvw_ivr;
wire neither_match;
wire tcu_muxtest_rep0;
wire [7:0] dec_int_dis_first;
wire tcu_muxtest_rep1;
wire [63:0] dec_int_dis;
wire asi_lat_scanin;
wire asi_lat_scanout;
wire [63:0] asi_data;
wire irl_cleared_lat_scanin;
wire irl_cleared_lat_scanout;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		tcu_dectest;
input		tcu_muxtest;

input		tcu_scan_en_wmr;
input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

input	[64:56]	lsu_rngf_cdbus;

input 	[7:0]	cxi_wr_int_dis;		// Interrupt Vector Dispatch packet
input 	[5:0]	cxi_int_dis_vec;	//   from gasket

input	[7:0]	asi_wr_int_rec;		// Write Interrupt Receive Register
input 	[7:0]	asi_rd_inc_vec_2;	// Update Interrupt Vector  Register
input 	[2:0]	asi_int_rec_mux_sel_in;
input 		asi_rd_int_rec;		// Read for any thread
input 		asi_rd_inc_vec;		// Read for any thread
input		asi_wr_any_int_rec;	// Write of any int_rec
input 	[63:0]	asi_wr_data;

input		asi_rd_stage_1;		// Power management

input	[47:0]	dfd_asi_data;		
input	[18:0]	dfd_asi_desr;		


output		scan_out;

output		wmr_scan_out;		// Warm reset (non)scan

output	[61:0]	cth_wr_data;		// Buffered version of asi_wr_data
output	[63:0]	cth_asi_data;
output	[63:0]	cth_irl_cleared;	// Copy of IRR after clearing operations


////////////////////////////////////////////////////////////////////////////////

assign clk      = l2clk;
assign en	= 1'b1;
assign stop	= 1'b0;
assign test	= tcu_dectest;

tlu_cth_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);


//////////////////////////////////////////////////////////////////////////////
//
//  Power management
//

tlu_cth_dp_or_macro__ports_3__width_8 irl_en_or   (
	.din0	(cxi_wr_int_dis		[7:0]	),
	.din1	(asi_wr_int_rec		[7:0]	),
	.din2	(asi_rd_inc_vec_2	[7:0]	),
	.dout	(irl_en			[7:0]	)
);

tlu_cth_dp_or_macro__ports_3__width_1 any_irl_0_2_en_or   (
	.din0	(irl_en			[   0]	),
	.din1	(irl_en			[   1]	),
	.din2	(irl_en			[   2]	),
	.dout	(any_irl_en_0_2			)
);

tlu_cth_dp_or_macro__ports_3__width_1 any_irl_3_5_en_or   (
	.din0	(irl_en			[   3]	),
	.din1	(irl_en			[   4]	),
	.din2	(irl_en			[   5]	),
	.dout	(any_irl_en_3_5			)
);

tlu_cth_dp_or_macro__ports_2__width_1 any_irl_6_7_en_or   (
	.din0	(irl_en			[   6]	),
	.din1	(irl_en			[   7]	),
	.dout	(any_irl_en_6_7			)
);

tlu_cth_dp_or_macro__ports_3__width_1 any_irl_en_or   (
	.din0	(any_irl_en_0_2			),
	.din1	(any_irl_en_3_5			),
	.din2	(any_irl_en_6_7			),
	.dout	(any_irl_en			)
);


////////////////////////////////////////////////////////////////////////////////
//
//  Interrupt Receive Registers
//

tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 interrupt_receive7_lat    ( // FS:wmr_protect
	.scan_in(interrupt_receive7_lat_wmr_scanin),
	.scan_out(interrupt_receive7_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din0	(int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.sel0	(cxi_wr_int_dis		[7   ]	),
	.sel1	(asi_wr_int_rec		[7   ]	),
	.en	(irl_en			[7   ]	),
	.dout	(int_rec7		[63:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 interrupt_receive6_lat    ( // FS:wmr_protect
	.scan_in(interrupt_receive6_lat_wmr_scanin),
	.scan_out(interrupt_receive6_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din0	(int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.sel0	(cxi_wr_int_dis		[6   ]	),
	.sel1	(asi_wr_int_rec		[6   ]	),
	.en	(irl_en			[6   ]	),
	.dout	(int_rec6		[63:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 interrupt_receive5_lat    ( // FS:wmr_protect
	.scan_in(interrupt_receive5_lat_wmr_scanin),
	.scan_out(interrupt_receive5_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din0	(int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.sel0	(cxi_wr_int_dis		[5   ]	),
	.sel1	(asi_wr_int_rec		[5   ]	),
	.en	(irl_en			[5   ]	),
	.dout	(int_rec5		[63:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 interrupt_receive4_lat    ( // FS:wmr_protect
	.scan_in(interrupt_receive4_lat_wmr_scanin),
	.scan_out(interrupt_receive4_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din0	(int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.sel0	(cxi_wr_int_dis		[4   ]	),
	.sel1	(asi_wr_int_rec		[4   ]	),
	.en	(irl_en			[4   ]	),
	.dout	(int_rec4		[63:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 interrupt_receive3_lat    ( // FS:wmr_protect
	.scan_in(interrupt_receive3_lat_wmr_scanin),
	.scan_out(interrupt_receive3_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din0	(int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.sel0	(cxi_wr_int_dis		[3   ]	),
	.sel1	(asi_wr_int_rec		[3   ]	),
	.en	(irl_en			[3   ]	),
	.dout	(int_rec3		[63:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 interrupt_receive2_lat    ( // FS:wmr_protect
	.scan_in(interrupt_receive2_lat_wmr_scanin),
	.scan_out(interrupt_receive2_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din0	(int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.sel0	(cxi_wr_int_dis		[2   ]	),
	.sel1	(asi_wr_int_rec		[2   ]	),
	.en	(irl_en			[2   ]	),
	.dout	(int_rec2		[63:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 interrupt_receive1_lat    ( // FS:wmr_protect
	.scan_in(interrupt_receive1_lat_wmr_scanin),
	.scan_out(interrupt_receive1_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din0	(int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.sel0	(cxi_wr_int_dis		[1   ]	),
	.sel1	(asi_wr_int_rec		[1   ]	),
	.en	(irl_en			[1   ]	),
	.dout	(int_rec1		[63:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 interrupt_receive0_lat    ( // FS:wmr_protect
	.scan_in(interrupt_receive0_lat_wmr_scanin),
	.scan_out(interrupt_receive0_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din0	(int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.sel0	(cxi_wr_int_dis		[0   ]	),
	.sel1	(asi_wr_int_rec		[0   ]	),
	.en	(irl_en			[0   ]	),
	.dout	(int_rec0		[63:0]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


////////////////////////////////////////////////////////////////////////////////
//
//  Mux the Interrupt Receive Registers to either 
//  write (clear bits that are set in write data) or
//  read (encode and clear the MSB)
//

tlu_cth_dp_msff_macro__dmux_8x__left_29__mux_aope__ports_2__width_3 int_rec_mux_sel_lat      (
	.scan_in(int_rec_mux_sel_lat_scanin),
	.scan_out(int_rec_mux_sel_lat_scanout),
	.din0	(lsu_rngf_cdbus		[58:56]	),
	.din1	(asi_int_rec_mux_sel_in	[2:0]	),
	.sel0	(lsu_rngf_cdbus		[64   ]	),
	.en	(1'b1				),
	.dout	(int_rec_mux_sel	[2:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign rngf_cdbus_unused[63:59] =
	lsu_rngf_cdbus[63:59];

tlu_cth_dp_mux_macro__dmux_8x__mux_aodec__ports_8__width_64 int_rec_mux     (
	.din0	(int_rec0		[63:0]	),
	.din1	(int_rec1		[63:0]	),
	.din2	(int_rec2		[63:0]	),
	.din3	(int_rec3		[63:0]	),
	.din4	(int_rec4		[63:0]	),
	.din5	(int_rec5		[63:0]	),
	.din6	(int_rec6		[63:0]	),
	.din7	(int_rec7		[63:0]	),
	.sel	(int_rec_mux_sel	[2:0]	),
	.dout	(int_rec_muxed		[63:0]	)
);


////////////////////////////////////////////////////////////////////////////////
//
//  Clear bits that are set in write data on write to Interrupt Receive Reg
//

tlu_cth_dp_buff_macro__width_62 wr_data_buf  (
	.din	(asi_wr_data		[61:0]	),
	.dout	(cth_wr_data		[61:0]	)
);

tlu_cth_dp_and_macro__ports_2__width_64 int_rec_and   (
	.din0	(int_rec_muxed		[63:0]	),
	.din1	({asi_wr_data		[63:62],
                  cth_wr_data		[61:0]}),
	.dout	(int_rec		[63:0]	)
);


////////////////////////////////////////////////////////////////////////////////
//
//  Encode and clear the MSB on reads from Incoming Vector Register
//

tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 ivr_63_56_mux    (
	.din0	(3'b111				),
	.din1	(3'b110				),
	.din2	(3'b101				),
	.din3	(3'b100				),
	.din4	(3'b011				),
	.din5	(3'b010				),
	.din6	(3'b001				),
	.din7	(3'b000		       		),
	.sel0	(int_rec_muxed		[63   ]	),
	.sel1	(int_rec_muxed		[62   ]	),
	.sel2	(int_rec_muxed		[61   ]	),
	.sel3	(int_rec_muxed		[60   ]	),
	.sel4	(int_rec_muxed		[59   ]	),
	.sel5	(int_rec_muxed		[58   ]	),
	.sel6	(int_rec_muxed		[57   ]	),
	.dout	(ivr_63_56		[2:0]	)
);

tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 ivr_55_48_mux    (
	.din0	(3'b111				),
	.din1	(3'b110				),
	.din2	(3'b101				),
	.din3	(3'b100				),
	.din4	(3'b011				),
	.din5	(3'b010				),
	.din6	(3'b001				),
	.din7	(3'b000		       		),
	.sel0	(int_rec_muxed		[55   ]	),
	.sel1	(int_rec_muxed		[54   ]	),
	.sel2	(int_rec_muxed		[53   ]	),
	.sel3	(int_rec_muxed		[52   ]	),
	.sel4	(int_rec_muxed		[51   ]	),
	.sel5	(int_rec_muxed		[50   ]	),
	.sel6	(int_rec_muxed		[49   ]	),
	.dout	(ivr_55_48		[2:0]	)
);

tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 ivr_47_40_mux    (
	.din0	(3'b111				),
	.din1	(3'b110				),
	.din2	(3'b101				),
	.din3	(3'b100				),
	.din4	(3'b011				),
	.din5	(3'b010				),
	.din6	(3'b001				),
	.din7	(3'b000		       		),
	.sel0	(int_rec_muxed		[47   ]	),
	.sel1	(int_rec_muxed		[46   ]	),
	.sel2	(int_rec_muxed		[45   ]	),
	.sel3	(int_rec_muxed		[44   ]	),
	.sel4	(int_rec_muxed		[43   ]	),
	.sel5	(int_rec_muxed		[42   ]	),
	.sel6	(int_rec_muxed		[41   ]	),
	.dout	(ivr_47_40		[2:0]	)
);

tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 ivr_39_32_mux    (
	.din0	(3'b111				),
	.din1	(3'b110				),
	.din2	(3'b101				),
	.din3	(3'b100				),
	.din4	(3'b011				),
	.din5	(3'b010				),
	.din6	(3'b001				),
	.din7	(3'b000		       		),
	.sel0	(int_rec_muxed		[39   ]	),
	.sel1	(int_rec_muxed		[38   ]	),
	.sel2	(int_rec_muxed		[37   ]	),
	.sel3	(int_rec_muxed		[36   ]	),
	.sel4	(int_rec_muxed		[35   ]	),
	.sel5	(int_rec_muxed		[34   ]	),
	.sel6	(int_rec_muxed		[33   ]	),
	.dout	(ivr_39_32		[2:0]	)
);

tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 ivr_31_24_mux    (
	.din0	(3'b111				),
	.din1	(3'b110				),
	.din2	(3'b101				),
	.din3	(3'b100				),
	.din4	(3'b011				),
	.din5	(3'b010				),
	.din6	(3'b001				),
	.din7	(3'b000		       		),
	.sel0	(int_rec_muxed		[31   ]	),
	.sel1	(int_rec_muxed		[30   ]	),
	.sel2	(int_rec_muxed		[29   ]	),
	.sel3	(int_rec_muxed		[28   ]	),
	.sel4	(int_rec_muxed		[27   ]	),
	.sel5	(int_rec_muxed		[26   ]	),
	.sel6	(int_rec_muxed		[25   ]	),
	.dout	(ivr_31_24		[2:0]	)
);

tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 ivr_23_16_mux    (
	.din0	(3'b111				),
	.din1	(3'b110				),
	.din2	(3'b101				),
	.din3	(3'b100				),
	.din4	(3'b011				),
	.din5	(3'b010				),
	.din6	(3'b001				),
	.din7	(3'b000		       		),
	.sel0	(int_rec_muxed		[23   ]	),
	.sel1	(int_rec_muxed		[22   ]	),
	.sel2	(int_rec_muxed		[21   ]	),
	.sel3	(int_rec_muxed		[20   ]	),
	.sel4	(int_rec_muxed		[19   ]	),
	.sel5	(int_rec_muxed		[18   ]	),
	.sel6	(int_rec_muxed		[17   ]	),
	.dout	(ivr_23_16		[2:0]	)
);

tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 ivr_15_08_mux    (
	.din0	(3'b111				),
	.din1	(3'b110				),
	.din2	(3'b101				),
	.din3	(3'b100				),
	.din4	(3'b011				),
	.din5	(3'b010				),
	.din6	(3'b001				),
	.din7	(3'b000		       		),
	.sel0	(int_rec_muxed		[15   ]	),
	.sel1	(int_rec_muxed		[14   ]	),
	.sel2	(int_rec_muxed		[13   ]	),
	.sel3	(int_rec_muxed		[12   ]	),
	.sel4	(int_rec_muxed		[11   ]	),
	.sel5	(int_rec_muxed		[10   ]	),
	.sel6	(int_rec_muxed		[9   ]	),
	.dout	(ivr_15_08		[2:0]	)
);

tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 ivr_07_00_mux    (
	.din0	(3'b111				),
	.din1	(3'b110				),
	.din2	(3'b101				),
	.din3	(3'b100				),
	.din4	(3'b011				),
	.din5	(3'b010				),
	.din6	(3'b001				),
	.din7	(3'b000		       		),
	.sel0	(int_rec_muxed		[7   ]	),
	.sel1	(int_rec_muxed		[6   ]	),
	.sel2	(int_rec_muxed		[5   ]	),
	.sel3	(int_rec_muxed		[4   ]	),
	.sel4	(int_rec_muxed		[3   ]	),
	.sel5	(int_rec_muxed		[2   ]	),
	.sel6	(int_rec_muxed		[1   ]	),
	.dout	(ivr_07_00		[2:0]	)
);

tlu_cth_dp_nor_macro__ports_2__width_28 ivr_nor  
(	.din0	({int_rec_muxed		[63:60],
		  int_rec_muxed		[55:52],
		  int_rec_muxed		[47:44],
		  int_rec_muxed		[39:36],
		  int_rec_muxed		[31:28],
		  int_rec_muxed		[23:20],
		  int_rec_muxed		[15:12]}),
	.din1	({int_rec_muxed		[59:56],
		  int_rec_muxed		[51:48],
		  int_rec_muxed		[43:40],
		  int_rec_muxed		[35:32],
		  int_rec_muxed		[27:24],
		  int_rec_muxed		[19:16],
		  int_rec_muxed		[11:8]}),
	.dout	(ivl_sel		[31:4]	)
);

tlu_cth_dp_nand_macro__ports_4__width_7 ivr_nand   (
	.din0	({ivl_sel		[31   ],
		  ivl_sel		[27   ],
		  ivl_sel		[23   ],
		  ivl_sel		[19   ],
		  ivl_sel		[15   ],
		  ivl_sel		[11   ],
		  ivl_sel		[7   ]}),
	.din1	({ivl_sel		[30   ],
		  ivl_sel		[26   ],
		  ivl_sel		[22   ],
		  ivl_sel		[18   ],
		  ivl_sel		[14   ],
		  ivl_sel		[10   ],
		  ivl_sel		[6   ]}),
	.din2	({ivl_sel		[29   ],
		  ivl_sel		[25   ],
		  ivl_sel		[21   ],
		  ivl_sel		[17   ],
		  ivl_sel		[13   ],
		  ivl_sel		[9   ],
		  ivl_sel		[5   ]}),
	.din3	({ivl_sel		[28   ],
		  ivl_sel		[24   ],
		  ivl_sel		[20   ],
		  ivl_sel		[16   ],
		  ivl_sel		[12   ],
		  ivl_sel		[8   ],
		  ivl_sel		[4   ]}),
	.dout	(incoming_vector_mux_sel[7:1]	)
);

tlu_cth_dp_mux_macro__dmux_6x__mux_aope__ports_8__width_6 incoming_vector_mux     (
	.din0	({3'b111		       ,
		  ivr_63_56		[2:0]}),
	.din1	({3'b110		       ,
		  ivr_55_48		[2:0]}),
	.din2	({3'b101		       ,
		  ivr_47_40		[2:0]}),
	.din3	({3'b100		       ,
		  ivr_39_32		[2:0]}),
	.din4	({3'b011		       ,
		  ivr_31_24		[2:0]}),
	.din5	({3'b010		       ,
		  ivr_23_16		[2:0]}),
	.din6	({3'b001		       ,
		  ivr_15_08		[2:0]}),
	.din7	({3'b000		       ,
		  ivr_07_00		[2:0]}),
	.sel0	(incoming_vector_mux_sel[7   ]	),
	.sel1	(incoming_vector_mux_sel[6   ]	),
	.sel2	(incoming_vector_mux_sel[5   ]	),
	.sel3	(incoming_vector_mux_sel[4   ]	),
	.sel4	(incoming_vector_mux_sel[3   ]	),
	.sel5	(incoming_vector_mux_sel[2   ]	),
	.sel6	(incoming_vector_mux_sel[1   ]	),
	.dout	(incoming_vector_in	[5:0]	)
);

tlu_cth_dp_msff_macro__width_6 incoming_vector_lat  (
	.scan_in(incoming_vector_lat_scanin),
	.scan_out(incoming_vector_lat_scanout),
	.din	(incoming_vector_in	[5:0]	),
	.dout	(incoming_vector	[5:0]	),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Now decode

tlu_cth_dp_mux_macro__mux_aodec__ports_8__width_8 enc_inc_vec_first_mux    (
	.din0	(8'h01				),
	.din1	(8'h02				),
	.din2	(8'h04				),
	.din3	(8'h08				),
	.din4	(8'h10				),
	.din5	(8'h20				),
	.din6	(8'h40				),
	.din7	(8'h80				),
	.sel	(incoming_vector	[2:0]	),
	.dout	(dec_inc_vec_first	[7:0]	)
);

tlu_cth_dp_mux_macro__mux_aodec__ports_8__width_64 dec_inc_vec_mux    (
	.din0	({56'h00000000000000	       ,
		  dec_inc_vec_first	[7:0]}),
	.din1	({48'h000000000000	       ,
		  dec_inc_vec_first	[7:0],
		  8'h00			       }),
	.din2	({40'h0000000000	       ,
		  dec_inc_vec_first	[7:0],
		  16'h0000		       }),
	.din3	({32'h00000000		       ,
		  dec_inc_vec_first	[7:0],
		  24'h000000		       }),
	.din4	({24'h000000		       ,
		  dec_inc_vec_first	[7:0],
		  32'h00000000		       }),
	.din5	({16'h0000		       ,
		  dec_inc_vec_first	[7:0],
		  40'h0000000000	       }),
	.din6	({8'h00			       ,
		  dec_inc_vec_first	[7:0],
		  48'h000000000000	       }),
	.din7	({dec_inc_vec_first	[7:0],
		  56'h00000000000000	       }),
	.sel	(incoming_vector	[5:3]	),
	.dout	(dec_inc_vec		[63:0]	)
);

// Now mask
tlu_cth_dp_inv_macro__width_64 int_rec_muxed_inv  (
	.din	(int_rec_muxed		[63:0]	),
	.dout	(int_rec_muxed_		[63:0]	)
);

tlu_cth_dp_nor_macro__ports_2__width_64 inc_vec_nor   (
	.din0	(dec_inc_vec		[63:0]	),
	.din1	(int_rec_muxed_		[63:0]	),
	.dout	(inc_vec		[63:0]	)
);


////////////////////////////////////////////////////////////////////////////////
//
//  Decode the Interrupt Dispatch Vector register for write
//    and OR into existing register
//

tlu_cth_dp_mux_macro__mux_aonpe__ports_8__width_64 int_rec_dis_mux    (
	.din0	(int_rec0		[63:0]	),
	.din1	(int_rec1		[63:0]	),
	.din2	(int_rec2		[63:0]	),
	.din3	(int_rec3		[63:0]	),
	.din4	(int_rec4		[63:0]	),
	.din5	(int_rec5		[63:0]	),
	.din6	(int_rec6		[63:0]	),
	.din7	(int_rec7		[63:0]	),
	.sel0	(cxi_wr_int_dis   	[0   ]	),
	.sel1	(cxi_wr_int_dis   	[1   ]	),
	.sel2	(cxi_wr_int_dis   	[2   ]	),
	.sel3	(cxi_wr_int_dis   	[3   ]	),
	.sel4	(cxi_wr_int_dis   	[4   ]	),
	.sel5	(cxi_wr_int_dis   	[5   ]	),
	.sel6	(cxi_wr_int_dis   	[6   ]	),
	.sel7	(cxi_wr_int_dis   	[7   ]	),
	.dout	(int_rec_dis_muxed	[63:0]	)
);

// BUT, still have to clear the bits due to Interrupt Receive write or
// Incoming Vector dispatch
// 

// First figure out if the same thread is involved

tlu_cth_dp_mux_macro__mux_aodec__ports_8__width_3 set_clear_same_thread_mux    (
	.din0	({asi_wr_int_rec	[0   ],
		  asi_rd_inc_vec_2	[0   ],
		  cxi_wr_int_dis   	[0   ]}),
	.din1	({asi_wr_int_rec	[1   ],
		  asi_rd_inc_vec_2	[1   ],
		  cxi_wr_int_dis   	[1   ]}),
	.din2	({asi_wr_int_rec	[2   ],
		  asi_rd_inc_vec_2	[2   ],
		  cxi_wr_int_dis   	[2   ]}),
	.din3	({asi_wr_int_rec	[3   ],
		  asi_rd_inc_vec_2	[3   ],
		  cxi_wr_int_dis   	[3   ]}),
	.din4	({asi_wr_int_rec	[4   ],
		  asi_rd_inc_vec_2	[4   ],
		  cxi_wr_int_dis   	[4   ]}),
	.din5	({asi_wr_int_rec	[5   ],
		  asi_rd_inc_vec_2	[5   ],
		  cxi_wr_int_dis   	[5   ]}),
	.din6	({asi_wr_int_rec	[6   ],
		  asi_rd_inc_vec_2	[6   ],
		  cxi_wr_int_dis   	[6   ]}),
	.din7	({asi_wr_int_rec	[7   ],
		  asi_rd_inc_vec_2	[7   ],
		  cxi_wr_int_dis   	[7   ]}),
	.sel	(int_rec_mux_sel	[2:0]	),
	.dout	({wr_int_rec		       ,
		  rd_inc_vec_2		       ,
		  set_clear_same_thread	       })
);

// Generate a select for Interrupt Receive write

tlu_cth_dp_nand_macro__ports_2__width_1 s_c_idvw_irw_b_nand   (
	.din0	(wr_int_rec			),
	.din1	(set_clear_same_thread		),
	.dout	(s_c_idvw_irw_			)
);

tlu_cth_dp_inv_macro__width_1 s_c_idvw_irw_inv  (
	.din	(s_c_idvw_irw_			),
	.dout	(s_c_idvw_irw			)
);

// Generate a select for Incoming Vector read

tlu_cth_dp_nand_macro__ports_2__width_1 s_c_idvw_ivr_b_nand   (
	.din0	(rd_inc_vec_2			),
	.din1	(set_clear_same_thread		),
	.dout	(s_c_idvw_ivr_			)
);

tlu_cth_dp_inv_macro__width_1 s_c_idvw_ivr_inv  (
	.din	(s_c_idvw_ivr_			),
	.dout	(s_c_idvw_ivr			)
);

// Generate a select for neither matching or for neither write occurring

tlu_cth_dp_and_macro__ports_2__width_1 neither_match_and   (
	.din0	(s_c_idvw_irw_			),
	.din1	(s_c_idvw_ivr_			),
	.dout	(neither_match			)
);


tlu_cth_dp_buff_macro__dbuff_32x__width_1 tst_mux_rep0   (
	.din	(tcu_muxtest			),
	.dout	(tcu_muxtest_rep0		)
);

tlu_cth_dp_mux_macro__mux_pgdec__ports_8__width_8 enc_int_dis_first_mux    (
	.din0	(8'h01				),
	.din1	(8'h02				),
	.din2	(8'h04				),
	.din3	(8'h08				),
	.din4	(8'h10				),
	.din5	(8'h20				),
	.din6	(8'h40				),
	.din7	(8'h80				),
	.sel	(cxi_int_dis_vec	[2:0]	),
	.muxtst	(tcu_muxtest_rep0		),
	.dout	(dec_int_dis_first	[7:0]	),
  .test(test)
);

tlu_cth_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep1   (
	.din	(tcu_muxtest			),
	.dout	(tcu_muxtest_rep1		)
);

tlu_cth_dp_mux_macro__mux_pgdec__ports_8__width_64 dec_int_dis_mux    (
	.din0	({56'h00000000000000	       ,
		  dec_int_dis_first	[7:0]}),
	.din1	({48'h000000000000	       ,
		  dec_int_dis_first	[7:0],
		  8'h00			       }),
	.din2	({40'h0000000000	       ,
		  dec_int_dis_first	[7:0],
		  16'h0000		       }),
	.din3	({32'h00000000		       ,
		  dec_int_dis_first	[7:0],
		  24'h000000		       }),
	.din4	({24'h000000		       ,
		  dec_int_dis_first	[7:0],
		  32'h00000000		       }),
	.din5	({16'h0000		       ,
		  dec_int_dis_first	[7:0],
		  40'h0000000000	       }),
	.din6	({8'h00			       ,
		  dec_int_dis_first	[7:0],
		  48'h000000000000	       }),
	.din7	({dec_int_dis_first	[7:0],
		  56'h00000000000000	       }),
	.sel	(cxi_int_dis_vec	[5:3]	),
	.muxtst	(tcu_muxtest_rep1		),
	.dout	(dec_int_dis		[63:0]	),
  .test(test)
);

// Mux the cleared registers with the base register and
//  OR the new vector in (saves gate levels...)

tlu_cth_dp_mux_macro__mux_aonpe__ports_4__width_64 int_rec_dis_muxed_mux    (
	.din0	(dec_int_dis		[63:0]	),
	.din1	(int_rec		[63:0]	),
	.din2	(inc_vec		[63:0]	),
	.din3	(int_rec_dis_muxed	[63:0]	),
	.sel0	(1'b1				),
	.sel1	(s_c_idvw_irw			),
	.sel2	(s_c_idvw_ivr			),
	.sel3	(neither_match			),
	.dout	(int_dis		[63:0]	)
);


////////////////////////////////////////////////////////////////////////////////
//
//  ASI muxing
//

tlu_cth_dp_msff_macro__mux_aonpe__ports_2__width_64 asi_lat    (
	.scan_in(asi_lat_scanin),
	.scan_out(asi_lat_scanout),
	.din0	(int_rec_muxed		[63:0]	),
	.din1	({58'h000000000000000	       ,
		  incoming_vector_in	[5:0]}),
	.sel0	(asi_rd_int_rec			),
	.sel1	(asi_rd_inc_vec			),
	.en	(asi_rd_stage_1			),
	.dout	(asi_data		[63:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_cth_dp_or_macro__ports_3__width_64 asi_data_or   (
	.din0	({{16 {1'b0}}		       ,
		 dfd_asi_data		[47:0]}),
	.din1	({{45 {1'b0}}		       ,
		 dfd_asi_desr		[18:0]}),
	.din2	(asi_data		[63:0]	),
	.dout	(cth_asi_data		[63:0]	)
);


////////////////////////////////////////////////////////////////////////////////
//
//  Check if the register has any bits set after clear operations
//
						
tlu_cth_dp_msff_macro__mux_aope__ports_2__width_64 irl_cleared_lat    (
	.scan_in(irl_cleared_lat_scanin),
	.scan_out(irl_cleared_lat_scanout),
	.din0	(int_rec		[63:0]	),
	.din1	(inc_vec		[63:0]	),
	.sel0	(asi_wr_any_int_rec		),
	.en	(any_irl_en			),
	.dout	(cth_irl_cleared	[63:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// fixscan start:
assign int_rec_mux_sel_lat_scanin = scan_in                  ;
assign incoming_vector_lat_scanin = int_rec_mux_sel_lat_scanout;
assign asi_lat_scanin            = incoming_vector_lat_scanout;
assign irl_cleared_lat_scanin    = asi_lat_scanout          ;
assign scan_out                  = irl_cleared_lat_scanout  ;

assign interrupt_receive7_lat_wmr_scanin = wmr_scan_in              ;
assign interrupt_receive6_lat_wmr_scanin = interrupt_receive7_lat_wmr_scanout;
assign interrupt_receive5_lat_wmr_scanin = interrupt_receive6_lat_wmr_scanout;
assign interrupt_receive4_lat_wmr_scanin = interrupt_receive5_lat_wmr_scanout;
assign interrupt_receive3_lat_wmr_scanin = interrupt_receive4_lat_wmr_scanout;
assign interrupt_receive2_lat_wmr_scanin = interrupt_receive3_lat_wmr_scanout;
assign interrupt_receive1_lat_wmr_scanin = interrupt_receive2_lat_wmr_scanout;
assign interrupt_receive0_lat_wmr_scanin = interrupt_receive1_lat_wmr_scanout;
assign wmr_scan_out              = interrupt_receive0_lat_wmr_scanout;
// fixscan end:
endmodule


//
//   buff macro
//
//


module tlu_cth_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_cth_dp_or_macro__ports_3__width_8 (
  din0, 
  din1, 
  din2, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  output [7:0] dout;


or3 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.in2(din2[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_cth_dp_or_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


or3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_cth_dp_or_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cth_dp_msff_macro__mux_aope__ports_3__width_64 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cth_dp_msff_macro__dmux_8x__left_29__mux_aope__ports_2__width_3 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [2:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [1:0] so;

  input [2:0] din0;
  input [2:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [2:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(3)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[2:0]),
  .in1(din1[2:0]),
.dout(muxout[2:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__dmux_8x__mux_aodec__ports_8__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input [2:0] sel;
  output [63:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   buff macro
//
//


module tlu_cth_dp_buff_macro__width_62 (
  din, 
  dout);
  input [61:0] din;
  output [61:0] dout;


buff #(62)  d0_0 (
.in(din[61:0]),
.out(dout[61:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_cth_dp_and_macro__ports_2__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;


and2 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__mux_aope__ports_8__width_3 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  input [2:0] din3;
  input [2:0] din4;
  input [2:0] din5;
  input [2:0] din6;
  input [2:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;
  output [2:0] dout;


cl_dp1_penc8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(3)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[2:0]),
  .in1(din1[2:0]),
  .in2(din2[2:0]),
  .in3(din3[2:0]),
  .in4(din4[2:0]),
  .in5(din5[2:0]),
  .in6(din6[2:0]),
  .in7(din7[2:0]),
.dout(dout[2:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module tlu_cth_dp_nor_macro__ports_2__width_28 (
  din0, 
  din1, 
  dout);
  input [27:0] din0;
  input [27:0] din1;
  output [27:0] dout;


nor2 #(28)  d0_0 (
.in0(din0[27:0]),
.in1(din1[27:0]),
.out(dout[27:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_cth_dp_nand_macro__ports_4__width_7 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [6:0] din0;
  input [6:0] din1;
  input [6:0] din2;
  input [6:0] din3;
  output [6:0] dout;


nand4 #(7)  d0_0 (
.in0(din0[6:0]),
.in1(din1[6:0]),
.in2(din2[6:0]),
.in3(din3[6:0]),
.out(dout[6:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__dmux_6x__mux_aope__ports_8__width_6 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [5:0] din0;
  input [5:0] din1;
  input [5:0] din2;
  input [5:0] din3;
  input [5:0] din4;
  input [5:0] din5;
  input [5:0] din6;
  input [5:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;
  output [5:0] dout;


cl_dp1_penc8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(6)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[5:0]),
  .in1(din1[5:0]),
  .in2(din2[5:0]),
  .in3(din3[5:0]),
  .in4(din4[5:0]),
  .in5(din5[5:0]),
  .in6(din6[5:0]),
  .in7(din7[5:0]),
.dout(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cth_dp_msff_macro__width_6 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [4:0] so;

  input [5:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [5:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__mux_aodec__ports_8__width_8 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  input [7:0] din3;
  input [7:0] din4;
  input [7:0] din5;
  input [7:0] din6;
  input [7:0] din7;
  input [2:0] sel;
  output [7:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
  .in4(din4[7:0]),
  .in5(din5[7:0]),
  .in6(din6[7:0]),
  .in7(din7[7:0]),
.dout(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__mux_aodec__ports_8__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input [2:0] sel;
  output [63:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


//
//   invert macro
//
//


module tlu_cth_dp_inv_macro__width_64 (
  din, 
  dout);
  input [63:0] din;
  output [63:0] dout;


inv #(64)  d0_0 (
.in(din[63:0]),
.out(dout[63:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module tlu_cth_dp_nor_macro__ports_2__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output [63:0] dout;


nor2 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__mux_aonpe__ports_8__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  input [63:0] din4;
  input sel4;
  input [63:0] din5;
  input sel5;
  input [63:0] din6;
  input sel6;
  input [63:0] din7;
  input sel7;
  output [63:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__mux_aodec__ports_8__width_3 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  input [2:0] din3;
  input [2:0] din4;
  input [2:0] din5;
  input [2:0] din6;
  input [2:0] din7;
  input [2:0] sel;
  output [2:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(3)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[2:0]),
  .in1(din1[2:0]),
  .in2(din2[2:0]),
  .in3(din3[2:0]),
  .in4(din4[2:0]),
  .in5(din5[2:0]),
  .in6(din6[2:0]),
  .in7(din7[2:0]),
.dout(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_cth_dp_nand_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module tlu_cth_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_cth_dp_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module tlu_cth_dp_buff_macro__dbuff_32x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__mux_pgdec__ports_8__width_8 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  input [7:0] din3;
  input [7:0] din4;
  input [7:0] din5;
  input [7:0] din6;
  input [7:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [7:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
  .in4(din4[7:0]),
  .in5(din5[7:0]),
  .in6(din6[7:0]),
  .in7(din7[7:0]),
.dout(dout[7:0]),
  .muxtst(muxtst)
);


endmodule


//
//   buff macro
//
//


module tlu_cth_dp_buff_macro__dbuff_48x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__mux_pgdec__ports_8__width_64 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  input [63:0] din3;
  input [63:0] din4;
  input [63:0] din5;
  input [63:0] din6;
  input [63:0] din7;
  input [2:0] sel;
  input muxtst;
  input test;
  output [63:0] dout;


cl_dp1_pdec8_8x  c0_0 (
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7),
  .test(test)
);

mux8 #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
  .in4(din4[63:0]),
  .in5(din5[63:0]),
  .in6(din6[63:0]),
  .in7(din7[63:0]),
.dout(dout[63:0]),
  .muxtst(muxtst)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_cth_dp_mux_macro__mux_aonpe__ports_4__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  output [63:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cth_dp_msff_macro__mux_aonpe__ports_2__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_muxbuff2_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(64)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_cth_dp_or_macro__ports_3__width_64 (
  din0, 
  din1, 
  din2, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  input [63:0] din2;
  output [63:0] dout;


or3 #(64)  d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.in2(din2[63:0]),
.out(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cth_dp_msff_macro__mux_aope__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [63:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(muxout[63:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_cxi_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_cxi_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  fls_core_running, 
  fls_ss_request, 
  lsu_cpx_req, 
  lsu_cpx_err, 
  lsu_cpx_sre, 
  lsu_cpx_err_thread_id, 
  lsu_cpx_thread_id, 
  lsu_cpx_valid, 
  lsu_cpx_type, 
  lsu_cpx_vector, 
  lsu_cpx_prefetch, 
  lsu_ext_interrupt, 
  lsu_ext_int_type, 
  lsu_ext_int_vec, 
  lsu_ext_int_tid, 
  trl_ss_complete, 
  asi_irl_cleared, 
  cth_irl_cleared, 
  tlu_cerer_l2c_socc, 
  tlu_cerer_l2u_socu, 
  tlu_cerer_l2nd, 
  scan_out, 
  cxi_xir, 
  cxi_ivt, 
  cxi_wr_int_dis, 
  cxi_int_dis_vec, 
  cxi_l2_soc_sre, 
  cxi_l2_soc_err_type, 
  cxi_l2_soc_tid, 
  cxi_l2_err, 
  cxi_soc_err, 
  spc_ss_complete);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire request_lat_scanin;
wire request_lat_scanout;
wire [1:0] cpx_err;
wire cpx_sre;
wire [2:0] cpx_err_thr_id;
wire [2:0] cpx_thr_id;
wire [3:0] cpx_req;
wire cpx_valid;
wire [1:0] cpx_type;
wire [5:0] cpx_vector;
wire cpx_prefetch;
wire valid_req;
wire [7:0] id_decode;
wire reset_type;
wire xir_excp;
wire ivd_lat_scanin;
wire ivd_lat_scanout;
wire l_ext_interrupt;
wire [1:0] l_ext_int_type;
wire [5:0] l_ext_int_vec;
wire [2:0] l_ext_int_tid;
wire [7:0] ivd_decode;
wire irr_ne_0;
wire hwint_type;
wire ivt_excp;
wire cerer_lat_scanin;
wire cerer_lat_scanout;
wire cerer_l2c_socc;
wire cerer_l2u_socu;
wire cerer_l2nd;
wire valid_l2_err;
wire valid_soc_err;
wire valid_prefetch_err;
wire [7:0] step_pending_in;
wire [7:0] step_pending;
wire step_pending_lat_scanin;
wire step_pending_lat_scanout;
wire ss_complete_in;
wire ss_complete_lat_scanin;
wire ss_complete_lat_scanout;
wire ss_complete;
wire spares_scanin;
wire spares_scanout;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input	[7:0] fls_core_running;
input		fls_ss_request;

input	[3:0] lsu_cpx_req;		// Same as "rtntype" in CPX chapter
input	[1:0]	lsu_cpx_err;		// Error type for errors
input		lsu_cpx_sre;		// software_recoverable_error
input	[2:0]	lsu_cpx_err_thread_id;	// Thread ID from CPX control
input	[2:0]	lsu_cpx_thread_id;	// Thread ID from CPX data
input		lsu_cpx_valid;		// Valid for CPX packet
input	[1:0] lsu_cpx_type;		// Interrupt type
input	[5:0]	lsu_cpx_vector;		// Trap requests from crossbar
input		lsu_cpx_prefetch;	// Prefetch response (not load)

input		lsu_ext_interrupt;	// Write to interrupt vector dispatch
input	[1:0]	lsu_ext_int_type;	// Type for CPX packet
input	[5:0]	lsu_ext_int_vec;	// Interrupt vector
input	[2:0]	lsu_ext_int_tid;

input 	[7:0]	trl_ss_complete;	// Single step is complete 

input	[7:0] asi_irl_cleared;	// Int_Received Reg had bits cleared
input	[63:0]	cth_irl_cleared;	// Copy of IRR after clearing operations

input		tlu_cerer_l2c_socc;	
input		tlu_cerer_l2u_socu;	
input		tlu_cerer_l2nd;	


output		scan_out;

output	[7:0]	cxi_xir;		// External Interrupt Request
output 	[7:0]	cxi_ivt;		// Interrupt Vector Trap Request

output 	[7:0]	cxi_wr_int_dis;		// Interrupt Vector Dispatch packet
output 	[5:0]	cxi_int_dis_vec;	//   from gasket

output		cxi_l2_soc_sre;		// software_recoverable_error
output	[1:0] cxi_l2_soc_err_type;	// C=01, UC=10, ND=11
output	[2:0] cxi_l2_soc_tid;
output		cxi_l2_err;		// L2 error reported
output		cxi_soc_err;		// SOC error reported

output		spc_ss_complete;	// Single step complete for all threads


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;


////////////////////////////////////////////////////////////////////////////////
// Clock header

tlu_cxi_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk 			),
        .l1en   (1'b1			),
        .l1clk  (l1clk			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


// Latch the request

tlu_cxi_ctl_msff_ctl_macro__width_23 request_lat  (
	.scan_in(request_lat_scanin),
	.scan_out(request_lat_scanout),
	.din	({lsu_cpx_err		[1:0],
		  lsu_cpx_sre		       ,
		  lsu_cpx_err_thread_id	[2:0],
		  lsu_cpx_thread_id	[2:0],
		  lsu_cpx_req		[3:0],
		  lsu_cpx_valid		       ,
		  lsu_cpx_type		[1:0],
		  lsu_cpx_vector	[5:0],
		  lsu_cpx_prefetch	       }),
	.dout	({cpx_err		[1:0],
		  cpx_sre		       ,
		  cpx_err_thr_id	[2:0],
		  cpx_thr_id		[2:0],
		  cpx_req		[3:0],
		  cpx_valid		       ,
		  cpx_type		[1:0],
		  cpx_vector		[5:0],
		  cpx_prefetch		       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


//////////////////////////////////////////////////////////////////////////////
//
// XIR decode
//
// decode thread_id

assign valid_req    =  cpx_valid & (cpx_req[3:0] == 4'b0111);

assign id_decode[7:0] =
       {cpx_thr_id[2:0] == 3'b111,
        cpx_thr_id[2:0] == 3'b110,
        cpx_thr_id[2:0] == 3'b101,
        cpx_thr_id[2:0] == 3'b100,
        cpx_thr_id[2:0] == 3'b011,
        cpx_thr_id[2:0] == 3'b010,
        cpx_thr_id[2:0] == 3'b001,
        cpx_thr_id[2:0] == 3'b000};


// process CPX interrupt type

assign reset_type = (cpx_type[1:0] == 2'b01);

assign xir_excp = valid_req & reset_type & (cpx_vector[5:0] == 6'b000011);

assign cxi_xir[7:0] = {8 {xir_excp}} & id_decode[7:0]; 


//////////////////////////////////////////////////////////////////////////////
//
// Interrupt Vector Dispatch decode
//

tlu_cxi_ctl_msff_ctl_macro__width_12 ivd_lat  (
	.scan_in(ivd_lat_scanin),
	.scan_out(ivd_lat_scanout),
	.din	({lsu_ext_interrupt	       ,
		  lsu_ext_int_type	[1:0],
		  lsu_ext_int_vec	[5:0],
		  lsu_ext_int_tid	[2:0]}),
	.dout	({l_ext_interrupt	       ,
		  l_ext_int_type	[1:0],
		  l_ext_int_vec		[5:0],
		  l_ext_int_tid		[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ivd_decode[7:0] =
       {l_ext_int_tid[2:0] == 3'b111,
        l_ext_int_tid[2:0] == 3'b110,
        l_ext_int_tid[2:0] == 3'b101,
        l_ext_int_tid[2:0] == 3'b100,
        l_ext_int_tid[2:0] == 3'b011,
        l_ext_int_tid[2:0] == 3'b010,
        l_ext_int_tid[2:0] == 3'b001,
        l_ext_int_tid[2:0] == 3'b000};


// Check if Interrupt Receive Register is zero   

assign irr_ne_0 = 
       (| cth_irl_cleared[63:0]);


// process  interrupt type

assign hwint_type = (l_ext_int_type[1:0] == 2'b00);

assign ivt_excp = l_ext_interrupt & hwint_type; 

assign cxi_ivt[7:0] = 
       ({8 {ivt_excp}} & ivd_decode[7:0]) |
       ({8 {irr_ne_0}} & asi_irl_cleared[7:0]) ;

assign cxi_wr_int_dis[7:0] = {8 {ivt_excp}} & ivd_decode[7:0];

assign cxi_int_dis_vec[5:0] = l_ext_int_vec[5:0];


//////////////////////////////////////////////////////////////////////////////
//
// L2 and SOC error decode
//

tlu_cxi_ctl_msff_ctl_macro__width_3 cerer_lat  (
	.scan_in(cerer_lat_scanin),
	.scan_out(cerer_lat_scanout),
	.din	({tlu_cerer_l2c_socc	       ,
		  tlu_cerer_l2u_socu	       ,
		  tlu_cerer_l2nd    	       }),
	.dout	({cerer_l2c_socc	       ,
		  cerer_l2u_socu	       ,
		  cerer_l2nd    	       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign valid_l2_err  =  
	cpx_valid & (cpx_req[3:0] == 4'b1100) & 
	((cpx_err[1:0] == 2'b01 & cerer_l2c_socc) |
	 (cpx_err[1:0] == 2'b10 & cerer_l2u_socu) |
	 (cpx_err[1:0] == 2'b11 & cerer_l2nd    ) ) ;
assign valid_soc_err  =  
	cpx_valid & (cpx_req[3:0] == 4'b1101) & 
	((cpx_err[1:0] == 2'b01 & cerer_l2c_socc) |
	 (cpx_err[1:0] == 2'b10 & cerer_l2u_socu) ) ;
assign valid_prefetch_err  =  
	cpx_valid & (cpx_req[3:0] == 4'b0000) & cpx_prefetch & 
	((cpx_err[1:0] == 2'b01 & cerer_l2c_socc) |
	 (cpx_err[1:0] == 2'b10 & cerer_l2u_socu) |
	 (cpx_err[1:0] == 2'b11 & cerer_l2nd    ) ) ;

assign cxi_l2_soc_sre =
       ((cpx_sre | (cpx_req[3:0] == 4'b0000 & cpx_prefetch)) & 
        (cpx_err[1:0] == 2'b01)) | 
       ((cpx_req[3:0] == 4'b1101) & 
        (cpx_err[1:0] == 2'b10)) ;
assign cxi_l2_soc_err_type[1:0] = 
       cpx_err[1:0];
assign cxi_l2_err =
       valid_l2_err | valid_prefetch_err;
assign cxi_soc_err =
       valid_soc_err;

assign cxi_l2_soc_tid[2:0] = 
       cpx_err_thr_id[2:0];


//////////////////////////////////////////////////////////////////////////////
//
// Figure out when all threads have stepped 
//

assign step_pending_in[7:0] =
       ((fls_core_running[7:0] & {8 {fls_ss_request}}) | 
	step_pending[7:0]) & ~trl_ss_complete[7:0];

tlu_cxi_ctl_msff_ctl_macro__width_8 step_pending_lat  (
	.scan_in(step_pending_lat_scanin),
	.scan_out(step_pending_lat_scanout),
	.din	(step_pending_in	[7:0]	),
	.dout	(step_pending		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ss_complete_in =
       (| step_pending[7:0]) & ~(| step_pending_in[7:0]);

tlu_cxi_ctl_msff_ctl_macro__width_1 ss_complete_lat  (
	.scan_in(ss_complete_lat_scanin),
	.scan_out(ss_complete_lat_scanout),
	.din	(ss_complete_in			),
	.dout	(ss_complete			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign spc_ss_complete =
       ss_complete;


//////////////////////////////////////////////////////////////////////////////
//
// Spares
//

tlu_cxi_ctl_spare_ctl_macro__num_1 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk				),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
// fixscan start:
assign request_lat_scanin        = scan_in                  ;
assign ivd_lat_scanin            = request_lat_scanout      ;
assign cerer_lat_scanin          = ivd_lat_scanout          ;
assign step_pending_lat_scanin   = cerer_lat_scanout        ;
assign ss_complete_lat_scanin    = step_pending_lat_scanout ;
assign spares_scanin             = ss_complete_lat_scanout  ;
assign scan_out                  = spares_scanout           ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module tlu_cxi_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cxi_ctl_msff_ctl_macro__width_23 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [22:0] fdin;
wire [21:0] so;

  input [22:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [22:0] dout;
  output scan_out;
assign fdin[22:0] = din[22:0];


dff #(23)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[22:0]),
.si({scan_in,so[21:0]}),
.so({so[21:0],scan_out}),
.q(dout[22:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cxi_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cxi_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cxi_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_cxi_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module tlu_cxi_ctl_spare_ctl_macro__num_1 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));
assign scan_out = so_0;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_dfd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_dfd_dp (
  l2clk, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_in, 
  tcu_scan_en_wmr, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lsu_va_b, 
  pct0_target_b, 
  pct1_target_b, 
  tic_exu_address0_b, 
  tic_exu_address1_b, 
  fls0_dfd_lsu_inst_b, 
  fls1_dfd_lsu_inst_b, 
  tel0_syndrome, 
  tel1_syndrome, 
  tlu_tsa_index_0, 
  tlu_tsa_index_1, 
  ras_dsfar_0, 
  ras_dsfar_1, 
  ras_dsfar_2, 
  ras_dsfar_3, 
  ras_dsfar_4, 
  ras_dsfar_5, 
  ras_dsfar_6, 
  ras_dsfar_7, 
  ras_dsfar_sel_lsu_va, 
  ras_dsfar_sel_ras, 
  ras_dsfar_sel_tsa, 
  ras_desr_et_0, 
  ras_desr_et_1, 
  ras_desr_et_2, 
  ras_desr_et_3, 
  ras_desr_et_4, 
  ras_desr_et_5, 
  ras_desr_et_6, 
  ras_desr_et_7, 
  ras_desr_ea_0, 
  ras_desr_ea_1, 
  ras_desr_ea_2, 
  ras_desr_ea_3, 
  ras_desr_ea_4, 
  ras_desr_ea_5, 
  ras_desr_ea_6, 
  ras_desr_ea_7, 
  ras_desr_me_0, 
  ras_desr_me_1, 
  ras_desr_me_2, 
  ras_desr_me_3, 
  ras_desr_me_4, 
  ras_desr_me_5, 
  ras_desr_me_6, 
  ras_desr_me_7, 
  ras_desr_en, 
  ras_write_desr_1st, 
  ras_write_desr_2nd, 
  ras_fesr_et_0, 
  ras_fesr_et_1, 
  ras_fesr_et_2, 
  ras_fesr_et_3, 
  ras_fesr_et_4, 
  ras_fesr_et_5, 
  ras_fesr_et_6, 
  ras_fesr_et_7, 
  ras_fesr_ea_0, 
  ras_fesr_ea_1, 
  ras_fesr_ea_2, 
  ras_fesr_ea_3, 
  ras_fesr_ea_4, 
  ras_fesr_ea_5, 
  ras_fesr_ea_6, 
  ras_fesr_ea_7, 
  ras_fesr_en, 
  ras_write_fesr, 
  ras_fesr_priv, 
  ras_update_priv, 
  ras_asi_data, 
  ras_rd_dsfar, 
  ras_rd_desr, 
  ras_rd_fesr, 
  asi_wr_dsfar, 
  asi_wr_data, 
  scan_out, 
  wmr_scan_out, 
  dfd_desr_f, 
  dfd_desr_s, 
  dfd_fls_desr_f, 
  dfd_fls_desr_s, 
  dfd_fesr_f, 
  dfd_fesr_priv_0, 
  dfd_fesr_priv_1, 
  dfd_fesr_priv_2, 
  dfd_fesr_priv_3, 
  dfd_fesr_priv_4, 
  dfd_fesr_priv_5, 
  dfd_fesr_priv_6, 
  dfd_fesr_priv_7, 
  dfd_asi_data, 
  dfd_asi_desr);
wire clk;
wire stop;
wire en;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire [54:48] wr_data_unused;
wire [61:0] wr_data;
wire lsu_br_va_0_lat_scanin;
wire lsu_br_va_0_lat_scanout;
wire [47:0] lsu_br_va_0_w;
wire lsu_br_va_1_lat_scanin;
wire lsu_br_va_1_lat_scanout;
wire [47:0] lsu_br_va_1_w;
wire va_0_w1_lat_scanin;
wire va_0_w1_lat_scanout;
wire [47:0] va_0_w1;
wire va_1_w1_lat_scanin;
wire va_1_w1_lat_scanout;
wire [47:0] va_1_w1;
wire dsfar_0_lat_wmr_scanin;
wire dsfar_0_lat_wmr_scanout;
wire [47:0] dsfar_0;
wire dsfar_1_lat_wmr_scanin;
wire dsfar_1_lat_wmr_scanout;
wire [47:0] dsfar_1;
wire dsfar_2_lat_wmr_scanin;
wire dsfar_2_lat_wmr_scanout;
wire [47:0] dsfar_2;
wire dsfar_3_lat_wmr_scanin;
wire dsfar_3_lat_wmr_scanout;
wire [47:0] dsfar_3;
wire dsfar_4_lat_wmr_scanin;
wire dsfar_4_lat_wmr_scanout;
wire [47:0] dsfar_4;
wire dsfar_5_lat_wmr_scanin;
wire dsfar_5_lat_wmr_scanout;
wire [47:0] dsfar_5;
wire dsfar_6_lat_wmr_scanin;
wire dsfar_6_lat_wmr_scanout;
wire [47:0] dsfar_6;
wire dsfar_7_lat_wmr_scanin;
wire dsfar_7_lat_wmr_scanout;
wire [47:0] dsfar_7;
wire desr_0_lat_wmr_scanin;
wire desr_0_lat_wmr_scanout;
wire [63:0] desr_0;
wire desr_1_lat_wmr_scanin;
wire desr_1_lat_wmr_scanout;
wire [63:0] desr_1;
wire desr_2_lat_wmr_scanin;
wire desr_2_lat_wmr_scanout;
wire [63:0] desr_2;
wire desr_3_lat_wmr_scanin;
wire desr_3_lat_wmr_scanout;
wire [63:0] desr_3;
wire desr_4_lat_wmr_scanin;
wire desr_4_lat_wmr_scanout;
wire [63:0] desr_4;
wire desr_5_lat_wmr_scanin;
wire desr_5_lat_wmr_scanout;
wire [63:0] desr_5;
wire desr_6_lat_wmr_scanin;
wire desr_6_lat_wmr_scanout;
wire [63:0] desr_6;
wire desr_7_lat_wmr_scanin;
wire desr_7_lat_wmr_scanout;
wire [63:0] desr_7;
wire fesr_0_lat_wmr_scanin;
wire fesr_0_lat_wmr_scanout;
wire [61:55] fesr_0;
wire fesr_1_lat_wmr_scanin;
wire fesr_1_lat_wmr_scanout;
wire [61:55] fesr_1;
wire fesr_2_lat_wmr_scanin;
wire fesr_2_lat_wmr_scanout;
wire [61:55] fesr_2;
wire fesr_3_lat_wmr_scanin;
wire fesr_3_lat_wmr_scanout;
wire [61:55] fesr_3;
wire fesr_4_lat_wmr_scanin;
wire fesr_4_lat_wmr_scanout;
wire [61:55] fesr_4;
wire fesr_5_lat_wmr_scanin;
wire fesr_5_lat_wmr_scanout;
wire [61:55] fesr_5;
wire fesr_6_lat_wmr_scanin;
wire fesr_6_lat_wmr_scanout;
wire [61:55] fesr_6;
wire fesr_7_lat_wmr_scanin;
wire fesr_7_lat_wmr_scanout;
wire [61:55] fesr_7;
wire [47:0] dsfar;
wire [18:0] desr;
wire [6:0] fesr;


input		l2clk;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		scan_in;

input		tcu_scan_en_wmr;
input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

// DSFARs
input	[47:0]	lsu_va_b;
input	[47:2] pct0_target_b;
input	[47:2] pct1_target_b;
input	[1:0]	tic_exu_address0_b;
input	[1:0]	tic_exu_address1_b;
input		fls0_dfd_lsu_inst_b;
input		fls1_dfd_lsu_inst_b;
input	[15:0]	tel0_syndrome;
input	[15:0]	tel1_syndrome;
input	[2:0]	tlu_tsa_index_0;
input	[2:0]	tlu_tsa_index_1;
input	[19:0]	ras_dsfar_0;
input	[19:0]	ras_dsfar_1;
input	[19:0]	ras_dsfar_2;
input	[19:0]	ras_dsfar_3;
input	[19:0]	ras_dsfar_4;
input	[19:0]	ras_dsfar_5;
input	[19:0]	ras_dsfar_6;
input	[19:0]	ras_dsfar_7;
input	[7:0] ras_dsfar_sel_lsu_va;
input	[7:0] ras_dsfar_sel_ras;
input	[7:0] ras_dsfar_sel_tsa;

// DESRs
input	[61:56]	ras_desr_et_0;
input	[61:56]	ras_desr_et_1;
input	[61:56]	ras_desr_et_2;
input	[61:56]	ras_desr_et_3;
input	[61:56]	ras_desr_et_4;
input	[61:56]	ras_desr_et_5;
input	[61:56]	ras_desr_et_6;
input	[61:56]	ras_desr_et_7;
input	[10:0]	ras_desr_ea_0;
input	[10:0]	ras_desr_ea_1;
input	[10:0]	ras_desr_ea_2;
input	[10:0]	ras_desr_ea_3;
input	[10:0]	ras_desr_ea_4;
input	[10:0]	ras_desr_ea_5;
input	[10:0]	ras_desr_ea_6;
input	[10:0]	ras_desr_ea_7;
input		ras_desr_me_0;
input		ras_desr_me_1;
input		ras_desr_me_2;
input		ras_desr_me_3;
input		ras_desr_me_4;
input		ras_desr_me_5;
input		ras_desr_me_6;
input		ras_desr_me_7;
input	[7:0]	ras_desr_en;
input	[7:0]	ras_write_desr_1st;
input	[7:0]	ras_write_desr_2nd;

// FESRs
input	[61:60]	ras_fesr_et_0;
input	[61:60]	ras_fesr_et_1;
input	[61:60]	ras_fesr_et_2;
input	[61:60]	ras_fesr_et_3;
input	[61:60]	ras_fesr_et_4;
input	[61:60]	ras_fesr_et_5;
input	[61:60]	ras_fesr_et_6;
input	[61:60]	ras_fesr_et_7;
input	[59:55]	ras_fesr_ea_0;
input	[59:55]	ras_fesr_ea_1;
input	[59:55]	ras_fesr_ea_2;
input	[59:55]	ras_fesr_ea_3;
input	[59:55]	ras_fesr_ea_4;
input	[59:55]	ras_fesr_ea_5;
input	[59:55]	ras_fesr_ea_6;
input	[59:55]	ras_fesr_ea_7;
input	[7:0]	ras_fesr_en;
input	[7:0]	ras_write_fesr;
input	[59:58] ras_fesr_priv;
input	[7:0] ras_update_priv;

input	[3:0] ras_asi_data;
input	[7:0]	ras_rd_dsfar;
input	[7:0]	ras_rd_desr;
input	[7:0]	ras_rd_fesr;


input	[7:0]	asi_wr_dsfar;
input	[61:0]	asi_wr_data;


output		scan_out;

output		wmr_scan_out;		// Warm reset (non)scan

output	[7:0]	dfd_desr_f;
output	[7:0]	dfd_desr_s;
output	[7:0]	dfd_fls_desr_f;
output	[7:0]	dfd_fls_desr_s;
output	[7:0]	dfd_fesr_f;
output	[1:0]	dfd_fesr_priv_0;
output	[1:0]	dfd_fesr_priv_1;
output	[1:0]	dfd_fesr_priv_2;
output	[1:0]	dfd_fesr_priv_3;
output	[1:0]	dfd_fesr_priv_4;
output	[1:0]	dfd_fesr_priv_5;
output	[1:0]	dfd_fesr_priv_6;
output	[1:0]	dfd_fesr_priv_7;

output	[47:0]	dfd_asi_data;
output	[18:0]	dfd_asi_desr;


//////////////////////////////////////////////////////////////////////

assign clk	= l2clk;
assign stop	= 1'b0;
assign en	= 1'b1;

tlu_dfd_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);

assign wr_data_unused[54:48] =
       asi_wr_data[54:48];

assign wr_data[61:55] =
       asi_wr_data[61:55];
assign wr_data[47:0] =
       asi_wr_data[47:0];


//////////////////////////////////////////////////////////////////////
//
// DSFARs
//

// First mux the LSU and EXU addresses together and flop for next cycle
tlu_dfd_dp_msff_macro__mux_aope__ports_2__stack_48c__width_48 lsu_br_va_0_lat     (
	.scan_in(lsu_br_va_0_lat_scanin),
	.scan_out(lsu_br_va_0_lat_scanout),
	.din0 	(lsu_va_b		[47:0]	),
	.din1 	({pct0_target_b		[47:2],
		  tic_exu_address0_b	[1:0]}),
	.sel0 	(fls0_dfd_lsu_inst_b		),
	.en 	(1'b1				),
	.dout	(lsu_br_va_0_w		[47:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__mux_aope__ports_2__stack_48c__width_48 lsu_br_va_1_lat     (
	.scan_in(lsu_br_va_1_lat_scanin),
	.scan_out(lsu_br_va_1_lat_scanout),
	.din0 	(lsu_va_b		[47:0]	),
	.din1 	({pct1_target_b		[47:2],
		  tic_exu_address1_b	[1:0]}),
	.sel0 	(fls1_dfd_lsu_inst_b		),
	.en 	(1'b1				),
	.dout	(lsu_br_va_1_w		[47:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__stack_48c__width_48 va_0_w1_lat   (
	.scan_in(va_0_w1_lat_scanin),
	.scan_out(va_0_w1_lat_scanout),
	.din 	(lsu_br_va_0_w		[47:0]	),
	.dout 	(va_0_w1		[47:0]	),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__stack_48c__width_48 va_1_w1_lat   (
	.scan_in(va_1_w1_lat_scanin),
	.scan_out(va_1_w1_lat_scanout),
	.din 	(lsu_br_va_1_w		[47:0]	),
	.dout 	(va_1_w1		[47:0]	),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 dsfar_0_lat     ( 
	.scan_in(dsfar_0_lat_wmr_scanin),
	.scan_out(dsfar_0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({{29 {1'b0}}		       ,	
		  tel0_syndrome		[15:0],	
		  tlu_tsa_index_0	[2:0]}),
	.din1	({{28 {1'b0}}		       ,	
		  ras_dsfar_0		[19:0]}),
	.din2	(va_0_w1		[47:0]	),
	.din3	(wr_data		[47:0]	),
	.din4	(dsfar_0		[47:0]	),
	.sel0	(ras_dsfar_sel_tsa	[0   ]	),
	.sel1	(ras_dsfar_sel_ras	[0   ]	),
	.sel2	(ras_dsfar_sel_lsu_va	[0   ]	),
	.sel3	(asi_wr_dsfar		[0   ]	),
	.dout	(dsfar_0		[47:0]	),
  .clk(clk),
  .en(en),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 dsfar_1_lat     ( 
	.scan_in(dsfar_1_lat_wmr_scanin),
	.scan_out(dsfar_1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({{29 {1'b0}}		       ,	
		  tel0_syndrome		[15:0],	
		  tlu_tsa_index_0	[2:0]}),
	.din1	({{28 {1'b0}}		       ,	
		  ras_dsfar_1		[19:0]}),
	.din2	(va_0_w1		[47:0]	),
	.din3	(wr_data		[47:0]	),
	.din4	(dsfar_1		[47:0]	),
	.sel0	(ras_dsfar_sel_tsa	[1   ]	),
	.sel1	(ras_dsfar_sel_ras	[1   ]	),
	.sel2	(ras_dsfar_sel_lsu_va	[1   ]	),
	.sel3	(asi_wr_dsfar		[1   ]	),
	.dout	(dsfar_1		[47:0]	),
  .clk(clk),
  .en(en),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 dsfar_2_lat     ( 
	.scan_in(dsfar_2_lat_wmr_scanin),
	.scan_out(dsfar_2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({{29 {1'b0}}		       ,	
		  tel0_syndrome		[15:0],	
		  tlu_tsa_index_0	[2:0]}),
	.din1	({{28 {1'b0}}		       ,	
		  ras_dsfar_2		[19:0]}),
	.din2	(va_0_w1		[47:0]	),
	.din3	(wr_data		[47:0]	),
	.din4	(dsfar_2		[47:0]	),
	.sel0	(ras_dsfar_sel_tsa	[2   ]	),
	.sel1	(ras_dsfar_sel_ras	[2   ]	),
	.sel2	(ras_dsfar_sel_lsu_va	[2   ]	),
	.sel3	(asi_wr_dsfar		[2   ]	),
	.dout	(dsfar_2		[47:0]	),
  .clk(clk),
  .en(en),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 dsfar_3_lat     ( 
	.scan_in(dsfar_3_lat_wmr_scanin),
	.scan_out(dsfar_3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({{29 {1'b0}}		       ,	
		  tel0_syndrome		[15:0],	
		  tlu_tsa_index_0	[2:0]}),
	.din1	({{28 {1'b0}}		       ,	
		  ras_dsfar_3 		[19:0]}),
	.din2	(va_0_w1		[47:0]	),
	.din3	(wr_data		[47:0]	),
	.din4	(dsfar_3		[47:0]	),
	.sel0	(ras_dsfar_sel_tsa	[3   ]	),
	.sel1	(ras_dsfar_sel_ras	[3   ]	),
	.sel2	(ras_dsfar_sel_lsu_va	[3   ]	),
	.sel3	(asi_wr_dsfar		[3   ]	),
	.dout	(dsfar_3		[47:0]	),
  .clk(clk),
  .en(en),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 dsfar_4_lat     ( 
	.scan_in(dsfar_4_lat_wmr_scanin),
	.scan_out(dsfar_4_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({{29 {1'b0}}		       ,	
		  tel1_syndrome		[15:0],	
		  tlu_tsa_index_1	[2:0]}),
	.din1	({{28 {1'b0}}		       ,	
		  ras_dsfar_4		[19:0]}),
	.din2	(va_1_w1		[47:0]	),
	.din3	(wr_data		[47:0]	),
	.din4	(dsfar_4		[47:0]	),
	.sel0	(ras_dsfar_sel_tsa	[4   ]	),
	.sel1	(ras_dsfar_sel_ras	[4   ]	),
	.sel2	(ras_dsfar_sel_lsu_va	[4   ]	),
	.sel3	(asi_wr_dsfar		[4   ]	),
	.dout	(dsfar_4		[47:0]	),
  .clk(clk),
  .en(en),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 dsfar_5_lat     ( 
	.scan_in(dsfar_5_lat_wmr_scanin),
	.scan_out(dsfar_5_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({{29 {1'b0}}		       ,	
		  tel1_syndrome		[15:0],	
		  tlu_tsa_index_1	[2:0]}),
	.din1	({{28 {1'b0}}		       ,	
		  ras_dsfar_5		[19:0]}),
	.din2	(va_1_w1		[47:0]	),
	.din3	(wr_data		[47:0]	),
	.din4	(dsfar_5		[47:0]	),
	.sel0	(ras_dsfar_sel_tsa	[5   ]	),
	.sel1	(ras_dsfar_sel_ras	[5   ]	),
	.sel2	(ras_dsfar_sel_lsu_va	[5   ]	),
	.sel3	(asi_wr_dsfar		[5   ]	),
	.dout	(dsfar_5		[47:0]	),
  .clk(clk),
  .en(en),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 dsfar_6_lat     ( 
	.scan_in(dsfar_6_lat_wmr_scanin),
	.scan_out(dsfar_6_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({{29 {1'b0}}		       ,	
		  tel1_syndrome		[15:0],	
		  tlu_tsa_index_1	[2:0]}),
	.din1	({{28 {1'b0}}		       ,	
		  ras_dsfar_6		[19:0]}),
	.din2	(va_1_w1		[47:0]	),
	.din3	(wr_data		[47:0]	),
	.din4	(dsfar_6		[47:0]	),
	.sel0	(ras_dsfar_sel_tsa	[6   ]	),
	.sel1	(ras_dsfar_sel_ras	[6   ]	),
	.sel2	(ras_dsfar_sel_lsu_va	[6   ]	),
	.sel3	(asi_wr_dsfar		[6   ]	),
	.dout	(dsfar_6		[47:0]	),
  .clk(clk),
  .en(en),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 dsfar_7_lat     ( 
	.scan_in(dsfar_7_lat_wmr_scanin),
	.scan_out(dsfar_7_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({{29 {1'b0}}		       ,	
		  tel1_syndrome		[15:0],	
		  tlu_tsa_index_1	[2:0]}),
	.din1	({{28 {1'b0}}		       ,	
		  ras_dsfar_7		[19:0]}),
	.din2	(va_1_w1		[47:0]	),
	.din3	(wr_data		[47:0]	),
	.din4	(dsfar_7		[47:0]	),
	.sel0	(ras_dsfar_sel_tsa	[7   ]	),
	.sel1	(ras_dsfar_sel_ras	[7   ]	),
	.sel2	(ras_dsfar_sel_lsu_va	[7   ]	),
	.sel3	(asi_wr_dsfar		[7   ]	),
	.dout	(dsfar_7		[47:0]	),
  .clk(clk),
  .en(en),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


//////////////////////////////////////////////////////////////////////
//
// DESRs
//
tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 desr_0_lat    ( 
	.scan_in(desr_0_lat_wmr_scanin),
	.scan_out(desr_0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({1'b1			       ,	// F
		  ras_desr_me_0		       ,	// ME
		  ras_desr_et_0		[61:56],	// S, ET
		  ras_desr_ea_0		[10:0]}),	// EA
	.din1	({1'b1			       ,	// F
		  1'b1			       ,	// ME
		  desr_0   		[61:56],	// S, ET
		  desr_0   		[10:0]}),	// EA
	.din2	({19 {1'b0}		       }),	
	.din3	({desr_0		[63   ],	// F
		  desr_0		[62   ],	// ME
		  desr_0  		[61:56],	// S, ET
		  desr_0  		[10:0]}),	// EA
	.sel0	(ras_write_desr_1st	[0   ]	),
	.sel1	(ras_write_desr_2nd	[0   ]	),
	.sel2	(ras_rd_desr		[0   ]	),
	.en 	(ras_desr_en		[0   ]	),
	.dout	({desr_0		[63   ],	// F
		  desr_0		[62   ],	// ME
		  desr_0  		[61:56],	// S, ET
		  desr_0  		[10:0]}),	// EA
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 desr_1_lat    ( 
	.scan_in(desr_1_lat_wmr_scanin),
	.scan_out(desr_1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({1'b1			       ,	// F
		  ras_desr_me_1		       ,	// ME
		  ras_desr_et_1		[61:56],	// S, ET
		  ras_desr_ea_1		[10:0]}),	// EA
	.din1	({1'b1			       ,	// F
		  1'b1			       ,	// ME
		  desr_1   		[61:56],	// S, ET
		  desr_1   		[10:0]}),	// EA
	.din2	({19 {1'b0}		       }),	
	.din3	({desr_1		[63   ],	// F
		  desr_1		[62   ],	// ME
		  desr_1  		[61:56],	// S, ET
		  desr_1  		[10:0]}),	// EA
	.sel0	(ras_write_desr_1st	[1   ]	),
	.sel1	(ras_write_desr_2nd	[1   ]	),
	.sel2	(ras_rd_desr		[1   ]	),
	.en 	(ras_desr_en		[1   ]	),
	.dout	({desr_1		[63   ],	// F
		  desr_1		[62   ],	// ME
		  desr_1  		[61:56],	// S, ET
		  desr_1  		[10:0]}),	// EA
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 desr_2_lat    ( 
	.scan_in(desr_2_lat_wmr_scanin),
	.scan_out(desr_2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({1'b1			       ,	// F
		  ras_desr_me_2		       ,	// ME
		  ras_desr_et_2		[61:56],	// S, ET
		  ras_desr_ea_2		[10:0]}),	// EA
	.din1	({1'b1			       ,	// F
		  1'b1			       ,	// ME
		  desr_2   		[61:56],	// S, ET
		  desr_2   		[10:0]}),	// EA
	.din2	({19 {1'b0}		       }),	
	.din3	({desr_2		[63   ],	// F
		  desr_2		[62   ],	// ME
		  desr_2  		[61:56],	// S, ET
		  desr_2  		[10:0]}),	// EA
	.sel0	(ras_write_desr_1st	[2   ]	),
	.sel1	(ras_write_desr_2nd	[2   ]	),
	.sel2	(ras_rd_desr		[2   ]	),
	.en 	(ras_desr_en		[2   ]	),
	.dout	({desr_2		[63   ],	// F
		  desr_2		[62   ],	// ME
		  desr_2  		[61:56],	// S, ET
		  desr_2  		[10:0]}),	// EA
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 desr_3_lat    ( 
	.scan_in(desr_3_lat_wmr_scanin),
	.scan_out(desr_3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({1'b1			       ,	// F
		  ras_desr_me_3 	       ,	// ME
		  ras_desr_et_3 	[61:56],	// S, ET
		  ras_desr_ea_3		[10:0]}),	// EA
	.din1	({1'b1			       ,	// F
		  1'b1			       ,	// ME
		  desr_3   		[61:56],	// S, ET
		  desr_3   		[10:0]}),	// EA
	.din2	({19 {1'b0}		       }),	
	.din3	({desr_3		[63   ],	// F
		  desr_3		[62   ],	// ME
		  desr_3  		[61:56],	// S, ET
		  desr_3  		[10:0]}),	// EA
	.sel0	(ras_write_desr_1st	[3   ]	),
	.sel1	(ras_write_desr_2nd	[3   ]	),
	.sel2	(ras_rd_desr		[3   ]	),
	.en 	(ras_desr_en		[3   ]	),
	.dout	({desr_3		[63   ],	// F
		  desr_3		[62   ],	// ME
		  desr_3  		[61:56],	// S, ET
		  desr_3  		[10:0]}),	// EA
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 desr_4_lat    ( 
	.scan_in(desr_4_lat_wmr_scanin),
	.scan_out(desr_4_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({1'b1			       ,	// F
		  ras_desr_me_4		       ,	// ME
		  ras_desr_et_4		[61:56],	// S, ET
		  ras_desr_ea_4		[10:0]}),	// EA
	.din1	({1'b1			       ,	// F
		  1'b1			       ,	// ME
		  desr_4   		[61:56],	// S, ET
		  desr_4   		[10:0]}),	// EA
	.din2	({19 {1'b0}		       }),	
	.din3	({desr_4		[63   ],	// F
		  desr_4		[62   ],	// ME
		  desr_4  		[61:56],	// S, ET
		  desr_4  		[10:0]}),	// EA
	.sel0	(ras_write_desr_1st	[4   ]	),
	.sel1	(ras_write_desr_2nd	[4   ]	),
	.sel2	(ras_rd_desr		[4   ]	),
	.en 	(ras_desr_en		[4   ]	),
	.dout	({desr_4		[63   ],	// F
		  desr_4		[62   ],	// ME
		  desr_4  		[61:56],	// S, ET
		  desr_4  		[10:0]}),	// EA
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 desr_5_lat    ( 
	.scan_in(desr_5_lat_wmr_scanin),
	.scan_out(desr_5_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({1'b1			       ,	// F
		  ras_desr_me_5		       ,	// ME
		  ras_desr_et_5		[61:56],	// S, ET
		  ras_desr_ea_5		[10:0]}),	// EA
	.din1	({1'b1			       ,	// F
		  1'b1			       ,	// ME
		  desr_5   		[61:56],	// S, ET
		  desr_5   		[10:0]}),	// EA
	.din2	({19 {1'b0}		       }),	
	.din3	({desr_5		[63   ],	// F
		  desr_5		[62   ],	// ME
		  desr_5  		[61:56],	// S, ET
		  desr_5  		[10:0]}),	// EA
	.sel0	(ras_write_desr_1st	[5   ]	),
	.sel1	(ras_write_desr_2nd	[5   ]	),
	.sel2	(ras_rd_desr		[5   ]	),
	.en 	(ras_desr_en		[5   ]	),
	.dout	({desr_5		[63   ],	// F
		  desr_5		[62   ],	// ME
		  desr_5  		[61:56],	// S, ET
		  desr_5  		[10:0]}),	// EA
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 desr_6_lat    ( 
	.scan_in(desr_6_lat_wmr_scanin),
	.scan_out(desr_6_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({1'b1			       ,	// F
		  ras_desr_me_6		       ,	// ME
		  ras_desr_et_6		[61:56],	// S, ET
		  ras_desr_ea_6		[10:0]}),	// EA
	.din1	({1'b1			       ,	// F
		  1'b1			       ,	// ME
		  desr_6   		[61:56],	// S, ET
		  desr_6   		[10:0]}),	// EA
	.din2	({19 {1'b0}		       }),	
	.din3	({desr_6		[63   ],	// F
		  desr_6		[62   ],	// ME
		  desr_6  		[61:56],	// S, ET
		  desr_6  		[10:0]}),	// EA
	.sel0	(ras_write_desr_1st	[6   ]	),
	.sel1	(ras_write_desr_2nd	[6   ]	),
	.sel2	(ras_rd_desr		[6   ]	),
	.en 	(ras_desr_en		[6   ]	),
	.dout	({desr_6		[63   ],	// F
		  desr_6		[62   ],	// ME
		  desr_6  		[61:56],	// S, ET
		  desr_6  		[10:0]}),	// EA
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 desr_7_lat    ( 
	.scan_in(desr_7_lat_wmr_scanin),
	.scan_out(desr_7_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({1'b1			       ,	// F
		  ras_desr_me_7		       ,	// ME
		  ras_desr_et_7		[61:56],	// S, ET
		  ras_desr_ea_7		[10:0]}),	// EA
	.din1	({1'b1			       ,	// F
		  1'b1			       ,	// ME
		  desr_7   		[61:56],	// S, ET
		  desr_7   		[10:0]}),	// EA
	.din2	({19 {1'b0}		       }),	
	.din3	({desr_7		[63   ],	// F
		  desr_7		[62   ],	// ME
		  desr_7  		[61:56],	// S, ET
		  desr_7  		[10:0]}),	// EA
	.sel0	(ras_write_desr_1st	[7   ]	),
	.sel1	(ras_write_desr_2nd	[7   ]	),
	.sel2	(ras_rd_desr		[7   ]	),
	.en 	(ras_desr_en		[7   ]	),
	.dout	({desr_7		[63   ],	// F
		  desr_7		[62   ],	// ME
		  desr_7  		[61:56],	// S, ET
		  desr_7  		[10:0]}),	// EA
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

assign dfd_desr_f[7:0] =
       {desr_7[63], desr_6[63], desr_5[63], desr_4[63],
        desr_3[63], desr_2[63], desr_1[63], desr_0[63]};

assign dfd_desr_s[7:0] =
       {desr_7[61], desr_6[61], desr_5[61], desr_4[61],
        desr_3[61], desr_2[61], desr_1[61], desr_0[61]};

tlu_dfd_dp_buff_macro__rep_1__stack_none__width_8 desr_f_buf    (
	.din	({desr_7[63], desr_6[63], desr_5[63], desr_4[63],
	          desr_3[63], desr_2[63], desr_1[63], desr_0[63]}),
	.dout	(dfd_fls_desr_f		[7:0]	)
);

tlu_dfd_dp_buff_macro__rep_1__stack_none__width_8 desr_s_buf    (
	.din	({desr_7[61], desr_6[61], desr_5[61], desr_4[61],
	          desr_3[61], desr_2[61], desr_1[61], desr_0[61]}),
	.dout	(dfd_fls_desr_s		[7:0]	)
);


//////////////////////////////////////////////////////////////////////
//
// FESRs
//

tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 fesr_0_lat    ( 
	.scan_in(fesr_0_lat_wmr_scanin),
	.scan_out(fesr_0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ras_fesr_et_0		[61:60],	// ET
		  ras_fesr_ea_0		[59:55]}),	// PL, STBI
	.din1	({fesr_0 		[61:60],	// ET
		  ras_fesr_priv		[59:58],	// PL
		  fesr_0 		[57:55]}),	// STBI
	.din2	({7 {1'b0}}			),
	.sel0	(ras_write_fesr		[0   ]	),
	.sel1	(ras_update_priv	[0   ]	),
	.sel2	(ras_rd_fesr		[0   ]	),
	.en	(ras_fesr_en		[0   ]	),
	.dout	({fesr_0		[61:60],	// ET
		  fesr_0		[59:58],	// PL
		  fesr_0		[57:55]}),	// STBI
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 fesr_1_lat    ( 
	.scan_in(fesr_1_lat_wmr_scanin),
	.scan_out(fesr_1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ras_fesr_et_1		[61:60],	// ET
		  ras_fesr_ea_1		[59:55]}),	// PL, STBI
	.din1	({fesr_1 		[61:60],	// ET
		  ras_fesr_priv		[59:58],	// PL
		  fesr_1 		[57:55]}),	// STBI
	.din2	({7 {1'b0}}			),
	.sel0	(ras_write_fesr		[1   ]	),
	.sel1	(ras_update_priv	[1   ]	),
	.sel2	(ras_rd_fesr		[1   ]	),
	.en	(ras_fesr_en		[1   ]	),
	.dout	({fesr_1		[61:60],	// ET
		  fesr_1		[59:58],	// PL
		  fesr_1		[57:55]}),	// STBI
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 fesr_2_lat    ( 
	.scan_in(fesr_2_lat_wmr_scanin),
	.scan_out(fesr_2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ras_fesr_et_2		[61:60],	// ET
		  ras_fesr_ea_2		[59:55]}),	// PL, STBI
	.din1	({fesr_2 		[61:60],	// ET
		  ras_fesr_priv		[59:58],	// PL
		  fesr_2 		[57:55]}),	// STBI
	.din2	({7 {1'b0}}			),
	.sel0	(ras_write_fesr		[2   ]	),
	.sel1	(ras_update_priv	[2   ]	),
	.sel2	(ras_rd_fesr		[2   ]	),
	.en	(ras_fesr_en		[2   ]	),
	.dout	({fesr_2		[61:60],	// ET
		  fesr_2		[59:58],	// PL
		  fesr_2		[57:55]}),	// STBI
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 fesr_3_lat    ( 
	.scan_in(fesr_3_lat_wmr_scanin),
	.scan_out(fesr_3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ras_fesr_et_3		[61:60],	// ET
		  ras_fesr_ea_3		[59:55]}),	// PL, STBI
	.din1	({fesr_3 		[61:60],	// ET
		  ras_fesr_priv		[59:58],	// PL
		  fesr_3 		[57:55]}),	// STBI
	.din2	({7 {1'b0}}			),
	.sel0	(ras_write_fesr		[3   ]	),
	.sel1	(ras_update_priv	[3   ]	),
	.sel2	(ras_rd_fesr		[3   ]	),
	.en	(ras_fesr_en		[3   ]	),
	.dout	({fesr_3		[61:60],	// ET
		  fesr_3		[59:58],	// PL
		  fesr_3		[57:55]}),	// STBI
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 fesr_4_lat    ( 
	.scan_in(fesr_4_lat_wmr_scanin),
	.scan_out(fesr_4_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ras_fesr_et_4		[61:60],	// ET
		  ras_fesr_ea_4		[59:55]}),	// PL, STBI
	.din1	({fesr_4 		[61:60],	// ET
		  ras_fesr_priv		[59:58],	// PL
		  fesr_4 		[57:55]}),	// STBI
	.din2	({7 {1'b0}}			),
	.sel0	(ras_write_fesr		[4   ]	),
	.sel1	(ras_update_priv	[4   ]	),
	.sel2	(ras_rd_fesr		[4   ]	),
	.en	(ras_fesr_en		[4   ]	),
	.dout	({fesr_4		[61:60],	// ET
		  fesr_4		[59:58],	// PL
		  fesr_4		[57:55]}),	// STBI
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 fesr_5_lat    ( 
	.scan_in(fesr_5_lat_wmr_scanin),
	.scan_out(fesr_5_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ras_fesr_et_5		[61:60],	// ET
		  ras_fesr_ea_5		[59:55]}),	// PL, STBI
	.din1	({fesr_5 		[61:60],	// ET
		  ras_fesr_priv		[59:58],	// PL
		  fesr_5 		[57:55]}),	// STBI
	.din2	({7 {1'b0}}			),
	.sel0	(ras_write_fesr		[5   ]	),
	.sel1	(ras_update_priv	[5   ]	),
	.sel2	(ras_rd_fesr		[5   ]	),
	.en	(ras_fesr_en		[5   ]	),
	.dout	({fesr_5		[61:60],	// ET
		  fesr_5		[59:58],	// PL
		  fesr_5		[57:55]}),	// STBI
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 fesr_6_lat    ( 
	.scan_in(fesr_6_lat_wmr_scanin),
	.scan_out(fesr_6_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ras_fesr_et_6		[61:60],	// ET
		  ras_fesr_ea_6		[59:55]}),	// PL, STBI
	.din1	({fesr_6 		[61:60],	// ET
		  ras_fesr_priv		[59:58],	// PL
		  fesr_6 		[57:55]}),	// STBI
	.din2	({7 {1'b0}}			),
	.sel0	(ras_write_fesr		[6   ]	),
	.sel1	(ras_update_priv	[6   ]	),
	.sel2	(ras_rd_fesr		[6   ]	),
	.en	(ras_fesr_en		[6   ]	),
	.dout	({fesr_6		[61:60],	// ET
		  fesr_6		[59:58],	// PL
		  fesr_6		[57:55]}),	// STBI
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 fesr_7_lat    ( 
	.scan_in(fesr_7_lat_wmr_scanin),
	.scan_out(fesr_7_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.se	(tcu_scan_en_wmr		),
	.din0	({ras_fesr_et_7		[61:60],	// ET
		  ras_fesr_ea_7		[59:55]}),	// PL, STBI
	.din1	({fesr_7 		[61:60],	// ET
		  ras_fesr_priv		[59:58],	// PL
		  fesr_7 		[57:55]}),	// STBI
	.din2	({7 {1'b0}}			),
	.sel0	(ras_write_fesr		[7   ]	),
	.sel1	(ras_update_priv	[7   ]	),
	.sel2	(ras_rd_fesr		[7   ]	),
	.en	(ras_fesr_en		[7   ]	),
	.dout	({fesr_7		[61:60],	// ET
		  fesr_7		[59:58],	// PL
		  fesr_7		[57:55]}),	// STBI
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

tlu_dfd_dp_or_macro__ports_2__width_8 fesr_f_or   (
	.din0	({fesr_7		[61   ], 
		  fesr_6		[61   ],
		  fesr_5		[61   ], 
		  fesr_4		[61   ],
		  fesr_3		[61   ], 
		  fesr_2		[61   ], 
		  fesr_1		[61   ], 
		  fesr_0		[61   ]}),
	.din1	({fesr_7		[60   ], 
		  fesr_6		[60   ],
		  fesr_5		[60   ], 
		  fesr_4		[60   ],
		  fesr_3		[60   ], 
		  fesr_2		[60   ], 
		  fesr_1		[60   ], 
		  fesr_0		[60   ]}),
	.dout	(dfd_fesr_f		[7:0]	)
);

tlu_dfd_dp_buff_macro__dbuff_16x__width_16 fesr_priv_buf   (
	.din 	({fesr_7		[59:58],
		  fesr_6		[59:58],
		  fesr_5		[59:58],
		  fesr_4		[59:58],
		  fesr_3		[59:58],
		  fesr_2		[59:58],
		  fesr_1		[59:58],
		  fesr_0		[59:58]}),
	.dout	({dfd_fesr_priv_7	[1:0],
		  dfd_fesr_priv_6	[1:0],
		  dfd_fesr_priv_5	[1:0],
		  dfd_fesr_priv_4	[1:0],
		  dfd_fesr_priv_3	[1:0],
		  dfd_fesr_priv_2	[1:0],
		  dfd_fesr_priv_1	[1:0],
		  dfd_fesr_priv_0	[1:0]})
);


//////////////////////////////////////////////////////////////////////
//
// Mux read data
//

tlu_dfd_dp_mux_macro__mux_aonpe__ports_8__stack_48c__width_48 dsfar_mux     (
	.din0	(dsfar_0		[47:0]	),
	.din1	(dsfar_1		[47:0]	),
	.din2	(dsfar_2		[47:0]	),
	.din3	(dsfar_3		[47:0]	),
	.din4	(dsfar_4		[47:0]	),
	.din5	(dsfar_5		[47:0]	),
	.din6	(dsfar_6		[47:0]	),
	.din7	(dsfar_7		[47:0]	),
	.sel0	(ras_rd_dsfar		[0   ]	),
	.sel1	(ras_rd_dsfar		[1   ]	),
	.sel2	(ras_rd_dsfar		[2   ]	),
	.sel3	(ras_rd_dsfar		[3   ]	),
	.sel4	(ras_rd_dsfar		[4   ]	),
	.sel5	(ras_rd_dsfar		[5   ]	),
	.sel6	(ras_rd_dsfar		[6   ]	),
	.sel7	(ras_rd_dsfar		[7   ]	),
	.dout	(dsfar			[47:0]	)
);

tlu_dfd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__width_19 desr_mux     (
	.din0	({desr_0		[63   ],	// F
		  desr_0		[62   ],	// ME
		  desr_0  		[61:56],	// S, ET
		  desr_0  		[10:0]}),	// EA
	.din1	({desr_1		[63   ],	// F
		  desr_1		[62   ],	// ME
		  desr_1  		[61:56],	// S, ET
		  desr_1  		[10:0]}),	// EA
	.din2	({desr_2		[63   ],	// F
		  desr_2		[62   ],	// ME
		  desr_2  		[61:56],	// S, ET
		  desr_2  		[10:0]}),	// EA
	.din3	({desr_3		[63   ],	// F
		  desr_3		[62   ],	// ME
		  desr_3  		[61:56],	// S, ET
		  desr_3  		[10:0]}),	// EA
	.din4	({desr_4		[63   ],	// F
		  desr_4		[62   ],	// ME
		  desr_4  		[61:56],	// S, ET
		  desr_4  		[10:0]}),	// EA
	.din5	({desr_5		[63   ],	// F
		  desr_5		[62   ],	// ME
		  desr_5  		[61:56],	// S, ET
		  desr_5  		[10:0]}),	// EA
	.din6	({desr_6		[63   ],	// F
		  desr_6		[62   ],	// ME
		  desr_6  		[61:56],	// S, ET
		  desr_6  		[10:0]}),	// EA
	.din7	({desr_7		[63   ],	// F
		  desr_7		[62   ],	// ME
		  desr_7  		[61:56],	// S, ET
		  desr_7  		[10:0]}),	// EA
	.sel0	(ras_rd_desr		[0   ]	),
	.sel1	(ras_rd_desr		[1   ]	),
	.sel2	(ras_rd_desr		[2   ]	),
	.sel3	(ras_rd_desr		[3   ]	),
	.sel4	(ras_rd_desr		[4   ]	),
	.sel5	(ras_rd_desr		[5   ]	),
	.sel6	(ras_rd_desr		[6   ]	),
	.sel7	(ras_rd_desr		[7   ]	),
	.dout	(desr			[18:0]	)
);

// Next stage of muxing in tlu_asi_ctl
assign dfd_asi_desr[18:0] =
       desr[18:0];

tlu_dfd_dp_mux_macro__mux_aonpe__ports_8__width_7 fesr_mux    (
	.din0	({fesr_0		[61:60],	// ET
		  fesr_0		[59:58],	// PL
		  fesr_0		[57:55]}),	// STBI
	.din1	({fesr_1		[61:60],	// ET
		  fesr_1		[59:58],	// PL
		  fesr_1		[57:55]}),	// STBI
	.din2	({fesr_2		[61:60],	// ET
		  fesr_2		[59:58],	// PL
		  fesr_2		[57:55]}),	// STBI
	.din3	({fesr_3		[61:60],	// ET
		  fesr_3		[59:58],	// PL
		  fesr_3		[57:55]}),	// STBI
	.din4	({fesr_4		[61:60],	// ET
		  fesr_4		[59:58],	// PL
		  fesr_4		[57:55]}),	// STBI
	.din5	({fesr_5		[61:60],	// ET
		  fesr_5		[59:58],	// PL
		  fesr_5		[57:55]}),	// STBI
	.din6	({fesr_6		[61:60],	// ET
		  fesr_6		[59:58],	// PL
		  fesr_6		[57:55]}),	// STBI
	.din7	({fesr_7		[61:60],	// ET
		  fesr_7		[59:58],	// PL
		  fesr_7		[57:55]}),	// STBI
	.sel0	(ras_rd_fesr		[0   ]	),
	.sel1	(ras_rd_fesr		[1   ]	),
	.sel2	(ras_rd_fesr		[2   ]	),
	.sel3	(ras_rd_fesr		[3   ]	),
	.sel4	(ras_rd_fesr		[4   ]	),
	.sel5	(ras_rd_fesr		[5   ]	),
	.sel6	(ras_rd_fesr		[6   ]	),
	.sel7	(ras_rd_fesr		[7   ]	),
	.dout	(fesr			[6:0]	)
);


// Map of how the various registers get merged into the ASI bus in DFD
// dfd_asi_data	47:41	40:37	36:19	18:0
// dsfar	47:41	40:37	36:19	18:0
// fesr		6:0
// desr					18:0
// dsfsr/{0,isfsr}	40:37

tlu_dfd_dp_or_macro__ports_2__stack_48c__width_48 asi_data_or    (
	.din0	(dsfar		[47:0]	),
	.din1	({fesr		[6:0],
		  ras_asi_data	[3:0],
		  {18 {1'b0}}	       ,
		  {19 {1'b0}}	       }),
	.dout	(dfd_asi_data	[47:0]	)
);


// fixscan start:
assign lsu_br_va_0_lat_scanin    = scan_in                  ;
assign lsu_br_va_1_lat_scanin    = lsu_br_va_0_lat_scanout  ;
assign va_0_w1_lat_scanin        = lsu_br_va_1_lat_scanout  ;
assign va_1_w1_lat_scanin        = va_0_w1_lat_scanout      ;
assign scan_out                  = va_1_w1_lat_scanout      ;

assign dsfar_0_lat_wmr_scanin    = wmr_scan_in              ;
assign dsfar_1_lat_wmr_scanin    = dsfar_0_lat_wmr_scanout  ;
assign dsfar_2_lat_wmr_scanin    = dsfar_1_lat_wmr_scanout  ;
assign dsfar_3_lat_wmr_scanin    = dsfar_2_lat_wmr_scanout  ;
assign dsfar_4_lat_wmr_scanin    = dsfar_3_lat_wmr_scanout  ;
assign dsfar_5_lat_wmr_scanin    = dsfar_4_lat_wmr_scanout  ;
assign dsfar_6_lat_wmr_scanin    = dsfar_5_lat_wmr_scanout  ;
assign dsfar_7_lat_wmr_scanin    = dsfar_6_lat_wmr_scanout  ;
assign desr_0_lat_wmr_scanin     = dsfar_7_lat_wmr_scanout  ;
assign desr_1_lat_wmr_scanin     = desr_0_lat_wmr_scanout   ;
assign desr_2_lat_wmr_scanin     = desr_1_lat_wmr_scanout   ;
assign desr_3_lat_wmr_scanin     = desr_2_lat_wmr_scanout   ;
assign desr_4_lat_wmr_scanin     = desr_3_lat_wmr_scanout   ;
assign desr_5_lat_wmr_scanin     = desr_4_lat_wmr_scanout   ;
assign desr_6_lat_wmr_scanin     = desr_5_lat_wmr_scanout   ;
assign desr_7_lat_wmr_scanin     = desr_6_lat_wmr_scanout   ;
assign fesr_0_lat_wmr_scanin     = desr_7_lat_wmr_scanout   ;
assign fesr_1_lat_wmr_scanin     = fesr_0_lat_wmr_scanout   ;
assign fesr_2_lat_wmr_scanin     = fesr_1_lat_wmr_scanout   ;
assign fesr_3_lat_wmr_scanin     = fesr_2_lat_wmr_scanout   ;
assign fesr_4_lat_wmr_scanin     = fesr_3_lat_wmr_scanout   ;
assign fesr_5_lat_wmr_scanin     = fesr_4_lat_wmr_scanout   ;
assign fesr_6_lat_wmr_scanin     = fesr_5_lat_wmr_scanout   ;
assign fesr_7_lat_wmr_scanin     = fesr_6_lat_wmr_scanout   ;
assign wmr_scan_out              = fesr_7_lat_wmr_scanout   ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module tlu_dfd_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_dfd_dp_msff_macro__mux_aope__ports_2__stack_48c__width_48 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [47:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din0;
  input [47:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(48)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
.dout(muxout[47:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_dfd_dp_msff_macro__stack_48c__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_dfd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_48 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [47:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din0;
  input [47:0] din1;
  input [47:0] din2;
  input [47:0] din3;
  input [47:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(48)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
.dout(muxout[47:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_dfd_dp_msff_macro__mux_aope__ports_4__width_19 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire [18:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [17:0] so;

  input [18:0] din0;
  input [18:0] din1;
  input [18:0] din2;
  input [18:0] din3;
  input sel0;
  input sel1;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [18:0] dout;


  output scan_out;


cl_dp1_penc4_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(19)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[18:0]),
  .in1(din1[18:0]),
  .in2(din2[18:0]),
  .in3(din3[18:0]),
.dout(muxout[18:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(19)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[18:0]),
.si({scan_in,so[17:0]}),
.so({so[17:0],scan_out}),
.q(dout[18:0])
);


endmodule


//
//   buff macro
//
//


module tlu_dfd_dp_buff_macro__rep_1__stack_none__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_dfd_dp_msff_macro__mux_aonpe__ports_3__width_7 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire [6:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [5:0] so;

  input [6:0] din0;
  input sel0;
  input [6:0] din1;
  input sel1;
  input [6:0] din2;
  input sel2;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [6:0] dout;


  output scan_out;


cl_dp1_muxbuff3_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(7)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
  .in2(din2[6:0]),
.dout(muxout[6:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_dfd_dp_or_macro__ports_2__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


or2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//
//   buff macro
//
//


module tlu_dfd_dp_buff_macro__dbuff_16x__width_16 (
  din, 
  dout);
  input [15:0] din;
  output [15:0] dout;


buff #(16)  d0_0 (
.in(din[15:0]),
.out(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_dfd_dp_mux_macro__mux_aonpe__ports_8__stack_48c__width_48 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [47:0] din0;
  input sel0;
  input [47:0] din1;
  input sel1;
  input [47:0] din2;
  input sel2;
  input [47:0] din3;
  input sel3;
  input [47:0] din4;
  input sel4;
  input [47:0] din5;
  input sel5;
  input [47:0] din6;
  input sel6;
  input [47:0] din7;
  input sel7;
  output [47:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(48)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
  .in5(din5[47:0]),
  .in6(din6[47:0]),
  .in7(din7[47:0]),
.dout(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_dfd_dp_mux_macro__dmux_8x__mux_aonpe__ports_8__width_19 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [18:0] din0;
  input sel0;
  input [18:0] din1;
  input sel1;
  input [18:0] din2;
  input sel2;
  input [18:0] din3;
  input sel3;
  input [18:0] din4;
  input sel4;
  input [18:0] din5;
  input sel5;
  input [18:0] din6;
  input sel6;
  input [18:0] din7;
  input sel7;
  output [18:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(19)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[18:0]),
  .in1(din1[18:0]),
  .in2(din2[18:0]),
  .in3(din3[18:0]),
  .in4(din4[18:0]),
  .in5(din5[18:0]),
  .in6(din6[18:0]),
  .in7(din7[18:0]),
.dout(dout[18:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_dfd_dp_mux_macro__mux_aonpe__ports_8__width_7 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [6:0] din0;
  input sel0;
  input [6:0] din1;
  input sel1;
  input [6:0] din2;
  input sel2;
  input [6:0] din3;
  input sel3;
  input [6:0] din4;
  input sel4;
  input [6:0] din5;
  input sel5;
  input [6:0] din6;
  input sel6;
  input [6:0] din7;
  input sel7;
  output [6:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(7)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
  .in2(din2[6:0]),
  .in3(din3[6:0]),
  .in4(din4[6:0]),
  .in5(din5[6:0]),
  .in6(din6[6:0]),
  .in7(din7[6:0]),
.dout(dout[6:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_dfd_dp_or_macro__ports_2__stack_48c__width_48 (
  din0, 
  din1, 
  dout);
  input [47:0] din0;
  input [47:0] din1;
  output [47:0] dout;


or2 #(48)  d0_0 (
.in0(din0[47:0]),
.in1(din1[47:0]),
.out(dout[47:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_ecd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_ecd_dp (
  data_in, 
  ecc_in, 
  cerer_ce, 
  cerer_ue, 
  syndrome, 
  cecc_err, 
  uecc_err, 
  uecc_err_);
wire [67:0] d;
wire [7:0] e;
wire [37:0] check0_bus;
wire check0_4;
wire check0_3;
wire check0_2;
wire check0_1;
wire check0_0;
wire c0;
wire [37:0] check1_bus;
wire check1_4;
wire check1_3;
wire check1_2;
wire check1_1;
wire check1_0;
wire c1;
wire [35:0] check2_bus;
wire check2_4;
wire check2_3;
wire check2_2;
wire check2_1;
wire check2_0;
wire c2;
wire [35:0] check3_bus;
wire check3_4;
wire check3_3;
wire check3_2;
wire check3_1;
wire check3_0;
wire c3;
wire [31:0] check4_bus;
wire c4;
wire [31:0] check5_bus;
wire c5;
wire [11:0] check6_bus;
wire c6;
wire [74:0] check7_bus;
wire check7_4;
wire check7_3;
wire check7_2;
wire check7_1;
wire check7_0;
wire c7;
wire [7:7] e_;
wire c7_;
wire parity_incorrect;
wire parity_correct;
wire ecc_err_0;
wire ecc_err_1;
wire ecc_err_2;
wire ecc_err;


input	[67:0]	data_in;	// Used for generation and checking
input	[7:0]	ecc_in;		// Used for checking only
input		cerer_ce;
input		cerer_ue;

output	[7:0]	syndrome;	// Used for generation and checking
output		cecc_err;	// Used for checking only; unused for gen
output		uecc_err;	// Used for checking only; unused for gen
output		uecc_err_;	// Used for checking only; unused for gen


//////////////////////////////////////////////////////////////////////////////

// Position	Binary	
//	 1	0000001	C0
//	 2	0000010	C1
//	 3	0000011	D0
//
//	 4	0000100	C2
//	 5	0000101	D1
//	 6	0000110	D2
//	 7	0000111	D3
//			
//	 8 	0001000	C3
//	 9	0001001	D4
//	10	0001010	D5
//	11	0001011 D6
//	12	0001100	D7
//	...		...
//	15	0001111	D10
//			
//	16	0010000	C4
//	17	0010001	D11
//	...		...
//	20	0010100 D14
//	...		...
//	24	0011000	D18
//	...		...
//	28	0011100	D22
//	...		...
//	31	0011111	D25
//			
//	32	0100000	C5
//	33	0100001	D26
//	...		...
//	36	0100100	D29
//	...		...
//	40	0101000	D33
//	...		...
//	44	0101100	D37
//	...		...
//	48	0110000	D41
//	...		...
//	52	0110100	D45
//	...		...
//	56	0111000	D49
//	...		...
//	60	0111100	D53
//	...		...
//	63	0111111	D56
//			
//	64	1000000	C6
//	65	1000001	D57
//	...		...
//	68	1000100	D60
//	...		...
//	72	1001000	D64
//	73	1001001	D65
//	74	1001010	D66
//	75	1001011	D67
//			
//	76	1001100	C7

assign d[67:0] = 
       data_in[67:0];
assign e[7:0] =
       ecc_in[7:0];


// All odd positions (LSB of position set)
assign check0_bus[37:0] = 
	{d[67], d[65], d[63], d[61], d[59], d[57], 
	 d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42], 
	 d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26], 
	 d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], 
	 d[10], d[8], d[6], d[4], 
	 d[3], d[1],
	 d[0], 
	 e[0]};

tlu_ecd_dp_prty_macro__width_8 check0_4_pty  (
	.din	(check0_bus	[37:30]	),
	.dout	(check0_4		)
);

tlu_ecd_dp_prty_macro__width_8 check0_3_pty  (
	.din	(check0_bus	[29:22]	),
	.dout	(check0_3		)
);

tlu_ecd_dp_prty_macro__width_8 check0_2_pty  (
	.din	(check0_bus	[21:14]	),
	.dout	(check0_2		)
);

tlu_ecd_dp_prty_macro__width_8 check0_1_pty  (
	.din	(check0_bus	[13:6]	),
	.dout	(check0_1		)
);

tlu_ecd_dp_prty_macro__width_8 check0_0_pty  (
	.din	({check0_bus	[5:0],
		  {2 {1'b0}}	       }),
	.dout	(check0_0		)
);

tlu_ecd_dp_prty_macro__width_8 check0_pty  (
	.din	({check0_4	       ,
		  check0_3	       ,
		  check0_2	       ,
		  check0_1	       ,
		  check0_0	       ,
		  {3 {1'b0}}	       }),
	.dout	(c0			)
);


// All positions with secondmost LSB set
assign check1_bus[37:0] =
       {d[67:66], d[63:62], d[59:58], 
        d[56:55], d[52:51], d[48:47], d[44:43],
        d[40:39], d[36:35], d[32:31], d[28:27],
        d[25:24], d[21:20], d[17:16], d[13:12],
        d[10:9], d[6:5], 
        d[3:2],
        d[0],
        e[1]};

tlu_ecd_dp_prty_macro__width_8 check1_4_pty  (
	.din	(check1_bus	[37:30]	),
	.dout	(check1_4		)
);

tlu_ecd_dp_prty_macro__width_8 check1_3_pty  (
	.din	(check1_bus	[29:22]	),
	.dout	(check1_3		)
);

tlu_ecd_dp_prty_macro__width_8 check1_2_pty  (
	.din	(check1_bus	[21:14]	),
	.dout	(check1_2		)
);

tlu_ecd_dp_prty_macro__width_8 check1_1_pty  (
	.din	(check1_bus	[13:6]	),
	.dout	(check1_1		)
);

tlu_ecd_dp_prty_macro__width_8 check1_0_pty  (
	.din	({check1_bus	[5:0],
		  {2 {1'b0}}	       }),
	.dout	(check1_0		)
);

tlu_ecd_dp_prty_macro__width_8 check1_pty  (
	.din	({check1_0	       ,
		  check1_1	       ,
		  check1_2	       ,
		  check1_3	       ,
		  check1_4	       ,
		  {3 {1'b0}}	       }),
	.dout	(c1			)
);


// All positions with thirdmost LSB set
assign check2_bus[35:0] =
       {d[63:60],
        d[56:53], d[48:45], d[40:37], d[32:29], 
        d[25:22], d[17:14],
        d[10:7],
        d[3:1],
	e[2]};

tlu_ecd_dp_prty_macro__width_8 check2_4_pty  (
	.din	({1'b0,
		  check2_bus	[35:29]}),
	.dout	(check2_4		)
);

tlu_ecd_dp_prty_macro__width_8 check2_3_pty  (
	.din	(check2_bus	[28:21]	),
	.dout	(check2_3		)
);

tlu_ecd_dp_prty_macro__width_8 check2_2_pty  (
	.din	(check2_bus	[20:13]	),
	.dout	(check2_2		)
);

tlu_ecd_dp_prty_macro__width_8 check2_1_pty  (
	.din	(check2_bus	[12:5]	),
	.dout	(check2_1		)
);

tlu_ecd_dp_prty_macro__width_8 check2_0_pty  (
	.din	({check2_bus	[4:0],
		  {3 {1'b0}}	       }),
	.dout	(check2_0		)
);

tlu_ecd_dp_prty_macro__width_8 check2_pty  (
	.din	({check2_0	       ,
		  check2_1	       ,
		  check2_2	       ,
		  check2_3	       ,
		  check2_4	       ,
		  {3 {1'b0}}	       }),
	.dout	(c2			)
);


// All positions with fourthmost LSB set
assign check3_bus[35:0] =
       {d[67:64],
        d[56:49], d[40:33], 
        d[25:18],
        d[10:4],
	e[3]};

tlu_ecd_dp_prty_macro__width_8 check3_4_pty  (
	.din	({{1 {1'b0}}	       ,
		  check3_bus	[35:29]}),
	.dout	(check3_4		)
);

tlu_ecd_dp_prty_macro__width_8 check3_3_pty  (
	.din	(check3_bus	[28:21]	),
	.dout	(check3_3		)
);

tlu_ecd_dp_prty_macro__width_8 check3_2_pty  (
	.din	(check3_bus	[20:13]	),
	.dout	(check3_2		)
);

tlu_ecd_dp_prty_macro__width_8 check3_1_pty  (
	.din	(check3_bus	[12:5]	),
	.dout	(check3_1		)
);

tlu_ecd_dp_prty_macro__width_8 check3_0_pty  (
	.din	({check3_bus	[4:0],
		  {3 {1'b0}}	       }),
	.dout	(check3_0		)
);

tlu_ecd_dp_prty_macro__width_8 check3_pty  (
	.din	({check3_0	       ,
		  check3_1	       ,
		  check3_2	       ,
		  check3_3	       ,
		  check3_4	       ,
		  {3 {1'b0}}	       }),
	.dout	(c3			)
);


// All positions with fifthmost LSB set
assign check4_bus[31:0] =
       {d[56:41],
        d[25:11],
	e[4]};

tlu_ecd_dp_prty_macro__width_32 check4_pty  (
	.din	(check4_bus	[31:0]	),
	.dout	(c4			)
);


// All positions with sixthmost LSB set
assign check5_bus[31:0] =
       {d[56:26], 
	e[5]};

tlu_ecd_dp_prty_macro__width_32 check5_pty  (
	.din	(check5_bus	[31:0]	),
	.dout	(c5			)
);


// All positions with seventhmost LSB set
assign check6_bus[11:0] =
       {d[67:57],
	e[6]};

tlu_ecd_dp_prty_macro__width_16 check6_pty  (
	.din	({{4 {1'b0}}	       ,
		  check6_bus	[11:0]}),
	.dout	(c6			)
);


// Parity of the whole word (including ECC bits)
// Then xnor with e[07] to check the parity
// (or in this case, xor with e[07] to get miscompare)
assign check7_bus[74:0] =
      {d[67:0], e[6:0]};

tlu_ecd_dp_prty_macro__width_16 check7_4_pty  (
	.din	({{5 {1'b0}}	       ,
		  check7_bus	[74:64]}),
	.dout	(check7_4		)
);

tlu_ecd_dp_prty_macro__width_16 check7_3_pty  (
	.din	(check7_bus	[63:48]	),
	.dout	(check7_3		)
);

tlu_ecd_dp_prty_macro__width_16 check7_2_pty  (
	.din	(check7_bus	[47:32]	),
	.dout	(check7_2		)
);

tlu_ecd_dp_prty_macro__width_16 check7_1_pty  (
	.din	(check7_bus	[31:16]	),
	.dout	(check7_1		)
);

tlu_ecd_dp_prty_macro__width_16 check7_0_pty  (
	.din	(check7_bus	[15:0]	),
	.dout	(check7_0		)
);

tlu_ecd_dp_prty_macro__width_8 check7_inv_pty  (
	.din	({{2 {1'b0}}	      ,
		  e		[7   ],
		  check7_0	       ,
		  check7_1	       ,
		  check7_2	       ,
		  check7_3	       ,
		  check7_4	       }),
	.dout	(c7			)
);

tlu_ecd_dp_inv_macro__width_1 e7_inv  (
	.din	(e		[7   ]	),
	.dout	(e_		[7   ]	)
);

tlu_ecd_dp_prty_macro__width_8 check7_pty  (
	.din	({{2 {1'b0}}	      ,
		  e_		[7   ],
		  check7_0	       ,
		  check7_1	       ,
		  check7_2	       ,
		  check7_3	       ,
		  check7_4	       }),
	.dout	(c7_			)
);

assign parity_incorrect =
       c7;

assign parity_correct =
       c7_;


assign syndrome[7:0] = 
       {c7, c6, c5, c4, c3, c2, c1, c0};


// If the syndrome is zero and overall parity is correct, then no errors

// If overall parity is incorrect, then correctable
//assign cecc_err =
//       c7;
// If overall parity is correct and the syndrome is nonzero, then uncorrectable
//assign uecc_err =
//       (| ecc_out[06:00]) & ~c7;
// Also need to factor in CERER bits

tlu_ecd_dp_nor_macro__ports_3__width_1 ecc_err_2_nor   (
	.din0	(syndrome	[6]	),
	.din1	(syndrome	[5]	),
	.din2	(syndrome	[4]	),
	.dout	(ecc_err_0		)
);

tlu_ecd_dp_nor_macro__ports_2__width_1 ecc_err_1_nor   (
	.din0	(syndrome	[3]	),
	.din1	(syndrome	[2]	),
	.dout	(ecc_err_1		)
);

tlu_ecd_dp_nor_macro__ports_2__width_1 ecc_err_0_nor   (
	.din0	(syndrome	[1]	),
	.din1	(syndrome	[0]	),
	.dout	(ecc_err_2		)
);

tlu_ecd_dp_nand_macro__ports_3__width_1 ecc_err_nand   (
	.din0	(ecc_err_0		),
	.din1	(ecc_err_1		),
	.din2	(ecc_err_2		),
	.dout	(ecc_err		)
);

tlu_ecd_dp_and_macro__ports_2__width_1 cecc_err_and   (
 	.din0	(parity_incorrect	),
 	.din1	(cerer_ce		),
	.dout	(cecc_err		)
);

tlu_ecd_dp_and_macro__ports_3__width_1 uecc_err_and   (
	.din0	(ecc_err		),
 	.din1	(parity_correct		),
 	.din2	(cerer_ue		),
	.dout	(uecc_err		)
);

tlu_ecd_dp_nand_macro__ports_3__width_1 uecc_err_nand   (
	.din0	(ecc_err		),
 	.din1	(parity_correct		),
 	.din2	(cerer_ue		),
	.dout	(uecc_err_		)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

endmodule


//
//   parity macro (even parity)
//
//


module tlu_ecd_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module tlu_ecd_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module tlu_ecd_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module tlu_ecd_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module tlu_ecd_dp_nor_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nor3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module tlu_ecd_dp_nor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_ecd_dp_nand_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nand3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_ecd_dp_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_ecd_dp_and_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


and3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_ecg_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_ecg_dp (
  data_in, 
  ecc_out);
wire [67:0] d;
wire [36:0] check0_bus;
wire check0_4;
wire check0_3;
wire check0_2;
wire check0_1;
wire check0_0;
wire c0;
wire [36:0] check1_bus;
wire check1_4;
wire check1_3;
wire check1_2;
wire check1_1;
wire check1_0;
wire c1;
wire [34:0] check2_bus;
wire check2_3;
wire check2_2;
wire check2_1;
wire check2_0;
wire c2;
wire [34:0] check3_bus;
wire check3_3;
wire check3_2;
wire check3_1;
wire check3_0;
wire c3;
wire [30:0] check4_bus;
wire c4;
wire [30:0] check5_bus;
wire c5;
wire [10:0] check6_bus;
wire c6;
wire [36:0] check7_bus;
wire check7_4;
wire check7_3;
wire check7_2;
wire check7_1;
wire check7_0;
wire c7;


input	[67:0]	data_in;	// Used for generation and checking

output	[7:0]	ecc_out;	// Used for generation and checking


//////////////////////////////////////////////////////////////////////////////

// Position	Binary	
//	 1	0000001	C0
//	 2	0000010	C1
//	 3	0000011	D0
//
//	 4	0000100	C2
//	 5	0000101	D1
//	 6	0000110	D2
//	 7	0000111	D3
//			
//	 8 	0001000	C3
//	 9	0001001	D4
//	10	0001010	D5
//	11	0001011 D6
//	12	0001100	D7
//	...		...
//	15	0001111	D10
//			
//	16	0010000	C4
//	17	0010001	D11
//	...		...
//	20	0010100 D14
//	...		...
//	24	0011000	D18
//	...		...
//	28	0011100	D22
//	...		...
//	31	0011111	D25
//			
//	32	0100000	C5
//	33	0100001	D26
//	...		...
//	36	0100100	D29
//	...		...
//	40	0101000	D33
//	...		...
//	44	0101100	D37
//	...		...
//	48	0110000	D41
//	...		...
//	52	0110100	D45
//	...		...
//	56	0111000	D49
//	...		...
//	60	0111100	D53
//	...		...
//	63	0111111	D56
//			
//	64	1000000	C6
//	65	1000001	D57
//	...		...
//	68	1000100	D60
//	...		...
//	72	1001000	D64
//	73	1001001	D65
//	74	1001010	D66
//	75	1001011	D67
//			
//	76	1001100	C7

assign d[67:0] = 
       data_in[67:0];


// All odd positions (LSB of position set)
assign check0_bus[36:0] = 
	{d[67], d[65], d[63], d[61], d[59], d[57], 
	 d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42], 
	 d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26], 
	 d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], 
	 d[10], d[8], d[6], d[4], 
	 d[3], d[1],
	 d[0]};

tlu_ecg_dp_prty_macro__width_4 check0_4_pty  (
	.din	(check0_bus	[35:32]	),
	.dout	(check0_4		)
);

tlu_ecg_dp_prty_macro__width_8 check0_3_pty  (
	.din	(check0_bus	[31:24]	),
	.dout	(check0_3		)
);

tlu_ecg_dp_prty_macro__width_8 check0_2_pty  (
	.din	(check0_bus	[23:16]	),
	.dout	(check0_2		)
);

tlu_ecg_dp_prty_macro__width_8 check0_1_pty  (
	.din	(check0_bus	[15:8]	),
	.dout	(check0_1		)
);

tlu_ecg_dp_prty_macro__width_8 check0_0_pty  (
	.din	(check0_bus	[7:0]	),
	.dout	(check0_0		)
);

tlu_ecg_dp_prty_macro__width_8 check0_pty  (
	.din	({{2 {1'b0}}	       ,
		  check0_bus	[36   ],
		  check0_4	       ,
		  check0_3	       ,
		  check0_2	       ,
		  check0_1	       ,
		  check0_0	       }),
	.dout	(c0			)
);


// All positions with secondmost LSB set
assign check1_bus[36:0] =
       {d[67:66], d[63:62], d[59:58], 
        d[56:55], d[52:51], d[48:47], d[44:43],
        d[40:39], d[36:35], d[32:31], d[28:27],
        d[25:24], d[21:20], d[17:16], d[13:12],
        d[10:9], d[6:5], 
        d[3:2],
        d[0]};

tlu_ecg_dp_prty_macro__width_4 check1_4_pty  (
	.din	(check1_bus	[35:32]	),
	.dout	(check1_4		)
);

tlu_ecg_dp_prty_macro__width_8 check1_3_pty  (
	.din	(check1_bus	[31:24]	),
	.dout	(check1_3		)
);

tlu_ecg_dp_prty_macro__width_8 check1_2_pty  (
	.din	(check1_bus	[23:16]	),
	.dout	(check1_2		)
);

tlu_ecg_dp_prty_macro__width_8 check1_1_pty  (
	.din	(check1_bus	[15:8]	),
	.dout	(check1_1		)
);

tlu_ecg_dp_prty_macro__width_8 check1_0_pty  (
	.din	(check1_bus	[7:0]	),
	.dout	(check1_0		)
);

tlu_ecg_dp_prty_macro__width_8 check1_pty  (
	.din	({{2 {1'b0}}	       ,
		  check1_bus	[36   ],
		  check1_4	       ,
		  check1_3	       ,
		  check1_2	       ,
		  check1_1	       ,
		  check1_0	       }),
	.dout	(c1			)
);


// All positions with thirdmost LSB set
assign check2_bus[34:0] =
       {d[63:60],
        d[56:53], d[48:45], d[40:37], d[32:29], 
        d[25:22], d[17:14],
        d[10:7],
        d[3:1]};

tlu_ecg_dp_prty_macro__width_8 check2_3_pty  (
	.din	(check2_bus	[31:24]	),
	.dout	(check2_3		)
);

tlu_ecg_dp_prty_macro__width_8 check2_2_pty  (
	.din	(check2_bus	[23:16]	),
	.dout	(check2_2		)
);

tlu_ecg_dp_prty_macro__width_8 check2_1_pty  (
	.din	(check2_bus	[15:8]	),
	.dout	(check2_1		)
);

tlu_ecg_dp_prty_macro__width_8 check2_0_pty  (
	.din	(check2_bus	[7:0]	),
	.dout	(check2_0		)
);

tlu_ecg_dp_prty_macro__width_8 check2_pty  (
	.din	({{1 {1'b0}}	       ,
		  check2_bus	[34:32],
		  check2_3	       ,
		  check2_2	       ,
		  check2_1	       ,
		  check2_0	       }),
	.dout	(c2			)
);


// All positions with fourthmost LSB set
assign check3_bus[34:0] =
       {d[67:64],
        d[56:49], d[40:33], 
        d[25:18],
        d[10:4]};

tlu_ecg_dp_prty_macro__width_8 check3_3_pty  (
	.din	(check3_bus	[31:24]	),
	.dout	(check3_3		)
);

tlu_ecg_dp_prty_macro__width_8 check3_2_pty  (
	.din	(check3_bus	[23:16]	),
	.dout	(check3_2		)
);

tlu_ecg_dp_prty_macro__width_8 check3_1_pty  (
	.din	(check3_bus	[15:8]	),
	.dout	(check3_1		)
);

tlu_ecg_dp_prty_macro__width_8 check3_0_pty  (
	.din	(check3_bus	[7:0]	),
	.dout	(check3_0		)
);

tlu_ecg_dp_prty_macro__width_8 check3_pty  (
	.din	({{1 {1'b0}}	       ,
		  check3_bus	[34:32],
		  check3_3	       ,
		  check3_2	       ,
		  check3_1	       ,
		  check3_0	       }),
	.dout	(c3			)
);


// All positions with fifthmost LSB set
assign check4_bus[30:0] =
       {d[56:41],
        d[25:11]};

tlu_ecg_dp_prty_macro__width_32 check4_pty  (
	.din	({{1 {1'b0}}	       ,
		  check4_bus	[30:0]}),
	.dout	(c4			)
);


// All positions with sixthmost LSB set
assign check5_bus[30:0] =
       {d[56:26]};

tlu_ecg_dp_prty_macro__width_32 check5_pty  (
	.din	({{1 {1'b0}}	       ,
		  check5_bus	[30:0]}),
	.dout	(c5			)
);


// All positions with seventhmost LSB set
assign check6_bus[10:0] =
       {d[67:57]};

tlu_ecg_dp_prty_macro__width_16 check6_pty  (
	.din	({{5 {1'b0}}	       ,
		  check6_bus	[10:0]}),
	.dout	(c6			)
);


// Parity of the whole word (including check bits)
//assign check7_bus[74:00] =
//      {d[67:00], c0, c1, c2, c3, c4, c5, c6};
// But in generation this simplifies to
//	(all d bits with even parity binary positions)

assign check7_bus[36:0] =
//        76
       {d[67],
//	  72     71     68     66     65     63     60     58     57
        d[64], d[63], d[60], d[58], d[57], d[56], d[53], d[51], d[50],
//        54     53     51     48     46     45     43     40     39     
	d[47], d[46], d[44], d[41], d[39], d[38], d[36], d[33], d[32],
//	  36     34     33     30     29     27     24     23     20
	d[29], d[27], d[26], d[24], d[23], d[21], d[18], d[17], d[14],
//        18     17     15     12     10      9      6      5      3
	d[12], d[11], d[10], d[7], d[5], d[4], d[2], d[1], d[0]};

tlu_ecg_dp_prty_macro__width_4 check7_4_pty  (
	.din	(check7_bus	[35:32]	),
	.dout	(check7_4		)
);

tlu_ecg_dp_prty_macro__width_8 check7_3_pty  (
	.din	(check7_bus	[31:24]	),
	.dout	(check7_3		)
);

tlu_ecg_dp_prty_macro__width_8 check7_2_pty  (
	.din	(check7_bus	[23:16]	),
	.dout	(check7_2		)
);

tlu_ecg_dp_prty_macro__width_8 check7_1_pty  (
	.din	(check7_bus	[15:8]	),
	.dout	(check7_1		)
);

tlu_ecg_dp_prty_macro__width_8 check7_0_pty  (
	.din	(check7_bus	[7:0]	),
	.dout	(check7_0		)
);

tlu_ecg_dp_prty_macro__width_8 check7_pty  (
	.din	({{2 {1'b0}}	       ,
		  check7_bus	[36   ],
		  check7_4	       ,
		  check7_3	       ,
		  check7_2	       ,
		  check7_1	       ,
		  check7_0	       }),
	.dout	(c7			)
);

assign ecc_out[7:0] = 
       {c7, c6, c5, c4, c3, c2, c1, c0};


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

endmodule


//
//   parity macro (even parity)
//
//


module tlu_ecg_dp_prty_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output dout;


prty #(4)  m0_0 (
.in(din[3:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module tlu_ecg_dp_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module tlu_ecg_dp_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module tlu_ecg_dp_prty_macro__width_16 (
  din, 
  dout);
  input [15:0] din;
  output dout;


prty #(16)  m0_0 (
.in(din[15:0]),
.out(dout)
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_eem_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_eem_dp (
  asi_error_inject, 
  asi_error_mask, 
  asi_mbist_ecc_in, 
  asi_mbist_run, 
  ecc_in, 
  ecc_out);
wire [7:0] error_inject;
wire [7:0] ecc_pre_mux;
wire [7:0] ecc_mux_0;
wire mbist_run_;
wire [7:0] ecc_mux_1;


input		asi_error_inject;
input	[7:0]	asi_error_mask;

input	[7:0]	asi_mbist_ecc_in;
input		asi_mbist_run;

input 	[7:0]	ecc_in;

output	[7:0]	ecc_out;	


//assign wr_ecc[07:00] = 
//	 ((pwr_ecc[07:00] ^ 
//	   ({8 {asi_error_tsau}} & asi_error_mask[07:00])) & 
//	  {8 {~asi_mbist_run}}) | asi_mbist_tsa_ecc_in[07:00];
//

tlu_eem_dp_and_macro__ports_2__stack_8r__width_8 error_inject_and    (
	.din0	({8 {asi_error_inject}}		),
	.din1	(asi_error_mask		[7:0]	),
	.dout	(error_inject		[7:0]	)
);

tlu_eem_dp_xor_macro__ports_2__stack_8r__width_8 ecc_pre_mux_xor    (
	.din0	(ecc_in			[7:0]	),
	.din1	(error_inject		[7:0]	),
	.dout	(ecc_pre_mux		[7:0]	)
);

tlu_eem_dp_inv_macro__stack_8r__width_8 ecc_mux_0_nand   (
	.din	(asi_mbist_ecc_in	[7:0]	),
	.dout	(ecc_mux_0		[7:0]	)
);

tlu_eem_dp_inv_macro__stack_8r__width_1 mbist_run_inv   (
	.din	(asi_mbist_run			),
	.dout	(mbist_run_			)
);

tlu_eem_dp_nand_macro__ports_2__stack_8r__width_8 ecc_mux_1_nand    (
	.din0	(ecc_pre_mux		[7:0]	),
	.din1	({8 {mbist_run_}}		),
	.dout	(ecc_mux_1		[7:0]	)
);

tlu_eem_dp_nand_macro__ports_2__stack_8r__width_8 ecc_mux_nand    (
	.din0	(ecc_mux_0		[7:0]	),
	.din1	(ecc_mux_1		[7:0]	),
	.dout	(ecc_out		[7:0]	)
);

//mux_macro ecc_mux (width=8, ports=2, mux=aope, stack=8r) (
//	  .din0	(asi_mbist_ecc_in	[07:00]	),
//	  .din1	(ecc_pre_mux		[07:00]	),
//	  .sel0	(asi_mbist_run			),
//	  .dout	(ecc_out		[07:00]	)
//);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_eem_dp_and_macro__ports_2__stack_8r__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


and2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module tlu_eem_dp_xor_macro__ports_2__stack_8r__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


xor2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module tlu_eem_dp_inv_macro__stack_8r__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module tlu_eem_dp_inv_macro__stack_8r__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_eem_dp_nand_macro__ports_2__stack_8r__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


nand2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_fls_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_fls_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lsu_tlu_pmen, 
  thread_group, 
  trl_shscanid, 
  tcu_core_running, 
  tcu_ss_mode, 
  tcu_do_mode, 
  tcu_ss_request, 
  cxi_xir, 
  cxi_ivt, 
  dec_raw_pick_p, 
  dec_tid_m, 
  dec_inst_valid_m, 
  dec_lsu_inst_m, 
  dec_fgu_inst_m, 
  dec_illegal_inst_m, 
  dec_exc_m, 
  dec_done_inst_m, 
  dec_retry_inst_m, 
  dec_sir_inst_m, 
  dec_hpriv_exc_m, 
  dec_priv_exc_m, 
  dec_fpdisable_exc_m, 
  dec_br_taken_m, 
  dec_annul_ds_m, 
  dec_ds_m, 
  dec_icache_perr_m, 
  dec_cti_inst_m, 
  dec_flush_b, 
  exu_ibp_m, 
  exu_tcc_m, 
  exu_tof_m, 
  exu_cecc_m, 
  exu_uecc_m, 
  exu_oor_va_m, 
  exu_misalign_m, 
  exu_spill_b, 
  exu_fill_m, 
  exu_normal_b, 
  exu_cleanwin_b, 
  exu_wstate_b, 
  exu_trap_number_b, 
  exu_cwp0, 
  exu_cwp1, 
  exu_cwp2, 
  exu_cwp3, 
  lsu_lddf_align_b, 
  lsu_stdf_align_b, 
  lsu_illegal_inst_b, 
  lsu_daccess_prot_b, 
  lsu_priv_action_b, 
  lsu_va_watchpoint_b, 
  lsu_pa_watchpoint_b, 
  lsu_align_b, 
  lsu_tlb_miss_b_, 
  lsu_dae_invalid_asi_b, 
  lsu_dae_nc_page_b, 
  lsu_dae_nfo_page_b, 
  lsu_dae_priv_viol_b, 
  lsu_dae_so_page, 
  lsu_priv_action_g, 
  lsu_tid_g, 
  lsu_trap_flush, 
  lsu_spec_enable, 
  lsu_tlb_bypass_b, 
  lsu_tlb_real_b, 
  lsu_sync_inst_b, 
  lsu_tlu_twocycle_m, 
  lsu_block_store_b, 
  lsu_dcl2u_err_g, 
  lsu_dcl2nd_err_g, 
  lsu_dcerr_tid_g, 
  lsu_sbdlc_err_g, 
  lsu_sbdlu_err_g, 
  lsu_sbapp_err_g, 
  lsu_sbdiou_err_g, 
  lsu_stberr_tid_g, 
  lsu_dttp_err_b, 
  lsu_dtdp_err_b, 
  lsu_dtmh_err_b, 
  lsu_perfmon_trap_b, 
  lsu_perfmon_trap_g, 
  lsu_immu_enable, 
  fgu_predict_fx2, 
  fgu_pdist_beat2_fx1, 
  fgu_cecc_fx2, 
  fgu_uecc_fx2, 
  fgu_fpx_ieee_trap_fw, 
  fgu_fpd_ieee_trap_fw, 
  fgu_fpx_unfin_fw, 
  fgu_fpd_unfin_fw, 
  fgu_fpd_idiv0_trap_fw, 
  fgu_fpx_trap_tid_fw, 
  fgu_fpd_trap_tid_fw, 
  asi_ece_exc, 
  asi_eue_exc, 
  asi_ecc_tid, 
  asi_irl_cleared, 
  asi_halt, 
  asi_decr, 
  asi_clear_spu_trap_req, 
  tel_tsacu_exc, 
  mmu_hw_tw_enable, 
  mmu_i_unauth_access, 
  mmu_i_tsb_miss, 
  mmu_d_tsb_miss, 
  mmu_i_tte_outofrange, 
  mmu_d_tte_outofrange, 
  mmu_asi_cecc, 
  mmu_asi_uecc, 
  mmu_asi_tid, 
  mmu_i_eccerr, 
  mmu_d_eccerr, 
  mmu_thr0_err_type_b1, 
  mmu_thr1_err_type_b1, 
  mmu_thr2_err_type_b1, 
  mmu_thr3_err_type_b1, 
  mmu_dae_req, 
  mmu_dae_tid, 
  spu_tlu_ma_int_req, 
  spu_tlu_cwq_int_req, 
  pmu_tlu_trap_m, 
  pmu_tlu_debug_event, 
  pct_iaw_exc_e, 
  pct_npc_0_w, 
  pct_npc_1_w, 
  pct_npc_2_w, 
  pct_npc_3_w, 
  pct_pc_oor_va_e, 
  flsx_flush_lsu_b, 
  flsx_flush_fgu_b, 
  trl_tl_eq_0, 
  trl_pil_mask_15, 
  trl_iln_exc, 
  trl_hstick_match, 
  trl_unhalt_, 
  trl_tlz_exc, 
  trl_nns_exc, 
  trl_ssc_exc, 
  trl_invalidate_pc, 
  trl_invalidate_npc, 
  trl_pc_sel_trap_pc, 
  trl_fls_npc_en, 
  trl_trap_taken, 
  trl_take_sma, 
  trl_take_cwq, 
  trl_take_xir, 
  trl_take_ftt, 
  trl_core_running_status, 
  trl_check_rqr, 
  tlu_ceter_de, 
  tlu_ceter_dhcce, 
  tsd_hpstate_ibe, 
  tsd_hpstate_hpriv, 
  tsd_hpstate_red, 
  tsd_pstate_tct, 
  tsd_pstate_priv, 
  tsd_pstate_ie, 
  tsd_pstate_am, 
  tsd_itlb_bypass, 
  tsd_mrqr_exc_, 
  tsd_dqr_exc_, 
  asi_check_qr_exc, 
  dfd_fls_desr_f, 
  dfd_fls_desr_s, 
  ras_precise_error, 
  ras_disrupting_error, 
  ras_deferred_error, 
  scan_out, 
  wmr_scan_out, 
  fls_spc_hardstop_request, 
  fls_spc_softstop_request, 
  fls_spc_trigger_pulse, 
  tlu_dbg_instr_cmt_grp, 
  tlu_flush_ifu, 
  tlu_flush_exu_b, 
  tlu_flush_lsu_b, 
  tlu_flush_fgu_b, 
  tlu_flush_pmu_b, 
  tlu_flush_pmu_w, 
  tlu_load_i_tag_access_p, 
  tlu_load_i_tag_access_n, 
  tlu_load_d_tag_access, 
  tlu_load_d_tag_access_r, 
  fls_flush_lsu_b, 
  fls_flush_fgu_b, 
  fls_pc_is_npc, 
  fls_tid_d, 
  fls_tid_dec_b, 
  fls_tid_dec_w, 
  fls_pc_sel_npc, 
  fls_pc_sel_npc_plus_4, 
  fls_npc_sel_npc_plus_4, 
  fls_npc_sel_npc_plus_8, 
  fls_npc_sel_target, 
  fls_npc_b_sel_npc, 
  fls_pstate_am_d_, 
  fls_pstate_am_b_, 
  fls_pstate_am_w_, 
  fls_lsu_inst_w, 
  fls_dfd_lsu_inst_b, 
  fls_wstate0, 
  fls_wstate1, 
  fls_wstate2, 
  fls_wstate3, 
  fls_tcc_number_0, 
  fls_tcc_number_1, 
  fls_tcc_number_2, 
  fls_tcc_number_3, 
  fls_tid_dec_w_in, 
  fls_por_request, 
  fls_xir_request, 
  fls_ivt_request, 
  fls_sir_request, 
  fls_itm_request, 
  fls_iln_request, 
  fls_hst_request, 
  fls_tlz_request, 
  fls_sma_request, 
  fls_cwq_request, 
  fls_ade_request, 
  fls_iae_request, 
  fls_ipe_request, 
  fls_ipv_request, 
  fls_inp_request, 
  fls_iar_request, 
  fls_irr_request, 
  fls_mar_request, 
  fls_mrr_request, 
  fls_pro_request, 
  fls_ill_request, 
  fls_don_request, 
  fls_ret_request, 
  fls_fpd_request, 
  fls_snn_request, 
  fls_sno_request, 
  fls_fnn_request, 
  fls_fno_request, 
  fls_clw_request, 
  fls_dtm_request, 
  fls_ldf_request, 
  fls_stf_request, 
  fls_dap_request, 
  fls_vaw_request, 
  fls_iaw_request, 
  fls_paw_request, 
  fls_maa_request, 
  fls_fpe_request, 
  fls_fei_request, 
  fls_fof_request, 
  fls_pra_request, 
  fls_dia_request, 
  fls_ups_request, 
  fls_dpv_request, 
  fls_dnc_request, 
  fls_dnf_request, 
  fls_dso_request, 
  fls_tof_request, 
  fls_dbz_request, 
  fls_tcc_request, 
  fls_dae_request, 
  fls_lsr_request, 
  fls_irt_request, 
  fls_drt_request, 
  fls_pmu_request, 
  fls_mqr_request, 
  fls_dqr_request, 
  fls_rqr_request, 
  fls_idl_request, 
  fls_res_request, 
  fls_ssr_request, 
  fls_ssc_request, 
  fls_nns_request, 
  fls_ime_request, 
  fls_dme_request, 
  fls_eer_request, 
  fls_icp_request, 
  fls_ftt_request, 
  fls_ibp_request, 
  fls_tct_request, 
  fls_ref_request, 
  fls_ipe_dme_request, 
  fls_pc_valid, 
  fls_load_dsfar, 
  fls_irf_cecc_b, 
  fls_irf_uecc_b, 
  fls_kill_irf_ecc_w, 
  fls_cwp0, 
  fls_cwp1, 
  fls_cwp2, 
  fls_cwp3, 
  fls_core_running, 
  fls_ss_request, 
  fls_pct_pc_en, 
  fls_pct_npc_en, 
  fls_trl_l1en, 
  fls_npc_if_cnt_eq_1_d, 
  fls_npc_if_cnt_eq_2_d, 
  fls_npc_if_cnt_eq_3_d, 
  fls_flush, 
  fls_disrupting_flush_w, 
  fls_f_cecc_w, 
  fls_f_uecc_w, 
  fls_ss_update_pc_w, 
  tlu_iht_request, 
  tlu_dht_request, 
  tlu_itlb_bypass_e, 
  tlu_tag_access_tid_b, 
  tlu_i_tag_access_b, 
  tlu_d_tag_access_b, 
  tlu_retry_state, 
  tlu_halted);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire beat_two_b_in;
wire l_tlu_twocycle_b;
wire fgu_inst_b;
wire beat_two_b_lat_scanin;
wire beat_two_b_lat_scanout;
wire beat_two_b;
wire pbeat_two_b;
wire beat_two_w;
wire exc_for_w;
wire l1en_b2w_in;
wire pre_inst_valid_b;
wire l1en_b2w;
wire [3:0] tid_dec_w;
wire [3:0] flush_gfb;
wire [3:0] m_dae_req_w;
wire [3:0] por_req;
wire [3:0] res_req;
wire [3:0] trap_flush;
wire [3:0] pdist_ecc_w;
wire [3:0] ssr_req;
wire [3:0] multicycle_nns_to_npc_w;
wire l1en_b2w_lat_scanin;
wire l1en_b2w_lat_scanout;
wire l1clk_pm1;
wire l1clk;
wire hpstate_hpriv_lat_scanin;
wire hpstate_hpriv_lat_scanout;
wire [3:0] hpstate_hpriv;
wire [3:0] hpriv_bar_or_ie_in;
wire hpriv_bar_or_ie_lat_scanin;
wire hpriv_bar_or_ie_lat_scanout;
wire [3:0] phpriv_bar_or_ie;
wire [3:0] hpriv_bar_or_ie_m;
wire [3:0] tid_dec_m;
wire [3:0] hpriv_bar_and_ie_in;
wire hpriv_bar_and_ie_lat_scanin;
wire hpriv_bar_and_ie_lat_scanout;
wire [3:0] hpriv_bar_and_ie;
wire [1:0] tid_p;
wire tid_dec_d_lat_scanin;
wire tid_dec_d_lat_scanout;
wire [1:0] tid_d;
wire [3:0] tid_dec_d;
wire itlb_bypass_lat_scanin;
wire itlb_bypass_lat_scanout;
wire [3:0] itlb_bypass;
wire itlb_bypass_d;
wire itlb_bypass_e_lat_scanin;
wire itlb_bypass_e_lat_scanout;
wire itlb_bypass_e;
wire l_tlu_twocycle_b_in;
wire l_tlu_twocycle_b_lat_scanin;
wire l_tlu_twocycle_b_lat_scanout;
wire [1:0] tid_m;
wire twocycle_inst_b;
wire [1:0] tid_b;
wire tid_b_lat_scanin;
wire tid_b_lat_scanout;
wire fast_tid_dec_b_lat_scanin;
wire fast_tid_dec_b_lat_scanout;
wire [3:0] fast_tid_dec_b;
wire inst_valid_m;
wire pre_inst_valid_b_lat_scanin;
wire pre_inst_valid_b_lat_scanout;
wire [3:0] tid_dec_b;
wire tl_eq_0_lat_scanin;
wire tl_eq_0_lat_scanout;
wire [3:0] tl_eq_0;
wire tl_eq_0_b;
wire inst_valid_b;
wire flush_b;
wire preflush_exu_b;
wire exception_for_w;
wire bsee_flush_b;
wire lsu_inst_m;
wire lsu_inst_b;
wire lsu_inst_b_lat_scanin;
wire lsu_inst_b_lat_scanout;
wire fgu_inst_m;
wire fgu_inst_b_lat_scanin;
wire fgu_inst_b_lat_scanout;
wire illegal_inst_b_in;
wire illegal_inst_b_lat_scanin;
wire illegal_inst_b_lat_scanout;
wire pillegal_inst_b;
wire illegal_inst_b;
wire illegal_sir_b;
wire illegal_done_inst_b;
wire illegal_retry_inst_b;
wire itlb_miss_m;
wire itlb_miss_b_lat_scanin;
wire itlb_miss_b_lat_scanout;
wire itlb_miss_b;
wire ra_itlb_miss_m;
wire ra_itlb_miss_b_lat_scanin;
wire ra_itlb_miss_b_lat_scanout;
wire ra_itlb_miss_b;
wire itlb_priv_exc_m;
wire itlb_priv_exc_b_lat_scanin;
wire itlb_priv_exc_b_lat_scanout;
wire itlb_priv_exc_b;
wire itlb_nfo_exc_m;
wire itlb_nfo_exc_b_lat_scanin;
wire itlb_nfo_exc_b_lat_scanout;
wire itlb_nfo_exc_b;
wire i_l2_unde_m;
wire i_l2_unde_b_lat_scanin;
wire i_l2_unde_b_lat_scanout;
wire i_l2_unde_b;
wire i_oor_va_m;
wire i_oor_va_b_lat_scanin;
wire i_oor_va_b_lat_scanout;
wire i_oor_va_b;
wire i_ra_oor_va_m;
wire i_ra_oor_va_b_lat_scanin;
wire i_ra_oor_va_b_lat_scanout;
wire i_ra_oor_va_b;
wire itlb_err_m;
wire itlb_err_b_lat_scanin;
wire itlb_err_b_lat_scanout;
wire itlb_err_b;
wire pre_icache_exc_m;
wire ic_err_m;
wire ic_err_b_lat_scanin;
wire ic_err_b_lat_scanout;
wire ic_err_b;
wire done_inst_b_in;
wire done_inst_b_lat_scanin;
wire done_inst_b_lat_scanout;
wire pdone_inst_b;
wire done_inst_b;
wire priv_exc_b;
wire retry_inst_b_in;
wire retry_inst_b_lat_scanin;
wire retry_inst_b_lat_scanout;
wire pretry_inst_b;
wire retry_inst_b;
wire sir_b_in;
wire sir_b_lat_scanin;
wire sir_b_lat_scanout;
wire psir_b;
wire in_hpriv_b;
wire sir_b;
wire hpriv_exc_b_in;
wire hpriv_exc_b_lat_scanin;
wire hpriv_exc_b_lat_scanout;
wire hpriv_exc_b;
wire priv_exc_b_in;
wire priv_exc_b_lat_scanin;
wire priv_exc_b_lat_scanout;
wire fpdisable_exc_b_in;
wire fpdisable_exc_b_lat_scanin;
wire fpdisable_exc_b_lat_scanout;
wire fpdisable_exc_b;
wire e_cecc_b_in;
wire e_uecc_b_in;
wire ecc_b_lat_scanin;
wire ecc_b_lat_scanout;
wire e_cecc_b;
wire e_uecc_b;
wire misalign_b_in;
wire misalign_b_lat_scanin;
wire misalign_b_lat_scanout;
wire misalign_b;
wire e_oor_va_b_lat_scanin;
wire e_oor_va_b_lat_scanout;
wire pe_oor_va_b;
wire e_oor_va_b;
wire pstate_am_b;
wire e_tcc_b_in;
wire e_tcc_b_lat_scanin;
wire e_tcc_b_lat_scanout;
wire e_tcc_b;
wire e_tof_b_in;
wire e_tof_b_lat_scanin;
wire e_tof_b_lat_scanout;
wire e_tof_b;
wire e_fill_b_in;
wire e_fill_b_lat_scanin;
wire e_fill_b_lat_scanout;
wire e_fill_b;
wire br_exc_b;
wire pdec_exc_b;
wire br_oor_va_b;
wire br_ra_oor_va_b;
wire [3:0] perf_trap_b;
wire ibp_b;
wire iaw_b;
wire tct_b;
wire target_oor_b;
wire disrupting_flush_pending_tid_dec_b;
wire br_taken_b_in;
wire br_taken_b_lat_scanin;
wire br_taken_b_lat_scanout;
wire pre_br_taken_b;
wire br_taken_b;
wire annul_ds_m_lat_scanin;
wire annul_ds_m_lat_scanout;
wire pre_annul_ds_b;
wire annul_ds_b;
wire ds_b_lat_scanin;
wire ds_b_lat_scanout;
wire pre_ds_b;
wire ds_b;
wire [3:0] perf_trap_m;
wire [3:0] pil_mask_15;
wire perf_trap_b_lat_scanin;
wire perf_trap_b_lat_scanout;
wire pil_mask_15_lat_scanin;
wire pil_mask_15_lat_scanout;
wire ibe_m;
wire ibp_b_in;
wire ibp_b_lat_scanin;
wire ibp_b_lat_scanout;
wire itlb_va_pa_enabled;
wire [3:0] immu_enable;
wire iaw_exc_m_in;
wire iaw_exc_m_lat_scanin;
wire iaw_exc_m_lat_scanout;
wire iaw_exc_m;
wire iaw_b_in;
wire iaw_b_lat_scanin;
wire iaw_b_lat_scanout;
wire pstate_tct_m;
wire pstate_tct_b_lat_scanin;
wire pstate_tct_b_lat_scanout;
wire pstate_tct_b;
wire tct_b_in_b;
wire tct_b_in;
wire tct_b_lat_scanin;
wire tct_b_lat_scanout;
wire ptct_b;
wire cti_b_in;
wire cti_b_lat_scanin;
wire cti_b_lat_scanout;
wire cti_b;
wire disrupting_flush_b;
wire pmu_debug_exc_b;
wire twocycle_inst_w_lat_scanin;
wire twocycle_inst_w_lat_scanout;
wire ptwocycle_inst_w;
wire twocycle_inst_w;
wire d_flush_w_lat_scanin;
wire d_flush_w_lat_scanout;
wire d_flush_w;
wire [3:0] dec_inst_valid_b;
wire [3:0] tid_dec_w_in;
wire tid_dec_w_lat_scanin;
wire tid_dec_w_lat_scanout;
wire pstate_am_b_in;
wire pstate_am_b_lat_scanin;
wire pstate_am_b_lat_scanout;
wire pstate_am_w_lat_scanin;
wire pstate_am_w_lat_scanout;
wire pstate_am_w;
wire [3:0] dec_two_tid_b;
wire [3:0] two_tid_dec_w_in;
wire two_tid_dec_w_lat_scanin;
wire two_tid_dec_w_lat_scanout;
wire [3:0] two_tid_dec_w;
wire inst_valid_w_lat_scanin;
wire inst_valid_w_lat_scanout;
wire pre_inst_valid_w;
wire inst_valid_w;
wire illegal_inst_w_in;
wire kill_exc_gt_6_lt_7_b_;
wire illegal_inst_w_lat_scanin;
wire illegal_inst_w_lat_scanout;
wire illegal_inst_w;
wire itlb_miss_w_in;
wire m103663_exc_b;
wire kill_exc_lt_6_b_;
wire itlb_miss_w_lat_scanin;
wire itlb_miss_w_lat_scanout;
wire itlb_miss_w;
wire ra_itlb_miss_w_in;
wire ra_itlb_miss_w_lat_scanin;
wire ra_itlb_miss_w_lat_scanout;
wire ra_itlb_miss_w;
wire itlb_priv_exc_w_in;
wire itlb_priv_exc_w_lat_scanin;
wire itlb_priv_exc_w_lat_scanout;
wire itlb_priv_exc_w;
wire itlb_nfo_exc_w_in;
wire itlb_nfo_exc_w_lat_scanin;
wire itlb_nfo_exc_w_lat_scanout;
wire itlb_nfo_exc_w;
wire i_l2_unde_w_in;
wire i_l2_err_w_lat_scanin;
wire i_l2_err_w_lat_scanout;
wire i_l2_unde_w;
wire i_oor_va_w_in;
wire target_oor_va_b;
wire kill_exc_iar_irr_b_;
wire i_oor_va_w_lat_scanin;
wire i_oor_va_w_lat_scanout;
wire i_oor_va_w;
wire i_ra_oor_va_w_in;
wire target_ra_oor_va_b;
wire i_ra_oor_va_w_lat_scanin;
wire i_ra_oor_va_w_lat_scanout;
wire i_ra_oor_va_w;
wire itlb_err_w_in;
wire itlb_err_w_lat_scanin;
wire itlb_err_w_lat_scanout;
wire itlb_err_w;
wire ic_err_w_in;
wire icp_req_in;
wire ic_err_w_lat_scanin;
wire ic_err_w_lat_scanout;
wire icp_req;
wire done_inst_w_in;
wire kill_exc_b_;
wire done_inst_w_lat_scanin;
wire done_inst_w_lat_scanout;
wire done_inst_w;
wire retry_inst_w_in;
wire retry_inst_w_lat_scanin;
wire retry_inst_w_lat_scanout;
wire retry_inst_w;
wire sir_w_in;
wire dsc_req_in;
wire sir_w_lat_scanin;
wire sir_w_lat_scanout;
wire sir_w;
wire hpriv_exc_w_in;
wire hpriv_exc_w_lat_scanin;
wire hpriv_exc_w_lat_scanout;
wire hpriv_exc_w;
wire priv_exc_w_in;
wire kill_exc_ge_7_lt_11_b_;
wire priv_exc_w_lat_scanin;
wire priv_exc_w_lat_scanout;
wire priv_exc_w;
wire fpdisable_exc_w_in;
wire fpdisable_exc_w_lat_scanin;
wire fpdisable_exc_w_lat_scanout;
wire fpdisable_exc_w;
wire tcc_w_in;
wire tcc_w_lat_scanin;
wire tcc_w_lat_scanout;
wire tcc_w;
wire tof_w_in;
wire tof_w_lat_scanin;
wire tof_w_lat_scanout;
wire tof_w;
wire kill_e_f_ecc_b;
wire e_ecc_b;
wire e_f_ecc_w_in;
wire f_ecc_b;
wire e_ecc_w_lat_scanin;
wire e_ecc_w_lat_scanout;
wire e_f_ecc_w;
wire kill_irf_ecc_w_lat_scanin;
wire kill_irf_ecc_w_lat_scanout;
wire kill_e_f_ecc_w;
wire e_misalign_b;
wire fnn_b;
wire fno_b;
wire e_misalign_w_in;
wire e_misalign_w_lat_scanin;
wire e_misalign_w_lat_scanout;
wire e_misalign_w;
wire immu_enable_lat_scanin;
wire immu_enable_lat_scanout;
wire br_real_b;
wire br_bypass_b;
wire ld_oor_va_b;
wire br_oor_va_w_in;
wire br_ld_oor_va_w_in;
wire br_ld_oor_va_w_lat_scanin;
wire br_ld_oor_va_w_lat_scanout;
wire br_ld_oor_va_w;
wire ld_ra_oor_va_b;
wire br_ra_oor_va_w_in;
wire br_ld_ra_oor_va_w_in;
wire br_ld_ra_oor_va_w_lat_scanin;
wire br_ld_ra_oor_va_w_lat_scanout;
wire br_ld_ra_oor_va_w;
wire pc_oor_va_b_lat_scanin;
wire pc_oor_va_b_lat_scanout;
wire pc_oor_va_m;
wire pc_oor_va_b;
wire snn_b;
wire sno_b;
wire snn_w_in;
wire sno_w_in;
wire fnn_w_in;
wire fno_w_in;
wire snn_w_lat_scanin;
wire snn_w_lat_scanout;
wire snn_w;
wire sno_w_lat_scanin;
wire sno_w_lat_scanout;
wire sno_w;
wire fnn_w_lat_scanin;
wire fnn_w_lat_scanout;
wire fnn_w;
wire fno_w_lat_scanin;
wire fno_w_lat_scanout;
wire fno_w;
wire clw_b;
wire clw_w_in;
wire clw_w_lat_scanin;
wire clw_w_lat_scanout;
wire clw_w;
wire lsu_inst_w_lat_scanin;
wire lsu_inst_w_lat_scanout;
wire lsu_inst_w;
wire cti_w_lat_scanin;
wire cti_w_lat_scanout;
wire cti_w;
wire [2:0] wstate3_b;
wire [2:0] wstate3_w;
wire wstate3_w_lat_scanin;
wire wstate3_w_lat_scanout;
wire [2:0] wstate2_b;
wire [2:0] wstate2_w;
wire wstate2_w_lat_scanin;
wire wstate2_w_lat_scanout;
wire [2:0] wstate1_b;
wire [2:0] wstate1_w;
wire wstate1_w_lat_scanin;
wire wstate1_w_lat_scanout;
wire [2:0] wstate0_b;
wire [2:0] wstate0_w;
wire wstate0_w_lat_scanin;
wire wstate0_w_lat_scanout;
wire in_user_b;
wire [7:0] trap_number_b;
wire trap_number_w_lat_scanin;
wire trap_number_w_lat_scanout;
wire [7:0] trap_number_w;
wire [7:0] trap_number_3_in;
wire [7:0] trap_number_3;
wire trap_number_3_lat_scanin;
wire trap_number_3_lat_scanout;
wire [7:0] trap_number_2_in;
wire [7:0] trap_number_2;
wire trap_number_2_lat_scanin;
wire trap_number_2_lat_scanout;
wire [7:0] trap_number_1_in;
wire [7:0] trap_number_1;
wire trap_number_1_lat_scanin;
wire trap_number_1_lat_scanout;
wire [7:0] trap_number_0_in;
wire [7:0] trap_number_0;
wire trap_number_0_lat_scanin;
wire trap_number_0_lat_scanout;
wire lddf_align_b;
wire lddf_align_w_in;
wire lddf_align_w_lat_scanin;
wire lddf_align_w_lat_scanout;
wire lddf_align_w;
wire stdf_align_b;
wire stdf_align_w_in;
wire stdf_align_w_lat_scanin;
wire stdf_align_w_lat_scanout;
wire stdf_align_w;
wire daccess_prot_b;
wire dtlb_error_b;
wire daccess_prot_w_in;
wire daccess_prot_w_lat_scanin;
wire daccess_prot_w_lat_scanout;
wire daccess_prot_w;
wire priv_action_b;
wire priv_action_w_in;
wire priv_action_w_lat_scanin;
wire priv_action_w_lat_scanout;
wire priv_action_w;
wire va_watchpoint_b;
wire va_watchpoint_w_in;
wire va_watchpoint_w_lat_scanin;
wire va_watchpoint_w_lat_scanout;
wire va_watchpoint_w;
wire pa_watchpoint_b;
wire pa_watchpoint_w_in;
wire pa_watchpoint_w_lat_scanin;
wire pa_watchpoint_w_lat_scanout;
wire pa_watchpoint_w;
wire align_b;
wire align_w_in;
wire align_w_lat_scanin;
wire align_w_lat_scanout;
wire align_w;
wire dtlb_miss_b;
wire perfmon_trap_b;
wire dtlb_miss_w_in;
wire dtlb_w_lat_scanin;
wire dtlb_w_lat_scanout;
wire dtlb_miss_w;
wire ra_dtlb_miss_b;
wire ra_dtlb_miss_w_in;
wire ra_dtlb_w_lat_scanin;
wire ra_dtlb_w_lat_scanout;
wire ra_dtlb_miss_w;
wire l_real_w_lat_scanin;
wire l_real_w_lat_scanout;
wire l_real_w;
wire dae_invalid_asi_b;
wire dae_invalid_asi_w_in;
wire dae_invalid_asi_w_lat_scanin;
wire dae_invalid_asi_w_lat_scanout;
wire dae_invalid_asi_w;
wire dae_nc_page_b;
wire dae_nc_page_w_in;
wire dae_nc_page_w_lat_scanin;
wire dae_nc_page_w_lat_scanout;
wire dae_nc_page_w;
wire dae_nfo_page_b;
wire dae_nfo_page_w_in;
wire dae_nfo_page_w_lat_scanin;
wire dae_nfo_page_w_lat_scanout;
wire dae_nfo_page_w;
wire dae_priv_viol_b;
wire dae_priv_viol_w_in;
wire dae_priv_viol_w_lat_scanin;
wire dae_priv_viol_w_lat_scanout;
wire dae_priv_viol_w;
wire dae_so_page_b;
wire dae_so_page_w_in;
wire dae_so_page_w_lat_scanin;
wire dae_so_page_w_lat_scanout;
wire dae_so_page_w;
wire dtlb_error_w_in;
wire dtlb_error_w_lat_scanin;
wire dtlb_error_w_lat_scanout;
wire dtlb_error_w;
wire pil_mask_15_b;
wire precise_perf_trap_b;
wire tlz_exc_dec_b;
wire por_req_in;
wire xir_req_in;
wire ftt_req_in;
wire debug_exc_b;
wire precise_perf_trap_w_in;
wire precise_perf_trap_w_lat_scanin;
wire precise_perf_trap_w_lat_scanout;
wire precise_perf_trap_w;
wire perf_trap_w_in;
wire perf_trap_w_lat_scanin;
wire perf_trap_w_lat_scanout;
wire perf_trap_w;
wire ibp_w_in;
wire ibp_w_lat_scanin;
wire ibp_w_lat_scanout;
wire ibp_w;
wire iaw_w_in;
wire kill_exc_iaw_b_;
wire iaw_w_lat_scanin;
wire iaw_w_lat_scanout;
wire iaw_w;
wire tct_w_in;
wire tct_w_lat_scanin;
wire tct_w_lat_scanout;
wire tct_w;
wire l_spec_enable_lat_scanin;
wire l_spec_enable_lat_scanout;
wire [3:0] l_spec_enable;
wire spec_enable;
wire f_predict_b;
wire f_predict_w_in;
wire f_predict_w_lat_scanin;
wire f_predict_w_lat_scanout;
wire f_predict_w;
wire pdist_beat2_fx2_in;
wire pdist_beat2_fx2_lat_scanin;
wire pdist_beat2_fx2_lat_scanout;
wire pdist_beat2_fx2;
wire f_cecc_w_lat_scanin;
wire f_cecc_w_lat_scanout;
wire f_uecc_w_lat_scanin;
wire f_uecc_w_lat_scanout;
wire pdist_ecc_b;
wire [3:0] pdist_ecc_w_in;
wire pdist_ecc_w_lat_scanin;
wire pdist_ecc_w_lat_scanout;
wire [3:0] m_asi_ecc_b;
wire [3:0] asi_ecc_b;
wire asi_ecc_w_lat_scanin;
wire asi_ecc_w_lat_scanout;
wire [3:0] asi_ecc_w;
wire [3:0] ime_b;
wire ime_w_lat_scanin;
wire ime_w_lat_scanout;
wire [3:0] ime_w;
wire [3:0] dme_b;
wire dme_w_lat_scanin;
wire dme_w_lat_scanout;
wire [3:0] dme_w;
wire [3:0] m_dae_req_m;
wire m_dae_req_b_lat_scanin;
wire m_dae_req_b_lat_scanout;
wire [3:0] pm_dae_req_b;
wire [3:0] m_dae_req_b;
wire m_dae_req_w_lat_scanin;
wire m_dae_req_w_lat_scanout;
wire br_taken_not_annul_ds_w_in;
wire br_taken_not_annul_ds_w_lat_scanin;
wire br_taken_not_annul_ds_w_lat_scanout;
wire br_taken_not_annul_ds_w;
wire [3:0] hold_nns_exc_w;
wire [3:0] clear_nns_exc_w;
wire [3:0] flush_not_tablewalk;
wire [3:0] flush_ifu;
wire [3:0] iht_request;
wire [3:0] dht_request;
wire [3:0] hwtw_exception;
wire [3:0] nns_exc_in;
wire [3:0] nns_exc;
wire nns_exc_lat_scanin;
wire nns_exc_lat_scanout;
wire ssmode;
wire domode;
wire sync_inst_b;
wire [3:0] nns_to_pc_b;
wire [3:0] tid_dec_valid_b;
wire [3:0] nns_to_npc_b;
wire [3:0] bsee_req_in;
wire [3:0] multicycle_nns_to_npc_b;
wire bsee_req_w_in;
wire [3:0] block_store_w;
wire nns_exc_w_lat_scanin;
wire nns_exc_w_lat_scanout;
wire [3:0] pnns_to_pc_w;
wire [3:0] pnns_to_npc_w;
wire [3:0] nns_to_pc_w;
wire [3:0] nns_to_npc_w;
wire same_thread_b_m;
wire [3:0] pbsee_pending_in;
wire [3:0] bsee_pending;
wire itlb_exc_b;
wire dtlb_exc_b;
wire dec_exc_b;
wire exu_exc_b;
wire lsu_exc_b;
wire fgu_exc_b;
wire exc_w_lat_scanin;
wire exc_w_lat_scanout;
wire dec_exc_w;
wire exu_exc_w;
wire lsu_exc_w;
wire fgu_exc_w;
wire bsee_req_w;
wire trap_flush_lat_scanin;
wire trap_flush_lat_scanout;
wire [3:0] ptrap_flush;
wire preflush_exu_m;
wire preflush_lsu_m;
wire preflush_fgu_m;
wire preflush_b_lat_scanin;
wire preflush_b_lat_scanout;
wire preflush_lsu_b;
wire preflush_fgu_b;
wire flush_lsu_b;
wire flush_fgu_b;
wire [3:0] sync_flush_ifu;
wire [3:0] flush_not_disrupting;
wire [3:0] bsee_req;
wire [3:0] clear_disrupting_flush_pending_w;
wire [3:0] core_running;
wire [3:0] clear_disrupting_flush_pending;
wire tlz_exc_b;
wire [3:0] l_tid_dec_g;
wire [3:0] fpx_tid_dec_fb;
wire [3:0] fpd_tid_dec_fb;
wire [3:0] dcerr_tid_dec_g;
wire [3:0] l_l2_ecc_g;
wire [3:0] l_sbdl_ecc_g;
wire [3:0] priv_action_g;
wire [3:0] precise_perf_trap_g;
wire [3:0] fpx_ieee_exc_fb;
wire [3:0] fpd_ieee_exc_fb;
wire [3:0] fpx_unfin_exc_fb;
wire [3:0] fpd_unfin_exc_fb;
wire [3:0] idiv0_exc_fb;
wire [3:0] flush_gfb_in;
wire flush_gfb_lat_scanin;
wire flush_gfb_lat_scanout;
wire l_l2_ecc_w_lat_scanin;
wire l_l2_ecc_w_lat_scanout;
wire [3:0] l_l2_ecc_w;
wire l_sbdl_ecc_w_lat_scanin;
wire l_sbdl_ecc_w_lat_scanout;
wire [3:0] l_sbdl_ecc_w;
wire priv_action_g_w_lat_scanin;
wire priv_action_g_w_lat_scanout;
wire [3:0] priv_action_g_w;
wire precise_perf_trap_g_w_lat_scanin;
wire precise_perf_trap_g_w_lat_scanout;
wire [3:0] precise_perf_trap_g_w;
wire [3:0] ieee_exc_fb;
wire ieee_exc_fw_lat_scanin;
wire ieee_exc_fw_lat_scanout;
wire [3:0] ieee_exc_fw;
wire [3:0] unfin_fb;
wire unfin_fw_lat_scanin;
wire unfin_fw_lat_scanout;
wire [3:0] unfin_fw;
wire idiv0_exc_fw_lat_scanin;
wire idiv0_exc_fw_lat_scanout;
wire [3:0] idiv0_exc_fw;
wire [3:0] xir_flush_in;
wire [3:0] pre_xir_flush;
wire xir_flush_lat_scanin;
wire xir_flush_lat_scanout;
wire [3:0] xir_flush_m;
wire xir_flush_b_in;
wire xir_flush_b_lat_scanin;
wire xir_flush_b_lat_scanout;
wire xir_flush_b;
wire pre_desr_f_lat_scanin;
wire pre_desr_f_lat_scanout;
wire [3:0] pre_desr_f;
wire [3:0] desr_f_in;
wire [3:0] desr_f;
wire desr_f_lat_scanin;
wire desr_f_lat_scanout;
wire desr_s_lat_scanin;
wire desr_s_lat_scanout;
wire [3:0] desr_s;
wire [3:0] eer_err_m;
wire eer_err_b_in;
wire eer_err_b_lat_scanin;
wire eer_err_b_lat_scanout;
wire eer_err_b;
wire [3:0] ade_err_m;
wire ade_err_b_in;
wire ade_err_b_lat_scanin;
wire ade_err_b_lat_scanout;
wire ade_err_b;
wire [3:0] l_sbpp_in;
wire [3:0] pre_l_sbpp;
wire l_sbpp_lat_scanin;
wire l_sbpp_lat_scanout;
wire [3:0] l_sbpp_m;
wire l_sbpp_b_in;
wire l_sbpp_b_lat_scanin;
wire l_sbpp_b_lat_scanout;
wire l_sbpp_b;
wire [3:0] ma_flush_in;
wire [3:0] pre_ma_flush;
wire ma_flush_lat_scanin;
wire ma_flush_lat_scanout;
wire [3:0] ma_flush_m;
wire ma_flush_b_in;
wire ma_flush_b_lat_scanin;
wire ma_flush_b_lat_scanout;
wire ma_flush_b;
wire [3:0] cwq_flush_in;
wire [3:0] pre_cwq_flush;
wire cwq_flush_lat_scanin;
wire cwq_flush_lat_scanout;
wire [3:0] cwq_flush_m;
wire cwq_flush_b_in;
wire cwq_flush_b_lat_scanin;
wire cwq_flush_b_lat_scanout;
wire cwq_flush_b;
wire tsa_tca_ecc_error;
wire [3:0] check_mqr_dqr_;
wire [3:0] check_mqr_dqr;
wire [3:0] check_rqr_;
wire [3:0] check_rqr;
wire [3:0] pmqr_exc_in;
wire [3:0] pmqr_exc;
wire pmqr_exc_lat_wmr_scanin;
wire pmqr_exc_lat_wmr_scanout;
wire [3:0] mqr_exc_m;
wire mqr_exc_b_in;
wire mqr_exc_b_lat_scanin;
wire mqr_exc_b_lat_scanout;
wire mqr_exc_b;
wire [3:0] pdqr_exc_in;
wire [3:0] pdqr_exc;
wire pdqr_exc_lat_wmr_scanin;
wire pdqr_exc_lat_wmr_scanout;
wire [3:0] dqr_exc_m;
wire dqr_exc_b_in;
wire dqr_exc_b_lat_scanin;
wire dqr_exc_b_lat_scanout;
wire dqr_exc_b;
wire [3:0] prqr_exc_in;
wire [3:0] prqr_exc;
wire prqr_exc_lat_wmr_scanin;
wire prqr_exc_lat_wmr_scanout;
wire [3:0] rqr_exc_m;
wire rqr_exc_b_in;
wire rqr_exc_b_lat_scanin;
wire rqr_exc_b_lat_scanout;
wire rqr_exc_b;
wire ivt_lat_scanin;
wire ivt_lat_scanout;
wire [3:0] ivt_last;
wire [3:0] ivt_flush_in;
wire [3:0] pre_ivt_flush;
wire ivt_flush_lat_wmr_scanin;
wire ivt_flush_lat_wmr_scanout;
wire [3:0] ivt_flush_m;
wire ivt_flush_b_in;
wire ivt_flush_b_lat_scanin;
wire ivt_flush_b_lat_scanout;
wire ivt_flush_b;
wire [3:0] iln_exc_m;
wire iln_exc_b_in;
wire iln_exc_b_lat_scanin;
wire iln_exc_b_lat_scanout;
wire iln_exc_b;
wire [3:0] tlz_exc_m;
wire tlz_exc_b_in;
wire tlz_exc_b_lat_scanin;
wire tlz_exc_b_lat_scanout;
wire [3:0] hst_exc_m;
wire hst_exc_b_in;
wire hst_exc_b_lat_scanin;
wire hst_exc_b_lat_scanout;
wire hst_exc_b;
wire [3:0] no_hold_disrupting_flush_in;
wire [3:0] idl_exc_in;
wire [3:0] disrupting_ssc_exc;
wire no_hold_disrupting_flush_lat_scanin;
wire no_hold_disrupting_flush_lat_scanout;
wire [3:0] no_hold_disrupting_flush;
wire [3:0] disrupting_flush_pending;
wire disrupting_flush_pending_tid_dec_m;
wire disrupting_flush_pending_tid_dec_b_lat_scanin;
wire disrupting_flush_pending_tid_dec_b_lat_scanout;
wire kill_pmu_debug_exc_b_;
wire pmu_debug_exc_ge_7_lt_11_b;
wire [3:0] clear_disrupting_flush_pending_w_in;
wire cdfpw_lat_scanin;
wire cdfpw_lat_scanout;
wire disrupting_flush_w_in;
wire refetch_b;
wire disrupting_flush_w_lat_scanin;
wire disrupting_flush_w_lat_scanout;
wire disrupting_flush_w;
wire block_store_w_lat_scanin;
wire block_store_w_lat_scanout;
wire [3:0] bsee_pending_in;
wire bsee_pending_lat_scanin;
wire bsee_pending_lat_scanout;
wire bsee_req_lat_scanin;
wire bsee_req_lat_scanout;
wire bsee_req_w_lat_scanin;
wire bsee_req_w_lat_scanout;
wire bsee_flush_b_in;
wire bsee_flush_b_lat_scanin;
wire bsee_flush_b_lat_scanout;
wire core_running_lat_scanin;
wire core_running_lat_scanout;
wire core_running_last_lat_scanin;
wire core_running_last_lat_scanout;
wire [3:0] core_running_last;
wire core_running_status_lat_scanin;
wire core_running_status_lat_scanout;
wire [3:0] core_running_status;
wire [3:0] idl_exc_new;
wire [3:0] idl_exc;
wire idl_exc_lat_scanin;
wire idl_exc_lat_scanout;
wire idl_exc_b;
wire idl_req_in;
wire rqr_req_in;
wire ade_req_in;
wire eer_req_in;
wire iln_req_in;
wire dqr_req_in;
wire mqr_req_in;
wire cwq_req_in;
wire ma_req_in;
wire ivt_req_in;
wire tlz_req_in;
wire hst_req_in;
wire idl_req_lat_scanin;
wire idl_req_lat_scanout;
wire idl_req;
wire [3:0] res_exc;
wire [3:0] ever_been_running;
wire ssmode_lat_scanin;
wire ssmode_lat_scanout;
wire domode_lat_scanin;
wire domode_lat_scanout;
wire ssreq_lat_scanin;
wire ssreq_lat_scanout;
wire ssreq;
wire [3:0] ssr_exc_forces_por;
wire [3:0] ssr_exc_b;
wire [3:0] por_exc;
wire [3:0] ssc_req;
wire [3:0] ssr_req_in;
wire ssr_req_lat_scanin;
wire ssr_req_lat_scanout;
wire [3:0] ever_been_running_in;
wire ever_been_running_lat_scanin;
wire ever_been_running_lat_scanout;
wire [3:0] por_req_vec_in;
wire por_req_lat_scanin;
wire por_req_lat_scanout;
wire [3:0] xir_request_in;
wire xir_req_lat_scanin;
wire xir_req_lat_scanout;
wire [3:0] xir_request;
wire [3:0] ftt_request_in;
wire ftt_req_lat_scanin;
wire ftt_req_lat_scanout;
wire [3:0] ftt_request;
wire ade_req_lat_scanin;
wire ade_req_lat_scanout;
wire ade_req;
wire eer_req_lat_scanin;
wire eer_req_lat_scanout;
wire eer_req;
wire ivt_req_lat_scanin;
wire ivt_req_lat_scanout;
wire ivt_req;
wire ma_req_lat_scanin;
wire ma_req_lat_scanout;
wire ma_req;
wire cwq_req_lat_scanin;
wire cwq_req_lat_scanout;
wire cwq_req;
wire mqr_req_lat_scanin;
wire mqr_req_lat_scanout;
wire mqr_req;
wire dqr_req_lat_scanin;
wire dqr_req_lat_scanout;
wire dqr_req;
wire rqr_req_lat_scanin;
wire rqr_req_lat_scanout;
wire rqr_req;
wire iln_req_lat_scanin;
wire iln_req_lat_scanout;
wire iln_req;
wire hst_req_lat_scanin;
wire hst_req_lat_scanout;
wire hst_req;
wire [3:0] tlz_request_in;
wire tlz_req_lat_scanin;
wire tlz_req_lat_scanout;
wire [3:0] tlz_request;
wire [3:0] ssc_req_in;
wire ssc_req_lat_scanin;
wire ssc_req_lat_scanout;
wire [3:0] disrupting_ssc_exc_in;
wire [3:0] idl_request;
wire [3:0] disrupting_ssc_req;
wire disrupting_ssc_exc_lat_scanin;
wire disrupting_ssc_exc_lat_scanout;
wire hw_tw_enabled_lat_scanin;
wire hw_tw_enabled_lat_scanout;
wire [3:0] hw_tw_enabled;
wire [3:0] hw_tw_disabled;
wire [3:0] itm_request;
wire load_i_tag_access_in;
wire load_i_tag_access_lat_scanin;
wire load_i_tag_access_lat_scanout;
wire load_i_tag_access_pre;
wire [3:0] load_i_tag_access;
wire [3:0] ipe_request;
wire [3:0] dtm_request;
wire load_d_tag_access_in;
wire load_d_tag_access_lat_scanin;
wire load_d_tag_access_lat_scanout;
wire load_d_tag_access;
wire [3:0] vaw_request;
wire [3:0] iaw_request;
wire [3:0] paw_request;
wire [3:0] irt_request;
wire [3:0] i_real_w;
wire [3:0] load_i_tag_access_r;
wire [3:0] drt_request;
wire [3:0] pre_lsr_request;
wire [3:0] ibp_request;
wire [3:0] tct_request;
wire refetch_w;
wire [3:0] m103663_in;
wire [3:0] m103663;
wire m103663_lat_scanin;
wire m103663_lat_scanout;
wire refetch_w_in;
wire refetch_w_lat_scanin;
wire refetch_w_lat_scanout;
wire [2:0] cwp3_in;
wire [2:0] cwp3;
wire [2:0] cwp2_in;
wire [2:0] cwp2;
wire [2:0] cwp1_in;
wire [2:0] cwp1;
wire [2:0] cwp0_in;
wire [2:0] cwp0;
wire cwp_lat_wmr_scanin;
wire cwp_lat_wmr_scanout;
wire [3:0] pc_valid;
wire [3:0] pc_sel_npc_plus_4;
wire [3:0] npc_valid;
wire prevent_valid;
wire [3:0] inst_b;
wire [3:0] pc_valid_in;
wire pc_valid_lat_scanin;
wire pc_valid_lat_scanout;
wire [3:0] npc_valid_in;
wire npc_valid_lat_scanin;
wire npc_valid_lat_scanout;
wire npc_is_valid;
wire [3:0] pc_is_npc_in;
wire [3:0] pc_is_npc;
wire pc_is_npc_lat_scanin;
wire pc_is_npc_lat_scanout;
wire [4:2] pre_npc_d;
wire sel_inst_cnt_m_1;
wire [4:2] npc_plus_0;
wire [4:2] npc_plus_1;
wire [4:2] npc_plus_2;
wire [4:2] npc_plus_3;
wire debug_event_lat_scanin;
wire debug_event_lat_scanout;
wire [3:0] debug_event;
wire softstop_req_in;
wire hardstop_req_in;
wire pulse_req_in;
wire softstop_req_lat_scanin;
wire softstop_req_lat_scanout;
wire softstop_req;
wire hardstop_req_lat_scanin;
wire hardstop_req_lat_scanout;
wire hardstop_req;
wire pulse_req_lat_scanin;
wire pulse_req_lat_scanout;
wire pulse_req;
wire [1:0] instr_cmt_grp_in;
wire instr_cmt_grp_lat_scanin;
wire instr_cmt_grp_lat_scanout;
wire [1:0] instr_cmt_grp;
wire [3:0] m114419_nor3_0;
wire [3:0] m114419_nor3_1;
wire [3:0] m114419_nor3_2;
wire [3:0] m114419_nand3_0;
wire [3:0] m114419_inv_0;
wire [3:0] unhalt;
wire [3:0] halted_in;
wire [3:0] halted;
wire spares_scanin;
wire spares_scanout;
wire [15:0] unused;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

input		lsu_tlu_pmen;		// Power management

input		thread_group;		// Which thread group?

input	[2:0]	trl_shscanid;		// Select which thread to shadow


input	[3:0]	tcu_core_running;
input		tcu_ss_mode;		// Core is in single step mode
input		tcu_do_mode;		// Core is in disable overlap mode
input		tcu_ss_request;		// Enabled threads should single step

input	[3:0]	cxi_xir;		// External Interrupt Request
input 	[3:0]	cxi_ivt;		// Interrupt Vector Trap Request

input	[3:1]	dec_raw_pick_p;		// Decoded TID for instruction in P
input	[1:0]	dec_tid_m;		// TID for instruction in M
input 		dec_inst_valid_m;	// Valid instruction
input 		dec_lsu_inst_m;		// LSU instruction
input 		dec_fgu_inst_m;		// FGU instruction
input		dec_illegal_inst_m;	// Illegal instruction
input	[4:0]	dec_exc_m;		// Exceptions before the ibuffer
input		dec_done_inst_m;	// DONE
input		dec_retry_inst_m;	// RETRY
input		dec_sir_inst_m;		// Software initiated reset
input		dec_hpriv_exc_m;	// Instruction has hyperprivilege exc
input		dec_priv_exc_m;		// Instruction has privilege exc
input		dec_fpdisable_exc_m;	// Floating-point disabled exception
input		dec_br_taken_m;		// Branch in M is taken
input		dec_annul_ds_m;		// Branch in M annuls delay slot
input		dec_ds_m;		// Instruction is in a delay slot
input		dec_icache_perr_m;	// Icache data array had parity error
input		dec_cti_inst_m;		// br/tcc/call/jmpl in M
input		dec_flush_b;		// Flush instruction in B

input		exu_ibp_m;		// Instruction breakpoint
input		exu_tcc_m;		// Trap on condition codes
input		exu_tof_m;		// Tag overflow (TADccTV, TSUBccTV)
input		exu_cecc_m;		// Correctable ECC error on source
input		exu_uecc_m;		// Uncorrectable ECC error on source
input		exu_oor_va_m;		// VA is out of range
input		exu_misalign_m;		// Misaligned address for JMPL, RETURN
input		exu_spill_b;
input		exu_fill_m; 
input		exu_normal_b; 
input		exu_cleanwin_b;
input	[2:0]	exu_wstate_b;  
input	[7:0]	exu_trap_number_b;
input	[2:0]	exu_cwp0;
input	[2:0]	exu_cwp1;
input	[2:0]	exu_cwp2;
input	[2:0]	exu_cwp3;

input		lsu_lddf_align_b;
input		lsu_stdf_align_b;
input		lsu_illegal_inst_b;
input		lsu_daccess_prot_b;
input		lsu_priv_action_b;
input		lsu_va_watchpoint_b;
input		lsu_pa_watchpoint_b;
input		lsu_align_b;		// Alignment exception
input		lsu_tlb_miss_b_;	// TLB miss
input		lsu_dae_invalid_asi_b;
input		lsu_dae_nc_page_b;
input		lsu_dae_nfo_page_b;
input		lsu_dae_priv_viol_b;
input		lsu_dae_so_page; 
input		lsu_priv_action_g;	
input	[2:0]	lsu_tid_g;		// TID for exceptions from G
input	[3:0]	lsu_trap_flush;		// Flush thread and redirect to NPC
input	[3:0]	lsu_spec_enable;	// Speculation mode enabled
input 		lsu_tlb_bypass_b;	// TLB in bypass mode
input 		lsu_tlb_real_b;		// TLB doing RA->PA translation
input 		lsu_sync_inst_b;	// Instruction will get a trap flush
input		lsu_tlu_twocycle_m;	// LSU takes extra cycle on this inst
input	[3:0]	lsu_block_store_b;	// LSU reads FRF for block store
input		lsu_dcl2u_err_g;	// LSU data cache L2 uncorrectable ECC
input		lsu_dcl2nd_err_g;	// LSU data cache L2 NotData
input	[2:0]	lsu_dcerr_tid_g;	// TID for G stage errors (above)
input		lsu_sbdlc_err_g;        // STB RAW error (CE)
input		lsu_sbdlu_err_g;        // STB RAW error (UE)
input		lsu_sbapp_err_g;        // STB read for issue addr parity error
input		lsu_sbdiou_err_g;       // STB read for issue IO/ext ASI parity
input	[2:0]	lsu_stberr_tid_g;       // TID of STB error
input		lsu_dttp_err_b;         // DTLB tag parity error
input		lsu_dtdp_err_b;         // DTLB data parity error
input		lsu_dtmh_err_b;         // DTLB tag multiple hit
input		lsu_perfmon_trap_b;	// Take pic_overflow on this instruction
input		lsu_perfmon_trap_g;	// Take pic_overflow on this instruction
input	[3:0]	lsu_immu_enable;     	// For instruction VA watchpoint

input		fgu_predict_fx2;	// Exception predicted
input		fgu_pdist_beat2_fx1;	// Second part of PDIST in FX1
input		fgu_cecc_fx2;		// Correctable ECC Error on FRF
input		fgu_uecc_fx2;		// Uncorrectable ECC Error on FRF
input		fgu_fpx_ieee_trap_fw;	// IEEE 754 trap exception
input		fgu_fpd_ieee_trap_fw;	// IEEE 754 trap exception
input		fgu_fpx_unfin_fw; 	// Other FGU exception
input		fgu_fpd_unfin_fw; 	// Other divide exception
input		fgu_fpd_idiv0_trap_fw; 	// Integer divide by zero exception
input	[2:0]	fgu_fpx_trap_tid_fw;	// TID for FGU exceptions except divide
input	[2:0]	fgu_fpd_trap_tid_fw;	// TID for divide exception

input		asi_ece_exc;		// Correctable ECC error on ASI rd/wr
input		asi_eue_exc;		// Uncorrectable ECC error on ASI rd/wr
input	[2:0]	asi_ecc_tid;		// TID for ECC error
input	[3:0]	asi_irl_cleared;	// Interrupt_receive_register cleared
input	[3:0]	asi_halt;		// 
input	[63:46]	asi_decr;		// Debug event control register
input	[3:0] asi_clear_spu_trap_req;	// 

input	[3:0]	tel_tsacu_exc;		// ECC error TSA rd don/ret

input	[3:0]	mmu_hw_tw_enable;	// Hardware tablewalk enables per thread
input	[3:0]	mmu_i_unauth_access;	// Hardware tablewalk ITSB with EP=0
input	[3:0]	mmu_i_tsb_miss;		// Hardware tablewalk missed
input	[3:0]	mmu_d_tsb_miss;		// Hardware tablewalk missed
input	[3:0]	mmu_i_tte_outofrange;	// RA out of range
input	[3:0]	mmu_d_tte_outofrange;	// RA out of range
input 		mmu_asi_cecc; 		// Correctable ECC error on ASI read
input 		mmu_asi_uecc; 		// Uncorrectable ECC error on ASI read
input	[2:0]	mmu_asi_tid;		// Thread for reported error
input	[3:0]	mmu_i_eccerr;		// HW TW had MRA or L2 error on I rld
input	[3:0]	mmu_d_eccerr;		// HW TW had MRA or L2 error on D rld
input		mmu_thr0_err_type_b1;	// [1:0] ND U C - (3-0)
input		mmu_thr1_err_type_b1;	// [1:0] ND U C - (3-0)
input		mmu_thr2_err_type_b1;	// [1:0] ND U C - (3-0)
input		mmu_thr3_err_type_b1;	// [1:0] ND U C - (3-0)
input		mmu_dae_req;		// unsupported_page_size exception
input	[2:0]	mmu_dae_tid;		

input	[4:0]	spu_tlu_ma_int_req;	// SPU MA  4 err  3 trap  2:0 thread ID
input	[3:0]	spu_tlu_cwq_int_req;	// SPU CWQ trap rq  3 vld  2:0 thread ID

input	[3:0]	pmu_tlu_trap_m;		// PMU trap; kill instruction in M
input	[3:0]	pmu_tlu_debug_event;	// PMU event; soft/hard stop or pulse 

input	[1:0]	pct_iaw_exc_e;
input	[3:2]	pct_npc_0_w;
input	[3:2]	pct_npc_1_w;
input	[3:2]	pct_npc_2_w;
input	[3:2]	pct_npc_3_w;
input		pct_pc_oor_va_e;

input		flsx_flush_lsu_b;
input		flsx_flush_fgu_b;

input	[3:0]	trl_tl_eq_0;		// TL equals zero
input	[3:0]	trl_pil_mask_15;	// PIL_mask 15
input	[3:0]	trl_iln_exc;		// interrupt_level_n exception 
input	[3:0]	trl_hstick_match;	// HSTICK_CMPR matches TICK
input	[3:0]	trl_unhalt_;		// Raw *STICK_CMPR match; 
input	[3:0]	trl_tlz_exc;		// TL equals zero exception
input 	[3:0]	trl_nns_exc;		// Retry with nonsequential NPC
input 	[3:0]	trl_ssc_exc;		// Single step complete exception
input 	[3:0]	trl_invalidate_pc;	// Trap, done, retry, or HW TW complete
input 	[3:0]	trl_invalidate_npc;	// Trap, retry, or HW TW complete
input 	[3:0]	trl_pc_sel_trap_pc;	// Power management
input 	[3:0]	trl_fls_npc_en;		// Power management
input	[3:0]	trl_trap_taken;
input           trl_take_sma;           // SPU Modular Arithmetic trap taken
input           trl_take_cwq;           // SPU Control Word Queue trap taken
input		trl_take_xir;	
input		trl_take_ftt;	
input	[3:0]	trl_core_running_status;
input		trl_check_rqr;		

input 	[3:0]	tlu_ceter_de;
input 	[3:0]	tlu_ceter_dhcce;

input 	[3:0]	tsd_hpstate_ibe;
input 	[3:0]	tsd_hpstate_hpriv;
input 	[3:0]	tsd_hpstate_red;
input 	[3:0]	tsd_pstate_tct;
input 	[3:0]	tsd_pstate_priv;
input 	[3:0]	tsd_pstate_ie;
input 	[3:0]	tsd_pstate_am;
input	[3:0] tsd_itlb_bypass;
input 		tsd_mrqr_exc_;		// Mondo or Res Err Queue Register exc
input 		tsd_dqr_exc_;		// Device  Queue Register exception

input 	[3:0]	asi_check_qr_exc;	// Check for Interrupt Queue Register
					// head vs. tail mismatch

input	[3:0]	dfd_fls_desr_f;
input	[3:0]	dfd_fls_desr_s;
input	[3:0]	ras_precise_error;
input	[3:0]	ras_disrupting_error;
input	[3:0]	ras_deferred_error;


output		scan_out;

output		wmr_scan_out;		// Warm reset (non)scan

output		fls_spc_hardstop_request;	
output		fls_spc_softstop_request;	
output		fls_spc_trigger_pulse;	
output	[1:0]	tlu_dbg_instr_cmt_grp;	

output	[3:0]	tlu_flush_ifu;		// Flush specified thread

output		tlu_flush_exu_b;	// EXU to flush instr in B stage

output 		tlu_flush_lsu_b;	// This covers both thread groups

output 		tlu_flush_fgu_b;	// This covers both thread groups

output		tlu_flush_pmu_b;	// PMU to flush instr in B stage
output		tlu_flush_pmu_w;	// PMU to flush instr in W stage

output	[3:0]	tlu_load_i_tag_access_p;
output	[3:0]	tlu_load_i_tag_access_n;
output	[3:0]	tlu_load_d_tag_access;
output	[3:0]	tlu_load_d_tag_access_r;

output 		fls_flush_lsu_b;	// LSU to flush instr in B stage

output		fls_flush_fgu_b;	// FGU to flush instr in B stage

output		fls_pc_is_npc;		// PC reg actually holds NPC, not PC

output 	[1:0]	fls_tid_d;
output 	[3:0]	fls_tid_dec_b;
output 	[3:0]	fls_tid_dec_w;
output 	[3:0]	fls_pc_sel_npc;		// Sequential flow
output 	[3:0]	fls_pc_sel_npc_plus_4;	// Branch taken or(not taken with annul)
output 	[3:0]	fls_npc_sel_npc_plus_4;	// Sequential flow
output 	[3:0]	fls_npc_sel_npc_plus_8;	// Sequential flow
output 	[3:0]	fls_npc_sel_target;	// Branch taken
output 		fls_npc_b_sel_npc;	// NPC for inst at B is invalid
output		fls_pstate_am_d_;	// For instruction watchpoint
output		fls_pstate_am_b_;	// For dsfar
output		fls_pstate_am_w_;	// For itlb_tag_access
output		fls_lsu_inst_w;		// For npc_w
output		fls_dfd_lsu_inst_b;	// For DSFAR

output	[2:0]	fls_wstate0;		// WSTATE value for spill, fill traps
output	[2:0]	fls_wstate1;		// WSTATE value for spill, fill traps
output	[2:0]	fls_wstate2;		// WSTATE value for spill, fill traps
output	[2:0]	fls_wstate3;		// WSTATE value for spill, fill traps

output	[7:0]	fls_tcc_number_0;	// Trap number for thread 0
output	[7:0]	fls_tcc_number_1;	// Trap number for thread 1
output	[7:0]	fls_tcc_number_2;	// Trap number for thread 2
output	[7:0]	fls_tcc_number_3;	// Trap number for thread 3

output	[3:0]	fls_tid_dec_w_in;	// Decoded TID for nonstranded requests

output	[3:0]	fls_por_request;	// POR trap request
output	[3:0]	fls_xir_request;	// XIR trap request
output	[3:0]	fls_ivt_request;	// Interrupt Vector Trap request
output	[3:0]	fls_sir_request;	// SIR trap request
output	[3:0]	fls_itm_request;	// ITLB miss trap request
output	[3:0]	fls_iln_request;	// Interrupt level n request
output	[3:0]	fls_hst_request;	// hstick_match request
output	[3:0]	fls_tlz_request;	// TL equals zero request
output	[3:0]	fls_sma_request;	// SPU Modular Arithmetic request
output	[3:0]	fls_cwq_request;	// SPU Control Word Queue request
output	[3:0]	fls_ade_request;	// Software recoverable error trap req
					// 	(Disrupting error on store,HWTW)
output	[3:0]	fls_iae_request;	// Instruction_access_error trap req
output	[3:0]	fls_ipe_request;	// Internal processor error trap request
					// 	(Error on array access, etc.)
output		fls_ipv_request;	// IAE_privilege_violation trap request
output		fls_inp_request;	// IAE_nfo_page trap request
output		fls_iar_request;	// instruction_address_range trap equest
output		fls_irr_request;	// instruction_real_range trap equest
output		fls_mar_request;	// mem_address_range trap request
output		fls_mrr_request;	// mem_real_range trap request
output		fls_pro_request;	// Privileged opcode trap request
output		fls_ill_request;	// Illegal instruction trap request
output		fls_don_request;	// Done instruction
output		fls_ret_request;	// Retry instruction
output		fls_fpd_request;	// FP disabled trap request
output		fls_snn_request;	// Spill normal trap request
output		fls_sno_request;	// Spill other trap request
output		fls_fnn_request;	// Fill normal trap request
output		fls_fno_request;	// Fill other trap request
output		fls_clw_request;	// Clean window trap request
output	[3:0]	fls_dtm_request;	// DTLB miss trap request
output		fls_ldf_request;	// lddf alignment trap request
output		fls_stf_request;	// stdf alignment trap request
output 		fls_dap_request;	// data_access_protection trap request
output		fls_vaw_request;	// VA watchpoint trap request
output		fls_iaw_request;	// Instruction VA watchpoint trap req
output		fls_paw_request;	// PA watchpoint trap request
output		fls_maa_request;	// Memory address alignment trap request
output		fls_fpe_request;	// FP predicted exception
output	[3:0]	fls_fei_request;	// FP IEEE 754 trap request
output	[3:0]	fls_fof_request;	// FP other trap request (unfinished)
output	[3:0]	fls_pra_request;	// Privileged action trap request
output		fls_dia_request;	// DAE_invalid_asi trap request
output	[3:0]	fls_ups_request;	// unsupported_page_size trap request
output		fls_dpv_request;	// DAE_privilege_violation trap request
output		fls_dnc_request;	// DAE_nc_page trap request
output		fls_dnf_request;	// DAE_nfo_page trap request
output		fls_dso_request;	// DAE_so_page trap request
output		fls_tof_request;	// Tag overflow trap request
output	[3:0]	fls_dbz_request;	// Divide by zero trap request
output		fls_tcc_request;	// Trap instruction trap request
output	[3:0]	fls_dae_request;	// LSU uncorrectable ECC on load miss
output	[3:0]	fls_lsr_request;	// LSU sync trap (postsync)
output		fls_irt_request;	// Instruction real translation miss
output		fls_drt_request;	// Data real translation miss
output	[3:0]	fls_pmu_request;	// pic_overflow
output 	[3:0]	fls_mqr_request;	// CPU mondo trap request
output 	[3:0]	fls_dqr_request;	// Device mondo trap request
output 	[3:0]	fls_rqr_request;	// Resumable error trap request
output 	[3:0]	fls_idl_request;	// CMP idle request
output 	[3:0]	fls_res_request;	// CMP resume request
output	[3:0]	fls_ssr_request;	// Single step request
output	[3:0]	fls_ssc_request;	// Single step completion
output 	[3:0]	fls_nns_request;	// NPC nonsequential redirect request
output 	[3:0]	fls_ime_request;	// Instruction_access_MMU_error request
output 	[3:0]	fls_dme_request;	// Data_access_MMU_error request
output 	[3:0]	fls_eer_request;	// Hardware corrected error trap request
output 		fls_icp_request;	// Icache parity error (invalidate)
output 	[3:0]	fls_ftt_request;	// Fatal_thread_trap request
output 		fls_ibp_request;	// Instruction breakpoint request
output 		fls_tct_request;	// Trap on control transfer request
output 		fls_ref_request;	// Refetch inst 

output 		fls_ipe_dme_request;	// Update DSFSR / DSFAR

output	[3:0]	fls_pc_valid;		// For single step redirection control

output	[3:0]	fls_load_dsfar;
output		fls_irf_cecc_b;
output		fls_irf_uecc_b;
output		fls_kill_irf_ecc_w;

output	[2:0]	fls_cwp0;
output	[2:0]	fls_cwp1;
output	[2:0]	fls_cwp2;
output	[2:0]	fls_cwp3;

output	[3:0]	fls_core_running;
output		fls_ss_request;

output	[3:0]	fls_pct_pc_en;		// Power management for pct PC flops
output	[3:0]	fls_pct_npc_en;		// Power management for pct NPC flops
output	[3:0]	fls_trl_l1en;		// Power management for trl

output	[4:2]	fls_npc_if_cnt_eq_1_d;
output	[4:2]	fls_npc_if_cnt_eq_2_d;
output	[4:2]	fls_npc_if_cnt_eq_3_d;

output	[3:0]	fls_flush;		// Copy of tlu_flush_ifu
output		fls_disrupting_flush_w;	
output		fls_f_cecc_w;		// For tlu_ras_ctl
output		fls_f_uecc_w;		// For tlu_ras_ctl

output		fls_ss_update_pc_w;

output 	[3:0]	tlu_iht_request;	// ITLB hardware tablewalk request
output 	[3:0]	tlu_dht_request;	// DTLB hardware tablewalk request

output		tlu_itlb_bypass_e;

output	[1:0]	tlu_tag_access_tid_b;	// Tag access power management
output		tlu_i_tag_access_b;	// Tag access power management
output		tlu_d_tag_access_b;	// Tag access power management

output	[3:0]	tlu_retry_state;	// DEC should not wait for delay slot

output	[3:0]	tlu_halted;		


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;


//////////////////////////////////////////////////////////////////////////////
// Power management

// l_tlu_twocycle_b is the M stage of the second beat
// fgu_pdist_beat2_fx1 is the M stage of the second beat
assign beat_two_b_in =
       (l_tlu_twocycle_b | (fgu_pdist_beat2_fx1 & fgu_inst_b)) & ~dec_flush_b;

tlu_fls_ctl_msff_ctl_macro__width_2 beat_two_b_lat  (
	.scan_in(beat_two_b_lat_scanin),
	.scan_out(beat_two_b_lat_scanout),
	.din	({beat_two_b_in	       ,
		  beat_two_b	       }),
	.dout	({pbeat_two_b	       ,
		  beat_two_w	       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign beat_two_b =
       pbeat_two_b & ~exc_for_w;

// dec_inst_valid_m is the M stage of normal instructions
// pre_inst_valid_b is the B stage of normal instructions and M of twocycle ops
// beat_two_b is the B stage of twocycle ops
assign l1en_b2w_in =
       dec_inst_valid_m | pre_inst_valid_b | ~lsu_tlu_pmen |
       beat_two_b;

assign fls_trl_l1en[3:0] =
       ({4 {l1en_b2w}} & tid_dec_w[3:0]) | flush_gfb[3:0] | 
       m_dae_req_w[3:0] | por_req[3:0] | res_req[3:0] | 
       trap_flush[3:0] | pdist_ecc_w[3:0] | ssr_req[3:0] | 
       multicycle_nns_to_npc_w[3:0];

tlu_fls_ctl_msff_ctl_macro__width_1 l1en_b2w_lat  (
	.scan_in(l1en_b2w_lat_scanin),
	.scan_out(l1en_b2w_lat_scanout),
	.din	(l1en_b2w_in		),
	.dout	(l1en_b2w		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_l1clkhdr_ctl_macro b2w_clken (
        .l2clk  (l2clk 			),
        .l1en   (l1en_b2w		),
        .l1clk  (l1clk_pm1		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


////////////////////////////////////////////////////////////////////////////////
// Clock header

tlu_fls_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk 			),
        .l1en   (1'b1			),
        .l1clk  (l1clk			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


////////////////////////////////////////////////////////////////////////////////
// Flop signals that are out of pipe

tlu_fls_ctl_msff_ctl_macro__width_4 hpstate_hpriv_lat  (
	.scan_in(hpstate_hpriv_lat_scanin),
	.scan_out(hpstate_hpriv_lat_scanout),
	.din	(tsd_hpstate_hpriv	[3:0]	),
	.dout	(hpstate_hpriv		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign hpriv_bar_or_ie_in[3:0] =
	~tsd_hpstate_hpriv[3:0] | tsd_pstate_ie[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 hpriv_bar_or_ie_lat  (
	.scan_in(hpriv_bar_or_ie_lat_scanin),
	.scan_out(hpriv_bar_or_ie_lat_scanout),
	.din	(hpriv_bar_or_ie_in	[3:0]	),
	.dout	(phpriv_bar_or_ie	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign hpriv_bar_or_ie_m[3:0] =
       phpriv_bar_or_ie[3:0] & tid_dec_m[3:0] & {4 {dec_inst_valid_m}};

assign hpriv_bar_and_ie_in[3:0] =
	~tsd_hpstate_hpriv[3:0] & tsd_pstate_ie[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 hpriv_bar_and_ie_lat  (
	.scan_in(hpriv_bar_and_ie_lat_scanin),
	.scan_out(hpriv_bar_and_ie_lat_scanout),
	.din	(hpriv_bar_and_ie_in	[3:0]	),
	.dout	(hpriv_bar_and_ie	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Pipe signals from P to D 

assign tid_p[1:0] =
       {dec_raw_pick_p[3] | dec_raw_pick_p[2],
	dec_raw_pick_p[3] | dec_raw_pick_p[1]};

tlu_fls_ctl_msff_ctl_macro__width_2 tid_dec_d_lat  (
	.scan_in(tid_dec_d_lat_scanin),
	.scan_out(tid_dec_d_lat_scanout),
	.din	(tid_p		[1:0]	),
	.dout	(tid_d		[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid_dec_d[3:0] = 
	{ tid_d[1] &  tid_d[0],
	  tid_d[1] & ~tid_d[0],
	 ~tid_d[1] &  tid_d[0],
	 ~tid_d[1] & ~tid_d[0]};

assign fls_tid_d[1:0] =
       tid_d[1:0];

assign fls_pstate_am_d_ =
       | (~tsd_pstate_am[3:0] & tid_dec_d[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 itlb_bypass_lat  (
	.scan_in(itlb_bypass_lat_scanin),
	.scan_out(itlb_bypass_lat_scanout),
	.din	(tsd_itlb_bypass[3:0]	),
	.dout	(itlb_bypass	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_bypass_d =
       | (itlb_bypass[3:0] & tid_dec_d[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_bypass_e_lat  (
	.scan_in(itlb_bypass_e_lat_scanin),
	.scan_out(itlb_bypass_e_lat_scanout),
	.din	(itlb_bypass_d		),
	.dout	(itlb_bypass_e		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_itlb_bypass_e =
       itlb_bypass_e;


////////////////////////////////////////////////////////////////////////////////
// Pipe signals from M to B 

assign l_tlu_twocycle_b_in =
       lsu_tlu_twocycle_m & dec_inst_valid_m & dec_lsu_inst_m;

tlu_fls_ctl_msff_ctl_macro__width_1 l_tlu_twocycle_b_lat  (
	.scan_in(l_tlu_twocycle_b_lat_scanin),
	.scan_out(l_tlu_twocycle_b_lat_scanout),
	.din	(l_tlu_twocycle_b_in		),
	.dout	(l_tlu_twocycle_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid_m[1:0] =
       (dec_tid_m[1:0] & {2 {~twocycle_inst_b}}) |
       (tid_b    [1:0] & {2 { twocycle_inst_b}}) ;

tlu_fls_ctl_msff_ctl_macro__width_2 tid_b_lat  (
	.scan_in(tid_b_lat_scanin),
	.scan_out(tid_b_lat_scanout),
	.din	(tid_m		[1:0]	),
	.dout	(tid_b		[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid_dec_m[3:0] = 
	{ tid_m[1] &  tid_m[0],
	  tid_m[1] & ~tid_m[0],
	 ~tid_m[1] &  tid_m[0],
	 ~tid_m[1] & ~tid_m[0]};

tlu_fls_ctl_msff_ctl_macro__width_4 fast_tid_dec_b_lat  (
	.scan_in(fast_tid_dec_b_lat_scanin),
	.scan_out(fast_tid_dec_b_lat_scanout),
	.din	(tid_dec_m	[3:0]	),
	.dout	(fast_tid_dec_b	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_tid_dec_b[3:0] = 
       fast_tid_dec_b[3:0];

assign inst_valid_m =
       dec_inst_valid_m;

tlu_fls_ctl_msff_ctl_macro__width_1 pre_inst_valid_b_lat  (
	.scan_in(pre_inst_valid_b_lat_scanin),
	.scan_out(pre_inst_valid_b_lat_scanout),
	.din	(inst_valid_m		),
	.dout	(pre_inst_valid_b	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid_dec_b[3:0] = 
	{ tid_b[1] &  tid_b[0],
	  tid_b[1] & ~tid_b[0],
	 ~tid_b[1] &  tid_b[0],
	 ~tid_b[1] & ~tid_b[0]};

tlu_fls_ctl_msff_ctl_macro__width_4 tl_eq_0_lat  (
	.scan_in(tl_eq_0_lat_scanin),
	.scan_out(tl_eq_0_lat_scanout),
	.din	(trl_tl_eq_0	[3:0]	),
	.dout	(tl_eq_0	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tl_eq_0_b = 
       (| (tl_eq_0[3:0] & tid_dec_b[3:0]));

assign inst_valid_b = 
       pre_inst_valid_b & ~flush_b;

// bsee_flush_b means there was an earlier block store with ECC error
// that is being injected 'just before' the next instruction for that thread
// coming down the pipe
assign flush_b = 
       (preflush_exu_b & exception_for_w) | bsee_flush_b;

assign lsu_inst_m =
       (dec_lsu_inst_m & ~twocycle_inst_b & dec_inst_valid_m) |
       (    lsu_inst_b &  twocycle_inst_b) ;

tlu_fls_ctl_msff_ctl_macro__width_1 lsu_inst_b_lat  (
	.scan_in(lsu_inst_b_lat_scanin),
	.scan_out(lsu_inst_b_lat_scanout),
	.din	(lsu_inst_m		),
	.dout	(lsu_inst_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_dfd_lsu_inst_b =
       lsu_inst_b & pre_inst_valid_b;

assign fgu_inst_m =
       dec_fgu_inst_m & dec_inst_valid_m;

tlu_fls_ctl_msff_ctl_macro__width_1 fgu_inst_b_lat  (
	.scan_in(fgu_inst_b_lat_scanin),
	.scan_out(fgu_inst_b_lat_scanout),
	.din	(fgu_inst_m		),
	.dout	(fgu_inst_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign illegal_inst_b_in =
       dec_illegal_inst_m & ~dec_icache_perr_m;

tlu_fls_ctl_msff_ctl_macro__width_1 illegal_inst_b_lat  (
	.scan_in(illegal_inst_b_lat_scanin),
	.scan_out(illegal_inst_b_lat_scanout),
	.din	(illegal_inst_b_in	),
	.dout	(pillegal_inst_b	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign illegal_inst_b =
       pillegal_inst_b | (lsu_illegal_inst_b & lsu_inst_b) |
       illegal_sir_b | illegal_done_inst_b | illegal_retry_inst_b;

assign itlb_miss_m =
       dec_exc_m[4:0] == 5'b00001;

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_miss_b_lat  (
	.scan_in(itlb_miss_b_lat_scanin),
	.scan_out(itlb_miss_b_lat_scanout),
	.din	(itlb_miss_m		),
	.dout	(itlb_miss_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ra_itlb_miss_m =
       dec_exc_m[4:0] == 5'b00100;

tlu_fls_ctl_msff_ctl_macro__width_1 ra_itlb_miss_b_lat  (
	.scan_in(ra_itlb_miss_b_lat_scanin),
	.scan_out(ra_itlb_miss_b_lat_scanout),
	.din	(ra_itlb_miss_m		),
	.dout	(ra_itlb_miss_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_priv_exc_m =
       dec_exc_m[4:0] == 5'b00010;

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_priv_exc_b_lat  (
	.scan_in(itlb_priv_exc_b_lat_scanin),
	.scan_out(itlb_priv_exc_b_lat_scanout),
	.din	(itlb_priv_exc_m	),
	.dout	(itlb_priv_exc_b	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_nfo_exc_m =
       dec_exc_m[4:0] == 5'b10001;

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_nfo_exc_b_lat  (
	.scan_in(itlb_nfo_exc_b_lat_scanin),
	.scan_out(itlb_nfo_exc_b_lat_scanout),
	.din	(itlb_nfo_exc_m		),
	.dout	(itlb_nfo_exc_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign i_l2_unde_m = 
       (dec_exc_m[4:0] == 5'b01111) | 
       (dec_exc_m[4:0] == 5'b10000) |
       (dec_exc_m[4:0] == 5'b10111) | 
       (dec_exc_m[4:0] == 5'b11000) ;

tlu_fls_ctl_msff_ctl_macro__width_1 i_l2_unde_b_lat  (
	.scan_in(i_l2_unde_b_lat_scanin),
	.scan_out(i_l2_unde_b_lat_scanout),
	.din	(i_l2_unde_m		),
	.dout	(i_l2_unde_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign i_oor_va_m =
       dec_exc_m[4:0] == 5'b00011;

tlu_fls_ctl_msff_ctl_macro__width_1 i_oor_va_b_lat  (
	.scan_in(i_oor_va_b_lat_scanin),
	.scan_out(i_oor_va_b_lat_scanout),
	.din	(i_oor_va_m		),
	.dout	(i_oor_va_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign i_ra_oor_va_m =
       dec_exc_m[4:0] == 5'b10011;

tlu_fls_ctl_msff_ctl_macro__width_1 i_ra_oor_va_b_lat  (
	.scan_in(i_ra_oor_va_b_lat_scanin),
	.scan_out(i_ra_oor_va_b_lat_scanout),
	.din	(i_ra_oor_va_m		),
	.dout	(i_ra_oor_va_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_err_m =
       (dec_exc_m[4:0] == 5'b00111) | 
       (dec_exc_m[4:0] == 5'b11111) | 
       (dec_exc_m[4:0] == 5'b01001) ;

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_err_b_lat  (
	.scan_in(itlb_err_b_lat_scanin),
	.scan_out(itlb_err_b_lat_scanout),
	.din	(itlb_err_m		),
	.dout	(itlb_err_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pre_icache_exc_m = 
       itlb_miss_m | ra_itlb_miss_m | itlb_priv_exc_m | itlb_nfo_exc_m |
       i_oor_va_m | i_ra_oor_va_m | itlb_err_m;

assign ic_err_m = 
       (dec_exc_m[4:0] == 5'b01010) | // ICVP
       (dec_exc_m[4:0] == 5'b01011) | // ICTP
       (dec_exc_m[4:0] == 5'b01100) | // ICTM
       (dec_icache_perr_m & ~pre_icache_exc_m) ; // ICDP

tlu_fls_ctl_msff_ctl_macro__width_1 ic_err_b_lat  (
	.scan_in(ic_err_b_lat_scanin),
	.scan_out(ic_err_b_lat_scanout),
	.din	(ic_err_m		),
	.dout	(ic_err_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign done_inst_b_in =
       dec_done_inst_m & ~dec_illegal_inst_m &
       ~dec_icache_perr_m;

tlu_fls_ctl_msff_ctl_macro__width_1 done_inst_b_lat  (
	.scan_in(done_inst_b_lat_scanin),
	.scan_out(done_inst_b_lat_scanout),
	.din	(done_inst_b_in		),
	.dout	(pdone_inst_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign done_inst_b =
       pdone_inst_b & ~tl_eq_0_b & ~priv_exc_b;

assign illegal_done_inst_b = 
       pdone_inst_b &  tl_eq_0_b & ~priv_exc_b;

assign retry_inst_b_in =
       dec_retry_inst_m & ~dec_illegal_inst_m &
       ~dec_icache_perr_m;

tlu_fls_ctl_msff_ctl_macro__width_1 retry_inst_b_lat  (
	.scan_in(retry_inst_b_lat_scanin),
	.scan_out(retry_inst_b_lat_scanout),
	.din	(retry_inst_b_in	),
	.dout	(pretry_inst_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign retry_inst_b =
       pretry_inst_b & ~tl_eq_0_b & ~priv_exc_b;

assign illegal_retry_inst_b = 
       pretry_inst_b &  tl_eq_0_b & ~priv_exc_b;

assign sir_b_in = 
       dec_sir_inst_m & ~dec_illegal_inst_m & ~dec_icache_perr_m;

tlu_fls_ctl_msff_ctl_macro__width_1 sir_b_lat  (
	.scan_in(sir_b_lat_scanin),
	.scan_out(sir_b_lat_scanout),
	.din	(sir_b_in		),
	.dout	(psir_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign in_hpriv_b = 
       ( | (tid_dec_b[3:0] & hpstate_hpriv[3:0]));

assign sir_b =
       psir_b & in_hpriv_b;

assign illegal_sir_b =
       psir_b & ~in_hpriv_b;

assign hpriv_exc_b_in =
       dec_hpriv_exc_m & ~dec_illegal_inst_m & ~dec_icache_perr_m;

tlu_fls_ctl_msff_ctl_macro__width_1 hpriv_exc_b_lat  (
	.scan_in(hpriv_exc_b_lat_scanin),
	.scan_out(hpriv_exc_b_lat_scanout),
	.din	(hpriv_exc_b_in		),
	.dout	(hpriv_exc_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// DEC generates privileged exceptions only on legal instructions so TLU
// can prioritize it correctly
assign priv_exc_b_in =
       dec_priv_exc_m & ~dec_icache_perr_m;

tlu_fls_ctl_msff_ctl_macro__width_1 priv_exc_b_lat  (
	.scan_in(priv_exc_b_lat_scanin),
	.scan_out(priv_exc_b_lat_scanout),
	.din	(priv_exc_b_in		),
	.dout	(priv_exc_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fpdisable_exc_b_in =
       dec_fpdisable_exc_m & ~dec_illegal_inst_m & ~dec_icache_perr_m;

tlu_fls_ctl_msff_ctl_macro__width_1 fpdisable_exc_b_lat  (
	.scan_in(fpdisable_exc_b_lat_scanin),
	.scan_out(fpdisable_exc_b_lat_scanout),
	.din	(fpdisable_exc_b_in	),
	.dout	(fpdisable_exc_b	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign e_cecc_b_in =
       exu_cecc_m & (dec_inst_valid_m | twocycle_inst_b);
assign e_uecc_b_in =
       exu_uecc_m & (dec_inst_valid_m | twocycle_inst_b);
tlu_fls_ctl_msff_ctl_macro__width_2 ecc_b_lat  (
	.scan_in(ecc_b_lat_scanin),
	.scan_out(ecc_b_lat_scanout),
	.din	({e_cecc_b_in	       ,
		  e_uecc_b_in	       }),
	.dout	({e_cecc_b	       ,
		  e_uecc_b	       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_irf_cecc_b =
       e_cecc_b;
assign fls_irf_uecc_b =
       e_uecc_b;

assign misalign_b_in =
       exu_misalign_m & ~exu_cecc_m & ~exu_uecc_m & dec_inst_valid_m;

tlu_fls_ctl_msff_ctl_macro__width_1 misalign_b_lat  (
	.scan_in(misalign_b_lat_scanin),
	.scan_out(misalign_b_lat_scanout),
	.din	(misalign_b_in		),
	.dout	(misalign_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 e_oor_va_b_lat  (
	.scan_in(e_oor_va_b_lat_scanin),
	.scan_out(e_oor_va_b_lat_scanout),
	.din	(exu_oor_va_m		),
	.dout	(pe_oor_va_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign e_oor_va_b =
       pe_oor_va_b & ~e_cecc_b & ~e_uecc_b & pre_inst_valid_b & ~pstate_am_b;

assign e_tcc_b_in =
       exu_tcc_m & ~exu_cecc_m & ~exu_uecc_m & dec_inst_valid_m;

tlu_fls_ctl_msff_ctl_macro__width_1 e_tcc_b_lat  (
	.scan_in(e_tcc_b_lat_scanin),
	.scan_out(e_tcc_b_lat_scanout),
	.din	(e_tcc_b_in		),
	.dout	(e_tcc_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign e_tof_b_in =
       exu_tof_m & ~exu_cecc_m & ~exu_uecc_m & dec_inst_valid_m;

tlu_fls_ctl_msff_ctl_macro__width_1 e_tof_b_lat  (
	.scan_in(e_tof_b_lat_scanin),
	.scan_out(e_tof_b_lat_scanout),
	.din	(e_tof_b_in		),
	.dout	(e_tof_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign e_fill_b_in =
       exu_fill_m & ~exu_cecc_m & ~exu_uecc_m & dec_inst_valid_m;

tlu_fls_ctl_msff_ctl_macro__width_1 e_fill_b_lat  (
	.scan_in(e_fill_b_lat_scanin),
	.scan_out(e_fill_b_lat_scanout),
	.din	(e_fill_b_in		),
	.dout	(e_fill_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// Possible exceptions on branches:
// - decode exceptions
// - VA out of range on branch
// - Misaligned address (for jmpl and return)
// - Fill exceptions (for return)
// - disrupting exceptions
// - PMU and debug exceptions
assign br_exc_b =
       pdec_exc_b | br_oor_va_b | br_ra_oor_va_b | misalign_b |
       e_fill_b | 
       e_cecc_b | e_uecc_b |
       (| perf_trap_b[3:0]) | ibp_b | iaw_b | tct_b | target_oor_b |
       disrupting_flush_pending_tid_dec_b;

assign br_taken_b_in =
       dec_br_taken_m & dec_inst_valid_m & ~dec_illegal_inst_m;

tlu_fls_ctl_msff_ctl_macro__width_1 br_taken_b_lat  (
	.scan_in(br_taken_b_lat_scanin),
	.scan_out(br_taken_b_lat_scanout),
	.din	(br_taken_b_in		),
	.dout	(pre_br_taken_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign br_taken_b =
       pre_br_taken_b & ~br_exc_b;

tlu_fls_ctl_msff_ctl_macro__width_1 annul_ds_m_lat  (
	.scan_in(annul_ds_m_lat_scanin),
	.scan_out(annul_ds_m_lat_scanout),
	.din	(dec_annul_ds_m		),
	.dout	(pre_annul_ds_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign annul_ds_b =
       pre_annul_ds_b & ~br_exc_b;

tlu_fls_ctl_msff_ctl_macro__width_1 ds_b_lat  (
	.scan_in(ds_b_lat_scanin),
	.scan_out(ds_b_lat_scanout),
	.din	(dec_ds_m		),
	.dout	(pre_ds_b		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ds_b =
       pre_ds_b & ~ibp_b & ~iaw_b & ~tct_b & ~target_oor_b & 
       ~(| {perf_trap_b[3:0],
	    disrupting_flush_pending_tid_dec_b});

// This takes care of M stage flushes
// Take PMU trap if IE == 1 and PIL != 15
assign perf_trap_m[3:0] = 
       pmu_tlu_trap_m[3:0] & tid_dec_m[3:0] & pil_mask_15[3:0] &
       {4 {dec_inst_valid_m}};

tlu_fls_ctl_msff_ctl_macro__width_4 perf_trap_b_lat  (
	.scan_in(perf_trap_b_lat_scanin),
	.scan_out(perf_trap_b_lat_scanout),
	.din	(perf_trap_m	[3:0]	),
	.dout	(perf_trap_b	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 pil_mask_15_lat  (
	.scan_in(pil_mask_15_lat_scanin),
	.scan_out(pil_mask_15_lat_scanout),
	.din	(trl_pil_mask_15	[3:0]	),
	.dout	(pil_mask_15		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Instruction breakpoint
assign ibe_m =
       | (tsd_hpstate_ibe[3:0] & tid_dec_m[3:0]);

assign ibp_b_in =
       exu_ibp_m & ibe_m & dec_inst_valid_m & ~itlb_err_m & 
       ~i_l2_unde_m & ~ic_err_m;

tlu_fls_ctl_msff_ctl_macro__width_1 ibp_b_lat  (
	.scan_in(ibp_b_lat_scanin),
	.scan_out(ibp_b_lat_scanout),
	.din	(ibp_b_in			),
	.dout	(ibp_b				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_va_pa_enabled = 
       | (tid_dec_m[3:0] & ~hpstate_hpriv[3:0] & 
	  ~tsd_hpstate_red[3:0] & immu_enable[3:0]);

assign iaw_exc_m_in = 
       (& pct_iaw_exc_e[1:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 iaw_exc_m_lat  (
	.scan_in(iaw_exc_m_lat_scanin),
	.scan_out(iaw_exc_m_lat_scanout),
	.din	(iaw_exc_m_in			),
	.dout	(iaw_exc_m			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign iaw_b_in =
       iaw_exc_m & itlb_va_pa_enabled & dec_inst_valid_m;

tlu_fls_ctl_msff_ctl_macro__width_1 iaw_b_lat  (
	.scan_in(iaw_b_lat_scanin),
	.scan_out(iaw_b_lat_scanout),
	.din	(iaw_b_in			),
	.dout	(iaw_b				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pstate_tct_m = 
       | (tid_dec_m[3:0] & tsd_pstate_tct[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 pstate_tct_b_lat  (
	.scan_in(pstate_tct_b_lat_scanin),
	.scan_out(pstate_tct_b_lat_scanout),
	.din	(pstate_tct_m			),
	.dout	(pstate_tct_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tct_b_in_b =
       ~(((dec_br_taken_m & ~exu_cecc_m & ~exu_uecc_m) | 
	 dec_done_inst_m | dec_retry_inst_m) & 
        dec_inst_valid_m & ~dec_illegal_inst_m & pstate_tct_m);

assign tct_b_in =
       ~(tct_b_in_b | exu_fill_m);

tlu_fls_ctl_msff_ctl_macro__width_1 tct_b_lat  (
	.scan_in(tct_b_lat_scanin),
	.scan_out(tct_b_lat_scanout),
	.din	(tct_b_in			),
	.dout	(ptct_b				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tct_b =
       ptct_b | (e_tcc_b & pstate_tct_b);


assign cti_b_in =
       dec_cti_inst_m | dec_done_inst_m | dec_retry_inst_m;

tlu_fls_ctl_msff_ctl_macro__width_1 cti_b_lat  (
	.scan_in(cti_b_lat_scanin),
	.scan_out(cti_b_lat_scanout),
	.din	(cti_b_in			),
	.dout	(cti_b				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Pipe signals from B to W

// lsu_tlu_twocycle_m means that the first beat is in M
// FGU pdist is handled differently
assign twocycle_inst_b =
       l_tlu_twocycle_b & lsu_inst_b & inst_valid_b & ~disrupting_flush_b &
       ~e_cecc_b & ~e_uecc_b & ~pmu_debug_exc_b & ~dec_flush_b ;

tlu_fls_ctl_msff_ctl_macro__width_1 twocycle_inst_w_lat  (
	.scan_in(twocycle_inst_w_lat_scanin),
	.scan_out(twocycle_inst_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(twocycle_inst_b	),
	.dout	(ptwocycle_inst_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign twocycle_inst_w =
       ptwocycle_inst_w & ~exc_for_w;

tlu_fls_ctl_msff_ctl_macro__width_1 d_flush_w_lat  (
	.scan_in(d_flush_w_lat_scanin),
	.scan_out(d_flush_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dec_flush_b		),
	.dout	(d_flush_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign dec_inst_valid_b[3] = 
	 tid_b[1] &  tid_b[0] & inst_valid_b;
assign dec_inst_valid_b[2] = 		      
	 tid_b[1] & ~tid_b[0] & inst_valid_b;
assign dec_inst_valid_b[1] = 		      
	~tid_b[1] &  tid_b[0] & inst_valid_b;
assign dec_inst_valid_b[0] = 		      
	~tid_b[1] & ~tid_b[0] & inst_valid_b;

assign tid_dec_w_in[3:0] =
       dec_inst_valid_b[3:0] & {4 {~dec_flush_b}};

assign fls_tid_dec_w_in[3:0] =
	tid_dec_w_in[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 tid_dec_w_lat  (
	.scan_in(tid_dec_w_lat_scanin),
	.scan_out(tid_dec_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(tid_dec_w_in		[3:0]	),
	.dout	(tid_dec_w		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_tid_dec_w[3:0] =
       tid_dec_w[3:0];

assign pstate_am_b_in =
       | (tsd_pstate_am[3:0] & tid_dec_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 pstate_am_b_lat  (
	.scan_in(pstate_am_b_lat_scanin),
	.scan_out(pstate_am_b_lat_scanout),
	.din	(pstate_am_b_in		       	),
	.dout	(pstate_am_b		       	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_pstate_am_b_ =
	~pstate_am_b;

tlu_fls_ctl_msff_ctl_macro__width_1 pstate_am_w_lat  (
	.scan_in(pstate_am_w_lat_scanin),
	.scan_out(pstate_am_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(pstate_am_b	     		),
	.dout	(pstate_am_w		    	),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_pstate_am_w_ =
	~pstate_am_w;

assign dec_two_tid_b[3:0] = 
       { tid_b[1] &  tid_b[0],
	 tid_b[1] & ~tid_b[0],
	~tid_b[1] &  tid_b[0],
	~tid_b[1] & ~tid_b[0]} & 
       {4 {inst_valid_b | twocycle_inst_w}};

assign two_tid_dec_w_in[3:0] =
       dec_two_tid_b[3:0] & {4 {~dec_flush_b}};

tlu_fls_ctl_msff_ctl_macro__width_4 two_tid_dec_w_lat  (
	.scan_in(two_tid_dec_w_lat_scanin),
	.scan_out(two_tid_dec_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(two_tid_dec_w_in	[3:0]	),
	.dout	(two_tid_dec_w		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);


tlu_fls_ctl_msff_ctl_macro__width_1 inst_valid_w_lat  (
	.scan_in(inst_valid_w_lat_scanin),
	.scan_out(inst_valid_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(inst_valid_b		),
	.dout	(pre_inst_valid_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign inst_valid_w =
       pre_inst_valid_w & ~d_flush_w;

assign illegal_inst_w_in =
       illegal_inst_b & 
       kill_exc_gt_6_lt_7_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 illegal_inst_w_lat  (
	.scan_in(illegal_inst_w_lat_scanin),
	.scan_out(illegal_inst_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(illegal_inst_w_in	),
	.dout	(illegal_inst_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_miss_w_in =
       itlb_miss_b & ~m103663_exc_b & kill_exc_lt_6_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_miss_w_lat  (
	.scan_in(itlb_miss_w_lat_scanin),
	.scan_out(itlb_miss_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(itlb_miss_w_in		),
	.dout	(itlb_miss_w		),
  .siclk(siclk),
  .soclk(soclk)
);


assign ra_itlb_miss_w_in =
       ra_itlb_miss_b & ~m103663_exc_b & kill_exc_lt_6_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 ra_itlb_miss_w_lat  (
	.scan_in(ra_itlb_miss_w_lat_scanin),
	.scan_out(ra_itlb_miss_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(ra_itlb_miss_w_in	),
	.dout	(ra_itlb_miss_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_priv_exc_w_in =
       itlb_priv_exc_b & ~m103663_exc_b & kill_exc_lt_6_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_priv_exc_w_lat  (
	.scan_in(itlb_priv_exc_w_lat_scanin),
	.scan_out(itlb_priv_exc_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(itlb_priv_exc_w_in	),
	.dout	(itlb_priv_exc_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_nfo_exc_w_in =
       itlb_nfo_exc_b & ~m103663_exc_b & kill_exc_lt_6_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_nfo_exc_w_lat  (
	.scan_in(itlb_nfo_exc_w_lat_scanin),
	.scan_out(itlb_nfo_exc_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(itlb_nfo_exc_w_in	),
	.dout	(itlb_nfo_exc_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign i_l2_unde_w_in =
       i_l2_unde_b & ~m103663_exc_b & kill_exc_lt_6_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 i_l2_err_w_lat  (
	.scan_in(i_l2_err_w_lat_scanin),
	.scan_out(i_l2_err_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(i_l2_unde_w_in		),
	.dout	(i_l2_unde_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign i_oor_va_w_in =
       (i_oor_va_b | target_oor_va_b) & kill_exc_iar_irr_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 i_oor_va_w_lat  (
	.scan_in(i_oor_va_w_lat_scanin),
	.scan_out(i_oor_va_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(i_oor_va_w_in		),
	.dout	(i_oor_va_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign i_ra_oor_va_w_in =
       (i_ra_oor_va_b | target_ra_oor_va_b) & kill_exc_iar_irr_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 i_ra_oor_va_w_lat  (
	.scan_in(i_ra_oor_va_w_lat_scanin),
	.scan_out(i_ra_oor_va_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(i_ra_oor_va_w_in	),
	.dout	(i_ra_oor_va_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign itlb_err_w_in =
       itlb_err_b & ~m103663_exc_b & kill_exc_lt_6_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 itlb_err_w_lat  (
	.scan_in(itlb_err_w_lat_scanin),
	.scan_out(itlb_err_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(itlb_err_w_in		),
	.dout	(itlb_err_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign ic_err_w_in =
       ic_err_b & ~itlb_err_b & ~m103663_exc_b & kill_exc_lt_6_b_;

assign icp_req_in =
       ic_err_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 ic_err_w_lat  (
	.scan_in(ic_err_w_lat_scanin),
	.scan_out(ic_err_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(icp_req_in		),
	.dout	(icp_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign done_inst_w_in =
       done_inst_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 done_inst_w_lat  (
	.scan_in(done_inst_w_lat_scanin),
	.scan_out(done_inst_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(done_inst_w_in		),
	.dout	(done_inst_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign retry_inst_w_in =
       retry_inst_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 retry_inst_w_lat  (
	.scan_in(retry_inst_w_lat_scanin),
	.scan_out(retry_inst_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(retry_inst_w_in	),
	.dout	(retry_inst_w		),
  .siclk(siclk),
  .soclk(soclk)
);

// Disrupting single step completion must be higher priority
// than SIR because it's really for the previous instruction
assign sir_w_in =
       sir_b & ~dsc_req_in & ~target_oor_b;

tlu_fls_ctl_msff_ctl_macro__width_1 sir_w_lat  (
	.scan_in(sir_w_lat_scanin),
	.scan_out(sir_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(sir_w_in		),
	.dout	(sir_w			),
  .siclk(siclk),
  .soclk(soclk)
);

assign hpriv_exc_w_in =
       hpriv_exc_b & kill_exc_gt_6_lt_7_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 hpriv_exc_w_lat  (
	.scan_in(hpriv_exc_w_lat_scanin),
	.scan_out(hpriv_exc_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(hpriv_exc_w_in		),
	.dout	(hpriv_exc_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign priv_exc_w_in =
       priv_exc_b & ~illegal_inst_b & ~hpriv_exc_b & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 priv_exc_w_lat  (
	.scan_in(priv_exc_w_lat_scanin),
	.scan_out(priv_exc_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(priv_exc_w_in		),
	.dout	(priv_exc_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign fpdisable_exc_w_in =
       fpdisable_exc_b & ~(lsu_inst_b & lsu_illegal_inst_b) & 
       kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 fpdisable_exc_w_lat  (
	.scan_in(fpdisable_exc_w_lat_scanin),
	.scan_out(fpdisable_exc_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(fpdisable_exc_w_in	),
	.dout	(fpdisable_exc_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign tcc_w_in =
       e_tcc_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 tcc_w_lat  (
	.scan_in(tcc_w_lat_scanin),
	.scan_out(tcc_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(tcc_w_in		),
	.dout	(tcc_w			),
  .siclk(siclk),
  .soclk(soclk)
);

assign tof_w_in =
       e_tof_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 tof_w_lat  (
	.scan_in(tof_w_lat_scanin),
	.scan_out(tof_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(tof_w_in		),
	.dout	(tof_w			),
  .siclk(siclk),
  .soclk(soclk)
);

assign kill_e_f_ecc_b =
       lsu_inst_b & lsu_illegal_inst_b;

assign e_ecc_b =
       e_cecc_b | e_uecc_b;

assign e_f_ecc_w_in =
       (e_ecc_b &              ~kill_e_f_ecc_b & kill_exc_ge_7_lt_11_b_) | 
       (f_ecc_b & fgu_inst_b & ~kill_e_f_ecc_b & kill_exc_ge_7_lt_11_b_);

tlu_fls_ctl_msff_ctl_macro__width_1 e_ecc_w_lat  (
	.scan_in(e_ecc_w_lat_scanin),
	.scan_out(e_ecc_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(e_f_ecc_w_in		),
	.dout	(e_f_ecc_w		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 kill_irf_ecc_w_lat  (
	.scan_in(kill_irf_ecc_w_lat_scanin),
	.scan_out(kill_irf_ecc_w_lat_scanout),
	.din	(kill_e_f_ecc_b		),
	.dout	(kill_e_f_ecc_w		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_kill_irf_ecc_w =
       kill_e_f_ecc_w;

assign e_misalign_b =
       misalign_b & ~fnn_b & ~fno_b;

assign e_misalign_w_in =
       e_misalign_b & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 e_misalign_w_lat  (
	.scan_in(e_misalign_w_lat_scanin),
	.scan_out(e_misalign_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(e_misalign_w_in	),
	.dout	(e_misalign_w		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 immu_enable_lat  (
	.scan_in(immu_enable_lat_scanin),
	.scan_out(immu_enable_lat_scanout),
	.din	(lsu_immu_enable	[3:0]	),
	.dout	(immu_enable		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign br_real_b =
       | (~itlb_bypass[3:0] & ~immu_enable[3:0] & tid_dec_b[3:0]);

assign br_bypass_b =
       | ( itlb_bypass[3:0] &                       tid_dec_b[3:0]);

assign br_oor_va_b =
       e_oor_va_b & pre_br_taken_b & ~e_fill_b & 
       ~misalign_b & ~tct_b & ~br_real_b & ~br_bypass_b;

// Kill ld_oor_va_b if FGU inst with FRF ECC error
assign ld_oor_va_b =
       e_oor_va_b & ~lsu_va_watchpoint_b & ~lsu_tlb_bypass_b & ~lsu_align_b &
       ~lsu_stdf_align_b & ~lsu_lddf_align_b & ~lsu_priv_action_b & 
       ~lsu_tlb_real_b & ~lsu_illegal_inst_b & ~fpdisable_exc_b & 
       lsu_inst_b & (~fgu_inst_b | ~f_ecc_b);

assign br_oor_va_w_in =
       br_oor_va_b & kill_exc_ge_7_lt_11_b_;

assign br_ld_oor_va_w_in =
       (br_oor_va_b | ld_oor_va_b) & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 br_ld_oor_va_w_lat  (
	.scan_in(br_ld_oor_va_w_lat_scanin),
	.scan_out(br_ld_oor_va_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(br_ld_oor_va_w_in	),
	.dout	(br_ld_oor_va_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign br_ra_oor_va_b =
       e_oor_va_b & pre_br_taken_b & ~e_fill_b & 
       ~misalign_b & ~tct_b & br_real_b;

// Kill ld_ra_oor_va_b if FGU inst with FRF ECC error
assign ld_ra_oor_va_b =
       e_oor_va_b & ~lsu_va_watchpoint_b & ~lsu_tlb_bypass_b & ~lsu_align_b &
       ~lsu_stdf_align_b & ~lsu_lddf_align_b & ~lsu_priv_action_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b & lsu_inst_b & lsu_tlb_real_b & 
       (~fgu_inst_b | ~f_ecc_b);

assign br_ra_oor_va_w_in =
       br_ra_oor_va_b & kill_exc_ge_7_lt_11_b_;

assign br_ld_ra_oor_va_w_in =
       (br_ra_oor_va_b | ld_ra_oor_va_b) & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 br_ld_ra_oor_va_w_lat  (
	.scan_in(br_ld_ra_oor_va_w_lat_scanin),
	.scan_out(br_ld_ra_oor_va_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(br_ld_ra_oor_va_w_in	),
	.dout	(br_ld_ra_oor_va_w	),
  .siclk(siclk),
  .soclk(soclk)
);

// Hang onto VA hole exceptions on branches with delay slots when the branch
// occurs with the TLB in bypass mode because the delay slot instruction can
// take us out of bypass.  In this case, the processor should take an
// instruction_address_range or instruction_real_range trap on the target

// Same basic scenario, but PSTATE.am is set when branch is executed but
// clears due to delay slot.

// Same scenario, but now take a trap in the delay slot and return from
// trap handler while changing PSTATE.am or activating translation
//
// So the generic fix is to carry a 'oor_va' bit with the PC and NPC
// even into the trap stack.  pct tracks the 'oor_va' bit into the E stage

tlu_fls_ctl_msff_ctl_macro__width_2 pc_oor_va_b_lat  (
	.scan_in(pc_oor_va_b_lat_scanin),
	.scan_out(pc_oor_va_b_lat_scanout),
	.din	({pct_pc_oor_va_e	       ,
		  pc_oor_va_m		       }),
	.dout	({pc_oor_va_m		       ,
		  pc_oor_va_b		       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// instruction_VA_watchpoint is higher priority
assign target_oor_b = 
       pc_oor_va_b & pre_inst_valid_b & ~br_bypass_b & ~pstate_am_b & ~iaw_b;

assign target_oor_va_b =
       target_oor_b & ~br_real_b;

assign target_ra_oor_va_b =
       target_oor_b &  br_real_b;

assign snn_b = 
       exu_spill_b &  exu_normal_b & ~e_cecc_b & ~e_uecc_b;
assign sno_b = 
       exu_spill_b & ~exu_normal_b & ~e_cecc_b & ~e_uecc_b;
assign fnn_b = 
       e_fill_b  &  exu_normal_b & ~e_cecc_b & ~e_uecc_b;
assign fno_b = 
       e_fill_b  & ~exu_normal_b & ~e_cecc_b & ~e_uecc_b;

assign snn_w_in =
       snn_b & kill_exc_ge_7_lt_11_b_;
assign sno_w_in =
       sno_b & kill_exc_ge_7_lt_11_b_;
assign fnn_w_in =
       fnn_b & kill_exc_ge_7_lt_11_b_;
assign fno_w_in =
       fno_b & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 snn_w_lat  (
	.scan_in(snn_w_lat_scanin),
	.scan_out(snn_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(snn_w_in		),
	.dout	(snn_w			),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 sno_w_lat  (
	.scan_in(sno_w_lat_scanin),
	.scan_out(sno_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(sno_w_in		),
	.dout	(sno_w			),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 fnn_w_lat  (
	.scan_in(fnn_w_lat_scanin),
	.scan_out(fnn_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(fnn_w_in		),
	.dout	(fnn_w			),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 fno_w_lat  (
	.scan_in(fno_w_lat_scanin),
	.scan_out(fno_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(fno_w_in		),
	.dout	(fno_w			),
  .siclk(siclk),
  .soclk(soclk)
);

assign clw_b = 
       exu_cleanwin_b & ~e_cecc_b & ~e_uecc_b;

assign clw_w_in =
       clw_b & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 clw_w_lat  (
	.scan_in(clw_w_lat_scanin),
	.scan_out(clw_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(clw_w_in		),
	.dout	(clw_w			),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 lsu_inst_w_lat  (
	.scan_in(lsu_inst_w_lat_scanin),
	.scan_out(lsu_inst_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(lsu_inst_b		),
	.dout	(lsu_inst_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_lsu_inst_w =
       lsu_inst_w & pre_inst_valid_w;

tlu_fls_ctl_msff_ctl_macro__width_1 cti_w_lat  (
	.scan_in(cti_w_lat_scanin),
	.scan_out(cti_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(cti_b			),
	.dout	(cti_w			),
  .siclk(siclk),
  .soclk(soclk)
);

assign wstate3_b[2:0] = 
	({3 { dec_inst_valid_b[3]}} & exu_wstate_b	[2:0]) | 
	({3 {~dec_inst_valid_b[3]}} & wstate3_w	[2:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_3 wstate3_w_lat  (
	.scan_in(wstate3_w_lat_scanin),
	.scan_out(wstate3_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(wstate3_b	[2:0]	),
	.dout	(wstate3_w	[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign wstate2_b[2:0] = 
	({3 { dec_inst_valid_b[2]}} & exu_wstate_b	[2:0]) | 
	({3 {~dec_inst_valid_b[2]}} & wstate2_w	[2:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_3 wstate2_w_lat  (
	.scan_in(wstate2_w_lat_scanin),
	.scan_out(wstate2_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(wstate2_b	[2:0]	),
	.dout	(wstate2_w	[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign wstate1_b[2:0] = 
	({3 { dec_inst_valid_b[1]}} & exu_wstate_b	[2:0]) | 
	({3 {~dec_inst_valid_b[1]}} & wstate1_w	[2:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_3 wstate1_w_lat  (
	.scan_in(wstate1_w_lat_scanin),
	.scan_out(wstate1_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(wstate1_b	[2:0]	),
	.dout	(wstate1_w	[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign wstate0_b[2:0] = 
	({3 { dec_inst_valid_b[0]}} & exu_wstate_b	[2:0]) | 
	({3 {~dec_inst_valid_b[0]}} & wstate0_w	[2:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_3 wstate0_w_lat  (
	.scan_in(wstate0_w_lat_scanin),
	.scan_out(wstate0_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(wstate0_b	[2:0]	),
	.dout	(wstate0_w	[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_wstate3[2:0] =
       wstate3_w[2:0];
assign fls_wstate2[2:0] =
       wstate2_w[2:0];
assign fls_wstate1[2:0] =
       wstate1_w[2:0];
assign fls_wstate0[2:0] =
       wstate0_w[2:0];

assign in_user_b = 
       ( | (tid_dec_b[3:0] & 
	    ~(hpstate_hpriv[3:0] | tsd_pstate_priv[3:0])));

assign trap_number_b[7:0] =
       {exu_trap_number_b[7] & ~in_user_b, exu_trap_number_b[6:0]};

tlu_fls_ctl_msff_ctl_macro__width_8 trap_number_w_lat  (
	.scan_in(trap_number_w_lat_scanin),
	.scan_out(trap_number_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(trap_number_b		[7:0]	),
	.dout	(trap_number_w		[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign trap_number_3_in[7:0] = 
	({8 { tid_dec_w[3]}} & trap_number_w		[7:0]) | 
	({8 {~tid_dec_w[3]}} & trap_number_3		[7:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_8 trap_number_3_lat  (
	.scan_in(trap_number_3_lat_scanin),
	.scan_out(trap_number_3_lat_scanout),
	.din	(trap_number_3_in	[7:0]	),
	.dout	(trap_number_3		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trap_number_2_in[7:0] = 
	({8 { tid_dec_w[2]}} & trap_number_w		[7:0]) |
	({8 {~tid_dec_w[2]}} & trap_number_2		[7:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_8 trap_number_2_lat  (
	.scan_in(trap_number_2_lat_scanin),
	.scan_out(trap_number_2_lat_scanout),
	.din	(trap_number_2_in	[7:0]	),
	.dout	(trap_number_2		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trap_number_1_in[7:0] = 
	({8 { tid_dec_w[1]}} & trap_number_w		[7:0]) | 
	({8 {~tid_dec_w[1]}} & trap_number_1		[7:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_8 trap_number_1_lat  (
	.scan_in(trap_number_1_lat_scanin),
	.scan_out(trap_number_1_lat_scanout),
	.din	(trap_number_1_in	[7:0]	),
	.dout	(trap_number_1		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trap_number_0_in[7:0] = 
	({8 { tid_dec_w[0]}} & trap_number_w		[7:0]) | 
	({8 {~tid_dec_w[0]}} & trap_number_0		[7:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_8 trap_number_0_lat  (
	.scan_in(trap_number_0_lat_scanin),
	.scan_out(trap_number_0_lat_scanout),
	.din	(trap_number_0_in	[7:0]	),
	.dout	(trap_number_0		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_tcc_number_3[7:0] = 
	trap_number_3_in[7:0];
assign fls_tcc_number_2[7:0] = 
	trap_number_2_in[7:0];
assign fls_tcc_number_1[7:0] = 
	trap_number_1_in[7:0];
assign fls_tcc_number_0[7:0] = 
	trap_number_0_in[7:0];

assign lddf_align_b = 
       lsu_lddf_align_b & lsu_inst_b & ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b;

assign lddf_align_w_in =
       lddf_align_b & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 lddf_align_w_lat  (
	.scan_in(lddf_align_w_lat_scanin),
	.scan_out(lddf_align_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(lddf_align_w_in	),
	.dout	(lddf_align_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign stdf_align_b = 
       lsu_stdf_align_b & lsu_inst_b & ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b;

assign stdf_align_w_in =
       stdf_align_b & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 stdf_align_w_lat  (
	.scan_in(stdf_align_w_lat_scanin),
	.scan_out(stdf_align_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(stdf_align_w_in	),
	.dout	(stdf_align_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign daccess_prot_b = 
       lsu_daccess_prot_b & ~(e_oor_va_b & ~lsu_tlb_bypass_b) & 
       ~lsu_align_b & ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & 
       ~lsu_priv_action_b & ~lsu_stdf_align_b & ~lsu_lddf_align_b &
       ~lsu_va_watchpoint_b & ~lsu_dae_invalid_asi_b & 
       ~lsu_dae_priv_viol_b & ~lsu_dae_nc_page_b & ~lsu_dae_nfo_page_b & 
       ~lsu_dae_so_page & ~dtlb_error_b & lsu_inst_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b;

assign daccess_prot_w_in =
       daccess_prot_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 daccess_prot_w_lat  (
	.scan_in(daccess_prot_w_lat_scanin),
	.scan_out(daccess_prot_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(daccess_prot_w_in	),
	.dout	(daccess_prot_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign priv_action_b = 
       lsu_priv_action_b &
       ~lsu_align_b & ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & 
       ~lsu_stdf_align_b & ~lsu_lddf_align_b & lsu_inst_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b;


assign priv_action_w_in =
       priv_action_b & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 priv_action_w_lat  (
	.scan_in(priv_action_w_lat_scanin),
	.scan_out(priv_action_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(priv_action_w_in	),
	.dout	(priv_action_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign va_watchpoint_b = 
       lsu_va_watchpoint_b & ~lsu_tlb_bypass_b & ~lsu_align_b & 
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & 
       ~lsu_priv_action_b & ~lsu_stdf_align_b & ~lsu_lddf_align_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b &
       lsu_inst_b;

assign va_watchpoint_w_in =
       va_watchpoint_b & kill_exc_ge_7_lt_11_b_; 

tlu_fls_ctl_msff_ctl_macro__width_1 va_watchpoint_w_lat  (
	.scan_in(va_watchpoint_w_lat_scanin),
	.scan_out(va_watchpoint_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(va_watchpoint_w_in	),
	.dout	(va_watchpoint_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pa_watchpoint_b = 
       lsu_pa_watchpoint_b & ~(e_oor_va_b & ~lsu_tlb_bypass_b) & 
       lsu_tlb_miss_b_ &
       ~lsu_align_b & ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & 
       ~lsu_priv_action_b & ~lsu_stdf_align_b & ~lsu_lddf_align_b &
       ~lsu_va_watchpoint_b & ~lsu_dae_invalid_asi_b & 
       ~lsu_dae_priv_viol_b & ~lsu_dae_nc_page_b & ~lsu_dae_nfo_page_b & 
       ~lsu_dae_so_page & ~dtlb_error_b & ~lsu_daccess_prot_b & lsu_inst_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b;

assign pa_watchpoint_w_in =
       pa_watchpoint_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 pa_watchpoint_w_lat  (
	.scan_in(pa_watchpoint_w_lat_scanin),
	.scan_out(pa_watchpoint_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(pa_watchpoint_w_in	),
	.dout	(pa_watchpoint_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign align_b =
       lsu_align_b & ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & lsu_inst_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b;


assign align_w_in =
       align_b & kill_exc_ge_7_lt_11_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 align_w_lat  (
	.scan_in(align_w_lat_scanin),
	.scan_out(align_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(align_w_in		),
	.dout	(align_w		),
  .siclk(siclk),
  .soclk(soclk)
);

// lsu_perfmon_trap_b can assert for TLB miss or for data cache miss
// If both signals assert, then the pic_overflow should have priority
// if the trap is not masked
assign dtlb_miss_b =
       ~lsu_tlb_miss_b_ & lsu_inst_b & ~lsu_tlb_real_b & ~lsu_priv_action_b & 
       ~lsu_align_b & ~lsu_lddf_align_b & ~lsu_stdf_align_b & 
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & ~e_oor_va_b &
       ~lsu_va_watchpoint_b & ~lsu_illegal_inst_b & ~fpdisable_exc_b & 
       ~lsu_dae_invalid_asi_b &
       ~perfmon_trap_b &
       ~ld_oor_va_b & ~ld_ra_oor_va_b & ~dtlb_error_b;

assign dtlb_miss_w_in =
       dtlb_miss_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 dtlb_w_lat  (
	.scan_in(dtlb_w_lat_scanin),
	.scan_out(dtlb_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dtlb_miss_w_in		),
	.dout	(dtlb_miss_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ra_dtlb_miss_b =
       ~lsu_tlb_miss_b_ & lsu_inst_b & lsu_tlb_real_b & ~lsu_priv_action_b & 
       ~lsu_align_b & ~lsu_lddf_align_b & ~lsu_stdf_align_b & 
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & ~e_oor_va_b &
       ~lsu_va_watchpoint_b & ~lsu_illegal_inst_b & ~fpdisable_exc_b & 
       ~lsu_dae_invalid_asi_b & 
       ~perfmon_trap_b &
       ~ld_oor_va_b & ~ld_ra_oor_va_b & ~dtlb_error_b;

assign ra_dtlb_miss_w_in =
       ra_dtlb_miss_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 ra_dtlb_w_lat  (
	.scan_in(ra_dtlb_w_lat_scanin),
	.scan_out(ra_dtlb_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(ra_dtlb_miss_w_in	),
	.dout	(ra_dtlb_miss_w		),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 l_real_w_lat  (
	.scan_in(l_real_w_lat_scanin),
	.scan_out(l_real_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(lsu_tlb_real_b		),
	.dout	(l_real_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign dae_invalid_asi_b = 
       lsu_dae_invalid_asi_b & ~(e_oor_va_b & ~lsu_tlb_bypass_b) &
       ~lsu_align_b & ~lsu_lddf_align_b & ~lsu_stdf_align_b & 
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b &
       ~lsu_priv_action_b & ~lsu_va_watchpoint_b & ~lsu_illegal_inst_b & 
       ~fpdisable_exc_b & lsu_inst_b;

assign dae_invalid_asi_w_in =
       dae_invalid_asi_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 dae_invalid_asi_w_lat  (
	.scan_in(dae_invalid_asi_w_lat_scanin),
	.scan_out(dae_invalid_asi_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dae_invalid_asi_w_in	),
	.dout	(dae_invalid_asi_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign dae_nc_page_b = 
       lsu_dae_nc_page_b & ~(e_oor_va_b & ~lsu_tlb_bypass_b) & 
       ~lsu_align_b & ~lsu_lddf_align_b & ~lsu_stdf_align_b & 
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b &
       ~lsu_dae_invalid_asi_b & ~lsu_dae_priv_viol_b & ~lsu_priv_action_b & 
       ~lsu_va_watchpoint_b & ~lsu_illegal_inst_b & ~fpdisable_exc_b & 
       ~dtlb_error_b & lsu_inst_b;

assign dae_nc_page_w_in =
       dae_nc_page_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 dae_nc_page_w_lat  (
	.scan_in(dae_nc_page_w_lat_scanin),
	.scan_out(dae_nc_page_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dae_nc_page_w_in	),
	.dout	(dae_nc_page_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign dae_nfo_page_b = 
       lsu_dae_nfo_page_b & ~(e_oor_va_b & ~lsu_tlb_bypass_b) & 
       ~lsu_align_b & ~lsu_lddf_align_b & ~lsu_stdf_align_b & 
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b &
       ~lsu_dae_invalid_asi_b & ~lsu_dae_priv_viol_b & ~lsu_dae_nc_page_b & 
       ~lsu_priv_action_b & ~lsu_va_watchpoint_b & ~lsu_illegal_inst_b & 
       ~fpdisable_exc_b & ~dtlb_error_b & lsu_inst_b;

assign dae_nfo_page_w_in =
       dae_nfo_page_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 dae_nfo_page_w_lat  (
	.scan_in(dae_nfo_page_w_lat_scanin),
	.scan_out(dae_nfo_page_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dae_nfo_page_w_in	),
	.dout	(dae_nfo_page_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign dae_priv_viol_b = 
       lsu_dae_priv_viol_b & ~(e_oor_va_b & ~lsu_tlb_bypass_b) & 
       ~lsu_align_b & ~lsu_lddf_align_b & ~lsu_stdf_align_b & 
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b &
       ~lsu_dae_invalid_asi_b & ~lsu_priv_action_b & ~lsu_va_watchpoint_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b & ~dtlb_error_b & lsu_inst_b;

assign dae_priv_viol_w_in =
       dae_priv_viol_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 dae_priv_viol_w_lat  (
	.scan_in(dae_priv_viol_w_lat_scanin),
	.scan_out(dae_priv_viol_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dae_priv_viol_w_in	),
	.dout	(dae_priv_viol_w	),
  .siclk(siclk),
  .soclk(soclk)
);

assign dae_so_page_b = 
       lsu_dae_so_page & ~(e_oor_va_b & ~lsu_tlb_bypass_b) & 
       ~lsu_align_b & ~lsu_lddf_align_b & ~lsu_stdf_align_b & 
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b &
       ~lsu_dae_invalid_asi_b & ~lsu_dae_priv_viol_b & ~lsu_dae_nc_page_b & 
       ~lsu_priv_action_b & ~lsu_va_watchpoint_b & ~lsu_illegal_inst_b & 
       ~fpdisable_exc_b & ~dtlb_error_b & lsu_inst_b;

assign dae_so_page_w_in =
       dae_so_page_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 dae_so_page_w_lat  (
	.scan_in(dae_so_page_w_lat_scanin),
	.scan_out(dae_so_page_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dae_so_page_w_in	),
	.dout	(dae_so_page_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign dtlb_error_b =
       (lsu_dttp_err_b | lsu_dtmh_err_b | lsu_dtdp_err_b) & 
       ~lsu_dae_invalid_asi_b & 
       ~(e_oor_va_b & ~lsu_tlb_bypass_b) & 
       ~lsu_align_b & ~lsu_lddf_align_b & ~lsu_stdf_align_b &
       ~e_cecc_b & ~e_uecc_b & ~f_ecc_b &
       ~lsu_priv_action_b & ~lsu_va_watchpoint_b & ~lsu_illegal_inst_b & 
       ~fpdisable_exc_b & lsu_inst_b;

assign dtlb_error_w_in =
       dtlb_error_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 dtlb_error_w_lat  (
	.scan_in(dtlb_error_w_lat_scanin),
	.scan_out(dtlb_error_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dtlb_error_w_in	),
	.dout	(dtlb_error_w		),
  .siclk(siclk),
  .soclk(soclk)
);

// If LSU signals PMU trap, and no earlier exception occurred,
// it will be treated as the same as if pmu_tlu_trap_m
// had been asserted in the M stage
//  Prioritizing precise_perf_trap over f_ecc
assign perfmon_trap_b = 
       lsu_perfmon_trap_b & pil_mask_15_b & lsu_inst_b;

assign precise_perf_trap_b =
       perfmon_trap_b & ~tlz_exc_dec_b & 
       ~dsc_req_in & 
       ~por_req_in & ~xir_req_in & ~ftt_req_in & 
       ~sir_b &
       ~lsu_pa_watchpoint_b & ~(e_oor_va_b & ~lsu_tlb_bypass_b) & 
       ~lsu_align_b & ~e_cecc_b & ~e_uecc_b & ~f_ecc_b & 
       ~lsu_priv_action_b & ~lsu_stdf_align_b & ~lsu_lddf_align_b &
       ~lsu_va_watchpoint_b & ~lsu_dae_invalid_asi_b & 
       ~lsu_dae_priv_viol_b & ~lsu_dae_nc_page_b & ~lsu_dae_nfo_page_b & 
       ~lsu_dae_so_page & ~dtlb_error_b & ~lsu_daccess_prot_b & lsu_inst_b & 
       ~lsu_illegal_inst_b & ~fpdisable_exc_b & ~debug_exc_b & ~target_oor_b;

assign pil_mask_15_b =
       | (pil_mask_15[3:0] & tid_dec_b[3:0]);

assign tlz_exc_dec_b =
       | (trl_tlz_exc[3:0] & tid_dec_b[3:0]);

// precise_perf_trap_w is higher priority than disrupting exceptions
// and it's essentially the same as pmu_exception
//   Prioritize precise_perf_trap_w lower than disrupting
// 		   exceptions to avoid OV bit not being set when pic_oveflow
// 		   trap is taken
assign precise_perf_trap_w_in =
       precise_perf_trap_b & ~disrupting_flush_b;

tlu_fls_ctl_msff_ctl_macro__width_1 precise_perf_trap_w_lat  (
	.scan_in(precise_perf_trap_w_lat_scanin),
	.scan_out(precise_perf_trap_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(precise_perf_trap_w_in	),
	.dout	(precise_perf_trap_w	),
  .siclk(siclk),
  .soclk(soclk)
);


// PMU trap is a disrupting exception with priority 16.0, so it needs to be 
// higher priority than all disruptings except
//	- disrupting single step completion
// 	- resets
//	- deferred (store_error)
//	- trap level zero
assign perf_trap_w_in = 
       (| (perf_trap_b[3:0] & ~trl_tlz_exc[3:0])) &
       ~dsc_req_in & 
       ~por_req_in & ~xir_req_in & ~ftt_req_in & 
       ~sir_b;

tlu_fls_ctl_msff_ctl_macro__width_1 perf_trap_w_lat  (
	.scan_in(perf_trap_w_lat_scanin),
	.scan_out(perf_trap_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(perf_trap_w_in			),
	.dout	(perf_trap_w			),
  .siclk(siclk),
  .soclk(soclk)
);

assign ibp_w_in = 
       ibp_b & ~ic_err_b & ~itlb_err_b & ~illegal_inst_b & ~hpriv_exc_b & 
       ~sir_b &
       ~itlb_miss_b & ~ra_itlb_miss_b & ~iaw_b & ~i_oor_va_b & ~i_ra_oor_va_b &
       ~target_oor_b & 
       ~i_l2_unde_b & ~itlb_priv_exc_b & ~itlb_nfo_exc_b & 
       kill_exc_lt_6_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 ibp_w_lat  (
	.scan_in(ibp_w_lat_scanin),
	.scan_out(ibp_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(ibp_w_in			),
	.dout	(ibp_w				),
  .siclk(siclk),
  .soclk(soclk)
);

assign iaw_w_in = 
       iaw_b & kill_exc_iaw_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 iaw_w_lat  (
	.scan_in(iaw_w_lat_scanin),
	.scan_out(iaw_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(iaw_w_in			),
	.dout	(iaw_w				),
  .siclk(siclk),
  .soclk(soclk)
);

assign tct_w_in = 
       tct_b & kill_exc_ge_7_lt_11_b_ & ~e_misalign_w_in & ~align_w_in & 
       ~br_oor_va_w_in & ~br_ra_oor_va_w_in & ~illegal_inst_w_in & 
       ~hpriv_exc_w_in & ~priv_exc_w_in & ~ic_err_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 tct_w_lat  (
	.scan_in(tct_w_lat_scanin),
	.scan_out(tct_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(tct_w_in			),
	.dout	(tct_w				),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 l_spec_enable_lat  (
	.scan_in(l_spec_enable_lat_scanin),
	.scan_out(l_spec_enable_lat_scanout),
	.din	(lsu_spec_enable	[3:0]	),
	.dout	(l_spec_enable		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign spec_enable =
       | (l_spec_enable[3:0] & tid_dec_b[3:0]);

// Kill FGU predicted exception if not in spec_enable mode
assign f_predict_b =
       fgu_inst_b & fgu_predict_fx2 & ~fgu_cecc_fx2 & ~fgu_uecc_fx2 & 
       spec_enable;

assign f_predict_w_in =
       f_predict_b & kill_exc_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 f_predict_w_lat  (
	.scan_in(f_predict_w_lat_scanin),
	.scan_out(f_predict_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(f_predict_w_in		),
	.dout	(f_predict_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdist_beat2_fx2_in =
       fgu_pdist_beat2_fx1 & fgu_inst_b & inst_valid_b & ~disrupting_flush_b & 
       ~pmu_debug_exc_b & ~dec_flush_b;

tlu_fls_ctl_msff_ctl_macro__width_1 pdist_beat2_fx2_lat  (
	.scan_in(pdist_beat2_fx2_lat_scanin),
	.scan_out(pdist_beat2_fx2_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(pdist_beat2_fx2_in	),
	.dout	(pdist_beat2_fx2	),
  .siclk(siclk),
  .soclk(soclk)
);

// Used to gate DTLB miss which can't happen for pdist
// and for in-pipe FRF ECC errors
assign f_ecc_b = 
       fgu_inst_b & (fgu_cecc_fx2 | fgu_uecc_fx2);

// Latch for tlu_ras_ctl
// No power management because this is used for both thread groups
tlu_fls_ctl_msff_ctl_macro__width_1 f_cecc_w_lat  (
	.scan_in(f_cecc_w_lat_scanin),
	.scan_out(f_cecc_w_lat_scanout),
	.din	(fgu_cecc_fx2		),
	.dout	(fls_f_cecc_w		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 f_uecc_w_lat  (
	.scan_in(f_uecc_w_lat_scanin),
	.scan_out(f_uecc_w_lat_scanout),
	.din	(fgu_uecc_fx2		),
	.dout	(fls_f_uecc_w		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign pdist_ecc_b = 
       pdist_beat2_fx2 & (fgu_cecc_fx2 | fgu_uecc_fx2);

assign pdist_ecc_w_in[3:0] =
       {4 {pdist_ecc_b}} & tid_dec_w[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 pdist_ecc_w_lat  (
	.scan_in(pdist_ecc_w_lat_scanin),
	.scan_out(pdist_ecc_w_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(pdist_ecc_w_in	[3:0]	),
	.dout	(pdist_ecc_w	[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign m_asi_ecc_b[3:0] =
       ({4 {mmu_asi_cecc | mmu_asi_uecc}} &
	{4 {mmu_asi_tid[2] == thread_group}} &
	{ mmu_asi_tid[1] &  mmu_asi_tid[0],
	  mmu_asi_tid[1] & ~mmu_asi_tid[0],
	 ~mmu_asi_tid[1] &  mmu_asi_tid[0],
	 ~mmu_asi_tid[1] & ~mmu_asi_tid[0]}) ;

assign asi_ecc_b[3:0] =
       m_asi_ecc_b[3:0] | 
       ({4 {asi_ece_exc  | asi_eue_exc }} &
	{4 {asi_ecc_tid[2] == thread_group}} &
	{ asi_ecc_tid[1] &  asi_ecc_tid[0],
	  asi_ecc_tid[1] & ~asi_ecc_tid[0],
	 ~asi_ecc_tid[1] &  asi_ecc_tid[0],
	 ~asi_ecc_tid[1] & ~asi_ecc_tid[0]}) | 
       tel_tsacu_exc[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 asi_ecc_w_lat  (
	.scan_in(asi_ecc_w_lat_scanin),
	.scan_out(asi_ecc_w_lat_scanout),
	.din	(asi_ecc_b	[3:0]	),
	.dout	(asi_ecc_w	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Instruction_access_MMU_error (HW TW MRA or L2 U/ND ECC error)
// Does not need to flush because flush occurred at beginning of HW TW
assign ime_b[3:0] =
       mmu_i_eccerr[3:0] & 
       {mmu_thr3_err_type_b1,
        mmu_thr2_err_type_b1,
        mmu_thr1_err_type_b1,
	mmu_thr0_err_type_b1};

tlu_fls_ctl_msff_ctl_macro__width_4 ime_w_lat  (
	.scan_in(ime_w_lat_scanin),
	.scan_out(ime_w_lat_scanout),
	.din	(ime_b		[3:0]	),
	.dout	(ime_w		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Data_access_MMU_error (HW TW MRA or L2 U/ND ECC error)
// Does not need to flush because flush occurred at beginning of HW TW
assign dme_b[3:0] =
       mmu_d_eccerr[3:0] & 
       {mmu_thr3_err_type_b1,
        mmu_thr2_err_type_b1,
        mmu_thr1_err_type_b1,
	mmu_thr0_err_type_b1};

tlu_fls_ctl_msff_ctl_macro__width_4 dme_w_lat  (
	.scan_in(dme_w_lat_scanin),
	.scan_out(dme_w_lat_scanout),
	.din	(dme_b		[3:0]	),
	.dout	(dme_w		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// unsupported_page_size in TSB config or data_in regs
// Does need to flush because only lsu_sync occurred (no previous flush)
// Pipe it one more cycle so MRA parity error can catch it
assign m_dae_req_m[3:0] = 
       {4 {mmu_dae_req}} &
       {4 {mmu_dae_tid[2] == thread_group}} &
	{ mmu_dae_tid[1] &  mmu_dae_tid[0],
	  mmu_dae_tid[1] & ~mmu_dae_tid[0],
	 ~mmu_dae_tid[1] &  mmu_dae_tid[0],
	 ~mmu_dae_tid[1] & ~mmu_dae_tid[0]};

tlu_fls_ctl_msff_ctl_macro__width_4 m_dae_req_b_lat  (
	.scan_in(m_dae_req_b_lat_scanin),
	.scan_out(m_dae_req_b_lat_scanout),
	.din	(m_dae_req_m		[3:0]	),
	.dout	(pm_dae_req_b		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign m_dae_req_b[3:0] = 
       pm_dae_req_b[3:0] & ~m_asi_ecc_b[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 m_dae_req_w_lat  (
	.scan_in(m_dae_req_w_lat_scanin),
	.scan_out(m_dae_req_w_lat_scanout),
	.din	(m_dae_req_b		[3:0]	),
	.dout	(m_dae_req_w		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// NPC nonsequential on retry
// Flag exception on first instruction after retry
// Reassert exception if instruction after retry is a taken branch that does
// not annul delay slot
// Have to hold nns exception through branch taken that does not annul DS
// Have to suppress nns exception for any other exception
// Have to clear nns_exc if thread is flushed OR non-flushing exception occurs

assign br_taken_not_annul_ds_w_in =
       br_taken_b & ~annul_ds_b;

tlu_fls_ctl_msff_ctl_macro__width_1 br_taken_not_annul_ds_w_lat  (
	.scan_in(br_taken_not_annul_ds_w_lat_scanin),
	.scan_out(br_taken_not_annul_ds_w_lat_scanout),
	.din	(br_taken_not_annul_ds_w_in	),
	.dout	(br_taken_not_annul_ds_w	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign hold_nns_exc_w[3:0] =
       ~tid_dec_w[3:0] | {4 {br_taken_not_annul_ds_w}} | 
       lsu_block_store_b[3:0];

assign clear_nns_exc_w[3:0] = 
       ({4 {~exc_for_w}} & tid_dec_w[3:0]) | multicycle_nns_to_npc_w[3:0];

assign flush_not_tablewalk[3:0] =
       (flush_ifu[3:0] & ~iht_request[3:0] & ~dht_request[3:0]) |
       hwtw_exception[3:0];

assign hwtw_exception[3:0] = 
	mmu_i_unauth_access[3:0] |
	mmu_i_tsb_miss[3:0] | mmu_d_tsb_miss[3:0] |
	mmu_i_tte_outofrange[3:0] | mmu_d_tte_outofrange[3:0] |
	ime_b[3:0] | dme_b[3:0] | m_dae_req_b[3:0] ;

assign nns_exc_in[3:0] =
       trl_nns_exc[3:0] | 
       (nns_exc[3:0] & (hold_nns_exc_w[3:0] | ~clear_nns_exc_w[3:0]) & 
	~flush_not_tablewalk[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 nns_exc_lat  (
	.scan_in(nns_exc_lat_scanin),
	.scan_out(nns_exc_lat_scanout),
	.din	(nns_exc_in		[3:0]	),
	.dout	(nns_exc		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_retry_state[3:0] =
       nns_exc[3:0] | {4 {ssmode | domode}};

// If the first instruction after retry is a taken branch that does not annul
// its delay shot,
// then the TNPC from the retry will be in the PC flop,
// otherwise it will be in the NPC flop
assign sync_inst_b =
       lsu_sync_inst_b & lsu_inst_b;

assign nns_to_pc_b[3:0] =
       nns_exc[3:0] & {4 {  br_taken_b & ~annul_ds_b  & ~sync_inst_b}} & 
       tid_dec_valid_b[3:0];

// This needs to be validated with EACH multicycle instruction taking an ECC
// error in EVERY cycle (including the first)
// Multicycle are pdist, casa, std, block store
assign nns_to_npc_b[3:0] =
       nns_exc[3:0] & 
       (({4 {~(br_taken_b & ~annul_ds_b) & ~sync_inst_b & 
           ~(fgu_pdist_beat2_fx1 & fgu_inst_b) & ~l_tlu_twocycle_b}} &
        ~(lsu_block_store_b[3:0] & bsee_req_in[3:0]) & 
        tid_dec_valid_b[3:0]) |
        multicycle_nns_to_npc_b[3:0]);

assign multicycle_nns_to_npc_b[3:0] = 
        (tid_dec_w[3:0] & {4 {beat_two_b & ~bsee_req_w_in}} & 
         ~pdist_ecc_w_in[3:0]) | 
        (~lsu_block_store_b[3:0] & block_store_w[3:0] & 
         ~bsee_req_in[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_12 nns_exc_w_lat  (
	.scan_in(nns_exc_w_lat_scanin),
	.scan_out(nns_exc_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	({nns_to_pc_b			[3:0],
		  nns_to_npc_b			[3:0],
		  multicycle_nns_to_npc_b	[3:0]}),
	.dout	({pnns_to_pc_w			[3:0],
		  pnns_to_npc_w			[3:0],
		  multicycle_nns_to_npc_w	[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);

assign nns_to_pc_w[3:0] =
       pnns_to_pc_w[3:0] & clear_nns_exc_w[3:0];

assign nns_to_npc_w[3:0] =
       pnns_to_npc_w[3:0] & clear_nns_exc_w[3:0];


////////////////////////////////////////////////////////////////////////////////
// Determine if instruction in M is from the same thread as in B

assign same_thread_b_m = 
       (((tid_m[1:0] == tid_b[1:0]) & 
         (pre_inst_valid_b | twocycle_inst_w)) |
	(| (tid_dec_m[3:0] & pbsee_pending_in[3:0])) |
	(| (tid_dec_m[3:0] & bsee_pending    [3:0])) |
	(| (tid_dec_m[3:0] & pdist_ecc_w_in  [3:0])) ) & inst_valid_m;


////////////////////////////////////////////////////////////////////////////////
// Determine if instruction in B had an exception

assign itlb_exc_b = 
       itlb_miss_b | ra_itlb_miss_b;

assign dtlb_exc_b = 
       ~lsu_tlb_miss_b_;

assign pdec_exc_b = 
       (i_l2_unde_b | i_oor_va_b | i_ra_oor_va_b | itlb_err_b | 
        ic_err_b | 
	pdone_inst_b | pretry_inst_b | 
	itlb_exc_b | itlb_priv_exc_b | itlb_nfo_exc_b | 
	pillegal_inst_b | psir_b | hpriv_exc_b |
	priv_exc_b | fpdisable_exc_b | pmu_debug_exc_b | 
	disrupting_flush_b) & inst_valid_b;

assign dec_exc_b = 
       (i_l2_unde_b | i_oor_va_b | i_ra_oor_va_b | itlb_err_b | 
        ic_err_b | 
	done_inst_b | retry_inst_b | 
	itlb_exc_b | itlb_priv_exc_b | itlb_nfo_exc_b | 
	illegal_inst_b | sir_b | hpriv_exc_b |
	priv_exc_b | fpdisable_exc_b | pmu_debug_exc_b | 
	disrupting_flush_b) & inst_valid_b;

assign exu_exc_b = 
       e_tcc_b | e_tof_b | e_cecc_b | e_uecc_b | misalign_b | 
       br_oor_va_b | br_ra_oor_va_b | ld_oor_va_b | ld_ra_oor_va_b | 
       exu_spill_b | e_fill_b | exu_cleanwin_b;

assign lsu_exc_b = 
       (lsu_align_b | dtlb_exc_b | lsu_dae_invalid_asi_b |
        lsu_dae_nc_page_b | lsu_dae_nfo_page_b | lsu_dae_priv_viol_b |
        lsu_dae_so_page |
        lsu_lddf_align_b | lsu_stdf_align_b | lsu_daccess_prot_b | 
        lsu_priv_action_b | lsu_va_watchpoint_b | lsu_pa_watchpoint_b | 
        lsu_dttp_err_b | lsu_dtdp_err_b | lsu_dtmh_err_b | 
        perfmon_trap_b) & 
        lsu_inst_b;

assign fgu_exc_b =
       f_predict_b | ((fgu_cecc_fx2 | fgu_uecc_fx2) & fgu_inst_b);

tlu_fls_ctl_msff_ctl_macro__width_4 exc_w_lat  (
	.scan_in(exc_w_lat_scanin),
	.scan_out(exc_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	({dec_exc_b		       ,
		  exu_exc_b		       ,
		  lsu_exc_b		       ,
		  fgu_exc_b		       }),
	.dout	({dec_exc_w		       ,
		  exu_exc_w		       ,
		  lsu_exc_w		       ,
		  fgu_exc_w		       }),
  .siclk(siclk),
  .soclk(soclk)
);

assign exc_for_w =
       (dec_exc_w | exu_exc_w | lsu_exc_w | fgu_exc_w) & 
       (inst_valid_w | beat_two_w);
assign exception_for_w =
       exc_for_w |
       bsee_req_w | (| (pdist_ecc_w[3:0] & tid_dec_b[3:0]));


////////////////////////////////////////////////////////////////////////////////
// Generate flushes

tlu_fls_ctl_msff_ctl_macro__width_4 trap_flush_lat  (
	.scan_in(trap_flush_lat_scanin),
	.scan_out(trap_flush_lat_scanout),
	.din	({lsu_trap_flush	[3:0]}),
	.dout	({ptrap_flush		[3:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Prevent trap_flush from flushing machine when in disable_overlap mode
// because there's no flush needed -- only one instruction in the machine
// at a time.  Also, the flush would kill the ssr_req in trl. 
assign trap_flush[3:0] =
       ptrap_flush[3:0] & {4 {~domode}};

assign preflush_exu_m = 
       same_thread_b_m;
assign preflush_lsu_m = 
       same_thread_b_m & dec_lsu_inst_m;
assign preflush_fgu_m = 
       same_thread_b_m & dec_fgu_inst_m;

tlu_fls_ctl_msff_ctl_macro__width_3 preflush_b_lat  (
	.scan_in(preflush_b_lat_scanin),
	.scan_out(preflush_b_lat_scanout),
	.din	({preflush_exu_m       , 
		  preflush_lsu_m       ,
		  preflush_fgu_m       }),
	.dout	({preflush_exu_b       , 
		  preflush_lsu_b       ,
		  preflush_fgu_b       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Note that pmu_debug_exc_b causes a flush in the B cycle of the instruction
// that has these exceptions.  
// Note that pmu_debug_exc_b is ORed into dec_exc_b, so that the execution units
// will receive flush_b when the instruction with the exception reaches W if
// the instruction in B is from the same thread
assign pmu_debug_exc_b =
       (| perf_trap_b[3:0]) | debug_exc_b;

assign debug_exc_b =
       ibp_b | iaw_b | tct_b | target_oor_b;

assign tlu_flush_exu_b = 
       (preflush_exu_b & exception_for_w) |
       (preflush_lsu_b & exception_for_w) | 
       disrupting_flush_b | pmu_debug_exc_b ;
			                                       
assign flush_lsu_b =
	(preflush_lsu_b     & exception_for_w) | 
	(disrupting_flush_b & lsu_inst_b     ) |
        (pmu_debug_exc_b    & lsu_inst_b     ) ;

assign flush_fgu_b =                                       
	(preflush_fgu_b     & exception_for_w) | 
	(disrupting_flush_b & fgu_inst_b     ) |
	(pmu_debug_exc_b    & fgu_inst_b     ) ;

assign fls_flush_lsu_b =
	flush_lsu_b;
			                                       
assign fls_flush_fgu_b =
	flush_fgu_b;

assign tlu_flush_lsu_b = 
	flush_lsu_b | flsx_flush_lsu_b;

assign tlu_flush_fgu_b = 
	flush_fgu_b | flsx_flush_fgu_b;

// IFU flushes regardless of whether the next instuction is from the same 
// thread
// IFU not flushed in B for tct, pmu, ibp, or iaw (but execution units are);
// IFU flushed in W for these exceptions
assign sync_flush_ifu[3:0] = 
       ({4 {exc_for_w}} & two_tid_dec_w[3:0]) |
       trap_flush[3:0];

assign flush_not_disrupting[3:0] =
       flush_gfb[3:0] | sync_flush_ifu[3:0] | m_dae_req_w[3:0] | 
       bsee_req[3:0] | pdist_ecc_w[3:0];

assign flush_ifu[3:0] =
       flush_not_disrupting[3:0] | clear_disrupting_flush_pending_w[3:0] | 
       (por_req[3:0] & core_running[3:0]);

assign tlu_flush_ifu[3:0] =
       flush_ifu[3:0];

assign fls_flush[3:0] =
       flush_ifu[3:0];	

// Flush PMU B if instruction in W had exception and instruction in B
// is from same thread
//	OR
// NPC arrived
//	OR
// disrupting flush for B
assign tlu_flush_pmu_b =
       flush_b | 
       (| (clear_disrupting_flush_pending[3:0] & ~perf_trap_b[3:0])) | 
       (debug_exc_b & ~(| perf_trap_b[3:0])) |
       tlz_exc_b;

// Flush PMU W if instruction in W had exception
assign tlu_flush_pmu_w =
       exc_for_w & ~perf_trap_w & ~precise_perf_trap_w;


////////////////////////////////////////////////////////////////////////////////
// Generate flushes for G and FB stages

assign l_tid_dec_g[3:0] = 
	{4 {thread_group == lsu_tid_g[2]}} &
	{ lsu_tid_g[1] &  lsu_tid_g[0],
	  lsu_tid_g[1] & ~lsu_tid_g[0],
	 ~lsu_tid_g[1] &  lsu_tid_g[0],
	 ~lsu_tid_g[1] & ~lsu_tid_g[0]};

assign fpx_tid_dec_fb[3:0] = 
	{4 {thread_group == fgu_fpx_trap_tid_fw[2]}} & 
	{ fgu_fpx_trap_tid_fw[1] &  fgu_fpx_trap_tid_fw[0],
	  fgu_fpx_trap_tid_fw[1] & ~fgu_fpx_trap_tid_fw[0],
	 ~fgu_fpx_trap_tid_fw[1] &  fgu_fpx_trap_tid_fw[0],
	 ~fgu_fpx_trap_tid_fw[1] & ~fgu_fpx_trap_tid_fw[0]};

assign fpd_tid_dec_fb[3:0] = 
	{4 {thread_group == fgu_fpd_trap_tid_fw[2]}} & 
	{ fgu_fpd_trap_tid_fw[1] &  fgu_fpd_trap_tid_fw[0],
	  fgu_fpd_trap_tid_fw[1] & ~fgu_fpd_trap_tid_fw[0],
	 ~fgu_fpd_trap_tid_fw[1] &  fgu_fpd_trap_tid_fw[0],
	 ~fgu_fpd_trap_tid_fw[1] & ~fgu_fpd_trap_tid_fw[0]};

assign dcerr_tid_dec_g[3:0] = 
       {4 {thread_group == lsu_dcerr_tid_g[2]}} &
	{ lsu_dcerr_tid_g[1] &  lsu_dcerr_tid_g[0],  
	  lsu_dcerr_tid_g[1] & ~lsu_dcerr_tid_g[0],  
	 ~lsu_dcerr_tid_g[1] &  lsu_dcerr_tid_g[0],  
	 ~lsu_dcerr_tid_g[1] & ~lsu_dcerr_tid_g[0]};

assign l_l2_ecc_g[3:0] =
       {4 {lsu_dcl2u_err_g | lsu_dcl2nd_err_g}} & dcerr_tid_dec_g[3:0];

assign l_sbdl_ecc_g[3:0] =
       {4 {(lsu_sbdlc_err_g | lsu_sbdlu_err_g) & 
       (thread_group == lsu_stberr_tid_g[2])}} &
	{ lsu_stberr_tid_g[1] &  lsu_stberr_tid_g[0],  
	  lsu_stberr_tid_g[1] & ~lsu_stberr_tid_g[0],  
	 ~lsu_stberr_tid_g[1] &  lsu_stberr_tid_g[0],  
	 ~lsu_stberr_tid_g[1] & ~lsu_stberr_tid_g[0]};

// lsu_priv_action_g can't happen for a L2 miss, so
// it will not happen on the same instruction as lsu_perfmon_trap_g
// lsu_priv_action_g and lsu_sbdp[cu]_err_g/lsu_sbapp_err_g/lsu_sbdiou_err_g
// can happen simultaneously for same thread; 
// the store buffer errors are
// disrupting, so no reason to prioritize
// lsu_priv_action_g cannot occur on same thread on same cycle as 
// lsu_sbdl[cu]_err_g
assign priv_action_g[3:0] = 
	{4 {lsu_priv_action_g}} & l_tid_dec_g[3:0];

assign precise_perf_trap_g[3:0] = 
	{4 {lsu_perfmon_trap_g & ~lsu_dcl2u_err_g & ~lsu_dcl2nd_err_g}} & 
        pil_mask_15[3:0] & dcerr_tid_dec_g[3:0];

assign fpx_ieee_exc_fb[3:0] = 
	{4 {fgu_fpx_ieee_trap_fw}} & fpx_tid_dec_fb[3:0];

assign fpd_ieee_exc_fb[3:0] = 
	{4 {fgu_fpd_ieee_trap_fw}} & fpd_tid_dec_fb[3:0];

assign fpx_unfin_exc_fb[3:0] = 
	{4 {fgu_fpx_unfin_fw}} & fpx_tid_dec_fb[3:0];

assign fpd_unfin_exc_fb[3:0] = 
	{4 {fgu_fpd_unfin_fw}} & fpd_tid_dec_fb[3:0];

assign idiv0_exc_fb[3:0] = 
	{4 {fgu_fpd_idiv0_trap_fw}} & fpx_tid_dec_fb[3:0];

assign flush_gfb_in[3:0] = 
       l_l2_ecc_g[3:0] | priv_action_g[3:0] |
       precise_perf_trap_g[3:0] |
       l_sbdl_ecc_g[3:0] |
       fpx_ieee_exc_fb[3:0] | fpd_ieee_exc_fb[3:0] |
       fpx_unfin_exc_fb[3:0] | fpd_unfin_exc_fb[3:0] | 
       idiv0_exc_fb[3:0] | asi_ecc_b[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 flush_gfb_lat  (
	.scan_in(flush_gfb_lat_scanin),
	.scan_out(flush_gfb_lat_scanout),
	.din	(flush_gfb_in	[3:0]	),
	.dout	(flush_gfb	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 l_l2_ecc_w_lat  (
	.scan_in(l_l2_ecc_w_lat_scanin),
	.scan_out(l_l2_ecc_w_lat_scanout),
	.din	(l_l2_ecc_g	[3:0]	),
	.dout	(l_l2_ecc_w	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 l_sbdl_ecc_w_lat  (
	.scan_in(l_sbdl_ecc_w_lat_scanin),
	.scan_out(l_sbdl_ecc_w_lat_scanout),
	.din	(l_sbdl_ecc_g	[3:0]	),
	.dout	(l_sbdl_ecc_w	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 priv_action_g_w_lat  (
	.scan_in(priv_action_g_w_lat_scanin),
	.scan_out(priv_action_g_w_lat_scanout),
	.din	(priv_action_g	[3:0]	),
	.dout	(priv_action_g_w[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 precise_perf_trap_g_w_lat  (
	.scan_in(precise_perf_trap_g_w_lat_scanin),
	.scan_out(precise_perf_trap_g_w_lat_scanout),
	.din	(precise_perf_trap_g	[3:0]	),
	.dout	(precise_perf_trap_g_w	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ieee_exc_fb[3:0] = 
	fpx_ieee_exc_fb[3:0] | fpd_ieee_exc_fb[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 ieee_exc_fw_lat  (
	.scan_in(ieee_exc_fw_lat_scanin),
	.scan_out(ieee_exc_fw_lat_scanout),
	.din	(ieee_exc_fb	[3:0]	),
	.dout	(ieee_exc_fw	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign unfin_fb[3:0] = 
	fpx_unfin_exc_fb[3:0] | fpd_unfin_exc_fb[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 unfin_fw_lat  (
	.scan_in(unfin_fw_lat_scanin),
	.scan_out(unfin_fw_lat_scanout),
	.din	(unfin_fb	[3:0]	),
	.dout	(unfin_fw	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 idiv0_exc_fw_lat  (
	.scan_in(idiv0_exc_fw_lat_scanin),
	.scan_out(idiv0_exc_fw_lat_scanout),
	.din	(idiv0_exc_fb	[3:0]	),
	.dout	(idiv0_exc_fw	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Generate flushes for disrupting traps
//	Includes reset requests
//

// XIR is not maskable, but use this structure to simplify verification
assign xir_flush_in[3:0] =
       cxi_xir[3:0] |
       (pre_xir_flush[3:0] & ~(trl_trap_taken[3:0] & {4 {trl_take_xir}}));

tlu_fls_ctl_msff_ctl_macro__width_4 xir_flush_lat  (
	.scan_in(xir_flush_lat_scanin),
	.scan_out(xir_flush_lat_scanout),
	.din	(xir_flush_in		[3:0]	),
	.dout	(pre_xir_flush		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign xir_flush_m[3:0] =
       pre_xir_flush[3:0] & tid_dec_m[3:0] & {4 {dec_inst_valid_m}};

assign xir_flush_b_in =
       | xir_flush_m[3:0];

tlu_fls_ctl_msff_ctl_macro__width_1 xir_flush_b_lat  (
	.scan_in(xir_flush_b_lat_scanin),
	.scan_out(xir_flush_b_lat_scanout),
	.din	(xir_flush_b_in			),
	.dout	(xir_flush_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// Disrupting RAS errors
//   Take disrupting RAS errors on second instruction to
// enter M to break the hardware_corrected_error loop on L2U/L2ND error
// on instruction fetch

tlu_fls_ctl_msff_ctl_macro__width_4 pre_desr_f_lat  (
	.scan_in(pre_desr_f_lat_scanin),
	.scan_out(pre_desr_f_lat_scanout),
	.din	(dfd_fls_desr_f		[3:0]	),
	.dout	(pre_desr_f		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign desr_f_in[3:0] =
       dfd_fls_desr_f[3:0] & 
       ((    pre_desr_f[3:0] &  tid_dec_m[3:0] & {4 { dec_inst_valid_m}}) |
       (         desr_f[3:0] & ~tid_dec_m[3:0]                          ) |
       (         desr_f[3:0] &                     {4 {~dec_inst_valid_m}}));

tlu_fls_ctl_msff_ctl_macro__width_4 desr_f_lat  (
	.scan_in(desr_f_lat_scanin),
	.scan_out(desr_f_lat_scanout),
	.din	(desr_f_in		[3:0]	),
	.dout	(desr_f			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 desr_s_lat  (
	.scan_in(desr_s_lat_scanin),
	.scan_out(desr_s_lat_scanout),
	.din	(dfd_fls_desr_s		[3:0]	),
	.dout	(desr_s			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign eer_err_m[3:0] =
       pre_desr_f[3:0] & desr_f[3:0] & ~desr_s[3:0] & 
       tlu_ceter_dhcce[3:0] & hpriv_bar_or_ie_m[3:0];

assign eer_err_b_in =
       | eer_err_m[3:0];

tlu_fls_ctl_msff_ctl_macro__width_1 eer_err_b_lat  (
	.scan_in(eer_err_b_lat_scanin),
	.scan_out(eer_err_b_lat_scanout),
	.din	(eer_err_b_in			),
	.dout	(eer_err_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ade_err_m[3:0] =
       pre_desr_f[3:0] & desr_f[3:0] &  desr_s[3:0] & 
       tlu_ceter_de[3:0] & hpriv_bar_or_ie_m[3:0];

assign ade_err_b_in =
       | ade_err_m[3:0];

tlu_fls_ctl_msff_ctl_macro__width_1 ade_err_b_lat  (
	.scan_in(ade_err_b_lat_scanin),
	.scan_out(ade_err_b_lat_scanout),
	.din	(ade_err_b_in			),
	.dout	(ade_err_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// Fatal errors, not (technically) disrupting, and not maskable
assign l_sbpp_in[3:0] =
       ({4 {(lsu_sbapp_err_g | lsu_sbdiou_err_g) & 
	    (thread_group == lsu_stberr_tid_g[2])}} &
        { lsu_stberr_tid_g[1] &  lsu_stberr_tid_g[0],  
	  lsu_stberr_tid_g[1] & ~lsu_stberr_tid_g[0],  
	 ~lsu_stberr_tid_g[1] &  lsu_stberr_tid_g[0],  
	 ~lsu_stberr_tid_g[1] & ~lsu_stberr_tid_g[0]}) |
       (pre_l_sbpp[3:0] & ~({4 {trl_take_ftt}} & trl_trap_taken[3:0]));

tlu_fls_ctl_msff_ctl_macro__width_4 l_sbpp_lat  (
	.scan_in(l_sbpp_lat_scanin),
	.scan_out(l_sbpp_lat_scanout),
	.din	(l_sbpp_in		[3:0]	),
	.dout	(pre_l_sbpp		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign l_sbpp_m[3:0] =
       pre_l_sbpp[3:0] & tid_dec_m[3:0] & {4 {dec_inst_valid_m}};

assign l_sbpp_b_in =
       (| l_sbpp_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 l_sbpp_b_lat  (
  	.scan_in(l_sbpp_b_lat_scanin),
  	.scan_out(l_sbpp_b_lat_scanout),
  	.din	(l_sbpp_b_in			),
  	.dout	(l_sbpp_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign ma_flush_in[3:0] =
       ({4 {spu_tlu_ma_int_req[3] & 
	(thread_group == spu_tlu_ma_int_req[2])}} &
        { spu_tlu_ma_int_req[1] &  spu_tlu_ma_int_req[0],
          spu_tlu_ma_int_req[1] & ~spu_tlu_ma_int_req[0],
         ~spu_tlu_ma_int_req[1] &  spu_tlu_ma_int_req[0],
         ~spu_tlu_ma_int_req[1] & ~spu_tlu_ma_int_req[0]}) |
       (pre_ma_flush[3:0] & ~({4 {trl_take_sma}} & trl_trap_taken[3:0]) &
	~asi_clear_spu_trap_req[3:0]);


tlu_fls_ctl_msff_ctl_macro__width_4 ma_flush_lat  (
	.scan_in(ma_flush_lat_scanin),
	.scan_out(ma_flush_lat_scanout),
	.din	(ma_flush_in			[3:0]	),
	.dout	(pre_ma_flush			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ma_flush_m[3:0] =
       pre_ma_flush[3:0] & 
       hpriv_bar_or_ie_m[3:0];

assign ma_flush_b_in =
       (| ma_flush_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 ma_flush_b_lat  (
	.scan_in(ma_flush_b_lat_scanin),
	.scan_out(ma_flush_b_lat_scanout),
	.din	(ma_flush_b_in			),
	.dout	(ma_flush_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign cwq_flush_in[3:0] =
       ({4 {spu_tlu_cwq_int_req[3] & 
        (thread_group == spu_tlu_cwq_int_req[2])}} &
        { spu_tlu_cwq_int_req[1] &  spu_tlu_cwq_int_req[0],
          spu_tlu_cwq_int_req[1] & ~spu_tlu_cwq_int_req[0],
         ~spu_tlu_cwq_int_req[1] &  spu_tlu_cwq_int_req[0],
         ~spu_tlu_cwq_int_req[1] & ~spu_tlu_cwq_int_req[0]}) |
       (pre_cwq_flush[3:0] & ~({4 {trl_take_cwq}} & trl_trap_taken[3:0]) &
	~asi_clear_spu_trap_req[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 cwq_flush_lat  (
	.scan_in(cwq_flush_lat_scanin),
	.scan_out(cwq_flush_lat_scanout),
	.din	(cwq_flush_in			[3:0]	),
	.dout	(pre_cwq_flush			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign cwq_flush_m[3:0] =
       pre_cwq_flush[3:0] & 
       hpriv_bar_or_ie_m[3:0];

assign cwq_flush_b_in =
       (| cwq_flush_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 cwq_flush_b_lat  (
	.scan_in(cwq_flush_b_lat_scanin),
	.scan_out(cwq_flush_b_lat_scanout),
	.din	(cwq_flush_b_in			),
	.dout	(cwq_flush_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign tsa_tca_ecc_error =
       asi_ece_exc | asi_eue_exc;

// No longer clear queue exceptions on taking the exception;
// have to see the head and tail the same.
// This should behave as registers outside an array.

assign check_mqr_dqr_[3:0] =
       ~(asi_check_qr_exc[3:0] & {4 {~trl_check_rqr}});
assign check_mqr_dqr[3:0] =
       ~check_mqr_dqr_[3:0];
assign check_rqr_[3:0] =
       ~(asi_check_qr_exc[3:0] & {4 {trl_check_rqr}});
assign check_rqr[3:0] =
       ~check_rqr_[3:0];

assign pmqr_exc_in[3:0] = 
       ({4 {~tsd_mrqr_exc_ & ~tsa_tca_ecc_error}} & check_mqr_dqr [3:0]) |
       (pmqr_exc[3:0]                           & check_mqr_dqr_[3:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_4 pmqr_exc_lat  ( 
	.scan_in(pmqr_exc_lat_wmr_scanin),
	.scan_out(pmqr_exc_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(pmqr_exc_in			[3:0]	),
	.dout	(pmqr_exc			[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

// Need mqr_exc active in M for disrupting_flush
// and need it in B for mqr_req
assign mqr_exc_m[3:0] =
       pmqr_exc[3:0] & hpriv_bar_and_ie[3:0] &
       (tid_dec_m[3:0] & {4 {dec_inst_valid_m}});
       
assign mqr_exc_b_in =
       (| mqr_exc_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 mqr_exc_b_lat  (
	.scan_in(mqr_exc_b_lat_scanin),
	.scan_out(mqr_exc_b_lat_scanout),
	.din	(mqr_exc_b_in			),
	.dout	(mqr_exc_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

       
assign pdqr_exc_in[3:0] = 
       ({4 {~tsd_dqr_exc_  & ~tsa_tca_ecc_error}} & check_mqr_dqr [3:0]) |
       (pdqr_exc[3:0]                           & check_mqr_dqr_[3:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_4 pdqr_exc_lat  ( 
	.scan_in(pdqr_exc_lat_wmr_scanin),
	.scan_out(pdqr_exc_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(pdqr_exc_in			[3:0]	),
	.dout	(pdqr_exc			[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

// Need dqr_exc active in M for disrupting_flush
// and need it in B for dqr_req
assign dqr_exc_m[3:0] =
       pdqr_exc[3:0] & hpriv_bar_and_ie[3:0] & 
       (tid_dec_m[3:0] & {4 {dec_inst_valid_m}});
       
assign dqr_exc_b_in =
       (| dqr_exc_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 dqr_exc_b_lat  (
	.scan_in(dqr_exc_b_lat_scanin),
	.scan_out(dqr_exc_b_lat_scanout),
	.din	(dqr_exc_b_in			),
	.dout	(dqr_exc_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

       
assign prqr_exc_in[3:0] = 
       ({4 {~tsd_mrqr_exc_ & ~tsa_tca_ecc_error}} & check_rqr     [3:0]) |
       (prqr_exc[3:0]                           & check_rqr_    [3:0]) ;

tlu_fls_ctl_msff_ctl_macro__width_4 prqr_exc_lat  ( 
	.scan_in(prqr_exc_lat_wmr_scanin),
	.scan_out(prqr_exc_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(prqr_exc_in			[3:0]	),
	.dout	(prqr_exc			[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

// Need rqr_exc active in M for disrupting_flush
// and need it in B for rqr_req
assign rqr_exc_m[3:0] =
       prqr_exc[3:0] & hpriv_bar_and_ie[3:0] & 
       (tid_dec_m[3:0] & {4 {dec_inst_valid_m}});

assign rqr_exc_b_in =
       (| rqr_exc_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 rqr_exc_b_lat  (
	.scan_in(rqr_exc_b_lat_scanin),
	.scan_out(rqr_exc_b_lat_scanout),
	.din	(rqr_exc_b_in			),
	.dout	(rqr_exc_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


tlu_fls_ctl_msff_ctl_macro__width_4 ivt_lat  (
	.scan_in(ivt_lat_scanin),
	.scan_out(ivt_lat_scanout),
	.din	(cxi_ivt			[3:0]	),
	.dout	(ivt_last			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Do not need to reinject exception on dec_flush_b because this
// only clears when the trap is taken
assign ivt_flush_in[3:0] =
       ivt_last[3:0] |
       (pre_ivt_flush[3:0] & ~asi_irl_cleared[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 ivt_flush_lat  ( 
	.scan_in(ivt_flush_lat_wmr_scanin),
	.scan_out(ivt_flush_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(ivt_flush_in		[3:0]	),
	.dout	(pre_ivt_flush		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

assign ivt_flush_m[3:0] =
       pre_ivt_flush[3:0] & 
       hpriv_bar_or_ie_m[3:0];

assign ivt_flush_b_in =
       (| ivt_flush_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 ivt_flush_b_lat  (
	.scan_in(ivt_flush_b_lat_scanin),
	.scan_out(ivt_flush_b_lat_scanout),
	.din	(ivt_flush_b_in			),
	.dout	(ivt_flush_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// Make sure these exceptions do not 'get ahead' of other disrupting exceptions
// This is not strictly required for correctness, but it makes
// verification much easier.

assign iln_exc_m[3:0] =
       trl_iln_exc[3:0] & tid_dec_m[3:0] & {4 {dec_inst_valid_m}};

assign iln_exc_b_in =
       (| iln_exc_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 iln_exc_b_lat  (
	.scan_in(iln_exc_b_lat_scanin),
	.scan_out(iln_exc_b_lat_scanout),
	.din	(iln_exc_b_in			),
	.dout	(iln_exc_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign tlz_exc_m[3:0] =
       trl_tlz_exc[3:0] & tid_dec_m[3:0] & {4 {dec_inst_valid_m}};

assign tlz_exc_b_in =
       (| tlz_exc_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 tlz_exc_b_lat  (
	.scan_in(tlz_exc_b_lat_scanin),
	.scan_out(tlz_exc_b_lat_scanout),
	.din	(tlz_exc_b_in			),
	.dout	(tlz_exc_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign hst_exc_m[3:0] =
       trl_hstick_match[3:0] & tid_dec_m[3:0] & {4 {dec_inst_valid_m}};

assign hst_exc_b_in =
       (| hst_exc_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 hst_exc_b_lat  (
	.scan_in(hst_exc_b_lat_scanin),
	.scan_out(hst_exc_b_lat_scanout),
	.din	(hst_exc_b_in			),
	.dout	(hst_exc_b			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign no_hold_disrupting_flush_in[3:0] =
	xir_flush_m[3:0] | l_sbpp_m[3:0] |
	iln_exc_m[3:0] | tlz_exc_m[3:0] | hst_exc_m[3:0] |
	ma_flush_m[3:0] | cwq_flush_m[3:0] |
	eer_err_m[3:0] | ade_err_m[3:0] |
	mqr_exc_m[3:0] | dqr_exc_m[3:0] | rqr_exc_m[3:0] | 
	ivt_flush_m[3:0] | idl_exc_in[3:0] |
        disrupting_ssc_exc[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 no_hold_disrupting_flush_lat  (
	.scan_in(no_hold_disrupting_flush_lat_scanin),
	.scan_out(no_hold_disrupting_flush_lat_scanout),
	.din	(no_hold_disrupting_flush_in	[3:0]	),
	.dout	(no_hold_disrupting_flush	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign disrupting_flush_pending[3:0] =
       no_hold_disrupting_flush[3:0];

assign disrupting_flush_pending_tid_dec_m =
       | (no_hold_disrupting_flush_in[3:0] & tid_dec_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 disrupting_flush_pending_tid_dec_b_lat  (
	.scan_in(disrupting_flush_pending_tid_dec_b_lat_scanin),
	.scan_out(disrupting_flush_pending_tid_dec_b_lat_scanout),
	.din	(disrupting_flush_pending_tid_dec_m	),
	.dout	(disrupting_flush_pending_tid_dec_b	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);
	

// Consider instruction in B valid if IFU is not flushing it
assign clear_disrupting_flush_pending[3:0] =
       disrupting_flush_pending[3:0] & tid_dec_b[3:0] & 
	{4 {pre_inst_valid_b}};

assign kill_pmu_debug_exc_b_ =
       ~(| clear_disrupting_flush_pending[3:0]);

assign kill_exc_b_ =
       kill_pmu_debug_exc_b_ & ~pmu_debug_exc_b & ~target_oor_b;

assign kill_exc_ge_7_lt_11_b_ =
       kill_pmu_debug_exc_b_ & ~pmu_debug_exc_ge_7_lt_11_b;

assign pmu_debug_exc_ge_7_lt_11_b =
       (| perf_trap_b[3:0]) | ibp_b | iaw_b | target_oor_b;

assign kill_exc_gt_6_lt_7_b_ =
       kill_pmu_debug_exc_b_ & 
       ~(| {perf_trap_b[3:0], iaw_b, target_oor_b});

assign kill_exc_lt_6_b_ =
       kill_pmu_debug_exc_b_ & ~(| {perf_trap_b[3:0], iaw_b, target_oor_b});

assign kill_exc_iar_irr_b_ =
       kill_pmu_debug_exc_b_ & ~(| {perf_trap_b[3:0], iaw_b});

assign kill_exc_iaw_b_ =
       kill_pmu_debug_exc_b_ & ~(| {perf_trap_b[3:0]});


assign disrupting_flush_b = 
	(| clear_disrupting_flush_pending[3:0]);

// Precise perf traps (precise_perf_trap_b) kills all disrupting EXCEPT
// - resets (POR, XIR), but not SIR
// - trap_level_zero
// These are handled later (by not requiring clear_disrupting_flush_pending_w)
//                 In the event of a pending disrupting trap request when
//		   LSU signals pic_overflow trap, take the disrupting trap
assign clear_disrupting_flush_pending_w_in[3:0] =
       clear_disrupting_flush_pending[3:0] & tid_dec_w_in[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 cdfpw_lat  (
	.scan_in(cdfpw_lat_scanin),
	.scan_out(cdfpw_lat_scanout),
	.l1clk	(l1clk_pm1					),
	.din	(clear_disrupting_flush_pending_w_in	[3:0]	),
	.dout	(clear_disrupting_flush_pending_w	[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// Do not suppress disrupting exceptions in the case of
// trap on control transfer exception

// Do not suppress disrupting exceptions in the case of
// any 'debug' related exception

// Suppress error register updates on DCTI couple with error on
// annulled delay slot being tagged against next instruction
assign disrupting_flush_w_in = 
       | {clear_disrupting_flush_pending[3:0] & tid_dec_w_in[3:0],
          target_oor_b, refetch_b};

tlu_fls_ctl_msff_ctl_macro__width_1 disrupting_flush_w_lat  (
	.scan_in(disrupting_flush_w_lat_scanin),
	.scan_out(disrupting_flush_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(disrupting_flush_w_in		),
	.dout	(disrupting_flush_w		),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_disrupting_flush_w =
       disrupting_flush_w;


////////////////////////////////////////////////////////////////////////////////
// Block store FRF ECC errors

// Cannot power manage this flop because block stores "stall" in  or repeat B
tlu_fls_ctl_msff_ctl_macro__width_4 block_store_w_lat  (
	.scan_in(block_store_w_lat_scanin),
	.scan_out(block_store_w_lat_scanout),
	.din	(lsu_block_store_b		[3:0]	),
	.dout	(block_store_w			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pbsee_pending_in[3:0] =
       (lsu_block_store_b[3:0] & {4 {fgu_cecc_fx2 | fgu_uecc_fx2}}) |
       (bsee_pending[3:0] & lsu_block_store_b[3:0]);

assign bsee_pending_in[3:0] = 
       pbsee_pending_in[3:0] & ~(tid_dec_m[3:0] & {4 {inst_valid_m}});

tlu_fls_ctl_msff_ctl_macro__width_4 bsee_pending_lat  (
	.scan_in(bsee_pending_lat_scanin),
	.scan_out(bsee_pending_lat_scanout),
	.din	(bsee_pending_in		[3:0]	),
	.dout	(bsee_pending			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign bsee_req_in[3:0] =
       (pbsee_pending_in[3:0] & tid_dec_m[3:0] & {4 {inst_valid_m}}) |
       (~lsu_block_store_b[3:0] & block_store_w[3:0] & bsee_pending[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 bsee_req_lat  (
	.scan_in(bsee_req_lat_scanin),
	.scan_out(bsee_req_lat_scanout),
	.din	(bsee_req_in			[3:0]	),
	.dout	(bsee_req			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign bsee_req_w_in =
       | (bsee_req_in[3:0] & tid_dec_m[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 bsee_req_w_lat  (
	.scan_in(bsee_req_w_lat_scanin),
	.scan_out(bsee_req_w_lat_scanout),
	.din	(bsee_req_w_in				),
	.dout	(bsee_req_w				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign bsee_flush_b_in =
       | (tid_dec_m[3:0] & bsee_req_in[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_1 bsee_flush_b_lat  (
	.scan_in(bsee_flush_b_lat_scanin),
	.scan_out(bsee_flush_b_lat_scanout),
	.din	(bsee_flush_b_in			),
	.dout	(bsee_flush_b				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Generate trap request:  prioritize the various requests

tlu_fls_ctl_msff_ctl_macro__width_4 core_running_lat  (
	.scan_in(core_running_lat_scanin),
	.scan_out(core_running_lat_scanout),
	.din	(tcu_core_running	[3:0]	),
	.dout	(core_running		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_core_running[3:0] =
       core_running[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 core_running_last_lat  (
	.scan_in(core_running_last_lat_scanin),
	.scan_out(core_running_last_lat_scanout),
	.din	(core_running		[3:0]	),
	.dout	(core_running_last	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_4 core_running_status_lat  (
	.scan_in(core_running_status_lat_scanin),
	.scan_out(core_running_status_lat_scanout),
	.din	(trl_core_running_status[3:0]	),
	.dout	(core_running_status	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Idle thread if core_running transitions to 0 while core_running_status is 1
// Clear idle request if core becomes idle
assign idl_exc_new[3:0] =			
       ~core_running[3:0] & core_running_last[3:0] & 
       core_running_status[3:0];
assign idl_exc_in[3:0] =
       idl_exc_new[3:0] | 
       (idl_exc[3:0] & core_running_status[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 idl_exc_lat  (
	.scan_in(idl_exc_lat_scanin),
	.scan_out(idl_exc_lat_scanout),
	.din	(idl_exc_in		[3:0]	),
	.dout	(idl_exc		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign idl_exc_b =
       | (idl_exc[3:0] & tid_dec_b[3:0]) & pre_inst_valid_b;


// dsc_req_in is purposefully NOT included here.
// The TCU should not try to park a thread that has a pending
// single step completion, so this is OK.
assign idl_req_in = 
       idl_exc_b & 
       ~rqr_req_in & 
       ~ade_req_in & ~eer_req_in & 
       ~iln_req_in & ~dqr_req_in &
       ~mqr_req_in & ~cwq_req_in & ~ma_req_in & 
       ~ivt_req_in & ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~xir_req_in & ~por_req_in &
       ~perf_trap_w_in & ~sir_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 idl_req_lat  (
	.scan_in(idl_req_lat_scanin),
	.scan_out(idl_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(idl_req_in		),
	.dout	(idl_req		),
  .siclk(siclk),
  .soclk(soclk)
);

// Resume thread if core_running transitions to 1 and thread has been in
// running state previously and is not currently running
assign res_exc[3:0] =
       core_running[3:0] & ~core_running_last[3:0] & ~{4 {ssmode}} & 
       ever_been_running[3:0] & ~core_running_status[3:0];

assign res_req[3:0] =
       res_exc[3:0] & ~{4 {domode}};

// Treat single step as special resume request
tlu_fls_ctl_msff_ctl_macro__width_1 ssmode_lat  (
	.scan_in(ssmode_lat_scanin),
	.scan_out(ssmode_lat_scanout),
	.din	(tcu_ss_mode		),
	.dout	(ssmode			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 domode_lat  (
	.scan_in(domode_lat_scanin),
	.scan_out(domode_lat_scanout),
	.din	(tcu_do_mode		),
	.dout	(domode			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 ssreq_lat  (
	.scan_in(ssreq_lat_scanin),
	.scan_out(ssreq_lat_scanout),
	.din	(tcu_ss_request		),
	.dout	(ssreq			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_ss_request =
       ssmode & ssreq;

assign ssr_exc_forces_por[3:0] =
       {4 {ssmode & ssreq}} & core_running[3:0] & ~ever_been_running[3:0];

assign ssr_exc_b[3:0] =
       ({4 {ssmode & ssreq}} & core_running[3:0]) |
       ({4 {domode & ~idl_req_in}} & (por_exc[3:0] | res_exc[3:0] | 
       (ssc_req[3:0] & tid_dec_w_in[3:0]))) | 
       ({4 {ssmode}} & idl_exc_new[3:0]);

assign ssr_req_in[3:0] =
       ssr_exc_b[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 ssr_req_lat  (
	.scan_in(ssr_req_lat_scanin),
	.scan_out(ssr_req_lat_scanout),
	.din	(ssr_req_in		[3:0]	),
	.dout	(ssr_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ever_been_running_in[3:0] =
       core_running_last[3:0] | ever_been_running[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 ever_been_running_lat  (
	.scan_in(ever_been_running_lat_scanin),
	.scan_out(ever_been_running_lat_scanout),
	.din	(ever_been_running_in	[3:0]	),
	.dout	(ever_been_running	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign por_exc[3:0] =
       core_running[3:0] & ~core_running_last[3:0] &
       ~ever_been_running[3:0];
       
assign por_req_vec_in[3:0] = 
       (por_exc[3:0] & ~{4 {ssmode}}) | ssr_exc_forces_por[3:0];

assign por_req_in =
       | (por_req_vec_in[3:0] & clear_disrupting_flush_pending[3:0]);


tlu_fls_ctl_msff_ctl_macro__width_4 por_req_lat  (
	.scan_in(por_req_lat_scanin),
	.scan_out(por_req_lat_scanout),
	.din	(por_req_vec_in	[3:0]	),
	.dout	(por_req	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign xir_req_in = 
       xir_flush_b &
       ~dec_flush_b & 
       ~dsc_req_in &
       ~por_req_in;

assign xir_request_in[3:0] = 
       {4 {xir_req_in}} & 
       clear_disrupting_flush_pending[3:0] & tid_dec_w_in[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 xir_req_lat  (
	.scan_in(xir_req_lat_scanin),
	.scan_out(xir_req_lat_scanout),
	.din	(xir_request_in	[3:0]	),
	.dout	(xir_request	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// The following are RAS errors
assign ftt_req_in =
       l_sbpp_b & 
       ~dec_flush_b & 
       ~sir_b & ~xir_req_in & 
       ~dsc_req_in & ~por_req_in;
       
assign ftt_request_in[3:0] = 
       {4 {ftt_req_in}} & 
       clear_disrupting_flush_pending[3:0] & tid_dec_w_in[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 ftt_req_lat  (
	.scan_in(ftt_req_lat_scanin),
	.scan_out(ftt_req_lat_scanout),
	.din	(ftt_request_in	[3:0]	),
	.dout	(ftt_request	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ade_req_in = 
       ade_err_b &
       ~dec_flush_b & 
       ~iln_req_in & ~dqr_req_in & 
       ~mqr_req_in & ~cwq_req_in & ~ma_req_in & 
       ~ivt_req_in & ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 ade_req_lat  (
	.scan_in(ade_req_lat_scanin),
	.scan_out(ade_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(ade_req_in		),
	.dout	(ade_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign eer_req_in = 
       eer_err_b &
       ~dec_flush_b & 
       ~ade_req_in & 
       ~iln_req_in & ~dqr_req_in & 
       ~mqr_req_in & ~cwq_req_in & ~ma_req_in & 
       ~ivt_req_in & ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;


tlu_fls_ctl_msff_ctl_macro__width_1 eer_req_lat  (
	.scan_in(eer_req_lat_scanin),
	.scan_out(eer_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(eer_req_in		),
	.dout	(eer_req		),
  .siclk(siclk),
  .soclk(soclk)
);

// The previous were RAS errors

assign ivt_req_in = 
       ivt_flush_b & 
       ~dec_flush_b & 
       ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 ivt_req_lat  (
	.scan_in(ivt_req_lat_scanin),
	.scan_out(ivt_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(ivt_req_in		),
	.dout	(ivt_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign ma_req_in = 
       ma_flush_b & 
       ~dec_flush_b & 
       ~ivt_req_in & 
       ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 ma_req_lat  (
	.scan_in(ma_req_lat_scanin),
	.scan_out(ma_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(ma_req_in		),
	.dout	(ma_req			),
  .siclk(siclk),
  .soclk(soclk)
);

assign cwq_req_in = 
       cwq_flush_b & 
       ~dec_flush_b & 
       ~ma_req_in & ~ivt_req_in & 
       ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 cwq_req_lat  (
	.scan_in(cwq_req_lat_scanin),
	.scan_out(cwq_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(cwq_req_in		),
	.dout	(cwq_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign mqr_req_in = 
       mqr_exc_b & 
       ~dec_flush_b & 
       ~cwq_req_in & ~ma_req_in & ~ivt_req_in & 
       ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 mqr_req_lat  (
	.scan_in(mqr_req_lat_scanin),
	.scan_out(mqr_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(mqr_req_in		),
	.dout	(mqr_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign dqr_req_in = 
       dqr_exc_b & 
       ~dec_flush_b & 
       ~mqr_req_in & ~cwq_req_in & ~ma_req_in & 
       ~ivt_req_in & ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 dqr_req_lat  (
	.scan_in(dqr_req_lat_scanin),
	.scan_out(dqr_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(dqr_req_in		),
	.dout	(dqr_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign rqr_req_in = 
       rqr_exc_b & 
       ~dec_flush_b & 
       ~iln_req_in & ~dqr_req_in & 
       ~mqr_req_in & ~cwq_req_in & ~ma_req_in & 
       ~ivt_req_in & ~tlz_req_in & ~hst_req_in &
       ~ade_req_in & ~eer_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 rqr_req_lat  (
	.scan_in(rqr_req_lat_scanin),
	.scan_out(rqr_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(rqr_req_in		),
	.dout	(rqr_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign iln_req_in =
       iln_exc_b &
       ~dec_flush_b & 
       ~dqr_req_in & 
       ~mqr_req_in & ~cwq_req_in & ~ma_req_in & 
       ~ivt_req_in & ~tlz_req_in & ~hst_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in & 
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 iln_req_lat  (
	.scan_in(iln_req_lat_scanin),
	.scan_out(iln_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(iln_req_in		),
	.dout	(iln_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign hst_req_in =
       hst_exc_b & 
       ~dec_flush_b & 
       ~tlz_req_in & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in &
       ~perf_trap_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 hst_req_lat  (
	.scan_in(hst_req_lat_scanin),
	.scan_out(hst_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(hst_req_in		),
	.dout	(hst_req		),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlz_req_in = 
       tlz_exc_b &
       ~dec_flush_b & 
       ~ftt_req_in & ~sir_b & ~xir_req_in & ~dsc_req_in & ~por_req_in;

assign tlz_request_in[3:0] = 
       {4 {tlz_req_in}} & 
       clear_disrupting_flush_pending[3:0] & tid_dec_w_in[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 tlz_req_lat  (
	.scan_in(tlz_req_lat_scanin),
	.scan_out(tlz_req_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(tlz_request_in	[3:0]	),
	.dout	(tlz_request	[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// Single step completion does not require a flush or gating from other
// exceptions
// Need to reset ssc_req_in in domode when G exceptions occur
// Or for exceptions on second cycle of twocycle instructions in domode
// Or for exceptions on second through eighth beats of block store in domode
assign ssc_req_in[3:0] = 
       (trl_ssc_exc[3:0] |
	((flush_gfb[3:0] | m_dae_req_w[3:0] |
	  (two_tid_dec_w[3:0] & {4 {e_f_ecc_w}}) |
          bsee_req[3:0] | pdist_ecc_w[3:0]) & {4 {domode}}) |
        ssc_req[3:0]) & 
       ~(tid_dec_w[3:0] & ~flush_ifu[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 ssc_req_lat  (
	.scan_in(ssc_req_lat_scanin),
	.scan_out(ssc_req_lat_scanout),
	.din	(ssc_req_in	[3:0]	),
	.dout	(ssc_req	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// There are certain cases for which we want to create a
// disrupting exception so that the 'next' instruction will be flushed
// and we can signal the completion
// This is the 'highest priority' disrupting or reset exception behind
// POR because it's really for the 'last' instruction
//
// tcu_ss_request	  x		x
// trl_trap_taken[n]	    x 		  x		x
// dec_inst_valid_m	      x		    x		  x
// ssc_req (precise)	        x
// flush_ifu				      x		    x
// disrupting_ssc_exc			       xxxxxxxxxxxxxx
// disrupting_ssc_req					    x
//
// suppress_d_s_e         xxxxxxx       xxxx
//
// But we don't want to do this on hardware tablewalks.  We want to let the
// tablewalk proceed without interruption, and want to stop after the 
// instruction with the hardware tablewalk.
//
// Also need to set disrupting_ssc_exc for late exceptions
// But have to suppress disrupting_ssc_req for late exceptions

assign disrupting_ssc_exc_in[3:0] =
       {4 {ssmode}} & 
        ((flush_ifu[3:0] & tid_dec_w[3:0] & ~disrupting_ssc_exc[3:0] & 
          ~idl_request[3:0] & ~iht_request[3:0] & ~dht_request[3:0]) |
         flush_gfb[3:0] | 
         hwtw_exception[3:0] |
         (two_tid_dec_w[3:0] & {4 {e_f_ecc_w}}) |
         bsee_req[3:0] | pdist_ecc_w[3:0] |
         (disrupting_ssc_exc[3:0] & ~disrupting_ssc_req[3:0]));

tlu_fls_ctl_msff_ctl_macro__width_4 disrupting_ssc_exc_lat  (
	.scan_in(disrupting_ssc_exc_lat_scanin),
	.scan_out(disrupting_ssc_exc_lat_scanout),
	.din	(disrupting_ssc_exc_in	[3:0]	),
	.dout	(disrupting_ssc_exc	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign dsc_req_in =
       | (disrupting_ssc_exc[3:0] & clear_disrupting_flush_pending[3:0]);

assign disrupting_ssc_req[3:0] =
       disrupting_ssc_exc[3:0] & flush_ifu[3:0] & ~por_req[3:0] & 
       ~(flush_gfb[3:0] | m_dae_req_w[3:0] |
         bsee_req[3:0] | pdist_ecc_w[3:0]);


//////////////////////////////////////////////////////////////////////////////
// Requests to trap redirect logic
//

assign fls_ssc_request[3:0] =
       (ssc_req[3:0] & tid_dec_w[3:0] & ~flush_ifu[3:0]) | 
       disrupting_ssc_req[3:0];

assign fls_ssr_request[3:0] =
       ssr_req[3:0];

assign fls_res_request[3:0] =
       res_req[3:0];

// Nonsequential NPC after retry (or taken branch after retry)
assign fls_nns_request[3:0] =
       nns_to_pc_w[3:0] & {4 {~(domode | ssmode)}};

assign fls_por_request[3:0] =  
       por_req[3:0];

assign fls_xir_request[3:0] =
       xir_request[3:0];

assign fls_tlz_request[3:0] = 
       tlz_request[3:0];

assign fls_hst_request[3:0] = 
       {4 {hst_req}} & 
       clear_disrupting_flush_pending_w[3:0];

assign fls_ivt_request[3:0] = 
       {4 {ivt_req}} & 
       clear_disrupting_flush_pending_w[3:0];

assign fls_sma_request[3:0] =
       {4 {ma_req}} & 
       clear_disrupting_flush_pending_w[3:0];

assign fls_cwq_request[3:0] =
       {4 {cwq_req}} & 
       clear_disrupting_flush_pending_w[3:0];

// CPU mondo trap request
assign fls_mqr_request[3:0] =
       {4 {mqr_req}} &
       clear_disrupting_flush_pending_w[3:0];

// Device mondo trap request
assign fls_dqr_request[3:0] =
       {4 {dqr_req}} & 
       clear_disrupting_flush_pending_w[3:0];

assign fls_iln_request[3:0] = 
       {4 {iln_req}} & 
       clear_disrupting_flush_pending_w[3:0];

assign fls_rqr_request[3:0] = 
       {4 {rqr_req}} &
       clear_disrupting_flush_pending_w[3:0];

assign fls_ade_request[3:0] = 
       {4 {ade_req}} & 
       clear_disrupting_flush_pending_w[3:0];

// Idle lower than all other exceptions so that the other exceptions are not
// lost
assign idl_request[3:0] =
       {4 {idl_req}} & 
       clear_disrupting_flush_pending_w[3:0];

assign fls_idl_request[3:0] =
       idl_request[3:0];

assign fls_sir_request[3:0] = 
       {4 {sir_w}} & tid_dec_w[3:0];

tlu_fls_ctl_msff_ctl_macro__width_4 hw_tw_enabled_lat  (
	.scan_in(hw_tw_enabled_lat_scanin),
	.scan_out(hw_tw_enabled_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(mmu_hw_tw_enable	[3:0]	),
	.dout	(hw_tw_enabled		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign hw_tw_disabled[3:0] = 
       ~hw_tw_enabled[3:0];

assign itm_request[3:0] = 
       {4 {itlb_miss_w}} & tid_dec_w[3:0];

assign fls_itm_request[3:0] =
       (itm_request[3:0] & hw_tw_disabled[3:0]);

assign iht_request[3:0] =
       itm_request[3:0] & hw_tw_enabled[3:0];

assign tlu_iht_request[3:0] =
       iht_request[3:0];

assign load_i_tag_access_in =
       itlb_priv_exc_w_in | itlb_nfo_exc_w_in | i_oor_va_w_in | itlb_err_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 load_i_tag_access_lat  (
	.scan_in(load_i_tag_access_lat_scanin),
	.scan_out(load_i_tag_access_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(load_i_tag_access_in	),
	.dout	(load_i_tag_access_pre	),
  .siclk(siclk),
  .soclk(soclk)
);

assign load_i_tag_access[3:0] =
       itm_request[3:0] | 
       ({4 {load_i_tag_access_pre}} & tid_dec_w[3:0]);

assign fls_iae_request[3:0] = 
       ({4 {i_l2_unde_w}} & tid_dec_w[3:0]); 

assign ipe_request[3:0] =
       ({4 {e_f_ecc_w}} & two_tid_dec_w[3:0]) |
       bsee_req[3:0] | asi_ecc_w[3:0] | l_sbdl_ecc_w[3:0] | 
       pdist_ecc_w[3:0];

assign fls_ipe_request[3:0] =
       ipe_request[3:0];

assign fls_ipv_request =
       itlb_priv_exc_w;

assign fls_inp_request =
       itlb_nfo_exc_w;

assign fls_iar_request =
       i_oor_va_w;

assign fls_irr_request =
       i_ra_oor_va_w;

assign fls_mar_request =
       br_ld_oor_va_w;

assign fls_mrr_request =
       br_ld_ra_oor_va_w;

assign fls_pro_request =
       priv_exc_w;

// hyperprivileged exceptions cause
// illegal instruction traps
assign fls_ill_request = 
       illegal_inst_w | hpriv_exc_w;

assign fls_don_request = 
       done_inst_w;

assign fls_ret_request = 
       retry_inst_w;

assign fls_fpd_request = 
       fpdisable_exc_w;

assign fls_snn_request = 
       snn_w;

assign fls_sno_request = 
       sno_w;

assign fls_fnn_request = 
       fnn_w;

assign fls_fno_request = 
       fno_w;

assign fls_clw_request = 
       clw_w;

assign dtm_request[3:0] = 
       {4 {dtlb_miss_w}} & tid_dec_w[3:0];

assign fls_dtm_request[3:0] =
       dtm_request[3:0] & hw_tw_disabled[3:0];

assign dht_request[3:0] =
       dtm_request[3:0] & hw_tw_enabled[3:0];

assign tlu_dht_request[3:0] =
       dht_request[3:0];

assign load_d_tag_access_in =
       dae_priv_viol_w_in | dae_nc_page_w_in | 
       dae_nfo_page_w_in | dae_so_page_w_in | daccess_prot_w_in |
       dtlb_error_w_in;

tlu_fls_ctl_msff_ctl_macro__width_1 load_d_tag_access_lat  (
	.scan_in(load_d_tag_access_lat_scanin),
	.scan_out(load_d_tag_access_lat_scanout),
	.l1clk	(l1clk_pm1		),
	.din	(load_d_tag_access_in	),
	.dout	(load_d_tag_access	),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_load_d_tag_access[3:0] = 
       dtm_request[3:0] | 
       ({4 {load_d_tag_access & ~l_real_w}} & tid_dec_w[3:0]);

assign fls_ldf_request = 
       lddf_align_w;

assign fls_stf_request = 
       stdf_align_w;

assign fls_dap_request =
       daccess_prot_w;

assign vaw_request[3:0] = 
       {4 {va_watchpoint_w}} & tid_dec_w[3:0];

assign fls_vaw_request = 
       va_watchpoint_w;

assign iaw_request[3:0] = 
       {4 {iaw_w}} & tid_dec_w[3:0];

assign fls_iaw_request = 
       iaw_w; 

assign paw_request[3:0] = 
       {4 {pa_watchpoint_w}} & tid_dec_w[3:0];

assign fls_paw_request = 
       pa_watchpoint_w; 

assign fls_maa_request = 
       align_w | e_misalign_w;

assign fls_fpe_request = 
       f_predict_w;
	
assign fls_fei_request[3:0] = 
       ieee_exc_fw[3:0];
	
assign fls_fof_request[3:0] = 
       unfin_fw[3:0];

assign fls_pra_request[3:0] = 
       ({4 {priv_action_w}} & tid_dec_w[3:0]) | priv_action_g_w[3:0]; 

assign fls_dia_request = 
       dae_invalid_asi_w;

assign fls_ups_request[3:0] = 
       m_dae_req_w[3:0];  
	
assign fls_dnc_request = 
       dae_nc_page_w;
	
assign fls_dnf_request = 
       dae_nfo_page_w;
	
assign fls_dpv_request = 
       dae_priv_viol_w;
	
assign fls_dso_request = 
       dae_so_page_w;
	
assign fls_tof_request = 
       tof_w;
	
assign fls_dbz_request[3:0] = 
       idiv0_exc_fw[3:0];
	
assign fls_tcc_request = 
       tcc_w;

assign fls_dae_request[3:0] = 
       l_l2_ecc_w[3:0];

assign irt_request[3:0] = 
       {4 {ra_itlb_miss_w}} & tid_dec_w[3:0];

assign i_real_w[3:0] =
       ~itlb_bypass[3:0] & ~immu_enable[3:0];

assign load_i_tag_access_r[3:0] = 
       ({4 {i_ra_oor_va_w}} & tid_dec_w[3:0]) | irt_request[3:0];

assign tlu_load_i_tag_access_p[3:0] =
       load_i_tag_access[3:0] &  tl_eq_0[3:0] & ~i_real_w[3:0];

assign tlu_load_i_tag_access_n[3:0] =
       (load_i_tag_access[3:0] & ~tl_eq_0[3:0]) | 
       (load_i_tag_access[3:0] & i_real_w[3:0]) | 
       load_i_tag_access_r[3:0];

assign fls_irt_request =
       ra_itlb_miss_w;

assign drt_request[3:0] = 
       {4 {ra_dtlb_miss_w}} & tid_dec_w[3:0];

assign tlu_load_d_tag_access_r[3:0] = 
       drt_request[3:0] | 
       ({4 {load_d_tag_access & l_real_w}} & tid_dec_w[3:0]);

assign fls_drt_request =
       ra_dtlb_miss_w;

assign fls_pmu_request[3:0] = 
       ({4 {perf_trap_w | precise_perf_trap_w}} & tid_dec_w[3:0]) | 
       precise_perf_trap_g_w[3:0];

assign pre_lsr_request[3:0] =
       (nns_to_npc_w[3:0] | trap_flush[3:0]) & {4 {~(domode | ssmode)}};

assign fls_lsr_request[3:0] =
       ~(~pre_lsr_request[3:0] | ipe_request[3:0]);

assign fls_ime_request[3:0] =
       ime_w[3:0] |
       ({4 {itlb_err_w}} & tid_dec_w[3:0]);

assign fls_dme_request[3:0] =
       dme_w[3:0] |
       ({4 {dtlb_error_w}} & tid_dec_w[3:0]);

assign fls_eer_request[3:0] =
       {4 {eer_req}} & clear_disrupting_flush_pending_w[3:0];

assign fls_icp_request = 
       icp_req;
	
assign fls_ftt_request[3:0] =
       ftt_request[3:0];

assign ibp_request[3:0] = 
       {4 {ibp_w}} & tid_dec_w[3:0];

assign fls_ibp_request = 
       ibp_w;

assign tct_request[3:0] = 
       {4 {tct_w}} & tid_dec_w[3:0];

assign fls_tct_request = 
       tct_w;

assign fls_ref_request =
       refetch_w;

assign fls_ipe_dme_request =
       ((e_f_ecc_w | dtlb_error_w) & (| two_tid_dec_w[3:0])) | 
       (| bsee_req[3:0]) | (| pdist_ecc_w[3:0]);

assign fls_load_dsfar[3:0] =
       ({4 {align_w | e_misalign_w | dae_invalid_asi_w | dae_priv_viol_w |
	    dae_nc_page_w | dae_nfo_page_w | dae_so_page_w | 
	    br_ld_oor_va_w | br_ld_ra_oor_va_w | 
            daccess_prot_w | pa_watchpoint_w |
	    va_watchpoint_w |
            lddf_align_w | stdf_align_w}} & tid_dec_w[3:0]); 


// If a
// branch that annuls its own delay slot that is in the delay slot of
// another branch 
// precedes an instruction with 
// a pre-icache exception, then that instruction will
// cause an instruction cache parity
// microarchitectural trap (icp).  Note that the disrupting exception is
// NOT posted, so no trap will be taken later.  
// This solution does cause
// the instruction cache line to be invalidated for no reason.

// First, capture that a branch in a delay slot has annulled its own delay slot

assign m103663_in[3:0] =
       ( tid_dec_w_in[3:0] & {4 {annul_ds_b & ~br_taken_b}}) | 
       (~tid_dec_w_in[3:0] & m103663[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 m103663_lat  (
	.scan_in(m103663_lat_scanin),
	.scan_out(m103663_lat_scanout),
	.din	(m103663_in	[3:0]	),
	.dout	(m103663	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Then generate exception and gate off the pre-icache exceptions
// This needs to be tid_dec_b to be fast, but the hold latch needs tid_dec_w_in
// to hold through dec_flush_b situations
// Have to gate off this exception in the absence of valid
assign m103663_exc_b =
       (| (m103663[3:0] & tid_dec_b[3:0])) & pre_inst_valid_b;

// i_oor_va_b and i_ra_oor_va_b not needed because these would not occur
// before the boundary.  IFU doesn't detect branches into VA hole; EXU
// and TLU do.
assign refetch_b = 
       m103663_exc_b & 
       (itlb_miss_b | ra_itlb_miss_b | itlb_priv_exc_b | itlb_nfo_exc_b |
	i_l2_unde_b | itlb_err_b | ic_err_b) ;

assign refetch_w_in =
       refetch_b & kill_exc_lt_6_b_;

tlu_fls_ctl_msff_ctl_macro__width_1 refetch_w_lat  (
	.scan_in(refetch_w_lat_scanin),
	.scan_out(refetch_w_lat_scanout),
	.din	(refetch_w_in		),
	.dout	(refetch_w		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Save CWP on flush

assign cwp3_in[2:0] =
        ({3 { flush_ifu[3]}} & exu_cwp3[2:0]) | 
	({3 {~flush_ifu[3]}} & cwp3[2:0]);
assign cwp2_in[2:0] =
        ({3 { flush_ifu[2]}} & exu_cwp2[2:0]) | 
	({3 {~flush_ifu[2]}} & cwp2[2:0]);
assign cwp1_in[2:0] =
        ({3 { flush_ifu[1]}} & exu_cwp1[2:0]) | 
	({3 {~flush_ifu[1]}} & cwp1[2:0]);
assign cwp0_in[2:0] =
        ({3 { flush_ifu[0]}} & exu_cwp0[2:0]) | 
	({3 {~flush_ifu[0]}} & cwp0[2:0]);

tlu_fls_ctl_msff_ctl_macro__width_12 cwp_lat  ( 
	.scan_in(cwp_lat_wmr_scanin),
	.scan_out(cwp_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	({cwp3_in	[2:0],
		  cwp2_in	[2:0],
		  cwp1_in	[2:0],
		  cwp0_in	[2:0]}),
	.dout	({cwp3		[2:0],
		  cwp2		[2:0],
		  cwp1		[2:0],
		  cwp0		[2:0]}),
  .l1clk(l1clk),
  .soclk(soclk)
);

assign fls_cwp3[2:0] =
       cwp3[2:0];
assign fls_cwp2[2:0] =
       cwp2[2:0];
assign fls_cwp1[2:0] =
       cwp1[2:0];
assign fls_cwp0[2:0] =
       cwp0[2:0];


////////////////////////////////////////////////////////////////////////////////
//
// Manage PC, NPC
//
// Terminology:  a taken branch will not have an exception
assign tid_dec_valid_b[3:0] =
       tid_dec_b[3:0] & {4 {inst_valid_b}};

// Sequential flow 
//   or 
// branch not taken that annuls the delay slot that itself is in a delay slot
//   or 
// branch taken and NPC is invalid
// In pct, pc_sel_npc_plus_4 is prioritized over pc_sel_npc
assign fls_pc_sel_npc[3:0] =
       (pc_valid[3:0] | {4 {br_taken_b | annul_ds_b}}) & 
       tid_dec_valid_b[3:0];
	

// Branch taken and NPC is valid 
//   or 
// branch not taken that annuls the delay slot that is not in a delay slot
assign pc_sel_npc_plus_4[3:0] =
       npc_valid[3:0] & {4 {br_taken_b | (annul_ds_b & ~ds_b)}} & 
       tid_dec_valid_b[3:0];

assign fls_pc_sel_npc_plus_4[3:0] =
       pc_sel_npc_plus_4[3:0];


// Sequential flow or 
// first instruction (with or without exception) after done 
//   or 
// branch not taken that annuls the delay slot that itself is in a delay slot 
//   or 
// branch not taken that annuls delay slot that's not in a delay slot w/npc inv
// In pct, npc_sel_target and npc_sel_npc_plus_8 are prioritized over 
// npc_sel_npc_plus_4
assign fls_npc_sel_npc_plus_4[3:0] =
       ((npc_valid[3:0] & {4 {~annul_ds_b}}) | {4 {annul_ds_b}}) & 
       tid_dec_valid_b[3:0]; 

// Branch not taken that annuls the delay slot that is not in a delay slot
// In pct, npc_sel_target is prioritized over npc_sel_npc_plus_8
assign fls_npc_sel_npc_plus_8[3:0] =
       npc_valid[3:0] & {4 {annul_ds_b & ~ds_b}} &
       tid_dec_valid_b[3:0];

// Taken branch that does not have exception
assign fls_npc_sel_target[3:0] =
       {4 {br_taken_b}} & tid_dec_valid_b[3:0];


// PC becomes valid whenever instruction comes down pipe and that instruction
// is not 
//   a taken branch that does not annul the delay slot
//   an instruction that is being flushed due to idle exception
// PC is invalidated on trap, done, retry
assign prevent_valid =
       (br_taken_b & ~annul_ds_b) | disrupting_flush_b | pmu_debug_exc_b | 
       refetch_b;

// A flushed instruction should not affect PC valids
// (Flushes prevent updates to pc_?_w registers in PCT)
assign inst_b[3:0] =
       tid_dec_valid_b[3:0] & {4 {~dec_flush_b}};

assign pc_valid_in[3:0] =
       ( inst_b[3:0] & ~{4 {prevent_valid}}) |
       (~inst_b[3:0] & pc_valid[3:0] & ~trl_invalidate_pc[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 pc_valid_lat  (
	.scan_in(pc_valid_lat_scanin),
	.scan_out(pc_valid_lat_scanout),
	.din	(pc_valid_in		[3:0]	),
	.dout	(pc_valid		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_pc_valid[3:0] =
       pc_valid[3:0];


// NPC becomes valid whenever instruction comes down pipe and that instruction
// is not
//   a taken branch that does not annul the delay slot
//   an instruction that is being flushed due to idle exception
// NPC is invalidated on trap and retry (valid on done to calculate real NPC)
assign npc_valid_in[3:0] =
       ( inst_b[3:0] & ~{4 {prevent_valid}}) |
       (~inst_b[3:0] & npc_valid[3:0] & ~trl_invalidate_npc[3:0]);

tlu_fls_ctl_msff_ctl_macro__width_4 npc_valid_lat  (
	.scan_in(npc_valid_lat_scanin),
	.scan_out(npc_valid_lat_scanout),
	.din	(npc_valid_in		[3:0]	),
	.dout	(npc_valid		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign npc_is_valid = 
       (| (tid_dec_b[3:0] & npc_valid[3:0])) & inst_valid_b;

assign fls_npc_b_sel_npc =
       ~npc_is_valid;


// PC is actually NPC if
//   inst is taken branch that does not annul delay slot that is not in a delay
//     slot itself
//   inst is after done, retry, or trap
// In the case of a delay slot that's annulled, we want to know
//  the NPC of the delay slot, not the branch.  In this case, the NPC of the
//  delay slot is in the NPC flop, so the PC is not the NPC (that we want).
// If a branch in the delay slot of another branch is at decode 
//  (signified by dec_inst_cnt[01:00] being nonzero), then the PC is no longer 
//  the NPC.  Handled in tlu_pct_dp
assign pc_is_npc_in[3:0] =
       (inst_b[3:0] & {4 { br_taken_b & ~annul_ds_b}}) |
       trl_invalidate_pc[3:0] |
       (pc_is_npc[3:0] & ~inst_b[3:0]); 

tlu_fls_ctl_msff_ctl_macro__width_4 pc_is_npc_lat  (
	.scan_in(pc_is_npc_lat_scanin),
	.scan_out(pc_is_npc_lat_scanout),
	.din	(pc_is_npc_in		[3:0]	),
	.dout	(pc_is_npc		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_pc_is_npc =
       | (pc_is_npc[3:0] & tid_dec_d[3:0]);


//////////////////////////////////////////////////////////////////////////////
//
// Implement adder for lower two bits of NPC at D
//

// Need to mux NPC down to by thread group
assign pre_npc_d[3:2] =        
       ({2 {tid_dec_d[0]}} & pct_npc_0_w[3:2]) |
       ({2 {tid_dec_d[1]}} & pct_npc_1_w[3:2]) |
       ({2 {tid_dec_d[2]}} & pct_npc_2_w[3:2]) |
       ({2 {tid_dec_d[3]}} & pct_npc_3_w[3:2]) ;

assign pre_npc_d[4] =
       1'b0;

// Need to select inst_cnt minus one when a branch in the delay slot of
//  another branch is at decode, because the PC of the instruction after the 
//  branch (which is at D and in the delay slot) is in the NPC register
assign sel_inst_cnt_m_1 = 
       | (pc_is_npc[3:0] & ~npc_valid[3:0] & tid_dec_d[3:0]);


// Precalculate possible outcomes and then mux them
// dec_inst_cnt	sel_inst_cnt_m1		npc_inc_d = pre_npc_d + ?
//	00		1			0
//	00		0			0
//	01		1			0
//	01		0			1
//	10		1			1
//	10		0			2
//	11		1			2
//	11		0			3

assign npc_plus_0[4:2] =
       pre_npc_d[4:2];

assign npc_plus_1[4:2] =
       pre_npc_d[4:2] + 3'b001;

assign npc_plus_2[4:2] =
       pre_npc_d[4:2] + 3'b010;

assign npc_plus_3[4:2] =
       pre_npc_d[4:2] + 3'b011;


assign fls_npc_if_cnt_eq_1_d[4:2] =
       ({3 { sel_inst_cnt_m_1}} & npc_plus_0[4:2]) |
       ({3 {~sel_inst_cnt_m_1}} & npc_plus_1[4:2]) ;

assign fls_npc_if_cnt_eq_2_d[4:2] =
       ({3 { sel_inst_cnt_m_1}} & npc_plus_1[4:2]) |
       ({3 {~sel_inst_cnt_m_1}} & npc_plus_2[4:2]) ;

assign fls_npc_if_cnt_eq_3_d[4:2] =
       ({3 { sel_inst_cnt_m_1}} & npc_plus_2[4:2]) |
       ({3 {~sel_inst_cnt_m_1}} & npc_plus_3[4:2]) ;


//////////////////////////////////////////////////////////////////////////////
//
//  tlu_pct_dp power management
//

assign fls_pct_pc_en[3:0] =
       trl_pc_sel_trap_pc[3:0] | (tid_dec_b[3:0] & {4 {pre_inst_valid_b}});

assign fls_pct_npc_en[3:0] =
       trl_fls_npc_en[3:0] | (tid_dec_b[3:0] & {4 {pre_inst_valid_b}});


//////////////////////////////////////////////////////////////////////////////
//
//  Debug event control register processing
//

tlu_fls_ctl_msff_ctl_macro__width_4 debug_event_lat  (
	.scan_in(debug_event_lat_scanin),
	.scan_out(debug_event_lat_scanout),
	.din	(pmu_tlu_debug_event		[3:0]	),
	.dout	(debug_event			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign softstop_req_in =
       | (
	({4 {asi_decr[63:62] == 2'b01}} & ibp_request		[3:0]) |
	({4 {asi_decr[61:60] == 2'b01}} & iaw_request		[3:0]) |
	({4 {asi_decr[59:58] == 2'b01}} & vaw_request		[3:0]) |
	({4 {asi_decr[57:56] == 2'b01}} & paw_request		[3:0]) |
	({4 {asi_decr[55:54] == 2'b01}} & tct_request		[3:0]) |
	({4 {asi_decr[53:52] == 2'b01}} & ras_precise_error	[3:0]) |
	({4 {asi_decr[51:50] == 2'b01}} & ras_disrupting_error	[3:0]) |
	({4 {asi_decr[49:48] == 2'b01}} & ras_deferred_error	[3:0]) |
	({4 {asi_decr[47:46] == 2'b01}} & debug_event		[3:0]) );

assign hardstop_req_in =
       | (
	({4 {asi_decr[63:62] == 2'b10}} & ibp_request		[3:0]) |
	({4 {asi_decr[61:60] == 2'b10}} & iaw_request		[3:0]) |
	({4 {asi_decr[59:58] == 2'b10}} & vaw_request		[3:0]) |
	({4 {asi_decr[57:56] == 2'b10}} & paw_request		[3:0]) |
	({4 {asi_decr[55:54] == 2'b10}} & tct_request		[3:0]) |
	({4 {asi_decr[53:52] == 2'b10}} & ras_precise_error	[3:0]) |
	({4 {asi_decr[51:50] == 2'b10}} & ras_disrupting_error	[3:0]) |
	({4 {asi_decr[49:48] == 2'b10}} & ras_deferred_error	[3:0]) |
	({4 {asi_decr[47:46] == 2'b10}} & debug_event		[3:0]) );

assign pulse_req_in =
       | (
	({4 {asi_decr[63:62] == 2'b11}} & ibp_request		[3:0]) |
	({4 {asi_decr[61:60] == 2'b11}} & iaw_request		[3:0]) |
	({4 {asi_decr[59:58] == 2'b11}} & vaw_request		[3:0]) |
	({4 {asi_decr[57:56] == 2'b11}} & paw_request		[3:0]) |
	({4 {asi_decr[55:54] == 2'b11}} & tct_request		[3:0]) |
	({4 {asi_decr[53:52] == 2'b11}} & ras_precise_error	[3:0]) |
	({4 {asi_decr[51:50] == 2'b11}} & ras_disrupting_error	[3:0]) |
	({4 {asi_decr[49:48] == 2'b11}} & ras_deferred_error	[3:0]) |
	({4 {asi_decr[47:46] == 2'b11}} & debug_event		[3:0]) );

tlu_fls_ctl_msff_ctl_macro__width_1 softstop_req_lat  (
	.scan_in(softstop_req_lat_scanin),
	.scan_out(softstop_req_lat_scanout),
	.din	(softstop_req_in			),
	.dout	(softstop_req				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 hardstop_req_lat  (
	.scan_in(hardstop_req_lat_scanin),
	.scan_out(hardstop_req_lat_scanout),
	.din	(hardstop_req_in			),
	.dout	(hardstop_req				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_fls_ctl_msff_ctl_macro__width_1 pulse_req_lat  (
	.scan_in(pulse_req_lat_scanin),
	.scan_out(pulse_req_lat_scanout),
	.din	(pulse_req_in				),
	.dout	(pulse_req				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fls_spc_softstop_request =
	softstop_req;
assign fls_spc_hardstop_request =
	hardstop_req;
assign fls_spc_trigger_pulse =
	pulse_req;


//////////////////////////////////////////////////////////////////////////////
//
//  Core instruction signature
//

// 00 : instruction non commited
// 01 : Control Transfer instruction commited in pipe
// 10 : Integer or FPU instruction commited in pipe
// 11 : Ld/Store instruction commited in pipe
assign instr_cmt_grp_in[1:0] =
       {2 {inst_valid_w & ~(| (flush_ifu[3:0] & tid_dec_w[3:0]))}} &
       {~cti_w, cti_w | lsu_inst_w};

tlu_fls_ctl_msff_ctl_macro__width_2 instr_cmt_grp_lat  (
	.scan_in(instr_cmt_grp_lat_scanin),
	.scan_out(instr_cmt_grp_lat_scanout),
	.din	(instr_cmt_grp_in		[1:0]	),
	.dout	(instr_cmt_grp			[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_dbg_instr_cmt_grp[1:0] =
       instr_cmt_grp[1:0];
 

//////////////////////////////////////////////////////////////////////////////
//
//  Tag access register power management
//

assign tlu_tag_access_tid_b[1:0] =
       tid_b[1:0];

assign tlu_i_tag_access_b =
       itlb_miss_b | ra_itlb_miss_b | itlb_priv_exc_b | itlb_nfo_exc_b | 
       i_oor_va_b | i_ra_oor_va_b | itlb_err_b | target_oor_b;

assign tlu_d_tag_access_b =
       lsu_inst_b;


//////////////////////////////////////////////////////////////////////////////
//
// Shadow scan control for PC
//

assign fls_ss_update_pc_w =
       (trl_shscanid[2] == thread_group) &
       (( trl_shscanid[1] &  trl_shscanid[0] & tid_dec_w_in[3]) |
	( trl_shscanid[1] & ~trl_shscanid[0] & tid_dec_w_in[2]) |
	(~trl_shscanid[1] &  trl_shscanid[0] & tid_dec_w_in[1]) |
	(~trl_shscanid[1] & ~trl_shscanid[0] & tid_dec_w_in[0]) );


//////////////////////////////////////////////////////////////////////////////
//
// Spares
//


assign m114419_nor3_0[3:0] =
       ~(pre_xir_flush[3:0] | pre_desr_f[3:0] | pre_l_sbpp[3:0]);

assign m114419_nor3_1[3:0] =
       ~(pre_ma_flush[3:0] | pre_cwq_flush[3:0] | pre_ivt_flush[3:0]);

assign m114419_nor3_2[3:0] =
       ~(idl_exc[3:0] | {4 {ssmode | domode}});

assign m114419_nand3_0[3:0] =
       ~(m114419_nor3_0 & m114419_nor3_1 & m114419_nor3_2);

assign m114419_inv_0[3:0] =
       ~(m114419_nand3_0[3:0]);

assign unhalt[3:0] =
       ~(trl_unhalt_[3:0] & m114419_inv_0[3:0]);

assign halted_in[3:0] =
       ~(~(halted[3:0] | asi_halt[3:0]) | unhalt[3:0]);

tlu_fls_ctl_msff_ctl_macro__scanreverse_1__width_16 spare_15_0_lat  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.din	({{6{1'b0}}		       ,
		  halted_in		[3   ],
		  1'b0			       ,
		  halted_in		[0   ],
		  1'b0			       ,
		  halted_in		[1   ],
		  1'b0			       ,
		  halted_in		[2   ],
		  {3{1'b0}}		       }),
	.dout	({unused		[15:10],
		  halted		[3   ],
		  unused		[8   ],
		  halted		[0   ],
		  unused		[6   ],
		  halted		[1   ],
		  unused		[4   ],
		  halted		[2   ],
		  unused		[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_halted[3:0] =
       halted[3:0];


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
// fixscan start:
assign beat_two_b_lat_scanin     = scan_in                  ;
assign l1en_b2w_lat_scanin       = beat_two_b_lat_scanout   ;
assign hpstate_hpriv_lat_scanin  = l1en_b2w_lat_scanout     ;
assign hpriv_bar_or_ie_lat_scanin = hpstate_hpriv_lat_scanout;
assign hpriv_bar_and_ie_lat_scanin = hpriv_bar_or_ie_lat_scanout;
assign tid_dec_d_lat_scanin      = hpriv_bar_and_ie_lat_scanout;
assign itlb_bypass_lat_scanin    = tid_dec_d_lat_scanout    ;
assign itlb_bypass_e_lat_scanin  = itlb_bypass_lat_scanout  ;
assign l_tlu_twocycle_b_lat_scanin = itlb_bypass_e_lat_scanout;
assign tid_b_lat_scanin          = l_tlu_twocycle_b_lat_scanout;
assign fast_tid_dec_b_lat_scanin = tid_b_lat_scanout        ;
assign pre_inst_valid_b_lat_scanin = fast_tid_dec_b_lat_scanout;
assign tl_eq_0_lat_scanin        = pre_inst_valid_b_lat_scanout;
assign lsu_inst_b_lat_scanin     = tl_eq_0_lat_scanout      ;
assign fgu_inst_b_lat_scanin     = lsu_inst_b_lat_scanout   ;
assign illegal_inst_b_lat_scanin = fgu_inst_b_lat_scanout   ;
assign itlb_miss_b_lat_scanin    = illegal_inst_b_lat_scanout;
assign ra_itlb_miss_b_lat_scanin = itlb_miss_b_lat_scanout  ;
assign itlb_priv_exc_b_lat_scanin = ra_itlb_miss_b_lat_scanout;
assign itlb_nfo_exc_b_lat_scanin = itlb_priv_exc_b_lat_scanout;
assign i_l2_unde_b_lat_scanin    = itlb_nfo_exc_b_lat_scanout;
assign i_oor_va_b_lat_scanin     = i_l2_unde_b_lat_scanout  ;
assign i_ra_oor_va_b_lat_scanin  = i_oor_va_b_lat_scanout   ;
assign itlb_err_b_lat_scanin     = i_ra_oor_va_b_lat_scanout;
assign ic_err_b_lat_scanin       = itlb_err_b_lat_scanout   ;
assign done_inst_b_lat_scanin    = ic_err_b_lat_scanout     ;
assign retry_inst_b_lat_scanin   = done_inst_b_lat_scanout  ;
assign sir_b_lat_scanin          = retry_inst_b_lat_scanout ;
assign hpriv_exc_b_lat_scanin    = sir_b_lat_scanout        ;
assign priv_exc_b_lat_scanin     = hpriv_exc_b_lat_scanout  ;
assign fpdisable_exc_b_lat_scanin = priv_exc_b_lat_scanout   ;
assign ecc_b_lat_scanin          = fpdisable_exc_b_lat_scanout;
assign misalign_b_lat_scanin     = ecc_b_lat_scanout        ;
assign e_oor_va_b_lat_scanin     = misalign_b_lat_scanout   ;
assign e_tcc_b_lat_scanin        = e_oor_va_b_lat_scanout   ;
assign e_tof_b_lat_scanin        = e_tcc_b_lat_scanout      ;
assign e_fill_b_lat_scanin       = e_tof_b_lat_scanout      ;
assign br_taken_b_lat_scanin     = e_fill_b_lat_scanout     ;
assign annul_ds_m_lat_scanin     = br_taken_b_lat_scanout   ;
assign ds_b_lat_scanin           = annul_ds_m_lat_scanout   ;
assign perf_trap_b_lat_scanin    = ds_b_lat_scanout         ;
assign pil_mask_15_lat_scanin    = perf_trap_b_lat_scanout  ;
assign ibp_b_lat_scanin          = pil_mask_15_lat_scanout  ;
assign iaw_exc_m_lat_scanin      = ibp_b_lat_scanout        ;
assign iaw_b_lat_scanin          = iaw_exc_m_lat_scanout    ;
assign pstate_tct_b_lat_scanin   = iaw_b_lat_scanout        ;
assign tct_b_lat_scanin          = pstate_tct_b_lat_scanout ;
assign cti_b_lat_scanin          = tct_b_lat_scanout        ;
assign twocycle_inst_w_lat_scanin = cti_b_lat_scanout        ;
assign d_flush_w_lat_scanin      = twocycle_inst_w_lat_scanout;
assign tid_dec_w_lat_scanin      = d_flush_w_lat_scanout    ;
assign pstate_am_b_lat_scanin    = tid_dec_w_lat_scanout    ;
assign pstate_am_w_lat_scanin    = pstate_am_b_lat_scanout  ;
assign two_tid_dec_w_lat_scanin  = pstate_am_w_lat_scanout  ;
assign inst_valid_w_lat_scanin   = two_tid_dec_w_lat_scanout;
assign illegal_inst_w_lat_scanin = inst_valid_w_lat_scanout ;
assign itlb_miss_w_lat_scanin    = illegal_inst_w_lat_scanout;
assign ra_itlb_miss_w_lat_scanin = itlb_miss_w_lat_scanout  ;
assign itlb_priv_exc_w_lat_scanin = ra_itlb_miss_w_lat_scanout;
assign itlb_nfo_exc_w_lat_scanin = itlb_priv_exc_w_lat_scanout;
assign i_l2_err_w_lat_scanin     = itlb_nfo_exc_w_lat_scanout;
assign i_oor_va_w_lat_scanin     = i_l2_err_w_lat_scanout   ;
assign i_ra_oor_va_w_lat_scanin  = i_oor_va_w_lat_scanout   ;
assign itlb_err_w_lat_scanin     = i_ra_oor_va_w_lat_scanout;
assign ic_err_w_lat_scanin       = itlb_err_w_lat_scanout   ;
assign done_inst_w_lat_scanin    = ic_err_w_lat_scanout     ;
assign retry_inst_w_lat_scanin   = done_inst_w_lat_scanout  ;
assign sir_w_lat_scanin          = retry_inst_w_lat_scanout ;
assign hpriv_exc_w_lat_scanin    = sir_w_lat_scanout        ;
assign priv_exc_w_lat_scanin     = hpriv_exc_w_lat_scanout  ;
assign fpdisable_exc_w_lat_scanin = priv_exc_w_lat_scanout   ;
assign tcc_w_lat_scanin          = fpdisable_exc_w_lat_scanout;
assign tof_w_lat_scanin          = tcc_w_lat_scanout        ;
assign e_ecc_w_lat_scanin        = tof_w_lat_scanout        ;
assign kill_irf_ecc_w_lat_scanin = e_ecc_w_lat_scanout      ;
assign e_misalign_w_lat_scanin   = kill_irf_ecc_w_lat_scanout;
assign immu_enable_lat_scanin    = e_misalign_w_lat_scanout ;
assign br_ld_oor_va_w_lat_scanin = immu_enable_lat_scanout  ;
assign br_ld_ra_oor_va_w_lat_scanin = br_ld_oor_va_w_lat_scanout;
assign pc_oor_va_b_lat_scanin    = br_ld_ra_oor_va_w_lat_scanout;
assign snn_w_lat_scanin          = pc_oor_va_b_lat_scanout  ;
assign sno_w_lat_scanin          = snn_w_lat_scanout        ;
assign fnn_w_lat_scanin          = sno_w_lat_scanout        ;
assign fno_w_lat_scanin          = fnn_w_lat_scanout        ;
assign clw_w_lat_scanin          = fno_w_lat_scanout        ;
assign lsu_inst_w_lat_scanin     = clw_w_lat_scanout        ;
assign cti_w_lat_scanin          = lsu_inst_w_lat_scanout   ;
assign wstate3_w_lat_scanin      = cti_w_lat_scanout        ;
assign wstate2_w_lat_scanin      = wstate3_w_lat_scanout    ;
assign wstate1_w_lat_scanin      = wstate2_w_lat_scanout    ;
assign wstate0_w_lat_scanin      = wstate1_w_lat_scanout    ;
assign trap_number_w_lat_scanin  = wstate0_w_lat_scanout    ;
assign trap_number_3_lat_scanin  = trap_number_w_lat_scanout;
assign trap_number_2_lat_scanin  = trap_number_3_lat_scanout;
assign trap_number_1_lat_scanin  = trap_number_2_lat_scanout;
assign trap_number_0_lat_scanin  = trap_number_1_lat_scanout;
assign lddf_align_w_lat_scanin   = trap_number_0_lat_scanout;
assign stdf_align_w_lat_scanin   = lddf_align_w_lat_scanout ;
assign daccess_prot_w_lat_scanin = stdf_align_w_lat_scanout ;
assign priv_action_w_lat_scanin  = daccess_prot_w_lat_scanout;
assign va_watchpoint_w_lat_scanin = priv_action_w_lat_scanout;
assign pa_watchpoint_w_lat_scanin = va_watchpoint_w_lat_scanout;
assign align_w_lat_scanin        = pa_watchpoint_w_lat_scanout;
assign dtlb_w_lat_scanin         = align_w_lat_scanout      ;
assign ra_dtlb_w_lat_scanin      = dtlb_w_lat_scanout       ;
assign l_real_w_lat_scanin       = ra_dtlb_w_lat_scanout    ;
assign dae_invalid_asi_w_lat_scanin = l_real_w_lat_scanout     ;
assign dae_nc_page_w_lat_scanin  = dae_invalid_asi_w_lat_scanout;
assign dae_nfo_page_w_lat_scanin = dae_nc_page_w_lat_scanout;
assign dae_priv_viol_w_lat_scanin = dae_nfo_page_w_lat_scanout;
assign dae_so_page_w_lat_scanin  = dae_priv_viol_w_lat_scanout;
assign dtlb_error_w_lat_scanin   = dae_so_page_w_lat_scanout;
assign precise_perf_trap_w_lat_scanin = dtlb_error_w_lat_scanout ;
assign perf_trap_w_lat_scanin    = precise_perf_trap_w_lat_scanout;
assign ibp_w_lat_scanin          = perf_trap_w_lat_scanout  ;
assign iaw_w_lat_scanin          = ibp_w_lat_scanout        ;
assign tct_w_lat_scanin          = iaw_w_lat_scanout        ;
assign l_spec_enable_lat_scanin  = tct_w_lat_scanout        ;
assign f_predict_w_lat_scanin    = l_spec_enable_lat_scanout;
assign pdist_beat2_fx2_lat_scanin = f_predict_w_lat_scanout  ;
assign f_cecc_w_lat_scanin       = pdist_beat2_fx2_lat_scanout;
assign f_uecc_w_lat_scanin       = f_cecc_w_lat_scanout     ;
assign pdist_ecc_w_lat_scanin    = f_uecc_w_lat_scanout     ;
assign asi_ecc_w_lat_scanin      = pdist_ecc_w_lat_scanout  ;
assign ime_w_lat_scanin          = asi_ecc_w_lat_scanout    ;
assign dme_w_lat_scanin          = ime_w_lat_scanout        ;
assign m_dae_req_b_lat_scanin    = dme_w_lat_scanout        ;
assign m_dae_req_w_lat_scanin    = m_dae_req_b_lat_scanout  ;
assign br_taken_not_annul_ds_w_lat_scanin = m_dae_req_w_lat_scanout  ;
assign nns_exc_lat_scanin        = br_taken_not_annul_ds_w_lat_scanout;
assign nns_exc_w_lat_scanin      = nns_exc_lat_scanout      ;
assign exc_w_lat_scanin          = nns_exc_w_lat_scanout    ;
assign trap_flush_lat_scanin     = exc_w_lat_scanout        ;
assign preflush_b_lat_scanin     = trap_flush_lat_scanout   ;
assign flush_gfb_lat_scanin      = preflush_b_lat_scanout   ;
assign l_l2_ecc_w_lat_scanin     = flush_gfb_lat_scanout    ;
assign l_sbdl_ecc_w_lat_scanin   = l_l2_ecc_w_lat_scanout   ;
assign priv_action_g_w_lat_scanin = l_sbdl_ecc_w_lat_scanout ;
assign precise_perf_trap_g_w_lat_scanin = priv_action_g_w_lat_scanout;
assign ieee_exc_fw_lat_scanin    = precise_perf_trap_g_w_lat_scanout;
assign unfin_fw_lat_scanin       = ieee_exc_fw_lat_scanout  ;
assign idiv0_exc_fw_lat_scanin   = unfin_fw_lat_scanout     ;
assign xir_flush_lat_scanin      = idiv0_exc_fw_lat_scanout ;
assign xir_flush_b_lat_scanin    = xir_flush_lat_scanout    ;
assign pre_desr_f_lat_scanin     = xir_flush_b_lat_scanout  ;
assign desr_f_lat_scanin         = pre_desr_f_lat_scanout   ;
assign desr_s_lat_scanin         = desr_f_lat_scanout       ;
assign eer_err_b_lat_scanin      = desr_s_lat_scanout       ;
assign ade_err_b_lat_scanin      = eer_err_b_lat_scanout    ;
assign l_sbpp_lat_scanin         = ade_err_b_lat_scanout    ;
assign l_sbpp_b_lat_scanin       = l_sbpp_lat_scanout       ;
assign ma_flush_lat_scanin       = l_sbpp_b_lat_scanout     ;
assign ma_flush_b_lat_scanin     = ma_flush_lat_scanout     ;
assign cwq_flush_lat_scanin      = ma_flush_b_lat_scanout   ;
assign cwq_flush_b_lat_scanin    = cwq_flush_lat_scanout    ;
assign mqr_exc_b_lat_scanin      = cwq_flush_b_lat_scanout  ;
assign dqr_exc_b_lat_scanin      = mqr_exc_b_lat_scanout    ;
assign rqr_exc_b_lat_scanin      = dqr_exc_b_lat_scanout    ;
assign ivt_lat_scanin            = rqr_exc_b_lat_scanout    ;
assign ivt_flush_b_lat_scanin    = ivt_lat_scanout          ;
assign iln_exc_b_lat_scanin      = ivt_flush_b_lat_scanout  ;
assign tlz_exc_b_lat_scanin      = iln_exc_b_lat_scanout    ;
assign hst_exc_b_lat_scanin      = tlz_exc_b_lat_scanout    ;
assign no_hold_disrupting_flush_lat_scanin = hst_exc_b_lat_scanout    ;
assign disrupting_flush_pending_tid_dec_b_lat_scanin = no_hold_disrupting_flush_lat_scanout;
assign cdfpw_lat_scanin          = disrupting_flush_pending_tid_dec_b_lat_scanout;
assign disrupting_flush_w_lat_scanin = cdfpw_lat_scanout        ;
assign block_store_w_lat_scanin  = disrupting_flush_w_lat_scanout;
assign bsee_pending_lat_scanin   = block_store_w_lat_scanout;
assign bsee_req_lat_scanin       = bsee_pending_lat_scanout ;
assign bsee_req_w_lat_scanin     = bsee_req_lat_scanout     ;
assign bsee_flush_b_lat_scanin   = bsee_req_w_lat_scanout   ;
assign core_running_lat_scanin   = bsee_flush_b_lat_scanout ;
assign core_running_last_lat_scanin = core_running_lat_scanout ;
assign core_running_status_lat_scanin = core_running_last_lat_scanout;
assign idl_exc_lat_scanin        = core_running_status_lat_scanout;
assign idl_req_lat_scanin        = idl_exc_lat_scanout      ;
assign ssmode_lat_scanin         = idl_req_lat_scanout      ;
assign domode_lat_scanin         = ssmode_lat_scanout       ;
assign ssreq_lat_scanin          = domode_lat_scanout       ;
assign ssr_req_lat_scanin        = ssreq_lat_scanout        ;
assign ever_been_running_lat_scanin = ssr_req_lat_scanout      ;
assign por_req_lat_scanin        = ever_been_running_lat_scanout;
assign xir_req_lat_scanin        = por_req_lat_scanout      ;
assign ftt_req_lat_scanin        = xir_req_lat_scanout      ;
assign ade_req_lat_scanin        = ftt_req_lat_scanout      ;
assign eer_req_lat_scanin        = ade_req_lat_scanout      ;
assign ivt_req_lat_scanin        = eer_req_lat_scanout      ;
assign ma_req_lat_scanin         = ivt_req_lat_scanout      ;
assign cwq_req_lat_scanin        = ma_req_lat_scanout       ;
assign mqr_req_lat_scanin        = cwq_req_lat_scanout      ;
assign dqr_req_lat_scanin        = mqr_req_lat_scanout      ;
assign rqr_req_lat_scanin        = dqr_req_lat_scanout      ;
assign iln_req_lat_scanin        = rqr_req_lat_scanout      ;
assign hst_req_lat_scanin        = iln_req_lat_scanout      ;
assign tlz_req_lat_scanin        = hst_req_lat_scanout      ;
assign ssc_req_lat_scanin        = tlz_req_lat_scanout      ;
assign disrupting_ssc_exc_lat_scanin = ssc_req_lat_scanout      ;
assign hw_tw_enabled_lat_scanin  = disrupting_ssc_exc_lat_scanout;
assign load_i_tag_access_lat_scanin = hw_tw_enabled_lat_scanout;
assign load_d_tag_access_lat_scanin = load_i_tag_access_lat_scanout;
assign m103663_lat_scanin        = load_d_tag_access_lat_scanout;
assign refetch_w_lat_scanin      = m103663_lat_scanout      ;
assign pc_valid_lat_scanin       = refetch_w_lat_scanout    ;
assign npc_valid_lat_scanin      = pc_valid_lat_scanout     ;
assign pc_is_npc_lat_scanin      = npc_valid_lat_scanout    ;
assign debug_event_lat_scanin    = pc_is_npc_lat_scanout    ;
assign softstop_req_lat_scanin   = debug_event_lat_scanout  ;
assign hardstop_req_lat_scanin   = softstop_req_lat_scanout ;
assign pulse_req_lat_scanin      = hardstop_req_lat_scanout ;
assign instr_cmt_grp_lat_scanin  = pulse_req_lat_scanout    ;
assign spares_scanin             = instr_cmt_grp_lat_scanout;
assign scan_out                  = spares_scanout           ;

assign pmqr_exc_lat_wmr_scanin   = wmr_scan_in              ;
assign pdqr_exc_lat_wmr_scanin   = pmqr_exc_lat_wmr_scanout ;
assign prqr_exc_lat_wmr_scanin   = pdqr_exc_lat_wmr_scanout ;
assign ivt_flush_lat_wmr_scanin  = prqr_exc_lat_wmr_scanout ;
assign cwp_lat_wmr_scanin        = ivt_flush_lat_wmr_scanout;
assign wmr_scan_out              = cwp_lat_wmr_scanout      ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module tlu_fls_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_fls_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_fls_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_fls_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_fls_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_fls_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_fls_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_fls_ctl_msff_ctl_macro__scanreverse_1__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [0:14] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({so[0:14],scan_in}),
.so({scan_out,so[0:14]}),
.q(dout[15:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_mbd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_mbd_dp (
  asi_mbd_compare_data, 
  asi_mbd_sel_tsd0, 
  asi_mbd_sel_tsd1, 
  asi_mbd_sel_tic, 
  tic_mbist_data, 
  tsd0_mbist_data, 
  tsd1_mbist_data, 
  tlu_pc_0_prebuf_d, 
  mbd_compare, 
  tlu_pc_0_d);
wire [31:0] read_data;


input	[7:0]	asi_mbd_compare_data;
input 		asi_mbd_sel_tsd0;
input 		asi_mbd_sel_tsd1;
input 		asi_mbd_sel_tic;

input	[31:0]	tic_mbist_data;

input	[31:0]	tsd0_mbist_data;
input	[31:0]	tsd1_mbist_data;

input	[47:2] tlu_pc_0_prebuf_d;


output		mbd_compare;

output	[47:2] tlu_pc_0_d;


//////////////////////////////////////////////////////////////////////


tlu_mbd_dp_mux_macro__mux_aonpe__ports_3__stack_32r__width_32 read_data_mux     (
	.din0	(tsd0_mbist_data	[31:0]	),
	.din1	(tsd1_mbist_data	[31:0]	),
	.din2	(tic_mbist_data		[31:0]	),
	.sel0	(asi_mbd_sel_tsd0		),
	.sel1	(asi_mbd_sel_tsd1		),
	.sel2	(asi_mbd_sel_tic		),
	.dout	(read_data		[31:0]	)
);

tlu_mbd_dp_cmp_macro__width_32 mbist_cmp  (
	.din0	(read_data			[31:0]	),
	.din1	({4 {asi_mbd_compare_data	[7:0]}}),
	.dout	(mbd_compare				)

);

tlu_mbd_dp_buff_macro__dbuff_40x__rep_1__stack_none__width_46 pc_0_d_buf     (
	.din	(tlu_pc_0_prebuf_d	[47:2]	),
	.dout	(tlu_pc_0_d		[47:2]	)

);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_mbd_dp_mux_macro__mux_aonpe__ports_3__stack_32r__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  input [31:0] din2;
  input sel2;
  output [31:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(32)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
.dout(dout[31:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module tlu_mbd_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   buff macro
//
//


module tlu_mbd_dp_buff_macro__dbuff_40x__rep_1__stack_none__width_46 (
  din, 
  dout);
  input [45:0] din;
  output [45:0] dout;


buff #(46)  d0_0 (
.in(din[45:0]),
.out(dout[45:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_npc_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_npc_dp (
  pct0_npc_w, 
  pct1_npc_w, 
  fls1_lsu_inst_w, 
  tlu_npc_w);


input	[47:2]	pct0_npc_w;
input	[47:2]	pct1_npc_w;
input 		fls1_lsu_inst_w;


output	[47:2]	tlu_npc_w;


//////////////////////////////////////////////////////////////////////


tlu_npc_dp_mux_macro__mux_aope__ports_2__stack_48c__width_46 npc_w_mux     (
	.din1	(pct0_npc_w		[47:2]	),
	.din0	(pct1_npc_w		[47:2]	),
	.sel0	(fls1_lsu_inst_w		),
	.dout	(tlu_npc_w		[47:2]	)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_npc_dp_mux_macro__mux_aope__ports_2__stack_48c__width_46 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [45:0] din0;
  input [45:0] din1;
  input sel0;
  output [45:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(46)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[45:0]),
  .in1(din1[45:0]),
.dout(dout[45:0])
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_pct_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_pct_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_scan_en_wmr, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  tcu_wmr_vec_mask, 
  dec_flush_b, 
  dec_inst_cnt, 
  dec_raw_pick_p, 
  exu_address_m, 
  exu_oor_va_m, 
  mmu_itte_tag_data, 
  asi_rd_pc, 
  asi_rd_iaw, 
  asi_wr_iaw, 
  asi_wr_data, 
  fls_tid_dec_b, 
  fls_tid_dec_w, 
  fls_pc_sel_npc, 
  fls_pc_sel_npc_plus_4, 
  fls_npc_sel_npc_plus_4, 
  fls_npc_sel_npc_plus_8, 
  fls_npc_sel_target, 
  fls_npc_b_sel_npc, 
  fls_pc_is_npc, 
  fls_pstate_am_d_, 
  fls_pstate_am_b_, 
  fls_pstate_am_w_, 
  fls_npc_if_cnt_eq_1_d, 
  fls_npc_if_cnt_eq_2_d, 
  fls_npc_if_cnt_eq_3_d, 
  fls_pct_pc_en, 
  fls_pct_npc_en, 
  trl_pc_sel_trap_pc, 
  trl_npc_sel_trap_npc, 
  trl_npc_sel_tnpc, 
  trl_trap_type, 
  trl_pc_thread_sel, 
  trl_pc_pstate_am_, 
  trl_pc_sel_pc, 
  trl_pc_sel_npc, 
  trl_pc_sel_trap, 
  trl_pc_sel_reset, 
  trl_pc_done, 
  trl_pc_retry, 
  trl_pc_tte, 
  trl_pct_trap_pc_en, 
  trl_pct_tnpc_en, 
  tsd_tba, 
  tsd_tpc, 
  tsd_tpc_oor_va, 
  tsd_tnpc, 
  tsd_tnpc_oor_va, 
  tsd_tnpc_nonseq, 
  tsd_asi_data_, 
  tsd_pstate_am, 
  scan_out, 
  wmr_scan_out, 
  pct_asi_data, 
  pct_npc_0_w, 
  pct_npc_1_w, 
  pct_npc_2_w, 
  pct_npc_3_w, 
  pct_tsa_pc, 
  pct_tsa_pc_oor_va, 
  pct_tsa_npc, 
  pct_tsa_npc_oor_va, 
  pct_tsa_npc_nonseq, 
  pct_npc_is_nonseq, 
  pct_pc_oor_va_e, 
  pct_iaw_exc_e, 
  pct_shadow_pc_d, 
  pct_npc_w, 
  pct_target_b, 
  pct_trl_wr_data, 
  tsd_pc_w, 
  tlu_pc_d, 
  tlu_pc_w, 
  tlu_trap_pc);
wire en;
wire clk;
wire stop;
wire test;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire target_b_lat_scanin;
wire target_b_lat_scanout;
wire wmr_vec_mask;
wire oor_va_b;
wire [47:2] target_b;
wire flush_b;
wire pc_3_w_lat_scanin;
wire pc_3_w_lat_scanout;
wire trap_pc_oor_va;
wire [47:0] trap_pc;
wire pc_3_oor_va_w;
wire [47:2] pc_3_w;
wire [47:2] npc_plus_4_noncrit_b;
wire npc_oor_va_b;
wire [47:2] npc_noncrit_b;
wire pc_2_w_lat_scanin;
wire pc_2_w_lat_scanout;
wire pc_2_oor_va_w;
wire [47:2] pc_2_w;
wire pc_1_w_lat_scanin;
wire pc_1_w_lat_scanout;
wire pc_1_oor_va_w;
wire [47:2] pc_1_w;
wire pc_0_w_lat_scanin;
wire pc_0_w_lat_scanout;
wire pc_0_oor_va_w;
wire [47:2] pc_0_w;
wire tnpc_lat_scanin;
wire tnpc_lat_scanout;
wire tnpc_nonseq;
wire tnpc_oor_va;
wire [47:2] tnpc;
wire npc_3_w_lat_scanin;
wire npc_3_w_lat_scanout;
wire npc_3_nonseq;
wire npc_3_oor_va_w;
wire [47:2] npc_3_w;
wire [47:2] npc_plus_8_b;
wire [3:2] npc_3_crit_w;
wire npc_2_w_lat_scanin;
wire npc_2_w_lat_scanout;
wire npc_2_nonseq;
wire npc_2_oor_va_w;
wire [47:2] npc_2_w;
wire [3:2] npc_2_crit_w;
wire npc_1_w_lat_scanin;
wire npc_1_w_lat_scanout;
wire npc_1_nonseq;
wire npc_1_oor_va_w;
wire [47:2] npc_1_w;
wire [3:2] npc_1_crit_w;
wire npc_0_w_lat_scanin;
wire npc_0_w_lat_scanout;
wire npc_0_nonseq;
wire npc_0_oor_va_w;
wire [47:2] npc_0_w;
wire [3:2] npc_0_crit_w;
wire [47:2] npc_b;
wire [47:2] npc_plus_4_b;
wire npc_33_02_plus_4_cout_b;
wire [49:48] npc_plus_4_b_unused;
wire npc_49_34_plus_4_cout_b_unused;
wire npc_34_03_plus_8_cout_b;
wire [50:48] npc_plus_8_b_unused;
wire npc_50_35_plus_8_cout_b_unused;
wire npc_b_mux_scanin;
wire npc_b_mux_scanout;
wire tsa_pc_oor_va_w;
wire [47:2] tsa_pc_unmasked_w;
wire [47:32] tsa_pc_w;
wire npc_nonseq;
wire tsa_npc_oor_va_w;
wire [47:2] tsa_npc_unmasked_w;
wire [47:32] tsa_npc_w;
wire [47:2] any_trap_pc;
wire [4:0] wmr_vec_mask_;
wire [47:2] reset_pc;
wire trap_pc_lat_scanin;
wire trap_pc_lat_scanout;
wire [47:5] piped_pc_w;
wire [31:5] piped_pc_pre_buf_w;
wire [12:11] piped_pc_pre_buf_w_unused;
wire [12:11] piped_pc_w_unused;
wire [47:32] masked_pc_w;
wire [3:0] tid_dec_buf_d;
wire pre_pc_oor_va_d;
wire [47:2] pre_pc_d;
wire [3:0] pstate_am_;
wire rd_pc_pstate_am_in;
wire tid_d_lat_scanin;
wire tid_d_lat_scanout;
wire prd_pc_pstate_am;
wire rd_iaw;
wire [3:0] rd_pc;
wire [3:0] tid_dec_d;
wire rd_iaw_;
wire rd_pc_pstate_am_;
wire pre_npc_oor_va_d;
wire [47:2] pre_npc_d;
wire [47:2] pre_npc_noncrit_d;
wire [63:22] npc_inc_unused;
wire [47:2] npc_inc_d;
wire npc_inc_cout_d_unused;
wire inst_cnt_nz;
wire [1:0] inst_cnt_;
wire [4:2] npc_inc_0_d;
wire [4:2] npc_inc_1_d;
wire [4:2] npc_inc_2_d;
wire [4:2] npc_inc_3_d;
wire pc_4_carry_d;
wire tcu_muxtest_rep3;
wire pc_oor_va_d;
wire [47:2] pc_d;
wire [47:2] pc_noncrit_d;
wire masked_pc_oor_va_d;
wire [47:32] masked_pc_d;
wire pc_e_lat_scanin;
wire pc_e_lat_scanout;
wire pc_oor_va_e;
wire [47:2] pc_e;
wire iaw_lat_wmr_scanin;
wire iaw_lat_wmr_scanout;
wire iaw_en;
wire [47:2] iaw_va;
wire [48:2] asi_data;
wire [48:2] asi_data_0_;


input		l2clk;		
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		tcu_dectest;
input		tcu_muxtest;

input		tcu_scan_en_wmr;
input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

// RSTVADDR (POR address) control
input 		tcu_wmr_vec_mask;	// PINDEF:BOT

input 		dec_flush_b;
input	[1:0]	dec_inst_cnt;		// Count of instructions in E, M, B
input	[3:0]	dec_raw_pick_p;		// Decoded TID at P

input	[47:2]	exu_address_m;		// Target for taken branches
input		exu_oor_va_m;

input	[47:0]	mmu_itte_tag_data;

input	[3:0]	asi_rd_pc;
input		asi_rd_iaw;
input		asi_wr_iaw;
input	[47:0]	asi_wr_data;

input 	[3:0]	fls_tid_dec_b;
input 	[3:0]	fls_tid_dec_w;
input 	[3:0]	fls_pc_sel_npc;		// Sequential flow
input 	[3:0]	fls_pc_sel_npc_plus_4;	// Branch taken or(not taken with annul)
input 	[3:0]	fls_npc_sel_npc_plus_4;	// Sequential flow
input 	[3:0]	fls_npc_sel_npc_plus_8;	// Branch not taken with annul
input 	[3:0]	fls_npc_sel_target;	// Branch taken
input 		fls_npc_b_sel_npc;	// NPC is invalid (but going valid)
input		fls_pc_is_npc;		// PC reg actually holds NPC, not PC
input		fls_pstate_am_d_;	// For instruction watchpoint
input		fls_pstate_am_b_;	// For dsfar
input		fls_pstate_am_w_;	// For itlb_tag_access
input	[4:2]	fls_npc_if_cnt_eq_1_d;
input	[4:2]	fls_npc_if_cnt_eq_2_d;
input	[4:2]	fls_npc_if_cnt_eq_3_d;
input	[3:0]	fls_pct_pc_en;		// Power managment for PC flops
input	[3:0]	fls_pct_npc_en;		// Power managment for NPC flops

input 	[3:0]	trl_pc_sel_trap_pc;	// Trap, retry, or done taken; update PC
input 	[3:0]	trl_npc_sel_trap_npc;	// Trap taken; update NPC
input 	[3:0]	trl_npc_sel_tnpc;	// Retry or done taken; update NPC
input	[8:0] trl_trap_type;		// Trap type
input	[3:0]	trl_pc_thread_sel;	// Which thread is trapping
input 		trl_pc_pstate_am_;
input		trl_pc_sel_pc;		// Retry the excepting instruction
input		trl_pc_sel_npc;		// Advance to the next instruction
input		trl_pc_sel_trap;	// Select the trap PC
input		trl_pc_sel_reset;	// Select the reset PC
input		trl_pc_done;		// Select the NPC from the stack
input		trl_pc_retry;		// Select the PC from the stack
input		trl_pc_tte;		// Select the TTE for ITLB write
input		trl_pct_trap_pc_en;	// Power management
input		trl_pct_tnpc_en;

input	[47:14]	tsd_tba;		// Trap Base Address 
input	[47:2]	tsd_tpc;
input		tsd_tpc_oor_va;
input	[47:2] tsd_tnpc;
input		tsd_tnpc_oor_va;
input		tsd_tnpc_nonseq;
input	[47:2]	tsd_asi_data_;
input	[3:0]	tsd_pstate_am;


output		scan_out;		

output		wmr_scan_out;		// Warm reset (non)scan

output	[48:2]	pct_asi_data;

output	[3:2]	pct_npc_0_w;
output	[3:2]	pct_npc_1_w;
output	[3:2]	pct_npc_2_w;
output	[3:2]	pct_npc_3_w;

output	[47:2]	pct_tsa_pc;
output 		pct_tsa_pc_oor_va;
output	[47:2]	pct_tsa_npc;
output 		pct_tsa_npc_oor_va;
output 		pct_tsa_npc_nonseq;
output	[3:0]	pct_npc_is_nonseq;
output		pct_pc_oor_va_e;

output	[1:0]	pct_iaw_exc_e;

output	[47:2]	pct_shadow_pc_d;

output	[47:2]	pct_npc_w;

output	[47:2]	pct_target_b;

output	[16:0]	pct_trl_wr_data;

output	[10:5]	tsd_pc_w;

output	[47:2]	tlu_pc_d;
output	[47:13]	tlu_pc_w;
output	[47:0] tlu_trap_pc;


////////////////////////////////////////////////////////////////////////////////

assign en 	= 1'b1;
assign clk 	= l2clk;
assign stop	= 1'b0;
assign test	= tcu_dectest;

tlu_pct_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);


////////////////////////////////////////////////////////////////////////////////
// Pass target from M to B

tlu_pct_dp_msff_macro__stack_48c__width_48 target_b_lat   (
	.scan_in(target_b_lat_scanin),
	.scan_out(target_b_lat_scanout),
	.din	({tcu_wmr_vec_mask	       ,
		  exu_oor_va_m		       ,
		  exu_address_m		[47:2]}),
	.dout	({wmr_vec_mask		       ,
		  oor_va_b		       ,
		  target_b		[47:2]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_and_macro__ports_2__stack_48c__width_46 target_b_buf    (
	.din0	(target_b		[47:2]	),
	.din1	({{16 {fls_pstate_am_b_}}      ,
		  {30 {1'b1}}		       }),
	.dout	(pct_target_b		[47:2]	)
);


////////////////////////////////////////////////////////////////////////////////
// Save each thread's PC and NPC

// Have to use trap_pc because it merges any_trap_pc and reset_trap_pc
//  Also already has TPC and TNPC merged in...
// PC update to trap vector value should happen concurrently with TSA update

tlu_pct_dp_buff_macro__stack_48c__width_1 flush_b_buf   (
	.din	(dec_flush_b			),
	.dout	(flush_b			)
);

tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 pc_3_w_lat     (
	.scan_in(pc_3_w_lat_scanin),
	.scan_out(pc_3_w_lat_scanout),
	.din0	({trap_pc_oor_va	       ,
		  trap_pc		[47:2]}),
	.din1	({pc_3_oor_va_w		       ,
		  pc_3_w		[47:2]}),
	.din2	({1'b0			       ,
		  npc_plus_4_noncrit_b	[47:2]}),
	.din3	({npc_oor_va_b		       ,
		  npc_noncrit_b		[47:2]}),
	.din4	({pc_3_oor_va_w		       ,
		  pc_3_w		[47:2]}),
	.sel0	(trl_pc_sel_trap_pc	[3   ]	),
	.sel1	(flush_b			),
	.sel2	(fls_pc_sel_npc_plus_4	[3   ]	),
	.sel3	(fls_pc_sel_npc		[3   ]	),
	.en	(fls_pct_pc_en		[3   ]	),
	.dout	({pc_3_oor_va_w		       ,
		  pc_3_w		[47:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 pc_2_w_lat     (
	.scan_in(pc_2_w_lat_scanin),
	.scan_out(pc_2_w_lat_scanout),
	.din0	({trap_pc_oor_va	       ,
		  trap_pc		[47:2]}),
	.din1	({pc_2_oor_va_w		       ,
		  pc_2_w		[47:2]}),
	.din2	({1'b0			       ,
		  npc_plus_4_noncrit_b	[47:2]}),
	.din3	({npc_oor_va_b		       ,
		  npc_noncrit_b		[47:2]}),
	.din4	({pc_2_oor_va_w		       ,
		  pc_2_w		[47:2]}),
	.sel0	(trl_pc_sel_trap_pc	[2   ]	),
	.sel1	(flush_b			),
	.sel2	(fls_pc_sel_npc_plus_4	[2   ]	),
	.sel3	(fls_pc_sel_npc		[2   ]	),
	.en	(fls_pct_pc_en		[2   ]	),
	.dout	({pc_2_oor_va_w		       ,
		  pc_2_w		[47:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 pc_1_w_lat     (
	.scan_in(pc_1_w_lat_scanin),
	.scan_out(pc_1_w_lat_scanout),
	.din0	({trap_pc_oor_va	       ,
		  trap_pc		[47:2]}),
	.din1	({pc_1_oor_va_w		       ,
		  pc_1_w		[47:2]}),
	.din2	({1'b0			       ,
		  npc_plus_4_noncrit_b	[47:2]}),
	.din3	({npc_oor_va_b		       ,
		  npc_noncrit_b		[47:2]}),
	.din4	({pc_1_oor_va_w		       ,
		  pc_1_w		[47:2]}),
	.sel0	(trl_pc_sel_trap_pc	[1   ]	),
	.sel1	(flush_b			),
	.sel2	(fls_pc_sel_npc_plus_4	[1   ]	),
	.sel3	(fls_pc_sel_npc		[1   ]	),
	.en	(fls_pct_pc_en		[1   ]	),
	.dout	({pc_1_oor_va_w		       ,
		  pc_1_w		[47:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 pc_0_w_lat     (
	.scan_in(pc_0_w_lat_scanin),
	.scan_out(pc_0_w_lat_scanout),
	.din0	({trap_pc_oor_va	       ,
		  trap_pc		[47:2]}),
	.din1	({pc_0_oor_va_w		       ,
		  pc_0_w		[47:2]}),
	.din2	({1'b0			       ,
		  npc_plus_4_noncrit_b	[47:2]}),
	.din3	({npc_oor_va_b		       ,
		  npc_noncrit_b		[47:2]}),
	.din4	({pc_0_oor_va_w		       ,
		  pc_0_w		[47:2]}),
	.sel0	(trl_pc_sel_trap_pc	[0   ]	),
	.sel1	(flush_b			),
	.sel2	(fls_pc_sel_npc_plus_4	[0   ]	),
	.sel3	(fls_pc_sel_npc		[0   ]	),
	.en	(fls_pct_pc_en		[0   ]	),
	.dout	({pc_0_oor_va_w		       ,
		  pc_0_w		[47:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Hold tsd_tnpc for one cycle to allow for ECC check of TSA
tlu_pct_dp_msff_macro__minbuff_1__stack_48c__width_48 tnpc_lat    (
	.scan_in(tnpc_lat_scanin),
	.scan_out(tnpc_lat_scanout),
	.din	({tsd_tnpc_nonseq	       ,
		  tsd_tnpc_oor_va	       ,
		  tsd_tnpc		[47:2]}),
	.en	(trl_pct_tnpc_en	       	),
	.dout	({tnpc_nonseq		       ,
		  tnpc_oor_va		       ,
		  tnpc			[47:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 npc_3_w_lat     (
	.scan_in(npc_3_w_lat_scanin),
	.scan_out(npc_3_w_lat_scanout),
	.din0	({1'b0			       ,
		  trap_pc_oor_va	       ,
		  trap_pc		[47:3],
		  1'b1			       }),
	.din1	({tnpc_nonseq		       ,
		  tnpc_oor_va		       ,
		  tnpc			[47:2]}),
	.din2	({npc_3_nonseq		       ,
		  npc_3_oor_va_w	       ,
		  npc_3_w		[47:2]}),
	.din3	({1'b1			       ,
		  oor_va_b		       ,
		  target_b		[47:2]}),
	.din4	({{2 {1'b0}}		       ,
		  npc_plus_8_b		[47:2]}),
	.din5	({{2 {1'b0}}		       ,
		  npc_plus_4_noncrit_b	[47:2]}),
	.din6	({npc_3_nonseq		       ,
		  npc_3_oor_va_w	       ,
		  npc_3_w		[47:2]}),
        .sel0	(trl_npc_sel_trap_npc	[3   ]	),
        .sel1	(trl_npc_sel_tnpc	[3   ]	),
	.sel2	(flush_b			),
	.sel3	(fls_npc_sel_target	[3   ]	),
	.sel4	(fls_npc_sel_npc_plus_8	[3   ]	),
	.sel5	(fls_npc_sel_npc_plus_4	[3   ]	),
	.en	(fls_pct_npc_en		[3   ]	),
	.dout	({npc_3_nonseq		       ,
		  npc_3_oor_va_w	       ,
		  npc_3_w		[47:4],
		  npc_3_crit_w		[3:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_buff_macro__stack_48c__width_2 npc_3_w_buf   (
	.din	(npc_3_crit_w		[3:2]	),
	.dout	(npc_3_w		[3:2]	)
);

tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 npc_2_w_lat     (
	.scan_in(npc_2_w_lat_scanin),
	.scan_out(npc_2_w_lat_scanout),
	.din0	({1'b0			       ,
		  trap_pc_oor_va	       ,
		  trap_pc		[47:3],
		  1'b1			       }),
	.din1	({tnpc_nonseq		       ,
		  tnpc_oor_va		       ,
		  tnpc			[47:2]}),
	.din2	({npc_2_nonseq		       ,
		  npc_2_oor_va_w	       ,
		  npc_2_w		[47:2]}),
	.din3	({1'b1			       ,
		  oor_va_b		       ,
		  target_b		[47:2]}),
	.din4	({{2 {1'b0}}		       ,
		  npc_plus_8_b		[47:2]}),
	.din5	({{2 {1'b0}}		       ,
		  npc_plus_4_noncrit_b	[47:2]}),
	.din6	({npc_2_nonseq		       ,
		  npc_2_oor_va_w	       ,
		  npc_2_w		[47:2]}),
        .sel0	(trl_npc_sel_trap_npc	[2   ]	),
        .sel1	(trl_npc_sel_tnpc	[2   ]	),
	.sel2	(flush_b			),
	.sel3	(fls_npc_sel_target	[2   ]	),
	.sel4	(fls_npc_sel_npc_plus_8	[2   ]	),
	.sel5	(fls_npc_sel_npc_plus_4	[2   ]	),
	.en	(fls_pct_npc_en		[2   ]	),
	.dout	({npc_2_nonseq		       ,
		  npc_2_oor_va_w	       ,
		  npc_2_w		[47:4],
		  npc_2_crit_w		[3:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_buff_macro__stack_48c__width_2 npc_2_w_buf   (
	.din	(npc_2_crit_w		[3:2]	),
	.dout	(npc_2_w		[3:2]	)
);

tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 npc_1_w_lat     (
	.scan_in(npc_1_w_lat_scanin),
	.scan_out(npc_1_w_lat_scanout),
	.din0	({1'b0			       ,
		  trap_pc_oor_va	       ,
		  trap_pc		[47:3],
		  1'b1			       }),
	.din1	({tnpc_nonseq		       ,
		  tnpc_oor_va		       ,
		  tnpc			[47:2]}),
	.din2	({npc_1_nonseq		       ,
		  npc_1_oor_va_w	       ,
		  npc_1_w		[47:2]}),
	.din3	({1'b1			       ,
		  oor_va_b		       ,
		  target_b		[47:2]}),
	.din4	({{2 {1'b0}}		       ,
		  npc_plus_8_b		[47:2]}),
	.din5	({{2 {1'b0}}		       ,
		  npc_plus_4_noncrit_b	[47:2]}),
	.din6	({npc_1_nonseq		       ,
		  npc_1_oor_va_w	       ,
		  npc_1_w		[47:2]}),
        .sel0	(trl_npc_sel_trap_npc	[1   ]	),
        .sel1	(trl_npc_sel_tnpc	[1   ]	),
	.sel2	(flush_b			),
	.sel3	(fls_npc_sel_target	[1   ]	),
	.sel4	(fls_npc_sel_npc_plus_8	[1   ]	),
	.sel5	(fls_npc_sel_npc_plus_4	[1   ]	),
	.en	(fls_pct_npc_en		[1   ]	),
	.dout	({npc_1_nonseq		       ,
		  npc_1_oor_va_w	       ,
		  npc_1_w		[47:4],
		  npc_1_crit_w		[3:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_buff_macro__stack_48c__width_2 npc_1_w_buf   (
	.din	(npc_1_crit_w		[3:2]	),
	.dout	(npc_1_w		[3:2]	)
);

tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 npc_0_w_lat     (
	.scan_in(npc_0_w_lat_scanin),
	.scan_out(npc_0_w_lat_scanout),
	.din0	({1'b0			       ,
		  trap_pc_oor_va	       ,
		  trap_pc		[47:3],
		  1'b1			       }),
	.din1	({tnpc_nonseq		       ,
		  tnpc_oor_va		       ,
		  tnpc			[47:2]}),
	.din2	({npc_0_nonseq		       ,
		  npc_0_oor_va_w	       ,
		  npc_0_w		[47:2]}),
	.din3	({1'b1			       ,
		  oor_va_b		       ,
		  target_b		[47:2]}),
	.din4	({{2 {1'b0}}		       ,
		  npc_plus_8_b		[47:2]}),
	.din5	({{2 {1'b0}}		       ,
		  npc_plus_4_noncrit_b	[47:2]}),
	.din6	({npc_0_nonseq		       ,
		  npc_0_oor_va_w	       ,
		  npc_0_w		[47:2]}),
        .sel0	(trl_npc_sel_trap_npc	[0   ]	),
        .sel1	(trl_npc_sel_tnpc	[0   ]	),
	.sel2	(flush_b			),
	.sel3	(fls_npc_sel_target	[0   ]	),
	.sel4	(fls_npc_sel_npc_plus_8	[0   ]	),
	.sel5	(fls_npc_sel_npc_plus_4	[0   ]	),
	.en	(fls_pct_npc_en		[0   ]	),
	.dout	({npc_0_nonseq		       ,
		  npc_0_oor_va_w	       ,
		  npc_0_w		[47:4],
		  npc_0_crit_w		[3:2]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_buff_macro__stack_48c__width_2 npc_0_w_buf   (
	.din	(npc_0_crit_w		[3:2]	),
	.dout	(npc_0_w		[3:2]	)
);


assign pct_npc_is_nonseq[3:0] =
       {npc_3_nonseq, npc_2_nonseq, npc_1_nonseq, npc_0_nonseq};


////////////////////////////////////////////////////////////////////////////////
// Generate NPC

tlu_pct_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_48c__width_47 npc_incr_mux      (
	.din0	({npc_0_oor_va_w	       ,
		  npc_0_w		[47:2]}),
	.din1	({npc_1_oor_va_w	       ,
		  npc_1_w		[47:2]}),
	.din2	({npc_2_oor_va_w	       ,
		  npc_2_w		[47:2]}),
	.din3	({npc_3_oor_va_w	       ,
		  npc_3_w		[47:2]}),
	.sel0	(fls_tid_dec_b		[0   ]	),
	.sel1	(fls_tid_dec_b		[1   ]	),
	.sel2	(fls_tid_dec_b		[2   ]	),
	.sel3	(fls_tid_dec_b		[3   ]	),
	.dout	({npc_oor_va_b		       ,
		  npc_b			[47:2]})
);

tlu_pct_dp_buff_macro__stack_48c__width_46 npc_buf   (
	.din	(npc_b			[47:2] ),
	.dout	(npc_noncrit_b		[47:2] )
);

tlu_pct_dp_increment_macro__width_32 npc_33_02_plus_4_b_inc  (
	.din	(npc_b			[33:2]	),
	.cin	(1'b1				),
	.dout	(npc_plus_4_b		[33:2]	),
	.cout	(npc_33_02_plus_4_cout_b	)
);

tlu_pct_dp_increment_macro__width_16 npc_plus_4_u_b_inc  (
	.din	({2'b00			       ,
		  npc_b			[47:34]}),
	.cin	(npc_33_02_plus_4_cout_b	),
	.dout	({npc_plus_4_b_unused	[49:48],
		  npc_plus_4_b		[47:34]}),
	.cout	(npc_49_34_plus_4_cout_b_unused	)
);

tlu_pct_dp_buff_macro__stack_48c__width_46 npc_plus_4_noncrit_b_buf   (
	.din	(npc_plus_4_b		[47:2]	),
	.dout	(npc_plus_4_noncrit_b	[47:2]	)
);

tlu_pct_dp_increment_macro__width_32 npc_34_03_plus_8_b_inc  (
	.din	(npc_b			[34:3]	),
	.cin	(1'b1				),
	.dout	(npc_plus_8_b		[34:3]	),
	.cout	(npc_34_03_plus_8_cout_b	)
);

assign npc_plus_8_b[2] = npc_noncrit_b[2];

tlu_pct_dp_increment_macro__width_16 npc_47_35_plus_8_b_inc  (
	.din	({3'b000		       ,
		  npc_b			[47:35]}),
	.cin	(npc_34_03_plus_8_cout_b	),
	.dout	({npc_plus_8_b_unused	[50:48],
		  npc_plus_8_b		[47:35]}),
	.cout	(npc_50_35_plus_8_cout_b_unused	)
);

// Generate NPC for instruction in W for load sync case for fetch
// Only has to be correct for loads that are not flushed
tlu_pct_dp_msff_macro__mux_pgpe__ports_2__stack_48c__width_46 npc_w_lat     (
	.scan_in(npc_b_mux_scanin),
	.scan_out(npc_b_mux_scanout),
	.din0	(npc_noncrit_b		[47:2]	),
	.din1	(npc_plus_4_b		[47:2]	),
	.sel0	(fls_npc_b_sel_npc		),
	.dout	(pct_npc_w		[47:2]	),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


////////////////////////////////////////////////////////////////////////////////
// Generate trap PC, NPC

tlu_pct_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_47 pc_mux     (
	.din0	({pc_0_oor_va_w		       ,
		  pc_0_w		[47:2]}),
	.din1	({pc_1_oor_va_w		       ,
		  pc_1_w		[47:2]}),
	.din2	({pc_2_oor_va_w		       ,
		  pc_2_w		[47:2]}),
	.din3	({pc_3_oor_va_w		       ,
		  pc_3_w		[47:2]}),
	.sel0	(trl_pc_thread_sel	[0   ]	),
	.sel1	(trl_pc_thread_sel	[1   ]	),
	.sel2	(trl_pc_thread_sel	[2   ]	),
	.sel3	(trl_pc_thread_sel	[3   ]	),
	.dout	({tsa_pc_oor_va_w	       ,
		  tsa_pc_unmasked_w	[47:2]})
);

tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_16 tsa_pc_w_and     (
	.din0	(tsa_pc_unmasked_w	[47:32]	),
	.din1	({16 {trl_pc_pstate_am_}}	),
	.dout	(tsa_pc_w		[47:32]	)
);

assign pct_tsa_pc[47:2] =
       {tsa_pc_w		[47:32],
	tsa_pc_unmasked_w	[31:2]};

assign pct_tsa_pc_oor_va =
       tsa_pc_oor_va_w;

tlu_pct_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_48 npc_mux     (
	.din0	({npc_0_nonseq		       ,
		  npc_0_oor_va_w	       ,
		  npc_0_w		[47:2]}),
	.din1	({npc_1_nonseq		       ,
		  npc_1_oor_va_w	       ,
		  npc_1_w		[47:2]}),
	.din2	({npc_2_nonseq		       ,
		  npc_2_oor_va_w	       ,
		  npc_2_w		[47:2]}),
	.din3	({npc_3_nonseq		       ,
		  npc_3_oor_va_w	       ,
		  npc_3_w		[47:2]}),
	.sel0	(trl_pc_thread_sel	[0   ]	),
	.sel1	(trl_pc_thread_sel	[1   ]	),
	.sel2	(trl_pc_thread_sel	[2   ]	),
	.sel3	(trl_pc_thread_sel	[3   ]	),
	.dout	({npc_nonseq		       ,
		  tsa_npc_oor_va_w	       ,
		  tsa_npc_unmasked_w	[47:2]})
);

tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_16 tsa_npc_w_and     (
	.din0	(tsa_npc_unmasked_w	[47:32]	),
	.din1	({16 {trl_pc_pstate_am_}}	),
	.dout	(tsa_npc_w		[47:32]	)
);

assign pct_tsa_npc[47:2] =
       {tsa_npc_w		[47:32],
	tsa_npc_unmasked_w	[31:2]};

assign pct_tsa_npc_oor_va =
       tsa_npc_oor_va_w;

assign pct_tsa_npc_nonseq =
       npc_nonseq;

assign any_trap_pc[47:14] = 
	tsd_tba[47:14];

assign any_trap_pc[13:5] = 
	trl_trap_type[8:0];

assign any_trap_pc[4:2] = 
	3'b000;

// Select RSTVADDR == 48'hfffff0000000 or == 0
// Create a tree to prevent overloading of flop

tlu_pct_dp_inv_macro__stack_48c__width_5 reset_pc_inv   (
	.din	({5 {wmr_vec_mask}}		),
	.dout	(wmr_vec_mask_		[4:0]	)
);

assign reset_pc[47:8] =
	{{ 4 {wmr_vec_mask_[4]}},
	 { 4 {wmr_vec_mask_[3]}},
	 { 4 {wmr_vec_mask_[2]}},
	 { 4 {wmr_vec_mask_[1]}},
	 { 4 {wmr_vec_mask_[0]}},
	 {20 {1'b0}}};

assign reset_pc[7:5] = 
	trl_trap_type[2:0];

assign reset_pc[4:2] = 
	3'b000;

// Selects are checked with 0in inside trl
tlu_pct_dp_msff_macro__mux_aope__ports_8__stack_48c__width_48 trap_pc_lat     (
	.scan_in(trap_pc_lat_scanin),
	.scan_out(trap_pc_lat_scanout),
	.din0	({tsa_pc_unmasked_w	[47:2],
		  tsa_pc_oor_va_w	       ,
		  {1 {1'b0}}		       }),
	.din1	({tsa_npc_unmasked_w	[47:2],
		  tsa_npc_oor_va_w	       ,
		  {1 {1'b0}}		       }),
	.din2	({any_trap_pc		[47:2],
		  {2 {1'b0}}		       }),
	.din3	({reset_pc		[47:2],
		  {2 {1'b0}}		       }),
	.din4	({tsd_tpc		[47:2],
		  tsd_tpc_oor_va	       ,
		  {1 {1'b0}}		       }),
	.din5	({tsd_tnpc		[47:2],
		  tsd_tnpc_oor_va	       ,
		  {1 {1'b0}}		       }),
	.din6	(mmu_itte_tag_data	[47:0]	),
	.din7	(trap_pc		[47:0]	),
	.sel0	(trl_pc_sel_pc			),
	.sel1	(trl_pc_sel_npc			),
	.sel2	(trl_pc_sel_trap		),
	.sel3	(trl_pc_sel_reset		),
	.sel4	(trl_pc_retry			),
	.sel5	(trl_pc_done			),
	.sel6	(trl_pc_tte			),
	.en	(trl_pct_trap_pc_en		),
	.dout	(trap_pc		[47:0] ),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


assign tlu_trap_pc[47:0] = 
       trap_pc[47:0];

assign trap_pc_oor_va =
       trap_pc[1];


////////////////////////////////////////////////////////////////////////////////
// Pass PC in W for tag_access reg
// and for DESR

tlu_pct_dp_mux_macro__left_3__mux_aonpe__ports_4__stack_48c__width_43 piped_pc_w_mux      (
	.din0	(pc_0_w			[47:5]	),
	.din1	(pc_1_w			[47:5]	),
	.din2	(pc_2_w			[47:5]	),
	.din3	(pc_3_w			[47:5]	),
	.sel0	(fls_tid_dec_w		[0   ]	),
	.sel1	(fls_tid_dec_w		[1   ]	),
	.sel2	(fls_tid_dec_w		[2   ]	),
	.sel3	(fls_tid_dec_w		[3   ]	),
	.dout	({piped_pc_w		[47:32],
		  piped_pc_pre_buf_w	[31:5]})
);

tlu_pct_dp_buff_macro__left_3__rep_1__stack_48c__width_27 piped_pc_w_buf     (
	.din	(piped_pc_pre_buf_w	[31:5]	),
	.dout	(piped_pc_w		[31:5]	)
);

assign tsd_pc_w[10:5] =
       piped_pc_w[10:5];

assign piped_pc_pre_buf_w_unused[12:11] =
       piped_pc_pre_buf_w[12:11];

assign piped_pc_w_unused[12:11] =
       piped_pc_w[12:11];
	
tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_16 masked_pc_w_and     (
	.din0	(piped_pc_w		[47:32]	),
	.din1	({16 {fls_pstate_am_w_}}	),
	.dout	(masked_pc_w		[47:32]	)
);

assign tlu_pc_w[47:13] = 
       {masked_pc_w[47:32], piped_pc_w[31:13]};


////////////////////////////////////////////////////////////////////////////////
// Mux PC for shadow scan


////////////////////////////////////////////////////////////////////////////////
// Generate PC for instruction in D

assign pct_npc_3_w[3:2] =
       npc_3_crit_w[3:2];
assign pct_npc_2_w[3:2] =
       npc_2_crit_w[3:2];
assign pct_npc_1_w[3:2] =
       npc_1_crit_w[3:2];
assign pct_npc_0_w[3:2] =
       npc_0_crit_w[3:2];

tlu_pct_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_48c__width_47 pre_pc_d_mux      (
	.din0	({pc_0_oor_va_w		       ,
		  pc_0_w		[47:2]}),
	.din1	({pc_1_oor_va_w		       ,
		  pc_1_w		[47:2]}),
	.din2	({pc_2_oor_va_w		       ,
		  pc_2_w		[47:2]}),
	.din3	({pc_3_oor_va_w		       ,
		  pc_3_w		[47:2]}),
	.sel0	(tid_dec_buf_d		[0]	),
	.sel1	(tid_dec_buf_d		[1]	),
	.sel2	(tid_dec_buf_d		[2]	),
	.sel3	(tid_dec_buf_d		[3]	),
	.dout	({pre_pc_oor_va_d	       ,
		  pre_pc_d		[47:2]})
);

// Muxing down PSTATE.am for PC reads.  However, if reading 
// instruction VA watchpoint, then masking must NOT occur

tlu_pct_dp_nand_macro__ports_2__width_4 pstate_am_b_nand   (
	.din0	(asi_rd_pc		[3:0]	),
	.din1	(tsd_pstate_am		[3:0]	),
	.dout	(pstate_am_		[3:0]	)
);

tlu_pct_dp_nand_macro__ports_4__width_1 rd_pc_pstate_am_in_nand   (
	.din0	(pstate_am_		[0   ]	),
	.din1	(pstate_am_		[1   ]	),
	.din2	(pstate_am_		[2   ]	),
	.din3	(pstate_am_		[3   ]	),
	.dout	(rd_pc_pstate_am_in		)
);

tlu_pct_dp_msff_macro__left_20__stack_48c__width_10 tid_d_lat    (
	.scan_in(tid_d_lat_scanin),
	.scan_out(tid_d_lat_scanout),
	.din	({rd_pc_pstate_am_in	       ,
		  asi_rd_iaw		       ,
		  asi_rd_pc		[3:0],
		  dec_raw_pick_p	[3:0]}),
	.dout	({prd_pc_pstate_am	       ,
		  rd_iaw		       ,
		  rd_pc			[3:0],
		  tid_dec_d		[3:0]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_inv_macro__width_1 rd_iaw_b_inv  (
	.din	(rd_iaw				),
	.dout	(rd_iaw_			)
);

tlu_pct_dp_nand_macro__ports_2__width_1 rd_pc_pstate_am_b_nand   (
	.din0	(rd_iaw_			),
	.din1	(prd_pc_pstate_am		),
	.dout	(rd_pc_pstate_am_		)
);

tlu_pct_dp_buff_macro__stack_48c__width_4 tid_d_buf   (
	.din	(tid_dec_d		[3:0]	),
	.dout	(tid_dec_buf_d		[3:0]	)
);

tlu_pct_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_48c__width_47 pre_npc_d_mux      (
	.din0	({npc_0_oor_va_w	       ,
		  npc_0_w		[47:2]}),
	.din1	({npc_1_oor_va_w	       ,
		  npc_1_w		[47:2]}),
	.din2	({npc_2_oor_va_w	       ,
		  npc_2_w		[47:2]}),
	.din3	({npc_3_oor_va_w	       ,
		  npc_3_w		[47:2]}),
	.sel0	(tid_dec_d		[0]	),
	.sel1	(tid_dec_d		[1]	),
	.sel2	(tid_dec_d		[2]	),
	.sel3	(tid_dec_d		[3]	),
	.dout	({pre_npc_oor_va_d	       ,
		  pre_npc_d		[47:2]})
);

tlu_pct_dp_buff_macro__stack_48c__width_46 pre_npc_noncrit_d_buf   (
	.din	(pre_npc_d		[47:2]	),
	.dout	(pre_npc_noncrit_d	[47:2]	)
);

// The increment can be before the mux because you have to use the
// NPC if the count is nonzero
// Bits are separated to account for alignment with 48c stack and
// that the lower two bits are not used
tlu_pct_dp_increment_macro__width_64 pc_d_47_04_inc  (
	.cin	(1'b1				),
	.din	({12'h000		       ,
		  pre_npc_d		[47:26],
		  8'hff			       ,
		  pre_npc_d		[25:4]}),
	.dout	({npc_inc_unused	[63:52],
		  npc_inc_d		[47:26],
		  npc_inc_unused	[29:22],
		  npc_inc_d		[25:4]}),
	.cout	(npc_inc_cout_d_unused		)
);

// Must take PC if PC actually holds NPC
// If a branch in the delay slot of another branch is at decode 
//  (signified by dec_inst_cnt[01:00] being nonzero), then the PC is no longer 
//  the NPC.

tlu_pct_dp_or_macro__stack_48c__width_1 inst_cnt_nz_or   (
	.din0	(dec_inst_cnt		[1   ]	),
	.din1	(dec_inst_cnt		[0   ]	),
	.dout	(inst_cnt_nz			)
);

tlu_pct_dp_inv_macro__width_2 inst_cnt_inv_inv  (
	.din	(dec_inst_cnt		[1:0]	),
	.dout	(inst_cnt_		[1:0]	)
);

tlu_pct_dp_nand_macro__ports_3__width_3 npc_inc_0_d_nand   (
	.din0	({1'b0			       ,
		  pre_npc_d		[3:2]}),
	.din1	({3 {inst_cnt_[1]}}		),
	.din2	({3 {inst_cnt_[0]}}		),
	.dout	(npc_inc_0_d		[4:2]	)
);

tlu_pct_dp_nand_macro__ports_3__width_3 npc_inc_1_d_nand   (
	.din0	(fls_npc_if_cnt_eq_1_d	[4:2]	),
	.din1	({3 {inst_cnt_[1]}}		),
	.din2	({3 {dec_inst_cnt[0]}}		),
	.dout	(npc_inc_1_d		[4:2]	)
);

tlu_pct_dp_nand_macro__ports_3__width_3 npc_inc_2_d_nand   (
	.din0	(fls_npc_if_cnt_eq_2_d	[4:2]	),
	.din1	({3 {dec_inst_cnt[1]}}		),
	.din2	({3 {inst_cnt_[0]}}		),
	.dout	(npc_inc_2_d		[4:2]	)
);

tlu_pct_dp_nand_macro__ports_3__width_3 npc_inc_3_d_nand   (
	.din0	(fls_npc_if_cnt_eq_3_d	[4:2]	),
	.din1	({3 {dec_inst_cnt[1]}}		),
	.din2	({3 {dec_inst_cnt[0]}}		),
	.dout	(npc_inc_3_d		[4:2]	)
);

tlu_pct_dp_nand_macro__ports_4__width_3 npc_inc_d_nand   (
	.din0	(npc_inc_0_d		[4:2]	),
	.din1	(npc_inc_1_d		[4:2]	),
	.din2	(npc_inc_2_d		[4:2]	),
	.din3	(npc_inc_3_d		[4:2]	),
	.dout	({pc_4_carry_d		       ,
		  npc_inc_d		[3:2]})
);


tlu_pct_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep3   (
	.din	(tcu_muxtest			),
	.dout	(tcu_muxtest_rep3		)
);

tlu_pct_dp_mux_macro__mux_pgpe__ports_4__stack_48c__width_47 pc_d_mux     (
	.din0	({pre_npc_oor_va_d	       ,
		  npc_inc_d		[47:2]}),
	.din1	({pre_npc_oor_va_d	       ,
		  pre_npc_noncrit_d	[47:4],
		  npc_inc_d		[3:2]}),
	.din2	({pre_pc_oor_va_d	       ,
		  pre_pc_d		[47:2]}),
	.din3	({pre_npc_oor_va_d	       ,
		  pre_npc_noncrit_d	[47:2]}),
	.sel0	(pc_4_carry_d			),
	.sel1	(inst_cnt_nz			),
	.sel2	(fls_pc_is_npc			),
	.muxtst	(tcu_muxtest_rep3		),
	.dout	({pc_oor_va_d		       ,
		  pc_d			[47:2]}),
  .test(test)
);

assign tlu_pc_d[47:2] =
       pc_d[47:2];

tlu_pct_dp_buff_macro__rep_1__stack_48c__width_46 pc_noncrit_d_buf    (
	.din	(pc_d			[47:2]	),
	.dout	(pc_noncrit_d		[47:2]	)
);

assign pct_shadow_pc_d[47:2] =
       pc_noncrit_d[47:2];


////////////////////////////////////////////////////////////////////////////////
// Compare instruction watchpoint in E

tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_17 am_and     (
	.din0	({pc_oor_va_d		       ,
		  pc_noncrit_d		[47:32]}),
	.din1	({17 {fls_pstate_am_d_}}	),
	.dout	({masked_pc_oor_va_d	       ,
		  masked_pc_d		[47:32]})
);

tlu_pct_dp_msff_macro__stack_48c__width_47 pc_e_lat   (
	.scan_in(pc_e_lat_scanin),
	.scan_out(pc_e_lat_scanout),
	.din	({masked_pc_oor_va_d	       ,
		  masked_pc_d		[47:32],
		  pc_noncrit_d		[31:2]}),
	.dout	({pc_oor_va_e		       ,
		  pc_e			[47:2]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign pct_pc_oor_va_e =
       pc_oor_va_e;

tlu_pct_dp_msff_macro__stack_48c__width_47 iaw_lat   ( // FS:wmr_protect
	.scan_in(iaw_lat_wmr_scanin),
	.scan_out(iaw_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_iaw			),
	.din	({asi_wr_data		[0   ],
		  asi_wr_data		[47:2]}),
	.dout	({iaw_en		       ,
		  iaw_va		[47:2]}),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_pct_dp_buff_macro__rep_1__stack_48c__width_17 wr_data_buf    (
	.din	({asi_wr_data		[1:0],
		  asi_wr_data		[16:2]}),
	.dout	({pct_trl_wr_data	[1:0],
		  pct_trl_wr_data	[16:2]})
);

tlu_pct_dp_cmp_macro__width_16 iaw_47_34_cmp  (
	.din0	({1'b0			       ,
		  1'b1			       ,
		  pc_e			[47:34]}),
	.din1	({1'b0			       ,
		  iaw_en		       ,
		  iaw_va		[47:34]}),
	.dout	(pct_iaw_exc_e		[1   ]	)
);

tlu_pct_dp_cmp_macro__width_32 iaw_33_02_cmp  (
	.din0	(pc_e			[33:2]	),
	.din1	(iaw_va			[33:2]	),
	.dout	(pct_iaw_exc_e		[0   ]	)
);


////////////////////////////////////////////////////////////////////////////////
// Mux PC for ASI reads

tlu_pct_dp_mux_macro__mux_aonpe__ports_5__stack_48c__width_47 asi_pc_mux     (
	.din0	({1'b0, pc_0_w		[47:2]}),
	.din1	({1'b0, pc_1_w		[47:2]}),
	.din2	({1'b0, pc_2_w		[47:2]}),
	.din3	({1'b0, pc_3_w		[47:2]}),
	.din4	({iaw_en, iaw_va	[47:2]}),
	.sel0	(rd_pc			[0   ]	),
	.sel1	(rd_pc			[1   ]	),
	.sel2	(rd_pc			[2   ]	),
	.sel3	(rd_pc			[3   ]	),
	.sel4	(rd_iaw				),
	.dout	(asi_data		[48:2]	)
);

tlu_pct_dp_nand_macro__ports_2__stack_48c__width_47 asi_data_0_b_nand    (
        .din0	({{17 {rd_pc_pstate_am_}}      ,
		  {30 {1'b1}}		       }),
	.din1	(asi_data		[48:2]	),
	.dout	(asi_data_0_		[48:2]	)
);

tlu_pct_dp_nand_macro__ports_2__stack_48c__width_47 asi_data_nand    (
	.din0	({1'b1, tsd_asi_data_	[47:2]}),
	.din1	(asi_data_0_		[48:2]	),
	.dout	(pct_asi_data		[48:2]	)
);


// fixscan start:
assign target_b_lat_scanin       = scan_in                  ;
assign pc_3_w_lat_scanin         = target_b_lat_scanout     ;
assign pc_2_w_lat_scanin         = pc_3_w_lat_scanout       ;
assign pc_1_w_lat_scanin         = pc_2_w_lat_scanout       ;
assign pc_0_w_lat_scanin         = pc_1_w_lat_scanout       ;
assign tnpc_lat_scanin           = pc_0_w_lat_scanout       ;
assign npc_3_w_lat_scanin        = tnpc_lat_scanout         ;
assign npc_2_w_lat_scanin        = npc_3_w_lat_scanout      ;
assign npc_1_w_lat_scanin        = npc_2_w_lat_scanout      ;
assign npc_0_w_lat_scanin        = npc_1_w_lat_scanout      ;
assign npc_b_mux_scanin          = npc_0_w_lat_scanout      ;
assign trap_pc_lat_scanin        = npc_b_mux_scanout        ;
assign tid_d_lat_scanin          = trap_pc_lat_scanout      ;
assign pc_e_lat_scanin           = tid_d_lat_scanout        ;
assign scan_out                  = pc_e_lat_scanout         ;

assign iaw_lat_wmr_scanin        = wmr_scan_in              ;
assign wmr_scan_out              = iaw_lat_wmr_scanout      ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_pct_dp_msff_macro__stack_48c__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_pct_dp_and_macro__ports_2__stack_48c__width_46 (
  din0, 
  din1, 
  dout);
  input [45:0] din0;
  input [45:0] din1;
  output [45:0] dout;


and2 #(46)  d0_0 (
.in0(din0[45:0]),
.in1(din1[45:0]),
.out(dout[45:0])
);


endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__stack_48c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [46:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [45:0] so;

  input [46:0] din0;
  input [46:0] din1;
  input [46:0] din2;
  input [46:0] din3;
  input [46:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [46:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(47)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[46:0]),
  .in1(din1[46:0]),
  .in2(din2[46:0]),
  .in3(din3[46:0]),
  .in4(din4[46:0]),
.dout(muxout[46:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(47)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[46:0]),
.si({scan_in,so[45:0]}),
.so({so[45:0],scan_out}),
.q(dout[46:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_pct_dp_msff_macro__minbuff_1__stack_48c__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire [47:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din0;
  input [47:0] din1;
  input [47:0] din2;
  input [47:0] din3;
  input [47:0] din4;
  input [47:0] din5;
  input [47:0] din6;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_penc7_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6)
);

mux7s #(48)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
  .in5(din5[47:0]),
  .in6(din6[47:0]),
.dout(muxout[47:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__stack_48c__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


buff #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_pct_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_48c__width_47 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [46:0] din0;
  input sel0;
  input [46:0] din1;
  input sel1;
  input [46:0] din2;
  input sel2;
  input [46:0] din3;
  input sel3;
  output [46:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(47)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[46:0]),
  .in1(din1[46:0]),
  .in2(din2[46:0]),
  .in3(din3[46:0]),
.dout(dout[46:0])
);


endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__stack_48c__width_46 (
  din, 
  dout);
  input [45:0] din;
  output [45:0] dout;


buff #(46)  d0_0 (
.in(din[45:0]),
.out(dout[45:0])
);


endmodule


//
//   increment macro 
//
//


module tlu_pct_dp_increment_macro__width_32 (
  din, 
  cin, 
  dout, 
  cout);
  input [31:0] din;
  input cin;
  output [31:0] dout;
  output cout;


incr #(32)  m0_0 (
.cin(cin),
.in(din[31:0]),
.out(dout[31:0]),
.cout(cout)
);


endmodule


//
//   increment macro 
//
//


module tlu_pct_dp_increment_macro__width_16 (
  din, 
  cin, 
  dout, 
  cout);
  input [15:0] din;
  input cin;
  output [15:0] dout;
  output cout;


incr #(16)  m0_0 (
.cin(cin),
.in(din[15:0]),
.out(dout[15:0]),
.cout(cout)
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_pct_dp_msff_macro__mux_pgpe__ports_2__stack_48c__width_46 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0_unused;
wire psel1;
wire [45:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [44:0] so;

  input [45:0] din0;
  input [45:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [45:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(46)  d1_0 (
  .sel(psel1),
  .in0(din0[45:0]),
  .in1(din1[45:0]),
.dout(muxout[45:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(46)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[45:0]),
.si({scan_in,so[44:0]}),
.so({so[44:0],scan_out}),
.q(dout[45:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_pct_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_47 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [46:0] din0;
  input sel0;
  input [46:0] din1;
  input sel1;
  input [46:0] din2;
  input sel2;
  input [46:0] din3;
  input sel3;
  output [46:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(47)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[46:0]),
  .in1(din1[46:0]),
  .in2(din2[46:0]),
  .in3(din3[46:0]),
.dout(dout[46:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output [15:0] dout;


and2 #(16)  d0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout[15:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_pct_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_48 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [47:0] din0;
  input sel0;
  input [47:0] din1;
  input sel1;
  input [47:0] din2;
  input sel2;
  input [47:0] din3;
  input sel3;
  output [47:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(48)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
.dout(dout[47:0])
);


endmodule


//
//   invert macro
//
//


module tlu_pct_dp_inv_macro__stack_48c__width_5 (
  din, 
  dout);
  input [4:0] din;
  output [4:0] dout;


inv #(5)  d0_0 (
.in(din[4:0]),
.out(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_pct_dp_msff_macro__mux_aope__ports_8__stack_48c__width_48 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;
wire [47:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din0;
  input [47:0] din1;
  input [47:0] din2;
  input [47:0] din3;
  input [47:0] din4;
  input [47:0] din5;
  input [47:0] din6;
  input [47:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_penc8_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(48)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
  .in5(din5[47:0]),
  .in6(din6[47:0]),
  .in7(din7[47:0]),
.dout(muxout[47:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_pct_dp_mux_macro__left_3__mux_aonpe__ports_4__stack_48c__width_43 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [42:0] din0;
  input sel0;
  input [42:0] din1;
  input sel1;
  input [42:0] din2;
  input sel2;
  input [42:0] din3;
  input sel3;
  output [42:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(43)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[42:0]),
  .in1(din1[42:0]),
  .in2(din2[42:0]),
  .in3(din3[42:0]),
.dout(dout[42:0])
);


endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__left_3__rep_1__stack_48c__width_27 (
  din, 
  dout);
  input [26:0] din;
  output [26:0] dout;


buff #(27)  d0_0 (
.in(din[26:0]),
.out(dout[26:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_pct_dp_nand_macro__ports_2__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


nand2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_pct_dp_nand_macro__ports_4__width_1 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  input [0:0] din3;
  output [0:0] dout;


nand4 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.in3(din3[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_pct_dp_msff_macro__left_20__stack_48c__width_10 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [8:0] so;

  input [9:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [9:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


//
//   invert macro
//
//


module tlu_pct_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_pct_dp_nand_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__stack_48c__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   increment macro 
//
//


module tlu_pct_dp_increment_macro__width_64 (
  din, 
  cin, 
  dout, 
  cout);
  input [63:0] din;
  input cin;
  output [63:0] dout;
  output cout;


incr #(64)  m0_0 (
.cin(cin),
.in(din[63:0]),
.out(dout[63:0]),
.cout(cout)
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_pct_dp_or_macro__stack_48c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module tlu_pct_dp_inv_macro__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


inv #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_pct_dp_nand_macro__ports_3__width_3 (
  din0, 
  din1, 
  din2, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  output [2:0] dout;


nand3 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.in2(din2[2:0]),
.out(dout[2:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_pct_dp_nand_macro__ports_4__width_3 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  input [2:0] din2;
  input [2:0] din3;
  output [2:0] dout;


nand4 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.in2(din2[2:0]),
.in3(din3[2:0]),
.out(dout[2:0])
);


endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__dbuff_48x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_pct_dp_mux_macro__mux_pgpe__ports_4__stack_48c__width_47 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [46:0] din0;
  input [46:0] din1;
  input [46:0] din2;
  input [46:0] din3;
  input sel0;
  input sel1;
  input sel2;
  input muxtst;
  input test;
  output [46:0] dout;


cl_dp1_penc4_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
  .test(test)
);

mux4 #(47)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[46:0]),
  .in1(din1[46:0]),
  .in2(din2[46:0]),
  .in3(din3[46:0]),
.dout(dout[46:0]),
  .muxtst(muxtst)
);


endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__rep_1__stack_48c__width_46 (
  din, 
  dout);
  input [45:0] din;
  output [45:0] dout;


buff #(46)  d0_0 (
.in(din[45:0]),
.out(dout[45:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_17 (
  din0, 
  din1, 
  dout);
  input [16:0] din0;
  input [16:0] din1;
  output [16:0] dout;


and2 #(17)  d0_0 (
.in0(din0[16:0]),
.in1(din1[16:0]),
.out(dout[16:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_pct_dp_msff_macro__stack_48c__width_47 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [45:0] so;

  input [46:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [46:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(47)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[46:0]),
.si({scan_in,so[45:0]}),
.so({so[45:0],scan_out}),
.q(dout[46:0])
);


endmodule


//
//   buff macro
//
//


module tlu_pct_dp_buff_macro__rep_1__stack_48c__width_17 (
  din, 
  dout);
  input [16:0] din;
  output [16:0] dout;


buff #(17)  d0_0 (
.in(din[16:0]),
.out(dout[16:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module tlu_pct_dp_cmp_macro__width_16 (
  din0, 
  din1, 
  dout);
  input [15:0] din0;
  input [15:0] din1;
  output dout;


cmp #(16)  m0_0 (
.in0(din0[15:0]),
.in1(din1[15:0]),
.out(dout)
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module tlu_pct_dp_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_pct_dp_mux_macro__mux_aonpe__ports_5__stack_48c__width_47 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [46:0] din0;
  input sel0;
  input [46:0] din1;
  input sel1;
  input [46:0] din2;
  input sel2;
  input [46:0] din3;
  input sel3;
  input [46:0] din4;
  input sel4;
  output [46:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(47)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[46:0]),
  .in1(din1[46:0]),
  .in2(din2[46:0]),
  .in3(din3[46:0]),
  .in4(din4[46:0]),
.dout(dout[46:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_pct_dp_nand_macro__ports_2__stack_48c__width_47 (
  din0, 
  din1, 
  dout);
  input [46:0] din0;
  input [46:0] din1;
  output [46:0] dout;


nand2 #(47)  d0_0 (
.in0(din0[46:0]),
.in1(din1[46:0]),
.out(dout[46:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_ras_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_ras_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lsu_tlu_pmen, 
  ftu_excp_way_d, 
  ftu_excp_tid_d, 
  ftu_excp_way_valid_d, 
  dec_exc0_m, 
  dec_exc1_m, 
  dec_icache_perr_m, 
  dec_tid0_m, 
  dec_tid1_m, 
  dec_inst_valid_m, 
  dec_fgu_inst_m, 
  dec_lsu_inst_m, 
  dec_flush_b, 
  fls_irf_cecc_b, 
  fls_irf_uecc_b, 
  fls_kill_irf_ecc_w, 
  exu0_ecc_addr_m, 
  exu1_ecc_addr_m, 
  exu0_ecc_check_m, 
  exu1_ecc_check_m, 
  fls_f_cecc_w, 
  fls_f_uecc_w, 
  fgu_ecc_addr_fx2, 
  fgu_ecc_check_fx2, 
  fgu_pdist_beat2_fx1, 
  lsu_tlu_twocycle_m, 
  lsu_block_store_b, 
  fls_load_dsfar, 
  fls_ipe_dme_request, 
  lsu_dttp_err_b, 
  lsu_dtdp_err_b, 
  lsu_dtmh_err_b, 
  lsu_dcmh_err_g, 
  lsu_dcvp_err_g, 
  lsu_dctp_err_g, 
  lsu_dcdp_err_g, 
  lsu_dcl2c_err_g, 
  lsu_dcl2u_err_g, 
  lsu_dcl2nd_err_g, 
  lsu_dcsoc_err_g, 
  lsu_dcerr_tid_g, 
  lsu_dcerr_sfar_g, 
  lsu_sbdlc_err_g, 
  lsu_sbdlu_err_g, 
  lsu_sbdpc_err_g, 
  lsu_sbdpu_err_g, 
  lsu_sbapp_err_g, 
  lsu_sbdiou_err_g, 
  lsu_stberr_tid_g, 
  lsu_stberr_index_g, 
  lsu_stberr_priv_g, 
  lsu_stb_flush_g, 
  cel_tccp, 
  cel_tcup, 
  cel_syndrome, 
  tlu_tca_tid, 
  tlu_tca_index, 
  tlu_tsac, 
  tlu_tsau, 
  asi_tsac, 
  asi_tsau, 
  asi_tsacu_tid, 
  tlu_tccd, 
  tlu_tcud, 
  tlu_tca_index_0, 
  tlu_tca_index_1, 
  tsd_pc_0_w, 
  tsd_pc_1_w, 
  fls_flush, 
  fls_disrupting_flush_w, 
  trl_gl0, 
  trl_gl1, 
  trl_gl2, 
  trl_gl3, 
  trl_gl4, 
  trl_gl5, 
  trl_gl6, 
  trl_gl7, 
  mmu_asi_cecc, 
  mmu_asi_uecc, 
  mmu_asi_index, 
  mmu_asi_mra_not_sca, 
  mmu_i_l2cerr, 
  mmu_d_l2cerr, 
  mmu_i_eccerr, 
  mmu_d_eccerr, 
  mmu_thr0_err_type, 
  mmu_thr1_err_type, 
  mmu_thr2_err_type, 
  mmu_thr3_err_type, 
  mmu_thr4_err_type, 
  mmu_thr5_err_type, 
  mmu_thr6_err_type, 
  mmu_thr7_err_type, 
  mmu_thr0_err_index, 
  mmu_thr1_err_index, 
  mmu_thr2_err_index, 
  mmu_thr3_err_index, 
  mmu_thr4_err_index, 
  mmu_thr5_err_index, 
  mmu_thr6_err_index, 
  mmu_thr7_err_index, 
  spu_tlu_mamu_err_req_v, 
  spu_tlu_mamu_err_req, 
  spu_tlu_ma_int_req, 
  spu_tlu_cwq_int_req, 
  spu_tlu_l2_error, 
  cxi_l2_soc_sre, 
  cxi_l2_soc_err_type, 
  cxi_l2_soc_tid, 
  cxi_l2_err, 
  cxi_soc_err, 
  asi_rd_isfsr, 
  asi_rd_dsfsr, 
  asi_rd_dsfar, 
  asi_rd_desr, 
  asi_rd_fesr, 
  asi_rd_tid, 
  asi_wr_isfsr, 
  asi_wr_dsfsr, 
  asi_wr_data, 
  dfd_desr_f, 
  dfd_desr_s, 
  dfd_fesr_f, 
  dfd_fesr_priv_0, 
  dfd_fesr_priv_1, 
  dfd_fesr_priv_2, 
  dfd_fesr_priv_3, 
  dfd_fesr_priv_4, 
  dfd_fesr_priv_5, 
  dfd_fesr_priv_6, 
  dfd_fesr_priv_7, 
  wmr_scan_out, 
  scan_out, 
  ras_asi_data, 
  ras_dsfar_0, 
  ras_dsfar_1, 
  ras_dsfar_2, 
  ras_dsfar_3, 
  ras_dsfar_4, 
  ras_dsfar_5, 
  ras_dsfar_6, 
  ras_dsfar_7, 
  ras_dsfar_sel_lsu_va, 
  ras_dsfar_sel_ras, 
  ras_dsfar_sel_tsa, 
  ras_rd_dsfar, 
  ras_desr_et_0, 
  ras_desr_et_1, 
  ras_desr_et_2, 
  ras_desr_et_3, 
  ras_desr_et_4, 
  ras_desr_et_5, 
  ras_desr_et_6, 
  ras_desr_et_7, 
  ras_desr_ea_0, 
  ras_desr_ea_1, 
  ras_desr_ea_2, 
  ras_desr_ea_3, 
  ras_desr_ea_4, 
  ras_desr_ea_5, 
  ras_desr_ea_6, 
  ras_desr_ea_7, 
  ras_desr_me_0, 
  ras_desr_me_1, 
  ras_desr_me_2, 
  ras_desr_me_3, 
  ras_desr_me_4, 
  ras_desr_me_5, 
  ras_desr_me_6, 
  ras_desr_me_7, 
  ras_desr_en, 
  ras_write_desr_1st, 
  ras_write_desr_2nd, 
  ras_rd_desr, 
  ras_fesr_et_0, 
  ras_fesr_et_1, 
  ras_fesr_et_2, 
  ras_fesr_et_3, 
  ras_fesr_et_4, 
  ras_fesr_et_5, 
  ras_fesr_et_6, 
  ras_fesr_et_7, 
  ras_fesr_ea_0, 
  ras_fesr_ea_1, 
  ras_fesr_ea_2, 
  ras_fesr_ea_3, 
  ras_fesr_ea_4, 
  ras_fesr_ea_5, 
  ras_fesr_ea_6, 
  ras_fesr_ea_7, 
  ras_fesr_en, 
  ras_write_fesr, 
  ras_fesr_priv, 
  ras_update_priv, 
  ras_rd_fesr, 
  ras_precise_error, 
  ras_disrupting_error, 
  ras_deferred_error);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk;
wire l1en_any_b2w;
wire [1:0] inst_valid_b;
wire w_en;
wire w1_en;
wire l1clk_pm1;
wire l1en_pm2;
wire excp_way_valid;
wire l1clk_pm2;
wire [1:0] twocycle_inst_m;
wire twocycle_inst_b_lat_scanin;
wire twocycle_inst_b_lat_scanout;
wire [1:0] ptwocycle_inst_b;
wire [1:0] twocycle_inst_b;
wire [1:0] fgu_inst_b;
wire [1:0] inst_valid_m;
wire inst_valid_b_lat_scanin;
wire inst_valid_b_lat_scanout;
wire w_en_in;
wire w_en_lat_scanin;
wire w_en_lat_scanout;
wire w1_en_lat_scanin;
wire w1_en_lat_scanout;
wire [1:0] flush_b;
wire [7:0] tid_dec_b;
wire [1:0] inst_valid_w_in;
wire inst_valid_w_lat_scanin;
wire inst_valid_w_lat_scanout;
wire [1:0] pre_inst_valid_w;
wire [7:0] block_store_w_in;
wire block_store_w_lat_scanin;
wire block_store_w_lat_scanout;
wire [7:0] pblock_store_w;
wire [7:0] block_store_w;
wire seen_bsee;
wire [1:0] inst_valid_w;
wire [1:0] tid1_m;
wire [1:0] tid1_b;
wire tid1_b_lat_scanin;
wire tid1_b_lat_scanout;
wire [1:0] tid0_m;
wire [1:0] tid0_b;
wire tid0_b_lat_scanin;
wire tid0_b_lat_scanout;
wire tid1_w_lat_scanin;
wire tid1_w_lat_scanout;
wire [1:0] tid1_w;
wire tid0_w_lat_scanin;
wire tid0_w_lat_scanout;
wire [1:0] tid0_w;
wire [7:0] tid_dec_w;
wire [1:0] fgu_inst_m;
wire fgu_inst_b_lat_scanin;
wire fgu_inst_b_lat_scanout;
wire fgu_inst_w_lat_scanin;
wire fgu_inst_w_lat_scanout;
wire [1:0] pfgu_inst_w;
wire [1:0] fgu_inst_w;
wire [1:0] lsu_inst_m;
wire lsu_inst_b_lat_scanin;
wire lsu_inst_b_lat_scanout;
wire [1:0] lsu_inst_b;
wire [1:0] ittp_m;
wire [1:0] ittm_m;
wire [1:0] itdp_m;
wire [1:0] icl2u_m;
wire [1:0] icl2nd_m;
wire [2:0] i_isfsr1_m;
wire [2:0] i_isfsr0_m;
wire i_isfsr1_b_lat_scanin;
wire i_isfsr1_b_lat_scanout;
wire [2:0] i_isfsr1_b;
wire i_isfsr0_b_lat_scanin;
wire i_isfsr0_b_lat_scanout;
wire [2:0] i_isfsr0_b;
wire [1:0] icvp_m;
wire [1:0] ictp_m;
wire [1:0] ictm_m;
wire [1:0] icl2c_m;
wire [1:0] icdp_m;
wire [3:0] i_desr1_m;
wire [3:0] i_desr0_m;
wire i_desr1_b_lat_scanin;
wire i_desr1_b_lat_scanout;
wire [3:0] i_desr1_b;
wire i_desr0_b_lat_scanin;
wire i_desr0_b_lat_scanout;
wire [3:0] i_desr0_b;
wire irf0_ecc_addr_b_lat_scanin;
wire irf0_ecc_addr_b_lat_scanout;
wire [4:0] irf0_ecc_addr_b;
wire irf1_ecc_addr_b_lat_scanin;
wire irf1_ecc_addr_b_lat_scanout;
wire [4:0] irf1_ecc_addr_b;
wire irf0_ecc_check_b_lat_scanin;
wire irf0_ecc_check_b_lat_scanout;
wire [7:0] irf0_ecc_check_b;
wire irf1_ecc_check_b_lat_scanin;
wire irf1_ecc_check_b_lat_scanout;
wire [7:0] irf1_ecc_check_b;
wire i_isfsr1_w_lat_scanin;
wire i_isfsr1_w_lat_scanout;
wire [2:0] i_isfsr1_w;
wire i_isfsr0_w_lat_scanin;
wire i_isfsr0_w_lat_scanout;
wire [2:0] i_isfsr0_w;
wire i_desr1_w_lat_scanin;
wire i_desr1_w_lat_scanout;
wire [3:0] i_desr1_w;
wire i_desr0_w_lat_scanin;
wire i_desr0_w_lat_scanout;
wire [3:0] i_desr0_w;
wire [1:0] irfu_b;
wire [1:0] irfc_b;
wire [1:0] dtmh_b;
wire [1:0] dttp_b;
wire [1:0] dtdp_b;
wire irfu_w_lat_scanin;
wire irfu_w_lat_scanout;
wire [1:0] pirfu_w;
wire [1:0] irfu_w;
wire irfc_w_lat_scanin;
wire irfc_w_lat_scanout;
wire [1:0] pirfc_w;
wire [1:0] irfc_w;
wire [1:0] pfrfu_w;
wire [1:0] pfrfc_w;
wire [1:0] frfu_w;
wire [1:0] frfc_w;
wire seen_bsee_in;
wire seen_bsee_lat_scanin;
wire seen_bsee_lat_scanout;
wire dttp_w_lat_scanin;
wire dttp_w_lat_scanout;
wire [1:0] pdttp_w;
wire [1:0] dttp_w;
wire dtmh_w_lat_scanin;
wire dtmh_w_lat_scanout;
wire [1:0] pdtmh_w;
wire [1:0] dtmh_w;
wire dtdp_w_lat_scanin;
wire dtdp_w_lat_scanout;
wire [1:0] pdtdp_w;
wire [1:0] dtdp_w;
wire irf0_ecc_addr_w_lat_scanin;
wire irf0_ecc_addr_w_lat_scanout;
wire [4:0] irf0_ecc_addr_w;
wire irf1_ecc_addr_w_lat_scanin;
wire irf1_ecc_addr_w_lat_scanout;
wire [4:0] irf1_ecc_addr_w;
wire irf0_ecc_check_w_lat_scanin;
wire irf0_ecc_check_w_lat_scanout;
wire [7:0] irf0_ecc_check_w;
wire irf1_ecc_check_w_lat_scanin;
wire irf1_ecc_check_w_lat_scanout;
wire [7:0] irf1_ecc_check_w;
wire frf_ecc_addr_w_lat_scanin;
wire frf_ecc_addr_w_lat_scanout;
wire [5:0] frf_ecc_addr_w;
wire frf_ecc_check_w_lat_scanin;
wire frf_ecc_check_w_lat_scanout;
wire [13:0] frf_ecc_check_w;
wire [2:0] pipe_isfsr_7;
wire [2:0] pipe_isfsr_6;
wire [2:0] pipe_isfsr_5;
wire [2:0] pipe_isfsr_4;
wire [2:0] pipe_isfsr_3;
wire [2:0] pipe_isfsr_2;
wire [2:0] pipe_isfsr_1;
wire [2:0] pipe_isfsr_0;
wire [2:0] pipe_dsfsr1_w;
wire [2:0] pipe_dsfsr0_w;
wire [1:0] gl1_w;
wire [1:0] gl0_w;
wire [19:0] pipe_dsfar1_w;
wire [19:0] pipe_dsfar0_w;
wire [1:0] ecc_w;
wire ecc_w1_lat_scanin;
wire ecc_w1_lat_scanout;
wire [1:0] ecc_w1;
wire [1:0] tid1_w1_in;
wire tid1_w1_lat_scanin;
wire tid1_w1_lat_scanout;
wire [1:0] tid1_w1;
wire [1:0] tid0_w1_in;
wire tid0_w1_lat_scanin;
wire tid0_w1_lat_scanout;
wire [1:0] tid0_w1;
wire pipe_dsfsr1_lat_scanin;
wire pipe_dsfsr1_lat_scanout;
wire [2:0] pipe_dsfsr1;
wire pipe_dsfsr0_lat_scanin;
wire pipe_dsfsr0_lat_scanout;
wire [2:0] pipe_dsfsr0;
wire pipe_dsfar1_lat_scanin;
wire pipe_dsfar1_lat_scanout;
wire [19:0] pipe_dsfar1;
wire pipe_dsfar0_lat_scanin;
wire pipe_dsfar0_lat_scanout;
wire [19:0] pipe_dsfar0;
wire [7:0] tid_dec_w1;
wire [2:0] pipe_dsfsr_7;
wire [2:0] pipe_dsfsr_6;
wire [2:0] pipe_dsfsr_5;
wire [2:0] pipe_dsfsr_4;
wire [2:0] pipe_dsfsr_3;
wire [2:0] pipe_dsfsr_2;
wire [2:0] pipe_dsfsr_1;
wire [2:0] pipe_dsfsr_0;
wire [19:0] pipe_dsfar_7;
wire [19:0] pipe_dsfar_6;
wire [19:0] pipe_dsfar_5;
wire [19:0] pipe_dsfar_4;
wire [19:0] pipe_dsfar_3;
wire [19:0] pipe_dsfar_2;
wire [19:0] pipe_dsfar_1;
wire [19:0] pipe_dsfar_0;
wire [7:0] dsfar_sel_lsu_va_for_error;
wire load_dsfar_lat_scanin;
wire load_dsfar_lat_scanout;
wire [7:0] load_dsfar;
wire [3:0] i_desr1_w1_in;
wire [3:0] i_desr0_w1_in;
wire i_desr1_w1_lat_scanin;
wire i_desr1_w1_lat_scanout;
wire [3:0] i_desr1_w1;
wire i_desr0_w1_lat_scanin;
wire i_desr0_w1_lat_scanout;
wire [3:0] i_desr0_w1;
wire [5:0] pipe_desr_et_7;
wire [5:0] pipe_desr_et_6;
wire [5:0] pipe_desr_et_5;
wire [5:0] pipe_desr_et_4;
wire [5:0] pipe_desr_et_3;
wire [5:0] pipe_desr_et_2;
wire [5:0] pipe_desr_et_1;
wire [5:0] pipe_desr_et_0;
wire excp_way_lat_scanin;
wire excp_way_lat_scanout;
wire [2:0] excp_tid;
wire [2:0] excp_way;
wire [7:0] sel_ftu_excp_way;
wire [2:0] ic_way7_in;
wire [2:0] ic_way7;
wire [2:0] ic_way6_in;
wire [2:0] ic_way6;
wire [2:0] ic_way5_in;
wire [2:0] ic_way5;
wire [2:0] ic_way4_in;
wire [2:0] ic_way4;
wire [2:0] ic_way3_in;
wire [2:0] ic_way3;
wire [2:0] ic_way2_in;
wire [2:0] ic_way2;
wire [2:0] ic_way1_in;
wire [2:0] ic_way1;
wire [2:0] ic_way0_in;
wire [2:0] ic_way0;
wire ic_way7_lat_scanin;
wire ic_way7_lat_scanout;
wire ic_way6_lat_scanin;
wire ic_way6_lat_scanout;
wire ic_way5_lat_scanin;
wire ic_way5_lat_scanout;
wire ic_way4_lat_scanin;
wire ic_way4_lat_scanout;
wire ic_way3_lat_scanin;
wire ic_way3_lat_scanout;
wire ic_way2_lat_scanin;
wire ic_way2_lat_scanout;
wire ic_way1_lat_scanin;
wire ic_way1_lat_scanout;
wire ic_way0_lat_scanin;
wire ic_way0_lat_scanout;
wire pc_1_w1_lat_scanin;
wire pc_1_w1_lat_scanout;
wire [10:5] pc_1_w1;
wire pc_0_w1_lat_scanin;
wire pc_0_w1_lat_scanout;
wire [10:5] pc_0_w1;
wire [8:0] pipe_desr_ea_7;
wire [8:0] pipe_desr_ea_6;
wire [8:0] pipe_desr_ea_5;
wire [8:0] pipe_desr_ea_4;
wire [8:0] pipe_desr_ea_3;
wire [8:0] pipe_desr_ea_2;
wire [8:0] pipe_desr_ea_1;
wire [8:0] pipe_desr_ea_0;
wire itmu_7;
wire itmu_6;
wire itmu_5;
wire itmu_4;
wire itmu_3;
wire itmu_2;
wire itmu_1;
wire itmu_0;
wire itl2u_7;
wire itl2u_6;
wire itl2u_5;
wire itl2u_4;
wire itl2u_3;
wire itl2u_2;
wire itl2u_1;
wire itl2u_0;
wire itl2nd_7;
wire itl2nd_6;
wire itl2nd_5;
wire itl2nd_4;
wire itl2nd_3;
wire itl2nd_2;
wire itl2nd_1;
wire itl2nd_0;
wire [2:0] m_isfsr_7;
wire [2:0] m_isfsr_6;
wire [2:0] m_isfsr_5;
wire [2:0] m_isfsr_4;
wire [2:0] m_isfsr_3;
wire [2:0] m_isfsr_2;
wire [2:0] m_isfsr_1;
wire [2:0] m_isfsr_0;
wire dtmu_7;
wire dtmu_6;
wire dtmu_5;
wire dtmu_4;
wire dtmu_3;
wire dtmu_2;
wire dtmu_1;
wire dtmu_0;
wire dtl2u_7;
wire dtl2u_6;
wire dtl2u_5;
wire dtl2u_4;
wire dtl2u_3;
wire dtl2u_2;
wire dtl2u_1;
wire dtl2u_0;
wire dtl2nd_7;
wire dtl2nd_6;
wire dtl2nd_5;
wire dtl2nd_4;
wire dtl2nd_3;
wire dtl2nd_2;
wire dtl2nd_1;
wire dtl2nd_0;
wire [2:0] m_dsfsr_7;
wire [2:0] m_dsfsr_6;
wire [2:0] m_dsfsr_5;
wire [2:0] m_dsfsr_4;
wire [2:0] m_dsfsr_3;
wire [2:0] m_dsfsr_2;
wire [2:0] m_dsfsr_1;
wire [2:0] m_dsfsr_0;
wire [2:0] m_dsfar_7;
wire [2:0] m_dsfar_6;
wire [2:0] m_dsfar_5;
wire [2:0] m_dsfar_4;
wire [2:0] m_dsfar_3;
wire [2:0] m_dsfar_2;
wire [2:0] m_dsfar_1;
wire [2:0] m_dsfar_0;
wire it2lc_lat_scanin;
wire it2lc_lat_scanout;
wire [7:0] m_i_l2cerr;
wire dt2lc_lat_scanin;
wire dt2lc_lat_scanout;
wire [7:0] m_d_l2cerr;
wire itl2c_7;
wire itl2c_6;
wire itl2c_5;
wire itl2c_4;
wire itl2c_3;
wire itl2c_2;
wire itl2c_1;
wire itl2c_0;
wire dtl2c_7;
wire dtl2c_6;
wire dtl2c_5;
wire dtl2c_4;
wire dtl2c_3;
wire dtl2c_2;
wire dtl2c_1;
wire dtl2c_0;
wire [5:0] m_desr_et_7;
wire [5:0] m_desr_et_6;
wire [5:0] m_desr_et_5;
wire [5:0] m_desr_et_4;
wire [5:0] m_desr_et_3;
wire [5:0] m_desr_et_2;
wire [5:0] m_desr_et_1;
wire [5:0] m_desr_et_0;
wire [2:0] a_tid;
wire [7:0] a_dec_tid;
wire mrau;
wire scac;
wire scau;
wire tca_error_lat_scanin;
wire tca_error_lat_scanout;
wire tccp;
wire tcup;
wire [2:0] tca_tid;
wire [7:0] tca_dec_tid;
wire [3:0] a_dsfsr;
wire [3:0] tca_dsfsr;
wire [3:0] a_dsfsr_7;
wire [3:0] a_dsfsr_6;
wire [3:0] a_dsfsr_5;
wire [3:0] a_dsfsr_4;
wire [3:0] a_dsfsr_3;
wire [3:0] a_dsfsr_2;
wire [3:0] a_dsfsr_1;
wire [3:0] a_dsfsr_0;
wire [10:0] a_dsfar;
wire [10:0] tca_dsfar;
wire [10:0] a_dsfar_7;
wire [10:0] a_dsfar_6;
wire [10:0] a_dsfar_5;
wire [10:0] a_dsfar_4;
wire [10:0] a_dsfar_3;
wire [10:0] a_dsfar_2;
wire [10:0] a_dsfar_1;
wire [10:0] a_dsfar_0;
wire [7:0] ta_dec_tid;
wire [7:0] tsac;
wire [7:0] tsau;
wire [3:0] t_dsfsr_7;
wire [3:0] t_dsfsr_6;
wire [3:0] t_dsfsr_5;
wire [3:0] t_dsfsr_4;
wire [3:0] t_dsfsr_3;
wire [3:0] t_dsfsr_2;
wire [3:0] t_dsfsr_1;
wire [3:0] t_dsfsr_0;
wire l_dsfar_lat_scanin;
wire l_dsfar_lat_scanout;
wire [8:0] l_dsfar;
wire l_tid_lat_scanin;
wire l_tid_lat_scanout;
wire [2:0] l_tid;
wire dcl2c_lat_scanin;
wire dcl2c_lat_scanout;
wire dcl2c;
wire dcl2u_lat_scanin;
wire dcl2u_lat_scanout;
wire dcl2u;
wire dcl2nd_lat_scanin;
wire dcl2nd_lat_scanout;
wire dcl2nd;
wire dcsoc_lat_scanin;
wire dcsoc_lat_scanout;
wire dcsoc;
wire [7:0] l_dec_tid;
wire [2:0] l_dsfsr;
wire [2:0] l_dsfsr_7;
wire [2:0] l_dsfsr_6;
wire [2:0] l_dsfsr_5;
wire [2:0] l_dsfsr_4;
wire [2:0] l_dsfsr_3;
wire [2:0] l_dsfsr_2;
wire [2:0] l_dsfsr_1;
wire [2:0] l_dsfsr_0;
wire [8:0] l_dsfar_7;
wire [8:0] l_dsfar_6;
wire [8:0] l_dsfar_5;
wire [8:0] l_dsfar_4;
wire [8:0] l_dsfar_3;
wire [8:0] l_dsfar_2;
wire [8:0] l_dsfar_1;
wire [8:0] l_dsfar_0;
wire [5:0] l_desr_et;
wire [5:0] l_desr_et_7;
wire [5:0] l_desr_et_6;
wire [5:0] l_desr_et_5;
wire [5:0] l_desr_et_4;
wire [5:0] l_desr_et_3;
wire [5:0] l_desr_et_2;
wire [5:0] l_desr_et_1;
wire [5:0] l_desr_et_0;
wire s_dsfar_lat_scanin;
wire s_dsfar_lat_scanout;
wire [1:0] fesr_priv;
wire [2:0] s_dsfar;
wire s_tid_lat_scanin;
wire s_tid_lat_scanout;
wire [2:0] s_tid;
wire stb_flush_lat_scanin;
wire stb_flush_lat_scanout;
wire stb_flush;
wire [7:0] update_priv;
wire [7:0] s_dsfsr_dec_tid_raw;
wire sbdlc_lat_scanin;
wire sbdlc_lat_scanout;
wire sbdlc;
wire sbdlu_lat_scanin;
wire sbdlu_lat_scanout;
wire sbdlu;
wire [7:0] s_dsfsr_dec_tid;
wire [2:0] s_dsfsr;
wire [2:0] s_dsfsr_7;
wire [2:0] s_dsfsr_6;
wire [2:0] s_dsfsr_5;
wire [2:0] s_dsfsr_4;
wire [2:0] s_dsfsr_3;
wire [2:0] s_dsfsr_2;
wire [2:0] s_dsfsr_1;
wire [2:0] s_dsfsr_0;
wire [2:0] s_dsfar_7;
wire [2:0] s_dsfar_6;
wire [2:0] s_dsfar_5;
wire [2:0] s_dsfar_4;
wire [2:0] s_dsfar_3;
wire [2:0] s_dsfar_2;
wire [2:0] s_dsfar_1;
wire [2:0] s_dsfar_0;
wire [2:0] isfsr_7_new_in;
wire [2:0] isfsr_6_new_in;
wire [2:0] isfsr_5_new_in;
wire [2:0] isfsr_4_new_in;
wire [2:0] isfsr_3_new_in;
wire [2:0] isfsr_2_new_in;
wire [2:0] isfsr_1_new_in;
wire [2:0] isfsr_0_new_in;
wire [2:0] isfsr_7_in;
wire [2:0] isfsr_7;
wire [2:0] isfsr_6_in;
wire [2:0] isfsr_6;
wire [2:0] isfsr_5_in;
wire [2:0] isfsr_5;
wire [2:0] isfsr_4_in;
wire [2:0] isfsr_4;
wire [2:0] isfsr_3_in;
wire [2:0] isfsr_3;
wire [2:0] isfsr_2_in;
wire [2:0] isfsr_2;
wire [2:0] isfsr_1_in;
wire [2:0] isfsr_1;
wire [2:0] isfsr_0_in;
wire [2:0] isfsr_0;
wire [7:0] precise_i_error;
wire isfsr_7_lat_wmr_scanin;
wire isfsr_7_lat_wmr_scanout;
wire isfsr_6_lat_wmr_scanin;
wire isfsr_6_lat_wmr_scanout;
wire isfsr_5_lat_wmr_scanin;
wire isfsr_5_lat_wmr_scanout;
wire isfsr_4_lat_wmr_scanin;
wire isfsr_4_lat_wmr_scanout;
wire isfsr_3_lat_wmr_scanin;
wire isfsr_3_lat_wmr_scanout;
wire isfsr_2_lat_wmr_scanin;
wire isfsr_2_lat_wmr_scanout;
wire isfsr_1_lat_wmr_scanin;
wire isfsr_1_lat_wmr_scanout;
wire isfsr_0_lat_wmr_scanin;
wire isfsr_0_lat_wmr_scanout;
wire [3:0] dsfsr_7_new_in;
wire [3:0] dsfsr_6_new_in;
wire [3:0] dsfsr_5_new_in;
wire [3:0] dsfsr_4_new_in;
wire [3:0] dsfsr_3_new_in;
wire [3:0] dsfsr_2_new_in;
wire [3:0] dsfsr_1_new_in;
wire [3:0] dsfsr_0_new_in;
wire [3:0] dsfsr_7_in;
wire [3:0] dsfsr_7;
wire [3:0] dsfsr_6_in;
wire [3:0] dsfsr_6;
wire [3:0] dsfsr_5_in;
wire [3:0] dsfsr_5;
wire [3:0] dsfsr_4_in;
wire [3:0] dsfsr_4;
wire [3:0] dsfsr_3_in;
wire [3:0] dsfsr_3;
wire [3:0] dsfsr_2_in;
wire [3:0] dsfsr_2;
wire [3:0] dsfsr_1_in;
wire [3:0] dsfsr_1;
wire [3:0] dsfsr_0_in;
wire [3:0] dsfsr_0;
wire [7:0] precise_d_error;
wire dsfsr_7_lat_wmr_scanin;
wire dsfsr_7_lat_wmr_scanout;
wire dsfsr_6_lat_wmr_scanin;
wire dsfsr_6_lat_wmr_scanout;
wire dsfsr_5_lat_wmr_scanin;
wire dsfsr_5_lat_wmr_scanout;
wire dsfsr_4_lat_wmr_scanin;
wire dsfsr_4_lat_wmr_scanout;
wire dsfsr_3_lat_wmr_scanin;
wire dsfsr_3_lat_wmr_scanout;
wire dsfsr_2_lat_wmr_scanin;
wire dsfsr_2_lat_wmr_scanout;
wire dsfsr_1_lat_wmr_scanin;
wire dsfsr_1_lat_wmr_scanout;
wire dsfsr_0_lat_wmr_scanin;
wire dsfsr_0_lat_wmr_scanout;
wire asi_rd_ctl_lat_scanin;
wire asi_rd_ctl_lat_scanout;
wire rd_isfsr;
wire rd_dsfsr;
wire rd_dsfar;
wire rd_desr;
wire rd_fesr;
wire [2:0] rd_tid;
wire [7:0] rd_tid_dec;
wire [7:0] rd_isfsr_dec;
wire [7:0] rd_dsfsr_dec;
wire [7:0] rd_desr_dec;
wire dcvp_lat_scanin;
wire dcvp_lat_scanout;
wire dcvp;
wire dctp_lat_scanin;
wire dctp_lat_scanout;
wire dctp;
wire dctm_lat_scanin;
wire dctm_lat_scanout;
wire dctm;
wire dcdp_lat_scanin;
wire dcdp_lat_scanout;
wire dcdp;
wire [7:0] d_dec_tid;
wire [3:0] d_desr_et;
wire [3:0] d_desr_et_7;
wire [3:0] d_desr_et_6;
wire [3:0] d_desr_et_5;
wire [3:0] d_desr_et_4;
wire [3:0] d_desr_et_3;
wire [3:0] d_desr_et_2;
wire [3:0] d_desr_et_1;
wire [3:0] d_desr_et_0;
wire [8:0] d_desr_ea_7;
wire [8:0] d_desr_ea_6;
wire [8:0] d_desr_ea_5;
wire [8:0] d_desr_ea_4;
wire [8:0] d_desr_ea_3;
wire [8:0] d_desr_ea_2;
wire [8:0] d_desr_ea_1;
wire [8:0] d_desr_ea_0;
wire cxi_lat_scanin;
wire cxi_lat_scanout;
wire l2_err;
wire soc_err;
wire [1:0] c_l2_soc_err_type;
wire [2:0] c_l2_soc_tid;
wire c_l2_soc_sre;
wire [7:0] c_l2_soc_dec_tid;
wire [7:0] c_l2_err;
wire [7:0] c_soc_err;
wire [7:0] l2_dec_tid;
wire l2ch;
wire l2cs;
wire soc;
wire l2u;
wire sou;
wire l2nd;
wire [5:0] l2_desr_et;
wire [5:0] l2_desr_et_7;
wire [5:0] l2_desr_et_6;
wire [5:0] l2_desr_et_5;
wire [5:0] l2_desr_et_4;
wire [5:0] l2_desr_et_3;
wire [5:0] l2_desr_et_2;
wire [5:0] l2_desr_et_1;
wire [5:0] l2_desr_et_0;
wire sbdpc_lat_scanin;
wire sbdpc_lat_scanout;
wire sbdpc;
wire sbdpu_lat_scanin;
wire sbdpu_lat_scanout;
wire sbdpu;
wire [7:0] sb_dec_tid;
wire [5:0] s_desr_et;
wire [5:0] s_desr_et_7;
wire [5:0] s_desr_et_6;
wire [5:0] s_desr_et_5;
wire [5:0] s_desr_et_4;
wire [5:0] s_desr_et_3;
wire [5:0] s_desr_et_2;
wire [5:0] s_desr_et_1;
wire [5:0] s_desr_et_0;
wire [2:0] s_desr_ea_7;
wire [2:0] s_desr_ea_6;
wire [2:0] s_desr_ea_5;
wire [2:0] s_desr_ea_4;
wire [2:0] s_desr_ea_3;
wire [2:0] s_desr_ea_2;
wire [2:0] s_desr_ea_1;
wire [2:0] s_desr_ea_0;
wire mamu_err_lat_scanin;
wire mamu_err_lat_scanout;
wire mamu_err_v;
wire [10:0] mamu_err;
wire [7:0] mamu_dec_tid;
wire [7:0] ma_dec_tid;
wire [5:0] mamu_desr_et;
wire [5:0] mamu_desr_et_7;
wire [5:0] mamu_desr_et_6;
wire [5:0] mamu_desr_et_5;
wire [5:0] mamu_desr_et_4;
wire [5:0] mamu_desr_et_3;
wire [5:0] mamu_desr_et_2;
wire [5:0] mamu_desr_et_1;
wire [5:0] mamu_desr_et_0;
wire [10:0] mamu_desr_ea_7;
wire [10:0] mamu_desr_ea_6;
wire [10:0] mamu_desr_ea_5;
wire [10:0] mamu_desr_ea_4;
wire [10:0] mamu_desr_ea_3;
wire [10:0] mamu_desr_ea_2;
wire [10:0] mamu_desr_ea_1;
wire [10:0] mamu_desr_ea_0;
wire ma_tid_lat_scanin;
wire ma_tid_lat_scanout;
wire [2:0] ma_tid;
wire cwq_tid_lat_scanin;
wire cwq_tid_lat_scanout;
wire [2:0] cwq_tid;
wire spu_error_lat_scanin;
wire spu_error_lat_scanout;
wire [5:0] spu_error;
wire [7:0] cwq_dec_tid;
wire mal2c;
wire mal2u;
wire mal2nd;
wire cwql2c;
wire cwql2u;
wire cwql2nd;
wire [5:0] ma_desr_et;
wire [5:0] cwq_desr_et;
wire [5:0] ma_desr_et_7;
wire [5:0] ma_desr_et_6;
wire [5:0] ma_desr_et_5;
wire [5:0] ma_desr_et_4;
wire [5:0] ma_desr_et_3;
wire [5:0] ma_desr_et_2;
wire [5:0] ma_desr_et_1;
wire [5:0] ma_desr_et_0;
wire [5:0] cwq_desr_et_7;
wire [5:0] cwq_desr_et_6;
wire [5:0] cwq_desr_et_5;
wire [5:0] cwq_desr_et_4;
wire [5:0] cwq_desr_et_3;
wire [5:0] cwq_desr_et_2;
wire [5:0] cwq_desr_et_1;
wire [5:0] cwq_desr_et_0;
wire [5:0] t_desr_et_7;
wire [5:0] t_desr_et_6;
wire [5:0] t_desr_et_5;
wire [5:0] t_desr_et_4;
wire [5:0] t_desr_et_3;
wire [5:0] t_desr_et_2;
wire [5:0] t_desr_et_1;
wire [5:0] t_desr_et_0;
wire [9:0] t_desr_ea_7;
wire [9:0] t_desr_ea_6;
wire [9:0] t_desr_ea_5;
wire [9:0] t_desr_ea_4;
wire [9:0] t_desr_ea_3;
wire [9:0] t_desr_ea_2;
wire [9:0] t_desr_ea_1;
wire [9:0] t_desr_ea_0;
wire pipe_desr_exc_7;
wire pipe_desr_exc_6;
wire pipe_desr_exc_5;
wire pipe_desr_exc_4;
wire pipe_desr_exc_3;
wire pipe_desr_exc_2;
wire pipe_desr_exc_1;
wire pipe_desr_exc_0;
wire m_desr_exc_7;
wire m_desr_exc_6;
wire m_desr_exc_5;
wire m_desr_exc_4;
wire m_desr_exc_3;
wire m_desr_exc_2;
wire m_desr_exc_1;
wire m_desr_exc_0;
wire l_desr_exc_7;
wire l_desr_exc_6;
wire l_desr_exc_5;
wire l_desr_exc_4;
wire l_desr_exc_3;
wire l_desr_exc_2;
wire l_desr_exc_1;
wire l_desr_exc_0;
wire d_desr_exc_7;
wire d_desr_exc_6;
wire d_desr_exc_5;
wire d_desr_exc_4;
wire d_desr_exc_3;
wire d_desr_exc_2;
wire d_desr_exc_1;
wire d_desr_exc_0;
wire l2_desr_exc_7;
wire l2_desr_exc_6;
wire l2_desr_exc_5;
wire l2_desr_exc_4;
wire l2_desr_exc_3;
wire l2_desr_exc_2;
wire l2_desr_exc_1;
wire l2_desr_exc_0;
wire s_desr_exc_7;
wire s_desr_exc_6;
wire s_desr_exc_5;
wire s_desr_exc_4;
wire s_desr_exc_3;
wire s_desr_exc_2;
wire s_desr_exc_1;
wire s_desr_exc_0;
wire mamu_desr_exc_7;
wire mamu_desr_exc_6;
wire mamu_desr_exc_5;
wire mamu_desr_exc_4;
wire mamu_desr_exc_3;
wire mamu_desr_exc_2;
wire mamu_desr_exc_1;
wire mamu_desr_exc_0;
wire ma_desr_exc_7;
wire ma_desr_exc_6;
wire ma_desr_exc_5;
wire ma_desr_exc_4;
wire ma_desr_exc_3;
wire ma_desr_exc_2;
wire ma_desr_exc_1;
wire ma_desr_exc_0;
wire cwq_desr_exc_7;
wire cwq_desr_exc_6;
wire cwq_desr_exc_5;
wire cwq_desr_exc_4;
wire cwq_desr_exc_3;
wire cwq_desr_exc_2;
wire cwq_desr_exc_1;
wire cwq_desr_exc_0;
wire t_desr_exc_7;
wire t_desr_exc_6;
wire t_desr_exc_5;
wire t_desr_exc_4;
wire t_desr_exc_3;
wire t_desr_exc_2;
wire t_desr_exc_1;
wire t_desr_exc_0;
wire take_s_7;
wire no_desr_s_7;
wire take_s_6;
wire no_desr_s_6;
wire take_s_5;
wire no_desr_s_5;
wire take_s_4;
wire no_desr_s_4;
wire take_s_3;
wire no_desr_s_3;
wire take_s_2;
wire no_desr_s_2;
wire take_s_1;
wire no_desr_s_1;
wire take_s_0;
wire no_desr_s_0;
wire take_t_7;
wire take_t_6;
wire take_t_5;
wire take_t_4;
wire take_t_3;
wire take_t_2;
wire take_t_1;
wire take_t_0;
wire take_ma_7;
wire take_ma_6;
wire take_ma_5;
wire take_ma_4;
wire take_ma_3;
wire take_ma_2;
wire take_ma_1;
wire take_ma_0;
wire take_mamu_7;
wire take_mamu_6;
wire take_mamu_5;
wire take_mamu_4;
wire take_mamu_3;
wire take_mamu_2;
wire take_mamu_1;
wire take_mamu_0;
wire take_cwq_7;
wire take_cwq_6;
wire take_cwq_5;
wire take_cwq_4;
wire take_cwq_3;
wire take_cwq_2;
wire take_cwq_1;
wire take_cwq_0;
wire take_l2_7;
wire take_l2_6;
wire take_l2_5;
wire take_l2_4;
wire take_l2_3;
wire take_l2_2;
wire take_l2_1;
wire take_l2_0;
wire take_pipe_7;
wire take_pipe_6;
wire take_pipe_5;
wire take_pipe_4;
wire take_pipe_3;
wire take_pipe_2;
wire take_pipe_1;
wire take_pipe_0;
wire take_m_7;
wire take_m_6;
wire take_m_5;
wire take_m_4;
wire take_m_3;
wire take_m_2;
wire take_m_1;
wire take_m_0;
wire take_l_7;
wire take_l_6;
wire take_l_5;
wire take_l_4;
wire take_l_3;
wire take_l_2;
wire take_l_1;
wire take_l_0;
wire take_d_7;
wire take_d_6;
wire take_d_5;
wire take_d_4;
wire take_d_3;
wire take_d_2;
wire take_d_1;
wire take_d_0;
wire [7:0] write_desr;
wire [7:0] write_desr_s;
wire sbdiou_lat_scanin;
wire sbdiou_lat_scanout;
wire sbdiou;
wire sbapp_lat_scanin;
wire sbapp_lat_scanout;
wire sbapp;
wire [7:0] f_dec_tid;
wire [7:0] write_fesr;
wire [7:0] error_event_1_in;
wire [7:0] error_event_0_in;
wire event_1_lat_scanin;
wire event_1_lat_scanout;
wire [7:0] error_event_1;
wire event_0_lat_scanin;
wire event_0_lat_scanout;
wire [7:0] error_event_0;
wire spares_scanin;
wire spares_scanout;
wire spare0_lat_scanin;
wire spare0_lat_scanout;
wire spare0_unused;
wire spare1_lat_scanin;
wire spare1_lat_scanout;
wire spare1_unused;
wire spare2_lat_scanin;
wire spare2_lat_scanout;
wire spare2_unused;
wire spare3_lat_scanin;
wire spare3_lat_scanout;
wire spare3_unused;
wire spare4_lat_scanin;
wire spare4_lat_scanout;
wire spare4_unused;
wire spare5_lat_scanin;
wire spare5_lat_scanout;
wire spare5_unused;
wire spare6_lat_scanin;
wire spare6_lat_scanout;
wire spare6_unused;
wire spare7_lat_scanin;
wire spare7_lat_scanout;
wire spare7_unused;
wire spare8_lat_scanin;
wire spare8_lat_scanout;
wire spare8_unused;
wire spare9_lat_scanin;
wire spare9_lat_scanout;
wire spare9_unused;
wire spare10_lat_scanin;
wire spare10_lat_scanout;
wire spare10_unused;
wire spare11_lat_scanin;
wire spare11_lat_scanout;
wire spare11_unused;
wire spare12_lat_scanin;
wire spare12_lat_scanout;
wire spare12_unused;
wire spare13_lat_scanin;
wire spare13_lat_scanout;
wire spare13_unused;
wire spare14_lat_scanin;
wire spare14_lat_scanout;
wire spare14_unused;
wire spare15_lat_scanin;
wire spare15_lat_scanout;
wire spare15_unused;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

input		lsu_tlu_pmen;		// Power management

input	[2:0]	ftu_excp_way_d;
input	[2:0]	ftu_excp_tid_d;
input		ftu_excp_way_valid_d;

input	[4:0]	dec_exc0_m;
input	[4:0]	dec_exc1_m;
input	[1:0]	dec_icache_perr_m;
input	[1:0]	dec_tid0_m;
input	[1:0]	dec_tid1_m;
input	[1:0] dec_inst_valid_m;
input	[1:0] dec_fgu_inst_m;
input	[1:0] dec_lsu_inst_m;
input 	[1:0]	dec_flush_b;

input	[1:0]	fls_irf_cecc_b;
input	[1:0]	fls_irf_uecc_b;
input	[1:0]	fls_kill_irf_ecc_w;
input	[4:0]	exu0_ecc_addr_m;
input	[4:0]	exu1_ecc_addr_m;
input	[7:0]	exu0_ecc_check_m;
input	[7:0]	exu1_ecc_check_m;

input		fls_f_cecc_w;
input		fls_f_uecc_w;
input	[5:0]	fgu_ecc_addr_fx2;
input	[13:0]	fgu_ecc_check_fx2;
input		fgu_pdist_beat2_fx1;

input		lsu_tlu_twocycle_m;	// LSU takes extra cycle on this inst
input	[7:0]	lsu_block_store_b;	// LSU reads FRF for block store

input	[7:0]	fls_load_dsfar;         // Trap that loads DSFAR
input	[1:0]	fls_ipe_dme_request;	// Update DSFSR/DSFAR for IRF/FRF ECC
input		lsu_dttp_err_b;         // DTLB tag parity error
input		lsu_dtdp_err_b;         // DTLB data parity error
input		lsu_dtmh_err_b;         // DTLB data parity error 

input		lsu_dcmh_err_g;		// LSU data cache multiple hit
input		lsu_dcvp_err_g;		// LSU data cache valid parity error
input		lsu_dctp_err_g;		// LSU data cache tag parity error
input		lsu_dcdp_err_g;		// LSU data cache parity error
input		lsu_dcl2c_err_g;	// LSU data cache L2 correctable ECC
input		lsu_dcl2u_err_g;	// LSU data cache L2 uncorrectable ECC
input		lsu_dcl2nd_err_g;	// LSU data cache L2 NotData
input		lsu_dcsoc_err_g;	// LSU data cache SOC error
input	[2:0]	lsu_dcerr_tid_g;	// TID for G stage errors (above)
input	[8:0]	lsu_dcerr_sfar_g;	// Contains way and index of the error

input		lsu_sbdlc_err_g;        // STB RAW error (CE)
input		lsu_sbdlu_err_g;        // STB RAW error (UE)
input		lsu_sbdpc_err_g;        // STB read for issue data (CE)
input		lsu_sbdpu_err_g;        // STB read for issue data (UE)
input		lsu_sbapp_err_g;        // STB read for issue addr parity error
input		lsu_sbdiou_err_g;       // STB read for issue IO/ext ASI parity
input	[2:0]	lsu_stberr_tid_g;       // TID of STB error
input	[2:0]	lsu_stberr_index_g;	// Index of STB error
input	[1:0]	lsu_stberr_priv_g;	// Privilege of STB error
input		lsu_stb_flush_g;	// STB entry flushed STB (capture priv)

input		cel_tccp;		
input		cel_tcup;
input	[7:0] cel_syndrome;
input	[2:0]	tlu_tca_tid;		
input	[1:0]	tlu_tca_index;		// Index for precise TCA errors
input	[7:0]	tlu_tsac;		// Only one per TG can report tsa[cu]
input	[7:0]	tlu_tsau;
input		asi_tsac;		// ASI TSA access errors
input		asi_tsau;		
input	[2:0]	asi_tsacu_tid;		// Only one per TG can report tsa[cu]
input	[7:0]	tlu_tccd;
input	[7:0]	tlu_tcud;
input	[1:0]	tlu_tca_index_0;
input	[1:0]	tlu_tca_index_1;
input	[10:5] tsd_pc_0_w;
input	[10:5] tsd_pc_1_w;
input	[7:0]	fls_flush;
input	[1:0]	fls_disrupting_flush_w;
input	[1:0]	trl_gl0;
input	[1:0]	trl_gl1;
input	[1:0]	trl_gl2;
input	[1:0]	trl_gl3;
input	[1:0]	trl_gl4;
input	[1:0]	trl_gl5;
input	[1:0]	trl_gl6;
input	[1:0]	trl_gl7;

input 		mmu_asi_cecc; 		// Correctable ECC error on ASI read
input 		mmu_asi_uecc; 		// Uncorrectable ECC error on ASI read
input	[10:0]	mmu_asi_index;		// Syndrome and index of the failure
input		mmu_asi_mra_not_sca;	// 1: MRA error 0: Scratchpad error
input	[7:0]	mmu_i_l2cerr;
input	[7:0]	mmu_d_l2cerr;
input	[7:0]	mmu_i_eccerr;
input	[7:0]	mmu_d_eccerr;
input	[2:0]	mmu_thr0_err_type;
input	[2:0]	mmu_thr1_err_type;
input	[2:0]	mmu_thr2_err_type;
input	[2:0]	mmu_thr3_err_type;
input	[2:0]	mmu_thr4_err_type;
input	[2:0]	mmu_thr5_err_type;
input	[2:0]	mmu_thr6_err_type;
input	[2:0]	mmu_thr7_err_type;
input	[2:0]	mmu_thr0_err_index;
input	[2:0]	mmu_thr1_err_index;
input	[2:0]	mmu_thr2_err_index;
input	[2:0]	mmu_thr3_err_index;
input	[2:0]	mmu_thr4_err_index;
input	[2:0]	mmu_thr5_err_index;
input	[2:0]	mmu_thr6_err_index;
input	[2:0]	mmu_thr7_err_index;

input		spu_tlu_mamu_err_req_v;	// SPU MAMEM parity error
input	[10:0]	spu_tlu_mamu_err_req;	// SPU MAMEM index
input	[2:0]	spu_tlu_ma_int_req;	// SPU MA  2:0 thread ID
input	[2:0]	spu_tlu_cwq_int_req;	// SPU CWQ 2:0 thread ID
input	[5:0]	spu_tlu_l2_error;	// MAL2[C,U,ND],CWQL2[C,U,ND]

input		cxi_l2_soc_sre;		// software_recoverable_error
input	[1:0]	cxi_l2_soc_err_type;	// C=01, UC=10, ND=11
input	[2:0]	cxi_l2_soc_tid;
input		cxi_l2_err;		// L2 error reported
input		cxi_soc_err;		// SOC error reported

input		asi_rd_isfsr;		// ASI read control in ASI cycle 1
input		asi_rd_dsfsr;		// but actual read is in ASI cycle 2
input		asi_rd_dsfar;
input		asi_rd_desr;
input		asi_rd_fesr;
input	[2:0]	asi_rd_tid;
input	[7:0]	asi_wr_isfsr;
input	[7:0]	asi_wr_dsfsr;
input	[3:0]	asi_wr_data;

input	[7:0]	dfd_desr_f;
input	[7:0]	dfd_desr_s;
input	[7:0]	dfd_fesr_f;
input	[1:0]	dfd_fesr_priv_0;
input	[1:0]	dfd_fesr_priv_1;
input	[1:0]	dfd_fesr_priv_2;
input	[1:0]	dfd_fesr_priv_3;
input	[1:0]	dfd_fesr_priv_4;
input	[1:0]	dfd_fesr_priv_5;
input	[1:0]	dfd_fesr_priv_6;
input	[1:0]	dfd_fesr_priv_7;


output		wmr_scan_out;

output		scan_out;

output	[3:0]	ras_asi_data;

// DSFAR
output	[19:0] ras_dsfar_0;
output	[19:0] ras_dsfar_1;
output	[19:0] ras_dsfar_2;
output	[19:0] ras_dsfar_3;
output	[19:0] ras_dsfar_4;
output	[19:0] ras_dsfar_5;
output	[19:0] ras_dsfar_6;
output	[19:0] ras_dsfar_7;
output	[7:0] ras_dsfar_sel_lsu_va;
output	[7:0] ras_dsfar_sel_ras;
output	[7:0] ras_dsfar_sel_tsa;
output	[7:0] ras_rd_dsfar;

// DESRs
output	[61:56]	ras_desr_et_0;
output	[61:56]	ras_desr_et_1;
output	[61:56]	ras_desr_et_2;
output	[61:56]	ras_desr_et_3;
output	[61:56]	ras_desr_et_4;
output	[61:56]	ras_desr_et_5;
output	[61:56]	ras_desr_et_6;
output	[61:56]	ras_desr_et_7;
output	[10:0]	ras_desr_ea_0;
output	[10:0]	ras_desr_ea_1;
output	[10:0]	ras_desr_ea_2;
output	[10:0]	ras_desr_ea_3;
output	[10:0]	ras_desr_ea_4;
output	[10:0]	ras_desr_ea_5;
output	[10:0]	ras_desr_ea_6;
output	[10:0]	ras_desr_ea_7;
output		ras_desr_me_0;
output		ras_desr_me_1;
output		ras_desr_me_2;
output		ras_desr_me_3;
output		ras_desr_me_4;
output		ras_desr_me_5;
output		ras_desr_me_6;
output		ras_desr_me_7;
output	[7:0]	ras_desr_en;
output	[7:0]	ras_write_desr_1st;
output	[7:0]	ras_write_desr_2nd;
output	[7:0]	ras_rd_desr;

// FESRs
output	[61:60]	ras_fesr_et_0;
output	[61:60]	ras_fesr_et_1;
output	[61:60]	ras_fesr_et_2;
output	[61:60]	ras_fesr_et_3;
output	[61:60]	ras_fesr_et_4;
output	[61:60]	ras_fesr_et_5;
output	[61:60]	ras_fesr_et_6;
output	[61:60]	ras_fesr_et_7;
output	[59:55]	ras_fesr_ea_0;
output	[59:55]	ras_fesr_ea_1;
output	[59:55]	ras_fesr_ea_2;
output	[59:55]	ras_fesr_ea_3;
output	[59:55]	ras_fesr_ea_4;
output	[59:55]	ras_fesr_ea_5;
output	[59:55]	ras_fesr_ea_6;
output	[59:55]	ras_fesr_ea_7;
output	[7:0]	ras_fesr_en;
output	[7:0]	ras_write_fesr;
output	[59:58]	ras_fesr_priv;
output	[7:0]	ras_update_priv;
output	[7:0]	ras_rd_fesr;

output	[7:0]	ras_precise_error;	// For debug events
output	[7:0]	ras_disrupting_error;	// For debug events
output	[7:0]	ras_deferred_error;	// For debug events


//////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;


//////////////////////////////////////////////////////////////////////////////
// Clock header

tlu_ras_ctl_l1clkhdr_ctl_macro free_clken (
        .l2clk  (l2clk 			),
        .l1en   (1'b1			),
        .l1clk  (l1clk			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


//////////////////////////////////////////////////////////////////////////////
// Power management

assign l1en_any_b2w =
       (| {inst_valid_b[1:0], 
           lsu_block_store_b[7:0], 
           w_en, w1_en, ~lsu_tlu_pmen});

tlu_ras_ctl_l1clkhdr_ctl_macro b2w_clken (
        .l2clk  (l2clk 			),
        .l1en   (l1en_any_b2w		),
        .l1clk  (l1clk_pm1		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

assign l1en_pm2 =
       excp_way_valid | ~lsu_tlu_pmen;

tlu_ras_ctl_l1clkhdr_ctl_macro exc_way_clken (
        .l2clk  (l2clk 			),
        .l1en   (l1en_pm2		),
        .l1clk  (l1clk_pm2		),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


//////////////////////////////////////////////////////////////////////////////
//
//  Pipe TIDs, etc. for in-pipe errors
//

assign twocycle_inst_m[1:0] =
       {2 {lsu_tlu_twocycle_m}} & dec_lsu_inst_m[1:0] & 
       dec_inst_valid_m[1:0];

tlu_ras_ctl_msff_ctl_macro__width_2 twocycle_inst_b_lat  (
	.scan_in(twocycle_inst_b_lat_scanin),
	.scan_out(twocycle_inst_b_lat_scanout),
	.din	(twocycle_inst_m	[1:0]	),
	.dout	(ptwocycle_inst_b	[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign twocycle_inst_b[1:0] =
       (ptwocycle_inst_b[1:0] | 
        ({2 {fgu_pdist_beat2_fx1}} & fgu_inst_b[1:0])) & 
       ~dec_flush_b[1:0] & 
       ~fls_irf_cecc_b[1:0] & ~fls_irf_uecc_b[1:0];

assign inst_valid_m[1:0] =
       dec_inst_valid_m[1:0] | twocycle_inst_b[1:0];

tlu_ras_ctl_msff_ctl_macro__width_2 inst_valid_b_lat  (
	.scan_in(inst_valid_b_lat_scanin),
	.scan_out(inst_valid_b_lat_scanout),
	.din	(inst_valid_m		[1:0]	),
	.dout	(inst_valid_b		[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign w_en_in =
       | {inst_valid_b[1:0], lsu_block_store_b[7:0]};

tlu_ras_ctl_msff_ctl_macro__width_1 w_en_lat  (
	.scan_in(w_en_lat_scanin),
	.scan_out(w_en_lat_scanout),
	.din	(w_en_in			),
	.dout	(w_en				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 w1_en_lat  (
	.scan_in(w1_en_lat_scanin),
	.scan_out(w1_en_lat_scanout),
	.din	(w_en				),
	.dout	(w1_en				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign flush_b[1:0] =
       {(fls_flush[7] & tid_dec_b[7]) |
        (fls_flush[6] & tid_dec_b[6]) |
        (fls_flush[5] & tid_dec_b[5]) |
        (fls_flush[4] & tid_dec_b[4]),
        (fls_flush[3] & tid_dec_b[3]) |
        (fls_flush[2] & tid_dec_b[2]) |
        (fls_flush[1] & tid_dec_b[1]) |
        (fls_flush[0] & tid_dec_b[0])};

assign inst_valid_w_in[1:0] =
       inst_valid_b[1:0] & ~dec_flush_b[1:0] & ~flush_b[1:0];

tlu_ras_ctl_msff_ctl_macro__width_2 inst_valid_w_lat  (
	.scan_in(inst_valid_w_lat_scanin),
	.scan_out(inst_valid_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(inst_valid_w_in	[1:0]	),
	.dout	(pre_inst_valid_w	[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// block_store_b is not actually in B, so it can't be flushed
assign block_store_w_in[7:0] =
       lsu_block_store_b[7:0];

tlu_ras_ctl_msff_ctl_macro__width_8 block_store_w_lat  (
	.scan_in(block_store_w_lat_scanin),
	.scan_out(block_store_w_lat_scanout),
	.din	(block_store_w_in	[7:0]	),
	.dout	(pblock_store_w		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign block_store_w[7:0] =
       pblock_store_w[7:0] & ~{8 {seen_bsee}};

assign inst_valid_w[1:0] =
       pre_inst_valid_w[1:0] & ~fls_disrupting_flush_w[1:0];

assign tid1_m[1:0] =
       (dec_tid1_m[1:0] & {2 {~twocycle_inst_b[1]}}) | 
       (    tid1_b[1:0] & {2 { twocycle_inst_b[1]}}) ; 

tlu_ras_ctl_msff_ctl_macro__width_2 tid1_b_lat  (
	.scan_in(tid1_b_lat_scanin),
	.scan_out(tid1_b_lat_scanout),
	.din	(tid1_m			[1:0]	),
	.dout	(tid1_b			[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid0_m[1:0] =
       (dec_tid0_m[1:0] & {2 {~twocycle_inst_b[0]}}) | 
       (    tid0_b[1:0] & {2 { twocycle_inst_b[0]}}) ; 

tlu_ras_ctl_msff_ctl_macro__width_2 tid0_b_lat  (
	.scan_in(tid0_b_lat_scanin),
	.scan_out(tid0_b_lat_scanout),
	.din	(tid0_m			[1:0]	),
	.dout	(tid0_b			[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid_dec_b[7:0] = 
       { tid1_b[1] &  tid1_b[0],
         tid1_b[1] & ~tid1_b[0],
        ~tid1_b[1] &  tid1_b[0],
        ~tid1_b[1] & ~tid1_b[0],
         tid0_b[1] &  tid0_b[0],
         tid0_b[1] & ~tid0_b[0],
        ~tid0_b[1] &  tid0_b[0],
        ~tid0_b[1] & ~tid0_b[0]};

tlu_ras_ctl_msff_ctl_macro__width_2 tid1_w_lat  (
	.scan_in(tid1_w_lat_scanin),
	.scan_out(tid1_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tid1_b			[1:0]	),
	.dout	(tid1_w			[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_2 tid0_w_lat  (
	.scan_in(tid0_w_lat_scanin),
	.scan_out(tid0_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tid0_b			[1:0]	),
	.dout	(tid0_w			[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid_dec_w[7:0] =
       { tid1_w[1] &  tid1_w[0],
         tid1_w[1] & ~tid1_w[0],
        ~tid1_w[1] &  tid1_w[0],
        ~tid1_w[1] & ~tid1_w[0],
         tid0_w[1] &  tid0_w[0],
         tid0_w[1] & ~tid0_w[0],
        ~tid0_w[1] &  tid0_w[0],
        ~tid0_w[1] & ~tid0_w[0]} & 
       {{4 {inst_valid_w[1]}}, {4 {inst_valid_w[0]}}} | 
       block_store_w[7:0];

assign fgu_inst_m[1:0] =
       (dec_fgu_inst_m[1:0] & dec_inst_valid_m[1:0]) |
       (    fgu_inst_b[1:0] &  twocycle_inst_b[1:0]) ;

tlu_ras_ctl_msff_ctl_macro__width_2 fgu_inst_b_lat  (
	.scan_in(fgu_inst_b_lat_scanin),
	.scan_out(fgu_inst_b_lat_scanout),
	.din	(fgu_inst_m		[1:0]	),
	.dout	(fgu_inst_b		[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_2 fgu_inst_w_lat  (
	.scan_in(fgu_inst_w_lat_scanin),
	.scan_out(fgu_inst_w_lat_scanout),
	.din	(fgu_inst_b		[1:0]	),
	.dout	(pfgu_inst_w		[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign fgu_inst_w[1:0] =
       pfgu_inst_w[1:0] | {| block_store_w[7:4], | block_store_w[3:0]};

// lsu_inst_m doesn't need twocycle stuff because TLB is only accessed once
assign lsu_inst_m[1:0] =
        dec_lsu_inst_m[1:0] & dec_inst_valid_m[1:0]  ;

tlu_ras_ctl_msff_ctl_macro__width_2 lsu_inst_b_lat  (
	.scan_in(lsu_inst_b_lat_scanin),
	.scan_out(lsu_inst_b_lat_scanout),
	.din	(lsu_inst_m		[1:0]	),
	.dout	(lsu_inst_b		[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


//////////////////////////////////////////////////////////////////////////////
//
//  In-pipe precise errors from M to B
//

// Instruction cache and TLB errors
// The precise errors for ISFSR are encoded in the exc bits as
// ittp   5'b00111
// ittm   5'b01001
// itdp   5'b11111
// icl2u  5'b01111
// icl2nd 5'b10000
//
// but architecturally should be
// ittm		001	1
// ittp		010	2
// itdp		011	3
// icl2u	001	1
// icl2nd	010	2
//
// DESR errors from this source are 
// icl2c  5'b01110
// icvp   5'b01010
// ictp   5'b01011
// ictm   5'b01100
// icdp   5'b01101
//
// but architecturally should be
// icvp		00001	1
// ictp		00010	2
// ictm		00011	3
// icdp		00100	4
// All these have S = 0
// icl2c	00010	0
// This has S = 1

assign ittp_m[1:0] = 
       {dec_exc1_m[4:0] == 5'b00111,
 	dec_exc0_m[4:0] == 5'b00111} & 
       dec_inst_valid_m[1:0];
assign ittm_m[1:0] = 
       {dec_exc1_m[4:0] == 5'b01001,
	dec_exc0_m[4:0] == 5'b01001} & 
       dec_inst_valid_m[1:0];
assign itdp_m[1:0] =
       {dec_exc1_m[4:0] == 5'b11111,
	dec_exc0_m[4:0] == 5'b11111} & 
       dec_inst_valid_m[1:0];
assign icl2u_m[1:0] =
       {dec_exc1_m[4:0] == 5'b01111 | dec_exc1_m[4:0] == 5'b10111,
	dec_exc0_m[4:0] == 5'b01111 | dec_exc0_m[4:0] == 5'b10111} & 
       dec_inst_valid_m[1:0];
assign icl2nd_m[1:0] =
       {dec_exc1_m[4:0] == 5'b10000 | dec_exc1_m[4:0] == 5'b11000,
	dec_exc0_m[4:0] == 5'b10000 | dec_exc0_m[4:0] == 5'b11000} & 
       dec_inst_valid_m[1:0];

assign i_isfsr1_m[2:0] =
       ({3 {  ittm_m[1]}} & 3'b001) |
       ({3 {  ittp_m[1]}} & 3'b010) |
       ({3 {  itdp_m[1]}} & 3'b011) |
       ({3 { icl2u_m[1]}} & 3'b001) |
       ({3 {icl2nd_m[1]}} & 3'b010) ;

assign i_isfsr0_m[2:0] =
       ({3 {  ittm_m[0]}} & 3'b001) |
       ({3 {  ittp_m[0]}} & 3'b010) |
       ({3 {  itdp_m[0]}} & 3'b011) |
       ({3 { icl2u_m[0]}} & 3'b001) |
       ({3 {icl2nd_m[0]}} & 3'b010) ;

tlu_ras_ctl_msff_ctl_macro__width_3 i_isfsr1_b_lat  (
	.scan_in(i_isfsr1_b_lat_scanin),
	.scan_out(i_isfsr1_b_lat_scanout),
	.din	(i_isfsr1_m		[2:0]	),
	.dout	(i_isfsr1_b		[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 i_isfsr0_b_lat  (
	.scan_in(i_isfsr0_b_lat_scanin),
	.scan_out(i_isfsr0_b_lat_scanout),
	.din	(i_isfsr0_m		[2:0]	),
	.dout	(i_isfsr0_b		[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign icvp_m[1:0] = 
       {dec_exc1_m[4:0] == 5'b01010,
	dec_exc0_m[4:0] == 5'b01010} & 
       dec_inst_valid_m[1:0];
assign ictp_m[1:0] = 
       {dec_exc1_m[4:0] == 5'b01011,
	dec_exc0_m[4:0] == 5'b01011} & 
       dec_inst_valid_m[1:0];
assign ictm_m[1:0] = 
       {dec_exc1_m[4:0] == 5'b01100,
	dec_exc0_m[4:0] == 5'b01100} & 
       dec_inst_valid_m[1:0];
assign icl2c_m[1:0] =
       {dec_exc1_m[4:0] == 5'b01110 | dec_exc1_m[4:0] == 5'b11110,
	dec_exc0_m[4:0] == 5'b01110 | dec_exc0_m[4:0] == 5'b11110} & 
       dec_inst_valid_m[1:0];
assign icdp_m[1:0] = 
       dec_icache_perr_m[1:0] & ~icvp_m[1:0] & ~ictp_m[1:0] & 
       ~ictm_m[1:0] & ~ittp_m[1:0] & ~ittm_m[1:0] & ~itdp_m[1:0] &
       ~icl2c_m[1:0] &
       ~{(                  ~dec_exc1_m[2] &  dec_exc1_m[1]                  ) | 
	 (                  ~dec_exc1_m[2] &                    dec_exc1_m[0]) | 
	 (~dec_exc1_m[4] &  dec_exc1_m[2] & ~dec_exc1_m[1] & ~dec_exc1_m[0])  ,
	 (                  ~dec_exc0_m[2] &  dec_exc0_m[1]                  ) | 
	 (                  ~dec_exc0_m[2] &                    dec_exc0_m[0]) | 
	 (~dec_exc0_m[4] &  dec_exc0_m[2] & ~dec_exc0_m[1] & ~dec_exc0_m[0])  } & 
       dec_inst_valid_m[1:0];

assign i_desr1_m[3:0] = 
       ({4 {  icvp_m[1]}} & 4'b0001) |
       ({4 {  ictp_m[1]}} & 4'b0010) |
       ({4 {  ictm_m[1]}} & 4'b0011) |
       ({4 {  icdp_m[1]}} & 4'b0100) |
       ({4 { icl2c_m[1]}} & 4'b1010) ;

assign i_desr0_m[3:0] = 
       ({4 {  icvp_m[0]}} & 4'b0001) |
       ({4 {  ictp_m[0]}} & 4'b0010) |
       ({4 {  ictm_m[0]}} & 4'b0011) |
       ({4 {  icdp_m[0]}} & 4'b0100) |
       ({4 { icl2c_m[0]}} & 4'b1010) ;

tlu_ras_ctl_msff_ctl_macro__width_4 i_desr1_b_lat  (
	.scan_in(i_desr1_b_lat_scanin),
	.scan_out(i_desr1_b_lat_scanout),
	.din	(i_desr1_m		[3:0]	),
	.dout	(i_desr1_b		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 i_desr0_b_lat  (
	.scan_in(i_desr0_b_lat_scanin),
	.scan_out(i_desr0_b_lat_scanout),
	.din	(i_desr0_m		[3:0]	),
	.dout	(i_desr0_b		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// IRF ECC errors
tlu_ras_ctl_msff_ctl_macro__width_5 irf0_ecc_addr_b_lat  (
	.scan_in(irf0_ecc_addr_b_lat_scanin),
	.scan_out(irf0_ecc_addr_b_lat_scanout),
	.din	(exu0_ecc_addr_m	[4:0]	),
	.dout	(irf0_ecc_addr_b	[4:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_5 irf1_ecc_addr_b_lat  (
	.scan_in(irf1_ecc_addr_b_lat_scanin),
	.scan_out(irf1_ecc_addr_b_lat_scanout),
	.din	(exu1_ecc_addr_m	[4:0]	),
	.dout	(irf1_ecc_addr_b	[4:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_8 irf0_ecc_check_b_lat  (
	.scan_in(irf0_ecc_check_b_lat_scanin),
	.scan_out(irf0_ecc_check_b_lat_scanout),
	.din	(exu0_ecc_check_m	[7:0]	),
	.dout	(irf0_ecc_check_b	[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_8 irf1_ecc_check_b_lat  (
	.scan_in(irf1_ecc_check_b_lat_scanin),
	.scan_out(irf1_ecc_check_b_lat_scanout),
	.din	(exu1_ecc_check_m	[7:0]	),
	.dout	(irf1_ecc_check_b	[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


//////////////////////////////////////////////////////////////////////////////
//
//  Flop in-pipe errors from B to W
//

tlu_ras_ctl_msff_ctl_macro__width_3 i_isfsr1_w_lat  (
	.scan_in(i_isfsr1_w_lat_scanin),
	.scan_out(i_isfsr1_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(i_isfsr1_b		[2:0]	),
	.dout	(i_isfsr1_w		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 i_isfsr0_w_lat  (
	.scan_in(i_isfsr0_w_lat_scanin),
	.scan_out(i_isfsr0_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(i_isfsr0_b		[2:0]	),
	.dout	(i_isfsr0_w		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 i_desr1_w_lat  (
	.scan_in(i_desr1_w_lat_scanin),
	.scan_out(i_desr1_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(i_desr1_b		[3:0]	),
	.dout	(i_desr1_w		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 i_desr0_w_lat  (
	.scan_in(i_desr0_w_lat_scanin),
	.scan_out(i_desr0_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(i_desr0_b		[3:0]	),
	.dout	(i_desr0_w		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);


//
// Encodings for DSFSR errors
// irfu		0001	1
// irfc 	0010	2
// frfu		0011	3
// frfc		0100	4
// dtmh		0001	1
// dttp		0010	2
// dtdp		0011	3

assign irfu_b[1:0] =
       fls_irf_uecc_b[1:0] & inst_valid_b[1:0];
assign irfc_b[1:0] =
       fls_irf_cecc_b[1:0] & inst_valid_b[1:0];

assign dtmh_b[1:0] =
       ~irfu_b[1:0] & ~irfc_b[1:0] & 
       {2 {lsu_dtmh_err_b}} & 
       lsu_inst_b[1:0] & inst_valid_b[1:0];
assign dttp_b[1:0] =
       ~irfu_b[1:0] & ~irfc_b[1:0] & 
       {2 {~lsu_dtmh_err_b & lsu_dttp_err_b}} & lsu_inst_b[1:0] & 
       inst_valid_b[1:0];
assign dtdp_b[1:0] =
       ~irfu_b[1:0] & ~irfc_b[1:0] & 
       {2 {~lsu_dttp_err_b & ~lsu_dtmh_err_b & lsu_dtdp_err_b}} & 
       lsu_inst_b[1:0] & inst_valid_b[1:0];

tlu_ras_ctl_msff_ctl_macro__width_2 irfu_w_lat  (
	.scan_in(irfu_w_lat_scanin),
	.scan_out(irfu_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(irfu_b			[1:0]	),
	.dout	(pirfu_w		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign irfu_w[1:0] =
       pirfu_w[1:0] & ~fls_kill_irf_ecc_w[1:0];

tlu_ras_ctl_msff_ctl_macro__width_2 irfc_w_lat  (
	.scan_in(irfc_w_lat_scanin),
	.scan_out(irfc_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(irfc_b			[1:0]	),
	.dout	(pirfc_w		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign irfc_w[1:0] =
       pirfc_w[1:0] & ~fls_kill_irf_ecc_w[1:0];

assign pfrfu_w[1:0] = 
       {2 {fls_f_uecc_w}} & fgu_inst_w[1:0];

assign pfrfc_w[1:0] = 
       {2 {fls_f_cecc_w}} & fgu_inst_w[1:0];

assign frfu_w[1:0] =
       pfrfu_w[1:0] & 
       ((inst_valid_w[1:0] &
         ~irfu_w[1:0] & ~irfc_w[1:0]) |
	{| block_store_w[7:4], | block_store_w[3:0]});

assign frfc_w[1:0] =
       pfrfc_w[1:0] & 
       ((inst_valid_w[1:0] &
         ~irfu_w[1:0] & ~irfc_w[1:0]) |
	{| block_store_w[7:4], | block_store_w[3:0]});


// Only capture first FGU ECC error on block store
assign seen_bsee_in =
       (| ((pfrfu_w[1:0] | pfrfc_w[1:0]) & 
           {| block_store_w[7:4], | block_store_w[3:0]})) |
       (seen_bsee & (| pblock_store_w[7:0]));
       
tlu_ras_ctl_msff_ctl_macro__width_1 seen_bsee_lat  (
	.scan_in(seen_bsee_lat_scanin),
	.scan_out(seen_bsee_lat_scanout),
	.din	(seen_bsee_in			),
	.dout	(seen_bsee			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


tlu_ras_ctl_msff_ctl_macro__width_2 dttp_w_lat  (
	.scan_in(dttp_w_lat_scanin),
	.scan_out(dttp_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(dttp_b			[1:0]	),
	.dout	(pdttp_w		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign dttp_w[1:0] =
       pdttp_w[1:0] & ~pfrfc_w[1:0] & ~pfrfu_w[1:0];

tlu_ras_ctl_msff_ctl_macro__width_2 dtmh_w_lat  (
	.scan_in(dtmh_w_lat_scanin),
	.scan_out(dtmh_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(dtmh_b			[1:0]	),
	.dout	(pdtmh_w		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign dtmh_w[1:0] =
       pdtmh_w[1:0] & ~pfrfc_w[1:0] & ~pfrfu_w[1:0];

tlu_ras_ctl_msff_ctl_macro__width_2 dtdp_w_lat  (
	.scan_in(dtdp_w_lat_scanin),
	.scan_out(dtdp_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(dtdp_b			[1:0]	),
	.dout	(pdtdp_w		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign dtdp_w[1:0] =
       pdtdp_w[1:0] & ~pfrfc_w[1:0] & ~pfrfu_w[1:0];

tlu_ras_ctl_msff_ctl_macro__width_5 irf0_ecc_addr_w_lat  (
	.scan_in(irf0_ecc_addr_w_lat_scanin),
	.scan_out(irf0_ecc_addr_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(irf0_ecc_addr_b	[4:0]	),
	.dout	(irf0_ecc_addr_w	[4:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_5 irf1_ecc_addr_w_lat  (
	.scan_in(irf1_ecc_addr_w_lat_scanin),
	.scan_out(irf1_ecc_addr_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(irf1_ecc_addr_b	[4:0]	),
	.dout	(irf1_ecc_addr_w	[4:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_8 irf0_ecc_check_w_lat  (
	.scan_in(irf0_ecc_check_w_lat_scanin),
	.scan_out(irf0_ecc_check_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(irf0_ecc_check_b	[7:0]	),
	.dout	(irf0_ecc_check_w	[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_8 irf1_ecc_check_w_lat  (
	.scan_in(irf1_ecc_check_w_lat_scanin),
	.scan_out(irf1_ecc_check_w_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(irf1_ecc_check_b	[7:0]	),
	.dout	(irf1_ecc_check_w	[7:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_6 frf_ecc_addr_w_lat  (
	.scan_in(frf_ecc_addr_w_lat_scanin),
	.scan_out(frf_ecc_addr_w_lat_scanout),
	.din	(fgu_ecc_addr_fx2	[5:0]	),
	.dout	(frf_ecc_addr_w		[5:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_14 frf_ecc_check_w_lat  (
	.scan_in(frf_ecc_check_w_lat_scanin),
	.scan_out(frf_ecc_check_w_lat_scanout),
	.din	(fgu_ecc_check_fx2	[13:0]	),
	.dout	(frf_ecc_check_w	[13:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// Decode in-pipe errors at W

assign pipe_isfsr_7[2:0] =
       i_isfsr1_w[2:0] & {3 {tid_dec_w[7]}};
assign pipe_isfsr_6[2:0] =
       i_isfsr1_w[2:0] & {3 {tid_dec_w[6]}};
assign pipe_isfsr_5[2:0] =
       i_isfsr1_w[2:0] & {3 {tid_dec_w[5]}};
assign pipe_isfsr_4[2:0] =
       i_isfsr1_w[2:0] & {3 {tid_dec_w[4]}};
assign pipe_isfsr_3[2:0] =
       i_isfsr0_w[2:0] & {3 {tid_dec_w[3]}};
assign pipe_isfsr_2[2:0] =
       i_isfsr0_w[2:0] & {3 {tid_dec_w[2]}};
assign pipe_isfsr_1[2:0] =
       i_isfsr0_w[2:0] & {3 {tid_dec_w[1]}};
assign pipe_isfsr_0[2:0] =
       i_isfsr0_w[2:0] & {3 {tid_dec_w[0]}};

assign pipe_dsfsr1_w[2:0] = 
       (({3 {irfu_w[1]}} & 3'b001) |
        ({3 {irfc_w[1]}} & 3'b010) |
        ({3 {frfu_w[1]}} & 3'b011) |
        ({3 {frfc_w[1]}} & 3'b100) |
        ({3 {dtmh_w[1]}} & 3'b001) |
        ({3 {dttp_w[1]}} & 3'b010) |
        ({3 {dtdp_w[1]}} & 3'b011) ) & 
       {3 {fls_ipe_dme_request[1] | (| block_store_w[7:4])}};

assign pipe_dsfsr0_w[2:0] = 
       (({3 {irfu_w[0]}} & 3'b001) |
        ({3 {irfc_w[0]}} & 3'b010) |
        ({3 {frfu_w[0]}} & 3'b011) |
        ({3 {frfc_w[0]}} & 3'b100) |
        ({3 {dtmh_w[0]}} & 3'b001) |
        ({3 {dttp_w[0]}} & 3'b010) |
        ({3 {dtdp_w[0]}} & 3'b011) ) &
       {3 {fls_ipe_dme_request[0] | (| block_store_w[3:0])}};

assign gl1_w[1:0] =
       (trl_gl7[1:0] & {2 {tid_dec_w[7]}}) | 
       (trl_gl6[1:0] & {2 {tid_dec_w[6]}}) | 
       (trl_gl5[1:0] & {2 {tid_dec_w[5]}}) | 
       (trl_gl4[1:0] & {2 {tid_dec_w[4]}}) ;

assign gl0_w[1:0] =
       (trl_gl3[1:0] & {2 {tid_dec_w[3]}}) | 
       (trl_gl2[1:0] & {2 {tid_dec_w[2]}}) | 
       (trl_gl1[1:0] & {2 {tid_dec_w[1]}}) | 
       (trl_gl0[1:0] & {2 {tid_dec_w[0]}}) ;

assign pipe_dsfar1_w[19:0] =
       (({20 {irfu_w[1] | irfc_w[1]}} & 
	 {{5 {1'b0}}, irf1_ecc_check_w[7:0], gl1_w[1:0], 
          irf1_ecc_addr_w[4:0]}) |
	({20 {frfu_w[1] | frfc_w[1]}} & 
	 {frf_ecc_check_w[13:0], frf_ecc_addr_w[5:0]})) & 
	{20 {(| tid_dec_w[7:4]) & 
       (fls_ipe_dme_request[1] | (| block_store_w[7:4]))}};

assign pipe_dsfar0_w[19:0] =
       (({20 {irfu_w[0] | irfc_w[0]}} & 
	 {{5 {1'b0}}, irf0_ecc_check_w[7:0], gl0_w[1:0], 
          irf0_ecc_addr_w[4:0]}) |
	({20 {frfu_w[0] | frfc_w[0]}} & 
	 {frf_ecc_check_w[13:0], frf_ecc_addr_w[5:0]})) & 
	{20 {(| tid_dec_w[3:0]) & 
       (fls_ipe_dme_request[0] | (| block_store_w[3:0]))}};

// Carry pipe DSFSR errors out one more cycle so they only update DSFSR/DSFAR
// if they are the highest priority exceptions

assign ecc_w[1:0] =
       irfu_w[1:0] | irfc_w[1:0] | frfu_w[1:0] | frfc_w[1:0];

tlu_ras_ctl_msff_ctl_macro__width_2 ecc_w1_lat  (
	.scan_in(ecc_w1_lat_scanin),
	.scan_out(ecc_w1_lat_scanout),
	.din	(ecc_w			[1:0]	),
	.dout	(ecc_w1			[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid1_w1_in[1:0] =
       (tid1_w[1:0] & ~{2 {| block_store_w[7:4]}}) |
       {block_store_w[7] | block_store_w[6],
	block_store_w[7] | block_store_w[5]};

tlu_ras_ctl_msff_ctl_macro__width_2 tid1_w1_lat  (
	.scan_in(tid1_w1_lat_scanin),
	.scan_out(tid1_w1_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tid1_w1_in		[1:0]	),
	.dout	(tid1_w1		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid0_w1_in[1:0] =
       (tid0_w[1:0] & ~{2 {| block_store_w[3:0]}}) |
       {block_store_w[3] | block_store_w[2],
	block_store_w[3] | block_store_w[1]};

tlu_ras_ctl_msff_ctl_macro__width_2 tid0_w1_lat  (
	.scan_in(tid0_w1_lat_scanin),
	.scan_out(tid0_w1_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tid0_w1_in		[1:0]	),
	.dout	(tid0_w1		[1:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 pipe_dsfsr1_lat  (
	.scan_in(pipe_dsfsr1_lat_scanin),
	.scan_out(pipe_dsfsr1_lat_scanout),
	.din	(pipe_dsfsr1_w		[2:0]	),
	.dout	(pipe_dsfsr1		[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 pipe_dsfsr0_lat  (
	.scan_in(pipe_dsfsr0_lat_scanin),
	.scan_out(pipe_dsfsr0_lat_scanout),
	.din	(pipe_dsfsr0_w		[2:0]	),
	.dout	(pipe_dsfsr0		[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_20 pipe_dsfar1_lat  (
	.scan_in(pipe_dsfar1_lat_scanin),
	.scan_out(pipe_dsfar1_lat_scanout),
	.din	(pipe_dsfar1_w		[19:0]	),
	.dout	(pipe_dsfar1		[19:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_20 pipe_dsfar0_lat  (
	.scan_in(pipe_dsfar0_lat_scanin),
	.scan_out(pipe_dsfar0_lat_scanout),
	.din	(pipe_dsfar0_w		[19:0]	),
	.dout	(pipe_dsfar0		[19:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tid_dec_w1[7:0] =
       { tid1_w1[1] &  tid1_w1[0],
         tid1_w1[1] & ~tid1_w1[0],
        ~tid1_w1[1] &  tid1_w1[0],
        ~tid1_w1[1] & ~tid1_w1[0],
         tid0_w1[1] &  tid0_w1[0],
         tid0_w1[1] & ~tid0_w1[0],
        ~tid0_w1[1] &  tid0_w1[0],
        ~tid0_w1[1] & ~tid0_w1[0]};


assign pipe_dsfsr_7[2:0] =
       pipe_dsfsr1[2:0] & {3 {tid_dec_w1[7]}};
assign pipe_dsfsr_6[2:0] =
       pipe_dsfsr1[2:0] & {3 {tid_dec_w1[6]}};
assign pipe_dsfsr_5[2:0] =
       pipe_dsfsr1[2:0] & {3 {tid_dec_w1[5]}};
assign pipe_dsfsr_4[2:0] =
       pipe_dsfsr1[2:0] & {3 {tid_dec_w1[4]}};
assign pipe_dsfsr_3[2:0] =
       pipe_dsfsr0[2:0] & {3 {tid_dec_w1[3]}};
assign pipe_dsfsr_2[2:0] =
       pipe_dsfsr0[2:0] & {3 {tid_dec_w1[2]}};
assign pipe_dsfsr_1[2:0] =
       pipe_dsfsr0[2:0] & {3 {tid_dec_w1[1]}};
assign pipe_dsfsr_0[2:0] =
       pipe_dsfsr0[2:0] & {3 {tid_dec_w1[0]}};

assign pipe_dsfar_7[19:0] =
       {20 {ecc_w1[1] & tid_dec_w1[7]}} & pipe_dsfar1[19:0];
assign pipe_dsfar_6[19:0] =
       {20 {ecc_w1[1] & tid_dec_w1[6]}} & pipe_dsfar1[19:0];
assign pipe_dsfar_5[19:0] =
       {20 {ecc_w1[1] & tid_dec_w1[5]}} & pipe_dsfar1[19:0];
assign pipe_dsfar_4[19:0] =
       {20 {ecc_w1[1] & tid_dec_w1[4]}} & pipe_dsfar1[19:0];
assign pipe_dsfar_3[19:0] =
       {20 {ecc_w1[0] & tid_dec_w1[3]}} & pipe_dsfar0[19:0];
assign pipe_dsfar_2[19:0] =
       {20 {ecc_w1[0] & tid_dec_w1[2]}} & pipe_dsfar0[19:0];
assign pipe_dsfar_1[19:0] =
       {20 {ecc_w1[0] & tid_dec_w1[1]}} & pipe_dsfar0[19:0];
assign pipe_dsfar_0[19:0] =
       {20 {ecc_w1[0] & tid_dec_w1[0]}} & pipe_dsfar0[19:0];

assign dsfar_sel_lsu_va_for_error[7:0] = 
       ({{4 {~ecc_w1[1] & (| pipe_dsfsr1[2:0])}},  
	 {4 {~ecc_w1[0] & (| pipe_dsfsr0[2:0])}}} & tid_dec_w1[7:0]) ;

tlu_ras_ctl_msff_ctl_macro__width_8 load_dsfar_lat  (
	.scan_in(load_dsfar_lat_scanin),
	.scan_out(load_dsfar_lat_scanout),
	.din	(fls_load_dsfar		[7:0]	),
	.dout	(load_dsfar		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ras_dsfar_sel_lsu_va[7:0] =
       dsfar_sel_lsu_va_for_error[7:0] |
       load_dsfar[7:0];

// Update DESR in W1

assign i_desr1_w1_in[3:0] =
       i_desr1_w[3:0] & {4 {| tid_dec_w[7:4]}};

assign i_desr0_w1_in[3:0] =
       i_desr0_w[3:0] & {4 {| tid_dec_w[3:0]}};

tlu_ras_ctl_msff_ctl_macro__width_4 i_desr1_w1_lat  (
	.scan_in(i_desr1_w1_lat_scanin),
	.scan_out(i_desr1_w1_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(i_desr1_w1_in		[3:0]	),
	.dout	(i_desr1_w1		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 i_desr0_w1_lat  (
	.scan_in(i_desr0_w1_lat_scanin),
	.scan_out(i_desr0_w1_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(i_desr0_w1_in		[3:0]	),
	.dout	(i_desr0_w1		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pipe_desr_et_7[5:0] =
       {i_desr1_w1[3], 2'b00, i_desr1_w1[2:0]} & {6 {tid_dec_w1[7]}};
assign pipe_desr_et_6[5:0] =			      
       {i_desr1_w1[3], 2'b00, i_desr1_w1[2:0]} & {6 {tid_dec_w1[6]}};
assign pipe_desr_et_5[5:0] =			      
       {i_desr1_w1[3], 2'b00, i_desr1_w1[2:0]} & {6 {tid_dec_w1[5]}};
assign pipe_desr_et_4[5:0] =			      
       {i_desr1_w1[3], 2'b00, i_desr1_w1[2:0]} & {6 {tid_dec_w1[4]}};
assign pipe_desr_et_3[5:0] =			      
       {i_desr0_w1[3], 2'b00, i_desr0_w1[2:0]} & {6 {tid_dec_w1[3]}};
assign pipe_desr_et_2[5:0] =			      
       {i_desr0_w1[3], 2'b00, i_desr0_w1[2:0]} & {6 {tid_dec_w1[2]}};
assign pipe_desr_et_1[5:0] =			      
       {i_desr0_w1[3], 2'b00, i_desr0_w1[2:0]} & {6 {tid_dec_w1[1]}};
assign pipe_desr_et_0[5:0] =			      
       {i_desr0_w1[3], 2'b00, i_desr0_w1[2:0]} & {6 {tid_dec_w1[0]}};


// Hold exception way
tlu_ras_ctl_msff_ctl_macro__width_7 excp_way_lat  (
	.scan_in(excp_way_lat_scanin),
	.scan_out(excp_way_lat_scanout),
	.din	({ftu_excp_tid_d	[2:0],
		  ftu_excp_way_d	[2:0],
		  ftu_excp_way_valid_d	       }),
	.dout	({excp_tid		[2:0],
		  excp_way		[2:0],
		  excp_way_valid	       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign sel_ftu_excp_way[7:0] =
       {(excp_tid[2:0] == 3'b111) & excp_way_valid,
	(excp_tid[2:0] == 3'b110) & excp_way_valid,
	(excp_tid[2:0] == 3'b101) & excp_way_valid,
	(excp_tid[2:0] == 3'b100) & excp_way_valid,
	(excp_tid[2:0] == 3'b011) & excp_way_valid,
	(excp_tid[2:0] == 3'b010) & excp_way_valid,
	(excp_tid[2:0] == 3'b001) & excp_way_valid,
	(excp_tid[2:0] == 3'b000) & excp_way_valid};

assign ic_way7_in[2:0] =
       (excp_way[2:0] & {3 { sel_ftu_excp_way[7]}}) |
       (ic_way7	[2:0] & {3 {~sel_ftu_excp_way[7]}}) ;
			       
assign ic_way6_in[2:0] =     
       (excp_way[2:0] & {3 { sel_ftu_excp_way[6]}}) |
       (ic_way6	[2:0] & {3 {~sel_ftu_excp_way[6]}}) ;
			       
assign ic_way5_in[2:0] =     
       (excp_way[2:0] & {3 { sel_ftu_excp_way[5]}}) |
       (ic_way5	[2:0] & {3 {~sel_ftu_excp_way[5]}}) ;
			       
assign ic_way4_in[2:0] =     
       (excp_way[2:0] & {3 { sel_ftu_excp_way[4]}}) |
       (ic_way4	[2:0] & {3 {~sel_ftu_excp_way[4]}}) ;
			       
assign ic_way3_in[2:0] =     
       (excp_way[2:0] & {3 { sel_ftu_excp_way[3]}}) |
       (ic_way3	[2:0] & {3 {~sel_ftu_excp_way[3]}}) ;
			       
assign ic_way2_in[2:0] =     
       (excp_way[2:0] & {3 { sel_ftu_excp_way[2]}}) |
       (ic_way2	[2:0] & {3 {~sel_ftu_excp_way[2]}}) ;
			       
assign ic_way1_in[2:0] =     
       (excp_way[2:0] & {3 { sel_ftu_excp_way[1]}}) |
       (ic_way1	[2:0] & {3 {~sel_ftu_excp_way[1]}}) ;
			       
assign ic_way0_in[2:0] =     
       (excp_way[2:0] & {3 { sel_ftu_excp_way[0]}}) |
       (ic_way0	[2:0] & {3 {~sel_ftu_excp_way[0]}}) ;

tlu_ras_ctl_msff_ctl_macro__width_3 ic_way7_lat  (
	.scan_in(ic_way7_lat_scanin),
	.scan_out(ic_way7_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(ic_way7_in		[2:0]	),
	.dout	(ic_way7		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 ic_way6_lat  (
	.scan_in(ic_way6_lat_scanin),
	.scan_out(ic_way6_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(ic_way6_in		[2:0]	),
	.dout	(ic_way6		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 ic_way5_lat  (
	.scan_in(ic_way5_lat_scanin),
	.scan_out(ic_way5_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(ic_way5_in		[2:0]	),
	.dout	(ic_way5		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 ic_way4_lat  (
	.scan_in(ic_way4_lat_scanin),
	.scan_out(ic_way4_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(ic_way4_in		[2:0]	),
	.dout	(ic_way4		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 ic_way3_lat  (
	.scan_in(ic_way3_lat_scanin),
	.scan_out(ic_way3_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(ic_way3_in		[2:0]	),
	.dout	(ic_way3		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 ic_way2_lat  (
	.scan_in(ic_way2_lat_scanin),
	.scan_out(ic_way2_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(ic_way2_in		[2:0]	),
	.dout	(ic_way2		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 ic_way1_lat  (
	.scan_in(ic_way1_lat_scanin),
	.scan_out(ic_way1_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(ic_way1_in		[2:0]	),
	.dout	(ic_way1		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 ic_way0_lat  (
	.scan_in(ic_way0_lat_scanin),
	.scan_out(ic_way0_lat_scanout),
	.l1clk	(l1clk_pm2			),
	.din	(ic_way0_in		[2:0]	),
	.dout	(ic_way0		[2:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// Hold pipe DESR address to W1
tlu_ras_ctl_msff_ctl_macro__width_6 pc_1_w1_lat  (
	.scan_in(pc_1_w1_lat_scanin),
	.scan_out(pc_1_w1_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tsd_pc_1_w		[10:5]	),
	.dout	(pc_1_w1		[10:5]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_6 pc_0_w1_lat  (
	.scan_in(pc_0_w1_lat_scanin),
	.scan_out(pc_0_w1_lat_scanout),
	.l1clk	(l1clk_pm1			),
	.din	(tsd_pc_0_w		[10:5]	),
	.dout	(pc_0_w1		[10:5]	),
  .siclk(siclk),
  .soclk(soclk)
);


// Force ea to zero for icl2c
assign pipe_desr_ea_7[8:0] = 
       {ic_way7[2:0], pc_1_w1[10:5]} & 
       {9 {(| pipe_desr_et_7[2:0]) & ~pipe_desr_et_7[5]}};
assign pipe_desr_ea_6[8:0] = 
       {ic_way6[2:0], pc_1_w1[10:5]} & 
       {9 {(| pipe_desr_et_6[2:0]) & ~pipe_desr_et_6[5]}};
assign pipe_desr_ea_5[8:0] = 
       {ic_way5[2:0], pc_1_w1[10:5]} & 
       {9 {(| pipe_desr_et_5[2:0]) & ~pipe_desr_et_5[5]}};
assign pipe_desr_ea_4[8:0] = 
       {ic_way4[2:0], pc_1_w1[10:5]} & 
       {9 {(| pipe_desr_et_4[2:0]) & ~pipe_desr_et_4[5]}};
assign pipe_desr_ea_3[8:0] = 
       {ic_way3[2:0], pc_0_w1[10:5]} & 
       {9 {(| pipe_desr_et_3[2:0]) & ~pipe_desr_et_3[5]}};
assign pipe_desr_ea_2[8:0] = 
       {ic_way2[2:0], pc_0_w1[10:5]} & 
       {9 {(| pipe_desr_et_2[2:0]) & ~pipe_desr_et_2[5]}};
assign pipe_desr_ea_1[8:0] = 
       {ic_way1[2:0], pc_0_w1[10:5]} & 
       {9 {(| pipe_desr_et_1[2:0]) & ~pipe_desr_et_1[5]}};
assign pipe_desr_ea_0[8:0] = 
       {ic_way0[2:0], pc_0_w1[10:5]} & 
       {9 {(| pipe_desr_et_0[2:0]) & ~pipe_desr_et_0[5]}};


//////////////////////////////////////////////////////////////////////////////
//
//  Handle out-of-pipe errors (flop, decode, and record)
//

//
// Incoming encoding
// i/dtmu	101
// i/dtl2c	001
// i/dtl2u	010
// i/dtl2nd	011
//
// ISFSR encodings
// itmu         100
// itl2u	101
// itl2nd       110
//
// DSFSR encodings
// dtmu		100
// dtl2u	101
// dtl2nd	110
//
// DESR encodings
// itl2c	001
// dtl2c	011
// Both have S = 1

assign   itmu_7 = mmu_i_eccerr[7] & (mmu_thr7_err_type[2   ] == 1'b1   );
assign   itmu_6 = mmu_i_eccerr[6] & (mmu_thr6_err_type[2   ] == 1'b1   );
assign   itmu_5 = mmu_i_eccerr[5] & (mmu_thr5_err_type[2   ] == 1'b1   );
assign   itmu_4 = mmu_i_eccerr[4] & (mmu_thr4_err_type[2   ] == 1'b1   );
assign   itmu_3 = mmu_i_eccerr[3] & (mmu_thr3_err_type[2   ] == 1'b1   );
assign   itmu_2 = mmu_i_eccerr[2] & (mmu_thr2_err_type[2   ] == 1'b1   );
assign   itmu_1 = mmu_i_eccerr[1] & (mmu_thr1_err_type[2   ] == 1'b1   );
assign   itmu_0 = mmu_i_eccerr[0] & (mmu_thr0_err_type[2   ] == 1'b1   );

assign  itl2u_7 = mmu_i_eccerr[7] & (mmu_thr7_err_type[2:0] == 3'b010 );
assign  itl2u_6 = mmu_i_eccerr[6] & (mmu_thr6_err_type[2:0] == 3'b010 );
assign  itl2u_5 = mmu_i_eccerr[5] & (mmu_thr5_err_type[2:0] == 3'b010 );
assign  itl2u_4 = mmu_i_eccerr[4] & (mmu_thr4_err_type[2:0] == 3'b010 );
assign  itl2u_3 = mmu_i_eccerr[3] & (mmu_thr3_err_type[2:0] == 3'b010 );
assign  itl2u_2 = mmu_i_eccerr[2] & (mmu_thr2_err_type[2:0] == 3'b010 );
assign  itl2u_1 = mmu_i_eccerr[1] & (mmu_thr1_err_type[2:0] == 3'b010 );
assign  itl2u_0 = mmu_i_eccerr[0] & (mmu_thr0_err_type[2:0] == 3'b010 );

assign itl2nd_7 = mmu_i_eccerr[7] & (mmu_thr7_err_type[2:0] == 3'b011 );
assign itl2nd_6 = mmu_i_eccerr[6] & (mmu_thr6_err_type[2:0] == 3'b011 );
assign itl2nd_5 = mmu_i_eccerr[5] & (mmu_thr5_err_type[2:0] == 3'b011 );
assign itl2nd_4 = mmu_i_eccerr[4] & (mmu_thr4_err_type[2:0] == 3'b011 );
assign itl2nd_3 = mmu_i_eccerr[3] & (mmu_thr3_err_type[2:0] == 3'b011 );
assign itl2nd_2 = mmu_i_eccerr[2] & (mmu_thr2_err_type[2:0] == 3'b011 );
assign itl2nd_1 = mmu_i_eccerr[1] & (mmu_thr1_err_type[2:0] == 3'b011 );
assign itl2nd_0 = mmu_i_eccerr[0] & (mmu_thr0_err_type[2:0] == 3'b011 );


assign m_isfsr_7[2:0] =
       ({3 {  itmu_7}} & 3'b100) | 
       ({3 { itl2u_7}} & 3'b101) | 
       ({3 {itl2nd_7}} & 3'b110) ;
assign m_isfsr_6[2:0] =
       ({3 {  itmu_6}} & 3'b100) | 
       ({3 { itl2u_6}} & 3'b101) | 
       ({3 {itl2nd_6}} & 3'b110) ;
assign m_isfsr_5[2:0] =
       ({3 {  itmu_5}} & 3'b100) | 
       ({3 { itl2u_5}} & 3'b101) | 
       ({3 {itl2nd_5}} & 3'b110) ;
assign m_isfsr_4[2:0] =
       ({3 {  itmu_4}} & 3'b100) | 
       ({3 { itl2u_4}} & 3'b101) | 
       ({3 {itl2nd_4}} & 3'b110) ;
assign m_isfsr_3[2:0] =
       ({3 {  itmu_3}} & 3'b100) | 
       ({3 { itl2u_3}} & 3'b101) | 
       ({3 {itl2nd_3}} & 3'b110) ;
assign m_isfsr_2[2:0] =
       ({3 {  itmu_2}} & 3'b100) | 
       ({3 { itl2u_2}} & 3'b101) | 
       ({3 {itl2nd_2}} & 3'b110) ;
assign m_isfsr_1[2:0] =
       ({3 {  itmu_1}} & 3'b100) | 
       ({3 { itl2u_1}} & 3'b101) | 
       ({3 {itl2nd_1}} & 3'b110) ;
assign m_isfsr_0[2:0] =
       ({3 {  itmu_0}} & 3'b100) | 
       ({3 { itl2u_0}} & 3'b101) | 
       ({3 {itl2nd_0}} & 3'b110) ;


assign   dtmu_7 = mmu_d_eccerr[7] & (mmu_thr7_err_type[2  ] == 1'b1  );
assign   dtmu_6 = mmu_d_eccerr[6] & (mmu_thr6_err_type[2  ] == 1'b1  );
assign   dtmu_5 = mmu_d_eccerr[5] & (mmu_thr5_err_type[2  ] == 1'b1  );
assign   dtmu_4 = mmu_d_eccerr[4] & (mmu_thr4_err_type[2  ] == 1'b1  );
assign   dtmu_3 = mmu_d_eccerr[3] & (mmu_thr3_err_type[2  ] == 1'b1  );
assign   dtmu_2 = mmu_d_eccerr[2] & (mmu_thr2_err_type[2  ] == 1'b1  );
assign   dtmu_1 = mmu_d_eccerr[1] & (mmu_thr1_err_type[2  ] == 1'b1  );
assign   dtmu_0 = mmu_d_eccerr[0] & (mmu_thr0_err_type[2  ] == 1'b1  );

assign  dtl2u_7 = mmu_d_eccerr[7] & (mmu_thr7_err_type[2:0] == 3'b010);
assign  dtl2u_6 = mmu_d_eccerr[6] & (mmu_thr6_err_type[2:0] == 3'b010);
assign  dtl2u_5 = mmu_d_eccerr[5] & (mmu_thr5_err_type[2:0] == 3'b010);
assign  dtl2u_4 = mmu_d_eccerr[4] & (mmu_thr4_err_type[2:0] == 3'b010);
assign  dtl2u_3 = mmu_d_eccerr[3] & (mmu_thr3_err_type[2:0] == 3'b010);
assign  dtl2u_2 = mmu_d_eccerr[2] & (mmu_thr2_err_type[2:0] == 3'b010);
assign  dtl2u_1 = mmu_d_eccerr[1] & (mmu_thr1_err_type[2:0] == 3'b010);
assign  dtl2u_0 = mmu_d_eccerr[0] & (mmu_thr0_err_type[2:0] == 3'b010);
								     	
assign dtl2nd_7 = mmu_d_eccerr[7] & (mmu_thr7_err_type[2:0] == 3'b011);
assign dtl2nd_6 = mmu_d_eccerr[6] & (mmu_thr6_err_type[2:0] == 3'b011);
assign dtl2nd_5 = mmu_d_eccerr[5] & (mmu_thr5_err_type[2:0] == 3'b011);
assign dtl2nd_4 = mmu_d_eccerr[4] & (mmu_thr4_err_type[2:0] == 3'b011);
assign dtl2nd_3 = mmu_d_eccerr[3] & (mmu_thr3_err_type[2:0] == 3'b011);
assign dtl2nd_2 = mmu_d_eccerr[2] & (mmu_thr2_err_type[2:0] == 3'b011);
assign dtl2nd_1 = mmu_d_eccerr[1] & (mmu_thr1_err_type[2:0] == 3'b011);
assign dtl2nd_0 = mmu_d_eccerr[0] & (mmu_thr0_err_type[2:0] == 3'b011);

assign m_dsfsr_7[2:0] =
       ({3 {  dtmu_7}} & 3'b100) | 
       ({3 { dtl2u_7}} & 3'b101) | 
       ({3 {dtl2nd_7}} & 3'b110) ;
assign m_dsfsr_6[2:0] =
       ({3 {  dtmu_6}} & 3'b100) | 
       ({3 { dtl2u_6}} & 3'b101) | 
       ({3 {dtl2nd_6}} & 3'b110) ;
assign m_dsfsr_5[2:0] =
       ({3 {  dtmu_5}} & 3'b100) | 
       ({3 { dtl2u_5}} & 3'b101) | 
       ({3 {dtl2nd_5}} & 3'b110) ;
assign m_dsfsr_4[2:0] =
       ({3 {  dtmu_4}} & 3'b100) | 
       ({3 { dtl2u_4}} & 3'b101) | 
       ({3 {dtl2nd_4}} & 3'b110) ;
assign m_dsfsr_3[2:0] =
       ({3 {  dtmu_3}} & 3'b100) | 
       ({3 { dtl2u_3}} & 3'b101) | 
       ({3 {dtl2nd_3}} & 3'b110) ;
assign m_dsfsr_2[2:0] =
       ({3 {  dtmu_2}} & 3'b100) | 
       ({3 { dtl2u_2}} & 3'b101) | 
       ({3 {dtl2nd_2}} & 3'b110) ;
assign m_dsfsr_1[2:0] =
       ({3 {  dtmu_1}} & 3'b100) | 
       ({3 { dtl2u_1}} & 3'b101) | 
       ({3 {dtl2nd_1}} & 3'b110) ;
assign m_dsfsr_0[2:0] =
       ({3 {  dtmu_0}} & 3'b100) | 
       ({3 { dtl2u_0}} & 3'b101) | 
       ({3 {dtl2nd_0}} & 3'b110) ;

assign m_dsfar_7[2:0] =
       mmu_thr7_err_index[2:0] & {3 {mmu_i_eccerr[7] | mmu_d_eccerr[7]}};
assign m_dsfar_6[2:0] =	                                         
       mmu_thr6_err_index[2:0] & {3 {mmu_i_eccerr[6] | mmu_d_eccerr[6]}};
assign m_dsfar_5[2:0] =	                                         
       mmu_thr5_err_index[2:0] & {3 {mmu_i_eccerr[5] | mmu_d_eccerr[5]}};
assign m_dsfar_4[2:0] =	                                         
       mmu_thr4_err_index[2:0] & {3 {mmu_i_eccerr[4] | mmu_d_eccerr[4]}};
assign m_dsfar_3[2:0] =	                                         
       mmu_thr3_err_index[2:0] & {3 {mmu_i_eccerr[3] | mmu_d_eccerr[3]}};
assign m_dsfar_2[2:0] =	                                         
       mmu_thr2_err_index[2:0] & {3 {mmu_i_eccerr[2] | mmu_d_eccerr[2]}};
assign m_dsfar_1[2:0] =	                                         
       mmu_thr1_err_index[2:0] & {3 {mmu_i_eccerr[1] | mmu_d_eccerr[1]}};
assign m_dsfar_0[2:0] =	                                         
       mmu_thr0_err_index[2:0] & {3 {mmu_i_eccerr[0] | mmu_d_eccerr[0]}};


tlu_ras_ctl_msff_ctl_macro__width_8 it2lc_lat  (
	.scan_in(it2lc_lat_scanin),
	.scan_out(it2lc_lat_scanout),
	.din	(mmu_i_l2cerr		[7:0]	),
	.dout	(m_i_l2cerr		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_8 dt2lc_lat  (
	.scan_in(dt2lc_lat_scanin),
	.scan_out(dt2lc_lat_scanout),
	.din	(mmu_d_l2cerr		[7:0]	),
	.dout	(m_d_l2cerr		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign itl2c_7 = m_i_l2cerr[7];
assign itl2c_6 = m_i_l2cerr[6];
assign itl2c_5 = m_i_l2cerr[5];
assign itl2c_4 = m_i_l2cerr[4];
assign itl2c_3 = m_i_l2cerr[3];
assign itl2c_2 = m_i_l2cerr[2];
assign itl2c_1 = m_i_l2cerr[1];
assign itl2c_0 = m_i_l2cerr[0];
		  
assign dtl2c_7 = m_d_l2cerr[7];
assign dtl2c_6 = m_d_l2cerr[6];
assign dtl2c_5 = m_d_l2cerr[5];
assign dtl2c_4 = m_d_l2cerr[4];
assign dtl2c_3 = m_d_l2cerr[3];
assign dtl2c_2 = m_d_l2cerr[2];
assign dtl2c_1 = m_d_l2cerr[1];
assign dtl2c_0 = m_d_l2cerr[0];

assign m_desr_et_7[5:0] = 
       ({6 { itl2c_7}} & 6'b100001) |
       ({6 { dtl2c_7}} & 6'b100011) ; 
assign m_desr_et_6[5:0] = 
       ({6 { itl2c_6}} & 6'b100001) |
       ({6 { dtl2c_6}} & 6'b100011) ; 
assign m_desr_et_5[5:0] = 
       ({6 { itl2c_5}} & 6'b100001) |
       ({6 { dtl2c_5}} & 6'b100011) ; 
assign m_desr_et_4[5:0] = 
       ({6 { itl2c_4}} & 6'b100001) |
       ({6 { dtl2c_4}} & 6'b100011) ; 
assign m_desr_et_3[5:0] = 
       ({6 { itl2c_3}} & 6'b100001) |
       ({6 { dtl2c_3}} & 6'b100011) ; 
assign m_desr_et_2[5:0] = 
       ({6 { itl2c_2}} & 6'b100001) |
       ({6 { dtl2c_2}} & 6'b100011) ; 
assign m_desr_et_1[5:0] = 
       ({6 { itl2c_1}} & 6'b100001) |
       ({6 { dtl2c_1}} & 6'b100011) ; 
assign m_desr_et_0[5:0] = 
       ({6 { itl2c_0}} & 6'b100001) |
       ({6 { dtl2c_0}} & 6'b100011) ; 

// No desr_ea for L2 correctable errors for MMU


//
// MRA, SCA, and TCA precise but out-of-pipe errors (ASI access)
//
// DSFSR
// mrau		0111
// scac		1010
// scau		1001
// tccp		1100
// tccu(tcup)	1101

// Both sources should have same TID
// but TCA errors take a cycle longer to be recorded due to longer path for
// disrupting TCA errors
assign a_tid[2:0] =
       tlu_tca_tid[2:0];

assign a_dec_tid[7:0] =
       { a_tid[2] &  a_tid[1] &  a_tid[0],
         a_tid[2] &  a_tid[1] & ~a_tid[0],
         a_tid[2] & ~a_tid[1] &  a_tid[0],
         a_tid[2] & ~a_tid[1] & ~a_tid[0],
        ~a_tid[2] &  a_tid[1] &  a_tid[0],
        ~a_tid[2] &  a_tid[1] & ~a_tid[0],
        ~a_tid[2] & ~a_tid[1] &  a_tid[0],
        ~a_tid[2] & ~a_tid[1] & ~a_tid[0]} & 
       {8 {mrau | scac | scau}};


tlu_ras_ctl_msff_ctl_macro__width_5 tca_error_lat  (
	.scan_in(tca_error_lat_scanin),
	.scan_out(tca_error_lat_scanout),
	.din	({cel_tccp		       ,
		  cel_tcup		       ,
		  tlu_tca_tid		[2:0]}),
	.dout	({tccp			       ,
		  tcup			       ,
		  tca_tid		[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tca_dec_tid[7:0] =
       { tca_tid[2] &  tca_tid[1] &  tca_tid[0],
         tca_tid[2] &  tca_tid[1] & ~tca_tid[0],
         tca_tid[2] & ~tca_tid[1] &  tca_tid[0],
         tca_tid[2] & ~tca_tid[1] & ~tca_tid[0],
        ~tca_tid[2] &  tca_tid[1] &  tca_tid[0],
        ~tca_tid[2] &  tca_tid[1] & ~tca_tid[0],
        ~tca_tid[2] & ~tca_tid[1] &  tca_tid[0],
        ~tca_tid[2] & ~tca_tid[1] & ~tca_tid[0]} & 
       {8 {tccp | tcup}};

assign mrau =
       mmu_asi_uecc &  mmu_asi_mra_not_sca;
assign scac =
       mmu_asi_cecc & ~mmu_asi_mra_not_sca;
assign scau =
       mmu_asi_uecc & ~mmu_asi_mra_not_sca;

assign a_dsfsr[3:0] = 
       ({4 {mrau}} & 4'b0111) |
       ({4 {scac}} & 4'b1010) | 
       ({4 {scau}} & 4'b1011) ;
assign tca_dsfsr[3:0] = 
       ({4 {tccp}} & 4'b1100) | 
       ({4 {tcup}} & 4'b1101) ;
assign a_dsfsr_7[3:0] =
       (  a_dsfsr[3:0] & {4 {  a_dec_tid[7]}}) |
       (tca_dsfsr[3:0] & {4 {tca_dec_tid[7]}}) ;
assign a_dsfsr_6[3:0] =
       (  a_dsfsr[3:0] & {4 {  a_dec_tid[6]}}) |
       (tca_dsfsr[3:0] & {4 {tca_dec_tid[6]}}) ;
assign a_dsfsr_5[3:0] =
       (  a_dsfsr[3:0] & {4 {  a_dec_tid[5]}}) |
       (tca_dsfsr[3:0] & {4 {tca_dec_tid[5]}}) ;
assign a_dsfsr_4[3:0] =
       (  a_dsfsr[3:0] & {4 {  a_dec_tid[4]}}) |
       (tca_dsfsr[3:0] & {4 {tca_dec_tid[4]}}) ;
assign a_dsfsr_3[3:0] =
       (  a_dsfsr[3:0] & {4 {  a_dec_tid[3]}}) |
       (tca_dsfsr[3:0] & {4 {tca_dec_tid[3]}}) ;
assign a_dsfsr_2[3:0] =
       (  a_dsfsr[3:0] & {4 {  a_dec_tid[2]}}) |
       (tca_dsfsr[3:0] & {4 {tca_dec_tid[2]}}) ;
assign a_dsfsr_1[3:0] =
       (  a_dsfsr[3:0] & {4 {  a_dec_tid[1]}}) |
       (tca_dsfsr[3:0] & {4 {tca_dec_tid[1]}}) ;
assign a_dsfsr_0[3:0] =
       (  a_dsfsr[3:0] & {4 {  a_dec_tid[0]}}) |
       (tca_dsfsr[3:0] & {4 {tca_dec_tid[0]}}) ;

assign a_dsfar[10:0] =
       ({11 {scac | scau}} &             mmu_asi_index[10:0] ) |
       ({11 {mrau       }} &{{8 {1'b0}}, mmu_asi_index[2:0]}) ;
assign tca_dsfar[10:0] = 
       ({11 {tccp | tcup}} & 
	{1'b0, cel_syndrome[7:0], tlu_tca_index[1:0]}) ;

assign a_dsfar_7[10:0] =
       (  a_dsfar[10:0] & {11 {  a_dec_tid[7]}}) |
       (tca_dsfar[10:0] & {11 {tca_dec_tid[7]}}) ;
assign a_dsfar_6[10:0] =
       (  a_dsfar[10:0] & {11 {  a_dec_tid[6]}}) |
       (tca_dsfar[10:0] & {11 {tca_dec_tid[6]}}) ;
assign a_dsfar_5[10:0] =
       (  a_dsfar[10:0] & {11 {  a_dec_tid[5]}}) |
       (tca_dsfar[10:0] & {11 {tca_dec_tid[5]}}) ;
assign a_dsfar_4[10:0] =
       (  a_dsfar[10:0] & {11 {  a_dec_tid[4]}}) |
       (tca_dsfar[10:0] & {11 {tca_dec_tid[4]}}) ;
assign a_dsfar_3[10:0] =
       (  a_dsfar[10:0] & {11 {  a_dec_tid[3]}}) |
       (tca_dsfar[10:0] & {11 {tca_dec_tid[3]}}) ;
assign a_dsfar_2[10:0] =
       (  a_dsfar[10:0] & {11 {  a_dec_tid[2]}}) |
       (tca_dsfar[10:0] & {11 {tca_dec_tid[2]}}) ;
assign a_dsfar_1[10:0] =
       (  a_dsfar[10:0] & {11 {  a_dec_tid[1]}}) |
       (tca_dsfar[10:0] & {11 {tca_dec_tid[1]}}) ;
assign a_dsfar_0[10:0] =
       (  a_dsfar[10:0] & {11 {  a_dec_tid[0]}}) |
       (tca_dsfar[10:0] & {11 {tca_dec_tid[0]}}) ;


//
// TSA precise but out-of-pipe errors (ASI access and done and retry)
//
// DSFSR
// tsac 1000
// tsau 1001

assign ta_dec_tid[7:0] = 
       { asi_tsacu_tid[2] &  asi_tsacu_tid[1] &  asi_tsacu_tid[0],
         asi_tsacu_tid[2] &  asi_tsacu_tid[1] & ~asi_tsacu_tid[0],
         asi_tsacu_tid[2] & ~asi_tsacu_tid[1] &  asi_tsacu_tid[0],
         asi_tsacu_tid[2] & ~asi_tsacu_tid[1] & ~asi_tsacu_tid[0],
        ~asi_tsacu_tid[2] &  asi_tsacu_tid[1] &  asi_tsacu_tid[0],
        ~asi_tsacu_tid[2] &  asi_tsacu_tid[1] & ~asi_tsacu_tid[0],
        ~asi_tsacu_tid[2] & ~asi_tsacu_tid[1] &  asi_tsacu_tid[0],
        ~asi_tsacu_tid[2] & ~asi_tsacu_tid[1] & ~asi_tsacu_tid[0]};

assign tsac[7:0] =
       tlu_tsac[7:0] | ({8 {asi_tsac}} & ta_dec_tid[7:0]);

assign tsau[7:0] =
       tlu_tsau[7:0] | ({8 {asi_tsau}} & ta_dec_tid[7:0]);

assign ras_dsfar_sel_tsa[7:0] =
       tsac[7:0] | tsau[7:0];

assign t_dsfsr_7[3:0] =
       ({4 {tsac[7]}} & 4'b1000) |
       ({4 {tsau[7]}} & 4'b1001) ;
assign t_dsfsr_6[3:0] =
       ({4 {tsac[6]}} & 4'b1000) |
       ({4 {tsau[6]}} & 4'b1001) ;
assign t_dsfsr_5[3:0] =
       ({4 {tsac[5]}} & 4'b1000) |
       ({4 {tsau[5]}} & 4'b1001) ;
assign t_dsfsr_4[3:0] =
       ({4 {tsac[4]}} & 4'b1000) |
       ({4 {tsau[4]}} & 4'b1001) ;
assign t_dsfsr_3[3:0] =
       ({4 {tsac[3]}} & 4'b1000) |
       ({4 {tsau[3]}} & 4'b1001) ;
assign t_dsfsr_2[3:0] =
       ({4 {tsac[2]}} & 4'b1000) |
       ({4 {tsau[2]}} & 4'b1001) ;
assign t_dsfsr_1[3:0] =
       ({4 {tsac[1]}} & 4'b1000) |
       ({4 {tsau[1]}} & 4'b1001) ;
assign t_dsfsr_0[3:0] =
       ({4 {tsac[0]}} & 4'b1000) |
       ({4 {tsau[0]}} & 4'b1001) ;

// DSFAR for TSA errors handled in tlu_dfd_dp


//
// Data cache errors on L2
//
// DSFSR
// dcl2u	001
// dcl2nd	010
// socc         011
// socu         100
//
// DESR
// dcl2c       1011
// This has S = 0 
// dcl2c	100
// This has S = 1

tlu_ras_ctl_msff_ctl_macro__width_9 l_dsfar_lat  (
	.scan_in(l_dsfar_lat_scanin),
	.scan_out(l_dsfar_lat_scanout),
	.din	(lsu_dcerr_sfar_g	[8:0]	),
	.dout	(l_dsfar		[8:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 l_tid_lat  (
	.scan_in(l_tid_lat_scanin),
	.scan_out(l_tid_lat_scanout),
	.din	(lsu_dcerr_tid_g	[2:0]	),
	.dout	(l_tid			[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 dcl2c_lat  (
	.scan_in(dcl2c_lat_scanin),
	.scan_out(dcl2c_lat_scanout),
	.din	(lsu_dcl2c_err_g		),
	.dout	(dcl2c				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 dcl2u_lat  (
	.scan_in(dcl2u_lat_scanin),
	.scan_out(dcl2u_lat_scanout),
	.din	(lsu_dcl2u_err_g		),
	.dout	(dcl2u				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 dcl2nd_lat  (
	.scan_in(dcl2nd_lat_scanin),
	.scan_out(dcl2nd_lat_scanout),
	.din	(lsu_dcl2nd_err_g		),
	.dout	(dcl2nd				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 dcsoc_lat  (
	.scan_in(dcsoc_lat_scanin),
	.scan_out(dcsoc_lat_scanout),
	.din	(lsu_dcsoc_err_g		),
	.dout	(dcsoc				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign l_dec_tid[7:0] =
       { l_tid[2] &  l_tid[1] &  l_tid[0],
         l_tid[2] &  l_tid[1] & ~l_tid[0],
         l_tid[2] & ~l_tid[1] &  l_tid[0],
         l_tid[2] & ~l_tid[1] & ~l_tid[0],
        ~l_tid[2] &  l_tid[1] &  l_tid[0],
        ~l_tid[2] &  l_tid[1] & ~l_tid[0],
        ~l_tid[2] & ~l_tid[1] &  l_tid[0],
        ~l_tid[2] & ~l_tid[1] & ~l_tid[0]} & {8 {dcl2c | dcl2u | dcl2nd}};

assign l_dsfsr[2:0] =
       ({3 {dcl2u  & ~dcsoc}} & 3'b001) |
       ({3 {dcl2nd & ~dcsoc}} & 3'b010) |
       ({3 {dcl2u  &  dcsoc}} & 3'b100) ;

assign l_dsfsr_7[2:0] =
       l_dsfsr[2:0] & {3 {l_dec_tid[7]}};
assign l_dsfsr_6[2:0] =
       l_dsfsr[2:0] & {3 {l_dec_tid[6]}};
assign l_dsfsr_5[2:0] =
       l_dsfsr[2:0] & {3 {l_dec_tid[5]}};
assign l_dsfsr_4[2:0] =
       l_dsfsr[2:0] & {3 {l_dec_tid[4]}};
assign l_dsfsr_3[2:0] =
       l_dsfsr[2:0] & {3 {l_dec_tid[3]}};
assign l_dsfsr_2[2:0] =
       l_dsfsr[2:0] & {3 {l_dec_tid[2]}};
assign l_dsfsr_1[2:0] =
       l_dsfsr[2:0] & {3 {l_dec_tid[1]}};
assign l_dsfsr_0[2:0] =
       l_dsfsr[2:0] & {3 {l_dec_tid[0]}};

assign l_dsfar_7[8:0] =
       l_dsfar[8:0] & {9 {l_dec_tid[7]}};
assign l_dsfar_6[8:0] =
       l_dsfar[8:0] & {9 {l_dec_tid[6]}};
assign l_dsfar_5[8:0] =
       l_dsfar[8:0] & {9 {l_dec_tid[5]}};
assign l_dsfar_4[8:0] =
       l_dsfar[8:0] & {9 {l_dec_tid[4]}};
assign l_dsfar_3[8:0] =
       l_dsfar[8:0] & {9 {l_dec_tid[3]}};
assign l_dsfar_2[8:0] =
       l_dsfar[8:0] & {9 {l_dec_tid[2]}};
assign l_dsfar_1[8:0] =
       l_dsfar[8:0] & {9 {l_dec_tid[1]}};
assign l_dsfar_0[8:0] =
       l_dsfar[8:0] & {9 {l_dec_tid[0]}};


assign l_desr_et[5:0] = 
       ({6 {dcl2c  &  dcsoc}} & 6'b001011) |
       ({6 {dcl2c  & ~dcsoc}} & 6'b100100) ;

assign l_desr_et_7[5:0] =
       l_desr_et[5:0] & {6 {l_dec_tid[7]}};
assign l_desr_et_6[5:0] =
       l_desr_et[5:0] & {6 {l_dec_tid[6]}};
assign l_desr_et_5[5:0] =
       l_desr_et[5:0] & {6 {l_dec_tid[5]}};
assign l_desr_et_4[5:0] =
       l_desr_et[5:0] & {6 {l_dec_tid[4]}};
assign l_desr_et_3[5:0] =
       l_desr_et[5:0] & {6 {l_dec_tid[3]}};
assign l_desr_et_2[5:0] =
       l_desr_et[5:0] & {6 {l_dec_tid[2]}};
assign l_desr_et_1[5:0] =
       l_desr_et[5:0] & {6 {l_dec_tid[1]}};
assign l_desr_et_0[5:0] =
       l_desr_et[5:0] & {6 {l_dec_tid[0]}};


//
// Precise but out-of-pipe store buffer errors
//
// DSFSR
// sbdlc	101
// sbdlu	110

tlu_ras_ctl_msff_ctl_macro__width_5 s_dsfar_lat  (
	.scan_in(s_dsfar_lat_scanin),
	.scan_out(s_dsfar_lat_scanout),
	.din	({lsu_stberr_priv_g	[1:0],
		  lsu_stberr_index_g	[2:0]}),
	.dout	({fesr_priv		[1:0],
		  s_dsfar		[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 s_tid_lat  (
	.scan_in(s_tid_lat_scanin),
	.scan_out(s_tid_lat_scanout),
	.din	(lsu_stberr_tid_g	[2:0]	),
	.dout	(s_tid			[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 stb_flush_lat  (
	.scan_in(stb_flush_lat_scanin),
	.scan_out(stb_flush_lat_scanout),
	.din	(lsu_stb_flush_g		),
	.dout	(stb_flush			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign update_priv[7:0] =
       {8 {stb_flush}} & s_dsfsr_dec_tid_raw[7:0] & 
       {(fesr_priv[1] & ~dfd_fesr_priv_7[1]                       ) | 
	(fesr_priv[0] & ~dfd_fesr_priv_7[1] & ~dfd_fesr_priv_7[0]),
        (fesr_priv[1] & ~dfd_fesr_priv_6[1]                       ) | 
	(fesr_priv[0] & ~dfd_fesr_priv_6[1] & ~dfd_fesr_priv_6[0]),
        (fesr_priv[1] & ~dfd_fesr_priv_5[1]                       ) | 
	(fesr_priv[0] & ~dfd_fesr_priv_5[1] & ~dfd_fesr_priv_5[0]),
        (fesr_priv[1] & ~dfd_fesr_priv_4[1]                       ) | 
	(fesr_priv[0] & ~dfd_fesr_priv_4[1] & ~dfd_fesr_priv_4[0]),
        (fesr_priv[1] & ~dfd_fesr_priv_3[1]                       ) | 
	(fesr_priv[0] & ~dfd_fesr_priv_3[1] & ~dfd_fesr_priv_3[0]),
        (fesr_priv[1] & ~dfd_fesr_priv_2[1]                       ) | 
	(fesr_priv[0] & ~dfd_fesr_priv_2[1] & ~dfd_fesr_priv_2[0]),
        (fesr_priv[1] & ~dfd_fesr_priv_1[1]                       ) | 
	(fesr_priv[0] & ~dfd_fesr_priv_1[1] & ~dfd_fesr_priv_1[0]),
        (fesr_priv[1] & ~dfd_fesr_priv_0[1]                       ) | 
	(fesr_priv[0] & ~dfd_fesr_priv_0[1] & ~dfd_fesr_priv_0[0])  };

assign ras_update_priv[7:0] =
       update_priv[7:0];

assign ras_fesr_priv[59:58] =
       fesr_priv[1:0];

tlu_ras_ctl_msff_ctl_macro__width_1 sbdlc_lat  (
	.scan_in(sbdlc_lat_scanin),
	.scan_out(sbdlc_lat_scanout),
	.din	(lsu_sbdlc_err_g		),
	.dout	(sbdlc				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 sbdlu_lat  (
	.scan_in(sbdlu_lat_scanin),
	.scan_out(sbdlu_lat_scanout),
	.din	(lsu_sbdlu_err_g		),
	.dout	(sbdlu				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign s_dsfsr_dec_tid_raw[7:0] =
       { s_tid[2] &  s_tid[1] &  s_tid[0],
         s_tid[2] &  s_tid[1] & ~s_tid[0],
         s_tid[2] & ~s_tid[1] &  s_tid[0],
         s_tid[2] & ~s_tid[1] & ~s_tid[0],
        ~s_tid[2] &  s_tid[1] &  s_tid[0],
        ~s_tid[2] &  s_tid[1] & ~s_tid[0],
        ~s_tid[2] & ~s_tid[1] &  s_tid[0],
        ~s_tid[2] & ~s_tid[1] & ~s_tid[0]} ;
assign s_dsfsr_dec_tid[7:0] =
       s_dsfsr_dec_tid_raw[7:0] & 
       {8 {sbdlc | sbdlu}};

assign s_dsfsr[2:0] =
       ({3 {sbdlc}} & 3'b101) |
       ({3 {sbdlu}} & 3'b110) ;

assign s_dsfsr_7[2:0] =
       s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[7]}};
assign s_dsfsr_6[2:0] =
       s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[6]}};
assign s_dsfsr_5[2:0] =
       s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[5]}};
assign s_dsfsr_4[2:0] =
       s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[4]}};
assign s_dsfsr_3[2:0] =
       s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[3]}};
assign s_dsfsr_2[2:0] =
       s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[2]}};
assign s_dsfsr_1[2:0] =
       s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[1]}};
assign s_dsfsr_0[2:0] =
       s_dsfsr[2:0] & {3 {s_dsfsr_dec_tid[0]}};

assign s_dsfar_7[2:0] =
       s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[7]}};
assign s_dsfar_6[2:0] =
       s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[6]}};
assign s_dsfar_5[2:0] =
       s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[5]}};
assign s_dsfar_4[2:0] =
       s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[4]}};
assign s_dsfar_3[2:0] =
       s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[3]}};
assign s_dsfar_2[2:0] =
       s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[2]}};
assign s_dsfar_1[2:0] =
       s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[1]}};
assign s_dsfar_0[2:0] =
       s_dsfar[2:0] & {3 {s_dsfsr_dec_tid[0]}};


//////////////////////////////////////////////////////////////////////////////
//
//  Instantiate ISFSRs
//

assign isfsr_7_new_in[2:0] = 
       pipe_isfsr_7[2:0] | m_isfsr_7[2:0] ;
assign isfsr_6_new_in[2:0] = 
       pipe_isfsr_6[2:0] | m_isfsr_6[2:0] ;
assign isfsr_5_new_in[2:0] = 
       pipe_isfsr_5[2:0] | m_isfsr_5[2:0] ;
assign isfsr_4_new_in[2:0] = 
       pipe_isfsr_4[2:0] | m_isfsr_4[2:0] ;
assign isfsr_3_new_in[2:0] = 
       pipe_isfsr_3[2:0] | m_isfsr_3[2:0] ;
assign isfsr_2_new_in[2:0] = 
       pipe_isfsr_2[2:0] | m_isfsr_2[2:0] ;
assign isfsr_1_new_in[2:0] = 
       pipe_isfsr_1[2:0] | m_isfsr_1[2:0] ;
assign isfsr_0_new_in[2:0] = 
       pipe_isfsr_0[2:0] | m_isfsr_0[2:0] ;

assign isfsr_7_in[2:0] =
       (isfsr_7_new_in[2:0] & {3 {~asi_wr_isfsr[7]}}) |
       (isfsr_7[2:0] & ~{3 {| {asi_wr_isfsr[7], isfsr_7_new_in[2:0]}}}) |
       (asi_wr_data[2:0] & {3 { asi_wr_isfsr[7]}}) ;
assign isfsr_6_in[2:0] =
       (isfsr_6_new_in[2:0] & {3 {~asi_wr_isfsr[6]}}) |
       (isfsr_6[2:0] & ~{3 {| {asi_wr_isfsr[6], isfsr_6_new_in[2:0]}}}) |
       (asi_wr_data[2:0] & {3 { asi_wr_isfsr[6]}}) ;
assign isfsr_5_in[2:0] =
       (isfsr_5_new_in[2:0] & {3 {~asi_wr_isfsr[5]}}) |
       (isfsr_5[2:0] & ~{3 {| {asi_wr_isfsr[5], isfsr_5_new_in[2:0]}}}) |
       (asi_wr_data[2:0] & {3 { asi_wr_isfsr[5]}}) ;
assign isfsr_4_in[2:0] =
       (isfsr_4_new_in[2:0] & {3 {~asi_wr_isfsr[4]}}) |
       (isfsr_4[2:0] & ~{3 {| {asi_wr_isfsr[4], isfsr_4_new_in[2:0]}}}) |
       (asi_wr_data[2:0] & {3 { asi_wr_isfsr[4]}}) ;
assign isfsr_3_in[2:0] =
       (isfsr_3_new_in[2:0] & {3 {~asi_wr_isfsr[3]}}) |
       (isfsr_3[2:0] & ~{3 {| {asi_wr_isfsr[3], isfsr_3_new_in[2:0]}}}) |
       (asi_wr_data[2:0] & {3 { asi_wr_isfsr[3]}}) ;
assign isfsr_2_in[2:0] =
       (isfsr_2_new_in[2:0] & {3 {~asi_wr_isfsr[2]}}) |
       (isfsr_2[2:0] & ~{3 {| {asi_wr_isfsr[2], isfsr_2_new_in[2:0]}}}) |
       (asi_wr_data[2:0] & {3 { asi_wr_isfsr[2]}}) ;
assign isfsr_1_in[2:0] =
       (isfsr_1_new_in[2:0] & {3 {~asi_wr_isfsr[1]}}) |
       (isfsr_1[2:0] & ~{3 {| {asi_wr_isfsr[1], isfsr_1_new_in[2:0]}}}) |
       (asi_wr_data[2:0] & {3 { asi_wr_isfsr[1]}}) ;
assign isfsr_0_in[2:0] =
       (isfsr_0_new_in[2:0] & {3 {~asi_wr_isfsr[0]}}) |
       (isfsr_0[2:0] & ~{3 {| {asi_wr_isfsr[0], isfsr_0_new_in[2:0]}}}) |
       (asi_wr_data[2:0] & {3 { asi_wr_isfsr[0]}}) ;

assign precise_i_error[7:0] = 
       { | {pipe_isfsr_7[2:0], m_isfsr_7[2:0]}, 
         | {pipe_isfsr_6[2:0], m_isfsr_6[2:0]}, 
         | {pipe_isfsr_5[2:0], m_isfsr_5[2:0]}, 
         | {pipe_isfsr_4[2:0], m_isfsr_4[2:0]}, 
         | {pipe_isfsr_3[2:0], m_isfsr_3[2:0]}, 
         | {pipe_isfsr_2[2:0], m_isfsr_2[2:0]}, 
         | {pipe_isfsr_1[2:0], m_isfsr_1[2:0]}, 
	 | {pipe_isfsr_0[2:0], m_isfsr_0[2:0]} };


tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_7_lat  ( 
	.scan_in(isfsr_7_lat_wmr_scanin),
	.scan_out(isfsr_7_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(isfsr_7_in		[2:0]	),
	.dout	(isfsr_7		[2:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_6_lat  ( 
	.scan_in(isfsr_6_lat_wmr_scanin),
	.scan_out(isfsr_6_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(isfsr_6_in		[2:0]	),
	.dout	(isfsr_6		[2:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_5_lat  ( 
	.scan_in(isfsr_5_lat_wmr_scanin),
	.scan_out(isfsr_5_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(isfsr_5_in		[2:0]	),
	.dout	(isfsr_5		[2:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_4_lat  ( 
	.scan_in(isfsr_4_lat_wmr_scanin),
	.scan_out(isfsr_4_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(isfsr_4_in		[2:0]	),
	.dout	(isfsr_4		[2:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_3_lat  ( 
	.scan_in(isfsr_3_lat_wmr_scanin),
	.scan_out(isfsr_3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(isfsr_3_in		[2:0]	),
	.dout	(isfsr_3		[2:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_2_lat  ( 
	.scan_in(isfsr_2_lat_wmr_scanin),
	.scan_out(isfsr_2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(isfsr_2_in		[2:0]	),
	.dout	(isfsr_2		[2:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_1_lat  ( 
	.scan_in(isfsr_1_lat_wmr_scanin),
	.scan_out(isfsr_1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(isfsr_1_in		[2:0]	),
	.dout	(isfsr_1		[2:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 isfsr_0_lat  ( 
	.scan_in(isfsr_0_lat_wmr_scanin),
	.scan_out(isfsr_0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(isfsr_0_in		[2:0]	),
	.dout	(isfsr_0		[2:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);


//////////////////////////////////////////////////////////////////////////////
//
//  Instantiate DSFSRs
//

assign dsfsr_7_new_in[3:0] = 
       {1'b0, pipe_dsfsr_7[2:0]} | {1'b0, m_dsfsr_7[2:0]} | 
       a_dsfsr_7[3:0] | t_dsfsr_7[3:0] | {{1 {1'b0}}, l_dsfsr_7[2:0]} | 
       {1'b0, s_dsfsr_7[2:0]} ;
assign dsfsr_6_new_in[3:0] = 
       {1'b0, pipe_dsfsr_6[2:0]} | {1'b0, m_dsfsr_6[2:0]} | 
       a_dsfsr_6[3:0] | t_dsfsr_6[3:0] | {{1 {1'b0}}, l_dsfsr_6[2:0]} | 
       {1'b0, s_dsfsr_6[2:0]} ;
assign dsfsr_5_new_in[3:0] = 
       {1'b0, pipe_dsfsr_5[2:0]} | {1'b0, m_dsfsr_5[2:0]} | 
       a_dsfsr_5[3:0] | t_dsfsr_5[3:0] | {{1 {1'b0}}, l_dsfsr_5[2:0]} | 
       {1'b0, s_dsfsr_5[2:0]} ;
assign dsfsr_4_new_in[3:0] = 
       {1'b0, pipe_dsfsr_4[2:0]} | {1'b0, m_dsfsr_4[2:0]} | 
       a_dsfsr_4[3:0] | t_dsfsr_4[3:0] | {{1 {1'b0}}, l_dsfsr_4[2:0]} | 
       {1'b0, s_dsfsr_4[2:0]} ;
assign dsfsr_3_new_in[3:0] = 
       {1'b0, pipe_dsfsr_3[2:0]} | {1'b0, m_dsfsr_3[2:0]} | 
       a_dsfsr_3[3:0] | t_dsfsr_3[3:0] | {{1 {1'b0}}, l_dsfsr_3[2:0]} | 
       {1'b0, s_dsfsr_3[2:0]} ;
assign dsfsr_2_new_in[3:0] = 
       {1'b0, pipe_dsfsr_2[2:0]} | {1'b0, m_dsfsr_2[2:0]} | 
       a_dsfsr_2[3:0] | t_dsfsr_2[3:0] | {{1 {1'b0}}, l_dsfsr_2[2:0]} | 
       {1'b0, s_dsfsr_2[2:0]} ;
assign dsfsr_1_new_in[3:0] = 
       {1'b0, pipe_dsfsr_1[2:0]} | {1'b0, m_dsfsr_1[2:0]} | 
       a_dsfsr_1[3:0] | t_dsfsr_1[3:0] | {{1 {1'b0}}, l_dsfsr_1[2:0]} | 
       {1'b0, s_dsfsr_1[2:0]} ;
assign dsfsr_0_new_in[3:0] = 
       {1'b0, pipe_dsfsr_0[2:0]} | {1'b0, m_dsfsr_0[2:0]} | 
       a_dsfsr_0[3:0] | t_dsfsr_0[3:0] | {{1 {1'b0}}, l_dsfsr_0[2:0]} | 
       {1'b0, s_dsfsr_0[2:0]} ;

assign dsfsr_7_in[3:0] =
       (dsfsr_7_new_in[3:0] & {4 {~asi_wr_dsfsr[7]}}) |
       (dsfsr_7[3:0] & ~{4 {| {asi_wr_dsfsr[7], dsfsr_7_new_in[3:0]}}}) |
       (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[7]}}) ;
assign dsfsr_6_in[3:0] =
       (dsfsr_6_new_in[3:0] & {4 {~asi_wr_dsfsr[6]}}) |
       (dsfsr_6[3:0] & ~{4 {| {asi_wr_dsfsr[6], dsfsr_6_new_in[3:0]}}}) |
       (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[6]}}) ;
assign dsfsr_5_in[3:0] =
       (dsfsr_5_new_in[3:0] & {4 {~asi_wr_dsfsr[5]}}) |
       (dsfsr_5[3:0] & ~{4 {| {asi_wr_dsfsr[5], dsfsr_5_new_in[3:0]}}}) |
       (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[5]}}) ;
assign dsfsr_4_in[3:0] =
       (dsfsr_4_new_in[3:0] & {4 {~asi_wr_dsfsr[4]}}) |
       (dsfsr_4[3:0] & ~{4 {| {asi_wr_dsfsr[4], dsfsr_4_new_in[3:0]}}}) |
       (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[4]}}) ;
assign dsfsr_3_in[3:0] =
       (dsfsr_3_new_in[3:0] & {4 {~asi_wr_dsfsr[3]}}) |
       (dsfsr_3[3:0] & ~{4 {| {asi_wr_dsfsr[3], dsfsr_3_new_in[3:0]}}}) |
       (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[3]}}) ;
assign dsfsr_2_in[3:0] =
       (dsfsr_2_new_in[3:0] & {4 {~asi_wr_dsfsr[2]}}) |
       (dsfsr_2[3:0] & ~{4 {| {asi_wr_dsfsr[2], dsfsr_2_new_in[3:0]}}}) |
       (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[2]}}) ;
assign dsfsr_1_in[3:0] =
       (dsfsr_1_new_in[3:0] & {4 {~asi_wr_dsfsr[1]}}) |
       (dsfsr_1[3:0] & ~{4 {| {asi_wr_dsfsr[1], dsfsr_1_new_in[3:0]}}}) |
       (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[1]}}) ;
assign dsfsr_0_in[3:0] =
       (dsfsr_0_new_in[3:0] & {4 {~asi_wr_dsfsr[0]}}) |
       (dsfsr_0[3:0] & ~{4 {| {asi_wr_dsfsr[0], dsfsr_0_new_in[3:0]}}}) |
       (asi_wr_data[3:0] & {4 { asi_wr_dsfsr[0]}}) ;

assign precise_d_error[7:0] = 
       { | {pipe_dsfsr_7[2:0], m_dsfsr_7[2:0], a_dsfsr_7[3:0],
	    t_dsfsr_7[3:0], l_dsfsr_7[2:0], s_dsfsr_7[2:0]},
         | {pipe_dsfsr_6[2:0], m_dsfsr_6[2:0], a_dsfsr_6[3:0],
	    t_dsfsr_6[3:0], l_dsfsr_6[2:0], s_dsfsr_6[2:0]},
         | {pipe_dsfsr_5[2:0], m_dsfsr_5[2:0], a_dsfsr_5[3:0],
	    t_dsfsr_5[3:0], l_dsfsr_5[2:0], s_dsfsr_5[2:0]},
         | {pipe_dsfsr_4[2:0], m_dsfsr_4[2:0], a_dsfsr_4[3:0],
	    t_dsfsr_4[3:0], l_dsfsr_4[2:0], s_dsfsr_4[2:0]},
         | {pipe_dsfsr_3[2:0], m_dsfsr_3[2:0], a_dsfsr_3[3:0],
	    t_dsfsr_3[3:0], l_dsfsr_3[2:0], s_dsfsr_3[2:0]},
         | {pipe_dsfsr_2[2:0], m_dsfsr_2[2:0], a_dsfsr_2[3:0],
	    t_dsfsr_2[3:0], l_dsfsr_2[2:0], s_dsfsr_2[2:0]},
         | {pipe_dsfsr_1[2:0], m_dsfsr_1[2:0], a_dsfsr_1[3:0],
	    t_dsfsr_1[3:0], l_dsfsr_1[2:0], s_dsfsr_1[2:0]},
         | {pipe_dsfsr_0[2:0], m_dsfsr_0[2:0], a_dsfsr_0[3:0],
	    t_dsfsr_0[3:0], l_dsfsr_0[2:0], s_dsfsr_0[2:0]}};

tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_7_lat  ( 
	.scan_in(dsfsr_7_lat_wmr_scanin),
	.scan_out(dsfsr_7_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(dsfsr_7_in		[3:0]	),
	.dout	(dsfsr_7		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_6_lat  ( 
	.scan_in(dsfsr_6_lat_wmr_scanin),
	.scan_out(dsfsr_6_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(dsfsr_6_in		[3:0]	),
	.dout	(dsfsr_6		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_5_lat  ( 
	.scan_in(dsfsr_5_lat_wmr_scanin),
	.scan_out(dsfsr_5_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(dsfsr_5_in		[3:0]	),
	.dout	(dsfsr_5		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_4_lat  ( 
	.scan_in(dsfsr_4_lat_wmr_scanin),
	.scan_out(dsfsr_4_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(dsfsr_4_in		[3:0]	),
	.dout	(dsfsr_4		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_3_lat  ( 
	.scan_in(dsfsr_3_lat_wmr_scanin),
	.scan_out(dsfsr_3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(dsfsr_3_in		[3:0]	),
	.dout	(dsfsr_3		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_2_lat  ( 
	.scan_in(dsfsr_2_lat_wmr_scanin),
	.scan_out(dsfsr_2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(dsfsr_2_in		[3:0]	),
	.dout	(dsfsr_2		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_1_lat  ( 
	.scan_in(dsfsr_1_lat_wmr_scanin),
	.scan_out(dsfsr_1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(dsfsr_1_in		[3:0]	),
	.dout	(dsfsr_1		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_4 dsfsr_0_lat  ( 
	.scan_in(dsfsr_0_lat_wmr_scanin),
	.scan_out(dsfsr_0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(dsfsr_0_in		[3:0]	),
	.dout	(dsfsr_0		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);


//////////////////////////////////////////////////////////////////////////////
//
//  ASI reads
//

tlu_ras_ctl_msff_ctl_macro__width_8 asi_rd_ctl_lat  (
	.scan_in(asi_rd_ctl_lat_scanin),
	.scan_out(asi_rd_ctl_lat_scanout),
	.din	({asi_rd_isfsr		       ,
		  asi_rd_dsfsr		       ,
		  asi_rd_dsfar		       ,
		  asi_rd_desr		       ,
		  asi_rd_fesr		       ,
		  asi_rd_tid		[2:0]}),
	.dout	({rd_isfsr		       ,
		  rd_dsfsr		       ,
		  rd_dsfar		       ,
		  rd_desr		       ,
		  rd_fesr		       ,
		  rd_tid		[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign rd_tid_dec[7:0] = 
       { rd_tid[2] &  rd_tid[1] &  rd_tid[0],
         rd_tid[2] &  rd_tid[1] & ~rd_tid[0],
         rd_tid[2] & ~rd_tid[1] &  rd_tid[0],
         rd_tid[2] & ~rd_tid[1] & ~rd_tid[0],
        ~rd_tid[2] &  rd_tid[1] &  rd_tid[0],
        ~rd_tid[2] &  rd_tid[1] & ~rd_tid[0],
        ~rd_tid[2] & ~rd_tid[1] &  rd_tid[0],
        ~rd_tid[2] & ~rd_tid[1] & ~rd_tid[0]}; 

assign rd_isfsr_dec[7:0] =
       {8 {rd_isfsr}} & rd_tid_dec[7:0];

assign rd_dsfsr_dec[7:0] =
       {8 {rd_dsfsr}} & rd_tid_dec[7:0];

assign rd_desr_dec[7:0] =
       {8 {rd_desr}} & rd_tid_dec[7:0];

assign ras_rd_dsfar[7:0] =
       {8 {rd_dsfar}} & rd_tid_dec[7:0];

assign ras_rd_desr[7:0] =
       {8 {rd_desr}} & rd_tid_dec[7:0];

assign ras_rd_fesr[7:0] =
       {8 {rd_fesr}} & rd_tid_dec[7:0];

assign ras_asi_data[3:0] =
       ({1'b0, isfsr_7[2:0]} & {4 {rd_isfsr_dec[7]}}) |
       ({1'b0, isfsr_6[2:0]} & {4 {rd_isfsr_dec[6]}}) |
       ({1'b0, isfsr_5[2:0]} & {4 {rd_isfsr_dec[5]}}) |
       ({1'b0, isfsr_4[2:0]} & {4 {rd_isfsr_dec[4]}}) |
       ({1'b0, isfsr_3[2:0]} & {4 {rd_isfsr_dec[3]}}) |
       ({1'b0, isfsr_2[2:0]} & {4 {rd_isfsr_dec[2]}}) |
       ({1'b0, isfsr_1[2:0]} & {4 {rd_isfsr_dec[1]}}) |
       ({1'b0, isfsr_0[2:0]} & {4 {rd_isfsr_dec[0]}}) |
       (       dsfsr_7[3:0]  & {4 {rd_dsfsr_dec[7]}}) |
       (       dsfsr_6[3:0]  & {4 {rd_dsfsr_dec[6]}}) |
       (       dsfsr_5[3:0]  & {4 {rd_dsfsr_dec[5]}}) |
       (       dsfsr_4[3:0]  & {4 {rd_dsfsr_dec[4]}}) |
       (       dsfsr_3[3:0]  & {4 {rd_dsfsr_dec[3]}}) |
       (       dsfsr_2[3:0]  & {4 {rd_dsfsr_dec[2]}}) |
       (       dsfsr_1[3:0]  & {4 {rd_dsfsr_dec[1]}}) |
       (       dsfsr_0[3:0]  & {4 {rd_dsfsr_dec[0]}}) ;


//////////////////////////////////////////////////////////////////////////////
//
//  Prepare DSFAR data
//

assign ras_dsfar_7[19:0] =
       pipe_dsfar_7[19:0] |
       {{17 {1'b0}}, m_dsfar_7[2:0]} |
       {{ 9 {1'b0}}, a_dsfar_7[10:0]} | 
       {{11 {1'b0}}, l_dsfar_7[8:0]} | 
       {{17 {1'b0}}, s_dsfar_7[2:0]} ;
assign ras_dsfar_6[19:0] =
       pipe_dsfar_6[19:0] |
       {{17 {1'b0}}, m_dsfar_6[2:0]} |
       {{ 9 {1'b0}}, a_dsfar_6[10:0]} | 
       {{11 {1'b0}}, l_dsfar_6[8:0]} | 
       {{17 {1'b0}}, s_dsfar_6[2:0]} ;
assign ras_dsfar_5[19:0] =
       pipe_dsfar_5[19:0] |
       {{17 {1'b0}}, m_dsfar_5[2:0]} |
       {{ 9 {1'b0}}, a_dsfar_5[10:0]} | 
       {{11 {1'b0}}, l_dsfar_5[8:0]} | 
       {{17 {1'b0}}, s_dsfar_5[2:0]} ;
assign ras_dsfar_4[19:0] =
       pipe_dsfar_4[19:0] |
       {{17 {1'b0}}, m_dsfar_4[2:0]} |
       {{ 9 {1'b0}}, a_dsfar_4[10:0]} | 
       {{11 {1'b0}}, l_dsfar_4[8:0]} | 
       {{17 {1'b0}}, s_dsfar_4[2:0]} ;
assign ras_dsfar_3[19:0] =
       pipe_dsfar_3[19:0] |
       {{17 {1'b0}}, m_dsfar_3[2:0]} |
       {{ 9 {1'b0}}, a_dsfar_3[10:0]} | 
       {{11 {1'b0}}, l_dsfar_3[8:0]} | 
       {{17 {1'b0}}, s_dsfar_3[2:0]} ;
assign ras_dsfar_2[19:0] =
       pipe_dsfar_2[19:0] |
       {{17 {1'b0}}, m_dsfar_2[2:0]} |
       {{ 9 {1'b0}}, a_dsfar_2[10:0]} | 
       {{11 {1'b0}}, l_dsfar_2[8:0]} | 
       {{17 {1'b0}}, s_dsfar_2[2:0]} ;
assign ras_dsfar_1[19:0] =
       pipe_dsfar_1[19:0] |
       {{17 {1'b0}}, m_dsfar_1[2:0]} |
       {{ 9 {1'b0}}, a_dsfar_1[10:0]} | 
       {{11 {1'b0}}, l_dsfar_1[8:0]} | 
       {{17 {1'b0}}, s_dsfar_1[2:0]} ;
assign ras_dsfar_0[19:0] =
       pipe_dsfar_0[19:0] |
       {{17 {1'b0}}, m_dsfar_0[2:0]} |
       {{ 9 {1'b0}}, a_dsfar_0[10:0]} | 
       {{11 {1'b0}}, l_dsfar_0[8:0]} | 
       {{17 {1'b0}}, s_dsfar_0[2:0]} ;

assign ras_dsfar_sel_ras[7:0] =
       {| {dsfsr_7_new_in[3:0], itmu_7, dtmu_7}, 
	| {dsfsr_6_new_in[3:0], itmu_6, dtmu_6},
        | {dsfsr_5_new_in[3:0], itmu_5, dtmu_5}, 
	| {dsfsr_4_new_in[3:0], itmu_4, dtmu_4},
        | {dsfsr_3_new_in[3:0], itmu_3, dtmu_3}, 
	| {dsfsr_2_new_in[3:0], itmu_2, dtmu_2},
        | {dsfsr_1_new_in[3:0], itmu_1, dtmu_1}, 
	| {dsfsr_0_new_in[3:0], itmu_0, dtmu_0}} &
       ~dsfar_sel_lsu_va_for_error[7:0];

       
//////////////////////////////////////////////////////////////////////////////
//
//  Handle disrupting errors
//

// Data cache errors -- long latency and implemented as precise but
//  technically disrupting
//
// DESR
// dcvp		0101
// dctp		0110
// dctm		0111
// dcdp		1000
// All these have S = 0

tlu_ras_ctl_msff_ctl_macro__width_1 dcvp_lat  (
	.scan_in(dcvp_lat_scanin),
	.scan_out(dcvp_lat_scanout),
	.din	(lsu_dcvp_err_g			),
	.dout	(dcvp				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 dctp_lat  (
	.scan_in(dctp_lat_scanin),
	.scan_out(dctp_lat_scanout),
	.din	(lsu_dctp_err_g			),
	.dout	(dctp				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 dctm_lat  (
	.scan_in(dctm_lat_scanin),
	.scan_out(dctm_lat_scanout),
	.din	(lsu_dcmh_err_g			),
	.dout	(dctm				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 dcdp_lat  (
	.scan_in(dcdp_lat_scanin),
	.scan_out(dcdp_lat_scanout),
	.din	(lsu_dcdp_err_g			),
	.dout	(dcdp				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign d_dec_tid[7:0] =
       { l_tid[2] &  l_tid[1] &  l_tid[0],
         l_tid[2] &  l_tid[1] & ~l_tid[0],
         l_tid[2] & ~l_tid[1] &  l_tid[0],
         l_tid[2] & ~l_tid[1] & ~l_tid[0],
        ~l_tid[2] &  l_tid[1] &  l_tid[0],
        ~l_tid[2] &  l_tid[1] & ~l_tid[0],
        ~l_tid[2] & ~l_tid[1] &  l_tid[0],
        ~l_tid[2] & ~l_tid[1] & ~l_tid[0]} & {8 {dcvp | dctp | dctm | dcdp}};

assign d_desr_et[3:0] =
       ({4 {dcvp}} & 4'b0101) |
       ({4 {dctp}} & 4'b0110) |
       ({4 {dctm}} & 4'b0111) |
       ({4 {dcdp}} & 4'b1000) ;

assign d_desr_et_7[3:0] =
       d_desr_et[3:0] & {4 {d_dec_tid[7]}};
assign d_desr_et_6[3:0] =
       d_desr_et[3:0] & {4 {d_dec_tid[6]}};
assign d_desr_et_5[3:0] =
       d_desr_et[3:0] & {4 {d_dec_tid[5]}};
assign d_desr_et_4[3:0] =
       d_desr_et[3:0] & {4 {d_dec_tid[4]}};
assign d_desr_et_3[3:0] =
       d_desr_et[3:0] & {4 {d_dec_tid[3]}};
assign d_desr_et_2[3:0] =
       d_desr_et[3:0] & {4 {d_dec_tid[2]}};
assign d_desr_et_1[3:0] =
       d_desr_et[3:0] & {4 {d_dec_tid[1]}};
assign d_desr_et_0[3:0] =
       d_desr_et[3:0] & {4 {d_dec_tid[0]}};

assign d_desr_ea_7[8:0] =
       l_dsfar[8:0] & {9 {d_dec_tid[7]}};
assign d_desr_ea_6[8:0] =
       l_dsfar[8:0] & {9 {d_dec_tid[6]}};
assign d_desr_ea_5[8:0] =
       l_dsfar[8:0] & {9 {d_dec_tid[5]}};
assign d_desr_ea_4[8:0] =
       l_dsfar[8:0] & {9 {d_dec_tid[4]}};
assign d_desr_ea_3[8:0] =
       l_dsfar[8:0] & {9 {d_dec_tid[3]}};
assign d_desr_ea_2[8:0] =
       l_dsfar[8:0] & {9 {d_dec_tid[2]}};
assign d_desr_ea_1[8:0] =
       l_dsfar[8:0] & {9 {d_dec_tid[1]}};
assign d_desr_ea_0[8:0] =
       l_dsfar[8:0] & {9 {d_dec_tid[0]}};


//  L2 and SOC errors
//
// DESR
// l2ch		01001
// l2u		10000
// l2nd		10001
// soc		01011
// sou		10011
// l2cs		10100
// l2ch and soc has S = 0, others have S = 1

tlu_ras_ctl_msff_ctl_macro__width_8 cxi_lat  (
	.scan_in(cxi_lat_scanin),
	.scan_out(cxi_lat_scanout),
	.din	({cxi_l2_err		       ,
		  cxi_soc_err		       ,
		  cxi_l2_soc_err_type	[1:0],
		  cxi_l2_soc_tid	[2:0],
		  cxi_l2_soc_sre	       }),
	.dout	({l2_err		       ,
		  soc_err		       ,
		  c_l2_soc_err_type	[1:0],
		  c_l2_soc_tid		[2:0],
		  c_l2_soc_sre	       	       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign c_l2_soc_dec_tid[7:0] =
       { c_l2_soc_tid[2] &  c_l2_soc_tid[1] &  c_l2_soc_tid[0],
         c_l2_soc_tid[2] &  c_l2_soc_tid[1] & ~c_l2_soc_tid[0],
         c_l2_soc_tid[2] & ~c_l2_soc_tid[1] &  c_l2_soc_tid[0],
         c_l2_soc_tid[2] & ~c_l2_soc_tid[1] & ~c_l2_soc_tid[0],
        ~c_l2_soc_tid[2] &  c_l2_soc_tid[1] &  c_l2_soc_tid[0],
        ~c_l2_soc_tid[2] &  c_l2_soc_tid[1] & ~c_l2_soc_tid[0],
        ~c_l2_soc_tid[2] & ~c_l2_soc_tid[1] &  c_l2_soc_tid[0],
        ~c_l2_soc_tid[2] & ~c_l2_soc_tid[1] & ~c_l2_soc_tid[0]};

assign c_l2_err[7:0] =
       {8 {l2_err}} & c_l2_soc_dec_tid[7:0];
	
assign c_soc_err[7:0] =
       {8 {soc_err}} & c_l2_soc_dec_tid[7:0];
	
assign l2_dec_tid[7:0] =
       c_l2_err[7:0] | c_soc_err[7:0];

assign l2ch =
       (c_l2_soc_err_type[1:0] == 2'b01) & l2_err & ~c_l2_soc_sre;
assign l2cs =
       (c_l2_soc_err_type[1:0] == 2'b01) & l2_err &  c_l2_soc_sre;
assign soc =
       (c_l2_soc_err_type[1:0] == 2'b01) & soc_err;
assign l2u =
       (c_l2_soc_err_type[1:0] == 2'b10) & l2_err;
assign sou =
       (c_l2_soc_err_type[1:0] == 2'b10) & soc_err;
assign l2nd =
       (c_l2_soc_err_type[1:0] == 2'b11) & l2_err;

assign l2_desr_et[5:0] =
       ({6 {l2ch}} & 6'b001001) |
       ({6 {l2u }} & 6'b110000) |
       ({6 {l2nd}} & 6'b110001) |
       ({6 {soc }} & 6'b001011) |
       ({6 {sou }} & 6'b110011) |
       ({6 {l2cs}} & 6'b110100) ;

assign l2_desr_et_7[5:0] =
       l2_desr_et[5:0] & {6 {l2_dec_tid[7]}};
assign l2_desr_et_6[5:0] =
       l2_desr_et[5:0] & {6 {l2_dec_tid[6]}};
assign l2_desr_et_5[5:0] =
       l2_desr_et[5:0] & {6 {l2_dec_tid[5]}};
assign l2_desr_et_4[5:0] =
       l2_desr_et[5:0] & {6 {l2_dec_tid[4]}};
assign l2_desr_et_3[5:0] =
       l2_desr_et[5:0] & {6 {l2_dec_tid[3]}};
assign l2_desr_et_2[5:0] =
       l2_desr_et[5:0] & {6 {l2_dec_tid[2]}};
assign l2_desr_et_1[5:0] =
       l2_desr_et[5:0] & {6 {l2_dec_tid[1]}};
assign l2_desr_et_0[5:0] =
       l2_desr_et[5:0] & {6 {l2_dec_tid[0]}};

// No data stored in DESR.EA for L2 or SOC errors


// Store buffer errors
//
// DESR
// sbdpc	01010
// sbdpu	00110
// sbdpu has S = 1

tlu_ras_ctl_msff_ctl_macro__width_1 sbdpc_lat  (
	.scan_in(sbdpc_lat_scanin),
	.scan_out(sbdpc_lat_scanout),
	.din	(lsu_sbdpc_err_g		),
	.dout	(sbdpc				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 sbdpu_lat  (
	.scan_in(sbdpu_lat_scanin),
	.scan_out(sbdpu_lat_scanout),
	.din	(lsu_sbdpu_err_g		),
	.dout	(sbdpu				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign sb_dec_tid[7:0] =
       {s_tid[2:0] == 3'b111,
	s_tid[2:0] == 3'b110,
	s_tid[2:0] == 3'b101,
	s_tid[2:0] == 3'b100,
	s_tid[2:0] == 3'b011,
	s_tid[2:0] == 3'b010,
	s_tid[2:0] == 3'b001,
	s_tid[2:0] == 3'b000} & {8 {sbdpc | sbdpu}};

assign s_desr_et[5:0] =
       {sbdpu, 1'b0, sbdpc, sbdpu, sbdpu | sbdpc, 1'b0};

assign s_desr_et_7[5:0] =
       s_desr_et[5:0] & {6 {sb_dec_tid[7]}};
assign s_desr_et_6[5:0] =
       s_desr_et[5:0] & {6 {sb_dec_tid[6]}};
assign s_desr_et_5[5:0] =
       s_desr_et[5:0] & {6 {sb_dec_tid[5]}};
assign s_desr_et_4[5:0] =
       s_desr_et[5:0] & {6 {sb_dec_tid[4]}};
assign s_desr_et_3[5:0] =
       s_desr_et[5:0] & {6 {sb_dec_tid[3]}};
assign s_desr_et_2[5:0] =
       s_desr_et[5:0] & {6 {sb_dec_tid[2]}};
assign s_desr_et_1[5:0] =
       s_desr_et[5:0] & {6 {sb_dec_tid[1]}};
assign s_desr_et_0[5:0] =
       s_desr_et[5:0] & {6 {sb_dec_tid[0]}};

assign s_desr_ea_7[2:0] = 
       s_dsfar[2:0] & {3 {sb_dec_tid[7]}};
assign s_desr_ea_6[2:0] = 
       s_dsfar[2:0] & {3 {sb_dec_tid[6]}};
assign s_desr_ea_5[2:0] = 
       s_dsfar[2:0] & {3 {sb_dec_tid[5]}};
assign s_desr_ea_4[2:0] = 
       s_dsfar[2:0] & {3 {sb_dec_tid[4]}};
assign s_desr_ea_3[2:0] = 
       s_dsfar[2:0] & {3 {sb_dec_tid[3]}};
assign s_desr_ea_2[2:0] = 
       s_dsfar[2:0] & {3 {sb_dec_tid[2]}};
assign s_desr_ea_1[2:0] = 
       s_dsfar[2:0] & {3 {sb_dec_tid[1]}};
assign s_desr_ea_0[2:0] = 
       s_dsfar[2:0] & {3 {sb_dec_tid[0]}};


// SPU errors
//
// DESR
// mamu		00111
// mal2c	01000
// mal2u	01001
// mal2nd	01010
// cwql2c	01011
// cwql2u	01100
// cwql2nd	01101
// All have S = 1

// 10 -  ma_copy; 9:8 - syndrome; 7:0 - MA index
tlu_ras_ctl_msff_ctl_macro__width_12 mamu_err_lat  (
	.scan_in(mamu_err_lat_scanin),
	.scan_out(mamu_err_lat_scanout),
	.din	({spu_tlu_mamu_err_req_v       ,
 		  spu_tlu_mamu_err_req	[10:0]}),
	.dout	({mamu_err_v		       ,
		  mamu_err		[10:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign mamu_dec_tid[7:0] =
       ma_dec_tid[7:0] & {8 {mamu_err_v}};

assign mamu_desr_et[5:0] =
       6'b100111;

assign mamu_desr_et_7[5:0] =
       mamu_desr_et[5:0] & {6 {mamu_dec_tid[7]}};
assign mamu_desr_et_6[5:0] =
       mamu_desr_et[5:0] & {6 {mamu_dec_tid[6]}};
assign mamu_desr_et_5[5:0] =
       mamu_desr_et[5:0] & {6 {mamu_dec_tid[5]}};
assign mamu_desr_et_4[5:0] =
       mamu_desr_et[5:0] & {6 {mamu_dec_tid[4]}};
assign mamu_desr_et_3[5:0] =
       mamu_desr_et[5:0] & {6 {mamu_dec_tid[3]}};
assign mamu_desr_et_2[5:0] =
       mamu_desr_et[5:0] & {6 {mamu_dec_tid[2]}};
assign mamu_desr_et_1[5:0] =
       mamu_desr_et[5:0] & {6 {mamu_dec_tid[1]}};
assign mamu_desr_et_0[5:0] =
       mamu_desr_et[5:0] & {6 {mamu_dec_tid[0]}};

assign mamu_desr_ea_7[10:0] =
       mamu_err[10:0] & {11 {mamu_dec_tid[7]}};
assign mamu_desr_ea_6[10:0] =
       mamu_err[10:0] & {11 {mamu_dec_tid[6]}};
assign mamu_desr_ea_5[10:0] =
       mamu_err[10:0] & {11 {mamu_dec_tid[5]}};
assign mamu_desr_ea_4[10:0] =
       mamu_err[10:0] & {11 {mamu_dec_tid[4]}};
assign mamu_desr_ea_3[10:0] =
       mamu_err[10:0] & {11 {mamu_dec_tid[3]}};
assign mamu_desr_ea_2[10:0] =
       mamu_err[10:0] & {11 {mamu_dec_tid[2]}};
assign mamu_desr_ea_1[10:0] =
       mamu_err[10:0] & {11 {mamu_dec_tid[1]}};
assign mamu_desr_ea_0[10:0] =
       mamu_err[10:0] & {11 {mamu_dec_tid[0]}};

tlu_ras_ctl_msff_ctl_macro__width_3 ma_tid_lat  (
	.scan_in(ma_tid_lat_scanin),
	.scan_out(ma_tid_lat_scanout),
	.din	(spu_tlu_ma_int_req	[2:0]	),
	.dout	(ma_tid			[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_3 cwq_tid_lat  (
	.scan_in(cwq_tid_lat_scanin),
	.scan_out(cwq_tid_lat_scanout),
	.din	(spu_tlu_cwq_int_req	[2:0]	),
	.dout	(cwq_tid		[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_6 spu_error_lat  (
	.scan_in(spu_error_lat_scanin),
	.scan_out(spu_error_lat_scanout),
	.din	(spu_tlu_l2_error	[5:0]	),
	.dout	(spu_error		[5:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ma_dec_tid[7:0] =
       {ma_tid[2:0] == 3'b111,
        ma_tid[2:0] == 3'b110,
        ma_tid[2:0] == 3'b101,
        ma_tid[2:0] == 3'b100,
        ma_tid[2:0] == 3'b011,
        ma_tid[2:0] == 3'b010,
        ma_tid[2:0] == 3'b001,
        ma_tid[2:0] == 3'b000};

assign cwq_dec_tid[7:0] =
       {cwq_tid[2:0] == 3'b111,
        cwq_tid[2:0] == 3'b110,
        cwq_tid[2:0] == 3'b101,
        cwq_tid[2:0] == 3'b100,
        cwq_tid[2:0] == 3'b011,
        cwq_tid[2:0] == 3'b010,
        cwq_tid[2:0] == 3'b001,
        cwq_tid[2:0] == 3'b000};

assign mal2c =
       spu_error[5];
assign mal2u =
       spu_error[4];
assign mal2nd =
       spu_error[3];
assign cwql2c =
       spu_error[2];
assign cwql2u =
       spu_error[1];
assign cwql2nd =
       spu_error[0];

assign ma_desr_et[5:0] =
       ({6 {mal2c  }} & 6'b101000) | 
       ({6 {mal2u  }} & 6'b101001) | 
       ({6 {mal2nd }} & 6'b101010) ;

assign cwq_desr_et[5:0] =
       ({6 {cwql2c }} & 6'b101011) | 
       ({6 {cwql2u }} & 6'b101100) | 
       ({6 {cwql2nd}} & 6'b101101) ;

assign ma_desr_et_7[5:0] =
       ma_desr_et[5:0] & {6 {ma_dec_tid[7]}};
assign ma_desr_et_6[5:0] =
       ma_desr_et[5:0] & {6 {ma_dec_tid[6]}};
assign ma_desr_et_5[5:0] =
       ma_desr_et[5:0] & {6 {ma_dec_tid[5]}};
assign ma_desr_et_4[5:0] =
       ma_desr_et[5:0] & {6 {ma_dec_tid[4]}};
assign ma_desr_et_3[5:0] =
       ma_desr_et[5:0] & {6 {ma_dec_tid[3]}};
assign ma_desr_et_2[5:0] =
       ma_desr_et[5:0] & {6 {ma_dec_tid[2]}};
assign ma_desr_et_1[5:0] =
       ma_desr_et[5:0] & {6 {ma_dec_tid[1]}};
assign ma_desr_et_0[5:0] =
       ma_desr_et[5:0] & {6 {ma_dec_tid[0]}};

assign cwq_desr_et_7[5:0] =
       cwq_desr_et[5:0] & {6 {cwq_dec_tid[7]}};
assign cwq_desr_et_6[5:0] =
       cwq_desr_et[5:0] & {6 {cwq_dec_tid[6]}};
assign cwq_desr_et_5[5:0] =
       cwq_desr_et[5:0] & {6 {cwq_dec_tid[5]}};
assign cwq_desr_et_4[5:0] =
       cwq_desr_et[5:0] & {6 {cwq_dec_tid[4]}};
assign cwq_desr_et_3[5:0] =
       cwq_desr_et[5:0] & {6 {cwq_dec_tid[3]}};
assign cwq_desr_et_2[5:0] =
       cwq_desr_et[5:0] & {6 {cwq_dec_tid[2]}};
assign cwq_desr_et_1[5:0] =
       cwq_desr_et[5:0] & {6 {cwq_dec_tid[1]}};
assign cwq_desr_et_0[5:0] =
       cwq_desr_et[5:0] & {6 {cwq_dec_tid[0]}};

// ma and cwq are all L2 errors so no DESR.EA for them


// TCA errors
//
// DESR
// tccd		01110
// tcud		01111
// Both have S = 1

assign t_desr_et_7[5:0] =
       ({6 {tlu_tccd[7]}} & 6'b101110) | 
       ({6 {tlu_tcud[7]}} & 6'b101111) ;
assign t_desr_et_6[5:0] =
       ({6 {tlu_tccd[6]}} & 6'b101110) | 
       ({6 {tlu_tcud[6]}} & 6'b101111) ;
assign t_desr_et_5[5:0] =
       ({6 {tlu_tccd[5]}} & 6'b101110) | 
       ({6 {tlu_tcud[5]}} & 6'b101111) ;
assign t_desr_et_4[5:0] =
       ({6 {tlu_tccd[4]}} & 6'b101110) | 
       ({6 {tlu_tcud[4]}} & 6'b101111) ;
assign t_desr_et_3[5:0] =
       ({6 {tlu_tccd[3]}} & 6'b101110) | 
       ({6 {tlu_tcud[3]}} & 6'b101111) ;
assign t_desr_et_2[5:0] =
       ({6 {tlu_tccd[2]}} & 6'b101110) | 
       ({6 {tlu_tcud[2]}} & 6'b101111) ;
assign t_desr_et_1[5:0] =
       ({6 {tlu_tccd[1]}} & 6'b101110) | 
       ({6 {tlu_tcud[1]}} & 6'b101111) ;
assign t_desr_et_0[5:0] =
       ({6 {tlu_tccd[0]}} & 6'b101110) | 
       ({6 {tlu_tcud[0]}} & 6'b101111) ;

assign t_desr_ea_7[9:0] =
       {10 {tlu_tccd[7] | tlu_tcud[7]}} & 
       {cel_syndrome[7:0], tlu_tca_index_1[1:0]};
assign t_desr_ea_6[9:0] =
       {10 {tlu_tccd[6] | tlu_tcud[6]}} &
       {cel_syndrome[7:0], tlu_tca_index_1[1:0]};
assign t_desr_ea_5[9:0] =
       {10 {tlu_tccd[5] | tlu_tcud[5]}} &
       {cel_syndrome[7:0], tlu_tca_index_1[1:0]};
assign t_desr_ea_4[9:0] =
       {10 {tlu_tccd[4] | tlu_tcud[4]}} &
       {cel_syndrome[7:0], tlu_tca_index_1[1:0]};
assign t_desr_ea_3[9:0] =
       {10 {tlu_tccd[3] | tlu_tcud[3]}} &
       {cel_syndrome[7:0], tlu_tca_index_0[1:0]};
assign t_desr_ea_2[9:0] =
       {10 {tlu_tccd[2] | tlu_tcud[2]}} &
       {cel_syndrome[7:0], tlu_tca_index_0[1:0]};
assign t_desr_ea_1[9:0] =
       {10 {tlu_tccd[1] | tlu_tcud[1]}} &
       {cel_syndrome[7:0], tlu_tca_index_0[1:0]};
assign t_desr_ea_0[9:0] =
       {10 {tlu_tccd[0] | tlu_tcud[0]}} &
       {cel_syndrome[7:0], tlu_tca_index_0[1:0]};
		   

//
// DESRs
//

// Prioritize DESR exceptions
// S = 0, type 1-4, priority 11
// and S = 1, type 2, priority 6
assign pipe_desr_exc_7 = (| pipe_desr_et_7[5:0]);
assign pipe_desr_exc_6 = (| pipe_desr_et_6[5:0]);
assign pipe_desr_exc_5 = (| pipe_desr_et_5[5:0]);
assign pipe_desr_exc_4 = (| pipe_desr_et_4[5:0]);
assign pipe_desr_exc_3 = (| pipe_desr_et_3[5:0]);
assign pipe_desr_exc_2 = (| pipe_desr_et_2[5:0]);
assign pipe_desr_exc_1 = (| pipe_desr_et_1[5:0]);
assign pipe_desr_exc_0 = (| pipe_desr_et_0[5:0]);

// S = 1, type 1&3, priority 6
assign m_desr_exc_7 = m_desr_et_7[5];
assign m_desr_exc_6 = m_desr_et_6[5];
assign m_desr_exc_5 = m_desr_et_5[5];
assign m_desr_exc_4 = m_desr_et_4[5];
assign m_desr_exc_3 = m_desr_et_3[5];
assign m_desr_exc_2 = m_desr_et_2[5];
assign m_desr_exc_1 = m_desr_et_1[5];
assign m_desr_exc_0 = m_desr_et_0[5];

// S = 1, type 4, priority 6
// and S = 0, type 11, priority 15 (shared with l2)
assign l_desr_exc_7 = (| l_desr_et_7[5:0]);
assign l_desr_exc_6 = (| l_desr_et_6[5:0]);
assign l_desr_exc_5 = (| l_desr_et_5[5:0]);
assign l_desr_exc_4 = (| l_desr_et_4[5:0]);
assign l_desr_exc_3 = (| l_desr_et_3[5:0]);
assign l_desr_exc_2 = (| l_desr_et_2[5:0]);
assign l_desr_exc_1 = (| l_desr_et_1[5:0]);
assign l_desr_exc_0 = (| l_desr_et_0[5:0]);

// S = 0, type 5-8, priority 12
assign d_desr_exc_7 = (| d_desr_et_7[3:0]);
assign d_desr_exc_6 = (| d_desr_et_6[3:0]);
assign d_desr_exc_5 = (| d_desr_et_5[3:0]);
assign d_desr_exc_4 = (| d_desr_et_4[3:0]);
assign d_desr_exc_3 = (| d_desr_et_3[3:0]);
assign d_desr_exc_2 = (| d_desr_et_2[3:0]);
assign d_desr_exc_1 = (| d_desr_et_1[3:0]);
assign d_desr_exc_0 = (| d_desr_et_0[3:0]);

// S = 0, type 9, priority 13
// and S = 0, type 11, priority 15 (shared with l)
// and S = 1, type 16-17, priority 5
// and S = 1, type 18-19, priority 7
assign l2_desr_exc_7 = (| l2_desr_et_7[5:0]);
assign l2_desr_exc_6 = (| l2_desr_et_6[5:0]);
assign l2_desr_exc_5 = (| l2_desr_et_5[5:0]);
assign l2_desr_exc_4 = (| l2_desr_et_4[5:0]);
assign l2_desr_exc_3 = (| l2_desr_et_3[5:0]);
assign l2_desr_exc_2 = (| l2_desr_et_2[5:0]);
assign l2_desr_exc_1 = (| l2_desr_et_1[5:0]);
assign l2_desr_exc_0 = (| l2_desr_et_0[5:0]);

// S = 0, type 10, priority 14 
// and S = 1, type 6, priority 1
assign s_desr_exc_7 = (| s_desr_et_7[5:0]);
assign s_desr_exc_6 = (| s_desr_et_6[5:0]);
assign s_desr_exc_5 = (| s_desr_et_5[5:0]);
assign s_desr_exc_4 = (| s_desr_et_4[5:0]);
assign s_desr_exc_3 = (| s_desr_et_3[5:0]);
assign s_desr_exc_2 = (| s_desr_et_2[5:0]);
assign s_desr_exc_1 = (| s_desr_et_1[5:0]);
assign s_desr_exc_0 = (| s_desr_et_0[5:0]);

// S = 1, type 7, priority 3
assign mamu_desr_exc_7 = mamu_desr_et_7[5];
assign mamu_desr_exc_6 = mamu_desr_et_6[5];
assign mamu_desr_exc_5 = mamu_desr_et_5[5];
assign mamu_desr_exc_4 = mamu_desr_et_4[5];
assign mamu_desr_exc_3 = mamu_desr_et_3[5];
assign mamu_desr_exc_2 = mamu_desr_et_2[5];
assign mamu_desr_exc_1 = mamu_desr_et_1[5];
assign mamu_desr_exc_0 = mamu_desr_et_0[5];

// S = 1, type 8-10, priority 3
assign ma_desr_exc_7 = ma_desr_et_7[5];
assign ma_desr_exc_6 = ma_desr_et_6[5];
assign ma_desr_exc_5 = ma_desr_et_5[5];
assign ma_desr_exc_4 = ma_desr_et_4[5];
assign ma_desr_exc_3 = ma_desr_et_3[5];
assign ma_desr_exc_2 = ma_desr_et_2[5];
assign ma_desr_exc_1 = ma_desr_et_1[5];
assign ma_desr_exc_0 = ma_desr_et_0[5];

// S = 1, type 11-13, priority 4
assign cwq_desr_exc_7 = cwq_desr_et_7[5];
assign cwq_desr_exc_6 = cwq_desr_et_6[5];
assign cwq_desr_exc_5 = cwq_desr_et_5[5];
assign cwq_desr_exc_4 = cwq_desr_et_4[5];
assign cwq_desr_exc_3 = cwq_desr_et_3[5];
assign cwq_desr_exc_2 = cwq_desr_et_2[5];
assign cwq_desr_exc_1 = cwq_desr_et_1[5];
assign cwq_desr_exc_0 = cwq_desr_et_0[5];

// S = 1, type 14-15, priority 2
assign t_desr_exc_7 = t_desr_et_7[5];
assign t_desr_exc_6 = t_desr_et_6[5];
assign t_desr_exc_5 = t_desr_et_5[5];
assign t_desr_exc_4 = t_desr_et_4[5];
assign t_desr_exc_3 = t_desr_et_3[5];
assign t_desr_exc_2 = t_desr_et_2[5];
assign t_desr_exc_1 = t_desr_et_1[5];
assign t_desr_exc_0 = t_desr_et_0[5];

assign ras_desr_en[7] =
       pipe_desr_exc_7 | m_desr_exc_7 |    l_desr_exc_7 |  d_desr_exc_7 | 
         l2_desr_exc_7 | s_desr_exc_7 | mamu_desr_exc_7 | ma_desr_exc_7 |
        cwq_desr_exc_7 | t_desr_exc_7 | rd_desr_dec[7];
assign ras_desr_en[6] =
       pipe_desr_exc_6 | m_desr_exc_6 |    l_desr_exc_6 |  d_desr_exc_6 | 
         l2_desr_exc_6 | s_desr_exc_6 | mamu_desr_exc_6 | ma_desr_exc_6 |
        cwq_desr_exc_6 | t_desr_exc_6 | rd_desr_dec[6];
assign ras_desr_en[5] =
       pipe_desr_exc_5 | m_desr_exc_5 |    l_desr_exc_5 |  d_desr_exc_5 | 
         l2_desr_exc_5 | s_desr_exc_5 | mamu_desr_exc_5 | ma_desr_exc_5 |
        cwq_desr_exc_5 | t_desr_exc_5 | rd_desr_dec[5];
assign ras_desr_en[4] =
       pipe_desr_exc_4 | m_desr_exc_4 |    l_desr_exc_4 |  d_desr_exc_4 | 
         l2_desr_exc_4 | s_desr_exc_4 | mamu_desr_exc_4 | ma_desr_exc_4 |
        cwq_desr_exc_4 | t_desr_exc_4 | rd_desr_dec[4];
assign ras_desr_en[3] =
       pipe_desr_exc_3 | m_desr_exc_3 |    l_desr_exc_3 |  d_desr_exc_3 | 
         l2_desr_exc_3 | s_desr_exc_3 | mamu_desr_exc_3 | ma_desr_exc_3 |
        cwq_desr_exc_3 | t_desr_exc_3 | rd_desr_dec[3];
assign ras_desr_en[2] =
       pipe_desr_exc_2 | m_desr_exc_2 |    l_desr_exc_2 |  d_desr_exc_2 | 
         l2_desr_exc_2 | s_desr_exc_2 | mamu_desr_exc_2 | ma_desr_exc_2 |
        cwq_desr_exc_2 | t_desr_exc_2 | rd_desr_dec[2];
assign ras_desr_en[1] =
       pipe_desr_exc_1 | m_desr_exc_1 |    l_desr_exc_1 |  d_desr_exc_1 | 
         l2_desr_exc_1 | s_desr_exc_1 | mamu_desr_exc_1 | ma_desr_exc_1 |
        cwq_desr_exc_1 | t_desr_exc_1 | rd_desr_dec[1];
assign ras_desr_en[0] =
       pipe_desr_exc_0 | m_desr_exc_0 |    l_desr_exc_0 |  d_desr_exc_0 | 
         l2_desr_exc_0 | s_desr_exc_0 | mamu_desr_exc_0 | ma_desr_exc_0 |
        cwq_desr_exc_0 | t_desr_exc_0 | rd_desr_dec[0];
			
// Third term is to catch the case of simultaneous 
// SBDPC (type 10, priority 14) and SOCC (type 11, priority 15)
assign take_s_7 = 
       s_desr_et_7[5] | 
       (s_desr_exc_7 & ~l2_desr_exc_7     & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7) |
       (s_desr_exc_7 &   l2_desr_et_7[1] & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7) ;
assign take_s_6 = 
       s_desr_et_6[5] | 
       (s_desr_exc_6 & ~l2_desr_exc_6     & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6) |
       (s_desr_exc_6 &   l2_desr_et_6[1] & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6) ;
assign take_s_5 = 
       s_desr_et_5[5] | 
       (s_desr_exc_5 & ~l2_desr_exc_5     & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5) |
       (s_desr_exc_5 &   l2_desr_et_5[1] & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5) ;
assign take_s_4 = 
       s_desr_et_4[5] | 
       (s_desr_exc_4 & ~l2_desr_exc_4     & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4) |
       (s_desr_exc_4 &   l2_desr_et_4[1] & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4) ;
assign take_s_3 = 
       s_desr_et_3[5] | 
       (s_desr_exc_3 & ~l2_desr_exc_3     & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3) |
       (s_desr_exc_3 &   l2_desr_et_3[1] & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3) ;
assign take_s_2 = 
       s_desr_et_2[5] | 
       (s_desr_exc_2 & ~l2_desr_exc_2     & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2) |
       (s_desr_exc_2 &   l2_desr_et_2[1] & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2) ;
assign take_s_1 = 
       s_desr_et_1[5] | 
       (s_desr_exc_1 & ~l2_desr_exc_1     & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1) |
       (s_desr_exc_1 &   l2_desr_et_1[1] & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1) ;
assign take_s_0 = 
       s_desr_et_0[5] | 
       (s_desr_exc_0 & ~l2_desr_exc_0     & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0) |
       (s_desr_exc_0 &   l2_desr_et_0[1] & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0) ;

assign take_t_7 = t_desr_exc_7 & ~s_desr_et_7[5];
assign take_t_6 = t_desr_exc_6 & ~s_desr_et_6[5];
assign take_t_5 = t_desr_exc_5 & ~s_desr_et_5[5];
assign take_t_4 = t_desr_exc_4 & ~s_desr_et_4[5];
assign take_t_3 = t_desr_exc_3 & ~s_desr_et_3[5];
assign take_t_2 = t_desr_exc_2 & ~s_desr_et_2[5];
assign take_t_1 = t_desr_exc_1 & ~s_desr_et_1[5];
assign take_t_0 = t_desr_exc_0 & ~s_desr_et_0[5];

assign take_ma_7 = ma_desr_exc_7 & ~t_desr_et_7[5] & ~s_desr_et_7[5];
assign take_ma_6 = ma_desr_exc_6 & ~t_desr_et_6[5] & ~s_desr_et_6[5];
assign take_ma_5 = ma_desr_exc_5 & ~t_desr_et_5[5] & ~s_desr_et_5[5];
assign take_ma_4 = ma_desr_exc_4 & ~t_desr_et_4[5] & ~s_desr_et_4[5];
assign take_ma_3 = ma_desr_exc_3 & ~t_desr_et_3[5] & ~s_desr_et_3[5];
assign take_ma_2 = ma_desr_exc_2 & ~t_desr_et_2[5] & ~s_desr_et_2[5];
assign take_ma_1 = ma_desr_exc_1 & ~t_desr_et_1[5] & ~s_desr_et_1[5];
assign take_ma_0 = ma_desr_exc_0 & ~t_desr_et_0[5] & ~s_desr_et_0[5];

assign take_mamu_7 = mamu_desr_exc_7 & ~ma_desr_exc_7 & ~t_desr_et_7[5] & ~s_desr_et_7[5];
assign take_mamu_6 = mamu_desr_exc_6 & ~ma_desr_exc_6 & ~t_desr_et_6[5] & ~s_desr_et_6[5];
assign take_mamu_5 = mamu_desr_exc_5 & ~ma_desr_exc_5 & ~t_desr_et_5[5] & ~s_desr_et_5[5];
assign take_mamu_4 = mamu_desr_exc_4 & ~ma_desr_exc_4 & ~t_desr_et_4[5] & ~s_desr_et_4[5];
assign take_mamu_3 = mamu_desr_exc_3 & ~ma_desr_exc_3 & ~t_desr_et_3[5] & ~s_desr_et_3[5];
assign take_mamu_2 = mamu_desr_exc_2 & ~ma_desr_exc_2 & ~t_desr_et_2[5] & ~s_desr_et_2[5];
assign take_mamu_1 = mamu_desr_exc_1 & ~ma_desr_exc_1 & ~t_desr_et_1[5] & ~s_desr_et_1[5];
assign take_mamu_0 = mamu_desr_exc_0 & ~ma_desr_exc_0 & ~t_desr_et_0[5] & ~s_desr_et_0[5];

assign take_cwq_7 = cwq_desr_exc_7 & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5];
assign take_cwq_6 = cwq_desr_exc_6 & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5];
assign take_cwq_5 = cwq_desr_exc_5 & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5];
assign take_cwq_4 = cwq_desr_exc_4 & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5];
assign take_cwq_3 = cwq_desr_exc_3 & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5];
assign take_cwq_2 = cwq_desr_exc_2 & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5];
assign take_cwq_1 = cwq_desr_exc_1 & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5];
assign take_cwq_0 = cwq_desr_exc_0 & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5];

assign take_l2_7 = (l2_desr_et_7[5] & ~l2_desr_et_7[1] &                                                              ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | 
                   (l2_desr_et_7[5] &  l2_desr_et_7[1] & ~pipe_desr_et_7[5]  & ~m_desr_et_7[5] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) | 
		   (l2_desr_exc_7 & ~l2_desr_et_7[1] &                 ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7) |
		   (l2_desr_exc_7 &  l2_desr_et_7[1] & ~s_desr_exc_7 & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7) ;
assign take_l2_6 = (l2_desr_et_6[5] & ~l2_desr_et_6[1] &          							~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | 
                   (l2_desr_et_6[5] &  l2_desr_et_6[1] & ~pipe_desr_et_6[5]  & ~m_desr_et_6[5] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | 
		   (l2_desr_exc_6 & ~l2_desr_et_6[1] &                 ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6) |
		   (l2_desr_exc_6 &  l2_desr_et_6[1] & ~s_desr_exc_6 & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6) ;
assign take_l2_5 = (l2_desr_et_5[5] & ~l2_desr_et_5[1] &          							~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | 
                   (l2_desr_et_5[5] &  l2_desr_et_5[1] & ~pipe_desr_et_5[5]  & ~m_desr_et_5[5] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | 
		   (l2_desr_exc_5 & ~l2_desr_et_5[1] &                 ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5) |
		   (l2_desr_exc_5 &  l2_desr_et_5[1] & ~s_desr_exc_5 & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5) ;
assign take_l2_4 = (l2_desr_et_4[5] & ~l2_desr_et_4[1] &          							~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | 
                   (l2_desr_et_4[5] &  l2_desr_et_4[1] & ~pipe_desr_et_4[5]  & ~m_desr_et_4[5] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | 
		   (l2_desr_exc_4 & ~l2_desr_et_4[1] &                 ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4) |
		   (l2_desr_exc_4 &  l2_desr_et_4[1] & ~s_desr_exc_4 & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4) ;
assign take_l2_3 = (l2_desr_et_3[5] & ~l2_desr_et_3[1] &          							~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | 
                   (l2_desr_et_3[5] &  l2_desr_et_3[1] & ~pipe_desr_et_3[5]  & ~m_desr_et_3[5] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | 
		   (l2_desr_exc_3 & ~l2_desr_et_3[1] &                 ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3) |
		   (l2_desr_exc_3 &  l2_desr_et_3[1] & ~s_desr_exc_3 & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3) ;
assign take_l2_2 = (l2_desr_et_2[5] & ~l2_desr_et_2[1] &          							~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | 
                   (l2_desr_et_2[5] &  l2_desr_et_2[1] & ~pipe_desr_et_2[5]  & ~m_desr_et_2[5] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | 
		   (l2_desr_exc_2 & ~l2_desr_et_2[1] &                 ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2) |
		   (l2_desr_exc_2 &  l2_desr_et_2[1] & ~s_desr_exc_2 & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2) ;
assign take_l2_1 = (l2_desr_et_1[5] & ~l2_desr_et_1[1] &          							~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | 
                   (l2_desr_et_1[5] &  l2_desr_et_1[1] & ~pipe_desr_et_1[5]  & ~m_desr_et_1[5] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | 
		   (l2_desr_exc_1 & ~l2_desr_et_1[1] &                 ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1) |
		   (l2_desr_exc_1 &  l2_desr_et_1[1] & ~s_desr_exc_1 & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1) ;
assign take_l2_0 = (l2_desr_et_0[5] & ~l2_desr_et_0[1] &          							~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | 
                   (l2_desr_et_0[5] &  l2_desr_et_0[1] & ~pipe_desr_et_0[5]  & ~m_desr_et_0[5] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | 
		   (l2_desr_exc_0 & ~l2_desr_et_0[1] &                 ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0) |
		   (l2_desr_exc_0 &  l2_desr_et_0[1] & ~s_desr_exc_0 & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0) ;

assign take_pipe_7 = (pipe_desr_et_7[5] & ~l2_desr_et_7[5] & ~m_desr_et_7[5] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) |
                     (pipe_desr_et_7[5] &  l2_desr_et_7[1] & ~m_desr_et_7[5] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) |
                     (pipe_desr_exc_7 & no_desr_s_7);
assign take_pipe_6 = (pipe_desr_et_6[5] & ~l2_desr_et_6[5] & ~m_desr_et_6[5] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | 
                     (pipe_desr_et_6[5] &  l2_desr_et_6[1] & ~m_desr_et_6[5] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) | 
                     (pipe_desr_exc_6 & no_desr_s_6);
assign take_pipe_5 = (pipe_desr_et_5[5] & ~l2_desr_et_5[5] & ~m_desr_et_5[5] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | 
                     (pipe_desr_et_5[5] &  l2_desr_et_5[1] & ~m_desr_et_5[5] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) | 
                     (pipe_desr_exc_5 & no_desr_s_5);
assign take_pipe_4 = (pipe_desr_et_4[5] & ~l2_desr_et_4[5] & ~m_desr_et_4[5] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | 
                     (pipe_desr_et_4[5] &  l2_desr_et_4[1] & ~m_desr_et_4[5] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) | 
                     (pipe_desr_exc_4 & no_desr_s_4);
assign take_pipe_3 = (pipe_desr_et_3[5] & ~l2_desr_et_3[5] & ~m_desr_et_3[5] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | 
                     (pipe_desr_et_3[5] &  l2_desr_et_3[1] & ~m_desr_et_3[5] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) | 
                     (pipe_desr_exc_3 & no_desr_s_3);
assign take_pipe_2 = (pipe_desr_et_2[5] & ~l2_desr_et_2[5] & ~m_desr_et_2[5] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | 
                     (pipe_desr_et_2[5] &  l2_desr_et_2[1] & ~m_desr_et_2[5] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) | 
                     (pipe_desr_exc_2 & no_desr_s_2);
assign take_pipe_1 = (pipe_desr_et_1[5] & ~l2_desr_et_1[5] & ~m_desr_et_1[5] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | 
                     (pipe_desr_et_1[5] &  l2_desr_et_1[1] & ~m_desr_et_1[5] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) | 
                     (pipe_desr_exc_1 & no_desr_s_1);
assign take_pipe_0 = (pipe_desr_et_0[5] & ~l2_desr_et_0[5] & ~m_desr_et_0[5] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | 
                     (pipe_desr_et_0[5] &  l2_desr_et_0[1] & ~m_desr_et_0[5] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) | 
                     (pipe_desr_exc_0 & no_desr_s_0);

assign take_m_7 = (m_desr_et_7[5] & ~l2_desr_et_7[5] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) |
                  (m_desr_et_7[5] &  l2_desr_et_7[1] & ~l_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) ;
assign take_m_6 = (m_desr_et_6[5] & ~l2_desr_et_6[5] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) |
		  (m_desr_et_6[5] &  l2_desr_et_6[1] & ~l_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) ;
assign take_m_5 = (m_desr_et_5[5] & ~l2_desr_et_5[5] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) |
		  (m_desr_et_5[5] &  l2_desr_et_5[1] & ~l_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) ;
assign take_m_4 = (m_desr_et_4[5] & ~l2_desr_et_4[5] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) |
		  (m_desr_et_4[5] &  l2_desr_et_4[1] & ~l_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) ;
assign take_m_3 = (m_desr_et_3[5] & ~l2_desr_et_3[5] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) |
		  (m_desr_et_3[5] &  l2_desr_et_3[1] & ~l_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) ;
assign take_m_2 = (m_desr_et_2[5] & ~l2_desr_et_2[5] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) |
		  (m_desr_et_2[5] &  l2_desr_et_2[1] & ~l_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) ;
assign take_m_1 = (m_desr_et_1[5] & ~l2_desr_et_1[5] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) |
		  (m_desr_et_1[5] &  l2_desr_et_1[1] & ~l_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) ;
assign take_m_0 = (m_desr_et_0[5] & ~l2_desr_et_0[5] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) |
		  (m_desr_et_0[5] &  l2_desr_et_0[1] & ~l_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) ;

assign take_l_7 = (l_desr_et_7[5] & ~l2_desr_et_7[5] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) |
		  (l_desr_et_7[5] &  l2_desr_et_7[1] & ~cwq_desr_et_7[5] & ~mamu_desr_et_7[5] & ~ma_desr_et_7[5] & ~t_desr_et_7[5] & ~s_desr_et_7[5]) |
                  (l_desr_exc_7    & ~l2_desr_exc_7 & ~s_desr_exc_7 & ~d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7);
assign take_l_6 = (l_desr_et_6[5] & ~l2_desr_et_6[5] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) |
		  (l_desr_et_6[5] &  l2_desr_et_6[1] & ~cwq_desr_et_6[5] & ~mamu_desr_et_6[5] & ~ma_desr_et_6[5] & ~t_desr_et_6[5] & ~s_desr_et_6[5]) |
                  (l_desr_exc_6    & ~l2_desr_exc_6 & ~s_desr_exc_6 & ~d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6);
assign take_l_5 = (l_desr_et_5[5] & ~l2_desr_et_5[5] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) |
		  (l_desr_et_5[5] &  l2_desr_et_5[1] & ~cwq_desr_et_5[5] & ~mamu_desr_et_5[5] & ~ma_desr_et_5[5] & ~t_desr_et_5[5] & ~s_desr_et_5[5]) |
                  (l_desr_exc_5    & ~l2_desr_exc_5 & ~s_desr_exc_5 & ~d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5);
assign take_l_4 = (l_desr_et_4[5] & ~l2_desr_et_4[5] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) |
		  (l_desr_et_4[5] &  l2_desr_et_4[1] & ~cwq_desr_et_4[5] & ~mamu_desr_et_4[5] & ~ma_desr_et_4[5] & ~t_desr_et_4[5] & ~s_desr_et_4[5]) |
                  (l_desr_exc_4    & ~l2_desr_exc_4 & ~s_desr_exc_4 & ~d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4);
assign take_l_3 = (l_desr_et_3[5] & ~l2_desr_et_3[5] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) |
		  (l_desr_et_3[5] &  l2_desr_et_3[1] & ~cwq_desr_et_3[5] & ~mamu_desr_et_3[5] & ~ma_desr_et_3[5] & ~t_desr_et_3[5] & ~s_desr_et_3[5]) |
                  (l_desr_exc_3    & ~l2_desr_exc_3 & ~s_desr_exc_3 & ~d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3);
assign take_l_2 = (l_desr_et_2[5] & ~l2_desr_et_2[5] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) |
		  (l_desr_et_2[5] &  l2_desr_et_2[1] & ~cwq_desr_et_2[5] & ~mamu_desr_et_2[5] & ~ma_desr_et_2[5] & ~t_desr_et_2[5] & ~s_desr_et_2[5]) |
                  (l_desr_exc_2    & ~l2_desr_exc_2 & ~s_desr_exc_2 & ~d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2);
assign take_l_1 = (l_desr_et_1[5] & ~l2_desr_et_1[5] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) |
		  (l_desr_et_1[5] &  l2_desr_et_1[1] & ~cwq_desr_et_1[5] & ~mamu_desr_et_1[5] & ~ma_desr_et_1[5] & ~t_desr_et_1[5] & ~s_desr_et_1[5]) |
                  (l_desr_exc_1    & ~l2_desr_exc_1 & ~s_desr_exc_1 & ~d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1);
assign take_l_0 = (l_desr_et_0[5] & ~l2_desr_et_0[5] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) |
		  (l_desr_et_0[5] &  l2_desr_et_0[1] & ~cwq_desr_et_0[5] & ~mamu_desr_et_0[5] & ~ma_desr_et_0[5] & ~t_desr_et_0[5] & ~s_desr_et_0[5]) |
                  (l_desr_exc_0    & ~l2_desr_exc_0 & ~s_desr_exc_0 & ~d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0);

assign take_d_7 = d_desr_exc_7 & ~pipe_desr_exc_7 & no_desr_s_7;
assign take_d_6 = d_desr_exc_6 & ~pipe_desr_exc_6 & no_desr_s_6;
assign take_d_5 = d_desr_exc_5 & ~pipe_desr_exc_5 & no_desr_s_5;
assign take_d_4 = d_desr_exc_4 & ~pipe_desr_exc_4 & no_desr_s_4;
assign take_d_3 = d_desr_exc_3 & ~pipe_desr_exc_3 & no_desr_s_3;
assign take_d_2 = d_desr_exc_2 & ~pipe_desr_exc_2 & no_desr_s_2;
assign take_d_1 = d_desr_exc_1 & ~pipe_desr_exc_1 & no_desr_s_1;
assign take_d_0 = d_desr_exc_0 & ~pipe_desr_exc_0 & no_desr_s_0;


assign no_desr_s_7 =
       ~(pipe_desr_et_7[5] | m_desr_et_7[5] | l_desr_et_7[5] |
	 l2_desr_et_7[5] | s_desr_et_7[5] | mamu_desr_et_7[5] |
	 ma_desr_et_7[5] | cwq_desr_et_7[5] | t_desr_et_7[5]);
assign no_desr_s_6 =
       ~(pipe_desr_et_6[5] | m_desr_et_6[5] | l_desr_et_6[5] |
	 l2_desr_et_6[5] | s_desr_et_6[5] | mamu_desr_et_6[5] |
	 ma_desr_et_6[5] | cwq_desr_et_6[5] | t_desr_et_6[5]);
assign no_desr_s_5 =
       ~(pipe_desr_et_5[5] | m_desr_et_5[5] | l_desr_et_5[5] |
	 l2_desr_et_5[5] | s_desr_et_5[5] | mamu_desr_et_5[5] |
	 ma_desr_et_5[5] | cwq_desr_et_5[5] | t_desr_et_5[5]);
assign no_desr_s_4 =
       ~(pipe_desr_et_4[5] | m_desr_et_4[5] | l_desr_et_4[5] |
	 l2_desr_et_4[5] | s_desr_et_4[5] | mamu_desr_et_4[5] |
	 ma_desr_et_4[5] | cwq_desr_et_4[5] | t_desr_et_4[5]);
assign no_desr_s_3 =
       ~(pipe_desr_et_3[5] | m_desr_et_3[5] | l_desr_et_3[5] |
	 l2_desr_et_3[5] | s_desr_et_3[5] | mamu_desr_et_3[5] |
	 ma_desr_et_3[5] | cwq_desr_et_3[5] | t_desr_et_3[5]);
assign no_desr_s_2 =
       ~(pipe_desr_et_2[5] | m_desr_et_2[5] | l_desr_et_2[5] |
	 l2_desr_et_2[5] | s_desr_et_2[5] | mamu_desr_et_2[5] |
	 ma_desr_et_2[5] | cwq_desr_et_2[5] | t_desr_et_2[5]);
assign no_desr_s_1 =
       ~(pipe_desr_et_1[5] | m_desr_et_1[5] | l_desr_et_1[5] |
	 l2_desr_et_1[5] | s_desr_et_1[5] | mamu_desr_et_1[5] |
	 ma_desr_et_1[5] | cwq_desr_et_1[5] | t_desr_et_1[5]);
assign no_desr_s_0 =
       ~(pipe_desr_et_0[5] | m_desr_et_0[5] | l_desr_et_0[5] |
	 l2_desr_et_0[5] | s_desr_et_0[5] | mamu_desr_et_0[5] |
	 ma_desr_et_0[5] | cwq_desr_et_0[5] | t_desr_et_0[5]);

assign ras_desr_et_7[61:56] =
       (                   pipe_desr_et_7[5:0]  & {6 {take_pipe_7}}) |
       (                      m_desr_et_7[5:0]  & {6 {   take_m_7}}) |
       (                      l_desr_et_7[5:0]  & {6 {   take_l_7}}) |
       ({1'b0, {1 {1'b0}},    d_desr_et_7[3:0]} & {6 {   take_d_7}}) |
       (                     l2_desr_et_7[5:0]  & {6 {  take_l2_7}}) |
       (                      s_desr_et_7[5:0]  & {6 {   take_s_7}}) |
       (                   mamu_desr_et_7[5:0]  & {6 {take_mamu_7}}) |
       (                     ma_desr_et_7[5:0]  & {6 {  take_ma_7}}) |
       (                    cwq_desr_et_7[5:0]  & {6 { take_cwq_7}}) |
       (                      t_desr_et_7[5:0]  & {6 {   take_t_7}}) ;

assign ras_desr_et_6[61:56] =
       (                   pipe_desr_et_6[5:0]  & {6 {take_pipe_6}}) |
       (                      m_desr_et_6[5:0]  & {6 {   take_m_6}}) |
       (                      l_desr_et_6[5:0]  & {6 {   take_l_6}}) |
       ({1'b0, {1 {1'b0}},    d_desr_et_6[3:0]} & {6 {   take_d_6}}) |
       (                     l2_desr_et_6[5:0]  & {6 {  take_l2_6}}) |
       (                      s_desr_et_6[5:0]  & {6 {   take_s_6}}) |
       (                   mamu_desr_et_6[5:0]  & {6 {take_mamu_6}}) |
       (                     ma_desr_et_6[5:0]  & {6 {  take_ma_6}}) |
       (                    cwq_desr_et_6[5:0]  & {6 { take_cwq_6}}) |
       (                      t_desr_et_6[5:0]  & {6 {   take_t_6}}) ;

assign ras_desr_et_5[61:56] =
       (                   pipe_desr_et_5[5:0]  & {6 {take_pipe_5}}) |
       (                      m_desr_et_5[5:0]  & {6 {   take_m_5}}) |
       (                      l_desr_et_5[5:0]  & {6 {   take_l_5}}) |
       ({1'b0, {1 {1'b0}},    d_desr_et_5[3:0]} & {6 {   take_d_5}}) |
       (                     l2_desr_et_5[5:0]  & {6 {  take_l2_5}}) |
       (                      s_desr_et_5[5:0]  & {6 {   take_s_5}}) |
       (                   mamu_desr_et_5[5:0]  & {6 {take_mamu_5}}) |
       (                     ma_desr_et_5[5:0]  & {6 {  take_ma_5}}) |
       (                    cwq_desr_et_5[5:0]  & {6 { take_cwq_5}}) |
       (                      t_desr_et_5[5:0]  & {6 {   take_t_5}}) ;

assign ras_desr_et_4[61:56] =
       (                   pipe_desr_et_4[5:0]  & {6 {take_pipe_4}}) |
       (                      m_desr_et_4[5:0]  & {6 {   take_m_4}}) |
       (                      l_desr_et_4[5:0]  & {6 {   take_l_4}}) |
       ({1'b0, {1 {1'b0}},    d_desr_et_4[3:0]} & {6 {   take_d_4}}) |
       (                     l2_desr_et_4[5:0]  & {6 {  take_l2_4}}) |
       (                      s_desr_et_4[5:0]  & {6 {   take_s_4}}) |
       (                   mamu_desr_et_4[5:0]  & {6 {take_mamu_4}}) |
       (                     ma_desr_et_4[5:0]  & {6 {  take_ma_4}}) |
       (                    cwq_desr_et_4[5:0]  & {6 { take_cwq_4}}) |
       (                      t_desr_et_4[5:0]  & {6 {   take_t_4}}) ;

assign ras_desr_et_3[61:56] =
       (                   pipe_desr_et_3[5:0]  & {6 {take_pipe_3}}) |
       (                      m_desr_et_3[5:0]  & {6 {   take_m_3}}) |
       (                      l_desr_et_3[5:0]  & {6 {   take_l_3}}) |
       ({1'b0, {1 {1'b0}},    d_desr_et_3[3:0]} & {6 {   take_d_3}}) |
       (                     l2_desr_et_3[5:0]  & {6 {  take_l2_3}}) |
       (                      s_desr_et_3[5:0]  & {6 {   take_s_3}}) |
       (                   mamu_desr_et_3[5:0]  & {6 {take_mamu_3}}) |
       (                     ma_desr_et_3[5:0]  & {6 {  take_ma_3}}) |
       (                    cwq_desr_et_3[5:0]  & {6 { take_cwq_3}}) |
       (                      t_desr_et_3[5:0]  & {6 {   take_t_3}}) ;

assign ras_desr_et_2[61:56] =
       (                   pipe_desr_et_2[5:0]  & {6 {take_pipe_2}}) |
       (                      m_desr_et_2[5:0]  & {6 {   take_m_2}}) |
       (                      l_desr_et_2[5:0]  & {6 {   take_l_2}}) |
       ({1'b0, {1 {1'b0}},    d_desr_et_2[3:0]} & {6 {   take_d_2}}) |
       (                     l2_desr_et_2[5:0]  & {6 {  take_l2_2}}) |
       (                      s_desr_et_2[5:0]  & {6 {   take_s_2}}) |
       (                   mamu_desr_et_2[5:0]  & {6 {take_mamu_2}}) |
       (                     ma_desr_et_2[5:0]  & {6 {  take_ma_2}}) |
       (                    cwq_desr_et_2[5:0]  & {6 { take_cwq_2}}) |
       (                      t_desr_et_2[5:0]  & {6 {   take_t_2}}) ;

assign ras_desr_et_1[61:56] =
       (                   pipe_desr_et_1[5:0]  & {6 {take_pipe_1}}) |
       (                      m_desr_et_1[5:0]  & {6 {   take_m_1}}) |
       (                      l_desr_et_1[5:0]  & {6 {   take_l_1}}) |
       ({1'b0, {1 {1'b0}},    d_desr_et_1[3:0]} & {6 {   take_d_1}}) |
       (                     l2_desr_et_1[5:0]  & {6 {  take_l2_1}}) |
       (                      s_desr_et_1[5:0]  & {6 {   take_s_1}}) |
       (                   mamu_desr_et_1[5:0]  & {6 {take_mamu_1}}) |
       (                     ma_desr_et_1[5:0]  & {6 {  take_ma_1}}) |
       (                    cwq_desr_et_1[5:0]  & {6 { take_cwq_1}}) |
       (                      t_desr_et_1[5:0]  & {6 {   take_t_1}}) ;

assign ras_desr_et_0[61:56] =
       (                   pipe_desr_et_0[5:0]  & {6 {take_pipe_0}}) |
       (                      m_desr_et_0[5:0]  & {6 {   take_m_0}}) |
       (                      l_desr_et_0[5:0]  & {6 {   take_l_0}}) |
       ({1'b0, {1 {1'b0}},    d_desr_et_0[3:0]} & {6 {   take_d_0}}) |
       (                     l2_desr_et_0[5:0]  & {6 {  take_l2_0}}) |
       (                      s_desr_et_0[5:0]  & {6 {   take_s_0}}) |
       (                   mamu_desr_et_0[5:0]  & {6 {take_mamu_0}}) |
       (                     ma_desr_et_0[5:0]  & {6 {  take_ma_0}}) |
       (                    cwq_desr_et_0[5:0]  & {6 { take_cwq_0}}) |
       (                      t_desr_et_0[5:0]  & {6 {   take_t_0}}) ;


assign write_desr[7:0] = 
       {| ras_desr_et_7[60:56],
	| ras_desr_et_6[60:56],
	| ras_desr_et_5[60:56],
	| ras_desr_et_4[60:56],
	| ras_desr_et_3[60:56],
	| ras_desr_et_2[60:56],
	| ras_desr_et_1[60:56],
	| ras_desr_et_0[60:56]};

assign write_desr_s[7:0] = 
       {ras_desr_et_7[61],
	ras_desr_et_6[61],
	ras_desr_et_5[61],
	ras_desr_et_4[61],
	ras_desr_et_3[61],
	ras_desr_et_2[61],
	ras_desr_et_1[61],
	ras_desr_et_0[61]};

assign ras_write_desr_1st[7:0] =
       (write_desr  [7:0] & ~dfd_desr_f[7:0]) | 
       (write_desr_s[7:0] & ~dfd_desr_s[7:0]) |
       (write_desr  [7:0] & rd_desr_dec[7:0]) ;

assign ras_write_desr_2nd[7:0] =
       (write_desr[7:0] & ~write_desr_s[7:0] & dfd_desr_f[7:0]) |
       (                     write_desr_s[7:0] & dfd_desr_s[7:0]) ;

assign ras_desr_me_7 =
       (({{3 {1'b0}}, pipe_desr_exc_7} +
      	 {{3 {1'b0}},    m_desr_exc_7} +
      	 {{3 {1'b0}},    l_desr_exc_7} +
      	 {{3 {1'b0}},    d_desr_exc_7} +
      	 {{3 {1'b0}},   l2_desr_exc_7} +
      	 {{3 {1'b0}},    s_desr_exc_7} +
      	 {{3 {1'b0}}, mamu_desr_exc_7} +
      	 {{3 {1'b0}},   ma_desr_exc_7} +
      	 {{3 {1'b0}},  cwq_desr_exc_7} +
      	 {{3 {1'b0}},    t_desr_exc_7}) > 4'b0001) | 
	(dfd_desr_f[7] & ~rd_desr_dec[7]);
assign ras_desr_me_6 =
       (({{3 {1'b0}}, pipe_desr_exc_6} +
      	 {{3 {1'b0}},    m_desr_exc_6} +
      	 {{3 {1'b0}},    l_desr_exc_6} +
      	 {{3 {1'b0}},    d_desr_exc_6} +
      	 {{3 {1'b0}},   l2_desr_exc_6} +
      	 {{3 {1'b0}},    s_desr_exc_6} +
      	 {{3 {1'b0}}, mamu_desr_exc_6} +
      	 {{3 {1'b0}},   ma_desr_exc_6} +
      	 {{3 {1'b0}},  cwq_desr_exc_6} +
      	 {{3 {1'b0}},    t_desr_exc_6}) > 4'b0001) | 
	(dfd_desr_f[6] & ~rd_desr_dec[6]);
assign ras_desr_me_5 =
       (({{3 {1'b0}}, pipe_desr_exc_5} +
      	 {{3 {1'b0}},    m_desr_exc_5} +
      	 {{3 {1'b0}},    l_desr_exc_5} +
      	 {{3 {1'b0}},    d_desr_exc_5} +
      	 {{3 {1'b0}},   l2_desr_exc_5} +
      	 {{3 {1'b0}},    s_desr_exc_5} +
      	 {{3 {1'b0}}, mamu_desr_exc_5} +
      	 {{3 {1'b0}},   ma_desr_exc_5} +
      	 {{3 {1'b0}},  cwq_desr_exc_5} +
      	 {{3 {1'b0}},    t_desr_exc_5}) > 4'b0001) | 
	(dfd_desr_f[5] & ~rd_desr_dec[5]);
assign ras_desr_me_4 =		    
       (({{3 {1'b0}}, pipe_desr_exc_4} +
      	 {{3 {1'b0}},    m_desr_exc_4} +
      	 {{3 {1'b0}},    l_desr_exc_4} +
      	 {{3 {1'b0}},    d_desr_exc_4} +
      	 {{3 {1'b0}},   l2_desr_exc_4} +
      	 {{3 {1'b0}},    s_desr_exc_4} +
      	 {{3 {1'b0}}, mamu_desr_exc_4} +
      	 {{3 {1'b0}},   ma_desr_exc_4} +
      	 {{3 {1'b0}},  cwq_desr_exc_4} +
      	 {{3 {1'b0}},    t_desr_exc_4}) > 4'b0001) | 
	(dfd_desr_f[4] & ~rd_desr_dec[4]);
assign ras_desr_me_3 =		    
       (({{3 {1'b0}}, pipe_desr_exc_3} +
      	 {{3 {1'b0}},    m_desr_exc_3} +
      	 {{3 {1'b0}},    l_desr_exc_3} +
      	 {{3 {1'b0}},    d_desr_exc_3} +
      	 {{3 {1'b0}},   l2_desr_exc_3} +
      	 {{3 {1'b0}},    s_desr_exc_3} +
      	 {{3 {1'b0}}, mamu_desr_exc_3} +
      	 {{3 {1'b0}},   ma_desr_exc_3} +
      	 {{3 {1'b0}},  cwq_desr_exc_3} +
      	 {{3 {1'b0}},    t_desr_exc_3}) > 4'b0001) | 
	(dfd_desr_f[3] & ~rd_desr_dec[3]);
assign ras_desr_me_2 =		    
       (({{3 {1'b0}}, pipe_desr_exc_2} +
      	 {{3 {1'b0}},    m_desr_exc_2} +
      	 {{3 {1'b0}},    l_desr_exc_2} +
      	 {{3 {1'b0}},    d_desr_exc_2} +
      	 {{3 {1'b0}},   l2_desr_exc_2} +
      	 {{3 {1'b0}},    s_desr_exc_2} +
      	 {{3 {1'b0}}, mamu_desr_exc_2} +
      	 {{3 {1'b0}},   ma_desr_exc_2} +
      	 {{3 {1'b0}},  cwq_desr_exc_2} +
      	 {{3 {1'b0}},    t_desr_exc_2}) > 4'b0001) | 
	(dfd_desr_f[2] & ~rd_desr_dec[2]);
assign ras_desr_me_1 =		    
       (({{3 {1'b0}}, pipe_desr_exc_1} +
      	 {{3 {1'b0}},    m_desr_exc_1} +
      	 {{3 {1'b0}},    l_desr_exc_1} +
      	 {{3 {1'b0}},    d_desr_exc_1} +
      	 {{3 {1'b0}},   l2_desr_exc_1} +
      	 {{3 {1'b0}},    s_desr_exc_1} +
      	 {{3 {1'b0}}, mamu_desr_exc_1} +
      	 {{3 {1'b0}},   ma_desr_exc_1} +
      	 {{3 {1'b0}},  cwq_desr_exc_1} +
      	 {{3 {1'b0}},    t_desr_exc_1}) > 4'b0001) | 
	(dfd_desr_f[1] & ~rd_desr_dec[1]);
assign ras_desr_me_0 =		    
       (({{3 {1'b0}}, pipe_desr_exc_0} +
      	 {{3 {1'b0}},    m_desr_exc_0} +
      	 {{3 {1'b0}},    l_desr_exc_0} +
      	 {{3 {1'b0}},    d_desr_exc_0} +
      	 {{3 {1'b0}},   l2_desr_exc_0} +
      	 {{3 {1'b0}},    s_desr_exc_0} +
      	 {{3 {1'b0}}, mamu_desr_exc_0} +
      	 {{3 {1'b0}},   ma_desr_exc_0} +
      	 {{3 {1'b0}},  cwq_desr_exc_0} +
      	 {{3 {1'b0}},    t_desr_exc_0}) > 4'b0001) | 
	(dfd_desr_f[0] & ~rd_desr_dec[0]);
			

assign ras_desr_ea_7[10:0] =
       ({{2 {1'b0}}, pipe_desr_ea_7[8:0]} & {11 {take_pipe_7}}) |
       ({{2 {1'b0}},    d_desr_ea_7[8:0]} & {11 {   take_d_7}}) |
       ({{8 {1'b0}},    s_desr_ea_7[2:0]} & {11 {   take_s_7}}) |
       (             mamu_desr_ea_7[10:0]  & {11 {take_mamu_7}}) |
       ({{1 {1'b0}},    t_desr_ea_7[9:0]} & {11 {   take_t_7}}) ;
assign ras_desr_ea_6[10:0] =
       ({{2 {1'b0}}, pipe_desr_ea_6[8:0]} & {11 {take_pipe_6}}) |
       ({{2 {1'b0}},    d_desr_ea_6[8:0]} & {11 {   take_d_6}}) |
       ({{8 {1'b0}},    s_desr_ea_6[2:0]} & {11 {   take_s_6}}) |
       (             mamu_desr_ea_6[10:0]  & {11 {take_mamu_6}}) |
       ({{1 {1'b0}},    t_desr_ea_6[9:0]} & {11 {   take_t_6}}) ;
assign ras_desr_ea_5[10:0] =
       ({{2 {1'b0}}, pipe_desr_ea_5[8:0]} & {11 {take_pipe_5}}) |
       ({{2 {1'b0}},    d_desr_ea_5[8:0]} & {11 {   take_d_5}}) |
       ({{8 {1'b0}},    s_desr_ea_5[2:0]} & {11 {   take_s_5}}) |
       (             mamu_desr_ea_5[10:0]  & {11 {take_mamu_5}}) |
       ({{1 {1'b0}},    t_desr_ea_5[9:0]} & {11 {   take_t_5}}) ;
assign ras_desr_ea_4[10:0] =
       ({{2 {1'b0}}, pipe_desr_ea_4[8:0]} & {11 {take_pipe_4}}) |
       ({{2 {1'b0}},    d_desr_ea_4[8:0]} & {11 {   take_d_4}}) |
       ({{8 {1'b0}},    s_desr_ea_4[2:0]} & {11 {   take_s_4}}) |
       (             mamu_desr_ea_4[10:0]  & {11 {take_mamu_4}}) |
       ({{1 {1'b0}},    t_desr_ea_4[9:0]} & {11 {   take_t_4}}) ;
assign ras_desr_ea_3[10:0] =
       ({{2 {1'b0}}, pipe_desr_ea_3[8:0]} & {11 {take_pipe_3}}) |
       ({{2 {1'b0}},    d_desr_ea_3[8:0]} & {11 {   take_d_3}}) |
       ({{8 {1'b0}},    s_desr_ea_3[2:0]} & {11 {   take_s_3}}) |
       (             mamu_desr_ea_3[10:0]  & {11 {take_mamu_3}}) |
       ({{1 {1'b0}},    t_desr_ea_3[9:0]} & {11 {   take_t_3}}) ;
assign ras_desr_ea_2[10:0] =
       ({{2 {1'b0}}, pipe_desr_ea_2[8:0]} & {11 {take_pipe_2}}) |
       ({{2 {1'b0}},    d_desr_ea_2[8:0]} & {11 {   take_d_2}}) |
       ({{8 {1'b0}},    s_desr_ea_2[2:0]} & {11 {   take_s_2}}) |
       (             mamu_desr_ea_2[10:0]  & {11 {take_mamu_2}}) |
       ({{1 {1'b0}},    t_desr_ea_2[9:0]} & {11 {   take_t_2}}) ;
assign ras_desr_ea_1[10:0] =
       ({{2 {1'b0}}, pipe_desr_ea_1[8:0]} & {11 {take_pipe_1}}) |
       ({{2 {1'b0}},    d_desr_ea_1[8:0]} & {11 {   take_d_1}}) |
       ({{8 {1'b0}},    s_desr_ea_1[2:0]} & {11 {   take_s_1}}) |
       (             mamu_desr_ea_1[10:0]  & {11 {take_mamu_1}}) |
       ({{1 {1'b0}},    t_desr_ea_1[9:0]} & {11 {   take_t_1}}) ;
assign ras_desr_ea_0[10:0] =
       ({{2 {1'b0}}, pipe_desr_ea_0[8:0]} & {11 {take_pipe_0}}) |
       ({{2 {1'b0}},    d_desr_ea_0[8:0]} & {11 {   take_d_0}}) |
       ({{8 {1'b0}},    s_desr_ea_0[2:0]} & {11 {   take_s_0}}) |
       (             mamu_desr_ea_0[10:0]  & {11 {take_mamu_0}}) |
       ({{1 {1'b0}},    t_desr_ea_0[9:0]} & {11 {   take_t_0}}) ;


//////////////////////////////////////////////////////////////////////////////
//
//  Handle fatal errors
//
// FESR
// sbdiou 01
// sbapp  10

tlu_ras_ctl_msff_ctl_macro__width_1 sbdiou_lat  (
	.scan_in(sbdiou_lat_scanin),
	.scan_out(sbdiou_lat_scanout),
	.din	(lsu_sbdiou_err_g		),
	.dout	(sbdiou				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 sbapp_lat  (
	.scan_in(sbapp_lat_scanin),
	.scan_out(sbapp_lat_scanout),
	.din	(lsu_sbapp_err_g		),
	.dout	(sbapp				),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign f_dec_tid[7:0] = 
       { s_tid[2] &  s_tid[1] &  s_tid[0],
         s_tid[2] &  s_tid[1] & ~s_tid[0],
         s_tid[2] & ~s_tid[1] &  s_tid[0],
         s_tid[2] & ~s_tid[1] & ~s_tid[0],
        ~s_tid[2] &  s_tid[1] &  s_tid[0],
        ~s_tid[2] &  s_tid[1] & ~s_tid[0],
        ~s_tid[2] & ~s_tid[1] &  s_tid[0],
        ~s_tid[2] & ~s_tid[1] & ~s_tid[0]} & 
       {8 {sbdiou | sbapp}};

assign ras_fesr_et_7[61:60] =
       {sbapp, sbdiou} & {2 {f_dec_tid[7]}};
assign ras_fesr_et_6[61:60] =
       {sbapp, sbdiou} & {2 {f_dec_tid[6]}};
assign ras_fesr_et_5[61:60] =
       {sbapp, sbdiou} & {2 {f_dec_tid[5]}};
assign ras_fesr_et_4[61:60] =
       {sbapp, sbdiou} & {2 {f_dec_tid[4]}};
assign ras_fesr_et_3[61:60] =
       {sbapp, sbdiou} & {2 {f_dec_tid[3]}};
assign ras_fesr_et_2[61:60] =
       {sbapp, sbdiou} & {2 {f_dec_tid[2]}};
assign ras_fesr_et_1[61:60] =
       {sbapp, sbdiou} & {2 {f_dec_tid[1]}};
assign ras_fesr_et_0[61:60] =
       {sbapp, sbdiou} & {2 {f_dec_tid[0]}};

assign write_fesr[7:0] =
       f_dec_tid[7:0];

assign ras_fesr_en[7:0] =
       write_fesr[7:0] | ras_rd_fesr[7:0] | update_priv[7:0];

assign ras_write_fesr[7:0] =
       write_fesr[7:0] & (~dfd_fesr_f[7:0] | ras_rd_fesr[7:0]);

assign ras_fesr_ea_7[59:55] =
       {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[7]}};
assign ras_fesr_ea_6[59:55] =
       {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[6]}};
assign ras_fesr_ea_5[59:55] =
       {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[5]}};
assign ras_fesr_ea_4[59:55] =
       {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[4]}};
assign ras_fesr_ea_3[59:55] =
       {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[3]}};
assign ras_fesr_ea_2[59:55] =
       {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[2]}};
assign ras_fesr_ea_1[59:55] =
       {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[1]}};
assign ras_fesr_ea_0[59:55] =
       {fesr_priv[1:0], s_dsfar[2:0]} & {5 {f_dec_tid[0]}};


//////////////////////////////////////////////////////////////////////////////
//
//  Support debug event control register function
//
// error_event_1 error_event_0	meaning
//	0		0	no event
//	0		1	precise error
//	1		0	disrupting error
//	1		1	deferred error

assign error_event_1_in[7:0] =
	write_desr[7:0] |
	write_fesr[7:0];

assign error_event_0_in[7:0] =
	precise_i_error[7:0] | precise_d_error[7:0] |
	write_fesr[7:0];

tlu_ras_ctl_msff_ctl_macro__width_8 event_1_lat  (
	.scan_in(event_1_lat_scanin),
	.scan_out(event_1_lat_scanout),
	.din	(error_event_1_in	[7:0]	),
	.dout	(error_event_1		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_8 event_0_lat  (
	.scan_in(event_0_lat_scanin),
	.scan_out(event_0_lat_scanout),
	.din	(error_event_0_in	[7:0]	),
	.dout	(error_event_0		[7:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ras_precise_error[7:0] =
	~error_event_1[7:0] &  error_event_0[7:0];

assign ras_disrupting_error[7:0] =
	 error_event_1[7:0] & ~error_event_0[7:0];

assign ras_deferred_error[7:0] =
	 error_event_1[7:0] &  error_event_0[7:0];


//////////////////////////////////////////////////////////////////////////////
//
// Spares
//

// Each pack has one flop
tlu_ras_ctl_spare_ctl_macro__num_16 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk				),
  .siclk(siclk),
  .soclk(soclk)
);


// Add some more flops
// sparex_lat gets placed with spare pack x
tlu_ras_ctl_msff_ctl_macro__width_1 spare0_lat  (
	.scan_in(spare0_lat_scanin),
	.scan_out(spare0_lat_scanout),
	.din	(1'b0				),
	.dout	(spare0_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare1_lat  (
	.scan_in(spare1_lat_scanin),
	.scan_out(spare1_lat_scanout),
	.din	(1'b0				),
	.dout	(spare1_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare2_lat  (
	.scan_in(spare2_lat_scanin),
	.scan_out(spare2_lat_scanout),
	.din	(1'b0				),
	.dout	(spare2_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare3_lat  (
	.scan_in(spare3_lat_scanin),
	.scan_out(spare3_lat_scanout),
	.din	(1'b0				),
	.dout	(spare3_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare4_lat  (
	.scan_in(spare4_lat_scanin),
	.scan_out(spare4_lat_scanout),
	.din	(1'b0				),
	.dout	(spare4_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare5_lat  (
	.scan_in(spare5_lat_scanin),
	.scan_out(spare5_lat_scanout),
	.din	(1'b0				),
	.dout	(spare5_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare6_lat  (
	.scan_in(spare6_lat_scanin),
	.scan_out(spare6_lat_scanout),
	.din	(1'b0				),
	.dout	(spare6_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare7_lat  (
	.scan_in(spare7_lat_scanin),
	.scan_out(spare7_lat_scanout),
	.din	(1'b0				),
	.dout	(spare7_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare8_lat  (
	.scan_in(spare8_lat_scanin),
	.scan_out(spare8_lat_scanout),
	.din	(1'b0				),
	.dout	(spare8_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare9_lat  (
	.scan_in(spare9_lat_scanin),
	.scan_out(spare9_lat_scanout),
	.din	(1'b0				),
	.dout	(spare9_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare10_lat  (
	.scan_in(spare10_lat_scanin),
	.scan_out(spare10_lat_scanout),
	.din	(1'b0				),
	.dout	(spare10_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare11_lat  (
	.scan_in(spare11_lat_scanin),
	.scan_out(spare11_lat_scanout),
	.din	(1'b0				),
	.dout	(spare11_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare12_lat  (
	.scan_in(spare12_lat_scanin),
	.scan_out(spare12_lat_scanout),
	.din	(1'b0				),
	.dout	(spare12_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare13_lat  (
	.scan_in(spare13_lat_scanin),
	.scan_out(spare13_lat_scanout),
	.din	(1'b0				),
	.dout	(spare13_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare14_lat  (
	.scan_in(spare14_lat_scanin),
	.scan_out(spare14_lat_scanout),
	.din	(1'b0				),
	.dout	(spare14_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_ras_ctl_msff_ctl_macro__width_1 spare15_lat  (
	.scan_in(spare15_lat_scanin),
	.scan_out(spare15_lat_scanout),
	.din	(1'b0				),
	.dout	(spare15_unused			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

// fixscan start:
assign twocycle_inst_b_lat_scanin = scan_in                  ;
assign inst_valid_b_lat_scanin   = twocycle_inst_b_lat_scanout;
assign w_en_lat_scanin           = inst_valid_b_lat_scanout ;
assign w1_en_lat_scanin          = w_en_lat_scanout         ;
assign inst_valid_w_lat_scanin   = w1_en_lat_scanout        ;
assign block_store_w_lat_scanin  = inst_valid_w_lat_scanout ;
assign tid1_b_lat_scanin         = block_store_w_lat_scanout;
assign tid0_b_lat_scanin         = tid1_b_lat_scanout       ;
assign tid1_w_lat_scanin         = tid0_b_lat_scanout       ;
assign tid0_w_lat_scanin         = tid1_w_lat_scanout       ;
assign fgu_inst_b_lat_scanin     = tid0_w_lat_scanout       ;
assign fgu_inst_w_lat_scanin     = fgu_inst_b_lat_scanout   ;
assign lsu_inst_b_lat_scanin     = fgu_inst_w_lat_scanout   ;
assign i_isfsr1_b_lat_scanin     = lsu_inst_b_lat_scanout   ;
assign i_isfsr0_b_lat_scanin     = i_isfsr1_b_lat_scanout   ;
assign i_desr1_b_lat_scanin      = i_isfsr0_b_lat_scanout   ;
assign i_desr0_b_lat_scanin      = i_desr1_b_lat_scanout    ;
assign irf0_ecc_addr_b_lat_scanin = i_desr0_b_lat_scanout    ;
assign irf1_ecc_addr_b_lat_scanin = irf0_ecc_addr_b_lat_scanout;
assign irf0_ecc_check_b_lat_scanin = irf1_ecc_addr_b_lat_scanout;
assign irf1_ecc_check_b_lat_scanin = irf0_ecc_check_b_lat_scanout;
assign i_isfsr1_w_lat_scanin     = irf1_ecc_check_b_lat_scanout;
assign i_isfsr0_w_lat_scanin     = i_isfsr1_w_lat_scanout   ;
assign i_desr1_w_lat_scanin      = i_isfsr0_w_lat_scanout   ;
assign i_desr0_w_lat_scanin      = i_desr1_w_lat_scanout    ;
assign irfu_w_lat_scanin         = i_desr0_w_lat_scanout    ;
assign irfc_w_lat_scanin         = irfu_w_lat_scanout       ;
assign seen_bsee_lat_scanin      = irfc_w_lat_scanout       ;
assign dttp_w_lat_scanin         = seen_bsee_lat_scanout    ;
assign dtmh_w_lat_scanin         = dttp_w_lat_scanout       ;
assign dtdp_w_lat_scanin         = dtmh_w_lat_scanout       ;
assign irf0_ecc_addr_w_lat_scanin = dtdp_w_lat_scanout       ;
assign irf1_ecc_addr_w_lat_scanin = irf0_ecc_addr_w_lat_scanout;
assign irf0_ecc_check_w_lat_scanin = irf1_ecc_addr_w_lat_scanout;
assign irf1_ecc_check_w_lat_scanin = irf0_ecc_check_w_lat_scanout;
assign frf_ecc_addr_w_lat_scanin = irf1_ecc_check_w_lat_scanout;
assign frf_ecc_check_w_lat_scanin = frf_ecc_addr_w_lat_scanout;
assign ecc_w1_lat_scanin         = frf_ecc_check_w_lat_scanout;
assign tid1_w1_lat_scanin        = ecc_w1_lat_scanout       ;
assign tid0_w1_lat_scanin        = tid1_w1_lat_scanout      ;
assign pipe_dsfsr1_lat_scanin    = tid0_w1_lat_scanout      ;
assign pipe_dsfsr0_lat_scanin    = pipe_dsfsr1_lat_scanout  ;
assign pipe_dsfar1_lat_scanin    = pipe_dsfsr0_lat_scanout  ;
assign pipe_dsfar0_lat_scanin    = pipe_dsfar1_lat_scanout  ;
assign load_dsfar_lat_scanin     = pipe_dsfar0_lat_scanout  ;
assign i_desr1_w1_lat_scanin     = load_dsfar_lat_scanout   ;
assign i_desr0_w1_lat_scanin     = i_desr1_w1_lat_scanout   ;
assign excp_way_lat_scanin       = i_desr0_w1_lat_scanout   ;
assign ic_way7_lat_scanin        = excp_way_lat_scanout     ;
assign ic_way6_lat_scanin        = ic_way7_lat_scanout      ;
assign ic_way5_lat_scanin        = ic_way6_lat_scanout      ;
assign ic_way4_lat_scanin        = ic_way5_lat_scanout      ;
assign ic_way3_lat_scanin        = ic_way4_lat_scanout      ;
assign ic_way2_lat_scanin        = ic_way3_lat_scanout      ;
assign ic_way1_lat_scanin        = ic_way2_lat_scanout      ;
assign ic_way0_lat_scanin        = ic_way1_lat_scanout      ;
assign pc_1_w1_lat_scanin        = ic_way0_lat_scanout      ;
assign pc_0_w1_lat_scanin        = pc_1_w1_lat_scanout      ;
assign it2lc_lat_scanin          = pc_0_w1_lat_scanout      ;
assign dt2lc_lat_scanin          = it2lc_lat_scanout        ;
assign tca_error_lat_scanin      = dt2lc_lat_scanout        ;
assign l_dsfar_lat_scanin        = tca_error_lat_scanout    ;
assign l_tid_lat_scanin          = l_dsfar_lat_scanout      ;
assign dcl2c_lat_scanin          = l_tid_lat_scanout        ;
assign dcl2u_lat_scanin          = dcl2c_lat_scanout        ;
assign dcl2nd_lat_scanin         = dcl2u_lat_scanout        ;
assign dcsoc_lat_scanin          = dcl2nd_lat_scanout       ;
assign s_dsfar_lat_scanin        = dcsoc_lat_scanout        ;
assign s_tid_lat_scanin          = s_dsfar_lat_scanout      ;
assign stb_flush_lat_scanin      = s_tid_lat_scanout        ;
assign sbdlc_lat_scanin          = stb_flush_lat_scanout    ;
assign sbdlu_lat_scanin          = sbdlc_lat_scanout        ;
assign asi_rd_ctl_lat_scanin     = sbdlu_lat_scanout        ;
assign dcvp_lat_scanin           = asi_rd_ctl_lat_scanout   ;
assign dctp_lat_scanin           = dcvp_lat_scanout         ;
assign dctm_lat_scanin           = dctp_lat_scanout         ;
assign dcdp_lat_scanin           = dctm_lat_scanout         ;
assign cxi_lat_scanin            = dcdp_lat_scanout         ;
assign sbdpc_lat_scanin          = cxi_lat_scanout          ;
assign sbdpu_lat_scanin          = sbdpc_lat_scanout        ;
assign mamu_err_lat_scanin       = sbdpu_lat_scanout        ;
assign ma_tid_lat_scanin         = mamu_err_lat_scanout     ;
assign cwq_tid_lat_scanin        = ma_tid_lat_scanout       ;
assign spu_error_lat_scanin      = cwq_tid_lat_scanout      ;
assign sbdiou_lat_scanin         = spu_error_lat_scanout    ;
assign sbapp_lat_scanin          = sbdiou_lat_scanout       ;
assign event_1_lat_scanin        = sbapp_lat_scanout        ;
assign event_0_lat_scanin        = event_1_lat_scanout      ;
assign spares_scanin             = event_0_lat_scanout      ;
assign spare0_lat_scanin         = spares_scanout           ;
assign spare1_lat_scanin         = spare0_lat_scanout       ;
assign spare2_lat_scanin         = spare1_lat_scanout       ;
assign spare3_lat_scanin         = spare2_lat_scanout       ;
assign spare4_lat_scanin         = spare3_lat_scanout       ;
assign spare5_lat_scanin         = spare4_lat_scanout       ;
assign spare6_lat_scanin         = spare5_lat_scanout       ;
assign spare7_lat_scanin         = spare6_lat_scanout       ;
assign spare8_lat_scanin         = spare7_lat_scanout       ;
assign spare9_lat_scanin         = spare8_lat_scanout       ;
assign spare10_lat_scanin        = spare9_lat_scanout       ;
assign spare11_lat_scanin        = spare10_lat_scanout      ;
assign spare12_lat_scanin        = spare11_lat_scanout      ;
assign spare13_lat_scanin        = spare12_lat_scanout      ;
assign spare14_lat_scanin        = spare13_lat_scanout      ;
assign spare15_lat_scanin        = spare14_lat_scanout      ;
assign scan_out                  = spare15_lat_scanout      ;

assign isfsr_7_lat_wmr_scanin    = wmr_scan_in              ;
assign isfsr_6_lat_wmr_scanin    = isfsr_7_lat_wmr_scanout  ;
assign isfsr_5_lat_wmr_scanin    = isfsr_6_lat_wmr_scanout  ;
assign isfsr_4_lat_wmr_scanin    = isfsr_5_lat_wmr_scanout  ;
assign isfsr_3_lat_wmr_scanin    = isfsr_4_lat_wmr_scanout  ;
assign isfsr_2_lat_wmr_scanin    = isfsr_3_lat_wmr_scanout  ;
assign isfsr_1_lat_wmr_scanin    = isfsr_2_lat_wmr_scanout  ;
assign isfsr_0_lat_wmr_scanin    = isfsr_1_lat_wmr_scanout  ;
assign dsfsr_7_lat_wmr_scanin    = isfsr_0_lat_wmr_scanout  ;
assign dsfsr_6_lat_wmr_scanin    = dsfsr_7_lat_wmr_scanout  ;
assign dsfsr_5_lat_wmr_scanin    = dsfsr_6_lat_wmr_scanout  ;
assign dsfsr_4_lat_wmr_scanin    = dsfsr_5_lat_wmr_scanout  ;
assign dsfsr_3_lat_wmr_scanin    = dsfsr_4_lat_wmr_scanout  ;
assign dsfsr_2_lat_wmr_scanin    = dsfsr_3_lat_wmr_scanout  ;
assign dsfsr_1_lat_wmr_scanin    = dsfsr_2_lat_wmr_scanout  ;
assign dsfsr_0_lat_wmr_scanin    = dsfsr_1_lat_wmr_scanout  ;
assign wmr_scan_out              = dsfsr_0_lat_wmr_scanout  ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;
wire [12:0] so;

  input [13:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si({scan_in,so[12:0]}),
.so({so[12:0],scan_out}),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_20 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [19:0] fdin;
wire [18:0] so;

  input [19:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [19:0] dout;
  output scan_out;
assign fdin[19:0] = din[19:0];


dff #(20)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[19:0]),
.si({scan_in,so[18:0]}),
.so({so[18:0],scan_out}),
.q(dout[19:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;
wire [5:0] so;

  input [6:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si({scan_in,so[5:0]}),
.so({so[5:0],scan_out}),
.q(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ras_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module tlu_ras_ctl_spare_ctl_macro__num_16 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire si_8;
wire so_8;
wire spare8_flop_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;
wire si_9;
wire so_9;
wire spare9_flop_unused;
wire spare9_buf_32x_unused;
wire spare9_nand3_8x_unused;
wire spare9_inv_8x_unused;
wire spare9_aoi22_4x_unused;
wire spare9_buf_8x_unused;
wire spare9_oai22_4x_unused;
wire spare9_inv_16x_unused;
wire spare9_nand2_16x_unused;
wire spare9_nor3_4x_unused;
wire spare9_nand2_8x_unused;
wire spare9_buf_16x_unused;
wire spare9_nor2_16x_unused;
wire spare9_inv_32x_unused;
wire si_10;
wire so_10;
wire spare10_flop_unused;
wire spare10_buf_32x_unused;
wire spare10_nand3_8x_unused;
wire spare10_inv_8x_unused;
wire spare10_aoi22_4x_unused;
wire spare10_buf_8x_unused;
wire spare10_oai22_4x_unused;
wire spare10_inv_16x_unused;
wire spare10_nand2_16x_unused;
wire spare10_nor3_4x_unused;
wire spare10_nand2_8x_unused;
wire spare10_buf_16x_unused;
wire spare10_nor2_16x_unused;
wire spare10_inv_32x_unused;
wire si_11;
wire so_11;
wire spare11_flop_unused;
wire spare11_buf_32x_unused;
wire spare11_nand3_8x_unused;
wire spare11_inv_8x_unused;
wire spare11_aoi22_4x_unused;
wire spare11_buf_8x_unused;
wire spare11_oai22_4x_unused;
wire spare11_inv_16x_unused;
wire spare11_nand2_16x_unused;
wire spare11_nor3_4x_unused;
wire spare11_nand2_8x_unused;
wire spare11_buf_16x_unused;
wire spare11_nor2_16x_unused;
wire spare11_inv_32x_unused;
wire si_12;
wire so_12;
wire spare12_flop_unused;
wire spare12_buf_32x_unused;
wire spare12_nand3_8x_unused;
wire spare12_inv_8x_unused;
wire spare12_aoi22_4x_unused;
wire spare12_buf_8x_unused;
wire spare12_oai22_4x_unused;
wire spare12_inv_16x_unused;
wire spare12_nand2_16x_unused;
wire spare12_nor3_4x_unused;
wire spare12_nand2_8x_unused;
wire spare12_buf_16x_unused;
wire spare12_nor2_16x_unused;
wire spare12_inv_32x_unused;
wire si_13;
wire so_13;
wire spare13_flop_unused;
wire spare13_buf_32x_unused;
wire spare13_nand3_8x_unused;
wire spare13_inv_8x_unused;
wire spare13_aoi22_4x_unused;
wire spare13_buf_8x_unused;
wire spare13_oai22_4x_unused;
wire spare13_inv_16x_unused;
wire spare13_nand2_16x_unused;
wire spare13_nor3_4x_unused;
wire spare13_nand2_8x_unused;
wire spare13_buf_16x_unused;
wire spare13_nor2_16x_unused;
wire spare13_inv_32x_unused;
wire si_14;
wire so_14;
wire spare14_flop_unused;
wire spare14_buf_32x_unused;
wire spare14_nand3_8x_unused;
wire spare14_inv_8x_unused;
wire spare14_aoi22_4x_unused;
wire spare14_buf_8x_unused;
wire spare14_oai22_4x_unused;
wire spare14_inv_16x_unused;
wire spare14_nand2_16x_unused;
wire spare14_nor3_4x_unused;
wire spare14_nand2_8x_unused;
wire spare14_buf_16x_unused;
wire spare14_nor2_16x_unused;
wire spare14_inv_32x_unused;
wire si_15;
wire so_15;
wire spare15_flop_unused;
wire spare15_buf_32x_unused;
wire spare15_nand3_8x_unused;
wire spare15_inv_8x_unused;
wire spare15_aoi22_4x_unused;
wire spare15_buf_8x_unused;
wire spare15_oai22_4x_unused;
wire spare15_inv_16x_unused;
wire spare15_nand2_16x_unused;
wire spare15_nor3_4x_unused;
wire spare15_nand2_8x_unused;
wire spare15_buf_16x_unused;
wire spare15_nor2_16x_unused;
wire spare15_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));

cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_8),
                               .so(so_8),
                               .d(1'b0),
                               .q(spare8_flop_unused));
assign si_8 = so_7;

cl_u1_buf_32x   spare8_buf_32x (.in(1'b1),
                                   .out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare8_nand3_8x_unused));
cl_u1_inv_8x    spare8_inv_8x (.in(1'b1),
                                  .out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_aoi22_4x_unused));
cl_u1_buf_8x    spare8_buf_8x (.in(1'b1),
                                  .out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_oai22_4x_unused));
cl_u1_inv_16x   spare8_inv_16x (.in(1'b1),
                                   .out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare8_nand2_8x_unused));
cl_u1_buf_16x   spare8_buf_16x (.in(1'b1),
                                   .out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare8_nor2_16x_unused));
cl_u1_inv_32x   spare8_inv_32x (.in(1'b1),
                                   .out(spare8_inv_32x_unused));

cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_9),
                               .so(so_9),
                               .d(1'b0),
                               .q(spare9_flop_unused));
assign si_9 = so_8;

cl_u1_buf_32x   spare9_buf_32x (.in(1'b1),
                                   .out(spare9_buf_32x_unused));
cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare9_nand3_8x_unused));
cl_u1_inv_8x    spare9_inv_8x (.in(1'b1),
                                  .out(spare9_inv_8x_unused));
cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_aoi22_4x_unused));
cl_u1_buf_8x    spare9_buf_8x (.in(1'b1),
                                  .out(spare9_buf_8x_unused));
cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_oai22_4x_unused));
cl_u1_inv_16x   spare9_inv_16x (.in(1'b1),
                                   .out(spare9_inv_16x_unused));
cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare9_nand2_16x_unused));
cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare9_nor3_4x_unused));
cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare9_nand2_8x_unused));
cl_u1_buf_16x   spare9_buf_16x (.in(1'b1),
                                   .out(spare9_buf_16x_unused));
cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare9_nor2_16x_unused));
cl_u1_inv_32x   spare9_inv_32x (.in(1'b1),
                                   .out(spare9_inv_32x_unused));

cl_sc1_msff_8x spare10_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_10),
                               .so(so_10),
                               .d(1'b0),
                               .q(spare10_flop_unused));
assign si_10 = so_9;

cl_u1_buf_32x   spare10_buf_32x (.in(1'b1),
                                   .out(spare10_buf_32x_unused));
cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare10_nand3_8x_unused));
cl_u1_inv_8x    spare10_inv_8x (.in(1'b1),
                                  .out(spare10_inv_8x_unused));
cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare10_aoi22_4x_unused));
cl_u1_buf_8x    spare10_buf_8x (.in(1'b1),
                                  .out(spare10_buf_8x_unused));
cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare10_oai22_4x_unused));
cl_u1_inv_16x   spare10_inv_16x (.in(1'b1),
                                   .out(spare10_inv_16x_unused));
cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare10_nand2_16x_unused));
cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare10_nor3_4x_unused));
cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare10_nand2_8x_unused));
cl_u1_buf_16x   spare10_buf_16x (.in(1'b1),
                                   .out(spare10_buf_16x_unused));
cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare10_nor2_16x_unused));
cl_u1_inv_32x   spare10_inv_32x (.in(1'b1),
                                   .out(spare10_inv_32x_unused));

cl_sc1_msff_8x spare11_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_11),
                               .so(so_11),
                               .d(1'b0),
                               .q(spare11_flop_unused));
assign si_11 = so_10;

cl_u1_buf_32x   spare11_buf_32x (.in(1'b1),
                                   .out(spare11_buf_32x_unused));
cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare11_nand3_8x_unused));
cl_u1_inv_8x    spare11_inv_8x (.in(1'b1),
                                  .out(spare11_inv_8x_unused));
cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare11_aoi22_4x_unused));
cl_u1_buf_8x    spare11_buf_8x (.in(1'b1),
                                  .out(spare11_buf_8x_unused));
cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare11_oai22_4x_unused));
cl_u1_inv_16x   spare11_inv_16x (.in(1'b1),
                                   .out(spare11_inv_16x_unused));
cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare11_nand2_16x_unused));
cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare11_nor3_4x_unused));
cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare11_nand2_8x_unused));
cl_u1_buf_16x   spare11_buf_16x (.in(1'b1),
                                   .out(spare11_buf_16x_unused));
cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare11_nor2_16x_unused));
cl_u1_inv_32x   spare11_inv_32x (.in(1'b1),
                                   .out(spare11_inv_32x_unused));

cl_sc1_msff_8x spare12_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_12),
                               .so(so_12),
                               .d(1'b0),
                               .q(spare12_flop_unused));
assign si_12 = so_11;

cl_u1_buf_32x   spare12_buf_32x (.in(1'b1),
                                   .out(spare12_buf_32x_unused));
cl_u1_nand3_8x spare12_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare12_nand3_8x_unused));
cl_u1_inv_8x    spare12_inv_8x (.in(1'b1),
                                  .out(spare12_inv_8x_unused));
cl_u1_aoi22_4x spare12_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare12_aoi22_4x_unused));
cl_u1_buf_8x    spare12_buf_8x (.in(1'b1),
                                  .out(spare12_buf_8x_unused));
cl_u1_oai22_4x spare12_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare12_oai22_4x_unused));
cl_u1_inv_16x   spare12_inv_16x (.in(1'b1),
                                   .out(spare12_inv_16x_unused));
cl_u1_nand2_16x spare12_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare12_nand2_16x_unused));
cl_u1_nor3_4x spare12_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare12_nor3_4x_unused));
cl_u1_nand2_8x spare12_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare12_nand2_8x_unused));
cl_u1_buf_16x   spare12_buf_16x (.in(1'b1),
                                   .out(spare12_buf_16x_unused));
cl_u1_nor2_16x spare12_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare12_nor2_16x_unused));
cl_u1_inv_32x   spare12_inv_32x (.in(1'b1),
                                   .out(spare12_inv_32x_unused));

cl_sc1_msff_8x spare13_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_13),
                               .so(so_13),
                               .d(1'b0),
                               .q(spare13_flop_unused));
assign si_13 = so_12;

cl_u1_buf_32x   spare13_buf_32x (.in(1'b1),
                                   .out(spare13_buf_32x_unused));
cl_u1_nand3_8x spare13_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare13_nand3_8x_unused));
cl_u1_inv_8x    spare13_inv_8x (.in(1'b1),
                                  .out(spare13_inv_8x_unused));
cl_u1_aoi22_4x spare13_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare13_aoi22_4x_unused));
cl_u1_buf_8x    spare13_buf_8x (.in(1'b1),
                                  .out(spare13_buf_8x_unused));
cl_u1_oai22_4x spare13_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare13_oai22_4x_unused));
cl_u1_inv_16x   spare13_inv_16x (.in(1'b1),
                                   .out(spare13_inv_16x_unused));
cl_u1_nand2_16x spare13_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare13_nand2_16x_unused));
cl_u1_nor3_4x spare13_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare13_nor3_4x_unused));
cl_u1_nand2_8x spare13_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare13_nand2_8x_unused));
cl_u1_buf_16x   spare13_buf_16x (.in(1'b1),
                                   .out(spare13_buf_16x_unused));
cl_u1_nor2_16x spare13_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare13_nor2_16x_unused));
cl_u1_inv_32x   spare13_inv_32x (.in(1'b1),
                                   .out(spare13_inv_32x_unused));

cl_sc1_msff_8x spare14_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_14),
                               .so(so_14),
                               .d(1'b0),
                               .q(spare14_flop_unused));
assign si_14 = so_13;

cl_u1_buf_32x   spare14_buf_32x (.in(1'b1),
                                   .out(spare14_buf_32x_unused));
cl_u1_nand3_8x spare14_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare14_nand3_8x_unused));
cl_u1_inv_8x    spare14_inv_8x (.in(1'b1),
                                  .out(spare14_inv_8x_unused));
cl_u1_aoi22_4x spare14_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare14_aoi22_4x_unused));
cl_u1_buf_8x    spare14_buf_8x (.in(1'b1),
                                  .out(spare14_buf_8x_unused));
cl_u1_oai22_4x spare14_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare14_oai22_4x_unused));
cl_u1_inv_16x   spare14_inv_16x (.in(1'b1),
                                   .out(spare14_inv_16x_unused));
cl_u1_nand2_16x spare14_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare14_nand2_16x_unused));
cl_u1_nor3_4x spare14_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare14_nor3_4x_unused));
cl_u1_nand2_8x spare14_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare14_nand2_8x_unused));
cl_u1_buf_16x   spare14_buf_16x (.in(1'b1),
                                   .out(spare14_buf_16x_unused));
cl_u1_nor2_16x spare14_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare14_nor2_16x_unused));
cl_u1_inv_32x   spare14_inv_32x (.in(1'b1),
                                   .out(spare14_inv_32x_unused));

cl_sc1_msff_8x spare15_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_15),
                               .so(so_15),
                               .d(1'b0),
                               .q(spare15_flop_unused));
assign si_15 = so_14;

cl_u1_buf_32x   spare15_buf_32x (.in(1'b1),
                                   .out(spare15_buf_32x_unused));
cl_u1_nand3_8x spare15_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare15_nand3_8x_unused));
cl_u1_inv_8x    spare15_inv_8x (.in(1'b1),
                                  .out(spare15_inv_8x_unused));
cl_u1_aoi22_4x spare15_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare15_aoi22_4x_unused));
cl_u1_buf_8x    spare15_buf_8x (.in(1'b1),
                                  .out(spare15_buf_8x_unused));
cl_u1_oai22_4x spare15_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare15_oai22_4x_unused));
cl_u1_inv_16x   spare15_inv_16x (.in(1'b1),
                                   .out(spare15_inv_16x_unused));
cl_u1_nand2_16x spare15_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare15_nand2_16x_unused));
cl_u1_nor3_4x spare15_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare15_nor3_4x_unused));
cl_u1_nand2_8x spare15_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare15_nand2_8x_unused));
cl_u1_buf_16x   spare15_buf_16x (.in(1'b1),
                                   .out(spare15_buf_16x_unused));
cl_u1_nor2_16x spare15_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare15_nor2_16x_unused));
cl_u1_inv_32x   spare15_inv_32x (.in(1'b1),
                                   .out(spare15_inv_32x_unused));
assign scan_out = so_15;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_ssd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_ssd_dp (
  shscan_l2clk, 
  tcu_shscan_scan_in, 
  tcu_shscan_pce_ov, 
  tcu_shscan_aclk, 
  tcu_shscan_bclk, 
  tcu_shscan_scan_en, 
  trl1_shscanid_2, 
  sse_shscan_clk_stop, 
  sse_shadow_pc, 
  tsd0_shadow_pstate, 
  tsd1_shadow_pstate, 
  tsd0_shadow_tpc, 
  tsd1_shadow_tpc, 
  tsd0_shadow_tt, 
  tsd1_shadow_tt, 
  trl0_shadow_tl, 
  trl1_shadow_tl, 
  trl0_tl_for_tt, 
  trl1_tl_for_tt, 
  spc_shscan_scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire en;
wire clk;
wire se;
wire shadow_0_lat_scan_out;
wire [117:0] shadow_unused;


input		shscan_l2clk;
input 		tcu_shscan_scan_in;
input		tcu_shscan_pce_ov;
input		tcu_shscan_aclk;
input		tcu_shscan_bclk;
input		tcu_shscan_scan_en;

input		trl1_shscanid_2;

input		sse_shscan_clk_stop;
input	[47:2]	sse_shadow_pc;

input	[10:0]	tsd0_shadow_pstate;
input	[10:0]	tsd1_shadow_pstate;

input	[47:2]	tsd0_shadow_tpc;
input	[47:2]	tsd1_shadow_tpc;

input	[8:0]	tsd0_shadow_tt;
input	[8:0]	tsd1_shadow_tt;

input	[2:0]	trl0_shadow_tl;
input	[2:0]	trl1_shadow_tl;

input	[2:0]	trl0_tl_for_tt;
input	[2:0]	trl1_tl_for_tt;


output		spc_shscan_scan_out;


//////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_shscan_pce_ov;
assign stop	= sse_shscan_clk_stop; // Synchronized
assign siclk	= tcu_shscan_aclk;
assign soclk	= tcu_shscan_bclk;
assign en	= 1'b1;
assign clk	= shscan_l2clk;
assign se       = tcu_shscan_scan_en;     


//////////////////////////////////////////////////////////////////////
//
// Shadow scan flops
//

// Note:  These ports are supposed to be cross-wired!
tlu_ssd_dp_msff_macro__mux_aope__ports_2__stack_60c__width_60 shadow_0_lat     (
	.scan_in(tcu_shscan_scan_in),
	.scan_out(shadow_0_lat_scan_out),
	.din1	({sse_shadow_pc		[47:2],
		  tsd0_shadow_pstate	[10:0],
		  trl0_shadow_tl	[2:0]}),
	.din0	({sse_shadow_pc		[47:2],
		  tsd1_shadow_pstate	[10:0],
		  trl1_shadow_tl	[2:0]}),
	.sel0	(trl1_shscanid_2		),
	.dout	(shadow_unused		[117:58]),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_ssd_dp_msff_macro__mux_aope__ports_2__stack_60c__width_58 shadow_1_lat     (
	.scan_in(shadow_0_lat_scan_out),
	.scan_out(spc_shscan_scan_out),
	.din1	({tsd0_shadow_tpc	[47:2],
		  tsd0_shadow_tt	[8:0],
		  trl0_tl_for_tt	[2:0]}),
	.din0	({tsd1_shadow_tpc	[47:2],
		  tsd1_shadow_tt	[8:0],
		  trl1_tl_for_tt	[2:0]}),
	.sel0	(trl1_shscanid_2		),
	.dout	(shadow_unused		[57:0]	),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// Do NOT run fixscan on this file!
endmodule


// any PARAMS parms go into naming of macro

module tlu_ssd_dp_msff_macro__mux_aope__ports_2__stack_60c__width_60 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [59:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [58:0] so;

  input [59:0] din0;
  input [59:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [59:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(60)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[59:0]),
  .in1(din1[59:0]),
.dout(muxout[59:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(60)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[59:0]),
.si({scan_in,so[58:0]}),
.so({so[58:0],scan_out}),
.q(dout[59:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_ssd_dp_msff_macro__mux_aope__ports_2__stack_60c__width_58 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [57:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [56:0] so;

  input [57:0] din0;
  input [57:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [57:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(58)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[57:0]),
  .in1(din1[57:0]),
.dout(muxout[57:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(58)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[57:0]),
.si({scan_in,so[56:0]}),
.so({so[56:0],scan_out}),
.q(dout[57:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_sse_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_sse_dp (
  l2clk, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  scan_in, 
  tcu_shscan_clk_stop, 
  trl1_shscanid_2, 
  fls_ss_update_pc_w, 
  pct0_shadow_pc_d, 
  pct1_shadow_pc_d, 
  fls0_spc_hardstop_request, 
  fls0_spc_softstop_request, 
  fls0_spc_trigger_pulse, 
  fls1_spc_hardstop_request, 
  fls1_spc_softstop_request, 
  fls1_spc_trigger_pulse, 
  scan_out, 
  sse_shscan_clk_stop, 
  sse_shadow_pc, 
  tlu_hardstop_request, 
  tlu_softstop_request, 
  tlu_trigger_pulse);
wire stop;
wire en;
wire clk;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire pc_e_lat_scanin;
wire pc_e_lat_scanout;
wire [47:2] pc_e;
wire pc_m_lat_scanin;
wire pc_m_lat_scanout;
wire [47:2] pc_m;
wire pc_b_lat_scanin;
wire pc_b_lat_scanout;
wire shscan_clk_stop_in;
wire [47:2] pc_b;
wire pc_w_lat_scanin;
wire pc_w_lat_scanout;


input		l2clk;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input 		scan_in;

input		tcu_shscan_clk_stop;	// To be synchronized

input		trl1_shscanid_2;

input	[1:0]	fls_ss_update_pc_w;

input	[47:2]	pct0_shadow_pc_d;
input	[47:2]	pct1_shadow_pc_d;

// NOT SHADOW SCAN, but debug
input		fls0_spc_hardstop_request;
input		fls0_spc_softstop_request;
input		fls0_spc_trigger_pulse;
input		fls1_spc_hardstop_request;
input		fls1_spc_softstop_request;
input		fls1_spc_trigger_pulse;


output		scan_out;

output 		sse_shscan_clk_stop;

output	[47:2]	sse_shadow_pc;

output		tlu_hardstop_request;
output		tlu_softstop_request;
output		tlu_trigger_pulse;


//////////////////////////////////////////////////////////////////////

assign stop	= 1'b0;
assign en	= 1'b1;
assign clk	= l2clk;

tlu_sse_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);


//////////////////////////////////////////////////////////////////////
//
// Stage PC to W
//

tlu_sse_dp_msff_macro__left_14__mux_aope__ports_2__stack_60c__width_46 pc_e_lat      (
	.scan_in(pc_e_lat_scanin),
	.scan_out(pc_e_lat_scanout),
	.din1	(pct0_shadow_pc_d	[47:2]	),
	.din0	(pct1_shadow_pc_d	[47:2]	),
	.sel0	(trl1_shscanid_2		),
	.dout	(pc_e			[47:2]	),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_sse_dp_msff_macro__left_14__stack_60c__width_46 pc_m_lat    (
	.scan_in(pc_m_lat_scanin),
	.scan_out(pc_m_lat_scanout),
	.din	(pc_e			[47:2]	),
	.dout	(pc_m			[47:2]	),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_sse_dp_msff_macro__left_12__stack_60c__width_48 pc_b_lat    (
	.scan_in(pc_b_lat_scanin),
	.scan_out(pc_b_lat_scanout),
	.din	({pc_m			[47:2],
		  tcu_shscan_clk_stop	       ,
		  shscan_clk_stop_in	       }),
	.dout	({pc_b			[47:2],
		  shscan_clk_stop_in	       ,
		  sse_shscan_clk_stop	       }),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_sse_dp_msff_macro__left_14__mux_aope__ports_3__stack_60c__width_46 pc_w_lat      (
	.scan_in(pc_w_lat_scanin),
	.scan_out(pc_w_lat_scanout),
	.din0	(pc_b			[47:2]	),
	.din1	(pc_b			[47:2]	),
	.din2	(sse_shadow_pc		[47:2]	),
	.sel0	(fls_ss_update_pc_w	[0   ]	),
	.sel1	(fls_ss_update_pc_w	[1   ]	),
	.dout	(sse_shadow_pc		[47:2]	),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


//////////////////////////////////////////////////////////////////////////////
// OR the stop requests and trigger pulses
//

tlu_sse_dp_or_macro__ports_2__stack_60c__width_3 debug_or    (
	.din0	({fls0_spc_hardstop_request    ,
		  fls0_spc_softstop_request    ,
		  fls0_spc_trigger_pulse       }),
	.din1	({fls1_spc_hardstop_request    ,
		  fls1_spc_softstop_request    ,
		  fls1_spc_trigger_pulse       }),
	.dout	({tlu_hardstop_request	       ,
		  tlu_softstop_request	       ,
		  tlu_trigger_pulse	       })
);


// fixscan start:
assign pc_e_lat_scanin           = scan_in                  ;
assign pc_m_lat_scanin           = pc_e_lat_scanout         ;
assign pc_b_lat_scanin           = pc_m_lat_scanout         ;
assign pc_w_lat_scanin           = pc_b_lat_scanout         ;
assign scan_out                  = pc_w_lat_scanout         ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module tlu_sse_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_sse_dp_msff_macro__left_14__mux_aope__ports_2__stack_60c__width_46 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [45:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [44:0] so;

  input [45:0] din0;
  input [45:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [45:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(46)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[45:0]),
  .in1(din1[45:0]),
.dout(muxout[45:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(46)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[45:0]),
.si({scan_in,so[44:0]}),
.so({so[44:0],scan_out}),
.q(dout[45:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_sse_dp_msff_macro__left_14__stack_60c__width_46 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [44:0] so;

  input [45:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [45:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(46)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[45:0]),
.si({scan_in,so[44:0]}),
.so({so[44:0],scan_out}),
.q(dout[45:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_sse_dp_msff_macro__left_12__stack_60c__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_sse_dp_msff_macro__left_14__mux_aope__ports_3__stack_60c__width_46 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire [45:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [44:0] so;

  input [45:0] din0;
  input [45:0] din1;
  input [45:0] din2;
  input sel0;
  input sel1;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [45:0] dout;


  output scan_out;


cl_dp1_penc3_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2)
);

mux3s #(46)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[45:0]),
  .in1(din1[45:0]),
  .in2(din2[45:0]),
.dout(muxout[45:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(46)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[45:0]),
.si({scan_in,so[44:0]}),
.so({so[44:0],scan_out}),
.q(dout[45:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_sse_dp_or_macro__ports_2__stack_60c__width_3 (
  din0, 
  din1, 
  dout);
  input [2:0] din0;
  input [2:0] din1;
  output [2:0] dout;


or2 #(3)  d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_tel_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_tel_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  trl_tel_en, 
  asi_mbist_tel_en, 
  ted_syndrome, 
  tsa_ecc, 
  ted0_cecc_err, 
  ted0_uecc_err, 
  ted0_uecc_err_, 
  ted1_cecc_err, 
  ted1_uecc_err, 
  ted1_uecc_err_, 
  trl_tsacu_en_in, 
  scan_out, 
  tel_syndrome, 
  tel_ecc, 
  tel_crit_ecc, 
  tel_tsac, 
  tel_tsau, 
  tel_tsacu_exc, 
  tel_tsac_exc, 
  tel_tsau_exc);
wire pce_ov;
wire clk;
wire stop;
wire siclk;
wire soclk;
wire se;
wire en;
wire [15:0] tsa_ecc_minbuf;
wire [3:0] trl_tsacu_en_in_minbuf;
wire ecc_lat_scanin;
wire ecc_lat_scanout;
wire tsac_in;
wire tsau_in;
wire [15:0] rd_ecc;
wire [3:0] tsacu_en;
wire tsac;
wire tsau;
wire cecc_or_;
wire [3:0] tsac_exc_;
wire [3:0] tsau_exc_;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input		trl_tel_en;
input		asi_mbist_tel_en;

input	[15:0]	ted_syndrome;
input	[15:0]	tsa_ecc;

input		ted0_cecc_err;
input		ted0_uecc_err;
input		ted0_uecc_err_;
input		ted1_cecc_err;
input		ted1_uecc_err;
input		ted1_uecc_err_;

input	[3:0] trl_tsacu_en_in;


output		scan_out;

output	[15:0]	tel_syndrome;
output	[15:0]	tel_ecc;
output	[15:0]	tel_crit_ecc;

output		tel_tsac;
output		tel_tsau;

output	[3:0]	tel_tsacu_exc;
output	[3:0]	tel_tsac_exc;
output	[3:0]	tel_tsau_exc;


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign clk      = l2clk;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;


////////////////////////////////////////////////////////////////////////////////
// Clock enable

tlu_tel_dp_or_macro__ports_2__width_1 en_or   (
	.din0	(trl_tel_en		),
	.din1	(asi_mbist_tel_en	),
	.dout	(en			)
);

// Data is flopped, but ECC is not,  so flop here

tlu_tel_dp_buff_macro__minbuff_1__width_20 ecc_lat_minbuff  (
	.din	({tsa_ecc		[15:0],
		  trl_tsacu_en_in	[3:0]}),
	.dout	({tsa_ecc_minbuf	[15:0],
		  trl_tsacu_en_in_minbuf[3:0]}));


tlu_tel_dp_msff_macro__width_38 ecc_lat  (
	.scan_in(ecc_lat_scanin),
	.scan_out(ecc_lat_scanout),
	.din	({tsa_ecc_minbuf	[15:0],
		  trl_tsacu_en_in_minbuf[3:0],
		  tsac_in		       ,
		  tsau_in		       ,
		  ted_syndrome		[15:0]}),
	.dout	({rd_ecc		[15:0],
		  tsacu_en		[3:0],
		  tsac			       ,
		  tsau			       ,
		  tel_syndrome		[15:0]}),
  .clk(clk),
  .en(en),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

assign tel_crit_ecc[15:0] =
       rd_ecc[15:0];

tlu_tel_dp_buff_macro__rep_1__width_16 ecc_buf   (
	.din	(rd_ecc			[15:0]	),
	.dout	(tel_ecc		[15:0]	)
);


tlu_tel_dp_nand_macro__ports_2__width_1 tsau_in_nand   (
	.din0	(ted0_uecc_err_			),
	.din1	(ted1_uecc_err_			),
	.dout	(tsau_in			)
);

tlu_tel_dp_nor_macro__ports_2__width_1 cecc_or_inv_nor   (
	.din0	(ted0_cecc_err			),
	.din1	(ted1_cecc_err			),
	.dout	(cecc_or_			)
);

tlu_tel_dp_nor_macro__ports_3__width_1 tsac_in_nor   (
	.din0	(cecc_or_			),
	.din1	(ted0_uecc_err			),
	.din2	(ted1_uecc_err			),
	.dout	(tsac_in			)
);

tlu_tel_dp_buff_macro__rep_1__width_1 tsac_buf   (
	.din	(tsac				),
	.dout	(tel_tsac			)
);

tlu_tel_dp_buff_macro__rep_1__width_1 tsau_buf   (
	.din	(tsau				),
	.dout	(tel_tsau			)
);


tlu_tel_dp_nand_macro__ports_2__width_4 tsac_exc_b_nand   (
	.din0	({4 {tsac}}			),
	.din1	(tsacu_en		[3:0]	),
	.dout	(tsac_exc_		[3:0]	)
);

tlu_tel_dp_nand_macro__ports_2__width_4 tsau_exc_b_nand   (
	.din0	({4 {tsau}}			),
	.din1	(tsacu_en		[3:0]	),
	.dout	(tsau_exc_		[3:0]	)
);

tlu_tel_dp_inv_macro__width_4 tsac_exc_inv  (
	.din	(tsac_exc_		[3:0]	),
	.dout	(tel_tsac_exc		[3:0]	)
);

tlu_tel_dp_inv_macro__width_4 tsau_exc_inv  (
	.din	(tsau_exc_		[3:0]	),
	.dout	(tel_tsau_exc		[3:0]	)
);

tlu_tel_dp_nand_macro__ports_2__width_4 tsacu_exc_nand   (
	.din0	(tsac_exc_		[3:0]	),
	.din1	(tsau_exc_		[3:0]	),
	.dout	(tel_tsacu_exc		[3:0]	)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power

// fixscan start:
assign ecc_lat_scanin            = scan_in                  ;
assign scan_out                  = ecc_lat_scanout          ;
// fixscan end:
endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_tel_dp_or_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tel_dp_buff_macro__minbuff_1__width_20 (
  din, 
  dout);
  input [19:0] din;
  output [19:0] dout;


buff #(20)  d0_0 (
.in(din[19:0]),
.out(dout[19:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tel_dp_msff_macro__width_38 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [36:0] so;

  input [37:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [37:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(38)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[37:0]),
.si({scan_in,so[36:0]}),
.so({so[36:0],scan_out}),
.q(dout[37:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tel_dp_buff_macro__rep_1__width_16 (
  din, 
  dout);
  input [15:0] din;
  output [15:0] dout;


buff #(16)  d0_0 (
.in(din[15:0]),
.out(dout[15:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_tel_dp_nand_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nand2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module tlu_tel_dp_nor_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module tlu_tel_dp_nor_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


nor3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tel_dp_buff_macro__rep_1__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module tlu_tel_dp_nand_macro__ports_2__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


nand2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//
//   invert macro
//
//


module tlu_tel_dp_inv_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_tic_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_tic_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  cmp_tick_enable, 
  asi_rd_tick, 
  asi_wr_tick, 
  asi_tca_addr, 
  asi_tca_addr_valid, 
  asi_tca_wr, 
  asi_wr_data, 
  asi_mbist_run, 
  asi_mbist_cmpsel, 
  tca_cmpr_data_in, 
  cel_ecc, 
  exu_address0_e, 
  exu_address1_e, 
  scan_out, 
  tic_cmpr_addr, 
  tic_cmpr_wr_en, 
  tic_cmpr_rd_en, 
  tic_asi_data, 
  tic_cmpr_data, 
  tic_addr, 
  tic_not_valid, 
  tic_match, 
  tic_mbist_data, 
  tic_exu_address0_m, 
  tic_exu_address1_m, 
  tic_exu_address0_b, 
  tic_exu_address1_b);
wire clk;
wire stop;
wire test;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire [62:0] wr_data;
wire tick_enable;
wire tick_en;
wire tick_lat_scanin;
wire tick_lat_scanout;
wire [62:0] tick_in;
wire [62:0] tick;
wire [17:16] unused;
wire [4:0] cmpr_addr_in;
wire cmpr_wr_en_in;
wire cmpr_rd_en_in;
wire cmpr_addr_lat_scanin;
wire cmpr_addr_lat_scanout;
wire [4:0] cmpr_addr;
wire cmpr_wr_en;
wire cmpr_data_lat_scanin;
wire cmpr_data_lat_scanout;
wire [63:0] cmpr_data;
wire [63:0] asi_data;
wire cmpsel_lat_scanin;
wire cmpsel_lat_scanout;
wire [1:0] cmpsel;
wire tcu_muxtest_rep0;
wire [31:0] mbist_data;
wire address0_m_lat_scanin;
wire address0_m_lat_scanout;
wire [1:0] address0_m;
wire address1_m_lat_scanin;
wire address1_m_lat_scanout;
wire [1:0] address1_m;


input 		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		tcu_dectest;
input		tcu_muxtest;

// TICK register enable
input 		cmp_tick_enable;

input		asi_rd_tick;
input		asi_wr_tick;

input	[4:0]	asi_tca_addr;
input		asi_tca_addr_valid;
input 		asi_tca_wr;
input	[62:0]	asi_wr_data;
input		asi_mbist_run;		// MBIST
input	[1:0]	asi_mbist_cmpsel;	// MBIST

input	[63:0]	tca_cmpr_data_in;

input	[7:0]	cel_ecc;		// MBIST

input	[47:0]	exu_address0_e;		// For PCT but here for placement
input	[47:0]	exu_address1_e;		// For PCT but here for placement


output		scan_out;

output	[4:0]	tic_cmpr_addr;
output		tic_cmpr_wr_en;
output		tic_cmpr_rd_en;

output 	[63:0]	tic_asi_data;
output 	[63:0]	tic_cmpr_data;

output	[4:0]	tic_addr;
output		tic_not_valid;
output		tic_match;

output	[31:0]	tic_mbist_data;		// MBIST

output	[47:2]	tic_exu_address0_m;	// For PCT but here for placement
output	[47:2]	tic_exu_address1_m;	// For PCT but here for placement
output	[1:0]	tic_exu_address0_b;	// For DFD
output	[1:0]	tic_exu_address1_b;	// For DFD


// 0in bits_on -var {asi_wr_tick, asi_tca_wr} -max 1 -message "Writing TICK and CMPR at same time"
// 0in constant -var (asi_tca_wr & !asi_tca_addr_valid) -message "CMPR write valid without valid address"


////////////////////////////////////////////////////////////////////////////////

assign clk	= l2clk;
assign stop	= 1'b0;
assign test     = tcu_dectest;

tlu_tic_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);


// Since bit 63 of the TICK and CMPR registers is stored negative active,
// need to invert write data and read data in tlu_asi_ctl

assign wr_data[62:0] =
       asi_wr_data[62:0];


///////////////////////////////////////////////////////////////////////////////
// Tick register
// TICK.NPT (bit 63) is stored in tlu_asi_ctl and 
// has POR value of 1

tlu_tic_dp_or_macro__ports_2__width_1 tick_en_or   (
	.din0	(asi_wr_tick			),
	.din1	(tick_enable			),
	.dout	(tick_en			)
);

tlu_tic_dp_msff_macro__mux_aope__ports_2__width_63 tick_lat    (	
	.scan_in(tick_lat_scanin),
	.scan_out(tick_lat_scanout),
	.en	(tick_en			),
	.din0	(wr_data		[62:0]	),
	.din1	(tick_in		[62:0]	),
	.sel0	(asi_wr_tick			),
	.dout	(tick			[62:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tic_dp_increment_macro__width_64 tick_inc  (
	.cin	(1'b1				),
	.din	({1'b0			       ,
		  tick			[62:0]}),
	.cout	(unused			[17   ]	),
	.dout	({unused		[16   ],
		  tick_in		[62:0]})
);

tlu_tic_dp_mux_macro__mux_pgpe__ports_2__width_6 cmpr_addr_mux    (
	.din0	({asi_tca_addr		[4:0],	
		  asi_tca_wr		       }),
	.din1	({tick			[6:2],
		  1'b0			       }),
	.sel0	(asi_tca_addr_valid		),
	.dout	({cmpr_addr_in		[4:0],
		  cmpr_wr_en_in		       })
);

tlu_tic_dp_inv_macro__width_1 cmpr_rd_en_in_inv  (
	.din	(cmpr_wr_en_in			),
	.dout	(cmpr_rd_en_in			)
);

assign tic_cmpr_addr[4:0] = 
       cmpr_addr_in[4:0];

assign tic_cmpr_wr_en =
       cmpr_wr_en_in;

assign tic_cmpr_rd_en =
       cmpr_rd_en_in;

tlu_tic_dp_msff_macro__width_13 cmpr_addr_lat  (
	.scan_in(cmpr_addr_lat_scanin),
	.scan_out(cmpr_addr_lat_scanout),
	.en	(1'b1				),
	.din	({cmp_tick_enable	       ,
		  cmpr_addr_in		[4:0],	
		  cmpr_wr_en_in		       ,
		  cmpr_addr		[4:0],
		  cmpr_wr_en		       }),
	.dout	({tick_enable		       ,
		  cmpr_addr		[4:0],
		  cmpr_wr_en		       ,
		  tic_addr		[4:0],
		  tic_not_valid		       }),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tic_dp_msff_macro__minbuff_1__width_64 cmpr_data_lat  (
	.scan_in(cmpr_data_lat_scanin),
	.scan_out(cmpr_data_lat_scanout),
	.en	(1'b1				),
	.din	(tca_cmpr_data_in	[63:0]	),
	.dout	(cmpr_data		[63:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)	
);

assign tic_cmpr_data[63:0] =
       cmpr_data[63:0];


///////////////////////////////////////////////////////////////////////////////
// Comparison
// Have to ignore 7 bits because
// - 5 bits for 8 threads x 3 cmpr regs per thread (round to 4)
// - 1 bit for ASI reads or writes
// - 1 more bit because ASI reads and writes are in different ASI pipe stages

tlu_tic_dp_cmp_macro__width_64 tick_cmp  (
	.din0	({cmpr_data		[63:7],
		  {7 {1'b0}}		       }),
 // INTDIS is stored negative active (effectively an interrupt enable), 
 // so compare when INTDIS is 1
	.din1	({1'b1			       ,
		  tick			[62:7],
		  {7 {1'b0}}		       }),
	.dout	(tic_match			)
);


///////////////////////////////////////////////////////////////////////////////
// ASI reads
// Note that bit 63 is inverted!

tlu_tic_dp_mux_macro__dmux_8x__mux_aope__ports_2__width_64 asi_lat     (
	.din0	({1'b0			       ,
		  tick			[62:0]}),
	.din1	(cmpr_data		[63:0]	),
	.sel0	(asi_rd_tick			),
	.dout	(asi_data		[63:0]	)
);

assign tic_asi_data[63:0] =
       asi_data[63:0];


///////////////////////////////////////////////////////////////////////////////
// MBIST muxing

tlu_tic_dp_msff_macro__width_2 cmpsel_lat  (
	.scan_in(cmpsel_lat_scanin),
	.scan_out(cmpsel_lat_scanout),
	.en	(asi_mbist_run			),
	.din	(asi_mbist_cmpsel	[1:0]	),
	.dout	(cmpsel			[1:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tic_dp_buff_macro__dbuff_32x__width_1 tst_mux_rep0   (
	.din	(tcu_muxtest			),
	.dout	(tcu_muxtest_rep0		)
);

tlu_tic_dp_mux_macro__mux_pgpe__ports_3__width_32 mbist_mux    (
	.din0	(cmpr_data		[31:0]	),
	.din1	(cmpr_data		[63:32]	),
	.din2	({4 {cel_ecc		[7:0]}}),
	.sel0	(cmpsel			[0   ]	),
	.sel1	(cmpsel			[1   ]	),
	.muxtst	(tcu_muxtest_rep0		),
	.dout	(mbist_data		[31:0]	),
  .test(test)
);

assign tic_mbist_data[31:0] =
       mbist_data[31:0];


///////////////////////////////////////////////////////////////////////////////
// Flop EXU address for PCT

tlu_tic_dp_msff_macro__width_50 address0_m_lat  (
	.scan_in(address0_m_lat_scanin),
	.scan_out(address0_m_lat_scanout),
	.en	(1'b1				),
	.din	({exu_address0_e	[47:0],
		  address0_m		[1:0]}),
	.dout	({tic_exu_address0_m	[47:2],
		  address0_m		[1:0],
		  tic_exu_address0_b	[1:0]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tic_dp_msff_macro__width_50 address1_m_lat  (
	.scan_in(address1_m_lat_scanin),
	.scan_out(address1_m_lat_scanout),
	.en	(1'b1				),
	.din	({exu_address1_e	[47:0],
		  address1_m		[1:0]}),
	.dout	({tic_exu_address1_m	[47:2],
		  address1_m		[1:0],
		  tic_exu_address1_b	[1:0]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


// fixscan start:
assign tick_lat_scanin           = scan_in                  ;
assign cmpr_addr_lat_scanin      = tick_lat_scanout         ;
assign cmpr_data_lat_scanin      = cmpr_addr_lat_scanout    ;
assign cmpsel_lat_scanin         = cmpr_data_lat_scanout    ;
assign address0_m_lat_scanin     = cmpsel_lat_scanout       ;
assign address1_m_lat_scanin     = address0_m_lat_scanout   ;
assign scan_out                  = address1_m_lat_scanout   ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module tlu_tic_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_tic_dp_or_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tic_dp_msff_macro__mux_aope__ports_2__width_63 (
  din0, 
  din1, 
  sel0, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire [62:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [61:0] so;

  input [62:0] din0;
  input [62:0] din1;
  input sel0;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [62:0] dout;


  output scan_out;


cl_dp1_penc2_8x  c1_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(63)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[62:0]),
  .in1(din1[62:0]),
.dout(muxout[62:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(63)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[62:0]),
.si({scan_in,so[61:0]}),
.so({so[61:0],scan_out}),
.q(dout[62:0])
);


endmodule


//
//   increment macro 
//
//


module tlu_tic_dp_increment_macro__width_64 (
  din, 
  cin, 
  dout, 
  cout);
  input [63:0] din;
  input cin;
  output [63:0] dout;
  output cout;


incr #(64)  m0_0 (
.cin(cin),
.in(din[63:0]),
.out(dout[63:0]),
.cout(cout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tic_dp_mux_macro__mux_pgpe__ports_2__width_6 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0_unused;
wire psel1;

  input [5:0] din0;
  input [5:0] din1;
  input sel0;
  output [5:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0_unused),
 .psel1(psel1)
);

mux2e #(6)  d0_0 (
  .sel(psel1),
  .in0(din0[5:0]),
  .in1(din1[5:0]),
.dout(dout[5:0])
);


endmodule


//
//   invert macro
//
//


module tlu_tic_dp_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tic_dp_msff_macro__width_13 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [11:0] so;

  input [12:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [12:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(13)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[12:0]),
.si({scan_in,so[11:0]}),
.so({so[11:0],scan_out}),
.q(dout[12:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tic_dp_msff_macro__minbuff_1__width_64 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [62:0] so;

  input [63:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [63:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[63:0]),
.si({scan_in,so[62:0]}),
.so({so[62:0],scan_out}),
.q(dout[63:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module tlu_tic_dp_cmp_macro__width_64 (
  din0, 
  din1, 
  dout);
  input [63:0] din0;
  input [63:0] din1;
  output dout;


cmp #(64)  m0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tic_dp_mux_macro__dmux_8x__mux_aope__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tic_dp_msff_macro__width_2 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [0:0] so;

  input [1:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [1:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tic_dp_buff_macro__dbuff_32x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tic_dp_mux_macro__mux_pgpe__ports_3__width_32 (
  din0, 
  din1, 
  din2, 
  sel0, 
  sel1, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input sel0;
  input sel1;
  input muxtst;
  input test;
  output [31:0] dout;


cl_dp1_penc3_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
  .test(test)
);

mux3 #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
.dout(dout[31:0]),
  .muxtst(muxtst)
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tic_dp_msff_macro__width_50 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [48:0] so;

  input [49:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [49:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(50)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[49:0]),
.si({scan_in,so[48:0]}),
.so({so[48:0],scan_out}),
.q(dout[49:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_trl_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_trl_ctl (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  lsu_tlu_pmen, 
  tcu_shscanid, 
  tcu_ss_mode, 
  tcu_do_mode, 
  thread_group, 
  mbi_run, 
  ftu_ifu_quiesce, 
  pku_quiesce, 
  exu_tlu_window_block, 
  lsu_stb_empty, 
  fgu_fpx_ieee_trap_fw, 
  fgu_fpd_ieee_trap_fw, 
  fgu_fpx_unfin_fw, 
  fgu_fpd_unfin_fw, 
  fgu_fpd_idiv0_trap_fw, 
  fgu_fpx_trap_tid_fw, 
  fgu_fpd_trap_tid_fw, 
  mmu_write_itlb, 
  mmu_reload_done, 
  mmu_i_unauth_access, 
  mmu_i_tsb_miss, 
  mmu_d_tsb_miss, 
  mmu_i_tte_outofrange, 
  mmu_d_tte_outofrange, 
  spu_pmu_ma_busy, 
  spu_tlu_cwq_busy, 
  spu_tlu_ma_int_req, 
  fls_wstate0, 
  fls_wstate1, 
  fls_wstate2, 
  fls_wstate3, 
  fls_tcc_number_0, 
  fls_tcc_number_1, 
  fls_tcc_number_2, 
  fls_tcc_number_3, 
  fls_tid_d, 
  fls_tid_dec_w_in, 
  fls_por_request, 
  fls_xir_request, 
  fls_ivt_request, 
  fls_sir_request, 
  fls_itm_request, 
  fls_iln_request, 
  fls_hst_request, 
  fls_tlz_request, 
  fls_sma_request, 
  fls_cwq_request, 
  fls_ade_request, 
  fls_iae_request, 
  fls_ipe_request, 
  fls_ipv_request, 
  fls_inp_request, 
  fls_iar_request, 
  fls_irr_request, 
  fls_mar_request, 
  fls_mrr_request, 
  fls_pro_request, 
  fls_ill_request, 
  fls_don_request, 
  fls_ret_request, 
  fls_fpd_request, 
  fls_snn_request, 
  fls_sno_request, 
  fls_fnn_request, 
  fls_fno_request, 
  fls_clw_request, 
  fls_dtm_request, 
  fls_ldf_request, 
  fls_stf_request, 
  fls_dap_request, 
  fls_vaw_request, 
  fls_iaw_request, 
  fls_paw_request, 
  fls_maa_request, 
  fls_fpe_request, 
  fls_fei_request, 
  fls_fof_request, 
  fls_pra_request, 
  fls_dia_request, 
  fls_ups_request, 
  fls_dpv_request, 
  fls_dnc_request, 
  fls_dnf_request, 
  fls_dso_request, 
  fls_tof_request, 
  fls_dbz_request, 
  fls_tcc_request, 
  fls_dae_request, 
  fls_lsr_request, 
  fls_irt_request, 
  fls_drt_request, 
  fls_pmu_request, 
  fls_mqr_request, 
  fls_dqr_request, 
  fls_rqr_request, 
  fls_idl_request, 
  fls_res_request, 
  fls_ssr_request, 
  fls_ssc_request, 
  fls_nns_request, 
  fls_ime_request, 
  fls_dme_request, 
  fls_eer_request, 
  fls_icp_request, 
  fls_ftt_request, 
  fls_ibp_request, 
  fls_tct_request, 
  fls_ref_request, 
  fls_pc_valid, 
  pmu_tlu_trap_m, 
  fls_trl_l1en, 
  fls_core_running, 
  tlu_flush_ifu, 
  pct_npc_is_nonseq, 
  trlx_itw_wait, 
  trlx_itw_last, 
  tsa_gl, 
  tsa_tnpc_nonseq, 
  tel_tsacu_exc, 
  tlu_ceter_de, 
  tlu_ceter_pscce, 
  tsd_hpstate_red, 
  tsd_hpstate_hpriv, 
  tsd_hpstate_tlz, 
  tsd_pstate_ie, 
  tsd_pstate_am, 
  tsd_htstate_hpriv, 
  tic_addr, 
  tic_not_valid, 
  tic_match, 
  cel_tccd, 
  cel_tcud, 
  asi_tsa_rd_addr, 
  asi_tsa_rd_iqr_ecc, 
  asi_tsa_tid, 
  asi_rd_tl, 
  asi_wr_tl, 
  asi_rd_pil, 
  asi_wr_pil, 
  asi_rd_gl, 
  asi_wr_gl, 
  asi_wr_set_softint, 
  asi_wr_clear_softint, 
  asi_rd_softint, 
  asi_wr_softint, 
  asi_rd_hintp, 
  asi_wr_hintp, 
  asi_wr_data, 
  asi_preempt_trap, 
  asi_preempt_done_retry, 
  asi_rmw_tsa, 
  asi_wr_asireg, 
  asi_trl_pstate_en, 
  asi_mbist_addr, 
  asi_mbist_tsa_rd_en, 
  asi_mbist_tsa_wr_en, 
  scan_out, 
  wmr_scan_out, 
  spc_core_running_status, 
  trl_core_running_status, 
  trl_pil_mask_15, 
  trl_iln_exc, 
  trl_hstick_match, 
  trl_unhalt_, 
  trl_tlz_exc, 
  trl_nns_exc, 
  trl_ssc_exc, 
  trl_take_sma, 
  trl_take_cwq, 
  trl_take_xir, 
  trl_take_ftt, 
  trl_pc_sel_trap_pc, 
  trl_npc_sel_trap_npc, 
  trl_npc_sel_tnpc, 
  trl_invalidate_pc, 
  trl_invalidate_npc, 
  trl_trap_type, 
  trl_tsa_trap_type, 
  trl_asireg_sel, 
  trl_asireg_en, 
  trl_thread_sel, 
  trl_tba_sel, 
  trl_pstate_thread_sel, 
  trl_don_ret_pstate_sel, 
  trl_pstate_en, 
  trl_pc_thread_sel, 
  trl_pc_pstate_am_, 
  trl_pc_sel_pc, 
  trl_pc_sel_npc, 
  trl_pc_sel_trap, 
  trl_pc_sel_reset, 
  trl_pc_done, 
  trl_pc_retry, 
  trl_pc_tte, 
  trl_pct_trap_pc_en, 
  trl_pct_tnpc_en, 
  trl_stay_in_priv, 
  trl_reset_trap, 
  trl_other_trap, 
  trl_tl_gt_0, 
  trl_tl_eq_0, 
  trl_tsa_wr_en, 
  trl_tsa_rd_en, 
  trl_tsa_wr_addr, 
  trl_tsa_rd_addr, 
  trl_save_tsa, 
  trl_tsd_tsa_en, 
  trl_tsd_tsa_wd_en, 
  trl_capture_ss, 
  trl_rmw_tsa, 
  trl_tsa_gl, 
  trl_asi_data, 
  trl_ss_complete, 
  trl_itw_wait, 
  trl_itw_last, 
  trl_shscanid, 
  trl_shscanid_2, 
  trl_shadow_tl, 
  trl_tl_for_tt, 
  trl_fls_npc_en, 
  trl_tel_en, 
  trl_trap_taken, 
  trl_gl0, 
  trl_gl1, 
  trl_gl2, 
  trl_gl3, 
  trl_tsacu_en_in, 
  tlu_tsa_index, 
  tlu_tccd, 
  tlu_tcud, 
  tlu_tca_index, 
  tlu_window_block, 
  tlu_trap_pc_valid, 
  tlu_retry, 
  tlu_ifu_invalidate, 
  tlu_trap_tid, 
  tlu_itlb_reload, 
  tlu_ccr_cwp_valid, 
  tlu_ccr_cwp_tid, 
  tlu_asi_valid, 
  tlu_asi_tid, 
  tlu_gl0, 
  tlu_gl1, 
  tlu_gl2, 
  tlu_gl3, 
  tlu_tl_gt_0, 
  tlu_mmu_tl_gt_0, 
  tlu_release_tte, 
  tlu_lsu_clear_ctl_reg_, 
  tlu_pmu_trap_taken, 
  tlu_pmu_trap_mask_e);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire [2:0] maxtl;
wire [2:0] maxptl;
wire [2:0] maxtl_minus_one;
wire [1:0] maxgl;
wire l1clk;
wire [3:0] thread_active;
wire [3:0] core_running_status;
wire [3:0] clear_l1en_per_thread_int;
wire [3:0] trap_taken0;
wire take_itw_last;
wire suppress_don_ret_taken_;
wire flush_ifu_last_lat_scanin;
wire flush_ifu_last_lat_scanout;
wire [3:0] flush_ifu_last;
wire [3:0] l1en_per_thread_int_in;
wire [3:0] l1en_per_thread_int;
wire l1en_per_thread_int_lat_scanin;
wire l1en_per_thread_int_lat_scanout;
wire [3:0] l1en_don_ret_in;
wire take_don_last;
wire take_ret_last;
wire l1en_don_ret_lat_scanin;
wire l1en_don_ret_lat_scanout;
wire [3:0] l1en_don_ret;
wire [3:0] l1en_per_thread;
wire l1clk_pm4;
wire l1clk_pm3;
wire l1clk_pm2;
wire l1clk_pm1;
wire tid_dec_w_lat_scanin;
wire tid_dec_w_lat_scanout;
wire [3:0] tid_dec_w;
wire cwq_busy_in;
wire cwq_busy_lat_scanin;
wire cwq_busy_lat_scanout;
wire cwq_busy;
wire [3:0] cwq_interlock_;
wire [3:0] quiesced_in;
wire [3:0] stb_empty;
wire [3:0] i_quiesce;
wire [3:0] p_quiesce;
wire [3:0] ma_idle;
wire [3:0] pitw_req_in;
wire quiesced_last_lat_scanin;
wire quiesced_last_lat_scanout;
wire [3:0] quiesced;
wire [3:0] quiesced_last;
wire [3:0] pidl_req_in;
wire [3:0] idl_req;
wire [3:0] idl_req_in;
wire idl_req_lat_scanin;
wire idl_req_lat_scanout;
wire i_quiesce_lat_scanin;
wire i_quiesce_lat_scanout;
wire p_quiesce_lat_scanin;
wire p_quiesce_lat_scanout;
wire ma_busy_lat_scanin;
wire ma_busy_lat_scanout;
wire ma_busy;
wire [2:0] ma_tid;
wire [3:0] core_running_status_in;
wire [3:0] trap_por_res_ssr;
wire core_running_status_lat_scanin;
wire core_running_status_lat_scanout;
wire [3:0] ever_been_running_in;
wire [3:0] ever_been_running;
wire ever_been_running_lat_scanin;
wire ever_been_running_lat_scanout;
wire [3:0] pdisrupting_req;
wire [3:0] disrupting_req;
wire [3:0] por_req_in;
wire [3:0] por_req;
wire [3:0] por_req_in_ntt;
wire por_req_lat_scanin;
wire por_req_lat_scanout;
wire [3:0] pxir_req_in;
wire [3:0] xir_req;
wire [3:0] xir_req_in;
wire [3:0] pxir_req_in_ntt;
wire xir_req_lat_scanin;
wire xir_req_lat_scanout;
wire [3:0] peer_req_in;
wire [3:0] eer_req;
wire [3:0] eer_req_in;
wire [3:0] peer_req_in_ntt;
wire eer_req_lat_scanin;
wire eer_req_lat_scanout;
wire [3:0] icp_req_in;
wire [3:0] icp_req;
wire [3:0] icp_req_in_ntt;
wire icp_req_lat_scanin;
wire icp_req_lat_scanout;
wire [3:0] pftt_req_in;
wire [3:0] ftt_req;
wire [3:0] ftt_req_in;
wire [3:0] pftt_req_in_ntt;
wire ftt_req_lat_scanin;
wire ftt_req_lat_scanout;
wire [3:0] pivt_req_in;
wire [3:0] ivt_req;
wire [3:0] ivt_req_in;
wire [3:0] stb_wait;
wire [3:0] pivt_req_in_ntt;
wire ivt_req_lat_scanin;
wire ivt_req_lat_scanout;
wire [3:0] pmqr_req_in;
wire [3:0] mqr_req;
wire [3:0] mqr_req_in;
wire [3:0] pmqr_req_in_ntt;
wire mqr_req_lat_scanin;
wire mqr_req_lat_scanout;
wire [3:0] pdqr_req_in;
wire [3:0] dqr_req;
wire [3:0] dqr_req_in;
wire [3:0] pdqr_req_in_ntt;
wire dqr_req_lat_scanin;
wire dqr_req_lat_scanout;
wire [3:0] prqr_req_in;
wire [3:0] rqr_req;
wire [3:0] rqr_req_in;
wire [3:0] prqr_req_in_ntt;
wire rqr_req_lat_scanin;
wire rqr_req_lat_scanout;
wire [3:0] pres_req_in;
wire [3:0] res_req;
wire [3:0] res_req_in;
wire [3:0] pres_req_in_ntt;
wire res_req_lat_scanin;
wire res_req_lat_scanout;
wire [3:0] pssr_req_in;
wire [3:0] ssr_req;
wire [3:0] ssr_req_in;
wire [3:0] ssr_req_in_for_taken;
wire [3:0] pssr_req_in_ntt;
wire take_ssr_last;
wire ssr_req_lat_scanin;
wire ssr_req_lat_scanout;
wire [3:0] ssc_req_in;
wire [3:0] ssc_req;
wire [3:0] fei_or_fof_incoming;
wire ssc_req_lat_scanin;
wire ssc_req_lat_scanout;
wire [3:0] pnns_req_in;
wire [3:0] nns_req;
wire [3:0] nns_req_in;
wire [3:0] pnns_req_in_ntt;
wire nns_req_lat_scanin;
wire nns_req_lat_scanout;
wire [3:0] psir_req_in;
wire [3:0] sir_req;
wire [3:0] sir_req_in;
wire [3:0] psir_req_in_ntt;
wire sir_req_lat_scanin;
wire sir_req_lat_scanout;
wire [3:0] pitm_req_in;
wire [3:0] itm_req;
wire [3:0] itm_req_in;
wire [3:0] irt_req_in;
wire [3:0] tlz_req_in;
wire [3:0] pmu_req_in;
wire [3:0] pitm_req_in_ntt;
wire itm_req_lat_scanin;
wire itm_req_lat_scanout;
wire i_tte_outofrange_lat_scanin;
wire i_tte_outofrange_lat_scanout;
wire [3:0] i_tte_outofrange;
wire [3:0] piit_req_in;
wire [3:0] iit_req;
wire [3:0] iit_req_in;
wire [3:0] piit_req_in_ntt;
wire iit_req_lat_scanin;
wire iit_req_lat_scanout;
wire [3:0] piln_req_in;
wire [3:0] iln_req;
wire [3:0] iln_req_in;
wire [3:0] piln_req_in_ntt;
wire iln_req_lat_scanin;
wire iln_req_lat_scanout;
wire [3:0] phst_req_in;
wire [3:0] hst_req;
wire [3:0] hst_req_in;
wire [3:0] phst_req_in_ntt;
wire hst_req_lat_scanin;
wire hst_req_lat_scanout;
wire [3:0] ptlz_req_in;
wire [3:0] tlz_req;
wire [3:0] ptlz_req_in_ntt;
wire tlz_req_lat_scanin;
wire tlz_req_lat_scanout;
wire [3:0] psma_req_in;
wire [3:0] sma_req;
wire [3:0] sma_req_in;
wire [3:0] psma_req_in_ntt;
wire [3:0] trap_taken1;
wire sma_req_lat_scanin;
wire sma_req_lat_scanout;
wire [3:0] pcwq_req_in;
wire [3:0] cwq_req;
wire [3:0] cwq_req_in;
wire [3:0] pcwq_req_in_ntt;
wire cwq_req_lat_scanin;
wire cwq_req_lat_scanout;
wire [3:0] pade_req_in;
wire [3:0] ade_req;
wire [3:0] ade_req_in;
wire [3:0] pade_req_in_ntt;
wire ade_req_lat_scanin;
wire ade_req_lat_scanout;
wire [3:0] piae_req_in;
wire [3:0] iae_req;
wire [3:0] iae_req_in;
wire [3:0] piae_req_in_ntt;
wire iae_req_lat_scanin;
wire iae_req_lat_scanout;
wire [3:0] pipe_req_in;
wire [3:0] ipe_req;
wire [3:0] tpe_exc;
wire [3:0] ipe_req_in;
wire [3:0] pipe_req_in_ntt;
wire take_lsr_last;
wire ipe_req_lat_scanin;
wire ipe_req_lat_scanout;
wire [3:0] pipv_req_in;
wire [3:0] ipv_req;
wire [3:0] ipv_req_in;
wire [3:0] pipv_req_in_ntt;
wire ipv_req_lat_scanin;
wire ipv_req_lat_scanout;
wire i_unauth_access_lat_scanin;
wire i_unauth_access_lat_scanout;
wire [3:0] i_unauth_access;
wire [3:0] piua_req_in;
wire [3:0] iua_req;
wire [3:0] iua_req_in;
wire [3:0] piua_req_in_ntt;
wire iua_req_lat_scanin;
wire iua_req_lat_scanout;
wire [3:0] pinp_req_in;
wire [3:0] inp_req;
wire [3:0] inp_req_in;
wire [3:0] pinp_req_in_ntt;
wire inp_req_lat_scanin;
wire inp_req_lat_scanout;
wire [3:0] piar_req_in;
wire [3:0] iar_req;
wire [3:0] iar_req_in;
wire [3:0] piar_req_in_ntt;
wire iar_req_lat_scanin;
wire iar_req_lat_scanout;
wire [3:0] pirr_req_in;
wire [3:0] irr_req;
wire [3:0] irr_req_in;
wire [3:0] pirr_req_in_ntt;
wire irr_req_lat_scanin;
wire irr_req_lat_scanout;
wire [3:0] pmar_req_in;
wire [3:0] mar_req;
wire [3:0] mar_req_in;
wire [3:0] pmar_req_in_ntt;
wire mar_req_lat_scanin;
wire mar_req_lat_scanout;
wire [3:0] pmrr_req_in;
wire [3:0] mrr_req;
wire [3:0] mrr_req_in;
wire [3:0] pmrr_req_in_ntt;
wire mrr_req_lat_scanin;
wire mrr_req_lat_scanout;
wire [3:0] ppro_req_in;
wire [3:0] pro_req;
wire [3:0] pro_req_in;
wire [3:0] ppro_req_in_ntt;
wire pro_req_lat_scanin;
wire pro_req_lat_scanout;
wire [3:0] pill_req_in;
wire [3:0] ill_req;
wire [3:0] ill_req_in;
wire [3:0] pill_req_in_ntt;
wire ill_req_lat_scanin;
wire ill_req_lat_scanout;
wire [3:0] pdon_req_in;
wire [3:0] don_req;
wire [3:0] don_req_in;
wire stall_don_ret;
wire [3:0] pdon_req_in_ntt;
wire hole_in_p;
wire don_req_lat_scanin;
wire don_req_lat_scanout;
wire [3:0] pret_req_in;
wire [3:0] ret_req;
wire [3:0] ret_req_in;
wire [3:0] pret_req_in_ntt;
wire ret_req_lat_scanin;
wire ret_req_lat_scanout;
wire [3:0] pfpd_req_in;
wire [3:0] fpd_req;
wire [3:0] fpd_req_in;
wire [3:0] pfpd_req_in_ntt;
wire fpd_req_lat_scanin;
wire fpd_req_lat_scanout;
wire [3:0] psnn_req_in;
wire [3:0] snn_req;
wire [3:0] snn_req_in;
wire [3:0] psnn_req_in_ntt;
wire snn_req_lat_scanin;
wire snn_req_lat_scanout;
wire [3:0] psno_req_in;
wire [3:0] sno_req;
wire [3:0] sno_req_in;
wire [3:0] psno_req_in_ntt;
wire sno_req_lat_scanin;
wire sno_req_lat_scanout;
wire [3:0] pfnn_req_in;
wire [3:0] fnn_req;
wire [3:0] fnn_req_in;
wire [3:0] pfnn_req_in_ntt;
wire fnn_req_lat_scanin;
wire fnn_req_lat_scanout;
wire [3:0] pfno_req_in;
wire [3:0] fno_req;
wire [3:0] fno_req_in;
wire [3:0] pfno_req_in_ntt;
wire fno_req_lat_scanin;
wire fno_req_lat_scanout;
wire [3:0] pclw_req_in;
wire [3:0] clw_req;
wire [3:0] clw_req_in;
wire [3:0] pclw_req_in_ntt;
wire clw_req_lat_scanin;
wire clw_req_lat_scanout;
wire [3:0] pdtm_req_in;
wire [3:0] dtm_req;
wire [3:0] dtm_req_in;
wire [3:0] maa_req_in;
wire [3:0] ldf_req_in;
wire [3:0] stf_req_in;
wire [3:0] pra_req_in;
wire [3:0] pdtm_req_in_ntt;
wire [3:0] trap_taken2;
wire dtm_req_lat_scanin;
wire dtm_req_lat_scanout;
wire [3:0] pldf_req_in;
wire [3:0] ldf_req;
wire [3:0] pldf_req_in_ntt;
wire ldf_req_lat_scanin;
wire ldf_req_lat_scanout;
wire [3:0] pstf_req_in;
wire [3:0] stf_req;
wire [3:0] pstf_req_in_ntt;
wire stf_req_lat_scanin;
wire stf_req_lat_scanout;
wire [3:0] pdap_req_in;
wire [3:0] dap_req;
wire [3:0] dap_req_in;
wire [3:0] pdap_req_in_ntt;
wire dap_req_lat_scanin;
wire dap_req_lat_scanout;
wire [3:0] pvaw_req_in;
wire [3:0] vaw_req;
wire [3:0] vaw_req_in;
wire [3:0] pvaw_req_in_ntt;
wire vaw_req_lat_scanin;
wire vaw_req_lat_scanout;
wire [3:0] piaw_req_in;
wire [3:0] iaw_req;
wire [3:0] iaw_req_in;
wire [3:0] piaw_req_in_ntt;
wire iaw_req_lat_scanin;
wire iaw_req_lat_scanout;
wire [3:0] ppaw_req_in;
wire [3:0] paw_req;
wire [3:0] paw_req_in;
wire [3:0] ppaw_req_in_ntt;
wire paw_req_lat_scanin;
wire paw_req_lat_scanout;
wire [3:0] pmaa_req_in;
wire [3:0] maa_req;
wire [3:0] pmaa_req_in_ntt;
wire maa_req_lat_scanin;
wire maa_req_lat_scanout;
wire [3:0] fpx_tid_dec_fw;
wire [3:0] fpd_tid_dec_fw;
wire [3:0] pfpe_req_in;
wire [3:0] fpe_req;
wire [3:0] fpe_req_in;
wire [3:0] pfpe_req_in_ntt;
wire fpe_req_lat_scanin;
wire fpe_req_lat_scanout;
wire [3:0] pfei_req_in;
wire [3:0] fei_req;
wire [3:0] fei_req_in;
wire [3:0] pfei_req_in_ntt;
wire take_fpe_last;
wire take_lsr_nns_last;
wire fei_req_lat_scanin;
wire fei_req_lat_scanout;
wire [3:0] pfof_req_in;
wire [3:0] fof_req;
wire [3:0] fof_req_in;
wire [3:0] pfof_req_in_ntt;
wire fof_req_lat_scanin;
wire fof_req_lat_scanout;
wire [3:0] ppra_req_in;
wire [3:0] pra_req;
wire [3:0] ppra_req_in_ntt;
wire pra_req_lat_scanin;
wire pra_req_lat_scanout;
wire [3:0] pdia_req_in;
wire [3:0] dia_req;
wire [3:0] dia_req_in;
wire [3:0] pdia_req_in_ntt;
wire dia_req_lat_scanin;
wire dia_req_lat_scanout;
wire [3:0] pups_req_in;
wire [3:0] ups_req;
wire [3:0] ups_req_in;
wire [3:0] pups_req_in_ntt;
wire ups_req_lat_scanin;
wire ups_req_lat_scanout;
wire [3:0] pdpv_req_in;
wire [3:0] dpv_req;
wire [3:0] dpv_req_in;
wire [3:0] pdpv_req_in_ntt;
wire dpv_req_lat_scanin;
wire dpv_req_lat_scanout;
wire [3:0] pdnc_req_in;
wire [3:0] dnc_req;
wire [3:0] dnc_req_in;
wire [3:0] pdnc_req_in_ntt;
wire dnc_req_lat_scanin;
wire dnc_req_lat_scanout;
wire [3:0] pdnf_req_in;
wire [3:0] dnf_req;
wire [3:0] dnf_req_in;
wire [3:0] pdnf_req_in_ntt;
wire dnf_req_lat_scanin;
wire dnf_req_lat_scanout;
wire [3:0] pdso_req_in;
wire [3:0] dso_req;
wire [3:0] dso_req_in;
wire [3:0] pdso_req_in_ntt;
wire dso_req_lat_scanin;
wire dso_req_lat_scanout;
wire [3:0] ptof_req_in;
wire [3:0] tof_req;
wire [3:0] tof_req_in;
wire [3:0] ptof_req_in_ntt;
wire tof_req_lat_scanin;
wire tof_req_lat_scanout;
wire [3:0] pdbz_req_in;
wire [3:0] dbz_req;
wire [3:0] dbz_req_in;
wire [3:0] pdbz_req_in_ntt;
wire dbz_req_lat_scanin;
wire dbz_req_lat_scanout;
wire [3:0] tcc_h;
wire [3:0] ptcc_req_in;
wire [3:0] tcc_req;
wire [3:0] tcc_req_in;
wire [3:0] ptcc_req_in_ntt;
wire [3:0] trap_taken3;
wire tcc_req_lat_scanin;
wire tcc_req_lat_scanout;
wire [3:0] pdae_req_in;
wire [3:0] dae_req;
wire [3:0] dae_req_in;
wire [3:0] pdae_req_in_ntt;
wire dae_req_lat_scanin;
wire dae_req_lat_scanout;
wire [3:0] dbz_incoming;
wire [3:0] plsr_req_in;
wire [3:0] lsr_req;
wire [3:0] real_trap_last;
wire [3:0] lsr_req_in;
wire [3:0] itw_req;
wire lsr_req_lat_scanin;
wire lsr_req_lat_scanout;
wire [3:0] pirt_req_in;
wire [3:0] irt_req;
wire [3:0] pirt_req_in_ntt;
wire irt_req_lat_scanin;
wire irt_req_lat_scanout;
wire [3:0] pdrt_req_in;
wire [3:0] drt_req;
wire [3:0] drt_req_in;
wire [3:0] pdrt_req_in_ntt;
wire drt_req_lat_scanin;
wire drt_req_lat_scanout;
wire d_tte_outofrange_lat_scanin;
wire d_tte_outofrange_lat_scanout;
wire [3:0] d_tte_outofrange;
wire [3:0] pdit_req_in;
wire [3:0] dit_req;
wire [3:0] dit_req_in;
wire [3:0] pdit_req_in_ntt;
wire dit_req_lat_scanin;
wire dit_req_lat_scanout;
wire [3:0] ppmu_req_in;
wire [3:0] pmu_req;
wire [3:0] ppmu_req_in_ntt;
wire pmu_req_lat_scanin;
wire pmu_req_lat_scanout;
wire [3:0] pime_req_in;
wire [3:0] ime_req;
wire [3:0] ime_req_in;
wire [3:0] pime_req_in_ntt;
wire ime_req_lat_scanin;
wire ime_req_lat_scanout;
wire [3:0] pdme_req_in;
wire [3:0] dme_req;
wire [3:0] dme_req_in;
wire [3:0] pdme_req_in_ntt;
wire dme_req_lat_scanin;
wire dme_req_lat_scanout;
wire write_itlb_lat_scanin;
wire write_itlb_lat_scanout;
wire [3:0] write_itlb;
wire [3:0] itw_req_in;
wire itw_req_lat_scanin;
wire itw_req_lat_scanout;
wire reload_done_lat_scanin;
wire reload_done_lat_scanout;
wire [3:0] reload_done;
wire [3:0] phtd_req_in;
wire [3:0] htd_req;
wire take_htd_last;
wire [3:0] htd_req_in;
wire htd_req_lat_scanin;
wire htd_req_lat_scanout;
wire i_tsb_miss_lat_scanin;
wire i_tsb_miss_lat_scanout;
wire [3:0] i_tsb_miss;
wire [3:0] phim_req_in;
wire [3:0] him_req;
wire [3:0] him_req_in;
wire [3:0] phim_req_in_ntt;
wire him_req_lat_scanin;
wire him_req_lat_scanout;
wire d_tsb_miss_lat_scanin;
wire d_tsb_miss_lat_scanout;
wire [3:0] d_tsb_miss;
wire [3:0] phdm_req_in;
wire [3:0] hdm_req;
wire [3:0] hdm_req_in;
wire [3:0] phdm_req_in_ntt;
wire hdm_req_lat_scanin;
wire hdm_req_lat_scanout;
wire [3:0] pibp_req_in;
wire [3:0] ibp_req;
wire [3:0] ibp_req_in;
wire [3:0] pibp_req_in_ntt;
wire ibp_req_lat_scanin;
wire ibp_req_lat_scanout;
wire [3:0] ptct_req_in;
wire [3:0] tct_req;
wire [3:0] tct_req_in;
wire [3:0] ptct_req_in_ntt;
wire tct_req_lat_scanin;
wire tct_req_lat_scanout;
wire [3:0] reset_category;
wire [3:0] trap_ndr;
wire [3:0] trap_taken5;
wire [3:0] disrupt_category;
wire [3:0] divide_category;
wire [3:0] long_category;
wire [3:0] fgu_category;
wire [3:0] don_ret_category;
wire [3:0] trap;
wire [3:0] notrap_category;
wire [3:0] itw_category;
wire [3:0] trap_itw;
wire [3:0] trap_itw_taken;
wire [3:0] other_category;
wire [3:0] reset_pre_trap_in;
wire [3:0] disrupt_pre_trap_in;
wire [3:0] divide_pre_trap_in;
wire [3:0] long_pre_trap_in;
wire [3:0] fgu_pre_trap_in;
wire [3:0] don_ret_pre_trap_in;
wire [3:0] notrap_pre_trap_in;
wire [3:0] itw_pre_trap_in;
wire [3:0] other_pre_trap_in;
wire reset_pre_trap_lat_scanin;
wire reset_pre_trap_lat_scanout;
wire [3:0] reset_pre_trap;
wire disrupt_pre_trap_lat_scanin;
wire disrupt_pre_trap_lat_scanout;
wire [3:0] disrupt_pre_trap;
wire divide_pre_trap_lat_scanin;
wire divide_pre_trap_lat_scanout;
wire [3:0] divide_pre_trap;
wire long_pre_trap_lat_scanin;
wire long_pre_trap_lat_scanout;
wire [3:0] long_pre_trap;
wire fgu_pre_trap_lat_scanin;
wire fgu_pre_trap_lat_scanout;
wire [3:0] fgu_pre_trap;
wire don_ret_pre_trap_lat_scanin;
wire don_ret_pre_trap_lat_scanout;
wire [3:0] don_ret_pre_trap;
wire notrap_pre_trap_lat_scanin;
wire notrap_pre_trap_lat_scanout;
wire [3:0] notrap_pre_trap;
wire itw_pre_trap_lat_scanin;
wire itw_pre_trap_lat_scanout;
wire [3:0] itw_pre_trap;
wire other_pre_trap_lat_scanin;
wire other_pre_trap_lat_scanout;
wire [3:0] other_pre_trap;
wire pre_allow_trap_in;
wire take_don;
wire take_ret;
wire take_itw;
wire pre_allow_trap_lat_scanin;
wire pre_allow_trap_lat_scanout;
wire pre_allow_trap;
wire allow_trap;
wire pre_allow_don_ret_in;
wire pre_allow_don_ret_lat_scanin;
wire pre_allow_don_ret_lat_scanout;
wire pre_allow_don_ret;
wire allow_don_ret;
wire take_reset_in;
wire take_disrupt_in;
wire take_div_in;
wire take_long_in;
wire take_fgu_in;
wire take_other_in;
wire take_don_ret_in;
wire take_itw_g_in;
wire take_notrap_in;
wire take_otr_in;
wire take_reset_lat_scanin;
wire take_reset_lat_scanout;
wire ptake_reset;
wire take_reset;
wire take_disrupt_lat_scanin;
wire take_disrupt_lat_scanout;
wire ptake_disrupt;
wire take_disrupt;
wire take_div_lat_scanin;
wire take_div_lat_scanout;
wire ptake_div;
wire take_div;
wire take_long_lat_scanin;
wire take_long_lat_scanout;
wire ptake_long;
wire take_long;
wire take_fgu_lat_scanin;
wire take_fgu_lat_scanout;
wire ptake_fgu;
wire take_fgu;
wire take_other_lat_scanin;
wire take_other_lat_scanout;
wire ptake_other;
wire take_other;
wire take_don_ret_lat_scanin;
wire take_don_ret_lat_scanout;
wire ptake_don_ret;
wire take_don_ret;
wire take_notrap_lat_scanin;
wire take_notrap_lat_scanout;
wire ptake_notrap;
wire take_notrap;
wire take_itw_lat_scanin;
wire take_itw_lat_scanout;
wire ptake_itw_g;
wire take_itw_g;
wire take_otr_lat_scanin;
wire take_otr_lat_scanout;
wire ptake_otr;
wire take_otr;
wire [3:0] take_any_dec;
wire [3:0] real_trap;
wire [3:0] take_any_dec_last;
wire take_por;
wire [3:0] take_por_dec;
wire [3:0] take_por_dec_last;
wire take_por_last;
wire take_xir;
wire take_sir;
wire take_ade;
wire take_iln;
wire take_ivt;
wire take_mqr;
wire take_dqr;
wire take_rqr;
wire take_eer;
wire take_ftt;
wire take_hst;
wire take_tlz;
wire take_sma;
wire take_cwq;
wire take_dae;
wire take_fei;
wire take_fof;
wire take_htd;
wire take_fpe;
wire take_lsr;
wire take_res;
wire take_ssr;
wire take_ssr_por;
wire take_nns;
wire take_icp;
wire take_ipe;
wire take_iae;
wire take_ipv;
wire take_inp;
wire take_iua;
wire take_iar;
wire take_irr;
wire take_mar;
wire take_mrr;
wire take_pro;
wire take_ill;
wire take_fpd;
wire take_snn;
wire take_sno;
wire take_fnn;
wire take_fno;
wire take_clw;
wire take_ldf;
wire take_stf;
wire take_dap;
wire take_pra;
wire take_vaw;
wire take_iaw;
wire take_paw;
wire take_maa;
wire take_dia;
wire take_ups;
wire take_dpv;
wire take_dnc;
wire take_dnf;
wire take_dso;
wire take_tof;
wire take_tcc;
wire take_itm;
wire take_dtm;
wire take_him;
wire take_hdm;
wire take_irt;
wire take_drt;
wire take_pmu;
wire take_ime;
wire take_dme;
wire take_ibp;
wire take_tct;
wire take_iit;
wire take_dit;
wire take_pmu_lat_scanin;
wire take_pmu_lat_scanout;
wire take_pmu_last;
wire take_ivt_lat_scanin;
wire take_ivt_lat_scanout;
wire take_sma_last;
wire take_cwq_last;
wire take_xir_last;
wire take_ftt_last;
wire take_rstnpor;
wire [3:0] trap_not_por;
wire [3:0] trap_taken_in;
wire trap_taken_lat_scanin;
wire trap_taken_lat_scanout;
wire [3:0] trap_taken;
wire trap_taken0_lat_scanin;
wire trap_taken0_lat_scanout;
wire trap_taken1_lat_scanin;
wire trap_taken1_lat_scanout;
wire trap_taken2_lat_scanin;
wire trap_taken2_lat_scanout;
wire trap_taken3_lat_scanin;
wire trap_taken3_lat_scanout;
wire trap_taken4_lat_scanin;
wire trap_taken4_lat_scanout;
wire [3:0] trap_taken4;
wire trap_taken5_lat_scanin;
wire trap_taken5_lat_scanout;
wire trap_itw_taken_lat_scanin;
wire trap_itw_taken_lat_scanout;
wire take_reset_last_lat_scanin;
wire take_reset_last_lat_scanout;
wire take_reset_last;
wire [8:0] trap_type_in;
wire [3:0] int_level_n;
wire [2:0] wstate;
wire [7:0] tcc_number;
wire no_special_trap;
wire next_trap_to_red;
wire next_trap_to_err;
wire priv_overflow_tl;
wire next_trap_to_hpriv;
wire sip;
wire [8:0] trap_type_for_pc_in;
wire trap_type_lat_scanin;
wire trap_type_lat_scanout;
wire [8:0] trap_type;
wire trap_type_for_pc_lat_scanin;
wire trap_type_for_pc_lat_scanout;
wire [8:0] trap_type_for_pc;
wire hpstate_hpriv_lat_scanin;
wire hpstate_hpriv_lat_scanout;
wire [3:0] hpstate_hpriv;
wire [3:0] h_wr_tl;
wire [3:0] n_wr_tl;
wire [2:0] tl_h_wr_data;
wire [2:0] tl_n_wr_data;
wire [3:0] hold_tl;
wire [3:0] npc_sel_tnpc;
wire [2:0] tl3_incr;
wire [2:0] tl3;
wire [2:0] tl3_decr;
wire [2:0] tl3_in;
wire [3:0] tlz_in;
wire [2:0] tl2_incr;
wire [2:0] tl2;
wire [2:0] tl2_decr;
wire [2:0] tl2_in;
wire [2:0] tl1_incr;
wire [2:0] tl1;
wire [2:0] tl1_decr;
wire [2:0] tl1_in;
wire [2:0] tl0_incr;
wire [2:0] tl0;
wire [2:0] tl0_decr;
wire [2:0] tl0_in;
wire tl_lat_scanin;
wire tl_lat_scanout;
wire tlz_lat_scanin;
wire tlz_lat_scanout;
wire [3:0] tlz;
wire [3:0] thread_sel;
wire [3:0] tl_gt_0_in;
wire [3:0] tl_gt_0;
wire tl_gt_0_last_lat_scanin;
wire tl_gt_0_last_lat_scanout;
wire [2:0] trap_tl;
wire [2:0] trap_tl_m1;
wire [2:0] rda_tl_m1;
wire [1:0] wr_gl_data_in_in;
wire [1:0] gl_data_in_in;
wire [3:0] update_gl_in_in;
wire wr_gl_lat_scanin;
wire wr_gl_lat_scanout;
wire [3:0] update_gl_in;
wire [1:0] gl_data_in;
wire [3:0] update_gl;
wire [1:0] gl_data;
wire [1:0] maxglc;
wire other_trap;
wire hpriv_last;
wire reset_trap;
wire [3:0] take_anr_dec_last;
wire [3:0] hold_gl;
wire saturate_restore;
wire [1:0] pgl_rest_in;
wire [1:0] gl_rest_in;
wire gl_rest_lat_scanin;
wire gl_rest_lat_scanout;
wire [1:0] gl_rest;
wire [1:0] gl3_incr;
wire [1:0] gl3;
wire [1:0] gl3_in;
wire [1:0] gl2_incr;
wire [1:0] gl2;
wire [1:0] gl2_in;
wire [1:0] gl1_incr;
wire [1:0] gl1;
wire [1:0] gl1_in;
wire [1:0] gl0_incr;
wire [1:0] gl0;
wire [1:0] gl0_in;
wire [1:0] trap_gl_in;
wire gl_lat_wmr_scanin;
wire gl_lat_wmr_scanout;
wire mbist_run_lat_scanin;
wire mbist_run_lat_scanout;
wire mbist_run;
wire [4:0] wr_addr_in_in;
wire [4:0] wr_addr_func_in;
wire rmw_tsa;
wire [4:0] wr_addr_in_p;
wire [4:0] rmw_addr;
wire [4:0] wr_addr_in;
wire tsa_wr_addr_lat_scanin;
wire tsa_wr_addr_lat_scanout;
wire [4:0] wr_addr;
wire [2:0] don_ret_tl_m1;
wire [4:0] rd_addr_in;
wire tsa_rd_addr_lat_scanin;
wire tsa_rd_addr_lat_scanout;
wire [4:0] rd_addr;
wire rmw_addr_lat_scanin;
wire rmw_addr_lat_scanout;
wire rmw_tsa_lat_scanin;
wire rmw_tsa_lat_scanout;
wire rmw_next;
wire [3:0] pil3_in;
wire [3:0] pil3;
wire [3:0] pil2_in;
wire [3:0] pil2;
wire [3:0] pil1_in;
wire [3:0] pil1;
wire [3:0] pil0_in;
wire [3:0] pil0;
wire pil3_lat_wmr_scanin;
wire pil3_lat_wmr_scanout;
wire pil2_lat_wmr_scanin;
wire pil2_lat_wmr_scanout;
wire pil1_lat_wmr_scanin;
wire pil1_lat_wmr_scanout;
wire pil0_lat_wmr_scanin;
wire pil0_lat_wmr_scanout;
wire [5:0] tic_compare_in;
wire tic_compare_lat_scanin;
wire tic_compare_lat_scanout;
wire [5:0] tic_compare;
wire [16:0] tick3_compare;
wire [16:0] softint3_mux;
wire [16:0] softint3;
wire [16:0] softint3_mask;
wire [16:0] softint3_in;
wire [16:0] tick2_compare;
wire [16:0] softint2_mux;
wire [16:0] softint2;
wire [16:0] softint2_mask;
wire [16:0] softint2_in;
wire [16:0] tick1_compare;
wire [16:0] softint1_mux;
wire [16:0] softint1;
wire [16:0] softint1_mask;
wire [16:0] softint1_in;
wire [16:0] tick0_compare;
wire [16:0] softint0_mux;
wire [16:0] softint0;
wire [16:0] softint0_mask;
wire [16:0] softint0_in;
wire softint3_lat_wmr_scanin;
wire softint3_lat_wmr_scanout;
wire softint2_lat_wmr_scanin;
wire softint2_lat_wmr_scanout;
wire softint1_lat_wmr_scanin;
wire softint1_lat_wmr_scanout;
wire softint0_lat_wmr_scanin;
wire softint0_lat_wmr_scanout;
wire pstate_ie_lat_scanin;
wire pstate_ie_lat_scanout;
wire [3:0] pstate_ie;
wire [16:0] pil3_mask;
wire [16:0] pil2_mask;
wire [16:0] pil1_mask;
wire [16:0] pil0_mask;
wire pmu_trap_mask_d;
wire pmu_trap_mask_lat_scanin;
wire pmu_trap_mask_lat_scanout;
wire pmu_trap_mask_e;
wire [15:1] sim3;
wire [15:1] sim2;
wire [15:1] sim1;
wire [15:1] sim0;
wire [3:0] int_level_n_3;
wire [3:0] int_level_n_2;
wire [3:0] int_level_n_1;
wire [3:0] int_level_n_0;
wire [3:0] int_level_n_3_last;
wire [3:0] int_level_n_2_last;
wire [3:0] int_level_n_1_last;
wire [3:0] int_level_n_0_last;
wire int_level_n_lat_scanin;
wire int_level_n_lat_scanout;
wire hstick3_compare;
wire hintp3_in;
wire hintp3;
wire hstick2_compare;
wire hintp2_in;
wire hintp2;
wire hstick1_compare;
wire hintp1_in;
wire hintp1;
wire hstick0_compare;
wire hintp0_in;
wire hintp0;
wire hintp_lat_wmr_scanin;
wire hintp_lat_wmr_scanout;
wire [3:0] tccd_in;
wire [3:0] tcud_in;
wire tccd_exc_lat_scanin;
wire tccd_exc_lat_scanout;
wire [3:0] tccd;
wire tcud_exc_lat_scanin;
wire tcud_exc_lat_scanout;
wire [3:0] tcud;
wire tic_index_lat_scanin;
wire tic_index_lat_scanout;
wire [4:3] tic_index;
wire [3:0] tsacu_en_in;
wire [3:0] tpe_exc_in;
wire tpe_exc_lat_scanin;
wire tpe_exc_lat_scanout;
wire tsa_index_lat_scanin;
wire tsa_index_lat_scanout;
wire [2:0] tsa_index;
wire p_trap_lat_scanin;
wire p_trap_lat_scanout;
wire [3:0] p_trap;
wire [16:0] rd_softint3;
wire [16:0] rd_softint2;
wire [16:0] rd_softint1;
wire [16:0] rd_softint0;
wire [16:0] asi_data_in;
wire asi_data_lat_scanin;
wire asi_data_lat_scanout;
wire [16:0] asi_data;
wire [3:0] enter_red_in;
wire enter_red_lat_scanin;
wire enter_red_lat_scanout;
wire [3:0] enter_red;
wire stb_empty_lat_scanin;
wire stb_empty_lat_scanout;
wire window_block_in;
wire ccr_cwp_valid;
wire window_block_lat_scanin;
wire window_block_lat_scanout;
wire don_ret_last_last;
wire take_lat_scanin;
wire take_lat_scanout;
wire ptake_don_last;
wire ptake_ret_last;
wire take_res_last;
wire take_ssr_por_last;
wire take_icp_last;
wire take_nns_last;
wire take_htd_icp_last;
wire take_last_lat_scanin;
wire take_last_lat_scanout;
wire don_ret_last;
wire take_don_last_last;
wire take_htd_icp_last_last;
wire take_don_last_last_last;
wire don_ret_last_last_last;
wire thread_sel_lat_scanin;
wire thread_sel_lat_scanout;
wire no_pstate_update;
wire pstate_am_lat_scanin;
wire pstate_am_lat_scanout;
wire [3:0] pstate_am;
wire take_ssr_pc_valid;
wire take_ssr_pc_invalid;
wire pc_sel_pc_in;
wire pc_sel_npc_in;
wire pc_sel_trap_in;
wire pc_sel_reset0_in;
wire pc_sel_reset1_in;
wire pc_done_in;
wire pc_retry_in;
wire pc_tte_in;
wire pc_npc_sel_lat_scanin;
wire pc_npc_sel_lat_scanout;
wire pc_sel_pc;
wire pc_sel_npc;
wire pc_sel_trap;
wire pc_sel_reset0;
wire pc_sel_reset1;
wire pc_done;
wire pc_retry;
wire pc_tte;
wire wr_en_in_in;
wire wr_en_func_in;
wire wr_en_in_p;
wire wr_en_in;
wire rd_en_in;
wire stack_lat_scanin;
wire stack_lat_scanout;
wire tsa_rd_en;
wire tsa_wr_en;
wire tsa_rd_en_last;
wire [3:0] check_tsa_ecc_in;
wire enable_tel_in;
wire check_tel_lat_scanin;
wire check_tel_lat_scanout;
wire enable_tel;
wire check_tel_in;
wire check_tel;
wire take_notrap_not_suppressed;
wire m107773_suppress_notrap_;
wire trap_pc_valid_in_in;
wire trap_pc_valid_in;
wire ptrap_pc_valid_in;
wire kill_fpe;
wire kill_lsr_nns;
wire m107773_suppress_pcvi;
wire real_trap_pc_valid_in;
wire npc_is_nonseq;
wire htd_res_icp_when_npc_nonseq;
wire htd_res_icp_when_npc_nonseq_last_lat_scanin;
wire htd_res_icp_when_npc_nonseq_last_lat_scanout;
wire htd_res_icp_when_npc_nonseq_last;
wire retry_in_in;
wire nns_exc;
wire retry_in;
wire pretry_in;
wire pc_valid_lat_scanin;
wire pc_valid_lat_scanout;
wire trap_pc_valid;
wire [1:0] trap_tid_in;
wire [1:0] ccr_cwp_asi_tid;
wire trap_tid_lat_scanin;
wire trap_tid_lat_scanout;
wire [1:0] trap_tid;
wire take_itw_last_lat_scanin;
wire take_itw_last_lat_scanout;
wire take_itw_last_last;
wire icache_perr_lat_scanin;
wire icache_perr_lat_scanout;
wire take_icp_last_last;
wire reset_trap_in;
wire in_red;
wire hpriv;
wire next_trap_in_hpriv;
wire take_tcc_nh;
wire stay_in_priv_in;
wire take_tcc_h;
wire pre_oti;
wire oti;
wire other_trap_in;
wire pstate_sel_lat_scanin;
wire pstate_sel_lat_scanout;
wire stay_in_priv;
wire [3:0] ccr_cwp_valid_per_thread;
wire [1:0] ccr_cwp_asi_tid_in_in;
wire ccr_cwp_asi_tid_lat_scanin;
wire ccr_cwp_asi_tid_lat_scanout;
wire [1:0] ccr_cwp_asi_tid_in;
wire [3:0] clear_ctl_reg_in;
wire clear_ctl_reg_lat_scanin;
wire clear_ctl_reg_lat_scanout;
wire [3:0] clear_ctl_reg;
wire [3:0] pnpc_nonseq_in;
wire [3:0] npc_nonseq_in;
wire nns_exc_in;
wire npc_nonseq_lat_scanin;
wire npc_nonseq_lat_scanout;
wire [3:0] npc_nonseq;
wire [3:0] trap_tid_in_dec;
wire [3:0] pc_sel_trap_pc_in;
wire pc_sel_trap_pc_lat_scanin;
wire pc_sel_trap_pc_lat_scanout;
wire [3:0] pc_sel_trap_pc;
wire [3:0] npc_sel_trap_npc_in;
wire npc_sel_trap_npc_lat_scanin;
wire npc_sel_trap_npc_lat_scanout;
wire [3:0] npc_sel_trap_npc;
wire [3:0] check_tsa_ecc_in_in;
wire [3:0] tsacu_en_in_in;
wire check_tsa_ecc_lat_scanin;
wire check_tsa_ecc_lat_scanout;
wire [3:0] check_tsa_ecc;
wire [3:0] trap_tid_dec;
wire [3:0] htd_icp_complete;
wire shscanid_lat_scanin;
wire shscanid_lat_scanout;
wire [2:0] shscanid;
wire [2:0] shadow_tl;
wire capture_ss_in;
wire capture_ss_lat_scanin;
wire capture_ss_lat_scanout;
wire capture_ss;
wire [2:0] tl_for_tt_in;
wire [2:0] tl_for_tt;
wire tl_for_tt_lat_scanin;
wire tl_for_tt_lat_scanout;
wire spares_scanin;
wire spares_scanout;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;

input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

input		lsu_tlu_pmen;

input	[2:0]	tcu_shscanid;		// Select which thread to shadow
input		tcu_ss_mode;
input		tcu_do_mode;

input		thread_group;		// Which thread group?

input		mbi_run;		// MBIST

input	[3:0]	ftu_ifu_quiesce;
input	[3:0]	pku_quiesce;

input		exu_tlu_window_block;	// EXU needs hole for CWP change

input	[3:0]	lsu_stb_empty;		// Store buffer empty (for entering RED)

input		fgu_fpx_ieee_trap_fw;	// IEEE 754 trap exception
input		fgu_fpd_ieee_trap_fw;	// IEEE 754 trap exception
input		fgu_fpx_unfin_fw; 	// Other FGU exception
input		fgu_fpd_unfin_fw; 	// Other divide exception
input		fgu_fpd_idiv0_trap_fw;
input	[2:0]	fgu_fpx_trap_tid_fw;	// TID for FGU exceptions except divide
input	[2:0]	fgu_fpd_trap_tid_fw;	// TID for divide exception

input	[3:0]	mmu_write_itlb;		// Write ITLB
input	[3:0]	mmu_reload_done;	// Hardware tablewalk done
input	[3:0]	mmu_i_unauth_access;	// Hardware tablewalk ITSB with EP=0
input	[3:0]	mmu_i_tsb_miss;		// Hardware tablewalk missed
input	[3:0]	mmu_d_tsb_miss;		// Hardware tablewalk missed
input	[3:0]	mmu_i_tte_outofrange;	// RA out of range
input	[3:0]	mmu_d_tte_outofrange;	// RA out of range

input		spu_pmu_ma_busy;	// MA must be idle before parking
input		spu_tlu_cwq_busy;	// Must idle before soft stop parking
input	[2:0]	spu_tlu_ma_int_req;	// Thread that MA is working on

input	[2:0]	fls_wstate0;		// WSTATE for thread 0
input	[2:0]	fls_wstate1;		// WSTATE for thread 1
input	[2:0]	fls_wstate2;		// WSTATE for thread 2
input	[2:0]	fls_wstate3;		// WSTATE for thread 3

input	[7:0]	fls_tcc_number_0;	// Trap number for Tcc thread 0
input	[7:0]	fls_tcc_number_1;	// Trap number for Tcc thread 1
input	[7:0]	fls_tcc_number_2;	// Trap number for Tcc thread 2
input	[7:0]	fls_tcc_number_3;	// Trap number for Tcc thread 3

input	[1:0]	fls_tid_d;		// TID for pic_overflow mask
input	[3:0]	fls_tid_dec_w_in;	// Decoded TID for nonstranded requests

input	[3:0]	fls_por_request;	// POR trap request
input	[3:0]	fls_xir_request;	// XIR trap request
input	[3:0]	fls_ivt_request;	// Interrupt Vector Trap request
input	[3:0]	fls_sir_request;	// SIR trap request
input	[3:0]	fls_itm_request;	// ITLB miss trap request
input	[3:0]	fls_iln_request;	// Interrupt level n request
input	[3:0]	fls_hst_request;	// hstick_match request
input	[3:0]	fls_tlz_request;	// TL equals zero request
input	[3:0]	fls_sma_request;	// SPU Modular Arithmetic request
input	[3:0]	fls_cwq_request;	// SPU Control Word Queue request
input	[3:0]	fls_ade_request;	// Async data error trap request
					// 	(Disrupting error on store, HWTW
input	[3:0]	fls_iae_request;	// Instruction access error trap request
input	[3:0]	fls_ipe_request;	// Internal processor error trap request
					// 	(Error on array access, etc.)
input		fls_ipv_request;	// IAE_privilege_violation trap request
input		fls_inp_request;	// IAE_nfo_page trap request
input		fls_iar_request;	// instruction_address_range trap equest
input		fls_irr_request;	// instruction_real_range trap equest
input		fls_mar_request;	// mem_address_range trap request
input		fls_mrr_request;	// mem_real_range trap request
input		fls_pro_request;	// Privileged opcode trap request
input		fls_ill_request;	// Illegal instruction trap request
input		fls_don_request;	// Done instruction
input		fls_ret_request;	// Retry instruction
input		fls_fpd_request;	// FP disabled trap request
input		fls_snn_request;	// Spill normal trap request
input		fls_sno_request;	// Spill other trap request
input		fls_fnn_request;	// Fill normal trap request
input		fls_fno_request;	// Fill other trap request
input		fls_clw_request;	// Clean window trap request
input	[3:0]	fls_dtm_request;	// DTLB miss trap request
input		fls_ldf_request;	// lddf alignment trap request
input		fls_stf_request;	// stdf alignment trap request
input		fls_dap_request;	// data_access_protection request
input		fls_vaw_request;	// VA watchpoint trap request
input		fls_iaw_request;	// Instruction VA watchpoint trap req
input		fls_paw_request;	// PA watchpoint trap request
input		fls_maa_request;	// Memory address alignment trap request
input		fls_fpe_request;	// FP predicted exception
input	[3:0]	fls_fei_request;	// FP IEEE 754 trap request
input	[3:0]	fls_fof_request;	// FP other trap request (unfinished)
input	[3:0]	fls_pra_request;	// Privileged action trap request
input		fls_dia_request;	// DAE_invalid_asi trap request
input	[3:0]	fls_ups_request;	// unsupported_page_size trap request
input		fls_dpv_request;	// DAE_privilege_violation trap request
input		fls_dnc_request;	// DAE_nc_page trap request
input		fls_dnf_request;	// DAE_nfo_page trap request
input		fls_dso_request;	// DAE_so_page trap request
input		fls_tof_request;	// Tag overflow trap request
input	[3:0]	fls_dbz_request;	// Divide by zero trap request
input		fls_tcc_request;	// Trap instruction trap request
input	[3:0]	fls_dae_request;	// LSU uncorrectable ECC on load miss
input	[3:0]	fls_lsr_request;	// LSU sync redirect to NPC (postsync)
input		fls_irt_request;	// Instruction real translation miss
input		fls_drt_request;	// Data real translation miss
input	[3:0]	fls_pmu_request;	// pic_overflow
input 	[3:0]	fls_mqr_request;	// CPU mondo trap request
input 	[3:0]	fls_dqr_request;	// Device mondo trap request
input 	[3:0]	fls_rqr_request;	// Resumable error trap request
input 	[3:0]	fls_idl_request;	// CMP idle request
input 	[3:0]	fls_res_request;	// CMP resume request
input	[3:0]	fls_ssr_request;	// Single step request
input	[3:0]	fls_ssc_request;	// Single step completion
input 	[3:0]	fls_nns_request;	// NPC nonsequential redirect request
input 	[3:0]	fls_ime_request;	// Instruction_access_MMU_error request
input 	[3:0]	fls_dme_request;	// Data_access_MMU_error request
input 	[3:0]	fls_eer_request;	// ECC_error request
input 		fls_icp_request;	// Icache parity error (ivalidate)
input 	[3:0]	fls_ftt_request;	// Fatal_thread_trap request
input 		fls_ibp_request;	// Instruction breakpoint request
input 		fls_tct_request;	// Trap on control transfer request
input 		fls_ref_request;	// Refetch inst 

input	[3:0]	fls_pc_valid;

input 	[3:0]	pmu_tlu_trap_m;		// pic_overflow is pending

input	[3:0]	fls_trl_l1en;		// Power management for trl
input	[3:0]	fls_core_running;	// Power management
input	[3:0]	tlu_flush_ifu;		// Used for power management

input 	[3:0]	pct_npc_is_nonseq;	// NPC nonsequential, per thread

input 		trlx_itw_wait;		// Other thread group forces ITLB write
                                        // in this group to wait 
input 		trlx_itw_last;		

input	[1:0]	tsa_gl;
input 		tsa_tnpc_nonseq;
input	[3:0]	tel_tsacu_exc;

input	[3:0] tlu_ceter_de;
input	[3:0] tlu_ceter_pscce;

input 	[3:0]	tsd_hpstate_red;
input 	[3:0]	tsd_hpstate_hpriv;
input 	[3:0]	tsd_hpstate_tlz;
input	[3:0]	tsd_pstate_ie;
input	[3:0]	tsd_pstate_am;
input		tsd_htstate_hpriv;	// For saturating GL restore

input	[4:0]	tic_addr;
input		tic_not_valid;
input		tic_match;
input		cel_tccd;
input		cel_tcud;

input	[4:0]	asi_tsa_rd_addr;
input		asi_tsa_rd_iqr_ecc;
input	[1:0]	asi_tsa_tid;
input	[3:0]	asi_rd_tl;
input	[3:0]	asi_wr_tl;
input	[3:0]	asi_rd_pil;
input	[3:0]	asi_wr_pil;
input	[3:0]	asi_rd_gl;
input	[3:0]	asi_wr_gl;
input	[3:0]	asi_wr_set_softint;
input	[3:0]	asi_wr_clear_softint;
input	[3:0]	asi_rd_softint;
input	[3:0]	asi_wr_softint;
input	[3:0]	asi_rd_hintp;
input	[3:0]	asi_wr_hintp;
input	[16:0]	asi_wr_data;
input		asi_preempt_trap;
input		asi_preempt_done_retry;
input		asi_rmw_tsa;
input	[3:0]	asi_wr_asireg;		// Power management
input		asi_trl_pstate_en;	// Power management
input	[4:0]	asi_mbist_addr;		// MBIST
input		asi_mbist_tsa_rd_en;	// MBIST
input		asi_mbist_tsa_wr_en;	// MBIST


output		scan_out;

output		wmr_scan_out;		// Warm reset (non)scan

output	[3:0]	spc_core_running_status;

output	[3:0]	trl_core_running_status;

output	[3:0]	trl_pil_mask_15;	// PIL_mask[15]
output 	[3:0]	trl_iln_exc;		// interrupt_level_n exception
output	[3:0]	trl_hstick_match;	// HSTICK_CMPR matches TICK
output	[3:0]	trl_unhalt_;		// Raw *TICK_CMPR matches
output	[3:0]	trl_tlz_exc;		// TL equals zero exception
output 	[3:0]	trl_nns_exc;		// Retry with nonsequential NPC
output 	[3:0]	trl_ssc_exc;		// Single step complete exception
output		trl_take_sma;		// SPU Modular Arithmetic trap taken
output		trl_take_cwq;		// SPU Control Word Queue trap taken
output		trl_take_xir;		// Hold XIR request until trap is taken
output		trl_take_ftt;		// Hold store_error rq until trap taken

output 	[3:0]	trl_pc_sel_trap_pc;	// Trap, retry, or done taken; update PC
output 	[3:0]	trl_npc_sel_trap_npc;	// Trap taken; update NPC
output 	[3:0]	trl_npc_sel_tnpc;	// Retry or done taken; update NPC
output 	[3:0]	trl_invalidate_pc;	// Trap, done, retry, or HW TW complete
output 	[3:0]	trl_invalidate_npc;	// Trap, retry, or HW TW complete
output	[8:0] trl_trap_type;		// Trap type generated from trap request
output	[8:0]	trl_tsa_trap_type;	// Trap type generated from trap request
output	[4:0]	trl_asireg_sel;		// Which asireg to update?
output		trl_asireg_en;		// Power management
output	[3:0]	trl_thread_sel;		// Which thread to trap?
output	[2:0]	trl_tba_sel;		// Which thread & to HPRIV?
output	[4:0]	trl_pstate_thread_sel;	// Which pstate to update?
output	[3:0]	trl_don_ret_pstate_sel;	// Which pstate to update?
output		trl_pstate_en;		// Power management
output	[3:0]	trl_pc_thread_sel;	// Which PC, NPC to use?
output		trl_pc_pstate_am_;
output		trl_pc_sel_pc;		// Retry the excepting instruction
output		trl_pc_sel_npc;		// Advance to the next instruction
output		trl_pc_sel_trap;	// Select the trap PC
output		trl_pc_sel_reset;	// Select the reset PC
output		trl_pc_done;		// Select the NPC from the stack
output		trl_pc_retry;		// Select the PC from the stack
output		trl_pc_tte;		// Select the TTE for ITLB write
output		trl_pct_trap_pc_en;	// Power management
output		trl_pct_tnpc_en;
output		trl_stay_in_priv;	// Trap should be in priv, not hyperpriv
output		trl_reset_trap;
output		trl_other_trap;
output		trl_tl_gt_0;
output	[3:0]	trl_tl_eq_0;


output		trl_tsa_wr_en;		// Store an entry on the trap stack
output		trl_tsa_rd_en;		// Retrieve an entry off the trap stack
output	[4:0]	trl_tsa_wr_addr;
output	[4:0]	trl_tsa_rd_addr;
output		trl_save_tsa;
output		trl_tsd_tsa_en;		// Power management
output		trl_tsd_tsa_wd_en;	// Power management
output		trl_capture_ss;		// Capture signal for TPC and TT
output		trl_rmw_tsa;

output	[1:0]	trl_tsa_gl;

output 	[16:0]	trl_asi_data;

output 	[3:0]	trl_ss_complete;

output 		trl_itw_wait;
output 		trl_itw_last;

output	[1:0]	trl_shscanid;
output		trl_shscanid_2;
output	[2:0]	trl_shadow_tl;
output	[2:0]	trl_tl_for_tt;

output	[3:0]	trl_fls_npc_en;		// Power management for NPC flops
output		trl_tel_en;		// Power management for tel

output	[3:0]	trl_trap_taken;		// To recycle disrupting requests

output	[1:0]	trl_gl0;
output	[1:0]	trl_gl1;
output	[1:0]	trl_gl2;
output	[1:0]	trl_gl3;

output	[3:0] trl_tsacu_en_in;
output	[2:0] tlu_tsa_index;
output	[3:0] tlu_tccd;
output	[3:0] tlu_tcud;
output	[1:0] tlu_tca_index;


output		tlu_window_block;

output		tlu_trap_pc_valid;
output		tlu_retry;
output		tlu_ifu_invalidate;
output	[1:0]	tlu_trap_tid;
output		tlu_itlb_reload;
output		tlu_ccr_cwp_valid;
output	[1:0]	tlu_ccr_cwp_tid;
output		tlu_asi_valid;
output	[1:0]	tlu_asi_tid;
output	[1:0]	tlu_gl0;
output	[1:0]	tlu_gl1;
output	[1:0]	tlu_gl2;
output	[1:0]	tlu_gl3;

output	[3:0]	tlu_tl_gt_0;

output	[3:0]	tlu_mmu_tl_gt_0;

output	[3:0]	tlu_release_tte;

output 	[3:0]	tlu_lsu_clear_ctl_reg_;

output 	[3:0]	tlu_pmu_trap_taken;

output		tlu_pmu_trap_mask_e;


////////////////////////////////////////////////////////////////////////////////

assign pce_ov	= tcu_pce_ov;
assign stop	= 1'b0;
assign siclk	= spc_aclk;
assign soclk	= spc_bclk;
assign se       = tcu_scan_en;

assign maxtl[2:0] = 3'b110;
assign maxptl[2:0] = 3'b010;
assign maxtl_minus_one[2:0] = maxtl[2:0] - 3'b001;
assign maxgl[1:0] = 2'b11;


////////////////////////////////////////////////////////////////////////////////
// Clock header for freerunning flops

tlu_trl_ctl_l1clkhdr_ctl_macro clkgen (
        .l2clk  (l2clk 			),
        .l1en   (1'b1			),
        .l1clk  (l1clk			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


////////////////////////////////////////////////////////////////////////////////
// Power management

assign thread_active[3:0] =
       fls_core_running[3:0] | core_running_status[3:0];

assign clear_l1en_per_thread_int[3:0] =
       trap_taken0[3:0] & ~{4 {take_itw_last}} & 
       {4 {suppress_don_ret_taken_}};

tlu_trl_ctl_msff_ctl_macro__width_4 flush_ifu_last_lat  (
	.scan_in(flush_ifu_last_lat_scanin),
	.scan_out(flush_ifu_last_lat_scanout),
	.din	(tlu_flush_ifu		[3:0]	),
	.dout	(flush_ifu_last		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign l1en_per_thread_int_in[3:0] =
       tlu_flush_ifu[3:0] | 
       flush_ifu_last[3:0] | 
       fls_res_request[3:0] | // No flush for resume
       fls_lsr_request[3:0] | // No flush for all LSR requests
       fls_nns_request[3:0] |
       fls_ssr_request[3:0] |
       mmu_write_itlb[3:0] |
       (l1en_per_thread_int[3:0] & ~clear_l1en_per_thread_int[3:0] & 
	thread_active[3:0]) |
       {4 {~lsu_tlu_pmen}};

tlu_trl_ctl_msff_ctl_macro__width_4 l1en_per_thread_int_lat  (
	.scan_in(l1en_per_thread_int_lat_scanin),
	.scan_out(l1en_per_thread_int_lat_scanout),
	.din	(l1en_per_thread_int_in	[3:0]	),
	.dout	(l1en_per_thread_int	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Dones and retries need an extra cycle

assign l1en_don_ret_in[3:0] =
       trap_taken0[3:0] & {4 {take_don_last | take_ret_last}};

tlu_trl_ctl_msff_ctl_macro__width_4 l1en_don_ret_lat  (
	.scan_in(l1en_don_ret_lat_scanin),
	.scan_out(l1en_don_ret_lat_scanout),
	.din	(l1en_don_ret_in	[3:0]	),
	.dout	(l1en_don_ret		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign l1en_per_thread[3:0] =
       fls_trl_l1en[3:0] | l1en_per_thread_int[3:0] | l1en_don_ret[3:0];

tlu_trl_ctl_l1clkhdr_ctl_macro t3_clken (
        .l2clk  (l2clk 				),
        .l1en   (l1en_per_thread	[3   ]	),
        .l1clk  (l1clk_pm4			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

tlu_trl_ctl_l1clkhdr_ctl_macro t2_clken (
        .l2clk  (l2clk 				),
        .l1en   (l1en_per_thread	[2   ]	),
        .l1clk  (l1clk_pm3			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

tlu_trl_ctl_l1clkhdr_ctl_macro t1_clken (
        .l2clk  (l2clk 				),
        .l1en   (l1en_per_thread	[1   ]	),
        .l1clk  (l1clk_pm2			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);

tlu_trl_ctl_l1clkhdr_ctl_macro t0_clken (
        .l2clk  (l2clk 				),
        .l1en   (l1en_per_thread	[0   ]	),
        .l1clk  (l1clk_pm1			),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
);


////////////////////////////////////////////////////////////////////////////////
// Record trap requests

tlu_trl_ctl_msff_ctl_macro__width_4 tid_dec_w_lat  (
	.scan_in(tid_dec_w_lat_scanin),
	.scan_out(tid_dec_w_lat_scanout),
	.din	(fls_tid_dec_w_in	[3:0]	),
	.dout	(tid_dec_w		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// Must wait for CWQ to go idle if this is a soft stop parking request
assign cwq_busy_in =
       spu_tlu_cwq_busy;

tlu_trl_ctl_msff_ctl_macro__width_1 cwq_busy_lat  (
	.scan_in(cwq_busy_lat_scanin),
	.scan_out(cwq_busy_lat_scanout),
	.din	(cwq_busy_in			),
	.dout	(cwq_busy			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign cwq_interlock_[3:0] =
       ~{4 {cwq_busy}};

// Don't quiesce until TLB updates are complete
// DTLB is covered by LSU which is covered by PKU, but
// ITLB is only known by TLU
assign quiesced_in[3:0] =
       stb_empty[3:0] & i_quiesce[3:0] & 
       p_quiesce[3:0] & ma_idle[3:0] & cwq_interlock_[3:0] & 
       ~pitw_req_in[3:0];

tlu_trl_ctl_msff_ctl_macro__width_8 quiesced_lat  (
	.scan_in(quiesced_last_lat_scanin),
	.scan_out(quiesced_last_lat_scanout),
	.din	({quiesced_in		[3:0],
		  quiesced		[3:0]}),
	.dout	({quiesced		[3:0],
		  quiesced_last		[3:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// Idle must suppress other pending (synchronous) traps 
assign pidl_req_in[3:0] = 
	(fls_idl_request[3:0] | idl_req[3:0]) & 
	core_running_status[3:0];

assign idl_req_in[3:0] =
       pidl_req_in[3:0] & quiesced[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 idl_req_lat   (
	.scan_in(idl_req_lat_scanin),
	.scan_out(idl_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pidl_req_in		[3:0]	),
	.dout	(idl_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 i_quiesce_lat  (
	.scan_in(i_quiesce_lat_scanin),
	.scan_out(i_quiesce_lat_scanout),
	.din	(ftu_ifu_quiesce	[3:0]	),
	.dout	(i_quiesce		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 p_quiesce_lat  (
	.scan_in(p_quiesce_lat_scanin),
	.scan_out(p_quiesce_lat_scanout),
	.din	(pku_quiesce		[3:0]	),
	.dout	(p_quiesce		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 ma_busy_lat  (
	.scan_in(ma_busy_lat_scanin),
	.scan_out(ma_busy_lat_scanout),
	.din	({spu_pmu_ma_busy	       ,
		  spu_tlu_ma_int_req	[2:0]}),
	.dout	({ma_busy		       ,
		  ma_tid		[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ma_idle[3:0] =
       ~({4 {ma_busy & (ma_tid[2] == thread_group)}} &
         {ma_tid[1:0] == 2'b11,
          ma_tid[1:0] == 2'b10,
          ma_tid[1:0] == 2'b01,
          ma_tid[1:0] == 2'b00});

// Report status once thread is actually idle
assign core_running_status_in[3:0] =
       (core_running_status[3:0] | trap_por_res_ssr[3:0]) & 
       ~idl_req_in[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 core_running_status_lat   (
	.scan_in(core_running_status_lat_scanin),
	.scan_out(core_running_status_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(core_running_status_in	[3:0]	),
	.dout	(core_running_status	[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ever_been_running_in[3:0] =
       ever_been_running[3:0] | core_running_status[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 ever_been_running_lat  (
	.scan_in(ever_been_running_lat_scanin),
	.scan_out(ever_been_running_lat_scanout),
	.din	(ever_been_running_in	[3:0]	),
	.dout	(ever_been_running	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign spc_core_running_status[3:0] = 
       core_running_status[3:0];

assign trl_core_running_status[3:0] = 
       core_running_status[3:0];


assign pdisrupting_req[3:0] = 4'h0;
assign disrupting_req[3:0] = 4'h0;


assign por_req_in[3:0] = 
	(fls_por_request[3:0] | por_req[3:0]);
assign por_req_in_ntt[3:0] = 
	por_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 por_req_lat   (
	.scan_in(por_req_lat_scanin),
	.scan_out(por_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(por_req_in_ntt		[3:0]	),
	.dout	(por_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pxir_req_in[3:0] = 
	(fls_xir_request[3:0] | xir_req[3:0]);

assign xir_req_in[3:0] =
       pxir_req_in[3:0] & stb_empty[3:0];

assign pxir_req_in_ntt[3:0] =
	pxir_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 xir_req_lat   (
	.scan_in(xir_req_lat_scanin),
	.scan_out(xir_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pxir_req_in_ntt	[3:0]	),
	.dout	(xir_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign peer_req_in[3:0] = 
	fls_eer_request[3:0] | eer_req[3:0];

assign eer_req_in[3:0] =
       peer_req_in[3:0] & stb_empty[3:0];

assign peer_req_in_ntt[3:0] =
	peer_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 eer_req_lat   (
	.scan_in(eer_req_lat_scanin),
	.scan_out(eer_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(peer_req_in_ntt	[3:0]	),
	.dout	(eer_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// icp means icache error.  TLU must redirect IFU to
// PC with an tlu_ifu_invalidate to force an invalidate and refetch
assign icp_req_in[3:0] = 
	({4 {fls_icp_request}} & tid_dec_w[3:0]) | icp_req[3:0];

assign icp_req_in_ntt[3:0] =
	icp_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 icp_req_lat   (
	.scan_in(icp_req_lat_scanin),
	.scan_out(icp_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(icp_req_in_ntt		[3:0]	),
	.dout	(icp_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pftt_req_in[3:0] = 
	fls_ftt_request[3:0] | ftt_req[3:0];

assign ftt_req_in[3:0] =
       pftt_req_in[3:0] & stb_empty[3:0];

assign pftt_req_in_ntt[3:0] =
	pftt_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ftt_req_lat   (
	.scan_in(ftt_req_lat_scanin),
	.scan_out(ftt_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pftt_req_in_ntt	[3:0]	),
	.dout	(ftt_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pivt_req_in[3:0] = 
	(fls_ivt_request[3:0] | ivt_req[3:0]);

assign ivt_req_in[3:0] =
       pivt_req_in[3:0] & ~stb_wait[3:0];

assign pivt_req_in_ntt[3:0] =
	pivt_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ivt_req_lat   (
	.scan_in(ivt_req_lat_scanin),
	.scan_out(ivt_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pivt_req_in_ntt	[3:0]	),
	.dout	(ivt_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pmqr_req_in[3:0] = 
	(fls_mqr_request[3:0] | mqr_req[3:0]);

assign mqr_req_in[3:0] =
       pmqr_req_in[3:0] & ~stb_wait[3:0];

assign pmqr_req_in_ntt[3:0] =
	pmqr_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 mqr_req_lat   (
	.scan_in(mqr_req_lat_scanin),
	.scan_out(mqr_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pmqr_req_in_ntt	[3:0]	),
	.dout	(mqr_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdqr_req_in[3:0] = 
	(fls_dqr_request[3:0] | dqr_req[3:0]);

assign dqr_req_in[3:0] =
       pdqr_req_in[3:0] & ~stb_wait[3:0];

assign pdqr_req_in_ntt[3:0] =
	pdqr_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dqr_req_lat   (
	.scan_in(dqr_req_lat_scanin),
	.scan_out(dqr_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdqr_req_in_ntt	[3:0]	),
	.dout	(dqr_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign prqr_req_in[3:0] = 
	(fls_rqr_request[3:0] | rqr_req[3:0]);

assign rqr_req_in[3:0] =
       prqr_req_in[3:0] & ~stb_wait[3:0];

assign prqr_req_in_ntt[3:0] =
	prqr_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 rqr_req_lat   (
	.scan_in(rqr_req_lat_scanin),
	.scan_out(rqr_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(prqr_req_in_ntt	[3:0]	),
	.dout	(rqr_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pres_req_in[3:0] = 
	(fls_res_request[3:0] | res_req[3:0]) & ever_been_running[3:0];

// Do not need to wait for anything for resume to take effect
assign res_req_in[3:0] =
       pres_req_in[3:0];

assign pres_req_in_ntt[3:0] =
	pres_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 res_req_lat   (
	.scan_in(res_req_lat_scanin),
	.scan_out(res_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pres_req_in_ntt	[3:0]	),
	.dout	(res_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pssr_req_in[3:0] = 
	(fls_ssr_request[3:0] | ssr_req[3:0]);

// Need to wait for quiesce for single step to take effect
assign ssr_req_in[3:0] =
       pssr_req_in[3:0] & quiesced[3:0];

assign ssr_req_in_for_taken[3:0] =
       pssr_req_in[3:0] & quiesced_last[3:0];

// Have to hold ssr until it's taken (in case of HW TW)
assign pssr_req_in_ntt[3:0] =
       pssr_req_in[3:0] & ~tlu_flush_ifu[3:0] & 
       ~(trap_taken0[3:0] & {4 {take_ssr_last}});

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ssr_req_lat   (
	.scan_in(ssr_req_lat_scanin),
	.scan_out(ssr_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pssr_req_in_ntt	[3:0]	),
	.dout	(ssr_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// Tracking when machine idles again
// Kill request if late exception occurs (based on flush_gfb_in in tlu_fls_ctl)
// But also need unsupported_page_size because that happens late with no
// flush in W (other MMU-related exceptions already caused flushes in W)
assign ssc_req_in[3:0] = 
	(fls_ssc_request[3:0] | ssc_req[3:0]) & 
	~quiesced[3:0] & 
	~fei_or_fof_incoming[3:0] & 
        ~fls_dae_request[3:0] & 
	~fls_pra_request[3:0] & 
	~fls_pmu_request[3:0] & 
	~fls_ipe_request[3:0] & 
	~fls_dbz_request[3:0] &
	~fls_ups_request[3:0] ;

tlu_trl_ctl_msff_ctl_macro__width_4 ssc_req_lat  (
	.scan_in(ssc_req_lat_scanin),
	.scan_out(ssc_req_lat_scanout),
	.din	(ssc_req_in		[3:0]	),
	.dout	(ssc_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_ss_complete[3:0] =
       ssc_req[3:0] & quiesced[3:0];

assign pnns_req_in[3:0] = 
	(fls_nns_request[3:0] | nns_req[3:0]);

assign nns_req_in[3:0] =
       pnns_req_in[3:0];

assign pnns_req_in_ntt[3:0] =
	pnns_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 nns_req_lat   (
	.scan_in(nns_req_lat_scanin),
	.scan_out(nns_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pnns_req_in_ntt	[3:0]	),
	.dout	(nns_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign psir_req_in[3:0] = 
	(fls_sir_request[3:0] | sir_req[3:0]) & ~pdisrupting_req[3:0];

assign sir_req_in[3:0] =
       psir_req_in[3:0] & stb_empty[3:0];

assign psir_req_in_ntt[3:0] =
	psir_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 sir_req_lat   (
	.scan_in(sir_req_lat_scanin),
	.scan_out(sir_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(psir_req_in_ntt	[3:0]	),
	.dout	(sir_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pitm_req_in[3:0] = 
	(fls_itm_request[3:0] | itm_req[3:0]) & ~disrupting_req[3:0];

assign itm_req_in[3:0] =
       pitm_req_in[3:0] & ~stb_wait[3:0] &
       ~irt_req_in[3:0] & ~tlz_req_in[3:0] & ~pmu_req_in[3:0];

assign pitm_req_in_ntt[3:0] =
	pitm_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 itm_req_lat   (
	.scan_in(itm_req_lat_scanin),
	.scan_out(itm_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pitm_req_in_ntt	[3:0]	),
	.dout	(itm_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 i_tte_outofrange_lat  (
	.scan_in(i_tte_outofrange_lat_scanin),
	.scan_out(i_tte_outofrange_lat_scanout),
	.din	(mmu_i_tte_outofrange	[3:0]	),
	.dout	(i_tte_outofrange	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign piit_req_in[3:0] = 
	(i_tte_outofrange[3:0] | iit_req[3:0]) & ~disrupting_req[3:0];

assign iit_req_in[3:0] =
       piit_req_in[3:0] & ~stb_wait[3:0];

assign piit_req_in_ntt[3:0] =
	piit_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 iit_req_lat  (
	.scan_in(iit_req_lat_scanin),
	.scan_out(iit_req_lat_scanout),
	.din	(piit_req_in_ntt	[3:0]	),
	.dout	(iit_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign piln_req_in[3:0] = 
	(fls_iln_request[3:0] | iln_req[3:0]) & 
	~pdisrupting_req[3:0] & ~sir_req[3:0];

assign iln_req_in[3:0] =
       piln_req_in[3:0] & ~stb_wait[3:0];

assign piln_req_in_ntt[3:0] =
	piln_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 iln_req_lat   (
	.scan_in(iln_req_lat_scanin),
	.scan_out(iln_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(piln_req_in_ntt	[3:0]	),
	.dout	(iln_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign phst_req_in[3:0] = 
	(fls_hst_request[3:0] | hst_req[3:0]) & 
	~pdisrupting_req[3:0] & ~sir_req[3:0];

assign hst_req_in[3:0] =
       phst_req_in[3:0] & ~stb_wait[3:0];

assign phst_req_in_ntt[3:0] =
	phst_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 hst_req_lat   (
	.scan_in(hst_req_lat_scanin),
	.scan_out(hst_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(phst_req_in_ntt	[3:0]	),
	.dout	(hst_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ptlz_req_in[3:0] = 
	(fls_tlz_request[3:0] | tlz_req[3:0]) & 
	~pdisrupting_req[3:0] & ~sir_req[3:0];

assign tlz_req_in[3:0] =
       ptlz_req_in[3:0] & ~stb_wait[3:0];

assign ptlz_req_in_ntt[3:0] =
	ptlz_req_in[3:0] & ~trap_taken0[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 tlz_req_lat   (
	.scan_in(tlz_req_lat_scanin),
	.scan_out(tlz_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(ptlz_req_in_ntt	[3:0]	),
	.dout	(tlz_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign psma_req_in[3:0] = 
	(fls_sma_request[3:0] | sma_req[3:0]) & 
	~pdisrupting_req[3:0] & ~sir_req[3:0];

assign sma_req_in[3:0] =
       psma_req_in[3:0] & ~stb_wait[3:0];

assign psma_req_in_ntt[3:0] =
	psma_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 sma_req_lat   (
	.scan_in(sma_req_lat_scanin),
	.scan_out(sma_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(psma_req_in_ntt	[3:0]	),
	.dout	(sma_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pcwq_req_in[3:0] = 
	(fls_cwq_request[3:0] | cwq_req[3:0]) & 
	~pdisrupting_req[3:0] & ~sir_req[3:0];

assign cwq_req_in[3:0] =
       pcwq_req_in[3:0] & ~stb_wait[3:0];

assign pcwq_req_in_ntt[3:0] =
	pcwq_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 cwq_req_lat   (
	.scan_in(cwq_req_lat_scanin),
	.scan_out(cwq_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pcwq_req_in_ntt	[3:0]	),
	.dout	(cwq_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pade_req_in[3:0] = 
	(fls_ade_request[3:0] | ade_req[3:0]) & 
	~pdisrupting_req[3:0] & ~sir_req[3:0];

assign ade_req_in[3:0] =
       pade_req_in[3:0] & stb_empty[3:0];

assign pade_req_in_ntt[3:0] =
	pade_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ade_req_lat   (
	.scan_in(ade_req_lat_scanin),
	.scan_out(ade_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pade_req_in_ntt	[3:0]	),
	.dout	(ade_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign piae_req_in[3:0] = 
	(fls_iae_request[3:0] | iae_req[3:0]) & 
	~disrupting_req[3:0];

assign iae_req_in[3:0] =
       piae_req_in[3:0] & stb_empty[3:0];

assign piae_req_in_ntt[3:0] =
	piae_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 iae_req_lat   (
	.scan_in(iae_req_lat_scanin),
	.scan_out(iae_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(piae_req_in_ntt	[3:0]	),
	.dout	(iae_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// Note that TSA precise exception on done/retry come straight here
// and do NOT go to tlu_fls_ctl
// Also note that IPE is NOT disrupting
assign pipe_req_in[3:0] = 
       (fls_ipe_request[3:0] | ipe_req[3:0] | tpe_exc[3:0]) & 
       ~disrupting_req[3:0];

assign ipe_req_in[3:0] =
       pipe_req_in[3:0] & stb_empty[3:0];

assign pipe_req_in_ntt[3:0] =
	pipe_req_in[3:0] & ~(trap_taken1[3:0] & ~{4 {take_lsr_last}});

tlu_trl_ctl_msff_ctl_macro__width_4 ipe_req_lat  (
	.scan_in(ipe_req_lat_scanin),
	.scan_out(ipe_req_lat_scanout),
	.din	(pipe_req_in_ntt	[3:0]	),
	.dout	(ipe_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pipv_req_in[3:0] = 
	(({4 {fls_ipv_request}} & tid_dec_w[3:0]) | ipv_req[3:0]) & 
	~disrupting_req[3:0];

assign ipv_req_in[3:0] =
       pipv_req_in[3:0] & ~stb_wait[3:0];

assign pipv_req_in_ntt[3:0] =
	pipv_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ipv_req_lat   (
	.scan_in(ipv_req_lat_scanin),
	.scan_out(ipv_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pipv_req_in_ntt	[3:0]	),
	.dout	(ipv_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 i_unauth_access_lat  (
	.scan_in(i_unauth_access_lat_scanin),
	.scan_out(i_unauth_access_lat_scanout),
	.din	(mmu_i_unauth_access	[3:0]	),
	.dout	(i_unauth_access	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign piua_req_in[3:0] = 
	(i_unauth_access[3:0] | iua_req[3:0]) & 
	~disrupting_req[3:0];

assign iua_req_in[3:0] =
       piua_req_in[3:0] & ~stb_wait[3:0];

assign piua_req_in_ntt[3:0] =
	piua_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 iua_req_lat   (
	.scan_in(iua_req_lat_scanin),
	.scan_out(iua_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(piua_req_in_ntt	[3:0]	),
	.dout	(iua_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pinp_req_in[3:0] = 
	(({4 {fls_inp_request}} & tid_dec_w[3:0]) | inp_req[3:0]) & 
	~disrupting_req[3:0];

assign inp_req_in[3:0] =
       pinp_req_in[3:0] & ~stb_wait[3:0];

assign pinp_req_in_ntt[3:0] =
	pinp_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 inp_req_lat   (
	.scan_in(inp_req_lat_scanin),
	.scan_out(inp_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pinp_req_in_ntt	[3:0]	),
	.dout	(inp_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign piar_req_in[3:0] = 
	(({4 {fls_iar_request}} & tid_dec_w[3:0]) | iar_req[3:0]) & 
	~disrupting_req[3:0];

assign iar_req_in[3:0] =
       piar_req_in[3:0] & ~stb_wait[3:0];

assign piar_req_in_ntt[3:0] =
	piar_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 iar_req_lat   (
	.scan_in(iar_req_lat_scanin),
	.scan_out(iar_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(piar_req_in_ntt	[3:0]	),
	.dout	(iar_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pirr_req_in[3:0] = 
	(({4 {fls_irr_request}} & tid_dec_w[3:0]) | irr_req[3:0]) & 
	~disrupting_req[3:0];

assign irr_req_in[3:0] =
       pirr_req_in[3:0] & ~stb_wait[3:0];

assign pirr_req_in_ntt[3:0] =
	pirr_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 irr_req_lat   (
	.scan_in(irr_req_lat_scanin),
	.scan_out(irr_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pirr_req_in_ntt	[3:0]	),
	.dout	(irr_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pmar_req_in[3:0] = 
	(({4 {fls_mar_request}} & tid_dec_w[3:0]) | mar_req[3:0]) & 
	~disrupting_req[3:0];

assign mar_req_in[3:0] =
       pmar_req_in[3:0] & ~stb_wait[3:0];

assign pmar_req_in_ntt[3:0] =
	pmar_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 mar_req_lat   (
	.scan_in(mar_req_lat_scanin),
	.scan_out(mar_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pmar_req_in_ntt	[3:0]	),
	.dout	(mar_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pmrr_req_in[3:0] = 
	(({4 {fls_mrr_request}} & tid_dec_w[3:0]) | mrr_req[3:0]) & 
	~disrupting_req[3:0];

assign mrr_req_in[3:0] =
       pmrr_req_in[3:0] & ~stb_wait[3:0];

assign pmrr_req_in_ntt[3:0] =
	pmrr_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 mrr_req_lat   (
	.scan_in(mrr_req_lat_scanin),
	.scan_out(mrr_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pmrr_req_in_ntt	[3:0]	),
	.dout	(mrr_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ppro_req_in[3:0] = 
	(({4 {fls_pro_request}} & tid_dec_w[3:0]) | pro_req[3:0]) & 
	~disrupting_req[3:0];

assign pro_req_in[3:0] =
       ppro_req_in[3:0] & ~stb_wait[3:0];

assign ppro_req_in_ntt[3:0] =
	ppro_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 pro_req_lat   (
	.scan_in(pro_req_lat_scanin),
	.scan_out(pro_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(ppro_req_in_ntt	[3:0]	),
	.dout	(pro_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pill_req_in[3:0] = 
	(({4 {fls_ill_request}} & tid_dec_w[3:0]) | ill_req[3:0]) & 
	~disrupting_req[3:0];

assign ill_req_in[3:0] =
       pill_req_in[3:0] & ~stb_wait[3:0];

assign pill_req_in_ntt[3:0] =
	pill_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ill_req_lat   (
	.scan_in(ill_req_lat_scanin),
	.scan_out(ill_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pill_req_in_ntt	[3:0]	),
	.dout	(ill_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdon_req_in[3:0] = 
	(({4 {fls_don_request}} & tid_dec_w[3:0]) | don_req[3:0]) & 
	~disrupting_req[3:0];

assign don_req_in[3:0] =
       {4 {~stall_don_ret}} & pdon_req_in[3:0];

assign pdon_req_in_ntt[3:0] =
	pdon_req_in[3:0] & (~trap_taken1[3:0] | {4 {hole_in_p}});

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 don_req_lat   (
	.scan_in(don_req_lat_scanin),
	.scan_out(don_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdon_req_in_ntt	[3:0]	),
	.dout	(don_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pret_req_in[3:0] = 
	(({4 {fls_ret_request}} & tid_dec_w[3:0]) | ret_req[3:0]) & 
	~disrupting_req[3:0];

assign ret_req_in[3:0] =
       {4 {~stall_don_ret}} & pret_req_in[3:0];

assign pret_req_in_ntt[3:0] =
	pret_req_in[3:0] & (~trap_taken1[3:0] | {4 {hole_in_p}});

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ret_req_lat   (
	.scan_in(ret_req_lat_scanin),
	.scan_out(ret_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pret_req_in_ntt	[3:0]	),
	.dout	(ret_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pfpd_req_in[3:0] = 
	(({4 {fls_fpd_request}} & tid_dec_w[3:0]) | fpd_req[3:0]) & 
	~disrupting_req[3:0];

assign fpd_req_in[3:0] =
       pfpd_req_in[3:0] & ~stb_wait[3:0];

assign pfpd_req_in_ntt[3:0] =
	pfpd_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 fpd_req_lat   (
	.scan_in(fpd_req_lat_scanin),
	.scan_out(fpd_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pfpd_req_in_ntt	[3:0]	),
	.dout	(fpd_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign psnn_req_in[3:0] = 
	(({4 {fls_snn_request}} & tid_dec_w[3:0]) | snn_req[3:0]) & 
	~disrupting_req[3:0];

assign snn_req_in[3:0] =
       psnn_req_in[3:0] & ~stb_wait[3:0];

assign psnn_req_in_ntt[3:0] =
	psnn_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 snn_req_lat   (
	.scan_in(snn_req_lat_scanin),
	.scan_out(snn_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(psnn_req_in_ntt	[3:0]	),
	.dout	(snn_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign psno_req_in[3:0] = 
	(({4 {fls_sno_request}} & tid_dec_w[3:0]) | sno_req[3:0]) & 
	~disrupting_req[3:0];

assign sno_req_in[3:0] =
       psno_req_in[3:0] & ~stb_wait[3:0];

assign psno_req_in_ntt[3:0] =
	psno_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 sno_req_lat   (
	.scan_in(sno_req_lat_scanin),
	.scan_out(sno_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(psno_req_in_ntt	[3:0]	),
	.dout	(sno_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pfnn_req_in[3:0] = 
	(({4 {fls_fnn_request}} & tid_dec_w[3:0]) | fnn_req[3:0]) & 
	~disrupting_req[3:0];

assign fnn_req_in[3:0] =
       pfnn_req_in[3:0] & ~stb_wait[3:0];

assign pfnn_req_in_ntt[3:0] =
	pfnn_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 fnn_req_lat   (
	.scan_in(fnn_req_lat_scanin),
	.scan_out(fnn_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pfnn_req_in_ntt	[3:0]	),
	.dout	(fnn_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pfno_req_in[3:0] = 
	(({4 {fls_fno_request}} & tid_dec_w[3:0]) | fno_req[3:0]) & 
	~disrupting_req[3:0];

assign fno_req_in[3:0] =
       pfno_req_in[3:0] & ~stb_wait[3:0];

assign pfno_req_in_ntt[3:0] =
	pfno_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 fno_req_lat   (
	.scan_in(fno_req_lat_scanin),
	.scan_out(fno_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pfno_req_in_ntt	[3:0]	),
	.dout	(fno_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pclw_req_in[3:0] = 
	(({4 {fls_clw_request}} & tid_dec_w[3:0]) | clw_req[3:0]) & 
	~disrupting_req[3:0];

assign clw_req_in[3:0] =
       pclw_req_in[3:0] & ~stb_wait[3:0];

assign pclw_req_in_ntt[3:0] =
	pclw_req_in[3:0] & ~trap_taken1[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 clw_req_lat   (
	.scan_in(clw_req_lat_scanin),
	.scan_out(clw_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pclw_req_in_ntt	[3:0]	),
	.dout	(clw_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdtm_req_in[3:0] = 
	(fls_dtm_request[3:0] | dtm_req[3:0]) & 
	~disrupting_req[3:0];

assign dtm_req_in[3:0] =
       pdtm_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pdtm_req_in_ntt[3:0] =
	pdtm_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dtm_req_lat   (
	.scan_in(dtm_req_lat_scanin),
	.scan_out(dtm_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdtm_req_in_ntt	[3:0]	),
	.dout	(dtm_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pldf_req_in[3:0] = 
	(({4 {fls_ldf_request}} & tid_dec_w[3:0]) | ldf_req[3:0]) & 
	~disrupting_req[3:0];

assign ldf_req_in[3:0] =
       pldf_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0];

assign pldf_req_in_ntt[3:0] =
	pldf_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ldf_req_lat   (
	.scan_in(ldf_req_lat_scanin),
	.scan_out(ldf_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pldf_req_in_ntt	[3:0]	),
	.dout	(ldf_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pstf_req_in[3:0] = 
	(({4 {fls_stf_request}} & tid_dec_w[3:0]) | stf_req[3:0]) & 
	~disrupting_req[3:0];

assign stf_req_in[3:0] =
       pstf_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0];

assign pstf_req_in_ntt[3:0] =
	pstf_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 stf_req_lat   (
	.scan_in(stf_req_lat_scanin),
	.scan_out(stf_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pstf_req_in_ntt	[3:0]	),
	.dout	(stf_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdap_req_in[3:0] = 
	(({4 {fls_dap_request}} & tid_dec_w[3:0]) | dap_req[3:0]) & 
	~disrupting_req[3:0];

assign dap_req_in[3:0] =
       pdap_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pdap_req_in_ntt[3:0] =
	pdap_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dap_req_lat   (
	.scan_in(dap_req_lat_scanin),
	.scan_out(dap_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdap_req_in_ntt	[3:0]	),
	.dout	(dap_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pvaw_req_in[3:0] = 
	(({4 {fls_vaw_request}} & tid_dec_w[3:0]) | vaw_req[3:0]) & 
	~disrupting_req[3:0];

assign vaw_req_in[3:0] =
       pvaw_req_in[3:0] & ~stb_wait[3:0];

assign pvaw_req_in_ntt[3:0] =
	pvaw_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 vaw_req_lat   (
	.scan_in(vaw_req_lat_scanin),
	.scan_out(vaw_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pvaw_req_in_ntt	[3:0]	),
	.dout	(vaw_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign piaw_req_in[3:0] = 
	(({4 {fls_iaw_request}} & tid_dec_w[3:0]) | iaw_req[3:0]) & 
	~disrupting_req[3:0];

assign iaw_req_in[3:0] =
       piaw_req_in[3:0] & ~stb_wait[3:0];

assign piaw_req_in_ntt[3:0] =
	piaw_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 iaw_req_lat   (
	.scan_in(iaw_req_lat_scanin),
	.scan_out(iaw_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(piaw_req_in_ntt	[3:0]	),
	.dout	(iaw_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ppaw_req_in[3:0] = 
	(({4 {fls_paw_request}} & tid_dec_w[3:0]) | paw_req[3:0]) & 
	~disrupting_req[3:0];

assign paw_req_in[3:0] =
       ppaw_req_in[3:0] & ~stb_wait[3:0];

assign ppaw_req_in_ntt[3:0] =
	ppaw_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 paw_req_lat   (
	.scan_in(paw_req_lat_scanin),
	.scan_out(paw_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(ppaw_req_in_ntt	[3:0]	),
	.dout	(paw_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pmaa_req_in[3:0] = 
	(({4 {fls_maa_request}} & tid_dec_w[3:0]) | maa_req[3:0]) & 
	~disrupting_req[3:0];

assign maa_req_in[3:0] =
       pmaa_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0];
assign pmaa_req_in_ntt[3:0] =
	pmaa_req_in[3:0] & ~trap_taken2[3:0];


tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 maa_req_lat   (
	.scan_in(maa_req_lat_scanin),
	.scan_out(maa_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pmaa_req_in_ntt	[3:0]	),
	.dout	(maa_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign fpx_tid_dec_fw[3:0] = 
	{4 {thread_group == fgu_fpx_trap_tid_fw[2]}} & 
	{ fgu_fpx_trap_tid_fw[1] &  fgu_fpx_trap_tid_fw[0],
	  fgu_fpx_trap_tid_fw[1] & ~fgu_fpx_trap_tid_fw[0],
	 ~fgu_fpx_trap_tid_fw[1] &  fgu_fpx_trap_tid_fw[0],
	 ~fgu_fpx_trap_tid_fw[1] & ~fgu_fpx_trap_tid_fw[0]};

assign fpd_tid_dec_fw[3:0] = 
	{4 {thread_group == fgu_fpd_trap_tid_fw[2]}} & 
	{ fgu_fpd_trap_tid_fw[1] &  fgu_fpd_trap_tid_fw[0],
	  fgu_fpd_trap_tid_fw[1] & ~fgu_fpd_trap_tid_fw[0],
	 ~fgu_fpd_trap_tid_fw[1] &  fgu_fpd_trap_tid_fw[0],
	 ~fgu_fpd_trap_tid_fw[1] & ~fgu_fpd_trap_tid_fw[0]};

assign fei_or_fof_incoming[3:0] = 
       ({4 {fgu_fpx_ieee_trap_fw | fgu_fpx_unfin_fw}} & fpx_tid_dec_fw[3:0]) |
       ({4 {fgu_fpd_ieee_trap_fw | fgu_fpd_unfin_fw}} & fpd_tid_dec_fw[3:0]) ;

// Have to kill FP predicted exception redirect in the event the actual
// exception catches up with it
// dbz is not predicted
assign pfpe_req_in[3:0] = 
	(({4 {fls_fpe_request}} & tid_dec_w[3:0]) | fpe_req[3:0]) & 
	~disrupting_req[3:0] & 
	~fei_or_fof_incoming[3:0];

assign fpe_req_in[3:0] =
       pfpe_req_in[3:0];

assign pfpe_req_in_ntt[3:0] =
	pfpe_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 fpe_req_lat   (
	.scan_in(fpe_req_lat_scanin),
	.scan_out(fpe_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pfpe_req_in_ntt	[3:0]	),
	.dout	(fpe_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pfei_req_in[3:0] = 
       (fls_fei_request[3:0] | fei_req[3:0]) & 
       ~disrupting_req[3:0];

assign fei_req_in[3:0] =
       pfei_req_in[3:0] & ~stb_wait[3:0];

assign pfei_req_in_ntt[3:0] =
	pfei_req_in[3:0] & 
       (~trap_taken2[3:0] | {4 {take_fpe_last | take_lsr_nns_last}});

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 fei_req_lat   (
	.scan_in(fei_req_lat_scanin),
	.scan_out(fei_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pfei_req_in_ntt	[3:0]	),
	.dout	(fei_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pfof_req_in[3:0] = 
       (fls_fof_request[3:0] | fof_req[3:0]) &
       ~disrupting_req[3:0];

assign fof_req_in[3:0] =
       pfof_req_in[3:0] & ~stb_wait[3:0];

assign pfof_req_in_ntt[3:0] =
	pfof_req_in[3:0] & 
       (~trap_taken2[3:0] | {4 {take_fpe_last | take_lsr_nns_last}});

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 fof_req_lat   (
	.scan_in(fof_req_lat_scanin),
	.scan_out(fof_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pfof_req_in_ntt	[3:0]	),
	.dout	(fof_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ppra_req_in[3:0] = 
	(fls_pra_request[3:0] | pra_req[3:0]) & 
	~disrupting_req[3:0];

assign pra_req_in[3:0] =
       ppra_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0];

assign ppra_req_in_ntt[3:0] =
	ppra_req_in[3:0] & ~(trap_taken1[3:0] & ~{4 {take_lsr_last}});

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 pra_req_lat   (
	.scan_in(pra_req_lat_scanin),
	.scan_out(pra_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(ppra_req_in_ntt	[3:0]	),
	.dout	(pra_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdia_req_in[3:0] = 
	(({4 {fls_dia_request}} & tid_dec_w[3:0]) | dia_req[3:0]) & 
	~disrupting_req[3:0];

assign dia_req_in[3:0] =
       pdia_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pdia_req_in_ntt[3:0] =
	pdia_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dia_req_lat   (
	.scan_in(dia_req_lat_scanin),
	.scan_out(dia_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdia_req_in_ntt	[3:0]	),
	.dout	(dia_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pups_req_in[3:0] = 
	(fls_ups_request[3:0] | ups_req[3:0]) &
	~disrupting_req[3:0];

assign ups_req_in[3:0] =
       pups_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pups_req_in_ntt[3:0] =
	pups_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ups_req_lat   (
	.scan_in(ups_req_lat_scanin),
	.scan_out(ups_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pups_req_in_ntt	[3:0]	),
	.dout	(ups_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdpv_req_in[3:0] = 
	(({4 {fls_dpv_request}} & tid_dec_w[3:0]) | dpv_req[3:0]) & 
	~disrupting_req[3:0];

assign dpv_req_in[3:0] =
       pdpv_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pdpv_req_in_ntt[3:0] =
	pdpv_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dpv_req_lat   (
	.scan_in(dpv_req_lat_scanin),
	.scan_out(dpv_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdpv_req_in_ntt	[3:0]	),
	.dout	(dpv_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdnc_req_in[3:0] = 
	(({4 {fls_dnc_request}} & tid_dec_w[3:0]) | dnc_req[3:0]) & 
	~disrupting_req[3:0];

assign dnc_req_in[3:0] =
       pdnc_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pdnc_req_in_ntt[3:0] =
	pdnc_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dnc_req_lat   (
	.scan_in(dnc_req_lat_scanin),
	.scan_out(dnc_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdnc_req_in_ntt	[3:0]	),
	.dout	(dnc_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdnf_req_in[3:0] = 
	(({4 {fls_dnf_request}} & tid_dec_w[3:0]) | dnf_req[3:0]) & 
	~disrupting_req[3:0];

assign dnf_req_in[3:0] =
       pdnf_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pdnf_req_in_ntt[3:0] =
	pdnf_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dnf_req_lat   (
	.scan_in(dnf_req_lat_scanin),
	.scan_out(dnf_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdnf_req_in_ntt	[3:0]	),
	.dout	(dnf_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdso_req_in[3:0] = 
	(({4 {fls_dso_request}} & tid_dec_w[3:0]) | dso_req[3:0]) & 
	~disrupting_req[3:0];

assign dso_req_in[3:0] =
       pdso_req_in[3:0] & ~stb_wait[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pdso_req_in_ntt[3:0] =
	pdso_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dso_req_lat   (
	.scan_in(dso_req_lat_scanin),
	.scan_out(dso_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdso_req_in_ntt	[3:0]	),
	.dout	(dso_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ptof_req_in[3:0] = 
	(({4 {fls_tof_request}} & tid_dec_w[3:0]) | tof_req[3:0]) & 
	~disrupting_req[3:0];

assign tof_req_in[3:0] =
       ptof_req_in[3:0] & ~stb_wait[3:0];

assign ptof_req_in_ntt[3:0] =
	ptof_req_in[3:0] & ~trap_taken2[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 tof_req_lat   (
	.scan_in(tof_req_lat_scanin),
	.scan_out(tof_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(ptof_req_in_ntt	[3:0]	),
	.dout	(tof_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdbz_req_in[3:0] = 
       (fls_dbz_request[3:0] | dbz_req[3:0]) & 
	~disrupting_req[3:0];

assign dbz_req_in[3:0] =
       pdbz_req_in[3:0] & ~stb_wait[3:0];

assign pdbz_req_in_ntt[3:0] =
	pdbz_req_in[3:0] & 
       (~trap_taken2[3:0] | {4 {take_lsr_nns_last}});

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dbz_req_lat   (
	.scan_in(dbz_req_lat_scanin),
	.scan_out(dbz_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdbz_req_in_ntt	[3:0]	),
	.dout	(dbz_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign tcc_h[3:0] = 
	{fls_tcc_number_3[7], fls_tcc_number_2[7],
	 fls_tcc_number_1[7], fls_tcc_number_0[7]};

assign ptcc_req_in[3:0] = 
	(({4 {fls_tcc_request}} & tid_dec_w[3:0]) | tcc_req[3:0]) & 
	~disrupting_req[3:0];

assign tcc_req_in[3:0] =
       ptcc_req_in[3:0] & 
       ((~stb_wait[3:0] &  tcc_h[3:0]) |
        (~stb_wait[3:0] & ~tcc_h[3:0]));

assign ptcc_req_in_ntt[3:0] =
	ptcc_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 tcc_req_lat   (
	.scan_in(tcc_req_lat_scanin),
	.scan_out(tcc_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(ptcc_req_in_ntt	[3:0]	),
	.dout	(tcc_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdae_req_in[3:0] = 
       (fls_dae_request[3:0] | dae_req[3:0]) &
       ~disrupting_req[3:0];

assign dae_req_in[3:0] = 
       pdae_req_in[3:0] & stb_empty[3:0] &
       ~ill_req_in[3:0] & ~maa_req_in[3:0] & ~ldf_req_in[3:0] & 
       ~stf_req_in[3:0] & ~pra_req_in[3:0] ;

assign pdae_req_in_ntt[3:0] =
	pdae_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dae_req_lat   (
	.scan_in(dae_req_lat_scanin),
	.scan_out(dae_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdae_req_in_ntt	[3:0]	),
	.dout	(dae_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

// Have to kill LSR exception redirect in the event an FPOP
// exception catches up with it
assign dbz_incoming[3:0] = 
	{4 {fgu_fpd_idiv0_trap_fw}} & fpx_tid_dec_fw[3:0];

assign plsr_req_in[3:0] = 
       (fls_lsr_request[3:0] | lsr_req[3:0]) & 
       ~((trap_taken3[3:0] & {4 {take_lsr_last | take_fpe_last}}) | 
	 real_trap_last[3:0] | fei_or_fof_incoming[3:0] | 
	 ({4 {fls_fpd_request}} & tid_dec_w[3:0]) | dbz_incoming[3:0]) & 
	~disrupting_req[3:0];

assign lsr_req_in[3:0] =
       plsr_req_in[3:0] & ~itw_req[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 lsr_req_lat   (
	.scan_in(lsr_req_lat_scanin),
	.scan_out(lsr_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(plsr_req_in		[3:0]	),
	.dout	(lsr_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pirt_req_in[3:0] = 
        (({4 {fls_irt_request}} & tid_dec_w[3:0]) | irt_req[3:0]) &
	~disrupting_req[3:0];

assign irt_req_in[3:0] =
       pirt_req_in[3:0] & ~stb_wait[3:0] & 
       ~tlz_req_in[3:0] & ~pmu_req_in[3:0];

assign pirt_req_in_ntt[3:0] =
	pirt_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 irt_req_lat   (
	.scan_in(irt_req_lat_scanin),
	.scan_out(irt_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pirt_req_in_ntt	[3:0]	),
	.dout	(irt_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdrt_req_in[3:0] = 
        (({4 {fls_drt_request}} & tid_dec_w[3:0]) | drt_req[3:0]) &
	~disrupting_req[3:0];

assign drt_req_in[3:0] =
       pdrt_req_in[3:0] & ~stb_wait[3:0];

assign pdrt_req_in_ntt[3:0] =
	pdrt_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 drt_req_lat   (
	.scan_in(drt_req_lat_scanin),
	.scan_out(drt_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdrt_req_in_ntt	[3:0]	),
	.dout	(drt_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 d_tte_outofrange_lat  (
	.scan_in(d_tte_outofrange_lat_scanin),
	.scan_out(d_tte_outofrange_lat_scanout),
	.din	(mmu_d_tte_outofrange	[3:0]	),
	.dout	(d_tte_outofrange	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pdit_req_in[3:0] = 
        (d_tte_outofrange[3:0] | dit_req[3:0]) & 
	~disrupting_req[3:0];

assign dit_req_in[3:0] =
       pdit_req_in[3:0] & ~stb_wait[3:0];

assign pdit_req_in_ntt[3:0] =
	pdit_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 dit_req_lat  (
	.scan_in(dit_req_lat_scanin),
	.scan_out(dit_req_lat_scanout),
	.din	(pdit_req_in_ntt	[3:0]	),
	.dout	(dit_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign ppmu_req_in[3:0] = 
        (fls_pmu_request[3:0] | pmu_req[3:0]) &
	~disrupting_req[3:0];

assign pmu_req_in[3:0] =
       ppmu_req_in[3:0] & ~stb_wait[3:0] & 
       ~tlz_req_in[3:0];

assign ppmu_req_in_ntt[3:0] =
	ppmu_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 pmu_req_lat   (
	.scan_in(pmu_req_lat_scanin),
	.scan_out(pmu_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(ppmu_req_in_ntt	[3:0]	),
	.dout	(pmu_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign pime_req_in[3:0] = 
       (fls_ime_request[3:0] | ime_req[3:0]) & 
       ~disrupting_req[3:0];

assign ime_req_in[3:0] =
       pime_req_in[3:0] & stb_empty[3:0];

assign pime_req_in_ntt[3:0] =
	pime_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ime_req_lat   (
	.scan_in(ime_req_lat_scanin),
	.scan_out(ime_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pime_req_in_ntt	[3:0]	),
	.dout	(ime_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);


assign pdme_req_in[3:0] = 
       (fls_dme_request[3:0] | dme_req[3:0]) & 
       ~disrupting_req[3:0];

assign dme_req_in[3:0] =
       pdme_req_in[3:0] & stb_empty[3:0];

assign pdme_req_in_ntt[3:0] =
	pdme_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 dme_req_lat   (
	.scan_in(dme_req_lat_scanin),
	.scan_out(dme_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pdme_req_in_ntt	[3:0]	),
	.dout	(dme_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 write_itlb_lat  (
	.scan_in(write_itlb_lat_scanin),
	.scan_out(write_itlb_lat_scanout),
	.din	(mmu_write_itlb		[3:0]	),
	.dout	(write_itlb		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pitw_req_in[3:0] = 
       (write_itlb[3:0] | itw_req[3:0]) & 
       ~({4 {take_itw_last}} & trap_taken3[3:0]) & 
       ~disrupting_req[3:0];

// Thread group 1 waits for thread group 0 to complete all writes to ITLB
// Must be two cycles between ITLB writes
assign itw_req_in[3:0] =
       pitw_req_in[3:0] & 
       {4 {~trlx_itw_wait & ~trlx_itw_last}};

tlu_trl_ctl_msff_ctl_macro__width_4 itw_req_lat  (
	.scan_in(itw_req_lat_scanin),
	.scan_out(itw_req_lat_scanout),
	.din	(pitw_req_in		[3:0]	),
	.dout	(itw_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_itw_wait = 
       (| {itw_req[3:0], write_itlb[3:0]});

assign trl_itw_last =
       take_itw_last;

tlu_trl_ctl_msff_ctl_macro__width_4 reload_done_lat  (
	.scan_in(reload_done_lat_scanin),
	.scan_out(reload_done_lat_scanout),
	.din	(mmu_reload_done[3:0]	),
	.dout	(reload_done	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign phtd_req_in[3:0] = 
	(((reload_done[3:0] | htd_req[3:0]) & ~pssr_req_in[3:0]) |
	 ({4 {fls_ref_request}} & tid_dec_w[3:0])) &
	~({4 {take_htd_last}} & trap_taken3[3:0]) & ~disrupting_req[3:0];

assign htd_req_in[3:0] =
       phtd_req_in[3:0] & ~itw_req[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 htd_req_lat  (
	.scan_in(htd_req_lat_scanin),
	.scan_out(htd_req_lat_scanout),
	.din	(phtd_req_in		[3:0]	),
	.dout	(htd_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 i_tsb_miss_lat  (
	.scan_in(i_tsb_miss_lat_scanin),
	.scan_out(i_tsb_miss_lat_scanout),
	.din	(mmu_i_tsb_miss		[3:0]	),
	.dout	(i_tsb_miss		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign phim_req_in[3:0] = 
        (i_tsb_miss[3:0] | him_req[3:0]) & 
	~disrupting_req[3:0];

assign him_req_in[3:0] =
       phim_req_in[3:0] & ~stb_wait[3:0];

assign phim_req_in_ntt[3:0] =
	phim_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 him_req_lat  (
	.scan_in(him_req_lat_scanin),
	.scan_out(him_req_lat_scanout),
	.din	(phim_req_in_ntt	[3:0]	),
	.dout	(him_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


tlu_trl_ctl_msff_ctl_macro__width_4 d_tsb_miss_lat  (
	.scan_in(d_tsb_miss_lat_scanin),
	.scan_out(d_tsb_miss_lat_scanout),
	.din	(mmu_d_tsb_miss		[3:0]	),
	.dout	(d_tsb_miss		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign phdm_req_in[3:0] = 
        (d_tsb_miss[3:0] | hdm_req[3:0]) & 
	~disrupting_req[3:0];

assign hdm_req_in[3:0] =
       phdm_req_in[3:0] & ~stb_wait[3:0];

assign phdm_req_in_ntt[3:0] =
	phdm_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 hdm_req_lat  (
	.scan_in(hdm_req_lat_scanin),
	.scan_out(hdm_req_lat_scanout),
	.din	(phdm_req_in_ntt	[3:0]	),
	.dout	(hdm_req		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pibp_req_in[3:0] = 
        (({4 {fls_ibp_request}} & tid_dec_w[3:0]) | ibp_req[3:0]) &
	~disrupting_req[3:0];

assign ibp_req_in[3:0] =
       pibp_req_in[3:0] & ~stb_wait[3:0] & 
       ~tlz_req_in[3:0];

assign pibp_req_in_ntt[3:0] =
	pibp_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 ibp_req_lat   (
	.scan_in(ibp_req_lat_scanin),
	.scan_out(ibp_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(pibp_req_in_ntt	[3:0]	),
	.dout	(ibp_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign ptct_req_in[3:0] = 
        (({4 {fls_tct_request}} & tid_dec_w[3:0]) | tct_req[3:0]) &
	~disrupting_req[3:0];

assign tct_req_in[3:0] =
       ptct_req_in[3:0] & ~stb_wait[3:0] & 
       ~tlz_req_in[3:0];

assign ptct_req_in_ntt[3:0] =
	ptct_req_in[3:0] & ~trap_taken3[3:0];

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 tct_req_lat   (
	.scan_in(tct_req_lat_scanin),
	.scan_out(tct_req_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(ptct_req_in_ntt	[3:0]	),
	.dout	(tct_req		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Categorize requests

assign reset_category[3:0] = 
       (por_req_in[3:0] | xir_req_in[3:0] | sir_req_in[3:0] ) & 
       ~trap_ndr[3:0] & ~trap_taken5[3:0];

assign disrupt_category[3:0] = 
       (ade_req_in[3:0] | iln_req_in[3:0] | 
	hst_req_in[3:0] | tlz_req_in[3:0] | sma_req_in[3:0] | 
	cwq_req_in[3:0] | ivt_req_in[3:0] | mqr_req_in[3:0] | 
	dqr_req_in[3:0] | rqr_req_in[3:0] | eer_req_in[3:0] | 
	ftt_req_in[3:0] ) &
       ~trap_ndr[3:0] & ~trap_taken5[3:0];

assign divide_category[3:0] = 
       (dbz_req_in[3:0]) &
       ~trap_ndr[3:0] & ~trap_taken5[3:0];

assign long_category[3:0] = 
       dae_req_in[3:0] & ~trap_ndr[3:0] & ~trap_taken5[3:0];

assign fgu_category[3:0] = 
       (fei_req_in[3:0] | fof_req_in[3:0]) &
       ~trap_ndr[3:0] & ~trap_taken5[3:0];

assign don_ret_category[3:0] = 
       (don_req_in[3:0] | ret_req_in[3:0]) &
       ~trap[3:0] & (~trap_taken5[3:0] | {4 {hole_in_p}});

assign notrap_category[3:0] = 
       (htd_req_in[3:0] | fpe_req_in[3:0] | lsr_req_in[3:0] | 
	res_req_in[3:0] | ssr_req_in[3:0] | 
	nns_req_in[3:0] | icp_req_in[3:0]) &
       ~trap_ndr[3:0] & ~trap_taken5[3:0];

assign itw_category[3:0] =
       itw_req_in[3:0] & ~trap_itw[3:0] & ~trap_itw_taken[3:0];

assign other_category[3:0] = 
       (iae_req_in[3:0] | ipv_req_in[3:0] | inp_req_in[3:0] |
	iua_req_in[3:0] | ipe_req_in[3:0] | 
	iar_req_in[3:0] | irr_req_in[3:0] |
        mar_req_in[3:0] | mrr_req_in[3:0] |
        pro_req_in[3:0] |
	ill_req_in[3:0] | fpd_req_in[3:0] | snn_req_in[3:0] |
	sno_req_in[3:0] | fnn_req_in[3:0] | fno_req_in[3:0] | 
	clw_req_in[3:0] | ldf_req_in[3:0] | stf_req_in[3:0] |
	dap_req_in[3:0] |
	vaw_req_in[3:0] | iaw_req_in[3:0] | paw_req_in[3:0] | 
	maa_req_in[3:0] | 
	pra_req_in[3:0] | dia_req_in[3:0] | 
	ups_req_in[3:0] | dpv_req_in[3:0] |
	dnc_req_in[3:0] | dnf_req_in[3:0] | dso_req_in[3:0] |
	tof_req_in[3:0] | tcc_req_in[3:0] | 
	itm_req_in[3:0] | dtm_req_in[3:0] | him_req_in[3:0] | 
	hdm_req_in[3:0] | irt_req_in[3:0] | drt_req_in[3:0] |
	pmu_req_in[3:0] | ime_req_in[3:0] | dme_req_in[3:0] |
	ibp_req_in[3:0] | tct_req_in[3:0] | 
	iit_req_in[3:0] | dit_req_in[3:0] ) &
       ~trap_ndr[3:0] & ~trap_taken5[3:0];


////////////////////////////////////////////////////////////////////////////////
// Select thread within each category using static priority

// POR resets cannot wait for store buffer to empty
assign reset_pre_trap_in[3:0] = 
       {reset_category[3] & ~(| reset_category[2:0]),
	reset_category[2] & ~(| reset_category[1:0]),
	reset_category[1] & ~(  reset_category[   0]),
	reset_category[0]} & (stb_empty[3:0] | por_req_in[3:0]);

assign disrupt_pre_trap_in[3:0] = 
       {disrupt_category[3] & ~(| disrupt_category[2:0]),
	disrupt_category[2] & ~(| disrupt_category[1:0]),
	disrupt_category[1] & ~(  disrupt_category[   0]),
	disrupt_category[0]};

assign divide_pre_trap_in[3:0] = 
       {divide_category[3] & ~(| divide_category[2:0]),
	divide_category[2] & ~(| divide_category[1:0]),
	divide_category[1] & ~(  divide_category[   0]),
	divide_category[0]};

assign long_pre_trap_in[3:0] =
       {long_category[3] & ~(| long_category[2:0]),
	long_category[2] & ~(| long_category[1:0]),
	long_category[1] & ~(  long_category[   0]),
	long_category[0]};

assign fgu_pre_trap_in[3:0] = 
       {fgu_category[3] & ~(| fgu_category[2:0]),
	fgu_category[2] & ~(| fgu_category[1:0]),
	fgu_category[1] & ~(  fgu_category[   0]),
	fgu_category[0]};

assign don_ret_pre_trap_in[3:0] = 
       {don_ret_category[3] & ~(| don_ret_category[2:0]),
	don_ret_category[2] & ~(| don_ret_category[1:0]),
	don_ret_category[1] & ~(  don_ret_category[   0]),
	don_ret_category[0]};

assign notrap_pre_trap_in[3:0] = 
       {notrap_category[3] & ~(| notrap_category[2:0]),
	notrap_category[2] & ~(| notrap_category[1:0]),
	notrap_category[1] & ~(  notrap_category[   0]),
	notrap_category[0]};

assign itw_pre_trap_in[3:0] = 
       {itw_category[3] & ~(| itw_category[2:0]),
	itw_category[2] & ~(| itw_category[1:0]),
	itw_category[1] & ~(  itw_category[   0]),
	itw_category[0]};

assign other_pre_trap_in[3:0] = 
       {other_category[3] & ~(| other_category[2:0]),
	other_category[2] & ~(| other_category[1:0]),
	other_category[1] & ~(  other_category[   0]),
	other_category[0]};

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 reset_pre_trap_lat   (
	.scan_in(reset_pre_trap_lat_scanin),
	.scan_out(reset_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(reset_pre_trap_in	[3:0]	),
	.dout	(reset_pre_trap		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 disrupt_pre_trap_lat   (
	.scan_in(disrupt_pre_trap_lat_scanin),
	.scan_out(disrupt_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(disrupt_pre_trap_in	[3:0]	),
	.dout	(disrupt_pre_trap	[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 divide_pre_trap_lat   (
	.scan_in(divide_pre_trap_lat_scanin),
	.scan_out(divide_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(divide_pre_trap_in	[3:0]	),
	.dout	(divide_pre_trap	[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 long_pre_trap_lat   (
	.scan_in(long_pre_trap_lat_scanin),
	.scan_out(long_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(long_pre_trap_in	[3:0]	),
	.dout	(long_pre_trap		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 fgu_pre_trap_lat   (
	.scan_in(fgu_pre_trap_lat_scanin),
	.scan_out(fgu_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(fgu_pre_trap_in	[3:0]	),
	.dout	(fgu_pre_trap		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 don_ret_pre_trap_lat   (
	.scan_in(don_ret_pre_trap_lat_scanin),
	.scan_out(don_ret_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(don_ret_pre_trap_in	[3:0]	),
	.dout	(don_ret_pre_trap	[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 notrap_pre_trap_lat   (
	.scan_in(notrap_pre_trap_lat_scanin),
	.scan_out(notrap_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(notrap_pre_trap_in	[3:0]	),
	.dout	(notrap_pre_trap	[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 itw_pre_trap_lat   (
	.scan_in(itw_pre_trap_lat_scanin),
	.scan_out(itw_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(itw_pre_trap_in	[3:0]	),
	.dout	(itw_pre_trap		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 other_pre_trap_lat   (
	.scan_in(other_pre_trap_lat_scanin),
	.scan_out(other_pre_trap_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(other_pre_trap_in	[3:0]	),
	.dout	(other_pre_trap		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Prioritize categories

// ITLB writes take two cycles on bus to IFU so must
// hold off traps in second cycle
// Traps must write the TSA

assign pre_allow_trap_in =
       ~asi_rmw_tsa & ~take_don & ~take_ret & ~take_don_last & 
       ~take_ret_last & ~take_itw;

tlu_trl_ctl_msff_ctl_macro__width_1 pre_allow_trap_lat  (
	.scan_in(pre_allow_trap_lat_scanin),
	.scan_out(pre_allow_trap_lat_scanout),
	.din	(pre_allow_trap_in	),
	.dout	(pre_allow_trap		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign allow_trap =
       ~asi_preempt_trap & pre_allow_trap;

assign pre_allow_don_ret_in =
       ~take_don & ~take_ret & ~take_itw;

tlu_trl_ctl_msff_ctl_macro__width_1 pre_allow_don_ret_lat  (
	.scan_in(pre_allow_don_ret_lat_scanin),
	.scan_out(pre_allow_don_ret_lat_scanout),
	.din	(pre_allow_don_ret_in	),
	.dout	(pre_allow_don_ret	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign allow_don_ret = 
       ~asi_preempt_done_retry & pre_allow_don_ret;

// POR resets cannot wait for store buffer to empty
assign take_reset_in = 
       (| (reset_category[3:0] & (stb_empty[3:0] | por_req_in[3:0])));

// Pending disrupting conditions prevent any other type of trap request
assign take_disrupt_in = 
       (| disrupt_category[3:0]) & ~take_reset_in;

assign take_div_in = 
       (| divide_category[3:0]) & ~take_disrupt_in & ~take_reset_in;

assign take_long_in = 
       (| long_category[3:0]) & ~take_div_in & ~take_disrupt_in & 
       ~take_reset_in;

assign take_fgu_in = 
	(| fgu_category[3:0]) & ~take_long_in & ~take_div_in & 
	~take_disrupt_in & ~take_reset_in;

assign take_other_in = 
       (| other_category[3:0]) & ~take_fgu_in & ~take_long_in & 
       ~take_div_in & ~take_disrupt_in & ~take_reset_in;

assign take_don_ret_in = 
       (| don_ret_category[3:0]) & ~take_other_in & ~take_fgu_in & 
       ~take_long_in & ~take_div_in & ~take_disrupt_in & ~take_disrupt_in & 
       ~take_reset_in;

// itw can occur at same time as disrupt or other categories
assign take_itw_g_in = 
       (| itw_category[3:0]) & ~take_don_ret_in & ~take_other_in & 
       ~take_fgu_in & ~take_long_in & ~take_div_in & ~take_disrupt_in & 
       ~take_disrupt_in & ~take_reset_in;

// notrap can occur at same time as disrupt or other categories
assign take_notrap_in = 
       (| notrap_category[3:0]) & ~take_don_ret_in & ~take_other_in & 
       ~take_fgu_in & ~take_long_in & ~take_div_in & ~take_disrupt_in & 
       ~take_disrupt_in & ~take_reset_in & ~take_itw_g_in;

assign take_otr_in =  // take trap other than reset
       take_disrupt_in | take_div_in | take_long_in | take_fgu_in | 
       take_other_in;

tlu_trl_ctl_msff_ctl_macro__width_1 take_reset_lat  (
	.scan_in(take_reset_lat_scanin),
	.scan_out(take_reset_lat_scanout),
	.din	(take_reset_in			),
	.dout	(ptake_reset			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_reset =
       ptake_reset & allow_trap;

tlu_trl_ctl_msff_ctl_macro__width_1 take_disrupt_lat  (
	.scan_in(take_disrupt_lat_scanin),
	.scan_out(take_disrupt_lat_scanout),
	.din	(take_disrupt_in		),
	.dout	(ptake_disrupt			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_disrupt =
       ptake_disrupt & allow_trap;

tlu_trl_ctl_msff_ctl_macro__width_1 take_div_lat  (
	.scan_in(take_div_lat_scanin),
	.scan_out(take_div_lat_scanout),
	.din	(take_div_in			),
	.dout	(ptake_div			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_div =
       ptake_div & allow_trap;

tlu_trl_ctl_msff_ctl_macro__width_1 take_long_lat  (
	.scan_in(take_long_lat_scanin),
	.scan_out(take_long_lat_scanout),
	.din	(take_long_in			),
	.dout	(ptake_long			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_long =
       ptake_long & allow_trap;

tlu_trl_ctl_msff_ctl_macro__width_1 take_fgu_lat  (
	.scan_in(take_fgu_lat_scanin),
	.scan_out(take_fgu_lat_scanout),
	.din	(take_fgu_in			),
	.dout	(ptake_fgu			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_fgu =
       ptake_fgu & allow_trap;

tlu_trl_ctl_msff_ctl_macro__width_1 take_other_lat  (
	.scan_in(take_other_lat_scanin),
	.scan_out(take_other_lat_scanout),
	.din	(take_other_in			),
	.dout	(ptake_other			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_other =
       ptake_other & allow_trap;

tlu_trl_ctl_msff_ctl_macro__width_1 take_don_ret_lat  (
	.scan_in(take_don_ret_lat_scanin),
	.scan_out(take_don_ret_lat_scanout),
	.din	(take_don_ret_in		),
	.dout	(ptake_don_ret			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_don_ret =
       ptake_don_ret & allow_don_ret;

tlu_trl_ctl_msff_ctl_macro__width_1 take_notrap_lat  (
	.scan_in(take_notrap_lat_scanin),
	.scan_out(take_notrap_lat_scanout),
	.din	(take_notrap_in			),
	.dout	(ptake_notrap			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_notrap =
       ptake_notrap & allow_trap;

tlu_trl_ctl_msff_ctl_macro__width_1 take_itw_lat  (
	.scan_in(take_itw_lat_scanin),
	.scan_out(take_itw_lat_scanout),
	.din	(take_itw_g_in			),
	.dout	(ptake_itw_g			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_itw_g =
       ptake_itw_g & allow_trap &
       ~trlx_itw_wait & ~trlx_itw_last;

tlu_trl_ctl_msff_ctl_macro__width_1 take_otr_lat  (
	.scan_in(take_otr_lat_scanin),
	.scan_out(take_otr_lat_scanout),
	.din	(take_otr_in			),
	.dout	(ptake_otr			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_otr =
       ptake_otr & allow_trap;

assign take_any_dec[3:0] =
       real_trap[3:0];

assign take_any_dec_last[3:0] =
       real_trap_last[3:0];


////////////////////////////////////////////////////////////////////////////////
// Figure out which trap in the group occurred

assign take_por = 
	(| ( por_req_in[3:0] & reset_pre_trap[3:0])) & 
	take_reset;

assign take_por_dec[3:0] = 
	por_req_in[3:0] & reset_pre_trap[3:0] & {4 {take_reset}};

assign take_por_dec_last[3:0] =
       {4 {take_por_last}} & trap_taken3[3:0];

assign take_xir = 
	(| ( xir_req_in[3:0] & reset_pre_trap[3:0] & ~por_req_in[3:0])) &
	take_reset;

assign take_sir = 
	(| ( sir_req_in[3:0] & reset_pre_trap[3:0] & ~por_req_in[3:0] &
	    ~xir_req_in[3:0])) & take_reset;

assign take_ade = 
	(| (ade_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_iln = 
	(| (iln_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_ivt = 
	(| (ivt_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_mqr = 
	(| (mqr_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_dqr = 
	(| (dqr_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_rqr = 
	(| (rqr_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_eer = 
	(| (eer_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_ftt = 
	(| (ftt_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_hst = 
	(| (hst_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_tlz = 
	(| (tlz_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_sma = 
	(| (sma_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_cwq = 
	(| (cwq_req_in[3:0] & disrupt_pre_trap[3:0])) & take_disrupt;

assign take_dae = 
	(| (dae_req_in[3:0] & long_pre_trap[3:0])) & take_long;

assign take_fei = 
	(| (fei_req_in[3:0] & fgu_pre_trap[3:0])) & take_fgu;

assign take_fof = 
	(| (fof_req_in[3:0] & fgu_pre_trap[3:0])) & take_fgu;

assign take_don = 
	(| (pdon_req_in[3:0] & don_ret_pre_trap[3:0])) & take_don_ret;

assign take_ret = 
	(| (pret_req_in[3:0] & don_ret_pre_trap[3:0])) & take_don_ret;

assign take_htd = 
	(| (htd_req_in[3:0] & notrap_pre_trap[3:0])) & take_notrap;

// fpe_req because this is not a trap, but if a real FPU trap
// catches up, then fpe is killed.  
// This led to a trap[03:00] without a take_fpe.
assign take_fpe = 
       (| (fpe_req[3:0] & notrap_pre_trap[3:0])) & take_notrap;

assign take_lsr = 
       (| (lsr_req_in[3:0] & notrap_pre_trap[3:0])) & take_notrap & 
       ~take_fpe;

assign take_itw =
       ( | (itw_req_in[3:0] & itw_pre_trap[3:0])) & take_itw_g;

assign take_res = 
       (| (res_req_in[3:0] & notrap_pre_trap[3:0])) & take_notrap & 
       ~take_fpe;

assign take_ssr = 
       (| (ssr_req_in_for_taken[3:0] & notrap_pre_trap[3:0])) & 
       take_notrap & 
       ~take_fpe;
assign take_ssr_por = 
       take_por & (| (ssr_req_in_for_taken[3:0] & reset_pre_trap[3:0]));

assign take_nns = 
       (| (nns_req_in[3:0] & notrap_pre_trap[3:0])) & take_notrap &
       ~take_fpe;

assign take_icp = 
       (| (icp_req_in[3:0] & notrap_pre_trap[3:0])) & take_notrap;

assign take_ipe = 
	(| (ipe_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_iae = 
	(| (iae_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_ipv = 
	(| (ipv_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_inp = 
	(| (inp_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_iua = 
	(| (iua_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_iar = 
	(| (iar_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_irr = 
	(| (irr_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_mar = 
	(| (mar_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_mrr = 
	(| (mrr_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_pro = 
	(| (pro_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_ill = 
	(| (ill_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_fpd = 
	(| (fpd_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_snn = 
	(| (snn_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_sno = 
	(| (sno_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_fnn = 
	(| (fnn_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_fno = 
	(| (fno_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_clw = 
	(| (clw_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_ldf = 
	(| (ldf_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_stf = 
	(| (stf_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_dap = 
	(| (dap_req_in[3:0] & other_pre_trap[3:0])) & take_other & 
       ~take_pra;

assign take_vaw = 
	(| (vaw_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_iaw = 
	(| (iaw_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_paw = 
	(| (paw_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_maa = 
	(| (maa_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_pra = 
	(| (pra_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_dia = 
	(| (dia_req_in[3:0] & other_pre_trap[3:0])) & take_other & 
	~take_pra;

assign take_ups = 
	(| (ups_req_in[3:0] & other_pre_trap[3:0])) & take_other & 
	~take_pra;

assign take_dpv = 
	(| (dpv_req_in[3:0] & other_pre_trap[3:0])) & take_other & 
	~take_pra;

assign take_dnc = 
	(| (dnc_req_in[3:0] & other_pre_trap[3:0])) & take_other & 
	~take_pra;

assign take_dnf = 
	(| (dnf_req_in[3:0] & other_pre_trap[3:0])) & take_other & 
	~take_pra;

assign take_dso = 
	(| (dso_req_in[3:0] & other_pre_trap[3:0])) & take_other & 
	~take_pra;

assign take_tof = 
	(| (tof_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_tcc = 
	(| (tcc_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_itm = 
	(| (itm_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_dtm = 
	(| (dtm_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_him = 
	(| (him_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_hdm = 
	(| (hdm_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_irt = 
	(| (irt_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_drt = 
	(| (drt_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_pmu = 
	(| (pmu_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_ime = 
	(| (ime_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_dme = 
	(| (dme_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_ibp = 
	(| (ibp_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_tct = 
	(| (tct_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_iit = 
	(| (iit_req_in[3:0] & other_pre_trap[3:0])) & take_other;

assign take_dit = 
	(| (dit_req_in[3:0] & other_pre_trap[3:0])) & take_other;

tlu_trl_ctl_msff_ctl_macro__width_1 take_pmu_lat  (
	.scan_in(take_pmu_lat_scanin),
	.scan_out(take_pmu_lat_scanout),
	.din	(take_pmu			),
	.dout	(take_pmu_last			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_pmu_trap_taken[3:0] =
       trap_taken3[3:0] & {4 {take_pmu_last}};

tlu_trl_ctl_msff_ctl_macro__width_4 take_ivt_lat  (
	.scan_in(take_ivt_lat_scanin),
	.scan_out(take_ivt_lat_scanout),
	.din	({take_sma,
		  take_cwq,
		  take_xir,
		  take_ftt}),
	.dout	({take_sma_last,
		  take_cwq_last,
		  take_xir_last,
		  take_ftt_last}		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_take_sma =
	take_sma_last;
assign trl_take_cwq =
	take_cwq_last;
assign trl_take_xir =
	take_xir_last;
assign trl_take_ftt =
	take_ftt_last;


////////////////////////////////////////////////////////////////////////////////
// Determine which thread traps

assign trap[3:0] = 
	({4 {take_reset  }} &   reset_pre_trap[3:0]) | 
	({4 {take_disrupt}} & disrupt_pre_trap[3:0]) | 
	({4 {take_div    }} &  divide_pre_trap[3:0]) | 
	({4 {take_long   }} &    long_pre_trap[3:0]) | 
	({4 {take_don_ret}} & don_ret_pre_trap[3:0]) | 
	({4 {take_notrap }} &  notrap_pre_trap[3:0]) | 
	({4 {take_itw_g  }} &     itw_pre_trap[3:0]) | 
	({4 {take_fgu    }} &     fgu_pre_trap[3:0]) | 
	({4 {take_other  }} &   other_pre_trap[3:0]) ;

// trap_not_por only used for TL, so must not have POR in it
assign take_rstnpor =
       take_reset & ~take_por;
assign trap_not_por[3:0] = 
	({4 {take_rstnpor}} &   reset_pre_trap[3:0]) | 
	({4 {take_disrupt}} & disrupt_pre_trap[3:0]) | 
	({4 {take_div    }} &  divide_pre_trap[3:0]) | 
	({4 {take_long   }} &    long_pre_trap[3:0]) | 
	({4 {take_fgu    }} &     fgu_pre_trap[3:0]) | 
	({4 {take_other  }} &   other_pre_trap[3:0]) ;

assign real_trap[3:0] = 
	({4 {take_reset  }} &   reset_pre_trap[3:0]) | 
	({4 {take_disrupt}} & disrupt_pre_trap[3:0]) | 
	({4 {take_div    }} &  divide_pre_trap[3:0]) | 
	({4 {take_long   }} &    long_pre_trap[3:0]) | 
	({4 {take_fgu    }} &     fgu_pre_trap[3:0]) | 
	({4 {take_other  }} &   other_pre_trap[3:0]) ;

assign trap_ndr[3:0] = 
	({4 {take_reset  }} &   reset_pre_trap[3:0]) | 
	({4 {take_disrupt}} & disrupt_pre_trap[3:0]) | 
	({4 {take_div    }} &  divide_pre_trap[3:0]) | 
	({4 {take_long   }} &    long_pre_trap[3:0]) | 
	({4 {take_notrap }} &  notrap_pre_trap[3:0]) | 
	({4 {take_itw_g  }} &     itw_pre_trap[3:0]) | 
	({4 {take_fgu    }} &     fgu_pre_trap[3:0]) | 
	({4 {take_other  }} &   other_pre_trap[3:0]) ;

assign trap_itw[3:0] = 
	({4 {take_itw_g  }} &     itw_pre_trap[3:0]) ;

assign trap_por_res_ssr[3:0] =
	({4 {take_por   }} &    reset_pre_trap[3:0]) |
	({4 {take_res   }} &   notrap_pre_trap[3:0]) |
	({4 {take_ssr   }} &   notrap_pre_trap[3:0]) ;

assign trap_taken_in[3:0] =
       trap[3:0] & ~(fei_or_fof_incoming[3:0] | dbz_incoming[3:0]);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 trap_taken_lat   (
	.scan_in(trap_taken_lat_scanin),
	.scan_out(trap_taken_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din  	(trap_taken_in		[3:0]	),
	.dout	(trap_taken		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 trap_taken0_lat   (
	.scan_in(trap_taken0_lat_scanin),
	.scan_out(trap_taken0_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din  	(trap_taken_in		[3:0]	),
	.dout	(trap_taken0		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 trap_taken1_lat   (
	.scan_in(trap_taken1_lat_scanin),
	.scan_out(trap_taken1_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din  	(trap_taken_in		[3:0]	),
	.dout	(trap_taken1		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 trap_taken2_lat   (
	.scan_in(trap_taken2_lat_scanin),
	.scan_out(trap_taken2_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din  	(trap_taken_in		[3:0]	),
	.dout	(trap_taken2		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 trap_taken3_lat   (
	.scan_in(trap_taken3_lat_scanin),
	.scan_out(trap_taken3_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din  	(trap_taken_in		[3:0]	),
	.dout	(trap_taken3		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 trap_taken4_lat   (
	.scan_in(trap_taken4_lat_scanin),
	.scan_out(trap_taken4_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din  	(trap_taken_in		[3:0]	),
	.dout	(trap_taken4		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 trap_taken5_lat   (
	.scan_in(trap_taken5_lat_scanin),
	.scan_out(trap_taken5_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din  	(trap_taken_in		[3:0]	),
	.dout	(trap_taken5		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 trap_itw_taken_lat   (
	.scan_in(trap_itw_taken_lat_scanin),
	.scan_out(trap_itw_taken_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din  	(trap_itw		[3:0]	),
	.dout	(trap_itw_taken		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_trap_taken[3:0] =
       trap_taken[3:0];

tlu_trl_ctl_msff_ctl_macro__width_1 take_reset_last_lat  (
	.scan_in(take_reset_last_lat_scanin),
	.scan_out(take_reset_last_lat_scanout),
	.din	(take_reset			),
	.dout	(take_reset_last		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

////////////////////////////////////////////////////////////////////////////////
// Generate trap type
//
//  The trap address is 
//	TBA<63:15> TL>0  TT(TL)  00000
//	63      15  14   13   5  4   0
//

assign trap_type_in[8:0] = 
	({9 {take_por}} & 9'h001) |
	({9 {take_xir}} & 9'h003) | 
	({9 {take_sir}} & 9'h004) |
	({9 {take_iln}} & {5'b00100, int_level_n[3:0]}) | 
	({9 {take_ivt}} & 9'h060) | 
	({9 {take_mqr}} & 9'h07c) | 
	({9 {take_dqr}} & 9'h07d) | 
	({9 {take_rqr}} & 9'h07e) | 
	({9 {take_eer}} & 9'h063) | 
	({9 {take_ftt}} & 9'h007) | 
	({9 {take_hst}} & 9'h05e) | 
	({9 {take_tlz}} & 9'h05f) | 
	({9 {take_cwq}} & 9'h03c) | 
	({9 {take_sma}} & 9'h03d) | 
	({9 {take_ade}} & 9'h040) | 
	({9 {take_ipe}} & 9'h029) | 
	({9 {take_dae}} & 9'h032) | 
	({9 {take_fei}} & 9'h021) | 
	({9 {take_fof}} & 9'h022) | 
	({9 {take_iae}} & 9'h00a) | 
	({9 {take_ipv}} & 9'h008) | 
	({9 {take_iua}} & 9'h00b) | 
	({9 {take_inp}} & 9'h00c) | 
	({9 {take_iar}} & 9'h00d) | 
	({9 {take_irr}} & 9'h00e) | 
	({9 {take_mar}} & 9'h02e) | 
	({9 {take_mrr}} & 9'h02d) | 
	({9 {take_pro}} & 9'h011) | 
	({9 {take_ill}} & 9'h010) | 
	({9 {take_fpd}} & 9'h020) |
	({9 {take_snn}} & {4'b0100, wstate[2:0], 2'b00}) |
	({9 {take_sno}} & {4'b0101, wstate[2:0], 2'b00}) |
	({9 {take_fnn}} & {4'b0110, wstate[2:0], 2'b00}) |
	({9 {take_fno}} & {4'b0111, wstate[2:0], 2'b00}) |
	({9 {take_clw}} & 9'h024) | 
	({9 {take_ldf}} & 9'h035) | 
	({9 {take_stf}} & 9'h036) | 
	({9 {take_dap}} & 9'h06c) | 
	({9 {take_vaw}} & 9'h062) | 
	({9 {take_iaw}} & 9'h075) | 
	({9 {take_paw}} & 9'h061) | 
	({9 {take_maa}} & 9'h034) | 
	({9 {take_pra}} & 9'h037) |
 	({9 {take_dia}} & 9'h014) | 
 	({9 {take_ups}} & 9'h03b) | 
 	({9 {take_dpv}} & 9'h015) | 
 	({9 {take_dnc}} & 9'h016) | 
 	({9 {take_dnf}} & 9'h017) | 
 	({9 {take_dso}} & 9'h030) | 
	({9 {take_tof}} & 9'h023) | 
	({9 {take_tcc}} & {1'b1, tcc_number[7:0]}) | 
	({9 {take_itm}} & 9'h064) |  
	({9 {take_dtm}} & 9'h068) |  
	({9 {take_him}} & 9'h009) |  
	({9 {take_hdm}} & 9'h031) |  
	({9 {take_irt}} & 9'h03e) |  
	({9 {take_drt}} & 9'h03f) |  
	({9 {take_pmu}} & 9'h04f) |
        ({9 {take_div}} & 9'h028) |
        ({9 {take_ime}} & 9'h071) |
        ({9 {take_dme}} & 9'h072) |
        ({9 {take_ibp}} & 9'h076) |
        ({9 {take_tct}} & 9'h074) |
        ({9 {take_iit}} & 9'h02a) |
        ({9 {take_dit}} & 9'h02b) ;

assign no_special_trap =
       ~next_trap_to_red & ~next_trap_to_err & ~priv_overflow_tl;

assign priv_overflow_tl =
       next_trap_to_hpriv & sip;

// XIR and POR at TL==MAXTL do NOT take WDR
// SIR at TL==MAXTL DOES take WDR
// All other traps  at TL== MAXTL take WDR
assign trap_type_for_pc_in[8:0] = 
	({9 {take_por                    }} & 9'h001) |
	({9 {take_xir                    }} & 9'h003) | 
	({9 {take_sir & ~next_trap_to_err}} & 9'h004) |
	({9 {take_sir &  next_trap_to_err}} & 9'h002) |
        ({9 {            no_special_trap }} & trap_type_in[8:0]) |
	({9 {take_otr &  next_trap_to_red}} & 9'h005) |
	({9 {take_otr &  next_trap_to_err}} & 9'h002) |
	({9 {take_otr &  priv_overflow_tl}} & 9'h002) ;

assign wstate[2:0] =
	({3 {real_trap[3]}} & fls_wstate3[2:0]) | 
	({3 {real_trap[2]}} & fls_wstate2[2:0]) | 
	({3 {real_trap[1]}} & fls_wstate1[2:0]) | 
	({3 {real_trap[0]}} & fls_wstate0[2:0]) ;

assign tcc_number[7:0] =
	({8 {real_trap[3]}} & fls_tcc_number_3[7:0]) | 
	({8 {real_trap[2]}} & fls_tcc_number_2[7:0]) | 
	({8 {real_trap[1]}} & fls_tcc_number_1[7:0]) | 
	({8 {real_trap[0]}} & fls_tcc_number_0[7:0]) ;

tlu_trl_ctl_msff_ctl_macro__width_9 trap_type_lat  (
	.scan_in(trap_type_lat_scanin),
	.scan_out(trap_type_lat_scanout),
	.din	(trap_type_in		[8:0]	),
	.dout	(trap_type		[8:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_9 trap_type_for_pc_lat  (
	.scan_in(trap_type_for_pc_lat_scanin),
	.scan_out(trap_type_for_pc_lat_scanout),
	.din	(trap_type_for_pc_in	[8:0]	),
	.dout	(trap_type_for_pc	[8:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// trl_trap_type goes into muxflop, so can be late
assign trl_trap_type[8:0] = 
	trap_type_for_pc[8:0];

// trl_tsa_trap_type goes into muxflop, so can be late
assign trl_tsa_trap_type[8:0] = 
	trap_type[8:0];


////////////////////////////////////////////////////////////////////////////////
// Maintain trap level

tlu_trl_ctl_msff_ctl_macro__width_4 hpstate_hpriv_lat  (
	.scan_in(hpstate_hpriv_lat_scanin),
	.scan_out(hpstate_hpriv_lat_scanout),
	.din	(tsd_hpstate_hpriv	[3:0]	),
	.dout	(hpstate_hpriv		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign h_wr_tl[3:0] =
       asi_wr_tl[3:0] &  hpstate_hpriv[3:0];
assign n_wr_tl[3:0] =
       asi_wr_tl[3:0] & ~hpstate_hpriv[3:0];

// Writes to TL when not in hyperprivileged mode saturate at MAXPTL (3'b010);
// writes to TL when in hyperprivileged mode saturate at MAXTL (3'b110)
// Saturation looks at bits 2:0 only
assign tl_h_wr_data[2:0] =
       {asi_wr_data[2:1], asi_wr_data[0] & ~(& asi_wr_data[2:1])};
assign tl_n_wr_data[2:0] =
       {1'b0, (| asi_wr_data[2:1]), asi_wr_data[0] & ~(| asi_wr_data[2:1])};

assign hold_tl[3:0] =
       ~(take_any_dec[3:0] | npc_sel_tnpc[3:0] | asi_wr_tl[3:0]);

assign tl3_incr[2:0] = 
	tl3[2:0] + {2'b00, tl3[2:0] != maxtl[2:0]};
assign tl3_decr[2:0] = 
	tl3[2:0] - {2'b00, tl3[2:0] != 3'b000};
assign tl3_in[2:0] = 
	({3 {take_por_dec    [3]                    }} & maxtl       [2:0]) | 
	({3 {take_any_dec    [3] & ~take_por_dec[3]}} & tl3_incr    [2:0]) |
	({3 {npc_sel_tnpc    [3]                    }} & tl3_decr    [2:0]) |
        ({3 {h_wr_tl         [3]                    }} & tl_h_wr_data[2:0]) |
        ({3 {n_wr_tl         [3]                    }} & tl_n_wr_data[2:0]) |
        ({3 {hold_tl         [3]                    }} & tl3         [2:0]) ;
assign tlz_in[3] =
       (tl3[2:0] == 3'b000) & tsd_hpstate_tlz[3] & ~ptlz_req_in[3];

assign tl2_incr[2:0] = 
	tl2[2:0] + {2'b00, tl2[2:0] != maxtl[2:0]};
assign tl2_decr[2:0] = 
	tl2[2:0] - {2'b00, tl2[2:0] != 3'b000};
assign tl2_in[2:0] = 
	({3 {take_por_dec    [2]                    }} & maxtl       [2:0]) | 
	({3 {take_any_dec    [2] & ~take_por_dec[2]}} & tl2_incr    [2:0]) |
	({3 {npc_sel_tnpc    [2]                    }} & tl2_decr    [2:0]) |
        ({3 {h_wr_tl         [2]                    }} & tl_h_wr_data[2:0]) |
        ({3 {n_wr_tl         [2]                    }} & tl_n_wr_data[2:0]) |
        ({3 {hold_tl         [2]                    }} & tl2         [2:0]) ;
assign tlz_in[2] =
       (tl2[2:0] == 3'b000) & tsd_hpstate_tlz[2] & ~ptlz_req_in[2];

assign tl1_incr[2:0] = 
	tl1[2:0] + {2'b00, tl1[2:0] != maxtl[2:0]};
assign tl1_decr[2:0] = 
	tl1[2:0] - {2'b00, tl1[2:0] != 3'b000};
assign tl1_in[2:0] = 
	({3 {take_por_dec    [1]                    }} & maxtl       [2:0]) | 
	({3 {take_any_dec    [1] & ~take_por_dec[1]}} & tl1_incr    [2:0]) |
	({3 {npc_sel_tnpc    [1]                    }} & tl1_decr    [2:0]) |
        ({3 {h_wr_tl         [1]                    }} & tl_h_wr_data[2:0]) |
        ({3 {n_wr_tl         [1]                    }} & tl_n_wr_data[2:0]) |
        ({3 {hold_tl         [1]                    }} & tl1         [2:0]) ;
assign tlz_in[1] =
       (tl1[2:0] == 3'b000) & tsd_hpstate_tlz[1] & ~ptlz_req_in[1];

assign tl0_incr[2:0] = 
	tl0[2:0] + {2'b00, tl0[2:0] != maxtl[2:0]};
assign tl0_decr[2:0] = 
	tl0[2:0] - {2'b00, tl0[2:0] != 3'b000};
assign tl0_in[2:0] = 
	({3 {take_por_dec    [0]                    }} & maxtl       [2:0]) | 
	({3 {take_any_dec    [0] & ~take_por_dec[0]}} & tl0_incr    [2:0]) |
	({3 {npc_sel_tnpc    [0]                    }} & tl0_decr    [2:0]) |
        ({3 {h_wr_tl         [0]                    }} & tl_h_wr_data[2:0]) |
        ({3 {n_wr_tl         [0]                    }} & tl_n_wr_data[2:0]) |
        ({3 {hold_tl         [0]                    }} & tl0         [2:0]) ;
assign tlz_in[0] =
       (tl0[2:0] == 3'b000) & tsd_hpstate_tlz[0] & ~ptlz_req_in[0];

tlu_trl_ctl_msff_ctl_macro__width_12 tl_lat  (
	.scan_in(tl_lat_scanin),
	.scan_out(tl_lat_scanout),
	.din	({tl3_in	[2:0],
		  tl2_in	[2:0],
		  tl1_in	[2:0],
		  tl0_in	[2:0]}),
	.dout	({tl3		[2:0],
		  tl2		[2:0],
		  tl1		[2:0],
		  tl0		[2:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


tlu_trl_ctl_msff_ctl_macro__width_4 tlz_lat  (
	.scan_in(tlz_lat_scanin),
	.scan_out(tlz_lat_scanout),
	.din	(tlz_in		[3:0]	),
	.dout	(tlz		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_tlz_exc[3:0] =
       tlz[3:0] & ~hpstate_hpriv[3:0];

// Since tl has already changed, check for tl > 1 when not in hpriv mode
assign trl_tl_gt_0 =
       (thread_sel[3] & (| tl3[2:1]) & ~hpstate_hpriv[3]) |
       (thread_sel[2] & (| tl2[2:1]) & ~hpstate_hpriv[2]) |
       (thread_sel[1] & (| tl1[2:1]) & ~hpstate_hpriv[1]) |
       (thread_sel[0] & (| tl0[2:1]) & ~hpstate_hpriv[0]) ;

assign tl_gt_0_in[3:0] =
       {(| tl3_in[2:0]), (| tl2_in[2:0]),  
	(| tl1_in[2:0]), (| tl0_in[2:0])};

assign trl_tl_eq_0[3:0] =
       ~tl_gt_0[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 tl_gt_0_last_lat  (
	.scan_in(tl_gt_0_last_lat_scanin),
	.scan_out(tl_gt_0_last_lat_scanout),
	.din	(tl_gt_0_in	[3:0]	),
	.dout	(tl_gt_0	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_tl_gt_0[3:0] =
       tl_gt_0[3:0];	

assign tlu_mmu_tl_gt_0[3:0] =
       tl_gt_0[3:0];

assign trap_tl[2:0] = 
	({3 {trap_not_por[3]}} & tl3			[2:0]) |
	({3 {trap_not_por[2]}} & tl2			[2:0]) |
	({3 {trap_not_por[1]}} & tl1			[2:0]) |
	({3 {trap_not_por[0]}} & tl0			[2:0]) |
        ({3 {take_por          }} & maxtl_minus_one	[2:0]) ;

assign trap_tl_m1[2:0] = 
	({3 {trap_ndr[3]}} & tl3_decr[2:0]) |
	({3 {trap_ndr[2]}} & tl2_decr[2:0]) |
	({3 {trap_ndr[1]}} & tl1_decr[2:0]) |
	({3 {trap_ndr[0]}} & tl0_decr[2:0]) ;

assign rda_tl_m1[2:0] =
       ({3 { asi_tsa_tid[1] &  asi_tsa_tid[0]}} & tl3_decr[2:0]) |
       ({3 { asi_tsa_tid[1] & ~asi_tsa_tid[0]}} & tl2_decr[2:0]) |
       ({3 {~asi_tsa_tid[1] &  asi_tsa_tid[0]}} & tl1_decr[2:0]) |
       ({3 {~asi_tsa_tid[1] & ~asi_tsa_tid[0]}} & tl0_decr[2:0]) ;


////////////////////////////////////////////////////////////////////////////////
// Maintain GL (global level)

// Writes to GL look at 4 bits
// Writes when HPSTATE.HPRIV == 1'b1 saturate at 2'b11
// Writes when HPSTATE.HPRIV == 1'b0 saturate at 2'b10

// Need to delay GL write and trap update by two cycles to avoid 
// simultaneous GL update by done or retry (for a different thread)
assign wr_gl_data_in_in[1] =
       (| asi_wr_data[3:1]);
assign wr_gl_data_in_in[0] =
        ((| {asi_wr_data[3:2], asi_wr_data[0]}) & 
	 (| (asi_wr_gl[3:0] & hpstate_hpriv[3:0]))) |
	(~asi_wr_data[3] & ~asi_wr_data[2] & ~asi_wr_data[1] & 
	 asi_wr_data[0] & 
	 (| (asi_wr_gl[3:0] & ~hpstate_hpriv[3:0])));

assign gl_data_in_in[1:0] =
        ({2 {| asi_wr_gl        [3:0]}} & wr_gl_data_in_in	[1:0]) ;

assign update_gl_in_in[3:0] =
       asi_wr_gl[3:0];

tlu_trl_ctl_msff_ctl_macro__width_12 wr_gl_lat  (
	.scan_in(wr_gl_lat_scanin),
	.scan_out(wr_gl_lat_scanout),
	.din	({update_gl_in_in	[3:0],
		  update_gl_in		[3:0],
		  gl_data_in_in		[1:0],
		  gl_data_in		[1:0]}),
	.dout	({update_gl_in		[3:0],
		  update_gl		[3:0],
		  gl_data_in		[1:0],
		  gl_data		[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

// GL saturates at 2'b11 when in hypervisor mode, but at MAXPTL when not
assign maxglc[1:0] =
       {2 {other_trap | hpriv_last | take_reset_last | reset_trap}} | 
       maxptl[1:0];

assign take_anr_dec_last[3:0] =
       take_any_dec_last[3:0] & ~take_por_dec_last[3:0];

assign hold_gl[3:0] =
       ~(take_any_dec_last[3:0] | npc_sel_tnpc[3:0] | update_gl[3:0]);

// Hold GL for two cycles so ECC errors can prevent GL update
// Saturate when not returning to hyperprivileged mode
assign saturate_restore =
       (pgl_rest_in[1:0] > maxptl[1:0]) & ~tsd_htstate_hpriv;
assign gl_rest_in[1:0] =
       ({ 2 { saturate_restore}} & maxptl     [1:0]) | 
       ({ 2 {~saturate_restore}} & pgl_rest_in[1:0]) ;
tlu_trl_ctl_msff_ctl_macro__width_4 gl_rest_lat  (
	.scan_in(gl_rest_lat_scanin),
	.scan_out(gl_rest_lat_scanout),
	.din	({tsa_gl	[1:0],
		  gl_rest_in	[1:0]}),
	.dout	({pgl_rest_in	[1:0],
		  gl_rest	[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign gl3_incr[1:0] = 
	(gl3[1:0] + {1'b0, gl3[1:0] < maxglc[1:0]}) & 
	{1'b1, ~gl3[1] | maxglc[0]};
assign gl3_in[1:0] = 
	({2 {take_por_dec_last[3]}} & maxgl	[1:0]) | 
	({2 {take_anr_dec_last[3]}} & gl3_incr	[1:0]) |
	({2 {npc_sel_tnpc     [3]}} & gl_rest	[1:0]) |
        ({2 {update_gl        [3]}} & gl_data	[1:0]) |
	({2 {hold_gl          [3]}} & gl3    	[1:0]) ;

assign gl2_incr[1:0] = 
	(gl2[1:0] + {1'b0, gl2[1:0] < maxglc[1:0]}) & 
	{1'b1, ~gl2[1] | maxglc[0]};
assign gl2_in[1:0] = 
	({2 {take_por_dec_last[2]}} & maxgl	[1:0]) | 
	({2 {take_anr_dec_last[2]}} & gl2_incr	[1:0]) |
	({2 {npc_sel_tnpc     [2]}} & gl_rest	[1:0]) |
        ({2 {update_gl        [2]}} & gl_data	[1:0]) |
	({2 {hold_gl          [2]}} & gl2    	[1:0]) ;

assign gl1_incr[1:0] = 
	(gl1[1:0] + {1'b0, gl1[1:0] < maxglc[1:0]}) & 
	{1'b1, ~gl1[1] | maxglc[0]};
assign gl1_in[1:0] = 
	({2 {take_por_dec_last[1]}} & maxgl	[1:0]) | 
	({2 {take_anr_dec_last[1]}} & gl1_incr	[1:0]) |
	({2 {npc_sel_tnpc     [1]}} & gl_rest	[1:0]) |
        ({2 {update_gl        [1]}} & gl_data	[1:0]) |
	({2 {hold_gl          [1]}} & gl1    	[1:0]) ;

assign gl0_incr[1:0] = 
	(gl0[1:0] + {1'b0, gl0[1:0] < maxglc[1:0]}) & 
	{1'b1, ~gl0[1] | maxglc[0]};
assign gl0_in[1:0] = 
	({2 {take_por_dec_last[0]}} & maxgl	[1:0]) | 
	({2 {take_anr_dec_last[0]}} & gl0_incr	[1:0]) |
	({2 {npc_sel_tnpc     [0]}} & gl_rest	[1:0]) |
        ({2 {update_gl        [0]}} & gl_data	[1:0]) |
	({2 {hold_gl          [0]}} & gl0    	[1:0]) ;

assign trap_gl_in[1:0] = 
	({2 {real_trap[3]}} & gl3[1:0]) |
	({2 {real_trap[2]}} & gl2[1:0]) |
	({2 {real_trap[1]}} & gl1[1:0]) |
	({2 {real_trap[0]}} & gl0[1:0]) ;

tlu_trl_ctl_msff_ctl_macro__width_10 gl_lat  ( 
	.scan_in(gl_lat_wmr_scanin),
	.scan_out(gl_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	({trap_gl_in	[1:0],
		  gl3_in	[1:0],
		  gl2_in	[1:0],
		  gl1_in	[1:0],
		  gl0_in	[1:0]}),
	.dout	({trl_tsa_gl	[1:0],
		  gl3		[1:0],
		  gl2		[1:0],
		  gl1		[1:0],
		  gl0		[1:0]}),
  .l1clk(l1clk),
  .soclk(soclk)
);

assign trl_gl3[1:0] =
       gl3[1:0];
assign trl_gl2[1:0] =
       gl2[1:0];
assign trl_gl1[1:0] =
       gl1[1:0];
assign trl_gl0[1:0] =
       gl0[1:0];

assign tlu_gl3[1:0] =
       gl3[1:0];
assign tlu_gl2[1:0] =
       gl2[1:0];
assign tlu_gl1[1:0] =
       gl1[1:0];
assign tlu_gl0[1:0] =
       gl0[1:0];


////////////////////////////////////////////////////////////////////////////////
// Manage TSA read and write addresses

tlu_trl_ctl_msff_ctl_macro__width_1 mbist_run_lat  (
	.scan_in(mbist_run_lat_scanin),
	.scan_out(mbist_run_lat_scanout),
	.din	(mbi_run	),
	.dout	(mbist_run	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign wr_addr_in_in[4:0] = 
       {5 {| trap_ndr[3:0]}} & 	
       {trap_ndr[3] | trap_ndr[2], trap_ndr[3] | trap_ndr[1], 
	({3 {~next_trap_to_err}} & trap_tl   [2:0]) | 
	({3 { next_trap_to_err}} & trap_tl_m1[2:0])};
assign wr_addr_func_in[4:0] =
       ({5 {~rmw_tsa}} & wr_addr_in_p	[4:0]) | 
       ({5 { rmw_tsa}} & rmw_addr	[4:0]) ;
assign wr_addr_in[4:0] =
       (wr_addr_func_in	[4:0] & {5 {~mbist_run}}) | 
       (asi_mbist_addr	[4:0] & {5 { mbist_run}}) ;

tlu_trl_ctl_msff_ctl_macro__width_10 tsa_wr_addr_lat  (
	.scan_in(tsa_wr_addr_lat_scanin),
	.scan_out(tsa_wr_addr_lat_scanout),
	.din	({wr_addr_in_in	[4:0],
		  wr_addr_in	[4:0]}),
	.dout	({wr_addr_in_p	[4:0],
		  wr_addr	[4:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_tsa_wr_addr[4:0] = 
       wr_addr[4:0];


assign don_ret_tl_m1[2:0] = 
	({3 {don_ret_pre_trap[3]}} & tl3_decr[2:0]) |
	({3 {don_ret_pre_trap[2]}} & tl2_decr[2:0]) |
	({3 {don_ret_pre_trap[1]}} & tl1_decr[2:0]) |
	({3 {don_ret_pre_trap[0]}} & tl0_decr[2:0]) ;

assign rd_addr_in[4:0] = 
        ({5 {~asi_preempt_done_retry}} &
	 {don_ret_pre_trap[3] | don_ret_pre_trap[2], 
	  don_ret_pre_trap[3] | don_ret_pre_trap[1], 
	  don_ret_tl_m1[2:0]}) |
	({5 { asi_preempt_done_retry}} & 
	 {asi_tsa_rd_addr[4:3], 
	  ({3 {~asi_tsa_rd_iqr_ecc}} & rda_tl_m1[2:0]) | 
	  ({3 { asi_tsa_rd_iqr_ecc}} & asi_tsa_rd_addr[2:0])}) ;

tlu_trl_ctl_msff_ctl_macro__width_5 tsa_rd_addr_lat  (
	.scan_in(tsa_rd_addr_lat_scanin),
	.scan_out(tsa_rd_addr_lat_scanout),
	.din	(rd_addr_in	[4:0]	),
	.dout	(rd_addr	[4:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_tsa_rd_addr[4:0] = 
	rd_addr_in[4:0] ;


tlu_trl_ctl_msff_ctl_macro__width_5 rmw_addr_lat  (
	.scan_in(rmw_addr_lat_scanin),
	.scan_out(rmw_addr_lat_scanout),
	.din	(rd_addr	[4:0]),
	.dout	(rmw_addr	[4:0]),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_2 rmw_tsa_lat  (
	.scan_in(rmw_tsa_lat_scanin),
	.scan_out(rmw_tsa_lat_scanout),
	.din	({asi_rmw_tsa, 
		  rmw_next}		),
	.dout	({rmw_next,
		  rmw_tsa}		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_rmw_tsa =
       rmw_tsa;


////////////////////////////////////////////////////////////////////////////////
// Processor Interrupt Level register

assign pil3_in[3:0] =
        ({4 { asi_wr_pil[3]}} & asi_wr_data	[3:0]) |
	({4 {~asi_wr_pil[3]}} & pil3		[3:0]) ;

assign pil2_in[3:0] =
        ({4 { asi_wr_pil[2]}} & asi_wr_data	[3:0]) |
	({4 {~asi_wr_pil[2]}} & pil2		[3:0]) ;

assign pil1_in[3:0] =
        ({4 { asi_wr_pil[1]}} & asi_wr_data	[3:0]) |
	({4 {~asi_wr_pil[1]}} & pil1		[3:0]) ;

assign pil0_in[3:0] =
        ({4 { asi_wr_pil[0]}} & asi_wr_data	[3:0]) |
	({4 {~asi_wr_pil[0]}} & pil0		[3:0]) ;

tlu_trl_ctl_msff_ctl_macro__width_4 pil3_lat  ( 
	.scan_in(pil3_lat_wmr_scanin),
	.scan_out(pil3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(pil3_in	[3:0]	),
	.dout	(pil3		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 pil2_lat  ( 
	.scan_in(pil2_lat_wmr_scanin),
	.scan_out(pil2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(pil2_in	[3:0]	),
	.dout	(pil2		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 pil1_lat  ( 
	.scan_in(pil1_lat_wmr_scanin),
	.scan_out(pil1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(pil1_in	[3:0]	),
	.dout	(pil1		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 pil0_lat  ( 
	.scan_in(pil0_lat_wmr_scanin),
	.scan_out(pil0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(pil0_in	[3:0]	),
	.dout	(pil0		[3:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Softint register

// Encode HSTICK/STICK/TICK data
// 05    = Valid for disrupt ECC exception
// 04:03 = HSTICK/STICK/TICK
// 02    = Valid for precise ECC exception
// 01:00 = TID
assign tic_compare_in[5:0] =
       {(tic_addr[2] == thread_group) & ~tic_not_valid,
	tic_addr[4:3],			
	(tic_addr[2] == thread_group) & tic_match & ~tic_not_valid,
	tic_addr[1:0]};			

tlu_trl_ctl_msff_ctl_macro__width_6 tic_compare_lat  (
	.scan_in(tic_compare_lat_scanin),
	.scan_out(tic_compare_lat_scanout),
	.din	(tic_compare_in	[5:0]	),
	.dout	(tic_compare	[5:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


// STICK_CMPR
assign tick3_compare[16] =
       (tic_compare[4:3] == 2'b01) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b11) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[3]);
// TICK_CMPR
assign tick3_compare[0] =
       (tic_compare[4:3] == 2'b00) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b11) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[3]);
assign tick3_compare[15:1] = 15'h0000;
assign softint3_mux[16:0] =
        ({17 { asi_wr_softint		[3]}} & asi_wr_data	[16:0]	) |
	({17 { asi_wr_set_softint	[3]}} & asi_wr_data	[16:0]	) |
	({17 {~asi_wr_softint		[3]}} & softint3	[16:0]	) |
        ({1'b0, fls_pmu_request[3], {15 {1'b0}}}			) ;
assign softint3_mask[16:0] = 	 
        ({17 {~asi_wr_clear_softint	[3]}} 				) |
	({17 { asi_wr_clear_softint	[3]}} & ~asi_wr_data	[16:0]	) ;
assign softint3_in[16:0] =
       (softint3_mux[16:0] & softint3_mask[16:0]) | tick3_compare[16:0];

// STICK_CMPR
assign tick2_compare[16] =
       (tic_compare[4:3] == 2'b01) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b10) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[2]);
// TICK_CMPR
assign tick2_compare[0] =
       (tic_compare[4:3] == 2'b00) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b10) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[2]);
assign tick2_compare[15:1] = 15'h0000;
assign softint2_mux[16:0] =
        ({17 { asi_wr_softint		[2]}} & asi_wr_data	[16:0]	) |
	({17 { asi_wr_set_softint	[2]}} & asi_wr_data	[16:0]	) |
	({17 {~asi_wr_softint		[2]}} & softint2	[16:0]	) |
        ({1'b0, fls_pmu_request[2], {15 {1'b0}}}			) ;
assign softint2_mask[16:0] = 	 
        ({17 {~asi_wr_clear_softint	[2]}} 				) |
	({17 { asi_wr_clear_softint	[2]}} & ~asi_wr_data	[16:0]	) ;
assign softint2_in[16:0] =
       (softint2_mux[16:0] & softint2_mask[16:0]) | tick2_compare[16:0];

// STICK_CMPR
assign tick1_compare[16] =
       (tic_compare[4:3] == 2'b01) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b01) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[1]);
// TICK_CMPR
assign tick1_compare[0] =
       (tic_compare[4:3] == 2'b00) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b01) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[1]);
assign tick1_compare[15:1] = 15'h0000;
assign softint1_mux[16:0] =
        ({17 { asi_wr_softint		[1]}} & asi_wr_data	[16:0]	) |
	({17 { asi_wr_set_softint	[1]}} & asi_wr_data	[16:0]	) |
	({17 {~asi_wr_softint		[1]}} & softint1	[16:0]	) |
        ({1'b0, fls_pmu_request[1], {15 {1'b0}}}			) ;
assign softint1_mask[16:0] = 	 
        ({17 {~asi_wr_clear_softint	[1]}} 				) |
	({17 { asi_wr_clear_softint	[1]}} & ~asi_wr_data	[16:0]	) ;
assign softint1_in[16:0] =
       (softint1_mux[16:0] & softint1_mask[16:0]) | tick1_compare[16:0];

// STICK_CMPR
assign tick0_compare[16] =
       (tic_compare[4:3] == 2'b01) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b00) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[0]);
// TICK_CMPR
assign tick0_compare[0] =
       (tic_compare[4:3] == 2'b00) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b00) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[0]);
assign tick0_compare[15:1] = 15'h0000;
assign softint0_mux[16:0] =
        ({17 { asi_wr_softint		[0]}} & asi_wr_data	[16:0]	) |
	({17 { asi_wr_set_softint	[0]}} & asi_wr_data	[16:0]	) |
	({17 {~asi_wr_softint		[0]}} & softint0	[16:0]	) |
        ({1'b0, fls_pmu_request[0], {15 {1'b0}}}			) ;
assign softint0_mask[16:0] = 	 
        ({17 {~asi_wr_clear_softint	[0]}} 				) |
	({17 { asi_wr_clear_softint	[0]}} & ~asi_wr_data	[16:0]	) ;
assign softint0_in[16:0] =
       (softint0_mux[16:0] & softint0_mask[16:0]) | tick0_compare[16:0];

tlu_trl_ctl_msff_ctl_macro__width_17 softint3_lat  ( 
	.scan_in(softint3_lat_wmr_scanin),
	.scan_out(softint3_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(softint3_in		[16:0]	),
	.dout	(softint3		[16:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_17 softint2_lat  ( 
	.scan_in(softint2_lat_wmr_scanin),
	.scan_out(softint2_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(softint2_in		[16:0]	),
	.dout	(softint2		[16:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_17 softint1_lat  ( 
	.scan_in(softint1_lat_wmr_scanin),
	.scan_out(softint1_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(softint1_in		[16:0]	),
	.dout	(softint1		[16:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_17 softint0_lat  ( 
	.scan_in(softint0_lat_wmr_scanin),
	.scan_out(softint0_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	(softint0_in		[16:0]	),
	.dout	(softint0		[16:0]	),
  .l1clk(l1clk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// interrupt_level_n
// Only take interrupts that are larger than the value in PIL

tlu_trl_ctl_msff_ctl_macro__width_4 pstate_ie_lat  (
	.scan_in(pstate_ie_lat_scanin),
	.scan_out(pstate_ie_lat_scanout),
	.din	(tsd_pstate_ie		[3:0]	),
	.dout	(pstate_ie		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign pil3_mask[15:1] =
       {15 {~hpstate_hpriv[3] & pstate_ie[3] & ~trap_taken3[3]}} &
       {~(( pil3[3] &  pil3[2] &  pil3[1] &  pil3[0]) ),	// 15
	~(( pil3[3] &  pil3[2] &  pil3[1]            ) ),	// 15-14
	~(( pil3[3] &  pil3[2] &  pil3[1]            ) |	
	  ( pil3[3] &  pil3[2] &              pil3[0]) ),	// 15-14,13
	~(( pil3[3] &  pil3[2]                        ) ),	// 15-12
	~(( pil3[3] &  pil3[2]                        ) |
	  ( pil3[3] &              pil3[1] &  pil3[0]) ),	// 15-12,11
	~(( pil3[3] &  pil3[2]                        ) |
	  ( pil3[3] &              pil3[1]            ) ),	// 15-12,11-10
	~(( pil3[3] &  pil3[2]                        ) |
	  ( pil3[3] &              pil3[1]            ) |
	  ( pil3[3] &                          pil3[0]) ),	// 15-12,11-10,9
	~(( pil3[3]                                    ) ),	// 15-8
	~(( pil3[3]                                    ) |
	  (             pil3[2] &  pil3[1] &  pil3[0]) ),	// 15-8,7
	~(( pil3[3]                                    ) |
	  (             pil3[2] &  pil3[1]            ) ),	// 15-8,7-6
	~(( pil3[3]                                    ) |
	  (             pil3[2] &  pil3[1]            ) |
	  (             pil3[2] &              pil3[0]) ),	// 15-8,7-6,5
	~(( pil3[3]                                    ) |
	  (             pil3[2]                        ) ),	// 15-8,7-4
	~(( pil3[3]                                    ) |
	  (             pil3[2]                        ) |
	  (                         pil3[1] &  pil3[0]) ),	// 15-8,7-4,3
	~(( pil3[3]                                    ) |
	  (             pil3[2]                        ) |
	  (                         pil3[1]            ) ),	// 15-8,7-4,3-2
	~(( pil3[3]                                    ) |
	  (             pil3[2]                        ) |
	  (                         pil3[1]            ) |
	  (                                     pil3[0]) )};	//15-8,7-4,3-2,1

assign pil2_mask[15:1] =
       {15 {~hpstate_hpriv[2] & pstate_ie[2] & ~trap_taken3[2]}} &
       {~(( pil2[3] &  pil2[2] &  pil2[1] &  pil2[0]) ),	// 15
	~(( pil2[3] &  pil2[2] &  pil2[1]            ) ),	// 15-14
	~(( pil2[3] &  pil2[2] &  pil2[1]            ) |	
	  ( pil2[3] &  pil2[2] &              pil2[0]) ),	// 15-14,13
	~(( pil2[3] &  pil2[2]                        ) ),	// 15-12
	~(( pil2[3] &  pil2[2]                        ) |
	  ( pil2[3] &              pil2[1] &  pil2[0]) ),	// 15-12,11
	~(( pil2[3] &  pil2[2]                        ) |
	  ( pil2[3] &              pil2[1]            ) ),	// 15-12,11-10
	~(( pil2[3] &  pil2[2]                        ) |
	  ( pil2[3] &              pil2[1]            ) |
	  ( pil2[3] &                          pil2[0]) ),	// 15-12,11-10,9
	~(( pil2[3]                                    ) ),	// 15-8
	~(( pil2[3]                                    ) |
	  (             pil2[2] &  pil2[1] &  pil2[0]) ),	// 15-8,7
	~(( pil2[3]                                    ) |
	  (             pil2[2] &  pil2[1]            ) ),	// 15-8,7-6
	~(( pil2[3]                                    ) |
	  (             pil2[2] &  pil2[1]            ) |
	  (             pil2[2] &              pil2[0]) ),	// 15-8,7-6,5
	~(( pil2[3]                                    ) |
	  (             pil2[2]                        ) ),	// 15-8,7-4
	~(( pil2[3]                                    ) |
	  (             pil2[2]                        ) |
	  (                         pil2[1] &  pil2[0]) ),	// 15-8,7-4,3
	~(( pil2[3]                                    ) |
	  (             pil2[2]                        ) |
	  (                         pil2[1]            ) ),	// 15-8,7-4,3-2
	~(( pil2[3]                                    ) |
	  (             pil2[2]                        ) |
	  (                         pil2[1]            ) |
	  (                                     pil2[0]) )};	//15-8,7-4,3-2,1

assign pil1_mask[15:1] =
       {15 {~hpstate_hpriv[1] & pstate_ie[1] & ~trap_taken3[1]}} &
       {~(( pil1[3] &  pil1[2] &  pil1[1] &  pil1[0]) ),	// 15
	~(( pil1[3] &  pil1[2] &  pil1[1]            ) ),	// 15-14
	~(( pil1[3] &  pil1[2] &  pil1[1]            ) |	
	  ( pil1[3] &  pil1[2] &              pil1[0]) ),	// 15-14,13
	~(( pil1[3] &  pil1[2]                        ) ),	// 15-12
	~(( pil1[3] &  pil1[2]                        ) |
	  ( pil1[3] &              pil1[1] &  pil1[0]) ),	// 15-12,11
	~(( pil1[3] &  pil1[2]                        ) |
	  ( pil1[3] &              pil1[1]            ) ),	// 15-12,11-10
	~(( pil1[3] &  pil1[2]                        ) |
	  ( pil1[3] &              pil1[1]            ) |
	  ( pil1[3] &                          pil1[0]) ),	// 15-12,11-10,9
	~(( pil1[3]                                    ) ),	// 15-8
	~(( pil1[3]                                    ) |
	  (             pil1[2] &  pil1[1] &  pil1[0]) ),	// 15-8,7
	~(( pil1[3]                                    ) |
	  (             pil1[2] &  pil1[1]            ) ),	// 15-8,7-6
	~(( pil1[3]                                    ) |
	  (             pil1[2] &  pil1[1]            ) |
	  (             pil1[2] &              pil1[0]) ),	// 15-8,7-6,5
	~(( pil1[3]                                    ) |
	  (             pil1[2]                        ) ),	// 15-8,7-4
	~(( pil1[3]                                    ) |
	  (             pil1[2]                        ) |
	  (                         pil1[1] &  pil1[0]) ),	// 15-8,7-4,3
	~(( pil1[3]                                    ) |
	  (             pil1[2]                        ) |
	  (                         pil1[1]            ) ),	// 15-8,7-4,3-2
	~(( pil1[3]                                    ) |
	  (             pil1[2]                        ) |
	  (                         pil1[1]            ) |
	  (                                     pil1[0]) )};	//15-8,7-4,3-2,1

assign pil0_mask[15:1] =
       {15 {~hpstate_hpriv[0] & pstate_ie[0] & ~trap_taken3[0]}} &
       {~(( pil0[3] &  pil0[2] &  pil0[1] &  pil0[0]) ),	// 15
	~(( pil0[3] &  pil0[2] &  pil0[1]            ) ),	// 15-14
	~(( pil0[3] &  pil0[2] &  pil0[1]            ) |	
	  ( pil0[3] &  pil0[2] &              pil0[0]) ),	// 15-14,13
	~(( pil0[3] &  pil0[2]                        ) ),	// 15-12
	~(( pil0[3] &  pil0[2]                        ) |
	  ( pil0[3] &              pil0[1] &  pil0[0]) ),	// 15-12,11
	~(( pil0[3] &  pil0[2]                        ) |
	  ( pil0[3] &              pil0[1]            ) ),	// 15-12,11-10
	~(( pil0[3] &  pil0[2]                        ) |
	  ( pil0[3] &              pil0[1]            ) |
	  ( pil0[3] &                          pil0[0]) ),	// 15-12,11-10,9
	~(( pil0[3]                                    ) ),	// 15-8
	~(( pil0[3]                                    ) |
	  (             pil0[2] &  pil0[1] &  pil0[0]) ),	// 15-8,7
	~(( pil0[3]                                    ) |
	  (             pil0[2] &  pil0[1]            ) ),	// 15-8,7-6
	~(( pil0[3]                                    ) |
	  (             pil0[2] &  pil0[1]            ) |
	  (             pil0[2] &              pil0[0]) ),	// 15-8,7-6,5
	~(( pil0[3]                                    ) |
	  (             pil0[2]                        ) ),	// 15-8,7-4
	~(( pil0[3]                                    ) |
	  (             pil0[2]                        ) |
	  (                         pil0[1] &  pil0[0]) ),	// 15-8,7-4,3
	~(( pil0[3]                                    ) |
	  (             pil0[2]                        ) |
	  (                         pil0[1]            ) ),	// 15-8,7-4,3-2
	~(( pil0[3]                                    ) |
	  (             pil0[2]                        ) |
	  (                         pil0[1]            ) |
	  (                                     pil0[0]) )};	//15-8,7-4,3-2,1

assign {pil3_mask[16], pil3_mask[0]} = 
       {pil3_mask[14], pil3_mask[14]};
assign {pil2_mask[16], pil2_mask[0]} = 
       {pil2_mask[14], pil2_mask[14]};
assign {pil1_mask[16], pil1_mask[0]} = 
       {pil1_mask[14], pil1_mask[14]};
assign {pil0_mask[16], pil0_mask[0]} = 
       {pil0_mask[14], pil0_mask[14]};

assign trl_pil_mask_15[3:0] =
       {pil3_mask[15], pil2_mask[15], pil1_mask[15], pil0_mask[15]};

assign pmu_trap_mask_d =
       (pil3_mask[15] &  fls_tid_d[1] &  fls_tid_d[0]) |
       (pil2_mask[15] &  fls_tid_d[1] & ~fls_tid_d[0]) |
       (pil1_mask[15] & ~fls_tid_d[1] &  fls_tid_d[0]) |
       (pil0_mask[15] & ~fls_tid_d[1] & ~fls_tid_d[0]) ;

tlu_trl_ctl_msff_ctl_macro__width_1 pmu_trap_mask_lat  (
	.scan_in(pmu_trap_mask_lat_scanin),
	.scan_out(pmu_trap_mask_lat_scanout),
	.din	(pmu_trap_mask_d		),
	.dout	(pmu_trap_mask_e		),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_pmu_trap_mask_e = 
       pmu_trap_mask_e;  

assign sim3[15] =
       softint3[15]    & pil3_mask[15];
assign sim3[14] =
       (softint3[16] & pil3_mask[16]) | 
       (softint3[14] & pil3_mask[14]) | 
       (softint3[0] & pil3_mask[0]);
assign sim3[13:1] =
       softint3[13:1] & pil3_mask[13:1];

assign sim2[15] =
       softint2[15]    & pil2_mask[15];
assign sim2[14] =
       (softint2[16] & pil2_mask[16]) | 
       (softint2[14] & pil2_mask[14]) | 
       (softint2[0] & pil2_mask[0]);
assign sim2[13:1] =
       softint2[13:1] & pil2_mask[13:1];

assign sim1[15] =
       softint1[15]    & pil1_mask[15];
assign sim1[14] =
       (softint1[16] & pil1_mask[16]) | 
       (softint1[14] & pil1_mask[14]) | 
       (softint1[0] & pil1_mask[0]);
assign sim1[13:1] =
       softint1[13:1] & pil1_mask[13:1];

assign sim0[15] =
       softint0[15]    & pil0_mask[15];
assign sim0[14] =
       (softint0[16] & pil0_mask[16]) | 
       (softint0[14] & pil0_mask[14]) | 
       (softint0[0] & pil0_mask[0]);
assign sim0[13:1] =
       softint0[13:1] & pil0_mask[13:1];

assign trl_iln_exc[3:0] =
       {(| sim3[15:1]), (| sim2[15:1]), (| sim1[15:1]), (| sim0[15:1])};

// Encode int level (leading one's detector)
assign int_level_n_3[3] =
       (| sim3[15:8]);

assign int_level_n_3[2] =
       (| sim3[15:12]) | 
       ((| sim3[7:4]) & ~(| sim3[11:8]));

assign int_level_n_3[1] = 
       (| sim3[15:14]) |
       ((| sim3[11:10]) & ~(| sim3[13:12])) |
       ((| sim3[7:6]) & ~(| {sim3[13:12], sim3[9:8]})) |
       ((| sim3[3:2]) & ~(| {sim3[13:12], sim3[9:8], sim3[5:4]}));

assign int_level_n_3[0] =
       sim3[15] |
       (sim3[13] & ~(  {sim3[14]})) |
       (sim3[11] & ~(| {sim3[14], sim3[12]})) |
       (sim3[9] & ~(| {sim3[14], sim3[12], sim3[10]})) |
       (sim3[7] & ~(| {sim3[14], sim3[12], sim3[10], sim3[8]})) |
       (sim3[5] & ~(| {sim3[14], sim3[12], sim3[10], sim3[8], sim3[6]})) |
       (sim3[3] & ~(| {sim3[14], sim3[12], sim3[10], sim3[8], sim3[6], 
			sim3[4]})) |
       (sim3[1] & ~(| {sim3[14], sim3[12], sim3[10], sim3[8], sim3[6], 
			sim3[4], sim3[2]}));

assign int_level_n_2[3] =
       (| sim2[15:8]);

assign int_level_n_2[2] =
       (| sim2[15:12]) | 
       ((| sim2[7:4]) & ~(| sim2[11:8]));

assign int_level_n_2[1] = 
       (| sim2[15:14]) |
       ((| sim2[11:10]) & ~(| sim2[13:12])) |
       ((| sim2[7:6]) & ~(| {sim2[13:12], sim2[9:8]})) |
       ((| sim2[3:2]) & ~(| {sim2[13:12], sim2[9:8], sim2[5:4]}));

assign int_level_n_2[0] =
       sim2[15] |
       (sim2[13] & ~(  {sim2[14]})) |
       (sim2[11] & ~(| {sim2[14], sim2[12]})) |
       (sim2[9] & ~(| {sim2[14], sim2[12], sim2[10]})) |
       (sim2[7] & ~(| {sim2[14], sim2[12], sim2[10], sim2[8]})) |
       (sim2[5] & ~(| {sim2[14], sim2[12], sim2[10], sim2[8], sim2[6]})) |
       (sim2[3] & ~(| {sim2[14], sim2[12], sim2[10], sim2[8], sim2[6], 
			sim2[4]})) |
       (sim2[1] & ~(| {sim2[14], sim2[12], sim2[10], sim2[8], sim2[6], 
			sim2[4], sim2[2]}));

assign int_level_n_1[3] =
       (| sim1[15:8]);

assign int_level_n_1[2] =
       (| sim1[15:12]) | 
       ((| sim1[7:4]) & ~(| sim1[11:8]));

assign int_level_n_1[1] = 
       (| sim1[15:14]) |
       ((| sim1[11:10]) & ~(| sim1[13:12])) |
       ((| sim1[7:6]) & ~(| {sim1[13:12], sim1[9:8]})) |
       ((| sim1[3:2]) & ~(| {sim1[13:12], sim1[9:8], sim1[5:4]}));

assign int_level_n_1[0] =
       sim1[15] |
       (sim1[13] & ~(  {sim1[14]})) |
       (sim1[11] & ~(| {sim1[14], sim1[12]})) |
       (sim1[9] & ~(| {sim1[14], sim1[12], sim1[10]})) |
       (sim1[7] & ~(| {sim1[14], sim1[12], sim1[10], sim1[8]})) |
       (sim1[5] & ~(| {sim1[14], sim1[12], sim1[10], sim1[8], sim1[6]})) |
       (sim1[3] & ~(| {sim1[14], sim1[12], sim1[10], sim1[8], sim1[6], 
			sim1[4]})) |
       (sim1[1] & ~(| {sim1[14], sim1[12], sim1[10], sim1[8], sim1[6], 
			sim1[4], sim1[2]}));

assign int_level_n_0[3] =
       (| sim0[15:8]);

assign int_level_n_0[2] =
       (| sim0[15:12]) | 
       ((| sim0[7:4]) & ~(| sim0[11:8]));

assign int_level_n_0[1] = 
       (| sim0[15:14]) |
       ((| sim0[11:10]) & ~(| sim0[13:12])) |
       ((| sim0[7:6]) & ~(| {sim0[13:12], sim0[9:8]})) |
       ((| sim0[3:2]) & ~(| {sim0[13:12], sim0[9:8], sim0[5:4]}));

assign int_level_n_0[0] =
       sim0[15] |
       (sim0[13] & ~(  {sim0[14]})) |
       (sim0[11] & ~(| {sim0[14], sim0[12]})) |
       (sim0[9] & ~(| {sim0[14], sim0[12], sim0[10]})) |
       (sim0[7] & ~(| {sim0[14], sim0[12], sim0[10], sim0[8]})) |
       (sim0[5] & ~(| {sim0[14], sim0[12], sim0[10], sim0[8], sim0[6]})) |
       (sim0[3] & ~(| {sim0[14], sim0[12], sim0[10], sim0[8], sim0[6], 
			sim0[4]})) |
       (sim0[1] & ~(| {sim0[14], sim0[12], sim0[10], sim0[8], sim0[6], 
			sim0[4], sim0[2]}));


assign int_level_n[3:0] =
       ({4 {real_trap[3]}} & int_level_n_3_last[3:0]) |
       ({4 {real_trap[2]}} & int_level_n_2_last[3:0]) |
       ({4 {real_trap[1]}} & int_level_n_1_last[3:0]) |
       ({4 {real_trap[0]}} & int_level_n_0_last[3:0]) ;

tlu_trl_ctl_msff_ctl_macro__width_16 int_level_n_lat  (
	.scan_in(int_level_n_lat_scanin),
	.scan_out(int_level_n_lat_scanout),
	.din	({int_level_n_3		[3:0],
		  int_level_n_2		[3:0],
		  int_level_n_1		[3:0],
		  int_level_n_0		[3:0]}),
	.dout	({int_level_n_3_last	[3:0],
		  int_level_n_2_last	[3:0],
		  int_level_n_1_last	[3:0],
		  int_level_n_0_last	[3:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// HINTP

// HSTICK_CMPR
assign hstick3_compare =
       (tic_compare[4:3] == 2'b10) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b11) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[3]);
assign hintp3_in =
        ( asi_wr_hintp[3] & asi_wr_data[0]) | 
	(~asi_wr_hintp[3] & hintp3         ) |
        (                    hstick3_compare) ;

// HSTICK_CMPR
assign hstick2_compare =
       (tic_compare[4:3] == 2'b10) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b10) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[2]);
assign hintp2_in =
        ( asi_wr_hintp[2] & asi_wr_data[0]) | 
	(~asi_wr_hintp[2] & hintp2         ) |
        (                    hstick2_compare) ;

// HSTICK_CMPR
assign hstick1_compare =
       (tic_compare[4:3] == 2'b10) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b01) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[1]);
assign hintp1_in =
        ( asi_wr_hintp[1] & asi_wr_data[0]) | 
	(~asi_wr_hintp[1] & hintp1         ) |
        (                    hstick1_compare) ;

// HSTICK_CMPR
assign hstick0_compare =
       (tic_compare[4:3] == 2'b10) & (tic_compare[2]) &
       (tic_compare[1:0] == 2'b00) &
       ((~cel_tccd & ~cel_tcud) | ~tlu_ceter_de[0]);
assign hintp0_in =
        ( asi_wr_hintp[0] & asi_wr_data[0]) | 
	(~asi_wr_hintp[0] & hintp0         ) |
        (                    hstick0_compare) ;

tlu_trl_ctl_msff_ctl_macro__width_4 hintp_lat  ( 
	.scan_in(hintp_lat_wmr_scanin),
	.scan_out(hintp_lat_wmr_scanout),
	.siclk(spc_aclk_wmr),
	.din	({hintp3_in,
		  hintp2_in,
		  hintp1_in,
		  hintp0_in	}),
	.dout	({hintp3,
		  hintp2,
		  hintp1,
		  hintp0	}),
  .l1clk(l1clk),
  .soclk(soclk)
);

assign trl_hstick_match[3:0] =
       {hintp3, hintp2, hintp1, hintp0} &
       (~hpstate_hpriv[3:0] | pstate_ie[3:0]) &
       ~hst_req[3:0];

assign trl_unhalt_[3:0] = 
       ~({hintp3, hintp2, hintp1, hintp0} |
         {softint3[16], softint2[16], softint1[16], softint0[16]} | 
         {softint3[0], softint2[0], softint1[0], softint0[0]} );


////////////////////////////////////////////////////////////////////////////////
// TCA (Tick Compare register Array) ECC disrupting exception detection

assign tccd_in[3] = 
       (tic_compare[5]) &
       (tic_compare[1:0] == 2'b11) &
       cel_tccd;
assign tccd_in[2] = 
       (tic_compare[5]) &
       (tic_compare[1:0] == 2'b10) &
       cel_tccd;
assign tccd_in[1] = 
       (tic_compare[5]) &
       (tic_compare[1:0] == 2'b01) &
       cel_tccd;
assign tccd_in[0] = 
       (tic_compare[5]) &
       (tic_compare[1:0] == 2'b00) &
       cel_tccd;

assign tcud_in[3] = 
       (tic_compare[5]) &
       (tic_compare[1:0] == 2'b11) &
       cel_tcud;
assign tcud_in[2] = 
       (tic_compare[5]) &
       (tic_compare[1:0] == 2'b10) &
       cel_tcud;
assign tcud_in[1] = 
       (tic_compare[5]) &
       (tic_compare[1:0] == 2'b01) &
       cel_tcud;
assign tcud_in[0] = 
       (tic_compare[5]) &
       (tic_compare[1:0] == 2'b00) &
       cel_tcud;

tlu_trl_ctl_msff_ctl_macro__width_4 tccd_exc_lat  (
	.scan_in(tccd_exc_lat_scanin),
	.scan_out(tccd_exc_lat_scanout),
	.din	(tccd_in	[3:0]	),
	.dout	(tccd		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_4 tcud_exc_lat  (
	.scan_in(tcud_exc_lat_scanin),
	.scan_out(tcud_exc_lat_scanout),
	.din	(tcud_in	[3:0]	),
	.dout	(tcud		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_tccd[3:0] =
       tccd[3:0];

assign tlu_tcud[3:0] =
       tcud[3:0];

tlu_trl_ctl_msff_ctl_macro__width_2 tic_index_lat  (
	.scan_in(tic_index_lat_scanin),
	.scan_out(tic_index_lat_scanout),
	.din	(tic_compare	[4:3]	),
	.dout	(tic_index	[4:3]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_tca_index[1:0] =
       tic_index[4:3];


////////////////////////////////////////////////////////////////////////////////
// TSA done/retry ECC precise exception detection

assign trl_tsacu_en_in[3:0] = 
       tsacu_en_in[3:0];

assign tpe_exc_in[3:0] = 
       tel_tsacu_exc[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 tpe_exc_lat  (
	.scan_in(tpe_exc_lat_scanin),
	.scan_out(tpe_exc_lat_scanout),
	.din	(tpe_exc_in	[3:0]	),
	.dout	(tpe_exc	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

tlu_trl_ctl_msff_ctl_macro__width_3 tsa_index_lat  (
	.scan_in(tsa_index_lat_scanin),
	.scan_out(tsa_index_lat_scanout),
	.din	(rmw_addr	[2:0]	),
	.dout	(tsa_index	[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_tsa_index[2:0] =
       tsa_index[2:0];


////////////////////////////////////////////////////////////////////////////////
// ASI read and writes

tlu_trl_ctl_msff_ctl_macro__width_4 p_trap_lat  (
	.scan_in(p_trap_lat_scanin),
	.scan_out(p_trap_lat_scanout),
	.din	(pmu_tlu_trap_m	[3:0]	),
	.dout	(p_trap		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign rd_softint3[16:0] =
       softint3[16:0] | {1'b0, p_trap[3], {15 {1'b0}}};
assign rd_softint2[16:0] =	      
       softint2[16:0] | {1'b0, p_trap[2], {15 {1'b0}}};
assign rd_softint1[16:0] =	      
       softint1[16:0] | {1'b0, p_trap[1], {15 {1'b0}}};
assign rd_softint0[16:0] =	      
       softint0[16:0] | {1'b0, p_trap[0], {15 {1'b0}}};

assign asi_data_in[16:0] =
       ({17 {asi_rd_tl		[3]}} & {14'h0000, tl3		[2:0]}) |
       ({17 {asi_rd_tl		[2]}} & {14'h0000, tl2		[2:0]}) |
       ({17 {asi_rd_tl		[1]}} & {14'h0000, tl1		[2:0]}) |
       ({17 {asi_rd_tl		[0]}} & {14'h0000, tl0		[2:0]}) |
       ({17 {asi_rd_pil		[3]}} & {13'h0000, pil3	[3:0]}) |
       ({17 {asi_rd_pil		[2]}} & {13'h0000, pil2	[3:0]}) |
       ({17 {asi_rd_pil		[1]}} & {13'h0000, pil1	[3:0]}) |
       ({17 {asi_rd_pil		[0]}} & {13'h0000, pil0	[3:0]}) |
       ({17 {asi_rd_gl		[3]}} & {15'h0000, gl3		[1:0]}) |
       ({17 {asi_rd_gl		[2]}} & {15'h0000, gl2		[1:0]}) |
       ({17 {asi_rd_gl		[1]}} & {15'h0000, gl1		[1:0]}) |
       ({17 {asi_rd_gl		[0]}} & {15'h0000, gl0		[1:0]}) |
       ({17 {asi_rd_softint	[3]}} & {rd_softint3		[16:0]}) |
       ({17 {asi_rd_softint	[2]}} & {rd_softint2		[16:0]}) |
       ({17 {asi_rd_softint	[1]}} & {rd_softint1		[16:0]}) |
       ({17 {asi_rd_softint	[0]}} & {rd_softint0		[16:0]}) |
       ({17 {asi_rd_hintp	[3]}} & {16'h0000, hintp3	       }) |
       ({17 {asi_rd_hintp	[2]}} & {16'h0000, hintp2	       }) |
       ({17 {asi_rd_hintp	[1]}} & {16'h0000, hintp1	       }) |
       ({17 {asi_rd_hintp	[0]}} & {16'h0000, hintp0	       }) ;

tlu_trl_ctl_msff_ctl_macro__width_17 asi_data_lat  (
	.scan_in(asi_data_lat_scanin),
	.scan_out(asi_data_lat_scanout),
	.din	(asi_data_in		[16:0]	),
	.dout	(asi_data		[16:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_asi_data[16:0] =
	asi_data[16:0];


////////////////////////////////////////////////////////////////////////////////
// Wait for store buffer empty if entering RED state

assign enter_red_in[3:0] = 
       {(tl3[2:0] == maxtl_minus_one[2:0]) &  hpstate_hpriv[3], 
        (tl2[2:0] == maxtl_minus_one[2:0]) &  hpstate_hpriv[2], 
        (tl1[2:0] == maxtl_minus_one[2:0]) &  hpstate_hpriv[1], 
        (tl0[2:0] == maxtl_minus_one[2:0]) &  hpstate_hpriv[0]}; 
						    
tlu_trl_ctl_msff_ctl_macro__width_4 enter_red_lat  (
	  .scan_in(enter_red_lat_scanin),
	  .scan_out(enter_red_lat_scanout),
	  .din	(enter_red_in		[3:0]	),
	  .dout	(enter_red		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign stb_wait[3:0] = 
       enter_red[3:0] & ~stb_empty[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 stb_empty_lat  (
	.scan_in(stb_empty_lat_scanin),
	.scan_out(stb_empty_lat_scanout),
	.din	(lsu_stb_empty	[3:0]	),
	.dout	(stb_empty	[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Block dispatch for done and retry
//	First, block from cycle of flush until done/retry wins arbitration
//	Second, block on cycle of redirect
// IRF only does single pass for CWP change, so don't need 
// second block
//  Cycle diagram ( TR - trap redirect  TF - trap flush   CU - TLU-EXU CWP msg
//                  RM - RML decode     RT - RML to IRF   ID - IRF decode
//                  IS - IRF save       IR - IRF restore  EC - EXU CWP update
//                  WB - TLU window block
//                  EB - EXU window block
// 	  	    t - trlX.trap[] signal  r - read TSA   c - check ECC
//		    p - generate redirect PC
//	(Redirect takes at least two cycles because must arbitrate in first 
//	 cycle and then read TSA in second cycle)
//	(IRF requires 0 to NOT be a read or write for this thread)
// TR |           t r c p X                
// BF |                     N
//  F |                       N
//  C |                         N
//  P |                           N
//  D | D           H H     H       N
//  E |   D           H H     H     .
//  M |     D           H H     H   .
//  B |       D           H H     H .
// TF |         X           |     | .
// CU |           t r c X   |     | .
// RT |                   X |     | .
// ID |                     X X   | .  
// IS |                       X   | .
// IR |                         X 0 .
// EC |                       X
// WB |           X X     X 
//
//	Instruction N reads operands from new window, so swap must be
//	complete before it reaches D

assign window_block_in =
       (| pdon_req_in[3:0]) | (| pret_req_in[3:0]) | 
       ccr_cwp_valid;

tlu_trl_ctl_msff_ctl_macro__width_1 window_block_lat  (
	.scan_in(window_block_lat_scanin),
	.scan_out(window_block_lat_scanout),
	.din	(window_block_in	),
	.dout	(tlu_window_block	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


////////////////////////////////////////////////////////////////////////////////
// Block done and retry when EXU needs hole for CWP change or when earlier
// done or retry needs hole for CWP change
// EB |   X
//  P |   H          
//  D |     H        
//  E |       H      
//  M |         H    
//  B |           H  
// TF |           |  
// CU | t r c X   |  
// RT |         X |  
// ID |           0
//
// So window_block doesn't happen until the trap_taken cycle

assign hole_in_p = 
       exu_tlu_window_block;

assign stall_don_ret = don_ret_last_last;


////////////////////////////////////////////////////////////////////////////////
// Assign outputs

tlu_trl_ctl_msff_ctl_macro__width_11 take_lat  (
	.scan_in(take_lat_scanin),
	.scan_out(take_lat_scanout),
	.din	({take_por,
		  take_htd,
		  take_lsr,
		  take_fpe,
		  take_don,
		  take_ret,
		  take_res,
		  take_ssr,
		  take_ssr_por,
		  take_icp,
		  take_nns		       }),
	.dout	({take_por_last,
		  take_htd_last,
		  take_lsr_last,
		  take_fpe_last,
		  ptake_don_last,
		  ptake_ret_last,
		  take_res_last,
		  take_ssr_last,
		  take_ssr_por_last,
		  take_icp_last,
		  take_nns_last		       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_don_last =
       ptake_don_last & ~hole_in_p;

assign take_ret_last =
       ptake_ret_last & ~hole_in_p;

assign take_htd_icp_last =
	take_htd_last | take_icp_last;

tlu_trl_ctl_msff_ctl_macro__width_5 take_last_lat  (
	.scan_in(take_last_lat_scanin),
	.scan_out(take_last_lat_scanout),
	.din	({take_htd_icp_last,
		  take_don_last,
		  don_ret_last,
		  take_don_last_last,
		  don_ret_last_last	       }),
	.dout	({take_htd_icp_last_last,
		  take_don_last_last,
		  don_ret_last_last,
		  take_don_last_last_last,
		  don_ret_last_last_last       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign take_lsr_nns_last =
       take_lsr_last | take_nns_last;

tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 thread_sel_lat   (
	.scan_in(thread_sel_lat_scanin),
	.scan_out(thread_sel_lat_scanout),
	.l1clk	({l1clk_pm4		       ,
		  l1clk_pm3		       ,
		  l1clk_pm2		       ,
		  l1clk_pm1		       }),
	.din	(real_trap		[3:0]	),
	.dout	(real_trap_last		[3:0]	),
  .siclk(siclk),
  .soclk(soclk)
);

assign thread_sel[3:0] =
       real_trap_last[3:0];

assign trl_thread_sel[3:0] =
       thread_sel[3:0];

assign suppress_don_ret_taken_ =
       ~hole_in_p | ~(ptake_don_last | ptake_ret_last);

assign no_pstate_update =
       take_lsr_last | take_fpe_last | 
       take_itw_last | take_htd_last | take_res_last | 
       take_ssr_last | take_nns_last | take_icp_last |
       ptake_don_last | ptake_ret_last;

assign trl_pstate_thread_sel[4:0] =
       {no_pstate_update | ~(| trap_taken3[3:0]),
        {4 {~no_pstate_update}} & trap_taken3[3:0]};

// Create select for TBA / HTBA muxing
// Bits 1:0 are the TID
// Bit 2 is the HTBA select (indicates trap goes to or stays in HPRIV)

assign trl_tba_sel[2] =
       (| (thread_sel[3:0] & hpstate_hpriv[3:0])) |
       other_trap | reset_trap;

assign trl_tba_sel[1] =
       thread_sel[3] | thread_sel[2];			

assign trl_tba_sel[0] =
       thread_sel[3] | thread_sel[1];			

assign trl_pstate_en =
       ((| trap_taken3[3:0]) & suppress_don_ret_taken_ & ~no_pstate_update) |
       asi_trl_pstate_en |
       (| npc_sel_tnpc[3:0]);

// PC and NPC are masked by PSTATE.am before going to TSA
tlu_trl_ctl_msff_ctl_macro__width_4 pstate_am_lat  (
	.scan_in(pstate_am_lat_scanin),
	.scan_out(pstate_am_lat_scanout),
	.din	(tsd_pstate_am		[3:0]	),
	.dout	(pstate_am		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign trl_pc_thread_sel[3:0] =
       trap_taken4[3:0];

assign trl_pc_pstate_am_ =
       ~(| (trap_taken4[3:0] & pstate_am[3:0]));

assign take_ssr_pc_valid =
       take_ssr & (| (trap[3:0] &  fls_pc_valid[3:0]));
assign take_ssr_pc_invalid =
       take_ssr & (| (trap[3:0] & ~fls_pc_valid[3:0]));

assign pc_sel_pc_in =			    
       take_htd | take_res | take_ssr_pc_invalid | take_nns | take_icp;

assign pc_sel_npc_in = 
       take_lsr | take_fpe | take_ssr_pc_valid;

assign pc_sel_trap_in = 
       ~take_htd & ~take_res & ~take_ssr & ~take_nns & ~take_icp & 
       ~take_don_last & 
       ~take_ret_last & ~take_reset & ~take_lsr & ~take_fpe & ~take_itw &
       (| (trap_ndr[3:0] & ~dbz_incoming[3:0] & 
           ~fei_or_fof_incoming[3:0])) & 
       ~take_don & ~take_ret & 
       ~(next_trap_to_red | next_trap_to_err); 

assign pc_sel_reset0_in = 
       ~take_htd & ~take_res & ~take_ssr & ~take_nns & ~take_icp & 
       ~take_don_last & ~take_ret_last & take_reset;
assign pc_sel_reset1_in = 
       next_trap_to_red | next_trap_to_err; 

assign pc_done_in = 
       take_don_last;

assign pc_retry_in = 
       take_ret_last;

assign pc_tte_in =
       take_itw | take_itw_last;

tlu_trl_ctl_msff_ctl_macro__width_8 pc_npc_sel_lat  (
	.scan_in(pc_npc_sel_lat_scanin),
	.scan_out(pc_npc_sel_lat_scanout),
	.din	({pc_sel_pc_in,
		  pc_sel_npc_in,
		  pc_sel_trap_in,
		  pc_sel_reset0_in,
		  pc_sel_reset1_in,
		  pc_done_in,
		  pc_retry_in,
		  pc_tte_in		       }),
	.dout	({pc_sel_pc,
		  pc_sel_npc,
		  pc_sel_trap,
		  pc_sel_reset0,
		  pc_sel_reset1,
		  pc_done,
		  pc_retry,
		  pc_tte		       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_pct_trap_pc_en =
       pc_sel_pc | pc_sel_npc | pc_sel_trap | pc_sel_reset0 | pc_sel_reset1 |
       pc_done | pc_retry | pc_tte;

assign trl_pc_sel_pc =
       pc_sel_pc;

assign trl_pc_sel_npc =
       pc_sel_npc;

assign trl_pc_done =
       pc_done;

assign trl_pc_retry =
       pc_retry;

assign trl_pc_tte =
       pc_tte;

assign trl_pc_sel_trap =
       pc_sel_trap & (| trap_taken4[3:0]);

assign trl_pc_sel_reset =
       pc_sel_reset0 | (pc_sel_reset1 & (| trap_taken4[3:0]));

assign wr_en_in_in =
       (take_reset | take_disrupt | take_div | take_long | take_fgu | 
	take_other) & ~take_htd;
assign wr_en_func_in =
       wr_en_in_p | rmw_tsa;
assign wr_en_in = 
       (wr_en_func_in & ~mbist_run) | asi_mbist_tsa_wr_en;

assign rd_en_in = 
	((take_don_ret | asi_preempt_done_retry) & ~mbist_run) | 
	asi_mbist_tsa_rd_en;

tlu_trl_ctl_msff_ctl_macro__width_4 stack_lat  (
	.scan_in(stack_lat_scanin),
	.scan_out(stack_lat_scanout),
	.din	({wr_en_in_in,
		  wr_en_in,
		  rd_en_in,
		  tsa_rd_en	       }),
	.dout	({wr_en_in_p,
		  tsa_wr_en,
		  tsa_rd_en,
		  tsa_rd_en_last       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_tsa_wr_en = 
       tsa_wr_en;
assign trl_tsa_rd_en = 
       rd_en_in;

assign trl_save_tsa = 
       (| check_tsa_ecc_in[3:0]);

assign trl_tsd_tsa_en =
       tsa_rd_en;

assign trl_tsd_tsa_wd_en =
       tsa_rd_en_last | wr_en_in;

assign don_ret_last = 
       take_don_last | take_ret_last;

assign enable_tel_in =
       (| (trap[3:0] & tlu_ceter_pscce[3:0])) | lsu_tlu_pmen;

tlu_trl_ctl_msff_ctl_macro__width_3 check_tel_lat  (
	.scan_in(check_tel_lat_scanin),
	.scan_out(check_tel_lat_scanout),
	.din	({enable_tel_in		       ,
		  enable_tel		       ,
		  check_tel_in		       }),
	.dout	({enable_tel		       ,
		  check_tel_in		       ,
		  check_tel		       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_tel_en =
       enable_tel | check_tel_in | check_tel;

assign take_notrap_not_suppressed =
       take_notrap & 
       ~(| (notrap_pre_trap[3:0] & 
	    (dbz_incoming[3:0] | fei_or_fof_incoming[3:0])));

assign m107773_suppress_notrap_ = 
       ~(take_notrap &  
         (| (notrap_pre_trap[3:0] & 
             (fls_ipe_request[3:0] | fls_pra_request[3:0]))));

assign trap_pc_valid_in_in = 
       (take_reset | take_disrupt | take_div | take_long | take_fgu | 
        take_other | take_notrap_not_suppressed) & m107773_suppress_notrap_;

assign trap_pc_valid_in =
       (ccr_cwp_valid | ptrap_pc_valid_in) & ~kill_fpe & ~kill_lsr_nns;

// If floating point predicted exception is "just ahead of" actual exception,
// kill FPE redirect
assign kill_fpe = 
       take_fpe_last & 
       (| ((fls_fei_request[3:0] | 
	    fls_fof_request[3:0]) & trap_taken4[3:0]));

// If LSR is "just ahead of" actual long-latency exception, kill LSR redirect
assign kill_lsr_nns = 
       take_lsr_nns_last & 
       (| ((fls_eer_request[3:0] | 
	    fls_ftt_request[3:0] | fls_ipe_request[3:0] | 
	    fls_fof_request[3:0] | 
	    fls_dbz_request[3:0] | 
	    fls_dae_request[3:0] |
	    fls_ime_request[3:0] | fls_dme_request[3:0] ) & 
	   trap_taken4[3:0]));

//  Also need to suppress LSR "just ahead of" ipe or pra
assign m107773_suppress_pcvi = 
       take_lsr_nns_last & 
         (| (trap_taken4[3:0] & 
             (fls_ipe_request[3:0] | fls_pra_request[3:0])));

assign real_trap_pc_valid_in =
       trap_pc_valid_in & ~m107773_suppress_pcvi;

assign npc_is_nonseq =
       | (trap_ndr[3:0] & pct_npc_is_nonseq[3:0]);

assign htd_res_icp_when_npc_nonseq =
       (take_htd | take_res | take_icp) & npc_is_nonseq;

tlu_trl_ctl_msff_ctl_macro__width_1 htd_res_icp_when_npc_nonseq_last_lat  (
	.scan_in(htd_res_icp_when_npc_nonseq_last_lat_scanin),
	.scan_out(htd_res_icp_when_npc_nonseq_last_lat_scanout),
	.din	(htd_res_icp_when_npc_nonseq	),
	.dout	(htd_res_icp_when_npc_nonseq_last	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign retry_in_in = 
       nns_exc | take_nns | take_ssr | take_ssr_por | 
       htd_res_icp_when_npc_nonseq;

assign retry_in =
       (pretry_in & ~(| {tel_tsacu_exc[3:0]})) | 
       (trap_pc_valid_in & (tcu_ss_mode | tcu_do_mode));

// Create single step complete exception (similar to idle) on single step
assign trl_ssc_exc[3:0] =
       trap_taken4[3:0] & {4 {take_ssr_last | take_ssr_por_last}};

tlu_trl_ctl_msff_ctl_macro__width_4 pc_valid_lat  (
	.scan_in(pc_valid_lat_scanin),
	.scan_out(pc_valid_lat_scanout),
	.din	({trap_pc_valid_in_in	       ,
		  real_trap_pc_valid_in	       ,
		  retry_in_in		       ,
		  retry_in		       }),
	.dout	({ptrap_pc_valid_in	       ,
		  trap_pc_valid		       ,
		  pretry_in		       ,
		  tlu_retry		       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_trap_pc_valid =
       trap_pc_valid;

assign trap_tid_in[1:0] =
        ({2 { don_ret_last_last_last}} & ccr_cwp_asi_tid[1:0]) |
	({2 {~don_ret_last_last_last}} & wr_addr_in	[4:3]) ;

tlu_trl_ctl_msff_ctl_macro__width_2 trap_tid_lat  (
	.scan_in(trap_tid_lat_scanin),
	.scan_out(trap_tid_lat_scanout),
	.din	(trap_tid_in		[1:0]	),
	.dout	(trap_tid		[1:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_trap_tid[1:0] = 
       trap_tid[1:0];

tlu_trl_ctl_msff_ctl_macro__width_2 take_itw_last_lat  (
	.scan_in(take_itw_last_lat_scanin),
	.scan_out(take_itw_last_lat_scanout),
	.din	({take_itw		       ,
		  take_itw_last		       }),
	.dout	({take_itw_last		       ,
		  take_itw_last_last	       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_itlb_reload = 
       take_itw_last_last;

tlu_trl_ctl_msff_ctl_macro__width_1 icache_perr_lat  (
	.scan_in(icache_perr_lat_scanin),
	.scan_out(icache_perr_lat_scanout),
	.din	(take_icp_last		       	),
	.dout	(take_icp_last_last	       	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_ifu_invalidate =
	take_icp_last_last;

assign reset_trap_in = 
	next_trap_to_red | next_trap_to_err | take_por | take_xir | take_sir;

assign in_red =
       | (tsd_hpstate_red[3:0] & real_trap[3:0]);

assign next_trap_to_red = 
       (((trap_tl[2:0] == maxtl_minus_one[2:0]) & (| real_trap[3:0])) |
	 in_red) & ~take_por & ~next_trap_to_err;

assign next_trap_to_err = 
       (trap_tl[2:0] == maxtl[2:0]) &
       (| real_trap[3:0]) & ~take_por;

assign next_trap_to_hpriv =
       (trap_tl[2:0] >= maxptl[2:0]) & 
       (trap_tl[2:0] < maxtl_minus_one[2:0]) &  // avoid red, err
       ~take_por & ~take_xir & ~take_sir & ~hpriv & ~in_red;

assign hpriv = 
       (| (real_trap[3:0] & hpstate_hpriv[3:0]));

assign hpriv_last = 
       (| (real_trap_last[3:0] & hpstate_hpriv[3:0]));

assign next_trap_in_hpriv =
       hpriv;

assign sip = 
       take_fpd | take_fgu | take_tof | take_clw | take_div | 
       take_snn | take_sno | take_fnn | take_fno | take_pro | take_iln |
       take_pmu | take_mqr | take_dqr | take_rqr | 
       take_tcc_nh |
       take_tct ;

assign stay_in_priv_in =
       sip & ~next_trap_to_red & ~next_trap_to_err & ~next_trap_to_hpriv & 
       ~next_trap_in_hpriv;

assign take_tcc_nh = 
       take_tcc & ~tcc_number[7];

assign take_tcc_h = 
       take_tcc &  tcc_number[7];

assign pre_oti = 
       take_itm | take_ipv | take_inp | take_iua | take_iar | take_irr |
       take_mar | take_mrr |
       take_ade | take_ivt | take_hst | take_sma | 
       take_cwq | take_iae | take_ipe | take_ill | take_ldf | take_stf | 
       take_dap | take_maa | take_pra | take_dia | 
       take_ups | take_dpv | take_dnc |
       take_dnf | take_dso | take_paw | 
       take_dae | take_dtm | take_irt | take_drt | 
       take_tlz | take_him | take_hdm | take_tcc_h | 
       take_ftt | take_eer | take_ime | take_dme |
       take_iit | take_dit | take_ibp |
       take_vaw | take_iaw ;

assign oti = 
       (pre_oti & ~next_trap_to_red & ~next_trap_to_err) | 
       (next_trap_to_hpriv & ~next_trap_to_red & ~next_trap_to_err) | 
       (sip & next_trap_in_hpriv & ~next_trap_to_red & ~next_trap_to_err);

assign other_trap_in =
       oti;

tlu_trl_ctl_msff_ctl_macro__width_3 pstate_sel_lat  (
	.scan_in(pstate_sel_lat_scanin),
	.scan_out(pstate_sel_lat_scanout),
	.din	({reset_trap_in,
		  stay_in_priv_in,
		  other_trap_in		       }),
	.dout	({reset_trap,
		  stay_in_priv,
		  other_trap		       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_reset_trap =
       reset_trap;

assign trl_stay_in_priv =
       stay_in_priv;

assign trl_other_trap =
       other_trap;


assign ccr_cwp_valid =
       don_ret_last_last_last & (~(| tel_tsacu_exc[3:0]) | ~check_tel);
 
assign ccr_cwp_valid_per_thread[3:0] =
       {4 {don_ret_last_last_last}} & 
       (~tel_tsacu_exc[3:0] | {4 {~check_tel}});
 
assign tlu_ccr_cwp_valid = 
       ccr_cwp_valid;
assign tlu_asi_valid = 
       ccr_cwp_valid;

assign ccr_cwp_asi_tid_in_in[1:0] =
       {trap_taken[3] | trap_taken[2], 
        trap_taken[3] | trap_taken[1]};

tlu_trl_ctl_msff_ctl_macro__width_4 ccr_cwp_asi_tid_lat  (
	.scan_in(ccr_cwp_asi_tid_lat_scanin),
	.scan_out(ccr_cwp_asi_tid_lat_scanout),
	.din	({ccr_cwp_asi_tid_in_in	[1:0],
		  ccr_cwp_asi_tid_in	[1:0]}),
	.dout	({ccr_cwp_asi_tid_in	[1:0],
		  ccr_cwp_asi_tid	[1:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_ccr_cwp_tid = 
       ccr_cwp_asi_tid[1:0];
assign tlu_asi_tid[1:0] = 
       ccr_cwp_asi_tid[1:0];

assign trl_asireg_sel[4:0] =
       {~ccr_cwp_valid, 
        ccr_cwp_valid_per_thread[3:0] & 
        { ccr_cwp_asi_tid[1] &  ccr_cwp_asi_tid[0],  
	  ccr_cwp_asi_tid[1] & ~ccr_cwp_asi_tid[0],  
 	 ~ccr_cwp_asi_tid[1] &  ccr_cwp_asi_tid[0],  
	 ~ccr_cwp_asi_tid[1] & ~ccr_cwp_asi_tid[0]}};

assign trl_asireg_en =
       (| asi_wr_asireg[3:0]) | ccr_cwp_valid;


assign tlu_release_tte[3:0] = 
       {4 {take_itw_last}} & trap_taken4[3:0];


//////////////////////////////////////////////////////////////////////
//
// Have to clear lsu_control_reg on any trap that sets HPSTATE.red
//

assign clear_ctl_reg_in[3:0] = 
       {4 {reset_trap}} & trap_taken4[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 clear_ctl_reg_lat  (
	.scan_in(clear_ctl_reg_lat_scanin),
	.scan_out(clear_ctl_reg_lat_scanout),
	.din	(clear_ctl_reg_in	[3:0]	),
	.dout	(clear_ctl_reg		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlu_lsu_clear_ctl_reg_[3:0] =
       ~clear_ctl_reg[3:0];


//////////////////////////////////////////////////////////////////////
//
// Determine when retry PC, NPC are nonsequential
//


assign pnpc_nonseq_in[3:0] =
       {4 {tsa_tnpc_nonseq & take_ret_last & suppress_don_ret_taken_}} & 
       trap_taken[3:0];

assign npc_nonseq_in[3:0] =
       pnpc_nonseq_in[3:0] | 
       ({4 {htd_res_icp_when_npc_nonseq_last}} & trap_taken[3:0]);

assign nns_exc_in =
       | pnpc_nonseq_in[3:0];

tlu_trl_ctl_msff_ctl_macro__width_5 npc_nonseq_lat  (
	.scan_in(npc_nonseq_lat_scanin),
	.scan_out(npc_nonseq_lat_scanout),
	.din	({npc_nonseq_in		[3:0],
		  nns_exc_in		       }),
	.dout	({npc_nonseq		[3:0],
		  nns_exc		       }),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_nns_exc[3:0] =
       npc_nonseq[3:0];


////////////////////////////////////////////////////////////////////////////////
//
//  Control load of PC, NPC (on trap, retry, done)
//

assign trap_tid_in_dec[3:0] =
       { trap_tid_in[1] &  trap_tid_in[0],
         trap_tid_in[1] & ~trap_tid_in[0],
        ~trap_tid_in[1] &  trap_tid_in[0],
        ~trap_tid_in[1] & ~trap_tid_in[0]};

// On return from hardware tablewalk, PC and NPC are already correct,
// just need to invalidate them
assign pc_sel_trap_pc_in[3:0] =
       {4 {trap_pc_valid_in & ~take_lsr_last & 
	   ~take_htd_last & ~take_fpe_last & ~take_nns_last & 
	   ~take_icp_last}} & 
       trap_tid_in_dec[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 pc_sel_trap_pc_lat  (
	.scan_in(pc_sel_trap_pc_lat_scanin),
	.scan_out(pc_sel_trap_pc_lat_scanout),
	.din	(pc_sel_trap_pc_in		[3:0]	),
	.dout	(pc_sel_trap_pc			[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_pc_sel_trap_pc[3:0] = 
       pc_sel_trap_pc[3:0];

assign npc_sel_trap_npc_in[3:0] =
       {4 {trap_pc_valid_in & ~don_ret_last_last_last & ~take_lsr_last & 
	   ~take_htd_last & ~take_fpe_last & ~take_res_last & 
	   ~take_ssr_last & ~take_nns_last & ~take_icp_last}} & 
       trap_tid_in_dec[3:0];

tlu_trl_ctl_msff_ctl_macro__width_4 npc_sel_trap_npc_lat  (
	.scan_in(npc_sel_trap_npc_lat_scanin),
	.scan_out(npc_sel_trap_npc_lat_scanout),
	.din	(npc_sel_trap_npc_in		[3:0]	),
	.dout	(npc_sel_trap_npc		[3:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_npc_sel_trap_npc[3:0] = 
       npc_sel_trap_npc[3:0];

assign check_tsa_ecc_in_in[3:0] = 
       {4 {don_ret_last & suppress_don_ret_taken_}} & trap_taken[3:0];

assign tsacu_en_in_in[3:0] =
       check_tsa_ecc_in_in[3:0] & tlu_ceter_pscce[3:0] & 
       {4 {enable_tel}};

tlu_trl_ctl_msff_ctl_macro__width_12 check_tsa_ecc_lat  (
	.scan_in(check_tsa_ecc_lat_scanin),
	.scan_out(check_tsa_ecc_lat_scanout),
	.din	({tsacu_en_in_in		[3:0],
		  check_tsa_ecc_in_in		[3:0],
		  check_tsa_ecc_in		[3:0]}),
	.dout	({tsacu_en_in			[3:0],
		  check_tsa_ecc_in		[3:0],
		  check_tsa_ecc			[3:0]}),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_pct_tnpc_en =
       | check_tsa_ecc_in[3:0];

assign trl_fls_npc_en[3:0] =
       check_tsa_ecc[3:0] | npc_sel_trap_npc[3:0];

assign npc_sel_tnpc[3:0] =
       check_tsa_ecc[3:0] & {4 {~(| tel_tsacu_exc[3:0]) | ~check_tel}};

assign trl_don_ret_pstate_sel[3:0] = 
       npc_sel_tnpc[3:0];

assign trl_npc_sel_tnpc[3:0] =
       npc_sel_tnpc[3:0];

assign trap_tid_dec[3:0] =
       { trap_tid[1] &  trap_tid[0],
         trap_tid[1] & ~trap_tid[0],
        ~trap_tid[1] &  trap_tid[0],
        ~trap_tid[1] & ~trap_tid[0]};

assign htd_icp_complete[3:0] = 
       {4 {trap_pc_valid & take_htd_icp_last_last}} & trap_tid_dec[3:0];

assign trl_invalidate_pc[3:0] =
       pc_sel_trap_pc[3:0] | htd_icp_complete[3:0];

assign trl_invalidate_npc[3:0] = 
       ((npc_sel_tnpc[3:0] & ~{4 {take_don_last_last_last}}) | 
	npc_sel_trap_npc[3:0]) |
       htd_icp_complete[3:0];	       


//////////////////////////////////////////////////////////////////////////////
//
// Shadow scan
//

tlu_trl_ctl_msff_ctl_macro__width_3 shscanid_lat  (
	.scan_in(shscanid_lat_scanin),
	.scan_out(shscanid_lat_scanout),
	.din	(tcu_shscanid		[2:0]	),
	.dout	(shscanid		[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_shscanid[1:0] =
       shscanid[1:0];

assign trl_shscanid_2 =
       shscanid[2];

assign shadow_tl[2:0] =
       (tl0[2:0] & {3 {~shscanid[1] & ~shscanid[0]}}) |
       (tl1[2:0] & {3 {~shscanid[1] &  shscanid[0]}}) |
       (tl2[2:0] & {3 { shscanid[1] & ~shscanid[0]}}) |
       (tl3[2:0] & {3 { shscanid[1] &  shscanid[0]}}) ;

assign trl_shadow_tl[2:0] =
       shadow_tl[2:0];

// Need to signal when to capture TPC and TT
assign capture_ss_in =
       (real_trap_last[0] & ~shscanid[1] & ~shscanid[0]) |
       (real_trap_last[1] & ~shscanid[1] &  shscanid[0]) |
       (real_trap_last[2] &  shscanid[1] & ~shscanid[0]) |
       (real_trap_last[3] &  shscanid[1] &  shscanid[0]) ;

tlu_trl_ctl_msff_ctl_macro__width_1 capture_ss_lat   (
	.scan_in(capture_ss_lat_scanin),
	.scan_out(capture_ss_lat_scanout),
	.din	(capture_ss_in			),
	.dout	(capture_ss			),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);

assign trl_capture_ss =
       capture_ss;

// Also have to capture (new) TL in sync with TPC and TT

assign tl_for_tt_in[2:0] =
       (tl_for_tt[2:0] & {3 {~capture_ss}}) |
       (shadow_tl[2:0] & {3 { capture_ss}}) ;

tlu_trl_ctl_msff_ctl_macro__width_3 tl_for_tt_lat  (
	.scan_in(tl_for_tt_lat_scanin),
	.scan_out(tl_for_tt_lat_scanout),
	.din	(tl_for_tt_in		[2:0]	),
	.dout	(tl_for_tt		[2:0]	),
  .l1clk(l1clk),
  .siclk(siclk),
  .soclk(soclk)
);


assign trl_tl_for_tt[2:0] =
       tl_for_tt[2:0];


//////////////////////////////////////////////////////////////////////////////
//
// Spares
//

// Each pack has one flop
tlu_trl_ctl_spare_ctl_macro__num_16 spares  (
	.scan_in(spares_scanin),
	.scan_out(spares_scanout),
	.l1clk	(l1clk				),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
// fixscan start:
assign flush_ifu_last_lat_scanin = scan_in                  ;
assign l1en_per_thread_int_lat_scanin = flush_ifu_last_lat_scanout;
assign l1en_don_ret_lat_scanin   = l1en_per_thread_int_lat_scanout;
assign tid_dec_w_lat_scanin      = l1en_don_ret_lat_scanout ;
assign cwq_busy_lat_scanin       = tid_dec_w_lat_scanout    ;
assign quiesced_last_lat_scanin  = cwq_busy_lat_scanout     ;
assign idl_req_lat_scanin        = quiesced_last_lat_scanout;
assign i_quiesce_lat_scanin      = idl_req_lat_scanout      ;
assign p_quiesce_lat_scanin      = i_quiesce_lat_scanout    ;
assign ma_busy_lat_scanin        = p_quiesce_lat_scanout    ;
assign core_running_status_lat_scanin = ma_busy_lat_scanout      ;
assign ever_been_running_lat_scanin = core_running_status_lat_scanout;
assign por_req_lat_scanin        = ever_been_running_lat_scanout;
assign xir_req_lat_scanin        = por_req_lat_scanout      ;
assign eer_req_lat_scanin        = xir_req_lat_scanout      ;
assign icp_req_lat_scanin        = eer_req_lat_scanout      ;
assign ftt_req_lat_scanin        = icp_req_lat_scanout      ;
assign ivt_req_lat_scanin        = ftt_req_lat_scanout      ;
assign mqr_req_lat_scanin        = ivt_req_lat_scanout      ;
assign dqr_req_lat_scanin        = mqr_req_lat_scanout      ;
assign rqr_req_lat_scanin        = dqr_req_lat_scanout      ;
assign res_req_lat_scanin        = rqr_req_lat_scanout      ;
assign ssr_req_lat_scanin        = res_req_lat_scanout      ;
assign ssc_req_lat_scanin        = ssr_req_lat_scanout      ;
assign nns_req_lat_scanin        = ssc_req_lat_scanout      ;
assign sir_req_lat_scanin        = nns_req_lat_scanout      ;
assign itm_req_lat_scanin        = sir_req_lat_scanout      ;
assign i_tte_outofrange_lat_scanin = itm_req_lat_scanout      ;
assign iit_req_lat_scanin        = i_tte_outofrange_lat_scanout;
assign iln_req_lat_scanin        = iit_req_lat_scanout      ;
assign hst_req_lat_scanin        = iln_req_lat_scanout      ;
assign tlz_req_lat_scanin        = hst_req_lat_scanout      ;
assign sma_req_lat_scanin        = tlz_req_lat_scanout      ;
assign cwq_req_lat_scanin        = sma_req_lat_scanout      ;
assign ade_req_lat_scanin        = cwq_req_lat_scanout      ;
assign iae_req_lat_scanin        = ade_req_lat_scanout      ;
assign ipe_req_lat_scanin        = iae_req_lat_scanout      ;
assign ipv_req_lat_scanin        = ipe_req_lat_scanout      ;
assign i_unauth_access_lat_scanin = ipv_req_lat_scanout      ;
assign iua_req_lat_scanin        = i_unauth_access_lat_scanout;
assign inp_req_lat_scanin        = iua_req_lat_scanout      ;
assign iar_req_lat_scanin        = inp_req_lat_scanout      ;
assign irr_req_lat_scanin        = iar_req_lat_scanout      ;
assign mar_req_lat_scanin        = irr_req_lat_scanout      ;
assign mrr_req_lat_scanin        = mar_req_lat_scanout      ;
assign pro_req_lat_scanin        = mrr_req_lat_scanout      ;
assign ill_req_lat_scanin        = pro_req_lat_scanout      ;
assign don_req_lat_scanin        = ill_req_lat_scanout      ;
assign ret_req_lat_scanin        = don_req_lat_scanout      ;
assign fpd_req_lat_scanin        = ret_req_lat_scanout      ;
assign snn_req_lat_scanin        = fpd_req_lat_scanout      ;
assign sno_req_lat_scanin        = snn_req_lat_scanout      ;
assign fnn_req_lat_scanin        = sno_req_lat_scanout      ;
assign fno_req_lat_scanin        = fnn_req_lat_scanout      ;
assign clw_req_lat_scanin        = fno_req_lat_scanout      ;
assign dtm_req_lat_scanin        = clw_req_lat_scanout      ;
assign ldf_req_lat_scanin        = dtm_req_lat_scanout      ;
assign stf_req_lat_scanin        = ldf_req_lat_scanout      ;
assign dap_req_lat_scanin        = stf_req_lat_scanout      ;
assign vaw_req_lat_scanin        = dap_req_lat_scanout      ;
assign iaw_req_lat_scanin        = vaw_req_lat_scanout      ;
assign paw_req_lat_scanin        = iaw_req_lat_scanout      ;
assign maa_req_lat_scanin        = paw_req_lat_scanout      ;
assign fpe_req_lat_scanin        = maa_req_lat_scanout      ;
assign fei_req_lat_scanin        = fpe_req_lat_scanout      ;
assign fof_req_lat_scanin        = fei_req_lat_scanout      ;
assign pra_req_lat_scanin        = fof_req_lat_scanout      ;
assign dia_req_lat_scanin        = pra_req_lat_scanout      ;
assign ups_req_lat_scanin        = dia_req_lat_scanout      ;
assign dpv_req_lat_scanin        = ups_req_lat_scanout      ;
assign dnc_req_lat_scanin        = dpv_req_lat_scanout      ;
assign dnf_req_lat_scanin        = dnc_req_lat_scanout      ;
assign dso_req_lat_scanin        = dnf_req_lat_scanout      ;
assign tof_req_lat_scanin        = dso_req_lat_scanout      ;
assign dbz_req_lat_scanin        = tof_req_lat_scanout      ;
assign tcc_req_lat_scanin        = dbz_req_lat_scanout      ;
assign dae_req_lat_scanin        = tcc_req_lat_scanout      ;
assign lsr_req_lat_scanin        = dae_req_lat_scanout      ;
assign irt_req_lat_scanin        = lsr_req_lat_scanout      ;
assign drt_req_lat_scanin        = irt_req_lat_scanout      ;
assign d_tte_outofrange_lat_scanin = drt_req_lat_scanout      ;
assign dit_req_lat_scanin        = d_tte_outofrange_lat_scanout;
assign pmu_req_lat_scanin        = dit_req_lat_scanout      ;
assign ime_req_lat_scanin        = pmu_req_lat_scanout      ;
assign dme_req_lat_scanin        = ime_req_lat_scanout      ;
assign write_itlb_lat_scanin     = dme_req_lat_scanout      ;
assign itw_req_lat_scanin        = write_itlb_lat_scanout   ;
assign reload_done_lat_scanin    = itw_req_lat_scanout      ;
assign htd_req_lat_scanin        = reload_done_lat_scanout  ;
assign i_tsb_miss_lat_scanin     = htd_req_lat_scanout      ;
assign him_req_lat_scanin        = i_tsb_miss_lat_scanout   ;
assign d_tsb_miss_lat_scanin     = him_req_lat_scanout      ;
assign hdm_req_lat_scanin        = d_tsb_miss_lat_scanout   ;
assign ibp_req_lat_scanin        = hdm_req_lat_scanout      ;
assign tct_req_lat_scanin        = ibp_req_lat_scanout      ;
assign reset_pre_trap_lat_scanin = tct_req_lat_scanout      ;
assign disrupt_pre_trap_lat_scanin = reset_pre_trap_lat_scanout;
assign divide_pre_trap_lat_scanin = disrupt_pre_trap_lat_scanout;
assign long_pre_trap_lat_scanin  = divide_pre_trap_lat_scanout;
assign fgu_pre_trap_lat_scanin   = long_pre_trap_lat_scanout;
assign don_ret_pre_trap_lat_scanin = fgu_pre_trap_lat_scanout ;
assign notrap_pre_trap_lat_scanin = don_ret_pre_trap_lat_scanout;
assign itw_pre_trap_lat_scanin   = notrap_pre_trap_lat_scanout;
assign other_pre_trap_lat_scanin = itw_pre_trap_lat_scanout ;
assign pre_allow_trap_lat_scanin = other_pre_trap_lat_scanout;
assign pre_allow_don_ret_lat_scanin = pre_allow_trap_lat_scanout;
assign take_reset_lat_scanin     = pre_allow_don_ret_lat_scanout;
assign take_disrupt_lat_scanin   = take_reset_lat_scanout   ;
assign take_div_lat_scanin       = take_disrupt_lat_scanout ;
assign take_long_lat_scanin      = take_div_lat_scanout     ;
assign take_fgu_lat_scanin       = take_long_lat_scanout    ;
assign take_other_lat_scanin     = take_fgu_lat_scanout     ;
assign take_don_ret_lat_scanin   = take_other_lat_scanout   ;
assign take_notrap_lat_scanin    = take_don_ret_lat_scanout ;
assign take_itw_lat_scanin       = take_notrap_lat_scanout  ;
assign take_otr_lat_scanin       = take_itw_lat_scanout     ;
assign take_pmu_lat_scanin       = take_otr_lat_scanout     ;
assign take_ivt_lat_scanin       = take_pmu_lat_scanout     ;
assign trap_taken_lat_scanin     = take_ivt_lat_scanout     ;
assign trap_taken0_lat_scanin    = trap_taken_lat_scanout   ;
assign trap_taken1_lat_scanin    = trap_taken0_lat_scanout  ;
assign trap_taken2_lat_scanin    = trap_taken1_lat_scanout  ;
assign trap_taken3_lat_scanin    = trap_taken2_lat_scanout  ;
assign trap_taken4_lat_scanin    = trap_taken3_lat_scanout  ;
assign trap_taken5_lat_scanin    = trap_taken4_lat_scanout  ;
assign trap_itw_taken_lat_scanin = trap_taken5_lat_scanout  ;
assign take_reset_last_lat_scanin = trap_itw_taken_lat_scanout;
assign trap_type_lat_scanin      = take_reset_last_lat_scanout;
assign trap_type_for_pc_lat_scanin = trap_type_lat_scanout    ;
assign hpstate_hpriv_lat_scanin  = trap_type_for_pc_lat_scanout;
assign tl_lat_scanin             = hpstate_hpriv_lat_scanout;
assign tlz_lat_scanin            = tl_lat_scanout           ;
assign tl_gt_0_last_lat_scanin   = tlz_lat_scanout          ;
assign wr_gl_lat_scanin          = tl_gt_0_last_lat_scanout ;
assign gl_rest_lat_scanin        = wr_gl_lat_scanout        ;
assign mbist_run_lat_scanin      = gl_rest_lat_scanout      ;
assign tsa_wr_addr_lat_scanin    = mbist_run_lat_scanout    ;
assign tsa_rd_addr_lat_scanin    = tsa_wr_addr_lat_scanout  ;
assign rmw_addr_lat_scanin       = tsa_rd_addr_lat_scanout  ;
assign rmw_tsa_lat_scanin        = rmw_addr_lat_scanout     ;
assign tic_compare_lat_scanin    = rmw_tsa_lat_scanout      ;
assign pstate_ie_lat_scanin      = tic_compare_lat_scanout  ;
assign pmu_trap_mask_lat_scanin  = pstate_ie_lat_scanout    ;
assign int_level_n_lat_scanin    = pmu_trap_mask_lat_scanout;
assign tccd_exc_lat_scanin       = int_level_n_lat_scanout  ;
assign tcud_exc_lat_scanin       = tccd_exc_lat_scanout     ;
assign tic_index_lat_scanin      = tcud_exc_lat_scanout     ;
assign tpe_exc_lat_scanin        = tic_index_lat_scanout    ;
assign tsa_index_lat_scanin      = tpe_exc_lat_scanout      ;
assign p_trap_lat_scanin         = tsa_index_lat_scanout    ;
assign asi_data_lat_scanin       = p_trap_lat_scanout       ;
assign enter_red_lat_scanin      = asi_data_lat_scanout     ;
assign stb_empty_lat_scanin      = enter_red_lat_scanout    ;
assign window_block_lat_scanin   = stb_empty_lat_scanout    ;
assign take_lat_scanin           = window_block_lat_scanout ;
assign take_last_lat_scanin      = take_lat_scanout         ;
assign thread_sel_lat_scanin     = take_last_lat_scanout    ;
assign pstate_am_lat_scanin      = thread_sel_lat_scanout   ;
assign pc_npc_sel_lat_scanin     = pstate_am_lat_scanout    ;
assign stack_lat_scanin          = pc_npc_sel_lat_scanout   ;
assign check_tel_lat_scanin      = stack_lat_scanout        ;
assign htd_res_icp_when_npc_nonseq_last_lat_scanin = check_tel_lat_scanout    ;
assign pc_valid_lat_scanin       = htd_res_icp_when_npc_nonseq_last_lat_scanout;
assign trap_tid_lat_scanin       = pc_valid_lat_scanout     ;
assign take_itw_last_lat_scanin  = trap_tid_lat_scanout     ;
assign icache_perr_lat_scanin    = take_itw_last_lat_scanout;
assign pstate_sel_lat_scanin     = icache_perr_lat_scanout  ;
assign ccr_cwp_asi_tid_lat_scanin = pstate_sel_lat_scanout   ;
assign clear_ctl_reg_lat_scanin  = ccr_cwp_asi_tid_lat_scanout;
assign npc_nonseq_lat_scanin     = clear_ctl_reg_lat_scanout;
assign pc_sel_trap_pc_lat_scanin = npc_nonseq_lat_scanout   ;
assign npc_sel_trap_npc_lat_scanin = pc_sel_trap_pc_lat_scanout;
assign check_tsa_ecc_lat_scanin  = npc_sel_trap_npc_lat_scanout;
assign shscanid_lat_scanin       = check_tsa_ecc_lat_scanout;
assign capture_ss_lat_scanin     = shscanid_lat_scanout     ;
assign tl_for_tt_lat_scanin      = capture_ss_lat_scanout   ;
assign spares_scanin             = tl_for_tt_lat_scanout    ;
assign scan_out                  = spares_scanout           ;

assign gl_lat_wmr_scanin         = wmr_scan_in              ;
assign pil3_lat_wmr_scanin       = gl_lat_wmr_scanout       ;
assign pil2_lat_wmr_scanin       = pil3_lat_wmr_scanout     ;
assign pil1_lat_wmr_scanin       = pil2_lat_wmr_scanout     ;
assign pil0_lat_wmr_scanin       = pil1_lat_wmr_scanout     ;
assign softint3_lat_wmr_scanin   = pil0_lat_wmr_scanout     ;
assign softint2_lat_wmr_scanin   = softint3_lat_wmr_scanout ;
assign softint1_lat_wmr_scanin   = softint2_lat_wmr_scanout ;
assign softint0_lat_wmr_scanin   = softint1_lat_wmr_scanout ;
assign hintp_lat_wmr_scanin      = softint0_lat_wmr_scanout ;
assign wmr_scan_out              = hintp_lat_wmr_scanout    ;
// fixscan end:
endmodule 


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [2:0] so;

  input [3:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__clockwidth_1__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [3:1] sout;

  input [3:0] din;
  input [3:0] l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output scan_out;
assign fdin[3:0] = din[3:0];


cl_sc1_msff_4x d0_0 (
.l1clk(l1clk[0]),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0]),
.si(sout[1]),
.so(scan_out),
.q(dout[0])
);
cl_sc1_msff_4x d0_1 (
.l1clk(l1clk[1]),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1]),
.si(sout[2]),
.so(sout[1]),
.q(dout[1])
);
cl_sc1_msff_4x d0_2 (
.l1clk(l1clk[2]),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2]),
.si(sout[3]),
.so(sout[2]),
.q(dout[2])
);
cl_sc1_msff_4x d0_3 (
.l1clk(l1clk[3]),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3]),
.si(scan_in),
.so(sout[3]),
.q(dout[3])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;
wire [7:0] so;

  input [8:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;
wire [10:0] so;

  input [11:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si({scan_in,so[10:0]}),
.so({so[10:0],scan_out}),
.q(dout[11:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;
wire [8:0] so;

  input [9:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si({scan_in,so[8:0]}),
.so({so[8:0],scan_out}),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_17 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [16:0] fdin;
wire [15:0] so;

  input [16:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [16:0] dout;
  output scan_out;
assign fdin[16:0] = din[16:0];


dff #(17)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[16:0]),
.si({scan_in,so[15:0]}),
.so({so[15:0],scan_out}),
.q(dout[16:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_trl_ctl_msff_ctl_macro__width_11 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [10:0] fdin;
wire [9:0] so;

  input [10:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [10:0] dout;
  output scan_out;
assign fdin[10:0] = din[10:0];


dff #(11)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[10:0]),
.si({scan_in,so[9:0]}),
.so({so[9:0],scan_out}),
.q(dout[10:0])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module tlu_trl_ctl_spare_ctl_macro__num_16 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire si_4;
wire so_4;
wire spare4_flop_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire si_5;
wire so_5;
wire spare5_flop_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire si_6;
wire so_6;
wire spare6_flop_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire si_7;
wire so_7;
wire spare7_flop_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire si_8;
wire so_8;
wire spare8_flop_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;
wire si_9;
wire so_9;
wire spare9_flop_unused;
wire spare9_buf_32x_unused;
wire spare9_nand3_8x_unused;
wire spare9_inv_8x_unused;
wire spare9_aoi22_4x_unused;
wire spare9_buf_8x_unused;
wire spare9_oai22_4x_unused;
wire spare9_inv_16x_unused;
wire spare9_nand2_16x_unused;
wire spare9_nor3_4x_unused;
wire spare9_nand2_8x_unused;
wire spare9_buf_16x_unused;
wire spare9_nor2_16x_unused;
wire spare9_inv_32x_unused;
wire si_10;
wire so_10;
wire spare10_flop_unused;
wire spare10_buf_32x_unused;
wire spare10_nand3_8x_unused;
wire spare10_inv_8x_unused;
wire spare10_aoi22_4x_unused;
wire spare10_buf_8x_unused;
wire spare10_oai22_4x_unused;
wire spare10_inv_16x_unused;
wire spare10_nand2_16x_unused;
wire spare10_nor3_4x_unused;
wire spare10_nand2_8x_unused;
wire spare10_buf_16x_unused;
wire spare10_nor2_16x_unused;
wire spare10_inv_32x_unused;
wire si_11;
wire so_11;
wire spare11_flop_unused;
wire spare11_buf_32x_unused;
wire spare11_nand3_8x_unused;
wire spare11_inv_8x_unused;
wire spare11_aoi22_4x_unused;
wire spare11_buf_8x_unused;
wire spare11_oai22_4x_unused;
wire spare11_inv_16x_unused;
wire spare11_nand2_16x_unused;
wire spare11_nor3_4x_unused;
wire spare11_nand2_8x_unused;
wire spare11_buf_16x_unused;
wire spare11_nor2_16x_unused;
wire spare11_inv_32x_unused;
wire si_12;
wire so_12;
wire spare12_flop_unused;
wire spare12_buf_32x_unused;
wire spare12_nand3_8x_unused;
wire spare12_inv_8x_unused;
wire spare12_aoi22_4x_unused;
wire spare12_buf_8x_unused;
wire spare12_oai22_4x_unused;
wire spare12_inv_16x_unused;
wire spare12_nand2_16x_unused;
wire spare12_nor3_4x_unused;
wire spare12_nand2_8x_unused;
wire spare12_buf_16x_unused;
wire spare12_nor2_16x_unused;
wire spare12_inv_32x_unused;
wire si_13;
wire so_13;
wire spare13_flop_unused;
wire spare13_buf_32x_unused;
wire spare13_nand3_8x_unused;
wire spare13_inv_8x_unused;
wire spare13_aoi22_4x_unused;
wire spare13_buf_8x_unused;
wire spare13_oai22_4x_unused;
wire spare13_inv_16x_unused;
wire spare13_nand2_16x_unused;
wire spare13_nor3_4x_unused;
wire spare13_nand2_8x_unused;
wire spare13_buf_16x_unused;
wire spare13_nor2_16x_unused;
wire spare13_inv_32x_unused;
wire si_14;
wire so_14;
wire spare14_flop_unused;
wire spare14_buf_32x_unused;
wire spare14_nand3_8x_unused;
wire spare14_inv_8x_unused;
wire spare14_aoi22_4x_unused;
wire spare14_buf_8x_unused;
wire spare14_oai22_4x_unused;
wire spare14_inv_16x_unused;
wire spare14_nand2_16x_unused;
wire spare14_nor3_4x_unused;
wire spare14_nand2_8x_unused;
wire spare14_buf_16x_unused;
wire spare14_nor2_16x_unused;
wire spare14_inv_32x_unused;
wire si_15;
wire so_15;
wire spare15_flop_unused;
wire spare15_buf_32x_unused;
wire spare15_nand3_8x_unused;
wire spare15_inv_8x_unused;
wire spare15_aoi22_4x_unused;
wire spare15_buf_8x_unused;
wire spare15_oai22_4x_unused;
wire spare15_inv_16x_unused;
wire spare15_nand2_16x_unused;
wire spare15_nor3_4x_unused;
wire spare15_nand2_8x_unused;
wire spare15_buf_16x_unused;
wire spare15_nor2_16x_unused;
wire spare15_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));

cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_4),
                               .so(so_4),
                               .d(1'b0),
                               .q(spare4_flop_unused));
assign si_4 = so_3;

cl_u1_buf_32x   spare4_buf_32x (.in(1'b1),
                                   .out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare4_nand3_8x_unused));
cl_u1_inv_8x    spare4_inv_8x (.in(1'b1),
                                  .out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_aoi22_4x_unused));
cl_u1_buf_8x    spare4_buf_8x (.in(1'b1),
                                  .out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare4_oai22_4x_unused));
cl_u1_inv_16x   spare4_inv_16x (.in(1'b1),
                                   .out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare4_nand2_8x_unused));
cl_u1_buf_16x   spare4_buf_16x (.in(1'b1),
                                   .out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare4_nor2_16x_unused));
cl_u1_inv_32x   spare4_inv_32x (.in(1'b1),
                                   .out(spare4_inv_32x_unused));

cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_5),
                               .so(so_5),
                               .d(1'b0),
                               .q(spare5_flop_unused));
assign si_5 = so_4;

cl_u1_buf_32x   spare5_buf_32x (.in(1'b1),
                                   .out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare5_nand3_8x_unused));
cl_u1_inv_8x    spare5_inv_8x (.in(1'b1),
                                  .out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_aoi22_4x_unused));
cl_u1_buf_8x    spare5_buf_8x (.in(1'b1),
                                  .out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare5_oai22_4x_unused));
cl_u1_inv_16x   spare5_inv_16x (.in(1'b1),
                                   .out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare5_nand2_8x_unused));
cl_u1_buf_16x   spare5_buf_16x (.in(1'b1),
                                   .out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare5_nor2_16x_unused));
cl_u1_inv_32x   spare5_inv_32x (.in(1'b1),
                                   .out(spare5_inv_32x_unused));

cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_6),
                               .so(so_6),
                               .d(1'b0),
                               .q(spare6_flop_unused));
assign si_6 = so_5;

cl_u1_buf_32x   spare6_buf_32x (.in(1'b1),
                                   .out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare6_nand3_8x_unused));
cl_u1_inv_8x    spare6_inv_8x (.in(1'b1),
                                  .out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_aoi22_4x_unused));
cl_u1_buf_8x    spare6_buf_8x (.in(1'b1),
                                  .out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare6_oai22_4x_unused));
cl_u1_inv_16x   spare6_inv_16x (.in(1'b1),
                                   .out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare6_nand2_8x_unused));
cl_u1_buf_16x   spare6_buf_16x (.in(1'b1),
                                   .out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare6_nor2_16x_unused));
cl_u1_inv_32x   spare6_inv_32x (.in(1'b1),
                                   .out(spare6_inv_32x_unused));

cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_7),
                               .so(so_7),
                               .d(1'b0),
                               .q(spare7_flop_unused));
assign si_7 = so_6;

cl_u1_buf_32x   spare7_buf_32x (.in(1'b1),
                                   .out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare7_nand3_8x_unused));
cl_u1_inv_8x    spare7_inv_8x (.in(1'b1),
                                  .out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_aoi22_4x_unused));
cl_u1_buf_8x    spare7_buf_8x (.in(1'b1),
                                  .out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare7_oai22_4x_unused));
cl_u1_inv_16x   spare7_inv_16x (.in(1'b1),
                                   .out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare7_nand2_8x_unused));
cl_u1_buf_16x   spare7_buf_16x (.in(1'b1),
                                   .out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare7_nor2_16x_unused));
cl_u1_inv_32x   spare7_inv_32x (.in(1'b1),
                                   .out(spare7_inv_32x_unused));

cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_8),
                               .so(so_8),
                               .d(1'b0),
                               .q(spare8_flop_unused));
assign si_8 = so_7;

cl_u1_buf_32x   spare8_buf_32x (.in(1'b1),
                                   .out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare8_nand3_8x_unused));
cl_u1_inv_8x    spare8_inv_8x (.in(1'b1),
                                  .out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_aoi22_4x_unused));
cl_u1_buf_8x    spare8_buf_8x (.in(1'b1),
                                  .out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare8_oai22_4x_unused));
cl_u1_inv_16x   spare8_inv_16x (.in(1'b1),
                                   .out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare8_nand2_8x_unused));
cl_u1_buf_16x   spare8_buf_16x (.in(1'b1),
                                   .out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare8_nor2_16x_unused));
cl_u1_inv_32x   spare8_inv_32x (.in(1'b1),
                                   .out(spare8_inv_32x_unused));

cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_9),
                               .so(so_9),
                               .d(1'b0),
                               .q(spare9_flop_unused));
assign si_9 = so_8;

cl_u1_buf_32x   spare9_buf_32x (.in(1'b1),
                                   .out(spare9_buf_32x_unused));
cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare9_nand3_8x_unused));
cl_u1_inv_8x    spare9_inv_8x (.in(1'b1),
                                  .out(spare9_inv_8x_unused));
cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_aoi22_4x_unused));
cl_u1_buf_8x    spare9_buf_8x (.in(1'b1),
                                  .out(spare9_buf_8x_unused));
cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare9_oai22_4x_unused));
cl_u1_inv_16x   spare9_inv_16x (.in(1'b1),
                                   .out(spare9_inv_16x_unused));
cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare9_nand2_16x_unused));
cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare9_nor3_4x_unused));
cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare9_nand2_8x_unused));
cl_u1_buf_16x   spare9_buf_16x (.in(1'b1),
                                   .out(spare9_buf_16x_unused));
cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare9_nor2_16x_unused));
cl_u1_inv_32x   spare9_inv_32x (.in(1'b1),
                                   .out(spare9_inv_32x_unused));

cl_sc1_msff_8x spare10_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_10),
                               .so(so_10),
                               .d(1'b0),
                               .q(spare10_flop_unused));
assign si_10 = so_9;

cl_u1_buf_32x   spare10_buf_32x (.in(1'b1),
                                   .out(spare10_buf_32x_unused));
cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare10_nand3_8x_unused));
cl_u1_inv_8x    spare10_inv_8x (.in(1'b1),
                                  .out(spare10_inv_8x_unused));
cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare10_aoi22_4x_unused));
cl_u1_buf_8x    spare10_buf_8x (.in(1'b1),
                                  .out(spare10_buf_8x_unused));
cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare10_oai22_4x_unused));
cl_u1_inv_16x   spare10_inv_16x (.in(1'b1),
                                   .out(spare10_inv_16x_unused));
cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare10_nand2_16x_unused));
cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare10_nor3_4x_unused));
cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare10_nand2_8x_unused));
cl_u1_buf_16x   spare10_buf_16x (.in(1'b1),
                                   .out(spare10_buf_16x_unused));
cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare10_nor2_16x_unused));
cl_u1_inv_32x   spare10_inv_32x (.in(1'b1),
                                   .out(spare10_inv_32x_unused));

cl_sc1_msff_8x spare11_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_11),
                               .so(so_11),
                               .d(1'b0),
                               .q(spare11_flop_unused));
assign si_11 = so_10;

cl_u1_buf_32x   spare11_buf_32x (.in(1'b1),
                                   .out(spare11_buf_32x_unused));
cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare11_nand3_8x_unused));
cl_u1_inv_8x    spare11_inv_8x (.in(1'b1),
                                  .out(spare11_inv_8x_unused));
cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare11_aoi22_4x_unused));
cl_u1_buf_8x    spare11_buf_8x (.in(1'b1),
                                  .out(spare11_buf_8x_unused));
cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare11_oai22_4x_unused));
cl_u1_inv_16x   spare11_inv_16x (.in(1'b1),
                                   .out(spare11_inv_16x_unused));
cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare11_nand2_16x_unused));
cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare11_nor3_4x_unused));
cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare11_nand2_8x_unused));
cl_u1_buf_16x   spare11_buf_16x (.in(1'b1),
                                   .out(spare11_buf_16x_unused));
cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare11_nor2_16x_unused));
cl_u1_inv_32x   spare11_inv_32x (.in(1'b1),
                                   .out(spare11_inv_32x_unused));

cl_sc1_msff_8x spare12_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_12),
                               .so(so_12),
                               .d(1'b0),
                               .q(spare12_flop_unused));
assign si_12 = so_11;

cl_u1_buf_32x   spare12_buf_32x (.in(1'b1),
                                   .out(spare12_buf_32x_unused));
cl_u1_nand3_8x spare12_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare12_nand3_8x_unused));
cl_u1_inv_8x    spare12_inv_8x (.in(1'b1),
                                  .out(spare12_inv_8x_unused));
cl_u1_aoi22_4x spare12_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare12_aoi22_4x_unused));
cl_u1_buf_8x    spare12_buf_8x (.in(1'b1),
                                  .out(spare12_buf_8x_unused));
cl_u1_oai22_4x spare12_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare12_oai22_4x_unused));
cl_u1_inv_16x   spare12_inv_16x (.in(1'b1),
                                   .out(spare12_inv_16x_unused));
cl_u1_nand2_16x spare12_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare12_nand2_16x_unused));
cl_u1_nor3_4x spare12_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare12_nor3_4x_unused));
cl_u1_nand2_8x spare12_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare12_nand2_8x_unused));
cl_u1_buf_16x   spare12_buf_16x (.in(1'b1),
                                   .out(spare12_buf_16x_unused));
cl_u1_nor2_16x spare12_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare12_nor2_16x_unused));
cl_u1_inv_32x   spare12_inv_32x (.in(1'b1),
                                   .out(spare12_inv_32x_unused));

cl_sc1_msff_8x spare13_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_13),
                               .so(so_13),
                               .d(1'b0),
                               .q(spare13_flop_unused));
assign si_13 = so_12;

cl_u1_buf_32x   spare13_buf_32x (.in(1'b1),
                                   .out(spare13_buf_32x_unused));
cl_u1_nand3_8x spare13_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare13_nand3_8x_unused));
cl_u1_inv_8x    spare13_inv_8x (.in(1'b1),
                                  .out(spare13_inv_8x_unused));
cl_u1_aoi22_4x spare13_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare13_aoi22_4x_unused));
cl_u1_buf_8x    spare13_buf_8x (.in(1'b1),
                                  .out(spare13_buf_8x_unused));
cl_u1_oai22_4x spare13_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare13_oai22_4x_unused));
cl_u1_inv_16x   spare13_inv_16x (.in(1'b1),
                                   .out(spare13_inv_16x_unused));
cl_u1_nand2_16x spare13_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare13_nand2_16x_unused));
cl_u1_nor3_4x spare13_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare13_nor3_4x_unused));
cl_u1_nand2_8x spare13_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare13_nand2_8x_unused));
cl_u1_buf_16x   spare13_buf_16x (.in(1'b1),
                                   .out(spare13_buf_16x_unused));
cl_u1_nor2_16x spare13_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare13_nor2_16x_unused));
cl_u1_inv_32x   spare13_inv_32x (.in(1'b1),
                                   .out(spare13_inv_32x_unused));

cl_sc1_msff_8x spare14_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_14),
                               .so(so_14),
                               .d(1'b0),
                               .q(spare14_flop_unused));
assign si_14 = so_13;

cl_u1_buf_32x   spare14_buf_32x (.in(1'b1),
                                   .out(spare14_buf_32x_unused));
cl_u1_nand3_8x spare14_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare14_nand3_8x_unused));
cl_u1_inv_8x    spare14_inv_8x (.in(1'b1),
                                  .out(spare14_inv_8x_unused));
cl_u1_aoi22_4x spare14_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare14_aoi22_4x_unused));
cl_u1_buf_8x    spare14_buf_8x (.in(1'b1),
                                  .out(spare14_buf_8x_unused));
cl_u1_oai22_4x spare14_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare14_oai22_4x_unused));
cl_u1_inv_16x   spare14_inv_16x (.in(1'b1),
                                   .out(spare14_inv_16x_unused));
cl_u1_nand2_16x spare14_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare14_nand2_16x_unused));
cl_u1_nor3_4x spare14_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare14_nor3_4x_unused));
cl_u1_nand2_8x spare14_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare14_nand2_8x_unused));
cl_u1_buf_16x   spare14_buf_16x (.in(1'b1),
                                   .out(spare14_buf_16x_unused));
cl_u1_nor2_16x spare14_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare14_nor2_16x_unused));
cl_u1_inv_32x   spare14_inv_32x (.in(1'b1),
                                   .out(spare14_inv_32x_unused));

cl_sc1_msff_8x spare15_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_15),
                               .so(so_15),
                               .d(1'b0),
                               .q(spare15_flop_unused));
assign si_15 = so_14;

cl_u1_buf_32x   spare15_buf_32x (.in(1'b1),
                                   .out(spare15_buf_32x_unused));
cl_u1_nand3_8x spare15_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare15_nand3_8x_unused));
cl_u1_inv_8x    spare15_inv_8x (.in(1'b1),
                                  .out(spare15_inv_8x_unused));
cl_u1_aoi22_4x spare15_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare15_aoi22_4x_unused));
cl_u1_buf_8x    spare15_buf_8x (.in(1'b1),
                                  .out(spare15_buf_8x_unused));
cl_u1_oai22_4x spare15_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare15_oai22_4x_unused));
cl_u1_inv_16x   spare15_inv_16x (.in(1'b1),
                                   .out(spare15_inv_16x_unused));
cl_u1_nand2_16x spare15_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare15_nand2_16x_unused));
cl_u1_nor3_4x spare15_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare15_nor3_4x_unused));
cl_u1_nand2_8x spare15_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare15_nand2_8x_unused));
cl_u1_buf_16x   spare15_buf_16x (.in(1'b1),
                                   .out(spare15_buf_16x_unused));
cl_u1_nor2_16x spare15_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare15_nor2_16x_unused));
cl_u1_inv_32x   spare15_inv_32x (.in(1'b1),
                                   .out(spare15_inv_32x_unused));
assign scan_out = so_15;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_tsb_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_tsb_dp (
  tsb_in, 
  wr_en_in, 
  ecc_error, 
  tsb_out, 
  wr_en_out);
wire [67:0] evb_in;
wire [67:0] evb_out;
wire [135:0] tsb_ou;
wire [67:0] odb_in;
wire [67:0] odb_out;
wire wr_en_in_;


input	[135:0]	tsb_in;
input		wr_en_in;
input 		ecc_error;

output	[135:0]	tsb_out;
output		wr_en_out;


////////////////////////////////////////////////////////////////////////////////
//
// The compiled SRAM used for the trap stack array is arranged so that
// din[000] is in bit 1
// din[001] is in bit 2
// din[002] is in bit 2
// din[003] is in bit 3
// din[004] is in bit 3
// etc.
// (pre-mirror)
//
// Also, data bits 135:134 wire to SRAM pins 151:150
//       ECC  bits  15:000 wire to SRAM pins 149:134
//       data bits 133:000 wire to SRAM pins 133:000
// The SRAM has its controls between bits 76 and 75

assign evb_in[67:0] =
       {                          tsb_in[134], tsb_in[132], tsb_in[130],
	tsb_in[128], tsb_in[126], tsb_in[124], tsb_in[122], tsb_in[120],
	tsb_in[118], tsb_in[116], tsb_in[114], tsb_in[112], tsb_in[110],
	tsb_in[108], tsb_in[106], tsb_in[104], tsb_in[102], tsb_in[100],
	tsb_in[98], tsb_in[96], tsb_in[94], tsb_in[92], tsb_in[90],
	tsb_in[88], tsb_in[86], tsb_in[84], tsb_in[82], tsb_in[80],
	tsb_in[78], tsb_in[76], tsb_in[74], tsb_in[72], tsb_in[70],
	tsb_in[68], tsb_in[66], tsb_in[64], tsb_in[62], tsb_in[60],
	tsb_in[58], tsb_in[56], tsb_in[54], tsb_in[52], tsb_in[50],
	tsb_in[48], tsb_in[46], tsb_in[44], tsb_in[42], tsb_in[40],
	tsb_in[38], tsb_in[36], tsb_in[34], tsb_in[32], tsb_in[30],
	tsb_in[28], tsb_in[26], tsb_in[24], tsb_in[22], tsb_in[20],
	tsb_in[18], tsb_in[16], tsb_in[14], tsb_in[12], tsb_in[10],
	tsb_in[8], tsb_in[6], tsb_in[4], tsb_in[2], tsb_in[0]};

tlu_tsb_dp_buff_macro__minbuff_1__stack_none__width_68 even_data_bits_buf    (
	.din	(evb_in			[67:0]	),
	.dout	(evb_out  		[67:0]	)
);

assign {                          tsb_ou[134], tsb_ou[132], tsb_ou[130],
	tsb_ou[128], tsb_ou[126], tsb_ou[124], tsb_ou[122], tsb_ou[120],
	tsb_ou[118], tsb_ou[116], tsb_ou[114], tsb_ou[112], tsb_ou[110],
	tsb_ou[108], tsb_ou[106], tsb_ou[104], tsb_ou[102], tsb_ou[100],
	tsb_ou[98], tsb_ou[96], tsb_ou[94], tsb_ou[92], tsb_ou[90],
	tsb_ou[88], tsb_ou[86], tsb_ou[84], tsb_ou[82], tsb_ou[80],
	tsb_ou[78], tsb_ou[76], tsb_ou[74], tsb_ou[72], tsb_ou[70],
	tsb_ou[68], tsb_ou[66], tsb_ou[64], tsb_ou[62], tsb_ou[60],
	tsb_ou[58], tsb_ou[56], tsb_ou[54], tsb_ou[52], tsb_ou[50],
	tsb_ou[48], tsb_ou[46], tsb_ou[44], tsb_ou[42], tsb_ou[40],
	tsb_ou[38], tsb_ou[36], tsb_ou[34], tsb_ou[32], tsb_ou[30],
	tsb_ou[28], tsb_ou[26], tsb_ou[24], tsb_ou[22], tsb_ou[20],
	tsb_ou[18], tsb_ou[16], tsb_ou[14], tsb_ou[12], tsb_ou[10],
	tsb_ou[8], tsb_ou[6], tsb_ou[4], tsb_ou[2], tsb_ou[0]} =
       evb_out[67:0];


assign odb_in[67:0] =
       {                          tsb_in[135], tsb_in[133], tsb_in[131],
	tsb_in[129], tsb_in[127], tsb_in[125], tsb_in[123], tsb_in[121],
	tsb_in[119], tsb_in[117], tsb_in[115], tsb_in[113], tsb_in[111],
	tsb_in[109], tsb_in[107], tsb_in[105], tsb_in[103], tsb_in[101],
	tsb_in[99], tsb_in[97], tsb_in[95], tsb_in[93], tsb_in[91],
	tsb_in[89], tsb_in[87], tsb_in[85], tsb_in[83], tsb_in[81],
	tsb_in[79], tsb_in[77], tsb_in[75], tsb_in[73], tsb_in[71],
	tsb_in[69], tsb_in[67], tsb_in[65], tsb_in[63], tsb_in[61],
	tsb_in[59], tsb_in[57], tsb_in[55], tsb_in[53], tsb_in[51],
	tsb_in[49], tsb_in[47], tsb_in[45], tsb_in[43], tsb_in[41],
	tsb_in[39], tsb_in[37], tsb_in[35], tsb_in[33], tsb_in[31],
	tsb_in[29], tsb_in[27], tsb_in[25], tsb_in[23], tsb_in[21],
	tsb_in[19], tsb_in[17], tsb_in[15], tsb_in[13], tsb_in[11],
	tsb_in[9], tsb_in[7], tsb_in[5], tsb_in[3], tsb_in[1]};

tlu_tsb_dp_buff_macro__minbuff_1__stack_none__width_68 odd_data_bits_buf    (
	.din	(odb_in			[67:0]	),
	.dout	(odb_out  		[67:0]	)
);

assign {                          tsb_ou[135], tsb_ou[133], tsb_ou[131],
	tsb_ou[129], tsb_ou[127], tsb_ou[125], tsb_ou[123], tsb_ou[121],
	tsb_ou[119], tsb_ou[117], tsb_ou[115], tsb_ou[113], tsb_ou[111],
	tsb_ou[109], tsb_ou[107], tsb_ou[105], tsb_ou[103], tsb_ou[101],
	tsb_ou[99], tsb_ou[97], tsb_ou[95], tsb_ou[93], tsb_ou[91],
	tsb_ou[89], tsb_ou[87], tsb_ou[85], tsb_ou[83], tsb_ou[81],
	tsb_ou[79], tsb_ou[77], tsb_ou[75], tsb_ou[73], tsb_ou[71],
	tsb_ou[69], tsb_ou[67], tsb_ou[65], tsb_ou[63], tsb_ou[61],
	tsb_ou[59], tsb_ou[57], tsb_ou[55], tsb_ou[53], tsb_ou[51],
	tsb_ou[49], tsb_ou[47], tsb_ou[45], tsb_ou[43], tsb_ou[41],
	tsb_ou[39], tsb_ou[37], tsb_ou[35], tsb_ou[33], tsb_ou[31],
	tsb_ou[29], tsb_ou[27], tsb_ou[25], tsb_ou[23], tsb_ou[21],
	tsb_ou[19], tsb_ou[17], tsb_ou[15], tsb_ou[13], tsb_ou[11],
	tsb_ou[9], tsb_ou[7], tsb_ou[5], tsb_ou[3], tsb_ou[1]} =
       odb_out[67:0];

assign tsb_out[135:0] =
       tsb_ou[135:0];


// The wr_en should be spaced 3 bits away from bit 76
// wr_en_out = wr_en_in & ~ecc_error = ~(~wr_en_in | ecc_error)

tlu_tsb_dp_inv_macro__stack_2r__width_1 wr_en_in_b_inv   ( // stack=none not supported
	.din	(wr_en_in			),
	.dout	(wr_en_in_  			)
);

tlu_tsb_dp_nor_macro__ports_2__stack_2r__width_1 wr_en_out_nor    (//stack=none not supported
	.din0	(ecc_error			),
	.din1	(wr_en_in_			),
	.dout	(wr_en_out  			)
);


endmodule


//
//   buff macro
//
//


module tlu_tsb_dp_buff_macro__minbuff_1__stack_none__width_68 (
  din, 
  dout);
  input [67:0] din;
  output [67:0] dout;


buff #(68)  d0_0 (
.in(din[67:0]),
.out(dout[67:0])
);


endmodule


//
//   invert macro
//
//


module tlu_tsb_dp_inv_macro__stack_2r__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module tlu_tsb_dp_nor_macro__ports_2__stack_2r__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: tlu_tsd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module tlu_tsd_dp (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  spc_aclk, 
  spc_bclk, 
  tcu_scan_en, 
  tcu_dectest, 
  tcu_muxtest, 
  tcu_scan_en_wmr, 
  spc_aclk_wmr, 
  wmr_scan_in, 
  trl_shscanid, 
  exu_ccr0, 
  exu_ccr1, 
  exu_ccr2, 
  exu_ccr3, 
  fls_cwp0, 
  fls_cwp1, 
  fls_cwp2, 
  fls_cwp3, 
  pct_tsa_pc, 
  pct_tsa_pc_oor_va, 
  pct_tsa_npc, 
  pct_tsa_npc_oor_va, 
  pct_tsa_npc_nonseq, 
  trl_tsa_gl, 
  trl_tsa_trap_type, 
  trl_asireg_sel, 
  trl_asireg_en, 
  trl_thread_sel, 
  trl_tba_sel, 
  trl_pstate_thread_sel, 
  trl_don_ret_pstate_sel, 
  trl_pstate_en, 
  trl_reset_trap, 
  trl_stay_in_priv, 
  trl_other_trap, 
  trl_tl_gt_0, 
  trl_tsd_tsa_en, 
  trl_tsd_tsa_wd_en, 
  trl_save_tsa, 
  trl_capture_ss, 
  trl_rmw_tsa, 
  tsa_tpc, 
  tsa_tpc_oor_va, 
  tsa_tnpc, 
  tsa_tnpc_oor_va, 
  tsa_tnpc_nonseq, 
  tsa_gl, 
  tsa_rd_data, 
  tsa_trap_type, 
  asi_wr_mondo_head, 
  asi_wr_mondo_tail, 
  asi_wr_device_head, 
  asi_wr_device_tail, 
  asi_wr_res_err_head, 
  asi_wr_res_err_tail, 
  asi_wr_nonres_err_head, 
  asi_wr_nonres_err_tail, 
  asi_rd_iqr_reg, 
  asi_rd_iqr, 
  asi_rd_tpc, 
  asi_wr_tpc, 
  asi_rd_tnpc, 
  asi_wr_tnpc, 
  asi_rd_tstate, 
  asi_wr_tstate, 
  asi_rd_tt, 
  asi_wr_tt, 
  asi_rd_htstate, 
  asi_wr_htstate, 
  asi_wr_tba, 
  asi_wr_pstate, 
  asi_wr_hpstate, 
  asi_wr_htba, 
  asi_rd_asireg, 
  asi_wr_asireg, 
  asi_rd_h_pstate_tba, 
  asi_rd_tba_htba, 
  asi_rd_pstate_hpstate, 
  asi_wr_data_47_14, 
  asi_wr_data_07_00, 
  asi_tsd_wr_data_12, 
  asi_tsd_wr_data_10_08, 
  asi_tsd_wr_data_05_00, 
  asi_tsa_wr_data, 
  asi_tsa_wr_data_npc_oor_va, 
  asi_tsa_wr_data_npc_nonseq, 
  asi_mbist_ecc_in, 
  asi_mbist_run, 
  asi_mbist_cmpsel, 
  tel_ecc, 
  scan_out, 
  wmr_scan_out, 
  tsd_tba, 
  tsd_wr_tpc, 
  tsd_wr_tpc_oor_va, 
  tsd_wr_tnpc, 
  tsd_wr_tnpc_oor_va, 
  tsd_wr_tnpc_nonseq, 
  tsd_wr_gl, 
  tsd_wr_data, 
  tsd_wr_trap_type, 
  tsd_tpc, 
  tsd_tpc_oor_va, 
  tsd_tnpc, 
  tsd_tnpc_oor_va, 
  tsd_tnpc_nonseq, 
  tsd_mrqr_exc_, 
  tsd_dqr_exc_, 
  tsd_asi_data_, 
  tsd_asi_data, 
  tsd_ted_mra_rd_data, 
  tsd_hpstate_ibe, 
  tsd_hpstate_red, 
  tsd_hpstate_hpriv, 
  tsd_hpstate_tlz, 
  tsd_pstate_tct, 
  tsd_pstate_priv, 
  tsd_pstate_ie, 
  tsd_pstate_am, 
  tsd_htstate_hpriv, 
  tsd_shadow_pstate, 
  tsd_shadow_tpc, 
  tsd_shadow_tt, 
  tsd_mbist_data, 
  tsd_itlb_bypass, 
  tlu_itlb_bypass, 
  tlu_lsu_hpstate_hpriv, 
  tlu_lsu_pstate_priv, 
  tlu_ifu_hpstate_hpriv, 
  tlu_ifu_pstate_priv, 
  tlu_pmu_hpstate_hpriv, 
  tlu_pmu_pstate_priv, 
  tlu_dec_hpstate_hpriv, 
  tlu_dec_pstate_priv, 
  tlu_dec_pstate_pef, 
  tlu_pstate_cle, 
  tlu_pstate_am, 
  tlu_ccr, 
  tlu_asi, 
  tlu_cwp);
wire clk;
wire stop;
wire test;
wire pce_ov;
wire se;
wire siclk;
wire soclk;
wire [47:0] wr_data;
wire asireg_lat_wmr_scanin;
wire asireg_lat_wmr_scanout;
wire [7:0] asimux3;
wire [7:0] asimux2;
wire [7:0] asimux1;
wire [7:0] asimux0;
wire [7:0] asi3;
wire [7:0] asi2;
wire [7:0] asi1;
wire [7:0] asi0;
wire htba3_lat_wmr_scanin;
wire htba3_lat_wmr_scanout;
wire [47:14] htba3;
wire htba2_lat_wmr_scanin;
wire htba2_lat_wmr_scanout;
wire [47:14] htba2;
wire htba1_lat_wmr_scanin;
wire htba1_lat_wmr_scanout;
wire [47:14] htba1;
wire htba0_lat_wmr_scanin;
wire htba0_lat_wmr_scanout;
wire [47:14] htba0;
wire tba3_lat_wmr_scanin;
wire tba3_lat_wmr_scanout;
wire [47:15] tba3;
wire tba2_lat_wmr_scanin;
wire tba2_lat_wmr_scanout;
wire [47:15] tba2;
wire tba1_lat_wmr_scanin;
wire tba1_lat_wmr_scanout;
wire [47:15] tba1;
wire tba0_lat_wmr_scanin;
wire tba0_lat_wmr_scanout;
wire [47:15] tba0;
wire pstate_lat_scanin;
wire pstate_lat_scanout;
wire [10:0] wdr_pstate3;
wire [10:0] wdr_pstate2;
wire [10:0] wdr_pstate1;
wire [10:0] new_pstate0;
wire [10:0] new_pstate1;
wire [10:0] wdr_pstate0;
wire [10:0] new_pstate2;
wire [10:0] new_pstate3;
wire [10:0] pstate3_reg;
wire [10:0] pstate2_reg;
wire [10:0] pstate1_reg;
wire [10:0] pstate0_reg;
wire [10:0] shadow_pstate;
wire [12:0] arch_pstate3;
wire [12:0] arch_pstate2;
wire [12:0] arch_pstate1;
wire [12:0] arch_pstate0;
wire [12:0] arch_hpstate3;
wire [12:0] arch_hpstate2;
wire [12:0] arch_hpstate1;
wire [12:0] arch_hpstate0;
wire [12:0] asi_tsd_wr_data_crit;
wire [3:0] wr_pstate;
wire [10:0] asi_pstate3;
wire [10:0] asi_pstate2;
wire [10:0] asi_pstate1;
wire [10:0] asi_pstate0;
wire [3:0] wr_hpstate;
wire [10:0] asi_hpstate3;
wire [10:0] asi_hpstate2;
wire [10:0] asi_hpstate1;
wire [10:0] asi_hpstate0;
wire [10:0] don_ret_pstate;
wire read_tpc_lat_scanin;
wire read_tpc_lat_scanout;
wire [47:2] tpc_mod_crit;
wire tpc_oor_va_mod_crit;
wire [47:2] tpc_mod;
wire tpc_oor_va_mod;
wire read_tnpc_lat_scanin;
wire read_tnpc_lat_scanout;
wire [47:2] tnpc_mod_crit;
wire tnpc_oor_va_mod_crit;
wire tnpc_nonseq_mod_crit;
wire [47:2] tnpc_mod;
wire tnpc_oor_va_mod;
wire tnpc_nonseq_mod;
wire read_tstate_lat_scanin;
wire read_tstate_lat_scanout;
wire [1:0] gl_mod_crit;
wire [29:0] tstate_mod_crit;
wire [8:0] trap_type_mod_crit;
wire [1:0] gl_mod;
wire [29:0] tstate_mod;
wire [8:0] trap_type_mod;
wire wr_tpc_lat_scanin;
wire wr_tpc_lat_scanout;
wire shadow_tpc_lat_scanin;
wire shadow_tpc_lat_scanout;
wire wr_tnpc_lat_scanin;
wire wr_tnpc_lat_scanout;
wire wr_tstate_lat_scanin;
wire wr_tstate_lat_scanout;
wire [29:0] tsa_wr_data;
wire shadow_tt_lat_scanin;
wire shadow_tt_lat_scanout;
wire rd_ctl_lat_scanin;
wire rd_ctl_lat_scanout;
wire [2:0] rd_iqr;
wire [2:0] rd_h_pstate_tba;
wire [3:0] rd_asireg;
wire rd_tba_htba;
wire rd_pstate_hpstate;
wire rd_tpc;
wire rd_tnpc;
wire rd_tstate;
wire rd_tt;
wire rd_htstate;
wire rd_iqr_reg;
wire [47:0] asi_h_pstate;
wire [47:0] asi_h_tba;
wire [47:0] asi_data;
wire [17:6] iqr_ungated;
wire [17:6] iqr_reg;
wire [10:0] pstate_mod;
wire [47:0] tsa_asi_data;
wire [47:0] asi_data_;
wire cmpsel_lat_scanin;
wire cmpsel_lat_scanout;
wire [3:0] cmpsel;
wire tcu_muxtest_rep0;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		spc_aclk;
input		spc_bclk;
input		tcu_scan_en;
input		tcu_dectest;
input		tcu_muxtest;

input		tcu_scan_en_wmr;
input 		spc_aclk_wmr;		// Warm reset (non)scan
input		wmr_scan_in;

input	[1:0]	trl_shscanid;		// Select which thread to shadow

input	[7:0]	exu_ccr0;
input	[7:0]	exu_ccr1;
input	[7:0]	exu_ccr2;
input	[7:0]	exu_ccr3;

input	[2:0]	fls_cwp0;
input	[2:0]	fls_cwp1;
input	[2:0]	fls_cwp2;
input	[2:0]	fls_cwp3;

input	[47:2]	pct_tsa_pc;
input 		pct_tsa_pc_oor_va;
input	[47:2]	pct_tsa_npc;
input 		pct_tsa_npc_oor_va;
input 		pct_tsa_npc_nonseq;

input	[1:0]	trl_tsa_gl;
input	[8:0]	trl_tsa_trap_type;
input	[4:0]	trl_asireg_sel;		// Which asireg to update?
input		trl_asireg_en;		// Power management
input	[3:0]	trl_thread_sel;		// Which thread to redirect?
input	[2:0]	trl_tba_sel;		// Which thread & to HPRIV?
input	[4:0]	trl_pstate_thread_sel;	// Which thread to update pstate?
input	[3:0]	trl_don_ret_pstate_sel;	// Which thread takes done / retry?
input		trl_pstate_en;		// Power management
input		trl_reset_trap;
input		trl_stay_in_priv;
input		trl_other_trap;
input		trl_tl_gt_0;
input		trl_tsd_tsa_en;		// Power management
input		trl_tsd_tsa_wd_en;	// Power management
input		trl_save_tsa;
input		trl_capture_ss;		// Capture signal for TPC and TT
input		trl_rmw_tsa;		

input	[47:2]	tsa_tpc;
input		tsa_tpc_oor_va;
input	[47:2]	tsa_tnpc;
input		tsa_tnpc_oor_va;
input 		tsa_tnpc_nonseq;
input	[1:0]	tsa_gl;
input	[29:0]	tsa_rd_data;
input	[8:0]	tsa_trap_type;

input		asi_wr_mondo_head;
input		asi_wr_mondo_tail;
input		asi_wr_device_head;
input		asi_wr_device_tail;
input		asi_wr_res_err_head;
input		asi_wr_res_err_tail;
input		asi_wr_nonres_err_head;
input		asi_wr_nonres_err_tail;
input		asi_rd_iqr_reg;		// Read any interrupt queue reg
input	[2:0]	asi_rd_iqr;		// encoded TID for IQR read
input		asi_rd_tpc;
input		asi_wr_tpc;
input		asi_rd_tnpc;
input		asi_wr_tnpc;
input		asi_rd_tstate;
input		asi_wr_tstate;
input		asi_rd_tt;
input		asi_wr_tt;
input		asi_rd_htstate;
input		asi_wr_htstate;
input	[3:0]	asi_wr_tba;
input 	[3:0]	asi_wr_pstate;
input 	[3:0]	asi_wr_hpstate;
input 	[3:0]	asi_wr_htba;
input	[3:0]	asi_rd_asireg;
input	[3:0]	asi_wr_asireg;
input 	[2:0]	asi_rd_h_pstate_tba;
input		asi_rd_tba_htba;
input		asi_rd_pstate_hpstate;
input 	[47:14]	asi_wr_data_47_14;
input 	[7:0]	asi_wr_data_07_00;
input 		asi_tsd_wr_data_12;
input 	[10:8]	asi_tsd_wr_data_10_08;
input 	[5:0]	asi_tsd_wr_data_05_00;
input 	[47:0]	asi_tsa_wr_data;
input 		asi_tsa_wr_data_npc_oor_va;
input 		asi_tsa_wr_data_npc_nonseq;
input	[7:0]	asi_mbist_ecc_in;	// MBIST write data (not really ECC)
input		asi_mbist_run;		// MBIST
input	[3:0]	asi_mbist_cmpsel;	// MBIST

input	[15:0]	tel_ecc;		// MBIST

output		scan_out;

output		wmr_scan_out;		// Warm reset (non)scan

output	[47:14]	tsd_tba;		// Trap Base Address
output	[47:2]	tsd_wr_tpc;
output 		tsd_wr_tpc_oor_va;
output	[47:2]	tsd_wr_tnpc;
output 		tsd_wr_tnpc_oor_va;
output 		tsd_wr_tnpc_nonseq;
output	[1:0]	tsd_wr_gl;
output	[29:0]	tsd_wr_data;
output	[8:0]	tsd_wr_trap_type;

output 	[47:2]	tsd_tpc;
output		tsd_tpc_oor_va;
output 	[47:2]	tsd_tnpc;
output		tsd_tnpc_oor_va;
output		tsd_tnpc_nonseq;

output 		tsd_mrqr_exc_;		// Mondo or Res Err Queue Register exc
output 		tsd_dqr_exc_;		// Device  Queue Register exception

output	[47:2]	tsd_asi_data_;
output	[1:0]	tsd_asi_data;

output	[135:0]	tsd_ted_mra_rd_data;

output 	[3:0]	tsd_hpstate_ibe;
output 	[3:0]	tsd_hpstate_red;
output 	[3:0]	tsd_hpstate_hpriv;
output 	[3:0]	tsd_hpstate_tlz;
output 	[3:0]	tsd_pstate_tct;
output 	[3:0]	tsd_pstate_priv;
output 	[3:0]	tsd_pstate_ie;
output 	[3:0]	tsd_pstate_am;
output		tsd_htstate_hpriv;	// For saturating GL restore

output	[10:0]	tsd_shadow_pstate;
output	[47:2] tsd_shadow_tpc;
output	[8:0] tsd_shadow_tt;

output	[31:0]	tsd_mbist_data;		// MBIST

output	[3:0]	tsd_itlb_bypass;

output	[3:0]	tlu_itlb_bypass;

output	[3:0] tlu_lsu_hpstate_hpriv;
output	[3:0]	tlu_lsu_pstate_priv;
output	[3:0] tlu_ifu_hpstate_hpriv;
output	[3:0] tlu_ifu_pstate_priv;
output	[3:0] tlu_pmu_hpstate_hpriv;
output	[3:0]	tlu_pmu_pstate_priv;
output	[3:0] tlu_dec_hpstate_hpriv;
output	[3:0]	tlu_dec_pstate_priv;
output	[3:0]	tlu_dec_pstate_pef;
output	[3:0]	tlu_pstate_cle;
output	[3:0]	tlu_pstate_am;

output	[7:0]	tlu_ccr;
output	[7:0]	tlu_asi;
output	[2:0]	tlu_cwp;


////////////////////////////////////////////////////////////////////////////////

assign clk      = l2clk;
assign stop	= 1'b0;
assign test     = tcu_dectest;

tlu_tsd_dp_buff_macro__width_4 clk_control_buf  (
	.din	({tcu_pce_ov		       ,
		  tcu_scan_en		       ,
		  spc_aclk		       ,
		  spc_bclk		       }),
	.dout	({pce_ov		       ,
		  se			       ,
		  siclk			       ,
		  soclk			       })
);


////////////////////////////////////////////////////////////////////////////////
// Buffer off noncritical writes
//

tlu_tsd_dp_buff_macro__width_34 wr_data_47_14_buf  (
	.din	(asi_wr_data_47_14	[47:14]	),
	.dout	(wr_data		[47:14]	)
);

tlu_tsd_dp_buff_macro__width_8 wr_data_07_00_buf  (
	.din	(asi_wr_data_07_00	[7:0]	),
	.dout	(wr_data		[7:0]	)
);


////////////////////////////////////////////////////////////////////////////////
// Shadow copy of ASI registers
//

tlu_tsd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_32 asireg_lat     ( // FS:wmr_protect
	.scan_in(asireg_lat_wmr_scanin),
	.scan_out(asireg_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.din4	({asimux3		[7:0],
		  asimux2		[7:0],
		  asimux1		[7:0],
		  asimux0		[7:0]}),
	.din3	({wr_data		[7:0],
		  asimux2		[7:0],
		  asimux1		[7:0],
		  asimux0		[7:0]}),
	.din2	({asimux3		[7:0],
		  wr_data		[7:0],
		  asimux1		[7:0],
		  asimux0		[7:0]}),
	.din1	({asimux3		[7:0],
		  asimux2		[7:0],
		  wr_data		[7:0],
		  asimux0		[7:0]}),
	.din0	({asimux3		[7:0],
		  asimux2		[7:0],
		  asimux1		[7:0],
		  wr_data		[7:0]}),
	.sel3	(asi_wr_asireg		[3   ]	),
	.sel2	(asi_wr_asireg		[2   ]	),
	.sel1	(asi_wr_asireg		[1   ]	),
	.sel0	(asi_wr_asireg		[0   ]	),
	.en	(trl_asireg_en			),
	.dout	({asi3			[7:0],
		  asi2			[7:0],
		  asi1			[7:0],
		  asi0			[7:0]}),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_mux_macro__mux_aonpe__ports_5__stack_48c__width_32 asireg_mux    
(
	.din4	({asi3			[7:0],
		  asi2			[7:0],
		  asi1			[7:0],
		  asi0			[7:0]}),
	.din3	({tlu_asi		[7:0],
		  asi2			[7:0],
		  asi1			[7:0],
		  asi0			[7:0]}),
	.din2	({asi3			[7:0],
		  tlu_asi		[7:0],
		  asi1			[7:0],
		  asi0			[7:0]}),
	.din1	({asi3			[7:0],
		  asi2			[7:0],
		  tlu_asi		[7:0],
		  asi0			[7:0]}),
	.din0	({asi3			[7:0],
		  asi2			[7:0],
		  asi1			[7:0],
		  tlu_asi		[7:0]}),
	.sel4	(trl_asireg_sel		[4   ]	),
	.sel3	(trl_asireg_sel		[3   ]	),
	.sel2	(trl_asireg_sel		[2   ]	),
	.sel1	(trl_asireg_sel		[1   ]	),
	.sel0	(trl_asireg_sel		[0   ]	),
	.dout	({asimux3		[7:0],
		  asimux2		[7:0],
		  asimux1		[7:0],
		  asimux0		[7:0]})
);


////////////////////////////////////////////////////////////////////////////////
// Trap Base Addresses and Hyperprivileged TBAs

tlu_tsd_dp_msff_macro__left_14__stack_48c__width_34 htba3_lat    ( // FS:wmr_protect
	.scan_in(htba3_lat_wmr_scanin),
	.scan_out(htba3_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_htba		[3]	),
	.din	(wr_data		[47:14]	),
	.dout	(htba3			[47:14]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__left_14__stack_48c__width_34 htba2_lat    ( // FS:wmr_protect
	.scan_in(htba2_lat_wmr_scanin),
	.scan_out(htba2_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_htba		[2]	),
	.din	(wr_data		[47:14]	),
	.dout	(htba2			[47:14]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__left_14__stack_48c__width_34 htba1_lat    ( // FS:wmr_protect
	.scan_in(htba1_lat_wmr_scanin),
	.scan_out(htba1_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_htba		[1]	),
	.din	(wr_data		[47:14]	),
	.dout	(htba1			[47:14]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__left_14__stack_48c__width_34 htba0_lat    ( // FS:wmr_protect
	.scan_in(htba0_lat_wmr_scanin),
	.scan_out(htba0_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_htba		[0]	),
	.din	(wr_data		[47:14]	),
	.dout	(htba0			[47:14]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__left_15__stack_48c__width_33 tba3_lat    ( // FS:wmr_protect
	.scan_in(tba3_lat_wmr_scanin),
	.scan_out(tba3_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_tba		[3]	),
	.din	(wr_data		[47:15]	),
	.dout	(tba3			[47:15]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__left_15__stack_48c__width_33 tba2_lat    ( // FS:wmr_protect
	.scan_in(tba2_lat_wmr_scanin),
	.scan_out(tba2_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_tba		[2]	),
	.din	(wr_data		[47:15]	),
	.dout	(tba2			[47:15]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__left_15__stack_48c__width_33 tba1_lat    ( // FS:wmr_protect
	.scan_in(tba1_lat_wmr_scanin),
	.scan_out(tba1_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_tba		[1]	),
	.din	(wr_data		[47:15]	),
	.dout	(tba1			[47:15]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__left_15__stack_48c__width_33 tba0_lat    ( // FS:wmr_protect
	.scan_in(tba0_lat_wmr_scanin),
	.scan_out(tba0_lat_wmr_scanout),
	.se	(tcu_scan_en_wmr		),
	.siclk	(spc_aclk_wmr			),
	.en	(asi_wr_tba		[0]	),
	.din	(wr_data		[47:15]	),
	.dout	(tba0			[47:15]	),
  .clk(clk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


////////////////////////////////////////////////////////////////////////////////
// Mux the TBAs

tlu_tsd_dp_mux_macro__dmux_8x__left_14__mux_aodec__ports_8__stack_48c__width_34 tba_mux       (
	.din0	({tba0			[47:15],
		  trl_tl_gt_0		       }),
	.din1	({tba1			[47:15],
		  trl_tl_gt_0		       }),
	.din2	({tba2			[47:15],
		  trl_tl_gt_0		       }),
	.din3	({tba3			[47:15],
		  trl_tl_gt_0		       }),
	.din4	(htba0			[47:14]	),
	.din5	(htba1			[47:14]	),
	.din6	(htba2			[47:14]	),
	.din7	(htba3			[47:14]	),
	.sel	(trl_tba_sel		[2:0]	),
	.dout	(tsd_tba		[47:14] )
);


////////////////////////////////////////////////////////////////////////////////
// PSTATE & HPSTATE
//	Note that Niagara 1 did not implement MM (bits 7:6 of PSTATE)
//
//			  HP  HP   HP   HP
// Name                  IBE RED HPRIV TLZ  TCT CLE TLE PEF AM PRIV IE 
// Architected Position   10  5    2    0    12  9   8   4  3   2   1  
// Physical Position      10  5    6    0     7  9   8   4  3   2   1

tlu_tsd_dp_msff_macro__mux_aonpe__ports_5__stack_48c__width_44 pstate_lat     (
	.scan_in(pstate_lat_scanin),
	.scan_out(pstate_lat_scanout),
	.din0	({wdr_pstate3		[10:0],
		  wdr_pstate2		[10:0],
		  wdr_pstate1		[10:0],
		  new_pstate0		[10:0]}),
	.din1	({wdr_pstate3		[10:0],
		  wdr_pstate2		[10:0],
		  new_pstate1		[10:0],
		  wdr_pstate0		[10:0]}),
	.din2	({wdr_pstate3		[10:0],
		  new_pstate2		[10:0],
		  wdr_pstate1		[10:0],
		  wdr_pstate0		[10:0]}),
	.din3	({new_pstate3		[10:0],
		  wdr_pstate2		[10:0],
		  wdr_pstate1		[10:0],
		  wdr_pstate0		[10:0]}),
	.din4	({wdr_pstate3		[10:0],
		  wdr_pstate2		[10:0],
		  wdr_pstate1		[10:0],
		  wdr_pstate0		[10:0]}),
	.sel0	(trl_pstate_thread_sel	[0   ]	),
	.sel1	(trl_pstate_thread_sel	[1   ]	),
	.sel2	(trl_pstate_thread_sel	[2   ]	),
	.sel3	(trl_pstate_thread_sel	[3   ]	),
	.sel4	(trl_pstate_thread_sel	[4   ]	),
	.en	(trl_pstate_en			),
	.dout	({pstate3_reg		[10:0],
		  pstate2_reg		[10:0],
		  pstate1_reg		[10:0],
		  pstate0_reg		[10:0]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_mux_macro__mux_aodec__ports_4__stack_48c__width_11 shadow_pstate_mux     (
	.din0	(pstate0_reg		[10:0]	),
	.din1	(pstate1_reg		[10:0]	),
	.din2	(pstate2_reg		[10:0]	),
	.din3	(pstate3_reg		[10:0]	),
	.sel	(trl_shscanid		[1:0]	),
	.dout	(shadow_pstate		[10:0]	)
);

assign tsd_shadow_pstate[10:0] =
       shadow_pstate[10:0];

assign arch_pstate3[12:0] =
       {pstate3_reg[7], 2'b00, pstate3_reg[9:8], 3'b000, pstate3_reg[4:1], 
	 1'b0};
assign arch_pstate2[12:0] =
       {pstate2_reg[7], 2'b00, pstate2_reg[9:8], 3'b000, pstate2_reg[4:1],
	1'b0};
assign arch_pstate1[12:0] =
       {pstate1_reg[7], 2'b00, pstate1_reg[9:8], 3'b000, pstate1_reg[4:1],
	1'b0};
assign arch_pstate0[12:0] =
       {pstate0_reg[7], 2'b00, pstate0_reg[9:8], 3'b000, pstate0_reg[4:1],
	1'b0};

assign arch_hpstate3[12:0] =
       {{2 {1'b0}}, pstate3_reg[10], {4 {1'b0}}, pstate3_reg[5],
	 {2 {1'b0}}, pstate3_reg[6], 1'b0, pstate3_reg[0]};
assign arch_hpstate2[12:0] =
       {{2 {1'b0}}, pstate2_reg[10], {4 {1'b0}}, pstate2_reg[5],
	 {2 {1'b0}}, pstate2_reg[6], 1'b0, pstate2_reg[0]};
assign arch_hpstate1[12:0] =
       {{2 {1'b0}}, pstate1_reg[10], {4 {1'b0}}, pstate1_reg[5],
	 {2 {1'b0}}, pstate1_reg[6], 1'b0, pstate1_reg[0]};
assign arch_hpstate0[12:0] =
       {{2 {1'b0}}, pstate0_reg[10], {4 {1'b0}}, pstate0_reg[5],
	 {2 {1'b0}}, pstate0_reg[6], 1'b0, pstate0_reg[0]};

tlu_tsd_dp_buff_macro__rep_1__stack_48c__width_48 pmu_pstate_buf    (
	.din	({    pstate3_reg	[9   ],
		  {5 {pstate3_reg	[6 ]}},
	  	      pstate3_reg	[4   ],
		  {5 {pstate3_reg	[2 ]}},
		      pstate2_reg	[9   ],
		  {5 {pstate2_reg	[6 ]}},
	  	      pstate2_reg	[4   ],
		  {5 {pstate2_reg	[2 ]}},
		      pstate1_reg	[9   ],
		  {5 {pstate1_reg	[6 ]}},
	  	      pstate1_reg	[4   ],
		  {5 {pstate1_reg	[2 ]}},
		      pstate0_reg	[9   ],
		  {5 {pstate0_reg	[6 ]}},
	  	      pstate0_reg	[4   ],
		  {5 {pstate0_reg	[2 ]}}}),
	.dout	({tlu_pstate_cle	[3   ],
		  tlu_pmu_hpstate_hpriv [3   ],
		  tlu_lsu_hpstate_hpriv [3   ],
		  tlu_dec_hpstate_hpriv [3   ],
		  tlu_ifu_hpstate_hpriv [3   ],
		  tsd_hpstate_hpriv     [3   ],
		  tlu_dec_pstate_pef    [3   ],
		  tlu_pmu_pstate_priv	[3   ],
		  tlu_lsu_pstate_priv	[3   ],
		  tlu_dec_pstate_priv	[3   ],
		  tlu_ifu_pstate_priv	[3   ],
		  tsd_pstate_priv	[3   ],
		  tlu_pstate_cle	[2   ],
		  tlu_pmu_hpstate_hpriv [2   ],
		  tlu_lsu_hpstate_hpriv [2   ],
		  tlu_dec_hpstate_hpriv [2   ],
		  tlu_ifu_hpstate_hpriv [2   ],
		  tsd_hpstate_hpriv     [2   ],
		  tlu_dec_pstate_pef    [2   ],
		  tlu_pmu_pstate_priv	[2   ],
		  tlu_lsu_pstate_priv	[2   ],
		  tlu_dec_pstate_priv	[2   ],
		  tlu_ifu_pstate_priv	[2   ],
		  tsd_pstate_priv	[2   ],
		  tlu_pstate_cle	[1   ],
		  tlu_pmu_hpstate_hpriv [1   ],
		  tlu_lsu_hpstate_hpriv [1   ],
		  tlu_dec_hpstate_hpriv [1   ],
		  tlu_ifu_hpstate_hpriv [1   ],
		  tsd_hpstate_hpriv     [1   ],
		  tlu_dec_pstate_pef    [1   ],
		  tlu_pmu_pstate_priv	[1   ],
		  tlu_lsu_pstate_priv	[1   ],
		  tlu_dec_pstate_priv	[1   ],
		  tlu_ifu_pstate_priv	[1   ],
		  tsd_pstate_priv	[1   ],
		  tlu_pstate_cle	[0   ],
		  tlu_pmu_hpstate_hpriv [0   ],
		  tlu_lsu_hpstate_hpriv [0   ],
		  tlu_dec_hpstate_hpriv [0   ],
		  tlu_ifu_hpstate_hpriv [0   ],
		  tsd_hpstate_hpriv     [0   ],
		  tlu_dec_pstate_pef    [0   ],
		  tlu_pmu_pstate_priv	[0   ],
		  tlu_lsu_pstate_priv	[0   ],
		  tlu_dec_pstate_priv	[0   ],
		  tlu_ifu_pstate_priv	[0   ],
		  tsd_pstate_priv	[0   ]})
);

assign tsd_pstate_tct[3:0] =
       {pstate3_reg[7], pstate2_reg[7], pstate1_reg[7], pstate0_reg[7]};

assign tlu_pstate_am[3:0] = 
       {pstate3_reg[3], pstate2_reg[3], pstate1_reg[3], pstate0_reg[3]};

assign tsd_pstate_am[3:0] =
       {pstate3_reg[3], pstate2_reg[3], pstate1_reg[3], pstate0_reg[3]};

assign tsd_pstate_ie[3:0] =
       {pstate3_reg[1], pstate2_reg[1], pstate1_reg[1], pstate0_reg[1]};

assign tsd_hpstate_ibe[3:0] =
       {pstate3_reg[10], pstate2_reg[10], pstate1_reg[10], pstate0_reg[10]};
 
assign tsd_hpstate_red[3:0] =
       {pstate3_reg[5], pstate2_reg[5], pstate1_reg[5], pstate0_reg[5]};

assign tsd_hpstate_tlz[3:0] =
       {pstate3_reg[0], pstate2_reg[0], pstate1_reg[0], pstate0_reg[0]};

// Bypass ITLB if in RED state or in HPRIV
tlu_tsd_dp_or_macro__ports_2__stack_4r__width_4 itlb_bypass_or    (
	.din0	({pstate3_reg		[5   ],
		  pstate2_reg		[5   ],
		  pstate1_reg		[5   ],
		  pstate0_reg		[5   ]}),
	.din1	({pstate3_reg		[6   ],
		  pstate2_reg		[6   ],
		  pstate1_reg		[6   ],
		  pstate0_reg		[6   ]}),
	.dout	(tlu_itlb_bypass	[3:0]	)
);								   

tlu_tsd_dp_buff_macro__rep_1__stack_4r__width_4 itlb_bypass_buf    (
	.din	(tlu_itlb_bypass	[3:0]	),
	.dout	(tsd_itlb_bypass	[3:0]	)
);								   

assign asi_tsd_wr_data_crit[12] =
       asi_tsd_wr_data_12;	
assign asi_tsd_wr_data_crit[10:8] =
       asi_tsd_wr_data_10_08[10:8];	
assign asi_tsd_wr_data_crit[5:0] =
       asi_tsd_wr_data_05_00[5:0];	

// Mux in ASI writes of PSTATE
tlu_tsd_dp_mux_macro__mux_aope__ports_5__stack_48c__width_44 asi_pstate_mux     (
	.din4	({pstate3_reg		[10:0],
		  pstate2_reg		[10:0],
		  pstate1_reg		[10:0],
		  pstate0_reg		[10:0]}),
	.din3	({pstate3_reg		[10   ],
		  asi_tsd_wr_data_crit	[9:8],
		  asi_tsd_wr_data_crit	[12   ],
		  pstate3_reg		[6:5],
		  asi_tsd_wr_data_crit	[4:1],
		  pstate3_reg		[0   ],
		  pstate2_reg		[10:0],
		  pstate1_reg		[10:0],
		  pstate0_reg		[10:0]}),
	.din2	({pstate3_reg		[10:0],
		  pstate2_reg		[10   ],
		  asi_tsd_wr_data_crit	[9:8],
		  asi_tsd_wr_data_crit	[12   ],
		  pstate2_reg		[6:5],
		  asi_tsd_wr_data_crit	[4:1],
		  pstate2_reg		[0   ],
		  pstate1_reg		[10:0],
		  pstate0_reg		[10:0]}),
	.din1	({pstate3_reg		[10:0],
		  pstate2_reg		[10:0],
		  pstate1_reg		[10   ],
		  asi_tsd_wr_data_crit	[9:8],
		  asi_tsd_wr_data_crit	[12   ],
		  pstate1_reg		[6:5],
		  asi_tsd_wr_data_crit	[4:1],
		  pstate1_reg		[0   ],
		  pstate0_reg		[10:0]}),
	.din0	({pstate3_reg		[10:0],
		  pstate2_reg		[10:0],
		  pstate1_reg		[10:0],
		  pstate0_reg		[10   ],
		  asi_tsd_wr_data_crit	[9:8],
		  asi_tsd_wr_data_crit	[12   ],
		  pstate0_reg		[6:5],
		  asi_tsd_wr_data_crit	[4:1],
		  pstate0_reg		[0   ]}),
	.sel3	(wr_pstate		[3   ]	),
	.sel2	(wr_pstate		[2   ]	),
	.sel1	(wr_pstate		[1   ]	),
	.sel0	(wr_pstate		[0   ]	),
	.dout	({asi_pstate3		[10:0],
		  asi_pstate2		[10:0],
		  asi_pstate1		[10:0],
		  asi_pstate0		[10:0]})
);

// Mux in ASI writes of HPSTATE
tlu_tsd_dp_mux_macro__mux_aope__ports_5__stack_48c__width_44 asi_hpstate_mux     (
	.din4	({asi_pstate3		[10:0],
		  asi_pstate2		[10:0],
		  asi_pstate1		[10:0],
		  asi_pstate0		[10:0]}),
	.din3	({asi_tsd_wr_data_crit	[10   ],
		  asi_pstate3		[9:7],
		  asi_tsd_wr_data_crit	[2   ],
		  asi_tsd_wr_data_crit	[5   ],
		  asi_pstate3		[4:1],
		  asi_tsd_wr_data_crit	[0   ],
		  asi_pstate2		[10:0],
		  asi_pstate1		[10:0],
		  asi_pstate0		[10:0]}),
	.din2	({asi_pstate3		[10:0],
		  asi_tsd_wr_data_crit	[10   ],
		  asi_pstate2		[9:7],
		  asi_tsd_wr_data_crit	[2   ],
		  asi_tsd_wr_data_crit	[5   ],
		  asi_pstate2		[4:1],
		  asi_tsd_wr_data_crit	[0   ],
		  asi_pstate1		[10:0],
		  asi_pstate0		[10:0]}),
	.din1	({asi_pstate3		[10:0],
		  asi_pstate2		[10:0],
		  asi_tsd_wr_data_crit	[10   ],
		  asi_pstate1		[9:7],
		  asi_tsd_wr_data_crit	[2   ],
		  asi_tsd_wr_data_crit	[5   ],
		  asi_pstate1		[4:1],
		  asi_tsd_wr_data_crit	[0   ],
		  asi_pstate0		[10:0]}),
	.din0	({asi_pstate3		[10:0],
		  asi_pstate2		[10:0],
		  asi_pstate1		[10:0],
		  asi_tsd_wr_data_crit	[10   ],
		  asi_pstate0		[9:7],
		  asi_tsd_wr_data_crit	[2   ],
		  asi_tsd_wr_data_crit	[5   ],
		  asi_pstate0		[4:1],
		  asi_tsd_wr_data_crit	[0   ]}),
	.sel3	(wr_hpstate		[3   ]	),
	.sel2	(wr_hpstate		[2   ]	),
	.sel1	(wr_hpstate		[1   ]	),
	.sel0	(wr_hpstate		[0   ]	),
	.dout	({asi_hpstate3		[10:0],
		  asi_hpstate2		[10:0],
		  asi_hpstate1		[10:0],
		  asi_hpstate0		[10:0]})
);

// Mux in done and retry H/PSTATE restores if ECC is good		 
tlu_tsd_dp_mux_macro__mux_aope__ports_5__stack_48c__width_44 don_ret_mux     (
	.din4	({asi_hpstate3		[10:0],
		  asi_hpstate2		[10:0],
		  asi_hpstate1		[10:0],
		  asi_hpstate0		[10:0]}),
	.din3	({don_ret_pstate	[10:0],
		  asi_hpstate2		[10:0],
		  asi_hpstate1		[10:0],
		  asi_hpstate0		[10:0]}),
	.din2	({asi_hpstate3		[10:0],
		  don_ret_pstate	[10:0],
		  asi_hpstate1		[10:0],
		  asi_hpstate0		[10:0]}),
	.din1	({asi_hpstate3		[10:0],
		  asi_hpstate2		[10:0],
		  don_ret_pstate	[10:0],
		  asi_hpstate0		[10:0]}),
	.din0	({asi_hpstate3		[10:0],
		  asi_hpstate2		[10:0],
		  asi_hpstate1		[10:0],
		  don_ret_pstate	[10:0]}),
	.sel3	(trl_don_ret_pstate_sel	[3   ]	),
	.sel2	(trl_don_ret_pstate_sel	[2   ]	),
	.sel1	(trl_don_ret_pstate_sel	[1   ]	),
	.sel0	(trl_don_ret_pstate_sel	[0   ]	),
	.dout	({wdr_pstate3		[10:0],
		  wdr_pstate2		[10:0],
		  wdr_pstate1		[10:0],
		  wdr_pstate0		[10:0]})
);

tlu_tsd_dp_mux_macro__mux_aonpe__ports_3__stack_48c__width_44 trap_pstate_mux     (
	// Normal trap to hypervisor
	// IBE to 0, HPRIV to 1,  RED to 0, TCT to 0, CLE to 0, PEF to 0, 
	// AM to 0, PRIV to 0, IE to 0
	.din2 	({2'b00			       ,
		  pstate3_reg		[8   ],
		  7'b0101000		       ,	
		  pstate3_reg		[0   ],
		  2'b00			       ,
		  pstate2_reg		[8   ],
		  7'b0101000		       ,	
		  pstate2_reg		[0   ],
		  2'b00			       ,
		  pstate1_reg		[8   ],
		  7'b0101000		       ,	
		  pstate1_reg		[0   ],
		  2'b00			       ,
		  pstate0_reg		[8   ],
		  7'b0101000		       ,	
		  pstate0_reg		[0   ]}),
	// Normal trap not to hypervisor
	// HPRIV unchanged, RED to 0, TCT to 0, PEF to 1, AM to 0, PRIV to 1, 
	// IE to 0, CLE set to TLE
	.din1	({pstate3_reg		[10   ],
		  pstate3_reg		[8   ],
		  pstate3_reg		[8   ],
		  1'b0			       ,
		  pstate3_reg		[6   ],
		  5'b01010		       ,	
		  pstate3_reg		[0   ],
		  pstate2_reg		[10   ],
		  pstate2_reg		[8   ],
		  pstate2_reg		[8   ],
		  1'b0			       ,
		  pstate2_reg		[6   ],
		  5'b01010		       ,	
		  pstate2_reg		[0   ],
		  pstate1_reg		[10   ],
		  pstate1_reg		[8   ],
		  pstate1_reg		[8   ],
		  1'b0			       ,
		  pstate1_reg		[6   ],
		  5'b01010		       ,	
		  pstate1_reg		[0   ],
		  pstate0_reg		[10   ],
		  pstate0_reg		[8   ],
		  pstate0_reg		[8   ],
		  1'b0			       ,
		  pstate0_reg		[6   ],
		  5'b01010		       ,	
		  pstate0_reg		[0   ]}),
	// Any reset trap
	.din0	({11'b00001110100	       ,	
		  11'b00001110100	       ,	
		  11'b00001110100	       ,	
		  11'b00001110100	       }),
	.sel2	(trl_other_trap			),
	.sel1	(trl_stay_in_priv		),
	.sel0	(trl_reset_trap			),
	.dout	({new_pstate3		[10:0],
		  new_pstate2		[10:0],
		  new_pstate1		[10:0],
		  new_pstate0		[10:0]})
);


////////////////////////////////////////////////////////////////////////////////
// Handle read-modify-write ASI accesses
//

// First capture read
tlu_tsd_dp_msff_macro__left_1__minbuff_1__stack_48c__width_47 read_tpc_lat     (
	.scan_in(read_tpc_lat_scanin),
	.scan_out(read_tpc_lat_scanout),
	.en	(trl_tsd_tsa_en			),
	.din	({tsa_tpc		[47:2],
		  tsa_tpc_oor_va	       }),
	.dout	({tpc_mod_crit		[47:2],
		  tpc_oor_va_mod_crit	       }),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_buff_macro__left_1__rep_1__stack_48c__width_47 read_tpc_buf     (
	.din	({tpc_mod_crit		[47:2],
		  tpc_oor_va_mod_crit	       }),
	.dout	({tpc_mod		[47:2],
		  tpc_oor_va_mod	       })
);

assign tsd_tpc[47:2] =
       tpc_mod[47:2];
assign tsd_tpc_oor_va = 
       tpc_oor_va_mod;

tlu_tsd_dp_msff_macro__minbuff_1__stack_48c__width_48 read_tnpc_lat    (
	.scan_in(read_tnpc_lat_scanin),
	.scan_out(read_tnpc_lat_scanout),
	.en	(trl_tsd_tsa_en			),
	.din	({tsa_tnpc		[47:2],
		  tsa_tnpc_oor_va	       ,
		  tsa_tnpc_nonseq	       }),
	.dout	({tnpc_mod_crit		[47:2],
		  tnpc_oor_va_mod_crit	       ,
		  tnpc_nonseq_mod_crit	       }),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_buff_macro__rep_1__stack_48c__width_48 read_tnpc_buf    (
	.din	({tnpc_mod_crit		[47:2],
		  tnpc_oor_va_mod_crit	       ,
		  tnpc_nonseq_mod_crit	       }),
	.dout	({tnpc_mod		[47:2],
		  tnpc_oor_va_mod	       ,
		  tnpc_nonseq_mod	       })
);

assign tsd_tnpc[47:2] =
       tnpc_mod[47:2];
assign tsd_tnpc_oor_va = 
       tnpc_oor_va_mod;
assign tsd_tnpc_nonseq =
       tnpc_nonseq_mod;

tlu_tsd_dp_msff_macro__left_7__minbuff_1__stack_48c__width_41 read_tstate_lat     (
	.scan_in(read_tstate_lat_scanin),
	.scan_out(read_tstate_lat_scanout),
	.en	(trl_tsd_tsa_en			),
	.din	({tsa_gl		[1:0],
		  tsa_rd_data		[29:0],
		  tsa_trap_type		[8:0]}),
	.dout	({gl_mod_crit		[1:0],
		  tstate_mod_crit	[29:0],
		  trap_type_mod_crit	[8:0]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_buff_macro__left_6__stack_48c__width_42 read_tstate_buf    (
	.din	({gl_mod_crit		[1:0],
		  tstate_mod_crit	[29:0],
		  trap_type_mod_crit	[8:0],
		  tstate_mod_crit	   [9]}),
	.dout	({gl_mod		[1:0],
		  tstate_mod		[29:0],
		  trap_type_mod		[8:0],
		  tsd_htstate_hpriv	      })
);

assign tsd_ted_mra_rd_data[135:0] =
       {tpc_oor_va_mod_crit	       ,
	tnpc_oor_va_mod_crit	       ,
	tnpc_nonseq_mod_crit	       ,
	gl_mod_crit		[1:0],
	tstate_mod_crit		[29:0],
	trap_type_mod_crit	[8:0],
	tpc_mod_crit		[47:2],
	tnpc_mod_crit		[47:2]};


// Then modify data
tlu_tsd_dp_msff_macro__left_1__mux_aope__ports_8__stack_48c__width_47 wr_tpc_lat      (
	.scan_in(wr_tpc_lat_scanin),
	.scan_out(wr_tpc_lat_scanout),
	.din0	({asi_mbist_ecc_in	[3:0],
		  {5 {asi_mbist_ecc_in	[7:0]}},
		  asi_mbist_ecc_in	[7:6],
		  asi_mbist_ecc_in	[1   ]}),
	.din1	({asi_tsa_wr_data	[47:2],
		  1'b0			       }),
	.din2	({asi_tsa_wr_data	[17:6],	// Mondo or Res Head
		  tpc_mod		[35:2],
		  tpc_oor_va_mod	       }),
	.din3	({tpc_mod		[47:36],
		  asi_tsa_wr_data	[17:6],	// Device or Nonres Head
		  tpc_mod		[23:2],
		  tpc_oor_va_mod	       }),
	.din4	({asi_tsa_wr_data	[17:6],	// Mondo or Res Head
		  tpc_mod		[35:2],
		  tpc_oor_va_mod	       }),
	.din5	({tpc_mod		[47:36],
		  asi_tsa_wr_data	[17:6],	// Device or Nonres Head
		  tpc_mod		[23:2],
		  tpc_oor_va_mod	       }),
	.din6	({tpc_mod		[47:2],
		  tpc_oor_va_mod	       }),
	.din7	({pct_tsa_pc		[47:2],
		  pct_tsa_pc_oor_va	       }),
	.sel0	(asi_mbist_run			),
	.sel1	(asi_wr_tpc			),
	.sel2	(asi_wr_mondo_head		),
	.sel3	(asi_wr_device_head		),
	.sel4	(asi_wr_res_err_head		),
	.sel5	(asi_wr_nonres_err_head		),
	.sel6	(trl_rmw_tsa			),
	.en	(trl_tsd_tsa_wd_en		),
	.dout	({tsd_wr_tpc		[47:2],
		  tsd_wr_tpc_oor_va	       }),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__left_2__minbuff_1__stack_48c__width_46 shadow_tpc_lat     (
	.scan_in(shadow_tpc_lat_scanin),
	.scan_out(shadow_tpc_lat_scanout),
	.din	(tsd_wr_tpc		[47:2] ),
	.en	(trl_capture_ss			),
	.dout	(tsd_shadow_tpc		[47:2]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Check Interrupt Queue Registers on write to any of them
// (qualification occurs in tlu_fls_ctl)
// Convert queue registers to 12 bit.
tlu_tsd_dp_cmp_macro__width_12 mondo_res_err_cmp  (
	.din0	(tsd_wr_tpc		[47:36]	),
	.din1	(tsd_wr_tnpc		[47:36]	),
	.dout	(tsd_mrqr_exc_		)
);

tlu_tsd_dp_cmp_macro__width_12 device_cmp  (
	.din0	(tsd_wr_tpc		[35:24]	),
	.din1	(tsd_wr_tnpc		[35:24]	),
	.dout	(tsd_dqr_exc_			)
);

// MBIST writes factored into asi_tsa_wr_data for TNPC
tlu_tsd_dp_msff_macro__mux_aope__ports_8__stack_48c__width_48 wr_tnpc_lat     (
	.scan_in(wr_tnpc_lat_scanin),
	.scan_out(wr_tnpc_lat_scanout),
	.din0	({asi_tsa_wr_data	[47:2],
		  asi_tsa_wr_data_npc_oor_va   ,
		  asi_tsa_wr_data_npc_nonseq   }),
	.din1	({tnpc_mod		[47:2],
		  tnpc_oor_va_mod	       ,
		  1'b1			       }),
	.din2	({asi_tsa_wr_data	[17:6],	// Mondo or Res Tail
		  tnpc_mod		[35:2],
		  tnpc_oor_va_mod	       ,
		  tnpc_nonseq_mod	       }),
	.din3	({tnpc_mod		[47:36],
		  asi_tsa_wr_data	[17:6],	// Device or Nonres Tail
		  tnpc_mod		[23:2],
		  tnpc_oor_va_mod	       ,
		  tnpc_nonseq_mod	       }),
	.din4	({asi_tsa_wr_data	[17:6],	// Mondo or Res Tail
		  tnpc_mod		[35:2],
		  tnpc_oor_va_mod	       ,
		  tnpc_nonseq_mod	       }),
	.din5	({tnpc_mod		[47:36],
		  asi_tsa_wr_data	[17:6],	// Device or Nonres Tail
		  tnpc_mod		[23:2],
		  tnpc_oor_va_mod	       ,
		  tnpc_nonseq_mod	       }),
	.din6	({tnpc_mod		[47:2],
		  tnpc_oor_va_mod	       ,
		  tnpc_nonseq_mod	       }),
	.din7	({pct_tsa_npc		[47:2],
		  pct_tsa_npc_oor_va	       ,
		  pct_tsa_npc_nonseq	       }),
	.sel0	(asi_wr_tnpc			),
	.sel1	(asi_wr_tpc			),
	.sel2	(asi_wr_mondo_tail		),
	.sel3	(asi_wr_device_tail		),
	.sel4	(asi_wr_res_err_tail		),
	.sel5	(asi_wr_nonres_err_tail		),
	.sel6	(trl_rmw_tsa			),
	.en	(trl_tsd_tsa_wd_en		),
	.dout	({tsd_wr_tnpc		[47:2],
		  tsd_wr_tnpc_oor_va	       ,
		  tsd_wr_tnpc_nonseq	       }),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_msff_macro__mux_aope__ports_8__stack_48c__width_41 wr_tstate_lat     (
	.scan_in(wr_tstate_lat_scanin),
	.scan_out(wr_tstate_lat_scanout),
	.din0	({asi_mbist_ecc_in	[4:0],
		  {4 {asi_mbist_ecc_in	[7:0]}},		  
		  asi_mbist_ecc_in	[7:4]}),		  
	.din1	({gl_mod		[1:0],
		  tstate_mod		[29:0],
		  trap_type_mod		[8:0]}),
	.din2	({gl_mod		[1:0],
		  tstate_mod		[29:0],
		  trap_type_mod		[8:0]}),
	.din3	({asi_tsa_wr_data	[41:40], // GL
		  asi_tsa_wr_data	[39:32], // CCR
		  asi_tsa_wr_data	[31:24], // ASI
		  tstate_mod		[13   ], // IBE
		  asi_tsa_wr_data	[17:16], // CLE, TLE
		  asi_tsa_wr_data	[20   ], // TCT
		  tstate_mod		[9   ], // HPRIV
		  tstate_mod		[8   ], // RED
		  asi_tsa_wr_data	[12:9], // PEF, AM, PRIV, IE
		  tstate_mod		[3   ], // TLZ
		  asi_tsa_wr_data	[2:0], // CWP
		  trap_type_mod		[8:0]}), // Trap Type
	.din4	({gl_mod		[1:0],
		  tstate_mod 		[29:0], // Everything but Trap Type
		  asi_tsa_wr_data	[8:0]}), // Trap Type
	.din5	({gl_mod 		[1:0], // GL
		  tstate_mod 		[29:22], // CCR
		  tstate_mod 		[21:14], // ASI
		  asi_tsa_wr_data	[10   ], // IBE
		  tstate_mod		[12:11], // CLE, TLE
		  tstate_mod		[10   ], // TCT
		  asi_tsa_wr_data	[2   ], // HPRIV
		  asi_tsa_wr_data	[5   ], // RED
		  tstate_mod		[7:4], // PEF, AM, PRIV, IE
		  asi_tsa_wr_data	[0   ], // TLZ
		  tstate_mod 		[2:0], // CWP
		  trap_type_mod		[8:0]}), // Trap Type
	.din6	({gl_mod		[1:0],
		  tstate_mod 		[29:0], // Everything but Trap Type
		  trap_type_mod		[8:0]}), // Trap Type
	.din7	({trl_tsa_gl		[1:0],
		  tsa_wr_data		[29:0], 
		  trl_tsa_trap_type	[8:0]}),
	.sel0	(asi_mbist_run			),
	.sel1	(asi_wr_tpc			),
	.sel2	(asi_wr_tnpc			),
	.sel3	(asi_wr_tstate			),
	.sel4	(asi_wr_tt			),
	.sel5	(asi_wr_htstate			),
	.sel6	(trl_save_tsa			),
	.en	(trl_tsd_tsa_wd_en		),
	.dout	({tsd_wr_gl		[1:0],
		  tsd_wr_data		[29:0],
		  tsd_wr_trap_type	[8:0]}),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_buff_macro__rep_1__stack_48c__width_30 ccr_cwp_asi_buf    (
	.din	(tsd_wr_data		[29:0]	),
	.dout	({tlu_ccr		[7:0],
		  tlu_asi		[7:0],
		  don_ret_pstate	[10:0],
		  tlu_cwp		[2:0]})
);

tlu_tsd_dp_msff_macro__stack_48c__width_9 shadow_tt_lat   (
	.scan_in(shadow_tt_lat_scanin),
	.scan_out(shadow_tt_lat_scanout),
	.din	(tsd_wr_trap_type	[8:0] ),
	.en	(trl_capture_ss			),
	.dout	(tsd_shadow_tt		[8:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);


////////////////////////////////////////////////////////////////////////////////
// Build write vector for Trap Stack Array
//   GL    CCR    ASI    (H)PSTATE   CWP   TT  PC nPC
// 41 40  39 32  31 24   19      8   4 0 
//
// GL, TT, PC, nPC concatenated at the array instantiation
// 
// Also implement HTSTATE
//   IBE  RED  HPRIV  TLZ
//    10   5     2     0

tlu_tsd_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_30 tsa_write_lat     (
	.din0	({exu_ccr0		[7:0], 
		  asi0			[7:0],
		  pstate0_reg		[10:0],
		  fls_cwp0		[2:0]}),
	.din1	({exu_ccr1		[7:0], 
		  asi1			[7:0],
		  pstate1_reg		[10:0],
		  fls_cwp1		[2:0]}),
	.din2	({exu_ccr2		[7:0], 
		  asi2			[7:0],
		  pstate2_reg		[10:0],
		  fls_cwp2		[2:0] }),
	.din3	({exu_ccr3		[7:0], 
		  asi3			[7:0],
		  pstate3_reg 		[10:0],
		  fls_cwp3		[2:0] }),
	.sel0	(trl_thread_sel		[0   ]	),
	.sel1	(trl_thread_sel		[1   ]	),
	.sel2	(trl_thread_sel		[2   ]	),
	.sel3	(trl_thread_sel		[3   ]	),
	.dout	(tsa_wr_data		[29:0]	)
);


////////////////////////////////////////////////////////////////////////////////
// Mux ASI reads
//

tlu_tsd_dp_msff_macro__left_11__stack_48c__width_26 rd_ctl_lat    (
	.scan_in(rd_ctl_lat_scanin),
	.scan_out(rd_ctl_lat_scanout),
	.en	(1'b1				),
	.din	({asi_rd_iqr		[2:0],
	          asi_wr_pstate		[3:0],
		  asi_rd_h_pstate_tba	[2:0],
		  asi_rd_asireg		[3:0],
		  asi_rd_tba_htba	       ,
		  asi_rd_pstate_hpstate	       ,
		  asi_wr_hpstate	[3:0],
		  asi_rd_tpc		       ,
		  asi_rd_tnpc		       ,
		  asi_rd_tstate		       ,
		  asi_rd_tt		       ,
		  asi_rd_htstate	       ,
		  asi_rd_iqr_reg	       }),
	.dout	({rd_iqr		[2:0],
	          wr_pstate		[3:0],
		  rd_h_pstate_tba	[2:0],
		  rd_asireg		[3:0],
		  rd_tba_htba		       ,
		  rd_pstate_hpstate	       ,
		  wr_hpstate		[3:0],
		  rd_tpc		       ,
		  rd_tnpc		       ,
		  rd_tstate		       ,
		  rd_tt			       ,
		  rd_htstate		       ,
		  rd_iqr_reg		       }),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_mux_macro__mux_aodec__ports_8__stack_48c__width_13 asi_php_mux     (
	.din0	(arch_pstate0	[12:0]	),
	.din1	(arch_pstate1	[12:0]	),
	.din2	(arch_pstate2	[12:0]	),
	.din3	(arch_pstate3	[12:0]	),
	.din4	(arch_hpstate0	[12:0]	),
	.din5	(arch_hpstate1	[12:0]	),
	.din6	(arch_hpstate2	[12:0]	),
	.din7	(arch_hpstate3	[12:0]	),
	.sel	(rd_h_pstate_tba[2:0]	),
	.dout	(asi_h_pstate	[12:0]	)
);

assign asi_h_pstate[47:13] =
       {35 {1'b0}};

tlu_tsd_dp_mux_macro__left_14__mux_aodec__ports_8__stack_48c__width_34 asi_pstate_tba_mux      (
	.din0	({tba0		[47:15],
		  1'b0		       }),
	.din1	({tba1		[47:15],
		  1'b0		       }),
	.din2	({tba2		[47:15],
		  1'b0		       }),
	.din3	({tba3		[47:15],
		  1'b0		       }),
	.din4	(htba0		[47:14]	),
	.din5	(htba1		[47:14]	),
	.din6	(htba2		[47:14]	),
	.din7	(htba3		[47:14]	),
	.sel	(rd_h_pstate_tba[2:0]	),
	.dout	(asi_h_tba	[47:14]	)
);

assign asi_h_tba[13:0] =
       {14 {1'b0}};

tlu_tsd_dp_mux_macro__dmux_8x__mux_aonpe__ports_6__stack_48c__width_48 asi_data_mux      (
	.din0	({40'h0000000000       ,
		  asi0		[7:0]}),
	.din1	({40'h0000000000       ,
		  asi1		[7:0]}),
	.din2	({40'h0000000000       ,
		  asi2		[7:0]}),
	.din3	({40'h0000000000       ,
		  asi3		[7:0]}),
	.din4	(asi_h_tba	[47:0]	),
 	.din5	(asi_h_pstate	[47:0]	),
	.sel0	(rd_asireg	[0   ]	),
	.sel1	(rd_asireg	[1   ]	),
	.sel2	(rd_asireg	[2   ]	),
	.sel3	(rd_asireg	[3   ]	),
	.sel4	(rd_tba_htba		),
	.sel5	(rd_pstate_hpstate	),
	.dout	(asi_data	[47:0]	)
);

tlu_tsd_dp_mux_macro__left_6__mux_aope__ports_4__stack_48c__width_12 iqr_mux      (
	.din0	(tnpc_mod		[35:24]	),	// Device or Nonres Tail
	.din1	(tnpc_mod		[47:36]	),	// Mondo or Res Tail
	.din2	(tpc_mod		[35:24]	),	// Device or Nonres Head
	.din3	(tpc_mod		[47:36]	),	// Mondo or Res Head
	.sel0	(rd_iqr			[0   ]	),
	.sel1	(rd_iqr			[1   ]	),
	.sel2	(rd_iqr			[2   ]	),
	.dout	(iqr_ungated		[17:6]	)
);

// Have to force this off since it's just ORed into downstream logic...
tlu_tsd_dp_and_macro__left_6__ports_2__stack_48c__width_12 iqr_and     (
	.din0	(iqr_ungated		[17:6]	),
	.din1	({12 {rd_iqr_reg}}		),
	.dout	(iqr_reg		[17:6]	)
);

assign pstate_mod[10:0] = 
	tstate_mod[13:3];

tlu_tsd_dp_mux_macro__mux_aonpe__ports_5__stack_48c__width_48 tsa_asi_data_mux     (
	.din0	({tpc_mod		[47:2],
		  2'b00			       }),
	.din1	({tnpc_mod		[47:2],
		  2'b00			       }),
	.din2	({6'h00			       ,
		  gl_mod		[1:0],
		  tstate_mod		[29:14],	// CCR, ASI
		  3'b000		       ,
		  pstate_mod		[7   ],	// TCT
		  2'b00			       ,
		  pstate_mod		[9:8],	// CLE, TLE
		  2'b00			       ,	// MM
		  1'b0			       ,
		  pstate_mod		[4:1],	// PEF, AM, PRIV, IE
		  1'b0			       ,
		  5'h00			       ,
		  tstate_mod		[2:0]}),	// CWP
	.din3	({39'h0000000000	       ,
		  trap_type_mod		[8:0]}),
	.din4	({37'h0000000000	       ,
		  pstate_mod		[10   ], 	// IBE
		  4'h0			       ,
		  pstate_mod		[5   ],	// RED
		  2'b00			       ,
		  pstate_mod		[6   ],	// HPRIV
		  1'b0			       ,
		  pstate_mod		[0   ]}),	// TLZ
	.sel0	(rd_tpc				),
	.sel1	(rd_tnpc			),
	.sel2	(rd_tstate			),
	.sel3	(rd_tt				),
	.sel4	(rd_htstate			),
	.dout	(tsa_asi_data		[47:0]	)
);

tlu_tsd_dp_nor_macro__ports_3__stack_48c__width_48 asi_data_nor    (
	.din0	(asi_data		[47:0]	),
	.din1	(tsa_asi_data		[47:0]	),
	.din2	({30'h000000000		       ,
		  iqr_reg		[17:6],
		  6'h00			       }),
	.dout	(asi_data_		[47:0]	)
);

tlu_tsd_dp_buff_macro__left_2__rep_1__stack_48c__width_46 asi_data_b_buf     (
	.din	(asi_data_		[47:2]	),
	.dout	(tsd_asi_data_		[47:2]	)
);

tlu_tsd_dp_inv_macro__stack_48c__width_2 asi_data_inv   (
	.din	(asi_data_		[1:0]	),
	.dout	(tsd_asi_data		[1:0]	)
);


////////////////////////////////////////////////////////////////////////////////
// MBIST muxing
//

tlu_tsd_dp_msff_macro__width_4 cmpsel_lat  (
	.scan_in(cmpsel_lat_scanin),
	.scan_out(cmpsel_lat_scanout),
	.en	(asi_mbist_run			),
	.din	(asi_mbist_cmpsel	[3:0]	),
	.dout	(cmpsel			[3:0]	),
  .clk(clk),
  .se(se),
  .siclk(siclk),
  .soclk(soclk),
  .pce_ov(pce_ov),
  .stop(stop)
);

tlu_tsd_dp_buff_macro__dbuff_32x__width_1 tst_mux_rep0   (
	.din	(tcu_muxtest			),
	.dout	(tcu_muxtest_rep0		)
);

tlu_tsd_dp_mux_macro__mux_pgpe__ports_5__stack_48c__width_32 mbist_mux     (
	.din4	({tel_ecc		[15:10],
		  tpc_oor_va_mod	       ,
		  tnpc_oor_va_mod	       ,
		  tel_ecc		[15:0],
		  tel_ecc		[7:6],
		  tnpc_nonseq_mod	       ,
		  gl_mod		[1:0],
		  tstate_mod		[29:27]}),
	.din3	({tstate_mod		[26:0],
		  trap_type_mod		[8:4]}),
	.din2	({trap_type_mod		[3:0],
		  tpc_mod		[47:20]}),
	.din1	({tpc_mod		[19:2],
		  tnpc_mod		[47:34]}),
	.din0	(tnpc_mod		[33:2]	),
	.sel3	(cmpsel			[3   ]	),
	.sel2	(cmpsel			[2   ]	),
	.sel1	(cmpsel			[1   ]	),
	.sel0	(cmpsel			[0   ]	),
	.muxtst	(tcu_muxtest_rep0		),
	.dout	(tsd_mbist_data		[31:0]	),
  .test(test)
);


// fixscan start:
assign pstate_lat_scanin         = scan_in                  ;
assign read_tpc_lat_scanin       = pstate_lat_scanout       ;
assign read_tnpc_lat_scanin      = read_tpc_lat_scanout     ;
assign read_tstate_lat_scanin    = read_tnpc_lat_scanout    ;
assign wr_tpc_lat_scanin         = read_tstate_lat_scanout  ;
assign shadow_tpc_lat_scanin     = wr_tpc_lat_scanout       ;
assign wr_tnpc_lat_scanin        = shadow_tpc_lat_scanout   ;
assign wr_tstate_lat_scanin      = wr_tnpc_lat_scanout      ;
assign shadow_tt_lat_scanin      = wr_tstate_lat_scanout    ;
assign rd_ctl_lat_scanin         = shadow_tt_lat_scanout    ;
assign cmpsel_lat_scanin         = rd_ctl_lat_scanout       ;
assign scan_out                  = cmpsel_lat_scanout       ;

assign asireg_lat_wmr_scanin     = wmr_scan_in              ;
assign htba3_lat_wmr_scanin      = asireg_lat_wmr_scanout   ;
assign htba2_lat_wmr_scanin      = htba3_lat_wmr_scanout    ;
assign htba1_lat_wmr_scanin      = htba2_lat_wmr_scanout    ;
assign htba0_lat_wmr_scanin      = htba1_lat_wmr_scanout    ;
assign tba3_lat_wmr_scanin       = htba0_lat_wmr_scanout    ;
assign tba2_lat_wmr_scanin       = tba3_lat_wmr_scanout     ;
assign tba1_lat_wmr_scanin       = tba2_lat_wmr_scanout     ;
assign tba0_lat_wmr_scanin       = tba1_lat_wmr_scanout     ;
assign wmr_scan_out              = tba0_lat_wmr_scanout     ;
// fixscan end:
endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__width_34 (
  din, 
  dout);
  input [33:0] din;
  output [33:0] dout;


buff #(34)  d0_0 (
.in(din[33:0]),
.out(dout[33:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


buff #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__mux_aope__ports_5__stack_48c__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire [31:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [30:0] so;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input [31:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [31:0] dout;


  output scan_out;


cl_dp1_penc5_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(32)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
.dout(muxout[31:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__mux_aonpe__ports_5__stack_48c__width_32 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [31:0] din0;
  input sel0;
  input [31:0] din1;
  input sel1;
  input [31:0] din2;
  input sel2;
  input [31:0] din3;
  input sel3;
  input [31:0] din4;
  input sel4;
  output [31:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(32)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
.dout(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__left_14__stack_48c__width_34 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [32:0] so;

  input [33:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [33:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(34)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[33:0]),
.si({scan_in,so[32:0]}),
.so({so[32:0],scan_out}),
.q(dout[33:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__left_15__stack_48c__width_33 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [31:0] so;

  input [32:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [32:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(33)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[32:0]),
.si({scan_in,so[31:0]}),
.so({so[31:0],scan_out}),
.q(dout[32:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__dmux_8x__left_14__mux_aodec__ports_8__stack_48c__width_34 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [33:0] din0;
  input [33:0] din1;
  input [33:0] din2;
  input [33:0] din3;
  input [33:0] din4;
  input [33:0] din5;
  input [33:0] din6;
  input [33:0] din7;
  input [2:0] sel;
  output [33:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(34)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[33:0]),
  .in1(din1[33:0]),
  .in2(din2[33:0]),
  .in3(din3[33:0]),
  .in4(din4[33:0]),
  .in5(din5[33:0]),
  .in6(din6[33:0]),
  .in7(din7[33:0]),
.dout(dout[33:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__mux_aonpe__ports_5__stack_48c__width_44 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire [43:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [42:0] so;

  input [43:0] din0;
  input sel0;
  input [43:0] din1;
  input sel1;
  input [43:0] din2;
  input sel2;
  input [43:0] din3;
  input sel3;
  input [43:0] din4;
  input sel4;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [43:0] dout;


  output scan_out;


cl_dp1_muxbuff5_8x  c1_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(44)  d1_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[43:0]),
  .in1(din1[43:0]),
  .in2(din2[43:0]),
  .in3(din3[43:0]),
  .in4(din4[43:0]),
.dout(muxout[43:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(44)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[43:0]),
.si({scan_in,so[42:0]}),
.so({so[42:0],scan_out}),
.q(dout[43:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__mux_aodec__ports_4__stack_48c__width_11 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [10:0] din0;
  input [10:0] din1;
  input [10:0] din2;
  input [10:0] din3;
  input [1:0] sel;
  output [10:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(11)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[10:0]),
  .in1(din1[10:0]),
  .in2(din2[10:0]),
  .in3(din3[10:0]),
.dout(dout[10:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__rep_1__stack_48c__width_48 (
  din, 
  dout);
  input [47:0] din;
  output [47:0] dout;


buff #(48)  d0_0 (
.in(din[47:0]),
.out(dout[47:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module tlu_tsd_dp_or_macro__ports_2__stack_4r__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


or2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__rep_1__stack_4r__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


buff #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__mux_aope__ports_5__stack_48c__width_44 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;

  input [43:0] din0;
  input [43:0] din1;
  input [43:0] din2;
  input [43:0] din3;
  input [43:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  output [43:0] dout;


cl_dp1_penc5_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4)
);

mux5s #(44)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[43:0]),
  .in1(din1[43:0]),
  .in2(din2[43:0]),
  .in3(din3[43:0]),
  .in4(din4[43:0]),
.dout(dout[43:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__mux_aonpe__ports_3__stack_48c__width_44 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [43:0] din0;
  input sel0;
  input [43:0] din1;
  input sel1;
  input [43:0] din2;
  input sel2;
  output [43:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(44)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[43:0]),
  .in1(din1[43:0]),
  .in2(din2[43:0]),
.dout(dout[43:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__left_1__minbuff_1__stack_48c__width_47 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [45:0] so;

  input [46:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [46:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(47)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[46:0]),
.si({scan_in,so[45:0]}),
.so({so[45:0],scan_out}),
.q(dout[46:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__left_1__rep_1__stack_48c__width_47 (
  din, 
  dout);
  input [46:0] din;
  output [46:0] dout;


buff #(47)  d0_0 (
.in(din[46:0]),
.out(dout[46:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__minbuff_1__stack_48c__width_48 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__left_7__minbuff_1__stack_48c__width_41 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [39:0] so;

  input [40:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [40:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(41)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[40:0]),
.si({scan_in,so[39:0]}),
.so({so[39:0],scan_out}),
.q(dout[40:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__left_6__stack_48c__width_42 (
  din, 
  dout);
  input [41:0] din;
  output [41:0] dout;


buff #(42)  d0_0 (
.in(din[41:0]),
.out(dout[41:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__left_1__mux_aope__ports_8__stack_48c__width_47 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;
wire [46:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [45:0] so;

  input [46:0] din0;
  input [46:0] din1;
  input [46:0] din2;
  input [46:0] din3;
  input [46:0] din4;
  input [46:0] din5;
  input [46:0] din6;
  input [46:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [46:0] dout;


  output scan_out;


cl_dp1_penc8_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(47)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[46:0]),
  .in1(din1[46:0]),
  .in2(din2[46:0]),
  .in3(din3[46:0]),
  .in4(din4[46:0]),
  .in5(din5[46:0]),
  .in6(din6[46:0]),
  .in7(din7[46:0]),
.dout(muxout[46:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(47)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[46:0]),
.si({scan_in,so[45:0]}),
.so({so[45:0],scan_out}),
.q(dout[46:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__left_2__minbuff_1__stack_48c__width_46 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [44:0] so;

  input [45:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [45:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(46)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[45:0]),
.si({scan_in,so[44:0]}),
.so({so[44:0],scan_out}),
.q(dout[45:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module tlu_tsd_dp_cmp_macro__width_12 (
  din0, 
  din1, 
  dout);
  input [11:0] din0;
  input [11:0] din1;
  output dout;


cmp #(12)  m0_0 (
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout)
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__mux_aope__ports_8__stack_48c__width_48 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;
wire [47:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [46:0] so;

  input [47:0] din0;
  input [47:0] din1;
  input [47:0] din2;
  input [47:0] din3;
  input [47:0] din4;
  input [47:0] din5;
  input [47:0] din6;
  input [47:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [47:0] dout;


  output scan_out;


cl_dp1_penc8_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(48)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
  .in5(din5[47:0]),
  .in6(din6[47:0]),
  .in7(din7[47:0]),
.dout(muxout[47:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(48)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[47:0]),
.si({scan_in,so[46:0]}),
.so({so[46:0],scan_out}),
.q(dout[47:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__mux_aope__ports_8__stack_48c__width_41 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  sel4, 
  sel5, 
  sel6, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;
wire [40:0] muxout;
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [39:0] so;

  input [40:0] din0;
  input [40:0] din1;
  input [40:0] din2;
  input [40:0] din3;
  input [40:0] din4;
  input [40:0] din5;
  input [40:0] din6;
  input [40:0] din7;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input sel4;
  input sel5;
  input sel6;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [40:0] dout;


  output scan_out;


cl_dp1_penc8_8x  c1_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .sel4(sel4),
 .sel5(sel5),
 .sel6(sel6),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(41)  d1_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[40:0]),
  .in1(din1[40:0]),
  .in2(din2[40:0]),
  .in3(din3[40:0]),
  .in4(din4[40:0]),
  .in5(din5[40:0]),
  .in6(din6[40:0]),
  .in7(din7[40:0]),
.dout(muxout[40:0])
);
cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(41)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(muxout[40:0]),
.si({scan_in,so[39:0]}),
.so({so[39:0],scan_out}),
.q(dout[40:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__rep_1__stack_48c__width_30 (
  din, 
  dout);
  input [29:0] din;
  output [29:0] dout;


buff #(30)  d0_0 (
.in(din[29:0]),
.out(dout[29:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__stack_48c__width_9 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [7:0] so;

  input [8:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [8:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.q(dout[8:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_30 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [29:0] din0;
  input sel0;
  input [29:0] din1;
  input sel1;
  input [29:0] din2;
  input sel2;
  input [29:0] din3;
  input sel3;
  output [29:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(30)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[29:0]),
  .in1(din1[29:0]),
  .in2(din2[29:0]),
  .in3(din3[29:0]),
.dout(dout[29:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__left_11__stack_48c__width_26 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [24:0] so;

  input [25:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [25:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(26)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[25:0]),
.si({scan_in,so[24:0]}),
.so({so[24:0],scan_out}),
.q(dout[25:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__mux_aodec__ports_8__stack_48c__width_13 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [12:0] din0;
  input [12:0] din1;
  input [12:0] din2;
  input [12:0] din3;
  input [12:0] din4;
  input [12:0] din5;
  input [12:0] din6;
  input [12:0] din7;
  input [2:0] sel;
  output [12:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(13)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[12:0]),
  .in1(din1[12:0]),
  .in2(din2[12:0]),
  .in3(din3[12:0]),
  .in4(din4[12:0]),
  .in5(din5[12:0]),
  .in6(din6[12:0]),
  .in7(din7[12:0]),
.dout(dout[12:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__left_14__mux_aodec__ports_8__stack_48c__width_34 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [33:0] din0;
  input [33:0] din1;
  input [33:0] din2;
  input [33:0] din3;
  input [33:0] din4;
  input [33:0] din5;
  input [33:0] din6;
  input [33:0] din7;
  input [2:0] sel;
  output [33:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(34)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[33:0]),
  .in1(din1[33:0]),
  .in2(din2[33:0]),
  .in3(din3[33:0]),
  .in4(din4[33:0]),
  .in5(din5[33:0]),
  .in6(din6[33:0]),
  .in7(din7[33:0]),
.dout(dout[33:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__dmux_8x__mux_aonpe__ports_6__stack_48c__width_48 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;

  input [47:0] din0;
  input sel0;
  input [47:0] din1;
  input sel1;
  input [47:0] din2;
  input sel2;
  input [47:0] din3;
  input sel3;
  input [47:0] din4;
  input sel4;
  input [47:0] din5;
  input sel5;
  output [47:0] dout;


cl_dp1_muxbuff6_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5)
);
mux6s #(48)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
  .in5(din5[47:0]),
.dout(dout[47:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__left_6__mux_aope__ports_4__stack_48c__width_12 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel0, 
  sel1, 
  sel2, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [11:0] din0;
  input [11:0] din1;
  input [11:0] din2;
  input [11:0] din3;
  input sel0;
  input sel1;
  input sel2;
  output [11:0] dout;


cl_dp1_penc4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(12)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[11:0]),
  .in1(din1[11:0]),
  .in2(din2[11:0]),
  .in3(din3[11:0]),
.dout(dout[11:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module tlu_tsd_dp_and_macro__left_6__ports_2__stack_48c__width_12 (
  din0, 
  din1, 
  dout);
  input [11:0] din0;
  input [11:0] din1;
  output [11:0] dout;


and2 #(12)  d0_0 (
.in0(din0[11:0]),
.in1(din1[11:0]),
.out(dout[11:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__mux_aonpe__ports_5__stack_48c__width_48 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;

  input [47:0] din0;
  input sel0;
  input [47:0] din1;
  input sel1;
  input [47:0] din2;
  input sel2;
  input [47:0] din3;
  input sel3;
  input [47:0] din4;
  input sel4;
  output [47:0] dout;


cl_dp1_muxbuff5_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4)
);
mux5s #(48)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .in0(din0[47:0]),
  .in1(din1[47:0]),
  .in2(din2[47:0]),
  .in3(din3[47:0]),
  .in4(din4[47:0]),
.dout(dout[47:0])
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module tlu_tsd_dp_nor_macro__ports_3__stack_48c__width_48 (
  din0, 
  din1, 
  din2, 
  dout);
  input [47:0] din0;
  input [47:0] din1;
  input [47:0] din2;
  output [47:0] dout;


nor3 #(48)  d0_0 (
.in0(din0[47:0]),
.in1(din1[47:0]),
.in2(din2[47:0]),
.out(dout[47:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__left_2__rep_1__stack_48c__width_46 (
  din, 
  dout);
  input [45:0] din;
  output [45:0] dout;


buff #(46)  d0_0 (
.in(din[45:0]),
.out(dout[45:0])
);


endmodule


//
//   invert macro
//
//


module tlu_tsd_dp_inv_macro__stack_48c__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


inv #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_msff_macro__width_4 (
  din, 
  clk, 
  en, 
  se, 
  scan_in, 
  siclk, 
  soclk, 
  pce_ov, 
  stop, 
  dout, 
  scan_out);
wire l1clk;
wire siclk_out;
wire soclk_out;
wire [2:0] so;

  input [3:0] din;


  input clk;
  input en;
  input se;
  input scan_in;
  input siclk;
  input soclk;
  input pce_ov;
  input stop;


  output [3:0] dout;


  output scan_out;


cl_dp1_l1hdr_8x c0_0 (
.l2clk(clk),
.pce(en),
.aclk(siclk),
.bclk(soclk),
.l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop),
  .siclk_out(siclk_out),
  .soclk_out(soclk_out)
);
dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(din[3:0]),
.si({scan_in,so[2:0]}),
.so({so[2:0],scan_out}),
.q(dout[3:0])
);


endmodule


//
//   buff macro
//
//


module tlu_tsd_dp_buff_macro__dbuff_32x__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module tlu_tsd_dp_mux_macro__mux_pgpe__ports_5__stack_48c__width_32 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  sel0, 
  sel1, 
  sel2, 
  sel3, 
  muxtst, 
  test, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;

  input [31:0] din0;
  input [31:0] din1;
  input [31:0] din2;
  input [31:0] din3;
  input [31:0] din4;
  input sel0;
  input sel1;
  input sel2;
  input sel3;
  input muxtst;
  input test;
  output [31:0] dout;


cl_dp1_penc5_8x  c0_0 (
 .sel0(sel0),
 .sel1(sel1),
 .sel2(sel2),
 .sel3(sel3),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
  .test(test)
);

mux5 #(32)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .in0(din0[31:0]),
  .in1(din1[31:0]),
  .in2(din2[31:0]),
  .in3(din3[31:0]),
  .in4(din4[31:0]),
.dout(dout[31:0]),
  .muxtst(muxtst)
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cl_dp1.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`define LIB
module cl_dp1_msffmin_30ps_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
             `ifdef FAST_FLUSH
 always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff


module cl_dp1_msffmin_30ps_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
             `ifdef FAST_FLUSH
 always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_msffmin_30ps_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE
	
             reg 	l1;
             `ifdef FAST_FLUSH
	 always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
		`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_msffmin_30ps_32x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
 always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_msffmin_30ps_1x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_bsac_cell_4x(q, so, d, l1clk, si, siclk, soclk, updateclk,
                           ac_mode, ac_test_signal);
   output     q;
   output       so;

   input         d, ac_test_signal;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   updateclk, ac_mode;

             reg       q;
             reg       so;
             wire      l1clk, siclk, soclk, updateclk;


             reg l1, qm;

             always @(l1clk or siclk or soclk or d or si)
              begin
    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
    if ( l1clk &&  siclk)           l1 <= si;    // Load master with
                                                 // scan or flush
    if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between
                                                   // data and scan
    if ( l1clk &&  !soclk)          so <= l1;     // Load slave with
                                                  // master data
    if ( l1clk &&  siclk && !soclk) so <= si;    // Flush
              end

                initial qm = 1'b0;

           always@(updateclk or l1)
                begin
                if(updateclk)  qm <=l1;
                end
always@(ac_mode or qm or ac_test_signal)
        begin
        if(ac_mode==0)  q=qm;
        else         q=qm ^ ac_test_signal;
        end
endmodule
module cl_dp1_blatch_4x ( latout, so, d, l1clk, si, siclk, soclk);

   output       latout;
   output       so;
   input         d;
   input         l1clk;
   input         si;
   input         siclk;
   input         soclk;
 

   wire  so;
   reg s, m;

   `ifdef SCAN_MODE

      always @(l1clk or siclk or soclk or d or si) begin

        if (!l1clk && !siclk)        m <=  d;    // Load master with data
        else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
        else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan

        if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
        else if (l1clk && siclk && !soclk)  s <= si;    // Flush
      end

   `else
      wire  si_unused = si;
`ifdef INITLATZERO


      initial m = 1'b0;
     `endif


      always @(l1clk or d or si or siclk) begin
        if(siclk==0 && l1clk==0) m =  d;
        else if(siclk && !l1clk)                m = 1'bx;
         if(siclk && l1clk) m = si;
        if(l1clk && !soclk) s = m;
      end

    `endif

      assign latout = m;
      assign so  =  s;


endmodule 
module cl_dp1_alatch_4x ( q, so, d, l1clk, si, siclk, soclk, se );


   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   se;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	

             reg l1;

             always @(l1clk or siclk or soclk or d or si or se)
              begin

                    if (siclk)           l1 <= si;    // Load master with scan or flush

		if(se && !soclk && l1clk && siclk) q <= si;
                else    if ( se && !soclk && l1clk)  q <= l1;    
                    else if ( !soclk && l1clk)  q <= d;
              end


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif


         assign so = q;

endmodule // dff
module cl_dp1_msffmin_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff


module cl_dp1_msffmin_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_msffmin_32x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_msffmin_1x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_rep_32x (
in,
out
);
input in;
output out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

module cl_dp1_rep_m6_32x (
in,
out
);
input in;
output out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

module cl_dp1_add12_8x (
cin,
in0,
in1,
out,
cout
);
input 	       cin;
input 	[11:0] in0;
input 	[11:0] in1;
output 	[11:0] out;
output 	       cout;

`ifdef LIB
  assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin});
`endif

endmodule
module cl_dp1_add136_8x (
  din0,
  din1,
  din2,
  sel_din2,
  sum,
  fya_sticky_dp,
  fya_sticky_sp,
  fya_xicc_z);
wire [101:0] p;
wire [100:0] k;
wire [101:0] z;


  input  [135:0]  din0;
  input  [132:0]  din1;
  input  [135:0]  din2;
  input    [3:0]  sel_din2;

  output [135:0]  sum;
  output          fya_sticky_dp;
  output          fya_sticky_sp;
  output [1:0]    fya_xicc_z;

`ifdef LIB

         assign sum[135:0]  = {       din0[135:0]}      +
                               {3'b000,din1[132:0]}     +
                               ({{{40{sel_din2[3]}} & din2[135:96]},
                                 {{32{sel_din2[2]}} & din2[95:64] },
                                 {{32{sel_din2[1]}} & din2[63:32] },
                                 {{32{sel_din2[0]}} & din2[31:0]  }});


        //            127 126   125    ...   74      73  72         0
        //            --- ---   ---------------     ---  ------------
        // Float DP    x   x  .     52 fraction       G  -> Sticky ->

        //            127 126   125    ...   103    102  101        0
        //            --- ---   ---------------     ---  ------------
        // Float SP    x   x  .     23 fraction       G  -> Sticky ->


        assign p[101:0]      =  din0[101:0] ^  {din1[101:4],{4{1'b0}}};
        assign k[100:0]      = ~din0[100:0] & ~{din1[100:4],{4{1'b0}}};

        assign z[101:1]      =  p[101:1] ^  k[100:0];
        assign z[0]          = ~p[0];

        assign fya_sticky_sp = ~(& z[101:0]);
        assign fya_sticky_dp = ~(& z[72:0]);

        assign fya_xicc_z[1] = & z[63:0];
        assign fya_xicc_z[0] = & z[31:0];

`endif

endmodule
module cl_dp1_add16_8x (
cin,
in0,
in1,
out,
cout
);
input 	       cin;
input 	[15:0] in0;
input 	[15:0] in1;
output 	[15:0] out;
output 	       cout;

`ifdef LIB
  assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin});
`endif

endmodule
module cl_dp1_add32_8x (
cin,
in0,
in1,
out,
cout
);
input 	       cin;
input 	[31:0] in0;
input 	[31:0] in1;
output 	[31:0] out;
output 	       cout;

`ifdef LIB
  assign {cout, out[31:0]} = ({1'b0, in0[31:0]} + {1'b0, in1[31:0]} + {{32{1'b0}}, cin});
`endif

endmodule
module cl_dp1_add4_8x (
cin,
in0,
in1,
out,
cout
);
input 	       cin;
input 	[3:0]  in0;
input 	[3:0]  in1;
output 	[3:0]  out;
output 	       cout;

`ifdef LIB
  assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin});
`endif

endmodule
module cl_dp1_add64_8x (
cin,
in0,
in1,
out,
cout
);
input 	       cin;
input 	[63:0] in0;
input 	[63:0] in1;
output 	[63:0] out;
output 	       cout;

`ifdef LIB
  assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin});
`endif

endmodule
module cl_dp1_add8_8x (
cin,
in0,
in1,
out,
cout
);
input 	       cin;
input 	[7:0]  in0;
input 	[7:0]  in1;
output 	[7:0]  out;
output 	       cout;

`ifdef LIB
  assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin});
`endif

endmodule

module cl_dp1_aomux2_1x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_dp1_aomux2_2x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_dp1_aomux2_4x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_dp1_aomux2_6x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_dp1_aomux2_8x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule

module cl_dp1_aomux3_1x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_dp1_aomux3_2x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_dp1_aomux3_4x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_dp1_aomux3_6x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_dp1_aomux3_8x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule

module cl_dp1_aomux4_1x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_dp1_aomux4_2x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_dp1_aomux4_4x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_dp1_aomux4_6x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_dp1_aomux4_8x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule

module cl_dp1_aomux5_1x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_dp1_aomux5_2x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_dp1_aomux5_4x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_dp1_aomux5_6x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_dp1_aomux5_8x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule

module cl_dp1_aomux6_1x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_dp1_aomux6_2x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_dp1_aomux6_4x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_dp1_aomux6_6x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_dp1_aomux6_8x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule

module cl_dp1_aomux7_1x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_dp1_aomux7_2x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_dp1_aomux7_4x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_dp1_aomux7_6x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_dp1_aomux7_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule

module cl_dp1_aomux8_1x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_dp1_aomux8_2x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_dp1_aomux8_4x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_dp1_aomux8_6x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_dp1_aomux8_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_dp1_boothenc_4x (
  din,  
  xr_mode,
  dout,
  pout,
  hout
);

  input [2:0] din;

  input xr_mode;

  output [4:0] dout;

  output pout;

  output hout;
`ifdef LIB
 assign dout[0]	= (~xr_mode & ~din[2] & ~din[1] &  din[0]) |	// +1
		  (~xr_mode & ~din[2] &  din[1] & ~din[0]) |
		  ( xr_mode & ~din[2] &  din[1]          );

 assign dout[1]	= (~xr_mode & ~din[2] &  din[1] &  din[0]) |	// +2
		  ( xr_mode &  din[2] & ~din[1]          );
 	     			
 assign dout[2]	= (~xr_mode &  din[2] & ~din[1] & ~din[0]);	// -2

 assign dout[3]	= (~xr_mode &  din[2] & ~din[1] &  din[0]) |	// -1
		  (~xr_mode &  din[2] &  din[1] & ~din[0]);

 assign dout[4]	= ( xr_mode &  din[2] &  din[1]          );	// +3


 assign pout	= (~xr_mode & ~din[2] ) |	// P
		  (~xr_mode &  din[1] &  din[0]);

 assign hout	= (~xr_mode &  din[2] & ~din[1]          ) |	// H
		  (~xr_mode &  din[2] & ~din[0]);

`endif


endmodule

module cl_dp1_boothenc_8x (
  din,  
  xr_mode,
  dout,
  pout,
  hout
);

  input [2:0] din;

  input xr_mode;

  output [4:0] dout;

  output pout;

  output hout;
`ifdef LIB
 assign dout[0]	= (~xr_mode & ~din[2] & ~din[1] &  din[0]) |	// +1
		  (~xr_mode & ~din[2] &  din[1] & ~din[0]) |
		  ( xr_mode & ~din[2] &  din[1]          );

 assign dout[1]	= (~xr_mode & ~din[2] &  din[1] &  din[0]) |	// +2
		  ( xr_mode &  din[2] & ~din[1]          );
 	     			
 assign dout[2]	= (~xr_mode &  din[2] & ~din[1] & ~din[0]);	// -2

 assign dout[3]	= (~xr_mode &  din[2] & ~din[1] &  din[0]) |	// -1
		  (~xr_mode &  din[2] &  din[1] & ~din[0]);

 assign dout[4]	= ( xr_mode &  din[2] &  din[1]          );	// +3


 assign pout	= (~xr_mode & ~din[2] ) |	// P
		  (~xr_mode &  din[1] &  din[0]);

 assign hout	= (~xr_mode &  din[2] & ~din[1]          ) |	// H
		  (~xr_mode &  din[2] & ~din[0]);

`endif


endmodule

module cl_dp1_cmpr12_8x (
in0,
in1,
out
);
input	[11:0] in0;
input	[11:0] in1;
output	out;

`ifdef LIB
assign out = (in0[11:0] == in1[11:0]);
`endif

endmodule
module cl_dp1_cmpr16_8x (
in0,
in1,
out
);
input	[15:0] in0;
input	[15:0] in1;
output	out;

`ifdef LIB
assign out = (in0[15:0] == in1[15:0]);
`endif

endmodule
module cl_dp1_cmpr32_8x (
in0,
in1,
out
);
input	[31:0] in0;
input	[31:0] in1;
output	out;

`ifdef LIB
assign out = (in0[31:0] == in1[31:0]);
`endif

endmodule
module cl_dp1_cmpr4_8x (
in0,
in1,
out
);
input	[3:0] in0;
input	[3:0] in1;
output	out;

`ifdef LIB
assign out = (in0[3:0] == in1[3:0]);
`endif

endmodule
module cl_dp1_cmpr64_8x (
in0,
in1,
out
);
input	[63:0] in0;
input	[63:0] in1;
output	out;

`ifdef LIB
assign out = (in0[63:0] == in1[63:0]);
`endif

endmodule
module cl_dp1_cmpr8_8x (
in0,
in1,
out
);
input	[7:0] in0;
input	[7:0] in1;
output	out;

`ifdef LIB
assign out = (in0[7:0] == in1[7:0]);
`endif

endmodule
module cl_dp1_incr12_8x (
cin,
in0,
out,
cout
);
input		cin;
input [11:0] 	in0;
output [11:0]	out;
output 		cout;

`ifdef LIB
  assign {cout, out[11:0]} = {1'b0, in0[11:0]} + {12'b0, cin};
`endif

endmodule
module cl_dp1_incr16_8x (
cin,
in0,
out,
cout
);
input		cin;
input [15:0] 	in0;
output [15:0]	out;
output 		cout;

`ifdef LIB
  assign {cout, out[15:0]} = {1'b0, in0[15:0]} + {16'b0, cin};
`endif

endmodule
module cl_dp1_incr32_8x (
cin,
in0,
out,
cout
);
input		cin;
input [31:0] 	in0;
output [31:0]	out;
output 		cout;

`ifdef LIB
  assign {cout, out[31:0]} = {1'b0, in0[31:0]} + {32'b0, cin};
`endif

endmodule
module cl_dp1_incr4_8x (
cin,
in0,
out,
cout
);
input		cin;
input [3:0] 	in0;
output [3:0]	out;
output 		cout;

`ifdef LIB
  assign {cout, out[3:0]} = {1'b0, in0[3:0]} + {4'b0, cin};
`endif

endmodule
module cl_dp1_incr48_8x (
cin,
in0,
out,
cout
);
input		cin;
input [47:0] 	in0;
output [47:0]	out;
output 		cout;

`ifdef LIB
  assign {cout, out[47:0]} = {1'b0, in0[47:0]} + {48'b0, cin};
`endif

endmodule
module cl_dp1_incr64_8x (
cin,
in0,
out,
cout
);
input		cin;
input [63:0] 	in0;
output [63:0]	out;
output 		cout;

`ifdef LIB
  assign {cout, out[63:0]} = {1'b0, in0[63:0]} + {64'b0, cin};
`endif

endmodule
module cl_dp1_incr8_8x (
cin,
in0,
out,
cout
);
input		cin;
input [7:0] 	in0;
output [7:0]	out;
output 		cout;

`ifdef LIB
  assign {cout, out[7:0]} = {1'b0, in0[7:0]} + {8'b0, cin};
`endif

endmodule // cl_dp1_incr8_8x
module  cl_dp1_l1hdr_12x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
wire            l1en = (~stop & ( pce | pce_ov ));
assign       l1clk = (l2clk & l1en) | se;
assign siclk_out = aclk;
assign soclk_out = bclk;
`else
 `ifdef LIB
reg             l1en;
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

 assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority  

assign siclk_out = aclk;
assign soclk_out = bclk;

 `endif //  `ifdef LIB
`endif // !`ifdef FORMAL_TOOL


endmodule

module  cl_dp1_l1hdr_16x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif


   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule
module  cl_dp1_l1hdr_24x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;
 
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   
   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule
module  cl_dp1_l1hdr_32x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;


  `ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule
module  cl_dp1_l1hdr_4x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;
 

  `ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule

`ifdef FPGA
`else
module  cl_dp1_l1hdr_8x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;
 

   `ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif
endmodule

`endif // `ifdef FPGA

module  cl_dp1_l1hdr_48x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;


  `ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule
module  cl_dp1_l1hdr_64x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;


  `ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule
module  cl_dp1_l1hdr_nostop_48x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en = pce | pce_ov ;
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= ((pce | pce_ov));
       end
`else


   always @ (negedge l2clk )
        begin
           l1en <= (( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule
module cl_dp1_inv_diode_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
assign out = ~in;
`endif

endmodule
module  cl_dp1_l1hdr_nostop_72x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en =  pce | pce_ov ;
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= ((pce | pce_ov));
       end
`else


   always @ (negedge l2clk )
        begin
           l1en <= (( pce | pce_ov ));
        end
`endif
   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule
module  cl_dp1_l1hdr_nostop_64x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
    wire l1en =  pce | pce_ov ;
    assign       l1clk = (l2clk & l1en) | se;
    assign siclk_out = aclk;
    assign soclk_out = bclk;
   `else
`ifdef LIB
   reg  l1en;

`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= ((pce | pce_ov));
       end
`else

   always @ (negedge l2clk )
        begin
           l1en <= (( pce | pce_ov ));
        end
`endif
   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

`endif
`endif

endmodule
module cl_dp1_msff_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff

module cl_dp1_msff_1x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff

module cl_dp1_msff_32x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff

module cl_dp1_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff

module cl_dp1_msff_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff

module cl_dp1_msffi_16x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg	q;
             wire     so;
             wire      l1clk, siclk, soclk;

      `ifdef SCAN_MODE
		reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else            

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff
module cl_dp1_msffi_1x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg	q;
             wire     so;
             wire      l1clk, siclk, soclk;

      `ifdef SCAN_MODE
		reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else            

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff
module cl_dp1_msffi_32x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg	q;
             wire     so;
             wire      l1clk, siclk, soclk;

     `ifdef SCAN_MODE
		reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else            

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff
module cl_dp1_msffi_4x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg	q;
             wire     so;
             wire      l1clk, siclk, soclk;

      `ifdef SCAN_MODE
		reg l1;
	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else            

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff
module cl_dp1_msffi_8x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg	q;
             wire     so;
             wire      l1clk, siclk, soclk;

       `ifdef SCAN_MODE
		reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else            

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff
module cl_dp1_msffiz_32x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
           
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q_l <=  1'b0;  //pseudo flush reset
                  end else begin
                    q_l <=  ~d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= ~d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q_l <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q_l <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q_l <=  ~d;
                else                  q_l <= 1'bx;
               end
        `endif

         assign so = q_l;

endmodule // dff
module cl_dp1_msffiz_16x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
          
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q_l <=  1'b0;  //pseudo flush reset
                  end else begin
                    q_l <=  ~d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= ~d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q_l <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q_l <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q_l <=  ~d;
                else                  q_l <= 1'bx;
               end
        `endif

         assign so = q_l;

endmodule // dff
module cl_dp1_mux2_12x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_dp1_mux2_16x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_dp1_mux2_24x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_dp1_mux2_2x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_dp1_mux2_32x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_dp1_mux2_4x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_dp1_mux2_6x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_dp1_mux2_8x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule


module cl_dp1_mux3_12x(
in0,
in1,
in2,
sel0,
sel1,
sel2,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              sel0;
   input              sel1;
   input              sel2;
   input              muxtst;
   output             out;

`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2}
`endif

 wire [3:0] sel= {muxtst,sel2,sel1,sel0};

 assign out = (sel[2:0] == 3'b001)   ?    in0:
              (sel[2:0] == 3'b010)   ?    in1:
              (sel[2:0] == 3'b100)   ?    in2:
              (sel[3:0] == 4'b0000)  ?   1'b1:
                                         1'bx;
`endif
endmodule

module cl_dp1_mux3_16x(
in0,
in1,
in2,
sel0,
sel1,
sel2,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              sel0;
   input              sel1;
   input              sel2;
   input              muxtst;
   output             out;

`ifdef LIB

`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2}
`endif

 wire [3:0] sel = {muxtst,sel2,sel1,sel0};

 assign out = (sel[2:0] == 3'b001)   ?    in0:
              (sel[2:0] == 3'b010)   ?    in1:
              (sel[2:0] == 3'b100)   ?    in2:
              (sel[3:0] == 4'b0000)  ?   1'b1:
                                         1'bx;
`endif
endmodule

module cl_dp1_mux3_24x(
in0,
in1,
in2,
sel0,
sel1,
sel2,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              sel0;
   input              sel1;
   input              sel2;
   input              muxtst;
   output             out;

`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2}
`endif

 wire [3:0] sel = {muxtst,sel2,sel1,sel0};

 assign out = (sel[2:0] == 3'b001)   ?    in0:
              (sel[2:0] == 3'b010)   ?    in1:
              (sel[2:0] == 3'b100)   ?    in2:
              (sel[3:0] == 4'b0000)  ?   1'b1:
                                         1'bx;
`endif
endmodule

module cl_dp1_mux3_2x(
in0,
in1,
in2,
sel0,
sel1,
sel2,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              sel0;
   input              sel1;
   input              sel2;
   input              muxtst;
   output             out;

`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2}
`endif

 wire [3:0] sel= {muxtst,sel2,sel1,sel0};

 assign out = (sel[2:0] == 3'b001)   ?    in0:
              (sel[2:0] == 3'b010)   ?    in1:
              (sel[2:0] == 3'b100)   ?    in2:
              (sel[3:0] == 4'b0000)  ?   1'b1:
                                         1'bx;
`endif
endmodule

module cl_dp1_mux3_32x(
in0,
in1,
in2,
sel0,
sel1,
sel2,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              sel0;
   input              sel1;
   input              sel2;
   input              muxtst;
   output             out;

`ifdef LIB


 wire [3:0] sel= {muxtst,sel2,sel1,sel0};

 assign out = (sel[2:0] == 3'b001)   ?    in0:
              (sel[2:0] == 3'b010)   ?    in1:
              (sel[2:0] == 3'b100)   ?    in2:
              (sel[3:0] == 4'b0000)  ?   1'b1:
                                         1'bx;
`endif
endmodule

module cl_dp1_mux3_4x(
in0,
in1,
in2,
sel0,
sel1,
sel2,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              sel0;
   input              sel1;
   input              sel2;
   input              muxtst;
   output             out;

`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2}
`endif

 wire [3:0] sel= {muxtst,sel2,sel1,sel0};

 assign out = (sel[2:0] == 3'b001)   ?    in0:
              (sel[2:0] == 3'b010)   ?    in1:
              (sel[2:0] == 3'b100)   ?    in2:
              (sel[3:0] == 4'b0000)  ?   1'b1:
                                         1'bx;
`endif
endmodule

module cl_dp1_mux3_6x(
in0,
in1,
in2,
sel0,
sel1,
sel2,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              sel0;
   input              sel1;
   input              sel2;
   input              muxtst;
   output             out;

`ifdef LIB

`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2}
`endif

 wire [3:0] sel= {muxtst,sel2,sel1,sel0};

 assign out = (sel[2:0] == 3'b001)   ?    in0:
              (sel[2:0] == 3'b010)   ?    in1:
              (sel[2:0] == 3'b100)   ?    in2:
              (sel[3:0] == 4'b0000)  ?   1'b1:
                                         1'bx;
`endif
endmodule

module cl_dp1_mux3_8x(
in0,
in1,
in2,
sel0,
sel1,
sel2,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              sel0;
   input              sel1;
   input              sel2;
   input              muxtst;
   output             out;

`ifdef LIB

`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2}
`endif

 wire [3:0] sel = {muxtst,sel2,sel1,sel0};

 assign out = (sel[2:0] == 3'b001)   ?    in0:
              (sel[2:0] == 3'b010)   ?    in1:
              (sel[2:0] == 3'b100)   ?    in2:
              (sel[3:0] == 4'b0000)  ?   1'b1:
                                         1'bx;
`endif
endmodule


module cl_dp1_mux4_12x(
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              muxtst;
   output             out;


 `ifdef LIB

`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3}
`endif 
  
 wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0};

 assign out = (sel[3:0] == 4'b0001)   ?    in0:
              (sel[3:0] == 4'b0010)   ?    in1:
              (sel[3:0] == 4'b0100)   ?    in2:
              (sel[3:0] == 4'b1000)   ?    in3:
              (sel[4:0] == 5'b00000)  ?   1'b1:
                                          1'bx;
`endif
endmodule

module cl_dp1_mux4_16x(
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              muxtst;
   output             out;


 `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3}
`endif
 
  
 wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0};

 assign out = (sel[3:0] == 4'b0001)   ?    in0:
              (sel[3:0] == 4'b0010)   ?    in1:
              (sel[3:0] == 4'b0100)   ?    in2:
              (sel[3:0] == 4'b1000)   ?    in3:
              (sel[4:0] == 5'b00000)  ?   1'b1:
                                          1'bx;
`endif
endmodule

module cl_dp1_mux4_24x(
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              muxtst;
   output             out;


 `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3}
`endif
 
  
 wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0};

 assign out = (sel[3:0] == 4'b0001)   ?    in0:
              (sel[3:0] == 4'b0010)   ?    in1:
              (sel[3:0] == 4'b0100)   ?    in2:
              (sel[3:0] == 4'b1000)   ?    in3:
              (sel[4:0] == 5'b00000)  ?   1'b1:
                                          1'bx;
`endif
endmodule

module cl_dp1_mux4_2x(
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              muxtst;
   output             out;


 `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3}
`endif
 
  
 wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0};

 assign out = (sel[3:0] == 4'b0001)   ?    in0:
              (sel[3:0] == 4'b0010)   ?    in1:
              (sel[3:0] == 4'b0100)   ?    in2:
              (sel[3:0] == 4'b1000)   ?    in3:
              (sel[4:0] == 5'b00000)  ?   1'b1:
                                          1'bx;
`endif
endmodule

module cl_dp1_mux4_32x(
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              muxtst;
   output             out;


 `ifdef LIB
 `ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3}
`endif
 
  
 wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0};

 assign out = (sel[3:0] == 4'b0001)   ?    in0:
              (sel[3:0] == 4'b0010)   ?    in1:
              (sel[3:0] == 4'b0100)   ?    in2:
              (sel[3:0] == 4'b1000)   ?    in3:
              (sel[4:0] == 5'b00000)  ?   1'b1:
                                          1'bx;
`endif
endmodule

module cl_dp1_mux4_4x(
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              muxtst;
   output             out;


 `ifdef LIB
 `ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3}
`endif
 
  
 wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0};

 assign out = (sel[3:0] == 4'b0001)   ?    in0:
              (sel[3:0] == 4'b0010)   ?    in1:
              (sel[3:0] == 4'b0100)   ?    in2:
              (sel[3:0] == 4'b1000)   ?    in3:
              (sel[4:0] == 5'b00000)  ?   1'b1:
                                          1'bx;
`endif
endmodule

module cl_dp1_mux4_6x(
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              muxtst;
   output             out;


 `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3}
`endif
 
  
 wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0};

 assign out = (sel[3:0] == 4'b0001)   ?    in0:
              (sel[3:0] == 4'b0010)   ?    in1:
              (sel[3:0] == 4'b0100)   ?    in2:
              (sel[3:0] == 4'b1000)   ?    in3:
              (sel[4:0] == 5'b00000)  ?   1'b1:
                                          1'bx;
`endif
endmodule

module cl_dp1_mux4_8x(
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
muxtst,
out
);

 
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              muxtst;
   output             out;


 `ifdef LIB

`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3}
`endif 
  
 wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0};

 assign out = (sel[3:0] == 4'b0001)   ?    in0:
              (sel[3:0] == 4'b0010)   ?    in1:
              (sel[3:0] == 4'b0100)   ?    in2:
              (sel[3:0] == 4'b1000)   ?    in3:
              (sel[4:0] == 5'b00000)  ?   1'b1:
                                          1'bx;
`endif
endmodule


module cl_dp1_mux5_12x(
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
muxtst,
out
);

  
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              muxtst;
   output             out;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4}
`endif
 
 wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[4:0] == 5'b00001)   ?    in0:
              (sel[4:0] == 5'b00010)   ?    in1:
              (sel[4:0] == 5'b00100)   ?    in2:
              (sel[4:0] == 5'b01000)   ?    in3:
              (sel[4:0] == 5'b10000)   ?    in4:
              (sel[5:0] == 6'b000000)  ?   1'b1:
                                           1'bx;
`endif
endmodule

module cl_dp1_mux5_16x(
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
muxtst,
out
);

  
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              muxtst;
   output             out;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4}
`endif
 
 wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[4:0] == 5'b00001)   ?    in0:
              (sel[4:0] == 5'b00010)   ?    in1:
              (sel[4:0] == 5'b00100)   ?    in2:
              (sel[4:0] == 5'b01000)   ?    in3:
              (sel[4:0] == 5'b10000)   ?    in4:
              (sel[5:0] == 6'b000000)  ?   1'b1:
                                           1'bx;
`endif
endmodule

module cl_dp1_mux5_24x(
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
muxtst,
out
);

  
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              muxtst;
   output             out;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4}
`endif
 
 wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[4:0] == 5'b00001)   ?    in0:
              (sel[4:0] == 5'b00010)   ?    in1:
              (sel[4:0] == 5'b00100)   ?    in2:
              (sel[4:0] == 5'b01000)   ?    in3:
              (sel[4:0] == 5'b10000)   ?    in4:
              (sel[5:0] == 6'b000000)  ?   1'b1:
                                           1'bx;
`endif
endmodule

module cl_dp1_mux5_2x(
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
muxtst,
out
);

  
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              muxtst;
   output             out;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4}
`endif
 
 wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[4:0] == 5'b00001)   ?    in0:
              (sel[4:0] == 5'b00010)   ?    in1:
              (sel[4:0] == 5'b00100)   ?    in2:
              (sel[4:0] == 5'b01000)   ?    in3:
              (sel[4:0] == 5'b10000)   ?    in4:
              (sel[5:0] == 6'b000000)  ?   1'b1:
                                           1'bx;
`endif
endmodule

module cl_dp1_mux5_32x(
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
muxtst,
out
);

  
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              muxtst;
   output             out;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4}
`endif
 
 wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[4:0] == 5'b00001)   ?    in0:
              (sel[4:0] == 5'b00010)   ?    in1:
              (sel[4:0] == 5'b00100)   ?    in2:
              (sel[4:0] == 5'b01000)   ?    in3:
              (sel[4:0] == 5'b10000)   ?    in4:
              (sel[5:0] == 6'b000000)  ?   1'b1:
                                           1'bx;
`endif
endmodule

module cl_dp1_mux5_4x(
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
muxtst,
out
);

  
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              muxtst;
   output             out;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4}
`endif
 
 wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[4:0] == 5'b00001)   ?    in0:
              (sel[4:0] == 5'b00010)   ?    in1:
              (sel[4:0] == 5'b00100)   ?    in2:
              (sel[4:0] == 5'b01000)   ?    in3:
              (sel[4:0] == 5'b10000)   ?    in4:
              (sel[5:0] == 6'b000000)  ?   1'b1:
                                           1'bx;
`endif
endmodule

module cl_dp1_mux5_6x(
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
muxtst,
out
);

  
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              muxtst;
   output             out;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4}
`endif
 
 wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[4:0] == 5'b00001)   ?    in0:
              (sel[4:0] == 5'b00010)   ?    in1:
              (sel[4:0] == 5'b00100)   ?    in2:
              (sel[4:0] == 5'b01000)   ?    in3:
              (sel[4:0] == 5'b10000)   ?    in4:
              (sel[5:0] == 6'b000000)  ?   1'b1:
                                           1'bx;
`endif
endmodule

module cl_dp1_mux5_8x(
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
muxtst,
out
);

  
   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              muxtst;
   output             out;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4}
`endif
 
 wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[4:0] == 5'b00001)   ?    in0:
              (sel[4:0] == 5'b00010)   ?    in1:
              (sel[4:0] == 5'b00100)   ?    in2:
              (sel[4:0] == 5'b01000)   ?    in3:
              (sel[4:0] == 5'b10000)   ?    in4:
              (sel[5:0] == 6'b000000)  ?   1'b1:
                                           1'bx;
`endif
endmodule

module cl_dp1_mux6_12x(
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              muxtst;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5}
`endif
 wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[5:0] == 6'b000001)   ?    in0:
              (sel[5:0] == 6'b000010)   ?    in1:
              (sel[5:0] == 6'b000100)   ?    in2:
              (sel[5:0] == 6'b001000)   ?    in3:
              (sel[5:0] == 6'b010000)   ?    in4:
              (sel[5:0] == 6'b100000)   ?    in5:
              (sel[6:0] == 7'b0000000)  ?   1'b1:
                                            1'bx;
`endif
endmodule

module cl_dp1_mux6_16x(
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              muxtst;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5}
`endif
 wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[5:0] == 6'b000001)   ?    in0:
              (sel[5:0] == 6'b000010)   ?    in1:
              (sel[5:0] == 6'b000100)   ?    in2:
              (sel[5:0] == 6'b001000)   ?    in3:
              (sel[5:0] == 6'b010000)   ?    in4:
              (sel[5:0] == 6'b100000)   ?    in5:
              (sel[6:0] == 7'b0000000)  ?   1'b1:
                                            1'bx;
`endif
endmodule

module cl_dp1_mux6_24x(
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              muxtst;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5}
`endif
 wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[5:0] == 6'b000001)   ?    in0:
              (sel[5:0] == 6'b000010)   ?    in1:
              (sel[5:0] == 6'b000100)   ?    in2:
              (sel[5:0] == 6'b001000)   ?    in3:
              (sel[5:0] == 6'b010000)   ?    in4:
              (sel[5:0] == 6'b100000)   ?    in5:
              (sel[6:0] == 7'b0000000)  ?   1'b1:
                                            1'bx;
`endif
endmodule

module cl_dp1_mux6_2x(
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              muxtst;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5}
`endif
 wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[5:0] == 6'b000001)   ?    in0:
              (sel[5:0] == 6'b000010)   ?    in1:
              (sel[5:0] == 6'b000100)   ?    in2:
              (sel[5:0] == 6'b001000)   ?    in3:
              (sel[5:0] == 6'b010000)   ?    in4:
              (sel[5:0] == 6'b100000)   ?    in5:
              (sel[6:0] == 7'b0000000)  ?   1'b1:
                                            1'bx;
`endif
endmodule

module cl_dp1_mux6_32x(
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              muxtst;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5}
`endif
 wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[5:0] == 6'b000001)   ?    in0:
              (sel[5:0] == 6'b000010)   ?    in1:
              (sel[5:0] == 6'b000100)   ?    in2:
              (sel[5:0] == 6'b001000)   ?    in3:
              (sel[5:0] == 6'b010000)   ?    in4:
              (sel[5:0] == 6'b100000)   ?    in5:
              (sel[6:0] == 7'b0000000)  ?   1'b1:
                                            1'bx;
`endif
endmodule

module cl_dp1_mux6_4x(
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              muxtst;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5}
`endif
 wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[5:0] == 6'b000001)   ?    in0:
              (sel[5:0] == 6'b000010)   ?    in1:
              (sel[5:0] == 6'b000100)   ?    in2:
              (sel[5:0] == 6'b001000)   ?    in3:
              (sel[5:0] == 6'b010000)   ?    in4:
              (sel[5:0] == 6'b100000)   ?    in5:
              (sel[6:0] == 7'b0000000)  ?   1'b1:
                                            1'bx;
`endif
endmodule

module cl_dp1_mux6_6x(
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              muxtst;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5}
`endif
 wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[5:0] == 6'b000001)   ?    in0:
              (sel[5:0] == 6'b000010)   ?    in1:
              (sel[5:0] == 6'b000100)   ?    in2:
              (sel[5:0] == 6'b001000)   ?    in3:
              (sel[5:0] == 6'b010000)   ?    in4:
              (sel[5:0] == 6'b100000)   ?    in5:
              (sel[6:0] == 7'b0000000)  ?   1'b1:
                                            1'bx;
`endif
endmodule

module cl_dp1_mux6_8x(
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              muxtst;
`ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5}
`endif

 wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[5:0] == 6'b000001)   ?    in0:
              (sel[5:0] == 6'b000010)   ?    in1:
              (sel[5:0] == 6'b000100)   ?    in2:
              (sel[5:0] == 6'b001000)   ?    in3:
              (sel[5:0] == 6'b010000)   ?    in4:
              (sel[5:0] == 6'b100000)   ?    in5:
              (sel[6:0] == 7'b0000000)  ?   1'b1:
                                            1'bx;
`endif
endmodule


module cl_dp1_mux7_12x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              muxtst;
  
   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6}
`endif   

 wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[6:0] == 7'b0000001)   ?    in0:
              (sel[6:0] == 7'b0000010)   ?    in1:
              (sel[6:0] == 7'b0000100)   ?    in2:
              (sel[6:0] == 7'b0001000)   ?    in3:
              (sel[6:0] == 7'b0010000)   ?    in4:
              (sel[6:0] == 7'b0100000)   ?    in5:
              (sel[6:0] == 7'b1000000)   ?    in6:
              (sel[7:0] == 8'b00000000)  ?   1'b1:
                                             1'bx;
`endif
endmodule

module cl_dp1_mux7_16x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              muxtst;
  
   `ifdef LIB
   
   `ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6}
`endif

 wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[6:0] == 7'b0000001)   ?    in0:
              (sel[6:0] == 7'b0000010)   ?    in1:
              (sel[6:0] == 7'b0000100)   ?    in2:
              (sel[6:0] == 7'b0001000)   ?    in3:
              (sel[6:0] == 7'b0010000)   ?    in4:
              (sel[6:0] == 7'b0100000)   ?    in5:
              (sel[6:0] == 7'b1000000)   ?    in6:
              (sel[7:0] == 8'b00000000)  ?   1'b1:
                                             1'bx;
`endif
endmodule

module cl_dp1_mux7_24x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              muxtst;
  
   `ifdef LIB
   `ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6}
`endif

 wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[6:0] == 7'b0000001)   ?    in0:
              (sel[6:0] == 7'b0000010)   ?    in1:
              (sel[6:0] == 7'b0000100)   ?    in2:
              (sel[6:0] == 7'b0001000)   ?    in3:
              (sel[6:0] == 7'b0010000)   ?    in4:
              (sel[6:0] == 7'b0100000)   ?    in5:
              (sel[6:0] == 7'b1000000)   ?    in6:
              (sel[7:0] == 8'b00000000)  ?   1'b1:
                                             1'bx;
`endif
endmodule

module cl_dp1_mux7_2x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              muxtst;
  
   `ifdef LIB
   `ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6}
`endif

 wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[6:0] == 7'b0000001)   ?    in0:
              (sel[6:0] == 7'b0000010)   ?    in1:
              (sel[6:0] == 7'b0000100)   ?    in2:
              (sel[6:0] == 7'b0001000)   ?    in3:
              (sel[6:0] == 7'b0010000)   ?    in4:
              (sel[6:0] == 7'b0100000)   ?    in5:
              (sel[6:0] == 7'b1000000)   ?    in6:
              (sel[7:0] == 8'b00000000)  ?   1'b1:
                                             1'bx;
`endif
endmodule

module cl_dp1_mux7_32x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              muxtst;
  
   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6}
`endif   

 wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[6:0] == 7'b0000001)   ?    in0:
              (sel[6:0] == 7'b0000010)   ?    in1:
              (sel[6:0] == 7'b0000100)   ?    in2:
              (sel[6:0] == 7'b0001000)   ?    in3:
              (sel[6:0] == 7'b0010000)   ?    in4:
              (sel[6:0] == 7'b0100000)   ?    in5:
              (sel[6:0] == 7'b1000000)   ?    in6:
              (sel[7:0] == 8'b00000000)  ?   1'b1:
                                             1'bx;
`endif
endmodule

module cl_dp1_mux7_4x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              muxtst;
  
   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6}
`endif   

 wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[6:0] == 7'b0000001)   ?    in0:
              (sel[6:0] == 7'b0000010)   ?    in1:
              (sel[6:0] == 7'b0000100)   ?    in2:
              (sel[6:0] == 7'b0001000)   ?    in3:
              (sel[6:0] == 7'b0010000)   ?    in4:
              (sel[6:0] == 7'b0100000)   ?    in5:
              (sel[6:0] == 7'b1000000)   ?    in6:
              (sel[7:0] == 8'b00000000)  ?   1'b1:
                                             1'bx;
`endif
endmodule

module cl_dp1_mux7_6x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              muxtst;
  
   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6}
`endif   

 wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[6:0] == 7'b0000001)   ?    in0:
              (sel[6:0] == 7'b0000010)   ?    in1:
              (sel[6:0] == 7'b0000100)   ?    in2:
              (sel[6:0] == 7'b0001000)   ?    in3:
              (sel[6:0] == 7'b0010000)   ?    in4:
              (sel[6:0] == 7'b0100000)   ?    in5:
              (sel[6:0] == 7'b1000000)   ?    in6:
              (sel[7:0] == 8'b00000000)  ?   1'b1:
                                             1'bx;
`endif
endmodule

module cl_dp1_mux7_8x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
muxtst,
out
);


   output             out;

   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              muxtst;
  
   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6}
`endif   

 wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[6:0] == 7'b0000001)   ?    in0:
              (sel[6:0] == 7'b0000010)   ?    in1:
              (sel[6:0] == 7'b0000100)   ?    in2:
              (sel[6:0] == 7'b0001000)   ?    in3:
              (sel[6:0] == 7'b0010000)   ?    in4:
              (sel[6:0] == 7'b0100000)   ?    in5:
              (sel[6:0] == 7'b1000000)   ?    in6:
              (sel[7:0] == 8'b00000000)  ?   1'b1:
                                             1'bx;
`endif
endmodule


module cl_dp1_mux8_12x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
muxtst,
out
);


   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              in7;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              sel7;
   input              muxtst;
   output             out;

   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7}
`endif   
 wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[7:0] == 8'b00000001)   ?    in0:
              (sel[7:0] == 8'b00000010)   ?    in1:
              (sel[7:0] == 8'b00000100)   ?    in2:
              (sel[7:0] == 8'b00001000)   ?    in3:
              (sel[7:0] == 8'b00010000)   ?    in4:
              (sel[7:0] == 8'b00100000)   ?    in5:
              (sel[7:0] == 8'b01000000)   ?    in6:
              (sel[7:0] == 8'b10000000)   ?    in7:
              (sel[8:0] == 9'b000000000)  ?   1'b1:
                                              1'bx;
`endif
endmodule

module cl_dp1_mux8_16x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
muxtst,
out
);


   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              in7;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              sel7;
   input              muxtst;
   output             out;

   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7}
`endif   
 wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[7:0] == 8'b00000001)   ?    in0:
              (sel[7:0] == 8'b00000010)   ?    in1:
              (sel[7:0] == 8'b00000100)   ?    in2:
              (sel[7:0] == 8'b00001000)   ?    in3:
              (sel[7:0] == 8'b00010000)   ?    in4:
              (sel[7:0] == 8'b00100000)   ?    in5:
              (sel[7:0] == 8'b01000000)   ?    in6:
              (sel[7:0] == 8'b10000000)   ?    in7:
              (sel[8:0] == 9'b000000000)  ?   1'b1:
                                              1'bx;
`endif
endmodule

module cl_dp1_mux8_24x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
muxtst,
out
);


   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              in7;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              sel7;
   input              muxtst;
   output             out;

   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7}
`endif   
 wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[7:0] == 8'b00000001)   ?    in0:
              (sel[7:0] == 8'b00000010)   ?    in1:
              (sel[7:0] == 8'b00000100)   ?    in2:
              (sel[7:0] == 8'b00001000)   ?    in3:
              (sel[7:0] == 8'b00010000)   ?    in4:
              (sel[7:0] == 8'b00100000)   ?    in5:
              (sel[7:0] == 8'b01000000)   ?    in6:
              (sel[7:0] == 8'b10000000)   ?    in7:
              (sel[8:0] == 9'b000000000)  ?   1'b1:
                                              1'bx;
`endif
endmodule

module cl_dp1_mux8_2x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
muxtst,
out
);


   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              in7;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              sel7;
   input              muxtst;
   output             out;

   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7}
`endif   
 wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[7:0] == 8'b00000001)   ?    in0:
              (sel[7:0] == 8'b00000010)   ?    in1:
              (sel[7:0] == 8'b00000100)   ?    in2:
              (sel[7:0] == 8'b00001000)   ?    in3:
              (sel[7:0] == 8'b00010000)   ?    in4:
              (sel[7:0] == 8'b00100000)   ?    in5:
              (sel[7:0] == 8'b01000000)   ?    in6:
              (sel[7:0] == 8'b10000000)   ?    in7:
              (sel[8:0] == 9'b000000000)  ?   1'b1:
                                              1'bx;
`endif
endmodule

module cl_dp1_mux8_32x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
muxtst,
out
);


   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              in7;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              sel7;
   input              muxtst;
   output             out;

   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7}
`endif   
 wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[7:0] == 8'b00000001)   ?    in0:
              (sel[7:0] == 8'b00000010)   ?    in1:
              (sel[7:0] == 8'b00000100)   ?    in2:
              (sel[7:0] == 8'b00001000)   ?    in3:
              (sel[7:0] == 8'b00010000)   ?    in4:
              (sel[7:0] == 8'b00100000)   ?    in5:
              (sel[7:0] == 8'b01000000)   ?    in6:
              (sel[7:0] == 8'b10000000)   ?    in7:
              (sel[8:0] == 9'b000000000)  ?   1'b1:
                                              1'bx;
`endif
endmodule

module cl_dp1_mux8_4x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
muxtst,
out
);


   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              in7;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              sel7;
   input              muxtst;
   output             out;

   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7}
`endif   
 wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[7:0] == 8'b00000001)   ?    in0:
              (sel[7:0] == 8'b00000010)   ?    in1:
              (sel[7:0] == 8'b00000100)   ?    in2:
              (sel[7:0] == 8'b00001000)   ?    in3:
              (sel[7:0] == 8'b00010000)   ?    in4:
              (sel[7:0] == 8'b00100000)   ?    in5:
              (sel[7:0] == 8'b01000000)   ?    in6:
              (sel[7:0] == 8'b10000000)   ?    in7:
              (sel[8:0] == 9'b000000000)  ?   1'b1:
                                              1'bx;
`endif
endmodule

module cl_dp1_mux8_6x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
muxtst,
out
);


   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              in7;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              sel7;
   input              muxtst;
   output             out;

   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7}
`endif   
 wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[7:0] == 8'b00000001)   ?    in0:
              (sel[7:0] == 8'b00000010)   ?    in1:
              (sel[7:0] == 8'b00000100)   ?    in2:
              (sel[7:0] == 8'b00001000)   ?    in3:
              (sel[7:0] == 8'b00010000)   ?    in4:
              (sel[7:0] == 8'b00100000)   ?    in5:
              (sel[7:0] == 8'b01000000)   ?    in6:
              (sel[7:0] == 8'b10000000)   ?    in7:
              (sel[8:0] == 9'b000000000)  ?   1'b1:
                                              1'bx;
`endif
endmodule

module cl_dp1_mux8_8x(
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
muxtst,
out
);


   input              in0;
   input              in1;
   input              in2;
   input              in3;
   input              in4;
   input              in5;
   input              in6;
   input              in7;
   input              sel0;
   input              sel1;
   input              sel2;
   input              sel3;
   input              sel4;
   input              sel5;
   input              sel6;
   input              sel7;
   input              muxtst;
   output             out;

   `ifdef LIB
`ifdef MUXOHTEST
//0in one_hot -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7}
`endif   
 wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0};

 assign out = (sel[7:0] == 8'b00000001)   ?    in0:
              (sel[7:0] == 8'b00000010)   ?    in1:
              (sel[7:0] == 8'b00000100)   ?    in2:
              (sel[7:0] == 8'b00001000)   ?    in3:
              (sel[7:0] == 8'b00010000)   ?    in4:
              (sel[7:0] == 8'b00100000)   ?    in5:
              (sel[7:0] == 8'b01000000)   ?    in6:
              (sel[7:0] == 8'b10000000)   ?    in7:
              (sel[8:0] == 9'b000000000)  ?   1'b1:
                                              1'bx;
`endif
endmodule


module cl_dp1_muxbuff2_16x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = {in1,in0};
buf (out1, in1);
buf (out0, in0);

`endif

endmodule
module cl_dp1_muxbuff2_32x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = {in1,in0};
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff2_48x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = {in1,in0};
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff2_64x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = {in1,in0};
buf (out1, in1);
buf (out0, in0);
`endif

endmodule

`ifdef FPGA
`else

module cl_dp1_muxbuff2_8x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = {in1,in0};
buf (out1, in1);
buf (out0, in0);
`endif

endmodule

`endif // `ifdef FPGA
module cl_dp1_muxbuff3_16x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = {in2,in1,in0};
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff3_32x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = {in2,in1,in0};
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff3_48x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = {in2,in1,in0};
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff3_64x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = {in2,in1,in0};
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule

module cl_dp1_muxbuff3_8x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = {in2,in1,in0};
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff4_16x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = {in3,in2,in1,in0};
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff4_32x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = {in3,in2,in1,in0};
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff4_48x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = {in3,in2,in1,in0};
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff4_64x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = {in3,in2,in1,in0};
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule

module cl_dp1_muxbuff4_8x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = {in3,in2,in1,in0};
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff5_16x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0};
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff5_32x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0};
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff5_48x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0};
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff5_64x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0};
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule

module cl_dp1_muxbuff5_8x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0};
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff6_16x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0};
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff6_32x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0};
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff6_48x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0};
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff6_64x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0};
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule

module cl_dp1_muxbuff6_8x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0};
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff7_16x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0};
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff7_32x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0};
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff7_48x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0};
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff7_64x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0};
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule

module cl_dp1_muxbuff7_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0};
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff8_16x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0};
buf (out7, in7);
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff8_32x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0};
buf (out7, in7);
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff8_48x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0};
buf (out7, in7);
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxbuff8_64x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0};
buf (out7, in7);
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule

module cl_dp1_muxbuff8_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0};
buf (out7, in7);
buf (out6, in6);
buf (out5, in5);
buf (out4, in4);
buf (out3, in3);
buf (out2, in2);
buf (out1, in1);
buf (out0, in0);
`endif

endmodule
module cl_dp1_muxinv2_16x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = ~{in1,in0};
not (out0, in0);
not (out1, in1);
`endif

endmodule
module cl_dp1_muxinv2_32x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = ~{in1,in0};
not (out0, in0);
not (out1, in1);
`endif

endmodule
module cl_dp1_muxinv2_48x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = ~{in1,in0};
not (out0, in0);
not (out1, in1);
`endif

endmodule
module cl_dp1_muxinv2_64x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = ~{in1,in0};
not (out0, in0);
not (out1, in1);
`endif

endmodule

module cl_dp1_muxinv2_8x (
in0,
in1,
out0,
out1
);
input	in0;
input	in1;
output	out0;
output	out1;

`ifdef LIB
//assign {out1,out0} = ~{in1,in0};
not (out0, in0);
not (out1, in1);
`endif

endmodule
module cl_dp1_muxinv3_16x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = ~{in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
`endif

endmodule
module cl_dp1_muxinv3_32x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = ~{in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
`endif

endmodule
module cl_dp1_muxinv3_48x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = ~{in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
`endif

endmodule
module cl_dp1_muxinv3_64x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = ~{in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
`endif

endmodule

module cl_dp1_muxinv3_8x (
in0,
in1,
in2,
out0,
out1,
out2
);
input	in0;
input	in1;
input	in2;
output	out0;
output	out1;
output	out2;

`ifdef LIB
//assign {out2,out1,out0} = ~{in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
`endif

endmodule
module cl_dp1_muxinv4_16x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
`endif

endmodule
module cl_dp1_muxinv4_32x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
`endif

endmodule
module cl_dp1_muxinv4_48x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
`endif

endmodule
module cl_dp1_muxinv4_64x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
`endif

endmodule

module cl_dp1_muxinv4_8x (
in0,
in1,
in2,
in3,
out0,
out1,
out2,
out3
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out0;
output	out1;
output	out2;
output	out3;

`ifdef LIB
//assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
`endif

endmodule
module cl_dp1_muxinv5_16x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
`endif

endmodule
module cl_dp1_muxinv5_32x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
`endif

endmodule
module cl_dp1_muxinv5_48x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
`endif

endmodule
module cl_dp1_muxinv5_64x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
`endif

endmodule

module cl_dp1_muxinv5_8x (
in0,
in1,
in2,
in3,
in4,
out0,
out1,
out2,
out3,
out4
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;

`ifdef LIB
//assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
`endif

endmodule
module cl_dp1_muxinv6_16x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
`endif

endmodule
module cl_dp1_muxinv6_32x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
`endif

endmodule
module cl_dp1_muxinv6_48x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
`endif

endmodule
module cl_dp1_muxinv6_64x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
`endif

endmodule

module cl_dp1_muxinv6_8x (
in0,
in1,
in2,
in3,
in4,
in5,
out0,
out1,
out2,
out3,
out4,
out5
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;

`ifdef LIB
//assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
`endif

endmodule
module cl_dp1_muxinv7_16x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
`endif

endmodule
module cl_dp1_muxinv7_32x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
`endif

endmodule
module cl_dp1_muxinv7_48x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
`endif

endmodule
module cl_dp1_muxinv7_64x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
`endif

endmodule

module cl_dp1_muxinv7_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
out0,
out1,
out2,
out3,
out4,
out5,
out6
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;

`ifdef LIB
//assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
`endif

endmodule
module cl_dp1_muxinv8_16x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
not (out7, in7);
`endif

endmodule
module cl_dp1_muxinv8_32x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
not (out7, in7);
`endif

endmodule
module cl_dp1_muxinv8_48x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
not (out7, in7);
`endif

endmodule
module cl_dp1_muxinv8_64x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
not (out7, in7);
`endif

endmodule

module cl_dp1_muxinv8_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
out0,
out1,
out2,
out3,
out4,
out5,
out6,
out7
);
input	in0;
input	in1;
input	in2;
input	in3;
input	in4;
input	in5;
input	in6;
input	in7;
output	out0;
output	out1;
output	out2;
output	out3;
output	out4;
output	out5;
output	out6;
output	out7;

`ifdef LIB
//assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0};
not (out0, in0);
not (out1, in1);
not (out2, in2);
not (out3, in3);
not (out4, in4);
not (out5, in5);
not (out6, in6);
not (out7, in7);
`endif

endmodule
module cl_dp1_pdec4_16x (
sel0,
sel1,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
  assign psel0 = ~sel1 & ~sel0;
  assign psel1 = ~sel1 &  sel0;
  assign psel2 =  sel1 & ~sel0;
  assign psel3 =  sel1 &  sel0 & test;
`endif
endmodule
module cl_dp1_pdec4_32x (
sel0,
sel1,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
  assign psel0 = ~sel1 & ~sel0;
  assign psel1 = ~sel1 &  sel0;
  assign psel2 =  sel1 & ~sel0;
  assign psel3 =  sel1 &  sel0 & test;
`endif
endmodule
module cl_dp1_pdec4_48x (
sel0,
sel1,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
  assign psel0 = ~sel1 & ~sel0;
  assign psel1 = ~sel1 &  sel0;
  assign psel2 =  sel1 & ~sel0;
  assign psel3 =  sel1 &  sel0 & test;
`endif
endmodule
module cl_dp1_pdec4_64x (
sel0,
sel1,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
  assign psel0 = ~sel1 & ~sel0;
  assign psel1 = ~sel1 &  sel0;
  assign psel2 =  sel1 & ~sel0;
  assign psel3 =  sel1 &  sel0 & test;
`endif
endmodule

`ifdef FPGA
`else

module cl_dp1_pdec4_8x (
sel0,
sel1,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
  assign psel0 = ~sel1 & ~sel0;
  assign psel1 = ~sel1 &  sel0;
  assign psel2 =  sel1 & ~sel0;
  assign psel3 =  sel1 &  sel0 & test;
`endif
endmodule

`endif // `ifdef FPGA


module cl_dp1_pdec8_16x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = ~sel2 & ~sel1 & ~sel0 & test;
assign psel1 = ~sel2 & ~sel1 &  sel0;
assign psel2 = ~sel2 &  sel1 & ~sel0;
assign psel3 = ~sel2 &  sel1 &  sel0;
assign psel4 =  sel2 & ~sel1 & ~sel0;
assign psel5 =  sel2 & ~sel1 &  sel0;
assign psel6 =  sel2 &  sel1 & ~sel0;
assign psel7 =  sel2 &  sel1 &  sel0;
`endif

endmodule
module cl_dp1_pdec8_32x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = ~sel2 & ~sel1 & ~sel0 & test;
assign psel1 = ~sel2 & ~sel1 &  sel0;
assign psel2 = ~sel2 &  sel1 & ~sel0;
assign psel3 = ~sel2 &  sel1 &  sel0;
assign psel4 =  sel2 & ~sel1 & ~sel0;
assign psel5 =  sel2 & ~sel1 &  sel0;
assign psel6 =  sel2 &  sel1 & ~sel0;
assign psel7 =  sel2 &  sel1 &  sel0;
`endif

endmodule
module cl_dp1_pdec8_48x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = ~sel2 & ~sel1 & ~sel0 & test;
assign psel1 = ~sel2 & ~sel1 &  sel0;
assign psel2 = ~sel2 &  sel1 & ~sel0;
assign psel3 = ~sel2 &  sel1 &  sel0;
assign psel4 =  sel2 & ~sel1 & ~sel0;
assign psel5 =  sel2 & ~sel1 &  sel0;
assign psel6 =  sel2 &  sel1 & ~sel0;
assign psel7 =  sel2 &  sel1 &  sel0;
`endif

endmodule
module cl_dp1_pdec8_64x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = ~sel2 & ~sel1 & ~sel0 & test;
assign psel1 = ~sel2 & ~sel1 &  sel0;
assign psel2 = ~sel2 &  sel1 & ~sel0;
assign psel3 = ~sel2 &  sel1 &  sel0;
assign psel4 =  sel2 & ~sel1 & ~sel0;
assign psel5 =  sel2 & ~sel1 &  sel0;
assign psel6 =  sel2 &  sel1 & ~sel0;
assign psel7 =  sel2 &  sel1 &  sel0;
`endif

endmodule

`ifdef FPGA
`else

module cl_dp1_pdec8_8x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = ~sel2 & ~sel1 & ~sel0 & test;
assign psel1 = ~sel2 & ~sel1 &  sel0;
assign psel2 = ~sel2 &  sel1 & ~sel0;
assign psel3 = ~sel2 &  sel1 &  sel0;
assign psel4 =  sel2 & ~sel1 & ~sel0;
assign psel5 =  sel2 & ~sel1 &  sel0;
assign psel6 =  sel2 &  sel1 & ~sel0;
assign psel7 =  sel2 &  sel1 &  sel0;
`endif

endmodule

`endif // `ifdef FPGA

module cl_dp1_penc2_16x (
sel0,
psel0,
psel1
);
input	sel0;
output	psel0;
output	psel1;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0;
`endif

endmodule
module cl_dp1_penc2_32x (
sel0,
psel0,
psel1
);
input	sel0;
output	psel0;
output	psel1;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0;
`endif

endmodule
module cl_dp1_penc2_48x (
sel0,
psel0,
psel1
);
input	sel0;
output	psel0;
output	psel1;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0;
`endif

endmodule
module cl_dp1_penc2_64x (
sel0,
psel0,
psel1
);
input	sel0;
output	psel0;
output	psel1;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0;
`endif

endmodule

`ifdef FPGA
`else
module cl_dp1_penc2_8x (
sel0,
psel0,
psel1
);
input	sel0;
output	psel0;
output	psel1;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0;
`endif

endmodule

`endif // ifdef FPGA


module cl_dp1_penc3_16x (
sel0,
sel1,
test,
psel0,
psel1,
psel2
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & test;
`endif

endmodule
module cl_dp1_penc3_32x (
sel0,
sel1,
test,
psel0,
psel1,
psel2
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & test;
`endif

endmodule
module cl_dp1_penc3_48x (
sel0,
sel1,
test,
psel0,
psel1,
psel2
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & test;
`endif

endmodule
module cl_dp1_penc3_64x (
sel0,
sel1,
test,
psel0,
psel1,
psel2
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & test;
`endif

endmodule
module cl_dp1_penc3_8x (
sel0,
sel1,
test,
psel0,
psel1,
psel2
);
input	sel0;
input	sel1;
input   test;
output	psel0;
output	psel1;
output	psel2;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & test;
`endif

endmodule
module cl_dp1_penc4_16x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2;
`endif

endmodule
module cl_dp1_penc4_32x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2;
`endif

endmodule
module cl_dp1_penc4_48x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2;
`endif

endmodule
module cl_dp1_penc4_64x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2;
`endif

endmodule
module cl_dp1_penc4_8x (
sel0,
sel1,
sel2,
test,
psel0,
psel1,
psel2,
psel3
);
input	sel0;
input	sel1;
input	sel2;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2;
`endif

endmodule
module cl_dp1_penc5_16x (
sel0,
sel1,
sel2,
sel3,
test,
psel0,
psel1,
psel2,
psel3,
psel4
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;

`ifdef LIB
assign psel0 = sel0 & test;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3;
`endif

endmodule
module cl_dp1_penc5_32x (
sel0,
sel1,
sel2,
sel3,
test,
psel0,
psel1,
psel2,
psel3,
psel4
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;

`ifdef LIB
assign psel0 = sel0 & test;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3;
`endif

endmodule
module cl_dp1_penc5_48x (
sel0,
sel1,
sel2,
sel3,
test,
psel0,
psel1,
psel2,
psel3,
psel4
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;

`ifdef LIB
assign psel0 = sel0 & test;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3;
`endif

endmodule
module cl_dp1_penc5_64x (
sel0,
sel1,
sel2,
sel3,
test,
psel0,
psel1,
psel2,
psel3,
psel4
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;

`ifdef LIB
assign psel0 = sel0 & test;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3;
`endif

endmodule
module cl_dp1_penc5_8x (
sel0,
sel1,
sel2,
sel3,
test,
psel0,
psel1,
psel2,
psel3,
psel4
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;

`ifdef LIB
assign psel0 = sel0 & test;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3;
`endif

endmodule
module cl_dp1_penc6_16x (
sel0,
sel1,
sel2,
sel3,
sel4,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2 & test;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4;
`endif

endmodule
module cl_dp1_penc6_32x (
sel0,
sel1,
sel2,
sel3,
sel4,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2 & test;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4;
`endif

endmodule
module cl_dp1_penc6_48x (
sel0,
sel1,
sel2,
sel3,
sel4,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2 & test;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4;
`endif

endmodule
module cl_dp1_penc6_64x (
sel0,
sel1,
sel2,
sel3,
sel4,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2 & test;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4;
`endif

endmodule
module cl_dp1_penc6_8x (
sel0,
sel1,
sel2,
sel3,
sel4,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1;
assign psel2 = ~sel0 & ~sel1 & sel2 & test;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4;
`endif

endmodule
module cl_dp1_penc7_16x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5;
`endif

endmodule
module cl_dp1_penc7_32x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5;
`endif

endmodule
module cl_dp1_penc7_48x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5;
`endif

endmodule
module cl_dp1_penc7_64x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5;
`endif

endmodule
module cl_dp1_penc7_8x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5;
`endif

endmodule
module cl_dp1_penc8_16x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input	sel6;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6;
assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6;
`endif

endmodule
module cl_dp1_penc8_32x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input	sel6;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6;
assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6;
`endif

endmodule
module cl_dp1_penc8_48x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input	sel6;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6;
assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6;
`endif

endmodule
module cl_dp1_penc8_64x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input	sel6;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6;
assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6;
`endif

endmodule
module cl_dp1_penc8_8x (
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
test,
psel0,
psel1,
psel2,
psel3,
psel4,
psel5,
psel6,
psel7
);
input	sel0;
input	sel1;
input	sel2;
input	sel3;
input	sel4;
input	sel5;
input	sel6;
input   test;
output	psel0;
output	psel1;
output	psel2;
output	psel3;
output	psel4;
output	psel5;
output	psel6;
output	psel7;

`ifdef LIB
assign psel0 = sel0;
assign psel1 = ~sel0 & sel1 & test;
assign psel2 = ~sel0 & ~sel1 & sel2;
assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3;
assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4;
assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5;
assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6;
assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6;
`endif

endmodule
module cl_dp1_prty16_8x (
in,
out
);
input	[15:0] in;
output	out;


`ifdef LIB
assign out = ^in[15:0];
`endif

endmodule
module cl_dp1_prty32_8x (
in,
out
);
input	[31:0] in;
output	out;

`ifdef LIB
assign out = ^in[31:0];
`endif

endmodule
module cl_dp1_prty4_8x (
in,
out
);
input	[3:0] in;
output	out;

`ifdef LIB
assign out = ^in[3:0];
`endif

endmodule
module cl_dp1_prty8_8x (
in,
out
);
input	[7:0] in;
output	out;

`ifdef LIB
assign out = ^in[7:0];
`endif

endmodule

module cl_dp1_zero12_12x (
in,
out
);

input [11:0] in;
output out;

`ifdef LIB

assign out = ( in[11:0] == 12'b0);

`endif


endmodule
module cl_dp1_zero16_12x (
in,
out
);

input [15:0] in;
output out;

`ifdef LIB

assign out = ( in[15:0] == 16'b0);

`endif


endmodule

module cl_dp1_zero32_12x (
in,
out
);

input [31:0] in;
output out;

`ifdef LIB

assign out = ( in[31:0] == 32'b0);

`endif


endmodule

module cl_dp1_zero4_12x (
in,
out
);

input [3:0] in;
output out;

`ifdef LIB

assign out = ( in[3:0] == 4'b0);

`endif


endmodule
module cl_dp1_zero64_12x (
in,
out
);

input [63:0] in;
output out;

`ifdef LIB

assign out = ( in[63:0] == 64'b0);

`endif


endmodule

module cl_dp1_zero8_12x (
in,
out
);

input [7:0] in;
output out;

`ifdef LIB

assign out = ( in[7:0] == 8'b0);

`endif


endmodule


module cl_dp1_zdt64_8x(
din0,
din1,
cin,
zdt_z64_,
zdt_z32_
);

  input  [63:0]  din0;
  input  [63:0]  din1;
  input          cin;

  output         zdt_z64_;
  output         zdt_z32_;
  
  wire [63:0] p;
  wire [62:0] k;
  wire [63:0] z;
  wire zero_detect32;
  wire zero_detect64;

`ifdef LIB


assign p[63:0]       =  din0[63:0] ^  din1[63:0];
assign k[62:0]       = ~din0[62:0] & ~din1[62:0];

assign z[63:1]       =  p[63:1] ^  k[62:0];
assign z[0]          =  p[0]    ^ ~cin;

assign zero_detect32 = & z[31:0];
assign zero_detect64 = & z[63:0];

assign zdt_z32_      = ~zero_detect32;
assign zdt_z64_      = ~zero_detect64;

`endif


endmodule
module cl_dp1_ccxhdr (
l2clk,
pce0,
pce1,
pce_ov,
stop,
siclk_in,
soclk_in,
siclk_out,
soclk_out,
l1clk0,
l1clk1,
se,
si,
so,    
l1clk,                     
grant_a,
grant_x,
qsel0,
qsel0_buf,
shift,
shift_buf                         
);

input l2clk;
input pce0;
input pce1;
input pce_ov;
input stop;
input siclk_in;
input soclk_in;

output siclk_out;
output soclk_out;
output  l1clk0;
output  l1clk1;

input   l1clk;
input	se;
input   si;
input   grant_a;
input   qsel0;
input   shift;
output  so;

output  grant_x;
output  qsel0_buf;
output  shift_buf;

wire    siclk_out_unused;
wire    soclk_out_unused;

cl_dp1_ccx_l1hdr_16x hdr0 (
.l2clk(l2clk),
.se(se),
.pce(pce0),
.aclk(siclk_in),
.bclk(soclk_in),
.siclk_out(siclk_out),
.soclk_out(soclk_out),
.l1clk(l1clk0),
.pce_ov(pce_ov),
.stop(stop)
);

cl_dp1_ccx_l1hdr_16x hdr1 (
.l2clk(l2clk),
.se(se),
.pce(pce1),
.aclk(siclk_in),
.bclk(soclk_in),
.siclk_out(siclk_out_unused),
.soclk_out(soclk_out_unused),
.l1clk(l1clk1),
.pce_ov(pce_ov),
.stop(stop)
);

cl_dp1_ccx_msff_16x msff1 (
.l1clk(l1clk),
.siclk(siclk_out),
.soclk(soclk_out),
.d(grant_a),
.si(si),
.so(so),
.q(grant_x)
);

assign qsel0_buf = qsel0;
assign shift_buf = shift;

                
endmodule // cl_dp1_ccxhdr

module cl_dp1_ccx_mac_a (
l1clk0,
l1clk1,
siclk,
soclk,
grant_x,
data_a,
data_x_l,
qsel0_buf,
shift_buf,                         
si,                         
so
);

input l1clk0;
input l1clk1;
input siclk;
input soclk;
input grant_x;
input data_a;

input qsel0_buf;
input shift_buf;

output data_x_l;

input  si;
output so;

wire   so1;
wire   q1;
wire   q0;
wire   q0_in;

cl_dp1_ccx_msff_4x msff1 (
.l1clk(l1clk1),
.siclk(siclk),
.soclk(soclk),
.d(data_a),
.si(si),
.so(so1),
.q(q1)
);

cl_dp1_ccx_aomux2_4x mux1(
.in0(data_a),
.in1(q1),
.sel0(qsel0_buf),
.sel1(shift_buf),
.out(q0_in)
);

cl_dp1_ccx_msff_4x msff0 (
.l1clk(l1clk0),
.siclk(siclk),
.soclk(soclk),
.d(q0_in),
.si(so1),
.so(so),
.q(q0)
);

cl_dp1_ccx_nand2_4x nand0(
.in0(q0),
.in1(grant_x),
.out(data_x_l)
);

endmodule // cl_dp1_ccx_mac_a

module cl_dp1_ccx_mac_b (
l1clk0,
l1clk1,
siclk,
soclk,
grant_x,
data_a,
data_prev_x_l,                         
data_x_l,
qsel0_buf,
shift_buf,                         
si,                         
so
);

input l1clk0;
input l1clk1;
input siclk;
input soclk;
input grant_x;
input data_a;
input data_prev_x_l;

input qsel0_buf;
input shift_buf;

output data_x_l;

input  si;
output so;

wire   so1;
wire   q1;
wire   q0;
wire   q0_in;
wire   x4;
wire   x5;


cl_dp1_ccx_msff_4x msff1 (
.l1clk(l1clk1),
.siclk(siclk),
.soclk(soclk),
.d(data_a),
.si(si),
.so(so1),
.q(q1)
);

cl_dp1_ccx_aomux2_4x mux1(
.in0(data_a),
.in1(q1),
.sel0(qsel0_buf),
.sel1(shift_buf),
.out(q0_in)
);

cl_dp1_ccx_msff_4x msff0 (
.l1clk(l1clk0),
.siclk(siclk),
.soclk(soclk),
.d(q0_in),
.si(so1),
.so(so),
.q(q0)
);

cl_dp1_ccx_nand2_4x nand0(
.in0(q0),
.in1(grant_x),
.out(x4)
);

cl_dp1_ccx_nand2_12x nand1(
.in0(x4),
.in1(data_prev_x_l),
.out(x5)
);

cl_dp1_ccx_inv_32x inv0(
.in(x5),
.out(data_x_l)
);

endmodule // cl_dp1_ccx_mac_b

module cl_dp1_ccx_mac_c (
l1clk0,
l1clk1,
siclk,
soclk,
grant_x,
data_a,
data_crit_x_l,                         
data_ncrit_x_l,                         
data_x_l,
qsel0_buf,
shift_buf,                         
si,                         
so
);

input l1clk0;
input l1clk1;
input siclk;
input soclk;
input grant_x;
input data_a;
input data_crit_x_l;
input data_ncrit_x_l;

input qsel0_buf;
input shift_buf;

output data_x_l;

input  si;
output so;

wire   so1;
wire   q1;
wire   q0;
wire   q0_in;
wire   x4;
wire   x5;


cl_dp1_ccx_msff_4x msff1 (
.l1clk(l1clk1),
.siclk(siclk),
.soclk(soclk),
.d(data_a),
.si(si),
.so(so1),
.q(q1)
);

cl_dp1_ccx_aomux2_4x mux1(
.in0(data_a),
.in1(q1),
.sel0(qsel0_buf),
.sel1(shift_buf),
.out(q0_in)
);

cl_dp1_ccx_msff_4x msff0 (
.l1clk(l1clk0),
.siclk(siclk),
.soclk(soclk),
.d(q0_in),
.si(so1),
.so(so),
.q(q0)
);

cl_dp1_ccx_nand2_4x nand0(
.in0(q0),
.in1(grant_x),
.out(x4)
);

cl_dp1_ccx_nand3_12x nand1(
.in0(x4),
.in1(data_ncrit_x_l),
.in2(data_crit_x_l),
.out(x5)
);

cl_dp1_ccx_inva_32x inv0(
.in(x5),
.out(data_x_l)
);

endmodule // cl_dp1_ccx_mac_c

module cl_dp1_ccx_mac_b2 (
l1clk0,
l1clk1,
siclk,
soclk,
grant_x,
data_a,
data_prev_x_l,                         
data_x_l,
qsel0_buf,
shift_buf,                         
si,                         
so
);

input l1clk0;
input l1clk1;
input siclk;
input soclk;
input grant_x;
input data_a;
input data_prev_x_l;

input qsel0_buf;
input shift_buf;

output data_x_l;

input  si;
output so;

wire   so1;
wire   q1;
wire   q0;
wire   q0_in;
wire   x4;
wire   x5;


cl_dp1_ccx_msff_4x msff1 (
.l1clk(l1clk1),
.siclk(siclk),
.soclk(soclk),
.d(data_a),
.si(si),
.so(so1),
.q(q1)
);

cl_dp1_ccx_aomux2_4x mux1(
.in0(data_a),
.in1(q1),
.sel0(qsel0_buf),
.sel1(shift_buf),
.out(q0_in)
);

cl_dp1_ccx_msff_4x msff0 (
.l1clk(l1clk0),
.siclk(siclk),
.soclk(soclk),
.d(q0_in),
.si(so1),
.so(so),
.q(q0)
);

cl_dp1_ccx_nand2_4x nand0(
.in0(q0),
.in1(grant_x),
.out(x4)
);

cl_dp1_ccx_nand2_12x nand1(
.in0(x4),
.in1(data_prev_x_l),
.out(x5)
);

cl_dp1_ccx_inva_32x inv0(
.in(x5),
.out(data_x_l)
);

endmodule // cl_dp1_ccx_mac_b2

module cl_dp1_ccx_mac_c2 (
l1clk0,
l1clk1,
siclk,
soclk,
grant_x,
data_a,
data_crit_x_l,                         
data_ncrit_x_l,                         
data_x_l,
qsel0_buf,
shift_buf,                         
si,                         
so
);

input l1clk0;
input l1clk1;
input siclk;
input soclk;
input grant_x;
input data_a;
input data_crit_x_l;
input data_ncrit_x_l;

input qsel0_buf;
input shift_buf;

output data_x_l;

input  si;
output so;

wire   so1;
wire   q1;
wire   q0;
wire   q0_in;
wire   x4;
wire   x5;


cl_dp1_ccx_msff_4x msff1 (
.l1clk(l1clk1),
.siclk(siclk),
.soclk(soclk),
.d(data_a),
.si(si),
.so(so1),
.q(q1)
);

cl_dp1_ccx_aomux2_4x mux1(
.in0(data_a),
.in1(q1),
.sel0(qsel0_buf),
.sel1(shift_buf),
.out(q0_in)
);

cl_dp1_ccx_msff_4x msff0 (
.l1clk(l1clk0),
.siclk(siclk),
.soclk(soclk),
.d(q0_in),
.si(so1),
.so(so),
.q(q0)
);

cl_dp1_ccx_nand2_4x nand0(
.in0(q0),
.in1(grant_x),
.out(x4)
);

cl_dp1_ccx_nand3_12x nand1(
.in0(x4),
.in1(data_ncrit_x_l),
.in2(data_crit_x_l),
.out(x5)
);

cl_dp1_ccx_inva_32x inv0(
.in(x5),
.out(data_x_l)
);

endmodule // cl_dp1_ccx_mac_c2

module cl_dp1_ccx_aomux2_4x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule

module cl_dp1_ccx_buf_8x (
in,
out
);
input	in;
output	out;

`ifdef LIB
assign out = in;
`endif

endmodule
module cl_dp1_ccx_buf_1x (
in,
out
);
input	in;
output	out;

`ifdef LIB
assign out = in;
`endif

endmodule
module cl_dp1_ccx_bufmin_1x (
in,
out
);
input	in;
output	out;

`ifdef LIB
assign out = in;
`endif

endmodule
module cl_dp1_ccx_inv_12x (
in,
out
);
input	in;
output	out;

`ifdef LIB
assign out = ~in;
`endif

endmodule
module cl_dp1_ccx_inv_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
assign out = ~in;
`endif

endmodule
module cl_dp1_ccx_inva_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
assign out = ~in;
`endif

endmodule

module cl_dp1_ccx_msff_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_ccx_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_ccx_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_dp1_ccx_msff_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff

module cl_dp1_ccx_nand2_1x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_dp1_ccx_nand2_12x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_dp1_ccx_nand2_4x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_dp1_ccx_nand3_12x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule
module  cl_dp1_ccx_l1hdr_16x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
wire            l1en = (~stop & ( pce | pce_ov ));
assign       l1clk = (l2clk & l1en) | se;
assign siclk_out = aclk;
assign soclk_out = bclk;
`else
 `ifdef LIB
reg             l1en;
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else

   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif
   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

 `endif //  `ifdef LIB
`endif // !`ifdef FORMAL_TOOL


endmodule

module  cl_dp1_ccx_l1hdr_8x (l1clk,
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 aclk,
                 bclk,
                 siclk_out,
                 soclk_out
                );
// RFM  05/21/2004


   output       l1clk;
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   input        aclk;
   input        bclk;
   output       siclk_out;
   output       soclk_out;
`ifdef FORMAL_TOOL
wire            l1en = (~stop & ( pce | pce_ov ));
assign       l1clk = (l2clk & l1en) | se;
assign siclk_out = aclk;
assign soclk_out = bclk;
`else
 `ifdef LIB
reg             l1en;
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else

   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif
   assign       l1clk = (l2clk & l1en) || se;  // se is async and highest priority

assign siclk_out = aclk;
assign soclk_out = bclk;

 `endif //  `ifdef LIB
`endif // !`ifdef FORMAL_TOOL


endmodule
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cl_mc1.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module cl_mc1_adrff2b_8x ( latout, latout_l, q, q_l, so, d, l1clk, si, siclk, soclk );

   output       latout;
   output       latout_l;
   output       so;
   output       q;
   output       q_l;
   input         d;
   input         l1clk;
   input         si;
   input         siclk;
   input         soclk;

   wire latout, latout_l, so;
   reg m, s;

   `ifdef SCAN_MODE
    `ifdef FAST_FLUSH
        always @(l1clk or siclk or d) begin //vcs optimized code

          if (!l1clk && !siclk)       m <= d;    // Load master with data
          else if ( l1clk && !siclk)  s <=  m;   // Load slave with master data
          else if ( l1clk &&  siclk) begin
               m <=  1'b0;    //  flush reset
               s <=  1'b0;
          end
        end
     `else

      always @(l1clk or siclk or soclk or d or si) begin

        if (!l1clk && !siclk)        m <=  d;    // Load master with data
        else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
        else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan

        if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
        else if (l1clk && siclk && !soclk)  s <= si;    // Flush
      end
     `endif

   `else
      wire  si_unused = si;
 `ifdef INITLATZERO
      initial m = 1'b0;
      initial s = 1'b0;
      `endif

      always @(l1clk or d or si or siclk) begin
        if(siclk==0 && l1clk==0) m <=  d;
        else if(siclk && !l1clk)                m <= 1'bx;
        else if(siclk && l1clk) m <= si;
        if(l1clk && !soclk) s<= m;
      end

    `endif
      assign latout = m & l1clk;
      assign latout_l = ~m & l1clk;
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;


endmodule

module cl_mc1_bistl1hdr_12x (
                 l2clk,
                 se,
                 clksel,
                 bistclk,
                 lce,
                 l1clk
                 );
                
                
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        clksel;
   input        bistclk;
   input        lce;
   output       l1clk;

  assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ;
 
endmodule


module cl_mc1_bistl1hdr_16x (
                 l2clk,
                 se,
                 clksel,
                 bistclk,
                 lce,
                 l1clk
                 );
                
                
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        clksel;
   input        bistclk;
   input        lce;
   output       l1clk;

  assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ;
 
endmodule


module cl_mc1_bistl1hdr_8x (
                 l2clk,
                 se,
                 clksel,
                 bistclk,
                 lce,
                 l1clk
                 );
                
                
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        clksel;
   input        bistclk;
   input        lce;
   output       l1clk;

  assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ;
 
endmodule


module cl_mc1_bistlatch_10x (
                l2clk,
                pce,
                pce_ov,
                lce);
 input  l2clk;
 input  pce;
 input  pce_ov;
 output lce;
 
 `ifdef FORMAL_TOOL
 assign lce = ~(pce | pce_ov);
 `else
 
 `ifdef LIB
 reg lce;
 
 always @ (negedge l2clk)
        begin
        lce <=  ~(pce | pce_ov);
        end
 `endif
 `endif
 endmodule

module cl_mc1_bistlatch_20x (
                l2clk,
                pce,
                pce_ov,
                lce);
 input  l2clk;
 input  pce;
 input  pce_ov;
 output lce;

 `ifdef FORMAL_TOOL
 assign lce = ~(pce | pce_ov);
 `else
 
 `ifdef LIB
 reg lce;
 
 always @ (negedge l2clk)
        begin
        lce <=  ~(pce | pce_ov);
        end
 `endif
 `endif
 endmodule

module cl_mc1_bistlatch_4x (
                l2clk,
                pce,
                pce_ov,
                lce);
 input  l2clk;
 input  pce;
 input  pce_ov;
 output lce;

 `ifdef FORMAL_TOOL
 assign lce = ~(pce | pce_ov);
 `else

 `ifdef LIB
 reg lce;

 always @ (negedge l2clk)
        begin
        lce <=  ~(pce | pce_ov);
        end
 `endif
 `endif
 endmodule
module cl_mc1_cm_com_adff_l ( master, so, d, l1clk, si, siclk, soclk );

   output master;
   output so;

   input  d;
   input  l1clk;
   input  si;
   input  siclk;
   input  soclk;

    wire  master;
    wire   so;

     reg m, s;

    `ifdef SCAN_MODE

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           m <= d;    // Load master with data
               else if ( l1clk &&  siclk)           m <= si;   // Load master with scan or flush
               else if (!l1clk &&  siclk)           m <= 1'bx; // Conflict between data and scan

                    if ( l1clk && !siclk && !soclk)  s <= m;  // Load slave with master data
               else if ( l1clk &&  siclk && !soclk)  s <= si; // Flush
              end
    `else
       wire  si_unused = si;
          `ifdef INITLATZERO
                initial m = 1'b0;
                initial s = 1'b0;
          `endif

       always @(l1clk or d or si or siclk) begin
         if(siclk==0 && l1clk==0) m <=  d;
         if(siclk && !l1clk)      m <= 1'bx;
         else if(siclk && l1clk)  m <= si;
       end

     `endif

         assign master   =   m;
         assign so  =  s;

endmodule

module cl_mc1_cm_com_adff_r ( master, so, d, l1clk, si, siclk, soclk );

   output master;
   output so;

   input  d;
   input  l1clk;
   input  si;
   input  siclk;
   input  soclk;

    wire  master;
    wire   so;

     reg m, s;

    `ifdef SCAN_MODE

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           m <= d;    // Load master with data
               else if ( l1clk &&  siclk)           m <= si;   // Load master with scan or flush
               else if (!l1clk &&  siclk)           m <= 1'bx; // Conflict between data and scan

                    if ( l1clk && !siclk && !soclk)  s <= m;  // Load slave with master data
               else if ( l1clk &&  siclk && !soclk)  s <= si; // Flush
              end
    `else
       wire  si_unused = si;
          `ifdef INITLATZERO
                initial m = 1'b0;
                initial s = 1'b0;
          `endif

       always @(l1clk or d or si or siclk) begin
         if(siclk==0 && l1clk==0) m <=  d;
         if(siclk && !l1clk)      m <= 1'bx;
         else if(siclk && l1clk)  m <= si;
       end

     `endif

         assign master   =   m;
         assign so  =  s;

endmodule

module cl_mc1_cm_com_dff ( master, master_l, so, d, l1clk, si, siclk, soclk );

   output master;
   output master_l;
   output so;

   input  d;
   input  l1clk;
   input  si;
   input  siclk;
   input  soclk;

    wire  master;
    wire  master_l;
    wire   so;

     reg m, s;

    `ifdef SCAN_MODE

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           m <= d;    // Load master with data
               else if ( l1clk &&  siclk)           m <= si;   // Load master with scan or flush
               else if (!l1clk &&  siclk)           m <= 1'bx; // Conflict between data and scan

                    if ( l1clk && !siclk && !soclk)  s <= m;  // Load slave with master data
               else if ( l1clk &&  siclk && !soclk)  s <= si; // Flush
              end
    `else
       wire  si_unused = si;
          `ifdef INITLATZERO
                initial m = 1'b0;
                initial s = 1'b0;
          `endif

       always @(l1clk or d or si or siclk) begin
         if(siclk==0 && l1clk==0) m <=  d;
         if(siclk && !l1clk)      m <= 1'bx;
         else if(siclk && l1clk)  m <= si;
       end

     `endif

         assign master   =   m;
         assign master_l =  ~m;
         assign so  =  s;

endmodule

 module cl_mc1_cm_nor_msff ( q, so, din, clear, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE

   output  q;
   output  so;

   input   din, clear;
   input   l1clk;
   input   si;
   input   siclk;
   input   soclk;

   reg     q;
   wire    so;
   wire    l1clk, siclk, soclk;
                
  `ifdef SCAN_MODE

    reg    m;

             always @(l1clk or siclk or soclk or din or clear or si)
              begin
                    if (!l1clk && !siclk)           m <= ~(din | clear);  // Load master with data
               else if ( l1clk &&  siclk)           m <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           m <= 1'bx;    // Conflict between data and scan
 
               else if ( l1clk && !siclk && !soclk)  q <= m;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
 
        `else
              wire  si_unused = si;
 
          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif
 
              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  ~(din | clear);
                else                  q <= 1'bx;
               end
        `endif
 
         assign so = q;
 
endmodule
// created June 6, 2005, ln

module cl_mc1_gate_antenna_50k ( in );

input in;

endmodule
// created June 6, 2005, ln

module cl_mc1_gate_antenna_5k ( in );

input in;

endmodule

module cl_mc1_irf_lat_rsto (
		l1clk,
		d,
		mq);
input	l1clk;		
input	d;
output	mq;

reg m;
wire mq;

always @ (l1clk or d)
        if (l1clk == 1'b0) m <=  d;

 `ifdef INITLATZERO
    initial m = 1'b0;
  `endif

assign mq = m && l1clk;

endmodule


module cl_mc1_irf_lat_swl (
		l1clk,
		d,
		mq);
input	l1clk;		
input	d;
output	mq;

reg m;
wire mq;

always @ (l1clk or d)
        if (l1clk == 1'b0) m <=  d;

 `ifdef INITLATZERO
    initial m = 1'b0;
  `endif

assign mq = m && l1clk;

endmodule


module cl_mc1_irf_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
 
    output       q;
    output       so;
 
    input         d;
    input         l1clk;
    input         si;
    input         siclk;
    input         soclk;
 
    wire q, so;
    reg m, s;
 
    `ifdef SCAN_MODE
 
       always @(l1clk or siclk or soclk or d or si) begin
 
         if (!l1clk && !siclk)        m <=  d;    // Load master with data
         else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
         else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan
 
         if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
         else if (l1clk && siclk && !soclk)  s <= si;    // Flush
       end
 
    `else
       wire  si_unused = si;
       `ifdef INITLATZERO
       initial m = 1'b0;
       initial s = 1'b0;
       `endif
 
       always @(l1clk or d or si or siclk) begin
         if(siclk==0 && l1clk==0) m <=  d;
         if(siclk && !l1clk)                m <= 1'bx;
         else if(siclk && l1clk) m <= si;
       end
 
     `endif
 
       assign q = s;
       assign so  =  s;
 
endmodule

// Driver
module  cl_mc1_l1driver_12x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

// Driver
module  cl_mc1_l1driver_16x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

// Driver
module  cl_mc1_l1driver_24x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

// Driver
module  cl_mc1_l1driver_32x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

module  cl_mc1_l1driver_48x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

// Driver
module  cl_mc1_l1driver_4x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;

   wire        l1clk;

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule


// Driver
module  cl_mc1_l1driver_64x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

// Driver
module  cl_mc1_l1driver_8x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;

   wire       l1clk;

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule


// Driver double wide
module  cl_mc1_l1driver_by2_24x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

// Driver double wide
module  cl_mc1_l1driver_by2_32x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire        l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

module  cl_mc1_l1driver_by2_48x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

module  cl_mc1_l1driver_by2_64x (
                 l2clk,
                 se,
                 l1en,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        l1en;           // Clock enable for local power savings
   output       l1clk;
 
   wire       l1clk;
 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority
endmodule

// Edge modeled Enable latch
module cl_mc1_l1enable_12x (
                l2clk,
                pce,
                pce_ov,
                l1en);
input   l2clk;
input   pce;
input   pce_ov;
output  l1en;
 
reg l1en;
 
always @ (negedge l2clk )
        begin
           l1en <=  (pce | pce_ov);
        end

// logically correct model
// always @ (l2clk or pce or pce_ov)
//         if (l2clk == 1'b0) l1en <=  (pce | pce_ov);
endmodule

// Edge modeled Enable latch
module cl_mc1_l1enable_16x (
                l2clk,
                pce,
                pce_ov,
                l1en);
input   l2clk;
input   pce;
input   pce_ov;
output  l1en;
 
reg l1en;
 
always @ (negedge l2clk )
        begin
           l1en <=  (pce | pce_ov);
        end

// logically correct model
// always @ (l2clk or pce or pce_ov)
//         if (l2clk == 1'b0) l1en <=  (pce | pce_ov);
endmodule

// Edge modeled Enable latch
module cl_mc1_l1enable_24x (
                l2clk,
                pce,
                pce_ov,
                l1en);
input   l2clk;
input   pce;
input   pce_ov;
output  l1en;
 
reg l1en;
 
always @ (negedge l2clk )
        begin
           l1en <=  (pce | pce_ov);
        end

// logically correct model
// always @ (l2clk or pce or pce_ov)
//         if (l2clk == 1'b0) l1en <=  (pce | pce_ov);
endmodule

// Edge modeled Enable latch
module cl_mc1_l1enable_32x (
                l2clk,
                pce,
                pce_ov,
                l1en);
input   l2clk;
input   pce;
input   pce_ov;
output  l1en;
 
reg l1en;
 
always @ (negedge l2clk )
        begin
           l1en <=  (pce | pce_ov);
        end

// logically correct model
// always @ (l2clk or pce or pce_ov)
//         if (l2clk == 1'b0) l1en <=  (pce | pce_ov);
endmodule

// Edge modeled Enable latch
module cl_mc1_l1enable_48x (
                l2clk,
                pce,
                pce_ov,
                l1en);
input   l2clk;
input   pce;
input   pce_ov;
output  l1en;
 
reg l1en;
 
always @ (negedge l2clk )
        begin
           l1en <=  (pce | pce_ov);
        end

// logically correct model
// always @ (l2clk or pce or pce_ov)
//         if (l2clk == 1'b0) l1en <=  (pce | pce_ov);
endmodule

// Edge modeled Enable latch
module cl_mc1_l1enable_4x (
                l2clk,
                pce,
                pce_ov,
                l1en);
input   l2clk;
input   pce;
input   pce_ov;
output  l1en;
 
reg l1en;
 
always @ (negedge l2clk )
        begin
           l1en <=  (pce | pce_ov);
        end

// logically correct model
// always @ (l2clk or pce or pce_ov)
//         if (l2clk == 1'b0) l1en <=  (pce | pce_ov);
endmodule

// Edge modeled Enable latch
module cl_mc1_l1enable_64x (
                l2clk,
                pce,
                pce_ov,
                l1en);
input   l2clk;
input   pce;
input   pce_ov;
output  l1en;
 
reg l1en;
 
always @ (negedge l2clk )
        begin
           l1en <=  (pce | pce_ov);
        end

// logically correct model
// always @ (l2clk or pce or pce_ov)
//         if (l2clk == 1'b0) l1en <=  (pce | pce_ov);
endmodule

// Edge modeled Enable latch
module cl_mc1_l1enable_8x (
                l2clk,
                pce,
                pce_ov,
                l1en);
input   l2clk;
input   pce;
input   pce_ov;
output  l1en;
 
reg l1en;
 
always @ (negedge l2clk )
        begin
           l1en <=  (pce | pce_ov);
        end

// logically correct model
// always @ (l2clk or pce or pce_ov)
//         if (l2clk == 1'b0) l1en <=  (pce | pce_ov);
endmodule
module  cl_mc1_l1hdr_16x (
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   output       l1clk;

   reg  l1en;
  `ifdef INITLATZERO
  initial begin
        l1en = 1'b0;
     end
  `endif
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule

module  cl_mc1_l1hdr_24x (
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   output       l1clk;

   reg  l1en;
  `ifdef INITLATZERO
  initial begin
        l1en = 1'b0;
     end
  `endif
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule

module  cl_mc1_l1hdr_32x (
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   output       l1clk;

   reg  l1en;
  `ifdef INITLATZERO
  initial begin
        l1en = 1'b0;
     end
  `endif
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule

module  cl_mc1_l1hdr_48x (
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   output       l1clk;

   reg  l1en;
  `ifdef INITLATZERO
  initial begin
        l1en = 1'b0;
     end
  `endif
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule

module  cl_mc1_l1hdr_64x (
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 l1clk
                );
 
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   output       l1clk;

   reg  l1en;
`ifdef INITLATZERO
  initial begin
        l1en = 1'b0;
     end
`endif
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule

module  cl_mc1_l1hdr_by4_64x (
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 l1clk
                );
  
   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   output       l1clk;
   reg  l1en;
`ifdef INITLATZERO
  initial begin
        l1en = 1'b0;
  end
`endif
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule


module cl_mc1_rep_m6_32x (
in,
out
);
input	in;
output	out;

assign out = in;

endmodule

module cl_mc1_rrf_msff_8x ( q, so, d, l1clk, si, siclk, soclk );
 
    output       q;
    output       so;
 
    input         d;
    input         l1clk;
    input         si;
    input         siclk;
    input         soclk;
 
    wire q, so;
    reg m, s;
 
    `ifdef SCAN_MODE
 
       always @(l1clk or siclk or soclk or d or si) begin
 
         if (!l1clk && !siclk)        m <=  d;    // Load master with data
         else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
         else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan
 
         if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
         else if (l1clk && siclk && !soclk)  s <= si;    // Flush
       end
 
    `else
       wire  si_unused = si;
       `ifdef INITLATZERO
       initial m = 1'b0;
       initial s = 1'b0;
       `endif
 
       always @(l1clk or d or si or siclk) begin
         if(siclk==0 && l1clk==0) m <=  d;
         if(siclk && !l1clk)                m <= 1'bx;
         else if(siclk && l1clk) m <= si;
       end
 
     `endif
 
       assign q = s;
       assign so  =  s;
 
endmodule

module cl_mc1_rrf_msff_mo_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   output     q_l;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, q_l, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule

module cl_mc1_scm_msff_flop_4x (  q, q_l, so, d, l1clk, si, siclk, soclk);
 
          
   output       so;
   output       q;
   output       q_l;
   input         d;
   input         l1clk;
   input         si;
   input         siclk;
   input         soclk;
 
 
   wire  so;
   reg m, s;
 
   `ifdef SCAN_MODE
 
      always @(l1clk or siclk or soclk or d or si) begin
 
        if (!l1clk && !siclk)        m <=  d;    // Load master with data
        else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
        else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan
 
        if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
        else if (l1clk && siclk && !soclk)  s <= si;    // Flush
      end
 
   `else
      wire  si_unused = si;
 `ifdef INITLATZERO
      initial m = 1'b0;
      initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if(siclk==0 && l1clk==0) m =  d;
        else if(siclk && !l1clk)                m = 1'bx;
         if(siclk && l1clk) m = si;
        if(l1clk && !soclk) s = m;
      end
 
    `endif
 
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
               
 
endmodule

module cl_mc1_scm_msff_lat_4x ( latout, q, q_l, so, d, l1clk, si, siclk, soclk);
 
   output       latout;
   output       so;
   output       q;
   output       q_l;
   input         d;
   input         l1clk;
   input         si;
   input         siclk;
   input         soclk;
 
   wire  so;
   reg m, s;
 
   `ifdef SCAN_MODE
    `ifdef FAST_FLUSH
        always @(l1clk or siclk or d) begin //vcs optimized code
 
          if (!l1clk && !siclk)       m <=  d;    // Load master with data
          else if ( l1clk && !siclk)  s <=  m;   // Load slave with master data
          else if ( l1clk &&  siclk) begin
               m <=  1'b0;    //  flush reset
               s <=  1'b0;
          end
        end
     `else
 
      always @(l1clk or siclk or soclk or d or si) begin
 
        if (!l1clk && !siclk)        m <=  d;    // Load master with data
        else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
        else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan
 
        if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
        else if (l1clk && siclk && !soclk)  s <= si;    // Flush
      end
     `endif
 
   `else
      wire  si_unused = si;
 `ifdef INITLATZERO
      initial m = 1'b0;
      initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if(siclk==0 && l1clk==0) m =  d;
        else if(siclk && !l1clk)                m = 1'bx;
         if(siclk && l1clk) m = si;
        if(l1clk && !soclk) s = m;
      end
 
    `endif
      assign latout = m;
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule

module cl_mc1_sram_msff_mo_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   output     q_l;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, q_l, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
   `ifdef FAST_FLUSH
        always @(l1clk or siclk or d) begin //vcs optimized code

          if (!l1clk && !siclk)       m <=  d;    // Load master with data
          else if ( l1clk && !siclk)  s <=  m;   // Load slave with master data
          else if ( l1clk &&  siclk) begin
               m <=  1'b0;    //  flush reset
               s <=  1'b0;
          end
        end
     `else

      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
    `endif
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule

module cl_mc1_sram_msff_mo_32x ( mq, mq_l, q, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
    `ifdef FAST_FLUSH
        always @(l1clk or siclk or d) begin //vcs optimized code

          if (!l1clk && !siclk)       m <=  d;    // Load master with data
          else if ( l1clk && !siclk)  s <=  m;   // Load slave with master data
          else if ( l1clk &&  siclk) begin
               m <=  1'b0;    //  flush reset
               s <=  1'b0;
          end
        end
     `else

      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
     `endif
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
 
endmodule

module cl_mc1_sram_msff_mo_4x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   output     q_l;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, q_l, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
   `ifdef FAST_FLUSH
        always @(l1clk or siclk or d) begin //vcs optimized code

          if (!l1clk && !siclk)       m <=  d;    // Load master with data
          else if ( l1clk && !siclk)  s <=  m;   // Load slave with master data
          else if ( l1clk &&  siclk) begin
               m <=  1'b0;    //  flush reset
               s <=  1'b0;
          end
        end
     `else

      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
    `endif
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule

module cl_mc1_sram_msff_mo_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   output     q_l;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, q_l, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
   `ifdef FAST_FLUSH
        always @(l1clk or siclk or d) begin //vcs optimized code

          if (!l1clk && !siclk)       m <=  d;    // Load master with data
          else if ( l1clk && !siclk)  s <=  m;   // Load slave with master data
          else if ( l1clk &&  siclk) begin
               m <=  1'b0;    //  flush reset
               s <=  1'b0;
          end
        end
     `else

      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
    `endif
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule
module cl_mc1_sram_msff_mo_nand2_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk );

   output mq;
   output mq_l;
   output q;
   output q_l;
   output so;

   input  d;
   input  l1clk;
   input  si;
   input  siclk;
   input  soclk;

    wire  mq;
    wire  mq_l;
    wire   q;
    wire  q_l;
    wire  so;

    reg m, s;

    `ifdef SCAN_MODE
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           m <= d;    // Load master with data
               else if ( l1clk &&  siclk)           m <= si;   // Load master with scan or flush
               else if (!l1clk &&  siclk)           m <= 1'bx; // Conflict between data and scan

                    if ( l1clk && !siclk && !soclk)  s <= m;   // Load slave with master data
               else if ( l1clk &&  siclk && !soclk)  s <= si;  // Flush
              end
   `else
//      wire   si_unused = si;

          `ifdef INITLATZERO
                initial m = 1'b0;
                initial s = 1'b0;
          `endif

      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif

    `ifdef MODEL_AND
      assign mq = m & l1clk;
      assign mq_l = ~m & l1clk;
    `else
      wire      si_unused = siclk;
      assign mq = m;
      assign mq_l = ~m;
    `endif

         assign so = s;
         assign q   =  s;
         assign q_l = ~s;

endmodule

module cl_mc1_sram_msff_mo_nand2_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk );

   output mq;
   output mq_l;
   output q;
   output q_l;
   output so;

   input  d;
   input  l1clk;
   input  si;
   input  siclk;
   input  soclk;

    wire  mq;
    wire  mq_l;
    wire   q;
    wire  q_l;
    wire  so;

    reg m, s;

    `ifdef SCAN_MODE
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           m <= d;    // Load master with data
               else if ( l1clk &&  siclk)           m <= si;   // Load master with scan or flush
               else if (!l1clk &&  siclk)           m <= 1'bx; // Conflict between data and scan

                    if ( l1clk && !siclk && !soclk)  s <= m;   // Load slave with master data
               else if ( l1clk &&  siclk && !soclk)  s <= si;  // Flush
              end
   `else
//      wire   si_unused = si;

          `ifdef INITLATZERO
                initial m = 1'b0;
                initial s = 1'b0;
          `endif

      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif

    `ifdef MODEL_AND
      assign mq = m & l1clk;
      assign mq_l = ~m & l1clk;
    `else
      wire      si_unused = siclk;
      assign mq = m;
      assign mq_l = ~m;
    `endif

         assign so = s;
         assign q   =  s;
         assign q_l = ~s;

endmodule


module cl_mc1_sram_msff_mo_nand3_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   output     q_l;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, q_l, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule

module cl_mc1_sram_msff_mo_nand3_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   output     q_l;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, q_l, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule

module cl_mc1_sram_msff_mo_opt_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   output     q_l;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, q_l, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule

module cl_mc1_sram_msff_mo_opt_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
 
   output     mq;
   output     mq_l;
   output     so;
   output     q;
   output     q_l;
   input      d;
   input      l1clk;
   input      and_clk;
   input      si;
   input      siclk;
   input      soclk;
 
   wire  mq, mq_l, q, q_l, so;
   reg   m, s;
 
   `ifdef SCAN_MODE
      always @(l1clk or siclk or soclk or d or si) begin
 
        if      (!l1clk && !siclk) m <=  d;   //Load master with data
        else if ( l1clk &&  siclk) m <=  si;  //Load master with scan or flush
        else if (!l1clk &&  siclk) m <=  1'bx;   //Conflict between data and scan
 
        if      (l1clk && !soclk && !siclk)  s <= m;  // Load slave with master data
        else if (l1clk && !soclk &&  siclk)  s <= si; // Flush
      end
 
   `else
//      wire   si_unused = si;
 
      `ifdef INITLATZERO
        initial m = 1'b0;
        initial s = 1'b0;
      `endif
 
      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) s <= m;
      end
 
    `endif
 
    `ifdef MODEL_AND
      assign mq = m & (and_clk & l1clk);
      assign mq_l = ~m & (and_clk & l1clk);
    `else
      wire      and_clk_unused = and_clk;
      assign mq = m;
      assign mq_l = ~m;
    `endif
      assign so  =  s;
      assign q   =  s;
      assign q_l = ~s;
 
endmodule
module cl_mc1_sram_msff_mo_phaseb_8x ( phaseb_mq, phaseb_mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );

   output phaseb_mq;
   output phaseb_mq_l;
   output q;
   output q_l;
   output so;

   input  d;
   input  l1clk;
   input  si;
   input  siclk;
   input  soclk;
   input  and_clk;

    wire  phaseb_mq;
    wire  phaseb_mq_l;
    reg   q;
    wire  q_l;
    wire  so;

    reg m;
    
   `ifdef SCAN_MODE
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           m <= d;    // Load master with data
               else if ( l1clk &&  siclk)           m <= si;   // Load master with scan or flush
               else if (!l1clk &&  siclk)           m <= 1'bx; // Conflict between data and scan

                    if ( l1clk && !siclk && !soclk)  q <= m;   // Load slave with master data
               else if ( l1clk &&  siclk && !soclk)  q <= si;   // Flush
              end
   `else
//      wire   si_unused = si;

          `ifdef INITLATZERO
                initial q = 1'b0;
                initial m = 1'b0;
          `endif

      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m <= d;
        else if ( siclk && !l1clk) m <= 1'bx;
        else if ( siclk &&  l1clk) m <= si;
        if      ( l1clk && !soclk) q <= m;
      end

    `endif

    `ifdef MODEL_AND
      assign phaseb_mq   = ~and_clk  && q;
      assign phaseb_mq_l = ~and_clk  && q_l;
    `else
      wire      and_clk_unused = and_clk;
      assign phaseb_mq   = q;
      assign phaseb_mq_l = ~q;
    `endif
         assign so = q;
         assign q_l = ~q;

endmodule


module cl_mc1_tcam_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
 
    output       q;
    output       so;
 
    input         d;
    input         l1clk;
    input         si;
    input         siclk;
    input         soclk;
 
    wire q, so;
    reg m, s;
 
    `ifdef SCAN_MODE
 
       always @(l1clk or siclk or soclk or d or si) begin
 
         if (!l1clk && !siclk)        m <=  d;    // Load master with data
         else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
         else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan
 
         if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
         else if (l1clk && siclk && !soclk)  s <= si;    // Flush
       end
 
    `else
       wire  si_unused = si;
       `ifdef INITLATZERO
       initial m = 1'b0;
       initial s = 1'b0;
       `endif
 
       always @(l1clk or d or si or siclk) begin
         if(siclk==0 && l1clk==0) m <=  d;
         if(siclk && !l1clk)                m <= 1'bx;
         else if(siclk && l1clk) m <= si;
       end
 
     `endif
 
       assign q = s;
       assign so  =  s;
 
endmodule

module cl_mc1_tisram_bla_4x (q_a, d_b, l1clk);
     output       q_a;
     input         d_b;
     input         l1clk;
  reg q_a;

 `ifdef INITLATZERO
                  initial q_a = 1'b0;
 `endif
 
        always @(l1clk or d_b) begin
          if(l1clk==1)    q_a <=  d_b;
        end
 
endmodule


module cl_mc1_tisram_blb_4x (q_b, d_a, l1clk);
     output       q_b;
     input         d_a;
     input         l1clk;
  reg q_b;

 `ifdef INITLATZERO
                  initial q_b = 1'b0;
 `endif
 
        always @(l1clk or d_a) begin
          if(l1clk==0)    q_b <=  d_a;
        end
 
endmodule


module cl_mc1_tisram_blbi_8x (q_b_l, d_a, l1clk);
     output       q_b_l;
     input         d_a;
     input         l1clk;
  reg q_b_l;

 `ifdef INITLATZERO
                  initial q_b_l = 1'b0;
 `endif

        always @(l1clk or d_a) begin
          if(l1clk==0)    q_b_l <=  ~d_a;
        end

endmodule

module cl_mc1_tisram_msff_16x ( latout, latout_l, so, d, l1clk, si,
siclk, soclk );
 
    output       latout;
    output       latout_l;
    output       so;
 
    input         d;
    input         l1clk;
    input         si;
    input         siclk;
    input         soclk;
 
    wire latout, latout_l, so;
    reg m, s;
 
    `ifdef SCAN_MODE
 
       always @(l1clk or siclk or soclk or d or si) begin
 
         if (!l1clk && !siclk)        m <=  d;    // Load master with data
         else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
         else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan
 
         if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
         else if (l1clk && siclk && !soclk)  s <= si;    // Flush
       end
 
    `else
       wire  si_unused = si;
       `ifdef INITLATZERO
       initial m = 1'b0;
       initial s = 1'b0;
       `endif
 
       always @(l1clk or d or si or siclk) begin
         if(siclk==0 && l1clk==0) m <=  d;
         if(siclk && !l1clk)                m <= 1'bx;
         else if(siclk && l1clk) m <= si;
       end
 
     `endif
 
       assign latout = m;
       assign latout_l = ~m;
       assign so  =  s;
 
endmodule

module cl_mc1_tisram_msff_8x ( latout, latout_l, so, d, l1clk, si,
siclk, soclk );
 
    output       latout;
    output       latout_l;
    output       so;
 
    input         d;
    input         l1clk;
    input         si;
    input         siclk;
    input         soclk;
 
    wire latout, latout_l, so;
    reg m, s;
 
    `ifdef SCAN_MODE
 
       always @(l1clk or siclk or soclk or d or si) begin
 
         if (!l1clk && !siclk)        m <=  d;    // Load master with data
         else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
         else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan
 
         if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
         else if (l1clk && siclk && !soclk)  s <= si;    // Flush
       end
 
    `else
       wire  si_unused = si;
       `ifdef INITLATZERO
       initial m = 1'b0;
       initial s = 1'b0;
       `endif
 
       always @(l1clk or d or si or siclk) begin
         if(siclk==0 && l1clk==0) m <=  d;
         if(siclk && !l1clk)                m <= 1'bx;
         else if(siclk && l1clk) m <= si;
       end
 
     `endif
 
       assign latout = m;
       assign latout_l = ~m;
       assign so  =  s;
 
endmodule
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cl_rtl_ext.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module  mux2e ( dout, in0, in1, sel );

   parameter                    SIZE = 1;

   output       [SIZE-1:0]      dout;
   input        [SIZE-1:0]      in0;
   input        [SIZE-1:0]      in1;
   input                        sel;

   reg          [SIZE-1:0]      dout;

   always @ ( sel or in0 or in1 )
	 begin
	    case ( sel )    
	      1'b0: dout = in0;
	      1'b1: dout = in1;
			    
	      default:
		  dout = { SIZE { 1'bx } }; 
	    endcase // case( sel )
	 end // always @ ( sel or in0 or in1 )

endmodule // mux2e


module	mux3 ( dout, in0,  in1,  in2,
		     sel0, sel1, sel2, muxtst );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input			sel0;
   input			sel1;
   input			sel2;
   input			muxtst;
 
   wire		     [3:0]	sel = { muxtst, sel2, sel1, sel0 };

  reg		[SIZE-1:0] 	dout;

`ifdef MUXOHTEST
//0in one_hot -var sel[2:0] -message "mux3 selects not one-hot!"
`endif

  always @ ( sel or in0 or in1 or in2 )
     casex ( sel )	
       4'bx001:			dout = in0;
       4'bx010:			dout = in1;
       4'bx100:			dout = in2;
       4'b0000:			dout = { SIZE {1'b1 }};
			
       default:
	      dout = { SIZE { 1'bx } }; 
     endcase // case( sel )

endmodule // mux3


module	mux4 ( dout, in0,  in1,  in2,  in3,
		     sel0, sel1, sel2, sel3, muxtst );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			muxtst;

   wire		     [4:0]	sel = { muxtst, sel3, sel2, sel1, sel0 };

   reg		[SIZE-1:0] 	dout;

`ifdef MUXOHTEST
//0in one_hot -var sel[3:0] -message "mux4 selects not one-hot!"
`endif

   always @ ( sel or in0 or in1 or in2 or in3 )
     casex ( sel )	
       5'bx0001:			dout = in0;
       5'bx0010:			dout = in1;
       5'bx0100:			dout = in2;
       5'bx1000:			dout = in3;
       5'b00000:			dout = { SIZE { 1'b1 } };
			
       default:
	      dout = { SIZE { 1'bx } }; 
     endcase // case( sel )


endmodule // mux4


module	mux5 ( dout, in0,  in1,  in2,  in3,  in4,
		     sel0, sel1, sel2, sel3, sel4, muxtst );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input	[SIZE-1:0]	in4;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			sel4;
   input			muxtst;

   wire		     [5:0]	sel = { muxtst, sel4, sel3, sel2, sel1, sel0 };

   reg		[SIZE-1:0] 	dout;

`ifdef MUXOHTEST
//0in one_hot -var sel[4:0] -message "mux5 selects not one-hot!"
`endif

   always @ ( sel or in0 or in1 or in2 or in3 or in4 )
     casex ( sel )	
       6'bx00001:		dout = in0;
       6'bx00010:		dout = in1;
       6'bx00100:		dout = in2;
       6'bx01000:		dout = in3;
       6'bx10000:		dout = in4;
       6'b000000:		dout = { SIZE { 1'b1 }};
			
       default:
	      dout = { SIZE { 1'bx } }; 
     endcase // case( sel )

endmodule // mux5


module	mux6 ( dout, in0,  in1,  in2,  in3,  in4,  in5,
		     sel0, sel1, sel2, sel3, sel4, sel5, muxtst );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input	[SIZE-1:0]	in4;
   input	[SIZE-1:0]	in5;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			sel4;
   input			sel5;
   input			muxtst;

   wire		     [6:0]	sel = { muxtst, sel5,
					sel4, sel3, sel2, sel1, sel0 };

   reg		[SIZE-1:0] 	dout;

`ifdef MUXOHTEST
//0in one_hot -var sel[5:0] -message "mux6 selects not one-hot!"
`endif

   always @ ( sel or in0 or in1 or in2 or in3 or in4 or
		     in5 )
     casex ( sel )	
       7'bx000001:		dout = in0;
       7'bx000010:		dout = in1;
       7'bx000100:		dout = in2;
       7'bx001000:		dout = in3;
       7'bx010000:		dout = in4;
       7'bx100000:		dout = in5;
       7'b0000000:		dout = { SIZE { 1'b1 } };
			
       default:
	      dout = { SIZE { 1'bx } }; 
     endcase // case( sel )

endmodule // mux6


module	mux7 ( dout, in0,  in1,  in2,  in3,  in4,  in5,  in6,
		     sel0, sel1, sel2, sel3, sel4, sel5, sel6, muxtst );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input	[SIZE-1:0]	in4;
   input	[SIZE-1:0]	in5;
   input	[SIZE-1:0]	in6;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			sel4;
   input			sel5;
   input			sel6;
   input 			muxtst;

   wire		     [7:0]	sel = { muxtst, sel6, sel5,
					sel4, sel3, sel2, sel1, sel0 };
   reg		[SIZE-1:0] 	dout;

`ifdef MUXOHTEST
//0in one_hot -var sel[6:0] -message "mux7 selects not one-hot!"
`endif

   always @ ( sel or in0 or in1 or in2 or in3 or in4 or
		     in5 or in6 )
     casex ( sel )	
       8'bx0000001:		dout = in0;
       8'bx0000010:		dout = in1;
       8'bx0000100:		dout = in2;
       8'bx0001000:		dout = in3;
       8'bx0010000:		dout = in4;
       8'bx0100000:		dout = in5;
       8'bx1000000:		dout = in6;
       8'b00000000:		dout = { SIZE { 1'b1 } };
			
       default:
	      dout = { SIZE { 1'bx } }; 
     endcase // case( sel )

endmodule // mux7


module	mux8 ( dout, in0,  in1,  in2,  in3,  in4,  in5,  in6,  in7,
		     sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7, muxtst );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input	[SIZE-1:0]	in4;
   input	[SIZE-1:0]	in5;
   input	[SIZE-1:0]	in6;
   input	[SIZE-1:0]	in7;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			sel4;
   input			sel5;
   input			sel6;
   input			sel7;
   input			muxtst;

   wire		     [8:0]	sel = { muxtst, sel7, sel6, sel5,
					sel4, sel3, sel2, sel1, sel0 };
   reg		[SIZE-1:0] 	dout;

`ifdef MUXOHTEST
//0in one_hot -var sel[7:0] -message "mux8 selects not one-hot!"
`endif

   always @ ( sel or in0 or in1 or in2 or in3 or in4 or
		     in5 or in6 or in7 )
     casex ( sel )	
       9'bx00000001:		dout = in0;
       9'bx00000010:		dout = in1;
       9'bx00000100:		dout = in2;
       9'bx00001000:		dout = in3;
       9'bx00010000:		dout = in4;
       9'bx00100000:		dout = in5;
       9'bx01000000:		dout = in6;
       9'bx10000000:		dout = in7;
       9'b000000000:		dout = { SIZE { 1'b1 } };
			
       default:
	      dout = { SIZE { 1'bx } }; 
     endcase // case( sel )

endmodule // mux8


`ifdef FPGA
`else
module	mux2s ( dout, in0,  in1,
		      sel0, sel1 );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input			sel0;
   input			sel1;

   assign			dout = ( ( in0 & { SIZE { sel0 } } ) |
					 ( in1 & { SIZE { sel1 } } ) );

endmodule // mux2s
`endif // `ifdef FPGA


module	mux3s ( dout, in0,  in1,  in2,
		      sel0, sel1, sel2 );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input			sel0;
   input			sel1;
   input			sel2;

   assign			dout = ( ( in0 & { SIZE { sel0 } } ) |
					 ( in1 & { SIZE { sel1 } } ) |
					 ( in2 & { SIZE { sel2 } } ) );

endmodule // mux3s


`ifdef FPGA
`else
module	mux4s ( dout, in0,  in1,  in2,  in3,
		      sel0, sel1, sel2, sel3 );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;

   assign			dout = ( ( in0 & { SIZE { sel0 } } ) |
					 ( in1 & { SIZE { sel1 } } ) |
					 ( in2 & { SIZE { sel2 } } ) |
					 ( in3 & { SIZE { sel3 } } ) );

endmodule // mux4s
`endif // `ifdef FPGA


module	mux5s ( dout, in0,  in1,  in2,  in3,  in4,
		      sel0, sel1, sel2, sel3, sel4 );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input	[SIZE-1:0]	in4;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			sel4;

   assign			dout = ( ( in0 & { SIZE { sel0 } } ) |
					 ( in1 & { SIZE { sel1 } } ) |
					 ( in2 & { SIZE { sel2 } } ) |
					 ( in3 & { SIZE { sel3 } } ) |
					 ( in4 & { SIZE { sel4 } } ) );

endmodule // mux5s


module	mux6s ( dout, in0,  in1,  in2,  in3,  in4,  in5,
		      sel0, sel1, sel2, sel3, sel4, sel5 );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input	[SIZE-1:0]	in4;
   input	[SIZE-1:0]	in5;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			sel4;
   input			sel5;

   assign			dout = ( ( in0 & { SIZE { sel0 } } ) |
					 ( in1 & { SIZE { sel1 } } ) |
					 ( in2 & { SIZE { sel2 } } ) |
					 ( in3 & { SIZE { sel3 } } ) |
					 ( in4 & { SIZE { sel4 } } ) |
					 ( in5 & { SIZE { sel5 } } ) );

endmodule // mux6s


module	mux7s ( dout, in0,  in1,  in2,  in3,  in4,  in5,  in6,
		      sel0, sel1, sel2, sel3, sel4, sel5, sel6 );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input	[SIZE-1:0]	in4;
   input	[SIZE-1:0]	in5;
   input	[SIZE-1:0]	in6;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			sel4;
   input			sel5;
   input			sel6;

   assign			dout = ( ( in0 & { SIZE { sel0 } } ) |
					 ( in1 & { SIZE { sel1 } } ) |
					 ( in2 & { SIZE { sel2 } } ) |
					 ( in3 & { SIZE { sel3 } } ) |
					 ( in4 & { SIZE { sel4 } } ) |
					 ( in5 & { SIZE { sel5 } } ) |
					 ( in6 & { SIZE { sel6 } } ) );

endmodule // mux7s


`ifdef FPGA
`else
module	mux8s ( dout, in0,  in1,  in2,  in3,  in4,  in5,  in6,  in7,
		      sel0, sel1, sel2, sel3, sel4, sel5, sel6, sel7 );

   parameter			SIZE = 1;

   output	[SIZE-1:0]	dout;
   input	[SIZE-1:0]	in0;
   input	[SIZE-1:0]	in1;
   input	[SIZE-1:0]	in2;
   input	[SIZE-1:0]	in3;
   input	[SIZE-1:0]	in4;
   input	[SIZE-1:0]	in5;
   input	[SIZE-1:0]	in6;
   input	[SIZE-1:0]	in7;
   input			sel0;
   input			sel1;
   input			sel2;
   input			sel3;
   input			sel4;
   input			sel5;
   input			sel6;
   input			sel7;

   assign			dout = ( ( in0 & { SIZE { sel0 } } ) |
					 ( in1 & { SIZE { sel1 } } ) |
					 ( in2 & { SIZE { sel2 } } ) |
					 ( in3 & { SIZE { sel3 } } ) |
					 ( in4 & { SIZE { sel4 } } ) |
					 ( in5 & { SIZE { sel5 } } ) |
					 ( in6 & { SIZE { sel6 } } ) |
					 ( in7 & { SIZE { sel7 } } ) );

endmodule // mux8s
`endif  // `ifdef FPGA

// There are inverted and non-inverted versions of this...different between power levels!
// First the non-inverting
module tisram_blb ( latout_l, d, l1clk);

   parameter SIZE = 1;


   output	[SIZE-1:0] 	latout_l;

   input        [SIZE-1:0] 	d;
   input         		l1clk;

   reg [SIZE-1:0] latout_l;

   `ifdef SCAN_MODE
   `else
      `ifdef INITLATZERO
        initial latout_l[SIZE-1:0] = {SIZE{1'b0}};
      `endif
   `endif

    always @(l1clk or d) begin
      if (!l1clk) latout_l[SIZE-1:0] <= d[SIZE-1:0];
    end

endmodule 

// Now the inverting
module tisram_blb_inv ( latout_l, d, l1clk);

   parameter SIZE = 1;
 

   output	[SIZE-1:0] 	latout_l;

   input        [SIZE-1:0] 	d;
   input         		l1clk;

   reg [SIZE-1:0] latout_l;

   `ifdef SCAN_MODE
   `else
      `ifdef INITLATZERO
        initial latout_l[SIZE-1:0] = {SIZE{1'b0}};
      `endif
   `endif

    always @(l1clk or d) begin
      if (!l1clk) latout_l[SIZE-1:0] <= ~d[SIZE-1:0];
    end

endmodule 

module tisram_bla (q_a, d_b, l1clk);

    parameter SIZE = 1;

    output   [SIZE-1:0] q_a;
    input    [SIZE-1:0] d_b;
    input         	l1clk;

    reg  [SIZE-1:0] q_a;

   `ifdef SCAN_MODE
   `else
      `ifdef INITLATZERO
        initial q_a[SIZE-1:0] = {SIZE{1'b0}};
      `endif
   `endif

    always @(l1clk or d_b) begin
      if (l1clk==1'b1)    
        q_a[SIZE-1:0] <= d_b[SIZE-1:0];
    end

endmodule 

module msffi ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output  	[SIZE-1:0]   	q_l;
   output       [SIZE-1:0]	so;

   input   	[SIZE-1:0]      d;
   input     			l1clk;
   input      	[SIZE-1:0]	si;
   input   			siclk;
   input   			soclk;

   reg		[SIZE-1:0]      q;
   reg		[SIZE-1:0]      q_l;

   wire     	[SIZE-1:0]	so;
   wire      			l1clk, siclk, soclk;
        `ifdef SCAN_MODE

          `ifdef FAST_FLUSH
             always @(posedge l1clk or posedge siclk ) begin
               if (siclk) begin
                 q[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
               end else begin
                 q[SIZE-1:0] <=  d[SIZE-1:0];
               end
             end

          `else

             reg [SIZE-1:0] l1;

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1[SIZE-1:0] <= d[SIZE-1:0];    // Load master with data
               else if ( l1clk &&  siclk)           l1[SIZE-1:0] <= si[SIZE-1:0];    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1[SIZE-1:0] <= {SIZE{1'bx}};    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q[SIZE-1:0] <= l1[SIZE-1:0];    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q[SIZE-1:0] <= si[SIZE-1:0];    // Flush
              end

	  `endif // FAST_FLUSH

        `else
              wire  [SIZE-1:0] si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused[SIZE-1:0] = si[SIZE-1:0];
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q[SIZE-1:0] = {SIZE{1'b0}};
                initial q_l[SIZE-1:0] = {SIZE{1'b1}};
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q[SIZE-1:0] <=  d[SIZE-1:0];
                else                  q[SIZE-1:0] <= {SIZE{1'bx}};
               end
        `endif

	always @ (q)  q_l=~q;

         assign so[SIZE-1:0] = q[SIZE-1:0];

endmodule // dff

module msffi_dp ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output  	[SIZE-1:0]   	q_l;
   output       [SIZE-1:0]	so;

   input   	[SIZE-1:0]      d;
   input     			l1clk;
   input      	[SIZE-1:0]	si;
   input   			siclk;
   input   			soclk;

   reg		[SIZE-1:0]      q;
   reg		[SIZE-1:0]      q_l;

   wire     	[SIZE-1:0]	so;
   wire      			l1clk, siclk, soclk;
        `ifdef SCAN_MODE

          `ifdef FAST_FLUSH
             always @(posedge l1clk or posedge siclk ) begin
               if (siclk) begin
                 q[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
               end else begin
                q[SIZE-1:0] <=  d[SIZE-1:0];
               end
             end

          `else

             reg [SIZE-1:0] l1;

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1[SIZE-1:0] <= d[SIZE-1:0];    // Load master with data
               else if ( l1clk &&  siclk)           l1[SIZE-1:0] <= si[SIZE-1:0];    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1[SIZE-1:0] <= {SIZE{1'bx}};    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q[SIZE-1:0] <= l1[SIZE-1:0];    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q[SIZE-1:0] <= si[SIZE-1:0];    // Flush
              end

           `endif // FAST_FLUSH

        `else
              wire  [SIZE-1:0] si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused[SIZE-1:0] = si[SIZE-1:0];
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                // dp macro inits to 0!
                initial q[SIZE-1:0] = {SIZE{1'b0}};
                initial q_l[SIZE-1:0] = {SIZE{1'b1}};
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q[SIZE-1:0] <=  d[SIZE-1:0];
                else                  q[SIZE-1:0] <= {SIZE{1'bx}};
               end
        `endif

	always @ (q)  q_l=~q;

         // Fake inversion
         assign so[SIZE-1:0] = q[SIZE-1:0];

endmodule // msffi_dp

module msffiz_dp ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output [SIZE-1:0]    q_l;
   output [SIZE-1:0]    so;

   input  [SIZE-1:0]    d;
   input  [SIZE-1:0]    si;
   input   		l1clk;
   input   		siclk;
   input   		soclk;

   reg    [SIZE-1:0]   q_l;

   wire    [SIZE-1:0] so;
   wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

          `ifdef FAST_FLUSH
             always @(posedge l1clk or posedge siclk ) begin
               if (siclk) begin
                 q_l[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
               end else begin
                 q_l[SIZE-1:0] <=  ~d[SIZE-1:0];
               end
             end

          `else

             reg [SIZE-1:0] l1;

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1[SIZE-1:0] <= ~d[SIZE-1:0];    // Load master with data
               else if ( l1clk &&  siclk)           l1[SIZE-1:0] <= si[SIZE-1:0];    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1[SIZE-1:0] <= {SIZE {1'bx}};   // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q_l[SIZE-1:0] <= l1[SIZE-1:0];  // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q_l[SIZE-1:0] <= si[SIZE-1:0];  // Flush
              end

           `endif // FAST_FLUSH

        `else
              wire  [SIZE-1:0] si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused[SIZE-1:0] = si[SIZE-1:0];
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l[SIZE-1:0] = {SIZE {1'b0}};
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q_l[SIZE-1:0] <=  ~d[SIZE-1:0];
                else                  q_l[SIZE-1:0] <= {SIZE {1'bx}};
               end
        `endif

         assign so[SIZE-1:0] = q_l[SIZE-1:0];


endmodule // msffiz_dp

module bs_cell2 (q, so, d, l1clk, si, siclk, soclk, updateclk, mode, muxd, highZ_N);

   parameter SIZE=1;

   output	[SIZE-1:0]	q;
   output       [SIZE-1:0]	so;

   input        [SIZE-1:0]	d, muxd;
   input     			l1clk;
   input      	[SIZE-1:0]	si;
   input   			siclk;
   input   			soclk;

   input   			updateclk, mode, highZ_N;

   reg       	[SIZE-1:0]	q;
   reg       	[SIZE-1:0]	so;

   wire      			l1clk, siclk, soclk, updateclk;


   reg 		[SIZE-1:0]	l1, qm;

   always @(l1clk or siclk or soclk or d or si) begin
     if (!l1clk && !siclk)           l1[SIZE-1:0] <= d[SIZE-1:0];
     if ( l1clk &&  siclk)           l1[SIZE-1:0] <= si[SIZE-1:0];
     if (!l1clk &&  siclk)           l1[SIZE-1:0] <= {SIZE {1'bx}};
     if ( l1clk &&  !soclk)          so[SIZE-1:0] <= l1[SIZE-1:0];
     if ( l1clk &&  siclk && !soclk) so[SIZE-1:0] <= si[SIZE-1:0];    // Flush
   end

   `ifdef INITLATZERO
      initial qm[SIZE-1:0] = {SIZE {1'b0}};
   `endif

   always @(updateclk or l1) begin
     if (updateclk)  qm[SIZE-1:0] <=l1[SIZE-1:0];
   end

   always@(mode or muxd or qm or highZ_N) begin
     if (mode==0)  q[SIZE-1:0] = (qm[SIZE-1:0] && {SIZE {highZ_N}});
     else          q[SIZE-1:0] = muxd[SIZE-1:0];
   end

endmodule

module scm_msff_lat ( latout, q, q_l, so, d, l1clk, si, siclk, soclk);

   parameter SIZE = 1;

   output  [SIZE-1:0]   latout;       
   output  [SIZE-1:0]   so;
   output  [SIZE-1:0]   q;
   output  [SIZE-1:0]   q_l;
   input   [SIZE-1:0]   d;
   input         	l1clk;
   input   [SIZE-1:0]   si;
   input         	siclk;
   input         	soclk;
  

   wire  [SIZE-1:0] so;
   reg [SIZE-1:0] m, s;

   `ifdef SCAN_MODE
     `ifdef FAST_FLUSH
        always @(l1clk or siclk or d ) begin // vcs optimized code

          if (!l1clk && !siclk)        m[SIZE-1:0] <=  d[SIZE-1:0];    // Load master with data
          else if ( l1clk &&  !siclk)  s[SIZE-1:0] <=  m[SIZE-1:0];   // Load slave with master data
          else if (l1clk &&  siclk)   begin   // flush reset
            m[SIZE-1:0] <= {SIZE {1'b0}};
            s[SIZE-1:0] <= {SIZE {1'b0}};
          end
        end
//     `ifdef FAST_FLUSH
//       always @(posedge l1clk or posedge siclk ) begin
//         if (siclk) begin
//           m[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
//           s[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
//         end else begin
//           m[SIZE-1:0] <=  d[SIZE-1:0];
//           s[SIZE-1:0] <=  d[SIZE-1:0];
//         end
//       end

     `else

       always @(l1clk or siclk or soclk or d or si) begin
         if (!l1clk && !siclk)        m[SIZE-1:0] <=  d[SIZE-1:0];    // Load master with data
         else if ( l1clk &&  siclk)   m[SIZE-1:0] <=  si[SIZE-1:0];   // Load master with scan or flush
         else if (!l1clk &&  siclk)   m[SIZE-1:0] <=  {SIZE {1'bx}};   // Conflict between data and scan

         if ( l1clk && !soclk && !siclk)     s[SIZE-1:0] <=  m[SIZE-1:0];   // Load slave with master data
         else if (l1clk && siclk && !soclk)  s[SIZE-1:0] <= si[SIZE-1:0];    // Flush
       end

     `endif // FAST_FLUSH

   `else
      wire [SIZE-1:0] si_unused = si;
      `ifdef INITLATZERO
        initial m[SIZE-1:0] = {SIZE {1'b0}};
        initial s[SIZE-1:0] = {SIZE {1'b0}};
     `endif

      always @(l1clk or d or si or siclk) begin
        if(siclk==0 && l1clk==0) m[SIZE-1:0] =  d[SIZE-1:0];
        else if(siclk && !l1clk) m[SIZE-1:0] = {SIZE {1'bx}};
         if(siclk && l1clk) m[SIZE-1:0] = si[SIZE-1:0];
        if(l1clk && !soclk) s[SIZE-1:0] = m[SIZE-1:0];
      end

    `endif

      assign latout[SIZE-1:0] = m[SIZE-1:0];
      assign so[SIZE-1:0]  =  s[SIZE-1:0];
      assign q[SIZE-1:0]   =  s[SIZE-1:0];
      assign q_l[SIZE-1:0] = ~s[SIZE-1:0];

endmodule // scm_msff_lat

module tisram_msff ( latout, latout_l, so, d, l1clk, si, siclk, soclk );

   parameter SIZE = 1;

   output  [SIZE-1:0]     latout;
   output  [SIZE-1:0]     latout_l;
   output  [SIZE-1:0]     so;

   input   [SIZE-1:0]     d;
   input         	  l1clk;
   input   [SIZE-1:0]     si;
   input       		  siclk;
   input         	  soclk;

   wire [SIZE-1:0] latout, latout_l, so;
   reg [SIZE-1:0] m, s;

   `ifdef SCAN_MODE

      always @(l1clk or siclk or soclk or d or si) begin

        if (!l1clk && !siclk)        m[SIZE-1:0] <=  d[SIZE-1:0];    // Load master with data
        else if ( l1clk &&  siclk)   m[SIZE-1:0] <=  si[SIZE-1:0];    // Load master with scan or flush
        else if (!l1clk &&  siclk)   m[SIZE-1:0] <=  {SIZE {1'bx}};    // Conflict between data and scan

        if ( l1clk && !soclk && !siclk)  s[SIZE-1:0] <=  m[SIZE-1:0];        // Load slave with master data
        else if (l1clk && siclk && !soclk)  s[SIZE-1:0] <= si[SIZE-1:0];    // Flush
      end

   `else
      wire  [SIZE-1:0] si_unused = si;
      wire  soclk_unused = soclk;
	
      `ifdef INITLATZERO
        initial m[SIZE-1:0] = {SIZE {1'b0}};
        initial s[SIZE-1:0] = {SIZE {1'b0}};
      `endif

      always @(l1clk or d or si or siclk) begin
        if(siclk==0 && l1clk==0) m[SIZE-1:0] <=  d[SIZE-1:0];
        if(siclk && !l1clk)      m[SIZE-1:0] <= {SIZE {1'bx}};
        else if(siclk && l1clk)  m[SIZE-1:0] <= si[SIZE-1:0];
      end
    `endif

      assign latout[SIZE-1:0]   =  m[SIZE-1:0];
      assign latout_l[SIZE-1:0] = ~m[SIZE-1:0];
      assign so[SIZE-1:0]       =  s[SIZE-1:0];

endmodule //

module blat ( latout, so, d, l1clk, si, siclk, soclk );

   parameter SIZE = 1;

   output  [SIZE-1:0]     latout;
   output  [SIZE-1:0]     so;

   input   [SIZE-1:0]     d;
   input         	  l1clk;
   input   [SIZE-1:0]     si;
   input       		  siclk;
   input         	  soclk;

   wire [SIZE-1:0] latout, so;
   reg [SIZE-1:0] m, s;

   `ifdef SCAN_MODE
     `ifdef FAST_FLUSH
       always @(posedge l1clk or posedge siclk ) begin
         if (siclk) begin
           m[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
           s[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
         end else begin
           m[SIZE-1:0] <=  d[SIZE-1:0];
           s[SIZE-1:0] <=  d[SIZE-1:0];
         end
       end

     `else

       always @(l1clk or siclk or soclk or d or si) begin

         if (!l1clk && !siclk)        m[SIZE-1:0] <=  d[SIZE-1:0];    // Load master with data
         else if ( l1clk &&  siclk)   m[SIZE-1:0] <=  si[SIZE-1:0];    // Load master with scan or flush
         else if (!l1clk &&  siclk)   m[SIZE-1:0] <=  {SIZE {1'bx}};    // Conflict between data and scan

         if ( l1clk && !soclk && !siclk)  s[SIZE-1:0] <=  m[SIZE-1:0];        // Load slave with master data
         else if (l1clk && siclk && !soclk)  s[SIZE-1:0] <= si[SIZE-1:0];    // Flush
       end

     `endif // FAST_FLUSH

   `else
      wire  [SIZE-1:0] si_unused = si;
      wire  soclk_unused = soclk;
	
      `ifdef INITLATZERO
        initial m[SIZE-1:0] = {SIZE {1'b0}};
        initial s[SIZE-1:0] = {SIZE {1'b0}};
      `endif

      always @(l1clk or d or si or siclk) begin
        if(siclk==0 && l1clk==0) m[SIZE-1:0] <=  d[SIZE-1:0];
        if(siclk && !l1clk)      m[SIZE-1:0] <= {SIZE {1'bx}};
        else if(siclk && l1clk)  m[SIZE-1:0] <= si[SIZE-1:0];
      end
    `endif

      assign latout[SIZE-1:0]   =  m[SIZE-1:0];
      assign so[SIZE-1:0]       =  s[SIZE-1:0];

endmodule //


module dlat ( latout, latout_l, so, d, l1clk, si, siclk, soclk );

   parameter SIZE = 1;


   output       [SIZE-1:0] latout;
   output       [SIZE-1:0] latout_l;
   output       [SIZE-1:0] so;

   input         [SIZE-1:0] d;
   input         l1clk;
   input         [SIZE-1:0] si;
   input         siclk;
   input         soclk;

   wire [SIZE-1:0] latout, latout_l, so;
   reg [SIZE-1:0] m, s;

   `ifdef SCAN_MODE
     `ifdef FAST_FLUSH
       always @(posedge l1clk or posedge siclk ) begin
         if (siclk) begin
           m[SIZE-1:0] <=  {SIZE{1'b1}};  //pseudo flush reset
           s[SIZE-1:0] <=  {SIZE{1'b1}};  //pseudo flush reset
         end else begin
           m[SIZE-1:0] <=  ~d[SIZE-1:0];
           s[SIZE-1:0] <=  ~d[SIZE-1:0];
         end
       end

     `else

       always @(l1clk or siclk or soclk or d or si) begin

         if (!l1clk && !siclk)        m[SIZE-1:0] <=  ~d[SIZE-1:0];    // Load master with data
         else if ( l1clk &&  siclk)   m[SIZE-1:0] <=  ~si[SIZE-1:0];    // Load master with scan or flush
         else if (!l1clk &&  siclk)   m[SIZE-1:0] <=  {SIZE {1'bx}};    // Conflict between data and scan

         if ( l1clk && !soclk && !siclk)     s[SIZE-1:0] <=  m[SIZE-1:0];   // Load slave with master data
         else if (l1clk && !soclk && siclk)  s[SIZE-1:0] <= ~si[SIZE-1:0];  // Flush
       end

     `endif // FAST_FLUSH

      assign so[SIZE-1:0]  =  ~s[SIZE-1:0];

   `else
      wire  [SIZE-1:0] si_unused = si[SIZE-1:0];
      wire soclk_unused = soclk;

      `ifdef INITLATZERO
        initial m[SIZE-1:0] = {SIZE{1'b1}};
        initial s[SIZE-1:0] = {SIZE{1'b1}};
      `endif

      always @(l1clk or d or si or siclk) begin
        if      (!l1clk && !siclk) m[SIZE-1:0] <= ~d[SIZE-1:0];
        else if ( l1clk &&  siclk) m[SIZE-1:0] <= ~si[SIZE-1:0];
        else if (!l1clk &&  siclk) m[SIZE-1:0] <= {SIZE {1'bx}};
      end

      // Don't model slave...since is a don't care for normal sim	
      // below is a hack since we don't really care about s, so use m
      assign so[SIZE-1:0]  =  ~m[SIZE-1:0];
    `endif

      assign latout[SIZE-1:0] = ~m[SIZE-1:0];
      assign latout_l[SIZE-1:0] = m[SIZE-1:0];
               
endmodule 


module dlata ( latout, latout_l, q, q_l, so, d, l1clk, si, siclk, soclk );

   parameter SIZE = 1;

   output      [SIZE-1:0] latout;
   output      [SIZE-1:0] latout_l;
   output      [SIZE-1:0] so;
   output      [SIZE-1:0] q;
   output      [SIZE-1:0] q_l;
   input       [SIZE-1:0]  d;
   input         l1clk;
   input       [SIZE-1:0]  si;
   input         siclk;
   input         soclk;

   wire [SIZE-1:0] so, latout, latout_l;
   reg [SIZE-1:0] m, s;

   `ifdef SCAN_MODE
     `ifdef FAST_FLUSH
       always @(posedge l1clk or posedge siclk ) begin
         if (siclk) begin
           m[SIZE-1:0] <=  {SIZE{1'b1}};  //pseudo flush reset
           s[SIZE-1:0] <=  {SIZE{1'b1}};  //pseudo flush reset
         end else begin
           m[SIZE-1:0] <=  ~d[SIZE-1:0];
           s[SIZE-1:0] <=  ~d[SIZE-1:0];
         end
       end

     `else

       always @(l1clk or siclk or soclk or d or si) begin

         if      (!l1clk && !siclk) m[SIZE-1:0] <=  ~d[SIZE-1:0];   // Load master with data
         else if ( l1clk &&  siclk) m[SIZE-1:0] <=  ~si[SIZE-1:0];  // Load master with scan or flush
         else if (!l1clk &&  siclk) m[SIZE-1:0] <=  {SIZE{1'bx}};   // Conflict between data and scan

         if      (l1clk && !soclk && !siclk)  s[SIZE-1:0] <=  m[SIZE-1:0];  // Load slave with master data
         else if (l1clk && !soclk &&  siclk)  s[SIZE-1:0] <= ~si[SIZE-1:0]; // Flush
       end

     `endif // FAST_FLUSH

   `else
//      wire  [SIZE-1:0] si_unused = si[SIZE-1:0];

      `ifdef INITLATZERO
        initial m[SIZE-1:0] = {SIZE{1'b1}};
        initial s[SIZE-1:0] = {SIZE{1'b1}};
      `endif

      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m[SIZE-1:0] <=  ~d[SIZE-1:0];
        else if ( siclk && !l1clk) m[SIZE-1:0] <= {SIZE {1'bx}};
        else if ( siclk &&  l1clk) m[SIZE-1:0] <= ~si[SIZE-1:0];
        if      ( l1clk && !soclk) s[SIZE-1:0] <= m[SIZE-1:0];
      end

//      always @(l1clk or d or siclk or si) begin
//        if (l1clk == 0) begin
//          if (siclk == 0) begin
//            m[SIZE-1:0] <=  ~d[SIZE-1:0];
//          end
//          else begin
//            m[SIZE-1:0] <= {SIZE{1'bx}};
//          end
//        end
//        else begin // l1clk == 1
//          if (!soclk) s[SIZE-1:0] <= m[SIZE-1:0];
//        end      
//      end

    `endif

      assign latout[SIZE-1:0] = ~m[SIZE-1:0] & {SIZE {l1clk}};
      assign latout_l[SIZE-1:0] = m[SIZE-1:0] & {SIZE {l1clk}};
      assign so[SIZE-1:0]  =  ~s[SIZE-1:0];
      assign q[SIZE-1:0]   =  ~s[SIZE-1:0];
      assign q_l[SIZE-1:0] = s[SIZE-1:0];
               

endmodule 

module new_dlata ( and_clk, mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk );

   parameter SIZE = 1;

   output      [SIZE-1:0] mq;
   output      [SIZE-1:0] mq_l;
   output      [SIZE-1:0] so;
   output      [SIZE-1:0] q;
   output      [SIZE-1:0] q_l;
   input       [SIZE-1:0]  d;
   input         l1clk;
   input	and_clk;
   input       [SIZE-1:0]  si;
   input         siclk;
   input         soclk;

   wire [SIZE-1:0] mq, mq_l, q, q_l, so;
   reg [SIZE-1:0] m, s;

   `ifdef SCAN_MODE
     `ifdef FAST_FLUSH
        always @(l1clk or siclk or d ) begin // vcs optimized code

          if      (!l1clk && !siclk) m[SIZE-1:0] <=  d[SIZE-1:0]; // Load master with data
          else if ( l1clk && !siclk) s[SIZE-1:0] <=  m[SIZE-1:0]; // Load slave with master data
          else if ( l1clk &&  siclk) begin                        // flush reset
            m[SIZE-1:0] <= {SIZE{1'b0}};
            s[SIZE-1:0] <= {SIZE{1'b0}};
            end
        end
//     `ifdef FAST_FLUSH
//       always @(posedge l1clk or posedge siclk ) begin
//         if (siclk) begin
//           m[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
//           s[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
//         end else begin
//           m[SIZE-1:0] <=  d[SIZE-1:0];
//           s[SIZE-1:0] <=  d[SIZE-1:0];
//         end
//       end

     `else

        always @(l1clk or siclk or soclk or d or si) begin

          if      (!l1clk && !siclk) m[SIZE-1:0] <=  d[SIZE-1:0];   // Load master with data
          else if ( l1clk &&  siclk) m[SIZE-1:0] <=  si[SIZE-1:0];  // Load master with scan or flush
          else if (!l1clk &&  siclk) m[SIZE-1:0] <=  {SIZE{1'bx}};  // Conflict between data and scan

          if      (l1clk && !soclk && !siclk)  s[SIZE-1:0] <=  m[SIZE-1:0];  // Load slave with master data
          else if (l1clk && !soclk &&  siclk)  s[SIZE-1:0] <=  si[SIZE-1:0]; // Flush
        end

     `endif // FAST_FLUSH

   `else
//      wire  [SIZE-1:0] si_unused = si[SIZE-1:0];

      `ifdef INITLATZERO
        initial m[SIZE-1:0] = {SIZE{1'b0}};
        initial s[SIZE-1:0] = {SIZE{1'b0}};
      `endif

      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m[SIZE-1:0] <= d[SIZE-1:0];
        else if ( siclk && !l1clk) m[SIZE-1:0] <= {SIZE {1'bx}};
        else if ( siclk &&  l1clk) m[SIZE-1:0] <= si[SIZE-1:0];
        if      ( l1clk && !soclk) s[SIZE-1:0] <= m[SIZE-1:0];
      end

    `endif

    `ifdef MODEL_AND
      assign mq[SIZE-1:0] = m[SIZE-1:0] & {SIZE {(and_clk & l1clk)}};
      assign mq_l[SIZE-1:0] = ~m[SIZE-1:0] & {SIZE {(and_clk & l1clk)}};
    `else
      wire	and_clk_unused = and_clk;
      assign mq[SIZE-1:0] = m[SIZE-1:0];
      assign mq_l[SIZE-1:0] = ~m[SIZE-1:0];
    `endif

      assign so[SIZE-1:0]  =  s[SIZE-1:0];
      assign q[SIZE-1:0]   =  s[SIZE-1:0];
      assign q_l[SIZE-1:0] = ~s[SIZE-1:0];
               
endmodule 

module new_dlat ( latout, latout_l, q, q_l, so, d, l1clk, si, siclk, soclk );

   parameter SIZE = 1;

   output      [SIZE-1:0] latout;
   output      [SIZE-1:0] latout_l;
   output      [SIZE-1:0] so;
   output      [SIZE-1:0] q;
   output      [SIZE-1:0] q_l;
   input       [SIZE-1:0]  d;
   input         l1clk;
   input       [SIZE-1:0]  si;
   input         siclk;
   input         soclk;

   wire [SIZE-1:0] mq, mq_l, q, q_l, so;
   reg [SIZE-1:0] m, s;

   `ifdef SCAN_MODE
     `ifdef FAST_FLUSH
       always @(posedge l1clk or posedge siclk ) begin
         if (siclk) begin
           m[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
           s[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
         end else begin
           m[SIZE-1:0] <=  d[SIZE-1:0];
           s[SIZE-1:0] <=  d[SIZE-1:0];
         end
       end

     `else

       always @(l1clk or siclk or soclk or d or si) begin

         if      (!l1clk && !siclk) m[SIZE-1:0] <=  d[SIZE-1:0];   // Load master with data
         else if ( l1clk &&  siclk) m[SIZE-1:0] <=  si[SIZE-1:0];  // Load master with scan or flush
         else if (!l1clk &&  siclk) m[SIZE-1:0] <=  {SIZE{1'bx}};   // Conflict between data and scan

         if      (l1clk && !soclk && !siclk)  s[SIZE-1:0] <=  m[SIZE-1:0];  // Load slave with master data
         else if (l1clk && !soclk &&  siclk)  s[SIZE-1:0] <=  si[SIZE-1:0]; // Flush
       end

     `endif // FAST_FLUSH

   `else
//      wire  [SIZE-1:0] si_unused = si[SIZE-1:0];

      `ifdef INITLATZERO
        initial m[SIZE-1:0] = {SIZE{1'b0}};
        initial s[SIZE-1:0] = {SIZE{1'b0}};
      `endif

      always @(l1clk or d or si or siclk) begin
        if      (!siclk && !l1clk) m[SIZE-1:0] <= d[SIZE-1:0];
        else if ( siclk && !l1clk) m[SIZE-1:0] <= {SIZE {1'bx}};
        else if ( siclk &&  l1clk) m[SIZE-1:0] <= si[SIZE-1:0];
        if      ( l1clk && !soclk) s[SIZE-1:0] <= m[SIZE-1:0];
      end

    `endif

    `ifdef MODEL_AND
      assign latout[SIZE-1:0] = m[SIZE-1:0] & {SIZE {l1clk}};
      assign latout_l[SIZE-1:0] = ~m[SIZE-1:0] & {SIZE {l1clk}};
    `else
      assign latout[SIZE-1:0] = m[SIZE-1:0];
      assign latout_l[SIZE-1:0] = ~m[SIZE-1:0];
    `endif

      assign so[SIZE-1:0]  =  s[SIZE-1:0];
      assign q[SIZE-1:0]   =  s[SIZE-1:0];
      assign q_l[SIZE-1:0] = ~s[SIZE-1:0];
               
endmodule 

module ccx_mac_a (l1clk0,l1clk1,siclk,soclk,grant_x,data_a,data_x_l,qsel0_buf,shift_buf,si,so);

parameter SIZE = 10;

input     l1clk0;
input     l1clk1;
input     siclk;
input     soclk;
input     grant_x;
input [SIZE-1:0] data_a;

input            qsel0_buf;
input            shift_buf;

output [SIZE-1:0] data_x_l;

input             si;
output            so;

wire [SIZE-1:0]   msff1_so,msff1_si,msff0_so,msff0_si;
wire [SIZE-1:0]   q1;
wire [SIZE-1:0]   q0;
wire [SIZE-1:0]   q0_in;


dff #(SIZE) msff1 
  (
   .l1clk(l1clk1),
   .siclk(siclk),
   .soclk(soclk),
   .d(data_a[SIZE-1:0]),
   .si(msff1_si[SIZE-1:0]),
   .so(msff1_so[SIZE-1:0]),
   .q(q1[SIZE-1:0])
   );

assign q0_in[SIZE-1:0] = ({SIZE{qsel0_buf}} & data_a[SIZE-1:0]) |
			             ({SIZE{shift_buf}} & q1[SIZE-1:0]);


dff #(SIZE) msff0 
  (
   .l1clk(l1clk0),
   .siclk(siclk),
   .soclk(soclk),
   .d(q0_in[SIZE-1:0]),
   .si(msff0_si[SIZE-1:0]),
   .so(msff0_so[SIZE-1:0]),
   .q(q0[SIZE-1:0])
   );

assign data_x_l[SIZE-1:0] = ~(q0[SIZE-1:0] & {SIZE{grant_x}});

//assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:0],si};
//assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]};
//assign so = msff0_so[SIZE-1];

//assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:0],si};
//assign msff1_si[9:5] = {msff0_so[SIZE-2:5],si};
//assign msff1_si[0] = msff0_so[SIZE-1];
//assign msff1_si[4:1] = msff0_so[3:0];
//assign so = msff0_so[4];

assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:5],si,msff0_so[3:0],msff0_so[SIZE-1]};
assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]};
assign so = msff0_so[4];

endmodule

module ccx_mac_b (l1clk0,l1clk1,siclk,soclk,grant_x,data_a,data_prev_x_l,data_x_l,qsel0_buf,shift_buf,si,so);

parameter SIZE = 10;

input     l1clk0;
input     l1clk1;
input     siclk;
input     soclk;
input     grant_x;
input [SIZE-1:0] data_a;
input [SIZE-1:0] data_prev_x_l;

input            qsel0_buf;
input            shift_buf;

output [SIZE-1:0] data_x_l;

input             si;
output            so;

wire [SIZE-1:0]   msff1_so,msff1_si,msff0_so,msff0_si;
wire [SIZE-1:0]   q1;
wire [SIZE-1:0]   q0;
wire [SIZE-1:0]   q0_in,x4,x5;


dff #(SIZE) msff1 
  (
   .l1clk(l1clk1),
   .siclk(siclk),
   .soclk(soclk),
   .d(data_a[SIZE-1:0]),
   .si(msff1_si[SIZE-1:0]),
   .so(msff1_so[SIZE-1:0]),
   .q(q1[SIZE-1:0])
   );

assign q0_in[SIZE-1:0] = ({SIZE{qsel0_buf}} & data_a[SIZE-1:0]) |
			             ({SIZE{shift_buf}} & q1[SIZE-1:0]);


dff #(SIZE) msff0 
  (
   .l1clk(l1clk0),
   .siclk(siclk),
   .soclk(soclk),
   .d(q0_in[SIZE-1:0]),
   .si(msff0_si[SIZE-1:0]),
   .so(msff0_so[SIZE-1:0]),
   .q(q0[SIZE-1:0])
   );

assign x4[SIZE-1:0] = ~(q0[SIZE-1:0] & {SIZE{grant_x}});
assign x5[SIZE-1:0] = ~(x4[SIZE-1:0] & data_prev_x_l[SIZE-1:0]);
assign data_x_l[SIZE-1:0] = ~x5[SIZE-1:0];

//assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:0],si};
//assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]};
//assign so = msff0_so[SIZE-1];

assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:5],si,msff0_so[3:0],msff0_so[SIZE-1]};
assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]};
assign so = msff0_so[4];

endmodule

module ccx_mac_c (l1clk0,l1clk1,siclk,soclk,grant_x,data_a,data_crit_x_l,data_ncrit_x_l,data_x_l,qsel0_buf,shift_buf,si,so);

parameter SIZE = 10;

input     l1clk0;
input     l1clk1;
input     siclk;
input     soclk;
input     grant_x;
input [SIZE-1:0] data_a;
input [SIZE-1:0] data_crit_x_l;
input [SIZE-1:0] data_ncrit_x_l;

input            qsel0_buf;
input            shift_buf;

output [SIZE-1:0] data_x_l;

input             si;
output            so;

wire [SIZE-1:0]   msff1_so,msff1_si,msff0_so,msff0_si;
wire [SIZE-1:0]   q1;
wire [SIZE-1:0]   q0;
wire [SIZE-1:0]   q0_in,x4,x5;


dff #(SIZE) msff1 
  (
   .l1clk(l1clk1),
   .siclk(siclk),
   .soclk(soclk),
   .d(data_a[SIZE-1:0]),
   .si(msff1_si[SIZE-1:0]),
   .so(msff1_so[SIZE-1:0]),
   .q(q1[SIZE-1:0])
   );

assign q0_in[SIZE-1:0] = ({SIZE{qsel0_buf}} & data_a[SIZE-1:0]) |
			             ({SIZE{shift_buf}} & q1[SIZE-1:0]);


dff #(SIZE) msff0 
  (
   .l1clk(l1clk0),
   .siclk(siclk),
   .soclk(soclk),
   .d(q0_in[SIZE-1:0]),
   .si(msff0_si[SIZE-1:0]),
   .so(msff0_so[SIZE-1:0]),
   .q(q0[SIZE-1:0])
   );

assign x4[SIZE-1:0] = ~(q0[SIZE-1:0] & {SIZE{grant_x}});
assign x5[SIZE-1:0] = ~(x4[SIZE-1:0] & data_crit_x_l[SIZE-1:0] & data_ncrit_x_l[SIZE-1:0]);
assign data_x_l[SIZE-1:0] = ~x5[SIZE-1:0];

//assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:0],si};
//assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]};
//assign so = msff0_so[SIZE-1];

assign msff1_si[SIZE-1:0] = {msff0_so[SIZE-2:5],si,msff0_so[3:0],msff0_so[SIZE-1]};
assign msff0_si[SIZE-1:0] = {msff1_so[SIZE-1:0]};
assign so = msff0_so[4];

endmodule

// new FAST_FLUSH
// new dff from RM with init to zero in scan section

`ifdef FPGA
`else
module dff ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
// 4-25-2005 added initlatzero to scan_mode


   parameter SIZE = 1;

   output    [SIZE-1:0]    q;
   output    [SIZE-1:0]    so;

   input     [SIZE-1:0]    d;
   input                   l1clk;
   input     [SIZE-1:0]    si;
   input                   siclk;
   input                   soclk;

             reg       [SIZE-1:0] q;
             wire      [SIZE-1:0] so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg       [SIZE-1:0] l1;

            `ifdef INITLATZERO
              initial l1[SIZE-1:0] = {SIZE{1'b0}};
              initial  q[SIZE-1:0] = {SIZE{1'b0}};
            `endif

             `ifdef FAST_FLUSH
                always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q[SIZE-1:0] <=  {SIZE{1'b0}};  //pseudo flush reset
                  end else begin
                    q[SIZE-1:0] <=  d[SIZE-1:0];
                  end
                end
             `else
              always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1[SIZE-1:0] <=   d[SIZE-1:0];    // Load master with data
               else if ( l1clk &&  siclk)           l1[SIZE-1:0] <=  si[SIZE-1:0];    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1[SIZE-1:0] <=  {SIZE{1'bx}};    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q[SIZE-1:0] <=  l1[SIZE-1:0];    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q[SIZE-1:0] <=  si[SIZE-1:0];    // Flush
              end
              `endif

        `else
              wire [SIZE-1:0] si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused[SIZE-1:0] = si[SIZE-1:0];
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


              `ifdef INITLATZERO
                initial q[SIZE-1:0] = {SIZE{1'b0}};
              `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q[SIZE-1:0] <=  d[SIZE-1:0];
                else                  q[SIZE-1:0] <= {SIZE{1'bx}};
               end
        `endif
              
         assign so[SIZE-1:0] = q[SIZE-1:0];

endmodule // dff
`endif // `ifdef FPGA


module dff_jtag ( q, so, d, l1clk, si, siclk, soclk, reset, updateclk );

   // modified 2/15/05 gfg as per Shawn

   parameter SIZE = 1;
 
   output [SIZE-1:0]    q;
   output  [SIZE-1:0]      so;

   input  [SIZE-1:0]       d;
   input     l1clk;
   input [SIZE-1:0]     si;
   input   siclk;
   input   soclk;
   input   reset;
   input   updateclk;

   reg  [SIZE-1:0]     q;
   reg  [SIZE-1:0]     so;
   reg  [SIZE-1:0]   l1;
   wire      l1clk, siclk, soclk, updateclk;

   always @(l1clk or siclk or soclk or d or si or reset)
     begin
       if (!l1clk && !siclk)                     l1[SIZE-1:0] <= d[SIZE-1:0];
       else if ( l1clk &&  siclk)                l1[SIZE-1:0] <= si[SIZE-1:0];
       else if (!l1clk &&  siclk)                l1[SIZE-1:0] <= {SIZE{1'bx}};
       if ( reset )                              so[SIZE-1:0] <= {SIZE{1'b0}};
       if ( l1clk && !siclk && !soclk && !reset) so[SIZE-1:0] <= l1[SIZE-1:0];
       if ( l1clk &&  siclk && !soclk && !reset) so[SIZE-1:0] <= si[SIZE-1:0];
     end

   `ifdef INITLATZERO
      initial q[SIZE-1:0]  = {SIZE{1'b0}};
   `endif

   always@(updateclk or reset or l1)
     begin
       if(reset) q[SIZE-1:0]  <= {SIZE{1'b0}};
       else if(updateclk)  q[SIZE-1:0] <= l1[SIZE-1:0];
     end

endmodule // dff_jtag


// parameterized sim sections for the common sunv macros besides muxes and flops

module and2 (out, in0, in1);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;


   assign out[SIZE-1:0] = in0[SIZE-1:0] & in1[SIZE-1:0];

endmodule

`ifdef FPGA
`else
module and3 (out, in0, in1, in2);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input [SIZE-1:0]  in2;


   assign out[SIZE-1:0] = in0[SIZE-1:0] & in1[SIZE-1:0] & in2[SIZE-1:0];

endmodule

module and4 (out, in0, in1, in2, in3);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input [SIZE-1:0]  in2;
   input [SIZE-1:0]  in3;


   assign out[SIZE-1:0] = in0[SIZE-1:0] & in1[SIZE-1:0] & in2[SIZE-1:0] & in3[SIZE-1:0];

endmodule

module nand2 (out, in0, in1);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;


   assign out[SIZE-1:0] = ~(in0[SIZE-1:0] & in1[SIZE-1:0]);

endmodule

module nand3 (out, in0, in1, in2);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input [SIZE-1:0]  in2;


   assign out[SIZE-1:0] = ~(in0[SIZE-1:0] & in1[SIZE-1:0] & in2[SIZE-1:0]);

endmodule

`endif // `ifdef FPGA

module nand4 (out, in0, in1, in2, in3);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input [SIZE-1:0]  in2;
   input [SIZE-1:0]  in3;


   assign out[SIZE-1:0] = ~(in0[SIZE-1:0] & in1[SIZE-1:0] & in2[SIZE-1:0] & in3[SIZE-1:0]);

endmodule

module or2 (out, in0, in1);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;


   assign out[SIZE-1:0] = in0[SIZE-1:0] | in1[SIZE-1:0];

endmodule

module or3 (out, in0, in1, in2);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input [SIZE-1:0]  in2;


   assign out[SIZE-1:0] = in0[SIZE-1:0] | in1[SIZE-1:0] | in2[SIZE-1:0];

endmodule

`ifdef FPGA
`else
module nor2 (out, in0, in1);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;


   assign out[SIZE-1:0] = ~(in0[SIZE-1:0] | in1[SIZE-1:0]);

endmodule

module nor3 (out, in0, in1, in2);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input [SIZE-1:0]  in2;


   assign out[SIZE-1:0] = ~(in0[SIZE-1:0] | in1[SIZE-1:0] | in2[SIZE-1:0]);

endmodule

`endif // `ifdef FPGA

module xor2 ( out, in0, in1 );

   parameter SIZE = 1;

   input     [SIZE-1:0] in0, in1;
   output    [SIZE-1:0] out;

   assign out = in0 ^ in1 ;

endmodule // xor2
				

module xor3 (out, in0, in1, in2);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input [SIZE-1:0]  in2;


   assign out[SIZE-1:0] = in0[SIZE-1:0] ^ in1[SIZE-1:0] ^ in2[SIZE-1:0];

endmodule

module xnor2 ( out, in0, in1 );

   parameter SIZE = 1;

   input     [SIZE-1:0] in0, in1;
   output    [SIZE-1:0] out;

   assign out = ~(in0 ^ in1) ;

endmodule // xnor2

module xnor3 (out, in0, in1, in2);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input [SIZE-1:0]  in2;


   assign out[SIZE-1:0] = ~(in0[SIZE-1:0] ^ in1[SIZE-1:0] ^ in2[SIZE-1:0]);

endmodule

`ifdef FPGA
`else

module buff (out, in);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in;

   assign out[SIZE-1:0] = in[SIZE-1:0];
   

endmodule

module inv (out, in);
   parameter	     SIZE=1;


   output [SIZE-1:0] out;
   input [SIZE-1:0]  in;

   assign out[SIZE-1:0] = ~in[SIZE-1:0];
endmodule

`endif // `ifdef FPGA


module cla(out, cout, in0, in1, cin);
   parameter	     SIZE=1;

   output [SIZE-1:0] out;
   output	     cout;
   input [SIZE-1:0]  in0;
   input [SIZE-1:0]  in1;
   input	     cin;
   

   assign {cout,out[SIZE-1:0]} = ({1'b0,in0[SIZE-1:0]} + {1'b0,in1[SIZE-1:0]} + {{SIZE{1'b0}},cin});
   
endmodule

module incr(out, cout, in, cin);
   parameter	     SIZE=1;

   output [SIZE-1:0] out;
   output	     cout;
   input [SIZE-1:0]  in;
   input	     cin;

   assign {cout,out[SIZE-1:0]} = ({1'b0,in[SIZE-1:0]} + {{SIZE{1'b0}},cin});
   
endmodule

module cmp(out, in0, in1);
   parameter	    SIZE=1;
   
   output	    out;
   input [SIZE-1:0] in0;
   input [SIZE-1:0] in1;
   
   assign out = (in0[SIZE-1:0] == in1[SIZE-1:0]);

endmodule

module zero(out, in);
   parameter	    SIZE=1;
   
   output	    out;
   input [SIZE-1:0] in;
   
   assign out = (in[SIZE-1:0] == {SIZE{1'b0}});

endmodule


module prty(out, in);
   parameter	    SIZE=1;
   
   output	    out;
   input [SIZE-1:0] in;
   
   assign out = ^in[SIZE-1:0];

endmodule 


module csa32(sum, carry, in0, in1, in2);
   parameter		   SIZE=1;
   
   input [SIZE-1:0]	   in0;
   input [SIZE-1:0]	   in1;
   input [SIZE-1:0]	   in2;
   output [SIZE-1:0]	   carry;
   output [SIZE-1:0]	   sum;
   
   assign carry[SIZE-1:0]  = ((in0[SIZE-1:0]  & in1[SIZE-1:0] ) | 
			      (in0[SIZE-1:0]  & in2[SIZE-1:0] ) | 
			      (in1[SIZE-1:0] & in2[SIZE-1:0]));
   
   assign sum[SIZE-1:0]  = (in0[SIZE-1:0] ^ in1[SIZE-1:0] ^ in2[SIZE-1:0]);
   
   
endmodule


module csa42(sum, carry, cout, cin, in0, in1, in2, in3);
   parameter	     SIZE=1;
   
   input [SIZE-1:0]  in0; 
   input [SIZE-1:0]  in1; 
   input [SIZE-1:0]  in2; 
   input [SIZE-1:0]  in3;
   input	     cin;
   output	     cout; 
   output [SIZE-1:0] carry; 
   output [SIZE-1:0] sum; 
   
   
   wire [SIZE-1:0]   i0_xor_i1 = (in0[SIZE-1:0] ^ in1[SIZE-1:0]);
   
   wire [SIZE-1:0]   co        = ((in0[SIZE-1:0] & in1[SIZE-1:0]) |
				  (in0[SIZE-1:0] & in2[SIZE-1:0]) |
				  (in1[SIZE-1:0] & in2[SIZE-1:0]));
   
   assign cout              = co[SIZE-1];

   wire [SIZE:0] cint      = { co[SIZE-1:0], cin };

   wire cint_unused;

   assign cint_unused = cint[SIZE];


   assign carry[SIZE-1:0]     = ((~i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] &  in3[SIZE-1:0] &  cint[SIZE-1:0]) |
				 (~i0_xor_i1[SIZE-1:0] &  in2[SIZE-1:0] & ~in3[SIZE-1:0] &  cint[SIZE-1:0]) |
				 (~i0_xor_i1[SIZE-1:0] &  in2[SIZE-1:0] &  in3[SIZE-1:0]                ) |
				 ( i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & ~in3[SIZE-1:0] &  cint[SIZE-1:0]) |
				 ( i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] &  in3[SIZE-1:0]                ) |
				 ( i0_xor_i1[SIZE-1:0] &  in2[SIZE-1:0] &  in3[SIZE-1:0] &  cint[SIZE-1:0]));
   
   
   assign sum[SIZE-1:0]       = ((~i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & ~in3[SIZE-1:0] &  cint[SIZE-1:0]) |
				 (~i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] &  in3[SIZE-1:0] & ~cint[SIZE-1:0]) |
				 (~i0_xor_i1[SIZE-1:0] &  in2[SIZE-1:0] & ~in3[SIZE-1:0] & ~cint[SIZE-1:0]) |
				 (~i0_xor_i1[SIZE-1:0] &  in2[SIZE-1:0] &  in3[SIZE-1:0] &  cint[SIZE-1:0]) |
				 ( i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] & ~in3[SIZE-1:0] & ~cint[SIZE-1:0]) |
				 ( i0_xor_i1[SIZE-1:0] & ~in2[SIZE-1:0] &  in3[SIZE-1:0] &  cint[SIZE-1:0]) |
				 ( i0_xor_i1[SIZE-1:0] &  in2[SIZE-1:0] & ~in3[SIZE-1:0] &  cint[SIZE-1:0]) |
				 ( i0_xor_i1[SIZE-1:0] &  in2[SIZE-1:0] &  in3[SIZE-1:0] & ~cint[SIZE-1:0]));

endmodule // csa42

module andmux8(out, in7,in6,in5,in4,in3,in2,in1,in0,
	            en7,en6,en5,en4,en3,en2,en1,en0,
	            sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0);

   parameter	    SIZE=1;
   
   output [SIZE-1:0] out;
   input [SIZE-1:0] in7;
   input [SIZE-1:0] in6;
   input [SIZE-1:0] in5;
   input [SIZE-1:0] in4;
   input [SIZE-1:0] in3;
   input [SIZE-1:0] in2;
   input [SIZE-1:0] in1;
   input [SIZE-1:0] in0;
   input [SIZE-1:0] en7;
   input [SIZE-1:0] en6;
   input [SIZE-1:0] en5;
   input [SIZE-1:0] en4;
   input [SIZE-1:0] en3;
   input [SIZE-1:0] en2;
   input [SIZE-1:0] en1;
   input [SIZE-1:0] en0;
   input sel7;
   input sel6;
   input sel5;
   input sel4;
   input sel3;
   input sel2;
   input sel1;
   input sel0;

assign out =        ({SIZE{sel0}} & in0 & en0) |
                    ({SIZE{sel1}} & in1 & en1) |
                    ({SIZE{sel2}} & in2 & en2) |
                    ({SIZE{sel3}} & in3 & en3) |
                    ({SIZE{sel4}} & in4 & en4) |
                    ({SIZE{sel5}} & in5 & en5) |
                    ({SIZE{sel6}} & in6 & en6) |
                    ({SIZE{sel7}} & in7 & en7);

endmodule 

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cl_sc1.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module cl_sc1_msffmin_fp_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff


module cl_sc1_msffmin_fp_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             reg 	l1;

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_32x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_1x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_30ps_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
        `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff


module cl_sc1_msffmin_fp_30ps_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_30ps_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_30ps_32x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_30ps_1x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff

module cl_sc1_msffmin_fp_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_fp_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_30ps_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
        `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff


module cl_sc1_msffmin_30ps_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_30ps_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_30ps_32x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_30ps_1x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
 module cl_sc1_clken_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk, clken);
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
// created by xl on 3/18


    output     q;
    output       so;

    input         d;
    input     l1clk;
    input      si;
    input   siclk;
    input   soclk;
    input   clken;
              reg       q;
              wire     so;
              wire      l1clk, siclk, soclk;

         `ifdef SCAN_MODE

              reg l1;

              always @(l1clk or siclk or soclk or d or si)
               begin
                     if (!l1clk && !siclk)           l1 <= (d & clken ) | (q & !clken);    // Load master with data
                else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
                else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

                else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                     if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
               end


         `else
               wire  si_unused;
               wire siclk_unused;
               wire soclk_unused;
               assign si_unused = si;
               assign siclk_unused        = siclk;
               assign soclk_unused        = soclk;


           `ifdef INITLATZERO

                 initial q = 1'b0;
           `endif

               always @(posedge l1clk)
                begin
                 if (!siclk && !soclk) q <=  (d & clken ) | (q & !clken);
                 else                  q <= 1'bx;
                end
         `endif

          assign so = q;

endmodule
module cl_sc1_msffmin_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_bsac_cell_4x(q, so, d, l1clk, si, siclk, soclk, updateclk,
                           ac_mode, ac_test_signal);
   output     q;
   output       so;

   input         d, ac_test_signal;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   updateclk, ac_mode;

             reg       q;
             reg       so;
             wire      l1clk, siclk, soclk, updateclk;


             reg l1, qm;

             always @(l1clk or siclk or soclk or d or si)
              begin
    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
    if ( l1clk &&  siclk)           l1 <= si;    // Load master with
                                                 // scan or flush
    if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between
                                                   // data and scan
    if ( l1clk &&  !soclk)          so <= l1;     // Load slave with
                                                  // master data
    if ( l1clk &&  siclk && !soclk) so <= si;    // Flush
              end

                initial qm = 1'b0;

           always@(updateclk or l1)
                begin
                if(updateclk)  qm <=l1;
                end
always@(ac_mode or qm or ac_test_signal)
        begin
        if(ac_mode==0)  q=qm;
        else         q=qm ^ ac_test_signal;
        end
endmodule
module cl_sc1_blatch_4x ( latout, so, d, l1clk, si, siclk, soclk);

   output       latout;
   output       so;
   input         d;
   input         l1clk;
   input         si;
   input         siclk;
   input         soclk;
 

   wire  so;
   reg s, m;

   `ifdef SCAN_MODE

      always @(l1clk or siclk or soclk or d or si) begin

        if (!l1clk && !siclk)        m <=  d;    // Load master with data
        else if ( l1clk &&  siclk)   m <=  si;    // Load master with scan or flush
        else if (!l1clk &&  siclk)   m <=  1'bx;    // Conflict between data and scan

        if ( l1clk && !soclk && !siclk)  s <=  m;   // Load slave with master data
        else if (l1clk && siclk && !soclk)  s <= si;    // Flush
      end

   `else
      wire  si_unused = si;
`ifdef INITLATZERO


      initial m = 1'b0;
     `endif


      always @(l1clk or d or si or siclk) begin
        if(siclk==0 && l1clk==0) m =  d;
        else if(siclk && !l1clk)                m = 1'bx;
         if(siclk && l1clk) m = si;
        if(l1clk && !soclk) s = m;
      end

    `endif

      assign latout = m;
      assign so  =  s;


endmodule 


 module cl_sc1_alatch_4x ( q, so, d, l1clk, si, siclk, soclk, se );


   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   se;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	

             reg l1;

             always @(l1clk or siclk or soclk or d or si or se)
              begin

                    if (siclk)           l1 <= si;    // Load master with scan or flush

		if(se && !soclk && l1clk && siclk) q <= si;
                else    if ( se && !soclk && l1clk)  q <= l1;    
                    else if ( !soclk && l1clk)  q <= d;
              end


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif


         assign so = q;

endmodule // dff
 module cl_sc1_clken_msff_4x ( q, so, d, l1clk, si, siclk, soclk, clken);
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
// created by xl on 3/18


    output     q;
    output       so;

    input         d;
    input     l1clk;
    input      si;
    input   siclk;
    input   soclk;
    input   clken;
              reg       q;
              wire     so;
              wire      l1clk, siclk, soclk;

         `ifdef SCAN_MODE

              reg l1;

              always @(l1clk or siclk or soclk or d or si)
               begin
                     if (!l1clk && !siclk)           l1 <= (d & clken ) | (q & !clken);    // Load master with data
                else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
                else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

                else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                     if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
               end


         `else
               wire  si_unused;
               wire siclk_unused;
               wire soclk_unused;
               assign si_unused = si;
               assign siclk_unused        = siclk;
               assign soclk_unused        = soclk;


           `ifdef INITLATZERO

                 initial q = 1'b0;
           `endif

               always @(posedge l1clk)
                begin
                 if (!siclk && !soclk) q <=  (d & clken ) | (q & !clken);
                 else                  q <= 1'bx;
                end
         `endif

          assign so = q;

endmodule
 
 module cl_sc1_msff_arst_4x ( q, so, d, l1clk, si, siclk, soclk, reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;

             always @(l1clk or siclk or soclk or d or si or reset)
               begin
                if (reset ) 			l1 <= 1'b0;
                else if (!l1clk && !siclk)      l1 <= d;
                else if ( l1clk &&  siclk)      l1 <= si;
                else if (!l1clk &&  siclk)      l1 <= 1'bx;

                if  (reset)                           q <= 1'b0;
                else if ( l1clk && !siclk && !soclk)  q <= l1;
                else if ( l1clk &&  siclk && !soclk)  q <= si;

               end

   
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk or posedge reset)
               begin
                
                if ( reset) q <= 1'b0;
                else if (!siclk && !soclk ) q <=  d;
                else             q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
 

module cl_sc1_aomux2_12x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_sc1_aomux2_16x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_sc1_aomux2_1x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_sc1_aomux2_2x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_sc1_aomux2_4x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_sc1_aomux2_6x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_sc1_aomux2_8x (
in0,
in1,
sel0,
sel1,
out
);
input 	in0;
input 	in1;
input 	sel0;
input 	sel1;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1));
`endif


endmodule
module cl_sc1_aomux3_12x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_sc1_aomux3_16x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_sc1_aomux3_1x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_sc1_aomux3_2x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_sc1_aomux3_4x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_sc1_aomux3_6x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_sc1_aomux3_8x (
in0,
in1,
in2,
sel0,
sel1,
sel2,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	sel0;
input 	sel1;
input 	sel2;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2));
`endif

endmodule
module cl_sc1_aomux4_12x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_sc1_aomux4_16x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_sc1_aomux4_1x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_sc1_aomux4_2x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_sc1_aomux4_4x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_sc1_aomux4_6x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_sc1_aomux4_8x (
in0,
in1,
in2,
in3,
sel0,
sel1,
sel2,
sel3,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3));
`endif

endmodule
module cl_sc1_aomux5_12x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_sc1_aomux5_16x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_sc1_aomux5_1x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_sc1_aomux5_2x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_sc1_aomux5_4x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_sc1_aomux5_6x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_sc1_aomux5_8x (
in0,
in1,
in2,
in3,
in4,
sel0,
sel1,
sel2,
sel3,
sel4,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4));
`endif

endmodule
module cl_sc1_aomux6_12x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux6_16x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux6_1x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux6_2x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux6_4x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux6_6x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux6_8x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux6_by2_1x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux6_by2_2x (
in0,
in1,
in2,
in3,
in4,
in5,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5));
`endif

endmodule
module cl_sc1_aomux7_12x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux7_16x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux7_1x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux7_2x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux7_4x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux7_6x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux7_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux7_by2_1x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux7_by2_2x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6));
`endif

endmodule
module cl_sc1_aomux8_12x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_sc1_aomux8_16x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_sc1_aomux8_1x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_sc1_aomux8_2x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_sc1_aomux8_4x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_sc1_aomux8_6x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_sc1_aomux8_8x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_sc1_aomux8_by2_1x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module cl_sc1_aomux8_by2_2x (
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
sel0,
sel1,
sel2,
sel3,
sel4,
sel5,
sel6,
sel7,
out
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input 	in4;
input 	in5;
input 	in6;
input 	in7;
input 	sel0;
input 	sel1;
input 	sel2;
input 	sel3;
input 	sel4;
input 	sel5;
input 	sel6;
input 	sel7;
output  out;

`ifdef LIB
assign out = ((sel0 & in0) |
	      (sel1 & in1) |
	      (sel2 & in2) |
	      (sel3 & in3) |
	      (sel4 & in4) |
	      (sel5 & in5) |
	      (sel6 & in6) |
	      (sel7 & in7));
`endif
		

endmodule
module	cl_sc1_l1hdr_12x (
		 l2clk,
		 se,
		 pce,
		 pce_ov,
		 stop,	
		 l1clk
	
		);


   input	l2clk;		// level 2 clock, from clock grid
   input	se;		// Scan Enable
   input	pce;             // Clock enable for local power savings
   input	pce_ov;        // TCU sourced clock enable override for testing
   input	stop;           // TCU/CCU sourced clock stop for debug 
    output	l1clk;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
   `else
`ifdef LIB
   reg	l1en;
 
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif
  

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority


`endif
`endif

endmodule

module	cl_sc1_l1hdr_16x (
		 l2clk,
		 se,
		 pce,
		 pce_ov,
		 stop,
		 l1clk
		);
// RFM  05/21/2004


   input	l2clk;		// level 2 clock, from clock grid
   input	se;		// Scan Enable
   input	pce;             // Clock enable for local power savings
   input	pce_ov;        // TCU sourced clock enable override for testing
   input	stop;           // TCU/CCU sourced clock stop for debug 
   output	l1clk;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
   `else
`ifdef LIB
   reg	l1en;
  
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority


`endif
`endif

endmodule
module	cl_sc1_l1hdr_24x (
		 l2clk,
		 se,
		 pce,
		 pce_ov,
		 stop,
		 l1clk
		);
// RFM  05/21/2004


   input	l2clk;		// level 2 clock, from clock grid
   input	se;		// Scan Enable
   input	pce;             // Clock enable for local power savings
   input	pce_ov;        // TCU sourced clock enable override for testing
   input	stop;           // TCU/CCU sourced clock stop for debug 
   output	l1clk;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
   `else
`ifdef LIB
   reg	l1en;
 

`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority


`endif
`endif

endmodule
module	cl_sc1_l1hdr_32x (
		 l2clk,
		 se,
		 pce,
		 pce_ov,
		 stop,
		 l1clk
		);
// RFM  05/21/2004


   input	l2clk;		// level 2 clock, from clock grid
   input	se;		// Scan Enable
   input	pce;             // Clock enable for local power savings
   input	pce_ov;        // TCU sourced clock enable override for testing
   input	stop;           // TCU/CCU sourced clock stop for debug 
   output	l1clk;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
   `else
`ifdef LIB
   reg	l1en;
 
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

  
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority


`endif
`endif

endmodule

module	cl_sc1_l1hdr_4x (
		 l2clk,
		 se,
		 pce,
		 pce_ov,
		 stop,
		 l1clk
		);
// RFM  05/21/2004


   input	l2clk;		// level 2 clock, from clock grid
   input	se;		// Scan Enable
   input	pce;             // Clock enable for local power savings
   input	pce_ov;        // TCU sourced clock enable override for testing
   input	stop;           // TCU/CCU sourced clock stop for debug 
   output	l1clk;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
   `else
`ifdef LIB
   reg	l1en;
  
`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

 
   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority


`endif
`endif

endmodule
module	cl_sc1_l1hdr_48x (
		 l2clk,
		 se,
		 pce,
		 pce_ov,
		 stop,	
		 l1clk
	
		);


   input	l2clk;		// level 2 clock, from clock grid
   input	se;		// Scan Enable
   input	pce;             // Clock enable for local power savings
   input	pce_ov;        // TCU sourced clock enable override for testing
   input	stop;           // TCU/CCU sourced clock stop for debug 
    output	l1clk;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
   `else
`ifdef LIB
   reg	l1en;
 

`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority


`endif
`endif

endmodule
module	cl_sc1_l1hdr_64x (
		 l2clk,
		 se,
		 pce,
		 pce_ov,
		 stop,	
		 l1clk
	
		);


   input	l2clk;		// level 2 clock, from clock grid
   input	se;		// Scan Enable
   input	pce;             // Clock enable for local power savings
   input	pce_ov;        // TCU sourced clock enable override for testing
   input	stop;           // TCU/CCU sourced clock stop for debug 
    output	l1clk;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
   `else
`ifdef LIB
   reg	l1en;
 

`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority


`endif
`endif

endmodule

`ifdef FPGA
`else
module	cl_sc1_l1hdr_8x (
		 l2clk,
		 se,
		 pce,
		 pce_ov,
		 stop,
		 l1clk
		);
// RFM  05/21/2004


   input	l2clk;		// level 2 clock, from clock grid
   input	se;		// Scan Enable
   input	pce;             // Clock enable for local power savings
   input	pce_ov;        // TCU sourced clock enable override for testing
   input	stop;           // TCU/CCU sourced clock stop for debug 
   output	l1clk;
`ifdef FORMAL_TOOL
    wire l1en = (~stop & ( pce | pce_ov ));
    assign       l1clk = (l2clk & l1en) | se;
   `else
`ifdef LIB
   reg	l1en;
 

`ifdef SCAN_MODE
   always @ (l2clk or stop or pce or pce_ov)
       begin
         if (~l2clk) l1en <= (~stop & (pce | pce_ov));
       end
`else
   always @ (negedge l2clk )
        begin
           l1en <= (~stop & ( pce | pce_ov ));
        end
`endif

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority


`endif
`endif

endmodule
`endif // `ifdef FPGA

module cl_sc1_msffmin_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff


module cl_sc1_msffmin_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             reg 	l1;

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_32x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msffmin_1x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msff_lp_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff


 module cl_sc1_msff_16x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     	
        `ifdef SCAN_MODE

             reg 	l1;
               `ifdef INITLATZERO
              initial l1 = 1'b0;
              initial  q = 1'b0;
            `endif
            
	 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msff_1x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	    	
        `ifdef SCAN_MODE
		 reg l1;
		 
               `ifdef INITLATZERO
              initial l1 = 1'b0;
              initial  q = 1'b0;
            `endif
   	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff


 module cl_sc1_msff_32x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     
        `ifdef SCAN_MODE
		reg l1;
		 
               `ifdef INITLATZERO
              initial l1 = 1'b0;
              initial  q = 1'b0;
            `endif
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else             

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     
        `ifdef SCAN_MODE

             reg l1;
              
               `ifdef INITLATZERO
              initial l1 = 1'b0;
              initial  q = 1'b0;
            `endif
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff

`ifdef FPGA
`else

 module cl_sc1_msff_8x ( q, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;
	     
        `ifdef SCAN_MODE
		reg l1;
		 
               `ifdef INITLATZERO
              initial l1 = 1'b0;
              initial  q = 1'b0;
            `endif
 	`ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else            

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
`endif // `ifdef FPGA

module cl_sc1_msff_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE
		reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msff_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msff_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msff_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
module cl_sc1_msff_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
             reg       q;
             wire     so;
             wire      l1clk, siclk, soclk;

        `ifdef SCAN_MODE

             reg l1;
`ifdef FAST_FLUSH
              always @(l1clk or siclk or  d )    // vcs optimized code 
               begin
                     if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
                else if ( l1clk && !siclk)           q  <= l1;    // Load slave with master data
                else if ( l1clk &&  siclk)           begin       // Conflict between data and scan
                  l1 <= 1'b0;
                  q <=  1'b0;
                end
               end
          `else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= (d&reset);    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  (d&reset);
                else                  q <= 1'bx;
               end
        `endif

         assign so = q;

endmodule // dff
 

module cl_sc1_msffi_16x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg 	q;
             wire     so;
             wire      l1clk, siclk, soclk;
	      
        `ifdef SCAN_MODE
		reg l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else            

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff

module cl_sc1_msffi_1x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg 	q;
             wire     so;
             wire      l1clk, siclk, soclk;
		
        `ifdef SCAN_MODE

             reg l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else
             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff


module cl_sc1_msffi_32x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg 	q;
             wire     so;
             wire      l1clk, siclk, soclk;
		
        `ifdef SCAN_MODE
		reg l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else             

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff


module cl_sc1_msffi_4x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg 	q;
             wire     so;
             wire      l1clk, siclk, soclk;
		
        `ifdef SCAN_MODE
		reg l1;
 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else             

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff

module cl_sc1_msffi_8x ( q_l, so, d, l1clk, si, siclk, soclk );
// RFM 05-14-2004
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE


   parameter SIZE = 1;

   output     q_l;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

             reg       q_l;
             reg 	q;
             wire     so;
             wire      l1clk, siclk, soclk;
		
        `ifdef SCAN_MODE
		reg l1;
	 `ifdef FAST_FLUSH
         always @(posedge l1clk or posedge siclk ) begin
                  if (siclk) begin
                    q <=  1'b0;  //pseudo flush reset
                  end else begin
                    q <=  d;
                  end
                end     
	`else             

             always @(l1clk or siclk or soclk or d or si)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan

               else if ( l1clk && !siclk && !soclk)  q <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk)  q <= si;    // Flush
              end
	`endif
        `else
              wire  si_unused;
              wire siclk_unused;
              wire soclk_unused;
              assign si_unused = si;
              assign siclk_unused        = siclk;
              assign soclk_unused        = soclk;


          `ifdef INITLATZERO
                initial q_l = 1'b1;
                initial q = 1'b0;
          `endif

              always @(posedge l1clk)
               begin
                if (!siclk && !soclk) q <=  d;
                else                  q <= 1'bx;
               end
        `endif
	 
	 
	always @ (q)
begin
  q_l=~q;
end


         assign so = q;

endmodule // dff

module cl_sc1_msffjtag_4x ( q, so, d, l1clk, si, siclk, soclk, reset, updateclk );

   output     q;
   output       so;

   input         d;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;
   input   reset;
   input   updateclk;
`ifdef LIB
             reg       q;
             reg       so;
             wire      l1clk, siclk, soclk, updateclk;

             reg l1;

             always @(l1clk or siclk or soclk or d or si or reset)
              begin
                    if (!l1clk && !siclk)           l1 <= d;    // Load master with data
               else if ( l1clk &&  siclk)           l1 <= si;    // Load master with scan or flush
               else if (!l1clk &&  siclk)           l1 <= 1'bx;    // Conflict between data and scan
                    if (reset)			    so <=1'b0;
                    if ( l1clk && !siclk && !soclk && !reset)  so <= l1;    // Load slave with master data
                    if ( l1clk &&  siclk && !soclk && !reset)  so <= si;    // Flush
              end

         `ifdef INITLATZERO
                initial q = 1'b0;
          `endif


           always@(updateclk or reset or l1)
                begin
                if(reset)  q <=1'b0;
           else if(updateclk)  q <=l1;
               
			
                end
             `endif
endmodule


module cl_sc1_clksyncff_4x(l1clk, d, si, siclk, soclk, q, so);
input l1clk, d, si, siclk, soclk;
output q, so;
wire q1o, slo;

cl_sc1_msff_4x  xx0 ( .l1clk(l1clk), .d(d), .si(si), .siclk(siclk), .soclk(soclk), .q(q1o), .so(slo));
cl_sc1_msff_4x  xx1 ( .l1clk(l1clk), .d(q1o), .si(slo), .siclk(siclk), .soclk(soclk), .q(q), .so(so));
endmodule
module cl_sc1_bs_cell2_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, mode,
muxd, highz_n);

   output     q;
   output       so;

   input         d, highz_n;
   input     l1clk;
   input      si;
   input   siclk;
   input   soclk;

   input   updateclk, mode, muxd;

             reg       q;
             reg       so;
             wire      l1clk, siclk, soclk, updateclk;


             reg l1, qm;

             always @(l1clk or siclk or soclk or d or si)
              begin
   if (!l1clk && !siclk)           l1 <= d;
   if ( l1clk &&  siclk)           l1 <= si;
   if (!l1clk &&  siclk)           l1 <= 1'bx;
   if ( l1clk &&  !soclk)          so <= l1;
   if ( l1clk &&  siclk && !soclk) so <= si;    // Flush
              end
             `ifdef INITLATZERO
                initial qm = 1'b0;
	     `endif
           always@(updateclk or l1)
                begin
                if(updateclk)  qm <=l1;
                end
always@(mode or muxd or qm or highz_n)
        begin
        if(mode==0)  q=(qm && highz_n);
        else         q=muxd;
        end
endmodule

module cl_sc1_clk_buf_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_sc1_clk_buf_20x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_sc1_clk_buf_24x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_sc1_clk_buf_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_sc1_clk_buf_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_sc1_clk_buf_64x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_sc1_clk_buf_8x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_sc1_clk_inv_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_sc1_clk_inv_20x (
clkin,
clkout
);
input	clkin;
output	clkout;

`ifdef LIB
//assign clkout = ~clkin;
not (clkout, clkin);
`endif

endmodule
module cl_sc1_clk_inv_24x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_sc1_clk_inv_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_sc1_clk_inv_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_sc1_clk_inv_64x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_sc1_clk_inv_8x (
clkin,
clkout
);
input	clkin;
output	clkout;

`ifdef LIB
//assign clkout = ~clkin;
not (clkout, clkin);
`endif

endmodule
module cl_sc1_clk_mux2_16x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_sc1_clk_mux2_24x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_sc1_clk_mux2_32x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule

module cl_sc1_clk_mux2_8x (
in0,
in1,
sel0,
out
);
input   in0;
input   in1;
input   sel0;
output  out;

`ifdef LIB
reg out;
   always @ ( sel0 or in0 or in1)
     case ( sel0 )
       1'b1:            out = in0;
       1'b0:            out = in1;

       default:                 out = 1'bx;

       endcase
`endif

endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cl_u1.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module cl_u1_aoi12_12x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) | ( in00 & in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi12_16x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi12_16x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) | ( in00 & in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi12_1x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Thursday Dec  6,2001 at 02:09:00 PM PST
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi12_1x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) | ( in00 & in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi12_2x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi12_2x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) | ( in00 & in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi12_4x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi12_4x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) | ( in00 & in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi12_8x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi12_8x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) | ( in00 & in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi21_12x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:15 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi21_12x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi21_16x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:15 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi21_16x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi21_1x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:15 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi21_1x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi21_2x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:15 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi21_2x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi21_4x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:15 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi21_4x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi21_8x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:15 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi21_8x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi22_12x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:16 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi22_12x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
`endif

endmodule

// --------------------------------------------------
// File: cl_u1_aoi22_1x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:32 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi22_1x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi22_2x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:16 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi22_2x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
`endif

endmodule

`ifdef FPGA
`else

// --------------------------------------------------
// File: cl_u1_aoi22_4x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:16 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi22_4x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
`endif

endmodule
`endif // `ifdef FPGA

// --------------------------------------------------
// File: cl_u1_aoi22_8x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:16 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi22_8x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
`endif

endmodule


// --------------------------------------------------
// File: cl_u1_aoi33_1x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Thursday Dec  6,2001 at 02:09:02 PM PST
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi33_1x (
    out,
    in10,
    in11,
    in12,
    in00,
    in01,
    in02 );

    output out;
    input  in10;
    input  in11;
    input  in12;
    input  in00;
    input  in01;
    input  in02;

`ifdef LIB
    assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi33_2x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:18 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi33_2x (
    out,
    in10,
    in11,
    in12,
    in00,
    in01,
    in02 );

    output out;
    input  in10;
    input  in11;
    input  in12;
    input  in00;
    input  in01;
    input  in02;

`ifdef LIB
    assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi33_4x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:18 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi33_4x (
    out,
    in10,
    in11,
    in12,
    in00,
    in01,
    in02 );

    output out;
    input  in10;
    input  in11;
    input  in12;
    input  in00;
    input  in01;
    input  in02;

`ifdef LIB
    assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_aoi33_8x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:18 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_aoi33_8x (
    out,
    in10,
    in11,
    in12,
    in00,
    in01,
    in02 );

    output out;
    input  in10;
    input  in11;
    input  in12;
    input  in00;
    input  in01;
    input  in02;

`ifdef LIB
    assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
`endif

endmodule
module cl_u1_rep_lvt_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_lvt_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_40x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_24x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_8x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp2x_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

module cl_u1_rep_dcp2x_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp2x_24x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp2x_40x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp2x_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

module cl_u1_rep_dcp_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp_24x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp_40x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp50k_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp50k_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_rep_dcp50k_40x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

module cl_u1_buf_12x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
`ifdef FPGA
`else

module cl_u1_buf_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

`endif // `ifdef FPGA

module cl_u1_buf_1x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_20x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_24x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_28x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_2x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_buf_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

`endif // `ifdef FPGA


module cl_u1_buf_36x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_40x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_44x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_4x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_56x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_64x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_buf_6x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_buf_8x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
`endif // `ifdef FPGA


module cl_u1_bufmin_15ps_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_bufmin_1x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_bufmin_4x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_bufmin_8x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_bufmin_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_bufmin_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = in;
buf (out, in);
`endif

endmodule
module cl_u1_csa32_16x (
in0,
in1,
in2,
carry,
sum
);
input 	in0;
input 	in1;
input 	in2;
output 	carry;
output 	sum;

`ifdef LIB
  assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2);
  assign sum = (in0 ^ in1 ^ in2);
`endif

endmodule
module cl_u1_csa32_4x (
in0,
in1,
in2,
carry,
sum
);
input 	in0;
input 	in1;
input 	in2;
output 	carry;
output 	sum;

`ifdef LIB
  assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2);
  assign sum = (in0 ^ in1 ^ in2);
`endif

endmodule
module cl_u1_csa32_8x (
in0,
in1,
in2,
carry,
sum
);
input 	in0;
input 	in1;
input 	in2;
output 	carry;
output 	sum;

`ifdef LIB
  assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2);
  assign sum = (in0 ^ in1 ^ in2);
`endif

endmodule
module cl_u1_csa42_16x (
in0,
in1,
in2,
in3,
cin,
cout,
carry,
sum
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input   cin;
output  cout;
output 	carry;
output 	sum;

`ifdef LIB
  assign cout  = (in1 & in2) | (in0 & in2) | (in0 & in1);

  assign sum   = (~in0 & ~in1 & ~in2 & ~in3 &  cin) |
                 (~in0 & ~in1 & ~in2 &  in3 & ~cin) |
                 (~in0 & ~in1 &  in2 & ~in3 & ~cin) |
                 (~in0 & ~in1 &  in2 &  in3 &  cin) |

                 (~in0 &  in1 & ~in2 & ~in3 & ~cin) |
                 (~in0 &  in1 & ~in2 &  in3 &  cin) |
                 (~in0 &  in1 &  in2 & ~in3 &  cin) |
                 (~in0 &  in1 &  in2 &  in3 & ~cin) |

                 ( in0 & ~in1 & ~in2 & ~in3 & ~cin) |
                 ( in0 & ~in1 & ~in2 &  in3 &  cin) |
                 ( in0 & ~in1 &  in2 & ~in3 &  cin) |
                 ( in0 & ~in1 &  in2 &  in3 & ~cin) |

                 ( in0 &  in1 & ~in2 & ~in3 &  cin) |
                 ( in0 &  in1 & ~in2 &  in3 & ~cin) |
                 ( in0 &  in1 &  in2 & ~in3 & ~cin) |
                 ( in0 &  in1 &  in2 &  in3 &  cin);

  assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) |
                 (~in0 & ~in1 & ~in2 &  in3 &  cin) |
                 (~in0 & ~in1 &  in2 & ~in3 &  cin) |
                 (~in0 & ~in1 &  in2 &  in3 & 1'b1) |

                 (~in0 &  in1 & ~in2 & ~in3 &  cin) |
                 (~in0 &  in1 & ~in2 &  in3 & 1'b1) |
                 (~in0 &  in1 &  in2 & ~in3 & 1'b0) |
                 (~in0 &  in1 &  in2 &  in3 &  cin) |

                 ( in0 & ~in1 & ~in2 & ~in3 &  cin) |
                 ( in0 & ~in1 & ~in2 &  in3 & 1'b1) |
                 ( in0 & ~in1 &  in2 & ~in3 & 1'b0) |
                 ( in0 & ~in1 &  in2 &  in3 &  cin) |

                 ( in0 &  in1 & ~in2 & ~in3 & 1'b0) |
                 ( in0 &  in1 & ~in2 &  in3 &  cin) |
                 ( in0 &  in1 &  in2 & ~in3 &  cin) |
                 ( in0 &  in1 &  in2 &  in3 & 1'b1);


`endif

endmodule
module cl_u1_csa42_4x (
in0,
in1,
in2,
in3,
cin,
cout,
carry,
sum
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input   cin;
output  cout;
output 	carry;
output 	sum;

`ifdef LIB
  assign cout  = (in1 & in2) | (in0 & in2) | (in0 & in1);

  assign sum   = (~in0 & ~in1 & ~in2 & ~in3 &  cin) |
                 (~in0 & ~in1 & ~in2 &  in3 & ~cin) |
                 (~in0 & ~in1 &  in2 & ~in3 & ~cin) |
                 (~in0 & ~in1 &  in2 &  in3 &  cin) |

                 (~in0 &  in1 & ~in2 & ~in3 & ~cin) |
                 (~in0 &  in1 & ~in2 &  in3 &  cin) |
                 (~in0 &  in1 &  in2 & ~in3 &  cin) |
                 (~in0 &  in1 &  in2 &  in3 & ~cin) |

                 ( in0 & ~in1 & ~in2 & ~in3 & ~cin) |
                 ( in0 & ~in1 & ~in2 &  in3 &  cin) |
                 ( in0 & ~in1 &  in2 & ~in3 &  cin) |
                 ( in0 & ~in1 &  in2 &  in3 & ~cin) |

                 ( in0 &  in1 & ~in2 & ~in3 &  cin) |
                 ( in0 &  in1 & ~in2 &  in3 & ~cin) |
                 ( in0 &  in1 &  in2 & ~in3 & ~cin) |
                 ( in0 &  in1 &  in2 &  in3 &  cin);

  assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) |
                 (~in0 & ~in1 & ~in2 &  in3 &  cin) |
                 (~in0 & ~in1 &  in2 & ~in3 &  cin) |
                 (~in0 & ~in1 &  in2 &  in3 & 1'b1) |

                 (~in0 &  in1 & ~in2 & ~in3 &  cin) |
                 (~in0 &  in1 & ~in2 &  in3 & 1'b1) |
                 (~in0 &  in1 &  in2 & ~in3 & 1'b0) |
                 (~in0 &  in1 &  in2 &  in3 &  cin) |

                 ( in0 & ~in1 & ~in2 & ~in3 &  cin) |
                 ( in0 & ~in1 & ~in2 &  in3 & 1'b1) |
                 ( in0 & ~in1 &  in2 & ~in3 & 1'b0) |
                 ( in0 & ~in1 &  in2 &  in3 &  cin) |

                 ( in0 &  in1 & ~in2 & ~in3 & 1'b0) |
                 ( in0 &  in1 & ~in2 &  in3 &  cin) |
                 ( in0 &  in1 &  in2 & ~in3 &  cin) |
                 ( in0 &  in1 &  in2 &  in3 & 1'b1);


`endif

endmodule
module cl_u1_csa42_8x (
in0,
in1,
in2,
in3,
cin,
cout,
carry,
sum
);
input 	in0;
input 	in1;
input 	in2;
input 	in3;
input   cin;
output  cout;
output 	carry;
output 	sum;

`ifdef LIB
  assign cout  = (in1 & in2) | (in0 & in2) | (in0 & in1);

  assign sum   = (~in0 & ~in1 & ~in2 & ~in3 &  cin) |
                 (~in0 & ~in1 & ~in2 &  in3 & ~cin) |
                 (~in0 & ~in1 &  in2 & ~in3 & ~cin) |
                 (~in0 & ~in1 &  in2 &  in3 &  cin) |

                 (~in0 &  in1 & ~in2 & ~in3 & ~cin) |
                 (~in0 &  in1 & ~in2 &  in3 &  cin) |
                 (~in0 &  in1 &  in2 & ~in3 &  cin) |
                 (~in0 &  in1 &  in2 &  in3 & ~cin) |

                 ( in0 & ~in1 & ~in2 & ~in3 & ~cin) |
                 ( in0 & ~in1 & ~in2 &  in3 &  cin) |
                 ( in0 & ~in1 &  in2 & ~in3 &  cin) |
                 ( in0 & ~in1 &  in2 &  in3 & ~cin) |

                 ( in0 &  in1 & ~in2 & ~in3 &  cin) |
                 ( in0 &  in1 & ~in2 &  in3 & ~cin) |
                 ( in0 &  in1 &  in2 & ~in3 & ~cin) |
                 ( in0 &  in1 &  in2 &  in3 &  cin);

  assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) |
                 (~in0 & ~in1 & ~in2 &  in3 &  cin) |
                 (~in0 & ~in1 &  in2 & ~in3 &  cin) |
                 (~in0 & ~in1 &  in2 &  in3 & 1'b1) |

                 (~in0 &  in1 & ~in2 & ~in3 &  cin) |
                 (~in0 &  in1 & ~in2 &  in3 & 1'b1) |
                 (~in0 &  in1 &  in2 & ~in3 & 1'b0) |
                 (~in0 &  in1 &  in2 &  in3 &  cin) |

                 ( in0 & ~in1 & ~in2 & ~in3 &  cin) |
                 ( in0 & ~in1 & ~in2 &  in3 & 1'b1) |
                 ( in0 & ~in1 &  in2 & ~in3 & 1'b0) |
                 ( in0 & ~in1 &  in2 &  in3 &  cin) |

                 ( in0 &  in1 & ~in2 & ~in3 & 1'b0) |
                 ( in0 &  in1 & ~in2 &  in3 &  cin) |
                 ( in0 &  in1 &  in2 & ~in3 &  cin) |
                 ( in0 &  in1 &  in2 &  in3 & 1'b1);


`endif

endmodule
module cl_u1_inv_12x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_inv_16x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
`endif // `ifdef FPGA

module cl_u1_inv_1x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_20x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_24x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_28x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_2x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_inv_32x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule

`endif // `ifdef FPGA


module cl_u1_inv_36x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_40x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_44x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_48x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_4x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_56x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_64x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule
module cl_u1_inv_6x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_inv_8x (
in,
out
);
input	in;
output	out;

`ifdef LIB
//assign out = ~in;
not (out, in);
`endif

endmodule

`endif // `ifdef FPGA


module cl_u1_nand2_12x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_nand2_16x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule

`endif // `ifdef FPGA


module cl_u1_nand2_1x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_u1_nand2_20x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_u1_nand2_24x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_u1_nand2_28x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_u1_nand2_2x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_u1_nand2_32x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_u1_nand2_4x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule
module cl_u1_nand2_6x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_nand2_8x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 & in1);
`endif

endmodule

`endif // `ifdef FPGA


module cl_u1_nand3_12x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule
module cl_u1_nand3_16x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule
module cl_u1_nand3_1x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule
module cl_u1_nand3_20x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule
module cl_u1_nand3_24x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule

module cl_u1_nand3_2x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule

module cl_u1_nand3_4x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule
module cl_u1_nand3_6x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_nand3_8x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2);
`endif

endmodule

`endif // `ifdef FPGA


module cl_u1_nand4_12x (
in0,
in1,
in2,
in3,
out
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2 & in3);
`endif

endmodule
module cl_u1_nand4_16x (
in0,
in1,
in2,
in3,
out
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2 & in3);
`endif

endmodule
module cl_u1_nand4_1x (
in0,
in1,
in2,
in3,
out
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2 & in3);
`endif

endmodule


module cl_u1_nand4_2x (
in0,
in1,
in2,
in3,
out
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2 & in3);
`endif

endmodule

module cl_u1_nand4_4x (
in0,
in1,
in2,
in3,
out
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2 & in3);
`endif

endmodule
module cl_u1_nand4_6x (
in0,
in1,
in2,
in3,
out
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2 & in3);
`endif

endmodule
module cl_u1_nand4_8x (
in0,
in1,
in2,
in3,
out
);
input	in0;
input	in1;
input	in2;
input	in3;
output	out;

`ifdef LIB
assign out = ~(in0 & in1 & in2 & in3);
`endif

endmodule
module cl_u1_nor2_12x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 | in1);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_nor2_16x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 | in1);
`endif

endmodule

`endif // `ifdef FPGA


module cl_u1_nor2_1x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 | in1);
`endif

endmodule
module cl_u1_nor2_2x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 | in1);
`endif

endmodule
module cl_u1_nor2_4x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 | in1);
`endif

endmodule
module cl_u1_nor2_6x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 | in1);
`endif

endmodule
module cl_u1_nor2_8x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 | in1);
`endif

endmodule
module cl_u1_nor3_1x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 | in1 | in2);
`endif

endmodule
module cl_u1_nor3_2x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 | in1 | in2);
`endif

endmodule

`ifdef FPGA
`else

module cl_u1_nor3_4x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 | in1 | in2);
`endif

endmodule

`endif // `ifdef FPGA


// --------------------------------------------------
// File: cl_u1_oai12_12x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai12_12x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai12_16x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai12_16x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai12_1x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai12_1x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai12_2x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai12_2x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai12_4x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai12_4x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai12_8x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai12_8x (
    out,
    in10,
    in00,
    in01 );

    output out;
    input  in10;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai21_12x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai21_12x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai21_16x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai21_16x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai21_1x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Friday Mar 15,2002 at 02:53:58 PM PST
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai21_1x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai21_2x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:23 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai21_2x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai21_4x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:23 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai21_4x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai21_8x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:23 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai21_8x (
    out,
    in10,
    in11,
    in00 );

    output out;
    input  in10;
    input  in11;
    input  in00;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai22_12x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai22_12x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai22_16x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai22_16x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai22_1x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai22_1x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
`endif

endmodule
// --------------------------------------------------
// File: cl_u1_oai22_2x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:24 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai22_2x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
`endif

endmodule

`ifdef FPGA
`else

// --------------------------------------------------
// File: cl_u1_oai22_4x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:24 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai22_4x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
`endif

endmodule

`endif // `ifdef FPGA

// --------------------------------------------------
// File: cl_u1_oai22_8x.behV
// Auto generated verilog module by HnBCellAuto
//
// Created: Monday Oct  8,2001 at 11:32:24 AM PDT
// By: balmiki
// --------------------------------------------------
// 
module cl_u1_oai22_8x (
    out,
    in10,
    in11,
    in00,
    in01 );

    output out;
    input  in10;
    input  in11;
    input  in00;
    input  in01;

`ifdef LIB
    assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
`endif

endmodule
module cl_u1_xnor2_16x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1);
`endif

endmodule

module cl_u1_xnor2_1x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1);
`endif

endmodule
module cl_u1_xnor2_2x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1);
`endif

endmodule
module cl_u1_xnor2_4x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1);
`endif

endmodule
module cl_u1_xnor2_6x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1);
`endif

endmodule
module cl_u1_xnor2_8x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1);
`endif

endmodule

module cl_u1_xnor3_16x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1 ^ in2);
`endif


endmodule
module cl_u1_xnor3_1x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1 ^ in2);
`endif


endmodule
module cl_u1_xnor3_2x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1 ^ in2);
`endif


endmodule
module cl_u1_xnor3_4x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1 ^ in2);
`endif


endmodule
module cl_u1_xnor3_6x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1 ^ in2);
`endif


endmodule
module cl_u1_xnor3_8x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = ~(in0 ^ in1 ^ in2);
`endif


endmodule
module cl_u1_xor2_16x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = in0 ^ in1;
`endif

endmodule

module cl_u1_xor2_1x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = in0 ^ in1;
`endif

endmodule
module cl_u1_xor2_2x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = in0 ^ in1;
`endif

endmodule
module cl_u1_xor2_4x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = in0 ^ in1;
`endif

endmodule
module cl_u1_xor2_6x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = in0 ^ in1;
`endif

endmodule
module cl_u1_xor2_8x (
in0,
in1,
out
);
input	in0;
input	in1;
output	out;

`ifdef LIB
assign out = in0 ^ in1;
`endif

endmodule
module cl_u1_xor3_16x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = in0 ^ in1 ^ in2;
`endif


endmodule

module cl_u1_xor3_1x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = in0 ^ in1 ^ in2;
`endif


endmodule
module cl_u1_xor3_2x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = in0 ^ in1 ^ in2;
`endif


endmodule
module cl_u1_xor3_4x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = in0 ^ in1 ^ in2;
`endif


endmodule
module cl_u1_xor3_6x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = in0 ^ in1 ^ in2;
`endif


endmodule
module cl_u1_xor3_8x (
in0,
in1,
in2,
out
);
input	in0;
input	in1;
input	in2;
output	out;

`ifdef LIB
assign out = in0 ^ in1 ^ in2;
`endif


endmodule

module cl_u1_clkchp_4x ( 
   tck, 
   aclk,
   bclk
);
input tck;
output aclk;
output bclk;


`ifdef LIB
  reg    chop_aclk, chop_bclk;

   always @(posedge tck) begin
      chop_aclk = 1'b1;
      #5 chop_aclk = 1'b0;
   end
   always @(negedge tck) begin
      chop_bclk = 1'b1;
      #5 chop_bclk = 1'b0;
   end
    
   assign aclk = chop_aclk;
   assign bclk = chop_bclk;
`endif 

endmodule

module cl_u1_muxprotect_2x (
d0,
d1,
d2,
d3,
scan_en,
e0,
e1,
e2,
e3
);
input d0;
input d1;
input d2;
input d3;
input scan_en;
output e0;
output e1;
output e2;
output e3;

`ifdef LIB
assign e0 = scan_en | d0;
assign e1= ~scan_en & d1;
assign e2= ~scan_en & d2;
assign e3= ~scan_en & d3;
`endif

endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_clk_ccx_cmp_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`timescale 1 ps / 1 ps

module n2_clk_ccx_cmp_cust (
	cclk_left,
	cclk_right,
	l2clk
);

input 	cclk_left;
input 	cclk_right;
output 	l2clk;

wire	cclk_left;
wire	cclk_right;
wire	l2clk;

assign #1 l2clk = cclk_left & cclk_right; 
				
endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_clk_spc_cmp_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`timescale 1 ps / 1 ps

module n2_clk_spc_cmp_cust (
	cclk,
	l2clk
);

input 	cclk;
output 	l2clk;

wire	cclk;
wire	l2clk;

assign #1 l2clk = cclk; 
				
endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_flop_bank_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_flop_bank_cust (
  l2clk, 
  scan_in, 
  scan_out, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  tcu_pce_ov, 
  local_stop, 
  data_out, 
  data_in);
wire siclk;
wire soclk;
wire se;
wire pce_ov;
wire l1clk;
wire datain_ff_scanin;
wire datain_ff_scanout;

   
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
   // Global interface
input		l2clk;		
input 		scan_in;
output		scan_out;
input 		tcu_aclk;
input		tcu_bclk;
input		tcu_scan_en;
input           tcu_pce_ov;
input 		local_stop;
// Local interface
output [15:0]  data_out;
input  [15:0]  data_in;

//Internal Scan Chain
wire  [14:0]  fdin;
wire  [15:0]  flop_out;


// Internal signals
//wire   [15:0]		data;

////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////

// Scan reassigns
assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;

cl_u1_buf_32x buf_15_ ( .in(flop_out[15]), .out(data_out[15]));
cl_u1_buf_32x buf_14_ ( .in(flop_out[14]), .out(data_out[14]));
cl_u1_buf_32x buf_13_ ( .in(flop_out[13]), .out(data_out[13]));
cl_u1_buf_32x buf_12_ ( .in(flop_out[12]), .out(data_out[12]));
cl_u1_buf_32x buf_11_ ( .in(flop_out[11]), .out(data_out[11]));
cl_u1_buf_32x buf_10_ ( .in(flop_out[10]), .out(data_out[10]));
cl_u1_buf_32x buf_9_ ( .in(flop_out[9]), .out(data_out[9]));
cl_u1_buf_32x buf_8_ ( .in(flop_out[8]), .out(data_out[8]));
cl_u1_buf_32x buf_7_ ( .in(flop_out[7]), .out(data_out[7]));
cl_u1_buf_32x buf_6_ ( .in(flop_out[6]), .out(data_out[6]));
cl_u1_buf_32x buf_5_ ( .in(flop_out[5]), .out(data_out[5]));
cl_u1_buf_32x buf_4_ ( .in(flop_out[4]), .out(data_out[4]));
cl_u1_buf_32x buf_3_ ( .in(flop_out[3]), .out(data_out[3]));
cl_u1_buf_32x buf_2_ ( .in(flop_out[2]), .out(data_out[2]));
cl_u1_buf_32x buf_1_ ( .in(flop_out[1]), .out(data_out[1]));
cl_u1_buf_32x buf_0_ ( .in(flop_out[0]), .out(data_out[0]));

cl_sc1_l1hdr_32x c_0 (
   .l2clk(l2clk),
   .pce(1'b1),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(local_stop)
);

cl_sc1_msff_8x d0_0 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[0]),
.q(flop_out[0]),
.si(scan_in),
.so(fdin[0])
);

cl_sc1_msff_8x d0_1 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[1]),
.q(flop_out[1]),
.si(fdin[0]),
.so(fdin[1])
);

cl_sc1_msff_8x d0_2 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[2]),
.q(flop_out[2]),
.si(fdin[1]),
.so(fdin[2])
);

cl_sc1_msff_8x d0_3 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[3]),
.q(flop_out[3]),
.si(fdin[2]),
.so(fdin[3])
);

cl_sc1_msff_8x d0_4 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[4]),
.q(flop_out[4]),
.si(fdin[3]),
.so(fdin[4])
);


cl_sc1_msff_8x d0_5 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[5]),
.q(flop_out[5]),
.si(fdin[4]),
.so(fdin[5])
);

cl_sc1_msff_8x d0_6 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[6]),
.q(flop_out[6]),
.si(fdin[5]),
.so(fdin[6])
);

cl_sc1_msff_8x d0_7 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[7]),
.q(flop_out[7]),
.si(fdin[6]),
.so(fdin[7])
);

cl_sc1_msff_8x d0_8 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[8]),
.q(flop_out[8]),
.si(fdin[7]),
.so(fdin[8])
);

cl_sc1_msff_8x d0_9 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[9]),
.q(flop_out[9]),
.si(fdin[8]),
.so(fdin[9])
);

cl_sc1_msff_8x d0_10 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[10]),
.q(flop_out[10]),
.si(fdin[9]),
.so(fdin[10])
);

cl_sc1_msff_8x d0_11 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[11]),
.q(flop_out[11]),
.si(fdin[10]),
.so(fdin[11])
);

cl_sc1_msff_8x d0_12 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[12]),
.q(flop_out[12]),
.si(fdin[11]),
.so(fdin[12])
);

cl_sc1_msff_8x d0_13 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[13]),
.q(flop_out[13]),
.si(fdin[12]),
.so(fdin[13])
);

cl_sc1_msff_8x d0_14 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[14]),
.q(flop_out[14]),
.si(fdin[13]),
.so(fdin[14])
);

cl_sc1_msff_8x d0_15 (
.l1clk(l1clk),
.siclk(tcu_aclk),
.soclk(tcu_bclk),
.d(data_in[15]),
.q(flop_out[15]),
.si(fdin[14]),
.so(scan_out)
);


endmodule
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: clkgen_ccx_cmp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module clkgen_ccx_cmp ( 
	array_wr_inhibit,
	tcu_atpg_mode,
	tcu_wr_inhibit,
	l2clk,
	aclk,
	bclk,
	scan_out,
	pce_ov,
	aclk_wmr,
	wmr_protect,
	wmr_,
	por_,
	cmp_slow_sync_en,
	slow_cmp_sync_en,
	tcu_clk_stop_left,
	tcu_clk_stop_right,
	tcu_pce_ov,
	rst_wmr_protect,
	rst_wmr_,
	rst_por_,
	ccu_cmp_slow_sync_en,
	ccu_slow_cmp_sync_en,
	tcu_div_bypass_left,
	tcu_div_bypass_right,
	ccu_div_ph,
	cluster_div_en,
	gclk_left,
	gclk_right,
	cluster_arst_l_left,
	cluster_arst_l_right,
	clk_ext,
	ccu_serdes_dtm,
	tcu_aclk,
	tcu_bclk,
	scan_en,
	scan_in
);

 
// ************************** 
// port declaration 
// ************************** 

// clock & test out
output	l2clk;	// assume we do not need aclk, bclk outputs
output	aclk;	// buffered version of aclk
output	bclk;	// buffered version of bclk
output	scan_out;		// unused as of today - feb 10, 05
output  aclk_wmr;

// pipelined out
output	pce_ov;				// pce override to l1 header
output	wmr_protect;		// warm reset protect
output	wmr_;				// warm reset (active low) 
output	por_;				// power-on-reset 
output	cmp_slow_sync_en;	// cmp->slow clk sync pulse
output	slow_cmp_sync_en;	// slow->cmp clk sync pulse

// ctrl in (for pipelining)
output	array_wr_inhibit;
input	tcu_atpg_mode;
input	tcu_wr_inhibit;
input	tcu_clk_stop_left;
input	tcu_clk_stop_right;
input	tcu_pce_ov;
input	rst_wmr_protect;		
input	rst_wmr_;		
input	rst_por_;
input	ccu_cmp_slow_sync_en;
input	ccu_slow_cmp_sync_en;

// ctrl in (for clock gen) 
// input	tcu_div_bypass;		// bypasses clk divider to mux in ext clk
input tcu_div_bypass_left;
input tcu_div_bypass_right;
input	ccu_div_ph;			// phase signal from ccu (div/4 or div/2)
input   cluster_div_en;		// if enabled, l2clk is divided down 
input cluster_arst_l_left;
input cluster_arst_l_right;

// clock & test in
input	gclk_left;			// global clk - this is either cmp or dr
input	gclk_right;			// global clk - this is either cmp or dr
input 	ccu_serdes_dtm;
input	clk_ext;		// external clk muxed in for ioclk bypass 
input	scan_en;		// unused as of today - feb 10, 05
input	scan_in;		// unused as of today - feb 10, 05
input	tcu_aclk;				
input	tcu_bclk;


// ************************** 
// wire declaration 
// ************************** 
wire	array_wr_inhibit;
wire	tcu_atpg_mode;
wire	tcu_wr_inhibit;
wire	l2clk;	
wire	aclk;
wire	bclk;
wire	scan_out;
wire	aclk_wmr;	
wire	pce_ov;
wire	wmr_protect;
wire	wmr_;
wire	por_;
wire	cmp_slow_sync_en;
wire	slow_cmp_sync_en;
wire	tcu_clk_stop_left;
wire	tcu_clk_stop_right;
wire	tcu_pce_ov;
wire	rst_wmr_protect;
wire	rst_wmr_;
wire	rst_por_;
wire	ccu_cmp_slow_sync_en;
wire	ccu_slow_cmp_sync_en;
wire	tcu_div_bypass_right;
wire	tcu_div_bypass_left;
wire	ccu_div_ph;
wire	cluster_div_en;
wire	gclk_left;
wire	gclk_right;
wire	cluster_arst_l_left;
wire	cluster_arst_l_right;
wire	clk_ext;
wire	ccu_serdes_dtm;
wire	scan_en;				
wire	scan_in;				
wire	tcu_aclk;				
wire	tcu_bclk;

wire	cclk_left;
wire	cclk_right;
	
wire 	scan_tmp;


// ************************** 
// instantiations
// ************************** 

// needs a few edits to cluster header def - mahmud.hassan 
// modified custom cell name for avoiding 
// collision with sparc core and other clusters - mhassan
n2_clk_clstr_hdr_cust xcluster_header_right (
	.gclk (gclk_right),
	.l2clk (l2clk),
	.cluster_arst_l (cluster_arst_l_right),
	.ccu_div_ph (ccu_div_ph),
	.cluster_div_en (cluster_div_en),	
	.tcu_div_bypass (tcu_div_bypass_right),
	// .clk_ext (clk_ext),
	// .ccu_serdes_dtm (ccu_serdes_dtm),
	.scan_in (scan_in),
	.scan_en (scan_en),	// temporary
	.tcu_aclk (tcu_aclk),
	.tcu_bclk (tcu_bclk),
	.ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en),
	.ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en),
	.tcu_pce_ov (tcu_pce_ov),
	.tcu_clk_stop (tcu_clk_stop_right),
	.rst_por_ (rst_por_),
	.rst_wmr_ (rst_wmr_),
	.rst_wmr_protect (rst_wmr_protect),
	.aclk_wmr (aclk_wmr),
	.aclk (aclk),
	.bclk (bclk),
	.cmp_slow_sync_en (cmp_slow_sync_en),
	.slow_cmp_sync_en (slow_cmp_sync_en),
	.pce_ov (pce_ov),
	.por_ (por_),
	.wmr_ (wmr_),
	.wmr_protect (wmr_protect),
	.scan_out (scan_out),
	.array_wr_inhibit (array_wr_inhibit),
	.tcu_atpg_mode (tcu_atpg_mode),
	.tcu_wr_inhibit (tcu_wr_inhibit),
	.cclk (cclk_right)
);


n2_clk_clstr_hdr_cust xcluster_header_left (
	.gclk (gclk_left),
	.l2clk (l2clk),
	.cluster_arst_l (cluster_arst_l_left),
	.ccu_div_ph (ccu_div_ph),
	.cluster_div_en (cluster_div_en),	
	.tcu_div_bypass (tcu_div_bypass_left),
	// .clk_ext (1'b0),
	// .ccu_serdes_dtm (1'b0),
	.scan_in (1'b0),
	.scan_en (1'b0),
	.tcu_aclk (1'b0),
	.tcu_bclk (1'b0),
	.ccu_cmp_slow_sync_en (1'b0),
	.ccu_slow_cmp_sync_en (1'b0),
	.tcu_pce_ov (1'b1),
	.tcu_clk_stop (tcu_clk_stop_left),
	.rst_por_ (1'b0),
	.rst_wmr_ (1'b0),
	.rst_wmr_protect (1'b0),
	.aclk_wmr (),
	.aclk (),
	.bclk (),
	.cmp_slow_sync_en (),
	.slow_cmp_sync_en (),
	.pce_ov (),
	.por_ (),
	.wmr_ (),
	.wmr_protect (),
	.scan_out (),
	.array_wr_inhibit (),
	.tcu_atpg_mode (tcu_atpg_mode),
	.tcu_wr_inhibit (1'b0),
	.cclk (cclk_left)
);

// cclk -> l2clk on bottom 
n2_clk_ccx_cmp_cust xbottom (
     .l2clk         (l2clk),
     .cclk_right    (cclk_right),
     .cclk_left 	(cclk_left) 
);


// cclk -> l2clk on top 
n2_clk_ccx_cmp_cust xtop (
     .l2clk         (l2clk),
     .cclk_right    (cclk_right), 
     .cclk_left 	(cclk_left) 
);


endmodule


`endif // `ifndef FPGA

`ifdef FPGA
module clkgen_ccx_cmp(array_wr_inhibit, tcu_atpg_mode, tcu_wr_inhibit, l2clk, 
	aclk, bclk, scan_out, pce_ov, aclk_wmr, wmr_protect, wmr_, por_, 
	cmp_slow_sync_en, slow_cmp_sync_en, tcu_clk_stop_left, 
	tcu_clk_stop_right, tcu_pce_ov, rst_wmr_protect, rst_wmr_, rst_por_, 
	ccu_cmp_slow_sync_en, ccu_slow_cmp_sync_en, tcu_div_bypass_left, 
	tcu_div_bypass_right, ccu_div_ph, cluster_div_en, gclk_left, gclk_right,
	cluster_arst_l_left, cluster_arst_l_right, clk_ext, ccu_serdes_dtm, 
	tcu_aclk, tcu_bclk, scan_en, scan_in);

	output			l2clk;
	output			aclk;
	output			bclk;
	output			scan_out;
	output			aclk_wmr;
	output			pce_ov;
	output			wmr_protect;
	output			wmr_;
	output			por_;
	output			cmp_slow_sync_en;
	output			slow_cmp_sync_en;
	output			array_wr_inhibit;
	input			tcu_atpg_mode;
	input			tcu_wr_inhibit;
	input			tcu_clk_stop_left;
	input			tcu_clk_stop_right;
	input			tcu_pce_ov;
	input			rst_wmr_protect;
	input			rst_wmr_;
	input			rst_por_;
	input			ccu_cmp_slow_sync_en;
	input			ccu_slow_cmp_sync_en;
	input			tcu_div_bypass_left;
	input			tcu_div_bypass_right;
	input			ccu_div_ph;
	input			cluster_div_en;
	input			cluster_arst_l_left;
	input			cluster_arst_l_right;
	input			gclk_left;
	input			gclk_right;
	input			ccu_serdes_dtm;
	input			clk_ext;
	input			scan_en;
	input			scan_in;
	input			tcu_aclk;
	input			tcu_bclk;

	wire			cclk_left;
	wire			cclk_right;
	wire			scan_tmp;

	n2_clk_clstr_hdr_cust xcluster_header_right(
		.gclk				(gclk_right), 
		.l2clk				(l2clk), 
		.cluster_arst_l			(cluster_arst_l_right), 
		.ccu_div_ph			(ccu_div_ph), 
		.cluster_div_en			(cluster_div_en), 
		.tcu_div_bypass			(tcu_div_bypass_right), 
		.scan_in			(scan_in), 
		.scan_en			(scan_en), 
		.tcu_aclk			(tcu_aclk), 
		.tcu_bclk			(tcu_bclk), 
		.ccu_cmp_slow_sync_en		(ccu_cmp_slow_sync_en), 
		.ccu_slow_cmp_sync_en		(ccu_slow_cmp_sync_en), 
		.tcu_pce_ov			(tcu_pce_ov), 
		.tcu_clk_stop			(tcu_clk_stop_right), 
		.rst_por_			(rst_por_), 
		.rst_wmr_			(rst_wmr_), 
		.rst_wmr_protect		(rst_wmr_protect), 
		.aclk_wmr			(aclk_wmr), 
		.aclk				(aclk), 
		.bclk				(bclk), 
		.cmp_slow_sync_en		(cmp_slow_sync_en), 
		.slow_cmp_sync_en		(slow_cmp_sync_en), 
		.pce_ov				(pce_ov), 
		.por_				(por_), 
		.wmr_				(wmr_), 
		.wmr_protect			(wmr_protect), 
		.scan_out			(scan_out), 
		.array_wr_inhibit		(array_wr_inhibit), 
		.tcu_atpg_mode			(tcu_atpg_mode), 
		.tcu_wr_inhibit			(tcu_wr_inhibit), 
		.cclk				(cclk_right));
	n2_clk_clstr_hdr_cust xcluster_header_left(
		.gclk				(gclk_left), 
		.l2clk				(l2clk), 
		.cluster_arst_l			(cluster_arst_l_left), 
		.ccu_div_ph			(ccu_div_ph), 
		.cluster_div_en			(cluster_div_en), 
		.tcu_div_bypass			(tcu_div_bypass_left), 
		.scan_in			(1'b0), 
		.scan_en			(1'b0), 
		.tcu_aclk			(1'b0), 
		.tcu_bclk			(1'b0), 
		.ccu_cmp_slow_sync_en		(1'b0), 
		.ccu_slow_cmp_sync_en		(1'b0), 
		.tcu_pce_ov			(1'b1), 
		.tcu_clk_stop			(tcu_clk_stop_left), 
		.rst_por_			(1'b0), 
		.rst_wmr_			(1'b0), 
		.rst_wmr_protect		(1'b0), 
		.tcu_atpg_mode			(tcu_atpg_mode), 
		.tcu_wr_inhibit			(1'b0), 
		.cclk				(cclk_left));
	n2_clk_ccx_cmp_cust xbottom(
		.l2clk				(l2clk), 
		.cclk_right			(cclk_right), 
		.cclk_left			(cclk_left));
	n2_clk_ccx_cmp_cust xtop(
		.l2clk				(l2clk), 
		.cclk_right			(cclk_right), 
		.cclk_left			(cclk_left));


endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: clkgen_spc_cmp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module clkgen_spc_cmp ( 
	array_wr_inhibit,
	tcu_atpg_mode,
	tcu_wr_inhibit,
	l2clk,
	aclk,
	bclk,
	scan_out,
	pce_ov,
	aclk_wmr,
	wmr_protect,
	wmr_,
	por_,
	cmp_slow_sync_en,
	slow_cmp_sync_en,
	tcu_clk_stop,
	tcu_pce_ov,
	rst_wmr_protect,
	rst_wmr_,
	rst_por_,
	ccu_cmp_slow_sync_en,
	ccu_slow_cmp_sync_en,
	tcu_div_bypass,
	ccu_div_ph,
	cluster_div_en,
	gclk,
	cluster_arst_l,
	clk_ext,
	ccu_serdes_dtm,
	tcu_aclk,
	tcu_bclk,
	scan_en,
	scan_in
);

 
// ************************** 
// port declaration 
// ************************** 

// clock & test out
output	l2clk;	// assume we do not need aclk, bclk outputs
output	aclk;	// buffered version of aclk
output	bclk;	// buffered version of bclk
output	scan_out;		// unused as of today - feb 10, 05
output  aclk_wmr;

// pipelined out
output	pce_ov;				// pce override to l1 header
output	wmr_protect;		// warm reset protect
output	wmr_;				// warm reset (active low) 
output	por_;				// power-on-reset 
output	cmp_slow_sync_en;	// cmp->slow clk sync pulse
output	slow_cmp_sync_en;	// slow->cmp clk sync pulse
// output	io2x_sync_en;		// cmp<->io2x clk sync pulse
// output	dr_sync_en;			// cmp<->dr clk sync pulse

// ctrl in (for pipelining)
output	array_wr_inhibit;
input	tcu_atpg_mode;
input	tcu_wr_inhibit;
input	tcu_clk_stop;
input	tcu_pce_ov;
input	rst_wmr_protect;		
input	rst_wmr_;		
input	rst_por_;
input	ccu_cmp_slow_sync_en;
input	ccu_slow_cmp_sync_en;
// input 	ccu_io2x_sync_en;		
// input 	ccu_dr_sync_en;			

// ctrl in (for clock gen) 
input	tcu_div_bypass;		// bypasses clk divider to mux in ext clk
input	ccu_div_ph;			// phase signal from ccu (div/4 or div/2)
input   cluster_div_en;		// if enabled, l2clk is divided down 

// clock & test in
input	gclk;			// global clk - this is either cmp or dr
input	cluster_arst_l;
input 	ccu_serdes_dtm;
input	clk_ext;		// external clk muxed in for ioclk bypass 
input	scan_en;		// unused as of today - feb 10, 05
input	scan_in;		// unused as of today - feb 10, 05
input	tcu_aclk;				
input	tcu_bclk;


// ************************** 
// wire declaration 
// ************************** 
wire	array_wr_inhibit;
wire	tcu_atpg_mode;
wire	tcu_wr_inhibit;
wire	l2clk;	
wire	aclk;
wire	bclk;
wire	scan_out;
wire	aclk_wmr;	
wire	pce_ov;
wire	wmr_protect;
wire	wmr_;
wire	por_;
wire	cmp_slow_sync_en;
wire	slow_cmp_sync_en;
// wire	io2x_sync_en;		
// wire	dr_sync_en;			
wire	tcu_clk_stop;
wire	tcu_pce_ov;
wire	rst_wmr_protect;
wire	rst_wmr_;
wire	rst_por_;
wire	ccu_cmp_slow_sync_en;
wire	ccu_slow_cmp_sync_en;
// wire	ccu_io2x_sync_en;		
// wire	ccu_dr_sync_en;			
wire	tcu_div_bypass;
wire	ccu_div_ph;
wire	cluster_div_en;
wire	gclk;
wire	cluster_arst_l;
wire	clk_ext;
wire	ccu_serdes_dtm;
wire	scan_en;				
wire	scan_in;				
wire	tcu_aclk;				
wire	tcu_bclk;

wire	cclk;
	

// ************************** 
// instantiations
// ************************** 

// needs a few edits to cluster header def - mahmud.hassan 
// modified custom cell name for avoiding 
// collision with sparc core and other clusters - mhassan
n2_clk_clstr_hdr_cust xcluster_header (
	.gclk (gclk),
	.l2clk (l2clk),
	.cluster_arst_l (cluster_arst_l),
	.ccu_div_ph (ccu_div_ph),
	.cluster_div_en (cluster_div_en),	
	.tcu_div_bypass (tcu_div_bypass),
	// .clk_ext (clk_ext),
	// .ccu_serdes_dtm (ccu_serdes_dtm),
	.scan_in (scan_in),
	.scan_en (scan_en),
	.tcu_aclk (tcu_aclk),
	.tcu_bclk (tcu_bclk),
	.ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en),
	.ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en),
	// .ccu_io2x_sync_en 		(ccu_io2x_sync_en ),		
	// .ccu_dr_sync_en 		(ccu_dr_sync_en ),		
	.tcu_pce_ov (tcu_pce_ov),
	.tcu_clk_stop (tcu_clk_stop),
	.rst_por_ (rst_por_),
	.rst_wmr_ (rst_wmr_),
	.rst_wmr_protect (rst_wmr_protect),
	.aclk_wmr (aclk_wmr),
	.aclk (aclk),
	.bclk (bclk),
	.cmp_slow_sync_en (cmp_slow_sync_en),
	.slow_cmp_sync_en (slow_cmp_sync_en),
	// .io2x_sync_en 			(io2x_sync_en ),			
	// .dr_sync_en 			(dr_sync_en ),			
	.pce_ov (pce_ov),
	.por_ (por_),
	.wmr_ (wmr_),
	.wmr_protect (wmr_protect),
	.scan_out (scan_out),
	.array_wr_inhibit (array_wr_inhibit),
	.tcu_atpg_mode (tcu_atpg_mode),
	.tcu_wr_inhibit (tcu_wr_inhibit),
	.cclk (cclk)
);


// cclk -> l2clk from right 
n2_clk_spc_cmp_cust xright (
     .l2clk         (l2clk),
     .cclk          (cclk) 
);


// cclk -> l2clk from left 
n2_clk_spc_cmp_cust xleft (
     .l2clk         (l2clk),
     .cclk          (cclk) 
);

endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_stb_cm_64x45_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_stb_cm_64x45_cust (
  stb_cam_rw_ptr, 
  stb_cam_rw_tid, 
  stb_cam_wptr_vld, 
  stb_cam_rptr_vld, 
  stb_camwr_data, 
  stb_cam_vld, 
  stb_cam_cm_tid, 
  stb_cam_line_en, 
  stb_quad_ld_cam, 
  stb_rdata_ramc, 
  stb_ld_partial_raw, 
  stb_cam_hit_ptr, 
  stb_cam_hit, 
  stb_cam_mhit, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  tcu_array_wr_inhibit, 
  pce, 
  scan_out);
wire l1clk_in;
wire l1clk_out;
wire l1clk_free;
wire [44:0] stb_rdata;
wire [44:0] stb_rdata_;
wire [44:0] stb_rdata_ramc_;
wire dff_out_mask_scanin;
wire dff_out_mask_scanout;
wire mo_din_scanin;
wire mo_din_scanout;
wire [2:0] cam_rw_tid;
wire [2:0] cam_rw_ptr;
wire rptr_vld;
wire wptr_vld;
wire [7:0] mo_din_q_unused;
wire [7:0] mo_din_q_l_unused;
wire [7:0] mo_din_mq_l_unused;
wire cam_vld_din_scanin;
wire cam_vld_din_scanout;
wire cam_vld;
wire cam_vld_din_q_unused;
wire cam_vld_din_q_l_unused;
wire cam_tid_din_scanin;
wire cam_tid_din_scanout;
wire [2:0] cam_cm_tid;
wire dff_out_addr_scanin;
wire dff_out_addr_scanout;
wire [45:0] camwr_din_scanin;
wire [45:0] camwr_din_scanout;
wire [44:0] camwr_data;
wire cam_ldq;
wire [45:0] camwr_din_q_unused;
wire [45:0] camwr_din_q_l_unused;


input	[2:0]	stb_cam_rw_ptr ;	// wr pointer for single port.
input	[2:0]	stb_cam_rw_tid ;	// thread id for rw.
input		stb_cam_wptr_vld ;	// write pointer vld
input		stb_cam_rptr_vld ;	// read pointer vld

input	[44:0]	stb_camwr_data ;	// data for compare/write
input		stb_cam_vld ;		// cam is required.
input	[2:0]	stb_cam_cm_tid ;	// thread id for cam operation.
input	[7:0]	stb_cam_line_en;	// mask for squashing cam results (unflopped input)

input		stb_quad_ld_cam ; 	// quad-ld cam.


output	[44:0]	stb_rdata_ramc ;  // rd data from CAM RAM.
output		stb_ld_partial_raw ; // ld with partial raw.
output	[2:0]	stb_cam_hit_ptr ;
output		stb_cam_hit ;	  // any hit in stb
output		stb_cam_mhit ;	  // multiple hits in stb	

input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_scan_en;
input		tcu_se_scancollar_in;
input		tcu_se_scancollar_out;
input		tcu_array_wr_inhibit;
input		pce;
output		scan_out;

`ifndef FPGA
// synopsys translate_off
`endif

wire pce_ov = tcu_pce_ov;
wire stop   = 1'b0;
wire siclk  = tcu_aclk ;
wire soclk  = tcu_bclk;

integer	i,l;

//================================================
// Clock headers
//================================================
n2_stb_cm_64x45_cust_l1clkhdr_ctl_macro l1ch_in (
	.l2clk	(l2clk), 
	.l1en 	(pce), 
	.se	(tcu_se_scancollar_in),
	.l1clk	(l1clk_in),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_stb_cm_64x45_cust_l1clkhdr_ctl_macro l1ch_out (
	.l2clk	(l2clk), 
	.l1en 	(pce), 
	.se	(tcu_se_scancollar_out),
	.l1clk	(l1clk_out),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_stb_cm_64x45_cust_l1clkhdr_ctl_macro l1ch_free (
	.l2clk	(l2clk), 
	.l1en 	(pce), 
	.se	(tcu_scan_en),
	.l1clk	(l1clk_free),
  .pce_ov(pce_ov),
  .stop(stop)
);

///////////////////////////////////////////////////////////////
// Input/output flops/latches
///////////////////////////////////////////////////////////////

// Output flops are inverted.
n2_stb_cm_64x45_cust_inv_macro__width_45 rdata_in_inv  (
	.din	(stb_rdata[44:0]),
	.dout	(stb_rdata_[44:0])
);
n2_stb_cm_64x45_cust_inv_macro__width_45 rdata_out_inv  (
	.din	(stb_rdata_ramc_[44:0]),
	.dout	(stb_rdata_ramc[44:0])
);

n2_stb_cm_64x45_cust_msff_ctl_macro__width_8 dff_out_mask  (
	.scan_in(dff_out_mask_scanin),
	.scan_out(dff_out_mask_scanout),
	.l1clk	(l1clk_out),
	.din	(stb_rdata_[7:0]),
	.dout	(stb_rdata_ramc_[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_stb_cm_64x45_cust_sram_msff_mo_macro__width_8 mo_din  (
	.scan_in(mo_din_scanin),
	.scan_out(mo_din_scanout),
	.l1clk	(l1clk_in),
	.and_clk(l1clk_free),
	.d	({stb_cam_rw_tid[2:0],stb_cam_rw_ptr[2:0],stb_cam_rptr_vld,stb_cam_wptr_vld}),
	.mq	({cam_rw_tid[2:0],    cam_rw_ptr[2:0],    rptr_vld,        wptr_vld}),
	.q	(mo_din_q_unused[7:0]),
	.q_l	( mo_din_q_l_unused[7:0]),
	.mq_l	( mo_din_mq_l_unused[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_stb_cm_64x45_cust_scm_msff_lat_macro__width_1 cam_vld_din  (
	.scan_in(cam_vld_din_scanin),
	.scan_out(cam_vld_din_scanout),
	.l1clk	(l1clk_in),
	.d	(stb_cam_vld),
	.latout	(cam_vld),
	.q	( cam_vld_din_q_unused),
	.q_l	( cam_vld_din_q_l_unused),
  .siclk(siclk),
  .soclk(soclk)   
);

n2_stb_cm_64x45_cust_msff_ctl_macro__width_3 cam_tid_din  (
	.scan_in(cam_tid_din_scanin),
	.scan_out(cam_tid_din_scanout),
	.l1clk	(l1clk_in),
	.din	(stb_cam_cm_tid[2:0]),
	.dout	(cam_cm_tid[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_stb_cm_64x45_cust_msff_ctl_macro__width_37 dff_out_addr  (
	.scan_in(dff_out_addr_scanin),
	.scan_out(dff_out_addr_scanout),
	.l1clk	(l1clk_out),
	.din	(stb_rdata_[44:8]),
	.dout	(stb_rdata_ramc_[44:8]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_stb_cm_64x45_cust_scm_msff_lat_macro__fs_1__width_46 camwr_din   (
	.scan_in(camwr_din_scanin[45:0]),
	.scan_out(camwr_din_scanout[45:0]),
	.l1clk	(l1clk_in),
	.d	({stb_camwr_data[44:0],stb_quad_ld_cam}),
	.latout	({    camwr_data[44:0],cam_ldq}),
	.q	(camwr_din_q_unused[45:0]),
	.q_l	(camwr_din_q_l_unused[45:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// 0in bits_on -var {wptr_vld,rptr_vld} -max 1
// 0in bits_on -var {wptr_vld,cam_vld} -max 1

n2_stb_cm_64x45_array cam_array (
	.cam_line_en	(stb_cam_line_en[7:0]),
	.clk		(l1clk_free),
  .cam_rw_ptr(cam_rw_ptr[2:0]),
  .cam_rw_tid(cam_rw_tid[2:0]),
  .wptr_vld(wptr_vld),
  .rptr_vld(rptr_vld),
  .camwr_data(camwr_data[44:0]),
  .cam_vld(cam_vld),
  .cam_cm_tid(cam_cm_tid[2:0]),
  .cam_ldq(cam_ldq),
  .stb_rdata(stb_rdata[44:0]),
  .stb_ld_partial_raw(stb_ld_partial_raw),
  .stb_cam_hit_ptr(stb_cam_hit_ptr[2:0]),
  .stb_cam_hit(stb_cam_hit),
  .stb_cam_mhit(stb_cam_mhit),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit),
  .siclk(siclk)
);


supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_out_mask_scanin       = scan_in                  ;
assign mo_din_scanin             = dff_out_mask_scanout     ;
assign cam_vld_din_scanin        = mo_din_scanout           ;
assign cam_tid_din_scanin        = cam_vld_din_scanout      ;
assign dff_out_addr_scanin       = cam_tid_din_scanout      ;
assign camwr_din_scanin[0]       = dff_out_addr_scanout     ;
assign camwr_din_scanin[9]       = camwr_din_scanout[0]     ;
assign camwr_din_scanin[10]      = camwr_din_scanout[9]     ;
assign camwr_din_scanin[11]      = camwr_din_scanout[10]     ;
assign camwr_din_scanin[12]      = camwr_din_scanout[11]     ;
assign camwr_din_scanin[13]      = camwr_din_scanout[12]     ;
assign camwr_din_scanin[14]      = camwr_din_scanout[13]     ;
assign camwr_din_scanin[15]      = camwr_din_scanout[14]     ;
assign camwr_din_scanin[16]      = camwr_din_scanout[15]     ;
assign camwr_din_scanin[17]      = camwr_din_scanout[16]     ;
assign camwr_din_scanin[18]      = camwr_din_scanout[17]     ;
assign camwr_din_scanin[19]      = camwr_din_scanout[18]     ;
assign camwr_din_scanin[20]      = camwr_din_scanout[19]     ;
assign camwr_din_scanin[21]      = camwr_din_scanout[20]     ;
assign camwr_din_scanin[22]      = camwr_din_scanout[21]     ;
assign camwr_din_scanin[23]      = camwr_din_scanout[22]     ;
assign camwr_din_scanin[24]      = camwr_din_scanout[23]     ;
assign camwr_din_scanin[25]      = camwr_din_scanout[24]     ;
assign camwr_din_scanin[26]      = camwr_din_scanout[25]     ;
assign camwr_din_scanin[27]      = camwr_din_scanout[26]     ;
assign camwr_din_scanin[28]      = camwr_din_scanout[27]     ;
assign camwr_din_scanin[29]      = camwr_din_scanout[28]     ;
assign camwr_din_scanin[30]      = camwr_din_scanout[29]     ;
assign camwr_din_scanin[31]      = camwr_din_scanout[30]     ;
assign camwr_din_scanin[32]      = camwr_din_scanout[31]     ;
assign camwr_din_scanin[33]      = camwr_din_scanout[32]     ;
assign camwr_din_scanin[34]      = camwr_din_scanout[33]     ;
assign camwr_din_scanin[35]      = camwr_din_scanout[34]     ;
assign camwr_din_scanin[36]      = camwr_din_scanout[35]     ;
assign camwr_din_scanin[37]      = camwr_din_scanout[36]     ;
assign camwr_din_scanin[38]      = camwr_din_scanout[37]     ;
assign camwr_din_scanin[39]      = camwr_din_scanout[38]     ;
assign camwr_din_scanin[40]      = camwr_din_scanout[39]     ;
assign camwr_din_scanin[41]      = camwr_din_scanout[40]     ;
assign camwr_din_scanin[42]      = camwr_din_scanout[41]     ;
assign camwr_din_scanin[43]      = camwr_din_scanout[42]     ;
assign camwr_din_scanin[44]      = camwr_din_scanout[43]     ;
assign camwr_din_scanin[45]      = camwr_din_scanout[44]     ;
assign camwr_din_scanin[1]       = camwr_din_scanout[45]     ;
assign camwr_din_scanin[2]       = camwr_din_scanout[1]     ;
assign camwr_din_scanin[3]       = camwr_din_scanout[2]     ;
assign camwr_din_scanin[4]       = camwr_din_scanout[3]     ;
assign camwr_din_scanin[5]       = camwr_din_scanout[4]     ;
assign camwr_din_scanin[6]       = camwr_din_scanout[5]     ;
assign camwr_din_scanin[7]       = camwr_din_scanout[6]     ;
assign camwr_din_scanin[8]       = camwr_din_scanout[7]     ;
assign scan_out                  = camwr_din_scanout[8]     ;
// fixscan end:

`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_stb_cm_64x45_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   invert macro
//
//


module n2_stb_cm_64x45_cust_inv_macro__width_45 (
  din, 
  dout);
  input [44:0] din;
  output [44:0] dout;


inv #(45)  d0_0 (
.in(din[44:0]),
.out(dout[44:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_stb_cm_64x45_cust_msff_ctl_macro__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;
wire [6:0] so;

  input [7:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.q(dout[7:0])
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_stb_cm_64x45_cust_sram_msff_mo_macro__width_8 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
wire [6:0] so;

input [7:0] d;
  input scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [7:0] mq;
output [7:0] mq_l;
  output scan_out;
output [7:0] q;
output [7:0] q_l;


new_dlata #(8)  d0_0 (
.d(d[7:0]),
.si({scan_in,so[6:0]}),
.so({so[6:0],scan_out}),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[7:0]),
.q_l(q_l[7:0]),
.mq(mq[7:0]),
.mq_l(mq_l[7:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_scm_msff_lat_{4}x flops
//
//


module n2_stb_cm_64x45_cust_scm_msff_lat_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  latout, 
  scan_out, 
  q, 
  q_l);
input [0:0] d;
  input scan_in;
input l1clk;
input siclk;
input soclk;
output [0:0] latout;
  output scan_out;
output [0:0] q;
output [0:0] q_l;


scm_msff_lat #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.q(q[0:0]),
.q_l(q_l[0:0]),
.latout(latout[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_stb_cm_64x45_cust_msff_ctl_macro__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;
wire [1:0] so;

  input [2:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_stb_cm_64x45_cust_msff_ctl_macro__width_37 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [36:0] fdin;
wire [35:0] so;

  input [36:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [36:0] dout;
  output scan_out;
assign fdin[36:0] = din[36:0];


dff #(37)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[36:0]),
.si({scan_in,so[35:0]}),
.so({so[35:0],scan_out}),
.q(dout[36:0])
);


endmodule


//
//   macro for cl_mc1_scm_msff_lat_{4}x flops
//
//


module n2_stb_cm_64x45_cust_scm_msff_lat_macro__fs_1__width_46 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  latout, 
  scan_out, 
  q, 
  q_l);
input [45:0] d;
  input [45:0] scan_in;
input l1clk;
input siclk;
input soclk;
output [45:0] latout;
  output [45:0] scan_out;
output [45:0] q;
output [45:0] q_l;


scm_msff_lat #(46)  d0_0 (
.d(d[45:0]),
.si(scan_in[45:0]),
.so(scan_out[45:0]),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.q(q[45:0]),
.q_l(q_l[45:0]),
.latout(latout[45:0])
);


//place::generic_place($width,$stack,$left);

endmodule


`ifndef FPGA
module n2_stb_cm_64x45_array (
  cam_rw_ptr, 
  cam_rw_tid, 
  wptr_vld, 
  rptr_vld, 
  camwr_data, 
  cam_vld, 
  cam_cm_tid, 
  cam_line_en, 
  cam_ldq, 
  stb_rdata, 
  stb_ld_partial_raw, 
  stb_cam_hit_ptr, 
  stb_cam_hit, 
  stb_cam_mhit, 
  clk, 
  tcu_array_wr_inhibit, 
  siclk);
wire [5:0] rw_addr;
wire write_vld;
wire read_vld;
wire [7:0] byte_overlap_mx;
wire [7:0] byte_match_mx;
wire [7:0] ptag_hit_mx;
wire [7:0] cam_hit;


input	[2:0]	cam_rw_ptr ;	// wr pointer for single port.
input	[2:0]	cam_rw_tid ;	// thread id for rw.
input		wptr_vld ;	// write pointer vld
input		rptr_vld ;	// read pointer vld

input	[44:0]	camwr_data ;	// data for compare/write
input		cam_vld ;	// cam is required.
input	[2:0]	cam_cm_tid ;	// thread id for cam operation.
input	[7:0]	cam_line_en;	// mask for squashing cam results (unflopped input)

input		cam_ldq ; 	// quad-ld cam.


output	[44:0]	stb_rdata;	// rd data from CAM RAM.
output		stb_ld_partial_raw ; // ld with partial raw.
output	[2:0]	stb_cam_hit_ptr ;
output		stb_cam_hit ;	  // any hit in stb
output		stb_cam_mhit ;	  // multiple hits in stb	

input		clk;
input		tcu_array_wr_inhibit;
input		siclk;

integer	i,l;

///////////////////////////////////////////////////////////////
// The array
///////////////////////////////////////////////////////////////

reg	[44:0]	stb_ramc[63:0];
reg	[44:0]	stb_rdata;

//=========================================================================================
//	initialize array
//=========================================================================================

`ifndef NOINITMEM
initial begin
  for (i=0;i<64;i=i+1) begin
  stb_ramc[i] =  45'd0;
  end
end
`endif

assign rw_addr[5:0] = {cam_rw_tid[2:0],cam_rw_ptr[2:0]};

assign write_vld = wptr_vld & ~tcu_array_wr_inhibit;
assign read_vld  = rptr_vld & ~tcu_array_wr_inhibit;

///////////
// Write
///////////
always @ (clk or write_vld or rw_addr or camwr_data or cam_vld) begin
    if (clk & write_vld) begin
        if (cam_vld)
            stb_ramc[rw_addr] <= 45'hx;
	else
            stb_ramc[rw_addr] <= camwr_data[44:0];
    end
end


///////////
// Read
///////////

always @(clk or read_vld or rw_addr or write_vld) begin
    if (clk) begin
	if (write_vld | ~read_vld)
		stb_rdata[44:0] <= 45'hx;
	else
		stb_rdata[44:0] <= stb_ramc[rw_addr];
    end
end

//=========================================================================================
//	CAM contents
//=========================================================================================

// - Generate full/partial raw for incoming load.
// - Output signals need to be qualified with per entry
// vlds before causing any subsequent event, the read of
// the DATA RAM specifically.

// Mapping of cam/write data
// 
//	| 	39-3=37b(pa)	|	8b(bytemask)	| <- use
//	|	44:8		|	7:0		| <- input port

reg	[44:0]	ramc_entry;
reg	[36:0]	cam_tag;
reg	[7:0]	cam_bmask;
reg	[63:0]	ptag_hit;
reg	[63:0]	byte_match;
reg	[63:0]	byte_overlap;

// ptag_hit indicates a match at the dword (or qword for quad loads) boundary
// byte_match indciates match at the byte level within the dword
// byte_overlap checks that all bytes in incoming bmask has a corresponding mask bit
//  set in the cam entry.  This differentiates between full and partial raw.

always @(posedge clk) begin
  for (l=0;l<64;l=l+1) begin
    ramc_entry[44:0] = stb_ramc[l] ;
    cam_tag[36:0] = ramc_entry[44:8] ;
    cam_bmask[7:0] = ramc_entry[7:0] ;
    ptag_hit[l] <= (cam_tag[36:1] == camwr_data[44:9]) & (((cam_tag[0] == camwr_data[8]) & ~cam_ldq) | cam_ldq) & cam_vld;
    byte_match[l] <= |(cam_bmask[7:0] & camwr_data[7:0]) & cam_vld;
    byte_overlap[l] <= |(~cam_bmask[7:0] & camwr_data[7:0]) & cam_vld ;
  end	
end

// CAM values will be indeterminate while scanning

always @(posedge siclk) begin
    ptag_hit[63:0] <= 64'hx; 
    byte_match[63:0] <= 64'hx; 
    byte_overlap[63:0] <= 64'hx; 
end


// Mux the raw signals down to 8b quantities. Line enable comes mid-way thru cycle.

assign	byte_overlap_mx[7:0] =
	({8{(cam_cm_tid[2:0] == 3'b000)}} & byte_overlap[7:0]  ) | 
	({8{(cam_cm_tid[2:0] == 3'b001)}} & byte_overlap[15:8] ) |
	({8{(cam_cm_tid[2:0] == 3'b010)}} & byte_overlap[23:16]) |
	({8{(cam_cm_tid[2:0] == 3'b011)}} & byte_overlap[31:24]) |
	({8{(cam_cm_tid[2:0] == 3'b100)}} & byte_overlap[39:32]) |
	({8{(cam_cm_tid[2:0] == 3'b101)}} & byte_overlap[47:40]) |
	({8{(cam_cm_tid[2:0] == 3'b110)}} & byte_overlap[55:48]) |
	({8{(cam_cm_tid[2:0] == 3'b111)}} & byte_overlap[63:56]) ;

assign	byte_match_mx[7:0] =
	({8{(cam_cm_tid[2:0] == 3'b000)}} & byte_match[7:0]  ) |
	({8{(cam_cm_tid[2:0] == 3'b001)}} & byte_match[15:8] ) |
	({8{(cam_cm_tid[2:0] == 3'b010)}} & byte_match[23:16]) |
	({8{(cam_cm_tid[2:0] == 3'b011)}} & byte_match[31:24]) |
	({8{(cam_cm_tid[2:0] == 3'b100)}} & byte_match[39:32]) |
	({8{(cam_cm_tid[2:0] == 3'b101)}} & byte_match[47:40]) |
	({8{(cam_cm_tid[2:0] == 3'b110)}} & byte_match[55:48]) |
	({8{(cam_cm_tid[2:0] == 3'b111)}} & byte_match[63:56]) ;

assign	ptag_hit_mx[7:0] =
	({8{(cam_cm_tid[2:0] == 3'b000)}} & ptag_hit[7:0]  ) |
	({8{(cam_cm_tid[2:0] == 3'b001)}} & ptag_hit[15:8] ) |
	({8{(cam_cm_tid[2:0] == 3'b010)}} & ptag_hit[23:16]) |
	({8{(cam_cm_tid[2:0] == 3'b011)}} & ptag_hit[31:24]) |
	({8{(cam_cm_tid[2:0] == 3'b100)}} & ptag_hit[39:32]) |
	({8{(cam_cm_tid[2:0] == 3'b101)}} & ptag_hit[47:40]) |
	({8{(cam_cm_tid[2:0] == 3'b110)}} & ptag_hit[55:48]) |
	({8{(cam_cm_tid[2:0] == 3'b111)}} & ptag_hit[63:56]) ;

assign	stb_ld_partial_raw =  
	|(ptag_hit_mx[7:0] & byte_match_mx[7:0] &  byte_overlap_mx[7:0] & cam_line_en[7:0]) ;

assign	cam_hit[7:0] = 
	ptag_hit_mx[7:0] & byte_match_mx[7:0] & cam_line_en[7:0] ;
assign	stb_cam_hit = |(cam_hit[7:0]);

// The stb data is meant to be read for single hit full raw case. It may actually be read
// for full raw, partial raw or multiple hit case but the read output will be ignored for
// partial and multiple hit case. Multiple hits will not cause a hazard as the ptr is first
// encoded and then decoded to form the wdline for the stb-data
// Use cam_hit result to void false hits.
assign	stb_cam_hit_ptr[0] 	=  cam_hit[1] | cam_hit[3] | cam_hit[5] | cam_hit[7] ;
assign	stb_cam_hit_ptr[1] 	=  cam_hit[2] | cam_hit[3] | cam_hit[6] | cam_hit[7] ;
assign	stb_cam_hit_ptr[2] 	=  cam_hit[4] | cam_hit[5] | cam_hit[6] | cam_hit[7] ;

//Generating multiple hits
assign  stb_cam_mhit            =  (cam_hit[0]  & cam_hit[1]) | (cam_hit[2] & cam_hit[3])  |
                                   (cam_hit[4]  & cam_hit[5]) | (cam_hit[6] & cam_hit[7])  |
                                   ((cam_hit[0] | cam_hit[1]) & (cam_hit[2] | cam_hit[3])) |
                                   ((cam_hit[4] | cam_hit[5]) & (cam_hit[6] | cam_hit[7])) |
                                   ((|cam_hit[3:0]) & (|cam_hit[7:4]));

supply0 vss;
supply1 vdd;
endmodule
`endif


`ifdef FPGA

module n2_stb_cm_64x45_array(cam_rw_ptr, cam_rw_tid, wptr_vld, rptr_vld, 
	camwr_data, cam_vld, cam_cm_tid, cam_line_en, cam_ldq, stb_rdata, 
	stb_ld_partial_raw, stb_cam_hit_ptr, stb_cam_hit, stb_cam_mhit, clk, 
	tcu_array_wr_inhibit, siclk);

	input	[2:0]		cam_rw_ptr;
	input	[2:0]		cam_rw_tid;
	input			wptr_vld;
	input			rptr_vld;
	input	[44:0]		camwr_data;
	input			cam_vld;
	input	[2:0]		cam_cm_tid;
	input	[7:0]		cam_line_en;
	input			cam_ldq;
	output	[44:0]		stb_rdata;
	output			stb_ld_partial_raw;
	output	[2:0]		stb_cam_hit_ptr;
	output			stb_cam_hit;
	output			stb_cam_mhit;
	input			clk;
	input			tcu_array_wr_inhibit;
	input			siclk;

	wire	[5:0]		rw_addr;
	wire			write_vld;
	wire			read_vld;
	wire	[7:0]		byte_overlap_mx;
	wire	[7:0]		byte_match_mx;
	wire	[7:0]		ptag_hit_mx;
	wire	[7:0]		cam_hit;
	integer			i;
	integer			l;

	reg	[44:0]		stb_ramc[63:0];
	reg	[44:0]		stb_rdata;
	reg	[44:0]		ramc_entry;
	reg	[36:0]		cam_tag;
	reg	[7:0]		cam_bmask;
	reg	[63:0]		ptag_hit;
	reg	[63:0]		byte_match;
	reg	[63:0]		byte_overlap;
	supply0			vss;
	supply1			vdd;

	assign rw_addr[5:0] = {cam_rw_tid[2:0], cam_rw_ptr[2:0]};
	assign write_vld = (wptr_vld & (~tcu_array_wr_inhibit));
	assign read_vld = (rptr_vld & (~tcu_array_wr_inhibit));
	assign byte_overlap_mx[7:0] = (((((((({8 {(cam_cm_tid[2:0] == 3'b0)}} & 
		byte_overlap[7:0]) | ({8 {(cam_cm_tid[2:0] == 3'b1)}} & 
		byte_overlap[15:8])) | ({8 {(cam_cm_tid[2:0] == 3'd2)}} & 
		byte_overlap[23:16])) | ({8 {(cam_cm_tid[2:0] == 3'd3)}} & 
		byte_overlap[31:24])) | ({8 {(cam_cm_tid[2:0] == 3'd4)}} & 
		byte_overlap[39:32])) | ({8 {(cam_cm_tid[2:0] == 3'd5)}} & 
		byte_overlap[47:40])) | ({8 {(cam_cm_tid[2:0] == 3'd6)}} & 
		byte_overlap[55:48])) | ({8 {(cam_cm_tid[2:0] == 3'd7)}} & 
		byte_overlap[63:56]));
	assign byte_match_mx[7:0] = (((((((({8 {(cam_cm_tid[2:0] == 3'b0)}} & 
		byte_match[7:0]) | ({8 {(cam_cm_tid[2:0] == 3'b1)}} & 
		byte_match[15:8])) | ({8 {(cam_cm_tid[2:0] == 3'd2)}} & 
		byte_match[23:16])) | ({8 {(cam_cm_tid[2:0] == 3'd3)}} & 
		byte_match[31:24])) | ({8 {(cam_cm_tid[2:0] == 3'd4)}} & 
		byte_match[39:32])) | ({8 {(cam_cm_tid[2:0] == 3'd5)}} & 
		byte_match[47:40])) | ({8 {(cam_cm_tid[2:0] == 3'd6)}} & 
		byte_match[55:48])) | ({8 {(cam_cm_tid[2:0] == 3'd7)}} & 
		byte_match[63:56]));
	assign ptag_hit_mx[7:0] = (((((((({8 {(cam_cm_tid[2:0] == 3'b0)}} & 
		ptag_hit[7:0]) | ({8 {(cam_cm_tid[2:0] == 3'b1)}} & 
		ptag_hit[15:8])) | ({8 {(cam_cm_tid[2:0] == 3'd2)}} & 
		ptag_hit[23:16])) | ({8 {(cam_cm_tid[2:0] == 3'd3)}} & 
		ptag_hit[31:24])) | ({8 {(cam_cm_tid[2:0] == 3'd4)}} & 
		ptag_hit[39:32])) | ({8 {(cam_cm_tid[2:0] == 3'd5)}} & 
		ptag_hit[47:40])) | ({8 {(cam_cm_tid[2:0] == 3'd6)}} & 
		ptag_hit[55:48])) | ({8 {(cam_cm_tid[2:0] == 3'd7)}} & 
		ptag_hit[63:56]));
	assign stb_ld_partial_raw = (|(((ptag_hit_mx[7:0] & byte_match_mx[7:0]) 
		& byte_overlap_mx[7:0]) & cam_line_en[7:0]));
	assign cam_hit[7:0] = ((ptag_hit_mx[7:0] & byte_match_mx[7:0]) & 
		cam_line_en[7:0]);
	assign stb_cam_hit = (|cam_hit[7:0]);
	assign stb_cam_hit_ptr[0] = (((cam_hit[1] | cam_hit[3]) | cam_hit[5]) | 
		cam_hit[7]);
	assign stb_cam_hit_ptr[1] = (((cam_hit[2] | cam_hit[3]) | cam_hit[6]) | 
		cam_hit[7]);
	assign stb_cam_hit_ptr[2] = (((cam_hit[4] | cam_hit[5]) | cam_hit[6]) | 
		cam_hit[7]);
	assign stb_cam_mhit = (((((((cam_hit[0] & cam_hit[1]) | (cam_hit[2] & 
		cam_hit[3])) | (cam_hit[4] & cam_hit[5])) | (cam_hit[6] & 
		cam_hit[7])) | ((cam_hit[0] | cam_hit[1]) & (cam_hit[2] | 
		cam_hit[3]))) | ((cam_hit[4] | cam_hit[5]) & (cam_hit[6] | 
		cam_hit[7]))) | ((|cam_hit[3:0]) & (|cam_hit[7:4])));

	initial begin
	  for (i = 0; (i < 64); i = (i + 1)) begin
	    stb_ramc[i] = 45'b0;
	  end
	end
	always @(clk or write_vld or rw_addr or camwr_data or cam_vld) begin
	  if (clk & write_vld) begin
	    if (cam_vld) begin
	      stb_ramc[rw_addr] <= 45'hxxxxxxxxxxxx;
	    end
	    else begin
	      stb_ramc[rw_addr] <= camwr_data[44:0];
	    end
	  end
	end
	always @(clk or read_vld or rw_addr or write_vld) begin
	  if (clk) begin
	    if (write_vld | (~read_vld)) begin
	      stb_rdata[44:0] <= 45'hxxxxxxxxxxxx;
	    end
	    else begin
	      stb_rdata[44:0] <= stb_ramc[rw_addr];
	    end
	  end
	end
	always @(posedge clk) begin
	  for (l = 0; (l < 64); l = (l + 1)) begin
	    ramc_entry[44:0] = stb_ramc[l];
	    cam_tag[36:0] = ramc_entry[44:8];
	    cam_bmask[7:0] = ramc_entry[7:0];
	    ptag_hit[l] <= (((cam_tag[36:1] == camwr_data[44:9]) & (((cam_tag[0]
		    == camwr_data[8]) & (~cam_ldq)) | cam_ldq)) & cam_vld);
	    byte_match[l] <= ((|(cam_bmask[7:0] & camwr_data[7:0])) & cam_vld);
	    byte_overlap[l] <= ((|((~cam_bmask[7:0]) & camwr_data[7:0])) & 
		    cam_vld);
	  end
	end
endmodule

`endif	// `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_com_dp_32x152_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_com_dp_32x152_cust (
  wr_adr, 
  wr_en, 
  rd_adr, 
  rd_en, 
  din, 
  dout, 
  rdclk, 
  wrclk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  bist_clk_mux_sel, 
  rd_pce, 
  wr_pce, 
  scan_out);
wire rd_lce;
wire wr_lce;
wire rdclk_in;
wire wrclk_in;
wire rdclk_free;
wire wrclk_free;
wire dff_wr_addr_scanin;
wire dff_wr_addr_scanout;
wire [4:0] wr_adr_d1;
wire [4:1] dff_rd_addr_scan;
wire dff_rd_addr_scanin;
wire dff_rd_addr_scanout;
wire [4:0] rd_adr_d1;
wire [4:0] rd_adr_mq_l_unused;
wire [4:0] rd_adr_q_unused;
wire [4:0] rd_adr_q_l_unused;
wire dff_rd_en_scanin;
wire dff_rd_en_scanout;
wire rd_en_d1;
wire rd_en_mq_l_unused;
wire rd_en_q_unused;
wire rd_en_q_l_unused;
wire dff_wr_en_scanin;
wire dff_wr_en_scanout;
wire wr_en_d1;
wire [75:1] dff_din_hi_scan;
wire dff_din_hi_scanin;
wire dff_din_hi_scanout;
wire [151:0] din_d1;
wire [75:1] dff_din_lo_scan;
wire dff_din_lo_scanin;
wire dff_din_lo_scanout;
wire wr_inh_;
wire rd_en_d1_qual;
wire wr_en_d1_qual;
wire [151:0] local_dout;
wire dff_dout_scanout;
wire dff_dout_scanin;
		
input	[4:0]	wr_adr;
input			wr_en;
input	[4:0]	rd_adr;
input			rd_en;
input	[151:0] 	din;
output	[151:0]	dout;
input		rdclk;
input		wrclk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_array_wr_inhibit;
input		tcu_se_scancollar_in;


input		bist_clk_mux_sel;
input		rd_pce;
input		wr_pce;
output		scan_out;

`ifndef FPGA
// synopsys translate_off
`endif

wire pce_ov	= tcu_pce_ov;
wire siclk	= tcu_aclk;
wire soclk	= tcu_bclk;
//================================================
// Clock headers
//================================================
cl_mc1_bistlatch_4x rd_pce_lat (
	.l2clk	(rdclk),
	.pce	(rd_pce),
	.pce_ov	(pce_ov),
	.lce	(rd_lce)
);
cl_mc1_bistlatch_4x wr_pce_lat (
	.l2clk	(wrclk),
	.pce	(wr_pce),
	.pce_ov	(pce_ov),
	.lce	(wr_lce)
);
cl_mc1_bistl1hdr_8x rch_in (
        .l2clk  (rdclk), 
        .se     (tcu_se_scancollar_in),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(rd_lce),
        .l1clk  (rdclk_in)
);
cl_mc1_bistl1hdr_8x wch_in (
        .l2clk  (wrclk), 
        .se     (tcu_se_scancollar_in),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(wr_lce),
        .l1clk  (wrclk_in)
);
cl_mc1_bistl1hdr_8x rch_free (
        .l2clk  (rdclk), 
        .se     (1'b0),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(rd_lce),
        .l1clk  (rdclk_free)
);
cl_mc1_bistl1hdr_8x wch_free (
        .l2clk  (wrclk), 
        .se     (1'b0),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(wr_lce),
        .l1clk  (wrclk_free)
);
 

///////////////////////////////////////////////////////////////
// Flop the inputs                                           //
///////////////////////////////////////////////////////////////
n2_com_dp_32x152_cust_msff_ctl_macro__width_5 dff_wr_addr  (
	.scan_in	(dff_wr_addr_scanin),
	.scan_out	(dff_wr_addr_scanout),
	.l1clk		(wrclk_in),
	.din		(wr_adr[4:0]),
	.dout		(wr_adr_d1[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x152_cust_sram_msff_mo_macro__fs_1__width_5 dff_rd_addr   (
	.scan_in	({dff_rd_addr_scan[4:1],dff_rd_addr_scanin}),
	.scan_out	({dff_rd_addr_scanout,dff_rd_addr_scan[4:1]}),
	.l1clk		(rdclk_in),
	.and_clk	(rdclk_in),
	.d		(rd_adr[4:0]),
	.mq		(rd_adr_d1[4:0]),
	.mq_l		(rd_adr_mq_l_unused[4:0]),
	.q		(rd_adr_q_unused[4:0]),
	.q_l		(rd_adr_q_l_unused[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x152_cust_sram_msff_mo_macro__width_1 dff_rd_en  (
	.scan_in	(dff_rd_en_scanin),
	.scan_out	(dff_rd_en_scanout),
	.l1clk		(rdclk_in),
	.and_clk	(rdclk_in),
	.d		(rd_en),
	.mq		(rd_en_d1),
	.mq_l		(rd_en_mq_l_unused),
	.q		(rd_en_q_unused),
	.q_l		(rd_en_q_l_unused),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x152_cust_msff_ctl_macro__width_1 dff_wr_en  (
	.scan_in	(dff_wr_en_scanin),
	.scan_out	(dff_wr_en_scanout),
	.l1clk		(wrclk_in),
	.din		(wr_en),
	.dout		(wr_en_d1),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x152_cust_msff_ctl_macro__fs_1__width_76 dff_din_hi   (
	.scan_in	({dff_din_hi_scan[75:1],dff_din_hi_scanin}),
	.scan_out	({dff_din_hi_scanout,dff_din_hi_scan[75:1]}),
	.l1clk		(wrclk_in),
	.din		(din[151:76]),
	.dout		(din_d1[151:76]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x152_cust_msff_ctl_macro__fs_1__width_76 dff_din_lo   (
	.scan_in	({dff_din_lo_scan[75:1],dff_din_lo_scanin}),
	.scan_out	({dff_din_lo_scanout,dff_din_lo_scan[75:1]}),
	.l1clk		(wrclk_in),
	.din		(din[75:0]),
	.dout		(din_d1[75:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x152_cust_inv_macro__width_1 wr_inh_inv  (
	.din		(tcu_array_wr_inhibit),
	.dout		(wr_inh_)
);
n2_com_dp_32x152_cust_and_macro__width_2 enable_qual  (
	.din0		({2{wr_inh_}}),
	.din1		({rd_en_d1,wr_en_d1}),
	.dout		({rd_en_d1_qual,wr_en_d1_qual})
);
n2_com_dp_32x152_cust_n2_com_array_macro__rows_32__width_152__z_array array    (
	.rclk	(rdclk_free),
	.wclk	(wrclk_free),
	.wr_adr (wr_adr_d1[4:0]),
	.wr_en	(wr_en_d1_qual),
	.rd_adr (rd_adr_d1[4:0]),
	.rd_en	(rd_en_d1_qual),
	.din	(din_d1[151:0]),
	.dout	(local_dout[151:0])
);


assign dout[151:0] = local_dout[151:0];
assign dff_dout_scanout = dff_dout_scanin;

supply0 vss;
supply1 vdd;

// fixscan start:
assign dff_din_lo_scanin          = scan_in                  ;
assign dff_wr_addr_scanin         = dff_din_lo_scanout       ;
assign dff_rd_addr_scanin         = dff_wr_addr_scanout      ;
assign dff_wr_en_scanin           = dff_rd_addr_scanout      ;
assign dff_rd_en_scanin           = dff_wr_en_scanout        ;
assign dff_din_hi_scanin          = dff_rd_en_scanout        ;
assign dff_dout_scanin            = dff_din_hi_scanout       ;
assign scan_out                   = dff_dout_scanout         ;
// fixscan end:

`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x152_cust_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_com_dp_32x152_cust_sram_msff_mo_macro__fs_1__width_5 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [4:0] d;
  input [4:0] scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [4:0] mq;
output [4:0] mq_l;
  output [4:0] scan_out;
output [4:0] q;
output [4:0] q_l;


new_dlata #(5)  d0_0 (
.d(d[4:0]),
.si(scan_in[4:0]),
.so(scan_out[4:0]),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[4:0]),
.q_l(q_l[4:0]),
.mq(mq[4:0]),
.mq_l(mq_l[4:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_com_dp_32x152_cust_sram_msff_mo_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [0:0] d;
  input scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [0:0] mq;
output [0:0] mq_l;
  output scan_out;
output [0:0] q;
output [0:0] q_l;


new_dlata #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[0:0]),
.q_l(q_l[0:0]),
.mq(mq[0:0]),
.mq_l(mq_l[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x152_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x152_cust_msff_ctl_macro__fs_1__width_76 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [75:0] fdin;

  input [75:0] din;
  input l1clk;
  input [75:0] scan_in;


  input siclk;
  input soclk;

  output [75:0] dout;
  output [75:0] scan_out;
assign fdin[75:0] = din[75:0];


dff #(76)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[75:0]),
.si(scan_in[75:0]),
.so(scan_out[75:0]),
.q(dout[75:0])
);


endmodule


//
//   invert macro
//
//


module n2_com_dp_32x152_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_com_dp_32x152_cust_and_macro__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


and2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


module n2_com_dp_32x152_cust_n2_com_array_macro__rows_32__width_152__z_array (
  rclk, 
  wclk, 
  rd_adr, 
  rd_en, 
  wr_en, 
  wr_adr, 
  din, 
  dout);

input		rclk;
input		wclk;
input	[4:0]	rd_adr;
input		rd_en;
input		wr_en;
input	[4:0]	wr_adr;
input	[152-1:0]	din;
output	[152-1:0]	dout; 


reg	[152-1:0]	mem[32-1:0];
reg	[152-1:0]	local_dout;

`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
 for (i=0; i<32; i=i+1) begin
   mem[i] = 152'b0;
 end
 local_dout = 152'b0;
end
`endif
//////////////////////
// Read/write array
//////////////////////
always @(negedge wclk) begin
   if (wr_en) begin
       mem[wr_adr] <= din;


   end
end
always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin
   if (rclk) begin
     if (rd_en) begin
         if (wr_en & (wr_adr[4:0] == rd_adr[4:0]))
             local_dout[152-1:0] <= 152'hx;
         else
             local_dout[152-1:0] <= mem[rd_adr] ;
     end
     else
             local_dout[152-1:0] <= ~(152'h0);
  end
end
assign dout[152-1:0] = local_dout[152-1:0];
supply0 vss;
supply1 vdd;


endmodule 

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_com_dp_32x72_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_com_dp_32x72_cust (
  wr_adr, 
  wr_en, 
  rd_adr, 
  rd_en, 
  din, 
  dout, 
  rdclk, 
  wrclk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  bist_clk_mux_sel, 
  rd_pce, 
  wr_pce, 
  scan_out);
wire rd_lce;
wire wr_lce;
wire rdclk_in;
wire wrclk_in;
wire rdclk_free;
wire wrclk_free;
wire dff_wr_addr_scanin;
wire dff_wr_addr_scanout;
wire [4:0] wr_adr_d1;
wire [4:1] dff_rd_addr_scan;
wire dff_rd_addr_scanin;
wire dff_rd_addr_scanout;
wire [4:0] rd_adr_d1;
wire [4:0] rd_adr_mq_l_unused;
wire [4:0] rd_adr_q_unused;
wire [4:0] rd_adr_q_l_unused;
wire dff_rd_en_scanin;
wire dff_rd_en_scanout;
wire rd_en_d1;
wire rd_en_mq_l_unused;
wire rd_en_q_unused;
wire rd_en_q_l_unused;
wire dff_wr_en_scanin;
wire dff_wr_en_scanout;
wire wr_en_d1;
wire [35:1] dff_din_hi_scan;
wire dff_din_hi_scanin;
wire dff_din_hi_scanout;
wire [71:0] din_d1;
wire [35:1] dff_din_lo_scan;
wire dff_din_lo_scanin;
wire dff_din_lo_scanout;
wire wr_inh_;
wire rd_en_d1_qual;
wire wr_en_d1_qual;
wire [71:0] local_dout;
wire dff_dout_scanout;
wire dff_dout_scanin;
		
input	[4:0]	wr_adr;
input			wr_en;
input	[4:0]	rd_adr;
input			rd_en;
input	[71:0] 	din;
output	[71:0]	dout;
input		rdclk;
input		wrclk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_array_wr_inhibit;
input		tcu_se_scancollar_in;


input		bist_clk_mux_sel;
input		rd_pce;
input		wr_pce;
output		scan_out;

`ifndef FPGA
// synopsys translate_off
`endif

wire pce_ov	= tcu_pce_ov;
wire siclk	= tcu_aclk;
wire soclk	= tcu_bclk;
//================================================
// Clock headers
//================================================
cl_mc1_bistlatch_4x rd_pce_lat (
	.l2clk	(rdclk),
	.pce	(rd_pce),
	.pce_ov	(pce_ov),
	.lce	(rd_lce)
);
cl_mc1_bistlatch_4x wr_pce_lat (
	.l2clk	(wrclk),
	.pce	(wr_pce),
	.pce_ov	(pce_ov),
	.lce	(wr_lce)
);
cl_mc1_bistl1hdr_8x rch_in (
        .l2clk  (rdclk), 
        .se     (tcu_se_scancollar_in),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(rd_lce),
        .l1clk  (rdclk_in)
);
cl_mc1_bistl1hdr_8x wch_in (
        .l2clk  (wrclk), 
        .se     (tcu_se_scancollar_in),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(wr_lce),
        .l1clk  (wrclk_in)
);
cl_mc1_bistl1hdr_8x rch_free (
        .l2clk  (rdclk), 
        .se     (1'b0),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(rd_lce),
        .l1clk  (rdclk_free)
);
cl_mc1_bistl1hdr_8x wch_free (
        .l2clk  (wrclk), 
        .se     (1'b0),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(wr_lce),
        .l1clk  (wrclk_free)
);
 

///////////////////////////////////////////////////////////////
// Flop the inputs                                           //
///////////////////////////////////////////////////////////////
n2_com_dp_32x72_cust_msff_ctl_macro__width_5 dff_wr_addr  (
	.scan_in	(dff_wr_addr_scanin),
	.scan_out	(dff_wr_addr_scanout),
	.l1clk		(wrclk_in),
	.din		(wr_adr[4:0]),
	.dout		(wr_adr_d1[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x72_cust_sram_msff_mo_macro__fs_1__width_5 dff_rd_addr   (
	.scan_in	({dff_rd_addr_scan[4:1],dff_rd_addr_scanin}),
	.scan_out	({dff_rd_addr_scanout,dff_rd_addr_scan[4:1]}),
	.l1clk		(rdclk_in),
	.and_clk	(rdclk_in),
	.d		(rd_adr[4:0]),
	.mq		(rd_adr_d1[4:0]),
	.mq_l		(rd_adr_mq_l_unused[4:0]),
	.q		(rd_adr_q_unused[4:0]),
	.q_l		(rd_adr_q_l_unused[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x72_cust_sram_msff_mo_macro__width_1 dff_rd_en  (
	.scan_in	(dff_rd_en_scanin),
	.scan_out	(dff_rd_en_scanout),
	.l1clk		(rdclk_in),
	.and_clk	(rdclk_in),
	.d		(rd_en),
	.mq		(rd_en_d1),
	.mq_l		(rd_en_mq_l_unused),
	.q		(rd_en_q_unused),
	.q_l		(rd_en_q_l_unused),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x72_cust_msff_ctl_macro__width_1 dff_wr_en  (
	.scan_in	(dff_wr_en_scanin),
	.scan_out	(dff_wr_en_scanout),
	.l1clk		(wrclk_in),
	.din		(wr_en),
	.dout		(wr_en_d1),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x72_cust_msff_ctl_macro__fs_1__width_36 dff_din_hi   (
	.scan_in	({dff_din_hi_scan[35:1],dff_din_hi_scanin}),
	.scan_out	({dff_din_hi_scanout,dff_din_hi_scan[35:1]}),
	.l1clk		(wrclk_in),
	.din		(din[71:36]),
	.dout		(din_d1[71:36]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x72_cust_msff_ctl_macro__fs_1__width_36 dff_din_lo   (
	.scan_in	({dff_din_lo_scan[35:1],dff_din_lo_scanin}),
	.scan_out	({dff_din_lo_scanout,dff_din_lo_scan[35:1]}),
	.l1clk		(wrclk_in),
	.din		(din[35:0]),
	.dout		(din_d1[35:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x72_cust_inv_macro__width_1 wr_inh_inv  (
	.din		(tcu_array_wr_inhibit),
	.dout		(wr_inh_)
);
n2_com_dp_32x72_cust_and_macro__width_2 enable_qual  (
	.din0		({2{wr_inh_}}),
	.din1		({rd_en_d1,wr_en_d1}),
	.dout		({rd_en_d1_qual,wr_en_d1_qual})
);
n2_com_dp_32x72_cust_n2_com_array_macro__rows_32__width_72__z_array array    (
	.rclk	(rdclk_free),
	.wclk	(wrclk_free),
	.wr_adr (wr_adr_d1[4:0]),
	.wr_en	(wr_en_d1_qual),
	.rd_adr (rd_adr_d1[4:0]),
	.rd_en	(rd_en_d1_qual),
	.din	(din_d1[71:0]),
	.dout	(local_dout[71:0])
);


assign dout[71:0] = local_dout[71:0];
assign dff_dout_scanout = dff_dout_scanin;

supply0 vss;
supply1 vdd;

// fixscan start:
assign dff_wr_addr_scanin         = scan_in                  ;
assign dff_rd_addr_scanin         = dff_wr_addr_scanout      ;
assign dff_wr_en_scanin           = dff_rd_addr_scanout      ;
assign dff_rd_en_scanin           = dff_wr_en_scanout        ;
assign dff_din_lo_scanin          = dff_rd_en_scanout        ;
assign dff_din_hi_scanin          = dff_din_lo_scanout       ;
assign dff_dout_scanin            = dff_din_hi_scanout       ;
assign scan_out                   = dff_dout_scanout         ;
// fixscan end:


`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x72_cust_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_com_dp_32x72_cust_sram_msff_mo_macro__fs_1__width_5 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [4:0] d;
  input [4:0] scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [4:0] mq;
output [4:0] mq_l;
  output [4:0] scan_out;
output [4:0] q;
output [4:0] q_l;


new_dlata #(5)  d0_0 (
.d(d[4:0]),
.si(scan_in[4:0]),
.so(scan_out[4:0]),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[4:0]),
.q_l(q_l[4:0]),
.mq(mq[4:0]),
.mq_l(mq_l[4:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_com_dp_32x72_cust_sram_msff_mo_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [0:0] d;
  input scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [0:0] mq;
output [0:0] mq_l;
  output scan_out;
output [0:0] q;
output [0:0] q_l;


new_dlata #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[0:0]),
.q_l(q_l[0:0]),
.mq(mq[0:0]),
.mq_l(mq_l[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x72_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x72_cust_msff_ctl_macro__fs_1__width_36 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [35:0] fdin;

  input [35:0] din;
  input l1clk;
  input [35:0] scan_in;


  input siclk;
  input soclk;

  output [35:0] dout;
  output [35:0] scan_out;
assign fdin[35:0] = din[35:0];


dff #(36)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[35:0]),
.si(scan_in[35:0]),
.so(scan_out[35:0]),
.q(dout[35:0])
);


endmodule


//
//   invert macro
//
//


module n2_com_dp_32x72_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_com_dp_32x72_cust_and_macro__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


and2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


module n2_com_dp_32x72_cust_n2_com_array_macro__rows_32__width_72__z_array (
  rclk, 
  wclk, 
  rd_adr, 
  rd_en, 
  wr_en, 
  wr_adr, 
  din, 
  dout);

input		rclk;
input		wclk;
input	[4:0]	rd_adr;
input		rd_en;
input		wr_en;
input	[4:0]	wr_adr;
input	[72-1:0]	din;
output	[72-1:0]	dout; 


reg	[72-1:0]	mem[32-1:0];
reg	[72-1:0]	local_dout;

`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
 for (i=0; i<32; i=i+1) begin
   mem[i] = 72'b0;
 end
 local_dout = 72'b0;
end
`endif
//////////////////////
// Read/write array
//////////////////////
always @(negedge wclk) begin
   if (wr_en) begin
       mem[wr_adr] <= din;


   end
end
always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin
   if (rclk) begin
     if (rd_en) begin
         if (wr_en & (wr_adr[4:0] == rd_adr[4:0]))
             local_dout[72-1:0] <= 72'hx;
         else
             local_dout[72-1:0] <= mem[rd_adr] ;
     end
     else
             local_dout[72-1:0] <= ~(72'h0);
  end
end
assign dout[72-1:0] = local_dout[72-1:0];
supply0 vss;
supply1 vdd;


endmodule 

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_com_dp_32x84_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_com_dp_32x84_cust (
  wr_adr, 
  wr_en, 
  rd_adr, 
  rd_en, 
  din, 
  dout, 
  rdclk, 
  wrclk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  bist_clk_mux_sel, 
  rd_pce, 
  wr_pce, 
  scan_out);
wire rd_lce;
wire wr_lce;
wire rdclk_in;
wire wrclk_in;
wire rdclk_free;
wire wrclk_free;
wire dff_wr_addr_scanin;
wire dff_wr_addr_scanout;
wire [4:0] wr_adr_d1;
wire [4:1] dff_rd_addr_scan;
wire dff_rd_addr_scanin;
wire dff_rd_addr_scanout;
wire [4:0] rd_adr_d1;
wire [4:0] rd_adr_mq_l_unused;
wire [4:0] rd_adr_q_unused;
wire [4:0] rd_adr_q_l_unused;
wire dff_rd_en_scanin;
wire dff_rd_en_scanout;
wire rd_en_d1;
wire rd_en_mq_l_unused;
wire rd_en_q_unused;
wire rd_en_q_l_unused;
wire dff_wr_en_scanin;
wire dff_wr_en_scanout;
wire wr_en_d1;
wire [41:1] dff_din_hi_scan;
wire dff_din_hi_scanin;
wire dff_din_hi_scanout;
wire [83:0] din_d1;
wire [41:1] dff_din_lo_scan;
wire dff_din_lo_scanin;
wire dff_din_lo_scanout;
wire wr_inh_;
wire rd_en_d1_qual;
wire wr_en_d1_qual;
wire [83:0] local_dout;
wire dff_dout_scanout;
wire dff_dout_scanin;
		
input	[4:0]	wr_adr;
input			wr_en;
input	[4:0]	rd_adr;
input			rd_en;
input	[83:0] 	din;
output	[83:0]	dout;
input		rdclk;
input		wrclk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_array_wr_inhibit;
input		tcu_se_scancollar_in;


input		bist_clk_mux_sel;
input		rd_pce;
input		wr_pce;
output		scan_out;


`ifndef FPGA
// JDL 05/17/07
// synopsys translate_off
`endif

wire pce_ov	= tcu_pce_ov;
wire siclk	= tcu_aclk;
wire soclk	= tcu_bclk;
//================================================
// Clock headers
//================================================
cl_mc1_bistlatch_4x rd_pce_lat (
	.l2clk	(rdclk),
	.pce	(rd_pce),
	.pce_ov	(pce_ov),
	.lce	(rd_lce)
);
cl_mc1_bistlatch_4x wr_pce_lat (
	.l2clk	(wrclk),
	.pce	(wr_pce),
	.pce_ov	(pce_ov),
	.lce	(wr_lce)
);
cl_mc1_bistl1hdr_8x rch_in (
        .l2clk  (rdclk), 
        .se     (tcu_se_scancollar_in),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(rd_lce),
        .l1clk  (rdclk_in)
);
cl_mc1_bistl1hdr_8x wch_in (
        .l2clk  (wrclk), 
        .se     (tcu_se_scancollar_in),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(wr_lce),
        .l1clk  (wrclk_in)
);
cl_mc1_bistl1hdr_8x rch_free (
        .l2clk  (rdclk), 
        .se     (1'b0),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(rd_lce),
        .l1clk  (rdclk_free)
);
cl_mc1_bistl1hdr_8x wch_free (
        .l2clk  (wrclk), 
        .se     (1'b0),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(wr_lce),
        .l1clk  (wrclk_free)
);
 

///////////////////////////////////////////////////////////////
// Flop the inputs                                           //
///////////////////////////////////////////////////////////////
n2_com_dp_32x84_cust_msff_ctl_macro__width_5 dff_wr_addr  (
	.scan_in	(dff_wr_addr_scanin),
	.scan_out	(dff_wr_addr_scanout),
	.l1clk		(wrclk_in),
	.din		(wr_adr[4:0]),
	.dout		(wr_adr_d1[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x84_cust_sram_msff_mo_macro__fs_1__width_5 dff_rd_addr   (
	.scan_in	({dff_rd_addr_scan[4:1],dff_rd_addr_scanin}),
	.scan_out	({dff_rd_addr_scanout,dff_rd_addr_scan[4:1]}),
	.l1clk		(rdclk_in),
	.and_clk	(rdclk_in),
	.d		(rd_adr[4:0]),
	.mq		(rd_adr_d1[4:0]),
	.mq_l		(rd_adr_mq_l_unused[4:0]),
	.q		(rd_adr_q_unused[4:0]),
	.q_l		(rd_adr_q_l_unused[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x84_cust_sram_msff_mo_macro__width_1 dff_rd_en  (
	.scan_in	(dff_rd_en_scanin),
	.scan_out	(dff_rd_en_scanout),
	.l1clk		(rdclk_in),
	.and_clk	(rdclk_in),
	.d		(rd_en),
	.mq		(rd_en_d1),
	.mq_l		(rd_en_mq_l_unused),
	.q		(rd_en_q_unused),
	.q_l		(rd_en_q_l_unused),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x84_cust_msff_ctl_macro__width_1 dff_wr_en  (
	.scan_in	(dff_wr_en_scanin),
	.scan_out	(dff_wr_en_scanout),
	.l1clk		(wrclk_in),
	.din		(wr_en),
	.dout		(wr_en_d1),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x84_cust_msff_ctl_macro__fs_1__width_42 dff_din_hi   (
	.scan_in	({dff_din_hi_scan[41:1],dff_din_hi_scanin}),
	.scan_out	({dff_din_hi_scanout,dff_din_hi_scan[41:1]}),
	.l1clk		(wrclk_in),
	.din		(din[83:42]),
	.dout		(din_d1[83:42]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x84_cust_msff_ctl_macro__fs_1__width_42 dff_din_lo   (
	.scan_in	({dff_din_lo_scan[41:1],dff_din_lo_scanin}),
	.scan_out	({dff_din_lo_scanout,dff_din_lo_scan[41:1]}),
	.l1clk		(wrclk_in),
	.din		(din[41:0]),
	.dout		(din_d1[41:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_32x84_cust_inv_macro__width_1 wr_inh_inv  (
	.din		(tcu_array_wr_inhibit),
	.dout		(wr_inh_)
);
n2_com_dp_32x84_cust_and_macro__width_2 enable_qual  (
	.din0		({2{wr_inh_}}),
	.din1		({rd_en_d1,wr_en_d1}),
	.dout		({rd_en_d1_qual,wr_en_d1_qual})
);
n2_com_dp_32x84_cust_n2_com_array_macro__rows_32__width_84__z_array array    (
	.rclk	(rdclk_free),
	.wclk	(wrclk_free),
	.wr_adr (wr_adr_d1[4:0]),
	.wr_en	(wr_en_d1_qual),
	.rd_adr (rd_adr_d1[4:0]),
	.rd_en	(rd_en_d1_qual),
	.din	(din_d1[83:0]),
	.dout	(local_dout[83:0])
);


assign dout[83:0] = local_dout[83:0];
assign dff_dout_scanout = dff_dout_scanin;

supply0 vss;
supply1 vdd;

// fixscan start:
assign dff_wr_addr_scanin         = scan_in                  ;
assign dff_rd_addr_scanin         = dff_wr_addr_scanout      ;
assign dff_wr_en_scanin           = dff_rd_addr_scanout      ;
assign dff_rd_en_scanin           = dff_wr_en_scanout        ;
assign dff_din_lo_scanin          = dff_rd_en_scanout        ;
assign dff_din_hi_scanin          = dff_din_lo_scanout       ;
assign dff_dout_scanin            = dff_din_hi_scanout       ;
assign scan_out                   = dff_dout_scanout         ;
// fixscan end:


`ifndef FPGA
// JDL 05/17/07
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x84_cust_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_com_dp_32x84_cust_sram_msff_mo_macro__fs_1__width_5 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [4:0] d;
  input [4:0] scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [4:0] mq;
output [4:0] mq_l;
  output [4:0] scan_out;
output [4:0] q;
output [4:0] q_l;


new_dlata #(5)  d0_0 (
.d(d[4:0]),
.si(scan_in[4:0]),
.so(scan_out[4:0]),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[4:0]),
.q_l(q_l[4:0]),
.mq(mq[4:0]),
.mq_l(mq_l[4:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_com_dp_32x84_cust_sram_msff_mo_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [0:0] d;
  input scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [0:0] mq;
output [0:0] mq_l;
  output scan_out;
output [0:0] q;
output [0:0] q_l;


new_dlata #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[0:0]),
.q_l(q_l[0:0]),
.mq(mq[0:0]),
.mq_l(mq_l[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x84_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_32x84_cust_msff_ctl_macro__fs_1__width_42 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [41:0] fdin;

  input [41:0] din;
  input l1clk;
  input [41:0] scan_in;


  input siclk;
  input soclk;

  output [41:0] dout;
  output [41:0] scan_out;
assign fdin[41:0] = din[41:0];


dff #(42)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[41:0]),
.si(scan_in[41:0]),
.so(scan_out[41:0]),
.q(dout[41:0])
);


endmodule


//
//   invert macro
//
//


module n2_com_dp_32x84_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_com_dp_32x84_cust_and_macro__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


and2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


module n2_com_dp_32x84_cust_n2_com_array_macro__rows_32__width_84__z_array (
  rclk, 
  wclk, 
  rd_adr, 
  rd_en, 
  wr_en, 
  wr_adr, 
  din, 
  dout);

input		rclk;
input		wclk;
input	[4:0]	rd_adr;
input		rd_en;
input		wr_en;
input	[4:0]	wr_adr;
input	[84-1:0]	din;
output	[84-1:0]	dout; 


reg	[84-1:0]	mem[32-1:0];
reg	[84-1:0]	local_dout;

`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
 for (i=0; i<32; i=i+1) begin
   mem[i] = 84'b0;
 end
 local_dout = 84'b0;
end
`endif
//////////////////////
// Read/write array
//////////////////////
always @(negedge wclk) begin
   if (wr_en) begin
       mem[wr_adr] <= din;


   end
end
always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin
   if (rclk) begin
     if (rd_en) begin
         if (wr_en & (wr_adr[4:0] == rd_adr[4:0]))
             local_dout[84-1:0] <= 84'hx;
         else
             local_dout[84-1:0] <= mem[rd_adr] ;
     end
     else
             local_dout[84-1:0] <= ~(84'h0);
  end
end
assign dout[84-1:0] = local_dout[84-1:0];
supply0 vss;
supply1 vdd;


endmodule 

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_com_dp_64x84_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_com_dp_64x84_cust (
  wr_adr, 
  wr_en, 
  rd_adr, 
  rd_en, 
  din, 
  dout, 
  rdclk, 
  wrclk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  bist_clk_mux_sel, 
  rd_pce, 
  wr_pce, 
  scan_out);
wire rd_lce;
wire wr_lce;
wire rdclk_in;
wire wrclk_in;
wire rdclk_free;
wire wrclk_free;
wire dff_wr_addr_scanin;
wire dff_wr_addr_scanout;
wire [5:0] wr_adr_d1;
wire [5:1] dff_rd_addr_scan;
wire dff_rd_addr_scanin;
wire dff_rd_addr_scanout;
wire [5:0] rd_adr_d1;
wire [5:0] rd_adr_mq_l_unused;
wire [5:0] rd_adr_q_unused;
wire [5:0] rd_adr_q_l_unused;
wire dff_rd_en_scanin;
wire dff_rd_en_scanout;
wire rd_en_d1;
wire rd_en_mq_l_unused;
wire rd_en_q_unused;
wire rd_en_q_l_unused;
wire dff_wr_en_scanin;
wire dff_wr_en_scanout;
wire wr_en_d1;
wire [41:1] dff_din_hi_scan;
wire dff_din_hi_scanin;
wire dff_din_hi_scanout;
wire [83:0] din_d1;
wire [41:1] dff_din_lo_scan;
wire dff_din_lo_scanin;
wire dff_din_lo_scanout;
wire wr_inh_;
wire rd_en_d1_qual;
wire wr_en_d1_qual;
wire [83:0] local_dout;
wire dff_dout_scanout;
wire dff_dout_scanin;
		
input	[5:0]	wr_adr;
input			wr_en;
input	[5:0]	rd_adr;
input			rd_en;
input	[83:0] 	din;
output	[83:0]	dout;
input		rdclk;
input		wrclk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_array_wr_inhibit;
input		tcu_se_scancollar_in;


input		bist_clk_mux_sel;
input		rd_pce;
input		wr_pce;
output		scan_out;

`ifndef FPGA
// synopsys translate_off
`endif

wire pce_ov	= tcu_pce_ov;
wire siclk	= tcu_aclk;
wire soclk	= tcu_bclk;
//================================================
// Clock headers
//================================================
cl_mc1_bistlatch_4x rd_pce_lat (
	.l2clk	(rdclk),
	.pce	(rd_pce),
	.pce_ov	(pce_ov),
	.lce	(rd_lce)
);
cl_mc1_bistlatch_4x wr_pce_lat (
	.l2clk	(wrclk),
	.pce	(wr_pce),
	.pce_ov	(pce_ov),
	.lce	(wr_lce)
);
cl_mc1_bistl1hdr_8x rch_in (
        .l2clk  (rdclk), 
        .se     (tcu_se_scancollar_in),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(rd_lce),
        .l1clk  (rdclk_in)
);
cl_mc1_bistl1hdr_8x wch_in (
        .l2clk  (wrclk), 
        .se     (tcu_se_scancollar_in),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(wr_lce),
        .l1clk  (wrclk_in)
);
cl_mc1_bistl1hdr_8x rch_free (
        .l2clk  (rdclk), 
        .se     (1'b0),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(rd_lce),
        .l1clk  (rdclk_free)
);
cl_mc1_bistl1hdr_8x wch_free (
        .l2clk  (wrclk), 
        .se     (1'b0),
	.clksel	(bist_clk_mux_sel),
	.bistclk(rdclk),
	.lce	(wr_lce),
        .l1clk  (wrclk_free)
);
 

///////////////////////////////////////////////////////////////
// Flop the inputs                                           //
///////////////////////////////////////////////////////////////
n2_com_dp_64x84_cust_msff_ctl_macro__width_6 dff_wr_addr  (
	.scan_in	(dff_wr_addr_scanin),
	.scan_out	(dff_wr_addr_scanout),
	.l1clk		(wrclk_in),
	.din		(wr_adr[5:0]),
	.dout		(wr_adr_d1[5:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_64x84_cust_sram_msff_mo_macro__fs_1__width_6 dff_rd_addr   (
	.scan_in	({dff_rd_addr_scan[5:1],dff_rd_addr_scanin}),
	.scan_out	({dff_rd_addr_scanout,dff_rd_addr_scan[5:1]}),
	.l1clk		(rdclk_in),
	.and_clk	(rdclk_in),
	.d		(rd_adr[5:0]),
	.mq		(rd_adr_d1[5:0]),
	.mq_l		(rd_adr_mq_l_unused[5:0]),
	.q		(rd_adr_q_unused[5:0]),
	.q_l		(rd_adr_q_l_unused[5:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_64x84_cust_sram_msff_mo_macro__width_1 dff_rd_en  (
	.scan_in	(dff_rd_en_scanin),
	.scan_out	(dff_rd_en_scanout),
	.l1clk		(rdclk_in),
	.and_clk	(rdclk_in),
	.d		(rd_en),
	.mq		(rd_en_d1),
	.mq_l		(rd_en_mq_l_unused),
	.q		(rd_en_q_unused),
	.q_l		(rd_en_q_l_unused),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_64x84_cust_msff_ctl_macro__width_1 dff_wr_en  (
	.scan_in	(dff_wr_en_scanin),
	.scan_out	(dff_wr_en_scanout),
	.l1clk		(wrclk_in),
	.din		(wr_en),
	.dout		(wr_en_d1),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_64x84_cust_msff_ctl_macro__fs_1__width_42 dff_din_hi   (
	.scan_in	({dff_din_hi_scan[41:1],dff_din_hi_scanin}),
	.scan_out	({dff_din_hi_scanout,dff_din_hi_scan[41:1]}),
	.l1clk		(wrclk_in),
	.din		(din[83:42]),
	.dout		(din_d1[83:42]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_64x84_cust_msff_ctl_macro__fs_1__width_42 dff_din_lo   (
	.scan_in	({dff_din_lo_scan[41:1],dff_din_lo_scanin}),
	.scan_out	({dff_din_lo_scanout,dff_din_lo_scan[41:1]}),
	.l1clk		(wrclk_in),
	.din		(din[41:0]),
	.dout		(din_d1[41:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_com_dp_64x84_cust_inv_macro__width_1 wr_inh_inv  (
	.din		(tcu_array_wr_inhibit),
	.dout		(wr_inh_)
);
n2_com_dp_64x84_cust_and_macro__width_2 enable_qual  (
	.din0		({2{wr_inh_}}),
	.din1		({rd_en_d1,wr_en_d1}),
	.dout		({rd_en_d1_qual,wr_en_d1_qual})
);
n2_com_dp_64x84_cust_n2_com_array_macro__rows_64__width_84__z_array array    (
	.rclk	(rdclk_free),
	.wclk	(wrclk_free),
	.wr_adr (wr_adr_d1[5:0]),
	.wr_en	(wr_en_d1_qual),
	.rd_adr (rd_adr_d1[5:0]),
	.rd_en	(rd_en_d1_qual),
	.din	(din_d1[83:0]),
	.dout	(local_dout[83:0])
);


assign dout[83:0] = local_dout[83:0];
assign dff_dout_scanout = dff_dout_scanin;

supply0 vss;
supply1 vdd;

// fixscan start:
assign dff_wr_addr_scanin         = scan_in                  ;
assign dff_rd_addr_scanin         = dff_wr_addr_scanout      ;
assign dff_wr_en_scanin           = dff_rd_addr_scanout      ;
assign dff_rd_en_scanin           = dff_wr_en_scanout        ;
assign dff_din_lo_scanin          = dff_rd_en_scanout        ;
assign dff_din_hi_scanin          = dff_din_lo_scanout       ;
assign dff_dout_scanin            = dff_din_hi_scanout       ;
assign scan_out                   = dff_dout_scanout         ;
// fixscan end:


`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_64x84_cust_msff_ctl_macro__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;
wire [4:0] so;

  input [5:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si({scan_in,so[4:0]}),
.so({so[4:0],scan_out}),
.q(dout[5:0])
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_com_dp_64x84_cust_sram_msff_mo_macro__fs_1__width_6 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [5:0] d;
  input [5:0] scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [5:0] mq;
output [5:0] mq_l;
  output [5:0] scan_out;
output [5:0] q;
output [5:0] q_l;


new_dlata #(6)  d0_0 (
.d(d[5:0]),
.si(scan_in[5:0]),
.so(scan_out[5:0]),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[5:0]),
.q_l(q_l[5:0]),
.mq(mq[5:0]),
.mq_l(mq_l[5:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_com_dp_64x84_cust_sram_msff_mo_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [0:0] d;
  input scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [0:0] mq;
output [0:0] mq_l;
  output scan_out;
output [0:0] q;
output [0:0] q_l;


new_dlata #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[0:0]),
.q_l(q_l[0:0]),
.mq(mq[0:0]),
.mq_l(mq_l[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_64x84_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_com_dp_64x84_cust_msff_ctl_macro__fs_1__width_42 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [41:0] fdin;

  input [41:0] din;
  input l1clk;
  input [41:0] scan_in;


  input siclk;
  input soclk;

  output [41:0] dout;
  output [41:0] scan_out;
assign fdin[41:0] = din[41:0];


dff #(42)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[41:0]),
.si(scan_in[41:0]),
.so(scan_out[41:0]),
.q(dout[41:0])
);


endmodule


//
//   invert macro
//
//


module n2_com_dp_64x84_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_com_dp_64x84_cust_and_macro__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


and2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


module n2_com_dp_64x84_cust_n2_com_array_macro__rows_64__width_84__z_array (
  rclk, 
  wclk, 
  rd_adr, 
  rd_en, 
  wr_en, 
  wr_adr, 
  din, 
  dout);

input		rclk;
input		wclk;
input	[5:0]	rd_adr;
input		rd_en;
input		wr_en;
input	[5:0]	wr_adr;
input	[84-1:0]	din;
output	[84-1:0]	dout; 


reg	[84-1:0]	mem[64-1:0];
reg	[84-1:0]	local_dout;

`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
 for (i=0; i<64; i=i+1) begin
   mem[i] = 84'b0;
 end
 local_dout = 84'b0;
end
`endif
//////////////////////
// Read/write array
//////////////////////
always @(negedge wclk) begin
   if (wr_en) begin
       mem[wr_adr] <= din;


   end
end
always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin
   if (rclk) begin
     if (rd_en) begin
         if (wr_en & (wr_adr[5:0] == rd_adr[5:0]))
             local_dout[84-1:0] <= 84'hx;
         else
             local_dout[84-1:0] <= mem[rd_adr] ;
     end
     else
             local_dout[84-1:0] <= ~(84'h0);
  end
end
assign dout[84-1:0] = local_dout[84-1:0];
supply0 vss;
supply1 vdd;


endmodule 

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_dva_dp_32x32_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_dva_dp_32x32_cust (
  l2clk, 
  tcu_pce_ov, 
  tcu_se_scancollar_in, 
  tcu_scan_en, 
  tcu_array_wr_inhibit, 
  tcu_aclk, 
  tcu_bclk, 
  pce, 
  scan_in, 
  rd_addr, 
  wr_addr, 
  din, 
  bit_wen, 
  rd_en, 
  wr_en, 
  dout, 
  scan_out);
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire l1clk_in;
wire l1clk_free;
wire dff_bit_en_scanin;
wire dff_bit_en_scanout;
wire [31:0] bit_wen_d1;
wire dff_wr_en_scanin;
wire dff_wr_en_scanout;
wire wr_en_d1;
wire dff_rd_addr_scanin;
wire dff_rd_addr_scanout;
wire [4:0] rd_addr_d1;
wire [4:0] mq_l_rd_addr_unused;
wire [4:0] q_rd_addr_unused;
wire [4:0] q_l_rd_addr_unused;
wire dff_rd_en_scanin;
wire dff_rd_en_scanout;
wire rd_en_d1;
wire mq_l_rd_en_unused;
wire q_rd_en_unused;
wire q_l_rd_en_unused;
wire dff_wr_addr_scanin;
wire dff_wr_addr_scanout;
wire [4:0] wr_addr_d1;
wire dff_din_scanin;
wire dff_din_scanout;
wire [31:0] din_d1;
wire wr_inhibit_;
wire wr_en_qual;
wire rd_en_qual;


input		l2clk;
input		tcu_pce_ov;
input		tcu_se_scancollar_in;
input		tcu_scan_en;
input		tcu_array_wr_inhibit;
input		tcu_aclk;
input		tcu_bclk;
input		pce;


input		scan_in;
input	[4:0]	rd_addr;
input	[4:0]	wr_addr;
input	[31:0]	din;
input	[31:0]	bit_wen;
input		rd_en;
input		wr_en;
   
output	[31:0]	dout;
output		scan_out;

`ifndef FPGA
// synopsys translate_off
`endif

assign pce_ov = tcu_pce_ov;
assign stop   = 1'b0;
assign siclk  = tcu_aclk ;
assign soclk  = tcu_bclk;

//================================================
// Clock headers
//================================================
n2_dva_dp_32x32_cust_l1clkhdr_ctl_macro l1ch_in (
	.l2clk	(l2clk), 
	.l1en 	(pce), 
	.se	(tcu_se_scancollar_in),
	.l1clk	(l1clk_in),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_dva_dp_32x32_cust_l1clkhdr_ctl_macro l1ch_free (
	.l2clk	(l2clk), 
	.l1en 	(pce), 
	.se	(tcu_scan_en),
	.l1clk	(l1clk_free),
  .pce_ov(pce_ov),
  .stop(stop)
);

///////////////////////////////////////////////////////////////
// Flop the inputs                                           //
///////////////////////////////////////////////////////////////
n2_dva_dp_32x32_cust_msff_ctl_macro__scanreverse_1__width_32 dff_bit_en   (
	.scan_in(dff_bit_en_scanin),
	.scan_out(dff_bit_en_scanout),
	.l1clk(l1clk_in),
	.din(bit_wen[31:0]),
	.dout(bit_wen_d1[31:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dva_dp_32x32_cust_msff_ctl_macro__width_1 dff_wr_en  (
	.scan_in(dff_wr_en_scanin),
	.scan_out(dff_wr_en_scanout),
	.l1clk(l1clk_in),
	.din(wr_en),
	.dout(wr_en_d1),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dva_dp_32x32_cust_sram_msff_mo_macro__scanreverse_1__width_5 dff_rd_addr   (
	.scan_in(dff_rd_addr_scanin),
	.scan_out(dff_rd_addr_scanout),
	.l1clk(l1clk_in),
	.and_clk(l1clk_free),
	.d(rd_addr[4:0]),
	.mq(rd_addr_d1[4:0]),
	.mq_l(mq_l_rd_addr_unused[4:0]),
	.q(q_rd_addr_unused[4:0]),
	.q_l(q_l_rd_addr_unused[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dva_dp_32x32_cust_sram_msff_mo_macro__width_1 dff_rd_en  (
	.scan_in(dff_rd_en_scanin),
	.scan_out(dff_rd_en_scanout),
	.l1clk(l1clk_in),
	.and_clk(l1clk_free),
	.d(rd_en),
	.mq(rd_en_d1),
	.mq_l(mq_l_rd_en_unused),
	.q(q_rd_en_unused),
	.q_l(q_l_rd_en_unused),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dva_dp_32x32_cust_msff_ctl_macro__width_5 dff_wr_addr  (
	.scan_in(dff_wr_addr_scanin),
	.scan_out(dff_wr_addr_scanout),
	.l1clk(l1clk_in),
	.din(wr_addr[4:0]),
	.dout(wr_addr_d1[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dva_dp_32x32_cust_msff_ctl_macro__width_32 dff_din  (
	.scan_in(dff_din_scanin),
	.scan_out(dff_din_scanout),
	.l1clk(l1clk_in),
	.din(din[31:0]),
	.dout(din_d1[31:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dva_dp_32x32_cust_inv_macro__width_1 wr_inh_inv  (
	.din	(tcu_array_wr_inhibit),
	.dout	(wr_inhibit_)
);
n2_dva_dp_32x32_cust_and_macro__width_2 wr_and  (
	.din0	({wr_en_d1   ,rd_en_d1}),
	.din1	({wr_inhibit_,wr_inhibit_}),
	.dout	({wr_en_qual ,rd_en_qual})
);

n2_dva_dp_32x32_array array (
	.clk		(l1clk_free),
	.rd_addr	(rd_addr_d1[4:0]),
	.wr_addr	(wr_addr_d1[4:0]),
	.din		(din_d1[31:0]),
	.bit_wen	(bit_wen_d1[31:0]),
	.rd_en		(rd_en_qual),
	.wr_en		(wr_en_qual),
	.dout		(dout[31:0])
);

supply0 vss;
supply1 vdd;

// fixscan start:
assign dff_bit_en_scanin         = scan_in                  ;
assign dff_wr_en_scanin          = dff_bit_en_scanout       ;
assign dff_rd_addr_scanin        = dff_wr_en_scanout        ;
assign dff_rd_en_scanin          = dff_rd_addr_scanout      ;
assign dff_wr_addr_scanin        = dff_rd_en_scanout        ;
assign dff_din_scanin            = dff_wr_addr_scanout      ;
assign scan_out                  = dff_din_scanout          ;
// fixscan end:

`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_dva_dp_32x32_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module n2_dva_dp_32x32_cust_msff_ctl_macro__scanreverse_1__width_32 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [0:30] so;

  input [31:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = din[31:0];


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({so[0:30],scan_in}),
.so({scan_out,so[0:30]}),
.q(dout[31:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_dva_dp_32x32_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_dva_dp_32x32_cust_sram_msff_mo_macro__scanreverse_1__width_5 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
wire [0:3] so;

input [4:0] d;
  input scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [4:0] mq;
output [4:0] mq_l;
  output scan_out;
output [4:0] q;
output [4:0] q_l;


new_dlata #(5)  d0_0 (
.d(d[4:0]),
.si({so[0:3],scan_in}),
.so({scan_out,so[0:3]}),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[4:0]),
.q_l(q_l[4:0]),
.mq(mq[4:0]),
.mq_l(mq_l[4:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_dva_dp_32x32_cust_sram_msff_mo_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [0:0] d;
  input scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [0:0] mq;
output [0:0] mq_l;
  output scan_out;
output [0:0] q;
output [0:0] q_l;


new_dlata #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[0:0]),
.q_l(q_l[0:0]),
.mq(mq[0:0]),
.mq_l(mq_l[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_dva_dp_32x32_cust_msff_ctl_macro__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [3:0] so;

  input [4:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si({scan_in,so[3:0]}),
.so({so[3:0],scan_out}),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_dva_dp_32x32_cust_msff_ctl_macro__width_32 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [31:0] fdin;
wire [30:0] so;

  input [31:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [31:0] dout;
  output scan_out;
assign fdin[31:0] = din[31:0];


dff #(32)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[31:0]),
.si({scan_in,so[30:0]}),
.so({so[30:0],scan_out}),
.q(dout[31:0])
);


endmodule


//
//   invert macro
//
//


module n2_dva_dp_32x32_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_dva_dp_32x32_cust_and_macro__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


and2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


module n2_dva_dp_32x32_array (
  clk, 
  rd_addr, 
  wr_addr, 
  din, 
  bit_wen, 
  rd_en, 
  wr_en, 
  dout);
wire [31:0] temp;
wire [31:0] vbit_sa;
wire [31:0] wt_data;
wire [31:0] vbit;


input		clk;
input	[4:0]	rd_addr;
input	[4:0]	wr_addr;
input	[31:0]	din;
input	[31:0]	bit_wen;
input		rd_en;
input		wr_en;
   
output	[31:0]	dout;

reg	[31:0] mem [31:0];
reg	[31:0] 	dout ;

`ifndef NOINITMEM
// Initialize the arrays.
integer i;
initial begin
  for (i=0;i<32;i=i+1) begin
      mem[i] = 32'b0 ;
  end
end 
`endif

/////////////
// Write on negedge
/////////////

assign temp[31:0] = mem[wr_addr[4:0]];

always @(negedge clk) begin
  if (wr_en) begin
    mem[wr_addr[4:0]] <= (bit_wen[31:0] & din[31:0]) | (~bit_wen[31:0] & temp[31:0]);


  end
end

/////////////
// Read 
/////////////

assign vbit_sa[31:0] = mem[rd_addr[4:0]] & {32{rd_en}};

// Handle write-through case.
// Read result is the AND of the previous and new values.
// wt_data represents the precharged write bit line
// It is high when writing a '1' or when not writing.

assign wt_data[31:0]  = {32{rd_addr[4:0] != wr_addr[4:0]}} | ~bit_wen[31:0] | din[31:0] | {32{~wr_en}};

assign vbit[31:0] = vbit_sa[31:0] & wt_data[31:0];

always @(clk or vbit) begin
  if (clk)
    dout[31:0] <= vbit[31:0];
end


supply0 vss;
supply1 vdd;

endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_frf_mp_256x78_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_frf_mp_256x78_cust (
  frf_r1_data, 
  frf_r1_ecc, 
  frf_r2_data, 
  frf_r2_ecc, 
  l2clk, 
  scan_in, 
  pce, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_array_wr_inhibit, 
  tcu_scan_en, 
  tcu_se_scancollar_in, 
  main_clken, 
  scan_out, 
  r_tid, 
  r1_valid, 
  r1_addr, 
  r2_valid, 
  r2_addr, 
  w1_tid, 
  w1_valid, 
  w1_addr, 
  w2_tid, 
  w2_valid, 
  w2_addr, 
  w1_data, 
  w1_ecc, 
  w2_data, 
  w2_ecc);
wire siclk;
wire soclk;
wire l1clk;
wire l1clk_main;
wire [13:0] w1_ecc_synd_fb_to_fw_scanin;
wire [13:0] w1_ecc_synd_fb_to_fw_scanout;
wire [13:0] w1_ecc_fw;
wire [13:0] w2_ecc_synd_fb_to_fw_scanin;
wire [13:0] w2_ecc_synd_fb_to_fw_scanout;
wire [13:0] w2_ecc_fw;
wire [14:0] frf_read_ctl_in2ph2_scanin;
wire [14:0] frf_read_ctl_in2ph2_scanout;
wire [4:0] r1_addr_ph2;
wire [4:0] r2_addr_ph2;
wire r1_valid_ph2;
wire r2_valid_ph2;
wire [2:0] r_tid_ph2;
wire [63:0] fw_w2data_scanin;
wire [63:0] fw_w2data_scanout;
wire [63:0] w2_data_fw;
wire [63:0] fw_w1data_scanin;
wire [63:0] fw_w1data_scanout;
wire [63:0] w1_data_fw;
wire [19:0] frf_write_input_ctl_in2fb_scanin;
wire [19:0] frf_write_input_ctl_in2fb_scanout;
wire [2:0] w1_tid_fw;
wire [1:0] w1_valid_fw;
wire [4:0] w1_addr_fw;
wire [2:0] w2_tid_fw;
wire [1:0] w2_valid_fw;
wire [4:0] w2_addr_fw;
wire l1clk_free;


   // -----------------------------------------------------------------------
   // Read output ports
   // -----------------------------------------------------------------------
   output  [63:0] frf_r1_data;
   output  [13:0] frf_r1_ecc;
   output  [63:0] frf_r2_data;
   output  [13:0] frf_r2_ecc;

   // -----------------------------------------------------------------------
   // global signals
   // -----------------------------------------------------------------------

   input        l2clk;
   input        scan_in;
   input	pce;
   input        tcu_pce_ov;
   input        tcu_aclk;
   input        tcu_bclk;
   input        tcu_array_wr_inhibit;
   input	tcu_scan_en;
   input        tcu_se_scancollar_in;

   input        main_clken;

   output       scan_out;


   // -----------------------------------------------------------------------
   // Reading controls
   // -----------------------------------------------------------------------
   input    [2:0] r_tid;
   input          r1_valid;
   input    [4:0] r1_addr;
   input          r2_valid;
   input    [4:0] r2_addr;
 
   // -----------------------------------------------------------------------
   // Writing controls 
   // -----------------------------------------------------------------------
   input    [2:0] w1_tid;
   input    [1:0] w1_valid;
   input    [4:0] w1_addr;
   input    [2:0] w2_tid;
   input    [1:0] w2_valid;
   input    [4:0] w2_addr;

   // -----------------------------------------------------------------------
   // Write data ports
   // -----------------------------------------------------------------------
   input   [63:0] w1_data;
   input   [13:0] w1_ecc;
   input   [63:0] w2_data;
   input   [13:0] w2_ecc;

`ifndef FPGA
   // synopsys translate_off
`endif

   assign siclk		= tcu_aclk;
   assign soclk		= tcu_bclk;

   n2_frf_mp_256x78_cust_l1clkhdr_ctl_macro	clkgen (
    .l2clk  (l2clk          		),
    .l1en   (pce			),
    .pce_ov (tcu_pce_ov			),
    .stop   (1'b0			),
    .se	    (tcu_se_scancollar_in	),
    .l1clk  (l1clk			));


   n2_frf_mp_256x78_cust_l1clkhdr_ctl_macro	clkgen_main (
    .l2clk  (l2clk          		),
    .l1en   (main_clken			),
    .pce_ov (tcu_pce_ov			),
    .stop   (1'b0			),
    .se	    (tcu_se_scancollar_in	),
    .l1clk  (l1clk_main			));


   n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_14	w1_ecc_synd_fb_to_fw		 (
     .scan_in(w1_ecc_synd_fb_to_fw_scanin[13:0]),
     .scan_out(w1_ecc_synd_fb_to_fw_scanout[13:0]),
    .l1clk (l1clk_main),
    .din   (w1_ecc   [13:0]),
    .dout  (w1_ecc_fw[13:0]),
  .siclk(siclk),
  .soclk(soclk));
   
   n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__scanreverse_1__width_14	w2_ecc_synd_fb_to_fw		 (
     .scan_in(w2_ecc_synd_fb_to_fw_scanin[13:0]),
     .scan_out(w2_ecc_synd_fb_to_fw_scanout[13:0]),
    .l1clk (l1clk_main),
    .din   (w2_ecc   [13:0]),
    .dout  (w2_ecc_fw[13:0]),
  .siclk(siclk),
  .soclk(soclk));

   n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_15	frf_read_ctl_in2ph2		 (
     .scan_in(frf_read_ctl_in2ph2_scanin[14:0]),
     .scan_out(frf_read_ctl_in2ph2_scanout[14:0]),
    .l1clk (l1clk),
    .din   ({r1_addr [4:0],    // requires free running clk or dec_fgu_decode_d en
  	     r2_addr [4:0],    // requires free running clk or dec_fgu_decode_d en
  	     r1_valid     ,    // requires free running clk or dec_fgu_decode_d en
  	     r2_valid     ,    // requires free running clk or dec_fgu_decode_d en
  	     r_tid   [2:0]}),  // requires free running clk or dec_fgu_decode_d en
    .dout  ({r1_addr_ph2[4:0],
  	     r2_addr_ph2[4:0],   
  	     r1_valid_ph2    ,
  	     r2_valid_ph2    ,
  	     r_tid_ph2  [2:0]}),
  .siclk(siclk),
  .soclk(soclk));


   n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__scanreverse_1__width_64	fw_w2data			 (
     .scan_in(fw_w2data_scanin[63:0]),
     .scan_out(fw_w2data_scanout[63:0]),
     .l1clk (l1clk_main),
     .din   (w2_data   [63:0]),
     .dout  (w2_data_fw[63:0]),
  .siclk(siclk),
  .soclk(soclk));
   
   n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_64	fw_w1data			 (
     .scan_in(fw_w1data_scanin[63:0]),
     .scan_out(fw_w1data_scanout[63:0]),
     .l1clk (l1clk_main),
     .din   (w1_data   [63:0]),
     .dout  (w1_data_fw[63:0]),
  .siclk(siclk),
  .soclk(soclk));


   n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_20	frf_write_input_ctl_in2fb	 (
     .scan_in(frf_write_input_ctl_in2fb_scanin[19:0]),
     .scan_out(frf_write_input_ctl_in2fb_scanout[19:0]),
     .l1clk (l1clk_main),
     .din   ({w1_tid      [2:0],
              w1_valid    [1:0],
              w1_addr     [4:0],
              w2_tid      [2:0],
              w2_valid    [1:0],
              w2_addr     [4:0]}),
     .dout  ({w1_tid_fw   [2:0],
              w1_valid_fw [1:0],
              w1_addr_fw  [4:0],
              w2_tid_fw   [2:0],
              w2_valid_fw [1:0],
              w2_addr_fw  [4:0]}),
  .siclk(siclk),
  .soclk(soclk));


// L2 clock "free-running" clock
n2_frf_mp_256x78_cust_l1clkhdr_ctl_macro	clkgen_free (
  .l2clk  (l2clk			),
  .l1en   (pce				),
  .pce_ov (tcu_pce_ov			),
  .stop	  (1'b0				),
  .se	  (tcu_scan_en			),
  .l1clk  (l1clk_free			));

fgu_frf_array	frf_array_o			(
  .clk      ( l1clk_free				),
  .r1_valid ( r1_valid_ph2				),
  .r1_addr  ({r_tid_ph2[2:0]  , r1_addr_ph2[4:0]}	),
  .r2_valid ( r2_valid_ph2				),
  .r2_addr  ({r_tid_ph2[2:0]  , r2_addr_ph2[4:0]}	),
  .w1_valid ( w1_valid_fw[0]				),
  .w1_addr  ({w1_tid_fw[2:0]  , w1_addr_fw[4:0]}	),
  .w1_data  ({w1_ecc_fw[6:0]  , w1_data_fw[31:0]}	),
  .w2_valid ( w2_valid_fw[0]				),
  .w2_addr  ({w2_tid_fw[2:0]  , w2_addr_fw[4:0]}	),
  .w2_data  ({w2_ecc_fw[6:0]  , w2_data_fw[31:0]}	),
     .r1_data   ({frf_r1_ecc[6:0]   , frf_r1_data[31:0]}	),
     .r2_data   ({frf_r2_ecc[6:0]   , frf_r2_data[31:0]}	),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit));


fgu_frf_array	frf_array_e			(
  .clk      ( l1clk_free				),
  .r1_valid ( r1_valid_ph2				),
  .r1_addr  ({r_tid_ph2[2:0]  , r1_addr_ph2[4:0]}	),
  .r2_valid ( r2_valid_ph2				),
  .r2_addr  ({r_tid_ph2[2:0]  , r2_addr_ph2[4:0]}	),
  .w1_valid ( w1_valid_fw[1]				),
  .w1_addr  ({w1_tid_fw[2:0]  , w1_addr_fw[4:0]}	),
  .w1_data  ({w1_ecc_fw[13:7] , w1_data_fw[63:32]}	),
  .w2_valid ( w2_valid_fw[1]				),
  .w2_addr  ({w2_tid_fw[2:0]  , w2_addr_fw[4:0]}	),
  .w2_data  ({w2_ecc_fw[13:7] , w2_data_fw[63:32]}	),
     .r1_data   ({frf_r1_ecc[13:7]  , frf_r1_data[63:32]}	),
     .r2_data   ({frf_r2_ecc[13:7]  , frf_r2_data[63:32]}	),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit));


supply0 vss;
supply1 vdd;


// scanorder start
//      w1_ecc_synd_fb_to_fw_scanin[13:7]
//      fw_w1data_scanin[63:32]
//      frf_write_input_ctl_in2fb_scanin[16]
//      frf_read_ctl_in2ph2_scanin[14:10]
//      frf_write_input_ctl_in2fb_scanin[9:7]
//      frf_write_input_ctl_in2fb_scanin[0]
//      frf_read_ctl_in2ph2_scanin[2:0]
//      frf_read_ctl_in2ph2_scanin[9:5]
//      frf_write_input_ctl_in2fb_scanin[4]
//      frf_write_input_ctl_in2fb_scanin[5]
//      w1_ecc_synd_fb_to_fw_scanin[6:0]
//      fw_w1data_scanin[31:0]
//      fw_w2data_scanin[0:31]
//      w2_ecc_synd_fb_to_fw_scanin[0:6]
//      frf_write_input_ctl_in2fb_scanin[15]
//      frf_write_input_ctl_in2fb_scanin[1]
//      frf_write_input_ctl_in2fb_scanin[2]
//      frf_write_input_ctl_in2fb_scanin[3]
//      frf_read_ctl_in2ph2_scanin[3]
//      frf_read_ctl_in2ph2_scanin[4]
//      frf_write_input_ctl_in2fb_scanin[10]
//      frf_write_input_ctl_in2fb_scanin[11]
//      frf_write_input_ctl_in2fb_scanin[12]
//      frf_write_input_ctl_in2fb_scanin[13]
//      frf_write_input_ctl_in2fb_scanin[14]
//      frf_write_input_ctl_in2fb_scanin[17]
//      frf_write_input_ctl_in2fb_scanin[18]
//      frf_write_input_ctl_in2fb_scanin[19]
//      frf_write_input_ctl_in2fb_scanin[6]
//      fw_w2data_scanin[32:63]
//      w2_ecc_synd_fb_to_fw_scanin[7:13]
// scanorder end
// fixscan start
assign w1_ecc_synd_fb_to_fw_scanin[13]=scan_in;
assign w1_ecc_synd_fb_to_fw_scanin[12]=w1_ecc_synd_fb_to_fw_scanout[13];
assign w1_ecc_synd_fb_to_fw_scanin[11]=w1_ecc_synd_fb_to_fw_scanout[12];
assign w1_ecc_synd_fb_to_fw_scanin[10]=w1_ecc_synd_fb_to_fw_scanout[11];
assign w1_ecc_synd_fb_to_fw_scanin[9]=w1_ecc_synd_fb_to_fw_scanout[10];
assign w1_ecc_synd_fb_to_fw_scanin[8]=w1_ecc_synd_fb_to_fw_scanout[9];
assign w1_ecc_synd_fb_to_fw_scanin[7]=w1_ecc_synd_fb_to_fw_scanout[8];
assign fw_w1data_scanin[63]=w1_ecc_synd_fb_to_fw_scanout[7];
assign fw_w1data_scanin[62]=fw_w1data_scanout[63];
assign fw_w1data_scanin[61]=fw_w1data_scanout[62];
assign fw_w1data_scanin[60]=fw_w1data_scanout[61];
assign fw_w1data_scanin[59]=fw_w1data_scanout[60];
assign fw_w1data_scanin[58]=fw_w1data_scanout[59];
assign fw_w1data_scanin[57]=fw_w1data_scanout[58];
assign fw_w1data_scanin[56]=fw_w1data_scanout[57];
assign fw_w1data_scanin[55]=fw_w1data_scanout[56];
assign fw_w1data_scanin[54]=fw_w1data_scanout[55];
assign fw_w1data_scanin[53]=fw_w1data_scanout[54];
assign fw_w1data_scanin[52]=fw_w1data_scanout[53];
assign fw_w1data_scanin[51]=fw_w1data_scanout[52];
assign fw_w1data_scanin[50]=fw_w1data_scanout[51];
assign fw_w1data_scanin[49]=fw_w1data_scanout[50];
assign fw_w1data_scanin[48]=fw_w1data_scanout[49];
assign fw_w1data_scanin[47]=fw_w1data_scanout[48];
assign fw_w1data_scanin[46]=fw_w1data_scanout[47];
assign fw_w1data_scanin[45]=fw_w1data_scanout[46];
assign fw_w1data_scanin[44]=fw_w1data_scanout[45];
assign fw_w1data_scanin[43]=fw_w1data_scanout[44];
assign fw_w1data_scanin[42]=fw_w1data_scanout[43];
assign fw_w1data_scanin[41]=fw_w1data_scanout[42];
assign fw_w1data_scanin[40]=fw_w1data_scanout[41];
assign fw_w1data_scanin[39]=fw_w1data_scanout[40];
assign fw_w1data_scanin[38]=fw_w1data_scanout[39];
assign fw_w1data_scanin[37]=fw_w1data_scanout[38];
assign fw_w1data_scanin[36]=fw_w1data_scanout[37];
assign fw_w1data_scanin[35]=fw_w1data_scanout[36];
assign fw_w1data_scanin[34]=fw_w1data_scanout[35];
assign fw_w1data_scanin[33]=fw_w1data_scanout[34];
assign fw_w1data_scanin[32]=fw_w1data_scanout[33];
assign frf_write_input_ctl_in2fb_scanin[16]=fw_w1data_scanout[32];
assign frf_read_ctl_in2ph2_scanin[14]=frf_write_input_ctl_in2fb_scanout[16];
assign frf_read_ctl_in2ph2_scanin[13]=frf_read_ctl_in2ph2_scanout[14];
assign frf_read_ctl_in2ph2_scanin[12]=frf_read_ctl_in2ph2_scanout[13];
assign frf_read_ctl_in2ph2_scanin[11]=frf_read_ctl_in2ph2_scanout[12];
assign frf_read_ctl_in2ph2_scanin[10]=frf_read_ctl_in2ph2_scanout[11];
assign frf_write_input_ctl_in2fb_scanin[9]=frf_read_ctl_in2ph2_scanout[10];
assign frf_write_input_ctl_in2fb_scanin[8]=frf_write_input_ctl_in2fb_scanout[9];
assign frf_write_input_ctl_in2fb_scanin[7]=frf_write_input_ctl_in2fb_scanout[8];
assign frf_write_input_ctl_in2fb_scanin[0]=frf_write_input_ctl_in2fb_scanout[7];
assign frf_read_ctl_in2ph2_scanin[2]=frf_write_input_ctl_in2fb_scanout[0];
assign frf_read_ctl_in2ph2_scanin[1]=frf_read_ctl_in2ph2_scanout[2];
assign frf_read_ctl_in2ph2_scanin[0]=frf_read_ctl_in2ph2_scanout[1];
assign frf_read_ctl_in2ph2_scanin[9]=frf_read_ctl_in2ph2_scanout[0];
assign frf_read_ctl_in2ph2_scanin[8]=frf_read_ctl_in2ph2_scanout[9];
assign frf_read_ctl_in2ph2_scanin[7]=frf_read_ctl_in2ph2_scanout[8];
assign frf_read_ctl_in2ph2_scanin[6]=frf_read_ctl_in2ph2_scanout[7];
assign frf_read_ctl_in2ph2_scanin[5]=frf_read_ctl_in2ph2_scanout[6];
assign frf_write_input_ctl_in2fb_scanin[4]=frf_read_ctl_in2ph2_scanout[5];
assign frf_write_input_ctl_in2fb_scanin[5]=frf_write_input_ctl_in2fb_scanout[4];
assign w1_ecc_synd_fb_to_fw_scanin[6]=frf_write_input_ctl_in2fb_scanout[5];
assign w1_ecc_synd_fb_to_fw_scanin[5]=w1_ecc_synd_fb_to_fw_scanout[6];
assign w1_ecc_synd_fb_to_fw_scanin[4]=w1_ecc_synd_fb_to_fw_scanout[5];
assign w1_ecc_synd_fb_to_fw_scanin[3]=w1_ecc_synd_fb_to_fw_scanout[4];
assign w1_ecc_synd_fb_to_fw_scanin[2]=w1_ecc_synd_fb_to_fw_scanout[3];
assign w1_ecc_synd_fb_to_fw_scanin[1]=w1_ecc_synd_fb_to_fw_scanout[2];
assign w1_ecc_synd_fb_to_fw_scanin[0]=w1_ecc_synd_fb_to_fw_scanout[1];
assign fw_w1data_scanin[31]=w1_ecc_synd_fb_to_fw_scanout[0];
assign fw_w1data_scanin[30]=fw_w1data_scanout[31];
assign fw_w1data_scanin[29]=fw_w1data_scanout[30];
assign fw_w1data_scanin[28]=fw_w1data_scanout[29];
assign fw_w1data_scanin[27]=fw_w1data_scanout[28];
assign fw_w1data_scanin[26]=fw_w1data_scanout[27];
assign fw_w1data_scanin[25]=fw_w1data_scanout[26];
assign fw_w1data_scanin[24]=fw_w1data_scanout[25];
assign fw_w1data_scanin[23]=fw_w1data_scanout[24];
assign fw_w1data_scanin[22]=fw_w1data_scanout[23];
assign fw_w1data_scanin[21]=fw_w1data_scanout[22];
assign fw_w1data_scanin[20]=fw_w1data_scanout[21];
assign fw_w1data_scanin[19]=fw_w1data_scanout[20];
assign fw_w1data_scanin[18]=fw_w1data_scanout[19];
assign fw_w1data_scanin[17]=fw_w1data_scanout[18];
assign fw_w1data_scanin[16]=fw_w1data_scanout[17];
assign fw_w1data_scanin[15]=fw_w1data_scanout[16];
assign fw_w1data_scanin[14]=fw_w1data_scanout[15];
assign fw_w1data_scanin[13]=fw_w1data_scanout[14];
assign fw_w1data_scanin[12]=fw_w1data_scanout[13];
assign fw_w1data_scanin[11]=fw_w1data_scanout[12];
assign fw_w1data_scanin[10]=fw_w1data_scanout[11];
assign fw_w1data_scanin[9]=fw_w1data_scanout[10];
assign fw_w1data_scanin[8]=fw_w1data_scanout[9];
assign fw_w1data_scanin[7]=fw_w1data_scanout[8];
assign fw_w1data_scanin[6]=fw_w1data_scanout[7];
assign fw_w1data_scanin[5]=fw_w1data_scanout[6];
assign fw_w1data_scanin[4]=fw_w1data_scanout[5];
assign fw_w1data_scanin[3]=fw_w1data_scanout[4];
assign fw_w1data_scanin[2]=fw_w1data_scanout[3];
assign fw_w1data_scanin[1]=fw_w1data_scanout[2];
assign fw_w1data_scanin[0]=fw_w1data_scanout[1];
assign fw_w2data_scanin[0]=fw_w1data_scanout[0];
assign fw_w2data_scanin[1]=fw_w2data_scanout[0];
assign fw_w2data_scanin[2]=fw_w2data_scanout[1];
assign fw_w2data_scanin[3]=fw_w2data_scanout[2];
assign fw_w2data_scanin[4]=fw_w2data_scanout[3];
assign fw_w2data_scanin[5]=fw_w2data_scanout[4];
assign fw_w2data_scanin[6]=fw_w2data_scanout[5];
assign fw_w2data_scanin[7]=fw_w2data_scanout[6];
assign fw_w2data_scanin[8]=fw_w2data_scanout[7];
assign fw_w2data_scanin[9]=fw_w2data_scanout[8];
assign fw_w2data_scanin[10]=fw_w2data_scanout[9];
assign fw_w2data_scanin[11]=fw_w2data_scanout[10];
assign fw_w2data_scanin[12]=fw_w2data_scanout[11];
assign fw_w2data_scanin[13]=fw_w2data_scanout[12];
assign fw_w2data_scanin[14]=fw_w2data_scanout[13];
assign fw_w2data_scanin[15]=fw_w2data_scanout[14];
assign fw_w2data_scanin[16]=fw_w2data_scanout[15];
assign fw_w2data_scanin[17]=fw_w2data_scanout[16];
assign fw_w2data_scanin[18]=fw_w2data_scanout[17];
assign fw_w2data_scanin[19]=fw_w2data_scanout[18];
assign fw_w2data_scanin[20]=fw_w2data_scanout[19];
assign fw_w2data_scanin[21]=fw_w2data_scanout[20];
assign fw_w2data_scanin[22]=fw_w2data_scanout[21];
assign fw_w2data_scanin[23]=fw_w2data_scanout[22];
assign fw_w2data_scanin[24]=fw_w2data_scanout[23];
assign fw_w2data_scanin[25]=fw_w2data_scanout[24];
assign fw_w2data_scanin[26]=fw_w2data_scanout[25];
assign fw_w2data_scanin[27]=fw_w2data_scanout[26];
assign fw_w2data_scanin[28]=fw_w2data_scanout[27];
assign fw_w2data_scanin[29]=fw_w2data_scanout[28];
assign fw_w2data_scanin[30]=fw_w2data_scanout[29];
assign fw_w2data_scanin[31]=fw_w2data_scanout[30];
assign w2_ecc_synd_fb_to_fw_scanin[0]=fw_w2data_scanout[31];
assign w2_ecc_synd_fb_to_fw_scanin[1]=w2_ecc_synd_fb_to_fw_scanout[0];
assign w2_ecc_synd_fb_to_fw_scanin[2]=w2_ecc_synd_fb_to_fw_scanout[1];
assign w2_ecc_synd_fb_to_fw_scanin[3]=w2_ecc_synd_fb_to_fw_scanout[2];
assign w2_ecc_synd_fb_to_fw_scanin[4]=w2_ecc_synd_fb_to_fw_scanout[3];
assign w2_ecc_synd_fb_to_fw_scanin[5]=w2_ecc_synd_fb_to_fw_scanout[4];
assign w2_ecc_synd_fb_to_fw_scanin[6]=w2_ecc_synd_fb_to_fw_scanout[5];
assign frf_write_input_ctl_in2fb_scanin[15]=w2_ecc_synd_fb_to_fw_scanout[6];
assign frf_write_input_ctl_in2fb_scanin[1]=frf_write_input_ctl_in2fb_scanout[15];
assign frf_write_input_ctl_in2fb_scanin[2]=frf_write_input_ctl_in2fb_scanout[1];
assign frf_write_input_ctl_in2fb_scanin[3]=frf_write_input_ctl_in2fb_scanout[2];
assign frf_read_ctl_in2ph2_scanin[3]=frf_write_input_ctl_in2fb_scanout[3];
assign frf_read_ctl_in2ph2_scanin[4]=frf_read_ctl_in2ph2_scanout[3];
assign frf_write_input_ctl_in2fb_scanin[10]=frf_read_ctl_in2ph2_scanout[4];
assign frf_write_input_ctl_in2fb_scanin[11]=frf_write_input_ctl_in2fb_scanout[10];
assign frf_write_input_ctl_in2fb_scanin[12]=frf_write_input_ctl_in2fb_scanout[11];
assign frf_write_input_ctl_in2fb_scanin[13]=frf_write_input_ctl_in2fb_scanout[12];
assign frf_write_input_ctl_in2fb_scanin[14]=frf_write_input_ctl_in2fb_scanout[13];
assign frf_write_input_ctl_in2fb_scanin[17]=frf_write_input_ctl_in2fb_scanout[14];
assign frf_write_input_ctl_in2fb_scanin[18]=frf_write_input_ctl_in2fb_scanout[17];
assign frf_write_input_ctl_in2fb_scanin[19]=frf_write_input_ctl_in2fb_scanout[18];
assign frf_write_input_ctl_in2fb_scanin[6]=frf_write_input_ctl_in2fb_scanout[19];
assign fw_w2data_scanin[32]=frf_write_input_ctl_in2fb_scanout[6];
assign fw_w2data_scanin[33]=fw_w2data_scanout[32];
assign fw_w2data_scanin[34]=fw_w2data_scanout[33];
assign fw_w2data_scanin[35]=fw_w2data_scanout[34];
assign fw_w2data_scanin[36]=fw_w2data_scanout[35];
assign fw_w2data_scanin[37]=fw_w2data_scanout[36];
assign fw_w2data_scanin[38]=fw_w2data_scanout[37];
assign fw_w2data_scanin[39]=fw_w2data_scanout[38];
assign fw_w2data_scanin[40]=fw_w2data_scanout[39];
assign fw_w2data_scanin[41]=fw_w2data_scanout[40];
assign fw_w2data_scanin[42]=fw_w2data_scanout[41];
assign fw_w2data_scanin[43]=fw_w2data_scanout[42];
assign fw_w2data_scanin[44]=fw_w2data_scanout[43];
assign fw_w2data_scanin[45]=fw_w2data_scanout[44];
assign fw_w2data_scanin[46]=fw_w2data_scanout[45];
assign fw_w2data_scanin[47]=fw_w2data_scanout[46];
assign fw_w2data_scanin[48]=fw_w2data_scanout[47];
assign fw_w2data_scanin[49]=fw_w2data_scanout[48];
assign fw_w2data_scanin[50]=fw_w2data_scanout[49];
assign fw_w2data_scanin[51]=fw_w2data_scanout[50];
assign fw_w2data_scanin[52]=fw_w2data_scanout[51];
assign fw_w2data_scanin[53]=fw_w2data_scanout[52];
assign fw_w2data_scanin[54]=fw_w2data_scanout[53];
assign fw_w2data_scanin[55]=fw_w2data_scanout[54];
assign fw_w2data_scanin[56]=fw_w2data_scanout[55];
assign fw_w2data_scanin[57]=fw_w2data_scanout[56];
assign fw_w2data_scanin[58]=fw_w2data_scanout[57];
assign fw_w2data_scanin[59]=fw_w2data_scanout[58];
assign fw_w2data_scanin[60]=fw_w2data_scanout[59];
assign fw_w2data_scanin[61]=fw_w2data_scanout[60];
assign fw_w2data_scanin[62]=fw_w2data_scanout[61];
assign fw_w2data_scanin[63]=fw_w2data_scanout[62];
assign w2_ecc_synd_fb_to_fw_scanin[7]=fw_w2data_scanout[63];
assign w2_ecc_synd_fb_to_fw_scanin[8]=w2_ecc_synd_fb_to_fw_scanout[7];
assign w2_ecc_synd_fb_to_fw_scanin[9]=w2_ecc_synd_fb_to_fw_scanout[8];
assign w2_ecc_synd_fb_to_fw_scanin[10]=w2_ecc_synd_fb_to_fw_scanout[9];
assign w2_ecc_synd_fb_to_fw_scanin[11]=w2_ecc_synd_fb_to_fw_scanout[10];
assign w2_ecc_synd_fb_to_fw_scanin[12]=w2_ecc_synd_fb_to_fw_scanout[11];
assign w2_ecc_synd_fb_to_fw_scanin[13]=w2_ecc_synd_fb_to_fw_scanout[12];
assign scan_out=w2_ecc_synd_fb_to_fw_scanout[13];
// fixscan end

`ifndef FPGA
// synopsys translate_on
`endif

endmodule  // fgu_frf_cust


// any PARAMS parms go into naming of macro

module n2_frf_mp_256x78_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;

  input [13:0] din;
  input l1clk;
  input [13:0] scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output [13:0] scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si(scan_in[13:0]),
.so(scan_out[13:0]),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__scanreverse_1__width_14 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [13:0] fdin;

  input [13:0] din;
  input l1clk;
  input [13:0] scan_in;


  input siclk;
  input soclk;

  output [13:0] dout;
  output [13:0] scan_out;
assign fdin[13:0] = din[13:0];


dff #(14)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[13:0]),
.si(scan_in[13:0]),
.so(scan_out[13:0]),
.q(dout[13:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_15 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [14:0] fdin;

  input [14:0] din;
  input l1clk;
  input [14:0] scan_in;


  input siclk;
  input soclk;

  output [14:0] dout;
  output [14:0] scan_out;
assign fdin[14:0] = din[14:0];


dff #(15)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[14:0]),
.si(scan_in[14:0]),
.so(scan_out[14:0]),
.q(dout[14:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__scanreverse_1__width_64 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [63:0] fdin;

  input [63:0] din;
  input l1clk;
  input [63:0] scan_in;


  input siclk;
  input soclk;

  output [63:0] dout;
  output [63:0] scan_out;
assign fdin[63:0] = din[63:0];


dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[63:0]),
.si(scan_in[63:0]),
.so(scan_out[63:0]),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_64 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [63:0] fdin;

  input [63:0] din;
  input l1clk;
  input [63:0] scan_in;


  input siclk;
  input soclk;

  output [63:0] dout;
  output [63:0] scan_out;
assign fdin[63:0] = din[63:0];


dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[63:0]),
.si(scan_in[63:0]),
.so(scan_out[63:0]),
.q(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_frf_mp_256x78_cust_msff_ctl_macro__fs_1__width_20 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [19:0] fdin;

  input [19:0] din;
  input l1clk;
  input [19:0] scan_in;


  input siclk;
  input soclk;

  output [19:0] dout;
  output [19:0] scan_out;
assign fdin[19:0] = din[19:0];


dff #(20)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[19:0]),
.si(scan_in[19:0]),
.so(scan_out[19:0]),
.q(dout[19:0])
);


endmodule


`ifndef FPGA
module fgu_frf_array (
  clk, 
  tcu_array_wr_inhibit, 
  r1_valid, 
  r1_addr, 
  r2_valid, 
  r2_addr, 
  w1_valid, 
  w1_addr, 
  w2_valid, 
  w2_addr, 
  w1_data, 
  w2_data, 
  r1_data, 
  r2_data);
wire masked_r1_valid;
wire masked_r2_valid;


   input          clk;

   input          tcu_array_wr_inhibit;

   // -----------------------------------------------------------------------
   // Reading controls
   // -----------------------------------------------------------------------
   input          r1_valid;
   input    [7:0] r1_addr;
   input          r2_valid;
   input    [7:0] r2_addr;
 
   // -----------------------------------------------------------------------
   // Writing controls 
   // -----------------------------------------------------------------------
   input          w1_valid;
   input    [7:0] w1_addr;
   input          w2_valid;
   input    [7:0] w2_addr;

   // -----------------------------------------------------------------------
   // Write data ports
   // -----------------------------------------------------------------------
   input   [38:0] w1_data;
   input   [38:0] w2_data;


   // -----------------------------------------------------------------------
   // Read output ports
   // -----------------------------------------------------------------------
   output  [38:0] r1_data;
   output  [38:0] r2_data;

   reg [38:0]    r1_data;            // *** Temporary array read regs (no physical flops involved) ***
   reg [38:0]    r2_data;            // *** Temporary array read regs (no physical flops involved) ***

   assign masked_r1_valid = r1_valid & ~(w1_valid & (r1_addr[7:0] == w1_addr[7:0]))
                                     & ~(w2_valid & (r1_addr[7:0] == w2_addr[7:0]));

   assign masked_r2_valid = r2_valid & ~(w1_valid & (r2_addr[7:0] == w1_addr[7:0]))
                                     & ~(w2_valid & (r2_addr[7:0] == w2_addr[7:0]));


   reg [38:0]    data_array[255:0];

   // *** Initialize section ***
`ifndef NOINITMEM
   integer i;
   initial begin
     for (i=0; i<=255; i=i+1) begin
     	 data_array[i] = {39{1'b0}};
     end
   end
`endif


   always @ (posedge clk) begin

            r1_data[38:0] <= {39{1'b0}};
            r2_data[38:0] <= {39{1'b0}};

   end // posedge always


   always @ (negedge clk) begin


   // -----------------------------------------------------------------------
   // *** Read Section *** 
   // -----------------------------------------------------------------------

      if (masked_r1_valid) begin
            r1_data[38:0] <= data_array[r1_addr[7:0]];
      end


      if (masked_r2_valid) begin
            r2_data[38:0] <= data_array[r2_addr[7:0]];
      end


   // -----------------------------------------------------------------------
   // *** Write Section *** 
   // -----------------------------------------------------------------------


   // 0in assert -active (w1_valid & w2_valid)  -var (w1_addr[7:0] != w2_addr[7:0]) -message "FGU FRF Multiple Write"


      if (w1_valid & ~tcu_array_wr_inhibit) begin
         data_array[w1_addr[7:0]] <= w1_data[38:0];
      end


      if (w2_valid & ~tcu_array_wr_inhibit) begin 
         data_array[w2_addr[7:0]] <= w2_data[38:0];
      end 


   end // negedge always


supply0 vss;
supply1 vdd;

endmodule  // fgu_frf_array

`endif

`ifdef FPGA
module fgu_frf_array(clk, tcu_array_wr_inhibit, r1_valid, r1_addr, r2_valid, 
	r2_addr, w1_valid, w1_addr, w2_valid, w2_addr, w1_data, w2_data, 
	r1_data, r2_data);

	input			clk;
	input			tcu_array_wr_inhibit;
	input			r1_valid;
	input	[7:0]		r1_addr;
	input			r2_valid;
	input	[7:0]		r2_addr;
	input			w1_valid;
	input	[7:0]		w1_addr;
	input			w2_valid;
	input	[7:0]		w2_addr;
	input	[38:0]		w1_data;
	input	[38:0]		w2_data;
	output	[38:0]		r1_data;
	output	[38:0]		r2_data;

	wire			masked_r1_valid;
	wire			masked_r2_valid;
	reg	[38:0]		r1_data;
	reg	[38:0]		r2_data;

  
            reg     [38:0]          data_array[255:0];
        integer                 i;

        assign masked_r1_valid = ((r1_valid & (~(w1_valid & (r1_addr[7:0] ==
                w1_addr[7:0])))) & (~(w2_valid & (r1_addr[7:0] == w2_addr[7:0]))
                ));
        assign masked_r2_valid = ((r2_valid & (~(w1_valid & (r2_addr[7:0] ==
                w1_addr[7:0])))) & (~(w2_valid & (r2_addr[7:0] == w2_addr[7:0]))
                ));

        initial begin
          for (i = 0; (i <= 255); i = (i + 1)) begin
            data_array[i] = {39 {1'b0}};
          end
        end
        always @(negedge clk) begin
          if (masked_r1_valid) begin
            r1_data[38:0] <= data_array[r1_addr[7:0]];
          end
          else
            begin
              r1_data[38:0] <= {39 {1'b0}};
            end
          if (masked_r2_valid) begin
            r2_data[38:0] <= data_array[r2_addr[7:0]];
          end
          else
            begin
              r2_data[38:0] <= {39 {1'b0}};
            end
          if (w1_valid & (~tcu_array_wr_inhibit)) begin
            data_array[w1_addr[7:0]] <= w1_data[38:0];
          end
          if (w2_valid & (~tcu_array_wr_inhibit)) begin
            data_array[w2_addr[7:0]] <= w2_data[38:0];
          end
        end

endmodule

`endif

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_irf_mp_128x72_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_irf_mp_128x72_cust (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_array_wr_inhibit, 
  tcu_scan_en, 
  tcu_se_scancollar_in, 
  clken, 
  rd_tid, 
  rd_addr_p0, 
  rd_addr_p1, 
  rd_addr_p2, 
  rd_en_p0, 
  rd_en_p1, 
  rd_en_p2, 
  wr_en_p0, 
  wr_en_p1, 
  wr_tid_p0, 
  wr_tid_p1, 
  wr_addr_p0, 
  wr_addr_p1, 
  wr_data_p0, 
  wr_data_p1, 
  save_tid, 
  save_local_addr, 
  save_even_addr, 
  save_odd_addr, 
  save_even_en, 
  save_odd_en, 
  save_local_en, 
  restore_tid, 
  restore_local_addr, 
  restore_even_addr, 
  restore_odd_addr, 
  restore_even_en, 
  restore_odd_en, 
  restore_local_en, 
  save_global_en, 
  save_global_tid, 
  save_global_addr, 
  restore_global_en, 
  restore_global_tid, 
  restore_global_addr, 
  dout_p0, 
  dout_p1, 
  dout_p2, 
  scan_out);
wire siclk;
wire soclk;
wire l1clk_sci;
wire [35:0] i_wr_data_1st_p0_ff_scanin;
wire [35:0] i_wr_data_1st_p0_ff_scanout;
wire [71:0] wr_data_p0_ff;
wire [35:0] i_wr_data_1st_p1_ff_scanin;
wire [35:0] i_wr_data_1st_p1_ff_scanout;
wire [71:0] wr_data_p1_ff;
wire [19:0] i_rd_control_ff_scanin;
wire [19:0] i_rd_control_ff_scanout;
wire l1clk_free;
wire rd_en_p0_ff;
wire rd_en_p1_ff;
wire rd_en_p2_ff;
wire [4:0] rd_addr_p0_ff;
wire [4:0] rd_addr_p1_ff;
wire [4:0] rd_addr_p2_ff;
wire [1:0] rd_tid_ff;
wire [19:0] rd_control_l1_l_unused;
wire [19:0] rd_control_ff_l_unused;
wire [19:0] rd_control_ff_unused;
wire [15:0] i_wr_control_ff_scanin;
wire [15:0] i_wr_control_ff_scanout;
wire [4:0] wr_addr_p1_ff;
wire [1:0] wr_tid_p1_ff;
wire wr_en_p1_ff;
wire [4:0] wr_addr_p0_ff;
wire [1:0] wr_tid_p0_ff;
wire wr_en_p0_ff;
wire [16:0] i_restore_ff_scanin;
wire [16:0] i_restore_ff_scanout;
wire [1:0] restore_even_addr_ff;
wire [2:0] restore_local_addr_ff;
wire [1:0] restore_odd_addr_ff;
wire [1:0] restore_global_addr_ff;
wire restore_even_en_ff;
wire restore_odd_en_ff;
wire restore_local_en_ff;
wire restore_global_en_ff;
wire [1:0] restore_tid_ff;
wire [1:0] restore_global_tid_ff;
wire [16:0] i_save_ff_scanin;
wire [16:0] i_save_ff_scanout;
wire [1:0] save_even_addr_ff;
wire [2:0] save_local_addr_ff;
wire [1:0] save_odd_addr_ff;
wire [1:0] save_global_addr_ff;
wire save_even_en_ff;
wire save_odd_en_ff;
wire save_local_en_ff;
wire save_global_en_ff;
wire [1:0] save_tid_ff;
wire [1:0] save_global_tid_ff;
wire [35:0] i_wr_data_2nd_p0_ff_scanin;
wire [35:0] i_wr_data_2nd_p0_ff_scanout;
wire [35:0] i_wr_data_2nd_p1_ff_scanin;
wire [35:0] i_wr_data_2nd_p1_ff_scanout;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_array_wr_inhibit;
input		tcu_scan_en;
input		tcu_se_scancollar_in;


// *** Power Management ***
input		clken;

// *** Reading controls ***
input [1:0]	rd_tid;
input [4:0]	rd_addr_p0;
input [4:0]	rd_addr_p1;
input [4:0]	rd_addr_p2;
input		rd_en_p0;
input		rd_en_p1;
input		rd_en_p2;

// *** Writing controls ***
input		wr_en_p0;
input		wr_en_p1;
input [1:0]	wr_tid_p0;
input [1:0]	wr_tid_p1;
input [4:0]	wr_addr_p0;
input [4:0]	wr_addr_p1;

// *** Write data ports ***
input [71:0]	wr_data_p0;
input [71:0]	wr_data_p1;

// *** Window swapping controls ***
input [1:0]	save_tid;
input [2:0]	save_local_addr;
input [1:0]	save_even_addr;
input [1:0]	save_odd_addr;
input		save_even_en;
input		save_odd_en;
input		save_local_en;

input [1:0]	restore_tid;
input [2:0]	restore_local_addr;
input [1:0]	restore_even_addr;
input [1:0]	restore_odd_addr;
input		restore_even_en;
input		restore_odd_en;
input		restore_local_en;

input		save_global_en;
input [1:0]	save_global_tid;
input [1:0]	save_global_addr;

input		restore_global_en;
input [1:0]	restore_global_tid;
input [1:0]	restore_global_addr;


output [71:0]	dout_p0;			// RS1 operand : [71:64] contains 8-bit ECC, [63:0] contains 64-bit data
output [71:0]	dout_p1;			// RS2 operand : [71:64] contains 8-bit ECC, [63:0] contains 64-bit data
output [71:0]	dout_p2;			// RS3 operand : [71:64] contains 8-bit ECC, [63:0] contains 64-bit data

output		scan_out;

`ifndef FPGA
// JDL
// synopsys translate_off
`endif

   
assign siclk	= tcu_aclk;
assign soclk	= tcu_bclk;


// 0in custom -fire (wr_en_p0       & wr_en_p1          & (wr_tid_p0[1:0]       == wr_tid_p1[1:0]))          -message "IRF p0 & p1 ports wrote to same TID"

// 0in custom -fire (save_even_en   & restore_even_en   & (save_tid[1:0]        == restore_tid[1:0]))        -message "IRF Save and Restore EVEN   to same TID"
// 0in custom -fire (save_odd_en    & restore_odd_en    & (save_tid[1:0]        == restore_tid[1:0]))        -message "IRF Save and Restore ODD    to same TID"
// 0in custom -fire (save_local_en  & restore_local_en  & (save_tid[1:0]        == restore_tid[1:0]))        -message "IRF Save and Restore LOCAL  to same TID"
// 0in custom -fire (save_global_en & restore_global_en & (save_global_tid[1:0] == restore_global_tid[1:0])) -message "IRF Save and Restore GLOBAL to same TID"


n2_irf_mp_128x72_cust_l1clkhdr_ctl_macro	clkgen_sci (
  .l2clk  (l2clk          		),
  .l1en   (clken			),
  .pce_ov (tcu_pce_ov			),
  .stop   (1'b0				),
  .se	  (tcu_se_scancollar_in		),
  .l1clk  (l1clk_sci			));


n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_36	i_wr_data_1st_p0_ff	 (
     .scan_in(i_wr_data_1st_p0_ff_scanin[35:0]),
     .scan_out(i_wr_data_1st_p0_ff_scanout[35:0]),
  .l1clk ( l1clk_sci			),
  .din   ( wr_data_p0[35:0]		),
  .dout  ( wr_data_p0_ff[35:0]		),
  .siclk(siclk),
  .soclk(soclk));


n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_36	i_wr_data_1st_p1_ff	 (
     .scan_in(i_wr_data_1st_p1_ff_scanin[35:0]),
     .scan_out(i_wr_data_1st_p1_ff_scanout[35:0]),
  .l1clk ( l1clk_sci			),
  .din   ( wr_data_p1[35:0]		),
  .dout  ( wr_data_p1_ff[35:0]		),
  .siclk(siclk),
  .soclk(soclk));


n2_irf_mp_128x72_cust_sram_msff_mo_macro__fs_1__width_20	i_rd_control_ff		 (
  .scan_in(i_rd_control_ff_scanin[19:0]),
  .scan_out(i_rd_control_ff_scanout[19:0]),
  .l1clk  ( l1clk_sci			),
  .and_clk( l1clk_free			),
  .d      ({rd_en_p0			,
	    rd_en_p1			,
	    rd_en_p2			,
	    rd_addr_p0[4:0]		,
	    rd_addr_p1[4:0]		,
	    rd_addr_p2[4:0]		,
	    rd_tid[1:0]}		),
  .mq     ({rd_en_p0_ff			,
	    rd_en_p1_ff			,
	    rd_en_p2_ff			,
	    rd_addr_p0_ff[4:0]		,
	    rd_addr_p1_ff[4:0]		,
	    rd_addr_p2_ff[4:0]		,
	    rd_tid_ff[1:0]}		),
  .mq_l   ( rd_control_l1_l_unused[19:0]),
  .q_l    ( rd_control_ff_l_unused[19:0]),
  .q      ( rd_control_ff_unused[19:0]  ),
  .siclk(siclk),
  .soclk(soclk));


n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_16	i_wr_control_ff		 (
     .scan_in(i_wr_control_ff_scanin[15:0]),
     .scan_out(i_wr_control_ff_scanout[15:0]),
  .l1clk ( l1clk_sci			),
  .din   ({wr_addr_p1[4:0]		,
	   wr_tid_p1[1:0]		,
	   wr_en_p1			,
	   wr_addr_p0[4:0]		,
	   wr_tid_p0[1:0]		,
	   wr_en_p0			}),
  .dout  ({wr_addr_p1_ff[4:0]		,
	   wr_tid_p1_ff[1:0]		,
	   wr_en_p1_ff			,
	   wr_addr_p0_ff[4:0]		,
	   wr_tid_p0_ff[1:0]		,
	   wr_en_p0_ff			}),
  .siclk(siclk),
  .soclk(soclk));


n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_17	i_restore_ff		 (
     .scan_in(i_restore_ff_scanin[16:0]),
     .scan_out(i_restore_ff_scanout[16:0]),
  .l1clk ( l1clk_sci			),
  .din   ({restore_even_addr[1:0]	,
	   restore_local_addr[2:0]	,
	   restore_odd_addr[1:0]	,
	   restore_global_addr[1:0]	,
	   restore_even_en		,
	   restore_odd_en		,
	   restore_local_en		,
	   restore_global_en		,
	   restore_tid[1:0]		,
	   restore_global_tid[1:0]	}),
  .dout  ({restore_even_addr_ff[1:0]	,
	   restore_local_addr_ff[2:0]	,
	   restore_odd_addr_ff[1:0]	,
	   restore_global_addr_ff[1:0]	,
	   restore_even_en_ff		,
	   restore_odd_en_ff		,
	   restore_local_en_ff		,
	   restore_global_en_ff		,
	   restore_tid_ff[1:0]		,
	   restore_global_tid_ff[1:0]	}),
  .siclk(siclk),
  .soclk(soclk));


n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_17	i_save_ff		 (
     .scan_in(i_save_ff_scanin[16:0]),
     .scan_out(i_save_ff_scanout[16:0]),
  .l1clk ( l1clk_sci			),
  .din   ({save_even_addr[1:0]		,
	   save_local_addr[2:0]		,
	   save_odd_addr[1:0]		,
	   save_global_addr[1:0]	,
	   save_even_en			,
	   save_odd_en			,
	   save_local_en		,
	   save_global_en		,
	   save_tid[1:0]		,
	   save_global_tid[1:0]		}),
  .dout  ({save_even_addr_ff[1:0]	,
	   save_local_addr_ff[2:0]	,
	   save_odd_addr_ff[1:0]	,
	   save_global_addr_ff[1:0]	,
	   save_even_en_ff		,
	   save_odd_en_ff		,
	   save_local_en_ff		,
	   save_global_en_ff		,
	   save_tid_ff[1:0]		,
	   save_global_tid_ff[1:0]	}),
  .siclk(siclk),
  .soclk(soclk));


n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_36	i_wr_data_2nd_p0_ff	 (
     .scan_in(i_wr_data_2nd_p0_ff_scanin[35:0]),
     .scan_out(i_wr_data_2nd_p0_ff_scanout[35:0]),
  .l1clk ( l1clk_sci			),
  .din   ( wr_data_p0[71:36]		),
  .dout  ( wr_data_p0_ff[71:36]		),
  .siclk(siclk),
  .soclk(soclk));


n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_36	i_wr_data_2nd_p1_ff	 (
     .scan_in(i_wr_data_2nd_p1_ff_scanin[35:0]),
     .scan_out(i_wr_data_2nd_p1_ff_scanout[35:0]),
  .l1clk ( l1clk_sci			),
  .din   ( wr_data_p1[71:36]		),
  .dout  ( wr_data_p1_ff[71:36]		),
  .siclk(siclk),
  .soclk(soclk));


n2_irf_mp_128x72_cust_l1clkhdr_ctl_macro	clkgen_free (
  .l2clk  (l2clk			),
  .l1en   (clken			),
  .pce_ov (tcu_pce_ov			),
  .stop	  (1'b0				),
  .se	  (tcu_scan_en			),
  .l1clk  (l1clk_free			));


exu_irf_array	irf_array		(
  .clk			( l1clk_free				),
  .a_rd_en_p0		( rd_en_p0_ff				),
  .a_rd_en_p1		( rd_en_p1_ff				),
  .a_rd_en_p2		( rd_en_p2_ff				),
  .a_rd_tid		( rd_tid_ff[1:0]			),
  .a_rd_addr_p0		( rd_addr_p0_ff[4:0]			),
  .a_rd_addr_p1		( rd_addr_p1_ff[4:0]			),
  .a_rd_addr_p2		( rd_addr_p2_ff[4:0]			),

  .a_wr_en_p0		( wr_en_p0_ff				),
  .a_wr_tid_p0		( wr_tid_p0_ff[1:0]			),
  .a_wr_addr_p0		( wr_addr_p0_ff[4:0]			),
  .a_wr_data_p0		( wr_data_p0_ff[71:0]			),
  .a_wr_en_p1		( wr_en_p1_ff				),
  .a_wr_tid_p1		( wr_tid_p1_ff[1:0]			),
  .a_wr_addr_p1		( wr_addr_p1_ff[4:0]			),
  .a_wr_data_p1		( wr_data_p1_ff[71:0]			),

  .a_save_tid		( save_tid_ff[1:0]			),
  .a_save_global_tid	( save_global_tid_ff[1:0]		),
  .a_save_global_addr	( save_global_addr_ff[1:0]		),
  .a_save_even_addr	( save_even_addr_ff[1:0]		),
  .a_save_odd_addr	( save_odd_addr_ff[1:0]			),
  .a_save_local_addr	( save_local_addr_ff[2:0]		),
  .a_save_global_en	( save_global_en_ff			),
  .a_save_even_en	( save_even_en_ff			),
  .a_save_local_en	( save_local_en_ff			),
  .a_save_odd_en	( save_odd_en_ff			),

  .a_restore_tid	( restore_tid_ff[1:0]			),
  .a_restore_global_tid	( restore_global_tid_ff[1:0]		),
  .a_restore_global_addr( restore_global_addr_ff[1:0]		),
  .a_restore_even_addr	( restore_even_addr_ff[1:0]		),
  .a_restore_odd_addr	( restore_odd_addr_ff[1:0]		),
  .a_restore_local_addr	( restore_local_addr_ff[2:0]		),
  .a_restore_global_en	( restore_global_en_ff			),
  .a_restore_even_en	( restore_even_en_ff			),
  .a_restore_local_en	( restore_local_en_ff			),
  .a_restore_odd_en	( restore_odd_en_ff			),

	.a_rd_data_p0		( dout_p0[71:0]				),
	.a_rd_data_p1		( dout_p1[71:0]				),
	.a_rd_data_p2		( dout_p2[71:0]				),
  .tcu_array_wr_inhibit(tcu_array_wr_inhibit));


supply0 vss;
supply1 vdd;


// scanorder start
//      i_wr_data_1st_p0_ff_scanin[0]
//      i_wr_data_1st_p1_ff_scanin[0]
//      i_wr_data_1st_p0_ff_scanin[1]
//      i_wr_data_1st_p1_ff_scanin[1]
//      i_wr_data_1st_p0_ff_scanin[2]
//      i_wr_data_1st_p1_ff_scanin[2]
//      i_wr_data_1st_p0_ff_scanin[3]
//      i_wr_data_1st_p1_ff_scanin[3]
//      i_wr_data_1st_p0_ff_scanin[4]
//      i_wr_data_1st_p1_ff_scanin[4]
//      i_wr_data_1st_p0_ff_scanin[5]
//      i_wr_data_1st_p1_ff_scanin[5]
//      i_wr_data_1st_p0_ff_scanin[6]
//      i_wr_data_1st_p1_ff_scanin[6]
//      i_wr_data_1st_p0_ff_scanin[7]
//      i_wr_data_1st_p1_ff_scanin[7]
//      i_wr_data_1st_p0_ff_scanin[8]
//      i_wr_data_1st_p1_ff_scanin[8]
//      i_wr_data_1st_p0_ff_scanin[9]
//      i_wr_data_1st_p1_ff_scanin[9]
//      i_wr_data_1st_p0_ff_scanin[10]
//      i_wr_data_1st_p1_ff_scanin[10]
//      i_wr_data_1st_p0_ff_scanin[11]
//      i_wr_data_1st_p1_ff_scanin[11]
//      i_wr_data_1st_p0_ff_scanin[12]
//      i_wr_data_1st_p1_ff_scanin[12]
//      i_wr_data_1st_p0_ff_scanin[13]
//      i_wr_data_1st_p1_ff_scanin[13]
//      i_wr_data_1st_p0_ff_scanin[14]
//      i_wr_data_1st_p1_ff_scanin[14]
//      i_wr_data_1st_p0_ff_scanin[15]
//      i_wr_data_1st_p1_ff_scanin[15]
//      i_wr_data_1st_p0_ff_scanin[16]
//      i_wr_data_1st_p1_ff_scanin[16]
//      i_wr_data_1st_p0_ff_scanin[17]
//      i_wr_data_1st_p1_ff_scanin[17]
//      i_wr_data_1st_p0_ff_scanin[18]
//      i_wr_data_1st_p1_ff_scanin[18]
//      i_wr_data_1st_p0_ff_scanin[19]
//      i_wr_data_1st_p1_ff_scanin[19]
//      i_wr_data_1st_p0_ff_scanin[20]
//      i_wr_data_1st_p1_ff_scanin[20]
//      i_wr_data_1st_p0_ff_scanin[21]
//      i_wr_data_1st_p1_ff_scanin[21]
//      i_wr_data_1st_p0_ff_scanin[22]
//      i_wr_data_1st_p1_ff_scanin[22]
//      i_wr_data_1st_p0_ff_scanin[23]
//      i_wr_data_1st_p1_ff_scanin[23]
//      i_wr_data_1st_p0_ff_scanin[24]
//      i_wr_data_1st_p1_ff_scanin[24]
//      i_wr_data_1st_p0_ff_scanin[25]
//      i_wr_data_1st_p1_ff_scanin[25]
//      i_wr_data_1st_p0_ff_scanin[26]
//      i_wr_data_1st_p1_ff_scanin[26]
//      i_wr_data_1st_p0_ff_scanin[27]
//      i_wr_data_1st_p1_ff_scanin[27]
//      i_wr_data_1st_p0_ff_scanin[28]
//      i_wr_data_1st_p1_ff_scanin[28]
//      i_wr_data_1st_p0_ff_scanin[29]
//      i_wr_data_1st_p1_ff_scanin[29]
//      i_wr_data_1st_p0_ff_scanin[30]
//      i_wr_data_1st_p1_ff_scanin[30]
//      i_wr_data_1st_p0_ff_scanin[31]
//      i_wr_data_1st_p1_ff_scanin[31]
//      i_wr_data_1st_p0_ff_scanin[32]
//      i_wr_data_1st_p1_ff_scanin[32]
//      i_wr_data_1st_p0_ff_scanin[33]
//      i_wr_data_1st_p1_ff_scanin[33]
//      i_wr_data_1st_p0_ff_scanin[34]
//      i_wr_data_1st_p1_ff_scanin[34]
//      i_wr_data_1st_p0_ff_scanin[35]
//      i_wr_data_1st_p1_ff_scanin[35]

//      i_rd_control_ff_scanin[1]
//      i_rd_control_ff_scanin[0]
//      i_rd_control_ff_scanin[6]
//      i_rd_control_ff_scanin[5]
//      i_rd_control_ff_scanin[4]
//      i_rd_control_ff_scanin[3]
//      i_rd_control_ff_scanin[2]
//      i_rd_control_ff_scanin[17]
//      i_rd_control_ff_scanin[7]
//      i_rd_control_ff_scanin[8]
//      i_rd_control_ff_scanin[9]
//      i_rd_control_ff_scanin[10]
//      i_rd_control_ff_scanin[11]
//      i_rd_control_ff_scanin[18]
//      i_rd_control_ff_scanin[12]
//      i_rd_control_ff_scanin[13]
//      i_rd_control_ff_scanin[14]
//      i_rd_control_ff_scanin[15]
//      i_rd_control_ff_scanin[16]
//      i_rd_control_ff_scanin[19]

//      i_wr_control_ff_scanin[0]
//      i_wr_control_ff_scanin[1]
//      i_wr_control_ff_scanin[2]
//      i_wr_control_ff_scanin[8]
//      i_wr_control_ff_scanin[9]
//      i_wr_control_ff_scanin[10]
//      i_wr_control_ff_scanin[3]
//      i_wr_control_ff_scanin[4]
//      i_wr_control_ff_scanin[5]
//      i_wr_control_ff_scanin[6]
//      i_wr_control_ff_scanin[7]
//      i_wr_control_ff_scanin[11]
//      i_wr_control_ff_scanin[12]
//      i_wr_control_ff_scanin[13]
//      i_wr_control_ff_scanin[14]
//      i_wr_control_ff_scanin[15]


//      i_restore_ff_scanin[1]
//      i_restore_ff_scanin[0]
//      i_restore_ff_scanin[2]
//      i_restore_ff_scanin[3]
//      i_restore_ff_scanin[4]
//      i_restore_ff_scanin[6]
//      i_restore_ff_scanin[5]
//      i_restore_ff_scanin[11]
//      i_restore_ff_scanin[10]
//      i_restore_ff_scanin[9]
//      i_restore_ff_scanin[8]
//      i_restore_ff_scanin[7]
//      i_restore_ff_scanin[12]
//      i_restore_ff_scanin[13]
//      i_restore_ff_scanin[14]
//      i_restore_ff_scanin[15]
//      i_restore_ff_scanin[16]

//      i_save_ff_scanin[1]
//      i_save_ff_scanin[0]
//      i_save_ff_scanin[2]
//      i_save_ff_scanin[3]
//      i_save_ff_scanin[4]
//      i_save_ff_scanin[6]
//      i_save_ff_scanin[5]
//      i_save_ff_scanin[11]
//      i_save_ff_scanin[10]
//      i_save_ff_scanin[9]
//      i_save_ff_scanin[8]
//      i_save_ff_scanin[7]
//      i_save_ff_scanin[12]
//      i_save_ff_scanin[13]
//      i_save_ff_scanin[14]
//      i_save_ff_scanin[15]
//      i_save_ff_scanin[16]


//      i_wr_data_2nd_p0_ff_scanin[0]
//      i_wr_data_2nd_p1_ff_scanin[0]
//      i_wr_data_2nd_p0_ff_scanin[1]
//      i_wr_data_2nd_p1_ff_scanin[1]
//      i_wr_data_2nd_p0_ff_scanin[2]
//      i_wr_data_2nd_p1_ff_scanin[2]
//      i_wr_data_2nd_p0_ff_scanin[3]
//      i_wr_data_2nd_p1_ff_scanin[3]
//      i_wr_data_2nd_p0_ff_scanin[4]
//      i_wr_data_2nd_p1_ff_scanin[4]
//      i_wr_data_2nd_p0_ff_scanin[5]
//      i_wr_data_2nd_p1_ff_scanin[5]
//      i_wr_data_2nd_p0_ff_scanin[6]
//      i_wr_data_2nd_p1_ff_scanin[6]
//      i_wr_data_2nd_p0_ff_scanin[7]
//      i_wr_data_2nd_p1_ff_scanin[7]
//      i_wr_data_2nd_p0_ff_scanin[8]
//      i_wr_data_2nd_p1_ff_scanin[8]
//      i_wr_data_2nd_p0_ff_scanin[9]
//      i_wr_data_2nd_p1_ff_scanin[9]
//      i_wr_data_2nd_p0_ff_scanin[10]
//      i_wr_data_2nd_p1_ff_scanin[10]
//      i_wr_data_2nd_p0_ff_scanin[11]
//      i_wr_data_2nd_p1_ff_scanin[11]
//      i_wr_data_2nd_p0_ff_scanin[12]
//      i_wr_data_2nd_p1_ff_scanin[12]
//      i_wr_data_2nd_p0_ff_scanin[13]
//      i_wr_data_2nd_p1_ff_scanin[13]
//      i_wr_data_2nd_p0_ff_scanin[14]
//      i_wr_data_2nd_p1_ff_scanin[14]
//      i_wr_data_2nd_p0_ff_scanin[15]
//      i_wr_data_2nd_p1_ff_scanin[15]
//      i_wr_data_2nd_p0_ff_scanin[16]
//      i_wr_data_2nd_p1_ff_scanin[16]
//      i_wr_data_2nd_p0_ff_scanin[17]
//      i_wr_data_2nd_p1_ff_scanin[17]
//      i_wr_data_2nd_p0_ff_scanin[18]
//      i_wr_data_2nd_p1_ff_scanin[18]
//      i_wr_data_2nd_p0_ff_scanin[19]
//      i_wr_data_2nd_p1_ff_scanin[19]
//      i_wr_data_2nd_p0_ff_scanin[20]
//      i_wr_data_2nd_p1_ff_scanin[20]
//      i_wr_data_2nd_p0_ff_scanin[21]
//      i_wr_data_2nd_p1_ff_scanin[21]
//      i_wr_data_2nd_p0_ff_scanin[22]
//      i_wr_data_2nd_p1_ff_scanin[22]
//      i_wr_data_2nd_p0_ff_scanin[23]
//      i_wr_data_2nd_p1_ff_scanin[23]
//      i_wr_data_2nd_p0_ff_scanin[24]
//      i_wr_data_2nd_p1_ff_scanin[24]
//      i_wr_data_2nd_p0_ff_scanin[25]
//      i_wr_data_2nd_p1_ff_scanin[25]
//      i_wr_data_2nd_p0_ff_scanin[26]
//      i_wr_data_2nd_p1_ff_scanin[26]
//      i_wr_data_2nd_p0_ff_scanin[27]
//      i_wr_data_2nd_p1_ff_scanin[27]
//      i_wr_data_2nd_p0_ff_scanin[28]
//      i_wr_data_2nd_p1_ff_scanin[28]
//      i_wr_data_2nd_p0_ff_scanin[29]
//      i_wr_data_2nd_p1_ff_scanin[29]
//      i_wr_data_2nd_p0_ff_scanin[30]
//      i_wr_data_2nd_p1_ff_scanin[30]
//      i_wr_data_2nd_p0_ff_scanin[31]
//      i_wr_data_2nd_p1_ff_scanin[31]
//      i_wr_data_2nd_p0_ff_scanin[32]
//      i_wr_data_2nd_p1_ff_scanin[32]
//      i_wr_data_2nd_p0_ff_scanin[33]
//      i_wr_data_2nd_p1_ff_scanin[33]
//      i_wr_data_2nd_p0_ff_scanin[34]
//      i_wr_data_2nd_p1_ff_scanin[34]
//      i_wr_data_2nd_p0_ff_scanin[35]
//      i_wr_data_2nd_p1_ff_scanin[35]

// scanorder end
// fixscan start
assign i_wr_data_1st_p0_ff_scanin[0]=scan_in;
assign i_wr_data_1st_p1_ff_scanin[0]=i_wr_data_1st_p0_ff_scanout[0];
assign i_wr_data_1st_p0_ff_scanin[1]=i_wr_data_1st_p1_ff_scanout[0];
assign i_wr_data_1st_p1_ff_scanin[1]=i_wr_data_1st_p0_ff_scanout[1];
assign i_wr_data_1st_p0_ff_scanin[2]=i_wr_data_1st_p1_ff_scanout[1];
assign i_wr_data_1st_p1_ff_scanin[2]=i_wr_data_1st_p0_ff_scanout[2];
assign i_wr_data_1st_p0_ff_scanin[3]=i_wr_data_1st_p1_ff_scanout[2];
assign i_wr_data_1st_p1_ff_scanin[3]=i_wr_data_1st_p0_ff_scanout[3];
assign i_wr_data_1st_p0_ff_scanin[4]=i_wr_data_1st_p1_ff_scanout[3];
assign i_wr_data_1st_p1_ff_scanin[4]=i_wr_data_1st_p0_ff_scanout[4];
assign i_wr_data_1st_p0_ff_scanin[5]=i_wr_data_1st_p1_ff_scanout[4];
assign i_wr_data_1st_p1_ff_scanin[5]=i_wr_data_1st_p0_ff_scanout[5];
assign i_wr_data_1st_p0_ff_scanin[6]=i_wr_data_1st_p1_ff_scanout[5];
assign i_wr_data_1st_p1_ff_scanin[6]=i_wr_data_1st_p0_ff_scanout[6];
assign i_wr_data_1st_p0_ff_scanin[7]=i_wr_data_1st_p1_ff_scanout[6];
assign i_wr_data_1st_p1_ff_scanin[7]=i_wr_data_1st_p0_ff_scanout[7];
assign i_wr_data_1st_p0_ff_scanin[8]=i_wr_data_1st_p1_ff_scanout[7];
assign i_wr_data_1st_p1_ff_scanin[8]=i_wr_data_1st_p0_ff_scanout[8];
assign i_wr_data_1st_p0_ff_scanin[9]=i_wr_data_1st_p1_ff_scanout[8];
assign i_wr_data_1st_p1_ff_scanin[9]=i_wr_data_1st_p0_ff_scanout[9];
assign i_wr_data_1st_p0_ff_scanin[10]=i_wr_data_1st_p1_ff_scanout[9];
assign i_wr_data_1st_p1_ff_scanin[10]=i_wr_data_1st_p0_ff_scanout[10];
assign i_wr_data_1st_p0_ff_scanin[11]=i_wr_data_1st_p1_ff_scanout[10];
assign i_wr_data_1st_p1_ff_scanin[11]=i_wr_data_1st_p0_ff_scanout[11];
assign i_wr_data_1st_p0_ff_scanin[12]=i_wr_data_1st_p1_ff_scanout[11];
assign i_wr_data_1st_p1_ff_scanin[12]=i_wr_data_1st_p0_ff_scanout[12];
assign i_wr_data_1st_p0_ff_scanin[13]=i_wr_data_1st_p1_ff_scanout[12];
assign i_wr_data_1st_p1_ff_scanin[13]=i_wr_data_1st_p0_ff_scanout[13];
assign i_wr_data_1st_p0_ff_scanin[14]=i_wr_data_1st_p1_ff_scanout[13];
assign i_wr_data_1st_p1_ff_scanin[14]=i_wr_data_1st_p0_ff_scanout[14];
assign i_wr_data_1st_p0_ff_scanin[15]=i_wr_data_1st_p1_ff_scanout[14];
assign i_wr_data_1st_p1_ff_scanin[15]=i_wr_data_1st_p0_ff_scanout[15];
assign i_wr_data_1st_p0_ff_scanin[16]=i_wr_data_1st_p1_ff_scanout[15];
assign i_wr_data_1st_p1_ff_scanin[16]=i_wr_data_1st_p0_ff_scanout[16];
assign i_wr_data_1st_p0_ff_scanin[17]=i_wr_data_1st_p1_ff_scanout[16];
assign i_wr_data_1st_p1_ff_scanin[17]=i_wr_data_1st_p0_ff_scanout[17];
assign i_wr_data_1st_p0_ff_scanin[18]=i_wr_data_1st_p1_ff_scanout[17];
assign i_wr_data_1st_p1_ff_scanin[18]=i_wr_data_1st_p0_ff_scanout[18];
assign i_wr_data_1st_p0_ff_scanin[19]=i_wr_data_1st_p1_ff_scanout[18];
assign i_wr_data_1st_p1_ff_scanin[19]=i_wr_data_1st_p0_ff_scanout[19];
assign i_wr_data_1st_p0_ff_scanin[20]=i_wr_data_1st_p1_ff_scanout[19];
assign i_wr_data_1st_p1_ff_scanin[20]=i_wr_data_1st_p0_ff_scanout[20];
assign i_wr_data_1st_p0_ff_scanin[21]=i_wr_data_1st_p1_ff_scanout[20];
assign i_wr_data_1st_p1_ff_scanin[21]=i_wr_data_1st_p0_ff_scanout[21];
assign i_wr_data_1st_p0_ff_scanin[22]=i_wr_data_1st_p1_ff_scanout[21];
assign i_wr_data_1st_p1_ff_scanin[22]=i_wr_data_1st_p0_ff_scanout[22];
assign i_wr_data_1st_p0_ff_scanin[23]=i_wr_data_1st_p1_ff_scanout[22];
assign i_wr_data_1st_p1_ff_scanin[23]=i_wr_data_1st_p0_ff_scanout[23];
assign i_wr_data_1st_p0_ff_scanin[24]=i_wr_data_1st_p1_ff_scanout[23];
assign i_wr_data_1st_p1_ff_scanin[24]=i_wr_data_1st_p0_ff_scanout[24];
assign i_wr_data_1st_p0_ff_scanin[25]=i_wr_data_1st_p1_ff_scanout[24];
assign i_wr_data_1st_p1_ff_scanin[25]=i_wr_data_1st_p0_ff_scanout[25];
assign i_wr_data_1st_p0_ff_scanin[26]=i_wr_data_1st_p1_ff_scanout[25];
assign i_wr_data_1st_p1_ff_scanin[26]=i_wr_data_1st_p0_ff_scanout[26];
assign i_wr_data_1st_p0_ff_scanin[27]=i_wr_data_1st_p1_ff_scanout[26];
assign i_wr_data_1st_p1_ff_scanin[27]=i_wr_data_1st_p0_ff_scanout[27];
assign i_wr_data_1st_p0_ff_scanin[28]=i_wr_data_1st_p1_ff_scanout[27];
assign i_wr_data_1st_p1_ff_scanin[28]=i_wr_data_1st_p0_ff_scanout[28];
assign i_wr_data_1st_p0_ff_scanin[29]=i_wr_data_1st_p1_ff_scanout[28];
assign i_wr_data_1st_p1_ff_scanin[29]=i_wr_data_1st_p0_ff_scanout[29];
assign i_wr_data_1st_p0_ff_scanin[30]=i_wr_data_1st_p1_ff_scanout[29];
assign i_wr_data_1st_p1_ff_scanin[30]=i_wr_data_1st_p0_ff_scanout[30];
assign i_wr_data_1st_p0_ff_scanin[31]=i_wr_data_1st_p1_ff_scanout[30];
assign i_wr_data_1st_p1_ff_scanin[31]=i_wr_data_1st_p0_ff_scanout[31];
assign i_wr_data_1st_p0_ff_scanin[32]=i_wr_data_1st_p1_ff_scanout[31];
assign i_wr_data_1st_p1_ff_scanin[32]=i_wr_data_1st_p0_ff_scanout[32];
assign i_wr_data_1st_p0_ff_scanin[33]=i_wr_data_1st_p1_ff_scanout[32];
assign i_wr_data_1st_p1_ff_scanin[33]=i_wr_data_1st_p0_ff_scanout[33];
assign i_wr_data_1st_p0_ff_scanin[34]=i_wr_data_1st_p1_ff_scanout[33];
assign i_wr_data_1st_p1_ff_scanin[34]=i_wr_data_1st_p0_ff_scanout[34];
assign i_wr_data_1st_p0_ff_scanin[35]=i_wr_data_1st_p1_ff_scanout[34];
assign i_wr_data_1st_p1_ff_scanin[35]=i_wr_data_1st_p0_ff_scanout[35];
assign i_rd_control_ff_scanin[1]=i_wr_data_1st_p1_ff_scanout[35];
assign i_rd_control_ff_scanin[0]=i_rd_control_ff_scanout[1];
assign i_rd_control_ff_scanin[6]=i_rd_control_ff_scanout[0];
assign i_rd_control_ff_scanin[5]=i_rd_control_ff_scanout[6];
assign i_rd_control_ff_scanin[4]=i_rd_control_ff_scanout[5];
assign i_rd_control_ff_scanin[3]=i_rd_control_ff_scanout[4];
assign i_rd_control_ff_scanin[2]=i_rd_control_ff_scanout[3];
assign i_rd_control_ff_scanin[17]=i_rd_control_ff_scanout[2];
assign i_rd_control_ff_scanin[7]=i_rd_control_ff_scanout[17];
assign i_rd_control_ff_scanin[8]=i_rd_control_ff_scanout[7];
assign i_rd_control_ff_scanin[9]=i_rd_control_ff_scanout[8];
assign i_rd_control_ff_scanin[10]=i_rd_control_ff_scanout[9];
assign i_rd_control_ff_scanin[11]=i_rd_control_ff_scanout[10];
assign i_rd_control_ff_scanin[18]=i_rd_control_ff_scanout[11];
assign i_rd_control_ff_scanin[12]=i_rd_control_ff_scanout[18];
assign i_rd_control_ff_scanin[13]=i_rd_control_ff_scanout[12];
assign i_rd_control_ff_scanin[14]=i_rd_control_ff_scanout[13];
assign i_rd_control_ff_scanin[15]=i_rd_control_ff_scanout[14];
assign i_rd_control_ff_scanin[16]=i_rd_control_ff_scanout[15];
assign i_rd_control_ff_scanin[19]=i_rd_control_ff_scanout[16];
assign i_wr_control_ff_scanin[0]=i_rd_control_ff_scanout[19];
assign i_wr_control_ff_scanin[1]=i_wr_control_ff_scanout[0];
assign i_wr_control_ff_scanin[2]=i_wr_control_ff_scanout[1];
assign i_wr_control_ff_scanin[8]=i_wr_control_ff_scanout[2];
assign i_wr_control_ff_scanin[9]=i_wr_control_ff_scanout[8];
assign i_wr_control_ff_scanin[10]=i_wr_control_ff_scanout[9];
assign i_wr_control_ff_scanin[3]=i_wr_control_ff_scanout[10];
assign i_wr_control_ff_scanin[4]=i_wr_control_ff_scanout[3];
assign i_wr_control_ff_scanin[5]=i_wr_control_ff_scanout[4];
assign i_wr_control_ff_scanin[6]=i_wr_control_ff_scanout[5];
assign i_wr_control_ff_scanin[7]=i_wr_control_ff_scanout[6];
assign i_wr_control_ff_scanin[11]=i_wr_control_ff_scanout[7];
assign i_wr_control_ff_scanin[12]=i_wr_control_ff_scanout[11];
assign i_wr_control_ff_scanin[13]=i_wr_control_ff_scanout[12];
assign i_wr_control_ff_scanin[14]=i_wr_control_ff_scanout[13];
assign i_wr_control_ff_scanin[15]=i_wr_control_ff_scanout[14];
assign i_restore_ff_scanin[1]=i_wr_control_ff_scanout[15];
assign i_restore_ff_scanin[0]=i_restore_ff_scanout[1];
assign i_restore_ff_scanin[2]=i_restore_ff_scanout[0];
assign i_restore_ff_scanin[3]=i_restore_ff_scanout[2];
assign i_restore_ff_scanin[4]=i_restore_ff_scanout[3];
assign i_restore_ff_scanin[6]=i_restore_ff_scanout[4];
assign i_restore_ff_scanin[5]=i_restore_ff_scanout[6];
assign i_restore_ff_scanin[11]=i_restore_ff_scanout[5];
assign i_restore_ff_scanin[10]=i_restore_ff_scanout[11];
assign i_restore_ff_scanin[9]=i_restore_ff_scanout[10];
assign i_restore_ff_scanin[8]=i_restore_ff_scanout[9];
assign i_restore_ff_scanin[7]=i_restore_ff_scanout[8];
assign i_restore_ff_scanin[12]=i_restore_ff_scanout[7];
assign i_restore_ff_scanin[13]=i_restore_ff_scanout[12];
assign i_restore_ff_scanin[14]=i_restore_ff_scanout[13];
assign i_restore_ff_scanin[15]=i_restore_ff_scanout[14];
assign i_restore_ff_scanin[16]=i_restore_ff_scanout[15];
assign i_save_ff_scanin[1]=i_restore_ff_scanout[16];
assign i_save_ff_scanin[0]=i_save_ff_scanout[1];
assign i_save_ff_scanin[2]=i_save_ff_scanout[0];
assign i_save_ff_scanin[3]=i_save_ff_scanout[2];
assign i_save_ff_scanin[4]=i_save_ff_scanout[3];
assign i_save_ff_scanin[6]=i_save_ff_scanout[4];
assign i_save_ff_scanin[5]=i_save_ff_scanout[6];
assign i_save_ff_scanin[11]=i_save_ff_scanout[5];
assign i_save_ff_scanin[10]=i_save_ff_scanout[11];
assign i_save_ff_scanin[9]=i_save_ff_scanout[10];
assign i_save_ff_scanin[8]=i_save_ff_scanout[9];
assign i_save_ff_scanin[7]=i_save_ff_scanout[8];
assign i_save_ff_scanin[12]=i_save_ff_scanout[7];
assign i_save_ff_scanin[13]=i_save_ff_scanout[12];
assign i_save_ff_scanin[14]=i_save_ff_scanout[13];
assign i_save_ff_scanin[15]=i_save_ff_scanout[14];
assign i_save_ff_scanin[16]=i_save_ff_scanout[15];
assign i_wr_data_2nd_p0_ff_scanin[0]=i_save_ff_scanout[16];
assign i_wr_data_2nd_p1_ff_scanin[0]=i_wr_data_2nd_p0_ff_scanout[0];
assign i_wr_data_2nd_p0_ff_scanin[1]=i_wr_data_2nd_p1_ff_scanout[0];
assign i_wr_data_2nd_p1_ff_scanin[1]=i_wr_data_2nd_p0_ff_scanout[1];
assign i_wr_data_2nd_p0_ff_scanin[2]=i_wr_data_2nd_p1_ff_scanout[1];
assign i_wr_data_2nd_p1_ff_scanin[2]=i_wr_data_2nd_p0_ff_scanout[2];
assign i_wr_data_2nd_p0_ff_scanin[3]=i_wr_data_2nd_p1_ff_scanout[2];
assign i_wr_data_2nd_p1_ff_scanin[3]=i_wr_data_2nd_p0_ff_scanout[3];
assign i_wr_data_2nd_p0_ff_scanin[4]=i_wr_data_2nd_p1_ff_scanout[3];
assign i_wr_data_2nd_p1_ff_scanin[4]=i_wr_data_2nd_p0_ff_scanout[4];
assign i_wr_data_2nd_p0_ff_scanin[5]=i_wr_data_2nd_p1_ff_scanout[4];
assign i_wr_data_2nd_p1_ff_scanin[5]=i_wr_data_2nd_p0_ff_scanout[5];
assign i_wr_data_2nd_p0_ff_scanin[6]=i_wr_data_2nd_p1_ff_scanout[5];
assign i_wr_data_2nd_p1_ff_scanin[6]=i_wr_data_2nd_p0_ff_scanout[6];
assign i_wr_data_2nd_p0_ff_scanin[7]=i_wr_data_2nd_p1_ff_scanout[6];
assign i_wr_data_2nd_p1_ff_scanin[7]=i_wr_data_2nd_p0_ff_scanout[7];
assign i_wr_data_2nd_p0_ff_scanin[8]=i_wr_data_2nd_p1_ff_scanout[7];
assign i_wr_data_2nd_p1_ff_scanin[8]=i_wr_data_2nd_p0_ff_scanout[8];
assign i_wr_data_2nd_p0_ff_scanin[9]=i_wr_data_2nd_p1_ff_scanout[8];
assign i_wr_data_2nd_p1_ff_scanin[9]=i_wr_data_2nd_p0_ff_scanout[9];
assign i_wr_data_2nd_p0_ff_scanin[10]=i_wr_data_2nd_p1_ff_scanout[9];
assign i_wr_data_2nd_p1_ff_scanin[10]=i_wr_data_2nd_p0_ff_scanout[10];
assign i_wr_data_2nd_p0_ff_scanin[11]=i_wr_data_2nd_p1_ff_scanout[10];
assign i_wr_data_2nd_p1_ff_scanin[11]=i_wr_data_2nd_p0_ff_scanout[11];
assign i_wr_data_2nd_p0_ff_scanin[12]=i_wr_data_2nd_p1_ff_scanout[11];
assign i_wr_data_2nd_p1_ff_scanin[12]=i_wr_data_2nd_p0_ff_scanout[12];
assign i_wr_data_2nd_p0_ff_scanin[13]=i_wr_data_2nd_p1_ff_scanout[12];
assign i_wr_data_2nd_p1_ff_scanin[13]=i_wr_data_2nd_p0_ff_scanout[13];
assign i_wr_data_2nd_p0_ff_scanin[14]=i_wr_data_2nd_p1_ff_scanout[13];
assign i_wr_data_2nd_p1_ff_scanin[14]=i_wr_data_2nd_p0_ff_scanout[14];
assign i_wr_data_2nd_p0_ff_scanin[15]=i_wr_data_2nd_p1_ff_scanout[14];
assign i_wr_data_2nd_p1_ff_scanin[15]=i_wr_data_2nd_p0_ff_scanout[15];
assign i_wr_data_2nd_p0_ff_scanin[16]=i_wr_data_2nd_p1_ff_scanout[15];
assign i_wr_data_2nd_p1_ff_scanin[16]=i_wr_data_2nd_p0_ff_scanout[16];
assign i_wr_data_2nd_p0_ff_scanin[17]=i_wr_data_2nd_p1_ff_scanout[16];
assign i_wr_data_2nd_p1_ff_scanin[17]=i_wr_data_2nd_p0_ff_scanout[17];
assign i_wr_data_2nd_p0_ff_scanin[18]=i_wr_data_2nd_p1_ff_scanout[17];
assign i_wr_data_2nd_p1_ff_scanin[18]=i_wr_data_2nd_p0_ff_scanout[18];
assign i_wr_data_2nd_p0_ff_scanin[19]=i_wr_data_2nd_p1_ff_scanout[18];
assign i_wr_data_2nd_p1_ff_scanin[19]=i_wr_data_2nd_p0_ff_scanout[19];
assign i_wr_data_2nd_p0_ff_scanin[20]=i_wr_data_2nd_p1_ff_scanout[19];
assign i_wr_data_2nd_p1_ff_scanin[20]=i_wr_data_2nd_p0_ff_scanout[20];
assign i_wr_data_2nd_p0_ff_scanin[21]=i_wr_data_2nd_p1_ff_scanout[20];
assign i_wr_data_2nd_p1_ff_scanin[21]=i_wr_data_2nd_p0_ff_scanout[21];
assign i_wr_data_2nd_p0_ff_scanin[22]=i_wr_data_2nd_p1_ff_scanout[21];
assign i_wr_data_2nd_p1_ff_scanin[22]=i_wr_data_2nd_p0_ff_scanout[22];
assign i_wr_data_2nd_p0_ff_scanin[23]=i_wr_data_2nd_p1_ff_scanout[22];
assign i_wr_data_2nd_p1_ff_scanin[23]=i_wr_data_2nd_p0_ff_scanout[23];
assign i_wr_data_2nd_p0_ff_scanin[24]=i_wr_data_2nd_p1_ff_scanout[23];
assign i_wr_data_2nd_p1_ff_scanin[24]=i_wr_data_2nd_p0_ff_scanout[24];
assign i_wr_data_2nd_p0_ff_scanin[25]=i_wr_data_2nd_p1_ff_scanout[24];
assign i_wr_data_2nd_p1_ff_scanin[25]=i_wr_data_2nd_p0_ff_scanout[25];
assign i_wr_data_2nd_p0_ff_scanin[26]=i_wr_data_2nd_p1_ff_scanout[25];
assign i_wr_data_2nd_p1_ff_scanin[26]=i_wr_data_2nd_p0_ff_scanout[26];
assign i_wr_data_2nd_p0_ff_scanin[27]=i_wr_data_2nd_p1_ff_scanout[26];
assign i_wr_data_2nd_p1_ff_scanin[27]=i_wr_data_2nd_p0_ff_scanout[27];
assign i_wr_data_2nd_p0_ff_scanin[28]=i_wr_data_2nd_p1_ff_scanout[27];
assign i_wr_data_2nd_p1_ff_scanin[28]=i_wr_data_2nd_p0_ff_scanout[28];
assign i_wr_data_2nd_p0_ff_scanin[29]=i_wr_data_2nd_p1_ff_scanout[28];
assign i_wr_data_2nd_p1_ff_scanin[29]=i_wr_data_2nd_p0_ff_scanout[29];
assign i_wr_data_2nd_p0_ff_scanin[30]=i_wr_data_2nd_p1_ff_scanout[29];
assign i_wr_data_2nd_p1_ff_scanin[30]=i_wr_data_2nd_p0_ff_scanout[30];
assign i_wr_data_2nd_p0_ff_scanin[31]=i_wr_data_2nd_p1_ff_scanout[30];
assign i_wr_data_2nd_p1_ff_scanin[31]=i_wr_data_2nd_p0_ff_scanout[31];
assign i_wr_data_2nd_p0_ff_scanin[32]=i_wr_data_2nd_p1_ff_scanout[31];
assign i_wr_data_2nd_p1_ff_scanin[32]=i_wr_data_2nd_p0_ff_scanout[32];
assign i_wr_data_2nd_p0_ff_scanin[33]=i_wr_data_2nd_p1_ff_scanout[32];
assign i_wr_data_2nd_p1_ff_scanin[33]=i_wr_data_2nd_p0_ff_scanout[33];
assign i_wr_data_2nd_p0_ff_scanin[34]=i_wr_data_2nd_p1_ff_scanout[33];
assign i_wr_data_2nd_p1_ff_scanin[34]=i_wr_data_2nd_p0_ff_scanout[34];
assign i_wr_data_2nd_p0_ff_scanin[35]=i_wr_data_2nd_p1_ff_scanout[34];
assign i_wr_data_2nd_p1_ff_scanin[35]=i_wr_data_2nd_p0_ff_scanout[35];
assign scan_out=i_wr_data_2nd_p1_ff_scanout[35];
// fixscan end

`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_irf_mp_128x72_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_36 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [35:0] fdin;

  input [35:0] din;
  input l1clk;
  input [35:0] scan_in;


  input siclk;
  input soclk;

  output [35:0] dout;
  output [35:0] scan_out;
assign fdin[35:0] = din[35:0];


dff #(36)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[35:0]),
.si(scan_in[35:0]),
.so(scan_out[35:0]),
.q(dout[35:0])
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_irf_mp_128x72_cust_sram_msff_mo_macro__fs_1__width_20 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [19:0] d;
  input [19:0] scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [19:0] mq;
output [19:0] mq_l;
  output [19:0] scan_out;
output [19:0] q;
output [19:0] q_l;


new_dlata #(20)  d0_0 (
.d(d[19:0]),
.si(scan_in[19:0]),
.so(scan_out[19:0]),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[19:0]),
.q_l(q_l[19:0]),
.mq(mq[19:0]),
.mq_l(mq_l[19:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;

  input [15:0] din;
  input l1clk;
  input [15:0] scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output [15:0] scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si(scan_in[15:0]),
.so(scan_out[15:0]),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_irf_mp_128x72_cust_msff_ctl_macro__fs_1__width_17 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [16:0] fdin;

  input [16:0] din;
  input l1clk;
  input [16:0] scan_in;


  input siclk;
  input soclk;

  output [16:0] dout;
  output [16:0] scan_out;
assign fdin[16:0] = din[16:0];


dff #(17)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[16:0]),
.si(scan_in[16:0]),
.so(scan_out[16:0]),
.q(dout[16:0])
);


endmodule


`ifndef FPGA

module exu_irf_array (
  clk, 
  tcu_array_wr_inhibit, 
  a_rd_en_p0, 
  a_rd_en_p1, 
  a_rd_en_p2, 
  a_rd_tid, 
  a_rd_addr_p0, 
  a_rd_addr_p1, 
  a_rd_addr_p2, 
  a_wr_en_p0, 
  a_wr_tid_p0, 
  a_wr_addr_p0, 
  a_wr_data_p0, 
  a_wr_en_p1, 
  a_wr_tid_p1, 
  a_wr_addr_p1, 
  a_wr_data_p1, 
  a_save_tid, 
  a_save_global_tid, 
  a_save_global_addr, 
  a_save_even_addr, 
  a_save_local_addr, 
  a_save_odd_addr, 
  a_save_global_en, 
  a_save_even_en, 
  a_save_local_en, 
  a_save_odd_en, 
  a_restore_tid, 
  a_restore_global_tid, 
  a_restore_global_addr, 
  a_restore_even_addr, 
  a_restore_odd_addr, 
  a_restore_local_addr, 
  a_restore_global_en, 
  a_restore_even_en, 
  a_restore_local_en, 
  a_restore_odd_en, 
  a_rd_data_p0, 
  a_rd_data_p1, 
  a_rd_data_p2);
wire [6:0] thr_rs1;
wire [6:0] thr_rs2;
wire [6:0] thr_rs3;
wire [6:0] thr_rd_w;
wire [6:0] thr_rd_w2;
wire rd_en_p0;
wire rd_en_p1;
wire rd_en_p2;
wire wr_en_p0;
wire wr_en_p1;
wire p0_rd_eq_wr;
wire p1_rd_eq_wr;
wire p2_rd_eq_wr;


input		clk;

input		tcu_array_wr_inhibit;

input		a_rd_en_p0;
input		a_rd_en_p1;
input		a_rd_en_p2;
input  [1:0]	a_rd_tid;
input  [4:0]	a_rd_addr_p0;
input  [4:0]	a_rd_addr_p1;
input  [4:0]	a_rd_addr_p2;

input		a_wr_en_p0;
input  [1:0]	a_wr_tid_p0;
input  [4:0]	a_wr_addr_p0;
input  [71:0]	a_wr_data_p0;

input		a_wr_en_p1;
input  [1:0]	a_wr_tid_p1;
input  [4:0]	a_wr_addr_p1;
input  [71:0]	a_wr_data_p1;


input  [1:0]	a_save_tid;
input  [1:0]	a_save_global_tid;
input  [1:0]	a_save_global_addr;
input  [2:1]	a_save_even_addr;
input  [2:0]	a_save_local_addr;
input  [2:1]	a_save_odd_addr;
input		a_save_global_en;
input		a_save_even_en;
input		a_save_local_en;
input		a_save_odd_en;

input  [1:0]	a_restore_tid;
input  [1:0]	a_restore_global_tid;
input  [1:0]	a_restore_global_addr;
input  [2:1]	a_restore_even_addr;
input  [2:1]	a_restore_odd_addr;
input  [2:0]	a_restore_local_addr;
input		a_restore_global_en;
input		a_restore_even_en;
input		a_restore_local_en;
input		a_restore_odd_en;


output [71:0]	a_rd_data_p0;
output [71:0]	a_rd_data_p1;
output [71:0]	a_rd_data_p2;


   reg [71:0]	active_window[127:0];		// Physical active array : 4(thread) x 32(reg) x 72 bit registers

   reg [71:0]	locals[255:0];			// Physical shadow array : 4(thread) x  8(reg) x 8(shadow)
   reg [71:0]	evens[127:0];			// Physical shadow array : 4(thread) x  8(reg) x 4(shadow)
   reg [71:0]	odds[127:0];			// Physical shadow array : 4(thread) x  8(reg) x 4(shadow)
   reg [71:0]	globals[127:0];			// Physical shadow array : 4(thread) x  8(reg) x 4(shadow)


   integer 	i;				// *** Temporary array      index (no physical flops involved) ***

   reg [71:0]	rd_data_p0;			// *** Temporary array read regs  (no physical flops involved) ***
   reg [71:0]	rd_data_p1;			// *** Temporary array read regs  (no physical flops involved) ***
   reg [71:0]	rd_data_p2;			// *** Temporary array read regs  (no physical flops involved) ***


// For Axis, make synthesizable by making all writes to active_window occur at negedge (normal write and restore)
// Reads of active occur at both edges (read and save)


   // -----------------------------------------------------------------------
   // *** initialization section ***
   // -----------------------------------------------------------------------

   initial begin
       active_window[0]  = {72{1'b0}};		// TID=0 G0 location is always ZERO - location is tied to ground, no memory cell at this address
       active_window[32] = {72{1'b0}};		// TID=1 G0 location is always ZERO - location is tied to ground, no memory cell at this address
       active_window[64] = {72{1'b0}};		// TID=2 G0 location is always ZERO - location is tied to ground, no memory cell at this address
       active_window[96] = {72{1'b0}};		// TID=3 G0 location is always ZERO - location is tied to ground, no memory cell at this address
   end


`ifndef NOINITMEM
   initial begin
     for (i=0; i<128; i=i+1) begin
       active_window[i] = {72{1'b0}};
       evens[i]         = {72{1'b0}};
       odds[i]          = {72{1'b0}};
       globals[i]       = {72{1'b0}};
       locals[i]        = {72{1'b0}};
       locals[i+128]    = {72{1'b0}};
     end
   end
`endif


// Concatenate the thread and index bits together

assign thr_rs1[6:0]	= {a_rd_tid[1:0]   , a_rd_addr_p0[4:0] };
assign thr_rs2[6:0]	= {a_rd_tid[1:0]   , a_rd_addr_p1[4:0] };
assign thr_rs3[6:0]	= {a_rd_tid[1:0]   , a_rd_addr_p2[4:0] };
assign thr_rd_w[6:0]	= {a_wr_tid_p0[1:0], a_wr_addr_p0[4:0] };
assign thr_rd_w2[6:0]	= {a_wr_tid_p1[1:0], a_wr_addr_p1[4:0] };


// Clear read enables if reading G0; clear write enables if writing G0;

assign rd_en_p0		= a_rd_en_p0 & (thr_rs1[4:0]   != 5'b00000) & ~tcu_array_wr_inhibit;
assign rd_en_p1		= a_rd_en_p1 & (thr_rs2[4:0]   != 5'b00000) & ~tcu_array_wr_inhibit;
assign rd_en_p2		= a_rd_en_p2 & (thr_rs3[4:0]   != 5'b00000) & ~tcu_array_wr_inhibit;

assign wr_en_p0		= a_wr_en_p0 & (thr_rd_w[4:0]  != 5'b00000) & ~tcu_array_wr_inhibit;
assign wr_en_p1		= a_wr_en_p1 & (thr_rd_w2[4:0] != 5'b00000) & ~tcu_array_wr_inhibit;

assign p0_rd_eq_wr	= (wr_en_p0 & (thr_rs1[6:0] == thr_rd_w[6:0])) | (wr_en_p1 & (thr_rs1[6:0] == thr_rd_w2[6:0]));
assign p1_rd_eq_wr	= (wr_en_p0 & (thr_rs2[6:0] == thr_rd_w[6:0])) | (wr_en_p1 & (thr_rs2[6:0] == thr_rd_w2[6:0]));
assign p2_rd_eq_wr	= (wr_en_p0 & (thr_rs3[6:0] == thr_rd_w[6:0])) | (wr_en_p1 & (thr_rs3[6:0] == thr_rd_w2[6:0]));


   always @ (clk or rd_en_p0 or rd_en_p1 or rd_en_p2 or thr_rs1 or thr_rs2 or thr_rs3 or p0_rd_eq_wr or p1_rd_eq_wr or p2_rd_eq_wr)

      begin

	if (clk)
	  begin 
	    if (rd_en_p0)
	      begin
	        if (p0_rd_eq_wr)	rd_data_p0[71:0] 	<= {72{1'bx}};
	        else			rd_data_p0[71:0]	<= active_window[thr_rs1[6:0]];
	      end
	    else			rd_data_p0[71:0] 	<= {72{1'b0}};


	    if (rd_en_p1)
	      begin
	        if (p1_rd_eq_wr)	rd_data_p1[71:0] 	<= {72{1'bx}};
	        else			rd_data_p1[71:0]	<= active_window[thr_rs2[6:0]];
	      end
	    else			rd_data_p1[71:0] 	<= {72{1'b0}};


	    if (rd_en_p2)
	      begin
	        if (p2_rd_eq_wr)	rd_data_p2[71:0] 	<= {72{1'bx}};
	        else			rd_data_p2[71:0]	<= active_window[thr_rs3[6:0]];
	      end
	    else			rd_data_p2[71:0] 	<= {72{1'b0}};

        end

      end		// ALWAYS CLK ...


   always @ (negedge clk)

      begin

	if (wr_en_p0)	active_window[thr_rd_w[6:0]]	<= a_wr_data_p0[71:0];

	if (wr_en_p1)	active_window[thr_rd_w2[6:0]]	<= a_wr_data_p1[71:0];


      end		// NEGEDGE ALWAYS


   /////////////////////////////////////////////
   // Globals
   //-----------------------------------
   // rml inputs are latched on rising edge
   // 1st cycle used for decode
   // 2nd cycle stores active window in phase 1
   // 3rd cycle loads new globals in phase 1
   /////////////////////////////////////////////

   ////////////////////////////
   // locals, ins and outs
   //-------------------------
   // E - set up inputs to flop
   // M - Decode
   // W  (phase 1) - Save
   // W  (phase 2) - write is allowed for save because restore will get killed
   // W2 (phase 1) - Restore
   // W2 (phase 2) - write is allowed
   //
   // actions that occur in phase one are modelled as occurring on the
   // rising edge
   //
   // swaps to the same thread in consecutive cycles not allowed
   /////////////////////////////


   // For synthesis, flop inputs again, then do write of active window on negedge...
   always @ (posedge clk) begin


       // *** *** *** *** *** *** *** *** *** SAVE *** *** *** *** *** *** *** *** ***


       if (a_save_global_en & ~tcu_array_wr_inhibit) begin		// save the globals (0-7 in active window)

          globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b000}]	<= active_window[{a_save_global_tid[1:0], 5'b00000}];
          globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b001}]	<= active_window[{a_save_global_tid[1:0], 5'b00001}];
          globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b010}]	<= active_window[{a_save_global_tid[1:0], 5'b00010}];
          globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b011}]	<= active_window[{a_save_global_tid[1:0], 5'b00011}];
          globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b100}]	<= active_window[{a_save_global_tid[1:0], 5'b00100}];
          globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b101}]	<= active_window[{a_save_global_tid[1:0], 5'b00101}];
          globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b110}]	<= active_window[{a_save_global_tid[1:0], 5'b00110}];
          globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b111}]	<= active_window[{a_save_global_tid[1:0], 5'b00111}];

       end


       if (a_save_odd_en & ~tcu_array_wr_inhibit) begin			// save the ins in odd window (8-15 in active window)

          odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b000}]			<= active_window[{a_save_tid[1:0], 5'b01000}];
          odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b001}]			<= active_window[{a_save_tid[1:0], 5'b01001}];
          odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b010}]			<= active_window[{a_save_tid[1:0], 5'b01010}];
          odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b011}]			<= active_window[{a_save_tid[1:0], 5'b01011}];
          odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b100}]			<= active_window[{a_save_tid[1:0], 5'b01100}];
          odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b101}]			<= active_window[{a_save_tid[1:0], 5'b01101}];
          odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b110}]			<= active_window[{a_save_tid[1:0], 5'b01110}];
          odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b111}]			<= active_window[{a_save_tid[1:0], 5'b01111}];

       end


       if (a_save_local_en & ~tcu_array_wr_inhibit) begin			// save the locals (16-23 in active window)

          locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b000}]		<= active_window[{a_save_tid[1:0], 5'b10000}];
          locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b001}]		<= active_window[{a_save_tid[1:0], 5'b10001}];
          locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b010}]		<= active_window[{a_save_tid[1:0], 5'b10010}];
          locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b011}]		<= active_window[{a_save_tid[1:0], 5'b10011}];
          locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b100}]		<= active_window[{a_save_tid[1:0], 5'b10100}];
          locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b101}]		<= active_window[{a_save_tid[1:0], 5'b10101}];
          locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b110}]		<= active_window[{a_save_tid[1:0], 5'b10110}];
          locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b111}]		<= active_window[{a_save_tid[1:0], 5'b10111}];

       end


       if (a_save_even_en & ~tcu_array_wr_inhibit) begin			// save the ins in even window (24-31 in active window)

          evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b000}]		<= active_window[{a_save_tid[1:0], 5'b11000}];
          evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b001}]		<= active_window[{a_save_tid[1:0], 5'b11001}];
          evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b010}]		<= active_window[{a_save_tid[1:0], 5'b11010}];
          evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b011}]		<= active_window[{a_save_tid[1:0], 5'b11011}];
          evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b100}]		<= active_window[{a_save_tid[1:0], 5'b11100}];
          evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b101}]		<= active_window[{a_save_tid[1:0], 5'b11101}];
          evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b110}]		<= active_window[{a_save_tid[1:0], 5'b11110}];
          evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b111}]		<= active_window[{a_save_tid[1:0], 5'b11111}];

       end


       // *** *** *** *** *** *** *** *** *** RESTORE *** *** *** *** *** *** *** *** ***


       if (a_restore_global_en & ~tcu_array_wr_inhibit) begin		// restore the globals (0-7 in active window)

          active_window[{a_restore_global_tid[1:0], 5'b00000}]			<= globals[{a_restore_global_tid[1:0], a_restore_global_addr[1:0], 3'b000}];
          active_window[{a_restore_global_tid[1:0], 5'b00001}]			<= globals[{a_restore_global_tid[1:0], a_restore_global_addr[1:0], 3'b001}];
          active_window[{a_restore_global_tid[1:0], 5'b00010}]			<= globals[{a_restore_global_tid[1:0], a_restore_global_addr[1:0], 3'b010}];
          active_window[{a_restore_global_tid[1:0], 5'b00011}]			<= globals[{a_restore_global_tid[1:0], a_restore_global_addr[1:0], 3'b011}];
          active_window[{a_restore_global_tid[1:0], 5'b00100}]			<= globals[{a_restore_global_tid[1:0], a_restore_global_addr[1:0], 3'b100}];
          active_window[{a_restore_global_tid[1:0], 5'b00101}]			<= globals[{a_restore_global_tid[1:0], a_restore_global_addr[1:0], 3'b101}];
          active_window[{a_restore_global_tid[1:0], 5'b00110}]			<= globals[{a_restore_global_tid[1:0], a_restore_global_addr[1:0], 3'b110}];
          active_window[{a_restore_global_tid[1:0], 5'b00111}]			<= globals[{a_restore_global_tid[1:0], a_restore_global_addr[1:0], 3'b111}];

       end


       if (a_restore_odd_en & ~tcu_array_wr_inhibit) begin			// restore the ins in odd window (8-15 in active window)

         active_window[{a_restore_tid[1:0], 5'b01000}]				<= odds[{a_restore_tid[1:0], a_restore_odd_addr[2:1], 3'b000}];
         active_window[{a_restore_tid[1:0], 5'b01001}]				<= odds[{a_restore_tid[1:0], a_restore_odd_addr[2:1], 3'b001}];
         active_window[{a_restore_tid[1:0], 5'b01010}]				<= odds[{a_restore_tid[1:0], a_restore_odd_addr[2:1], 3'b010}];
         active_window[{a_restore_tid[1:0], 5'b01011}]				<= odds[{a_restore_tid[1:0], a_restore_odd_addr[2:1], 3'b011}];
         active_window[{a_restore_tid[1:0], 5'b01100}]				<= odds[{a_restore_tid[1:0], a_restore_odd_addr[2:1], 3'b100}];
         active_window[{a_restore_tid[1:0], 5'b01101}]				<= odds[{a_restore_tid[1:0], a_restore_odd_addr[2:1], 3'b101}];
         active_window[{a_restore_tid[1:0], 5'b01110}]				<= odds[{a_restore_tid[1:0], a_restore_odd_addr[2:1], 3'b110}];
         active_window[{a_restore_tid[1:0], 5'b01111}]				<= odds[{a_restore_tid[1:0], a_restore_odd_addr[2:1], 3'b111}];

       end


       if (a_restore_local_en & ~tcu_array_wr_inhibit) begin			// restore the locals (16-23 in active window)

         active_window[{a_restore_tid[1:0], 5'b10000}]				<= locals[{a_restore_tid[1:0], a_restore_local_addr[2:0], 3'b000}];
         active_window[{a_restore_tid[1:0], 5'b10001}]				<= locals[{a_restore_tid[1:0], a_restore_local_addr[2:0], 3'b001}];
         active_window[{a_restore_tid[1:0], 5'b10010}]				<= locals[{a_restore_tid[1:0], a_restore_local_addr[2:0], 3'b010}];
         active_window[{a_restore_tid[1:0], 5'b10011}]				<= locals[{a_restore_tid[1:0], a_restore_local_addr[2:0], 3'b011}];
         active_window[{a_restore_tid[1:0], 5'b10100}]				<= locals[{a_restore_tid[1:0], a_restore_local_addr[2:0], 3'b100}];
         active_window[{a_restore_tid[1:0], 5'b10101}]				<= locals[{a_restore_tid[1:0], a_restore_local_addr[2:0], 3'b101}];
         active_window[{a_restore_tid[1:0], 5'b10110}]				<= locals[{a_restore_tid[1:0], a_restore_local_addr[2:0], 3'b110}];
         active_window[{a_restore_tid[1:0], 5'b10111}]				<= locals[{a_restore_tid[1:0], a_restore_local_addr[2:0], 3'b111}];

       end


       if (a_restore_even_en & ~tcu_array_wr_inhibit) begin			// restore the ins in even window (24-31 in active window)

         active_window[{a_restore_tid[1:0], 5'b11000}]				<= evens[{a_restore_tid[1:0], a_restore_even_addr[2:1], 3'b000}];
         active_window[{a_restore_tid[1:0], 5'b11001}]				<= evens[{a_restore_tid[1:0], a_restore_even_addr[2:1], 3'b001}];
         active_window[{a_restore_tid[1:0], 5'b11010}]				<= evens[{a_restore_tid[1:0], a_restore_even_addr[2:1], 3'b010}];
         active_window[{a_restore_tid[1:0], 5'b11011}]				<= evens[{a_restore_tid[1:0], a_restore_even_addr[2:1], 3'b011}];
         active_window[{a_restore_tid[1:0], 5'b11100}]				<= evens[{a_restore_tid[1:0], a_restore_even_addr[2:1], 3'b100}];
         active_window[{a_restore_tid[1:0], 5'b11101}]				<= evens[{a_restore_tid[1:0], a_restore_even_addr[2:1], 3'b101}];
         active_window[{a_restore_tid[1:0], 5'b11110}]				<= evens[{a_restore_tid[1:0], a_restore_even_addr[2:1], 3'b110}];
         active_window[{a_restore_tid[1:0], 5'b11111}]				<= evens[{a_restore_tid[1:0], a_restore_even_addr[2:1], 3'b111}];

       end


    end		// POSEDGE ALWAYS


assign a_rd_data_p0[71:0]	= rd_data_p0[71:0];
assign a_rd_data_p1[71:0]	= rd_data_p1[71:0];
assign a_rd_data_p2[71:0]	= rd_data_p2[71:0];


supply0 vss;
supply1 vdd;

endmodule
`endif // `ifndef FPGA


`ifdef FPGA

module exu_irf_array(clk, tcu_array_wr_inhibit, a_rd_en_p0, a_rd_en_p1, 
	a_rd_en_p2, a_rd_tid, a_rd_addr_p0, a_rd_addr_p1, a_rd_addr_p2, 
	a_wr_en_p0, a_wr_tid_p0, a_wr_addr_p0, a_wr_data_p0, a_wr_en_p1, 
	a_wr_tid_p1, a_wr_addr_p1, a_wr_data_p1, a_save_tid, a_save_global_tid, 
	a_save_global_addr, a_save_even_addr, a_save_local_addr, 
	a_save_odd_addr, a_save_global_en, a_save_even_en, a_save_local_en, 
	a_save_odd_en, a_restore_tid, a_restore_global_tid, 
	a_restore_global_addr, a_restore_even_addr, a_restore_odd_addr, 
	a_restore_local_addr, a_restore_global_en, a_restore_even_en, 
	a_restore_local_en, a_restore_odd_en, a_rd_data_p0, a_rd_data_p1, 
	a_rd_data_p2);

	input			clk;
	input			tcu_array_wr_inhibit;
	input			a_rd_en_p0;
	input			a_rd_en_p1;
	input			a_rd_en_p2;
	input	[1:0]		a_rd_tid;
	input	[4:0]		a_rd_addr_p0;
	input	[4:0]		a_rd_addr_p1;
	input	[4:0]		a_rd_addr_p2;
	input			a_wr_en_p0;
	input	[1:0]		a_wr_tid_p0;
	input	[4:0]		a_wr_addr_p0;
	input	[71:0]		a_wr_data_p0;
	input			a_wr_en_p1;
	input	[1:0]		a_wr_tid_p1;
	input	[4:0]		a_wr_addr_p1;
	input	[71:0]		a_wr_data_p1;
	input	[1:0]		a_save_tid;
	input	[1:0]		a_save_global_tid;
	input	[1:0]		a_save_global_addr;
	input	[2:1]		a_save_even_addr;
	input	[2:0]		a_save_local_addr;
	input	[2:1]		a_save_odd_addr;
	input			a_save_global_en;
	input			a_save_even_en;
	input			a_save_local_en;
	input			a_save_odd_en;
	input	[1:0]		a_restore_tid;
	input	[1:0]		a_restore_global_tid;
	input	[1:0]		a_restore_global_addr;
	input	[2:1]		a_restore_even_addr;
	input	[2:1]		a_restore_odd_addr;
	input	[2:0]		a_restore_local_addr;
	input			a_restore_global_en;
	input			a_restore_even_en;
	input			a_restore_local_en;
	input			a_restore_odd_en;
	output	[71:0]		a_rd_data_p0;
	output	[71:0]		a_rd_data_p1;
	output	[71:0]		a_rd_data_p2;

	wire	[6:0]		thr_rs1;
	wire	[6:0]		thr_rs2;
	wire	[6:0]		thr_rs3;
	wire	[6:0]		thr_rd_w;
	wire	[6:0]		thr_rd_w2;
	wire			rd_en_p0;
	wire			rd_en_p1;
	wire			rd_en_p2;
	wire			wr_en_p0;
	wire			wr_en_p1;
	wire			p0_rd_eq_wr;
	wire			p1_rd_eq_wr;
	wire			p2_rd_eq_wr;

        reg     [71:0]          active_window[127:0];
        reg     [71:0]          locals[255:0];
        reg     [71:0]          evens[127:0];
        reg     [71:0]          odds[127:0];
        reg     [71:0]          globals[127:0];
	integer			i;
	reg	[71:0]		rd_data_p0;
	reg	[71:0]		rd_data_p1;
	reg	[71:0]		rd_data_p2;
	reg	[1:0]		a_restore_global_tid_d1;
	reg	[1:0]		a_restore_tid_d1;
	reg	[1:0]		a_restore_global_addr_d1;
	reg	[2:1]		a_restore_odd_addr_d1;
	reg	[2:1]		a_restore_even_addr_d1;
	reg	[2:0]		a_restore_local_addr_d1;
	reg			a_save_global_en_d1;
	reg			tcu_array_wr_inhibit_d1;
	reg			a_save_odd_en_d1;
	reg			a_save_local_en_d1;
	reg			a_save_even_en_d1;
	reg			a_restore_global_en_d1;
	reg			a_restore_odd_en_d1;
	reg			a_restore_local_en_d1;
	reg			a_restore_even_en_d1;
	supply0			vss;
	supply1			vdd;


        assign thr_rs1[6:0] = {a_rd_tid[1:0], a_rd_addr_p0[4:0]};
        assign thr_rs2[6:0] = {a_rd_tid[1:0], a_rd_addr_p1[4:0]};
        assign thr_rs3[6:0] = {a_rd_tid[1:0], a_rd_addr_p2[4:0]};
        assign thr_rd_w[6:0] = {a_wr_tid_p0[1:0], a_wr_addr_p0[4:0]};
        assign thr_rd_w2[6:0] = {a_wr_tid_p1[1:0], a_wr_addr_p1[4:0]};


	assign rd_en_p0 = ((a_rd_en_p0 & (thr_rs1[4:0] != 5'b0)) & (~
		tcu_array_wr_inhibit));
	assign rd_en_p1 = ((a_rd_en_p1 & (thr_rs2[4:0] != 5'b0)) & (~
		tcu_array_wr_inhibit));
	assign rd_en_p2 = ((a_rd_en_p2 & (thr_rs3[4:0] != 5'b0)) & (~
		tcu_array_wr_inhibit));
	assign wr_en_p0 = ((a_wr_en_p0 & (thr_rd_w[4:0] != 5'b0)) & (~
		tcu_array_wr_inhibit));
	assign wr_en_p1 = ((a_wr_en_p1 & (thr_rd_w2[4:0] != 5'b0)) & (~
		tcu_array_wr_inhibit));
	assign p0_rd_eq_wr = ((wr_en_p0 & (thr_rs1[6:0] == thr_rd_w[6:0])) | (
		wr_en_p1 & (thr_rs1[6:0] == thr_rd_w2[6:0])));
	assign p1_rd_eq_wr = ((wr_en_p0 & (thr_rs2[6:0] == thr_rd_w[6:0])) | (
		wr_en_p1 & (thr_rs2[6:0] == thr_rd_w2[6:0])));
	assign p2_rd_eq_wr = ((wr_en_p0 & (thr_rs3[6:0] == thr_rd_w[6:0])) | (
		wr_en_p1 & (thr_rs3[6:0] == thr_rd_w2[6:0])));
	assign a_rd_data_p0[71:0] = rd_data_p0[71:0];
	assign a_rd_data_p1[71:0] = rd_data_p1[71:0];
	assign a_rd_data_p2[71:0] = rd_data_p2[71:0];

	initial begin
	  active_window[0] = {72 {1'b0}};
	  active_window[32] = {72 {1'b0}};
	  active_window[64] = {72 {1'b0}};
	  active_window[96] = {72 {1'b0}};
	end
	initial begin
	  for (i = 0; (i < 128); i = (i + 1)) begin
	    active_window[i] = {72 {1'b0}};
	    evens[i] = {72 {1'b0}};
	    odds[i] = {72 {1'b0}};
	    globals[i] = {72 {1'b0}};
	    locals[i] = {72 {1'b0}};
	    locals[(i + 128)] = {72 {1'b0}};
	  end
	end
	always @(clk or rd_en_p0 or rd_en_p1 or rd_en_p2 or thr_rs1 or thr_rs2
		or thr_rs3 or p0_rd_eq_wr or p1_rd_eq_wr or p2_rd_eq_wr) begin
	  if (clk) begin
	    if (rd_en_p0) begin
	      if (p0_rd_eq_wr) begin
		rd_data_p0[71:0] <= {72 {1'bx}};
	      end
	      else begin
		rd_data_p0[71:0] <= active_window[thr_rs1[6:0]];
	      end
	    end
	    else begin
	      rd_data_p0[71:0] <= {72 {1'b0}};
	    end
	    if (rd_en_p1) begin
	      if (p1_rd_eq_wr) begin
		rd_data_p1[71:0] <= {72 {1'bx}};
	      end
	      else begin
		rd_data_p1[71:0] <= active_window[thr_rs2[6:0]];
	      end
	    end
	    else begin
	      rd_data_p1[71:0] <= {72 {1'b0}};
	    end
	    if (rd_en_p2) begin
	      if (p2_rd_eq_wr) begin
		rd_data_p2[71:0] <= {72 {1'bx}};
	      end
	      else begin
		rd_data_p2[71:0] <= active_window[thr_rs3[6:0]];
	      end
	    end
	    else begin
	      rd_data_p2[71:0] <= {72 {1'b0}};
	    end
	  end
	end
	always @(negedge clk) begin
	  if (wr_en_p0) begin
	    active_window[thr_rd_w[6:0]] <= a_wr_data_p0[71:0];
	  end
	  if (wr_en_p1) begin
	    active_window[thr_rd_w2[6:0]] <= a_wr_data_p1[71:0];
	  end
	  if (a_restore_global_en_d1 & (~tcu_array_wr_inhibit_d1)) begin
	    active_window[{a_restore_global_tid_d1[1:0], 5'b0}] <= 
		    globals[{a_restore_global_tid_d1[1:0],
		    a_restore_global_addr_d1[1:0], 3'b0}];
	    active_window[{a_restore_global_tid_d1[1:0], 5'b1}] <= 
		    globals[{a_restore_global_tid_d1[1:0],
		    a_restore_global_addr_d1[1:0], 3'b1}];
	    active_window[{a_restore_global_tid_d1[1:0], 5'b00010}] <= 
		    globals[{a_restore_global_tid_d1[1:0],
		    a_restore_global_addr_d1[1:0], 3'd2}];
	    active_window[{a_restore_global_tid_d1[1:0], 5'b00011}] <= 
		    globals[{a_restore_global_tid_d1[1:0],
		    a_restore_global_addr_d1[1:0], 3'd3}];
	    active_window[{a_restore_global_tid_d1[1:0], 5'b00100}] <= 
		    globals[{a_restore_global_tid_d1[1:0],
		    a_restore_global_addr_d1[1:0], 3'd4}];
	    active_window[{a_restore_global_tid_d1[1:0], 5'b00101}] <= 
		    globals[{a_restore_global_tid_d1[1:0],
		    a_restore_global_addr_d1[1:0], 3'd5}];
	    active_window[{a_restore_global_tid_d1[1:0], 5'b00110}] <= 
		    globals[{a_restore_global_tid_d1[1:0],
		    a_restore_global_addr_d1[1:0], 3'd6}];
	    active_window[{a_restore_global_tid_d1[1:0], 5'b00111}] <= 
		    globals[{a_restore_global_tid_d1[1:0],
		    a_restore_global_addr_d1[1:0], 3'd7}];
	  end
	  if (a_restore_odd_en_d1 & (~tcu_array_wr_inhibit_d1)) begin
	    active_window[{a_restore_tid_d1[1:0], 5'b01000}] <= 
		    odds[{a_restore_tid_d1[1:0], a_restore_odd_addr_d1[2:1],
		    3'b0}];
	    active_window[{a_restore_tid_d1[1:0], 5'b01001}] <= 
		    odds[{a_restore_tid_d1[1:0], a_restore_odd_addr_d1[2:1],
		    3'b1}];
	    active_window[{a_restore_tid_d1[1:0], 5'b01010}] <= 
		    odds[{a_restore_tid_d1[1:0], a_restore_odd_addr_d1[2:1],
		    3'd2}];
	    active_window[{a_restore_tid_d1[1:0], 5'b01011}] <= 
		    odds[{a_restore_tid_d1[1:0], a_restore_odd_addr_d1[2:1],
		    3'd3}];
	    active_window[{a_restore_tid_d1[1:0], 5'b01100}] <= 
		    odds[{a_restore_tid_d1[1:0], a_restore_odd_addr_d1[2:1],
		    3'd4}];
	    active_window[{a_restore_tid_d1[1:0], 5'b01101}] <= 
		    odds[{a_restore_tid_d1[1:0], a_restore_odd_addr_d1[2:1],
		    3'd5}];
	    active_window[{a_restore_tid_d1[1:0], 5'b01110}] <= 
		    odds[{a_restore_tid_d1[1:0], a_restore_odd_addr_d1[2:1],
		    3'd6}];
	    active_window[{a_restore_tid_d1[1:0], 5'b01111}] <= 
		    odds[{a_restore_tid_d1[1:0], a_restore_odd_addr_d1[2:1],
		    3'd7}];
	  end
	  if (a_restore_local_en_d1 & (~tcu_array_wr_inhibit_d1)) begin
	    active_window[{a_restore_tid_d1[1:0], 5'b10000}] <= 
		    locals[{a_restore_tid_d1[1:0], a_restore_local_addr_d1[2:0],
		    3'b0}];
	    active_window[{a_restore_tid_d1[1:0], 5'b10001}] <= 
		    locals[{a_restore_tid_d1[1:0], a_restore_local_addr_d1[2:0],
		    3'b1}];
	    active_window[{a_restore_tid_d1[1:0], 5'b10010}] <= 
		    locals[{a_restore_tid_d1[1:0], a_restore_local_addr_d1[2:0],
		    3'd2}];
	    active_window[{a_restore_tid_d1[1:0], 5'b10011}] <= 
		    locals[{a_restore_tid_d1[1:0], a_restore_local_addr_d1[2:0],
		    3'd3}];
	    active_window[{a_restore_tid_d1[1:0], 5'b10100}] <= 
		    locals[{a_restore_tid_d1[1:0], a_restore_local_addr_d1[2:0],
		    3'd4}];
	    active_window[{a_restore_tid_d1[1:0], 5'b10101}] <= 
		    locals[{a_restore_tid_d1[1:0], a_restore_local_addr_d1[2:0],
		    3'd5}];
	    active_window[{a_restore_tid_d1[1:0], 5'b10110}] <= 
		    locals[{a_restore_tid_d1[1:0], a_restore_local_addr_d1[2:0],
		    3'd6}];
	    active_window[{a_restore_tid_d1[1:0], 5'b10111}] <= 
		    locals[{a_restore_tid_d1[1:0], a_restore_local_addr_d1[2:0],
		    3'd7}];
	  end
	  if (a_restore_even_en_d1 & (~tcu_array_wr_inhibit_d1)) begin
	    active_window[{a_restore_tid_d1[1:0], 5'b11000}] <= 
		    evens[{a_restore_tid_d1[1:0], a_restore_even_addr_d1[2:1],
		    3'b0}];
	    active_window[{a_restore_tid_d1[1:0], 5'b11001}] <= 
		    evens[{a_restore_tid_d1[1:0], a_restore_even_addr_d1[2:1],
		    3'b1}];
	    active_window[{a_restore_tid_d1[1:0], 5'b11010}] <= 
		    evens[{a_restore_tid_d1[1:0], a_restore_even_addr_d1[2:1],
		    3'd2}];
	    active_window[{a_restore_tid_d1[1:0], 5'b11011}] <= 
		    evens[{a_restore_tid_d1[1:0], a_restore_even_addr_d1[2:1],
		    3'd3}];
	    active_window[{a_restore_tid_d1[1:0], 5'b11100}] <= 
		    evens[{a_restore_tid_d1[1:0], a_restore_even_addr_d1[2:1],
		    3'd4}];
	    active_window[{a_restore_tid_d1[1:0], 5'b11101}] <= 
		    evens[{a_restore_tid_d1[1:0], a_restore_even_addr_d1[2:1],
		    3'd5}];
	    active_window[{a_restore_tid_d1[1:0], 5'b11110}] <= 
		    evens[{a_restore_tid_d1[1:0], a_restore_even_addr_d1[2:1],
		    3'd6}];
	    active_window[{a_restore_tid_d1[1:0], 5'b11111}] <= 
		    evens[{a_restore_tid_d1[1:0], a_restore_even_addr_d1[2:1],
		    3'd7}];
	  end
	end
	always @(posedge clk) begin
	  tcu_array_wr_inhibit_d1 <= tcu_array_wr_inhibit;
	  a_restore_global_tid_d1[1:0] <= a_restore_global_tid[1:0];
	  a_restore_global_addr_d1[1:0] <= a_restore_global_addr[1:0];
	  a_restore_tid_d1[1:0] <= a_restore_tid[1:0];
	  a_restore_odd_addr_d1[2:1] <= a_restore_odd_addr[2:1];
	  a_restore_local_addr_d1[2:0] <= a_restore_local_addr[2:0];
	  a_restore_even_addr_d1[2:1] <= a_restore_even_addr[2:1];
	  a_restore_global_en_d1 <= a_restore_global_en;
	  a_restore_odd_en_d1 <= a_restore_odd_en;
	  a_restore_local_en_d1 <= a_restore_local_en;
	  a_restore_even_en_d1 <= a_restore_even_en;
	  if (a_save_global_en & (~tcu_array_wr_inhibit)) begin
	    globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b0}] <= 
		    active_window[{a_save_global_tid[1:0], 5'b0}];
	    globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'b1}] <= 
		    active_window[{a_save_global_tid[1:0], 5'b1}];
	    globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'd2}] <= 
		    active_window[{a_save_global_tid[1:0], 5'b00010}];
	    globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'd3}] <= 
		    active_window[{a_save_global_tid[1:0], 5'b00011}];
	    globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'd4}] <= 
		    active_window[{a_save_global_tid[1:0], 5'b00100}];
	    globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'd5}] <= 
		    active_window[{a_save_global_tid[1:0], 5'b00101}];
	    globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'd6}] <= 
		    active_window[{a_save_global_tid[1:0], 5'b00110}];
	    globals[{a_save_global_tid[1:0], a_save_global_addr[1:0], 3'd7}] <= 
		    active_window[{a_save_global_tid[1:0], 5'b00111}];
	  end
	  if (a_save_odd_en & (~tcu_array_wr_inhibit)) begin
	    odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b0}] <= 
		    active_window[{a_save_tid[1:0], 5'b01000}];
	    odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'b1}] <= 
		    active_window[{a_save_tid[1:0], 5'b01001}];
	    odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'd2}] <= 
		    active_window[{a_save_tid[1:0], 5'b01010}];
	    odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'd3}] <= 
		    active_window[{a_save_tid[1:0], 5'b01011}];
	    odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'd4}] <= 
		    active_window[{a_save_tid[1:0], 5'b01100}];
	    odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'd5}] <= 
		    active_window[{a_save_tid[1:0], 5'b01101}];
	    odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'd6}] <= 
		    active_window[{a_save_tid[1:0], 5'b01110}];
	    odds[{a_save_tid[1:0], a_save_odd_addr[2:1], 3'd7}] <= 
		    active_window[{a_save_tid[1:0], 5'b01111}];
	  end
	  if (a_save_local_en & (~tcu_array_wr_inhibit)) begin
	    locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b0}] <= 
		    active_window[{a_save_tid[1:0], 5'b10000}];
	    locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'b1}] <= 
		    active_window[{a_save_tid[1:0], 5'b10001}];
	    locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'd2}] <= 
		    active_window[{a_save_tid[1:0], 5'b10010}];
	    locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'd3}] <= 
		    active_window[{a_save_tid[1:0], 5'b10011}];
	    locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'd4}] <= 
		    active_window[{a_save_tid[1:0], 5'b10100}];
	    locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'd5}] <= 
		    active_window[{a_save_tid[1:0], 5'b10101}];
	    locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'd6}] <= 
		    active_window[{a_save_tid[1:0], 5'b10110}];
	    locals[{a_save_tid[1:0], a_save_local_addr[2:0], 3'd7}] <= 
		    active_window[{a_save_tid[1:0], 5'b10111}];
	  end
	  if (a_save_even_en & (~tcu_array_wr_inhibit)) begin
	    evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b0}] <= 
		    active_window[{a_save_tid[1:0], 5'b11000}];
	    evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'b1}] <= 
		    active_window[{a_save_tid[1:0], 5'b11001}];
	    evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'd2}] <= 
		    active_window[{a_save_tid[1:0], 5'b11010}];
	    evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'd3}] <= 
		    active_window[{a_save_tid[1:0], 5'b11011}];
	    evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'd4}] <= 
		    active_window[{a_save_tid[1:0], 5'b11100}];
	    evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'd5}] <= 
		    active_window[{a_save_tid[1:0], 5'b11101}];
	    evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'd6}] <= 
		    active_window[{a_save_tid[1:0], 5'b11110}];
	    evens[{a_save_tid[1:0], a_save_even_addr[2:1], 3'd7}] <= 
		    active_window[{a_save_tid[1:0], 5'b11111}];
	  end
	end

endmodule

`endif // `ifdef FPGA

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_tlb_tl_128x59_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_tlb_tl_128x59_cust (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  pce, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  tcu_array_wr_inhibit, 
  tcu_scan_en, 
  disable_clear_ubit, 
  scan_out, 
  tlb_bypass, 
  tlb_wr_vld, 
  tlb_rd_vld, 
  tlb_cam_vld, 
  tlb_rw_index, 
  tlb_rw_index_vld, 
  tlb_demap, 
  tlb_demap_context, 
  tlb_demap_all, 
  tlb_demap_real, 
  tte_tag, 
  tte_ubit, 
  tte_page_size_mask, 
  tte_data, 
  tlb_va, 
  cache_ptag_w0, 
  cache_ptag_w1, 
  cache_ptag_w2, 
  cache_ptag_w3, 
  cache_set_vld, 
  cache_way_hit, 
  cache_hit, 
  tlb_cam_hit, 
  tlb_cam_mhit, 
  tlb_context0_hit, 
  tlb_pgnum_crit, 
  tlb_pgnum, 
  tlb_tte_data, 
  tlb_tte_tag, 
  tlb_tte_u_bit, 
  tlb_tte_data_parity) ;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk_in;
wire l1clk_free;
wire [73:0] cam_ctl_lat_scanin;
wire [73:0] cam_ctl_lat_scanout;
wire [65:0] tte_tag_1;
wire tte_ubit_1;
wire tlb_wr_1_in_unused;
wire tlb_rd_1_unused;
wire tlb_cam_1_in;
wire demap_1_in;
wire demap_context_1;
wire demap_all_1;
wire demap_real_1;
wire [73:0] lat_l_unused;
wire [65:0] tte_tag_1_dout;
wire tte_ubit_1_unused;
wire tlb_wr_1_in_dout;
wire tlb_rd_1_in_dout;
wire tlb_cam_1_in_dout;
wire demap_1_in_unused;
wire demap_context_1_unused;
wire demap_all_1_unused;
wire demap_real_1_unused;
wire [73:0] dout_l_unused;
wire demap_page_1_unused;
wire wr_inhibit_;
wire tlb_wr_1_dout;
wire tlb_rd_1_dout;
wire tlb_cam_1;
wire tlb_cam_1_dout;
wire demap_1;
wire [2:0] page_size_mask_reg_scanin;
wire [2:0] page_size_mask_reg_scanout;
wire [2:0] tte_page_size_mask_1;
wire disable_clear_ubit_reg_scanin;
wire disable_clear_ubit_reg_scanout;
wire disable_clear_ubit_1_in;
wire disable_clear_ubit_1;
wire tlb_bypass_reg_scanin;
wire tlb_bypass_reg_scanout;
wire tlb_bypass_1;
wire [1:0] vaddr_reg_scanin;
wire [1:0] vaddr_reg_scanout;
wire [12:11] va_1;
wire [37:0] tte_data_reg_scanin;
wire [37:0] tte_data_reg_scanout;
wire [37:0] tte_data_1;
wire [6:0] tlb_replacement_index;
wire [6:0] rw_index_0;
wire [6:0] rw_index_reg_scanin;
wire [6:0] rw_index_reg_scanout;
wire [6:0] rw_index_1;
wire rw_index_vld_reg_scanin;
wire rw_index_vld_reg_scanout;
wire rw_index_vld_unused;
wire [39:11] pa_1;
wire tlb_cam_hit_1;
wire l1clk_out;
wire [2:0] tlb_cam_hit_reg_scanin;
wire [2:0] tlb_cam_hit_reg_scanout;
wire multiple_match;
wire context0_hit;
wire tlb_cam_mhit_b;
wire [39:13] pa_1_b;
wire [26:0] pa_reg_scanin;
wire [26:0] pa_reg_scanout;
wire [39:13] pa_2_b;
wire [39:13] pa_2;
wire [37:0] tte_data_out_reg_scanin;
wire [37:0] tte_data_out_reg_scanout;
wire [37:0] rd_tte_data;
wire [65:0] rd_tte_tag;
wire [65:0] rd_tte_tag_b;
wire [65:0] tte_tag_out_reg_scanin;
wire [65:0] tte_tag_out_reg_scanout;
wire [65:0] tlb_tte_tag_b;
wire rd_tte_u_bit;
wire rd_tte_u_bit_b;
wire tte_u_bit_out_reg_scanin;
wire tte_u_bit_out_reg_scanout;
wire tlb_tte_u_bit_b;
wire [3:0] cache_way_hit_in;
wire [3:0] cache_way_hit_in_b;
wire [3:0] cache_way_hit_reg_scanin;
wire [3:0] cache_way_hit_reg_scanout;
wire [3:0] cache_way_hit_b;
wire data_parity_0;
wire [3:0] mm_debug_reg_scanin;
wire [3:0] mm_debug_reg_scanout;
wire [3:0] mm_debug;
wire tag_read_mux_control;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input 		pce;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_se_scancollar_in;
input		tcu_se_scancollar_out;
input		tcu_array_wr_inhibit;
input		tcu_scan_en;
input		disable_clear_ubit;
output		scan_out;

input		tlb_bypass;	// DO NOT CHANGE THIS NAME - IT'S USED BY THE BENCH
input		tlb_wr_vld;
input		tlb_rd_vld;
input		tlb_cam_vld;	// DO NOT CHANGE THIS NAME - IT'S USED BY THE BENCH
input	[6:0]	tlb_rw_index;
input		tlb_rw_index_vld;
input		tlb_demap;
input		tlb_demap_context;
input		tlb_demap_all;
input		tlb_demap_real;

input	[65:0]	tte_tag;
input		tte_ubit;
input	[2:0]	tte_page_size_mask;
input	[37:0]	tte_data;
input	[12:11]	tlb_va;		// Incoming VA

// Cache tag compare
input	[39:11]	cache_ptag_w0;
input	[39:11]	cache_ptag_w1;
input	[39:11]	cache_ptag_w2;
input	[39:11]	cache_ptag_w3;
//
//
//
//
input	[3:0]	cache_set_vld;

output	[3:0]	cache_way_hit;
output		cache_hit;
output		tlb_cam_hit;
output		tlb_cam_mhit;
output		tlb_context0_hit;
output	[39:13]	tlb_pgnum_crit; 	// PA unflopped
output	[39:13]	tlb_pgnum;	 	// PA flopped
output	[37:0]	tlb_tte_data;
output	[65:0]	tlb_tte_tag;
output		tlb_tte_u_bit;
output		tlb_tte_data_parity;

`ifndef FPGA
// synopsys translate_off
`endif

assign pce_ov = tcu_pce_ov;
assign stop   = 1'b0;
assign siclk  = tcu_aclk ;
assign soclk  = tcu_bclk;
assign se     = tcu_scan_en;


// 0in bits_on -var {tlb_wr_vld,tlb_rd_vld,tlb_cam_vld,tlb_demap} -max 1
// 0in bits_on -var {tlb_demap_context,tlb_demap_all,tlb_demap_real} -max 1
// 0in bits_on -var {tlb_cam_vld,tlb_bypass} -max 1
// 0in assert -var (~(tlb_demap_context & ~tlb_demap)) -message "Cannot asert tlb_demap_context without tlb_demap"
// 0in assert -var (~(tlb_demap_all     & ~tlb_demap)) -message "Cannot asert tlb_demap_all     without tlb_demap"
// 0in assert -var (~(tlb_demap_real    & ~tlb_demap)) -message "Cannot asert tlb_demap_real    without tlb_demap"
// 0in known_driven -var tlb_cam_hit


///////////////////////////////////////////////////////////////
// Input flops
///////////////////////////////////////////////////////////////

n2_tlb_tl_128x59_cust_l1clkhdr_ctl_macro in_clken (
 .l2clk(l2clk),
 .l1en(pce),
 .se(tcu_se_scancollar_in),
 .l1clk(l1clk_in),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_tlb_tl_128x59_cust_l1clkhdr_ctl_macro free_clken (
 .l2clk(l2clk),
 .l1en(pce),
 .se(se),
 .l1clk(l1clk_free),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Put all the CAM controls and data in one latch to avoid races
// Doesn't really matter any more... also this gets split up in 
// gate level model
n2_tlb_tl_128x59_cust_sram_msff_mo_macro__fs_1__width_74 cam_ctl_lat   (
 .scan_in(cam_ctl_lat_scanin[73:0]),
 .scan_out(cam_ctl_lat_scanout[73:0]),
 .l1clk	(l1clk_in),
 .and_clk(l1clk_free),
//	            73:8      7        6
 .d	({tte_tag  [65:0],tte_ubit  ,tlb_wr_vld ,
//               5      4             3         2
	  tlb_rd_vld,tlb_cam_vld ,tlb_demap ,tlb_demap_context,
//	         1          0
	  tlb_demap_all,tlb_demap_real}),
 .mq	({tte_tag_1[65:0],tte_ubit_1,tlb_wr_1_in_unused,
	  tlb_rd_1_unused ,tlb_cam_1_in,demap_1_in,demap_context_1  ,
	  demap_all_1  ,demap_real_1  }),
 .mq_l	(lat_l_unused[73:0]),
// NOTE:  Some signals on dout port ARE used by bench (dtlb_wr.v)!
 .q	({tte_tag_1_dout[65:0],tte_ubit_1_unused,tlb_wr_1_in_dout,
	  tlb_rd_1_in_dout,tlb_cam_1_in_dout,demap_1_in_unused,demap_context_1_unused  ,
	  demap_all_1_unused  ,demap_real_1_unused  }),
 .q_l	(dout_l_unused[73:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// This is strictly for DV
assign demap_page_1_unused =
       demap_1_in_unused & ~demap_context_1_unused & ~demap_all_1_unused & 
       ~demap_real_1_unused;

n2_tlb_tl_128x59_cust_inv_macro__width_1 wr_inhibit_b_inv  (
 .din(tcu_array_wr_inhibit),
 .dout(wr_inhibit_)
);				  

n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 tlb_wr_dout_and   (
 .din0(tlb_wr_1_in_dout),
 .din1(wr_inhibit_),
 .dout(tlb_wr_1_dout)
);				  

n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 tlb_rd_dout_and   (
 .din0(tlb_rd_1_in_dout),
 .din1(wr_inhibit_),
 .dout(tlb_rd_1_dout)
);				  

n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 tlb_cam_and   (
 .din0(tlb_cam_1_in),
 .din1(wr_inhibit_),
 .dout(tlb_cam_1)
);				  

n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 tlb_cam_dout_and   (
 .din0(tlb_cam_1_in_dout),
 .din1(wr_inhibit_),
 .dout(tlb_cam_1_dout)
);				  

n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 demap_and   (
 .din0(demap_1_in),
 .din1(wr_inhibit_),
 .dout(demap_1)
);				  

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_3 page_size_mask_reg   (
 .scan_in(page_size_mask_reg_scanin[2:0]),
 .scan_out(page_size_mask_reg_scanout[2:0]),
 .l1clk(l1clk_in),
 .din(tte_page_size_mask[2:0]),
 .dout(tte_page_size_mask_1[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 disable_clear_ubit_reg  (
 .scan_in(disable_clear_ubit_reg_scanin),
 .scan_out(disable_clear_ubit_reg_scanout),
 .l1clk(l1clk_in),
 .din(disable_clear_ubit),
 .dout(disable_clear_ubit_1_in),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 disable_clear_ubit_and   (
 .din0(disable_clear_ubit_1_in),
 .din1(wr_inhibit_),
 .dout(disable_clear_ubit_1)
);				  

n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 tlb_bypass_reg  (
 .scan_in(tlb_bypass_reg_scanin),
 .scan_out(tlb_bypass_reg_scanout),
 .l1clk(l1clk_in),
 .din(tlb_bypass),
 .dout(tlb_bypass_1),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_2 vaddr_reg   (
 .scan_in(vaddr_reg_scanin[1:0]),
 .scan_out(vaddr_reg_scanout[1:0]),
 .l1clk(l1clk_in),
 .din(tlb_va[12:11]),
 .dout(va_1[12:11]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_38 tte_data_reg   (
 .scan_in(tte_data_reg_scanin[37:0]),
 .scan_out(tte_data_reg_scanout[37:0]),
 .l1clk(l1clk_in),
 .din(tte_data[37:0]),
 .dout(tte_data_1[37:0]),
  .siclk(siclk),
  .soclk(soclk)
);


/////////////////////////////////////////////////////////////////////      
// Write index muxing
//////////////////////////////////////////////////////////////////////

n2_tlb_tl_128x59_cust_mux_macro__mux_aope__ports_2__width_7 rw_index_mux    (
	.din0	(tlb_rw_index[6:0]),
	.din1	(tlb_replacement_index[6:0]),
	.sel0	(tlb_rw_index_vld),
	.dout	(rw_index_0[6:0])	
);

// The output of this flop is used by the bench (dtlb_wr.vpal)
n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_7 rw_index_reg   (
 .scan_in(rw_index_reg_scanin[6:0]),
 .scan_out(rw_index_reg_scanout[6:0]),
 .l1clk(l1clk_in),
 .din(rw_index_0[6:0]),
 .dout(rw_index_1[6:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// This flop is here to mirror the circuit; it has no functional purpose;
// Just want it here for 'debug' even though this signal
// is flopped outside the circuit
n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 rw_index_vld_reg  (
 .scan_in(rw_index_vld_reg_scanin),
 .scan_out(rw_index_vld_reg_scanout),
 .l1clk(l1clk_in),
 .din(tlb_rw_index_vld),
 .dout(rw_index_vld_unused),
  .siclk(siclk),
  .soclk(soclk)
);


/////////////////////////////////////////////////////////////////////      
// Array behavioral
//////////////////////////////////////////////////////////////////////

n2_tlb_tl_128x59_array array (
// Inputs
	.l1clk		(l1clk_free),
	.tlb_bypass	(tlb_bypass_1),
	.tlb_wr_flopped	(tlb_wr_1_dout),
	.tlb_rd_flopped	(tlb_rd_1_dout),
	.rw_index	(rw_index_1[6:0]),
	.tlb_cam	(tlb_cam_1),
	.tlb_cam_flopped(tlb_cam_1_dout),
	.disable_clear_ubit(disable_clear_ubit_1),
	.demap		(demap_1),
	.demap_context	(demap_context_1),
	.demap_all	(demap_all_1),
	.demap_real	(demap_real_1),
	.tte_tag	(tte_tag_1[65:0]),
	.tte_tag_flopped(tte_tag_1_dout[65:0]),
	.tte_ubit	(tte_ubit_1),
	.tte_page_size_mask(tte_page_size_mask_1[2:0]),
	.tte_data	(tte_data_1[37:0]),
	.va		(va_1[12:11]),
// Outputs
	.pa		(pa_1[39:11]),
	.tlb_cam_hit	(tlb_cam_hit_1),
  .tag_read_mux_control(tag_read_mux_control),
  .context0_hit(context0_hit),
  .multiple_match(multiple_match),
  .rd_tte_data(rd_tte_data[37:0]),
  .rd_tte_tag(rd_tte_tag[65:0]),
  .rd_tte_u_bit(rd_tte_u_bit),
  .tlb_replacement_index(tlb_replacement_index[6:0])
);

// Unflopped output
assign tlb_pgnum_crit[39:13] = pa_1[39:13];

//////////////////////////////////////////////////
// Flop the output data
//////////////////////////////////////////////////

n2_tlb_tl_128x59_cust_l1clkhdr_ctl_macro out_clken (
 .l2clk(l2clk),
 .l1en(pce),
 .se(tcu_se_scancollar_out),
 .l1clk(l1clk_out),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_3 tlb_cam_hit_reg   (
 .scan_in(tlb_cam_hit_reg_scanin[2:0]),
 .scan_out(tlb_cam_hit_reg_scanout[2:0]),
 .l1clk(l1clk_out),
 .din({tlb_cam_hit_1,multiple_match,context0_hit}),
 .dout({tlb_cam_hit,tlb_cam_mhit,tlb_context0_hit}),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_inv_macro__width_1 tlb_cam_mhit_b_inv  (
 .din(tlb_cam_mhit),
 .dout(tlb_cam_mhit_b)
);					

n2_tlb_tl_128x59_cust_inv_macro__width_27 pa_1_b_inv  (
 .din(pa_1[39:13]),
 .dout(pa_1_b[39:13])
);					

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_27 pa_reg   (
 .scan_in(pa_reg_scanin[26:0]),
 .scan_out(pa_reg_scanout[26:0]),
 .l1clk(l1clk_out),
 .din(pa_1_b[39:13]),
 .dout(pa_2_b[39:13]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_inv_macro__width_27 pa_2_inv  (
 .din(pa_2_b[39:13]),
 .dout(pa_2[39:13])
);					

assign tlb_pgnum[39:13] = pa_2[39:13];

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_38 tte_data_out_reg   (
 .scan_in(tte_data_out_reg_scanin[37:0]),
 .scan_out(tte_data_out_reg_scanout[37:0]),
 .l1clk(l1clk_out),
 .din(rd_tte_data[37:0]),
 .dout(tlb_tte_data[37:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_inv_macro__stack_66c__width_66 rd_tte_tag_b_inv   (
 .din(rd_tte_tag[65:0]),
 .dout(rd_tte_tag_b[65:0])
);					

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_66 tte_tag_out_reg   (
 .scan_in(tte_tag_out_reg_scanin[65:0]),
 .scan_out(tte_tag_out_reg_scanout[65:0]),
 .l1clk(l1clk_out),
 .din(rd_tte_tag_b[65:0]),
 .dout(tlb_tte_tag_b[65:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_inv_macro__stack_66c__width_66 tlb_tte_tag_inv   (
 .din(tlb_tte_tag_b[65:0]),
 .dout(tlb_tte_tag[65:0])
);					

n2_tlb_tl_128x59_cust_inv_macro__width_1 rd_tte_u_bit_b_inv  (
 .din(rd_tte_u_bit),
 .dout(rd_tte_u_bit_b)
);

n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 tte_u_bit_out_reg  (
 .scan_in(tte_u_bit_out_reg_scanin),
 .scan_out(tte_u_bit_out_reg_scanout),
 .l1clk(l1clk_out),
 .din(rd_tte_u_bit_b),
 .dout(tlb_tte_u_bit_b),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_inv_macro__width_1 tlb_tte_u_bit_inv  (
 .din(tlb_tte_u_bit_b),
 .dout(tlb_tte_u_bit)
);

///////////////////////////////////////////////////////////////
// Tag compare logic
///////////////////////////////////////////////////////////////

n2_tlb_tl_128x59_cust_cmp_macro__width_32 way0_cmp  (
	.din0	({cache_ptag_w0[39:11],cache_set_vld[0],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1            ,1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[0])
);
n2_tlb_tl_128x59_cust_cmp_macro__width_32 way1_cmp  (
	.din0	({cache_ptag_w1[39:11],cache_set_vld[1],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1            ,1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[1])
);
n2_tlb_tl_128x59_cust_cmp_macro__width_32 way2_cmp  (
	.din0	({cache_ptag_w2[39:11],cache_set_vld[2],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1            ,1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[2])
);
n2_tlb_tl_128x59_cust_cmp_macro__width_32 way3_cmp  (
	.din0	({cache_ptag_w3[39:11],cache_set_vld[3],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1            ,1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[3])
);
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//

n2_tlb_tl_128x59_cust_inv_macro__width_4 cache_way_hit_in_b_inv  (
 .din(cache_way_hit_in[3:0]),
 .dout(cache_way_hit_in_b[3:0])
);

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_4 cache_way_hit_reg   (
 .scan_in(cache_way_hit_reg_scanin[3:0]),
 .scan_out(cache_way_hit_reg_scanout[3:0]),
 .l1clk(l1clk_out),
 .din(cache_way_hit_in_b[3:0]),
 .dout(cache_way_hit_b[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_128x59_cust_inv_macro__width_4 cache_way_hit_inv  (
 .din(cache_way_hit_b[3:0]),
 .dout(cache_way_hit[3:0])
);

n2_tlb_tl_128x59_cust_mux_macro__mux_aonpe__ports_4__width_1 cache_hit_or    (
	.din0	(cache_way_hit[0]),
	.din1	(cache_way_hit[1]),
	.din2	(cache_way_hit[2]),
	.din3	(cache_way_hit[3]),
	//
	//
	//
	//
	.sel0	(tlb_cam_mhit_b),
	.sel1	(tlb_cam_mhit_b),
	.sel2	(tlb_cam_mhit_b),
	.sel3	(tlb_cam_mhit_b),
	//
	//
	//
	//
	.dout	(cache_hit)	
);

///////////////////////////////////////////////////////////////
// Parity checks for tag and data
///////////////////////////////////////////////////////////////

n2_tlb_tl_128x59_cust_prty_macro__width_32 dprty0  (
	.din	(tlb_tte_data[31:0]),
	.dout	(data_parity_0)
);
n2_tlb_tl_128x59_cust_prty_macro__width_8 dprty1  (
	.din	({tlb_tte_data[36:32],data_parity_0,2'b0}),
	.dout	(tlb_tte_data_parity)
);


// Flops for circuit use

n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_4 mm_debug_reg   (
 .scan_in(mm_debug_reg_scanin[3:0]),
 .scan_out(mm_debug_reg_scanout[3:0]),
 .l1clk(l1clk_in),
 .din(mm_debug[3:0]),
 .dout(mm_debug[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign tag_read_mux_control = mm_debug[3];


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power
// Fullscan hookups begin
assign tte_data_reg_scanin	    [0] = scan_in			     ;
assign tte_data_reg_scanin	 [37:1] = tte_data_reg_scanout	      [36:0];

assign vaddr_reg_scanin		    [0] = tte_data_reg_scanout		 [37];
assign vaddr_reg_scanin		    [1] = vaddr_reg_scanout  		 [0];

assign rw_index_reg_scanin	    [5] = vaddr_reg_scanout  		 [1];
assign rw_index_reg_scanin	    [4] = rw_index_reg_scanout 	 [5];
assign rw_index_reg_scanin	    [3] = rw_index_reg_scanout 	 [4];
assign rw_index_reg_scanin	    [0] = rw_index_reg_scanout 	 [3];
assign rw_index_reg_scanin	    [1] = rw_index_reg_scanout 	 [0];
assign rw_index_reg_scanin	    [2] = rw_index_reg_scanout 	 [1];
assign rw_index_reg_scanin	    [6] = rw_index_reg_scanout 	 [2];

assign rw_index_vld_reg_scanin	         = rw_index_reg_scanout 	 [6];

assign cam_ctl_lat_scanin	    [6] = rw_index_vld_reg_scanout 	     ;
assign cam_ctl_lat_scanin	    [5] = cam_ctl_lat_scanout	 	 [6];
assign cam_ctl_lat_scanin	    [58] = cam_ctl_lat_scanout	 	 [5];
assign cam_ctl_lat_scanin	 [60:59] = cam_ctl_lat_scanout	      [59:58];
assign cam_ctl_lat_scanin	    [37] = cam_ctl_lat_scanout	 	 [60];
assign cam_ctl_lat_scanin	 [56:38] = cam_ctl_lat_scanout	      [55:37];

assign page_size_mask_reg_scanin    [0] = cam_ctl_lat_scanout	         [56];

assign cam_ctl_lat_scanin	    [21] = page_size_mask_reg_scanout    [0];
assign cam_ctl_lat_scanin	 [26:22] = cam_ctl_lat_scanout	      [25:21];

assign page_size_mask_reg_scanin    [1] = cam_ctl_lat_scanout	         [26];

assign cam_ctl_lat_scanin           [27] = page_size_mask_reg_scanout    [1];
assign cam_ctl_lat_scanin	 [29:28] = cam_ctl_lat_scanout	      [28:27];
assign cam_ctl_lat_scanin	    [31] = cam_ctl_lat_scanout	         [29];
assign cam_ctl_lat_scanin	 [33:32] = cam_ctl_lat_scanout	      [32:31];

assign page_size_mask_reg_scanin    [2] = cam_ctl_lat_scanout	         [33];

assign cam_ctl_lat_scanin           [34] = page_size_mask_reg_scanout    [2];
assign cam_ctl_lat_scanin	 [36:35] = cam_ctl_lat_scanout	      [35:34];
assign cam_ctl_lat_scanin	    [57] = cam_ctl_lat_scanout	 	 [36];
assign cam_ctl_lat_scanin	    [3] = cam_ctl_lat_scanout	 	 [57];
assign cam_ctl_lat_scanin	    [4] = cam_ctl_lat_scanout	 	 [3];
assign cam_ctl_lat_scanin	    [61] = cam_ctl_lat_scanout	 	 [4];
assign cam_ctl_lat_scanin	 [73:62] = cam_ctl_lat_scanout	      [72:61];
assign cam_ctl_lat_scanin	    [8] = cam_ctl_lat_scanout	 	 [73];
assign cam_ctl_lat_scanin	 [20:9] = cam_ctl_lat_scanout	      [19:8];

assign mm_debug_reg_scanin	    [3] = cam_ctl_lat_scanout	 	 [20];
assign mm_debug_reg_scanin	 [2:0] = mm_debug_reg_scanout	      [3:1];

assign cam_ctl_lat_scanin	    [7] = mm_debug_reg_scanout	 	 [0];

assign disable_clear_ubit_reg_scanin     = cam_ctl_lat_scanout	 	 [7];

assign cam_ctl_lat_scanin	    [30] = disable_clear_ubit_reg_scanout    ;
assign cam_ctl_lat_scanin	    [0] = cam_ctl_lat_scanout	 	 [30];
assign cam_ctl_lat_scanin	    [2] = cam_ctl_lat_scanout	 	 [0];
assign cam_ctl_lat_scanin	    [1] = cam_ctl_lat_scanout	 	 [2];

assign tlb_bypass_reg_scanin	         = cam_ctl_lat_scanout	 	 [1];

assign tlb_cam_hit_reg_scanin	    [2] = tlb_bypass_reg_scanout 	     ;
assign tlb_cam_hit_reg_scanin	    [0] = tlb_cam_hit_reg_scanout 	 [2];

assign tte_tag_out_reg_scanin	    [22] = tlb_cam_hit_reg_scanout 	 [0];

assign tte_u_bit_out_reg_scanin 	 = tte_tag_out_reg_scanout       [22];

assign tte_tag_out_reg_scanin	    [12] = tte_u_bit_out_reg_scanout 	     ;
assign tte_tag_out_reg_scanin	 [11:0] = tte_tag_out_reg_scanout    [12:1];
assign tte_tag_out_reg_scanin	    [65] = tte_tag_out_reg_scanout 	 [0];
assign tte_tag_out_reg_scanin	 [64:53] = tte_tag_out_reg_scanout    [65:54];
assign tte_tag_out_reg_scanin	    [49] = tte_tag_out_reg_scanout 	 [53];
assign tte_tag_out_reg_scanin       [28] = tte_tag_out_reg_scanout	 [49];
assign tte_tag_out_reg_scanin    [27:23] = tte_tag_out_reg_scanout    [28:24];
assign tte_tag_out_reg_scanin       [21] = tte_tag_out_reg_scanout       [23];
assign tte_tag_out_reg_scanin    [20:13] = tte_tag_out_reg_scanout    [21:14];
assign tte_tag_out_reg_scanin       [48] = tte_tag_out_reg_scanout       [13];
assign tte_tag_out_reg_scanin    [47:29] = tte_tag_out_reg_scanout    [48:30];
assign tte_tag_out_reg_scanin       [52] = tte_tag_out_reg_scanout       [29];
assign tte_tag_out_reg_scanin    [51:50] = tte_tag_out_reg_scanout    [52:51];

assign tte_data_out_reg_scanin      [0] = tte_tag_out_reg_scanout       [50];
assign tte_data_out_reg_scanin   [37:1] = tte_data_out_reg_scanout   [36:0];

assign cache_way_hit_reg_scanin     [0] = tte_data_out_reg_scanout      [37];
assign cache_way_hit_reg_scanin  [3:1] = cache_way_hit_reg_scanout  [2:0];

assign pa_reg_scanin                [0] = cache_way_hit_reg_scanout     [3];
assign pa_reg_scanin             [26:1] = pa_reg_scanout             [25:0];

assign tlb_cam_hit_reg_scanin       [1] = pa_reg_scanout                [26];

assign scan_out                          = tlb_cam_hit_reg_scanout       [1];
// Fullscan hookups end

`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_tlb_tl_128x59_cust_sram_msff_mo_macro__fs_1__width_74 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [73:0] d;
  input [73:0] scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [73:0] mq;
output [73:0] mq_l;
  output [73:0] scan_out;
output [73:0] q;
output [73:0] q_l;


new_dlata #(74)  d0_0 (
.d(d[73:0]),
.si(scan_in[73:0]),
.so(scan_out[73:0]),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[73:0]),
.q_l(q_l[73:0]),
.mq(mq[73:0]),
.mq_l(mq_l[73:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   invert macro
//
//


module n2_tlb_tl_128x59_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;

  input [2:0] din;
  input l1clk;
  input [2:0] scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output [2:0] scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si(scan_in[2:0]),
.so(scan_out[2:0]),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;

  input [1:0] din;
  input l1clk;
  input [1:0] scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output [1:0] scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si(scan_in[1:0]),
.so(scan_out[1:0]),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_38 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [37:0] fdin;

  input [37:0] din;
  input l1clk;
  input [37:0] scan_in;


  input siclk;
  input soclk;

  output [37:0] dout;
  output [37:0] scan_out;
assign fdin[37:0] = din[37:0];


dff #(38)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[37:0]),
.si(scan_in[37:0]),
.so(scan_out[37:0]),
.q(dout[37:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_mux_macro__mux_aope__ports_2__width_7 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [6:0] din0;
  input [6:0] din1;
  input sel0;
  output [6:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(7)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
.dout(dout[6:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;

  input [6:0] din;
  input l1clk;
  input [6:0] scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output [6:0] scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si(scan_in[6:0]),
.so(scan_out[6:0]),
.q(dout[6:0])
);


endmodule


module n2_tlb_tl_128x59_array (
  l1clk, 
  disable_clear_ubit, 
  tlb_bypass, 
  tlb_wr_flopped, 
  tlb_rd_flopped, 
  rw_index, 
  tlb_cam, 
  tlb_cam_flopped, 
  demap, 
  demap_context, 
  demap_all, 
  demap_real, 
  tte_tag, 
  tte_tag_flopped, 
  tte_ubit, 
  tte_page_size_mask, 
  tte_data, 
  va, 
  tag_read_mux_control, 
  pa, 
  tlb_cam_hit, 
  context0_hit, 
  multiple_match, 
  rd_tte_data, 
  rd_tte_tag, 
  rd_tte_u_bit, 
  tlb_replacement_index) ;
wire [127:0] ram_wwl;
wire [127:0] ram_rwl;
wire [127:0] valid;
wire force_data_to_x;
wire [127:0] used;


`define ENTRIES		128
`define INDEX		6

input		l1clk;
input		disable_clear_ubit;

input		tlb_bypass;
input		tlb_wr_flopped;
input		tlb_rd_flopped;
input	[`INDEX:0] rw_index;
input		tlb_cam;
input		tlb_cam_flopped;
input		demap;
input		demap_context;
input		demap_all;
input		demap_real;

input	[65:0]	tte_tag;
input	[65:0]	tte_tag_flopped;
input		tte_ubit;
input	[2:0]	tte_page_size_mask;
input	[37:0]	tte_data;
input	[12:11]	va;		// Incoming VA

input 		tag_read_mux_control;

output	[39:11]	pa;
output		tlb_cam_hit;
output		context0_hit;
output		multiple_match;
output	[37:0]	rd_tte_data;
output	[65:0]	rd_tte_tag;
output		rd_tte_u_bit;
output	[`INDEX:0] tlb_replacement_index;


`define VA_39 40
`define VA_28 29
`define VA_27 28
`define VA_22 23
`define VA_21 21
`define VA_16 16
`define VA_15 15 
`define VA_13 13


n2_tlb_tl_128x59_cam		cam(
  .l1clk(l1clk),
  .tlb_bypass(tlb_bypass),
  .tlb_wr_flopped(tlb_wr_flopped),
  .tlb_rd_flopped(tlb_rd_flopped),
  .rw_index(rw_index[6:0]),
  .tlb_cam(tlb_cam),
  .tlb_cam_flopped(tlb_cam_flopped),
  .demap(demap),
  .demap_context(demap_context),
  .demap_all(demap_all),
  .demap_real(demap_real),
  .tte_tag(tte_tag[65:0]),
  .tte_tag_flopped(tte_tag_flopped[65:0]),
  .tte_page_size_mask(tte_page_size_mask[2:0]),
  .tag_read_mux_control(tag_read_mux_control),
  .tlb_cam_hit(tlb_cam_hit),
  .context0_hit(context0_hit),
  .rd_tte_tag(rd_tte_tag[65:0]),
  .ram_wwl(ram_wwl[127:0]),
  .ram_rwl(ram_rwl[127:0]),
  .valid(valid[127:0]));

n2_tlb_tl_128x59_ram		ram(
	.va		({tte_tag_flopped[`VA_39:`VA_28],
			  tte_tag_flopped[`VA_27:`VA_22],
			  tte_tag_flopped[`VA_21:`VA_16],
			  tte_tag_flopped[`VA_15:`VA_13],
			  va[12:11]}),
  .l1clk(l1clk),
  .tlb_bypass(tlb_bypass),
  .tlb_cam_flopped(tlb_cam_flopped),
  .ram_wwl(ram_wwl[127:0]),
  .ram_rwl(ram_rwl[127:0]),
  .tte_data(tte_data[37:0]),
  .force_data_to_x(force_data_to_x),
  .pa(pa[39:11]),
  .rd_tte_data(rd_tte_data[37:0])
);

n2_tlb_tl_128x59_multihit	multihit (
	.tlb_cam_mhit			(multiple_match		),
  .ram_rwl(ram_rwl[127:0]),
  .tlb_bypass(tlb_bypass),
  .force_data_to_x(force_data_to_x)
);

n2_tlb_tl_128x59_ubit		ubit(
  .l1clk(l1clk),
  .disable_clear_ubit(disable_clear_ubit),
  .tlb_bypass(tlb_bypass),
  .ram_rwl(ram_rwl[127:0]),
  .ram_wwl(ram_wwl[127:0]),
  .tte_ubit(tte_ubit),
  .tlb_wr_flopped(tlb_wr_flopped),
  .tlb_rd_flopped(tlb_rd_flopped),
  .tlb_cam_flopped(tlb_cam_flopped),
  .used(used[127:0]),
  .rd_tte_u_bit(rd_tte_u_bit));

n2_tlb_tl_128x59_repl_index	repl_index(
  .l1clk(l1clk),
  .used(used[127:0]),
  .valid(valid[127:0]),
  .tlb_replacement_index(tlb_replacement_index[6:0]));


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule


`ifndef FPGA
module n2_tlb_tl_128x59_cam (
  l1clk, 
  tlb_bypass, 
  tlb_wr_flopped, 
  tlb_rd_flopped, 
  rw_index, 
  tlb_cam, 
  tlb_cam_flopped, 
  demap, 
  demap_context, 
  demap_all, 
  demap_real, 
  tte_tag, 
  tte_tag_flopped, 
  tte_page_size_mask, 
  tag_read_mux_control, 
  tlb_cam_hit, 
  context0_hit, 
  rd_tte_tag, 
  ram_wwl, 
  ram_rwl, 
  valid) ;
wire [6:0] rw_index_to_decode;
wire [127:0] decoded_index;


`define ENTRIES		128
`define INDEX		6


input		l1clk;

input		tlb_bypass;
input		tlb_wr_flopped;
input		tlb_rd_flopped;
input	[`INDEX:0] rw_index;
input		tlb_cam;
input		tlb_cam_flopped;
input		demap;
input		demap_context;
input		demap_all;
input		demap_real;

input	[65:0]	tte_tag;
input	[65:0]	tte_tag_flopped;
input	[2:0]	tte_page_size_mask;

input 		tag_read_mux_control;


output		tlb_cam_hit;
output		context0_hit;
output	[65:0]	rd_tte_tag;
output	[`ENTRIES-1:0] ram_wwl;
output	[`ENTRIES-1:0] ram_rwl;
output	[`ENTRIES-1:0] valid;


`define CNTX1_HI 65
`define CNTX1_LO 53
`define PID_HI   52
`define PID_LO   50
`define REAL_BIT 49
`define VA_47    48
`define VA_28    29
`define VA_27    28
`define VA_22    23
`define TTE_VALID 22 
`define VA_21    21
`define VA_16    16
`define VA_15    15 
`define VA_13    13
`define CNTX0_HI 12
`define CNTX0_LO  0


//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------

// local signals

reg 	[12:0] 	context_a	[`ENTRIES-1:0];  // Contexts a and b are
reg 	[12:0] 	context_a_	[`ENTRIES-1:0];  // to be equal at all times
reg 	[12:0] 	context_b	[`ENTRIES-1:0];  // This is NOT context 0 and 1
reg 	[12:0] 	context_b_	[`ENTRIES-1:0];  // This is NOT primary/secondary
reg        	r_bit		[`ENTRIES-1:0];
reg        	r_bit_		[`ENTRIES-1:0];
reg     [47:28] va_47_28	[`ENTRIES-1:0];
reg     [47:28] va_47_28_	[`ENTRIES-1:0];
reg     [27:22] va_27_22	[`ENTRIES-1:0];
reg     [27:22] va_27_22_	[`ENTRIES-1:0];
reg     [21:16] va_21_16	[`ENTRIES-1:0];
reg     [21:16] va_21_16_	[`ENTRIES-1:0];
reg     [15:13] va_15_13	[`ENTRIES-1:0];
reg     [15:13] va_15_13_	[`ENTRIES-1:0];
reg	[2:0]	pid		[`ENTRIES-1:0];
reg	[2:0]	pid_		[`ENTRIES-1:0];
reg 	[`ENTRIES-1:0]	valid;
reg 	[`ENTRIES-1:0]	match_for_sat;
reg 			tlb_cam_hit;
reg 			context0_hit;

integer n;
reg [31:0] n_reg;

reg [`ENTRIES-1:0] va_47_28_match ;
reg [`ENTRIES-1:0] va_27_22_match ;
reg [`ENTRIES-1:0] va_21_16_match ;
reg [`ENTRIES-1:0] va_15_13_match ;
reg [`ENTRIES-1:0] pid_match      ;
reg [`ENTRIES-1:0] real_match     ;
reg [`ENTRIES-1:0] context0_match ;
reg [`ENTRIES-1:0] context1_match ;
reg [`ENTRIES-1:0] context_match  ;
reg [`ENTRIES-1:0] match          ;
reg [`ENTRIES-1:0] ram_wl         ;
reg [65:0] rd_tte_tag;
reg [12:0] a_xnor_tag;
reg [12:0] b_xnor_tag;

reg 	   demap_posedge_l1clk;


`ifndef NOINITMEM
///////////////////////////////////////
// Initialize the arrays.            //
///////////////////////////////////////
initial begin
	for (n = 0; n < `ENTRIES; n = n+1) begin
		context_a	[n] = {13 {1'b0}};
		context_a_	[n] = {13 {1'b1}};
		context_b	[n] = {13 {1'b0}};
		context_b_	[n] = {13 {1'b1}};
		r_bit		[n] = { 1 {1'b0}};
		r_bit_		[n] = { 1 {1'b1}};
		va_47_28	[n] = {20 {1'b0}};
		va_47_28_	[n] = {20 {1'b1}};
		va_27_22	[n] = { 6 {1'b0}};
		va_27_22_	[n] = { 6 {1'b1}};
		va_21_16	[n] = { 6 {1'b0}};
		va_21_16_	[n] = { 6 {1'b1}};
		va_15_13	[n] = { 3 {1'b0}};
		va_15_13_	[n] = { 3 {1'b1}};
		pid		[n] = { 3 {1'b0}};
		pid_		[n] = { 3 {1'b1}};
		valid		[n] = { 1 {1'b0}};
	end // for (n = 0; n < `ENTRIES; n = n+1)
end
`endif


///////////////////////////////////////////////////////////////
// CAM, read
///////////////////////////////////////////////////////////////
always @(posedge l1clk) begin

	demap_posedge_l1clk = demap;

	match[`ENTRIES-1:0] = {`ENTRIES {1'b0}};

	if (tlb_cam | demap) begin
		for (n = 0; n < `ENTRIES; n = n + 1) begin
			// Have to represent dual match line architecture...
			// LSB 2 bits of context must both match AND MSB 11 bits must not mismatch
			a_xnor_tag[12:0] =       (context_a	[n] &  tte_tag[`CNTX1_HI:`CNTX1_LO]) |
						 (context_a_	[n] & ~tte_tag[`CNTX1_HI:`CNTX1_LO]) ;
			b_xnor_tag[12:0] =       (context_b	[n] &  tte_tag[`CNTX0_HI:`CNTX0_LO]) |
						 (context_b_	[n] & ~tte_tag[`CNTX0_HI:`CNTX0_LO]) ;
			context1_match[n] = demap_all | demap_real | 
					    (& a_xnor_tag[1:0]) & 
					    (~(| {context_a	[n] & ~tte_tag[`CNTX1_HI:`CNTX1_LO] & 13'h1ffc,
						  context_a_	[n] &  tte_tag[`CNTX1_HI:`CNTX1_LO] & 13'h1ffc}));
			context0_match[n] = demap_all | demap_real |
					    (& b_xnor_tag[1:0]) & 
					    (~(| {context_b	[n] & ~tte_tag[`CNTX0_HI:`CNTX0_LO] & 13'h1ffc,
						  context_b_	[n] &  tte_tag[`CNTX0_HI:`CNTX0_LO] & 13'h1ffc}));
			pid_match[n]      = (~(| {pid		[n] & ~tte_tag[`PID_HI	:`PID_LO  ],
						  pid_		[n] &  tte_tag[`PID_HI	:`PID_LO  ]}));
			real_match[n]     = demap_all | 
					    (~(| {r_bit		[n] & ~tte_tag[`REAL_BIT	  ],
						  r_bit_	[n] &  tte_tag[`REAL_BIT	  ]}));
			va_47_28_match[n] = demap_all | demap_real | demap_context |  
					    (~(| {va_47_28	[n] & ~tte_tag[`VA_47	:`VA_28   ],
						  va_47_28_	[n] &  tte_tag[`VA_47	:`VA_28   ]}));
			va_27_22_match[n] = demap_all | demap_real | demap_context |  
					    (~(| {va_27_22	[n] & ~tte_tag[`VA_27	:`VA_22   ],
						  va_27_22_	[n] &  tte_tag[`VA_27	:`VA_22   ]}));
			va_21_16_match[n] = demap_all | demap_real | demap_context |  
					    (~(| {va_21_16	[n] & ~tte_tag[`VA_21	:`VA_16   ],
						  va_21_16_	[n] &  tte_tag[`VA_21	:`VA_16   ]}));
			va_15_13_match[n] = demap_all | demap_real | demap_context |  
					    (~(| {va_15_13	[n] & ~tte_tag[`VA_15	:`VA_13   ],
						  va_15_13_	[n] &  tte_tag[`VA_15	:`VA_13   ]}));

			context_match[n]  = context0_match[n] | context1_match[n];
			
			match[n] = va_47_28_match[n] & va_27_22_match[n] & va_21_16_match[n] & 
				   va_15_13_match[n] & pid_match[n] & real_match[n] & context_match[n] &
				   valid[n];

		end // for (n = 0; n < `ENTRIES; n = n + 1)
		
		
	end // if (tlb_cam | demap)
	

	ram_wl[`ENTRIES-1:0] <= match[`ENTRIES-1:0];
	
end // always @ (posedge l1clk)


///////////////////////////////////////////////////////////////
// Demap, Write, Read
///////////////////////////////////////////////////////////////
always @(negedge l1clk) begin

	// Demap
	if (demap) begin	
		for (n = 0; n < `ENTRIES; n = n + 1) begin
			if (match[n]) begin
				valid[n] <= 1'b0;
			end
		end
	end // if (demap)	

	// Write
	if (tlb_wr_flopped) begin

		for (n = 0; n < `ENTRIES; n = n + 1) begin
			if (ram_wwl[n]) begin
				context_a	[n] <=( tte_tag_flopped[`CNTX1_HI:`CNTX1_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}};
				context_a_	[n] <=(~tte_tag_flopped[`CNTX1_HI:`CNTX1_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}};
				pid		[n] <=  tte_tag_flopped[`PID_HI  :`PID_LO  ];
				pid_		[n] <= ~tte_tag_flopped[`PID_HI  :`PID_LO  ];
				r_bit		[n] <=  tte_tag_flopped[`REAL_BIT          ];
				r_bit_		[n] <= ~tte_tag_flopped[`REAL_BIT          ];
				va_47_28	[n] <=  tte_tag_flopped[`VA_47   :`VA_28   ];
				va_47_28_	[n] <= ~tte_tag_flopped[`VA_47   :`VA_28   ];
				va_27_22	[n] <=  tte_tag_flopped[`VA_27   :`VA_22   ] & { 6 {~tte_page_size_mask[2]}};
				va_27_22_	[n] <= ~tte_tag_flopped[`VA_27   :`VA_22   ] & { 6 {~tte_page_size_mask[2]}};
				va_21_16	[n] <=  tte_tag_flopped[`VA_21   :`VA_16   ] & { 6 {~tte_page_size_mask[1]}};
				va_21_16_	[n] <= ~tte_tag_flopped[`VA_21   :`VA_16   ] & { 6 {~tte_page_size_mask[1]}};
				va_15_13	[n] <=  tte_tag_flopped[`VA_15   :`VA_13   ] & { 3 {~tte_page_size_mask[0]}};
				va_15_13_	[n] <= ~tte_tag_flopped[`VA_15   :`VA_13   ] & { 3 {~tte_page_size_mask[0]}};
				context_b	[n] <=( tte_tag_flopped[`CNTX0_HI:`CNTX0_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}};
				context_b_	[n] <=(~tte_tag_flopped[`CNTX0_HI:`CNTX0_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}};
				valid 		[n] <=  tte_tag_flopped[`TTE_VALID         ];

				
			end // if (ram_wwl[n])
		end // for (n = 0; n < `ENTRIES; n = n + 1)
		
	end // if (tlb_wr_flopped)
	
	// Read
	if (tlb_rd_flopped) begin
		if (tag_read_mux_control) begin
			rd_tte_tag[`CNTX1_HI:`CNTX1_LO] <= context_a_	[rw_index[`INDEX:0]];
			rd_tte_tag[`PID_HI  :`PID_LO  ] <= pid_		[rw_index[`INDEX:0]];
			rd_tte_tag[`REAL_BIT          ] <= r_bit_	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_47   :`VA_28   ] <= va_47_28_	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_27   :`VA_22   ] <= va_27_22_	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_21   :`VA_16   ] <= va_21_16_	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_15   :`VA_13   ] <= va_15_13_	[rw_index[`INDEX:0]];
			rd_tte_tag[`CNTX0_HI:`CNTX0_LO] <= context_b_	[rw_index[`INDEX:0]];
		end // if (tag_read_mux_control)
		else begin
			rd_tte_tag[`CNTX1_HI:`CNTX1_LO] <= context_a	[rw_index[`INDEX:0]];
			rd_tte_tag[`PID_HI  :`PID_LO  ] <= pid		[rw_index[`INDEX:0]];
			rd_tte_tag[`REAL_BIT          ] <= r_bit	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_47   :`VA_28   ] <= va_47_28	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_27   :`VA_22   ] <= va_27_22	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_21   :`VA_16   ] <= va_21_16	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_15   :`VA_13   ] <= va_15_13	[rw_index[`INDEX:0]];
			rd_tte_tag[`CNTX0_HI:`CNTX0_LO] <= context_b	[rw_index[`INDEX:0]];
		end // else: !if(tag_read_mux_control)
		rd_tte_tag[`TTE_VALID         ] <= valid	[rw_index[`INDEX:0]];
	end // if (tlb_rd
	else begin
	        rd_tte_tag[65:0] <= {66 {1'b0}} ;
	end // else: !if(tlb_rd)

end // always @ (negedge l1clk)


///////////////////////////////////////////////////////////////
// Output assignments
///////////////////////////////////////////////////////////////
// Have to hold them to next clock edge

// Read and write address decode
assign rw_index_to_decode[6:0] =
//	{1'b0,
	{rw_index[6],
	rw_index[5:0]};

assign decoded_index[127:0] = 
	{(rw_index_to_decode[6:0] == 7'h7f),
	 (rw_index_to_decode[6:0] == 7'h7e),
	 (rw_index_to_decode[6:0] == 7'h7d),
	 (rw_index_to_decode[6:0] == 7'h7c),
	 (rw_index_to_decode[6:0] == 7'h7b),
	 (rw_index_to_decode[6:0] == 7'h7a),
	 (rw_index_to_decode[6:0] == 7'h79),
	 (rw_index_to_decode[6:0] == 7'h78),
	 (rw_index_to_decode[6:0] == 7'h77),
	 (rw_index_to_decode[6:0] == 7'h76),
	 (rw_index_to_decode[6:0] == 7'h75),
	 (rw_index_to_decode[6:0] == 7'h74),
	 (rw_index_to_decode[6:0] == 7'h73),
	 (rw_index_to_decode[6:0] == 7'h72),
	 (rw_index_to_decode[6:0] == 7'h71),
	 (rw_index_to_decode[6:0] == 7'h70),
	 (rw_index_to_decode[6:0] == 7'h6f),
	 (rw_index_to_decode[6:0] == 7'h6e),
	 (rw_index_to_decode[6:0] == 7'h6d),
	 (rw_index_to_decode[6:0] == 7'h6c),
	 (rw_index_to_decode[6:0] == 7'h6b),
	 (rw_index_to_decode[6:0] == 7'h6a),
	 (rw_index_to_decode[6:0] == 7'h69),
	 (rw_index_to_decode[6:0] == 7'h68),
	 (rw_index_to_decode[6:0] == 7'h67),
	 (rw_index_to_decode[6:0] == 7'h66),
	 (rw_index_to_decode[6:0] == 7'h65),
	 (rw_index_to_decode[6:0] == 7'h64),
	 (rw_index_to_decode[6:0] == 7'h63),
	 (rw_index_to_decode[6:0] == 7'h62),
	 (rw_index_to_decode[6:0] == 7'h61),
	 (rw_index_to_decode[6:0] == 7'h60),
	 (rw_index_to_decode[6:0] == 7'h5f),
	 (rw_index_to_decode[6:0] == 7'h5e),
	 (rw_index_to_decode[6:0] == 7'h5d),
	 (rw_index_to_decode[6:0] == 7'h5c),
	 (rw_index_to_decode[6:0] == 7'h5b),
	 (rw_index_to_decode[6:0] == 7'h5a),
	 (rw_index_to_decode[6:0] == 7'h59),
	 (rw_index_to_decode[6:0] == 7'h58),
	 (rw_index_to_decode[6:0] == 7'h57),
	 (rw_index_to_decode[6:0] == 7'h56),
	 (rw_index_to_decode[6:0] == 7'h55),
	 (rw_index_to_decode[6:0] == 7'h54),
	 (rw_index_to_decode[6:0] == 7'h53),
	 (rw_index_to_decode[6:0] == 7'h52),
	 (rw_index_to_decode[6:0] == 7'h51),
	 (rw_index_to_decode[6:0] == 7'h50),
	 (rw_index_to_decode[6:0] == 7'h4f),
	 (rw_index_to_decode[6:0] == 7'h4e),
	 (rw_index_to_decode[6:0] == 7'h4d),
	 (rw_index_to_decode[6:0] == 7'h4c),
	 (rw_index_to_decode[6:0] == 7'h4b),
	 (rw_index_to_decode[6:0] == 7'h4a),
	 (rw_index_to_decode[6:0] == 7'h49),
	 (rw_index_to_decode[6:0] == 7'h48),
	 (rw_index_to_decode[6:0] == 7'h47),
	 (rw_index_to_decode[6:0] == 7'h46),
	 (rw_index_to_decode[6:0] == 7'h45),
	 (rw_index_to_decode[6:0] == 7'h44),
	 (rw_index_to_decode[6:0] == 7'h43),
	 (rw_index_to_decode[6:0] == 7'h42),
	 (rw_index_to_decode[6:0] == 7'h41),
	 (rw_index_to_decode[6:0] == 7'h40),
	 (rw_index_to_decode[6:0] == 7'h3f),
	 (rw_index_to_decode[6:0] == 7'h3e),
	 (rw_index_to_decode[6:0] == 7'h3d),
	 (rw_index_to_decode[6:0] == 7'h3c),
	 (rw_index_to_decode[6:0] == 7'h3b),
	 (rw_index_to_decode[6:0] == 7'h3a),
	 (rw_index_to_decode[6:0] == 7'h39),
	 (rw_index_to_decode[6:0] == 7'h38),
	 (rw_index_to_decode[6:0] == 7'h37),
	 (rw_index_to_decode[6:0] == 7'h36),
	 (rw_index_to_decode[6:0] == 7'h35),
	 (rw_index_to_decode[6:0] == 7'h34),
	 (rw_index_to_decode[6:0] == 7'h33),
	 (rw_index_to_decode[6:0] == 7'h32),
	 (rw_index_to_decode[6:0] == 7'h31),
	 (rw_index_to_decode[6:0] == 7'h30),
	 (rw_index_to_decode[6:0] == 7'h2f),
	 (rw_index_to_decode[6:0] == 7'h2e),
	 (rw_index_to_decode[6:0] == 7'h2d),
	 (rw_index_to_decode[6:0] == 7'h2c),
	 (rw_index_to_decode[6:0] == 7'h2b),
	 (rw_index_to_decode[6:0] == 7'h2a),
	 (rw_index_to_decode[6:0] == 7'h29),
	 (rw_index_to_decode[6:0] == 7'h28),
	 (rw_index_to_decode[6:0] == 7'h27),
	 (rw_index_to_decode[6:0] == 7'h26),
	 (rw_index_to_decode[6:0] == 7'h25),
	 (rw_index_to_decode[6:0] == 7'h24),
	 (rw_index_to_decode[6:0] == 7'h23),
	 (rw_index_to_decode[6:0] == 7'h22),
	 (rw_index_to_decode[6:0] == 7'h21),
	 (rw_index_to_decode[6:0] == 7'h20),
	 (rw_index_to_decode[6:0] == 7'h1f),
	 (rw_index_to_decode[6:0] == 7'h1e),
	 (rw_index_to_decode[6:0] == 7'h1d),
	 (rw_index_to_decode[6:0] == 7'h1c),
	 (rw_index_to_decode[6:0] == 7'h1b),
	 (rw_index_to_decode[6:0] == 7'h1a),
	 (rw_index_to_decode[6:0] == 7'h19),
	 (rw_index_to_decode[6:0] == 7'h18),
	 (rw_index_to_decode[6:0] == 7'h17),
	 (rw_index_to_decode[6:0] == 7'h16),
	 (rw_index_to_decode[6:0] == 7'h15),
	 (rw_index_to_decode[6:0] == 7'h14),
	 (rw_index_to_decode[6:0] == 7'h13),
	 (rw_index_to_decode[6:0] == 7'h12),
	 (rw_index_to_decode[6:0] == 7'h11),
	 (rw_index_to_decode[6:0] == 7'h10),
	 (rw_index_to_decode[6:0] == 7'h0f),
	 (rw_index_to_decode[6:0] == 7'h0e),
	 (rw_index_to_decode[6:0] == 7'h0d),
	 (rw_index_to_decode[6:0] == 7'h0c),
	 (rw_index_to_decode[6:0] == 7'h0b),
	 (rw_index_to_decode[6:0] == 7'h0a),
	 (rw_index_to_decode[6:0] == 7'h09),
	 (rw_index_to_decode[6:0] == 7'h08),
	 (rw_index_to_decode[6:0] == 7'h07),
	 (rw_index_to_decode[6:0] == 7'h06),
	 (rw_index_to_decode[6:0] == 7'h05),
	 (rw_index_to_decode[6:0] == 7'h04),
	 (rw_index_to_decode[6:0] == 7'h03),
	 (rw_index_to_decode[6:0] == 7'h02),
	 (rw_index_to_decode[6:0] == 7'h01),
	 (rw_index_to_decode[6:0] == 7'h00)};

//assign decoded_index_unused[127:64] = decoded_index[127:64];

always @(negedge l1clk) begin
	match_for_sat[`ENTRIES-1:0] <= match[`ENTRIES-1:0]; // For MMU SAT
	tlb_cam_hit <= (| match[`ENTRIES-1:0]) | tlb_bypass | ~tlb_cam;
	context0_hit <= (|(match[`ENTRIES-1:0] & context0_match[`ENTRIES-1:0])) & ~demap_posedge_l1clk;
end // always @ (negedge l1clk)

assign ram_wwl[`ENTRIES-1:0] = 
       decoded_index[`ENTRIES-1:0] & {`ENTRIES {tlb_wr_flopped}};

assign ram_rwl[`ENTRIES-1:0] = 
       (decoded_index[`ENTRIES-1:0] & {`ENTRIES {tlb_rd_flopped }}) |
       (ram_wl       [`ENTRIES-1:0] & {`ENTRIES {tlb_cam_flopped}});


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule
`endif 	// `ifndef FPGA

`ifdef FPGA
module n2_tlb_tl_128x59_cam(l1clk, tlb_bypass, tlb_wr_flopped, tlb_rd_flopped, 
	rw_index, tlb_cam, tlb_cam_flopped, demap, demap_context, demap_all, 
	demap_real, tte_tag, tte_tag_flopped, tte_page_size_mask, 
	tag_read_mux_control, tlb_cam_hit, context0_hit, rd_tte_tag, ram_wwl, 
	ram_rwl, valid);

	input			l1clk;
	input			tlb_bypass;
	input			tlb_wr_flopped;
	input			tlb_rd_flopped;
	input	[6:0]		rw_index;
	input			tlb_cam;
	input			tlb_cam_flopped;
	input			demap;
	input			demap_context;
	input			demap_all;
	input			demap_real;
	input	[65:0]		tte_tag;
	input	[65:0]		tte_tag_flopped;
	input	[2:0]		tte_page_size_mask;
	input			tag_read_mux_control;
	output			tlb_cam_hit;
	output			context0_hit;
	output	[65:0]		rd_tte_tag;
	output	[(128 - 1):0]	ram_wwl;
	output	[(128 - 1):0]	ram_rwl;
	output	[(128 - 1):0]	valid;

	wire	[6:0]		rw_index_to_decode;
	wire	[127:0]		decoded_index;

	reg	[12:0]		context_a[(128 - 1):0];
	reg	[12:0]		context_a_[(128 - 1):0];
	reg	[12:0]		context_b[(128 - 1):0];
	reg	[12:0]		context_b_[(128 - 1):0];
	reg			r_bit[(128 - 1):0];
	reg			r_bit_[(128 - 1):0];
	reg	[47:28]		va_47_28[(128 - 1):0];
	reg	[47:28]		va_47_28_[(128 - 1):0];
	reg	[27:22]		va_27_22[(128 - 1):0];
	reg	[27:22]		va_27_22_[(128 - 1):0];
	reg	[21:16]		va_21_16[(128 - 1):0];
	reg	[21:16]		va_21_16_[(128 - 1):0];
	reg	[15:13]		va_15_13[(128 - 1):0];
	reg	[15:13]		va_15_13_[(128 - 1):0];
	reg	[2:0]		pid[(128 - 1):0];
	reg	[2:0]		pid_[(128 - 1):0];
	reg	[(128 - 1):0]	match_for_sat;
	reg			tlb_cam_hit;
	reg			context0_hit;
	integer			n;
	reg	[31:0]		n_reg;
	reg	[(128 - 1):0]	va_47_28_match;
	reg	[(128 - 1):0]	va_27_22_match;
	reg	[(128 - 1):0]	va_21_16_match;
	reg	[(128 - 1):0]	va_15_13_match;
	reg	[(128 - 1):0]	pid_match;
	reg	[(128 - 1):0]	real_match;
	reg	[(128 - 1):0]	context0_match;
	reg	[(128 - 1):0]	context1_match;
	reg	[(128 - 1):0]	context_match;
	reg	[(128 - 1):0]	match;
	reg	[(128 - 1):0]	ram_wl;
	reg	[65:0]		rd_tte_tag;
	reg	[(128 - 1):0]	valid;
	reg	[12:0]		a_xnor_tag;
	reg	[12:0]		b_xnor_tag;
	reg			demap_posedge_l1clk;
	supply0			vss;
	supply1			vdd;

	assign rw_index_to_decode[6:0] = {rw_index[6], rw_index[5:0]};
	assign decoded_index[127:0] = {(rw_index_to_decode[6:0] == 7'b1111111), 
		(rw_index_to_decode[6:0] == 7'h7e), (rw_index_to_decode[6:0] ==
		7'h7d), (rw_index_to_decode[6:0] == 7'h7c), 
		(rw_index_to_decode[6:0] == 7'h7b), (rw_index_to_decode[6:0] ==
		7'h7a), (rw_index_to_decode[6:0] == 7'h79), 
		(rw_index_to_decode[6:0] == 7'h78), (rw_index_to_decode[6:0] ==
		7'h77), (rw_index_to_decode[6:0] == 7'h76), 
		(rw_index_to_decode[6:0] == 7'h75), (rw_index_to_decode[6:0] ==
		7'h74), (rw_index_to_decode[6:0] == 7'h73), 
		(rw_index_to_decode[6:0] == 7'h72), (rw_index_to_decode[6:0] ==
		7'h71), (rw_index_to_decode[6:0] == 7'h70), 
		(rw_index_to_decode[6:0] == 7'h6f), (rw_index_to_decode[6:0] ==
		7'h6e), (rw_index_to_decode[6:0] == 7'h6d), 
		(rw_index_to_decode[6:0] == 7'h6c), (rw_index_to_decode[6:0] ==
		7'h6b), (rw_index_to_decode[6:0] == 7'h6a), 
		(rw_index_to_decode[6:0] == 7'h69), (rw_index_to_decode[6:0] ==
		7'h68), (rw_index_to_decode[6:0] == 7'h67), 
		(rw_index_to_decode[6:0] == 7'h66), (rw_index_to_decode[6:0] ==
		7'h65), (rw_index_to_decode[6:0] == 7'h64), 
		(rw_index_to_decode[6:0] == 7'h63), (rw_index_to_decode[6:0] ==
		7'h62), (rw_index_to_decode[6:0] == 7'h61), 
		(rw_index_to_decode[6:0] == 7'h60), (rw_index_to_decode[6:0] ==
		7'h5f), (rw_index_to_decode[6:0] == 7'h5e), 
		(rw_index_to_decode[6:0] == 7'h5d), (rw_index_to_decode[6:0] ==
		7'h5c), (rw_index_to_decode[6:0] == 7'h5b), 
		(rw_index_to_decode[6:0] == 7'h5a), (rw_index_to_decode[6:0] ==
		7'h59), (rw_index_to_decode[6:0] == 7'h58), 
		(rw_index_to_decode[6:0] == 7'h57), (rw_index_to_decode[6:0] ==
		7'h56), (rw_index_to_decode[6:0] == 7'h55), 
		(rw_index_to_decode[6:0] == 7'h54), (rw_index_to_decode[6:0] ==
		7'h53), (rw_index_to_decode[6:0] == 7'h52), 
		(rw_index_to_decode[6:0] == 7'h51), (rw_index_to_decode[6:0] ==
		7'h50), (rw_index_to_decode[6:0] == 7'h4f), 
		(rw_index_to_decode[6:0] == 7'h4e), (rw_index_to_decode[6:0] ==
		7'h4d), (rw_index_to_decode[6:0] == 7'h4c), 
		(rw_index_to_decode[6:0] == 7'h4b), (rw_index_to_decode[6:0] ==
		7'h4a), (rw_index_to_decode[6:0] == 7'h49), 
		(rw_index_to_decode[6:0] == 7'h48), (rw_index_to_decode[6:0] ==
		7'h47), (rw_index_to_decode[6:0] == 7'h46), 
		(rw_index_to_decode[6:0] == 7'h45), (rw_index_to_decode[6:0] ==
		7'h44), (rw_index_to_decode[6:0] == 7'h43), 
		(rw_index_to_decode[6:0] == 7'h42), (rw_index_to_decode[6:0] ==
		7'h41), (rw_index_to_decode[6:0] == 7'h40), 
		(rw_index_to_decode[6:0] == 7'b0111111), 
		(rw_index_to_decode[6:0] == 7'h3e), (rw_index_to_decode[6:0] ==
		7'h3d), (rw_index_to_decode[6:0] == 7'h3c), 
		(rw_index_to_decode[6:0] == 7'h3b), (rw_index_to_decode[6:0] ==
		7'h3a), (rw_index_to_decode[6:0] == 7'h39), 
		(rw_index_to_decode[6:0] == 7'h38), (rw_index_to_decode[6:0] ==
		7'h37), (rw_index_to_decode[6:0] == 7'h36), 
		(rw_index_to_decode[6:0] == 7'h35), (rw_index_to_decode[6:0] ==
		7'h34), (rw_index_to_decode[6:0] == 7'h33), 
		(rw_index_to_decode[6:0] == 7'h32), (rw_index_to_decode[6:0] ==
		7'h31), (rw_index_to_decode[6:0] == 7'h30), 
		(rw_index_to_decode[6:0] == 7'h2f), (rw_index_to_decode[6:0] ==
		7'h2e), (rw_index_to_decode[6:0] == 7'h2d), 
		(rw_index_to_decode[6:0] == 7'h2c), (rw_index_to_decode[6:0] ==
		7'h2b), (rw_index_to_decode[6:0] == 7'h2a), 
		(rw_index_to_decode[6:0] == 7'h29), (rw_index_to_decode[6:0] ==
		7'h28), (rw_index_to_decode[6:0] == 7'h27), 
		(rw_index_to_decode[6:0] == 7'h26), (rw_index_to_decode[6:0] ==
		7'h25), (rw_index_to_decode[6:0] == 7'h24), 
		(rw_index_to_decode[6:0] == 7'h23), (rw_index_to_decode[6:0] ==
		7'h22), (rw_index_to_decode[6:0] == 7'h21), 
		(rw_index_to_decode[6:0] == 7'h20), (rw_index_to_decode[6:0] ==
		7'h1f), (rw_index_to_decode[6:0] == 7'h1e), 
		(rw_index_to_decode[6:0] == 7'h1d), (rw_index_to_decode[6:0] ==
		7'h1c), (rw_index_to_decode[6:0] == 7'h1b), 
		(rw_index_to_decode[6:0] == 7'h1a), (rw_index_to_decode[6:0] ==
		7'h19), (rw_index_to_decode[6:0] == 7'h18), 
		(rw_index_to_decode[6:0] == 7'h17), (rw_index_to_decode[6:0] ==
		7'h16), (rw_index_to_decode[6:0] == 7'h15), 
		(rw_index_to_decode[6:0] == 7'h14), (rw_index_to_decode[6:0] ==
		7'h13), (rw_index_to_decode[6:0] == 7'h12), 
		(rw_index_to_decode[6:0] == 7'h11), (rw_index_to_decode[6:0] ==
		7'h10), (rw_index_to_decode[6:0] == 7'h0f), 
		(rw_index_to_decode[6:0] == 7'h0e), (rw_index_to_decode[6:0] ==
		7'h0d), (rw_index_to_decode[6:0] == 7'h0c), 
		(rw_index_to_decode[6:0] == 7'h0b), (rw_index_to_decode[6:0] ==
		7'h0a), (rw_index_to_decode[6:0] == 7'h09), 
		(rw_index_to_decode[6:0] == 7'h08), (rw_index_to_decode[6:0] ==
		7'h07), (rw_index_to_decode[6:0] == 7'h06), 
		(rw_index_to_decode[6:0] == 7'h05), (rw_index_to_decode[6:0] ==
		7'h04), (rw_index_to_decode[6:0] == 7'h03), 
		(rw_index_to_decode[6:0] == 7'b0000010), 
		(rw_index_to_decode[6:0] == 7'b1), (rw_index_to_decode[6:0] ==
		7'b0)};
	assign ram_wwl[(128 - 1):0] = (decoded_index[(128 - 1):0] & {128 {
		tlb_wr_flopped}});
	assign ram_rwl[(128 - 1):0] = ((decoded_index[(128 - 1):0] & {128 {
		tlb_rd_flopped}}) | (ram_wl[(128 - 1):0] & {128 {tlb_cam_flopped
		}}));

	initial begin
	  for (n = 0; (n < 128); n = (n + 1)) begin
	    context_a[n] = {13 {1'b0}};
	    context_a_[n] = {13 {1'b1}};
	    context_b[n] = {13 {1'b0}};
	    context_b_[n] = {13 {1'b1}};
	    r_bit[n] = {1 {1'b0}};
	    r_bit_[n] = {1 {1'b1}};
	    va_47_28[n] = {20 {1'b0}};
	    va_47_28_[n] = {20 {1'b1}};
	    va_27_22[n] = {6 {1'b0}};
	    va_27_22_[n] = {6 {1'b1}};
	    va_21_16[n] = {6 {1'b0}};
	    va_21_16_[n] = {6 {1'b1}};
	    va_15_13[n] = {3 {1'b0}};
	    va_15_13_[n] = {3 {1'b1}};
	    pid[n] = {3 {1'b0}};
	    pid_[n] = {3 {1'b1}};
	    valid[n] = {1 {1'b0}};
	  end
	end
	always @(posedge l1clk) begin
	  demap_posedge_l1clk = demap;
	  match[(128 - 1):0] = {128 {1'b0}};
	  if (tlb_cam | demap) begin
	    for (n = 0; (n < 128); n = (n + 1)) begin
	      a_xnor_tag[12:0] = ((context_a[n] & tte_tag[65:53]) | (
		      context_a_[n] & (~tte_tag[65:53])));
	      b_xnor_tag[12:0] = ((context_b[n] & tte_tag[12:0]) | (
		      context_b_[n] & (~tte_tag[12:0])));
	      context1_match[n] = ((demap_all | demap_real) | ((&a_xnor_tag[1:0]
		      ) & (~(|{((context_a[n] & (~tte_tag[65:53])) & 13'h1ffc), 
		      ((context_a_[n] & tte_tag[65:53]) & 13'h1ffc)}))));
	      context0_match[n] = ((demap_all | demap_real) | ((&b_xnor_tag[1:0]
		      ) & (~(|{((context_b[n] & (~tte_tag[12:0])) & 13'h1ffc), 
		      ((context_b_[n] & tte_tag[12:0]) & 13'h1ffc)}))));
	      pid_match[n] = (~(|{(pid[n] & (~tte_tag[52:50])), (pid_[n] &
		      tte_tag[52:50])}));
	      real_match[n] = (demap_all | (~(|{(r_bit[n] & (~tte_tag[49])), 
		      (r_bit_[n] & tte_tag[49])})));
	      va_47_28_match[n] = (((demap_all | demap_real) | demap_context) | 
		      (~(|{(va_47_28[n] & (~tte_tag[48:29])), (va_47_28_[n] &
		      tte_tag[48:29])})));
	      va_27_22_match[n] = (((demap_all | demap_real) | demap_context) | 
		      (~(|{(va_27_22[n] & (~tte_tag[28:23])), (va_27_22_[n] &
		      tte_tag[28:23])})));
	      va_21_16_match[n] = (((demap_all | demap_real) | demap_context) | 
		      (~(|{(va_21_16[n] & (~tte_tag[21:16])), (va_21_16_[n] &
		      tte_tag[21:16])})));
	      va_15_13_match[n] = (((demap_all | demap_real) | demap_context) | 
		      (~(|{(va_15_13[n] & (~tte_tag[15:13])), (va_15_13_[n] &
		      tte_tag[15:13])})));
	      context_match[n] = (context0_match[n] | context1_match[n]);
	      match[n] = (((((((va_47_28_match[n] & va_27_22_match[n]) & 
		      va_21_16_match[n]) & va_15_13_match[n]) & pid_match[n]) & 
		      real_match[n]) & context_match[n]) & valid[n]);
	    end
	  end
	  ram_wl[(128 - 1):0] <= match[(128 - 1):0];
	end
	always @(negedge l1clk) begin
	  if (demap) begin
	    for (n = 0; (n < 128); n = (n + 1)) begin
	      if (match[n]) begin
		valid[n] <= 1'b0;
	      end
	    end
	  end
	  if (tlb_wr_flopped) begin
	    for (n = 0; (n < 128); n = (n + 1)) begin
	      if (ram_wwl[n]) begin
		context_a[n] <= ((tte_tag_flopped[65:53] & {13 {
			(~tte_tag_flopped[49])}}) | {11'b0, {2
			{tte_tag_flopped[49]}}});
		context_a_[n] <= (((~tte_tag_flopped[65:53]) & {13 {
			(~tte_tag_flopped[49])}}) | {11'b0, {2
			{tte_tag_flopped[49]}}});
		pid[n] <= tte_tag_flopped[52:50];
		pid_[n] <= (~tte_tag_flopped[52:50]);
		r_bit[n] <= tte_tag_flopped[49];
		r_bit_[n] <= (~tte_tag_flopped[49]);
		va_47_28[n] <= tte_tag_flopped[48:29];
		va_47_28_[n] <= (~tte_tag_flopped[48:29]);
		va_27_22[n] <= (tte_tag_flopped[28:23] & {6 {
			(~tte_page_size_mask[2])}});
		va_27_22_[n] <= ((~tte_tag_flopped[28:23]) & {6 {
			(~tte_page_size_mask[2])}});
		va_21_16[n] <= (tte_tag_flopped[21:16] & {6 {
			(~tte_page_size_mask[1])}});
		va_21_16_[n] <= ((~tte_tag_flopped[21:16]) & {6 {
			(~tte_page_size_mask[1])}});
		va_15_13[n] <= (tte_tag_flopped[15:13] & {3 {
			(~tte_page_size_mask[0])}});
		va_15_13_[n] <= ((~tte_tag_flopped[15:13]) & {3 {
			(~tte_page_size_mask[0])}});
		context_b[n] <= ((tte_tag_flopped[12:0] & {13 {
			(~tte_tag_flopped[49])}}) | {11'b0, {2
			{tte_tag_flopped[49]}}});
		context_b_[n] <= (((~tte_tag_flopped[12:0]) & {13 {
			(~tte_tag_flopped[49])}}) | {11'b0, {2
			{tte_tag_flopped[49]}}});
		valid[n] <= tte_tag_flopped[22];
	      end
	    end
	  end
	  if (tlb_rd_flopped) begin
	    if (tag_read_mux_control) begin
	      rd_tte_tag[65:53] <= context_a_[rw_index[6:0]];
	      rd_tte_tag[52:50] <= pid_[rw_index[6:0]];
	      rd_tte_tag[49] <= r_bit_[rw_index[6:0]];
	      rd_tte_tag[48:29] <= va_47_28_[rw_index[6:0]];
	      rd_tte_tag[28:23] <= va_27_22_[rw_index[6:0]];
	      rd_tte_tag[21:16] <= va_21_16_[rw_index[6:0]];
	      rd_tte_tag[15:13] <= va_15_13_[rw_index[6:0]];
	      rd_tte_tag[12:0] <= context_b_[rw_index[6:0]];
	    end
	    else
	      begin
		rd_tte_tag[65:53] <= context_a[rw_index[6:0]];
		rd_tte_tag[52:50] <= pid[rw_index[6:0]];
		rd_tte_tag[49] <= r_bit[rw_index[6:0]];
		rd_tte_tag[48:29] <= va_47_28[rw_index[6:0]];
		rd_tte_tag[28:23] <= va_27_22[rw_index[6:0]];
		rd_tte_tag[21:16] <= va_21_16[rw_index[6:0]];
		rd_tte_tag[15:13] <= va_15_13[rw_index[6:0]];
		rd_tte_tag[12:0] <= context_b[rw_index[6:0]];
	      end
	    rd_tte_tag[22] <= valid[rw_index[6:0]];
	  end
	  else
	    begin
	      rd_tte_tag[65:0] <= {66 {1'b0}};
	    end
	end
	always @(negedge l1clk) begin
	  match_for_sat[(128 - 1):0] <= match[(128 - 1):0];
	  tlb_cam_hit <= (((|match[(128 - 1):0]) | tlb_bypass) | (~tlb_cam));
	  context0_hit <= ((|(match[(128 - 1):0] & context0_match[(128 - 1):0]))
		  & (~demap_posedge_l1clk));
	end
endmodule

`endif


`ifndef FPGA
module n2_tlb_tl_128x59_ram (
  l1clk, 
  tlb_bypass, 
  tlb_cam_flopped, 
  ram_wwl, 
  ram_rwl, 
  tte_data, 
  va, 
  force_data_to_x, 
  pa, 
  rd_tte_data) ;
wire [6:0] encoded_rwl;
wire any_wwl;
wire any_rwl;
wire [39:13] tte_pa;


`define ENTRIES		128
`define INDEX		6


input		l1clk;

input		tlb_bypass;
input 		tlb_cam_flopped;
input	[`ENTRIES-1:0] ram_wwl;
input	[`ENTRIES-1:0] ram_rwl;

input	[37:0]	tte_data;
input	[39:11]	va;		// Incoming VA
input		force_data_to_x;


output	[39:11]	pa;
output	[37:0]	rd_tte_data;


`define DATA_PARITY         36
`define DATA_PA_39_28_HI    35
`define DATA_PA_39_28_LO    24
`define DATA_PA_27_22_HI    23
`define DATA_PA_27_22_LO    18
`define DATA_VA_27_22_V     17 
`define DATA_PA_21_16_HI    16
`define DATA_PA_21_16_LO    11
`define DATA_VA_21_16_V     10 
`define DATA_PA_15_13_HI     9
`define DATA_PA_15_13_LO     7
`define DATA_VA_15_13_V      6 
`define DATA_NFO             5 
`define DATA_IE              4 
`define DATA_CP              3 
`define DATA_X               2 
`define DATA_P               1 
`define DATA_W               0 

// Converted to structural to eliminate races
assign encoded_rwl[`INDEX:0] =
	{| {ram_rwl[127:64] },
	 | {ram_rwl[127:96] , ram_rwl[63:32]},
	 | {ram_rwl[127:112], ram_rwl[95:80], ram_rwl[63:48], ram_rwl[31:16]},
	 | {ram_rwl[127:120], ram_rwl[111:104], 
	    ram_rwl[95:88], ram_rwl[79:72], ram_rwl[63:56], ram_rwl[47:40],
	    ram_rwl[31:24], ram_rwl[15:8]},
	 | {ram_rwl[127:124], ram_rwl[119:116], ram_rwl[111:108], ram_rwl[103:100],
	    ram_rwl[95:92], ram_rwl[87:84], ram_rwl[79:76], ram_rwl[71:68], 
	    ram_rwl[63:60], ram_rwl[55:52], ram_rwl[47:44], ram_rwl[39:36],
	    ram_rwl[31:28], ram_rwl[23:20], ram_rwl[15:12], ram_rwl[7:4]},
	 | {ram_rwl[127:126], ram_rwl[123:122], ram_rwl[119:118], ram_rwl[115:114],
	    ram_rwl[111:110], ram_rwl[107:106], ram_rwl[103:102], ram_rwl[99:98],
	    ram_rwl[95:94], ram_rwl[91:90], ram_rwl[87:86], ram_rwl[83:82], 
	    ram_rwl[79:78], ram_rwl[75:74], ram_rwl[71:70], ram_rwl[67:66],
	    ram_rwl[63:62], ram_rwl[59:58], ram_rwl[55:54], ram_rwl[51:50],
	    ram_rwl[47:46], ram_rwl[43:42], ram_rwl[39:38], ram_rwl[35:34],
	    ram_rwl[31:30], ram_rwl[27:26], ram_rwl[23:22], ram_rwl[19:18],
	    ram_rwl[15:14], ram_rwl[11:10], ram_rwl[7:6], ram_rwl[3:2]},
	 | {ram_rwl[127], ram_rwl[125], ram_rwl[123], ram_rwl[121], 
	    ram_rwl[119], ram_rwl[117], ram_rwl[115], ram_rwl[113], ram_rwl[111], 
	    ram_rwl[109], ram_rwl[107], ram_rwl[105], ram_rwl[103], ram_rwl[101], 
	    ram_rwl[99], ram_rwl[97], ram_rwl[95], ram_rwl[93], ram_rwl[91], 
	    ram_rwl[89], ram_rwl[87], ram_rwl[85], ram_rwl[83], ram_rwl[81], 
	    ram_rwl[79], ram_rwl[77], ram_rwl[75], ram_rwl[73], ram_rwl[71], 
	    ram_rwl[69], ram_rwl[67], ram_rwl[65], ram_rwl[63], ram_rwl[61], 
	    ram_rwl[59], ram_rwl[57], ram_rwl[55], ram_rwl[53], ram_rwl[51], 
	    ram_rwl[49], ram_rwl[47], ram_rwl[45], ram_rwl[43], ram_rwl[41], 
	    ram_rwl[39], ram_rwl[37], ram_rwl[35], ram_rwl[33], ram_rwl[31], 
	    ram_rwl[29], ram_rwl[27], ram_rwl[25], ram_rwl[23], ram_rwl[21], 
	    ram_rwl[19], ram_rwl[17], ram_rwl[15], ram_rwl[13], ram_rwl[11], 
	    ram_rwl[9], ram_rwl[7], ram_rwl[5], ram_rwl[3], ram_rwl[1]}};

assign any_wwl =
	| ram_wwl[`ENTRIES-1:0];

assign any_rwl =
	| ram_rwl[`ENTRIES-1:0];


//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------

reg [37:0]  tlb_data[`ENTRIES-1:0] ;		// this models the data array

integer n;

`ifndef NOINITMEM
///////////////////////////////////////
// Initialize the arrays.            //
///////////////////////////////////////
initial begin
	for (n = 0; n < `ENTRIES; n = n + 1) begin
		tlb_data[n] = {38 {1'b0}};
	end
	`ifdef ENABLE_DUMPMEM
	if ($test$plusargs("DUMPMEM_DTLB")) begin
		$fsdbDumpMem(tlb_data, 0, `ENTRIES);
	end
	`endif
end
`endif


///////////////////////////////////////////////////////////////
// Write                                                     // 
///////////////////////////////////////////////////////////////
always @(negedge l1clk) begin

	for (n = 0; n < `ENTRIES; n = n + 1) begin
		if (ram_wwl[n]) begin
			tlb_data[n] <= tte_data[37:0];
			
			
			n = `ENTRIES;
			
		end // if (ram_wl[n])
	end // for (n = 0; n < `ENTRIES; n = n + 1)
	
end // always @ (ram_wl[`ENTRIES-1:0])


///////////////////////////////////////////////////////////////
// Read                                                      // 
///////////////////////////////////////////////////////////////

// ram_rwl is now second half cycle signal... so no need to latch
// Only force outputs to X if read and write at same time
// or on multiple hit
assign rd_tte_data[37:0] =
	({38 {any_rwl & ~any_wwl & ~force_data_to_x}} & tlb_data[encoded_rwl]) |
	({38 {any_rwl &  any_wwl & 1'bx}}) |
	({38 {force_data_to_x & 1'bx}}) ;


///////////////////////////////////////////////////////////////
// Construct the physical page number                        //
///////////////////////////////////////////////////////////////
assign tte_pa[39:13] = {rd_tte_data[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO],
                        rd_tte_data[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO],
                        rd_tte_data[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], 
                        rd_tte_data[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO]};

assign pa[12:11] = va[12:11];

assign pa[15:13] = 
       (~rd_tte_data[`DATA_VA_15_13_V] & tlb_cam_flopped & ~tlb_bypass) ? 
	       tte_pa[15:13] : va[15:13] ;
assign pa[21:16] = 
       (~rd_tte_data[`DATA_VA_21_16_V] & tlb_cam_flopped & ~tlb_bypass) ? 
	       tte_pa[21:16] : va[21:16] ;
assign pa[27:22] = 
       (~rd_tte_data[`DATA_VA_27_22_V] & tlb_cam_flopped & ~tlb_bypass) ? 
	       tte_pa[27:22] : va[27:22] ;
assign pa[39:28] = 
       (tlb_cam_flopped & ~tlb_bypass) ? 
	       tte_pa[39:28] : va[39:28];


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 

endmodule
`endif 	// `ifndef FPGA

`ifdef FPGA
module n2_tlb_tl_128x59_ram(l1clk, tlb_bypass, tlb_cam_flopped, ram_wwl, 
	ram_rwl, tte_data, va, force_data_to_x, pa, rd_tte_data);

	input			l1clk;
	input			tlb_bypass;
	input			tlb_cam_flopped;
	input	[(128 - 1):0]	ram_wwl;
	input	[(128 - 1):0]	ram_rwl;
	input	[37:0]		tte_data;
	input	[39:11]		va;
	input			force_data_to_x;
	output	[39:11]		pa;
	output	[37:0]		rd_tte_data;

	wire	[6:0]		encoded_rwl;
	wire			any_wwl;
	wire			any_rwl;
	wire	[39:13]		tte_pa;

	reg	[37:0]		tlb_data[(128 - 1):0];
	integer			n;
	supply0			vss;
	supply1			vdd;

	assign encoded_rwl[6:0] = {(|{ram_rwl[127:64]}), (|{ram_rwl[127:96],
		ram_rwl[63:32]}), (|{ram_rwl[127:112], ram_rwl[95:80],
		ram_rwl[63:48], ram_rwl[31:16]}), (|{ram_rwl[127:120],
		ram_rwl[111:104], ram_rwl[95:88], ram_rwl[79:72],
		ram_rwl[63:56], ram_rwl[47:40], ram_rwl[31:24], ram_rwl[15:8]}),
		(|{ram_rwl[127:124], ram_rwl[119:116], ram_rwl[111:108],
		ram_rwl[103:100], ram_rwl[95:92], ram_rwl[87:84],
		ram_rwl[79:76], ram_rwl[71:68], ram_rwl[63:60], ram_rwl[55:52],
		ram_rwl[47:44], ram_rwl[39:36], ram_rwl[31:28], ram_rwl[23:20],
		ram_rwl[15:12], ram_rwl[7:4]}), (|{ram_rwl[127:126],
		ram_rwl[123:122], ram_rwl[119:118], ram_rwl[115:114],
		ram_rwl[111:110], ram_rwl[107:106], ram_rwl[103:102],
		ram_rwl[99:98], ram_rwl[95:94], ram_rwl[91:90], ram_rwl[87:86],
		ram_rwl[83:82], ram_rwl[79:78], ram_rwl[75:74], ram_rwl[71:70],
		ram_rwl[67:66], ram_rwl[63:62], ram_rwl[59:58], ram_rwl[55:54],
		ram_rwl[51:50], ram_rwl[47:46], ram_rwl[43:42], ram_rwl[39:38],
		ram_rwl[35:34], ram_rwl[31:30], ram_rwl[27:26], ram_rwl[23:22],
		ram_rwl[19:18], ram_rwl[15:14], ram_rwl[11:10], ram_rwl[7:6],
		ram_rwl[3:2]}), (|{ram_rwl[127], ram_rwl[125], ram_rwl[123],
		ram_rwl[121], ram_rwl[119], ram_rwl[117], ram_rwl[115],
		ram_rwl[113], ram_rwl[111], ram_rwl[109], ram_rwl[107],
		ram_rwl[105], ram_rwl[103], ram_rwl[101], ram_rwl[99],
		ram_rwl[97], ram_rwl[95], ram_rwl[93], ram_rwl[91], ram_rwl[89],
		ram_rwl[87], ram_rwl[85], ram_rwl[83], ram_rwl[81], ram_rwl[79],
		ram_rwl[77], ram_rwl[75], ram_rwl[73], ram_rwl[71], ram_rwl[69],
		ram_rwl[67], ram_rwl[65], ram_rwl[63], ram_rwl[61], ram_rwl[59],
		ram_rwl[57], ram_rwl[55], ram_rwl[53], ram_rwl[51], ram_rwl[49],
		ram_rwl[47], ram_rwl[45], ram_rwl[43], ram_rwl[41], ram_rwl[39],
		ram_rwl[37], ram_rwl[35], ram_rwl[33], ram_rwl[31], ram_rwl[29],
		ram_rwl[27], ram_rwl[25], ram_rwl[23], ram_rwl[21], ram_rwl[19],
		ram_rwl[17], ram_rwl[15], ram_rwl[13], ram_rwl[11], ram_rwl[9],
		ram_rwl[7], ram_rwl[5], ram_rwl[3], ram_rwl[1]})};
	assign any_wwl = (|ram_wwl[(128 - 1):0]);
	assign any_rwl = (|ram_rwl[(128 - 1):0]);
	assign rd_tte_data[37:0] = ((({38 {((any_rwl & (~any_wwl)) &
		(~force_data_to_x))}} & tlb_data[encoded_rwl]) | {38 {((any_rwl
		& any_wwl) & 1'bx)}}) | {38 {(force_data_to_x & 1'bx)}});
	assign tte_pa[39:13] = {rd_tte_data[35:24], rd_tte_data[23:18], 
		rd_tte_data[16:11], rd_tte_data[9:7]};
	assign pa[12:11] = va[12:11];
	assign pa[15:13] = ((((~rd_tte_data[6]) & tlb_cam_flopped) & (~
		tlb_bypass)) ? tte_pa[15:13] : va[15:13]);
	assign pa[21:16] = ((((~rd_tte_data[10]) & tlb_cam_flopped) & (~
		tlb_bypass)) ? tte_pa[21:16] : va[21:16]);
	assign pa[27:22] = ((((~rd_tte_data[17]) & tlb_cam_flopped) & (~
		tlb_bypass)) ? tte_pa[27:22] : va[27:22]);
	assign pa[39:28] = ((tlb_cam_flopped & (~tlb_bypass)) ? tte_pa[39:28] : 
		va[39:28]);

	initial begin
	  for (n = 0; (n < 128); n = (n + 1)) begin
	    tlb_data[n] = {38 {1'b0}};
	  end
	end
	always @(negedge l1clk) begin
	  for (n = 0; (n < 128); n = (n + 1)) begin
	    if (ram_wwl[n]) begin
	      tlb_data[n] <= tte_data[37:0];
	    end
	  end
	end
endmodule

`endif


module n2_tlb_tl_128x59_multihit (
  ram_rwl, 
  tlb_bypass, 
  tlb_cam_mhit, 
  force_data_to_x) ;
wire [7:0] sum;
wire multiple_match;
wire unused;


`define ENTRIES		128
//`define INDEX		6


input	[`ENTRIES-1:0] ram_rwl;
input		tlb_bypass;


output		tlb_cam_mhit;
output		force_data_to_x;


assign sum[7:0] = 
	{{7 {1'b0}}, ram_rwl[0]} +
	{{7 {1'b0}}, ram_rwl[1]} +
	{{7 {1'b0}}, ram_rwl[2]} +
	{{7 {1'b0}}, ram_rwl[3]} +
	{{7 {1'b0}}, ram_rwl[4]} +
	{{7 {1'b0}}, ram_rwl[5]} +
	{{7 {1'b0}}, ram_rwl[6]} +
	{{7 {1'b0}}, ram_rwl[7]} +
	{{7 {1'b0}}, ram_rwl[8]} +
	{{7 {1'b0}}, ram_rwl[9]} +
	{{7 {1'b0}}, ram_rwl[10]} +
	{{7 {1'b0}}, ram_rwl[11]} +
	{{7 {1'b0}}, ram_rwl[12]} +
	{{7 {1'b0}}, ram_rwl[13]} +
	{{7 {1'b0}}, ram_rwl[14]} +
	{{7 {1'b0}}, ram_rwl[15]} +
	{{7 {1'b0}}, ram_rwl[16]} +
	{{7 {1'b0}}, ram_rwl[17]} +
	{{7 {1'b0}}, ram_rwl[18]} +
	{{7 {1'b0}}, ram_rwl[19]} +
	{{7 {1'b0}}, ram_rwl[20]} +
	{{7 {1'b0}}, ram_rwl[21]} +
	{{7 {1'b0}}, ram_rwl[22]} +
	{{7 {1'b0}}, ram_rwl[23]} +
	{{7 {1'b0}}, ram_rwl[24]} +
	{{7 {1'b0}}, ram_rwl[25]} +
	{{7 {1'b0}}, ram_rwl[26]} +
	{{7 {1'b0}}, ram_rwl[27]} +
	{{7 {1'b0}}, ram_rwl[28]} +
	{{7 {1'b0}}, ram_rwl[29]} +
	{{7 {1'b0}}, ram_rwl[30]} +
	{{7 {1'b0}}, ram_rwl[31]} +
	{{7 {1'b0}}, ram_rwl[32]} +
	{{7 {1'b0}}, ram_rwl[33]} +
	{{7 {1'b0}}, ram_rwl[34]} +
	{{7 {1'b0}}, ram_rwl[35]} +
	{{7 {1'b0}}, ram_rwl[36]} +
	{{7 {1'b0}}, ram_rwl[37]} +
	{{7 {1'b0}}, ram_rwl[38]} +
	{{7 {1'b0}}, ram_rwl[39]} +
	{{7 {1'b0}}, ram_rwl[40]} +
	{{7 {1'b0}}, ram_rwl[41]} +
	{{7 {1'b0}}, ram_rwl[42]} +
	{{7 {1'b0}}, ram_rwl[43]} +
	{{7 {1'b0}}, ram_rwl[44]} +
	{{7 {1'b0}}, ram_rwl[45]} +
	{{7 {1'b0}}, ram_rwl[46]} +
	{{7 {1'b0}}, ram_rwl[47]} +
	{{7 {1'b0}}, ram_rwl[48]} +
	{{7 {1'b0}}, ram_rwl[49]} +
	{{7 {1'b0}}, ram_rwl[50]} +
	{{7 {1'b0}}, ram_rwl[51]} +
	{{7 {1'b0}}, ram_rwl[52]} +
	{{7 {1'b0}}, ram_rwl[53]} +
	{{7 {1'b0}}, ram_rwl[54]} +
	{{7 {1'b0}}, ram_rwl[55]} +
	{{7 {1'b0}}, ram_rwl[56]} +
	{{7 {1'b0}}, ram_rwl[57]} +
	{{7 {1'b0}}, ram_rwl[58]} +
	{{7 {1'b0}}, ram_rwl[59]} +
	{{7 {1'b0}}, ram_rwl[60]} +
	{{7 {1'b0}}, ram_rwl[61]} +
	{{7 {1'b0}}, ram_rwl[62]} +
	{{7 {1'b0}}, ram_rwl[63]} +
	{{7 {1'b0}}, ram_rwl[64]} +
	{{7 {1'b0}}, ram_rwl[65]} +
	{{7 {1'b0}}, ram_rwl[66]} +
	{{7 {1'b0}}, ram_rwl[67]} +
	{{7 {1'b0}}, ram_rwl[68]} +
	{{7 {1'b0}}, ram_rwl[69]} +
	{{7 {1'b0}}, ram_rwl[70]} +
	{{7 {1'b0}}, ram_rwl[71]} +
	{{7 {1'b0}}, ram_rwl[72]} +
	{{7 {1'b0}}, ram_rwl[73]} +
	{{7 {1'b0}}, ram_rwl[74]} +
	{{7 {1'b0}}, ram_rwl[75]} +
	{{7 {1'b0}}, ram_rwl[76]} +
	{{7 {1'b0}}, ram_rwl[77]} +
	{{7 {1'b0}}, ram_rwl[78]} +
	{{7 {1'b0}}, ram_rwl[79]} +
	{{7 {1'b0}}, ram_rwl[80]} +
	{{7 {1'b0}}, ram_rwl[81]} +
	{{7 {1'b0}}, ram_rwl[82]} +
	{{7 {1'b0}}, ram_rwl[83]} +
	{{7 {1'b0}}, ram_rwl[84]} +
	{{7 {1'b0}}, ram_rwl[85]} +
	{{7 {1'b0}}, ram_rwl[86]} +
	{{7 {1'b0}}, ram_rwl[87]} +
	{{7 {1'b0}}, ram_rwl[88]} +
	{{7 {1'b0}}, ram_rwl[89]} +
	{{7 {1'b0}}, ram_rwl[90]} +
	{{7 {1'b0}}, ram_rwl[91]} +
	{{7 {1'b0}}, ram_rwl[92]} +
	{{7 {1'b0}}, ram_rwl[93]} +
	{{7 {1'b0}}, ram_rwl[94]} +
	{{7 {1'b0}}, ram_rwl[95]} +
	{{7 {1'b0}}, ram_rwl[96]} +
	{{7 {1'b0}}, ram_rwl[97]} +
	{{7 {1'b0}}, ram_rwl[98]} +
	{{7 {1'b0}}, ram_rwl[99]} +
	{{7 {1'b0}}, ram_rwl[100]} +
	{{7 {1'b0}}, ram_rwl[101]} +
	{{7 {1'b0}}, ram_rwl[102]} +
	{{7 {1'b0}}, ram_rwl[103]} +
	{{7 {1'b0}}, ram_rwl[104]} +
	{{7 {1'b0}}, ram_rwl[105]} +
	{{7 {1'b0}}, ram_rwl[106]} +
	{{7 {1'b0}}, ram_rwl[107]} +
	{{7 {1'b0}}, ram_rwl[108]} +
	{{7 {1'b0}}, ram_rwl[109]} +
	{{7 {1'b0}}, ram_rwl[110]} +
	{{7 {1'b0}}, ram_rwl[111]} +
	{{7 {1'b0}}, ram_rwl[112]} +
	{{7 {1'b0}}, ram_rwl[113]} +
	{{7 {1'b0}}, ram_rwl[114]} +
	{{7 {1'b0}}, ram_rwl[115]} +
	{{7 {1'b0}}, ram_rwl[116]} +
	{{7 {1'b0}}, ram_rwl[117]} +
	{{7 {1'b0}}, ram_rwl[118]} +
	{{7 {1'b0}}, ram_rwl[119]} +
	{{7 {1'b0}}, ram_rwl[120]} +
	{{7 {1'b0}}, ram_rwl[121]} +
	{{7 {1'b0}}, ram_rwl[122]} +
	{{7 {1'b0}}, ram_rwl[123]} +
	{{7 {1'b0}}, ram_rwl[124]} +
	{{7 {1'b0}}, ram_rwl[125]} +
	{{7 {1'b0}}, ram_rwl[126]} +
	{{7 {1'b0}}, ram_rwl[127]} ;


assign force_data_to_x = 
	(| sum[7:1]);

assign multiple_match = 
	(| sum[7:1]) & ~tlb_bypass;

assign unused = sum[0];

assign tlb_cam_mhit = 
       multiple_match;


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule


`ifndef FPGA
module n2_tlb_tl_128x59_ubit (
  l1clk, 
  disable_clear_ubit, 
  tlb_bypass, 
  ram_rwl, 
  ram_wwl, 
  tte_ubit, 
  tlb_wr_flopped, 
  tlb_rd_flopped, 
  tlb_cam_flopped, 
  used, 
  rd_tte_u_bit) ;
wire all_entries_used;


`define ENTRIES		128


input		l1clk;
input		disable_clear_ubit;

input		tlb_bypass;
input	[`ENTRIES-1:0] ram_rwl;
input	[`ENTRIES-1:0] ram_wwl;
input		tte_ubit;

input		tlb_wr_flopped;
input		tlb_rd_flopped;
input		tlb_cam_flopped;


output	[`ENTRIES-1:0] used;
output 		   rd_tte_u_bit;


//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------
reg [`ENTRIES-1:0] used;

integer 	   n;

reg 		   rd_tte_u_bit_in;


`ifndef NOINITMEM
///////////////////////////////////////
// Initialize the arrays.            //
///////////////////////////////////////
initial begin
	used[`ENTRIES-1:0]  = {`ENTRIES {1'b0}} ;
end
`endif


assign all_entries_used  = 
       (& used[`ENTRIES-1:0]) & ~disable_clear_ubit;


always @(negedge l1clk) begin
	// Maintain the used bits
	if (all_entries_used) begin
		used[`ENTRIES-1:0] <= {`ENTRIES {1'b0}};
	end

	if (~all_entries_used & ((~tlb_bypass & tlb_cam_flopped) | tlb_wr_flopped)) begin
		for (n = 0; n < `ENTRIES; n = n + 1) begin
			if (ram_rwl[n]) begin
				used[n] <= 1'b1;
			end
			if (ram_wwl[n]) begin
				used[n] <= tte_ubit;
			end
		end
	end // if (~all_entries_used & ((~tlb_bypass & tlb_cam_flopped) | tlb_wr_flopped))

	
end // always @ (negedge l1clk)


///////////////////////////////////////////////////////////////
// Read U bit
///////////////////////////////////////////////////////////////


always @(ram_rwl[`ENTRIES-1:0] or used[`ENTRIES-1:0] or tlb_rd_flopped) begin

	rd_tte_u_bit_in = {1'b0};

	if (tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0])) begin	 
		for (n = 0; n < `ENTRIES; n = n + 1) begin
			if (ram_rwl[n]) begin
				rd_tte_u_bit_in = used[n];
				
				
				n = `ENTRIES;
				
			end // if (ram_wl[n])
		end // for (n = 0; n < `ENTRIES; n = n + 1)
	end // if (tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0]))
	else if (~tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0])) begin
		rd_tte_u_bit_in = {1'bx};
	end
	
end

assign rd_tte_u_bit = 
       rd_tte_u_bit_in;


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule

`endif 	// `ifndef FPGA

`ifdef FPGA

module n2_tlb_tl_128x59_ubit(l1clk, disable_clear_ubit, tlb_bypass, ram_rwl, 
	ram_wwl, tte_ubit, tlb_wr_flopped, tlb_rd_flopped, tlb_cam_flopped, 
	used, rd_tte_u_bit);

	input			l1clk;
	input			disable_clear_ubit;
	input			tlb_bypass;
	input	[(128 - 1):0]	ram_rwl;
	input	[(128 - 1):0]	ram_wwl;
	input			tte_ubit;
	input			tlb_wr_flopped;
	input			tlb_rd_flopped;
	input			tlb_cam_flopped;
	output	[(128 - 1):0]	used;
	output			rd_tte_u_bit;

	wire			all_entries_used;
	reg	[(128 - 1):0]	used;
	integer			n;
	reg			rd_tte_u_bit_in;
	supply0			vss;
	supply1			vdd;

	assign all_entries_used = ((&used[(128 - 1):0]) & (~disable_clear_ubit))
		;
	assign rd_tte_u_bit = rd_tte_u_bit_in;

	initial begin
	  used[(128 - 1):0] = {128 {1'b0}};
	end
	always @(negedge l1clk) begin
	  if (all_entries_used) begin
	    used[(128 - 1):0] <= {128 {1'b0}};
	  end
	  if ((~all_entries_used) & (((~tlb_bypass) & tlb_cam_flopped) | 
		  tlb_wr_flopped)) begin
	    for (n = 0; (n < 128); n = (n + 1)) begin
	      if (ram_rwl[n]) begin
		used[n] <= 1'b1;
	      end
	      if (ram_wwl[n]) begin
		used[n] <= tte_ubit;
	      end
	    end
	  end
	end
	always @(ram_rwl[(128 - 1):0] or used[(128 - 1):0] or tlb_rd_flopped) 
		begin
	  rd_tte_u_bit_in = {1'b0};
	  if (tlb_rd_flopped & (|ram_rwl[(128 - 1):0])) begin
	    for (n = 0; (n < 128); n = (n + 1)) begin
	      if (ram_rwl[n]) begin
		rd_tte_u_bit_in = used[n];
	      end
	    end
	  end
	  else if ((~tlb_rd_flopped) & (|ram_rwl[(128 - 1):0])) begin
	    rd_tte_u_bit_in = {1'bx};
	  end
	end
endmodule

`endif  // `ifdef FPGA


module n2_tlb_tl_128x59_repl_index (
  l1clk, 
  used, 
  valid, 
  tlb_replacement_index) ;
wire [127:0] nu_or_nv;
wire [127:0] used_and_valid;
wire [1:0] enc4_00;
wire sel4_00_b;
wire [1:0] enc4_01;
wire sel4_01_b;
wire [1:0] enc4_02;
wire sel4_02_b;
wire [1:0] enc4_03;
wire sel4_03_b;
wire [1:0] enc4_04;
wire sel4_04_b;
wire [1:0] enc4_05;
wire sel4_05_b;
wire [1:0] enc4_06;
wire sel4_06_b;
wire [1:0] enc4_07;
wire sel4_07_b;
wire [1:0] enc4_08;
wire sel4_08_b;
wire [1:0] enc4_09;
wire sel4_09_b;
wire [1:0] enc4_10;
wire sel4_10_b;
wire [1:0] enc4_11;
wire sel4_11_b;
wire [1:0] enc4_12;
wire sel4_12_b;
wire [1:0] enc4_13;
wire sel4_13_b;
wire [1:0] enc4_14;
wire sel4_14_b;
wire [1:0] enc4_15;
wire sel4_15_b;
wire [1:0] enc4_16;
wire sel4_16_b;
wire [1:0] enc4_17;
wire sel4_17_b;
wire [1:0] enc4_18;
wire sel4_18_b;
wire [1:0] enc4_19;
wire sel4_19_b;
wire [1:0] enc4_20;
wire sel4_20_b;
wire [1:0] enc4_21;
wire sel4_21_b;
wire [1:0] enc4_22;
wire sel4_22_b;
wire [1:0] enc4_23;
wire sel4_23_b;
wire [1:0] enc4_24;
wire sel4_24_b;
wire [1:0] enc4_25;
wire sel4_25_b;
wire [1:0] enc4_26;
wire sel4_26_b;
wire [1:0] enc4_27;
wire sel4_27_b;
wire [1:0] enc4_28;
wire sel4_28_b;
wire [1:0] enc4_29;
wire sel4_29_b;
wire [1:0] enc4_30;
wire sel4_30_b;
wire [1:0] enc4_31;
wire sel4_31_b;
wire [2:0] enc8_00;
wire sel8_00_b;
wire [2:0] enc8_01;
wire sel8_01_b;
wire [2:0] enc8_02;
wire sel8_02_b;
wire [2:0] enc8_03;
wire sel8_03_b;
wire [2:0] enc8_04;
wire sel8_04_b;
wire [2:0] enc8_05;
wire sel8_05_b;
wire [2:0] enc8_06;
wire sel8_06_b;
wire [2:0] enc8_07;
wire sel8_07_b;
wire [2:0] enc8_08;
wire sel8_08_b;
wire [2:0] enc8_09;
wire sel8_09_b;
wire [2:0] enc8_10;
wire sel8_10_b;
wire [2:0] enc8_11;
wire sel8_11_b;
wire [2:0] enc8_12;
wire sel8_12_b;
wire [2:0] enc8_13;
wire sel8_13_b;
wire [2:0] enc8_14;
wire sel8_14_b;
wire [2:0] enc8_15;
wire sel8_15_b;
wire [3:0] enc16_0;
wire sel16_0_b;
wire [3:0] enc16_1;
wire sel16_1_b;
wire [3:0] enc16_2;
wire sel16_2_b;
wire [3:0] enc16_3;
wire sel16_3_b;
wire [3:0] enc16_4;
wire sel16_4_b;
wire [3:0] enc16_5;
wire sel16_5_b;
wire [3:0] enc16_6;
wire sel16_6_b;
wire [3:0] enc16_7;
wire sel16_7_b;
wire unused;
wire [3:0] enc16_l_0;
wire [3:0] enc16_l_1;
wire [3:0] enc16_l_2;
wire [3:0] enc16_l_3;
wire [3:0] enc16_l_4;
wire [3:0] enc16_l_5;
wire [3:0] enc16_l_6;
wire [3:0] enc16_l_7;
wire sel16_l_0_b;
wire sel16_l_1_b;
wire sel16_l_2_b;
wire sel16_l_3_b;
wire sel16_l_4_b;
wire sel16_l_5_b;
wire sel16_l_6_b;
wire sel16_l_7_b_unused;
wire [4:0] enc32_0;
wire sel32_0_b;
wire [4:0] enc32_1;
wire sel32_1_b;
wire [4:0] enc32_2;
wire sel32_2_b;
wire [4:0] enc32_3;
wire [5:0] enc64_0;
wire sel64_0_b;
wire [5:0] enc64_1;
wire [6:0] enc128_0;


`define ENTRIES		128
`define INDEX		6


input		l1clk;

input	[`ENTRIES-1:0] used;
input	[`ENTRIES-1:0] valid;


output	[`INDEX:0] tlb_replacement_index;


assign nu_or_nv[`ENTRIES-1:0] =
       ~valid[`ENTRIES-1:0] | ~used[`ENTRIES-1:0];

assign used_and_valid[`ENTRIES-1:0] =
       ~nu_or_nv[`ENTRIES-1:0];


// 4 bit priority encoders
assign enc4_00[1] = used_and_valid[0] &   used_and_valid[1];
assign enc4_00[0] = used_and_valid[0] & (~used_and_valid[1] | used_and_valid[2]);
assign sel4_00_b  = &used_and_valid[3:0];

assign enc4_01[1] = used_and_valid[4] &   used_and_valid[5];
assign enc4_01[0] = used_and_valid[4] & (~used_and_valid[5] | used_and_valid[6]);
assign sel4_01_b  = &used_and_valid[7:4];

assign enc4_02[1] = used_and_valid[8] &   used_and_valid[9];
assign enc4_02[0] = used_and_valid[8] & (~used_and_valid[9] | used_and_valid[10]);
assign sel4_02_b  = &used_and_valid[11:8];

assign enc4_03[1] = used_and_valid[12] &   used_and_valid[13];
assign enc4_03[0] = used_and_valid[12] & (~used_and_valid[13] | used_and_valid[14]);
assign sel4_03_b  = &used_and_valid[15:12];

assign enc4_04[1] = used_and_valid[16] &   used_and_valid[17];
assign enc4_04[0] = used_and_valid[16] & (~used_and_valid[17] | used_and_valid[18]);
assign sel4_04_b  = &used_and_valid[19:16];

assign enc4_05[1] = used_and_valid[20] &   used_and_valid[21];
assign enc4_05[0] = used_and_valid[20] & (~used_and_valid[21] | used_and_valid[22]);
assign sel4_05_b  = &used_and_valid[23:20];

assign enc4_06[1] = used_and_valid[24] &   used_and_valid[25];
assign enc4_06[0] = used_and_valid[24] & (~used_and_valid[25] | used_and_valid[26]);
assign sel4_06_b  = &used_and_valid[27:24];

assign enc4_07[1] = used_and_valid[28] &   used_and_valid[29];
assign enc4_07[0] = used_and_valid[28] & (~used_and_valid[29] | used_and_valid[30]);
assign sel4_07_b  = &used_and_valid[31:28];

assign enc4_08[1] = used_and_valid[32] &   used_and_valid[33];
assign enc4_08[0] = used_and_valid[32] & (~used_and_valid[33] | used_and_valid[34]);
assign sel4_08_b  = &used_and_valid[35:32];

assign enc4_09[1] = used_and_valid[36] &   used_and_valid[37];
assign enc4_09[0] = used_and_valid[36] & (~used_and_valid[37] | used_and_valid[38]);
assign sel4_09_b  = &used_and_valid[39:36];

assign enc4_10[1] = used_and_valid[40] &   used_and_valid[41];
assign enc4_10[0] = used_and_valid[40] & (~used_and_valid[41] | used_and_valid[42]);
assign sel4_10_b  = &used_and_valid[43:40];

assign enc4_11[1] = used_and_valid[44] &   used_and_valid[45];
assign enc4_11[0] = used_and_valid[44] & (~used_and_valid[45] | used_and_valid[46]);
assign sel4_11_b  = &used_and_valid[47:44];

assign enc4_12[1] = used_and_valid[48] &   used_and_valid[49];
assign enc4_12[0] = used_and_valid[48] & (~used_and_valid[49] | used_and_valid[50]);
assign sel4_12_b  = &used_and_valid[51:48];

assign enc4_13[1] = used_and_valid[52] &   used_and_valid[53];
assign enc4_13[0] = used_and_valid[52] & (~used_and_valid[53] | used_and_valid[54]);
assign sel4_13_b  = &used_and_valid[55:52];

assign enc4_14[1] = used_and_valid[56] &   used_and_valid[57];
assign enc4_14[0] = used_and_valid[56] & (~used_and_valid[57] | used_and_valid[58]);
assign sel4_14_b  = &used_and_valid[59:56];

assign enc4_15[1] = used_and_valid[60] &   used_and_valid[61];
assign enc4_15[0] = used_and_valid[60] & (~used_and_valid[61] | used_and_valid[62]);
assign sel4_15_b  = &used_and_valid[63:60];

assign enc4_16[1] = used_and_valid[64] &   used_and_valid[65];
assign enc4_16[0] = used_and_valid[64] & (~used_and_valid[65] | used_and_valid[66]);
assign sel4_16_b  = &used_and_valid[67:64];

assign enc4_17[1] = used_and_valid[68] &   used_and_valid[69];
assign enc4_17[0] = used_and_valid[68] & (~used_and_valid[69] | used_and_valid[70]);
assign sel4_17_b  = &used_and_valid[71:68];

assign enc4_18[1] = used_and_valid[72] &   used_and_valid[73];
assign enc4_18[0] = used_and_valid[72] & (~used_and_valid[73] | used_and_valid[74]);
assign sel4_18_b  = &used_and_valid[75:72];

assign enc4_19[1] = used_and_valid[76] &   used_and_valid[77];
assign enc4_19[0] = used_and_valid[76] & (~used_and_valid[77] | used_and_valid[78]);
assign sel4_19_b  = &used_and_valid[79:76];

assign enc4_20[1] = used_and_valid[80] &   used_and_valid[81];
assign enc4_20[0] = used_and_valid[80] & (~used_and_valid[81] | used_and_valid[82]);
assign sel4_20_b  = &used_and_valid[83:80];

assign enc4_21[1] = used_and_valid[84] &   used_and_valid[85];
assign enc4_21[0] = used_and_valid[84] & (~used_and_valid[85] | used_and_valid[86]);
assign sel4_21_b  = &used_and_valid[87:84];

assign enc4_22[1] = used_and_valid[88] &   used_and_valid[89];
assign enc4_22[0] = used_and_valid[88] & (~used_and_valid[89] | used_and_valid[90]);
assign sel4_22_b  = &used_and_valid[91:88];

assign enc4_23[1] = used_and_valid[92] &   used_and_valid[93];
assign enc4_23[0] = used_and_valid[92] & (~used_and_valid[93] | used_and_valid[94]);
assign sel4_23_b  = &used_and_valid[95:92];

assign enc4_24[1] = used_and_valid[96] &   used_and_valid[97];
assign enc4_24[0] = used_and_valid[96] & (~used_and_valid[97] | used_and_valid[98]);
assign sel4_24_b  = &used_and_valid[99:96];

assign enc4_25[1] = used_and_valid[100] &   used_and_valid[101];
assign enc4_25[0] = used_and_valid[100] & (~used_and_valid[101] | used_and_valid[102]);
assign sel4_25_b  = &used_and_valid[103:100];

assign enc4_26[1] = used_and_valid[104] &   used_and_valid[105];
assign enc4_26[0] = used_and_valid[104] & (~used_and_valid[105] | used_and_valid[106]);
assign sel4_26_b  = &used_and_valid[107:104];

assign enc4_27[1] = used_and_valid[108] &   used_and_valid[109];
assign enc4_27[0] = used_and_valid[108] & (~used_and_valid[109] | used_and_valid[110]);
assign sel4_27_b  = &used_and_valid[111:108];

assign enc4_28[1] = used_and_valid[112] &   used_and_valid[113];
assign enc4_28[0] = used_and_valid[112] & (~used_and_valid[113] | used_and_valid[114]);
assign sel4_28_b  = &used_and_valid[115:112];

assign enc4_29[1] = used_and_valid[116] &   used_and_valid[117];
assign enc4_29[0] = used_and_valid[116] & (~used_and_valid[117] | used_and_valid[118]);
assign sel4_29_b  = &used_and_valid[119:116];

assign enc4_30[1] = used_and_valid[120] &   used_and_valid[121];
assign enc4_30[0] = used_and_valid[120] & (~used_and_valid[121] | used_and_valid[122]);
assign sel4_30_b  = &used_and_valid[123:120];

assign enc4_31[1] = used_and_valid[124] &   used_and_valid[125];
assign enc4_31[0] = used_and_valid[124] & (~used_and_valid[125] | used_and_valid[126]);
assign sel4_31_b  = &used_and_valid[127:124];


// Now generate 8 bit group encodings
assign enc8_00[2]   = sel4_00_b;
assign enc8_00[1:0] = (enc4_00[1:0] & {2 {~sel4_00_b}}) | (enc4_01[1:0] & {2 {sel4_00_b}});
assign sel8_00_b    = sel4_00_b & sel4_01_b;

assign enc8_01[2]   = sel4_02_b;
assign enc8_01[1:0] = (enc4_02[1:0] & {2 {~sel4_02_b}}) | (enc4_03[1:0] & {2 {sel4_02_b}});
assign sel8_01_b    = sel4_02_b & sel4_03_b;

assign enc8_02[2]   = sel4_04_b;
assign enc8_02[1:0] = (enc4_04[1:0] & {2 {~sel4_04_b}}) | (enc4_05[1:0] & {2 {sel4_04_b}});
assign sel8_02_b    = sel4_04_b & sel4_05_b;

assign enc8_03[2]   = sel4_06_b;
assign enc8_03[1:0] = (enc4_06[1:0] & {2 {~sel4_06_b}}) | (enc4_07[1:0] & {2 {sel4_06_b}});
assign sel8_03_b    = sel4_06_b & sel4_07_b;

assign enc8_04[2]   = sel4_08_b;
assign enc8_04[1:0] = (enc4_08[1:0] & {2 {~sel4_08_b}}) | (enc4_09[1:0] & {2 {sel4_08_b}});
assign sel8_04_b    = sel4_08_b & sel4_09_b;

assign enc8_05[2]   = sel4_10_b;
assign enc8_05[1:0] = (enc4_10[1:0] & {2 {~sel4_10_b}}) | (enc4_11[1:0] & {2 {sel4_10_b}});
assign sel8_05_b    = sel4_10_b & sel4_11_b;

assign enc8_06[2]   = sel4_12_b;
assign enc8_06[1:0] = (enc4_12[1:0] & {2 {~sel4_12_b}}) | (enc4_13[1:0] & {2 {sel4_12_b}});
assign sel8_06_b    = sel4_12_b & sel4_13_b;

assign enc8_07[2]   = sel4_14_b;
assign enc8_07[1:0] = (enc4_14[1:0] & {2 {~sel4_14_b}}) | (enc4_15[1:0] & {2 {sel4_14_b}});
assign sel8_07_b    = sel4_14_b & sel4_15_b;

assign enc8_08[2]   = sel4_16_b;
assign enc8_08[1:0] = (enc4_16[1:0] & {2 {~sel4_16_b}}) | (enc4_17[1:0] & {2 {sel4_16_b}});
assign sel8_08_b    = sel4_16_b & sel4_17_b;

assign enc8_09[2]   = sel4_18_b;
assign enc8_09[1:0] = (enc4_18[1:0] & {2 {~sel4_18_b}}) | (enc4_19[1:0] & {2 {sel4_18_b}});
assign sel8_09_b    = sel4_18_b & sel4_19_b;

assign enc8_10[2]   = sel4_20_b;
assign enc8_10[1:0] = (enc4_20[1:0] & {2 {~sel4_20_b}}) | (enc4_21[1:0] & {2 {sel4_20_b}});
assign sel8_10_b    = sel4_20_b & sel4_21_b;

assign enc8_11[2]   = sel4_22_b;
assign enc8_11[1:0] = (enc4_22[1:0] & {2 {~sel4_22_b}}) | (enc4_23[1:0] & {2 {sel4_22_b}});
assign sel8_11_b    = sel4_22_b & sel4_23_b;

assign enc8_12[2]   = sel4_24_b;
assign enc8_12[1:0] = (enc4_24[1:0] & {2 {~sel4_24_b}}) | (enc4_25[1:0] & {2 {sel4_24_b}});
assign sel8_12_b    = sel4_24_b & sel4_25_b;

assign enc8_13[2]   = sel4_26_b;
assign enc8_13[1:0] = (enc4_26[1:0] & {2 {~sel4_26_b}}) | (enc4_27[1:0] & {2 {sel4_26_b}});
assign sel8_13_b    = sel4_26_b & sel4_27_b;

assign enc8_14[2]   = sel4_28_b;
assign enc8_14[1:0] = (enc4_28[1:0] & {2 {~sel4_28_b}}) | (enc4_29[1:0] & {2 {sel4_28_b}});
assign sel8_14_b    = sel4_28_b & sel4_29_b;

assign enc8_15[2]   = sel4_30_b;
assign enc8_15[1:0] = (enc4_30[1:0] & {2 {~sel4_30_b}}) | (enc4_31[1:0] & {2 {sel4_30_b}});
assign sel8_15_b    = sel4_30_b & sel4_31_b;


// Now generate 16 bit group encodings
assign enc16_0[3]   = sel8_00_b;
assign enc16_0[2:0] = (enc8_00[2:0] & {3 {~sel8_00_b}}) | (enc8_01[2:0] & {3 {sel8_00_b}});
assign sel16_0_b    = sel8_00_b & sel8_01_b;

assign enc16_1[3]   = sel8_02_b;
assign enc16_1[2:0] = (enc8_02[2:0] & {3 {~sel8_02_b}}) | (enc8_03[2:0] & {3 {sel8_02_b}});
assign sel16_1_b    = sel8_02_b & sel8_03_b;

assign enc16_2[3]   = sel8_04_b;
assign enc16_2[2:0] = (enc8_04[2:0] & {3 {~sel8_04_b}}) | (enc8_05[2:0] & {3 {sel8_04_b}});
assign sel16_2_b    = sel8_04_b & sel8_05_b;

assign enc16_3[3]   = sel8_06_b;
assign enc16_3[2:0] = (enc8_06[2:0] & {3 {~sel8_06_b}}) | (enc8_07[2:0] & {3 {sel8_06_b}});
assign sel16_3_b    = sel8_06_b & sel8_07_b;

assign enc16_4[3]   = sel8_08_b;
assign enc16_4[2:0] = (enc8_08[2:0] & {3 {~sel8_08_b}}) | (enc8_09[2:0] & {3 {sel8_08_b}});
assign sel16_4_b    = sel8_08_b & sel8_09_b;

assign enc16_5[3]   = sel8_10_b;
assign enc16_5[2:0] = (enc8_10[2:0] & {3 {~sel8_10_b}}) | (enc8_11[2:0] & {3 {sel8_10_b}});
assign sel16_5_b    = sel8_10_b & sel8_11_b;

assign enc16_6[3]   = sel8_12_b;
assign enc16_6[2:0] = (enc8_12[2:0] & {3 {~sel8_12_b}}) | (enc8_13[2:0] & {3 {sel8_12_b}});
assign sel16_6_b    = sel8_12_b & sel8_13_b;

assign enc16_7[3]   = sel8_14_b;
assign enc16_7[2:0] = (enc8_14[2:0] & {3 {~sel8_14_b}}) | (enc8_15[2:0] & {3 {sel8_14_b}});
assign sel16_7_b    = sel8_14_b & sel8_15_b;


// Now flop (nonscan)

n2_tlb_tl_128x59_cust_msff_ctl_macro__width_40 enc16_lat  (
 .scan_in	(1'b0),
 .scan_out	(unused),
 .l1clk		(l1clk),
 .siclk		(1'b0),				 
 .soclk		(1'b0),				 
 .din		({enc16_0[3:0],
		  enc16_1[3:0],
		  enc16_2[3:0],
		  enc16_3[3:0],
		  enc16_4[3:0],
		  enc16_5[3:0],
		  enc16_6[3:0],
		  enc16_7[3:0],
		  sel16_0_b,
		  sel16_1_b,
		  sel16_2_b,
		  sel16_3_b,
		  sel16_4_b,
		  sel16_5_b,
		  sel16_6_b,
		  sel16_7_b}),
 .dout		({enc16_l_0[3:0],
		  enc16_l_1[3:0],
		  enc16_l_2[3:0],
		  enc16_l_3[3:0],
		  enc16_l_4[3:0],
		  enc16_l_5[3:0],
		  enc16_l_6[3:0],
		  enc16_l_7[3:0],
		  sel16_l_0_b,
		  sel16_l_1_b,
		  sel16_l_2_b,
		  sel16_l_3_b,
		  sel16_l_4_b,
		  sel16_l_5_b,
		  sel16_l_6_b,
		  sel16_l_7_b_unused})
);


// Now generate 32 bit group encodings
assign enc32_0[4]   = sel16_l_0_b;
assign enc32_0[3:0] = (enc16_l_0[3:0] & {4 {~sel16_l_0_b}}) | (enc16_l_1[3:0] & {4 {sel16_l_0_b}});
assign sel32_0_b    = sel16_l_0_b & sel16_l_1_b;

assign enc32_1[4]   = sel16_l_2_b;
assign enc32_1[3:0] = (enc16_l_2[3:0] & {4 {~sel16_l_2_b}}) | (enc16_l_3[3:0] & {4 {sel16_l_2_b}});
assign sel32_1_b    = sel16_l_2_b & sel16_l_3_b;

assign enc32_2[4]   = sel16_l_4_b;
assign enc32_2[3:0] = (enc16_l_4[3:0] & {4 {~sel16_l_4_b}}) | (enc16_l_5[3:0] & {4 {sel16_l_4_b}});
assign sel32_2_b    = sel16_l_4_b & sel16_l_5_b;

assign enc32_3[4]   = sel16_l_6_b;
assign enc32_3[3:0] = (enc16_l_6[3:0] & {4 {~sel16_l_6_b}}) | (enc16_l_7[3:0] & {4 {sel16_l_6_b}});


// Now generate 64 bit group encodings
assign enc64_0[5]   = sel32_0_b;
assign enc64_0[4:0] = (enc32_0[4:0] & {5 {~sel32_0_b}}) | (enc32_1[4:0] & {5 {sel32_0_b}});
assign sel64_0_b    = sel32_0_b & sel32_1_b;

assign enc64_1[5]   = sel32_2_b;
assign enc64_1[4:0] = (enc32_2[4:0] & {5 {~sel32_2_b}}) | (enc32_3[4:0] & {5 {sel32_2_b}});


// Now generate 128 bit group encodings
assign enc128_0[6]   = sel64_0_b;
assign enc128_0[5:0] = (enc64_0[5:0] & {6 {~sel64_0_b}}) | (enc64_1[5:0] & {6 {sel64_0_b}});


assign tlb_replacement_index[6:0] = enc128_0[6:0];


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__width_40 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [39:0] fdin;
wire [38:0] so;

  input [39:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [39:0] dout;
  output scan_out;
assign fdin[39:0] = din[39:0];


dff #(40)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[39:0]),
.si({scan_in,so[38:0]}),
.so({so[38:0],scan_out}),
.q(dout[39:0])
);


endmodule


//
//   invert macro
//
//


module n2_tlb_tl_128x59_cust_inv_macro__width_27 (
  din, 
  dout);
  input [26:0] din;
  output [26:0] dout;


inv #(27)  d0_0 (
.in(din[26:0]),
.out(dout[26:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_27 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [26:0] fdin;

  input [26:0] din;
  input l1clk;
  input [26:0] scan_in;


  input siclk;
  input soclk;

  output [26:0] dout;
  output [26:0] scan_out;
assign fdin[26:0] = din[26:0];


dff #(27)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[26:0]),
.si(scan_in[26:0]),
.so(scan_out[26:0]),
.q(dout[26:0])
);


endmodule


//
//   invert macro
//
//


module n2_tlb_tl_128x59_cust_inv_macro__stack_66c__width_66 (
  din, 
  dout);
  input [65:0] din;
  output [65:0] dout;


inv #(66)  d0_0 (
.in(din[65:0]),
.out(dout[65:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_66 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [65:0] fdin;

  input [65:0] din;
  input l1clk;
  input [65:0] scan_in;


  input siclk;
  input soclk;

  output [65:0] dout;
  output [65:0] scan_out;
assign fdin[65:0] = din[65:0];


dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[65:0]),
.si(scan_in[65:0]),
.so(scan_out[65:0]),
.q(dout[65:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module n2_tlb_tl_128x59_cust_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module n2_tlb_tl_128x59_cust_inv_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;

  input [3:0] din;
  input l1clk;
  input [3:0] scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output [3:0] scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si(scan_in[3:0]),
.so(scan_out[3:0]),
.q(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_tlb_tl_128x59_cust_mux_macro__mux_aonpe__ports_4__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  input [0:0] din2;
  input sel2;
  input [0:0] din3;
  input sel3;
  output [0:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(1)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
  .in2(din2[0:0]),
  .in3(din3[0:0]),
.dout(dout[0:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module n2_tlb_tl_128x59_cust_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module n2_tlb_tl_128x59_cust_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_tlb_tl_64x59_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_tlb_tl_64x59_cust (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  pce, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  tcu_array_wr_inhibit, 
  tcu_scan_en, 
  disable_clear_ubit, 
  scan_out, 
  tlb_bypass, 
  tlb_wr_vld, 
  tlb_rd_vld, 
  tlb_cam_vld, 
  tlb_rw_index, 
  tlb_rw_index_vld, 
  tlb_demap, 
  tlb_demap_context, 
  tlb_demap_all, 
  tlb_demap_real, 
  tte_tag, 
  tte_ubit, 
  tte_page_size_mask, 
  tte_data, 
  tlb_va, 
  cache_ptag_w0, 
  cache_ptag_w1, 
  cache_ptag_w2, 
  cache_ptag_w3, 
  cache_ptag_w4, 
  cache_ptag_w5, 
  cache_ptag_w6, 
  cache_ptag_w7, 
  cache_set_vld, 
  cache_way_hit, 
  cache_hit, 
  tlb_cam_hit, 
  tlb_cam_mhit, 
  tlb_context0_hit, 
  tlb_pgnum_crit, 
  tlb_pgnum, 
  tlb_tte_data, 
  tlb_tte_tag, 
  tlb_tte_u_bit, 
  tlb_tte_data_parity) ;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire se;
wire l1clk_in;
wire l1clk_free;
wire [73:0] cam_ctl_lat_scanin;
wire [73:0] cam_ctl_lat_scanout;
wire [65:0] tte_tag_1;
wire tte_ubit_1;
wire tlb_wr_1_in_unused;
wire tlb_rd_1_unused;
wire tlb_cam_1_in;
wire demap_1_in;
wire demap_context_1;
wire demap_all_1;
wire demap_real_1;
wire [73:0] lat_l_unused;
wire [65:0] tte_tag_1_dout;
wire tte_ubit_1_unused;
wire tlb_wr_1_in_dout;
wire tlb_rd_1_in_dout;
wire tlb_cam_1_in_dout;
wire demap_1_in_unused;
wire demap_context_1_unused;
wire demap_all_1_unused;
wire demap_real_1_unused;
wire [73:0] dout_l_unused;
wire demap_page_1_unused;
wire wr_inhibit_;
wire tlb_wr_1_dout;
wire tlb_rd_1_dout;
wire tlb_cam_1;
wire tlb_cam_1_dout;
wire demap_1;
wire [2:0] page_size_mask_reg_scanin;
wire [2:0] page_size_mask_reg_scanout;
wire [2:0] tte_page_size_mask_1;
wire disable_clear_ubit_reg_scanin;
wire disable_clear_ubit_reg_scanout;
wire disable_clear_ubit_1_in;
wire disable_clear_ubit_1;
wire tlb_bypass_reg_scanin;
wire tlb_bypass_reg_scanout;
wire tlb_bypass_1;
wire [1:0] vaddr_reg_scanin;
wire [1:0] vaddr_reg_scanout;
wire [12:11] va_1;
wire [37:0] tte_data_reg_scanin;
wire [37:0] tte_data_reg_scanout;
wire [37:0] tte_data_1;
wire [5:0] tlb_replacement_index;
wire [5:0] rw_index_0;
wire [5:0] rw_index_reg_scanin;
wire [5:0] rw_index_reg_scanout;
wire [5:0] rw_index_1;
wire rw_index_vld_reg_scanin;
wire rw_index_vld_reg_scanout;
wire rw_index_vld_unused;
wire [39:11] pa_1;
wire tlb_cam_hit_1;
wire l1clk_out;
wire [2:0] tlb_cam_hit_reg_scanin;
wire [2:0] tlb_cam_hit_reg_scanout;
wire multiple_match;
wire context0_hit;
wire tlb_cam_mhit_b;
wire [26:0] pa_reg_scanin;
wire [26:0] pa_reg_scanout;
wire [39:13] pa_2;
wire [37:0] tte_data_out_reg_scanin;
wire [37:0] tte_data_out_reg_scanout;
wire [37:0] rd_tte_data;
wire [65:0] rd_tte_tag;
wire [65:0] rd_tte_tag_b;
wire [65:0] tte_tag_out_reg_scanin;
wire [65:0] tte_tag_out_reg_scanout;
wire [65:0] tlb_tte_tag_b;
wire rd_tte_u_bit;
wire rd_tte_u_bit_b;
wire tte_u_bit_out_reg_scanin;
wire tte_u_bit_out_reg_scanout;
wire tlb_tte_u_bit_b;
wire [7:0] cache_way_hit_in;
wire [7:0] cache_way_hit_in_b;
wire [7:0] cache_way_hit_reg_scanin;
wire [7:0] cache_way_hit_reg_scanout;
wire [7:0] cache_way_hit_b;
wire data_parity_0;
wire [3:0] mm_debug_reg_scanin;
wire [3:0] mm_debug_reg_scanout;
wire [3:0] mm_debug;
wire tag_read_mux_control;


input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input 		pce;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_se_scancollar_in;
input		tcu_se_scancollar_out;
input		tcu_array_wr_inhibit;
input		tcu_scan_en ;
input		disable_clear_ubit;
output		scan_out;

input		tlb_bypass;
input		tlb_wr_vld;
input		tlb_rd_vld;
input		tlb_cam_vld;
input	[5:0]	tlb_rw_index;
input		tlb_rw_index_vld;
input		tlb_demap;
input		tlb_demap_context;
input		tlb_demap_all;
input		tlb_demap_real;

input	[65:0]	tte_tag;
input		tte_ubit;
input	[2:0]	tte_page_size_mask;
input	[37:0]	tte_data;
input	[12:11]	tlb_va;		// Incoming VA

// Cache tag compare
input	[39:11]	cache_ptag_w0;
input	[39:11]	cache_ptag_w1;
input	[39:11]	cache_ptag_w2;
input	[39:11]	cache_ptag_w3;
input	[39:11]	cache_ptag_w4;
input	[39:11]	cache_ptag_w5;
input	[39:11]	cache_ptag_w6;
input	[39:11]	cache_ptag_w7;
input	[7:0]	cache_set_vld;

output	[7:0]	cache_way_hit;
output		cache_hit;
output		tlb_cam_hit;
output		tlb_cam_mhit;
output		tlb_context0_hit;
output	[39:13]	tlb_pgnum_crit; 	// PA unflopped
output	[39:13]	tlb_pgnum;	 	// PA flopped
output	[37:0]	tlb_tte_data;
output	[65:0]	tlb_tte_tag;
output		tlb_tte_u_bit;
output		tlb_tte_data_parity;

`ifndef FPGA
// synopsys translate_off
`endif

assign pce_ov = tcu_pce_ov;
assign stop   = 1'b0;
assign siclk  = tcu_aclk ;
assign soclk  = tcu_bclk;
assign se     = tcu_scan_en;


// 0in bits_on -var {tlb_wr_vld,tlb_rd_vld,tlb_cam_vld,tlb_demap} -max 1
// 0in bits_on -var {tlb_demap_context,tlb_demap_all,tlb_demap_real} -max 1
// 0in bits_on -var {tlb_cam_vld,tlb_bypass} -max 1
// 0in assert -var (~(tlb_demap_context & ~tlb_demap)) -message "Cannot asert tlb_demap_context without tlb_demap"
// 0in assert -var (~(tlb_demap_all     & ~tlb_demap)) -message "Cannot asert tlb_demap_all     without tlb_demap"
// 0in assert -var (~(tlb_demap_real    & ~tlb_demap)) -message "Cannot asert tlb_demap_real    without tlb_demap"
// 0in known_driven -var tlb_cam_hit


///////////////////////////////////////////////////////////////
// Input flops
///////////////////////////////////////////////////////////////

n2_tlb_tl_64x59_cust_l1clkhdr_ctl_macro in_clken (
 .l2clk(l2clk),
 .l1en(pce),
 .se(tcu_se_scancollar_in),
 .l1clk(l1clk_in),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_tlb_tl_64x59_cust_l1clkhdr_ctl_macro free_clken (
 .l2clk(l2clk),
 .l1en(pce),
 .se(se),
 .l1clk(l1clk_free),
  .pce_ov(pce_ov),
  .stop(stop)
);

// Put all the CAM controls and data in one latch to avoid races
// Doesn't really matter any more... also this gets split up in 
// gate level model
n2_tlb_tl_64x59_cust_sram_msff_mo_macro__fs_1__width_74 cam_ctl_lat   (
 .scan_in(cam_ctl_lat_scanin[73:0]),
 .scan_out(cam_ctl_lat_scanout[73:0]),
 .l1clk	(l1clk_in),
 .and_clk(l1clk_free),
//	            73:8      7        6
 .d	({tte_tag  [65:0],tte_ubit  ,tlb_wr_vld ,
//               5      4             3         2
	  tlb_rd_vld,tlb_cam_vld ,tlb_demap ,tlb_demap_context,
//	         1          0
	  tlb_demap_all,tlb_demap_real}),
 .mq	({tte_tag_1[65:0],tte_ubit_1,tlb_wr_1_in_unused,
	  tlb_rd_1_unused ,tlb_cam_1_in,demap_1_in,demap_context_1  ,
	  demap_all_1  ,demap_real_1  }),
 .mq_l	(lat_l_unused[73:0]),
// NOTE:  Some signals on dout port ARE used by bench (itlb_wr.v)!
 .q	({tte_tag_1_dout[65:0],tte_ubit_1_unused,tlb_wr_1_in_dout,
	  tlb_rd_1_in_dout,tlb_cam_1_in_dout,demap_1_in_unused,demap_context_1_unused  ,
	  demap_all_1_unused  ,demap_real_1_unused  }),
 .q_l	(dout_l_unused[73:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// This is strictly for DV
assign demap_page_1_unused =
       demap_1_in_unused & ~demap_context_1_unused & ~demap_all_1_unused & 
       ~demap_real_1_unused;

n2_tlb_tl_64x59_cust_inv_macro__width_1 wr_inhibit_b_inv  (
 .din(tcu_array_wr_inhibit),
 .dout(wr_inhibit_)
);				  

n2_tlb_tl_64x59_cust_and_macro__ports_2__width_1 tlb_wr_dout_and   (
 .din0(tlb_wr_1_in_dout),
 .din1(wr_inhibit_),
 .dout(tlb_wr_1_dout)
);				  

n2_tlb_tl_64x59_cust_and_macro__ports_2__width_1 tlb_rd_dout_and   (
 .din0(tlb_rd_1_in_dout),
 .din1(wr_inhibit_),
 .dout(tlb_rd_1_dout)
);				  

n2_tlb_tl_64x59_cust_and_macro__ports_2__width_1 tlb_cam_and   (
 .din0(tlb_cam_1_in),
 .din1(wr_inhibit_),
 .dout(tlb_cam_1)
);				  

n2_tlb_tl_64x59_cust_and_macro__ports_2__width_1 tlb_cam_dout_and   (
 .din0(tlb_cam_1_in_dout),
 .din1(wr_inhibit_),
 .dout(tlb_cam_1_dout)
);				  

n2_tlb_tl_64x59_cust_and_macro__ports_2__width_1 demap_and   (
 .din0(demap_1_in),
 .din1(wr_inhibit_),
 .dout(demap_1)
);				  

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_3 page_size_mask_reg   (
 .scan_in(page_size_mask_reg_scanin[2:0]),
 .scan_out(page_size_mask_reg_scanout[2:0]),
 .l1clk(l1clk_in),
 .din(tte_page_size_mask[2:0]),
 .dout(tte_page_size_mask_1[2:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_msff_ctl_macro__width_1 disable_clear_ubit_reg  (
 .scan_in(disable_clear_ubit_reg_scanin),
 .scan_out(disable_clear_ubit_reg_scanout),
 .l1clk(l1clk_in),
 .din(disable_clear_ubit),
 .dout(disable_clear_ubit_1_in),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_and_macro__ports_2__width_1 disable_clear_ubit_and   (
 .din0(disable_clear_ubit_1_in),
 .din1(wr_inhibit_),
 .dout(disable_clear_ubit_1)
);				  

n2_tlb_tl_64x59_cust_msff_ctl_macro__width_1 tlb_bypass_reg  (
 .scan_in(tlb_bypass_reg_scanin),
 .scan_out(tlb_bypass_reg_scanout),
 .l1clk(l1clk_in),
 .din(tlb_bypass),
 .dout(tlb_bypass_1),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_2 vaddr_reg   (
 .scan_in(vaddr_reg_scanin[1:0]),
 .scan_out(vaddr_reg_scanout[1:0]),
 .l1clk(l1clk_in),
 .din(tlb_va[12:11]),
 .dout(va_1[12:11]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_38 tte_data_reg   (
 .scan_in(tte_data_reg_scanin[37:0]),
 .scan_out(tte_data_reg_scanout[37:0]),
 .l1clk(l1clk_in),
 .din(tte_data[37:0]),
 .dout(tte_data_1[37:0]),
  .siclk(siclk),
  .soclk(soclk)
);


/////////////////////////////////////////////////////////////////////      
// Write index muxing
//////////////////////////////////////////////////////////////////////

n2_tlb_tl_64x59_cust_mux_macro__mux_aope__ports_2__width_6 rw_index_mux    (
 .din0	(tlb_rw_index[5:0]),
 .din1	(tlb_replacement_index[5:0]),
 .sel0	(tlb_rw_index_vld),
 .dout	(rw_index_0[5:0])	
);

// The output of this flop is used by the bench (dtlb_wr.vpal)
n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_6 rw_index_reg   (
 .scan_in(rw_index_reg_scanin[5:0]),
 .scan_out(rw_index_reg_scanout[5:0]),
 .l1clk(l1clk_in),
 .din(rw_index_0[5:0]),
 .dout(rw_index_1[5:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// This flop is here to mirror the circuit; it has no functional purpose;
// just want it here for 'debug' even though this signal
// is flopped outside the circuit
n2_tlb_tl_64x59_cust_msff_ctl_macro__width_1 rw_index_vld_reg  (
 .scan_in(rw_index_vld_reg_scanin),
 .scan_out(rw_index_vld_reg_scanout),
 .l1clk(l1clk_in),
 .din(tlb_rw_index_vld),
 .dout(rw_index_vld_unused),
  .siclk(siclk),
  .soclk(soclk)
);


/////////////////////////////////////////////////////////////////////      
// Array behavioral
/////////////////////////////////////////////////////////////////////      

n2_tlb_tl_64x59_array array (
// Inputs
	.l1clk		(l1clk_free),
	.tlb_bypass	(tlb_bypass_1),
	.tlb_wr_flopped	(tlb_wr_1_dout),
	.tlb_rd_flopped	(tlb_rd_1_dout),
	.rw_index	(rw_index_1[5:0]),
	.tlb_cam	(tlb_cam_1),
	.tlb_cam_flopped(tlb_cam_1_dout),
	.disable_clear_ubit(disable_clear_ubit_1),
	.demap		(demap_1),
	.demap_context	(demap_context_1),
	.demap_all	(demap_all_1),
	.demap_real	(demap_real_1),
	.tte_tag	(tte_tag_1[65:0]),
	.tte_tag_flopped(tte_tag_1_dout[65:0]),
	.tte_ubit	(tte_ubit_1),			     
	.tte_page_size_mask(tte_page_size_mask_1[2:0]),
	.tte_data	(tte_data_1[37:0]),
	.va		(va_1[12:11]),
// Outputs
	.pa		(pa_1[39:11]),
	.tlb_cam_hit	(tlb_cam_hit_1),
  .tag_read_mux_control(tag_read_mux_control),
  .context0_hit(context0_hit),
  .multiple_match(multiple_match),
  .rd_tte_data(rd_tte_data[37:0]),
  .rd_tte_tag(rd_tte_tag[65:0]),
  .rd_tte_u_bit(rd_tte_u_bit),
  .tlb_replacement_index(tlb_replacement_index[5:0])
);

// Unflopped output
assign tlb_pgnum_crit[39:13] = pa_1[39:13];

//////////////////////////////////////////////////
// Flop the output data
//////////////////////////////////////////////////

n2_tlb_tl_64x59_cust_l1clkhdr_ctl_macro out_clken (
 .l2clk(l2clk),
 .l1en(pce),
 .se(tcu_se_scancollar_out),
 .l1clk(l1clk_out),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_3 tlb_cam_hit_reg   (
 .scan_in(tlb_cam_hit_reg_scanin[2:0]),
 .scan_out(tlb_cam_hit_reg_scanout[2:0]),
 .l1clk(l1clk_out),
 .din({tlb_cam_hit_1,multiple_match,context0_hit}),
 .dout({tlb_cam_hit,tlb_cam_mhit,tlb_context0_hit}),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_inv_macro__width_1 tlb_cam_mhit_b_inv  (
 .din(tlb_cam_mhit),
 .dout(tlb_cam_mhit_b)
);					

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_27 pa_reg   (
 .scan_in(pa_reg_scanin[26:0]),
 .scan_out(pa_reg_scanout[26:0]),
 .l1clk(l1clk_out),
 .din(pa_1[39:13]),
 .dout(pa_2[39:13]),
  .siclk(siclk),
  .soclk(soclk)
);

assign tlb_pgnum[39:13] = pa_2[39:13];

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_38 tte_data_out_reg   (
 .scan_in(tte_data_out_reg_scanin[37:0]),
 .scan_out(tte_data_out_reg_scanout[37:0]),
 .l1clk(l1clk_out),
 .din(rd_tte_data[37:0]),
 .dout(tlb_tte_data[37:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_inv_macro__stack_66c__width_66 rd_tte_tag_b_inv   (
 .din(rd_tte_tag[65:0]),
 .dout(rd_tte_tag_b[65:0])
);					

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_66 tte_tag_out_reg   (
 .scan_in(tte_tag_out_reg_scanin[65:0]),
 .scan_out(tte_tag_out_reg_scanout[65:0]),
 .l1clk(l1clk_out),
 .din(rd_tte_tag_b[65:0]),
 .dout(tlb_tte_tag_b[65:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_inv_macro__stack_66c__width_66 tlb_tte_tag_inv   (
 .din(tlb_tte_tag_b[65:0]),
 .dout(tlb_tte_tag[65:0])
);					

n2_tlb_tl_64x59_cust_inv_macro__width_1 rd_tte_u_bit_b_inv  (
 .din(rd_tte_u_bit),
 .dout(rd_tte_u_bit_b)
);

n2_tlb_tl_64x59_cust_msff_ctl_macro__width_1 tte_u_bit_out_reg  (
 .scan_in(tte_u_bit_out_reg_scanin),
 .scan_out(tte_u_bit_out_reg_scanout),
 .l1clk(l1clk_out),
 .din(rd_tte_u_bit_b),
 .dout(tlb_tte_u_bit_b),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_inv_macro__width_1 tlb_tte_u_bit_inv  (
 .din(tlb_tte_u_bit_b),
 .dout(tlb_tte_u_bit)
);

///////////////////////////////////////////////////////////////
// Tag compare logic
///////////////////////////////////////////////////////////////

n2_tlb_tl_64x59_cust_cmp_macro__width_32 way0_cmp  (
	.din0	({cache_ptag_w0[39:11],cache_set_vld[0],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1,            1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[0])
);
n2_tlb_tl_64x59_cust_cmp_macro__width_32 way1_cmp  (
	.din0	({cache_ptag_w1[39:11],cache_set_vld[1],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1,            1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[1])
);
n2_tlb_tl_64x59_cust_cmp_macro__width_32 way2_cmp  (
	.din0	({cache_ptag_w2[39:11],cache_set_vld[2],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1,            1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[2])
);
n2_tlb_tl_64x59_cust_cmp_macro__width_32 way3_cmp  (
	.din0	({cache_ptag_w3[39:11],cache_set_vld[3],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1,            1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[3])
);
n2_tlb_tl_64x59_cust_cmp_macro__width_32 way4_cmp  (
	.din0	({cache_ptag_w4[39:11],cache_set_vld[4],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1,            1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[4])
);
n2_tlb_tl_64x59_cust_cmp_macro__width_32 way5_cmp  (
	.din0	({cache_ptag_w5[39:11],cache_set_vld[5],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1,            1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[5])
);
n2_tlb_tl_64x59_cust_cmp_macro__width_32 way6_cmp  (
	.din0	({cache_ptag_w6[39:11],cache_set_vld[6],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1,            1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[6])
);
n2_tlb_tl_64x59_cust_cmp_macro__width_32 way7_cmp  (
	.din0	({cache_ptag_w7[39:11],cache_set_vld[7],1'b0          , 1'b0}),
	.din1	({pa_1[39:11],         1'b1,            1'b0          , 1'b0}),
	.dout	(cache_way_hit_in[7])
);

n2_tlb_tl_64x59_cust_inv_macro__width_8 cache_way_hit_in_b_inv  (
 .din(cache_way_hit_in[7:0]),
 .dout(cache_way_hit_in_b[7:0])
);

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_8 cache_way_hit_reg   (
 .scan_in(cache_way_hit_reg_scanin[7:0]),
 .scan_out(cache_way_hit_reg_scanout[7:0]),
 .l1clk(l1clk_out),
 .din(cache_way_hit_in_b[7:0]),
 .dout(cache_way_hit_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_tlb_tl_64x59_cust_inv_macro__width_8 cache_way_hit_inv  (
 .din(cache_way_hit_b[7:0]),
 .dout(cache_way_hit[7:0])
);

n2_tlb_tl_64x59_cust_mux_macro__mux_aonpe__ports_8__width_1 cache_hit_or    (
	.din0	(cache_way_hit[0]),
	.din1	(cache_way_hit[1]),
	.din2	(cache_way_hit[2]),
	.din3	(cache_way_hit[3]),
	.din4	(cache_way_hit[4]),
	.din5	(cache_way_hit[5]),
	.din6	(cache_way_hit[6]),
	.din7	(cache_way_hit[7]),
	.sel0	(tlb_cam_mhit_b),
	.sel1	(tlb_cam_mhit_b),
	.sel2	(tlb_cam_mhit_b),
	.sel3	(tlb_cam_mhit_b),
	.sel4	(tlb_cam_mhit_b),
	.sel5	(tlb_cam_mhit_b),
	.sel6	(tlb_cam_mhit_b),
	.sel7	(tlb_cam_mhit_b),
	.dout	(cache_hit)	
);

///////////////////////////////////////////////////////////////
// Parity checks for data
///////////////////////////////////////////////////////////////

n2_tlb_tl_64x59_cust_prty_macro__width_32 dprty0  (
	.din	(tlb_tte_data[31:0]),
	.dout	(data_parity_0)
);
n2_tlb_tl_64x59_cust_prty_macro__width_8 dprty1  (
	.din	({2'b00,tlb_tte_data[36:32],data_parity_0}),
	.dout	(tlb_tte_data_parity)
);


// Flops for circuit use

n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_4 mm_debug_reg   (
 .scan_in(mm_debug_reg_scanin[3:0]),
 .scan_out(mm_debug_reg_scanout[3:0]),
 .l1clk(l1clk_in),
 .din(mm_debug[3:0]),
 .dout(mm_debug[3:0]),
  .siclk(siclk),
  .soclk(soclk)
);

assign tag_read_mux_control = mm_debug[3];


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
// Fullscan hookups begin
assign tte_data_reg_scanin	    [0] = scan_in			     ;
assign tte_data_reg_scanin	 [37:1] = tte_data_reg_scanout	      [36:0];

assign vaddr_reg_scanin		    [0] = tte_data_reg_scanout		 [37];
assign vaddr_reg_scanin		    [1] = vaddr_reg_scanout  		 [0];

assign rw_index_reg_scanin	    [5] = vaddr_reg_scanout  		 [1];
assign rw_index_reg_scanin	    [4] = rw_index_reg_scanout 	 [5];
assign rw_index_reg_scanin	    [3] = rw_index_reg_scanout 	 [4];
assign rw_index_reg_scanin	    [0] = rw_index_reg_scanout 	 [3];
assign rw_index_reg_scanin	    [1] = rw_index_reg_scanout 	 [0];
assign rw_index_reg_scanin	    [2] = rw_index_reg_scanout 	 [1];


assign rw_index_vld_reg_scanin	         = rw_index_reg_scanout 	 [2];

assign cam_ctl_lat_scanin	    [6] = rw_index_vld_reg_scanout 	     ;
assign cam_ctl_lat_scanin	    [5] = cam_ctl_lat_scanout	 	 [6];
assign cam_ctl_lat_scanin	    [58] = cam_ctl_lat_scanout	 	 [5];
assign cam_ctl_lat_scanin	 [60:59] = cam_ctl_lat_scanout	      [59:58];
assign cam_ctl_lat_scanin	    [37] = cam_ctl_lat_scanout	 	 [60];
assign cam_ctl_lat_scanin	 [56:38] = cam_ctl_lat_scanout	      [55:37];

assign page_size_mask_reg_scanin    [0] = cam_ctl_lat_scanout	         [56];

assign cam_ctl_lat_scanin           [21] = page_size_mask_reg_scanout    [0];
assign cam_ctl_lat_scanin	 [26:22] = cam_ctl_lat_scanout	      [25:21];

assign page_size_mask_reg_scanin    [1] = cam_ctl_lat_scanout	         [26];

assign cam_ctl_lat_scanin           [27] = page_size_mask_reg_scanout    [1];
assign cam_ctl_lat_scanin	 [29:28] = cam_ctl_lat_scanout	      [28:27];
assign cam_ctl_lat_scanin	    [31] = cam_ctl_lat_scanout	         [29];
assign cam_ctl_lat_scanin	 [33:32] = cam_ctl_lat_scanout	      [32:31];

assign page_size_mask_reg_scanin    [2] = cam_ctl_lat_scanout	         [33];

assign cam_ctl_lat_scanin           [34] = page_size_mask_reg_scanout    [2];
assign cam_ctl_lat_scanin	 [36:35] = cam_ctl_lat_scanout	      [35:34];
assign cam_ctl_lat_scanin	    [57] = cam_ctl_lat_scanout	 	 [36];
assign cam_ctl_lat_scanin	    [3] = cam_ctl_lat_scanout	 	 [57];
assign cam_ctl_lat_scanin	    [4] = cam_ctl_lat_scanout	 	 [3];
assign cam_ctl_lat_scanin	    [61] = cam_ctl_lat_scanout	 	 [4];
assign cam_ctl_lat_scanin	 [73:62] = cam_ctl_lat_scanout	      [72:61];
assign cam_ctl_lat_scanin	    [8] = cam_ctl_lat_scanout	 	 [73];
assign cam_ctl_lat_scanin	 [20:9] = cam_ctl_lat_scanout	      [19:8];

assign mm_debug_reg_scanin	    [3] = cam_ctl_lat_scanout	 	 [20];
assign mm_debug_reg_scanin	 [2:0] = mm_debug_reg_scanout	      [3:1];

assign cam_ctl_lat_scanin	    [7] = mm_debug_reg_scanout	 	 [0];

assign disable_clear_ubit_reg_scanin     = cam_ctl_lat_scanout	 	 [7];

assign cam_ctl_lat_scanin	    [30] = disable_clear_ubit_reg_scanout    ;
assign cam_ctl_lat_scanin	    [0] = cam_ctl_lat_scanout	 	 [30];
assign cam_ctl_lat_scanin	    [2] = cam_ctl_lat_scanout	 	 [0];
assign cam_ctl_lat_scanin	    [1] = cam_ctl_lat_scanout	 	 [2];

assign tlb_bypass_reg_scanin	         = cam_ctl_lat_scanout	 	 [1];

assign tlb_cam_hit_reg_scanin	    [2] = tlb_bypass_reg_scanout 	     ;
assign tlb_cam_hit_reg_scanin	    [0] = tlb_cam_hit_reg_scanout 	 [2];

assign tte_tag_out_reg_scanin	    [22] = tlb_cam_hit_reg_scanout 	 [0];

assign tte_u_bit_out_reg_scanin 	 = tte_tag_out_reg_scanout       [22];

assign tte_tag_out_reg_scanin	    [12] = tte_u_bit_out_reg_scanout 	     ;
assign tte_tag_out_reg_scanin	 [11:0] = tte_tag_out_reg_scanout    [12:1];
assign tte_tag_out_reg_scanin	    [65] = tte_tag_out_reg_scanout 	 [0];
assign tte_tag_out_reg_scanin	 [64:53] = tte_tag_out_reg_scanout    [65:54];
assign tte_tag_out_reg_scanin	    [49] = tte_tag_out_reg_scanout 	 [53];
assign tte_tag_out_reg_scanin       [28] = tte_tag_out_reg_scanout	 [49];
assign tte_tag_out_reg_scanin    [27:23] = tte_tag_out_reg_scanout    [28:24];
assign tte_tag_out_reg_scanin       [21] = tte_tag_out_reg_scanout       [23];
assign tte_tag_out_reg_scanin    [20:13] = tte_tag_out_reg_scanout    [21:14];
assign tte_tag_out_reg_scanin       [48] = tte_tag_out_reg_scanout       [13];
assign tte_tag_out_reg_scanin    [47:29] = tte_tag_out_reg_scanout    [48:30];
assign tte_tag_out_reg_scanin       [52] = tte_tag_out_reg_scanout       [29];
assign tte_tag_out_reg_scanin    [51:50] = tte_tag_out_reg_scanout    [52:51];

assign tte_data_out_reg_scanin      [0] = tte_tag_out_reg_scanout       [50];
assign tte_data_out_reg_scanin   [37:1] = tte_data_out_reg_scanout   [36:0];

assign cache_way_hit_reg_scanin     [0] = tte_data_out_reg_scanout      [37];
assign cache_way_hit_reg_scanin  [7:1] = cache_way_hit_reg_scanout  [6:0];

assign pa_reg_scanin                [0] = cache_way_hit_reg_scanout     [7];
assign pa_reg_scanin             [26:1] = pa_reg_scanout             [25:0];

assign tlb_cam_hit_reg_scanin       [1] = pa_reg_scanout                [26];

assign scan_out                          = tlb_cam_hit_reg_scanout       [1];
// Fullscan hookups end

`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
//
//


module n2_tlb_tl_64x59_cust_sram_msff_mo_macro__fs_1__width_74 (
  d, 
  scan_in, 
  l1clk, 
  and_clk, 
  siclk, 
  soclk, 
  mq, 
  mq_l, 
  scan_out, 
  q, 
  q_l);
input [73:0] d;
  input [73:0] scan_in;
input l1clk;
input and_clk;
input siclk;
input soclk;
output [73:0] mq;
output [73:0] mq_l;
  output [73:0] scan_out;
output [73:0] q;
output [73:0] q_l;


new_dlata #(74)  d0_0 (
.d(d[73:0]),
.si(scan_in[73:0]),
.so(scan_out[73:0]),
.l1clk(l1clk),
.and_clk(and_clk),
.siclk(siclk),
.soclk(soclk),
.q(q[73:0]),
.q_l(q_l[73:0]),
.mq(mq[73:0]),
.mq_l(mq_l[73:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   invert macro
//
//


module n2_tlb_tl_64x59_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_tlb_tl_64x59_cust_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;

  input [2:0] din;
  input l1clk;
  input [2:0] scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output [2:0] scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si(scan_in[2:0]),
.so(scan_out[2:0]),
.q(dout[2:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;

  input [1:0] din;
  input l1clk;
  input [1:0] scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output [1:0] scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si(scan_in[1:0]),
.so(scan_out[1:0]),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_38 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [37:0] fdin;

  input [37:0] din;
  input l1clk;
  input [37:0] scan_in;


  input siclk;
  input soclk;

  output [37:0] dout;
  output [37:0] scan_out;
assign fdin[37:0] = din[37:0];


dff #(38)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[37:0]),
.si(scan_in[37:0]),
.so(scan_out[37:0]),
.q(dout[37:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_mux_macro__mux_aope__ports_2__width_6 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [5:0] din0;
  input [5:0] din1;
  input sel0;
  output [5:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(6)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[5:0]),
  .in1(din1[5:0]),
.dout(dout[5:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_6 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [5:0] fdin;

  input [5:0] din;
  input l1clk;
  input [5:0] scan_in;


  input siclk;
  input soclk;

  output [5:0] dout;
  output [5:0] scan_out;
assign fdin[5:0] = din[5:0];


dff #(6)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[5:0]),
.si(scan_in[5:0]),
.so(scan_out[5:0]),
.q(dout[5:0])
);


endmodule


module n2_tlb_tl_64x59_array (
  l1clk, 
  disable_clear_ubit, 
  tlb_bypass, 
  tlb_wr_flopped, 
  tlb_rd_flopped, 
  rw_index, 
  tlb_cam, 
  tlb_cam_flopped, 
  demap, 
  demap_context, 
  demap_all, 
  demap_real, 
  tte_tag, 
  tte_tag_flopped, 
  tte_ubit, 
  tte_page_size_mask, 
  tte_data, 
  va, 
  tag_read_mux_control, 
  pa, 
  tlb_cam_hit, 
  context0_hit, 
  multiple_match, 
  rd_tte_data, 
  rd_tte_tag, 
  rd_tte_u_bit, 
  tlb_replacement_index) ;
wire [63:0] ram_wwl;
wire [63:0] ram_rwl;
wire [63:0] valid;
wire [63:0] used;


`define ENTRIES		64
`define INDEX		5

input		l1clk;
input		disable_clear_ubit;

input		tlb_bypass;
input		tlb_wr_flopped;
input		tlb_rd_flopped;
input	[`INDEX:0] rw_index;
input		tlb_cam;
input		tlb_cam_flopped;
input		demap;
input		demap_context;
input		demap_all;
input		demap_real;

input	[65:0]	tte_tag;
input	[65:0]	tte_tag_flopped;
input		tte_ubit;
input	[2:0]	tte_page_size_mask;
input	[37:0]	tte_data;
input	[12:11]	va;		// Incoming VA

input 		tag_read_mux_control;

output	[39:11]	pa;
output		tlb_cam_hit;
output		context0_hit;
output		multiple_match;
output	[37:0]	rd_tte_data;
output	[65:0]	rd_tte_tag;
output		rd_tte_u_bit;
output	[`INDEX:0] tlb_replacement_index;


`define VA_39 40
`define VA_28 29
`define VA_27 28
`define VA_22 23
`define VA_21 21
`define VA_16 16
`define VA_15 15 
`define VA_13 13


n2_tlb_tl_64x59_cam		cam(
  .l1clk(l1clk),
  .tlb_bypass(tlb_bypass),
  .tlb_wr_flopped(tlb_wr_flopped),
  .tlb_rd_flopped(tlb_rd_flopped),
  .rw_index(rw_index[5:0]),
  .tlb_cam(tlb_cam),
  .tlb_cam_flopped(tlb_cam_flopped),
  .demap(demap),
  .demap_context(demap_context),
  .demap_all(demap_all),
  .demap_real(demap_real),
  .tte_tag(tte_tag[65:0]),
  .tte_tag_flopped(tte_tag_flopped[65:0]),
  .tte_page_size_mask(tte_page_size_mask[2:0]),
  .tag_read_mux_control(tag_read_mux_control),
  .tlb_cam_hit(tlb_cam_hit),
  .context0_hit(context0_hit),
  .rd_tte_tag(rd_tte_tag[65:0]),
  .ram_wwl(ram_wwl[63:0]),
  .ram_rwl(ram_rwl[63:0]),
  .valid(valid[63:0]));

n2_tlb_tl_64x59_ram		ram(
	.va		({tte_tag_flopped[`VA_39:`VA_28],
			  tte_tag_flopped[`VA_27:`VA_22],
			  tte_tag_flopped[`VA_21:`VA_16],
			  tte_tag_flopped[`VA_15:`VA_13],
			  va[12:11]}),
  .l1clk(l1clk),
  .tlb_bypass(tlb_bypass),
  .tlb_cam_flopped(tlb_cam_flopped),
  .ram_wwl(ram_wwl[63:0]),
  .ram_rwl(ram_rwl[63:0]),
  .tte_data(tte_data[37:0]),
  .pa(pa[39:11]),
  .rd_tte_data(rd_tte_data[37:0])
);

n2_tlb_tl_64x59_multihit	multihit (
	.tlb_cam_mhit			(multiple_match		),
  .ram_rwl(ram_rwl[63:0]),
  .tlb_bypass(tlb_bypass)
);

n2_tlb_tl_64x59_ubit		ubit(
  .l1clk(l1clk),
  .disable_clear_ubit(disable_clear_ubit),
  .tlb_bypass(tlb_bypass),
  .ram_rwl(ram_rwl[63:0]),
  .ram_wwl(ram_wwl[63:0]),
  .tte_ubit(tte_ubit),
  .tlb_wr_flopped(tlb_wr_flopped),
  .tlb_rd_flopped(tlb_rd_flopped),
  .tlb_cam_flopped(tlb_cam_flopped),
  .used(used[63:0]),
  .rd_tte_u_bit(rd_tte_u_bit));

n2_tlb_tl_64x59_repl_index	repl_index(
  .l1clk(l1clk),
  .used(used[63:0]),
  .valid(valid[63:0]),
  .tlb_replacement_index(tlb_replacement_index[5:0]));


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule


`ifndef FPGA
module n2_tlb_tl_64x59_cam (
  l1clk, 
  tlb_bypass, 
  tlb_wr_flopped, 
  tlb_rd_flopped, 
  rw_index, 
  tlb_cam, 
  tlb_cam_flopped, 
  demap, 
  demap_context, 
  demap_all, 
  demap_real, 
  tte_tag, 
  tte_tag_flopped, 
  tte_page_size_mask, 
  tag_read_mux_control, 
  tlb_cam_hit, 
  context0_hit, 
  rd_tte_tag, 
  ram_wwl, 
  ram_rwl, 
  valid) ;
wire [6:0] rw_index_to_decode;
wire [127:0] decoded_index;
wire [127:64] decoded_index_unused;


`define ENTRIES		64
`define INDEX		5


input		l1clk;

input		tlb_bypass;
input		tlb_wr_flopped;
input		tlb_rd_flopped;
input	[`INDEX:0] rw_index;
input		tlb_cam;
input		tlb_cam_flopped;
input		demap;
input		demap_context;
input		demap_all;
input		demap_real;

input	[65:0]	tte_tag;
input	[65:0]	tte_tag_flopped;
input	[2:0]	tte_page_size_mask;

input 		tag_read_mux_control;


output		tlb_cam_hit;
output		context0_hit;
output	[65:0]	rd_tte_tag;
output	[`ENTRIES-1:0] ram_wwl;
output	[`ENTRIES-1:0] ram_rwl;
output	[`ENTRIES-1:0] valid;


`define CNTX1_HI 65
`define CNTX1_LO 53
`define PID_HI   52
`define PID_LO   50
`define REAL_BIT 49
`define VA_47    48
`define VA_28    29
`define VA_27    28
`define VA_22    23
`define TTE_VALID 22 
`define VA_21    21
`define VA_16    16
`define VA_15    15 
`define VA_13    13
`define CNTX0_HI 12
`define CNTX0_LO  0


//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------

// local signals

reg 	[12:0] 	context_a	[`ENTRIES-1:0];  // Contexts a and b are
reg 	[12:0] 	context_a_	[`ENTRIES-1:0];  // to be equal at all times
reg 	[12:0] 	context_b	[`ENTRIES-1:0];  // This is NOT context 0 and 1
reg 	[12:0] 	context_b_	[`ENTRIES-1:0];  // This is NOT primary/secondary
reg        	r_bit		[`ENTRIES-1:0];
reg        	r_bit_		[`ENTRIES-1:0];
reg     [47:28] va_47_28	[`ENTRIES-1:0];
reg     [47:28] va_47_28_	[`ENTRIES-1:0];
reg     [27:22] va_27_22	[`ENTRIES-1:0];
reg     [27:22] va_27_22_	[`ENTRIES-1:0];
reg     [21:16] va_21_16	[`ENTRIES-1:0];
reg     [21:16] va_21_16_	[`ENTRIES-1:0];
reg     [15:13] va_15_13	[`ENTRIES-1:0];
reg     [15:13] va_15_13_	[`ENTRIES-1:0];
reg	[2:0]	pid		[`ENTRIES-1:0];
reg	[2:0]	pid_		[`ENTRIES-1:0];
reg 	[`ENTRIES-1:0]	valid;
reg 	[`ENTRIES-1:0]	match_for_sat;
reg 			tlb_cam_hit;
reg 			context0_hit;

integer n;
reg [31:0] n_reg;

reg [`ENTRIES-1:0] va_47_28_match ;
reg [`ENTRIES-1:0] va_27_22_match ;
reg [`ENTRIES-1:0] va_21_16_match ;
reg [`ENTRIES-1:0] va_15_13_match ;
reg [`ENTRIES-1:0] pid_match      ;
reg [`ENTRIES-1:0] real_match     ;
reg [`ENTRIES-1:0] context0_match ;
reg [`ENTRIES-1:0] context1_match ;
reg [`ENTRIES-1:0] context_match  ;
reg [`ENTRIES-1:0] match          ;
reg [`ENTRIES-1:0] ram_wl         ;
reg [65:0] rd_tte_tag;
reg [12:0] a_xnor_tag;
reg [12:0] b_xnor_tag;

reg 	   demap_posedge_l1clk;


`ifndef NOINITMEM
///////////////////////////////////////
// Initialize the arrays.            //
///////////////////////////////////////
initial begin
	for (n = 0; n < `ENTRIES; n = n+1) begin
		context_a	[n] = {13 {1'b0}};
		context_a_	[n] = {13 {1'b1}};
		context_b	[n] = {13 {1'b0}};
		context_b_	[n] = {13 {1'b1}};
		r_bit		[n] = { 1 {1'b0}};
		r_bit_		[n] = { 1 {1'b1}};
		va_47_28	[n] = {20 {1'b0}};
		va_47_28_	[n] = {20 {1'b1}};
		va_27_22	[n] = { 6 {1'b0}};
		va_27_22_	[n] = { 6 {1'b1}};
		va_21_16	[n] = { 6 {1'b0}};
		va_21_16_	[n] = { 6 {1'b1}};
		va_15_13	[n] = { 3 {1'b0}};
		va_15_13_	[n] = { 3 {1'b1}};
		pid		[n] = { 3 {1'b0}};
		pid_		[n] = { 3 {1'b1}};
		valid		[n] = { 1 {1'b0}};
	end // for (n = 0; n < `ENTRIES; n = n+1)
end
`endif


///////////////////////////////////////////////////////////////
// CAM, read
///////////////////////////////////////////////////////////////
always @(posedge l1clk) begin

	demap_posedge_l1clk = demap;
	
	match[`ENTRIES-1:0] = {`ENTRIES {1'b0}};

	if (tlb_cam | demap) begin
		for (n = 0; n < `ENTRIES; n = n + 1) begin
			// Have to represent dual match line architecture...
			// LSB 2 bits of context must both match AND MSB 11 bits must not mismatch
			a_xnor_tag[12:0] =       (context_a	[n] &  tte_tag[`CNTX1_HI:`CNTX1_LO]) |
						 (context_a_	[n] & ~tte_tag[`CNTX1_HI:`CNTX1_LO]) ;
			b_xnor_tag[12:0] =       (context_b	[n] &  tte_tag[`CNTX0_HI:`CNTX0_LO]) |
						 (context_b_	[n] & ~tte_tag[`CNTX0_HI:`CNTX0_LO]) ;
			context1_match[n] = demap_all | demap_real | 
					    (& a_xnor_tag[1:0]) & 
					    (~(| {context_a	[n] & ~tte_tag[`CNTX1_HI:`CNTX1_LO] & 13'h1ffc,
						  context_a_	[n] &  tte_tag[`CNTX1_HI:`CNTX1_LO] & 13'h1ffc}));
			context0_match[n] = demap_all | demap_real |
					    (& b_xnor_tag[1:0]) & 
					    (~(| {context_b	[n] & ~tte_tag[`CNTX0_HI:`CNTX0_LO] & 13'h1ffc,
						  context_b_	[n] &  tte_tag[`CNTX0_HI:`CNTX0_LO] & 13'h1ffc}));
			pid_match[n]      = (~(| {pid		[n] & ~tte_tag[`PID_HI	:`PID_LO  ],
						  pid_		[n] &  tte_tag[`PID_HI	:`PID_LO  ]}));
			real_match[n]     = demap_all | 
					    (~(| {r_bit		[n] & ~tte_tag[`REAL_BIT	  ],
						  r_bit_	[n] &  tte_tag[`REAL_BIT	  ]}));
			va_47_28_match[n] = demap_all | demap_real | demap_context |  
					    (~(| {va_47_28	[n] & ~tte_tag[`VA_47	:`VA_28   ],
						  va_47_28_	[n] &  tte_tag[`VA_47	:`VA_28   ]}));
			va_27_22_match[n] = demap_all | demap_real | demap_context |  
					    (~(| {va_27_22	[n] & ~tte_tag[`VA_27	:`VA_22   ],
						  va_27_22_	[n] &  tte_tag[`VA_27	:`VA_22   ]}));
			va_21_16_match[n] = demap_all | demap_real | demap_context |  
					    (~(| {va_21_16	[n] & ~tte_tag[`VA_21	:`VA_16   ],
						  va_21_16_	[n] &  tte_tag[`VA_21	:`VA_16   ]}));
			va_15_13_match[n] = demap_all | demap_real | demap_context |  
					    (~(| {va_15_13	[n] & ~tte_tag[`VA_15	:`VA_13   ],
						  va_15_13_	[n] &  tte_tag[`VA_15	:`VA_13   ]}));

			context_match[n]  = context0_match[n] | context1_match[n];
			
			match[n] = va_47_28_match[n] & va_27_22_match[n] & va_21_16_match[n] & 
				   va_15_13_match[n] & pid_match[n] & real_match[n] & context_match[n] &
				   valid[n];

		end // for (n = 0; n < `ENTRIES; n = n + 1)
		
		
	end // if (tlb_cam | demap)
	

	ram_wl[`ENTRIES-1:0] <= match[`ENTRIES-1:0];
	
end // always @ (posedge l1clk)


///////////////////////////////////////////////////////////////
// Demap, Write, Read
///////////////////////////////////////////////////////////////
always @(negedge l1clk) begin

	// Demap
	if (demap) begin	
		for (n = 0; n < `ENTRIES; n = n + 1) begin
			if (match[n]) begin
				valid[n] <= 1'b0;
			end
		end
	end // if (demap)	

	// Write
	if (tlb_wr_flopped) begin

		for (n = 0; n < `ENTRIES; n = n + 1) begin
			if (ram_wwl[n]) begin
				context_a	[n] <=( tte_tag_flopped[`CNTX1_HI:`CNTX1_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}};
				context_a_	[n] <=(~tte_tag_flopped[`CNTX1_HI:`CNTX1_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}};
				pid		[n] <=  tte_tag_flopped[`PID_HI  :`PID_LO  ];
				pid_		[n] <= ~tte_tag_flopped[`PID_HI  :`PID_LO  ];
				r_bit		[n] <=  tte_tag_flopped[`REAL_BIT          ];
				r_bit_		[n] <= ~tte_tag_flopped[`REAL_BIT          ];
				va_47_28	[n] <=  tte_tag_flopped[`VA_47   :`VA_28   ];
				va_47_28_	[n] <= ~tte_tag_flopped[`VA_47   :`VA_28   ];
				va_27_22	[n] <=  tte_tag_flopped[`VA_27   :`VA_22   ] & { 6 {~tte_page_size_mask[2]}};
				va_27_22_	[n] <= ~tte_tag_flopped[`VA_27   :`VA_22   ] & { 6 {~tte_page_size_mask[2]}};
				va_21_16	[n] <=  tte_tag_flopped[`VA_21   :`VA_16   ] & { 6 {~tte_page_size_mask[1]}};
				va_21_16_	[n] <= ~tte_tag_flopped[`VA_21   :`VA_16   ] & { 6 {~tte_page_size_mask[1]}};
				va_15_13	[n] <=  tte_tag_flopped[`VA_15   :`VA_13   ] & { 3 {~tte_page_size_mask[0]}};
				va_15_13_	[n] <= ~tte_tag_flopped[`VA_15   :`VA_13   ] & { 3 {~tte_page_size_mask[0]}};
				context_b	[n] <=( tte_tag_flopped[`CNTX0_HI:`CNTX0_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}};
				context_b_	[n] <=(~tte_tag_flopped[`CNTX0_HI:`CNTX0_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}};
				valid 		[n] <=  tte_tag_flopped[`TTE_VALID         ];

				
			end // if (ram_wwl[n])
		end // for (n = 0; n < `ENTRIES; n = n + 1)
		
	end // if (tlb_wr_flopped)

	// Read	
	if (tlb_rd_flopped) begin
		if (tag_read_mux_control) begin
			rd_tte_tag[`CNTX1_HI:`CNTX1_LO] <= context_a_	[rw_index[`INDEX:0]];
			rd_tte_tag[`PID_HI  :`PID_LO  ] <= pid_		[rw_index[`INDEX:0]];
			rd_tte_tag[`REAL_BIT          ] <= r_bit_	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_47   :`VA_28   ] <= va_47_28_	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_27   :`VA_22   ] <= va_27_22_	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_21   :`VA_16   ] <= va_21_16_	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_15   :`VA_13   ] <= va_15_13_	[rw_index[`INDEX:0]];
			rd_tte_tag[`CNTX0_HI:`CNTX0_LO] <= context_b_	[rw_index[`INDEX:0]];
		end // if (tag_read_mux_control)
		else begin
			rd_tte_tag[`CNTX1_HI:`CNTX1_LO] <= context_a	[rw_index[`INDEX:0]];
			rd_tte_tag[`PID_HI  :`PID_LO  ] <= pid		[rw_index[`INDEX:0]];
			rd_tte_tag[`REAL_BIT          ] <= r_bit	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_47   :`VA_28   ] <= va_47_28	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_27   :`VA_22   ] <= va_27_22	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_21   :`VA_16   ] <= va_21_16	[rw_index[`INDEX:0]];
			rd_tte_tag[`VA_15   :`VA_13   ] <= va_15_13	[rw_index[`INDEX:0]];
			rd_tte_tag[`CNTX0_HI:`CNTX0_LO] <= context_b	[rw_index[`INDEX:0]];
		end // else: !if(tag_read_mux_control)
		rd_tte_tag[`TTE_VALID         ] <= valid	[rw_index[`INDEX:0]];
	end // if (tlb_rd
	else begin
	        rd_tte_tag[65:0] <= {66 {1'b0}} ;
	end // else: !if(tlb_rd)

end // always @ (negedge l1clk)


///////////////////////////////////////////////////////////////
// Output assignments
///////////////////////////////////////////////////////////////
// Have to hold them to next clock edge

// Read and write address decode
assign rw_index_to_decode[6:0] =
	{1'b0,
//	{rw_index[6],
	rw_index[5:0]};

assign decoded_index[127:0] = 
	{(rw_index_to_decode[6:0] == 7'h7f),
	 (rw_index_to_decode[6:0] == 7'h7e),
	 (rw_index_to_decode[6:0] == 7'h7d),
	 (rw_index_to_decode[6:0] == 7'h7c),
	 (rw_index_to_decode[6:0] == 7'h7b),
	 (rw_index_to_decode[6:0] == 7'h7a),
	 (rw_index_to_decode[6:0] == 7'h79),
	 (rw_index_to_decode[6:0] == 7'h78),
	 (rw_index_to_decode[6:0] == 7'h77),
	 (rw_index_to_decode[6:0] == 7'h76),
	 (rw_index_to_decode[6:0] == 7'h75),
	 (rw_index_to_decode[6:0] == 7'h74),
	 (rw_index_to_decode[6:0] == 7'h73),
	 (rw_index_to_decode[6:0] == 7'h72),
	 (rw_index_to_decode[6:0] == 7'h71),
	 (rw_index_to_decode[6:0] == 7'h70),
	 (rw_index_to_decode[6:0] == 7'h6f),
	 (rw_index_to_decode[6:0] == 7'h6e),
	 (rw_index_to_decode[6:0] == 7'h6d),
	 (rw_index_to_decode[6:0] == 7'h6c),
	 (rw_index_to_decode[6:0] == 7'h6b),
	 (rw_index_to_decode[6:0] == 7'h6a),
	 (rw_index_to_decode[6:0] == 7'h69),
	 (rw_index_to_decode[6:0] == 7'h68),
	 (rw_index_to_decode[6:0] == 7'h67),
	 (rw_index_to_decode[6:0] == 7'h66),
	 (rw_index_to_decode[6:0] == 7'h65),
	 (rw_index_to_decode[6:0] == 7'h64),
	 (rw_index_to_decode[6:0] == 7'h63),
	 (rw_index_to_decode[6:0] == 7'h62),
	 (rw_index_to_decode[6:0] == 7'h61),
	 (rw_index_to_decode[6:0] == 7'h60),
	 (rw_index_to_decode[6:0] == 7'h5f),
	 (rw_index_to_decode[6:0] == 7'h5e),
	 (rw_index_to_decode[6:0] == 7'h5d),
	 (rw_index_to_decode[6:0] == 7'h5c),
	 (rw_index_to_decode[6:0] == 7'h5b),
	 (rw_index_to_decode[6:0] == 7'h5a),
	 (rw_index_to_decode[6:0] == 7'h59),
	 (rw_index_to_decode[6:0] == 7'h58),
	 (rw_index_to_decode[6:0] == 7'h57),
	 (rw_index_to_decode[6:0] == 7'h56),
	 (rw_index_to_decode[6:0] == 7'h55),
	 (rw_index_to_decode[6:0] == 7'h54),
	 (rw_index_to_decode[6:0] == 7'h53),
	 (rw_index_to_decode[6:0] == 7'h52),
	 (rw_index_to_decode[6:0] == 7'h51),
	 (rw_index_to_decode[6:0] == 7'h50),
	 (rw_index_to_decode[6:0] == 7'h4f),
	 (rw_index_to_decode[6:0] == 7'h4e),
	 (rw_index_to_decode[6:0] == 7'h4d),
	 (rw_index_to_decode[6:0] == 7'h4c),
	 (rw_index_to_decode[6:0] == 7'h4b),
	 (rw_index_to_decode[6:0] == 7'h4a),
	 (rw_index_to_decode[6:0] == 7'h49),
	 (rw_index_to_decode[6:0] == 7'h48),
	 (rw_index_to_decode[6:0] == 7'h47),
	 (rw_index_to_decode[6:0] == 7'h46),
	 (rw_index_to_decode[6:0] == 7'h45),
	 (rw_index_to_decode[6:0] == 7'h44),
	 (rw_index_to_decode[6:0] == 7'h43),
	 (rw_index_to_decode[6:0] == 7'h42),
	 (rw_index_to_decode[6:0] == 7'h41),
	 (rw_index_to_decode[6:0] == 7'h40),
	 (rw_index_to_decode[6:0] == 7'h3f),
	 (rw_index_to_decode[6:0] == 7'h3e),
	 (rw_index_to_decode[6:0] == 7'h3d),
	 (rw_index_to_decode[6:0] == 7'h3c),
	 (rw_index_to_decode[6:0] == 7'h3b),
	 (rw_index_to_decode[6:0] == 7'h3a),
	 (rw_index_to_decode[6:0] == 7'h39),
	 (rw_index_to_decode[6:0] == 7'h38),
	 (rw_index_to_decode[6:0] == 7'h37),
	 (rw_index_to_decode[6:0] == 7'h36),
	 (rw_index_to_decode[6:0] == 7'h35),
	 (rw_index_to_decode[6:0] == 7'h34),
	 (rw_index_to_decode[6:0] == 7'h33),
	 (rw_index_to_decode[6:0] == 7'h32),
	 (rw_index_to_decode[6:0] == 7'h31),
	 (rw_index_to_decode[6:0] == 7'h30),
	 (rw_index_to_decode[6:0] == 7'h2f),
	 (rw_index_to_decode[6:0] == 7'h2e),
	 (rw_index_to_decode[6:0] == 7'h2d),
	 (rw_index_to_decode[6:0] == 7'h2c),
	 (rw_index_to_decode[6:0] == 7'h2b),
	 (rw_index_to_decode[6:0] == 7'h2a),
	 (rw_index_to_decode[6:0] == 7'h29),
	 (rw_index_to_decode[6:0] == 7'h28),
	 (rw_index_to_decode[6:0] == 7'h27),
	 (rw_index_to_decode[6:0] == 7'h26),
	 (rw_index_to_decode[6:0] == 7'h25),
	 (rw_index_to_decode[6:0] == 7'h24),
	 (rw_index_to_decode[6:0] == 7'h23),
	 (rw_index_to_decode[6:0] == 7'h22),
	 (rw_index_to_decode[6:0] == 7'h21),
	 (rw_index_to_decode[6:0] == 7'h20),
	 (rw_index_to_decode[6:0] == 7'h1f),
	 (rw_index_to_decode[6:0] == 7'h1e),
	 (rw_index_to_decode[6:0] == 7'h1d),
	 (rw_index_to_decode[6:0] == 7'h1c),
	 (rw_index_to_decode[6:0] == 7'h1b),
	 (rw_index_to_decode[6:0] == 7'h1a),
	 (rw_index_to_decode[6:0] == 7'h19),
	 (rw_index_to_decode[6:0] == 7'h18),
	 (rw_index_to_decode[6:0] == 7'h17),
	 (rw_index_to_decode[6:0] == 7'h16),
	 (rw_index_to_decode[6:0] == 7'h15),
	 (rw_index_to_decode[6:0] == 7'h14),
	 (rw_index_to_decode[6:0] == 7'h13),
	 (rw_index_to_decode[6:0] == 7'h12),
	 (rw_index_to_decode[6:0] == 7'h11),
	 (rw_index_to_decode[6:0] == 7'h10),
	 (rw_index_to_decode[6:0] == 7'h0f),
	 (rw_index_to_decode[6:0] == 7'h0e),
	 (rw_index_to_decode[6:0] == 7'h0d),
	 (rw_index_to_decode[6:0] == 7'h0c),
	 (rw_index_to_decode[6:0] == 7'h0b),
	 (rw_index_to_decode[6:0] == 7'h0a),
	 (rw_index_to_decode[6:0] == 7'h09),
	 (rw_index_to_decode[6:0] == 7'h08),
	 (rw_index_to_decode[6:0] == 7'h07),
	 (rw_index_to_decode[6:0] == 7'h06),
	 (rw_index_to_decode[6:0] == 7'h05),
	 (rw_index_to_decode[6:0] == 7'h04),
	 (rw_index_to_decode[6:0] == 7'h03),
	 (rw_index_to_decode[6:0] == 7'h02),
	 (rw_index_to_decode[6:0] == 7'h01),
	 (rw_index_to_decode[6:0] == 7'h00)};

assign decoded_index_unused[127:64] = decoded_index[127:64];

always @(negedge l1clk) begin
	match_for_sat[`ENTRIES-1:0] <= match[`ENTRIES-1:0]; // For MMU SAT
	tlb_cam_hit <= (| match[`ENTRIES-1:0]) | tlb_bypass | ~tlb_cam;
	context0_hit <= (|(match[`ENTRIES-1:0] & context0_match[`ENTRIES-1:0])) & ~demap_posedge_l1clk;
end // always @ (negedge l1clk)

assign ram_wwl[`ENTRIES-1:0] = 
       decoded_index[`ENTRIES-1:0] & {`ENTRIES {tlb_wr_flopped}};

assign ram_rwl[`ENTRIES-1:0] = 
       (decoded_index[`ENTRIES-1:0] & {`ENTRIES {tlb_rd_flopped }}) |
       (ram_wl       [`ENTRIES-1:0] & {`ENTRIES {tlb_cam_flopped}});


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule
`endif // `ifndef FPGA

`ifdef FPGA
module n2_tlb_tl_64x59_cam(l1clk, tlb_bypass, tlb_wr_flopped, tlb_rd_flopped, 
	rw_index, tlb_cam, tlb_cam_flopped, demap, demap_context, demap_all, 
	demap_real, tte_tag, tte_tag_flopped, tte_page_size_mask, 
	tag_read_mux_control, tlb_cam_hit, context0_hit, rd_tte_tag, ram_wwl, 
	ram_rwl, valid);

	input			l1clk;
	input			tlb_bypass;
	input			tlb_wr_flopped;
	input			tlb_rd_flopped;
	input	[5:0]		rw_index;
	input			tlb_cam;
	input			tlb_cam_flopped;
	input			demap;
	input			demap_context;
	input			demap_all;
	input			demap_real;
	input	[65:0]		tte_tag;
	input	[65:0]		tte_tag_flopped;
	input	[2:0]		tte_page_size_mask;
	input			tag_read_mux_control;
	output			tlb_cam_hit;
	output			context0_hit;
	output	[65:0]		rd_tte_tag;
	output	[(64 - 1):0]	ram_wwl;
	output	[(64 - 1):0]	ram_rwl;
	output	[(64 - 1):0]	valid;

	wire	[6:0]		rw_index_to_decode;
	wire	[127:0]		decoded_index;
	wire	[127:64]	decoded_index_unused;

	reg	[12:0]		context_a[(64 - 1):0];
	reg	[12:0]		context_a_[(64 - 1):0];
	reg	[12:0]		context_b[(64 - 1):0];
	reg	[12:0]		context_b_[(64 - 1):0];
	reg			r_bit[(64 - 1):0];
	reg			r_bit_[(64 - 1):0];
	reg	[47:28]		va_47_28[(64 - 1):0];
	reg	[47:28]		va_47_28_[(64 - 1):0];
	reg	[27:22]		va_27_22[(64 - 1):0];
	reg	[27:22]		va_27_22_[(64 - 1):0];
	reg	[21:16]		va_21_16[(64 - 1):0];
	reg	[21:16]		va_21_16_[(64 - 1):0];
	reg	[15:13]		va_15_13[(64 - 1):0];
	reg	[15:13]		va_15_13_[(64 - 1):0];
	reg	[2:0]		pid[(64 - 1):0];
	reg	[2:0]		pid_[(64 - 1):0];
	reg	[(64 - 1):0]	match_for_sat;
	reg			tlb_cam_hit;
	reg			context0_hit;
	integer			n;
	reg	[31:0]		n_reg;
	reg	[(64 - 1):0]	va_47_28_match;
	reg	[(64 - 1):0]	va_27_22_match;
	reg	[(64 - 1):0]	va_21_16_match;
	reg	[(64 - 1):0]	va_15_13_match;
	reg	[(64 - 1):0]	pid_match;
	reg	[(64 - 1):0]	real_match;
	reg	[(64 - 1):0]	context0_match;
	reg	[(64 - 1):0]	context1_match;
	reg	[(64 - 1):0]	context_match;
	reg	[(64 - 1):0]	match;
	reg	[(64 - 1):0]	ram_wl;
	reg	[65:0]		rd_tte_tag;
	reg	[(64 - 1):0]	valid;
	reg	[12:0]		a_xnor_tag;
	reg	[12:0]		b_xnor_tag;
	reg			demap_posedge_l1clk;
	supply0			vss;
	supply1			vdd;

	assign rw_index_to_decode[6:0] = {1'b0, rw_index[5:0]};
	assign decoded_index[127:0] = {(rw_index_to_decode[6:0] == 7'b1111111), 
		(rw_index_to_decode[6:0] == 7'h7e), (rw_index_to_decode[6:0] ==
		7'h7d), (rw_index_to_decode[6:0] == 7'h7c), 
		(rw_index_to_decode[6:0] == 7'h7b), (rw_index_to_decode[6:0] ==
		7'h7a), (rw_index_to_decode[6:0] == 7'h79), 
		(rw_index_to_decode[6:0] == 7'h78), (rw_index_to_decode[6:0] ==
		7'h77), (rw_index_to_decode[6:0] == 7'h76), 
		(rw_index_to_decode[6:0] == 7'h75), (rw_index_to_decode[6:0] ==
		7'h74), (rw_index_to_decode[6:0] == 7'h73), 
		(rw_index_to_decode[6:0] == 7'h72), (rw_index_to_decode[6:0] ==
		7'h71), (rw_index_to_decode[6:0] == 7'h70), 
		(rw_index_to_decode[6:0] == 7'h6f), (rw_index_to_decode[6:0] ==
		7'h6e), (rw_index_to_decode[6:0] == 7'h6d), 
		(rw_index_to_decode[6:0] == 7'h6c), (rw_index_to_decode[6:0] ==
		7'h6b), (rw_index_to_decode[6:0] == 7'h6a), 
		(rw_index_to_decode[6:0] == 7'h69), (rw_index_to_decode[6:0] ==
		7'h68), (rw_index_to_decode[6:0] == 7'h67), 
		(rw_index_to_decode[6:0] == 7'h66), (rw_index_to_decode[6:0] ==
		7'h65), (rw_index_to_decode[6:0] == 7'h64), 
		(rw_index_to_decode[6:0] == 7'h63), (rw_index_to_decode[6:0] ==
		7'h62), (rw_index_to_decode[6:0] == 7'h61), 
		(rw_index_to_decode[6:0] == 7'h60), (rw_index_to_decode[6:0] ==
		7'h5f), (rw_index_to_decode[6:0] == 7'h5e), 
		(rw_index_to_decode[6:0] == 7'h5d), (rw_index_to_decode[6:0] ==
		7'h5c), (rw_index_to_decode[6:0] == 7'h5b), 
		(rw_index_to_decode[6:0] == 7'h5a), (rw_index_to_decode[6:0] ==
		7'h59), (rw_index_to_decode[6:0] == 7'h58), 
		(rw_index_to_decode[6:0] == 7'h57), (rw_index_to_decode[6:0] ==
		7'h56), (rw_index_to_decode[6:0] == 7'h55), 
		(rw_index_to_decode[6:0] == 7'h54), (rw_index_to_decode[6:0] ==
		7'h53), (rw_index_to_decode[6:0] == 7'h52), 
		(rw_index_to_decode[6:0] == 7'h51), (rw_index_to_decode[6:0] ==
		7'h50), (rw_index_to_decode[6:0] == 7'h4f), 
		(rw_index_to_decode[6:0] == 7'h4e), (rw_index_to_decode[6:0] ==
		7'h4d), (rw_index_to_decode[6:0] == 7'h4c), 
		(rw_index_to_decode[6:0] == 7'h4b), (rw_index_to_decode[6:0] ==
		7'h4a), (rw_index_to_decode[6:0] == 7'h49), 
		(rw_index_to_decode[6:0] == 7'h48), (rw_index_to_decode[6:0] ==
		7'h47), (rw_index_to_decode[6:0] == 7'h46), 
		(rw_index_to_decode[6:0] == 7'h45), (rw_index_to_decode[6:0] ==
		7'h44), (rw_index_to_decode[6:0] == 7'h43), 
		(rw_index_to_decode[6:0] == 7'h42), (rw_index_to_decode[6:0] ==
		7'h41), (rw_index_to_decode[6:0] == 7'h40), 
		(rw_index_to_decode[6:0] == 7'b0111111), 
		(rw_index_to_decode[6:0] == 7'h3e), (rw_index_to_decode[6:0] ==
		7'h3d), (rw_index_to_decode[6:0] == 7'h3c), 
		(rw_index_to_decode[6:0] == 7'h3b), (rw_index_to_decode[6:0] ==
		7'h3a), (rw_index_to_decode[6:0] == 7'h39), 
		(rw_index_to_decode[6:0] == 7'h38), (rw_index_to_decode[6:0] ==
		7'h37), (rw_index_to_decode[6:0] == 7'h36), 
		(rw_index_to_decode[6:0] == 7'h35), (rw_index_to_decode[6:0] ==
		7'h34), (rw_index_to_decode[6:0] == 7'h33), 
		(rw_index_to_decode[6:0] == 7'h32), (rw_index_to_decode[6:0] ==
		7'h31), (rw_index_to_decode[6:0] == 7'h30), 
		(rw_index_to_decode[6:0] == 7'h2f), (rw_index_to_decode[6:0] ==
		7'h2e), (rw_index_to_decode[6:0] == 7'h2d), 
		(rw_index_to_decode[6:0] == 7'h2c), (rw_index_to_decode[6:0] ==
		7'h2b), (rw_index_to_decode[6:0] == 7'h2a), 
		(rw_index_to_decode[6:0] == 7'h29), (rw_index_to_decode[6:0] ==
		7'h28), (rw_index_to_decode[6:0] == 7'h27), 
		(rw_index_to_decode[6:0] == 7'h26), (rw_index_to_decode[6:0] ==
		7'h25), (rw_index_to_decode[6:0] == 7'h24), 
		(rw_index_to_decode[6:0] == 7'h23), (rw_index_to_decode[6:0] ==
		7'h22), (rw_index_to_decode[6:0] == 7'h21), 
		(rw_index_to_decode[6:0] == 7'h20), (rw_index_to_decode[6:0] ==
		7'h1f), (rw_index_to_decode[6:0] == 7'h1e), 
		(rw_index_to_decode[6:0] == 7'h1d), (rw_index_to_decode[6:0] ==
		7'h1c), (rw_index_to_decode[6:0] == 7'h1b), 
		(rw_index_to_decode[6:0] == 7'h1a), (rw_index_to_decode[6:0] ==
		7'h19), (rw_index_to_decode[6:0] == 7'h18), 
		(rw_index_to_decode[6:0] == 7'h17), (rw_index_to_decode[6:0] ==
		7'h16), (rw_index_to_decode[6:0] == 7'h15), 
		(rw_index_to_decode[6:0] == 7'h14), (rw_index_to_decode[6:0] ==
		7'h13), (rw_index_to_decode[6:0] == 7'h12), 
		(rw_index_to_decode[6:0] == 7'h11), (rw_index_to_decode[6:0] ==
		7'h10), (rw_index_to_decode[6:0] == 7'h0f), 
		(rw_index_to_decode[6:0] == 7'h0e), (rw_index_to_decode[6:0] ==
		7'h0d), (rw_index_to_decode[6:0] == 7'h0c), 
		(rw_index_to_decode[6:0] == 7'h0b), (rw_index_to_decode[6:0] ==
		7'h0a), (rw_index_to_decode[6:0] == 7'h09), 
		(rw_index_to_decode[6:0] == 7'h08), (rw_index_to_decode[6:0] ==
		7'h07), (rw_index_to_decode[6:0] == 7'h06), 
		(rw_index_to_decode[6:0] == 7'h05), (rw_index_to_decode[6:0] ==
		7'h04), (rw_index_to_decode[6:0] == 7'h03), 
		(rw_index_to_decode[6:0] == 7'b0000010), 
		(rw_index_to_decode[6:0] == 7'b1), (rw_index_to_decode[6:0] ==
		7'b0)};
	assign decoded_index_unused[127:64] = decoded_index[127:64];
	assign ram_wwl[(64 - 1):0] = (decoded_index[(64 - 1):0] & {64 {
		tlb_wr_flopped}});
	assign ram_rwl[(64 - 1):0] = ((decoded_index[(64 - 1):0] & {64 {
		tlb_rd_flopped}}) | (ram_wl[(64 - 1):0] & {64 {tlb_cam_flopped}}
		));

	initial begin
	  for (n = 0; (n < 64); n = (n + 1)) begin
	    context_a[n] = {13 {1'b0}};
	    context_a_[n] = {13 {1'b1}};
	    context_b[n] = {13 {1'b0}};
	    context_b_[n] = {13 {1'b1}};
	    r_bit[n] = {1 {1'b0}};
	    r_bit_[n] = {1 {1'b1}};
	    va_47_28[n] = {20 {1'b0}};
	    va_47_28_[n] = {20 {1'b1}};
	    va_27_22[n] = {6 {1'b0}};
	    va_27_22_[n] = {6 {1'b1}};
	    va_21_16[n] = {6 {1'b0}};
	    va_21_16_[n] = {6 {1'b1}};
	    va_15_13[n] = {3 {1'b0}};
	    va_15_13_[n] = {3 {1'b1}};
	    pid[n] = {3 {1'b0}};
	    pid_[n] = {3 {1'b1}};
	    valid[n] = {1 {1'b0}};
	  end
	end
	always @(posedge l1clk) begin
	  demap_posedge_l1clk = demap;
	  match[(64 - 1):0] = {64 {1'b0}};
	  if (tlb_cam | demap) begin
	    for (n = 0; (n < 64); n = (n + 1)) begin
	      a_xnor_tag[12:0] = ((context_a[n] & tte_tag[65:53]) | (
		      context_a_[n] & (~tte_tag[65:53])));
	      b_xnor_tag[12:0] = ((context_b[n] & tte_tag[12:0]) | (
		      context_b_[n] & (~tte_tag[12:0])));
	      context1_match[n] = ((demap_all | demap_real) | ((&a_xnor_tag[1:0]
		      ) & (~(|{((context_a[n] & (~tte_tag[65:53])) & 13'h1ffc), 
		      ((context_a_[n] & tte_tag[65:53]) & 13'h1ffc)}))));
	      context0_match[n] = ((demap_all | demap_real) | ((&b_xnor_tag[1:0]
		      ) & (~(|{((context_b[n] & (~tte_tag[12:0])) & 13'h1ffc), 
		      ((context_b_[n] & tte_tag[12:0]) & 13'h1ffc)}))));
	      pid_match[n] = (~(|{(pid[n] & (~tte_tag[52:50])), (pid_[n] &
		      tte_tag[52:50])}));
	      real_match[n] = (demap_all | (~(|{(r_bit[n] & (~tte_tag[49])), 
		      (r_bit_[n] & tte_tag[49])})));
	      va_47_28_match[n] = (((demap_all | demap_real) | demap_context) | 
		      (~(|{(va_47_28[n] & (~tte_tag[48:29])), (va_47_28_[n] &
		      tte_tag[48:29])})));
	      va_27_22_match[n] = (((demap_all | demap_real) | demap_context) | 
		      (~(|{(va_27_22[n] & (~tte_tag[28:23])), (va_27_22_[n] &
		      tte_tag[28:23])})));
	      va_21_16_match[n] = (((demap_all | demap_real) | demap_context) | 
		      (~(|{(va_21_16[n] & (~tte_tag[21:16])), (va_21_16_[n] &
		      tte_tag[21:16])})));
	      va_15_13_match[n] = (((demap_all | demap_real) | demap_context) | 
		      (~(|{(va_15_13[n] & (~tte_tag[15:13])), (va_15_13_[n] &
		      tte_tag[15:13])})));
	      context_match[n] = (context0_match[n] | context1_match[n]);
	      match[n] = (((((((va_47_28_match[n] & va_27_22_match[n]) & 
		      va_21_16_match[n]) & va_15_13_match[n]) & pid_match[n]) & 
		      real_match[n]) & context_match[n]) & valid[n]);
	    end
	  end
	  ram_wl[(64 - 1):0] <= match[(64 - 1):0];
	end
	always @(negedge l1clk) begin
	  if (demap) begin
	    for (n = 0; (n < 64); n = (n + 1)) begin
	      if (match[n]) begin
		valid[n] <= 1'b0;
	      end
	    end
	  end
	  if (tlb_wr_flopped) begin
	    for (n = 0; (n < 64); n = (n + 1)) begin
	      if (ram_wwl[n]) begin
		context_a[n] <= ((tte_tag_flopped[65:53] & {13 {
			(~tte_tag_flopped[49])}}) | {11'b0, {2
			{tte_tag_flopped[49]}}});
		context_a_[n] <= (((~tte_tag_flopped[65:53]) & {13 {
			(~tte_tag_flopped[49])}}) | {11'b0, {2
			{tte_tag_flopped[49]}}});
		pid[n] <= tte_tag_flopped[52:50];
		pid_[n] <= (~tte_tag_flopped[52:50]);
		r_bit[n] <= tte_tag_flopped[49];
		r_bit_[n] <= (~tte_tag_flopped[49]);
		va_47_28[n] <= tte_tag_flopped[48:29];
		va_47_28_[n] <= (~tte_tag_flopped[48:29]);
		va_27_22[n] <= (tte_tag_flopped[28:23] & {6 {
			(~tte_page_size_mask[2])}});
		va_27_22_[n] <= ((~tte_tag_flopped[28:23]) & {6 {
			(~tte_page_size_mask[2])}});
		va_21_16[n] <= (tte_tag_flopped[21:16] & {6 {
			(~tte_page_size_mask[1])}});
		va_21_16_[n] <= ((~tte_tag_flopped[21:16]) & {6 {
			(~tte_page_size_mask[1])}});
		va_15_13[n] <= (tte_tag_flopped[15:13] & {3 {
			(~tte_page_size_mask[0])}});
		va_15_13_[n] <= ((~tte_tag_flopped[15:13]) & {3 {
			(~tte_page_size_mask[0])}});
		context_b[n] <= ((tte_tag_flopped[12:0] & {13 {
			(~tte_tag_flopped[49])}}) | {11'b0, {2
			{tte_tag_flopped[49]}}});
		context_b_[n] <= (((~tte_tag_flopped[12:0]) & {13 {
			(~tte_tag_flopped[49])}}) | {11'b0, {2
			{tte_tag_flopped[49]}}});
		valid[n] <= tte_tag_flopped[22];
	      end
	    end
	  end
	  if (tlb_rd_flopped) begin
	    if (tag_read_mux_control) begin
	      rd_tte_tag[65:53] <= context_a_[rw_index[5:0]];
	      rd_tte_tag[52:50] <= pid_[rw_index[5:0]];
	      rd_tte_tag[49] <= r_bit_[rw_index[5:0]];
	      rd_tte_tag[48:29] <= va_47_28_[rw_index[5:0]];
	      rd_tte_tag[28:23] <= va_27_22_[rw_index[5:0]];
	      rd_tte_tag[21:16] <= va_21_16_[rw_index[5:0]];
	      rd_tte_tag[15:13] <= va_15_13_[rw_index[5:0]];
	      rd_tte_tag[12:0] <= context_b_[rw_index[5:0]];
	    end
	    else
	      begin
		rd_tte_tag[65:53] <= context_a[rw_index[5:0]];
		rd_tte_tag[52:50] <= pid[rw_index[5:0]];
		rd_tte_tag[49] <= r_bit[rw_index[5:0]];
		rd_tte_tag[48:29] <= va_47_28[rw_index[5:0]];
		rd_tte_tag[28:23] <= va_27_22[rw_index[5:0]];
		rd_tte_tag[21:16] <= va_21_16[rw_index[5:0]];
		rd_tte_tag[15:13] <= va_15_13[rw_index[5:0]];
		rd_tte_tag[12:0] <= context_b[rw_index[5:0]];
	      end
	    rd_tte_tag[22] <= valid[rw_index[5:0]];
	  end
	  else
	    begin
	      rd_tte_tag[65:0] <= {66 {1'b0}};
	    end
	end
	always @(negedge l1clk) begin
	  match_for_sat[(64 - 1):0] <= match[(64 - 1):0];
	  tlb_cam_hit <= (((|match[(64 - 1):0]) | tlb_bypass) | (~tlb_cam));
	  context0_hit <= ((|(match[(64 - 1):0] & context0_match[(64 - 1):0])) &
		  (~demap_posedge_l1clk));
	end
endmodule

`endif // `ifdef FPGA


`ifndef FPGA
module n2_tlb_tl_64x59_ram (
  l1clk, 
  tlb_bypass, 
  tlb_cam_flopped, 
  ram_wwl, 
  ram_rwl, 
  tte_data, 
  va, 
  pa, 
  rd_tte_data) ;
wire any_wwl;
wire any_rwl;
wire [37:0] prd_data;
wire [39:13] tte_pa;


`define ENTRIES		64
`define INDEX		5


input		l1clk;

input		tlb_bypass;
input 		tlb_cam_flopped;
input	[`ENTRIES-1:0] ram_wwl;
input	[`ENTRIES-1:0] ram_rwl;

input	[37:0]	tte_data;
input	[39:11]	va;		// Incoming VA


output	[39:11]	pa;
output	[37:0]	rd_tte_data;


`define DATA_PARITY         36
`define DATA_PA_39_28_HI    35
`define DATA_PA_39_28_LO    24
`define DATA_PA_27_22_HI    23
`define DATA_PA_27_22_LO    18
`define DATA_VA_27_22_V     17 
`define DATA_PA_21_16_HI    16
`define DATA_PA_21_16_LO    11
`define DATA_VA_21_16_V     10 
`define DATA_PA_15_13_HI     9
`define DATA_PA_15_13_LO     7
`define DATA_VA_15_13_V      6 
`define DATA_NFO             5 
`define DATA_IE              4 
`define DATA_CP              3 
`define DATA_X               2 
`define DATA_P               1 
`define DATA_W               0 

assign any_wwl =
	| ram_wwl[`ENTRIES-1:0];

assign any_rwl =
	| ram_rwl[`ENTRIES-1:0];


//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------

reg [37:0]  tlb_data_[`ENTRIES-1:0] ;		// this models the data array
						// data stored negative active

integer n;

`ifndef NOINITMEM
///////////////////////////////////////
// Initialize the arrays.            //
///////////////////////////////////////
initial begin
	for (n = 0; n < `ENTRIES; n = n + 1) begin
		tlb_data_[n] = {38 {1'b1}};
	end
	`ifdef ENABLE_DUMPMEM
	if ($test$plusargs("DUMPMEM_DTLB")) begin
		$fsdbDumpMem(tlb_data_, 0, `ENTRIES);
	end
	`endif
end
`endif


///////////////////////////////////////////////////////////////
// Write                                                     // 
///////////////////////////////////////////////////////////////
always @(negedge l1clk) begin

	for (n = 0; n < `ENTRIES; n = n + 1) begin
		if (ram_wwl[n]) begin
			// data stored negative active
			tlb_data_[n] <= ~tte_data[37:0];
			
			
			n = `ENTRIES;
			
		end // if (ram_wl[n])
	end // for (n = 0; n < `ENTRIES; n = n + 1)
	
end // always @ (ram_wl[`ENTRIES-1:0])


///////////////////////////////////////////////////////////////
// Read                                                      // 
///////////////////////////////////////////////////////////////

// ram_rwl is now second half cycle signal... so no need to latch
// Only force outputs to X if read and write at same time
// Model multiple hit read accurately:
//    Whenever stored_data==0 is read from a bit by any of wordline,
//    dout is 0.
// Invert data since stored_data is negative active
assign prd_data[37:0] =
        ((~tlb_data_[0] & {38 {ram_rwl[0]}}) |
         (~tlb_data_[1] & {38 {ram_rwl[1]}}) |
         (~tlb_data_[2] & {38 {ram_rwl[2]}}) |
         (~tlb_data_[3] & {38 {ram_rwl[3]}}) |
         (~tlb_data_[4] & {38 {ram_rwl[4]}}) |
         (~tlb_data_[5] & {38 {ram_rwl[5]}}) |
         (~tlb_data_[6] & {38 {ram_rwl[6]}}) |
         (~tlb_data_[7] & {38 {ram_rwl[7]}}) |
         (~tlb_data_[8] & {38 {ram_rwl[8]}}) |
         (~tlb_data_[9] & {38 {ram_rwl[9]}}) |
         (~tlb_data_[10] & {38 {ram_rwl[10]}}) |
         (~tlb_data_[11] & {38 {ram_rwl[11]}}) |
         (~tlb_data_[12] & {38 {ram_rwl[12]}}) |
         (~tlb_data_[13] & {38 {ram_rwl[13]}}) |
         (~tlb_data_[14] & {38 {ram_rwl[14]}}) |
         (~tlb_data_[15] & {38 {ram_rwl[15]}}) |
         (~tlb_data_[16] & {38 {ram_rwl[16]}}) |
         (~tlb_data_[17] & {38 {ram_rwl[17]}}) |
         (~tlb_data_[18] & {38 {ram_rwl[18]}}) |
         (~tlb_data_[19] & {38 {ram_rwl[19]}}) |
         (~tlb_data_[20] & {38 {ram_rwl[20]}}) |
         (~tlb_data_[21] & {38 {ram_rwl[21]}}) |
         (~tlb_data_[22] & {38 {ram_rwl[22]}}) |
         (~tlb_data_[23] & {38 {ram_rwl[23]}}) |
         (~tlb_data_[24] & {38 {ram_rwl[24]}}) |
         (~tlb_data_[25] & {38 {ram_rwl[25]}}) |
         (~tlb_data_[26] & {38 {ram_rwl[26]}}) |
         (~tlb_data_[27] & {38 {ram_rwl[27]}}) |
         (~tlb_data_[28] & {38 {ram_rwl[28]}}) |
         (~tlb_data_[29] & {38 {ram_rwl[29]}}) |
         (~tlb_data_[30] & {38 {ram_rwl[30]}}) |
         (~tlb_data_[31] & {38 {ram_rwl[31]}}) |
         (~tlb_data_[32] & {38 {ram_rwl[32]}}) |
         (~tlb_data_[33] & {38 {ram_rwl[33]}}) |
         (~tlb_data_[34] & {38 {ram_rwl[34]}}) |
         (~tlb_data_[35] & {38 {ram_rwl[35]}}) |
         (~tlb_data_[36] & {38 {ram_rwl[36]}}) |
         (~tlb_data_[37] & {38 {ram_rwl[37]}}) |
         (~tlb_data_[38] & {38 {ram_rwl[38]}}) |
         (~tlb_data_[39] & {38 {ram_rwl[39]}}) |
         (~tlb_data_[40] & {38 {ram_rwl[40]}}) |
         (~tlb_data_[41] & {38 {ram_rwl[41]}}) |
         (~tlb_data_[42] & {38 {ram_rwl[42]}}) |
         (~tlb_data_[43] & {38 {ram_rwl[43]}}) |
         (~tlb_data_[44] & {38 {ram_rwl[44]}}) |
         (~tlb_data_[45] & {38 {ram_rwl[45]}}) |
         (~tlb_data_[46] & {38 {ram_rwl[46]}}) |
         (~tlb_data_[47] & {38 {ram_rwl[47]}}) |
         (~tlb_data_[48] & {38 {ram_rwl[48]}}) |
         (~tlb_data_[49] & {38 {ram_rwl[49]}}) |
         (~tlb_data_[50] & {38 {ram_rwl[50]}}) |
         (~tlb_data_[51] & {38 {ram_rwl[51]}}) |
         (~tlb_data_[52] & {38 {ram_rwl[52]}}) |
         (~tlb_data_[53] & {38 {ram_rwl[53]}}) |
         (~tlb_data_[54] & {38 {ram_rwl[54]}}) |
         (~tlb_data_[55] & {38 {ram_rwl[55]}}) |
         (~tlb_data_[56] & {38 {ram_rwl[56]}}) |
         (~tlb_data_[57] & {38 {ram_rwl[57]}}) |
         (~tlb_data_[58] & {38 {ram_rwl[58]}}) |
         (~tlb_data_[59] & {38 {ram_rwl[59]}}) |
         (~tlb_data_[60] & {38 {ram_rwl[60]}}) |
         (~tlb_data_[61] & {38 {ram_rwl[61]}}) |
         (~tlb_data_[62] & {38 {ram_rwl[62]}}) |
         (~tlb_data_[63] & {38 {ram_rwl[63]}}) );
			   
assign rd_tte_data[37:0] =
	({38 {any_rwl & ~any_wwl       }} & prd_data[37:0]) |
	({38 {any_rwl &  any_wwl & 1'bx}}                 ) ;


///////////////////////////////////////////////////////////////
// Construct the physical page number                        //
///////////////////////////////////////////////////////////////
assign tte_pa[39:13] = {rd_tte_data[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO],
                        rd_tte_data[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO],
                        rd_tte_data[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], 
                        rd_tte_data[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO]};

assign pa[12:11] = va[12:11];

assign pa[15:13] = 
       (~rd_tte_data[`DATA_VA_15_13_V] & tlb_cam_flopped & ~tlb_bypass) ? 
	       tte_pa[15:13] : va[15:13] ;
assign pa[21:16] = 
       (~rd_tte_data[`DATA_VA_21_16_V] & tlb_cam_flopped & ~tlb_bypass) ? 
	       tte_pa[21:16] : va[21:16] ;
assign pa[27:22] = 
       (~rd_tte_data[`DATA_VA_27_22_V] & tlb_cam_flopped & ~tlb_bypass) ? 
	       tte_pa[27:22] : va[27:22] ;
assign pa[39:28] = 
       (tlb_cam_flopped & ~tlb_bypass) ? 
	       tte_pa[39:28] : va[39:28];


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 

endmodule
`endif // `ifndef FPGA

`ifdef FPGA
module n2_tlb_tl_64x59_ram(l1clk, tlb_bypass, tlb_cam_flopped, ram_wwl, ram_rwl,
	tte_data, va, pa, rd_tte_data);

	input			l1clk;
	input			tlb_bypass;
	input			tlb_cam_flopped;
	input	[(64 - 1):0]	ram_wwl;
	input	[(64 - 1):0]	ram_rwl;
	input	[37:0]		tte_data;
	input	[39:11]		va;
	output	[39:11]		pa;
	output	[37:0]		rd_tte_data;

	wire			any_wwl;
	wire			any_rwl;
	wire	[37:0]		prd_data;
	wire	[39:13]		tte_pa;

	reg	[37:0]		tlb_data_[(64 - 1):0];
	integer			n;
	integer			done;
	supply0			vss;
	supply1			vdd;

	assign any_wwl = (|ram_wwl[(64 - 1):0]);
	assign any_rwl = (|ram_rwl[(64 - 1):0]);
	assign prd_data[37:0] = ((((((((((((((((((((((((((((((((((((((((((((((((
		(((((((((((((((((~tlb_data_[0]) & {38 {ram_rwl[0]}}) | ((~
		tlb_data_[1]) & {38 {ram_rwl[1]}})) | ((~tlb_data_[2]) & {38 {
		ram_rwl[2]}})) | ((~tlb_data_[3]) & {38 {ram_rwl[3]}})) | ((~
		tlb_data_[4]) & {38 {ram_rwl[4]}})) | ((~tlb_data_[5]) & {38 {
		ram_rwl[5]}})) | ((~tlb_data_[6]) & {38 {ram_rwl[6]}})) | ((~
		tlb_data_[7]) & {38 {ram_rwl[7]}})) | ((~tlb_data_[8]) & {38 {
		ram_rwl[8]}})) | ((~tlb_data_[9]) & {38 {ram_rwl[9]}})) | ((~
		tlb_data_[10]) & {38 {ram_rwl[10]}})) | ((~tlb_data_[11]) & {38 
		{ram_rwl[11]}})) | ((~tlb_data_[12]) & {38 {ram_rwl[12]}})) | ((
		~tlb_data_[13]) & {38 {ram_rwl[13]}})) | ((~tlb_data_[14]) & {38
		{ram_rwl[14]}})) | ((~tlb_data_[15]) & {38 {ram_rwl[15]}})) | ((
		~tlb_data_[16]) & {38 {ram_rwl[16]}})) | ((~tlb_data_[17]) & {38
		{ram_rwl[17]}})) | ((~tlb_data_[18]) & {38 {ram_rwl[18]}})) | ((
		~tlb_data_[19]) & {38 {ram_rwl[19]}})) | ((~tlb_data_[20]) & {38
		{ram_rwl[20]}})) | ((~tlb_data_[21]) & {38 {ram_rwl[21]}})) | ((
		~tlb_data_[22]) & {38 {ram_rwl[22]}})) | ((~tlb_data_[23]) & {38
		{ram_rwl[23]}})) | ((~tlb_data_[24]) & {38 {ram_rwl[24]}})) | ((
		~tlb_data_[25]) & {38 {ram_rwl[25]}})) | ((~tlb_data_[26]) & {38
		{ram_rwl[26]}})) | ((~tlb_data_[27]) & {38 {ram_rwl[27]}})) | ((
		~tlb_data_[28]) & {38 {ram_rwl[28]}})) | ((~tlb_data_[29]) & {38
		{ram_rwl[29]}})) | ((~tlb_data_[30]) & {38 {ram_rwl[30]}})) | ((
		~tlb_data_[31]) & {38 {ram_rwl[31]}})) | ((~tlb_data_[32]) & {38
		{ram_rwl[32]}})) | ((~tlb_data_[33]) & {38 {ram_rwl[33]}})) | ((
		~tlb_data_[34]) & {38 {ram_rwl[34]}})) | ((~tlb_data_[35]) & {38
		{ram_rwl[35]}})) | ((~tlb_data_[36]) & {38 {ram_rwl[36]}})) | ((
		~tlb_data_[37]) & {38 {ram_rwl[37]}})) | ((~tlb_data_[38]) & {38
		{ram_rwl[38]}})) | ((~tlb_data_[39]) & {38 {ram_rwl[39]}})) | ((
		~tlb_data_[40]) & {38 {ram_rwl[40]}})) | ((~tlb_data_[41]) & {38
		{ram_rwl[41]}})) | ((~tlb_data_[42]) & {38 {ram_rwl[42]}})) | ((
		~tlb_data_[43]) & {38 {ram_rwl[43]}})) | ((~tlb_data_[44]) & {38
		{ram_rwl[44]}})) | ((~tlb_data_[45]) & {38 {ram_rwl[45]}})) | ((
		~tlb_data_[46]) & {38 {ram_rwl[46]}})) | ((~tlb_data_[47]) & {38
		{ram_rwl[47]}})) | ((~tlb_data_[48]) & {38 {ram_rwl[48]}})) | ((
		~tlb_data_[49]) & {38 {ram_rwl[49]}})) | ((~tlb_data_[50]) & {38
		{ram_rwl[50]}})) | ((~tlb_data_[51]) & {38 {ram_rwl[51]}})) | ((
		~tlb_data_[52]) & {38 {ram_rwl[52]}})) | ((~tlb_data_[53]) & {38
		{ram_rwl[53]}})) | ((~tlb_data_[54]) & {38 {ram_rwl[54]}})) | ((
		~tlb_data_[55]) & {38 {ram_rwl[55]}})) | ((~tlb_data_[56]) & {38
		{ram_rwl[56]}})) | ((~tlb_data_[57]) & {38 {ram_rwl[57]}})) | ((
		~tlb_data_[58]) & {38 {ram_rwl[58]}})) | ((~tlb_data_[59]) & {38
		{ram_rwl[59]}})) | ((~tlb_data_[60]) & {38 {ram_rwl[60]}})) | ((
		~tlb_data_[61]) & {38 {ram_rwl[61]}})) | ((~tlb_data_[62]) & {38
		{ram_rwl[62]}})) | ((~tlb_data_[63]) & {38 {ram_rwl[63]}}));
	assign rd_tte_data[37:0] = (({38 {(any_rwl & (~any_wwl))}} & 
		prd_data[37:0]) | {38 {((any_rwl & any_wwl) & 1'bx)}});
	assign tte_pa[39:13] = {rd_tte_data[35:24], rd_tte_data[23:18], 
		rd_tte_data[16:11], rd_tte_data[9:7]};
	assign pa[12:11] = va[12:11];
	assign pa[15:13] = ((((~rd_tte_data[6]) & tlb_cam_flopped) & (~
		tlb_bypass)) ? tte_pa[15:13] : va[15:13]);
	assign pa[21:16] = ((((~rd_tte_data[10]) & tlb_cam_flopped) & (~
		tlb_bypass)) ? tte_pa[21:16] : va[21:16]);
	assign pa[27:22] = ((((~rd_tte_data[17]) & tlb_cam_flopped) & (~
		tlb_bypass)) ? tte_pa[27:22] : va[27:22]);
	assign pa[39:28] = ((tlb_cam_flopped & (~tlb_bypass)) ? tte_pa[39:28] : 
		va[39:28]);

	initial begin
	  for (n = 0; (n < 64); n = (n + 1)) begin
	    tlb_data_[n] = {38 {1'b1}};
	  end
	end
	always @(negedge l1clk) begin
	  done = 0;
	  for (n = 0; (n < 64); n = (n + 1)) begin
	    if (ram_wwl[n] && (!done)) begin
	      tlb_data_[n] <= (~tte_data[37:0]);
	      done = 1;
	    end
	  end
	end
endmodule

`endif // `ifdef FPGA


module n2_tlb_tl_64x59_multihit (
  ram_rwl, 
  tlb_bypass, 
  tlb_cam_mhit) ;
wire [7:0] sum;
wire multiple_match;
wire unused;


`define ENTRIES		64
//`define INDEX		5


input	[`ENTRIES-1:0] ram_rwl;
input		tlb_bypass;


output		tlb_cam_mhit;


assign sum[7:0] = 
	{{7 {1'b0}}, ram_rwl[0]} +
	{{7 {1'b0}}, ram_rwl[1]} +
	{{7 {1'b0}}, ram_rwl[2]} +
	{{7 {1'b0}}, ram_rwl[3]} +
	{{7 {1'b0}}, ram_rwl[4]} +
	{{7 {1'b0}}, ram_rwl[5]} +
	{{7 {1'b0}}, ram_rwl[6]} +
	{{7 {1'b0}}, ram_rwl[7]} +
	{{7 {1'b0}}, ram_rwl[8]} +
	{{7 {1'b0}}, ram_rwl[9]} +
	{{7 {1'b0}}, ram_rwl[10]} +
	{{7 {1'b0}}, ram_rwl[11]} +
	{{7 {1'b0}}, ram_rwl[12]} +
	{{7 {1'b0}}, ram_rwl[13]} +
	{{7 {1'b0}}, ram_rwl[14]} +
	{{7 {1'b0}}, ram_rwl[15]} +
	{{7 {1'b0}}, ram_rwl[16]} +
	{{7 {1'b0}}, ram_rwl[17]} +
	{{7 {1'b0}}, ram_rwl[18]} +
	{{7 {1'b0}}, ram_rwl[19]} +
	{{7 {1'b0}}, ram_rwl[20]} +
	{{7 {1'b0}}, ram_rwl[21]} +
	{{7 {1'b0}}, ram_rwl[22]} +
	{{7 {1'b0}}, ram_rwl[23]} +
	{{7 {1'b0}}, ram_rwl[24]} +
	{{7 {1'b0}}, ram_rwl[25]} +
	{{7 {1'b0}}, ram_rwl[26]} +
	{{7 {1'b0}}, ram_rwl[27]} +
	{{7 {1'b0}}, ram_rwl[28]} +
	{{7 {1'b0}}, ram_rwl[29]} +
	{{7 {1'b0}}, ram_rwl[30]} +
	{{7 {1'b0}}, ram_rwl[31]} +
	{{7 {1'b0}}, ram_rwl[32]} +
	{{7 {1'b0}}, ram_rwl[33]} +
	{{7 {1'b0}}, ram_rwl[34]} +
	{{7 {1'b0}}, ram_rwl[35]} +
	{{7 {1'b0}}, ram_rwl[36]} +
	{{7 {1'b0}}, ram_rwl[37]} +
	{{7 {1'b0}}, ram_rwl[38]} +
	{{7 {1'b0}}, ram_rwl[39]} +
	{{7 {1'b0}}, ram_rwl[40]} +
	{{7 {1'b0}}, ram_rwl[41]} +
	{{7 {1'b0}}, ram_rwl[42]} +
	{{7 {1'b0}}, ram_rwl[43]} +
	{{7 {1'b0}}, ram_rwl[44]} +
	{{7 {1'b0}}, ram_rwl[45]} +
	{{7 {1'b0}}, ram_rwl[46]} +
	{{7 {1'b0}}, ram_rwl[47]} +
	{{7 {1'b0}}, ram_rwl[48]} +
	{{7 {1'b0}}, ram_rwl[49]} +
	{{7 {1'b0}}, ram_rwl[50]} +
	{{7 {1'b0}}, ram_rwl[51]} +
	{{7 {1'b0}}, ram_rwl[52]} +
	{{7 {1'b0}}, ram_rwl[53]} +
	{{7 {1'b0}}, ram_rwl[54]} +
	{{7 {1'b0}}, ram_rwl[55]} +
	{{7 {1'b0}}, ram_rwl[56]} +
	{{7 {1'b0}}, ram_rwl[57]} +
	{{7 {1'b0}}, ram_rwl[58]} +
	{{7 {1'b0}}, ram_rwl[59]} +
	{{7 {1'b0}}, ram_rwl[60]} +
	{{7 {1'b0}}, ram_rwl[61]} +
	{{7 {1'b0}}, ram_rwl[62]} +
	{{7 {1'b0}}, ram_rwl[63]} ;
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assign multiple_match = 
	(| sum[7:1]) & ~tlb_bypass;

assign unused = sum[0];

assign tlb_cam_mhit = 
       multiple_match;


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule


`ifndef FPGA
module n2_tlb_tl_64x59_ubit (
  l1clk, 
  disable_clear_ubit, 
  tlb_bypass, 
  ram_rwl, 
  ram_wwl, 
  tte_ubit, 
  tlb_wr_flopped, 
  tlb_rd_flopped, 
  tlb_cam_flopped, 
  used, 
  rd_tte_u_bit) ;
wire all_entries_used;


`define ENTRIES		64


input		l1clk;
input		disable_clear_ubit;

input		tlb_bypass;
input	[`ENTRIES-1:0] ram_rwl;
input	[`ENTRIES-1:0] ram_wwl;
input		tte_ubit;

input		tlb_wr_flopped;
input		tlb_rd_flopped;
input		tlb_cam_flopped;


output	[`ENTRIES-1:0] used;
output 		   rd_tte_u_bit;


//----------------------------------------------------------------------
// Declarations
//----------------------------------------------------------------------
reg [`ENTRIES-1:0] used;

integer 	   n;

reg 		   rd_tte_u_bit_in;


`ifndef NOINITMEM
///////////////////////////////////////
// Initialize the arrays.            //
///////////////////////////////////////
initial begin
	used[`ENTRIES-1:0]  = {`ENTRIES {1'b0}} ;
end
`endif


assign all_entries_used  = 
       (& used[`ENTRIES-1:0]) & ~disable_clear_ubit;


always @(negedge l1clk) begin
	// Maintain the used bits
	if (all_entries_used) begin
		used[`ENTRIES-1:0] <= {`ENTRIES {1'b0}};
	end

	if (~all_entries_used & ((~tlb_bypass & tlb_cam_flopped) | tlb_wr_flopped)) begin
		for (n = 0; n < `ENTRIES; n = n + 1) begin
			if (ram_rwl[n]) begin
				used[n] <= 1'b1;
			end
			if (ram_wwl[n]) begin
				used[n] <= tte_ubit;
			end
		end
	end // if (~all_entries_used & ((~tlb_bypass & tlb_cam_flopped) | tlb_wr_flopped))

	
end // always @ (negedge l1clk)


///////////////////////////////////////////////////////////////
// Read U bit
///////////////////////////////////////////////////////////////


always @(ram_rwl[`ENTRIES-1:0] or used[`ENTRIES-1:0] or tlb_rd_flopped) begin

	rd_tte_u_bit_in = {1'b0};

	if (tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0])) begin	 
		for (n = 0; n < `ENTRIES; n = n + 1) begin
			if (ram_rwl[n]) begin
				rd_tte_u_bit_in = used[n];
				
				
				n = `ENTRIES;
				
			end // if (ram_wl[n])
		end // for (n = 0; n < `ENTRIES; n = n + 1)
	end // if (tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0]))
	else if (~tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0])) begin
		rd_tte_u_bit_in = {1'bx};
	end
	
end

assign rd_tte_u_bit = 
       rd_tte_u_bit_in;


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule
`endif // `ifndef FPGA

`ifdef FPGA
module n2_tlb_tl_64x59_ubit(l1clk, disable_clear_ubit, tlb_bypass, ram_rwl, 
	ram_wwl, tte_ubit, tlb_wr_flopped, tlb_rd_flopped, tlb_cam_flopped, 
	used, rd_tte_u_bit);

	input			l1clk;
	input			disable_clear_ubit;
	input			tlb_bypass;
	input	[(64 - 1):0]	ram_rwl;
	input	[(64 - 1):0]	ram_wwl;
	input			tte_ubit;
	input			tlb_wr_flopped;
	input			tlb_rd_flopped;
	input			tlb_cam_flopped;
	output	[(64 - 1):0]	used;
	output			rd_tte_u_bit;

	wire			all_entries_used;
	reg	[(64 - 1):0]	used;
	integer			n;
	integer			done;
	reg			rd_tte_u_bit_in;
	supply0			vss;
	supply1			vdd;

	assign all_entries_used = ((&used[(64 - 1):0]) & (~disable_clear_ubit));
	assign rd_tte_u_bit = rd_tte_u_bit_in;

	initial begin
	  used[(64 - 1):0] = {64 {1'b0}};
	end
	always @(negedge l1clk) begin
	  if (all_entries_used) begin
	    used[(64 - 1):0] <= {64 {1'b0}};
	  end
	  if ((~all_entries_used) & (((~tlb_bypass) & tlb_cam_flopped) | 
		  tlb_wr_flopped)) begin
	    for (n = 0; (n < 64); n = (n + 1)) begin
	      if (ram_rwl[n]) begin
		used[n] <= 1'b1;
	      end
	      if (ram_wwl[n]) begin
		used[n] <= tte_ubit;
	      end
	    end
	  end
	end
	always @(ram_rwl[(64 - 1):0] or used[(64 - 1):0] or tlb_rd_flopped) 
		begin
	  rd_tte_u_bit_in = {1'b0};
	  if (tlb_rd_flopped & (|ram_rwl[(64 - 1):0])) begin
	    done = 0;
	    for (n = 0; (n < 64); n = (n + 1)) begin
	      if (ram_rwl[n] && (!done)) begin
		rd_tte_u_bit_in = used[n];
		done = 1;
	      end
	    end
	  end
	end
endmodule

`endif // `ifdef FPGA


module n2_tlb_tl_64x59_repl_index (
  l1clk, 
  used, 
  valid, 
  tlb_replacement_index) ;
wire [63:0] nu_or_nv;
wire [63:0] used_and_valid;
wire [1:0] enc4_00;
wire sel4_00_b;
wire [1:0] enc4_01;
wire sel4_01_b;
wire [1:0] enc4_02;
wire sel4_02_b;
wire [1:0] enc4_03;
wire sel4_03_b;
wire [1:0] enc4_04;
wire sel4_04_b;
wire [1:0] enc4_05;
wire sel4_05_b;
wire [1:0] enc4_06;
wire sel4_06_b;
wire [1:0] enc4_07;
wire sel4_07_b;
wire [1:0] enc4_08;
wire sel4_08_b;
wire [1:0] enc4_09;
wire sel4_09_b;
wire [1:0] enc4_10;
wire sel4_10_b;
wire [1:0] enc4_11;
wire sel4_11_b;
wire [1:0] enc4_12;
wire sel4_12_b;
wire [1:0] enc4_13;
wire sel4_13_b;
wire [1:0] enc4_14;
wire sel4_14_b;
wire [1:0] enc4_15;
wire sel4_15_b;
wire [2:0] enc8_00;
wire sel8_00_b;
wire [2:0] enc8_01;
wire sel8_01_b;
wire [2:0] enc8_02;
wire sel8_02_b;
wire [2:0] enc8_03;
wire sel8_03_b;
wire [2:0] enc8_04;
wire sel8_04_b;
wire [2:0] enc8_05;
wire sel8_05_b;
wire [2:0] enc8_06;
wire sel8_06_b;
wire [2:0] enc8_07;
wire sel8_07_b;
wire [3:0] enc16_0;
wire sel16_0_b;
wire [3:0] enc16_1;
wire sel16_1_b;
wire [3:0] enc16_2;
wire sel16_2_b;
wire [3:0] enc16_3;
wire sel16_3_b;
wire unused;
wire [3:0] enc16_l_0;
wire [3:0] enc16_l_1;
wire [3:0] enc16_l_2;
wire [3:0] enc16_l_3;
wire sel16_l_0_b;
wire sel16_l_1_b;
wire sel16_l_2_b;
wire sel16_l_3_b_unused;
wire [4:0] enc32_0;
wire sel32_0_b;
wire [4:0] enc32_1;
wire [5:0] enc64_0;


`define ENTRIES		64
`define INDEX		5


input		l1clk;

input	[`ENTRIES-1:0] used;
input	[`ENTRIES-1:0] valid;


output	[`INDEX:0] tlb_replacement_index;


assign nu_or_nv[`ENTRIES-1:0] =
       ~valid[`ENTRIES-1:0] | ~used[`ENTRIES-1:0];

assign used_and_valid[`ENTRIES-1:0] =
       ~nu_or_nv[`ENTRIES-1:0];


// 4 bit priority encoders
assign enc4_00[1] = used_and_valid[0] &   used_and_valid[1];
assign enc4_00[0] = used_and_valid[0] & (~used_and_valid[1] | used_and_valid[2]);
assign sel4_00_b  = &used_and_valid[3:0];

assign enc4_01[1] = used_and_valid[4] &   used_and_valid[5];
assign enc4_01[0] = used_and_valid[4] & (~used_and_valid[5] | used_and_valid[6]);
assign sel4_01_b  = &used_and_valid[7:4];

assign enc4_02[1] = used_and_valid[8] &   used_and_valid[9];
assign enc4_02[0] = used_and_valid[8] & (~used_and_valid[9] | used_and_valid[10]);
assign sel4_02_b  = &used_and_valid[11:8];

assign enc4_03[1] = used_and_valid[12] &   used_and_valid[13];
assign enc4_03[0] = used_and_valid[12] & (~used_and_valid[13] | used_and_valid[14]);
assign sel4_03_b  = &used_and_valid[15:12];

assign enc4_04[1] = used_and_valid[16] &   used_and_valid[17];
assign enc4_04[0] = used_and_valid[16] & (~used_and_valid[17] | used_and_valid[18]);
assign sel4_04_b  = &used_and_valid[19:16];

assign enc4_05[1] = used_and_valid[20] &   used_and_valid[21];
assign enc4_05[0] = used_and_valid[20] & (~used_and_valid[21] | used_and_valid[22]);
assign sel4_05_b  = &used_and_valid[23:20];

assign enc4_06[1] = used_and_valid[24] &   used_and_valid[25];
assign enc4_06[0] = used_and_valid[24] & (~used_and_valid[25] | used_and_valid[26]);
assign sel4_06_b  = &used_and_valid[27:24];

assign enc4_07[1] = used_and_valid[28] &   used_and_valid[29];
assign enc4_07[0] = used_and_valid[28] & (~used_and_valid[29] | used_and_valid[30]);
assign sel4_07_b  = &used_and_valid[31:28];

assign enc4_08[1] = used_and_valid[32] &   used_and_valid[33];
assign enc4_08[0] = used_and_valid[32] & (~used_and_valid[33] | used_and_valid[34]);
assign sel4_08_b  = &used_and_valid[35:32];

assign enc4_09[1] = used_and_valid[36] &   used_and_valid[37];
assign enc4_09[0] = used_and_valid[36] & (~used_and_valid[37] | used_and_valid[38]);
assign sel4_09_b  = &used_and_valid[39:36];

assign enc4_10[1] = used_and_valid[40] &   used_and_valid[41];
assign enc4_10[0] = used_and_valid[40] & (~used_and_valid[41] | used_and_valid[42]);
assign sel4_10_b  = &used_and_valid[43:40];

assign enc4_11[1] = used_and_valid[44] &   used_and_valid[45];
assign enc4_11[0] = used_and_valid[44] & (~used_and_valid[45] | used_and_valid[46]);
assign sel4_11_b  = &used_and_valid[47:44];

assign enc4_12[1] = used_and_valid[48] &   used_and_valid[49];
assign enc4_12[0] = used_and_valid[48] & (~used_and_valid[49] | used_and_valid[50]);
assign sel4_12_b  = &used_and_valid[51:48];

assign enc4_13[1] = used_and_valid[52] &   used_and_valid[53];
assign enc4_13[0] = used_and_valid[52] & (~used_and_valid[53] | used_and_valid[54]);
assign sel4_13_b  = &used_and_valid[55:52];

assign enc4_14[1] = used_and_valid[56] &   used_and_valid[57];
assign enc4_14[0] = used_and_valid[56] & (~used_and_valid[57] | used_and_valid[58]);
assign sel4_14_b  = &used_and_valid[59:56];

assign enc4_15[1] = used_and_valid[60] &   used_and_valid[61];
assign enc4_15[0] = used_and_valid[60] & (~used_and_valid[61] | used_and_valid[62]);
assign sel4_15_b  = &used_and_valid[63:60];


// Now generate 8 bit group encodings
assign enc8_00[2]   = sel4_00_b;
assign enc8_00[1:0] = (enc4_00[1:0] & {2 {~sel4_00_b}}) | (enc4_01[1:0] & {2 {sel4_00_b}});
assign sel8_00_b    = sel4_00_b & sel4_01_b;

assign enc8_01[2]   = sel4_02_b;
assign enc8_01[1:0] = (enc4_02[1:0] & {2 {~sel4_02_b}}) | (enc4_03[1:0] & {2 {sel4_02_b}});
assign sel8_01_b    = sel4_02_b & sel4_03_b;

assign enc8_02[2]   = sel4_04_b;
assign enc8_02[1:0] = (enc4_04[1:0] & {2 {~sel4_04_b}}) | (enc4_05[1:0] & {2 {sel4_04_b}});
assign sel8_02_b    = sel4_04_b & sel4_05_b;

assign enc8_03[2]   = sel4_06_b;
assign enc8_03[1:0] = (enc4_06[1:0] & {2 {~sel4_06_b}}) | (enc4_07[1:0] & {2 {sel4_06_b}});
assign sel8_03_b    = sel4_06_b & sel4_07_b;

assign enc8_04[2]   = sel4_08_b;
assign enc8_04[1:0] = (enc4_08[1:0] & {2 {~sel4_08_b}}) | (enc4_09[1:0] & {2 {sel4_08_b}});
assign sel8_04_b    = sel4_08_b & sel4_09_b;

assign enc8_05[2]   = sel4_10_b;
assign enc8_05[1:0] = (enc4_10[1:0] & {2 {~sel4_10_b}}) | (enc4_11[1:0] & {2 {sel4_10_b}});
assign sel8_05_b    = sel4_10_b & sel4_11_b;

assign enc8_06[2]   = sel4_12_b;
assign enc8_06[1:0] = (enc4_12[1:0] & {2 {~sel4_12_b}}) | (enc4_13[1:0] & {2 {sel4_12_b}});
assign sel8_06_b    = sel4_12_b & sel4_13_b;

assign enc8_07[2]   = sel4_14_b;
assign enc8_07[1:0] = (enc4_14[1:0] & {2 {~sel4_14_b}}) | (enc4_15[1:0] & {2 {sel4_14_b}});
assign sel8_07_b    = sel4_14_b & sel4_15_b;


// Now generate 16 bit group encodings
assign enc16_0[3]   = sel8_00_b;
assign enc16_0[2:0] = (enc8_00[2:0] & {3 {~sel8_00_b}}) | (enc8_01[2:0] & {3 {sel8_00_b}});
assign sel16_0_b    = sel8_00_b & sel8_01_b;

assign enc16_1[3]   = sel8_02_b;
assign enc16_1[2:0] = (enc8_02[2:0] & {3 {~sel8_02_b}}) | (enc8_03[2:0] & {3 {sel8_02_b}});
assign sel16_1_b    = sel8_02_b & sel8_03_b;

assign enc16_2[3]   = sel8_04_b;
assign enc16_2[2:0] = (enc8_04[2:0] & {3 {~sel8_04_b}}) | (enc8_05[2:0] & {3 {sel8_04_b}});
assign sel16_2_b    = sel8_04_b & sel8_05_b;

assign enc16_3[3]   = sel8_06_b;
assign enc16_3[2:0] = (enc8_06[2:0] & {3 {~sel8_06_b}}) | (enc8_07[2:0] & {3 {sel8_06_b}});
assign sel16_3_b    = sel8_06_b & sel8_07_b;


// Now flop (nonscan)

n2_tlb_tl_64x59_cust_msff_ctl_macro__width_20 enc16_lat  (
 .scan_in	(1'b0),
 .scan_out	(unused),
 .l1clk		(l1clk),
 .siclk		(1'b0),				 
 .soclk		(1'b0),				 
 .din		({enc16_0[3:0],
		  enc16_1[3:0],
		  enc16_2[3:0],
		  enc16_3[3:0],
		  sel16_0_b,
		  sel16_1_b,
		  sel16_2_b,
		  sel16_3_b}),
 .dout		({enc16_l_0[3:0],
		  enc16_l_1[3:0],
		  enc16_l_2[3:0],
		  enc16_l_3[3:0],
		  sel16_l_0_b,
		  sel16_l_1_b,
		  sel16_l_2_b,
		  sel16_l_3_b_unused})
);


// Now generate 32 bit group encodings
assign enc32_0[4]   = sel16_l_0_b;
assign enc32_0[3:0] = (enc16_l_0[3:0] & {4 {~sel16_l_0_b}}) | (enc16_l_1[3:0] & {4 {sel16_l_0_b}});
assign sel32_0_b    = sel16_l_0_b & sel16_l_1_b;

assign enc32_1[4]   = sel16_l_2_b;
assign enc32_1[3:0] = (enc16_l_2[3:0] & {4 {~sel16_l_2_b}}) | (enc16_l_3[3:0] & {4 {sel16_l_2_b}});


// Now generate 64 bit group encodings
assign enc64_0[5]   = sel32_0_b;
assign enc64_0[4:0] = (enc32_0[4:0] & {5 {~sel32_0_b}}) | (enc32_1[4:0] & {5 {sel32_0_b}});


assign tlb_replacement_index[5:0] = enc64_0[5:0];


supply0 vss; // <- port for ground
supply1 vdd; // <- port for power 
endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__width_20 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [19:0] fdin;
wire [18:0] so;

  input [19:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [19:0] dout;
  output scan_out;
assign fdin[19:0] = din[19:0];


dff #(20)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[19:0]),
.si({scan_in,so[18:0]}),
.so({so[18:0],scan_out}),
.q(dout[19:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_27 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [26:0] fdin;

  input [26:0] din;
  input l1clk;
  input [26:0] scan_in;


  input siclk;
  input soclk;

  output [26:0] dout;
  output [26:0] scan_out;
assign fdin[26:0] = din[26:0];


dff #(27)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[26:0]),
.si(scan_in[26:0]),
.so(scan_out[26:0]),
.q(dout[26:0])
);


endmodule


//
//   invert macro
//
//


module n2_tlb_tl_64x59_cust_inv_macro__stack_66c__width_66 (
  din, 
  dout);
  input [65:0] din;
  output [65:0] dout;


inv #(66)  d0_0 (
.in(din[65:0]),
.out(dout[65:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_66 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [65:0] fdin;

  input [65:0] din;
  input l1clk;
  input [65:0] scan_in;


  input siclk;
  input soclk;

  output [65:0] dout;
  output [65:0] scan_out;
assign fdin[65:0] = din[65:0];


dff #(66)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[65:0]),
.si(scan_in[65:0]),
.so(scan_out[65:0]),
.q(dout[65:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module n2_tlb_tl_64x59_cust_cmp_macro__width_32 (
  din0, 
  din1, 
  dout);
  input [31:0] din0;
  input [31:0] din1;
  output dout;


cmp #(32)  m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);


endmodule


//
//   invert macro
//
//


module n2_tlb_tl_64x59_cust_inv_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;

  input [7:0] din;
  input l1clk;
  input [7:0] scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output [7:0] scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si(scan_in[7:0]),
.so(scan_out[7:0]),
.q(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_mux_macro__mux_aonpe__ports_8__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  input [0:0] din2;
  input sel2;
  input [0:0] din3;
  input sel3;
  input [0:0] din4;
  input sel4;
  input [0:0] din5;
  input sel5;
  input [0:0] din6;
  input sel6;
  input [0:0] din7;
  input sel7;
  output [0:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(1)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
  .in2(din2[0:0]),
  .in3(din3[0:0]),
  .in4(din4[0:0]),
  .in5(din5[0:0]),
  .in6(din6[0:0]),
  .in7(din7[0:0]),
.dout(dout[0:0])
);


endmodule


//
//   parity macro (even parity)
//
//


module n2_tlb_tl_64x59_cust_prty_macro__width_32 (
  din, 
  dout);
  input [31:0] din;
  output dout;


prty #(32)  m0_0 (
.in(din[31:0]),
.out(dout)
);


endmodule


//
//   parity macro (even parity)
//
//


module n2_tlb_tl_64x59_cust_prty_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output dout;


prty #(8)  m0_0 (
.in(din[7:0]),
.out(dout)
);


endmodule


// any PARAMS parms go into naming of macro

module n2_tlb_tl_64x59_cust_msff_ctl_macro__fs_1__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;

  input [3:0] din;
  input l1clk;
  input [3:0] scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output [3:0] scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si(scan_in[3:0]),
.so(scan_out[3:0]),
.q(dout[3:0])
);


endmodule


// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_efuhdr1_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_efuhdr1_ctl (
  efu_hdr_write_data, 
  efu_hdr_xfer_en, 
  efu_hdr_clr, 
  hdr_efu_read_data, 
  hdr_efu_xfer_en, 
  hdr_sram_rvalue, 
  hdr_sram_rid, 
  hdr_sram_wr_en, 
  hdr_sram_red_clr, 
  sram_hdr_read_data, 
  l2clk, 
  io_cmp_sync_en, 
  cmp_io_sync_en, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  tcu_clk_stop, 
  scan_in, 
  scan_out) ;
wire stop;
wire se;
wire l1clk_cmp;
wire ff_cmp_io_sync_en_scanin;
wire ff_cmp_io_sync_en_scanout;
wire cmp_io_sync_en_r1;
wire ff_io_cmp_sync_en_scanin;
wire ff_io_cmp_sync_en_scanout;
wire io_cmp_sync_en_r1;
wire ff_input_all_enable_scanin;
wire ff_input_all_enable_scanout;
wire efu_hdr_xfer_en_r1;
wire efu_hdr_write_data_r1;
wire efu_hdr_clr_r1;
wire efu_hdr_xfer_en_r2;
wire [21:0] efu_instr;
wire [21:0] instr;
wire [21:0] sram_read_data;
wire [21:0] received_instr;
wire [4:0] rdcount;
wire [21:0] sync_read;
wire dispatch_read_data;
wire load_shift_reg;
wire ff_receiver_instr_slice_scanin;
wire ff_receiver_instr_slice_scanout;
wire data_en_io_cmp;
wire [4:0] count;
wire wr_en;
wire [21:0] sync_instr;
wire read_en_io_cmp;
wire ff_sync_sram_data_scanin;
wire ff_sync_sram_data_scanout;
wire ff_sync_read_data_scanin;
wire ff_sync_read_data_scanout;
wire ff_sync_sram_clr_scanin;
wire ff_sync_sram_clr_scanout;
wire sync_clr;
wire ff_sync_sram_wr_scanin;
wire ff_sync_sram_wr_scanout;
wire sync_wr;
wire load_en;
wire ld_rd_en;
wire reset_count;
wire rdreset_count;
wire [4:0] count_in;
wire [4:0] rdcount_in;
wire ff_counter_slice_scanin;
wire ff_counter_slice_scanout;
wire ff_rd_counter_scanin;
wire ff_rd_counter_scanout;
wire spares_cmp_scanin;
wire spares_cmp_scanout;


// EFU to SRAM header 
input		efu_hdr_write_data;
input		efu_hdr_xfer_en;
input		efu_hdr_clr;

// SRAM header to EFU 
output		hdr_efu_read_data;
output		hdr_efu_xfer_en;

// SRAM header to SRAM
output	[ 10 : 0 ]	hdr_sram_rvalue;
output	[ 10 : 0 ]	hdr_sram_rid;
output		hdr_sram_wr_en;
output		hdr_sram_red_clr;

// SRAM to SRAM header
input	[ 10 : 0 ]	sram_hdr_read_data;


// other common signals

input           l2clk;
input		io_cmp_sync_en;
input		cmp_io_sync_en;
input 		tcu_pce_ov;
input 		tcu_aclk;
input 		tcu_bclk;
input 		tcu_scan_en;
input 		tcu_clk_stop;
input           scan_in;
output		scan_out;


// scan renames
wire pce_ov;
wire siclk;
wire soclk;

assign pce_ov = tcu_pce_ov;
assign stop  = tcu_clk_stop;
assign siclk = tcu_aclk;
assign soclk = tcu_bclk;
assign se    = tcu_scan_en;
// end scan renames


l1clkhdr_ctl_macro clkgen_l1clk   
	(
 	.l2clk( l2clk      ),
 	.l1en ( 1'b1       ),
 	.l1clk( l1clk_cmp  ),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
	);


msff_ctl_macro__width_1 ff_cmp_io_sync_en        
	(
	.scan_in(ff_cmp_io_sync_en_scanin),
	.scan_out(ff_cmp_io_sync_en_scanout),
	.dout	(cmp_io_sync_en_r1),
	.din	(cmp_io_sync_en),
	.l1clk	(l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
	);

msff_ctl_macro__width_1 ff_io_cmp_sync_en        
	(
	.scan_in(ff_io_cmp_sync_en_scanin),
	.scan_out(ff_io_cmp_sync_en_scanout),
	.dout	(io_cmp_sync_en_r1),
	.din	(io_cmp_sync_en),
	.l1clk	(l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
	);

msff_ctl_macro__en_1__width_4 ff_input_all_enable         
	(
	.scan_in(ff_input_all_enable_scanin),
	.scan_out(ff_input_all_enable_scanout),
	.dout	({efu_hdr_xfer_en_r1,efu_hdr_write_data_r1,efu_hdr_clr_r1,efu_hdr_xfer_en_r2}),
	.din	({efu_hdr_xfer_en,   efu_hdr_write_data   ,efu_hdr_clr,   efu_hdr_xfer_en_r1}),
        .en     (io_cmp_sync_en_r1),
	.l1clk	(l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
	);


assign efu_instr[ 21 : 0 ]      = {instr[ 20 : 0 ],efu_hdr_write_data_r1}; 

assign sram_read_data[ 21 : 0 ] = {instr[ 21 : 11 ],sram_hdr_read_data[ 10 : 0 ]};

//assign received_instr[21:0] = efu_hdr_xfer_en_r1 ? efu_instr[21:0] : 
//			      (count==5'd6) ? sram_read_data[21:0] : 
//				dispatch_read_data ? ({instr[20:0],1'b0}) : 22'b0;

assign received_instr[ 21 : 0 ] = efu_hdr_xfer_en_r1 ? efu_instr[ 21 : 0 ] 
                            : rdcount == 5'd23 ? sync_read 
                            : dispatch_read_data ? ({instr[ 20 : 0 ],1'b0}) : 22'b0;


//assign load_shift_reg = efu_hdr_xfer_en_r1 | dispatch_read_data;
assign load_shift_reg = efu_hdr_xfer_en_r1 | dispatch_read_data | rdcount == 5'd23;

msff_ctl_macro__en_1__width_22 ff_receiver_instr_slice 
	(
        .scan_in(ff_receiver_instr_slice_scanin),
        .scan_out(ff_receiver_instr_slice_scanout),
        .dout   (instr[ 21 : 0 ]),
        .din    (load_shift_reg ? received_instr[ 21 : 0 ] : instr[ 21 : 0 ]),
	.en	(io_cmp_sync_en_r1),
        .l1clk    (l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
        );

//data available at 5'd8 (completely shifted in)
assign data_en_io_cmp = (count==5'd8) & io_cmp_sync_en_r1;
// generate wr_en after 1 cycle of setup and enable bits are valid
//assign wr_en          = (count==5'd7) & sync_instr[11] & sync_instr[0];
assign wr_en          = (count==5'd7) & ~sync_instr[ 21 ];
//get data back from sram after 4 ioclk cycles wait
assign read_en_io_cmp = (count==5'd1) & cmp_io_sync_en_r1;

msff_ctl_macro__en_1__width_22 ff_sync_sram_data 
	(
        .scan_in(ff_sync_sram_data_scanin),
	.scan_out(ff_sync_sram_data_scanout),
	.dout	(sync_instr[ 21 : 0 ]),
	.din	((count==5'd8) ? instr[ 21 : 0 ] : sync_instr[ 21 : 0 ]),
	.en	(io_cmp_sync_en_r1),
	.l1clk	(l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
	);

msff_ctl_macro__en_1__width_22 ff_sync_read_data 
	(
        .scan_in(ff_sync_read_data_scanin),
	.scan_out(ff_sync_read_data_scanout),
	.dout	(sync_read[ 21 : 0 ]),
	.din	((count==5'd1) ? sram_read_data[ 21 : 0 ] : sync_read[ 21 : 0 ]),
	.en	(cmp_io_sync_en_r1),
	.l1clk	(l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
	);

msff_ctl_macro__en_1__width_1 ff_sync_sram_clr 
	(
        .scan_in(ff_sync_sram_clr_scanin),
	.scan_out(ff_sync_sram_clr_scanout),
	.dout	(sync_clr),
	.din	(efu_hdr_clr_r1),
	.en	(io_cmp_sync_en_r1),
	.l1clk	(l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
	);

msff_ctl_macro__en_1__width_1 ff_sync_sram_wr 
	(
        .scan_in(ff_sync_sram_wr_scanin),
	.scan_out(ff_sync_sram_wr_scanout),
	.dout	(sync_wr),
	.din	(wr_en),
	.en	(io_cmp_sync_en_r1),
	.l1clk	(l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
	);


assign load_en = (~efu_hdr_xfer_en_r2 & efu_hdr_xfer_en_r1);
assign ld_rd_en = (count==5'd1);

assign reset_count   = (   count == 5'd0 );
assign rdreset_count = ( rdcount == 5'd0 );

assign   count_in = load_en  ? 5'd29 : reset_count   ? 5'b0 : (  count - 5'b1);
assign rdcount_in = ld_rd_en ? 5'd23 : rdreset_count ? 5'b0 : (rdcount - 5'b1);

msff_ctl_macro__en_1__width_5 ff_counter_slice 
        (
        .scan_in(ff_counter_slice_scanin),
        .scan_out(ff_counter_slice_scanout),
        .dout   (count[ 4 : 0 ]),
        .din    (count_in[ 4 : 0 ]),
        .en     (io_cmp_sync_en_r1),
        .l1clk    (l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
        );

msff_ctl_macro__en_1__width_5 ff_rd_counter 
        (
        .scan_in(ff_rd_counter_scanin),
        .scan_out(ff_rd_counter_scanout),
        .dout   (rdcount[ 4 : 0 ]),
        .din    (rdcount_in[ 4 : 0 ]),
        .en     (io_cmp_sync_en_r1),
        .l1clk    (l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
        );

spare_ctl_macro__num_4 spares_cmp  (
	.scan_in(spares_cmp_scanin),
	.scan_out(spares_cmp_scanout),
	.l1clk (l1clk_cmp),
  .siclk(siclk),
  .soclk(soclk)
);

//assign hdr_sram_rvalue[10:0]  = instr[10:0];
//assign hdr_sram_rid[10:0]     = instr[21:11];
//assign hdr_sram_red_clr       = efu_hdr_clr_r1;
//assign hdr_sram_wr_en         = |(count[1:0]);
assign hdr_sram_rvalue[ 10 : 0 ]  = sync_instr[ 10 : 0 ];
assign hdr_sram_rid[ 10 : 0 ]     = sync_instr[ 21 : 11 ];
assign hdr_sram_red_clr       = sync_clr;
assign hdr_sram_wr_en         = sync_wr;


assign dispatch_read_data = (rdcount[ 4 : 0 ] < 5'd23 & rdcount[ 4 : 0 ] != 5'd0);

assign hdr_efu_read_data  = instr[ 21 ];
assign hdr_efu_xfer_en    = dispatch_read_data;

// fixscan start:
assign ff_cmp_io_sync_en_scanin = scan_in ;
assign ff_io_cmp_sync_en_scanin = ff_cmp_io_sync_en_scanout;
assign ff_input_all_enable_scanin = ff_io_cmp_sync_en_scanout;
assign ff_receiver_instr_slice_scanin = ff_input_all_enable_scanout;
assign ff_counter_slice_scanin   = ff_receiver_instr_slice_scanout;
assign ff_sync_sram_data_scanin = ff_counter_slice_scanout;
assign ff_sync_read_data_scanin = ff_sync_sram_data_scanout;
assign ff_sync_sram_clr_scanin = ff_sync_read_data_scanout;
assign ff_sync_sram_wr_scanin = ff_sync_sram_clr_scanout;
assign ff_rd_counter_scanin = ff_sync_sram_wr_scanout;
assign spares_cmp_scanin = ff_rd_counter_scanout ;
assign scan_out                  = spares_cmp_scanout ;
// fixscan end:
endmodule


// any PARAMS parms go into naming of macro

module l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// any PARAMS parms go into naming of macro

module msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [ 0 : 0 ] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [ 0 : 0 ] dout;
  output scan_out;
assign fdin[ 0 : 0 ] = din[ 0 : 0 ];


cl_sc1_msff_4x d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 0 ]),
.si(scan_in),
.so(scan_out),
.q(dout[ 0 ])
);


endmodule


// any PARAMS parms go into naming of macro

module msff_ctl_macro__en_1__width_4 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;
wire [3:1] sout;

  input [ 3 : 0 ] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [ 3 : 0 ] dout;
  output scan_out;
assign fdin[ 3 : 0 ] = (din[ 3 : 0 ] & {4{en}}) | (dout[ 3 : 0 ] & ~{4{en}});


cl_sc1_msff_4x d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 0 ]),
.si(sout[ 1 ]),
.so(scan_out),
.q(dout[ 0 ])
);
cl_sc1_msff_4x d0_1 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 1 ]),
.si(sout[ 2 ]),
.so(sout[ 1 ]),
.q(dout[ 1 ])
);
cl_sc1_msff_4x d0_2 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 2 ]),
.si(sout[ 3 ]),
.so(sout[ 2 ]),
.q(dout[ 2 ])
);
cl_sc1_msff_4x d0_3 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 3 ]),
.si(scan_in),
.so(sout[ 3 ]),
.q(dout[ 3 ])
);


endmodule


// any PARAMS parms go into naming of macro

module msff_ctl_macro__en_1__width_22 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [21:0] fdin;
wire [21:1] sout;

  input [ 21 : 0 ] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [ 21 : 0 ] dout;
  output scan_out;
assign fdin[ 21 : 0 ] = (din[ 21 : 0 ] & {22{en}}) | (dout[ 21 : 0 ] & ~{22{en}});


cl_sc1_msff_4x d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 0 ]),
.si(sout[ 1 ]),
.so(scan_out),
.q(dout[ 0 ])
);
cl_sc1_msff_4x d0_1 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 1 ]),
.si(sout[ 2 ]),
.so(sout[ 1 ]),
.q(dout[ 1 ])
);
cl_sc1_msff_4x d0_2 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 2 ]),
.si(sout[ 3 ]),
.so(sout[ 2 ]),
.q(dout[ 2 ])
);
cl_sc1_msff_4x d0_3 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 3 ]),
.si(sout[ 4 ]),
.so(sout[ 3 ]),
.q(dout[ 3 ])
);
cl_sc1_msff_4x d0_4 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 4 ]),
.si(sout[ 5 ]),
.so(sout[ 4 ]),
.q(dout[ 4 ])
);
cl_sc1_msff_4x d0_5 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 5 ]),
.si(sout[ 6 ]),
.so(sout[ 5 ]),
.q(dout[ 5 ])
);
cl_sc1_msff_4x d0_6 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 6 ]),
.si(sout[ 7 ]),
.so(sout[ 6 ]),
.q(dout[ 6 ])
);
cl_sc1_msff_4x d0_7 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 7 ]),
.si(sout[ 8 ]),
.so(sout[ 7 ]),
.q(dout[ 7 ])
);
cl_sc1_msff_4x d0_8 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 8 ]),
.si(sout[ 9 ]),
.so(sout[ 8 ]),
.q(dout[ 8 ])
);
cl_sc1_msff_4x d0_9 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 9 ]),
.si(sout[ 10 ]),
.so(sout[ 9 ]),
.q(dout[ 9 ])
);
cl_sc1_msff_4x d0_10 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 10 ]),
.si(sout[ 11 ]),
.so(sout[ 10 ]),
.q(dout[ 10 ])
);
cl_sc1_msff_4x d0_11 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 11 ]),
.si(sout[ 12 ]),
.so(sout[ 11 ]),
.q(dout[ 11 ])
);
cl_sc1_msff_4x d0_12 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 12 ]),
.si(sout[ 13 ]),
.so(sout[ 12 ]),
.q(dout[ 12 ])
);
cl_sc1_msff_4x d0_13 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 13 ]),
.si(sout[ 14 ]),
.so(sout[ 13 ]),
.q(dout[ 13 ])
);
cl_sc1_msff_4x d0_14 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 14 ]),
.si(sout[ 15 ]),
.so(sout[ 14 ]),
.q(dout[ 14 ])
);
cl_sc1_msff_4x d0_15 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 15 ]),
.si(sout[ 16 ]),
.so(sout[ 15 ]),
.q(dout[ 15 ])
);
cl_sc1_msff_4x d0_16 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 16 ]),
.si(sout[ 17 ]),
.so(sout[ 16 ]),
.q(dout[ 16 ])
);
cl_sc1_msff_4x d0_17 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 17 ]),
.si(sout[ 18 ]),
.so(sout[ 17 ]),
.q(dout[ 17 ])
);
cl_sc1_msff_4x d0_18 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 18 ]),
.si(sout[ 19 ]),
.so(sout[ 18 ]),
.q(dout[ 18 ])
);
cl_sc1_msff_4x d0_19 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 19 ]),
.si(sout[ 20 ]),
.so(sout[ 19 ]),
.q(dout[ 19 ])
);
cl_sc1_msff_4x d0_20 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 20 ]),
.si(sout[ 21 ]),
.so(sout[ 20 ]),
.q(dout[ 20 ])
);
cl_sc1_msff_4x d0_21 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 21 ]),
.si(scan_in),
.so(sout[ 21 ]),
.q(dout[ 21 ])
);


endmodule


// any PARAMS parms go into naming of macro

module msff_ctl_macro__en_1__width_1 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [ 0 : 0 ] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [ 0 : 0 ] dout;
  output scan_out;
assign fdin[ 0 : 0 ] = (din[ 0 : 0 ] & {1{en}}) | (dout[ 0 : 0 ] & ~{1{en}});


cl_sc1_msff_4x d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 0 ]),
.si(scan_in),
.so(scan_out),
.q(dout[ 0 ])
);


endmodule


// any PARAMS parms go into naming of macro

module msff_ctl_macro__en_1__width_5 (
  din, 
  en, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;
wire [4:1] sout;

  input [ 4 : 0 ] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [ 4 : 0 ] dout;
  output scan_out;
assign fdin[ 4 : 0 ] = (din[ 4 : 0 ] & {5{en}}) | (dout[ 4 : 0 ] & ~{5{en}});


cl_sc1_msff_4x d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 0 ]),
.si(sout[ 1 ]),
.so(scan_out),
.q(dout[ 0 ])
);
cl_sc1_msff_4x d0_1 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 1 ]),
.si(sout[ 2 ]),
.so(sout[ 1 ]),
.q(dout[ 1 ])
);
cl_sc1_msff_4x d0_2 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 2 ]),
.si(sout[ 3 ]),
.so(sout[ 2 ]),
.q(dout[ 2 ])
);
cl_sc1_msff_4x d0_3 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 3 ]),
.si(sout[ 4 ]),
.so(sout[ 3 ]),
.q(dout[ 3 ])
);
cl_sc1_msff_4x d0_4 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 4 ]),
.si(scan_in),
.so(sout[ 4 ]),
.q(dout[ 4 ])
);


endmodule


//  Description:        Spare gate macro for control blocks
//
//  Param num controls the number of times the macro is added
//  flops=0 can be used to use only combination spare logic


module spare_ctl_macro__num_4 (
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  scan_out);
wire si_0;
wire so_0;
wire spare0_flop_unused;
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire si_1;
wire so_1;
wire spare1_flop_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire si_2;
wire so_2;
wire spare2_flop_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire si_3;
wire so_3;
wire spare3_flop_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;


input		l1clk;
input		scan_in;
input		siclk;
input		soclk;
output		scan_out;

cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_0),
                               .so(so_0),
                               .d(1'b0),
                               .q(spare0_flop_unused));
assign si_0 = scan_in;

cl_u1_buf_32x   spare0_buf_32x (.in(1'b1),
                                   .out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare0_nand3_8x_unused));
cl_u1_inv_8x    spare0_inv_8x (.in(1'b1),
                                  .out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_aoi22_4x_unused));
cl_u1_buf_8x    spare0_buf_8x (.in(1'b1),
                                  .out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare0_oai22_4x_unused));
cl_u1_inv_16x   spare0_inv_16x (.in(1'b1),
                                   .out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare0_nand2_8x_unused));
cl_u1_buf_16x   spare0_buf_16x (.in(1'b1),
                                   .out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare0_nor2_16x_unused));
cl_u1_inv_32x   spare0_inv_32x (.in(1'b1),
                                   .out(spare0_inv_32x_unused));

cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_1),
                               .so(so_1),
                               .d(1'b0),
                               .q(spare1_flop_unused));
assign si_1 = so_0;

cl_u1_buf_32x   spare1_buf_32x (.in(1'b1),
                                   .out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare1_nand3_8x_unused));
cl_u1_inv_8x    spare1_inv_8x (.in(1'b1),
                                  .out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_aoi22_4x_unused));
cl_u1_buf_8x    spare1_buf_8x (.in(1'b1),
                                  .out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare1_oai22_4x_unused));
cl_u1_inv_16x   spare1_inv_16x (.in(1'b1),
                                   .out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare1_nand2_8x_unused));
cl_u1_buf_16x   spare1_buf_16x (.in(1'b1),
                                   .out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare1_nor2_16x_unused));
cl_u1_inv_32x   spare1_inv_32x (.in(1'b1),
                                   .out(spare1_inv_32x_unused));

cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_2),
                               .so(so_2),
                               .d(1'b0),
                               .q(spare2_flop_unused));
assign si_2 = so_1;

cl_u1_buf_32x   spare2_buf_32x (.in(1'b1),
                                   .out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare2_nand3_8x_unused));
cl_u1_inv_8x    spare2_inv_8x (.in(1'b1),
                                  .out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_aoi22_4x_unused));
cl_u1_buf_8x    spare2_buf_8x (.in(1'b1),
                                  .out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare2_oai22_4x_unused));
cl_u1_inv_16x   spare2_inv_16x (.in(1'b1),
                                   .out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare2_nand2_8x_unused));
cl_u1_buf_16x   spare2_buf_16x (.in(1'b1),
                                   .out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare2_nor2_16x_unused));
cl_u1_inv_32x   spare2_inv_32x (.in(1'b1),
                                   .out(spare2_inv_32x_unused));

cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
                               .siclk(siclk),
                               .soclk(soclk),
                               .si(si_3),
                               .so(so_3),
                               .d(1'b0),
                               .q(spare3_flop_unused));
assign si_3 = so_2;

cl_u1_buf_32x   spare3_buf_32x (.in(1'b1),
                                   .out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .in2(1'b1),
                                   .out(spare3_nand3_8x_unused));
cl_u1_inv_8x    spare3_inv_8x (.in(1'b1),
                                  .out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_aoi22_4x_unused));
cl_u1_buf_8x    spare3_buf_8x (.in(1'b1),
                                  .out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
                                   .in01(1'b1),
                                   .in10(1'b1),
                                   .in11(1'b1),
                                   .out(spare3_oai22_4x_unused));
cl_u1_inv_16x   spare3_inv_16x (.in(1'b1),
                                   .out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
                                     .in1(1'b1),
                                     .out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
                                 .in1(1'b0),
                                 .in2(1'b0),
                                 .out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
                                   .in1(1'b1),
                                   .out(spare3_nand2_8x_unused));
cl_u1_buf_16x   spare3_buf_16x (.in(1'b1),
                                   .out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
                                   .in1(1'b0),
                                   .out(spare3_nor2_16x_unused));
cl_u1_inv_32x   spare3_inv_32x (.in(1'b1),
                                   .out(spare3_inv_32x_unused));
assign scan_out = so_3;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_dca_sp_9kb_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef FPGA
module n2_dca_sp_9kb_cust (
  dcache_rd_addr_e, 
  dcache_alt_addr_e, 
  dcache_alt_addr_sel_e, 
  dcache_rvld_e, 
  dcache_wvld_e, 
  dcache_clk_en_e, 
  dcache_wclk_en_e, 
  dcache_rclk_en_m, 
  dcache_wdata_e, 
  dcache_wr_way_e, 
  dcache_byte_wr_en_e, 
  dcache_alt_rsel_way_m, 
  dcache_rsel_way_b, 
  dcache_alt_way_sel_m, 
  lsu_l2fill_or_byp_data_m, 
  dcache_bypass_e_, 
  dcache_rdata_b, 
  dcache_rparity_b, 
  dcache_perr_w0_b, 
  dcache_perr_w1_b, 
  dcache_perr_w2_b, 
  dcache_perr_w3_b, 
  dcache_rdata_msb_w0_b, 
  dcache_rdata_msb_w1_b, 
  dcache_rdata_msb_w2_b, 
  dcache_rdata_msb_w3_b, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_array_wr_inhibit, 
  tcu_scan_en, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  scan_out, 
  fuse_dca_repair_value, 
  fuse_dca_repair_en, 
  fuse_dca_rid, 
  fuse_dca_wen, 
  fuse_red_reset, 
  dca_fuse_repair_value, 
  dca_fuse_repair_en, 
  vnw_ary);
wire l1clk_in;
wire l1clk_in_pm;
wire l1clk_out_pm;
wire l1clk_out;
wire l1clk_free;
wire l1clk_free_wpm;
wire l1clk_red;
wire [10:3] dcache_rwaddr_e;
wire [7:0] lat_addr_scanin;
wire [7:0] lat_addr_scanout;
wire [10:3] dcache_rwaddr_eb;
wire [10:3] dcache_rwaddr_l_unused;
wire [3:0] wr_way_dec_e;
wire [6:0] lat_ctl_eb_scanin;
wire [6:0] lat_ctl_eb_scanout;
wire dcache_rvld_top_eb;
wire dcache_rvld_bot_eb;
wire dcache_wvld_eb;
wire [3:0] wr_way_dec_eb;
wire [6:0] lat_ctl_unused;
wire [2:0] dff_ctl_m_0_scanin;
wire [2:0] dff_ctl_m_0_scanout;
wire dcache_rvld_m;
wire dcache_wvld_m;
wire dcache_bypass_m_;
wire [15:0] dff_ctl_m_1_scanin;
wire [15:0] dff_ctl_m_1_scanout;
wire [15:0] byte_wr_en_eb;
wire [15:0] dff_ctl_l_unused;
wire [4:0] dff_ctl_b_scanin;
wire [4:0] dff_ctl_b_scanout;
wire dcache_alt_way_sel_b;
wire [3:0] dcache_alt_rsel_way_b;
wire [143:0] dff_wdata_m_scanin;
wire [143:0] dff_wdata_m_scanout;
wire [15:0] dcache_wparity_m;
wire [127:0] dcache_wdata_m;
wire [5:0] fuse_dca_repair_value_ff;
wire [1:0] fuse_dca_repair_en_ff;
wire [1:0] fuse_dca_rid_ff;
wire fuse_dca_wen_ff;
wire fuse_red_reset_ff;
wire [5:0] dca_fuse_repair_value_pre;
wire [1:0] dca_fuse_repair_en_pre;
wire [63:0] dcache_rdata_w0_m;
wire [63:0] rdata_w0_m;
wire [63:0] rdata_w1_m;
wire [63:0] dcache_rdata_w1_m;
wire [63:0] rdata_w2_m;
wire [63:0] dcache_rdata_w2_m;
wire [63:0] rdata_w3_m;
wire [63:0] dcache_rdata_w3_m;
wire [7:0] dff_msb_w0_scanin;
wire [7:0] dff_msb_w0_scanout;
wire [7:0] dff_msb_w1_scanin;
wire [7:0] dff_msb_w1_scanout;
wire [7:0] dff_msb_w2_scanin;
wire [7:0] dff_msb_w2_scanout;
wire [7:0] dff_msb_w3_scanin;
wire [7:0] dff_msb_w3_scanout;
wire [63:0] dff_rdata_w0_m_scanin;
wire [63:0] dff_rdata_w0_m_scanout;
wire [63:0] rdata_w0_b;
wire [7:0] dff_rparity_w0_m_scanin;
wire [7:0] dff_rparity_w0_m_scanout;
wire [7:0] rparity_w0_m;
wire [7:0] rparity_w0_b;
wire [63:0] dff_rdata_w1_m_scanin;
wire [63:0] dff_rdata_w1_m_scanout;
wire [63:0] rdata_w1_b;
wire [7:0] dff_rparity_w1_m_scanin;
wire [7:0] dff_rparity_w1_m_scanout;
wire [7:0] rparity_w1_m;
wire [7:0] rparity_w1_b;
wire [63:0] dff_rdata_w2_m_scanin;
wire [63:0] dff_rdata_w2_m_scanout;
wire [63:0] rdata_w2_b;
wire [7:0] dff_rparity_w2_m_scanin;
wire [7:0] dff_rparity_w2_m_scanout;
wire [7:0] rparity_w2_m;
wire [7:0] rparity_w2_b;
wire [63:0] dff_rdata_w3_m_scanin;
wire [63:0] dff_rdata_w3_m_scanout;
wire [63:0] rdata_w3_b;
wire [7:0] dff_rparity_w3_m_scanin;
wire [7:0] dff_rparity_w3_m_scanout;
wire [7:0] rparity_w3_m;
wire [7:0] rparity_w3_b;
wire [3:0] dcache_rd_sel_way_b;
wire w0_p0_0;
wire w0_p0_1;
wire w0_p0_2;
wire [7:0] w0_parity_m;
wire w0_p1_0;
wire w0_p1_1;
wire w0_p1_2;
wire w0_p2_0;
wire w0_p2_1;
wire w0_p2_2;
wire w0_p3_0;
wire w0_p3_1;
wire w0_p3_2;
wire w0_p4_0;
wire w0_p4_1;
wire w0_p4_2;
wire w0_p5_0;
wire w0_p5_1;
wire w0_p5_2;
wire w0_p6_0;
wire w0_p6_1;
wire w0_p6_2;
wire w0_p7_0;
wire w0_p7_1;
wire w0_p7_2;
wire w1_p0_0;
wire w1_p0_1;
wire w1_p0_2;
wire [7:0] w1_parity_m;
wire w1_p1_0;
wire w1_p1_1;
wire w1_p1_2;
wire w1_p2_0;
wire w1_p2_1;
wire w1_p2_2;
wire w1_p3_0;
wire w1_p3_1;
wire w1_p3_2;
wire w1_p4_0;
wire w1_p4_1;
wire w1_p4_2;
wire w1_p5_0;
wire w1_p5_1;
wire w1_p5_2;
wire w1_p6_0;
wire w1_p6_1;
wire w1_p6_2;
wire w1_p7_0;
wire w1_p7_1;
wire w1_p7_2;
wire w2_p0_0;
wire w2_p0_1;
wire w2_p0_2;
wire [7:0] w2_parity_m;
wire w2_p1_0;
wire w2_p1_1;
wire w2_p1_2;
wire w2_p2_0;
wire w2_p2_1;
wire w2_p2_2;
wire w2_p3_0;
wire w2_p3_1;
wire w2_p3_2;
wire w2_p4_0;
wire w2_p4_1;
wire w2_p4_2;
wire w2_p5_0;
wire w2_p5_1;
wire w2_p5_2;
wire w2_p6_0;
wire w2_p6_1;
wire w2_p6_2;
wire w2_p7_0;
wire w2_p7_1;
wire w2_p7_2;
wire w3_p0_0;
wire w3_p0_1;
wire w3_p0_2;
wire [7:0] w3_parity_m;
wire w3_p1_0;
wire w3_p1_1;
wire w3_p1_2;
wire w3_p2_0;
wire w3_p2_1;
wire w3_p2_2;
wire w3_p3_0;
wire w3_p3_1;
wire w3_p3_2;
wire w3_p4_0;
wire w3_p4_1;
wire w3_p4_2;
wire w3_p5_0;
wire w3_p5_1;
wire w3_p5_2;
wire w3_p6_0;
wire w3_p6_1;
wire w3_p6_2;
wire w3_p7_0;
wire w3_p7_1;
wire w3_p7_2;
wire [7:0] dff_byte_perr_w0_scanin;
wire [7:0] dff_byte_perr_w0_scanout;
wire [7:0] w0_parity_b;
wire [7:0] dff_byte_perr_w1_scanin;
wire [7:0] dff_byte_perr_w1_scanout;
wire [7:0] w1_parity_b;
wire [7:0] dff_byte_perr_w2_scanin;
wire [7:0] dff_byte_perr_w2_scanout;
wire [7:0] w2_parity_b;
wire [7:0] dff_byte_perr_w3_scanin;
wire [7:0] dff_byte_perr_w3_scanout;
wire [7:0] w3_parity_b;
wire w0_parity_err_b;
wire w1_parity_err_b;
wire w2_parity_err_b;
wire w3_parity_err_b;
wire [11:0] dff_red_in_scanin;
wire [11:0] dff_red_in_scanout;
wire [7:0] dff_red_out_scanin;
wire [7:0] dff_red_out_scanout;
 

input [10:3]    dcache_rd_addr_e;     // read cache index [10:4] + bit [3] offset
input [10:3]    dcache_alt_addr_e;    // write/bist/diagnostic read cache index + offset 
input           dcache_alt_addr_sel_e;

input           dcache_rvld_e;        // read accesses d$.
input           dcache_wvld_e;        // valid write setup to m-stage.
// 0in bits_on -var {dcache_rvld_e,dcache_wvld_e} -max 1 -message "Attempt to read AND write dcache on same cycle"
input           dcache_clk_en_e;      // array clock enable
input           dcache_wclk_en_e;     // write data/byte_wr_en flops clock enable
input           dcache_rclk_en_m;     // read flops clock enable
   
input [143:0]   dcache_wdata_e;       // write data - 16Bx8 + 8b parity.
input [1:0]     dcache_wr_way_e;     // replacement way for load miss/store (encoded).
input [15:0]    dcache_byte_wr_en_e;  // 16b byte wr enable for stores.

input [3:0]     dcache_alt_rsel_way_m;// bist/diagnostic read way select
input [3:0]     dcache_rsel_way_b;    // load way select, connect to cache_way_hit
input           dcache_alt_way_sel_m;
       
input [63:0]	lsu_l2fill_or_byp_data_m;
input       	dcache_bypass_e_;
   
output  [63:0]  dcache_rdata_b;
output  [7:0]   dcache_rparity_b;
   
output  	dcache_perr_w0_b; 
output  	dcache_perr_w1_b; 
output  	dcache_perr_w2_b; 
output  	dcache_perr_w3_b; 

output [7:0] dcache_rdata_msb_w0_b;
output [7:0] dcache_rdata_msb_w1_b;
output [7:0] dcache_rdata_msb_w2_b;
output [7:0] dcache_rdata_msb_w3_b;
   
input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_array_wr_inhibit;
input		tcu_scan_en;
input		tcu_se_scancollar_in;
input		tcu_se_scancollar_out;
output          scan_out;

input	[5:0]	fuse_dca_repair_value;
input	[1:0]	fuse_dca_repair_en;
input	[1:0]	fuse_dca_rid;
input		fuse_dca_wen;
input		fuse_red_reset;
output	[5:0]	dca_fuse_repair_value;
output	[1:0]	dca_fuse_repair_en;

input		vnw_ary;

// synopsys translate_off

// 0in bits_on -var {~dcache_clk_en_e,dcache_wvld_e} -max 1 -message "Attempt to write with clk_en disabled"
// 0in bits_on -var {~dcache_clk_en_e,dcache_rvld_e} -max 1 -message "Attempt to read with clk_en disabled"
// 0in bits_on -var {~dcache_wclk_en_e,dcache_wvld_e} -max 1 -message "Attempt to write with wclk_en disabled"
// 0in bits_on -var {~dcache_rclk_en_m,dcache_rvld_m} -max 1 -message "Attempt to read with rclk_en disabled"
// 0in bits_on -var {~dcache_bypass_e_,dcache_rvld_e} -max 1 -message "Read and bypass both active"

wire pce_ov = tcu_pce_ov;
wire stop   = 1'b0;
wire siclk  = tcu_aclk ;
wire soclk  = tcu_bclk;

//================================================
// Clock headers
//================================================
n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_in (
        .l2clk	(l2clk), 
        .l1en 	(1'b1), 
	.pce_ov	(1'b1),
	.se	(tcu_se_scancollar_in),
        .l1clk	(l1clk_in),
  .stop(stop)
);

n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_in_pm (
        .l2clk	(l2clk), 
        .l1en 	(dcache_wclk_en_e), 
	.se	(tcu_se_scancollar_in),
        .l1clk	(l1clk_in_pm),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_out_pm (
        .l2clk	(l2clk), 
        .l1en 	(dcache_rclk_en_m), 
	.se	(tcu_se_scancollar_out),
        .l1clk	(l1clk_out_pm),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_out (
        .l2clk	(l2clk), 
        .l1en 	(1'b1), 
	.pce_ov	(1'b1),
	.se	(tcu_se_scancollar_out),
        .l1clk	(l1clk_out),
  .stop(stop)
);

n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_free (
        .l2clk	(l2clk), 
        .l1en 	(dcache_clk_en_e), 
	.se	(tcu_scan_en),
        .l1clk	(l1clk_free),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_free_wpm (
        .l2clk	(l2clk), 
        .l1en 	(dcache_wclk_en_e), 
	.se	(tcu_scan_en),
        .l1clk	(l1clk_free_wpm),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro l1ch_red (
        .l2clk	(l2clk), 
        .l1en 	(1'b1), 
	.pce_ov	(1'b1),
	.se	(1'b0),
        .l1clk	(l1clk_red),
  .stop(stop)
);

//=========================================================================================
//  Input flops
//=========================================================================================

// BIST Rd used fill address port.
n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_8 mx_addr_e    (
	.din0	(dcache_alt_addr_e[10:3]),
	.din1	(dcache_rd_addr_e[10:3]),
	.sel0	(dcache_alt_addr_sel_e),
	.dout	(dcache_rwaddr_e[10:3])
);
   
n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_8 lat_addr   (
        .scan_in(lat_addr_scanin[7:0]),
        .scan_out(lat_addr_scanout[7:0]),
        .l1clk		(l1clk_in),
	.d		(dcache_rwaddr_e[10:3]),
	.latout		(dcache_rwaddr_eb[10:3]),
	.latout_l	(dcache_rwaddr_l_unused[10:3]),
  .siclk(siclk),
  .soclk(soclk)
);

// This is just a 2:4 decoder
n2_dca_sp_9kb_cust_mux_macro__mux_aodec__ports_4__width_4 wr_way_decode    (
	.din0	(4'b0001),
	.din1	(4'b0010),
	.din2	(4'b0100),
	.din3	(4'b1000),
	.sel	(dcache_wr_way_e[1:0]),
	.dout	(wr_way_dec_e[3:0])
);

n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_7 lat_ctl_eb   (
        .scan_in(lat_ctl_eb_scanin[6:0]),
        .scan_out(lat_ctl_eb_scanout[6:0]),
        .l1clk		(l1clk_in),
	.d		({dcache_rvld_e,     dcache_rvld_e,     dcache_wvld_e, wr_way_dec_e[3:0]}),
	.latout		({dcache_rvld_top_eb,dcache_rvld_bot_eb,dcache_wvld_eb,wr_way_dec_eb[3:0]}),
	.latout_l	(lat_ctl_unused[6:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_3 dff_ctl_m_0  (
     .scan_in(dff_ctl_m_0_scanin[2:0]),
     .scan_out(dff_ctl_m_0_scanout[2:0]),
	.l1clk	(l1clk_in),
	.din	({dcache_rvld_e,dcache_wvld_e,dcache_bypass_e_}),
	.dout	({dcache_rvld_m,dcache_wvld_m,dcache_bypass_m_}),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_16 dff_ctl_m_1   (
	.scan_in(dff_ctl_m_1_scanin[15:0]),
	.scan_out(dff_ctl_m_1_scanout[15:0]),
	.l1clk		(l1clk_in_pm),
	.d		(dcache_byte_wr_en_e[15:0]),
	.latout		(byte_wr_en_eb[15:0]),
	.latout_l	(dff_ctl_l_unused[15:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_5 dff_ctl_b  (
     .scan_in(dff_ctl_b_scanin[4:0]),
     .scan_out(dff_ctl_b_scanout[4:0]),
	.l1clk	(l1clk_in),
	.din	({dcache_alt_way_sel_m,dcache_alt_rsel_way_m[3:0]}),
	.dout	({dcache_alt_way_sel_b,dcache_alt_rsel_way_b[3:0]}),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_144 dff_wdata_m  (
     .scan_in(dff_wdata_m_scanin[143:0]),
     .scan_out(dff_wdata_m_scanout[143:0]),
	.l1clk	(l1clk_in_pm),
	.din	(dcache_wdata_e[143:0]),
        .dout	({dcache_wparity_m[15],dcache_wdata_m[127:120],
		  dcache_wparity_m[14],dcache_wdata_m[119:112],
		  dcache_wparity_m[13],dcache_wdata_m[111:104],
		  dcache_wparity_m[12],dcache_wdata_m[103:96],
		  dcache_wparity_m[11],dcache_wdata_m[95:88],
		  dcache_wparity_m[10],dcache_wdata_m[87:80],
		  dcache_wparity_m[9],dcache_wdata_m[79:72],
		  dcache_wparity_m[8],dcache_wdata_m[71:64],
		  dcache_wparity_m[7],dcache_wdata_m[63:56],
		  dcache_wparity_m[6],dcache_wdata_m[55:48],
		  dcache_wparity_m[5],dcache_wdata_m[47:40],
		  dcache_wparity_m[4],dcache_wdata_m[39:32],
		  dcache_wparity_m[3],dcache_wdata_m[31:24],
		  dcache_wparity_m[2],dcache_wdata_m[23:16],
		  dcache_wparity_m[1],dcache_wdata_m[15:8],
		  dcache_wparity_m[0],dcache_wdata_m[7:0] }),
  .siclk(siclk),
  .soclk(soclk)
);


n2_dca_sp_9kb_array array (
	.l1clk			(l1clk_free),
	.l1clk_wr		(l1clk_free_wpm),
	.addr_b			(dcache_rwaddr_eb[10:3]),
	.rd_en_top_b		(dcache_rvld_top_eb),
	.rd_en_bot_b		(dcache_rvld_bot_eb),
	.rd_en_a		(dcache_rvld_m),
	.wr_en_b		(dcache_wvld_eb),
	.wr_en_a		(dcache_wvld_m),
	.wr_inh_b		(tcu_array_wr_inhibit),
	.byte_wr_en_b		(byte_wr_en_eb[15:0]),
	.wr_waysel_b		(wr_way_dec_eb[3:0]),
	.fuse_dca_repair_value	(fuse_dca_repair_value_ff[5:0]),
	.fuse_dca_repair_en	(fuse_dca_repair_en_ff[1:0]),
	.fuse_dca_rid		(fuse_dca_rid_ff[1:0]),
	.fuse_dca_wen		(fuse_dca_wen_ff),
	.fuse_red_reset		(fuse_red_reset_ff),
	.dca_fuse_repair_value	(dca_fuse_repair_value_pre[5:0]),
	.dca_fuse_repair_en	(dca_fuse_repair_en_pre[1:0]),
  .l1clk_red(l1clk_red),
  .dcache_wdata_m(dcache_wdata_m[127:0]),
  .dcache_wparity_m(dcache_wparity_m[15:0]),
  .dcache_rdata_w0_m(dcache_rdata_w0_m[63:0]),
  .rparity_w0_m(rparity_w0_m[7:0]),
  .dcache_rdata_w1_m(dcache_rdata_w1_m[63:0]),
  .rparity_w1_m(rparity_w1_m[7:0]),
  .dcache_rdata_w2_m(dcache_rdata_w2_m[63:0]),
  .rparity_w2_m(rparity_w2_m[7:0]),
  .dcache_rdata_w3_m(dcache_rdata_w3_m[63:0]),
  .rparity_w3_m(rparity_w3_m[7:0]),
  .vnw_ary(vnw_ary)
);


// mux fill/bypass data into way0 here so that it's not in the critical B stage path
n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_64 mx_way0_data    (
	.din0	(dcache_rdata_w0_m[63:0]),
	.din1	(lsu_l2fill_or_byp_data_m[63:0]),
	.sel0	(dcache_bypass_m_),
	.dout	(rdata_w0_m[63:0])
);
assign rdata_w1_m[63:0] = dcache_rdata_w1_m[63:0];
assign rdata_w2_m[63:0] = dcache_rdata_w2_m[63:0];
assign rdata_w3_m[63:0] = dcache_rdata_w3_m[63:0];

//=========================================================================================
//  Output flops
//=========================================================================================

n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_msb_w0  (
     .scan_in(dff_msb_w0_scanin[7:0]),
     .scan_out(dff_msb_w0_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	({dcache_rdata_w0_m[63],dcache_rdata_w0_m[55],dcache_rdata_w0_m[47],dcache_rdata_w0_m[39],
		  dcache_rdata_w0_m[31],dcache_rdata_w0_m[23],dcache_rdata_w0_m[15],dcache_rdata_w0_m[7]}),
	.dout	(dcache_rdata_msb_w0_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_msb_w1  (
     .scan_in(dff_msb_w1_scanin[7:0]),
     .scan_out(dff_msb_w1_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	({dcache_rdata_w1_m[63],dcache_rdata_w1_m[55],dcache_rdata_w1_m[47],dcache_rdata_w1_m[39],
		  dcache_rdata_w1_m[31],dcache_rdata_w1_m[23],dcache_rdata_w1_m[15],dcache_rdata_w1_m[7]}),
	.dout	(dcache_rdata_msb_w1_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_msb_w2  (
     .scan_in(dff_msb_w2_scanin[7:0]),
     .scan_out(dff_msb_w2_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	({dcache_rdata_w2_m[63],dcache_rdata_w2_m[55],dcache_rdata_w2_m[47],dcache_rdata_w2_m[39],
		  dcache_rdata_w2_m[31],dcache_rdata_w2_m[23],dcache_rdata_w2_m[15],dcache_rdata_w2_m[7]}),
	.dout	(dcache_rdata_msb_w2_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_msb_w3  (
     .scan_in(dff_msb_w3_scanin[7:0]),
     .scan_out(dff_msb_w3_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	({dcache_rdata_w3_m[63],dcache_rdata_w3_m[55],dcache_rdata_w3_m[47],dcache_rdata_w3_m[39],
		  dcache_rdata_w3_m[31],dcache_rdata_w3_m[23],dcache_rdata_w3_m[15],dcache_rdata_w3_m[7]}),
	.dout	(dcache_rdata_msb_w3_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 dff_rdata_w0_m  (
     .scan_in(dff_rdata_w0_m_scanin[63:0]),
     .scan_out(dff_rdata_w0_m_scanout[63:0]),
	.l1clk	(l1clk_out_pm),
	.din	(rdata_w0_m[63:0]),
	.dout	(rdata_w0_b[63:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_rparity_w0_m  (
     .scan_in(dff_rparity_w0_m_scanin[7:0]),
     .scan_out(dff_rparity_w0_m_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	(rparity_w0_m[7:0]),
	.dout	(rparity_w0_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 dff_rdata_w1_m  (
     .scan_in(dff_rdata_w1_m_scanin[63:0]),
     .scan_out(dff_rdata_w1_m_scanout[63:0]),
	.l1clk	(l1clk_out_pm),
	.din	(rdata_w1_m[63:0]),
	.dout	(rdata_w1_b[63:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_rparity_w1_m  (
     .scan_in(dff_rparity_w1_m_scanin[7:0]),
     .scan_out(dff_rparity_w1_m_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	(rparity_w1_m[7:0]),
	.dout	(rparity_w1_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 dff_rdata_w2_m  (
     .scan_in(dff_rdata_w2_m_scanin[63:0]),
     .scan_out(dff_rdata_w2_m_scanout[63:0]),
	.l1clk	(l1clk_out_pm),
	.din	(rdata_w2_m[63:0]),
	.dout	(rdata_w2_b[63:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_rparity_w2_m  (
     .scan_in(dff_rparity_w2_m_scanin[7:0]),
     .scan_out(dff_rparity_w2_m_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	(rparity_w2_m[7:0]),
	.dout	(rparity_w2_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 dff_rdata_w3_m  (
     .scan_in(dff_rdata_w3_m_scanin[63:0]),
     .scan_out(dff_rdata_w3_m_scanout[63:0]),
	.l1clk	(l1clk_out_pm),
	.din	(rdata_w3_m[63:0]),
	.dout	(rdata_w3_b[63:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_rparity_w3_m  (
     .scan_in(dff_rparity_w3_m_scanin[7:0]),
     .scan_out(dff_rparity_w3_m_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	(rparity_w3_m[7:0]),
	.dout	(rparity_w3_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

//=========================================================================================
//  Way select
//=========================================================================================

n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_4 mx_sel_way    (
	.din0	(dcache_alt_rsel_way_b[3:0]),
	.din1	(dcache_rsel_way_b[3:0]),
	.sel0	(dcache_alt_way_sel_b),
	.dout	(dcache_rd_sel_way_b[3:0])
);
   
n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_4__width_64 mx_rdata_b    (
	.din0	(rdata_w0_b[63:0]),
	.din1	(rdata_w1_b[63:0]),
	.din2	(rdata_w2_b[63:0]),
	.din3	(rdata_w3_b[63:0]),
	.sel0	(dcache_rd_sel_way_b[0]),
	.sel1	(dcache_rd_sel_way_b[1]),
	.sel2	(dcache_rd_sel_way_b[2]),
	.sel3	(dcache_rd_sel_way_b[3]),
	.dout	(dcache_rdata_b[63:0])
);

n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_4__width_8 mx_rparity_b    (
	.din0	(rparity_w0_b[7:0]),
	.din1	(rparity_w1_b[7:0]),
	.din2	(rparity_w2_b[7:0]),
	.din3	(rparity_w3_b[7:0]),
	.sel0	(dcache_rd_sel_way_b[0]),
	.sel1	(dcache_rd_sel_way_b[1]),
	.sel2	(dcache_rd_sel_way_b[2]),
	.sel3	(dcache_rd_sel_way_b[3]),
	.dout	(dcache_rparity_b[7:0])
);

//=========================================================================================
// Parity check. Parity for each byte is calculated in M.  The result of all bytes is
// flopped and OR'ed in B. 
//=========================================================================================

// ***** Way 0 *****
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par0   (
	.din0({dcache_rdata_w0_m[0],dcache_rdata_w0_m[3],dcache_rdata_w0_m[6], w0_p0_0}),
	.din1({dcache_rdata_w0_m[1],dcache_rdata_w0_m[4],dcache_rdata_w0_m[7], w0_p0_1}),
	.din2({dcache_rdata_w0_m[2],dcache_rdata_w0_m[5],rparity_w0_m[0],w0_p0_2}),
	.dout({w0_p0_0,w0_p0_1,w0_p0_2,w0_parity_m[0]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par1   (
	.din0({dcache_rdata_w0_m[8],dcache_rdata_w0_m[11],dcache_rdata_w0_m[14], w0_p1_0}),
	.din1({dcache_rdata_w0_m[9],dcache_rdata_w0_m[12],dcache_rdata_w0_m[15], w0_p1_1}),
	.din2({dcache_rdata_w0_m[10],dcache_rdata_w0_m[13],rparity_w0_m[1],w0_p1_2}),
	.dout({w0_p1_0,w0_p1_1,w0_p1_2,w0_parity_m[1]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par2   (
	.din0({dcache_rdata_w0_m[16],dcache_rdata_w0_m[19],dcache_rdata_w0_m[22], w0_p2_0}),
	.din1({dcache_rdata_w0_m[17],dcache_rdata_w0_m[20],dcache_rdata_w0_m[23], w0_p2_1}),
	.din2({dcache_rdata_w0_m[18],dcache_rdata_w0_m[21],rparity_w0_m[2],w0_p2_2}),
	.dout({w0_p2_0,w0_p2_1,w0_p2_2,w0_parity_m[2]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par3   (
	.din0({dcache_rdata_w0_m[24],dcache_rdata_w0_m[27],dcache_rdata_w0_m[30], w0_p3_0}),
	.din1({dcache_rdata_w0_m[25],dcache_rdata_w0_m[28],dcache_rdata_w0_m[31], w0_p3_1}),
	.din2({dcache_rdata_w0_m[26],dcache_rdata_w0_m[29],rparity_w0_m[3],w0_p3_2}),
	.dout({w0_p3_0,w0_p3_1,w0_p3_2,w0_parity_m[3]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par4   (
	.din0({dcache_rdata_w0_m[32],dcache_rdata_w0_m[35],dcache_rdata_w0_m[38], w0_p4_0}),
	.din1({dcache_rdata_w0_m[33],dcache_rdata_w0_m[36],dcache_rdata_w0_m[39], w0_p4_1}),
	.din2({dcache_rdata_w0_m[34],dcache_rdata_w0_m[37],rparity_w0_m[4],w0_p4_2}),
	.dout({w0_p4_0,w0_p4_1,w0_p4_2,w0_parity_m[4]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par5   (
	.din0({dcache_rdata_w0_m[40],dcache_rdata_w0_m[43],dcache_rdata_w0_m[46], w0_p5_0}),
	.din1({dcache_rdata_w0_m[41],dcache_rdata_w0_m[44],dcache_rdata_w0_m[47], w0_p5_1}),
	.din2({dcache_rdata_w0_m[42],dcache_rdata_w0_m[45],rparity_w0_m[5],w0_p5_2}),
	.dout({w0_p5_0,w0_p5_1,w0_p5_2,w0_parity_m[5]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par6   (
	.din0({dcache_rdata_w0_m[48],dcache_rdata_w0_m[51],dcache_rdata_w0_m[54], w0_p6_0}),
	.din1({dcache_rdata_w0_m[49],dcache_rdata_w0_m[52],dcache_rdata_w0_m[55], w0_p6_1}),
	.din2({dcache_rdata_w0_m[50],dcache_rdata_w0_m[53],rparity_w0_m[6],w0_p6_2}),
	.dout({w0_p6_0,w0_p6_1,w0_p6_2,w0_parity_m[6]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w0_par7   (
	.din0({dcache_rdata_w0_m[56],dcache_rdata_w0_m[59],dcache_rdata_w0_m[62], w0_p7_0}),
	.din1({dcache_rdata_w0_m[57],dcache_rdata_w0_m[60],dcache_rdata_w0_m[63], w0_p7_1}),
	.din2({dcache_rdata_w0_m[58],dcache_rdata_w0_m[61],rparity_w0_m[7],w0_p7_2}),
	.dout({w0_p7_0,w0_p7_1,w0_p7_2,w0_parity_m[7]})
);
   
// ***** Way 1 *****
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par0   (
	.din0({dcache_rdata_w1_m[0],dcache_rdata_w1_m[3],dcache_rdata_w1_m[6], w1_p0_0}),
	.din1({dcache_rdata_w1_m[1],dcache_rdata_w1_m[4],dcache_rdata_w1_m[7], w1_p0_1}),
	.din2({dcache_rdata_w1_m[2],dcache_rdata_w1_m[5],rparity_w1_m[0],w1_p0_2}),
	.dout({w1_p0_0,w1_p0_1,w1_p0_2,w1_parity_m[0]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par1   (
	.din0({dcache_rdata_w1_m[8],dcache_rdata_w1_m[11],dcache_rdata_w1_m[14], w1_p1_0}),
	.din1({dcache_rdata_w1_m[9],dcache_rdata_w1_m[12],dcache_rdata_w1_m[15], w1_p1_1}),
	.din2({dcache_rdata_w1_m[10],dcache_rdata_w1_m[13],rparity_w1_m[1],w1_p1_2}),
	.dout({w1_p1_0,w1_p1_1,w1_p1_2,w1_parity_m[1]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par2   (
	.din0({dcache_rdata_w1_m[16],dcache_rdata_w1_m[19],dcache_rdata_w1_m[22], w1_p2_0}),
	.din1({dcache_rdata_w1_m[17],dcache_rdata_w1_m[20],dcache_rdata_w1_m[23], w1_p2_1}),
	.din2({dcache_rdata_w1_m[18],dcache_rdata_w1_m[21],rparity_w1_m[2],w1_p2_2}),
	.dout({w1_p2_0,w1_p2_1,w1_p2_2,w1_parity_m[2]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par3   (
	.din0({dcache_rdata_w1_m[24],dcache_rdata_w1_m[27],dcache_rdata_w1_m[30], w1_p3_0}),
	.din1({dcache_rdata_w1_m[25],dcache_rdata_w1_m[28],dcache_rdata_w1_m[31], w1_p3_1}),
	.din2({dcache_rdata_w1_m[26],dcache_rdata_w1_m[29],rparity_w1_m[3],w1_p3_2}),
	.dout({w1_p3_0,w1_p3_1,w1_p3_2,w1_parity_m[3]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par4   (
	.din0({dcache_rdata_w1_m[32],dcache_rdata_w1_m[35],dcache_rdata_w1_m[38], w1_p4_0}),
	.din1({dcache_rdata_w1_m[33],dcache_rdata_w1_m[36],dcache_rdata_w1_m[39], w1_p4_1}),
	.din2({dcache_rdata_w1_m[34],dcache_rdata_w1_m[37],rparity_w1_m[4],w1_p4_2}),
	.dout({w1_p4_0,w1_p4_1,w1_p4_2,w1_parity_m[4]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par5   (
	.din0({dcache_rdata_w1_m[40],dcache_rdata_w1_m[43],dcache_rdata_w1_m[46], w1_p5_0}),
	.din1({dcache_rdata_w1_m[41],dcache_rdata_w1_m[44],dcache_rdata_w1_m[47], w1_p5_1}),
	.din2({dcache_rdata_w1_m[42],dcache_rdata_w1_m[45],rparity_w1_m[5],w1_p5_2}),
	.dout({w1_p5_0,w1_p5_1,w1_p5_2,w1_parity_m[5]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par6   (
	.din0({dcache_rdata_w1_m[48],dcache_rdata_w1_m[51],dcache_rdata_w1_m[54], w1_p6_0}),
	.din1({dcache_rdata_w1_m[49],dcache_rdata_w1_m[52],dcache_rdata_w1_m[55], w1_p6_1}),
	.din2({dcache_rdata_w1_m[50],dcache_rdata_w1_m[53],rparity_w1_m[6],w1_p6_2}),
	.dout({w1_p6_0,w1_p6_1,w1_p6_2,w1_parity_m[6]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w1_par7   (
	.din0({dcache_rdata_w1_m[56],dcache_rdata_w1_m[59],dcache_rdata_w1_m[62], w1_p7_0}),
	.din1({dcache_rdata_w1_m[57],dcache_rdata_w1_m[60],dcache_rdata_w1_m[63], w1_p7_1}),
	.din2({dcache_rdata_w1_m[58],dcache_rdata_w1_m[61],rparity_w1_m[7],w1_p7_2}),
	.dout({w1_p7_0,w1_p7_1,w1_p7_2,w1_parity_m[7]})
);
   
// ***** Way 2 *****
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par0   (
	.din0({dcache_rdata_w2_m[0],dcache_rdata_w2_m[3],dcache_rdata_w2_m[6], w2_p0_0}),
	.din1({dcache_rdata_w2_m[1],dcache_rdata_w2_m[4],dcache_rdata_w2_m[7], w2_p0_1}),
	.din2({dcache_rdata_w2_m[2],dcache_rdata_w2_m[5],rparity_w2_m[0],w2_p0_2}),
	.dout({w2_p0_0,w2_p0_1,w2_p0_2,w2_parity_m[0]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par1   (
	.din0({dcache_rdata_w2_m[8],dcache_rdata_w2_m[11],dcache_rdata_w2_m[14], w2_p1_0}),
	.din1({dcache_rdata_w2_m[9],dcache_rdata_w2_m[12],dcache_rdata_w2_m[15], w2_p1_1}),
	.din2({dcache_rdata_w2_m[10],dcache_rdata_w2_m[13],rparity_w2_m[1],w2_p1_2}),
	.dout({w2_p1_0,w2_p1_1,w2_p1_2,w2_parity_m[1]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par2   (
	.din0({dcache_rdata_w2_m[16],dcache_rdata_w2_m[19],dcache_rdata_w2_m[22], w2_p2_0}),
	.din1({dcache_rdata_w2_m[17],dcache_rdata_w2_m[20],dcache_rdata_w2_m[23], w2_p2_1}),
	.din2({dcache_rdata_w2_m[18],dcache_rdata_w2_m[21],rparity_w2_m[2],w2_p2_2}),
	.dout({w2_p2_0,w2_p2_1,w2_p2_2,w2_parity_m[2]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par3   (
	.din0({dcache_rdata_w2_m[24],dcache_rdata_w2_m[27],dcache_rdata_w2_m[30], w2_p3_0}),
	.din1({dcache_rdata_w2_m[25],dcache_rdata_w2_m[28],dcache_rdata_w2_m[31], w2_p3_1}),
	.din2({dcache_rdata_w2_m[26],dcache_rdata_w2_m[29],rparity_w2_m[3],w2_p3_2}),
	.dout({w2_p3_0,w2_p3_1,w2_p3_2,w2_parity_m[3]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par4   (
	.din0({dcache_rdata_w2_m[32],dcache_rdata_w2_m[35],dcache_rdata_w2_m[38], w2_p4_0}),
	.din1({dcache_rdata_w2_m[33],dcache_rdata_w2_m[36],dcache_rdata_w2_m[39], w2_p4_1}),
	.din2({dcache_rdata_w2_m[34],dcache_rdata_w2_m[37],rparity_w2_m[4],w2_p4_2}),
	.dout({w2_p4_0,w2_p4_1,w2_p4_2,w2_parity_m[4]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par5   (
	.din0({dcache_rdata_w2_m[40],dcache_rdata_w2_m[43],dcache_rdata_w2_m[46], w2_p5_0}),
	.din1({dcache_rdata_w2_m[41],dcache_rdata_w2_m[44],dcache_rdata_w2_m[47], w2_p5_1}),
	.din2({dcache_rdata_w2_m[42],dcache_rdata_w2_m[45],rparity_w2_m[5],w2_p5_2}),
	.dout({w2_p5_0,w2_p5_1,w2_p5_2,w2_parity_m[5]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par6   (
	.din0({dcache_rdata_w2_m[48],dcache_rdata_w2_m[51],dcache_rdata_w2_m[54], w2_p6_0}),
	.din1({dcache_rdata_w2_m[49],dcache_rdata_w2_m[52],dcache_rdata_w2_m[55], w2_p6_1}),
	.din2({dcache_rdata_w2_m[50],dcache_rdata_w2_m[53],rparity_w2_m[6],w2_p6_2}),
	.dout({w2_p6_0,w2_p6_1,w2_p6_2,w2_parity_m[6]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w2_par7   (
	.din0({dcache_rdata_w2_m[56],dcache_rdata_w2_m[59],dcache_rdata_w2_m[62], w2_p7_0}),
	.din1({dcache_rdata_w2_m[57],dcache_rdata_w2_m[60],dcache_rdata_w2_m[63], w2_p7_1}),
	.din2({dcache_rdata_w2_m[58],dcache_rdata_w2_m[61],rparity_w2_m[7],w2_p7_2}),
	.dout({w2_p7_0,w2_p7_1,w2_p7_2,w2_parity_m[7]})
);
   
// ***** Way 3 *****
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par0   (
	.din0({dcache_rdata_w3_m[0],dcache_rdata_w3_m[3],dcache_rdata_w3_m[6], w3_p0_0}),
	.din1({dcache_rdata_w3_m[1],dcache_rdata_w3_m[4],dcache_rdata_w3_m[7], w3_p0_1}),
	.din2({dcache_rdata_w3_m[2],dcache_rdata_w3_m[5],rparity_w3_m[0],w3_p0_2}),
	.dout({w3_p0_0,w3_p0_1,w3_p0_2,w3_parity_m[0]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par1   (
	.din0({dcache_rdata_w3_m[8],dcache_rdata_w3_m[11],dcache_rdata_w3_m[14], w3_p1_0}),
	.din1({dcache_rdata_w3_m[9],dcache_rdata_w3_m[12],dcache_rdata_w3_m[15], w3_p1_1}),
	.din2({dcache_rdata_w3_m[10],dcache_rdata_w3_m[13],rparity_w3_m[1],w3_p1_2}),
	.dout({w3_p1_0,w3_p1_1,w3_p1_2,w3_parity_m[1]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par2   (
	.din0({dcache_rdata_w3_m[16],dcache_rdata_w3_m[19],dcache_rdata_w3_m[22], w3_p2_0}),
	.din1({dcache_rdata_w3_m[17],dcache_rdata_w3_m[20],dcache_rdata_w3_m[23], w3_p2_1}),
	.din2({dcache_rdata_w3_m[18],dcache_rdata_w3_m[21],rparity_w3_m[2],w3_p2_2}),
	.dout({w3_p2_0,w3_p2_1,w3_p2_2,w3_parity_m[2]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par3   (
	.din0({dcache_rdata_w3_m[24],dcache_rdata_w3_m[27],dcache_rdata_w3_m[30], w3_p3_0}),
	.din1({dcache_rdata_w3_m[25],dcache_rdata_w3_m[28],dcache_rdata_w3_m[31], w3_p3_1}),
	.din2({dcache_rdata_w3_m[26],dcache_rdata_w3_m[29],rparity_w3_m[3],w3_p3_2}),
	.dout({w3_p3_0,w3_p3_1,w3_p3_2,w3_parity_m[3]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par4   (
	.din0({dcache_rdata_w3_m[32],dcache_rdata_w3_m[35],dcache_rdata_w3_m[38], w3_p4_0}),
	.din1({dcache_rdata_w3_m[33],dcache_rdata_w3_m[36],dcache_rdata_w3_m[39], w3_p4_1}),
	.din2({dcache_rdata_w3_m[34],dcache_rdata_w3_m[37],rparity_w3_m[4],w3_p4_2}),
	.dout({w3_p4_0,w3_p4_1,w3_p4_2,w3_parity_m[4]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par5   (
	.din0({dcache_rdata_w3_m[40],dcache_rdata_w3_m[43],dcache_rdata_w3_m[46], w3_p5_0}),
	.din1({dcache_rdata_w3_m[41],dcache_rdata_w3_m[44],dcache_rdata_w3_m[47], w3_p5_1}),
	.din2({dcache_rdata_w3_m[42],dcache_rdata_w3_m[45],rparity_w3_m[5],w3_p5_2}),
	.dout({w3_p5_0,w3_p5_1,w3_p5_2,w3_parity_m[5]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par6   (
	.din0({dcache_rdata_w3_m[48],dcache_rdata_w3_m[51],dcache_rdata_w3_m[54], w3_p6_0}),
	.din1({dcache_rdata_w3_m[49],dcache_rdata_w3_m[52],dcache_rdata_w3_m[55], w3_p6_1}),
	.din2({dcache_rdata_w3_m[50],dcache_rdata_w3_m[53],rparity_w3_m[6],w3_p6_2}),
	.dout({w3_p6_0,w3_p6_1,w3_p6_2,w3_parity_m[6]})
);
n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 w3_par7   (
	.din0({dcache_rdata_w3_m[56],dcache_rdata_w3_m[59],dcache_rdata_w3_m[62], w3_p7_0}),
	.din1({dcache_rdata_w3_m[57],dcache_rdata_w3_m[60],dcache_rdata_w3_m[63], w3_p7_1}),
	.din2({dcache_rdata_w3_m[58],dcache_rdata_w3_m[61],rparity_w3_m[7],w3_p7_2}),
	.dout({w3_p7_0,w3_p7_1,w3_p7_2,w3_parity_m[7]})
);

n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_byte_perr_w0  (
     .scan_in(dff_byte_perr_w0_scanin[7:0]),
     .scan_out(dff_byte_perr_w0_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	(w0_parity_m[7:0]),
	.dout	(w0_parity_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_byte_perr_w1  (
     .scan_in(dff_byte_perr_w1_scanin[7:0]),
     .scan_out(dff_byte_perr_w1_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	(w1_parity_m[7:0]),
	.dout	(w1_parity_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_byte_perr_w2  (
     .scan_in(dff_byte_perr_w2_scanin[7:0]),
     .scan_out(dff_byte_perr_w2_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	(w2_parity_m[7:0]),
	.dout	(w2_parity_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);
n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_byte_perr_w3  (
     .scan_in(dff_byte_perr_w3_scanin[7:0]),
     .scan_out(dff_byte_perr_w3_scanout[7:0]),
	.l1clk	(l1clk_out_pm),
	.din	(w3_parity_m[7:0]),
	.dout	(w3_parity_b[7:0]),
  .siclk(siclk),
  .soclk(soclk)
);

// Funcionally this is just an OR gate.
n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 parity_w0    (
	.din0(1'b1), .din1(1'b1), .din2(1'b1), .din3(1'b1), .din4(1'b1), .din5(1'b1), .din6(1'b1), .din7(1'b1),
	.sel0(w0_parity_b[0]), .sel1(w0_parity_b[1]), .sel2(w0_parity_b[2]), .sel3(w0_parity_b[3]),
	.sel4(w0_parity_b[4]), .sel5(w0_parity_b[5]), .sel6(w0_parity_b[6]), .sel7(w0_parity_b[7]),
	.dout(w0_parity_err_b)
);
// Funcionally this is just an OR gate.
n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 parity_w1    (
	.din0(1'b1), .din1(1'b1), .din2(1'b1), .din3(1'b1), .din4(1'b1), .din5(1'b1), .din6(1'b1), .din7(1'b1),
	.sel0(w1_parity_b[0]), .sel1(w1_parity_b[1]), .sel2(w1_parity_b[2]), .sel3(w1_parity_b[3]),
	.sel4(w1_parity_b[4]), .sel5(w1_parity_b[5]), .sel6(w1_parity_b[6]), .sel7(w1_parity_b[7]),
	.dout(w1_parity_err_b)
);
// Funcionally this is just an OR gate.
n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 parity_w2    (
	.din0(1'b1), .din1(1'b1), .din2(1'b1), .din3(1'b1), .din4(1'b1), .din5(1'b1), .din6(1'b1), .din7(1'b1),
	.sel0(w2_parity_b[0]), .sel1(w2_parity_b[1]), .sel2(w2_parity_b[2]), .sel3(w2_parity_b[3]),
	.sel4(w2_parity_b[4]), .sel5(w2_parity_b[5]), .sel6(w2_parity_b[6]), .sel7(w2_parity_b[7]),
	.dout(w2_parity_err_b)
);
// Funcionally this is just an OR gate.
n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 parity_w3    (
	.din0(1'b1), .din1(1'b1), .din2(1'b1), .din3(1'b1), .din4(1'b1), .din5(1'b1), .din6(1'b1), .din7(1'b1),
	.sel0(w3_parity_b[0]), .sel1(w3_parity_b[1]), .sel2(w3_parity_b[2]), .sel3(w3_parity_b[3]),
	.sel4(w3_parity_b[4]), .sel5(w3_parity_b[5]), .sel6(w3_parity_b[6]), .sel7(w3_parity_b[7]),
	.dout(w3_parity_err_b)
);
   
assign dcache_perr_w0_b = w0_parity_err_b;
assign dcache_perr_w1_b = w1_parity_err_b;
assign dcache_perr_w2_b = w2_parity_err_b;
assign dcache_perr_w3_b = w3_parity_err_b;

//=========================================================================================
//  Redundancy flops
//=========================================================================================

n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_12 dff_red_in  (
     .scan_in(dff_red_in_scanin[11:0]),
     .scan_out(dff_red_in_scanout[11:0]),
	.l1clk	(l1clk_in),
	.din	({fuse_dca_repair_value[5:0],   fuse_dca_repair_en[1:0],
		  fuse_dca_rid[1:0],   fuse_dca_wen,   fuse_red_reset}),
	.dout	({fuse_dca_repair_value_ff[5:0],fuse_dca_repair_en_ff[1:0],
		  fuse_dca_rid_ff[1:0],fuse_dca_wen_ff,fuse_red_reset_ff}),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 dff_red_out  (
     .scan_in(dff_red_out_scanin[7:0]),
     .scan_out(dff_red_out_scanout[7:0]),
	.l1clk	(l1clk_out),
	.din	({dca_fuse_repair_value_pre[5:0],dca_fuse_repair_en_pre[1:0]}),
	.dout	({dca_fuse_repair_value[5:0],    dca_fuse_repair_en[1:0]}),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss;
supply1 vdd;

// scanorder start
// dff_byte_perr_w0_scanin[7]
// dff_byte_perr_w1_scanin[7]
// dff_byte_perr_w1_scanin[6]
// dff_byte_perr_w0_scanin[6]
// dff_byte_perr_w0_scanin[5]
// dff_byte_perr_w1_scanin[5]
// dff_byte_perr_w1_scanin[4]
// dff_byte_perr_w0_scanin[4]
// dff_wdata_m_scanin[143]
// dff_wdata_m_scanin[71]
// dff_rparity_w3_m_scanin[7]
// dff_rparity_w2_m_scanin[7]
// dff_rparity_w1_m_scanin[7]
// dff_rparity_w0_m_scanin[7]
// dff_wdata_m_scanin[134]
// dff_wdata_m_scanin[62]
// dff_rparity_w3_m_scanin[6]
// dff_rparity_w2_m_scanin[6]
// dff_rparity_w1_m_scanin[6]
// dff_rparity_w0_m_scanin[6]
// dff_wdata_m_scanin[142]
// dff_wdata_m_scanin[70]
// dff_rdata_w3_m_scanin[63]
// dff_rdata_w2_m_scanin[63]
// dff_rdata_w1_m_scanin[63]
// dff_rdata_w0_m_scanin[63]
// dff_wdata_m_scanin[133]
// dff_wdata_m_scanin[61]
// dff_rdata_w3_m_scanin[55]
// dff_rdata_w2_m_scanin[55]
// dff_rdata_w1_m_scanin[55]
// dff_rdata_w0_m_scanin[55]
// dff_wdata_m_scanin[141]
// dff_wdata_m_scanin[69]
// dff_rdata_w3_m_scanin[62]
// dff_rdata_w2_m_scanin[62]
// dff_rdata_w1_m_scanin[62]
// dff_rdata_w0_m_scanin[62]
// dff_wdata_m_scanin[132]
// dff_wdata_m_scanin[60]
// dff_rdata_w3_m_scanin[54]
// dff_rdata_w2_m_scanin[54]
// dff_rdata_w1_m_scanin[54]
// dff_rdata_w0_m_scanin[54]
// dff_wdata_m_scanin[140]
// dff_wdata_m_scanin[68]
// dff_rdata_w3_m_scanin[61]
// dff_rdata_w2_m_scanin[61]
// dff_rdata_w1_m_scanin[61]
// dff_rdata_w0_m_scanin[61]
// dff_wdata_m_scanin[131]
// dff_wdata_m_scanin[59]
// dff_rdata_w3_m_scanin[53]
// dff_rdata_w2_m_scanin[53]
// dff_rdata_w1_m_scanin[53]
// dff_rdata_w0_m_scanin[53]
// dff_wdata_m_scanin[139]
// dff_wdata_m_scanin[67]
// dff_rdata_w3_m_scanin[60]
// dff_rdata_w2_m_scanin[60]
// dff_rdata_w1_m_scanin[60]
// dff_rdata_w0_m_scanin[60]
// dff_wdata_m_scanin[130]
// dff_wdata_m_scanin[58]
// dff_rdata_w3_m_scanin[52]
// dff_rdata_w2_m_scanin[52]
// dff_rdata_w1_m_scanin[52]
// dff_rdata_w0_m_scanin[52]
// dff_wdata_m_scanin[138]
// dff_wdata_m_scanin[66]
// dff_rdata_w3_m_scanin[59]
// dff_rdata_w2_m_scanin[59]
// dff_rdata_w1_m_scanin[59]
// dff_rdata_w0_m_scanin[59]
// dff_wdata_m_scanin[129]
// dff_wdata_m_scanin[57]
// dff_rdata_w3_m_scanin[51]
// dff_rdata_w2_m_scanin[51]
// dff_rdata_w1_m_scanin[51]
// dff_rdata_w0_m_scanin[51]
// dff_wdata_m_scanin[137]
// dff_wdata_m_scanin[65]
// dff_rdata_w3_m_scanin[58]
// dff_rdata_w2_m_scanin[58]
// dff_rdata_w1_m_scanin[58]
// dff_rdata_w0_m_scanin[58]
// dff_wdata_m_scanin[128]
// dff_wdata_m_scanin[56]
// dff_rdata_w3_m_scanin[50]
// dff_rdata_w2_m_scanin[50]
// dff_rdata_w1_m_scanin[50]
// dff_rdata_w0_m_scanin[50]
// dff_wdata_m_scanin[136]
// dff_wdata_m_scanin[64]
// dff_rdata_w3_m_scanin[57]
// dff_rdata_w2_m_scanin[57]
// dff_rdata_w1_m_scanin[57]
// dff_rdata_w0_m_scanin[57]
// dff_wdata_m_scanin[127]
// dff_wdata_m_scanin[55]
// dff_rdata_w3_m_scanin[49]
// dff_rdata_w2_m_scanin[49]
// dff_rdata_w1_m_scanin[49]
// dff_rdata_w0_m_scanin[49]
// dff_wdata_m_scanin[135]
// dff_wdata_m_scanin[63]
// dff_rdata_w3_m_scanin[56]
// dff_rdata_w2_m_scanin[56]
// dff_rdata_w1_m_scanin[56]
// dff_rdata_w0_m_scanin[56]
// dff_wdata_m_scanin[126]
// dff_wdata_m_scanin[54]
// dff_rdata_w3_m_scanin[48]
// dff_rdata_w2_m_scanin[48]
// dff_rdata_w1_m_scanin[48]
// dff_rdata_w0_m_scanin[48]
// dff_wdata_m_scanin[125]
// dff_wdata_m_scanin[53]
// dff_rparity_w3_m_scanin[5]
// dff_rparity_w2_m_scanin[5]
// dff_rparity_w1_m_scanin[5]
// dff_rparity_w0_m_scanin[5]
// dff_wdata_m_scanin[116]
// dff_wdata_m_scanin[44]
// dff_rparity_w3_m_scanin[4]
// dff_rparity_w2_m_scanin[4]
// dff_rparity_w1_m_scanin[4]
// dff_rparity_w0_m_scanin[4]
// dff_wdata_m_scanin[124]
// dff_wdata_m_scanin[52]
// dff_rdata_w3_m_scanin[47]
// dff_rdata_w2_m_scanin[47]
// dff_rdata_w1_m_scanin[47]
// dff_rdata_w0_m_scanin[47]
// dff_wdata_m_scanin[115]
// dff_wdata_m_scanin[43]
// dff_rdata_w3_m_scanin[39]
// dff_rdata_w2_m_scanin[39]
// dff_rdata_w1_m_scanin[39]
// dff_rdata_w0_m_scanin[39]
// dff_wdata_m_scanin[123]
// dff_wdata_m_scanin[51]
// dff_rdata_w3_m_scanin[46]
// dff_rdata_w2_m_scanin[46]
// dff_rdata_w1_m_scanin[46]
// dff_rdata_w0_m_scanin[46]
// dff_wdata_m_scanin[114]
// dff_wdata_m_scanin[42]
// dff_rdata_w3_m_scanin[38]
// dff_rdata_w2_m_scanin[38]
// dff_rdata_w1_m_scanin[38]
// dff_rdata_w0_m_scanin[38]
// dff_wdata_m_scanin[122]
// dff_wdata_m_scanin[50]
// dff_rdata_w3_m_scanin[45]
// dff_rdata_w2_m_scanin[45]
// dff_rdata_w1_m_scanin[45]
// dff_rdata_w0_m_scanin[45]
// dff_wdata_m_scanin[113]
// dff_wdata_m_scanin[41]
// dff_rdata_w3_m_scanin[37]
// dff_rdata_w2_m_scanin[37]
// dff_rdata_w1_m_scanin[37]
// dff_rdata_w0_m_scanin[37]
// dff_wdata_m_scanin[121]
// dff_wdata_m_scanin[49]
// dff_rdata_w3_m_scanin[44]
// dff_rdata_w2_m_scanin[44]
// dff_rdata_w1_m_scanin[44]
// dff_rdata_w0_m_scanin[44]
// dff_wdata_m_scanin[112]
// dff_wdata_m_scanin[40]
// dff_rdata_w3_m_scanin[36]
// dff_rdata_w2_m_scanin[36]
// dff_rdata_w1_m_scanin[36]
// dff_rdata_w0_m_scanin[36]
// dff_wdata_m_scanin[120]
// dff_wdata_m_scanin[48]
// dff_rdata_w3_m_scanin[43]
// dff_rdata_w2_m_scanin[43]
// dff_rdata_w1_m_scanin[43]
// dff_rdata_w0_m_scanin[43]
// dff_wdata_m_scanin[111]
// dff_wdata_m_scanin[39]
// dff_rdata_w3_m_scanin[35]
// dff_rdata_w2_m_scanin[35]
// dff_rdata_w1_m_scanin[35]
// dff_rdata_w0_m_scanin[35]
// dff_wdata_m_scanin[119]
// dff_wdata_m_scanin[47]
// dff_rdata_w3_m_scanin[42]
// dff_rdata_w2_m_scanin[42]
// dff_rdata_w1_m_scanin[42]
// dff_rdata_w0_m_scanin[42]
// dff_wdata_m_scanin[110]
// dff_wdata_m_scanin[38]
// dff_rdata_w3_m_scanin[34]
// dff_rdata_w2_m_scanin[34]
// dff_rdata_w1_m_scanin[34]
// dff_rdata_w0_m_scanin[34]
// dff_wdata_m_scanin[118]
// dff_wdata_m_scanin[46]
// dff_rdata_w3_m_scanin[41]
// dff_rdata_w2_m_scanin[41]
// dff_rdata_w1_m_scanin[41]
// dff_rdata_w0_m_scanin[41]
// dff_wdata_m_scanin[109]
// dff_wdata_m_scanin[37]
// dff_rdata_w3_m_scanin[33]
// dff_rdata_w2_m_scanin[33]
// dff_rdata_w1_m_scanin[33]
// dff_rdata_w0_m_scanin[33]
// dff_wdata_m_scanin[117]
// dff_wdata_m_scanin[45]
// dff_rdata_w3_m_scanin[40]
// dff_rdata_w2_m_scanin[40]
// dff_rdata_w1_m_scanin[40]
// dff_rdata_w0_m_scanin[40]
// dff_wdata_m_scanin[108]
// dff_wdata_m_scanin[36]
// dff_rdata_w3_m_scanin[32]
// dff_rdata_w2_m_scanin[32]
// dff_rdata_w1_m_scanin[32]
// dff_rdata_w0_m_scanin[32]
// dff_ctl_m_1_scanin[15]
// dff_ctl_m_1_scanin[7]
// dff_ctl_m_1_scanin[14]
// dff_ctl_m_1_scanin[6]
// dff_ctl_m_1_scanin[13]
// dff_ctl_m_1_scanin[5]
// dff_ctl_m_1_scanin[12]
// dff_ctl_m_1_scanin[4]
// dff_byte_perr_w2_scanin[7]
// dff_byte_perr_w3_scanin[7]
// dff_byte_perr_w3_scanin[6]
// dff_byte_perr_w2_scanin[6]
// dff_byte_perr_w2_scanin[5]
// dff_byte_perr_w3_scanin[5]
// dff_byte_perr_w3_scanin[4]
// dff_byte_perr_w2_scanin[4]
// dff_ctl_m_0_scanin[0]
// dff_ctl_b_scanin[4]
// dff_ctl_b_scanin[0]
// dff_ctl_b_scanin[1]
// dff_ctl_b_scanin[2]
// dff_ctl_b_scanin[3]
// lat_ctl_eb_scanin[6]
// lat_ctl_eb_scanin[1]
// lat_ctl_eb_scanin[0]
// lat_ctl_eb_scanin[2]
// lat_ctl_eb_scanin[3]
// lat_addr_scanin[1]
// lat_addr_scanin[0]
// lat_addr_scanin[7]
// lat_addr_scanin[6]
// lat_addr_scanin[5]
// lat_addr_scanin[4]
// lat_addr_scanin[3]
// lat_addr_scanin[2]
// lat_ctl_eb_scanin[4]
// dff_ctl_m_0_scanin[1]
// dff_ctl_m_0_scanin[2]
// lat_ctl_eb_scanin[5]
// dff_byte_perr_w0_scanin[0]
// dff_byte_perr_w1_scanin[0]
// dff_byte_perr_w1_scanin[1]
// dff_byte_perr_w0_scanin[1]
// dff_byte_perr_w0_scanin[2]
// dff_byte_perr_w1_scanin[2]
// dff_byte_perr_w1_scanin[3]
// dff_byte_perr_w0_scanin[3]
// dff_wdata_m_scanin[80]
// dff_wdata_m_scanin[8]
// dff_rparity_w3_m_scanin[0]
// dff_rparity_w2_m_scanin[0]
// dff_rparity_w1_m_scanin[0]
// dff_rparity_w0_m_scanin[0]
// dff_wdata_m_scanin[89]
// dff_wdata_m_scanin[17]
// dff_rparity_w3_m_scanin[1]
// dff_rparity_w2_m_scanin[1]
// dff_rparity_w1_m_scanin[1]
// dff_rparity_w0_m_scanin[1]
// dff_wdata_m_scanin[72]
// dff_wdata_m_scanin[0]
// dff_rdata_w3_m_scanin[0]
// dff_rdata_w2_m_scanin[0]
// dff_rdata_w1_m_scanin[0]
// dff_rdata_w0_m_scanin[0]
// dff_wdata_m_scanin[81]
// dff_wdata_m_scanin[9]
// dff_rdata_w3_m_scanin[8]
// dff_rdata_w2_m_scanin[8]
// dff_rdata_w1_m_scanin[8]
// dff_rdata_w0_m_scanin[8]
// dff_wdata_m_scanin[73]
// dff_wdata_m_scanin[1]
// dff_rdata_w3_m_scanin[1]
// dff_rdata_w2_m_scanin[1]
// dff_rdata_w1_m_scanin[1]
// dff_rdata_w0_m_scanin[1]
// dff_wdata_m_scanin[82]
// dff_wdata_m_scanin[10]
// dff_rdata_w3_m_scanin[9]
// dff_rdata_w2_m_scanin[9]
// dff_rdata_w1_m_scanin[9]
// dff_rdata_w0_m_scanin[9]
// dff_wdata_m_scanin[74]
// dff_wdata_m_scanin[2]
// dff_rdata_w3_m_scanin[2]
// dff_rdata_w2_m_scanin[2]
// dff_rdata_w1_m_scanin[2]
// dff_rdata_w0_m_scanin[2]
// dff_wdata_m_scanin[83]
// dff_wdata_m_scanin[11]
// dff_rdata_w3_m_scanin[10]
// dff_rdata_w2_m_scanin[10]
// dff_rdata_w1_m_scanin[10]
// dff_rdata_w0_m_scanin[10]
// dff_wdata_m_scanin[75]
// dff_wdata_m_scanin[3]
// dff_rdata_w3_m_scanin[3]
// dff_rdata_w2_m_scanin[3]
// dff_rdata_w1_m_scanin[3]
// dff_rdata_w0_m_scanin[3]
// dff_wdata_m_scanin[84]
// dff_wdata_m_scanin[12]
// dff_rdata_w3_m_scanin[11]
// dff_rdata_w2_m_scanin[11]
// dff_rdata_w1_m_scanin[11]
// dff_rdata_w0_m_scanin[11]
// dff_wdata_m_scanin[76]
// dff_wdata_m_scanin[4]
// dff_rdata_w3_m_scanin[4]
// dff_rdata_w2_m_scanin[4]
// dff_rdata_w1_m_scanin[4]
// dff_rdata_w0_m_scanin[4]
// dff_wdata_m_scanin[85]
// dff_wdata_m_scanin[13]
// dff_rdata_w3_m_scanin[12]
// dff_rdata_w2_m_scanin[12]
// dff_rdata_w1_m_scanin[12]
// dff_rdata_w0_m_scanin[12]
// dff_wdata_m_scanin[77]
// dff_wdata_m_scanin[5]
// dff_rdata_w3_m_scanin[5]
// dff_rdata_w2_m_scanin[5]
// dff_rdata_w1_m_scanin[5]
// dff_rdata_w0_m_scanin[5]
// dff_wdata_m_scanin[86]
// dff_wdata_m_scanin[14]
// dff_rdata_w3_m_scanin[13]
// dff_rdata_w2_m_scanin[13]
// dff_rdata_w1_m_scanin[13]
// dff_rdata_w0_m_scanin[13]
// dff_wdata_m_scanin[78]
// dff_wdata_m_scanin[6]
// dff_rdata_w3_m_scanin[6]
// dff_rdata_w2_m_scanin[6]
// dff_rdata_w1_m_scanin[6]
// dff_rdata_w0_m_scanin[6]
// dff_wdata_m_scanin[87]
// dff_wdata_m_scanin[15]
// dff_rdata_w3_m_scanin[14]
// dff_rdata_w2_m_scanin[14]
// dff_rdata_w1_m_scanin[14]
// dff_rdata_w0_m_scanin[14]
// dff_wdata_m_scanin[79]
// dff_wdata_m_scanin[7]
// dff_rdata_w3_m_scanin[7]
// dff_rdata_w2_m_scanin[7]
// dff_rdata_w1_m_scanin[7]
// dff_rdata_w0_m_scanin[7]
// dff_wdata_m_scanin[88]
// dff_wdata_m_scanin[16]
// dff_rdata_w3_m_scanin[15]
// dff_rdata_w2_m_scanin[15]
// dff_rdata_w1_m_scanin[15]
// dff_rdata_w0_m_scanin[15]
// dff_wdata_m_scanin[98]
// dff_wdata_m_scanin[26]
// dff_rparity_w3_m_scanin[2]
// dff_rparity_w2_m_scanin[2]
// dff_rparity_w1_m_scanin[2]
// dff_rparity_w0_m_scanin[2]
// dff_wdata_m_scanin[107]
// dff_wdata_m_scanin[35]
// dff_rparity_w3_m_scanin[3]
// dff_rparity_w2_m_scanin[3]
// dff_rparity_w1_m_scanin[3]
// dff_rparity_w0_m_scanin[3]
// dff_wdata_m_scanin[90]
// dff_wdata_m_scanin[18]
// dff_rdata_w3_m_scanin[16]
// dff_rdata_w2_m_scanin[16]
// dff_rdata_w1_m_scanin[16]
// dff_rdata_w0_m_scanin[16]
// dff_wdata_m_scanin[99]
// dff_wdata_m_scanin[27]
// dff_rdata_w3_m_scanin[24]
// dff_rdata_w2_m_scanin[24]
// dff_rdata_w1_m_scanin[24]
// dff_rdata_w0_m_scanin[24]
// dff_wdata_m_scanin[91]
// dff_wdata_m_scanin[19]
// dff_rdata_w3_m_scanin[17]
// dff_rdata_w2_m_scanin[17]
// dff_rdata_w1_m_scanin[17]
// dff_rdata_w0_m_scanin[17]
// dff_wdata_m_scanin[100]
// dff_wdata_m_scanin[28]
// dff_rdata_w3_m_scanin[25]
// dff_rdata_w2_m_scanin[25]
// dff_rdata_w1_m_scanin[25]
// dff_rdata_w0_m_scanin[25]
// dff_wdata_m_scanin[92]
// dff_wdata_m_scanin[20]
// dff_rdata_w3_m_scanin[18]
// dff_rdata_w2_m_scanin[18]
// dff_rdata_w1_m_scanin[18]
// dff_rdata_w0_m_scanin[18]
// dff_wdata_m_scanin[101]
// dff_wdata_m_scanin[29]
// dff_rdata_w3_m_scanin[26]
// dff_rdata_w2_m_scanin[26]
// dff_rdata_w1_m_scanin[26]
// dff_rdata_w0_m_scanin[26]
// dff_wdata_m_scanin[93]
// dff_wdata_m_scanin[21]
// dff_rdata_w3_m_scanin[19]
// dff_rdata_w2_m_scanin[19]
// dff_rdata_w1_m_scanin[19]
// dff_rdata_w0_m_scanin[19]
// dff_wdata_m_scanin[102]
// dff_wdata_m_scanin[30]
// dff_rdata_w3_m_scanin[27]
// dff_rdata_w2_m_scanin[27]
// dff_rdata_w1_m_scanin[27]
// dff_rdata_w0_m_scanin[27]
// dff_wdata_m_scanin[94]
// dff_wdata_m_scanin[22]
// dff_rdata_w3_m_scanin[20]
// dff_rdata_w2_m_scanin[20]
// dff_rdata_w1_m_scanin[20]
// dff_rdata_w0_m_scanin[20]
// dff_wdata_m_scanin[103]
// dff_wdata_m_scanin[31]
// dff_rdata_w3_m_scanin[28]
// dff_rdata_w2_m_scanin[28]
// dff_rdata_w1_m_scanin[28]
// dff_rdata_w0_m_scanin[28]
// dff_wdata_m_scanin[95]
// dff_wdata_m_scanin[23]
// dff_rdata_w3_m_scanin[21]
// dff_rdata_w2_m_scanin[21]
// dff_rdata_w1_m_scanin[21]
// dff_rdata_w0_m_scanin[21]
// dff_wdata_m_scanin[104]
// dff_wdata_m_scanin[32]
// dff_rdata_w3_m_scanin[29]
// dff_rdata_w2_m_scanin[29]
// dff_rdata_w1_m_scanin[29]
// dff_rdata_w0_m_scanin[29]
// dff_wdata_m_scanin[96]
// dff_wdata_m_scanin[24]
// dff_rdata_w3_m_scanin[22]
// dff_rdata_w2_m_scanin[22]
// dff_rdata_w1_m_scanin[22]
// dff_rdata_w0_m_scanin[22]
// dff_wdata_m_scanin[105]
// dff_wdata_m_scanin[33]
// dff_rdata_w3_m_scanin[30]
// dff_rdata_w2_m_scanin[30]
// dff_rdata_w1_m_scanin[30]
// dff_rdata_w0_m_scanin[30]
// dff_wdata_m_scanin[97]
// dff_wdata_m_scanin[25]
// dff_rdata_w3_m_scanin[23]
// dff_rdata_w2_m_scanin[23]
// dff_rdata_w1_m_scanin[23]
// dff_rdata_w0_m_scanin[23]
// dff_wdata_m_scanin[106]
// dff_wdata_m_scanin[34]
// dff_rdata_w3_m_scanin[31]
// dff_rdata_w2_m_scanin[31]
// dff_rdata_w1_m_scanin[31]
// dff_rdata_w0_m_scanin[31]
// dff_ctl_m_1_scanin[8]
// dff_ctl_m_1_scanin[0]
// dff_ctl_m_1_scanin[9]
// dff_ctl_m_1_scanin[1]
// dff_ctl_m_1_scanin[10]
// dff_ctl_m_1_scanin[2]
// dff_ctl_m_1_scanin[11]
// dff_ctl_m_1_scanin[3]
// dff_byte_perr_w2_scanin[0]
// dff_byte_perr_w3_scanin[0]
// dff_byte_perr_w3_scanin[1]
// dff_byte_perr_w2_scanin[1]
// dff_byte_perr_w2_scanin[2]
// dff_byte_perr_w3_scanin[2]
// dff_byte_perr_w3_scanin[3]
// dff_byte_perr_w2_scanin[3]
// dff_msb_w3_scanin[7]
// dff_msb_w2_scanin[7]
// dff_msb_w1_scanin[7]
// dff_msb_w0_scanin[7]
// dff_msb_w3_scanin[6]
// dff_msb_w2_scanin[6]
// dff_msb_w1_scanin[6]
// dff_msb_w0_scanin[6]
// dff_msb_w3_scanin[5]
// dff_msb_w2_scanin[5]
// dff_msb_w1_scanin[5]
// dff_msb_w0_scanin[5]
// dff_msb_w3_scanin[4]
// dff_msb_w2_scanin[4]
// dff_msb_w1_scanin[4]
// dff_msb_w0_scanin[4]
// dff_msb_w3_scanin[0]
// dff_msb_w2_scanin[0]
// dff_msb_w1_scanin[0]
// dff_msb_w0_scanin[0]
// dff_msb_w3_scanin[1]
// dff_msb_w2_scanin[1]
// dff_msb_w1_scanin[1]
// dff_msb_w0_scanin[1]
// dff_msb_w3_scanin[2]
// dff_msb_w2_scanin[2]
// dff_msb_w1_scanin[2]
// dff_msb_w0_scanin[2]
// dff_msb_w3_scanin[3]
// dff_msb_w2_scanin[3]
// dff_msb_w1_scanin[3]
// dff_msb_w0_scanin[3]
// dff_red_out_scanin[2]
// dff_red_out_scanin[3]
// dff_red_out_scanin[4]
// dff_red_out_scanin[5]
// dff_red_out_scanin[6]
// dff_red_out_scanin[7]
// dff_red_out_scanin[0]
// dff_red_out_scanin[1]
// dff_red_in_scanin[2]
// dff_red_in_scanin[3]
// dff_red_in_scanin[1]
// dff_red_in_scanin[0]
// dff_red_in_scanin[6]
// dff_red_in_scanin[7]
// dff_red_in_scanin[8]
// dff_red_in_scanin[9]
// dff_red_in_scanin[10]
// dff_red_in_scanin[11]
// dff_red_in_scanin[4]
// dff_red_in_scanin[5]
// scanorder end
// fixscan start
assign dff_byte_perr_w0_scanin[7]=scan_in;
assign dff_byte_perr_w1_scanin[7]=dff_byte_perr_w0_scanout[7];
assign dff_byte_perr_w1_scanin[6]=dff_byte_perr_w1_scanout[7];
assign dff_byte_perr_w0_scanin[6]=dff_byte_perr_w1_scanout[6];
assign dff_byte_perr_w0_scanin[5]=dff_byte_perr_w0_scanout[6];
assign dff_byte_perr_w1_scanin[5]=dff_byte_perr_w0_scanout[5];
assign dff_byte_perr_w1_scanin[4]=dff_byte_perr_w1_scanout[5];
assign dff_byte_perr_w0_scanin[4]=dff_byte_perr_w1_scanout[4];
assign dff_wdata_m_scanin[143]=dff_byte_perr_w0_scanout[4];
assign dff_wdata_m_scanin[71]=dff_wdata_m_scanout[143];
assign dff_rparity_w3_m_scanin[7]=dff_wdata_m_scanout[71];
assign dff_rparity_w2_m_scanin[7]=dff_rparity_w3_m_scanout[7];
assign dff_rparity_w1_m_scanin[7]=dff_rparity_w2_m_scanout[7];
assign dff_rparity_w0_m_scanin[7]=dff_rparity_w1_m_scanout[7];
assign dff_wdata_m_scanin[134]=dff_rparity_w0_m_scanout[7];
assign dff_wdata_m_scanin[62]=dff_wdata_m_scanout[134];
assign dff_rparity_w3_m_scanin[6]=dff_wdata_m_scanout[62];
assign dff_rparity_w2_m_scanin[6]=dff_rparity_w3_m_scanout[6];
assign dff_rparity_w1_m_scanin[6]=dff_rparity_w2_m_scanout[6];
assign dff_rparity_w0_m_scanin[6]=dff_rparity_w1_m_scanout[6];
assign dff_wdata_m_scanin[142]=dff_rparity_w0_m_scanout[6];
assign dff_wdata_m_scanin[70]=dff_wdata_m_scanout[142];
assign dff_rdata_w3_m_scanin[63]=dff_wdata_m_scanout[70];
assign dff_rdata_w2_m_scanin[63]=dff_rdata_w3_m_scanout[63];
assign dff_rdata_w1_m_scanin[63]=dff_rdata_w2_m_scanout[63];
assign dff_rdata_w0_m_scanin[63]=dff_rdata_w1_m_scanout[63];
assign dff_wdata_m_scanin[133]=dff_rdata_w0_m_scanout[63];
assign dff_wdata_m_scanin[61]=dff_wdata_m_scanout[133];
assign dff_rdata_w3_m_scanin[55]=dff_wdata_m_scanout[61];
assign dff_rdata_w2_m_scanin[55]=dff_rdata_w3_m_scanout[55];
assign dff_rdata_w1_m_scanin[55]=dff_rdata_w2_m_scanout[55];
assign dff_rdata_w0_m_scanin[55]=dff_rdata_w1_m_scanout[55];
assign dff_wdata_m_scanin[141]=dff_rdata_w0_m_scanout[55];
assign dff_wdata_m_scanin[69]=dff_wdata_m_scanout[141];
assign dff_rdata_w3_m_scanin[62]=dff_wdata_m_scanout[69];
assign dff_rdata_w2_m_scanin[62]=dff_rdata_w3_m_scanout[62];
assign dff_rdata_w1_m_scanin[62]=dff_rdata_w2_m_scanout[62];
assign dff_rdata_w0_m_scanin[62]=dff_rdata_w1_m_scanout[62];
assign dff_wdata_m_scanin[132]=dff_rdata_w0_m_scanout[62];
assign dff_wdata_m_scanin[60]=dff_wdata_m_scanout[132];
assign dff_rdata_w3_m_scanin[54]=dff_wdata_m_scanout[60];
assign dff_rdata_w2_m_scanin[54]=dff_rdata_w3_m_scanout[54];
assign dff_rdata_w1_m_scanin[54]=dff_rdata_w2_m_scanout[54];
assign dff_rdata_w0_m_scanin[54]=dff_rdata_w1_m_scanout[54];
assign dff_wdata_m_scanin[140]=dff_rdata_w0_m_scanout[54];
assign dff_wdata_m_scanin[68]=dff_wdata_m_scanout[140];
assign dff_rdata_w3_m_scanin[61]=dff_wdata_m_scanout[68];
assign dff_rdata_w2_m_scanin[61]=dff_rdata_w3_m_scanout[61];
assign dff_rdata_w1_m_scanin[61]=dff_rdata_w2_m_scanout[61];
assign dff_rdata_w0_m_scanin[61]=dff_rdata_w1_m_scanout[61];
assign dff_wdata_m_scanin[131]=dff_rdata_w0_m_scanout[61];
assign dff_wdata_m_scanin[59]=dff_wdata_m_scanout[131];
assign dff_rdata_w3_m_scanin[53]=dff_wdata_m_scanout[59];
assign dff_rdata_w2_m_scanin[53]=dff_rdata_w3_m_scanout[53];
assign dff_rdata_w1_m_scanin[53]=dff_rdata_w2_m_scanout[53];
assign dff_rdata_w0_m_scanin[53]=dff_rdata_w1_m_scanout[53];
assign dff_wdata_m_scanin[139]=dff_rdata_w0_m_scanout[53];
assign dff_wdata_m_scanin[67]=dff_wdata_m_scanout[139];
assign dff_rdata_w3_m_scanin[60]=dff_wdata_m_scanout[67];
assign dff_rdata_w2_m_scanin[60]=dff_rdata_w3_m_scanout[60];
assign dff_rdata_w1_m_scanin[60]=dff_rdata_w2_m_scanout[60];
assign dff_rdata_w0_m_scanin[60]=dff_rdata_w1_m_scanout[60];
assign dff_wdata_m_scanin[130]=dff_rdata_w0_m_scanout[60];
assign dff_wdata_m_scanin[58]=dff_wdata_m_scanout[130];
assign dff_rdata_w3_m_scanin[52]=dff_wdata_m_scanout[58];
assign dff_rdata_w2_m_scanin[52]=dff_rdata_w3_m_scanout[52];
assign dff_rdata_w1_m_scanin[52]=dff_rdata_w2_m_scanout[52];
assign dff_rdata_w0_m_scanin[52]=dff_rdata_w1_m_scanout[52];
assign dff_wdata_m_scanin[138]=dff_rdata_w0_m_scanout[52];
assign dff_wdata_m_scanin[66]=dff_wdata_m_scanout[138];
assign dff_rdata_w3_m_scanin[59]=dff_wdata_m_scanout[66];
assign dff_rdata_w2_m_scanin[59]=dff_rdata_w3_m_scanout[59];
assign dff_rdata_w1_m_scanin[59]=dff_rdata_w2_m_scanout[59];
assign dff_rdata_w0_m_scanin[59]=dff_rdata_w1_m_scanout[59];
assign dff_wdata_m_scanin[129]=dff_rdata_w0_m_scanout[59];
assign dff_wdata_m_scanin[57]=dff_wdata_m_scanout[129];
assign dff_rdata_w3_m_scanin[51]=dff_wdata_m_scanout[57];
assign dff_rdata_w2_m_scanin[51]=dff_rdata_w3_m_scanout[51];
assign dff_rdata_w1_m_scanin[51]=dff_rdata_w2_m_scanout[51];
assign dff_rdata_w0_m_scanin[51]=dff_rdata_w1_m_scanout[51];
assign dff_wdata_m_scanin[137]=dff_rdata_w0_m_scanout[51];
assign dff_wdata_m_scanin[65]=dff_wdata_m_scanout[137];
assign dff_rdata_w3_m_scanin[58]=dff_wdata_m_scanout[65];
assign dff_rdata_w2_m_scanin[58]=dff_rdata_w3_m_scanout[58];
assign dff_rdata_w1_m_scanin[58]=dff_rdata_w2_m_scanout[58];
assign dff_rdata_w0_m_scanin[58]=dff_rdata_w1_m_scanout[58];
assign dff_wdata_m_scanin[128]=dff_rdata_w0_m_scanout[58];
assign dff_wdata_m_scanin[56]=dff_wdata_m_scanout[128];
assign dff_rdata_w3_m_scanin[50]=dff_wdata_m_scanout[56];
assign dff_rdata_w2_m_scanin[50]=dff_rdata_w3_m_scanout[50];
assign dff_rdata_w1_m_scanin[50]=dff_rdata_w2_m_scanout[50];
assign dff_rdata_w0_m_scanin[50]=dff_rdata_w1_m_scanout[50];
assign dff_wdata_m_scanin[136]=dff_rdata_w0_m_scanout[50];
assign dff_wdata_m_scanin[64]=dff_wdata_m_scanout[136];
assign dff_rdata_w3_m_scanin[57]=dff_wdata_m_scanout[64];
assign dff_rdata_w2_m_scanin[57]=dff_rdata_w3_m_scanout[57];
assign dff_rdata_w1_m_scanin[57]=dff_rdata_w2_m_scanout[57];
assign dff_rdata_w0_m_scanin[57]=dff_rdata_w1_m_scanout[57];
assign dff_wdata_m_scanin[127]=dff_rdata_w0_m_scanout[57];
assign dff_wdata_m_scanin[55]=dff_wdata_m_scanout[127];
assign dff_rdata_w3_m_scanin[49]=dff_wdata_m_scanout[55];
assign dff_rdata_w2_m_scanin[49]=dff_rdata_w3_m_scanout[49];
assign dff_rdata_w1_m_scanin[49]=dff_rdata_w2_m_scanout[49];
assign dff_rdata_w0_m_scanin[49]=dff_rdata_w1_m_scanout[49];
assign dff_wdata_m_scanin[135]=dff_rdata_w0_m_scanout[49];
assign dff_wdata_m_scanin[63]=dff_wdata_m_scanout[135];
assign dff_rdata_w3_m_scanin[56]=dff_wdata_m_scanout[63];
assign dff_rdata_w2_m_scanin[56]=dff_rdata_w3_m_scanout[56];
assign dff_rdata_w1_m_scanin[56]=dff_rdata_w2_m_scanout[56];
assign dff_rdata_w0_m_scanin[56]=dff_rdata_w1_m_scanout[56];
assign dff_wdata_m_scanin[126]=dff_rdata_w0_m_scanout[56];
assign dff_wdata_m_scanin[54]=dff_wdata_m_scanout[126];
assign dff_rdata_w3_m_scanin[48]=dff_wdata_m_scanout[54];
assign dff_rdata_w2_m_scanin[48]=dff_rdata_w3_m_scanout[48];
assign dff_rdata_w1_m_scanin[48]=dff_rdata_w2_m_scanout[48];
assign dff_rdata_w0_m_scanin[48]=dff_rdata_w1_m_scanout[48];
assign dff_wdata_m_scanin[125]=dff_rdata_w0_m_scanout[48];
assign dff_wdata_m_scanin[53]=dff_wdata_m_scanout[125];
assign dff_rparity_w3_m_scanin[5]=dff_wdata_m_scanout[53];
assign dff_rparity_w2_m_scanin[5]=dff_rparity_w3_m_scanout[5];
assign dff_rparity_w1_m_scanin[5]=dff_rparity_w2_m_scanout[5];
assign dff_rparity_w0_m_scanin[5]=dff_rparity_w1_m_scanout[5];
assign dff_wdata_m_scanin[116]=dff_rparity_w0_m_scanout[5];
assign dff_wdata_m_scanin[44]=dff_wdata_m_scanout[116];
assign dff_rparity_w3_m_scanin[4]=dff_wdata_m_scanout[44];
assign dff_rparity_w2_m_scanin[4]=dff_rparity_w3_m_scanout[4];
assign dff_rparity_w1_m_scanin[4]=dff_rparity_w2_m_scanout[4];
assign dff_rparity_w0_m_scanin[4]=dff_rparity_w1_m_scanout[4];
assign dff_wdata_m_scanin[124]=dff_rparity_w0_m_scanout[4];
assign dff_wdata_m_scanin[52]=dff_wdata_m_scanout[124];
assign dff_rdata_w3_m_scanin[47]=dff_wdata_m_scanout[52];
assign dff_rdata_w2_m_scanin[47]=dff_rdata_w3_m_scanout[47];
assign dff_rdata_w1_m_scanin[47]=dff_rdata_w2_m_scanout[47];
assign dff_rdata_w0_m_scanin[47]=dff_rdata_w1_m_scanout[47];
assign dff_wdata_m_scanin[115]=dff_rdata_w0_m_scanout[47];
assign dff_wdata_m_scanin[43]=dff_wdata_m_scanout[115];
assign dff_rdata_w3_m_scanin[39]=dff_wdata_m_scanout[43];
assign dff_rdata_w2_m_scanin[39]=dff_rdata_w3_m_scanout[39];
assign dff_rdata_w1_m_scanin[39]=dff_rdata_w2_m_scanout[39];
assign dff_rdata_w0_m_scanin[39]=dff_rdata_w1_m_scanout[39];
assign dff_wdata_m_scanin[123]=dff_rdata_w0_m_scanout[39];
assign dff_wdata_m_scanin[51]=dff_wdata_m_scanout[123];
assign dff_rdata_w3_m_scanin[46]=dff_wdata_m_scanout[51];
assign dff_rdata_w2_m_scanin[46]=dff_rdata_w3_m_scanout[46];
assign dff_rdata_w1_m_scanin[46]=dff_rdata_w2_m_scanout[46];
assign dff_rdata_w0_m_scanin[46]=dff_rdata_w1_m_scanout[46];
assign dff_wdata_m_scanin[114]=dff_rdata_w0_m_scanout[46];
assign dff_wdata_m_scanin[42]=dff_wdata_m_scanout[114];
assign dff_rdata_w3_m_scanin[38]=dff_wdata_m_scanout[42];
assign dff_rdata_w2_m_scanin[38]=dff_rdata_w3_m_scanout[38];
assign dff_rdata_w1_m_scanin[38]=dff_rdata_w2_m_scanout[38];
assign dff_rdata_w0_m_scanin[38]=dff_rdata_w1_m_scanout[38];
assign dff_wdata_m_scanin[122]=dff_rdata_w0_m_scanout[38];
assign dff_wdata_m_scanin[50]=dff_wdata_m_scanout[122];
assign dff_rdata_w3_m_scanin[45]=dff_wdata_m_scanout[50];
assign dff_rdata_w2_m_scanin[45]=dff_rdata_w3_m_scanout[45];
assign dff_rdata_w1_m_scanin[45]=dff_rdata_w2_m_scanout[45];
assign dff_rdata_w0_m_scanin[45]=dff_rdata_w1_m_scanout[45];
assign dff_wdata_m_scanin[113]=dff_rdata_w0_m_scanout[45];
assign dff_wdata_m_scanin[41]=dff_wdata_m_scanout[113];
assign dff_rdata_w3_m_scanin[37]=dff_wdata_m_scanout[41];
assign dff_rdata_w2_m_scanin[37]=dff_rdata_w3_m_scanout[37];
assign dff_rdata_w1_m_scanin[37]=dff_rdata_w2_m_scanout[37];
assign dff_rdata_w0_m_scanin[37]=dff_rdata_w1_m_scanout[37];
assign dff_wdata_m_scanin[121]=dff_rdata_w0_m_scanout[37];
assign dff_wdata_m_scanin[49]=dff_wdata_m_scanout[121];
assign dff_rdata_w3_m_scanin[44]=dff_wdata_m_scanout[49];
assign dff_rdata_w2_m_scanin[44]=dff_rdata_w3_m_scanout[44];
assign dff_rdata_w1_m_scanin[44]=dff_rdata_w2_m_scanout[44];
assign dff_rdata_w0_m_scanin[44]=dff_rdata_w1_m_scanout[44];
assign dff_wdata_m_scanin[112]=dff_rdata_w0_m_scanout[44];
assign dff_wdata_m_scanin[40]=dff_wdata_m_scanout[112];
assign dff_rdata_w3_m_scanin[36]=dff_wdata_m_scanout[40];
assign dff_rdata_w2_m_scanin[36]=dff_rdata_w3_m_scanout[36];
assign dff_rdata_w1_m_scanin[36]=dff_rdata_w2_m_scanout[36];
assign dff_rdata_w0_m_scanin[36]=dff_rdata_w1_m_scanout[36];
assign dff_wdata_m_scanin[120]=dff_rdata_w0_m_scanout[36];
assign dff_wdata_m_scanin[48]=dff_wdata_m_scanout[120];
assign dff_rdata_w3_m_scanin[43]=dff_wdata_m_scanout[48];
assign dff_rdata_w2_m_scanin[43]=dff_rdata_w3_m_scanout[43];
assign dff_rdata_w1_m_scanin[43]=dff_rdata_w2_m_scanout[43];
assign dff_rdata_w0_m_scanin[43]=dff_rdata_w1_m_scanout[43];
assign dff_wdata_m_scanin[111]=dff_rdata_w0_m_scanout[43];
assign dff_wdata_m_scanin[39]=dff_wdata_m_scanout[111];
assign dff_rdata_w3_m_scanin[35]=dff_wdata_m_scanout[39];
assign dff_rdata_w2_m_scanin[35]=dff_rdata_w3_m_scanout[35];
assign dff_rdata_w1_m_scanin[35]=dff_rdata_w2_m_scanout[35];
assign dff_rdata_w0_m_scanin[35]=dff_rdata_w1_m_scanout[35];
assign dff_wdata_m_scanin[119]=dff_rdata_w0_m_scanout[35];
assign dff_wdata_m_scanin[47]=dff_wdata_m_scanout[119];
assign dff_rdata_w3_m_scanin[42]=dff_wdata_m_scanout[47];
assign dff_rdata_w2_m_scanin[42]=dff_rdata_w3_m_scanout[42];
assign dff_rdata_w1_m_scanin[42]=dff_rdata_w2_m_scanout[42];
assign dff_rdata_w0_m_scanin[42]=dff_rdata_w1_m_scanout[42];
assign dff_wdata_m_scanin[110]=dff_rdata_w0_m_scanout[42];
assign dff_wdata_m_scanin[38]=dff_wdata_m_scanout[110];
assign dff_rdata_w3_m_scanin[34]=dff_wdata_m_scanout[38];
assign dff_rdata_w2_m_scanin[34]=dff_rdata_w3_m_scanout[34];
assign dff_rdata_w1_m_scanin[34]=dff_rdata_w2_m_scanout[34];
assign dff_rdata_w0_m_scanin[34]=dff_rdata_w1_m_scanout[34];
assign dff_wdata_m_scanin[118]=dff_rdata_w0_m_scanout[34];
assign dff_wdata_m_scanin[46]=dff_wdata_m_scanout[118];
assign dff_rdata_w3_m_scanin[41]=dff_wdata_m_scanout[46];
assign dff_rdata_w2_m_scanin[41]=dff_rdata_w3_m_scanout[41];
assign dff_rdata_w1_m_scanin[41]=dff_rdata_w2_m_scanout[41];
assign dff_rdata_w0_m_scanin[41]=dff_rdata_w1_m_scanout[41];
assign dff_wdata_m_scanin[109]=dff_rdata_w0_m_scanout[41];
assign dff_wdata_m_scanin[37]=dff_wdata_m_scanout[109];
assign dff_rdata_w3_m_scanin[33]=dff_wdata_m_scanout[37];
assign dff_rdata_w2_m_scanin[33]=dff_rdata_w3_m_scanout[33];
assign dff_rdata_w1_m_scanin[33]=dff_rdata_w2_m_scanout[33];
assign dff_rdata_w0_m_scanin[33]=dff_rdata_w1_m_scanout[33];
assign dff_wdata_m_scanin[117]=dff_rdata_w0_m_scanout[33];
assign dff_wdata_m_scanin[45]=dff_wdata_m_scanout[117];
assign dff_rdata_w3_m_scanin[40]=dff_wdata_m_scanout[45];
assign dff_rdata_w2_m_scanin[40]=dff_rdata_w3_m_scanout[40];
assign dff_rdata_w1_m_scanin[40]=dff_rdata_w2_m_scanout[40];
assign dff_rdata_w0_m_scanin[40]=dff_rdata_w1_m_scanout[40];
assign dff_wdata_m_scanin[108]=dff_rdata_w0_m_scanout[40];
assign dff_wdata_m_scanin[36]=dff_wdata_m_scanout[108];
assign dff_rdata_w3_m_scanin[32]=dff_wdata_m_scanout[36];
assign dff_rdata_w2_m_scanin[32]=dff_rdata_w3_m_scanout[32];
assign dff_rdata_w1_m_scanin[32]=dff_rdata_w2_m_scanout[32];
assign dff_rdata_w0_m_scanin[32]=dff_rdata_w1_m_scanout[32];
assign dff_ctl_m_1_scanin[15]=dff_rdata_w0_m_scanout[32];
assign dff_ctl_m_1_scanin[7]=dff_ctl_m_1_scanout[15];
assign dff_ctl_m_1_scanin[14]=dff_ctl_m_1_scanout[7];
assign dff_ctl_m_1_scanin[6]=dff_ctl_m_1_scanout[14];
assign dff_ctl_m_1_scanin[13]=dff_ctl_m_1_scanout[6];
assign dff_ctl_m_1_scanin[5]=dff_ctl_m_1_scanout[13];
assign dff_ctl_m_1_scanin[12]=dff_ctl_m_1_scanout[5];
assign dff_ctl_m_1_scanin[4]=dff_ctl_m_1_scanout[12];
assign dff_byte_perr_w2_scanin[7]=dff_ctl_m_1_scanout[4];
assign dff_byte_perr_w3_scanin[7]=dff_byte_perr_w2_scanout[7];
assign dff_byte_perr_w3_scanin[6]=dff_byte_perr_w3_scanout[7];
assign dff_byte_perr_w2_scanin[6]=dff_byte_perr_w3_scanout[6];
assign dff_byte_perr_w2_scanin[5]=dff_byte_perr_w2_scanout[6];
assign dff_byte_perr_w3_scanin[5]=dff_byte_perr_w2_scanout[5];
assign dff_byte_perr_w3_scanin[4]=dff_byte_perr_w3_scanout[5];
assign dff_byte_perr_w2_scanin[4]=dff_byte_perr_w3_scanout[4];
assign dff_ctl_m_0_scanin[0]=dff_byte_perr_w2_scanout[4];
assign dff_ctl_b_scanin[4]=dff_ctl_m_0_scanout[0];
assign dff_ctl_b_scanin[0]=dff_ctl_b_scanout[4];
assign dff_ctl_b_scanin[1]=dff_ctl_b_scanout[0];
assign dff_ctl_b_scanin[2]=dff_ctl_b_scanout[1];
assign dff_ctl_b_scanin[3]=dff_ctl_b_scanout[2];
assign lat_ctl_eb_scanin[6]=dff_ctl_b_scanout[3];
assign lat_ctl_eb_scanin[1]=lat_ctl_eb_scanout[6];
assign lat_ctl_eb_scanin[0]=lat_ctl_eb_scanout[1];
assign lat_ctl_eb_scanin[2]=lat_ctl_eb_scanout[0];
assign lat_ctl_eb_scanin[3]=lat_ctl_eb_scanout[2];
assign lat_addr_scanin[1]=lat_ctl_eb_scanout[3];
assign lat_addr_scanin[0]=lat_addr_scanout[1];
assign lat_addr_scanin[7]=lat_addr_scanout[0];
assign lat_addr_scanin[6]=lat_addr_scanout[7];
assign lat_addr_scanin[5]=lat_addr_scanout[6];
assign lat_addr_scanin[4]=lat_addr_scanout[5];
assign lat_addr_scanin[3]=lat_addr_scanout[4];
assign lat_addr_scanin[2]=lat_addr_scanout[3];
assign lat_ctl_eb_scanin[4]=lat_addr_scanout[2];
assign dff_ctl_m_0_scanin[1]=lat_ctl_eb_scanout[4];
assign dff_ctl_m_0_scanin[2]=dff_ctl_m_0_scanout[1];
assign lat_ctl_eb_scanin[5]=dff_ctl_m_0_scanout[2];
assign dff_byte_perr_w0_scanin[0]=lat_ctl_eb_scanout[5];
assign dff_byte_perr_w1_scanin[0]=dff_byte_perr_w0_scanout[0];
assign dff_byte_perr_w1_scanin[1]=dff_byte_perr_w1_scanout[0];
assign dff_byte_perr_w0_scanin[1]=dff_byte_perr_w1_scanout[1];
assign dff_byte_perr_w0_scanin[2]=dff_byte_perr_w0_scanout[1];
assign dff_byte_perr_w1_scanin[2]=dff_byte_perr_w0_scanout[2];
assign dff_byte_perr_w1_scanin[3]=dff_byte_perr_w1_scanout[2];
assign dff_byte_perr_w0_scanin[3]=dff_byte_perr_w1_scanout[3];
assign dff_wdata_m_scanin[80]=dff_byte_perr_w0_scanout[3];
assign dff_wdata_m_scanin[8]=dff_wdata_m_scanout[80];
assign dff_rparity_w3_m_scanin[0]=dff_wdata_m_scanout[8];
assign dff_rparity_w2_m_scanin[0]=dff_rparity_w3_m_scanout[0];
assign dff_rparity_w1_m_scanin[0]=dff_rparity_w2_m_scanout[0];
assign dff_rparity_w0_m_scanin[0]=dff_rparity_w1_m_scanout[0];
assign dff_wdata_m_scanin[89]=dff_rparity_w0_m_scanout[0];
assign dff_wdata_m_scanin[17]=dff_wdata_m_scanout[89];
assign dff_rparity_w3_m_scanin[1]=dff_wdata_m_scanout[17];
assign dff_rparity_w2_m_scanin[1]=dff_rparity_w3_m_scanout[1];
assign dff_rparity_w1_m_scanin[1]=dff_rparity_w2_m_scanout[1];
assign dff_rparity_w0_m_scanin[1]=dff_rparity_w1_m_scanout[1];
assign dff_wdata_m_scanin[72]=dff_rparity_w0_m_scanout[1];
assign dff_wdata_m_scanin[0]=dff_wdata_m_scanout[72];
assign dff_rdata_w3_m_scanin[0]=dff_wdata_m_scanout[0];
assign dff_rdata_w2_m_scanin[0]=dff_rdata_w3_m_scanout[0];
assign dff_rdata_w1_m_scanin[0]=dff_rdata_w2_m_scanout[0];
assign dff_rdata_w0_m_scanin[0]=dff_rdata_w1_m_scanout[0];
assign dff_wdata_m_scanin[81]=dff_rdata_w0_m_scanout[0];
assign dff_wdata_m_scanin[9]=dff_wdata_m_scanout[81];
assign dff_rdata_w3_m_scanin[8]=dff_wdata_m_scanout[9];
assign dff_rdata_w2_m_scanin[8]=dff_rdata_w3_m_scanout[8];
assign dff_rdata_w1_m_scanin[8]=dff_rdata_w2_m_scanout[8];
assign dff_rdata_w0_m_scanin[8]=dff_rdata_w1_m_scanout[8];
assign dff_wdata_m_scanin[73]=dff_rdata_w0_m_scanout[8];
assign dff_wdata_m_scanin[1]=dff_wdata_m_scanout[73];
assign dff_rdata_w3_m_scanin[1]=dff_wdata_m_scanout[1];
assign dff_rdata_w2_m_scanin[1]=dff_rdata_w3_m_scanout[1];
assign dff_rdata_w1_m_scanin[1]=dff_rdata_w2_m_scanout[1];
assign dff_rdata_w0_m_scanin[1]=dff_rdata_w1_m_scanout[1];
assign dff_wdata_m_scanin[82]=dff_rdata_w0_m_scanout[1];
assign dff_wdata_m_scanin[10]=dff_wdata_m_scanout[82];
assign dff_rdata_w3_m_scanin[9]=dff_wdata_m_scanout[10];
assign dff_rdata_w2_m_scanin[9]=dff_rdata_w3_m_scanout[9];
assign dff_rdata_w1_m_scanin[9]=dff_rdata_w2_m_scanout[9];
assign dff_rdata_w0_m_scanin[9]=dff_rdata_w1_m_scanout[9];
assign dff_wdata_m_scanin[74]=dff_rdata_w0_m_scanout[9];
assign dff_wdata_m_scanin[2]=dff_wdata_m_scanout[74];
assign dff_rdata_w3_m_scanin[2]=dff_wdata_m_scanout[2];
assign dff_rdata_w2_m_scanin[2]=dff_rdata_w3_m_scanout[2];
assign dff_rdata_w1_m_scanin[2]=dff_rdata_w2_m_scanout[2];
assign dff_rdata_w0_m_scanin[2]=dff_rdata_w1_m_scanout[2];
assign dff_wdata_m_scanin[83]=dff_rdata_w0_m_scanout[2];
assign dff_wdata_m_scanin[11]=dff_wdata_m_scanout[83];
assign dff_rdata_w3_m_scanin[10]=dff_wdata_m_scanout[11];
assign dff_rdata_w2_m_scanin[10]=dff_rdata_w3_m_scanout[10];
assign dff_rdata_w1_m_scanin[10]=dff_rdata_w2_m_scanout[10];
assign dff_rdata_w0_m_scanin[10]=dff_rdata_w1_m_scanout[10];
assign dff_wdata_m_scanin[75]=dff_rdata_w0_m_scanout[10];
assign dff_wdata_m_scanin[3]=dff_wdata_m_scanout[75];
assign dff_rdata_w3_m_scanin[3]=dff_wdata_m_scanout[3];
assign dff_rdata_w2_m_scanin[3]=dff_rdata_w3_m_scanout[3];
assign dff_rdata_w1_m_scanin[3]=dff_rdata_w2_m_scanout[3];
assign dff_rdata_w0_m_scanin[3]=dff_rdata_w1_m_scanout[3];
assign dff_wdata_m_scanin[84]=dff_rdata_w0_m_scanout[3];
assign dff_wdata_m_scanin[12]=dff_wdata_m_scanout[84];
assign dff_rdata_w3_m_scanin[11]=dff_wdata_m_scanout[12];
assign dff_rdata_w2_m_scanin[11]=dff_rdata_w3_m_scanout[11];
assign dff_rdata_w1_m_scanin[11]=dff_rdata_w2_m_scanout[11];
assign dff_rdata_w0_m_scanin[11]=dff_rdata_w1_m_scanout[11];
assign dff_wdata_m_scanin[76]=dff_rdata_w0_m_scanout[11];
assign dff_wdata_m_scanin[4]=dff_wdata_m_scanout[76];
assign dff_rdata_w3_m_scanin[4]=dff_wdata_m_scanout[4];
assign dff_rdata_w2_m_scanin[4]=dff_rdata_w3_m_scanout[4];
assign dff_rdata_w1_m_scanin[4]=dff_rdata_w2_m_scanout[4];
assign dff_rdata_w0_m_scanin[4]=dff_rdata_w1_m_scanout[4];
assign dff_wdata_m_scanin[85]=dff_rdata_w0_m_scanout[4];
assign dff_wdata_m_scanin[13]=dff_wdata_m_scanout[85];
assign dff_rdata_w3_m_scanin[12]=dff_wdata_m_scanout[13];
assign dff_rdata_w2_m_scanin[12]=dff_rdata_w3_m_scanout[12];
assign dff_rdata_w1_m_scanin[12]=dff_rdata_w2_m_scanout[12];
assign dff_rdata_w0_m_scanin[12]=dff_rdata_w1_m_scanout[12];
assign dff_wdata_m_scanin[77]=dff_rdata_w0_m_scanout[12];
assign dff_wdata_m_scanin[5]=dff_wdata_m_scanout[77];
assign dff_rdata_w3_m_scanin[5]=dff_wdata_m_scanout[5];
assign dff_rdata_w2_m_scanin[5]=dff_rdata_w3_m_scanout[5];
assign dff_rdata_w1_m_scanin[5]=dff_rdata_w2_m_scanout[5];
assign dff_rdata_w0_m_scanin[5]=dff_rdata_w1_m_scanout[5];
assign dff_wdata_m_scanin[86]=dff_rdata_w0_m_scanout[5];
assign dff_wdata_m_scanin[14]=dff_wdata_m_scanout[86];
assign dff_rdata_w3_m_scanin[13]=dff_wdata_m_scanout[14];
assign dff_rdata_w2_m_scanin[13]=dff_rdata_w3_m_scanout[13];
assign dff_rdata_w1_m_scanin[13]=dff_rdata_w2_m_scanout[13];
assign dff_rdata_w0_m_scanin[13]=dff_rdata_w1_m_scanout[13];
assign dff_wdata_m_scanin[78]=dff_rdata_w0_m_scanout[13];
assign dff_wdata_m_scanin[6]=dff_wdata_m_scanout[78];
assign dff_rdata_w3_m_scanin[6]=dff_wdata_m_scanout[6];
assign dff_rdata_w2_m_scanin[6]=dff_rdata_w3_m_scanout[6];
assign dff_rdata_w1_m_scanin[6]=dff_rdata_w2_m_scanout[6];
assign dff_rdata_w0_m_scanin[6]=dff_rdata_w1_m_scanout[6];
assign dff_wdata_m_scanin[87]=dff_rdata_w0_m_scanout[6];
assign dff_wdata_m_scanin[15]=dff_wdata_m_scanout[87];
assign dff_rdata_w3_m_scanin[14]=dff_wdata_m_scanout[15];
assign dff_rdata_w2_m_scanin[14]=dff_rdata_w3_m_scanout[14];
assign dff_rdata_w1_m_scanin[14]=dff_rdata_w2_m_scanout[14];
assign dff_rdata_w0_m_scanin[14]=dff_rdata_w1_m_scanout[14];
assign dff_wdata_m_scanin[79]=dff_rdata_w0_m_scanout[14];
assign dff_wdata_m_scanin[7]=dff_wdata_m_scanout[79];
assign dff_rdata_w3_m_scanin[7]=dff_wdata_m_scanout[7];
assign dff_rdata_w2_m_scanin[7]=dff_rdata_w3_m_scanout[7];
assign dff_rdata_w1_m_scanin[7]=dff_rdata_w2_m_scanout[7];
assign dff_rdata_w0_m_scanin[7]=dff_rdata_w1_m_scanout[7];
assign dff_wdata_m_scanin[88]=dff_rdata_w0_m_scanout[7];
assign dff_wdata_m_scanin[16]=dff_wdata_m_scanout[88];
assign dff_rdata_w3_m_scanin[15]=dff_wdata_m_scanout[16];
assign dff_rdata_w2_m_scanin[15]=dff_rdata_w3_m_scanout[15];
assign dff_rdata_w1_m_scanin[15]=dff_rdata_w2_m_scanout[15];
assign dff_rdata_w0_m_scanin[15]=dff_rdata_w1_m_scanout[15];
assign dff_wdata_m_scanin[98]=dff_rdata_w0_m_scanout[15];
assign dff_wdata_m_scanin[26]=dff_wdata_m_scanout[98];
assign dff_rparity_w3_m_scanin[2]=dff_wdata_m_scanout[26];
assign dff_rparity_w2_m_scanin[2]=dff_rparity_w3_m_scanout[2];
assign dff_rparity_w1_m_scanin[2]=dff_rparity_w2_m_scanout[2];
assign dff_rparity_w0_m_scanin[2]=dff_rparity_w1_m_scanout[2];
assign dff_wdata_m_scanin[107]=dff_rparity_w0_m_scanout[2];
assign dff_wdata_m_scanin[35]=dff_wdata_m_scanout[107];
assign dff_rparity_w3_m_scanin[3]=dff_wdata_m_scanout[35];
assign dff_rparity_w2_m_scanin[3]=dff_rparity_w3_m_scanout[3];
assign dff_rparity_w1_m_scanin[3]=dff_rparity_w2_m_scanout[3];
assign dff_rparity_w0_m_scanin[3]=dff_rparity_w1_m_scanout[3];
assign dff_wdata_m_scanin[90]=dff_rparity_w0_m_scanout[3];
assign dff_wdata_m_scanin[18]=dff_wdata_m_scanout[90];
assign dff_rdata_w3_m_scanin[16]=dff_wdata_m_scanout[18];
assign dff_rdata_w2_m_scanin[16]=dff_rdata_w3_m_scanout[16];
assign dff_rdata_w1_m_scanin[16]=dff_rdata_w2_m_scanout[16];
assign dff_rdata_w0_m_scanin[16]=dff_rdata_w1_m_scanout[16];
assign dff_wdata_m_scanin[99]=dff_rdata_w0_m_scanout[16];
assign dff_wdata_m_scanin[27]=dff_wdata_m_scanout[99];
assign dff_rdata_w3_m_scanin[24]=dff_wdata_m_scanout[27];
assign dff_rdata_w2_m_scanin[24]=dff_rdata_w3_m_scanout[24];
assign dff_rdata_w1_m_scanin[24]=dff_rdata_w2_m_scanout[24];
assign dff_rdata_w0_m_scanin[24]=dff_rdata_w1_m_scanout[24];
assign dff_wdata_m_scanin[91]=dff_rdata_w0_m_scanout[24];
assign dff_wdata_m_scanin[19]=dff_wdata_m_scanout[91];
assign dff_rdata_w3_m_scanin[17]=dff_wdata_m_scanout[19];
assign dff_rdata_w2_m_scanin[17]=dff_rdata_w3_m_scanout[17];
assign dff_rdata_w1_m_scanin[17]=dff_rdata_w2_m_scanout[17];
assign dff_rdata_w0_m_scanin[17]=dff_rdata_w1_m_scanout[17];
assign dff_wdata_m_scanin[100]=dff_rdata_w0_m_scanout[17];
assign dff_wdata_m_scanin[28]=dff_wdata_m_scanout[100];
assign dff_rdata_w3_m_scanin[25]=dff_wdata_m_scanout[28];
assign dff_rdata_w2_m_scanin[25]=dff_rdata_w3_m_scanout[25];
assign dff_rdata_w1_m_scanin[25]=dff_rdata_w2_m_scanout[25];
assign dff_rdata_w0_m_scanin[25]=dff_rdata_w1_m_scanout[25];
assign dff_wdata_m_scanin[92]=dff_rdata_w0_m_scanout[25];
assign dff_wdata_m_scanin[20]=dff_wdata_m_scanout[92];
assign dff_rdata_w3_m_scanin[18]=dff_wdata_m_scanout[20];
assign dff_rdata_w2_m_scanin[18]=dff_rdata_w3_m_scanout[18];
assign dff_rdata_w1_m_scanin[18]=dff_rdata_w2_m_scanout[18];
assign dff_rdata_w0_m_scanin[18]=dff_rdata_w1_m_scanout[18];
assign dff_wdata_m_scanin[101]=dff_rdata_w0_m_scanout[18];
assign dff_wdata_m_scanin[29]=dff_wdata_m_scanout[101];
assign dff_rdata_w3_m_scanin[26]=dff_wdata_m_scanout[29];
assign dff_rdata_w2_m_scanin[26]=dff_rdata_w3_m_scanout[26];
assign dff_rdata_w1_m_scanin[26]=dff_rdata_w2_m_scanout[26];
assign dff_rdata_w0_m_scanin[26]=dff_rdata_w1_m_scanout[26];
assign dff_wdata_m_scanin[93]=dff_rdata_w0_m_scanout[26];
assign dff_wdata_m_scanin[21]=dff_wdata_m_scanout[93];
assign dff_rdata_w3_m_scanin[19]=dff_wdata_m_scanout[21];
assign dff_rdata_w2_m_scanin[19]=dff_rdata_w3_m_scanout[19];
assign dff_rdata_w1_m_scanin[19]=dff_rdata_w2_m_scanout[19];
assign dff_rdata_w0_m_scanin[19]=dff_rdata_w1_m_scanout[19];
assign dff_wdata_m_scanin[102]=dff_rdata_w0_m_scanout[19];
assign dff_wdata_m_scanin[30]=dff_wdata_m_scanout[102];
assign dff_rdata_w3_m_scanin[27]=dff_wdata_m_scanout[30];
assign dff_rdata_w2_m_scanin[27]=dff_rdata_w3_m_scanout[27];
assign dff_rdata_w1_m_scanin[27]=dff_rdata_w2_m_scanout[27];
assign dff_rdata_w0_m_scanin[27]=dff_rdata_w1_m_scanout[27];
assign dff_wdata_m_scanin[94]=dff_rdata_w0_m_scanout[27];
assign dff_wdata_m_scanin[22]=dff_wdata_m_scanout[94];
assign dff_rdata_w3_m_scanin[20]=dff_wdata_m_scanout[22];
assign dff_rdata_w2_m_scanin[20]=dff_rdata_w3_m_scanout[20];
assign dff_rdata_w1_m_scanin[20]=dff_rdata_w2_m_scanout[20];
assign dff_rdata_w0_m_scanin[20]=dff_rdata_w1_m_scanout[20];
assign dff_wdata_m_scanin[103]=dff_rdata_w0_m_scanout[20];
assign dff_wdata_m_scanin[31]=dff_wdata_m_scanout[103];
assign dff_rdata_w3_m_scanin[28]=dff_wdata_m_scanout[31];
assign dff_rdata_w2_m_scanin[28]=dff_rdata_w3_m_scanout[28];
assign dff_rdata_w1_m_scanin[28]=dff_rdata_w2_m_scanout[28];
assign dff_rdata_w0_m_scanin[28]=dff_rdata_w1_m_scanout[28];
assign dff_wdata_m_scanin[95]=dff_rdata_w0_m_scanout[28];
assign dff_wdata_m_scanin[23]=dff_wdata_m_scanout[95];
assign dff_rdata_w3_m_scanin[21]=dff_wdata_m_scanout[23];
assign dff_rdata_w2_m_scanin[21]=dff_rdata_w3_m_scanout[21];
assign dff_rdata_w1_m_scanin[21]=dff_rdata_w2_m_scanout[21];
assign dff_rdata_w0_m_scanin[21]=dff_rdata_w1_m_scanout[21];
assign dff_wdata_m_scanin[104]=dff_rdata_w0_m_scanout[21];
assign dff_wdata_m_scanin[32]=dff_wdata_m_scanout[104];
assign dff_rdata_w3_m_scanin[29]=dff_wdata_m_scanout[32];
assign dff_rdata_w2_m_scanin[29]=dff_rdata_w3_m_scanout[29];
assign dff_rdata_w1_m_scanin[29]=dff_rdata_w2_m_scanout[29];
assign dff_rdata_w0_m_scanin[29]=dff_rdata_w1_m_scanout[29];
assign dff_wdata_m_scanin[96]=dff_rdata_w0_m_scanout[29];
assign dff_wdata_m_scanin[24]=dff_wdata_m_scanout[96];
assign dff_rdata_w3_m_scanin[22]=dff_wdata_m_scanout[24];
assign dff_rdata_w2_m_scanin[22]=dff_rdata_w3_m_scanout[22];
assign dff_rdata_w1_m_scanin[22]=dff_rdata_w2_m_scanout[22];
assign dff_rdata_w0_m_scanin[22]=dff_rdata_w1_m_scanout[22];
assign dff_wdata_m_scanin[105]=dff_rdata_w0_m_scanout[22];
assign dff_wdata_m_scanin[33]=dff_wdata_m_scanout[105];
assign dff_rdata_w3_m_scanin[30]=dff_wdata_m_scanout[33];
assign dff_rdata_w2_m_scanin[30]=dff_rdata_w3_m_scanout[30];
assign dff_rdata_w1_m_scanin[30]=dff_rdata_w2_m_scanout[30];
assign dff_rdata_w0_m_scanin[30]=dff_rdata_w1_m_scanout[30];
assign dff_wdata_m_scanin[97]=dff_rdata_w0_m_scanout[30];
assign dff_wdata_m_scanin[25]=dff_wdata_m_scanout[97];
assign dff_rdata_w3_m_scanin[23]=dff_wdata_m_scanout[25];
assign dff_rdata_w2_m_scanin[23]=dff_rdata_w3_m_scanout[23];
assign dff_rdata_w1_m_scanin[23]=dff_rdata_w2_m_scanout[23];
assign dff_rdata_w0_m_scanin[23]=dff_rdata_w1_m_scanout[23];
assign dff_wdata_m_scanin[106]=dff_rdata_w0_m_scanout[23];
assign dff_wdata_m_scanin[34]=dff_wdata_m_scanout[106];
assign dff_rdata_w3_m_scanin[31]=dff_wdata_m_scanout[34];
assign dff_rdata_w2_m_scanin[31]=dff_rdata_w3_m_scanout[31];
assign dff_rdata_w1_m_scanin[31]=dff_rdata_w2_m_scanout[31];
assign dff_rdata_w0_m_scanin[31]=dff_rdata_w1_m_scanout[31];
assign dff_ctl_m_1_scanin[8]=dff_rdata_w0_m_scanout[31];
assign dff_ctl_m_1_scanin[0]=dff_ctl_m_1_scanout[8];
assign dff_ctl_m_1_scanin[9]=dff_ctl_m_1_scanout[0];
assign dff_ctl_m_1_scanin[1]=dff_ctl_m_1_scanout[9];
assign dff_ctl_m_1_scanin[10]=dff_ctl_m_1_scanout[1];
assign dff_ctl_m_1_scanin[2]=dff_ctl_m_1_scanout[10];
assign dff_ctl_m_1_scanin[11]=dff_ctl_m_1_scanout[2];
assign dff_ctl_m_1_scanin[3]=dff_ctl_m_1_scanout[11];
assign dff_byte_perr_w2_scanin[0]=dff_ctl_m_1_scanout[3];
assign dff_byte_perr_w3_scanin[0]=dff_byte_perr_w2_scanout[0];
assign dff_byte_perr_w3_scanin[1]=dff_byte_perr_w3_scanout[0];
assign dff_byte_perr_w2_scanin[1]=dff_byte_perr_w3_scanout[1];
assign dff_byte_perr_w2_scanin[2]=dff_byte_perr_w2_scanout[1];
assign dff_byte_perr_w3_scanin[2]=dff_byte_perr_w2_scanout[2];
assign dff_byte_perr_w3_scanin[3]=dff_byte_perr_w3_scanout[2];
assign dff_byte_perr_w2_scanin[3]=dff_byte_perr_w3_scanout[3];
assign dff_msb_w3_scanin[7]=dff_byte_perr_w2_scanout[3];
assign dff_msb_w2_scanin[7]=dff_msb_w3_scanout[7];
assign dff_msb_w1_scanin[7]=dff_msb_w2_scanout[7];
assign dff_msb_w0_scanin[7]=dff_msb_w1_scanout[7];
assign dff_msb_w3_scanin[6]=dff_msb_w0_scanout[7];
assign dff_msb_w2_scanin[6]=dff_msb_w3_scanout[6];
assign dff_msb_w1_scanin[6]=dff_msb_w2_scanout[6];
assign dff_msb_w0_scanin[6]=dff_msb_w1_scanout[6];
assign dff_msb_w3_scanin[5]=dff_msb_w0_scanout[6];
assign dff_msb_w2_scanin[5]=dff_msb_w3_scanout[5];
assign dff_msb_w1_scanin[5]=dff_msb_w2_scanout[5];
assign dff_msb_w0_scanin[5]=dff_msb_w1_scanout[5];
assign dff_msb_w3_scanin[4]=dff_msb_w0_scanout[5];
assign dff_msb_w2_scanin[4]=dff_msb_w3_scanout[4];
assign dff_msb_w1_scanin[4]=dff_msb_w2_scanout[4];
assign dff_msb_w0_scanin[4]=dff_msb_w1_scanout[4];
assign dff_msb_w3_scanin[0]=dff_msb_w0_scanout[4];
assign dff_msb_w2_scanin[0]=dff_msb_w3_scanout[0];
assign dff_msb_w1_scanin[0]=dff_msb_w2_scanout[0];
assign dff_msb_w0_scanin[0]=dff_msb_w1_scanout[0];
assign dff_msb_w3_scanin[1]=dff_msb_w0_scanout[0];
assign dff_msb_w2_scanin[1]=dff_msb_w3_scanout[1];
assign dff_msb_w1_scanin[1]=dff_msb_w2_scanout[1];
assign dff_msb_w0_scanin[1]=dff_msb_w1_scanout[1];
assign dff_msb_w3_scanin[2]=dff_msb_w0_scanout[1];
assign dff_msb_w2_scanin[2]=dff_msb_w3_scanout[2];
assign dff_msb_w1_scanin[2]=dff_msb_w2_scanout[2];
assign dff_msb_w0_scanin[2]=dff_msb_w1_scanout[2];
assign dff_msb_w3_scanin[3]=dff_msb_w0_scanout[2];
assign dff_msb_w2_scanin[3]=dff_msb_w3_scanout[3];
assign dff_msb_w1_scanin[3]=dff_msb_w2_scanout[3];
assign dff_msb_w0_scanin[3]=dff_msb_w1_scanout[3];
assign dff_red_out_scanin[2]=dff_msb_w0_scanout[3];
assign dff_red_out_scanin[3]=dff_red_out_scanout[2];
assign dff_red_out_scanin[4]=dff_red_out_scanout[3];
assign dff_red_out_scanin[5]=dff_red_out_scanout[4];
assign dff_red_out_scanin[6]=dff_red_out_scanout[5];
assign dff_red_out_scanin[7]=dff_red_out_scanout[6];
assign dff_red_out_scanin[0]=dff_red_out_scanout[7];
assign dff_red_out_scanin[1]=dff_red_out_scanout[0];
assign dff_red_in_scanin[2]=dff_red_out_scanout[1];
assign dff_red_in_scanin[3]=dff_red_in_scanout[2];
assign dff_red_in_scanin[1]=dff_red_in_scanout[3];
assign dff_red_in_scanin[0]=dff_red_in_scanout[1];
assign dff_red_in_scanin[6]=dff_red_in_scanout[0];
assign dff_red_in_scanin[7]=dff_red_in_scanout[6];
assign dff_red_in_scanin[8]=dff_red_in_scanout[7];
assign dff_red_in_scanin[9]=dff_red_in_scanout[8];
assign dff_red_in_scanin[10]=dff_red_in_scanout[9];
assign dff_red_in_scanin[11]=dff_red_in_scanout[10];
assign dff_red_in_scanin[4]=dff_red_in_scanout[11];
assign dff_red_in_scanin[5]=dff_red_in_scanout[4];
assign scan_out=dff_red_in_scanout[5];
// fixscan end

// synopsys translate_on

endmodule


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_8 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [7:0] din0;
  input [7:0] din1;
  input sel0;
  output [7:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_8 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
input [7:0] d;
  input [7:0] scan_in;
input l1clk;
input siclk;
input soclk;
  output [7:0] scan_out;
output [7:0] latout;
output [7:0] latout_l;


tisram_msff #(8)  d0_0 (
.d(d[7:0]),
.si(scan_in[7:0]),
.so(scan_out[7:0]),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[7:0]),
.latout_l(latout_l[7:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_mux_macro__mux_aodec__ports_4__width_4 (
  din0, 
  din1, 
  din2, 
  din3, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;

  input [3:0] din0;
  input [3:0] din1;
  input [3:0] din2;
  input [3:0] din3;
  input [1:0] sel;
  output [3:0] dout;


cl_dp1_pdec4_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3)
);

mux4s #(4)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .in0(din0[3:0]),
  .in1(din1[3:0]),
  .in2(din2[3:0]),
  .in3(din3[3:0]),
.dout(dout[3:0])
);


endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_7 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
input [6:0] d;
  input [6:0] scan_in;
input l1clk;
input siclk;
input soclk;
  output [6:0] scan_out;
output [6:0] latout;
output [6:0] latout_l;


tisram_msff #(7)  d0_0 (
.d(d[6:0]),
.si(scan_in[6:0]),
.so(scan_out[6:0]),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[6:0]),
.latout_l(latout_l[6:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;

  input [2:0] din;
  input l1clk;
  input [2:0] scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output [2:0] scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si(scan_in[2:0]),
.so(scan_out[2:0]),
.q(dout[2:0])
);


endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_dca_sp_9kb_cust_tisram_msff_macro__fs_1__width_16 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
input [15:0] d;
  input [15:0] scan_in;
input l1clk;
input siclk;
input soclk;
  output [15:0] scan_out;
output [15:0] latout;
output [15:0] latout_l;


tisram_msff #(16)  d0_0 (
.d(d[15:0]),
.si(scan_in[15:0]),
.so(scan_out[15:0]),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[15:0]),
.latout_l(latout_l[15:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;

  input [4:0] din;
  input l1clk;
  input [4:0] scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output [4:0] scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si(scan_in[4:0]),
.so(scan_out[4:0]),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_144 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [143:0] fdin;

  input [143:0] din;
  input l1clk;
  input [143:0] scan_in;


  input siclk;
  input soclk;

  output [143:0] dout;
  output [143:0] scan_out;
assign fdin[143:0] = din[143:0];


dff #(144)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[143:0]),
.si(scan_in[143:0]),
.so(scan_out[143:0]),
.q(dout[143:0])
);


endmodule


module n2_dca_sp_9kb_array (
  l1clk, 
  l1clk_wr, 
  l1clk_red, 
  rd_en_top_b, 
  rd_en_bot_b, 
  rd_en_a, 
  wr_en_a, 
  wr_en_b, 
  wr_inh_b, 
  addr_b, 
  byte_wr_en_b, 
  wr_waysel_b, 
  dcache_wdata_m, 
  dcache_wparity_m, 
  dcache_rdata_w0_m, 
  rparity_w0_m, 
  dcache_rdata_w1_m, 
  rparity_w1_m, 
  dcache_rdata_w2_m, 
  rparity_w2_m, 
  dcache_rdata_w3_m, 
  rparity_w3_m, 
  fuse_dca_repair_value, 
  fuse_dca_repair_en, 
  fuse_dca_rid, 
  fuse_dca_wen, 
  fuse_red_reset, 
  dca_fuse_repair_value, 
  dca_fuse_repair_en, 
  vnw_ary);
wire fuse_red_reset_qual;
wire fuse_dca_wen_qual;
wire [3:0] red_id;
wire [3:0] red_reg_clk_;
wire [5:0] red_data;
wire [1:0] red_enable;
wire [8:0] w0_byte7_l_unused;
wire [8:0] w0_byte6_l_unused;
wire [8:0] w0_byte5_l_unused;
wire [8:0] w0_byte4_l_unused;
wire [8:0] w0_byte3_l_unused;
wire [8:0] w0_byte2_l_unused;
wire [8:0] w0_byte1_l_unused;
wire [8:0] w0_byte0_l_unused;
wire [8:0] w1_byte7_l_unused;
wire [8:0] w1_byte6_l_unused;
wire [8:0] w1_byte5_l_unused;
wire [8:0] w1_byte4_l_unused;
wire [8:0] w1_byte3_l_unused;
wire [8:0] w1_byte2_l_unused;
wire [8:0] w1_byte1_l_unused;
wire [8:0] w1_byte0_l_unused;
wire [8:0] w2_byte7_l_unused;
wire [8:0] w2_byte6_l_unused;
wire [8:0] w2_byte5_l_unused;
wire [8:0] w2_byte4_l_unused;
wire [8:0] w2_byte3_l_unused;
wire [8:0] w2_byte2_l_unused;
wire [8:0] w2_byte1_l_unused;
wire [8:0] w2_byte0_l_unused;
wire [8:0] w3_byte7_l_unused;
wire [8:0] w3_byte6_l_unused;
wire [8:0] w3_byte5_l_unused;
wire [8:0] w3_byte4_l_unused;
wire [8:0] w3_byte3_l_unused;
wire [8:0] w3_byte2_l_unused;
wire [8:0] w3_byte1_l_unused;
wire [8:0] w3_byte0_l_unused;
       

input                   l1clk;          // l1clk from l1clk_header
input			l1clk_wr;
input			l1clk_red;
input                   rd_en_top_b;    // e_cycle b_phase signal
input                   rd_en_bot_b;    // e_cycle b_phase signal
input                   rd_en_a;        // m_cycle a_phase signal
input                   wr_en_a;        // m_cycle a_phase signal
input                   wr_en_b;        // e_cycle b_phase signal
input                   wr_inh_b;       // e_cycle b_phase signal
input   [10:3]          addr_b;         // e_cycle b_phase signal
input   [15:0]          byte_wr_en_b;   // e_cycle b_phase signal
input   [3:0]           wr_waysel_b;    // e_cycle b_phase signal

input	[127:0]		dcache_wdata_m;
input	[15:0]		dcache_wparity_m;

output	[63:0]		dcache_rdata_w0_m;
output	[7:0]		rparity_w0_m;
output	[63:0]		dcache_rdata_w1_m;
output	[7:0]		rparity_w1_m;
output	[63:0]		dcache_rdata_w2_m;
output	[7:0]		rparity_w2_m;
output	[63:0]		dcache_rdata_w3_m;
output	[7:0]		rparity_w3_m;

input	[5:0]	fuse_dca_repair_value;
input	[1:0]	fuse_dca_repair_en;
input	[1:0]	fuse_dca_rid;
input		fuse_dca_wen;
input		fuse_red_reset;
output	[5:0]	dca_fuse_repair_value;
output	[1:0]	dca_fuse_repair_en;

input		vnw_ary;

///////////////////////////////////////////
// Redundancy register logic
///////////////////////////////////////////

// Clock and data enables

assign fuse_red_reset_qual = fuse_red_reset & ~wr_inh_b;
assign fuse_dca_wen_qual = fuse_dca_wen & ~wr_inh_b;

assign red_id[0] = ~fuse_dca_rid[1] & ~fuse_dca_rid[0];
assign red_id[1] = ~fuse_dca_rid[1] &  fuse_dca_rid[0];
assign red_id[2] =  fuse_dca_rid[1] & ~fuse_dca_rid[0];
assign red_id[3] =  fuse_dca_rid[1] &  fuse_dca_rid[0];

assign red_reg_clk_[0] = ~(~l1clk_red & ((red_id[0] & fuse_dca_wen_qual) | fuse_red_reset_qual));
assign red_reg_clk_[1] = ~(~l1clk_red & ((red_id[1] & fuse_dca_wen_qual) | fuse_red_reset_qual));
assign red_reg_clk_[2] = ~(~l1clk_red & ((red_id[2] & fuse_dca_wen_qual) | fuse_red_reset_qual));
assign red_reg_clk_[3] = ~(~l1clk_red & ((red_id[3] & fuse_dca_wen_qual) | fuse_red_reset_qual));

assign red_data[5:0] = fuse_dca_repair_value[5:0] & {6{~fuse_red_reset_qual}};
assign red_enable[1:0] = fuse_dca_repair_en[1:0] & {2{~fuse_red_reset_qual}};

// 4 set of 8 registers.
// register is a simple b_latch. active when clk is low.

reg	[5:0]	red_reg_d_bl;
reg	[5:0]	red_reg_d_br;
reg	[5:0]	red_reg_d_tl;
reg	[5:0]	red_reg_d_tr;
reg	[1:0]	red_reg_en_bl;
reg	[1:0]	red_reg_en_br;
reg	[1:0]	red_reg_en_tl;
reg	[1:0]	red_reg_en_tr;

`ifndef NOINITMEM
// Initialize the arrays.
initial begin
  red_reg_d_bl[5:0] = 6'd0;
  red_reg_en_bl[1:0] = 2'd0;
  red_reg_d_br[5:0] = 6'd0;
  red_reg_en_br[1:0] = 2'd0;
  red_reg_d_tl[5:0] = 6'd0;
  red_reg_en_tl[1:0] = 2'd0;
  red_reg_d_tr[5:0] = 6'd0;
  red_reg_en_tr[1:0] = 2'd0;
end
`endif

always @(red_reg_clk_ or red_data or red_enable) begin
  if (~red_reg_clk_[0]) begin
    red_reg_d_bl[5:0]  = red_data[5:0];
    red_reg_en_bl[1:0] = red_enable[1:0];
  end
  if (~red_reg_clk_[1]) begin
    red_reg_d_br[5:0]  = red_data[5:0];
    red_reg_en_br[1:0] = red_enable[1:0];
  end
  if (~red_reg_clk_[2]) begin
    red_reg_d_tl[5:0]  = red_data[5:0];
    red_reg_en_tl[1:0] = red_enable[1:0];
  end
  if (~red_reg_clk_[3]) begin
    red_reg_d_tr[5:0]  = red_data[5:0];
    red_reg_en_tr[1:0] = red_enable[1:0];
  end
end

// output muxing
assign dca_fuse_repair_value[5:0] = (red_reg_d_tr[5:0] & {6{red_id[3]}}) |
                                    (red_reg_d_tl[5:0] & {6{red_id[2]}}) |
                                    (red_reg_d_br[5:0] & {6{red_id[1]}}) |
                                    (red_reg_d_bl[5:0] & {6{red_id[0]}});

assign dca_fuse_repair_en[1:0] = (red_reg_en_tr[1:0] & {2{red_id[3]}}) |
                                 (red_reg_en_tl[1:0] & {2{red_id[2]}}) |
                                 (red_reg_en_br[1:0] & {2{red_id[1]}}) |
                                 (red_reg_en_bl[1:0] & {2{red_id[0]}}) ;

// The two subarrays

n2_dca_sp_9kb_bank way01 (
	.red_data_l	(red_reg_d_tl[5:0]),
	.red_enable_l	(red_reg_en_tl[1:0]),
	.red_data_r	(red_reg_d_tr[5:0]),
	.red_enable_r	(red_reg_en_tr[1:0]),
	.rd_en_b	(rd_en_top_b),
	.wr_waysel_b	(wr_waysel_b[1:0]),
	.wrd_byte15_a	({dcache_wparity_m[15],dcache_wdata_m[127:120]}),
	.wrd_byte14_a	({dcache_wparity_m[14],dcache_wdata_m[119:112]}),
	.wrd_byte13_a	({dcache_wparity_m[13],dcache_wdata_m[111:104]}),
	.wrd_byte12_a	({dcache_wparity_m[12],dcache_wdata_m[103:96]}),
	.wrd_byte11_a	({dcache_wparity_m[11],dcache_wdata_m[95:88]}),
	.wrd_byte10_a	({dcache_wparity_m[10],dcache_wdata_m[87:80]}),
	.wrd_byte9_a	({dcache_wparity_m[9],dcache_wdata_m[79:72]}),
	.wrd_byte8_a	({dcache_wparity_m[8],dcache_wdata_m[71:64]}),
	.wrd_byte7_a	({dcache_wparity_m[7],dcache_wdata_m[63:56]}),
	.wrd_byte6_a	({dcache_wparity_m[6],dcache_wdata_m[55:48]}),
	.wrd_byte5_a	({dcache_wparity_m[5],dcache_wdata_m[47:40]}),
	.wrd_byte4_a	({dcache_wparity_m[4],dcache_wdata_m[39:32]}),
	.wrd_byte3_a	({dcache_wparity_m[3],dcache_wdata_m[31:24]}),
	.wrd_byte2_a	({dcache_wparity_m[2],dcache_wdata_m[23:16]}),
	.wrd_byte1_a	({dcache_wparity_m[1],dcache_wdata_m[15:8]}),
	.wrd_byte0_a	({dcache_wparity_m[0],dcache_wdata_m[7:0]}),
	.w0_byte7_h	({rparity_w0_m[7],dcache_rdata_w0_m[63:56]}),
	.w0_byte6_h	({rparity_w0_m[6],dcache_rdata_w0_m[55:48]}),
	.w0_byte5_h	({rparity_w0_m[5],dcache_rdata_w0_m[47:40]}),
	.w0_byte4_h	({rparity_w0_m[4],dcache_rdata_w0_m[39:32]}),
	.w0_byte3_h	({rparity_w0_m[3],dcache_rdata_w0_m[31:24]}),
	.w0_byte2_h	({rparity_w0_m[2],dcache_rdata_w0_m[23:16]}),
	.w0_byte1_h	({rparity_w0_m[1],dcache_rdata_w0_m[15:8]}),
	.w0_byte0_h	({rparity_w0_m[0],dcache_rdata_w0_m[7:0]}),
	.w1_byte7_h	({rparity_w1_m[7],dcache_rdata_w1_m[63:56]}),
	.w1_byte6_h	({rparity_w1_m[6],dcache_rdata_w1_m[55:48]}),
	.w1_byte5_h	({rparity_w1_m[5],dcache_rdata_w1_m[47:40]}),
	.w1_byte4_h	({rparity_w1_m[4],dcache_rdata_w1_m[39:32]}),
	.w1_byte3_h	({rparity_w1_m[3],dcache_rdata_w1_m[31:24]}),
	.w1_byte2_h	({rparity_w1_m[2],dcache_rdata_w1_m[23:16]}),
	.w1_byte1_h	({rparity_w1_m[1],dcache_rdata_w1_m[15:8]}),
	.w1_byte0_h	({rparity_w1_m[0],dcache_rdata_w1_m[7:0]}),
	.w0_byte7_l	(w0_byte7_l_unused[8:0]),
	.w0_byte6_l	(w0_byte6_l_unused[8:0]),
	.w0_byte5_l	(w0_byte5_l_unused[8:0]),
	.w0_byte4_l	(w0_byte4_l_unused[8:0]),
	.w0_byte3_l	(w0_byte3_l_unused[8:0]),
	.w0_byte2_l	(w0_byte2_l_unused[8:0]),
	.w0_byte1_l	(w0_byte1_l_unused[8:0]),
	.w0_byte0_l	(w0_byte0_l_unused[8:0]),
	.w1_byte7_l	(w1_byte7_l_unused[8:0]),
	.w1_byte6_l	(w1_byte6_l_unused[8:0]),
	.w1_byte5_l	(w1_byte5_l_unused[8:0]),
	.w1_byte4_l	(w1_byte4_l_unused[8:0]),
	.w1_byte3_l	(w1_byte3_l_unused[8:0]),
	.w1_byte2_l	(w1_byte2_l_unused[8:0]),
	.w1_byte1_l	(w1_byte1_l_unused[8:0]),
	.w1_byte0_l	(w1_byte0_l_unused[8:0]),
  .l1clk(l1clk),
  .l1clk_wr(l1clk_wr),
  .rd_en_a(rd_en_a),
  .wr_en_a(wr_en_a),
  .wr_en_b(wr_en_b),
  .wr_inh_b(wr_inh_b),
  .addr_b(addr_b[10:3]),
  .byte_wr_en_b(byte_wr_en_b[15:0]),
  .vnw_ary(vnw_ary)
);

n2_dca_sp_9kb_bank way23 (
	.red_data_l	(red_reg_d_bl[5:0]),
	.red_enable_l	(red_reg_en_bl[1:0]),
	.red_data_r	(red_reg_d_br[5:0]),
	.red_enable_r	(red_reg_en_br[1:0]),
	.rd_en_b	(rd_en_bot_b),
	.wr_waysel_b	(wr_waysel_b[3:2]),
	.wrd_byte15_a	({dcache_wparity_m[15],dcache_wdata_m[127:120]}),
	.wrd_byte14_a	({dcache_wparity_m[14],dcache_wdata_m[119:112]}),
	.wrd_byte13_a	({dcache_wparity_m[13],dcache_wdata_m[111:104]}),
	.wrd_byte12_a	({dcache_wparity_m[12],dcache_wdata_m[103:96]}),
	.wrd_byte11_a	({dcache_wparity_m[11],dcache_wdata_m[95:88]}),
	.wrd_byte10_a	({dcache_wparity_m[10],dcache_wdata_m[87:80]}),
	.wrd_byte9_a	({dcache_wparity_m[9],dcache_wdata_m[79:72]}),
	.wrd_byte8_a	({dcache_wparity_m[8],dcache_wdata_m[71:64]}),
	.wrd_byte7_a	({dcache_wparity_m[7],dcache_wdata_m[63:56]}),
	.wrd_byte6_a	({dcache_wparity_m[6],dcache_wdata_m[55:48]}),
	.wrd_byte5_a	({dcache_wparity_m[5],dcache_wdata_m[47:40]}),
	.wrd_byte4_a	({dcache_wparity_m[4],dcache_wdata_m[39:32]}),
	.wrd_byte3_a	({dcache_wparity_m[3],dcache_wdata_m[31:24]}),
	.wrd_byte2_a	({dcache_wparity_m[2],dcache_wdata_m[23:16]}),
	.wrd_byte1_a	({dcache_wparity_m[1],dcache_wdata_m[15:8]}),
	.wrd_byte0_a	({dcache_wparity_m[0],dcache_wdata_m[7:0]}),
	.w0_byte7_h	({rparity_w2_m[7],dcache_rdata_w2_m[63:56]}),
	.w0_byte6_h	({rparity_w2_m[6],dcache_rdata_w2_m[55:48]}),
	.w0_byte5_h	({rparity_w2_m[5],dcache_rdata_w2_m[47:40]}),
	.w0_byte4_h	({rparity_w2_m[4],dcache_rdata_w2_m[39:32]}),
	.w0_byte3_h	({rparity_w2_m[3],dcache_rdata_w2_m[31:24]}),
	.w0_byte2_h	({rparity_w2_m[2],dcache_rdata_w2_m[23:16]}),
	.w0_byte1_h	({rparity_w2_m[1],dcache_rdata_w2_m[15:8]}),
	.w0_byte0_h	({rparity_w2_m[0],dcache_rdata_w2_m[7:0]}),
	.w1_byte7_h	({rparity_w3_m[7],dcache_rdata_w3_m[63:56]}),
	.w1_byte6_h	({rparity_w3_m[6],dcache_rdata_w3_m[55:48]}),
	.w1_byte5_h	({rparity_w3_m[5],dcache_rdata_w3_m[47:40]}),
	.w1_byte4_h	({rparity_w3_m[4],dcache_rdata_w3_m[39:32]}),
	.w1_byte3_h	({rparity_w3_m[3],dcache_rdata_w3_m[31:24]}),
	.w1_byte2_h	({rparity_w3_m[2],dcache_rdata_w3_m[23:16]}),
	.w1_byte1_h	({rparity_w3_m[1],dcache_rdata_w3_m[15:8]}),
	.w1_byte0_h	({rparity_w3_m[0],dcache_rdata_w3_m[7:0]}),
	.w0_byte7_l	(w2_byte7_l_unused[8:0]),
	.w0_byte6_l	(w2_byte6_l_unused[8:0]),
	.w0_byte5_l	(w2_byte5_l_unused[8:0]),
	.w0_byte4_l	(w2_byte4_l_unused[8:0]),
	.w0_byte3_l	(w2_byte3_l_unused[8:0]),
	.w0_byte2_l	(w2_byte2_l_unused[8:0]),
	.w0_byte1_l	(w2_byte1_l_unused[8:0]),
	.w0_byte0_l	(w2_byte0_l_unused[8:0]),
	.w1_byte7_l	(w3_byte7_l_unused[8:0]),
	.w1_byte6_l	(w3_byte6_l_unused[8:0]),
	.w1_byte5_l	(w3_byte5_l_unused[8:0]),
	.w1_byte4_l	(w3_byte4_l_unused[8:0]),
	.w1_byte3_l	(w3_byte3_l_unused[8:0]),
	.w1_byte2_l	(w3_byte2_l_unused[8:0]),
	.w1_byte1_l	(w3_byte1_l_unused[8:0]),
	.w1_byte0_l	(w3_byte0_l_unused[8:0]),
  .l1clk(l1clk),
  .l1clk_wr(l1clk_wr),
  .rd_en_a(rd_en_a),
  .wr_en_a(wr_en_a),
  .wr_en_b(wr_en_b),
  .wr_inh_b(wr_inh_b),
  .addr_b(addr_b[10:3]),
  .byte_wr_en_b(byte_wr_en_b[15:0]),
  .vnw_ary(vnw_ary)
);


supply0 vss;
supply1 vdd;
endmodule


module n2_dca_sp_9kb_bank (
  l1clk, 
  l1clk_wr, 
  rd_en_b, 
  rd_en_a, 
  wr_en_a, 
  wr_en_b, 
  wr_inh_b, 
  addr_b, 
  byte_wr_en_b, 
  wr_waysel_b, 
  red_data_l, 
  red_data_r, 
  red_enable_l, 
  red_enable_r, 
  vnw_ary, 
  wrd_byte15_a, 
  wrd_byte14_a, 
  wrd_byte13_a, 
  wrd_byte12_a, 
  wrd_byte11_a, 
  wrd_byte10_a, 
  wrd_byte9_a, 
  wrd_byte8_a, 
  wrd_byte7_a, 
  wrd_byte6_a, 
  wrd_byte5_a, 
  wrd_byte4_a, 
  wrd_byte3_a, 
  wrd_byte2_a, 
  wrd_byte1_a, 
  wrd_byte0_a, 
  w1_byte7_h, 
  w1_byte6_h, 
  w1_byte5_h, 
  w1_byte4_h, 
  w1_byte3_h, 
  w1_byte2_h, 
  w1_byte1_h, 
  w1_byte0_h, 
  w1_byte7_l, 
  w1_byte6_l, 
  w1_byte5_l, 
  w1_byte4_l, 
  w1_byte3_l, 
  w1_byte2_l, 
  w1_byte1_l, 
  w1_byte0_l, 
  w0_byte7_h, 
  w0_byte6_h, 
  w0_byte5_h, 
  w0_byte4_h, 
  w0_byte3_h, 
  w0_byte2_h, 
  w0_byte1_h, 
  w0_byte0_h, 
  w0_byte7_l, 
  w0_byte6_l, 
  w0_byte5_l, 
  w0_byte4_l, 
  w0_byte3_l, 
  w0_byte2_l, 
  w0_byte1_l, 
  w0_byte0_l);       

`define WIDTH 288
`define ENTRIES 128

// way0 and way1 are interleaved physically across 2 subbanks
//        [288,277,..................,145,144] -- xdec -- [143,142,.............,1,0]
//          H   L   H   L       H   L   H   L  -- xdec --  L   H   L   H      L H L H      
// way1 = [288,287,284,283,...,151,150,147,146 -- xdec -- 141,140,137,136,...,5,4,1,0
// way0 = [286,285,282,281,...,149,148,145,144 -- xdec -- 143,142,139,138,...,7,6,3,2

input                   l1clk;          // l1clk from l1clk_header
input                   l1clk_wr;       // l1clk from l1clk_header
input                   rd_en_b;        // e_cycle b_phase signal
input                   rd_en_a;        // m_cycle a_phase signal
input                   wr_en_a;        // m_cycle a_phase signal
input                   wr_en_b;        // e_cycle b_phase signal
input                   wr_inh_b;       // e_cycle b_phase signal
input   [10:3]          addr_b;         // e_cycle b_phase signal
input   [15:0]          byte_wr_en_b;   // e_cycle b_phase signal
input   [1:0]           wr_waysel_b;    // e_cycle b_phase signal

input	[5:0]		red_data_l;
input	[5:0]		red_data_r;
input	[1:0]		red_enable_l;
input	[1:0]		red_enable_r;

input			vnw_ary;

input   [8:0]           wrd_byte15_a;   // m_cycle a_phase signal
input   [8:0]           wrd_byte14_a;
input   [8:0]           wrd_byte13_a;
input   [8:0]           wrd_byte12_a;
input   [8:0]           wrd_byte11_a;
input   [8:0]           wrd_byte10_a;
input   [8:0]           wrd_byte9_a;
input   [8:0]           wrd_byte8_a;
input   [8:0]           wrd_byte7_a;
input   [8:0]           wrd_byte6_a;
input   [8:0]           wrd_byte5_a;
input   [8:0]           wrd_byte4_a;
input   [8:0]           wrd_byte3_a;
input   [8:0]           wrd_byte2_a;
input   [8:0]           wrd_byte1_a;
input   [8:0]           wrd_byte0_a;

output  [8:0]           w1_byte7_h;     // m_cycle b_phase clock-like signal    
output  [8:0]           w1_byte6_h;
output  [8:0]           w1_byte5_h;
output  [8:0]           w1_byte4_h;
output  [8:0]           w1_byte3_h;
output  [8:0]           w1_byte2_h;
output  [8:0]           w1_byte1_h;
output  [8:0]           w1_byte0_h;
output  [8:0]           w1_byte7_l;
output  [8:0]           w1_byte6_l;
output  [8:0]           w1_byte5_l;
output  [8:0]           w1_byte4_l;
output  [8:0]           w1_byte3_l;
output  [8:0]           w1_byte2_l;
output  [8:0]           w1_byte1_l;
output  [8:0]           w1_byte0_l;

output  [8:0]           w0_byte7_h;     // m_cycle b_phase clock-like signal    
output  [8:0]           w0_byte6_h;
output  [8:0]           w0_byte5_h;
output  [8:0]           w0_byte4_h;
output  [8:0]           w0_byte3_h;
output  [8:0]           w0_byte2_h;
output  [8:0]           w0_byte1_h;
output  [8:0]           w0_byte0_h;
output  [8:0]           w0_byte7_l;
output  [8:0]           w0_byte6_l;
output  [8:0]           w0_byte5_l;
output  [8:0]           w0_byte4_l;
output  [8:0]           w0_byte3_l;
output  [8:0]           w0_byte2_l;
output  [8:0]           w0_byte1_l;
output  [8:0]           w0_byte0_l;


reg	[71:0]		w0_sao_h;
reg	[71:0]		w0_sao_l;
reg	[71:0]		w1_sao_h;
reg	[71:0]		w1_sao_l;


n2_dca_sp_9kb_subbank left (
	.byte_wr_en_b 	({byte_wr_en_b[15],byte_wr_en_b[7],byte_wr_en_b[14],byte_wr_en_b[6],
			  byte_wr_en_b[13],byte_wr_en_b[5],byte_wr_en_b[12],byte_wr_en_b[4]}),
	.wr_data_a	({wrd_byte15_a[8], wrd_byte7_a[8], wrd_byte14_a[8], wrd_byte6_a[8], 
			  wrd_byte15_a[7], wrd_byte7_a[7], wrd_byte14_a[7], wrd_byte6_a[7],
			  wrd_byte15_a[6], wrd_byte7_a[6], wrd_byte14_a[6], wrd_byte6_a[6],
			  wrd_byte15_a[5], wrd_byte7_a[5], wrd_byte14_a[5], wrd_byte6_a[5],
			  wrd_byte15_a[4], wrd_byte7_a[4], wrd_byte14_a[4], wrd_byte6_a[4],
			  wrd_byte15_a[3], wrd_byte7_a[3], wrd_byte14_a[3], wrd_byte6_a[3],
			  wrd_byte15_a[2], wrd_byte7_a[2], wrd_byte14_a[2], wrd_byte6_a[2],
			  wrd_byte15_a[1], wrd_byte7_a[1], wrd_byte14_a[1], wrd_byte6_a[1],
			  wrd_byte15_a[0], wrd_byte7_a[0], wrd_byte14_a[0], wrd_byte6_a[0],
			  wrd_byte13_a[8], wrd_byte5_a[8], wrd_byte12_a[8], wrd_byte4_a[8], 
			  wrd_byte13_a[7], wrd_byte5_a[7], wrd_byte12_a[7], wrd_byte4_a[7],
			  wrd_byte13_a[6], wrd_byte5_a[6], wrd_byte12_a[6], wrd_byte4_a[6],
			  wrd_byte13_a[5], wrd_byte5_a[5], wrd_byte12_a[5], wrd_byte4_a[5],
			  wrd_byte13_a[4], wrd_byte5_a[4], wrd_byte12_a[4], wrd_byte4_a[4],
			  wrd_byte13_a[3], wrd_byte5_a[3], wrd_byte12_a[3], wrd_byte4_a[3],
			  wrd_byte13_a[2], wrd_byte5_a[2], wrd_byte12_a[2], wrd_byte4_a[2],
			  wrd_byte13_a[1], wrd_byte5_a[1], wrd_byte12_a[1], wrd_byte4_a[1],
			  wrd_byte13_a[0], wrd_byte5_a[0], wrd_byte12_a[0], wrd_byte4_a[0]}),
	.red_data	(red_data_l[5:0]),
	.red_en		(red_enable_l[1:0]),
	.w0_rdata_h	({w0_byte7_h[8],w0_byte6_h[8],w0_byte7_h[7],w0_byte6_h[7],
			  w0_byte7_h[6],w0_byte6_h[6],w0_byte7_h[5],w0_byte6_h[5],
			  w0_byte7_h[4],w0_byte6_h[4],w0_byte7_h[3],w0_byte6_h[3],
			  w0_byte7_h[2],w0_byte6_h[2],w0_byte7_h[1],w0_byte6_h[1],
			  w0_byte7_h[0],w0_byte6_h[0],w0_byte5_h[8],w0_byte4_h[8],
	 		  w0_byte5_h[7],w0_byte4_h[7],w0_byte5_h[6],w0_byte4_h[6],
	 		  w0_byte5_h[5],w0_byte4_h[5],w0_byte5_h[4],w0_byte4_h[4],
	 		  w0_byte5_h[3],w0_byte4_h[3],w0_byte5_h[2],w0_byte4_h[2],
	 		  w0_byte5_h[1],w0_byte4_h[1],w0_byte5_h[0],w0_byte4_h[0]}),
	.w0_rdata_l	({w0_byte7_l[8],w0_byte6_l[8],w0_byte7_l[7],w0_byte6_l[7],
			  w0_byte7_l[6],w0_byte6_l[6],w0_byte7_l[5],w0_byte6_l[5],
			  w0_byte7_l[4],w0_byte6_l[4],w0_byte7_l[3],w0_byte6_l[3],
			  w0_byte7_l[2],w0_byte6_l[2],w0_byte7_l[1],w0_byte6_l[1],
			  w0_byte7_l[0],w0_byte6_l[0],w0_byte5_l[8],w0_byte4_l[8],
	 		  w0_byte5_l[7],w0_byte4_l[7],w0_byte5_l[6],w0_byte4_l[6],
	 		  w0_byte5_l[5],w0_byte4_l[5],w0_byte5_l[4],w0_byte4_l[4],
	 		  w0_byte5_l[3],w0_byte4_l[3],w0_byte5_l[2],w0_byte4_l[2],
	 		  w0_byte5_l[1],w0_byte4_l[1],w0_byte5_l[0],w0_byte4_l[0]}),
	.w1_rdata_h	({w1_byte7_h[8],w1_byte6_h[8],w1_byte7_h[7],w1_byte6_h[7],
			  w1_byte7_h[6],w1_byte6_h[6],w1_byte7_h[5],w1_byte6_h[5],
			  w1_byte7_h[4],w1_byte6_h[4],w1_byte7_h[3],w1_byte6_h[3],
			  w1_byte7_h[2],w1_byte6_h[2],w1_byte7_h[1],w1_byte6_h[1],
			  w1_byte7_h[0],w1_byte6_h[0],w1_byte5_h[8],w1_byte4_h[8],
	 		  w1_byte5_h[7],w1_byte4_h[7],w1_byte5_h[6],w1_byte4_h[6],
	 		  w1_byte5_h[5],w1_byte4_h[5],w1_byte5_h[4],w1_byte4_h[4],
	 		  w1_byte5_h[3],w1_byte4_h[3],w1_byte5_h[2],w1_byte4_h[2],
	 		  w1_byte5_h[1],w1_byte4_h[1],w1_byte5_h[0],w1_byte4_h[0]}),
	.w1_rdata_l	({w1_byte7_l[8],w1_byte6_l[8],w1_byte7_l[7],w1_byte6_l[7],
			  w1_byte7_l[6],w1_byte6_l[6],w1_byte7_l[5],w1_byte6_l[5],
			  w1_byte7_l[4],w1_byte6_l[4],w1_byte7_l[3],w1_byte6_l[3],
			  w1_byte7_l[2],w1_byte6_l[2],w1_byte7_l[1],w1_byte6_l[1],
			  w1_byte7_l[0],w1_byte6_l[0],w1_byte5_l[8],w1_byte4_l[8],
	 		  w1_byte5_l[7],w1_byte4_l[7],w1_byte5_l[6],w1_byte4_l[6],
	 		  w1_byte5_l[5],w1_byte4_l[5],w1_byte5_l[4],w1_byte4_l[4],
	 		  w1_byte5_l[3],w1_byte4_l[3],w1_byte5_l[2],w1_byte4_l[2],
	 		  w1_byte5_l[1],w1_byte4_l[1],w1_byte5_l[0],w1_byte4_l[0]}),
  .l1clk(l1clk),
  .l1clk_wr(l1clk_wr),
  .rd_en_b(rd_en_b),
  .rd_en_a(rd_en_a),
  .wr_en_a(wr_en_a),
  .wr_en_b(wr_en_b),
  .wr_inh_b(wr_inh_b),
  .addr_b(addr_b[10:3]),
  .wr_waysel_b(wr_waysel_b[1:0]),
  .vnw_ary(vnw_ary)
);

// The right subbank is a mirrored copy of the left (redundant columns on the left),
// so all I/O's must be reverse ordered.

n2_dca_sp_9kb_subbank right (
	.byte_wr_en_b 	({byte_wr_en_b[8],byte_wr_en_b[0],byte_wr_en_b[9],byte_wr_en_b[1],
			  byte_wr_en_b[10],byte_wr_en_b[2],byte_wr_en_b[11],byte_wr_en_b[3]}),
	.wr_data_a	({wrd_byte8_a[8], wrd_byte0_a[8], wrd_byte9_a[8], wrd_byte1_a[8], 
			  wrd_byte8_a[0], wrd_byte0_a[0], wrd_byte9_a[0], wrd_byte1_a[0],
			  wrd_byte8_a[1], wrd_byte0_a[1], wrd_byte9_a[1], wrd_byte1_a[1],
			  wrd_byte8_a[2], wrd_byte0_a[2], wrd_byte9_a[2], wrd_byte1_a[2],
			  wrd_byte8_a[3], wrd_byte0_a[3], wrd_byte9_a[3], wrd_byte1_a[3],
			  wrd_byte8_a[4], wrd_byte0_a[4], wrd_byte9_a[4], wrd_byte1_a[4],
			  wrd_byte8_a[5], wrd_byte0_a[5], wrd_byte9_a[5], wrd_byte1_a[5],
			  wrd_byte8_a[6], wrd_byte0_a[6], wrd_byte9_a[6], wrd_byte1_a[6],
			  wrd_byte8_a[7], wrd_byte0_a[7], wrd_byte9_a[7], wrd_byte1_a[7],
			  wrd_byte10_a[8], wrd_byte2_a[8], wrd_byte11_a[8], wrd_byte3_a[8], 
			  wrd_byte10_a[0], wrd_byte2_a[0], wrd_byte11_a[0], wrd_byte3_a[0],
			  wrd_byte10_a[1], wrd_byte2_a[1], wrd_byte11_a[1], wrd_byte3_a[1],
			  wrd_byte10_a[2], wrd_byte2_a[2], wrd_byte11_a[2], wrd_byte3_a[2],
			  wrd_byte10_a[3], wrd_byte2_a[3], wrd_byte11_a[3], wrd_byte3_a[3],
			  wrd_byte10_a[4], wrd_byte2_a[4], wrd_byte11_a[4], wrd_byte3_a[4],
			  wrd_byte10_a[5], wrd_byte2_a[5], wrd_byte11_a[5], wrd_byte3_a[5],
			  wrd_byte10_a[6], wrd_byte2_a[6], wrd_byte11_a[6], wrd_byte3_a[6],
			  wrd_byte10_a[7], wrd_byte2_a[7], wrd_byte11_a[7], wrd_byte3_a[7]}),
	.red_data	(red_data_r[5:0]),
	.red_en		(red_enable_r[1:0]),
	.w0_rdata_h	({w0_byte0_h[8],w0_byte1_h[8],w0_byte0_h[0],w0_byte1_h[0],
			  w0_byte0_h[1],w0_byte1_h[1],w0_byte0_h[2],w0_byte1_h[2],
			  w0_byte0_h[3],w0_byte1_h[3],w0_byte0_h[4],w0_byte1_h[4],
			  w0_byte0_h[5],w0_byte1_h[5],w0_byte0_h[6],w0_byte1_h[6],
			  w0_byte0_h[7],w0_byte1_h[7],w0_byte2_h[8],w0_byte3_h[8],
			  w0_byte2_h[0],w0_byte3_h[0],w0_byte2_h[1],w0_byte3_h[1],
			  w0_byte2_h[2],w0_byte3_h[2],w0_byte2_h[3],w0_byte3_h[3],
			  w0_byte2_h[4],w0_byte3_h[4],w0_byte2_h[5],w0_byte3_h[5],
			  w0_byte2_h[6],w0_byte3_h[6],w0_byte2_h[7],w0_byte3_h[7]}),
	.w0_rdata_l	({w0_byte0_l[8],w0_byte1_l[8],w0_byte0_l[0],w0_byte1_l[0],
			  w0_byte0_l[1],w0_byte1_l[1],w0_byte0_l[2],w0_byte1_l[2],
			  w0_byte0_l[3],w0_byte1_l[3],w0_byte0_l[4],w0_byte1_l[4],
			  w0_byte0_l[5],w0_byte1_l[5],w0_byte0_l[6],w0_byte1_l[6],
			  w0_byte0_l[7],w0_byte1_l[7],w0_byte2_l[8],w0_byte3_l[8],
			  w0_byte2_l[0],w0_byte3_l[0],w0_byte2_l[1],w0_byte3_l[1],
			  w0_byte2_l[2],w0_byte3_l[2],w0_byte2_l[3],w0_byte3_l[3],
			  w0_byte2_l[4],w0_byte3_l[4],w0_byte2_l[5],w0_byte3_l[5],
			  w0_byte2_l[6],w0_byte3_l[6],w0_byte2_l[7],w0_byte3_l[7]}),
	.w1_rdata_h	({w1_byte0_h[8],w1_byte1_h[8],w1_byte0_h[0],w1_byte1_h[0],
			  w1_byte0_h[1],w1_byte1_h[1],w1_byte0_h[2],w1_byte1_h[2],
			  w1_byte0_h[3],w1_byte1_h[3],w1_byte0_h[4],w1_byte1_h[4],
			  w1_byte0_h[5],w1_byte1_h[5],w1_byte0_h[6],w1_byte1_h[6],
			  w1_byte0_h[7],w1_byte1_h[7],w1_byte2_h[8],w1_byte3_h[8],
			  w1_byte2_h[0],w1_byte3_h[0],w1_byte2_h[1],w1_byte3_h[1],
			  w1_byte2_h[2],w1_byte3_h[2],w1_byte2_h[3],w1_byte3_h[3],
			  w1_byte2_h[4],w1_byte3_h[4],w1_byte2_h[5],w1_byte3_h[5],
			  w1_byte2_h[6],w1_byte3_h[6],w1_byte2_h[7],w1_byte3_h[7]}),
	.w1_rdata_l	({w1_byte0_l[8],w1_byte1_l[8],w1_byte0_l[0],w1_byte1_l[0],
			  w1_byte0_l[1],w1_byte1_l[1],w1_byte0_l[2],w1_byte1_l[2],
			  w1_byte0_l[3],w1_byte1_l[3],w1_byte0_l[4],w1_byte1_l[4],
			  w1_byte0_l[5],w1_byte1_l[5],w1_byte0_l[6],w1_byte1_l[6],
			  w1_byte0_l[7],w1_byte1_l[7],w1_byte2_l[8],w1_byte3_l[8],
			  w1_byte2_l[0],w1_byte3_l[0],w1_byte2_l[1],w1_byte3_l[1],
			  w1_byte2_l[2],w1_byte3_l[2],w1_byte2_l[3],w1_byte3_l[3],
			  w1_byte2_l[4],w1_byte3_l[4],w1_byte2_l[5],w1_byte3_l[5],
			  w1_byte2_l[6],w1_byte3_l[6],w1_byte2_l[7],w1_byte3_l[7]}),
  .l1clk(l1clk),
  .l1clk_wr(l1clk_wr),
  .rd_en_b(rd_en_b),
  .rd_en_a(rd_en_a),
  .wr_en_a(wr_en_a),
  .wr_en_b(wr_en_b),
  .wr_inh_b(wr_inh_b),
  .addr_b(addr_b[10:3]),
  .wr_waysel_b(wr_waysel_b[1:0]),
  .vnw_ary(vnw_ary)
);


supply0 vss;
supply1 vdd;
endmodule


module n2_dca_sp_9kb_subbank (
  l1clk, 
  l1clk_wr, 
  rd_en_b, 
  rd_en_a, 
  wr_en_a, 
  wr_en_b, 
  wr_inh_b, 
  addr_b, 
  byte_wr_en_b, 
  wr_waysel_b, 
  wr_data_a, 
  red_data, 
  red_en, 
  vnw_ary, 
  w0_rdata_h, 
  w0_rdata_l, 
  w1_rdata_h, 
  w1_rdata_l);
wire red_shift_en;
wire [143:0] data_in;
wire [143:0] byte_mask;
wire w0_wcs;
wire w1_wcs;
wire [143:0] way_mask;
wire [143:0] local_dout;
wire rcs_l;
wire [35:0] w0_dout;
wire [35:0] w1_dout;
       

`define ENTRIES 128

// way0 and way1 are interleaved physically across 2 subbanks
//        [288,277,..................,145,144] -- xdec -- [143,142,.............,1,0]
//          H   L   H   L       H   L   H   L  -- xdec --  L   H   L   H      L H L H      
// way1 = [288,287,284,283,...,151,150,147,146 -- xdec -- 141,140,137,136,...,5,4,1,0
// way0 = [286,285,282,281,...,149,148,145,144 -- xdec -- 143,142,139,138,...,7,6,3,2

input		l1clk;          // l1clk from l1clk_header
input		l1clk_wr;       // l1clk from l1clk_header
input		rd_en_b;        // e_cycle b_phase signal
input		rd_en_a;        // m_cycle a_phase signal
input		wr_en_a;        // m_cycle a_phase signal
input		wr_en_b;        // e_cycle b_phase signal
input		wr_inh_b;       // e_cycle b_phase signal
input   [10:3]	addr_b;         // e_cycle b_phase signal
input   [7:0]	byte_wr_en_b;   // e_cycle b_phase signal
input   [1:0]	wr_waysel_b;    // e_cycle b_phase signal

input   [71:0]	wr_data_a;   // m_cycle a_phase signal

input	[5:0]	red_data;
input	[1:0]	red_en;

input		vnw_ary;

output  [35:0]	w0_rdata_h;     // m_cycle b_phase clock-like signal    
output  [35:0]	w0_rdata_l;     // m_cycle b_phase clock-like signal    
output  [35:0]	w1_rdata_h;     // m_cycle b_phase clock-like signal    
output  [35:0]	w1_rdata_l;     // m_cycle b_phase clock-like signal    

// synopsys translate_off

reg     [147:0]	mem[`ENTRIES-1:0];
reg     [143:0]	dout;
reg	[35:0]	w0_sao_h;
reg	[35:0]	w0_sao_l;
reg	[35:0]	w1_sao_h;
reg	[35:0]	w1_sao_l;

wire	[147:0]	wr_data;
wire	[143:0]	din;
wire	[147:0]	temp;


assign red_shift_en = red_en[1] & red_en[0];

//////////////////////////////////
// Initialize to zeros
`ifndef NOINITMEM
integer i;
initial begin
  for (i=0;i<128;i=i+1) begin
  mem[i] =  148'd0;
  end
end
`endif

/////////////////////////////
// wrdata input mapping 
////////////////////////////

assign data_in[143:0] = {
	wr_data_a[71],wr_data_a[70],wr_data_a[71],wr_data_a[70],
	wr_data_a[69],wr_data_a[68],wr_data_a[69],wr_data_a[68],
	wr_data_a[67],wr_data_a[66],wr_data_a[67],wr_data_a[66],
	wr_data_a[65],wr_data_a[64],wr_data_a[65],wr_data_a[64],
	wr_data_a[63],wr_data_a[62],wr_data_a[63],wr_data_a[62],
	wr_data_a[61],wr_data_a[60],wr_data_a[61],wr_data_a[60],
	wr_data_a[59],wr_data_a[58],wr_data_a[59],wr_data_a[58],
	wr_data_a[57],wr_data_a[56],wr_data_a[57],wr_data_a[56],
	wr_data_a[55],wr_data_a[54],wr_data_a[55],wr_data_a[54],
	wr_data_a[53],wr_data_a[52],wr_data_a[53],wr_data_a[52],
	wr_data_a[51],wr_data_a[50],wr_data_a[51],wr_data_a[50],
	wr_data_a[49],wr_data_a[48],wr_data_a[49],wr_data_a[48],
	wr_data_a[47],wr_data_a[46],wr_data_a[47],wr_data_a[46],
	wr_data_a[45],wr_data_a[44],wr_data_a[45],wr_data_a[44],
	wr_data_a[43],wr_data_a[42],wr_data_a[43],wr_data_a[42],
	wr_data_a[41],wr_data_a[40],wr_data_a[41],wr_data_a[40],
	wr_data_a[39],wr_data_a[38],wr_data_a[39],wr_data_a[38],
	wr_data_a[37],wr_data_a[36],wr_data_a[37],wr_data_a[36],
	wr_data_a[35],wr_data_a[34],wr_data_a[35],wr_data_a[34],
	wr_data_a[33],wr_data_a[32],wr_data_a[33],wr_data_a[32],
	wr_data_a[31],wr_data_a[30],wr_data_a[31],wr_data_a[30],
	wr_data_a[29],wr_data_a[28],wr_data_a[29],wr_data_a[28],
	wr_data_a[27],wr_data_a[26],wr_data_a[27],wr_data_a[26],
	wr_data_a[25],wr_data_a[24],wr_data_a[25],wr_data_a[24],
	wr_data_a[23],wr_data_a[22],wr_data_a[23],wr_data_a[22],
	wr_data_a[21],wr_data_a[20],wr_data_a[21],wr_data_a[20],
	wr_data_a[19],wr_data_a[18],wr_data_a[19],wr_data_a[18],
	wr_data_a[17],wr_data_a[16],wr_data_a[17],wr_data_a[16],
	wr_data_a[15],wr_data_a[14],wr_data_a[15],wr_data_a[14],
	wr_data_a[13],wr_data_a[12],wr_data_a[13],wr_data_a[12],
	wr_data_a[11],wr_data_a[10],wr_data_a[11],wr_data_a[10],
	wr_data_a[9],wr_data_a[8],wr_data_a[9],wr_data_a[8],
	wr_data_a[7],wr_data_a[6],wr_data_a[7],wr_data_a[6],
	wr_data_a[5],wr_data_a[4],wr_data_a[5],wr_data_a[4],
	wr_data_a[3],wr_data_a[2],wr_data_a[3],wr_data_a[2],
	wr_data_a[1],wr_data_a[0],wr_data_a[1],wr_data_a[0]};

////////////////////////////////
// Encode mask for byte enables
////////////////////////////////
assign byte_mask[143:0] = {
	{9{byte_wr_en_b[7],byte_wr_en_b[6],byte_wr_en_b[7],byte_wr_en_b[6],
 	   byte_wr_en_b[5],byte_wr_en_b[4],byte_wr_en_b[5],byte_wr_en_b[4]}},
	{9{byte_wr_en_b[3],byte_wr_en_b[2],byte_wr_en_b[3],byte_wr_en_b[2],
	   byte_wr_en_b[1],byte_wr_en_b[0],byte_wr_en_b[1],byte_wr_en_b[0]}}};

////////////////////////////////
// Encode mask for way enables
////////////////////////////////
assign w0_wcs = wr_waysel_b[0] & wr_en_b & ~wr_inh_b & ~rd_en_b ;   // way0 write 
assign w1_wcs = wr_waysel_b[1] & wr_en_b & ~wr_inh_b & ~rd_en_b ;   // way1 write

assign way_mask[143:0] = { {36{ {2{w1_wcs}},{2{w0_wcs}} }} };


assign din[143:0] = ( (byte_mask[143:0] & way_mask[143:0]) & data_in[143:0]) |
                    (~(byte_mask[143:0] & way_mask[143:0]) & local_dout[143:0]);

//////////////////////////
// Redundancy write shifter
//////////////////////////

assign wr_data[  3:  0] = din[  3:  0];
assign wr_data[  7:  4] = (red_shift_en && (red_data >= 6'd0 )) ? din[  7:  4] : din[  3:  0];
assign wr_data[ 11:  8] = (red_shift_en && (red_data >= 6'd1 )) ? din[ 11:  8] : din[  7:  4];
assign wr_data[ 15: 12] = (red_shift_en && (red_data >= 6'd2 )) ? din[ 15: 12] : din[ 11:  8];
assign wr_data[ 19: 16] = (red_shift_en && (red_data >= 6'd3 )) ? din[ 19: 16] : din[ 15: 12];
assign wr_data[ 23: 20] = (red_shift_en && (red_data >= 6'd4 )) ? din[ 23: 20] : din[ 19: 16];
assign wr_data[ 27: 24] = (red_shift_en && (red_data >= 6'd5 )) ? din[ 27: 24] : din[ 23: 20];
assign wr_data[ 31: 28] = (red_shift_en && (red_data >= 6'd6 )) ? din[ 31: 28] : din[ 27: 24];
assign wr_data[ 35: 32] = (red_shift_en && (red_data >= 6'd7 )) ? din[ 35: 32] : din[ 31: 28];
assign wr_data[ 39: 36] = (red_shift_en && (red_data >= 6'd8 )) ? din[ 39: 36] : din[ 35: 32];
assign wr_data[ 43: 40] = (red_shift_en && (red_data >= 6'd9 )) ? din[ 43: 40] : din[ 39: 36];
assign wr_data[ 47: 44] = (red_shift_en && (red_data >= 6'd10)) ? din[ 47: 44] : din[ 43: 40];
assign wr_data[ 51: 48] = (red_shift_en && (red_data >= 6'd11)) ? din[ 51: 48] : din[ 47: 44];
assign wr_data[ 55: 52] = (red_shift_en && (red_data >= 6'd12)) ? din[ 55: 52] : din[ 51: 48];
assign wr_data[ 59: 56] = (red_shift_en && (red_data >= 6'd13)) ? din[ 59: 56] : din[ 55: 52];
assign wr_data[ 63: 60] = (red_shift_en && (red_data >= 6'd14)) ? din[ 63: 60] : din[ 59: 56];
assign wr_data[ 67: 64] = (red_shift_en && (red_data >= 6'd15)) ? din[ 67: 64] : din[ 63: 60];
assign wr_data[ 71: 68] = (red_shift_en && (red_data >= 6'd16)) ? din[ 71: 68] : din[ 67: 64];
assign wr_data[ 75: 72] = (red_shift_en && (red_data >= 6'd17)) ? din[ 75: 72] : din[ 71: 68];
assign wr_data[ 79: 76] = (red_shift_en && (red_data >= 6'd18)) ? din[ 79: 76] : din[ 75: 72];
assign wr_data[ 83: 80] = (red_shift_en && (red_data >= 6'd19)) ? din[ 83: 80] : din[ 79: 76];
assign wr_data[ 87: 84] = (red_shift_en && (red_data >= 6'd20)) ? din[ 87: 84] : din[ 83: 80];
assign wr_data[ 91: 88] = (red_shift_en && (red_data >= 6'd21)) ? din[ 91: 88] : din[ 87: 84];
assign wr_data[ 95: 92] = (red_shift_en && (red_data >= 6'd22)) ? din[ 95: 92] : din[ 91: 88];
assign wr_data[ 99: 96] = (red_shift_en && (red_data >= 6'd23)) ? din[ 99: 96] : din[ 95: 92];
assign wr_data[103:100] = (red_shift_en && (red_data >= 6'd24)) ? din[103:100] : din[ 99: 96];
assign wr_data[107:104] = (red_shift_en && (red_data >= 6'd25)) ? din[107:104] : din[103:100];
assign wr_data[111:108] = (red_shift_en && (red_data >= 6'd26)) ? din[111:108] : din[107:104];
assign wr_data[115:112] = (red_shift_en && (red_data >= 6'd27)) ? din[115:112] : din[111:108];
assign wr_data[119:116] = (red_shift_en && (red_data >= 6'd28)) ? din[119:116] : din[115:112];
assign wr_data[123:120] = (red_shift_en && (red_data >= 6'd29)) ? din[123:120] : din[119:116];
assign wr_data[127:124] = (red_shift_en && (red_data >= 6'd30)) ? din[127:124] : din[123:120];
assign wr_data[131:128] = (red_shift_en && (red_data >= 6'd31)) ? din[131:128] : din[127:124];
assign wr_data[135:132] = (red_shift_en && (red_data >= 6'd32)) ? din[135:132] : din[131:128];
assign wr_data[139:136] = (red_shift_en && (red_data >= 6'd33)) ? din[139:136] : din[135:132];
assign wr_data[143:140] = (red_shift_en && (red_data >= 6'd34)) ? din[143:140] : din[139:136];
assign wr_data[147:144] = (red_shift_en && (red_data >= 6'd35)) ? 4'bx         : din[143:140];

//////////////////////
// Write array       
//////////////////////
assign rcs_l = rd_en_b & ~wr_en_b;              // read for both way0 & way1

always @ (negedge l1clk_wr) begin
    if ((w0_wcs | w1_wcs) & ~rcs_l & vnw_ary) begin
        mem[addr_b[10:4]] <= wr_data;


    end
end

assign temp[147:0] = mem[addr_b[10:4]];

//////////////////////////
// Redundancy read shifter
//////////////////////////

assign local_dout[  3:  0] = (red_shift_en && (red_data >= 6'd0 )) ? temp[  3:  0] : temp[  7:  4];
assign local_dout[  7:  4] = (red_shift_en && (red_data >= 6'd1 )) ? temp[  7:  4] : temp[ 11:  8];
assign local_dout[ 11:  8] = (red_shift_en && (red_data >= 6'd2 )) ? temp[ 11:  8] : temp[ 15: 12];
assign local_dout[ 15: 12] = (red_shift_en && (red_data >= 6'd3 )) ? temp[ 15: 12] : temp[ 19: 16];
assign local_dout[ 19: 16] = (red_shift_en && (red_data >= 6'd4 )) ? temp[ 19: 16] : temp[ 23: 20];
assign local_dout[ 23: 20] = (red_shift_en && (red_data >= 6'd5 )) ? temp[ 23: 20] : temp[ 27: 24];
assign local_dout[ 27: 24] = (red_shift_en && (red_data >= 6'd6 )) ? temp[ 27: 24] : temp[ 31: 28];
assign local_dout[ 31: 28] = (red_shift_en && (red_data >= 6'd7 )) ? temp[ 31: 28] : temp[ 35: 32];
assign local_dout[ 35: 32] = (red_shift_en && (red_data >= 6'd8 )) ? temp[ 35: 32] : temp[ 39: 36];
assign local_dout[ 39: 36] = (red_shift_en && (red_data >= 6'd9 )) ? temp[ 39: 36] : temp[ 43: 40];
assign local_dout[ 43: 40] = (red_shift_en && (red_data >= 6'd10)) ? temp[ 43: 40] : temp[ 47: 44];
assign local_dout[ 47: 44] = (red_shift_en && (red_data >= 6'd11)) ? temp[ 47: 44] : temp[ 51: 48];
assign local_dout[ 51: 48] = (red_shift_en && (red_data >= 6'd12)) ? temp[ 51: 48] : temp[ 55: 52];
assign local_dout[ 55: 52] = (red_shift_en && (red_data >= 6'd13)) ? temp[ 55: 52] : temp[ 59: 56];
assign local_dout[ 59: 56] = (red_shift_en && (red_data >= 6'd14)) ? temp[ 59: 56] : temp[ 63: 60];
assign local_dout[ 63: 60] = (red_shift_en && (red_data >= 6'd15)) ? temp[ 63: 60] : temp[ 67: 64];
assign local_dout[ 67: 64] = (red_shift_en && (red_data >= 6'd16)) ? temp[ 67: 64] : temp[ 71: 68];
assign local_dout[ 71: 68] = (red_shift_en && (red_data >= 6'd17)) ? temp[ 71: 68] : temp[ 75: 72];
assign local_dout[ 75: 72] = (red_shift_en && (red_data >= 6'd18)) ? temp[ 75: 72] : temp[ 79: 76];
assign local_dout[ 79: 76] = (red_shift_en && (red_data >= 6'd19)) ? temp[ 79: 76] : temp[ 83: 80];
assign local_dout[ 83: 80] = (red_shift_en && (red_data >= 6'd20)) ? temp[ 83: 80] : temp[ 87: 84];
assign local_dout[ 87: 84] = (red_shift_en && (red_data >= 6'd21)) ? temp[ 87: 84] : temp[ 91: 88];
assign local_dout[ 91: 88] = (red_shift_en && (red_data >= 6'd22)) ? temp[ 91: 88] : temp[ 95: 92];
assign local_dout[ 95: 92] = (red_shift_en && (red_data >= 6'd23)) ? temp[ 95: 92] : temp[ 99: 96];
assign local_dout[ 99: 96] = (red_shift_en && (red_data >= 6'd24)) ? temp[ 99: 96] : temp[103:100];
assign local_dout[103:100] = (red_shift_en && (red_data >= 6'd25)) ? temp[103:100] : temp[107:104];
assign local_dout[107:104] = (red_shift_en && (red_data >= 6'd26)) ? temp[107:104] : temp[111:108];
assign local_dout[111:108] = (red_shift_en && (red_data >= 6'd27)) ? temp[111:108] : temp[115:112];
assign local_dout[115:112] = (red_shift_en && (red_data >= 6'd28)) ? temp[115:112] : temp[119:116];
assign local_dout[119:116] = (red_shift_en && (red_data >= 6'd29)) ? temp[119:116] : temp[123:120];
assign local_dout[123:120] = (red_shift_en && (red_data >= 6'd30)) ? temp[123:120] : temp[127:124];
assign local_dout[127:124] = (red_shift_en && (red_data >= 6'd31)) ? temp[127:124] : temp[131:128];
assign local_dout[131:128] = (red_shift_en && (red_data >= 6'd32)) ? temp[131:128] : temp[135:132];
assign local_dout[135:132] = (red_shift_en && (red_data >= 6'd33)) ? temp[135:132] : temp[139:136];
assign local_dout[139:136] = (red_shift_en && (red_data >= 6'd34)) ? temp[139:136] : temp[143:140];
assign local_dout[143:140] = (red_shift_en && (red_data >= 6'd35)) ? temp[143:140] : temp[147:144];

//////////////////////
// Read array
//////////////////////
always @(posedge l1clk) begin
    if (rcs_l & vnw_ary) begin
        if (w0_wcs | w1_wcs | wr_inh_b)
            dout[143:0] <= 144'hx;
        else
            dout[143:0] <= local_dout[143:0];
    end
end

// Precharge
always @(negedge l1clk) begin
            dout[143:0] <= 144'h0;
end

//////////////////////////
// rd_data column mux 
//////////////////////////
assign w0_dout[35:0] = addr_b[3] ? 
{	dout[140], dout[136], dout[132], dout[128], dout[124], dout[120],
	dout[116], dout[112], dout[108], dout[104], dout[100], dout[96],
	dout[92], dout[88], dout[84], dout[80], dout[76], dout[72],
	dout[68], dout[64], dout[60], dout[56], dout[52], dout[48],
	dout[44], dout[40], dout[36], dout[32], dout[28], dout[24],
	dout[20], dout[16], dout[12], dout[8], dout[4], dout[0]} :
{	dout[141], dout[137], dout[133], dout[129], dout[125], dout[121],
	dout[117], dout[113], dout[109], dout[105], dout[101], dout[97],
	dout[93], dout[89], dout[85], dout[81], dout[77], dout[73],
	dout[69], dout[65], dout[61], dout[57], dout[53], dout[49],
	dout[45], dout[41], dout[37], dout[33], dout[29], dout[25],
	dout[21], dout[17], dout[13], dout[9], dout[5], dout[1]} ;

assign w1_dout[35:0] = addr_b[3] ? 
{	dout[142], dout[138], dout[134], dout[130], dout[126], dout[122],
	dout[118], dout[114], dout[110], dout[106], dout[102], dout[98],
	dout[94], dout[90], dout[86], dout[82], dout[78], dout[74],
	dout[70], dout[66], dout[62], dout[58], dout[54], dout[50],
	dout[46], dout[42], dout[38], dout[34], dout[30], dout[26],
	dout[22], dout[18], dout[14], dout[10], dout[6], dout[2]} :
{	dout[143], dout[139], dout[135], dout[131], dout[127], dout[123],
	dout[119], dout[115], dout[111], dout[107], dout[103], dout[99],
	dout[95], dout[91], dout[87], dout[83], dout[79], dout[75],
	dout[71], dout[67], dout[63], dout[59], dout[55], dout[51],
	dout[47], dout[43], dout[39], dout[35], dout[31], dout[27],
	dout[23], dout[19], dout[15], dout[11], dout[7], dout[3]} ;

// Need dual-rail at the outputs
always @(negedge l1clk or posedge wr_inh_b) begin
    if (wr_inh_b) begin
	w0_sao_h[35:0] <= 36'hx;
	w0_sao_l[35:0] <= 36'hx;
	w1_sao_h[35:0] <= 36'hx;
	w1_sao_l[35:0] <= 36'hx;
    end
    else begin
	w0_sao_h[35:0] <=  w0_dout[35:0] & {36{(rd_en_a & ~wr_en_a)}};
	w0_sao_l[35:0] <= ~w0_dout[35:0] & {36{(rd_en_a & ~wr_en_a)}};
	w1_sao_h[35:0] <=  w1_dout[35:0] & {36{(rd_en_a & ~wr_en_a)}};
	w1_sao_l[35:0] <= ~w1_dout[35:0] & {36{(rd_en_a & ~wr_en_a)}};
    end
end
always @(posedge l1clk or negedge rd_en_a) begin
	w0_sao_h[35:0] <= 36'h0;
	w0_sao_l[35:0] <= 36'h0;
	w1_sao_h[35:0] <= 36'h0;
	w1_sao_l[35:0] <= 36'h0;
end

//////////////////////////
// rd_data out mapping 
//////////////////////////
assign w0_rdata_h[35:0] = w0_sao_h[35:0] ;
assign w0_rdata_l[35:0] = w0_sao_l[35:0] ;
assign w1_rdata_h[35:0] = w1_sao_h[35:0] ;
assign w1_rdata_l[35:0] = w1_sao_l[35:0] ;


supply0 vss;
supply1 vdd;

// synopsys translate_on

endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_64 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [63:0] din0;
  input [63:0] din1;
  input sel0;
  output [63:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(64)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
.dout(dout[63:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;

  input [7:0] din;
  input l1clk;
  input [7:0] scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output [7:0] scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si(scan_in[7:0]),
.so(scan_out[7:0]),
.q(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_64 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [63:0] fdin;

  input [63:0] din;
  input l1clk;
  input [63:0] scan_in;


  input siclk;
  input soclk;

  output [63:0] dout;
  output [63:0] scan_out;
assign fdin[63:0] = din[63:0];


dff #(64)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[63:0]),
.si(scan_in[63:0]),
.so(scan_out[63:0]),
.q(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_mux_macro__mux_aope__ports_2__width_4 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [3:0] din0;
  input [3:0] din1;
  input sel0;
  output [3:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(4)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[3:0]),
  .in1(din1[3:0]),
.dout(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_4__width_64 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [63:0] din0;
  input sel0;
  input [63:0] din1;
  input sel1;
  input [63:0] din2;
  input sel2;
  input [63:0] din3;
  input sel3;
  output [63:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(64)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[63:0]),
  .in1(din1[63:0]),
  .in2(din2[63:0]),
  .in3(din3[63:0]),
.dout(dout[63:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_4__width_8 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;

  input [7:0] din0;
  input sel0;
  input [7:0] din1;
  input sel1;
  input [7:0] din2;
  input sel2;
  input [7:0] din3;
  input sel3;
  output [7:0] dout;


cl_dp1_muxbuff4_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3)
);
mux4s #(8)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
.dout(dout[7:0])
);


endmodule


//
//   xor macro for ports = 2,3
//
//


module n2_dca_sp_9kb_cust_xor_macro__ports_3__width_4 (
  din0, 
  din1, 
  din2, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  input [3:0] din2;
  output [3:0] dout;


xor3 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.in2(din2[3:0]),
.out(dout[3:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_mux_macro__mux_aonpe__ports_8__width_1 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [0:0] din0;
  input sel0;
  input [0:0] din1;
  input sel1;
  input [0:0] din2;
  input sel2;
  input [0:0] din3;
  input sel3;
  input [0:0] din4;
  input sel4;
  input [0:0] din5;
  input sel5;
  input [0:0] din6;
  input sel6;
  input [0:0] din7;
  input sel7;
  output [0:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(1)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[0:0]),
  .in1(din1[0:0]),
  .in2(din2[0:0]),
  .in3(din3[0:0]),
  .in4(din4[0:0]),
  .in5(din5[0:0]),
  .in6(din6[0:0]),
  .in7(din7[0:0]),
.dout(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_dca_sp_9kb_cust_msff_ctl_macro__fs_1__width_12 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [11:0] fdin;

  input [11:0] din;
  input l1clk;
  input [11:0] scan_in;


  input siclk;
  input soclk;

  output [11:0] dout;
  output [11:0] scan_out;
assign fdin[11:0] = din[11:0];


dff #(12)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[11:0]),
.si(scan_in[11:0]),
.so(scan_out[11:0]),
.q(dout[11:0])
);


endmodule

`endif // `ifndef FPGA

`ifdef FPGA
/* Source file "n2_dca_sp_9kb_cust_vj.v", line 1 */
// No timescale specified
module n2_dca_sp_9kb_cust(dcache_rd_addr_e, dcache_alt_addr_e, 
	dcache_alt_addr_sel_e, dcache_rvld_e, dcache_wvld_e, dcache_clk_en_e, 
	dcache_wclk_en_e, dcache_rclk_en_m, dcache_wdata_e, dcache_wr_way_e, 
	dcache_byte_wr_en_e, dcache_alt_rsel_way_m, dcache_rsel_way_b, 
	dcache_alt_way_sel_m, lsu_l2fill_or_byp_data_m, dcache_bypass_e_, 
	dcache_rdata_b, dcache_rparity_b, dcache_perr_w0_b, dcache_perr_w1_b, 
	dcache_perr_w2_b, dcache_perr_w3_b, dcache_rdata_msb_w0_b, 
	dcache_rdata_msb_w1_b, dcache_rdata_msb_w2_b, dcache_rdata_msb_w3_b, 
	l2clk, scan_in, tcu_pce_ov, tcu_aclk, tcu_bclk, tcu_array_wr_inhibit, 
	tcu_scan_en, tcu_se_scancollar_in, tcu_se_scancollar_out, scan_out, 
	fuse_dca_repair_value, fuse_dca_repair_en, fuse_dca_rid, fuse_dca_wen, 
	fuse_red_reset, dca_fuse_repair_value, dca_fuse_repair_en, vnw_ary);

	input	[10:3]		dcache_rd_addr_e;
	input	[10:3]		dcache_alt_addr_e;
	input			dcache_alt_addr_sel_e;
	input			dcache_rvld_e;
	input			dcache_wvld_e;
	input			dcache_clk_en_e;
	input			dcache_wclk_en_e;
	input			dcache_rclk_en_m;
	input	[143:0]		dcache_wdata_e;
	input	[1:0]		dcache_wr_way_e;
	input	[15:0]		dcache_byte_wr_en_e;
	input	[3:0]		dcache_alt_rsel_way_m;
	input	[3:0]		dcache_rsel_way_b;
	input			dcache_alt_way_sel_m;
	input	[63:0]		lsu_l2fill_or_byp_data_m;
	input			dcache_bypass_e_;
	output	[63:0]		dcache_rdata_b;
	output	[7:0]		dcache_rparity_b;
	output			dcache_perr_w0_b;
	output			dcache_perr_w1_b;
	output			dcache_perr_w2_b;
	output			dcache_perr_w3_b;
	output	[7:0]		dcache_rdata_msb_w0_b;
	output	[7:0]		dcache_rdata_msb_w1_b;
	output	[7:0]		dcache_rdata_msb_w2_b;
	output	[7:0]		dcache_rdata_msb_w3_b;
	input			l2clk;
	input			scan_in;
	input			tcu_pce_ov;
	input			tcu_aclk;
	input			tcu_bclk;
	input			tcu_array_wr_inhibit;
	input			tcu_scan_en;
	input			tcu_se_scancollar_in;
	input			tcu_se_scancollar_out;
	output			scan_out;
	input	[5:0]		fuse_dca_repair_value;
	input	[1:0]		fuse_dca_repair_en;
	input	[1:0]		fuse_dca_rid;
	input			fuse_dca_wen;
	input			fuse_red_reset;
	output	[5:0]		dca_fuse_repair_value;
	output	[1:0]		dca_fuse_repair_en;
	input			vnw_ary;

	wire			l1clk_in;
	wire			l1clk_in_pm;
	wire			l1clk_out_pm;
	wire			l1clk_out;
	wire			l1clk_free;
	wire			l1clk_free_wpm;
	wire			l1clk_red;
	wire	[10:3]		dcache_rwaddr_e;
	wire	[7:0]		lat_addr_scanin;
	wire	[7:0]		lat_addr_scanout;
	wire	[10:3]		dcache_rwaddr_eb;
	wire	[10:3]		dcache_rwaddr_l_unused;
	wire	[3:0]		wr_way_dec_e;
	wire	[6:0]		lat_ctl_eb_scanin;
	wire	[6:0]		lat_ctl_eb_scanout;
	wire			dcache_rvld_top_eb;
	wire			dcache_rvld_bot_eb;
	wire			dcache_wvld_eb;
	wire	[3:0]		wr_way_dec_eb;
	wire	[6:0]		lat_ctl_unused;
	wire	[2:0]		dff_ctl_m_0_scanin;
	wire	[2:0]		dff_ctl_m_0_scanout;
	wire			dcache_rvld_m;
	wire			dcache_wvld_m;
	wire			dcache_bypass_m_;
	wire	[15:0]		dff_ctl_m_1_scanin;
	wire	[15:0]		dff_ctl_m_1_scanout;
	wire	[15:0]		byte_wr_en_eb;
	wire	[15:0]		dff_ctl_l_unused;
	wire	[4:0]		dff_ctl_b_scanin;
	wire	[4:0]		dff_ctl_b_scanout;
	wire			dcache_alt_way_sel_b;
	wire	[3:0]		dcache_alt_rsel_way_b;
	wire	[143:0]		dff_wdata_m_scanin;
	wire	[143:0]		dff_wdata_m_scanout;
	wire	[15:0]		dcache_wparity_m;
	wire	[127:0]		dcache_wdata_m;
	wire	[5:0]		fuse_dca_repair_value_ff;
	wire	[1:0]		fuse_dca_repair_en_ff;
	wire	[1:0]		fuse_dca_rid_ff;
	wire			fuse_dca_wen_ff;
	wire			fuse_red_reset_ff;
	wire	[5:0]		dca_fuse_repair_value_pre;
	wire	[1:0]		dca_fuse_repair_en_pre;
	wire	[63:0]		dcache_rdata_w0_m;
	wire	[63:0]		rdata_w0_m;
	wire	[63:0]		rdata_w1_m;
	wire	[63:0]		dcache_rdata_w1_m;
	wire	[63:0]		rdata_w2_m;
	wire	[63:0]		dcache_rdata_w2_m;
	wire	[63:0]		rdata_w3_m;
	wire	[63:0]		dcache_rdata_w3_m;
	wire	[7:0]		dff_msb_w0_scanin;
	wire	[7:0]		dff_msb_w0_scanout;
	wire	[7:0]		dff_msb_w1_scanin;
	wire	[7:0]		dff_msb_w1_scanout;
	wire	[7:0]		dff_msb_w2_scanin;
	wire	[7:0]		dff_msb_w2_scanout;
	wire	[7:0]		dff_msb_w3_scanin;
	wire	[7:0]		dff_msb_w3_scanout;
	wire	[63:0]		dff_rdata_w0_m_scanin;
	wire	[63:0]		dff_rdata_w0_m_scanout;
	wire	[63:0]		rdata_w0_b;
	wire	[7:0]		dff_rparity_w0_m_scanin;
	wire	[7:0]		dff_rparity_w0_m_scanout;
	wire	[7:0]		rparity_w0_m;
	wire	[7:0]		rparity_w0_b;
	wire	[63:0]		dff_rdata_w1_m_scanin;
	wire	[63:0]		dff_rdata_w1_m_scanout;
	wire	[63:0]		rdata_w1_b;
	wire	[7:0]		dff_rparity_w1_m_scanin;
	wire	[7:0]		dff_rparity_w1_m_scanout;
	wire	[7:0]		rparity_w1_m;
	wire	[7:0]		rparity_w1_b;
	wire	[63:0]		dff_rdata_w2_m_scanin;
	wire	[63:0]		dff_rdata_w2_m_scanout;
	wire	[63:0]		rdata_w2_b;
	wire	[7:0]		dff_rparity_w2_m_scanin;
	wire	[7:0]		dff_rparity_w2_m_scanout;
	wire	[7:0]		rparity_w2_m;
	wire	[7:0]		rparity_w2_b;
	wire	[63:0]		dff_rdata_w3_m_scanin;
	wire	[63:0]		dff_rdata_w3_m_scanout;
	wire	[63:0]		rdata_w3_b;
	wire	[7:0]		dff_rparity_w3_m_scanin;
	wire	[7:0]		dff_rparity_w3_m_scanout;
	wire	[7:0]		rparity_w3_m;
	wire	[7:0]		rparity_w3_b;
	wire	[3:0]		dcache_rd_sel_way_b;
	wire			w0_p0_0;
	wire			w0_p0_1;
	wire			w0_p0_2;
	wire	[7:0]		w0_parity_m;
	wire			w0_p1_0;
	wire			w0_p1_1;
	wire			w0_p1_2;
	wire			w0_p2_0;
	wire			w0_p2_1;
	wire			w0_p2_2;
	wire			w0_p3_0;
	wire			w0_p3_1;
	wire			w0_p3_2;
	wire			w0_p4_0;
	wire			w0_p4_1;
	wire			w0_p4_2;
	wire			w0_p5_0;
	wire			w0_p5_1;
	wire			w0_p5_2;
	wire			w0_p6_0;
	wire			w0_p6_1;
	wire			w0_p6_2;
	wire			w0_p7_0;
	wire			w0_p7_1;
	wire			w0_p7_2;
	wire			w1_p0_0;
	wire			w1_p0_1;
	wire			w1_p0_2;
	wire	[7:0]		w1_parity_m;
	wire			w1_p1_0;
	wire			w1_p1_1;
	wire			w1_p1_2;
	wire			w1_p2_0;
	wire			w1_p2_1;
	wire			w1_p2_2;
	wire			w1_p3_0;
	wire			w1_p3_1;
	wire			w1_p3_2;
	wire			w1_p4_0;
	wire			w1_p4_1;
	wire			w1_p4_2;
	wire			w1_p5_0;
	wire			w1_p5_1;
	wire			w1_p5_2;
	wire			w1_p6_0;
	wire			w1_p6_1;
	wire			w1_p6_2;
	wire			w1_p7_0;
	wire			w1_p7_1;
	wire			w1_p7_2;
	wire			w2_p0_0;
	wire			w2_p0_1;
	wire			w2_p0_2;
	wire	[7:0]		w2_parity_m;
	wire			w2_p1_0;
	wire			w2_p1_1;
	wire			w2_p1_2;
	wire			w2_p2_0;
	wire			w2_p2_1;
	wire			w2_p2_2;
	wire			w2_p3_0;
	wire			w2_p3_1;
	wire			w2_p3_2;
	wire			w2_p4_0;
	wire			w2_p4_1;
	wire			w2_p4_2;
	wire			w2_p5_0;
	wire			w2_p5_1;
	wire			w2_p5_2;
	wire			w2_p6_0;
	wire			w2_p6_1;
	wire			w2_p6_2;
	wire			w2_p7_0;
	wire			w2_p7_1;
	wire			w2_p7_2;
	wire			w3_p0_0;
	wire			w3_p0_1;
	wire			w3_p0_2;
	wire	[7:0]		w3_parity_m;
	wire			w3_p1_0;
	wire			w3_p1_1;
	wire			w3_p1_2;
	wire			w3_p2_0;
	wire			w3_p2_1;
	wire			w3_p2_2;
	wire			w3_p3_0;
	wire			w3_p3_1;
	wire			w3_p3_2;
	wire			w3_p4_0;
	wire			w3_p4_1;
	wire			w3_p4_2;
	wire			w3_p5_0;
	wire			w3_p5_1;
	wire			w3_p5_2;
	wire			w3_p6_0;
	wire			w3_p6_1;
	wire			w3_p6_2;
	wire			w3_p7_0;
	wire			w3_p7_1;
	wire			w3_p7_2;
	wire	[7:0]		dff_byte_perr_w0_scanin;
	wire	[7:0]		dff_byte_perr_w0_scanout;
	wire	[7:0]		w0_parity_b;
	wire	[7:0]		dff_byte_perr_w1_scanin;
	wire	[7:0]		dff_byte_perr_w1_scanout;
	wire	[7:0]		w1_parity_b;
	wire	[7:0]		dff_byte_perr_w2_scanin;
	wire	[7:0]		dff_byte_perr_w2_scanout;
	wire	[7:0]		w2_parity_b;
	wire	[7:0]		dff_byte_perr_w3_scanin;
	wire	[7:0]		dff_byte_perr_w3_scanout;
	wire	[7:0]		w3_parity_b;
	wire			w0_parity_err_b;
	wire			w1_parity_err_b;
	wire			w2_parity_err_b;
	wire			w3_parity_err_b;
	wire	[11:0]		dff_red_in_scanin;
	wire	[11:0]		dff_red_in_scanout;
	wire	[7:0]		dff_red_out_scanin;
	wire	[7:0]		dff_red_out_scanout;
	wire			pce_ov = tcu_pce_ov;
	wire			stop = 1'b0;
	wire			siclk = tcu_aclk;
	wire			soclk = tcu_bclk;
	supply0			vss;
	supply1			vdd;

	assign rdata_w1_m[63:0] = dcache_rdata_w1_m[63:0];
	assign rdata_w2_m[63:0] = dcache_rdata_w2_m[63:0];
	assign rdata_w3_m[63:0] = dcache_rdata_w3_m[63:0];
	assign dcache_perr_w0_b = w0_parity_err_b;
	assign dcache_perr_w1_b = w1_parity_err_b;
	assign dcache_perr_w2_b = w2_parity_err_b;
	assign dcache_perr_w3_b = w3_parity_err_b;
	assign dff_byte_perr_w0_scanin[7] = scan_in;
	assign dff_byte_perr_w1_scanin[7] = dff_byte_perr_w0_scanout[7];
	assign dff_byte_perr_w1_scanin[6] = dff_byte_perr_w1_scanout[7];
	assign dff_byte_perr_w0_scanin[6] = dff_byte_perr_w1_scanout[6];
	assign dff_byte_perr_w0_scanin[5] = dff_byte_perr_w0_scanout[6];
	assign dff_byte_perr_w1_scanin[5] = dff_byte_perr_w0_scanout[5];
	assign dff_byte_perr_w1_scanin[4] = dff_byte_perr_w1_scanout[5];
	assign dff_byte_perr_w0_scanin[4] = dff_byte_perr_w1_scanout[4];
	assign dff_wdata_m_scanin[143] = dff_byte_perr_w0_scanout[4];
	assign dff_wdata_m_scanin[71] = dff_wdata_m_scanout[143];
	assign dff_rparity_w3_m_scanin[7] = dff_wdata_m_scanout[71];
	assign dff_rparity_w2_m_scanin[7] = dff_rparity_w3_m_scanout[7];
	assign dff_rparity_w1_m_scanin[7] = dff_rparity_w2_m_scanout[7];
	assign dff_rparity_w0_m_scanin[7] = dff_rparity_w1_m_scanout[7];
	assign dff_wdata_m_scanin[134] = dff_rparity_w0_m_scanout[7];
	assign dff_wdata_m_scanin[62] = dff_wdata_m_scanout[134];
	assign dff_rparity_w3_m_scanin[6] = dff_wdata_m_scanout[62];
	assign dff_rparity_w2_m_scanin[6] = dff_rparity_w3_m_scanout[6];
	assign dff_rparity_w1_m_scanin[6] = dff_rparity_w2_m_scanout[6];
	assign dff_rparity_w0_m_scanin[6] = dff_rparity_w1_m_scanout[6];
	assign dff_wdata_m_scanin[142] = dff_rparity_w0_m_scanout[6];
	assign dff_wdata_m_scanin[70] = dff_wdata_m_scanout[142];
	assign dff_rdata_w3_m_scanin[63] = dff_wdata_m_scanout[70];
	assign dff_rdata_w2_m_scanin[63] = dff_rdata_w3_m_scanout[63];
	assign dff_rdata_w1_m_scanin[63] = dff_rdata_w2_m_scanout[63];
	assign dff_rdata_w0_m_scanin[63] = dff_rdata_w1_m_scanout[63];
	assign dff_wdata_m_scanin[133] = dff_rdata_w0_m_scanout[63];
	assign dff_wdata_m_scanin[61] = dff_wdata_m_scanout[133];
	assign dff_rdata_w3_m_scanin[55] = dff_wdata_m_scanout[61];
	assign dff_rdata_w2_m_scanin[55] = dff_rdata_w3_m_scanout[55];
	assign dff_rdata_w1_m_scanin[55] = dff_rdata_w2_m_scanout[55];
	assign dff_rdata_w0_m_scanin[55] = dff_rdata_w1_m_scanout[55];
	assign dff_wdata_m_scanin[141] = dff_rdata_w0_m_scanout[55];
	assign dff_wdata_m_scanin[69] = dff_wdata_m_scanout[141];
	assign dff_rdata_w3_m_scanin[62] = dff_wdata_m_scanout[69];
	assign dff_rdata_w2_m_scanin[62] = dff_rdata_w3_m_scanout[62];
	assign dff_rdata_w1_m_scanin[62] = dff_rdata_w2_m_scanout[62];
	assign dff_rdata_w0_m_scanin[62] = dff_rdata_w1_m_scanout[62];
	assign dff_wdata_m_scanin[132] = dff_rdata_w0_m_scanout[62];
	assign dff_wdata_m_scanin[60] = dff_wdata_m_scanout[132];
	assign dff_rdata_w3_m_scanin[54] = dff_wdata_m_scanout[60];
	assign dff_rdata_w2_m_scanin[54] = dff_rdata_w3_m_scanout[54];
	assign dff_rdata_w1_m_scanin[54] = dff_rdata_w2_m_scanout[54];
	assign dff_rdata_w0_m_scanin[54] = dff_rdata_w1_m_scanout[54];
	assign dff_wdata_m_scanin[140] = dff_rdata_w0_m_scanout[54];
	assign dff_wdata_m_scanin[68] = dff_wdata_m_scanout[140];
	assign dff_rdata_w3_m_scanin[61] = dff_wdata_m_scanout[68];
	assign dff_rdata_w2_m_scanin[61] = dff_rdata_w3_m_scanout[61];
	assign dff_rdata_w1_m_scanin[61] = dff_rdata_w2_m_scanout[61];
	assign dff_rdata_w0_m_scanin[61] = dff_rdata_w1_m_scanout[61];
	assign dff_wdata_m_scanin[131] = dff_rdata_w0_m_scanout[61];
	assign dff_wdata_m_scanin[59] = dff_wdata_m_scanout[131];
	assign dff_rdata_w3_m_scanin[53] = dff_wdata_m_scanout[59];
	assign dff_rdata_w2_m_scanin[53] = dff_rdata_w3_m_scanout[53];
	assign dff_rdata_w1_m_scanin[53] = dff_rdata_w2_m_scanout[53];
	assign dff_rdata_w0_m_scanin[53] = dff_rdata_w1_m_scanout[53];
	assign dff_wdata_m_scanin[139] = dff_rdata_w0_m_scanout[53];
	assign dff_wdata_m_scanin[67] = dff_wdata_m_scanout[139];
	assign dff_rdata_w3_m_scanin[60] = dff_wdata_m_scanout[67];
	assign dff_rdata_w2_m_scanin[60] = dff_rdata_w3_m_scanout[60];
	assign dff_rdata_w1_m_scanin[60] = dff_rdata_w2_m_scanout[60];
	assign dff_rdata_w0_m_scanin[60] = dff_rdata_w1_m_scanout[60];
	assign dff_wdata_m_scanin[130] = dff_rdata_w0_m_scanout[60];
	assign dff_wdata_m_scanin[58] = dff_wdata_m_scanout[130];
	assign dff_rdata_w3_m_scanin[52] = dff_wdata_m_scanout[58];
	assign dff_rdata_w2_m_scanin[52] = dff_rdata_w3_m_scanout[52];
	assign dff_rdata_w1_m_scanin[52] = dff_rdata_w2_m_scanout[52];
	assign dff_rdata_w0_m_scanin[52] = dff_rdata_w1_m_scanout[52];
	assign dff_wdata_m_scanin[138] = dff_rdata_w0_m_scanout[52];
	assign dff_wdata_m_scanin[66] = dff_wdata_m_scanout[138];
	assign dff_rdata_w3_m_scanin[59] = dff_wdata_m_scanout[66];
	assign dff_rdata_w2_m_scanin[59] = dff_rdata_w3_m_scanout[59];
	assign dff_rdata_w1_m_scanin[59] = dff_rdata_w2_m_scanout[59];
	assign dff_rdata_w0_m_scanin[59] = dff_rdata_w1_m_scanout[59];
	assign dff_wdata_m_scanin[129] = dff_rdata_w0_m_scanout[59];
	assign dff_wdata_m_scanin[57] = dff_wdata_m_scanout[129];
	assign dff_rdata_w3_m_scanin[51] = dff_wdata_m_scanout[57];
	assign dff_rdata_w2_m_scanin[51] = dff_rdata_w3_m_scanout[51];
	assign dff_rdata_w1_m_scanin[51] = dff_rdata_w2_m_scanout[51];
	assign dff_rdata_w0_m_scanin[51] = dff_rdata_w1_m_scanout[51];
	assign dff_wdata_m_scanin[137] = dff_rdata_w0_m_scanout[51];
	assign dff_wdata_m_scanin[65] = dff_wdata_m_scanout[137];
	assign dff_rdata_w3_m_scanin[58] = dff_wdata_m_scanout[65];
	assign dff_rdata_w2_m_scanin[58] = dff_rdata_w3_m_scanout[58];
	assign dff_rdata_w1_m_scanin[58] = dff_rdata_w2_m_scanout[58];
	assign dff_rdata_w0_m_scanin[58] = dff_rdata_w1_m_scanout[58];
	assign dff_wdata_m_scanin[128] = dff_rdata_w0_m_scanout[58];
	assign dff_wdata_m_scanin[56] = dff_wdata_m_scanout[128];
	assign dff_rdata_w3_m_scanin[50] = dff_wdata_m_scanout[56];
	assign dff_rdata_w2_m_scanin[50] = dff_rdata_w3_m_scanout[50];
	assign dff_rdata_w1_m_scanin[50] = dff_rdata_w2_m_scanout[50];
	assign dff_rdata_w0_m_scanin[50] = dff_rdata_w1_m_scanout[50];
	assign dff_wdata_m_scanin[136] = dff_rdata_w0_m_scanout[50];
	assign dff_wdata_m_scanin[64] = dff_wdata_m_scanout[136];
	assign dff_rdata_w3_m_scanin[57] = dff_wdata_m_scanout[64];
	assign dff_rdata_w2_m_scanin[57] = dff_rdata_w3_m_scanout[57];
	assign dff_rdata_w1_m_scanin[57] = dff_rdata_w2_m_scanout[57];
	assign dff_rdata_w0_m_scanin[57] = dff_rdata_w1_m_scanout[57];
	assign dff_wdata_m_scanin[127] = dff_rdata_w0_m_scanout[57];
	assign dff_wdata_m_scanin[55] = dff_wdata_m_scanout[127];
	assign dff_rdata_w3_m_scanin[49] = dff_wdata_m_scanout[55];
	assign dff_rdata_w2_m_scanin[49] = dff_rdata_w3_m_scanout[49];
	assign dff_rdata_w1_m_scanin[49] = dff_rdata_w2_m_scanout[49];
	assign dff_rdata_w0_m_scanin[49] = dff_rdata_w1_m_scanout[49];
	assign dff_wdata_m_scanin[135] = dff_rdata_w0_m_scanout[49];
	assign dff_wdata_m_scanin[63] = dff_wdata_m_scanout[135];
	assign dff_rdata_w3_m_scanin[56] = dff_wdata_m_scanout[63];
	assign dff_rdata_w2_m_scanin[56] = dff_rdata_w3_m_scanout[56];
	assign dff_rdata_w1_m_scanin[56] = dff_rdata_w2_m_scanout[56];
	assign dff_rdata_w0_m_scanin[56] = dff_rdata_w1_m_scanout[56];
	assign dff_wdata_m_scanin[126] = dff_rdata_w0_m_scanout[56];
	assign dff_wdata_m_scanin[54] = dff_wdata_m_scanout[126];
	assign dff_rdata_w3_m_scanin[48] = dff_wdata_m_scanout[54];
	assign dff_rdata_w2_m_scanin[48] = dff_rdata_w3_m_scanout[48];
	assign dff_rdata_w1_m_scanin[48] = dff_rdata_w2_m_scanout[48];
	assign dff_rdata_w0_m_scanin[48] = dff_rdata_w1_m_scanout[48];
	assign dff_wdata_m_scanin[125] = dff_rdata_w0_m_scanout[48];
	assign dff_wdata_m_scanin[53] = dff_wdata_m_scanout[125];
	assign dff_rparity_w3_m_scanin[5] = dff_wdata_m_scanout[53];
	assign dff_rparity_w2_m_scanin[5] = dff_rparity_w3_m_scanout[5];
	assign dff_rparity_w1_m_scanin[5] = dff_rparity_w2_m_scanout[5];
	assign dff_rparity_w0_m_scanin[5] = dff_rparity_w1_m_scanout[5];
	assign dff_wdata_m_scanin[116] = dff_rparity_w0_m_scanout[5];
	assign dff_wdata_m_scanin[44] = dff_wdata_m_scanout[116];
	assign dff_rparity_w3_m_scanin[4] = dff_wdata_m_scanout[44];
	assign dff_rparity_w2_m_scanin[4] = dff_rparity_w3_m_scanout[4];
	assign dff_rparity_w1_m_scanin[4] = dff_rparity_w2_m_scanout[4];
	assign dff_rparity_w0_m_scanin[4] = dff_rparity_w1_m_scanout[4];
	assign dff_wdata_m_scanin[124] = dff_rparity_w0_m_scanout[4];
	assign dff_wdata_m_scanin[52] = dff_wdata_m_scanout[124];
	assign dff_rdata_w3_m_scanin[47] = dff_wdata_m_scanout[52];
	assign dff_rdata_w2_m_scanin[47] = dff_rdata_w3_m_scanout[47];
	assign dff_rdata_w1_m_scanin[47] = dff_rdata_w2_m_scanout[47];
	assign dff_rdata_w0_m_scanin[47] = dff_rdata_w1_m_scanout[47];
	assign dff_wdata_m_scanin[115] = dff_rdata_w0_m_scanout[47];
	assign dff_wdata_m_scanin[43] = dff_wdata_m_scanout[115];
	assign dff_rdata_w3_m_scanin[39] = dff_wdata_m_scanout[43];
	assign dff_rdata_w2_m_scanin[39] = dff_rdata_w3_m_scanout[39];
	assign dff_rdata_w1_m_scanin[39] = dff_rdata_w2_m_scanout[39];
	assign dff_rdata_w0_m_scanin[39] = dff_rdata_w1_m_scanout[39];
	assign dff_wdata_m_scanin[123] = dff_rdata_w0_m_scanout[39];
	assign dff_wdata_m_scanin[51] = dff_wdata_m_scanout[123];
	assign dff_rdata_w3_m_scanin[46] = dff_wdata_m_scanout[51];
	assign dff_rdata_w2_m_scanin[46] = dff_rdata_w3_m_scanout[46];
	assign dff_rdata_w1_m_scanin[46] = dff_rdata_w2_m_scanout[46];
	assign dff_rdata_w0_m_scanin[46] = dff_rdata_w1_m_scanout[46];
	assign dff_wdata_m_scanin[114] = dff_rdata_w0_m_scanout[46];
	assign dff_wdata_m_scanin[42] = dff_wdata_m_scanout[114];
	assign dff_rdata_w3_m_scanin[38] = dff_wdata_m_scanout[42];
	assign dff_rdata_w2_m_scanin[38] = dff_rdata_w3_m_scanout[38];
	assign dff_rdata_w1_m_scanin[38] = dff_rdata_w2_m_scanout[38];
	assign dff_rdata_w0_m_scanin[38] = dff_rdata_w1_m_scanout[38];
	assign dff_wdata_m_scanin[122] = dff_rdata_w0_m_scanout[38];
	assign dff_wdata_m_scanin[50] = dff_wdata_m_scanout[122];
	assign dff_rdata_w3_m_scanin[45] = dff_wdata_m_scanout[50];
	assign dff_rdata_w2_m_scanin[45] = dff_rdata_w3_m_scanout[45];
	assign dff_rdata_w1_m_scanin[45] = dff_rdata_w2_m_scanout[45];
	assign dff_rdata_w0_m_scanin[45] = dff_rdata_w1_m_scanout[45];
	assign dff_wdata_m_scanin[113] = dff_rdata_w0_m_scanout[45];
	assign dff_wdata_m_scanin[41] = dff_wdata_m_scanout[113];
	assign dff_rdata_w3_m_scanin[37] = dff_wdata_m_scanout[41];
	assign dff_rdata_w2_m_scanin[37] = dff_rdata_w3_m_scanout[37];
	assign dff_rdata_w1_m_scanin[37] = dff_rdata_w2_m_scanout[37];
	assign dff_rdata_w0_m_scanin[37] = dff_rdata_w1_m_scanout[37];
	assign dff_wdata_m_scanin[121] = dff_rdata_w0_m_scanout[37];
	assign dff_wdata_m_scanin[49] = dff_wdata_m_scanout[121];
	assign dff_rdata_w3_m_scanin[44] = dff_wdata_m_scanout[49];
	assign dff_rdata_w2_m_scanin[44] = dff_rdata_w3_m_scanout[44];
	assign dff_rdata_w1_m_scanin[44] = dff_rdata_w2_m_scanout[44];
	assign dff_rdata_w0_m_scanin[44] = dff_rdata_w1_m_scanout[44];
	assign dff_wdata_m_scanin[112] = dff_rdata_w0_m_scanout[44];
	assign dff_wdata_m_scanin[40] = dff_wdata_m_scanout[112];
	assign dff_rdata_w3_m_scanin[36] = dff_wdata_m_scanout[40];
	assign dff_rdata_w2_m_scanin[36] = dff_rdata_w3_m_scanout[36];
	assign dff_rdata_w1_m_scanin[36] = dff_rdata_w2_m_scanout[36];
	assign dff_rdata_w0_m_scanin[36] = dff_rdata_w1_m_scanout[36];
	assign dff_wdata_m_scanin[120] = dff_rdata_w0_m_scanout[36];
	assign dff_wdata_m_scanin[48] = dff_wdata_m_scanout[120];
	assign dff_rdata_w3_m_scanin[43] = dff_wdata_m_scanout[48];
	assign dff_rdata_w2_m_scanin[43] = dff_rdata_w3_m_scanout[43];
	assign dff_rdata_w1_m_scanin[43] = dff_rdata_w2_m_scanout[43];
	assign dff_rdata_w0_m_scanin[43] = dff_rdata_w1_m_scanout[43];
	assign dff_wdata_m_scanin[111] = dff_rdata_w0_m_scanout[43];
	assign dff_wdata_m_scanin[39] = dff_wdata_m_scanout[111];
	assign dff_rdata_w3_m_scanin[35] = dff_wdata_m_scanout[39];
	assign dff_rdata_w2_m_scanin[35] = dff_rdata_w3_m_scanout[35];
	assign dff_rdata_w1_m_scanin[35] = dff_rdata_w2_m_scanout[35];
	assign dff_rdata_w0_m_scanin[35] = dff_rdata_w1_m_scanout[35];
	assign dff_wdata_m_scanin[119] = dff_rdata_w0_m_scanout[35];
	assign dff_wdata_m_scanin[47] = dff_wdata_m_scanout[119];
	assign dff_rdata_w3_m_scanin[42] = dff_wdata_m_scanout[47];
	assign dff_rdata_w2_m_scanin[42] = dff_rdata_w3_m_scanout[42];
	assign dff_rdata_w1_m_scanin[42] = dff_rdata_w2_m_scanout[42];
	assign dff_rdata_w0_m_scanin[42] = dff_rdata_w1_m_scanout[42];
	assign dff_wdata_m_scanin[110] = dff_rdata_w0_m_scanout[42];
	assign dff_wdata_m_scanin[38] = dff_wdata_m_scanout[110];
	assign dff_rdata_w3_m_scanin[34] = dff_wdata_m_scanout[38];
	assign dff_rdata_w2_m_scanin[34] = dff_rdata_w3_m_scanout[34];
	assign dff_rdata_w1_m_scanin[34] = dff_rdata_w2_m_scanout[34];
	assign dff_rdata_w0_m_scanin[34] = dff_rdata_w1_m_scanout[34];
	assign dff_wdata_m_scanin[118] = dff_rdata_w0_m_scanout[34];
	assign dff_wdata_m_scanin[46] = dff_wdata_m_scanout[118];
	assign dff_rdata_w3_m_scanin[41] = dff_wdata_m_scanout[46];
	assign dff_rdata_w2_m_scanin[41] = dff_rdata_w3_m_scanout[41];
	assign dff_rdata_w1_m_scanin[41] = dff_rdata_w2_m_scanout[41];
	assign dff_rdata_w0_m_scanin[41] = dff_rdata_w1_m_scanout[41];
	assign dff_wdata_m_scanin[109] = dff_rdata_w0_m_scanout[41];
	assign dff_wdata_m_scanin[37] = dff_wdata_m_scanout[109];
	assign dff_rdata_w3_m_scanin[33] = dff_wdata_m_scanout[37];
	assign dff_rdata_w2_m_scanin[33] = dff_rdata_w3_m_scanout[33];
	assign dff_rdata_w1_m_scanin[33] = dff_rdata_w2_m_scanout[33];
	assign dff_rdata_w0_m_scanin[33] = dff_rdata_w1_m_scanout[33];
	assign dff_wdata_m_scanin[117] = dff_rdata_w0_m_scanout[33];
	assign dff_wdata_m_scanin[45] = dff_wdata_m_scanout[117];
	assign dff_rdata_w3_m_scanin[40] = dff_wdata_m_scanout[45];
	assign dff_rdata_w2_m_scanin[40] = dff_rdata_w3_m_scanout[40];
	assign dff_rdata_w1_m_scanin[40] = dff_rdata_w2_m_scanout[40];
	assign dff_rdata_w0_m_scanin[40] = dff_rdata_w1_m_scanout[40];
	assign dff_wdata_m_scanin[108] = dff_rdata_w0_m_scanout[40];
	assign dff_wdata_m_scanin[36] = dff_wdata_m_scanout[108];
	assign dff_rdata_w3_m_scanin[32] = dff_wdata_m_scanout[36];
	assign dff_rdata_w2_m_scanin[32] = dff_rdata_w3_m_scanout[32];
	assign dff_rdata_w1_m_scanin[32] = dff_rdata_w2_m_scanout[32];
	assign dff_rdata_w0_m_scanin[32] = dff_rdata_w1_m_scanout[32];
	assign dff_ctl_m_1_scanin[15] = dff_rdata_w0_m_scanout[32];
	assign dff_ctl_m_1_scanin[7] = dff_ctl_m_1_scanout[15];
	assign dff_ctl_m_1_scanin[14] = dff_ctl_m_1_scanout[7];
	assign dff_ctl_m_1_scanin[6] = dff_ctl_m_1_scanout[14];
	assign dff_ctl_m_1_scanin[13] = dff_ctl_m_1_scanout[6];
	assign dff_ctl_m_1_scanin[5] = dff_ctl_m_1_scanout[13];
	assign dff_ctl_m_1_scanin[12] = dff_ctl_m_1_scanout[5];
	assign dff_ctl_m_1_scanin[4] = dff_ctl_m_1_scanout[12];
	assign dff_byte_perr_w2_scanin[7] = dff_ctl_m_1_scanout[4];
	assign dff_byte_perr_w3_scanin[7] = dff_byte_perr_w2_scanout[7];
	assign dff_byte_perr_w3_scanin[6] = dff_byte_perr_w3_scanout[7];
	assign dff_byte_perr_w2_scanin[6] = dff_byte_perr_w3_scanout[6];
	assign dff_byte_perr_w2_scanin[5] = dff_byte_perr_w2_scanout[6];
	assign dff_byte_perr_w3_scanin[5] = dff_byte_perr_w2_scanout[5];
	assign dff_byte_perr_w3_scanin[4] = dff_byte_perr_w3_scanout[5];
	assign dff_byte_perr_w2_scanin[4] = dff_byte_perr_w3_scanout[4];
	assign dff_ctl_m_0_scanin[0] = dff_byte_perr_w2_scanout[4];
	assign dff_ctl_b_scanin[4] = dff_ctl_m_0_scanout[0];
	assign dff_ctl_b_scanin[0] = dff_ctl_b_scanout[4];
	assign dff_ctl_b_scanin[1] = dff_ctl_b_scanout[0];
	assign dff_ctl_b_scanin[2] = dff_ctl_b_scanout[1];
	assign dff_ctl_b_scanin[3] = dff_ctl_b_scanout[2];
	assign lat_ctl_eb_scanin[6] = dff_ctl_b_scanout[3];
	assign lat_ctl_eb_scanin[1] = lat_ctl_eb_scanout[6];
	assign lat_ctl_eb_scanin[0] = lat_ctl_eb_scanout[1];
	assign lat_ctl_eb_scanin[2] = lat_ctl_eb_scanout[0];
	assign lat_ctl_eb_scanin[3] = lat_ctl_eb_scanout[2];
	assign lat_addr_scanin[1] = lat_ctl_eb_scanout[3];
	assign lat_addr_scanin[0] = lat_addr_scanout[1];
	assign lat_addr_scanin[7] = lat_addr_scanout[0];
	assign lat_addr_scanin[6] = lat_addr_scanout[7];
	assign lat_addr_scanin[5] = lat_addr_scanout[6];
	assign lat_addr_scanin[4] = lat_addr_scanout[5];
	assign lat_addr_scanin[3] = lat_addr_scanout[4];
	assign lat_addr_scanin[2] = lat_addr_scanout[3];
	assign lat_ctl_eb_scanin[4] = lat_addr_scanout[2];
	assign dff_ctl_m_0_scanin[1] = lat_ctl_eb_scanout[4];
	assign dff_ctl_m_0_scanin[2] = dff_ctl_m_0_scanout[1];
	assign lat_ctl_eb_scanin[5] = dff_ctl_m_0_scanout[2];
	assign dff_byte_perr_w0_scanin[0] = lat_ctl_eb_scanout[5];
	assign dff_byte_perr_w1_scanin[0] = dff_byte_perr_w0_scanout[0];
	assign dff_byte_perr_w1_scanin[1] = dff_byte_perr_w1_scanout[0];
	assign dff_byte_perr_w0_scanin[1] = dff_byte_perr_w1_scanout[1];
	assign dff_byte_perr_w0_scanin[2] = dff_byte_perr_w0_scanout[1];
	assign dff_byte_perr_w1_scanin[2] = dff_byte_perr_w0_scanout[2];
	assign dff_byte_perr_w1_scanin[3] = dff_byte_perr_w1_scanout[2];
	assign dff_byte_perr_w0_scanin[3] = dff_byte_perr_w1_scanout[3];
	assign dff_wdata_m_scanin[80] = dff_byte_perr_w0_scanout[3];
	assign dff_wdata_m_scanin[8] = dff_wdata_m_scanout[80];
	assign dff_rparity_w3_m_scanin[0] = dff_wdata_m_scanout[8];
	assign dff_rparity_w2_m_scanin[0] = dff_rparity_w3_m_scanout[0];
	assign dff_rparity_w1_m_scanin[0] = dff_rparity_w2_m_scanout[0];
	assign dff_rparity_w0_m_scanin[0] = dff_rparity_w1_m_scanout[0];
	assign dff_wdata_m_scanin[89] = dff_rparity_w0_m_scanout[0];
	assign dff_wdata_m_scanin[17] = dff_wdata_m_scanout[89];
	assign dff_rparity_w3_m_scanin[1] = dff_wdata_m_scanout[17];
	assign dff_rparity_w2_m_scanin[1] = dff_rparity_w3_m_scanout[1];
	assign dff_rparity_w1_m_scanin[1] = dff_rparity_w2_m_scanout[1];
	assign dff_rparity_w0_m_scanin[1] = dff_rparity_w1_m_scanout[1];
	assign dff_wdata_m_scanin[72] = dff_rparity_w0_m_scanout[1];
	assign dff_wdata_m_scanin[0] = dff_wdata_m_scanout[72];
	assign dff_rdata_w3_m_scanin[0] = dff_wdata_m_scanout[0];
	assign dff_rdata_w2_m_scanin[0] = dff_rdata_w3_m_scanout[0];
	assign dff_rdata_w1_m_scanin[0] = dff_rdata_w2_m_scanout[0];
	assign dff_rdata_w0_m_scanin[0] = dff_rdata_w1_m_scanout[0];
	assign dff_wdata_m_scanin[81] = dff_rdata_w0_m_scanout[0];
	assign dff_wdata_m_scanin[9] = dff_wdata_m_scanout[81];
	assign dff_rdata_w3_m_scanin[8] = dff_wdata_m_scanout[9];
	assign dff_rdata_w2_m_scanin[8] = dff_rdata_w3_m_scanout[8];
	assign dff_rdata_w1_m_scanin[8] = dff_rdata_w2_m_scanout[8];
	assign dff_rdata_w0_m_scanin[8] = dff_rdata_w1_m_scanout[8];
	assign dff_wdata_m_scanin[73] = dff_rdata_w0_m_scanout[8];
	assign dff_wdata_m_scanin[1] = dff_wdata_m_scanout[73];
	assign dff_rdata_w3_m_scanin[1] = dff_wdata_m_scanout[1];
	assign dff_rdata_w2_m_scanin[1] = dff_rdata_w3_m_scanout[1];
	assign dff_rdata_w1_m_scanin[1] = dff_rdata_w2_m_scanout[1];
	assign dff_rdata_w0_m_scanin[1] = dff_rdata_w1_m_scanout[1];
	assign dff_wdata_m_scanin[82] = dff_rdata_w0_m_scanout[1];
	assign dff_wdata_m_scanin[10] = dff_wdata_m_scanout[82];
	assign dff_rdata_w3_m_scanin[9] = dff_wdata_m_scanout[10];
	assign dff_rdata_w2_m_scanin[9] = dff_rdata_w3_m_scanout[9];
	assign dff_rdata_w1_m_scanin[9] = dff_rdata_w2_m_scanout[9];
	assign dff_rdata_w0_m_scanin[9] = dff_rdata_w1_m_scanout[9];
	assign dff_wdata_m_scanin[74] = dff_rdata_w0_m_scanout[9];
	assign dff_wdata_m_scanin[2] = dff_wdata_m_scanout[74];
	assign dff_rdata_w3_m_scanin[2] = dff_wdata_m_scanout[2];
	assign dff_rdata_w2_m_scanin[2] = dff_rdata_w3_m_scanout[2];
	assign dff_rdata_w1_m_scanin[2] = dff_rdata_w2_m_scanout[2];
	assign dff_rdata_w0_m_scanin[2] = dff_rdata_w1_m_scanout[2];
	assign dff_wdata_m_scanin[83] = dff_rdata_w0_m_scanout[2];
	assign dff_wdata_m_scanin[11] = dff_wdata_m_scanout[83];
	assign dff_rdata_w3_m_scanin[10] = dff_wdata_m_scanout[11];
	assign dff_rdata_w2_m_scanin[10] = dff_rdata_w3_m_scanout[10];
	assign dff_rdata_w1_m_scanin[10] = dff_rdata_w2_m_scanout[10];
	assign dff_rdata_w0_m_scanin[10] = dff_rdata_w1_m_scanout[10];
	assign dff_wdata_m_scanin[75] = dff_rdata_w0_m_scanout[10];
	assign dff_wdata_m_scanin[3] = dff_wdata_m_scanout[75];
	assign dff_rdata_w3_m_scanin[3] = dff_wdata_m_scanout[3];
	assign dff_rdata_w2_m_scanin[3] = dff_rdata_w3_m_scanout[3];
	assign dff_rdata_w1_m_scanin[3] = dff_rdata_w2_m_scanout[3];
	assign dff_rdata_w0_m_scanin[3] = dff_rdata_w1_m_scanout[3];
	assign dff_wdata_m_scanin[84] = dff_rdata_w0_m_scanout[3];
	assign dff_wdata_m_scanin[12] = dff_wdata_m_scanout[84];
	assign dff_rdata_w3_m_scanin[11] = dff_wdata_m_scanout[12];
	assign dff_rdata_w2_m_scanin[11] = dff_rdata_w3_m_scanout[11];
	assign dff_rdata_w1_m_scanin[11] = dff_rdata_w2_m_scanout[11];
	assign dff_rdata_w0_m_scanin[11] = dff_rdata_w1_m_scanout[11];
	assign dff_wdata_m_scanin[76] = dff_rdata_w0_m_scanout[11];
	assign dff_wdata_m_scanin[4] = dff_wdata_m_scanout[76];
	assign dff_rdata_w3_m_scanin[4] = dff_wdata_m_scanout[4];
	assign dff_rdata_w2_m_scanin[4] = dff_rdata_w3_m_scanout[4];
	assign dff_rdata_w1_m_scanin[4] = dff_rdata_w2_m_scanout[4];
	assign dff_rdata_w0_m_scanin[4] = dff_rdata_w1_m_scanout[4];
	assign dff_wdata_m_scanin[85] = dff_rdata_w0_m_scanout[4];
	assign dff_wdata_m_scanin[13] = dff_wdata_m_scanout[85];
	assign dff_rdata_w3_m_scanin[12] = dff_wdata_m_scanout[13];
	assign dff_rdata_w2_m_scanin[12] = dff_rdata_w3_m_scanout[12];
	assign dff_rdata_w1_m_scanin[12] = dff_rdata_w2_m_scanout[12];
	assign dff_rdata_w0_m_scanin[12] = dff_rdata_w1_m_scanout[12];
	assign dff_wdata_m_scanin[77] = dff_rdata_w0_m_scanout[12];
	assign dff_wdata_m_scanin[5] = dff_wdata_m_scanout[77];
	assign dff_rdata_w3_m_scanin[5] = dff_wdata_m_scanout[5];
	assign dff_rdata_w2_m_scanin[5] = dff_rdata_w3_m_scanout[5];
	assign dff_rdata_w1_m_scanin[5] = dff_rdata_w2_m_scanout[5];
	assign dff_rdata_w0_m_scanin[5] = dff_rdata_w1_m_scanout[5];
	assign dff_wdata_m_scanin[86] = dff_rdata_w0_m_scanout[5];
	assign dff_wdata_m_scanin[14] = dff_wdata_m_scanout[86];
	assign dff_rdata_w3_m_scanin[13] = dff_wdata_m_scanout[14];
	assign dff_rdata_w2_m_scanin[13] = dff_rdata_w3_m_scanout[13];
	assign dff_rdata_w1_m_scanin[13] = dff_rdata_w2_m_scanout[13];
	assign dff_rdata_w0_m_scanin[13] = dff_rdata_w1_m_scanout[13];
	assign dff_wdata_m_scanin[78] = dff_rdata_w0_m_scanout[13];
	assign dff_wdata_m_scanin[6] = dff_wdata_m_scanout[78];
	assign dff_rdata_w3_m_scanin[6] = dff_wdata_m_scanout[6];
	assign dff_rdata_w2_m_scanin[6] = dff_rdata_w3_m_scanout[6];
	assign dff_rdata_w1_m_scanin[6] = dff_rdata_w2_m_scanout[6];
	assign dff_rdata_w0_m_scanin[6] = dff_rdata_w1_m_scanout[6];
	assign dff_wdata_m_scanin[87] = dff_rdata_w0_m_scanout[6];
	assign dff_wdata_m_scanin[15] = dff_wdata_m_scanout[87];
	assign dff_rdata_w3_m_scanin[14] = dff_wdata_m_scanout[15];
	assign dff_rdata_w2_m_scanin[14] = dff_rdata_w3_m_scanout[14];
	assign dff_rdata_w1_m_scanin[14] = dff_rdata_w2_m_scanout[14];
	assign dff_rdata_w0_m_scanin[14] = dff_rdata_w1_m_scanout[14];
	assign dff_wdata_m_scanin[79] = dff_rdata_w0_m_scanout[14];
	assign dff_wdata_m_scanin[7] = dff_wdata_m_scanout[79];
	assign dff_rdata_w3_m_scanin[7] = dff_wdata_m_scanout[7];
	assign dff_rdata_w2_m_scanin[7] = dff_rdata_w3_m_scanout[7];
	assign dff_rdata_w1_m_scanin[7] = dff_rdata_w2_m_scanout[7];
	assign dff_rdata_w0_m_scanin[7] = dff_rdata_w1_m_scanout[7];
	assign dff_wdata_m_scanin[88] = dff_rdata_w0_m_scanout[7];
	assign dff_wdata_m_scanin[16] = dff_wdata_m_scanout[88];
	assign dff_rdata_w3_m_scanin[15] = dff_wdata_m_scanout[16];
	assign dff_rdata_w2_m_scanin[15] = dff_rdata_w3_m_scanout[15];
	assign dff_rdata_w1_m_scanin[15] = dff_rdata_w2_m_scanout[15];
	assign dff_rdata_w0_m_scanin[15] = dff_rdata_w1_m_scanout[15];
	assign dff_wdata_m_scanin[98] = dff_rdata_w0_m_scanout[15];
	assign dff_wdata_m_scanin[26] = dff_wdata_m_scanout[98];
	assign dff_rparity_w3_m_scanin[2] = dff_wdata_m_scanout[26];
	assign dff_rparity_w2_m_scanin[2] = dff_rparity_w3_m_scanout[2];
	assign dff_rparity_w1_m_scanin[2] = dff_rparity_w2_m_scanout[2];
	assign dff_rparity_w0_m_scanin[2] = dff_rparity_w1_m_scanout[2];
	assign dff_wdata_m_scanin[107] = dff_rparity_w0_m_scanout[2];
	assign dff_wdata_m_scanin[35] = dff_wdata_m_scanout[107];
	assign dff_rparity_w3_m_scanin[3] = dff_wdata_m_scanout[35];
	assign dff_rparity_w2_m_scanin[3] = dff_rparity_w3_m_scanout[3];
	assign dff_rparity_w1_m_scanin[3] = dff_rparity_w2_m_scanout[3];
	assign dff_rparity_w0_m_scanin[3] = dff_rparity_w1_m_scanout[3];
	assign dff_wdata_m_scanin[90] = dff_rparity_w0_m_scanout[3];
	assign dff_wdata_m_scanin[18] = dff_wdata_m_scanout[90];
	assign dff_rdata_w3_m_scanin[16] = dff_wdata_m_scanout[18];
	assign dff_rdata_w2_m_scanin[16] = dff_rdata_w3_m_scanout[16];
	assign dff_rdata_w1_m_scanin[16] = dff_rdata_w2_m_scanout[16];
	assign dff_rdata_w0_m_scanin[16] = dff_rdata_w1_m_scanout[16];
	assign dff_wdata_m_scanin[99] = dff_rdata_w0_m_scanout[16];
	assign dff_wdata_m_scanin[27] = dff_wdata_m_scanout[99];
	assign dff_rdata_w3_m_scanin[24] = dff_wdata_m_scanout[27];
	assign dff_rdata_w2_m_scanin[24] = dff_rdata_w3_m_scanout[24];
	assign dff_rdata_w1_m_scanin[24] = dff_rdata_w2_m_scanout[24];
	assign dff_rdata_w0_m_scanin[24] = dff_rdata_w1_m_scanout[24];
	assign dff_wdata_m_scanin[91] = dff_rdata_w0_m_scanout[24];
	assign dff_wdata_m_scanin[19] = dff_wdata_m_scanout[91];
	assign dff_rdata_w3_m_scanin[17] = dff_wdata_m_scanout[19];
	assign dff_rdata_w2_m_scanin[17] = dff_rdata_w3_m_scanout[17];
	assign dff_rdata_w1_m_scanin[17] = dff_rdata_w2_m_scanout[17];
	assign dff_rdata_w0_m_scanin[17] = dff_rdata_w1_m_scanout[17];
	assign dff_wdata_m_scanin[100] = dff_rdata_w0_m_scanout[17];
	assign dff_wdata_m_scanin[28] = dff_wdata_m_scanout[100];
	assign dff_rdata_w3_m_scanin[25] = dff_wdata_m_scanout[28];
	assign dff_rdata_w2_m_scanin[25] = dff_rdata_w3_m_scanout[25];
	assign dff_rdata_w1_m_scanin[25] = dff_rdata_w2_m_scanout[25];
	assign dff_rdata_w0_m_scanin[25] = dff_rdata_w1_m_scanout[25];
	assign dff_wdata_m_scanin[92] = dff_rdata_w0_m_scanout[25];
	assign dff_wdata_m_scanin[20] = dff_wdata_m_scanout[92];
	assign dff_rdata_w3_m_scanin[18] = dff_wdata_m_scanout[20];
	assign dff_rdata_w2_m_scanin[18] = dff_rdata_w3_m_scanout[18];
	assign dff_rdata_w1_m_scanin[18] = dff_rdata_w2_m_scanout[18];
	assign dff_rdata_w0_m_scanin[18] = dff_rdata_w1_m_scanout[18];
	assign dff_wdata_m_scanin[101] = dff_rdata_w0_m_scanout[18];
	assign dff_wdata_m_scanin[29] = dff_wdata_m_scanout[101];
	assign dff_rdata_w3_m_scanin[26] = dff_wdata_m_scanout[29];
	assign dff_rdata_w2_m_scanin[26] = dff_rdata_w3_m_scanout[26];
	assign dff_rdata_w1_m_scanin[26] = dff_rdata_w2_m_scanout[26];
	assign dff_rdata_w0_m_scanin[26] = dff_rdata_w1_m_scanout[26];
	assign dff_wdata_m_scanin[93] = dff_rdata_w0_m_scanout[26];
	assign dff_wdata_m_scanin[21] = dff_wdata_m_scanout[93];
	assign dff_rdata_w3_m_scanin[19] = dff_wdata_m_scanout[21];
	assign dff_rdata_w2_m_scanin[19] = dff_rdata_w3_m_scanout[19];
	assign dff_rdata_w1_m_scanin[19] = dff_rdata_w2_m_scanout[19];
	assign dff_rdata_w0_m_scanin[19] = dff_rdata_w1_m_scanout[19];
	assign dff_wdata_m_scanin[102] = dff_rdata_w0_m_scanout[19];
	assign dff_wdata_m_scanin[30] = dff_wdata_m_scanout[102];
	assign dff_rdata_w3_m_scanin[27] = dff_wdata_m_scanout[30];
	assign dff_rdata_w2_m_scanin[27] = dff_rdata_w3_m_scanout[27];
	assign dff_rdata_w1_m_scanin[27] = dff_rdata_w2_m_scanout[27];
	assign dff_rdata_w0_m_scanin[27] = dff_rdata_w1_m_scanout[27];
	assign dff_wdata_m_scanin[94] = dff_rdata_w0_m_scanout[27];
	assign dff_wdata_m_scanin[22] = dff_wdata_m_scanout[94];
	assign dff_rdata_w3_m_scanin[20] = dff_wdata_m_scanout[22];
	assign dff_rdata_w2_m_scanin[20] = dff_rdata_w3_m_scanout[20];
	assign dff_rdata_w1_m_scanin[20] = dff_rdata_w2_m_scanout[20];
	assign dff_rdata_w0_m_scanin[20] = dff_rdata_w1_m_scanout[20];
	assign dff_wdata_m_scanin[103] = dff_rdata_w0_m_scanout[20];
	assign dff_wdata_m_scanin[31] = dff_wdata_m_scanout[103];
	assign dff_rdata_w3_m_scanin[28] = dff_wdata_m_scanout[31];
	assign dff_rdata_w2_m_scanin[28] = dff_rdata_w3_m_scanout[28];
	assign dff_rdata_w1_m_scanin[28] = dff_rdata_w2_m_scanout[28];
	assign dff_rdata_w0_m_scanin[28] = dff_rdata_w1_m_scanout[28];
	assign dff_wdata_m_scanin[95] = dff_rdata_w0_m_scanout[28];
	assign dff_wdata_m_scanin[23] = dff_wdata_m_scanout[95];
	assign dff_rdata_w3_m_scanin[21] = dff_wdata_m_scanout[23];
	assign dff_rdata_w2_m_scanin[21] = dff_rdata_w3_m_scanout[21];
	assign dff_rdata_w1_m_scanin[21] = dff_rdata_w2_m_scanout[21];
	assign dff_rdata_w0_m_scanin[21] = dff_rdata_w1_m_scanout[21];
	assign dff_wdata_m_scanin[104] = dff_rdata_w0_m_scanout[21];
	assign dff_wdata_m_scanin[32] = dff_wdata_m_scanout[104];
	assign dff_rdata_w3_m_scanin[29] = dff_wdata_m_scanout[32];
	assign dff_rdata_w2_m_scanin[29] = dff_rdata_w3_m_scanout[29];
	assign dff_rdata_w1_m_scanin[29] = dff_rdata_w2_m_scanout[29];
	assign dff_rdata_w0_m_scanin[29] = dff_rdata_w1_m_scanout[29];
	assign dff_wdata_m_scanin[96] = dff_rdata_w0_m_scanout[29];
	assign dff_wdata_m_scanin[24] = dff_wdata_m_scanout[96];
	assign dff_rdata_w3_m_scanin[22] = dff_wdata_m_scanout[24];
	assign dff_rdata_w2_m_scanin[22] = dff_rdata_w3_m_scanout[22];
	assign dff_rdata_w1_m_scanin[22] = dff_rdata_w2_m_scanout[22];
	assign dff_rdata_w0_m_scanin[22] = dff_rdata_w1_m_scanout[22];
	assign dff_wdata_m_scanin[105] = dff_rdata_w0_m_scanout[22];
	assign dff_wdata_m_scanin[33] = dff_wdata_m_scanout[105];
	assign dff_rdata_w3_m_scanin[30] = dff_wdata_m_scanout[33];
	assign dff_rdata_w2_m_scanin[30] = dff_rdata_w3_m_scanout[30];
	assign dff_rdata_w1_m_scanin[30] = dff_rdata_w2_m_scanout[30];
	assign dff_rdata_w0_m_scanin[30] = dff_rdata_w1_m_scanout[30];
	assign dff_wdata_m_scanin[97] = dff_rdata_w0_m_scanout[30];
	assign dff_wdata_m_scanin[25] = dff_wdata_m_scanout[97];
	assign dff_rdata_w3_m_scanin[23] = dff_wdata_m_scanout[25];
	assign dff_rdata_w2_m_scanin[23] = dff_rdata_w3_m_scanout[23];
	assign dff_rdata_w1_m_scanin[23] = dff_rdata_w2_m_scanout[23];
	assign dff_rdata_w0_m_scanin[23] = dff_rdata_w1_m_scanout[23];
	assign dff_wdata_m_scanin[106] = dff_rdata_w0_m_scanout[23];
	assign dff_wdata_m_scanin[34] = dff_wdata_m_scanout[106];
	assign dff_rdata_w3_m_scanin[31] = dff_wdata_m_scanout[34];
	assign dff_rdata_w2_m_scanin[31] = dff_rdata_w3_m_scanout[31];
	assign dff_rdata_w1_m_scanin[31] = dff_rdata_w2_m_scanout[31];
	assign dff_rdata_w0_m_scanin[31] = dff_rdata_w1_m_scanout[31];
	assign dff_ctl_m_1_scanin[8] = dff_rdata_w0_m_scanout[31];
	assign dff_ctl_m_1_scanin[0] = dff_ctl_m_1_scanout[8];
	assign dff_ctl_m_1_scanin[9] = dff_ctl_m_1_scanout[0];
	assign dff_ctl_m_1_scanin[1] = dff_ctl_m_1_scanout[9];
	assign dff_ctl_m_1_scanin[10] = dff_ctl_m_1_scanout[1];
	assign dff_ctl_m_1_scanin[2] = dff_ctl_m_1_scanout[10];
	assign dff_ctl_m_1_scanin[11] = dff_ctl_m_1_scanout[2];
	assign dff_ctl_m_1_scanin[3] = dff_ctl_m_1_scanout[11];
	assign dff_byte_perr_w2_scanin[0] = dff_ctl_m_1_scanout[3];
	assign dff_byte_perr_w3_scanin[0] = dff_byte_perr_w2_scanout[0];
	assign dff_byte_perr_w3_scanin[1] = dff_byte_perr_w3_scanout[0];
	assign dff_byte_perr_w2_scanin[1] = dff_byte_perr_w3_scanout[1];
	assign dff_byte_perr_w2_scanin[2] = dff_byte_perr_w2_scanout[1];
	assign dff_byte_perr_w3_scanin[2] = dff_byte_perr_w2_scanout[2];
	assign dff_byte_perr_w3_scanin[3] = dff_byte_perr_w3_scanout[2];
	assign dff_byte_perr_w2_scanin[3] = dff_byte_perr_w3_scanout[3];
	assign dff_msb_w3_scanin[7] = dff_byte_perr_w2_scanout[3];
	assign dff_msb_w2_scanin[7] = dff_msb_w3_scanout[7];
	assign dff_msb_w1_scanin[7] = dff_msb_w2_scanout[7];
	assign dff_msb_w0_scanin[7] = dff_msb_w1_scanout[7];
	assign dff_msb_w3_scanin[6] = dff_msb_w0_scanout[7];
	assign dff_msb_w2_scanin[6] = dff_msb_w3_scanout[6];
	assign dff_msb_w1_scanin[6] = dff_msb_w2_scanout[6];
	assign dff_msb_w0_scanin[6] = dff_msb_w1_scanout[6];
	assign dff_msb_w3_scanin[5] = dff_msb_w0_scanout[6];
	assign dff_msb_w2_scanin[5] = dff_msb_w3_scanout[5];
	assign dff_msb_w1_scanin[5] = dff_msb_w2_scanout[5];
	assign dff_msb_w0_scanin[5] = dff_msb_w1_scanout[5];
	assign dff_msb_w3_scanin[4] = dff_msb_w0_scanout[5];
	assign dff_msb_w2_scanin[4] = dff_msb_w3_scanout[4];
	assign dff_msb_w1_scanin[4] = dff_msb_w2_scanout[4];
	assign dff_msb_w0_scanin[4] = dff_msb_w1_scanout[4];
	assign dff_msb_w3_scanin[0] = dff_msb_w0_scanout[4];
	assign dff_msb_w2_scanin[0] = dff_msb_w3_scanout[0];
	assign dff_msb_w1_scanin[0] = dff_msb_w2_scanout[0];
	assign dff_msb_w0_scanin[0] = dff_msb_w1_scanout[0];
	assign dff_msb_w3_scanin[1] = dff_msb_w0_scanout[0];
	assign dff_msb_w2_scanin[1] = dff_msb_w3_scanout[1];
	assign dff_msb_w1_scanin[1] = dff_msb_w2_scanout[1];
	assign dff_msb_w0_scanin[1] = dff_msb_w1_scanout[1];
	assign dff_msb_w3_scanin[2] = dff_msb_w0_scanout[1];
	assign dff_msb_w2_scanin[2] = dff_msb_w3_scanout[2];
	assign dff_msb_w1_scanin[2] = dff_msb_w2_scanout[2];
	assign dff_msb_w0_scanin[2] = dff_msb_w1_scanout[2];
	assign dff_msb_w3_scanin[3] = dff_msb_w0_scanout[2];
	assign dff_msb_w2_scanin[3] = dff_msb_w3_scanout[3];
	assign dff_msb_w1_scanin[3] = dff_msb_w2_scanout[3];
	assign dff_msb_w0_scanin[3] = dff_msb_w1_scanout[3];
	assign dff_red_out_scanin[2] = dff_msb_w0_scanout[3];
	assign dff_red_out_scanin[3] = dff_red_out_scanout[2];
	assign dff_red_out_scanin[4] = dff_red_out_scanout[3];
	assign dff_red_out_scanin[5] = dff_red_out_scanout[4];
	assign dff_red_out_scanin[6] = dff_red_out_scanout[5];
	assign dff_red_out_scanin[7] = dff_red_out_scanout[6];
	assign dff_red_out_scanin[0] = dff_red_out_scanout[7];
	assign dff_red_out_scanin[1] = dff_red_out_scanout[0];
	assign dff_red_in_scanin[2] = dff_red_out_scanout[1];
	assign dff_red_in_scanin[3] = dff_red_in_scanout[2];
	assign dff_red_in_scanin[1] = dff_red_in_scanout[3];
	assign dff_red_in_scanin[0] = dff_red_in_scanout[1];
	assign dff_red_in_scanin[6] = dff_red_in_scanout[0];
	assign dff_red_in_scanin[7] = dff_red_in_scanout[6];
	assign dff_red_in_scanin[8] = dff_red_in_scanout[7];
	assign dff_red_in_scanin[9] = dff_red_in_scanout[8];
	assign dff_red_in_scanin[10] = dff_red_in_scanout[9];
	assign dff_red_in_scanin[11] = dff_red_in_scanout[10];
	assign dff_red_in_scanin[4] = dff_red_in_scanout[11];
	assign dff_red_in_scanin[5] = dff_red_in_scanout[4];
	assign scan_out = dff_red_in_scanout[5];

	l1clkhdr_ctl_macro l1ch_in(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.pce_ov				(1'b1), 
		.se				(tcu_se_scancollar_in), 
		.l1clk				(l1clk_in), 
		.stop				(stop));
	l1clkhdr_ctl_macro l1ch_in_pm(
		.l2clk				(l2clk), 
		.l1en				(dcache_wclk_en_e), 
		.se				(tcu_se_scancollar_in), 
		.l1clk				(l1clk_in_pm), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	l1clkhdr_ctl_macro l1ch_out_pm(
		.l2clk				(l2clk), 
		.l1en				(dcache_rclk_en_m), 
		.se				(tcu_se_scancollar_out), 
		.l1clk				(l1clk_out_pm), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	l1clkhdr_ctl_macro l1ch_out(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.pce_ov				(1'b1), 
		.se				(tcu_se_scancollar_out), 
		.l1clk				(l1clk_out), 
		.stop				(stop));
	l1clkhdr_ctl_macro l1ch_free(
		.l2clk				(l2clk), 
		.l1en				(dcache_clk_en_e), 
		.se				(tcu_scan_en), 
		.l1clk				(l1clk_free), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	l1clkhdr_ctl_macro l1ch_free_wpm(
		.l2clk				(l2clk), 
		.l1en				(dcache_wclk_en_e), 
		.se				(tcu_scan_en), 
		.l1clk				(l1clk_free_wpm), 
		.pce_ov				(pce_ov), 
		.stop				(stop));
	l1clkhdr_ctl_macro l1ch_red(
		.l2clk				(l2clk), 
		.l1en				(1'b1), 
		.pce_ov				(1'b1), 
		.se				(1'b0), 
		.l1clk				(l1clk_red), 
		.stop				(stop));
	mux_macro__mux_aope__ports_2__width_8 mx_addr_e(
		.din0				(dcache_alt_addr_e[10:3]), 
		.din1				(dcache_rd_addr_e[10:3]), 
		.sel0				(dcache_alt_addr_sel_e), 
		.dout				(dcache_rwaddr_e[10:3]));
	tisram_msff_macro__fs_1__width_8 lat_addr(
		.scan_in			(lat_addr_scanin[7:0]), 
		.scan_out			(lat_addr_scanout[7:0]), 
		.l1clk				(l1clk_in), 
		.d				(dcache_rwaddr_e[10:3]), 
		.latout				(dcache_rwaddr_eb[10:3]), 
		.latout_l			(dcache_rwaddr_l_unused[10:3]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	mux_macro__mux_aodec__ports_4__width_4 wr_way_decode(
		.din0				(4'b1), 
		.din1				(4'd2), 
		.din2				(4'd4), 
		.din3				(4'd8), 
		.sel				(dcache_wr_way_e[1:0]), 
		.dout				(wr_way_dec_e[3:0]));
	tisram_msff_macro__fs_1__width_7 lat_ctl_eb(
		.scan_in			(lat_ctl_eb_scanin[6:0]), 
		.scan_out			(lat_ctl_eb_scanout[6:0]), 
		.l1clk				(l1clk_in), 
		.d				({dcache_rvld_e, dcache_rvld_e,
		dcache_wvld_e, wr_way_dec_e[3:0]}), 
		.latout				({dcache_rvld_top_eb,
		dcache_rvld_bot_eb, dcache_wvld_eb, wr_way_dec_eb[3:0]}), 
		.latout_l			(lat_ctl_unused[6:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_3 dff_ctl_m_0(
		.scan_in			(dff_ctl_m_0_scanin[2:0]), 
		.scan_out			(dff_ctl_m_0_scanout[2:0]), 
		.l1clk				(l1clk_in), 
		.din				({dcache_rvld_e, dcache_wvld_e,
		dcache_bypass_e_}), 
		.dout				({dcache_rvld_m, dcache_wvld_m,
		dcache_bypass_m_}), 
		.siclk				(siclk), 
		.soclk				(soclk));
	tisram_msff_macro__fs_1__width_16 dff_ctl_m_1(
		.scan_in			(dff_ctl_m_1_scanin[15:0]), 
		.scan_out			(dff_ctl_m_1_scanout[15:0]), 
		.l1clk				(l1clk_in_pm), 
		.d				(dcache_byte_wr_en_e[15:0]), 
		.latout				(byte_wr_en_eb[15:0]), 
		.latout_l			(dff_ctl_l_unused[15:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_5 dff_ctl_b(
		.scan_in			(dff_ctl_b_scanin[4:0]), 
		.scan_out			(dff_ctl_b_scanout[4:0]), 
		.l1clk				(l1clk_in), 
		.din				({dcache_alt_way_sel_m,
		dcache_alt_rsel_way_m[3:0]}), 
		.dout				({dcache_alt_way_sel_b,
		dcache_alt_rsel_way_b[3:0]}), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_144 dff_wdata_m(
		.scan_in			(dff_wdata_m_scanin[143:0]), 
		.scan_out			(dff_wdata_m_scanout[143:0]), 
		.l1clk				(l1clk_in_pm), 
		.din				(dcache_wdata_e[143:0]), 
		.dout				({dcache_wparity_m[15],
		dcache_wdata_m[127:120], dcache_wparity_m[14],
		dcache_wdata_m[119:112], dcache_wparity_m[13],
		dcache_wdata_m[111:104], dcache_wparity_m[12],
		dcache_wdata_m[103:96], dcache_wparity_m[11],
		dcache_wdata_m[95:88], dcache_wparity_m[10],
		dcache_wdata_m[87:80], dcache_wparity_m[9],
		dcache_wdata_m[79:72], dcache_wparity_m[8],
		dcache_wdata_m[71:64], dcache_wparity_m[7],
		dcache_wdata_m[63:56], dcache_wparity_m[6],
		dcache_wdata_m[55:48], dcache_wparity_m[5],
		dcache_wdata_m[47:40], dcache_wparity_m[4],
		dcache_wdata_m[39:32], dcache_wparity_m[3],
		dcache_wdata_m[31:24], dcache_wparity_m[2],
		dcache_wdata_m[23:16], dcache_wparity_m[1],
		dcache_wdata_m[15:8], dcache_wparity_m[0],
		dcache_wdata_m[7:0]}), 
		.siclk				(siclk), 
		.soclk				(soclk));
	n2_dca_sp_9kb_array array(
		.l1clk				(l1clk_free), 
		.l1clk_wr			(l1clk_free_wpm), 
		.addr_b				(dcache_rwaddr_eb[10:3]), 
		.rd_en_top_b			(dcache_rvld_top_eb), 
		.rd_en_bot_b			(dcache_rvld_bot_eb), 
		.rd_en_a			(dcache_rvld_m), 
		.wr_en_b			(dcache_wvld_eb), 
		.wr_en_a			(dcache_wvld_m), 
		.wr_inh_b			(tcu_array_wr_inhibit), 
		.byte_wr_en_b			(byte_wr_en_eb[15:0]), 
		.wr_waysel_b			(wr_way_dec_eb[3:0]), 
		.fuse_dca_repair_value		(fuse_dca_repair_value_ff[5:0]),
		.fuse_dca_repair_en		(fuse_dca_repair_en_ff[1:0]), 
		.fuse_dca_rid			(fuse_dca_rid_ff[1:0]), 
		.fuse_dca_wen			(fuse_dca_wen_ff), 
		.fuse_red_reset			(fuse_red_reset_ff), 
		.dca_fuse_repair_value		
		(dca_fuse_repair_value_pre[5:0]), 
		.dca_fuse_repair_en		(dca_fuse_repair_en_pre[1:0]), 
		.l1clk_red			(l1clk_red), 
		.dcache_wdata_m			(dcache_wdata_m[127:0]), 
		.dcache_wparity_m		(dcache_wparity_m[15:0]), 
		.dcache_rdata_w0_m		(dcache_rdata_w0_m[63:0]), 
		.rparity_w0_m			(rparity_w0_m[7:0]), 
		.dcache_rdata_w1_m		(dcache_rdata_w1_m[63:0]), 
		.rparity_w1_m			(rparity_w1_m[7:0]), 
		.dcache_rdata_w2_m		(dcache_rdata_w2_m[63:0]), 
		.rparity_w2_m			(rparity_w2_m[7:0]), 
		.dcache_rdata_w3_m		(dcache_rdata_w3_m[63:0]), 
		.rparity_w3_m			(rparity_w3_m[7:0]), 
		.vnw_ary			(vnw_ary));
	mux_macro__mux_aope__ports_2__width_64 mx_way0_data(
		.din0				(dcache_rdata_w0_m[63:0]), 
		.din1				
		(lsu_l2fill_or_byp_data_m[63:0]), 
		.sel0				(dcache_bypass_m_), 
		.dout				(rdata_w0_m[63:0]));
	msff_ctl_macro__fs_1__width_8 dff_msb_w0(
		.scan_in			(dff_msb_w0_scanin[7:0]), 
		.scan_out			(dff_msb_w0_scanout[7:0]), 
		.l1clk				(l1clk_out_pm), 
		.din				({dcache_rdata_w0_m[63],
		dcache_rdata_w0_m[55], dcache_rdata_w0_m[47],
		dcache_rdata_w0_m[39], dcache_rdata_w0_m[31],
		dcache_rdata_w0_m[23], dcache_rdata_w0_m[15],
		dcache_rdata_w0_m[7]}), 
		.dout				(dcache_rdata_msb_w0_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_msb_w1(
		.scan_in			(dff_msb_w1_scanin[7:0]), 
		.scan_out			(dff_msb_w1_scanout[7:0]), 
		.l1clk				(l1clk_out_pm), 
		.din				({dcache_rdata_w1_m[63],
		dcache_rdata_w1_m[55], dcache_rdata_w1_m[47],
		dcache_rdata_w1_m[39], dcache_rdata_w1_m[31],
		dcache_rdata_w1_m[23], dcache_rdata_w1_m[15],
		dcache_rdata_w1_m[7]}), 
		.dout				(dcache_rdata_msb_w1_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_msb_w2(
		.scan_in			(dff_msb_w2_scanin[7:0]), 
		.scan_out			(dff_msb_w2_scanout[7:0]), 
		.l1clk				(l1clk_out_pm), 
		.din				({dcache_rdata_w2_m[63],
		dcache_rdata_w2_m[55], dcache_rdata_w2_m[47],
		dcache_rdata_w2_m[39], dcache_rdata_w2_m[31],
		dcache_rdata_w2_m[23], dcache_rdata_w2_m[15],
		dcache_rdata_w2_m[7]}), 
		.dout				(dcache_rdata_msb_w2_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_msb_w3(
		.scan_in			(dff_msb_w3_scanin[7:0]), 
		.scan_out			(dff_msb_w3_scanout[7:0]), 
		.l1clk				(l1clk_out_pm), 
		.din				({dcache_rdata_w3_m[63],
		dcache_rdata_w3_m[55], dcache_rdata_w3_m[47],
		dcache_rdata_w3_m[39], dcache_rdata_w3_m[31],
		dcache_rdata_w3_m[23], dcache_rdata_w3_m[15],
		dcache_rdata_w3_m[7]}), 
		.dout				(dcache_rdata_msb_w3_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_64 dff_rdata_w0_m(
		.scan_in			(dff_rdata_w0_m_scanin[63:0]), 
		.scan_out			(dff_rdata_w0_m_scanout[63:0]), 
		.l1clk				(l1clk_out_pm), 
		.din				(rdata_w0_m[63:0]), 
		.dout				(rdata_w0_b[63:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_rparity_w0_m(
		.scan_in			(dff_rparity_w0_m_scanin[7:0]), 
		.scan_out			(dff_rparity_w0_m_scanout[7:0]),
		.l1clk				(l1clk_out_pm), 
		.din				(rparity_w0_m[7:0]), 
		.dout				(rparity_w0_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_64 dff_rdata_w1_m(
		.scan_in			(dff_rdata_w1_m_scanin[63:0]), 
		.scan_out			(dff_rdata_w1_m_scanout[63:0]), 
		.l1clk				(l1clk_out_pm), 
		.din				(rdata_w1_m[63:0]), 
		.dout				(rdata_w1_b[63:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_rparity_w1_m(
		.scan_in			(dff_rparity_w1_m_scanin[7:0]), 
		.scan_out			(dff_rparity_w1_m_scanout[7:0]),
		.l1clk				(l1clk_out_pm), 
		.din				(rparity_w1_m[7:0]), 
		.dout				(rparity_w1_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_64 dff_rdata_w2_m(
		.scan_in			(dff_rdata_w2_m_scanin[63:0]), 
		.scan_out			(dff_rdata_w2_m_scanout[63:0]), 
		.l1clk				(l1clk_out_pm), 
		.din				(rdata_w2_m[63:0]), 
		.dout				(rdata_w2_b[63:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_rparity_w2_m(
		.scan_in			(dff_rparity_w2_m_scanin[7:0]), 
		.scan_out			(dff_rparity_w2_m_scanout[7:0]),
		.l1clk				(l1clk_out_pm), 
		.din				(rparity_w2_m[7:0]), 
		.dout				(rparity_w2_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_64 dff_rdata_w3_m(
		.scan_in			(dff_rdata_w3_m_scanin[63:0]), 
		.scan_out			(dff_rdata_w3_m_scanout[63:0]), 
		.l1clk				(l1clk_out_pm), 
		.din				(rdata_w3_m[63:0]), 
		.dout				(rdata_w3_b[63:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_rparity_w3_m(
		.scan_in			(dff_rparity_w3_m_scanin[7:0]), 
		.scan_out			(dff_rparity_w3_m_scanout[7:0]),
		.l1clk				(l1clk_out_pm), 
		.din				(rparity_w3_m[7:0]), 
		.dout				(rparity_w3_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	mux_macro__mux_aope__ports_2__width_4 mx_sel_way(
		.din0				(dcache_alt_rsel_way_b[3:0]), 
		.din1				(dcache_rsel_way_b[3:0]), 
		.sel0				(dcache_alt_way_sel_b), 
		.dout				(dcache_rd_sel_way_b[3:0]));
	mux_macro__mux_aonpe__ports_4__width_64 mx_rdata_b(
		.din0				(rdata_w0_b[63:0]), 
		.din1				(rdata_w1_b[63:0]), 
		.din2				(rdata_w2_b[63:0]), 
		.din3				(rdata_w3_b[63:0]), 
		.sel0				(dcache_rd_sel_way_b[0]), 
		.sel1				(dcache_rd_sel_way_b[1]), 
		.sel2				(dcache_rd_sel_way_b[2]), 
		.sel3				(dcache_rd_sel_way_b[3]), 
		.dout				(dcache_rdata_b[63:0]));
	mux_macro__mux_aonpe__ports_4__width_8 mx_rparity_b(
		.din0				(rparity_w0_b[7:0]), 
		.din1				(rparity_w1_b[7:0]), 
		.din2				(rparity_w2_b[7:0]), 
		.din3				(rparity_w3_b[7:0]), 
		.sel0				(dcache_rd_sel_way_b[0]), 
		.sel1				(dcache_rd_sel_way_b[1]), 
		.sel2				(dcache_rd_sel_way_b[2]), 
		.sel3				(dcache_rd_sel_way_b[3]), 
		.dout				(dcache_rparity_b[7:0]));
	xor_macro__ports_3__width_4 w0_par0(
		.din0				({dcache_rdata_w0_m[0],
		dcache_rdata_w0_m[3], dcache_rdata_w0_m[6], w0_p0_0}), 
		.din1				({dcache_rdata_w0_m[1],
		dcache_rdata_w0_m[4], dcache_rdata_w0_m[7], w0_p0_1}), 
		.din2				({dcache_rdata_w0_m[2],
		dcache_rdata_w0_m[5], rparity_w0_m[0], w0_p0_2}), 
		.dout				({w0_p0_0, w0_p0_1, w0_p0_2,
		w0_parity_m[0]}));
	xor_macro__ports_3__width_4 w0_par1(
		.din0				({dcache_rdata_w0_m[8],
		dcache_rdata_w0_m[11], dcache_rdata_w0_m[14], w0_p1_0}), 
		.din1				({dcache_rdata_w0_m[9],
		dcache_rdata_w0_m[12], dcache_rdata_w0_m[15], w0_p1_1}), 
		.din2				({dcache_rdata_w0_m[10],
		dcache_rdata_w0_m[13], rparity_w0_m[1], w0_p1_2}), 
		.dout				({w0_p1_0, w0_p1_1, w0_p1_2,
		w0_parity_m[1]}));
	xor_macro__ports_3__width_4 w0_par2(
		.din0				({dcache_rdata_w0_m[16],
		dcache_rdata_w0_m[19], dcache_rdata_w0_m[22], w0_p2_0}), 
		.din1				({dcache_rdata_w0_m[17],
		dcache_rdata_w0_m[20], dcache_rdata_w0_m[23], w0_p2_1}), 
		.din2				({dcache_rdata_w0_m[18],
		dcache_rdata_w0_m[21], rparity_w0_m[2], w0_p2_2}), 
		.dout				({w0_p2_0, w0_p2_1, w0_p2_2,
		w0_parity_m[2]}));
	xor_macro__ports_3__width_4 w0_par3(
		.din0				({dcache_rdata_w0_m[24],
		dcache_rdata_w0_m[27], dcache_rdata_w0_m[30], w0_p3_0}), 
		.din1				({dcache_rdata_w0_m[25],
		dcache_rdata_w0_m[28], dcache_rdata_w0_m[31], w0_p3_1}), 
		.din2				({dcache_rdata_w0_m[26],
		dcache_rdata_w0_m[29], rparity_w0_m[3], w0_p3_2}), 
		.dout				({w0_p3_0, w0_p3_1, w0_p3_2,
		w0_parity_m[3]}));
	xor_macro__ports_3__width_4 w0_par4(
		.din0				({dcache_rdata_w0_m[32],
		dcache_rdata_w0_m[35], dcache_rdata_w0_m[38], w0_p4_0}), 
		.din1				({dcache_rdata_w0_m[33],
		dcache_rdata_w0_m[36], dcache_rdata_w0_m[39], w0_p4_1}), 
		.din2				({dcache_rdata_w0_m[34],
		dcache_rdata_w0_m[37], rparity_w0_m[4], w0_p4_2}), 
		.dout				({w0_p4_0, w0_p4_1, w0_p4_2,
		w0_parity_m[4]}));
	xor_macro__ports_3__width_4 w0_par5(
		.din0				({dcache_rdata_w0_m[40],
		dcache_rdata_w0_m[43], dcache_rdata_w0_m[46], w0_p5_0}), 
		.din1				({dcache_rdata_w0_m[41],
		dcache_rdata_w0_m[44], dcache_rdata_w0_m[47], w0_p5_1}), 
		.din2				({dcache_rdata_w0_m[42],
		dcache_rdata_w0_m[45], rparity_w0_m[5], w0_p5_2}), 
		.dout				({w0_p5_0, w0_p5_1, w0_p5_2,
		w0_parity_m[5]}));
	xor_macro__ports_3__width_4 w0_par6(
		.din0				({dcache_rdata_w0_m[48],
		dcache_rdata_w0_m[51], dcache_rdata_w0_m[54], w0_p6_0}), 
		.din1				({dcache_rdata_w0_m[49],
		dcache_rdata_w0_m[52], dcache_rdata_w0_m[55], w0_p6_1}), 
		.din2				({dcache_rdata_w0_m[50],
		dcache_rdata_w0_m[53], rparity_w0_m[6], w0_p6_2}), 
		.dout				({w0_p6_0, w0_p6_1, w0_p6_2,
		w0_parity_m[6]}));
	xor_macro__ports_3__width_4 w0_par7(
		.din0				({dcache_rdata_w0_m[56],
		dcache_rdata_w0_m[59], dcache_rdata_w0_m[62], w0_p7_0}), 
		.din1				({dcache_rdata_w0_m[57],
		dcache_rdata_w0_m[60], dcache_rdata_w0_m[63], w0_p7_1}), 
		.din2				({dcache_rdata_w0_m[58],
		dcache_rdata_w0_m[61], rparity_w0_m[7], w0_p7_2}), 
		.dout				({w0_p7_0, w0_p7_1, w0_p7_2,
		w0_parity_m[7]}));
	xor_macro__ports_3__width_4 w1_par0(
		.din0				({dcache_rdata_w1_m[0],
		dcache_rdata_w1_m[3], dcache_rdata_w1_m[6], w1_p0_0}), 
		.din1				({dcache_rdata_w1_m[1],
		dcache_rdata_w1_m[4], dcache_rdata_w1_m[7], w1_p0_1}), 
		.din2				({dcache_rdata_w1_m[2],
		dcache_rdata_w1_m[5], rparity_w1_m[0], w1_p0_2}), 
		.dout				({w1_p0_0, w1_p0_1, w1_p0_2,
		w1_parity_m[0]}));
	xor_macro__ports_3__width_4 w1_par1(
		.din0				({dcache_rdata_w1_m[8],
		dcache_rdata_w1_m[11], dcache_rdata_w1_m[14], w1_p1_0}), 
		.din1				({dcache_rdata_w1_m[9],
		dcache_rdata_w1_m[12], dcache_rdata_w1_m[15], w1_p1_1}), 
		.din2				({dcache_rdata_w1_m[10],
		dcache_rdata_w1_m[13], rparity_w1_m[1], w1_p1_2}), 
		.dout				({w1_p1_0, w1_p1_1, w1_p1_2,
		w1_parity_m[1]}));
	xor_macro__ports_3__width_4 w1_par2(
		.din0				({dcache_rdata_w1_m[16],
		dcache_rdata_w1_m[19], dcache_rdata_w1_m[22], w1_p2_0}), 
		.din1				({dcache_rdata_w1_m[17],
		dcache_rdata_w1_m[20], dcache_rdata_w1_m[23], w1_p2_1}), 
		.din2				({dcache_rdata_w1_m[18],
		dcache_rdata_w1_m[21], rparity_w1_m[2], w1_p2_2}), 
		.dout				({w1_p2_0, w1_p2_1, w1_p2_2,
		w1_parity_m[2]}));
	xor_macro__ports_3__width_4 w1_par3(
		.din0				({dcache_rdata_w1_m[24],
		dcache_rdata_w1_m[27], dcache_rdata_w1_m[30], w1_p3_0}), 
		.din1				({dcache_rdata_w1_m[25],
		dcache_rdata_w1_m[28], dcache_rdata_w1_m[31], w1_p3_1}), 
		.din2				({dcache_rdata_w1_m[26],
		dcache_rdata_w1_m[29], rparity_w1_m[3], w1_p3_2}), 
		.dout				({w1_p3_0, w1_p3_1, w1_p3_2,
		w1_parity_m[3]}));
	xor_macro__ports_3__width_4 w1_par4(
		.din0				({dcache_rdata_w1_m[32],
		dcache_rdata_w1_m[35], dcache_rdata_w1_m[38], w1_p4_0}), 
		.din1				({dcache_rdata_w1_m[33],
		dcache_rdata_w1_m[36], dcache_rdata_w1_m[39], w1_p4_1}), 
		.din2				({dcache_rdata_w1_m[34],
		dcache_rdata_w1_m[37], rparity_w1_m[4], w1_p4_2}), 
		.dout				({w1_p4_0, w1_p4_1, w1_p4_2,
		w1_parity_m[4]}));
	xor_macro__ports_3__width_4 w1_par5(
		.din0				({dcache_rdata_w1_m[40],
		dcache_rdata_w1_m[43], dcache_rdata_w1_m[46], w1_p5_0}), 
		.din1				({dcache_rdata_w1_m[41],
		dcache_rdata_w1_m[44], dcache_rdata_w1_m[47], w1_p5_1}), 
		.din2				({dcache_rdata_w1_m[42],
		dcache_rdata_w1_m[45], rparity_w1_m[5], w1_p5_2}), 
		.dout				({w1_p5_0, w1_p5_1, w1_p5_2,
		w1_parity_m[5]}));
	xor_macro__ports_3__width_4 w1_par6(
		.din0				({dcache_rdata_w1_m[48],
		dcache_rdata_w1_m[51], dcache_rdata_w1_m[54], w1_p6_0}), 
		.din1				({dcache_rdata_w1_m[49],
		dcache_rdata_w1_m[52], dcache_rdata_w1_m[55], w1_p6_1}), 
		.din2				({dcache_rdata_w1_m[50],
		dcache_rdata_w1_m[53], rparity_w1_m[6], w1_p6_2}), 
		.dout				({w1_p6_0, w1_p6_1, w1_p6_2,
		w1_parity_m[6]}));
	xor_macro__ports_3__width_4 w1_par7(
		.din0				({dcache_rdata_w1_m[56],
		dcache_rdata_w1_m[59], dcache_rdata_w1_m[62], w1_p7_0}), 
		.din1				({dcache_rdata_w1_m[57],
		dcache_rdata_w1_m[60], dcache_rdata_w1_m[63], w1_p7_1}), 
		.din2				({dcache_rdata_w1_m[58],
		dcache_rdata_w1_m[61], rparity_w1_m[7], w1_p7_2}), 
		.dout				({w1_p7_0, w1_p7_1, w1_p7_2,
		w1_parity_m[7]}));
	xor_macro__ports_3__width_4 w2_par0(
		.din0				({dcache_rdata_w2_m[0],
		dcache_rdata_w2_m[3], dcache_rdata_w2_m[6], w2_p0_0}), 
		.din1				({dcache_rdata_w2_m[1],
		dcache_rdata_w2_m[4], dcache_rdata_w2_m[7], w2_p0_1}), 
		.din2				({dcache_rdata_w2_m[2],
		dcache_rdata_w2_m[5], rparity_w2_m[0], w2_p0_2}), 
		.dout				({w2_p0_0, w2_p0_1, w2_p0_2,
		w2_parity_m[0]}));
	xor_macro__ports_3__width_4 w2_par1(
		.din0				({dcache_rdata_w2_m[8],
		dcache_rdata_w2_m[11], dcache_rdata_w2_m[14], w2_p1_0}), 
		.din1				({dcache_rdata_w2_m[9],
		dcache_rdata_w2_m[12], dcache_rdata_w2_m[15], w2_p1_1}), 
		.din2				({dcache_rdata_w2_m[10],
		dcache_rdata_w2_m[13], rparity_w2_m[1], w2_p1_2}), 
		.dout				({w2_p1_0, w2_p1_1, w2_p1_2,
		w2_parity_m[1]}));
	xor_macro__ports_3__width_4 w2_par2(
		.din0				({dcache_rdata_w2_m[16],
		dcache_rdata_w2_m[19], dcache_rdata_w2_m[22], w2_p2_0}), 
		.din1				({dcache_rdata_w2_m[17],
		dcache_rdata_w2_m[20], dcache_rdata_w2_m[23], w2_p2_1}), 
		.din2				({dcache_rdata_w2_m[18],
		dcache_rdata_w2_m[21], rparity_w2_m[2], w2_p2_2}), 
		.dout				({w2_p2_0, w2_p2_1, w2_p2_2,
		w2_parity_m[2]}));
	xor_macro__ports_3__width_4 w2_par3(
		.din0				({dcache_rdata_w2_m[24],
		dcache_rdata_w2_m[27], dcache_rdata_w2_m[30], w2_p3_0}), 
		.din1				({dcache_rdata_w2_m[25],
		dcache_rdata_w2_m[28], dcache_rdata_w2_m[31], w2_p3_1}), 
		.din2				({dcache_rdata_w2_m[26],
		dcache_rdata_w2_m[29], rparity_w2_m[3], w2_p3_2}), 
		.dout				({w2_p3_0, w2_p3_1, w2_p3_2,
		w2_parity_m[3]}));
	xor_macro__ports_3__width_4 w2_par4(
		.din0				({dcache_rdata_w2_m[32],
		dcache_rdata_w2_m[35], dcache_rdata_w2_m[38], w2_p4_0}), 
		.din1				({dcache_rdata_w2_m[33],
		dcache_rdata_w2_m[36], dcache_rdata_w2_m[39], w2_p4_1}), 
		.din2				({dcache_rdata_w2_m[34],
		dcache_rdata_w2_m[37], rparity_w2_m[4], w2_p4_2}), 
		.dout				({w2_p4_0, w2_p4_1, w2_p4_2,
		w2_parity_m[4]}));
	xor_macro__ports_3__width_4 w2_par5(
		.din0				({dcache_rdata_w2_m[40],
		dcache_rdata_w2_m[43], dcache_rdata_w2_m[46], w2_p5_0}), 
		.din1				({dcache_rdata_w2_m[41],
		dcache_rdata_w2_m[44], dcache_rdata_w2_m[47], w2_p5_1}), 
		.din2				({dcache_rdata_w2_m[42],
		dcache_rdata_w2_m[45], rparity_w2_m[5], w2_p5_2}), 
		.dout				({w2_p5_0, w2_p5_1, w2_p5_2,
		w2_parity_m[5]}));
	xor_macro__ports_3__width_4 w2_par6(
		.din0				({dcache_rdata_w2_m[48],
		dcache_rdata_w2_m[51], dcache_rdata_w2_m[54], w2_p6_0}), 
		.din1				({dcache_rdata_w2_m[49],
		dcache_rdata_w2_m[52], dcache_rdata_w2_m[55], w2_p6_1}), 
		.din2				({dcache_rdata_w2_m[50],
		dcache_rdata_w2_m[53], rparity_w2_m[6], w2_p6_2}), 
		.dout				({w2_p6_0, w2_p6_1, w2_p6_2,
		w2_parity_m[6]}));
	xor_macro__ports_3__width_4 w2_par7(
		.din0				({dcache_rdata_w2_m[56],
		dcache_rdata_w2_m[59], dcache_rdata_w2_m[62], w2_p7_0}), 
		.din1				({dcache_rdata_w2_m[57],
		dcache_rdata_w2_m[60], dcache_rdata_w2_m[63], w2_p7_1}), 
		.din2				({dcache_rdata_w2_m[58],
		dcache_rdata_w2_m[61], rparity_w2_m[7], w2_p7_2}), 
		.dout				({w2_p7_0, w2_p7_1, w2_p7_2,
		w2_parity_m[7]}));
	xor_macro__ports_3__width_4 w3_par0(
		.din0				({dcache_rdata_w3_m[0],
		dcache_rdata_w3_m[3], dcache_rdata_w3_m[6], w3_p0_0}), 
		.din1				({dcache_rdata_w3_m[1],
		dcache_rdata_w3_m[4], dcache_rdata_w3_m[7], w3_p0_1}), 
		.din2				({dcache_rdata_w3_m[2],
		dcache_rdata_w3_m[5], rparity_w3_m[0], w3_p0_2}), 
		.dout				({w3_p0_0, w3_p0_1, w3_p0_2,
		w3_parity_m[0]}));
	xor_macro__ports_3__width_4 w3_par1(
		.din0				({dcache_rdata_w3_m[8],
		dcache_rdata_w3_m[11], dcache_rdata_w3_m[14], w3_p1_0}), 
		.din1				({dcache_rdata_w3_m[9],
		dcache_rdata_w3_m[12], dcache_rdata_w3_m[15], w3_p1_1}), 
		.din2				({dcache_rdata_w3_m[10],
		dcache_rdata_w3_m[13], rparity_w3_m[1], w3_p1_2}), 
		.dout				({w3_p1_0, w3_p1_1, w3_p1_2,
		w3_parity_m[1]}));
	xor_macro__ports_3__width_4 w3_par2(
		.din0				({dcache_rdata_w3_m[16],
		dcache_rdata_w3_m[19], dcache_rdata_w3_m[22], w3_p2_0}), 
		.din1				({dcache_rdata_w3_m[17],
		dcache_rdata_w3_m[20], dcache_rdata_w3_m[23], w3_p2_1}), 
		.din2				({dcache_rdata_w3_m[18],
		dcache_rdata_w3_m[21], rparity_w3_m[2], w3_p2_2}), 
		.dout				({w3_p2_0, w3_p2_1, w3_p2_2,
		w3_parity_m[2]}));
	xor_macro__ports_3__width_4 w3_par3(
		.din0				({dcache_rdata_w3_m[24],
		dcache_rdata_w3_m[27], dcache_rdata_w3_m[30], w3_p3_0}), 
		.din1				({dcache_rdata_w3_m[25],
		dcache_rdata_w3_m[28], dcache_rdata_w3_m[31], w3_p3_1}), 
		.din2				({dcache_rdata_w3_m[26],
		dcache_rdata_w3_m[29], rparity_w3_m[3], w3_p3_2}), 
		.dout				({w3_p3_0, w3_p3_1, w3_p3_2,
		w3_parity_m[3]}));
	xor_macro__ports_3__width_4 w3_par4(
		.din0				({dcache_rdata_w3_m[32],
		dcache_rdata_w3_m[35], dcache_rdata_w3_m[38], w3_p4_0}), 
		.din1				({dcache_rdata_w3_m[33],
		dcache_rdata_w3_m[36], dcache_rdata_w3_m[39], w3_p4_1}), 
		.din2				({dcache_rdata_w3_m[34],
		dcache_rdata_w3_m[37], rparity_w3_m[4], w3_p4_2}), 
		.dout				({w3_p4_0, w3_p4_1, w3_p4_2,
		w3_parity_m[4]}));
	xor_macro__ports_3__width_4 w3_par5(
		.din0				({dcache_rdata_w3_m[40],
		dcache_rdata_w3_m[43], dcache_rdata_w3_m[46], w3_p5_0}), 
		.din1				({dcache_rdata_w3_m[41],
		dcache_rdata_w3_m[44], dcache_rdata_w3_m[47], w3_p5_1}), 
		.din2				({dcache_rdata_w3_m[42],
		dcache_rdata_w3_m[45], rparity_w3_m[5], w3_p5_2}), 
		.dout				({w3_p5_0, w3_p5_1, w3_p5_2,
		w3_parity_m[5]}));
	xor_macro__ports_3__width_4 w3_par6(
		.din0				({dcache_rdata_w3_m[48],
		dcache_rdata_w3_m[51], dcache_rdata_w3_m[54], w3_p6_0}), 
		.din1				({dcache_rdata_w3_m[49],
		dcache_rdata_w3_m[52], dcache_rdata_w3_m[55], w3_p6_1}), 
		.din2				({dcache_rdata_w3_m[50],
		dcache_rdata_w3_m[53], rparity_w3_m[6], w3_p6_2}), 
		.dout				({w3_p6_0, w3_p6_1, w3_p6_2,
		w3_parity_m[6]}));
	xor_macro__ports_3__width_4 w3_par7(
		.din0				({dcache_rdata_w3_m[56],
		dcache_rdata_w3_m[59], dcache_rdata_w3_m[62], w3_p7_0}), 
		.din1				({dcache_rdata_w3_m[57],
		dcache_rdata_w3_m[60], dcache_rdata_w3_m[63], w3_p7_1}), 
		.din2				({dcache_rdata_w3_m[58],
		dcache_rdata_w3_m[61], rparity_w3_m[7], w3_p7_2}), 
		.dout				({w3_p7_0, w3_p7_1, w3_p7_2,
		w3_parity_m[7]}));
	msff_ctl_macro__fs_1__width_8 dff_byte_perr_w0(
		.scan_in			(dff_byte_perr_w0_scanin[7:0]), 
		.scan_out			(dff_byte_perr_w0_scanout[7:0]),
		.l1clk				(l1clk_out_pm), 
		.din				(w0_parity_m[7:0]), 
		.dout				(w0_parity_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_byte_perr_w1(
		.scan_in			(dff_byte_perr_w1_scanin[7:0]), 
		.scan_out			(dff_byte_perr_w1_scanout[7:0]),
		.l1clk				(l1clk_out_pm), 
		.din				(w1_parity_m[7:0]), 
		.dout				(w1_parity_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_byte_perr_w2(
		.scan_in			(dff_byte_perr_w2_scanin[7:0]), 
		.scan_out			(dff_byte_perr_w2_scanout[7:0]),
		.l1clk				(l1clk_out_pm), 
		.din				(w2_parity_m[7:0]), 
		.dout				(w2_parity_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_byte_perr_w3(
		.scan_in			(dff_byte_perr_w3_scanin[7:0]), 
		.scan_out			(dff_byte_perr_w3_scanout[7:0]),
		.l1clk				(l1clk_out_pm), 
		.din				(w3_parity_m[7:0]), 
		.dout				(w3_parity_b[7:0]), 
		.siclk				(siclk), 
		.soclk				(soclk));
	mux_macro__mux_aonpe__ports_8__width_1 parity_w0(
		.din0				(1'b1), 
		.din1				(1'b1), 
		.din2				(1'b1), 
		.din3				(1'b1), 
		.din4				(1'b1), 
		.din5				(1'b1), 
		.din6				(1'b1), 
		.din7				(1'b1), 
		.sel0				(w0_parity_b[0]), 
		.sel1				(w0_parity_b[1]), 
		.sel2				(w0_parity_b[2]), 
		.sel3				(w0_parity_b[3]), 
		.sel4				(w0_parity_b[4]), 
		.sel5				(w0_parity_b[5]), 
		.sel6				(w0_parity_b[6]), 
		.sel7				(w0_parity_b[7]), 
		.dout				(w0_parity_err_b));
	mux_macro__mux_aonpe__ports_8__width_1 parity_w1(
		.din0				(1'b1), 
		.din1				(1'b1), 
		.din2				(1'b1), 
		.din3				(1'b1), 
		.din4				(1'b1), 
		.din5				(1'b1), 
		.din6				(1'b1), 
		.din7				(1'b1), 
		.sel0				(w1_parity_b[0]), 
		.sel1				(w1_parity_b[1]), 
		.sel2				(w1_parity_b[2]), 
		.sel3				(w1_parity_b[3]), 
		.sel4				(w1_parity_b[4]), 
		.sel5				(w1_parity_b[5]), 
		.sel6				(w1_parity_b[6]), 
		.sel7				(w1_parity_b[7]), 
		.dout				(w1_parity_err_b));
	mux_macro__mux_aonpe__ports_8__width_1 parity_w2(
		.din0				(1'b1), 
		.din1				(1'b1), 
		.din2				(1'b1), 
		.din3				(1'b1), 
		.din4				(1'b1), 
		.din5				(1'b1), 
		.din6				(1'b1), 
		.din7				(1'b1), 
		.sel0				(w2_parity_b[0]), 
		.sel1				(w2_parity_b[1]), 
		.sel2				(w2_parity_b[2]), 
		.sel3				(w2_parity_b[3]), 
		.sel4				(w2_parity_b[4]), 
		.sel5				(w2_parity_b[5]), 
		.sel6				(w2_parity_b[6]), 
		.sel7				(w2_parity_b[7]), 
		.dout				(w2_parity_err_b));
	mux_macro__mux_aonpe__ports_8__width_1 parity_w3(
		.din0				(1'b1), 
		.din1				(1'b1), 
		.din2				(1'b1), 
		.din3				(1'b1), 
		.din4				(1'b1), 
		.din5				(1'b1), 
		.din6				(1'b1), 
		.din7				(1'b1), 
		.sel0				(w3_parity_b[0]), 
		.sel1				(w3_parity_b[1]), 
		.sel2				(w3_parity_b[2]), 
		.sel3				(w3_parity_b[3]), 
		.sel4				(w3_parity_b[4]), 
		.sel5				(w3_parity_b[5]), 
		.sel6				(w3_parity_b[6]), 
		.sel7				(w3_parity_b[7]), 
		.dout				(w3_parity_err_b));
	msff_ctl_macro__fs_1__width_12 dff_red_in(
		.scan_in			(dff_red_in_scanin[11:0]), 
		.scan_out			(dff_red_in_scanout[11:0]), 
		.l1clk				(l1clk_in), 
		.din				({fuse_dca_repair_value[5:0],
		fuse_dca_repair_en[1:0], fuse_dca_rid[1:0], fuse_dca_wen,
		fuse_red_reset}), 
		.dout				({fuse_dca_repair_value_ff[5:0],
		fuse_dca_repair_en_ff[1:0], fuse_dca_rid_ff[1:0],
		fuse_dca_wen_ff, fuse_red_reset_ff}), 
		.siclk				(siclk), 
		.soclk				(soclk));
	msff_ctl_macro__fs_1__width_8 dff_red_out(
		.scan_in			(dff_red_out_scanin[7:0]), 
		.scan_out			(dff_red_out_scanout[7:0]), 
		.l1clk				(l1clk_out), 
		.din				
		({dca_fuse_repair_value_pre[5:0], dca_fuse_repair_en_pre[1:0]}),
		.dout				({dca_fuse_repair_value[5:0],
		dca_fuse_repair_en[1:0]}), 
		.siclk				(siclk), 
		.soclk				(soclk));
endmodule

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 36871 */
// No timescale specified
module mux_macro__mux_aonpe__ports_4__width_64(din0, sel0, din1, sel1, din2, 
	sel2, din3, sel3, dout);

	input	[63:0]		din0;
	input			sel0;
	input	[63:0]		din1;
	input			sel1;
	input	[63:0]		din2;
	input			sel2;
	input	[63:0]		din3;
	input			sel3;
	output	[63:0]		dout;

	wire			buffout0;
	wire			buffout1;
	wire			buffout2;
	wire			buffout3;

	cl_dp1_muxbuff4_8x c0_0(
		.in0				(sel0), 
		.in1				(sel1), 
		.in2				(sel2), 
		.in3				(sel3), 
		.out0				(buffout0), 
		.out1				(buffout1), 
		.out2				(buffout2), 
		.out3				(buffout3));
	mux4s #(64) d0_0(
		.sel0				(buffout0), 
		.sel1				(buffout1), 
		.sel2				(buffout2), 
		.sel3				(buffout3), 
		.in0				(din0[63:0]), 
		.in1				(din1[63:0]), 
		.in2				(din2[63:0]), 
		.in3				(din3[63:0]), 
		.dout				(dout[63:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 40507 */
// No timescale specified
module msff_ctl_macro__fs_1__width_64(din, l1clk, scan_in, siclk, soclk, dout, 
	scan_out);

	input	[63:0]		din;
	input			l1clk;
	input	[63:0]		scan_in;
	input			siclk;
	input			soclk;
	output	[63:0]		dout;
	output	[63:0]		scan_out;

	wire	[63:0]		fdin;

	assign fdin[63:0] = din[63:0];

	dff #(64) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.d				(fdin[63:0]), 
		.si				(scan_in[63:0]), 
		.so				(scan_out[63:0]), 
		.q				(dout[63:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 58446 */
// No timescale specified
module msff_ctl_macro__fs_1__width_5(din, l1clk, scan_in, siclk, soclk, dout, 
	scan_out);

	input	[4:0]		din;
	input			l1clk;
	input	[4:0]		scan_in;
	input			siclk;
	input			soclk;
	output	[4:0]		dout;
	output	[4:0]		scan_out;

	wire	[4:0]		fdin;

	assign fdin[4:0] = din[4:0];

	dff #(5) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.d				(fdin[4:0]), 
		.si				(scan_in[4:0]), 
		.so				(scan_out[4:0]), 
		.q				(dout[4:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 58527 */
// No timescale specified
module msff_ctl_macro__fs_1__width_8(din, l1clk, scan_in, siclk, soclk, dout, 
	scan_out);

	input	[7:0]		din;
	input			l1clk;
	input	[7:0]		scan_in;
	input			siclk;
	input			soclk;
	output	[7:0]		dout;
	output	[7:0]		scan_out;

	wire	[7:0]		fdin;

	assign fdin[7:0] = din[7:0];

	dff #(8) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.d				(fdin[7:0]), 
		.si				(scan_in[7:0]), 
		.so				(scan_out[7:0]), 
		.q				(dout[7:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 61614 */
// No timescale specified
module msff_ctl_macro__fs_1__width_3(din, l1clk, scan_in, siclk, soclk, dout, 
	scan_out);

	input	[2:0]		din;
	input			l1clk;
	input	[2:0]		scan_in;
	input			siclk;
	input			soclk;
	output	[2:0]		dout;
	output	[2:0]		scan_out;

	wire	[2:0]		fdin;

	assign fdin[2:0] = din[2:0];

	dff #(3) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.d				(fdin[2:0]), 
		.si				(scan_in[2:0]), 
		.so				(scan_out[2:0]), 
		.q				(dout[2:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 62461 */
// No timescale specified
module mux_macro__mux_aonpe__ports_8__width_1(din0, sel0, din1, sel1, din2, 
	sel2, din3, sel3, din4, sel4, din5, sel5, din6, sel6, din7, sel7, dout);

	input	[0:0]		din0;
	input			sel0;
	input	[0:0]		din1;
	input			sel1;
	input	[0:0]		din2;
	input			sel2;
	input	[0:0]		din3;
	input			sel3;
	input	[0:0]		din4;
	input			sel4;
	input	[0:0]		din5;
	input			sel5;
	input	[0:0]		din6;
	input			sel6;
	input	[0:0]		din7;
	input			sel7;
	output	[0:0]		dout;

	wire			buffout0;
	wire			buffout1;
	wire			buffout2;
	wire			buffout3;
	wire			buffout4;
	wire			buffout5;
	wire			buffout6;
	wire			buffout7;

	cl_dp1_muxbuff8_8x c0_0(
		.in0				(sel0), 
		.in1				(sel1), 
		.in2				(sel2), 
		.in3				(sel3), 
		.in4				(sel4), 
		.in5				(sel5), 
		.in6				(sel6), 
		.in7				(sel7), 
		.out0				(buffout0), 
		.out1				(buffout1), 
		.out2				(buffout2), 
		.out3				(buffout3), 
		.out4				(buffout4), 
		.out5				(buffout5), 
		.out6				(buffout6), 
		.out7				(buffout7));
	mux8s #(1) d0_0(
		.sel0				(buffout0), 
		.sel1				(buffout1), 
		.sel2				(buffout2), 
		.sel3				(buffout3), 
		.sel4				(buffout4), 
		.sel5				(buffout5), 
		.sel6				(buffout6), 
		.sel7				(buffout7), 
		.in0				(din0[0]), 
		.in1				(din1[0]), 
		.in2				(din2[0]), 
		.in3				(din3[0]), 
		.in4				(din4[0]), 
		.in5				(din5[0]), 
		.in6				(din6[0]), 
		.in7				(din7[0]), 
		.dout				(dout[0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129372 */
// No timescale specified
module mux_macro__mux_aope__ports_2__width_8(din0, din1, sel0, dout);

	input	[7:0]		din0;
	input	[7:0]		din1;
	input			sel0;
	output	[7:0]		dout;

	wire			psel0;
	wire			psel1;

	cl_dp1_penc2_8x c0_0(
		.sel0				(sel0), 
		.psel0				(psel0), 
		.psel1				(psel1));
	mux2s #(8) d0_0(
		.sel0				(psel0), 
		.sel1				(psel1), 
		.in0				(din0[7:0]), 
		.in1				(din1[7:0]), 
		.dout				(dout[7:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129421 */
// No timescale specified
module mux_macro__mux_aodec__ports_4__width_4(din0, din1, din2, din3, sel, dout)
	;

	input	[3:0]		din0;
	input	[3:0]		din1;
	input	[3:0]		din2;
	input	[3:0]		din3;
	input	[1:0]		sel;
	output	[3:0]		dout;

	wire			psel0;
	wire			psel1;
	wire			psel2;
	wire			psel3;

	cl_dp1_pdec4_8x c0_0(
		.test				(1'b1), 
		.sel0				(sel[0]), 
		.sel1				(sel[1]), 
		.psel0				(psel0), 
		.psel1				(psel1), 
		.psel2				(psel2), 
		.psel3				(psel3));
	mux4s #(4) d0_0(
		.sel0				(psel0), 
		.sel1				(psel1), 
		.sel2				(psel2), 
		.sel3				(psel3), 
		.in0				(din0[3:0]), 
		.in1				(din1[3:0]), 
		.in2				(din2[3:0]), 
		.in3				(din3[3:0]), 
		.dout				(dout[3:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129458 */
// No timescale specified
module tisram_msff_macro__fs_1__width_7(d, scan_in, l1clk, siclk, soclk, 
	scan_out, latout, latout_l);

	input	[6:0]		d;
	input	[6:0]		scan_in;
	input			l1clk;
	input			siclk;
	input			soclk;
	output	[6:0]		scan_out;
	output	[6:0]		latout;
	output	[6:0]		latout_l;

	tisram_msff #(7) d0_0(
		.d				(d[6:0]), 
		.si				(scan_in[6:0]), 
		.so				(scan_out[6:0]), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.latout				(latout[6:0]), 
		.latout_l			(latout_l[6:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129483 */
// No timescale specified
module tisram_msff_macro__fs_1__width_16(d, scan_in, l1clk, siclk, soclk, 
	scan_out, latout, latout_l);

	input	[15:0]		d;
	input	[15:0]		scan_in;
	input			l1clk;
	input			siclk;
	input			soclk;
	output	[15:0]		scan_out;
	output	[15:0]		latout;
	output	[15:0]		latout_l;

	tisram_msff #(16) d0_0(
		.d				(d[15:0]), 
		.si				(scan_in[15:0]), 
		.so				(scan_out[15:0]), 
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.latout				(latout[15:0]), 
		.latout_l			(latout_l[15:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129508 */
// No timescale specified
module msff_ctl_macro__fs_1__width_144(din, l1clk, scan_in, siclk, soclk, dout, 
	scan_out);

	input	[143:0]		din;
	input			l1clk;
	input	[143:0]		scan_in;
	input			siclk;
	input			soclk;
	output	[143:0]		dout;
	output	[143:0]		scan_out;

	wire	[143:0]		fdin;

	assign fdin[143:0] = din[143:0];

	dff #(144) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.d				(fdin[143:0]), 
		.si				(scan_in[143:0]), 
		.so				(scan_out[143:0]), 
		.q				(dout[143:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129535 */
// No timescale specified
module n2_dca_sp_9kb_array(l1clk, l1clk_wr, l1clk_red, rd_en_top_b, rd_en_bot_b,
	rd_en_a, wr_en_a, wr_en_b, wr_inh_b, addr_b, byte_wr_en_b, wr_waysel_b, 
	dcache_wdata_m, dcache_wparity_m, dcache_rdata_w0_m, rparity_w0_m, 
	dcache_rdata_w1_m, rparity_w1_m, dcache_rdata_w2_m, rparity_w2_m, 
	dcache_rdata_w3_m, rparity_w3_m, fuse_dca_repair_value, 
	fuse_dca_repair_en, fuse_dca_rid, fuse_dca_wen, fuse_red_reset, 
	dca_fuse_repair_value, dca_fuse_repair_en, vnw_ary);

	input			l1clk;
	input			l1clk_wr;
	input			l1clk_red;
	input			rd_en_top_b;
	input			rd_en_bot_b;
	input			rd_en_a;
	input			wr_en_a;
	input			wr_en_b;
	input			wr_inh_b;
	input	[10:3]		addr_b;
	input	[15:0]		byte_wr_en_b;
	input	[3:0]		wr_waysel_b;
	input	[127:0]		dcache_wdata_m;
	input	[15:0]		dcache_wparity_m;
	output	[63:0]		dcache_rdata_w0_m;
	output	[7:0]		rparity_w0_m;
	output	[63:0]		dcache_rdata_w1_m;
	output	[7:0]		rparity_w1_m;
	output	[63:0]		dcache_rdata_w2_m;
	output	[7:0]		rparity_w2_m;
	output	[63:0]		dcache_rdata_w3_m;
	output	[7:0]		rparity_w3_m;
	input	[5:0]		fuse_dca_repair_value;
	input	[1:0]		fuse_dca_repair_en;
	input	[1:0]		fuse_dca_rid;
	input			fuse_dca_wen;
	input			fuse_red_reset;
	output	[5:0]		dca_fuse_repair_value;
	output	[1:0]		dca_fuse_repair_en;
	input			vnw_ary;

	wire			fuse_red_reset_qual;
	wire			fuse_dca_wen_qual;
	wire	[3:0]		red_id;
	wire	[3:0]		red_reg_clk_;
	wire	[5:0]		red_data;
	wire	[1:0]		red_enable;
	wire	[8:0]		w0_byte7_l_unused;
	wire	[8:0]		w0_byte6_l_unused;
	wire	[8:0]		w0_byte5_l_unused;
	wire	[8:0]		w0_byte4_l_unused;
	wire	[8:0]		w0_byte3_l_unused;
	wire	[8:0]		w0_byte2_l_unused;
	wire	[8:0]		w0_byte1_l_unused;
	wire	[8:0]		w0_byte0_l_unused;
	wire	[8:0]		w1_byte7_l_unused;
	wire	[8:0]		w1_byte6_l_unused;
	wire	[8:0]		w1_byte5_l_unused;
	wire	[8:0]		w1_byte4_l_unused;
	wire	[8:0]		w1_byte3_l_unused;
	wire	[8:0]		w1_byte2_l_unused;
	wire	[8:0]		w1_byte1_l_unused;
	wire	[8:0]		w1_byte0_l_unused;
	wire	[8:0]		w2_byte7_l_unused;
	wire	[8:0]		w2_byte6_l_unused;
	wire	[8:0]		w2_byte5_l_unused;
	wire	[8:0]		w2_byte4_l_unused;
	wire	[8:0]		w2_byte3_l_unused;
	wire	[8:0]		w2_byte2_l_unused;
	wire	[8:0]		w2_byte1_l_unused;
	wire	[8:0]		w2_byte0_l_unused;
	wire	[8:0]		w3_byte7_l_unused;
	wire	[8:0]		w3_byte6_l_unused;
	wire	[8:0]		w3_byte5_l_unused;
	wire	[8:0]		w3_byte4_l_unused;
	wire	[8:0]		w3_byte3_l_unused;
	wire	[8:0]		w3_byte2_l_unused;
	wire	[8:0]		w3_byte1_l_unused;
	wire	[8:0]		w3_byte0_l_unused;
	reg	[5:0]		red_reg_d_bl;
	reg	[5:0]		red_reg_d_br;
	reg	[5:0]		red_reg_d_tl;
	reg	[5:0]		red_reg_d_tr;
	reg	[1:0]		red_reg_en_bl;
	reg	[1:0]		red_reg_en_br;
	reg	[1:0]		red_reg_en_tl;
	reg	[1:0]		red_reg_en_tr;
	supply0			vss;
	supply1			vdd;

	assign fuse_red_reset_qual = (fuse_red_reset & (~wr_inh_b));
	assign fuse_dca_wen_qual = (fuse_dca_wen & (~wr_inh_b));
	assign red_id[0] = ((~fuse_dca_rid[1]) & (~fuse_dca_rid[0]));
	assign red_id[1] = ((~fuse_dca_rid[1]) & fuse_dca_rid[0]);
	assign red_id[2] = (fuse_dca_rid[1] & (~fuse_dca_rid[0]));
	assign red_id[3] = (fuse_dca_rid[1] & fuse_dca_rid[0]);
	assign red_reg_clk_[0] = (~((~l1clk_red) & ((red_id[0] & 
		fuse_dca_wen_qual) | fuse_red_reset_qual)));
	assign red_reg_clk_[1] = (~((~l1clk_red) & ((red_id[1] & 
		fuse_dca_wen_qual) | fuse_red_reset_qual)));
	assign red_reg_clk_[2] = (~((~l1clk_red) & ((red_id[2] & 
		fuse_dca_wen_qual) | fuse_red_reset_qual)));
	assign red_reg_clk_[3] = (~((~l1clk_red) & ((red_id[3] & 
		fuse_dca_wen_qual) | fuse_red_reset_qual)));
	assign red_data[5:0] = (fuse_dca_repair_value[5:0] & {6 {
		(~fuse_red_reset_qual)}});
	assign red_enable[1:0] = (fuse_dca_repair_en[1:0] & {2 {
		(~fuse_red_reset_qual)}});
	assign dca_fuse_repair_value[5:0] = ((((red_reg_d_tr[5:0] & {6 {
		red_id[3]}}) | (red_reg_d_tl[5:0] & {6 {red_id[2]}})) | (
		red_reg_d_br[5:0] & {6 {red_id[1]}})) | (red_reg_d_bl[5:0] & {6 
		{red_id[0]}}));
	assign dca_fuse_repair_en[1:0] = ((((red_reg_en_tr[1:0] & {2 {red_id[3]}
		}) | (red_reg_en_tl[1:0] & {2 {red_id[2]}})) | (
		red_reg_en_br[1:0] & {2 {red_id[1]}})) | (red_reg_en_bl[1:0] & {
		2 {red_id[0]}}));

	n2_dca_sp_9kb_bank way01(
		.red_data_l			(red_reg_d_tl[5:0]), 
		.red_enable_l			(red_reg_en_tl[1:0]), 
		.red_data_r			(red_reg_d_tr[5:0]), 
		.red_enable_r			(red_reg_en_tr[1:0]), 
		.rd_en_b			(rd_en_top_b), 
		.wr_waysel_b			(wr_waysel_b[1:0]), 
		.wrd_byte15_a			({dcache_wparity_m[15],
		dcache_wdata_m[127:120]}), 
		.wrd_byte14_a			({dcache_wparity_m[14],
		dcache_wdata_m[119:112]}), 
		.wrd_byte13_a			({dcache_wparity_m[13],
		dcache_wdata_m[111:104]}), 
		.wrd_byte12_a			({dcache_wparity_m[12],
		dcache_wdata_m[103:96]}), 
		.wrd_byte11_a			({dcache_wparity_m[11],
		dcache_wdata_m[95:88]}), 
		.wrd_byte10_a			({dcache_wparity_m[10],
		dcache_wdata_m[87:80]}), 
		.wrd_byte9_a			({dcache_wparity_m[9],
		dcache_wdata_m[79:72]}), 
		.wrd_byte8_a			({dcache_wparity_m[8],
		dcache_wdata_m[71:64]}), 
		.wrd_byte7_a			({dcache_wparity_m[7],
		dcache_wdata_m[63:56]}), 
		.wrd_byte6_a			({dcache_wparity_m[6],
		dcache_wdata_m[55:48]}), 
		.wrd_byte5_a			({dcache_wparity_m[5],
		dcache_wdata_m[47:40]}), 
		.wrd_byte4_a			({dcache_wparity_m[4],
		dcache_wdata_m[39:32]}), 
		.wrd_byte3_a			({dcache_wparity_m[3],
		dcache_wdata_m[31:24]}), 
		.wrd_byte2_a			({dcache_wparity_m[2],
		dcache_wdata_m[23:16]}), 
		.wrd_byte1_a			({dcache_wparity_m[1],
		dcache_wdata_m[15:8]}), 
		.wrd_byte0_a			({dcache_wparity_m[0],
		dcache_wdata_m[7:0]}), 
		.w0_byte7_h			({rparity_w0_m[7],
		dcache_rdata_w0_m[63:56]}), 
		.w0_byte6_h			({rparity_w0_m[6],
		dcache_rdata_w0_m[55:48]}), 
		.w0_byte5_h			({rparity_w0_m[5],
		dcache_rdata_w0_m[47:40]}), 
		.w0_byte4_h			({rparity_w0_m[4],
		dcache_rdata_w0_m[39:32]}), 
		.w0_byte3_h			({rparity_w0_m[3],
		dcache_rdata_w0_m[31:24]}), 
		.w0_byte2_h			({rparity_w0_m[2],
		dcache_rdata_w0_m[23:16]}), 
		.w0_byte1_h			({rparity_w0_m[1],
		dcache_rdata_w0_m[15:8]}), 
		.w0_byte0_h			({rparity_w0_m[0],
		dcache_rdata_w0_m[7:0]}), 
		.w1_byte7_h			({rparity_w1_m[7],
		dcache_rdata_w1_m[63:56]}), 
		.w1_byte6_h			({rparity_w1_m[6],
		dcache_rdata_w1_m[55:48]}), 
		.w1_byte5_h			({rparity_w1_m[5],
		dcache_rdata_w1_m[47:40]}), 
		.w1_byte4_h			({rparity_w1_m[4],
		dcache_rdata_w1_m[39:32]}), 
		.w1_byte3_h			({rparity_w1_m[3],
		dcache_rdata_w1_m[31:24]}), 
		.w1_byte2_h			({rparity_w1_m[2],
		dcache_rdata_w1_m[23:16]}), 
		.w1_byte1_h			({rparity_w1_m[1],
		dcache_rdata_w1_m[15:8]}), 
		.w1_byte0_h			({rparity_w1_m[0],
		dcache_rdata_w1_m[7:0]}), 
		.w0_byte7_l			(w0_byte7_l_unused[8:0]), 
		.w0_byte6_l			(w0_byte6_l_unused[8:0]), 
		.w0_byte5_l			(w0_byte5_l_unused[8:0]), 
		.w0_byte4_l			(w0_byte4_l_unused[8:0]), 
		.w0_byte3_l			(w0_byte3_l_unused[8:0]), 
		.w0_byte2_l			(w0_byte2_l_unused[8:0]), 
		.w0_byte1_l			(w0_byte1_l_unused[8:0]), 
		.w0_byte0_l			(w0_byte0_l_unused[8:0]), 
		.w1_byte7_l			(w1_byte7_l_unused[8:0]), 
		.w1_byte6_l			(w1_byte6_l_unused[8:0]), 
		.w1_byte5_l			(w1_byte5_l_unused[8:0]), 
		.w1_byte4_l			(w1_byte4_l_unused[8:0]), 
		.w1_byte3_l			(w1_byte3_l_unused[8:0]), 
		.w1_byte2_l			(w1_byte2_l_unused[8:0]), 
		.w1_byte1_l			(w1_byte1_l_unused[8:0]), 
		.w1_byte0_l			(w1_byte0_l_unused[8:0]), 
		.l1clk				(l1clk), 
		.l1clk_wr			(l1clk_wr), 
		.rd_en_a			(rd_en_a), 
		.wr_en_a			(wr_en_a), 
		.wr_en_b			(wr_en_b), 
		.wr_inh_b			(wr_inh_b), 
		.addr_b				(addr_b[10:3]), 
		.byte_wr_en_b			(byte_wr_en_b[15:0]), 
		.vnw_ary			(vnw_ary));
	n2_dca_sp_9kb_bank way23(
		.red_data_l			(red_reg_d_bl[5:0]), 
		.red_enable_l			(red_reg_en_bl[1:0]), 
		.red_data_r			(red_reg_d_br[5:0]), 
		.red_enable_r			(red_reg_en_br[1:0]), 
		.rd_en_b			(rd_en_bot_b), 
		.wr_waysel_b			(wr_waysel_b[3:2]), 
		.wrd_byte15_a			({dcache_wparity_m[15],
		dcache_wdata_m[127:120]}), 
		.wrd_byte14_a			({dcache_wparity_m[14],
		dcache_wdata_m[119:112]}), 
		.wrd_byte13_a			({dcache_wparity_m[13],
		dcache_wdata_m[111:104]}), 
		.wrd_byte12_a			({dcache_wparity_m[12],
		dcache_wdata_m[103:96]}), 
		.wrd_byte11_a			({dcache_wparity_m[11],
		dcache_wdata_m[95:88]}), 
		.wrd_byte10_a			({dcache_wparity_m[10],
		dcache_wdata_m[87:80]}), 
		.wrd_byte9_a			({dcache_wparity_m[9],
		dcache_wdata_m[79:72]}), 
		.wrd_byte8_a			({dcache_wparity_m[8],
		dcache_wdata_m[71:64]}), 
		.wrd_byte7_a			({dcache_wparity_m[7],
		dcache_wdata_m[63:56]}), 
		.wrd_byte6_a			({dcache_wparity_m[6],
		dcache_wdata_m[55:48]}), 
		.wrd_byte5_a			({dcache_wparity_m[5],
		dcache_wdata_m[47:40]}), 
		.wrd_byte4_a			({dcache_wparity_m[4],
		dcache_wdata_m[39:32]}), 
		.wrd_byte3_a			({dcache_wparity_m[3],
		dcache_wdata_m[31:24]}), 
		.wrd_byte2_a			({dcache_wparity_m[2],
		dcache_wdata_m[23:16]}), 
		.wrd_byte1_a			({dcache_wparity_m[1],
		dcache_wdata_m[15:8]}), 
		.wrd_byte0_a			({dcache_wparity_m[0],
		dcache_wdata_m[7:0]}), 
		.w0_byte7_h			({rparity_w2_m[7],
		dcache_rdata_w2_m[63:56]}), 
		.w0_byte6_h			({rparity_w2_m[6],
		dcache_rdata_w2_m[55:48]}), 
		.w0_byte5_h			({rparity_w2_m[5],
		dcache_rdata_w2_m[47:40]}), 
		.w0_byte4_h			({rparity_w2_m[4],
		dcache_rdata_w2_m[39:32]}), 
		.w0_byte3_h			({rparity_w2_m[3],
		dcache_rdata_w2_m[31:24]}), 
		.w0_byte2_h			({rparity_w2_m[2],
		dcache_rdata_w2_m[23:16]}), 
		.w0_byte1_h			({rparity_w2_m[1],
		dcache_rdata_w2_m[15:8]}), 
		.w0_byte0_h			({rparity_w2_m[0],
		dcache_rdata_w2_m[7:0]}), 
		.w1_byte7_h			({rparity_w3_m[7],
		dcache_rdata_w3_m[63:56]}), 
		.w1_byte6_h			({rparity_w3_m[6],
		dcache_rdata_w3_m[55:48]}), 
		.w1_byte5_h			({rparity_w3_m[5],
		dcache_rdata_w3_m[47:40]}), 
		.w1_byte4_h			({rparity_w3_m[4],
		dcache_rdata_w3_m[39:32]}), 
		.w1_byte3_h			({rparity_w3_m[3],
		dcache_rdata_w3_m[31:24]}), 
		.w1_byte2_h			({rparity_w3_m[2],
		dcache_rdata_w3_m[23:16]}), 
		.w1_byte1_h			({rparity_w3_m[1],
		dcache_rdata_w3_m[15:8]}), 
		.w1_byte0_h			({rparity_w3_m[0],
		dcache_rdata_w3_m[7:0]}), 
		.w0_byte7_l			(w2_byte7_l_unused[8:0]), 
		.w0_byte6_l			(w2_byte6_l_unused[8:0]), 
		.w0_byte5_l			(w2_byte5_l_unused[8:0]), 
		.w0_byte4_l			(w2_byte4_l_unused[8:0]), 
		.w0_byte3_l			(w2_byte3_l_unused[8:0]), 
		.w0_byte2_l			(w2_byte2_l_unused[8:0]), 
		.w0_byte1_l			(w2_byte1_l_unused[8:0]), 
		.w0_byte0_l			(w2_byte0_l_unused[8:0]), 
		.w1_byte7_l			(w3_byte7_l_unused[8:0]), 
		.w1_byte6_l			(w3_byte6_l_unused[8:0]), 
		.w1_byte5_l			(w3_byte5_l_unused[8:0]), 
		.w1_byte4_l			(w3_byte4_l_unused[8:0]), 
		.w1_byte3_l			(w3_byte3_l_unused[8:0]), 
		.w1_byte2_l			(w3_byte2_l_unused[8:0]), 
		.w1_byte1_l			(w3_byte1_l_unused[8:0]), 
		.w1_byte0_l			(w3_byte0_l_unused[8:0]), 
		.l1clk				(l1clk), 
		.l1clk_wr			(l1clk_wr), 
		.rd_en_a			(rd_en_a), 
		.wr_en_a			(wr_en_a), 
		.wr_en_b			(wr_en_b), 
		.wr_inh_b			(wr_inh_b), 
		.addr_b				(addr_b[10:3]), 
		.byte_wr_en_b			(byte_wr_en_b[15:0]), 
		.vnw_ary			(vnw_ary));

	initial begin
	  red_reg_d_bl[5:0] = 6'b0;
	  red_reg_en_bl[1:0] = 2'b0;
	  red_reg_d_br[5:0] = 6'b0;
	  red_reg_en_br[1:0] = 2'b0;
	  red_reg_d_tl[5:0] = 6'b0;
	  red_reg_en_tl[1:0] = 2'b0;
	  red_reg_d_tr[5:0] = 6'b0;
	  red_reg_en_tr[1:0] = 2'b0;
	end
	always @(red_reg_clk_ or red_data or red_enable) begin
	  if (~red_reg_clk_[0]) begin
	    red_reg_d_bl[5:0] = red_data[5:0];
	    red_reg_en_bl[1:0] = red_enable[1:0];
	  end
	  if (~red_reg_clk_[1]) begin
	    red_reg_d_br[5:0] = red_data[5:0];
	    red_reg_en_br[1:0] = red_enable[1:0];
	  end
	  if (~red_reg_clk_[2]) begin
	    red_reg_d_tl[5:0] = red_data[5:0];
	    red_reg_en_tl[1:0] = red_enable[1:0];
	  end
	  if (~red_reg_clk_[3]) begin
	    red_reg_d_tr[5:0] = red_data[5:0];
	    red_reg_en_tr[1:0] = red_enable[1:0];
	  end
	end
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129875 */
// No timescale specified
module n2_dca_sp_9kb_bank(l1clk, l1clk_wr, rd_en_b, rd_en_a, wr_en_a, wr_en_b, 
	wr_inh_b, addr_b, byte_wr_en_b, wr_waysel_b, red_data_l, red_data_r, 
	red_enable_l, red_enable_r, vnw_ary, wrd_byte15_a, wrd_byte14_a, 
	wrd_byte13_a, wrd_byte12_a, wrd_byte11_a, wrd_byte10_a, wrd_byte9_a, 
	wrd_byte8_a, wrd_byte7_a, wrd_byte6_a, wrd_byte5_a, wrd_byte4_a, 
	wrd_byte3_a, wrd_byte2_a, wrd_byte1_a, wrd_byte0_a, w1_byte7_h, 
	w1_byte6_h, w1_byte5_h, w1_byte4_h, w1_byte3_h, w1_byte2_h, w1_byte1_h, 
	w1_byte0_h, w1_byte7_l, w1_byte6_l, w1_byte5_l, w1_byte4_l, w1_byte3_l, 
	w1_byte2_l, w1_byte1_l, w1_byte0_l, w0_byte7_h, w0_byte6_h, w0_byte5_h, 
	w0_byte4_h, w0_byte3_h, w0_byte2_h, w0_byte1_h, w0_byte0_h, w0_byte7_l, 
	w0_byte6_l, w0_byte5_l, w0_byte4_l, w0_byte3_l, w0_byte2_l, w0_byte1_l, 
	w0_byte0_l);

	input			l1clk;
	input			l1clk_wr;
	input			rd_en_b;
	input			rd_en_a;
	input			wr_en_a;
	input			wr_en_b;
	input			wr_inh_b;
	input	[10:3]		addr_b;
	input	[15:0]		byte_wr_en_b;
	input	[1:0]		wr_waysel_b;
	input	[5:0]		red_data_l;
	input	[5:0]		red_data_r;
	input	[1:0]		red_enable_l;
	input	[1:0]		red_enable_r;
	input			vnw_ary;
	input	[8:0]		wrd_byte15_a;
	input	[8:0]		wrd_byte14_a;
	input	[8:0]		wrd_byte13_a;
	input	[8:0]		wrd_byte12_a;
	input	[8:0]		wrd_byte11_a;
	input	[8:0]		wrd_byte10_a;
	input	[8:0]		wrd_byte9_a;
	input	[8:0]		wrd_byte8_a;
	input	[8:0]		wrd_byte7_a;
	input	[8:0]		wrd_byte6_a;
	input	[8:0]		wrd_byte5_a;
	input	[8:0]		wrd_byte4_a;
	input	[8:0]		wrd_byte3_a;
	input	[8:0]		wrd_byte2_a;
	input	[8:0]		wrd_byte1_a;
	input	[8:0]		wrd_byte0_a;
	output	[8:0]		w1_byte7_h;
	output	[8:0]		w1_byte6_h;
	output	[8:0]		w1_byte5_h;
	output	[8:0]		w1_byte4_h;
	output	[8:0]		w1_byte3_h;
	output	[8:0]		w1_byte2_h;
	output	[8:0]		w1_byte1_h;
	output	[8:0]		w1_byte0_h;
	output	[8:0]		w1_byte7_l;
	output	[8:0]		w1_byte6_l;
	output	[8:0]		w1_byte5_l;
	output	[8:0]		w1_byte4_l;
	output	[8:0]		w1_byte3_l;
	output	[8:0]		w1_byte2_l;
	output	[8:0]		w1_byte1_l;
	output	[8:0]		w1_byte0_l;
	output	[8:0]		w0_byte7_h;
	output	[8:0]		w0_byte6_h;
	output	[8:0]		w0_byte5_h;
	output	[8:0]		w0_byte4_h;
	output	[8:0]		w0_byte3_h;
	output	[8:0]		w0_byte2_h;
	output	[8:0]		w0_byte1_h;
	output	[8:0]		w0_byte0_h;
	output	[8:0]		w0_byte7_l;
	output	[8:0]		w0_byte6_l;
	output	[8:0]		w0_byte5_l;
	output	[8:0]		w0_byte4_l;
	output	[8:0]		w0_byte3_l;
	output	[8:0]		w0_byte2_l;
	output	[8:0]		w0_byte1_l;
	output	[8:0]		w0_byte0_l;

	wire	[71:0]		w0_sao_h;
	wire	[71:0]		w0_sao_l;
	wire	[71:0]		w1_sao_h;
	wire	[71:0]		w1_sao_l;
	wire	[15:0]		red_unused;
	wire	[143:0]		wrd;
	wire	[287:0]		din;
	wire	[287:0]		byte_mask;
	wire	[287:0]		byte_mask_inv;
	wire	[287:0]		temp;
	wire	[287:0]		new_data;
	wire			w0_wcs;
	wire			w1_wcs;
	wire	[287:0]		wr_data;
	wire			rcs_l;
	wire	[71:0]		w0_dout;
	wire	[71:0]		w1_dout;
	wire			l1clk_b;

	reg	[(288 - 1):0]	mem[(128 - 1):0];
	reg	[(288 - 1):0]	local_dout;
	integer			i;
	reg	[71:0]		w0_sao_h_r;
	reg	[71:0]		w0_sao_l_r;
	reg	[71:0]		w1_sao_h_r;
	reg	[71:0]		w1_sao_l_r;
	supply0			vss;
	supply1			vdd;

	assign red_unused[15:0] = {red_data_l[5:0], red_enable_l[1:0], 
		red_data_r[5:0], red_enable_r[1:0]};
	assign wrd[143:0] = {wrd_byte15_a[8:0], wrd_byte14_a[8:0], 
		wrd_byte13_a[8:0], wrd_byte12_a[8:0], wrd_byte11_a[8:0], 
		wrd_byte10_a[8:0], wrd_byte9_a[8:0], wrd_byte8_a[8:0], 
		wrd_byte7_a[8:0], wrd_byte6_a[8:0], wrd_byte5_a[8:0], 
		wrd_byte4_a[8:0], wrd_byte3_a[8:0], wrd_byte2_a[8:0], 
		wrd_byte1_a[8:0], wrd_byte0_a[8:0]};
	assign din[287:0] = {wrd[143:0], wrd[143:0]};
	assign byte_mask[287:0] = {{9 {byte_wr_en_b[15]}}, {9
		{byte_wr_en_b[14]}}, {9 {byte_wr_en_b[13]}}, {9
		{byte_wr_en_b[12]}}, {9 {byte_wr_en_b[11]}}, {9
		{byte_wr_en_b[10]}}, {9 {byte_wr_en_b[9]}}, {9
		{byte_wr_en_b[8]}}, {9 {byte_wr_en_b[7]}}, {9
		{byte_wr_en_b[6]}}, {9 {byte_wr_en_b[5]}}, {9
		{byte_wr_en_b[4]}}, {9 {byte_wr_en_b[3]}}, {9
		{byte_wr_en_b[2]}}, {9 {byte_wr_en_b[1]}}, {9
		{byte_wr_en_b[0]}}, {9 {byte_wr_en_b[15]}}, {9
		{byte_wr_en_b[14]}}, {9 {byte_wr_en_b[13]}}, {9
		{byte_wr_en_b[12]}}, {9 {byte_wr_en_b[11]}}, {9
		{byte_wr_en_b[10]}}, {9 {byte_wr_en_b[9]}}, {9
		{byte_wr_en_b[8]}}, {9 {byte_wr_en_b[7]}}, {9
		{byte_wr_en_b[6]}}, {9 {byte_wr_en_b[5]}}, {9
		{byte_wr_en_b[4]}}, {9 {byte_wr_en_b[3]}}, {9
		{byte_wr_en_b[2]}}, {9 {byte_wr_en_b[1]}}, {9 {byte_wr_en_b[0]}}
		};
	assign byte_mask_inv[287:0] = (~byte_mask[287:0]);
	assign temp[287:0] = mem[addr_b[10:4]];
	assign new_data[287:0] = ((temp[287:0] & byte_mask_inv[287:0]) | (
		din[287:0] & byte_mask[287:0]));
	assign w0_wcs = (((wr_waysel_b[0] & wr_en_b) & (~wr_inh_b)) & (~rd_en_b)
		);
	assign w1_wcs = (((wr_waysel_b[1] & wr_en_b) & (~wr_inh_b)) & (~rd_en_b)
		);
	assign wr_data[143:0] = (w0_wcs ? new_data[143:0] : temp[143:0]);
	assign wr_data[287:144] = (w1_wcs ? new_data[287:144] : temp[287:144]);
	assign rcs_l = (rd_en_b & (~wr_en_b));
	assign w0_dout[71:0] = (addr_b[3] ? local_dout[71:0] : 
		local_dout[143:72]);
	assign w1_dout[71:0] = (addr_b[3] ? local_dout[215:144] : 
		local_dout[287:216]);
	assign l1clk_b = (~l1clk);
	assign w0_sao_h[71:0] = (w0_sao_h_r[71:0] & {72 {l1clk_b}});
	assign w0_sao_l[71:0] = (w0_sao_l_r[71:0] & {72 {l1clk_b}});
	assign w1_sao_h[71:0] = (w1_sao_h_r[71:0] & {72 {l1clk_b}});
	assign w1_sao_l[71:0] = (w1_sao_l_r[71:0] & {72 {l1clk_b}});
	assign w0_byte7_h[8:0] = w0_sao_h[71:63];
	assign w0_byte6_h[8:0] = w0_sao_h[62:54];
	assign w0_byte5_h[8:0] = w0_sao_h[53:45];
	assign w0_byte4_h[8:0] = w0_sao_h[44:36];
	assign w0_byte3_h[8:0] = w0_sao_h[35:27];
	assign w0_byte2_h[8:0] = w0_sao_h[26:18];
	assign w0_byte1_h[8:0] = w0_sao_h[17:9];
	assign w0_byte0_h[8:0] = w0_sao_h[8:0];
	assign w0_byte7_l[8:0] = w0_sao_l[71:63];
	assign w0_byte6_l[8:0] = w0_sao_l[62:54];
	assign w0_byte5_l[8:0] = w0_sao_l[53:45];
	assign w0_byte4_l[8:0] = w0_sao_l[44:36];
	assign w0_byte3_l[8:0] = w0_sao_l[35:27];
	assign w0_byte2_l[8:0] = w0_sao_l[26:18];
	assign w0_byte1_l[8:0] = w0_sao_l[17:9];
	assign w0_byte0_l[8:0] = w0_sao_l[8:0];
	assign w1_byte7_h[8:0] = w1_sao_h[71:63];
	assign w1_byte6_h[8:0] = w1_sao_h[62:54];
	assign w1_byte5_h[8:0] = w1_sao_h[53:45];
	assign w1_byte4_h[8:0] = w1_sao_h[44:36];
	assign w1_byte3_h[8:0] = w1_sao_h[35:27];
	assign w1_byte2_h[8:0] = w1_sao_h[26:18];
	assign w1_byte1_h[8:0] = w1_sao_h[17:9];
	assign w1_byte0_h[8:0] = w1_sao_h[8:0];
	assign w1_byte7_l[8:0] = w1_sao_l[71:63];
	assign w1_byte6_l[8:0] = w1_sao_l[62:54];
	assign w1_byte5_l[8:0] = w1_sao_l[53:45];
	assign w1_byte4_l[8:0] = w1_sao_l[44:36];
	assign w1_byte3_l[8:0] = w1_sao_l[35:27];
	assign w1_byte2_l[8:0] = w1_sao_l[26:18];
	assign w1_byte1_l[8:0] = w1_sao_l[17:9];
	assign w1_byte0_l[8:0] = w1_sao_l[8:0];

	initial begin
	  for (i = 0; (i < 128); i = (i + 1)) begin
	    mem[i] = 288'b0;
	  end
	end
	always @(negedge l1clk_wr) begin
	  if (w0_wcs | w1_wcs) begin
	    if (rcs_l) begin
	      mem[addr_b[10:4]] <= 288'hxxxxxxxx;
	    end
	    else
	      begin
		mem[addr_b[10:4]] <= wr_data;
	      end
	  end
	end
	always @(l1clk) begin
	  if (~l1clk) begin
	    local_dout[(288 - 1):0] <= 288'b0;
	  end
	  else
	    begin
	      if (rcs_l) begin
		if ((w0_wcs | w1_wcs) | wr_inh_b) begin
		  local_dout[(288 - 1):0] <= 288'hxxxxxxxx;
		end
		else
		  begin
		    local_dout[(288 - 1):0] <= mem[addr_b[10:4]];
		  end
	      end
	    end
	end
	always @(negedge l1clk) begin
	  w0_sao_h_r[71:0] <= (w0_dout[71:0] & {72 {(rd_en_a & (~wr_en_a))}});
	  w0_sao_l_r[71:0] <= ((~w0_dout[71:0]) & {72 {(rd_en_a & (~wr_en_a))}})
		  ;
	  w1_sao_h_r[71:0] <= (w1_dout[71:0] & {72 {(rd_en_a & (~wr_en_a))}});
	  w1_sao_l_r[71:0] <= ((~w1_dout[71:0]) & {72 {(rd_en_a & (~wr_en_a))}})
		  ;
	end
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130103 */
// No timescale specified
module mux_macro__mux_aope__ports_2__width_64(din0, din1, sel0, dout);

	input	[63:0]		din0;
	input	[63:0]		din1;
	input			sel0;
	output	[63:0]		dout;

	wire			psel0;
	wire			psel1;

	cl_dp1_penc2_8x c0_0(
		.sel0				(sel0), 
		.psel0				(psel0), 
		.psel1				(psel1));
	mux2s #(64) d0_0(
		.sel0				(psel0), 
		.sel1				(psel1), 
		.in0				(din0[63:0]), 
		.in1				(din1[63:0]), 
		.dout				(dout[63:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130127 */
// No timescale specified
module mux_macro__mux_aope__ports_2__width_4(din0, din1, sel0, dout);

	input	[3:0]		din0;
	input	[3:0]		din1;
	input			sel0;
	output	[3:0]		dout;

	wire			psel0;
	wire			psel1;

	cl_dp1_penc2_8x c0_0(
		.sel0				(sel0), 
		.psel0				(psel0), 
		.psel1				(psel1));
	mux2s #(4) d0_0(
		.sel0				(psel0), 
		.sel1				(psel1), 
		.in0				(din0[3:0]), 
		.in1				(din1[3:0]), 
		.dout				(dout[3:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130151 */
// No timescale specified
module mux_macro__mux_aonpe__ports_4__width_8(din0, sel0, din1, sel1, din2, 
	sel2, din3, sel3, dout);

	input	[7:0]		din0;
	input			sel0;
	input	[7:0]		din1;
	input			sel1;
	input	[7:0]		din2;
	input			sel2;
	input	[7:0]		din3;
	input			sel3;
	output	[7:0]		dout;

	wire			buffout0;
	wire			buffout1;
	wire			buffout2;
	wire			buffout3;

	cl_dp1_muxbuff4_8x c0_0(
		.in0				(sel0), 
		.in1				(sel1), 
		.in2				(sel2), 
		.in3				(sel3), 
		.out0				(buffout0), 
		.out1				(buffout1), 
		.out2				(buffout2), 
		.out3				(buffout3));
	mux4s #(8) d0_0(
		.sel0				(buffout0), 
		.sel1				(buffout1), 
		.sel2				(buffout2), 
		.sel3				(buffout3), 
		.in0				(din0[7:0]), 
		.in1				(din1[7:0]), 
		.in2				(din2[7:0]), 
		.in3				(din3[7:0]), 
		.dout				(dout[7:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130192 */
// No timescale specified
module xor_macro__ports_3__width_4(din0, din1, din2, dout);

	input	[3:0]		din0;
	input	[3:0]		din1;
	input	[3:0]		din2;
	output	[3:0]		dout;

	xor3 #(4) d0_0(
		.in0				(din0[3:0]), 
		.in1				(din1[3:0]), 
		.in2				(din2[3:0]), 
		.out				(dout[3:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 130208 */
// No timescale specified
module msff_ctl_macro__fs_1__width_12(din, l1clk, scan_in, siclk, soclk, dout, 
	scan_out);

	input	[11:0]		din;
	input			l1clk;
	input	[11:0]		scan_in;
	input			siclk;
	input			soclk;
	output	[11:0]		dout;
	output	[11:0]		scan_out;

	wire	[11:0]		fdin;

	assign fdin[11:0] = din[11:0];

	dff #(12) d0_0(
		.l1clk				(l1clk), 
		.siclk				(siclk), 
		.soclk				(soclk), 
		.d				(fdin[11:0]), 
		.si				(scan_in[11:0]), 
		.so				(scan_out[11:0]), 
		.q				(dout[11:0]));
endmodule
`endcelldefine

`celldefine
/* Source file "1_core_8_thrd_dut_rtl.v.edt.3", line 129396 */
// No timescale specified
module tisram_msff_macro__fs_1__width_8(d, scan_in, l1clk, siclk, soclk,
        scan_out, latout, latout_l);

        input   [7:0]           d;
        input   [7:0]           scan_in;
        input                   l1clk;
        input                   siclk;
        input                   soclk;
        output  [7:0]           scan_out;
        output  [7:0]           latout;
        output  [7:0]           latout_l;

        tisram_msff #(8) d0_0(
                .d                              (d[7:0]),
                .si                             (scan_in[7:0]),
                .so                             (scan_out[7:0]),
                .l1clk                          (l1clk),
                .siclk                          (siclk),
                .soclk                          (soclk),
                .latout                         (latout[7:0]),
                .latout_l                       (latout_l[7:0]));
endmodule
`endcelldefine


`endif // `ifdef FPGA
// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_dta_sp_1920b_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_dta_sp_1920b_cust (
  index0_x, 
  index1_x, 
  index_sel_x, 
  wrway_x, 
  rdreq_x, 
  wrreq_x, 
  wrtag_x, 
  dta_clken, 
  rdtag_w0_y, 
  rdtag_w1_y, 
  rdtag_w2_y, 
  rdtag_w3_y, 
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_se_scancollar_in, 
  tcu_scan_en, 
  tcu_array_wr_inhibit, 
  scan_out);
wire l1clk_din;
wire l1clk_in;
wire l1clk_array;
wire [6:0] index_x;
wire dff_inputs1_scanin;
wire dff_inputs1_scanout;
wire [1:0] wrway_y;
wire [6:0] index_y;
wire [8:0] dff_inputs1_unused;
wire dff_inputs2_scanin;
wire dff_inputs2_scanout;
wire [0:0] index_y_unused;
wire dff_inputs3_scanin;
wire dff_inputs3_scanout;
wire rdreq_b;
wire wrreq_b;
wire [1:0] dff_inputs3_unused;
wire dff_inputs4_scanin;
wire dff_inputs4_scanout;
wire rdreq_a;
wire wrreq_a;
wire dff_wrtag_scanin;
wire dff_wrtag_scanout;
wire [29:0] wrtag_y;
wire [1:0] wrway_y_;
wire wr_inhibit_;
wire wr_inhibit;
wire [3:0] wr_way;


input	[6:0]	index0_x;	// address0 (used for read)
input	[6:0]	index1_x;	// address1 (used for write)
input		index_sel_x;	// selects between index1 and index0
input	[1:0]	wrway_x;	// way to write to
input		rdreq_x;	// read enable
input		wrreq_x;	// write enable
// 0in bits_on -var {rdreq_x,wrreq_x} -max 1 -message "Attempt to read AND write dtag on same cycle"
// 0in custom -fire ((rdreq_x | wrreq_x) & ~dta_clken) -message "Attempt to read or write with clock disabled"
input	[29:0]	wrtag_x;      // write data
input		dta_clken;	// array clock enable

output	[29:0]	rdtag_w0_y;    // read data split into 4 ports
output	[29:0]	rdtag_w1_y;    // read data
output	[29:0]	rdtag_w2_y;    // read data
output	[29:0]	rdtag_w3_y;    // read data

input		l2clk;
input		scan_in;
input		tcu_pce_ov;
input		tcu_aclk;
input		tcu_bclk;
input		tcu_se_scancollar_in;
input		tcu_scan_en;
input		tcu_array_wr_inhibit;
output		scan_out;

`ifndef FPGA
// synopsys translate_off
`endif

wire pce_ov = tcu_pce_ov;
wire stop   = 1'b0;
wire siclk  = tcu_aclk ;
wire soclk  = tcu_bclk;

//================================================
// Clock headers
//================================================

// This clock gates the wrtag input flops.
n2_dta_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_din (	
        .l2clk	(l2clk), 
        .l1en 	(dta_clken),
	.se	(tcu_se_scancollar_in),
        .l1clk	(l1clk_din),
  .pce_ov(pce_ov),
  .stop(stop)
);

// This clock gates the other input flops and latches.
// It will be not be power managed.
n2_dta_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_in (	
        .l2clk	(l2clk), 
        .l1en 	(1'b1), 
	.se	(tcu_se_scancollar_in),
        .l1clk	(l1clk_in),
  .pce_ov(pce_ov),
  .stop(stop)
);

// This clock gates the array and internal logic.
n2_dta_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_array (
        .l2clk	(l2clk), 
        .l1en 	(dta_clken),
	.se	(tcu_scan_en),
        .l1clk	(l1clk_array),
  .pce_ov(pce_ov),
  .stop(stop)
);

//=========================================================================================
//  Input flops
//=========================================================================================

// 2:1 mux on address input
// address inputs are critical and this mux needs to be merged with the receiving flop.
assign index_x[6:0] = index_sel_x ? index1_x[6:0] : index0_x[6:0];

n2_dta_sp_1920b_cust_tisram_msff_macro__width_9 dff_inputs1  (
	.scan_in(dff_inputs1_scanin),
	.scan_out(dff_inputs1_scanout),
	.l1clk	(l1clk_in),
	.d	({wrway_x[1:0],
		  index_x[0],
		  index_x[1],
		  index_x[2],
		  index_x[3],
		  index_x[4],
		  index_x[5],
		  index_x[6]
		}),
	.latout	({wrway_y[1:0],
		  index_y[0],
		  index_y[1],
		  index_y[2],
		  index_y[3],
		  index_y[4],
		  index_y[5],
		  index_y[6]
		}),
	.latout_l(dff_inputs1_unused[8:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dta_sp_1920b_cust_msff_ctl_macro__width_1 dff_inputs2  (
	.scan_in(dff_inputs2_scanin),
	.scan_out(dff_inputs2_scanout),
	.l1clk	(l1clk_in),
	.din	(index_x[0]),
	.dout	(index_y_unused[0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dta_sp_1920b_cust_tisram_msff_macro__width_2 dff_inputs3  (
	.scan_in(dff_inputs3_scanin),
	.scan_out(dff_inputs3_scanout),
	.l1clk	(l1clk_in),
	.d	({rdreq_x,wrreq_x}),
	.latout	({rdreq_b,wrreq_b}),
	.latout_l(dff_inputs3_unused[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dta_sp_1920b_cust_msff_ctl_macro__width_2 dff_inputs4  (
	.scan_in(dff_inputs4_scanin),
	.scan_out(dff_inputs4_scanout),
	.l1clk	(l1clk_in),
	.din	({rdreq_x,wrreq_x}),
	.dout	({rdreq_a,wrreq_a}),
  .siclk(siclk),
  .soclk(soclk)
);

n2_dta_sp_1920b_cust_msff_ctl_macro__width_30 dff_wrtag  (
	.scan_in(dff_wrtag_scanin),
	.scan_out(dff_wrtag_scanout),
	.l1clk	(l1clk_din),
	.din	({wrtag_x[0],
		  wrtag_x[1],
		  wrtag_x[2],
		  wrtag_x[3],
		  wrtag_x[4],
		  wrtag_x[5],
		  wrtag_x[6],
		  wrtag_x[7],
		  wrtag_x[8],
		  wrtag_x[9],
		  wrtag_x[10],
		  wrtag_x[11],
		  wrtag_x[12],
		  wrtag_x[13],
		  wrtag_x[14],
		  wrtag_x[15],
		  wrtag_x[16],
		  wrtag_x[17],
		  wrtag_x[18],
		  wrtag_x[19],
		  wrtag_x[20],
		  wrtag_x[21],
		  wrtag_x[22],
		  wrtag_x[23],
		  wrtag_x[24],
		  wrtag_x[25],
		  wrtag_x[26],
		  wrtag_x[27],
		  wrtag_x[28],
		  wrtag_x[29]}),
	.dout	({wrtag_y[0],
		  wrtag_y[1],
		  wrtag_y[2],
		  wrtag_y[3],
		  wrtag_y[4],
		  wrtag_y[5],
		  wrtag_y[6],
		  wrtag_y[7],
		  wrtag_y[8],
		  wrtag_y[9],
		  wrtag_y[10],
		  wrtag_y[11],
		  wrtag_y[12],
		  wrtag_y[13],
		  wrtag_y[14],
		  wrtag_y[15],
		  wrtag_y[16],
		  wrtag_y[17],
		  wrtag_y[18],
		  wrtag_y[19],
		  wrtag_y[20],
		  wrtag_y[21],
		  wrtag_y[22],
		  wrtag_y[23],
		  wrtag_y[24],
		  wrtag_y[25],
		  wrtag_y[26],
		  wrtag_y[27],
		  wrtag_y[28],
		  wrtag_y[29]}),
  .siclk(siclk),
  .soclk(soclk)
);

// Decode write enables
n2_dta_sp_1920b_cust_inv_macro__width_3 way_inv  (
	.din	({wrway_y[1:0], tcu_array_wr_inhibit}),
	.dout	({wrway_y_[1:0],wr_inhibit_})
);

assign wr_inhibit = tcu_array_wr_inhibit;

n2_dta_sp_1920b_cust_and_macro__ports_4__width_4 way_and   (
	.din0	({wrreq_b,    wrreq_b,    wrreq_b,    wrreq_b}),
	.din1	({wrway_y [0],wrway_y_[0],wrway_y [0],wrway_y_[0]}),
	.din2	({wrway_y [1],wrway_y [1],wrway_y_[1],wrway_y_[1]}),
	.din3	({4{wr_inhibit_}}),
	.dout	(wr_way[3:0])
);

n2_dta_sp_1920b_array way0 (
	.clk		(l1clk_array),
	.wr_en_b	(wr_way[0]),
	.rd_en_b	(rdreq_b),
	.wr_en_a	(wrreq_a),
	.rd_en_a	(rdreq_a),
	.addr		(index_y[6:0]),
	.din		(wrtag_y[29:0]),
	.dout		(rdtag_w0_y[29:0]),
  .wr_inhibit(wr_inhibit)
);
n2_dta_sp_1920b_array way1 (
	.clk		(l1clk_array),
	.wr_en_b	(wr_way[1]),
	.rd_en_b	(rdreq_b),
	.wr_en_a	(wrreq_a),
	.rd_en_a	(rdreq_a),
	.addr		(index_y[6:0]),
	.din		(wrtag_y[29:0]),
	.dout		(rdtag_w1_y[29:0]),
  .wr_inhibit(wr_inhibit)
);
n2_dta_sp_1920b_array way2 (
	.clk		(l1clk_array),
	.wr_en_b	(wr_way[2]),
	.rd_en_b	(rdreq_b),
	.wr_en_a	(wrreq_a),
	.rd_en_a	(rdreq_a),
	.addr		(index_y[6:0]),
	.din		(wrtag_y[29:0]),
	.dout		(rdtag_w2_y[29:0]),
  .wr_inhibit(wr_inhibit)
);
n2_dta_sp_1920b_array way3 (
	.clk		(l1clk_array),
	.wr_en_b	(wr_way[3]),
	.rd_en_b	(rdreq_b),
	.wr_en_a	(wrreq_a),
	.rd_en_a	(rdreq_a),
	.addr		(index_y[6:0]),
	.din		(wrtag_y[29:0]),
	.dout		(rdtag_w3_y[29:0]),
  .wr_inhibit(wr_inhibit)
);

supply0 vss;
supply1 vdd;
// fixscan start:
assign dff_inputs1_scanin        = scan_in                  ;
assign dff_inputs2_scanin        = dff_inputs1_scanout      ;
assign dff_inputs3_scanin        = dff_inputs2_scanout      ;
assign dff_inputs4_scanin        = dff_inputs3_scanout      ;
assign dff_wrtag_scanin          = dff_inputs4_scanout      ;
assign scan_out                  = dff_wrtag_scanout        ;
// fixscan end:

`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_dta_sp_1920b_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_dta_sp_1920b_cust_tisram_msff_macro__width_9 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
wire [7:0] so;

input [8:0] d;
  input scan_in;
input l1clk;
input siclk;
input soclk;
  output scan_out;
output [8:0] latout;
output [8:0] latout_l;


tisram_msff #(9)  d0_0 (
.d(d[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[8:0]),
.latout_l(latout_l[8:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_dta_sp_1920b_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_dta_sp_1920b_cust_tisram_msff_macro__width_2 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
wire [0:0] so;

input [1:0] d;
  input scan_in;
input l1clk;
input siclk;
input soclk;
  output scan_out;
output [1:0] latout;
output [1:0] latout_l;


tisram_msff #(2)  d0_0 (
.d(d[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[1:0]),
.latout_l(latout_l[1:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_dta_sp_1920b_cust_msff_ctl_macro__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;
wire [0:0] so;

  input [1:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si({scan_in,so[0:0]}),
.so({so[0:0],scan_out}),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_dta_sp_1920b_cust_msff_ctl_macro__width_30 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [29:0] fdin;
wire [28:0] so;

  input [29:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [29:0] dout;
  output scan_out;
assign fdin[29:0] = din[29:0];


dff #(30)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[29:0]),
.si({scan_in,so[28:0]}),
.so({so[28:0],scan_out}),
.q(dout[29:0])
);


endmodule


//
//   invert macro
//
//


module n2_dta_sp_1920b_cust_inv_macro__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_dta_sp_1920b_cust_and_macro__ports_4__width_4 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  input [3:0] din2;
  input [3:0] din3;
  output [3:0] dout;


and4 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.in2(din2[3:0]),
.in3(din3[3:0]),
.out(dout[3:0])
);


endmodule


module n2_dta_sp_1920b_array (
  clk, 
  rd_en_b, 
  wr_en_b, 
  rd_en_a, 
  wr_en_a, 
  addr, 
  wr_inhibit, 
  din, 
  dout);
wire rd_en_b_unused;
	

`define	WIDTH 30
`define ENTRIES 128
`define ADDRBITS 7

input			clk;
input	     		rd_en_b;	// comes on negedge
input	     		wr_en_b;	// comes on negedge (way specific)
input	     		rd_en_a;	// comes on posedge
input	     		wr_en_a;	// comes on posedge (not way specific)
input	[`ADDRBITS-1:0]	addr;		// comes on negedge
input			wr_inhibit;	// async

input	[`WIDTH-1:0]	din;		// comes on posedge
output	[`WIDTH-1:0]	dout;


reg	[`WIDTH-1:0]	mem[`ENTRIES-1:0];
reg	[`WIDTH-1:0]	local_dout;

assign rd_en_b_unused = rd_en_b;

`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
  for (i=0; i<`ENTRIES; i=i+1) begin
    mem[i] = {`WIDTH{1'b0}}; 
  end
  local_dout = {`WIDTH{1'b0}};
end
`endif

//////////////////////
// Read/write array
//////////////////////

always @(negedge clk) begin
    if (wr_en_b) begin
        mem[addr] <= din;


    end
end

always @(posedge clk) begin
    local_dout[`WIDTH-1:0] <= mem[addr];
end

assign dout[`WIDTH-1:0] = local_dout[`WIDTH-1:0] & {`WIDTH{rd_en_a & ~wr_en_a & ~wr_inhibit}};

supply0 vss;
supply1 vdd;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_icd_sp_16p5kb_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_icd_sp_16p5kb_cust (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_array_wr_inhibit, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  tcu_scan_en, 
  red_en_in, 
  red_d_in, 
  rid_in, 
  red_wen, 
  red_arst, 
  ftp_icd_quad_0_en_bf, 
  ftp_icd_quad_1_en_bf, 
  ftp_icd_quad_2_en_bf, 
  ftp_icd_quad_3_en_bf, 
  agd_ic_index_bf, 
  agc_fill_wrway_bf, 
  cmu_ic_data, 
  agd_asi_bist_wrdata, 
  itb_icd_waysel_c, 
  agc_word_en_bf, 
  ftp_ic_rd_req_bf, 
  ftp_ic_wr_req_bf, 
  ftp_ic_wr_ps_en_bf, 
  ftp_asi_mbist_access_bf, 
  vnw_ary, 
  icd_bus_0_instr_c, 
  icd_bus_1_instr_c, 
  icd_bus_2_instr_c, 
  icd_bus_3_instr_c, 
  scan_out, 
  red_d_out, 
  red_en_out) ;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire wr_inhibit;
wire l1clk_in;
wire icd_quad_0_en_f_qual;
wire l1clk_q0_out;
wire icd_quad_1_en_f_qual;
wire l1clk_q1_out;
wire icd_quad_2_en_f_qual;
wire l1clk_q2_out;
wire icd_quad_3_en_f_qual;
wire l1clk_q3_out;
wire l1clk_free;
wire l1clk_fuse_clk1;
wire l1clk_red_in;
wire l1clk_red_out;
wire l1clk_int;
wire l1clk_out;
wire l1clk_wr;
wire [10:2] index_bf_l;
wire [2:0] wrway_bf_l;
wire [7:0] word_en_bf_l;
wire wr_inhibit_in_l;
wire ic_rd_req_bf_l;
wire ic_wr_req_bf_l;
wire ftp_icd_quad_0_en_l_bf;
wire ftp_icd_quad_1_en_l_bf;
wire ftp_icd_quad_2_en_l_bf;
wire ftp_icd_quad_3_en_l_bf;
wire quad_en_0_latch_scanin;
wire quad_en_0_latch_scanout;
wire icd_quad_0_en_f_lat;
wire icd_quad_0_en_f_lat_l;
wire quad_en_1_latch_scanin;
wire quad_en_1_latch_scanout;
wire icd_quad_1_en_f_lat;
wire icd_quad_1_en_f_lat_l;
wire quad_en_2_latch_scanin;
wire quad_en_2_latch_scanout;
wire icd_quad_2_en_f_lat;
wire icd_quad_2_en_f_lat_l;
wire quad_en_3_latch_scanin;
wire quad_en_3_latch_scanout;
wire icd_quad_3_en_f_lat;
wire icd_quad_3_en_f_lat_l;
wire icd_quad_0_en_f_lat_unused;
wire icd_quad_1_en_f_lat_unused;
wire icd_quad_2_en_f_lat_unused;
wire icd_quad_3_en_f_lat_unused;
wire index_reg_i_scanin;
wire index_reg_i_scanout;
wire [10:2] index_f;
wire [10:5] index_f_l;
wire [4:2] index_f_l_unused;
wire wrway_0_reg_scanin;
wire wrway_0_reg_scanout;
wire [2:0] wrway_f;
wire [2:0] wrway_f_unused;
wire wrway_1_reg_scanin;
wire wrway_1_reg_scanout;
wire wrway_2_reg_scanin;
wire wrway_2_reg_scanout;
wire wr_word_en_0_reg_scanin;
wire wr_word_en_0_reg_scanout;
wire [7:0] word_en_f;
wire [7:0] word_en_f_unused;
wire wr_word_en_1_reg_scanin;
wire wr_word_en_1_reg_scanout;
wire wr_word_en_2_reg_scanin;
wire wr_word_en_2_reg_scanout;
wire wr_word_en_3_reg_scanin;
wire wr_word_en_3_reg_scanout;
wire wr_word_en_4_reg_scanin;
wire wr_word_en_4_reg_scanout;
wire wr_word_en_5_reg_scanin;
wire wr_word_en_5_reg_scanout;
wire wr_word_en_6_reg_scanin;
wire wr_word_en_6_reg_scanout;
wire wr_word_en_7_reg_scanin;
wire wr_word_en_7_reg_scanout;
wire [3:0] quad_en_reg_scanin;
wire [3:0] quad_en_reg_scanout;
wire icd_quad_3_en_l_f;
wire icd_quad_2_en_l_f;
wire icd_quad_1_en_l_f;
wire icd_quad_0_en_l_f;
wire icd_quad_3_en_f;
wire icd_quad_2_en_f;
wire icd_quad_1_en_f;
wire icd_quad_0_en_f;
wire [0:0] wrreq_reg_scanin;
wire [0:0] wrreq_reg_scanout;
wire wrreq_f;
wire wrreq_f_l_unused;
wire wrreq_reg_b_scanin;
wire wrreq_reg_b_scanout;
wire wrreq_f_l;
wire [0:0] ftp_access_f_reg_scanin;
wire [0:0] ftp_access_f_reg_scanout;
wire asi_access_f;
wire rdreq_reg_scanin;
wire rdreq_reg_scanout;
wire rdreq_f_l_unused;
wire rdreq_f_unused;
wire rdreq_reg_b_scanin;
wire rdreq_reg_b_scanout;
wire rdreq_f;
wire [263:0] wrdata_in;
wire [32:0] wrdata_q0_0_scanin;
wire [32:0] wrdata_q0_0_scanout;
wire [263:0] wrdata_f;
wire [32:0] wrdata_q1_1_scanin;
wire [32:0] wrdata_q1_1_scanout;
wire [32:0] wrdata_q2_2_scanin;
wire [32:0] wrdata_q2_2_scanout;
wire [32:0] wrdata_q3_3_scanin;
wire [32:0] wrdata_q3_3_scanout;
wire [32:0] wrdata_q0_4_scanin;
wire [32:0] wrdata_q0_4_scanout;
wire [32:0] wrdata_q1_5_scanin;
wire [32:0] wrdata_q1_5_scanout;
wire [32:0] wrdata_q2_6_scanin;
wire [32:0] wrdata_q2_6_scanout;
wire [32:0] wrdata_q3_7_scanin;
wire [32:0] wrdata_q3_7_scanout;
wire [4:0] red_d_reg_scanin;
wire [4:0] red_d_reg_scanout;
wire [4:0] red_d_ff;
wire [1:0] red_en_reg_scanin;
wire [1:0] red_en_reg_scanout;
wire [1:0] red_en_ff;
wire [3:0] rid_reg_scanin;
wire [3:0] rid_reg_scanout;
wire [3:0] rid_ff;
wire [0:0] red_wen_reg_scanin;
wire [0:0] red_wen_reg_scanout;
wire red_wen_ff_and;
wire red_wen_ff;
wire [0:0] red_arst_reg_scanin;
wire [0:0] red_arst_reg_scanout;
wire red_arst_ff_and;
wire red_arst_ff;
wire [7:0] way_f_reg_scanin;
wire [7:0] way_f_reg_scanout;
wire [7:0] wrway_dec_bf;
wire [7:0] wrway_dec_f;
wire [7:0] way_c_reg_scanin;
wire [7:0] way_c_reg_scanout;
wire [7:0] wrway_dec_c;
wire [0:0] ftp_access_c_reg_scanin;
wire [0:0] ftp_access_c_reg_scanout;
wire asi_access_c;
wire ftp_access_c_dum_scanin;
wire ftp_access_c_dum_scanout;
wire asi_access_c_l;
wire asi_access_c_l_inv;
wire asi_access_c_inv;
wire [7:0] muxed_way_sel_c;
wire i4_i0_sel_upper;
wire i4_i0_sel_upper_;
wire i5_i1_sel_upper;
wire i5_i1_sel_upper_;
wire i6_i2_sel_upper_or_2;
wire i6_i2_sel_upper;
wire i6_i2_sel_upper_;
wire i7_i3_sel_upper;
wire i7_i3_sel_upper_;
wire [7:0] wr_word_en_f_l;
wire rdreq_f_q0_l;
wire rdreq_f_q0;
wire rdreq_f_q1_l;
wire rdreq_f_q1;
wire rdreq_f_q2_l;
wire rdreq_f_q2;
wire rdreq_f_q3_l;
wire rdreq_f_q3;
wire [7:0] wrway_dec_f_;
wire [7:0] rid_sel_dec;
wire [15:0] rid_sel;
wire [32:0] rd_data_w0_i4_or_i0;
wire [32:0] rd_data_w1_i4_or_i0;
wire [32:0] rd_data_w2_i4_or_i0;
wire [32:0] rd_data_w3_i4_or_i0;
wire [32:0] rd_data_w4_i4_or_i0;
wire [32:0] rd_data_w5_i4_or_i0;
wire [32:0] rd_data_w6_i4_or_i0;
wire [32:0] rd_data_w7_i4_or_i0;
wire [4:0] reg_d_q0_w3_w0_lft_d;
wire [1:0] reg_d_q0_w3_w0_lft_en;
wire [4:0] reg_d_q0_w3_w0_rgt_d;
wire [1:0] reg_d_q0_w3_w0_rgt_en;
wire [4:0] reg_d_q0_w7_w4_lft_d;
wire [1:0] reg_d_q0_w7_w4_lft_en;
wire [4:0] reg_d_q0_w7_w4_rgt_d;
wire [1:0] reg_d_q0_w7_w4_rgt_en;
wire [32:0] rd_data_w0_i5_or_i1;
wire [32:0] rd_data_w1_i5_or_i1;
wire [32:0] rd_data_w2_i5_or_i1;
wire [32:0] rd_data_w3_i5_or_i1;
wire [32:0] rd_data_w4_i5_or_i1;
wire [32:0] rd_data_w5_i5_or_i1;
wire [32:0] rd_data_w6_i5_or_i1;
wire [32:0] rd_data_w7_i5_or_i1;
wire [4:0] reg_d_q1_w3_w0_lft_d;
wire [1:0] reg_d_q1_w3_w0_lft_en;
wire [4:0] reg_d_q1_w3_w0_rgt_d;
wire [1:0] reg_d_q1_w3_w0_rgt_en;
wire [4:0] reg_d_q1_w7_w4_lft_d;
wire [1:0] reg_d_q1_w7_w4_lft_en;
wire [4:0] reg_d_q1_w7_w4_rgt_d;
wire [1:0] reg_d_q1_w7_w4_rgt_en;
wire [32:0] rd_data_w0_i6_or_i2;
wire [32:0] rd_data_w1_i6_or_i2;
wire [32:0] rd_data_w2_i6_or_i2;
wire [32:0] rd_data_w3_i6_or_i2;
wire [32:0] rd_data_w4_i6_or_i2;
wire [32:0] rd_data_w5_i6_or_i2;
wire [32:0] rd_data_w6_i6_or_i2;
wire [32:0] rd_data_w7_i6_or_i2;
wire [4:0] reg_d_q2_w3_w0_lft_d;
wire [1:0] reg_d_q2_w3_w0_lft_en;
wire [4:0] reg_d_q2_w3_w0_rgt_d;
wire [1:0] reg_d_q2_w3_w0_rgt_en;
wire [4:0] reg_d_q2_w7_w4_lft_d;
wire [1:0] reg_d_q2_w7_w4_lft_en;
wire [4:0] reg_d_q2_w7_w4_rgt_d;
wire [1:0] reg_d_q2_w7_w4_rgt_en;
wire [32:0] rd_data_w0_i7_or_i3;
wire [32:0] rd_data_w1_i7_or_i3;
wire [32:0] rd_data_w2_i7_or_i3;
wire [32:0] rd_data_w3_i7_or_i3;
wire [32:0] rd_data_w4_i7_or_i3;
wire [32:0] rd_data_w5_i7_or_i3;
wire [32:0] rd_data_w6_i7_or_i3;
wire [32:0] rd_data_w7_i7_or_i3;
wire [4:0] reg_d_q3_w3_w0_lft_d;
wire [1:0] reg_d_q3_w3_w0_lft_en;
wire [4:0] reg_d_q3_w3_w0_rgt_d;
wire [1:0] reg_d_q3_w3_w0_rgt_en;
wire [4:0] reg_d_q3_w7_w4_lft_d;
wire [1:0] reg_d_q3_w7_w4_lft_en;
wire [4:0] reg_d_q3_w7_w4_rgt_d;
wire [1:0] reg_d_q3_w7_w4_rgt_en;
wire [32:0] data_bus_0_w0_reg_scanin;
wire [32:0] data_bus_0_w0_reg_scanout;
wire [32:0] data_bus_0_w0_c;
wire [32:0] data_bus_1_w0_reg_scanin;
wire [32:0] data_bus_1_w0_reg_scanout;
wire [32:0] data_bus_1_w0_c;
wire [32:0] data_bus_2_w0_reg_scanin;
wire [32:0] data_bus_2_w0_reg_scanout;
wire [32:0] data_bus_2_w0_c;
wire [32:0] data_bus_3_w0_reg_scanin;
wire [32:0] data_bus_3_w0_reg_scanout;
wire [32:0] data_bus_3_w0_c;
wire [32:0] data_bus_0_w1_reg_scanin;
wire [32:0] data_bus_0_w1_reg_scanout;
wire [32:0] data_bus_0_w1_c;
wire [32:0] data_bus_1_w1_reg_scanin;
wire [32:0] data_bus_1_w1_reg_scanout;
wire [32:0] data_bus_1_w1_c;
wire [32:0] data_bus_2_w1_reg_scanin;
wire [32:0] data_bus_2_w1_reg_scanout;
wire [32:0] data_bus_2_w1_c;
wire [32:0] data_bus_3_w1_reg_scanin;
wire [32:0] data_bus_3_w1_reg_scanout;
wire [32:0] data_bus_3_w1_c;
wire [32:0] data_bus_0_w2_reg_scanin;
wire [32:0] data_bus_0_w2_reg_scanout;
wire [32:0] data_bus_0_w2_c;
wire [32:0] data_bus_1_w2_reg_scanin;
wire [32:0] data_bus_1_w2_reg_scanout;
wire [32:0] data_bus_1_w2_c;
wire [32:0] data_bus_2_w2_reg_scanin;
wire [32:0] data_bus_2_w2_reg_scanout;
wire [32:0] data_bus_2_w2_c;
wire [32:0] data_bus_3_w2_reg_scanin;
wire [32:0] data_bus_3_w2_reg_scanout;
wire [32:0] data_bus_3_w2_c;
wire [32:0] data_bus_0_w3_reg_scanin;
wire [32:0] data_bus_0_w3_reg_scanout;
wire [32:0] data_bus_0_w3_c;
wire [32:0] data_bus_1_w3_reg_scanin;
wire [32:0] data_bus_1_w3_reg_scanout;
wire [32:0] data_bus_1_w3_c;
wire [32:0] data_bus_2_w3_reg_scanin;
wire [32:0] data_bus_2_w3_reg_scanout;
wire [32:0] data_bus_2_w3_c;
wire [32:0] data_bus_3_w3_reg_scanin;
wire [32:0] data_bus_3_w3_reg_scanout;
wire [32:0] data_bus_3_w3_c;
wire [32:0] data_bus_0_w4_reg_scanin;
wire [32:0] data_bus_0_w4_reg_scanout;
wire [32:0] data_bus_0_w4_c;
wire [32:0] data_bus_1_w4_reg_scanin;
wire [32:0] data_bus_1_w4_reg_scanout;
wire [32:0] data_bus_1_w4_c;
wire [32:0] data_bus_2_w4_reg_scanin;
wire [32:0] data_bus_2_w4_reg_scanout;
wire [32:0] data_bus_2_w4_c;
wire [32:0] data_bus_3_w4_reg_scanin;
wire [32:0] data_bus_3_w4_reg_scanout;
wire [32:0] data_bus_3_w4_c;
wire [32:0] data_bus_0_w5_reg_scanin;
wire [32:0] data_bus_0_w5_reg_scanout;
wire [32:0] data_bus_0_w5_c;
wire [32:0] data_bus_1_w5_reg_scanin;
wire [32:0] data_bus_1_w5_reg_scanout;
wire [32:0] data_bus_1_w5_c;
wire [32:0] data_bus_2_w5_reg_scanin;
wire [32:0] data_bus_2_w5_reg_scanout;
wire [32:0] data_bus_2_w5_c;
wire [32:0] data_bus_3_w5_reg_scanin;
wire [32:0] data_bus_3_w5_reg_scanout;
wire [32:0] data_bus_3_w5_c;
wire [32:0] data_bus_0_w6_reg_scanin;
wire [32:0] data_bus_0_w6_reg_scanout;
wire [32:0] data_bus_0_w6_c;
wire [32:0] data_bus_1_w6_reg_scanin;
wire [32:0] data_bus_1_w6_reg_scanout;
wire [32:0] data_bus_1_w6_c;
wire [32:0] data_bus_2_w6_reg_scanin;
wire [32:0] data_bus_2_w6_reg_scanout;
wire [32:0] data_bus_2_w6_c;
wire [32:0] data_bus_3_w6_reg_scanin;
wire [32:0] data_bus_3_w6_reg_scanout;
wire [32:0] data_bus_3_w6_c;
wire [32:0] data_bus_0_w7_reg_scanin;
wire [32:0] data_bus_0_w7_reg_scanout;
wire [32:0] data_bus_0_w7_c;
wire [32:0] data_bus_1_w7_reg_scanin;
wire [32:0] data_bus_1_w7_reg_scanout;
wire [32:0] data_bus_1_w7_c;
wire [32:0] data_bus_2_w7_reg_scanin;
wire [32:0] data_bus_2_w7_reg_scanout;
wire [32:0] data_bus_2_w7_c;
wire [32:0] data_bus_3_w7_reg_scanin;
wire [32:0] data_bus_3_w7_reg_scanout;
wire [32:0] data_bus_3_w7_c;
wire [4:0] reg_d_out_mux_0;
wire [1:0] reg_en_out_mux_0;
wire [4:0] reg_d_out_mux_1;
wire [1:0] reg_en_out_mux_1;
wire [4:0] red_mux_d_out;
wire [1:0] red_mux_en_out;
wire [4:0] red_d_out_reg_scanin;
wire [4:0] red_d_out_reg_scanout;
wire [1:0] red_en_out_reg_scanin;
wire [1:0] red_en_out_reg_scanout;
 

// make sure you have .l2clk(l2clk), 1 level up; run fixscan


   input          l2clk;
   input          scan_in;
   input          tcu_pce_ov;
   input          tcu_aclk;
   input          tcu_bclk;
   input          tcu_array_wr_inhibit;
   input          tcu_se_scancollar_in;
   input          tcu_se_scancollar_out;
   input          tcu_scan_en;

   input [1:0]    red_en_in ;
   input [4:0]    red_d_in ;
   input [3:0]    rid_in ;
   input          red_wen ;
   input          red_arst ;

   input      ftp_icd_quad_0_en_bf;    // enable quad 0
   input      ftp_icd_quad_1_en_bf;    // enable quad 1
   input      ftp_icd_quad_2_en_bf;    // enable quad 2
   input      ftp_icd_quad_3_en_bf;    // enable quad 3


   input [10:2]                agd_ic_index_bf;    // index to write to/read from
   input [2:0]                 agc_fill_wrway_bf;  // way to write to
   input [263:0]               cmu_ic_data;        // 128b data, 4b parity
   input [32:0]                agd_asi_bist_wrdata;     // Debug wr data 
   input [7:0]                 itb_icd_waysel_c;   // read way select encoded
   input [7:0]                 agc_word_en_bf;     // read/write  word enable 

   input          ftp_ic_rd_req_bf;
   input          ftp_ic_wr_req_bf;
   input          ftp_ic_wr_ps_en_bf;
   input          ftp_asi_mbist_access_bf;

   input          vnw_ary;


   // outputs
   output [32:0]  icd_bus_0_instr_c ;
   output [32:0]  icd_bus_1_instr_c ;
   output [32:0]  icd_bus_2_instr_c ;
   output [32:0]  icd_bus_3_instr_c ;
   output         scan_out;
   output [4:0]   red_d_out  ;
   output [1:0]   red_en_out ;

   `ifndef FPGA 
   // synopsys translate_off
   `endif

   assign pce_ov = tcu_pce_ov;
   assign stop   = 1'b0 ;
   assign siclk  = tcu_aclk ;
   assign soclk  = tcu_bclk;
   assign wr_inhibit  = tcu_array_wr_inhibit;

// Temporary

// assign red_d_out[4:0]  = 5'b00000 ;
// assign red_en_out[1:0] = 2'b00 ;
//================================================
// Clock headers
//================================================
n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_in (
        .l2clk  (l2clk),
        .l1en   (1'b1),
        .se     (tcu_se_scancollar_in),
        .l1clk  (l1clk_in),
  .pce_ov(pce_ov),
  .stop(stop)
);

// l1clkhdr_ctl_macro l1ch_q0_in (
//         .l2clk  (l2clk),
//         .l1en	(ftp_icd_quad_0_en_bf),
//         .se     (tcu_se_scancollar_in),
//         .l1clk  (l1clk_q0_in)
// );

// l1clkhdr_ctl_macro l1ch_q1_in (
//         .l2clk  (l2clk),
//         .l1en	(ftp_icd_quad_1_en_bf),
//         .se     (tcu_se_scancollar_in),
//         .l1clk  (l1clk_q1_in)
// );

// l1clkhdr_ctl_macro l1ch_q2_in (
//         .l2clk  (l2clk),
//         .l1en	(ftp_icd_quad_2_en_bf),
//         .se     (tcu_se_scancollar_in),
//         .l1clk  (l1clk_q2_in)
// );

// l1clkhdr_ctl_macro l1ch_q3_in (
//         .l2clk  (l2clk),
//         .l1en	(ftp_icd_quad_3_en_bf),
//         .se     (tcu_se_scancollar_in),
//         .l1clk  (l1clk_q3_in)
// );


n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_q0_out (
        .l2clk  (l2clk),
        .l1en	(icd_quad_0_en_f_qual),
        .se     (tcu_se_scancollar_out),
        .l1clk  (l1clk_q0_out),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_q1_out (
        .l2clk  (l2clk),
        .l1en	(icd_quad_1_en_f_qual),
        .se     (tcu_se_scancollar_out),
        .l1clk  (l1clk_q1_out),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_q2_out (
        .l2clk  (l2clk),
        .l1en	(icd_quad_2_en_f_qual),
        .se     (tcu_se_scancollar_out),
        .l1clk  (l1clk_q2_out),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_q3_out (
        .l2clk  (l2clk),
        .l1en	(icd_quad_3_en_f_qual),
        .se     (tcu_se_scancollar_out),
        .l1clk  (l1clk_q3_out),
  .pce_ov(pce_ov),
  .stop(stop)
);


n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_free (
        .l2clk  (l2clk),
        .l1en	(1'b1),
        .se     (tcu_scan_en),
        .l1clk  (l1clk_free),
  .pce_ov(pce_ov),
  .stop(stop)
);

 n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_red_free (
  .l2clk  (l2clk),
  .l1en   (1'b1),
  .se     (1'b0),
  .l1clk  (l1clk_fuse_clk1),
  .pce_ov(1'b1),
  .stop(1'b0)
);

 n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_red_in (
  .l2clk  (l2clk),
  .l1en   (1'b1),
  .se     (tcu_se_scancollar_in),
  .l1clk  (l1clk_red_in),
  .pce_ov(1'b1),
  .stop(1'b0)
);

 n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_red_out (
  .l2clk  (l2clk),
  .l1en   (1'b1),
  .se     (tcu_se_scancollar_out),
  .l1clk  (l1clk_red_out),
  .pce_ov(1'b1),
  .stop(1'b0)
);

n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_int (
        .l2clk  (l2clk),
        .l1en   (1'b1),
        .se     (tcu_scan_en),
        .l1clk  (l1clk_int),
  .pce_ov(pce_ov),
  .stop(stop)
);

n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_out (
        .l2clk  (l2clk),
        .l1en   (1'b1),
        .se     (tcu_se_scancollar_out),
        .l1clk  (l1clk_out),
  .pce_ov(pce_ov),
  .stop(stop)
);

 n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro l1ch_wr (
        .l2clk  (l2clk),
        .l1en	(ftp_ic_wr_ps_en_bf),
        .se     (tcu_se_scancollar_in),
        .l1clk  (l1clk_wr),
  .pce_ov(pce_ov),
  .stop(stop)
);


   //----------------------------------------------------------------------
   // Declarations
   //----------------------------------------------------------------------

   // local signals


 ////////////////////////////////////////////////////////////
 //
 // Code start here
 //
 ////////////////////////////////////////////////////////////
 // Inverters before the flops                             //

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_9 index_inv    (
    .din(agd_ic_index_bf[10:2]),
    .dout(index_bf_l[10:2])
);


n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_3 wrway_inv    (
    .din(agc_fill_wrway_bf[2:0]),
    .dout(wrway_bf_l[2:0])
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_8 word_en_inv    (
    .din(agc_word_en_bf[7:0]),
    .dout(word_en_bf_l[7:0])
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 wr_inhibit_inv    (
    .din(wr_inhibit),
    .dout(wr_inhibit_in_l)
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 ic_rd_req_inv    (
    .din(ftp_ic_rd_req_bf),
    .dout(ic_rd_req_bf_l)
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 ic_wr_req_inv    (
    .din(ftp_ic_wr_req_bf),
    .dout(ic_wr_req_bf_l)
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_4 quad_en_in_inv    (
    .din ({ftp_icd_quad_0_en_bf, ftp_icd_quad_1_en_bf , ftp_icd_quad_2_en_bf , ftp_icd_quad_3_en_bf}),
    .dout({ftp_icd_quad_0_en_l_bf, ftp_icd_quad_1_en_l_bf , ftp_icd_quad_2_en_l_bf , ftp_icd_quad_3_en_l_bf}) 
);

n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 quad_0_en_latch  (
    .scan_in(quad_en_0_latch_scanin),
    .scan_out(quad_en_0_latch_scanout),
    .l1clk(l1clk_in),
    .d(ftp_icd_quad_0_en_l_bf),
    .latout_l(icd_quad_0_en_f_lat),
    .latout(icd_quad_0_en_f_lat_l),
  .siclk(siclk),
  .soclk(soclk)
    );
n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 quad_1_en_latch  (
    .scan_in(quad_en_1_latch_scanin),
    .scan_out(quad_en_1_latch_scanout),
    .l1clk(l1clk_in),
    .d(ftp_icd_quad_1_en_l_bf),
    .latout_l(icd_quad_1_en_f_lat),
    .latout(icd_quad_1_en_f_lat_l),
  .siclk(siclk),
  .soclk(soclk)
    );

n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 quad_2_en_latch  (
    .scan_in(quad_en_2_latch_scanin),
    .scan_out(quad_en_2_latch_scanout),
    .l1clk(l1clk_in),
    .d(ftp_icd_quad_2_en_l_bf),
    .latout_l(icd_quad_2_en_f_lat),
    .latout(icd_quad_2_en_f_lat_l),
  .siclk(siclk),
  .soclk(soclk)
    );

n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 quad_3_en_latch  (
    .scan_in(quad_en_3_latch_scanin),
    .scan_out(quad_en_3_latch_scanout),
    .l1clk(l1clk_in),
    .d(ftp_icd_quad_3_en_l_bf),
    .latout_l(icd_quad_3_en_f_lat),
    .latout(icd_quad_3_en_f_lat_l),
  .siclk(siclk),
  .soclk(soclk)
    );
assign icd_quad_0_en_f_lat_unused = icd_quad_0_en_f_lat ;
assign icd_quad_1_en_f_lat_unused = icd_quad_1_en_f_lat ;
assign icd_quad_2_en_f_lat_unused = icd_quad_2_en_f_lat ;
assign icd_quad_3_en_f_lat_unused = icd_quad_3_en_f_lat ;


 ///////////////////////////////////////////////////////////////
 // Flop the inputs                                           //
 ///////////////////////////////////////////////////////////////


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_9	index_reg_i		 (
  .scan_in(index_reg_i_scanin),
  .scan_out(index_reg_i_scanout),
  .l1clk ( l1clk_in				),
  .d ( index_bf_l[10:2]			),
  .latout_l( index_f[10:2] 			),
  .latout( {index_f_l[10:5],index_f_l_unused[4:2]}		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wrway_0_reg		 (
  .scan_in(wrway_0_reg_scanin),
  .scan_out(wrway_0_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( wrway_bf_l[0]			),
  .latout_l( wrway_f[0] 			),
  .latout( wrway_f_unused[0]		),
  .siclk(siclk),
  .soclk(soclk));

 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wrway_1_reg		 (
  .scan_in(wrway_1_reg_scanin),
  .scan_out(wrway_1_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( wrway_bf_l[1]			),
  .latout_l( wrway_f[1] 			),
  .latout( wrway_f_unused[1]		),
  .siclk(siclk),
  .soclk(soclk));

 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wrway_2_reg		 (
  .scan_in(wrway_2_reg_scanin),
  .scan_out(wrway_2_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( wrway_bf_l[2]			),
  .latout_l( wrway_f[2] 			),
  .latout( wrway_f_unused[2]		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wr_word_en_0_reg		 (
  .scan_in(wr_word_en_0_reg_scanin),
  .scan_out(wr_word_en_0_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( word_en_bf_l[0]			),
  .latout_l( word_en_f[0]			),
  .latout( word_en_f_unused[0]		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wr_word_en_1_reg		 (
  .scan_in(wr_word_en_1_reg_scanin),
  .scan_out(wr_word_en_1_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( word_en_bf_l[1]			),
  .latout_l( word_en_f[1]			),
  .latout( word_en_f_unused[1]		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wr_word_en_2_reg		 (
  .scan_in(wr_word_en_2_reg_scanin),
  .scan_out(wr_word_en_2_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( word_en_bf_l[2]			),
  .latout_l( word_en_f[2]			),
  .latout( word_en_f_unused[2]		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wr_word_en_3_reg		 (
  .scan_in(wr_word_en_3_reg_scanin),
  .scan_out(wr_word_en_3_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( word_en_bf_l[3]			),
  .latout_l( word_en_f[3]			),
  .latout( word_en_f_unused[3]		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wr_word_en_4_reg		 (
  .scan_in(wr_word_en_4_reg_scanin),
  .scan_out(wr_word_en_4_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( word_en_bf_l[4]			),
  .latout_l( word_en_f[4]			),
  .latout( word_en_f_unused[4]		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wr_word_en_5_reg		 (
  .scan_in(wr_word_en_5_reg_scanin),
  .scan_out(wr_word_en_5_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( word_en_bf_l[5]			),
  .latout_l( word_en_f[5]			),
  .latout( word_en_f_unused[5]		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wr_word_en_6_reg		 (
  .scan_in(wr_word_en_6_reg_scanin),
  .scan_out(wr_word_en_6_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( word_en_bf_l[6]			),
  .latout_l( word_en_f[6]			),
  .latout( word_en_f_unused[6]		),
  .siclk(siclk),
  .soclk(soclk));


 n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	wr_word_en_7_reg		 (
  .scan_in(wr_word_en_7_reg_scanin),
  .scan_out(wr_word_en_7_reg_scanout),
  .l1clk ( l1clk_in				),
  .d ( word_en_bf_l[7]			),
  .latout_l( word_en_f[7]			),
  .latout( word_en_f_unused[7]		),
  .siclk(siclk),
  .soclk(soclk));


   n2_icd_sp_16p5kb_cust_msffi_ctl_macro__fs_1__width_4 quad_en_reg  (
     .scan_in(quad_en_reg_scanin[3:0]),
     .scan_out(quad_en_reg_scanout[3:0]),
    .l1clk(l1clk_in),
    .din( {ftp_icd_quad_3_en_bf,ftp_icd_quad_2_en_bf,ftp_icd_quad_1_en_bf,ftp_icd_quad_0_en_bf}),
    .q_l({icd_quad_3_en_l_f,icd_quad_2_en_l_f,icd_quad_1_en_l_f,icd_quad_0_en_l_f}),
  .siclk(siclk),
  .soclk(soclk) 
    );

n2_icd_sp_16p5kb_cust_inv_macro__width_4 quad_inv  (
    .din ({icd_quad_3_en_l_f,icd_quad_2_en_l_f,icd_quad_1_en_l_f,icd_quad_0_en_l_f}) ,
    .dout({icd_quad_3_en_f,icd_quad_2_en_f,icd_quad_1_en_f,icd_quad_0_en_f}) 
    );

   n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 wrreq_reg  (
    .scan_in(wrreq_reg_scanin[0:0]),
    .scan_out(wrreq_reg_scanout[0:0]),
    .l1clk(l1clk_in),
    .d(ic_wr_req_bf_l),
    .latout_l(wrreq_f),
    .latout(wrreq_f_l_unused),
  .siclk(siclk),
  .soclk(soclk)
    );


n2_icd_sp_16p5kb_cust_msffi_ctl_macro__width_1	wrreq_reg_b			 (
  .scan_in(wrreq_reg_b_scanin),
  .scan_out(wrreq_reg_b_scanout),
  .l1clk ( l1clk_in				),
  .din ( ftp_ic_wr_req_bf			),
  .q_l ( wrreq_f_l				),
  .siclk(siclk),
  .soclk(soclk));

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1 ftp_access_f_reg  (
     .scan_in(ftp_access_f_reg_scanin[0:0]),
     .scan_out(ftp_access_f_reg_scanout[0:0]),
    .l1clk(l1clk_in),
    .din(ftp_asi_mbist_access_bf),
    .dout(asi_access_f),
  .siclk(siclk),
  .soclk(soclk)
    );


n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1	rdreq_reg			 (
  .scan_in(rdreq_reg_scanin),
  .scan_out(rdreq_reg_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( ic_rd_req_bf_l                   ),
  .latout ( rdreq_f_l_unused                           ),
  .latout_l ( rdreq_f_unused                          ),
  .siclk(siclk),
  .soclk(soclk));


n2_icd_sp_16p5kb_cust_msff_ctl_macro__width_1	rdreq_reg_b			 (
  .scan_in(rdreq_reg_b_scanin),
  .scan_out(rdreq_reg_b_scanout),
  .l1clk ( l1clk_in				),
  .din ( ftp_ic_rd_req_bf			),
  .dout ( rdreq_f				),
  .siclk(siclk),
  .soclk(soclk));


   // write data regsiter

n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 wrdata_reg_lo_1_mux     (
    .din0({agd_asi_bist_wrdata[32:0],agd_asi_bist_wrdata[32:0]}),
    .din1(cmu_ic_data[65:0]),
    .sel0(ftp_asi_mbist_access_bf),
    .dout(wrdata_in[65:0])
);


   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q0_0  (
     .scan_in(wrdata_q0_0_scanin[32:0]),
     .scan_out(wrdata_q0_0_scanout[32:0]),
    .l1clk(l1clk_wr),
    .din(wrdata_in[32:0]),
    .dout(wrdata_f[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q1_1  (
     .scan_in(wrdata_q1_1_scanin[32:0]),
     .scan_out(wrdata_q1_1_scanout[32:0]),
    .l1clk(l1clk_wr),
    .din(wrdata_in[65:33]),
    .dout(wrdata_f[65:33]),
  .siclk(siclk),
  .soclk(soclk)
    );

n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 wrdata_reg_lo_2_mux     (
    .din0({agd_asi_bist_wrdata[32:0],agd_asi_bist_wrdata[32:0]}),
    .din1(cmu_ic_data[131:66]),
    .sel0(ftp_asi_mbist_access_bf),
    .dout(wrdata_in[131:66])
);

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q2_2  (
     .scan_in(wrdata_q2_2_scanin[32:0]),
     .scan_out(wrdata_q2_2_scanout[32:0]),
    .l1clk(l1clk_wr),
    .din(wrdata_in[98:66]),
    .dout(wrdata_f[98:66]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q3_3  (
     .scan_in(wrdata_q3_3_scanin[32:0]),
     .scan_out(wrdata_q3_3_scanout[32:0]),
    .l1clk(l1clk_wr),
    .din(wrdata_in[131:99]),
    .dout(wrdata_f[131:99]),
  .siclk(siclk),
  .soclk(soclk)
    );


n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 wrdata_reg_hi_1_mux     (
    .din0({agd_asi_bist_wrdata[32:0],agd_asi_bist_wrdata[32:0]}),
    .din1(cmu_ic_data[197:132]),
    .sel0(ftp_asi_mbist_access_bf),
    .dout(wrdata_in[197:132])
);

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q0_4  (
     .scan_in(wrdata_q0_4_scanin[32:0]),
     .scan_out(wrdata_q0_4_scanout[32:0]),
    .l1clk(l1clk_wr),
    .din(wrdata_in[164:132]),
    .dout(wrdata_f[164:132]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q1_5  (
     .scan_in(wrdata_q1_5_scanin[32:0]),
     .scan_out(wrdata_q1_5_scanout[32:0]),
    .l1clk(l1clk_wr),
    .din(wrdata_in[197:165]),
    .dout(wrdata_f[197:165]),
  .siclk(siclk),
  .soclk(soclk)
    );

n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 wrdata_reg_hi_2_mux     (
    .din0({agd_asi_bist_wrdata[32:0],agd_asi_bist_wrdata[32:0]}),
    .din1(cmu_ic_data[263:198]),
    .sel0(ftp_asi_mbist_access_bf),
    .dout(wrdata_in[263:198])
);


   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q2_6  (
     .scan_in(wrdata_q2_6_scanin[32:0]),
     .scan_out(wrdata_q2_6_scanout[32:0]),
    .l1clk(l1clk_wr),
    .din(wrdata_in[230:198]),
    .dout(wrdata_f[230:198]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 wrdata_q3_7  (
     .scan_in(wrdata_q3_7_scanin[32:0]),
     .scan_out(wrdata_q3_7_scanout[32:0]),
    .l1clk(l1clk_wr),
    .din(wrdata_in[263:231]),
    .dout(wrdata_f[263:231]),
  .siclk(siclk),
  .soclk(soclk)
    );


  n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_5  red_d_reg  (
     .scan_in(red_d_reg_scanin[4:0]),
     .scan_out(red_d_reg_scanout[4:0]),
    .l1clk(l1clk_red_in),
    .din(red_d_in[4:0]),
    .dout(red_d_ff[4:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

  n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_2  red_en_reg  (
     .scan_in(red_en_reg_scanin[1:0]),
     .scan_out(red_en_reg_scanout[1:0]),
    .l1clk(l1clk_red_in),
    .din(red_en_in[1:0]),
    .dout(red_en_ff[1:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

  n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_4  rid_reg  (
     .scan_in(rid_reg_scanin[3:0]),
     .scan_out(rid_reg_scanout[3:0]),
    .l1clk(l1clk_red_in),
    .din(rid_in[3:0]),
    .dout(rid_ff[3:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

  n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1  red_wen_reg  (
     .scan_in(red_wen_reg_scanin[0:0]),
     .scan_out(red_wen_reg_scanout[0:0]),
    .l1clk(l1clk_red_in),
    .din(red_wen),
    .dout(red_wen_ff_and),
  .siclk(siclk),
  .soclk(soclk)
    );

n2_icd_sp_16p5kb_cust_and_macro__ports_2__width_1 red_wen_wrinhib_and_gate      (
    .din0(red_wen_ff_and),
    .din1(wr_inhibit_in_l),
    .dout(red_wen_ff)
);

  n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1  red_arst_reg  (
     .scan_in(red_arst_reg_scanin[0:0]),
     .scan_out(red_arst_reg_scanout[0:0]),
    .l1clk(l1clk_red_in),
    .din(red_arst),
    .dout(red_arst_ff_and),
  .siclk(siclk),
  .soclk(soclk)
    );

n2_icd_sp_16p5kb_cust_and_macro__ports_2__width_1 red_arst_wrinhib_and_gate     (
    .din0(red_arst_ff_and),
    .din1(wr_inhibit_in_l),
    .dout(red_arst_ff)
);


////////////////////////////////////////////////////
// C-stage flops and muxes on the input side      //
////////////////////////////////////////////////////

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_8 way_f_reg  (
     .scan_in(way_f_reg_scanin[7:0]),
     .scan_out(way_f_reg_scanout[7:0]),
    .l1clk(l1clk_int),
    .din(wrway_dec_bf[7:0]),
    .dout(wrway_dec_f[7:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_8 way_c_reg  (
     .scan_in(way_c_reg_scanin[7:0]),
     .scan_out(way_c_reg_scanout[7:0]),
    .l1clk(l1clk_out),
    .din(wrway_dec_f[7:0]),
    .dout(wrway_dec_c[7:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1 ftp_access_c_reg  (
     .scan_in(ftp_access_c_reg_scanin[0:0]),
     .scan_out(ftp_access_c_reg_scanout[0:0]),
    .l1clk(l1clk_out),
    .din(asi_access_f),
    .dout(asi_access_c),
  .siclk(siclk),
  .soclk(soclk)
    );

n2_icd_sp_16p5kb_cust_msffi_ctl_macro__width_1 ftp_access_c_dum          (
  .scan_in(ftp_access_c_dum_scanin),
  .scan_out(ftp_access_c_dum_scanout),
  .l1clk ( l1clk_out             ),
  .din ( asi_access_f           ),
  .q_l ( asi_access_c_l             ),
  .siclk(siclk),
  .soclk(soclk));

n2_icd_sp_16p5kb_cust_inv_macro__width_1 asi_access_c_l_invt   (
    .din(asi_access_c_l),
    .dout(asi_access_c_l_inv)
);

n2_icd_sp_16p5kb_cust_inv_macro__width_1 asi_access_c_invt   (
    .din(asi_access_c),
    .dout(asi_access_c_inv)
);


n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_2__stack_50c__width_8 way_sel_mux  (
 .din1(wrway_dec_c[7:0]),
 .din0(itb_icd_waysel_c[7:0]),
 .sel0 ( asi_access_c_inv),
 .sel1 ( asi_access_c_l_inv),
 .dout( muxed_way_sel_c[7:0] ));


//////////////////////////////////////////////////////////////////////////////////////////////
//   assign i4_i0_sel_upper = ~(index_f[4:2] == 3'b000) ;
//   assign i5_i1_sel_upper = ~( ~index_f[4] & ~index_f[3] ); 
//   assign i6_i2_sel_upper = ~((~index_f[4] & ~index_f[3]) | (~index_f[4] & ~index_f[2]));
//   assign i7_i3_sel_upper =     index_f[4] ;
//////////////////////////////////////////////////////////////////////////////////////////////
n2_icd_sp_16p5kb_cust_or_macro__ports_3__stack_50c__width_1 i4_i0_sel_upper_or     (
    .din0(index_f[4]),
    .din1(index_f[3]),
    .din2(index_f[2]),
    .dout(i4_i0_sel_upper)
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 i4_i0_sel_upper_gate_l    (
    .din(i4_i0_sel_upper),
    .dout(i4_i0_sel_upper_)
);

n2_icd_sp_16p5kb_cust_or_macro__ports_2__stack_50c__width_1 i5_i1_sel_upper_or     (
    .din0(index_f[4]),
    .din1(index_f[3]),
    .dout(i5_i1_sel_upper)
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 i5_i1_sel_upper_gate_l    (
    .din(i5_i1_sel_upper),
    .dout(i5_i1_sel_upper_)
);

n2_icd_sp_16p5kb_cust_or_macro__ports_2__stack_50c__width_1 i6_i2_sel_upper_or_2_gate     (
    .din0(index_f[4]),
    .din1(index_f[2]),
    .dout(i6_i2_sel_upper_or_2)
);

n2_icd_sp_16p5kb_cust_and_macro__ports_2__stack_50c__width_1 i6_i2_sel_upper_and_gate     (
    .din0(i6_i2_sel_upper_or_2),
    .din1(i5_i1_sel_upper),
    .dout(i6_i2_sel_upper)
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 i6_i2_sel_upper_gate_l    (
    .din(i6_i2_sel_upper),
    .dout(i6_i2_sel_upper_)
);

n2_icd_sp_16p5kb_cust_buff_macro__stack_50c__width_1 i7_i3_sel_upper_gate    (
    .din(index_f[4]),
    .dout(i7_i3_sel_upper)
);

n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 i7_i3_sel_upper_gate_l    (
    .din(i7_i3_sel_upper),
    .dout(i7_i3_sel_upper_)
);
//////////////////////////////////////////////////////////
// write_enable                                         //
//////////////////////////////////////////////////////////

// tisram_msff_macro	wr_inh_ff		(width=1) (
//   .scan_in(wr_inh_ff_scanin),
//   .scan_out(wr_inh_ff_scanout),
//   .l1clk ( l1clk_in				),
//   .d ( wr_inhibit_in_l					),
//   .latout_l( wr_inhibit_unused			),
//   .latout( wr_inhibit_l		));

n2_icd_sp_16p5kb_cust_nand_macro__ports_3__stack_50c__width_8 wr_word_en_nand     (
    .din0({8{wr_inhibit_in_l}}),
    .din1({8{wrreq_f}}),
    .din2(word_en_f[7:0]),
    .dout(wr_word_en_f_l[7:0])
);


//////////////////////////////////////////////////////////
// Disable reads when quad is not enabled
//////////////////////////////////////////////////////////
n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 rd_req_q_0_en        (
    .din0(icd_quad_0_en_f),
    .din1(rdreq_f),
    .din2(wrreq_f_l),
    .din3(wr_inhibit_in_l),
    .dout(rdreq_f_q0_l)
);

n2_icd_sp_16p5kb_cust_inv_macro rd_req_q_0_en_inv ( 
    .din  (rdreq_f_q0_l),
    .dout (rdreq_f_q0)) ; 

n2_icd_sp_16p5kb_cust_and_macro quad_0_en_qualify (
     .din0 (rdreq_f_q0)       ,
     .din1 (icd_quad_0_en_f)  ,
     .dout (icd_quad_0_en_f_qual)) ;


n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 rd_req_q_1_en        (
    .din0(icd_quad_1_en_f),
    .din1(rdreq_f),
    .din2(wrreq_f_l),
    .din3(wr_inhibit_in_l),
    .dout(rdreq_f_q1_l)
);

n2_icd_sp_16p5kb_cust_inv_macro rd_req_q_1_en_inv ( 
    .din  (rdreq_f_q1_l),
    .dout (rdreq_f_q1)) ; 

n2_icd_sp_16p5kb_cust_and_macro quad_1_en_qualify (
     .din0 (rdreq_f_q1)       ,
     .din1 (icd_quad_1_en_f)  ,
     .dout (icd_quad_1_en_f_qual)) ;


n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 rd_req_q_2_en        (
    .din0(icd_quad_2_en_f),
    .din1(rdreq_f),
    .din2(wrreq_f_l),
    .din3(wr_inhibit_in_l),
    .dout(rdreq_f_q2_l)
);

n2_icd_sp_16p5kb_cust_inv_macro rd_req_q_2_en_inv ( 
    .din  (rdreq_f_q2_l),
    .dout (rdreq_f_q2)) ; 

n2_icd_sp_16p5kb_cust_and_macro quad_2_en_qualify (
     .din0 (rdreq_f_q2)       ,
     .din1 (icd_quad_2_en_f)  ,
     .dout (icd_quad_2_en_f_qual)) ;


n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 rd_req_q_3_en        (
    .din0(icd_quad_3_en_f),
    .din1(rdreq_f),
    .din2(wrreq_f_l),
    .din3(wr_inhibit_in_l),
    .dout(rdreq_f_q3_l)
);


n2_icd_sp_16p5kb_cust_inv_macro rd_req_q_3_en_inv ( 
    .din  (rdreq_f_q3_l),
    .dout (rdreq_f_q3)) ; 

n2_icd_sp_16p5kb_cust_and_macro quad_3_en_qualify (
     .din0 (rdreq_f_q3)       ,
     .din1 (icd_quad_3_en_f)  ,
     .dout (icd_quad_3_en_f_qual)) ;


//////////////////////////////////////////////////////////
// 4:8 decode                                           //
//////////////////////////////////////////////////////////
n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_8 wr_way_decode    (
        .din0   (8'b00000001),
        .din1   (8'b00000010),
        .din2   (8'b00000100),
        .din3   (8'b00001000),
        .din4   (8'b00010000),
        .din5   (8'b00100000),
        .din6   (8'b01000000),
        .din7   (8'b10000000),
        .sel    (wrway_f[2:0]), // This changed
        .dout   (wrway_dec_bf[7:0])
);

n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_8 wr_way_decode_l    (
        .din0   (8'b11111110),
        .din1   (8'b11111101),
        .din2   (8'b11111011),
        .din3   (8'b11110111),
        .din4   (8'b11101111),
        .din5   (8'b11011111),
        .din6   (8'b10111111),
        .din7   (8'b01111111),
        .sel    (wrway_f[2:0]),
        .dout   (wrway_dec_f_[7:0])
);

//////////////////////////////////////////////////////////
n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_8 rid_sel_mux0    (
        .din0   (8'b00000001),
        .din1   (8'b00000010),
        .din2   (8'b00000100),
        .din3   (8'b00001000),
        .din4   (8'b00010000),
        .din5   (8'b00100000),
        .din6   (8'b01000000),
        .din7   (8'b10000000),
        .sel    (rid_ff[2:0]),
        .dout   (rid_sel_dec[7:0])
);

n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__width_16 rid_sel_mux1    (
        .din0   ({rid_sel_dec[7:0],8'b00000000}),
        .din1   ({8'b00000000,rid_sel_dec[7:0]}),
        .sel0    (rid_ff[3]),
        .dout   (rid_sel[15:0])
);


/////////////////////////////////////////////////////////////////
// Instantiate each way ARRAY.                                 //
/////////////////////////////////////////////////////////////////
// The Icache is divided in four quads.                        //
// Each quad    is made of two Banks.                          //
// Each quad    has two words for all the 8 ways.              //
// ----------------------------------------------------------- //
// quad_0 has I0/I4 for ways 7 to 0                            //
// quad-1 has I1/I5 for ways 7 to 0                            //
// quad-2 has I2/I6 for ways 7 to 0                            //
// quad-3 has I3/I7 for ways 7 to 0                            //
// ----------------------------------------------------------- //
// Inside quad-0 top bank has ways 3 to 0                      //
// Inside quad-0 bottom bank has ways 7 to 4                   //
// ----------------------------------------------------------- //
// Other quads   are arranged similarly.                       //
///////////////////////////////////////////////////////////////// 

///////////////////////////////////////////////////////////////// 
///////////////////////////////////////////////////////////////// 
// quad-0                                                      //
///////////////////////////////////////////////////////////////// 
//////////////////////////////////////////////
// quad-0                                   //
/////////////////////////////////////////////
n2_icd_quad_array        quad_0 	      (.adr_ac_h(index_f[10:5]),
                                               .adr_ac_l(index_f_l[10:5]),
                                               .rd_en_a_l(rdreq_f_q0_l),
                                               .quaden_f_l(icd_quad_0_en_f_lat_l),
                                               .wr_word_en_ac_l({wr_word_en_f_l[4],wr_word_en_f_l[0]}),
                                               .wr_waysel0_ac_l(wrway_dec_f_[7:0]),
                                               .wr_waysel1_ac_l(wrway_dec_f_[7:0]),
                                               .din0_a(wrdata_f[32:0]),
                                               .din1_a(wrdata_f[164:132]),
                                               .dout_wy0_bc(rd_data_w0_i4_or_i0[32:0]),
                                               .dout_wy1_bc(rd_data_w1_i4_or_i0[32:0]),
                                               .dout_wy2_bc(rd_data_w2_i4_or_i0[32:0]),
                                               .dout_wy3_bc(rd_data_w3_i4_or_i0[32:0]),
                                               .dout_wy4_bc(rd_data_w4_i4_or_i0[32:0]),
                                               .dout_wy5_bc(rd_data_w5_i4_or_i0[32:0]),
                                               .dout_wy6_bc(rd_data_w6_i4_or_i0[32:0]),
                                               .dout_wy7_bc(rd_data_w7_i4_or_i0[32:0]),
						.reg_d_lft_top(reg_d_q0_w3_w0_lft_d[4:0]) ,
						.reg_en_lft_top(reg_d_q0_w3_w0_lft_en[1:0]) ,
						.reg_d_rgt_top(reg_d_q0_w3_w0_rgt_d[4:0]) ,
						.reg_en_rgt_top(reg_d_q0_w3_w0_rgt_en[1:0]) ,
						.reg_d_lft_bot(reg_d_q0_w7_w4_lft_d[4:0]) ,
						.reg_en_lft_bot(reg_d_q0_w7_w4_lft_en[1:0]) ,
						.reg_d_rgt_bot(reg_d_q0_w7_w4_rgt_d[4:0]) ,
						.reg_en_rgt_bot(reg_d_q0_w7_w4_rgt_en[1:0]) ,
                                               .red_d_ff(red_d_ff[4:0]),
                                               .red_en_ff(red_en_ff[1:0]),
                                               .rid_sel(rid_sel[3:0]) ,
   					       .red_wen_ff(red_wen_ff) ,
   					       .red_arst_ff(red_arst_ff), 
                                               .rd_worden_ac_l({i4_i0_sel_upper_,i4_i0_sel_upper}),
                                               .l1clk_fuse(l1clk_fuse_clk1),
                                               .l1clk(l1clk_free),
  .vnw_ary(vnw_ary)
                                               );


///////////////////////////////////////////////////////////////// 
///////////////////////////////////////////////////////////////// 
// quad-1                                                      //
///////////////////////////////////////////////////////////////// 
n2_icd_quad_array        quad_1 	      (.adr_ac_h(index_f[10:5]),
                                               .adr_ac_l(index_f_l[10:5]),
                                               .rd_en_a_l(rdreq_f_q1_l),
                                               .quaden_f_l(icd_quad_1_en_f_lat_l),
                                               .wr_word_en_ac_l({wr_word_en_f_l[5],wr_word_en_f_l[1]}),
                                               .wr_waysel0_ac_l(wrway_dec_f_[7:0]),
                                               .wr_waysel1_ac_l(wrway_dec_f_[7:0]),
                                               .din0_a(wrdata_f[65:33]),
                                               .din1_a(wrdata_f[197:165]),
                                               .dout_wy0_bc(rd_data_w0_i5_or_i1[32:0]),
                                               .dout_wy1_bc(rd_data_w1_i5_or_i1[32:0]),
                                               .dout_wy2_bc(rd_data_w2_i5_or_i1[32:0]),
                                               .dout_wy3_bc(rd_data_w3_i5_or_i1[32:0]),
                                               .dout_wy4_bc(rd_data_w4_i5_or_i1[32:0]),
                                               .dout_wy5_bc(rd_data_w5_i5_or_i1[32:0]),
                                               .dout_wy6_bc(rd_data_w6_i5_or_i1[32:0]),
                                               .dout_wy7_bc(rd_data_w7_i5_or_i1[32:0]),
						.reg_d_lft_top(reg_d_q1_w3_w0_lft_d[4:0]) ,
						.reg_en_lft_top(reg_d_q1_w3_w0_lft_en[1:0]) ,
						.reg_d_rgt_top(reg_d_q1_w3_w0_rgt_d[4:0]) ,
						.reg_en_rgt_top(reg_d_q1_w3_w0_rgt_en[1:0]) ,
						.reg_d_lft_bot(reg_d_q1_w7_w4_lft_d[4:0]) ,
						.reg_en_lft_bot(reg_d_q1_w7_w4_lft_en[1:0]) ,
						.reg_d_rgt_bot(reg_d_q1_w7_w4_rgt_d[4:0]) ,
						.reg_en_rgt_bot(reg_d_q1_w7_w4_rgt_en[1:0]) ,
                                               .red_d_ff(red_d_ff[4:0]),
                                               .red_en_ff(red_en_ff[1:0]),
                                               .rid_sel(rid_sel[7:4]) ,
   					       .red_wen_ff(red_wen_ff) ,
   					       .red_arst_ff(red_arst_ff), 
                                               .rd_worden_ac_l({i5_i1_sel_upper_,i5_i1_sel_upper}),
                                               .l1clk_fuse(l1clk_fuse_clk1),
                                               .l1clk(l1clk_free),
  .vnw_ary(vnw_ary)
                                               );


///////////////////////////////////////////////////////////////// 
///////////////////////////////////////////////////////////////// 
// quad-2                                                      //
///////////////////////////////////////////////////////////////// 
n2_icd_quad_array        quad_2 	      (.adr_ac_h(index_f[10:5]),
                                               .adr_ac_l(index_f_l[10:5]),
                                               .rd_en_a_l(rdreq_f_q2_l),
                                               .quaden_f_l(icd_quad_2_en_f_lat_l),
                                               .wr_word_en_ac_l({wr_word_en_f_l[6],wr_word_en_f_l[2]}),
                                               .wr_waysel0_ac_l(wrway_dec_f_[7:0]),
                                               .wr_waysel1_ac_l(wrway_dec_f_[7:0]),
                                               .din0_a(wrdata_f[98:66]),
                                               .din1_a(wrdata_f[230:198]),
                                               .dout_wy0_bc(rd_data_w0_i6_or_i2[32:0]),
                                               .dout_wy1_bc(rd_data_w1_i6_or_i2[32:0]),
                                               .dout_wy2_bc(rd_data_w2_i6_or_i2[32:0]),
                                               .dout_wy3_bc(rd_data_w3_i6_or_i2[32:0]),
                                               .dout_wy4_bc(rd_data_w4_i6_or_i2[32:0]),
                                               .dout_wy5_bc(rd_data_w5_i6_or_i2[32:0]),
                                               .dout_wy6_bc(rd_data_w6_i6_or_i2[32:0]),
                                               .dout_wy7_bc(rd_data_w7_i6_or_i2[32:0]),
						.reg_d_lft_top(reg_d_q2_w3_w0_lft_d[4:0]) ,
						.reg_en_lft_top(reg_d_q2_w3_w0_lft_en[1:0]) ,
						.reg_d_rgt_top(reg_d_q2_w3_w0_rgt_d[4:0]) ,
						.reg_en_rgt_top(reg_d_q2_w3_w0_rgt_en[1:0]) ,
						.reg_d_lft_bot(reg_d_q2_w7_w4_lft_d[4:0]) ,
						.reg_en_lft_bot(reg_d_q2_w7_w4_lft_en[1:0]) ,
						.reg_d_rgt_bot(reg_d_q2_w7_w4_rgt_d[4:0]) ,
						.reg_en_rgt_bot(reg_d_q2_w7_w4_rgt_en[1:0]) ,
                                               .red_d_ff(red_d_ff[4:0]),
                                               .red_en_ff(red_en_ff[1:0]),
                                               .rid_sel(rid_sel[11:8]) ,
   					       .red_wen_ff(red_wen_ff) ,
   					       .red_arst_ff(red_arst_ff), 
                                               .rd_worden_ac_l({i6_i2_sel_upper_,i6_i2_sel_upper}),
                                               .l1clk_fuse(l1clk_fuse_clk1),
                                               .l1clk(l1clk_free),
  .vnw_ary(vnw_ary)
                                               );


///////////////////////////////////////////////////////////////// 
///////////////////////////////////////////////////////////////// 
// quad-3                                                      //
///////////////////////////////////////////////////////////////// 
n2_icd_quad_array        quad_3 	      (.adr_ac_h(index_f[10:5]),
                                               .adr_ac_l(index_f_l[10:5]),
                                               .rd_en_a_l(rdreq_f_q3_l),
                                               .quaden_f_l(icd_quad_3_en_f_lat_l),
                                               .wr_word_en_ac_l({wr_word_en_f_l[7],wr_word_en_f_l[3]}),
                                               .wr_waysel0_ac_l(wrway_dec_f_[7:0]),
                                               .wr_waysel1_ac_l(wrway_dec_f_[7:0]),
                                               .din0_a(wrdata_f[131:99]),
                                               .din1_a(wrdata_f[263:231]),
                                               .dout_wy0_bc(rd_data_w0_i7_or_i3[32:0]),
                                               .dout_wy1_bc(rd_data_w1_i7_or_i3[32:0]),
                                               .dout_wy2_bc(rd_data_w2_i7_or_i3[32:0]),
                                               .dout_wy3_bc(rd_data_w3_i7_or_i3[32:0]),
                                               .dout_wy4_bc(rd_data_w4_i7_or_i3[32:0]),
                                               .dout_wy5_bc(rd_data_w5_i7_or_i3[32:0]),
                                               .dout_wy6_bc(rd_data_w6_i7_or_i3[32:0]),
                                               .dout_wy7_bc(rd_data_w7_i7_or_i3[32:0]),
						.reg_d_lft_top(reg_d_q3_w3_w0_lft_d[4:0]) ,
						.reg_en_lft_top(reg_d_q3_w3_w0_lft_en[1:0]) ,
						.reg_d_rgt_top(reg_d_q3_w3_w0_rgt_d[4:0]) ,
						.reg_en_rgt_top(reg_d_q3_w3_w0_rgt_en[1:0]) ,
						.reg_d_lft_bot(reg_d_q3_w7_w4_lft_d[4:0]) ,
						.reg_en_lft_bot(reg_d_q3_w7_w4_lft_en[1:0]) ,
						.reg_d_rgt_bot(reg_d_q3_w7_w4_rgt_d[4:0]) ,
						.reg_en_rgt_bot(reg_d_q3_w7_w4_rgt_en[1:0]) ,
                                               .red_d_ff(red_d_ff[4:0]),
                                               .red_en_ff(red_en_ff[1:0]),
                                               .rid_sel(rid_sel[15:12]) ,
   					       .red_wen_ff(red_wen_ff) ,
   					       .red_arst_ff(red_arst_ff), 
                                               .rd_worden_ac_l({i7_i3_sel_upper_,i7_i3_sel_upper}),
                                               .l1clk_fuse(l1clk_fuse_clk1),
                                               .l1clk(l1clk_free),
  .vnw_ary(vnw_ary)
                                               );


//////////////////////////////////////////////////////////////////////////
// Mux the instructions in each way to four buses                       //
//////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////
// Flop all the way outputs.                                            //
//////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////
// way 0 flops                                  //
//////////////////////////////////////////////////
   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w0_reg  (
     .scan_in(data_bus_0_w0_reg_scanin[32:0]),
     .scan_out(data_bus_0_w0_reg_scanout[32:0]),
    .l1clk(l1clk_q0_out),
    .din(rd_data_w0_i4_or_i0[32:0]),
    .dout(data_bus_0_w0_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w0_reg  (
     .scan_in(data_bus_1_w0_reg_scanin[32:0]),
     .scan_out(data_bus_1_w0_reg_scanout[32:0]),
    .l1clk(l1clk_q1_out),
    .din(rd_data_w0_i5_or_i1[32:0]),
    .dout(data_bus_1_w0_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );


   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w0_reg  (
     .scan_in(data_bus_2_w0_reg_scanin[32:0]),
     .scan_out(data_bus_2_w0_reg_scanout[32:0]),
    .l1clk(l1clk_q2_out),
    .din(rd_data_w0_i6_or_i2[32:0]),
    .dout(data_bus_2_w0_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w0_reg  (
     .scan_in(data_bus_3_w0_reg_scanin[32:0]),
     .scan_out(data_bus_3_w0_reg_scanout[32:0]),
    .l1clk(l1clk_q3_out),
    .din(rd_data_w0_i7_or_i3[32:0]),
    .dout(data_bus_3_w0_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
//////////////////////////////////////////////////
// way 1 flops                                  //
//////////////////////////////////////////////////
   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w1_reg  (
     .scan_in(data_bus_0_w1_reg_scanin[32:0]),
     .scan_out(data_bus_0_w1_reg_scanout[32:0]),
    .l1clk(l1clk_q0_out),
    .din(rd_data_w1_i4_or_i0[32:0]),
    .dout(data_bus_0_w1_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w1_reg  (
     .scan_in(data_bus_1_w1_reg_scanin[32:0]),
     .scan_out(data_bus_1_w1_reg_scanout[32:0]),
    .l1clk(l1clk_q1_out),
    .din(rd_data_w1_i5_or_i1[32:0]),
    .dout(data_bus_1_w1_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );


   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w1_reg  (
     .scan_in(data_bus_2_w1_reg_scanin[32:0]),
     .scan_out(data_bus_2_w1_reg_scanout[32:0]),
    .l1clk(l1clk_q2_out),
    .din(rd_data_w1_i6_or_i2[32:0]),
    .dout(data_bus_2_w1_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w1_reg  (
     .scan_in(data_bus_3_w1_reg_scanin[32:0]),
     .scan_out(data_bus_3_w1_reg_scanout[32:0]),
    .l1clk(l1clk_q3_out),
    .din(rd_data_w1_i7_or_i3[32:0]),
    .dout(data_bus_3_w1_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
//////////////////////////////////////////////////
// way 2 flops                                  //
//////////////////////////////////////////////////
   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w2_reg  (
     .scan_in(data_bus_0_w2_reg_scanin[32:0]),
     .scan_out(data_bus_0_w2_reg_scanout[32:0]),
    .l1clk(l1clk_q0_out),
    .din(rd_data_w2_i4_or_i0[32:0]),
    .dout(data_bus_0_w2_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w2_reg  (
     .scan_in(data_bus_1_w2_reg_scanin[32:0]),
     .scan_out(data_bus_1_w2_reg_scanout[32:0]),
    .l1clk(l1clk_q1_out),
    .din(rd_data_w2_i5_or_i1[32:0]),
    .dout(data_bus_1_w2_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w2_reg  (
     .scan_in(data_bus_2_w2_reg_scanin[32:0]),
     .scan_out(data_bus_2_w2_reg_scanout[32:0]),
    .l1clk(l1clk_q2_out),
    .din(rd_data_w2_i6_or_i2[32:0]),
    .dout(data_bus_2_w2_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w2_reg  (
     .scan_in(data_bus_3_w2_reg_scanin[32:0]),
     .scan_out(data_bus_3_w2_reg_scanout[32:0]),
    .l1clk(l1clk_q3_out),
    .din(rd_data_w2_i7_or_i3[32:0]),
    .dout(data_bus_3_w2_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
//////////////////////////////////////////////////
// way 3 flops                                  //
//////////////////////////////////////////////////
   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w3_reg  (
     .scan_in(data_bus_0_w3_reg_scanin[32:0]),
     .scan_out(data_bus_0_w3_reg_scanout[32:0]),
    .l1clk(l1clk_q0_out),
    .din(rd_data_w3_i4_or_i0[32:0]),
    .dout(data_bus_0_w3_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w3_reg  (
     .scan_in(data_bus_1_w3_reg_scanin[32:0]),
     .scan_out(data_bus_1_w3_reg_scanout[32:0]),
   .l1clk(l1clk_q1_out),
    .din(rd_data_w3_i5_or_i1[32:0]),
    .dout(data_bus_1_w3_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w3_reg  (
     .scan_in(data_bus_2_w3_reg_scanin[32:0]),
     .scan_out(data_bus_2_w3_reg_scanout[32:0]),
    .l1clk(l1clk_q2_out),
    .din(rd_data_w3_i6_or_i2[32:0]),
    .dout(data_bus_2_w3_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w3_reg  (
     .scan_in(data_bus_3_w3_reg_scanin[32:0]),
     .scan_out(data_bus_3_w3_reg_scanout[32:0]),
    .l1clk(l1clk_q3_out),
    .din(rd_data_w3_i7_or_i3[32:0]),
    .dout(data_bus_3_w3_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
//////////////////////////////////////////////////
// way 4 flops                                  //
//////////////////////////////////////////////////
   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w4_reg  (
     .scan_in(data_bus_0_w4_reg_scanin[32:0]),
     .scan_out(data_bus_0_w4_reg_scanout[32:0]),
    .l1clk(l1clk_q0_out),
    .din(rd_data_w4_i4_or_i0[32:0]),
    .dout(data_bus_0_w4_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w4_reg  (
     .scan_in(data_bus_1_w4_reg_scanin[32:0]),
     .scan_out(data_bus_1_w4_reg_scanout[32:0]),
    .l1clk(l1clk_q1_out),
    .din(rd_data_w4_i5_or_i1[32:0]),
    .dout(data_bus_1_w4_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w4_reg  (
     .scan_in(data_bus_2_w4_reg_scanin[32:0]),
     .scan_out(data_bus_2_w4_reg_scanout[32:0]),
    .l1clk(l1clk_q2_out),
    .din(rd_data_w4_i6_or_i2[32:0]),
    .dout(data_bus_2_w4_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w4_reg  (
     .scan_in(data_bus_3_w4_reg_scanin[32:0]),
     .scan_out(data_bus_3_w4_reg_scanout[32:0]),
    .l1clk(l1clk_q3_out),
    .din(rd_data_w4_i7_or_i3[32:0]),
    .dout(data_bus_3_w4_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
//////////////////////////////////////////////////
// way 5 flops                                  //
//////////////////////////////////////////////////
   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w5_reg  (
     .scan_in(data_bus_0_w5_reg_scanin[32:0]),
     .scan_out(data_bus_0_w5_reg_scanout[32:0]),
    .l1clk(l1clk_q0_out),
    .din(rd_data_w5_i4_or_i0[32:0]),
    .dout(data_bus_0_w5_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w5_reg  (
     .scan_in(data_bus_1_w5_reg_scanin[32:0]),
     .scan_out(data_bus_1_w5_reg_scanout[32:0]),
    .l1clk(l1clk_q1_out),
    .din(rd_data_w5_i5_or_i1[32:0]),
    .dout(data_bus_1_w5_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w5_reg  (
     .scan_in(data_bus_2_w5_reg_scanin[32:0]),
     .scan_out(data_bus_2_w5_reg_scanout[32:0]),
    .l1clk(l1clk_q2_out),
    .din(rd_data_w5_i6_or_i2[32:0]),
    .dout(data_bus_2_w5_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w5_reg  (
     .scan_in(data_bus_3_w5_reg_scanin[32:0]),
     .scan_out(data_bus_3_w5_reg_scanout[32:0]),
    .l1clk(l1clk_q3_out),
    .din(rd_data_w5_i7_or_i3[32:0]),
    .dout(data_bus_3_w5_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
//////////////////////////////////////////////////
// way 6 flops                                  //
//////////////////////////////////////////////////
   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w6_reg  (
     .scan_in(data_bus_0_w6_reg_scanin[32:0]),
     .scan_out(data_bus_0_w6_reg_scanout[32:0]),
    .l1clk(l1clk_q0_out),
    .din(rd_data_w6_i4_or_i0[32:0]),
    .dout(data_bus_0_w6_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w6_reg  (
     .scan_in(data_bus_1_w6_reg_scanin[32:0]),
     .scan_out(data_bus_1_w6_reg_scanout[32:0]),
    .l1clk(l1clk_q1_out),
    .din(rd_data_w6_i5_or_i1[32:0]),
    .dout(data_bus_1_w6_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w6_reg  (
     .scan_in(data_bus_2_w6_reg_scanin[32:0]),
     .scan_out(data_bus_2_w6_reg_scanout[32:0]),
    .l1clk(l1clk_q2_out),
    .din(rd_data_w6_i6_or_i2[32:0]),
    .dout(data_bus_2_w6_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w6_reg  (
     .scan_in(data_bus_3_w6_reg_scanin[32:0]),
     .scan_out(data_bus_3_w6_reg_scanout[32:0]),
    .l1clk(l1clk_q3_out),
    .din(rd_data_w6_i7_or_i3[32:0]),
    .dout(data_bus_3_w6_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
//////////////////////////////////////////////////
// way 7 flops                                  //
//////////////////////////////////////////////////
   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_0_w7_reg  (
     .scan_in(data_bus_0_w7_reg_scanin[32:0]),
     .scan_out(data_bus_0_w7_reg_scanout[32:0]),
    .l1clk(l1clk_q0_out),
    .din(rd_data_w7_i4_or_i0[32:0]),
    .dout(data_bus_0_w7_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_1_w7_reg  (
     .scan_in(data_bus_1_w7_reg_scanin[32:0]),
     .scan_out(data_bus_1_w7_reg_scanout[32:0]),
    .l1clk(l1clk_q1_out),
    .din(rd_data_w7_i5_or_i1[32:0]),
    .dout(data_bus_1_w7_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_2_w7_reg  (
     .scan_in(data_bus_2_w7_reg_scanin[32:0]),
     .scan_out(data_bus_2_w7_reg_scanout[32:0]),
    .l1clk(l1clk_q2_out),
    .din(rd_data_w7_i6_or_i2[32:0]),
    .dout(data_bus_2_w7_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );

   n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 data_bus_3_w7_reg  (
     .scan_in(data_bus_3_w7_reg_scanin[32:0]),
     .scan_out(data_bus_3_w7_reg_scanout[32:0]),
    .l1clk(l1clk_q3_out),
    .din(rd_data_w7_i7_or_i3[32:0]),
    .dout(data_bus_3_w7_c[32:0]),
  .siclk(siclk),
  .soclk(soclk)
    );
//////////////////////////////////////////////////////////////////////////
// Muxing ALL ways to get instr 0,1,2,3  based on the way select from   //
// Icache tags and TLB.                                                 //
// NOTE: These instructions are unordered.                              //
//////////////////////////////////////////////////////////////////////////

 
n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 bus_0_mux  (
 .din0({data_bus_0_w0_c[32],data_bus_0_w0_c[31:0]}),
 .din1({data_bus_0_w1_c[32],data_bus_0_w1_c[31:0]}),
 .din2({data_bus_0_w2_c[32],data_bus_0_w2_c[31:0]}),
 .din3({data_bus_0_w3_c[32],data_bus_0_w3_c[31:0]}),
 .din4({data_bus_0_w4_c[32],data_bus_0_w4_c[31:0]}),
 .din5({data_bus_0_w5_c[32],data_bus_0_w5_c[31:0]}),
 .din6({data_bus_0_w6_c[32],data_bus_0_w6_c[31:0]}),
 .din7({data_bus_0_w7_c[32],data_bus_0_w7_c[31:0]} ),
 .sel0 ( muxed_way_sel_c[0]),
 .sel1 ( muxed_way_sel_c[1]),
 .sel2 ( muxed_way_sel_c[2]),
 .sel3 ( muxed_way_sel_c[3]),
 .sel4 ( muxed_way_sel_c[4]),
 .sel5 ( muxed_way_sel_c[5]),
 .sel6 ( muxed_way_sel_c[6]),
 .sel7 ( muxed_way_sel_c[7]),
 .dout( icd_bus_0_instr_c[32:0] ));

n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 bus_1_mux  (
 .din0({data_bus_1_w0_c[32],data_bus_1_w0_c[31:0]}),
 .din1({data_bus_1_w1_c[32],data_bus_1_w1_c[31:0]}),
 .din2({data_bus_1_w2_c[32],data_bus_1_w2_c[31:0]}),
 .din3({data_bus_1_w3_c[32],data_bus_1_w3_c[31:0]}),
 .din4({data_bus_1_w4_c[32],data_bus_1_w4_c[31:0]}),
 .din5({data_bus_1_w5_c[32],data_bus_1_w5_c[31:0]}),
 .din6({data_bus_1_w6_c[32],data_bus_1_w6_c[31:0]}),
 .din7({data_bus_1_w7_c[32],data_bus_1_w7_c[31:0]} ),
 .sel0 ( muxed_way_sel_c[0]),
 .sel1 ( muxed_way_sel_c[1]),
 .sel2 ( muxed_way_sel_c[2]),
 .sel3 ( muxed_way_sel_c[3]),
 .sel4 ( muxed_way_sel_c[4]),
 .sel5 ( muxed_way_sel_c[5]),
 .sel6 ( muxed_way_sel_c[6]),
 .sel7 ( muxed_way_sel_c[7]),
 .dout( icd_bus_1_instr_c[32:0] ));

n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 bus_2_mux  (
 .din0({data_bus_2_w0_c[32],data_bus_2_w0_c[31:0]}),
 .din1({data_bus_2_w1_c[32],data_bus_2_w1_c[31:0]}),
 .din2({data_bus_2_w2_c[32],data_bus_2_w2_c[31:0]}),
 .din3({data_bus_2_w3_c[32],data_bus_2_w3_c[31:0]}),
 .din4({data_bus_2_w4_c[32],data_bus_2_w4_c[31:0]}),
 .din5({data_bus_2_w5_c[32],data_bus_2_w5_c[31:0]}),
 .din6({data_bus_2_w6_c[32],data_bus_2_w6_c[31:0]}),
 .din7({data_bus_2_w7_c[32],data_bus_2_w7_c[31:0]} ),
 .sel0 ( muxed_way_sel_c[0]),
 .sel1 ( muxed_way_sel_c[1]),
 .sel2 ( muxed_way_sel_c[2]),
 .sel3 ( muxed_way_sel_c[3]),
 .sel4 ( muxed_way_sel_c[4]),
 .sel5 ( muxed_way_sel_c[5]),
 .sel6 ( muxed_way_sel_c[6]),
 .sel7 ( muxed_way_sel_c[7]),
 .dout( icd_bus_2_instr_c[32:0] ));

n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 bus_3_mux  (
 .din0({data_bus_3_w0_c[32],data_bus_3_w0_c[31:0]}),
 .din1({data_bus_3_w1_c[32],data_bus_3_w1_c[31:0]}),
 .din2({data_bus_3_w2_c[32],data_bus_3_w2_c[31:0]}),
 .din3({data_bus_3_w3_c[32],data_bus_3_w3_c[31:0]}),
 .din4({data_bus_3_w4_c[32],data_bus_3_w4_c[31:0]}),
 .din5({data_bus_3_w5_c[32],data_bus_3_w5_c[31:0]}),
 .din6({data_bus_3_w6_c[32],data_bus_3_w6_c[31:0]}),
 .din7({data_bus_3_w7_c[32],data_bus_3_w7_c[31:0]} ),
 .sel0 ( muxed_way_sel_c[0]),
 .sel1 ( muxed_way_sel_c[1]),
 .sel2 ( muxed_way_sel_c[2]),
 .sel3 ( muxed_way_sel_c[3]),
 .sel4 ( muxed_way_sel_c[4]),
 .sel5 ( muxed_way_sel_c[5]),
 .sel6 ( muxed_way_sel_c[6]),
 .sel7 ( muxed_way_sel_c[7]),
 .dout( icd_bus_3_instr_c[32:0] ));
////////////////////////////////////////////////////////////
// Redunduncy Data out muxing                             //
////////////////////////////////////////////////////////////

n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_7 red_data_out_mux0    (
        .din0   ({reg_d_q0_w7_w4_lft_d[4:0],reg_d_q0_w7_w4_lft_en[1:0]}),
        .din1   ({reg_d_q0_w7_w4_rgt_d[4:0],reg_d_q0_w7_w4_rgt_en[1:0]}),
        .din2   ({reg_d_q0_w3_w0_lft_d[4:0],reg_d_q0_w3_w0_lft_en[1:0]}),
        .din3   ({reg_d_q0_w3_w0_rgt_d[4:0],reg_d_q0_w3_w0_rgt_en[1:0]}),
        .din4   ({reg_d_q1_w7_w4_lft_d[4:0],reg_d_q1_w7_w4_lft_en[1:0]}),
        .din5   ({reg_d_q1_w7_w4_rgt_d[4:0],reg_d_q1_w7_w4_rgt_en[1:0]}),
        .din6   ({reg_d_q1_w3_w0_lft_d[4:0],reg_d_q1_w3_w0_lft_en[1:0]}),
        .din7   ({reg_d_q1_w3_w0_rgt_d[4:0],reg_d_q1_w3_w0_rgt_en[1:0]}),
        .sel    (rid_ff[2:0]),
        .dout   ({reg_d_out_mux_0[4:0],reg_en_out_mux_0[1:0]})
);

n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_7 red_data_out_mux1    (
        .din0   ({reg_d_q2_w7_w4_lft_d[4:0],reg_d_q2_w7_w4_lft_en[1:0]}),
        .din1   ({reg_d_q2_w7_w4_rgt_d[4:0],reg_d_q2_w7_w4_rgt_en[1:0]}),
        .din2   ({reg_d_q2_w3_w0_lft_d[4:0],reg_d_q2_w3_w0_lft_en[1:0]}),
        .din3   ({reg_d_q2_w3_w0_rgt_d[4:0],reg_d_q2_w3_w0_rgt_en[1:0]}),
        .din4   ({reg_d_q3_w7_w4_lft_d[4:0],reg_d_q3_w7_w4_lft_en[1:0]}),
        .din5   ({reg_d_q3_w7_w4_rgt_d[4:0],reg_d_q3_w7_w4_rgt_en[1:0]}),
        .din6   ({reg_d_q3_w3_w0_lft_d[4:0],reg_d_q3_w3_w0_lft_en[1:0]}),
        .din7   ({reg_d_q3_w3_w0_rgt_d[4:0],reg_d_q3_w3_w0_rgt_en[1:0]}),
        .sel    (rid_ff[2:0]),
        .dout   ({reg_d_out_mux_1[4:0],reg_en_out_mux_1[1:0]})
);

n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__width_7 red_data_out_mux2    (
        .din0   ({reg_d_out_mux_1[4:0],reg_en_out_mux_1[1:0]}),
        .din1   ({reg_d_out_mux_0[4:0],reg_en_out_mux_0[1:0]}),
        .sel0    (rid_ff[3]),
        .dout   ({red_mux_d_out[4:0],red_mux_en_out[1:0]})
);

n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_5 red_d_out_reg  (
     .scan_in(red_d_out_reg_scanin[4:0]),
     .scan_out(red_d_out_reg_scanout[4:0]),
    .l1clk(l1clk_red_out),
    .din(red_mux_d_out[4:0]),
    .dout(red_d_out[4:0]),
  .siclk(siclk),
  .soclk(soclk)
);


n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_2 red_en_out_reg   (
     .scan_in(red_en_out_reg_scanin[1:0]),
     .scan_out(red_en_out_reg_scanout[1:0]),
    .l1clk(l1clk_red_out),
    .din(red_mux_en_out[1:0]),
    .dout(red_en_out[1:0]),
  .siclk(siclk),
  .soclk(soclk)
);


supply0 vss;
supply1 vdd;

assign ftp_access_f_reg_scanin[0]=scan_in;
assign ftp_access_c_reg_scanin[0]=ftp_access_f_reg_scanout;
assign ftp_access_c_dum_scanin=ftp_access_c_reg_scanout[0];
assign wrdata_q1_5_scanin[32]=ftp_access_c_dum_scanout;
assign wrdata_q1_1_scanin[32]=wrdata_q1_5_scanout[32];
assign wrdata_q1_5_scanin[31]=wrdata_q1_1_scanout[32];
assign wrdata_q1_1_scanin[31]=wrdata_q1_5_scanout[31];
assign wrdata_q1_5_scanin[30]=wrdata_q1_1_scanout[31];
assign wrdata_q1_1_scanin[30]=wrdata_q1_5_scanout[30];
assign wrdata_q1_5_scanin[29]=wrdata_q1_1_scanout[30];
assign wrdata_q1_1_scanin[29]=wrdata_q1_5_scanout[29];
assign wrdata_q1_5_scanin[28]=wrdata_q1_1_scanout[29];
assign wrdata_q1_1_scanin[28]=wrdata_q1_5_scanout[28];
assign wrdata_q1_5_scanin[27]=wrdata_q1_1_scanout[28];
assign wrdata_q1_1_scanin[27]=wrdata_q1_5_scanout[27];
assign wrdata_q1_5_scanin[26]=wrdata_q1_1_scanout[27];
assign wrdata_q1_1_scanin[26]=wrdata_q1_5_scanout[26];
assign wrdata_q1_5_scanin[25]=wrdata_q1_1_scanout[26];
assign wrdata_q1_1_scanin[25]=wrdata_q1_5_scanout[25];
assign wrdata_q1_5_scanin[24]=wrdata_q1_1_scanout[25];
assign wrdata_q1_1_scanin[24]=wrdata_q1_5_scanout[24];
assign wrdata_q1_5_scanin[23]=wrdata_q1_1_scanout[24];
assign wrdata_q1_1_scanin[23]=wrdata_q1_5_scanout[23];
assign wrdata_q1_5_scanin[22]=wrdata_q1_1_scanout[23];
assign wrdata_q1_1_scanin[22]=wrdata_q1_5_scanout[22];
assign wrdata_q1_5_scanin[21]=wrdata_q1_1_scanout[22];
assign wrdata_q1_1_scanin[21]=wrdata_q1_5_scanout[21];
assign wrdata_q1_5_scanin[20]=wrdata_q1_1_scanout[21];
assign wrdata_q1_1_scanin[20]=wrdata_q1_5_scanout[20];
assign wrdata_q1_5_scanin[19]=wrdata_q1_1_scanout[20];
assign wrdata_q1_1_scanin[19]=wrdata_q1_5_scanout[19];
assign wrdata_q1_5_scanin[18]=wrdata_q1_1_scanout[19];
assign wrdata_q1_1_scanin[18]=wrdata_q1_5_scanout[18];
assign wrdata_q1_5_scanin[17]=wrdata_q1_1_scanout[18];
assign wrdata_q1_1_scanin[17]=wrdata_q1_5_scanout[17];
assign wrdata_q1_5_scanin[16]=wrdata_q1_1_scanout[17];
assign wrdata_q1_1_scanin[16]=wrdata_q1_5_scanout[16];
assign wrdata_q1_5_scanin[15]=wrdata_q1_1_scanout[16];
assign wrdata_q1_1_scanin[15]=wrdata_q1_5_scanout[15];
assign wrdata_q1_5_scanin[14]=wrdata_q1_1_scanout[15];
assign wrdata_q1_1_scanin[14]=wrdata_q1_5_scanout[14];
assign wrdata_q1_5_scanin[13]=wrdata_q1_1_scanout[14];
assign wrdata_q1_1_scanin[13]=wrdata_q1_5_scanout[13];
assign wrdata_q1_5_scanin[12]=wrdata_q1_1_scanout[13];
assign wrdata_q1_1_scanin[12]=wrdata_q1_5_scanout[12];
assign wrdata_q1_5_scanin[11]=wrdata_q1_1_scanout[12];
assign wrdata_q1_1_scanin[11]=wrdata_q1_5_scanout[11];
assign wrdata_q1_5_scanin[10]=wrdata_q1_1_scanout[11];
assign wrdata_q1_1_scanin[10]=wrdata_q1_5_scanout[10];
assign wrdata_q1_5_scanin[9]=wrdata_q1_1_scanout[10];
assign wrdata_q1_1_scanin[9]=wrdata_q1_5_scanout[9];
assign wrdata_q1_5_scanin[8]=wrdata_q1_1_scanout[9];
assign wrdata_q1_1_scanin[8]=wrdata_q1_5_scanout[8];
assign wrdata_q1_5_scanin[7]=wrdata_q1_1_scanout[8];
assign wrdata_q1_1_scanin[7]=wrdata_q1_5_scanout[7];
assign wrdata_q1_5_scanin[6]=wrdata_q1_1_scanout[7];
assign wrdata_q1_1_scanin[6]=wrdata_q1_5_scanout[6];
assign wrdata_q1_5_scanin[5]=wrdata_q1_1_scanout[6];
assign wrdata_q1_1_scanin[5]=wrdata_q1_5_scanout[5];
assign wrdata_q1_5_scanin[4]=wrdata_q1_1_scanout[5];
assign wrdata_q1_1_scanin[4]=wrdata_q1_5_scanout[4];
assign wrdata_q1_5_scanin[3]=wrdata_q1_1_scanout[4];
assign wrdata_q1_1_scanin[3]=wrdata_q1_5_scanout[3];
assign wrdata_q1_5_scanin[2]=wrdata_q1_1_scanout[3];
assign wrdata_q1_1_scanin[2]=wrdata_q1_5_scanout[2];
assign wrdata_q1_5_scanin[1]=wrdata_q1_1_scanout[2];
assign wrdata_q1_1_scanin[1]=wrdata_q1_5_scanout[1];
assign wrdata_q1_5_scanin[0]=wrdata_q1_1_scanout[1];
assign wrdata_q1_1_scanin[0]=wrdata_q1_5_scanout[0];


// ***************************BEGIN SECTION*************************

assign data_bus_1_w2_reg_scanin[32]=wrdata_q1_1_scanout[0];
assign data_bus_1_w3_reg_scanin[32]=data_bus_1_w2_reg_scanout[32];
assign data_bus_1_w6_reg_scanin[32]=data_bus_1_w3_reg_scanout[32];
assign data_bus_1_w7_reg_scanin[32]=data_bus_1_w6_reg_scanout[32];
assign data_bus_1_w0_reg_scanin[32]=data_bus_1_w7_reg_scanout[32];
assign data_bus_1_w1_reg_scanin[32]=data_bus_1_w0_reg_scanout[32];
assign data_bus_1_w4_reg_scanin[32]=data_bus_1_w1_reg_scanout[32];
assign data_bus_1_w5_reg_scanin[32]=data_bus_1_w4_reg_scanout[32];

assign data_bus_1_w2_reg_scanin[31]=data_bus_1_w5_reg_scanout[32];
assign data_bus_1_w3_reg_scanin[31]=data_bus_1_w2_reg_scanout[31];
assign data_bus_1_w6_reg_scanin[31]=data_bus_1_w3_reg_scanout[31];
assign data_bus_1_w7_reg_scanin[31]=data_bus_1_w6_reg_scanout[31];
assign data_bus_1_w0_reg_scanin[31]=data_bus_1_w7_reg_scanout[31];
assign data_bus_1_w1_reg_scanin[31]=data_bus_1_w0_reg_scanout[31];
assign data_bus_1_w4_reg_scanin[31]=data_bus_1_w1_reg_scanout[31];
assign data_bus_1_w5_reg_scanin[31]=data_bus_1_w4_reg_scanout[31];

assign data_bus_1_w2_reg_scanin[30]=data_bus_1_w5_reg_scanout[31];
assign data_bus_1_w3_reg_scanin[30]=data_bus_1_w2_reg_scanout[30];
assign data_bus_1_w6_reg_scanin[30]=data_bus_1_w3_reg_scanout[30];
assign data_bus_1_w7_reg_scanin[30]=data_bus_1_w6_reg_scanout[30];
assign data_bus_1_w0_reg_scanin[30]=data_bus_1_w7_reg_scanout[30];
assign data_bus_1_w1_reg_scanin[30]=data_bus_1_w0_reg_scanout[30];
assign data_bus_1_w4_reg_scanin[30]=data_bus_1_w1_reg_scanout[30];
assign data_bus_1_w5_reg_scanin[30]=data_bus_1_w4_reg_scanout[30];

assign data_bus_1_w2_reg_scanin[29]=data_bus_1_w5_reg_scanout[30];
assign data_bus_1_w3_reg_scanin[29]=data_bus_1_w2_reg_scanout[29];
assign data_bus_1_w6_reg_scanin[29]=data_bus_1_w3_reg_scanout[29];
assign data_bus_1_w7_reg_scanin[29]=data_bus_1_w6_reg_scanout[29];
assign data_bus_1_w0_reg_scanin[29]=data_bus_1_w7_reg_scanout[29];
assign data_bus_1_w1_reg_scanin[29]=data_bus_1_w0_reg_scanout[29];
assign data_bus_1_w4_reg_scanin[29]=data_bus_1_w1_reg_scanout[29];
assign data_bus_1_w5_reg_scanin[29]=data_bus_1_w4_reg_scanout[29];

assign data_bus_1_w2_reg_scanin[28]=data_bus_1_w5_reg_scanout[29];
assign data_bus_1_w3_reg_scanin[28]=data_bus_1_w2_reg_scanout[28];
assign data_bus_1_w6_reg_scanin[28]=data_bus_1_w3_reg_scanout[28];
assign data_bus_1_w7_reg_scanin[28]=data_bus_1_w6_reg_scanout[28];
assign data_bus_1_w0_reg_scanin[28]=data_bus_1_w7_reg_scanout[28];
assign data_bus_1_w1_reg_scanin[28]=data_bus_1_w0_reg_scanout[28];
assign data_bus_1_w4_reg_scanin[28]=data_bus_1_w1_reg_scanout[28];
assign data_bus_1_w5_reg_scanin[28]=data_bus_1_w4_reg_scanout[28];

assign data_bus_1_w2_reg_scanin[27]=data_bus_1_w5_reg_scanout[28];
assign data_bus_1_w3_reg_scanin[27]=data_bus_1_w2_reg_scanout[27];
assign data_bus_1_w6_reg_scanin[27]=data_bus_1_w3_reg_scanout[27];
assign data_bus_1_w7_reg_scanin[27]=data_bus_1_w6_reg_scanout[27];
assign data_bus_1_w0_reg_scanin[27]=data_bus_1_w7_reg_scanout[27];
assign data_bus_1_w1_reg_scanin[27]=data_bus_1_w0_reg_scanout[27];
assign data_bus_1_w4_reg_scanin[27]=data_bus_1_w1_reg_scanout[27];
assign data_bus_1_w5_reg_scanin[27]=data_bus_1_w4_reg_scanout[27];

assign data_bus_1_w2_reg_scanin[26]=data_bus_1_w5_reg_scanout[27];
assign data_bus_1_w3_reg_scanin[26]=data_bus_1_w2_reg_scanout[26];
assign data_bus_1_w6_reg_scanin[26]=data_bus_1_w3_reg_scanout[26];
assign data_bus_1_w7_reg_scanin[26]=data_bus_1_w6_reg_scanout[26];
assign data_bus_1_w0_reg_scanin[26]=data_bus_1_w7_reg_scanout[26];
assign data_bus_1_w1_reg_scanin[26]=data_bus_1_w0_reg_scanout[26];
assign data_bus_1_w4_reg_scanin[26]=data_bus_1_w1_reg_scanout[26];
assign data_bus_1_w5_reg_scanin[26]=data_bus_1_w4_reg_scanout[26];

assign data_bus_1_w2_reg_scanin[25]=data_bus_1_w5_reg_scanout[26];
assign data_bus_1_w3_reg_scanin[25]=data_bus_1_w2_reg_scanout[25];
assign data_bus_1_w6_reg_scanin[25]=data_bus_1_w3_reg_scanout[25];
assign data_bus_1_w7_reg_scanin[25]=data_bus_1_w6_reg_scanout[25];
assign data_bus_1_w0_reg_scanin[25]=data_bus_1_w7_reg_scanout[25];
assign data_bus_1_w1_reg_scanin[25]=data_bus_1_w0_reg_scanout[25];
assign data_bus_1_w4_reg_scanin[25]=data_bus_1_w1_reg_scanout[25];
assign data_bus_1_w5_reg_scanin[25]=data_bus_1_w4_reg_scanout[25];

assign data_bus_1_w2_reg_scanin[24]=data_bus_1_w5_reg_scanout[25];
assign data_bus_1_w3_reg_scanin[24]=data_bus_1_w2_reg_scanout[24];
assign data_bus_1_w6_reg_scanin[24]=data_bus_1_w3_reg_scanout[24];
assign data_bus_1_w7_reg_scanin[24]=data_bus_1_w6_reg_scanout[24];
assign data_bus_1_w0_reg_scanin[24]=data_bus_1_w7_reg_scanout[24];
assign data_bus_1_w1_reg_scanin[24]=data_bus_1_w0_reg_scanout[24];
assign data_bus_1_w4_reg_scanin[24]=data_bus_1_w1_reg_scanout[24];
assign data_bus_1_w5_reg_scanin[24]=data_bus_1_w4_reg_scanout[24];

assign data_bus_1_w2_reg_scanin[23]=data_bus_1_w5_reg_scanout[24];
assign data_bus_1_w3_reg_scanin[23]=data_bus_1_w2_reg_scanout[23];
assign data_bus_1_w6_reg_scanin[23]=data_bus_1_w3_reg_scanout[23];
assign data_bus_1_w7_reg_scanin[23]=data_bus_1_w6_reg_scanout[23];
assign data_bus_1_w0_reg_scanin[23]=data_bus_1_w7_reg_scanout[23];
assign data_bus_1_w1_reg_scanin[23]=data_bus_1_w0_reg_scanout[23];
assign data_bus_1_w4_reg_scanin[23]=data_bus_1_w1_reg_scanout[23];
assign data_bus_1_w5_reg_scanin[23]=data_bus_1_w4_reg_scanout[23];

assign data_bus_1_w2_reg_scanin[22]=data_bus_1_w5_reg_scanout[23];
assign data_bus_1_w3_reg_scanin[22]=data_bus_1_w2_reg_scanout[22];
assign data_bus_1_w6_reg_scanin[22]=data_bus_1_w3_reg_scanout[22];
assign data_bus_1_w7_reg_scanin[22]=data_bus_1_w6_reg_scanout[22];
assign data_bus_1_w0_reg_scanin[22]=data_bus_1_w7_reg_scanout[22];
assign data_bus_1_w1_reg_scanin[22]=data_bus_1_w0_reg_scanout[22];
assign data_bus_1_w4_reg_scanin[22]=data_bus_1_w1_reg_scanout[22];
assign data_bus_1_w5_reg_scanin[22]=data_bus_1_w4_reg_scanout[22];

assign data_bus_1_w2_reg_scanin[21]=data_bus_1_w5_reg_scanout[22];
assign data_bus_1_w3_reg_scanin[21]=data_bus_1_w2_reg_scanout[21];
assign data_bus_1_w6_reg_scanin[21]=data_bus_1_w3_reg_scanout[21];
assign data_bus_1_w7_reg_scanin[21]=data_bus_1_w6_reg_scanout[21];
assign data_bus_1_w0_reg_scanin[21]=data_bus_1_w7_reg_scanout[21];
assign data_bus_1_w1_reg_scanin[21]=data_bus_1_w0_reg_scanout[21];
assign data_bus_1_w4_reg_scanin[21]=data_bus_1_w1_reg_scanout[21];
assign data_bus_1_w5_reg_scanin[21]=data_bus_1_w4_reg_scanout[21];

assign data_bus_1_w2_reg_scanin[20]=data_bus_1_w5_reg_scanout[21];
assign data_bus_1_w3_reg_scanin[20]=data_bus_1_w2_reg_scanout[20];
assign data_bus_1_w6_reg_scanin[20]=data_bus_1_w3_reg_scanout[20];
assign data_bus_1_w7_reg_scanin[20]=data_bus_1_w6_reg_scanout[20];
assign data_bus_1_w0_reg_scanin[20]=data_bus_1_w7_reg_scanout[20];
assign data_bus_1_w1_reg_scanin[20]=data_bus_1_w0_reg_scanout[20];
assign data_bus_1_w4_reg_scanin[20]=data_bus_1_w1_reg_scanout[20];
assign data_bus_1_w5_reg_scanin[20]=data_bus_1_w4_reg_scanout[20];

assign data_bus_1_w2_reg_scanin[19]=data_bus_1_w5_reg_scanout[20];
assign data_bus_1_w3_reg_scanin[19]=data_bus_1_w2_reg_scanout[19];
assign data_bus_1_w6_reg_scanin[19]=data_bus_1_w3_reg_scanout[19];
assign data_bus_1_w7_reg_scanin[19]=data_bus_1_w6_reg_scanout[19];
assign data_bus_1_w0_reg_scanin[19]=data_bus_1_w7_reg_scanout[19];
assign data_bus_1_w1_reg_scanin[19]=data_bus_1_w0_reg_scanout[19];
assign data_bus_1_w4_reg_scanin[19]=data_bus_1_w1_reg_scanout[19];
assign data_bus_1_w5_reg_scanin[19]=data_bus_1_w4_reg_scanout[19];

assign data_bus_1_w2_reg_scanin[18]=data_bus_1_w5_reg_scanout[19];
assign data_bus_1_w3_reg_scanin[18]=data_bus_1_w2_reg_scanout[18];
assign data_bus_1_w6_reg_scanin[18]=data_bus_1_w3_reg_scanout[18];
assign data_bus_1_w7_reg_scanin[18]=data_bus_1_w6_reg_scanout[18];
assign data_bus_1_w0_reg_scanin[18]=data_bus_1_w7_reg_scanout[18];
assign data_bus_1_w1_reg_scanin[18]=data_bus_1_w0_reg_scanout[18];
assign data_bus_1_w4_reg_scanin[18]=data_bus_1_w1_reg_scanout[18];
assign data_bus_1_w5_reg_scanin[18]=data_bus_1_w4_reg_scanout[18];

assign data_bus_1_w2_reg_scanin[17]=data_bus_1_w5_reg_scanout[18];
assign data_bus_1_w3_reg_scanin[17]=data_bus_1_w2_reg_scanout[17];
assign data_bus_1_w6_reg_scanin[17]=data_bus_1_w3_reg_scanout[17];
assign data_bus_1_w7_reg_scanin[17]=data_bus_1_w6_reg_scanout[17];
assign data_bus_1_w0_reg_scanin[17]=data_bus_1_w7_reg_scanout[17];
assign data_bus_1_w1_reg_scanin[17]=data_bus_1_w0_reg_scanout[17];
assign data_bus_1_w4_reg_scanin[17]=data_bus_1_w1_reg_scanout[17];
assign data_bus_1_w5_reg_scanin[17]=data_bus_1_w4_reg_scanout[17];

assign data_bus_1_w0_reg_scanin[16]=data_bus_1_w5_reg_scanout[17];
assign data_bus_1_w1_reg_scanin[16]=data_bus_1_w0_reg_scanout[16];
assign data_bus_1_w4_reg_scanin[16]=data_bus_1_w1_reg_scanout[16];
assign data_bus_1_w5_reg_scanin[16]=data_bus_1_w4_reg_scanout[16];
assign data_bus_1_w2_reg_scanin[16]=data_bus_1_w5_reg_scanout[16];
assign data_bus_1_w3_reg_scanin[16]=data_bus_1_w2_reg_scanout[16];
assign data_bus_1_w6_reg_scanin[16]=data_bus_1_w3_reg_scanout[16];
assign data_bus_1_w7_reg_scanin[16]=data_bus_1_w6_reg_scanout[16];

assign data_bus_1_w0_reg_scanin[15]=data_bus_1_w7_reg_scanout[16];
assign data_bus_1_w1_reg_scanin[15]=data_bus_1_w0_reg_scanout[15];
assign data_bus_1_w4_reg_scanin[15]=data_bus_1_w1_reg_scanout[15];
assign data_bus_1_w5_reg_scanin[15]=data_bus_1_w4_reg_scanout[15];
assign data_bus_1_w2_reg_scanin[15]=data_bus_1_w5_reg_scanout[15];
assign data_bus_1_w3_reg_scanin[15]=data_bus_1_w2_reg_scanout[15];
assign data_bus_1_w6_reg_scanin[15]=data_bus_1_w3_reg_scanout[15];
assign data_bus_1_w7_reg_scanin[15]=data_bus_1_w6_reg_scanout[15];

assign data_bus_1_w0_reg_scanin[14]=data_bus_1_w7_reg_scanout[15];
assign data_bus_1_w1_reg_scanin[14]=data_bus_1_w0_reg_scanout[14];
assign data_bus_1_w4_reg_scanin[14]=data_bus_1_w1_reg_scanout[14];
assign data_bus_1_w5_reg_scanin[14]=data_bus_1_w4_reg_scanout[14];
assign data_bus_1_w2_reg_scanin[14]=data_bus_1_w5_reg_scanout[14];
assign data_bus_1_w3_reg_scanin[14]=data_bus_1_w2_reg_scanout[14];
assign data_bus_1_w6_reg_scanin[14]=data_bus_1_w3_reg_scanout[14];
assign data_bus_1_w7_reg_scanin[14]=data_bus_1_w6_reg_scanout[14];

assign data_bus_1_w0_reg_scanin[13]=data_bus_1_w7_reg_scanout[14];
assign data_bus_1_w1_reg_scanin[13]=data_bus_1_w0_reg_scanout[13];
assign data_bus_1_w4_reg_scanin[13]=data_bus_1_w1_reg_scanout[13];
assign data_bus_1_w5_reg_scanin[13]=data_bus_1_w4_reg_scanout[13];
assign data_bus_1_w2_reg_scanin[13]=data_bus_1_w5_reg_scanout[13];
assign data_bus_1_w3_reg_scanin[13]=data_bus_1_w2_reg_scanout[13];
assign data_bus_1_w6_reg_scanin[13]=data_bus_1_w3_reg_scanout[13];
assign data_bus_1_w7_reg_scanin[13]=data_bus_1_w6_reg_scanout[13];

assign data_bus_1_w0_reg_scanin[12]=data_bus_1_w7_reg_scanout[13];
assign data_bus_1_w1_reg_scanin[12]=data_bus_1_w0_reg_scanout[12];
assign data_bus_1_w4_reg_scanin[12]=data_bus_1_w1_reg_scanout[12];
assign data_bus_1_w5_reg_scanin[12]=data_bus_1_w4_reg_scanout[12];
assign data_bus_1_w2_reg_scanin[12]=data_bus_1_w5_reg_scanout[12];
assign data_bus_1_w3_reg_scanin[12]=data_bus_1_w2_reg_scanout[12];
assign data_bus_1_w6_reg_scanin[12]=data_bus_1_w3_reg_scanout[12];
assign data_bus_1_w7_reg_scanin[12]=data_bus_1_w6_reg_scanout[12];

assign data_bus_1_w0_reg_scanin[11]=data_bus_1_w7_reg_scanout[12];
assign data_bus_1_w1_reg_scanin[11]=data_bus_1_w0_reg_scanout[11];
assign data_bus_1_w4_reg_scanin[11]=data_bus_1_w1_reg_scanout[11];
assign data_bus_1_w5_reg_scanin[11]=data_bus_1_w4_reg_scanout[11];
assign data_bus_1_w2_reg_scanin[11]=data_bus_1_w5_reg_scanout[11];
assign data_bus_1_w3_reg_scanin[11]=data_bus_1_w2_reg_scanout[11];
assign data_bus_1_w6_reg_scanin[11]=data_bus_1_w3_reg_scanout[11];
assign data_bus_1_w7_reg_scanin[11]=data_bus_1_w6_reg_scanout[11];

assign data_bus_1_w0_reg_scanin[10]=data_bus_1_w7_reg_scanout[11];
assign data_bus_1_w1_reg_scanin[10]=data_bus_1_w0_reg_scanout[10];
assign data_bus_1_w4_reg_scanin[10]=data_bus_1_w1_reg_scanout[10];
assign data_bus_1_w5_reg_scanin[10]=data_bus_1_w4_reg_scanout[10];
assign data_bus_1_w2_reg_scanin[10]=data_bus_1_w5_reg_scanout[10];
assign data_bus_1_w3_reg_scanin[10]=data_bus_1_w2_reg_scanout[10];
assign data_bus_1_w6_reg_scanin[10]=data_bus_1_w3_reg_scanout[10];
assign data_bus_1_w7_reg_scanin[10]=data_bus_1_w6_reg_scanout[10];

assign data_bus_1_w0_reg_scanin[9]=data_bus_1_w7_reg_scanout[10];
assign data_bus_1_w1_reg_scanin[9]=data_bus_1_w0_reg_scanout[9];
assign data_bus_1_w4_reg_scanin[9]=data_bus_1_w1_reg_scanout[9];
assign data_bus_1_w5_reg_scanin[9]=data_bus_1_w4_reg_scanout[9];
assign data_bus_1_w2_reg_scanin[9]=data_bus_1_w5_reg_scanout[9];
assign data_bus_1_w3_reg_scanin[9]=data_bus_1_w2_reg_scanout[9];
assign data_bus_1_w6_reg_scanin[9]=data_bus_1_w3_reg_scanout[9];
assign data_bus_1_w7_reg_scanin[9]=data_bus_1_w6_reg_scanout[9];

assign data_bus_1_w0_reg_scanin[8]=data_bus_1_w7_reg_scanout[9];
assign data_bus_1_w1_reg_scanin[8]=data_bus_1_w0_reg_scanout[8];
assign data_bus_1_w4_reg_scanin[8]=data_bus_1_w1_reg_scanout[8];
assign data_bus_1_w5_reg_scanin[8]=data_bus_1_w4_reg_scanout[8];
assign data_bus_1_w2_reg_scanin[8]=data_bus_1_w5_reg_scanout[8];
assign data_bus_1_w3_reg_scanin[8]=data_bus_1_w2_reg_scanout[8];
assign data_bus_1_w6_reg_scanin[8]=data_bus_1_w3_reg_scanout[8];
assign data_bus_1_w7_reg_scanin[8]=data_bus_1_w6_reg_scanout[8];

assign data_bus_1_w0_reg_scanin[7]=data_bus_1_w7_reg_scanout[8];
assign data_bus_1_w1_reg_scanin[7]=data_bus_1_w0_reg_scanout[7];
assign data_bus_1_w4_reg_scanin[7]=data_bus_1_w1_reg_scanout[7];
assign data_bus_1_w5_reg_scanin[7]=data_bus_1_w4_reg_scanout[7];
assign data_bus_1_w2_reg_scanin[7]=data_bus_1_w5_reg_scanout[7];
assign data_bus_1_w3_reg_scanin[7]=data_bus_1_w2_reg_scanout[7];
assign data_bus_1_w6_reg_scanin[7]=data_bus_1_w3_reg_scanout[7];
assign data_bus_1_w7_reg_scanin[7]=data_bus_1_w6_reg_scanout[7];

assign data_bus_1_w0_reg_scanin[6]=data_bus_1_w7_reg_scanout[7];
assign data_bus_1_w1_reg_scanin[6]=data_bus_1_w0_reg_scanout[6];
assign data_bus_1_w4_reg_scanin[6]=data_bus_1_w1_reg_scanout[6];
assign data_bus_1_w5_reg_scanin[6]=data_bus_1_w4_reg_scanout[6];
assign data_bus_1_w2_reg_scanin[6]=data_bus_1_w5_reg_scanout[6];
assign data_bus_1_w3_reg_scanin[6]=data_bus_1_w2_reg_scanout[6];
assign data_bus_1_w6_reg_scanin[6]=data_bus_1_w3_reg_scanout[6];
assign data_bus_1_w7_reg_scanin[6]=data_bus_1_w6_reg_scanout[6];

assign data_bus_1_w0_reg_scanin[5]=data_bus_1_w7_reg_scanout[6];
assign data_bus_1_w1_reg_scanin[5]=data_bus_1_w0_reg_scanout[5];
assign data_bus_1_w4_reg_scanin[5]=data_bus_1_w1_reg_scanout[5];
assign data_bus_1_w5_reg_scanin[5]=data_bus_1_w4_reg_scanout[5];
assign data_bus_1_w2_reg_scanin[5]=data_bus_1_w5_reg_scanout[5];
assign data_bus_1_w3_reg_scanin[5]=data_bus_1_w2_reg_scanout[5];
assign data_bus_1_w6_reg_scanin[5]=data_bus_1_w3_reg_scanout[5];
assign data_bus_1_w7_reg_scanin[5]=data_bus_1_w6_reg_scanout[5];

assign data_bus_1_w0_reg_scanin[4]=data_bus_1_w7_reg_scanout[5];
assign data_bus_1_w1_reg_scanin[4]=data_bus_1_w0_reg_scanout[4];
assign data_bus_1_w4_reg_scanin[4]=data_bus_1_w1_reg_scanout[4];
assign data_bus_1_w5_reg_scanin[4]=data_bus_1_w4_reg_scanout[4];
assign data_bus_1_w2_reg_scanin[4]=data_bus_1_w5_reg_scanout[4];
assign data_bus_1_w3_reg_scanin[4]=data_bus_1_w2_reg_scanout[4];
assign data_bus_1_w6_reg_scanin[4]=data_bus_1_w3_reg_scanout[4];
assign data_bus_1_w7_reg_scanin[4]=data_bus_1_w6_reg_scanout[4];

assign data_bus_1_w0_reg_scanin[3]=data_bus_1_w7_reg_scanout[4];
assign data_bus_1_w1_reg_scanin[3]=data_bus_1_w0_reg_scanout[3];
assign data_bus_1_w4_reg_scanin[3]=data_bus_1_w1_reg_scanout[3];
assign data_bus_1_w5_reg_scanin[3]=data_bus_1_w4_reg_scanout[3];
assign data_bus_1_w2_reg_scanin[3]=data_bus_1_w5_reg_scanout[3];
assign data_bus_1_w3_reg_scanin[3]=data_bus_1_w2_reg_scanout[3];
assign data_bus_1_w6_reg_scanin[3]=data_bus_1_w3_reg_scanout[3];
assign data_bus_1_w7_reg_scanin[3]=data_bus_1_w6_reg_scanout[3];

assign data_bus_1_w0_reg_scanin[2]=data_bus_1_w7_reg_scanout[3];
assign data_bus_1_w1_reg_scanin[2]=data_bus_1_w0_reg_scanout[2];
assign data_bus_1_w4_reg_scanin[2]=data_bus_1_w1_reg_scanout[2];
assign data_bus_1_w5_reg_scanin[2]=data_bus_1_w4_reg_scanout[2];
assign data_bus_1_w2_reg_scanin[2]=data_bus_1_w5_reg_scanout[2];
assign data_bus_1_w3_reg_scanin[2]=data_bus_1_w2_reg_scanout[2];
assign data_bus_1_w6_reg_scanin[2]=data_bus_1_w3_reg_scanout[2];
assign data_bus_1_w7_reg_scanin[2]=data_bus_1_w6_reg_scanout[2];

assign data_bus_1_w0_reg_scanin[1]=data_bus_1_w7_reg_scanout[2];
assign data_bus_1_w1_reg_scanin[1]=data_bus_1_w0_reg_scanout[1];
assign data_bus_1_w4_reg_scanin[1]=data_bus_1_w1_reg_scanout[1];
assign data_bus_1_w5_reg_scanin[1]=data_bus_1_w4_reg_scanout[1];
assign data_bus_1_w2_reg_scanin[1]=data_bus_1_w5_reg_scanout[1];
assign data_bus_1_w3_reg_scanin[1]=data_bus_1_w2_reg_scanout[1];
assign data_bus_1_w6_reg_scanin[1]=data_bus_1_w3_reg_scanout[1];
assign data_bus_1_w7_reg_scanin[1]=data_bus_1_w6_reg_scanout[1];

assign data_bus_1_w0_reg_scanin[0]=data_bus_1_w7_reg_scanout[1];
assign data_bus_1_w1_reg_scanin[0]=data_bus_1_w0_reg_scanout[0];
assign data_bus_1_w4_reg_scanin[0]=data_bus_1_w1_reg_scanout[0];
assign data_bus_1_w5_reg_scanin[0]=data_bus_1_w4_reg_scanout[0];
assign data_bus_1_w2_reg_scanin[0]=data_bus_1_w5_reg_scanout[0];
assign data_bus_1_w3_reg_scanin[0]=data_bus_1_w2_reg_scanout[0];
assign data_bus_1_w6_reg_scanin[0]=data_bus_1_w3_reg_scanout[0];
assign data_bus_1_w7_reg_scanin[0]=data_bus_1_w6_reg_scanout[0];


// ***************************END SECTION***************************

assign wrdata_q0_4_scanin[32]=data_bus_1_w7_reg_scanout[0];
assign wrdata_q0_0_scanin[32]=wrdata_q0_4_scanout[32];
assign wrdata_q0_4_scanin[31]=wrdata_q0_0_scanout[32];
assign wrdata_q0_0_scanin[31]=wrdata_q0_4_scanout[31];
assign wrdata_q0_4_scanin[30]=wrdata_q0_0_scanout[31];
assign wrdata_q0_0_scanin[30]=wrdata_q0_4_scanout[30];
assign wrdata_q0_4_scanin[29]=wrdata_q0_0_scanout[30];
assign wrdata_q0_0_scanin[29]=wrdata_q0_4_scanout[29];
assign wrdata_q0_4_scanin[28]=wrdata_q0_0_scanout[29];
assign wrdata_q0_0_scanin[28]=wrdata_q0_4_scanout[28];
assign wrdata_q0_4_scanin[27]=wrdata_q0_0_scanout[28];
assign wrdata_q0_0_scanin[27]=wrdata_q0_4_scanout[27];
assign wrdata_q0_4_scanin[26]=wrdata_q0_0_scanout[27];
assign wrdata_q0_0_scanin[26]=wrdata_q0_4_scanout[26];
assign wrdata_q0_4_scanin[25]=wrdata_q0_0_scanout[26];
assign wrdata_q0_0_scanin[25]=wrdata_q0_4_scanout[25];
assign wrdata_q0_4_scanin[24]=wrdata_q0_0_scanout[25];
assign wrdata_q0_0_scanin[24]=wrdata_q0_4_scanout[24];
assign wrdata_q0_4_scanin[23]=wrdata_q0_0_scanout[24];
assign wrdata_q0_0_scanin[23]=wrdata_q0_4_scanout[23];
assign wrdata_q0_4_scanin[22]=wrdata_q0_0_scanout[23];
assign wrdata_q0_0_scanin[22]=wrdata_q0_4_scanout[22];
assign wrdata_q0_4_scanin[21]=wrdata_q0_0_scanout[22];
assign wrdata_q0_0_scanin[21]=wrdata_q0_4_scanout[21];
assign wrdata_q0_4_scanin[20]=wrdata_q0_0_scanout[21];
assign wrdata_q0_0_scanin[20]=wrdata_q0_4_scanout[20];
assign wrdata_q0_4_scanin[19]=wrdata_q0_0_scanout[20];
assign wrdata_q0_0_scanin[19]=wrdata_q0_4_scanout[19];
assign wrdata_q0_4_scanin[18]=wrdata_q0_0_scanout[19];
assign wrdata_q0_0_scanin[18]=wrdata_q0_4_scanout[18];
assign wrdata_q0_4_scanin[17]=wrdata_q0_0_scanout[18];
assign wrdata_q0_0_scanin[17]=wrdata_q0_4_scanout[17];
assign wrdata_q0_4_scanin[16]=wrdata_q0_0_scanout[17];
assign wrdata_q0_0_scanin[16]=wrdata_q0_4_scanout[16];
assign wrdata_q0_4_scanin[15]=wrdata_q0_0_scanout[16];
assign wrdata_q0_0_scanin[15]=wrdata_q0_4_scanout[15];
assign wrdata_q0_4_scanin[14]=wrdata_q0_0_scanout[15];
assign wrdata_q0_0_scanin[14]=wrdata_q0_4_scanout[14];
assign wrdata_q0_4_scanin[13]=wrdata_q0_0_scanout[14];
assign wrdata_q0_0_scanin[13]=wrdata_q0_4_scanout[13];
assign wrdata_q0_4_scanin[12]=wrdata_q0_0_scanout[13];
assign wrdata_q0_0_scanin[12]=wrdata_q0_4_scanout[12];
assign wrdata_q0_4_scanin[11]=wrdata_q0_0_scanout[12];
assign wrdata_q0_0_scanin[11]=wrdata_q0_4_scanout[11];
assign wrdata_q0_4_scanin[10]=wrdata_q0_0_scanout[11];
assign wrdata_q0_0_scanin[10]=wrdata_q0_4_scanout[10];
assign wrdata_q0_4_scanin[9]=wrdata_q0_0_scanout[10];
assign wrdata_q0_0_scanin[9]=wrdata_q0_4_scanout[9];
assign wrdata_q0_4_scanin[8]=wrdata_q0_0_scanout[9];
assign wrdata_q0_0_scanin[8]=wrdata_q0_4_scanout[8];
assign wrdata_q0_4_scanin[7]=wrdata_q0_0_scanout[8];
assign wrdata_q0_0_scanin[7]=wrdata_q0_4_scanout[7];
assign wrdata_q0_4_scanin[6]=wrdata_q0_0_scanout[7];
assign wrdata_q0_0_scanin[6]=wrdata_q0_4_scanout[6];
assign wrdata_q0_4_scanin[5]=wrdata_q0_0_scanout[6];
assign wrdata_q0_0_scanin[5]=wrdata_q0_4_scanout[5];
assign wrdata_q0_4_scanin[4]=wrdata_q0_0_scanout[5];
assign wrdata_q0_0_scanin[4]=wrdata_q0_4_scanout[4];
assign wrdata_q0_4_scanin[3]=wrdata_q0_0_scanout[4];
assign wrdata_q0_0_scanin[3]=wrdata_q0_4_scanout[3];
assign wrdata_q0_4_scanin[2]=wrdata_q0_0_scanout[3];
assign wrdata_q0_0_scanin[2]=wrdata_q0_4_scanout[2];
assign wrdata_q0_4_scanin[1]=wrdata_q0_0_scanout[2];
assign wrdata_q0_0_scanin[1]=wrdata_q0_4_scanout[1];
assign wrdata_q0_4_scanin[0]=wrdata_q0_0_scanout[1];
assign wrdata_q0_0_scanin[0]=wrdata_q0_4_scanout[0];

// ***************************BEGIN SECTION*************************

assign data_bus_0_w2_reg_scanin[32]=wrdata_q0_0_scanout[0];
assign data_bus_0_w3_reg_scanin[32]=data_bus_0_w2_reg_scanout[32];
assign data_bus_0_w6_reg_scanin[32]=data_bus_0_w3_reg_scanout[32];
assign data_bus_0_w7_reg_scanin[32]=data_bus_0_w6_reg_scanout[32];
assign data_bus_0_w0_reg_scanin[32]=data_bus_0_w7_reg_scanout[32];
assign data_bus_0_w1_reg_scanin[32]=data_bus_0_w0_reg_scanout[32];
assign data_bus_0_w4_reg_scanin[32]=data_bus_0_w1_reg_scanout[32];
assign data_bus_0_w5_reg_scanin[32]=data_bus_0_w4_reg_scanout[32];

assign data_bus_0_w2_reg_scanin[31]=data_bus_0_w5_reg_scanout[32];
assign data_bus_0_w3_reg_scanin[31]=data_bus_0_w2_reg_scanout[31];
assign data_bus_0_w6_reg_scanin[31]=data_bus_0_w3_reg_scanout[31];
assign data_bus_0_w7_reg_scanin[31]=data_bus_0_w6_reg_scanout[31];
assign data_bus_0_w0_reg_scanin[31]=data_bus_0_w7_reg_scanout[31];
assign data_bus_0_w1_reg_scanin[31]=data_bus_0_w0_reg_scanout[31];
assign data_bus_0_w4_reg_scanin[31]=data_bus_0_w1_reg_scanout[31];
assign data_bus_0_w5_reg_scanin[31]=data_bus_0_w4_reg_scanout[31];

assign data_bus_0_w2_reg_scanin[30]=data_bus_0_w5_reg_scanout[31];
assign data_bus_0_w3_reg_scanin[30]=data_bus_0_w2_reg_scanout[30];
assign data_bus_0_w6_reg_scanin[30]=data_bus_0_w3_reg_scanout[30];
assign data_bus_0_w7_reg_scanin[30]=data_bus_0_w6_reg_scanout[30];
assign data_bus_0_w0_reg_scanin[30]=data_bus_0_w7_reg_scanout[30];
assign data_bus_0_w1_reg_scanin[30]=data_bus_0_w0_reg_scanout[30];
assign data_bus_0_w4_reg_scanin[30]=data_bus_0_w1_reg_scanout[30];
assign data_bus_0_w5_reg_scanin[30]=data_bus_0_w4_reg_scanout[30];

assign data_bus_0_w2_reg_scanin[29]=data_bus_0_w5_reg_scanout[30];
assign data_bus_0_w3_reg_scanin[29]=data_bus_0_w2_reg_scanout[29];
assign data_bus_0_w6_reg_scanin[29]=data_bus_0_w3_reg_scanout[29];
assign data_bus_0_w7_reg_scanin[29]=data_bus_0_w6_reg_scanout[29];
assign data_bus_0_w0_reg_scanin[29]=data_bus_0_w7_reg_scanout[29];
assign data_bus_0_w1_reg_scanin[29]=data_bus_0_w0_reg_scanout[29];
assign data_bus_0_w4_reg_scanin[29]=data_bus_0_w1_reg_scanout[29];
assign data_bus_0_w5_reg_scanin[29]=data_bus_0_w4_reg_scanout[29];

assign data_bus_0_w2_reg_scanin[28]=data_bus_0_w5_reg_scanout[29];
assign data_bus_0_w3_reg_scanin[28]=data_bus_0_w2_reg_scanout[28];
assign data_bus_0_w6_reg_scanin[28]=data_bus_0_w3_reg_scanout[28];
assign data_bus_0_w7_reg_scanin[28]=data_bus_0_w6_reg_scanout[28];
assign data_bus_0_w0_reg_scanin[28]=data_bus_0_w7_reg_scanout[28];
assign data_bus_0_w1_reg_scanin[28]=data_bus_0_w0_reg_scanout[28];
assign data_bus_0_w4_reg_scanin[28]=data_bus_0_w1_reg_scanout[28];
assign data_bus_0_w5_reg_scanin[28]=data_bus_0_w4_reg_scanout[28];

assign data_bus_0_w2_reg_scanin[27]=data_bus_0_w5_reg_scanout[28];
assign data_bus_0_w3_reg_scanin[27]=data_bus_0_w2_reg_scanout[27];
assign data_bus_0_w6_reg_scanin[27]=data_bus_0_w3_reg_scanout[27];
assign data_bus_0_w7_reg_scanin[27]=data_bus_0_w6_reg_scanout[27];
assign data_bus_0_w0_reg_scanin[27]=data_bus_0_w7_reg_scanout[27];
assign data_bus_0_w1_reg_scanin[27]=data_bus_0_w0_reg_scanout[27];
assign data_bus_0_w4_reg_scanin[27]=data_bus_0_w1_reg_scanout[27];
assign data_bus_0_w5_reg_scanin[27]=data_bus_0_w4_reg_scanout[27];

assign data_bus_0_w2_reg_scanin[26]=data_bus_0_w5_reg_scanout[27];
assign data_bus_0_w3_reg_scanin[26]=data_bus_0_w2_reg_scanout[26];
assign data_bus_0_w6_reg_scanin[26]=data_bus_0_w3_reg_scanout[26];
assign data_bus_0_w7_reg_scanin[26]=data_bus_0_w6_reg_scanout[26];
assign data_bus_0_w0_reg_scanin[26]=data_bus_0_w7_reg_scanout[26];
assign data_bus_0_w1_reg_scanin[26]=data_bus_0_w0_reg_scanout[26];
assign data_bus_0_w4_reg_scanin[26]=data_bus_0_w1_reg_scanout[26];
assign data_bus_0_w5_reg_scanin[26]=data_bus_0_w4_reg_scanout[26];

assign data_bus_0_w2_reg_scanin[25]=data_bus_0_w5_reg_scanout[26];
assign data_bus_0_w3_reg_scanin[25]=data_bus_0_w2_reg_scanout[25];
assign data_bus_0_w6_reg_scanin[25]=data_bus_0_w3_reg_scanout[25];
assign data_bus_0_w7_reg_scanin[25]=data_bus_0_w6_reg_scanout[25];
assign data_bus_0_w0_reg_scanin[25]=data_bus_0_w7_reg_scanout[25];
assign data_bus_0_w1_reg_scanin[25]=data_bus_0_w0_reg_scanout[25];
assign data_bus_0_w4_reg_scanin[25]=data_bus_0_w1_reg_scanout[25];
assign data_bus_0_w5_reg_scanin[25]=data_bus_0_w4_reg_scanout[25];

assign data_bus_0_w2_reg_scanin[24]=data_bus_0_w5_reg_scanout[25];
assign data_bus_0_w3_reg_scanin[24]=data_bus_0_w2_reg_scanout[24];
assign data_bus_0_w6_reg_scanin[24]=data_bus_0_w3_reg_scanout[24];
assign data_bus_0_w7_reg_scanin[24]=data_bus_0_w6_reg_scanout[24];
assign data_bus_0_w0_reg_scanin[24]=data_bus_0_w7_reg_scanout[24];
assign data_bus_0_w1_reg_scanin[24]=data_bus_0_w0_reg_scanout[24];
assign data_bus_0_w4_reg_scanin[24]=data_bus_0_w1_reg_scanout[24];
assign data_bus_0_w5_reg_scanin[24]=data_bus_0_w4_reg_scanout[24];

assign data_bus_0_w2_reg_scanin[23]=data_bus_0_w5_reg_scanout[24];
assign data_bus_0_w3_reg_scanin[23]=data_bus_0_w2_reg_scanout[23];
assign data_bus_0_w6_reg_scanin[23]=data_bus_0_w3_reg_scanout[23];
assign data_bus_0_w7_reg_scanin[23]=data_bus_0_w6_reg_scanout[23];
assign data_bus_0_w0_reg_scanin[23]=data_bus_0_w7_reg_scanout[23];
assign data_bus_0_w1_reg_scanin[23]=data_bus_0_w0_reg_scanout[23];
assign data_bus_0_w4_reg_scanin[23]=data_bus_0_w1_reg_scanout[23];
assign data_bus_0_w5_reg_scanin[23]=data_bus_0_w4_reg_scanout[23];

assign data_bus_0_w2_reg_scanin[22]=data_bus_0_w5_reg_scanout[23];
assign data_bus_0_w3_reg_scanin[22]=data_bus_0_w2_reg_scanout[22];
assign data_bus_0_w6_reg_scanin[22]=data_bus_0_w3_reg_scanout[22];
assign data_bus_0_w7_reg_scanin[22]=data_bus_0_w6_reg_scanout[22];
assign data_bus_0_w0_reg_scanin[22]=data_bus_0_w7_reg_scanout[22];
assign data_bus_0_w1_reg_scanin[22]=data_bus_0_w0_reg_scanout[22];
assign data_bus_0_w4_reg_scanin[22]=data_bus_0_w1_reg_scanout[22];
assign data_bus_0_w5_reg_scanin[22]=data_bus_0_w4_reg_scanout[22];

assign data_bus_0_w2_reg_scanin[21]=data_bus_0_w5_reg_scanout[22];
assign data_bus_0_w3_reg_scanin[21]=data_bus_0_w2_reg_scanout[21];
assign data_bus_0_w6_reg_scanin[21]=data_bus_0_w3_reg_scanout[21];
assign data_bus_0_w7_reg_scanin[21]=data_bus_0_w6_reg_scanout[21];
assign data_bus_0_w0_reg_scanin[21]=data_bus_0_w7_reg_scanout[21];
assign data_bus_0_w1_reg_scanin[21]=data_bus_0_w0_reg_scanout[21];
assign data_bus_0_w4_reg_scanin[21]=data_bus_0_w1_reg_scanout[21];
assign data_bus_0_w5_reg_scanin[21]=data_bus_0_w4_reg_scanout[21];

assign data_bus_0_w2_reg_scanin[20]=data_bus_0_w5_reg_scanout[21];
assign data_bus_0_w3_reg_scanin[20]=data_bus_0_w2_reg_scanout[20];
assign data_bus_0_w6_reg_scanin[20]=data_bus_0_w3_reg_scanout[20];
assign data_bus_0_w7_reg_scanin[20]=data_bus_0_w6_reg_scanout[20];
assign data_bus_0_w0_reg_scanin[20]=data_bus_0_w7_reg_scanout[20];
assign data_bus_0_w1_reg_scanin[20]=data_bus_0_w0_reg_scanout[20];
assign data_bus_0_w4_reg_scanin[20]=data_bus_0_w1_reg_scanout[20];
assign data_bus_0_w5_reg_scanin[20]=data_bus_0_w4_reg_scanout[20];

assign data_bus_0_w2_reg_scanin[19]=data_bus_0_w5_reg_scanout[20];
assign data_bus_0_w3_reg_scanin[19]=data_bus_0_w2_reg_scanout[19];
assign data_bus_0_w6_reg_scanin[19]=data_bus_0_w3_reg_scanout[19];
assign data_bus_0_w7_reg_scanin[19]=data_bus_0_w6_reg_scanout[19];
assign data_bus_0_w0_reg_scanin[19]=data_bus_0_w7_reg_scanout[19];
assign data_bus_0_w1_reg_scanin[19]=data_bus_0_w0_reg_scanout[19];
assign data_bus_0_w4_reg_scanin[19]=data_bus_0_w1_reg_scanout[19];
assign data_bus_0_w5_reg_scanin[19]=data_bus_0_w4_reg_scanout[19];

assign data_bus_0_w2_reg_scanin[18]=data_bus_0_w5_reg_scanout[19];
assign data_bus_0_w3_reg_scanin[18]=data_bus_0_w2_reg_scanout[18];
assign data_bus_0_w6_reg_scanin[18]=data_bus_0_w3_reg_scanout[18];
assign data_bus_0_w7_reg_scanin[18]=data_bus_0_w6_reg_scanout[18];
assign data_bus_0_w0_reg_scanin[18]=data_bus_0_w7_reg_scanout[18];
assign data_bus_0_w1_reg_scanin[18]=data_bus_0_w0_reg_scanout[18];
assign data_bus_0_w4_reg_scanin[18]=data_bus_0_w1_reg_scanout[18];
assign data_bus_0_w5_reg_scanin[18]=data_bus_0_w4_reg_scanout[18];

assign data_bus_0_w2_reg_scanin[17]=data_bus_0_w5_reg_scanout[18];
assign data_bus_0_w3_reg_scanin[17]=data_bus_0_w2_reg_scanout[17];
assign data_bus_0_w6_reg_scanin[17]=data_bus_0_w3_reg_scanout[17];
assign data_bus_0_w7_reg_scanin[17]=data_bus_0_w6_reg_scanout[17];
assign data_bus_0_w0_reg_scanin[17]=data_bus_0_w7_reg_scanout[17];
assign data_bus_0_w1_reg_scanin[17]=data_bus_0_w0_reg_scanout[17];
assign data_bus_0_w4_reg_scanin[17]=data_bus_0_w1_reg_scanout[17];
assign data_bus_0_w5_reg_scanin[17]=data_bus_0_w4_reg_scanout[17];

assign data_bus_0_w0_reg_scanin[16]=data_bus_0_w5_reg_scanout[17];
assign data_bus_0_w1_reg_scanin[16]=data_bus_0_w0_reg_scanout[16];
assign data_bus_0_w4_reg_scanin[16]=data_bus_0_w1_reg_scanout[16];
assign data_bus_0_w5_reg_scanin[16]=data_bus_0_w4_reg_scanout[16];
assign data_bus_0_w2_reg_scanin[16]=data_bus_0_w5_reg_scanout[16];
assign data_bus_0_w3_reg_scanin[16]=data_bus_0_w2_reg_scanout[16];
assign data_bus_0_w6_reg_scanin[16]=data_bus_0_w3_reg_scanout[16];
assign data_bus_0_w7_reg_scanin[16]=data_bus_0_w6_reg_scanout[16];

assign data_bus_0_w0_reg_scanin[15]=data_bus_0_w7_reg_scanout[16];
assign data_bus_0_w1_reg_scanin[15]=data_bus_0_w0_reg_scanout[15];
assign data_bus_0_w4_reg_scanin[15]=data_bus_0_w1_reg_scanout[15];
assign data_bus_0_w5_reg_scanin[15]=data_bus_0_w4_reg_scanout[15];
assign data_bus_0_w2_reg_scanin[15]=data_bus_0_w5_reg_scanout[15];
assign data_bus_0_w3_reg_scanin[15]=data_bus_0_w2_reg_scanout[15];
assign data_bus_0_w6_reg_scanin[15]=data_bus_0_w3_reg_scanout[15];
assign data_bus_0_w7_reg_scanin[15]=data_bus_0_w6_reg_scanout[15];

assign data_bus_0_w0_reg_scanin[14]=data_bus_0_w7_reg_scanout[15];
assign data_bus_0_w1_reg_scanin[14]=data_bus_0_w0_reg_scanout[14];
assign data_bus_0_w4_reg_scanin[14]=data_bus_0_w1_reg_scanout[14];
assign data_bus_0_w5_reg_scanin[14]=data_bus_0_w4_reg_scanout[14];
assign data_bus_0_w2_reg_scanin[14]=data_bus_0_w5_reg_scanout[14];
assign data_bus_0_w3_reg_scanin[14]=data_bus_0_w2_reg_scanout[14];
assign data_bus_0_w6_reg_scanin[14]=data_bus_0_w3_reg_scanout[14];
assign data_bus_0_w7_reg_scanin[14]=data_bus_0_w6_reg_scanout[14];

assign data_bus_0_w0_reg_scanin[13]=data_bus_0_w7_reg_scanout[14];
assign data_bus_0_w1_reg_scanin[13]=data_bus_0_w0_reg_scanout[13];
assign data_bus_0_w4_reg_scanin[13]=data_bus_0_w1_reg_scanout[13];
assign data_bus_0_w5_reg_scanin[13]=data_bus_0_w4_reg_scanout[13];
assign data_bus_0_w2_reg_scanin[13]=data_bus_0_w5_reg_scanout[13];
assign data_bus_0_w3_reg_scanin[13]=data_bus_0_w2_reg_scanout[13];
assign data_bus_0_w6_reg_scanin[13]=data_bus_0_w3_reg_scanout[13];
assign data_bus_0_w7_reg_scanin[13]=data_bus_0_w6_reg_scanout[13];

assign data_bus_0_w0_reg_scanin[12]=data_bus_0_w7_reg_scanout[13];
assign data_bus_0_w1_reg_scanin[12]=data_bus_0_w0_reg_scanout[12];
assign data_bus_0_w4_reg_scanin[12]=data_bus_0_w1_reg_scanout[12];
assign data_bus_0_w5_reg_scanin[12]=data_bus_0_w4_reg_scanout[12];
assign data_bus_0_w2_reg_scanin[12]=data_bus_0_w5_reg_scanout[12];
assign data_bus_0_w3_reg_scanin[12]=data_bus_0_w2_reg_scanout[12];
assign data_bus_0_w6_reg_scanin[12]=data_bus_0_w3_reg_scanout[12];
assign data_bus_0_w7_reg_scanin[12]=data_bus_0_w6_reg_scanout[12];

assign data_bus_0_w0_reg_scanin[11]=data_bus_0_w7_reg_scanout[12];
assign data_bus_0_w1_reg_scanin[11]=data_bus_0_w0_reg_scanout[11];
assign data_bus_0_w4_reg_scanin[11]=data_bus_0_w1_reg_scanout[11];
assign data_bus_0_w5_reg_scanin[11]=data_bus_0_w4_reg_scanout[11];
assign data_bus_0_w2_reg_scanin[11]=data_bus_0_w5_reg_scanout[11];
assign data_bus_0_w3_reg_scanin[11]=data_bus_0_w2_reg_scanout[11];
assign data_bus_0_w6_reg_scanin[11]=data_bus_0_w3_reg_scanout[11];
assign data_bus_0_w7_reg_scanin[11]=data_bus_0_w6_reg_scanout[11];

assign data_bus_0_w0_reg_scanin[10]=data_bus_0_w7_reg_scanout[11];
assign data_bus_0_w1_reg_scanin[10]=data_bus_0_w0_reg_scanout[10];
assign data_bus_0_w4_reg_scanin[10]=data_bus_0_w1_reg_scanout[10];
assign data_bus_0_w5_reg_scanin[10]=data_bus_0_w4_reg_scanout[10];
assign data_bus_0_w2_reg_scanin[10]=data_bus_0_w5_reg_scanout[10];
assign data_bus_0_w3_reg_scanin[10]=data_bus_0_w2_reg_scanout[10];
assign data_bus_0_w6_reg_scanin[10]=data_bus_0_w3_reg_scanout[10];
assign data_bus_0_w7_reg_scanin[10]=data_bus_0_w6_reg_scanout[10];

assign data_bus_0_w0_reg_scanin[9]=data_bus_0_w7_reg_scanout[10];
assign data_bus_0_w1_reg_scanin[9]=data_bus_0_w0_reg_scanout[9];
assign data_bus_0_w4_reg_scanin[9]=data_bus_0_w1_reg_scanout[9];
assign data_bus_0_w5_reg_scanin[9]=data_bus_0_w4_reg_scanout[9];
assign data_bus_0_w2_reg_scanin[9]=data_bus_0_w5_reg_scanout[9];
assign data_bus_0_w3_reg_scanin[9]=data_bus_0_w2_reg_scanout[9];
assign data_bus_0_w6_reg_scanin[9]=data_bus_0_w3_reg_scanout[9];
assign data_bus_0_w7_reg_scanin[9]=data_bus_0_w6_reg_scanout[9];

assign data_bus_0_w0_reg_scanin[8]=data_bus_0_w7_reg_scanout[9];
assign data_bus_0_w1_reg_scanin[8]=data_bus_0_w0_reg_scanout[8];
assign data_bus_0_w4_reg_scanin[8]=data_bus_0_w1_reg_scanout[8];
assign data_bus_0_w5_reg_scanin[8]=data_bus_0_w4_reg_scanout[8];
assign data_bus_0_w2_reg_scanin[8]=data_bus_0_w5_reg_scanout[8];
assign data_bus_0_w3_reg_scanin[8]=data_bus_0_w2_reg_scanout[8];
assign data_bus_0_w6_reg_scanin[8]=data_bus_0_w3_reg_scanout[8];
assign data_bus_0_w7_reg_scanin[8]=data_bus_0_w6_reg_scanout[8];

assign data_bus_0_w0_reg_scanin[7]=data_bus_0_w7_reg_scanout[8];
assign data_bus_0_w1_reg_scanin[7]=data_bus_0_w0_reg_scanout[7];
assign data_bus_0_w4_reg_scanin[7]=data_bus_0_w1_reg_scanout[7];
assign data_bus_0_w5_reg_scanin[7]=data_bus_0_w4_reg_scanout[7];
assign data_bus_0_w2_reg_scanin[7]=data_bus_0_w5_reg_scanout[7];
assign data_bus_0_w3_reg_scanin[7]=data_bus_0_w2_reg_scanout[7];
assign data_bus_0_w6_reg_scanin[7]=data_bus_0_w3_reg_scanout[7];
assign data_bus_0_w7_reg_scanin[7]=data_bus_0_w6_reg_scanout[7];

assign data_bus_0_w0_reg_scanin[6]=data_bus_0_w7_reg_scanout[7];
assign data_bus_0_w1_reg_scanin[6]=data_bus_0_w0_reg_scanout[6];
assign data_bus_0_w4_reg_scanin[6]=data_bus_0_w1_reg_scanout[6];
assign data_bus_0_w5_reg_scanin[6]=data_bus_0_w4_reg_scanout[6];
assign data_bus_0_w2_reg_scanin[6]=data_bus_0_w5_reg_scanout[6];
assign data_bus_0_w3_reg_scanin[6]=data_bus_0_w2_reg_scanout[6];
assign data_bus_0_w6_reg_scanin[6]=data_bus_0_w3_reg_scanout[6];
assign data_bus_0_w7_reg_scanin[6]=data_bus_0_w6_reg_scanout[6];

assign data_bus_0_w0_reg_scanin[5]=data_bus_0_w7_reg_scanout[6];
assign data_bus_0_w1_reg_scanin[5]=data_bus_0_w0_reg_scanout[5];
assign data_bus_0_w4_reg_scanin[5]=data_bus_0_w1_reg_scanout[5];
assign data_bus_0_w5_reg_scanin[5]=data_bus_0_w4_reg_scanout[5];
assign data_bus_0_w2_reg_scanin[5]=data_bus_0_w5_reg_scanout[5];
assign data_bus_0_w3_reg_scanin[5]=data_bus_0_w2_reg_scanout[5];
assign data_bus_0_w6_reg_scanin[5]=data_bus_0_w3_reg_scanout[5];
assign data_bus_0_w7_reg_scanin[5]=data_bus_0_w6_reg_scanout[5];

assign data_bus_0_w0_reg_scanin[4]=data_bus_0_w7_reg_scanout[5];
assign data_bus_0_w1_reg_scanin[4]=data_bus_0_w0_reg_scanout[4];
assign data_bus_0_w4_reg_scanin[4]=data_bus_0_w1_reg_scanout[4];
assign data_bus_0_w5_reg_scanin[4]=data_bus_0_w4_reg_scanout[4];
assign data_bus_0_w2_reg_scanin[4]=data_bus_0_w5_reg_scanout[4];
assign data_bus_0_w3_reg_scanin[4]=data_bus_0_w2_reg_scanout[4];
assign data_bus_0_w6_reg_scanin[4]=data_bus_0_w3_reg_scanout[4];
assign data_bus_0_w7_reg_scanin[4]=data_bus_0_w6_reg_scanout[4];

assign data_bus_0_w0_reg_scanin[3]=data_bus_0_w7_reg_scanout[4];
assign data_bus_0_w1_reg_scanin[3]=data_bus_0_w0_reg_scanout[3];
assign data_bus_0_w4_reg_scanin[3]=data_bus_0_w1_reg_scanout[3];
assign data_bus_0_w5_reg_scanin[3]=data_bus_0_w4_reg_scanout[3];
assign data_bus_0_w2_reg_scanin[3]=data_bus_0_w5_reg_scanout[3];
assign data_bus_0_w3_reg_scanin[3]=data_bus_0_w2_reg_scanout[3];
assign data_bus_0_w6_reg_scanin[3]=data_bus_0_w3_reg_scanout[3];
assign data_bus_0_w7_reg_scanin[3]=data_bus_0_w6_reg_scanout[3];

assign data_bus_0_w0_reg_scanin[2]=data_bus_0_w7_reg_scanout[3];
assign data_bus_0_w1_reg_scanin[2]=data_bus_0_w0_reg_scanout[2];
assign data_bus_0_w4_reg_scanin[2]=data_bus_0_w1_reg_scanout[2];
assign data_bus_0_w5_reg_scanin[2]=data_bus_0_w4_reg_scanout[2];
assign data_bus_0_w2_reg_scanin[2]=data_bus_0_w5_reg_scanout[2];
assign data_bus_0_w3_reg_scanin[2]=data_bus_0_w2_reg_scanout[2];
assign data_bus_0_w6_reg_scanin[2]=data_bus_0_w3_reg_scanout[2];
assign data_bus_0_w7_reg_scanin[2]=data_bus_0_w6_reg_scanout[2];

assign data_bus_0_w0_reg_scanin[1]=data_bus_0_w7_reg_scanout[2];
assign data_bus_0_w1_reg_scanin[1]=data_bus_0_w0_reg_scanout[1];
assign data_bus_0_w4_reg_scanin[1]=data_bus_0_w1_reg_scanout[1];
assign data_bus_0_w5_reg_scanin[1]=data_bus_0_w4_reg_scanout[1];
assign data_bus_0_w2_reg_scanin[1]=data_bus_0_w5_reg_scanout[1];
assign data_bus_0_w3_reg_scanin[1]=data_bus_0_w2_reg_scanout[1];
assign data_bus_0_w6_reg_scanin[1]=data_bus_0_w3_reg_scanout[1];
assign data_bus_0_w7_reg_scanin[1]=data_bus_0_w6_reg_scanout[1];

assign data_bus_0_w0_reg_scanin[0]=data_bus_0_w7_reg_scanout[1];
assign data_bus_0_w1_reg_scanin[0]=data_bus_0_w0_reg_scanout[0];
assign data_bus_0_w4_reg_scanin[0]=data_bus_0_w1_reg_scanout[0];
assign data_bus_0_w5_reg_scanin[0]=data_bus_0_w4_reg_scanout[0];
assign data_bus_0_w2_reg_scanin[0]=data_bus_0_w5_reg_scanout[0];
assign data_bus_0_w3_reg_scanin[0]=data_bus_0_w2_reg_scanout[0];
assign data_bus_0_w6_reg_scanin[0]=data_bus_0_w3_reg_scanout[0];
assign data_bus_0_w7_reg_scanin[0]=data_bus_0_w6_reg_scanout[0];


// ***************************END SECTION***************************

//////////////////////////
// Middle section scan  //   
//////////////////////////


assign red_en_reg_scanin[0] = data_bus_0_w7_reg_scanout[0];
assign red_en_reg_scanin[1] = red_en_reg_scanout[0];
assign red_en_out_reg_scanin[0] = red_en_reg_scanout[1];
assign red_en_out_reg_scanin[1] = red_en_out_reg_scanout[0];
assign red_arst_reg_scanin  =  red_en_out_reg_scanout[1];
assign red_wen_reg_scanin   =  red_arst_reg_scanout;
assign red_d_out_reg_scanin[0]  =  red_wen_reg_scanout;
assign red_d_out_reg_scanin[1]  =  red_d_out_reg_scanout[0];
assign red_d_out_reg_scanin[3]  =  red_d_out_reg_scanout[1];
assign red_d_out_reg_scanin[2]  =  red_d_out_reg_scanout[3];
assign red_d_out_reg_scanin[4]  =  red_d_out_reg_scanout[2];
assign rid_reg_scanin[1]    =  red_d_out_reg_scanout[4];
assign rid_reg_scanin[0]    =  rid_reg_scanout[1];
assign rid_reg_scanin[3]    =  rid_reg_scanout[0];
assign rid_reg_scanin[2]    =  rid_reg_scanout[3];
assign red_d_reg_scanin[0]  =  rid_reg_scanout[2];
assign red_d_reg_scanin[3]  =  red_d_reg_scanout[0];
assign red_d_reg_scanin[4]  =  red_d_reg_scanout[3];
assign red_d_reg_scanin[1]  =  red_d_reg_scanout[4];
assign red_d_reg_scanin[2]  =  red_d_reg_scanout[1];
assign quad_en_reg_scanin[2]= red_d_reg_scanout[2];   
assign quad_en_reg_scanin[0]= quad_en_reg_scanout[2]; 
assign index_reg_i_scanin    =  quad_en_reg_scanout[0] ;
assign way_f_reg_scanin[4]   =  index_reg_i_scanout ; 
assign way_f_reg_scanin[5]   =  way_f_reg_scanout[4] ; 
assign way_f_reg_scanin[6]   =  way_f_reg_scanout[5] ; 
assign way_f_reg_scanin[7]   =  way_f_reg_scanout[6] ; 
assign quad_en_1_latch_scanin = way_f_reg_scanout[7] ;
assign quad_en_0_latch_scanin = quad_en_1_latch_scanout ;  
assign wr_word_en_5_reg_scanin =  quad_en_0_latch_scanout ; 
assign wr_word_en_1_reg_scanin =  wr_word_en_5_reg_scanout ;
assign wr_word_en_0_reg_scanin =  wr_word_en_1_reg_scanout ;
assign wr_word_en_4_reg_scanin =  wr_word_en_0_reg_scanout ;
assign wr_word_en_6_reg_scanin =  wr_word_en_4_reg_scanout ;
assign wr_word_en_2_reg_scanin =  wr_word_en_6_reg_scanout ;
assign wr_word_en_7_reg_scanin =  wr_word_en_2_reg_scanout ;
assign wr_word_en_3_reg_scanin =  wr_word_en_7_reg_scanout ;
assign quad_en_3_latch_scanin = wr_word_en_3_reg_scanout ;  
assign quad_en_2_latch_scanin = quad_en_3_latch_scanout ;  
assign way_f_reg_scanin[0]   =  quad_en_2_latch_scanout ; 
assign way_f_reg_scanin[1]   =  way_f_reg_scanout[0] ;     
assign way_f_reg_scanin[2]   =  way_f_reg_scanout[1] ;     
assign way_f_reg_scanin[3]   =  way_f_reg_scanout[2] ;     
assign wrway_0_reg_scanin      =  way_f_reg_scanout[3] ;
assign wrway_1_reg_scanin      =  wrway_0_reg_scanout ;
assign wrway_2_reg_scanin      =  wrway_1_reg_scanout ;
assign wrreq_reg_scanin      =  wrway_2_reg_scanout    ;
assign rdreq_reg_scanin      =  wrreq_reg_scanout    ;
assign quad_en_reg_scanin[3]= rdreq_reg_scanout   ;   
assign quad_en_reg_scanin[1]= quad_en_reg_scanout[3]; 
assign rdreq_reg_b_scanin    =  quad_en_reg_scanout[1]    ;
assign wrreq_reg_b_scanin    =  rdreq_reg_b_scanout  ;
assign way_c_reg_scanin[7]   =  wrreq_reg_b_scanout  ; 
assign way_c_reg_scanin[6]   =  way_c_reg_scanout[7] ; 
assign way_c_reg_scanin[5]   =  way_c_reg_scanout[6] ; 
assign way_c_reg_scanin[4]   =  way_c_reg_scanout[5] ; 
assign way_c_reg_scanin[3]   =  way_c_reg_scanout[4] ; 
assign way_c_reg_scanin[2]   =  way_c_reg_scanout[3] ; 
assign way_c_reg_scanin[1]   =  way_c_reg_scanout[2] ; 
assign way_c_reg_scanin[0]   =  way_c_reg_scanout[1] ; 


/////// end of middle section                 ///////////////////

assign wrdata_q3_7_scanin[32]=way_c_reg_scanout[0];
assign wrdata_q3_3_scanin[32]=wrdata_q3_7_scanout[32];
assign wrdata_q3_7_scanin[31]=wrdata_q3_3_scanout[32];
assign wrdata_q3_3_scanin[31]=wrdata_q3_7_scanout[31];
assign wrdata_q3_7_scanin[30]=wrdata_q3_3_scanout[31];
assign wrdata_q3_3_scanin[30]=wrdata_q3_7_scanout[30];
assign wrdata_q3_7_scanin[29]=wrdata_q3_3_scanout[30];
assign wrdata_q3_3_scanin[29]=wrdata_q3_7_scanout[29];
assign wrdata_q3_7_scanin[28]=wrdata_q3_3_scanout[29];
assign wrdata_q3_3_scanin[28]=wrdata_q3_7_scanout[28];
assign wrdata_q3_7_scanin[27]=wrdata_q3_3_scanout[28];
assign wrdata_q3_3_scanin[27]=wrdata_q3_7_scanout[27];
assign wrdata_q3_7_scanin[26]=wrdata_q3_3_scanout[27];
assign wrdata_q3_3_scanin[26]=wrdata_q3_7_scanout[26];
assign wrdata_q3_7_scanin[25]=wrdata_q3_3_scanout[26];
assign wrdata_q3_3_scanin[25]=wrdata_q3_7_scanout[25];
assign wrdata_q3_7_scanin[24]=wrdata_q3_3_scanout[25];
assign wrdata_q3_3_scanin[24]=wrdata_q3_7_scanout[24];
assign wrdata_q3_7_scanin[23]=wrdata_q3_3_scanout[24];
assign wrdata_q3_3_scanin[23]=wrdata_q3_7_scanout[23];
assign wrdata_q3_7_scanin[22]=wrdata_q3_3_scanout[23];
assign wrdata_q3_3_scanin[22]=wrdata_q3_7_scanout[22];
assign wrdata_q3_7_scanin[21]=wrdata_q3_3_scanout[22];
assign wrdata_q3_3_scanin[21]=wrdata_q3_7_scanout[21];
assign wrdata_q3_7_scanin[20]=wrdata_q3_3_scanout[21];
assign wrdata_q3_3_scanin[20]=wrdata_q3_7_scanout[20];
assign wrdata_q3_7_scanin[19]=wrdata_q3_3_scanout[20];
assign wrdata_q3_3_scanin[19]=wrdata_q3_7_scanout[19];
assign wrdata_q3_7_scanin[18]=wrdata_q3_3_scanout[19];
assign wrdata_q3_3_scanin[18]=wrdata_q3_7_scanout[18];
assign wrdata_q3_7_scanin[17]=wrdata_q3_3_scanout[18];
assign wrdata_q3_3_scanin[17]=wrdata_q3_7_scanout[17];
assign wrdata_q3_7_scanin[16]=wrdata_q3_3_scanout[17];
assign wrdata_q3_3_scanin[16]=wrdata_q3_7_scanout[16];
assign wrdata_q3_7_scanin[15]=wrdata_q3_3_scanout[16];
assign wrdata_q3_3_scanin[15]=wrdata_q3_7_scanout[15];
assign wrdata_q3_7_scanin[14]=wrdata_q3_3_scanout[15];
assign wrdata_q3_3_scanin[14]=wrdata_q3_7_scanout[14];
assign wrdata_q3_7_scanin[13]=wrdata_q3_3_scanout[14];
assign wrdata_q3_3_scanin[13]=wrdata_q3_7_scanout[13];
assign wrdata_q3_7_scanin[12]=wrdata_q3_3_scanout[13];
assign wrdata_q3_3_scanin[12]=wrdata_q3_7_scanout[12];
assign wrdata_q3_7_scanin[11]=wrdata_q3_3_scanout[12];
assign wrdata_q3_3_scanin[11]=wrdata_q3_7_scanout[11];
assign wrdata_q3_7_scanin[10]=wrdata_q3_3_scanout[11];
assign wrdata_q3_3_scanin[10]=wrdata_q3_7_scanout[10];
assign wrdata_q3_7_scanin[9]=wrdata_q3_3_scanout[10];
assign wrdata_q3_3_scanin[9]=wrdata_q3_7_scanout[9];
assign wrdata_q3_7_scanin[8]=wrdata_q3_3_scanout[9];
assign wrdata_q3_3_scanin[8]=wrdata_q3_7_scanout[8];
assign wrdata_q3_7_scanin[7]=wrdata_q3_3_scanout[8];
assign wrdata_q3_3_scanin[7]=wrdata_q3_7_scanout[7];
assign wrdata_q3_7_scanin[6]=wrdata_q3_3_scanout[7];
assign wrdata_q3_3_scanin[6]=wrdata_q3_7_scanout[6];
assign wrdata_q3_7_scanin[5]=wrdata_q3_3_scanout[6];
assign wrdata_q3_3_scanin[5]=wrdata_q3_7_scanout[5];
assign wrdata_q3_7_scanin[4]=wrdata_q3_3_scanout[5];
assign wrdata_q3_3_scanin[4]=wrdata_q3_7_scanout[4];
assign wrdata_q3_7_scanin[3]=wrdata_q3_3_scanout[4];
assign wrdata_q3_3_scanin[3]=wrdata_q3_7_scanout[3];
assign wrdata_q3_7_scanin[2]=wrdata_q3_3_scanout[3];
assign wrdata_q3_3_scanin[2]=wrdata_q3_7_scanout[2];
assign wrdata_q3_7_scanin[1]=wrdata_q3_3_scanout[2];
assign wrdata_q3_3_scanin[1]=wrdata_q3_7_scanout[1];
assign wrdata_q3_7_scanin[0]=wrdata_q3_3_scanout[1];
assign wrdata_q3_3_scanin[0]=wrdata_q3_7_scanout[0];

// ***************************BEGIN SECTION*************************

assign data_bus_3_w2_reg_scanin[32]=wrdata_q3_3_scanout[0];
assign data_bus_3_w3_reg_scanin[32]=data_bus_3_w2_reg_scanout[32];
assign data_bus_3_w6_reg_scanin[32]=data_bus_3_w3_reg_scanout[32];
assign data_bus_3_w7_reg_scanin[32]=data_bus_3_w6_reg_scanout[32];
assign data_bus_3_w0_reg_scanin[32]=data_bus_3_w7_reg_scanout[32];
assign data_bus_3_w1_reg_scanin[32]=data_bus_3_w0_reg_scanout[32];
assign data_bus_3_w4_reg_scanin[32]=data_bus_3_w1_reg_scanout[32];
assign data_bus_3_w5_reg_scanin[32]=data_bus_3_w4_reg_scanout[32];

assign data_bus_3_w2_reg_scanin[31]=data_bus_3_w5_reg_scanout[32];
assign data_bus_3_w3_reg_scanin[31]=data_bus_3_w2_reg_scanout[31];
assign data_bus_3_w6_reg_scanin[31]=data_bus_3_w3_reg_scanout[31];
assign data_bus_3_w7_reg_scanin[31]=data_bus_3_w6_reg_scanout[31];
assign data_bus_3_w0_reg_scanin[31]=data_bus_3_w7_reg_scanout[31];
assign data_bus_3_w1_reg_scanin[31]=data_bus_3_w0_reg_scanout[31];
assign data_bus_3_w4_reg_scanin[31]=data_bus_3_w1_reg_scanout[31];
assign data_bus_3_w5_reg_scanin[31]=data_bus_3_w4_reg_scanout[31];

assign data_bus_3_w2_reg_scanin[30]=data_bus_3_w5_reg_scanout[31];
assign data_bus_3_w3_reg_scanin[30]=data_bus_3_w2_reg_scanout[30];
assign data_bus_3_w6_reg_scanin[30]=data_bus_3_w3_reg_scanout[30];
assign data_bus_3_w7_reg_scanin[30]=data_bus_3_w6_reg_scanout[30];
assign data_bus_3_w0_reg_scanin[30]=data_bus_3_w7_reg_scanout[30];
assign data_bus_3_w1_reg_scanin[30]=data_bus_3_w0_reg_scanout[30];
assign data_bus_3_w4_reg_scanin[30]=data_bus_3_w1_reg_scanout[30];
assign data_bus_3_w5_reg_scanin[30]=data_bus_3_w4_reg_scanout[30];

assign data_bus_3_w2_reg_scanin[29]=data_bus_3_w5_reg_scanout[30];
assign data_bus_3_w3_reg_scanin[29]=data_bus_3_w2_reg_scanout[29];
assign data_bus_3_w6_reg_scanin[29]=data_bus_3_w3_reg_scanout[29];
assign data_bus_3_w7_reg_scanin[29]=data_bus_3_w6_reg_scanout[29];
assign data_bus_3_w0_reg_scanin[29]=data_bus_3_w7_reg_scanout[29];
assign data_bus_3_w1_reg_scanin[29]=data_bus_3_w0_reg_scanout[29];
assign data_bus_3_w4_reg_scanin[29]=data_bus_3_w1_reg_scanout[29];
assign data_bus_3_w5_reg_scanin[29]=data_bus_3_w4_reg_scanout[29];

assign data_bus_3_w2_reg_scanin[28]=data_bus_3_w5_reg_scanout[29];
assign data_bus_3_w3_reg_scanin[28]=data_bus_3_w2_reg_scanout[28];
assign data_bus_3_w6_reg_scanin[28]=data_bus_3_w3_reg_scanout[28];
assign data_bus_3_w7_reg_scanin[28]=data_bus_3_w6_reg_scanout[28];
assign data_bus_3_w0_reg_scanin[28]=data_bus_3_w7_reg_scanout[28];
assign data_bus_3_w1_reg_scanin[28]=data_bus_3_w0_reg_scanout[28];
assign data_bus_3_w4_reg_scanin[28]=data_bus_3_w1_reg_scanout[28];
assign data_bus_3_w5_reg_scanin[28]=data_bus_3_w4_reg_scanout[28];

assign data_bus_3_w2_reg_scanin[27]=data_bus_3_w5_reg_scanout[28];
assign data_bus_3_w3_reg_scanin[27]=data_bus_3_w2_reg_scanout[27];
assign data_bus_3_w6_reg_scanin[27]=data_bus_3_w3_reg_scanout[27];
assign data_bus_3_w7_reg_scanin[27]=data_bus_3_w6_reg_scanout[27];
assign data_bus_3_w0_reg_scanin[27]=data_bus_3_w7_reg_scanout[27];
assign data_bus_3_w1_reg_scanin[27]=data_bus_3_w0_reg_scanout[27];
assign data_bus_3_w4_reg_scanin[27]=data_bus_3_w1_reg_scanout[27];
assign data_bus_3_w5_reg_scanin[27]=data_bus_3_w4_reg_scanout[27];

assign data_bus_3_w2_reg_scanin[26]=data_bus_3_w5_reg_scanout[27];
assign data_bus_3_w3_reg_scanin[26]=data_bus_3_w2_reg_scanout[26];
assign data_bus_3_w6_reg_scanin[26]=data_bus_3_w3_reg_scanout[26];
assign data_bus_3_w7_reg_scanin[26]=data_bus_3_w6_reg_scanout[26];
assign data_bus_3_w0_reg_scanin[26]=data_bus_3_w7_reg_scanout[26];
assign data_bus_3_w1_reg_scanin[26]=data_bus_3_w0_reg_scanout[26];
assign data_bus_3_w4_reg_scanin[26]=data_bus_3_w1_reg_scanout[26];
assign data_bus_3_w5_reg_scanin[26]=data_bus_3_w4_reg_scanout[26];

assign data_bus_3_w2_reg_scanin[25]=data_bus_3_w5_reg_scanout[26];
assign data_bus_3_w3_reg_scanin[25]=data_bus_3_w2_reg_scanout[25];
assign data_bus_3_w6_reg_scanin[25]=data_bus_3_w3_reg_scanout[25];
assign data_bus_3_w7_reg_scanin[25]=data_bus_3_w6_reg_scanout[25];
assign data_bus_3_w0_reg_scanin[25]=data_bus_3_w7_reg_scanout[25];
assign data_bus_3_w1_reg_scanin[25]=data_bus_3_w0_reg_scanout[25];
assign data_bus_3_w4_reg_scanin[25]=data_bus_3_w1_reg_scanout[25];
assign data_bus_3_w5_reg_scanin[25]=data_bus_3_w4_reg_scanout[25];

assign data_bus_3_w2_reg_scanin[24]=data_bus_3_w5_reg_scanout[25];
assign data_bus_3_w3_reg_scanin[24]=data_bus_3_w2_reg_scanout[24];
assign data_bus_3_w6_reg_scanin[24]=data_bus_3_w3_reg_scanout[24];
assign data_bus_3_w7_reg_scanin[24]=data_bus_3_w6_reg_scanout[24];
assign data_bus_3_w0_reg_scanin[24]=data_bus_3_w7_reg_scanout[24];
assign data_bus_3_w1_reg_scanin[24]=data_bus_3_w0_reg_scanout[24];
assign data_bus_3_w4_reg_scanin[24]=data_bus_3_w1_reg_scanout[24];
assign data_bus_3_w5_reg_scanin[24]=data_bus_3_w4_reg_scanout[24];

assign data_bus_3_w2_reg_scanin[23]=data_bus_3_w5_reg_scanout[24];
assign data_bus_3_w3_reg_scanin[23]=data_bus_3_w2_reg_scanout[23];
assign data_bus_3_w6_reg_scanin[23]=data_bus_3_w3_reg_scanout[23];
assign data_bus_3_w7_reg_scanin[23]=data_bus_3_w6_reg_scanout[23];
assign data_bus_3_w0_reg_scanin[23]=data_bus_3_w7_reg_scanout[23];
assign data_bus_3_w1_reg_scanin[23]=data_bus_3_w0_reg_scanout[23];
assign data_bus_3_w4_reg_scanin[23]=data_bus_3_w1_reg_scanout[23];
assign data_bus_3_w5_reg_scanin[23]=data_bus_3_w4_reg_scanout[23];

assign data_bus_3_w2_reg_scanin[22]=data_bus_3_w5_reg_scanout[23];
assign data_bus_3_w3_reg_scanin[22]=data_bus_3_w2_reg_scanout[22];
assign data_bus_3_w6_reg_scanin[22]=data_bus_3_w3_reg_scanout[22];
assign data_bus_3_w7_reg_scanin[22]=data_bus_3_w6_reg_scanout[22];
assign data_bus_3_w0_reg_scanin[22]=data_bus_3_w7_reg_scanout[22];
assign data_bus_3_w1_reg_scanin[22]=data_bus_3_w0_reg_scanout[22];
assign data_bus_3_w4_reg_scanin[22]=data_bus_3_w1_reg_scanout[22];
assign data_bus_3_w5_reg_scanin[22]=data_bus_3_w4_reg_scanout[22];

assign data_bus_3_w2_reg_scanin[21]=data_bus_3_w5_reg_scanout[22];
assign data_bus_3_w3_reg_scanin[21]=data_bus_3_w2_reg_scanout[21];
assign data_bus_3_w6_reg_scanin[21]=data_bus_3_w3_reg_scanout[21];
assign data_bus_3_w7_reg_scanin[21]=data_bus_3_w6_reg_scanout[21];
assign data_bus_3_w0_reg_scanin[21]=data_bus_3_w7_reg_scanout[21];
assign data_bus_3_w1_reg_scanin[21]=data_bus_3_w0_reg_scanout[21];
assign data_bus_3_w4_reg_scanin[21]=data_bus_3_w1_reg_scanout[21];
assign data_bus_3_w5_reg_scanin[21]=data_bus_3_w4_reg_scanout[21];

assign data_bus_3_w2_reg_scanin[20]=data_bus_3_w5_reg_scanout[21];
assign data_bus_3_w3_reg_scanin[20]=data_bus_3_w2_reg_scanout[20];
assign data_bus_3_w6_reg_scanin[20]=data_bus_3_w3_reg_scanout[20];
assign data_bus_3_w7_reg_scanin[20]=data_bus_3_w6_reg_scanout[20];
assign data_bus_3_w0_reg_scanin[20]=data_bus_3_w7_reg_scanout[20];
assign data_bus_3_w1_reg_scanin[20]=data_bus_3_w0_reg_scanout[20];
assign data_bus_3_w4_reg_scanin[20]=data_bus_3_w1_reg_scanout[20];
assign data_bus_3_w5_reg_scanin[20]=data_bus_3_w4_reg_scanout[20];

assign data_bus_3_w2_reg_scanin[19]=data_bus_3_w5_reg_scanout[20];
assign data_bus_3_w3_reg_scanin[19]=data_bus_3_w2_reg_scanout[19];
assign data_bus_3_w6_reg_scanin[19]=data_bus_3_w3_reg_scanout[19];
assign data_bus_3_w7_reg_scanin[19]=data_bus_3_w6_reg_scanout[19];
assign data_bus_3_w0_reg_scanin[19]=data_bus_3_w7_reg_scanout[19];
assign data_bus_3_w1_reg_scanin[19]=data_bus_3_w0_reg_scanout[19];
assign data_bus_3_w4_reg_scanin[19]=data_bus_3_w1_reg_scanout[19];
assign data_bus_3_w5_reg_scanin[19]=data_bus_3_w4_reg_scanout[19];

assign data_bus_3_w2_reg_scanin[18]=data_bus_3_w5_reg_scanout[19];
assign data_bus_3_w3_reg_scanin[18]=data_bus_3_w2_reg_scanout[18];
assign data_bus_3_w6_reg_scanin[18]=data_bus_3_w3_reg_scanout[18];
assign data_bus_3_w7_reg_scanin[18]=data_bus_3_w6_reg_scanout[18];
assign data_bus_3_w0_reg_scanin[18]=data_bus_3_w7_reg_scanout[18];
assign data_bus_3_w1_reg_scanin[18]=data_bus_3_w0_reg_scanout[18];
assign data_bus_3_w4_reg_scanin[18]=data_bus_3_w1_reg_scanout[18];
assign data_bus_3_w5_reg_scanin[18]=data_bus_3_w4_reg_scanout[18];

assign data_bus_3_w2_reg_scanin[17]=data_bus_3_w5_reg_scanout[18];
assign data_bus_3_w3_reg_scanin[17]=data_bus_3_w2_reg_scanout[17];
assign data_bus_3_w6_reg_scanin[17]=data_bus_3_w3_reg_scanout[17];
assign data_bus_3_w7_reg_scanin[17]=data_bus_3_w6_reg_scanout[17];
assign data_bus_3_w0_reg_scanin[17]=data_bus_3_w7_reg_scanout[17];
assign data_bus_3_w1_reg_scanin[17]=data_bus_3_w0_reg_scanout[17];
assign data_bus_3_w4_reg_scanin[17]=data_bus_3_w1_reg_scanout[17];
assign data_bus_3_w5_reg_scanin[17]=data_bus_3_w4_reg_scanout[17];

assign data_bus_3_w0_reg_scanin[16]=data_bus_3_w5_reg_scanout[17];
assign data_bus_3_w1_reg_scanin[16]=data_bus_3_w0_reg_scanout[16];
assign data_bus_3_w4_reg_scanin[16]=data_bus_3_w1_reg_scanout[16];
assign data_bus_3_w5_reg_scanin[16]=data_bus_3_w4_reg_scanout[16];
assign data_bus_3_w2_reg_scanin[16]=data_bus_3_w5_reg_scanout[16];
assign data_bus_3_w3_reg_scanin[16]=data_bus_3_w2_reg_scanout[16];
assign data_bus_3_w6_reg_scanin[16]=data_bus_3_w3_reg_scanout[16];
assign data_bus_3_w7_reg_scanin[16]=data_bus_3_w6_reg_scanout[16];

assign data_bus_3_w0_reg_scanin[15]=data_bus_3_w7_reg_scanout[16];
assign data_bus_3_w1_reg_scanin[15]=data_bus_3_w0_reg_scanout[15];
assign data_bus_3_w4_reg_scanin[15]=data_bus_3_w1_reg_scanout[15];
assign data_bus_3_w5_reg_scanin[15]=data_bus_3_w4_reg_scanout[15];
assign data_bus_3_w2_reg_scanin[15]=data_bus_3_w5_reg_scanout[15];
assign data_bus_3_w3_reg_scanin[15]=data_bus_3_w2_reg_scanout[15];
assign data_bus_3_w6_reg_scanin[15]=data_bus_3_w3_reg_scanout[15];
assign data_bus_3_w7_reg_scanin[15]=data_bus_3_w6_reg_scanout[15];

assign data_bus_3_w0_reg_scanin[14]=data_bus_3_w7_reg_scanout[15];
assign data_bus_3_w1_reg_scanin[14]=data_bus_3_w0_reg_scanout[14];
assign data_bus_3_w4_reg_scanin[14]=data_bus_3_w1_reg_scanout[14];
assign data_bus_3_w5_reg_scanin[14]=data_bus_3_w4_reg_scanout[14];
assign data_bus_3_w2_reg_scanin[14]=data_bus_3_w5_reg_scanout[14];
assign data_bus_3_w3_reg_scanin[14]=data_bus_3_w2_reg_scanout[14];
assign data_bus_3_w6_reg_scanin[14]=data_bus_3_w3_reg_scanout[14];
assign data_bus_3_w7_reg_scanin[14]=data_bus_3_w6_reg_scanout[14];

assign data_bus_3_w0_reg_scanin[13]=data_bus_3_w7_reg_scanout[14];
assign data_bus_3_w1_reg_scanin[13]=data_bus_3_w0_reg_scanout[13];
assign data_bus_3_w4_reg_scanin[13]=data_bus_3_w1_reg_scanout[13];
assign data_bus_3_w5_reg_scanin[13]=data_bus_3_w4_reg_scanout[13];
assign data_bus_3_w2_reg_scanin[13]=data_bus_3_w5_reg_scanout[13];
assign data_bus_3_w3_reg_scanin[13]=data_bus_3_w2_reg_scanout[13];
assign data_bus_3_w6_reg_scanin[13]=data_bus_3_w3_reg_scanout[13];
assign data_bus_3_w7_reg_scanin[13]=data_bus_3_w6_reg_scanout[13];

assign data_bus_3_w0_reg_scanin[12]=data_bus_3_w7_reg_scanout[13];
assign data_bus_3_w1_reg_scanin[12]=data_bus_3_w0_reg_scanout[12];
assign data_bus_3_w4_reg_scanin[12]=data_bus_3_w1_reg_scanout[12];
assign data_bus_3_w5_reg_scanin[12]=data_bus_3_w4_reg_scanout[12];
assign data_bus_3_w2_reg_scanin[12]=data_bus_3_w5_reg_scanout[12];
assign data_bus_3_w3_reg_scanin[12]=data_bus_3_w2_reg_scanout[12];
assign data_bus_3_w6_reg_scanin[12]=data_bus_3_w3_reg_scanout[12];
assign data_bus_3_w7_reg_scanin[12]=data_bus_3_w6_reg_scanout[12];

assign data_bus_3_w0_reg_scanin[11]=data_bus_3_w7_reg_scanout[12];
assign data_bus_3_w1_reg_scanin[11]=data_bus_3_w0_reg_scanout[11];
assign data_bus_3_w4_reg_scanin[11]=data_bus_3_w1_reg_scanout[11];
assign data_bus_3_w5_reg_scanin[11]=data_bus_3_w4_reg_scanout[11];
assign data_bus_3_w2_reg_scanin[11]=data_bus_3_w5_reg_scanout[11];
assign data_bus_3_w3_reg_scanin[11]=data_bus_3_w2_reg_scanout[11];
assign data_bus_3_w6_reg_scanin[11]=data_bus_3_w3_reg_scanout[11];
assign data_bus_3_w7_reg_scanin[11]=data_bus_3_w6_reg_scanout[11];

assign data_bus_3_w0_reg_scanin[10]=data_bus_3_w7_reg_scanout[11];
assign data_bus_3_w1_reg_scanin[10]=data_bus_3_w0_reg_scanout[10];
assign data_bus_3_w4_reg_scanin[10]=data_bus_3_w1_reg_scanout[10];
assign data_bus_3_w5_reg_scanin[10]=data_bus_3_w4_reg_scanout[10];
assign data_bus_3_w2_reg_scanin[10]=data_bus_3_w5_reg_scanout[10];
assign data_bus_3_w3_reg_scanin[10]=data_bus_3_w2_reg_scanout[10];
assign data_bus_3_w6_reg_scanin[10]=data_bus_3_w3_reg_scanout[10];
assign data_bus_3_w7_reg_scanin[10]=data_bus_3_w6_reg_scanout[10];

assign data_bus_3_w0_reg_scanin[9]=data_bus_3_w7_reg_scanout[10];
assign data_bus_3_w1_reg_scanin[9]=data_bus_3_w0_reg_scanout[9];
assign data_bus_3_w4_reg_scanin[9]=data_bus_3_w1_reg_scanout[9];
assign data_bus_3_w5_reg_scanin[9]=data_bus_3_w4_reg_scanout[9];
assign data_bus_3_w2_reg_scanin[9]=data_bus_3_w5_reg_scanout[9];
assign data_bus_3_w3_reg_scanin[9]=data_bus_3_w2_reg_scanout[9];
assign data_bus_3_w6_reg_scanin[9]=data_bus_3_w3_reg_scanout[9];
assign data_bus_3_w7_reg_scanin[9]=data_bus_3_w6_reg_scanout[9];

assign data_bus_3_w0_reg_scanin[8]=data_bus_3_w7_reg_scanout[9];
assign data_bus_3_w1_reg_scanin[8]=data_bus_3_w0_reg_scanout[8];
assign data_bus_3_w4_reg_scanin[8]=data_bus_3_w1_reg_scanout[8];
assign data_bus_3_w5_reg_scanin[8]=data_bus_3_w4_reg_scanout[8];
assign data_bus_3_w2_reg_scanin[8]=data_bus_3_w5_reg_scanout[8];
assign data_bus_3_w3_reg_scanin[8]=data_bus_3_w2_reg_scanout[8];
assign data_bus_3_w6_reg_scanin[8]=data_bus_3_w3_reg_scanout[8];
assign data_bus_3_w7_reg_scanin[8]=data_bus_3_w6_reg_scanout[8];

assign data_bus_3_w0_reg_scanin[7]=data_bus_3_w7_reg_scanout[8];
assign data_bus_3_w1_reg_scanin[7]=data_bus_3_w0_reg_scanout[7];
assign data_bus_3_w4_reg_scanin[7]=data_bus_3_w1_reg_scanout[7];
assign data_bus_3_w5_reg_scanin[7]=data_bus_3_w4_reg_scanout[7];
assign data_bus_3_w2_reg_scanin[7]=data_bus_3_w5_reg_scanout[7];
assign data_bus_3_w3_reg_scanin[7]=data_bus_3_w2_reg_scanout[7];
assign data_bus_3_w6_reg_scanin[7]=data_bus_3_w3_reg_scanout[7];
assign data_bus_3_w7_reg_scanin[7]=data_bus_3_w6_reg_scanout[7];

assign data_bus_3_w0_reg_scanin[6]=data_bus_3_w7_reg_scanout[7];
assign data_bus_3_w1_reg_scanin[6]=data_bus_3_w0_reg_scanout[6];
assign data_bus_3_w4_reg_scanin[6]=data_bus_3_w1_reg_scanout[6];
assign data_bus_3_w5_reg_scanin[6]=data_bus_3_w4_reg_scanout[6];
assign data_bus_3_w2_reg_scanin[6]=data_bus_3_w5_reg_scanout[6];
assign data_bus_3_w3_reg_scanin[6]=data_bus_3_w2_reg_scanout[6];
assign data_bus_3_w6_reg_scanin[6]=data_bus_3_w3_reg_scanout[6];
assign data_bus_3_w7_reg_scanin[6]=data_bus_3_w6_reg_scanout[6];

assign data_bus_3_w0_reg_scanin[5]=data_bus_3_w7_reg_scanout[6];
assign data_bus_3_w1_reg_scanin[5]=data_bus_3_w0_reg_scanout[5];
assign data_bus_3_w4_reg_scanin[5]=data_bus_3_w1_reg_scanout[5];
assign data_bus_3_w5_reg_scanin[5]=data_bus_3_w4_reg_scanout[5];
assign data_bus_3_w2_reg_scanin[5]=data_bus_3_w5_reg_scanout[5];
assign data_bus_3_w3_reg_scanin[5]=data_bus_3_w2_reg_scanout[5];
assign data_bus_3_w6_reg_scanin[5]=data_bus_3_w3_reg_scanout[5];
assign data_bus_3_w7_reg_scanin[5]=data_bus_3_w6_reg_scanout[5];

assign data_bus_3_w0_reg_scanin[4]=data_bus_3_w7_reg_scanout[5];
assign data_bus_3_w1_reg_scanin[4]=data_bus_3_w0_reg_scanout[4];
assign data_bus_3_w4_reg_scanin[4]=data_bus_3_w1_reg_scanout[4];
assign data_bus_3_w5_reg_scanin[4]=data_bus_3_w4_reg_scanout[4];
assign data_bus_3_w2_reg_scanin[4]=data_bus_3_w5_reg_scanout[4];
assign data_bus_3_w3_reg_scanin[4]=data_bus_3_w2_reg_scanout[4];
assign data_bus_3_w6_reg_scanin[4]=data_bus_3_w3_reg_scanout[4];
assign data_bus_3_w7_reg_scanin[4]=data_bus_3_w6_reg_scanout[4];

assign data_bus_3_w0_reg_scanin[3]=data_bus_3_w7_reg_scanout[4];
assign data_bus_3_w1_reg_scanin[3]=data_bus_3_w0_reg_scanout[3];
assign data_bus_3_w4_reg_scanin[3]=data_bus_3_w1_reg_scanout[3];
assign data_bus_3_w5_reg_scanin[3]=data_bus_3_w4_reg_scanout[3];
assign data_bus_3_w2_reg_scanin[3]=data_bus_3_w5_reg_scanout[3];
assign data_bus_3_w3_reg_scanin[3]=data_bus_3_w2_reg_scanout[3];
assign data_bus_3_w6_reg_scanin[3]=data_bus_3_w3_reg_scanout[3];
assign data_bus_3_w7_reg_scanin[3]=data_bus_3_w6_reg_scanout[3];

assign data_bus_3_w0_reg_scanin[2]=data_bus_3_w7_reg_scanout[3];
assign data_bus_3_w1_reg_scanin[2]=data_bus_3_w0_reg_scanout[2];
assign data_bus_3_w4_reg_scanin[2]=data_bus_3_w1_reg_scanout[2];
assign data_bus_3_w5_reg_scanin[2]=data_bus_3_w4_reg_scanout[2];
assign data_bus_3_w2_reg_scanin[2]=data_bus_3_w5_reg_scanout[2];
assign data_bus_3_w3_reg_scanin[2]=data_bus_3_w2_reg_scanout[2];
assign data_bus_3_w6_reg_scanin[2]=data_bus_3_w3_reg_scanout[2];
assign data_bus_3_w7_reg_scanin[2]=data_bus_3_w6_reg_scanout[2];

assign data_bus_3_w0_reg_scanin[1]=data_bus_3_w7_reg_scanout[2];
assign data_bus_3_w1_reg_scanin[1]=data_bus_3_w0_reg_scanout[1];
assign data_bus_3_w4_reg_scanin[1]=data_bus_3_w1_reg_scanout[1];
assign data_bus_3_w5_reg_scanin[1]=data_bus_3_w4_reg_scanout[1];
assign data_bus_3_w2_reg_scanin[1]=data_bus_3_w5_reg_scanout[1];
assign data_bus_3_w3_reg_scanin[1]=data_bus_3_w2_reg_scanout[1];
assign data_bus_3_w6_reg_scanin[1]=data_bus_3_w3_reg_scanout[1];
assign data_bus_3_w7_reg_scanin[1]=data_bus_3_w6_reg_scanout[1];

assign data_bus_3_w0_reg_scanin[0]=data_bus_3_w7_reg_scanout[1];
assign data_bus_3_w1_reg_scanin[0]=data_bus_3_w0_reg_scanout[0];
assign data_bus_3_w4_reg_scanin[0]=data_bus_3_w1_reg_scanout[0];
assign data_bus_3_w5_reg_scanin[0]=data_bus_3_w4_reg_scanout[0];
assign data_bus_3_w2_reg_scanin[0]=data_bus_3_w5_reg_scanout[0];
assign data_bus_3_w3_reg_scanin[0]=data_bus_3_w2_reg_scanout[0];
assign data_bus_3_w6_reg_scanin[0]=data_bus_3_w3_reg_scanout[0];
assign data_bus_3_w7_reg_scanin[0]=data_bus_3_w6_reg_scanout[0];


// ***************************END SECTION***************************
assign wrdata_q2_6_scanin[32]=data_bus_3_w7_reg_scanout[0];
assign wrdata_q2_2_scanin[32]=wrdata_q2_6_scanout[32];
assign wrdata_q2_6_scanin[31]=wrdata_q2_2_scanout[32];
assign wrdata_q2_2_scanin[31]=wrdata_q2_6_scanout[31];
assign wrdata_q2_6_scanin[30]=wrdata_q2_2_scanout[31];
assign wrdata_q2_2_scanin[30]=wrdata_q2_6_scanout[30];
assign wrdata_q2_6_scanin[29]=wrdata_q2_2_scanout[30];
assign wrdata_q2_2_scanin[29]=wrdata_q2_6_scanout[29];
assign wrdata_q2_6_scanin[28]=wrdata_q2_2_scanout[29];
assign wrdata_q2_2_scanin[28]=wrdata_q2_6_scanout[28];
assign wrdata_q2_6_scanin[27]=wrdata_q2_2_scanout[28];
assign wrdata_q2_2_scanin[27]=wrdata_q2_6_scanout[27];
assign wrdata_q2_6_scanin[26]=wrdata_q2_2_scanout[27];
assign wrdata_q2_2_scanin[26]=wrdata_q2_6_scanout[26];
assign wrdata_q2_6_scanin[25]=wrdata_q2_2_scanout[26];
assign wrdata_q2_2_scanin[25]=wrdata_q2_6_scanout[25];
assign wrdata_q2_6_scanin[24]=wrdata_q2_2_scanout[25];
assign wrdata_q2_2_scanin[24]=wrdata_q2_6_scanout[24];
assign wrdata_q2_6_scanin[23]=wrdata_q2_2_scanout[24];
assign wrdata_q2_2_scanin[23]=wrdata_q2_6_scanout[23];
assign wrdata_q2_6_scanin[22]=wrdata_q2_2_scanout[23];
assign wrdata_q2_2_scanin[22]=wrdata_q2_6_scanout[22];
assign wrdata_q2_6_scanin[21]=wrdata_q2_2_scanout[22];
assign wrdata_q2_2_scanin[21]=wrdata_q2_6_scanout[21];
assign wrdata_q2_6_scanin[20]=wrdata_q2_2_scanout[21];
assign wrdata_q2_2_scanin[20]=wrdata_q2_6_scanout[20];
assign wrdata_q2_6_scanin[19]=wrdata_q2_2_scanout[20];
assign wrdata_q2_2_scanin[19]=wrdata_q2_6_scanout[19];
assign wrdata_q2_6_scanin[18]=wrdata_q2_2_scanout[19];
assign wrdata_q2_2_scanin[18]=wrdata_q2_6_scanout[18];
assign wrdata_q2_6_scanin[17]=wrdata_q2_2_scanout[18];
assign wrdata_q2_2_scanin[17]=wrdata_q2_6_scanout[17];
assign wrdata_q2_6_scanin[16]=wrdata_q2_2_scanout[17];
assign wrdata_q2_2_scanin[16]=wrdata_q2_6_scanout[16];
assign wrdata_q2_6_scanin[15]=wrdata_q2_2_scanout[16];
assign wrdata_q2_2_scanin[15]=wrdata_q2_6_scanout[15];
assign wrdata_q2_6_scanin[14]=wrdata_q2_2_scanout[15];
assign wrdata_q2_2_scanin[14]=wrdata_q2_6_scanout[14];
assign wrdata_q2_6_scanin[13]=wrdata_q2_2_scanout[14];
assign wrdata_q2_2_scanin[13]=wrdata_q2_6_scanout[13];
assign wrdata_q2_6_scanin[12]=wrdata_q2_2_scanout[13];
assign wrdata_q2_2_scanin[12]=wrdata_q2_6_scanout[12];
assign wrdata_q2_6_scanin[11]=wrdata_q2_2_scanout[12];
assign wrdata_q2_2_scanin[11]=wrdata_q2_6_scanout[11];
assign wrdata_q2_6_scanin[10]=wrdata_q2_2_scanout[11];
assign wrdata_q2_2_scanin[10]=wrdata_q2_6_scanout[10];
assign wrdata_q2_6_scanin[9]=wrdata_q2_2_scanout[10];
assign wrdata_q2_2_scanin[9]=wrdata_q2_6_scanout[9];
assign wrdata_q2_6_scanin[8]=wrdata_q2_2_scanout[9];
assign wrdata_q2_2_scanin[8]=wrdata_q2_6_scanout[8];
assign wrdata_q2_6_scanin[7]=wrdata_q2_2_scanout[8];
assign wrdata_q2_2_scanin[7]=wrdata_q2_6_scanout[7];
assign wrdata_q2_6_scanin[6]=wrdata_q2_2_scanout[7];
assign wrdata_q2_2_scanin[6]=wrdata_q2_6_scanout[6];
assign wrdata_q2_6_scanin[5]=wrdata_q2_2_scanout[6];
assign wrdata_q2_2_scanin[5]=wrdata_q2_6_scanout[5];
assign wrdata_q2_6_scanin[4]=wrdata_q2_2_scanout[5];
assign wrdata_q2_2_scanin[4]=wrdata_q2_6_scanout[4];
assign wrdata_q2_6_scanin[3]=wrdata_q2_2_scanout[4];
assign wrdata_q2_2_scanin[3]=wrdata_q2_6_scanout[3];
assign wrdata_q2_6_scanin[2]=wrdata_q2_2_scanout[3];
assign wrdata_q2_2_scanin[2]=wrdata_q2_6_scanout[2];
assign wrdata_q2_6_scanin[1]=wrdata_q2_2_scanout[2];
assign wrdata_q2_2_scanin[1]=wrdata_q2_6_scanout[1];
assign wrdata_q2_6_scanin[0]=wrdata_q2_2_scanout[1];
assign wrdata_q2_2_scanin[0]=wrdata_q2_6_scanout[0];

// ***************************BEGIN SECTION*************************

assign data_bus_2_w2_reg_scanin[32]=wrdata_q2_2_scanout[0];
assign data_bus_2_w3_reg_scanin[32]=data_bus_2_w2_reg_scanout[32];
assign data_bus_2_w6_reg_scanin[32]=data_bus_2_w3_reg_scanout[32];
assign data_bus_2_w7_reg_scanin[32]=data_bus_2_w6_reg_scanout[32];
assign data_bus_2_w0_reg_scanin[32]=data_bus_2_w7_reg_scanout[32];
assign data_bus_2_w1_reg_scanin[32]=data_bus_2_w0_reg_scanout[32];
assign data_bus_2_w4_reg_scanin[32]=data_bus_2_w1_reg_scanout[32];
assign data_bus_2_w5_reg_scanin[32]=data_bus_2_w4_reg_scanout[32];

assign data_bus_2_w2_reg_scanin[31]=data_bus_2_w5_reg_scanout[32];
assign data_bus_2_w3_reg_scanin[31]=data_bus_2_w2_reg_scanout[31];
assign data_bus_2_w6_reg_scanin[31]=data_bus_2_w3_reg_scanout[31];
assign data_bus_2_w7_reg_scanin[31]=data_bus_2_w6_reg_scanout[31];
assign data_bus_2_w0_reg_scanin[31]=data_bus_2_w7_reg_scanout[31];
assign data_bus_2_w1_reg_scanin[31]=data_bus_2_w0_reg_scanout[31];
assign data_bus_2_w4_reg_scanin[31]=data_bus_2_w1_reg_scanout[31];
assign data_bus_2_w5_reg_scanin[31]=data_bus_2_w4_reg_scanout[31];

assign data_bus_2_w2_reg_scanin[30]=data_bus_2_w5_reg_scanout[31];
assign data_bus_2_w3_reg_scanin[30]=data_bus_2_w2_reg_scanout[30];
assign data_bus_2_w6_reg_scanin[30]=data_bus_2_w3_reg_scanout[30];
assign data_bus_2_w7_reg_scanin[30]=data_bus_2_w6_reg_scanout[30];
assign data_bus_2_w0_reg_scanin[30]=data_bus_2_w7_reg_scanout[30];
assign data_bus_2_w1_reg_scanin[30]=data_bus_2_w0_reg_scanout[30];
assign data_bus_2_w4_reg_scanin[30]=data_bus_2_w1_reg_scanout[30];
assign data_bus_2_w5_reg_scanin[30]=data_bus_2_w4_reg_scanout[30];

assign data_bus_2_w2_reg_scanin[29]=data_bus_2_w5_reg_scanout[30];
assign data_bus_2_w3_reg_scanin[29]=data_bus_2_w2_reg_scanout[29];
assign data_bus_2_w6_reg_scanin[29]=data_bus_2_w3_reg_scanout[29];
assign data_bus_2_w7_reg_scanin[29]=data_bus_2_w6_reg_scanout[29];
assign data_bus_2_w0_reg_scanin[29]=data_bus_2_w7_reg_scanout[29];
assign data_bus_2_w1_reg_scanin[29]=data_bus_2_w0_reg_scanout[29];
assign data_bus_2_w4_reg_scanin[29]=data_bus_2_w1_reg_scanout[29];
assign data_bus_2_w5_reg_scanin[29]=data_bus_2_w4_reg_scanout[29];

assign data_bus_2_w2_reg_scanin[28]=data_bus_2_w5_reg_scanout[29];
assign data_bus_2_w3_reg_scanin[28]=data_bus_2_w2_reg_scanout[28];
assign data_bus_2_w6_reg_scanin[28]=data_bus_2_w3_reg_scanout[28];
assign data_bus_2_w7_reg_scanin[28]=data_bus_2_w6_reg_scanout[28];
assign data_bus_2_w0_reg_scanin[28]=data_bus_2_w7_reg_scanout[28];
assign data_bus_2_w1_reg_scanin[28]=data_bus_2_w0_reg_scanout[28];
assign data_bus_2_w4_reg_scanin[28]=data_bus_2_w1_reg_scanout[28];
assign data_bus_2_w5_reg_scanin[28]=data_bus_2_w4_reg_scanout[28];

assign data_bus_2_w2_reg_scanin[27]=data_bus_2_w5_reg_scanout[28];
assign data_bus_2_w3_reg_scanin[27]=data_bus_2_w2_reg_scanout[27];
assign data_bus_2_w6_reg_scanin[27]=data_bus_2_w3_reg_scanout[27];
assign data_bus_2_w7_reg_scanin[27]=data_bus_2_w6_reg_scanout[27];
assign data_bus_2_w0_reg_scanin[27]=data_bus_2_w7_reg_scanout[27];
assign data_bus_2_w1_reg_scanin[27]=data_bus_2_w0_reg_scanout[27];
assign data_bus_2_w4_reg_scanin[27]=data_bus_2_w1_reg_scanout[27];
assign data_bus_2_w5_reg_scanin[27]=data_bus_2_w4_reg_scanout[27];

assign data_bus_2_w2_reg_scanin[26]=data_bus_2_w5_reg_scanout[27];
assign data_bus_2_w3_reg_scanin[26]=data_bus_2_w2_reg_scanout[26];
assign data_bus_2_w6_reg_scanin[26]=data_bus_2_w3_reg_scanout[26];
assign data_bus_2_w7_reg_scanin[26]=data_bus_2_w6_reg_scanout[26];
assign data_bus_2_w0_reg_scanin[26]=data_bus_2_w7_reg_scanout[26];
assign data_bus_2_w1_reg_scanin[26]=data_bus_2_w0_reg_scanout[26];
assign data_bus_2_w4_reg_scanin[26]=data_bus_2_w1_reg_scanout[26];
assign data_bus_2_w5_reg_scanin[26]=data_bus_2_w4_reg_scanout[26];

assign data_bus_2_w2_reg_scanin[25]=data_bus_2_w5_reg_scanout[26];
assign data_bus_2_w3_reg_scanin[25]=data_bus_2_w2_reg_scanout[25];
assign data_bus_2_w6_reg_scanin[25]=data_bus_2_w3_reg_scanout[25];
assign data_bus_2_w7_reg_scanin[25]=data_bus_2_w6_reg_scanout[25];
assign data_bus_2_w0_reg_scanin[25]=data_bus_2_w7_reg_scanout[25];
assign data_bus_2_w1_reg_scanin[25]=data_bus_2_w0_reg_scanout[25];
assign data_bus_2_w4_reg_scanin[25]=data_bus_2_w1_reg_scanout[25];
assign data_bus_2_w5_reg_scanin[25]=data_bus_2_w4_reg_scanout[25];

assign data_bus_2_w2_reg_scanin[24]=data_bus_2_w5_reg_scanout[25];
assign data_bus_2_w3_reg_scanin[24]=data_bus_2_w2_reg_scanout[24];
assign data_bus_2_w6_reg_scanin[24]=data_bus_2_w3_reg_scanout[24];
assign data_bus_2_w7_reg_scanin[24]=data_bus_2_w6_reg_scanout[24];
assign data_bus_2_w0_reg_scanin[24]=data_bus_2_w7_reg_scanout[24];
assign data_bus_2_w1_reg_scanin[24]=data_bus_2_w0_reg_scanout[24];
assign data_bus_2_w4_reg_scanin[24]=data_bus_2_w1_reg_scanout[24];
assign data_bus_2_w5_reg_scanin[24]=data_bus_2_w4_reg_scanout[24];

assign data_bus_2_w2_reg_scanin[23]=data_bus_2_w5_reg_scanout[24];
assign data_bus_2_w3_reg_scanin[23]=data_bus_2_w2_reg_scanout[23];
assign data_bus_2_w6_reg_scanin[23]=data_bus_2_w3_reg_scanout[23];
assign data_bus_2_w7_reg_scanin[23]=data_bus_2_w6_reg_scanout[23];
assign data_bus_2_w0_reg_scanin[23]=data_bus_2_w7_reg_scanout[23];
assign data_bus_2_w1_reg_scanin[23]=data_bus_2_w0_reg_scanout[23];
assign data_bus_2_w4_reg_scanin[23]=data_bus_2_w1_reg_scanout[23];
assign data_bus_2_w5_reg_scanin[23]=data_bus_2_w4_reg_scanout[23];

assign data_bus_2_w2_reg_scanin[22]=data_bus_2_w5_reg_scanout[23];
assign data_bus_2_w3_reg_scanin[22]=data_bus_2_w2_reg_scanout[22];
assign data_bus_2_w6_reg_scanin[22]=data_bus_2_w3_reg_scanout[22];
assign data_bus_2_w7_reg_scanin[22]=data_bus_2_w6_reg_scanout[22];
assign data_bus_2_w0_reg_scanin[22]=data_bus_2_w7_reg_scanout[22];
assign data_bus_2_w1_reg_scanin[22]=data_bus_2_w0_reg_scanout[22];
assign data_bus_2_w4_reg_scanin[22]=data_bus_2_w1_reg_scanout[22];
assign data_bus_2_w5_reg_scanin[22]=data_bus_2_w4_reg_scanout[22];

assign data_bus_2_w2_reg_scanin[21]=data_bus_2_w5_reg_scanout[22];
assign data_bus_2_w3_reg_scanin[21]=data_bus_2_w2_reg_scanout[21];
assign data_bus_2_w6_reg_scanin[21]=data_bus_2_w3_reg_scanout[21];
assign data_bus_2_w7_reg_scanin[21]=data_bus_2_w6_reg_scanout[21];
assign data_bus_2_w0_reg_scanin[21]=data_bus_2_w7_reg_scanout[21];
assign data_bus_2_w1_reg_scanin[21]=data_bus_2_w0_reg_scanout[21];
assign data_bus_2_w4_reg_scanin[21]=data_bus_2_w1_reg_scanout[21];
assign data_bus_2_w5_reg_scanin[21]=data_bus_2_w4_reg_scanout[21];

assign data_bus_2_w2_reg_scanin[20]=data_bus_2_w5_reg_scanout[21];
assign data_bus_2_w3_reg_scanin[20]=data_bus_2_w2_reg_scanout[20];
assign data_bus_2_w6_reg_scanin[20]=data_bus_2_w3_reg_scanout[20];
assign data_bus_2_w7_reg_scanin[20]=data_bus_2_w6_reg_scanout[20];
assign data_bus_2_w0_reg_scanin[20]=data_bus_2_w7_reg_scanout[20];
assign data_bus_2_w1_reg_scanin[20]=data_bus_2_w0_reg_scanout[20];
assign data_bus_2_w4_reg_scanin[20]=data_bus_2_w1_reg_scanout[20];
assign data_bus_2_w5_reg_scanin[20]=data_bus_2_w4_reg_scanout[20];

assign data_bus_2_w2_reg_scanin[19]=data_bus_2_w5_reg_scanout[20];
assign data_bus_2_w3_reg_scanin[19]=data_bus_2_w2_reg_scanout[19];
assign data_bus_2_w6_reg_scanin[19]=data_bus_2_w3_reg_scanout[19];
assign data_bus_2_w7_reg_scanin[19]=data_bus_2_w6_reg_scanout[19];
assign data_bus_2_w0_reg_scanin[19]=data_bus_2_w7_reg_scanout[19];
assign data_bus_2_w1_reg_scanin[19]=data_bus_2_w0_reg_scanout[19];
assign data_bus_2_w4_reg_scanin[19]=data_bus_2_w1_reg_scanout[19];
assign data_bus_2_w5_reg_scanin[19]=data_bus_2_w4_reg_scanout[19];

assign data_bus_2_w2_reg_scanin[18]=data_bus_2_w5_reg_scanout[19];
assign data_bus_2_w3_reg_scanin[18]=data_bus_2_w2_reg_scanout[18];
assign data_bus_2_w6_reg_scanin[18]=data_bus_2_w3_reg_scanout[18];
assign data_bus_2_w7_reg_scanin[18]=data_bus_2_w6_reg_scanout[18];
assign data_bus_2_w0_reg_scanin[18]=data_bus_2_w7_reg_scanout[18];
assign data_bus_2_w1_reg_scanin[18]=data_bus_2_w0_reg_scanout[18];
assign data_bus_2_w4_reg_scanin[18]=data_bus_2_w1_reg_scanout[18];
assign data_bus_2_w5_reg_scanin[18]=data_bus_2_w4_reg_scanout[18];

assign data_bus_2_w2_reg_scanin[17]=data_bus_2_w5_reg_scanout[18];
assign data_bus_2_w3_reg_scanin[17]=data_bus_2_w2_reg_scanout[17];
assign data_bus_2_w6_reg_scanin[17]=data_bus_2_w3_reg_scanout[17];
assign data_bus_2_w7_reg_scanin[17]=data_bus_2_w6_reg_scanout[17];
assign data_bus_2_w0_reg_scanin[17]=data_bus_2_w7_reg_scanout[17];
assign data_bus_2_w1_reg_scanin[17]=data_bus_2_w0_reg_scanout[17];
assign data_bus_2_w4_reg_scanin[17]=data_bus_2_w1_reg_scanout[17];
assign data_bus_2_w5_reg_scanin[17]=data_bus_2_w4_reg_scanout[17];

assign data_bus_2_w0_reg_scanin[16]=data_bus_2_w5_reg_scanout[17];
assign data_bus_2_w1_reg_scanin[16]=data_bus_2_w0_reg_scanout[16];
assign data_bus_2_w4_reg_scanin[16]=data_bus_2_w1_reg_scanout[16];
assign data_bus_2_w5_reg_scanin[16]=data_bus_2_w4_reg_scanout[16];
assign data_bus_2_w2_reg_scanin[16]=data_bus_2_w5_reg_scanout[16];
assign data_bus_2_w3_reg_scanin[16]=data_bus_2_w2_reg_scanout[16];
assign data_bus_2_w6_reg_scanin[16]=data_bus_2_w3_reg_scanout[16];
assign data_bus_2_w7_reg_scanin[16]=data_bus_2_w6_reg_scanout[16];

assign data_bus_2_w0_reg_scanin[15]=data_bus_2_w7_reg_scanout[16];
assign data_bus_2_w1_reg_scanin[15]=data_bus_2_w0_reg_scanout[15];
assign data_bus_2_w4_reg_scanin[15]=data_bus_2_w1_reg_scanout[15];
assign data_bus_2_w5_reg_scanin[15]=data_bus_2_w4_reg_scanout[15];
assign data_bus_2_w2_reg_scanin[15]=data_bus_2_w5_reg_scanout[15];
assign data_bus_2_w3_reg_scanin[15]=data_bus_2_w2_reg_scanout[15];
assign data_bus_2_w6_reg_scanin[15]=data_bus_2_w3_reg_scanout[15];
assign data_bus_2_w7_reg_scanin[15]=data_bus_2_w6_reg_scanout[15];

assign data_bus_2_w0_reg_scanin[14]=data_bus_2_w7_reg_scanout[15];
assign data_bus_2_w1_reg_scanin[14]=data_bus_2_w0_reg_scanout[14];
assign data_bus_2_w4_reg_scanin[14]=data_bus_2_w1_reg_scanout[14];
assign data_bus_2_w5_reg_scanin[14]=data_bus_2_w4_reg_scanout[14];
assign data_bus_2_w2_reg_scanin[14]=data_bus_2_w5_reg_scanout[14];
assign data_bus_2_w3_reg_scanin[14]=data_bus_2_w2_reg_scanout[14];
assign data_bus_2_w6_reg_scanin[14]=data_bus_2_w3_reg_scanout[14];
assign data_bus_2_w7_reg_scanin[14]=data_bus_2_w6_reg_scanout[14];

assign data_bus_2_w0_reg_scanin[13]=data_bus_2_w7_reg_scanout[14];
assign data_bus_2_w1_reg_scanin[13]=data_bus_2_w0_reg_scanout[13];
assign data_bus_2_w4_reg_scanin[13]=data_bus_2_w1_reg_scanout[13];
assign data_bus_2_w5_reg_scanin[13]=data_bus_2_w4_reg_scanout[13];
assign data_bus_2_w2_reg_scanin[13]=data_bus_2_w5_reg_scanout[13];
assign data_bus_2_w3_reg_scanin[13]=data_bus_2_w2_reg_scanout[13];
assign data_bus_2_w6_reg_scanin[13]=data_bus_2_w3_reg_scanout[13];
assign data_bus_2_w7_reg_scanin[13]=data_bus_2_w6_reg_scanout[13];

assign data_bus_2_w0_reg_scanin[12]=data_bus_2_w7_reg_scanout[13];
assign data_bus_2_w1_reg_scanin[12]=data_bus_2_w0_reg_scanout[12];
assign data_bus_2_w4_reg_scanin[12]=data_bus_2_w1_reg_scanout[12];
assign data_bus_2_w5_reg_scanin[12]=data_bus_2_w4_reg_scanout[12];
assign data_bus_2_w2_reg_scanin[12]=data_bus_2_w5_reg_scanout[12];
assign data_bus_2_w3_reg_scanin[12]=data_bus_2_w2_reg_scanout[12];
assign data_bus_2_w6_reg_scanin[12]=data_bus_2_w3_reg_scanout[12];
assign data_bus_2_w7_reg_scanin[12]=data_bus_2_w6_reg_scanout[12];

assign data_bus_2_w0_reg_scanin[11]=data_bus_2_w7_reg_scanout[12];
assign data_bus_2_w1_reg_scanin[11]=data_bus_2_w0_reg_scanout[11];
assign data_bus_2_w4_reg_scanin[11]=data_bus_2_w1_reg_scanout[11];
assign data_bus_2_w5_reg_scanin[11]=data_bus_2_w4_reg_scanout[11];
assign data_bus_2_w2_reg_scanin[11]=data_bus_2_w5_reg_scanout[11];
assign data_bus_2_w3_reg_scanin[11]=data_bus_2_w2_reg_scanout[11];
assign data_bus_2_w6_reg_scanin[11]=data_bus_2_w3_reg_scanout[11];
assign data_bus_2_w7_reg_scanin[11]=data_bus_2_w6_reg_scanout[11];

assign data_bus_2_w0_reg_scanin[10]=data_bus_2_w7_reg_scanout[11];
assign data_bus_2_w1_reg_scanin[10]=data_bus_2_w0_reg_scanout[10];
assign data_bus_2_w4_reg_scanin[10]=data_bus_2_w1_reg_scanout[10];
assign data_bus_2_w5_reg_scanin[10]=data_bus_2_w4_reg_scanout[10];
assign data_bus_2_w2_reg_scanin[10]=data_bus_2_w5_reg_scanout[10];
assign data_bus_2_w3_reg_scanin[10]=data_bus_2_w2_reg_scanout[10];
assign data_bus_2_w6_reg_scanin[10]=data_bus_2_w3_reg_scanout[10];
assign data_bus_2_w7_reg_scanin[10]=data_bus_2_w6_reg_scanout[10];

assign data_bus_2_w0_reg_scanin[9]=data_bus_2_w7_reg_scanout[10];
assign data_bus_2_w1_reg_scanin[9]=data_bus_2_w0_reg_scanout[9];
assign data_bus_2_w4_reg_scanin[9]=data_bus_2_w1_reg_scanout[9];
assign data_bus_2_w5_reg_scanin[9]=data_bus_2_w4_reg_scanout[9];
assign data_bus_2_w2_reg_scanin[9]=data_bus_2_w5_reg_scanout[9];
assign data_bus_2_w3_reg_scanin[9]=data_bus_2_w2_reg_scanout[9];
assign data_bus_2_w6_reg_scanin[9]=data_bus_2_w3_reg_scanout[9];
assign data_bus_2_w7_reg_scanin[9]=data_bus_2_w6_reg_scanout[9];

assign data_bus_2_w0_reg_scanin[8]=data_bus_2_w7_reg_scanout[9];
assign data_bus_2_w1_reg_scanin[8]=data_bus_2_w0_reg_scanout[8];
assign data_bus_2_w4_reg_scanin[8]=data_bus_2_w1_reg_scanout[8];
assign data_bus_2_w5_reg_scanin[8]=data_bus_2_w4_reg_scanout[8];
assign data_bus_2_w2_reg_scanin[8]=data_bus_2_w5_reg_scanout[8];
assign data_bus_2_w3_reg_scanin[8]=data_bus_2_w2_reg_scanout[8];
assign data_bus_2_w6_reg_scanin[8]=data_bus_2_w3_reg_scanout[8];
assign data_bus_2_w7_reg_scanin[8]=data_bus_2_w6_reg_scanout[8];

assign data_bus_2_w0_reg_scanin[7]=data_bus_2_w7_reg_scanout[8];
assign data_bus_2_w1_reg_scanin[7]=data_bus_2_w0_reg_scanout[7];
assign data_bus_2_w4_reg_scanin[7]=data_bus_2_w1_reg_scanout[7];
assign data_bus_2_w5_reg_scanin[7]=data_bus_2_w4_reg_scanout[7];
assign data_bus_2_w2_reg_scanin[7]=data_bus_2_w5_reg_scanout[7];
assign data_bus_2_w3_reg_scanin[7]=data_bus_2_w2_reg_scanout[7];
assign data_bus_2_w6_reg_scanin[7]=data_bus_2_w3_reg_scanout[7];
assign data_bus_2_w7_reg_scanin[7]=data_bus_2_w6_reg_scanout[7];

assign data_bus_2_w0_reg_scanin[6]=data_bus_2_w7_reg_scanout[7];
assign data_bus_2_w1_reg_scanin[6]=data_bus_2_w0_reg_scanout[6];
assign data_bus_2_w4_reg_scanin[6]=data_bus_2_w1_reg_scanout[6];
assign data_bus_2_w5_reg_scanin[6]=data_bus_2_w4_reg_scanout[6];
assign data_bus_2_w2_reg_scanin[6]=data_bus_2_w5_reg_scanout[6];
assign data_bus_2_w3_reg_scanin[6]=data_bus_2_w2_reg_scanout[6];
assign data_bus_2_w6_reg_scanin[6]=data_bus_2_w3_reg_scanout[6];
assign data_bus_2_w7_reg_scanin[6]=data_bus_2_w6_reg_scanout[6];

assign data_bus_2_w0_reg_scanin[5]=data_bus_2_w7_reg_scanout[6];
assign data_bus_2_w1_reg_scanin[5]=data_bus_2_w0_reg_scanout[5];
assign data_bus_2_w4_reg_scanin[5]=data_bus_2_w1_reg_scanout[5];
assign data_bus_2_w5_reg_scanin[5]=data_bus_2_w4_reg_scanout[5];
assign data_bus_2_w2_reg_scanin[5]=data_bus_2_w5_reg_scanout[5];
assign data_bus_2_w3_reg_scanin[5]=data_bus_2_w2_reg_scanout[5];
assign data_bus_2_w6_reg_scanin[5]=data_bus_2_w3_reg_scanout[5];
assign data_bus_2_w7_reg_scanin[5]=data_bus_2_w6_reg_scanout[5];

assign data_bus_2_w0_reg_scanin[4]=data_bus_2_w7_reg_scanout[5];
assign data_bus_2_w1_reg_scanin[4]=data_bus_2_w0_reg_scanout[4];
assign data_bus_2_w4_reg_scanin[4]=data_bus_2_w1_reg_scanout[4];
assign data_bus_2_w5_reg_scanin[4]=data_bus_2_w4_reg_scanout[4];
assign data_bus_2_w2_reg_scanin[4]=data_bus_2_w5_reg_scanout[4];
assign data_bus_2_w3_reg_scanin[4]=data_bus_2_w2_reg_scanout[4];
assign data_bus_2_w6_reg_scanin[4]=data_bus_2_w3_reg_scanout[4];
assign data_bus_2_w7_reg_scanin[4]=data_bus_2_w6_reg_scanout[4];

assign data_bus_2_w0_reg_scanin[3]=data_bus_2_w7_reg_scanout[4];
assign data_bus_2_w1_reg_scanin[3]=data_bus_2_w0_reg_scanout[3];
assign data_bus_2_w4_reg_scanin[3]=data_bus_2_w1_reg_scanout[3];
assign data_bus_2_w5_reg_scanin[3]=data_bus_2_w4_reg_scanout[3];
assign data_bus_2_w2_reg_scanin[3]=data_bus_2_w5_reg_scanout[3];
assign data_bus_2_w3_reg_scanin[3]=data_bus_2_w2_reg_scanout[3];
assign data_bus_2_w6_reg_scanin[3]=data_bus_2_w3_reg_scanout[3];
assign data_bus_2_w7_reg_scanin[3]=data_bus_2_w6_reg_scanout[3];

assign data_bus_2_w0_reg_scanin[2]=data_bus_2_w7_reg_scanout[3];
assign data_bus_2_w1_reg_scanin[2]=data_bus_2_w0_reg_scanout[2];
assign data_bus_2_w4_reg_scanin[2]=data_bus_2_w1_reg_scanout[2];
assign data_bus_2_w5_reg_scanin[2]=data_bus_2_w4_reg_scanout[2];
assign data_bus_2_w2_reg_scanin[2]=data_bus_2_w5_reg_scanout[2];
assign data_bus_2_w3_reg_scanin[2]=data_bus_2_w2_reg_scanout[2];
assign data_bus_2_w6_reg_scanin[2]=data_bus_2_w3_reg_scanout[2];
assign data_bus_2_w7_reg_scanin[2]=data_bus_2_w6_reg_scanout[2];

assign data_bus_2_w0_reg_scanin[1]=data_bus_2_w7_reg_scanout[2];
assign data_bus_2_w1_reg_scanin[1]=data_bus_2_w0_reg_scanout[1];
assign data_bus_2_w4_reg_scanin[1]=data_bus_2_w1_reg_scanout[1];
assign data_bus_2_w5_reg_scanin[1]=data_bus_2_w4_reg_scanout[1];
assign data_bus_2_w2_reg_scanin[1]=data_bus_2_w5_reg_scanout[1];
assign data_bus_2_w3_reg_scanin[1]=data_bus_2_w2_reg_scanout[1];
assign data_bus_2_w6_reg_scanin[1]=data_bus_2_w3_reg_scanout[1];
assign data_bus_2_w7_reg_scanin[1]=data_bus_2_w6_reg_scanout[1];

assign data_bus_2_w0_reg_scanin[0]=data_bus_2_w7_reg_scanout[1];
assign data_bus_2_w1_reg_scanin[0]=data_bus_2_w0_reg_scanout[0];
assign data_bus_2_w4_reg_scanin[0]=data_bus_2_w1_reg_scanout[0];
assign data_bus_2_w5_reg_scanin[0]=data_bus_2_w4_reg_scanout[0];
assign data_bus_2_w2_reg_scanin[0]=data_bus_2_w5_reg_scanout[0];
assign data_bus_2_w3_reg_scanin[0]=data_bus_2_w2_reg_scanout[0];
assign data_bus_2_w6_reg_scanin[0]=data_bus_2_w3_reg_scanout[0];
assign data_bus_2_w7_reg_scanin[0]=data_bus_2_w6_reg_scanout[0];

assign scan_out			  =data_bus_2_w7_reg_scanout[0];

// ***************************END SECTION***************************


`ifndef FPGA
// synopsys translate_on
`endif

endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//
//   invert macro
//
//


module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_9 (
  din, 
  dout);
  input [8:0] din;
  output [8:0] dout;


inv #(9)  d0_0 (
.in(din[8:0]),
.out(dout[8:0])
);


endmodule


//
//   invert macro
//
//


module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


//
//   invert macro
//
//


module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module n2_icd_sp_16p5kb_cust_inv_macro__stack_50c__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
input [0:0] d;
  input scan_in;
input l1clk;
input siclk;
input soclk;
  output scan_out;
output [0:0] latout;
output [0:0] latout_l;


tisram_msff #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[0:0]),
.latout_l(latout_l[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_icd_sp_16p5kb_cust_tisram_msff_macro__width_9 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
wire [7:0] so;

input [8:0] d;
  input scan_in;
input l1clk;
input siclk;
input soclk;
  output scan_out;
output [8:0] latout;
output [8:0] latout_l;


tisram_msff #(9)  d0_0 (
.d(d[8:0]),
.si({scan_in,so[7:0]}),
.so({so[7:0],scan_out}),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[8:0]),
.latout_l(latout_l[8:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msffi_ctl_macro__fs_1__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  q_l, 
  scan_out);
  input [3:0] din;
  input l1clk;
  input [3:0] scan_in;


  input siclk;
  input soclk;

  output [3:0] q_l;
  output [3:0] scan_out;


msffi #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(din[3:0]),
.si(scan_in[3:0]),
.so(scan_out[3:0]),
.q_l(q_l[3:0])
);


endmodule


//
//   invert macro
//
//


module n2_icd_sp_16p5kb_cust_inv_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msffi_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  q_l, 
  scan_out);
  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] q_l;
  output scan_out;


msffi #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(din[0:0]),
.si(scan_in),
.so(scan_out),
.q_l(q_l[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input [0:0] scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output [0:0] scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in[0:0]),
.so(scan_out[0:0]),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__stack_66c__width_66 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [65:0] din0;
  input [65:0] din1;
  input sel0;
  output [65:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(66)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[65:0]),
  .in1(din1[65:0]),
.dout(dout[65:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_33 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [32:0] fdin;

  input [32:0] din;
  input l1clk;
  input [32:0] scan_in;


  input siclk;
  input soclk;

  output [32:0] dout;
  output [32:0] scan_out;
assign fdin[32:0] = din[32:0];


dff #(33)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[32:0]),
.si(scan_in[32:0]),
.so(scan_out[32:0]),
.q(dout[32:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_5 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [4:0] fdin;

  input [4:0] din;
  input l1clk;
  input [4:0] scan_in;


  input siclk;
  input soclk;

  output [4:0] dout;
  output [4:0] scan_out;
assign fdin[4:0] = din[4:0];


dff #(5)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[4:0]),
.si(scan_in[4:0]),
.so(scan_out[4:0]),
.q(dout[4:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;

  input [1:0] din;
  input l1clk;
  input [1:0] scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output [1:0] scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si(scan_in[1:0]),
.so(scan_out[1:0]),
.q(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;

  input [3:0] din;
  input l1clk;
  input [3:0] scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output [3:0] scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si(scan_in[3:0]),
.so(scan_out[3:0]),
.q(dout[3:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_icd_sp_16p5kb_cust_and_macro__ports_2__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_msff_ctl_macro__fs_1__width_8 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [7:0] fdin;

  input [7:0] din;
  input l1clk;
  input [7:0] scan_in;


  input siclk;
  input soclk;

  output [7:0] dout;
  output [7:0] scan_out;
assign fdin[7:0] = din[7:0];


dff #(8)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[7:0]),
.si(scan_in[7:0]),
.so(scan_out[7:0]),
.q(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module n2_icd_sp_16p5kb_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_2__stack_50c__width_8 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [7:0] din0;
  input sel0;
  input [7:0] din1;
  input sel1;
  output [7:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(8)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
.dout(dout[7:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module n2_icd_sp_16p5kb_cust_or_macro__ports_3__stack_50c__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


or3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module n2_icd_sp_16p5kb_cust_or_macro__ports_2__stack_50c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_icd_sp_16p5kb_cust_and_macro__ports_2__stack_50c__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


//
//   buff macro
//
//


module n2_icd_sp_16p5kb_cust_buff_macro__stack_50c__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


buff #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module n2_icd_sp_16p5kb_cust_nand_macro__ports_3__stack_50c__width_8 (
  din0, 
  din1, 
  din2, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  output [7:0] dout;


nand3 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.in2(din2[7:0]),
.out(dout[7:0])
);


endmodule


//
//   nand macro for ports = 2,3,4
//
//


module n2_icd_sp_16p5kb_cust_nand_macro__ports_4__stack_50c__width_1 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  input [0:0] din3;
  output [0:0] dout;


nand4 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.in3(din3[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module n2_icd_sp_16p5kb_cust_inv_macro (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_icd_sp_16p5kb_cust_and_macro (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_8 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  input [7:0] din3;
  input [7:0] din4;
  input [7:0] din5;
  input [7:0] din6;
  input [7:0] din7;
  input [2:0] sel;
  output [7:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
  .in4(din4[7:0]),
  .in5(din5[7:0]),
  .in6(din6[7:0]),
  .in7(din7[7:0]),
.dout(dout[7:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__width_16 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [15:0] din0;
  input [15:0] din1;
  input sel0;
  output [15:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(16)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[15:0]),
  .in1(din1[15:0]),
.dout(dout[15:0])
);


endmodule


module n2_icd_quad_array (
  adr_ac_h, 
  adr_ac_l, 
  rd_en_a_l, 
  quaden_f_l, 
  wr_word_en_ac_l, 
  wr_waysel0_ac_l, 
  wr_waysel1_ac_l, 
  din0_a, 
  din1_a, 
  red_d_ff, 
  red_en_ff, 
  rid_sel, 
  red_arst_ff, 
  red_wen_ff, 
  rd_worden_ac_l, 
  l1clk, 
  l1clk_fuse,
  vnw_ary,
  dout_wy0_bc, 
  dout_wy1_bc, 
  dout_wy2_bc, 
  dout_wy3_bc, 
  dout_wy4_bc, 
  dout_wy5_bc, 
  dout_wy6_bc, 
  dout_wy7_bc, 
  reg_d_lft_top, 
  reg_en_lft_top, 
  reg_d_rgt_top, 
  reg_en_rgt_top, 
  reg_d_lft_bot, 
  reg_en_lft_bot, 
  reg_d_rgt_bot, 
  reg_en_rgt_bot) ;
wire [3:0] red_write;
wire [4:0] reg_d_lft_top_in;
wire [1:0] reg_en_lft_top_in;
wire [4:0] reg_d_rgt_top_in;
wire [1:0] reg_en_rgt_top_in;
wire [4:0] reg_d_lft_bot_in;
wire [1:0] reg_en_lft_bot_in;
wire [4:0] reg_d_rgt_bot_in;
wire [1:0] reg_en_rgt_bot_in;


input  [10:5] adr_ac_h;
input  [10:5] adr_ac_l;
input         rd_en_a_l;
input         quaden_f_l;
input  [1:0]  wr_word_en_ac_l;
input  [7:0]  wr_waysel0_ac_l;
input  [7:0]  wr_waysel1_ac_l;
input  [32:0] din0_a;
input  [32:0] din1_a;
input  [4:0]  red_d_ff;
input  [1:0]  red_en_ff;
input  [3:0]  rid_sel;
input         red_arst_ff;
input         red_wen_ff;
input  [1:0]  rd_worden_ac_l;
input         l1clk;
input         l1clk_fuse;
input         vnw_ary;

output [32:0] dout_wy0_bc;
output [32:0] dout_wy1_bc;
output [32:0] dout_wy2_bc;
output [32:0] dout_wy3_bc;
output [32:0] dout_wy4_bc;
output [32:0] dout_wy5_bc;
output [32:0] dout_wy6_bc;
output [32:0] dout_wy7_bc;

output [4:0]  reg_d_lft_top ;
output [1:0]  reg_en_lft_top ;
output [4:0]  reg_d_rgt_top ;
output [1:0]  reg_en_rgt_top ;
output [4:0]  reg_d_lft_bot ;
output [1:0]  reg_en_lft_bot ;
output [4:0]  reg_d_rgt_bot ;
output [1:0]  reg_en_rgt_bot ;

reg [4:0]     reg_d_lft_top ;
reg [1:0]     reg_en_lft_top ;
reg [4:0]     reg_d_rgt_top ;
reg [1:0]     reg_en_rgt_top ;
reg [4:0]     reg_d_lft_bot ;
reg [1:0]     reg_en_lft_bot ;
reg [4:0]     reg_d_rgt_bot ;
reg [1:0]     reg_en_rgt_bot ;

//////////////////////////////////////////
// top    bank                          //
//////////////////////////////////////////
n2_icd_bank              w3_to_w0_bank(.adr_ac_h(adr_ac_h[10:5]),
                                       .adr_ac_l(adr_ac_l[10:5]),
                                       .rd_en_a_l(rd_en_a_l),
                                       .quaden_f_l(quaden_f_l),
                                       .wr_word_en_ac_l(wr_word_en_ac_l[1:0]),
                                       .wr_waysel0_ac_l(wr_waysel0_ac_l[3:0]),
                                       .wr_waysel1_ac_l(wr_waysel1_ac_l[3:0]),
                                       .din0_a(din0_a[32:0]),
                                       .din1_a(din1_a[32:0]),
                                       .dout_wy0_bc(dout_wy0_bc[32:0]),
                                       .dout_wy1_bc(dout_wy1_bc[32:0]),
                                       .dout_wy2_bc(dout_wy2_bc[32:0]),
                                       .dout_wy3_bc(dout_wy3_bc[32:0]),
                                       .reg_d_lft(reg_d_lft_top[4:0]),
                                       .reg_en_lft(reg_en_lft_top[1:0]),
                                       .reg_d_rgt(reg_d_rgt_top[4:0]),
                                       .reg_en_rgt(reg_en_rgt_top[1:0]),
                                       .rd_worden_ac_l(rd_worden_ac_l[1:0]),
                                       .l1clk(l1clk),
  .vnw_ary(vnw_ary)
                                       );


//////////////////////////////////////////
// bottom bank                          //
//////////////////////////////////////////
n2_icd_bank              w7_to_w4_bank(.adr_ac_h(adr_ac_h[10:5]),
                                       .adr_ac_l(adr_ac_l[10:5]),
                                       .rd_en_a_l(rd_en_a_l),
                                       .quaden_f_l(quaden_f_l),
                                       .wr_word_en_ac_l(wr_word_en_ac_l[1:0]),
                                       .wr_waysel0_ac_l(wr_waysel0_ac_l[7:4]),
                                       .wr_waysel1_ac_l(wr_waysel1_ac_l[7:4]),
                                       .din0_a(din0_a[32:0]),
                                       .din1_a(din1_a[32:0]),
                                       .dout_wy0_bc(dout_wy4_bc[32:0]),
                                       .dout_wy1_bc(dout_wy5_bc[32:0]),
                                       .dout_wy2_bc(dout_wy6_bc[32:0]),
                                       .dout_wy3_bc(dout_wy7_bc[32:0]),
                                       .reg_d_lft(reg_d_lft_bot[4:0]),
                                       .reg_en_lft(reg_en_lft_bot[1:0]),
                                       .reg_d_rgt(reg_d_rgt_bot[4:0]),
                                       .reg_en_rgt(reg_en_rgt_bot[1:0]),
                                       .rd_worden_ac_l(rd_worden_ac_l[1:0]),
                                       .l1clk(l1clk),
  .vnw_ary(vnw_ary)
                                       );


assign red_write[3:0] = ({4{red_wen_ff}} & rid_sel[3:0]) ;
assign reg_d_lft_top_in[4:0]  = (red_arst_ff) ? 5'b00000 : 
                                (red_write[2]) ? red_d_ff[4:0]  : reg_d_lft_top[4:0] ;
assign reg_en_lft_top_in[1:0] = (red_arst_ff) ? 2'b00    : 
                                (red_write[2]) ? red_en_ff[1:0] : reg_en_lft_top[1:0];

assign reg_d_rgt_top_in[4:0]  = (red_arst_ff) ? 5'b00000 : 
                                (red_write[3]) ? red_d_ff[4:0]  : reg_d_rgt_top[4:0] ;
assign reg_en_rgt_top_in[1:0] = (red_arst_ff) ? 2'b00    : 
                                (red_write[3]) ? red_en_ff[1:0] : reg_en_rgt_top[1:0];

assign reg_d_lft_bot_in[4:0]  = (red_arst_ff) ? 5'b00000 : 
                                (red_write[0]) ? red_d_ff[4:0]  : reg_d_lft_bot[4:0] ;
assign reg_en_lft_bot_in[1:0] = (red_arst_ff) ? 2'b00    : 
                                (red_write[0]) ? red_en_ff[1:0] : reg_en_lft_bot[1:0];

assign reg_d_rgt_bot_in[4:0]  = (red_arst_ff) ? 5'b00000 : 
                                (red_write[1]) ? red_d_ff[4:0]  : reg_d_rgt_bot[4:0] ;
assign reg_en_rgt_bot_in[1:0] = (red_arst_ff) ? 2'b00    : 
                                (red_write[1]) ? red_en_ff[1:0] : reg_en_rgt_bot[1:0];


//always @(posedge l1clk) begin
always @(l1clk_fuse or red_arst_ff or red_wen_ff) begin

  // this is a b-latch so need to update when red_wen_ff or red_arst_ff changes
  // red_wen_ff or red_arst_ff can change in b-phase b/c of wr_inhibit signal
  if (~l1clk_fuse) begin
   reg_d_lft_top[4:0]  <= reg_d_lft_top_in[4:0] ;
   reg_en_lft_top[1:0] <= reg_en_lft_top_in[1:0] ;
   reg_d_rgt_top[4:0]  <= reg_d_rgt_top_in[4:0] ;
   reg_en_rgt_top[1:0] <= reg_en_rgt_top_in[1:0] ;
   reg_d_lft_bot[4:0]  <= reg_d_lft_bot_in[4:0] ;
   reg_en_lft_bot[1:0] <= reg_en_lft_bot_in[1:0] ;
   reg_d_rgt_bot[4:0]  <= reg_d_rgt_bot_in[4:0] ;
   reg_en_rgt_bot[1:0] <= reg_en_rgt_bot_in[1:0] ;
  end

end


endmodule


module n2_icd_bank (
  adr_ac_h, 
  adr_ac_l, 
  rd_en_a_l, 
  quaden_f_l, 
  wr_word_en_ac_l, 
  wr_waysel0_ac_l, 
  wr_waysel1_ac_l, 
  din0_a, 
  din1_a, 
  rd_worden_ac_l, 
  l1clk, 
  vnw_ary,
  reg_d_lft, 
  reg_d_rgt, 
  reg_en_lft, 
  reg_en_rgt, 
  dout_wy0_bc, 
  dout_wy1_bc, 
  dout_wy2_bc, 
  dout_wy3_bc);
wire [16:0] din0_a_rev;
wire [16:0] din1_a_rev;
wire [16:0] dout_wy0_bc_rev;
wire [16:0] dout_wy1_bc_rev;
wire [16:0] dout_wy2_bc_rev;
wire [16:0] dout_wy3_bc_rev;


input [5:0] 	adr_ac_h ;
input [5:0] 	adr_ac_l ;
input       	rd_en_a_l ;
input       	quaden_f_l ;
input [1:0] 	wr_word_en_ac_l ;
input [3:0] 	wr_waysel0_ac_l ;
input [3:0] 	wr_waysel1_ac_l ;
input [32:0] 	din0_a ;
input [32:0] 	din1_a ;
input [1:0]  	rd_worden_ac_l ;
input        	l1clk ;

input		vnw_ary;

input [4:0]     reg_d_lft;
input [4:0]     reg_d_rgt;
input [1:0]     reg_en_lft;
input [1:0]     reg_en_rgt;

output [32:0] 	dout_wy0_bc ;
output [32:0] 	dout_wy1_bc ;
output [32:0] 	dout_wy2_bc ;
output [32:0] 	dout_wy3_bc ;


assign din0_a_rev[16:0] = {din0_a[0],din0_a[1],din0_a[2],din0_a[3],din0_a[4],din0_a[5],din0_a[6],din0_a[7],din0_a[8],
                           din0_a[9],din0_a[10],din0_a[11],din0_a[12],din0_a[13],din0_a[14],din0_a[15],din0_a[16]};
assign din1_a_rev[16:0] = {din1_a[0],din1_a[1],din1_a[2],din1_a[3],din1_a[4],din1_a[5],din1_a[6],din1_a[7],din1_a[8],
                           din1_a[9],din1_a[10],din1_a[11],din1_a[12],din1_a[13],din1_a[14],din1_a[15],din1_a[16]};

n2_icd_lft_sb_array   left_sb_array (

	.adr_ac_h (adr_ac_h[5:0]),
	.adr_ac_l (adr_ac_l[5:0]),
	.rd_en_a_l (rd_en_a_l),
	.quaden_f_l (quaden_f_l),
	.wr_word_en_ac_l (wr_word_en_ac_l[1:0]) ,
	.wr_waysel0_ac_l (wr_waysel0_ac_l[3:0]),
	.wr_waysel1_ac_l (wr_waysel1_ac_l[3:0]),
	.din0_a (din0_a_rev[16:0]),
	.din1_a (din1_a_rev[16:0]),
	.rd_worden_ac_l (rd_worden_ac_l[1:0]),
	.l1clk (l1clk),

	.reg_d_lft (reg_d_lft[4:0]),
	.reg_en_lft (reg_en_lft[1:0]),

	.dout_wy0_bc (dout_wy0_bc_rev[16:0]),
	.dout_wy1_bc (dout_wy1_bc_rev[16:0]),
	.dout_wy2_bc (dout_wy2_bc_rev[16:0]),
	.dout_wy3_bc (dout_wy3_bc_rev[16:0]),
  .vnw_ary(vnw_ary) ) ; 

assign dout_wy0_bc[16:0] = {dout_wy0_bc_rev[0],dout_wy0_bc_rev[1],dout_wy0_bc_rev[2],dout_wy0_bc_rev[3],
                            dout_wy0_bc_rev[4], dout_wy0_bc_rev[5],dout_wy0_bc_rev[6],dout_wy0_bc_rev[7],
                            dout_wy0_bc_rev[8],dout_wy0_bc_rev[9], dout_wy0_bc_rev[10],dout_wy0_bc_rev[11],
                            dout_wy0_bc_rev[12],dout_wy0_bc_rev[13],dout_wy0_bc_rev[14], dout_wy0_bc_rev[15],dout_wy0_bc_rev[16]};

assign dout_wy1_bc[16:0] = {dout_wy1_bc_rev[0],dout_wy1_bc_rev[1],dout_wy1_bc_rev[2],dout_wy1_bc_rev[3],
                            dout_wy1_bc_rev[4],dout_wy1_bc_rev[5],dout_wy1_bc_rev[6],dout_wy1_bc_rev[7],
                            dout_wy1_bc_rev[8],dout_wy1_bc_rev[9],dout_wy1_bc_rev[10],dout_wy1_bc_rev[11],
                            dout_wy1_bc_rev[12],dout_wy1_bc_rev[13],dout_wy1_bc_rev[14],dout_wy1_bc_rev[15],dout_wy1_bc_rev[16]};

assign dout_wy2_bc[16:0] = {dout_wy2_bc_rev[0],dout_wy2_bc_rev[1],dout_wy2_bc_rev[2],dout_wy2_bc_rev[3],
                            dout_wy2_bc_rev[4],dout_wy2_bc_rev[5],dout_wy2_bc_rev[6],dout_wy2_bc_rev[7],
                            dout_wy2_bc_rev[8],dout_wy2_bc_rev[9],dout_wy2_bc_rev[10],dout_wy2_bc_rev[11],
                            dout_wy2_bc_rev[12],dout_wy2_bc_rev[13],dout_wy2_bc_rev[14],dout_wy2_bc_rev[15],dout_wy2_bc_rev[16]};

assign dout_wy3_bc[16:0] = {dout_wy3_bc_rev[0],dout_wy3_bc_rev[1],dout_wy3_bc_rev[2],dout_wy3_bc_rev[3],
                            dout_wy3_bc_rev[4],dout_wy3_bc_rev[5],dout_wy3_bc_rev[6],dout_wy3_bc_rev[7],
                            dout_wy3_bc_rev[8],dout_wy3_bc_rev[9],dout_wy3_bc_rev[10],dout_wy3_bc_rev[11],
                            dout_wy3_bc_rev[12],dout_wy3_bc_rev[13],dout_wy3_bc_rev[14],dout_wy3_bc_rev[15],dout_wy3_bc_rev[16]};

n2_icd_rgt_sb_array   right_sb_array (

	.adr_ac_h (adr_ac_h[5:0]),
	.adr_ac_l (adr_ac_l[5:0]),
	.rd_en_a_l (rd_en_a_l),
	.quaden_f_l (quaden_f_l),
	.wr_word_en_ac_l (wr_word_en_ac_l[1:0]) ,
	.wr_waysel0_ac_l (wr_waysel0_ac_l[3:0]),
	.wr_waysel1_ac_l (wr_waysel1_ac_l[3:0]),
	.din0_a (din0_a[32:17]),
	.din1_a (din1_a[32:17]),
	.rd_worden_ac_l (rd_worden_ac_l[1:0]),
	.l1clk (l1clk),

	.reg_d_rgt (reg_d_rgt[4:0]),
	.reg_en_rgt (reg_en_rgt[1:0]),

	.dout_wy0_bc (dout_wy0_bc[32:17]),
	.dout_wy1_bc (dout_wy1_bc[32:17]),
	.dout_wy2_bc (dout_wy2_bc[32:17]),
	.dout_wy3_bc (dout_wy3_bc[32:17]),
  .vnw_ary(vnw_ary) ) ; 


supply0 vss;
supply1 vdd;
endmodule


`ifndef FPGA

module n2_icd_lft_sb_array (
  adr_ac_h, 
  adr_ac_l, 
  rd_en_a_l, 
  quaden_f_l, 
  wr_word_en_ac_l, 
  wr_waysel0_ac_l, 
  wr_waysel1_ac_l, 
  din0_a, 
  din1_a, 
  rd_worden_ac_l, 
  l1clk, 
  reg_d_lft, 
  reg_en_lft, 
  vnw_ary, 
  dout_wy0_bc, 
  dout_wy1_bc, 
  dout_wy2_bc, 
  dout_wy3_bc);
wire [135:0] word_write_en;
wire [135:0] way_write_en;
wire [135:0] data_in;
wire rd_worden_ac_l_unused;
wire [5:0] adr_ac_l_unused;


input [5:0] 	adr_ac_h ;
input [5:0] 	adr_ac_l ;
input       	rd_en_a_l ;
input       	quaden_f_l ;
input [1:0] 	wr_word_en_ac_l ;
input [3:0] 	wr_waysel0_ac_l ;
input [3:0] 	wr_waysel1_ac_l ;
input [16:0] 	din0_a ;
input [16:0] 	din1_a ;
input [1:0]  	rd_worden_ac_l ;
input        	l1clk ;

input [4:0]     reg_d_lft;
input [1:0]     reg_en_lft;

input		vnw_ary;

output [16:0] 	dout_wy0_bc ;
output [16:0] 	dout_wy1_bc ;
output [16:0] 	dout_wy2_bc ;
output [16:0] 	dout_wy3_bc ;


reg     [143:0]   mem[63:0] ;


reg     [143:0]      local_dout;
reg     [135:0]      old_data;
reg     [143:0]      wr_data;
reg     [135:0]      dout;
wire    [143:0]      temp;
wire    [135:0]      din;

 reg    [16:0]  dout_wy0_bc ;
 reg    [16:0]  dout_wy1_bc ;
 reg    [16:0]  dout_wy2_bc ;
 reg    [16:0]  dout_wy3_bc ;

 reg    [16:0]  way3_word0 ;
 reg    [16:0]  way3_word1 ;
 reg    [16:0]  way2_word0 ;
 reg    [16:0]  way2_word1 ;
 reg    [16:0]  way1_word0 ;
 reg    [16:0]  way1_word1 ;
 reg    [16:0]  way0_word0 ;
 reg    [16:0]  way0_word1 ;
 reg    [31:0] 	n_reg1;
 reg    [31:0] 	n_reg2;
 reg    [31:0] 	n_reg3;
 reg            word_0_read;
integer n;

`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
  for (i=0; i<64; i=i+1) begin
   mem [i] = {144{1'b0}};
  end
  local_dout = {144{1'b0}};
end
`endif


// assign word_0_read    = ~rd_worden_ac_l[0] & ~rd_en_a_l ;
// assign red_value[4:0] = reg_d_lft[4:0] & {5{reg_en_lft[1] & reg_en_lft[0]}};
assign temp[143:0] = mem[adr_ac_h[5:0]] ;

////////////////////////////////
// Redunduncy Read shifter
////////////////////////////////
always @(reg_en_lft[1:0]  or reg_d_lft  or temp ) begin
	for (n = 0;  n < 136; n = n + 1 ) begin
		n_reg1 = n;
		if (reg_en_lft[1] & reg_en_lft[0] & ( reg_d_lft >= 5'b00000) & (reg_d_lft <= 5'b10000)) begin
     			if ( n_reg1[9:0] >= ((reg_d_lft + 5'h1) * 5'b01000))
				old_data[n] = temp[n+8] ;
		        else
				old_data[n] = temp[n] ;
		end else
			old_data[n] = temp[n+8] ;
	end 
end 

assign word_write_en[135:0] =  {68{~wr_word_en_ac_l[0], ~wr_word_en_ac_l[1]}} ;   
assign way_write_en[135:0]  =  {17{~wr_waysel0_ac_l[3] , ~wr_waysel1_ac_l[3] ,~wr_waysel0_ac_l[2] , ~wr_waysel1_ac_l[2],
                                   ~wr_waysel0_ac_l[1] , ~wr_waysel1_ac_l[1] ,~wr_waysel0_ac_l[0] , ~wr_waysel1_ac_l[0] }} ;

assign data_in[135:0] = {din0_a[16],din1_a[16] , din0_a[16],din1_a[16] ,  din0_a[16],din1_a[16] , din0_a[16],din1_a[16], // 135:128 
                         din0_a[15],din1_a[15] , din0_a[15],din1_a[15] ,  din0_a[15],din1_a[15] , din0_a[15],din1_a[15], // 127:120 
                         din0_a[14],din1_a[14] , din0_a[14],din1_a[14] ,  din0_a[14],din1_a[14] , din0_a[14],din1_a[14], // 119:112 
                         din0_a[13],din1_a[13] , din0_a[13],din1_a[13] ,  din0_a[13],din1_a[13] , din0_a[13],din1_a[13], // 111:104 
                         din0_a[12],din1_a[12] , din0_a[12],din1_a[12] ,  din0_a[12],din1_a[12] , din0_a[12],din1_a[12], // 103:096 
                         din0_a[11],din1_a[11] , din0_a[11],din1_a[11] ,  din0_a[11],din1_a[11] , din0_a[11],din1_a[11], // 095:088 
                         din0_a[10],din1_a[10] , din0_a[10],din1_a[10] ,  din0_a[10],din1_a[10] , din0_a[10],din1_a[10], // 087:080 
                         din0_a[9],din1_a[9] , din0_a[9],din1_a[9] ,  din0_a[9],din1_a[9] , din0_a[9],din1_a[9], // 079:072 
                         din0_a[8],din1_a[8] , din0_a[8],din1_a[8] ,  din0_a[8],din1_a[8] , din0_a[8],din1_a[8], // 071:064 
                         din0_a[7],din1_a[7] , din0_a[7],din1_a[7] ,  din0_a[7],din1_a[7] , din0_a[7],din1_a[7], // 063:056 
                         din0_a[6],din1_a[6] , din0_a[6],din1_a[6] ,  din0_a[6],din1_a[6] , din0_a[6],din1_a[6], // 055:048 
                         din0_a[5],din1_a[5] , din0_a[5],din1_a[5] ,  din0_a[5],din1_a[5] , din0_a[5],din1_a[5], // 047:040 
                         din0_a[4],din1_a[4] , din0_a[4],din1_a[4] ,  din0_a[4],din1_a[4] , din0_a[4],din1_a[4], // 039:032 
                         din0_a[3],din1_a[3] , din0_a[3],din1_a[3] ,  din0_a[3],din1_a[3] , din0_a[3],din1_a[3], // 031:024 
                         din0_a[2],din1_a[2] , din0_a[2],din1_a[2] ,  din0_a[2],din1_a[2] , din0_a[2],din1_a[2], // 023:016 
                         din0_a[1],din1_a[1] , din0_a[1],din1_a[1] ,  din0_a[1],din1_a[1] , din0_a[1],din1_a[1], // 015:008 
                         din0_a[0],din1_a[0] , din0_a[0],din1_a[0] ,  din0_a[0],din1_a[0] , din0_a[0],din1_a[0]};// 007:000


assign din[135:0] =  (   way_write_en[135:0] & word_write_en[135:0]  & data_in[135:0]  ) |
                     ( ~(way_write_en[135:0] & word_write_en[135:0]) & old_data[135:0] ) ;


////////////////////////////////
// Redunduncy write shifter
////////////////////////////////

always @(reg_en_lft[1:0] or reg_d_lft  or din ) begin
	for (n = 0;  n < 144; n = n + 1 ) begin
		n_reg2 = n;
		if (reg_en_lft[1] & reg_en_lft[0] & ( reg_d_lft >= 5'b00000) & (reg_d_lft <= 5'b10000)) begin
			if ( n_reg2[9:0] <  ((reg_d_lft + 5'h1) * 5'b01000 ))
				wr_data[n] = din[n] ;
			else begin
				if ( n_reg2[9:0] <  ((reg_d_lft + 5'h2)  * 5'b01000 ))
					wr_data[n] = 1'bx ; 
				else
					wr_data[n] = din[n-8] ;
			end
		end else begin
			if (n < 8 ) 
				wr_data[n] = 1'bx ;
			else  
				wr_data[n] = din[n-8] ;
		end
	end
end 

//////////////////////
// Read/write array
//////////////////////

always @ (l1clk or wr_data[143:0] or wr_word_en_ac_l[1:0] or adr_ac_h[5:0] or quaden_f_l or vnw_ary) begin
    if (l1clk & ~quaden_f_l & (~wr_word_en_ac_l[1] | ~wr_word_en_ac_l[0]) & vnw_ary) begin
        mem[adr_ac_h] <= wr_data[143:0] ;
        
        
    end // end if
end // end always


 always @(l1clk or rd_en_a_l or reg_en_lft[1:0] or  reg_d_lft or adr_ac_h[5:0] or rd_worden_ac_l[0] or vnw_ary) begin
    if (l1clk | rd_en_a_l) begin
     dout_wy0_bc[16:0] <= 17'h0;
     dout_wy1_bc[16:0] <= 17'h0;
     dout_wy2_bc[16:0] <= 17'h0;
     dout_wy3_bc[16:0] <= 17'h0;
     word_0_read       <= ~rd_worden_ac_l[0];
     local_dout[143:0] <=  rd_en_a_l ? 144'h0 : mem[adr_ac_h[5:0]];
    end
    if (~l1clk & ~rd_en_a_l & vnw_ary) begin


     		////////////////////////////////
     		// Redunduncy Read shifter
     		////////////////////////////////

		for (n = 0;  n < 136; n = n + 1 ) begin
			n_reg3 = n;
			if (reg_en_lft[1] & reg_en_lft[0] & ( reg_d_lft >= 5'b00000) & (reg_d_lft <= 5'b10000)) begin
     				if ( n_reg3[9:0] >= ((reg_d_lft + 5'h1) * 5'b01000))
					dout[n] = local_dout[n+8] ;
		       	 else
					dout[n] = local_dout[n] ;
			end else
				dout[n] = local_dout[n+8] ;
		end 
     		/////////////end redundacy shifter ///////////////////

     		way3_word0[16:0]  = {dout[135], dout[127], dout[119] , dout[111], 
	         		             dout[103], dout[95], dout[87] , dout[79],
                          	     dout[71], dout[63], dout[55] , dout[47],
                          	     dout[39], dout[31], dout[23] , dout[15],
                          	     dout[7] } ;

     		way3_word1[16:0]  = {dout[134], dout[126], dout[118] , dout[110], 
                          	     dout[102], dout[94], dout[86] , dout[78],
                          	     dout[70], dout[62], dout[54] , dout[46],
                          	     dout[38], dout[30], dout[22] , dout[14],
                          	     dout[6] } ;

     		way2_word0[16:0]  = {dout[133], dout[125], dout[117] , dout[109], 
                          	     dout[101], dout[93], dout[85] , dout[77],
                          	     dout[69], dout[61], dout[53] , dout[45],
                          	     dout[37], dout[29], dout[21] , dout[13],
                          	     dout[5] } ;

     		way2_word1[16:0]  = {dout[132], dout[124], dout[116] , dout[108], 
                          	     dout[100], dout[92], dout[84] , dout[76],
                          	     dout[68], dout[60], dout[52] , dout[44],
                          	     dout[36], dout[28], dout[20] , dout[12],
                          	     dout[4] } ;

     		way1_word0[16:0]  = {dout[131], dout[123], dout[115] , dout[107], 
                          	     dout[99], dout[91], dout[83] , dout[75],
                          	     dout[67], dout[59], dout[51] , dout[43],
                          	     dout[35], dout[27], dout[19] , dout[11],
                          	     dout[3] } ;

     		way1_word1[16:0]  = {dout[130], dout[122], dout[114] , dout[106], 
                          	     dout[98], dout[90], dout[82] , dout[74],
                          	     dout[66], dout[58], dout[50] , dout[42],
                          	     dout[34], dout[26], dout[18] , dout[10],
                          	     dout[2] } ;

		way0_word0[16:0]  = {dout[129], dout[121], dout[113] , dout[105], 
                          	     dout[97], dout[89], dout[81] , dout[73],
                          	     dout[65], dout[57], dout[49] , dout[41],
                          	     dout[33], dout[25], dout[17] , dout[9],
                          	     dout[1] } ;

		way0_word1[16:0]  = {dout[128], dout[120], dout[112] , dout[104], 
                          	     dout[96], dout[88], dout[80] , dout[72],
                          	     dout[64], dout[56], dout[48] , dout[40],
                          	     dout[32], dout[24], dout[16] , dout[8],
                          	     dout[0] } ;

		///////////////////////
		// rd_data column mux
		///////////////////////
       		dout_wy0_bc[16:0] <=  word_0_read ? way0_word0[16:0] : way0_word1[16:0] ;
       		dout_wy1_bc[16:0] <=  word_0_read ? way1_word0[16:0] : way1_word1[16:0] ;
       		dout_wy2_bc[16:0] <=  word_0_read ? way2_word0[16:0] : way2_word1[16:0] ;
       		dout_wy3_bc[16:0] <=  word_0_read ? way3_word0[16:0] : way3_word1[16:0] ;

    end // if (~rd_en_a_l) 
end // always

// Precharge
// always @ (posedge l1clk) begin
//      // local_dout[143:0] = 144'h0;
//      dout_wy0_bc[16:0] <= 17'h0;
//      dout_wy1_bc[16:0] <= 17'h0;
//      dout_wy2_bc[16:0] <= 17'h0;
//      dout_wy3_bc[16:0] <= 17'h0;
// end

////////////////////////////////
// Redunduncy Read shifter
////////////////////////////////
// always @(red_value or local_dout ) begin
//   for (n = 0;  n < 144; n = n + 1 ) begin
//      if ( n >= (red_value * 8 ))
//        dout[n] = local_dout[n+8] ;
//      else
//        dout[n] = local_dout[n] ;
//   end
// end 

assign rd_worden_ac_l_unused = rd_worden_ac_l[1] ;
assign adr_ac_l_unused[5:0]  = adr_ac_l[5:0] ;


supply0 vss;
supply1 vdd;
endmodule
`endif 	// `ifndef FPGA

`ifdef FPGA 

module n2_icd_lft_sb_array(adr_ac_h, adr_ac_l, rd_en_a_l, quaden_f_l, 
	wr_word_en_ac_l, wr_waysel0_ac_l, wr_waysel1_ac_l, din0_a, din1_a, 
	rd_worden_ac_l, l1clk, reg_d_lft, reg_en_lft, vnw_ary, dout_wy0_bc, 
	dout_wy1_bc, dout_wy2_bc, dout_wy3_bc);

	input	[5:0]		adr_ac_h;
	input	[5:0]		adr_ac_l;
	input			rd_en_a_l;
	input			quaden_f_l;
	input	[1:0]		wr_word_en_ac_l;
	input	[3:0]		wr_waysel0_ac_l;
	input	[3:0]		wr_waysel1_ac_l;
	input	[16:0]		din0_a;
	input	[16:0]		din1_a;
	input	[1:0]		rd_worden_ac_l;
	input			l1clk;
	input	[4:0]		reg_d_lft;
	input	[1:0]		reg_en_lft;
	input			vnw_ary;
	output	[16:0]		dout_wy0_bc;
	output	[16:0]		dout_wy1_bc;
	output	[16:0]		dout_wy2_bc;
	output	[16:0]		dout_wy3_bc;

	wire	[135:0]		word_write_en;
	wire	[135:0]		way_write_en;
	wire	[135:0]		data_in;
	wire			rd_worden_ac_l_unused;
	wire	[5:0]		adr_ac_l_unused;

	reg	[143:0]		mem[63:0];
	reg	[143:0]		local_dout;
	reg	[135:0]		old_data;
	reg	[143:0]		wr_data;
	reg	[135:0]		dout;
	wire	[143:0]		temp;
	wire	[135:0]		din;
	reg	[16:0]		dout_wy0_bc;
	reg	[16:0]		dout_wy1_bc;
	reg	[16:0]		dout_wy2_bc;
	reg	[16:0]		dout_wy3_bc;
	reg	[16:0]		way3_word0;
	reg	[16:0]		way3_word1;
	reg	[16:0]		way2_word0;
	reg	[16:0]		way2_word1;
	reg	[16:0]		way1_word0;
	reg	[16:0]		way1_word1;
	reg	[16:0]		way0_word0;
	reg	[16:0]		way0_word1;
	reg	[31:0]		n_reg1;
	reg	[31:0]		n_reg2;
	reg	[31:0]		n_reg3;
	reg			word_0_read;
	integer			n;
	integer			i;
	supply0			vss;
	supply1			vdd;

	assign temp[143:0] = mem[adr_ac_h[5:0]];
	assign word_write_en[135:0] = {68 {(~wr_word_en_ac_l[0]), 
		(~wr_word_en_ac_l[1])}};
	assign way_write_en[135:0] = {17 {(~wr_waysel0_ac_l[3]), 
		(~wr_waysel1_ac_l[3]), (~wr_waysel0_ac_l[2]), 
		(~wr_waysel1_ac_l[2]), (~wr_waysel0_ac_l[1]), 
		(~wr_waysel1_ac_l[1]), (~wr_waysel0_ac_l[0]), 
		(~wr_waysel1_ac_l[0])}};
	assign data_in[135:0] = {din0_a[16], din1_a[16], din0_a[16], din1_a[16],
		din0_a[16], din1_a[16], din0_a[16], din1_a[16], din0_a[15], 
		din1_a[15], din0_a[15], din1_a[15], din0_a[15], din1_a[15], 
		din0_a[15], din1_a[15], din0_a[14], din1_a[14], din0_a[14], 
		din1_a[14], din0_a[14], din1_a[14], din0_a[14], din1_a[14], 
		din0_a[13], din1_a[13], din0_a[13], din1_a[13], din0_a[13], 
		din1_a[13], din0_a[13], din1_a[13], din0_a[12], din1_a[12], 
		din0_a[12], din1_a[12], din0_a[12], din1_a[12], din0_a[12], 
		din1_a[12], din0_a[11], din1_a[11], din0_a[11], din1_a[11], 
		din0_a[11], din1_a[11], din0_a[11], din1_a[11], din0_a[10], 
		din1_a[10], din0_a[10], din1_a[10], din0_a[10], din1_a[10], 
		din0_a[10], din1_a[10], din0_a[9], din1_a[9], din0_a[9], 
		din1_a[9], din0_a[9], din1_a[9], din0_a[9], din1_a[9], 
		din0_a[8], din1_a[8], din0_a[8], din1_a[8], din0_a[8], 
		din1_a[8], din0_a[8], din1_a[8], din0_a[7], din1_a[7], 
		din0_a[7], din1_a[7], din0_a[7], din1_a[7], din0_a[7], 
		din1_a[7], din0_a[6], din1_a[6], din0_a[6], din1_a[6], 
		din0_a[6], din1_a[6], din0_a[6], din1_a[6], din0_a[5], 
		din1_a[5], din0_a[5], din1_a[5], din0_a[5], din1_a[5], 
		din0_a[5], din1_a[5], din0_a[4], din1_a[4], din0_a[4], 
		din1_a[4], din0_a[4], din1_a[4], din0_a[4], din1_a[4], 
		din0_a[3], din1_a[3], din0_a[3], din1_a[3], din0_a[3], 
		din1_a[3], din0_a[3], din1_a[3], din0_a[2], din1_a[2], 
		din0_a[2], din1_a[2], din0_a[2], din1_a[2], din0_a[2], 
		din1_a[2], din0_a[1], din1_a[1], din0_a[1], din1_a[1], 
		din0_a[1], din1_a[1], din0_a[1], din1_a[1], din0_a[0], 
		din1_a[0], din0_a[0], din1_a[0], din0_a[0], din1_a[0], 
		din0_a[0], din1_a[0]};
	assign din[135:0] = (((way_write_en[135:0] & word_write_en[135:0]) & 
		data_in[135:0]) | ((~(way_write_en[135:0] & word_write_en[135:0]
		)) & old_data[135:0]));
	assign rd_worden_ac_l_unused = rd_worden_ac_l[1];
	assign adr_ac_l_unused[5:0] = adr_ac_l[5:0];

	initial begin
	  for (i = 0; (i < 64); i = (i + 1)) begin
	    mem[i] = {144 {1'b0}};
	  end
	  local_dout = {144 {1'b0}};
	end
	always @(reg_en_lft[1:0] or reg_d_lft or temp) begin
	  for (n = 0; (n < 136); n = (n + 1)) begin
	    n_reg1 = n;
	    if (((reg_en_lft[1] & reg_en_lft[0]) & (reg_d_lft >= 5'b0)) & (
		    reg_d_lft <= 5'b10000)) begin
	      if (n_reg1[9:0] >= ((reg_d_lft + 5'b1) * 5'b01000)) begin
		old_data[n] = temp[(n + 8)];
	      end
	      else begin
		old_data[n] = temp[n];
	      end
	    end
	    else begin
	      old_data[n] = temp[(n + 8)];
	    end
	  end
	end
	always @(reg_en_lft[1:0] or reg_d_lft or din) begin
	  for (n = 0; (n < 144); n = (n + 1)) begin
	    n_reg2 = n;
	    if (((reg_en_lft[1] & reg_en_lft[0]) & (reg_d_lft >= 5'b0)) & (
		    reg_d_lft <= 5'b10000)) begin
	      if (n_reg2[9:0] < ((reg_d_lft + 5'b1) * 5'b01000)) begin
		wr_data[n] = din[n];
	      end
	      else
		begin
		  if (n_reg2[9:0] < ((reg_d_lft + 5'b00010) * 5'b01000)) begin
		    wr_data[n] = 1'bx;
		  end
		  else begin
		    wr_data[n] = din[(n - 8)];
		  end
		end
	    end
	    else
	      begin
		if (n < 8) begin
		  wr_data[n] = 1'bx;
		end
		else begin
		  wr_data[n] = din[(n - 8)];
		end
	      end
	  end
	end

	always @(l1clk or wr_data[143:0] or wr_word_en_ac_l[1:0] or 
		adr_ac_h[5:0] or quaden_f_l or vnw_ary) begin
	  if (((l1clk & (~quaden_f_l)) & ((~wr_word_en_ac_l[1]) | (~
		  wr_word_en_ac_l[0]))) & vnw_ary) begin
	    mem[adr_ac_h] <= wr_data[143:0];
	  end
	end
	always @(l1clk or adr_ac_h[5:0] or rd_worden_ac_l[0]) begin
	  if (l1clk) begin
	    word_0_read <= (~rd_worden_ac_l[0]);
	    local_dout[143:0] <= mem[adr_ac_h[5:0]];
	  end
	end

	always @(negedge l1clk) begin
	  if (~rd_en_a_l) begin
	    for (n = 0; (n < 136); n = (n + 1)) begin
	      n_reg3 = n;
	      if (((reg_en_lft[1] & reg_en_lft[0]) & (reg_d_lft >= 5'b0)) & (
		      reg_d_lft <= 5'b10000)) begin
		if (n_reg3[9:0] >= ((reg_d_lft + 5'b1) * 5'b01000)) begin
		  dout[n] = local_dout[(n + 8)];
		end
		else begin
		  dout[n] = local_dout[n];
		end
	      end
	      else begin
		dout[n] = local_dout[(n + 8)];
	      end
	    end
	    way3_word0[16:0] = {dout[135], dout[127], dout[119], dout[111], 
		    dout[103], dout[95], dout[87], dout[79], dout[71], dout[63],
		    dout[55], dout[47], dout[39], dout[31], dout[23], dout[15], 
		    dout[7]};
	    way3_word1[16:0] = {dout[134], dout[126], dout[118], dout[110], 
		    dout[102], dout[94], dout[86], dout[78], dout[70], dout[62],
		    dout[54], dout[46], dout[38], dout[30], dout[22], dout[14], 
		    dout[6]};
	    way2_word0[16:0] = {dout[133], dout[125], dout[117], dout[109], 
		    dout[101], dout[93], dout[85], dout[77], dout[69], dout[61],
		    dout[53], dout[45], dout[37], dout[29], dout[21], dout[13], 
		    dout[5]};
	    way2_word1[16:0] = {dout[132], dout[124], dout[116], dout[108], 
		    dout[100], dout[92], dout[84], dout[76], dout[68], dout[60],
		    dout[52], dout[44], dout[36], dout[28], dout[20], dout[12], 
		    dout[4]};
	    way1_word0[16:0] = {dout[131], dout[123], dout[115], dout[107], 
		    dout[99], dout[91], dout[83], dout[75], dout[67], dout[59], 
		    dout[51], dout[43], dout[35], dout[27], dout[19], dout[11], 
		    dout[3]};
	    way1_word1[16:0] = {dout[130], dout[122], dout[114], dout[106], 
		    dout[98], dout[90], dout[82], dout[74], dout[66], dout[58], 
		    dout[50], dout[42], dout[34], dout[26], dout[18], dout[10], 
		    dout[2]};
	    way0_word0[16:0] = {dout[129], dout[121], dout[113], dout[105], 
		    dout[97], dout[89], dout[81], dout[73], dout[65], dout[57], 
		    dout[49], dout[41], dout[33], dout[25], dout[17], dout[9], 
		    dout[1]};
	    way0_word1[16:0] = {dout[128], dout[120], dout[112], dout[104], 
		    dout[96], dout[88], dout[80], dout[72], dout[64], dout[56], 
		    dout[48], dout[40], dout[32], dout[24], dout[16], dout[8], 
		    dout[0]};
	    dout_wy0_bc[16:0] <= (word_0_read ? way0_word0[16:0] : 
		    way0_word1[16:0]);
	    dout_wy1_bc[16:0] <= (word_0_read ? way1_word0[16:0] : 
		    way1_word1[16:0]);
	    dout_wy2_bc[16:0] <= (word_0_read ? way2_word0[16:0] : 
		    way2_word1[16:0]);
	    dout_wy3_bc[16:0] <= (word_0_read ? way3_word0[16:0] : 
		    way3_word1[16:0]);
	  end
	end
endmodule

`endif 	// `ifdef FPGA


`ifndef FPGA
module n2_icd_rgt_sb_array (
  adr_ac_h, 
  adr_ac_l, 
  rd_en_a_l, 
  quaden_f_l, 
  wr_word_en_ac_l, 
  wr_waysel0_ac_l, 
  wr_waysel1_ac_l, 
  din0_a, 
  din1_a, 
  rd_worden_ac_l, 
  l1clk, 
  vnw_ary, 
  reg_d_rgt, 
  reg_en_rgt, 
  dout_wy0_bc, 
  dout_wy1_bc, 
  dout_wy2_bc, 
  dout_wy3_bc);
wire [127:0] word_write_en;
wire [127:0] way_write_en;
wire [127:0] data_in;
wire rd_worden_ac_l_unused;
wire [5:0] adr_ac_l_unused;


input [5:0] 	adr_ac_h ;
input [5:0] 	adr_ac_l ;
input       	rd_en_a_l ;
input       	quaden_f_l ;
input [1:0] 	wr_word_en_ac_l ;
input [3:0] 	wr_waysel0_ac_l ;
input [3:0] 	wr_waysel1_ac_l ;
input [32:17] 	din0_a ;
input [32:17] 	din1_a ;
input [1:0]  	rd_worden_ac_l ;
input        	l1clk ;

input		vnw_ary;

input [4:0]     reg_d_rgt;
input [1:0]     reg_en_rgt;

output [15:0] 	dout_wy0_bc ;
output [15:0] 	dout_wy1_bc ;
output [15:0] 	dout_wy2_bc ;
output [15:0] 	dout_wy3_bc ;


reg     [135:0]   mem[63:0] ;


reg     [135:0]      local_dout;
reg     [127:0]      old_data;
reg     [135:0]      wr_data;
reg     [127:0]      dout;
wire    [135:0]      temp;
wire    [127:0]      din;

 reg    [15:0]  dout_wy0_bc ;
 reg    [15:0]  dout_wy1_bc ;
 reg    [15:0]  dout_wy2_bc ;
 reg    [15:0]  dout_wy3_bc ;

 reg    [15:0]  way3_word0 ;
 reg    [15:0]  way3_word1 ;
 reg    [15:0]  way2_word0 ;
 reg    [15:0]  way2_word1 ;
 reg    [15:0]  way1_word0 ;
 reg    [15:0]  way1_word1 ;
 reg    [15:0]  way0_word0 ;
 reg    [15:0]  way0_word1 ;
 reg    [31:0] 	n_reg1;
 reg    [31:0] 	n_reg2;
 reg    [31:0] 	n_reg3;
 reg            word_0_read ;

integer n;


`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
  for (i=0; i<64; i=i+1) begin
   mem [i] = {136{1'b0}};
  end
  local_dout = {136{1'b0}};
end
`endif


// assign word_0_read = ~rd_worden_ac_l[0] & ~rd_en_a_l ;
// assign red_value[4:0] = reg_d_rgt[4:0] & {5{reg_en_rgt[1] & reg_en_rgt[0]}};
assign temp[135:0] = mem[adr_ac_h[5:0]] ;

////////////////////////////////
// Redunduncy Read shifter
////////////////////////////////
always @(reg_en_rgt[1:0]  or reg_d_rgt  or temp ) begin
        for (n = 0;  n < 128; n = n + 1 ) begin
		n_reg1 = n;
                if (reg_en_rgt[1] & reg_en_rgt[0] & ( reg_d_rgt >= 5'b00000) & (reg_d_rgt <= 5'b01111)) begin
                        if ( n_reg1[9:0] >= ((reg_d_rgt + 5'h1) * 5'b01000))
                                old_data[n] = temp[n+8] ;
                        else
                                old_data[n] = temp[n] ;
                end else
                        old_data[n] = temp[n+8] ;
        end
end

assign word_write_en[127:0] =  {64{~wr_word_en_ac_l[0], ~wr_word_en_ac_l[1]}} ;   
assign way_write_en[127:0]  =  {16{~wr_waysel0_ac_l[0] , ~wr_waysel1_ac_l[0] ,~wr_waysel0_ac_l[1] , ~wr_waysel1_ac_l[1],
                                   ~wr_waysel0_ac_l[2] , ~wr_waysel1_ac_l[2] ,~wr_waysel0_ac_l[3] , ~wr_waysel1_ac_l[3] }} ;

assign data_in[127:0] = {din0_a[32],din1_a[32] , din0_a[32],din1_a[32] ,  din0_a[32],din1_a[32] , din0_a[32],din1_a[32], // 127:120 
                         din0_a[31],din1_a[31] , din0_a[31],din1_a[31] ,  din0_a[31],din1_a[31] , din0_a[31],din1_a[31], // 119:112 
                         din0_a[30],din1_a[30] , din0_a[30],din1_a[30] ,  din0_a[30],din1_a[30] , din0_a[30],din1_a[30], // 111:104 
                         din0_a[29],din1_a[29] , din0_a[29],din1_a[29] ,  din0_a[29],din1_a[29] , din0_a[29],din1_a[29], // 103:096 
                         din0_a[28],din1_a[28] , din0_a[28],din1_a[28] ,  din0_a[28],din1_a[28] , din0_a[28],din1_a[28], // 095:088 
                         din0_a[27],din1_a[27] , din0_a[27],din1_a[27] ,  din0_a[27],din1_a[27] , din0_a[27],din1_a[27], // 087:080 
                         din0_a[26],din1_a[26] , din0_a[26],din1_a[26] ,  din0_a[26],din1_a[26] , din0_a[26],din1_a[26], // 079:072 
                         din0_a[25],din1_a[25] , din0_a[25],din1_a[25] ,  din0_a[25],din1_a[25] , din0_a[25],din1_a[25], // 071:064 
                         din0_a[24],din1_a[24] , din0_a[24],din1_a[24] ,  din0_a[24],din1_a[24] , din0_a[24],din1_a[24], // 063:056 
                         din0_a[23],din1_a[23] , din0_a[23],din1_a[23] ,  din0_a[23],din1_a[23] , din0_a[23],din1_a[23], // 055:048 
                         din0_a[22],din1_a[22] , din0_a[22],din1_a[22] ,  din0_a[22],din1_a[22] , din0_a[22],din1_a[22], // 047:040 
                         din0_a[21],din1_a[21] , din0_a[21],din1_a[21] ,  din0_a[21],din1_a[21] , din0_a[21],din1_a[21], // 039:032 
                         din0_a[20],din1_a[20] , din0_a[20],din1_a[20] ,  din0_a[20],din1_a[20] , din0_a[20],din1_a[20], // 031:024
                         din0_a[19],din1_a[19] , din0_a[19],din1_a[19] ,  din0_a[19],din1_a[19] , din0_a[19],din1_a[19], // 023:016 
                         din0_a[18],din1_a[18] , din0_a[18],din1_a[18] ,  din0_a[18],din1_a[18] , din0_a[18],din1_a[18], // 015:008 
                         din0_a[17],din1_a[17] , din0_a[17],din1_a[17] ,  din0_a[17],din1_a[17] , din0_a[17],din1_a[17]};// 007:000 


assign din[127:0] =  (   way_write_en[127:0] & word_write_en[127:0]  & data_in[127:0]  ) |
                     ( ~(way_write_en[127:0] & word_write_en[127:0]) & old_data[127:0] ) ;

////////////////////////////////
// Redunduncy write shifter
////////////////////////////////
always @(reg_en_rgt[1:0] or reg_d_rgt  or din ) begin
        for (n = 0;  n < 136; n = n + 1 ) begin
		n_reg2 = n;
                if (reg_en_rgt[1] & reg_en_rgt[0] & ( reg_d_rgt >= 5'b00000) & (reg_d_rgt <= 5'b01111)) begin
                        if ( n_reg2[9:0] <  ((reg_d_rgt + 5'h1) * 5'b01000 ))
                                wr_data[n] = din[n] ;
                        else begin
                                if ( n_reg2[9:0] <  ((reg_d_rgt + 5'h2)  * 5'b01000 ))
                                        wr_data[n] = 1'bx ;
                                else
                                        wr_data[n] = din[n-8] ;
                        end
                end else begin
			if (n < 8) 
				wr_data[n] = 1'bx ;
			else
				wr_data[n] = din[n-8] ;
		end
        end
end

//////////////////////
// Read/write array
//////////////////////


always @ (l1clk or wr_data[135:0] or wr_word_en_ac_l[1:0] or adr_ac_h[5:0] or quaden_f_l or vnw_ary) begin
    if (l1clk  & ~quaden_f_l & (~wr_word_en_ac_l[1] | ~wr_word_en_ac_l[0]) & vnw_ary) begin
        mem[adr_ac_h] <= wr_data[135:0] ;
        
        
    end // end if
end // end always


 always @(l1clk or rd_en_a_l or reg_en_rgt[1:0] or  reg_d_rgt or adr_ac_h[5:0] or rd_worden_ac_l[0] or vnw_ary) begin
    if (l1clk | rd_en_a_l) begin
     dout_wy0_bc[15:0] <= 16'h0;
     dout_wy1_bc[15:0] <= 16'h0;
     dout_wy2_bc[15:0] <= 16'h0;
     dout_wy3_bc[15:0] <= 16'h0;
     word_0_read       <= ~rd_worden_ac_l[0];
     local_dout[135:0] <=  rd_en_a_l ? 136'h0 : mem[adr_ac_h[5:0]];
    end
    if (~l1clk & ~rd_en_a_l & vnw_ary) begin


    		////////////////////////////////
    		// Redunduncy Read shifter
    		////////////////////////////////
        	for (n = 0;  n < 128; n = n + 1 ) begin
			n_reg3 = n;
			if (reg_en_rgt[1] & reg_en_rgt[0] & ( reg_d_rgt >= 5'b00000) & (reg_d_rgt <= 5'b01111)) begin
				if ( n_reg3[9:0] >= ((reg_d_rgt + 5'h1) * 5'b01000))
                                	dout[n] = local_dout[n+8] ;
                        	else
                                	dout[n] = local_dout[n] ;
                	end else
                        	dout[n] = local_dout[n+8] ;
        	end
    		///////////////////////
    		// rd_data column mux
    		///////////////////////

    		way0_word0[15:0]  = {dout[127], dout[119] , dout[111], dout[103], 
       		                     dout[95], dout[87] , dout[79], dout[71], 
       		                     dout[63], dout[55] , dout[47], dout[39], 
       		                     dout[31], dout[23] , dout[15], dout[7] } ;

    		way0_word1[15:0]  = {dout[126], dout[118] , dout[110], dout[102], 
       		                     dout[94], dout[86] , dout[78], dout[70], 
       		                     dout[62], dout[54] , dout[46], dout[38], 
       		                     dout[30], dout[22] , dout[14], dout[6] } ;

    		way1_word0[15:0]  = {dout[125], dout[117] , dout[109], dout[101], 
       		                     dout[93], dout[85] , dout[77], dout[69], 
       		                     dout[61], dout[53] , dout[45], dout[37], 
       		                     dout[29], dout[21] , dout[13], dout[5] } ;

    		way1_word1[15:0]  = {dout[124], dout[116] , dout[108], dout[100], 
       		                     dout[92], dout[84] , dout[76], dout[68], 
       		                     dout[60], dout[52] , dout[44], dout[36], 
       		                     dout[28], dout[20] , dout[12], dout[4] } ;

    		way2_word0[15:0]  = {dout[123], dout[115] , dout[107], dout[99], 
       		                     dout[91], dout[83] , dout[75], dout[67], 
       		                     dout[59], dout[51] , dout[43], dout[35], 
       		                     dout[27], dout[19] , dout[11], dout[3] } ;

    		way2_word1[15:0]  = {dout[122], dout[114] , dout[106], dout[98], 
       		                     dout[90], dout[82] , dout[74], dout[66], 
       		                     dout[58], dout[50] , dout[42], dout[34], 
       		                     dout[26], dout[18] , dout[10], dout[2] } ;

    		way3_word0[15:0]  = {dout[121], dout[113] , dout[105], dout[97], 
       		                     dout[89], dout[81] , dout[73], dout[65], 
       		                     dout[57], dout[49] , dout[41], dout[33], 
       		                     dout[25], dout[17] , dout[9], dout[1] } ;

    		way3_word1[15:0]  = {dout[120], dout[112] , dout[104], dout[96], 
       		                     dout[88], dout[80] , dout[72], dout[64], 
       		                     dout[56], dout[48] , dout[40], dout[32], 
       		                     dout[24], dout[16] , dout[8], dout[0] } ;

    		dout_wy0_bc[15:0] <=  word_0_read ? way0_word0[15:0] : way0_word1[15:0] ;  
    		dout_wy1_bc[15:0] <=  word_0_read ? way1_word0[15:0] : way1_word1[15:0] ;  
    		dout_wy2_bc[15:0] <=  word_0_read ? way2_word0[15:0] : way2_word1[15:0] ;  
    		dout_wy3_bc[15:0] <=  word_0_read ? way3_word0[15:0] : way3_word1[15:0] ;  

    end // if (~rd_en_a_l)
end // always

// Precharge
// always @ (posedge l1clk) begin
// local_dout[135:0] = 136'h0;
//	dout_wy0_bc[15:0] <= 16'b0;
//	dout_wy1_bc[15:0] <= 16'b0;
//	dout_wy2_bc[15:0] <= 16'b0;
//	dout_wy3_bc[15:0] <= 16'b0;
//end

////////////////////////////////
// Redunduncy Read shifter
////////////////////////////////
// always @(red_value or local_dout ) begin
//   for (n = 0;  n < 136; n = n + 1 ) begin
//      if ( n >= (red_value * 8 ))
//        dout[n] = local_dout[n+8] ;
//      else
//        dout[n] = local_dout[n] ;
//   end
// end

assign rd_worden_ac_l_unused = rd_worden_ac_l[1] ;
assign adr_ac_l_unused[5:0]  = adr_ac_l[5:0] ;


supply0 vss;
supply1 vdd;
endmodule
`endif	// `ifndef FPGA

`ifdef FPGA

module n2_icd_rgt_sb_array(adr_ac_h, adr_ac_l, rd_en_a_l, quaden_f_l, 
	wr_word_en_ac_l, wr_waysel0_ac_l, wr_waysel1_ac_l, din0_a, din1_a, 
	rd_worden_ac_l, l1clk, vnw_ary, reg_d_rgt, reg_en_rgt, dout_wy0_bc, 
	dout_wy1_bc, dout_wy2_bc, dout_wy3_bc);

	input	[5:0]		adr_ac_h;
	input	[5:0]		adr_ac_l;
	input			rd_en_a_l;
	input			quaden_f_l;
	input	[1:0]		wr_word_en_ac_l;
	input	[3:0]		wr_waysel0_ac_l;
	input	[3:0]		wr_waysel1_ac_l;
	input	[32:17]		din0_a;
	input	[32:17]		din1_a;
	input	[1:0]		rd_worden_ac_l;
	input			l1clk;
	input			vnw_ary;
	input	[4:0]		reg_d_rgt;
	input	[1:0]		reg_en_rgt;
	output	[15:0]		dout_wy0_bc;
	output	[15:0]		dout_wy1_bc;
	output	[15:0]		dout_wy2_bc;
	output	[15:0]		dout_wy3_bc;

	wire	[127:0]		word_write_en;
	wire	[127:0]		way_write_en;
	wire	[127:0]		data_in;
	wire			rd_worden_ac_l_unused;
	wire	[5:0]		adr_ac_l_unused;

	reg	[135:0]		mem[63:0];
	reg	[135:0]		local_dout;
	reg	[127:0]		old_data;
	reg	[135:0]		wr_data;
	reg	[127:0]		dout;
	wire	[135:0]		temp;
	wire	[127:0]		din;
	reg	[15:0]		dout_wy0_bc;
	reg	[15:0]		dout_wy1_bc;
	reg	[15:0]		dout_wy2_bc;
	reg	[15:0]		dout_wy3_bc;
	reg	[15:0]		way3_word0;
	reg	[15:0]		way3_word1;
	reg	[15:0]		way2_word0;
	reg	[15:0]		way2_word1;
	reg	[15:0]		way1_word0;
	reg	[15:0]		way1_word1;
	reg	[15:0]		way0_word0;
	reg	[15:0]		way0_word1;
	reg	[31:0]		n_reg1;
	reg	[31:0]		n_reg2;
	reg	[31:0]		n_reg3;
	reg			word_0_read;
	integer			n;
	integer			i;
	supply0			vss;
	supply1			vdd;

	assign temp[135:0] = mem[adr_ac_h[5:0]];
	assign word_write_en[127:0] = {64 {(~wr_word_en_ac_l[0]), 
		(~wr_word_en_ac_l[1])}};
	assign way_write_en[127:0] = {16 {(~wr_waysel0_ac_l[0]), 
		(~wr_waysel1_ac_l[0]), (~wr_waysel0_ac_l[1]), 
		(~wr_waysel1_ac_l[1]), (~wr_waysel0_ac_l[2]), 
		(~wr_waysel1_ac_l[2]), (~wr_waysel0_ac_l[3]), 
		(~wr_waysel1_ac_l[3])}};
	assign data_in[127:0] = {din0_a[32], din1_a[32], din0_a[32], din1_a[32],
		din0_a[32], din1_a[32], din0_a[32], din1_a[32], din0_a[31], 
		din1_a[31], din0_a[31], din1_a[31], din0_a[31], din1_a[31], 
		din0_a[31], din1_a[31], din0_a[30], din1_a[30], din0_a[30], 
		din1_a[30], din0_a[30], din1_a[30], din0_a[30], din1_a[30], 
		din0_a[29], din1_a[29], din0_a[29], din1_a[29], din0_a[29], 
		din1_a[29], din0_a[29], din1_a[29], din0_a[28], din1_a[28], 
		din0_a[28], din1_a[28], din0_a[28], din1_a[28], din0_a[28], 
		din1_a[28], din0_a[27], din1_a[27], din0_a[27], din1_a[27], 
		din0_a[27], din1_a[27], din0_a[27], din1_a[27], din0_a[26], 
		din1_a[26], din0_a[26], din1_a[26], din0_a[26], din1_a[26], 
		din0_a[26], din1_a[26], din0_a[25], din1_a[25], din0_a[25], 
		din1_a[25], din0_a[25], din1_a[25], din0_a[25], din1_a[25], 
		din0_a[24], din1_a[24], din0_a[24], din1_a[24], din0_a[24], 
		din1_a[24], din0_a[24], din1_a[24], din0_a[23], din1_a[23], 
		din0_a[23], din1_a[23], din0_a[23], din1_a[23], din0_a[23], 
		din1_a[23], din0_a[22], din1_a[22], din0_a[22], din1_a[22], 
		din0_a[22], din1_a[22], din0_a[22], din1_a[22], din0_a[21], 
		din1_a[21], din0_a[21], din1_a[21], din0_a[21], din1_a[21], 
		din0_a[21], din1_a[21], din0_a[20], din1_a[20], din0_a[20], 
		din1_a[20], din0_a[20], din1_a[20], din0_a[20], din1_a[20], 
		din0_a[19], din1_a[19], din0_a[19], din1_a[19], din0_a[19], 
		din1_a[19], din0_a[19], din1_a[19], din0_a[18], din1_a[18], 
		din0_a[18], din1_a[18], din0_a[18], din1_a[18], din0_a[18], 
		din1_a[18], din0_a[17], din1_a[17], din0_a[17], din1_a[17], 
		din0_a[17], din1_a[17], din0_a[17], din1_a[17]};
	assign din[127:0] = (((way_write_en[127:0] & word_write_en[127:0]) & 
		data_in[127:0]) | ((~(way_write_en[127:0] & word_write_en[127:0]
		)) & old_data[127:0]));
	assign rd_worden_ac_l_unused = rd_worden_ac_l[1];
	assign adr_ac_l_unused[5:0] = adr_ac_l[5:0];

	initial begin
	  for (i = 0; (i < 64); i = (i + 1)) begin
	    mem[i] = {136 {1'b0}};
	  end
	  local_dout = {136 {1'b0}};
	end
	always @(reg_en_rgt[1:0] or reg_d_rgt or temp) begin
	  for (n = 0; (n < 128); n = (n + 1)) begin
	    n_reg1 = n;
	    if (((reg_en_rgt[1] & reg_en_rgt[0]) & (reg_d_rgt >= 5'b0)) & (
		    reg_d_rgt <= 5'b01111)) begin
	      if (n_reg1[9:0] >= ((reg_d_rgt + 5'b1) * 5'b01000)) begin
		old_data[n] = temp[(n + 8)];
	      end
	      else begin
		old_data[n] = temp[n];
	      end
	    end
	    else begin
	      old_data[n] = temp[(n + 8)];
	    end
	  end
	end
	always @(reg_en_rgt[1:0] or reg_d_rgt or din) begin
	  for (n = 0; (n < 136); n = (n + 1)) begin
	    n_reg2 = n;
	    if (((reg_en_rgt[1] & reg_en_rgt[0]) & (reg_d_rgt >= 5'b0)) & (
		    reg_d_rgt <= 5'b01111)) begin
	      if (n_reg2[9:0] < ((reg_d_rgt + 5'b1) * 5'b01000)) begin
		wr_data[n] = din[n];
	      end
	      else
		begin
		  if (n_reg2[9:0] < ((reg_d_rgt + 5'b00010) * 5'b01000)) begin
		    wr_data[n] = 1'bx;
		  end
		  else begin
		    wr_data[n] = din[(n - 8)];
		  end
		end
	    end
	    else
	      begin
		if (n < 8) begin
		  wr_data[n] = 1'bx;
		end
		else begin
		  wr_data[n] = din[(n - 8)];
		end
	      end
	  end
	end


	always @(l1clk or wr_data[135:0] or wr_word_en_ac_l[1:0] or 
		adr_ac_h[5:0] or quaden_f_l or vnw_ary) begin
	  if (((l1clk & (~quaden_f_l)) & ((~wr_word_en_ac_l[1]) | (~
		  wr_word_en_ac_l[0]))) & vnw_ary) begin
	    mem[adr_ac_h] <= wr_data[135:0];
	  end
	end
	always @(l1clk or adr_ac_h[5:0] or rd_worden_ac_l[0]) begin
	  if (l1clk) begin
	    word_0_read <= (~rd_worden_ac_l[0]);
	    local_dout[135:0] <= mem[adr_ac_h[5:0]];
	  end
	end

	always @(negedge l1clk) begin
	  if (~rd_en_a_l) begin
	    for (n = 0; (n < 128); n = (n + 1)) begin
	      n_reg3 = n;
	      if (((reg_en_rgt[1] & reg_en_rgt[0]) & (reg_d_rgt >= 5'b0)) & (
		      reg_d_rgt <= 5'b01111)) begin
		if (n_reg3[9:0] >= ((reg_d_rgt + 5'b1) * 5'b01000)) begin
		  dout[n] = local_dout[(n + 8)];
		end
		else begin
		  dout[n] = local_dout[n];
		end
	      end
	      else begin
		dout[n] = local_dout[(n + 8)];
	      end
	    end
	    way0_word0[15:0] = {dout[127], dout[119], dout[111], dout[103], 
		    dout[95], dout[87], dout[79], dout[71], dout[63], dout[55], 
		    dout[47], dout[39], dout[31], dout[23], dout[15], dout[7]};
	    way0_word1[15:0] = {dout[126], dout[118], dout[110], dout[102], 
		    dout[94], dout[86], dout[78], dout[70], dout[62], dout[54], 
		    dout[46], dout[38], dout[30], dout[22], dout[14], dout[6]};
	    way1_word0[15:0] = {dout[125], dout[117], dout[109], dout[101], 
		    dout[93], dout[85], dout[77], dout[69], dout[61], dout[53], 
		    dout[45], dout[37], dout[29], dout[21], dout[13], dout[5]};
	    way1_word1[15:0] = {dout[124], dout[116], dout[108], dout[100], 
		    dout[92], dout[84], dout[76], dout[68], dout[60], dout[52], 
		    dout[44], dout[36], dout[28], dout[20], dout[12], dout[4]};
	    way2_word0[15:0] = {dout[123], dout[115], dout[107], dout[99], 
		    dout[91], dout[83], dout[75], dout[67], dout[59], dout[51], 
		    dout[43], dout[35], dout[27], dout[19], dout[11], dout[3]};
	    way2_word1[15:0] = {dout[122], dout[114], dout[106], dout[98], 
		    dout[90], dout[82], dout[74], dout[66], dout[58], dout[50], 
		    dout[42], dout[34], dout[26], dout[18], dout[10], dout[2]};
	    way3_word0[15:0] = {dout[121], dout[113], dout[105], dout[97], 
		    dout[89], dout[81], dout[73], dout[65], dout[57], dout[49], 
		    dout[41], dout[33], dout[25], dout[17], dout[9], dout[1]};
	    way3_word1[15:0] = {dout[120], dout[112], dout[104], dout[96], 
		    dout[88], dout[80], dout[72], dout[64], dout[56], dout[48], 
		    dout[40], dout[32], dout[24], dout[16], dout[8], dout[0]};
	    dout_wy0_bc[15:0] <= (word_0_read ? way0_word0[15:0] : 
		    way0_word1[15:0]);
	    dout_wy1_bc[15:0] <= (word_0_read ? way1_word0[15:0] : 
		    way1_word1[15:0]);
	    dout_wy2_bc[15:0] <= (word_0_read ? way2_word0[15:0] : 
		    way2_word1[15:0]);
	    dout_wy3_bc[15:0] <= (word_0_read ? way3_word0[15:0] : 
		    way3_word1[15:0]);
	  end
	end
endmodule

`endif	// `ifdef FPGA


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_mux_macro__mux_aonpe__ports_8__stack_50c__width_33 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  din3, 
  sel3, 
  din4, 
  sel4, 
  din5, 
  sel5, 
  din6, 
  sel6, 
  din7, 
  sel7, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;
wire buffout3;
wire buffout4;
wire buffout5;
wire buffout6;
wire buffout7;

  input [32:0] din0;
  input sel0;
  input [32:0] din1;
  input sel1;
  input [32:0] din2;
  input sel2;
  input [32:0] din3;
  input sel3;
  input [32:0] din4;
  input sel4;
  input [32:0] din5;
  input sel5;
  input [32:0] din6;
  input sel6;
  input [32:0] din7;
  input sel7;
  output [32:0] dout;


cl_dp1_muxbuff8_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .in3(sel3),
 .in4(sel4),
 .in5(sel5),
 .in6(sel6),
 .in7(sel7),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2),
 .out3(buffout3),
 .out4(buffout4),
 .out5(buffout5),
 .out6(buffout6),
 .out7(buffout7)
);
mux8s #(33)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .sel3(buffout3),
  .sel4(buffout4),
  .sel5(buffout5),
  .sel6(buffout6),
  .sel7(buffout7),
  .in0(din0[32:0]),
  .in1(din1[32:0]),
  .in2(din2[32:0]),
  .in3(din3[32:0]),
  .in4(din4[32:0]),
  .in5(din5[32:0]),
  .in6(din6[32:0]),
  .in7(din7[32:0]),
.dout(dout[32:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_mux_macro__mux_aodec__ports_8__width_7 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [6:0] din0;
  input [6:0] din1;
  input [6:0] din2;
  input [6:0] din3;
  input [6:0] din4;
  input [6:0] din5;
  input [6:0] din6;
  input [6:0] din7;
  input [2:0] sel;
  output [6:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(7)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
  .in2(din2[6:0]),
  .in3(din3[6:0]),
  .in4(din4[6:0]),
  .in5(din5[6:0]),
  .in6(din6[6:0]),
  .in7(din7[6:0]),
.dout(dout[6:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_icd_sp_16p5kb_cust_mux_macro__mux_aope__ports_2__width_7 (
  din0, 
  din1, 
  sel0, 
  dout);
wire psel0;
wire psel1;

  input [6:0] din0;
  input [6:0] din1;
  input sel0;
  output [6:0] dout;


cl_dp1_penc2_8x  c0_0 (
 .sel0(sel0),
 .psel0(psel0),
 .psel1(psel1)
);

mux2s #(7)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .in0(din0[6:0]),
  .in1(din1[6:0]),
.dout(dout[6:0])
);


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_ict_sp_1920b_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_ict_sp_1920b_cust (
  l2clk, 
  scan_in, 
  tcu_pce_ov, 
  tcu_scan_en, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_se_scancollar_in, 
  tcu_array_wr_inhibit, 
  agd_ic_index_bf, 
  agc_fill_wrway_bf, 
  ftp_tg_rd_req_bf, 
  ftp_tg_wr_req_bf, 
  ftp_tg_clk_en, 
  agd_ict_wrtag_bf, 
  ict_itlb_way_0_tag_f, 
  ict_itlb_way_1_tag_f, 
  ict_itlb_way_2_tag_f, 
  ict_itlb_way_3_tag_f, 
  ict_itlb_way_4_tag_f, 
  ict_itlb_way_5_tag_f, 
  ict_itlb_way_6_tag_f, 
  ict_itlb_way_7_tag_f, 
  scan_out)  ;
wire l1clk_din;
wire l1clk_in;
wire l1clk_array;
wire pce_ov;
wire stop;
wire siclk;
wire soclk;
wire wr_inhibit;
wire [2:0] wrway_b;
wire [7:0] wrway_dec_b;
wire wr_inhibit_;
wire wrreq_b;
wire [7:0] wr_en_way_b;
wire [7:0] wr_en_way_f;
wire [7:0] wr_en_unused;
wire wrway_reg_scanin;
wire wrway_reg_scanout;
wire [2:0] wrway_b_unused;
wire index_reg_i_5_scanin;
wire index_reg_i_5_scanout;
wire [10:5] index_f;
wire [10:5] index_f_l_unused;
wire index_reg_i_6_scanin;
wire index_reg_i_6_scanout;
wire index_reg_i_7_scanin;
wire index_reg_i_7_scanout;
wire index_reg_i_8_scanin;
wire index_reg_i_8_scanout;
wire index_reg_i_9_scanin;
wire index_reg_i_9_scanout;
wire index_reg_i_10_scanin;
wire index_reg_i_10_scanout;
wire rdreq_reg_scanin;
wire rdreq_reg_scanout;
wire rdreq_a;
wire rdreq_f;
wire rdreq_f_unused;
wire wrreq_reg_scanin;
wire wrreq_reg_scanout;
wire wrreq_a;
wire rdreq_reg_dup_scanin;
wire rdreq_reg_dup_scanout;
wire rdreq_b;
wire rdreq_f_l_dup_unused;
wire wrreq_reg_dup_scanin;
wire wrreq_reg_dup_scanout;
wire wrreq_b_;
wire rd_en_b;
wire [29:0] wrtag_reg_in;
wire wrtag_reg_scanin;
wire wrtag_reg_scanout;
wire [29:0] wrtag_reg_out;
wire [29:0] ic_wrtag_f_l;
wire [29:0] ic_wrtag_f;


   input          l2clk;
   input          scan_in;
   input          tcu_pce_ov;
   input          tcu_scan_en;
   input          tcu_aclk;
   input          tcu_bclk;
   input          tcu_se_scancollar_in;
   input          tcu_array_wr_inhibit;

   input [10:5]   agd_ic_index_bf;
   input [2:0]    agc_fill_wrway_bf;     // way to write to, this is
                                     	       // sent by the l2c over the cpx
   input          ftp_tg_rd_req_bf;
   input          ftp_tg_wr_req_bf;
   input          ftp_tg_clk_en;


   input [29:0]   agd_ict_wrtag_bf;      // tag + 1b parity

   output [29:0]  ict_itlb_way_0_tag_f; // Tag compare is done in TLB block
   output [29:0]  ict_itlb_way_1_tag_f; // Tag compare is done in TLB block
   output [29:0]  ict_itlb_way_2_tag_f; // Tag compare is done in TLB block
   output [29:0]  ict_itlb_way_3_tag_f; // Tag compare is done in TLB block
   output [29:0]  ict_itlb_way_4_tag_f; // Tag compare is done in TLB block
   output [29:0]  ict_itlb_way_5_tag_f; // Tag compare is done in TLB block
   output [29:0]  ict_itlb_way_6_tag_f; // Tag compare is done in TLB block
   output [29:0]  ict_itlb_way_7_tag_f; // Tag compare is done in TLB block
   output         scan_out;

`ifndef FPGA
// synopsys translate_off
`endif

//================================================
// Clock headers
//================================================
// This clock gates the wrtag input flops.
n2_ict_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_din (
        .l2clk  (l2clk),
        .l1en   (ftp_tg_clk_en),
        .se     (tcu_se_scancollar_in),
        .l1clk  (l1clk_din),
  .pce_ov(pce_ov),
  .stop(stop)
);


n2_ict_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_in (
        .l2clk  (l2clk),
        .l1en   (1'b1),
        .se     (tcu_se_scancollar_in),
        .l1clk  (l1clk_in),
  .pce_ov(pce_ov),
  .stop(stop)
);

// This clock gates the array and internal logic.
n2_ict_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_free (
        .l2clk  (l2clk),
        .l1en   (ftp_tg_clk_en),
        .se     (tcu_scan_en),
        .l1clk  (l1clk_array),
  .pce_ov(pce_ov),
  .stop(stop)
);


   assign pce_ov = tcu_pce_ov;
   assign stop   = 1'b0;
   assign siclk  = tcu_aclk ;
   assign soclk  = tcu_bclk;
   assign wr_inhibit  = tcu_array_wr_inhibit;


   ///////////////////////
   // Code starts here 
   ///////////////////////
   // assign wr_en_way_0_f = wrreq_f & (wrway_f[2:0] == 3'b000) ;  
   // assign wr_en_way_1_f = wrreq_f & (wrway_f[2:0] == 3'b001) ;  
   // assign wr_en_way_2_f = wrreq_f & (wrway_f[2:0] == 3'b010) ;  
   // assign wr_en_way_3_f = wrreq_f & (wrway_f[2:0] == 3'b011) ;  
   // assign wr_en_way_4_f = wrreq_f & (wrway_f[2:0] == 3'b100) ;  
   // assign wr_en_way_5_f = wrreq_f & (wrway_f[2:0] == 3'b101) ;  
   // assign wr_en_way_6_f = wrreq_f & (wrway_f[2:0] == 3'b110) ;  
   // assign wr_en_way_7_f = wrreq_f & (wrway_f[2:0] == 3'b111) ;  

   //////////////////////////////////////////////////////////
   // 4:8 decode                                           //
   //////////////////////////////////////////////////////////
   n2_ict_sp_1920b_cust_mux_macro__mux_aodec__ports_8__width_8 wr_way_decode    (
        .din0   (8'b00000001),
        .din1   (8'b00000010),
        .din2   (8'b00000100),
        .din3   (8'b00001000),
        .din4   (8'b00010000),
        .din5   (8'b00100000),
        .din6   (8'b01000000),
        .din7   (8'b10000000),
        .sel    (wrway_b[2:0]),
        .dout   (wrway_dec_b[7:0])
   );

n2_ict_sp_1920b_cust_inv_macro__width_1 wr_inhibit_gate   (
    .din(wr_inhibit),
    .dout(wr_inhibit_)
);

n2_ict_sp_1920b_cust_and_macro__ports_3__width_8 wr_en_gate    (
    .din0(wrway_dec_b[7:0]),
    .din1({8{wrreq_b}}),
    .din2({8{wr_inhibit_}}),
    .dout(wr_en_way_b[7:0])
);


assign wr_en_way_f[7:0] = wr_en_way_b[7:0] ;
assign wr_en_unused[7:0] = wr_en_way_f[7:0] ;

   ///////////////////////////////////////////////////////////////
   // Scan chain connections                                    //
   ///////////////////////////////////////////////////////////////
   ///////////////////////////////////////////////////////////////
   // Flop the inputs                                           //
   ///////////////////////////////////////////////////////////////
 n2_ict_sp_1920b_cust_tisram_msff_macro__width_3      wrway_reg                (
  .scan_in(wrway_reg_scanin),
  .scan_out(wrway_reg_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( agc_fill_wrway_bf[2:0]                   ),
  .latout( wrway_b[2:0]                         ),
  .latout_l( wrway_b_unused[2:0]                ),
  .siclk(siclk),
  .soclk(soclk));

 n2_ict_sp_1920b_cust_tisram_msff_macro__width_1      index_reg_i_5              (
  .scan_in(index_reg_i_5_scanin),
  .scan_out(index_reg_i_5_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( agd_ic_index_bf[5]                    ),
  .latout( index_f[5]                        ),
  .latout_l( index_f_l_unused[5]            ),
  .siclk(siclk),
  .soclk(soclk));


 n2_ict_sp_1920b_cust_tisram_msff_macro__width_1      index_reg_i_6              (
  .scan_in(index_reg_i_6_scanin),
  .scan_out(index_reg_i_6_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( agd_ic_index_bf[6]                    ),
  .latout( index_f[6]                        ),
  .latout_l( index_f_l_unused[6]            ),
  .siclk(siclk),
  .soclk(soclk));


 n2_ict_sp_1920b_cust_tisram_msff_macro__width_1      index_reg_i_7              (
  .scan_in(index_reg_i_7_scanin),
  .scan_out(index_reg_i_7_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( agd_ic_index_bf[7]                    ),
  .latout( index_f[7]                        ),
  .latout_l( index_f_l_unused[7]            ),
  .siclk(siclk),
  .soclk(soclk));


 n2_ict_sp_1920b_cust_tisram_msff_macro__width_1      index_reg_i_8              (
  .scan_in(index_reg_i_8_scanin),
  .scan_out(index_reg_i_8_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( agd_ic_index_bf[8]                    ),
  .latout( index_f[8]                        ),
  .latout_l( index_f_l_unused[8]            ),
  .siclk(siclk),
  .soclk(soclk));


 n2_ict_sp_1920b_cust_tisram_msff_macro__width_1      index_reg_i_9              (
  .scan_in(index_reg_i_9_scanin),
  .scan_out(index_reg_i_9_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( agd_ic_index_bf[9]                    ),
  .latout( index_f[9]                        ),
  .latout_l( index_f_l_unused[9]            ),
  .siclk(siclk),
  .soclk(soclk));


 n2_ict_sp_1920b_cust_tisram_msff_macro__width_1      index_reg_i_10              (
  .scan_in(index_reg_i_10_scanin),
  .scan_out(index_reg_i_10_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( agd_ic_index_bf[10]                    ),
  .latout( index_f[10]                        ),
  .latout_l( index_f_l_unused[10]            ),
  .siclk(siclk),
  .soclk(soclk));


 n2_ict_sp_1920b_cust_msff_ctl_macro__width_1      rdreq_reg                (
  .scan_in(rdreq_reg_scanin),
  .scan_out(rdreq_reg_scanout),
  .l1clk ( l1clk_in                             ),
  .din ( ftp_tg_rd_req_bf                         ),
  .dout( rdreq_a                              ),
  .siclk(siclk),
  .soclk(soclk)) ;

assign rdreq_f = rdreq_a ;
assign rdreq_f_unused = rdreq_f ;

 n2_ict_sp_1920b_cust_msff_ctl_macro__width_1      wrreq_reg                (
  .scan_in(wrreq_reg_scanin),
  .scan_out(wrreq_reg_scanout),
  .l1clk ( l1clk_in                             ),
  .din ( ftp_tg_wr_req_bf                         ),
  .dout( wrreq_a                              ),
  .siclk(siclk),
  .soclk(soclk)) ;

 n2_ict_sp_1920b_cust_tisram_msff_macro__width_1      rdreq_reg_dup                (
  .scan_in(rdreq_reg_dup_scanin),
  .scan_out(rdreq_reg_dup_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( ftp_tg_rd_req_bf                         ),
  .latout( rdreq_b                              ),
  .latout_l( rdreq_f_l_dup_unused                     ),
  .siclk(siclk),
  .soclk(soclk));


 n2_ict_sp_1920b_cust_tisram_msff_macro__width_1      wrreq_reg_dup                (
  .scan_in(wrreq_reg_dup_scanin),
  .scan_out(wrreq_reg_dup_scanout),
  .l1clk ( l1clk_in                             ),
  .d ( ftp_tg_wr_req_bf                         ),
  .latout( wrreq_b                              ),
  .latout_l( wrreq_b_                           ),
  .siclk(siclk),
  .soclk(soclk));


n2_ict_sp_1920b_cust_and_macro__ports_3__width_1 read_and   (
        .din0   (rdreq_b),
        .din1   (wrreq_b_),
        .din2   (wr_inhibit_),
        .dout   (rd_en_b)
);


   // write data regsiter

assign wrtag_reg_in[29:0] = {agd_ict_wrtag_bf[0],
                             agd_ict_wrtag_bf[1],
                             agd_ict_wrtag_bf[2],
                             agd_ict_wrtag_bf[3],
                             agd_ict_wrtag_bf[4],
                             agd_ict_wrtag_bf[5],
                             agd_ict_wrtag_bf[6],
                             agd_ict_wrtag_bf[7],
                             agd_ict_wrtag_bf[8],
                             agd_ict_wrtag_bf[9],
                             agd_ict_wrtag_bf[10],
                             agd_ict_wrtag_bf[11],
                             agd_ict_wrtag_bf[12],
                             agd_ict_wrtag_bf[13],
                             agd_ict_wrtag_bf[14],
                             agd_ict_wrtag_bf[15],
                             agd_ict_wrtag_bf[16],
                             agd_ict_wrtag_bf[17],
                             agd_ict_wrtag_bf[18],
                             agd_ict_wrtag_bf[19],
                             agd_ict_wrtag_bf[20],
                             agd_ict_wrtag_bf[21],
                             agd_ict_wrtag_bf[22],
                             agd_ict_wrtag_bf[23],
                             agd_ict_wrtag_bf[24],
                             agd_ict_wrtag_bf[25],
                             agd_ict_wrtag_bf[26],
                             agd_ict_wrtag_bf[27],
                             agd_ict_wrtag_bf[28],
                             agd_ict_wrtag_bf[29]} ;

n2_ict_sp_1920b_cust_msffi_ctl_macro__width_30	wrtag_reg    (
  .scan_in(wrtag_reg_scanin),
  .scan_out(wrtag_reg_scanout),
  .l1clk(l1clk_din),
  .din(wrtag_reg_in[29:0]),
  .q_l (wrtag_reg_out[29:0]				),
  .siclk(siclk),
  .soclk(soclk));

assign ic_wrtag_f_l[29:0] = {wrtag_reg_out[0],
                             wrtag_reg_out[1],
                             wrtag_reg_out[2],
                             wrtag_reg_out[3],
                             wrtag_reg_out[4],
                             wrtag_reg_out[5],
                             wrtag_reg_out[6],
                             wrtag_reg_out[7],
                             wrtag_reg_out[8],
                             wrtag_reg_out[9],
                             wrtag_reg_out[10],
                             wrtag_reg_out[11],
                             wrtag_reg_out[12],
                             wrtag_reg_out[13],
                             wrtag_reg_out[14],
                             wrtag_reg_out[15],
                             wrtag_reg_out[16],
                             wrtag_reg_out[17],
                             wrtag_reg_out[18],
                             wrtag_reg_out[19],
                             wrtag_reg_out[20],
                             wrtag_reg_out[21],
                             wrtag_reg_out[22],
                             wrtag_reg_out[23],
                             wrtag_reg_out[24],
                             wrtag_reg_out[25],
                             wrtag_reg_out[26],
                             wrtag_reg_out[27],
                             wrtag_reg_out[28],
                             wrtag_reg_out[29]} ;

n2_ict_sp_1920b_cust_inv_macro__width_30 data_inv  (
    .din(ic_wrtag_f_l[29:0]),
    .dout(ic_wrtag_f[29:0]) ) ;

/////////////////////////////////////////////////////////////////
// Instantiate each TAG way ARRAY.                             //
/////////////////////////////////////////////////////////////////
// WAY 0               ///////
//////////////////////////////
n2_ict_sp_1920b_array tag_way_0 (.addr(index_f[10:5]),        // comes on negedge
                                .rd_en_b(rd_en_b),            // comes on negedge
                                .wr_en_w_b(wr_en_way_b[0]),   // comes on negedge
                                .rd_en_a(rdreq_a),            // comes on posedge
                                .wrreq_a(wrreq_a),            // comes on posedge
                                .din(ic_wrtag_f[29:0]),
                                .dout(ict_itlb_way_0_tag_f[29:0]),
                                .clk(l1clk_array),
  .wr_inhibit(wr_inhibit)
                              );


//////////////////////////////
// WAY 1               ///////
//////////////////////////////
n2_ict_sp_1920b_array tag_way_1  (.addr(index_f[10:5]),
                                .rd_en_b(rd_en_b),            // comes on negedge
                                .wr_en_w_b(wr_en_way_b[1]),   // comes on negedge
                                .rd_en_a(rdreq_a),            // comes on posedge
                                .wrreq_a(wrreq_a),            // comes on posedge
                                .wr_inhibit(wr_inhibit),
                                .din(ic_wrtag_f[29:0]),
                                .dout(ict_itlb_way_1_tag_f[29:0]),
                                .clk(l1clk_array)
                              );
//////////////////////////////
// WAY 2               ///////
//////////////////////////////
n2_ict_sp_1920b_array tag_way_2  (.addr(index_f[10:5]),
                                .rd_en_b(rd_en_b),            // comes on negedge
                                .wr_en_w_b(wr_en_way_b[2]),   // comes on negedge
                                .rd_en_a(rdreq_a),            // comes on posedge
                                .wrreq_a(wrreq_a),            // comes on posedge
                                .wr_inhibit(wr_inhibit),
                                .din(ic_wrtag_f[29:0]),
                                .dout(ict_itlb_way_2_tag_f[29:0]),
                                .clk(l1clk_array)
                              );
//////////////////////////////
// WAY 3               ///////
//////////////////////////////
n2_ict_sp_1920b_array tag_way_3  (.addr(index_f[10:5]),
                                .rd_en_b(rd_en_b),            // comes on negedge
                                .wr_en_w_b(wr_en_way_b[3]),   // comes on negedge
                                .rd_en_a(rdreq_a),            // comes on posedge
                                .wrreq_a(wrreq_a),            // comes on posedge
                                .wr_inhibit(wr_inhibit),
                                .din(ic_wrtag_f[29:0]),
                                .dout(ict_itlb_way_3_tag_f[29:0]),
                                .clk(l1clk_array)
                              );
//////////////////////////////
// WAY 4               ///////
//////////////////////////////
n2_ict_sp_1920b_array tag_way_4  (.addr(index_f[10:5]),
                                .rd_en_b(rd_en_b),            // comes on negedge
                                .wr_en_w_b(wr_en_way_b[4]),   // comes on negedge
                                .rd_en_a(rdreq_a),            // comes on posedge
                                .wrreq_a(wrreq_a),            // comes on posedge
                                .wr_inhibit(wr_inhibit),
                                .din(ic_wrtag_f[29:0]),
                                .dout(ict_itlb_way_4_tag_f[29:0]),
                                .clk(l1clk_array)
                              );
//////////////////////////////
// WAY 5               ///////
//////////////////////////////
n2_ict_sp_1920b_array tag_way_5  (.addr(index_f[10:5]),
                                .rd_en_b(rd_en_b),            // comes on negedge
                                .wr_en_w_b(wr_en_way_b[5]),   // comes on negedge
                                .rd_en_a(rdreq_a),            // comes on posedge
                                .wrreq_a(wrreq_a),            // comes on posedge
                                .wr_inhibit(wr_inhibit),
                                .din(ic_wrtag_f[29:0]),
                                .dout(ict_itlb_way_5_tag_f[29:0]),
                                .clk(l1clk_array)
                              );
//////////////////////////////
// WAY 6               ///////
//////////////////////////////
n2_ict_sp_1920b_array tag_way_6  (.addr(index_f[10:5]),
                                .rd_en_b(rd_en_b),            // comes on negedge
                                .wr_en_w_b(wr_en_way_b[6]),   // comes on negedge
                                .rd_en_a(rdreq_a),            // comes on posedge
                                .wrreq_a(wrreq_a),            // comes on posedge
                                .wr_inhibit(wr_inhibit),
                                .din(ic_wrtag_f[29:0]),
                                .dout(ict_itlb_way_6_tag_f[29:0]),
                                .clk(l1clk_array)
                              );
//////////////////////////////
// WAY 7               ///////
//////////////////////////////
n2_ict_sp_1920b_array tag_way_7  (.addr(index_f[10:5]),
                                .rd_en_b(rd_en_b),            // comes on negedge
                                .wr_en_w_b(wr_en_way_b[7]),   // comes on negedge
                                .rd_en_a(rdreq_a),            // comes on posedge
                                .wrreq_a(wrreq_a),            // comes on posedge
                                .wr_inhibit(wr_inhibit),
                                .din(ic_wrtag_f[29:0]),
                                .dout(ict_itlb_way_7_tag_f[29:0]),
                                .clk(l1clk_array)
                              );
supply0 vss;
supply1 vdd;

// scan_in                  ->
// agc_fill_wrway_bf<2>     - 43th
// agc_fill_wrway_bf<1>     - 42th
// agc_fill_wrway_bf<0>     - 41th
// agd_ic_index_bf<5>       - 40th
// agd_ic_index_bf<6>       - 39th
// agd_ic_index_bf<7>       - 38th
// agd_ic_index_bf<8>       - 37th
// agd_ic_index_bf<9>       - 36th
// agd_ic_index_bf<10>      - 35th
// ftp_tg_rd_req_bf         - 34th
// ftp_tg_wr_req_bf         - 33th
// ftp_tg_rd_req_bf         - 32th
// ftp_tg_wr_req_bf         - 31th
// agd_ict_wrtag_bf<0>      - 30th
// agd_ict_wrtag_bf<1>      - 29th
// .....            ..      - ..
// agd_ict_wrtag_bf<27>     - 3rd
// agd_ict_wrtag_bf<28>     - 2nd
// agd_ict_wrtag_bf<29>     - 1st
// scan_out


// fixscan start:
assign wrway_reg_scanin          = scan_in                  ;
assign index_reg_i_5_scanin      = wrway_reg_scanout        ;
assign index_reg_i_6_scanin      = index_reg_i_5_scanout    ;
assign index_reg_i_7_scanin      = index_reg_i_6_scanout    ;
assign index_reg_i_8_scanin      = index_reg_i_7_scanout    ;
assign index_reg_i_9_scanin      = index_reg_i_8_scanout    ;
assign index_reg_i_10_scanin     = index_reg_i_9_scanout    ;
assign rdreq_reg_scanin          = index_reg_i_10_scanout   ;
assign wrreq_reg_scanin          = rdreq_reg_scanout        ;
assign rdreq_reg_dup_scanin      = wrreq_reg_scanout        ;
assign wrreq_reg_dup_scanin      = rdreq_reg_dup_scanout    ;
assign wrtag_reg_scanin          = wrreq_reg_dup_scanout    ;
assign scan_out                  = wrtag_reg_scanout        ;
// fixscan end:

`ifndef FPGA
// synopsys translate_on
`endif

endmodule // sparc_ifu_ict


// any PARAMS parms go into naming of macro

module n2_ict_sp_1920b_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_ict_sp_1920b_cust_mux_macro__mux_aodec__ports_8__width_8 (
  din0, 
  din1, 
  din2, 
  din3, 
  din4, 
  din5, 
  din6, 
  din7, 
  sel, 
  dout);
wire psel0;
wire psel1;
wire psel2;
wire psel3;
wire psel4;
wire psel5;
wire psel6;
wire psel7;

  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  input [7:0] din3;
  input [7:0] din4;
  input [7:0] din5;
  input [7:0] din6;
  input [7:0] din7;
  input [2:0] sel;
  output [7:0] dout;


cl_dp1_pdec8_8x  c0_0 (
  .test(1'b1),
 .sel0(sel[0]),
 .sel1(sel[1]),
 .sel2(sel[2]),
 .psel0(psel0),
 .psel1(psel1),
 .psel2(psel2),
 .psel3(psel3),
 .psel4(psel4),
 .psel5(psel5),
 .psel6(psel6),
 .psel7(psel7)
);

mux8s #(8)  d0_0 (
  .sel0(psel0),
  .sel1(psel1),
  .sel2(psel2),
  .sel3(psel3),
  .sel4(psel4),
  .sel5(psel5),
  .sel6(psel6),
  .sel7(psel7),
  .in0(din0[7:0]),
  .in1(din1[7:0]),
  .in2(din2[7:0]),
  .in3(din3[7:0]),
  .in4(din4[7:0]),
  .in5(din5[7:0]),
  .in6(din6[7:0]),
  .in7(din7[7:0]),
.dout(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module n2_ict_sp_1920b_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_ict_sp_1920b_cust_and_macro__ports_3__width_8 (
  din0, 
  din1, 
  din2, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  input [7:0] din2;
  output [7:0] dout;


and3 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.in2(din2[7:0]),
.out(dout[7:0])
);


endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_ict_sp_1920b_cust_tisram_msff_macro__width_3 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
wire [1:0] so;

input [2:0] d;
  input scan_in;
input l1clk;
input siclk;
input soclk;
  output scan_out;
output [2:0] latout;
output [2:0] latout_l;


tisram_msff #(3)  d0_0 (
.d(d[2:0]),
.si({scan_in,so[1:0]}),
.so({so[1:0],scan_out}),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[2:0]),
.latout_l(latout_l[2:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_tisram_msff_{16,8}x flops
//
//


module n2_ict_sp_1920b_cust_tisram_msff_macro__width_1 (
  d, 
  scan_in, 
  l1clk, 
  siclk, 
  soclk, 
  scan_out, 
  latout, 
  latout_l);
input [0:0] d;
  input scan_in;
input l1clk;
input siclk;
input soclk;
  output scan_out;
output [0:0] latout;
output [0:0] latout_l;


tisram_msff #(1)  d0_0 (
.d(d[0:0]),
.si(scan_in),
.so(scan_out),
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.latout(latout[0:0]),
.latout_l(latout_l[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_ict_sp_1920b_cust_msff_ctl_macro__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_ict_sp_1920b_cust_and_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


and3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_ict_sp_1920b_cust_msffi_ctl_macro__width_30 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  q_l, 
  scan_out);
wire [28:0] so;

  input [29:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [29:0] q_l;
  output scan_out;


msffi #(30)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(din[29:0]),
.si({scan_in,so[28:0]}),
.so({so[28:0],scan_out}),
.q_l(q_l[29:0])
);


endmodule


//
//   invert macro
//
//


module n2_ict_sp_1920b_cust_inv_macro__width_30 (
  din, 
  dout);
  input [29:0] din;
  output [29:0] dout;


inv #(30)  d0_0 (
.in(din[29:0]),
.out(dout[29:0])
);


endmodule


module n2_ict_sp_1920b_array (
  clk, 
  rd_en_b, 
  wr_en_w_b, 
  rd_en_a, 
  wrreq_a, 
  addr, 
  wr_inhibit, 
  din, 
  dout);
wire rd_en_b_unused;


`define WIDTH 30
`define ENTRIES 64
`define ADDRBITS 6


input			clk;
input	     		rd_en_b;	// comes on negedge
input	     		wr_en_w_b;	// comes on negedge (way specific)
input	     		rd_en_a;	// comes on posedge
input	     		wrreq_a;	// comes on posedge (not way specific)
input	[`ADDRBITS-1:0]	addr;		// comes on negedge
input			wr_inhibit;	// async

input	[`WIDTH-1:0]	din;		// comes on posedge
output	[`WIDTH-1:0]	dout;


reg	[`WIDTH-1:0]	mem[`ENTRIES-1:0];
reg	[`WIDTH-1:0]	local_dout;

assign rd_en_b_unused = rd_en_b;

`ifndef NOINITMEM
// Emulate reset
integer i;
initial begin
  for (i=0; i<`ENTRIES; i=i+1) begin
    mem[i] = {`WIDTH{1'b0}}; 
  end
  local_dout = {`WIDTH{1'b0}};
end
`endif

//////////////////////
// Read/write array
//////////////////////

always @(negedge clk) begin
    if (wr_en_w_b) begin
        mem[addr] <= din;


    end
end

// always @(clk or rd_en_a or wr_en_a or addr) begin
//    if (clk) begin
//      if (rd_en_a) begin
//          if (wr_en_a)
//              local_dout[`WIDTH-1:0] = `WIDTH'hx;
//          else    
//              local_dout[`WIDTH-1:0] = mem[addr] ;
//      end
//      else
//          local_dout[`WIDTH-1:0] = `WIDTH'h0;
// end

 always @(posedge clk) begin
  if (rd_en_b)
     local_dout[`WIDTH-1:0] <= mem[addr];
  else
     local_dout[`WIDTH-1:0] <= `WIDTH'h0;
 end

assign dout[`WIDTH-1:0] = local_dout[`WIDTH-1:0] & {`WIDTH{rd_en_a & ~wrreq_a & ~wr_inhibit}};

supply0 vss;
supply1 vdd;


endmodule

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: n2_l2d_sp_512kb_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module n2_l2d_sp_512kb_cust (
  l2t_l2d_way_sel_c2, 
  l2t_l2d_col_offset_c2, 
  l2t_l2d_fb_hit_c3, 
  l2t_l2d_fbrd_c3, 
  l2t_l2d_rd_wr_c2, 
  l2t_l2d_set_c2, 
  l2t_l2d_word_en_c2, 
  l2t_l2d_stdecc_c2, 
  l2b_l2d_fbdecc_c4, 
  rst_wmr_protect, 
  rst_wmr_, 
  rst_por_, 
  vnw_ary0, 
  vnw_ary1, 
  l2d_l2b_decc_out_c7, 
  l2d_l2t_decc_c6, 
  gclk, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  tcu_pce_ov, 
  tcu_ce, 
  tcu_clk_stop, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  tcu_array_wr_inhibit, 
  tcu_atpg_mode, 
  scan_in, 
  scan_out, 
  l2d_l2b_efc_fuse_data, 
  l2b_l2d_fuse_l2d_data_in, 
  l2b_l2d_fuse_rid, 
  l2b_l2d_fuse_reset, 
  l2b_l2d_fuse_l2d_wren, 
  l2b_l2d_en_fill_clk_v0, 
  l2b_l2d_en_fill_clk_v1, 
  l2t_l2d_en_fill_clk_ov, 
  l2t_l2d_pwrsav_ov) ;
wire [155:0] l2d_l2t_decc_c52_mux;
wire [623:0] l2d_decc_out_c6;
wire l2clk;
wire siclk_peri;
wire soclk_peri;
wire pce_ov_peri;
wire pce_peri;
wire clk_stop_peri;
wire l2t_l2d_pwrsav_ov_stg;
wire cache_col_offset_all_c7;
wire wr_inhibit_peri;
wire perif_io_scanin;
wire perif_io_scanout;
wire scan_collarin_peri;
wire scan_collarout_peri;
wire [9:0] l2b_l2d_fuse_l2d_data_in_d;
wire [6:0] l2b_l2d_fuse_rid_d;
wire l2b_l2d_fuse_reset_d_l;
wire l2b_l2d_fuse_l2d_wren_d;
wire [623:0] l2b_l2d_fbdecc_c5;
wire [15:0] l2t_l2d_way_sel_c3;
wire wayerr_c3;
wire l2t_l2d_rd_wr_c3;
wire [15:0] cache_way_sel_c3_30;
wire cache_wayerr_c3_30;
wire [8:0] cache_set_c3_30;
wire cache_col_offset_c3_30;
wire cache_col_offset_c4_l_30;
wire [1:0] cache_col_offset_c5_30;
wire cache_rd_wr_c3_30;
wire cache_readen_c5_30;
wire [3:0] cache_word_en_c3_30;
wire tcu_pce_ov_30;
wire tcu_pce_30;
wire tcu_clk_stop_30;
wire se_30;
wire wee_l_q30;
wire [623:0] cache_decc_in_c3b_l;
wire [623:0] cache_decc_out_c5b;
wire [9:0] fuse_l2d_data_in_030;
wire [4:0] fuse_l2d_rid_030;
wire fuse_l2d_wren_030;
wire fuse_l2d_reset_030_l;
wire [9:0] fdout_030;
wire [9:0] fuse_l2d_data_in_130;
wire [4:0] fuse_l2d_rid_130;
wire fuse_l2d_wren_130;
wire fuse_l2d_reset_130_l;
wire [9:0] fdout_130;
wire [9:0] fuse_l2d_data_in_031;
wire [4:0] fuse_l2d_rid_031;
wire fuse_l2d_wren_031;
wire fuse_l2d_reset_031_l;
wire [9:0] fdout_031;
wire [9:0] fuse_l2d_data_in_131;
wire [4:0] fuse_l2d_rid_131;
wire fuse_l2d_wren_131;
wire fuse_l2d_reset_131_l;
wire [9:0] fdout_131;
wire [15:0] cache_way_sel_c3_31;
wire cache_wayerr_c3_31;
wire [8:0] cache_set_c3_31;
wire cache_col_offset_c3_31;
wire cache_col_offset_c4_l_31;
wire [1:0] cache_col_offset_c5_31;
wire cache_rd_wr_c3_31;
wire cache_readen_c5_31;
wire [3:0] cache_word_en_c3_31;
wire tcu_pce_ov_31;
wire tcu_pce_31;
wire tcu_clk_stop_31;
wire se_31;
wire wee_l_q31;
wire tstmodclk_30_l;
wire tstmodclk_31_l;
wire [15:0] cache_way_sel_c3_10;
wire cache_wayerr_c3_10;
wire [8:0] cache_set_c3_10;
wire cache_col_offset_c3_10;
wire cache_col_offset_c4_l_10;
wire [1:0] cache_col_offset_c5_10;
wire cache_rd_wr_c3_10;
wire cache_readen_c5_10;
wire [3:0] cache_word_en_c3_10;
wire tcu_pce_ov_10;
wire tcu_pce_10;
wire tcu_clk_stop_10;
wire se_10;
wire wee_l_q10;
wire [9:0] fuse_l2d_data_in_010;
wire [4:0] fuse_l2d_rid_010;
wire fuse_l2d_wren_010;
wire fuse_l2d_reset_010_l;
wire [9:0] fdout_010;
wire [9:0] fuse_l2d_data_in_110;
wire [4:0] fuse_l2d_rid_110;
wire fuse_l2d_wren_110;
wire fuse_l2d_reset_110_l;
wire [9:0] fdout_110;
wire [9:0] fuse_l2d_data_in_011;
wire [4:0] fuse_l2d_rid_011;
wire fuse_l2d_wren_011;
wire fuse_l2d_reset_011_l;
wire [9:0] fdout_011;
wire [9:0] fuse_l2d_data_in_111;
wire [4:0] fuse_l2d_rid_111;
wire fuse_l2d_wren_111;
wire fuse_l2d_reset_111_l;
wire [9:0] fdout_111;
wire [15:0] cache_way_sel_c3_11;
wire cache_wayerr_c3_11;
wire [8:0] cache_set_c3_11;
wire cache_col_offset_c3_11;
wire cache_col_offset_c4_l_11;
wire [1:0] cache_col_offset_c5_11;
wire cache_rd_wr_c3_11;
wire cache_readen_c5_11;
wire [3:0] cache_word_en_c3_11;
wire tcu_pce_ov_11;
wire tcu_pce_11;
wire tcu_clk_stop_11;
wire se_11;
wire wee_l_q11;
wire tstmodclk_10_l;
wire tstmodclk_11_l;
wire [15:0] cache_way_sel_c3_20;
wire cache_wayerr_c3_20;
wire [8:0] cache_set_c3_20;
wire cache_col_offset_c3_20;
wire cache_col_offset_c4_l_20;
wire [1:0] cache_col_offset_c5_20;
wire cache_rd_wr_c3_20;
wire cache_readen_c5_20;
wire [3:0] cache_word_en_c3_20;
wire tcu_pce_ov_20;
wire tcu_pce_20;
wire tcu_clk_stop_20;
wire se_20;
wire wee_l_q20;
wire [9:0] fuse_l2d_data_in_020;
wire [4:0] fuse_l2d_rid_020;
wire fuse_l2d_wren_020;
wire fuse_l2d_reset_020_l;
wire [9:0] fdout_020;
wire [9:0] fuse_l2d_data_in_120;
wire [4:0] fuse_l2d_rid_120;
wire fuse_l2d_wren_120;
wire fuse_l2d_reset_120_l;
wire [9:0] fdout_120;
wire [9:0] fuse_l2d_data_in_021;
wire [4:0] fuse_l2d_rid_021;
wire fuse_l2d_wren_021;
wire fuse_l2d_reset_021_l;
wire [9:0] fdout_021;
wire [9:0] fuse_l2d_data_in_121;
wire [4:0] fuse_l2d_rid_121;
wire fuse_l2d_wren_121;
wire fuse_l2d_reset_121_l;
wire [9:0] fdout_121;
wire [15:0] cache_way_sel_c3_21;
wire cache_wayerr_c3_21;
wire [8:0] cache_set_c3_21;
wire cache_col_offset_c3_21;
wire cache_col_offset_c4_l_21;
wire [1:0] cache_col_offset_c5_21;
wire cache_rd_wr_c3_21;
wire cache_readen_c5_21;
wire [3:0] cache_word_en_c3_21;
wire tcu_pce_ov_21;
wire tcu_pce_21;
wire tcu_clk_stop_21;
wire se_21;
wire wee_l_q21;
wire tstmodclk_20_l;
wire tstmodclk_21_l;
wire [15:0] cache_way_sel_c3_00;
wire cache_wayerr_c3_00;
wire [8:0] cache_set_c3_00;
wire cache_col_offset_c3_00;
wire cache_col_offset_c4_l_00;
wire [1:0] cache_col_offset_c5_00;
wire cache_rd_wr_c3_00;
wire cache_readen_c5_00;
wire [3:0] cache_word_en_c3_00;
wire tcu_pce_ov_00;
wire tcu_pce_00;
wire tcu_clk_stop_00;
wire se_00;
wire wee_l_q00;
wire [9:0] fuse_l2d_data_in_000;
wire [4:0] fuse_l2d_rid_000;
wire fuse_l2d_wren_000;
wire fuse_l2d_reset_000_l;
wire [9:0] fdout_000;
wire [9:0] fuse_l2d_data_in_100;
wire [4:0] fuse_l2d_rid_100;
wire fuse_l2d_wren_100;
wire fuse_l2d_reset_100_l;
wire [9:0] fdout_100;
wire [9:0] fuse_l2d_data_in_001;
wire [4:0] fuse_l2d_rid_001;
wire fuse_l2d_wren_001;
wire fuse_l2d_reset_001_l;
wire [9:0] fdout_001;
wire [9:0] fuse_l2d_data_in_101;
wire [4:0] fuse_l2d_rid_101;
wire fuse_l2d_wren_101;
wire fuse_l2d_reset_101_l;
wire [9:0] fdout_101;
wire [15:0] cache_way_sel_c3_01;
wire cache_wayerr_c3_01;
wire [8:0] cache_set_c3_01;
wire cache_col_offset_c3_01;
wire cache_col_offset_c4_l_01;
wire [1:0] cache_col_offset_c5_01;
wire cache_rd_wr_c3_01;
wire cache_readen_c5_01;
wire [3:0] cache_word_en_c3_01;
wire tcu_pce_ov_01;
wire tcu_pce_01;
wire tcu_clk_stop_01;
wire se_01;
wire wee_l_q01;
wire tstmodclk_00_l;
wire tstmodclk_01_l;
wire ctrlio_cust_scanin;
wire ctrlio_cust_scanout;
wire array_wr_inhibit;
wire [9:0] efc_fuse_data;
wire aclk_clsrhdr;
wire bclk_clsrhdr;
wire scan_en_clsrhdr;
wire rst_wmr_protect_unused;
wire rst_wmr_unused;
wire rst_por_unused;
wire [8:0] l2d_clk_header_unused;
wire clstr_hdr_scanout;
wire clstr_hdr_scanin;
wire cclk;


input [15:0]  	l2t_l2d_way_sel_c2;
input [3:0]     l2t_l2d_col_offset_c2;  
input           l2t_l2d_fb_hit_c3;      
input           l2t_l2d_fbrd_c3;        
input           l2t_l2d_rd_wr_c2;       
input [8:0]     l2t_l2d_set_c2;         
input [15:0]    l2t_l2d_word_en_c2;     
input [77:0]    l2t_l2d_stdecc_c2;      
input [623:0] 	l2b_l2d_fbdecc_c4;
input           rst_wmr_protect;
input           rst_wmr_;
input           rst_por_;
//input           l2clk;
input           vnw_ary0;
input           vnw_ary1;


output [623:0]  l2d_l2b_decc_out_c7;	
output [155:0]  l2d_l2t_decc_c6;   

input           gclk;
input           tcu_aclk;
input           tcu_bclk;
input           tcu_scan_en;
input           tcu_pce_ov;
input           tcu_ce;
input           tcu_clk_stop;
input   	tcu_se_scancollar_in;
input   	tcu_se_scancollar_out;
input   	tcu_array_wr_inhibit;
input   	tcu_atpg_mode;
input           scan_in;
output          scan_out;

output  [9:0]   l2d_l2b_efc_fuse_data;    
input   [9:0]   l2b_l2d_fuse_l2d_data_in;      
input   [6:0]   l2b_l2d_fuse_rid;      
input           l2b_l2d_fuse_reset;      
input           l2b_l2d_fuse_l2d_wren;    


// power save signals

input		l2b_l2d_en_fill_clk_v0;
input		l2b_l2d_en_fill_clk_v1;
input		l2t_l2d_en_fill_clk_ov;
input		l2t_l2d_pwrsav_ov; 


n2_l2d_perf_io_cust     perif_io
(
.l2d_l2t_decc_c52_mux        (l2d_l2t_decc_c52_mux[155:0]),
.l2d_l2t_decc_c6             (l2d_l2t_decc_c6[155:0]),
.l2d_decc_out_c6             (l2d_decc_out_c6[623:0]),
.l2b_l2d_fbdecc_c4           (l2b_l2d_fbdecc_c4[623:0]),
.l2t_l2d_way_sel_c2          (l2t_l2d_way_sel_c2[15:0]),
.l2clk                       (l2clk),
.tcu_aclk                    (siclk_peri),
.tcu_bclk                    (soclk_peri),
.tcu_pce_ov                  (pce_ov_peri),
.tcu_ce                      (pce_peri),
.tcu_clk_stop                (clk_stop_peri),
.l2b_l2d_en_fill_clk_v0      (l2b_l2d_en_fill_clk_v0),
.l2b_l2d_en_fill_clk_v1      (l2b_l2d_en_fill_clk_v1),
.l2t_l2d_en_fill_clk_ov      (l2t_l2d_en_fill_clk_ov),
.l2t_l2d_pwrsav_ov           (l2t_l2d_pwrsav_ov),
.l2t_l2d_pwrsav_ov_stg       (l2t_l2d_pwrsav_ov_stg),
.cache_col_offset_all_c7     (cache_col_offset_all_c7),
.wr_inhibit                  (wr_inhibit_peri),
.scan_in                     (perif_io_scanin),
.scan_out                    (perif_io_scanout),
.tcu_se_scancollar_in        (scan_collarin_peri),
.tcu_se_scancollar_out       (scan_collarout_peri),
.l2b_l2d_fuse_l2d_data_in    (l2b_l2d_fuse_l2d_data_in[9:0]),
.l2b_l2d_fuse_rid            (l2b_l2d_fuse_rid[6:0]),
.l2b_l2d_fuse_reset          (l2b_l2d_fuse_reset),
.l2b_l2d_fuse_l2d_wren       (l2b_l2d_fuse_l2d_wren),
.l2d_l2b_efc_fuse_data       (l2d_l2b_efc_fuse_data[9:0]),
.l2b_l2d_fuse_l2d_data_in_d  (l2b_l2d_fuse_l2d_data_in_d[9:0]),
.l2b_l2d_fuse_rid_d          (l2b_l2d_fuse_rid_d[6:0]),
.l2b_l2d_fuse_reset_d_l      (l2b_l2d_fuse_reset_d_l),
.l2b_l2d_fuse_l2d_wren_d     (l2b_l2d_fuse_l2d_wren_d),
.l2d_l2b_decc_out_c7         (l2d_l2b_decc_out_c7[623:0]),
.l2b_l2d_fbdecc_c5           (l2b_l2d_fbdecc_c5[623:0]),
.l2t_l2d_way_sel_c3          (l2t_l2d_way_sel_c3[15:0]),
.wayerr_c3                   (wayerr_c3),
.l2t_l2d_rd_wr_c2            (l2t_l2d_rd_wr_c2),
.l2t_l2d_rd_wr_c3            (l2t_l2d_rd_wr_c3),
  .efc_fuse_data(efc_fuse_data[9:0])
);


n2_l2d_quad_cust	quad_top_left // 31 to left and 30 to right
(
.waysel_c3_0		(cache_way_sel_c3_30[15:0]),
.wayerr_c3_0        (cache_wayerr_c3_30),
.set_c3_0               (cache_set_c3_30[8:0]),
.coloff_c3_0            (cache_col_offset_c3_30),
.coloff_c4_l_0          (cache_col_offset_c4_l_30),
.coloff_c5_0            (cache_col_offset_c5_30[1:0]),
.rd_wr_c3_0             (cache_rd_wr_c3_30),
.readen_c5_0            (cache_readen_c5_30),
.worden_c3_0            (cache_word_en_c3_30[3:0]),
.l2clk                  (l2clk),
.tcu_pce_ov_0           (tcu_pce_ov_30),
.pce_0                  (tcu_pce_30),
.tcu_clk_stop_0         (tcu_clk_stop_30),
.se_0			(se_30),
.wee_l_0                (wee_l_q30),	//NEW
.wrdlo0_b_l		(cache_decc_in_c3b_l[233:195]), // write
.wrdhi0_b_l		(cache_decc_in_c3b_l[311:273]),
.wrdlo1_b_l		(cache_decc_in_c3b_l[545:507]),
.wrdhi1_b_l		(cache_decc_in_c3b_l[623:585]),
.ldoutlo0_b		(cache_decc_out_c5b[233:195]), // read
.ldouthi0_b		(cache_decc_out_c5b[311:273]),
.ldoutlo1_b		(cache_decc_out_c5b[545:507]),
.ldouthi1_b		(cache_decc_out_c5b[623:585]),
/////////
.fuse_l2d_data_in_00    (fuse_l2d_data_in_030[9:0]       ),
.fuse_l2d_rid_00        (fuse_l2d_rid_030[4:0]   ),
.fuse_l2d_wren_00       (fuse_l2d_wren_030       ),
.fuse_l2d_reset_00_l    (fuse_l2d_reset_030_l     ),
.fdout_00               (fdout_030[9:0]  ),
.fuse_l2d_data_in_01    (fuse_l2d_data_in_130[9:0]       ),
.fuse_l2d_rid_01        (fuse_l2d_rid_130[4:0]   ),
.fuse_l2d_wren_01       (fuse_l2d_wren_130       ),
.fuse_l2d_reset_01_l    (fuse_l2d_reset_130_l     ),
.fdout_01               (fdout_130[9:0]  ),
.fuse_l2d_data_in_10    (fuse_l2d_data_in_031[9:0]       ),
.fuse_l2d_rid_10        (fuse_l2d_rid_031[4:0]   ),
.fuse_l2d_wren_10       (fuse_l2d_wren_031       ),
.fuse_l2d_reset_10_l    (fuse_l2d_reset_031_l     ),
.fdout_10               (fdout_031[9:0]  ),
.fuse_l2d_data_in_11    (fuse_l2d_data_in_131[9:0]       ),
.fuse_l2d_rid_11        (fuse_l2d_rid_131[4:0]   ),
.fuse_l2d_wren_11       (fuse_l2d_wren_131       ),
.fuse_l2d_reset_11_l    (fuse_l2d_reset_131_l     ),
.fdout_11               (fdout_131[9:0]  ),
/////////
.waysel_c3_1            (cache_way_sel_c3_31[15:0]),
.wayerr_c3_1        (cache_wayerr_c3_31),
.set_c3_1               (cache_set_c3_31[8:0]),        
.coloff_c3_1            (cache_col_offset_c3_31),
.coloff_c4_l_1          (cache_col_offset_c4_l_31),
.coloff_c5_1            (cache_col_offset_c5_31[1:0]),
.rd_wr_c3_1             (cache_rd_wr_c3_31),
.readen_c5_1            (cache_readen_c5_31),
.worden_c3_1            (cache_word_en_c3_31[3:0]),
.tcu_pce_ov_1           (tcu_pce_ov_31),
.pce_1                  (tcu_pce_31),
.tcu_clk_stop_1         (tcu_clk_stop_31),
.se_1			(se_31),
.wee_l_1                (wee_l_q31),	//NEW
.tstmodclk_l_0		(tstmodclk_30_l),
.tstmodclk_l_1		(tstmodclk_31_l),
.vnw_ary                (vnw_ary1)
);


n2_l2d_quad_cust        quad_top_right 
	(
.waysel_c3_0            (cache_way_sel_c3_10[15:0]),
.wayerr_c3_0        (cache_wayerr_c3_10),
.set_c3_0               (cache_set_c3_10[8:0]),
.coloff_c3_0            (cache_col_offset_c3_10),
.coloff_c4_l_0          (cache_col_offset_c4_l_10),
.coloff_c5_0            (cache_col_offset_c5_10[1:0]),
.rd_wr_c3_0             (cache_rd_wr_c3_10),
.readen_c5_0            (cache_readen_c5_10),
.worden_c3_0            (cache_word_en_c3_10[3:0]),
.l2clk                  (l2clk),
.tcu_pce_ov_0           (tcu_pce_ov_10),
.pce_0                  (tcu_pce_10),
.tcu_clk_stop_0         (tcu_clk_stop_10),
.se_0			(se_10),
.wee_l_0                (wee_l_q10),	//NEW
.wrdlo0_b_l		(cache_decc_in_c3b_l[194:156]),
.wrdhi0_b_l		(cache_decc_in_c3b_l[272:234]),
.wrdlo1_b_l		(cache_decc_in_c3b_l[506:468]),
.wrdhi1_b_l		(cache_decc_in_c3b_l[584:546]),
.ldoutlo0_b		(cache_decc_out_c5b[194:156]),
.ldouthi0_b		(cache_decc_out_c5b[272:234]),
.ldoutlo1_b		(cache_decc_out_c5b[506:468]),
.ldouthi1_b		(cache_decc_out_c5b[584:546]),
////////////
.fuse_l2d_data_in_00    (fuse_l2d_data_in_010[9:0]       ),
.fuse_l2d_rid_00        (fuse_l2d_rid_010[4:0]   ),
.fuse_l2d_wren_00       (fuse_l2d_wren_010       ),
.fuse_l2d_reset_00_l    (fuse_l2d_reset_010_l     ),
.fdout_00               (fdout_010[9:0]  ),
.fuse_l2d_data_in_01    (fuse_l2d_data_in_110[9:0]       ),
.fuse_l2d_rid_01        (fuse_l2d_rid_110[4:0]   ),
.fuse_l2d_wren_01       (fuse_l2d_wren_110       ),
.fuse_l2d_reset_01_l    (fuse_l2d_reset_110_l     ),
.fdout_01               (fdout_110[9:0]  ),
.fuse_l2d_data_in_10    (fuse_l2d_data_in_011[9:0]       ),
.fuse_l2d_rid_10        (fuse_l2d_rid_011[4:0]   ),
.fuse_l2d_wren_10       (fuse_l2d_wren_011       ),
.fuse_l2d_reset_10_l    (fuse_l2d_reset_011_l     ),
.fdout_10               (fdout_011[9:0]  ),
.fuse_l2d_data_in_11    (fuse_l2d_data_in_111[9:0]       ),
.fuse_l2d_rid_11        (fuse_l2d_rid_111[4:0]   ),
.fuse_l2d_wren_11       (fuse_l2d_wren_111       ),
.fuse_l2d_reset_11_l    (fuse_l2d_reset_111_l     ),
.fdout_11               (fdout_111[9:0]  ),
////////////
.waysel_c3_1            (cache_way_sel_c3_11[15:0]),
.wayerr_c3_1            (cache_wayerr_c3_11),
.set_c3_1               (cache_set_c3_11[8:0]),
.coloff_c3_1            (cache_col_offset_c3_11),
.coloff_c4_l_1          (cache_col_offset_c4_l_11),
.coloff_c5_1            (cache_col_offset_c5_11[1:0]),
.rd_wr_c3_1             (cache_rd_wr_c3_11),
.readen_c5_1            (cache_readen_c5_11),
.worden_c3_1            (cache_word_en_c3_11[3:0]),
.tcu_pce_ov_1           (tcu_pce_ov_11),
.pce_1                  (tcu_pce_11),
.tcu_clk_stop_1         (tcu_clk_stop_11),
.se_1			(se_11),
.wee_l_1                (wee_l_q11),	//NEW
.tstmodclk_l_0		(tstmodclk_10_l),
.tstmodclk_l_1		(tstmodclk_11_l),
.vnw_ary                (vnw_ary1)
);


n2_l2d_quad_cust	quad_bot_left 
	(
.waysel_c3_0		(cache_way_sel_c3_20[15:0]),
.wayerr_c3_0            (cache_wayerr_c3_20),
.set_c3_0               (cache_set_c3_20[8:0]),
.coloff_c3_0            (cache_col_offset_c3_20),
.coloff_c4_l_0          (cache_col_offset_c4_l_20),
.coloff_c5_0            (cache_col_offset_c5_20[1:0]),
.rd_wr_c3_0             (cache_rd_wr_c3_20),
.readen_c5_0            (cache_readen_c5_20),
.worden_c3_0            (cache_word_en_c3_20[3:0]),
.l2clk                  (l2clk),
.tcu_pce_ov_0           (tcu_pce_ov_20),
.pce_0                  (tcu_pce_20),
.tcu_clk_stop_0         (tcu_clk_stop_20),
.se_0			(se_20),
.wee_l_0                (wee_l_q20),	//NEW
.wrdlo0_b_l		(cache_decc_in_c3b_l[77 :39 ]),
.wrdhi0_b_l		(cache_decc_in_c3b_l[155:117]),
.wrdlo1_b_l		(cache_decc_in_c3b_l[389:351]),
.wrdhi1_b_l		(cache_decc_in_c3b_l[467:429]),
.ldoutlo0_b		(cache_decc_out_c5b[77 :39 ]),
.ldouthi0_b		(cache_decc_out_c5b[155:117]),
.ldoutlo1_b		(cache_decc_out_c5b[389:351]),
.ldouthi1_b		(cache_decc_out_c5b[467:429]),
////////////
.fuse_l2d_data_in_00    (fuse_l2d_data_in_020[9:0]       ),
.fuse_l2d_rid_00        (fuse_l2d_rid_020[4:0]   ),
.fuse_l2d_wren_00       (fuse_l2d_wren_020       ),
.fuse_l2d_reset_00_l    (fuse_l2d_reset_020_l     ),
.fdout_00               (fdout_020[9:0]  ),
.fuse_l2d_data_in_01    (fuse_l2d_data_in_120[9:0]       ),
.fuse_l2d_rid_01        (fuse_l2d_rid_120[4:0]   ),
.fuse_l2d_wren_01       (fuse_l2d_wren_120       ),
.fuse_l2d_reset_01_l    (fuse_l2d_reset_120_l     ),
.fdout_01               (fdout_120[9:0]  ),
.fuse_l2d_data_in_10    (fuse_l2d_data_in_021[9:0]       ),
.fuse_l2d_rid_10        (fuse_l2d_rid_021[4:0]   ),
.fuse_l2d_wren_10       (fuse_l2d_wren_021       ),
.fuse_l2d_reset_10_l    (fuse_l2d_reset_021_l     ),
.fdout_10               (fdout_021[9:0]  ),
.fuse_l2d_data_in_11    (fuse_l2d_data_in_121[9:0]       ),
.fuse_l2d_rid_11        (fuse_l2d_rid_121[4:0]   ),
.fuse_l2d_wren_11       (fuse_l2d_wren_121       ),
.fuse_l2d_reset_11_l    (fuse_l2d_reset_121_l     ),
.fdout_11               (fdout_121[9:0]  ),
////////////

.waysel_c3_1            (cache_way_sel_c3_21[15:0]),
.wayerr_c3_1            (cache_wayerr_c3_21),
.set_c3_1               (cache_set_c3_21[8:0]),
.coloff_c3_1            (cache_col_offset_c3_21),
.coloff_c4_l_1          (cache_col_offset_c4_l_21),
.coloff_c5_1            (cache_col_offset_c5_21[1:0]),
.rd_wr_c3_1             (cache_rd_wr_c3_21),
.readen_c5_1            (cache_readen_c5_21),
.worden_c3_1            (cache_word_en_c3_21[3:0]),
.tcu_pce_ov_1           (tcu_pce_ov_21),
.pce_1                  (tcu_pce_21),
.tcu_clk_stop_1         (tcu_clk_stop_21),
.se_1			(se_21),
.wee_l_1                (wee_l_q21),	//NEW
.tstmodclk_l_0		(tstmodclk_20_l),
.tstmodclk_l_1		(tstmodclk_21_l),
.vnw_ary                (vnw_ary0)
);


n2_l2d_quad_cust        quad_bot_right 
	(
.waysel_c3_0            (cache_way_sel_c3_00[15:0]),
.wayerr_c3_0            (cache_wayerr_c3_00),
.set_c3_0               (cache_set_c3_00[8:0]),
.coloff_c3_0            (cache_col_offset_c3_00),
.coloff_c4_l_0          (cache_col_offset_c4_l_00),
.coloff_c5_0            (cache_col_offset_c5_00[1:0]),
.rd_wr_c3_0             (cache_rd_wr_c3_00),
.readen_c5_0            (cache_readen_c5_00),
.worden_c3_0            (cache_word_en_c3_00[3:0]),
.l2clk                  (l2clk),
.tcu_pce_ov_0           (tcu_pce_ov_00),
.pce_0                  (tcu_pce_00),
.tcu_clk_stop_0         (tcu_clk_stop_00),
.se_0			(se_00),
.wee_l_0                (wee_l_q00),	//NEW
.wrdlo0_b_l		(cache_decc_in_c3b_l[38 : 0 ]),
.wrdhi0_b_l		(cache_decc_in_c3b_l[116: 78]),
.wrdlo1_b_l		(cache_decc_in_c3b_l[350:312]),
.wrdhi1_b_l		(cache_decc_in_c3b_l[428:390]),
.ldoutlo0_b		(cache_decc_out_c5b[38 : 0 ]),
.ldouthi0_b		(cache_decc_out_c5b[116: 78]),
.ldoutlo1_b		(cache_decc_out_c5b[350:312]),
.ldouthi1_b		(cache_decc_out_c5b[428:390]),
////////////
.fuse_l2d_data_in_00    (fuse_l2d_data_in_000[9:0]       ),
.fuse_l2d_rid_00        (fuse_l2d_rid_000[4:0]   ),
.fuse_l2d_wren_00       (fuse_l2d_wren_000       ),
.fuse_l2d_reset_00_l    (fuse_l2d_reset_000_l     ),
.fdout_00               (fdout_000[9:0]  ),
.fuse_l2d_data_in_01    (fuse_l2d_data_in_100[9:0]       ),
.fuse_l2d_rid_01        (fuse_l2d_rid_100[4:0]   ),
.fuse_l2d_wren_01       (fuse_l2d_wren_100       ),
.fuse_l2d_reset_01_l    (fuse_l2d_reset_100_l     ),
.fdout_01               (fdout_100[9:0]  ),
.fuse_l2d_data_in_10    (fuse_l2d_data_in_001[9:0]       ),
.fuse_l2d_rid_10        (fuse_l2d_rid_001[4:0]   ),
.fuse_l2d_wren_10       (fuse_l2d_wren_001       ),
.fuse_l2d_reset_10_l    (fuse_l2d_reset_001_l     ),
.fdout_10               (fdout_001[9:0]  ),
.fuse_l2d_data_in_11    (fuse_l2d_data_in_101[9:0]       ),
.fuse_l2d_rid_11        (fuse_l2d_rid_101[4:0]   ),
.fuse_l2d_wren_11       (fuse_l2d_wren_101       ),
.fuse_l2d_reset_11_l    (fuse_l2d_reset_101_l     ),
.fdout_11               (fdout_101[9:0]  ),
////////////
.waysel_c3_1            (cache_way_sel_c3_01[15:0]),
.wayerr_c3_1            (cache_wayerr_c3_01),
.set_c3_1               (cache_set_c3_01[8:0]),
.coloff_c3_1            (cache_col_offset_c3_01),
.coloff_c4_l_1          (cache_col_offset_c4_l_01),
.coloff_c5_1            (cache_col_offset_c5_01[1:0]),
.rd_wr_c3_1             (cache_rd_wr_c3_01),
.readen_c5_1            (cache_readen_c5_01),
.worden_c3_1            (cache_word_en_c3_01[3:0]),
.tcu_pce_ov_1           (tcu_pce_ov_01),
.pce_1                  (tcu_pce_01),
.tcu_clk_stop_1         (tcu_clk_stop_01),
.se_1			(se_01),
.wee_l_1                (wee_l_q01),	//NEW
.tstmodclk_l_0		(tstmodclk_00_l),
.tstmodclk_l_1		(tstmodclk_01_l),
.vnw_ary                (vnw_ary0)
);


n2_l2d_ctrlio_cust	ctr
	(
	.l2t_l2d_word_en_c2			(l2t_l2d_word_en_c2[15:0]),
	.l2b_l2d_fbdecc_c5               	(l2b_l2d_fbdecc_c5[623:0]),
	.l2t_l2d_fbrd_c3                 	(l2t_l2d_fbrd_c3),
	.l2t_l2d_col_offset_c2           	(l2t_l2d_col_offset_c2[3:0]),
	.l2t_l2d_set_c2                  	(l2t_l2d_set_c2[8:0]),
	.l2t_l2d_rd_wr_c3                	(l2t_l2d_rd_wr_c3),
	.l2t_l2d_way_sel_c3              	(l2t_l2d_way_sel_c3[15:0]),
	.l2t_l2d_fb_hit_c3               	(l2t_l2d_fb_hit_c3),
	.scan_in(ctrlio_cust_scanin),
	.scan_out(ctrlio_cust_scanout),
	.l2clk                           	(l2clk),
	.tcu_aclk                        	(tcu_aclk),
	.tcu_bclk                        	(tcu_bclk),
	.tcu_scan_en                     	(tcu_scan_en),
	.tcu_pce_ov                      	(tcu_pce_ov),
	.tcu_ce                      	 	(tcu_ce),
	.tcu_clk_stop                    	(1'b0),
	.tcu_se_scancollar_in			(tcu_se_scancollar_in),
	.tcu_se_scancollar_out			(tcu_se_scancollar_out),
	.l2t_l2d_stdecc_c2			(l2t_l2d_stdecc_c2[77:0]),
	.l2d_decc_out_c6	         	(l2d_decc_out_c6[623:0]),
	.cache_decc_in_c3b_l	        	(cache_decc_in_c3b_l[623:0]),
	.cache_decc_out_c5b	 		(cache_decc_out_c5b[623:0]),
	.l2d_l2t_decc_c52_mux                 	(l2d_l2t_decc_c52_mux[155:0]),
	.cache_way_sel_c3_00             	(cache_way_sel_c3_00[15:0]),
	.cache_way_sel_c3_01             	(cache_way_sel_c3_01[15:0]),
	.cache_way_sel_c3_10             	(cache_way_sel_c3_10[15:0]),
	.cache_way_sel_c3_11             	(cache_way_sel_c3_11[15:0]),
	.cache_way_sel_c3_20             	(cache_way_sel_c3_20[15:0]),
	.cache_way_sel_c3_21             	(cache_way_sel_c3_21[15:0]),
	.cache_way_sel_c3_30             	(cache_way_sel_c3_30[15:0]),
	.cache_way_sel_c3_31             	(cache_way_sel_c3_31[15:0]),
        .cache_wayerr_c3_00		        (cache_wayerr_c3_00),
        .cache_wayerr_c3_01		        (cache_wayerr_c3_01),
        .cache_wayerr_c3_10		        (cache_wayerr_c3_10),
        .cache_wayerr_c3_11		        (cache_wayerr_c3_11),
        .cache_wayerr_c3_20		        (cache_wayerr_c3_20),
        .cache_wayerr_c3_21		        (cache_wayerr_c3_21),
        .cache_wayerr_c3_30		        (cache_wayerr_c3_30),
        .cache_wayerr_c3_31		        (cache_wayerr_c3_31),
	.cache_set_c3_00	         	(cache_set_c3_00[8:0]),
	.cache_set_c3_01	         	(cache_set_c3_01[8:0]),
	.cache_set_c3_10	         	(cache_set_c3_10[8:0]),
	.cache_set_c3_11	         	(cache_set_c3_11[8:0]),
	.cache_set_c3_20	         	(cache_set_c3_20[8:0]),
	.cache_set_c3_21	         	(cache_set_c3_21[8:0]),
	.cache_set_c3_30	         	(cache_set_c3_30[8:0]),
	.cache_set_c3_31	         	(cache_set_c3_31[8:0]),
	.cache_col_offset_c3_00          	(cache_col_offset_c3_00),
	.cache_col_offset_c3_01          	(cache_col_offset_c3_01),
	.cache_col_offset_c3_10          	(cache_col_offset_c3_10),
	.cache_col_offset_c3_11          	(cache_col_offset_c3_11),
	.cache_col_offset_c3_20          	(cache_col_offset_c3_20),
	.cache_col_offset_c3_21          	(cache_col_offset_c3_21),
	.cache_col_offset_c3_30          	(cache_col_offset_c3_30),
	.cache_col_offset_c3_31          	(cache_col_offset_c3_31),
	.cache_col_offset_c4_l_00        	(cache_col_offset_c4_l_00),
	.cache_col_offset_c4_l_01        	(cache_col_offset_c4_l_01),
	.cache_col_offset_c4_l_10        	(cache_col_offset_c4_l_10),
	.cache_col_offset_c4_l_11        	(cache_col_offset_c4_l_11),
	.cache_col_offset_c4_l_20        	(cache_col_offset_c4_l_20),
	.cache_col_offset_c4_l_21        	(cache_col_offset_c4_l_21),
	.cache_col_offset_c4_l_30        	(cache_col_offset_c4_l_30),
	.cache_col_offset_c4_l_31        	(cache_col_offset_c4_l_31),
	.cache_col_offset_c5_00          	(cache_col_offset_c5_00[1:0]),
	.cache_col_offset_c5_01          	(cache_col_offset_c5_01[1:0]),
	.cache_col_offset_c5_10          	(cache_col_offset_c5_10[1:0]),
	.cache_col_offset_c5_11          	(cache_col_offset_c5_11[1:0]),
	.cache_col_offset_c5_20          	(cache_col_offset_c5_20[1:0]),
	.cache_col_offset_c5_21          	(cache_col_offset_c5_21[1:0]),
	.cache_col_offset_c5_30          	(cache_col_offset_c5_30[1:0]),
	.cache_col_offset_c5_31          	(cache_col_offset_c5_31[1:0]),
	.cache_rd_wr_c3_00               	(cache_rd_wr_c3_00),
	.cache_rd_wr_c3_01               	(cache_rd_wr_c3_01),
	.cache_rd_wr_c3_10               	(cache_rd_wr_c3_10),
	.cache_rd_wr_c3_11               	(cache_rd_wr_c3_11),
	.cache_rd_wr_c3_20               	(cache_rd_wr_c3_20),
	.cache_rd_wr_c3_21               	(cache_rd_wr_c3_21),
	.cache_rd_wr_c3_30               	(cache_rd_wr_c3_30),
	.cache_rd_wr_c3_31               	(cache_rd_wr_c3_31),
	.cache_readen_c5_00              	(cache_readen_c5_00),
	.cache_readen_c5_01              	(cache_readen_c5_01),
	.cache_readen_c5_10              	(cache_readen_c5_10),
	.cache_readen_c5_11              	(cache_readen_c5_11),
	.cache_readen_c5_20              	(cache_readen_c5_20),
	.cache_readen_c5_21              	(cache_readen_c5_21),
	.cache_readen_c5_30              	(cache_readen_c5_30),
	.cache_readen_c5_31              	(cache_readen_c5_31),
	.cache_word_en_c3_00             	(cache_word_en_c3_00[3:0]),
	.cache_word_en_c3_01             	(cache_word_en_c3_01[3:0]),
	.cache_word_en_c3_10             	(cache_word_en_c3_10[3:0]),
	.cache_word_en_c3_11             	(cache_word_en_c3_11[3:0]),
	.cache_word_en_c3_20             	(cache_word_en_c3_20[3:0]),
	.cache_word_en_c3_21             	(cache_word_en_c3_21[3:0]),
	.cache_word_en_c3_30             	(cache_word_en_c3_30[3:0]),
	.cache_word_en_c3_31             	(cache_word_en_c3_31[3:0]),
	.tcu_pce_ov_00          		(tcu_pce_ov_00),
	.tcu_pce_ov_01          		(tcu_pce_ov_01),
	.tcu_pce_ov_10          		(tcu_pce_ov_10),
	.tcu_pce_ov_11          		(tcu_pce_ov_11),
	.tcu_pce_ov_20          		(tcu_pce_ov_20),
	.tcu_pce_ov_21          		(tcu_pce_ov_21),
	.tcu_pce_ov_30          		(tcu_pce_ov_30),
	.tcu_pce_ov_31          		(tcu_pce_ov_31),
	.tcu_pce_00             		(tcu_pce_00),
	.tcu_pce_01             		(tcu_pce_01),
	.tcu_pce_10             		(tcu_pce_10),
	.tcu_pce_11             		(tcu_pce_11),
	.tcu_pce_20             		(tcu_pce_20),
	.tcu_pce_21             		(tcu_pce_21),
	.tcu_pce_30             		(tcu_pce_30),
	.tcu_pce_31             		(tcu_pce_31),
	.se_00          		(se_00),
	.se_01          		(se_01),
	.se_10          		(se_10),
	.se_11          		(se_11),
	.se_20          		(se_20),
	.se_21          		(se_21),
	.se_30          		(se_30),
	.se_31          		(se_31),
	.tcu_clk_stop_00        		(tcu_clk_stop_00),
	.tcu_clk_stop_01        		(tcu_clk_stop_01),
	.tcu_clk_stop_10        		(tcu_clk_stop_10),
	.tcu_clk_stop_11        		(tcu_clk_stop_11),
	.tcu_clk_stop_20        		(tcu_clk_stop_20),
	.tcu_clk_stop_21        		(tcu_clk_stop_21),
	.tcu_clk_stop_30        		(tcu_clk_stop_30),
	.tcu_clk_stop_31         		(tcu_clk_stop_31),
        .array_wr_inhibit			 (array_wr_inhibit),
	.wayerr_c3				 (wayerr_c3),
	.siclk_peri				 (siclk_peri),
        .soclk_peri				 (soclk_peri),
        .pce_ov_peri				 (pce_ov_peri),
        .pce_peri				 (pce_peri),
        .scan_collarin_peri			 (scan_collarin_peri),
        .scan_collarout_peri			 (scan_collarout_peri),
        .wr_inhibit_peri			 (wr_inhibit_peri),
        .clk_stop_peri				 (clk_stop_peri),
        .wee_l_q00				 (wee_l_q00),
        .wee_l_q01				 (wee_l_q01),
        .wee_l_q10				 (wee_l_q10),
        .wee_l_q11				 (wee_l_q11),
        .wee_l_q20				 (wee_l_q20),
        .wee_l_q21				 (wee_l_q21),
        .wee_l_q30				 (wee_l_q30),
        .wee_l_q31				 (wee_l_q31),
	// Redudancy
	.l2b_l2d_fuse_l2d_data_in_d		 (l2b_l2d_fuse_l2d_data_in_d[9:0]),
	.l2b_l2d_fuse_rid_d                      (l2b_l2d_fuse_rid_d[6:0]),
	.l2b_l2d_fuse_reset_l                    (l2b_l2d_fuse_reset_d_l),
	.l2b_l2d_fuse_l2d_wren_d                 (l2b_l2d_fuse_l2d_wren_d),
	.efc_fuse_data                           (efc_fuse_data[9:0]),
	.fuse_l2d_data_in_131                    (fuse_l2d_data_in_131[9:0]),
	.fuse_l2d_rid_131                        (fuse_l2d_rid_131[4:0]),
	.fuse_l2d_wren_131                       (fuse_l2d_wren_131),
	.fuse_l2d_reset_131_l                    (fuse_l2d_reset_131_l),
	.fdout_131                               (fdout_131[9:0]),
	.fuse_l2d_data_in_031                    (fuse_l2d_data_in_031[9:0]	),
	.fuse_l2d_rid_031                        (fuse_l2d_rid_031[4:0]	),
	.fuse_l2d_wren_031                       (fuse_l2d_wren_031         	),
	.fuse_l2d_reset_031_l                    (fuse_l2d_reset_031_l        	),
	.fdout_031                               (fdout_031                 [9:0]	),
	.fuse_l2d_data_in_130                    (fuse_l2d_data_in_130      [9:0]	),
	.fuse_l2d_rid_130                        (fuse_l2d_rid_130          [4:0]	),
	.fuse_l2d_wren_130                       (fuse_l2d_wren_130         	),
	.fuse_l2d_reset_130_l                    (fuse_l2d_reset_130_l        	),
	.fdout_130                               (fdout_130                 [9:0]	),
	.fuse_l2d_data_in_030                    (fuse_l2d_data_in_030      [9:0]	),
	.fuse_l2d_rid_030                        (fuse_l2d_rid_030          [4:0]	),
	.fuse_l2d_wren_030                       (fuse_l2d_wren_030         	),
	.fuse_l2d_reset_030_l                    (fuse_l2d_reset_030_l        	),
	.fdout_030                               (fdout_030                 [9:0]	),
	.fuse_l2d_data_in_111                    (fuse_l2d_data_in_111      [9:0]	),
	.fuse_l2d_rid_111                        (fuse_l2d_rid_111          [4:0]	),
	.fuse_l2d_wren_111                       (fuse_l2d_wren_111         	),
	.fuse_l2d_reset_111_l                    (fuse_l2d_reset_111_l        	),
	.fdout_111                               (fdout_111                 [9:0]	),
	.fuse_l2d_data_in_011                    (fuse_l2d_data_in_011      [9:0]   ),
	.fuse_l2d_rid_011                        (fuse_l2d_rid_011          [4:0]   ),
	.fuse_l2d_wren_011                       (fuse_l2d_wren_011                 ),
	.fuse_l2d_reset_011_l                    (fuse_l2d_reset_011_l                ),
	.fdout_011                               (fdout_011                 [9:0]   ),
	.fuse_l2d_data_in_110                    (fuse_l2d_data_in_110      [9:0]	),
	.fuse_l2d_rid_110                        (fuse_l2d_rid_110          [4:0]	),
	.fuse_l2d_wren_110                       (fuse_l2d_wren_110         	),
	.fuse_l2d_reset_110_l                    (fuse_l2d_reset_110_l        	),
	.fdout_110                               (fdout_110                 [9:0]	),
	.fuse_l2d_data_in_010                    (fuse_l2d_data_in_010      [9:0]	),
	.fuse_l2d_rid_010                        (fuse_l2d_rid_010          [4:0]	),
	.fuse_l2d_wren_010                       (fuse_l2d_wren_010         	),
	.fuse_l2d_reset_010_l                    (fuse_l2d_reset_010_l        	),
	.fdout_010                               (fdout_010                 [9:0]	),
	.fuse_l2d_data_in_121                    (fuse_l2d_data_in_121      [9:0]	),
	.fuse_l2d_rid_121                        (fuse_l2d_rid_121          [4:0]	),
	.fuse_l2d_wren_121                       (fuse_l2d_wren_121         	),
	.fuse_l2d_reset_121_l                    (fuse_l2d_reset_121_l        	),
	.fdout_121                               (fdout_121                 [9:0]	),
	.fuse_l2d_data_in_021                    (fuse_l2d_data_in_021      [9:0]	),
	.fuse_l2d_rid_021                        (fuse_l2d_rid_021          [4:0]	),
	.fuse_l2d_wren_021                       (fuse_l2d_wren_021         	),
	.fuse_l2d_reset_021_l                    (fuse_l2d_reset_021_l        	),
	.fdout_021                               (fdout_021                 [9:0]	),
	.fuse_l2d_data_in_120                    (fuse_l2d_data_in_120      [9:0]	),
	.fuse_l2d_rid_120                        (fuse_l2d_rid_120          [4:0]	),
	.fuse_l2d_wren_120                       (fuse_l2d_wren_120         	),
	.fuse_l2d_reset_120_l                    (fuse_l2d_reset_120_l        	),
	.fdout_120                               (fdout_120                 [9:0]	),
	.fuse_l2d_data_in_020                    (fuse_l2d_data_in_020      [9:0]	),
	.fuse_l2d_rid_020                        (fuse_l2d_rid_020          [4:0]	),
	.fuse_l2d_wren_020                       (fuse_l2d_wren_020         	),
	.fuse_l2d_reset_020_l                    (fuse_l2d_reset_020_l        	),
	.fdout_020                               (fdout_020                 [9:0]	),
	.fuse_l2d_data_in_101                    (fuse_l2d_data_in_101      [9:0]	),
	.fuse_l2d_rid_101                        (fuse_l2d_rid_101          [4:0]	),
	.fuse_l2d_wren_101                       (fuse_l2d_wren_101         	),
	.fuse_l2d_reset_101_l                    (fuse_l2d_reset_101_l        	),
	.fdout_101                               (fdout_101                 [9:0]	),
	.fuse_l2d_data_in_001                    (fuse_l2d_data_in_001      [9:0]	),
	.fuse_l2d_rid_001                        (fuse_l2d_rid_001          [4:0]	),
	.fuse_l2d_wren_001                       (fuse_l2d_wren_001         	),
	.fuse_l2d_reset_001_l                    (fuse_l2d_reset_001_l        	),
	.fdout_001                               (fdout_001                 [9:0]	),
	.fuse_l2d_data_in_100                    (fuse_l2d_data_in_100      [9:0]	),
	.fuse_l2d_rid_100                        (fuse_l2d_rid_100          [4:0]	),
	.fuse_l2d_wren_100                       (fuse_l2d_wren_100         	),
	.fuse_l2d_reset_100_l                    (fuse_l2d_reset_100_l        	),
	.fdout_100                               (fdout_100                 [9:0]	),
	.fuse_l2d_data_in_000                    (fuse_l2d_data_in_000      [9:0]	),
	.fuse_l2d_rid_000                        (fuse_l2d_rid_000          [4:0]	),
	.fuse_l2d_wren_000                       (fuse_l2d_wren_000         	),
        .fuse_l2d_reset_000_l                    (fuse_l2d_reset_000_l        	),
        .fdout_000                               (fdout_000                 [9:0]	),
	.l2t_l2d_pwrsav_ov_stg                   (l2t_l2d_pwrsav_ov_stg),	//NEW
        .cache_col_offset_all_c7                 (cache_col_offset_all_c7),	//NEW
        .delout00	(tstmodclk_00_l),
        .delout01	(tstmodclk_01_l),
        .delout10	(tstmodclk_10_l),
        .delout11	(tstmodclk_11_l),
        .delout20	(tstmodclk_20_l),
        .delout21	(tstmodclk_21_l),
        .delout30	(tstmodclk_30_l),
        .delout31	(tstmodclk_31_l),
        .aclk		(aclk_clsrhdr),
	.bclk		(bclk_clsrhdr),
	.scan_en_clsrhdr (scan_en_clsrhdr)
	);

// For vlint
assign rst_wmr_protect_unused 	= rst_wmr_protect;
assign rst_wmr_unused	      	= rst_wmr_;
assign rst_por_unused		= rst_por_;
	
n2_clk_clstr_hdr_cust l2d_clk_header 
        ( 
	.tcu_wr_inhibit		(tcu_array_wr_inhibit	),
	.array_wr_inhibit	(array_wr_inhibit),
	.tcu_atpg_mode		(tcu_atpg_mode		),
        .l2clk                  (l2clk                  ),
        .aclk                   (l2d_clk_header_unused[0]),
        .bclk                   (l2d_clk_header_unused[1]),
        .scan_out               (clstr_hdr_scanout     ),
        .pce_ov                 (l2d_clk_header_unused[2]),
        .wmr_protect            (l2d_clk_header_unused[3]),
        .wmr_                   (l2d_clk_header_unused[4]),
        .por_                   (l2d_clk_header_unused[5]),
        .cmp_slow_sync_en       (l2d_clk_header_unused[6]),
        .slow_cmp_sync_en       (l2d_clk_header_unused[7]),
        .tcu_clk_stop           (tcu_clk_stop           ),
        .tcu_pce_ov             (1'b0                   ),
	.cluster_arst_l		(1'b1                   ),
	.aclk_wmr		(l2d_clk_header_unused[8]),
        .rst_wmr_protect        (1'b0                   ),
        .rst_wmr_               (1'b0                   ),
        .rst_por_               (1'b0                   ),
        .ccu_cmp_slow_sync_en   (1'b0                   ),
        .ccu_slow_cmp_sync_en   (1'b0                   ),
        .tcu_div_bypass         (1'b0                   ),
        .ccu_div_ph             (1'b1                   ),
        .cluster_div_en         (1'b0                   ),
        .gclk                   (gclk                   ),
        .tcu_aclk               (aclk_clsrhdr           ),
        .tcu_bclk               (bclk_clsrhdr           ),
        .scan_en                (scan_en_clsrhdr        ),
        .scan_in                (clstr_hdr_scanin       ),
  .cclk(cclk)
        );

n2_clk_l2d_cmp_cust l2d_pregrid_drv_top
        (
        .cclk 	(cclk),
        .l2clk  (l2clk)
        );
n2_clk_l2d_cmp_cust l2d_pregrid_drv_bot
        (
        .cclk   (cclk),
        .l2clk  (l2clk)
        );

// fixscan start:
assign perif_io_scanin           = scan_in                  ;
assign clstr_hdr_scanin          = perif_io_scanout         ;
assign ctrlio_cust_scanin        = clstr_hdr_scanout        ;
assign scan_out                  = ctrlio_cust_scanout      ;
// fixscan end:
endmodule


module n2_l2d_perf_io_cust (
  l2d_decc_out_c6, 
  l2b_l2d_fbdecc_c4, 
  l2t_l2d_way_sel_c2, 
  l2clk, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_pce_ov, 
  tcu_clk_stop, 
  tcu_ce, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  scan_in, 
  wr_inhibit, 
  l2d_l2t_decc_c52_mux, 
  l2b_l2d_en_fill_clk_v0, 
  l2b_l2d_en_fill_clk_v1, 
  l2t_l2d_en_fill_clk_ov, 
  cache_col_offset_all_c7, 
  l2t_l2d_pwrsav_ov, 
  l2t_l2d_rd_wr_c2, 
  l2t_l2d_pwrsav_ov_stg, 
  scan_out, 
  l2t_l2d_rd_wr_c3, 
  l2b_l2d_fuse_l2d_data_in, 
  l2b_l2d_fuse_rid, 
  l2b_l2d_fuse_reset, 
  l2b_l2d_fuse_l2d_wren, 
  l2d_l2b_efc_fuse_data, 
  l2b_l2d_fuse_l2d_data_in_d, 
  l2b_l2d_fuse_rid_d, 
  l2b_l2d_fuse_reset_d_l, 
  l2b_l2d_fuse_l2d_wren_d, 
  efc_fuse_data, 
  l2d_l2b_decc_out_c7, 
  l2b_l2d_fbdecc_c5, 
  l2t_l2d_way_sel_c3, 
  l2d_l2t_decc_c6, 
  wayerr_c3);
wire stop;
wire l1clk_in;
wire l1clk_out;
wire fill_pce0;
wire l1clk_fill0;
wire fill_pce1;
wire l1clk_fill1;
wire cache_col_offset_all_c7_or_l2t_l2d_pwrsav_ov_stg;
wire l1clk_decc_c7;
wire [0:0] ff_l2t_l2d_rd_wr_c3_scanin;
wire [0:0] ff_l2t_l2d_rd_wr_c3_scanout;
wire [0:0] ff_fill_clk_en_ov_stg_scanin;
wire [0:0] ff_fill_clk_en_ov_stg_scanout;
wire fill_clk_en_ov_stg;
wire [0:0] ff_pwrsav_ov_stg_scanin;
wire [0:0] ff_pwrsav_ov_stg_scanout;
wire [155:0] ff_l2d_l2t_decc_c6_scanin;
wire [155:0] ff_l2d_l2t_decc_c6_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_1_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_1_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_2_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_2_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_3_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_3_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_4_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_4_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_5_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_5_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_6_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_6_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_7_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_7_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_8_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_8_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_9_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_9_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_10_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_10_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_11_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_11_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_12_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_12_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_13_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_13_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_14_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_14_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_15_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_15_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c5_16_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c5_16_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_1_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_1_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_2_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_2_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_3_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_3_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_4_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_4_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_5_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_5_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_6_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_6_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_7_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_7_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_8_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_8_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_9_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_9_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_10_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_10_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_11_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_11_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_12_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_12_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_13_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_13_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_14_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_14_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_15_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_15_scanout;
wire [38:0] ff_l2d_l2b_decc_out_c7_16_scanin;
wire [38:0] ff_l2d_l2b_decc_out_c7_16_scanout;
wire [15:0] ff_l2t_l2d_way_sel_c3_scanin;
wire [15:0] ff_l2t_l2d_way_sel_c3_scanout;
wire [9:0] ff_l2b_l2d_fuse_l2d_data_in_scanin;
wire [9:0] ff_l2b_l2d_fuse_l2d_data_in_scanout;
wire [9:0] ff_l2d_l2b_efc_fuse_data_scanin;
wire [9:0] ff_l2d_l2b_efc_fuse_data_scanout;
wire [6:0] ff_l2b_l2d_fuse_rid_d_scanin;
wire [6:0] ff_l2b_l2d_fuse_rid_d_scanout;
wire [0:0] ff_l2b_l2d_fuse_wren_d_scanin;
wire [0:0] ff_l2b_l2d_fuse_wren_d_scanout;
wire l2b_l2d_fuse_l2d_wren_stg;
wire l2b_l2d_fuse_reset_stg_n;
wire wr_inhibit_n;
wire l2b_l2d_fuse_reset_stg;
wire [0:0] ff_l2b_l2d_fuse_reset_d_scanin;
wire [0:0] ff_l2b_l2d_fuse_reset_d_scanout;


input 	[623:0] l2d_decc_out_c6;
input 	[623:0] l2b_l2d_fbdecc_c4;
input	[15:0]	l2t_l2d_way_sel_c2;
input 	  	l2clk;
input           tcu_aclk;
input           tcu_bclk;
input           tcu_pce_ov;
input		tcu_clk_stop;
input		tcu_ce;
input           tcu_se_scancollar_in;
input           tcu_se_scancollar_out;
input           scan_in;
input		wr_inhibit;
input 	[155:0] l2d_l2t_decc_c52_mux;
input		l2b_l2d_en_fill_clk_v0;
input		l2b_l2d_en_fill_clk_v1;
input		l2t_l2d_en_fill_clk_ov;
input		cache_col_offset_all_c7;
input		l2t_l2d_pwrsav_ov;
input		l2t_l2d_rd_wr_c2;
output		l2t_l2d_pwrsav_ov_stg;
output          scan_out;
output		l2t_l2d_rd_wr_c3;
// From outside world
input   [9:0]   l2b_l2d_fuse_l2d_data_in;
input   [6:0]   l2b_l2d_fuse_rid;
input           l2b_l2d_fuse_reset;
input           l2b_l2d_fuse_l2d_wren;
output  [9:0]   l2d_l2b_efc_fuse_data;

// to outside world
output  [9:0]   l2b_l2d_fuse_l2d_data_in_d;
output  [6:0]   l2b_l2d_fuse_rid_d;
output          l2b_l2d_fuse_reset_d_l;
output          l2b_l2d_fuse_l2d_wren_d;
input	[9:0]	efc_fuse_data;
   
// Regular outputs
output [623:0] l2d_l2b_decc_out_c7;
output [623:0] l2b_l2d_fbdecc_c5;
output [15:0]  l2t_l2d_way_sel_c3;
output [155:0] l2d_l2t_decc_c6;
output         wayerr_c3;
//////////////////////////////////////////////////////////////////////////////

wire pce_ov;
wire siclk;
wire soclk;
wire scan_out;

assign stop = tcu_clk_stop;
assign siclk = tcu_aclk;
assign soclk = tcu_bclk;
assign pce_ov = tcu_pce_ov;

//////////////////////////////////////////////////////////////////////////////
//   wire [623:0]   l2d_decc_out_c6;


n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_in_hdr (
        .l2clk  (l2clk),
        .se     (tcu_se_scancollar_in),
        .l1en   (tcu_ce),
        .pce_ov (pce_ov),
        .stop   (stop),
        .l1clk  (l1clk_in)
        );
	
n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_out_hdr (
        .l2clk  (l2clk),
        .se     (tcu_se_scancollar_out),
        .l1en   (tcu_ce),
        .pce_ov (pce_ov),
        .stop   (stop),
        .l1clk  (l1clk_out)
        );
	
n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_fill0_hdr (
        .l2clk  (l2clk),
        .se     (tcu_se_scancollar_in),
        .l1en   (fill_pce0),
        .pce_ov (pce_ov),
        .stop   (stop),
        .l1clk  (l1clk_fill0)
        );

n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_fill1_hdr (
        .l2clk  (l2clk),
        .se     (tcu_se_scancollar_in),
        .l1en   (fill_pce1),
        .pce_ov (pce_ov),
        .stop   (stop),
        .l1clk  (l1clk_fill1)
        );

n2_l2d_sp_512kb_cust_or_macro__width_1 or_slice_col_offset_all_pwrsv 
	(
	.dout	(cache_col_offset_all_c7_or_l2t_l2d_pwrsav_ov_stg),
	.din0	(l2t_l2d_pwrsav_ov_stg),
	.din1	(cache_col_offset_all_c7)
	);	

	
n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_decc_c7_hdr (
        .l2clk  (l2clk),
        .se     (tcu_se_scancollar_out),
//        .l1en   (cache_col_offset_all_c7 | l2t_l2d_pwrsav_ov_stg),
	.l1en	(cache_col_offset_all_c7_or_l2t_l2d_pwrsav_ov_stg),
        .pce_ov (pce_ov),
        .stop   (stop),
        .l1clk  (l1clk_decc_c7)
        );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1      ff_l2t_l2d_rd_wr_c3  
     (
     .scan_in(ff_l2t_l2d_rd_wr_c3_scanin[0:0]),
     .scan_out(ff_l2t_l2d_rd_wr_c3_scanout[0:0]),
	.dout		(l2t_l2d_rd_wr_c3),
	.din		(l2t_l2d_rd_wr_c2),
	.l1clk  	(l1clk_in),
  .siclk(siclk),
  .soclk(soclk)
	);
	
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1      ff_fill_clk_en_ov_stg  
     (
     .scan_in(ff_fill_clk_en_ov_stg_scanin[0:0]),
     .scan_out(ff_fill_clk_en_ov_stg_scanout[0:0]),
	.dout		(fill_clk_en_ov_stg),
	.din		(l2t_l2d_en_fill_clk_ov),
	.l1clk  	(l1clk_in),
  .siclk(siclk),
  .soclk(soclk)
	);
	
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1      ff_pwrsav_ov_stg  
     (
     .scan_in(ff_pwrsav_ov_stg_scanin[0:0]),
     .scan_out(ff_pwrsav_ov_stg_scanout[0:0]),
	.dout		(l2t_l2d_pwrsav_ov_stg),
	.din		(l2t_l2d_pwrsav_ov),
	.l1clk  	(l1clk_in),
  .siclk(siclk),
  .soclk(soclk)
	);
//assign 	fill_pce0 = l2b_l2d_en_fill_clk_v0 | fill_clk_en_ov_stg;
//assign 	fill_pce1 = l2b_l2d_en_fill_clk_v1 | fill_clk_en_ov_stg;

n2_l2d_sp_512kb_cust_or_macro__width_2  or_fill_pce0  
        (
        .dout	({fill_pce0,fill_pce1}),
        .din0	({l2b_l2d_en_fill_clk_v0,l2b_l2d_en_fill_clk_v1}),
        .din1	({fill_clk_en_ov_stg,fill_clk_en_ov_stg})
        );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_156      ff_l2d_l2t_decc_c6  
     (
     .scan_in(ff_l2d_l2t_decc_c6_scanin[155:0]),
     .scan_out(ff_l2d_l2t_decc_c6_scanout[155:0]),
	.dout		(l2d_l2t_decc_c6[155:0]),
	.din		(l2d_l2t_decc_c52_mux[155:0]),
	.l1clk  	(l1clk_out),
  .siclk(siclk),
  .soclk(soclk)
	);


n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_1  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_1_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_1_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[38:0]),
	.din		(l2b_l2d_fbdecc_c4[38:0]),
	.l1clk		(l1clk_fill1),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_2  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_2_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_2_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[77:39]),
	.din		(l2b_l2d_fbdecc_c4[77:39]),
	.l1clk		(l1clk_fill0),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_3  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_3_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_3_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[116:78]),
	.din		(l2b_l2d_fbdecc_c4[116:78]),
	.l1clk		(l1clk_fill1),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_4  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_4_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_4_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[155:117]),
	.din		(l2b_l2d_fbdecc_c4[155:117]),
	.l1clk		(l1clk_fill0),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_5  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_5_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_5_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[194:156]),
	.din		(l2b_l2d_fbdecc_c4[194:156]),
	.l1clk		(l1clk_fill1),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_6  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_6_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_6_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[233:195]),
	.din		(l2b_l2d_fbdecc_c4[233:195]),
	.l1clk		(l1clk_fill0),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_7  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_7_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_7_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[272:234]),
	.din		(l2b_l2d_fbdecc_c4[272:234]),
	.l1clk		(l1clk_fill1),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_8  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_8_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_8_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[311:273]),
	.din		(l2b_l2d_fbdecc_c4[311:273]),
	.l1clk		(l1clk_fill0),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_9  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_9_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_9_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[350:312]),
	.din		(l2b_l2d_fbdecc_c4[350:312]),
	.l1clk		(l1clk_fill1),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_10  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_10_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_10_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[389:351]),
	.din		(l2b_l2d_fbdecc_c4[389:351]),
	.l1clk		(l1clk_fill0),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_11  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_11_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_11_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[428:390]),
	.din		(l2b_l2d_fbdecc_c4[428:390]),
	.l1clk		(l1clk_fill1),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_12  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_12_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_12_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[467:429]),
	.din		(l2b_l2d_fbdecc_c4[467:429]),
	.l1clk		(l1clk_fill0),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_13  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_13_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_13_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[506:468]),
	.din		(l2b_l2d_fbdecc_c4[506:468]),
	.l1clk		(l1clk_fill1),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_14  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_14_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_14_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[545:507]),
	.din		(l2b_l2d_fbdecc_c4[545:507]),
	.l1clk		(l1clk_fill0),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_15  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_15_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_15_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[584:546]),
	.din		(l2b_l2d_fbdecc_c4[584:546]),
	.l1clk		(l1clk_fill1),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2b_l2d_fbdecc_c5_16  
     (
     .scan_in(ff_l2b_l2d_fbdecc_c5_16_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c5_16_scanout[38:0]),
	.dout		(l2b_l2d_fbdecc_c5[623:585]),
	.din		(l2b_l2d_fbdecc_c4[623:585]),
	.l1clk		(l1clk_fill0),
  .siclk(siclk),
  .soclk(soclk)
	);


n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_1  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_1_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_1_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[38:0]),
	.din		(l2d_decc_out_c6[38:0]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_2  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_2_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_2_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[77:39]),
	.din		(l2d_decc_out_c6[77:39]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_3  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_3_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_3_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[116:78]),
	.din		(l2d_decc_out_c6[116:78]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_4  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_4_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_4_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[155:117]),
	.din		(l2d_decc_out_c6[155:117]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_5  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_5_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_5_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[194:156]),
	.din		(l2d_decc_out_c6[194:156]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_6  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_6_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_6_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[233:195]),
	.din		(l2d_decc_out_c6[233:195]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_7  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_7_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_7_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[272:234]),
	.din		(l2d_decc_out_c6[272:234]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_8  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_8_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_8_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[311:273]),
	.din		(l2d_decc_out_c6[311:273]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_9  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_9_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_9_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[350:312]),
	.din		(l2d_decc_out_c6[350:312]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_10  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_10_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_10_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[389:351]),
	.din		(l2d_decc_out_c6[389:351]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_11  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_11_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_11_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[428:390]),
	.din		(l2d_decc_out_c6[428:390]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_12  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_12_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_12_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[467:429]),
	.din		(l2d_decc_out_c6[467:429]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_13  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_13_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_13_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[506:468]),
	.din		(l2d_decc_out_c6[506:468]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_14  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_14_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_14_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[545:507]),
	.din		(l2d_decc_out_c6[545:507]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_15  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_15_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_15_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[584:546]),
	.din		(l2d_decc_out_c6[584:546]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39	ff_l2d_l2b_decc_out_c7_16  
     (
     .scan_in(ff_l2d_l2b_decc_out_c7_16_scanin[38:0]),
     .scan_out(ff_l2d_l2b_decc_out_c7_16_scanout[38:0]),
	.dout		(l2d_l2b_decc_out_c7[623:585]),
	.din		(l2d_decc_out_c6[623:585]),
	.l1clk		(l1clk_decc_c7),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_16      ff_l2t_l2d_way_sel_c3  
     (
     .scan_in(ff_l2t_l2d_way_sel_c3_scanin[15:0]),
     .scan_out(ff_l2t_l2d_way_sel_c3_scanout[15:0]),
        .dout           (l2t_l2d_way_sel_c3[15:0]),
        .din            (l2t_l2d_way_sel_c2[15:0]),
        .l1clk            (l1clk_in),
  .siclk(siclk),
  .soclk(soclk)
        );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_10	ff_l2b_l2d_fuse_l2d_data_in 
     (
     .scan_in(ff_l2b_l2d_fuse_l2d_data_in_scanin[9:0]),
     .scan_out(ff_l2b_l2d_fuse_l2d_data_in_scanout[9:0]),
	.dout		(l2b_l2d_fuse_l2d_data_in_d),
	.din		(l2b_l2d_fuse_l2d_data_in),
	.l1clk		(l1clk_in),
  .siclk(siclk),
  .soclk(soclk)
	);

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_10  ff_l2d_l2b_efc_fuse_data 
     (
     .scan_in(ff_l2d_l2b_efc_fuse_data_scanin[9:0]),
     .scan_out(ff_l2d_l2b_efc_fuse_data_scanout[9:0]),
        .dout           (l2d_l2b_efc_fuse_data),
        .din            (efc_fuse_data),
        .l1clk            (l1clk_out),
  .siclk(siclk),
  .soclk(soclk)
        );


n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_7  ff_l2b_l2d_fuse_rid_d 
     (
     .scan_in(ff_l2b_l2d_fuse_rid_d_scanin[6:0]),
     .scan_out(ff_l2b_l2d_fuse_rid_d_scanout[6:0]),
        .din            (l2b_l2d_fuse_rid),
        .dout           (l2b_l2d_fuse_rid_d),
        .l1clk            (l1clk_in),
  .siclk(siclk),
  .soclk(soclk)
        );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1  ff_l2b_l2d_fuse_wren_d 
     (
     .scan_in(ff_l2b_l2d_fuse_wren_d_scanin[0:0]),
     .scan_out(ff_l2b_l2d_fuse_wren_d_scanout[0:0]),
        .din            (l2b_l2d_fuse_l2d_wren),
        .dout           (l2b_l2d_fuse_l2d_wren_stg),
        .l1clk            (l1clk_in),
  .siclk(siclk),
  .soclk(soclk)
        );
//assign l2b_l2d_fuse_l2d_wren_d = (l2b_l2d_fuse_l2d_wren_stg) & (~wr_inhibit);

n2_l2d_sp_512kb_cust_inv_macro__width_2 inv_wr_inhibit 
	(
	.dout	({l2b_l2d_fuse_reset_stg_n,wr_inhibit_n}),
	.din	({l2b_l2d_fuse_reset_stg,wr_inhibit})
	);
n2_l2d_sp_512kb_cust_and_macro__width_1 and_l2b_l2d_fuse_l2d_wren_d 
	(
	.dout	(l2b_l2d_fuse_l2d_wren_d),
	.din0	(wr_inhibit_n),
	.din1	(l2b_l2d_fuse_l2d_wren_stg)
	);
	
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1  ff_l2b_l2d_fuse_reset_d 
     (
     .scan_in(ff_l2b_l2d_fuse_reset_d_scanin[0:0]),
     .scan_out(ff_l2b_l2d_fuse_reset_d_scanout[0:0]),
        .din            (l2b_l2d_fuse_reset),
        .dout           (l2b_l2d_fuse_reset_stg),
        .l1clk            (l1clk_in),
  .siclk(siclk),
  .soclk(soclk)
        );
//assign l2b_l2d_fuse_reset_d_l =  ~l2b_l2d_fuse_reset_stg | wr_inhibit;

n2_l2d_sp_512kb_cust_or_macro__width_1 and_l2b_l2d_fuse_reset_d_l 
        (
        .dout   (l2b_l2d_fuse_reset_d_l),
        .din0   (wr_inhibit),
        .din1   (l2b_l2d_fuse_reset_stg_n)
        );

//always@(l2t_l2d_way_sel_c3)
//begin
//case(l2t_l2d_way_sel_c3)
//16'b0000_0000_0000_0000   :       wayerr_c3 = 1;
//16'b0000_0000_0000_0001   :       wayerr_c3 = 0;
//16'b0000_0000_0000_0010   :       wayerr_c3 = 0;
//16'b0000_0000_0000_0100   :       wayerr_c3 = 0;
//16'b0000_0000_0000_1000   :       wayerr_c3 = 0;
//16'b0000_0000_0001_0000   :	  wayerr_c3 = 0;
//16'b0000_0000_0010_0000   :	  wayerr_c3 = 0;
//16'b0000_0000_0100_0000   :	  wayerr_c3 = 0;
//16'b0000_0000_1000_0000   :	  wayerr_c3 = 0;
//16'b0000_0001_0000_0000   :	  wayerr_c3 = 0;
//16'b0000_0010_0000_0000   :	  wayerr_c3 = 0;
//16'b0000_0100_0000_0000   :	  wayerr_c3 = 0;
//16'b0000_1000_0000_0000   :	  wayerr_c3 = 0;
//16'b0001_0000_0000_0000   :	  wayerr_c3 = 0;
//16'b0010_0000_0000_0000   :	  wayerr_c3 = 0;
//16'b0100_0000_0000_0000   :	  wayerr_c3 = 0;
//16'b1000_0000_0000_0000   :	  wayerr_c3 = 0;
//default                   :       wayerr_c3 = 1;
//endcase
//end

l2t_wayerr_ctl  way_err_computed
        (
        .wayerr_c3      (wayerr_c3),
        .l2t_l2d_way_sel_c3(l2t_l2d_way_sel_c3[15:0])
        );


// scanorder start
//  ff_l2t_l2d_rd_wr_c3_scanin
//  ff_l2t_l2d_way_sel_c3_scanin[0:15]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_1_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_5_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_3_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_7_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_9_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_13_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_11_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_15_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[0]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[1]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[2]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[3]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[4]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[5]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[6]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[7]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[8]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[9]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[10]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[11]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[12]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[13]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[14]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[15]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[16]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[17]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[18]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[19]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[20]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[21]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[22]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[23]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[24]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[25]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[26]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[27]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[28]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[29]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[30]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[31]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[32]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[33]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[34]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[35]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[36]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[37]
//  ff_l2b_l2d_fbdecc_c5_2_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_6_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_4_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_8_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_10_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_14_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_12_scanin[38]
//  ff_l2b_l2d_fbdecc_c5_16_scanin[38]

//  ff_l2d_l2b_decc_out_c7_1_scanin[0]
//  ff_l2d_l2b_decc_out_c7_5_scanin[0]
//  ff_l2d_l2b_decc_out_c7_3_scanin[0]
//  ff_l2d_l2b_decc_out_c7_7_scanin[0]
//  ff_l2d_l2b_decc_out_c7_9_scanin[0]
//  ff_l2d_l2b_decc_out_c7_13_scanin[0]
//  ff_l2d_l2b_decc_out_c7_11_scanin[0]
//  ff_l2d_l2b_decc_out_c7_15_scanin[0]
//  ff_l2d_l2b_decc_out_c7_1_scanin[1]
//  ff_l2d_l2b_decc_out_c7_5_scanin[1]
//  ff_l2d_l2b_decc_out_c7_3_scanin[1]
//  ff_l2d_l2b_decc_out_c7_7_scanin[1]
//  ff_l2d_l2b_decc_out_c7_9_scanin[1]
//  ff_l2d_l2b_decc_out_c7_13_scanin[1]
//  ff_l2d_l2b_decc_out_c7_11_scanin[1]
//  ff_l2d_l2b_decc_out_c7_15_scanin[1]
//  ff_l2d_l2b_decc_out_c7_1_scanin[2]
//  ff_l2d_l2b_decc_out_c7_5_scanin[2]
//  ff_l2d_l2b_decc_out_c7_3_scanin[2]
//  ff_l2d_l2b_decc_out_c7_7_scanin[2]
//  ff_l2d_l2b_decc_out_c7_9_scanin[2]
//  ff_l2d_l2b_decc_out_c7_13_scanin[2]
//  ff_l2d_l2b_decc_out_c7_11_scanin[2]
//  ff_l2d_l2b_decc_out_c7_15_scanin[2]
//  ff_l2d_l2b_decc_out_c7_1_scanin[3]
//  ff_l2d_l2b_decc_out_c7_5_scanin[3]
//  ff_l2d_l2b_decc_out_c7_3_scanin[3]
//  ff_l2d_l2b_decc_out_c7_7_scanin[3]
//  ff_l2d_l2b_decc_out_c7_9_scanin[3]
//  ff_l2d_l2b_decc_out_c7_13_scanin[3]
//  ff_l2d_l2b_decc_out_c7_11_scanin[3]
//  ff_l2d_l2b_decc_out_c7_15_scanin[3]
//  ff_l2d_l2b_decc_out_c7_1_scanin[4]
//  ff_l2d_l2b_decc_out_c7_5_scanin[4]
//  ff_l2d_l2b_decc_out_c7_3_scanin[4]
//  ff_l2d_l2b_decc_out_c7_7_scanin[4]
//  ff_l2d_l2b_decc_out_c7_9_scanin[4]
//  ff_l2d_l2b_decc_out_c7_13_scanin[4]
//  ff_l2d_l2b_decc_out_c7_11_scanin[4]
//  ff_l2d_l2b_decc_out_c7_15_scanin[4]
//  ff_l2d_l2b_decc_out_c7_1_scanin[5]
//  ff_l2d_l2b_decc_out_c7_5_scanin[5]
//  ff_l2d_l2b_decc_out_c7_3_scanin[5]
//  ff_l2d_l2b_decc_out_c7_7_scanin[5]
//  ff_l2d_l2b_decc_out_c7_9_scanin[5]
//  ff_l2d_l2b_decc_out_c7_13_scanin[5]
//  ff_l2d_l2b_decc_out_c7_11_scanin[5]
//  ff_l2d_l2b_decc_out_c7_15_scanin[5]
//  ff_l2d_l2b_decc_out_c7_1_scanin[6]
//  ff_l2d_l2b_decc_out_c7_5_scanin[6]
//  ff_l2d_l2b_decc_out_c7_3_scanin[6]
//  ff_l2d_l2b_decc_out_c7_7_scanin[6]
//  ff_l2d_l2b_decc_out_c7_9_scanin[6]
//  ff_l2d_l2b_decc_out_c7_13_scanin[6]
//  ff_l2d_l2b_decc_out_c7_11_scanin[6]
//  ff_l2d_l2b_decc_out_c7_15_scanin[6]
//  ff_l2d_l2b_decc_out_c7_1_scanin[7]
//  ff_l2d_l2b_decc_out_c7_5_scanin[7]
//  ff_l2d_l2b_decc_out_c7_3_scanin[7]
//  ff_l2d_l2b_decc_out_c7_7_scanin[7]
//  ff_l2d_l2b_decc_out_c7_9_scanin[7]
//  ff_l2d_l2b_decc_out_c7_13_scanin[7]
//  ff_l2d_l2b_decc_out_c7_11_scanin[7]
//  ff_l2d_l2b_decc_out_c7_15_scanin[7]
//  ff_l2d_l2b_decc_out_c7_1_scanin[8]
//  ff_l2d_l2b_decc_out_c7_5_scanin[8]
//  ff_l2d_l2b_decc_out_c7_3_scanin[8]
//  ff_l2d_l2b_decc_out_c7_7_scanin[8]
//  ff_l2d_l2b_decc_out_c7_9_scanin[8]
//  ff_l2d_l2b_decc_out_c7_13_scanin[8]
//  ff_l2d_l2b_decc_out_c7_11_scanin[8]
//  ff_l2d_l2b_decc_out_c7_15_scanin[8]
//  ff_l2d_l2b_decc_out_c7_1_scanin[9]
//  ff_l2d_l2b_decc_out_c7_5_scanin[9]
//  ff_l2d_l2b_decc_out_c7_3_scanin[9]
//  ff_l2d_l2b_decc_out_c7_7_scanin[9]
//  ff_l2d_l2b_decc_out_c7_9_scanin[9]
//  ff_l2d_l2b_decc_out_c7_13_scanin[9]
//  ff_l2d_l2b_decc_out_c7_11_scanin[9]
//  ff_l2d_l2b_decc_out_c7_15_scanin[9]
//  ff_l2d_l2b_decc_out_c7_1_scanin[10]
//  ff_l2d_l2b_decc_out_c7_5_scanin[10]
//  ff_l2d_l2b_decc_out_c7_3_scanin[10]
//  ff_l2d_l2b_decc_out_c7_7_scanin[10]
//  ff_l2d_l2b_decc_out_c7_9_scanin[10]
//  ff_l2d_l2b_decc_out_c7_13_scanin[10]
//  ff_l2d_l2b_decc_out_c7_11_scanin[10]
//  ff_l2d_l2b_decc_out_c7_15_scanin[10]
//  ff_l2d_l2b_decc_out_c7_1_scanin[11]
//  ff_l2d_l2b_decc_out_c7_5_scanin[11]
//  ff_l2d_l2b_decc_out_c7_3_scanin[11]
//  ff_l2d_l2b_decc_out_c7_7_scanin[11]
//  ff_l2d_l2b_decc_out_c7_9_scanin[11]
//  ff_l2d_l2b_decc_out_c7_13_scanin[11]
//  ff_l2d_l2b_decc_out_c7_11_scanin[11]
//  ff_l2d_l2b_decc_out_c7_15_scanin[11]
//  ff_l2d_l2b_decc_out_c7_1_scanin[12]
//  ff_l2d_l2b_decc_out_c7_5_scanin[12]
//  ff_l2d_l2b_decc_out_c7_3_scanin[12]
//  ff_l2d_l2b_decc_out_c7_7_scanin[12]
//  ff_l2d_l2b_decc_out_c7_9_scanin[12]
//  ff_l2d_l2b_decc_out_c7_13_scanin[12]
//  ff_l2d_l2b_decc_out_c7_11_scanin[12]
//  ff_l2d_l2b_decc_out_c7_15_scanin[12]
//  ff_l2d_l2b_decc_out_c7_1_scanin[13]
//  ff_l2d_l2b_decc_out_c7_5_scanin[13]
//  ff_l2d_l2b_decc_out_c7_3_scanin[13]
//  ff_l2d_l2b_decc_out_c7_7_scanin[13]
//  ff_l2d_l2b_decc_out_c7_9_scanin[13]
//  ff_l2d_l2b_decc_out_c7_13_scanin[13]
//  ff_l2d_l2b_decc_out_c7_11_scanin[13]
//  ff_l2d_l2b_decc_out_c7_15_scanin[13]
//  ff_l2d_l2b_decc_out_c7_1_scanin[14]
//  ff_l2d_l2b_decc_out_c7_5_scanin[14]
//  ff_l2d_l2b_decc_out_c7_3_scanin[14]
//  ff_l2d_l2b_decc_out_c7_7_scanin[14]
//  ff_l2d_l2b_decc_out_c7_9_scanin[14]
//  ff_l2d_l2b_decc_out_c7_13_scanin[14]
//  ff_l2d_l2b_decc_out_c7_11_scanin[14]
//  ff_l2d_l2b_decc_out_c7_15_scanin[14]
//  ff_l2d_l2b_decc_out_c7_1_scanin[15]
//  ff_l2d_l2b_decc_out_c7_5_scanin[15]
//  ff_l2d_l2b_decc_out_c7_3_scanin[15]
//  ff_l2d_l2b_decc_out_c7_7_scanin[15]
//  ff_l2d_l2b_decc_out_c7_9_scanin[15]
//  ff_l2d_l2b_decc_out_c7_13_scanin[15]
//  ff_l2d_l2b_decc_out_c7_11_scanin[15]
//  ff_l2d_l2b_decc_out_c7_15_scanin[15]
//  ff_l2d_l2b_decc_out_c7_1_scanin[16]
//  ff_l2d_l2b_decc_out_c7_5_scanin[16]
//  ff_l2d_l2b_decc_out_c7_3_scanin[16]
//  ff_l2d_l2b_decc_out_c7_7_scanin[16]
//  ff_l2d_l2b_decc_out_c7_9_scanin[16]
//  ff_l2d_l2b_decc_out_c7_13_scanin[16]
//  ff_l2d_l2b_decc_out_c7_11_scanin[16]
//  ff_l2d_l2b_decc_out_c7_15_scanin[16]
//  ff_l2d_l2b_decc_out_c7_1_scanin[17]
//  ff_l2d_l2b_decc_out_c7_5_scanin[17]
//  ff_l2d_l2b_decc_out_c7_3_scanin[17]
//  ff_l2d_l2b_decc_out_c7_7_scanin[17]
//  ff_l2d_l2b_decc_out_c7_9_scanin[17]
//  ff_l2d_l2b_decc_out_c7_13_scanin[17]
//  ff_l2d_l2b_decc_out_c7_11_scanin[17]
//  ff_l2d_l2b_decc_out_c7_15_scanin[17]
//  ff_l2d_l2b_decc_out_c7_1_scanin[18]
//  ff_l2d_l2b_decc_out_c7_5_scanin[18]
//  ff_l2d_l2b_decc_out_c7_3_scanin[18]
//  ff_l2d_l2b_decc_out_c7_7_scanin[18]
//  ff_l2d_l2b_decc_out_c7_9_scanin[18]
//  ff_l2d_l2b_decc_out_c7_13_scanin[18]
//  ff_l2d_l2b_decc_out_c7_11_scanin[18]
//  ff_l2d_l2b_decc_out_c7_15_scanin[18]
//  ff_l2d_l2b_decc_out_c7_1_scanin[19]
//  ff_l2d_l2b_decc_out_c7_5_scanin[19]
//  ff_l2d_l2b_decc_out_c7_3_scanin[19]
//  ff_l2d_l2b_decc_out_c7_7_scanin[19]
//  ff_l2d_l2b_decc_out_c7_9_scanin[19]
//  ff_l2d_l2b_decc_out_c7_13_scanin[19]
//  ff_l2d_l2b_decc_out_c7_11_scanin[19]
//  ff_l2d_l2b_decc_out_c7_15_scanin[19]
//  ff_l2d_l2b_decc_out_c7_1_scanin[20]
//  ff_l2d_l2b_decc_out_c7_5_scanin[20]
//  ff_l2d_l2b_decc_out_c7_3_scanin[20]
//  ff_l2d_l2b_decc_out_c7_7_scanin[20]
//  ff_l2d_l2b_decc_out_c7_9_scanin[20]
//  ff_l2d_l2b_decc_out_c7_13_scanin[20]
//  ff_l2d_l2b_decc_out_c7_11_scanin[20]
//  ff_l2d_l2b_decc_out_c7_15_scanin[20]
//  ff_l2d_l2b_decc_out_c7_1_scanin[21]
//  ff_l2d_l2b_decc_out_c7_5_scanin[21]
//  ff_l2d_l2b_decc_out_c7_3_scanin[21]
//  ff_l2d_l2b_decc_out_c7_7_scanin[21]
//  ff_l2d_l2b_decc_out_c7_9_scanin[21]
//  ff_l2d_l2b_decc_out_c7_13_scanin[21]
//  ff_l2d_l2b_decc_out_c7_11_scanin[21]
//  ff_l2d_l2b_decc_out_c7_15_scanin[21]
//  ff_l2d_l2b_decc_out_c7_1_scanin[22]
//  ff_l2d_l2b_decc_out_c7_5_scanin[22]
//  ff_l2d_l2b_decc_out_c7_3_scanin[22]
//  ff_l2d_l2b_decc_out_c7_7_scanin[22]
//  ff_l2d_l2b_decc_out_c7_9_scanin[22]
//  ff_l2d_l2b_decc_out_c7_13_scanin[22]
//  ff_l2d_l2b_decc_out_c7_11_scanin[22]
//  ff_l2d_l2b_decc_out_c7_15_scanin[22]
//  ff_l2d_l2b_decc_out_c7_1_scanin[23]
//  ff_l2d_l2b_decc_out_c7_5_scanin[23]
//  ff_l2d_l2b_decc_out_c7_3_scanin[23]
//  ff_l2d_l2b_decc_out_c7_7_scanin[23]
//  ff_l2d_l2b_decc_out_c7_9_scanin[23]
//  ff_l2d_l2b_decc_out_c7_13_scanin[23]
//  ff_l2d_l2b_decc_out_c7_11_scanin[23]
//  ff_l2d_l2b_decc_out_c7_15_scanin[23]
//  ff_l2d_l2b_decc_out_c7_1_scanin[24]
//  ff_l2d_l2b_decc_out_c7_5_scanin[24]
//  ff_l2d_l2b_decc_out_c7_3_scanin[24]
//  ff_l2d_l2b_decc_out_c7_7_scanin[24]
//  ff_l2d_l2b_decc_out_c7_9_scanin[24]
//  ff_l2d_l2b_decc_out_c7_13_scanin[24]
//  ff_l2d_l2b_decc_out_c7_11_scanin[24]
//  ff_l2d_l2b_decc_out_c7_15_scanin[24]
//  ff_l2d_l2b_decc_out_c7_1_scanin[25]
//  ff_l2d_l2b_decc_out_c7_5_scanin[25]
//  ff_l2d_l2b_decc_out_c7_3_scanin[25]
//  ff_l2d_l2b_decc_out_c7_7_scanin[25]
//  ff_l2d_l2b_decc_out_c7_9_scanin[25]
//  ff_l2d_l2b_decc_out_c7_13_scanin[25]
//  ff_l2d_l2b_decc_out_c7_11_scanin[25]
//  ff_l2d_l2b_decc_out_c7_15_scanin[25]
//  ff_l2d_l2b_decc_out_c7_1_scanin[26]
//  ff_l2d_l2b_decc_out_c7_5_scanin[26]
//  ff_l2d_l2b_decc_out_c7_3_scanin[26]
//  ff_l2d_l2b_decc_out_c7_7_scanin[26]
//  ff_l2d_l2b_decc_out_c7_9_scanin[26]
//  ff_l2d_l2b_decc_out_c7_13_scanin[26]
//  ff_l2d_l2b_decc_out_c7_11_scanin[26]
//  ff_l2d_l2b_decc_out_c7_15_scanin[26]
//  ff_l2d_l2b_decc_out_c7_1_scanin[27]
//  ff_l2d_l2b_decc_out_c7_5_scanin[27]
//  ff_l2d_l2b_decc_out_c7_3_scanin[27]
//  ff_l2d_l2b_decc_out_c7_7_scanin[27]
//  ff_l2d_l2b_decc_out_c7_9_scanin[27]
//  ff_l2d_l2b_decc_out_c7_13_scanin[27]
//  ff_l2d_l2b_decc_out_c7_11_scanin[27]
//  ff_l2d_l2b_decc_out_c7_15_scanin[27]
//  ff_l2d_l2b_decc_out_c7_1_scanin[28]
//  ff_l2d_l2b_decc_out_c7_5_scanin[28]
//  ff_l2d_l2b_decc_out_c7_3_scanin[28]
//  ff_l2d_l2b_decc_out_c7_7_scanin[28]
//  ff_l2d_l2b_decc_out_c7_9_scanin[28]
//  ff_l2d_l2b_decc_out_c7_13_scanin[28]
//  ff_l2d_l2b_decc_out_c7_11_scanin[28]
//  ff_l2d_l2b_decc_out_c7_15_scanin[28]
//  ff_l2d_l2b_decc_out_c7_1_scanin[29]
//  ff_l2d_l2b_decc_out_c7_5_scanin[29]
//  ff_l2d_l2b_decc_out_c7_3_scanin[29]
//  ff_l2d_l2b_decc_out_c7_7_scanin[29]
//  ff_l2d_l2b_decc_out_c7_9_scanin[29]
//  ff_l2d_l2b_decc_out_c7_13_scanin[29]
//  ff_l2d_l2b_decc_out_c7_11_scanin[29]
//  ff_l2d_l2b_decc_out_c7_15_scanin[29]
//  ff_l2d_l2b_decc_out_c7_1_scanin[30]
//  ff_l2d_l2b_decc_out_c7_5_scanin[30]
//  ff_l2d_l2b_decc_out_c7_3_scanin[30]
//  ff_l2d_l2b_decc_out_c7_7_scanin[30]
//  ff_l2d_l2b_decc_out_c7_9_scanin[30]
//  ff_l2d_l2b_decc_out_c7_13_scanin[30]
//  ff_l2d_l2b_decc_out_c7_11_scanin[30]
//  ff_l2d_l2b_decc_out_c7_15_scanin[30]
//  ff_l2d_l2b_decc_out_c7_1_scanin[31]
//  ff_l2d_l2b_decc_out_c7_5_scanin[31]
//  ff_l2d_l2b_decc_out_c7_3_scanin[31]
//  ff_l2d_l2b_decc_out_c7_7_scanin[31]
//  ff_l2d_l2b_decc_out_c7_9_scanin[31]
//  ff_l2d_l2b_decc_out_c7_13_scanin[31]
//  ff_l2d_l2b_decc_out_c7_11_scanin[31]
//  ff_l2d_l2b_decc_out_c7_15_scanin[31]
//  ff_l2d_l2b_decc_out_c7_1_scanin[32]
//  ff_l2d_l2b_decc_out_c7_5_scanin[32]
//  ff_l2d_l2b_decc_out_c7_3_scanin[32]
//  ff_l2d_l2b_decc_out_c7_7_scanin[32]
//  ff_l2d_l2b_decc_out_c7_9_scanin[32]
//  ff_l2d_l2b_decc_out_c7_13_scanin[32]
//  ff_l2d_l2b_decc_out_c7_11_scanin[32]
//  ff_l2d_l2b_decc_out_c7_15_scanin[32]
//  ff_l2d_l2b_decc_out_c7_1_scanin[33]
//  ff_l2d_l2b_decc_out_c7_5_scanin[33]
//  ff_l2d_l2b_decc_out_c7_3_scanin[33]
//  ff_l2d_l2b_decc_out_c7_7_scanin[33]
//  ff_l2d_l2b_decc_out_c7_9_scanin[33]
//  ff_l2d_l2b_decc_out_c7_13_scanin[33]
//  ff_l2d_l2b_decc_out_c7_11_scanin[33]
//  ff_l2d_l2b_decc_out_c7_15_scanin[33]
//  ff_l2d_l2b_decc_out_c7_1_scanin[34]
//  ff_l2d_l2b_decc_out_c7_5_scanin[34]
//  ff_l2d_l2b_decc_out_c7_3_scanin[34]
//  ff_l2d_l2b_decc_out_c7_7_scanin[34]
//  ff_l2d_l2b_decc_out_c7_9_scanin[34]
//  ff_l2d_l2b_decc_out_c7_13_scanin[34]
//  ff_l2d_l2b_decc_out_c7_11_scanin[34]
//  ff_l2d_l2b_decc_out_c7_15_scanin[34]
//  ff_l2d_l2b_decc_out_c7_1_scanin[35]
//  ff_l2d_l2b_decc_out_c7_5_scanin[35]
//  ff_l2d_l2b_decc_out_c7_3_scanin[35]
//  ff_l2d_l2b_decc_out_c7_7_scanin[35]
//  ff_l2d_l2b_decc_out_c7_9_scanin[35]
//  ff_l2d_l2b_decc_out_c7_13_scanin[35]
//  ff_l2d_l2b_decc_out_c7_11_scanin[35]
//  ff_l2d_l2b_decc_out_c7_15_scanin[35]
//  ff_l2d_l2b_decc_out_c7_1_scanin[36]
//  ff_l2d_l2b_decc_out_c7_5_scanin[36]
//  ff_l2d_l2b_decc_out_c7_3_scanin[36]
//  ff_l2d_l2b_decc_out_c7_7_scanin[36]
//  ff_l2d_l2b_decc_out_c7_9_scanin[36]
//  ff_l2d_l2b_decc_out_c7_13_scanin[36]
//  ff_l2d_l2b_decc_out_c7_11_scanin[36]
//  ff_l2d_l2b_decc_out_c7_15_scanin[36]
//  ff_l2d_l2b_decc_out_c7_1_scanin[37]
//  ff_l2d_l2b_decc_out_c7_5_scanin[37]
//  ff_l2d_l2b_decc_out_c7_3_scanin[37]
//  ff_l2d_l2b_decc_out_c7_7_scanin[37]
//  ff_l2d_l2b_decc_out_c7_9_scanin[37]
//  ff_l2d_l2b_decc_out_c7_13_scanin[37]
//  ff_l2d_l2b_decc_out_c7_11_scanin[37]
//  ff_l2d_l2b_decc_out_c7_15_scanin[37]
//  ff_l2d_l2b_decc_out_c7_1_scanin[38]
//  ff_l2d_l2b_decc_out_c7_5_scanin[38]
//  ff_l2d_l2b_decc_out_c7_3_scanin[38]
//  ff_l2d_l2b_decc_out_c7_7_scanin[38]
//  ff_l2d_l2b_decc_out_c7_9_scanin[38]
//  ff_l2d_l2b_decc_out_c7_13_scanin[38]
//  ff_l2d_l2b_decc_out_c7_11_scanin[38]
//  ff_l2d_l2b_decc_out_c7_15_scanin[38]
//  ff_l2d_l2b_decc_out_c7_2_scanin[0]
//  ff_l2d_l2b_decc_out_c7_6_scanin[0]
//  ff_l2d_l2b_decc_out_c7_4_scanin[0]
//  ff_l2d_l2b_decc_out_c7_8_scanin[0]
//  ff_l2d_l2b_decc_out_c7_10_scanin[0]
//  ff_l2d_l2b_decc_out_c7_14_scanin[0]
//  ff_l2d_l2b_decc_out_c7_12_scanin[0]
//  ff_l2d_l2b_decc_out_c7_16_scanin[0]
//  ff_l2d_l2b_decc_out_c7_2_scanin[1]
//  ff_l2d_l2b_decc_out_c7_6_scanin[1]
//  ff_l2d_l2b_decc_out_c7_4_scanin[1]
//  ff_l2d_l2b_decc_out_c7_8_scanin[1]
//  ff_l2d_l2b_decc_out_c7_10_scanin[1]
//  ff_l2d_l2b_decc_out_c7_14_scanin[1]
//  ff_l2d_l2b_decc_out_c7_12_scanin[1]
//  ff_l2d_l2b_decc_out_c7_16_scanin[1]
//  ff_l2d_l2b_decc_out_c7_2_scanin[2]
//  ff_l2d_l2b_decc_out_c7_6_scanin[2]
//  ff_l2d_l2b_decc_out_c7_4_scanin[2]
//  ff_l2d_l2b_decc_out_c7_8_scanin[2]
//  ff_l2d_l2b_decc_out_c7_10_scanin[2]
//  ff_l2d_l2b_decc_out_c7_14_scanin[2]
//  ff_l2d_l2b_decc_out_c7_12_scanin[2]
//  ff_l2d_l2b_decc_out_c7_16_scanin[2]
//  ff_l2d_l2b_decc_out_c7_2_scanin[3]
//  ff_l2d_l2b_decc_out_c7_6_scanin[3]
//  ff_l2d_l2b_decc_out_c7_4_scanin[3]
//  ff_l2d_l2b_decc_out_c7_8_scanin[3]
//  ff_l2d_l2b_decc_out_c7_10_scanin[3]
//  ff_l2d_l2b_decc_out_c7_14_scanin[3]
//  ff_l2d_l2b_decc_out_c7_12_scanin[3]
//  ff_l2d_l2b_decc_out_c7_16_scanin[3]
//  ff_l2d_l2b_decc_out_c7_2_scanin[4]
//  ff_l2d_l2b_decc_out_c7_6_scanin[4]
//  ff_l2d_l2b_decc_out_c7_4_scanin[4]
//  ff_l2d_l2b_decc_out_c7_8_scanin[4]
//  ff_l2d_l2b_decc_out_c7_10_scanin[4]
//  ff_l2d_l2b_decc_out_c7_14_scanin[4]
//  ff_l2d_l2b_decc_out_c7_12_scanin[4]
//  ff_l2d_l2b_decc_out_c7_16_scanin[4]
//  ff_l2d_l2b_decc_out_c7_2_scanin[5]
//  ff_l2d_l2b_decc_out_c7_6_scanin[5]
//  ff_l2d_l2b_decc_out_c7_4_scanin[5]
//  ff_l2d_l2b_decc_out_c7_8_scanin[5]
//  ff_l2d_l2b_decc_out_c7_10_scanin[5]
//  ff_l2d_l2b_decc_out_c7_14_scanin[5]
//  ff_l2d_l2b_decc_out_c7_12_scanin[5]
//  ff_l2d_l2b_decc_out_c7_16_scanin[5]
//  ff_l2d_l2b_decc_out_c7_2_scanin[6]
//  ff_l2d_l2b_decc_out_c7_6_scanin[6]
//  ff_l2d_l2b_decc_out_c7_4_scanin[6]
//  ff_l2d_l2b_decc_out_c7_8_scanin[6]
//  ff_l2d_l2b_decc_out_c7_10_scanin[6]
//  ff_l2d_l2b_decc_out_c7_14_scanin[6]
//  ff_l2d_l2b_decc_out_c7_12_scanin[6]
//  ff_l2d_l2b_decc_out_c7_16_scanin[6]
//  ff_l2d_l2b_decc_out_c7_2_scanin[7]
//  ff_l2d_l2b_decc_out_c7_6_scanin[7]
//  ff_l2d_l2b_decc_out_c7_4_scanin[7]
//  ff_l2d_l2b_decc_out_c7_8_scanin[7]
//  ff_l2d_l2b_decc_out_c7_10_scanin[7]
//  ff_l2d_l2b_decc_out_c7_14_scanin[7]
//  ff_l2d_l2b_decc_out_c7_12_scanin[7]
//  ff_l2d_l2b_decc_out_c7_16_scanin[7]
//  ff_l2d_l2b_decc_out_c7_2_scanin[8]
//  ff_l2d_l2b_decc_out_c7_6_scanin[8]
//  ff_l2d_l2b_decc_out_c7_4_scanin[8]
//  ff_l2d_l2b_decc_out_c7_8_scanin[8]
//  ff_l2d_l2b_decc_out_c7_10_scanin[8]
//  ff_l2d_l2b_decc_out_c7_14_scanin[8]
//  ff_l2d_l2b_decc_out_c7_12_scanin[8]
//  ff_l2d_l2b_decc_out_c7_16_scanin[8]
//  ff_l2d_l2b_decc_out_c7_2_scanin[9]
//  ff_l2d_l2b_decc_out_c7_6_scanin[9]
//  ff_l2d_l2b_decc_out_c7_4_scanin[9]
//  ff_l2d_l2b_decc_out_c7_8_scanin[9]
//  ff_l2d_l2b_decc_out_c7_10_scanin[9]
//  ff_l2d_l2b_decc_out_c7_14_scanin[9]
//  ff_l2d_l2b_decc_out_c7_12_scanin[9]
//  ff_l2d_l2b_decc_out_c7_16_scanin[9]
//  ff_l2d_l2b_decc_out_c7_2_scanin[10]
//  ff_l2d_l2b_decc_out_c7_6_scanin[10]
//  ff_l2d_l2b_decc_out_c7_4_scanin[10]
//  ff_l2d_l2b_decc_out_c7_8_scanin[10]
//  ff_l2d_l2b_decc_out_c7_10_scanin[10]
//  ff_l2d_l2b_decc_out_c7_14_scanin[10]
//  ff_l2d_l2b_decc_out_c7_12_scanin[10]
//  ff_l2d_l2b_decc_out_c7_16_scanin[10]
//  ff_l2d_l2b_decc_out_c7_2_scanin[11]
//  ff_l2d_l2b_decc_out_c7_6_scanin[11]
//  ff_l2d_l2b_decc_out_c7_4_scanin[11]
//  ff_l2d_l2b_decc_out_c7_8_scanin[11]
//  ff_l2d_l2b_decc_out_c7_10_scanin[11]
//  ff_l2d_l2b_decc_out_c7_14_scanin[11]
//  ff_l2d_l2b_decc_out_c7_12_scanin[11]
//  ff_l2d_l2b_decc_out_c7_16_scanin[11]
//  ff_l2d_l2b_decc_out_c7_2_scanin[12]
//  ff_l2d_l2b_decc_out_c7_6_scanin[12]
//  ff_l2d_l2b_decc_out_c7_4_scanin[12]
//  ff_l2d_l2b_decc_out_c7_8_scanin[12]
//  ff_l2d_l2b_decc_out_c7_10_scanin[12]
//  ff_l2d_l2b_decc_out_c7_14_scanin[12]
//  ff_l2d_l2b_decc_out_c7_12_scanin[12]
//  ff_l2d_l2b_decc_out_c7_16_scanin[12]
//  ff_l2d_l2b_decc_out_c7_2_scanin[13]
//  ff_l2d_l2b_decc_out_c7_6_scanin[13]
//  ff_l2d_l2b_decc_out_c7_4_scanin[13]
//  ff_l2d_l2b_decc_out_c7_8_scanin[13]
//  ff_l2d_l2b_decc_out_c7_10_scanin[13]
//  ff_l2d_l2b_decc_out_c7_14_scanin[13]
//  ff_l2d_l2b_decc_out_c7_12_scanin[13]
//  ff_l2d_l2b_decc_out_c7_16_scanin[13]
//  ff_l2d_l2b_decc_out_c7_2_scanin[14]
//  ff_l2d_l2b_decc_out_c7_6_scanin[14]
//  ff_l2d_l2b_decc_out_c7_4_scanin[14]
//  ff_l2d_l2b_decc_out_c7_8_scanin[14]
//  ff_l2d_l2b_decc_out_c7_10_scanin[14]
//  ff_l2d_l2b_decc_out_c7_14_scanin[14]
//  ff_l2d_l2b_decc_out_c7_12_scanin[14]
//  ff_l2d_l2b_decc_out_c7_16_scanin[14]
//  ff_l2d_l2b_decc_out_c7_2_scanin[15]
//  ff_l2d_l2b_decc_out_c7_6_scanin[15]
//  ff_l2d_l2b_decc_out_c7_4_scanin[15]
//  ff_l2d_l2b_decc_out_c7_8_scanin[15]
//  ff_l2d_l2b_decc_out_c7_10_scanin[15]
//  ff_l2d_l2b_decc_out_c7_14_scanin[15]
//  ff_l2d_l2b_decc_out_c7_12_scanin[15]
//  ff_l2d_l2b_decc_out_c7_16_scanin[15]
//  ff_l2d_l2b_decc_out_c7_2_scanin[16]
//  ff_l2d_l2b_decc_out_c7_6_scanin[16]
//  ff_l2d_l2b_decc_out_c7_4_scanin[16]
//  ff_l2d_l2b_decc_out_c7_8_scanin[16]
//  ff_l2d_l2b_decc_out_c7_10_scanin[16]
//  ff_l2d_l2b_decc_out_c7_14_scanin[16]
//  ff_l2d_l2b_decc_out_c7_12_scanin[16]
//  ff_l2d_l2b_decc_out_c7_16_scanin[16]
//  ff_l2d_l2b_decc_out_c7_2_scanin[17]
//  ff_l2d_l2b_decc_out_c7_6_scanin[17]
//  ff_l2d_l2b_decc_out_c7_4_scanin[17]
//  ff_l2d_l2b_decc_out_c7_8_scanin[17]
//  ff_l2d_l2b_decc_out_c7_10_scanin[17]
//  ff_l2d_l2b_decc_out_c7_14_scanin[17]
//  ff_l2d_l2b_decc_out_c7_12_scanin[17]
//  ff_l2d_l2b_decc_out_c7_16_scanin[17]
//  ff_l2d_l2b_decc_out_c7_2_scanin[18]
//  ff_l2d_l2b_decc_out_c7_6_scanin[18]
//  ff_l2d_l2b_decc_out_c7_4_scanin[18]
//  ff_l2d_l2b_decc_out_c7_8_scanin[18]
//  ff_l2d_l2b_decc_out_c7_10_scanin[18]
//  ff_l2d_l2b_decc_out_c7_14_scanin[18]
//  ff_l2d_l2b_decc_out_c7_12_scanin[18]
//  ff_l2d_l2b_decc_out_c7_16_scanin[18]
//  ff_l2d_l2b_decc_out_c7_2_scanin[19]
//  ff_l2d_l2b_decc_out_c7_6_scanin[19]
//  ff_l2d_l2b_decc_out_c7_4_scanin[19]
//  ff_l2d_l2b_decc_out_c7_8_scanin[19]
//  ff_l2d_l2b_decc_out_c7_10_scanin[19]
//  ff_l2d_l2b_decc_out_c7_14_scanin[19]
//  ff_l2d_l2b_decc_out_c7_12_scanin[19]
//  ff_l2d_l2b_decc_out_c7_16_scanin[19]
//  ff_l2d_l2b_decc_out_c7_2_scanin[20]
//  ff_l2d_l2b_decc_out_c7_6_scanin[20]
//  ff_l2d_l2b_decc_out_c7_4_scanin[20]
//  ff_l2d_l2b_decc_out_c7_8_scanin[20]
//  ff_l2d_l2b_decc_out_c7_10_scanin[20]
//  ff_l2d_l2b_decc_out_c7_14_scanin[20]
//  ff_l2d_l2b_decc_out_c7_12_scanin[20]
//  ff_l2d_l2b_decc_out_c7_16_scanin[20]
//  ff_l2d_l2b_decc_out_c7_2_scanin[21]
//  ff_l2d_l2b_decc_out_c7_6_scanin[21]
//  ff_l2d_l2b_decc_out_c7_4_scanin[21]
//  ff_l2d_l2b_decc_out_c7_8_scanin[21]
//  ff_l2d_l2b_decc_out_c7_10_scanin[21]
//  ff_l2d_l2b_decc_out_c7_14_scanin[21]
//  ff_l2d_l2b_decc_out_c7_12_scanin[21]
//  ff_l2d_l2b_decc_out_c7_16_scanin[21]
//  ff_l2d_l2b_decc_out_c7_2_scanin[22]
//  ff_l2d_l2b_decc_out_c7_6_scanin[22]
//  ff_l2d_l2b_decc_out_c7_4_scanin[22]
//  ff_l2d_l2b_decc_out_c7_8_scanin[22]
//  ff_l2d_l2b_decc_out_c7_10_scanin[22]
//  ff_l2d_l2b_decc_out_c7_14_scanin[22]
//  ff_l2d_l2b_decc_out_c7_12_scanin[22]
//  ff_l2d_l2b_decc_out_c7_16_scanin[22]
//  ff_l2d_l2b_decc_out_c7_2_scanin[23]
//  ff_l2d_l2b_decc_out_c7_6_scanin[23]
//  ff_l2d_l2b_decc_out_c7_4_scanin[23]
//  ff_l2d_l2b_decc_out_c7_8_scanin[23]
//  ff_l2d_l2b_decc_out_c7_10_scanin[23]
//  ff_l2d_l2b_decc_out_c7_14_scanin[23]
//  ff_l2d_l2b_decc_out_c7_12_scanin[23]
//  ff_l2d_l2b_decc_out_c7_16_scanin[23]
//  ff_l2d_l2b_decc_out_c7_2_scanin[24]
//  ff_l2d_l2b_decc_out_c7_6_scanin[24]
//  ff_l2d_l2b_decc_out_c7_4_scanin[24]
//  ff_l2d_l2b_decc_out_c7_8_scanin[24]
//  ff_l2d_l2b_decc_out_c7_10_scanin[24]
//  ff_l2d_l2b_decc_out_c7_14_scanin[24]
//  ff_l2d_l2b_decc_out_c7_12_scanin[24]
//  ff_l2d_l2b_decc_out_c7_16_scanin[24]
//  ff_l2d_l2b_decc_out_c7_2_scanin[25]
//  ff_l2d_l2b_decc_out_c7_6_scanin[25]
//  ff_l2d_l2b_decc_out_c7_4_scanin[25]
//  ff_l2d_l2b_decc_out_c7_8_scanin[25]
//  ff_l2d_l2b_decc_out_c7_10_scanin[25]
//  ff_l2d_l2b_decc_out_c7_14_scanin[25]
//  ff_l2d_l2b_decc_out_c7_12_scanin[25]
//  ff_l2d_l2b_decc_out_c7_16_scanin[25]
//  ff_l2d_l2b_decc_out_c7_2_scanin[26]
//  ff_l2d_l2b_decc_out_c7_6_scanin[26]
//  ff_l2d_l2b_decc_out_c7_4_scanin[26]
//  ff_l2d_l2b_decc_out_c7_8_scanin[26]
//  ff_l2d_l2b_decc_out_c7_10_scanin[26]
//  ff_l2d_l2b_decc_out_c7_14_scanin[26]
//  ff_l2d_l2b_decc_out_c7_12_scanin[26]
//  ff_l2d_l2b_decc_out_c7_16_scanin[26]
//  ff_l2d_l2b_decc_out_c7_2_scanin[27]
//  ff_l2d_l2b_decc_out_c7_6_scanin[27]
//  ff_l2d_l2b_decc_out_c7_4_scanin[27]
//  ff_l2d_l2b_decc_out_c7_8_scanin[27]
//  ff_l2d_l2b_decc_out_c7_10_scanin[27]
//  ff_l2d_l2b_decc_out_c7_14_scanin[27]
//  ff_l2d_l2b_decc_out_c7_12_scanin[27]
//  ff_l2d_l2b_decc_out_c7_16_scanin[27]
//  ff_l2d_l2b_decc_out_c7_2_scanin[28]
//  ff_l2d_l2b_decc_out_c7_6_scanin[28]
//  ff_l2d_l2b_decc_out_c7_4_scanin[28]
//  ff_l2d_l2b_decc_out_c7_8_scanin[28]
//  ff_l2d_l2b_decc_out_c7_10_scanin[28]
//  ff_l2d_l2b_decc_out_c7_14_scanin[28]
//  ff_l2d_l2b_decc_out_c7_12_scanin[28]
//  ff_l2d_l2b_decc_out_c7_16_scanin[28]
//  ff_l2d_l2b_decc_out_c7_2_scanin[29]
//  ff_l2d_l2b_decc_out_c7_6_scanin[29]
//  ff_l2d_l2b_decc_out_c7_4_scanin[29]
//  ff_l2d_l2b_decc_out_c7_8_scanin[29]
//  ff_l2d_l2b_decc_out_c7_10_scanin[29]
//  ff_l2d_l2b_decc_out_c7_14_scanin[29]
//  ff_l2d_l2b_decc_out_c7_12_scanin[29]
//  ff_l2d_l2b_decc_out_c7_16_scanin[29]
//  ff_l2d_l2b_decc_out_c7_2_scanin[30]
//  ff_l2d_l2b_decc_out_c7_6_scanin[30]
//  ff_l2d_l2b_decc_out_c7_4_scanin[30]
//  ff_l2d_l2b_decc_out_c7_8_scanin[30]
//  ff_l2d_l2b_decc_out_c7_10_scanin[30]
//  ff_l2d_l2b_decc_out_c7_14_scanin[30]
//  ff_l2d_l2b_decc_out_c7_12_scanin[30]
//  ff_l2d_l2b_decc_out_c7_16_scanin[30]
//  ff_l2d_l2b_decc_out_c7_2_scanin[31]
//  ff_l2d_l2b_decc_out_c7_6_scanin[31]
//  ff_l2d_l2b_decc_out_c7_4_scanin[31]
//  ff_l2d_l2b_decc_out_c7_8_scanin[31]
//  ff_l2d_l2b_decc_out_c7_10_scanin[31]
//  ff_l2d_l2b_decc_out_c7_14_scanin[31]
//  ff_l2d_l2b_decc_out_c7_12_scanin[31]
//  ff_l2d_l2b_decc_out_c7_16_scanin[31]
//  ff_l2d_l2b_decc_out_c7_2_scanin[32]
//  ff_l2d_l2b_decc_out_c7_6_scanin[32]
//  ff_l2d_l2b_decc_out_c7_4_scanin[32]
//  ff_l2d_l2b_decc_out_c7_8_scanin[32]
//  ff_l2d_l2b_decc_out_c7_10_scanin[32]
//  ff_l2d_l2b_decc_out_c7_14_scanin[32]
//  ff_l2d_l2b_decc_out_c7_12_scanin[32]
//  ff_l2d_l2b_decc_out_c7_16_scanin[32]
//  ff_l2d_l2b_decc_out_c7_2_scanin[33]
//  ff_l2d_l2b_decc_out_c7_6_scanin[33]
//  ff_l2d_l2b_decc_out_c7_4_scanin[33]
//  ff_l2d_l2b_decc_out_c7_8_scanin[33]
//  ff_l2d_l2b_decc_out_c7_10_scanin[33]
//  ff_l2d_l2b_decc_out_c7_14_scanin[33]
//  ff_l2d_l2b_decc_out_c7_12_scanin[33]
//  ff_l2d_l2b_decc_out_c7_16_scanin[33]
//  ff_l2d_l2b_decc_out_c7_2_scanin[34]
//  ff_l2d_l2b_decc_out_c7_6_scanin[34]
//  ff_l2d_l2b_decc_out_c7_4_scanin[34]
//  ff_l2d_l2b_decc_out_c7_8_scanin[34]
//  ff_l2d_l2b_decc_out_c7_10_scanin[34]
//  ff_l2d_l2b_decc_out_c7_14_scanin[34]
//  ff_l2d_l2b_decc_out_c7_12_scanin[34]
//  ff_l2d_l2b_decc_out_c7_16_scanin[34]
//  ff_l2d_l2b_decc_out_c7_2_scanin[35]
//  ff_l2d_l2b_decc_out_c7_6_scanin[35]
//  ff_l2d_l2b_decc_out_c7_4_scanin[35]
//  ff_l2d_l2b_decc_out_c7_8_scanin[35]
//  ff_l2d_l2b_decc_out_c7_10_scanin[35]
//  ff_l2d_l2b_decc_out_c7_14_scanin[35]
//  ff_l2d_l2b_decc_out_c7_12_scanin[35]
//  ff_l2d_l2b_decc_out_c7_16_scanin[35]
//  ff_l2d_l2b_decc_out_c7_2_scanin[36]
//  ff_l2d_l2b_decc_out_c7_6_scanin[36]
//  ff_l2d_l2b_decc_out_c7_4_scanin[36]
//  ff_l2d_l2b_decc_out_c7_8_scanin[36]
//  ff_l2d_l2b_decc_out_c7_10_scanin[36]
//  ff_l2d_l2b_decc_out_c7_14_scanin[36]
//  ff_l2d_l2b_decc_out_c7_12_scanin[36]
//  ff_l2d_l2b_decc_out_c7_16_scanin[36]
//  ff_l2d_l2b_decc_out_c7_2_scanin[37]
//  ff_l2d_l2b_decc_out_c7_6_scanin[37]
//  ff_l2d_l2b_decc_out_c7_4_scanin[37]
//  ff_l2d_l2b_decc_out_c7_8_scanin[37]
//  ff_l2d_l2b_decc_out_c7_10_scanin[37]
//  ff_l2d_l2b_decc_out_c7_14_scanin[37]
//  ff_l2d_l2b_decc_out_c7_12_scanin[37]
//  ff_l2d_l2b_decc_out_c7_16_scanin[37]
//  ff_l2d_l2b_decc_out_c7_2_scanin[38]
//  ff_l2d_l2b_decc_out_c7_6_scanin[38]
//  ff_l2d_l2b_decc_out_c7_4_scanin[38]
//  ff_l2d_l2b_decc_out_c7_8_scanin[38]
//  ff_l2d_l2b_decc_out_c7_10_scanin[38]
//  ff_l2d_l2b_decc_out_c7_14_scanin[38]
//  ff_l2d_l2b_decc_out_c7_12_scanin[38]
//  ff_l2d_l2b_decc_out_c7_16_scanin[38]


//  ff_l2d_l2t_decc_c6_scanin[0]
//  ff_l2d_l2t_decc_c6_scanin[78]
//  ff_l2d_l2t_decc_c6_scanin[1]
//  ff_l2d_l2t_decc_c6_scanin[79]
//  ff_l2d_l2t_decc_c6_scanin[2]
//  ff_l2d_l2t_decc_c6_scanin[80]
//  ff_l2d_l2t_decc_c6_scanin[3]
//  ff_l2d_l2t_decc_c6_scanin[81]
//  ff_l2d_l2t_decc_c6_scanin[4]
//  ff_l2d_l2t_decc_c6_scanin[82]
//  ff_l2d_l2t_decc_c6_scanin[5]
//  ff_l2d_l2t_decc_c6_scanin[83]
//  ff_l2d_l2t_decc_c6_scanin[6]
//  ff_l2d_l2t_decc_c6_scanin[84]
//  ff_l2d_l2t_decc_c6_scanin[7]
//  ff_l2d_l2t_decc_c6_scanin[85]
//  ff_l2d_l2t_decc_c6_scanin[8]
//  ff_l2d_l2t_decc_c6_scanin[86]
//  ff_l2d_l2t_decc_c6_scanin[9]
//  ff_l2d_l2t_decc_c6_scanin[87]
//  ff_l2d_l2t_decc_c6_scanin[10]
//  ff_l2d_l2t_decc_c6_scanin[88]
//  ff_l2d_l2t_decc_c6_scanin[11]
//  ff_l2d_l2t_decc_c6_scanin[89]
//  ff_l2d_l2t_decc_c6_scanin[12]
//  ff_l2d_l2t_decc_c6_scanin[90]
//  ff_l2d_l2t_decc_c6_scanin[13]
//  ff_l2d_l2t_decc_c6_scanin[91]
//  ff_l2d_l2t_decc_c6_scanin[14]
//  ff_l2d_l2t_decc_c6_scanin[92]
//  ff_l2d_l2t_decc_c6_scanin[15]
//  ff_l2d_l2t_decc_c6_scanin[93]
//  ff_l2d_l2t_decc_c6_scanin[16]
//  ff_l2d_l2t_decc_c6_scanin[94]
//  ff_l2d_l2t_decc_c6_scanin[17]
//  ff_l2d_l2t_decc_c6_scanin[95]
//  ff_l2d_l2t_decc_c6_scanin[18]
//  ff_l2d_l2t_decc_c6_scanin[96]
//  ff_l2d_l2t_decc_c6_scanin[19]
//  ff_l2d_l2t_decc_c6_scanin[97]
//  ff_l2d_l2t_decc_c6_scanin[20]
//  ff_l2d_l2t_decc_c6_scanin[98]
//  ff_l2d_l2t_decc_c6_scanin[21]
//  ff_l2d_l2t_decc_c6_scanin[99]
//  ff_l2d_l2t_decc_c6_scanin[22]
//  ff_l2d_l2t_decc_c6_scanin[100]
//  ff_l2d_l2t_decc_c6_scanin[23]
//  ff_l2d_l2t_decc_c6_scanin[101]
//  ff_l2d_l2t_decc_c6_scanin[24]
//  ff_l2d_l2t_decc_c6_scanin[102]
//  ff_l2d_l2t_decc_c6_scanin[25]
//  ff_l2d_l2t_decc_c6_scanin[103]
//  ff_l2d_l2t_decc_c6_scanin[26]
//  ff_l2d_l2t_decc_c6_scanin[104]
//  ff_l2d_l2t_decc_c6_scanin[27]
//  ff_l2d_l2t_decc_c6_scanin[105]
//  ff_l2d_l2t_decc_c6_scanin[28]
//  ff_l2d_l2t_decc_c6_scanin[106]
//  ff_l2d_l2t_decc_c6_scanin[29]
//  ff_l2d_l2t_decc_c6_scanin[107]
//  ff_l2d_l2t_decc_c6_scanin[30]
//  ff_l2d_l2t_decc_c6_scanin[108]
//  ff_l2d_l2t_decc_c6_scanin[31]
//  ff_l2d_l2t_decc_c6_scanin[109]
//  ff_l2d_l2t_decc_c6_scanin[32]
//  ff_l2d_l2t_decc_c6_scanin[110]
//  ff_l2d_l2t_decc_c6_scanin[33]
//  ff_l2d_l2t_decc_c6_scanin[111]
//  ff_l2d_l2t_decc_c6_scanin[34]
//  ff_l2d_l2t_decc_c6_scanin[112]
//  ff_l2d_l2t_decc_c6_scanin[35]
//  ff_l2d_l2t_decc_c6_scanin[113]
//  ff_l2d_l2t_decc_c6_scanin[36]
//  ff_l2d_l2t_decc_c6_scanin[114]
//  ff_l2d_l2t_decc_c6_scanin[37]
//  ff_l2d_l2t_decc_c6_scanin[115]
//  ff_l2d_l2t_decc_c6_scanin[38]
//  ff_l2d_l2t_decc_c6_scanin[116]
//  ff_l2d_l2t_decc_c6_scanin[39]
//  ff_l2d_l2t_decc_c6_scanin[117]
//  ff_l2d_l2t_decc_c6_scanin[40]
//  ff_l2d_l2t_decc_c6_scanin[118]
//  ff_l2d_l2t_decc_c6_scanin[41]
//  ff_l2d_l2t_decc_c6_scanin[119]
//  ff_l2d_l2t_decc_c6_scanin[42]
//  ff_l2d_l2t_decc_c6_scanin[120]
//  ff_l2d_l2t_decc_c6_scanin[43]
//  ff_l2d_l2t_decc_c6_scanin[121]
//  ff_l2d_l2t_decc_c6_scanin[44]
//  ff_l2d_l2t_decc_c6_scanin[122]
//  ff_l2d_l2t_decc_c6_scanin[45]
//  ff_l2d_l2t_decc_c6_scanin[123]
//  ff_l2d_l2t_decc_c6_scanin[46]
//  ff_l2d_l2t_decc_c6_scanin[124]
//  ff_l2d_l2t_decc_c6_scanin[47]
//  ff_l2d_l2t_decc_c6_scanin[125]
//  ff_l2d_l2t_decc_c6_scanin[48]
//  ff_l2d_l2t_decc_c6_scanin[126]
//  ff_l2d_l2t_decc_c6_scanin[49]
//  ff_l2d_l2t_decc_c6_scanin[127]
//  ff_l2d_l2t_decc_c6_scanin[50]
//  ff_l2d_l2t_decc_c6_scanin[128]
//  ff_l2d_l2t_decc_c6_scanin[51]
//  ff_l2d_l2t_decc_c6_scanin[129]
//  ff_l2d_l2t_decc_c6_scanin[52]
//  ff_l2d_l2t_decc_c6_scanin[130]
//  ff_l2d_l2t_decc_c6_scanin[53]
//  ff_l2d_l2t_decc_c6_scanin[131]
//  ff_l2d_l2t_decc_c6_scanin[54]
//  ff_l2d_l2t_decc_c6_scanin[132]
//  ff_l2d_l2t_decc_c6_scanin[55]
//  ff_l2d_l2t_decc_c6_scanin[133]
//  ff_l2d_l2t_decc_c6_scanin[56]
//  ff_l2d_l2t_decc_c6_scanin[134]
//  ff_l2d_l2t_decc_c6_scanin[57]
//  ff_l2d_l2t_decc_c6_scanin[135]
//  ff_l2d_l2t_decc_c6_scanin[58]
//  ff_l2d_l2t_decc_c6_scanin[136]
//  ff_l2d_l2t_decc_c6_scanin[59]
//  ff_l2d_l2t_decc_c6_scanin[137]
//  ff_l2d_l2t_decc_c6_scanin[60]
//  ff_l2d_l2t_decc_c6_scanin[138]
//  ff_l2d_l2t_decc_c6_scanin[61]
//  ff_l2d_l2t_decc_c6_scanin[139]
//  ff_l2d_l2t_decc_c6_scanin[62]
//  ff_l2d_l2t_decc_c6_scanin[140]
//  ff_l2d_l2t_decc_c6_scanin[63]
//  ff_l2d_l2t_decc_c6_scanin[141]
//  ff_l2d_l2t_decc_c6_scanin[64]
//  ff_l2d_l2t_decc_c6_scanin[142]
//  ff_l2d_l2t_decc_c6_scanin[65]
//  ff_l2d_l2t_decc_c6_scanin[143]
//  ff_l2d_l2t_decc_c6_scanin[66]
//  ff_l2d_l2t_decc_c6_scanin[144]
//  ff_l2d_l2t_decc_c6_scanin[67]
//  ff_l2d_l2t_decc_c6_scanin[145]
//  ff_l2d_l2t_decc_c6_scanin[68]
//  ff_l2d_l2t_decc_c6_scanin[146]
//  ff_l2d_l2t_decc_c6_scanin[69]
//  ff_l2d_l2t_decc_c6_scanin[147]
//  ff_l2d_l2t_decc_c6_scanin[70]
//  ff_l2d_l2t_decc_c6_scanin[148]
//  ff_l2d_l2t_decc_c6_scanin[71]
//  ff_l2d_l2t_decc_c6_scanin[149]
//  ff_l2d_l2t_decc_c6_scanin[72]
//  ff_l2d_l2t_decc_c6_scanin[150]
//  ff_l2d_l2t_decc_c6_scanin[73]
//  ff_l2d_l2t_decc_c6_scanin[151]
//  ff_l2d_l2t_decc_c6_scanin[74]
//  ff_l2d_l2t_decc_c6_scanin[152]
//  ff_l2d_l2t_decc_c6_scanin[75]
//  ff_l2d_l2t_decc_c6_scanin[153]
//  ff_l2d_l2t_decc_c6_scanin[76]
//  ff_l2d_l2t_decc_c6_scanin[154]
//  ff_l2d_l2t_decc_c6_scanin[77]
//  ff_l2d_l2t_decc_c6_scanin[155]
//  ff_l2d_l2b_efc_fuse_data_scanin[0:9]
//  ff_l2b_l2d_fuse_reset_d_scanin
//  ff_l2b_l2d_fuse_wren_d_scanin
//  ff_l2b_l2d_fuse_rid_d_scanin[0:6]	
//  ff_l2b_l2d_fuse_l2d_data_in_scanin[0:9]
//  ff_fill_clk_en_ov_stg_scanin
//  ff_pwrsav_ov_stg_scanin
//  scanorder end
// fixscan start
assign ff_l2t_l2d_rd_wr_c3_scanin=scan_in;
assign ff_l2t_l2d_way_sel_c3_scanin[0]=ff_l2t_l2d_rd_wr_c3_scanout;
assign ff_l2t_l2d_way_sel_c3_scanin[1]=ff_l2t_l2d_way_sel_c3_scanout[0];
assign ff_l2t_l2d_way_sel_c3_scanin[2]=ff_l2t_l2d_way_sel_c3_scanout[1];
assign ff_l2t_l2d_way_sel_c3_scanin[3]=ff_l2t_l2d_way_sel_c3_scanout[2];
assign ff_l2t_l2d_way_sel_c3_scanin[4]=ff_l2t_l2d_way_sel_c3_scanout[3];
assign ff_l2t_l2d_way_sel_c3_scanin[5]=ff_l2t_l2d_way_sel_c3_scanout[4];
assign ff_l2t_l2d_way_sel_c3_scanin[6]=ff_l2t_l2d_way_sel_c3_scanout[5];
assign ff_l2t_l2d_way_sel_c3_scanin[7]=ff_l2t_l2d_way_sel_c3_scanout[6];
assign ff_l2t_l2d_way_sel_c3_scanin[8]=ff_l2t_l2d_way_sel_c3_scanout[7];
assign ff_l2t_l2d_way_sel_c3_scanin[9]=ff_l2t_l2d_way_sel_c3_scanout[8];
assign ff_l2t_l2d_way_sel_c3_scanin[10]=ff_l2t_l2d_way_sel_c3_scanout[9];
assign ff_l2t_l2d_way_sel_c3_scanin[11]=ff_l2t_l2d_way_sel_c3_scanout[10];
assign ff_l2t_l2d_way_sel_c3_scanin[12]=ff_l2t_l2d_way_sel_c3_scanout[11];
assign ff_l2t_l2d_way_sel_c3_scanin[13]=ff_l2t_l2d_way_sel_c3_scanout[12];
assign ff_l2t_l2d_way_sel_c3_scanin[14]=ff_l2t_l2d_way_sel_c3_scanout[13];
assign ff_l2t_l2d_way_sel_c3_scanin[15]=ff_l2t_l2d_way_sel_c3_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[0]=ff_l2t_l2d_way_sel_c3_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[0]=ff_l2b_l2d_fbdecc_c5_1_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[0]=ff_l2b_l2d_fbdecc_c5_5_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[0]=ff_l2b_l2d_fbdecc_c5_3_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[0]=ff_l2b_l2d_fbdecc_c5_7_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[0]=ff_l2b_l2d_fbdecc_c5_9_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[0]=ff_l2b_l2d_fbdecc_c5_13_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[0]=ff_l2b_l2d_fbdecc_c5_11_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[1]=ff_l2b_l2d_fbdecc_c5_15_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[1]=ff_l2b_l2d_fbdecc_c5_1_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[1]=ff_l2b_l2d_fbdecc_c5_5_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[1]=ff_l2b_l2d_fbdecc_c5_3_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[1]=ff_l2b_l2d_fbdecc_c5_7_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[1]=ff_l2b_l2d_fbdecc_c5_9_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[1]=ff_l2b_l2d_fbdecc_c5_13_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[1]=ff_l2b_l2d_fbdecc_c5_11_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[2]=ff_l2b_l2d_fbdecc_c5_15_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[2]=ff_l2b_l2d_fbdecc_c5_1_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[2]=ff_l2b_l2d_fbdecc_c5_5_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[2]=ff_l2b_l2d_fbdecc_c5_3_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[2]=ff_l2b_l2d_fbdecc_c5_7_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[2]=ff_l2b_l2d_fbdecc_c5_9_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[2]=ff_l2b_l2d_fbdecc_c5_13_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[2]=ff_l2b_l2d_fbdecc_c5_11_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[3]=ff_l2b_l2d_fbdecc_c5_15_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[3]=ff_l2b_l2d_fbdecc_c5_1_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[3]=ff_l2b_l2d_fbdecc_c5_5_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[3]=ff_l2b_l2d_fbdecc_c5_3_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[3]=ff_l2b_l2d_fbdecc_c5_7_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[3]=ff_l2b_l2d_fbdecc_c5_9_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[3]=ff_l2b_l2d_fbdecc_c5_13_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[3]=ff_l2b_l2d_fbdecc_c5_11_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[4]=ff_l2b_l2d_fbdecc_c5_15_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[4]=ff_l2b_l2d_fbdecc_c5_1_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[4]=ff_l2b_l2d_fbdecc_c5_5_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[4]=ff_l2b_l2d_fbdecc_c5_3_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[4]=ff_l2b_l2d_fbdecc_c5_7_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[4]=ff_l2b_l2d_fbdecc_c5_9_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[4]=ff_l2b_l2d_fbdecc_c5_13_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[4]=ff_l2b_l2d_fbdecc_c5_11_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[5]=ff_l2b_l2d_fbdecc_c5_15_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[5]=ff_l2b_l2d_fbdecc_c5_1_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[5]=ff_l2b_l2d_fbdecc_c5_5_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[5]=ff_l2b_l2d_fbdecc_c5_3_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[5]=ff_l2b_l2d_fbdecc_c5_7_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[5]=ff_l2b_l2d_fbdecc_c5_9_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[5]=ff_l2b_l2d_fbdecc_c5_13_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[5]=ff_l2b_l2d_fbdecc_c5_11_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[6]=ff_l2b_l2d_fbdecc_c5_15_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[6]=ff_l2b_l2d_fbdecc_c5_1_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[6]=ff_l2b_l2d_fbdecc_c5_5_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[6]=ff_l2b_l2d_fbdecc_c5_3_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[6]=ff_l2b_l2d_fbdecc_c5_7_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[6]=ff_l2b_l2d_fbdecc_c5_9_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[6]=ff_l2b_l2d_fbdecc_c5_13_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[6]=ff_l2b_l2d_fbdecc_c5_11_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[7]=ff_l2b_l2d_fbdecc_c5_15_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[7]=ff_l2b_l2d_fbdecc_c5_1_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[7]=ff_l2b_l2d_fbdecc_c5_5_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[7]=ff_l2b_l2d_fbdecc_c5_3_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[7]=ff_l2b_l2d_fbdecc_c5_7_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[7]=ff_l2b_l2d_fbdecc_c5_9_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[7]=ff_l2b_l2d_fbdecc_c5_13_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[7]=ff_l2b_l2d_fbdecc_c5_11_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[8]=ff_l2b_l2d_fbdecc_c5_15_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[8]=ff_l2b_l2d_fbdecc_c5_1_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[8]=ff_l2b_l2d_fbdecc_c5_5_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[8]=ff_l2b_l2d_fbdecc_c5_3_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[8]=ff_l2b_l2d_fbdecc_c5_7_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[8]=ff_l2b_l2d_fbdecc_c5_9_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[8]=ff_l2b_l2d_fbdecc_c5_13_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[8]=ff_l2b_l2d_fbdecc_c5_11_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[9]=ff_l2b_l2d_fbdecc_c5_15_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[9]=ff_l2b_l2d_fbdecc_c5_1_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[9]=ff_l2b_l2d_fbdecc_c5_5_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[9]=ff_l2b_l2d_fbdecc_c5_3_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[9]=ff_l2b_l2d_fbdecc_c5_7_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[9]=ff_l2b_l2d_fbdecc_c5_9_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[9]=ff_l2b_l2d_fbdecc_c5_13_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[9]=ff_l2b_l2d_fbdecc_c5_11_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[10]=ff_l2b_l2d_fbdecc_c5_15_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[10]=ff_l2b_l2d_fbdecc_c5_1_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[10]=ff_l2b_l2d_fbdecc_c5_5_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[10]=ff_l2b_l2d_fbdecc_c5_3_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[10]=ff_l2b_l2d_fbdecc_c5_7_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[10]=ff_l2b_l2d_fbdecc_c5_9_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[10]=ff_l2b_l2d_fbdecc_c5_13_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[10]=ff_l2b_l2d_fbdecc_c5_11_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[11]=ff_l2b_l2d_fbdecc_c5_15_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[11]=ff_l2b_l2d_fbdecc_c5_1_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[11]=ff_l2b_l2d_fbdecc_c5_5_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[11]=ff_l2b_l2d_fbdecc_c5_3_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[11]=ff_l2b_l2d_fbdecc_c5_7_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[11]=ff_l2b_l2d_fbdecc_c5_9_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[11]=ff_l2b_l2d_fbdecc_c5_13_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[11]=ff_l2b_l2d_fbdecc_c5_11_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[12]=ff_l2b_l2d_fbdecc_c5_15_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[12]=ff_l2b_l2d_fbdecc_c5_1_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[12]=ff_l2b_l2d_fbdecc_c5_5_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[12]=ff_l2b_l2d_fbdecc_c5_3_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[12]=ff_l2b_l2d_fbdecc_c5_7_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[12]=ff_l2b_l2d_fbdecc_c5_9_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[12]=ff_l2b_l2d_fbdecc_c5_13_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[12]=ff_l2b_l2d_fbdecc_c5_11_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[13]=ff_l2b_l2d_fbdecc_c5_15_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[13]=ff_l2b_l2d_fbdecc_c5_1_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[13]=ff_l2b_l2d_fbdecc_c5_5_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[13]=ff_l2b_l2d_fbdecc_c5_3_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[13]=ff_l2b_l2d_fbdecc_c5_7_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[13]=ff_l2b_l2d_fbdecc_c5_9_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[13]=ff_l2b_l2d_fbdecc_c5_13_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[13]=ff_l2b_l2d_fbdecc_c5_11_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[14]=ff_l2b_l2d_fbdecc_c5_15_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[14]=ff_l2b_l2d_fbdecc_c5_1_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[14]=ff_l2b_l2d_fbdecc_c5_5_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[14]=ff_l2b_l2d_fbdecc_c5_3_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[14]=ff_l2b_l2d_fbdecc_c5_7_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[14]=ff_l2b_l2d_fbdecc_c5_9_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[14]=ff_l2b_l2d_fbdecc_c5_13_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[14]=ff_l2b_l2d_fbdecc_c5_11_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[15]=ff_l2b_l2d_fbdecc_c5_15_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[15]=ff_l2b_l2d_fbdecc_c5_1_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[15]=ff_l2b_l2d_fbdecc_c5_5_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[15]=ff_l2b_l2d_fbdecc_c5_3_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[15]=ff_l2b_l2d_fbdecc_c5_7_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[15]=ff_l2b_l2d_fbdecc_c5_9_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[15]=ff_l2b_l2d_fbdecc_c5_13_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[15]=ff_l2b_l2d_fbdecc_c5_11_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[16]=ff_l2b_l2d_fbdecc_c5_15_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[16]=ff_l2b_l2d_fbdecc_c5_1_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[16]=ff_l2b_l2d_fbdecc_c5_5_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[16]=ff_l2b_l2d_fbdecc_c5_3_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[16]=ff_l2b_l2d_fbdecc_c5_7_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[16]=ff_l2b_l2d_fbdecc_c5_9_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[16]=ff_l2b_l2d_fbdecc_c5_13_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[16]=ff_l2b_l2d_fbdecc_c5_11_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[17]=ff_l2b_l2d_fbdecc_c5_15_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[17]=ff_l2b_l2d_fbdecc_c5_1_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[17]=ff_l2b_l2d_fbdecc_c5_5_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[17]=ff_l2b_l2d_fbdecc_c5_3_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[17]=ff_l2b_l2d_fbdecc_c5_7_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[17]=ff_l2b_l2d_fbdecc_c5_9_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[17]=ff_l2b_l2d_fbdecc_c5_13_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[17]=ff_l2b_l2d_fbdecc_c5_11_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[18]=ff_l2b_l2d_fbdecc_c5_15_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[18]=ff_l2b_l2d_fbdecc_c5_1_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[18]=ff_l2b_l2d_fbdecc_c5_5_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[18]=ff_l2b_l2d_fbdecc_c5_3_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[18]=ff_l2b_l2d_fbdecc_c5_7_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[18]=ff_l2b_l2d_fbdecc_c5_9_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[18]=ff_l2b_l2d_fbdecc_c5_13_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[18]=ff_l2b_l2d_fbdecc_c5_11_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[19]=ff_l2b_l2d_fbdecc_c5_15_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[19]=ff_l2b_l2d_fbdecc_c5_1_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[19]=ff_l2b_l2d_fbdecc_c5_5_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[19]=ff_l2b_l2d_fbdecc_c5_3_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[19]=ff_l2b_l2d_fbdecc_c5_7_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[19]=ff_l2b_l2d_fbdecc_c5_9_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[19]=ff_l2b_l2d_fbdecc_c5_13_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[19]=ff_l2b_l2d_fbdecc_c5_11_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[20]=ff_l2b_l2d_fbdecc_c5_15_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[20]=ff_l2b_l2d_fbdecc_c5_1_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[20]=ff_l2b_l2d_fbdecc_c5_5_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[20]=ff_l2b_l2d_fbdecc_c5_3_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[20]=ff_l2b_l2d_fbdecc_c5_7_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[20]=ff_l2b_l2d_fbdecc_c5_9_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[20]=ff_l2b_l2d_fbdecc_c5_13_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[20]=ff_l2b_l2d_fbdecc_c5_11_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[21]=ff_l2b_l2d_fbdecc_c5_15_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[21]=ff_l2b_l2d_fbdecc_c5_1_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[21]=ff_l2b_l2d_fbdecc_c5_5_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[21]=ff_l2b_l2d_fbdecc_c5_3_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[21]=ff_l2b_l2d_fbdecc_c5_7_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[21]=ff_l2b_l2d_fbdecc_c5_9_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[21]=ff_l2b_l2d_fbdecc_c5_13_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[21]=ff_l2b_l2d_fbdecc_c5_11_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[22]=ff_l2b_l2d_fbdecc_c5_15_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[22]=ff_l2b_l2d_fbdecc_c5_1_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[22]=ff_l2b_l2d_fbdecc_c5_5_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[22]=ff_l2b_l2d_fbdecc_c5_3_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[22]=ff_l2b_l2d_fbdecc_c5_7_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[22]=ff_l2b_l2d_fbdecc_c5_9_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[22]=ff_l2b_l2d_fbdecc_c5_13_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[22]=ff_l2b_l2d_fbdecc_c5_11_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[23]=ff_l2b_l2d_fbdecc_c5_15_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[23]=ff_l2b_l2d_fbdecc_c5_1_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[23]=ff_l2b_l2d_fbdecc_c5_5_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[23]=ff_l2b_l2d_fbdecc_c5_3_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[23]=ff_l2b_l2d_fbdecc_c5_7_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[23]=ff_l2b_l2d_fbdecc_c5_9_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[23]=ff_l2b_l2d_fbdecc_c5_13_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[23]=ff_l2b_l2d_fbdecc_c5_11_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[24]=ff_l2b_l2d_fbdecc_c5_15_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[24]=ff_l2b_l2d_fbdecc_c5_1_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[24]=ff_l2b_l2d_fbdecc_c5_5_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[24]=ff_l2b_l2d_fbdecc_c5_3_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[24]=ff_l2b_l2d_fbdecc_c5_7_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[24]=ff_l2b_l2d_fbdecc_c5_9_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[24]=ff_l2b_l2d_fbdecc_c5_13_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[24]=ff_l2b_l2d_fbdecc_c5_11_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[25]=ff_l2b_l2d_fbdecc_c5_15_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[25]=ff_l2b_l2d_fbdecc_c5_1_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[25]=ff_l2b_l2d_fbdecc_c5_5_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[25]=ff_l2b_l2d_fbdecc_c5_3_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[25]=ff_l2b_l2d_fbdecc_c5_7_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[25]=ff_l2b_l2d_fbdecc_c5_9_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[25]=ff_l2b_l2d_fbdecc_c5_13_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[25]=ff_l2b_l2d_fbdecc_c5_11_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[26]=ff_l2b_l2d_fbdecc_c5_15_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[26]=ff_l2b_l2d_fbdecc_c5_1_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[26]=ff_l2b_l2d_fbdecc_c5_5_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[26]=ff_l2b_l2d_fbdecc_c5_3_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[26]=ff_l2b_l2d_fbdecc_c5_7_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[26]=ff_l2b_l2d_fbdecc_c5_9_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[26]=ff_l2b_l2d_fbdecc_c5_13_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[26]=ff_l2b_l2d_fbdecc_c5_11_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[27]=ff_l2b_l2d_fbdecc_c5_15_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[27]=ff_l2b_l2d_fbdecc_c5_1_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[27]=ff_l2b_l2d_fbdecc_c5_5_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[27]=ff_l2b_l2d_fbdecc_c5_3_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[27]=ff_l2b_l2d_fbdecc_c5_7_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[27]=ff_l2b_l2d_fbdecc_c5_9_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[27]=ff_l2b_l2d_fbdecc_c5_13_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[27]=ff_l2b_l2d_fbdecc_c5_11_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[28]=ff_l2b_l2d_fbdecc_c5_15_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[28]=ff_l2b_l2d_fbdecc_c5_1_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[28]=ff_l2b_l2d_fbdecc_c5_5_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[28]=ff_l2b_l2d_fbdecc_c5_3_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[28]=ff_l2b_l2d_fbdecc_c5_7_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[28]=ff_l2b_l2d_fbdecc_c5_9_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[28]=ff_l2b_l2d_fbdecc_c5_13_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[28]=ff_l2b_l2d_fbdecc_c5_11_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[29]=ff_l2b_l2d_fbdecc_c5_15_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[29]=ff_l2b_l2d_fbdecc_c5_1_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[29]=ff_l2b_l2d_fbdecc_c5_5_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[29]=ff_l2b_l2d_fbdecc_c5_3_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[29]=ff_l2b_l2d_fbdecc_c5_7_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[29]=ff_l2b_l2d_fbdecc_c5_9_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[29]=ff_l2b_l2d_fbdecc_c5_13_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[29]=ff_l2b_l2d_fbdecc_c5_11_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[30]=ff_l2b_l2d_fbdecc_c5_15_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[30]=ff_l2b_l2d_fbdecc_c5_1_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[30]=ff_l2b_l2d_fbdecc_c5_5_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[30]=ff_l2b_l2d_fbdecc_c5_3_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[30]=ff_l2b_l2d_fbdecc_c5_7_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[30]=ff_l2b_l2d_fbdecc_c5_9_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[30]=ff_l2b_l2d_fbdecc_c5_13_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[30]=ff_l2b_l2d_fbdecc_c5_11_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[31]=ff_l2b_l2d_fbdecc_c5_15_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[31]=ff_l2b_l2d_fbdecc_c5_1_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[31]=ff_l2b_l2d_fbdecc_c5_5_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[31]=ff_l2b_l2d_fbdecc_c5_3_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[31]=ff_l2b_l2d_fbdecc_c5_7_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[31]=ff_l2b_l2d_fbdecc_c5_9_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[31]=ff_l2b_l2d_fbdecc_c5_13_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[31]=ff_l2b_l2d_fbdecc_c5_11_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[32]=ff_l2b_l2d_fbdecc_c5_15_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[32]=ff_l2b_l2d_fbdecc_c5_1_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[32]=ff_l2b_l2d_fbdecc_c5_5_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[32]=ff_l2b_l2d_fbdecc_c5_3_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[32]=ff_l2b_l2d_fbdecc_c5_7_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[32]=ff_l2b_l2d_fbdecc_c5_9_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[32]=ff_l2b_l2d_fbdecc_c5_13_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[32]=ff_l2b_l2d_fbdecc_c5_11_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[33]=ff_l2b_l2d_fbdecc_c5_15_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[33]=ff_l2b_l2d_fbdecc_c5_1_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[33]=ff_l2b_l2d_fbdecc_c5_5_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[33]=ff_l2b_l2d_fbdecc_c5_3_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[33]=ff_l2b_l2d_fbdecc_c5_7_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[33]=ff_l2b_l2d_fbdecc_c5_9_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[33]=ff_l2b_l2d_fbdecc_c5_13_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[33]=ff_l2b_l2d_fbdecc_c5_11_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[34]=ff_l2b_l2d_fbdecc_c5_15_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[34]=ff_l2b_l2d_fbdecc_c5_1_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[34]=ff_l2b_l2d_fbdecc_c5_5_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[34]=ff_l2b_l2d_fbdecc_c5_3_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[34]=ff_l2b_l2d_fbdecc_c5_7_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[34]=ff_l2b_l2d_fbdecc_c5_9_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[34]=ff_l2b_l2d_fbdecc_c5_13_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[34]=ff_l2b_l2d_fbdecc_c5_11_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[35]=ff_l2b_l2d_fbdecc_c5_15_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[35]=ff_l2b_l2d_fbdecc_c5_1_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[35]=ff_l2b_l2d_fbdecc_c5_5_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[35]=ff_l2b_l2d_fbdecc_c5_3_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[35]=ff_l2b_l2d_fbdecc_c5_7_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[35]=ff_l2b_l2d_fbdecc_c5_9_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[35]=ff_l2b_l2d_fbdecc_c5_13_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[35]=ff_l2b_l2d_fbdecc_c5_11_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[36]=ff_l2b_l2d_fbdecc_c5_15_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[36]=ff_l2b_l2d_fbdecc_c5_1_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[36]=ff_l2b_l2d_fbdecc_c5_5_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[36]=ff_l2b_l2d_fbdecc_c5_3_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[36]=ff_l2b_l2d_fbdecc_c5_7_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[36]=ff_l2b_l2d_fbdecc_c5_9_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[36]=ff_l2b_l2d_fbdecc_c5_13_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[36]=ff_l2b_l2d_fbdecc_c5_11_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[37]=ff_l2b_l2d_fbdecc_c5_15_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[37]=ff_l2b_l2d_fbdecc_c5_1_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[37]=ff_l2b_l2d_fbdecc_c5_5_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[37]=ff_l2b_l2d_fbdecc_c5_3_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[37]=ff_l2b_l2d_fbdecc_c5_7_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[37]=ff_l2b_l2d_fbdecc_c5_9_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[37]=ff_l2b_l2d_fbdecc_c5_13_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[37]=ff_l2b_l2d_fbdecc_c5_11_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_1_scanin[38]=ff_l2b_l2d_fbdecc_c5_15_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_5_scanin[38]=ff_l2b_l2d_fbdecc_c5_1_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_3_scanin[38]=ff_l2b_l2d_fbdecc_c5_5_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_7_scanin[38]=ff_l2b_l2d_fbdecc_c5_3_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_9_scanin[38]=ff_l2b_l2d_fbdecc_c5_7_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_13_scanin[38]=ff_l2b_l2d_fbdecc_c5_9_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_11_scanin[38]=ff_l2b_l2d_fbdecc_c5_13_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_15_scanin[38]=ff_l2b_l2d_fbdecc_c5_11_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[0]=ff_l2b_l2d_fbdecc_c5_15_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[0]=ff_l2b_l2d_fbdecc_c5_2_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[0]=ff_l2b_l2d_fbdecc_c5_6_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[0]=ff_l2b_l2d_fbdecc_c5_4_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[0]=ff_l2b_l2d_fbdecc_c5_8_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[0]=ff_l2b_l2d_fbdecc_c5_10_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[0]=ff_l2b_l2d_fbdecc_c5_14_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[0]=ff_l2b_l2d_fbdecc_c5_12_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[1]=ff_l2b_l2d_fbdecc_c5_16_scanout[0];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[1]=ff_l2b_l2d_fbdecc_c5_2_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[1]=ff_l2b_l2d_fbdecc_c5_6_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[1]=ff_l2b_l2d_fbdecc_c5_4_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[1]=ff_l2b_l2d_fbdecc_c5_8_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[1]=ff_l2b_l2d_fbdecc_c5_10_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[1]=ff_l2b_l2d_fbdecc_c5_14_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[1]=ff_l2b_l2d_fbdecc_c5_12_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[2]=ff_l2b_l2d_fbdecc_c5_16_scanout[1];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[2]=ff_l2b_l2d_fbdecc_c5_2_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[2]=ff_l2b_l2d_fbdecc_c5_6_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[2]=ff_l2b_l2d_fbdecc_c5_4_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[2]=ff_l2b_l2d_fbdecc_c5_8_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[2]=ff_l2b_l2d_fbdecc_c5_10_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[2]=ff_l2b_l2d_fbdecc_c5_14_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[2]=ff_l2b_l2d_fbdecc_c5_12_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[3]=ff_l2b_l2d_fbdecc_c5_16_scanout[2];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[3]=ff_l2b_l2d_fbdecc_c5_2_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[3]=ff_l2b_l2d_fbdecc_c5_6_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[3]=ff_l2b_l2d_fbdecc_c5_4_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[3]=ff_l2b_l2d_fbdecc_c5_8_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[3]=ff_l2b_l2d_fbdecc_c5_10_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[3]=ff_l2b_l2d_fbdecc_c5_14_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[3]=ff_l2b_l2d_fbdecc_c5_12_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[4]=ff_l2b_l2d_fbdecc_c5_16_scanout[3];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[4]=ff_l2b_l2d_fbdecc_c5_2_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[4]=ff_l2b_l2d_fbdecc_c5_6_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[4]=ff_l2b_l2d_fbdecc_c5_4_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[4]=ff_l2b_l2d_fbdecc_c5_8_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[4]=ff_l2b_l2d_fbdecc_c5_10_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[4]=ff_l2b_l2d_fbdecc_c5_14_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[4]=ff_l2b_l2d_fbdecc_c5_12_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[5]=ff_l2b_l2d_fbdecc_c5_16_scanout[4];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[5]=ff_l2b_l2d_fbdecc_c5_2_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[5]=ff_l2b_l2d_fbdecc_c5_6_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[5]=ff_l2b_l2d_fbdecc_c5_4_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[5]=ff_l2b_l2d_fbdecc_c5_8_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[5]=ff_l2b_l2d_fbdecc_c5_10_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[5]=ff_l2b_l2d_fbdecc_c5_14_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[5]=ff_l2b_l2d_fbdecc_c5_12_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[6]=ff_l2b_l2d_fbdecc_c5_16_scanout[5];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[6]=ff_l2b_l2d_fbdecc_c5_2_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[6]=ff_l2b_l2d_fbdecc_c5_6_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[6]=ff_l2b_l2d_fbdecc_c5_4_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[6]=ff_l2b_l2d_fbdecc_c5_8_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[6]=ff_l2b_l2d_fbdecc_c5_10_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[6]=ff_l2b_l2d_fbdecc_c5_14_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[6]=ff_l2b_l2d_fbdecc_c5_12_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[7]=ff_l2b_l2d_fbdecc_c5_16_scanout[6];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[7]=ff_l2b_l2d_fbdecc_c5_2_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[7]=ff_l2b_l2d_fbdecc_c5_6_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[7]=ff_l2b_l2d_fbdecc_c5_4_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[7]=ff_l2b_l2d_fbdecc_c5_8_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[7]=ff_l2b_l2d_fbdecc_c5_10_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[7]=ff_l2b_l2d_fbdecc_c5_14_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[7]=ff_l2b_l2d_fbdecc_c5_12_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[8]=ff_l2b_l2d_fbdecc_c5_16_scanout[7];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[8]=ff_l2b_l2d_fbdecc_c5_2_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[8]=ff_l2b_l2d_fbdecc_c5_6_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[8]=ff_l2b_l2d_fbdecc_c5_4_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[8]=ff_l2b_l2d_fbdecc_c5_8_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[8]=ff_l2b_l2d_fbdecc_c5_10_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[8]=ff_l2b_l2d_fbdecc_c5_14_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[8]=ff_l2b_l2d_fbdecc_c5_12_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[9]=ff_l2b_l2d_fbdecc_c5_16_scanout[8];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[9]=ff_l2b_l2d_fbdecc_c5_2_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[9]=ff_l2b_l2d_fbdecc_c5_6_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[9]=ff_l2b_l2d_fbdecc_c5_4_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[9]=ff_l2b_l2d_fbdecc_c5_8_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[9]=ff_l2b_l2d_fbdecc_c5_10_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[9]=ff_l2b_l2d_fbdecc_c5_14_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[9]=ff_l2b_l2d_fbdecc_c5_12_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[10]=ff_l2b_l2d_fbdecc_c5_16_scanout[9];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[10]=ff_l2b_l2d_fbdecc_c5_2_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[10]=ff_l2b_l2d_fbdecc_c5_6_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[10]=ff_l2b_l2d_fbdecc_c5_4_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[10]=ff_l2b_l2d_fbdecc_c5_8_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[10]=ff_l2b_l2d_fbdecc_c5_10_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[10]=ff_l2b_l2d_fbdecc_c5_14_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[10]=ff_l2b_l2d_fbdecc_c5_12_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[11]=ff_l2b_l2d_fbdecc_c5_16_scanout[10];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[11]=ff_l2b_l2d_fbdecc_c5_2_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[11]=ff_l2b_l2d_fbdecc_c5_6_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[11]=ff_l2b_l2d_fbdecc_c5_4_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[11]=ff_l2b_l2d_fbdecc_c5_8_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[11]=ff_l2b_l2d_fbdecc_c5_10_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[11]=ff_l2b_l2d_fbdecc_c5_14_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[11]=ff_l2b_l2d_fbdecc_c5_12_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[12]=ff_l2b_l2d_fbdecc_c5_16_scanout[11];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[12]=ff_l2b_l2d_fbdecc_c5_2_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[12]=ff_l2b_l2d_fbdecc_c5_6_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[12]=ff_l2b_l2d_fbdecc_c5_4_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[12]=ff_l2b_l2d_fbdecc_c5_8_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[12]=ff_l2b_l2d_fbdecc_c5_10_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[12]=ff_l2b_l2d_fbdecc_c5_14_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[12]=ff_l2b_l2d_fbdecc_c5_12_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[13]=ff_l2b_l2d_fbdecc_c5_16_scanout[12];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[13]=ff_l2b_l2d_fbdecc_c5_2_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[13]=ff_l2b_l2d_fbdecc_c5_6_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[13]=ff_l2b_l2d_fbdecc_c5_4_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[13]=ff_l2b_l2d_fbdecc_c5_8_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[13]=ff_l2b_l2d_fbdecc_c5_10_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[13]=ff_l2b_l2d_fbdecc_c5_14_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[13]=ff_l2b_l2d_fbdecc_c5_12_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[14]=ff_l2b_l2d_fbdecc_c5_16_scanout[13];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[14]=ff_l2b_l2d_fbdecc_c5_2_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[14]=ff_l2b_l2d_fbdecc_c5_6_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[14]=ff_l2b_l2d_fbdecc_c5_4_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[14]=ff_l2b_l2d_fbdecc_c5_8_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[14]=ff_l2b_l2d_fbdecc_c5_10_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[14]=ff_l2b_l2d_fbdecc_c5_14_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[14]=ff_l2b_l2d_fbdecc_c5_12_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[15]=ff_l2b_l2d_fbdecc_c5_16_scanout[14];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[15]=ff_l2b_l2d_fbdecc_c5_2_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[15]=ff_l2b_l2d_fbdecc_c5_6_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[15]=ff_l2b_l2d_fbdecc_c5_4_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[15]=ff_l2b_l2d_fbdecc_c5_8_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[15]=ff_l2b_l2d_fbdecc_c5_10_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[15]=ff_l2b_l2d_fbdecc_c5_14_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[15]=ff_l2b_l2d_fbdecc_c5_12_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[16]=ff_l2b_l2d_fbdecc_c5_16_scanout[15];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[16]=ff_l2b_l2d_fbdecc_c5_2_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[16]=ff_l2b_l2d_fbdecc_c5_6_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[16]=ff_l2b_l2d_fbdecc_c5_4_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[16]=ff_l2b_l2d_fbdecc_c5_8_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[16]=ff_l2b_l2d_fbdecc_c5_10_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[16]=ff_l2b_l2d_fbdecc_c5_14_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[16]=ff_l2b_l2d_fbdecc_c5_12_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[17]=ff_l2b_l2d_fbdecc_c5_16_scanout[16];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[17]=ff_l2b_l2d_fbdecc_c5_2_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[17]=ff_l2b_l2d_fbdecc_c5_6_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[17]=ff_l2b_l2d_fbdecc_c5_4_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[17]=ff_l2b_l2d_fbdecc_c5_8_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[17]=ff_l2b_l2d_fbdecc_c5_10_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[17]=ff_l2b_l2d_fbdecc_c5_14_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[17]=ff_l2b_l2d_fbdecc_c5_12_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[18]=ff_l2b_l2d_fbdecc_c5_16_scanout[17];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[18]=ff_l2b_l2d_fbdecc_c5_2_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[18]=ff_l2b_l2d_fbdecc_c5_6_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[18]=ff_l2b_l2d_fbdecc_c5_4_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[18]=ff_l2b_l2d_fbdecc_c5_8_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[18]=ff_l2b_l2d_fbdecc_c5_10_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[18]=ff_l2b_l2d_fbdecc_c5_14_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[18]=ff_l2b_l2d_fbdecc_c5_12_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[19]=ff_l2b_l2d_fbdecc_c5_16_scanout[18];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[19]=ff_l2b_l2d_fbdecc_c5_2_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[19]=ff_l2b_l2d_fbdecc_c5_6_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[19]=ff_l2b_l2d_fbdecc_c5_4_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[19]=ff_l2b_l2d_fbdecc_c5_8_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[19]=ff_l2b_l2d_fbdecc_c5_10_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[19]=ff_l2b_l2d_fbdecc_c5_14_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[19]=ff_l2b_l2d_fbdecc_c5_12_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[20]=ff_l2b_l2d_fbdecc_c5_16_scanout[19];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[20]=ff_l2b_l2d_fbdecc_c5_2_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[20]=ff_l2b_l2d_fbdecc_c5_6_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[20]=ff_l2b_l2d_fbdecc_c5_4_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[20]=ff_l2b_l2d_fbdecc_c5_8_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[20]=ff_l2b_l2d_fbdecc_c5_10_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[20]=ff_l2b_l2d_fbdecc_c5_14_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[20]=ff_l2b_l2d_fbdecc_c5_12_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[21]=ff_l2b_l2d_fbdecc_c5_16_scanout[20];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[21]=ff_l2b_l2d_fbdecc_c5_2_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[21]=ff_l2b_l2d_fbdecc_c5_6_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[21]=ff_l2b_l2d_fbdecc_c5_4_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[21]=ff_l2b_l2d_fbdecc_c5_8_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[21]=ff_l2b_l2d_fbdecc_c5_10_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[21]=ff_l2b_l2d_fbdecc_c5_14_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[21]=ff_l2b_l2d_fbdecc_c5_12_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[22]=ff_l2b_l2d_fbdecc_c5_16_scanout[21];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[22]=ff_l2b_l2d_fbdecc_c5_2_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[22]=ff_l2b_l2d_fbdecc_c5_6_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[22]=ff_l2b_l2d_fbdecc_c5_4_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[22]=ff_l2b_l2d_fbdecc_c5_8_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[22]=ff_l2b_l2d_fbdecc_c5_10_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[22]=ff_l2b_l2d_fbdecc_c5_14_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[22]=ff_l2b_l2d_fbdecc_c5_12_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[23]=ff_l2b_l2d_fbdecc_c5_16_scanout[22];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[23]=ff_l2b_l2d_fbdecc_c5_2_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[23]=ff_l2b_l2d_fbdecc_c5_6_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[23]=ff_l2b_l2d_fbdecc_c5_4_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[23]=ff_l2b_l2d_fbdecc_c5_8_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[23]=ff_l2b_l2d_fbdecc_c5_10_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[23]=ff_l2b_l2d_fbdecc_c5_14_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[23]=ff_l2b_l2d_fbdecc_c5_12_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[24]=ff_l2b_l2d_fbdecc_c5_16_scanout[23];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[24]=ff_l2b_l2d_fbdecc_c5_2_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[24]=ff_l2b_l2d_fbdecc_c5_6_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[24]=ff_l2b_l2d_fbdecc_c5_4_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[24]=ff_l2b_l2d_fbdecc_c5_8_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[24]=ff_l2b_l2d_fbdecc_c5_10_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[24]=ff_l2b_l2d_fbdecc_c5_14_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[24]=ff_l2b_l2d_fbdecc_c5_12_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[25]=ff_l2b_l2d_fbdecc_c5_16_scanout[24];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[25]=ff_l2b_l2d_fbdecc_c5_2_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[25]=ff_l2b_l2d_fbdecc_c5_6_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[25]=ff_l2b_l2d_fbdecc_c5_4_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[25]=ff_l2b_l2d_fbdecc_c5_8_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[25]=ff_l2b_l2d_fbdecc_c5_10_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[25]=ff_l2b_l2d_fbdecc_c5_14_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[25]=ff_l2b_l2d_fbdecc_c5_12_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[26]=ff_l2b_l2d_fbdecc_c5_16_scanout[25];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[26]=ff_l2b_l2d_fbdecc_c5_2_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[26]=ff_l2b_l2d_fbdecc_c5_6_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[26]=ff_l2b_l2d_fbdecc_c5_4_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[26]=ff_l2b_l2d_fbdecc_c5_8_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[26]=ff_l2b_l2d_fbdecc_c5_10_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[26]=ff_l2b_l2d_fbdecc_c5_14_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[26]=ff_l2b_l2d_fbdecc_c5_12_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[27]=ff_l2b_l2d_fbdecc_c5_16_scanout[26];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[27]=ff_l2b_l2d_fbdecc_c5_2_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[27]=ff_l2b_l2d_fbdecc_c5_6_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[27]=ff_l2b_l2d_fbdecc_c5_4_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[27]=ff_l2b_l2d_fbdecc_c5_8_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[27]=ff_l2b_l2d_fbdecc_c5_10_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[27]=ff_l2b_l2d_fbdecc_c5_14_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[27]=ff_l2b_l2d_fbdecc_c5_12_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[28]=ff_l2b_l2d_fbdecc_c5_16_scanout[27];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[28]=ff_l2b_l2d_fbdecc_c5_2_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[28]=ff_l2b_l2d_fbdecc_c5_6_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[28]=ff_l2b_l2d_fbdecc_c5_4_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[28]=ff_l2b_l2d_fbdecc_c5_8_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[28]=ff_l2b_l2d_fbdecc_c5_10_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[28]=ff_l2b_l2d_fbdecc_c5_14_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[28]=ff_l2b_l2d_fbdecc_c5_12_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[29]=ff_l2b_l2d_fbdecc_c5_16_scanout[28];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[29]=ff_l2b_l2d_fbdecc_c5_2_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[29]=ff_l2b_l2d_fbdecc_c5_6_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[29]=ff_l2b_l2d_fbdecc_c5_4_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[29]=ff_l2b_l2d_fbdecc_c5_8_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[29]=ff_l2b_l2d_fbdecc_c5_10_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[29]=ff_l2b_l2d_fbdecc_c5_14_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[29]=ff_l2b_l2d_fbdecc_c5_12_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[30]=ff_l2b_l2d_fbdecc_c5_16_scanout[29];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[30]=ff_l2b_l2d_fbdecc_c5_2_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[30]=ff_l2b_l2d_fbdecc_c5_6_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[30]=ff_l2b_l2d_fbdecc_c5_4_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[30]=ff_l2b_l2d_fbdecc_c5_8_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[30]=ff_l2b_l2d_fbdecc_c5_10_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[30]=ff_l2b_l2d_fbdecc_c5_14_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[30]=ff_l2b_l2d_fbdecc_c5_12_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[31]=ff_l2b_l2d_fbdecc_c5_16_scanout[30];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[31]=ff_l2b_l2d_fbdecc_c5_2_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[31]=ff_l2b_l2d_fbdecc_c5_6_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[31]=ff_l2b_l2d_fbdecc_c5_4_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[31]=ff_l2b_l2d_fbdecc_c5_8_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[31]=ff_l2b_l2d_fbdecc_c5_10_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[31]=ff_l2b_l2d_fbdecc_c5_14_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[31]=ff_l2b_l2d_fbdecc_c5_12_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[32]=ff_l2b_l2d_fbdecc_c5_16_scanout[31];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[32]=ff_l2b_l2d_fbdecc_c5_2_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[32]=ff_l2b_l2d_fbdecc_c5_6_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[32]=ff_l2b_l2d_fbdecc_c5_4_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[32]=ff_l2b_l2d_fbdecc_c5_8_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[32]=ff_l2b_l2d_fbdecc_c5_10_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[32]=ff_l2b_l2d_fbdecc_c5_14_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[32]=ff_l2b_l2d_fbdecc_c5_12_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[33]=ff_l2b_l2d_fbdecc_c5_16_scanout[32];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[33]=ff_l2b_l2d_fbdecc_c5_2_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[33]=ff_l2b_l2d_fbdecc_c5_6_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[33]=ff_l2b_l2d_fbdecc_c5_4_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[33]=ff_l2b_l2d_fbdecc_c5_8_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[33]=ff_l2b_l2d_fbdecc_c5_10_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[33]=ff_l2b_l2d_fbdecc_c5_14_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[33]=ff_l2b_l2d_fbdecc_c5_12_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[34]=ff_l2b_l2d_fbdecc_c5_16_scanout[33];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[34]=ff_l2b_l2d_fbdecc_c5_2_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[34]=ff_l2b_l2d_fbdecc_c5_6_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[34]=ff_l2b_l2d_fbdecc_c5_4_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[34]=ff_l2b_l2d_fbdecc_c5_8_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[34]=ff_l2b_l2d_fbdecc_c5_10_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[34]=ff_l2b_l2d_fbdecc_c5_14_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[34]=ff_l2b_l2d_fbdecc_c5_12_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[35]=ff_l2b_l2d_fbdecc_c5_16_scanout[34];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[35]=ff_l2b_l2d_fbdecc_c5_2_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[35]=ff_l2b_l2d_fbdecc_c5_6_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[35]=ff_l2b_l2d_fbdecc_c5_4_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[35]=ff_l2b_l2d_fbdecc_c5_8_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[35]=ff_l2b_l2d_fbdecc_c5_10_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[35]=ff_l2b_l2d_fbdecc_c5_14_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[35]=ff_l2b_l2d_fbdecc_c5_12_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[36]=ff_l2b_l2d_fbdecc_c5_16_scanout[35];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[36]=ff_l2b_l2d_fbdecc_c5_2_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[36]=ff_l2b_l2d_fbdecc_c5_6_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[36]=ff_l2b_l2d_fbdecc_c5_4_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[36]=ff_l2b_l2d_fbdecc_c5_8_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[36]=ff_l2b_l2d_fbdecc_c5_10_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[36]=ff_l2b_l2d_fbdecc_c5_14_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[36]=ff_l2b_l2d_fbdecc_c5_12_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[37]=ff_l2b_l2d_fbdecc_c5_16_scanout[36];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[37]=ff_l2b_l2d_fbdecc_c5_2_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[37]=ff_l2b_l2d_fbdecc_c5_6_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[37]=ff_l2b_l2d_fbdecc_c5_4_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[37]=ff_l2b_l2d_fbdecc_c5_8_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[37]=ff_l2b_l2d_fbdecc_c5_10_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[37]=ff_l2b_l2d_fbdecc_c5_14_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[37]=ff_l2b_l2d_fbdecc_c5_12_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_2_scanin[38]=ff_l2b_l2d_fbdecc_c5_16_scanout[37];
assign ff_l2b_l2d_fbdecc_c5_6_scanin[38]=ff_l2b_l2d_fbdecc_c5_2_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_4_scanin[38]=ff_l2b_l2d_fbdecc_c5_6_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_8_scanin[38]=ff_l2b_l2d_fbdecc_c5_4_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_10_scanin[38]=ff_l2b_l2d_fbdecc_c5_8_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_14_scanin[38]=ff_l2b_l2d_fbdecc_c5_10_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_12_scanin[38]=ff_l2b_l2d_fbdecc_c5_14_scanout[38];
assign ff_l2b_l2d_fbdecc_c5_16_scanin[38]=ff_l2b_l2d_fbdecc_c5_12_scanout[38];
assign ff_l2d_l2b_decc_out_c7_1_scanin[0]=ff_l2b_l2d_fbdecc_c5_16_scanout[38];
assign ff_l2d_l2b_decc_out_c7_5_scanin[0]=ff_l2d_l2b_decc_out_c7_1_scanout[0];
assign ff_l2d_l2b_decc_out_c7_3_scanin[0]=ff_l2d_l2b_decc_out_c7_5_scanout[0];
assign ff_l2d_l2b_decc_out_c7_7_scanin[0]=ff_l2d_l2b_decc_out_c7_3_scanout[0];
assign ff_l2d_l2b_decc_out_c7_9_scanin[0]=ff_l2d_l2b_decc_out_c7_7_scanout[0];
assign ff_l2d_l2b_decc_out_c7_13_scanin[0]=ff_l2d_l2b_decc_out_c7_9_scanout[0];
assign ff_l2d_l2b_decc_out_c7_11_scanin[0]=ff_l2d_l2b_decc_out_c7_13_scanout[0];
assign ff_l2d_l2b_decc_out_c7_15_scanin[0]=ff_l2d_l2b_decc_out_c7_11_scanout[0];
assign ff_l2d_l2b_decc_out_c7_1_scanin[1]=ff_l2d_l2b_decc_out_c7_15_scanout[0];
assign ff_l2d_l2b_decc_out_c7_5_scanin[1]=ff_l2d_l2b_decc_out_c7_1_scanout[1];
assign ff_l2d_l2b_decc_out_c7_3_scanin[1]=ff_l2d_l2b_decc_out_c7_5_scanout[1];
assign ff_l2d_l2b_decc_out_c7_7_scanin[1]=ff_l2d_l2b_decc_out_c7_3_scanout[1];
assign ff_l2d_l2b_decc_out_c7_9_scanin[1]=ff_l2d_l2b_decc_out_c7_7_scanout[1];
assign ff_l2d_l2b_decc_out_c7_13_scanin[1]=ff_l2d_l2b_decc_out_c7_9_scanout[1];
assign ff_l2d_l2b_decc_out_c7_11_scanin[1]=ff_l2d_l2b_decc_out_c7_13_scanout[1];
assign ff_l2d_l2b_decc_out_c7_15_scanin[1]=ff_l2d_l2b_decc_out_c7_11_scanout[1];
assign ff_l2d_l2b_decc_out_c7_1_scanin[2]=ff_l2d_l2b_decc_out_c7_15_scanout[1];
assign ff_l2d_l2b_decc_out_c7_5_scanin[2]=ff_l2d_l2b_decc_out_c7_1_scanout[2];
assign ff_l2d_l2b_decc_out_c7_3_scanin[2]=ff_l2d_l2b_decc_out_c7_5_scanout[2];
assign ff_l2d_l2b_decc_out_c7_7_scanin[2]=ff_l2d_l2b_decc_out_c7_3_scanout[2];
assign ff_l2d_l2b_decc_out_c7_9_scanin[2]=ff_l2d_l2b_decc_out_c7_7_scanout[2];
assign ff_l2d_l2b_decc_out_c7_13_scanin[2]=ff_l2d_l2b_decc_out_c7_9_scanout[2];
assign ff_l2d_l2b_decc_out_c7_11_scanin[2]=ff_l2d_l2b_decc_out_c7_13_scanout[2];
assign ff_l2d_l2b_decc_out_c7_15_scanin[2]=ff_l2d_l2b_decc_out_c7_11_scanout[2];
assign ff_l2d_l2b_decc_out_c7_1_scanin[3]=ff_l2d_l2b_decc_out_c7_15_scanout[2];
assign ff_l2d_l2b_decc_out_c7_5_scanin[3]=ff_l2d_l2b_decc_out_c7_1_scanout[3];
assign ff_l2d_l2b_decc_out_c7_3_scanin[3]=ff_l2d_l2b_decc_out_c7_5_scanout[3];
assign ff_l2d_l2b_decc_out_c7_7_scanin[3]=ff_l2d_l2b_decc_out_c7_3_scanout[3];
assign ff_l2d_l2b_decc_out_c7_9_scanin[3]=ff_l2d_l2b_decc_out_c7_7_scanout[3];
assign ff_l2d_l2b_decc_out_c7_13_scanin[3]=ff_l2d_l2b_decc_out_c7_9_scanout[3];
assign ff_l2d_l2b_decc_out_c7_11_scanin[3]=ff_l2d_l2b_decc_out_c7_13_scanout[3];
assign ff_l2d_l2b_decc_out_c7_15_scanin[3]=ff_l2d_l2b_decc_out_c7_11_scanout[3];
assign ff_l2d_l2b_decc_out_c7_1_scanin[4]=ff_l2d_l2b_decc_out_c7_15_scanout[3];
assign ff_l2d_l2b_decc_out_c7_5_scanin[4]=ff_l2d_l2b_decc_out_c7_1_scanout[4];
assign ff_l2d_l2b_decc_out_c7_3_scanin[4]=ff_l2d_l2b_decc_out_c7_5_scanout[4];
assign ff_l2d_l2b_decc_out_c7_7_scanin[4]=ff_l2d_l2b_decc_out_c7_3_scanout[4];
assign ff_l2d_l2b_decc_out_c7_9_scanin[4]=ff_l2d_l2b_decc_out_c7_7_scanout[4];
assign ff_l2d_l2b_decc_out_c7_13_scanin[4]=ff_l2d_l2b_decc_out_c7_9_scanout[4];
assign ff_l2d_l2b_decc_out_c7_11_scanin[4]=ff_l2d_l2b_decc_out_c7_13_scanout[4];
assign ff_l2d_l2b_decc_out_c7_15_scanin[4]=ff_l2d_l2b_decc_out_c7_11_scanout[4];
assign ff_l2d_l2b_decc_out_c7_1_scanin[5]=ff_l2d_l2b_decc_out_c7_15_scanout[4];
assign ff_l2d_l2b_decc_out_c7_5_scanin[5]=ff_l2d_l2b_decc_out_c7_1_scanout[5];
assign ff_l2d_l2b_decc_out_c7_3_scanin[5]=ff_l2d_l2b_decc_out_c7_5_scanout[5];
assign ff_l2d_l2b_decc_out_c7_7_scanin[5]=ff_l2d_l2b_decc_out_c7_3_scanout[5];
assign ff_l2d_l2b_decc_out_c7_9_scanin[5]=ff_l2d_l2b_decc_out_c7_7_scanout[5];
assign ff_l2d_l2b_decc_out_c7_13_scanin[5]=ff_l2d_l2b_decc_out_c7_9_scanout[5];
assign ff_l2d_l2b_decc_out_c7_11_scanin[5]=ff_l2d_l2b_decc_out_c7_13_scanout[5];
assign ff_l2d_l2b_decc_out_c7_15_scanin[5]=ff_l2d_l2b_decc_out_c7_11_scanout[5];
assign ff_l2d_l2b_decc_out_c7_1_scanin[6]=ff_l2d_l2b_decc_out_c7_15_scanout[5];
assign ff_l2d_l2b_decc_out_c7_5_scanin[6]=ff_l2d_l2b_decc_out_c7_1_scanout[6];
assign ff_l2d_l2b_decc_out_c7_3_scanin[6]=ff_l2d_l2b_decc_out_c7_5_scanout[6];
assign ff_l2d_l2b_decc_out_c7_7_scanin[6]=ff_l2d_l2b_decc_out_c7_3_scanout[6];
assign ff_l2d_l2b_decc_out_c7_9_scanin[6]=ff_l2d_l2b_decc_out_c7_7_scanout[6];
assign ff_l2d_l2b_decc_out_c7_13_scanin[6]=ff_l2d_l2b_decc_out_c7_9_scanout[6];
assign ff_l2d_l2b_decc_out_c7_11_scanin[6]=ff_l2d_l2b_decc_out_c7_13_scanout[6];
assign ff_l2d_l2b_decc_out_c7_15_scanin[6]=ff_l2d_l2b_decc_out_c7_11_scanout[6];
assign ff_l2d_l2b_decc_out_c7_1_scanin[7]=ff_l2d_l2b_decc_out_c7_15_scanout[6];
assign ff_l2d_l2b_decc_out_c7_5_scanin[7]=ff_l2d_l2b_decc_out_c7_1_scanout[7];
assign ff_l2d_l2b_decc_out_c7_3_scanin[7]=ff_l2d_l2b_decc_out_c7_5_scanout[7];
assign ff_l2d_l2b_decc_out_c7_7_scanin[7]=ff_l2d_l2b_decc_out_c7_3_scanout[7];
assign ff_l2d_l2b_decc_out_c7_9_scanin[7]=ff_l2d_l2b_decc_out_c7_7_scanout[7];
assign ff_l2d_l2b_decc_out_c7_13_scanin[7]=ff_l2d_l2b_decc_out_c7_9_scanout[7];
assign ff_l2d_l2b_decc_out_c7_11_scanin[7]=ff_l2d_l2b_decc_out_c7_13_scanout[7];
assign ff_l2d_l2b_decc_out_c7_15_scanin[7]=ff_l2d_l2b_decc_out_c7_11_scanout[7];
assign ff_l2d_l2b_decc_out_c7_1_scanin[8]=ff_l2d_l2b_decc_out_c7_15_scanout[7];
assign ff_l2d_l2b_decc_out_c7_5_scanin[8]=ff_l2d_l2b_decc_out_c7_1_scanout[8];
assign ff_l2d_l2b_decc_out_c7_3_scanin[8]=ff_l2d_l2b_decc_out_c7_5_scanout[8];
assign ff_l2d_l2b_decc_out_c7_7_scanin[8]=ff_l2d_l2b_decc_out_c7_3_scanout[8];
assign ff_l2d_l2b_decc_out_c7_9_scanin[8]=ff_l2d_l2b_decc_out_c7_7_scanout[8];
assign ff_l2d_l2b_decc_out_c7_13_scanin[8]=ff_l2d_l2b_decc_out_c7_9_scanout[8];
assign ff_l2d_l2b_decc_out_c7_11_scanin[8]=ff_l2d_l2b_decc_out_c7_13_scanout[8];
assign ff_l2d_l2b_decc_out_c7_15_scanin[8]=ff_l2d_l2b_decc_out_c7_11_scanout[8];
assign ff_l2d_l2b_decc_out_c7_1_scanin[9]=ff_l2d_l2b_decc_out_c7_15_scanout[8];
assign ff_l2d_l2b_decc_out_c7_5_scanin[9]=ff_l2d_l2b_decc_out_c7_1_scanout[9];
assign ff_l2d_l2b_decc_out_c7_3_scanin[9]=ff_l2d_l2b_decc_out_c7_5_scanout[9];
assign ff_l2d_l2b_decc_out_c7_7_scanin[9]=ff_l2d_l2b_decc_out_c7_3_scanout[9];
assign ff_l2d_l2b_decc_out_c7_9_scanin[9]=ff_l2d_l2b_decc_out_c7_7_scanout[9];
assign ff_l2d_l2b_decc_out_c7_13_scanin[9]=ff_l2d_l2b_decc_out_c7_9_scanout[9];
assign ff_l2d_l2b_decc_out_c7_11_scanin[9]=ff_l2d_l2b_decc_out_c7_13_scanout[9];
assign ff_l2d_l2b_decc_out_c7_15_scanin[9]=ff_l2d_l2b_decc_out_c7_11_scanout[9];
assign ff_l2d_l2b_decc_out_c7_1_scanin[10]=ff_l2d_l2b_decc_out_c7_15_scanout[9];
assign ff_l2d_l2b_decc_out_c7_5_scanin[10]=ff_l2d_l2b_decc_out_c7_1_scanout[10];
assign ff_l2d_l2b_decc_out_c7_3_scanin[10]=ff_l2d_l2b_decc_out_c7_5_scanout[10];
assign ff_l2d_l2b_decc_out_c7_7_scanin[10]=ff_l2d_l2b_decc_out_c7_3_scanout[10];
assign ff_l2d_l2b_decc_out_c7_9_scanin[10]=ff_l2d_l2b_decc_out_c7_7_scanout[10];
assign ff_l2d_l2b_decc_out_c7_13_scanin[10]=ff_l2d_l2b_decc_out_c7_9_scanout[10];
assign ff_l2d_l2b_decc_out_c7_11_scanin[10]=ff_l2d_l2b_decc_out_c7_13_scanout[10];
assign ff_l2d_l2b_decc_out_c7_15_scanin[10]=ff_l2d_l2b_decc_out_c7_11_scanout[10];
assign ff_l2d_l2b_decc_out_c7_1_scanin[11]=ff_l2d_l2b_decc_out_c7_15_scanout[10];
assign ff_l2d_l2b_decc_out_c7_5_scanin[11]=ff_l2d_l2b_decc_out_c7_1_scanout[11];
assign ff_l2d_l2b_decc_out_c7_3_scanin[11]=ff_l2d_l2b_decc_out_c7_5_scanout[11];
assign ff_l2d_l2b_decc_out_c7_7_scanin[11]=ff_l2d_l2b_decc_out_c7_3_scanout[11];
assign ff_l2d_l2b_decc_out_c7_9_scanin[11]=ff_l2d_l2b_decc_out_c7_7_scanout[11];
assign ff_l2d_l2b_decc_out_c7_13_scanin[11]=ff_l2d_l2b_decc_out_c7_9_scanout[11];
assign ff_l2d_l2b_decc_out_c7_11_scanin[11]=ff_l2d_l2b_decc_out_c7_13_scanout[11];
assign ff_l2d_l2b_decc_out_c7_15_scanin[11]=ff_l2d_l2b_decc_out_c7_11_scanout[11];
assign ff_l2d_l2b_decc_out_c7_1_scanin[12]=ff_l2d_l2b_decc_out_c7_15_scanout[11];
assign ff_l2d_l2b_decc_out_c7_5_scanin[12]=ff_l2d_l2b_decc_out_c7_1_scanout[12];
assign ff_l2d_l2b_decc_out_c7_3_scanin[12]=ff_l2d_l2b_decc_out_c7_5_scanout[12];
assign ff_l2d_l2b_decc_out_c7_7_scanin[12]=ff_l2d_l2b_decc_out_c7_3_scanout[12];
assign ff_l2d_l2b_decc_out_c7_9_scanin[12]=ff_l2d_l2b_decc_out_c7_7_scanout[12];
assign ff_l2d_l2b_decc_out_c7_13_scanin[12]=ff_l2d_l2b_decc_out_c7_9_scanout[12];
assign ff_l2d_l2b_decc_out_c7_11_scanin[12]=ff_l2d_l2b_decc_out_c7_13_scanout[12];
assign ff_l2d_l2b_decc_out_c7_15_scanin[12]=ff_l2d_l2b_decc_out_c7_11_scanout[12];
assign ff_l2d_l2b_decc_out_c7_1_scanin[13]=ff_l2d_l2b_decc_out_c7_15_scanout[12];
assign ff_l2d_l2b_decc_out_c7_5_scanin[13]=ff_l2d_l2b_decc_out_c7_1_scanout[13];
assign ff_l2d_l2b_decc_out_c7_3_scanin[13]=ff_l2d_l2b_decc_out_c7_5_scanout[13];
assign ff_l2d_l2b_decc_out_c7_7_scanin[13]=ff_l2d_l2b_decc_out_c7_3_scanout[13];
assign ff_l2d_l2b_decc_out_c7_9_scanin[13]=ff_l2d_l2b_decc_out_c7_7_scanout[13];
assign ff_l2d_l2b_decc_out_c7_13_scanin[13]=ff_l2d_l2b_decc_out_c7_9_scanout[13];
assign ff_l2d_l2b_decc_out_c7_11_scanin[13]=ff_l2d_l2b_decc_out_c7_13_scanout[13];
assign ff_l2d_l2b_decc_out_c7_15_scanin[13]=ff_l2d_l2b_decc_out_c7_11_scanout[13];
assign ff_l2d_l2b_decc_out_c7_1_scanin[14]=ff_l2d_l2b_decc_out_c7_15_scanout[13];
assign ff_l2d_l2b_decc_out_c7_5_scanin[14]=ff_l2d_l2b_decc_out_c7_1_scanout[14];
assign ff_l2d_l2b_decc_out_c7_3_scanin[14]=ff_l2d_l2b_decc_out_c7_5_scanout[14];
assign ff_l2d_l2b_decc_out_c7_7_scanin[14]=ff_l2d_l2b_decc_out_c7_3_scanout[14];
assign ff_l2d_l2b_decc_out_c7_9_scanin[14]=ff_l2d_l2b_decc_out_c7_7_scanout[14];
assign ff_l2d_l2b_decc_out_c7_13_scanin[14]=ff_l2d_l2b_decc_out_c7_9_scanout[14];
assign ff_l2d_l2b_decc_out_c7_11_scanin[14]=ff_l2d_l2b_decc_out_c7_13_scanout[14];
assign ff_l2d_l2b_decc_out_c7_15_scanin[14]=ff_l2d_l2b_decc_out_c7_11_scanout[14];
assign ff_l2d_l2b_decc_out_c7_1_scanin[15]=ff_l2d_l2b_decc_out_c7_15_scanout[14];
assign ff_l2d_l2b_decc_out_c7_5_scanin[15]=ff_l2d_l2b_decc_out_c7_1_scanout[15];
assign ff_l2d_l2b_decc_out_c7_3_scanin[15]=ff_l2d_l2b_decc_out_c7_5_scanout[15];
assign ff_l2d_l2b_decc_out_c7_7_scanin[15]=ff_l2d_l2b_decc_out_c7_3_scanout[15];
assign ff_l2d_l2b_decc_out_c7_9_scanin[15]=ff_l2d_l2b_decc_out_c7_7_scanout[15];
assign ff_l2d_l2b_decc_out_c7_13_scanin[15]=ff_l2d_l2b_decc_out_c7_9_scanout[15];
assign ff_l2d_l2b_decc_out_c7_11_scanin[15]=ff_l2d_l2b_decc_out_c7_13_scanout[15];
assign ff_l2d_l2b_decc_out_c7_15_scanin[15]=ff_l2d_l2b_decc_out_c7_11_scanout[15];
assign ff_l2d_l2b_decc_out_c7_1_scanin[16]=ff_l2d_l2b_decc_out_c7_15_scanout[15];
assign ff_l2d_l2b_decc_out_c7_5_scanin[16]=ff_l2d_l2b_decc_out_c7_1_scanout[16];
assign ff_l2d_l2b_decc_out_c7_3_scanin[16]=ff_l2d_l2b_decc_out_c7_5_scanout[16];
assign ff_l2d_l2b_decc_out_c7_7_scanin[16]=ff_l2d_l2b_decc_out_c7_3_scanout[16];
assign ff_l2d_l2b_decc_out_c7_9_scanin[16]=ff_l2d_l2b_decc_out_c7_7_scanout[16];
assign ff_l2d_l2b_decc_out_c7_13_scanin[16]=ff_l2d_l2b_decc_out_c7_9_scanout[16];
assign ff_l2d_l2b_decc_out_c7_11_scanin[16]=ff_l2d_l2b_decc_out_c7_13_scanout[16];
assign ff_l2d_l2b_decc_out_c7_15_scanin[16]=ff_l2d_l2b_decc_out_c7_11_scanout[16];
assign ff_l2d_l2b_decc_out_c7_1_scanin[17]=ff_l2d_l2b_decc_out_c7_15_scanout[16];
assign ff_l2d_l2b_decc_out_c7_5_scanin[17]=ff_l2d_l2b_decc_out_c7_1_scanout[17];
assign ff_l2d_l2b_decc_out_c7_3_scanin[17]=ff_l2d_l2b_decc_out_c7_5_scanout[17];
assign ff_l2d_l2b_decc_out_c7_7_scanin[17]=ff_l2d_l2b_decc_out_c7_3_scanout[17];
assign ff_l2d_l2b_decc_out_c7_9_scanin[17]=ff_l2d_l2b_decc_out_c7_7_scanout[17];
assign ff_l2d_l2b_decc_out_c7_13_scanin[17]=ff_l2d_l2b_decc_out_c7_9_scanout[17];
assign ff_l2d_l2b_decc_out_c7_11_scanin[17]=ff_l2d_l2b_decc_out_c7_13_scanout[17];
assign ff_l2d_l2b_decc_out_c7_15_scanin[17]=ff_l2d_l2b_decc_out_c7_11_scanout[17];
assign ff_l2d_l2b_decc_out_c7_1_scanin[18]=ff_l2d_l2b_decc_out_c7_15_scanout[17];
assign ff_l2d_l2b_decc_out_c7_5_scanin[18]=ff_l2d_l2b_decc_out_c7_1_scanout[18];
assign ff_l2d_l2b_decc_out_c7_3_scanin[18]=ff_l2d_l2b_decc_out_c7_5_scanout[18];
assign ff_l2d_l2b_decc_out_c7_7_scanin[18]=ff_l2d_l2b_decc_out_c7_3_scanout[18];
assign ff_l2d_l2b_decc_out_c7_9_scanin[18]=ff_l2d_l2b_decc_out_c7_7_scanout[18];
assign ff_l2d_l2b_decc_out_c7_13_scanin[18]=ff_l2d_l2b_decc_out_c7_9_scanout[18];
assign ff_l2d_l2b_decc_out_c7_11_scanin[18]=ff_l2d_l2b_decc_out_c7_13_scanout[18];
assign ff_l2d_l2b_decc_out_c7_15_scanin[18]=ff_l2d_l2b_decc_out_c7_11_scanout[18];
assign ff_l2d_l2b_decc_out_c7_1_scanin[19]=ff_l2d_l2b_decc_out_c7_15_scanout[18];
assign ff_l2d_l2b_decc_out_c7_5_scanin[19]=ff_l2d_l2b_decc_out_c7_1_scanout[19];
assign ff_l2d_l2b_decc_out_c7_3_scanin[19]=ff_l2d_l2b_decc_out_c7_5_scanout[19];
assign ff_l2d_l2b_decc_out_c7_7_scanin[19]=ff_l2d_l2b_decc_out_c7_3_scanout[19];
assign ff_l2d_l2b_decc_out_c7_9_scanin[19]=ff_l2d_l2b_decc_out_c7_7_scanout[19];
assign ff_l2d_l2b_decc_out_c7_13_scanin[19]=ff_l2d_l2b_decc_out_c7_9_scanout[19];
assign ff_l2d_l2b_decc_out_c7_11_scanin[19]=ff_l2d_l2b_decc_out_c7_13_scanout[19];
assign ff_l2d_l2b_decc_out_c7_15_scanin[19]=ff_l2d_l2b_decc_out_c7_11_scanout[19];
assign ff_l2d_l2b_decc_out_c7_1_scanin[20]=ff_l2d_l2b_decc_out_c7_15_scanout[19];
assign ff_l2d_l2b_decc_out_c7_5_scanin[20]=ff_l2d_l2b_decc_out_c7_1_scanout[20];
assign ff_l2d_l2b_decc_out_c7_3_scanin[20]=ff_l2d_l2b_decc_out_c7_5_scanout[20];
assign ff_l2d_l2b_decc_out_c7_7_scanin[20]=ff_l2d_l2b_decc_out_c7_3_scanout[20];
assign ff_l2d_l2b_decc_out_c7_9_scanin[20]=ff_l2d_l2b_decc_out_c7_7_scanout[20];
assign ff_l2d_l2b_decc_out_c7_13_scanin[20]=ff_l2d_l2b_decc_out_c7_9_scanout[20];
assign ff_l2d_l2b_decc_out_c7_11_scanin[20]=ff_l2d_l2b_decc_out_c7_13_scanout[20];
assign ff_l2d_l2b_decc_out_c7_15_scanin[20]=ff_l2d_l2b_decc_out_c7_11_scanout[20];
assign ff_l2d_l2b_decc_out_c7_1_scanin[21]=ff_l2d_l2b_decc_out_c7_15_scanout[20];
assign ff_l2d_l2b_decc_out_c7_5_scanin[21]=ff_l2d_l2b_decc_out_c7_1_scanout[21];
assign ff_l2d_l2b_decc_out_c7_3_scanin[21]=ff_l2d_l2b_decc_out_c7_5_scanout[21];
assign ff_l2d_l2b_decc_out_c7_7_scanin[21]=ff_l2d_l2b_decc_out_c7_3_scanout[21];
assign ff_l2d_l2b_decc_out_c7_9_scanin[21]=ff_l2d_l2b_decc_out_c7_7_scanout[21];
assign ff_l2d_l2b_decc_out_c7_13_scanin[21]=ff_l2d_l2b_decc_out_c7_9_scanout[21];
assign ff_l2d_l2b_decc_out_c7_11_scanin[21]=ff_l2d_l2b_decc_out_c7_13_scanout[21];
assign ff_l2d_l2b_decc_out_c7_15_scanin[21]=ff_l2d_l2b_decc_out_c7_11_scanout[21];
assign ff_l2d_l2b_decc_out_c7_1_scanin[22]=ff_l2d_l2b_decc_out_c7_15_scanout[21];
assign ff_l2d_l2b_decc_out_c7_5_scanin[22]=ff_l2d_l2b_decc_out_c7_1_scanout[22];
assign ff_l2d_l2b_decc_out_c7_3_scanin[22]=ff_l2d_l2b_decc_out_c7_5_scanout[22];
assign ff_l2d_l2b_decc_out_c7_7_scanin[22]=ff_l2d_l2b_decc_out_c7_3_scanout[22];
assign ff_l2d_l2b_decc_out_c7_9_scanin[22]=ff_l2d_l2b_decc_out_c7_7_scanout[22];
assign ff_l2d_l2b_decc_out_c7_13_scanin[22]=ff_l2d_l2b_decc_out_c7_9_scanout[22];
assign ff_l2d_l2b_decc_out_c7_11_scanin[22]=ff_l2d_l2b_decc_out_c7_13_scanout[22];
assign ff_l2d_l2b_decc_out_c7_15_scanin[22]=ff_l2d_l2b_decc_out_c7_11_scanout[22];
assign ff_l2d_l2b_decc_out_c7_1_scanin[23]=ff_l2d_l2b_decc_out_c7_15_scanout[22];
assign ff_l2d_l2b_decc_out_c7_5_scanin[23]=ff_l2d_l2b_decc_out_c7_1_scanout[23];
assign ff_l2d_l2b_decc_out_c7_3_scanin[23]=ff_l2d_l2b_decc_out_c7_5_scanout[23];
assign ff_l2d_l2b_decc_out_c7_7_scanin[23]=ff_l2d_l2b_decc_out_c7_3_scanout[23];
assign ff_l2d_l2b_decc_out_c7_9_scanin[23]=ff_l2d_l2b_decc_out_c7_7_scanout[23];
assign ff_l2d_l2b_decc_out_c7_13_scanin[23]=ff_l2d_l2b_decc_out_c7_9_scanout[23];
assign ff_l2d_l2b_decc_out_c7_11_scanin[23]=ff_l2d_l2b_decc_out_c7_13_scanout[23];
assign ff_l2d_l2b_decc_out_c7_15_scanin[23]=ff_l2d_l2b_decc_out_c7_11_scanout[23];
assign ff_l2d_l2b_decc_out_c7_1_scanin[24]=ff_l2d_l2b_decc_out_c7_15_scanout[23];
assign ff_l2d_l2b_decc_out_c7_5_scanin[24]=ff_l2d_l2b_decc_out_c7_1_scanout[24];
assign ff_l2d_l2b_decc_out_c7_3_scanin[24]=ff_l2d_l2b_decc_out_c7_5_scanout[24];
assign ff_l2d_l2b_decc_out_c7_7_scanin[24]=ff_l2d_l2b_decc_out_c7_3_scanout[24];
assign ff_l2d_l2b_decc_out_c7_9_scanin[24]=ff_l2d_l2b_decc_out_c7_7_scanout[24];
assign ff_l2d_l2b_decc_out_c7_13_scanin[24]=ff_l2d_l2b_decc_out_c7_9_scanout[24];
assign ff_l2d_l2b_decc_out_c7_11_scanin[24]=ff_l2d_l2b_decc_out_c7_13_scanout[24];
assign ff_l2d_l2b_decc_out_c7_15_scanin[24]=ff_l2d_l2b_decc_out_c7_11_scanout[24];
assign ff_l2d_l2b_decc_out_c7_1_scanin[25]=ff_l2d_l2b_decc_out_c7_15_scanout[24];
assign ff_l2d_l2b_decc_out_c7_5_scanin[25]=ff_l2d_l2b_decc_out_c7_1_scanout[25];
assign ff_l2d_l2b_decc_out_c7_3_scanin[25]=ff_l2d_l2b_decc_out_c7_5_scanout[25];
assign ff_l2d_l2b_decc_out_c7_7_scanin[25]=ff_l2d_l2b_decc_out_c7_3_scanout[25];
assign ff_l2d_l2b_decc_out_c7_9_scanin[25]=ff_l2d_l2b_decc_out_c7_7_scanout[25];
assign ff_l2d_l2b_decc_out_c7_13_scanin[25]=ff_l2d_l2b_decc_out_c7_9_scanout[25];
assign ff_l2d_l2b_decc_out_c7_11_scanin[25]=ff_l2d_l2b_decc_out_c7_13_scanout[25];
assign ff_l2d_l2b_decc_out_c7_15_scanin[25]=ff_l2d_l2b_decc_out_c7_11_scanout[25];
assign ff_l2d_l2b_decc_out_c7_1_scanin[26]=ff_l2d_l2b_decc_out_c7_15_scanout[25];
assign ff_l2d_l2b_decc_out_c7_5_scanin[26]=ff_l2d_l2b_decc_out_c7_1_scanout[26];
assign ff_l2d_l2b_decc_out_c7_3_scanin[26]=ff_l2d_l2b_decc_out_c7_5_scanout[26];
assign ff_l2d_l2b_decc_out_c7_7_scanin[26]=ff_l2d_l2b_decc_out_c7_3_scanout[26];
assign ff_l2d_l2b_decc_out_c7_9_scanin[26]=ff_l2d_l2b_decc_out_c7_7_scanout[26];
assign ff_l2d_l2b_decc_out_c7_13_scanin[26]=ff_l2d_l2b_decc_out_c7_9_scanout[26];
assign ff_l2d_l2b_decc_out_c7_11_scanin[26]=ff_l2d_l2b_decc_out_c7_13_scanout[26];
assign ff_l2d_l2b_decc_out_c7_15_scanin[26]=ff_l2d_l2b_decc_out_c7_11_scanout[26];
assign ff_l2d_l2b_decc_out_c7_1_scanin[27]=ff_l2d_l2b_decc_out_c7_15_scanout[26];
assign ff_l2d_l2b_decc_out_c7_5_scanin[27]=ff_l2d_l2b_decc_out_c7_1_scanout[27];
assign ff_l2d_l2b_decc_out_c7_3_scanin[27]=ff_l2d_l2b_decc_out_c7_5_scanout[27];
assign ff_l2d_l2b_decc_out_c7_7_scanin[27]=ff_l2d_l2b_decc_out_c7_3_scanout[27];
assign ff_l2d_l2b_decc_out_c7_9_scanin[27]=ff_l2d_l2b_decc_out_c7_7_scanout[27];
assign ff_l2d_l2b_decc_out_c7_13_scanin[27]=ff_l2d_l2b_decc_out_c7_9_scanout[27];
assign ff_l2d_l2b_decc_out_c7_11_scanin[27]=ff_l2d_l2b_decc_out_c7_13_scanout[27];
assign ff_l2d_l2b_decc_out_c7_15_scanin[27]=ff_l2d_l2b_decc_out_c7_11_scanout[27];
assign ff_l2d_l2b_decc_out_c7_1_scanin[28]=ff_l2d_l2b_decc_out_c7_15_scanout[27];
assign ff_l2d_l2b_decc_out_c7_5_scanin[28]=ff_l2d_l2b_decc_out_c7_1_scanout[28];
assign ff_l2d_l2b_decc_out_c7_3_scanin[28]=ff_l2d_l2b_decc_out_c7_5_scanout[28];
assign ff_l2d_l2b_decc_out_c7_7_scanin[28]=ff_l2d_l2b_decc_out_c7_3_scanout[28];
assign ff_l2d_l2b_decc_out_c7_9_scanin[28]=ff_l2d_l2b_decc_out_c7_7_scanout[28];
assign ff_l2d_l2b_decc_out_c7_13_scanin[28]=ff_l2d_l2b_decc_out_c7_9_scanout[28];
assign ff_l2d_l2b_decc_out_c7_11_scanin[28]=ff_l2d_l2b_decc_out_c7_13_scanout[28];
assign ff_l2d_l2b_decc_out_c7_15_scanin[28]=ff_l2d_l2b_decc_out_c7_11_scanout[28];
assign ff_l2d_l2b_decc_out_c7_1_scanin[29]=ff_l2d_l2b_decc_out_c7_15_scanout[28];
assign ff_l2d_l2b_decc_out_c7_5_scanin[29]=ff_l2d_l2b_decc_out_c7_1_scanout[29];
assign ff_l2d_l2b_decc_out_c7_3_scanin[29]=ff_l2d_l2b_decc_out_c7_5_scanout[29];
assign ff_l2d_l2b_decc_out_c7_7_scanin[29]=ff_l2d_l2b_decc_out_c7_3_scanout[29];
assign ff_l2d_l2b_decc_out_c7_9_scanin[29]=ff_l2d_l2b_decc_out_c7_7_scanout[29];
assign ff_l2d_l2b_decc_out_c7_13_scanin[29]=ff_l2d_l2b_decc_out_c7_9_scanout[29];
assign ff_l2d_l2b_decc_out_c7_11_scanin[29]=ff_l2d_l2b_decc_out_c7_13_scanout[29];
assign ff_l2d_l2b_decc_out_c7_15_scanin[29]=ff_l2d_l2b_decc_out_c7_11_scanout[29];
assign ff_l2d_l2b_decc_out_c7_1_scanin[30]=ff_l2d_l2b_decc_out_c7_15_scanout[29];
assign ff_l2d_l2b_decc_out_c7_5_scanin[30]=ff_l2d_l2b_decc_out_c7_1_scanout[30];
assign ff_l2d_l2b_decc_out_c7_3_scanin[30]=ff_l2d_l2b_decc_out_c7_5_scanout[30];
assign ff_l2d_l2b_decc_out_c7_7_scanin[30]=ff_l2d_l2b_decc_out_c7_3_scanout[30];
assign ff_l2d_l2b_decc_out_c7_9_scanin[30]=ff_l2d_l2b_decc_out_c7_7_scanout[30];
assign ff_l2d_l2b_decc_out_c7_13_scanin[30]=ff_l2d_l2b_decc_out_c7_9_scanout[30];
assign ff_l2d_l2b_decc_out_c7_11_scanin[30]=ff_l2d_l2b_decc_out_c7_13_scanout[30];
assign ff_l2d_l2b_decc_out_c7_15_scanin[30]=ff_l2d_l2b_decc_out_c7_11_scanout[30];
assign ff_l2d_l2b_decc_out_c7_1_scanin[31]=ff_l2d_l2b_decc_out_c7_15_scanout[30];
assign ff_l2d_l2b_decc_out_c7_5_scanin[31]=ff_l2d_l2b_decc_out_c7_1_scanout[31];
assign ff_l2d_l2b_decc_out_c7_3_scanin[31]=ff_l2d_l2b_decc_out_c7_5_scanout[31];
assign ff_l2d_l2b_decc_out_c7_7_scanin[31]=ff_l2d_l2b_decc_out_c7_3_scanout[31];
assign ff_l2d_l2b_decc_out_c7_9_scanin[31]=ff_l2d_l2b_decc_out_c7_7_scanout[31];
assign ff_l2d_l2b_decc_out_c7_13_scanin[31]=ff_l2d_l2b_decc_out_c7_9_scanout[31];
assign ff_l2d_l2b_decc_out_c7_11_scanin[31]=ff_l2d_l2b_decc_out_c7_13_scanout[31];
assign ff_l2d_l2b_decc_out_c7_15_scanin[31]=ff_l2d_l2b_decc_out_c7_11_scanout[31];
assign ff_l2d_l2b_decc_out_c7_1_scanin[32]=ff_l2d_l2b_decc_out_c7_15_scanout[31];
assign ff_l2d_l2b_decc_out_c7_5_scanin[32]=ff_l2d_l2b_decc_out_c7_1_scanout[32];
assign ff_l2d_l2b_decc_out_c7_3_scanin[32]=ff_l2d_l2b_decc_out_c7_5_scanout[32];
assign ff_l2d_l2b_decc_out_c7_7_scanin[32]=ff_l2d_l2b_decc_out_c7_3_scanout[32];
assign ff_l2d_l2b_decc_out_c7_9_scanin[32]=ff_l2d_l2b_decc_out_c7_7_scanout[32];
assign ff_l2d_l2b_decc_out_c7_13_scanin[32]=ff_l2d_l2b_decc_out_c7_9_scanout[32];
assign ff_l2d_l2b_decc_out_c7_11_scanin[32]=ff_l2d_l2b_decc_out_c7_13_scanout[32];
assign ff_l2d_l2b_decc_out_c7_15_scanin[32]=ff_l2d_l2b_decc_out_c7_11_scanout[32];
assign ff_l2d_l2b_decc_out_c7_1_scanin[33]=ff_l2d_l2b_decc_out_c7_15_scanout[32];
assign ff_l2d_l2b_decc_out_c7_5_scanin[33]=ff_l2d_l2b_decc_out_c7_1_scanout[33];
assign ff_l2d_l2b_decc_out_c7_3_scanin[33]=ff_l2d_l2b_decc_out_c7_5_scanout[33];
assign ff_l2d_l2b_decc_out_c7_7_scanin[33]=ff_l2d_l2b_decc_out_c7_3_scanout[33];
assign ff_l2d_l2b_decc_out_c7_9_scanin[33]=ff_l2d_l2b_decc_out_c7_7_scanout[33];
assign ff_l2d_l2b_decc_out_c7_13_scanin[33]=ff_l2d_l2b_decc_out_c7_9_scanout[33];
assign ff_l2d_l2b_decc_out_c7_11_scanin[33]=ff_l2d_l2b_decc_out_c7_13_scanout[33];
assign ff_l2d_l2b_decc_out_c7_15_scanin[33]=ff_l2d_l2b_decc_out_c7_11_scanout[33];
assign ff_l2d_l2b_decc_out_c7_1_scanin[34]=ff_l2d_l2b_decc_out_c7_15_scanout[33];
assign ff_l2d_l2b_decc_out_c7_5_scanin[34]=ff_l2d_l2b_decc_out_c7_1_scanout[34];
assign ff_l2d_l2b_decc_out_c7_3_scanin[34]=ff_l2d_l2b_decc_out_c7_5_scanout[34];
assign ff_l2d_l2b_decc_out_c7_7_scanin[34]=ff_l2d_l2b_decc_out_c7_3_scanout[34];
assign ff_l2d_l2b_decc_out_c7_9_scanin[34]=ff_l2d_l2b_decc_out_c7_7_scanout[34];
assign ff_l2d_l2b_decc_out_c7_13_scanin[34]=ff_l2d_l2b_decc_out_c7_9_scanout[34];
assign ff_l2d_l2b_decc_out_c7_11_scanin[34]=ff_l2d_l2b_decc_out_c7_13_scanout[34];
assign ff_l2d_l2b_decc_out_c7_15_scanin[34]=ff_l2d_l2b_decc_out_c7_11_scanout[34];
assign ff_l2d_l2b_decc_out_c7_1_scanin[35]=ff_l2d_l2b_decc_out_c7_15_scanout[34];
assign ff_l2d_l2b_decc_out_c7_5_scanin[35]=ff_l2d_l2b_decc_out_c7_1_scanout[35];
assign ff_l2d_l2b_decc_out_c7_3_scanin[35]=ff_l2d_l2b_decc_out_c7_5_scanout[35];
assign ff_l2d_l2b_decc_out_c7_7_scanin[35]=ff_l2d_l2b_decc_out_c7_3_scanout[35];
assign ff_l2d_l2b_decc_out_c7_9_scanin[35]=ff_l2d_l2b_decc_out_c7_7_scanout[35];
assign ff_l2d_l2b_decc_out_c7_13_scanin[35]=ff_l2d_l2b_decc_out_c7_9_scanout[35];
assign ff_l2d_l2b_decc_out_c7_11_scanin[35]=ff_l2d_l2b_decc_out_c7_13_scanout[35];
assign ff_l2d_l2b_decc_out_c7_15_scanin[35]=ff_l2d_l2b_decc_out_c7_11_scanout[35];
assign ff_l2d_l2b_decc_out_c7_1_scanin[36]=ff_l2d_l2b_decc_out_c7_15_scanout[35];
assign ff_l2d_l2b_decc_out_c7_5_scanin[36]=ff_l2d_l2b_decc_out_c7_1_scanout[36];
assign ff_l2d_l2b_decc_out_c7_3_scanin[36]=ff_l2d_l2b_decc_out_c7_5_scanout[36];
assign ff_l2d_l2b_decc_out_c7_7_scanin[36]=ff_l2d_l2b_decc_out_c7_3_scanout[36];
assign ff_l2d_l2b_decc_out_c7_9_scanin[36]=ff_l2d_l2b_decc_out_c7_7_scanout[36];
assign ff_l2d_l2b_decc_out_c7_13_scanin[36]=ff_l2d_l2b_decc_out_c7_9_scanout[36];
assign ff_l2d_l2b_decc_out_c7_11_scanin[36]=ff_l2d_l2b_decc_out_c7_13_scanout[36];
assign ff_l2d_l2b_decc_out_c7_15_scanin[36]=ff_l2d_l2b_decc_out_c7_11_scanout[36];
assign ff_l2d_l2b_decc_out_c7_1_scanin[37]=ff_l2d_l2b_decc_out_c7_15_scanout[36];
assign ff_l2d_l2b_decc_out_c7_5_scanin[37]=ff_l2d_l2b_decc_out_c7_1_scanout[37];
assign ff_l2d_l2b_decc_out_c7_3_scanin[37]=ff_l2d_l2b_decc_out_c7_5_scanout[37];
assign ff_l2d_l2b_decc_out_c7_7_scanin[37]=ff_l2d_l2b_decc_out_c7_3_scanout[37];
assign ff_l2d_l2b_decc_out_c7_9_scanin[37]=ff_l2d_l2b_decc_out_c7_7_scanout[37];
assign ff_l2d_l2b_decc_out_c7_13_scanin[37]=ff_l2d_l2b_decc_out_c7_9_scanout[37];
assign ff_l2d_l2b_decc_out_c7_11_scanin[37]=ff_l2d_l2b_decc_out_c7_13_scanout[37];
assign ff_l2d_l2b_decc_out_c7_15_scanin[37]=ff_l2d_l2b_decc_out_c7_11_scanout[37];
assign ff_l2d_l2b_decc_out_c7_1_scanin[38]=ff_l2d_l2b_decc_out_c7_15_scanout[37];
assign ff_l2d_l2b_decc_out_c7_5_scanin[38]=ff_l2d_l2b_decc_out_c7_1_scanout[38];
assign ff_l2d_l2b_decc_out_c7_3_scanin[38]=ff_l2d_l2b_decc_out_c7_5_scanout[38];
assign ff_l2d_l2b_decc_out_c7_7_scanin[38]=ff_l2d_l2b_decc_out_c7_3_scanout[38];
assign ff_l2d_l2b_decc_out_c7_9_scanin[38]=ff_l2d_l2b_decc_out_c7_7_scanout[38];
assign ff_l2d_l2b_decc_out_c7_13_scanin[38]=ff_l2d_l2b_decc_out_c7_9_scanout[38];
assign ff_l2d_l2b_decc_out_c7_11_scanin[38]=ff_l2d_l2b_decc_out_c7_13_scanout[38];
assign ff_l2d_l2b_decc_out_c7_15_scanin[38]=ff_l2d_l2b_decc_out_c7_11_scanout[38];
assign ff_l2d_l2b_decc_out_c7_2_scanin[0]=ff_l2d_l2b_decc_out_c7_15_scanout[38];
assign ff_l2d_l2b_decc_out_c7_6_scanin[0]=ff_l2d_l2b_decc_out_c7_2_scanout[0];
assign ff_l2d_l2b_decc_out_c7_4_scanin[0]=ff_l2d_l2b_decc_out_c7_6_scanout[0];
assign ff_l2d_l2b_decc_out_c7_8_scanin[0]=ff_l2d_l2b_decc_out_c7_4_scanout[0];
assign ff_l2d_l2b_decc_out_c7_10_scanin[0]=ff_l2d_l2b_decc_out_c7_8_scanout[0];
assign ff_l2d_l2b_decc_out_c7_14_scanin[0]=ff_l2d_l2b_decc_out_c7_10_scanout[0];
assign ff_l2d_l2b_decc_out_c7_12_scanin[0]=ff_l2d_l2b_decc_out_c7_14_scanout[0];
assign ff_l2d_l2b_decc_out_c7_16_scanin[0]=ff_l2d_l2b_decc_out_c7_12_scanout[0];
assign ff_l2d_l2b_decc_out_c7_2_scanin[1]=ff_l2d_l2b_decc_out_c7_16_scanout[0];
assign ff_l2d_l2b_decc_out_c7_6_scanin[1]=ff_l2d_l2b_decc_out_c7_2_scanout[1];
assign ff_l2d_l2b_decc_out_c7_4_scanin[1]=ff_l2d_l2b_decc_out_c7_6_scanout[1];
assign ff_l2d_l2b_decc_out_c7_8_scanin[1]=ff_l2d_l2b_decc_out_c7_4_scanout[1];
assign ff_l2d_l2b_decc_out_c7_10_scanin[1]=ff_l2d_l2b_decc_out_c7_8_scanout[1];
assign ff_l2d_l2b_decc_out_c7_14_scanin[1]=ff_l2d_l2b_decc_out_c7_10_scanout[1];
assign ff_l2d_l2b_decc_out_c7_12_scanin[1]=ff_l2d_l2b_decc_out_c7_14_scanout[1];
assign ff_l2d_l2b_decc_out_c7_16_scanin[1]=ff_l2d_l2b_decc_out_c7_12_scanout[1];
assign ff_l2d_l2b_decc_out_c7_2_scanin[2]=ff_l2d_l2b_decc_out_c7_16_scanout[1];
assign ff_l2d_l2b_decc_out_c7_6_scanin[2]=ff_l2d_l2b_decc_out_c7_2_scanout[2];
assign ff_l2d_l2b_decc_out_c7_4_scanin[2]=ff_l2d_l2b_decc_out_c7_6_scanout[2];
assign ff_l2d_l2b_decc_out_c7_8_scanin[2]=ff_l2d_l2b_decc_out_c7_4_scanout[2];
assign ff_l2d_l2b_decc_out_c7_10_scanin[2]=ff_l2d_l2b_decc_out_c7_8_scanout[2];
assign ff_l2d_l2b_decc_out_c7_14_scanin[2]=ff_l2d_l2b_decc_out_c7_10_scanout[2];
assign ff_l2d_l2b_decc_out_c7_12_scanin[2]=ff_l2d_l2b_decc_out_c7_14_scanout[2];
assign ff_l2d_l2b_decc_out_c7_16_scanin[2]=ff_l2d_l2b_decc_out_c7_12_scanout[2];
assign ff_l2d_l2b_decc_out_c7_2_scanin[3]=ff_l2d_l2b_decc_out_c7_16_scanout[2];
assign ff_l2d_l2b_decc_out_c7_6_scanin[3]=ff_l2d_l2b_decc_out_c7_2_scanout[3];
assign ff_l2d_l2b_decc_out_c7_4_scanin[3]=ff_l2d_l2b_decc_out_c7_6_scanout[3];
assign ff_l2d_l2b_decc_out_c7_8_scanin[3]=ff_l2d_l2b_decc_out_c7_4_scanout[3];
assign ff_l2d_l2b_decc_out_c7_10_scanin[3]=ff_l2d_l2b_decc_out_c7_8_scanout[3];
assign ff_l2d_l2b_decc_out_c7_14_scanin[3]=ff_l2d_l2b_decc_out_c7_10_scanout[3];
assign ff_l2d_l2b_decc_out_c7_12_scanin[3]=ff_l2d_l2b_decc_out_c7_14_scanout[3];
assign ff_l2d_l2b_decc_out_c7_16_scanin[3]=ff_l2d_l2b_decc_out_c7_12_scanout[3];
assign ff_l2d_l2b_decc_out_c7_2_scanin[4]=ff_l2d_l2b_decc_out_c7_16_scanout[3];
assign ff_l2d_l2b_decc_out_c7_6_scanin[4]=ff_l2d_l2b_decc_out_c7_2_scanout[4];
assign ff_l2d_l2b_decc_out_c7_4_scanin[4]=ff_l2d_l2b_decc_out_c7_6_scanout[4];
assign ff_l2d_l2b_decc_out_c7_8_scanin[4]=ff_l2d_l2b_decc_out_c7_4_scanout[4];
assign ff_l2d_l2b_decc_out_c7_10_scanin[4]=ff_l2d_l2b_decc_out_c7_8_scanout[4];
assign ff_l2d_l2b_decc_out_c7_14_scanin[4]=ff_l2d_l2b_decc_out_c7_10_scanout[4];
assign ff_l2d_l2b_decc_out_c7_12_scanin[4]=ff_l2d_l2b_decc_out_c7_14_scanout[4];
assign ff_l2d_l2b_decc_out_c7_16_scanin[4]=ff_l2d_l2b_decc_out_c7_12_scanout[4];
assign ff_l2d_l2b_decc_out_c7_2_scanin[5]=ff_l2d_l2b_decc_out_c7_16_scanout[4];
assign ff_l2d_l2b_decc_out_c7_6_scanin[5]=ff_l2d_l2b_decc_out_c7_2_scanout[5];
assign ff_l2d_l2b_decc_out_c7_4_scanin[5]=ff_l2d_l2b_decc_out_c7_6_scanout[5];
assign ff_l2d_l2b_decc_out_c7_8_scanin[5]=ff_l2d_l2b_decc_out_c7_4_scanout[5];
assign ff_l2d_l2b_decc_out_c7_10_scanin[5]=ff_l2d_l2b_decc_out_c7_8_scanout[5];
assign ff_l2d_l2b_decc_out_c7_14_scanin[5]=ff_l2d_l2b_decc_out_c7_10_scanout[5];
assign ff_l2d_l2b_decc_out_c7_12_scanin[5]=ff_l2d_l2b_decc_out_c7_14_scanout[5];
assign ff_l2d_l2b_decc_out_c7_16_scanin[5]=ff_l2d_l2b_decc_out_c7_12_scanout[5];
assign ff_l2d_l2b_decc_out_c7_2_scanin[6]=ff_l2d_l2b_decc_out_c7_16_scanout[5];
assign ff_l2d_l2b_decc_out_c7_6_scanin[6]=ff_l2d_l2b_decc_out_c7_2_scanout[6];
assign ff_l2d_l2b_decc_out_c7_4_scanin[6]=ff_l2d_l2b_decc_out_c7_6_scanout[6];
assign ff_l2d_l2b_decc_out_c7_8_scanin[6]=ff_l2d_l2b_decc_out_c7_4_scanout[6];
assign ff_l2d_l2b_decc_out_c7_10_scanin[6]=ff_l2d_l2b_decc_out_c7_8_scanout[6];
assign ff_l2d_l2b_decc_out_c7_14_scanin[6]=ff_l2d_l2b_decc_out_c7_10_scanout[6];
assign ff_l2d_l2b_decc_out_c7_12_scanin[6]=ff_l2d_l2b_decc_out_c7_14_scanout[6];
assign ff_l2d_l2b_decc_out_c7_16_scanin[6]=ff_l2d_l2b_decc_out_c7_12_scanout[6];
assign ff_l2d_l2b_decc_out_c7_2_scanin[7]=ff_l2d_l2b_decc_out_c7_16_scanout[6];
assign ff_l2d_l2b_decc_out_c7_6_scanin[7]=ff_l2d_l2b_decc_out_c7_2_scanout[7];
assign ff_l2d_l2b_decc_out_c7_4_scanin[7]=ff_l2d_l2b_decc_out_c7_6_scanout[7];
assign ff_l2d_l2b_decc_out_c7_8_scanin[7]=ff_l2d_l2b_decc_out_c7_4_scanout[7];
assign ff_l2d_l2b_decc_out_c7_10_scanin[7]=ff_l2d_l2b_decc_out_c7_8_scanout[7];
assign ff_l2d_l2b_decc_out_c7_14_scanin[7]=ff_l2d_l2b_decc_out_c7_10_scanout[7];
assign ff_l2d_l2b_decc_out_c7_12_scanin[7]=ff_l2d_l2b_decc_out_c7_14_scanout[7];
assign ff_l2d_l2b_decc_out_c7_16_scanin[7]=ff_l2d_l2b_decc_out_c7_12_scanout[7];
assign ff_l2d_l2b_decc_out_c7_2_scanin[8]=ff_l2d_l2b_decc_out_c7_16_scanout[7];
assign ff_l2d_l2b_decc_out_c7_6_scanin[8]=ff_l2d_l2b_decc_out_c7_2_scanout[8];
assign ff_l2d_l2b_decc_out_c7_4_scanin[8]=ff_l2d_l2b_decc_out_c7_6_scanout[8];
assign ff_l2d_l2b_decc_out_c7_8_scanin[8]=ff_l2d_l2b_decc_out_c7_4_scanout[8];
assign ff_l2d_l2b_decc_out_c7_10_scanin[8]=ff_l2d_l2b_decc_out_c7_8_scanout[8];
assign ff_l2d_l2b_decc_out_c7_14_scanin[8]=ff_l2d_l2b_decc_out_c7_10_scanout[8];
assign ff_l2d_l2b_decc_out_c7_12_scanin[8]=ff_l2d_l2b_decc_out_c7_14_scanout[8];
assign ff_l2d_l2b_decc_out_c7_16_scanin[8]=ff_l2d_l2b_decc_out_c7_12_scanout[8];
assign ff_l2d_l2b_decc_out_c7_2_scanin[9]=ff_l2d_l2b_decc_out_c7_16_scanout[8];
assign ff_l2d_l2b_decc_out_c7_6_scanin[9]=ff_l2d_l2b_decc_out_c7_2_scanout[9];
assign ff_l2d_l2b_decc_out_c7_4_scanin[9]=ff_l2d_l2b_decc_out_c7_6_scanout[9];
assign ff_l2d_l2b_decc_out_c7_8_scanin[9]=ff_l2d_l2b_decc_out_c7_4_scanout[9];
assign ff_l2d_l2b_decc_out_c7_10_scanin[9]=ff_l2d_l2b_decc_out_c7_8_scanout[9];
assign ff_l2d_l2b_decc_out_c7_14_scanin[9]=ff_l2d_l2b_decc_out_c7_10_scanout[9];
assign ff_l2d_l2b_decc_out_c7_12_scanin[9]=ff_l2d_l2b_decc_out_c7_14_scanout[9];
assign ff_l2d_l2b_decc_out_c7_16_scanin[9]=ff_l2d_l2b_decc_out_c7_12_scanout[9];
assign ff_l2d_l2b_decc_out_c7_2_scanin[10]=ff_l2d_l2b_decc_out_c7_16_scanout[9];
assign ff_l2d_l2b_decc_out_c7_6_scanin[10]=ff_l2d_l2b_decc_out_c7_2_scanout[10];
assign ff_l2d_l2b_decc_out_c7_4_scanin[10]=ff_l2d_l2b_decc_out_c7_6_scanout[10];
assign ff_l2d_l2b_decc_out_c7_8_scanin[10]=ff_l2d_l2b_decc_out_c7_4_scanout[10];
assign ff_l2d_l2b_decc_out_c7_10_scanin[10]=ff_l2d_l2b_decc_out_c7_8_scanout[10];
assign ff_l2d_l2b_decc_out_c7_14_scanin[10]=ff_l2d_l2b_decc_out_c7_10_scanout[10];
assign ff_l2d_l2b_decc_out_c7_12_scanin[10]=ff_l2d_l2b_decc_out_c7_14_scanout[10];
assign ff_l2d_l2b_decc_out_c7_16_scanin[10]=ff_l2d_l2b_decc_out_c7_12_scanout[10];
assign ff_l2d_l2b_decc_out_c7_2_scanin[11]=ff_l2d_l2b_decc_out_c7_16_scanout[10];
assign ff_l2d_l2b_decc_out_c7_6_scanin[11]=ff_l2d_l2b_decc_out_c7_2_scanout[11];
assign ff_l2d_l2b_decc_out_c7_4_scanin[11]=ff_l2d_l2b_decc_out_c7_6_scanout[11];
assign ff_l2d_l2b_decc_out_c7_8_scanin[11]=ff_l2d_l2b_decc_out_c7_4_scanout[11];
assign ff_l2d_l2b_decc_out_c7_10_scanin[11]=ff_l2d_l2b_decc_out_c7_8_scanout[11];
assign ff_l2d_l2b_decc_out_c7_14_scanin[11]=ff_l2d_l2b_decc_out_c7_10_scanout[11];
assign ff_l2d_l2b_decc_out_c7_12_scanin[11]=ff_l2d_l2b_decc_out_c7_14_scanout[11];
assign ff_l2d_l2b_decc_out_c7_16_scanin[11]=ff_l2d_l2b_decc_out_c7_12_scanout[11];
assign ff_l2d_l2b_decc_out_c7_2_scanin[12]=ff_l2d_l2b_decc_out_c7_16_scanout[11];
assign ff_l2d_l2b_decc_out_c7_6_scanin[12]=ff_l2d_l2b_decc_out_c7_2_scanout[12];
assign ff_l2d_l2b_decc_out_c7_4_scanin[12]=ff_l2d_l2b_decc_out_c7_6_scanout[12];
assign ff_l2d_l2b_decc_out_c7_8_scanin[12]=ff_l2d_l2b_decc_out_c7_4_scanout[12];
assign ff_l2d_l2b_decc_out_c7_10_scanin[12]=ff_l2d_l2b_decc_out_c7_8_scanout[12];
assign ff_l2d_l2b_decc_out_c7_14_scanin[12]=ff_l2d_l2b_decc_out_c7_10_scanout[12];
assign ff_l2d_l2b_decc_out_c7_12_scanin[12]=ff_l2d_l2b_decc_out_c7_14_scanout[12];
assign ff_l2d_l2b_decc_out_c7_16_scanin[12]=ff_l2d_l2b_decc_out_c7_12_scanout[12];
assign ff_l2d_l2b_decc_out_c7_2_scanin[13]=ff_l2d_l2b_decc_out_c7_16_scanout[12];
assign ff_l2d_l2b_decc_out_c7_6_scanin[13]=ff_l2d_l2b_decc_out_c7_2_scanout[13];
assign ff_l2d_l2b_decc_out_c7_4_scanin[13]=ff_l2d_l2b_decc_out_c7_6_scanout[13];
assign ff_l2d_l2b_decc_out_c7_8_scanin[13]=ff_l2d_l2b_decc_out_c7_4_scanout[13];
assign ff_l2d_l2b_decc_out_c7_10_scanin[13]=ff_l2d_l2b_decc_out_c7_8_scanout[13];
assign ff_l2d_l2b_decc_out_c7_14_scanin[13]=ff_l2d_l2b_decc_out_c7_10_scanout[13];
assign ff_l2d_l2b_decc_out_c7_12_scanin[13]=ff_l2d_l2b_decc_out_c7_14_scanout[13];
assign ff_l2d_l2b_decc_out_c7_16_scanin[13]=ff_l2d_l2b_decc_out_c7_12_scanout[13];
assign ff_l2d_l2b_decc_out_c7_2_scanin[14]=ff_l2d_l2b_decc_out_c7_16_scanout[13];
assign ff_l2d_l2b_decc_out_c7_6_scanin[14]=ff_l2d_l2b_decc_out_c7_2_scanout[14];
assign ff_l2d_l2b_decc_out_c7_4_scanin[14]=ff_l2d_l2b_decc_out_c7_6_scanout[14];
assign ff_l2d_l2b_decc_out_c7_8_scanin[14]=ff_l2d_l2b_decc_out_c7_4_scanout[14];
assign ff_l2d_l2b_decc_out_c7_10_scanin[14]=ff_l2d_l2b_decc_out_c7_8_scanout[14];
assign ff_l2d_l2b_decc_out_c7_14_scanin[14]=ff_l2d_l2b_decc_out_c7_10_scanout[14];
assign ff_l2d_l2b_decc_out_c7_12_scanin[14]=ff_l2d_l2b_decc_out_c7_14_scanout[14];
assign ff_l2d_l2b_decc_out_c7_16_scanin[14]=ff_l2d_l2b_decc_out_c7_12_scanout[14];
assign ff_l2d_l2b_decc_out_c7_2_scanin[15]=ff_l2d_l2b_decc_out_c7_16_scanout[14];
assign ff_l2d_l2b_decc_out_c7_6_scanin[15]=ff_l2d_l2b_decc_out_c7_2_scanout[15];
assign ff_l2d_l2b_decc_out_c7_4_scanin[15]=ff_l2d_l2b_decc_out_c7_6_scanout[15];
assign ff_l2d_l2b_decc_out_c7_8_scanin[15]=ff_l2d_l2b_decc_out_c7_4_scanout[15];
assign ff_l2d_l2b_decc_out_c7_10_scanin[15]=ff_l2d_l2b_decc_out_c7_8_scanout[15];
assign ff_l2d_l2b_decc_out_c7_14_scanin[15]=ff_l2d_l2b_decc_out_c7_10_scanout[15];
assign ff_l2d_l2b_decc_out_c7_12_scanin[15]=ff_l2d_l2b_decc_out_c7_14_scanout[15];
assign ff_l2d_l2b_decc_out_c7_16_scanin[15]=ff_l2d_l2b_decc_out_c7_12_scanout[15];
assign ff_l2d_l2b_decc_out_c7_2_scanin[16]=ff_l2d_l2b_decc_out_c7_16_scanout[15];
assign ff_l2d_l2b_decc_out_c7_6_scanin[16]=ff_l2d_l2b_decc_out_c7_2_scanout[16];
assign ff_l2d_l2b_decc_out_c7_4_scanin[16]=ff_l2d_l2b_decc_out_c7_6_scanout[16];
assign ff_l2d_l2b_decc_out_c7_8_scanin[16]=ff_l2d_l2b_decc_out_c7_4_scanout[16];
assign ff_l2d_l2b_decc_out_c7_10_scanin[16]=ff_l2d_l2b_decc_out_c7_8_scanout[16];
assign ff_l2d_l2b_decc_out_c7_14_scanin[16]=ff_l2d_l2b_decc_out_c7_10_scanout[16];
assign ff_l2d_l2b_decc_out_c7_12_scanin[16]=ff_l2d_l2b_decc_out_c7_14_scanout[16];
assign ff_l2d_l2b_decc_out_c7_16_scanin[16]=ff_l2d_l2b_decc_out_c7_12_scanout[16];
assign ff_l2d_l2b_decc_out_c7_2_scanin[17]=ff_l2d_l2b_decc_out_c7_16_scanout[16];
assign ff_l2d_l2b_decc_out_c7_6_scanin[17]=ff_l2d_l2b_decc_out_c7_2_scanout[17];
assign ff_l2d_l2b_decc_out_c7_4_scanin[17]=ff_l2d_l2b_decc_out_c7_6_scanout[17];
assign ff_l2d_l2b_decc_out_c7_8_scanin[17]=ff_l2d_l2b_decc_out_c7_4_scanout[17];
assign ff_l2d_l2b_decc_out_c7_10_scanin[17]=ff_l2d_l2b_decc_out_c7_8_scanout[17];
assign ff_l2d_l2b_decc_out_c7_14_scanin[17]=ff_l2d_l2b_decc_out_c7_10_scanout[17];
assign ff_l2d_l2b_decc_out_c7_12_scanin[17]=ff_l2d_l2b_decc_out_c7_14_scanout[17];
assign ff_l2d_l2b_decc_out_c7_16_scanin[17]=ff_l2d_l2b_decc_out_c7_12_scanout[17];
assign ff_l2d_l2b_decc_out_c7_2_scanin[18]=ff_l2d_l2b_decc_out_c7_16_scanout[17];
assign ff_l2d_l2b_decc_out_c7_6_scanin[18]=ff_l2d_l2b_decc_out_c7_2_scanout[18];
assign ff_l2d_l2b_decc_out_c7_4_scanin[18]=ff_l2d_l2b_decc_out_c7_6_scanout[18];
assign ff_l2d_l2b_decc_out_c7_8_scanin[18]=ff_l2d_l2b_decc_out_c7_4_scanout[18];
assign ff_l2d_l2b_decc_out_c7_10_scanin[18]=ff_l2d_l2b_decc_out_c7_8_scanout[18];
assign ff_l2d_l2b_decc_out_c7_14_scanin[18]=ff_l2d_l2b_decc_out_c7_10_scanout[18];
assign ff_l2d_l2b_decc_out_c7_12_scanin[18]=ff_l2d_l2b_decc_out_c7_14_scanout[18];
assign ff_l2d_l2b_decc_out_c7_16_scanin[18]=ff_l2d_l2b_decc_out_c7_12_scanout[18];
assign ff_l2d_l2b_decc_out_c7_2_scanin[19]=ff_l2d_l2b_decc_out_c7_16_scanout[18];
assign ff_l2d_l2b_decc_out_c7_6_scanin[19]=ff_l2d_l2b_decc_out_c7_2_scanout[19];
assign ff_l2d_l2b_decc_out_c7_4_scanin[19]=ff_l2d_l2b_decc_out_c7_6_scanout[19];
assign ff_l2d_l2b_decc_out_c7_8_scanin[19]=ff_l2d_l2b_decc_out_c7_4_scanout[19];
assign ff_l2d_l2b_decc_out_c7_10_scanin[19]=ff_l2d_l2b_decc_out_c7_8_scanout[19];
assign ff_l2d_l2b_decc_out_c7_14_scanin[19]=ff_l2d_l2b_decc_out_c7_10_scanout[19];
assign ff_l2d_l2b_decc_out_c7_12_scanin[19]=ff_l2d_l2b_decc_out_c7_14_scanout[19];
assign ff_l2d_l2b_decc_out_c7_16_scanin[19]=ff_l2d_l2b_decc_out_c7_12_scanout[19];
assign ff_l2d_l2b_decc_out_c7_2_scanin[20]=ff_l2d_l2b_decc_out_c7_16_scanout[19];
assign ff_l2d_l2b_decc_out_c7_6_scanin[20]=ff_l2d_l2b_decc_out_c7_2_scanout[20];
assign ff_l2d_l2b_decc_out_c7_4_scanin[20]=ff_l2d_l2b_decc_out_c7_6_scanout[20];
assign ff_l2d_l2b_decc_out_c7_8_scanin[20]=ff_l2d_l2b_decc_out_c7_4_scanout[20];
assign ff_l2d_l2b_decc_out_c7_10_scanin[20]=ff_l2d_l2b_decc_out_c7_8_scanout[20];
assign ff_l2d_l2b_decc_out_c7_14_scanin[20]=ff_l2d_l2b_decc_out_c7_10_scanout[20];
assign ff_l2d_l2b_decc_out_c7_12_scanin[20]=ff_l2d_l2b_decc_out_c7_14_scanout[20];
assign ff_l2d_l2b_decc_out_c7_16_scanin[20]=ff_l2d_l2b_decc_out_c7_12_scanout[20];
assign ff_l2d_l2b_decc_out_c7_2_scanin[21]=ff_l2d_l2b_decc_out_c7_16_scanout[20];
assign ff_l2d_l2b_decc_out_c7_6_scanin[21]=ff_l2d_l2b_decc_out_c7_2_scanout[21];
assign ff_l2d_l2b_decc_out_c7_4_scanin[21]=ff_l2d_l2b_decc_out_c7_6_scanout[21];
assign ff_l2d_l2b_decc_out_c7_8_scanin[21]=ff_l2d_l2b_decc_out_c7_4_scanout[21];
assign ff_l2d_l2b_decc_out_c7_10_scanin[21]=ff_l2d_l2b_decc_out_c7_8_scanout[21];
assign ff_l2d_l2b_decc_out_c7_14_scanin[21]=ff_l2d_l2b_decc_out_c7_10_scanout[21];
assign ff_l2d_l2b_decc_out_c7_12_scanin[21]=ff_l2d_l2b_decc_out_c7_14_scanout[21];
assign ff_l2d_l2b_decc_out_c7_16_scanin[21]=ff_l2d_l2b_decc_out_c7_12_scanout[21];
assign ff_l2d_l2b_decc_out_c7_2_scanin[22]=ff_l2d_l2b_decc_out_c7_16_scanout[21];
assign ff_l2d_l2b_decc_out_c7_6_scanin[22]=ff_l2d_l2b_decc_out_c7_2_scanout[22];
assign ff_l2d_l2b_decc_out_c7_4_scanin[22]=ff_l2d_l2b_decc_out_c7_6_scanout[22];
assign ff_l2d_l2b_decc_out_c7_8_scanin[22]=ff_l2d_l2b_decc_out_c7_4_scanout[22];
assign ff_l2d_l2b_decc_out_c7_10_scanin[22]=ff_l2d_l2b_decc_out_c7_8_scanout[22];
assign ff_l2d_l2b_decc_out_c7_14_scanin[22]=ff_l2d_l2b_decc_out_c7_10_scanout[22];
assign ff_l2d_l2b_decc_out_c7_12_scanin[22]=ff_l2d_l2b_decc_out_c7_14_scanout[22];
assign ff_l2d_l2b_decc_out_c7_16_scanin[22]=ff_l2d_l2b_decc_out_c7_12_scanout[22];
assign ff_l2d_l2b_decc_out_c7_2_scanin[23]=ff_l2d_l2b_decc_out_c7_16_scanout[22];
assign ff_l2d_l2b_decc_out_c7_6_scanin[23]=ff_l2d_l2b_decc_out_c7_2_scanout[23];
assign ff_l2d_l2b_decc_out_c7_4_scanin[23]=ff_l2d_l2b_decc_out_c7_6_scanout[23];
assign ff_l2d_l2b_decc_out_c7_8_scanin[23]=ff_l2d_l2b_decc_out_c7_4_scanout[23];
assign ff_l2d_l2b_decc_out_c7_10_scanin[23]=ff_l2d_l2b_decc_out_c7_8_scanout[23];
assign ff_l2d_l2b_decc_out_c7_14_scanin[23]=ff_l2d_l2b_decc_out_c7_10_scanout[23];
assign ff_l2d_l2b_decc_out_c7_12_scanin[23]=ff_l2d_l2b_decc_out_c7_14_scanout[23];
assign ff_l2d_l2b_decc_out_c7_16_scanin[23]=ff_l2d_l2b_decc_out_c7_12_scanout[23];
assign ff_l2d_l2b_decc_out_c7_2_scanin[24]=ff_l2d_l2b_decc_out_c7_16_scanout[23];
assign ff_l2d_l2b_decc_out_c7_6_scanin[24]=ff_l2d_l2b_decc_out_c7_2_scanout[24];
assign ff_l2d_l2b_decc_out_c7_4_scanin[24]=ff_l2d_l2b_decc_out_c7_6_scanout[24];
assign ff_l2d_l2b_decc_out_c7_8_scanin[24]=ff_l2d_l2b_decc_out_c7_4_scanout[24];
assign ff_l2d_l2b_decc_out_c7_10_scanin[24]=ff_l2d_l2b_decc_out_c7_8_scanout[24];
assign ff_l2d_l2b_decc_out_c7_14_scanin[24]=ff_l2d_l2b_decc_out_c7_10_scanout[24];
assign ff_l2d_l2b_decc_out_c7_12_scanin[24]=ff_l2d_l2b_decc_out_c7_14_scanout[24];
assign ff_l2d_l2b_decc_out_c7_16_scanin[24]=ff_l2d_l2b_decc_out_c7_12_scanout[24];
assign ff_l2d_l2b_decc_out_c7_2_scanin[25]=ff_l2d_l2b_decc_out_c7_16_scanout[24];
assign ff_l2d_l2b_decc_out_c7_6_scanin[25]=ff_l2d_l2b_decc_out_c7_2_scanout[25];
assign ff_l2d_l2b_decc_out_c7_4_scanin[25]=ff_l2d_l2b_decc_out_c7_6_scanout[25];
assign ff_l2d_l2b_decc_out_c7_8_scanin[25]=ff_l2d_l2b_decc_out_c7_4_scanout[25];
assign ff_l2d_l2b_decc_out_c7_10_scanin[25]=ff_l2d_l2b_decc_out_c7_8_scanout[25];
assign ff_l2d_l2b_decc_out_c7_14_scanin[25]=ff_l2d_l2b_decc_out_c7_10_scanout[25];
assign ff_l2d_l2b_decc_out_c7_12_scanin[25]=ff_l2d_l2b_decc_out_c7_14_scanout[25];
assign ff_l2d_l2b_decc_out_c7_16_scanin[25]=ff_l2d_l2b_decc_out_c7_12_scanout[25];
assign ff_l2d_l2b_decc_out_c7_2_scanin[26]=ff_l2d_l2b_decc_out_c7_16_scanout[25];
assign ff_l2d_l2b_decc_out_c7_6_scanin[26]=ff_l2d_l2b_decc_out_c7_2_scanout[26];
assign ff_l2d_l2b_decc_out_c7_4_scanin[26]=ff_l2d_l2b_decc_out_c7_6_scanout[26];
assign ff_l2d_l2b_decc_out_c7_8_scanin[26]=ff_l2d_l2b_decc_out_c7_4_scanout[26];
assign ff_l2d_l2b_decc_out_c7_10_scanin[26]=ff_l2d_l2b_decc_out_c7_8_scanout[26];
assign ff_l2d_l2b_decc_out_c7_14_scanin[26]=ff_l2d_l2b_decc_out_c7_10_scanout[26];
assign ff_l2d_l2b_decc_out_c7_12_scanin[26]=ff_l2d_l2b_decc_out_c7_14_scanout[26];
assign ff_l2d_l2b_decc_out_c7_16_scanin[26]=ff_l2d_l2b_decc_out_c7_12_scanout[26];
assign ff_l2d_l2b_decc_out_c7_2_scanin[27]=ff_l2d_l2b_decc_out_c7_16_scanout[26];
assign ff_l2d_l2b_decc_out_c7_6_scanin[27]=ff_l2d_l2b_decc_out_c7_2_scanout[27];
assign ff_l2d_l2b_decc_out_c7_4_scanin[27]=ff_l2d_l2b_decc_out_c7_6_scanout[27];
assign ff_l2d_l2b_decc_out_c7_8_scanin[27]=ff_l2d_l2b_decc_out_c7_4_scanout[27];
assign ff_l2d_l2b_decc_out_c7_10_scanin[27]=ff_l2d_l2b_decc_out_c7_8_scanout[27];
assign ff_l2d_l2b_decc_out_c7_14_scanin[27]=ff_l2d_l2b_decc_out_c7_10_scanout[27];
assign ff_l2d_l2b_decc_out_c7_12_scanin[27]=ff_l2d_l2b_decc_out_c7_14_scanout[27];
assign ff_l2d_l2b_decc_out_c7_16_scanin[27]=ff_l2d_l2b_decc_out_c7_12_scanout[27];
assign ff_l2d_l2b_decc_out_c7_2_scanin[28]=ff_l2d_l2b_decc_out_c7_16_scanout[27];
assign ff_l2d_l2b_decc_out_c7_6_scanin[28]=ff_l2d_l2b_decc_out_c7_2_scanout[28];
assign ff_l2d_l2b_decc_out_c7_4_scanin[28]=ff_l2d_l2b_decc_out_c7_6_scanout[28];
assign ff_l2d_l2b_decc_out_c7_8_scanin[28]=ff_l2d_l2b_decc_out_c7_4_scanout[28];
assign ff_l2d_l2b_decc_out_c7_10_scanin[28]=ff_l2d_l2b_decc_out_c7_8_scanout[28];
assign ff_l2d_l2b_decc_out_c7_14_scanin[28]=ff_l2d_l2b_decc_out_c7_10_scanout[28];
assign ff_l2d_l2b_decc_out_c7_12_scanin[28]=ff_l2d_l2b_decc_out_c7_14_scanout[28];
assign ff_l2d_l2b_decc_out_c7_16_scanin[28]=ff_l2d_l2b_decc_out_c7_12_scanout[28];
assign ff_l2d_l2b_decc_out_c7_2_scanin[29]=ff_l2d_l2b_decc_out_c7_16_scanout[28];
assign ff_l2d_l2b_decc_out_c7_6_scanin[29]=ff_l2d_l2b_decc_out_c7_2_scanout[29];
assign ff_l2d_l2b_decc_out_c7_4_scanin[29]=ff_l2d_l2b_decc_out_c7_6_scanout[29];
assign ff_l2d_l2b_decc_out_c7_8_scanin[29]=ff_l2d_l2b_decc_out_c7_4_scanout[29];
assign ff_l2d_l2b_decc_out_c7_10_scanin[29]=ff_l2d_l2b_decc_out_c7_8_scanout[29];
assign ff_l2d_l2b_decc_out_c7_14_scanin[29]=ff_l2d_l2b_decc_out_c7_10_scanout[29];
assign ff_l2d_l2b_decc_out_c7_12_scanin[29]=ff_l2d_l2b_decc_out_c7_14_scanout[29];
assign ff_l2d_l2b_decc_out_c7_16_scanin[29]=ff_l2d_l2b_decc_out_c7_12_scanout[29];
assign ff_l2d_l2b_decc_out_c7_2_scanin[30]=ff_l2d_l2b_decc_out_c7_16_scanout[29];
assign ff_l2d_l2b_decc_out_c7_6_scanin[30]=ff_l2d_l2b_decc_out_c7_2_scanout[30];
assign ff_l2d_l2b_decc_out_c7_4_scanin[30]=ff_l2d_l2b_decc_out_c7_6_scanout[30];
assign ff_l2d_l2b_decc_out_c7_8_scanin[30]=ff_l2d_l2b_decc_out_c7_4_scanout[30];
assign ff_l2d_l2b_decc_out_c7_10_scanin[30]=ff_l2d_l2b_decc_out_c7_8_scanout[30];
assign ff_l2d_l2b_decc_out_c7_14_scanin[30]=ff_l2d_l2b_decc_out_c7_10_scanout[30];
assign ff_l2d_l2b_decc_out_c7_12_scanin[30]=ff_l2d_l2b_decc_out_c7_14_scanout[30];
assign ff_l2d_l2b_decc_out_c7_16_scanin[30]=ff_l2d_l2b_decc_out_c7_12_scanout[30];
assign ff_l2d_l2b_decc_out_c7_2_scanin[31]=ff_l2d_l2b_decc_out_c7_16_scanout[30];
assign ff_l2d_l2b_decc_out_c7_6_scanin[31]=ff_l2d_l2b_decc_out_c7_2_scanout[31];
assign ff_l2d_l2b_decc_out_c7_4_scanin[31]=ff_l2d_l2b_decc_out_c7_6_scanout[31];
assign ff_l2d_l2b_decc_out_c7_8_scanin[31]=ff_l2d_l2b_decc_out_c7_4_scanout[31];
assign ff_l2d_l2b_decc_out_c7_10_scanin[31]=ff_l2d_l2b_decc_out_c7_8_scanout[31];
assign ff_l2d_l2b_decc_out_c7_14_scanin[31]=ff_l2d_l2b_decc_out_c7_10_scanout[31];
assign ff_l2d_l2b_decc_out_c7_12_scanin[31]=ff_l2d_l2b_decc_out_c7_14_scanout[31];
assign ff_l2d_l2b_decc_out_c7_16_scanin[31]=ff_l2d_l2b_decc_out_c7_12_scanout[31];
assign ff_l2d_l2b_decc_out_c7_2_scanin[32]=ff_l2d_l2b_decc_out_c7_16_scanout[31];
assign ff_l2d_l2b_decc_out_c7_6_scanin[32]=ff_l2d_l2b_decc_out_c7_2_scanout[32];
assign ff_l2d_l2b_decc_out_c7_4_scanin[32]=ff_l2d_l2b_decc_out_c7_6_scanout[32];
assign ff_l2d_l2b_decc_out_c7_8_scanin[32]=ff_l2d_l2b_decc_out_c7_4_scanout[32];
assign ff_l2d_l2b_decc_out_c7_10_scanin[32]=ff_l2d_l2b_decc_out_c7_8_scanout[32];
assign ff_l2d_l2b_decc_out_c7_14_scanin[32]=ff_l2d_l2b_decc_out_c7_10_scanout[32];
assign ff_l2d_l2b_decc_out_c7_12_scanin[32]=ff_l2d_l2b_decc_out_c7_14_scanout[32];
assign ff_l2d_l2b_decc_out_c7_16_scanin[32]=ff_l2d_l2b_decc_out_c7_12_scanout[32];
assign ff_l2d_l2b_decc_out_c7_2_scanin[33]=ff_l2d_l2b_decc_out_c7_16_scanout[32];
assign ff_l2d_l2b_decc_out_c7_6_scanin[33]=ff_l2d_l2b_decc_out_c7_2_scanout[33];
assign ff_l2d_l2b_decc_out_c7_4_scanin[33]=ff_l2d_l2b_decc_out_c7_6_scanout[33];
assign ff_l2d_l2b_decc_out_c7_8_scanin[33]=ff_l2d_l2b_decc_out_c7_4_scanout[33];
assign ff_l2d_l2b_decc_out_c7_10_scanin[33]=ff_l2d_l2b_decc_out_c7_8_scanout[33];
assign ff_l2d_l2b_decc_out_c7_14_scanin[33]=ff_l2d_l2b_decc_out_c7_10_scanout[33];
assign ff_l2d_l2b_decc_out_c7_12_scanin[33]=ff_l2d_l2b_decc_out_c7_14_scanout[33];
assign ff_l2d_l2b_decc_out_c7_16_scanin[33]=ff_l2d_l2b_decc_out_c7_12_scanout[33];
assign ff_l2d_l2b_decc_out_c7_2_scanin[34]=ff_l2d_l2b_decc_out_c7_16_scanout[33];
assign ff_l2d_l2b_decc_out_c7_6_scanin[34]=ff_l2d_l2b_decc_out_c7_2_scanout[34];
assign ff_l2d_l2b_decc_out_c7_4_scanin[34]=ff_l2d_l2b_decc_out_c7_6_scanout[34];
assign ff_l2d_l2b_decc_out_c7_8_scanin[34]=ff_l2d_l2b_decc_out_c7_4_scanout[34];
assign ff_l2d_l2b_decc_out_c7_10_scanin[34]=ff_l2d_l2b_decc_out_c7_8_scanout[34];
assign ff_l2d_l2b_decc_out_c7_14_scanin[34]=ff_l2d_l2b_decc_out_c7_10_scanout[34];
assign ff_l2d_l2b_decc_out_c7_12_scanin[34]=ff_l2d_l2b_decc_out_c7_14_scanout[34];
assign ff_l2d_l2b_decc_out_c7_16_scanin[34]=ff_l2d_l2b_decc_out_c7_12_scanout[34];
assign ff_l2d_l2b_decc_out_c7_2_scanin[35]=ff_l2d_l2b_decc_out_c7_16_scanout[34];
assign ff_l2d_l2b_decc_out_c7_6_scanin[35]=ff_l2d_l2b_decc_out_c7_2_scanout[35];
assign ff_l2d_l2b_decc_out_c7_4_scanin[35]=ff_l2d_l2b_decc_out_c7_6_scanout[35];
assign ff_l2d_l2b_decc_out_c7_8_scanin[35]=ff_l2d_l2b_decc_out_c7_4_scanout[35];
assign ff_l2d_l2b_decc_out_c7_10_scanin[35]=ff_l2d_l2b_decc_out_c7_8_scanout[35];
assign ff_l2d_l2b_decc_out_c7_14_scanin[35]=ff_l2d_l2b_decc_out_c7_10_scanout[35];
assign ff_l2d_l2b_decc_out_c7_12_scanin[35]=ff_l2d_l2b_decc_out_c7_14_scanout[35];
assign ff_l2d_l2b_decc_out_c7_16_scanin[35]=ff_l2d_l2b_decc_out_c7_12_scanout[35];
assign ff_l2d_l2b_decc_out_c7_2_scanin[36]=ff_l2d_l2b_decc_out_c7_16_scanout[35];
assign ff_l2d_l2b_decc_out_c7_6_scanin[36]=ff_l2d_l2b_decc_out_c7_2_scanout[36];
assign ff_l2d_l2b_decc_out_c7_4_scanin[36]=ff_l2d_l2b_decc_out_c7_6_scanout[36];
assign ff_l2d_l2b_decc_out_c7_8_scanin[36]=ff_l2d_l2b_decc_out_c7_4_scanout[36];
assign ff_l2d_l2b_decc_out_c7_10_scanin[36]=ff_l2d_l2b_decc_out_c7_8_scanout[36];
assign ff_l2d_l2b_decc_out_c7_14_scanin[36]=ff_l2d_l2b_decc_out_c7_10_scanout[36];
assign ff_l2d_l2b_decc_out_c7_12_scanin[36]=ff_l2d_l2b_decc_out_c7_14_scanout[36];
assign ff_l2d_l2b_decc_out_c7_16_scanin[36]=ff_l2d_l2b_decc_out_c7_12_scanout[36];
assign ff_l2d_l2b_decc_out_c7_2_scanin[37]=ff_l2d_l2b_decc_out_c7_16_scanout[36];
assign ff_l2d_l2b_decc_out_c7_6_scanin[37]=ff_l2d_l2b_decc_out_c7_2_scanout[37];
assign ff_l2d_l2b_decc_out_c7_4_scanin[37]=ff_l2d_l2b_decc_out_c7_6_scanout[37];
assign ff_l2d_l2b_decc_out_c7_8_scanin[37]=ff_l2d_l2b_decc_out_c7_4_scanout[37];
assign ff_l2d_l2b_decc_out_c7_10_scanin[37]=ff_l2d_l2b_decc_out_c7_8_scanout[37];
assign ff_l2d_l2b_decc_out_c7_14_scanin[37]=ff_l2d_l2b_decc_out_c7_10_scanout[37];
assign ff_l2d_l2b_decc_out_c7_12_scanin[37]=ff_l2d_l2b_decc_out_c7_14_scanout[37];
assign ff_l2d_l2b_decc_out_c7_16_scanin[37]=ff_l2d_l2b_decc_out_c7_12_scanout[37];
assign ff_l2d_l2b_decc_out_c7_2_scanin[38]=ff_l2d_l2b_decc_out_c7_16_scanout[37];
assign ff_l2d_l2b_decc_out_c7_6_scanin[38]=ff_l2d_l2b_decc_out_c7_2_scanout[38];
assign ff_l2d_l2b_decc_out_c7_4_scanin[38]=ff_l2d_l2b_decc_out_c7_6_scanout[38];
assign ff_l2d_l2b_decc_out_c7_8_scanin[38]=ff_l2d_l2b_decc_out_c7_4_scanout[38];
assign ff_l2d_l2b_decc_out_c7_10_scanin[38]=ff_l2d_l2b_decc_out_c7_8_scanout[38];
assign ff_l2d_l2b_decc_out_c7_14_scanin[38]=ff_l2d_l2b_decc_out_c7_10_scanout[38];
assign ff_l2d_l2b_decc_out_c7_12_scanin[38]=ff_l2d_l2b_decc_out_c7_14_scanout[38];
assign ff_l2d_l2b_decc_out_c7_16_scanin[38]=ff_l2d_l2b_decc_out_c7_12_scanout[38];
assign ff_l2d_l2t_decc_c6_scanin[0]=ff_l2d_l2b_decc_out_c7_16_scanout[38];
assign ff_l2d_l2t_decc_c6_scanin[78]=ff_l2d_l2t_decc_c6_scanout[0];
assign ff_l2d_l2t_decc_c6_scanin[1]=ff_l2d_l2t_decc_c6_scanout[78];
assign ff_l2d_l2t_decc_c6_scanin[79]=ff_l2d_l2t_decc_c6_scanout[1];
assign ff_l2d_l2t_decc_c6_scanin[2]=ff_l2d_l2t_decc_c6_scanout[79];
assign ff_l2d_l2t_decc_c6_scanin[80]=ff_l2d_l2t_decc_c6_scanout[2];
assign ff_l2d_l2t_decc_c6_scanin[3]=ff_l2d_l2t_decc_c6_scanout[80];
assign ff_l2d_l2t_decc_c6_scanin[81]=ff_l2d_l2t_decc_c6_scanout[3];
assign ff_l2d_l2t_decc_c6_scanin[4]=ff_l2d_l2t_decc_c6_scanout[81];
assign ff_l2d_l2t_decc_c6_scanin[82]=ff_l2d_l2t_decc_c6_scanout[4];
assign ff_l2d_l2t_decc_c6_scanin[5]=ff_l2d_l2t_decc_c6_scanout[82];
assign ff_l2d_l2t_decc_c6_scanin[83]=ff_l2d_l2t_decc_c6_scanout[5];
assign ff_l2d_l2t_decc_c6_scanin[6]=ff_l2d_l2t_decc_c6_scanout[83];
assign ff_l2d_l2t_decc_c6_scanin[84]=ff_l2d_l2t_decc_c6_scanout[6];
assign ff_l2d_l2t_decc_c6_scanin[7]=ff_l2d_l2t_decc_c6_scanout[84];
assign ff_l2d_l2t_decc_c6_scanin[85]=ff_l2d_l2t_decc_c6_scanout[7];
assign ff_l2d_l2t_decc_c6_scanin[8]=ff_l2d_l2t_decc_c6_scanout[85];
assign ff_l2d_l2t_decc_c6_scanin[86]=ff_l2d_l2t_decc_c6_scanout[8];
assign ff_l2d_l2t_decc_c6_scanin[9]=ff_l2d_l2t_decc_c6_scanout[86];
assign ff_l2d_l2t_decc_c6_scanin[87]=ff_l2d_l2t_decc_c6_scanout[9];
assign ff_l2d_l2t_decc_c6_scanin[10]=ff_l2d_l2t_decc_c6_scanout[87];
assign ff_l2d_l2t_decc_c6_scanin[88]=ff_l2d_l2t_decc_c6_scanout[10];
assign ff_l2d_l2t_decc_c6_scanin[11]=ff_l2d_l2t_decc_c6_scanout[88];
assign ff_l2d_l2t_decc_c6_scanin[89]=ff_l2d_l2t_decc_c6_scanout[11];
assign ff_l2d_l2t_decc_c6_scanin[12]=ff_l2d_l2t_decc_c6_scanout[89];
assign ff_l2d_l2t_decc_c6_scanin[90]=ff_l2d_l2t_decc_c6_scanout[12];
assign ff_l2d_l2t_decc_c6_scanin[13]=ff_l2d_l2t_decc_c6_scanout[90];
assign ff_l2d_l2t_decc_c6_scanin[91]=ff_l2d_l2t_decc_c6_scanout[13];
assign ff_l2d_l2t_decc_c6_scanin[14]=ff_l2d_l2t_decc_c6_scanout[91];
assign ff_l2d_l2t_decc_c6_scanin[92]=ff_l2d_l2t_decc_c6_scanout[14];
assign ff_l2d_l2t_decc_c6_scanin[15]=ff_l2d_l2t_decc_c6_scanout[92];
assign ff_l2d_l2t_decc_c6_scanin[93]=ff_l2d_l2t_decc_c6_scanout[15];
assign ff_l2d_l2t_decc_c6_scanin[16]=ff_l2d_l2t_decc_c6_scanout[93];
assign ff_l2d_l2t_decc_c6_scanin[94]=ff_l2d_l2t_decc_c6_scanout[16];
assign ff_l2d_l2t_decc_c6_scanin[17]=ff_l2d_l2t_decc_c6_scanout[94];
assign ff_l2d_l2t_decc_c6_scanin[95]=ff_l2d_l2t_decc_c6_scanout[17];
assign ff_l2d_l2t_decc_c6_scanin[18]=ff_l2d_l2t_decc_c6_scanout[95];
assign ff_l2d_l2t_decc_c6_scanin[96]=ff_l2d_l2t_decc_c6_scanout[18];
assign ff_l2d_l2t_decc_c6_scanin[19]=ff_l2d_l2t_decc_c6_scanout[96];
assign ff_l2d_l2t_decc_c6_scanin[97]=ff_l2d_l2t_decc_c6_scanout[19];
assign ff_l2d_l2t_decc_c6_scanin[20]=ff_l2d_l2t_decc_c6_scanout[97];
assign ff_l2d_l2t_decc_c6_scanin[98]=ff_l2d_l2t_decc_c6_scanout[20];
assign ff_l2d_l2t_decc_c6_scanin[21]=ff_l2d_l2t_decc_c6_scanout[98];
assign ff_l2d_l2t_decc_c6_scanin[99]=ff_l2d_l2t_decc_c6_scanout[21];
assign ff_l2d_l2t_decc_c6_scanin[22]=ff_l2d_l2t_decc_c6_scanout[99];
assign ff_l2d_l2t_decc_c6_scanin[100]=ff_l2d_l2t_decc_c6_scanout[22];
assign ff_l2d_l2t_decc_c6_scanin[23]=ff_l2d_l2t_decc_c6_scanout[100];
assign ff_l2d_l2t_decc_c6_scanin[101]=ff_l2d_l2t_decc_c6_scanout[23];
assign ff_l2d_l2t_decc_c6_scanin[24]=ff_l2d_l2t_decc_c6_scanout[101];
assign ff_l2d_l2t_decc_c6_scanin[102]=ff_l2d_l2t_decc_c6_scanout[24];
assign ff_l2d_l2t_decc_c6_scanin[25]=ff_l2d_l2t_decc_c6_scanout[102];
assign ff_l2d_l2t_decc_c6_scanin[103]=ff_l2d_l2t_decc_c6_scanout[25];
assign ff_l2d_l2t_decc_c6_scanin[26]=ff_l2d_l2t_decc_c6_scanout[103];
assign ff_l2d_l2t_decc_c6_scanin[104]=ff_l2d_l2t_decc_c6_scanout[26];
assign ff_l2d_l2t_decc_c6_scanin[27]=ff_l2d_l2t_decc_c6_scanout[104];
assign ff_l2d_l2t_decc_c6_scanin[105]=ff_l2d_l2t_decc_c6_scanout[27];
assign ff_l2d_l2t_decc_c6_scanin[28]=ff_l2d_l2t_decc_c6_scanout[105];
assign ff_l2d_l2t_decc_c6_scanin[106]=ff_l2d_l2t_decc_c6_scanout[28];
assign ff_l2d_l2t_decc_c6_scanin[29]=ff_l2d_l2t_decc_c6_scanout[106];
assign ff_l2d_l2t_decc_c6_scanin[107]=ff_l2d_l2t_decc_c6_scanout[29];
assign ff_l2d_l2t_decc_c6_scanin[30]=ff_l2d_l2t_decc_c6_scanout[107];
assign ff_l2d_l2t_decc_c6_scanin[108]=ff_l2d_l2t_decc_c6_scanout[30];
assign ff_l2d_l2t_decc_c6_scanin[31]=ff_l2d_l2t_decc_c6_scanout[108];
assign ff_l2d_l2t_decc_c6_scanin[109]=ff_l2d_l2t_decc_c6_scanout[31];
assign ff_l2d_l2t_decc_c6_scanin[32]=ff_l2d_l2t_decc_c6_scanout[109];
assign ff_l2d_l2t_decc_c6_scanin[110]=ff_l2d_l2t_decc_c6_scanout[32];
assign ff_l2d_l2t_decc_c6_scanin[33]=ff_l2d_l2t_decc_c6_scanout[110];
assign ff_l2d_l2t_decc_c6_scanin[111]=ff_l2d_l2t_decc_c6_scanout[33];
assign ff_l2d_l2t_decc_c6_scanin[34]=ff_l2d_l2t_decc_c6_scanout[111];
assign ff_l2d_l2t_decc_c6_scanin[112]=ff_l2d_l2t_decc_c6_scanout[34];
assign ff_l2d_l2t_decc_c6_scanin[35]=ff_l2d_l2t_decc_c6_scanout[112];
assign ff_l2d_l2t_decc_c6_scanin[113]=ff_l2d_l2t_decc_c6_scanout[35];
assign ff_l2d_l2t_decc_c6_scanin[36]=ff_l2d_l2t_decc_c6_scanout[113];
assign ff_l2d_l2t_decc_c6_scanin[114]=ff_l2d_l2t_decc_c6_scanout[36];
assign ff_l2d_l2t_decc_c6_scanin[37]=ff_l2d_l2t_decc_c6_scanout[114];
assign ff_l2d_l2t_decc_c6_scanin[115]=ff_l2d_l2t_decc_c6_scanout[37];
assign ff_l2d_l2t_decc_c6_scanin[38]=ff_l2d_l2t_decc_c6_scanout[115];
assign ff_l2d_l2t_decc_c6_scanin[116]=ff_l2d_l2t_decc_c6_scanout[38];
assign ff_l2d_l2t_decc_c6_scanin[39]=ff_l2d_l2t_decc_c6_scanout[116];
assign ff_l2d_l2t_decc_c6_scanin[117]=ff_l2d_l2t_decc_c6_scanout[39];
assign ff_l2d_l2t_decc_c6_scanin[40]=ff_l2d_l2t_decc_c6_scanout[117];
assign ff_l2d_l2t_decc_c6_scanin[118]=ff_l2d_l2t_decc_c6_scanout[40];
assign ff_l2d_l2t_decc_c6_scanin[41]=ff_l2d_l2t_decc_c6_scanout[118];
assign ff_l2d_l2t_decc_c6_scanin[119]=ff_l2d_l2t_decc_c6_scanout[41];
assign ff_l2d_l2t_decc_c6_scanin[42]=ff_l2d_l2t_decc_c6_scanout[119];
assign ff_l2d_l2t_decc_c6_scanin[120]=ff_l2d_l2t_decc_c6_scanout[42];
assign ff_l2d_l2t_decc_c6_scanin[43]=ff_l2d_l2t_decc_c6_scanout[120];
assign ff_l2d_l2t_decc_c6_scanin[121]=ff_l2d_l2t_decc_c6_scanout[43];
assign ff_l2d_l2t_decc_c6_scanin[44]=ff_l2d_l2t_decc_c6_scanout[121];
assign ff_l2d_l2t_decc_c6_scanin[122]=ff_l2d_l2t_decc_c6_scanout[44];
assign ff_l2d_l2t_decc_c6_scanin[45]=ff_l2d_l2t_decc_c6_scanout[122];
assign ff_l2d_l2t_decc_c6_scanin[123]=ff_l2d_l2t_decc_c6_scanout[45];
assign ff_l2d_l2t_decc_c6_scanin[46]=ff_l2d_l2t_decc_c6_scanout[123];
assign ff_l2d_l2t_decc_c6_scanin[124]=ff_l2d_l2t_decc_c6_scanout[46];
assign ff_l2d_l2t_decc_c6_scanin[47]=ff_l2d_l2t_decc_c6_scanout[124];
assign ff_l2d_l2t_decc_c6_scanin[125]=ff_l2d_l2t_decc_c6_scanout[47];
assign ff_l2d_l2t_decc_c6_scanin[48]=ff_l2d_l2t_decc_c6_scanout[125];
assign ff_l2d_l2t_decc_c6_scanin[126]=ff_l2d_l2t_decc_c6_scanout[48];
assign ff_l2d_l2t_decc_c6_scanin[49]=ff_l2d_l2t_decc_c6_scanout[126];
assign ff_l2d_l2t_decc_c6_scanin[127]=ff_l2d_l2t_decc_c6_scanout[49];
assign ff_l2d_l2t_decc_c6_scanin[50]=ff_l2d_l2t_decc_c6_scanout[127];
assign ff_l2d_l2t_decc_c6_scanin[128]=ff_l2d_l2t_decc_c6_scanout[50];
assign ff_l2d_l2t_decc_c6_scanin[51]=ff_l2d_l2t_decc_c6_scanout[128];
assign ff_l2d_l2t_decc_c6_scanin[129]=ff_l2d_l2t_decc_c6_scanout[51];
assign ff_l2d_l2t_decc_c6_scanin[52]=ff_l2d_l2t_decc_c6_scanout[129];
assign ff_l2d_l2t_decc_c6_scanin[130]=ff_l2d_l2t_decc_c6_scanout[52];
assign ff_l2d_l2t_decc_c6_scanin[53]=ff_l2d_l2t_decc_c6_scanout[130];
assign ff_l2d_l2t_decc_c6_scanin[131]=ff_l2d_l2t_decc_c6_scanout[53];
assign ff_l2d_l2t_decc_c6_scanin[54]=ff_l2d_l2t_decc_c6_scanout[131];
assign ff_l2d_l2t_decc_c6_scanin[132]=ff_l2d_l2t_decc_c6_scanout[54];
assign ff_l2d_l2t_decc_c6_scanin[55]=ff_l2d_l2t_decc_c6_scanout[132];
assign ff_l2d_l2t_decc_c6_scanin[133]=ff_l2d_l2t_decc_c6_scanout[55];
assign ff_l2d_l2t_decc_c6_scanin[56]=ff_l2d_l2t_decc_c6_scanout[133];
assign ff_l2d_l2t_decc_c6_scanin[134]=ff_l2d_l2t_decc_c6_scanout[56];
assign ff_l2d_l2t_decc_c6_scanin[57]=ff_l2d_l2t_decc_c6_scanout[134];
assign ff_l2d_l2t_decc_c6_scanin[135]=ff_l2d_l2t_decc_c6_scanout[57];
assign ff_l2d_l2t_decc_c6_scanin[58]=ff_l2d_l2t_decc_c6_scanout[135];
assign ff_l2d_l2t_decc_c6_scanin[136]=ff_l2d_l2t_decc_c6_scanout[58];
assign ff_l2d_l2t_decc_c6_scanin[59]=ff_l2d_l2t_decc_c6_scanout[136];
assign ff_l2d_l2t_decc_c6_scanin[137]=ff_l2d_l2t_decc_c6_scanout[59];
assign ff_l2d_l2t_decc_c6_scanin[60]=ff_l2d_l2t_decc_c6_scanout[137];
assign ff_l2d_l2t_decc_c6_scanin[138]=ff_l2d_l2t_decc_c6_scanout[60];
assign ff_l2d_l2t_decc_c6_scanin[61]=ff_l2d_l2t_decc_c6_scanout[138];
assign ff_l2d_l2t_decc_c6_scanin[139]=ff_l2d_l2t_decc_c6_scanout[61];
assign ff_l2d_l2t_decc_c6_scanin[62]=ff_l2d_l2t_decc_c6_scanout[139];
assign ff_l2d_l2t_decc_c6_scanin[140]=ff_l2d_l2t_decc_c6_scanout[62];
assign ff_l2d_l2t_decc_c6_scanin[63]=ff_l2d_l2t_decc_c6_scanout[140];
assign ff_l2d_l2t_decc_c6_scanin[141]=ff_l2d_l2t_decc_c6_scanout[63];
assign ff_l2d_l2t_decc_c6_scanin[64]=ff_l2d_l2t_decc_c6_scanout[141];
assign ff_l2d_l2t_decc_c6_scanin[142]=ff_l2d_l2t_decc_c6_scanout[64];
assign ff_l2d_l2t_decc_c6_scanin[65]=ff_l2d_l2t_decc_c6_scanout[142];
assign ff_l2d_l2t_decc_c6_scanin[143]=ff_l2d_l2t_decc_c6_scanout[65];
assign ff_l2d_l2t_decc_c6_scanin[66]=ff_l2d_l2t_decc_c6_scanout[143];
assign ff_l2d_l2t_decc_c6_scanin[144]=ff_l2d_l2t_decc_c6_scanout[66];
assign ff_l2d_l2t_decc_c6_scanin[67]=ff_l2d_l2t_decc_c6_scanout[144];
assign ff_l2d_l2t_decc_c6_scanin[145]=ff_l2d_l2t_decc_c6_scanout[67];
assign ff_l2d_l2t_decc_c6_scanin[68]=ff_l2d_l2t_decc_c6_scanout[145];
assign ff_l2d_l2t_decc_c6_scanin[146]=ff_l2d_l2t_decc_c6_scanout[68];
assign ff_l2d_l2t_decc_c6_scanin[69]=ff_l2d_l2t_decc_c6_scanout[146];
assign ff_l2d_l2t_decc_c6_scanin[147]=ff_l2d_l2t_decc_c6_scanout[69];
assign ff_l2d_l2t_decc_c6_scanin[70]=ff_l2d_l2t_decc_c6_scanout[147];
assign ff_l2d_l2t_decc_c6_scanin[148]=ff_l2d_l2t_decc_c6_scanout[70];
assign ff_l2d_l2t_decc_c6_scanin[71]=ff_l2d_l2t_decc_c6_scanout[148];
assign ff_l2d_l2t_decc_c6_scanin[149]=ff_l2d_l2t_decc_c6_scanout[71];
assign ff_l2d_l2t_decc_c6_scanin[72]=ff_l2d_l2t_decc_c6_scanout[149];
assign ff_l2d_l2t_decc_c6_scanin[150]=ff_l2d_l2t_decc_c6_scanout[72];
assign ff_l2d_l2t_decc_c6_scanin[73]=ff_l2d_l2t_decc_c6_scanout[150];
assign ff_l2d_l2t_decc_c6_scanin[151]=ff_l2d_l2t_decc_c6_scanout[73];
assign ff_l2d_l2t_decc_c6_scanin[74]=ff_l2d_l2t_decc_c6_scanout[151];
assign ff_l2d_l2t_decc_c6_scanin[152]=ff_l2d_l2t_decc_c6_scanout[74];
assign ff_l2d_l2t_decc_c6_scanin[75]=ff_l2d_l2t_decc_c6_scanout[152];
assign ff_l2d_l2t_decc_c6_scanin[153]=ff_l2d_l2t_decc_c6_scanout[75];
assign ff_l2d_l2t_decc_c6_scanin[76]=ff_l2d_l2t_decc_c6_scanout[153];
assign ff_l2d_l2t_decc_c6_scanin[154]=ff_l2d_l2t_decc_c6_scanout[76];
assign ff_l2d_l2t_decc_c6_scanin[77]=ff_l2d_l2t_decc_c6_scanout[154];
assign ff_l2d_l2t_decc_c6_scanin[155]=ff_l2d_l2t_decc_c6_scanout[77];
assign ff_l2d_l2b_efc_fuse_data_scanin[0]=ff_l2d_l2t_decc_c6_scanout[155];
assign ff_l2d_l2b_efc_fuse_data_scanin[1]=ff_l2d_l2b_efc_fuse_data_scanout[0];
assign ff_l2d_l2b_efc_fuse_data_scanin[2]=ff_l2d_l2b_efc_fuse_data_scanout[1];
assign ff_l2d_l2b_efc_fuse_data_scanin[3]=ff_l2d_l2b_efc_fuse_data_scanout[2];
assign ff_l2d_l2b_efc_fuse_data_scanin[4]=ff_l2d_l2b_efc_fuse_data_scanout[3];
assign ff_l2d_l2b_efc_fuse_data_scanin[5]=ff_l2d_l2b_efc_fuse_data_scanout[4];
assign ff_l2d_l2b_efc_fuse_data_scanin[6]=ff_l2d_l2b_efc_fuse_data_scanout[5];
assign ff_l2d_l2b_efc_fuse_data_scanin[7]=ff_l2d_l2b_efc_fuse_data_scanout[6];
assign ff_l2d_l2b_efc_fuse_data_scanin[8]=ff_l2d_l2b_efc_fuse_data_scanout[7];
assign ff_l2d_l2b_efc_fuse_data_scanin[9]=ff_l2d_l2b_efc_fuse_data_scanout[8];
assign ff_l2b_l2d_fuse_reset_d_scanin=ff_l2d_l2b_efc_fuse_data_scanout[9];
assign ff_l2b_l2d_fuse_wren_d_scanin=ff_l2b_l2d_fuse_reset_d_scanout;
assign ff_l2b_l2d_fuse_rid_d_scanin[0]=ff_l2b_l2d_fuse_wren_d_scanout;
assign ff_l2b_l2d_fuse_rid_d_scanin[1]=ff_l2b_l2d_fuse_rid_d_scanout[0];
assign ff_l2b_l2d_fuse_rid_d_scanin[2]=ff_l2b_l2d_fuse_rid_d_scanout[1];
assign ff_l2b_l2d_fuse_rid_d_scanin[3]=ff_l2b_l2d_fuse_rid_d_scanout[2];
assign ff_l2b_l2d_fuse_rid_d_scanin[4]=ff_l2b_l2d_fuse_rid_d_scanout[3];
assign ff_l2b_l2d_fuse_rid_d_scanin[5]=ff_l2b_l2d_fuse_rid_d_scanout[4];
assign ff_l2b_l2d_fuse_rid_d_scanin[6]=ff_l2b_l2d_fuse_rid_d_scanout[5];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[0]=ff_l2b_l2d_fuse_rid_d_scanout[6];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[1]=ff_l2b_l2d_fuse_l2d_data_in_scanout[0];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[2]=ff_l2b_l2d_fuse_l2d_data_in_scanout[1];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[3]=ff_l2b_l2d_fuse_l2d_data_in_scanout[2];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[4]=ff_l2b_l2d_fuse_l2d_data_in_scanout[3];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[5]=ff_l2b_l2d_fuse_l2d_data_in_scanout[4];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[6]=ff_l2b_l2d_fuse_l2d_data_in_scanout[5];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[7]=ff_l2b_l2d_fuse_l2d_data_in_scanout[6];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[8]=ff_l2b_l2d_fuse_l2d_data_in_scanout[7];
assign ff_l2b_l2d_fuse_l2d_data_in_scanin[9]=ff_l2b_l2d_fuse_l2d_data_in_scanout[8];
assign ff_fill_clk_en_ov_stg_scanin=ff_l2b_l2d_fuse_l2d_data_in_scanout[9];
assign ff_pwrsav_ov_stg_scanin=ff_fill_clk_en_ov_stg_scanout;
assign scan_out=ff_pwrsav_ov_stg_scanout;
// fixscan end
endmodule // l2d_periph_io

module l2t_wayerr_ctl (
  l2t_l2d_way_sel_c3, 
  wayerr_c3) ;
  input [15:0] l2t_l2d_way_sel_c3;
  output wayerr_c3;
  wire   n_cell_265_net292, net10948, net10949, net10971, net12595, net12602,
         net12610, net12614, net12628, net12629, net12631, net12633, net12635,
         net12636, net12637, net12639, net1877, net1878, net1894, net1902,
         net1903, net1917, net508, net545, net566, net9955, n_cell_265_net315,
         n_cell_265_net321, net1749, net1887, net1891, net1893, net533, net534,
         net560, net586, net9949, net9959, net2033, net2035, net2041, net555,
         n_cell_265_net312, net1876, net1912, net2006, net2036, net2063,
         net2068, net1892, net11658, net11667, net2040, net544, net576, net585,
         net9930, net12609, n_cell_265_net340, n_cell_265_net341, net557,
         net558, net501, n3, net11684, n_cell_265_net310, n_cell_265_net311,
         net2052, net551, net552, net553, net554, net575, net2062, net587, n4,
         net588, n_cell_265_net308, net4464, n5, n6, n7, n8, n10, n13, n15,
         n16, n18, n20, n22, n23, n24, n27, n28, n30, n31, n34, n35, n36, n37,
         n38, n39, n40, n41, n42, n43, n44, n45;

  cl_u1_nand2_20x U88 ( .in0(n24), .in1(net11684), .out(n3) );
  cl_u1_inv_20x U90 ( .in(n_cell_265_net308), .out(net11684) );
  cl_u1_nand3_16x U40 ( .in0(n_cell_265_net292), .in1(net575), .in2(net9949), 
        .out(net545) );
  cl_u1_aoi21_16x net522 ( .in00(net545), .in10(net544), .in11(n37), .out(
        wayerr_c3) );
  cl_u1_nand2_2x U53 ( .in0(l2t_l2d_way_sel_c3[12]), .in1(
        l2t_l2d_way_sel_c3[11]), .out(net12595) );
  cl_u1_buf_32x U44 ( .in(l2t_l2d_way_sel_c3[1]), .out(net508) );
  cl_u1_inv_12x U30 ( .in(l2t_l2d_way_sel_c3[1]), .out(net1903) );
  cl_u1_nand2_6x U37 ( .in0(net1903), .in1(net12602), .out(net1902) );
  cl_u1_nand2_6x U36 ( .in0(net12602), .in1(net12635), .out(net12631) );
  cl_u1_inv_28x U11 ( .in(l2t_l2d_way_sel_c3[0]), .out(net12635) );
  cl_u1_inv_12x U54 ( .in(net12635), .out(net10971) );
  cl_u1_nor2_6x U55 ( .in0(l2t_l2d_way_sel_c3[14]), .in1(l2t_l2d_way_sel_c3[5]), .out(net10949) );
  cl_u1_nor2_12x U25 ( .in0(l2t_l2d_way_sel_c3[6]), .in1(net554), .out(net553)
         );
  cl_u1_inv_32x U75 ( .in(net2068), .out(net501) );
  cl_u1_nor2_8x U8 ( .in0(net501), .in1(net552), .out(net551) );
  cl_u1_nand2_16x U71 ( .in0(net2035), .in1(net2036), .out(net588) );
  cl_u1_inv_24x U19 ( .in(net552), .out(net2052) );
  cl_u1_nand2_20x U102 ( .in0(n34), .in1(n43), .out(net9949) );
  cl_u1_nor2_16x syn441 ( .in0(net560), .in1(net9930), .out(net533) );
  cl_u1_oai21_16x U42 ( .in00(net12629), .in10(net12628), .in11(net1917), 
        .out(net1877) );
  cl_u1_inv_24x U31 ( .in(net1902), .out(net1917) );
  cl_u1_nand2_20x U43 ( .in0(net12628), .in1(net1917), .out(net12629) );
  cl_u1_inv_16x U12 ( .in(net9955), .out(net1912) );
  cl_u1_nor2_16x U47 ( .in0(net1894), .in1(net1893), .out(net1878) );
  cl_u1_oai21_4x U108 ( .in00(l2t_l2d_way_sel_c3[2]), .in10(n23), .in11(
        l2t_l2d_way_sel_c3[4]), .out(n_cell_265_net311) );
  cl_u1_nor2_16x U56 ( .in0(net1892), .in1(net1891), .out(net1876) );
  cl_u1_nand2_6x U26 ( .in0(net552), .in1(net2063), .out(net2062) );
  cl_u1_inv_24x U93 ( .in(l2t_l2d_way_sel_c3[10]), .out(net12637) );
  cl_u1_inv_24x U74 ( .in(net2068), .out(net2006) );
  cl_u1_nand2_6x U17 ( .in0(net586), .in1(net576), .out(n10) );
  cl_u1_inv_12x U34 ( .in(net10971), .out(net10948) );
  cl_u1_inv_12x U35 ( .in(net11658), .out(n13) );
  cl_u1_inv_16x syn341 ( .in(n_cell_265_net340), .out(net12609) );
  cl_u1_nand3_12x U104 ( .in0(net1887), .in1(net1912), .in2(net552), .out(
        net1891) );
  cl_u1_inv_28x U50 ( .in(l2t_l2d_way_sel_c3[11]), .out(net12639) );
  cl_u1_nand3_24x net4453 ( .in0(n41), .in1(n42), .in2(n22), .out(net2033) );
  cl_u1_nand2_8x U52 ( .in0(n15), .in1(n16), .out(net11667) );
  cl_u1_nand2_16x U22 ( .in0(net1749), .in1(n27), .out(net560) );
  cl_u1_nor2_16x U66 ( .in0(n18), .in1(net2062), .out(net2041) );
  cl_u1_nand2_6x U106 ( .in0(n23), .in1(net4464), .out(n5) );
  cl_u1_buf_32x U67 ( .in(l2t_l2d_way_sel_c3[7]), .out(n20) );
  cl_u1_nor2_4x U61 ( .in0(n20), .in1(l2t_l2d_way_sel_c3[6]), .out(
        n_cell_265_net315) );
  cl_u1_inv_8x syn445 ( .in(l2t_l2d_way_sel_c3[7]), .out(net1749) );
  cl_u1_nor2_8x U13 ( .in0(net2006), .in1(net2052), .out(net2036) );
  cl_u1_inv_4x U32 ( .in(net2006), .out(net2063) );
  cl_u1_nor2_6x U70 ( .in0(n28), .in1(net2006), .out(n_cell_265_net312) );
  cl_u1_nand2_16x U48 ( .in0(n8), .in1(net12614), .out(net558) );
  cl_u1_nand3_8x U49 ( .in0(n8), .in1(net12609), .in2(net12610), .out(net9959)
         );
  cl_u1_nand2_4x U112 ( .in0(l2t_l2d_way_sel_c3[4]), .in1(n22), .out(n6) );
  cl_u1_inv_12x U82 ( .in(l2t_l2d_way_sel_c3[5]), .out(n27) );
  cl_u1_nand3_8x U21 ( .in0(net533), .in1(net534), .in2(net552), .out(
        n_cell_265_net321) );
  cl_u1_nand3_16x U28 ( .in0(n38), .in1(n13), .in2(n35), .out(net1892) );
  cl_u1_oai22_8x U59 ( .in00(n28), .in01(net1749), .in10(n20), .in11(n27), 
        .out(net586) );
  cl_u1_buf_32x U83 ( .in(l2t_l2d_way_sel_c3[5]), .out(n28) );
  cl_u1_inv_16x U9 ( .in(net12636), .out(n8) );
  cl_u1_inv_28x U94 ( .in(l2t_l2d_way_sel_c3[12]), .out(n31) );
  cl_u1_nand2_20x U78 ( .in0(net585), .in1(n3), .out(net544) );
  cl_u1_inv_12x U86 ( .in(n_cell_265_net341), .out(n_cell_265_net340) );
  cl_u1_nor2_6x U45 ( .in0(net508), .in1(net501), .out(n_cell_265_net341) );
  cl_u1_nand3_6x U98 ( .in0(net12602), .in1(net12635), .in2(net566), .out(
        net12633) );
  cl_u1_nor2_6x U33 ( .in0(net1903), .in1(net12602), .out(net9955) );
  cl_u1_nor2_8x U27 ( .in0(net566), .in1(net12631), .out(net12610) );
  cl_u1_inv_24x U29 ( .in(l2t_l2d_way_sel_c3[15]), .out(net12602) );
  cl_u1_inv_16x U10 ( .in(l2t_l2d_way_sel_c3[14]), .out(net566) );
  cl_u1_inv_12x U76 ( .in(net501), .out(net554) );
  cl_u1_inv_28x syn450 ( .in(l2t_l2d_way_sel_c3[6]), .out(net552) );
  cl_u1_inv_20x U24 ( .in(l2t_l2d_way_sel_c3[13]), .out(net2068) );
  cl_u1_nand2_6x U62 ( .in0(n_cell_265_net315), .in1(net576), .out(
        n_cell_265_net308) );
  cl_u1_inv_20x U103 ( .in(net534), .out(net1893) );
  cl_u1_nand2_6x U81 ( .in0(n36), .in1(n40), .out(net11658) );
  cl_u1_inv_24x U38 ( .in(net9930), .out(net576) );
  cl_u1_nand2_12x U80 ( .in0(n36), .in1(n40), .out(net9930) );
  cl_u1_inv_12x U72 ( .in(n22), .out(n23) );
  cl_u1_inv_24x U69 ( .in(l2t_l2d_way_sel_c3[3]), .out(n22) );
  cl_u1_inv_20x U96 ( .in(net9959), .out(n34) );
  cl_u1_nor2_16x U97 ( .in0(net558), .in1(net560), .out(net557) );
  cl_u1_oai21_12x U100 ( .in00(net555), .in10(net551), .in11(net553), .out(
        net587) );
  cl_u1_nand2_16x U109 ( .in0(net2040), .in1(net2041), .out(net585) );
  cl_u1_inv_6x U20 ( .in(n10), .out(net2040) );
  cl_u1_nor2_16x U16 ( .in0(n20), .in1(net2006), .out(net1887) );
  cl_u1_buf_16x U110 ( .in(net12595), .out(n35) );
  cl_u1_nand2_16x U99 ( .in0(net588), .in1(net587), .out(n4) );
  cl_u1_nor2_16x U101 ( .in0(net2033), .in1(net11667), .out(net2035) );
  cl_u1_inv_16x U111 ( .in(l2t_l2d_way_sel_c3[8]), .out(n40) );
  cl_u1_nand2_28x U113 ( .in0(n45), .in1(net12635), .out(net12628) );
  cl_u1_buf_16x U114 ( .in(n39), .out(n37) );
  cl_u1_nand2_2x U115 ( .in0(l2t_l2d_way_sel_c3[9]), .in1(
        l2t_l2d_way_sel_c3[8]), .out(n15) );
  cl_u1_nand2_8x U51 ( .in0(n36), .in1(n40), .out(n16) );
  cl_u1_inv_20x U116 ( .in(l2t_l2d_way_sel_c3[9]), .out(n36) );
  cl_u1_oai12_12x U23 ( .in00(n30), .in01(net10948), .in10(net10949), .out(
        net1894) );
  cl_u1_inv_20x U117 ( .in(n7), .out(n38) );
  cl_u1_inv_4x U118 ( .in(net558), .out(n39) );
  cl_u1_nor2_12x syn281 ( .in0(net508), .in1(net12633), .out(net12614) );
  cl_u1_nand2_20x U18 ( .in0(n4), .in1(net557), .out(net575) );
  cl_u1_inv_32x U119 ( .in(net12636), .out(n45) );
  cl_u1_inv_20x U120 ( .in(l2t_l2d_way_sel_c3[4]), .out(n41) );
  cl_u1_inv_4x U105 ( .in(l2t_l2d_way_sel_c3[4]), .out(net4464) );
  cl_u1_inv_20x U121 ( .in(l2t_l2d_way_sel_c3[2]), .out(n42) );
  cl_u1_nand3_4x U107 ( .in0(n5), .in1(n6), .in2(n42), .out(n_cell_265_net310)
         );
  cl_u1_inv_20x U122 ( .in(n_cell_265_net321), .out(n43) );
  cl_u1_nand3_16x U123 ( .in0(net1877), .in1(net1876), .in2(net1878), .out(
        n_cell_265_net292) );
  cl_u1_nand3_6x U124 ( .in0(n_cell_265_net310), .in1(n_cell_265_net311), 
        .in2(n_cell_265_net312), .out(n44) );
  cl_u1_inv_20x U125 ( .in(n44), .out(n24) );
  cl_u1_inv_28x U57 ( .in(net2033), .out(net534) );
  cl_u1_buf_20x U39 ( .in(net2033), .out(n18) );
  cl_u1_nor2_16x U126 ( .in0(net2033), .in1(net9930), .out(net555) );
  cl_u1_inv_28x U91 ( .in(net12636), .out(n30) );
  cl_u1_nand3_20x U92 ( .in0(net12639), .in1(n31), .in2(net12637), .out(
        net12636) );
  cl_u1_aoi21_8x U6 ( .in00(net12637), .in10(net12639), .in11(n31), .out(n7)
         );
endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro (
  l2clk, 
  l1en, 
  pce_ov, 
  stop, 
  se, 
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module n2_l2d_sp_512kb_cust_or_macro__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


or2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input [0:0] scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output [0:0] scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in[0:0]),
.so(scan_out[0:0]),
.q(dout[0:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module n2_l2d_sp_512kb_cust_or_macro__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


or2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_156 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [155:0] fdin;

  input [155:0] din;
  input l1clk;
  input [155:0] scan_in;


  input siclk;
  input soclk;

  output [155:0] dout;
  output [155:0] scan_out;
assign fdin[155:0] = din[155:0];


dff #(156)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[155:0]),
.si(scan_in[155:0]),
.so(scan_out[155:0]),
.q(dout[155:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [38:0] fdin;

  input [38:0] din;
  input l1clk;
  input [38:0] scan_in;


  input siclk;
  input soclk;

  output [38:0] dout;
  output [38:0] scan_out;
assign fdin[38:0] = din[38:0];


dff #(39)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[38:0]),
.si(scan_in[38:0]),
.so(scan_out[38:0]),
.q(dout[38:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_16 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [15:0] fdin;

  input [15:0] din;
  input l1clk;
  input [15:0] scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output [15:0] scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si(scan_in[15:0]),
.so(scan_out[15:0]),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_10 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [9:0] fdin;

  input [9:0] din;
  input l1clk;
  input [9:0] scan_in;


  input siclk;
  input soclk;

  output [9:0] dout;
  output [9:0] scan_out;
assign fdin[9:0] = din[9:0];


dff #(10)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[9:0]),
.si(scan_in[9:0]),
.so(scan_out[9:0]),
.q(dout[9:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_7 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [6:0] fdin;

  input [6:0] din;
  input l1clk;
  input [6:0] scan_in;


  input siclk;
  input soclk;

  output [6:0] dout;
  output [6:0] scan_out;
assign fdin[6:0] = din[6:0];


dff #(7)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[6:0]),
.si(scan_in[6:0]),
.so(scan_out[6:0]),
.q(dout[6:0])
);


endmodule


//
//   invert macro
//
//


module n2_l2d_sp_512kb_cust_inv_macro__width_2 (
  din, 
  dout);
  input [1:0] din;
  output [1:0] dout;


inv #(2)  d0_0 (
.in(din[1:0]),
.out(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_l2d_sp_512kb_cust_and_macro__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


and2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


module n2_l2d_quad_cust (
  waysel_c3_0, 
  wayerr_c3_0, 
  set_c3_0, 
  coloff_c3_0, 
  coloff_c4_l_0, 
  coloff_c5_0, 
  rd_wr_c3_0, 
  readen_c5_0, 
  worden_c3_0, 
  l2clk, 
  tcu_pce_ov_0, 
  pce_0, 
  se_0, 
  tcu_clk_stop_0, 
  wrdlo0_b_l, 
  wrdhi0_b_l, 
  wrdlo1_b_l, 
  wrdhi1_b_l, 
  ldoutlo0_b, 
  ldouthi0_b, 
  ldoutlo1_b, 
  ldouthi1_b, 
  fuse_l2d_data_in_00, 
  fuse_l2d_rid_00, 
  fuse_l2d_wren_00, 
  fuse_l2d_reset_00_l, 
  fdout_00, 
  fuse_l2d_data_in_01, 
  fuse_l2d_rid_01, 
  fuse_l2d_wren_01, 
  fuse_l2d_reset_01_l, 
  fdout_01, 
  fuse_l2d_data_in_10, 
  fuse_l2d_rid_10, 
  fuse_l2d_wren_10, 
  fuse_l2d_reset_10_l, 
  fdout_10, 
  fuse_l2d_data_in_11, 
  fuse_l2d_rid_11, 
  fuse_l2d_wren_11, 
  fuse_l2d_reset_11_l, 
  fdout_11, 
  waysel_c3_1, 
  wayerr_c3_1, 
  set_c3_1, 
  coloff_c3_1, 
  coloff_c4_l_1, 
  coloff_c5_1, 
  rd_wr_c3_1, 
  readen_c5_1, 
  worden_c3_1, 
  tcu_pce_ov_1, 
  pce_1, 
  se_1, 
  tcu_clk_stop_1, 
  wee_l_0, 
  wee_l_1, 
  tstmodclk_l_0, 
  tstmodclk_l_1, 
  vnw_ary);
wire [9:0] left_red_top_d_00;
wire [9:0] left_red_top_d_01;
wire [38:0] ldoutlo0_b_top;
wire [38:0] ldouthi0_b_top;
wire [38:0] ldoutlo1_b_top;
wire [38:0] ldouthi1_b_top;
wire [9:0] right_red_top_d_00;
wire [9:0] right_red_top_d_01;

		
input	[15:0]	 	waysel_c3_0;			//	way_sel
input			wayerr_c3_0;		// 	way_sel error
input	[8:0] 	 	set_c3_0;		  	//	set
input	 	 	coloff_c3_0;		  	//	col_offset
input	 	 	coloff_c4_l_0;		  	//	NEW(one stage+inv)
input	[1:0] 	 	coloff_c5_0;		  	//	NEW(two stage)
input	     	 	rd_wr_c3_0;		  	//	wr_en
input	     	 	readen_c5_0;		  	//	NEW(two stage)
input	[3:0] 	 	worden_c3_0;		  	//	word_en
input	      	 	l2clk;			  	//	l2clk
input	     	 	tcu_pce_ov_0;		  	//	tcu_pce_ov
input	     	 	pce_0;			  	//	NEW
input			se_0;
input	     	 	tcu_clk_stop_0;	  	//	NEW
input	[38:0]	 	wrdlo0_b_l;		     //      decc_in(c3-bphase)
input	[38:0]	 	wrdhi0_b_l;		     //      decc_in(c3-bphase)
input	[38:0]	 	wrdlo1_b_l;		     //      decc_in(c3-bphase)
input	[38:0]	 	wrdhi1_b_l;		     //      decc_in(c3-bphase)
output	[38:0]		ldoutlo0_b;		     //      decc_c52-b
output	[38:0]		ldouthi0_b;		     //      decc_c52-b
output	[38:0]		ldoutlo1_b;		     //      decc_c52-b
output	[38:0]		ldouthi1_b;		     //      decc_c52-b

input   [9:0]   fuse_l2d_data_in_00;
input   [4:0]   fuse_l2d_rid_00;
input           fuse_l2d_wren_00;
input           fuse_l2d_reset_00_l;
output  [9:0]   fdout_00;
input   [9:0]   fuse_l2d_data_in_01;
input   [4:0]   fuse_l2d_rid_01;
input           fuse_l2d_wren_01;
input           fuse_l2d_reset_01_l;
output  [9:0]   fdout_01;
input   [9:0]   fuse_l2d_data_in_10;
input   [4:0]   fuse_l2d_rid_10;
input           fuse_l2d_wren_10;
input           fuse_l2d_reset_10_l;
output  [9:0]   fdout_10;
input   [9:0]   fuse_l2d_data_in_11;
input   [4:0]   fuse_l2d_rid_11;
input           fuse_l2d_wren_11;
input           fuse_l2d_reset_11_l;
output  [9:0]   fdout_11;

input	[15:0]		 waysel_c3_1;		//	way_sel
input			 wayerr_c3_1;		// 	way_sel error
input	[8:0]		 set_c3_1;		//	set
input		 	coloff_c3_1;		//	col_offset
input		 	coloff_c4_l_1;		//	NEW(one stage+inv)
input	[1:0]		 coloff_c5_1;		//	NEW(two stage)
input			 rd_wr_c3_1;		//	wr_en
input			 readen_c5_1;		//	NEW(two stage)
input	[3:0]		 worden_c3_1;		//	word_en
input			 tcu_pce_ov_1;		//	tcu_pce_ov
input	       	 	 pce_1;			//	NEW
input			 se_1;
input			 tcu_clk_stop_1;	//	NEW
input                    wee_l_0;               //	NEW
input                    wee_l_1;               //	NEW
input			 tstmodclk_l_0;
input			 tstmodclk_l_1;
input                    vnw_ary;               //      NEW


n2_l2d_32kb_cust	way07_00	
	(
	.waysel_c3           	(waysel_c3_0[7:0]),
	.waysel_err_c3         (wayerr_c3_0),
	.set_c3              	(set_c3_0[8:0]),
	.coloff_c3           	(coloff_c3_0),
	.coloff_c4_l         	(coloff_c4_l_0),
	.coloff_c5           	(coloff_c5_0[1:0]),
	.rd_wr_c3            	(rd_wr_c3_0),
	.readen_c5           	(readen_c5_0),
	.l2clk               	(l2clk),
	.fuse_l2d_data_in_00    (fuse_l2d_data_in_00[9:0]),
	.fuse_l2d_rid_00        (fuse_l2d_rid_00[2:0]),
	.fuse_l2d_wren_00       (fuse_l2d_wren_00),
	.fuse_l2d_reset_00_l     (fuse_l2d_reset_00_l),
	.sel_quad_00            (fuse_l2d_rid_00[4]),
	.fuse_l2d_data_in_01    (fuse_l2d_data_in_01[9:0]),
	.fuse_l2d_rid_01        (fuse_l2d_rid_01[2:0]),
	.fuse_l2d_wren_01       (fuse_l2d_wren_01),
	.fuse_l2d_reset_01_l     (fuse_l2d_reset_01_l),
	.sel_quad_01            (fuse_l2d_rid_01[4]),
	.red_d_out_00		(left_red_top_d_00[9:0]),
	.red_d_out_01		(left_red_top_d_01[9:0]),
	.red_top_d_00		(10'b0),
	.red_top_d_01		(10'b0),
	.tcu_pce_ov          	(tcu_pce_ov_0),
	.tcu_pce                (pce_0),
	.se                     (se_0),
	.tcu_clk_stop        	(tcu_clk_stop_0),
	.wrd0lo_b_l          	(wrdlo0_b_l[19:0]),
	.wrd0hi_b_l          	(wrdhi0_b_l[19:0]),
	.wrd1lo_b_l          	(wrdlo1_b_l[18:0]),
	.wrd1hi_b_l          	(wrdhi1_b_l[18:0]),
	.ldin0lo_b           	(20'b0),
	.ldin0hi_b           	(20'b0),
	.ldin1lo_b           	(19'b0),
	.ldin1hi_b           	(19'b0),
	.worden_c3           	(worden_c3_0[3:0]),
        .tstmodclk_l            (tstmodclk_l_0),
	.wee_l                  (wee_l_0),
	.ldout0lo_b00		(ldoutlo0_b_top[19:0]),
	.ldout0hi_b00		(ldouthi0_b_top[19:0]),
	.ldout1lo_b00		(ldoutlo1_b_top[18:0]),
	.ldout1hi_b00		(ldouthi1_b_top[18:0]),
        .vnw_ary                (vnw_ary)
	);

n2_l2d_32kb_cust        way158_00
        (
        .waysel_c3              (waysel_c3_0[15:8]),
	.waysel_err_c3         (wayerr_c3_0),
        .set_c3                 (set_c3_0[8:0]),
        .coloff_c3              (coloff_c3_0),
        .coloff_c4_l            (coloff_c4_l_0),
        .coloff_c5              (coloff_c5_0[1:0]),
        .rd_wr_c3               (rd_wr_c3_0),
        .readen_c5              (readen_c5_0),
        .l2clk                  (l2clk),
	.fuse_l2d_data_in_00    (fuse_l2d_data_in_00[9:0]),
	.fuse_l2d_rid_00        (fuse_l2d_rid_00[2:0]),
	.fuse_l2d_wren_00       (fuse_l2d_wren_00),
	.fuse_l2d_reset_00_l     (fuse_l2d_reset_00_l),
	.sel_quad_00            (fuse_l2d_rid_00[3]),
	.fuse_l2d_data_in_01    (fuse_l2d_data_in_01[9:0]),
	.fuse_l2d_rid_01        (fuse_l2d_rid_01[2:0]),
	.fuse_l2d_wren_01       (fuse_l2d_wren_01),
	.fuse_l2d_reset_01_l     (fuse_l2d_reset_01_l),
	.sel_quad_01            (fuse_l2d_rid_01[3]),
	.red_d_out_00		(fdout_00[9:0]),
	.red_d_out_01		(fdout_01[9:0]),
	.red_top_d_00		(left_red_top_d_00[9:0]),
	.red_top_d_01		(left_red_top_d_01[9:0]),
        .tcu_pce_ov             (tcu_pce_ov_0),
        .tcu_pce                (pce_0),
        .se                     (se_0),
        .tcu_clk_stop           (tcu_clk_stop_0),
        .worden_c3              (worden_c3_0[3:0]),
        .tstmodclk_l            (tstmodclk_l_0),
	.wee_l                  (wee_l_0),	
        .wrd0lo_b_l             (wrdlo0_b_l[19:0]),
        .wrd0hi_b_l             (wrdhi0_b_l[19:0]),
        .wrd1lo_b_l             (wrdlo1_b_l[18:0]),
        .wrd1hi_b_l             (wrdhi1_b_l[18:0]),
        .ldin0lo_b              (ldoutlo0_b_top[19:0]),
        .ldin0hi_b              (ldouthi0_b_top[19:0]),
        .ldin1lo_b              (ldoutlo1_b_top[18:0]),
        .ldin1hi_b              (ldouthi1_b_top[18:0]),
        .ldout0lo_b00		(ldoutlo0_b[19:0]),
        .ldout0hi_b00		(ldouthi0_b[19:0]),
        .ldout1lo_b00		(ldoutlo1_b[18:0]),
        .ldout1hi_b00		(ldouthi1_b[18:0]),
        .vnw_ary                (vnw_ary)
        );


n2_l2d_32kb_cust	way70_01	
	(
	.waysel_c3           	(waysel_c3_1[7:0]),
	.waysel_err_c3         (wayerr_c3_1),
	.set_c3              	(set_c3_1[8:0]),
	.coloff_c3           	(coloff_c3_1),
	.coloff_c4_l         	(coloff_c4_l_1),
	.coloff_c5           	({coloff_c5_1[0],coloff_c5_1[1]}),
	.rd_wr_c3            	(rd_wr_c3_1),
	.readen_c5           	(readen_c5_1),
	.l2clk               	(l2clk),
	.fuse_l2d_data_in_00    (fuse_l2d_data_in_10[9:0]),
	.fuse_l2d_rid_00        (fuse_l2d_rid_10[2:0]),
	.fuse_l2d_wren_00       (fuse_l2d_wren_10),
	.fuse_l2d_reset_00_l     (fuse_l2d_reset_10_l),
	.sel_quad_00            (fuse_l2d_rid_10[4]),
	.fuse_l2d_data_in_01    (fuse_l2d_data_in_11[9:0]),
	.fuse_l2d_rid_01        (fuse_l2d_rid_11[2:0]),
	.fuse_l2d_wren_01       (fuse_l2d_wren_11),
	.fuse_l2d_reset_01_l     (fuse_l2d_reset_11_l),
	.sel_quad_01            (fuse_l2d_rid_11[4]),
	.red_d_out_00		(right_red_top_d_00[9:0]),
	.red_d_out_01		(right_red_top_d_01[9:0]),
	.red_top_d_00		(10'b0),
	.red_top_d_01		(10'b0),
	.tcu_pce_ov          	(tcu_pce_ov_1),
	.tcu_pce                (pce_1),
        .se                     (se_1),
	.tcu_clk_stop        	(tcu_clk_stop_1),
	.wrd0lo_b_l          	(wrdlo1_b_l[38:19]),
	.wrd0hi_b_l          	(wrdhi1_b_l[38:19]),
	.wrd1lo_b_l          	(wrdlo0_b_l[38:20]),
	.wrd1hi_b_l          	(wrdhi0_b_l[38:20]),
	.ldin0lo_b           	(20'b0),
	.ldin0hi_b           	(20'b0),
	.ldin1lo_b           	(19'b0),
	.ldin1hi_b           	(19'b0),
	.worden_c3           	(worden_c3_1[3:0]),
        .tstmodclk_l            (tstmodclk_l_1),
	.wee_l                  (wee_l_1),
	.ldout0lo_b00		(ldoutlo1_b_top[38:19]),
	.ldout0hi_b00		(ldouthi1_b_top[38:19]),
	.ldout1lo_b00		(ldoutlo0_b_top[38:20]),
	.ldout1hi_b00		(ldouthi0_b_top[38:20]),
        .vnw_ary                (vnw_ary)
	);

n2_l2d_32kb_cust        way158_01
        (
        .waysel_c3              (waysel_c3_1[15:8]),
	.waysel_err_c3         (wayerr_c3_1),
        .set_c3                 (set_c3_1[8:0]),
        .coloff_c3              (coloff_c3_1),
        .coloff_c4_l            (coloff_c4_l_1),
        .coloff_c5              ({coloff_c5_1[0],coloff_c5_1[1]}),
        .rd_wr_c3               (rd_wr_c3_1),
        .readen_c5              (readen_c5_1),
        .l2clk                  (l2clk),
	.fuse_l2d_data_in_00    (fuse_l2d_data_in_10[9:0]),
	.fuse_l2d_rid_00        (fuse_l2d_rid_10[2:0]),
	.fuse_l2d_wren_00       (fuse_l2d_wren_10),
	.fuse_l2d_reset_00_l     (fuse_l2d_reset_10_l),
	.sel_quad_00            (fuse_l2d_rid_10[3]),
	.fuse_l2d_data_in_01    (fuse_l2d_data_in_11[9:0]),
	.fuse_l2d_rid_01        (fuse_l2d_rid_11[2:0]),
	.fuse_l2d_wren_01       (fuse_l2d_wren_11),
	.fuse_l2d_reset_01_l     (fuse_l2d_reset_11_l),
	.sel_quad_01            (fuse_l2d_rid_11[3]),
	.red_d_out_00		(fdout_10[9:0]),
	.red_d_out_01		(fdout_11[9:0]),
	.red_top_d_00		(right_red_top_d_00[9:0]),
	.red_top_d_01		(right_red_top_d_01[9:0]),
        .tcu_pce_ov             (tcu_pce_ov_1),
	.tcu_pce                (pce_1),
        .se                     (se_1),
        .tcu_clk_stop           (tcu_clk_stop_1),
        .wrd0lo_b_l             (wrdlo1_b_l[38:19]),
        .wrd0hi_b_l             (wrdhi1_b_l[38:19]),
        .wrd1lo_b_l             (wrdlo0_b_l[38:20]),
        .wrd1hi_b_l             (wrdhi0_b_l[38:20]),
        .ldin0lo_b              (ldoutlo1_b_top[38:19]),
        .ldin0hi_b              (ldouthi1_b_top[38:19]),
        .ldin1lo_b              (ldoutlo0_b_top[38:20]),
        .ldin1hi_b              (ldouthi0_b_top[38:20]),
        .worden_c3              (worden_c3_1[3:0]),
        .tstmodclk_l            (tstmodclk_l_1),
	.wee_l                  (wee_l_1),
        .ldout0lo_b00		(ldoutlo1_b[38:19]),
        .ldout0hi_b00		(ldouthi1_b[38:19]),
        .ldout1lo_b00		(ldoutlo0_b[38:20]),
        .ldout1hi_b00		(ldouthi0_b[38:20]),
        .vnw_ary                (vnw_ary)
        );


endmodule


module n2_l2d_32kb_cust (
  waysel_c3, 
  waysel_err_c3, 
  set_c3, 
  coloff_c3, 
  coloff_c4_l, 
  coloff_c5, 
  rd_wr_c3, 
  readen_c5, 
  l2clk, 
  fuse_l2d_data_in_00, 
  fuse_l2d_rid_00, 
  fuse_l2d_wren_00, 
  fuse_l2d_reset_00_l, 
  sel_quad_00, 
  red_d_out_00, 
  fuse_l2d_data_in_01, 
  fuse_l2d_rid_01, 
  fuse_l2d_wren_01, 
  fuse_l2d_reset_01_l, 
  sel_quad_01, 
  red_d_out_01, 
  red_top_d_00, 
  red_top_d_01, 
  tcu_pce_ov, 
  tcu_pce, 
  se, 
  tcu_clk_stop, 
  wrd0lo_b_l, 
  wrd0hi_b_l, 
  wrd1lo_b_l, 
  wrd1hi_b_l, 
  ldin0lo_b, 
  ldin0hi_b, 
  ldin1lo_b, 
  ldin1hi_b, 
  worden_c3, 
  tstmodclk_l, 
  wee_l, 
  vnw_ary, 
  ldout0lo_b00, 
  ldout0hi_b00, 
  ldout1lo_b00, 
  ldout1hi_b00);
wire [7:0] waysel_top_c4;
wire [8:0] set_top_c3b;
wire coloff_top_c3b_l;
wire writeen_top_c3b;
wire [3:0] worden_top_c3b;
wire l1clk;
wire [9:0] red_addr_top_01;
wire [77:0] cred;
wire [19:0] sat_lo0_bc_l;
wire [19:0] sat_hi0_bc_l;
wire [18:0] sat_lo1_bc_l;
wire [18:0] sat_hi1_bc_l;
wire [7:0] waysel_bot_c4;
wire [8:0] set_bot_c3b;
wire coloff_bot_c3b_l;
wire writeen_bot_c3b;
wire [3:0] worden_bot_c3b;
wire [9:0] red_addr_bot_00;
wire [19:0] sab_lo0_bc_l;
wire [19:0] sab_hi0_bc_l;
wire [18:0] sab_lo1_bc_l;
wire [18:0] sab_hi1_bc_l;


input	[7:0]	waysel_c3;
input	     	waysel_err_c3;
input	[8:0]	set_c3;
input		coloff_c3;
input		coloff_c4_l;	// check if 1 bit
input	[1:0]	coloff_c5;	// check if 1 bit
input		rd_wr_c3;
input		readen_c5;
input		l2clk;


input	[9:0]	fuse_l2d_data_in_00;
input	[2:0]	fuse_l2d_rid_00;
input		fuse_l2d_wren_00;
input		fuse_l2d_reset_00_l;
input		sel_quad_00;
output	[9:0]	red_d_out_00;

input	[9:0]	fuse_l2d_data_in_01;
input	[2:0]	fuse_l2d_rid_01;
input		fuse_l2d_wren_01;
input		fuse_l2d_reset_01_l;
input		sel_quad_01;
output	[9:0]	red_d_out_01;

input	[9:0]	red_top_d_00;
input	[9:0]	red_top_d_01;

input		tcu_pce_ov;
input		tcu_pce;
input		se;
input		tcu_clk_stop;
input	[19:0]	wrd0lo_b_l;
input	[19:0]	wrd0hi_b_l;
input	[18:0]	wrd1lo_b_l;
input	[18:0]	wrd1hi_b_l;
input	[19:0]	ldin0lo_b;
input	[19:0]	ldin0hi_b;
input	[18:0]	ldin1lo_b;
input	[18:0]	ldin1hi_b;
input	[3:0]	worden_c3;
input           tstmodclk_l;
input           wee_l;
input           vnw_ary;        //NEW

output	[19:0]	ldout0lo_b00;
output	[19:0]	ldout0hi_b00;
output	[18:0]	ldout1lo_b00;
output	[18:0]	ldout1hi_b00;


n2_l2d_16kb_cust	set_top
	(
	.waysel_c4		(waysel_top_c4[7:0]),
	.waysel_err_c3		(waysel_err_c3),
	.set_c3b		(set_top_c3b[8:0]),
	.coloff_c3b_l		(coloff_top_c3b_l),
	.coloff_c4_l		(coloff_c4_l),
	.coloff_c5		(coloff_c5[1:0]),
	.wen_c3b		(writeen_top_c3b),
	.readen_c5		(readen_c5),
	.worden_c3b		(worden_top_c3b[3:0]),
	.l1clk			(l1clk),
	.wrd_lo0_b_l		(wrd0lo_b_l[19:0]),
	.wrd_hi0_b_l		(wrd0hi_b_l[19:0]),
	.wrd_lo1_b_l		(wrd1lo_b_l[18:0]),
	.wrd_hi1_b_l		(wrd1hi_b_l[18:0]),
//	.bnken_lat		(bnken_lat),
	.red_adr		(red_addr_top_01[9:0]),
	.cred			(cred[77:0]),
//        .fuse_l2d_reset  	(fuse_l2d_reset_00_l_buf),
	.saout_lo0_bc_l		(sat_lo0_bc_l[19:0]),
	.saout_hi0_bc_l		(sat_hi0_bc_l[19:0]),
	.saout_lo1_bc_l		(sat_lo1_bc_l[18:0]),
	.saout_hi1_bc_l		(sat_hi1_bc_l[18:0]),
	.tstmodclk_l		(tstmodclk_l),		//NEW
	.wee_l			(wee_l),		//NEW
	.vnw_ary                (vnw_ary)               //NEW
	);

n2_l2d_16kb_cust     set_bot
        (
        .waysel_c4        	(waysel_bot_c4[7:0]),
	.waysel_err_c3		(waysel_err_c3),
        .set_c3b           	(set_bot_c3b[8:0]),
        .coloff_c3b_l      	(coloff_bot_c3b_l),
        .coloff_c4_l       	(coloff_c4_l),
        .coloff_c5         	(coloff_c5[1:0]),
        .wen_c3b               	(writeen_bot_c3b),
        .readen_c5             	(readen_c5),
        .worden_c3b        	(worden_bot_c3b[3:0]),
        .l1clk                 	(l1clk),
	.wrd_lo0_b_l		(wrd0lo_b_l[19:0]),
	.wrd_hi0_b_l		(wrd0hi_b_l[19:0]),
	.wrd_lo1_b_l		(wrd1lo_b_l[18:0]),
	.wrd_hi1_b_l		(wrd1hi_b_l[18:0]),
	.red_adr		(red_addr_bot_00[9:0]),
//        .bnken_lat             	(),
	.cred			(cred[77:0]),
//        .fuse_l2d_reset  	(fuse_l2d_reset_01_l_buf),
        .saout_lo0_bc_l   	(sab_lo0_bc_l[19:0]),
        .saout_hi0_bc_l   	(sab_hi0_bc_l[19:0]),
        .saout_lo1_bc_l   	(sab_lo1_bc_l[18:0]),
        .saout_hi1_bc_l   	(sab_hi1_bc_l[18:0]),
	.tstmodclk_l		(tstmodclk_l),		//NEW
	.wee_l			(wee_l),		//NEW
        .vnw_ary                (vnw_ary)               //NEW
        );


n2_l2d_dmux78_cust	data_mux
	(
	.waysel_c3		(waysel_c3[7:0]),		// should be 15:0
	.set_c3			(set_c3[8:0]),
	.coloff_c3		(coloff_c3),
//	.coloff_c4_l		(coloff_c4_l),
//	.coloff_c5		(coloff_c5[1:0]),
	.rd_wr_c3        	(rd_wr_c3),
//	.readen_c5       	(readen_c5),
	.worden_c3       	(worden_c3[3:0]),
	.l2clk           	(l2clk),
	.tcu_pce_ov      	(tcu_pce_ov),
	.tcu_pce             	(tcu_pce),
	.se             	(se),
	.tcu_clk_stop    	(tcu_clk_stop),
	.waysel_top_c4		(waysel_top_c4[7:0]),
	.waysel_bot_c4		(waysel_bot_c4[7:0]),
	.set_top_c3b		(set_top_c3b[8:0]),
	.set_bot_c3b		(set_bot_c3b[8:0]),
//	.coloff_top_c3b_l	(coloff_top_c3b_l),
//	.coloff_bot_c3b_l	(coloff_bot_c3b_l),
//	.coloff_top_c4_l 	(coloff_top_c4_l),
//	.coloff_bot_c4_l 	(coloff_bot_c4_l),
//	.coloff_top_c5   	(coloff_top_c5),
//	.coloff_bot_c5   	(coloff_bot_c5),
	.writeen_top_c3b 	(writeen_top_c3b),
	.writeen_bot_c3b 	(writeen_bot_c3b),
//	.readen_top_c5   	(readen_top_c5),
//	.readen_bot_c5   	(readen_bot_c5),
	.l1clk           	(l1clk),
	.worden_top_c3b		(worden_top_c3b[3:0]),
	.worden_bot_c3b		(worden_bot_c3b[3:0]),
	.sat_lo0_bc_l		(sat_lo0_bc_l[19:0]),
	.sat_hi0_bc_l		(sat_hi0_bc_l[19:0]),
	.sat_lo1_bc_l		(sat_lo1_bc_l[18:0]),
	.sat_hi1_bc_l		(sat_hi1_bc_l[18:0]),
	.sab_lo0_bc_l		(sab_lo0_bc_l[19:0]),
	.sab_hi0_bc_l		(sab_hi0_bc_l[19:0]),
	.sab_lo1_bc_l		(sab_lo1_bc_l[18:0]),
	.sab_hi1_bc_l		(sab_hi1_bc_l[18:0]),
	.ldin0lo_b		(ldin0lo_b[19:0]),
	.ldin0hi_b		(ldin0hi_b[19:0]),
	.ldin1lo_b		(ldin1lo_b[18:0]),
	.ldin1hi_b		(ldin1hi_b[18:0]),
//	.bnken_lat       	(bnken_lat),
	.ldout0lo_b		(ldout0lo_b00[19:0]),
	.ldout1lo_b		(ldout1lo_b00[18:0]),
	.ldout0hi_b		(ldout0hi_b00[19:0]),
	.ldout1hi_b		(ldout1hi_b00[18:0]),
	.red_d_out_00		(red_d_out_00[9:0]),
	.red_d_in_00    	(fuse_l2d_data_in_00[9:0]),
	.fuse_l2d_rid_00        (fuse_l2d_rid_00[2:0]),
	.fuse_l2d_wren_00       (fuse_l2d_wren_00),
	.fuse_l2d_reset_00_l    (fuse_l2d_reset_00_l),
	.sel_quad_00            (sel_quad_00),
	.red_d_out_01		(red_d_out_01[9:0]),
	.red_top_d_00		(red_top_d_00[9:0]),
	.red_top_d_01		(red_top_d_01[9:0]),
	.red_d_in_01    	(fuse_l2d_data_in_01[9:0]),
	.fuse_l2d_rid_01        (fuse_l2d_rid_01[2:0]),
	.fuse_l2d_wren_01       (fuse_l2d_wren_01),
	.fuse_l2d_reset_01_l    (fuse_l2d_reset_01_l),
	.sel_quad_01            (sel_quad_01),
	.cred			(cred[77:0]),
//        .fuse_l2d_reset_00_l_buf  (fuse_l2d_reset_00_l_buf),
//        .fuse_l2d_reset_01_l_buf  (fuse_l2d_reset_01_l_buf),
	.red_addr_top		(red_addr_top_01),
	.red_addr_bot		(red_addr_bot_00),
  .coloff_c4_l(coloff_c4_l),
  .coloff_top_c3b_l(coloff_top_c3b_l),
  .coloff_bot_c3b_l(coloff_bot_c3b_l)
	);

endmodule


`ifndef SYNTHESIS
module n2_l2d_16kb_cust (
  waysel_c4, 
  waysel_err_c3, 
  set_c3b, 
  coloff_c3b_l, 
  coloff_c4_l, 
  coloff_c5, 
  wen_c3b, 
  readen_c5, 
  worden_c3b, 
  l1clk, 
  wrd_lo0_b_l, 
  wrd_lo1_b_l, 
  wrd_hi0_b_l, 
  wrd_hi1_b_l, 
  red_adr, 
  cred, 
  tstmodclk_l, 
  wee_l, 
  vnw_ary, 
  saout_lo0_bc_l, 
  saout_lo1_bc_l, 
  saout_hi0_bc_l, 
  saout_hi1_bc_l);
wire coloff_c3b_l_unused;
wire bank_select;
wire coloff_c4;
wire [7:0] set_c4;
wire [1:0] spare_word_enable;
wire select_red_odd;
wire select_red_even;

	
input [7:0] 	waysel_c4;		
input		waysel_err_c3;		// 	Active when multiple way sel is on
input [8:0]   	set_c3b;		//	After b-latch
input    	coloff_c3b_l;		//	After b-latch+inv
input    	coloff_c4_l;		//	stage+inv
input [1:0]   	coloff_c5;		//	2-stage
input         	wen_c3b;	 	//	Write-enable, after b-latch
input         	readen_c5;	 	//	
input [3:0]   	worden_c3b;		//	After b-latch
input         	l1clk;	 		//	After l1clk hdr
input [19:0]  	wrd_lo0_b_l;		//	
input [18:0]  	wrd_lo1_b_l;		//	
input [19:0]  	wrd_hi0_b_l;		//	
input [18:0]  	wrd_hi1_b_l;		//	
input [9:0]	red_adr;		// Redudancy address
input [77:0]	cred;			// Redudancy address
input		tstmodclk_l;		//NEW
input		wee_l;			//NEW
input           vnw_ary;                //NEW

//output		bnken_lat;	//	Address latch enable (1.5cycle)
output [19:0]  	saout_lo0_bc_l;		//	C5bc output from senseamp
output [18:0]  	saout_lo1_bc_l;		//	C5bc output from senseamp
output [19:0]  	saout_hi0_bc_l;		//	C5bc output from senseamp
output [18:0]  	saout_hi1_bc_l;		//	C5bc output from senseamp

//reg		rd_data_out_sel_c5b;
//reg select_read_data_c5b;
reg select_read_data_c5b_hi_rgt;
reg select_read_data_c5b_hi_lft;
reg select_read_data_c5b_lo_rgt;
reg select_read_data_c5b_lo_lft;
reg select_read_data_all_c5b;
reg select_read_red_all_c5b;

//reg select_read_red_c5b;
reg select_read_red_c5b_hi_rgt;
reg select_read_red_c5b_hi_lft;
reg select_read_red_c5b_lo_rgt;
reg select_read_red_c5b_lo_lft;

//reg    	bnken_lat;

reg [19:0]    saout_lo0_bc_l;         //      C5bc output from senseamp
reg [18:0]    saout_lo1_bc_l;         //      C5bc output from senseamp
reg [19:0]    saout_hi0_bc_l;         //      C5bc output from senseamp
reg [18:0]    saout_hi1_bc_l;         //      C5bc output from senseamp

reg [79:0]    read_data;
wire [79:0]    rd_data;
wire [79:0]    wr_data;
reg	rd_spare_0,rd_spare_1;
wire    wr_spare_0,wr_spare_1;

wire [19:0] saout_hi0_b_out_l, saout_lo0_b_out_l;
wire [18:0] saout_hi1_b_out_l, saout_lo1_b_out_l;
wire [19:0]     red_lo0_b_out_l;
wire [18:0]     red_lo1_b_out_l;
wire [19:0]     red_hi0_b_out_l;
wire [18:0]     red_hi1_b_out_l;

wire [1:0] coloff_c5_rgt;
wire [1:0] coloff_c5_lft;
wire	   red_sel_rgt;
wire	   red_sel_lft;


reg  [19:0] mem_lo0_way0 [255:0];
reg  [18:0] mem_lo1_way0 [255:0];
reg  [19:0] mem_hi0_way0 [255:0];
reg  [18:0] mem_hi1_way0 [255:0];
reg  [255:0] mem_way0_spare_0;
reg  [255:0] mem_way0_spare_1;

reg  [19:0] mem_lo0_way1 [255:0];
reg  [18:0] mem_lo1_way1 [255:0];
reg  [19:0] mem_hi0_way1 [255:0];
reg  [18:0] mem_hi1_way1 [255:0];
reg  [255:0] mem_way1_spare_0;
reg  [255:0] mem_way1_spare_1;

reg  [19:0] mem_lo0_way2 [255:0];
reg  [18:0] mem_lo1_way2 [255:0];
reg  [19:0] mem_hi0_way2 [255:0];
reg  [18:0] mem_hi1_way2 [255:0];
reg  [255:0] mem_way2_spare_0;
reg  [255:0] mem_way2_spare_1;


reg  [19:0] mem_lo0_way3 [255:0];
reg  [18:0] mem_lo1_way3 [255:0];
reg  [19:0] mem_hi0_way3 [255:0];
reg  [18:0] mem_hi1_way3 [255:0];
reg  [255:0] mem_way3_spare_0;
reg  [255:0] mem_way3_spare_1;


reg  [19:0] mem_lo0_way4 [255:0];
reg  [18:0] mem_lo1_way4 [255:0];
reg  [19:0] mem_hi0_way4 [255:0];
reg  [18:0] mem_hi1_way4 [255:0];
reg  [255:0] mem_way4_spare_0;
reg  [255:0] mem_way4_spare_1;


reg  [19:0] mem_lo0_way5 [255:0];
reg  [18:0] mem_lo1_way5 [255:0];
reg  [19:0] mem_hi0_way5 [255:0];
reg  [18:0] mem_hi1_way5 [255:0];
reg  [255:0] mem_way5_spare_0;
reg  [255:0] mem_way5_spare_1;


reg  [19:0] mem_lo0_way6 [255:0];
reg  [18:0] mem_lo1_way6 [255:0];
reg  [19:0] mem_hi0_way6 [255:0];
reg  [18:0] mem_hi1_way6 [255:0];
reg  [255:0] mem_way6_spare_0;
reg  [255:0] mem_way6_spare_1;


reg  [19:0] mem_lo0_way7 [255:0];
reg  [18:0] mem_lo1_way7 [255:0];
reg  [19:0] mem_hi0_way7 [255:0];
reg  [18:0] mem_hi1_way7 [255:0];
reg  [255:0] mem_way7_spare_0;
reg  [255:0] mem_way7_spare_1;

//reg    	bnken_lat_c52;
reg [19:0]    saout_lo0_bc;         //      C5bc output from senseamp
reg [18:0]    saout_lo1_bc;         //      C5bc output from senseamp
reg [19:0]    saout_hi0_bc;         //      C5bc output from senseamp
reg [18:0]    saout_hi1_bc;         //      C5bc output from senseamp


//reg [19:0]    saout_lo0_bc_d;         //      C5bc output from senseamp
//reg [18:0]    saout_lo1_bc_d;         //      C5bc output from senseamp
//reg [19:0]    saout_hi0_bc_d;         //      C5bc output from senseamp
//reg [18:0]    saout_hi1_bc_d;         //      C5bc output from senseamp

//reg	set_banken_lat, reset_banken_lat;

reg [19:0]       saout_lo0_bc_c5b_l;
reg [18:0]       saout_lo1_bc_c5b_l;
reg [19:0]       saout_hi0_bc_c5b_l;
reg [18:0]       saout_hi1_bc_c5b_l;

reg [19:0]       saout_lo0_bc_d_l;
reg [18:0]       saout_lo1_bc_d_l;
reg [19:0]       saout_hi0_bc_d_l;
reg [18:0]       saout_hi1_bc_d_l;


assign coloff_c3b_l_unused = coloff_c3b_l;


//always@(posedge l1clk)
//begin
//        if(~coloff_c3b_l)
//                set_banken_lat <= 1'b1;
//        else    set_banken_lat <= 1'b0;
//end
//
//always@(negedge l1clk)
//begin
//        if(coloff_c4_l)
//                reset_banken_lat  <= 1'b1;
//        else    reset_banken_lat  <= 1'b0;
//end
//
//always@(set_banken_lat or reset_banken_lat)
//begin
//        if(set_banken_lat )
//                bnken_lat       <=      1'b1;
//        else if(reset_banken_lat )
//                bnken_lat       <=      1'b0;
//end


reg	[7:0] waysel_c5;
reg	[8:0]	index_c4;
reg	[8:0]	set_c5;
reg	wen_c4; 
reg	[3:0]	worden_c4;


reg	bank_select_c5;
reg     waysel_err_c3b, waysel_err_c4,waysel_err_c5;

always@(l1clk or coloff_c4_l)
begin
        if(~l1clk & coloff_c4_l)
	waysel_err_c3b	<=	waysel_err_c3;
end


always@(posedge l1clk)
begin
	waysel_err_c4	<=	waysel_err_c3b;
	waysel_err_c5	<=	waysel_err_c4;
	waysel_c5[7:0]	<=	waysel_c4[7:0];
	index_c4[8:0]	<=	set_c3b[8:0];
	set_c5[8:0]	<=	index_c4[8:0];
	worden_c4[3:0]	<=	worden_c3b[3:0];
	wen_c4		<=	wen_c3b;
	bank_select_c5  <= 	bank_select;
end


assign coloff_c4 = ~coloff_c4_l;
assign bank_select = index_c4[8];

//reg	[19:0]	saout_lo0_bc_c5b;
//reg	[18:0]	saout_lo1_bc_c5b;
//reg	[19:0]	saout_hi0_bc_c5b;
//reg	[18:0]	saout_hi1_bc_c5b;


assign set_c4[7:0] = index_c4[7:0];
wire	[19:0] wrd_lo0_a;
wire	[19:0] wrd_hi0_a;
wire	[18:0] wrd_lo1_a;
wire	[18:0] wrd_hi1_a;

reg	[19:0] wrd_lo0_a_reg;
reg	[19:0] wrd_hi0_a_reg;
reg	[18:0] wrd_lo1_a_reg;
reg	[18:0] wrd_hi1_a_reg;


always@(posedge l1clk)
begin
wrd_lo0_a_reg[19:0] <= ~wrd_lo0_b_l[19:0];
wrd_hi0_a_reg[19:0] <= ~wrd_hi0_b_l[19:0];
wrd_lo1_a_reg[18:0] <= ~wrd_lo1_b_l[18:0];
wrd_hi1_a_reg[18:0] <= ~wrd_hi1_b_l[18:0];
end


// COL redudancy

//reg [255:0] red_reg1;
//reg [255:0] red_reg2;

wire [79:0] cred_mod;


assign cred_mod[79:0] = {cred[77:59],1'b0,cred[58:19],1'b0,cred[18:0]};


//assign spare_word_enable[1] = cred_mod[19] ? worden_c4[3] : worden_c4[2]; 
//assign spare_word_enable[0] = cred_mod[59] ? worden_c4[3] : worden_c4[2];


assign wr_data[19:0] = 
{wr_spare_0,	  wrd_lo1_a_reg[4], wrd_hi0_a_reg[4],wrd_lo0_a_reg[4],
wrd_hi1_a_reg[3], wrd_lo1_a_reg[3], wrd_hi0_a_reg[3],wrd_lo0_a_reg[3],
wrd_hi1_a_reg[2], wrd_lo1_a_reg[2], wrd_hi0_a_reg[2],wrd_lo0_a_reg[2],
wrd_hi1_a_reg[1], wrd_lo1_a_reg[1], wrd_hi0_a_reg[1],wrd_lo0_a_reg[1],
wrd_hi1_a_reg[0], wrd_lo1_a_reg[0], wrd_hi0_a_reg[0],wrd_lo0_a_reg[0]};

assign wr_data[39:20] = {
		  wrd_lo1_a_reg[9], wrd_hi0_a_reg[9],wrd_lo0_a_reg[9],
wrd_hi1_a_reg[8], wrd_lo1_a_reg[8], wrd_hi0_a_reg[8],wrd_lo0_a_reg[8],
wrd_hi1_a_reg[7], wrd_lo1_a_reg[7], wrd_hi0_a_reg[7],wrd_lo0_a_reg[7],
wrd_hi1_a_reg[6], wrd_lo1_a_reg[6], wrd_hi0_a_reg[6],wrd_lo0_a_reg[6],
wrd_hi1_a_reg[5], wrd_lo1_a_reg[5], wrd_hi0_a_reg[5],wrd_lo0_a_reg[5], wrd_hi1_a_reg[4]};


assign wr_data[59:40] = {
wrd_lo1_a_reg[14], wrd_hi0_a_reg[14],wrd_lo0_a_reg[14],
wrd_hi1_a_reg[13], wrd_lo1_a_reg[13], wrd_hi0_a_reg[13],wrd_lo0_a_reg[13],
wrd_hi1_a_reg[12], wrd_lo1_a_reg[12], wrd_hi0_a_reg[12],wrd_lo0_a_reg[12],
wrd_hi1_a_reg[11], wrd_lo1_a_reg[11], wrd_hi0_a_reg[11],wrd_lo0_a_reg[11],
wrd_hi1_a_reg[10], wrd_lo1_a_reg[10], wrd_hi0_a_reg[10],wrd_lo0_a_reg[10], wrd_hi1_a_reg[9]};

assign wr_data[79:60] = {
wrd_hi0_a_reg[19], wrd_lo0_a_reg[19],
wrd_hi1_a_reg[18], wrd_lo1_a_reg[18], wrd_hi0_a_reg[18],wrd_lo0_a_reg[18],
wrd_hi1_a_reg[17], wrd_lo1_a_reg[17], wrd_hi0_a_reg[17],wrd_lo0_a_reg[17],
wrd_hi1_a_reg[16], wrd_lo1_a_reg[16], wrd_hi0_a_reg[16],wrd_lo0_a_reg[16],
wrd_hi1_a_reg[15], wrd_lo1_a_reg[15], wrd_hi0_a_reg[15],wrd_lo0_a_reg[15], wrd_hi1_a_reg[14],wr_spare_1};


integer i; 
reg	[80:0] data;

always@(cred_mod or wr_data)
begin
if (~cred_mod[0]) begin
 data[0] = wr_data[0];
end

for(i=0; i<18; i=i+1)
begin
  data[i+1] = cred_mod[i] ? wr_data[i] : wr_data[i+1];
end

data[19] = cred_mod[18] ? wr_data[18] : cred_mod[20] ? wr_data[20] : 1'b0;

for(i=21;i<40;i=i+1)
begin 
 data[i-1] = cred_mod[i] ? wr_data[i] : wr_data[i-1];
end


if (~cred_mod[39]) begin
 data[39] = wr_data[39];
end

if (~cred_mod[40]) begin
 data[40] = wr_data[40];
end

for(i=40;i<59;i=i+1)
begin
  data[i+1] = cred_mod[i] ? wr_data[i] : wr_data[i+1];
end

data[60] = cred_mod[59] ? wr_data[59] : cred_mod[61] ? wr_data[61] : 1'b0;

for(i=62;i<80;i=i+1)
begin
  data[i-1] = cred_mod[i] ? wr_data[i] : wr_data[i-1];
end

if (~cred_mod[79]) begin
 data[79] = wr_data[79];
end 
 
end

 
assign { wrd_hi0_a[19], wrd_lo0_a[19],
wrd_hi1_a[18], wrd_lo1_a[18], wrd_hi0_a[18],wrd_lo0_a[18],
wrd_hi1_a[17], wrd_lo1_a[17], wrd_hi0_a[17],wrd_lo0_a[17],
wrd_hi1_a[16], wrd_lo1_a[16], wrd_hi0_a[16],wrd_lo0_a[16],
wrd_hi1_a[15], wrd_lo1_a[15], wrd_hi0_a[15],wrd_lo0_a[15], 
wrd_hi1_a[14],wr_spare_1} = data[79:60];

assign {
wrd_lo1_a[14], wrd_hi0_a[14],wrd_lo0_a[14],
wrd_hi1_a[13], wrd_lo1_a[13], wrd_hi0_a[13],wrd_lo0_a[13],
wrd_hi1_a[12], wrd_lo1_a[12], wrd_hi0_a[12],wrd_lo0_a[12],
wrd_hi1_a[11], wrd_lo1_a[11], wrd_hi0_a[11],wrd_lo0_a[11],
wrd_hi1_a[10], wrd_lo1_a[10], wrd_hi0_a[10],wrd_lo0_a[10],wrd_hi1_a[9]} = data[59:40];

assign {
wrd_lo1_a[9], wrd_hi0_a[9],wrd_lo0_a[9],
wrd_hi1_a[8], wrd_lo1_a[8], wrd_hi0_a[8],wrd_lo0_a[8],
wrd_hi1_a[7], wrd_lo1_a[7], wrd_hi0_a[7],wrd_lo0_a[7],
wrd_hi1_a[6], wrd_lo1_a[6], wrd_hi0_a[6],wrd_lo0_a[6],
wrd_hi1_a[5], wrd_lo1_a[5], wrd_hi0_a[5],wrd_lo0_a[5], wrd_hi1_a[4]} = data[39:20];

assign {
wr_spare_0,   wrd_lo1_a[4], wrd_hi0_a[4],wrd_lo0_a[4],
wrd_hi1_a[3], wrd_lo1_a[3], wrd_hi0_a[3],wrd_lo0_a[3],
wrd_hi1_a[2], wrd_lo1_a[2], wrd_hi0_a[2],wrd_lo0_a[2],
wrd_hi1_a[1], wrd_lo1_a[1], wrd_hi0_a[1],wrd_lo0_a[1],
wrd_hi1_a[0], wrd_lo1_a[0], wrd_hi0_a[0],wrd_lo0_a[0]} = data[19:0];


wire [79:0] worden_data;
wire [19:0] worden_lo0;
wire [19:0] worden_hi0;
wire [18:0] worden_lo1;
wire [18:0] worden_hi1;


assign worden_data[19:0] = 
{spare_word_enable[0],  worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0]};

assign worden_data[39:20] = {
	      worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3]};


assign worden_data[59:40] = {
              worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3]};

assign worden_data[79:60] = {
                            worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0],
worden_c4[3], worden_c4[2], worden_c4[1],worden_c4[0], worden_c4[3],spare_word_enable[1]};

reg	[79:0] worden_shift;


always@(cred_mod or worden_data or wen_c4 or coloff_c4)
begin
if (wen_c4 & coloff_c4)
begin
if (~cred_mod[0]) begin
 worden_shift[0] = worden_data[0];
end

for(i=0; i<18; i=i+1)
begin
  worden_shift[i+1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i+1] ? worden_data[i+1] : 1'b0;
end

worden_shift[19] = cred_mod[18] ? worden_data[18] : cred_mod[20] ? worden_data[20] : 1'b0;

for(i=21;i<40;i=i+1)
begin 
 worden_shift[i-1]  = cred_mod[i] ? worden_data[i] : ~cred_mod[i-1] ? worden_data[i-1] : 1'b0;
end


if (~cred_mod[39]) begin
 worden_shift[39] = worden_data[39];
end

if (~cred_mod[40]) begin
 worden_shift[40] = worden_data[40];
end

for(i=40;i<59;i=i+1)
begin
  worden_shift[i+1] = cred_mod[i] ? worden_data[i] : ~cred_mod[i+1] ? worden_data[i+1] : 1'b0;
end

worden_shift[60] = cred_mod[59] ? worden_data[59] : cred_mod[61] ? worden_data[61] : 1'b0;

for(i=62;i<80;i=i+1)
begin
  worden_shift[i-1]  = cred_mod[i] ? worden_data[i] : ~cred_mod[i-1] ? worden_data[i-1] : 1'b0;
end

if (~cred_mod[79]) begin
 worden_shift[79] = worden_data[79];
end 

end
else worden_shift[79:0] = 80'b0;

end
 
 
assign { worden_hi0[19], worden_lo0[19],
worden_hi1[18], worden_lo1[18], worden_hi0[18],worden_lo0[18],
worden_hi1[17], worden_lo1[17], worden_hi0[17],worden_lo0[17],
worden_hi1[16], worden_lo1[16], worden_hi0[16],worden_lo0[16],
worden_hi1[15], worden_lo1[15], worden_hi0[15],worden_lo0[15], 
worden_hi1[14],spare_word_enable[1]} = worden_shift[79:60];

assign {
worden_lo1[14], worden_hi0[14],worden_lo0[14],
worden_hi1[13], worden_lo1[13], worden_hi0[13],worden_lo0[13],
worden_hi1[12], worden_lo1[12], worden_hi0[12],worden_lo0[12],
worden_hi1[11], worden_lo1[11], worden_hi0[11],worden_lo0[11],
worden_hi1[10], worden_lo1[10], worden_hi0[10],worden_lo0[10],worden_hi1[9]} = worden_shift[59:40];

assign {
worden_lo1[9], worden_hi0[9],worden_lo0[9],
worden_hi1[8], worden_lo1[8], worden_hi0[8],worden_lo0[8],
worden_hi1[7], worden_lo1[7], worden_hi0[7],worden_lo0[7],
worden_hi1[6], worden_lo1[6], worden_hi0[6],worden_lo0[6],
worden_hi1[5], worden_lo1[5], worden_hi0[5],worden_lo0[5], worden_hi1[4]} = worden_shift[39:20];

assign {
spare_word_enable[0],   worden_lo1[4], worden_hi0[4],worden_lo0[4],
worden_hi1[3], worden_lo1[3], worden_hi0[3],worden_lo0[3],
worden_hi1[2], worden_lo1[2], worden_hi0[2],worden_lo0[2],
worden_hi1[1], worden_lo1[1], worden_hi0[1],worden_lo0[1],
worden_hi1[0], worden_lo1[0], worden_hi0[0],worden_lo0[0]} = worden_shift[19:0];


always@(l1clk or wen_c4 or set_c4 or waysel_c4 or  waysel_err_c4 or worden_c4 or wrd_lo0_a or 
	wrd_hi0_a or wrd_lo1_a or wrd_hi1_a or coloff_c4 or bank_select  or wr_spare_0 or 
	wr_spare_1 or wee_l or worden_hi0 or worden_lo0 or worden_lo1 or worden_hi1 or spare_word_enable
        or vnw_ary)
begin

////////////////////////////////////////////////////////////////
// Read all entries for a given set 
////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////
//  Write data computation
////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////
// Write to memory
//////////////////////////////////////////////////////////////


    #0


//if(wen_c4  & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4))
if(~l1clk & wee_l & wen_c4  & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary)
begin
	if(waysel_c4[0])
	begin
	mem_lo0_way0[set_c4]   = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way0[set_c4]);
	mem_hi0_way0[set_c4]   = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way0[set_c4]);
	mem_lo1_way0[set_c4]   = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way0[set_c4]);
	mem_hi1_way0[set_c4]   = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way0[set_c4]);
	mem_way0_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way0_spare_0[set_c4]);
	mem_way0_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way0_spare_1[set_c4]);
	end
	else if(waysel_c4[1])
	begin
	mem_lo0_way1[set_c4]   =  (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way1[set_c4]);
	mem_hi0_way1[set_c4]   =  (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way1[set_c4]);
	mem_lo1_way1[set_c4]   =  (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way1[set_c4]);
	mem_hi1_way1[set_c4]   =  (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way1[set_c4]);
	mem_way1_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way1_spare_0[set_c4]);
	mem_way1_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way1_spare_1[set_c4]);
	end
	else if(waysel_c4[2])
	begin
	mem_lo0_way2[set_c4]   =  (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way2[set_c4]);
	mem_lo1_way2[set_c4]   =  (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way2[set_c4]);
	mem_hi0_way2[set_c4]   =  (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way2[set_c4]);
	mem_hi1_way2[set_c4]   =  (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way2[set_c4]);
	mem_way2_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way2_spare_0[set_c4]);
	mem_way2_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way2_spare_1[set_c4]);
	end
	else if(waysel_c4[3])
	begin
	mem_lo0_way3[set_c4]   = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way3[set_c4]);
	mem_lo1_way3[set_c4]   = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way3[set_c4]);
	mem_hi0_way3[set_c4]   = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way3[set_c4]);
	mem_hi1_way3[set_c4]   = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way3[set_c4]);
	mem_way3_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way3_spare_0[set_c4]);
	mem_way3_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way3_spare_1[set_c4]);
	end
	else if(waysel_c4[4])
	begin
	mem_lo0_way4[set_c4]   = (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way4[set_c4]);
	mem_lo1_way4[set_c4]   = (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way4[set_c4]);
	mem_hi0_way4[set_c4]   = (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way4[set_c4]);
	mem_hi1_way4[set_c4]   = (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way4[set_c4]);
	mem_way4_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way4_spare_0[set_c4]);
	mem_way4_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way4_spare_1[set_c4]);
	end
	else if(waysel_c4[5])
	begin
	mem_lo0_way5[set_c4]   =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way5[set_c4]);
	mem_lo1_way5[set_c4]   =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way5[set_c4]);
	mem_hi0_way5[set_c4]   =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way5[set_c4]);
	mem_hi1_way5[set_c4]   =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way5[set_c4]);
	mem_way5_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way5_spare_0[set_c4]);
	mem_way5_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way5_spare_1[set_c4]);
	end
	else if(waysel_c4[6])
	begin
	mem_lo0_way6[set_c4]   =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way6[set_c4]);
	mem_lo1_way6[set_c4]   =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way6[set_c4]);
	mem_hi0_way6[set_c4]   =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way6[set_c4]);
	mem_hi1_way6[set_c4]   =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way6[set_c4]);
	mem_way6_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way6_spare_0[set_c4]);
	mem_way6_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way6_spare_1[set_c4]);
	end
	else if(waysel_c4[7])
	begin
	mem_lo0_way7[set_c4]   =(worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & mem_lo0_way7[set_c4]);
	mem_lo1_way7[set_c4]   =(worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & mem_lo1_way7[set_c4]);
	mem_hi0_way7[set_c4]   =(worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & mem_hi0_way7[set_c4]);
	mem_hi1_way7[set_c4]   =(worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & mem_hi1_way7[set_c4]);
	mem_way7_spare_0[set_c4] = (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & mem_way7_spare_0[set_c4]);
	mem_way7_spare_1[set_c4] = (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & mem_way7_spare_1[set_c4]);
	end
  end
end

//always@(waysel_c4 or set_c4 or bnken_lat )
always@(waysel_c4 or set_c4 or coloff_c4_l or vnw_ary)

begin


    #0

if(~coloff_c4_l & vnw_ary)
begin
	if(waysel_c4[0])
		begin
		saout_lo0_bc[19:0]	<=	mem_lo0_way0[set_c4];
		saout_lo1_bc[18:0]	<=	mem_lo1_way0[set_c4];
		saout_hi0_bc[19:0]	<=	mem_hi0_way0[set_c4];
		saout_hi1_bc[18:0]	<=	mem_hi1_way0[set_c4];
 		rd_spare_0		<=	mem_way0_spare_0[set_c4];
 		rd_spare_1		<=	mem_way0_spare_1[set_c4];
		end
	else if(waysel_c4[1])
		begin
		saout_lo0_bc[19:0]	<=	mem_lo0_way1[set_c4];	
		saout_lo1_bc[18:0]	<=	mem_lo1_way1[set_c4];	
		saout_hi0_bc[19:0]	<=	mem_hi0_way1[set_c4];	
		saout_hi1_bc[18:0]	<=	mem_hi1_way1[set_c4];	
 		rd_spare_0		<=	mem_way1_spare_0[set_c4];
 		rd_spare_1		<=	mem_way1_spare_1[set_c4];
		end
	else if(waysel_c4[2])
		begin
		saout_lo0_bc[19:0]	<=	mem_lo0_way2[set_c4];	
		saout_lo1_bc[18:0]	<=	mem_lo1_way2[set_c4];	
		saout_hi0_bc[19:0]	<=	mem_hi0_way2[set_c4];	
		saout_hi1_bc[18:0]	<=	mem_hi1_way2[set_c4];	
 		rd_spare_0		<=	mem_way2_spare_0[set_c4];
 		rd_spare_1		<=	mem_way2_spare_1[set_c4];
		end
	else if(waysel_c4[3])
		begin
		saout_lo0_bc[19:0]	<=	mem_lo0_way3[set_c4];	
		saout_lo1_bc[18:0]	<=	mem_lo1_way3[set_c4];	
		saout_hi0_bc[19:0]	<=	mem_hi0_way3[set_c4];	
		saout_hi1_bc[18:0]	<=	mem_hi1_way3[set_c4];	
 		rd_spare_0		<=	mem_way3_spare_0[set_c4];
 		rd_spare_1		<=	mem_way3_spare_1[set_c4];
		end
	else if(waysel_c4[4])
		begin
		saout_lo0_bc[19:0]	<=	mem_lo0_way4[set_c4];	
		saout_lo1_bc[18:0]	<=	mem_lo1_way4[set_c4];	
		saout_hi0_bc[19:0]	<=	mem_hi0_way4[set_c4];	
		saout_hi1_bc[18:0]	<=	mem_hi1_way4[set_c4];	
 		rd_spare_0		<=	mem_way4_spare_0[set_c4];
 		rd_spare_1		<=	mem_way4_spare_1[set_c4];
		end
	else if(waysel_c4[5])
		begin
		saout_lo0_bc[19:0]	<=	mem_lo0_way5[set_c4];
		saout_lo1_bc[18:0]	<=	mem_lo1_way5[set_c4];
		saout_hi0_bc[19:0]	<=	mem_hi0_way5[set_c4];
		saout_hi1_bc[18:0]	<=	mem_hi1_way5[set_c4];
 		rd_spare_0		<=	mem_way5_spare_0[set_c4];
 		rd_spare_1		<=	mem_way5_spare_1[set_c4];
		end
	else if(waysel_c4[6])
		begin
		saout_lo0_bc[19:0]	<=	mem_lo0_way6[set_c4];	
		saout_lo1_bc[18:0]	<=	mem_lo1_way6[set_c4];	
		saout_hi0_bc[19:0]	<=	mem_hi0_way6[set_c4];	
		saout_hi1_bc[18:0]	<=	mem_hi1_way6[set_c4];	
 		rd_spare_0		<=	mem_way6_spare_0[set_c4];
 		rd_spare_1		<=	mem_way6_spare_1[set_c4];
		end
	else if(waysel_c4[7])
		begin
	        saout_lo0_bc[19:0]    	<=	mem_lo0_way7[set_c4];      
	        saout_lo1_bc[18:0]    	<=	mem_lo1_way7[set_c4];      
	        saout_hi0_bc[19:0]    	<=	mem_hi0_way7[set_c4];      
	        saout_hi1_bc[18:0]    	<=	mem_hi1_way7[set_c4];      
 		rd_spare_0		<=	mem_way7_spare_0[set_c4];
 		rd_spare_1		<=	mem_way7_spare_1[set_c4];
		end
end
end


// READ
// Data is read out of the above array in c4 and gets registered and latched
// to become a c5b signal which gets muxed and goes to dmux


reg rd_spare_0_d_l,rd_spare_1_d_l;
reg rdd_spare_0,rdd_spare_1;
reg tstmodclk_c3b_l;
always@(posedge l1clk)
begin
	saout_lo0_bc_d_l[19:0] <= ~saout_lo0_bc[19:0];
	saout_lo1_bc_d_l[18:0] <= ~saout_lo1_bc[18:0];
	saout_hi0_bc_d_l[19:0] <= ~saout_hi0_bc[19:0];
	saout_hi1_bc_d_l[18:0] <= ~saout_hi1_bc[18:0];
	rd_spare_0_d_l         <= ~rd_spare_0;
	rd_spare_1_d_l         <= ~rd_spare_1;
end

always@(negedge l1clk)
begin
        saout_lo0_bc_c5b_l[19:0] <= saout_lo0_bc_d_l[19:0];
        saout_lo1_bc_c5b_l[18:0] <= saout_lo1_bc_d_l[18:0];
        saout_hi0_bc_c5b_l[19:0] <= saout_hi0_bc_d_l[19:0];
        saout_hi1_bc_c5b_l[18:0] <= saout_hi1_bc_d_l[18:0];
	rdd_spare_0		 <= rd_spare_0_d_l;
	rdd_spare_1		 <= rd_spare_1_d_l;
	tstmodclk_c3b_l		 <= tstmodclk_l;
end


assign rd_data[19:0] =
	{rdd_spare_0,      saout_lo1_bc_c5b_l[4], saout_hi0_bc_c5b_l[4],saout_lo0_bc_c5b_l[4],
	saout_hi1_bc_c5b_l[3], saout_lo1_bc_c5b_l[3], saout_hi0_bc_c5b_l[3],saout_lo0_bc_c5b_l[3],
	saout_hi1_bc_c5b_l[2], saout_lo1_bc_c5b_l[2], saout_hi0_bc_c5b_l[2],saout_lo0_bc_c5b_l[2],
	saout_hi1_bc_c5b_l[1], saout_lo1_bc_c5b_l[1], saout_hi0_bc_c5b_l[1],saout_lo0_bc_c5b_l[1],
	saout_hi1_bc_c5b_l[0], saout_lo1_bc_c5b_l[0], saout_hi0_bc_c5b_l[0],saout_lo0_bc_c5b_l[0]};

	assign rd_data[39:20] = {
			  saout_lo1_bc_c5b_l[9], saout_hi0_bc_c5b_l[9],saout_lo0_bc_c5b_l[9],
	saout_hi1_bc_c5b_l[8], saout_lo1_bc_c5b_l[8], saout_hi0_bc_c5b_l[8],saout_lo0_bc_c5b_l[8],
	saout_hi1_bc_c5b_l[7], saout_lo1_bc_c5b_l[7], saout_hi0_bc_c5b_l[7],saout_lo0_bc_c5b_l[7],
	saout_hi1_bc_c5b_l[6], saout_lo1_bc_c5b_l[6], saout_hi0_bc_c5b_l[6],saout_lo0_bc_c5b_l[6],
	saout_hi1_bc_c5b_l[5], saout_lo1_bc_c5b_l[5], saout_hi0_bc_c5b_l[5],saout_lo0_bc_c5b_l[5], saout_hi1_bc_c5b_l[4]};


	assign rd_data[59:40] = {
	saout_lo1_bc_c5b_l[14], saout_hi0_bc_c5b_l[14],saout_lo0_bc_c5b_l[14],
	saout_hi1_bc_c5b_l[13], saout_lo1_bc_c5b_l[13], saout_hi0_bc_c5b_l[13],saout_lo0_bc_c5b_l[13],
	saout_hi1_bc_c5b_l[12], saout_lo1_bc_c5b_l[12], saout_hi0_bc_c5b_l[12],saout_lo0_bc_c5b_l[12],
	saout_hi1_bc_c5b_l[11], saout_lo1_bc_c5b_l[11], saout_hi0_bc_c5b_l[11],saout_lo0_bc_c5b_l[11],
	saout_hi1_bc_c5b_l[10], saout_lo1_bc_c5b_l[10], saout_hi0_bc_c5b_l[10],saout_lo0_bc_c5b_l[10], saout_hi1_bc_c5b_l[9]};

	assign rd_data[79:60] = {
	saout_hi0_bc_c5b_l[19], saout_lo0_bc_c5b_l[19],
	saout_hi1_bc_c5b_l[18], saout_lo1_bc_c5b_l[18], saout_hi0_bc_c5b_l[18],saout_lo0_bc_c5b_l[18],
	saout_hi1_bc_c5b_l[17], saout_lo1_bc_c5b_l[17], saout_hi0_bc_c5b_l[17],saout_lo0_bc_c5b_l[17],
	saout_hi1_bc_c5b_l[16], saout_lo1_bc_c5b_l[16], saout_hi0_bc_c5b_l[16],saout_lo0_bc_c5b_l[16],
	saout_hi1_bc_c5b_l[15], saout_lo1_bc_c5b_l[15], saout_hi0_bc_c5b_l[15],saout_lo0_bc_c5b_l[15], saout_hi1_bc_c5b_l[14],rdd_spare_1};


	always@(cred_mod or rd_data)
	begin
	
	for(i=0;i<19;i=i+1)
	begin
	read_data[i] = cred_mod[i] ? rd_data[i+1] : rd_data[i];
        end
	
	for(i=20;i<40;i=i+1)
        begin
	read_data[i] = cred_mod[i] ? rd_data[i-1] : rd_data[i];
        end
	

	for(i=40;i<60;i=i+1)
	 begin
	 read_data[i] = cred_mod[i] ? rd_data[i+1] : rd_data[i];
         end
	 
	for(i=61;i<80;i=i+1)
         begin
	 read_data[i] = cred_mod[i] ? rd_data[i-1] : rd_data[i];
         end
	
	end 


	assign { saout_hi0_b_out_l[19], saout_lo0_b_out_l[19],
        saout_hi1_b_out_l[18], saout_lo1_b_out_l[18], saout_hi0_b_out_l[18],saout_lo0_b_out_l[18],
        saout_hi1_b_out_l[17], saout_lo1_b_out_l[17], saout_hi0_b_out_l[17],saout_lo0_b_out_l[17],
        saout_hi1_b_out_l[16], saout_lo1_b_out_l[16], saout_hi0_b_out_l[16],saout_lo0_b_out_l[16],
        saout_hi1_b_out_l[15], saout_lo1_b_out_l[15], saout_hi0_b_out_l[15],saout_lo0_b_out_l[15], 
	saout_hi1_b_out_l[14]} = read_data[79:61];
         
        assign {saout_lo1_b_out_l[14], saout_hi0_b_out_l[14],saout_lo0_b_out_l[14],
        saout_hi1_b_out_l[13], saout_lo1_b_out_l[13], saout_hi0_b_out_l[13],saout_lo0_b_out_l[13],
        saout_hi1_b_out_l[12], saout_lo1_b_out_l[12], saout_hi0_b_out_l[12],saout_lo0_b_out_l[12],
        saout_hi1_b_out_l[11], saout_lo1_b_out_l[11], saout_hi0_b_out_l[11],saout_lo0_b_out_l[11],
        saout_hi1_b_out_l[10], saout_lo1_b_out_l[10], saout_hi0_b_out_l[10],saout_lo0_b_out_l[10], 
	saout_hi1_b_out_l[9]} = read_data[59:40];

        assign { saout_lo1_b_out_l[9], saout_hi0_b_out_l[9],saout_lo0_b_out_l[9],
        saout_hi1_b_out_l[8], saout_lo1_b_out_l[8], saout_hi0_b_out_l[8],saout_lo0_b_out_l[8],
        saout_hi1_b_out_l[7], saout_lo1_b_out_l[7], saout_hi0_b_out_l[7],saout_lo0_b_out_l[7],
        saout_hi1_b_out_l[6], saout_lo1_b_out_l[6], saout_hi0_b_out_l[6],saout_lo0_b_out_l[6],
        saout_hi1_b_out_l[5], saout_lo1_b_out_l[5], saout_hi0_b_out_l[5],saout_lo0_b_out_l[5], 
	saout_hi1_b_out_l[4]} = read_data[39:20];

        assign {saout_lo1_b_out_l[4], saout_hi0_b_out_l[4],saout_lo0_b_out_l[4],
        saout_hi1_b_out_l[3], saout_lo1_b_out_l[3], saout_hi0_b_out_l[3],saout_lo0_b_out_l[3],
        saout_hi1_b_out_l[2], saout_lo1_b_out_l[2], saout_hi0_b_out_l[2],saout_lo0_b_out_l[2],
        saout_hi1_b_out_l[1], saout_lo1_b_out_l[1], saout_hi0_b_out_l[1],saout_lo0_b_out_l[1],
        saout_hi1_b_out_l[0], saout_lo1_b_out_l[0], saout_hi0_b_out_l[0],saout_lo0_b_out_l[0]} = read_data[18:0];

assign red_sel_rgt = |cred[19:18];
assign red_sel_lft = |cred[59:58];

assign coloff_c5_rgt[1] = coloff_c5[1] | red_sel_rgt & coloff_c5[0];
assign coloff_c5_rgt[0] = coloff_c5[0] | red_sel_rgt & coloff_c5[1];
assign coloff_c5_lft[1] = coloff_c5[1] | red_sel_lft & coloff_c5[0];
assign coloff_c5_lft[0] = coloff_c5[0] | red_sel_lft & coloff_c5[1];


always@(negedge l1clk)
begin
select_read_data_all_c5b <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5) & (|coloff_c5) & readen_c5 & wee_l & ~waysel_err_c4);
select_read_red_all_c5b  <=(bank_select_c5 &  (select_red_odd | select_red_even) & (|waysel_c5) & (|coloff_c5) & readen_c5 & wee_l & ~waysel_err_c4);
 
select_read_data_c5b_hi_rgt <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5)  & wee_l) & 
                               (readen_c5 & coloff_c5_rgt[1] & ~waysel_err_c5);
select_read_data_c5b_hi_lft <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5)  & wee_l) & 
                               (readen_c5 & coloff_c5_lft[1] & ~waysel_err_c5);
select_read_data_c5b_lo_rgt <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5)  & wee_l) & 
                               (readen_c5 & coloff_c5_rgt[0] & ~waysel_err_c5);
select_read_data_c5b_lo_lft <= (bank_select_c5 & ~(select_red_odd | select_red_even) & (|waysel_c5)  & wee_l) & 
                               (readen_c5 & coloff_c5_lft[0] & ~waysel_err_c5);
select_read_red_c5b_hi_rgt  <=(bank_select_c5 &  (select_red_odd | select_red_even) & (|waysel_c5)  & wee_l) & 
                               (readen_c5 & coloff_c5_rgt[1] & ~waysel_err_c5);
select_read_red_c5b_hi_lft  <=(bank_select_c5 &  (select_red_odd | select_red_even) & (|waysel_c5)  & wee_l) & 
                               (readen_c5 & coloff_c5_lft[1] & ~waysel_err_c5);
select_read_red_c5b_lo_rgt  <=(bank_select_c5 &  (select_red_odd | select_red_even) & (|waysel_c5)  & wee_l) & 
                               (readen_c5 & coloff_c5_rgt[0] & ~waysel_err_c5);
select_read_red_c5b_lo_lft  <=(bank_select_c5 &  (select_red_odd | select_red_even) & (|waysel_c5)  & wee_l) & 
                               (readen_c5 & coloff_c5_lft[0] & ~waysel_err_c5);
end


//assign saout_lo0_bc_l[19:0] = select_read_data_c5b ? saout_lo0_bc_c5b_l[19:0] : 
//			      select_read_red_c5b ? red_lo0_out[19:0] : 20'hFFFFF;
//assign saout_lo1_bc_l[18:0] = select_read_data_c5b ? saout_lo1_bc_c5b_l[18:0] : 
//			      select_read_red_c5b ? red_lo1_out[18:0] : 19'h7FFFF;
//assign saout_hi0_bc_l[19:0] = select_read_data_c5b ? saout_hi0_bc_c5b_l[19:0] : 
//			      select_read_red_c5b ? red_hi0_out[19:0] : 20'hFFFFF;
//assign saout_hi1_bc_l[18:0] = select_read_data_c5b ? saout_hi1_bc_c5b_l[18:0] : 
//			      select_read_red_c5b ? red_hi1_out[18:0] : 19'h7FFFF;
//
always@(select_read_red_c5b_lo_rgt or select_read_red_c5b_lo_lft or select_read_red_c5b_hi_rgt or select_read_red_c5b_hi_lft or
	select_read_data_c5b_lo_rgt or select_read_data_c5b_lo_lft or select_read_data_c5b_hi_rgt or select_read_data_c5b_hi_lft
      or red_lo0_b_out_l or red_hi0_b_out_l or red_lo1_b_out_l or saout_hi1_b_out_l 
      or saout_lo0_b_out_l or red_hi0_b_out_l or saout_lo1_b_out_l or saout_hi1_b_out_l or tstmodclk_c3b_l or l1clk)
begin

if(tstmodclk_c3b_l)
begin
saout_lo0_bc_l[9:0]   = select_read_red_c5b_lo_rgt  ? red_lo0_b_out_l[9:0]     : 
		      select_read_data_c5b_lo_rgt ? saout_lo0_b_out_l[9:0]   : 10'h3FF;
saout_lo0_bc_l[19:10] = select_read_red_c5b_lo_lft  ? red_lo0_b_out_l[19:10]   : 
		      select_read_data_c5b_lo_lft ? saout_lo0_b_out_l[19:10] : 10'h3FF;
saout_hi0_bc_l[9:0]   = select_read_red_c5b_lo_rgt  ? red_hi0_b_out_l[9:0]     : 
		      select_read_data_c5b_lo_rgt ? saout_hi0_b_out_l[9:0]   : 10'h3FF;
saout_hi0_bc_l[19:10] = select_read_red_c5b_lo_lft  ? red_hi0_b_out_l[19:10]   : 
		      select_read_data_c5b_lo_lft ? saout_hi0_b_out_l[19:10] : 10'h3FF;
saout_lo1_bc_l[9:0]   = select_read_red_c5b_hi_rgt  ? red_lo1_b_out_l[9:0]     : 
		      select_read_data_c5b_hi_rgt ? saout_lo1_b_out_l[9:0]   : 10'h3FF;
saout_lo1_bc_l[18:10] = select_read_red_c5b_hi_lft  ? red_lo1_b_out_l[18:10]   : 
		      select_read_data_c5b_hi_lft ? saout_lo1_b_out_l[18:10] : 9'h1FF;
saout_hi1_bc_l[8:0]   = select_read_red_c5b_hi_rgt  ? red_hi1_b_out_l[8:0]     : 
		      select_read_data_c5b_hi_rgt ? saout_hi1_b_out_l[8:0]   : 9'h1FF;
saout_hi1_bc_l[18:9]  = select_read_red_c5b_hi_lft  ? red_hi1_b_out_l[18:9]    : 
		      select_read_data_c5b_hi_lft ? saout_hi1_b_out_l[18:9]  : 10'h3FF;
end
else
begin
saout_lo0_bc_l[19:0] = select_read_red_all_c5b  ? red_lo0_b_out_l[19:0]   : 
 		       select_read_data_all_c5b ? saout_lo0_b_out_l[19:0] : 20'bx;
saout_hi0_bc_l[19:0] = select_read_red_all_c5b  ? red_hi0_b_out_l[19:0]   : 
 		       select_read_data_all_c5b ? saout_hi0_b_out_l[19:0] : 20'bx;
saout_lo1_bc_l[18:0] = select_read_red_all_c5b  ? red_lo1_b_out_l[18:0]   : 
 		       select_read_data_all_c5b ? saout_lo1_b_out_l[18:0] : 19'bx;
saout_hi1_bc_l[18:0] = select_read_red_all_c5b  ? red_hi1_b_out_l[18:0]   : 
		       select_read_data_all_c5b ? saout_hi1_b_out_l[18:0] : 19'bx;
		       
//saout_lo0_bc_l[19:0] = select_read_data_all_c5b ? saout_lo0_bc_c5b_l[19:0] : 20'hFFFFF;
//saout_lo1_bc_l[18:0] = select_read_data_all_c5b ? saout_lo1_bc_c5b_l[18:0] : 19'hFFFFF;
//saout_hi0_bc_l[19:0] = select_read_data_all_c5b ? saout_hi0_bc_c5b_l[19:0] : 20'hFFFFF;
//saout_hi1_bc_l[18:0] = select_read_data_all_c5b ? saout_hi1_bc_c5b_l[18:0] : 19'hFFFFF;
end
end


//assign repair_saout_lo0_bc_l[9:0]   = 
//select_read_red_c5b_lo_rgt  ? red_lo0_b_out_l[9:0]     : select_read_data_c5b_lo_rgt ? saout_lo0_b_out_l[9:0]   : 10'h3FF ;
//assign repair_saout_lo0_bc_l[19:10] = 
//select_read_red_c5b_lo_lft  ? red_lo0_b_out_l[19:10]   : select_read_data_c5b_lo_lft ? saout_lo0_b_out_l[19:10] : 10'h3FF ;
//assign repair_saout_hi0_bc_l[9:0]   = 
//select_read_red_c5b_lo_rgt  ? red_hi0_b_out_l[9:0]     : select_read_data_c5b_lo_rgt ? saout_hi0_b_out_l[9:0]   : 10'h3FF ;
//assign repair_saout_hi0_bc_l[19:10] = 
//select_read_red_c5b_lo_lft  ? red_hi0_b_out_l[19:10]   : select_read_data_c5b_lo_lft ? saout_hi0_b_out_l[19:10] : 10'h3FF ;
//assign repair_saout_lo1_bc_l[9:0]   = 
//select_read_red_c5b_hi_rgt  ? red_lo1_b_out_l[9:0]     : select_read_data_c5b_hi_rgt ? saout_lo1_b_out_l[9:0]   : 10'h3FF ;
//assign repair_saout_lo1_bc_l[18:10] = 
//select_read_red_c5b_hi_lft  ? red_lo1_b_out_l[18:10]   : select_read_data_c5b_hi_lft ? saout_lo1_b_out_l[18:10] : 9'h1FF ;
//assign repair_saout_hi1_bc_l[8:0]   = 
//select_read_red_c5b_hi_rgt  ? red_hi1_b_out_l[8:0]     : select_read_data_c5b_hi_rgt ? saout_hi1_b_out_l[8:0]   : 9'h1FF ;
//assign repair_saout_hi1_bc_l[18:9]  = 
//select_read_red_c5b_hi_lft  ? red_hi1_b_out_l[18:9]    : select_read_data_c5b_hi_lft ? saout_hi1_b_out_l[18:9]  : 10'h3FF ;
//
//
//assign norepair_saout_lo0_bc_l[19:0] = select_read_data_all_c5b ? saout_lo0_bc_c5b_l[19:0] : 20'hFFFFF;
//assign norepair_saout_lo1_bc_l[18:0] = select_read_data_all_c5b ? saout_lo1_bc_c5b_l[18:0] : 19'hFFFFF;
//assign norepair_saout_hi0_bc_l[19:0] = select_read_data_all_c5b ? saout_hi0_bc_c5b_l[19:0] : 20'hFFFFF;
//assign norepair_saout_hi1_bc_l[18:0] = select_read_data_all_c5b ? saout_hi1_bc_c5b_l[18:0] : 19'hFFFFF;
//
//`endif
//
//`ifdef AXIS_SMEM
//
//	always@(negedge l1clk)  
//	begin
//        axis_saout_lo0_bc[19:0]  = saout_lo0_bc[19:0];
//        axis_saout_lo1_bc[18:0]  = saout_lo1_bc[18:0];
//        axis_saout_hi0_bc[19:0]  = saout_hi0_bc[19:0];
//        axis_saout_hi1_bc[18:0]  = saout_hi1_bc[18:0];
//	end
//	assign saout_lo0_bc_l[19:0] = axis_select_read_data_c5b ? axis_saout_lo0_bc[19:0] : 20'hFFFFF;
//	assign saout_lo1_bc_l[18:0] = axis_select_read_data_c5b ? axis_saout_lo1_bc[18:0] : 19'h7FFFF;
//	assign saout_hi0_bc_l[19:0] = axis_select_read_data_c5b ? axis_saout_hi0_bc[19:0] : 20'hFFFFF;
//	assign saout_hi1_bc_l[18:0] = axis_select_read_data_c5b ? axis_saout_hi1_bc[18:0] : 19'h7FFFF;
//
//`else
//assign saout_lo0_bc_l[19:0] = ~tstmodclk_c3b_l ? repair_saout_lo0_bc_l[19:0] : norepair_saout_lo0_bc_l[19:0];
//assign saout_lo1_bc_l[18:0] = ~tstmodclk_c3b_l ? repair_saout_lo1_bc_l[18:0] : norepair_saout_lo1_bc_l[18:0];
//assign saout_hi0_bc_l[19:0] = ~tstmodclk_c3b_l ? repair_saout_hi0_bc_l[19:0] : norepair_saout_hi0_bc_l[19:0];
//assign saout_hi1_bc_l[18:0] = ~tstmodclk_c3b_l ? repair_saout_hi1_bc_l[18:0] : norepair_saout_hi1_bc_l[18:0];

///////////////////////////////////////////////////////////////////////////////////////////////

// REDUDANCY

reg [19:0]    red_lo0_odd_0;         
reg [18:0]    red_lo1_odd_0;         
reg [19:0]    red_hi0_odd_0;         
reg [18:0]    red_hi1_odd_0;         
reg [19:0]    red_lo0_even_0;
reg [18:0]    red_lo1_even_0;
reg [19:0]    red_hi0_even_0;
reg [18:0]    red_hi1_even_0;
reg	      redrow_way0_spare_odd_0;
reg	      redrow_way0_spare_even_0;
reg	      redrow_way0_spare_odd_1;
reg	      redrow_way0_spare_even_1;

reg [19:0]    red_lo0_odd_1;
reg [18:0]    red_lo1_odd_1;
reg [19:0]    red_hi0_odd_1;
reg [18:0]    red_hi1_odd_1;
reg [19:0]    red_lo0_even_1;
reg [18:0]    red_lo1_even_1;
reg [19:0]    red_hi0_even_1;
reg [18:0]    red_hi1_even_1;
reg	      redrow_way1_spare_odd_0;
reg	      redrow_way1_spare_even_0;
reg	      redrow_way1_spare_odd_1;
reg	      redrow_way1_spare_even_1;

reg [19:0]    red_lo0_odd_2;
reg [18:0]    red_lo1_odd_2;
reg [19:0]    red_hi0_odd_2;
reg [18:0]    red_hi1_odd_2;
reg [19:0]    red_lo0_even_2;
reg [18:0]    red_lo1_even_2;
reg [19:0]    red_hi0_even_2;
reg [18:0]    red_hi1_even_2;
reg	      redrow_way2_spare_odd_0;
reg	      redrow_way2_spare_even_0;
reg	      redrow_way2_spare_odd_1;
reg	      redrow_way2_spare_even_1;

reg [19:0]    red_lo0_odd_3;
reg [18:0]    red_lo1_odd_3;
reg [19:0]    red_hi0_odd_3;
reg [18:0]    red_hi1_odd_3;
reg [19:0]    red_lo0_even_3;
reg [18:0]    red_lo1_even_3;
reg [19:0]    red_hi0_even_3;
reg [18:0]    red_hi1_even_3;
reg	      redrow_way3_spare_odd_0;
reg	      redrow_way3_spare_even_0;
reg	      redrow_way3_spare_odd_1;
reg	      redrow_way3_spare_even_1;

reg [19:0]    red_lo0_odd_4;
reg [18:0]    red_lo1_odd_4;
reg [19:0]    red_hi0_odd_4;
reg [18:0]    red_hi1_odd_4;
reg [19:0]    red_lo0_even_4;
reg [18:0]    red_lo1_even_4;
reg [19:0]    red_hi0_even_4;
reg [18:0]    red_hi1_even_4;
reg	      redrow_way4_spare_odd_0;
reg	      redrow_way4_spare_even_0;
reg	      redrow_way4_spare_odd_1;
reg	      redrow_way4_spare_even_1;

reg [19:0]    red_lo0_odd_5;
reg [18:0]    red_lo1_odd_5;
reg [19:0]    red_hi0_odd_5;
reg [18:0]    red_hi1_odd_5;
reg [19:0]    red_lo0_even_5;
reg [18:0]    red_lo1_even_5;
reg [19:0]    red_hi0_even_5;
reg [18:0]    red_hi1_even_5;
reg	      redrow_way5_spare_odd_0;
reg	      redrow_way5_spare_even_0;
reg	      redrow_way5_spare_odd_1;
reg	      redrow_way5_spare_even_1;

reg [19:0]    red_lo0_odd_6;
reg [18:0]    red_lo1_odd_6;
reg [19:0]    red_hi0_odd_6;
reg [18:0]    red_hi1_odd_6;
reg [19:0]    red_lo0_even_6;
reg [18:0]    red_lo1_even_6;
reg [19:0]    red_hi0_even_6;
reg [18:0]    red_hi1_even_6;
reg	      redrow_way6_spare_odd_0;
reg	      redrow_way6_spare_even_0;
reg	      redrow_way6_spare_odd_1;
reg	      redrow_way6_spare_even_1;

reg [19:0]    red_lo0_odd_7;
reg [18:0]    red_lo1_odd_7;
reg [19:0]    red_hi0_odd_7;
reg [18:0]    red_hi1_odd_7;
reg [19:0]    red_lo0_even_7;
reg [18:0]    red_lo1_even_7;
reg [19:0]    red_hi0_even_7;
reg [18:0]    red_hi1_even_7;
reg	      redrow_way7_spare_odd_0;
reg	      redrow_way7_spare_even_0;
reg	      redrow_way7_spare_odd_1;
reg	      redrow_way7_spare_even_1;


reg [19:0]     red_lo0_out_bc;
reg [18:0]     red_lo1_out_bc;
reg [19:0]     red_hi0_out_bc;
reg [18:0]     red_hi1_out_bc;
reg            redrow_rd_spare_0;
reg            redrow_rd_spare_1;

reg [19:0]     red_lo0_out_bc_d_l;
reg [18:0]     red_lo1_out_bc_d_l;
reg [19:0]     red_hi0_out_bc_d_l;
reg [18:0]     red_hi1_out_bc_d_l;
reg	       redrow_rd_spare_0_d_l;
reg	       redrow_rd_spare_1_d_l;

reg [19:0]     red_lo0_bc_c5b_l;
reg [19:0]     red_hi0_bc_c5b_l;
reg [18:0]     red_lo1_bc_c5b_l;
reg [18:0]     red_hi1_bc_c5b_l;
reg	       redrow_rdd_spare_0;
reg	       redrow_rdd_spare_1;

wire [79:0]    red_rd_data;
reg [79:0]    red_read_data;

// Folloing 2 assigns detects a red index to hit with incoming index
// and assert.  While writing and reading the way info is looked at

assign select_red_odd = (red_adr[9:8] == 2'b11) & (red_adr[7:1] == set_c3b[7:1]) 
				& set_c3b[0]  & red_adr[0];
assign select_red_even = (red_adr[9:8] == 2'b11) & (red_adr[7:1] == set_c3b[7:1]) 
				& ~set_c3b[0] & ~red_adr[0];


always@(wee_l or l1clk or wen_c4 or set_c4 or waysel_c4 or waysel_err_c4 or bank_select or coloff_c4 or worden_c4 or
        select_red_odd or select_red_even or worden_lo0 or worden_hi0 or worden_lo1 or worden_hi1 or wrd_lo0_a
	or wrd_hi0_a or wrd_lo1_a or wrd_hi1_a or wr_spare_0 or wr_spare_1 or spare_word_enable or vnw_ary)
begin
// Odd row to be written
if(~l1clk & wee_l & wen_c4 & select_red_odd & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary)
 begin
  if(waysel_c4[0])
  begin  
    red_lo0_odd_0   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_0);
    red_hi0_odd_0   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_0);
    red_lo1_odd_0   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_0);
    red_hi1_odd_0   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_0);
    redrow_way0_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way0_spare_odd_0);
    redrow_way0_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way0_spare_odd_1);
   end
  else if(waysel_c4[1])
  begin
    red_lo0_odd_1   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_1);
    red_hi0_odd_1   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_1);
    red_lo1_odd_1   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_1);
    red_hi1_odd_1   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_1);
    redrow_way1_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way1_spare_odd_0);
    redrow_way1_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way1_spare_odd_1);
  end
  else if(waysel_c4[2])
  begin
    red_lo0_odd_2   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_2);
    red_hi0_odd_2   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_2);
    red_lo1_odd_2   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_2);
    red_hi1_odd_2   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_2);
    redrow_way2_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way2_spare_odd_0);
    redrow_way2_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way2_spare_odd_1);
  end
  else if(waysel_c4[3])
  begin
    red_lo0_odd_3   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_3);
    red_hi0_odd_3   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_3);
    red_lo1_odd_3   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_3);
    red_hi1_odd_3   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_3);
    redrow_way3_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way3_spare_odd_0);
    redrow_way3_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way3_spare_odd_1);
  end
  else if(waysel_c4[4])
  begin
    red_lo0_odd_4   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_4);
    red_hi0_odd_4   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_4);
    red_lo1_odd_4   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_4);
    red_hi1_odd_4   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_4);
    redrow_way4_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way4_spare_odd_0);
    redrow_way4_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way4_spare_odd_1);
  end
  else if(waysel_c4[5])
  begin
    red_lo0_odd_5   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_5);
    red_hi0_odd_5   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_5);
    red_lo1_odd_5   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_5);
    red_hi1_odd_5   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_5);
    redrow_way5_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way5_spare_odd_0);
    redrow_way5_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way5_spare_odd_1);
  end
  else if(waysel_c4[6])
  begin
    red_lo0_odd_6   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_6);
    red_hi0_odd_6   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_6);
    red_lo1_odd_6   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_6);
    red_hi1_odd_6   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_6);
    redrow_way6_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way6_spare_odd_0);
    redrow_way6_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way6_spare_odd_1);
  end
  else if(waysel_c4[7])
  begin
    red_lo0_odd_7   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_odd_7);
    red_hi0_odd_7   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_odd_7);
    red_lo1_odd_7   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_odd_7);
    red_hi1_odd_7   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_odd_7);
    redrow_way7_spare_odd_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way7_spare_odd_0);
    redrow_way7_spare_odd_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way7_spare_odd_1);
   end
  end
 

// Even rows to be written
if(~l1clk & wee_l & wen_c4 & select_red_even & ~waysel_err_c4 & bank_select & coloff_c4 & (|worden_c4) & vnw_ary)
 begin
  if(waysel_c4[0])
  begin
    red_lo0_even_0   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_0);
    red_hi0_even_0   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_0);
    red_lo1_even_0   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_0);
    red_hi1_even_0   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_0);
    redrow_way0_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way0_spare_even_0);
    redrow_way0_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way0_spare_even_1);
   end
  else if(waysel_c4[1])
  begin
    red_lo0_even_1   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_1);
    red_hi0_even_1   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_1);
    red_lo1_even_1   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_1);
    red_hi1_even_1   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_1);
    redrow_way1_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way1_spare_even_0);
    redrow_way1_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way1_spare_even_1);
  end
  else if(waysel_c4[2])
  begin
    red_lo0_even_2   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_2);
    red_hi0_even_2   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_2);
    red_lo1_even_2   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_2);
    red_hi1_even_2   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_2);
    redrow_way2_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way2_spare_even_0);
    redrow_way2_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way2_spare_even_1);
  end
  else if(waysel_c4[3])
  begin
    red_lo0_even_3   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_3);
    red_hi0_even_3   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_3);
    red_lo1_even_3   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_3);
    red_hi1_even_3   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_3);
    redrow_way3_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way3_spare_even_0);
    redrow_way3_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way3_spare_even_1);
  end
  else if(waysel_c4[4])
  begin
    red_lo0_even_4   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_4);
    red_hi0_even_4   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_4);
    red_lo1_even_4   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_4);
    red_hi1_even_4   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_4);
    redrow_way4_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way4_spare_even_0);
    redrow_way4_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way4_spare_even_1);
  end
  else if(waysel_c4[5])
  begin
    red_lo0_even_5   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_5);
    red_hi0_even_5   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_5);
    red_lo1_even_5   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_5);
    red_hi1_even_5   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_5);
    redrow_way5_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way5_spare_even_0);
    redrow_way5_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way5_spare_even_1);
  end
  else if(waysel_c4[6])
  begin
    red_lo0_even_6   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_6);
    red_hi0_even_6   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_6);
    red_lo1_even_6   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_6);
    red_hi1_even_6   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_6);
    redrow_way6_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way6_spare_even_0);
    redrow_way6_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way6_spare_even_1);
  end
  else if(waysel_c4[7])
  begin
    red_lo0_even_7   <= (worden_lo0[19:0] & wrd_lo0_a[19:0] | ~worden_lo0[19:0] & red_lo0_even_7);
    red_hi0_even_7   <= (worden_hi0[19:0] & wrd_hi0_a[19:0] | ~worden_hi0[19:0] & red_hi0_even_7);
    red_lo1_even_7   <= (worden_lo1[18:0] & wrd_lo1_a[18:0] | ~worden_lo1[18:0] & red_lo1_even_7);
    red_hi1_even_7   <= (worden_hi1[18:0] & wrd_hi1_a[18:0] | ~worden_hi1[18:0] & red_hi1_even_7);
    redrow_way7_spare_even_0 <= (spare_word_enable[0] & wr_spare_0 | ~spare_word_enable[0] & redrow_way7_spare_even_0);
    redrow_way7_spare_even_1 <= (spare_word_enable[1] & wr_spare_1 | ~spare_word_enable[1] & redrow_way7_spare_even_1);
  end
end
end

// read out
always@(waysel_c4 or coloff_c4_l or set_c4 or vnw_ary)
begin
if(~coloff_c4_l & vnw_ary)
 begin
 if(waysel_c4[0])
     begin
     red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_0 : red_lo0_even_0;
     red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_0 : red_lo1_even_0;
     red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_0 : red_hi0_even_0;
     red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_0 : red_hi1_even_0;
     redrow_rd_spare_0 	  <= (set_c4[0]) ? redrow_way0_spare_odd_0 : redrow_way0_spare_even_0;
     redrow_rd_spare_1 	  <= (set_c4[0]) ? redrow_way0_spare_odd_1 : redrow_way0_spare_even_1;	     
     end
 else if(waysel_c4[1])
     begin
     red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_1 : red_lo0_even_1;
     red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_1 : red_lo1_even_1;
     red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_1 : red_hi0_even_1;
     red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_1 : red_hi1_even_1;
     redrow_rd_spare_0 	  <= (set_c4[0]) ? redrow_way1_spare_odd_0 : redrow_way1_spare_even_0;
     redrow_rd_spare_1 	  <= (set_c4[0]) ? redrow_way1_spare_odd_1 : redrow_way1_spare_even_1;	     
     end
 else if(waysel_c4[2])
     begin            							  
     red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_2 : red_lo0_even_2;
     red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_2 : red_lo1_even_2;
     red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_2 : red_hi0_even_2;
     red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_2 : red_hi1_even_2;
     redrow_rd_spare_0 	  <= (set_c4[0]) ? redrow_way2_spare_odd_0 : redrow_way2_spare_even_0;
     redrow_rd_spare_1 	  <= (set_c4[0]) ? redrow_way2_spare_odd_1 : redrow_way2_spare_even_1;	     
     end
 else if(waysel_c4[3])
     begin            							  
     red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_3 : red_lo0_even_3;
     red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_3 : red_lo1_even_3;
     red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_3 : red_hi0_even_3;
     red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_3 : red_hi1_even_3;
     redrow_rd_spare_0 	  <= (set_c4[0]) ? redrow_way3_spare_odd_0 : redrow_way3_spare_even_0;
     redrow_rd_spare_1 	  <= (set_c4[0]) ? redrow_way3_spare_odd_1 : redrow_way3_spare_even_1;	     
     end
 else if(waysel_c4[4])
     begin            							  
     red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_4 : red_lo0_even_4;
     red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_4 : red_lo1_even_4;
     red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_4 : red_hi0_even_4;
     red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_4 : red_hi1_even_4;
     redrow_rd_spare_0 	  <= (set_c4[0]) ? redrow_way4_spare_odd_0 : redrow_way4_spare_even_0;
     redrow_rd_spare_1 	  <= (set_c4[0]) ? redrow_way4_spare_odd_1 : redrow_way4_spare_even_1;	     
     end
 else if(waysel_c4[5])
     begin            							  
     red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_5 : red_lo0_even_5;
     red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_5 : red_lo1_even_5;
     red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_5 : red_hi0_even_5;
     red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_5 : red_hi1_even_5;
     redrow_rd_spare_0 	  <= (set_c4[0]) ? redrow_way5_spare_odd_0 : redrow_way5_spare_even_0;
     redrow_rd_spare_1 	  <= (set_c4[0]) ? redrow_way5_spare_odd_1 : redrow_way5_spare_even_1;	     
     end
 else if(waysel_c4[6])
     begin            							  
     red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_6 : red_lo0_even_6;
     red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_6 : red_lo1_even_6;
     red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_6 : red_hi0_even_6;
     red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_6 : red_hi1_even_6;
     redrow_rd_spare_0 	  <= (set_c4[0]) ? redrow_way6_spare_odd_0 : redrow_way6_spare_even_0;
     redrow_rd_spare_1 	  <= (set_c4[0]) ? redrow_way6_spare_odd_1 : redrow_way6_spare_even_1;	     
     end
 else if(waysel_c4[7])
     begin           							  
     red_lo0_out_bc[19:0] <= (set_c4[0]) ? red_lo0_odd_7 : red_lo0_even_7;
     red_lo1_out_bc[18:0] <= (set_c4[0]) ? red_lo1_odd_7 : red_lo1_even_7;
     red_hi0_out_bc[19:0] <= (set_c4[0]) ? red_hi0_odd_7 : red_hi0_even_7;
     red_hi1_out_bc[18:0] <= (set_c4[0]) ? red_hi1_odd_7 : red_hi1_even_7;
     redrow_rd_spare_0 	  <= (set_c4[0]) ? redrow_way7_spare_odd_0 : redrow_way7_spare_even_0;
     redrow_rd_spare_1 	  <= (set_c4[0]) ? redrow_way7_spare_odd_1 : redrow_way7_spare_even_1;	
     end
end
end

always@(negedge l1clk)
begin
    red_lo0_out_bc_d_l <= ~red_lo0_out_bc;
    red_hi0_out_bc_d_l <= ~red_hi0_out_bc;
    red_lo1_out_bc_d_l <= ~red_lo1_out_bc;
    red_hi1_out_bc_d_l <= ~red_hi1_out_bc;
    redrow_rd_spare_0_d_l	     <= ~redrow_rd_spare_0;
    redrow_rd_spare_1_d_l	     <= ~redrow_rd_spare_1;	
end

always@(posedge l1clk)
begin
    red_lo0_bc_c5b_l <= red_lo0_out_bc_d_l;
    red_hi0_bc_c5b_l <= red_hi0_out_bc_d_l;
    red_lo1_bc_c5b_l <= red_lo1_out_bc_d_l;
    red_hi1_bc_c5b_l <= red_hi1_out_bc_d_l;
    redrow_rdd_spare_0	 <= redrow_rd_spare_0_d_l;
    redrow_rdd_spare_1	 <= redrow_rd_spare_1_d_l;
end

assign red_rd_data[19:0] =
	{redrow_rdd_spare_0,      red_lo1_bc_c5b_l[4], red_hi0_bc_c5b_l[4],red_lo0_bc_c5b_l[4],
	red_hi1_bc_c5b_l[3], red_lo1_bc_c5b_l[3], red_hi0_bc_c5b_l[3],red_lo0_bc_c5b_l[3],
	red_hi1_bc_c5b_l[2], red_lo1_bc_c5b_l[2], red_hi0_bc_c5b_l[2],red_lo0_bc_c5b_l[2],
	red_hi1_bc_c5b_l[1], red_lo1_bc_c5b_l[1], red_hi0_bc_c5b_l[1],red_lo0_bc_c5b_l[1],
	red_hi1_bc_c5b_l[0], red_lo1_bc_c5b_l[0], red_hi0_bc_c5b_l[0],red_lo0_bc_c5b_l[0]};

	assign red_rd_data[39:20] = {
			  red_lo1_bc_c5b_l[9], red_hi0_bc_c5b_l[9],red_lo0_bc_c5b_l[9],
	red_hi1_bc_c5b_l[8], red_lo1_bc_c5b_l[8], red_hi0_bc_c5b_l[8],red_lo0_bc_c5b_l[8],
	red_hi1_bc_c5b_l[7], red_lo1_bc_c5b_l[7], red_hi0_bc_c5b_l[7],red_lo0_bc_c5b_l[7],
	red_hi1_bc_c5b_l[6], red_lo1_bc_c5b_l[6], red_hi0_bc_c5b_l[6],red_lo0_bc_c5b_l[6],
	red_hi1_bc_c5b_l[5], red_lo1_bc_c5b_l[5], red_hi0_bc_c5b_l[5],red_lo0_bc_c5b_l[5], red_hi1_bc_c5b_l[4]};


	assign red_rd_data[59:40] = {
	red_lo1_bc_c5b_l[14], red_hi0_bc_c5b_l[14],red_lo0_bc_c5b_l[14],
	red_hi1_bc_c5b_l[13], red_lo1_bc_c5b_l[13], red_hi0_bc_c5b_l[13],red_lo0_bc_c5b_l[13],
	red_hi1_bc_c5b_l[12], red_lo1_bc_c5b_l[12], red_hi0_bc_c5b_l[12],red_lo0_bc_c5b_l[12],
	red_hi1_bc_c5b_l[11], red_lo1_bc_c5b_l[11], red_hi0_bc_c5b_l[11],red_lo0_bc_c5b_l[11],
	red_hi1_bc_c5b_l[10], red_lo1_bc_c5b_l[10], red_hi0_bc_c5b_l[10],red_lo0_bc_c5b_l[10], red_hi1_bc_c5b_l[9]};

	assign red_rd_data[79:60] = {
	red_hi0_bc_c5b_l[19], red_lo0_bc_c5b_l[19],
	red_hi1_bc_c5b_l[18], red_lo1_bc_c5b_l[18], red_hi0_bc_c5b_l[18],red_lo0_bc_c5b_l[18],
	red_hi1_bc_c5b_l[17], red_lo1_bc_c5b_l[17], red_hi0_bc_c5b_l[17],red_lo0_bc_c5b_l[17],
	red_hi1_bc_c5b_l[16], red_lo1_bc_c5b_l[16], red_hi0_bc_c5b_l[16],red_lo0_bc_c5b_l[16],
	red_hi1_bc_c5b_l[15], red_lo1_bc_c5b_l[15], red_hi0_bc_c5b_l[15],red_lo0_bc_c5b_l[15], red_hi1_bc_c5b_l[14],redrow_rdd_spare_1};


	always@(cred_mod or red_rd_data)
	begin
	
	for(i=0;i<19;i=i+1)
	begin
	 red_read_data[i] = cred_mod[i] ? red_rd_data[i+1] : red_rd_data[i];
        end
	
	for(i=20;i<40;i=i+1)
        begin
	 red_read_data[i] = cred_mod[i] ? red_rd_data[i-1] : red_rd_data[i];
        end
	

	for(i=40;i<60;i=i+1)
	begin
	 red_read_data[i] = cred_mod[i] ? red_rd_data[i+1] : red_rd_data[i];
        end
	
	for(i=61;i<80;i=i+1)
        begin
	 red_read_data[i] = cred_mod[i] ? red_rd_data[i-1] : red_rd_data[i];
        end
	
	end 


	assign { red_hi0_b_out_l[19], red_lo0_b_out_l[19],
        red_hi1_b_out_l[18], red_lo1_b_out_l[18], red_hi0_b_out_l[18],red_lo0_b_out_l[18],
        red_hi1_b_out_l[17], red_lo1_b_out_l[17], red_hi0_b_out_l[17],red_lo0_b_out_l[17],
        red_hi1_b_out_l[16], red_lo1_b_out_l[16], red_hi0_b_out_l[16],red_lo0_b_out_l[16],
        red_hi1_b_out_l[15], red_lo1_b_out_l[15], red_hi0_b_out_l[15],red_lo0_b_out_l[15], 
	red_hi1_b_out_l[14]} = red_read_data[79:61];
         
        assign {red_lo1_b_out_l[14], red_hi0_b_out_l[14],red_lo0_b_out_l[14],
        red_hi1_b_out_l[13], red_lo1_b_out_l[13], red_hi0_b_out_l[13],red_lo0_b_out_l[13],
        red_hi1_b_out_l[12], red_lo1_b_out_l[12], red_hi0_b_out_l[12],red_lo0_b_out_l[12],
        red_hi1_b_out_l[11], red_lo1_b_out_l[11], red_hi0_b_out_l[11],red_lo0_b_out_l[11],
        red_hi1_b_out_l[10], red_lo1_b_out_l[10], red_hi0_b_out_l[10],red_lo0_b_out_l[10], 
	red_hi1_b_out_l[9]} = red_read_data[59:40];

        assign { red_lo1_b_out_l[9], red_hi0_b_out_l[9],red_lo0_b_out_l[9],
        red_hi1_b_out_l[8], red_lo1_b_out_l[8], red_hi0_b_out_l[8],red_lo0_b_out_l[8],
        red_hi1_b_out_l[7], red_lo1_b_out_l[7], red_hi0_b_out_l[7],red_lo0_b_out_l[7],
        red_hi1_b_out_l[6], red_lo1_b_out_l[6], red_hi0_b_out_l[6],red_lo0_b_out_l[6],
        red_hi1_b_out_l[5], red_lo1_b_out_l[5], red_hi0_b_out_l[5],red_lo0_b_out_l[5], 
	red_hi1_b_out_l[4]} = red_read_data[39:20];

        assign {red_lo1_b_out_l[4], red_hi0_b_out_l[4],red_lo0_b_out_l[4],
        red_hi1_b_out_l[3], red_lo1_b_out_l[3], red_hi0_b_out_l[3],red_lo0_b_out_l[3],
        red_hi1_b_out_l[2], red_lo1_b_out_l[2], red_hi0_b_out_l[2],red_lo0_b_out_l[2],
        red_hi1_b_out_l[1], red_lo1_b_out_l[1], red_hi0_b_out_l[1],red_lo0_b_out_l[1],
        red_hi1_b_out_l[0], red_lo1_b_out_l[0], red_hi0_b_out_l[0],red_lo0_b_out_l[0]} = red_read_data[18:0];


//////////////////////////////////////////////////////////////////////////////
// col redudancy
// hi1, lo1, hi0, lo0

//assign cred_mod_lo0[18:0]  = cred_mod[18:0];
//assign cred_mod_hi0[38:19] = cred_mod[38:19];
//assign cred_mod_lo1[58:39] = cred_mod[58:39];
//assign cred_mod_hi1[77:59] = cred_mod[77:59];

// mux 0+1
// mux 19 spare
// mux 18 and spare
// mux 38 and 37 
// mux 77  


endmodule
`endif

module n2_l2d_dmux78_cust (
  waysel_c3, 
  set_c3, 
  coloff_c3, 
  coloff_c4_l, 
  rd_wr_c3, 
  worden_c3, 
  l2clk, 
  tcu_pce_ov, 
  tcu_pce, 
  se, 
  tcu_clk_stop, 
  waysel_top_c4, 
  waysel_bot_c4, 
  set_top_c3b, 
  set_bot_c3b, 
  coloff_top_c3b_l, 
  coloff_bot_c3b_l, 
  writeen_top_c3b, 
  writeen_bot_c3b, 
  l1clk, 
  worden_top_c3b, 
  worden_bot_c3b, 
  sat_lo0_bc_l, 
  sat_hi0_bc_l, 
  sat_lo1_bc_l, 
  sat_hi1_bc_l, 
  sab_lo0_bc_l, 
  sab_hi0_bc_l, 
  sab_lo1_bc_l, 
  sab_hi1_bc_l, 
  ldin0lo_b, 
  ldin0hi_b, 
  ldin1lo_b, 
  ldin1hi_b, 
  ldout0lo_b, 
  ldout0hi_b, 
  ldout1lo_b, 
  ldout1hi_b, 
  red_d_in_00, 
  red_d_out_00, 
  fuse_l2d_rid_00, 
  fuse_l2d_wren_00, 
  fuse_l2d_reset_00_l, 
  sel_quad_00, 
  red_d_in_01, 
  red_d_out_01, 
  fuse_l2d_rid_01, 
  fuse_l2d_wren_01, 
  fuse_l2d_reset_01_l, 
  sel_quad_01, 
  red_addr_top, 
  red_addr_bot, 
  red_top_d_00, 
  red_top_d_01, 
  cred);

input	[7:0]	waysel_c3;
input	[8:0]   set_c3;
input	   	coloff_c3;
input	   	coloff_c4_l;
//input	[1:0]   coloff_c5;
input	       	rd_wr_c3;
//input	       	readen_c5;
input	[3:0]   worden_c3;
input	       	l2clk;
input	       	tcu_pce_ov;
input	       	tcu_pce;
input	       	se;
input	       	tcu_clk_stop;
		
output	[7:0]	waysel_top_c4;			
output	[7:0]	waysel_bot_c4;			
output	[8:0]	set_top_c3b;		//	Set 8 will be inverted for top/bot
output	[8:0]	set_bot_c3b;		//	Set 8 will be inverted for top/bot
output		coloff_top_c3b_l;		
output		coloff_bot_c3b_l;		
//output		coloff_top_c4_l	;		
//output		coloff_bot_c4_l;			
//output	[1:0]	coloff_top_c5;			
//output	[1:0]	coloff_bot_c5;			
output		writeen_top_c3b;			
output		writeen_bot_c3b;			
//output		readen_top_c5;			
//output		readen_bot_c5;			
output		l1clk;				
output	[3:0]	worden_top_c3b;			
output	[3:0]	worden_bot_c3b;			


input	[19:0]	sat_lo0_bc_l;		//	Senseamp out from top-16kb
input	[19:0]	sat_hi0_bc_l;		//	Senseamp out from top-16kb
input	[18:0]	sat_lo1_bc_l;		//	Senseamp out from top-16kb
input	[18:0]	sat_hi1_bc_l;		//	Senseamp out from top-16kb
input	[19:0]	sab_lo0_bc_l;		//	Senseamp out from bot-16kb
input	[19:0]	sab_hi0_bc_l;		//	Senseamp out from bot-16kb
input	[18:0]	sab_lo1_bc_l;		//	Senseamp out from bot-16kb
input	[18:0]	sab_hi1_bc_l;		//	Senseamp out from bot-16kb
input	[19:0]	ldin0lo_b;	
input	[19:0]	ldin0hi_b;	
input	[18:0]	ldin1lo_b;	
input	[18:0]	ldin1hi_b;	
//input		bnken_lat;		//	Address latch enable (1.5cycle)
output	[19:0]	ldout0lo_b;	
output	[19:0]	ldout0hi_b;
output	[18:0]	ldout1lo_b;	
output	[18:0]	ldout1hi_b;	
		

input	[9:0]	red_d_in_00;
output	[9:0]	red_d_out_00;
input	[2:0]	fuse_l2d_rid_00;
input		fuse_l2d_wren_00;
input		fuse_l2d_reset_00_l;
input		sel_quad_00;

input	[9:0]	red_d_in_01;
output	[9:0]	red_d_out_01;
input	[2:0]	fuse_l2d_rid_01;
input		fuse_l2d_wren_01;
input		fuse_l2d_reset_01_l;
input		sel_quad_01;

output	[9:0]	red_addr_top;
output	[9:0]	red_addr_bot;
// forwarded
input	[9:0]	red_top_d_00;
input	[9:0]	red_top_d_01;

output	[77:0]	cred;
//output		fuse_l2d_reset_00_l_buf;
//output		fuse_l2d_reset_01_l_buf;

reg	[7:0]	waysel_top_c4;
reg	[7:0]	waysel_bot_c4;
reg	[8:0]	set_top_c3b;
reg	[8:0]	set_bot_c3b;
reg		writeen_top_c3b;
reg		writeen_bot_c3b;
reg	[3:0]	worden_top_c3b;
reg	[3:0]	worden_bot_c3b;
reg		coloff_top_c3b_l;
reg		coloff_bot_c3b_l;
reg     [7:0]   waysel_top_c3b;
reg     [7:0]   waysel_bot_c3b;
//always@(posedge l2clk)
always@(negedge l2clk)
begin
        coloff_top_c3b_l                <= ~coloff_c3;
        coloff_bot_c3b_l                <= ~coloff_c3;
	worden_top_c3b[3:0]		<=  worden_c3[3:0];
	worden_bot_c3b[3:0]		<=  worden_c3[3:0];
	writeen_top_c3b			<=  ~rd_wr_c3;
	writeen_bot_c3b			<=  ~rd_wr_c3;	
end

//always@(negedge l2clk)
//always@(l2clk or bnken_lat)
always@(l2clk or coloff_c4_l)
begin
//	if(~bnken_lat)
        if(~l2clk & coloff_c4_l)
	begin
		waysel_top_c3b[7:0]		<=  waysel_c3[7:0];	
		waysel_bot_c3b[7:0]		<=  waysel_c3[7:0];	
		set_bot_c3b[8:0]		<=  set_c3[8:0];
		set_top_c3b[8:0]		<=  {~set_c3[8],set_c3[7:0]};

	end
end

always@(posedge l2clk )
begin
waysel_top_c4[7:0]		<=  waysel_top_c3b[7:0];
waysel_bot_c4[7:0]		<=  waysel_bot_c3b[7:0];
end
//assign 	readen_top_c5	= readen_c5;
//assign 	readen_bot_c5	= readen_c5;
//assign 	coloff_top_c5	= coloff_c5[1:0];
//assign 	coloff_bot_c5	= coloff_c5[1:0];
//assign 	coloff_top_c4_l	= coloff_c4_l;
//assign 	coloff_bot_c4_l	= coloff_c4_l;


wire	[19:0]	sat_lo0_bc;
wire	[19:0]	sab_lo0_bc;
wire	[19:0]	sat_hi0_bc;
wire	[19:0]	sab_hi0_bc;
                       
wire	[18:0]	sat_lo1_bc;
wire	[18:0]	sab_lo1_bc;
wire	[18:0]	sat_hi1_bc;
wire	[18:0]	sab_hi1_bc;


//always@(posedge l1clk)
//begin
assign  sat_lo0_bc[19:0] = ~sat_lo0_bc_l[19:0];
assign  sab_lo0_bc[19:0] = ~sab_lo0_bc_l[19:0];
assign  sat_hi0_bc[19:0] = ~sat_hi0_bc_l[19:0];
assign  sab_hi0_bc[19:0] = ~sab_hi0_bc_l[19:0];

assign  sat_lo1_bc[18:0] = ~sat_lo1_bc_l[18:0];
assign  sab_lo1_bc[18:0] = ~sab_lo1_bc_l[18:0];
assign  sat_hi1_bc[18:0] = ~sat_hi1_bc_l[18:0];
assign  sab_hi1_bc[18:0] = ~sab_hi1_bc_l[18:0];
//end


n2_l2d_sp_512kb_cust_or_macro__ports_3__width_20  or_ldout0lo_b	
	(
	.dout	(ldout0lo_b[19:0]),
	.din0	(sat_lo0_bc[19:0]),
	.din1	(sab_lo0_bc[19:0]),
	.din2	(ldin0lo_b[19:0])
	);

n2_l2d_sp_512kb_cust_or_macro__ports_3__width_20  or_ldout0hi_b       
        (
        .dout   (ldout0hi_b[19:0]),
        .din0   (sat_hi0_bc[19:0]),
        .din1   (sab_hi0_bc[19:0]),
        .din2   (ldin0hi_b[19:0])
        );

n2_l2d_sp_512kb_cust_or_macro__ports_3__width_19  or_ldout1lo_b       
        (
        .dout   (ldout1lo_b[18:0]),
        .din0   (sat_lo1_bc[18:0]),
        .din1   (sab_lo1_bc[18:0]),
        .din2   (ldin1lo_b[18:0])
        );


n2_l2d_sp_512kb_cust_or_macro__ports_3__width_19  or_ldout1hi_b       
        (
        .dout   (ldout1hi_b[18:0]),
        .din0   (sat_hi1_bc[18:0]),
        .din1   (sab_hi1_bc[18:0]),
        .din2   (ldin1hi_b[18:0])
        );


cl_sc1_l1hdr_12x clk_hdr (
	.l2clk	(l2clk),
	.se	(se),
	.pce	(tcu_pce),
	.pce_ov	(tcu_pce_ov),
	.stop  	(tcu_clk_stop),
	.l1clk	(l1clk)
	);


// Redudant row modelling


reg	[9:0]	red_odd_0;
reg	[9:0]	red_odd_1;
reg	[9:0]	red_even_0;
reg	[9:0]	red_even_1;
reg	[7:0]	red_col_0;
reg	[7:0]	red_col_1;
//reg	[9:0]	red_d_out_00;
//reg	[9:0]	red_d_out_01;

wire  red_reg_clk_even_0;
wire  red_reg_clk_even_1;
wire  red_reg_clk_odd_0;
wire  red_reg_clk_odd_1;
wire  red_reg_clk_col_0;
wire  red_reg_clk_col_1;
wire [9:0] red_data_00;
wire [9:0] red_data_01;

// Initialize the register.
initial begin
   
   red_odd_0[9:0] = 10'b0;
   red_odd_1[9:0] = 10'b0;
   red_even_0[9:0]= 10'b0;
   red_even_1[9:0]= 10'b0;
   red_col_0[7:0] = 8'b0;
   red_col_1[7:0] = 8'b0;
end

assign  red_reg_clk_even_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b000) & sel_quad_00) | ~fuse_l2d_reset_00_l);
assign  red_reg_clk_even_1 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b010) & sel_quad_00) | ~fuse_l2d_reset_00_l);
assign  red_reg_clk_col_0  =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b100) & sel_quad_00) | ~fuse_l2d_reset_00_l);

assign  red_reg_clk_odd_0  =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b001) & sel_quad_01) | ~fuse_l2d_reset_01_l);
assign  red_reg_clk_odd_1  =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b011) & sel_quad_01) | ~fuse_l2d_reset_01_l);
assign  red_reg_clk_col_1  =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b101) & sel_quad_01) | ~fuse_l2d_reset_01_l);

assign  red_data_00[9:0] = red_d_in_00[9:0] & {10{fuse_l2d_reset_00_l}};
assign  red_data_01[9:0] = red_d_in_01[9:0] & {10{fuse_l2d_reset_01_l}};

always @(red_reg_clk_even_0 or red_reg_clk_even_1 or red_reg_clk_col_0 or red_reg_clk_odd_0 or red_reg_clk_odd_1 or red_reg_clk_col_1 or red_d_in_00 or red_d_in_01) begin
  if (~red_reg_clk_even_0) begin
    red_even_0[9:0] <= red_data_00[9:0];
  end

  if (~red_reg_clk_even_1) begin
    red_even_1[9:0] <= red_data_00[9:0];
  end  
  
  if (~red_reg_clk_col_0) begin
    red_col_0[7:0] <= {red_data_00[9:8],red_data_00[5:0]};
  end
  
  if (~red_reg_clk_odd_0) begin
    red_odd_0[9:0] <= red_data_01[9:0];
  end

  if (~red_reg_clk_odd_1) begin
    red_odd_1[9:0] <= red_data_01[9:0];
  end  
  
  if (~red_reg_clk_col_1) begin
    red_col_1[7:0] <= {red_data_01[9:8],red_data_01[5:0]};
  end  
end
  
  
// 00 = bot and 01 = top

//always@(fuse_l2d_wren_00 or fuse_l2d_wren_01 or fuse_l2d_rid_01 or fuse_l2d_rid_00 
//	or red_d_in_00 or red_d_in_01 or sel_quad_00 or sel_quad_01)
//begin
//	if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_bot_c3b[8] & (fuse_l2d_rid_00[2:1]==2'b00) & sel_quad_00)
//		red_even_0	<= red_d_in_00;
//	else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_00)
//		red_even_1	<= red_d_in_00;
//	else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_00)
//		red_col_0	<= red_d_in_00[7:0];
//	
//	if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b00) & sel_quad_01)
//                red_odd_0 	<= red_d_in_01;
//	else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_bot_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_01)
//                red_odd_1       <= red_d_in_01;
//	else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_01)
//                red_col_1        <= red_d_in_01[7:0];
//end
//			

//assign red_addr_top = set_top_c3b[0] ? red_odd_0 : red_even_0;
//assign red_addr_bot = set_top_c3b[0] ? red_odd_1 : red_even_1;
assign red_addr_top = set_top_c3b[0] ? red_odd_1 : red_even_1;
assign red_addr_bot = set_top_c3b[0] ? red_odd_0 : red_even_0;

assign red_d_out_00[7:0] = (red_even_0[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b000}}) | 
                           (red_even_1[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b010}}) |
			   ({2'b0,(red_col_0[5:0] & {6{fuse_l2d_rid_00[2:0]==3'b100}})})  | 
			   (red_top_d_00[7:0] & {8{~sel_quad_00}});
			   
assign red_d_out_00[9:8] = (red_even_0[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b000}}) | 
                           (red_even_1[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b010}}) | 
			   (red_col_0[7:6] & {2{fuse_l2d_rid_00[2:0]==3'b100}}) | 
			   (red_top_d_00[9:8] & {2{~sel_quad_00}});			   
			   
			   
assign red_d_out_01[7:0] = (red_odd_0[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b001}}) | 
                           (red_odd_1[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b011}}) |
			   ({2'b0,(red_col_1[5:0] & {6{fuse_l2d_rid_01[2:0]==3'b101}})}) | 
			   (red_top_d_01[7:0] & {8{~sel_quad_01}});			   
			   
assign red_d_out_01[9:8] = (red_odd_0[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b001}}) | 
                           (red_odd_1[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b011}}) |
			   (red_col_1[7:6] & {2{fuse_l2d_rid_01[2:0]==3'b101}}) | 
			   (red_top_d_01[9:8] & {2{~sel_quad_01}});			   
			   			   
			   
//always@(fuse_l2d_rid_00)
//begin
//case(fuse_l2d_rid_00)
//3'b000	: begin 
//		red_d_out_00  = red_even_0; 
//		red_d_out_01  = 10'b0; 
//		end
//3'b010	: begin 
//		red_d_out_00  = red_even_1; 
//		red_d_out_01  = 10'b0; 
//		end
//3'b100	: begin 
//		red_d_out_00  = {2'b0,red_col_0};  
//		red_d_out_01  = 10'b0; 
//		end
//
//3'b001	: begin 
//		red_d_out_01  = red_odd_0;  
//		red_d_out_00  = 10'b0; 
//		end
//3'b011	: begin 
//		red_d_out_01  = red_odd_1;  
//		red_d_out_00  = 10'b0; 
//		end
//3'b101	: begin 
//		red_d_out_01  = {2'b0,red_col_1};  
//		red_d_out_00  = 10'b0; 
//		end
//
//default : begin 
//		red_d_out_00  = red_top_d_00;       
//		red_d_out_01  = red_top_d_01;
//		end
//endcase
//end

// Col redudancy

//reg     [7:0]   red_col_0;
//reg     [7:0]   red_col_1;

reg	[38:0] cred0;
reg	[38:0] cred1;

// Initialize cred0, cred1
initial begin
  cred0[38:0] = 39'b0;
  cred1[38:0] = 39'b0;
end

always@(red_col_0)
if(red_col_0[7] & red_col_0[6] & ~red_col_0[5])
case(red_col_0)
8'b11_0_00000	: 	cred0[18:0]	= 19'b111_1111_1111_1111_1111; //0
8'b11_0_00001	: 	cred0[18:0]	= 19'b111_1111_1111_1111_1110; //1
8'b11_0_00010	: 	cred0[18:0]	= 19'b111_1111_1111_1111_1100; //2
8'b11_0_00011	: 	cred0[18:0]	= 19'b111_1111_1111_1111_1000; //3
8'b11_0_00100	: 	cred0[18:0]	= 19'b111_1111_1111_1111_0000; //4
8'b11_0_00101	: 	cred0[18:0]	= 19'b111_1111_1111_1110_0000; //5
8'b11_0_00110	: 	cred0[18:0]	= 19'b111_1111_1111_1100_0000; //6
8'b11_0_00111	: 	cred0[18:0]	= 19'b111_1111_1111_1000_0000; //7
8'b11_0_01000	: 	cred0[18:0]	= 19'b111_1111_1111_0000_0000; //8
8'b11_0_01001	: 	cred0[18:0]	= 19'b111_1111_1110_0000_0000; //9
8'b11_0_01010	: 	cred0[18:0]	= 19'b111_1111_1100_0000_0000; //10
8'b11_0_01011	: 	cred0[18:0]	= 19'b111_1111_1000_0000_0000; //11
8'b11_0_01100	: 	cred0[18:0]	= 19'b111_1111_0000_0000_0000; //12
8'b11_0_01101	: 	cred0[18:0]	= 19'b111_1110_0000_0000_0000; //13
8'b11_0_01110	: 	cred0[18:0]	= 19'b111_1100_0000_0000_0000; //14
8'b11_0_01111	: 	cred0[18:0]	= 19'b111_1000_0000_0000_0000; //15
8'b11_0_10000	: 	cred0[18:0]	= 19'b111_0000_0000_0000_0000; //16
8'b11_0_10001	: 	cred0[18:0]	= 19'b110_0000_0000_0000_0000; //17
8'b11_0_10010	: 	cred0[18:0]	= 19'b100_0000_0000_0000_0000; //18
default		:       cred0[18:0]	= 19'b0;
endcase 
else cred0[18:0] = 19'b0;

always@(red_col_0)
if(red_col_0[7] & red_col_0[6] & red_col_0[5])
case(red_col_0)
8'b11_1_00000	: 	cred0[38:19]	= 20'b1111_1111_1111_1111_1111;//0
8'b11_1_00001	: 	cred0[38:19]	= 20'b0111_1111_1111_1111_1111;//1
8'b11_1_00010	: 	cred0[38:19]	= 20'b0011_1111_1111_1111_1111;//2
8'b11_1_00011	: 	cred0[38:19]	= 20'b0001_1111_1111_1111_1111;//3
8'b11_1_00100	: 	cred0[38:19]	= 20'b0000_1111_1111_1111_1111;//4
8'b11_1_00101	: 	cred0[38:19]	= 20'b0000_0111_1111_1111_1111;//5
8'b11_1_00110	: 	cred0[38:19]	= 20'b0000_0011_1111_1111_1111;//6
8'b11_1_00111	: 	cred0[38:19]	= 20'b0000_0001_1111_1111_1111;//7
8'b11_1_01000	: 	cred0[38:19]	= 20'b0000_0000_1111_1111_1111;//8
8'b11_1_01001	: 	cred0[38:19]	= 20'b0000_0000_0111_1111_1111;//9
8'b11_1_01010	: 	cred0[38:19]	= 20'b0000_0000_0011_1111_1111;//10
8'b11_1_01011	: 	cred0[38:19]	= 20'b0000_0000_0001_1111_1111;//11
8'b11_1_01100	: 	cred0[38:19]	= 20'b0000_0000_0000_1111_1111;//12
8'b11_1_01101	: 	cred0[38:19]	= 20'b0000_0000_0000_0111_1111;//13
8'b11_1_01110	: 	cred0[38:19]	= 20'b0000_0000_0000_0011_1111;//14
8'b11_1_01111	: 	cred0[38:19]	= 20'b0000_0000_0000_0001_1111;//15
8'b11_1_10000	: 	cred0[38:19]	= 20'b0000_0000_0000_0000_1111;//16
8'b11_1_10001	: 	cred0[38:19]	= 20'b0000_0000_0000_0000_0111;//17
8'b11_1_10010	: 	cred0[38:19]	= 20'b0000_0000_0000_0000_0011;//18
8'b11_1_10011	: 	cred0[38:19]	= 20'b0000_0000_0000_0000_0001;//19
default		:  	cred0[38:19]	= 20'b0;
endcase 				     
else cred0[38:19] = 20'b0;

always@(red_col_1)
if(red_col_1[7] & red_col_1[6] & red_col_1[5])
case(red_col_1)
8'b11_1_00000   :       cred1[19:0]	= 20'b1111_1111_1111_1111_1111; //0
8'b11_1_00001   :       cred1[19:0]	= 20'b1111_1111_1111_1111_1110; //1
8'b11_1_00010   :       cred1[19:0]	= 20'b1111_1111_1111_1111_1100; //2
8'b11_1_00011   :       cred1[19:0]	= 20'b1111_1111_1111_1111_1000; //3
8'b11_1_00100   :       cred1[19:0]	= 20'b1111_1111_1111_1111_0000; //4
8'b11_1_00101   :       cred1[19:0]	= 20'b1111_1111_1111_1110_0000; //5
8'b11_1_00110   :       cred1[19:0]	= 20'b1111_1111_1111_1100_0000; //6
8'b11_1_00111   :       cred1[19:0]	= 20'b1111_1111_1111_1000_0000; //7
8'b11_1_01000   :       cred1[19:0]	= 20'b1111_1111_1111_0000_0000; //8
8'b11_1_01001   :       cred1[19:0]	= 20'b1111_1111_1110_0000_0000; //9
8'b11_1_01010   :       cred1[19:0]	= 20'b1111_1111_1100_0000_0000; //10
8'b11_1_01011   :       cred1[19:0]	= 20'b1111_1111_1000_0000_0000; //11
8'b11_1_01100   :       cred1[19:0]	= 20'b1111_1111_0000_0000_0000; //12
8'b11_1_01101   :       cred1[19:0]	= 20'b1111_1110_0000_0000_0000; //13
8'b11_1_01110   :       cred1[19:0]	= 20'b1111_1100_0000_0000_0000; //14
8'b11_1_01111   :       cred1[19:0]	= 20'b1111_1000_0000_0000_0000; //15
8'b11_1_10000   :       cred1[19:0]	= 20'b1111_0000_0000_0000_0000; //16
8'b11_1_10001   :       cred1[19:0]	= 20'b1110_0000_0000_0000_0000; //17
8'b11_1_10010   :       cred1[19:0]	= 20'b1100_0000_0000_0000_0000; //18
8'b11_1_10011   :       cred1[19:0]	= 20'b1000_0000_0000_0000_0000; //19
default		:       cred1[19:0]	= 20'b0;
endcase
else cred1[19:0] = 20'b0;

always@(red_col_1)
if(red_col_1[7] & red_col_1[6] & ~red_col_1[5])
case(red_col_1)
8'b11_0_00000   :       cred1[38:20]	= 19'b111_1111_1111_1111_1111;//0
8'b11_0_00001   :       cred1[38:20]	= 19'b011_1111_1111_1111_1111;//1
8'b11_0_00010   :       cred1[38:20]	= 19'b001_1111_1111_1111_1111;//2
8'b11_0_00011   :       cred1[38:20]	= 19'b000_1111_1111_1111_1111;//3
8'b11_0_00100   :       cred1[38:20]	= 19'b000_0111_1111_1111_1111;//4
8'b11_0_00101   :       cred1[38:20]	= 19'b000_0011_1111_1111_1111;//5
8'b11_0_00110   :       cred1[38:20]	= 19'b000_0001_1111_1111_1111;//6
8'b11_0_00111   :       cred1[38:20]	= 19'b000_0000_1111_1111_1111;//7
8'b11_0_01000   :       cred1[38:20]	= 19'b000_0000_0111_1111_1111;//8
8'b11_0_01001   :       cred1[38:20]	= 19'b000_0000_0011_1111_1111;//9
8'b11_0_01010   :       cred1[38:20]	= 19'b000_0000_0001_1111_1111;//10
8'b11_0_01011   :       cred1[38:20]	= 19'b000_0000_0000_1111_1111;//11
8'b11_0_01100   :       cred1[38:20]	= 19'b000_0000_0000_0111_1111;//12
8'b11_0_01101   :       cred1[38:20]	= 19'b000_0000_0000_0011_1111;//13
8'b11_0_01110   :       cred1[38:20]	= 19'b000_0000_0000_0001_1111;//14
8'b11_0_01111   :       cred1[38:20]	= 19'b000_0000_0000_0000_1111;//15
8'b11_0_10000   :       cred1[38:20]	= 19'b000_0000_0000_0000_0111;//16
8'b11_0_10001   :       cred1[38:20]	= 19'b000_0000_0000_0000_0011;//17
8'b11_0_10010   :       cred1[38:20]	= 19'b000_0000_0000_0000_0001;//18
default		:       cred1[38:20]	= 19'b0;
endcase
else cred1[38:20] = 19'b0;

assign cred[77:0] = {cred1[38:0], cred0[38:0]};
//assign cred[77:0] = 78'b0;


//assign fuse_l2d_reset_00_buf = fuse_l2d_reset_00;
//assign fuse_l2d_reset_01_buf = fuse_l2d_reset_01;


endmodule


//  
//   or macro for ports = 2,3
//
//


module n2_l2d_sp_512kb_cust_or_macro__ports_3__width_20 (
  din0, 
  din1, 
  din2, 
  dout);
  input [19:0] din0;
  input [19:0] din1;
  input [19:0] din2;
  output [19:0] dout;


or3 #(20)  d0_0 (
.in0(din0[19:0]),
.in1(din1[19:0]),
.in2(din2[19:0]),
.out(dout[19:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module n2_l2d_sp_512kb_cust_or_macro__ports_3__width_19 (
  din0, 
  din1, 
  din2, 
  dout);
  input [18:0] din0;
  input [18:0] din1;
  input [18:0] din2;
  output [18:0] dout;


or3 #(19)  d0_0 (
.in0(din0[18:0]),
.in1(din1[18:0]),
.in2(din2[18:0]),
.out(dout[18:0])
);


endmodule


module n2_l2d_ctrlio_cust (
  l2t_l2d_word_en_c2, 
  l2t_l2d_fbrd_c3, 
  l2t_l2d_col_offset_c2, 
  l2t_l2d_set_c2, 
  l2t_l2d_rd_wr_c3, 
  l2t_l2d_way_sel_c3, 
  l2t_l2d_fb_hit_c3, 
  l2clk, 
  tcu_aclk, 
  tcu_bclk, 
  tcu_scan_en, 
  tcu_pce_ov, 
  tcu_ce, 
  tcu_clk_stop, 
  array_wr_inhibit, 
  scan_in, 
  tcu_se_scancollar_in, 
  tcu_se_scancollar_out, 
  wayerr_c3, 
  l2t_l2d_pwrsav_ov_stg, 
  scan_out, 
  cache_col_offset_all_c7, 
  aclk, 
  bclk, 
  scan_en_clsrhdr, 
  l2b_l2d_fbdecc_c5, 
  l2t_l2d_stdecc_c2, 
  cache_decc_out_c5b, 
  l2d_decc_out_c6, 
  cache_decc_in_c3b_l, 
  l2d_l2t_decc_c52_mux, 
  cache_way_sel_c3_00, 
  cache_way_sel_c3_01, 
  cache_way_sel_c3_10, 
  cache_way_sel_c3_11, 
  cache_way_sel_c3_20, 
  cache_way_sel_c3_21, 
  cache_way_sel_c3_30, 
  cache_way_sel_c3_31, 
  cache_wayerr_c3_00, 
  cache_wayerr_c3_01, 
  cache_wayerr_c3_10, 
  cache_wayerr_c3_11, 
  cache_wayerr_c3_20, 
  cache_wayerr_c3_21, 
  cache_wayerr_c3_30, 
  cache_wayerr_c3_31, 
  cache_set_c3_00, 
  cache_set_c3_01, 
  cache_set_c3_10, 
  cache_set_c3_11, 
  cache_set_c3_20, 
  cache_set_c3_21, 
  cache_set_c3_30, 
  cache_set_c3_31, 
  cache_col_offset_c3_00, 
  cache_col_offset_c3_01, 
  cache_col_offset_c3_10, 
  cache_col_offset_c3_11, 
  cache_col_offset_c3_20, 
  cache_col_offset_c3_21, 
  cache_col_offset_c3_30, 
  cache_col_offset_c3_31, 
  cache_col_offset_c4_l_00, 
  cache_col_offset_c4_l_01, 
  cache_col_offset_c4_l_10, 
  cache_col_offset_c4_l_11, 
  cache_col_offset_c4_l_20, 
  cache_col_offset_c4_l_21, 
  cache_col_offset_c4_l_30, 
  cache_col_offset_c4_l_31, 
  cache_col_offset_c5_00, 
  cache_col_offset_c5_01, 
  cache_col_offset_c5_10, 
  cache_col_offset_c5_11, 
  cache_col_offset_c5_20, 
  cache_col_offset_c5_21, 
  cache_col_offset_c5_30, 
  cache_col_offset_c5_31, 
  cache_rd_wr_c3_00, 
  cache_rd_wr_c3_01, 
  cache_rd_wr_c3_10, 
  cache_rd_wr_c3_11, 
  cache_rd_wr_c3_20, 
  cache_rd_wr_c3_21, 
  cache_rd_wr_c3_30, 
  cache_rd_wr_c3_31, 
  cache_readen_c5_00, 
  cache_readen_c5_01, 
  cache_readen_c5_10, 
  cache_readen_c5_11, 
  cache_readen_c5_20, 
  cache_readen_c5_21, 
  cache_readen_c5_30, 
  cache_readen_c5_31, 
  cache_word_en_c3_00, 
  cache_word_en_c3_01, 
  cache_word_en_c3_10, 
  cache_word_en_c3_11, 
  cache_word_en_c3_20, 
  cache_word_en_c3_21, 
  cache_word_en_c3_30, 
  cache_word_en_c3_31, 
  tcu_pce_ov_00, 
  tcu_pce_ov_01, 
  tcu_pce_ov_10, 
  tcu_pce_ov_11, 
  tcu_pce_ov_20, 
  tcu_pce_ov_21, 
  tcu_pce_ov_30, 
  tcu_pce_ov_31, 
  tcu_pce_00, 
  tcu_pce_01, 
  tcu_pce_10, 
  tcu_pce_11, 
  tcu_pce_20, 
  tcu_pce_21, 
  tcu_pce_30, 
  tcu_pce_31, 
  tcu_clk_stop_00, 
  tcu_clk_stop_01, 
  tcu_clk_stop_10, 
  tcu_clk_stop_11, 
  tcu_clk_stop_20, 
  tcu_clk_stop_21, 
  tcu_clk_stop_30, 
  tcu_clk_stop_31, 
  se_00, 
  se_01, 
  se_10, 
  se_11, 
  se_20, 
  se_21, 
  se_30, 
  se_31, 
  l2b_l2d_fuse_l2d_data_in_d, 
  l2b_l2d_fuse_rid_d, 
  l2b_l2d_fuse_reset_l, 
  l2b_l2d_fuse_l2d_wren_d, 
  efc_fuse_data, 
  fuse_l2d_data_in_131, 
  fuse_l2d_rid_131, 
  fuse_l2d_wren_131, 
  fuse_l2d_reset_131_l, 
  fdout_131, 
  fuse_l2d_data_in_031, 
  fuse_l2d_rid_031, 
  fuse_l2d_wren_031, 
  fuse_l2d_reset_031_l, 
  fdout_031, 
  fuse_l2d_data_in_130, 
  fuse_l2d_rid_130, 
  fuse_l2d_wren_130, 
  fuse_l2d_reset_130_l, 
  fdout_130, 
  fuse_l2d_data_in_030, 
  fuse_l2d_rid_030, 
  fuse_l2d_wren_030, 
  fuse_l2d_reset_030_l, 
  fdout_030, 
  fuse_l2d_data_in_111, 
  fuse_l2d_rid_111, 
  fuse_l2d_wren_111, 
  fuse_l2d_reset_111_l, 
  fdout_111, 
  fuse_l2d_data_in_011, 
  fuse_l2d_rid_011, 
  fuse_l2d_wren_011, 
  fuse_l2d_reset_011_l, 
  fdout_011, 
  fuse_l2d_data_in_110, 
  fuse_l2d_rid_110, 
  fuse_l2d_wren_110, 
  fuse_l2d_reset_110_l, 
  fdout_110, 
  fuse_l2d_data_in_010, 
  fuse_l2d_rid_010, 
  fuse_l2d_wren_010, 
  fuse_l2d_reset_010_l, 
  fdout_010, 
  fuse_l2d_data_in_121, 
  fuse_l2d_rid_121, 
  fuse_l2d_wren_121, 
  fuse_l2d_reset_121_l, 
  fdout_121, 
  fuse_l2d_data_in_021, 
  fuse_l2d_rid_021, 
  fuse_l2d_wren_021, 
  fuse_l2d_reset_021_l, 
  fdout_021, 
  fuse_l2d_data_in_120, 
  fuse_l2d_rid_120, 
  fuse_l2d_wren_120, 
  fuse_l2d_reset_120_l, 
  fdout_120, 
  fuse_l2d_data_in_020, 
  fuse_l2d_rid_020, 
  fuse_l2d_wren_020, 
  fuse_l2d_reset_020_l, 
  fdout_020, 
  fuse_l2d_data_in_101, 
  fuse_l2d_rid_101, 
  fuse_l2d_wren_101, 
  fuse_l2d_reset_101_l, 
  fdout_101, 
  fuse_l2d_data_in_001, 
  fuse_l2d_rid_001, 
  fuse_l2d_wren_001, 
  fuse_l2d_reset_001_l, 
  fdout_001, 
  fuse_l2d_data_in_100, 
  fuse_l2d_rid_100, 
  fuse_l2d_wren_100, 
  fuse_l2d_reset_100_l, 
  fdout_100, 
  fuse_l2d_data_in_000, 
  fuse_l2d_rid_000, 
  fuse_l2d_wren_000, 
  fuse_l2d_reset_000_l, 
  fdout_000, 
  siclk_peri, 
  soclk_peri, 
  pce_ov_peri, 
  pce_peri, 
  scan_collarin_peri, 
  scan_collarout_peri, 
  wr_inhibit_peri, 
  clk_stop_peri, 
  wee_l_q00, 
  wee_l_q01, 
  wee_l_q10, 
  wee_l_q11, 
  wee_l_q20, 
  wee_l_q21, 
  wee_l_q30, 
  wee_l_q31, 
  delout00, 
  delout01, 
  delout10, 
  delout11, 
  delout20, 
  delout21, 
  delout30, 
  delout31);
wire tcu_array_wr_inhibit;
wire l1clk_in;
wire l1clk_intnl;
wire evit_pce_c6;
wire l1clk_evict_c6;
wire [8:0] ff_cache_set_c3_scanin;
wire [8:0] ff_cache_set_c3_scanout;
wire [8:0] cache_set_c3;
wire [3:0] ff_cache_col_offset_c3_scanin;
wire [3:0] ff_cache_col_offset_c3_scanout;
wire [3:0] cache_col_offset_c3;
wire [3:0] ff_cache_col_offset_c4_scanin;
wire [3:0] ff_cache_col_offset_c4_scanout;
wire [3:0] cache_col_offset_c4_muxsel;
wire [3:0] ff_cache_col_offset_c5_muxsel_scanin;
wire [3:0] ff_cache_col_offset_c5_muxsel_scanout;
wire [3:0] cache_col_offset_c5_muxsel;
wire [1:0] ff_cache_col_offset_c52_scanin;
wire [1:0] ff_cache_col_offset_c52_scanout;
wire [3:2] cache_col_offset_c52;
wire cache_col_offset_c5_muxsel_3_or_1;
wire [0:0] ff_cache_col_offset_c52_topsel_scanin;
wire [0:0] ff_cache_col_offset_c52_topsel_scanout;
wire cache_col_offset_c52_topsel;
wire cache_col_offset_all_c3;
wire [0:0] ff_cache_col_offset_all_c4_scanin;
wire [0:0] ff_cache_col_offset_all_c4_scanout;
wire cache_col_offset_all_c4;
wire [0:0] ff_cache_col_offset_all_c5_scanin;
wire [0:0] ff_cache_col_offset_all_c5_scanout;
wire cache_col_offset_all_c5;
wire [0:0] ff_cache_col_offset_all_c6_scanin;
wire [0:0] ff_cache_col_offset_all_c6_scanout;
wire cache_col_offset_all_c6;
wire [0:0] ff_cache_col_offset_all_c7_scanin;
wire [0:0] ff_cache_col_offset_all_c7_scanout;
wire tcu_array_wr_inhibit_n;
wire cache_col_offset_c3_2_tcu_array_wr_inhibit_n;
wire cache_col_offset_c3_0_tcu_array_wr_inhibit_n;
wire cache_col_offset_c3_3_tcu_array_wr_inhibit_n;
wire cache_col_offset_c3_1_tcu_array_wr_inhibit_n;
wire cache_col_offset_c4_tog_001_0_n;
wire cache_col_offset_c4_tog_101_0_n;
wire cache_col_offset_c4_tog_001_1_n;
wire cache_col_offset_c4_tog_101_1_n;
wire cache_col_offset_c4_tog_023_0_n;
wire cache_col_offset_c4_tog_123_0_n;
wire cache_col_offset_c4_tog_023_1_n;
wire cache_col_offset_c4_tog_123_1_n;
wire [1:0] cache_col_offset_c4_tog_001;
wire [1:0] cache_col_offset_c4_tog_101;
wire [1:0] cache_col_offset_c4_tog_023;
wire [1:0] cache_col_offset_c4_tog_123;
wire [3:0] cache_col_offset_c3_n;
wire [3:0] wr_inhibit_cache_col_offset_c3_l;
wire [3:0] wr_inhibit_cache_col_offset_c3;
wire [1:0] cache_col_offset_c4_tog_001_n;
wire wayerr_c3_n;
wire [1:0] wayerr_cache_col_offset_c4_l_tog_001;
wire [1:0] cache_col_offset_c4_tog_101_n;
wire [1:0] wayerr_cache_col_offset_c4_l_tog_101;
wire [1:0] cache_col_offset_c4_tog_023_n;
wire [1:0] wayerr_cache_col_offset_c4_l_tog_023;
wire [1:0] cache_col_offset_c4_tog_123_n;
wire [1:0] wayerr_cache_col_offset_c4_l_tog_123;
wire cache_col_offset_c3_top;
wire cache_col_offset_c3_bot;
wire [1:0] cache_col_offset_c4_tog_in_001;
wire [1:0] cache_col_offset_c4_tog_in_101;
wire [1:0] cache_col_offset_c4_tog_in_023;
wire [1:0] cache_col_offset_c4_tog_in_123;
wire [1:0] ff_cache_col_offset_c4_tog_001_scanin;
wire [1:0] ff_cache_col_offset_c4_tog_001_scanout;
wire [1:0] ff_cache_col_offset_c4_tog_101_scanin;
wire [1:0] ff_cache_col_offset_c4_tog_101_scanout;
wire [1:0] ff_cache_col_offset_c4_tog_023_scanin;
wire [1:0] ff_cache_col_offset_c4_tog_023_scanout;
wire [1:0] ff_cache_col_offset_c4_tog_123_scanin;
wire [1:0] ff_cache_col_offset_c4_tog_123_scanout;
wire [3:0] ff_cache_col_offset_c4_001_scanin;
wire [3:0] ff_cache_col_offset_c4_001_scanout;
wire [3:0] cache_col_offset_c4_001;
wire [3:0] ff_cache_col_offset_c4_101_scanin;
wire [3:0] ff_cache_col_offset_c4_101_scanout;
wire [3:0] cache_col_offset_c4_101;
wire [3:0] ff_cache_col_offset_c4_023_scanin;
wire [3:0] ff_cache_col_offset_c4_023_scanout;
wire [3:0] cache_col_offset_c4_023;
wire [3:0] ff_cache_col_offset_c4_123_scanin;
wire [3:0] ff_cache_col_offset_c4_123_scanout;
wire [3:0] cache_col_offset_c4_123;
wire [3:0] cache_col_offset_c5_001_in;
wire [3:0] cache_col_offset_c5_101_in;
wire [3:0] cache_col_offset_c5_023_in;
wire [3:0] cache_col_offset_c5_123_in;
wire [3:0] ff_cache_col_offset_c5_001_scanin;
wire [3:0] ff_cache_col_offset_c5_001_scanout;
wire [3:0] cache_col_offset_c5_001;
wire [3:0] ff_cache_col_offset_c5_101_scanin;
wire [3:0] ff_cache_col_offset_c5_101_scanout;
wire [3:0] cache_col_offset_c5_101;
wire [3:0] ff_cache_col_offset_c5_023_scanin;
wire [3:0] ff_cache_col_offset_c5_023_scanout;
wire [3:0] cache_col_offset_c5_023;
wire [3:0] ff_cache_col_offset_c5_123_scanin;
wire [3:0] ff_cache_col_offset_c5_123_scanout;
wire [3:0] cache_col_offset_c5_123;
wire cache_rd_wr_c3_generic;
wire cache_rd_wr_c3_next_stage;
wire [0:0] ff_cache_cache_rd_wr_c4_scanin;
wire [0:0] ff_cache_cache_rd_wr_c4_scanout;
wire cache_rd_wr_c4;
wire [0:0] ff_cache_cache_rd_wr_c5_00_scanin;
wire [0:0] ff_cache_cache_rd_wr_c5_00_scanout;
wire cache_rd_wr_c5_00;
wire [0:0] ff_cache_cache_rd_wr_c5_01_scanin;
wire [0:0] ff_cache_cache_rd_wr_c5_01_scanout;
wire cache_rd_wr_c5_01;
wire [0:0] ff_cache_cache_rd_wr_c5_20_scanin;
wire [0:0] ff_cache_cache_rd_wr_c5_20_scanout;
wire cache_rd_wr_c5_20;
wire [0:0] ff_cache_cache_rd_wr_c5_21_scanin;
wire [0:0] ff_cache_cache_rd_wr_c5_21_scanout;
wire cache_rd_wr_c5_21;
wire [15:0] ff_cache_word_en_c3_scanin;
wire [15:0] ff_cache_word_en_c3_scanout;
wire [15:0] cache_word_en_c3;
wire [0:0] ff_cache_sel_fbdecc_c4_scanin;
wire [0:0] ff_cache_sel_fbdecc_c4_scanout;
wire cache_sel_fbdecc_c4;
wire [0:0] ff_cache_sel_fbdecc_c5_scanin;
wire [0:0] ff_cache_sel_fbdecc_c5_scanout;
wire cache_sel_fbdecc_c5;
wire cache_sel_fbdecc_c5_n;
wire [77:0] ff_l2t_l2d_stdecc_c3_scanin;
wire [77:0] ff_l2t_l2d_stdecc_c3_scanout;
wire [77:0] l2t_l2d_stdecc_c3;
wire [0:0] ff_cache_fb_hit_c4_scanin;
wire [0:0] ff_cache_fb_hit_c4_scanout;
wire cache_fb_hit_c4;
wire [0:0] ff_cache_fb_hit_c5_scanin;
wire [0:0] ff_cache_fb_hit_c5_scanout;
wire cache_fb_hit_c5;
wire [0:0] ff_cache_fb_hit_c52_scanin;
wire [0:0] ff_cache_fb_hit_c52_scanout;
wire cache_fb_hit_c52;
wire cache_fb_hit_c52_n;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo0_1_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo0_1_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo0_2_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo0_2_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi0_1_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi0_1_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi0_2_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi0_2_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo0_3_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo0_3_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo0_4_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo0_4_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi0_3_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi0_3_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi0_4_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi0_4_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo1_1_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo1_1_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo1_2_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo1_2_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi1_1_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi1_1_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi1_2_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi1_2_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo1_3_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo1_3_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo1_4_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_lo1_4_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi1_3_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi1_3_scanout;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi1_4_scanin;
wire [38:0] ff_l2b_l2d_fbdecc_c52_hi1_4_scanout;
wire [38:0] ff_l2d_decc_out_c6_lo0_1_scanin;
wire [38:0] ff_l2d_decc_out_c6_lo0_1_scanout;
wire [155:0] l2d_l2t_decc_c52_0;
wire [38:0] ff_l2d_decc_out_c6_lo0_2_scanin;
wire [38:0] ff_l2d_decc_out_c6_lo0_2_scanout;
wire [38:0] ff_l2d_decc_out_c6_hi0_1_scanin;
wire [38:0] ff_l2d_decc_out_c6_hi0_1_scanout;
wire [38:0] ff_l2d_decc_out_c6_hi0_2_scanin;
wire [38:0] ff_l2d_decc_out_c6_hi0_2_scanout;
wire [38:0] ff_l2d_decc_out_c6_lo0_3_scanin;
wire [38:0] ff_l2d_decc_out_c6_lo0_3_scanout;
wire [155:0] l2d_l2t_decc_c52_1;
wire [38:0] ff_l2d_decc_out_c6_lo0_4_scanin;
wire [38:0] ff_l2d_decc_out_c6_lo0_4_scanout;
wire [38:0] ff_l2d_decc_out_c6_hi0_3_scanin;
wire [38:0] ff_l2d_decc_out_c6_hi0_3_scanout;
wire [38:0] ff_l2d_decc_out_c6_hi0_4_scanin;
wire [38:0] ff_l2d_decc_out_c6_hi0_4_scanout;
wire [38:0] ff_l2d_decc_out_c6_lo1_1_scanin;
wire [38:0] ff_l2d_decc_out_c6_lo1_1_scanout;
wire [155:0] l2d_l2t_decc_c52_2;
wire [38:0] ff_l2d_decc_out_c6_lo1_2_scanin;
wire [38:0] ff_l2d_decc_out_c6_lo1_2_scanout;
wire [38:0] ff_l2d_decc_out_c6_hi1_1_scanin;
wire [38:0] ff_l2d_decc_out_c6_hi1_1_scanout;
wire [38:0] ff_l2d_decc_out_c6_hi1_2_scanin;
wire [38:0] ff_l2d_decc_out_c6_hi1_2_scanout;
wire [38:0] ff_l2d_decc_out_c6_lo1_3_scanin;
wire [38:0] ff_l2d_decc_out_c6_lo1_3_scanout;
wire [155:0] l2d_l2t_decc_c52_3;
wire [38:0] ff_l2d_decc_out_c6_lo1_4_scanin;
wire [38:0] ff_l2d_decc_out_c6_lo1_4_scanout;
wire [38:0] ff_l2d_decc_out_c6_hi1_3_scanin;
wire [38:0] ff_l2d_decc_out_c6_hi1_3_scanout;
wire [38:0] ff_l2d_decc_out_c6_hi1_4_scanin;
wire [38:0] ff_l2d_decc_out_c6_hi1_4_scanout;
wire [155:0] cache_decc_out_0_c52;
wire [155:0] cache_decc_out_1_c52;
wire [155:0] cache_decc_out_2_c52;
wire [155:0] cache_decc_out_3_c52;
wire [623:0] cache_decc_out_c52;
wire cache_rd_wr_c3;
wire [155:0] l2d_l2t_decc_c52_20;
wire [155:0] l2d_l2t_decc_c52_31;
wire itis0000;
wire itis0001;
wire itis0010;
wire itis0011;
wire itis0100;
wire itis0101;
wire itis0110;
wire itis0111;
wire itis1000;
wire itis1001;
wire itis1010;
wire itis1011;
wire itis1100;
wire itis1101;
wire itis1110;
wire itis1111;
wire l2b_l2d_fuse_rid_d_0n;
wire or_fuse_l2d_rid_131;
wire stage1_mux_sel0;
wire or_fuse_l2d_rid_121;
wire stage1_mux_sel1;
wire stage1_mux_sel2;
wire [9:0] fdout_stage1;
wire or_fuse_l2d_rid_031;
wire stage2_mux_sel0;
wire or_fuse_l2d_rid_021;
wire stage2_mux_sel1;
wire stage2_mux_sel2;
wire [9:0] fdout_stage2;
wire or_fuse_l2d_rid_130;
wire stage3_mux_sel0;
wire or_fuse_l2d_rid_120;
wire stage3_mux_sel1;
wire stage3_mux_sel2;
wire [9:0] fdout_stage3;
wire or_fuse_l2d_rid_030;
wire stage4_mux_sel0;
wire or_fuse_l2d_rid_020;
wire stage4_mux_sel1;
wire stage4_mux_sel2;
wire [9:0] fdout_stage4;
wire or_fuse_l2d_rid_010;
wire stage10_mux_sel0;
wire or_fuse_l2d_rid_000;
wire stage10_mux_sel1;
wire stage10_mux_sel2;
wire [9:0] fdout_stage10;
wire or_fuse_l2d_rid_110;
wire stage20_mux_sel0;
wire or_fuse_l2d_rid_100;
wire stage20_mux_sel1;
wire stage20_mux_sel2;
wire [9:0] fdout_stage20;
wire or_fuse_l2d_rid_011;
wire stage30_mux_sel0;
wire or_fuse_l2d_rid_001;
wire stage30_mux_sel1;
wire stage30_mux_sel2;
wire [9:0] fdout_stage30;
wire or_fuse_l2d_rid_111;
wire stage40_mux_sel0;
wire or_fuse_l2d_rid_101;
wire stage40_mux_sel1;
wire stage40_mux_sel2;
wire [9:0] fdout_stage40;
wire l2b_l2d_fuse_rid_d_6n;
wire delout20_rgt;
wire delout31_rgt;
wire delout20_lft;
wire delout31_lft;
wire so_q23;
wire so_tstmod;


input	[15:0]	l2t_l2d_word_en_c2;
input	        l2t_l2d_fbrd_c3;
input	[3:0]   l2t_l2d_col_offset_c2;
input	[8:0]   l2t_l2d_set_c2;
input	        l2t_l2d_rd_wr_c3;
input	[15:0]  l2t_l2d_way_sel_c3;
input	        l2t_l2d_fb_hit_c3;
input	        l2clk;
input	        tcu_aclk;
input	        tcu_bclk;
input	        tcu_scan_en;
input	        tcu_pce_ov;
input	        tcu_ce;
input	        tcu_clk_stop;
input	        array_wr_inhibit;
input	        scan_in;
input		tcu_se_scancollar_in;
input		tcu_se_scancollar_out;
input		wayerr_c3;
input		l2t_l2d_pwrsav_ov_stg;
output	        scan_out;
output		cache_col_offset_all_c7;
output		aclk;
output		bclk;
output		scan_en_clsrhdr;

// I/O from Quads

input	[623:0] l2b_l2d_fbdecc_c5;	// filbuf data 
input	[77:0]  l2t_l2d_stdecc_c2;	// store data input
// CHANGE 2
//input	[623:0] cache_decc_out_c52b_l;	// quad 0 read data
input	[623:0] cache_decc_out_c5b;	// quad 0 read data

output	[623:0] l2d_decc_out_c6; 	// evict data
output	[623:0]	cache_decc_in_c3b_l; 	// store data | fbdecc data getting piped to quad
//output	[155:0]	l2d_l2t_decc_c6;	// read data rtn to load 16B
output	[155:0]	l2d_l2t_decc_c52_mux;	// read data rtn to load 16B

output	[15:0]  cache_way_sel_c3_00;
output	[15:0]  cache_way_sel_c3_01;
output	[15:0]  cache_way_sel_c3_10;
output	[15:0]  cache_way_sel_c3_11;
output	[15:0]  cache_way_sel_c3_20;
output	[15:0]  cache_way_sel_c3_21;
output	[15:0]  cache_way_sel_c3_30;
output	[15:0]  cache_way_sel_c3_31;

output    	cache_wayerr_c3_00;
output    	cache_wayerr_c3_01;
output    	cache_wayerr_c3_10;
output    	cache_wayerr_c3_11;
output    	cache_wayerr_c3_20;
output    	cache_wayerr_c3_21;
output    	cache_wayerr_c3_30;
output    	cache_wayerr_c3_31;


output	[8:0]   cache_set_c3_00;	 
output	[8:0]   cache_set_c3_01;	 
output	[8:0]   cache_set_c3_10;	 
output	[8:0]   cache_set_c3_11;	 
output	[8:0]   cache_set_c3_20;	 
output	[8:0]   cache_set_c3_21;	 
output	[8:0]   cache_set_c3_30;	 
output	[8:0]   cache_set_c3_31;	 

output	   cache_col_offset_c3_00;
output	   cache_col_offset_c3_01;
output	   cache_col_offset_c3_10;
output	   cache_col_offset_c3_11;
output	   cache_col_offset_c3_20;
output	   cache_col_offset_c3_21;
output	   cache_col_offset_c3_30;
output	   cache_col_offset_c3_31;

output     cache_col_offset_c4_l_00;
output     cache_col_offset_c4_l_01;
output     cache_col_offset_c4_l_10;
output     cache_col_offset_c4_l_11;
output     cache_col_offset_c4_l_20;
output     cache_col_offset_c4_l_21;
output     cache_col_offset_c4_l_30;
output     cache_col_offset_c4_l_31;

output  [1:0]   cache_col_offset_c5_00;
output  [1:0]   cache_col_offset_c5_01;
output  [1:0]   cache_col_offset_c5_10;
output  [1:0]   cache_col_offset_c5_11;
output  [1:0]   cache_col_offset_c5_20;
output  [1:0]   cache_col_offset_c5_21;
output  [1:0]   cache_col_offset_c5_30;
output  [1:0]   cache_col_offset_c5_31;

output		cache_rd_wr_c3_00;
output		cache_rd_wr_c3_01;
output		cache_rd_wr_c3_10;
output		cache_rd_wr_c3_11;
output		cache_rd_wr_c3_20;
output		cache_rd_wr_c3_21;
output		cache_rd_wr_c3_30;
output		cache_rd_wr_c3_31;


output		cache_readen_c5_00;
output		cache_readen_c5_01;
output		cache_readen_c5_10;
output		cache_readen_c5_11;
output		cache_readen_c5_20;
output		cache_readen_c5_21;
output		cache_readen_c5_30;
output		cache_readen_c5_31;

output	[3:0]   cache_word_en_c3_00;    
output	[3:0]   cache_word_en_c3_01;    
output	[3:0]   cache_word_en_c3_10;    
output	[3:0]   cache_word_en_c3_11;    
output	[3:0]   cache_word_en_c3_20;    
output	[3:0]   cache_word_en_c3_21;    
output	[3:0]   cache_word_en_c3_30;    
output	[3:0]   cache_word_en_c3_31;    

output		tcu_pce_ov_00;
output		tcu_pce_ov_01;
output		tcu_pce_ov_10;
output		tcu_pce_ov_11;
output		tcu_pce_ov_20;
output		tcu_pce_ov_21;
output		tcu_pce_ov_30;
output		tcu_pce_ov_31;
output		tcu_pce_00;
output		tcu_pce_01;
output		tcu_pce_10;
output		tcu_pce_11;
output		tcu_pce_20;
output		tcu_pce_21;
output		tcu_pce_30;
output		tcu_pce_31;
output		tcu_clk_stop_00;
output		tcu_clk_stop_01;
output		tcu_clk_stop_10;
output		tcu_clk_stop_11;
output		tcu_clk_stop_20;
output		tcu_clk_stop_21;
output		tcu_clk_stop_30;
output		tcu_clk_stop_31;

output		se_00;
output		se_01;
output		se_10;
output		se_11;
output		se_20;
output		se_21;
output		se_30;
output		se_31;
// Redudancy

input   [9:0]   l2b_l2d_fuse_l2d_data_in_d;
input   [6:0]   l2b_l2d_fuse_rid_d;
input           l2b_l2d_fuse_reset_l;
input           l2b_l2d_fuse_l2d_wren_d;
output  [9:0]   efc_fuse_data;

// io to the ram
output	[9:0]	fuse_l2d_data_in_131;
output	[4:0]	fuse_l2d_rid_131;
output		fuse_l2d_wren_131;
output		fuse_l2d_reset_131_l;
input	[9:0]	fdout_131;

output	[9:0]	fuse_l2d_data_in_031;
output	[4:0]	fuse_l2d_rid_031;
output		fuse_l2d_wren_031;
output		fuse_l2d_reset_031_l;
input	[9:0]	fdout_031;

output	[9:0]	fuse_l2d_data_in_130;
output	[4:0]	fuse_l2d_rid_130;
output		fuse_l2d_wren_130;
output		fuse_l2d_reset_130_l;
input	[9:0]	fdout_130;

output	[9:0]	fuse_l2d_data_in_030;
output	[4:0]	fuse_l2d_rid_030;
output		fuse_l2d_wren_030;
output		fuse_l2d_reset_030_l;
input	[9:0]	fdout_030;

output	[9:0]	fuse_l2d_data_in_111;
output	[4:0]	fuse_l2d_rid_111;
output		fuse_l2d_wren_111;
output		fuse_l2d_reset_111_l;
input	[9:0]	fdout_111;


output  [9:0]   fuse_l2d_data_in_011;
output  [4:0]   fuse_l2d_rid_011;
output          fuse_l2d_wren_011;
output          fuse_l2d_reset_011_l;
input  [9:0]   fdout_011;


output	[9:0]	fuse_l2d_data_in_110;
output	[4:0]	fuse_l2d_rid_110;
output		fuse_l2d_wren_110;
output		fuse_l2d_reset_110_l;
input	[9:0]	fdout_110;


output	[9:0]	fuse_l2d_data_in_010;
output	[4:0]	fuse_l2d_rid_010;
output		fuse_l2d_wren_010;
output		fuse_l2d_reset_010_l;
input	[9:0]	fdout_010;

output	[9:0]	fuse_l2d_data_in_121;
output	[4:0]	fuse_l2d_rid_121;
output		fuse_l2d_wren_121;
output		fuse_l2d_reset_121_l;
input	[9:0]	fdout_121;


output	[9:0]	fuse_l2d_data_in_021;
output	[4:0]	fuse_l2d_rid_021;
output		fuse_l2d_wren_021;
output		fuse_l2d_reset_021_l;
input	[9:0]	fdout_021;

output	[9:0]	fuse_l2d_data_in_120;
output	[4:0]	fuse_l2d_rid_120;
output		fuse_l2d_wren_120;
output		fuse_l2d_reset_120_l;
input	[9:0]	fdout_120;

output	[9:0]	fuse_l2d_data_in_020;
output	[4:0]	fuse_l2d_rid_020;
output		fuse_l2d_wren_020;
output		fuse_l2d_reset_020_l;
input	[9:0]	fdout_020;

output	[9:0]	fuse_l2d_data_in_101;
output	[4:0]	fuse_l2d_rid_101;
output		fuse_l2d_wren_101;
output		fuse_l2d_reset_101_l;
input	[9:0]	fdout_101;

output	[9:0]	fuse_l2d_data_in_001;
output	[4:0]	fuse_l2d_rid_001;
output		fuse_l2d_wren_001;
output		fuse_l2d_reset_001_l;
input	[9:0]	fdout_001;

output	[9:0]	fuse_l2d_data_in_100;
output	[4:0]	fuse_l2d_rid_100;
output		fuse_l2d_wren_100;
output		fuse_l2d_reset_100_l;
input	[9:0]	fdout_100;

output	[9:0]	fuse_l2d_data_in_000;
output	[4:0]	fuse_l2d_rid_000;
output		fuse_l2d_wren_000;
output		fuse_l2d_reset_000_l;
input	[9:0]	fdout_000;

output		siclk_peri;
output		soclk_peri;
output		pce_ov_peri;
output		pce_peri;
output		scan_collarin_peri;
output		scan_collarout_peri;
output		wr_inhibit_peri;
output		clk_stop_peri;

output		wee_l_q00;
output		wee_l_q01;
output		wee_l_q10;
output		wee_l_q11;
output		wee_l_q20;
output		wee_l_q21;
output		wee_l_q30;
output		wee_l_q31;

output 		delout00;
output 		delout01;
output 		delout10;
output 		delout11;
output 		delout20;
output 		delout21;
output 		delout30;
output 		delout31;

//////////////////////////////////////////////////////////////////////////////
assign tcu_array_wr_inhibit = array_wr_inhibit;
wire pce_ov;
wire siclk;
wire soclk;
//wire scan_out;

//assign stop = tcu_clk_stop;
assign siclk = tcu_aclk;
assign soclk = tcu_bclk;
//assign se = tcu_scan_en;
assign pce_ov = tcu_pce_ov;
assign aclk = tcu_aclk;
assign bclk = tcu_bclk;
assign scan_en_clsrhdr = tcu_scan_en;

assign siclk_peri = siclk;
assign soclk_peri = soclk;
assign pce_ov_peri = pce_ov;
assign pce_peri = tcu_ce;
assign scan_collarin_peri = tcu_se_scancollar_in;
assign scan_collarout_peri = tcu_se_scancollar_out;
assign wr_inhibit_peri = tcu_array_wr_inhibit;
assign clk_stop_peri = tcu_clk_stop;

assign wee_l_q00 = ~tcu_array_wr_inhibit;
assign wee_l_q01 = ~tcu_array_wr_inhibit;
assign wee_l_q10 = ~tcu_array_wr_inhibit;
assign wee_l_q11 = ~tcu_array_wr_inhibit;
assign wee_l_q20 = ~tcu_array_wr_inhibit;
assign wee_l_q21 = ~tcu_array_wr_inhibit;
assign wee_l_q30 = ~tcu_array_wr_inhibit;
assign wee_l_q31 = ~tcu_array_wr_inhibit;

//////////////////////////////////////////////////////////////////////////////

wire	[623:0] cache_decc_in_c3b_l;

wire	[623:0]	cache_decc_in_c3;
//wire	[623:0]	cache_decc_out_c52;
wire	[623:0]	concat_st_decc_out_c3;
wire	[623:0]	l2d_decc_out_c52;
wire	[155:0]	l2d_l2t_decc_c52;
wire	[155:0]	l2d_l2t_decc_c6;		// read data rtn to load 16B
wire	[623:0] l2b_l2d_fbdecc_c52; 
wire	[623:0] l2b_l2d_fbdecc_c5; 


n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_in_hdr (
        .l2clk  (l2clk),
        .se     (tcu_se_scancollar_in),
        .l1en   (tcu_ce),
        .pce_ov (tcu_pce_ov),
        .stop   (tcu_clk_stop),
        .l1clk  (l1clk_in)
        );

n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_intnl_hdr (
        .l2clk  (l2clk),
        .se     (tcu_scan_en),
        .l1en   (tcu_ce),
        .pce_ov (tcu_pce_ov),
        .stop   (tcu_clk_stop),
        .l1clk  (l1clk_intnl)
        );

n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_evict_c6_hdr (
        .l2clk  (l2clk),
        .se     (tcu_scan_en),
        .l1en   (evit_pce_c6),
        .pce_ov (tcu_pce_ov),
        .stop   (tcu_clk_stop),
        .l1clk  (l1clk_evict_c6)
        );

assign cache_way_sel_c3_00[15:0] = l2t_l2d_way_sel_c3[15:0];
assign cache_way_sel_c3_01[15:0] = l2t_l2d_way_sel_c3[15:0];
assign cache_way_sel_c3_10[15:0] = l2t_l2d_way_sel_c3[15:0];
assign cache_way_sel_c3_11[15:0] = l2t_l2d_way_sel_c3[15:0];
assign cache_way_sel_c3_20[15:0] = l2t_l2d_way_sel_c3[15:0];
assign cache_way_sel_c3_21[15:0] = l2t_l2d_way_sel_c3[15:0];
assign cache_way_sel_c3_30[15:0] = l2t_l2d_way_sel_c3[15:0];
assign cache_way_sel_c3_31[15:0] = l2t_l2d_way_sel_c3[15:0];


//
// Way select when more than one is turned on
//


assign cache_wayerr_c3_00 = wayerr_c3;
assign cache_wayerr_c3_01 = wayerr_c3;
assign cache_wayerr_c3_10 = wayerr_c3;
assign cache_wayerr_c3_11 = wayerr_c3;
assign cache_wayerr_c3_20 = wayerr_c3;
assign cache_wayerr_c3_21 = wayerr_c3;
assign cache_wayerr_c3_30 = wayerr_c3;
assign cache_wayerr_c3_31 = wayerr_c3;

// set

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_9   ff_cache_set_c3   
     (
     .scan_in(ff_cache_set_c3_scanin[8:0]),
     .scan_out(ff_cache_set_c3_scanout[8:0]),
     .din	     (l2t_l2d_set_c2[8:0]),
     .l1clk	       (l1clk_in),
     .dout	     (cache_set_c3[8:0]),
  .siclk(siclk),
  .soclk(soclk)
     );

assign cache_set_c3_00[8:0] = cache_set_c3[8:0];         
assign cache_set_c3_01[8:0] = cache_set_c3[8:0];         
assign cache_set_c3_10[8:0] = cache_set_c3[8:0];         
assign cache_set_c3_11[8:0] = cache_set_c3[8:0];         
assign cache_set_c3_20[8:0] = cache_set_c3[8:0];         
assign cache_set_c3_21[8:0] = cache_set_c3[8:0];         
assign cache_set_c3_30[8:0] = cache_set_c3[8:0];         
assign cache_set_c3_31[8:0] = cache_set_c3[8:0];         

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c3   
     (
     .scan_in(ff_cache_col_offset_c3_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c3_scanout[3:0]),
     .din	     (l2t_l2d_col_offset_c2[3:0]),
     .l1clk	       (l1clk_in),
     .dout	     (cache_col_offset_c3[3:0]),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c4   
                (
                .scan_in(ff_cache_col_offset_c4_scanin[3:0]),
                .scan_out(ff_cache_col_offset_c4_scanout[3:0]),
                .din            (cache_col_offset_c3[3:0]),
                .l1clk            (l1clk_intnl),
                .dout           (cache_col_offset_c4_muxsel[3:0]),
  .siclk(siclk),
  .soclk(soclk)
                );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c5_muxsel   
                (
                .scan_in(ff_cache_col_offset_c5_muxsel_scanin[3:0]),
                .scan_out(ff_cache_col_offset_c5_muxsel_scanout[3:0]),
                .din            (cache_col_offset_c4_muxsel[3:0]),
                .l1clk            (l1clk_intnl),
                .dout           (cache_col_offset_c5_muxsel[3:0]),
  .siclk(siclk),
  .soclk(soclk)
                );


n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_2   ff_cache_col_offset_c52   
                (
                .scan_in(ff_cache_col_offset_c52_scanin[1:0]),
                .scan_out(ff_cache_col_offset_c52_scanout[1:0]),
                .din            (cache_col_offset_c5_muxsel[3:2]),
                .l1clk            (l1clk_intnl),
                .dout           (cache_col_offset_c52[3:2]),
  .siclk(siclk),
  .soclk(soclk)
                );

n2_l2d_sp_512kb_cust_or_macro__width_1 slice_or_col_offset_c5_3_1 
	(
	.dout	(cache_col_offset_c5_muxsel_3_or_1),
	.din0	(cache_col_offset_c5_muxsel[3]),
	.din1	(cache_col_offset_c5_muxsel[1])
	);


n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_col_offset_c52_topsel   
     (
     .scan_in(ff_cache_col_offset_c52_topsel_scanin[0:0]),
     .scan_out(ff_cache_col_offset_c52_topsel_scanout[0:0]),
//     .din	     (cache_col_offset_c5_muxsel[3] | cache_col_offset_c5_muxsel[1]),
	.din	(cache_col_offset_c5_muxsel_3_or_1),
     .l1clk	       (l1clk_intnl),
     .dout	     (cache_col_offset_c52_topsel),
  .siclk(siclk),
  .soclk(soclk)
     );


//assign cache_col_offset_all_c3 = cache_col_offset_c3[3] & 
//		cache_col_offset_c3[2] & cache_col_offset_c3[1] & cache_col_offset_c3[0];

n2_l2d_sp_512kb_cust_and_macro__ports_4__width_1 slice_and_cache_col_offset_all_c3 
	(
	.dout	(cache_col_offset_all_c3),
	.din3	(cache_col_offset_c3[3]),
	.din2	(cache_col_offset_c3[2]),
	.din1	(cache_col_offset_c3[1]),
	.din0	(cache_col_offset_c3[0])
	);


n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_col_offset_all_c4   
     (
     .scan_in(ff_cache_col_offset_all_c4_scanin[0:0]),
     .scan_out(ff_cache_col_offset_all_c4_scanout[0:0]),
     .din	     (cache_col_offset_all_c3),
     .l1clk	       (l1clk_intnl),
     .dout	     (cache_col_offset_all_c4),
  .siclk(siclk),
  .soclk(soclk)
     );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_col_offset_all_c5  
     (
     .scan_in(ff_cache_col_offset_all_c5_scanin[0:0]),
     .scan_out(ff_cache_col_offset_all_c5_scanout[0:0]),
     .din	     (cache_col_offset_all_c4),
     .l1clk	       (l1clk_intnl),
     .dout	     (cache_col_offset_all_c5),
  .siclk(siclk),
  .soclk(soclk)
     );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_col_offset_all_c6   
     (
     .scan_in(ff_cache_col_offset_all_c6_scanin[0:0]),
     .scan_out(ff_cache_col_offset_all_c6_scanout[0:0]),
     .din	     (cache_col_offset_all_c5),
     .l1clk	       (l1clk_intnl),
     .dout	     (cache_col_offset_all_c6),
  .siclk(siclk),
  .soclk(soclk)
     );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_col_offset_all_c7   
     (
     .scan_in(ff_cache_col_offset_all_c7_scanin[0:0]),
     .scan_out(ff_cache_col_offset_all_c7_scanout[0:0]),
     .din	     (cache_col_offset_all_c6),
     .l1clk	       (l1clk_intnl),
     .dout	     (cache_col_offset_all_c7),
  .siclk(siclk),
  .soclk(soclk)
     ); 	     
	

//assign evit_pce_c6 = cache_col_offset_all_c6 | l2t_l2d_pwrsav_ov_stg;

n2_l2d_sp_512kb_cust_or_macro__width_1 or_slice_evit_pce_c6 
	(
	.dout	(evit_pce_c6),
	.din0	(cache_col_offset_all_c6),
	.din1	(l2t_l2d_pwrsav_ov_stg)
	);


//assign    cache_col_offset_c3_00 = |{cache_col_offset_c3[2],cache_col_offset_c3[0]};
//assign    cache_col_offset_c3_01 = |{cache_col_offset_c3[2],cache_col_offset_c3[0]};
//assign    cache_col_offset_c3_10 = |{cache_col_offset_c3[3],cache_col_offset_c3[1]};
//assign    cache_col_offset_c3_11 = |{cache_col_offset_c3[3],cache_col_offset_c3[1]};
//assign    cache_col_offset_c3_20 = |{cache_col_offset_c3[2],cache_col_offset_c3[0]};
//assign    cache_col_offset_c3_21 = |{cache_col_offset_c3[2],cache_col_offset_c3[0]};
//assign    cache_col_offset_c3_30 = |{cache_col_offset_c3[3],cache_col_offset_c3[1]};
//assign    cache_col_offset_c3_31 = |{cache_col_offset_c3[3],cache_col_offset_c3[1]};


n2_l2d_sp_512kb_cust_inv_macro__width_1 inv_tcu_array_wr_inhibit 
	(
	.dout	(tcu_array_wr_inhibit_n),
	.din	(tcu_array_wr_inhibit)
	);

n2_l2d_sp_512kb_cust_and_macro__width_1 and_slice_cache_col_offset_c3_00_0 
	(
	.dout	(cache_col_offset_c3_2_tcu_array_wr_inhibit_n),
	.din0	(tcu_array_wr_inhibit_n),
	.din1	(cache_col_offset_c3[2])
	);

n2_l2d_sp_512kb_cust_and_macro__width_1 and_slice_cache_col_offset_c3_00_1 
        (
        .dout   (cache_col_offset_c3_0_tcu_array_wr_inhibit_n),
        .din0   (tcu_array_wr_inhibit_n),
        .din1   (cache_col_offset_c3[0])
        );

n2_l2d_sp_512kb_cust_and_macro__width_1 and_slice_cache_col_offset_c3_10_0 
        (
        .dout   (cache_col_offset_c3_3_tcu_array_wr_inhibit_n),
        .din0    (tcu_array_wr_inhibit_n),
        .din1   (cache_col_offset_c3[3])
        );

n2_l2d_sp_512kb_cust_and_macro__width_1 and_slice_cache_col_offset_c3_10_1 
        (
        .dout   (cache_col_offset_c3_1_tcu_array_wr_inhibit_n),
        .din0    (tcu_array_wr_inhibit_n),
        .din1   (cache_col_offset_c3[1])
        );


n2_l2d_sp_512kb_cust_or_macro__width_1 or_cache_col_offset_c3_00 
        (
        .dout   (cache_col_offset_c3_00),
        .din0   (cache_col_offset_c3_2_tcu_array_wr_inhibit_n),
        .din1   (cache_col_offset_c3_0_tcu_array_wr_inhibit_n)
        );
n2_l2d_sp_512kb_cust_or_macro__width_1 or_cache_col_offset_c3_10 
        (
        .dout   (cache_col_offset_c3_10),
//        .din0   (~tcu_array_wr_inhibit & cache_col_offset_c3[3]),
//        .din1   (~tcu_array_wr_inhibit & cache_col_offset_c3[1])
	.din0	(cache_col_offset_c3_3_tcu_array_wr_inhibit_n),
	.din1	(cache_col_offset_c3_1_tcu_array_wr_inhibit_n)
        );

n2_l2d_sp_512kb_cust_or_macro__width_1 or_cache_col_offset_c3_20 
        (
        .dout   (cache_col_offset_c3_20),
//        .din0   (~tcu_array_wr_inhibit & cache_col_offset_c3[2]),
//        .din1   (~tcu_array_wr_inhibit & cache_col_offset_c3[0])
	.din0	(cache_col_offset_c3_2_tcu_array_wr_inhibit_n),
	.din1	(cache_col_offset_c3_0_tcu_array_wr_inhibit_n)
        );

n2_l2d_sp_512kb_cust_or_macro__width_1 or_cache_col_offset_c3_30 
        (
        .dout   (cache_col_offset_c3_30),
//        .din0   (~tcu_array_wr_inhibit & cache_col_offset_c3[3]),
//        .din1   (~tcu_array_wr_inhibit & cache_col_offset_c3[1])
	.din0	(cache_col_offset_c3_3_tcu_array_wr_inhibit_n),
        .din1   (cache_col_offset_c3_1_tcu_array_wr_inhibit_n)
        );

assign cache_col_offset_c3_01 = cache_col_offset_c3_00;
assign cache_col_offset_c3_11 = cache_col_offset_c3_10;
assign cache_col_offset_c3_21 = cache_col_offset_c3_20;
assign cache_col_offset_c3_31 = cache_col_offset_c3_30;

//inv_macro    inv_cache_col_offset_c3	(width=4)
//	(
//	.dout	(cache_col_offset_c3_1[3:0]),
//	.din	(cache_col_offset_c3[3:0])
//	);

//msff_ctl_macro   ff_cache_col_offset_c4   (fs=1,width=4)
//     (
//     .scan_in(ff_cache_col_offset_c4_scanin[3:0]),
//     .scan_out(ff_cache_col_offset_c4_scanout[3:0]),
//     .din  (cache_col_offset_c4_l[3:0] & (cache_col_offset_c3[3:0] & {4{~tcu_array_wr_inhibit}})),
//     .l1clk	       (l1clk_intnl),
//     .dout	     (cache_col_offset_c4[3:0]),
//     );
//
//assign    cache_col_offset_c4_l_00 = (&{cache_col_offset_c4_l[2],cache_col_offset_c4_l[0]});
//assign    cache_col_offset_c4_l_01 = (&{cache_col_offset_c4_l[2],cache_col_offset_c4_l[0]});
//assign    cache_col_offset_c4_l_10 = (&{cache_col_offset_c4_l[3],cache_col_offset_c4_l[1]});
//assign    cache_col_offset_c4_l_11 = (&{cache_col_offset_c4_l[3],cache_col_offset_c4_l[1]});
//assign    cache_col_offset_c4_l_20 = (&{cache_col_offset_c4_l[2],cache_col_offset_c4_l[0]});
//assign    cache_col_offset_c4_l_21 = (&{cache_col_offset_c4_l[2],cache_col_offset_c4_l[0]});
//assign    cache_col_offset_c4_l_30 = (&{cache_col_offset_c4_l[3],cache_col_offset_c4_l[1]});
//assign    cache_col_offset_c4_l_31 = (&{cache_col_offset_c4_l[3],cache_col_offset_c4_l[1]});


n2_l2d_sp_512kb_cust_inv_macro__width_8 inv_cache_col_offset_c4_tog_all 
	(
	.dout	( { cache_col_offset_c4_tog_001_0_n, cache_col_offset_c4_tog_101_0_n,
                    cache_col_offset_c4_tog_001_1_n, cache_col_offset_c4_tog_101_1_n,
                    cache_col_offset_c4_tog_023_0_n, cache_col_offset_c4_tog_123_0_n,
                    cache_col_offset_c4_tog_023_1_n, cache_col_offset_c4_tog_123_1_n } ),
	.din	( { cache_col_offset_c4_tog_001[0],  cache_col_offset_c4_tog_101[0],
                    cache_col_offset_c4_tog_001[1],  cache_col_offset_c4_tog_101[1],
                    cache_col_offset_c4_tog_023[0],  cache_col_offset_c4_tog_123[0],
                    cache_col_offset_c4_tog_023[1],  cache_col_offset_c4_tog_123[1] })
	);

//assign    cache_col_offset_c4_l_00 =  ~cache_col_offset_c4_tog_001[0] |tcu_array_wr_inhibit;
//assign    cache_col_offset_c4_l_01 =  ~cache_col_offset_c4_tog_101[0] |tcu_array_wr_inhibit;
//assign    cache_col_offset_c4_l_10 =  ~cache_col_offset_c4_tog_001[1] |tcu_array_wr_inhibit;
//assign    cache_col_offset_c4_l_11 =  ~cache_col_offset_c4_tog_101[1] |tcu_array_wr_inhibit;
//assign    cache_col_offset_c4_l_20 =  ~cache_col_offset_c4_tog_023[0] |tcu_array_wr_inhibit;
//assign    cache_col_offset_c4_l_21 =  ~cache_col_offset_c4_tog_123[0] |tcu_array_wr_inhibit;
//assign    cache_col_offset_c4_l_30 =  ~cache_col_offset_c4_tog_023[1] |tcu_array_wr_inhibit;
//assign    cache_col_offset_c4_l_31 =  ~cache_col_offset_c4_tog_123[1] |tcu_array_wr_inhibit;


n2_l2d_sp_512kb_cust_or_macro__width_8 slice_or_cache_col_offset_c4_l_00_to31 
	(
	.dout	( {
		  cache_col_offset_c4_l_00,
                  cache_col_offset_c4_l_01,
                  cache_col_offset_c4_l_10,
                  cache_col_offset_c4_l_11,
                  cache_col_offset_c4_l_20,
                  cache_col_offset_c4_l_21,
                  cache_col_offset_c4_l_30,
                  cache_col_offset_c4_l_31
		 } ),
	.din0	( {
		cache_col_offset_c4_tog_001_0_n,
                cache_col_offset_c4_tog_101_0_n,
                cache_col_offset_c4_tog_001_1_n,
                cache_col_offset_c4_tog_101_1_n,
                cache_col_offset_c4_tog_023_0_n,
                cache_col_offset_c4_tog_123_0_n,
                cache_col_offset_c4_tog_023_1_n,
                cache_col_offset_c4_tog_123_1_n
		}),
	.din1	({8{tcu_array_wr_inhibit}})
	);


n2_l2d_sp_512kb_cust_inv_macro__width_4 inv_slice_cache_col_offset_c3_x 
	(
	.dout	(cache_col_offset_c3_n[3:0]),
	.din	(cache_col_offset_c3[3:0])
	);


n2_l2d_sp_512kb_cust_or_macro__width_4 or_wr_inhibit_cache_col_offset_c3 
        (
        .dout   (wr_inhibit_cache_col_offset_c3_l[3:0]),
//        .din0   (~cache_col_offset_c3[3:0]),
        .din0   (cache_col_offset_c3_n[3:0]),
        .din1   ({4{tcu_array_wr_inhibit}})
        );


n2_l2d_sp_512kb_cust_inv_macro__width_4    inv_wr_inhibit_cache_col_offset_c3    
	(
	.dout	(wr_inhibit_cache_col_offset_c3[3:0]),
	.din	(wr_inhibit_cache_col_offset_c3_l[3:0])
	);

n2_l2d_sp_512kb_cust_inv_macro__width_2 inv_slice_cache_col_offset_c4_tog_001_x 
        (
        .dout   (cache_col_offset_c4_tog_001_n[1:0]),
        .din    (cache_col_offset_c4_tog_001[1:0])
        );

n2_l2d_sp_512kb_cust_inv_macro__width_1 inv_wayerr_c3 
	(
	.dout	(wayerr_c3_n),
	.din	(wayerr_c3)
	);

n2_l2d_sp_512kb_cust_and_macro__width_2 and_wayerr_col_offset_c4_l_001 
        (
        .dout   (wayerr_cache_col_offset_c4_l_tog_001[1:0]),
        .din0   (cache_col_offset_c4_tog_001_n[1:0]),
        .din1   ({2{wayerr_c3_n}})
        );

n2_l2d_sp_512kb_cust_inv_macro__width_2 inv_slice_cache_col_offset_c4_tog_101_x 
        (
        .dout   (cache_col_offset_c4_tog_101_n[1:0]),
        .din    (cache_col_offset_c4_tog_101[1:0])
        );

n2_l2d_sp_512kb_cust_and_macro__width_2 and_wayerr_col_offset_c4_l_101 
        (
        .dout   (wayerr_cache_col_offset_c4_l_tog_101[1:0]),
//        .din0   (~cache_col_offset_c4_tog_101[1:0]),
        .din0   (cache_col_offset_c4_tog_101_n[1:0]),
        .din1   ({2{wayerr_c3_n}})
        );

n2_l2d_sp_512kb_cust_inv_macro__width_2 inv_slice_cache_col_offset_c4_tog_023_x 
        (
        .dout   (cache_col_offset_c4_tog_023_n[1:0]),
        .din    (cache_col_offset_c4_tog_023[1:0])
        );


n2_l2d_sp_512kb_cust_and_macro__width_2 and_wayerr_col_offset_c4_l_023 
        (
        .dout   (wayerr_cache_col_offset_c4_l_tog_023[1:0]),
        .din0   (cache_col_offset_c4_tog_023_n[1:0]),
        .din1   ({2{wayerr_c3_n}})
        );

n2_l2d_sp_512kb_cust_inv_macro__width_2 inv_slice_cache_col_offset_c4_tog_123_x 
        (
        .dout   (cache_col_offset_c4_tog_123_n[1:0]),
        .din    (cache_col_offset_c4_tog_123[1:0])
        );

n2_l2d_sp_512kb_cust_and_macro__width_2 and_wayerr_col_offset_c4_l_123 
        (
        .dout   (wayerr_cache_col_offset_c4_l_tog_123[1:0]),
//        .din0   (~cache_col_offset_c4_tog_123[1:0]),
        .din0   (cache_col_offset_c4_tog_123_n[1:0]),
        .din1   ({2{wayerr_c3_n}})
        );

n2_l2d_sp_512kb_cust_or_macro__width_1 or_col_offset_c3_top 
        (
        .dout   (cache_col_offset_c3_top),
        .din0   (wr_inhibit_cache_col_offset_c3[3]),
        .din1   (wr_inhibit_cache_col_offset_c3[1])
        );

n2_l2d_sp_512kb_cust_or_macro__width_1 or_col_offset_c3_bot 
        (
        .dout   (cache_col_offset_c3_bot),
        .din0   (wr_inhibit_cache_col_offset_c3[2]),
        .din1   (wr_inhibit_cache_col_offset_c3[0])
        );

n2_l2d_sp_512kb_cust_and_macro__width_2 and_cache_col_offset_c4_tog_in_001 
        (
        .dout   (cache_col_offset_c4_tog_in_001[1:0]),
        .din0   (wayerr_cache_col_offset_c4_l_tog_001[1:0]),
        .din1   ({cache_col_offset_c3_top,cache_col_offset_c3_bot})
        );

n2_l2d_sp_512kb_cust_and_macro__width_2 slice_cache_col_offset_c4_tog_in_101 
        (
        .dout   (cache_col_offset_c4_tog_in_101[1:0]),
        .din0   (wayerr_cache_col_offset_c4_l_tog_101[1:0]),
        .din1   ({cache_col_offset_c3_top,cache_col_offset_c3_bot})
        );
n2_l2d_sp_512kb_cust_and_macro__width_2 slice_cache_col_offset_c4_tog_in_023 
        (
        .dout   (cache_col_offset_c4_tog_in_023[1:0]),
        .din0   (wayerr_cache_col_offset_c4_l_tog_023[1:0]),
        .din1   ({cache_col_offset_c3_top,cache_col_offset_c3_bot})
        );
n2_l2d_sp_512kb_cust_and_macro__width_2 slice_cache_col_offset_c4_tog_in_123 
        (
        .dout   (cache_col_offset_c4_tog_in_123[1:0]),
        .din0   (wayerr_cache_col_offset_c4_l_tog_123[1:0]),
        .din1   ({cache_col_offset_c3_top,cache_col_offset_c3_bot})
        );		
	
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_2   ff_cache_col_offset_c4_tog_001   
     (
     .scan_in(ff_cache_col_offset_c4_tog_001_scanin[1:0]),
     .scan_out(ff_cache_col_offset_c4_tog_001_scanout[1:0]),
     .din     (cache_col_offset_c4_tog_in_001[1:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c4_tog_001[1:0]),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_2   ff_cache_col_offset_c4_tog_101   
     (
     .scan_in(ff_cache_col_offset_c4_tog_101_scanin[1:0]),
     .scan_out(ff_cache_col_offset_c4_tog_101_scanout[1:0]),
     .din     (cache_col_offset_c4_tog_in_101[1:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c4_tog_101[1:0]),
  .siclk(siclk),
  .soclk(soclk)
     );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_2   ff_cache_col_offset_c4_tog_023   
     (
     .scan_in(ff_cache_col_offset_c4_tog_023_scanin[1:0]),
     .scan_out(ff_cache_col_offset_c4_tog_023_scanout[1:0]),
      .din     (cache_col_offset_c4_tog_in_023[1:0]),
      .l1clk   (l1clk_intnl),
      .dout    (cache_col_offset_c4_tog_023[1:0]),
  .siclk(siclk),
  .soclk(soclk)
      );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_2   ff_cache_col_offset_c4_tog_123   
     (
     .scan_in(ff_cache_col_offset_c4_tog_123_scanin[1:0]),
     .scan_out(ff_cache_col_offset_c4_tog_123_scanout[1:0]),
     .din     (cache_col_offset_c4_tog_in_123[1:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c4_tog_123[1:0]),
  .siclk(siclk),
  .soclk(soclk)
     );


n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c4_001   
     (
     .scan_in(ff_cache_col_offset_c4_001_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c4_001_scanout[3:0]),
     .din     (wr_inhibit_cache_col_offset_c3[3:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c4_001[3:0]),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c4_101   
     (
     .scan_in(ff_cache_col_offset_c4_101_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c4_101_scanout[3:0]),
     .din     (wr_inhibit_cache_col_offset_c3[3:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c4_101[3:0]),
  .siclk(siclk),
  .soclk(soclk)
     );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c4_023   
     (
     .scan_in(ff_cache_col_offset_c4_023_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c4_023_scanout[3:0]),
      .din     (wr_inhibit_cache_col_offset_c3[3:0]),
      .l1clk   (l1clk_intnl),
      .dout    (cache_col_offset_c4_023[3:0]),
  .siclk(siclk),
  .soclk(soclk)
      );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c4_123   
     (
     .scan_in(ff_cache_col_offset_c4_123_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c4_123_scanout[3:0]),
     .din     (wr_inhibit_cache_col_offset_c3[3:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c4_123[3:0]),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_and_macro__width_4  and_cache_col_offset_c5_001_in 
        (
        .dout   (cache_col_offset_c5_001_in[3:0]),
        .din0   ({cache_col_offset_c4_tog_001[1:0],cache_col_offset_c4_tog_001[1:0]}),
        .din1   (cache_col_offset_c4_001[3:0])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_4  and_cache_col_offset_c5_101_in 
        (
        .dout   (cache_col_offset_c5_101_in[3:0]),
        .din0   ({cache_col_offset_c4_tog_101[1:0],cache_col_offset_c4_tog_101[1:0]}),
        .din1   (cache_col_offset_c4_101[3:0])
        );

n2_l2d_sp_512kb_cust_and_macro__width_4  and_cache_col_offset_c5_023_in 
        (
        .dout   (cache_col_offset_c5_023_in[3:0]),
        .din0   ({cache_col_offset_c4_tog_023[1:0],cache_col_offset_c4_tog_023[1:0]}),
        .din1   (cache_col_offset_c4_023[3:0])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_4  and_cache_col_offset_c5_123_in 
        (
        .dout   (cache_col_offset_c5_123_in[3:0]),
        .din0   ({cache_col_offset_c4_tog_123[1:0],cache_col_offset_c4_tog_123[1:0]}),
        .din1   (cache_col_offset_c4_123[3:0])
        );		

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c5_001   
     (
     .scan_in(ff_cache_col_offset_c5_001_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c5_001_scanout[3:0]),
     .din     (cache_col_offset_c5_001_in[3:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c5_001[3:0]),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c5_101   
     (
     .scan_in(ff_cache_col_offset_c5_101_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c5_101_scanout[3:0]),
     .din     (cache_col_offset_c5_101_in[3:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c5_101[3:0]),
  .siclk(siclk),
  .soclk(soclk)
     );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c5_023   
     (
     .scan_in(ff_cache_col_offset_c5_023_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c5_023_scanout[3:0]),
      .din     (cache_col_offset_c5_023_in[3:0]),
      .l1clk   (l1clk_intnl),
      .dout    (cache_col_offset_c5_023[3:0]),
  .siclk(siclk),
  .soclk(soclk)
      );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4   ff_cache_col_offset_c5_123   
     (
     .scan_in(ff_cache_col_offset_c5_123_scanin[3:0]),
     .scan_out(ff_cache_col_offset_c5_123_scanout[3:0]),
     .din     (cache_col_offset_c5_123_in[3:0]),
     .l1clk   (l1clk_intnl),
     .dout    (cache_col_offset_c5_123[3:0]),
  .siclk(siclk),
  .soclk(soclk)
     );

//assign    cache_col_offset_c4_l_00 = ~(|{cache_col_offset_c4[2],cache_col_offset_c4[0]});
//assign    cache_col_offset_c4_l_01 = ~(|{cache_col_offset_c4[2],cache_col_offset_c4[0]});
//assign    cache_col_offset_c4_l_10 = ~(|{cache_col_offset_c4[3],cache_col_offset_c4[1]});
//assign    cache_col_offset_c4_l_11 = ~(|{cache_col_offset_c4[3],cache_col_offset_c4[1]});
//assign    cache_col_offset_c4_l_20 = ~(|{cache_col_offset_c4[2],cache_col_offset_c4[0]});
//assign    cache_col_offset_c4_l_21 = ~(|{cache_col_offset_c4[2],cache_col_offset_c4[0]});
//assign    cache_col_offset_c4_l_30 = ~(|{cache_col_offset_c4[3],cache_col_offset_c4[1]});
//assign    cache_col_offset_c4_l_31 = ~(|{cache_col_offset_c4[3],cache_col_offset_c4[1]});

assign    cache_col_offset_c5_00[1:0] 	= {cache_col_offset_c5_001[2],cache_col_offset_c5_001[0]};
assign    cache_col_offset_c5_01[1:0] 	= {cache_col_offset_c5_101[2],cache_col_offset_c5_101[0]};
assign    cache_col_offset_c5_10[1:0] 	= {cache_col_offset_c5_001[3],cache_col_offset_c5_001[1]};
assign    cache_col_offset_c5_11[1:0] 	= {cache_col_offset_c5_101[3],cache_col_offset_c5_101[1]};
assign    cache_col_offset_c5_20[1:0] 	= {cache_col_offset_c5_023[2],cache_col_offset_c5_023[0]};
assign    cache_col_offset_c5_21[1:0] 	= {cache_col_offset_c5_123[2],cache_col_offset_c5_123[0]};
assign    cache_col_offset_c5_30[1:0] 	= {cache_col_offset_c5_023[3],cache_col_offset_c5_023[1]};
assign    cache_col_offset_c5_31[1:0] 	= {cache_col_offset_c5_123[3],cache_col_offset_c5_123[1]};


// read writes signals


//assign  cache_rd_wr_c3_00 = cache_rd_wr_c3 | tcu_array_wr_inhibit;
//assign  cache_rd_wr_c3_01 = cache_rd_wr_c3 | tcu_array_wr_inhibit;
//assign  cache_rd_wr_c3_10 = cache_rd_wr_c3 | tcu_array_wr_inhibit;
//assign  cache_rd_wr_c3_11 = cache_rd_wr_c3 | tcu_array_wr_inhibit;
//assign  cache_rd_wr_c3_20 = cache_rd_wr_c3 | tcu_array_wr_inhibit;
//assign  cache_rd_wr_c3_21 = cache_rd_wr_c3 | tcu_array_wr_inhibit;
//assign  cache_rd_wr_c3_30 = cache_rd_wr_c3 | tcu_array_wr_inhibit;
//assign  cache_rd_wr_c3_31 = cache_rd_wr_c3 | tcu_array_wr_inhibit;
//assign  cache_rd_wr_c3_next_stage = cache_rd_wr_c3 | tcu_array_wr_inhibit;

n2_l2d_sp_512kb_cust_or_macro__width_1 or_x111 
	(
	.dout	(cache_rd_wr_c3_generic),
	.din0	(l2t_l2d_rd_wr_c3),
	.din1	(1'b0)
	);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_x112 
        (
        .dout   (cache_rd_wr_c3_next_stage),
        .din0   (l2t_l2d_rd_wr_c3),
        .din1   (1'b0)
        );


assign cache_rd_wr_c3_00 = cache_rd_wr_c3_generic;
assign cache_rd_wr_c3_01 = cache_rd_wr_c3_generic;
assign cache_rd_wr_c3_10 = cache_rd_wr_c3_generic;
assign cache_rd_wr_c3_11 = cache_rd_wr_c3_generic;
assign cache_rd_wr_c3_20 = cache_rd_wr_c3_generic;
assign cache_rd_wr_c3_21 = cache_rd_wr_c3_generic;
assign cache_rd_wr_c3_30 = cache_rd_wr_c3_generic;
assign cache_rd_wr_c3_31 = cache_rd_wr_c3_generic;

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_cache_rd_wr_c4   
     (
     .scan_in(ff_cache_cache_rd_wr_c4_scanin[0:0]),
     .scan_out(ff_cache_cache_rd_wr_c4_scanout[0:0]),
     .din	     (cache_rd_wr_c3_next_stage),
     .l1clk	     (l1clk_intnl),
     .dout	     (cache_rd_wr_c4),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_cache_rd_wr_c5_00   
     (
     .scan_in(ff_cache_cache_rd_wr_c5_00_scanin[0:0]),
     .scan_out(ff_cache_cache_rd_wr_c5_00_scanout[0:0]),
     .din	     (cache_rd_wr_c4),
     .l1clk	     (l1clk_intnl),
     .dout	     (cache_rd_wr_c5_00),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_cache_rd_wr_c5_01   
     (
     .scan_in(ff_cache_cache_rd_wr_c5_01_scanin[0:0]),
     .scan_out(ff_cache_cache_rd_wr_c5_01_scanout[0:0]),
     .din	     (cache_rd_wr_c4),
     .l1clk	     (l1clk_intnl),
     .dout	     (cache_rd_wr_c5_01),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_cache_rd_wr_c5_20   
     (
     .scan_in(ff_cache_cache_rd_wr_c5_20_scanin[0:0]),
     .scan_out(ff_cache_cache_rd_wr_c5_20_scanout[0:0]),
     .din	     (cache_rd_wr_c4),
     .l1clk	     (l1clk_intnl),
     .dout	     (cache_rd_wr_c5_20),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_cache_rd_wr_c5_21   
     (
     .scan_in(ff_cache_cache_rd_wr_c5_21_scanin[0:0]),
     .scan_out(ff_cache_cache_rd_wr_c5_21_scanout[0:0]),
     .din	     (cache_rd_wr_c4),
     .l1clk	     (l1clk_intnl),
     .dout	     (cache_rd_wr_c5_21),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_and_macro__width_8 and_slice_cache_rd_wr_c5_x 
	(
	.dout	({cache_readen_c5_00,
                  cache_readen_c5_01,
                  cache_readen_c5_10,
                  cache_readen_c5_11,
                  cache_readen_c5_20,
                  cache_readen_c5_21,
                  cache_readen_c5_30,
                  cache_readen_c5_31
		}),
	.din0	({cache_rd_wr_c5_00,
                  cache_rd_wr_c5_01,
                  cache_rd_wr_c5_00,
                  cache_rd_wr_c5_01,
                  cache_rd_wr_c5_20,
                  cache_rd_wr_c5_21,
                  cache_rd_wr_c5_20,
                  cache_rd_wr_c5_21
		}),
	.din1	({8{tcu_array_wr_inhibit_n}})
	);


//assign cache_readen_c5_00 = cache_rd_wr_c5_00 & ~tcu_array_wr_inhibit;
//assign cache_readen_c5_01 = cache_rd_wr_c5_01 & ~tcu_array_wr_inhibit;
//assign cache_readen_c5_10 = cache_rd_wr_c5_00 & ~tcu_array_wr_inhibit;
//assign cache_readen_c5_11 = cache_rd_wr_c5_01 & ~tcu_array_wr_inhibit;
//assign cache_readen_c5_20 = cache_rd_wr_c5_20 & ~tcu_array_wr_inhibit;
//assign cache_readen_c5_21 = cache_rd_wr_c5_21 & ~tcu_array_wr_inhibit;
//assign cache_readen_c5_30 = cache_rd_wr_c5_20 & ~tcu_array_wr_inhibit;
//assign cache_readen_c5_31 = cache_rd_wr_c5_21 & ~tcu_array_wr_inhibit;


// word enables for writes
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_16   ff_cache_word_en_c3   
     (
     .scan_in(ff_cache_word_en_c3_scanin[15:0]),
     .scan_out(ff_cache_word_en_c3_scanout[15:0]),
     .din	     (l2t_l2d_word_en_c2[15:0]),
     .l1clk	       (l1clk_in),
     .dout	     (cache_word_en_c3[15:0]),
  .siclk(siclk),
  .soclk(soclk)
     );


//assign cache_word_en_c3_11[3:0]   = {cache_word_en_c3[4],cache_word_en_c3[6], cache_word_en_c3[12],cache_word_en_c3[14]};
//assign cache_word_en_c3_10[3:0]   = {cache_word_en_c3[14],cache_word_en_c3[12], cache_word_en_c3[6],cache_word_en_c3[4]};
//assign cache_word_en_c3_01[3:0]   = {cache_word_en_c3[0],cache_word_en_c3[2], cache_word_en_c3[8],cache_word_en_c3[10]};
//assign cache_word_en_c3_00[3:0]   = {cache_word_en_c3[10],cache_word_en_c3[8], cache_word_en_c3[2],cache_word_en_c3[0]};
//assign cache_word_en_c3_21[3:0]   = {cache_word_en_c3[1],cache_word_en_c3[3], cache_word_en_c3[9],cache_word_en_c3[11]};
//assign cache_word_en_c3_20[3:0]   = {cache_word_en_c3[11],cache_word_en_c3[9], cache_word_en_c3[3],cache_word_en_c3[1]};
//assign cache_word_en_c3_31[3:0]   = {cache_word_en_c3[5],cache_word_en_c3[7], cache_word_en_c3[13],cache_word_en_c3[15]};
//assign cache_word_en_c3_30[3:0]   = {cache_word_en_c3[15],cache_word_en_c3[13], cache_word_en_c3[7],cache_word_en_c3[5]};


assign cache_word_en_c3_01[3:0]   = {cache_word_en_c3[2], cache_word_en_c3[0],cache_word_en_c3[10],cache_word_en_c3[8]};
assign cache_word_en_c3_11[3:0]   = {cache_word_en_c3[6], cache_word_en_c3[4],cache_word_en_c3[14],cache_word_en_c3[12]};
assign cache_word_en_c3_21[3:0]   = {cache_word_en_c3[3], cache_word_en_c3[1],cache_word_en_c3[11],cache_word_en_c3[9] };
assign cache_word_en_c3_31[3:0]   = {cache_word_en_c3[7], cache_word_en_c3[5],cache_word_en_c3[15],cache_word_en_c3[13]};

assign cache_word_en_c3_00[3:0]   = {cache_word_en_c3[10],cache_word_en_c3[8], cache_word_en_c3[2],cache_word_en_c3[0]};
assign cache_word_en_c3_10[3:0]   = {cache_word_en_c3[14],cache_word_en_c3[12], cache_word_en_c3[6],cache_word_en_c3[4]};
assign cache_word_en_c3_20[3:0]   = {cache_word_en_c3[11],cache_word_en_c3[9], cache_word_en_c3[3],cache_word_en_c3[1]};
assign cache_word_en_c3_30[3:0]   = {cache_word_en_c3[15],cache_word_en_c3[13], cache_word_en_c3[7],cache_word_en_c3[5]};


// data going out
// sel fill data instead of store data.

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_sel_fbdecc_c4   
     (
     .scan_in(ff_cache_sel_fbdecc_c4_scanin[0:0]),
     .scan_out(ff_cache_sel_fbdecc_c4_scanout[0:0]),
     .din	     (l2t_l2d_fbrd_c3),
     .l1clk	       (l1clk_in),
     .dout	     (cache_sel_fbdecc_c4),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_sel_fbdecc_c5   
     (
     .scan_in(ff_cache_sel_fbdecc_c5_scanin[0:0]),
     .scan_out(ff_cache_sel_fbdecc_c5_scanout[0:0]),
     .din	     (cache_sel_fbdecc_c4),
     .l1clk	       (l1clk_intnl),
     .dout	     (cache_sel_fbdecc_c5),
  .siclk(siclk),
  .soclk(soclk)
     );


///
//	This portion will concat and prepare store data 
//	it will then mux fill dat awith store data and drive it to memory
//


n2_l2d_sp_512kb_cust_inv_macro__width_1 cache_sel_fbdecc_c5_inv_slice   (
        .dout   (cache_sel_fbdecc_c5_n),
        .din    (cache_sel_fbdecc_c5)
        );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_78   ff_l2t_l2d_stdecc_c3   
     (
     .scan_in(ff_l2t_l2d_stdecc_c3_scanin[77:0]),
     .scan_out(ff_l2t_l2d_stdecc_c3_scanout[77:0]),
     .din	     (l2t_l2d_stdecc_c2[77:0]),
     .l1clk	       (l1clk_in),
     .dout	     (l2t_l2d_stdecc_c3[77:0]),
  .siclk(siclk),
  .soclk(soclk)
     );


assign concat_st_decc_out_c3[623:0] = {l2t_l2d_stdecc_c3[77:0], l2t_l2d_stdecc_c3[77:0], 
	l2t_l2d_stdecc_c3[77:0], l2t_l2d_stdecc_c3[77:0], l2t_l2d_stdecc_c3[77:0], 
	l2t_l2d_stdecc_c3[77:0], l2t_l2d_stdecc_c3[77:0], l2t_l2d_stdecc_c3[77:0]};

n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_1  
	(
	.dout	(cache_decc_in_c3[38:0]),
	.din0	(concat_st_decc_out_c3[38:0]),
	.din1	(l2b_l2d_fbdecc_c5[38:0]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_2  
	(
	.dout	(cache_decc_in_c3[77:39]),
	.din0	(concat_st_decc_out_c3[77:39]),
	.din1	(l2b_l2d_fbdecc_c5[77:39]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_3  
	(
	.dout	(cache_decc_in_c3[116:78]),
	.din0	(concat_st_decc_out_c3[116:78]),
	.din1	(l2b_l2d_fbdecc_c5[116:78]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_4  
	(
	.dout	(cache_decc_in_c3[155:117]),
	.din0	(concat_st_decc_out_c3[155:117]),
	.din1	(l2b_l2d_fbdecc_c5[155:117]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_5  
	(
	.dout	(cache_decc_in_c3[194:156]),
	.din0	(concat_st_decc_out_c3[194:156]),
	.din1	(l2b_l2d_fbdecc_c5[194:156]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_6  
	(
	.dout	(cache_decc_in_c3[233:195]),
	.din0	(concat_st_decc_out_c3[233:195]),
	.din1	(l2b_l2d_fbdecc_c5[233:195]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_7  
	(
	.dout	(cache_decc_in_c3[272:234]),
	.din0	(concat_st_decc_out_c3[272:234]),
	.din1	(l2b_l2d_fbdecc_c5[272:234]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_8  
	(
	.dout	(cache_decc_in_c3[311:273]),
	.din0	(concat_st_decc_out_c3[311:273]),
	.din1	(l2b_l2d_fbdecc_c5[311:273]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_9  
	(
	.dout	(cache_decc_in_c3[350:312]),
	.din0	(concat_st_decc_out_c3[350:312]),
	.din1	(l2b_l2d_fbdecc_c5[350:312]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_10  
	(
	.dout	(cache_decc_in_c3[389:351]),
	.din0	(concat_st_decc_out_c3[389:351]),
	.din1	(l2b_l2d_fbdecc_c5[389:351]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_11  
	(
	.dout	(cache_decc_in_c3[428:390]),
	.din0	(concat_st_decc_out_c3[428:390]),
	.din1	(l2b_l2d_fbdecc_c5[428:390]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_12  
	(
	.dout	(cache_decc_in_c3[467:429]),
	.din0	(concat_st_decc_out_c3[467:429]),
	.din1	(l2b_l2d_fbdecc_c5[467:429]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_13  
	(
	.dout	(cache_decc_in_c3[506:468]),
	.din0	(concat_st_decc_out_c3[506:468]),
	.din1	(l2b_l2d_fbdecc_c5[506:468]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_14  
	(
	.dout	(cache_decc_in_c3[545:507]),
	.din0	(concat_st_decc_out_c3[545:507]),
	.din1	(l2b_l2d_fbdecc_c5[545:507]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_15  
	(
	.dout	(cache_decc_in_c3[584:546]),
	.din0	(concat_st_decc_out_c3[584:546]),
	.din1	(l2b_l2d_fbdecc_c5[584:546]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);
n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39	mux_cache_decc_in_c3_16  
	(
	.dout	(cache_decc_in_c3[623:585]),
	.din0	(concat_st_decc_out_c3[623:585]),
	.din1	(l2b_l2d_fbdecc_c5[623:585]),
	.sel0	(cache_sel_fbdecc_c5_n),
	.sel1	(cache_sel_fbdecc_c5)
	);


// CHANGE 1
//always@(negedge l1clk)
//begin
//	cache_decc_in_c3b_l[623:0] <= ~cache_decc_in_c3[623:0];
//end
//

n2_l2d_sp_512kb_cust_tisram_blbi_macro__width_624	j3		 
  (
  .l1clk ( l1clk_intnl),
  .d_a   (cache_decc_in_c3[623:0]),
  .q_b_l (cache_decc_in_c3b_l[623:0])
  );


//assign cache_decc_in_c3b_l[623:0] = ~cache_decc_in_c3b[623:0];

//
// This portion will bypass filldata 
// and send out read data from meory or filldata

// sel fill buffer data over l2$ data.

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_fb_hit_c4   
     (
     .scan_in(ff_cache_fb_hit_c4_scanin[0:0]),
     .scan_out(ff_cache_fb_hit_c4_scanout[0:0]),
     .din	     (l2t_l2d_fb_hit_c3),
     .l1clk	       (l1clk_in),
     .dout	     (cache_fb_hit_c4),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_fb_hit_c5   
     (
     .scan_in(ff_cache_fb_hit_c5_scanin[0:0]),
     .scan_out(ff_cache_fb_hit_c5_scanout[0:0]),
     .din	     (cache_fb_hit_c4),
     .l1clk	       (l1clk_intnl),
     .dout	     (cache_fb_hit_c5),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1   ff_cache_fb_hit_c52   
     (
     .scan_in(ff_cache_fb_hit_c52_scanin[0:0]),
     .scan_out(ff_cache_fb_hit_c52_scanout[0:0]),
     .din	     (cache_fb_hit_c5),
     .l1clk	       (l1clk_intnl),
     .dout	     (cache_fb_hit_c52),
  .siclk(siclk),
  .soclk(soclk)
     );

n2_l2d_sp_512kb_cust_inv_macro__width_1 cache_fb_hit_c52_inv_slice   (
        .dout   (cache_fb_hit_c52_n),
        .din    (cache_fb_hit_c52)
        );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_lo0_1 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[38:0]),
     .din            (l2b_l2d_fbdecc_c5[38:0]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_lo0_2 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[77:39]),
     .din            (l2b_l2d_fbdecc_c5[77:39]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_hi0_1 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[116:78]),
     .din            (l2b_l2d_fbdecc_c5[116:78]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_hi0_2 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[155:117]),
     .din            (l2b_l2d_fbdecc_c5[155:117]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_lo0_3 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[194:156]),
     .din            (l2b_l2d_fbdecc_c5[194:156]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_lo0_4 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[233:195]),
     .din            (l2b_l2d_fbdecc_c5[233:195]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_hi0_3 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[272:234]),
     .din            (l2b_l2d_fbdecc_c5[272:234]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_hi0_4 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[311:273]),
     .din            (l2b_l2d_fbdecc_c5[311:273]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
	
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_lo1_1 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[350:312]),
     .din            (l2b_l2d_fbdecc_c5[350:312]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_lo1_2 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[389:351]),
     .din            (l2b_l2d_fbdecc_c5[389:351]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_hi1_1 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[428:390]),
     .din            (l2b_l2d_fbdecc_c5[428:390]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_hi1_2 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[467:429]),
     .din            (l2b_l2d_fbdecc_c5[467:429]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_lo1_3 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[506:468]),
     .din            (l2b_l2d_fbdecc_c5[506:468]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_lo1_4 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[545:507]),
     .din            (l2b_l2d_fbdecc_c5[545:507]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_hi1_3 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[584:546]),
     .din            (l2b_l2d_fbdecc_c5[584:546]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2b_l2d_fbdecc_c52_hi1_4 
     (
     .scan_in(ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[38:0]),
     .scan_out(ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[38:0]),
     .dout           (l2b_l2d_fbdecc_c52[623:585]),
     .din            (l2b_l2d_fbdecc_c5[623:585]),
     .l1clk            (l1clk_intnl),
  .siclk(siclk),
  .soclk(soclk)
        );
		
	
// CHECK 

//assign cache_decc_out_c52= {cache_decc_out_3_c52[155:0], cache_decc_out_2_c52[155:0],
//			cache_decc_out_1_c52[155:0],cache_decc_out_0_c52[155:0]};

//mux_macro	mux_rd_decc_out_c52_1  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[38:0]),
//	.din0	(cache_decc_out_c52[38:0]),
//	.din1	(l2b_l2d_fbdecc_c52[38:0]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_2  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[77:39]),
//	.din0	(cache_decc_out_c52[77:39]),
//	.din1	(l2b_l2d_fbdecc_c52[77:39]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_3  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[116:78]),
//	.din0	(cache_decc_out_c52[116:78]),
//	.din1	(l2b_l2d_fbdecc_c52[116:78]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_4  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[155:117]),
//	.din0	(cache_decc_out_c52[155:117]),
//	.din1	(l2b_l2d_fbdecc_c52[155:117]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_5  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[194:156]),
//	.din0	(cache_decc_out_c52[194:156]),
//	.din1	(l2b_l2d_fbdecc_c52[194:156]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_6  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[233:195]),
//	.din0	(cache_decc_out_c52[233:195]),
//	.din1	(l2b_l2d_fbdecc_c52[233:195]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_7  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[272:234]),
//	.din0	(cache_decc_out_c52[272:234]),
//	.din1	(l2b_l2d_fbdecc_c52[272:234]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_8  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[311:273]),
//	.din0	(cache_decc_out_c52[311:273]),
//	.din1	(l2b_l2d_fbdecc_c52[311:273]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_9  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[350:312]),
//	.din0	(cache_decc_out_c52[350:312]),
//	.din1	(l2b_l2d_fbdecc_c52[350:312]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_10  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[389:351]),
//	.din0	(cache_decc_out_c52[389:351]),
//	.din1	(l2b_l2d_fbdecc_c52[389:351]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_11  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[428:390]),
//	.din0	(cache_decc_out_c52[428:390]),
//	.din1	(l2b_l2d_fbdecc_c52[428:390]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_12  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[467:429]),
//	.din0	(cache_decc_out_c52[467:429]),
//	.din1	(l2b_l2d_fbdecc_c52[467:429]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_13  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[506:468]),
//	.din0	(cache_decc_out_c52[506:468]),
//	.din1	(l2b_l2d_fbdecc_c52[506:468]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_14  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[545:507]),
//	.din0	(cache_decc_out_c52[545:507]),
//	.din1	(l2b_l2d_fbdecc_c52[545:507]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_15  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[584:546]),
//	.din0	(cache_decc_out_c52[584:546]),
//	.din1	(l2b_l2d_fbdecc_c52[584:546]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);
//mux_macro	mux_rd_decc_out_c52_16  (width=39,ports=2,mux=aonpe)
//	(
//	.dout	(rd_decc_out_c52[623:585]),
//	.din0	(cache_decc_out_c52[623:585]),
//	.din1	(l2b_l2d_fbdecc_c52[623:585]),
//	.sel0	(cache_fb_hit_c52_n),
//	.sel1	(cache_fb_hit_c52)
//	);

//assign 	   l2d_decc_out_c52[623:0] = rd_decc_out_c52[623:0];

//split following bus into 39 chunk because of the scan connection
//msff_ctl_macro      ff_l2d_decc_out_c6_0  (width=156)
//        (
//        .scan_in(ff_l2d_decc_out_c6_0_scanin),
//        .scan_out(ff_l2d_decc_out_c6_0_scanout),
//        .dout           (l2d_decc_out_c6[155:0]),
//        .din            (l2d_l2t_decc_c52_0[155:0]),
//        .l1clk            (l1clk_evict_c6),
//        );
//
//msff_ctl_macro      ff_l2d_decc_out_c6_1  (width=156)
//        (
//        .scan_in(ff_l2d_decc_out_c6_1_scanin),
//        .scan_out(ff_l2d_decc_out_c6_1_scanout),
//        .dout           (l2d_decc_out_c6[311:156]),
//        .din            (l2d_l2t_decc_c52_1[155:0]),
//        .l1clk            (l1clk_evict_c6),
//        );
//
//msff_ctl_macro      ff_l2d_decc_out_c6_2  (width=156)
//        (
//        .scan_in(ff_l2d_decc_out_c6_2_scanin),
//        .scan_out(ff_l2d_decc_out_c6_2_scanout),
//        .dout           (l2d_decc_out_c6[467:312]),
//        .din            (l2d_l2t_decc_c52_2[155:0]),
//        .l1clk            (l1clk_evict_c6),
//        );
//
//msff_ctl_macro      ff_l2d_decc_out_c6_3  (width=156)
//        (
//        .scan_in(ff_l2d_decc_out_c6_3_scanin),
//        .scan_out(ff_l2d_decc_out_c6_3_scanout),
//        .dout           (l2d_decc_out_c6[623:468]),
//        .din            (l2d_l2t_decc_c52_3[155:0]),
//        .l1clk            (l1clk_evict_c6),
//        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_lo0_1 
     (
     .scan_in(ff_l2d_decc_out_c6_lo0_1_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_lo0_1_scanout[38:0]),
     .dout           (l2d_decc_out_c6[38:0]),
     .din            (l2d_l2t_decc_c52_0[38:0]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_lo0_2 
     (
     .scan_in(ff_l2d_decc_out_c6_lo0_2_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_lo0_2_scanout[38:0]),
     .dout           (l2d_decc_out_c6[77:39]),
     .din            (l2d_l2t_decc_c52_0[77:39]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_hi0_1 
     (
     .scan_in(ff_l2d_decc_out_c6_hi0_1_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_hi0_1_scanout[38:0]),
     .dout           (l2d_decc_out_c6[116:78]),
     .din            (l2d_l2t_decc_c52_0[116:78]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_hi0_2 
     (
     .scan_in(ff_l2d_decc_out_c6_hi0_2_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_hi0_2_scanout[38:0]),
     .dout           (l2d_decc_out_c6[155:117]),
     .din            (l2d_l2t_decc_c52_0[155:117]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_lo0_3 
     (
     .scan_in(ff_l2d_decc_out_c6_lo0_3_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_lo0_3_scanout[38:0]),
     .dout           (l2d_decc_out_c6[194:156]),
     .din            (l2d_l2t_decc_c52_1[38:0]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_lo0_4 
     (
     .scan_in(ff_l2d_decc_out_c6_lo0_4_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_lo0_4_scanout[38:0]),
     .dout           (l2d_decc_out_c6[233:195]),
     .din            (l2d_l2t_decc_c52_1[77:39]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_hi0_3 
     (
     .scan_in(ff_l2d_decc_out_c6_hi0_3_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_hi0_3_scanout[38:0]),
     .dout           (l2d_decc_out_c6[272:234]),
     .din            (l2d_l2t_decc_c52_1[116:78]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_hi0_4 
     (
     .scan_in(ff_l2d_decc_out_c6_hi0_4_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_hi0_4_scanout[38:0]),
     .dout           (l2d_decc_out_c6[311:273]),
     .din            (l2d_l2t_decc_c52_1[155:117]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
	
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_lo1_1 
     (
     .scan_in(ff_l2d_decc_out_c6_lo1_1_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_lo1_1_scanout[38:0]),
     .dout           (l2d_decc_out_c6[350:312]),
     .din            (l2d_l2t_decc_c52_2[38:0]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_lo1_2 
     (
     .scan_in(ff_l2d_decc_out_c6_lo1_2_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_lo1_2_scanout[38:0]),
     .dout           (l2d_decc_out_c6[389:351]),
     .din            (l2d_l2t_decc_c52_2[77:39]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_hi1_1 
     (
     .scan_in(ff_l2d_decc_out_c6_hi1_1_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_hi1_1_scanout[38:0]),
     .dout           (l2d_decc_out_c6[428:390]),
     .din            (l2d_l2t_decc_c52_2[116:78]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_hi1_2 
     (
     .scan_in(ff_l2d_decc_out_c6_hi1_2_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_hi1_2_scanout[38:0]),
     .dout           (l2d_decc_out_c6[467:429]),
     .din            (l2d_l2t_decc_c52_2[155:117]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_lo1_3 
     (
     .scan_in(ff_l2d_decc_out_c6_lo1_3_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_lo1_3_scanout[38:0]),
     .dout           (l2d_decc_out_c6[506:468]),
     .din            (l2d_l2t_decc_c52_3[38:0]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_lo1_4 
     (
     .scan_in(ff_l2d_decc_out_c6_lo1_4_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_lo1_4_scanout[38:0]),
     .dout           (l2d_decc_out_c6[545:507]),
     .din            (l2d_l2t_decc_c52_3[77:39]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_hi1_3 
     (
     .scan_in(ff_l2d_decc_out_c6_hi1_3_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_hi1_3_scanout[38:0]),
     .dout           (l2d_decc_out_c6[584:546]),
     .din            (l2d_l2t_decc_c52_3[116:78]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_39      ff_l2d_decc_out_c6_hi1_4 
     (
     .scan_in(ff_l2d_decc_out_c6_hi1_4_scanin[38:0]),
     .scan_out(ff_l2d_decc_out_c6_hi1_4_scanout[38:0]),
     .dout           (l2d_decc_out_c6[623:585]),
     .din            (l2d_l2t_decc_c52_3[155:117]),
     .l1clk            (l1clk_evict_c6),
  .siclk(siclk),
  .soclk(soclk)
        );
		

////////////////////////////////////////////////////////////////////////
// The 64B-16B mux will be performed in the full custom data array.
// if the col offsets are non one hot, l2t will cause the hold signal
// to be high causing the output mux to hold its old value.
////////////////////////////////////////////////////////////////////////
//assign sel_top = cache_col_offset_c52[0] | cache_col_offset_c52[2];
//assign sel_bot = cache_col_offset_c52[1] | cache_col_offset_c52[3];
//
//assign l2d_l2t_decc_c52[155:0] = sel_top ? cache_decc_out_top_c52b[155:0] : 
//				cache_decc_out_bot_c52b[155:0];

//reg	[155:0] cache_decc_out_0_c52;
//reg	[155:0] cache_decc_out_1_c52;
//reg	[155:0] cache_decc_out_2_c52;
//reg	[155:0] cache_decc_out_3_c52;

//CHANGE 2
//always@(posedge l1clk)
//begin
//
//	cache_decc_out_0_c52_d[155:0] <= cache_decc_out_c52b_l[155:0];
//	cache_decc_out_1_c52_d[155:0] <= cache_decc_out_c52b_l[311:156];
//	cache_decc_out_2_c52_d[155:0] <= cache_decc_out_c52b_l[467:312];
//	cache_decc_out_3_c52_d[155:0] <= cache_decc_out_c52b_l[623:468];
//end

n2_l2d_sp_512kb_cust_tisram_bla_macro__width_156	ff_cache_decc_out_0_c52_d 
	(
	.q_a		(cache_decc_out_0_c52[155:0]),
	.d_b		(cache_decc_out_c5b[155:0]),
	.l1clk		(l1clk_intnl)
	);

n2_l2d_sp_512kb_cust_tisram_bla_macro__width_156      ff_cache_decc_out_1_c52_d 
        (
        .q_a           (cache_decc_out_1_c52[155:0]),
        .d_b            (cache_decc_out_c5b[311:156]),
        .l1clk            (l1clk_intnl)
        );


n2_l2d_sp_512kb_cust_tisram_bla_macro__width_156      ff_cache_decc_out_2_c52_d 
        (
        .q_a           (cache_decc_out_2_c52[155:0]),
        .d_b            (cache_decc_out_c5b[467:312]),
        .l1clk            (l1clk_intnl)
        );

n2_l2d_sp_512kb_cust_tisram_bla_macro__width_156      ff_cache_decc_out_3_c52_d 
        (
        .q_a           (cache_decc_out_3_c52[155:0]),
        .d_b            (cache_decc_out_c5b[623:468]),
        .l1clk            (l1clk_intnl)
        );


// The following portion of the code is used for verification
// synopsys translate_off
assign cache_decc_out_c52[623:0] = {cache_decc_out_3_c52[155:0],cache_decc_out_2_c52[155:0],
				    cache_decc_out_1_c52[155:0],cache_decc_out_0_c52[155:0]};

assign cache_rd_wr_c3 = l2t_l2d_rd_wr_c3;
// synopsys translate_on


// CHANGE 10
//always@(negedge l1clk)
//begin
//        cache_decc_out_0_c52b[155:0] <= cache_decc_out_0_c52[155:0];
//        cache_decc_out_1_c52b[155:0] <= cache_decc_out_1_c52[155:0];
//        cache_decc_out_2_c52b[155:0] <= cache_decc_out_2_c52[155:0];
//        cache_decc_out_3_c52b[155:0] <= cache_decc_out_3_c52[155:0];
//end
//


//always@(negedge l1clk)
//begin
//	//l2b_l2d_fbdecc_c52b[623:0] 	<= l2b_l2d_fbdecc_c52[623:0];
//	//cache_fb_hit_c52b 		<= cache_fb_hit_c52;
//	//cache_col_offset_c52b[3:0]	<= cache_col_offset_c52[3:0];
//end

//mux_macro       mux_cache_data_out_c52  (width=156,ports=4,mux=aonpe,stack=156c)
//        (
//        .dout   (cache_data_out_c52[155:0]),
//        .din0   (cache_decc_out_0_c52[155:0]),
//        .din1   (cache_decc_out_1_c52[155:0]),
//        .din2   (cache_decc_out_2_c52[155:0]),
//        .din3   (cache_decc_out_3_c52[155:0]),
//        .sel0   (cache_col_offset_c52[0]),
//        .sel1   (cache_col_offset_c52[1]),
//        .sel2   (cache_col_offset_c52[2]),
//        .sel3   (cache_col_offset_c52[3])
//        );

//always@(cache_decc_out_0_c52 or cache_decc_out_1_c52 or cache_decc_out_2_c52
//	or cache_decc_out_3_c52 or cache_col_offset_c52 or l2b_l2d_fbdecc_c52 or cache_fb_hit_c52)
//begin
//case(cache_col_offset_c52)
//4'b0001	:	begin
//		fill_bypass_data_c52[155:0] = l2b_l2d_fbdecc_c52[155:0];
//		end
//4'b0010	:	begin
//		fill_bypass_data_c52[155:0] = l2b_l2d_fbdecc_c52[311:156];
//		end
//4'b0100	:	begin
//		fill_bypass_data_c52[155:0] = l2b_l2d_fbdecc_c52[467:312];
//		end
//4'b1000	:	begin
//		fill_bypass_data_c52[155:0] = l2b_l2d_fbdecc_c52[623:468];
//		end
//default	:	begin
//		fill_bypass_data_c52[155:0] = 156'b0;
//		end
//endcase
//end

//mux_macro       mux_fill_bypass_data_c52  (width=156,ports=4,mux=aonpe,stack=156c)
//        (
//        .dout   (fill_bypass_data_c52[155:0]),
//        .din0   (l2b_l2d_fbdecc_c52[155:0]),
//        .din1   (l2b_l2d_fbdecc_c52[311:156]),
//        .din2   (l2b_l2d_fbdecc_c52[467:312]),
//        .din3   (l2b_l2d_fbdecc_c52[623:468]),
//        .sel0   (cache_col_offset_c52[0]),
//        .sel1   (cache_col_offset_c52[1]),
//        .sel2   (cache_col_offset_c52[2]),
//        .sel3   (cache_col_offset_c52[3])
//        );

//assign l2d_l2t_decc_c52[155:0] = cache_fb_hit_c52 ? 
//		fill_bypass_data_c52[155:0] : cache_data_out_c52[155:0] ;

//inv_macro inv_cache_fb_hit_c52 (width=1)
//	(
//	.dout 	(cache_fb_hit_c52_n),
//	.din	(cache_fb_hit_c52)
//	);

n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_156       mux_l2d_l2t_decc_c52_0  
        (
        .dout   (l2d_l2t_decc_c52_0[155:0]),
        .din0   (l2b_l2d_fbdecc_c52[155:0]),
        .din1   (cache_decc_out_0_c52[155:0]),
        .sel0   (cache_fb_hit_c52),
        .sel1   (cache_fb_hit_c52_n)
        );

n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_156       mux_l2d_l2t_decc_c52_1  
        (
        .dout   (l2d_l2t_decc_c52_1[155:0]),
        .din0   (l2b_l2d_fbdecc_c52[311:156]),
        .din1   (cache_decc_out_1_c52[155:0]),
        .sel0   (cache_fb_hit_c52),
        .sel1   (cache_fb_hit_c52_n)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_156       mux_l2d_l2t_decc_c52_2  
        (
        .dout   (l2d_l2t_decc_c52_2[155:0]),
        .din0   (l2b_l2d_fbdecc_c52[467:312]),
        .din1   (cache_decc_out_2_c52[155:0]),
        .sel0   (cache_fb_hit_c52),
        .sel1   (cache_fb_hit_c52_n)
        );

n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_156       mux_l2d_l2t_decc_c52_3  
        (
        .dout   (l2d_l2t_decc_c52_3[155:0]),
        .din0   (l2b_l2d_fbdecc_c52[623:468]),
        .din1   (cache_decc_out_3_c52[155:0]),
        .sel0   (cache_fb_hit_c52),
        .sel1   (cache_fb_hit_c52_n)
        );

n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_156       mux_l2d_l2t_decc_c52_20  
        (
        .dout   (l2d_l2t_decc_c52_20[155:0]),
        .din0   (l2d_l2t_decc_c52_2[155:0]),
        .din1   (l2d_l2t_decc_c52_0[155:0]),
        .sel0   (cache_col_offset_c52[2]),
        .sel1   (~cache_col_offset_c52[2])
        );

n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_156       mux_l2d_l2t_decc_c52_31  
        (
        .dout   (l2d_l2t_decc_c52_31[155:0]),
        .din0   (l2d_l2t_decc_c52_3[155:0]),
        .din1   (l2d_l2t_decc_c52_1[155:0]),
        .sel0   (cache_col_offset_c52[3]),
        .sel1   (~cache_col_offset_c52[3])
        );

n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_156       mux_l2d_l2t_decc_c52_topsel  
        (
        .dout   (l2d_l2t_decc_c52_mux[155:0]),
        .din0   (l2d_l2t_decc_c52_31[155:0]),
        .din1   (l2d_l2t_decc_c52_20[155:0]),
        .sel0   (cache_col_offset_c52_topsel),
        .sel1   (~cache_col_offset_c52_topsel)
        );

//msff_ctl_macro      ff_l2d_l2t_decc_c6  (width=156)
//        (
//        .scan_in(ff_l2d_l2t_decc_c6_scanin),
//        .scan_out(ff_l2d_l2t_decc_c6_scanout),
//        .dout           (l2d_l2t_decc_c6[155:0]),
//        .din            (l2d_l2t_decc_c52_topsel[155:0]),
//        .l1clk            (l1clk_intnl),
//        );


// tcu signals

assign          tcu_pce_ov_00 = tcu_pce_ov;
assign          tcu_pce_ov_01 = tcu_pce_ov;
assign          tcu_pce_ov_10 = tcu_pce_ov;
assign          tcu_pce_ov_11 = tcu_pce_ov;
assign          tcu_pce_ov_20 = tcu_pce_ov;
assign          tcu_pce_ov_21 = tcu_pce_ov;
assign          tcu_pce_ov_30 = tcu_pce_ov;
assign          tcu_pce_ov_31 = tcu_pce_ov;
assign          tcu_pce_00 = tcu_ce;
assign          tcu_pce_01 = tcu_ce;
assign          tcu_pce_10 = tcu_ce;
assign          tcu_pce_11 = tcu_ce;
assign          tcu_pce_20 = tcu_ce;
assign          tcu_pce_21 = tcu_ce;
assign          tcu_pce_30 = tcu_ce;
assign          tcu_pce_31 = tcu_ce;
assign          tcu_clk_stop_00 = tcu_clk_stop;
assign          tcu_clk_stop_01 = tcu_clk_stop;
assign          tcu_clk_stop_10 = tcu_clk_stop;
assign          tcu_clk_stop_11 = tcu_clk_stop;
assign          tcu_clk_stop_20 = tcu_clk_stop;
assign          tcu_clk_stop_21 = tcu_clk_stop;
assign          tcu_clk_stop_30 = tcu_clk_stop;
assign          tcu_clk_stop_31 = tcu_clk_stop;


assign		se_00 = tcu_scan_en;
assign		se_01 = tcu_scan_en;
assign		se_10 = tcu_scan_en;
assign		se_11 = tcu_scan_en;
assign		se_20 = tcu_scan_en;
assign		se_21 = tcu_scan_en;
assign		se_30 = tcu_scan_en;
assign		se_31 = tcu_scan_en;

// Redudancy

wire  [4:0]      fuse_l2d_rid_100;
wire  [4:0]      fuse_l2d_rid_110;
wire  [4:0]      fuse_l2d_rid_101;
wire  [4:0]      fuse_l2d_rid_111;
wire  [4:0]      fuse_l2d_rid_120;
wire  [4:0]      fuse_l2d_rid_121;
wire  [4:0]      fuse_l2d_rid_130;
wire  [4:0]      fuse_l2d_rid_131;
wire  [4:0]      fuse_l2d_rid_000;
wire  [4:0]      fuse_l2d_rid_001;
wire  [4:0]      fuse_l2d_rid_010;
wire  [4:0]      fuse_l2d_rid_011;
wire  [4:0]      fuse_l2d_rid_020;
wire  [4:0]      fuse_l2d_rid_021;
wire  [4:0]      fuse_l2d_rid_030;
wire  [4:0]      fuse_l2d_rid_031;

//assign fuse_l2d_rid_111[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b0000),(l2b_l2d_fuse_rid_d[6:3] == 4'b0001),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_011[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b0000),(l2b_l2d_fuse_rid_d[6:3] == 4'b0001),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_101[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b0010),(l2b_l2d_fuse_rid_d[6:3] == 4'b0011),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_001[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b0010),(l2b_l2d_fuse_rid_d[6:3] == 4'b0011),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_110[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b0100),(l2b_l2d_fuse_rid_d[6:3] == 4'b0101),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_010[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b0100),(l2b_l2d_fuse_rid_d[6:3] == 4'b0101),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_100[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b0110),(l2b_l2d_fuse_rid_d[6:3] == 4'b0111),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_000[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b0110),(l2b_l2d_fuse_rid_d[6:3] == 4'b0111),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_131[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b1000),(l2b_l2d_fuse_rid_d[6:3] == 4'b1001),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_031[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b1000),(l2b_l2d_fuse_rid_d[6:3] == 4'b1001),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_121[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b1010),(l2b_l2d_fuse_rid_d[6:3] == 4'b1011),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_021[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b1010),(l2b_l2d_fuse_rid_d[6:3] == 4'b1011),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_130[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b1100),(l2b_l2d_fuse_rid_d[6:3] == 4'b1101),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_030[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b1100),(l2b_l2d_fuse_rid_d[6:3] == 4'b1101),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_120[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b1110),(l2b_l2d_fuse_rid_d[6:3] == 4'b1111),l2b_l2d_fuse_rid_d[2:0]};
//assign fuse_l2d_rid_020[4:0] = {(l2b_l2d_fuse_rid_d[6:3] == 4'b1110),(l2b_l2d_fuse_rid_d[6:3] == 4'b1111),l2b_l2d_fuse_rid_d[2:0]};


n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_0 
	(
	.dout	(itis0000),
	.din0	(4'b0000),
	.din1	(l2b_l2d_fuse_rid_d[6:3])
	);

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_1 
        (
        .dout   (itis0001),
        .din0   (4'b0001),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_2 
        (
        .dout   (itis0010),
        .din0   (4'b0010),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_3 
        (
        .dout   (itis0011),
        .din0   (4'b0011),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_4 
        (
        .dout   (itis0100),
        .din0   (4'b0100),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_5 
        (
        .dout   (itis0101),
        .din0   (4'b0101),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_6 
        (
        .dout   (itis0110),
        .din0   (4'b0110),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );
n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_7 
        (
        .dout   (itis0111),
        .din0   (4'b0111),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_8 
        (
        .dout   (itis1000),
        .din0   (4'b1000),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_9 
        (
        .dout   (itis1001),
        .din0   (4'b1001),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_02 
        (
        .dout   (itis1010),
        .din0   (4'b1010),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_03 
        (
        .dout   (itis1011),
        .din0   (4'b1011),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_04 
        (
        .dout   (itis1100),
        .din0   (4'b1100),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_05 
        (
        .dout   (itis1101),
        .din0   (4'b1101),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );

n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_06 
        (
        .dout   (itis1110),
        .din0   (4'b1110),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );
n2_l2d_sp_512kb_cust_cmp_macro__width_4 cmp_l2b_l2d_fuse_rid_d_07 
        (
        .dout   (itis1111),
        .din0   (4'b1111),
        .din1   (l2b_l2d_fuse_rid_d[6:3])
        );


assign fuse_l2d_rid_111[4:0] = {itis0000,itis0001,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_011[4:0] = {itis0000,itis0001,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_101[4:0] = {itis0010,itis0011,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_001[4:0] = {itis0010,itis0011,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_110[4:0] = {itis0100,itis0101,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_010[4:0] = {itis0100,itis0101,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_100[4:0] = {itis0110,itis0111,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_000[4:0] = {itis0110,itis0111,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_131[4:0] = {itis1000,itis1001,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_031[4:0] = {itis1000,itis1001,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_121[4:0] = {itis1010,itis1011,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_021[4:0] = {itis1010,itis1011,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_130[4:0] = {itis1100,itis1101,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_030[4:0] = {itis1100,itis1101,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_120[4:0] = {itis1110,itis1111,l2b_l2d_fuse_rid_d[2:0]};
assign fuse_l2d_rid_020[4:0] = {itis1110,itis1111,l2b_l2d_fuse_rid_d[2:0]};


assign fuse_l2d_data_in_100[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_110[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_101[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_111[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_120[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_121[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_130[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_131[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_000[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_001[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_010[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_011[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_020[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_021[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_030[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];
assign fuse_l2d_data_in_031[9:0] = l2b_l2d_fuse_l2d_data_in_d[9:0];

assign fuse_l2d_wren_100 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_110 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_101 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_111 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_120 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_121 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_130 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_131 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_000 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_001 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_010 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_011 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_020 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_021 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_030 = l2b_l2d_fuse_l2d_wren_d;
assign fuse_l2d_wren_031 = l2b_l2d_fuse_l2d_wren_d;

assign fuse_l2d_reset_000_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_001_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_010_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_011_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_020_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_021_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_030_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_031_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_100_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_101_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_110_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_111_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_120_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_121_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_130_l = l2b_l2d_fuse_reset_l;
assign fuse_l2d_reset_131_l = l2b_l2d_fuse_reset_l;
       

//assign stage1_mux_sel0 = |(fuse_l2d_rid_131[4:3]); 
//assign stage1_mux_sel1 = |(fuse_l2d_rid_121[4:3]); 
//assign stage1_mux_sel2 = ~(stage1_mux_sel0 | stage1_mux_sel1);

n2_l2d_sp_512kb_cust_inv_macro__width_1 inv_l2b_l2d_fuse_rid_d_0n 
	(
	.dout	(l2b_l2d_fuse_rid_d_0n),
	.din	(l2b_l2d_fuse_rid_d[0])
	);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_131 
	(
	.dout	(or_fuse_l2d_rid_131),
	.din0	(fuse_l2d_rid_131[4]),
	.din1	(fuse_l2d_rid_131[3])
	);
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_131 
	(
	.dout	(stage1_mux_sel0),
	.din0	(or_fuse_l2d_rid_131),
	.din1	(l2b_l2d_fuse_rid_d[0])
	);	

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_121 
        (
        .dout   (or_fuse_l2d_rid_121),
        .din0   (fuse_l2d_rid_121[4]),
        .din1   (fuse_l2d_rid_121[3])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_121 
	(
	.dout	(stage1_mux_sel1),
	.din0	(or_fuse_l2d_rid_121),
	.din1	(l2b_l2d_fuse_rid_d[0])
	);
		
n2_l2d_sp_512kb_cust_nor_macro__width_1 or_stage1_mux_sel2 
        (
        .dout   (stage1_mux_sel2),
        .din0   (stage1_mux_sel0),
        .din1   (stage1_mux_sel1)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10       mux_fdout_stage1  
        (
        .dout   (fdout_stage1[9:0]),
        .din0   (fdout_131[9:0]),
        .din1   (fdout_121[9:0]),
        .din2   (10'b0),
        .sel0   (stage1_mux_sel0),
        .sel1   (stage1_mux_sel1),
        .sel2   (stage1_mux_sel2)
        );

//assign stage2_mux_sel0 = |(fuse_l2d_rid_031[4:3]);
//assign stage2_mux_sel1 = |(fuse_l2d_rid_021[4:3]);
//assign stage2_mux_sel2 = ~(stage2_mux_sel0 | stage2_mux_sel1);


n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_031 
	(
	.dout	(or_fuse_l2d_rid_031),
	.din0	(fuse_l2d_rid_031[4]),
	.din1	(fuse_l2d_rid_031[3])
	);
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_031 
	(
	.dout	(stage2_mux_sel0),
	.din0	(or_fuse_l2d_rid_031),
	.din1	(l2b_l2d_fuse_rid_d_0n)
	);	

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_021 
        (
        .dout   (or_fuse_l2d_rid_021),
        .din0   (fuse_l2d_rid_021[4]),
        .din1   (fuse_l2d_rid_021[3])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_021 
	(
	.dout	(stage2_mux_sel1),
	.din0	(or_fuse_l2d_rid_021),
	.din1	(l2b_l2d_fuse_rid_d_0n)
	);	
	

n2_l2d_sp_512kb_cust_nor_macro__width_1 or_stage2_mux_sel2 
        (
        .dout   (stage2_mux_sel2),
        .din0   (stage2_mux_sel0),
        .din1   (stage2_mux_sel1)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10       mux_fdout_stage2  
        (
        .dout   (fdout_stage2[9:0]),
        .din0   (fdout_031[9:0]),
        .din1   (fdout_021[9:0]),
        .din2   (fdout_stage1[9:0]),
        .sel0   (stage2_mux_sel0),
        .sel1   (stage2_mux_sel1),
        .sel2   (stage2_mux_sel2)
        );

//assign stage3_mux_sel0 = |(fuse_l2d_rid_130[4:3]);
//assign stage3_mux_sel1 = |(fuse_l2d_rid_120[4:3]);
//assign stage3_mux_sel2 = ~(stage3_mux_sel0 | stage3_mux_sel1);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_130 
	(
	.dout	(or_fuse_l2d_rid_130),
	.din0	(fuse_l2d_rid_130[4]),
	.din1	(fuse_l2d_rid_130[3])
	);
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_130 
	(
	.dout	(stage3_mux_sel0),
	.din0	(or_fuse_l2d_rid_130),
	.din1	(l2b_l2d_fuse_rid_d[0])
	);	

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_120 
        (
        .dout   (or_fuse_l2d_rid_120),
        .din0   (fuse_l2d_rid_120[4]),
        .din1   (fuse_l2d_rid_120[3])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_120 
	(
	.dout	(stage3_mux_sel1),
	.din0	(or_fuse_l2d_rid_120),
	.din1	(l2b_l2d_fuse_rid_d[0])
	);
	
n2_l2d_sp_512kb_cust_nor_macro__width_1 or_stage3_mux_sel2 
        (
        .dout   (stage3_mux_sel2),
        .din0   (stage3_mux_sel0),
        .din1   (stage3_mux_sel1)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10       mux_fdout_stage3  
        (
        .dout   (fdout_stage3[9:0]),
        .din0   (fdout_130[9:0]),
        .din1   (fdout_120[9:0]),
        .din2   (fdout_stage2[9:0]),
        .sel0   (stage3_mux_sel0),
        .sel1   (stage3_mux_sel1),
        .sel2   (stage3_mux_sel2)
        );

//assign stage4_mux_sel0 = |(fuse_l2d_rid_030[4:3]);
//assign stage4_mux_sel1 = |(fuse_l2d_rid_020[4:3]);
//assign stage4_mux_sel2 = ~(stage4_mux_sel0 | stage4_mux_sel1);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_030 
	(
	.dout	(or_fuse_l2d_rid_030),
	.din0	(fuse_l2d_rid_030[4]),
	.din1	(fuse_l2d_rid_030[3])
	);
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_030 
	(
	.dout	(stage4_mux_sel0),
	.din0	(or_fuse_l2d_rid_030),
	.din1	(l2b_l2d_fuse_rid_d_0n)
	);	

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_020 
        (
        .dout   (or_fuse_l2d_rid_020),
        .din0   (fuse_l2d_rid_020[4]),
        .din1   (fuse_l2d_rid_020[3])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_020 
	(
	.dout	(stage4_mux_sel1),
	.din0	(or_fuse_l2d_rid_020),
	.din1	(l2b_l2d_fuse_rid_d_0n)
	);
	
n2_l2d_sp_512kb_cust_nor_macro__width_1 or_stage4_mux_sel2 
        (
        .dout   (stage4_mux_sel2),
        .din0   (stage4_mux_sel0),
        .din1   (stage4_mux_sel1)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10       mux_fdout_stage4  
        (
        .dout   (fdout_stage4[9:0]),
        .din0   (fdout_030[9:0]),
        .din1   (fdout_020[9:0]),
        .din2   (fdout_stage3[9:0]),
        .sel0   (stage4_mux_sel0),
        .sel1   (stage4_mux_sel1),
        .sel2   (stage4_mux_sel2)
        );

// Right to left

//assign stage10_mux_sel0 = |(fuse_l2d_rid_010[4:3]);
//assign stage10_mux_sel1 = |(fuse_l2d_rid_000[4:3]);
//assign stage10_mux_sel2 = ~(stage10_mux_sel0 | stage10_mux_sel1);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_010 
	(
	.dout	(or_fuse_l2d_rid_010),
	.din0	(fuse_l2d_rid_010[4]),
	.din1	(fuse_l2d_rid_010[3])
	);
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_010 
	(
	.dout	(stage10_mux_sel0),
	.din0	(or_fuse_l2d_rid_010),
	.din1	(l2b_l2d_fuse_rid_d_0n)
	);	

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_000 
        (
        .dout   (or_fuse_l2d_rid_000),
        .din0   (fuse_l2d_rid_000[4]),
        .din1   (fuse_l2d_rid_000[3])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_000 
	(
	.dout	(stage10_mux_sel1),
	.din0	(or_fuse_l2d_rid_000),
	.din1	(l2b_l2d_fuse_rid_d_0n)
	);
	
n2_l2d_sp_512kb_cust_nor_macro__width_1 or_stage10_mux_sel2 
        (
        .dout   (stage10_mux_sel2),
        .din0   (stage10_mux_sel0),
        .din1   (stage10_mux_sel1)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10       mux_fdout_stage10  
        (
        .dout   (fdout_stage10[9:0]),
        .din0   (fdout_010[9:0]),
        .din1   (fdout_000[9:0]),
        .din2   (10'b0),
        .sel0   (stage10_mux_sel0),
        .sel1   (stage10_mux_sel1),
        .sel2   (stage10_mux_sel2)
        );

//assign stage20_mux_sel0 = |(fuse_l2d_rid_110[4:3]);
//assign stage20_mux_sel1 = |(fuse_l2d_rid_100[4:3]);
//assign stage20_mux_sel2 = ~(stage20_mux_sel0 | stage20_mux_sel1);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_110 
	(
	.dout	(or_fuse_l2d_rid_110),
	.din0	(fuse_l2d_rid_110[4]),
	.din1	(fuse_l2d_rid_110[3])
	);
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_110 
	(
	.dout	(stage20_mux_sel0),
	.din0	(or_fuse_l2d_rid_110),
	.din1	(l2b_l2d_fuse_rid_d[0])
	);	

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_100 
        (
        .dout   (or_fuse_l2d_rid_100),
        .din0   (fuse_l2d_rid_100[4]),
        .din1   (fuse_l2d_rid_100[3])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_100 
	(
	.dout	(stage20_mux_sel1),
	.din0	(or_fuse_l2d_rid_100),
	.din1	(l2b_l2d_fuse_rid_d[0])
	);
	
n2_l2d_sp_512kb_cust_nor_macro__width_1 or_stage20_mux_sel2 
        (
        .dout   (stage20_mux_sel2),
        .din0   (stage20_mux_sel0),
        .din1   (stage20_mux_sel1)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10       mux_fdout_stage20  
        (
        .dout   (fdout_stage20[9:0]),
        .din0   (fdout_110[9:0]),
        .din1   (fdout_100[9:0]),
        .din2   (fdout_stage10[9:0]),
        .sel0   (stage20_mux_sel0),
        .sel1   (stage20_mux_sel1),
        .sel2   (stage20_mux_sel2)
        );

//assign stage30_mux_sel0 = |(fuse_l2d_rid_011[4:3]);
//assign stage30_mux_sel1 = |(fuse_l2d_rid_001[4:3]);
//assign stage30_mux_sel2 = ~(stage30_mux_sel0 | stage30_mux_sel1);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_011 
	(
	.dout	(or_fuse_l2d_rid_011),
	.din0	(fuse_l2d_rid_011[4]),
	.din1	(fuse_l2d_rid_011[3])
	);
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_011 
	(
	.dout	(stage30_mux_sel0),
	.din0	(or_fuse_l2d_rid_011),
	.din1	(l2b_l2d_fuse_rid_d_0n)
	);	

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_001 
        (
        .dout   (or_fuse_l2d_rid_001),
        .din0   (fuse_l2d_rid_001[4]),
        .din1   (fuse_l2d_rid_001[3])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_001 
	(
	.dout	(stage30_mux_sel1),
	.din0	(or_fuse_l2d_rid_001),
	.din1	(l2b_l2d_fuse_rid_d_0n)
	);
	
n2_l2d_sp_512kb_cust_nor_macro__width_1 or_1stage20_mux_sel2 
        (
        .dout   (stage30_mux_sel2),
        .din0   (stage30_mux_sel0),
        .din1   (stage30_mux_sel1)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10       mux_fdout_stage30  
        (
        .dout   (fdout_stage30[9:0]),
        .din0   (fdout_011[9:0]),
        .din1   (fdout_001[9:0]),
        .din2   (fdout_stage20[9:0]),
        .sel0   (stage30_mux_sel0),
        .sel1   (stage30_mux_sel1),
        .sel2   (stage30_mux_sel2)
        );

//assign stage40_mux_sel0 = |(fuse_l2d_rid_111[4:3]);
//assign stage40_mux_sel1 = |(fuse_l2d_rid_101[4:3]);
//assign stage40_mux_sel2 = ~(stage40_mux_sel0 | stage40_mux_sel1);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_111 
	(
	.dout	(or_fuse_l2d_rid_111),
	.din0	(fuse_l2d_rid_111[4]),
	.din1	(fuse_l2d_rid_111[3])
	);
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_111 
	(
	.dout	(stage40_mux_sel0),
	.din0	(or_fuse_l2d_rid_111),
	.din1	(l2b_l2d_fuse_rid_d[0])
	);	

n2_l2d_sp_512kb_cust_or_macro__width_1 or_rid_101 
        (
        .dout   (or_fuse_l2d_rid_101),
        .din0   (fuse_l2d_rid_101[4]),
        .din1   (fuse_l2d_rid_101[3])
        );
	
n2_l2d_sp_512kb_cust_and_macro__width_1 and_rid_101 
	(
	.dout	(stage40_mux_sel1),
	.din0	(or_fuse_l2d_rid_101),
	.din1	(l2b_l2d_fuse_rid_d[0])
	);
	
n2_l2d_sp_512kb_cust_nor_macro__width_1 or_1stage40_mux_sel2 
        (
        .dout   (stage40_mux_sel2),
        .din0   (stage40_mux_sel0),
        .din1   (stage40_mux_sel1)
        );


n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10       mux_fdout_stage40  
        (
        .dout   (fdout_stage40[9:0]),
        .din0   (fdout_111[9:0]),
        .din1   (fdout_101[9:0]),
        .din2   (fdout_stage30[9:0]),
        .sel0   (stage40_mux_sel0),
        .sel1   (stage40_mux_sel1),
        .sel2   (stage40_mux_sel2)
        );

n2_l2d_sp_512kb_cust_inv_macro__width_1 inv_l2b_l2d_fuse_rid_d_6n 
	(
	.dout	(l2b_l2d_fuse_rid_d_6n),
	.din	(l2b_l2d_fuse_rid_d[6])
	);

n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_10       mux_fdout_fnl  
        (
        .dout   (efc_fuse_data[9:0]),
        .din0   (fdout_stage40[9:0]),
        .din1   (fdout_stage4[9:0]),
        .sel0   (l2b_l2d_fuse_rid_d_6n),
        .sel1   (l2b_l2d_fuse_rid_d[6])
        );

 
assign 		delout00 = delout20_rgt;
assign 		delout01 = delout20_rgt;
assign 		delout10 = delout31_rgt;
assign 		delout11 = delout31_rgt;
assign 		delout20 = delout20_lft;
assign 		delout21 = delout20_lft;
assign 		delout30 = delout31_lft;
assign 		delout31 = delout31_lft;

n2_l2d_tstmod_cust tstmod
      (
      .rd_wr_c3 	(l2t_l2d_rd_wr_c3),
      .wayerr_c3 	(wayerr_c3 ),
      .wr_inhibit 	(tcu_array_wr_inhibit ),
      .coloff_c3 	(cache_col_offset_c3[3:0]),
      .l2clk 		(l2clk),
      .scanen 		(tcu_scan_en),
      .si 		(so_q23 ),
      .siclk 		(tcu_aclk),
      .soclk 		(tcu_bclk),
      .so 		(so_tstmod ),
      .delout20_rgt 	(delout20_rgt ),
      .delout31_lft 	(delout31_lft ),
      .delout31_rgt 	(delout31_rgt ),
      .delout20_lft	(delout20_lft)
      ) ;

// scanorder start
//  ff_cache_cache_rd_wr_c4_scanin
//  ff_cache_set_c3_scanin[8]
//  ff_cache_set_c3_scanin[7]
//  ff_cache_set_c3_scanin[6]
//  ff_cache_set_c3_scanin[5]
//  ff_cache_set_c3_scanin[4]
//  ff_cache_set_c3_scanin[3]
//  ff_cache_set_c3_scanin[2]
//  ff_cache_set_c3_scanin[1]
//  ff_cache_set_c3_scanin[0]
//  ff_cache_word_en_c3_scanin[1]
//  ff_cache_word_en_c3_scanin[3]
//  ff_cache_word_en_c3_scanin[5]
//  ff_cache_word_en_c3_scanin[7]
//  ff_cache_word_en_c3_scanin[9]
//  ff_cache_word_en_c3_scanin[11]
//  ff_cache_word_en_c3_scanin[13]
//  ff_cache_word_en_c3_scanin[15]
//  ff_cache_col_offset_c3_scanin[0]
//  ff_cache_col_offset_c4_scanin[0]
//  ff_cache_col_offset_c5_muxsel_scanin[0]
//  ff_cache_col_offset_c5_muxsel_scanin[1]
//  ff_cache_col_offset_c4_scanin[1]
//  ff_cache_col_offset_c3_scanin[1]
//  ff_cache_col_offset_c3_scanin[2]
//  ff_cache_col_offset_c4_scanin[2]
//  ff_cache_col_offset_c5_muxsel_scanin[2]
//  ff_cache_col_offset_c5_muxsel_scanin[3]
//  ff_cache_col_offset_c4_scanin[3]
//  ff_cache_col_offset_c3_scanin[3]
//  ff_cache_col_offset_all_c4_scanin
//  ff_cache_col_offset_all_c5_scanin
//  ff_cache_col_offset_all_c6_scanin
//  ff_cache_col_offset_all_c7_scanin
//  ff_cache_word_en_c3_scanin[0]
//  ff_cache_word_en_c3_scanin[2]
//  ff_cache_word_en_c3_scanin[4]
//  ff_cache_word_en_c3_scanin[6]
//  ff_cache_word_en_c3_scanin[8]
//  ff_cache_word_en_c3_scanin[10]
//  ff_cache_word_en_c3_scanin[12]
//  ff_cache_word_en_c3_scanin[14]
//  ff_cache_col_offset_c52_scanin[1]	
//  ff_cache_col_offset_c52_scanin[0]	

//  ff_cache_col_offset_c52_topsel_scanin
//  ff_cache_fb_hit_c4_scanin
//  ff_cache_fb_hit_c5_scanin
//  ff_cache_fb_hit_c52_scanin
//  ff_cache_sel_fbdecc_c4_scanin
//  ff_cache_sel_fbdecc_c5_scanin

//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[4]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[4]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[4]

//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[4]

//  ff_l2t_l2d_stdecc_c3_scanin[77:39] 	
//  ff_cache_col_offset_c5_023_scanin[0]
//  ff_cache_col_offset_c5_023_scanin[2]
//  ff_cache_col_offset_c4_023_scanin[0]
//  ff_cache_col_offset_c4_023_scanin[2]
//  ff_cache_col_offset_c4_tog_023_scanin[0]
//  ff_cache_cache_rd_wr_c5_20_scanin
//  ff_cache_col_offset_c5_023_scanin[1]
//  ff_cache_col_offset_c5_023_scanin[3]
//  ff_cache_col_offset_c4_023_scanin[1]
//  ff_cache_col_offset_c4_023_scanin[3]
//  ff_cache_col_offset_c4_tog_023_scanin[1]

//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[14]

//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[14]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[14]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[14]

//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[14]

//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[14]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[14]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[14]


//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[4]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[4]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[4]


//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[4]


//  ff_l2d_decc_out_c6_lo0_2_scanin[0]
//  ff_l2d_decc_out_c6_lo0_4_scanin[0]
//  ff_l2d_decc_out_c6_hi0_2_scanin[0]
//  ff_l2d_decc_out_c6_hi0_4_scanin[0]
//  ff_l2d_decc_out_c6_lo1_2_scanin[0]
//  ff_l2d_decc_out_c6_lo1_4_scanin[0]
//  ff_l2d_decc_out_c6_hi1_2_scanin[0]
//  ff_l2d_decc_out_c6_hi1_4_scanin[0]
//  ff_l2d_decc_out_c6_lo0_2_scanin[1]
//  ff_l2d_decc_out_c6_lo0_4_scanin[1]
//  ff_l2d_decc_out_c6_hi0_2_scanin[1]
//  ff_l2d_decc_out_c6_hi0_4_scanin[1]
//  ff_l2d_decc_out_c6_lo1_2_scanin[1]
//  ff_l2d_decc_out_c6_lo1_4_scanin[1]
//  ff_l2d_decc_out_c6_hi1_2_scanin[1]
//  ff_l2d_decc_out_c6_hi1_4_scanin[1]
//  ff_l2d_decc_out_c6_lo0_2_scanin[2]
//  ff_l2d_decc_out_c6_lo0_4_scanin[2]
//  ff_l2d_decc_out_c6_hi0_2_scanin[2]
//  ff_l2d_decc_out_c6_hi0_4_scanin[2]
//  ff_l2d_decc_out_c6_lo1_2_scanin[2]
//  ff_l2d_decc_out_c6_lo1_4_scanin[2]
//  ff_l2d_decc_out_c6_hi1_2_scanin[2]
//  ff_l2d_decc_out_c6_hi1_4_scanin[2]
//  ff_l2d_decc_out_c6_lo0_2_scanin[3]
//  ff_l2d_decc_out_c6_lo0_4_scanin[3]
//  ff_l2d_decc_out_c6_hi0_2_scanin[3]
//  ff_l2d_decc_out_c6_hi0_4_scanin[3]
//  ff_l2d_decc_out_c6_lo1_2_scanin[3]
//  ff_l2d_decc_out_c6_lo1_4_scanin[3]
//  ff_l2d_decc_out_c6_hi1_2_scanin[3]
//  ff_l2d_decc_out_c6_hi1_4_scanin[3]
//  ff_l2d_decc_out_c6_lo0_2_scanin[4]
//  ff_l2d_decc_out_c6_lo0_4_scanin[4]
//  ff_l2d_decc_out_c6_hi0_2_scanin[4]
//  ff_l2d_decc_out_c6_hi0_4_scanin[4]
//  ff_l2d_decc_out_c6_lo1_2_scanin[4]
//  ff_l2d_decc_out_c6_lo1_4_scanin[4]
//  ff_l2d_decc_out_c6_hi1_2_scanin[4]
//  ff_l2d_decc_out_c6_hi1_4_scanin[4]
//  ff_l2d_decc_out_c6_lo0_2_scanin[5]
//  ff_l2d_decc_out_c6_lo0_4_scanin[5]
//  ff_l2d_decc_out_c6_hi0_2_scanin[5]
//  ff_l2d_decc_out_c6_hi0_4_scanin[5]
//  ff_l2d_decc_out_c6_lo1_2_scanin[5]
//  ff_l2d_decc_out_c6_lo1_4_scanin[5]
//  ff_l2d_decc_out_c6_hi1_2_scanin[5]
//  ff_l2d_decc_out_c6_hi1_4_scanin[5]
//  ff_l2d_decc_out_c6_lo0_2_scanin[6]
//  ff_l2d_decc_out_c6_lo0_4_scanin[6]
//  ff_l2d_decc_out_c6_hi0_2_scanin[6]
//  ff_l2d_decc_out_c6_hi0_4_scanin[6]
//  ff_l2d_decc_out_c6_lo1_2_scanin[6]
//  ff_l2d_decc_out_c6_lo1_4_scanin[6]
//  ff_l2d_decc_out_c6_hi1_2_scanin[6]
//  ff_l2d_decc_out_c6_hi1_4_scanin[6]
//  ff_l2d_decc_out_c6_lo0_2_scanin[7]
//  ff_l2d_decc_out_c6_lo0_4_scanin[7]
//  ff_l2d_decc_out_c6_hi0_2_scanin[7]
//  ff_l2d_decc_out_c6_hi0_4_scanin[7]
//  ff_l2d_decc_out_c6_lo1_2_scanin[7]
//  ff_l2d_decc_out_c6_lo1_4_scanin[7]
//  ff_l2d_decc_out_c6_hi1_2_scanin[7]
//  ff_l2d_decc_out_c6_hi1_4_scanin[7]
//  ff_l2d_decc_out_c6_lo0_2_scanin[8]
//  ff_l2d_decc_out_c6_lo0_4_scanin[8]
//  ff_l2d_decc_out_c6_hi0_2_scanin[8]
//  ff_l2d_decc_out_c6_hi0_4_scanin[8]
//  ff_l2d_decc_out_c6_lo1_2_scanin[8]
//  ff_l2d_decc_out_c6_lo1_4_scanin[8]
//  ff_l2d_decc_out_c6_hi1_2_scanin[8]
//  ff_l2d_decc_out_c6_hi1_4_scanin[8]
//  ff_l2d_decc_out_c6_lo0_2_scanin[9]
//  ff_l2d_decc_out_c6_lo0_4_scanin[9]
//  ff_l2d_decc_out_c6_hi0_2_scanin[9]
//  ff_l2d_decc_out_c6_hi0_4_scanin[9]
//  ff_l2d_decc_out_c6_lo1_2_scanin[9]
//  ff_l2d_decc_out_c6_lo1_4_scanin[9]
//  ff_l2d_decc_out_c6_hi1_2_scanin[9]
//  ff_l2d_decc_out_c6_hi1_4_scanin[9]

//  ff_l2d_decc_out_c6_lo0_2_scanin[10]
//  ff_l2d_decc_out_c6_lo0_4_scanin[10]
//  ff_l2d_decc_out_c6_hi0_2_scanin[10]
//  ff_l2d_decc_out_c6_hi0_4_scanin[10]
//  ff_l2d_decc_out_c6_lo1_2_scanin[10]
//  ff_l2d_decc_out_c6_lo1_4_scanin[10]
//  ff_l2d_decc_out_c6_hi1_2_scanin[10]
//  ff_l2d_decc_out_c6_hi1_4_scanin[10]
//  ff_l2d_decc_out_c6_lo0_2_scanin[11]
//  ff_l2d_decc_out_c6_lo0_4_scanin[11]
//  ff_l2d_decc_out_c6_hi0_2_scanin[11]
//  ff_l2d_decc_out_c6_hi0_4_scanin[11]
//  ff_l2d_decc_out_c6_lo1_2_scanin[11]
//  ff_l2d_decc_out_c6_lo1_4_scanin[11]
//  ff_l2d_decc_out_c6_hi1_2_scanin[11]
//  ff_l2d_decc_out_c6_hi1_4_scanin[11]
//  ff_l2d_decc_out_c6_lo0_2_scanin[12]
//  ff_l2d_decc_out_c6_lo0_4_scanin[12]
//  ff_l2d_decc_out_c6_hi0_2_scanin[12]
//  ff_l2d_decc_out_c6_hi0_4_scanin[12]
//  ff_l2d_decc_out_c6_lo1_2_scanin[12]
//  ff_l2d_decc_out_c6_lo1_4_scanin[12]
//  ff_l2d_decc_out_c6_hi1_2_scanin[12]
//  ff_l2d_decc_out_c6_hi1_4_scanin[12]
//  ff_l2d_decc_out_c6_lo0_2_scanin[13]
//  ff_l2d_decc_out_c6_lo0_4_scanin[13]
//  ff_l2d_decc_out_c6_hi0_2_scanin[13]
//  ff_l2d_decc_out_c6_hi0_4_scanin[13]
//  ff_l2d_decc_out_c6_lo1_2_scanin[13]
//  ff_l2d_decc_out_c6_lo1_4_scanin[13]
//  ff_l2d_decc_out_c6_hi1_2_scanin[13]
//  ff_l2d_decc_out_c6_hi1_4_scanin[13]
//  ff_l2d_decc_out_c6_lo0_2_scanin[14]
//  ff_l2d_decc_out_c6_lo0_4_scanin[14]
//  ff_l2d_decc_out_c6_hi0_2_scanin[14]
//  ff_l2d_decc_out_c6_hi0_4_scanin[14]
//  ff_l2d_decc_out_c6_lo1_2_scanin[14]
//  ff_l2d_decc_out_c6_lo1_4_scanin[14]
//  ff_l2d_decc_out_c6_hi1_2_scanin[14]
//  ff_l2d_decc_out_c6_hi1_4_scanin[14]
//  ff_l2d_decc_out_c6_lo0_2_scanin[15]
//  ff_l2d_decc_out_c6_lo0_4_scanin[15]
//  ff_l2d_decc_out_c6_hi0_2_scanin[15]
//  ff_l2d_decc_out_c6_hi0_4_scanin[15]
//  ff_l2d_decc_out_c6_lo1_2_scanin[15]
//  ff_l2d_decc_out_c6_lo1_4_scanin[15]
//  ff_l2d_decc_out_c6_hi1_2_scanin[15]
//  ff_l2d_decc_out_c6_hi1_4_scanin[15]
//  ff_l2d_decc_out_c6_lo0_2_scanin[16]
//  ff_l2d_decc_out_c6_lo0_4_scanin[16]
//  ff_l2d_decc_out_c6_hi0_2_scanin[16]
//  ff_l2d_decc_out_c6_hi0_4_scanin[16]
//  ff_l2d_decc_out_c6_lo1_2_scanin[16]
//  ff_l2d_decc_out_c6_lo1_4_scanin[16]
//  ff_l2d_decc_out_c6_hi1_2_scanin[16]
//  ff_l2d_decc_out_c6_hi1_4_scanin[16]
//  ff_l2d_decc_out_c6_lo0_2_scanin[17]
//  ff_l2d_decc_out_c6_lo0_4_scanin[17]
//  ff_l2d_decc_out_c6_hi0_2_scanin[17]
//  ff_l2d_decc_out_c6_hi0_4_scanin[17]
//  ff_l2d_decc_out_c6_lo1_2_scanin[17]
//  ff_l2d_decc_out_c6_lo1_4_scanin[17]
//  ff_l2d_decc_out_c6_hi1_2_scanin[17]
//  ff_l2d_decc_out_c6_hi1_4_scanin[17]
//  ff_l2d_decc_out_c6_lo0_2_scanin[18]
//  ff_l2d_decc_out_c6_lo0_4_scanin[18]
//  ff_l2d_decc_out_c6_hi0_2_scanin[18]
//  ff_l2d_decc_out_c6_hi0_4_scanin[18]
//  ff_l2d_decc_out_c6_lo1_2_scanin[18]
//  ff_l2d_decc_out_c6_lo1_4_scanin[18]
//  ff_l2d_decc_out_c6_hi1_2_scanin[18]
//  ff_l2d_decc_out_c6_hi1_4_scanin[18]
//  ff_l2d_decc_out_c6_lo0_2_scanin[19]
//  ff_l2d_decc_out_c6_lo0_4_scanin[19]
//  ff_l2d_decc_out_c6_hi0_2_scanin[19]
//  ff_l2d_decc_out_c6_hi0_4_scanin[19]

//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[24]


//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[24]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[24]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[24]

//  ff_cache_col_offset_c5_123_scanin[0]
//  ff_cache_col_offset_c5_123_scanin[2]
//  ff_cache_col_offset_c4_123_scanin[0]
//  ff_cache_col_offset_c4_123_scanin[2]
//  ff_cache_col_offset_c4_tog_123_scanin[0]
//  ff_cache_cache_rd_wr_c5_21_scanin
//  ff_cache_col_offset_c5_123_scanin[1]
//  ff_cache_col_offset_c5_123_scanin[3]
//  ff_cache_col_offset_c4_123_scanin[1]
//  ff_cache_col_offset_c4_123_scanin[3]
//  ff_cache_col_offset_c4_tog_123_scanin[1]

//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[34]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[34]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[34]

//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[34]

//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[34]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[34]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[34]

//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[34]

//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[24]


//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[24]
//  ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[24]
//  ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[24]

//  ff_l2d_decc_out_c6_lo1_2_scanin[19]
//  ff_l2d_decc_out_c6_lo1_4_scanin[19]
//  ff_l2d_decc_out_c6_hi1_2_scanin[19]
//  ff_l2d_decc_out_c6_hi1_4_scanin[19]
//  ff_l2d_decc_out_c6_lo0_2_scanin[20]
//  ff_l2d_decc_out_c6_lo0_4_scanin[20]
//  ff_l2d_decc_out_c6_hi0_2_scanin[20]
//  ff_l2d_decc_out_c6_hi0_4_scanin[20]
//  ff_l2d_decc_out_c6_lo1_2_scanin[20]
//  ff_l2d_decc_out_c6_lo1_4_scanin[20]
//  ff_l2d_decc_out_c6_hi1_2_scanin[20]
//  ff_l2d_decc_out_c6_hi1_4_scanin[20]
//  ff_l2d_decc_out_c6_lo0_2_scanin[21]
//  ff_l2d_decc_out_c6_lo0_4_scanin[21]
//  ff_l2d_decc_out_c6_hi0_2_scanin[21]
//  ff_l2d_decc_out_c6_hi0_4_scanin[21]
//  ff_l2d_decc_out_c6_lo1_2_scanin[21]
//  ff_l2d_decc_out_c6_lo1_4_scanin[21]
//  ff_l2d_decc_out_c6_hi1_2_scanin[21]
//  ff_l2d_decc_out_c6_hi1_4_scanin[21]
//  ff_l2d_decc_out_c6_lo0_2_scanin[22]
//  ff_l2d_decc_out_c6_lo0_4_scanin[22]
//  ff_l2d_decc_out_c6_hi0_2_scanin[22]
//  ff_l2d_decc_out_c6_hi0_4_scanin[22]
//  ff_l2d_decc_out_c6_lo1_2_scanin[22]
//  ff_l2d_decc_out_c6_lo1_4_scanin[22]
//  ff_l2d_decc_out_c6_hi1_2_scanin[22]
//  ff_l2d_decc_out_c6_hi1_4_scanin[22]
//  ff_l2d_decc_out_c6_lo0_2_scanin[23]
//  ff_l2d_decc_out_c6_lo0_4_scanin[23]
//  ff_l2d_decc_out_c6_hi0_2_scanin[23]
//  ff_l2d_decc_out_c6_hi0_4_scanin[23]
//  ff_l2d_decc_out_c6_lo1_2_scanin[23]
//  ff_l2d_decc_out_c6_lo1_4_scanin[23]
//  ff_l2d_decc_out_c6_hi1_2_scanin[23]
//  ff_l2d_decc_out_c6_hi1_4_scanin[23]
//  ff_l2d_decc_out_c6_lo0_2_scanin[24]
//  ff_l2d_decc_out_c6_lo0_4_scanin[24]
//  ff_l2d_decc_out_c6_hi0_2_scanin[24]
//  ff_l2d_decc_out_c6_hi0_4_scanin[24]
//  ff_l2d_decc_out_c6_lo1_2_scanin[24]
//  ff_l2d_decc_out_c6_lo1_4_scanin[24]
//  ff_l2d_decc_out_c6_hi1_2_scanin[24]
//  ff_l2d_decc_out_c6_hi1_4_scanin[24]
//  ff_l2d_decc_out_c6_lo0_2_scanin[25]
//  ff_l2d_decc_out_c6_lo0_4_scanin[25]
//  ff_l2d_decc_out_c6_hi0_2_scanin[25]
//  ff_l2d_decc_out_c6_hi0_4_scanin[25]
//  ff_l2d_decc_out_c6_lo1_2_scanin[25]
//  ff_l2d_decc_out_c6_lo1_4_scanin[25]
//  ff_l2d_decc_out_c6_hi1_2_scanin[25]
//  ff_l2d_decc_out_c6_hi1_4_scanin[25]
//  ff_l2d_decc_out_c6_lo0_2_scanin[26]
//  ff_l2d_decc_out_c6_lo0_4_scanin[26]
//  ff_l2d_decc_out_c6_hi0_2_scanin[26]
//  ff_l2d_decc_out_c6_hi0_4_scanin[26]
//  ff_l2d_decc_out_c6_lo1_2_scanin[26]
//  ff_l2d_decc_out_c6_lo1_4_scanin[26]
//  ff_l2d_decc_out_c6_hi1_2_scanin[26]
//  ff_l2d_decc_out_c6_hi1_4_scanin[26]
//  ff_l2d_decc_out_c6_lo0_2_scanin[27]
//  ff_l2d_decc_out_c6_lo0_4_scanin[27]
//  ff_l2d_decc_out_c6_hi0_2_scanin[27]
//  ff_l2d_decc_out_c6_hi0_4_scanin[27]
//  ff_l2d_decc_out_c6_lo1_2_scanin[27]
//  ff_l2d_decc_out_c6_lo1_4_scanin[27]
//  ff_l2d_decc_out_c6_hi1_2_scanin[27]
//  ff_l2d_decc_out_c6_hi1_4_scanin[27]
//  ff_l2d_decc_out_c6_lo0_2_scanin[28]
//  ff_l2d_decc_out_c6_lo0_4_scanin[28]
//  ff_l2d_decc_out_c6_hi0_2_scanin[28]
//  ff_l2d_decc_out_c6_hi0_4_scanin[28]
//  ff_l2d_decc_out_c6_lo1_2_scanin[28]
//  ff_l2d_decc_out_c6_lo1_4_scanin[28]
//  ff_l2d_decc_out_c6_hi1_2_scanin[28]
//  ff_l2d_decc_out_c6_hi1_4_scanin[28]
//  ff_l2d_decc_out_c6_lo0_2_scanin[29]
//  ff_l2d_decc_out_c6_lo0_4_scanin[29]

//  ff_l2d_decc_out_c6_hi0_2_scanin[29]
//  ff_l2d_decc_out_c6_hi0_4_scanin[29]
//  ff_l2d_decc_out_c6_lo1_2_scanin[29]
//  ff_l2d_decc_out_c6_lo1_4_scanin[29]
//  ff_l2d_decc_out_c6_hi1_2_scanin[29]
//  ff_l2d_decc_out_c6_hi1_4_scanin[29]
//  ff_l2d_decc_out_c6_lo0_2_scanin[30]
//  ff_l2d_decc_out_c6_lo0_4_scanin[30]
//  ff_l2d_decc_out_c6_hi0_2_scanin[30]
//  ff_l2d_decc_out_c6_hi0_4_scanin[30]
//  ff_l2d_decc_out_c6_lo1_2_scanin[30]
//  ff_l2d_decc_out_c6_lo1_4_scanin[30]
//  ff_l2d_decc_out_c6_hi1_2_scanin[30]
//  ff_l2d_decc_out_c6_hi1_4_scanin[30]
//  ff_l2d_decc_out_c6_lo0_2_scanin[31]
//  ff_l2d_decc_out_c6_lo0_4_scanin[31]
//  ff_l2d_decc_out_c6_hi0_2_scanin[31]
//  ff_l2d_decc_out_c6_hi0_4_scanin[31]
//  ff_l2d_decc_out_c6_lo1_2_scanin[31]
//  ff_l2d_decc_out_c6_lo1_4_scanin[31]
//  ff_l2d_decc_out_c6_hi1_2_scanin[31]
//  ff_l2d_decc_out_c6_hi1_4_scanin[31]
//  ff_l2d_decc_out_c6_lo0_2_scanin[32]
//  ff_l2d_decc_out_c6_lo0_4_scanin[32]
//  ff_l2d_decc_out_c6_hi0_2_scanin[32]
//  ff_l2d_decc_out_c6_hi0_4_scanin[32]
//  ff_l2d_decc_out_c6_lo1_2_scanin[32]
//  ff_l2d_decc_out_c6_lo1_4_scanin[32]
//  ff_l2d_decc_out_c6_hi1_2_scanin[32]
//  ff_l2d_decc_out_c6_hi1_4_scanin[32]
//  ff_l2d_decc_out_c6_lo0_2_scanin[33]
//  ff_l2d_decc_out_c6_lo0_4_scanin[33]
//  ff_l2d_decc_out_c6_hi0_2_scanin[33]
//  ff_l2d_decc_out_c6_hi0_4_scanin[33]
//  ff_l2d_decc_out_c6_lo1_2_scanin[33]
//  ff_l2d_decc_out_c6_lo1_4_scanin[33]
//  ff_l2d_decc_out_c6_hi1_2_scanin[33]
//  ff_l2d_decc_out_c6_hi1_4_scanin[33]
//  ff_l2d_decc_out_c6_lo0_2_scanin[34]
//  ff_l2d_decc_out_c6_lo0_4_scanin[34]
//  ff_l2d_decc_out_c6_hi0_2_scanin[34]
//  ff_l2d_decc_out_c6_hi0_4_scanin[34]
//  ff_l2d_decc_out_c6_lo1_2_scanin[34]
//  ff_l2d_decc_out_c6_lo1_4_scanin[34]
//  ff_l2d_decc_out_c6_hi1_2_scanin[34]
//  ff_l2d_decc_out_c6_hi1_4_scanin[34]
//  ff_l2d_decc_out_c6_lo0_2_scanin[35]
//  ff_l2d_decc_out_c6_lo0_4_scanin[35]
//  ff_l2d_decc_out_c6_hi0_2_scanin[35]
//  ff_l2d_decc_out_c6_hi0_4_scanin[35]
//  ff_l2d_decc_out_c6_lo1_2_scanin[35]
//  ff_l2d_decc_out_c6_lo1_4_scanin[35]
//  ff_l2d_decc_out_c6_hi1_2_scanin[35]
//  ff_l2d_decc_out_c6_hi1_4_scanin[35]
//  ff_l2d_decc_out_c6_lo0_2_scanin[36]
//  ff_l2d_decc_out_c6_lo0_4_scanin[36]
//  ff_l2d_decc_out_c6_hi0_2_scanin[36]
//  ff_l2d_decc_out_c6_hi0_4_scanin[36]
//  ff_l2d_decc_out_c6_lo1_2_scanin[36]
//  ff_l2d_decc_out_c6_lo1_4_scanin[36]
//  ff_l2d_decc_out_c6_hi1_2_scanin[36]
//  ff_l2d_decc_out_c6_hi1_4_scanin[36]
//  ff_l2d_decc_out_c6_lo0_2_scanin[37]
//  ff_l2d_decc_out_c6_lo0_4_scanin[37]
//  ff_l2d_decc_out_c6_hi0_2_scanin[37]
//  ff_l2d_decc_out_c6_hi0_4_scanin[37]
//  ff_l2d_decc_out_c6_lo1_2_scanin[37]
//  ff_l2d_decc_out_c6_lo1_4_scanin[37]
//  ff_l2d_decc_out_c6_hi1_2_scanin[37]
//  ff_l2d_decc_out_c6_hi1_4_scanin[37]
//  ff_l2d_decc_out_c6_lo0_2_scanin[38]
//  ff_l2d_decc_out_c6_lo0_4_scanin[38]
//  ff_l2d_decc_out_c6_hi0_2_scanin[38]
//  ff_l2d_decc_out_c6_hi0_4_scanin[38]
//  ff_l2d_decc_out_c6_lo1_2_scanin[38]
//  ff_l2d_decc_out_c6_lo1_4_scanin[38]
//  ff_l2d_decc_out_c6_hi1_2_scanin[38]
//  ff_l2d_decc_out_c6_hi1_4_scanin[38]
//  so_tstmod
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[24]


//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[24]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[24]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[24]

//  ff_cache_col_offset_c5_101_scanin[0]
//  ff_cache_col_offset_c5_101_scanin[2]
//  ff_cache_col_offset_c4_101_scanin[0]
//  ff_cache_col_offset_c4_101_scanin[2]
//  ff_cache_col_offset_c4_tog_101_scanin[0]
//  ff_cache_cache_rd_wr_c5_01_scanin
//  ff_cache_col_offset_c5_101_scanin[1]
//  ff_cache_col_offset_c5_101_scanin[3]
//  ff_cache_col_offset_c4_101_scanin[1]
//  ff_cache_col_offset_c4_101_scanin[3]
//  ff_cache_col_offset_c4_tog_101_scanin[1]

//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[34]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[34]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[34]

//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[34]

//  ff_l2t_l2d_stdecc_c3_scanin[0:38]

//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[38]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[37]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[36]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[35]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[34]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[34]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[34]

//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[30]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[31]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[32]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[33]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[34]

//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[20]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[21]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[22]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[23]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[24]


//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[29]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[28]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[27]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[26]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[25]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[24]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[24]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[24]

//  ff_l2d_decc_out_c6_lo1_1_scanin[19]
//  ff_l2d_decc_out_c6_lo1_3_scanin[19]
//  ff_l2d_decc_out_c6_hi1_1_scanin[19]
//  ff_l2d_decc_out_c6_hi1_3_scanin[19]
//  ff_l2d_decc_out_c6_lo0_1_scanin[20]
//  ff_l2d_decc_out_c6_lo0_3_scanin[20]
//  ff_l2d_decc_out_c6_hi0_1_scanin[20]
//  ff_l2d_decc_out_c6_hi0_3_scanin[20]
//  ff_l2d_decc_out_c6_lo1_1_scanin[20]
//  ff_l2d_decc_out_c6_lo1_3_scanin[20]
//  ff_l2d_decc_out_c6_hi1_1_scanin[20]
//  ff_l2d_decc_out_c6_hi1_3_scanin[20]
//  ff_l2d_decc_out_c6_lo0_1_scanin[21]
//  ff_l2d_decc_out_c6_lo0_3_scanin[21]
//  ff_l2d_decc_out_c6_hi0_1_scanin[21]
//  ff_l2d_decc_out_c6_hi0_3_scanin[21]
//  ff_l2d_decc_out_c6_lo1_1_scanin[21]
//  ff_l2d_decc_out_c6_lo1_3_scanin[21]
//  ff_l2d_decc_out_c6_hi1_1_scanin[21]
//  ff_l2d_decc_out_c6_hi1_3_scanin[21]
//  ff_l2d_decc_out_c6_lo0_1_scanin[22]
//  ff_l2d_decc_out_c6_lo0_3_scanin[22]
//  ff_l2d_decc_out_c6_hi0_1_scanin[22]
//  ff_l2d_decc_out_c6_hi0_3_scanin[22]
//  ff_l2d_decc_out_c6_lo1_1_scanin[22]
//  ff_l2d_decc_out_c6_lo1_3_scanin[22]
//  ff_l2d_decc_out_c6_hi1_1_scanin[22]
//  ff_l2d_decc_out_c6_hi1_3_scanin[22]
//  ff_l2d_decc_out_c6_lo0_1_scanin[23]
//  ff_l2d_decc_out_c6_lo0_3_scanin[23]
//  ff_l2d_decc_out_c6_hi0_1_scanin[23]
//  ff_l2d_decc_out_c6_hi0_3_scanin[23]
//  ff_l2d_decc_out_c6_lo1_1_scanin[23]
//  ff_l2d_decc_out_c6_lo1_3_scanin[23]
//  ff_l2d_decc_out_c6_hi1_1_scanin[23]
//  ff_l2d_decc_out_c6_hi1_3_scanin[23]
//  ff_l2d_decc_out_c6_lo0_1_scanin[24]
//  ff_l2d_decc_out_c6_lo0_3_scanin[24]
//  ff_l2d_decc_out_c6_hi0_1_scanin[24]
//  ff_l2d_decc_out_c6_hi0_3_scanin[24]
//  ff_l2d_decc_out_c6_lo1_1_scanin[24]
//  ff_l2d_decc_out_c6_lo1_3_scanin[24]
//  ff_l2d_decc_out_c6_hi1_1_scanin[24]
//  ff_l2d_decc_out_c6_hi1_3_scanin[24]
//  ff_l2d_decc_out_c6_lo0_1_scanin[25]
//  ff_l2d_decc_out_c6_lo0_3_scanin[25]
//  ff_l2d_decc_out_c6_hi0_1_scanin[25]
//  ff_l2d_decc_out_c6_hi0_3_scanin[25]
//  ff_l2d_decc_out_c6_lo1_1_scanin[25]
//  ff_l2d_decc_out_c6_lo1_3_scanin[25]
//  ff_l2d_decc_out_c6_hi1_1_scanin[25]
//  ff_l2d_decc_out_c6_hi1_3_scanin[25]
//  ff_l2d_decc_out_c6_lo0_1_scanin[26]
//  ff_l2d_decc_out_c6_lo0_3_scanin[26]
//  ff_l2d_decc_out_c6_hi0_1_scanin[26]
//  ff_l2d_decc_out_c6_hi0_3_scanin[26]
//  ff_l2d_decc_out_c6_lo1_1_scanin[26]
//  ff_l2d_decc_out_c6_lo1_3_scanin[26]
//  ff_l2d_decc_out_c6_hi1_1_scanin[26]
//  ff_l2d_decc_out_c6_hi1_3_scanin[26]
//  ff_l2d_decc_out_c6_lo0_1_scanin[27]
//  ff_l2d_decc_out_c6_lo0_3_scanin[27]
//  ff_l2d_decc_out_c6_hi0_1_scanin[27]
//  ff_l2d_decc_out_c6_hi0_3_scanin[27]
//  ff_l2d_decc_out_c6_lo1_1_scanin[27]
//  ff_l2d_decc_out_c6_lo1_3_scanin[27]
//  ff_l2d_decc_out_c6_hi1_1_scanin[27]
//  ff_l2d_decc_out_c6_hi1_3_scanin[27]
//  ff_l2d_decc_out_c6_lo0_1_scanin[28]
//  ff_l2d_decc_out_c6_lo0_3_scanin[28]
//  ff_l2d_decc_out_c6_hi0_1_scanin[28]
//  ff_l2d_decc_out_c6_hi0_3_scanin[28]
//  ff_l2d_decc_out_c6_lo1_1_scanin[28]
//  ff_l2d_decc_out_c6_lo1_3_scanin[28]
//  ff_l2d_decc_out_c6_hi1_1_scanin[28]
//  ff_l2d_decc_out_c6_hi1_3_scanin[28]
//  ff_l2d_decc_out_c6_lo0_1_scanin[29]
//  ff_l2d_decc_out_c6_lo0_3_scanin[29]

//  ff_l2d_decc_out_c6_hi0_1_scanin[29]
//  ff_l2d_decc_out_c6_hi0_3_scanin[29]
//  ff_l2d_decc_out_c6_lo1_1_scanin[29]
//  ff_l2d_decc_out_c6_lo1_3_scanin[29]
//  ff_l2d_decc_out_c6_hi1_1_scanin[29]
//  ff_l2d_decc_out_c6_hi1_3_scanin[29]
//  ff_l2d_decc_out_c6_lo0_1_scanin[30]
//  ff_l2d_decc_out_c6_lo0_3_scanin[30]
//  ff_l2d_decc_out_c6_hi0_1_scanin[30]
//  ff_l2d_decc_out_c6_hi0_3_scanin[30]
//  ff_l2d_decc_out_c6_lo1_1_scanin[30]
//  ff_l2d_decc_out_c6_lo1_3_scanin[30]
//  ff_l2d_decc_out_c6_hi1_1_scanin[30]
//  ff_l2d_decc_out_c6_hi1_3_scanin[30]
//  ff_l2d_decc_out_c6_lo0_1_scanin[31]
//  ff_l2d_decc_out_c6_lo0_3_scanin[31]
//  ff_l2d_decc_out_c6_hi0_1_scanin[31]
//  ff_l2d_decc_out_c6_hi0_3_scanin[31]
//  ff_l2d_decc_out_c6_lo1_1_scanin[31]
//  ff_l2d_decc_out_c6_lo1_3_scanin[31]
//  ff_l2d_decc_out_c6_hi1_1_scanin[31]
//  ff_l2d_decc_out_c6_hi1_3_scanin[31]
//  ff_l2d_decc_out_c6_lo0_1_scanin[32]
//  ff_l2d_decc_out_c6_lo0_3_scanin[32]
//  ff_l2d_decc_out_c6_hi0_1_scanin[32]
//  ff_l2d_decc_out_c6_hi0_3_scanin[32]
//  ff_l2d_decc_out_c6_lo1_1_scanin[32]
//  ff_l2d_decc_out_c6_lo1_3_scanin[32]
//  ff_l2d_decc_out_c6_hi1_1_scanin[32]
//  ff_l2d_decc_out_c6_hi1_3_scanin[32]
//  ff_l2d_decc_out_c6_lo0_1_scanin[33]
//  ff_l2d_decc_out_c6_lo0_3_scanin[33]
//  ff_l2d_decc_out_c6_hi0_1_scanin[33]
//  ff_l2d_decc_out_c6_hi0_3_scanin[33]
//  ff_l2d_decc_out_c6_lo1_1_scanin[33]
//  ff_l2d_decc_out_c6_lo1_3_scanin[33]
//  ff_l2d_decc_out_c6_hi1_1_scanin[33]
//  ff_l2d_decc_out_c6_hi1_3_scanin[33]
//  ff_l2d_decc_out_c6_lo0_1_scanin[34]
//  ff_l2d_decc_out_c6_lo0_3_scanin[34]
//  ff_l2d_decc_out_c6_hi0_1_scanin[34]
//  ff_l2d_decc_out_c6_hi0_3_scanin[34]
//  ff_l2d_decc_out_c6_lo1_1_scanin[34]
//  ff_l2d_decc_out_c6_lo1_3_scanin[34]
//  ff_l2d_decc_out_c6_hi1_1_scanin[34]
//  ff_l2d_decc_out_c6_hi1_3_scanin[34]
//  ff_l2d_decc_out_c6_lo0_1_scanin[35]
//  ff_l2d_decc_out_c6_lo0_3_scanin[35]
//  ff_l2d_decc_out_c6_hi0_1_scanin[35]
//  ff_l2d_decc_out_c6_hi0_3_scanin[35]
//  ff_l2d_decc_out_c6_lo1_1_scanin[35]
//  ff_l2d_decc_out_c6_lo1_3_scanin[35]
//  ff_l2d_decc_out_c6_hi1_1_scanin[35]
//  ff_l2d_decc_out_c6_hi1_3_scanin[35]
//  ff_l2d_decc_out_c6_lo0_1_scanin[36]
//  ff_l2d_decc_out_c6_lo0_3_scanin[36]
//  ff_l2d_decc_out_c6_hi0_1_scanin[36]
//  ff_l2d_decc_out_c6_hi0_3_scanin[36]
//  ff_l2d_decc_out_c6_lo1_1_scanin[36]
//  ff_l2d_decc_out_c6_lo1_3_scanin[36]
//  ff_l2d_decc_out_c6_hi1_1_scanin[36]
//  ff_l2d_decc_out_c6_hi1_3_scanin[36]
//  ff_l2d_decc_out_c6_lo0_1_scanin[37]
//  ff_l2d_decc_out_c6_lo0_3_scanin[37]
//  ff_l2d_decc_out_c6_hi0_1_scanin[37]
//  ff_l2d_decc_out_c6_hi0_3_scanin[37]
//  ff_l2d_decc_out_c6_lo1_1_scanin[37]
//  ff_l2d_decc_out_c6_lo1_3_scanin[37]
//  ff_l2d_decc_out_c6_hi1_1_scanin[37]
//  ff_l2d_decc_out_c6_hi1_3_scanin[37]
//  ff_l2d_decc_out_c6_lo0_1_scanin[38]
//  ff_l2d_decc_out_c6_lo0_3_scanin[38]
//  ff_l2d_decc_out_c6_hi0_1_scanin[38]
//  ff_l2d_decc_out_c6_hi0_3_scanin[38]
//  ff_l2d_decc_out_c6_lo1_1_scanin[38]
//  ff_l2d_decc_out_c6_lo1_3_scanin[38]
//  ff_l2d_decc_out_c6_hi1_1_scanin[38]
//  ff_l2d_decc_out_c6_hi1_3_scanin[38]

//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[4]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[4]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[4]

//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[4]

//  ff_cache_col_offset_c5_001_scanin[0]
//  ff_cache_col_offset_c5_001_scanin[2]
//  ff_cache_col_offset_c4_001_scanin[0]
//  ff_cache_col_offset_c4_001_scanin[2]
//  ff_cache_col_offset_c4_tog_001_scanin[0]
//  ff_cache_cache_rd_wr_c5_00_scanin
//  ff_cache_col_offset_c5_001_scanin[1]
//  ff_cache_col_offset_c5_001_scanin[3]
//  ff_cache_col_offset_c4_001_scanin[1]
//  ff_cache_col_offset_c4_001_scanin[3]
//  ff_cache_col_offset_c4_tog_001_scanin[1]

//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[14]

//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[14]
//  ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[14]
//  ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[14]

//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[19]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[18]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[17]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[16]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[15]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[14]

//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[10]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[11]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[12]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[13]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[14]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[14]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[14]


//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[0]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[1]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[2]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[3]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[4]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[4]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[4]


//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[9]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[8]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[7]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[6]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[5]
//  ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[4]


//  ff_l2d_decc_out_c6_lo0_1_scanin[0]
//  ff_l2d_decc_out_c6_lo0_3_scanin[0]
//  ff_l2d_decc_out_c6_hi0_1_scanin[0]
//  ff_l2d_decc_out_c6_hi0_3_scanin[0]
//  ff_l2d_decc_out_c6_lo1_1_scanin[0]
//  ff_l2d_decc_out_c6_lo1_3_scanin[0]
//  ff_l2d_decc_out_c6_hi1_1_scanin[0]
//  ff_l2d_decc_out_c6_hi1_3_scanin[0]
//  ff_l2d_decc_out_c6_lo0_1_scanin[1]
//  ff_l2d_decc_out_c6_lo0_3_scanin[1]
//  ff_l2d_decc_out_c6_hi0_1_scanin[1]
//  ff_l2d_decc_out_c6_hi0_3_scanin[1]
//  ff_l2d_decc_out_c6_lo1_1_scanin[1]
//  ff_l2d_decc_out_c6_lo1_3_scanin[1]
//  ff_l2d_decc_out_c6_hi1_1_scanin[1]
//  ff_l2d_decc_out_c6_hi1_3_scanin[1]
//  ff_l2d_decc_out_c6_lo0_1_scanin[2]
//  ff_l2d_decc_out_c6_lo0_3_scanin[2]
//  ff_l2d_decc_out_c6_hi0_1_scanin[2]
//  ff_l2d_decc_out_c6_hi0_3_scanin[2]
//  ff_l2d_decc_out_c6_lo1_1_scanin[2]
//  ff_l2d_decc_out_c6_lo1_3_scanin[2]
//  ff_l2d_decc_out_c6_hi1_1_scanin[2]
//  ff_l2d_decc_out_c6_hi1_3_scanin[2]
//  ff_l2d_decc_out_c6_lo0_1_scanin[3]
//  ff_l2d_decc_out_c6_lo0_3_scanin[3]
//  ff_l2d_decc_out_c6_hi0_1_scanin[3]
//  ff_l2d_decc_out_c6_hi0_3_scanin[3]
//  ff_l2d_decc_out_c6_lo1_1_scanin[3]
//  ff_l2d_decc_out_c6_lo1_3_scanin[3]
//  ff_l2d_decc_out_c6_hi1_1_scanin[3]
//  ff_l2d_decc_out_c6_hi1_3_scanin[3]
//  ff_l2d_decc_out_c6_lo0_1_scanin[4]
//  ff_l2d_decc_out_c6_lo0_3_scanin[4]
//  ff_l2d_decc_out_c6_hi0_1_scanin[4]
//  ff_l2d_decc_out_c6_hi0_3_scanin[4]
//  ff_l2d_decc_out_c6_lo1_1_scanin[4]
//  ff_l2d_decc_out_c6_lo1_3_scanin[4]
//  ff_l2d_decc_out_c6_hi1_1_scanin[4]
//  ff_l2d_decc_out_c6_hi1_3_scanin[4]
//  ff_l2d_decc_out_c6_lo0_1_scanin[5]
//  ff_l2d_decc_out_c6_lo0_3_scanin[5]
//  ff_l2d_decc_out_c6_hi0_1_scanin[5]
//  ff_l2d_decc_out_c6_hi0_3_scanin[5]
//  ff_l2d_decc_out_c6_lo1_1_scanin[5]
//  ff_l2d_decc_out_c6_lo1_3_scanin[5]
//  ff_l2d_decc_out_c6_hi1_1_scanin[5]
//  ff_l2d_decc_out_c6_hi1_3_scanin[5]
//  ff_l2d_decc_out_c6_lo0_1_scanin[6]
//  ff_l2d_decc_out_c6_lo0_3_scanin[6]
//  ff_l2d_decc_out_c6_hi0_1_scanin[6]
//  ff_l2d_decc_out_c6_hi0_3_scanin[6]
//  ff_l2d_decc_out_c6_lo1_1_scanin[6]
//  ff_l2d_decc_out_c6_lo1_3_scanin[6]
//  ff_l2d_decc_out_c6_hi1_1_scanin[6]
//  ff_l2d_decc_out_c6_hi1_3_scanin[6]
//  ff_l2d_decc_out_c6_lo0_1_scanin[7]
//  ff_l2d_decc_out_c6_lo0_3_scanin[7]
//  ff_l2d_decc_out_c6_hi0_1_scanin[7]
//  ff_l2d_decc_out_c6_hi0_3_scanin[7]
//  ff_l2d_decc_out_c6_lo1_1_scanin[7]
//  ff_l2d_decc_out_c6_lo1_3_scanin[7]
//  ff_l2d_decc_out_c6_hi1_1_scanin[7]
//  ff_l2d_decc_out_c6_hi1_3_scanin[7]
//  ff_l2d_decc_out_c6_lo0_1_scanin[8]
//  ff_l2d_decc_out_c6_lo0_3_scanin[8]
//  ff_l2d_decc_out_c6_hi0_1_scanin[8]
//  ff_l2d_decc_out_c6_hi0_3_scanin[8]
//  ff_l2d_decc_out_c6_lo1_1_scanin[8]
//  ff_l2d_decc_out_c6_lo1_3_scanin[8]
//  ff_l2d_decc_out_c6_hi1_1_scanin[8]
//  ff_l2d_decc_out_c6_hi1_3_scanin[8]
//  ff_l2d_decc_out_c6_lo0_1_scanin[9]
//  ff_l2d_decc_out_c6_lo0_3_scanin[9]
//  ff_l2d_decc_out_c6_hi0_1_scanin[9]
//  ff_l2d_decc_out_c6_hi0_3_scanin[9]
//  ff_l2d_decc_out_c6_lo1_1_scanin[9]
//  ff_l2d_decc_out_c6_lo1_3_scanin[9]
//  ff_l2d_decc_out_c6_hi1_1_scanin[9]
//  ff_l2d_decc_out_c6_hi1_3_scanin[9]

//  ff_l2d_decc_out_c6_lo0_1_scanin[10]
//  ff_l2d_decc_out_c6_lo0_3_scanin[10]
//  ff_l2d_decc_out_c6_hi0_1_scanin[10]
//  ff_l2d_decc_out_c6_hi0_3_scanin[10]
//  ff_l2d_decc_out_c6_lo1_1_scanin[10]
//  ff_l2d_decc_out_c6_lo1_3_scanin[10]
//  ff_l2d_decc_out_c6_hi1_1_scanin[10]
//  ff_l2d_decc_out_c6_hi1_3_scanin[10]
//  ff_l2d_decc_out_c6_lo0_1_scanin[11]
//  ff_l2d_decc_out_c6_lo0_3_scanin[11]
//  ff_l2d_decc_out_c6_hi0_1_scanin[11]
//  ff_l2d_decc_out_c6_hi0_3_scanin[11]
//  ff_l2d_decc_out_c6_lo1_1_scanin[11]
//  ff_l2d_decc_out_c6_lo1_3_scanin[11]
//  ff_l2d_decc_out_c6_hi1_1_scanin[11]
//  ff_l2d_decc_out_c6_hi1_3_scanin[11]
//  ff_l2d_decc_out_c6_lo0_1_scanin[12]
//  ff_l2d_decc_out_c6_lo0_3_scanin[12]
//  ff_l2d_decc_out_c6_hi0_1_scanin[12]
//  ff_l2d_decc_out_c6_hi0_3_scanin[12]
//  ff_l2d_decc_out_c6_lo1_1_scanin[12]
//  ff_l2d_decc_out_c6_lo1_3_scanin[12]
//  ff_l2d_decc_out_c6_hi1_1_scanin[12]
//  ff_l2d_decc_out_c6_hi1_3_scanin[12]
//  ff_l2d_decc_out_c6_lo0_1_scanin[13]
//  ff_l2d_decc_out_c6_lo0_3_scanin[13]
//  ff_l2d_decc_out_c6_hi0_1_scanin[13]
//  ff_l2d_decc_out_c6_hi0_3_scanin[13]
//  ff_l2d_decc_out_c6_lo1_1_scanin[13]
//  ff_l2d_decc_out_c6_lo1_3_scanin[13]
//  ff_l2d_decc_out_c6_hi1_1_scanin[13]
//  ff_l2d_decc_out_c6_hi1_3_scanin[13]
//  ff_l2d_decc_out_c6_lo0_1_scanin[14]
//  ff_l2d_decc_out_c6_lo0_3_scanin[14]
//  ff_l2d_decc_out_c6_hi0_1_scanin[14]
//  ff_l2d_decc_out_c6_hi0_3_scanin[14]
//  ff_l2d_decc_out_c6_lo1_1_scanin[14]
//  ff_l2d_decc_out_c6_lo1_3_scanin[14]
//  ff_l2d_decc_out_c6_hi1_1_scanin[14]
//  ff_l2d_decc_out_c6_hi1_3_scanin[14]
//  ff_l2d_decc_out_c6_lo0_1_scanin[15]
//  ff_l2d_decc_out_c6_lo0_3_scanin[15]
//  ff_l2d_decc_out_c6_hi0_1_scanin[15]
//  ff_l2d_decc_out_c6_hi0_3_scanin[15]
//  ff_l2d_decc_out_c6_lo1_1_scanin[15]
//  ff_l2d_decc_out_c6_lo1_3_scanin[15]
//  ff_l2d_decc_out_c6_hi1_1_scanin[15]
//  ff_l2d_decc_out_c6_hi1_3_scanin[15]
//  ff_l2d_decc_out_c6_lo0_1_scanin[16]
//  ff_l2d_decc_out_c6_lo0_3_scanin[16]
//  ff_l2d_decc_out_c6_hi0_1_scanin[16]
//  ff_l2d_decc_out_c6_hi0_3_scanin[16]
//  ff_l2d_decc_out_c6_lo1_1_scanin[16]
//  ff_l2d_decc_out_c6_lo1_3_scanin[16]
//  ff_l2d_decc_out_c6_hi1_1_scanin[16]
//  ff_l2d_decc_out_c6_hi1_3_scanin[16]
//  ff_l2d_decc_out_c6_lo0_1_scanin[17]
//  ff_l2d_decc_out_c6_lo0_3_scanin[17]
//  ff_l2d_decc_out_c6_hi0_1_scanin[17]
//  ff_l2d_decc_out_c6_hi0_3_scanin[17]
//  ff_l2d_decc_out_c6_lo1_1_scanin[17]
//  ff_l2d_decc_out_c6_lo1_3_scanin[17]
//  ff_l2d_decc_out_c6_hi1_1_scanin[17]
//  ff_l2d_decc_out_c6_hi1_3_scanin[17]
//  ff_l2d_decc_out_c6_lo0_1_scanin[18]
//  ff_l2d_decc_out_c6_lo0_3_scanin[18]
//  ff_l2d_decc_out_c6_hi0_1_scanin[18]
//  ff_l2d_decc_out_c6_hi0_3_scanin[18]
//  ff_l2d_decc_out_c6_lo1_1_scanin[18]
//  ff_l2d_decc_out_c6_lo1_3_scanin[18]
//  ff_l2d_decc_out_c6_hi1_1_scanin[18]
//  ff_l2d_decc_out_c6_hi1_3_scanin[18]
//  ff_l2d_decc_out_c6_lo0_1_scanin[19]
//  ff_l2d_decc_out_c6_lo0_3_scanin[19]
//  ff_l2d_decc_out_c6_hi0_1_scanin[19]
//  ff_l2d_decc_out_c6_hi0_3_scanin[19]
// scanorder end
// fixscan start
assign ff_cache_cache_rd_wr_c4_scanin=scan_in;
assign ff_cache_set_c3_scanin[8]=ff_cache_cache_rd_wr_c4_scanout;
assign ff_cache_set_c3_scanin[7]=ff_cache_set_c3_scanout[8];
assign ff_cache_set_c3_scanin[6]=ff_cache_set_c3_scanout[7];
assign ff_cache_set_c3_scanin[5]=ff_cache_set_c3_scanout[6];
assign ff_cache_set_c3_scanin[4]=ff_cache_set_c3_scanout[5];
assign ff_cache_set_c3_scanin[3]=ff_cache_set_c3_scanout[4];
assign ff_cache_set_c3_scanin[2]=ff_cache_set_c3_scanout[3];
assign ff_cache_set_c3_scanin[1]=ff_cache_set_c3_scanout[2];
assign ff_cache_set_c3_scanin[0]=ff_cache_set_c3_scanout[1];
assign ff_cache_word_en_c3_scanin[1]=ff_cache_set_c3_scanout[0];
assign ff_cache_word_en_c3_scanin[3]=ff_cache_word_en_c3_scanout[1];
assign ff_cache_word_en_c3_scanin[5]=ff_cache_word_en_c3_scanout[3];
assign ff_cache_word_en_c3_scanin[7]=ff_cache_word_en_c3_scanout[5];
assign ff_cache_word_en_c3_scanin[9]=ff_cache_word_en_c3_scanout[7];
assign ff_cache_word_en_c3_scanin[11]=ff_cache_word_en_c3_scanout[9];
assign ff_cache_word_en_c3_scanin[13]=ff_cache_word_en_c3_scanout[11];
assign ff_cache_word_en_c3_scanin[15]=ff_cache_word_en_c3_scanout[13];
assign ff_cache_col_offset_c3_scanin[0]=ff_cache_word_en_c3_scanout[15];
assign ff_cache_col_offset_c4_scanin[0]=ff_cache_col_offset_c3_scanout[0];
assign ff_cache_col_offset_c5_muxsel_scanin[0]=ff_cache_col_offset_c4_scanout[0];
assign ff_cache_col_offset_c5_muxsel_scanin[1]=ff_cache_col_offset_c5_muxsel_scanout[0];
assign ff_cache_col_offset_c4_scanin[1]=ff_cache_col_offset_c5_muxsel_scanout[1];
assign ff_cache_col_offset_c3_scanin[1]=ff_cache_col_offset_c4_scanout[1];
assign ff_cache_col_offset_c3_scanin[2]=ff_cache_col_offset_c3_scanout[1];
assign ff_cache_col_offset_c4_scanin[2]=ff_cache_col_offset_c3_scanout[2];
assign ff_cache_col_offset_c5_muxsel_scanin[2]=ff_cache_col_offset_c4_scanout[2];
assign ff_cache_col_offset_c5_muxsel_scanin[3]=ff_cache_col_offset_c5_muxsel_scanout[2];
assign ff_cache_col_offset_c4_scanin[3]=ff_cache_col_offset_c5_muxsel_scanout[3];
assign ff_cache_col_offset_c3_scanin[3]=ff_cache_col_offset_c4_scanout[3];
assign ff_cache_col_offset_all_c4_scanin=ff_cache_col_offset_c3_scanout[3];
assign ff_cache_col_offset_all_c5_scanin=ff_cache_col_offset_all_c4_scanout;
assign ff_cache_col_offset_all_c6_scanin=ff_cache_col_offset_all_c5_scanout;
assign ff_cache_col_offset_all_c7_scanin=ff_cache_col_offset_all_c6_scanout;
assign ff_cache_word_en_c3_scanin[0]=ff_cache_col_offset_all_c7_scanout;
assign ff_cache_word_en_c3_scanin[2]=ff_cache_word_en_c3_scanout[0];
assign ff_cache_word_en_c3_scanin[4]=ff_cache_word_en_c3_scanout[2];
assign ff_cache_word_en_c3_scanin[6]=ff_cache_word_en_c3_scanout[4];
assign ff_cache_word_en_c3_scanin[8]=ff_cache_word_en_c3_scanout[6];
assign ff_cache_word_en_c3_scanin[10]=ff_cache_word_en_c3_scanout[8];
assign ff_cache_word_en_c3_scanin[12]=ff_cache_word_en_c3_scanout[10];
assign ff_cache_word_en_c3_scanin[14]=ff_cache_word_en_c3_scanout[12];
assign ff_cache_col_offset_c52_scanin[1]=ff_cache_word_en_c3_scanout[14];
assign ff_cache_col_offset_c52_scanin[0]=ff_cache_col_offset_c52_scanout[1];
assign ff_cache_col_offset_c52_topsel_scanin=ff_cache_col_offset_c52_scanout[0];
assign ff_cache_fb_hit_c4_scanin=ff_cache_col_offset_c52_topsel_scanout;
assign ff_cache_fb_hit_c5_scanin=ff_cache_fb_hit_c4_scanout;
assign ff_cache_fb_hit_c52_scanin=ff_cache_fb_hit_c5_scanout;
assign ff_cache_sel_fbdecc_c4_scanin=ff_cache_fb_hit_c52_scanout;
assign ff_cache_sel_fbdecc_c5_scanin=ff_cache_sel_fbdecc_c4_scanout;
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[0]=ff_cache_sel_fbdecc_c5_scanout;
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[1]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[1]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[1]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[1]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[2]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[2]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[2]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[2]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[3]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[3]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[3]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[3]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[4]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[4]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[4]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[9]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[9]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[9]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[8]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[8]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[8]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[8]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[7]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[7]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[7]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[7]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[6]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[6]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[6]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[6]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[5]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[5]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[5]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[5]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[4]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[5];
assign ff_l2t_l2d_stdecc_c3_scanin[77]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[4];
assign ff_l2t_l2d_stdecc_c3_scanin[76]=ff_l2t_l2d_stdecc_c3_scanout[77];
assign ff_l2t_l2d_stdecc_c3_scanin[75]=ff_l2t_l2d_stdecc_c3_scanout[76];
assign ff_l2t_l2d_stdecc_c3_scanin[74]=ff_l2t_l2d_stdecc_c3_scanout[75];
assign ff_l2t_l2d_stdecc_c3_scanin[73]=ff_l2t_l2d_stdecc_c3_scanout[74];
assign ff_l2t_l2d_stdecc_c3_scanin[72]=ff_l2t_l2d_stdecc_c3_scanout[73];
assign ff_l2t_l2d_stdecc_c3_scanin[71]=ff_l2t_l2d_stdecc_c3_scanout[72];
assign ff_l2t_l2d_stdecc_c3_scanin[70]=ff_l2t_l2d_stdecc_c3_scanout[71];
assign ff_l2t_l2d_stdecc_c3_scanin[69]=ff_l2t_l2d_stdecc_c3_scanout[70];
assign ff_l2t_l2d_stdecc_c3_scanin[68]=ff_l2t_l2d_stdecc_c3_scanout[69];
assign ff_l2t_l2d_stdecc_c3_scanin[67]=ff_l2t_l2d_stdecc_c3_scanout[68];
assign ff_l2t_l2d_stdecc_c3_scanin[66]=ff_l2t_l2d_stdecc_c3_scanout[67];
assign ff_l2t_l2d_stdecc_c3_scanin[65]=ff_l2t_l2d_stdecc_c3_scanout[66];
assign ff_l2t_l2d_stdecc_c3_scanin[64]=ff_l2t_l2d_stdecc_c3_scanout[65];
assign ff_l2t_l2d_stdecc_c3_scanin[63]=ff_l2t_l2d_stdecc_c3_scanout[64];
assign ff_l2t_l2d_stdecc_c3_scanin[62]=ff_l2t_l2d_stdecc_c3_scanout[63];
assign ff_l2t_l2d_stdecc_c3_scanin[61]=ff_l2t_l2d_stdecc_c3_scanout[62];
assign ff_l2t_l2d_stdecc_c3_scanin[60]=ff_l2t_l2d_stdecc_c3_scanout[61];
assign ff_l2t_l2d_stdecc_c3_scanin[59]=ff_l2t_l2d_stdecc_c3_scanout[60];
assign ff_l2t_l2d_stdecc_c3_scanin[58]=ff_l2t_l2d_stdecc_c3_scanout[59];
assign ff_l2t_l2d_stdecc_c3_scanin[57]=ff_l2t_l2d_stdecc_c3_scanout[58];
assign ff_l2t_l2d_stdecc_c3_scanin[56]=ff_l2t_l2d_stdecc_c3_scanout[57];
assign ff_l2t_l2d_stdecc_c3_scanin[55]=ff_l2t_l2d_stdecc_c3_scanout[56];
assign ff_l2t_l2d_stdecc_c3_scanin[54]=ff_l2t_l2d_stdecc_c3_scanout[55];
assign ff_l2t_l2d_stdecc_c3_scanin[53]=ff_l2t_l2d_stdecc_c3_scanout[54];
assign ff_l2t_l2d_stdecc_c3_scanin[52]=ff_l2t_l2d_stdecc_c3_scanout[53];
assign ff_l2t_l2d_stdecc_c3_scanin[51]=ff_l2t_l2d_stdecc_c3_scanout[52];
assign ff_l2t_l2d_stdecc_c3_scanin[50]=ff_l2t_l2d_stdecc_c3_scanout[51];
assign ff_l2t_l2d_stdecc_c3_scanin[49]=ff_l2t_l2d_stdecc_c3_scanout[50];
assign ff_l2t_l2d_stdecc_c3_scanin[48]=ff_l2t_l2d_stdecc_c3_scanout[49];
assign ff_l2t_l2d_stdecc_c3_scanin[47]=ff_l2t_l2d_stdecc_c3_scanout[48];
assign ff_l2t_l2d_stdecc_c3_scanin[46]=ff_l2t_l2d_stdecc_c3_scanout[47];
assign ff_l2t_l2d_stdecc_c3_scanin[45]=ff_l2t_l2d_stdecc_c3_scanout[46];
assign ff_l2t_l2d_stdecc_c3_scanin[44]=ff_l2t_l2d_stdecc_c3_scanout[45];
assign ff_l2t_l2d_stdecc_c3_scanin[43]=ff_l2t_l2d_stdecc_c3_scanout[44];
assign ff_l2t_l2d_stdecc_c3_scanin[42]=ff_l2t_l2d_stdecc_c3_scanout[43];
assign ff_l2t_l2d_stdecc_c3_scanin[41]=ff_l2t_l2d_stdecc_c3_scanout[42];
assign ff_l2t_l2d_stdecc_c3_scanin[40]=ff_l2t_l2d_stdecc_c3_scanout[41];
assign ff_l2t_l2d_stdecc_c3_scanin[39]=ff_l2t_l2d_stdecc_c3_scanout[40];
assign ff_cache_col_offset_c5_023_scanin[0]=ff_l2t_l2d_stdecc_c3_scanout[39];
assign ff_cache_col_offset_c5_023_scanin[2]=ff_cache_col_offset_c5_023_scanout[0];
assign ff_cache_col_offset_c4_023_scanin[0]=ff_cache_col_offset_c5_023_scanout[2];
assign ff_cache_col_offset_c4_023_scanin[2]=ff_cache_col_offset_c4_023_scanout[0];
assign ff_cache_col_offset_c4_tog_023_scanin[0]=ff_cache_col_offset_c4_023_scanout[2];
assign ff_cache_cache_rd_wr_c5_20_scanin=ff_cache_col_offset_c4_tog_023_scanout[0];
assign ff_cache_col_offset_c5_023_scanin[1]=ff_cache_cache_rd_wr_c5_20_scanout;
assign ff_cache_col_offset_c5_023_scanin[3]=ff_cache_col_offset_c5_023_scanout[1];
assign ff_cache_col_offset_c4_023_scanin[1]=ff_cache_col_offset_c5_023_scanout[3];
assign ff_cache_col_offset_c4_023_scanin[3]=ff_cache_col_offset_c4_023_scanout[1];
assign ff_cache_col_offset_c4_tog_023_scanin[1]=ff_cache_col_offset_c4_023_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[19]=ff_cache_col_offset_c4_tog_023_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[19]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[18]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[18]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[18]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[18]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[17]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[17]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[17]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[17]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[16]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[16]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[16]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[16]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[15]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[15]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[15]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[15]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[14]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[9]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[10]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[10]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[10]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[10]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[11]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[11]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[11]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[11]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[12]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[12]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[12]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[12]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[13]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[13]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[13]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[13]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[14]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[14]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[14]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[19]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[19]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[18]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[18]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[18]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[18]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[17]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[17]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[17]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[17]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[16]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[16]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[16]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[16]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[15]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[15]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[15]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[15]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[14]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[9]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[10]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[10]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[10]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[10]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[11]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[11]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[11]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[11]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[12]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[12]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[12]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[12]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[13]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[13]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[13]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[13]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[14]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[14]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[14]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[1]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[1]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[1]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[1]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[2]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[2]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[2]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[2]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[3]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[3]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[3]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[3]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[4]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[4]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[4]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[9]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[9]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[9]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[8]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[8]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[8]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[8]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[7]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[7]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[7]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[7]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[6]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[6]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[6]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[6]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[5]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[5]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[5]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[5]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[4]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[5];
assign ff_l2d_decc_out_c6_lo0_2_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[4];
assign ff_l2d_decc_out_c6_lo0_4_scanin[0]=ff_l2d_decc_out_c6_lo0_2_scanout[0];
assign ff_l2d_decc_out_c6_hi0_2_scanin[0]=ff_l2d_decc_out_c6_lo0_4_scanout[0];
assign ff_l2d_decc_out_c6_hi0_4_scanin[0]=ff_l2d_decc_out_c6_hi0_2_scanout[0];
assign ff_l2d_decc_out_c6_lo1_2_scanin[0]=ff_l2d_decc_out_c6_hi0_4_scanout[0];
assign ff_l2d_decc_out_c6_lo1_4_scanin[0]=ff_l2d_decc_out_c6_lo1_2_scanout[0];
assign ff_l2d_decc_out_c6_hi1_2_scanin[0]=ff_l2d_decc_out_c6_lo1_4_scanout[0];
assign ff_l2d_decc_out_c6_hi1_4_scanin[0]=ff_l2d_decc_out_c6_hi1_2_scanout[0];
assign ff_l2d_decc_out_c6_lo0_2_scanin[1]=ff_l2d_decc_out_c6_hi1_4_scanout[0];
assign ff_l2d_decc_out_c6_lo0_4_scanin[1]=ff_l2d_decc_out_c6_lo0_2_scanout[1];
assign ff_l2d_decc_out_c6_hi0_2_scanin[1]=ff_l2d_decc_out_c6_lo0_4_scanout[1];
assign ff_l2d_decc_out_c6_hi0_4_scanin[1]=ff_l2d_decc_out_c6_hi0_2_scanout[1];
assign ff_l2d_decc_out_c6_lo1_2_scanin[1]=ff_l2d_decc_out_c6_hi0_4_scanout[1];
assign ff_l2d_decc_out_c6_lo1_4_scanin[1]=ff_l2d_decc_out_c6_lo1_2_scanout[1];
assign ff_l2d_decc_out_c6_hi1_2_scanin[1]=ff_l2d_decc_out_c6_lo1_4_scanout[1];
assign ff_l2d_decc_out_c6_hi1_4_scanin[1]=ff_l2d_decc_out_c6_hi1_2_scanout[1];
assign ff_l2d_decc_out_c6_lo0_2_scanin[2]=ff_l2d_decc_out_c6_hi1_4_scanout[1];
assign ff_l2d_decc_out_c6_lo0_4_scanin[2]=ff_l2d_decc_out_c6_lo0_2_scanout[2];
assign ff_l2d_decc_out_c6_hi0_2_scanin[2]=ff_l2d_decc_out_c6_lo0_4_scanout[2];
assign ff_l2d_decc_out_c6_hi0_4_scanin[2]=ff_l2d_decc_out_c6_hi0_2_scanout[2];
assign ff_l2d_decc_out_c6_lo1_2_scanin[2]=ff_l2d_decc_out_c6_hi0_4_scanout[2];
assign ff_l2d_decc_out_c6_lo1_4_scanin[2]=ff_l2d_decc_out_c6_lo1_2_scanout[2];
assign ff_l2d_decc_out_c6_hi1_2_scanin[2]=ff_l2d_decc_out_c6_lo1_4_scanout[2];
assign ff_l2d_decc_out_c6_hi1_4_scanin[2]=ff_l2d_decc_out_c6_hi1_2_scanout[2];
assign ff_l2d_decc_out_c6_lo0_2_scanin[3]=ff_l2d_decc_out_c6_hi1_4_scanout[2];
assign ff_l2d_decc_out_c6_lo0_4_scanin[3]=ff_l2d_decc_out_c6_lo0_2_scanout[3];
assign ff_l2d_decc_out_c6_hi0_2_scanin[3]=ff_l2d_decc_out_c6_lo0_4_scanout[3];
assign ff_l2d_decc_out_c6_hi0_4_scanin[3]=ff_l2d_decc_out_c6_hi0_2_scanout[3];
assign ff_l2d_decc_out_c6_lo1_2_scanin[3]=ff_l2d_decc_out_c6_hi0_4_scanout[3];
assign ff_l2d_decc_out_c6_lo1_4_scanin[3]=ff_l2d_decc_out_c6_lo1_2_scanout[3];
assign ff_l2d_decc_out_c6_hi1_2_scanin[3]=ff_l2d_decc_out_c6_lo1_4_scanout[3];
assign ff_l2d_decc_out_c6_hi1_4_scanin[3]=ff_l2d_decc_out_c6_hi1_2_scanout[3];
assign ff_l2d_decc_out_c6_lo0_2_scanin[4]=ff_l2d_decc_out_c6_hi1_4_scanout[3];
assign ff_l2d_decc_out_c6_lo0_4_scanin[4]=ff_l2d_decc_out_c6_lo0_2_scanout[4];
assign ff_l2d_decc_out_c6_hi0_2_scanin[4]=ff_l2d_decc_out_c6_lo0_4_scanout[4];
assign ff_l2d_decc_out_c6_hi0_4_scanin[4]=ff_l2d_decc_out_c6_hi0_2_scanout[4];
assign ff_l2d_decc_out_c6_lo1_2_scanin[4]=ff_l2d_decc_out_c6_hi0_4_scanout[4];
assign ff_l2d_decc_out_c6_lo1_4_scanin[4]=ff_l2d_decc_out_c6_lo1_2_scanout[4];
assign ff_l2d_decc_out_c6_hi1_2_scanin[4]=ff_l2d_decc_out_c6_lo1_4_scanout[4];
assign ff_l2d_decc_out_c6_hi1_4_scanin[4]=ff_l2d_decc_out_c6_hi1_2_scanout[4];
assign ff_l2d_decc_out_c6_lo0_2_scanin[5]=ff_l2d_decc_out_c6_hi1_4_scanout[4];
assign ff_l2d_decc_out_c6_lo0_4_scanin[5]=ff_l2d_decc_out_c6_lo0_2_scanout[5];
assign ff_l2d_decc_out_c6_hi0_2_scanin[5]=ff_l2d_decc_out_c6_lo0_4_scanout[5];
assign ff_l2d_decc_out_c6_hi0_4_scanin[5]=ff_l2d_decc_out_c6_hi0_2_scanout[5];
assign ff_l2d_decc_out_c6_lo1_2_scanin[5]=ff_l2d_decc_out_c6_hi0_4_scanout[5];
assign ff_l2d_decc_out_c6_lo1_4_scanin[5]=ff_l2d_decc_out_c6_lo1_2_scanout[5];
assign ff_l2d_decc_out_c6_hi1_2_scanin[5]=ff_l2d_decc_out_c6_lo1_4_scanout[5];
assign ff_l2d_decc_out_c6_hi1_4_scanin[5]=ff_l2d_decc_out_c6_hi1_2_scanout[5];
assign ff_l2d_decc_out_c6_lo0_2_scanin[6]=ff_l2d_decc_out_c6_hi1_4_scanout[5];
assign ff_l2d_decc_out_c6_lo0_4_scanin[6]=ff_l2d_decc_out_c6_lo0_2_scanout[6];
assign ff_l2d_decc_out_c6_hi0_2_scanin[6]=ff_l2d_decc_out_c6_lo0_4_scanout[6];
assign ff_l2d_decc_out_c6_hi0_4_scanin[6]=ff_l2d_decc_out_c6_hi0_2_scanout[6];
assign ff_l2d_decc_out_c6_lo1_2_scanin[6]=ff_l2d_decc_out_c6_hi0_4_scanout[6];
assign ff_l2d_decc_out_c6_lo1_4_scanin[6]=ff_l2d_decc_out_c6_lo1_2_scanout[6];
assign ff_l2d_decc_out_c6_hi1_2_scanin[6]=ff_l2d_decc_out_c6_lo1_4_scanout[6];
assign ff_l2d_decc_out_c6_hi1_4_scanin[6]=ff_l2d_decc_out_c6_hi1_2_scanout[6];
assign ff_l2d_decc_out_c6_lo0_2_scanin[7]=ff_l2d_decc_out_c6_hi1_4_scanout[6];
assign ff_l2d_decc_out_c6_lo0_4_scanin[7]=ff_l2d_decc_out_c6_lo0_2_scanout[7];
assign ff_l2d_decc_out_c6_hi0_2_scanin[7]=ff_l2d_decc_out_c6_lo0_4_scanout[7];
assign ff_l2d_decc_out_c6_hi0_4_scanin[7]=ff_l2d_decc_out_c6_hi0_2_scanout[7];
assign ff_l2d_decc_out_c6_lo1_2_scanin[7]=ff_l2d_decc_out_c6_hi0_4_scanout[7];
assign ff_l2d_decc_out_c6_lo1_4_scanin[7]=ff_l2d_decc_out_c6_lo1_2_scanout[7];
assign ff_l2d_decc_out_c6_hi1_2_scanin[7]=ff_l2d_decc_out_c6_lo1_4_scanout[7];
assign ff_l2d_decc_out_c6_hi1_4_scanin[7]=ff_l2d_decc_out_c6_hi1_2_scanout[7];
assign ff_l2d_decc_out_c6_lo0_2_scanin[8]=ff_l2d_decc_out_c6_hi1_4_scanout[7];
assign ff_l2d_decc_out_c6_lo0_4_scanin[8]=ff_l2d_decc_out_c6_lo0_2_scanout[8];
assign ff_l2d_decc_out_c6_hi0_2_scanin[8]=ff_l2d_decc_out_c6_lo0_4_scanout[8];
assign ff_l2d_decc_out_c6_hi0_4_scanin[8]=ff_l2d_decc_out_c6_hi0_2_scanout[8];
assign ff_l2d_decc_out_c6_lo1_2_scanin[8]=ff_l2d_decc_out_c6_hi0_4_scanout[8];
assign ff_l2d_decc_out_c6_lo1_4_scanin[8]=ff_l2d_decc_out_c6_lo1_2_scanout[8];
assign ff_l2d_decc_out_c6_hi1_2_scanin[8]=ff_l2d_decc_out_c6_lo1_4_scanout[8];
assign ff_l2d_decc_out_c6_hi1_4_scanin[8]=ff_l2d_decc_out_c6_hi1_2_scanout[8];
assign ff_l2d_decc_out_c6_lo0_2_scanin[9]=ff_l2d_decc_out_c6_hi1_4_scanout[8];
assign ff_l2d_decc_out_c6_lo0_4_scanin[9]=ff_l2d_decc_out_c6_lo0_2_scanout[9];
assign ff_l2d_decc_out_c6_hi0_2_scanin[9]=ff_l2d_decc_out_c6_lo0_4_scanout[9];
assign ff_l2d_decc_out_c6_hi0_4_scanin[9]=ff_l2d_decc_out_c6_hi0_2_scanout[9];
assign ff_l2d_decc_out_c6_lo1_2_scanin[9]=ff_l2d_decc_out_c6_hi0_4_scanout[9];
assign ff_l2d_decc_out_c6_lo1_4_scanin[9]=ff_l2d_decc_out_c6_lo1_2_scanout[9];
assign ff_l2d_decc_out_c6_hi1_2_scanin[9]=ff_l2d_decc_out_c6_lo1_4_scanout[9];
assign ff_l2d_decc_out_c6_hi1_4_scanin[9]=ff_l2d_decc_out_c6_hi1_2_scanout[9];
assign ff_l2d_decc_out_c6_lo0_2_scanin[10]=ff_l2d_decc_out_c6_hi1_4_scanout[9];
assign ff_l2d_decc_out_c6_lo0_4_scanin[10]=ff_l2d_decc_out_c6_lo0_2_scanout[10];
assign ff_l2d_decc_out_c6_hi0_2_scanin[10]=ff_l2d_decc_out_c6_lo0_4_scanout[10];
assign ff_l2d_decc_out_c6_hi0_4_scanin[10]=ff_l2d_decc_out_c6_hi0_2_scanout[10];
assign ff_l2d_decc_out_c6_lo1_2_scanin[10]=ff_l2d_decc_out_c6_hi0_4_scanout[10];
assign ff_l2d_decc_out_c6_lo1_4_scanin[10]=ff_l2d_decc_out_c6_lo1_2_scanout[10];
assign ff_l2d_decc_out_c6_hi1_2_scanin[10]=ff_l2d_decc_out_c6_lo1_4_scanout[10];
assign ff_l2d_decc_out_c6_hi1_4_scanin[10]=ff_l2d_decc_out_c6_hi1_2_scanout[10];
assign ff_l2d_decc_out_c6_lo0_2_scanin[11]=ff_l2d_decc_out_c6_hi1_4_scanout[10];
assign ff_l2d_decc_out_c6_lo0_4_scanin[11]=ff_l2d_decc_out_c6_lo0_2_scanout[11];
assign ff_l2d_decc_out_c6_hi0_2_scanin[11]=ff_l2d_decc_out_c6_lo0_4_scanout[11];
assign ff_l2d_decc_out_c6_hi0_4_scanin[11]=ff_l2d_decc_out_c6_hi0_2_scanout[11];
assign ff_l2d_decc_out_c6_lo1_2_scanin[11]=ff_l2d_decc_out_c6_hi0_4_scanout[11];
assign ff_l2d_decc_out_c6_lo1_4_scanin[11]=ff_l2d_decc_out_c6_lo1_2_scanout[11];
assign ff_l2d_decc_out_c6_hi1_2_scanin[11]=ff_l2d_decc_out_c6_lo1_4_scanout[11];
assign ff_l2d_decc_out_c6_hi1_4_scanin[11]=ff_l2d_decc_out_c6_hi1_2_scanout[11];
assign ff_l2d_decc_out_c6_lo0_2_scanin[12]=ff_l2d_decc_out_c6_hi1_4_scanout[11];
assign ff_l2d_decc_out_c6_lo0_4_scanin[12]=ff_l2d_decc_out_c6_lo0_2_scanout[12];
assign ff_l2d_decc_out_c6_hi0_2_scanin[12]=ff_l2d_decc_out_c6_lo0_4_scanout[12];
assign ff_l2d_decc_out_c6_hi0_4_scanin[12]=ff_l2d_decc_out_c6_hi0_2_scanout[12];
assign ff_l2d_decc_out_c6_lo1_2_scanin[12]=ff_l2d_decc_out_c6_hi0_4_scanout[12];
assign ff_l2d_decc_out_c6_lo1_4_scanin[12]=ff_l2d_decc_out_c6_lo1_2_scanout[12];
assign ff_l2d_decc_out_c6_hi1_2_scanin[12]=ff_l2d_decc_out_c6_lo1_4_scanout[12];
assign ff_l2d_decc_out_c6_hi1_4_scanin[12]=ff_l2d_decc_out_c6_hi1_2_scanout[12];
assign ff_l2d_decc_out_c6_lo0_2_scanin[13]=ff_l2d_decc_out_c6_hi1_4_scanout[12];
assign ff_l2d_decc_out_c6_lo0_4_scanin[13]=ff_l2d_decc_out_c6_lo0_2_scanout[13];
assign ff_l2d_decc_out_c6_hi0_2_scanin[13]=ff_l2d_decc_out_c6_lo0_4_scanout[13];
assign ff_l2d_decc_out_c6_hi0_4_scanin[13]=ff_l2d_decc_out_c6_hi0_2_scanout[13];
assign ff_l2d_decc_out_c6_lo1_2_scanin[13]=ff_l2d_decc_out_c6_hi0_4_scanout[13];
assign ff_l2d_decc_out_c6_lo1_4_scanin[13]=ff_l2d_decc_out_c6_lo1_2_scanout[13];
assign ff_l2d_decc_out_c6_hi1_2_scanin[13]=ff_l2d_decc_out_c6_lo1_4_scanout[13];
assign ff_l2d_decc_out_c6_hi1_4_scanin[13]=ff_l2d_decc_out_c6_hi1_2_scanout[13];
assign ff_l2d_decc_out_c6_lo0_2_scanin[14]=ff_l2d_decc_out_c6_hi1_4_scanout[13];
assign ff_l2d_decc_out_c6_lo0_4_scanin[14]=ff_l2d_decc_out_c6_lo0_2_scanout[14];
assign ff_l2d_decc_out_c6_hi0_2_scanin[14]=ff_l2d_decc_out_c6_lo0_4_scanout[14];
assign ff_l2d_decc_out_c6_hi0_4_scanin[14]=ff_l2d_decc_out_c6_hi0_2_scanout[14];
assign ff_l2d_decc_out_c6_lo1_2_scanin[14]=ff_l2d_decc_out_c6_hi0_4_scanout[14];
assign ff_l2d_decc_out_c6_lo1_4_scanin[14]=ff_l2d_decc_out_c6_lo1_2_scanout[14];
assign ff_l2d_decc_out_c6_hi1_2_scanin[14]=ff_l2d_decc_out_c6_lo1_4_scanout[14];
assign ff_l2d_decc_out_c6_hi1_4_scanin[14]=ff_l2d_decc_out_c6_hi1_2_scanout[14];
assign ff_l2d_decc_out_c6_lo0_2_scanin[15]=ff_l2d_decc_out_c6_hi1_4_scanout[14];
assign ff_l2d_decc_out_c6_lo0_4_scanin[15]=ff_l2d_decc_out_c6_lo0_2_scanout[15];
assign ff_l2d_decc_out_c6_hi0_2_scanin[15]=ff_l2d_decc_out_c6_lo0_4_scanout[15];
assign ff_l2d_decc_out_c6_hi0_4_scanin[15]=ff_l2d_decc_out_c6_hi0_2_scanout[15];
assign ff_l2d_decc_out_c6_lo1_2_scanin[15]=ff_l2d_decc_out_c6_hi0_4_scanout[15];
assign ff_l2d_decc_out_c6_lo1_4_scanin[15]=ff_l2d_decc_out_c6_lo1_2_scanout[15];
assign ff_l2d_decc_out_c6_hi1_2_scanin[15]=ff_l2d_decc_out_c6_lo1_4_scanout[15];
assign ff_l2d_decc_out_c6_hi1_4_scanin[15]=ff_l2d_decc_out_c6_hi1_2_scanout[15];
assign ff_l2d_decc_out_c6_lo0_2_scanin[16]=ff_l2d_decc_out_c6_hi1_4_scanout[15];
assign ff_l2d_decc_out_c6_lo0_4_scanin[16]=ff_l2d_decc_out_c6_lo0_2_scanout[16];
assign ff_l2d_decc_out_c6_hi0_2_scanin[16]=ff_l2d_decc_out_c6_lo0_4_scanout[16];
assign ff_l2d_decc_out_c6_hi0_4_scanin[16]=ff_l2d_decc_out_c6_hi0_2_scanout[16];
assign ff_l2d_decc_out_c6_lo1_2_scanin[16]=ff_l2d_decc_out_c6_hi0_4_scanout[16];
assign ff_l2d_decc_out_c6_lo1_4_scanin[16]=ff_l2d_decc_out_c6_lo1_2_scanout[16];
assign ff_l2d_decc_out_c6_hi1_2_scanin[16]=ff_l2d_decc_out_c6_lo1_4_scanout[16];
assign ff_l2d_decc_out_c6_hi1_4_scanin[16]=ff_l2d_decc_out_c6_hi1_2_scanout[16];
assign ff_l2d_decc_out_c6_lo0_2_scanin[17]=ff_l2d_decc_out_c6_hi1_4_scanout[16];
assign ff_l2d_decc_out_c6_lo0_4_scanin[17]=ff_l2d_decc_out_c6_lo0_2_scanout[17];
assign ff_l2d_decc_out_c6_hi0_2_scanin[17]=ff_l2d_decc_out_c6_lo0_4_scanout[17];
assign ff_l2d_decc_out_c6_hi0_4_scanin[17]=ff_l2d_decc_out_c6_hi0_2_scanout[17];
assign ff_l2d_decc_out_c6_lo1_2_scanin[17]=ff_l2d_decc_out_c6_hi0_4_scanout[17];
assign ff_l2d_decc_out_c6_lo1_4_scanin[17]=ff_l2d_decc_out_c6_lo1_2_scanout[17];
assign ff_l2d_decc_out_c6_hi1_2_scanin[17]=ff_l2d_decc_out_c6_lo1_4_scanout[17];
assign ff_l2d_decc_out_c6_hi1_4_scanin[17]=ff_l2d_decc_out_c6_hi1_2_scanout[17];
assign ff_l2d_decc_out_c6_lo0_2_scanin[18]=ff_l2d_decc_out_c6_hi1_4_scanout[17];
assign ff_l2d_decc_out_c6_lo0_4_scanin[18]=ff_l2d_decc_out_c6_lo0_2_scanout[18];
assign ff_l2d_decc_out_c6_hi0_2_scanin[18]=ff_l2d_decc_out_c6_lo0_4_scanout[18];
assign ff_l2d_decc_out_c6_hi0_4_scanin[18]=ff_l2d_decc_out_c6_hi0_2_scanout[18];
assign ff_l2d_decc_out_c6_lo1_2_scanin[18]=ff_l2d_decc_out_c6_hi0_4_scanout[18];
assign ff_l2d_decc_out_c6_lo1_4_scanin[18]=ff_l2d_decc_out_c6_lo1_2_scanout[18];
assign ff_l2d_decc_out_c6_hi1_2_scanin[18]=ff_l2d_decc_out_c6_lo1_4_scanout[18];
assign ff_l2d_decc_out_c6_hi1_4_scanin[18]=ff_l2d_decc_out_c6_hi1_2_scanout[18];
assign ff_l2d_decc_out_c6_lo0_2_scanin[19]=ff_l2d_decc_out_c6_hi1_4_scanout[18];
assign ff_l2d_decc_out_c6_lo0_4_scanin[19]=ff_l2d_decc_out_c6_lo0_2_scanout[19];
assign ff_l2d_decc_out_c6_hi0_2_scanin[19]=ff_l2d_decc_out_c6_lo0_4_scanout[19];
assign ff_l2d_decc_out_c6_hi0_4_scanin[19]=ff_l2d_decc_out_c6_hi0_2_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[19]=ff_l2d_decc_out_c6_hi0_4_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[19]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[20]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[20]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[20]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[20]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[21]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[21]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[21]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[21]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[22]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[22]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[22]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[22]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[23]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[23]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[23]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[23]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[24]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[29]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[24];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[28]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[28]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[28]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[28]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[27]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[27]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[27]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[27]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[26]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[26]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[26]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[26]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[25]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[25]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[25]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[25]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[24]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[24]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[24];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[24]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[24];
assign ff_cache_col_offset_c5_123_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[24];
assign ff_cache_col_offset_c5_123_scanin[2]=ff_cache_col_offset_c5_123_scanout[0];
assign ff_cache_col_offset_c4_123_scanin[0]=ff_cache_col_offset_c5_123_scanout[2];
assign ff_cache_col_offset_c4_123_scanin[2]=ff_cache_col_offset_c4_123_scanout[0];
assign ff_cache_col_offset_c4_tog_123_scanin[0]=ff_cache_col_offset_c4_123_scanout[2];
assign ff_cache_cache_rd_wr_c5_21_scanin=ff_cache_col_offset_c4_tog_123_scanout[0];
assign ff_cache_col_offset_c5_123_scanin[1]=ff_cache_cache_rd_wr_c5_21_scanout;
assign ff_cache_col_offset_c5_123_scanin[3]=ff_cache_col_offset_c5_123_scanout[1];
assign ff_cache_col_offset_c4_123_scanin[1]=ff_cache_col_offset_c5_123_scanout[3];
assign ff_cache_col_offset_c4_123_scanin[3]=ff_cache_col_offset_c4_123_scanout[1];
assign ff_cache_col_offset_c4_tog_123_scanin[1]=ff_cache_col_offset_c4_123_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[38]=ff_cache_col_offset_c4_tog_123_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[38]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[38]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[38]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[37]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[37]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[37]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[37]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[36]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[36]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[36]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[36]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[35]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[35]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[35]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[35]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[34]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[34]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[34]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[29]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[29]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[29]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[30]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[30]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[30]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[30]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[31]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[31]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[31]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[31]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[32]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[32]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[32]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[32]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[33]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_hi0_4_scanin[33]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo1_4_scanin[33]=ff_l2b_l2d_fbdecc_c52_hi0_4_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_hi1_4_scanin[33]=ff_l2b_l2d_fbdecc_c52_lo1_4_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo0_4_scanin[34]=ff_l2b_l2d_fbdecc_c52_hi1_4_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[38]=ff_l2b_l2d_fbdecc_c52_lo0_4_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[38]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[38]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[38]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[37]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[37]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[37]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[37]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[36]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[36]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[36]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[36]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[35]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[35]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[35]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[35]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[34]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[34]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[34]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[29]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[29]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[29]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[30]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[30]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[30]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[30]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[31]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[31]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[31]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[31]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[32]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[32]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[32]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[32]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[33]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[33]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[33]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[33]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[34]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[19]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[19]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[20]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[20]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[20]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[20]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[21]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[21]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[21]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[21]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[22]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[22]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[22]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[22]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[23]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[23]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[23]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[23]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[24]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[29]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[24];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[28]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[28]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[28]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[28]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[27]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[27]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[27]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[27]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[26]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[26]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[26]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[26]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[25]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[25]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[25]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_lo0_2_scanin[25]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_hi1_2_scanin[24]=ff_l2b_l2d_fbdecc_c52_lo0_2_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_lo1_2_scanin[24]=ff_l2b_l2d_fbdecc_c52_hi1_2_scanout[24];
assign ff_l2b_l2d_fbdecc_c52_hi0_2_scanin[24]=ff_l2b_l2d_fbdecc_c52_lo1_2_scanout[24];
assign ff_l2d_decc_out_c6_lo1_2_scanin[19]=ff_l2b_l2d_fbdecc_c52_hi0_2_scanout[24];
assign ff_l2d_decc_out_c6_lo1_4_scanin[19]=ff_l2d_decc_out_c6_lo1_2_scanout[19];
assign ff_l2d_decc_out_c6_hi1_2_scanin[19]=ff_l2d_decc_out_c6_lo1_4_scanout[19];
assign ff_l2d_decc_out_c6_hi1_4_scanin[19]=ff_l2d_decc_out_c6_hi1_2_scanout[19];
assign ff_l2d_decc_out_c6_lo0_2_scanin[20]=ff_l2d_decc_out_c6_hi1_4_scanout[19];
assign ff_l2d_decc_out_c6_lo0_4_scanin[20]=ff_l2d_decc_out_c6_lo0_2_scanout[20];
assign ff_l2d_decc_out_c6_hi0_2_scanin[20]=ff_l2d_decc_out_c6_lo0_4_scanout[20];
assign ff_l2d_decc_out_c6_hi0_4_scanin[20]=ff_l2d_decc_out_c6_hi0_2_scanout[20];
assign ff_l2d_decc_out_c6_lo1_2_scanin[20]=ff_l2d_decc_out_c6_hi0_4_scanout[20];
assign ff_l2d_decc_out_c6_lo1_4_scanin[20]=ff_l2d_decc_out_c6_lo1_2_scanout[20];
assign ff_l2d_decc_out_c6_hi1_2_scanin[20]=ff_l2d_decc_out_c6_lo1_4_scanout[20];
assign ff_l2d_decc_out_c6_hi1_4_scanin[20]=ff_l2d_decc_out_c6_hi1_2_scanout[20];
assign ff_l2d_decc_out_c6_lo0_2_scanin[21]=ff_l2d_decc_out_c6_hi1_4_scanout[20];
assign ff_l2d_decc_out_c6_lo0_4_scanin[21]=ff_l2d_decc_out_c6_lo0_2_scanout[21];
assign ff_l2d_decc_out_c6_hi0_2_scanin[21]=ff_l2d_decc_out_c6_lo0_4_scanout[21];
assign ff_l2d_decc_out_c6_hi0_4_scanin[21]=ff_l2d_decc_out_c6_hi0_2_scanout[21];
assign ff_l2d_decc_out_c6_lo1_2_scanin[21]=ff_l2d_decc_out_c6_hi0_4_scanout[21];
assign ff_l2d_decc_out_c6_lo1_4_scanin[21]=ff_l2d_decc_out_c6_lo1_2_scanout[21];
assign ff_l2d_decc_out_c6_hi1_2_scanin[21]=ff_l2d_decc_out_c6_lo1_4_scanout[21];
assign ff_l2d_decc_out_c6_hi1_4_scanin[21]=ff_l2d_decc_out_c6_hi1_2_scanout[21];
assign ff_l2d_decc_out_c6_lo0_2_scanin[22]=ff_l2d_decc_out_c6_hi1_4_scanout[21];
assign ff_l2d_decc_out_c6_lo0_4_scanin[22]=ff_l2d_decc_out_c6_lo0_2_scanout[22];
assign ff_l2d_decc_out_c6_hi0_2_scanin[22]=ff_l2d_decc_out_c6_lo0_4_scanout[22];
assign ff_l2d_decc_out_c6_hi0_4_scanin[22]=ff_l2d_decc_out_c6_hi0_2_scanout[22];
assign ff_l2d_decc_out_c6_lo1_2_scanin[22]=ff_l2d_decc_out_c6_hi0_4_scanout[22];
assign ff_l2d_decc_out_c6_lo1_4_scanin[22]=ff_l2d_decc_out_c6_lo1_2_scanout[22];
assign ff_l2d_decc_out_c6_hi1_2_scanin[22]=ff_l2d_decc_out_c6_lo1_4_scanout[22];
assign ff_l2d_decc_out_c6_hi1_4_scanin[22]=ff_l2d_decc_out_c6_hi1_2_scanout[22];
assign ff_l2d_decc_out_c6_lo0_2_scanin[23]=ff_l2d_decc_out_c6_hi1_4_scanout[22];
assign ff_l2d_decc_out_c6_lo0_4_scanin[23]=ff_l2d_decc_out_c6_lo0_2_scanout[23];
assign ff_l2d_decc_out_c6_hi0_2_scanin[23]=ff_l2d_decc_out_c6_lo0_4_scanout[23];
assign ff_l2d_decc_out_c6_hi0_4_scanin[23]=ff_l2d_decc_out_c6_hi0_2_scanout[23];
assign ff_l2d_decc_out_c6_lo1_2_scanin[23]=ff_l2d_decc_out_c6_hi0_4_scanout[23];
assign ff_l2d_decc_out_c6_lo1_4_scanin[23]=ff_l2d_decc_out_c6_lo1_2_scanout[23];
assign ff_l2d_decc_out_c6_hi1_2_scanin[23]=ff_l2d_decc_out_c6_lo1_4_scanout[23];
assign ff_l2d_decc_out_c6_hi1_4_scanin[23]=ff_l2d_decc_out_c6_hi1_2_scanout[23];
assign ff_l2d_decc_out_c6_lo0_2_scanin[24]=ff_l2d_decc_out_c6_hi1_4_scanout[23];
assign ff_l2d_decc_out_c6_lo0_4_scanin[24]=ff_l2d_decc_out_c6_lo0_2_scanout[24];
assign ff_l2d_decc_out_c6_hi0_2_scanin[24]=ff_l2d_decc_out_c6_lo0_4_scanout[24];
assign ff_l2d_decc_out_c6_hi0_4_scanin[24]=ff_l2d_decc_out_c6_hi0_2_scanout[24];
assign ff_l2d_decc_out_c6_lo1_2_scanin[24]=ff_l2d_decc_out_c6_hi0_4_scanout[24];
assign ff_l2d_decc_out_c6_lo1_4_scanin[24]=ff_l2d_decc_out_c6_lo1_2_scanout[24];
assign ff_l2d_decc_out_c6_hi1_2_scanin[24]=ff_l2d_decc_out_c6_lo1_4_scanout[24];
assign ff_l2d_decc_out_c6_hi1_4_scanin[24]=ff_l2d_decc_out_c6_hi1_2_scanout[24];
assign ff_l2d_decc_out_c6_lo0_2_scanin[25]=ff_l2d_decc_out_c6_hi1_4_scanout[24];
assign ff_l2d_decc_out_c6_lo0_4_scanin[25]=ff_l2d_decc_out_c6_lo0_2_scanout[25];
assign ff_l2d_decc_out_c6_hi0_2_scanin[25]=ff_l2d_decc_out_c6_lo0_4_scanout[25];
assign ff_l2d_decc_out_c6_hi0_4_scanin[25]=ff_l2d_decc_out_c6_hi0_2_scanout[25];
assign ff_l2d_decc_out_c6_lo1_2_scanin[25]=ff_l2d_decc_out_c6_hi0_4_scanout[25];
assign ff_l2d_decc_out_c6_lo1_4_scanin[25]=ff_l2d_decc_out_c6_lo1_2_scanout[25];
assign ff_l2d_decc_out_c6_hi1_2_scanin[25]=ff_l2d_decc_out_c6_lo1_4_scanout[25];
assign ff_l2d_decc_out_c6_hi1_4_scanin[25]=ff_l2d_decc_out_c6_hi1_2_scanout[25];
assign ff_l2d_decc_out_c6_lo0_2_scanin[26]=ff_l2d_decc_out_c6_hi1_4_scanout[25];
assign ff_l2d_decc_out_c6_lo0_4_scanin[26]=ff_l2d_decc_out_c6_lo0_2_scanout[26];
assign ff_l2d_decc_out_c6_hi0_2_scanin[26]=ff_l2d_decc_out_c6_lo0_4_scanout[26];
assign ff_l2d_decc_out_c6_hi0_4_scanin[26]=ff_l2d_decc_out_c6_hi0_2_scanout[26];
assign ff_l2d_decc_out_c6_lo1_2_scanin[26]=ff_l2d_decc_out_c6_hi0_4_scanout[26];
assign ff_l2d_decc_out_c6_lo1_4_scanin[26]=ff_l2d_decc_out_c6_lo1_2_scanout[26];
assign ff_l2d_decc_out_c6_hi1_2_scanin[26]=ff_l2d_decc_out_c6_lo1_4_scanout[26];
assign ff_l2d_decc_out_c6_hi1_4_scanin[26]=ff_l2d_decc_out_c6_hi1_2_scanout[26];
assign ff_l2d_decc_out_c6_lo0_2_scanin[27]=ff_l2d_decc_out_c6_hi1_4_scanout[26];
assign ff_l2d_decc_out_c6_lo0_4_scanin[27]=ff_l2d_decc_out_c6_lo0_2_scanout[27];
assign ff_l2d_decc_out_c6_hi0_2_scanin[27]=ff_l2d_decc_out_c6_lo0_4_scanout[27];
assign ff_l2d_decc_out_c6_hi0_4_scanin[27]=ff_l2d_decc_out_c6_hi0_2_scanout[27];
assign ff_l2d_decc_out_c6_lo1_2_scanin[27]=ff_l2d_decc_out_c6_hi0_4_scanout[27];
assign ff_l2d_decc_out_c6_lo1_4_scanin[27]=ff_l2d_decc_out_c6_lo1_2_scanout[27];
assign ff_l2d_decc_out_c6_hi1_2_scanin[27]=ff_l2d_decc_out_c6_lo1_4_scanout[27];
assign ff_l2d_decc_out_c6_hi1_4_scanin[27]=ff_l2d_decc_out_c6_hi1_2_scanout[27];
assign ff_l2d_decc_out_c6_lo0_2_scanin[28]=ff_l2d_decc_out_c6_hi1_4_scanout[27];
assign ff_l2d_decc_out_c6_lo0_4_scanin[28]=ff_l2d_decc_out_c6_lo0_2_scanout[28];
assign ff_l2d_decc_out_c6_hi0_2_scanin[28]=ff_l2d_decc_out_c6_lo0_4_scanout[28];
assign ff_l2d_decc_out_c6_hi0_4_scanin[28]=ff_l2d_decc_out_c6_hi0_2_scanout[28];
assign ff_l2d_decc_out_c6_lo1_2_scanin[28]=ff_l2d_decc_out_c6_hi0_4_scanout[28];
assign ff_l2d_decc_out_c6_lo1_4_scanin[28]=ff_l2d_decc_out_c6_lo1_2_scanout[28];
assign ff_l2d_decc_out_c6_hi1_2_scanin[28]=ff_l2d_decc_out_c6_lo1_4_scanout[28];
assign ff_l2d_decc_out_c6_hi1_4_scanin[28]=ff_l2d_decc_out_c6_hi1_2_scanout[28];
assign ff_l2d_decc_out_c6_lo0_2_scanin[29]=ff_l2d_decc_out_c6_hi1_4_scanout[28];
assign ff_l2d_decc_out_c6_lo0_4_scanin[29]=ff_l2d_decc_out_c6_lo0_2_scanout[29];
assign ff_l2d_decc_out_c6_hi0_2_scanin[29]=ff_l2d_decc_out_c6_lo0_4_scanout[29];
assign ff_l2d_decc_out_c6_hi0_4_scanin[29]=ff_l2d_decc_out_c6_hi0_2_scanout[29];
assign ff_l2d_decc_out_c6_lo1_2_scanin[29]=ff_l2d_decc_out_c6_hi0_4_scanout[29];
assign ff_l2d_decc_out_c6_lo1_4_scanin[29]=ff_l2d_decc_out_c6_lo1_2_scanout[29];
assign ff_l2d_decc_out_c6_hi1_2_scanin[29]=ff_l2d_decc_out_c6_lo1_4_scanout[29];
assign ff_l2d_decc_out_c6_hi1_4_scanin[29]=ff_l2d_decc_out_c6_hi1_2_scanout[29];
assign ff_l2d_decc_out_c6_lo0_2_scanin[30]=ff_l2d_decc_out_c6_hi1_4_scanout[29];
assign ff_l2d_decc_out_c6_lo0_4_scanin[30]=ff_l2d_decc_out_c6_lo0_2_scanout[30];
assign ff_l2d_decc_out_c6_hi0_2_scanin[30]=ff_l2d_decc_out_c6_lo0_4_scanout[30];
assign ff_l2d_decc_out_c6_hi0_4_scanin[30]=ff_l2d_decc_out_c6_hi0_2_scanout[30];
assign ff_l2d_decc_out_c6_lo1_2_scanin[30]=ff_l2d_decc_out_c6_hi0_4_scanout[30];
assign ff_l2d_decc_out_c6_lo1_4_scanin[30]=ff_l2d_decc_out_c6_lo1_2_scanout[30];
assign ff_l2d_decc_out_c6_hi1_2_scanin[30]=ff_l2d_decc_out_c6_lo1_4_scanout[30];
assign ff_l2d_decc_out_c6_hi1_4_scanin[30]=ff_l2d_decc_out_c6_hi1_2_scanout[30];
assign ff_l2d_decc_out_c6_lo0_2_scanin[31]=ff_l2d_decc_out_c6_hi1_4_scanout[30];
assign ff_l2d_decc_out_c6_lo0_4_scanin[31]=ff_l2d_decc_out_c6_lo0_2_scanout[31];
assign ff_l2d_decc_out_c6_hi0_2_scanin[31]=ff_l2d_decc_out_c6_lo0_4_scanout[31];
assign ff_l2d_decc_out_c6_hi0_4_scanin[31]=ff_l2d_decc_out_c6_hi0_2_scanout[31];
assign ff_l2d_decc_out_c6_lo1_2_scanin[31]=ff_l2d_decc_out_c6_hi0_4_scanout[31];
assign ff_l2d_decc_out_c6_lo1_4_scanin[31]=ff_l2d_decc_out_c6_lo1_2_scanout[31];
assign ff_l2d_decc_out_c6_hi1_2_scanin[31]=ff_l2d_decc_out_c6_lo1_4_scanout[31];
assign ff_l2d_decc_out_c6_hi1_4_scanin[31]=ff_l2d_decc_out_c6_hi1_2_scanout[31];
assign ff_l2d_decc_out_c6_lo0_2_scanin[32]=ff_l2d_decc_out_c6_hi1_4_scanout[31];
assign ff_l2d_decc_out_c6_lo0_4_scanin[32]=ff_l2d_decc_out_c6_lo0_2_scanout[32];
assign ff_l2d_decc_out_c6_hi0_2_scanin[32]=ff_l2d_decc_out_c6_lo0_4_scanout[32];
assign ff_l2d_decc_out_c6_hi0_4_scanin[32]=ff_l2d_decc_out_c6_hi0_2_scanout[32];
assign ff_l2d_decc_out_c6_lo1_2_scanin[32]=ff_l2d_decc_out_c6_hi0_4_scanout[32];
assign ff_l2d_decc_out_c6_lo1_4_scanin[32]=ff_l2d_decc_out_c6_lo1_2_scanout[32];
assign ff_l2d_decc_out_c6_hi1_2_scanin[32]=ff_l2d_decc_out_c6_lo1_4_scanout[32];
assign ff_l2d_decc_out_c6_hi1_4_scanin[32]=ff_l2d_decc_out_c6_hi1_2_scanout[32];
assign ff_l2d_decc_out_c6_lo0_2_scanin[33]=ff_l2d_decc_out_c6_hi1_4_scanout[32];
assign ff_l2d_decc_out_c6_lo0_4_scanin[33]=ff_l2d_decc_out_c6_lo0_2_scanout[33];
assign ff_l2d_decc_out_c6_hi0_2_scanin[33]=ff_l2d_decc_out_c6_lo0_4_scanout[33];
assign ff_l2d_decc_out_c6_hi0_4_scanin[33]=ff_l2d_decc_out_c6_hi0_2_scanout[33];
assign ff_l2d_decc_out_c6_lo1_2_scanin[33]=ff_l2d_decc_out_c6_hi0_4_scanout[33];
assign ff_l2d_decc_out_c6_lo1_4_scanin[33]=ff_l2d_decc_out_c6_lo1_2_scanout[33];
assign ff_l2d_decc_out_c6_hi1_2_scanin[33]=ff_l2d_decc_out_c6_lo1_4_scanout[33];
assign ff_l2d_decc_out_c6_hi1_4_scanin[33]=ff_l2d_decc_out_c6_hi1_2_scanout[33];
assign ff_l2d_decc_out_c6_lo0_2_scanin[34]=ff_l2d_decc_out_c6_hi1_4_scanout[33];
assign ff_l2d_decc_out_c6_lo0_4_scanin[34]=ff_l2d_decc_out_c6_lo0_2_scanout[34];
assign ff_l2d_decc_out_c6_hi0_2_scanin[34]=ff_l2d_decc_out_c6_lo0_4_scanout[34];
assign ff_l2d_decc_out_c6_hi0_4_scanin[34]=ff_l2d_decc_out_c6_hi0_2_scanout[34];
assign ff_l2d_decc_out_c6_lo1_2_scanin[34]=ff_l2d_decc_out_c6_hi0_4_scanout[34];
assign ff_l2d_decc_out_c6_lo1_4_scanin[34]=ff_l2d_decc_out_c6_lo1_2_scanout[34];
assign ff_l2d_decc_out_c6_hi1_2_scanin[34]=ff_l2d_decc_out_c6_lo1_4_scanout[34];
assign ff_l2d_decc_out_c6_hi1_4_scanin[34]=ff_l2d_decc_out_c6_hi1_2_scanout[34];
assign ff_l2d_decc_out_c6_lo0_2_scanin[35]=ff_l2d_decc_out_c6_hi1_4_scanout[34];
assign ff_l2d_decc_out_c6_lo0_4_scanin[35]=ff_l2d_decc_out_c6_lo0_2_scanout[35];
assign ff_l2d_decc_out_c6_hi0_2_scanin[35]=ff_l2d_decc_out_c6_lo0_4_scanout[35];
assign ff_l2d_decc_out_c6_hi0_4_scanin[35]=ff_l2d_decc_out_c6_hi0_2_scanout[35];
assign ff_l2d_decc_out_c6_lo1_2_scanin[35]=ff_l2d_decc_out_c6_hi0_4_scanout[35];
assign ff_l2d_decc_out_c6_lo1_4_scanin[35]=ff_l2d_decc_out_c6_lo1_2_scanout[35];
assign ff_l2d_decc_out_c6_hi1_2_scanin[35]=ff_l2d_decc_out_c6_lo1_4_scanout[35];
assign ff_l2d_decc_out_c6_hi1_4_scanin[35]=ff_l2d_decc_out_c6_hi1_2_scanout[35];
assign ff_l2d_decc_out_c6_lo0_2_scanin[36]=ff_l2d_decc_out_c6_hi1_4_scanout[35];
assign ff_l2d_decc_out_c6_lo0_4_scanin[36]=ff_l2d_decc_out_c6_lo0_2_scanout[36];
assign ff_l2d_decc_out_c6_hi0_2_scanin[36]=ff_l2d_decc_out_c6_lo0_4_scanout[36];
assign ff_l2d_decc_out_c6_hi0_4_scanin[36]=ff_l2d_decc_out_c6_hi0_2_scanout[36];
assign ff_l2d_decc_out_c6_lo1_2_scanin[36]=ff_l2d_decc_out_c6_hi0_4_scanout[36];
assign ff_l2d_decc_out_c6_lo1_4_scanin[36]=ff_l2d_decc_out_c6_lo1_2_scanout[36];
assign ff_l2d_decc_out_c6_hi1_2_scanin[36]=ff_l2d_decc_out_c6_lo1_4_scanout[36];
assign ff_l2d_decc_out_c6_hi1_4_scanin[36]=ff_l2d_decc_out_c6_hi1_2_scanout[36];
assign ff_l2d_decc_out_c6_lo0_2_scanin[37]=ff_l2d_decc_out_c6_hi1_4_scanout[36];
assign ff_l2d_decc_out_c6_lo0_4_scanin[37]=ff_l2d_decc_out_c6_lo0_2_scanout[37];
assign ff_l2d_decc_out_c6_hi0_2_scanin[37]=ff_l2d_decc_out_c6_lo0_4_scanout[37];
assign ff_l2d_decc_out_c6_hi0_4_scanin[37]=ff_l2d_decc_out_c6_hi0_2_scanout[37];
assign ff_l2d_decc_out_c6_lo1_2_scanin[37]=ff_l2d_decc_out_c6_hi0_4_scanout[37];
assign ff_l2d_decc_out_c6_lo1_4_scanin[37]=ff_l2d_decc_out_c6_lo1_2_scanout[37];
assign ff_l2d_decc_out_c6_hi1_2_scanin[37]=ff_l2d_decc_out_c6_lo1_4_scanout[37];
assign ff_l2d_decc_out_c6_hi1_4_scanin[37]=ff_l2d_decc_out_c6_hi1_2_scanout[37];
assign ff_l2d_decc_out_c6_lo0_2_scanin[38]=ff_l2d_decc_out_c6_hi1_4_scanout[37];
assign ff_l2d_decc_out_c6_lo0_4_scanin[38]=ff_l2d_decc_out_c6_lo0_2_scanout[38];
assign ff_l2d_decc_out_c6_hi0_2_scanin[38]=ff_l2d_decc_out_c6_lo0_4_scanout[38];
assign ff_l2d_decc_out_c6_hi0_4_scanin[38]=ff_l2d_decc_out_c6_hi0_2_scanout[38];
assign ff_l2d_decc_out_c6_lo1_2_scanin[38]=ff_l2d_decc_out_c6_hi0_4_scanout[38];
assign ff_l2d_decc_out_c6_lo1_4_scanin[38]=ff_l2d_decc_out_c6_lo1_2_scanout[38];
assign ff_l2d_decc_out_c6_hi1_2_scanin[38]=ff_l2d_decc_out_c6_lo1_4_scanout[38];
assign ff_l2d_decc_out_c6_hi1_4_scanin[38]=ff_l2d_decc_out_c6_hi1_2_scanout[38];
assign  so_q23=ff_l2d_decc_out_c6_hi1_4_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[19]=so_tstmod;
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[19]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[20]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[20]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[20]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[20]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[21]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[21]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[21]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[21]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[22]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[22]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[22]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[22]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[23]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[23]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[23]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[23]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[24]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[29]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[24];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[28]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[28]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[28]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[28]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[27]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[27]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[27]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[27]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[26]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[26]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[26]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[26]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[25]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[25]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[25]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[25]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[24]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[24]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[24];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[24]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[24];
assign ff_cache_col_offset_c5_101_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[24];
assign ff_cache_col_offset_c5_101_scanin[2]=ff_cache_col_offset_c5_101_scanout[0];
assign ff_cache_col_offset_c4_101_scanin[0]=ff_cache_col_offset_c5_101_scanout[2];
assign ff_cache_col_offset_c4_101_scanin[2]=ff_cache_col_offset_c4_101_scanout[0];
assign ff_cache_col_offset_c4_tog_101_scanin[0]=ff_cache_col_offset_c4_101_scanout[2];
assign ff_cache_cache_rd_wr_c5_01_scanin=ff_cache_col_offset_c4_tog_101_scanout[0];
assign ff_cache_col_offset_c5_101_scanin[1]=ff_cache_cache_rd_wr_c5_01_scanout;
assign ff_cache_col_offset_c5_101_scanin[3]=ff_cache_col_offset_c5_101_scanout[1];
assign ff_cache_col_offset_c4_101_scanin[1]=ff_cache_col_offset_c5_101_scanout[3];
assign ff_cache_col_offset_c4_101_scanin[3]=ff_cache_col_offset_c4_101_scanout[1];
assign ff_cache_col_offset_c4_tog_101_scanin[1]=ff_cache_col_offset_c4_101_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[38]=ff_cache_col_offset_c4_tog_101_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[38]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[38]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[38]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[37]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[37]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[37]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[37]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[36]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[36]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[36]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[36]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[35]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[35]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[35]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[35]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[34]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[34]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[34]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[29]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[29]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[29]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[30]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[30]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[30]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[30]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[31]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[31]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[31]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[31]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[32]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[32]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[32]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[32]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[33]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[33]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[33]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[33]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[34]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[33];
assign ff_l2t_l2d_stdecc_c3_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[34];
assign ff_l2t_l2d_stdecc_c3_scanin[1]=ff_l2t_l2d_stdecc_c3_scanout[0];
assign ff_l2t_l2d_stdecc_c3_scanin[2]=ff_l2t_l2d_stdecc_c3_scanout[1];
assign ff_l2t_l2d_stdecc_c3_scanin[3]=ff_l2t_l2d_stdecc_c3_scanout[2];
assign ff_l2t_l2d_stdecc_c3_scanin[4]=ff_l2t_l2d_stdecc_c3_scanout[3];
assign ff_l2t_l2d_stdecc_c3_scanin[5]=ff_l2t_l2d_stdecc_c3_scanout[4];
assign ff_l2t_l2d_stdecc_c3_scanin[6]=ff_l2t_l2d_stdecc_c3_scanout[5];
assign ff_l2t_l2d_stdecc_c3_scanin[7]=ff_l2t_l2d_stdecc_c3_scanout[6];
assign ff_l2t_l2d_stdecc_c3_scanin[8]=ff_l2t_l2d_stdecc_c3_scanout[7];
assign ff_l2t_l2d_stdecc_c3_scanin[9]=ff_l2t_l2d_stdecc_c3_scanout[8];
assign ff_l2t_l2d_stdecc_c3_scanin[10]=ff_l2t_l2d_stdecc_c3_scanout[9];
assign ff_l2t_l2d_stdecc_c3_scanin[11]=ff_l2t_l2d_stdecc_c3_scanout[10];
assign ff_l2t_l2d_stdecc_c3_scanin[12]=ff_l2t_l2d_stdecc_c3_scanout[11];
assign ff_l2t_l2d_stdecc_c3_scanin[13]=ff_l2t_l2d_stdecc_c3_scanout[12];
assign ff_l2t_l2d_stdecc_c3_scanin[14]=ff_l2t_l2d_stdecc_c3_scanout[13];
assign ff_l2t_l2d_stdecc_c3_scanin[15]=ff_l2t_l2d_stdecc_c3_scanout[14];
assign ff_l2t_l2d_stdecc_c3_scanin[16]=ff_l2t_l2d_stdecc_c3_scanout[15];
assign ff_l2t_l2d_stdecc_c3_scanin[17]=ff_l2t_l2d_stdecc_c3_scanout[16];
assign ff_l2t_l2d_stdecc_c3_scanin[18]=ff_l2t_l2d_stdecc_c3_scanout[17];
assign ff_l2t_l2d_stdecc_c3_scanin[19]=ff_l2t_l2d_stdecc_c3_scanout[18];
assign ff_l2t_l2d_stdecc_c3_scanin[20]=ff_l2t_l2d_stdecc_c3_scanout[19];
assign ff_l2t_l2d_stdecc_c3_scanin[21]=ff_l2t_l2d_stdecc_c3_scanout[20];
assign ff_l2t_l2d_stdecc_c3_scanin[22]=ff_l2t_l2d_stdecc_c3_scanout[21];
assign ff_l2t_l2d_stdecc_c3_scanin[23]=ff_l2t_l2d_stdecc_c3_scanout[22];
assign ff_l2t_l2d_stdecc_c3_scanin[24]=ff_l2t_l2d_stdecc_c3_scanout[23];
assign ff_l2t_l2d_stdecc_c3_scanin[25]=ff_l2t_l2d_stdecc_c3_scanout[24];
assign ff_l2t_l2d_stdecc_c3_scanin[26]=ff_l2t_l2d_stdecc_c3_scanout[25];
assign ff_l2t_l2d_stdecc_c3_scanin[27]=ff_l2t_l2d_stdecc_c3_scanout[26];
assign ff_l2t_l2d_stdecc_c3_scanin[28]=ff_l2t_l2d_stdecc_c3_scanout[27];
assign ff_l2t_l2d_stdecc_c3_scanin[29]=ff_l2t_l2d_stdecc_c3_scanout[28];
assign ff_l2t_l2d_stdecc_c3_scanin[30]=ff_l2t_l2d_stdecc_c3_scanout[29];
assign ff_l2t_l2d_stdecc_c3_scanin[31]=ff_l2t_l2d_stdecc_c3_scanout[30];
assign ff_l2t_l2d_stdecc_c3_scanin[32]=ff_l2t_l2d_stdecc_c3_scanout[31];
assign ff_l2t_l2d_stdecc_c3_scanin[33]=ff_l2t_l2d_stdecc_c3_scanout[32];
assign ff_l2t_l2d_stdecc_c3_scanin[34]=ff_l2t_l2d_stdecc_c3_scanout[33];
assign ff_l2t_l2d_stdecc_c3_scanin[35]=ff_l2t_l2d_stdecc_c3_scanout[34];
assign ff_l2t_l2d_stdecc_c3_scanin[36]=ff_l2t_l2d_stdecc_c3_scanout[35];
assign ff_l2t_l2d_stdecc_c3_scanin[37]=ff_l2t_l2d_stdecc_c3_scanout[36];
assign ff_l2t_l2d_stdecc_c3_scanin[38]=ff_l2t_l2d_stdecc_c3_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[38]=ff_l2t_l2d_stdecc_c3_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[38]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[38]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[38]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[37]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[37]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[37]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[37]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[36]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[37];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[36]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[36]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[36]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[35]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[36];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[35]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[35]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[35]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[34]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[35];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[34]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[34]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[29]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[29]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[29]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[30]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[30]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[30]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[30]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[31]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[30];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[31]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[31]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[31]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[32]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[31];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[32]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[32]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[32]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[33]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[32];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[33]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[33]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[33]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[34]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[33];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[19]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[34];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[19]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[20]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[20]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[20]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[20]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[21]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[20];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[21]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[21]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[21]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[22]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[21];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[22]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[22]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[22]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[23]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[22];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[23]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[23]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[23]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[24]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[23];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[29]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[24];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[28]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[29];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[28]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[28]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[28]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[27]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[28];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[27]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[27]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[27]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[26]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[27];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[26]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[26]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[26]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[25]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[26];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[25]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[25]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[25]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[24]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[25];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[24]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[24];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[24]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[24];
assign ff_l2d_decc_out_c6_lo1_1_scanin[19]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[24];
assign ff_l2d_decc_out_c6_lo1_3_scanin[19]=ff_l2d_decc_out_c6_lo1_1_scanout[19];
assign ff_l2d_decc_out_c6_hi1_1_scanin[19]=ff_l2d_decc_out_c6_lo1_3_scanout[19];
assign ff_l2d_decc_out_c6_hi1_3_scanin[19]=ff_l2d_decc_out_c6_hi1_1_scanout[19];
assign ff_l2d_decc_out_c6_lo0_1_scanin[20]=ff_l2d_decc_out_c6_hi1_3_scanout[19];
assign ff_l2d_decc_out_c6_lo0_3_scanin[20]=ff_l2d_decc_out_c6_lo0_1_scanout[20];
assign ff_l2d_decc_out_c6_hi0_1_scanin[20]=ff_l2d_decc_out_c6_lo0_3_scanout[20];
assign ff_l2d_decc_out_c6_hi0_3_scanin[20]=ff_l2d_decc_out_c6_hi0_1_scanout[20];
assign ff_l2d_decc_out_c6_lo1_1_scanin[20]=ff_l2d_decc_out_c6_hi0_3_scanout[20];
assign ff_l2d_decc_out_c6_lo1_3_scanin[20]=ff_l2d_decc_out_c6_lo1_1_scanout[20];
assign ff_l2d_decc_out_c6_hi1_1_scanin[20]=ff_l2d_decc_out_c6_lo1_3_scanout[20];
assign ff_l2d_decc_out_c6_hi1_3_scanin[20]=ff_l2d_decc_out_c6_hi1_1_scanout[20];
assign ff_l2d_decc_out_c6_lo0_1_scanin[21]=ff_l2d_decc_out_c6_hi1_3_scanout[20];
assign ff_l2d_decc_out_c6_lo0_3_scanin[21]=ff_l2d_decc_out_c6_lo0_1_scanout[21];
assign ff_l2d_decc_out_c6_hi0_1_scanin[21]=ff_l2d_decc_out_c6_lo0_3_scanout[21];
assign ff_l2d_decc_out_c6_hi0_3_scanin[21]=ff_l2d_decc_out_c6_hi0_1_scanout[21];
assign ff_l2d_decc_out_c6_lo1_1_scanin[21]=ff_l2d_decc_out_c6_hi0_3_scanout[21];
assign ff_l2d_decc_out_c6_lo1_3_scanin[21]=ff_l2d_decc_out_c6_lo1_1_scanout[21];
assign ff_l2d_decc_out_c6_hi1_1_scanin[21]=ff_l2d_decc_out_c6_lo1_3_scanout[21];
assign ff_l2d_decc_out_c6_hi1_3_scanin[21]=ff_l2d_decc_out_c6_hi1_1_scanout[21];
assign ff_l2d_decc_out_c6_lo0_1_scanin[22]=ff_l2d_decc_out_c6_hi1_3_scanout[21];
assign ff_l2d_decc_out_c6_lo0_3_scanin[22]=ff_l2d_decc_out_c6_lo0_1_scanout[22];
assign ff_l2d_decc_out_c6_hi0_1_scanin[22]=ff_l2d_decc_out_c6_lo0_3_scanout[22];
assign ff_l2d_decc_out_c6_hi0_3_scanin[22]=ff_l2d_decc_out_c6_hi0_1_scanout[22];
assign ff_l2d_decc_out_c6_lo1_1_scanin[22]=ff_l2d_decc_out_c6_hi0_3_scanout[22];
assign ff_l2d_decc_out_c6_lo1_3_scanin[22]=ff_l2d_decc_out_c6_lo1_1_scanout[22];
assign ff_l2d_decc_out_c6_hi1_1_scanin[22]=ff_l2d_decc_out_c6_lo1_3_scanout[22];
assign ff_l2d_decc_out_c6_hi1_3_scanin[22]=ff_l2d_decc_out_c6_hi1_1_scanout[22];
assign ff_l2d_decc_out_c6_lo0_1_scanin[23]=ff_l2d_decc_out_c6_hi1_3_scanout[22];
assign ff_l2d_decc_out_c6_lo0_3_scanin[23]=ff_l2d_decc_out_c6_lo0_1_scanout[23];
assign ff_l2d_decc_out_c6_hi0_1_scanin[23]=ff_l2d_decc_out_c6_lo0_3_scanout[23];
assign ff_l2d_decc_out_c6_hi0_3_scanin[23]=ff_l2d_decc_out_c6_hi0_1_scanout[23];
assign ff_l2d_decc_out_c6_lo1_1_scanin[23]=ff_l2d_decc_out_c6_hi0_3_scanout[23];
assign ff_l2d_decc_out_c6_lo1_3_scanin[23]=ff_l2d_decc_out_c6_lo1_1_scanout[23];
assign ff_l2d_decc_out_c6_hi1_1_scanin[23]=ff_l2d_decc_out_c6_lo1_3_scanout[23];
assign ff_l2d_decc_out_c6_hi1_3_scanin[23]=ff_l2d_decc_out_c6_hi1_1_scanout[23];
assign ff_l2d_decc_out_c6_lo0_1_scanin[24]=ff_l2d_decc_out_c6_hi1_3_scanout[23];
assign ff_l2d_decc_out_c6_lo0_3_scanin[24]=ff_l2d_decc_out_c6_lo0_1_scanout[24];
assign ff_l2d_decc_out_c6_hi0_1_scanin[24]=ff_l2d_decc_out_c6_lo0_3_scanout[24];
assign ff_l2d_decc_out_c6_hi0_3_scanin[24]=ff_l2d_decc_out_c6_hi0_1_scanout[24];
assign ff_l2d_decc_out_c6_lo1_1_scanin[24]=ff_l2d_decc_out_c6_hi0_3_scanout[24];
assign ff_l2d_decc_out_c6_lo1_3_scanin[24]=ff_l2d_decc_out_c6_lo1_1_scanout[24];
assign ff_l2d_decc_out_c6_hi1_1_scanin[24]=ff_l2d_decc_out_c6_lo1_3_scanout[24];
assign ff_l2d_decc_out_c6_hi1_3_scanin[24]=ff_l2d_decc_out_c6_hi1_1_scanout[24];
assign ff_l2d_decc_out_c6_lo0_1_scanin[25]=ff_l2d_decc_out_c6_hi1_3_scanout[24];
assign ff_l2d_decc_out_c6_lo0_3_scanin[25]=ff_l2d_decc_out_c6_lo0_1_scanout[25];
assign ff_l2d_decc_out_c6_hi0_1_scanin[25]=ff_l2d_decc_out_c6_lo0_3_scanout[25];
assign ff_l2d_decc_out_c6_hi0_3_scanin[25]=ff_l2d_decc_out_c6_hi0_1_scanout[25];
assign ff_l2d_decc_out_c6_lo1_1_scanin[25]=ff_l2d_decc_out_c6_hi0_3_scanout[25];
assign ff_l2d_decc_out_c6_lo1_3_scanin[25]=ff_l2d_decc_out_c6_lo1_1_scanout[25];
assign ff_l2d_decc_out_c6_hi1_1_scanin[25]=ff_l2d_decc_out_c6_lo1_3_scanout[25];
assign ff_l2d_decc_out_c6_hi1_3_scanin[25]=ff_l2d_decc_out_c6_hi1_1_scanout[25];
assign ff_l2d_decc_out_c6_lo0_1_scanin[26]=ff_l2d_decc_out_c6_hi1_3_scanout[25];
assign ff_l2d_decc_out_c6_lo0_3_scanin[26]=ff_l2d_decc_out_c6_lo0_1_scanout[26];
assign ff_l2d_decc_out_c6_hi0_1_scanin[26]=ff_l2d_decc_out_c6_lo0_3_scanout[26];
assign ff_l2d_decc_out_c6_hi0_3_scanin[26]=ff_l2d_decc_out_c6_hi0_1_scanout[26];
assign ff_l2d_decc_out_c6_lo1_1_scanin[26]=ff_l2d_decc_out_c6_hi0_3_scanout[26];
assign ff_l2d_decc_out_c6_lo1_3_scanin[26]=ff_l2d_decc_out_c6_lo1_1_scanout[26];
assign ff_l2d_decc_out_c6_hi1_1_scanin[26]=ff_l2d_decc_out_c6_lo1_3_scanout[26];
assign ff_l2d_decc_out_c6_hi1_3_scanin[26]=ff_l2d_decc_out_c6_hi1_1_scanout[26];
assign ff_l2d_decc_out_c6_lo0_1_scanin[27]=ff_l2d_decc_out_c6_hi1_3_scanout[26];
assign ff_l2d_decc_out_c6_lo0_3_scanin[27]=ff_l2d_decc_out_c6_lo0_1_scanout[27];
assign ff_l2d_decc_out_c6_hi0_1_scanin[27]=ff_l2d_decc_out_c6_lo0_3_scanout[27];
assign ff_l2d_decc_out_c6_hi0_3_scanin[27]=ff_l2d_decc_out_c6_hi0_1_scanout[27];
assign ff_l2d_decc_out_c6_lo1_1_scanin[27]=ff_l2d_decc_out_c6_hi0_3_scanout[27];
assign ff_l2d_decc_out_c6_lo1_3_scanin[27]=ff_l2d_decc_out_c6_lo1_1_scanout[27];
assign ff_l2d_decc_out_c6_hi1_1_scanin[27]=ff_l2d_decc_out_c6_lo1_3_scanout[27];
assign ff_l2d_decc_out_c6_hi1_3_scanin[27]=ff_l2d_decc_out_c6_hi1_1_scanout[27];
assign ff_l2d_decc_out_c6_lo0_1_scanin[28]=ff_l2d_decc_out_c6_hi1_3_scanout[27];
assign ff_l2d_decc_out_c6_lo0_3_scanin[28]=ff_l2d_decc_out_c6_lo0_1_scanout[28];
assign ff_l2d_decc_out_c6_hi0_1_scanin[28]=ff_l2d_decc_out_c6_lo0_3_scanout[28];
assign ff_l2d_decc_out_c6_hi0_3_scanin[28]=ff_l2d_decc_out_c6_hi0_1_scanout[28];
assign ff_l2d_decc_out_c6_lo1_1_scanin[28]=ff_l2d_decc_out_c6_hi0_3_scanout[28];
assign ff_l2d_decc_out_c6_lo1_3_scanin[28]=ff_l2d_decc_out_c6_lo1_1_scanout[28];
assign ff_l2d_decc_out_c6_hi1_1_scanin[28]=ff_l2d_decc_out_c6_lo1_3_scanout[28];
assign ff_l2d_decc_out_c6_hi1_3_scanin[28]=ff_l2d_decc_out_c6_hi1_1_scanout[28];
assign ff_l2d_decc_out_c6_lo0_1_scanin[29]=ff_l2d_decc_out_c6_hi1_3_scanout[28];
assign ff_l2d_decc_out_c6_lo0_3_scanin[29]=ff_l2d_decc_out_c6_lo0_1_scanout[29];
assign ff_l2d_decc_out_c6_hi0_1_scanin[29]=ff_l2d_decc_out_c6_lo0_3_scanout[29];
assign ff_l2d_decc_out_c6_hi0_3_scanin[29]=ff_l2d_decc_out_c6_hi0_1_scanout[29];
assign ff_l2d_decc_out_c6_lo1_1_scanin[29]=ff_l2d_decc_out_c6_hi0_3_scanout[29];
assign ff_l2d_decc_out_c6_lo1_3_scanin[29]=ff_l2d_decc_out_c6_lo1_1_scanout[29];
assign ff_l2d_decc_out_c6_hi1_1_scanin[29]=ff_l2d_decc_out_c6_lo1_3_scanout[29];
assign ff_l2d_decc_out_c6_hi1_3_scanin[29]=ff_l2d_decc_out_c6_hi1_1_scanout[29];
assign ff_l2d_decc_out_c6_lo0_1_scanin[30]=ff_l2d_decc_out_c6_hi1_3_scanout[29];
assign ff_l2d_decc_out_c6_lo0_3_scanin[30]=ff_l2d_decc_out_c6_lo0_1_scanout[30];
assign ff_l2d_decc_out_c6_hi0_1_scanin[30]=ff_l2d_decc_out_c6_lo0_3_scanout[30];
assign ff_l2d_decc_out_c6_hi0_3_scanin[30]=ff_l2d_decc_out_c6_hi0_1_scanout[30];
assign ff_l2d_decc_out_c6_lo1_1_scanin[30]=ff_l2d_decc_out_c6_hi0_3_scanout[30];
assign ff_l2d_decc_out_c6_lo1_3_scanin[30]=ff_l2d_decc_out_c6_lo1_1_scanout[30];
assign ff_l2d_decc_out_c6_hi1_1_scanin[30]=ff_l2d_decc_out_c6_lo1_3_scanout[30];
assign ff_l2d_decc_out_c6_hi1_3_scanin[30]=ff_l2d_decc_out_c6_hi1_1_scanout[30];
assign ff_l2d_decc_out_c6_lo0_1_scanin[31]=ff_l2d_decc_out_c6_hi1_3_scanout[30];
assign ff_l2d_decc_out_c6_lo0_3_scanin[31]=ff_l2d_decc_out_c6_lo0_1_scanout[31];
assign ff_l2d_decc_out_c6_hi0_1_scanin[31]=ff_l2d_decc_out_c6_lo0_3_scanout[31];
assign ff_l2d_decc_out_c6_hi0_3_scanin[31]=ff_l2d_decc_out_c6_hi0_1_scanout[31];
assign ff_l2d_decc_out_c6_lo1_1_scanin[31]=ff_l2d_decc_out_c6_hi0_3_scanout[31];
assign ff_l2d_decc_out_c6_lo1_3_scanin[31]=ff_l2d_decc_out_c6_lo1_1_scanout[31];
assign ff_l2d_decc_out_c6_hi1_1_scanin[31]=ff_l2d_decc_out_c6_lo1_3_scanout[31];
assign ff_l2d_decc_out_c6_hi1_3_scanin[31]=ff_l2d_decc_out_c6_hi1_1_scanout[31];
assign ff_l2d_decc_out_c6_lo0_1_scanin[32]=ff_l2d_decc_out_c6_hi1_3_scanout[31];
assign ff_l2d_decc_out_c6_lo0_3_scanin[32]=ff_l2d_decc_out_c6_lo0_1_scanout[32];
assign ff_l2d_decc_out_c6_hi0_1_scanin[32]=ff_l2d_decc_out_c6_lo0_3_scanout[32];
assign ff_l2d_decc_out_c6_hi0_3_scanin[32]=ff_l2d_decc_out_c6_hi0_1_scanout[32];
assign ff_l2d_decc_out_c6_lo1_1_scanin[32]=ff_l2d_decc_out_c6_hi0_3_scanout[32];
assign ff_l2d_decc_out_c6_lo1_3_scanin[32]=ff_l2d_decc_out_c6_lo1_1_scanout[32];
assign ff_l2d_decc_out_c6_hi1_1_scanin[32]=ff_l2d_decc_out_c6_lo1_3_scanout[32];
assign ff_l2d_decc_out_c6_hi1_3_scanin[32]=ff_l2d_decc_out_c6_hi1_1_scanout[32];
assign ff_l2d_decc_out_c6_lo0_1_scanin[33]=ff_l2d_decc_out_c6_hi1_3_scanout[32];
assign ff_l2d_decc_out_c6_lo0_3_scanin[33]=ff_l2d_decc_out_c6_lo0_1_scanout[33];
assign ff_l2d_decc_out_c6_hi0_1_scanin[33]=ff_l2d_decc_out_c6_lo0_3_scanout[33];
assign ff_l2d_decc_out_c6_hi0_3_scanin[33]=ff_l2d_decc_out_c6_hi0_1_scanout[33];
assign ff_l2d_decc_out_c6_lo1_1_scanin[33]=ff_l2d_decc_out_c6_hi0_3_scanout[33];
assign ff_l2d_decc_out_c6_lo1_3_scanin[33]=ff_l2d_decc_out_c6_lo1_1_scanout[33];
assign ff_l2d_decc_out_c6_hi1_1_scanin[33]=ff_l2d_decc_out_c6_lo1_3_scanout[33];
assign ff_l2d_decc_out_c6_hi1_3_scanin[33]=ff_l2d_decc_out_c6_hi1_1_scanout[33];
assign ff_l2d_decc_out_c6_lo0_1_scanin[34]=ff_l2d_decc_out_c6_hi1_3_scanout[33];
assign ff_l2d_decc_out_c6_lo0_3_scanin[34]=ff_l2d_decc_out_c6_lo0_1_scanout[34];
assign ff_l2d_decc_out_c6_hi0_1_scanin[34]=ff_l2d_decc_out_c6_lo0_3_scanout[34];
assign ff_l2d_decc_out_c6_hi0_3_scanin[34]=ff_l2d_decc_out_c6_hi0_1_scanout[34];
assign ff_l2d_decc_out_c6_lo1_1_scanin[34]=ff_l2d_decc_out_c6_hi0_3_scanout[34];
assign ff_l2d_decc_out_c6_lo1_3_scanin[34]=ff_l2d_decc_out_c6_lo1_1_scanout[34];
assign ff_l2d_decc_out_c6_hi1_1_scanin[34]=ff_l2d_decc_out_c6_lo1_3_scanout[34];
assign ff_l2d_decc_out_c6_hi1_3_scanin[34]=ff_l2d_decc_out_c6_hi1_1_scanout[34];
assign ff_l2d_decc_out_c6_lo0_1_scanin[35]=ff_l2d_decc_out_c6_hi1_3_scanout[34];
assign ff_l2d_decc_out_c6_lo0_3_scanin[35]=ff_l2d_decc_out_c6_lo0_1_scanout[35];
assign ff_l2d_decc_out_c6_hi0_1_scanin[35]=ff_l2d_decc_out_c6_lo0_3_scanout[35];
assign ff_l2d_decc_out_c6_hi0_3_scanin[35]=ff_l2d_decc_out_c6_hi0_1_scanout[35];
assign ff_l2d_decc_out_c6_lo1_1_scanin[35]=ff_l2d_decc_out_c6_hi0_3_scanout[35];
assign ff_l2d_decc_out_c6_lo1_3_scanin[35]=ff_l2d_decc_out_c6_lo1_1_scanout[35];
assign ff_l2d_decc_out_c6_hi1_1_scanin[35]=ff_l2d_decc_out_c6_lo1_3_scanout[35];
assign ff_l2d_decc_out_c6_hi1_3_scanin[35]=ff_l2d_decc_out_c6_hi1_1_scanout[35];
assign ff_l2d_decc_out_c6_lo0_1_scanin[36]=ff_l2d_decc_out_c6_hi1_3_scanout[35];
assign ff_l2d_decc_out_c6_lo0_3_scanin[36]=ff_l2d_decc_out_c6_lo0_1_scanout[36];
assign ff_l2d_decc_out_c6_hi0_1_scanin[36]=ff_l2d_decc_out_c6_lo0_3_scanout[36];
assign ff_l2d_decc_out_c6_hi0_3_scanin[36]=ff_l2d_decc_out_c6_hi0_1_scanout[36];
assign ff_l2d_decc_out_c6_lo1_1_scanin[36]=ff_l2d_decc_out_c6_hi0_3_scanout[36];
assign ff_l2d_decc_out_c6_lo1_3_scanin[36]=ff_l2d_decc_out_c6_lo1_1_scanout[36];
assign ff_l2d_decc_out_c6_hi1_1_scanin[36]=ff_l2d_decc_out_c6_lo1_3_scanout[36];
assign ff_l2d_decc_out_c6_hi1_3_scanin[36]=ff_l2d_decc_out_c6_hi1_1_scanout[36];
assign ff_l2d_decc_out_c6_lo0_1_scanin[37]=ff_l2d_decc_out_c6_hi1_3_scanout[36];
assign ff_l2d_decc_out_c6_lo0_3_scanin[37]=ff_l2d_decc_out_c6_lo0_1_scanout[37];
assign ff_l2d_decc_out_c6_hi0_1_scanin[37]=ff_l2d_decc_out_c6_lo0_3_scanout[37];
assign ff_l2d_decc_out_c6_hi0_3_scanin[37]=ff_l2d_decc_out_c6_hi0_1_scanout[37];
assign ff_l2d_decc_out_c6_lo1_1_scanin[37]=ff_l2d_decc_out_c6_hi0_3_scanout[37];
assign ff_l2d_decc_out_c6_lo1_3_scanin[37]=ff_l2d_decc_out_c6_lo1_1_scanout[37];
assign ff_l2d_decc_out_c6_hi1_1_scanin[37]=ff_l2d_decc_out_c6_lo1_3_scanout[37];
assign ff_l2d_decc_out_c6_hi1_3_scanin[37]=ff_l2d_decc_out_c6_hi1_1_scanout[37];
assign ff_l2d_decc_out_c6_lo0_1_scanin[38]=ff_l2d_decc_out_c6_hi1_3_scanout[37];
assign ff_l2d_decc_out_c6_lo0_3_scanin[38]=ff_l2d_decc_out_c6_lo0_1_scanout[38];
assign ff_l2d_decc_out_c6_hi0_1_scanin[38]=ff_l2d_decc_out_c6_lo0_3_scanout[38];
assign ff_l2d_decc_out_c6_hi0_3_scanin[38]=ff_l2d_decc_out_c6_hi0_1_scanout[38];
assign ff_l2d_decc_out_c6_lo1_1_scanin[38]=ff_l2d_decc_out_c6_hi0_3_scanout[38];
assign ff_l2d_decc_out_c6_lo1_3_scanin[38]=ff_l2d_decc_out_c6_lo1_1_scanout[38];
assign ff_l2d_decc_out_c6_hi1_1_scanin[38]=ff_l2d_decc_out_c6_lo1_3_scanout[38];
assign ff_l2d_decc_out_c6_hi1_3_scanin[38]=ff_l2d_decc_out_c6_hi1_1_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[0]=ff_l2d_decc_out_c6_hi1_3_scanout[38];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[1]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[1]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[1]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[1]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[2]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[2]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[2]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[2]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[3]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[3]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[3]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[3]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[4]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[4]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[4]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[9]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[9]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[9]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[8]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[8]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[8]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[8]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[7]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[7]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[7]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[7]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[6]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[6]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[6]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[6]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[5]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[5]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[5]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[5]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[4]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[5];
assign ff_cache_col_offset_c5_001_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[4];
assign ff_cache_col_offset_c5_001_scanin[2]=ff_cache_col_offset_c5_001_scanout[0];
assign ff_cache_col_offset_c4_001_scanin[0]=ff_cache_col_offset_c5_001_scanout[2];
assign ff_cache_col_offset_c4_001_scanin[2]=ff_cache_col_offset_c4_001_scanout[0];
assign ff_cache_col_offset_c4_tog_001_scanin[0]=ff_cache_col_offset_c4_001_scanout[2];
assign ff_cache_cache_rd_wr_c5_00_scanin=ff_cache_col_offset_c4_tog_001_scanout[0];
assign ff_cache_col_offset_c5_001_scanin[1]=ff_cache_cache_rd_wr_c5_00_scanout;
assign ff_cache_col_offset_c5_001_scanin[3]=ff_cache_col_offset_c5_001_scanout[1];
assign ff_cache_col_offset_c4_001_scanin[1]=ff_cache_col_offset_c5_001_scanout[3];
assign ff_cache_col_offset_c4_001_scanin[3]=ff_cache_col_offset_c4_001_scanout[1];
assign ff_cache_col_offset_c4_tog_001_scanin[1]=ff_cache_col_offset_c4_001_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[19]=ff_cache_col_offset_c4_tog_001_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[19]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[18]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[18]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[18]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[18]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[17]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[17]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[17]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[17]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[16]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[16]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[16]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[16]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[15]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[15]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[15]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[15]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[14]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[9]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[10]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[10]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[10]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[10]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[11]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[11]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[11]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[11]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[12]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[12]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[12]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[12]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[13]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[13]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[13]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_hi1_3_scanin[13]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_lo0_3_scanin[14]=ff_l2b_l2d_fbdecc_c52_hi1_3_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_hi0_3_scanin[14]=ff_l2b_l2d_fbdecc_c52_lo0_3_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo1_3_scanin[14]=ff_l2b_l2d_fbdecc_c52_hi0_3_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[19]=ff_l2b_l2d_fbdecc_c52_lo1_3_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[19]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[18]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[19];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[18]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[18]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[18]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[17]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[18];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[17]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[17]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[17]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[16]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[17];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[16]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[16]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[16]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[15]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[16];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[15]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[15]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[15]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[14]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[15];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[9]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[10]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[10]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[10]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[10]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[11]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[10];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[11]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[11]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[11]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[12]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[11];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[12]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[12]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[12]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[13]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[12];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[13]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[13]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[13]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[14]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[13];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[14]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[14]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[14];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[0]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[1]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[0];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[1]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[1]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[1]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[2]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[1];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[2]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[2]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[2]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[3]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[2];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[3]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[3]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[3]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[4]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[3];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[4]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[4]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[9]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[4];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[9]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[9]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[8]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[9];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[8]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[8]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[8]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[7]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[8];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[7]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[7]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[7]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[6]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[7];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[6]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[6]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[6]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[5]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[6];
assign ff_l2b_l2d_fbdecc_c52_lo1_1_scanin[5]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_hi0_1_scanin[5]=ff_l2b_l2d_fbdecc_c52_lo1_1_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_lo0_1_scanin[5]=ff_l2b_l2d_fbdecc_c52_hi0_1_scanout[5];
assign ff_l2b_l2d_fbdecc_c52_hi1_1_scanin[4]=ff_l2b_l2d_fbdecc_c52_lo0_1_scanout[5];
assign ff_l2d_decc_out_c6_lo0_1_scanin[0]=ff_l2b_l2d_fbdecc_c52_hi1_1_scanout[4];
assign ff_l2d_decc_out_c6_lo0_3_scanin[0]=ff_l2d_decc_out_c6_lo0_1_scanout[0];
assign ff_l2d_decc_out_c6_hi0_1_scanin[0]=ff_l2d_decc_out_c6_lo0_3_scanout[0];
assign ff_l2d_decc_out_c6_hi0_3_scanin[0]=ff_l2d_decc_out_c6_hi0_1_scanout[0];
assign ff_l2d_decc_out_c6_lo1_1_scanin[0]=ff_l2d_decc_out_c6_hi0_3_scanout[0];
assign ff_l2d_decc_out_c6_lo1_3_scanin[0]=ff_l2d_decc_out_c6_lo1_1_scanout[0];
assign ff_l2d_decc_out_c6_hi1_1_scanin[0]=ff_l2d_decc_out_c6_lo1_3_scanout[0];
assign ff_l2d_decc_out_c6_hi1_3_scanin[0]=ff_l2d_decc_out_c6_hi1_1_scanout[0];
assign ff_l2d_decc_out_c6_lo0_1_scanin[1]=ff_l2d_decc_out_c6_hi1_3_scanout[0];
assign ff_l2d_decc_out_c6_lo0_3_scanin[1]=ff_l2d_decc_out_c6_lo0_1_scanout[1];
assign ff_l2d_decc_out_c6_hi0_1_scanin[1]=ff_l2d_decc_out_c6_lo0_3_scanout[1];
assign ff_l2d_decc_out_c6_hi0_3_scanin[1]=ff_l2d_decc_out_c6_hi0_1_scanout[1];
assign ff_l2d_decc_out_c6_lo1_1_scanin[1]=ff_l2d_decc_out_c6_hi0_3_scanout[1];
assign ff_l2d_decc_out_c6_lo1_3_scanin[1]=ff_l2d_decc_out_c6_lo1_1_scanout[1];
assign ff_l2d_decc_out_c6_hi1_1_scanin[1]=ff_l2d_decc_out_c6_lo1_3_scanout[1];
assign ff_l2d_decc_out_c6_hi1_3_scanin[1]=ff_l2d_decc_out_c6_hi1_1_scanout[1];
assign ff_l2d_decc_out_c6_lo0_1_scanin[2]=ff_l2d_decc_out_c6_hi1_3_scanout[1];
assign ff_l2d_decc_out_c6_lo0_3_scanin[2]=ff_l2d_decc_out_c6_lo0_1_scanout[2];
assign ff_l2d_decc_out_c6_hi0_1_scanin[2]=ff_l2d_decc_out_c6_lo0_3_scanout[2];
assign ff_l2d_decc_out_c6_hi0_3_scanin[2]=ff_l2d_decc_out_c6_hi0_1_scanout[2];
assign ff_l2d_decc_out_c6_lo1_1_scanin[2]=ff_l2d_decc_out_c6_hi0_3_scanout[2];
assign ff_l2d_decc_out_c6_lo1_3_scanin[2]=ff_l2d_decc_out_c6_lo1_1_scanout[2];
assign ff_l2d_decc_out_c6_hi1_1_scanin[2]=ff_l2d_decc_out_c6_lo1_3_scanout[2];
assign ff_l2d_decc_out_c6_hi1_3_scanin[2]=ff_l2d_decc_out_c6_hi1_1_scanout[2];
assign ff_l2d_decc_out_c6_lo0_1_scanin[3]=ff_l2d_decc_out_c6_hi1_3_scanout[2];
assign ff_l2d_decc_out_c6_lo0_3_scanin[3]=ff_l2d_decc_out_c6_lo0_1_scanout[3];
assign ff_l2d_decc_out_c6_hi0_1_scanin[3]=ff_l2d_decc_out_c6_lo0_3_scanout[3];
assign ff_l2d_decc_out_c6_hi0_3_scanin[3]=ff_l2d_decc_out_c6_hi0_1_scanout[3];
assign ff_l2d_decc_out_c6_lo1_1_scanin[3]=ff_l2d_decc_out_c6_hi0_3_scanout[3];
assign ff_l2d_decc_out_c6_lo1_3_scanin[3]=ff_l2d_decc_out_c6_lo1_1_scanout[3];
assign ff_l2d_decc_out_c6_hi1_1_scanin[3]=ff_l2d_decc_out_c6_lo1_3_scanout[3];
assign ff_l2d_decc_out_c6_hi1_3_scanin[3]=ff_l2d_decc_out_c6_hi1_1_scanout[3];
assign ff_l2d_decc_out_c6_lo0_1_scanin[4]=ff_l2d_decc_out_c6_hi1_3_scanout[3];
assign ff_l2d_decc_out_c6_lo0_3_scanin[4]=ff_l2d_decc_out_c6_lo0_1_scanout[4];
assign ff_l2d_decc_out_c6_hi0_1_scanin[4]=ff_l2d_decc_out_c6_lo0_3_scanout[4];
assign ff_l2d_decc_out_c6_hi0_3_scanin[4]=ff_l2d_decc_out_c6_hi0_1_scanout[4];
assign ff_l2d_decc_out_c6_lo1_1_scanin[4]=ff_l2d_decc_out_c6_hi0_3_scanout[4];
assign ff_l2d_decc_out_c6_lo1_3_scanin[4]=ff_l2d_decc_out_c6_lo1_1_scanout[4];
assign ff_l2d_decc_out_c6_hi1_1_scanin[4]=ff_l2d_decc_out_c6_lo1_3_scanout[4];
assign ff_l2d_decc_out_c6_hi1_3_scanin[4]=ff_l2d_decc_out_c6_hi1_1_scanout[4];
assign ff_l2d_decc_out_c6_lo0_1_scanin[5]=ff_l2d_decc_out_c6_hi1_3_scanout[4];
assign ff_l2d_decc_out_c6_lo0_3_scanin[5]=ff_l2d_decc_out_c6_lo0_1_scanout[5];
assign ff_l2d_decc_out_c6_hi0_1_scanin[5]=ff_l2d_decc_out_c6_lo0_3_scanout[5];
assign ff_l2d_decc_out_c6_hi0_3_scanin[5]=ff_l2d_decc_out_c6_hi0_1_scanout[5];
assign ff_l2d_decc_out_c6_lo1_1_scanin[5]=ff_l2d_decc_out_c6_hi0_3_scanout[5];
assign ff_l2d_decc_out_c6_lo1_3_scanin[5]=ff_l2d_decc_out_c6_lo1_1_scanout[5];
assign ff_l2d_decc_out_c6_hi1_1_scanin[5]=ff_l2d_decc_out_c6_lo1_3_scanout[5];
assign ff_l2d_decc_out_c6_hi1_3_scanin[5]=ff_l2d_decc_out_c6_hi1_1_scanout[5];
assign ff_l2d_decc_out_c6_lo0_1_scanin[6]=ff_l2d_decc_out_c6_hi1_3_scanout[5];
assign ff_l2d_decc_out_c6_lo0_3_scanin[6]=ff_l2d_decc_out_c6_lo0_1_scanout[6];
assign ff_l2d_decc_out_c6_hi0_1_scanin[6]=ff_l2d_decc_out_c6_lo0_3_scanout[6];
assign ff_l2d_decc_out_c6_hi0_3_scanin[6]=ff_l2d_decc_out_c6_hi0_1_scanout[6];
assign ff_l2d_decc_out_c6_lo1_1_scanin[6]=ff_l2d_decc_out_c6_hi0_3_scanout[6];
assign ff_l2d_decc_out_c6_lo1_3_scanin[6]=ff_l2d_decc_out_c6_lo1_1_scanout[6];
assign ff_l2d_decc_out_c6_hi1_1_scanin[6]=ff_l2d_decc_out_c6_lo1_3_scanout[6];
assign ff_l2d_decc_out_c6_hi1_3_scanin[6]=ff_l2d_decc_out_c6_hi1_1_scanout[6];
assign ff_l2d_decc_out_c6_lo0_1_scanin[7]=ff_l2d_decc_out_c6_hi1_3_scanout[6];
assign ff_l2d_decc_out_c6_lo0_3_scanin[7]=ff_l2d_decc_out_c6_lo0_1_scanout[7];
assign ff_l2d_decc_out_c6_hi0_1_scanin[7]=ff_l2d_decc_out_c6_lo0_3_scanout[7];
assign ff_l2d_decc_out_c6_hi0_3_scanin[7]=ff_l2d_decc_out_c6_hi0_1_scanout[7];
assign ff_l2d_decc_out_c6_lo1_1_scanin[7]=ff_l2d_decc_out_c6_hi0_3_scanout[7];
assign ff_l2d_decc_out_c6_lo1_3_scanin[7]=ff_l2d_decc_out_c6_lo1_1_scanout[7];
assign ff_l2d_decc_out_c6_hi1_1_scanin[7]=ff_l2d_decc_out_c6_lo1_3_scanout[7];
assign ff_l2d_decc_out_c6_hi1_3_scanin[7]=ff_l2d_decc_out_c6_hi1_1_scanout[7];
assign ff_l2d_decc_out_c6_lo0_1_scanin[8]=ff_l2d_decc_out_c6_hi1_3_scanout[7];
assign ff_l2d_decc_out_c6_lo0_3_scanin[8]=ff_l2d_decc_out_c6_lo0_1_scanout[8];
assign ff_l2d_decc_out_c6_hi0_1_scanin[8]=ff_l2d_decc_out_c6_lo0_3_scanout[8];
assign ff_l2d_decc_out_c6_hi0_3_scanin[8]=ff_l2d_decc_out_c6_hi0_1_scanout[8];
assign ff_l2d_decc_out_c6_lo1_1_scanin[8]=ff_l2d_decc_out_c6_hi0_3_scanout[8];
assign ff_l2d_decc_out_c6_lo1_3_scanin[8]=ff_l2d_decc_out_c6_lo1_1_scanout[8];
assign ff_l2d_decc_out_c6_hi1_1_scanin[8]=ff_l2d_decc_out_c6_lo1_3_scanout[8];
assign ff_l2d_decc_out_c6_hi1_3_scanin[8]=ff_l2d_decc_out_c6_hi1_1_scanout[8];
assign ff_l2d_decc_out_c6_lo0_1_scanin[9]=ff_l2d_decc_out_c6_hi1_3_scanout[8];
assign ff_l2d_decc_out_c6_lo0_3_scanin[9]=ff_l2d_decc_out_c6_lo0_1_scanout[9];
assign ff_l2d_decc_out_c6_hi0_1_scanin[9]=ff_l2d_decc_out_c6_lo0_3_scanout[9];
assign ff_l2d_decc_out_c6_hi0_3_scanin[9]=ff_l2d_decc_out_c6_hi0_1_scanout[9];
assign ff_l2d_decc_out_c6_lo1_1_scanin[9]=ff_l2d_decc_out_c6_hi0_3_scanout[9];
assign ff_l2d_decc_out_c6_lo1_3_scanin[9]=ff_l2d_decc_out_c6_lo1_1_scanout[9];
assign ff_l2d_decc_out_c6_hi1_1_scanin[9]=ff_l2d_decc_out_c6_lo1_3_scanout[9];
assign ff_l2d_decc_out_c6_hi1_3_scanin[9]=ff_l2d_decc_out_c6_hi1_1_scanout[9];
assign ff_l2d_decc_out_c6_lo0_1_scanin[10]=ff_l2d_decc_out_c6_hi1_3_scanout[9];
assign ff_l2d_decc_out_c6_lo0_3_scanin[10]=ff_l2d_decc_out_c6_lo0_1_scanout[10];
assign ff_l2d_decc_out_c6_hi0_1_scanin[10]=ff_l2d_decc_out_c6_lo0_3_scanout[10];
assign ff_l2d_decc_out_c6_hi0_3_scanin[10]=ff_l2d_decc_out_c6_hi0_1_scanout[10];
assign ff_l2d_decc_out_c6_lo1_1_scanin[10]=ff_l2d_decc_out_c6_hi0_3_scanout[10];
assign ff_l2d_decc_out_c6_lo1_3_scanin[10]=ff_l2d_decc_out_c6_lo1_1_scanout[10];
assign ff_l2d_decc_out_c6_hi1_1_scanin[10]=ff_l2d_decc_out_c6_lo1_3_scanout[10];
assign ff_l2d_decc_out_c6_hi1_3_scanin[10]=ff_l2d_decc_out_c6_hi1_1_scanout[10];
assign ff_l2d_decc_out_c6_lo0_1_scanin[11]=ff_l2d_decc_out_c6_hi1_3_scanout[10];
assign ff_l2d_decc_out_c6_lo0_3_scanin[11]=ff_l2d_decc_out_c6_lo0_1_scanout[11];
assign ff_l2d_decc_out_c6_hi0_1_scanin[11]=ff_l2d_decc_out_c6_lo0_3_scanout[11];
assign ff_l2d_decc_out_c6_hi0_3_scanin[11]=ff_l2d_decc_out_c6_hi0_1_scanout[11];
assign ff_l2d_decc_out_c6_lo1_1_scanin[11]=ff_l2d_decc_out_c6_hi0_3_scanout[11];
assign ff_l2d_decc_out_c6_lo1_3_scanin[11]=ff_l2d_decc_out_c6_lo1_1_scanout[11];
assign ff_l2d_decc_out_c6_hi1_1_scanin[11]=ff_l2d_decc_out_c6_lo1_3_scanout[11];
assign ff_l2d_decc_out_c6_hi1_3_scanin[11]=ff_l2d_decc_out_c6_hi1_1_scanout[11];
assign ff_l2d_decc_out_c6_lo0_1_scanin[12]=ff_l2d_decc_out_c6_hi1_3_scanout[11];
assign ff_l2d_decc_out_c6_lo0_3_scanin[12]=ff_l2d_decc_out_c6_lo0_1_scanout[12];
assign ff_l2d_decc_out_c6_hi0_1_scanin[12]=ff_l2d_decc_out_c6_lo0_3_scanout[12];
assign ff_l2d_decc_out_c6_hi0_3_scanin[12]=ff_l2d_decc_out_c6_hi0_1_scanout[12];
assign ff_l2d_decc_out_c6_lo1_1_scanin[12]=ff_l2d_decc_out_c6_hi0_3_scanout[12];
assign ff_l2d_decc_out_c6_lo1_3_scanin[12]=ff_l2d_decc_out_c6_lo1_1_scanout[12];
assign ff_l2d_decc_out_c6_hi1_1_scanin[12]=ff_l2d_decc_out_c6_lo1_3_scanout[12];
assign ff_l2d_decc_out_c6_hi1_3_scanin[12]=ff_l2d_decc_out_c6_hi1_1_scanout[12];
assign ff_l2d_decc_out_c6_lo0_1_scanin[13]=ff_l2d_decc_out_c6_hi1_3_scanout[12];
assign ff_l2d_decc_out_c6_lo0_3_scanin[13]=ff_l2d_decc_out_c6_lo0_1_scanout[13];
assign ff_l2d_decc_out_c6_hi0_1_scanin[13]=ff_l2d_decc_out_c6_lo0_3_scanout[13];
assign ff_l2d_decc_out_c6_hi0_3_scanin[13]=ff_l2d_decc_out_c6_hi0_1_scanout[13];
assign ff_l2d_decc_out_c6_lo1_1_scanin[13]=ff_l2d_decc_out_c6_hi0_3_scanout[13];
assign ff_l2d_decc_out_c6_lo1_3_scanin[13]=ff_l2d_decc_out_c6_lo1_1_scanout[13];
assign ff_l2d_decc_out_c6_hi1_1_scanin[13]=ff_l2d_decc_out_c6_lo1_3_scanout[13];
assign ff_l2d_decc_out_c6_hi1_3_scanin[13]=ff_l2d_decc_out_c6_hi1_1_scanout[13];
assign ff_l2d_decc_out_c6_lo0_1_scanin[14]=ff_l2d_decc_out_c6_hi1_3_scanout[13];
assign ff_l2d_decc_out_c6_lo0_3_scanin[14]=ff_l2d_decc_out_c6_lo0_1_scanout[14];
assign ff_l2d_decc_out_c6_hi0_1_scanin[14]=ff_l2d_decc_out_c6_lo0_3_scanout[14];
assign ff_l2d_decc_out_c6_hi0_3_scanin[14]=ff_l2d_decc_out_c6_hi0_1_scanout[14];
assign ff_l2d_decc_out_c6_lo1_1_scanin[14]=ff_l2d_decc_out_c6_hi0_3_scanout[14];
assign ff_l2d_decc_out_c6_lo1_3_scanin[14]=ff_l2d_decc_out_c6_lo1_1_scanout[14];
assign ff_l2d_decc_out_c6_hi1_1_scanin[14]=ff_l2d_decc_out_c6_lo1_3_scanout[14];
assign ff_l2d_decc_out_c6_hi1_3_scanin[14]=ff_l2d_decc_out_c6_hi1_1_scanout[14];
assign ff_l2d_decc_out_c6_lo0_1_scanin[15]=ff_l2d_decc_out_c6_hi1_3_scanout[14];
assign ff_l2d_decc_out_c6_lo0_3_scanin[15]=ff_l2d_decc_out_c6_lo0_1_scanout[15];
assign ff_l2d_decc_out_c6_hi0_1_scanin[15]=ff_l2d_decc_out_c6_lo0_3_scanout[15];
assign ff_l2d_decc_out_c6_hi0_3_scanin[15]=ff_l2d_decc_out_c6_hi0_1_scanout[15];
assign ff_l2d_decc_out_c6_lo1_1_scanin[15]=ff_l2d_decc_out_c6_hi0_3_scanout[15];
assign ff_l2d_decc_out_c6_lo1_3_scanin[15]=ff_l2d_decc_out_c6_lo1_1_scanout[15];
assign ff_l2d_decc_out_c6_hi1_1_scanin[15]=ff_l2d_decc_out_c6_lo1_3_scanout[15];
assign ff_l2d_decc_out_c6_hi1_3_scanin[15]=ff_l2d_decc_out_c6_hi1_1_scanout[15];
assign ff_l2d_decc_out_c6_lo0_1_scanin[16]=ff_l2d_decc_out_c6_hi1_3_scanout[15];
assign ff_l2d_decc_out_c6_lo0_3_scanin[16]=ff_l2d_decc_out_c6_lo0_1_scanout[16];
assign ff_l2d_decc_out_c6_hi0_1_scanin[16]=ff_l2d_decc_out_c6_lo0_3_scanout[16];
assign ff_l2d_decc_out_c6_hi0_3_scanin[16]=ff_l2d_decc_out_c6_hi0_1_scanout[16];
assign ff_l2d_decc_out_c6_lo1_1_scanin[16]=ff_l2d_decc_out_c6_hi0_3_scanout[16];
assign ff_l2d_decc_out_c6_lo1_3_scanin[16]=ff_l2d_decc_out_c6_lo1_1_scanout[16];
assign ff_l2d_decc_out_c6_hi1_1_scanin[16]=ff_l2d_decc_out_c6_lo1_3_scanout[16];
assign ff_l2d_decc_out_c6_hi1_3_scanin[16]=ff_l2d_decc_out_c6_hi1_1_scanout[16];
assign ff_l2d_decc_out_c6_lo0_1_scanin[17]=ff_l2d_decc_out_c6_hi1_3_scanout[16];
assign ff_l2d_decc_out_c6_lo0_3_scanin[17]=ff_l2d_decc_out_c6_lo0_1_scanout[17];
assign ff_l2d_decc_out_c6_hi0_1_scanin[17]=ff_l2d_decc_out_c6_lo0_3_scanout[17];
assign ff_l2d_decc_out_c6_hi0_3_scanin[17]=ff_l2d_decc_out_c6_hi0_1_scanout[17];
assign ff_l2d_decc_out_c6_lo1_1_scanin[17]=ff_l2d_decc_out_c6_hi0_3_scanout[17];
assign ff_l2d_decc_out_c6_lo1_3_scanin[17]=ff_l2d_decc_out_c6_lo1_1_scanout[17];
assign ff_l2d_decc_out_c6_hi1_1_scanin[17]=ff_l2d_decc_out_c6_lo1_3_scanout[17];
assign ff_l2d_decc_out_c6_hi1_3_scanin[17]=ff_l2d_decc_out_c6_hi1_1_scanout[17];
assign ff_l2d_decc_out_c6_lo0_1_scanin[18]=ff_l2d_decc_out_c6_hi1_3_scanout[17];
assign ff_l2d_decc_out_c6_lo0_3_scanin[18]=ff_l2d_decc_out_c6_lo0_1_scanout[18];
assign ff_l2d_decc_out_c6_hi0_1_scanin[18]=ff_l2d_decc_out_c6_lo0_3_scanout[18];
assign ff_l2d_decc_out_c6_hi0_3_scanin[18]=ff_l2d_decc_out_c6_hi0_1_scanout[18];
assign ff_l2d_decc_out_c6_lo1_1_scanin[18]=ff_l2d_decc_out_c6_hi0_3_scanout[18];
assign ff_l2d_decc_out_c6_lo1_3_scanin[18]=ff_l2d_decc_out_c6_lo1_1_scanout[18];
assign ff_l2d_decc_out_c6_hi1_1_scanin[18]=ff_l2d_decc_out_c6_lo1_3_scanout[18];
assign ff_l2d_decc_out_c6_hi1_3_scanin[18]=ff_l2d_decc_out_c6_hi1_1_scanout[18];
assign ff_l2d_decc_out_c6_lo0_1_scanin[19]=ff_l2d_decc_out_c6_hi1_3_scanout[18];
assign ff_l2d_decc_out_c6_lo0_3_scanin[19]=ff_l2d_decc_out_c6_lo0_1_scanout[19];
assign ff_l2d_decc_out_c6_hi0_1_scanin[19]=ff_l2d_decc_out_c6_lo0_3_scanout[19];
assign ff_l2d_decc_out_c6_hi0_3_scanin[19]=ff_l2d_decc_out_c6_hi0_1_scanout[19];
assign scan_out=ff_l2d_decc_out_c6_hi0_3_scanout[19];
// fixscan end
endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_9 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [8:0] fdin;

  input [8:0] din;
  input l1clk;
  input [8:0] scan_in;


  input siclk;
  input soclk;

  output [8:0] dout;
  output [8:0] scan_out;
assign fdin[8:0] = din[8:0];


dff #(9)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[8:0]),
.si(scan_in[8:0]),
.so(scan_out[8:0]),
.q(dout[8:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_4 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [3:0] fdin;

  input [3:0] din;
  input l1clk;
  input [3:0] scan_in;


  input siclk;
  input soclk;

  output [3:0] dout;
  output [3:0] scan_out;
assign fdin[3:0] = din[3:0];


dff #(4)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[3:0]),
.si(scan_in[3:0]),
.so(scan_out[3:0]),
.q(dout[3:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_2 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [1:0] fdin;

  input [1:0] din;
  input l1clk;
  input [1:0] scan_in;


  input siclk;
  input soclk;

  output [1:0] dout;
  output [1:0] scan_out;
assign fdin[1:0] = din[1:0];


dff #(2)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[1:0]),
.si(scan_in[1:0]),
.so(scan_out[1:0]),
.q(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_l2d_sp_512kb_cust_and_macro__ports_4__width_1 (
  din0, 
  din1, 
  din2, 
  din3, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  input [0:0] din3;
  output [0:0] dout;


and4 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.in3(din3[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module n2_l2d_sp_512kb_cust_inv_macro__width_1 (
  din, 
  dout);
  input [0:0] din;
  output [0:0] dout;


inv #(1)  d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);


endmodule


//
//   invert macro
//
//


module n2_l2d_sp_512kb_cust_inv_macro__width_8 (
  din, 
  dout);
  input [7:0] din;
  output [7:0] dout;


inv #(8)  d0_0 (
.in(din[7:0]),
.out(dout[7:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module n2_l2d_sp_512kb_cust_or_macro__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


or2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


//
//   invert macro
//
//


module n2_l2d_sp_512kb_cust_inv_macro__width_4 (
  din, 
  dout);
  input [3:0] din;
  output [3:0] dout;


inv #(4)  d0_0 (
.in(din[3:0]),
.out(dout[3:0])
);


endmodule


//  
//   or macro for ports = 2,3
//
//


module n2_l2d_sp_512kb_cust_or_macro__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


or2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_l2d_sp_512kb_cust_and_macro__width_2 (
  din0, 
  din1, 
  dout);
  input [1:0] din0;
  input [1:0] din1;
  output [1:0] dout;


and2 #(2)  d0_0 (
.in0(din0[1:0]),
.in1(din1[1:0]),
.out(dout[1:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_l2d_sp_512kb_cust_and_macro__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output [3:0] dout;


and2 #(4)  d0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout[3:0])
);


endmodule


//  
//   and macro for ports = 2,3,4
//
//


module n2_l2d_sp_512kb_cust_and_macro__width_8 (
  din0, 
  din1, 
  dout);
  input [7:0] din0;
  input [7:0] din1;
  output [7:0] dout;


and2 #(8)  d0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout[7:0])
);


endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_78 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [77:0] fdin;

  input [77:0] din;
  input l1clk;
  input [77:0] scan_in;


  input siclk;
  input soclk;

  output [77:0] dout;
  output [77:0] scan_out;
assign fdin[77:0] = din[77:0];


dff #(78)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[77:0]),
.si(scan_in[77:0]),
.so(scan_out[77:0]),
.q(dout[77:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_39 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [38:0] din0;
  input sel0;
  input [38:0] din1;
  input sel1;
  output [38:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(39)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[38:0]),
  .in1(din1[38:0]),
.dout(dout[38:0])
);


endmodule


//
//   macro for cl_mc1_tisram_blbi_8x flop
//
//


module n2_l2d_sp_512kb_cust_tisram_blbi_macro__width_624 (
  d_a, 
  l1clk, 
  q_b_l);
input [623:0] d_a;
input l1clk;
output [623:0] q_b_l;


tisram_blb_inv #(624)  d0_0 (
.d(d_a[623:0]),
.l1clk(l1clk),
.latout_l(q_b_l[623:0])
);


//place::generic_place($width,$stack,$left);

endmodule


//
//   macro for cl_mc1_tisram_bla_{4}x flops
//
//


module n2_l2d_sp_512kb_cust_tisram_bla_macro__width_156 (
  d_b, 
  l1clk, 
  q_a);
input [155:0] d_b;
input l1clk;
output [155:0] q_a;


tisram_bla #(156)  d0_0 (
.d_b(d_b[155:0]),
.l1clk(l1clk),
.q_a(q_a[155:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__stack_156c__width_156 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [155:0] din0;
  input sel0;
  input [155:0] din1;
  input sel1;
  output [155:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(156)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[155:0]),
  .in1(din1[155:0]),
.dout(dout[155:0])
);


endmodule


//
//   comparator macro (output is 1 if both inputs are equal; 0 otherwise)
//
//


module n2_l2d_sp_512kb_cust_cmp_macro__width_4 (
  din0, 
  din1, 
  dout);
  input [3:0] din0;
  input [3:0] din1;
  output dout;


cmp #(4)  m0_0 (
.in0(din0[3:0]),
.in1(din1[3:0]),
.out(dout)
);


endmodule


//
//   nor macro for ports = 2,3
//
//


module n2_l2d_sp_512kb_cust_nor_macro__width_1 (
  din0, 
  din1, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  output [0:0] dout;


nor2 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_3__width_10 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  din2, 
  sel2, 
  dout);
wire buffout0;
wire buffout1;
wire buffout2;

  input [9:0] din0;
  input sel0;
  input [9:0] din1;
  input sel1;
  input [9:0] din2;
  input sel2;
  output [9:0] dout;


cl_dp1_muxbuff3_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .in2(sel2),
 .out0(buffout0),
 .out1(buffout1),
 .out2(buffout2)
);
mux3s #(10)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .sel2(buffout2),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
  .in2(din2[9:0]),
.dout(dout[9:0])
);


endmodule


// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_mux_macro__mux_aonpe__ports_2__width_10 (
  din0, 
  sel0, 
  din1, 
  sel1, 
  dout);
wire buffout0;
wire buffout1;

  input [9:0] din0;
  input sel0;
  input [9:0] din1;
  input sel1;
  output [9:0] dout;


cl_dp1_muxbuff2_8x  c0_0 (
 .in0(sel0),
 .in1(sel1),
 .out0(buffout0),
 .out1(buffout1)
);
mux2s #(10)  d0_0 (
  .sel0(buffout0),
  .sel1(buffout1),
  .in0(din0[9:0]),
  .in1(din1[9:0]),
.dout(dout[9:0])
);


endmodule


module n2_l2d_tstmod_cust (
  rd_wr_c3, 
  wayerr_c3, 
  wr_inhibit, 
  coloff_c3, 
  l2clk, 
  scanen, 
  si, 
  siclk, 
  soclk, 
  so, 
  delout20_rgt, 
  delout31_lft, 
  delout31_rgt, 
  delout20_lft) ;
wire not_wayerr_c3;
wire coloff_c3_1_3;
wire coloff_c3_2_0;
wire [1:0] msff_read_c4_scanin;
wire [1:0] msff_read_c4_scanout;
wire msff_buf_out_top_scanin;
wire msff_buf_out_top_scanout;
wire msff_buf_out_bot_scanin;
wire msff_buf_out_bot_scanout;
wire [2:0] msff_buf_out_corse_scanin;
wire [2:0] msff_buf_out_corse_scanout;
wire [2:0] msff_buf_out_fine_scanin;
wire [2:0] msff_buf_out_fine_scanout;
wire wr_inhibit_n;
wire [2:0] ff_buf_out_corse_n;
wire [2:0] ff_buf_out_fine_n;

//-----------------------------------------------------------
//  I/O declarations
//-----------------------------------------------------------
input		rd_wr_c3;	// 
input		wayerr_c3;	// added 9/21/2005
input		wr_inhibit;	// 
//  coloff_c3<3:0>,           
input	[3:0]	coloff_c3;	// 
input		l2clk;		// 
input		scanen;		// 
input		si;		// 
input		siclk;		// 
input		soclk;		// 

output 		so;		// 
output		delout20_rgt;	// 
output 		delout31_lft;	// 
output 		delout31_rgt;	// 
output  	delout20_lft;	// 


//-----------------------------------------------------------------------------
//  Wire/reg declarations
//-----------------------------------------------------------------------------

// connecting between n2_l2d_tstmod_logic  &  n2_l2d_tstmod_delay_cust
wire		l1clk;
wire		tst_bnken31_setb;
wire		tst_bnken02_setb;
wire		tst_bnken31_rstb;
wire		tst_bnken02_rstb;
wire		tst_bnken31_rstb_n;
wire		tst_bnken02_rstb_n;
//wire		so_internal;
wire		tstmod_rst_l;
wire	[5:0]	corse_sel;
wire	[7:0]	fine_sel;


wire	[1:0]	tst_read_c3a;
//wire	[1:0]	tst_read_c3b;
//wire	[3:0]	tst_read_c4;
//wire	[3:0]	tst_so;
wire	[1:0]	tst_so;
wire	[2:0]	tst_so_corse;
wire	[2:0]	tst_so_fine;
wire		tst_so_en0;

wire		ff_buf_out_top;
wire	[2:0]	ff_buf_out_corse;
wire	[2:0]	ff_buf_out_fine;
wire		ff_buf_out_bot;


// start n2_l2d_tstmod_logic


n2_l2d_sp_512kb_cust_l1clkhdr_ctl_macro l1_clk_hdr (
        .l2clk  (l2clk),
        .se     (scanen),
        .l1en   (1'b1),
        .pce_ov (1'b1),
        .stop   (1'b0),
        .l1clk  (l1clk)
        );


//assign tst_read_c3a[1] = (~wayerr_c3  &  rd_wr_c3  &  (coloff_c3[3] | coloff_c3[1]));
//assign tst_read_c3a[0] = (~wayerr_c3  &  rd_wr_c3  &  (coloff_c3[2] | coloff_c3[0]));


n2_l2d_sp_512kb_cust_inv_macro__width_1 inv_wayerr_c3 
	(
	.dout	(not_wayerr_c3),
	.din	(wayerr_c3)
	);

n2_l2d_sp_512kb_cust_or_macro__width_1 or_coloff_c3_1_3 
	(
	.din0	(coloff_c3[1]),
	.din1	(coloff_c3[3]),
	.dout	(coloff_c3_1_3)
	);


n2_l2d_sp_512kb_cust_or_macro__width_1 or_coloff_c3_2_3 
        (
        .din0   (coloff_c3[2]),
        .din1   (coloff_c3[0]),
        .dout   (coloff_c3_2_0)
        );

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_tst_read_c3a_1 
	(
	.dout	(tst_read_c3a[1]),
	.din0	(not_wayerr_c3),
	.din1	(coloff_c3_1_3),
	.din2	(rd_wr_c3)
	);

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_tst_read_c3a_0 
        (
        .dout   (tst_read_c3a[0]),
        .din0   (not_wayerr_c3),
        .din1   (coloff_c3_2_0),
        .din2   (rd_wr_c3)
        );

n2_l2d_sp_512kb_cust_tisram_blb_macro__dmsff_4x__width_1 blb_read_c3_1  
        (
        .l1clk  (l1clk),
        .d_a    (tst_read_c3a[1]),
        .q_b	(tst_bnken31_setb)
        );
n2_l2d_sp_512kb_cust_tisram_blb_macro__dmsff_4x__width_1 blb_read_c3_0  
        (
        .l1clk  (l1clk),
        .d_a    (tst_read_c3a[0]),
        .q_b	(tst_bnken02_setb)
        );

//initialize
//assign tst_read_c4[3:0] = 4'b0;

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_2  msff_read_c4  
        ( 
        .scan_in    (msff_read_c4_scanin[1:0]),
	.scan_out   (msff_read_c4_scanout[1:0]), 
        .din   ( tst_read_c3a[1:0]  &  {~tst_bnken31_rstb_n,~tst_bnken02_rstb_n} ),
        .l1clk ( l1clk ),
        .dout   ( {tst_bnken31_rstb_n,tst_bnken02_rstb_n} ),
  .siclk(siclk),
  .soclk(soclk)
); 


//assign tst_bnken31_rstb = ~tst_bnken31_rstb_n;
//assign tst_bnken02_rstb = ~tst_bnken02_rstb_n;

n2_l2d_sp_512kb_cust_inv_macro__width_1 inv_tst_bnken31_rstb 
	(
	.dout	(tst_bnken31_rstb),
	.din	(tst_bnken31_rstb_n)
	);

n2_l2d_sp_512kb_cust_inv_macro__width_1 inv_tst_bnken02_rstb 
        (
        .dout   (tst_bnken02_rstb),
        .din    (tst_bnken02_rstb_n)
        );

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1  msff_buf_out_top  
        ( 
        .scan_in    (msff_buf_out_top_scanin),
	.scan_out   (msff_buf_out_top_scanout), 
        .din     ( ff_buf_out_top ), 
        .l1clk   ( l1clk ), 
        .dout    ( ff_buf_out_top ),
  .siclk(siclk),
  .soclk(soclk) 
); 

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_1  msff_buf_out_bot  
        ( 
        .scan_in    (msff_buf_out_bot_scanin),
	.scan_out   (msff_buf_out_bot_scanout),  
        .din    ( ff_buf_out_bot ),
        .l1clk  ( l1clk ),
        .dout   ( ff_buf_out_bot ),
  .siclk(siclk),
  .soclk(soclk)
); 


n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_3  msff_buf_out_corse  
        ( 
        .scan_in    (msff_buf_out_corse_scanin[2:0]),
	.scan_out   (msff_buf_out_corse_scanout[2:0]),  
        .din   ( ff_buf_out_corse[2:0] ),
        .l1clk ( l1clk ),
        .dout  ( ff_buf_out_corse[2:0] ),
  .siclk(siclk),
  .soclk(soclk)
); 

n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_3  msff_buf_out_fine  
        ( 
        .scan_in    (msff_buf_out_fine_scanin[2:0]),
	.scan_out   (msff_buf_out_fine_scanout[2:0]),  
        .din   ( ff_buf_out_fine[2:0] ),
        .l1clk ( l1clk ),
        .dout  ( ff_buf_out_fine[2:0] ),
  .siclk(siclk),
  .soclk(soclk)
); 

//assign tstmod_rst_l = ff_buf_out_top  &  ff_buf_out_bot  &  ~wr_inhibit;


n2_l2d_sp_512kb_cust_inv_macro__width_1 inv_wr_inhibit 
	(
	.dout	(wr_inhibit_n),
	.din	(wr_inhibit)
	);

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_tstmod_rst_l 
	(
	.dout	(tstmod_rst_l),
	.din0	(ff_buf_out_top),
	.din1	(ff_buf_out_bot),
	.din2	(wr_inhibit_n)
	);


n2_l2d_sp_512kb_cust_inv_macro__width_3 inv_ff_buf_out_corse_012 
	(
	.dout	(ff_buf_out_corse_n[2:0]),
	.din	(ff_buf_out_corse[2:0])
	);


//decoding: 3-to-8. 2/3, 1/0 swapped
//assign corse_sel[5] = ff_buf_out_corse[2]  &  ~ff_buf_out_corse[1]  &  ~ff_buf_out_corse[0];

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_corse_sel_5 
        (
        .dout   (corse_sel[5]),
        .din0   (ff_buf_out_corse[2]),
        .din1   (ff_buf_out_corse_n[1]),
        .din2   (ff_buf_out_corse_n[0])
        );

//assign corse_sel[4] = ff_buf_out_corse[2]  &  ~ff_buf_out_corse[1]  &  ff_buf_out_corse[0];

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_corse_sel_4 
        (
        .dout   (corse_sel[4]),
        .din0   (ff_buf_out_corse[2]),
        .din1   (ff_buf_out_corse_n[1]),
        .din2   (ff_buf_out_corse[0])
        );

//assign corse_sel[3] = ~ff_buf_out_corse[2]  &  ff_buf_out_corse[1]  &  ~ff_buf_out_corse[0];

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_corse_sel_3 
        (
        .dout   (corse_sel[3]),
        .din0   (ff_buf_out_corse_n[2]),
        .din1   (ff_buf_out_corse[1]),
        .din2   (ff_buf_out_corse_n[0])
        );

//assign corse_sel[2] = ~ff_buf_out_corse[2]  &  ff_buf_out_corse[1]  &  ff_buf_out_corse[0];

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_corse_sel_2 
        (
        .dout   (corse_sel[2]),
        .din0   (ff_buf_out_corse_n[2]),
        .din1   (ff_buf_out_corse[1]),
        .din2   (ff_buf_out_corse[0])
        );

//assign corse_sel[1] = ~ff_buf_out_corse[2]  &  ~ff_buf_out_corse[1]  &  ~ff_buf_out_corse[0];

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_corse_sel_1 
        (
        .dout   (corse_sel[1]),
        .din0   (ff_buf_out_corse_n[2]),
        .din1   (ff_buf_out_corse_n[1]),
        .din2   (ff_buf_out_corse_n[0])
        );

//assign corse_sel[0] = ~ff_buf_out_corse[2]  &  ~ff_buf_out_corse[1]  &  ff_buf_out_corse[0];

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_corse_sel_0 
        (
        .dout   (corse_sel[0]),
        .din0   (ff_buf_out_corse_n[2]),
        .din1   (ff_buf_out_corse_n[1]),
        .din2   (ff_buf_out_corse[0])
        );

n2_l2d_sp_512kb_cust_inv_macro__width_3 inv_ff_buf_out_fine_n 
	(
	.dout	(ff_buf_out_fine_n[2:0]),
	.din	(ff_buf_out_fine[2:0])
	);


//assign fine_sel[7] = ff_buf_out_fine[2]  &  ff_buf_out_fine[1]  &  ~ff_buf_out_fine[0];

n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_fine_sel_7 
        (
        .dout   (fine_sel[7]),
        .din0   (ff_buf_out_fine[2]),
        .din1   (ff_buf_out_fine[1]),
        .din2   (ff_buf_out_fine_n[0])
        );

//assign fine_sel[6] = ff_buf_out_fine[2]  &  ff_buf_out_fine[1]  &  ff_buf_out_fine[0];


n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_fine_sel_6 
        (
        .dout   (fine_sel[6]),
        .din0   (ff_buf_out_fine[2]),
        .din1   (ff_buf_out_fine[1]),
        .din2   (ff_buf_out_fine[0])
        );

//assign fine_sel[5] = ff_buf_out_fine[2]  &  ~ff_buf_out_fine[1]  &  ~ff_buf_out_fine[0];


n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_fine_sel_5 
        (
        .dout   (fine_sel[5]),
        .din0   (ff_buf_out_fine[2]),
        .din1   (ff_buf_out_fine_n[1]),
        .din2   (ff_buf_out_fine_n[0])
        );

//assign fine_sel[4] = ff_buf_out_fine[2]  &  ~ff_buf_out_fine[1]  &  ff_buf_out_fine[0];


n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_fine_sel_4 
        (
        .dout   (fine_sel[4]),
        .din0   (ff_buf_out_fine[2]),
        .din1   (ff_buf_out_fine_n[1]),
        .din2   (ff_buf_out_fine[0])
        );

//assign fine_sel[3] = ~ff_buf_out_fine[2]  &  ff_buf_out_fine[1]  &  ~ff_buf_out_fine[0];


n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_fine_sel_3 
        (
        .dout   (fine_sel[3]),
        .din0   (ff_buf_out_fine_n[2]),
        .din1   (ff_buf_out_fine[1]),
        .din2   (ff_buf_out_fine_n[0])
        );

//assign fine_sel[2] = ~ff_buf_out_fine[2]  &  ff_buf_out_fine[1]  &  ff_buf_out_fine[0];


n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_fine_sel_2 
        (
        .dout   (fine_sel[2]),
        .din0   (ff_buf_out_fine_n[2]),
        .din1   (ff_buf_out_fine[1]),
        .din2   (ff_buf_out_fine[0])
        );

//assign fine_sel[1] = ~ff_buf_out_fine[2]  &  ~ff_buf_out_fine[1]  &  ~ff_buf_out_fine[0];


n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_fine_sel_1 
        (
        .dout   (fine_sel[1]),
        .din0   (ff_buf_out_fine_n[2]),
        .din1   (ff_buf_out_fine_n[1]),
        .din2   (ff_buf_out_fine_n[0])
        );

//assign fine_sel[0] = ~ff_buf_out_fine[2]  &  ~ff_buf_out_fine[1]  &  ff_buf_out_fine[0];


n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 and_fine_sel_0 
        (
        .dout   (fine_sel[0]),
        .din0   (ff_buf_out_fine_n[2]),
        .din1   (ff_buf_out_fine_n[1]),
        .din2   (ff_buf_out_fine[0])
        );


//end of n2_l2d_tstmod_logic

n2_l2d_tstmod_delay_cust  tstmod_delay	// NOT ATPGABLE
       (
       .l1clk           (l1clk),
       .tstmod_rst_l    (tstmod_rst_l),
       .tst_bnken31_setb(tst_bnken31_setb),
       .tst_bnken02_setb(tst_bnken02_setb),
       .tst_bnken31_rstb(tst_bnken31_rstb),
       .tst_bnken02_rstb(tst_bnken02_rstb),
       .corse_sel       (corse_sel[5:0]),
       .fine_sel        (fine_sel[7:0]),
       .delout31_lft    (delout31_lft),
       .delout31_rgt    (delout31_rgt),
       .delout20_lft    (delout20_lft),
       .delout20_rgt    (delout20_rgt)
       );
       
       
// scanorder start
//msff_read_c4_scanin[1:0]
//msff_buf_out_top_scanin
//msff_buf_out_corse_scanin[0]
//msff_buf_out_corse_scanin[1]
//msff_buf_out_corse_scanin[2]
//msff_buf_out_fine_scanin[0]
//msff_buf_out_fine_scanin[1]
//msff_buf_out_fine_scanin[2]
//msff_buf_out_bot_scanin
// scanorder end281     // fixscan start
assign msff_read_c4_scanin[1]=si;
assign msff_read_c4_scanin[0]=msff_read_c4_scanout[1];
assign msff_buf_out_top_scanin=msff_read_c4_scanout[0];
assign msff_buf_out_corse_scanin[0]=msff_buf_out_top_scanout;
assign msff_buf_out_corse_scanin[1]=msff_buf_out_corse_scanout[0];
assign msff_buf_out_corse_scanin[2]=msff_buf_out_corse_scanout[1];
assign msff_buf_out_fine_scanin[0]=msff_buf_out_corse_scanout[2];
assign msff_buf_out_fine_scanin[1]=msff_buf_out_fine_scanout[0];
assign msff_buf_out_fine_scanin[2]=msff_buf_out_fine_scanout[1];
assign msff_buf_out_bot_scanin=msff_buf_out_fine_scanout[2];
assign so=msff_buf_out_bot_scanout;
// fixscan end
endmodule // main program

//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
//////////////////////////////////////////////
// THE FOLLOWING MODULE IS BLACKBOX TO ATPG
//////////////////////////////////////////////

module n2_l2d_tstmod_delay_cust (
  l1clk, 
  tstmod_rst_l, 
  tst_bnken31_setb, 
  tst_bnken02_setb, 
  tst_bnken31_rstb, 
  tst_bnken02_rstb, 
  corse_sel, 
  fine_sel, 
  delout31_lft, 
  delout31_rgt, 
  delout20_lft, 
  delout20_rgt) ;

input   l1clk;   
input   tstmod_rst_l;   
input   tst_bnken31_setb;   
input   tst_bnken02_setb;   
input   tst_bnken31_rstb;   
input   tst_bnken02_rstb;   
input   [5:0] corse_sel;   
input   [7:0] fine_sel;   

output   delout31_lft;   
output   delout31_rgt;   
output   delout20_lft;   
output   delout20_rgt;   

wire    [5:0]   corse_sel_muxout;
wire    [7:1]   fine_sel_muxout;

wire 		delayline_en_31;
wire 		delayline_en_02;
wire 		fine_dout_31;
wire 		fine_dout_02;

assign corse_sel_muxout[5:0] = ( {1'b0,corse_sel_muxout[5:1]}  &  {~({5{tstmod_rst_l}} & corse_sel[5:1]),(tstmod_rst_l & ~corse_sel[0])}) | 
                               ({6{l1clk}}  &  {{{5{tstmod_rst_l}} & corse_sel[5:1]},(~(tstmod_rst_l & ~corse_sel[0])) & tstmod_rst_l});

//  
//assign fine_sel_muxout[7:1] = ( ({corse_sel_muxout[0],fine_sel_muxout[7:2]})  &  (~fine_sel[7:1]) )
// | ({&{corse_sel_muxout[0]}}  &  fine_sel[7:1]);


assign fine_sel_muxout[7:1] = ( ({corse_sel_muxout[0],fine_sel_muxout[7:2]})  &  (~fine_sel[7:1]) ) |
({7{corse_sel_muxout[0]}}  &  fine_sel[7:1]);


srlatch1	latch1_31
	(
	.setl (~(l1clk & tstmod_rst_l  &  tst_bnken31_setb)),
	.rstl1 (tstmod_rst_l),
	.rstl2 (l1clk|~tst_bnken31_rstb),
	.out (delayline_en_31)
	);

srlatch1	latch1_02
	(
	.setl (~(l1clk & tstmod_rst_l  &  tst_bnken02_setb)),
	.rstl1 (tstmod_rst_l),
	.rstl2 (l1clk|~tst_bnken02_rstb),
	.out (delayline_en_02)
	);

srlatch2	latch2_31
	(
	.setl1 (~(fine_sel_muxout[1] & delayline_en_31 & ~fine_sel[0])),
	.setl2 (~(corse_sel_muxout[0] & delayline_en_31 & fine_sel[0])),
	.rstl (delayline_en_31),
	.out (fine_dout_31)
	);

srlatch2	latch2_02
	(
	.setl1 (~(fine_sel_muxout[1] & delayline_en_02 & ~fine_sel[0])),
	.setl2 (~(corse_sel_muxout[0] & delayline_en_02 & fine_sel[0])),
	.rstl (delayline_en_02),
	.out (fine_dout_02)
	);

assign delout31_lft = ~fine_dout_31;
assign delout31_rgt = ~fine_dout_31;
assign delout20_lft = ~fine_dout_02;
assign delout20_rgt = ~fine_dout_02;
endmodule  //n2_l2d_tstmod_delay_cust


module srlatch1 (
  setl, 
  rstl1, 
  rstl2, 
  out) ;

  input setl;
  input rstl1;
  input rstl2;
  output out;

reg out;

        always @(setl or rstl1 or rstl2) 
        begin
           if(~setl)  out   =  1'b1;
           else if( ~(rstl1 & rstl2) )  out   =  1'b0;
        end
endmodule // srlatch1


module srlatch2 (
  setl1, 
  setl2, 
  rstl, 
  out) ;

  input setl1;
  input setl2;
  input rstl;
  output out;

reg out;

        always @(setl1 or setl2 or rstl) begin
          if( (setl1==0) || (setl2==0))  out   =  1'b1;
          else if(~rstl)  out   =  1'b0;
        end
endmodule // srlatch2


//  
//   and macro for ports = 2,3,4
//
//


module n2_l2d_sp_512kb_cust_and_macro__ports_3__width_1 (
  din0, 
  din1, 
  din2, 
  dout);
  input [0:0] din0;
  input [0:0] din1;
  input [0:0] din2;
  output [0:0] dout;


and3 #(1)  d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.in2(din2[0:0]),
.out(dout[0:0])
);


endmodule


//
//   macro for cl_mc1_tisram_blb_{8,4}x flops
//
//


module n2_l2d_sp_512kb_cust_tisram_blb_macro__dmsff_4x__width_1 (
  d_a, 
  l1clk, 
  q_b);
input [0:0] d_a;
input l1clk;
output [0:0] q_b;


tisram_blb #(1)  d0_0 (
.d(d_a[0:0]),
.l1clk(l1clk),
.latout_l(q_b[0:0])
);


//place::generic_place($width,$stack,$left);

endmodule


// any PARAMS parms go into naming of macro

module n2_l2d_sp_512kb_cust_msff_ctl_macro__fs_1__width_3 (
  din, 
  l1clk, 
  scan_in, 
  siclk, 
  soclk, 
  dout, 
  scan_out);
wire [2:0] fdin;

  input [2:0] din;
  input l1clk;
  input [2:0] scan_in;


  input siclk;
  input soclk;

  output [2:0] dout;
  output [2:0] scan_out;
assign fdin[2:0] = din[2:0];


dff #(3)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[2:0]),
.si(scan_in[2:0]),
.so(scan_out[2:0]),
.q(dout[2:0])
);


endmodule


//
//   invert macro
//
//


module n2_l2d_sp_512kb_cust_inv_macro__width_3 (
  din, 
  dout);
  input [2:0] din;
  output [2:0] dout;


inv #(3)  d0_0 (
.in(din[2:0]),
.out(dout[2:0])
);


endmodule


/* ******************************************** 

TRUTH TABLE FOR CLK OUTPUT

div_en	div_bypass 	div_r	div_f 	cclk	
=========================================
0       0           1        0      gclk	
1       0           div_ph   1      div_ph	
x       1           1        0      gclk

******************************************** */


module n2_clk_clstr_hdr_cust (
	gclk,
	l2clk,
	cluster_arst_l,
	ccu_div_ph,
	cluster_div_en,	
	tcu_div_bypass,
	scan_in,
	scan_en,
	tcu_aclk,
	tcu_bclk,
	ccu_cmp_slow_sync_en,
	ccu_slow_cmp_sync_en,
	tcu_pce_ov,
	tcu_clk_stop,
	rst_por_,
	rst_wmr_,
	rst_wmr_protect,
	tcu_wr_inhibit,
	tcu_atpg_mode,
	array_wr_inhibit,
	aclk_wmr,
	aclk,
	bclk,
	cmp_slow_sync_en,
	slow_cmp_sync_en,
	pce_ov,
	por_,
	wmr_,
	wmr_protect,
	scan_out,
	cclk
);

// *******************************
// port declaration
// *******************************
 
input gclk;
input l2clk;
input cluster_arst_l; 
input ccu_div_ph;
input cluster_div_en;	
input tcu_div_bypass;
input scan_in;
input scan_en;
input tcu_aclk;
input tcu_bclk;
input ccu_cmp_slow_sync_en;
input ccu_slow_cmp_sync_en;
input tcu_pce_ov;
input tcu_clk_stop;
input rst_por_;
input rst_wmr_;
input rst_wmr_protect;
input tcu_wr_inhibit;	
input tcu_atpg_mode;			
output array_wr_inhibit;	
output aclk_wmr;
output aclk;
output bclk;
output cmp_slow_sync_en;
output slow_cmp_sync_en;
output pce_ov;
output por_;
output wmr_;
output wmr_protect;
output scan_out;
output cclk;


// *******************************
// wire declaration
// *******************************
 
wire gclk;
wire l2clk;
wire cluster_arst_l; 
wire ccu_div_ph;
wire cluster_div_en;	
wire tcu_div_bypass;
wire scan_in;
wire scan_en;
wire tcu_aclk;
wire tcu_bclk;
wire ccu_cmp_slow_sync_en;
wire ccu_slow_cmp_sync_en;
wire tcu_pce_ov;
wire tcu_clk_stop;
wire rst_por_;
wire rst_wmr_;
wire rst_wmr_protect;
wire tcu_wr_inhibit;	// to be made input
wire tcu_atpg_mode;			// to be made input
wire array_wr_inhibit;	// to be made output
wire aclk_wmr;
wire aclk;
wire bclk;
wire cmp_slow_sync_en;
wire slow_cmp_sync_en;
wire pce_ov;
wire por_;
wire wmr_;
wire wmr_protect;
wire scan_out;
wire cclk;


// additional internal nets 
wire div_r;
// wire div_f; // vlint

wire cluster_div_en_n;
wire tcu_div_bypass_n; 


wire sel0;
wire sel1;
// wire sel2; // vlint

wire div_out;
// wire div_r_n; // vlint
// wire div_f_n; // vlint

// wire gclk_n; // vlint
wire array_wr_inhibit_n;	


wire cclk_n;
wire pre_cclk;
wire div_clk;

wire l1clk;
wire l1gclk;

wire aclk_gated;
wire bclk_gated;
wire scan_en_gated;
wire scan_out_pre_mux;

wire aclk_gated_n;
wire bclk_gated_n;
wire scan_en_gated_n;
wire tcu_atpg_mode_n;

wire scan_ch;

// wire clk_stop_muxed; // vlint
// wire clk_stop_q; // vlint
wire clk_stop_synced;

wire rst_wmr_protect_n;
wire aclk_wmr_n;
wire div_r_sync;
wire sel0_n;
wire sel1_n;
wire div_ph_blatch;
wire div_r_sync_n;
wire div_mux;

// **********************************************************
// buffered & gated stuff 
// **********************************************************

cl_u1_buf_1x aclk_buf ( .in( tcu_aclk ), .out ( aclk ) );
cl_u1_buf_1x bclk_buf ( .in( tcu_bclk ), .out ( bclk ) );
cl_u1_buf_1x pce_ov_buf ( .in( tcu_pce_ov ), .out ( pce_ov ) );
cl_u1_buf_1x wmr_protect_buf ( .in( rst_wmr_protect ), .out ( wmr_protect ) );

// assign aclk_gated = aclk & tcu_atpg_mode;
// assign bclk_gated = bclk & tcu_atpg_mode;
// assign scan_en_gated = scan_en & tcu_atpg_mode;
// implemented right here
cl_u1_nand2_1x aclk_gated_nand ( .in0 (aclk), .in1 (tcu_atpg_mode), .out (aclk_gated_n) );
cl_u1_nand2_1x bclk_gated_nand ( .in0 (bclk), .in1 (tcu_atpg_mode), .out (bclk_gated_n) );
cl_u1_nand2_1x scan_en_gated_nand ( .in0 (scan_en), .in1 (tcu_atpg_mode), .out (scan_en_gated_n) );
cl_u1_inv_1x   aclk_gated_inv  ( .in (aclk_gated_n), .out (aclk_gated) );
cl_u1_inv_1x   bclk_gated_inv  ( .in (bclk_gated_n), .out (bclk_gated) );
cl_u1_inv_1x   scan_en_gated_inv  ( .in (scan_en_gated_n), .out (scan_en_gated) );

// assign scan_out = tcu_atpg_mode ? scan_out_pre_mux : scan_in ;	
// implemented below, and as instance "scan_chain_mux"
cl_u1_inv_1x tcu_atpg_mode_inv ( .in (tcu_atpg_mode) , .out (tcu_atpg_mode_n) );


// assign aclk_wmr = ~rst_wmr_protect & tcu_aclk; 


cl_u1_inv_1x wmr_protect_inv ( .in (rst_wmr_protect) , .out (rst_wmr_protect_n) );

cl_u1_nand2_1x aclk_wmr_gate ( 
	.in0 (aclk), 
	.in1 (rst_wmr_protect_n),
	.out (aclk_wmr_n) 
);

cl_u1_inv_1x aclk_wmr_inv ( .in (aclk_wmr_n) , .out (aclk_wmr) );

// cl_u1_inv_1x gclk_inv ( .in (gclk) , .out (gclk_n) );	// vlint

// **********************************************************
// l1hdr for scan 
// **********************************************************

n2_clk_clstr_hdr_l1hdr gclk_header (
    .l2clk(gclk),
    .l1clk(l1gclk),
    .pce(1'b1),
    .se(scan_en_gated),
    .pce_ov(1'b1),
    .stop(1'b0) // ECO1.2 - not allowed to stop local clocks
);

n2_clk_clstr_hdr_l1hdr l1_header (
    .l2clk(l2clk),
    .l1clk(l1clk),
    .pce(1'b1),
    .se(scan_en_gated),
    .pce_ov(1'b1),
    .stop(1'b0) // ECO1.3 - false info; no action needed
);

// **********************************************************
// make observe flops part of scan chain (observe only)
// **********************************************************

n2_clk_clstr_hdr_obs_flops observe_flops (
	.tcu_clk_stop (tcu_clk_stop),
	.ccu_div_ph (ccu_div_ph),
	.array_wr_inhibit (array_wr_inhibit), 
	.l1clk (l1gclk),
	.aclk (aclk_gated),
	.bclk (bclk_gated),
	.scan_in (scan_in),
	.scan_out (scan_ch)
);

cl_sc1_aomux2_1x scan_chain_mux (
	.sel0 ( tcu_atpg_mode ),
	.sel1 ( tcu_atpg_mode_n ),
	.in0 ( scan_out_pre_mux ),
	.in1 ( scan_in ),
	.out ( scan_out )
);


// **********************************************************
// synchronize the control signals 
// **********************************************************

n2_clk_clstr_hdr_sync control_sig_sync ( 
	.div_r ( div_r_sync ),
	.gclk ( l1gclk ),
	.l1clk ( l1clk ),
	.ccu_slow_cmp_sync_en ( ccu_slow_cmp_sync_en),
	.ccu_cmp_slow_sync_en ( ccu_cmp_slow_sync_en),
	.rst_por_ ( rst_por_),
	.rst_wmr_ ( rst_wmr_),
	.scan_in ( scan_ch ),
	.aclk ( aclk_gated ),
	.bclk ( bclk_gated ),
	.slow_cmp_sync_en ( slow_cmp_sync_en ),
	.cmp_slow_sync_en ( cmp_slow_sync_en ),
	.por_ ( por_ ),
	.wmr_ ( wmr_ ),
	.scan_out ( scan_out_pre_mux )
);


// **********************************************************
// divider & mux model
// **********************************************************

wire ccu_div_ph_ff;
wire ccu_div_ph_flop_unused; 

// first flop ccu_div_ph
cl_sc1_msff_1x ccu_div_ph_flop ( 
	.d ( ccu_div_ph ), 
	.l1clk ( gclk ), 
	.si ( 1'b0 ), 
	.siclk ( 1'b0 ), 
	.soclk ( 1'b0 ), 
	.q ( ccu_div_ph_ff ), 
	.so (ccu_div_ph_flop_unused) 
); 

// div_r = sel1 (ie, ~div_en | tcu_div_bypass ) | div_ph 	
// div_f = sel0 (ie, div_en & ~tcu_div_bypass )
//

// sel0 = ~div_bypass & div_en 		// div_ph select 
// sel1 = div_bypass | ~div_en 		// gclk select

cl_u1_inv_1x  div_bypass_inv ( .in (tcu_div_bypass), .out (tcu_div_bypass_n) );
cl_u1_inv_1x  cluster_div_inv ( .in (cluster_div_en), .out (cluster_div_en_n) );

//
// generate sel0 - div_ph sel 
// 

cl_u1_nand2_1x sel0_n_gen (
	.in0 (tcu_div_bypass_n),
	.in1 (cluster_div_en),
	.out (sel0_n)
);

cl_u1_inv_1x sel0_gen ( .in (sel0_n), .out (sel0) ); 


//
// generate sel1 - gclk sel 
//

cl_u1_nor2_1x sel2_n_gen (
	.in0 (cluster_div_en_n),
	.in1 (tcu_div_bypass),
	.out (sel1_n)
);

cl_u1_inv_1x sel1_gen ( .in (sel1_n), .out (sel1) ); 


// gate off div_r  
//cl_u1_nor2_1x div_r_gate ( 
//	.in0 (sel1),
//	.in1 (div_ph_blatch),
//	.out (div_r_n)
//);
wire blatch_divr_unused;
cl_sc1_blatch_4x blatch_divr (
        .latout(div_ph_blatch), .d(ccu_div_ph_ff), .l1clk (gclk),
        .so (blatch_divr_unused),  .si (1'b0), .siclk(1'b0), .soclk(1'b0) );

//cl_u1_nor2_1x div_r_gate ( 
//	.in0 (sel1),
//	.in1 (div_ph_blatch),
//	.out (div_r_n)
//);

cl_u1_buf_1x div_r_buf ( .in (div_ph_blatch), .out (div_r ) );


//
// divider model  
// 

// creating the div_r_to_syncronizer to mimic generation of
//div_r in schematic.

cl_u1_nor2_1x div_r_sync_gen_nor ( 
	.in0 (sel0_n),
	.in1 (ccu_div_ph_ff),
	.out (div_r_sync_n)
);

cl_u1_inv_1x div_r_sync_gen_inv ( .in (div_r_sync_n), .out (div_r_sync) );

cl_sc1_aomux2_1x alatch_in (
	.sel0 (~sel1 ),
	.sel1 ( sel1 ),
	.in0 ( div_r ),
	.in1 ( div_clk ),
	.out ( div_mux )
);

wire gclk_reset;
wire gclk_reset_n;
cl_u1_nor2_1x  nor_gclk_reset ( .in0 (sel1), .in1 (gclk), .out (gclk_reset_n));
cl_u1_inv_1x  inv_gclk_reset ( .in (gclk_reset_n), .out (gclk_reset));


wire alatch_unused;  
cl_sc1_alatch_4x alatch (
        .q(div_out), .d(div_mux), .l1clk (gclk_reset),
        .so (alatch_unused),  .si (1'b0), .siclk(1'b0), .soclk(1'b0), .se(1'b0) );

// muxed clock out 
cl_sc1_aomux2_1x final_mux (
	.sel0 ( sel0 ),
	.sel1 ( sel1 ),
	.in0 ( div_out ),
	.in1 ( gclk ),
	.out ( div_clk )
);

// **********************************************************
// clkstop for l2clk (via control of cclk) 
// **********************************************************

// 1. sync up clock stop (these are non-scanned)
n2_clk_clstr_hdr_clk_stop_syncff  clk_stop_syncff (
	.din ( tcu_clk_stop ),
	.synced ( clk_stop_synced ), 
	.clkin ( gclk ),
	.sync_clk ( div_clk ),
	.sel ( div_r_sync )

);

wire clk_stop_synced_stg1;
wire clk_stop_synced_stg2;
wire clk_stop_del_stg1_unused;  
wire clk_stop_del_stg2_unused;  
// 2. now delay sync'd up clock stop (these are non-scanned)
cl_sc1_msff_1x clk_stop_del_stg1  (
	.d (clk_stop_synced), .q (clk_stop_synced_stg1), .l1clk (div_clk),
	.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg1_unused)
);

cl_sc1_msff_1x clk_stop_del_stg2  (
	.d (clk_stop_synced_stg1), .q (clk_stop_synced_stg2), .l1clk (div_clk),
	.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg2_unused)
);

wire clk_stop_synced_stg2_gated;
wire clk_stop_synced_stg2_n;

cl_u1_inv_1x   clk_stop_stg2_inv ( .in (clk_stop_synced_stg2), .out (clk_stop_synced_stg2_n) );

// ECO1.5 - pushed the gate after the latch in the clk-stop instance "clk_stopper" 
// cl_u1_nor2_1x  clk_stop_stg2_nor ( .in0 (clk_stop_synced_stg2_n), .in1 (tcu_atpg_mode), .out (clk_stop_synced_stg2_gated) );
//
// 3. use blatch & and-gate for controlling clock
n2_clk_clstr_hdr_clkgate clk_stopper (
    .l2clk(div_clk),
    .l1clk(pre_cclk),
    .atpg_mode(tcu_atpg_mode),
    .clken(clk_stop_synced_stg2_n) 
);

// 4. finally gate-off with async reset 
// assign cclk = pre_cclk & cluster_arst_l; 
 
cl_u1_nand2_1x cclk_nand ( .in0 (pre_cclk), .in1 (cluster_arst_l), .out (cclk_n) );
cl_u1_inv_1x   cclk_inv  ( .in (cclk_n), .out (cclk) ); 


// **********************************************************
// array write inhibit operation 
// **********************************************************

wire clk_stop_synced_n; 

wire clk_stop_synced_stg3;
wire clk_stop_synced_stg4;
wire clk_stop_synced_stg5;
 
wire array_wr_inhibit1;
wire array_wr_inhibit2;

wire array_wr_inhibit1_n;
wire array_wr_inhibit2_n;
wire cluster_arst;
wire clk_stop_del_stg3_unused;
wire clk_stop_del_stg4_unused;
wire clk_stop_del_stg5_unused; 

cl_sc1_msff_1x clk_stop_del_stg3  (
	.d (clk_stop_synced_stg2), .q (clk_stop_synced_stg3), .l1clk (div_clk),
	.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg3_unused)
);

cl_sc1_msff_1x clk_stop_del_stg4  (
	.d (clk_stop_synced_stg3), .q (clk_stop_synced_stg4), .l1clk (div_clk),
	.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg4_unused)
);

cl_sc1_msff_1x clk_stop_del_stg5  (
	.d (clk_stop_synced_stg4), .q (clk_stop_synced_stg5), .l1clk (div_clk),
	.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg5_unused)
);


// assign array_wr_inhibit1 = clk_stop_synced & clk_stop_synced_stg5;

cl_u1_nand3_1x clk_stop_and_delayed ( // ECO1.4 - changed cl_u1_nand2_1x 
	.in0 (clk_stop_synced),
	.in1 (clk_stop_synced_stg5),
	.in2 (tcu_atpg_mode_n),
	.out (array_wr_inhibit1_n)
); 

cl_u1_inv_1x array_wr_inhibit1_inv ( .in(array_wr_inhibit1_n), .out(array_wr_inhibit1) );


// assign array_wr_inhibit2 = (~clk_stop_synced) & wr_inhibit_q2;
cl_u1_inv_1x clk_stop_synced_inv ( .in(clk_stop_synced), .out(clk_stop_synced_n) );

// ECO1.1 - removed nand gate from path of tcu_wr_inhibit
//          and replaced with buffer 
// 
// cl_u1_nand2_1x clk_stop_synced_and_wr_inhibit_q2 (
// 	.in0 (clk_stop_synced_n),
// 	.in1 (tcu_wr_inhibit), // (wr_inhibit_q2),
// 	.out (array_wr_inhibit2_n)
// ); 
//
// cl_u1_inv_1x array_wr_inhibit2_inv ( .in(array_wr_inhibit2_n), .out(array_wr_inhibit2) );
cl_u1_buf_1x array_wr_inhibit2_buf ( .in(tcu_wr_inhibit), .out(array_wr_inhibit2) );


// assign array_wr_inhibit  = array_wr_inhibit1 |  array_wr_inhibit2 | (~cluster_arst_l); 

cl_u1_inv_1x cluster_arst_inv (.in (cluster_arst_l), .out (cluster_arst));

cl_u1_nor3_1x array_wr_inhibit_nor (
	.in0 (array_wr_inhibit1),
	.in1 (array_wr_inhibit2),
	.in2 (cluster_arst),
	.out (array_wr_inhibit_n)
); 

cl_u1_inv_1x array_wr_inhibit_inv (.in (array_wr_inhibit_n), .out (array_wr_inhibit));

endmodule // n2_clk_clstr_hdr_cust 


// **********************************************************
// (fictitous) observe flop module for ATPG purposes 
// **********************************************************

module n2_clk_clstr_hdr_obs_flops (
	tcu_clk_stop,
	ccu_div_ph,
	array_wr_inhibit, 
	l1clk, 
	aclk,
	bclk,
	scan_in,
	scan_out
);

input tcu_clk_stop;
input ccu_div_ph;
input array_wr_inhibit; 
input l1clk;
input aclk;
input bclk;
input scan_in;
output scan_out;

wire tcu_clk_stop;
wire ccu_div_ph;
wire array_wr_inhibit; 
wire l1clk; 
wire aclk;
wire bclk;
wire scan_in;
wire scan_out;

wire scan_ch1;
wire scan_ch2;
wire obs_ff1_unused; 
wire obs_ff2_unused; 
wire obs_ff3_unused; 

cl_sc1_msff_1x obs_ff1 ( 
	.d ( tcu_clk_stop ), 
	.l1clk ( l1clk ), 
	.si ( scan_in ), 
	.siclk ( aclk ), 
	.soclk ( bclk ), 
	.q (obs_ff1_unused ), 
	.so ( scan_ch1 )
); 

cl_sc1_msff_1x obs_ff2 ( 
	.d ( ccu_div_ph ), 
	.l1clk ( l1clk ), 
	.si ( scan_ch1 ), 
	.siclk ( aclk ), 
	.soclk ( bclk ), 
	.q (obs_ff2_unused ), 
	.so ( scan_ch2 )
);

cl_sc1_msff_1x obs_ff3 ( 
	.d ( array_wr_inhibit ), 
	.l1clk ( l1clk ), 
	.si ( scan_ch2 ), 
	.siclk ( aclk ), 
	.soclk ( bclk ), 
	.q (obs_ff3_unused ), 
	.so ( scan_out )
);
endmodule // n2_clk_clstr_hdr_obs_flops 


// **********************************************************
// (fictitous) synchronizer module for ATPG purposes 
// **********************************************************

module n2_clk_clstr_hdr_sync ( 
	div_r,
	gclk,
	l1clk,
	ccu_slow_cmp_sync_en ,
	ccu_cmp_slow_sync_en ,
	rst_por_ ,
	rst_wmr_ ,
	scan_in,
	aclk,
	bclk,
	slow_cmp_sync_en,
	cmp_slow_sync_en,
	por_,
	wmr_,
	scan_out
);


input div_r;
input gclk;
input l1clk;
input ccu_slow_cmp_sync_en ;
input ccu_cmp_slow_sync_en ;
input rst_por_ ;
input rst_wmr_ ;
input scan_in;
input aclk;
input bclk;

output slow_cmp_sync_en;
output cmp_slow_sync_en;
output por_;
output wmr_;
output scan_out;

wire div_r;
// wire div_r_n; // vlint
wire gclk;
// wire gclk_n; // vlint
wire l1clk;

wire ccu_slow_cmp_sync_en ;
wire slow_cmp_sync_en;
wire ccu_cmp_slow_sync_en ;
wire cmp_slow_sync_en;
wire rst_por_ ;
wire por_;

wire rst_wmr_ ;
wire wmr_;

wire scan_in;
wire scan_out;
wire aclk;
wire bclk;

wire scan_ch1;
wire scan_ch2;
wire scan_ch3;


// slow_cmp_sync_en 
n2_clk_clstr_hdr_sync_ff  slow_cmp_sync_en_syncff (
	.din ( ccu_slow_cmp_sync_en ),
	.synced ( slow_cmp_sync_en ), 
	.clkin ( gclk ),
	.sync_clk ( l1clk ),
	.sel ( div_r ),
	.siclk ( aclk ),
	.soclk ( bclk ),
	.si ( scan_in ), 
	.so ( scan_ch1 )
);

// cmp_slow_sync_en 
n2_clk_clstr_hdr_sync_ff  cmp_slow_sync_en_syncff (
	.din ( ccu_cmp_slow_sync_en ),
	.synced ( cmp_slow_sync_en ), 
	.clkin ( gclk ),
	.sync_clk ( l1clk ),
	.sel ( div_r ),
	.siclk ( aclk ),
	.soclk ( bclk ),
	.si ( scan_ch1 ), 
	.so ( scan_ch2 )
);

// por_  
n2_clk_clstr_hdr_sync_ff  por_syncff (
	.din ( rst_por_ ),
	.synced ( por_ ), 
	.clkin ( gclk ),
	.sync_clk ( l1clk ),
	.sel ( div_r ),
	.siclk ( aclk ),
	.soclk ( bclk ),
	.si ( scan_ch2 ), 
	.so ( scan_ch3 )
);

// wmr_  
n2_clk_clstr_hdr_sync_ff  wmr_syncff (
	.din ( rst_wmr_ ),
	.synced ( wmr_ ), 
	.clkin ( gclk ),
	.sync_clk ( l1clk ),
	.sel ( div_r ),
	.siclk ( aclk ),
	.soclk ( bclk ),
	.si ( scan_ch3 ), 
	.so ( scan_out )
);

endmodule // n2_clk_clstr_hdr_sync 


// **********************************************************
// (fictitous) 1-bit synchronizer for ATPG purposes 
// **********************************************************

module n2_clk_clstr_hdr_sync_ff ( 
	din,
	synced,
	clkin,
	sync_clk,
	sel,
	siclk,
	soclk,
	si,
	so
);

input din;
output synced;
input clkin;
input sync_clk;
input siclk;
input soclk;
input si;
output so;
input sel;

wire din;
wire synced;
wire clkin;
wire sync_clk;
wire siclk;
wire soclk;
wire si;
wire so;
wire sel;

wire so_tmp;
wire sel_n;
wire din_q1;
wire din_muxed;

cl_u1_inv_1x sel_inv ( .in ( sel ), .out ( sel_n ) );

cl_sc1_aomux2_1x sync_mux1 (
	.sel0 ( sel_n ),
	.sel1 ( sel ),
	.in0 ( din_q1 ), 
	.in1 ( din ),
	.out ( din_muxed ) 
);

cl_sc1_msff_1x din_stg1 ( 
	.d ( din_muxed ), 
	.l1clk ( clkin ), 
	.si ( si ), 
	.siclk ( siclk ), 
	.soclk ( soclk ), 
	.q ( din_q1 ), 
	.so ( so_tmp )
); 
 
cl_sc1_msff_1x din_stg2 ( 
	.d ( din_q1 ), 
	.l1clk ( sync_clk ), 
	.si ( so_tmp ), 
	.siclk ( siclk ), 
	.soclk ( soclk ), 
	.q ( synced ), 
	.so ( so ) 
); 
endmodule // n2_clk_clstr_hdr_sync_ff 


// **********************************************************
// (fictitous)  module for clock stop sync.
// **********************************************************
module n2_clk_clstr_hdr_clk_stop_syncff  (
	din,
	synced,
	clkin,
	sync_clk,
	sel
);

input din;
output synced;
input clkin;
input sync_clk;
input sel;

wire din;
wire synced;
wire clkin;
wire sync_clk;
wire sel;

wire [2:0] so_unused; 

wire sel_n;
wire  din_q1_lat;
wire din_q1;
wire din_muxed;

cl_u1_inv_1x sel_inv ( .in(sel), .out(sel_n) );

cl_sc1_aomux2_1x sync_mux1 (
	.sel0 ( sel_n ), .sel1 ( sel ),
	.in0 ( din_q1 ), .in1 ( din ),
	.out ( din_muxed ) 
);

cl_sc1_msff_1x din_stg1 ( 
	.d ( din_muxed ), .l1clk ( clkin ), .q ( din_q1 ), 
	.si ( 1'b0 ), .siclk ( 1'b0 ), .soclk ( 1'b0 ),
        .so (so_unused[0])); 

cl_sc1_blatch_4x blatch ( 
	.latout(din_q1_lat), .d(din_q1), .l1clk (clkin), 
	.so (so_unused[1]),  .si (1'b0), .siclk(1'b0), .soclk(1'b0) );

cl_sc1_msff_1x din_stg2 ( 
	.d ( din_q1_lat ), .l1clk ( sync_clk ), .q ( synced ), 
	.siclk ( 1'b0 ), .soclk ( 1'b0 ), .si ( 1'b0 ), .so (so_unused[2] ) ); 

endmodule // n2_clk_clstr_hdr_clk_stop_sync_ff  


module  n2_clk_clstr_hdr_clkgate (
	 atpg_mode,
	 clken,
	 l2clk,
	 l1clk
);

input        atpg_mode;
input        clken;          // clken, active high 
input        l2clk;          // level 2 clock, from clock grid
output       l1clk;

wire         atpg_mode, clken, l2clk, l1clk;

wire  clken_gated;
wire  clken_gated_n;
wire  l1clk_n;
wire  clken_lat;
wire  so_unused;

cl_sc1_blatch_4x blatch ( 
	.latout(clken_lat), .d(clken), .l1clk (l2clk), 
	.so (so_unused),  .si (1'b0), .siclk(1'b0), .soclk(1'b0) );

cl_u1_nor2_1x  clken_nor ( .in0(clken_lat), .in1(atpg_mode), .out(clken_gated_n) );
cl_u1_inv_1x   clken_gated_inv ( .in(clken_gated_n), .out(clken_gated) );

cl_u1_nand2_1x clk_nand ( .in0(clken_gated), .in1(l2clk), .out(l1clk_n) );
cl_u1_inv_1x   clk_inv  ( .in(l1clk_n), .out(l1clk) );

endmodule // n2_clk_clstr_hdr_clkgate 

module  n2_clk_clstr_hdr_l1hdr (
                 l2clk,
                 se,
                 pce,
                 pce_ov,
                 stop,
                 l1clk
                );

   input        l2clk;          // level 2 clock, from clock grid
   input        se;             // Scan Enable
   input        pce;             // Clock enable for local power savings
   input        pce_ov;        // TCU sourced clock enable override for testing
   input        stop;           // TCU/CCU sourced clock stop for debug
   output       l1clk;

 reg l1en;

   always @ (l2clk or stop or pce or pce_ov ) begin  // vlint fix - latch model
		if (!l2clk) 
           l1en = (~stop & ( pce | pce_ov ));	 // vlint fix - replaced w/blocking 
   end

   assign       l1clk = (l2clk & l1en) | se;  // se is async and highest priority

endmodule // n2_clk_clstr_hdr_l1hdr 


module n2_clk_l2d_cmp_cust (
	cclk,
	l2clk
);

input 	cclk;
output 	l2clk;

wire	cclk;
wire	l2clk;

assign #1 l2clk = cclk; 
				
endmodule